From e250d185ef3a663f18861a6c3ba00bf85351da45 Mon Sep 17 00:00:00 2001 From: Weisson Date: Thu, 31 Jul 2025 22:00:09 -0400 Subject: [PATCH] Add RISC-V ISA extensions. Signed-off-by: Weisson --- 1001-Add-support-for-_Bfloat16.patch | 727 ++++++ ...box-the-result-of-movbf-on-soft-bf16.patch | 182 ++ 1003-RISC-V-Modify-_Bfloat16-to-__bf16.patch | 208 ++ ...fbfmin-extension-to-the-march-option.patch | 226 ++ ...fbfwma-extension-to-the-march-option.patch | 245 ++ ...rmat-issue-for-trailing-operator-NFC.patch | 89 + ...V-Add-vector-type-of-BFloat16-format.patch | 729 ++++++ ...C-V-Add-md-files-for-vector-BFloat16.patch | 935 +++++++ ...-Add-Zvfbfmin-and-Zvfbfwma-intrinsic.patch | 480 ++++ ...or-vector-single-width-integer-multi.patch | 288 +++ ...-Minimal-support-for-Zimop-extension.patch | 108 + ...lib_os_dir-and-multiarch_dir-for-tho.patch | 195 ++ ...r-RVV-rounding-intrinsic-ICE-in-func.patch | 115 + 1014-RISC-V-Add-Zfbfmin-extension.patch | 371 +++ ...ing-shift-for-scatter-gather-if-appl.patch | 370 +++ ...ISC-V-Introduce-mvector-strict-align.patch | 409 +++ ...isaligned-vector-access-in-hook-risc.patch | 111 + 1018-expr-Export-clear_by_pieces.patch | 64 + ...-V-testsuite-Make-cmo-tests-LTO-safe.patch | 108 + ...dd-memset-zero-expansion-to-cbo.zero.patch | 200 ++ ...e-condition-for-add-additional-vars-.patch | 113 + ...detection-of-store-pair-fusion-cases.patch | 104 + ...-synthesis-for-constants-with-2-bits.patch | 2248 +++++++++++++++++ ...xclusively-Jivan-s-work.-His-origina.patch | 630 +++++ ...-failure-on-rv32-and-formatting-nits.patch | 138 + ...unding-tests-on-newlib-risc-v-target.patch | 51 + 1027-RISC-V-miscll-comment-fixes-NFC.patch | 59 + ...other-constant-synthesis-improvement.patch | 1708 +++++++++++++ 1029-RISC-V-Document-mcmodel-large.patch | 46 + 1030-Enable-inlining-str-by-default.patch | 106 + ...Reassociate-constants-in-logical-ops.patch | 120 + ...ic-patterns-for-zbkb-code-generation.patch | 288 +++ ...OpenMP-Fix-for-ICE-in-tree-nested.cc.patch | 42 + ...eduction_guide-for-invalid-template-.patch | 66 + ...-rv32-issues-with-recent-zicboz-work.patch | 82 + ...ept.cc-on-targets-that-don-t-support.patch | 68 + ...ICE-taking-the-address-of-bound-stat.patch | 77 + 1038-Avoid-ICE-with-pointer-reduction.patch | 39 + ...V-Add-basic-Zaamo-and-Zalrsc-support.patch | 335 +++ ...d-Zalrsc-and-Zaamo-testsuite-support.patch | 626 +++++ 1041-RISC-V-Add-Zalrsc-amo-op-patterns.patch | 378 +++ ...RISC-V-Move-amo-tests-into-subfolder.patch | 648 +++++ 1043-RISC-V-Fix-amoadd-call-arguments.patch | 413 +++ ...-temp-register-to-be-used-in-amo-tes.patch | 232 ++ ...port-for-subword-atomic-loads-stores.patch | 999 ++++++++ ...gure-check-for-Zaamo-Zalrsc-assemble.patch | 147 ++ ...aamo-Zalrsc-to-a-when-using-an-old-b.patch | 42 + ...dd-dg-remove-option-for-z-extensions.patch | 856 +++++++ 1049-RISC-V-Rename-amo-testcases.patch | 318 +++ ...-V-Consolidate-amo-testcase-variants.patch | 1118 ++++++++ ...stcase-comments-to-point-to-PSABI-ra.patch | 548 ++++ ...SC-V-Add-support-for-Zabha-extension.patch | 1001 ++++++++ ...Add-support-for-B-standard-extension.patch | 73 + 1054-RISC-V-Update-testsuite-to-use-b.patch | 81 + ...mplies-zca-and-conditionally-zcf-zcd.patch | 204 ++ ...ment-locality-for-__builtin_prefetch.patch | 124 + ...C-V-Remove-configure-check-for-zabha.patch | 146 ++ ...asic-support-for-the-Zacas-extension.patch | 1564 ++++++++++++ ...figure-check-for-B-extention-support.patch | 140 + 1060-testsuite-fix-dg-compile-typos.patch | 414 +++ ...ot-use-zicond-for-pr105314-testcases.patch | 64 + ...-Minimal-support-for-Zimop-extension.patch | 43 + ...-xtheadfmemidx-Rename-test-and-add-s.patch | 106 + ...nsic-support-for-the-CMOs-extensions.patch | 126 + ...rinsic-cases-for-the-CMOs-extensions.patch | 151 ++ ...SC-V-Add-implication-for-M-extension.patch | 306 +++ ...rror-early-with-V-and-no-M-extension.patch | 116 + ...am-logic-errors-caused-by-data-trunc.patch | 80 + 1069-RISC-V-Add-vector-popcount-clz-ctz.patch | 649 +++++ ...esult-error-caused-by-not-updating-r.patch | 66 + ...RISC-V-Implement-TARGET_CAN_INLINE_P.patch | 548 ++++ 1072-RISC-V-Add-Zicfiss-ISA-extension.patch | 606 +++++ 1073-RISC-V-Add-Zicfilp-ISA-extension.patch | 761 ++++++ ....gnu.property-for-ZICFILP-and-ZICFIS.patch | 249 ++ ...rotection-full-branch-return-to-enab.patch | 414 +++ ...LMUL-when-using-maximum-SEW-PR117955.patch | 264 ++ ...V-Eliminate-latter-vsetvl-when-fused.patch | 82 + ...x-ratio-in-vsetvl-fuse-rule-PR115703.patch | 176 ++ ...le-two-instruction-macc-alternatives.patch | 640 +++++ ...thon3-usage-to-avoid-SyntaxError-wit.patch | 33 + ...validation-for-RVV-fixed-length-vari.patch | 120 + 1082-RISC-V-Fix-ICE-for-amo.patch | 35 + ...-vcpop-intrinsics-for-Zvbb-extension.patch | 85 + ...d-missing-overlaps-for-vector-crypto.patch | 54 + ...Fix-the-wrong-vmul-for-vector-crypto.patch | 87 + ...XuanTie-Add-xt-c930-support-for-mcpu.patch | 192 ++ ...Tie-Add-xt-c930-pipeline-description.patch | 471 ++++ gcc.spec | 183 +- 88 files changed, 29258 insertions(+), 1 deletion(-) create mode 100644 1001-Add-support-for-_Bfloat16.patch create mode 100644 1002-RISC-V-Nan-box-the-result-of-movbf-on-soft-bf16.patch create mode 100644 1003-RISC-V-Modify-_Bfloat16-to-__bf16.patch create mode 100644 1004-RISC-V-Add-Zfbfmin-extension-to-the-march-option.patch create mode 100644 1005-RISC-V-Add-Zvfbfwma-extension-to-the-march-option.patch create mode 100644 1006-RISC-V-Fix-format-issue-for-trailing-operator-NFC.patch create mode 100644 1007-RISC-V-Add-vector-type-of-BFloat16-format.patch create mode 100644 1008-RISC-V-Add-md-files-for-vector-BFloat16.patch create mode 100644 1009-RISC-V-Add-Zvfbfmin-and-Zvfbfwma-intrinsic.patch create mode 100644 1010-RISC-V-Fix-ICE-for-vector-single-width-integer-multi.patch create mode 100644 1011-RISC-V-Minimal-support-for-Zimop-extension.patch create mode 100644 1012-driver-Fix-multilib_os_dir-and-multiarch_dir-for-tho.patch create mode 100644 1013-RISC-V-Bugfix-for-RVV-rounding-intrinsic-ICE-in-func.patch create mode 100644 1014-RISC-V-Add-Zfbfmin-extension.patch create mode 100644 1015-RISC-V-Use-widening-shift-for-scatter-gather-if-appl.patch create mode 100644 1016-RISC-V-Introduce-mvector-strict-align.patch create mode 100644 1017-RISC-V-Disable-misaligned-vector-access-in-hook-risc.patch create mode 100644 1018-expr-Export-clear_by_pieces.patch create mode 100644 1019-RISC-V-testsuite-Make-cmo-tests-LTO-safe.patch create mode 100644 1020-RISC-V-Add-memset-zero-expansion-to-cbo.zero.patch create mode 100644 1021-RISC-V-Refine-the-condition-for-add-additional-vars-.patch create mode 100644 1022-Fix-detection-of-store-pair-fusion-cases.patch create mode 100644 1023-Improve-constant-synthesis-for-constants-with-2-bits.patch create mode 100644 1024-This-is-almost-exclusively-Jivan-s-work.-His-origina.patch create mode 100644 1025-Fix-nearbyint-failure-on-rv32-and-formatting-nits.patch create mode 100644 1026-Don-t-run-new-rounding-tests-on-newlib-risc-v-target.patch create mode 100644 1027-RISC-V-miscll-comment-fixes-NFC.patch create mode 100644 1028-So-another-constant-synthesis-improvement.patch create mode 100644 1029-RISC-V-Document-mcmodel-large.patch create mode 100644 1030-Enable-inlining-str-by-default.patch create mode 100644 1031-Reassociate-constants-in-logical-ops.patch create mode 100644 1032-Some-basic-patterns-for-zbkb-code-generation.patch create mode 100644 1033-OpenMP-Fix-for-ICE-in-tree-nested.cc.patch create mode 100644 1034-c-ICE-in-build_deduction_guide-for-invalid-template-.patch create mode 100644 1035-Fix-rv32-issues-with-recent-zicboz-work.patch create mode 100644 1036-Avoid-ICE-in-except.cc-on-targets-that-don-t-support.patch create mode 100644 1037-Fix-PR-c-109958-ICE-taking-the-address-of-bound-stat.patch create mode 100644 1038-Avoid-ICE-with-pointer-reduction.patch create mode 100644 1039-RISC-V-Add-basic-Zaamo-and-Zalrsc-support.patch create mode 100644 1040-RISC-V-Add-Zalrsc-and-Zaamo-testsuite-support.patch create mode 100644 1041-RISC-V-Add-Zalrsc-amo-op-patterns.patch create mode 100644 1042-RISC-V-Move-amo-tests-into-subfolder.patch create mode 100644 1043-RISC-V-Fix-amoadd-call-arguments.patch create mode 100644 1044-RISC-V-Allow-any-temp-register-to-be-used-in-amo-tes.patch create mode 100644 1045-RISC-V-Add-support-for-subword-atomic-loads-stores.patch create mode 100644 1046-RISC-V-Add-configure-check-for-Zaamo-Zalrsc-assemble.patch create mode 100644 1047-RISC-V-Promote-Zaamo-Zalrsc-to-a-when-using-an-old-b.patch create mode 100644 1048-RISC-V-Add-dg-remove-option-for-z-extensions.patch create mode 100644 1049-RISC-V-Rename-amo-testcases.patch create mode 100644 1050-RISC-V-Consolidate-amo-testcase-variants.patch create mode 100644 1051-RISC-V-Update-testcase-comments-to-point-to-PSABI-ra.patch create mode 100644 1052-RISC-V-Add-support-for-Zabha-extension.patch create mode 100644 1053-RISC-V-Add-support-for-B-standard-extension.patch create mode 100644 1054-RISC-V-Update-testsuite-to-use-b.patch create mode 100644 1055-RISC-V-c-implies-zca-and-conditionally-zcf-zcd.patch create mode 100644 1056-RISC-V-Implement-locality-for-__builtin_prefetch.patch create mode 100644 1057-RISC-V-Remove-configure-check-for-zabha.patch create mode 100644 1058-RISC-V-Add-basic-support-for-the-Zacas-extension.patch create mode 100644 1059-RISC-V-Add-configure-check-for-B-extention-support.patch create mode 100644 1060-testsuite-fix-dg-compile-typos.patch create mode 100644 1061-RISC-V-NFC-Do-not-use-zicond-for-pr105314-testcases.patch create mode 100644 1062-RISC-V-Minimal-support-for-Zimop-extension.patch create mode 100644 1063-RISC-V-testsuite-xtheadfmemidx-Rename-test-and-add-s.patch create mode 100644 1064-RISC-V-Add-intrinsic-support-for-the-CMOs-extensions.patch create mode 100644 1065-RISC-V-Add-intrinsic-cases-for-the-CMOs-extensions.patch create mode 100644 1066-RISC-V-Add-implication-for-M-extension.patch create mode 100644 1067-RISC-V-Error-early-with-V-and-no-M-extension.patch create mode 100644 1068-RISC-V-Fix-program-logic-errors-caused-by-data-trunc.patch create mode 100644 1069-RISC-V-Add-vector-popcount-clz-ctz.patch create mode 100644 1070-RISC-V-Fix-the-result-error-caused-by-not-updating-r.patch create mode 100644 1071-RISC-V-Implement-TARGET_CAN_INLINE_P.patch create mode 100644 1072-RISC-V-Add-Zicfiss-ISA-extension.patch create mode 100644 1073-RISC-V-Add-Zicfilp-ISA-extension.patch create mode 100644 1074-RISC-V-Add-.note.gnu.property-for-ZICFILP-and-ZICFIS.patch create mode 100644 1075-RISC-V-Add-fcf-protection-full-branch-return-to-enab.patch create mode 100644 1076-RISC-V-Adjust-LMUL-when-using-maximum-SEW-PR117955.patch create mode 100644 1077-RISC-V-Eliminate-latter-vsetvl-when-fused.patch create mode 100644 1078-RISC-V-Fix-ratio-in-vsetvl-fuse-rule-PR115703.patch create mode 100644 1079-Drop-undesirable-two-instruction-macc-alternatives.patch create mode 100644 1080-RISC-V-Prefer-Python3-usage-to-avoid-SyntaxError-wit.patch create mode 100644 1081-RISC-V-Fix-type-validation-for-RVV-fixed-length-vari.patch create mode 100644 1082-RISC-V-Fix-ICE-for-amo.patch create mode 100644 1083-RISC-V-Implement-vcpop-intrinsics-for-Zvbb-extension.patch create mode 100644 1084-RISC-V-Add-missing-overlaps-for-vector-crypto.patch create mode 100644 1085-RISC-V-Fix-the-wrong-vmul-for-vector-crypto.patch create mode 100644 1086-RISC-V-XuanTie-Add-xt-c930-support-for-mcpu.patch create mode 100644 1087-RISC-V-XuanTie-Add-xt-c930-pipeline-description.patch diff --git a/1001-Add-support-for-_Bfloat16.patch b/1001-Add-support-for-_Bfloat16.patch new file mode 100644 index 0000000..ed03c77 --- /dev/null +++ b/1001-Add-support-for-_Bfloat16.patch @@ -0,0 +1,727 @@ +From 72b9aa753c3e5f6cb1c7cfdad5e3c814d9ea7959 Mon Sep 17 00:00:00 2001 +From: Xiao Zeng +Date: Mon, 6 May 2024 15:39:12 -0600 +Subject: [PATCH 1001/1087] Add support for _Bfloat16 + +commit 8c7cee80eb50792e57d514be1418c453ddd1073e upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +1 At point , + BF16 has already been completed "post public review". + +2 LLVM has also added support for RISCV BF16 in + and + . + +3 According to the discussion , + this use __bf16 and use DF16b in riscv_mangle_type like x86. + +Below test are passed for this patch + * The riscv fully regression test. + +gcc/ChangeLog: + + * config/riscv/iterators.md: New mode iterator HFBF. + * config/riscv/riscv-builtins.cc (riscv_init_builtin_types): + Initialize data type _Bfloat16. + * config/riscv/riscv-modes.def (FLOAT_MODE): New. + (ADJUST_FLOAT_FORMAT): New. + * config/riscv/riscv.cc (riscv_mangle_type): Support for BFmode. + (riscv_scalar_mode_supported_p): Ditto. + (riscv_libgcc_floating_mode_supported_p): Ditto. + (riscv_init_libfuncs): Set the conversion method for BFmode and + HFmode. + (riscv_block_arith_comp_libfuncs_for_mode): Set the arithmetic + and comparison libfuncs for the mode. + * config/riscv/riscv.md (mode" ): Add BF. + (movhf): Support for BFmode. + (mov): Ditto. + (*movhf_softfloat): Ditto. + (*mov_softfloat): Ditto. + +libgcc/ChangeLog: + + * config/riscv/sfp-machine.h (_FP_NANFRAC_B): New. + (_FP_NANSIGN_B): Ditto. + * config/riscv/t-softfp32: Add support for BF16 libfuncs. + * config/riscv/t-softfp64: Ditto. + * soft-fp/floatsibf.c: For si -> bf16. + * soft-fp/floatunsibf.c: For unsi -> bf16. + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/bf16_arithmetic.c: New test. + * gcc.target/riscv/bf16_call.c: New test. + * gcc.target/riscv/bf16_comparison.c: New test. + * gcc.target/riscv/bf16_float_libcall_convert.c: New test. + * gcc.target/riscv/bf16_integer_libcall_convert.c: New test. + +Co-authored-by: Jin Ma +--- + gcc/config/riscv/iterators.md | 2 + + gcc/config/riscv/riscv-builtins.cc | 16 ++++ + gcc/config/riscv/riscv-modes.def | 3 + + gcc/config/riscv/riscv.cc | 64 ++++++++++----- + gcc/config/riscv/riscv.md | 24 +++--- + .../gcc.target/riscv/bf16_arithmetic.c | 42 ++++++++++ + gcc/testsuite/gcc.target/riscv/bf16_call.c | 12 +++ + .../gcc.target/riscv/bf16_comparison.c | 36 +++++++++ + .../riscv/bf16_float_libcall_convert.c | 57 +++++++++++++ + .../riscv/bf16_integer_libcall_convert.c | 81 +++++++++++++++++++ + libgcc/config/riscv/sfp-machine.h | 3 + + libgcc/config/riscv/t-softfp32 | 10 ++- + libgcc/config/riscv/t-softfp64 | 3 +- + libgcc/soft-fp/floatsibf.c | 45 +++++++++++ + libgcc/soft-fp/floatunsibf.c | 45 +++++++++++ + 15 files changed, 407 insertions(+), 36 deletions(-) + create mode 100644 gcc/testsuite/gcc.target/riscv/bf16_arithmetic.c + create mode 100644 gcc/testsuite/gcc.target/riscv/bf16_call.c + create mode 100644 gcc/testsuite/gcc.target/riscv/bf16_comparison.c + create mode 100644 gcc/testsuite/gcc.target/riscv/bf16_float_libcall_convert.c + create mode 100644 gcc/testsuite/gcc.target/riscv/bf16_integer_libcall_convert.c + create mode 100644 libgcc/soft-fp/floatsibf.c + create mode 100644 libgcc/soft-fp/floatunsibf.c + +diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md +index a7694137685..40bf20f42bb 100644 +--- a/gcc/config/riscv/iterators.md ++++ b/gcc/config/riscv/iterators.md +@@ -75,6 +75,8 @@ + ;; Iterator for floating-point modes that can be loaded into X registers. + (define_mode_iterator SOFTF [SF (DF "TARGET_64BIT") (HF "TARGET_ZFHMIN")]) + ++;; Iterator for floating-point modes of BF16 ++(define_mode_iterator HFBF [HF BF]) + + ;; ------------------------------------------------------------------- + ;; Mode attributes +diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc +index d457e306dd1..4c08834288a 100644 +--- a/gcc/config/riscv/riscv-builtins.cc ++++ b/gcc/config/riscv/riscv-builtins.cc +@@ -230,6 +230,7 @@ static GTY(()) int riscv_builtin_decl_index[NUM_INSN_CODES]; + riscv_builtin_decls[riscv_builtin_decl_index[(CODE)]] + + tree riscv_float16_type_node = NULL_TREE; ++tree riscv_bfloat16_type_node = NULL_TREE; + + /* Return the function type associated with function prototype TYPE. */ + +@@ -273,6 +274,21 @@ riscv_init_builtin_types (void) + if (!maybe_get_identifier ("_Float16")) + lang_hooks.types.register_builtin_type (riscv_float16_type_node, + "_Float16"); ++ ++ /* Provide the _Bfloat16 type and bfloat16_type_node if needed. */ ++ if (!bfloat16_type_node) ++ { ++ riscv_bfloat16_type_node = make_node (REAL_TYPE); ++ TYPE_PRECISION (riscv_bfloat16_type_node) = 16; ++ SET_TYPE_MODE (riscv_bfloat16_type_node, BFmode); ++ layout_type (riscv_bfloat16_type_node); ++ } ++ else ++ riscv_bfloat16_type_node = bfloat16_type_node; ++ ++ if (!maybe_get_identifier ("_Bfloat16")) ++ lang_hooks.types.register_builtin_type (riscv_bfloat16_type_node, ++ "_Bfloat16"); + } + + /* Implement TARGET_INIT_BUILTINS. */ +diff --git a/gcc/config/riscv/riscv-modes.def b/gcc/config/riscv/riscv-modes.def +index bdce89b17aa..6de4e440298 100644 +--- a/gcc/config/riscv/riscv-modes.def ++++ b/gcc/config/riscv/riscv-modes.def +@@ -21,6 +21,9 @@ along with GCC; see the file COPYING3. If not see + + FLOAT_MODE (HF, 2, ieee_half_format); + FLOAT_MODE (TF, 16, ieee_quad_format); ++FLOAT_MODE (BF, 2, 0); ++/* Reuse definition from arm. */ ++ADJUST_FLOAT_FORMAT (BF, &arm_bfloat_half_format); + + /* Vector modes. */ + +diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc +index fe9c8085551..188ae18f2f4 100644 +--- a/gcc/config/riscv/riscv.cc ++++ b/gcc/config/riscv/riscv.cc +@@ -10098,9 +10098,17 @@ riscv_asan_shadow_offset (void) + static const char * + riscv_mangle_type (const_tree type) + { +- /* Half-precision float, _Float16 is "DF16_". */ ++ /* Half-precision float, _Float16 is "DF16_" and _Bfloat16 is "DF16b". */ + if (SCALAR_FLOAT_TYPE_P (type) && TYPE_PRECISION (type) == 16) +- return "DF16_"; ++ { ++ if (TYPE_MODE (type) == HFmode) ++ return "DF16_"; ++ ++ if (TYPE_MODE (type) == BFmode) ++ return "DF16b"; ++ ++ gcc_unreachable (); ++ } + + /* Mangle all vector type for vector extension. */ + /* The mangle name follows the rule of RVV LLVM +@@ -10121,19 +10129,20 @@ riscv_mangle_type (const_tree type) + static bool + riscv_scalar_mode_supported_p (scalar_mode mode) + { +- if (mode == HFmode) ++ if (mode == HFmode || mode == BFmode) + return true; + else + return default_scalar_mode_supported_p (mode); + } + + /* Implement TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P - return TRUE +- if MODE is HFmode, and punt to the generic implementation otherwise. */ ++ if MODE is HFmode or BFmode, and punt to the generic implementation ++ otherwise. */ + + static bool + riscv_libgcc_floating_mode_supported_p (scalar_float_mode mode) + { +- if (mode == HFmode) ++ if (mode == HFmode || mode == BFmode) + return true; + else + return default_libgcc_floating_mode_supported_p (mode); +@@ -10184,27 +10193,42 @@ riscv_floatn_mode (int n, bool extended) + return default_floatn_mode (n, extended); + } + ++/* Record that we have no arithmetic or comparison libfuncs for ++ machine_mode MODE. */ + static void +-riscv_init_libfuncs (void) ++riscv_block_arith_comp_libfuncs_for_mode (machine_mode mode) + { +- /* Half-precision float operations. The compiler handles all operations +- with NULL libfuncs by converting to SFmode. */ ++ /* Half-precision float or Brain float operations. The compiler handles all ++ operations with NULL libfuncs by converting to SFmode. */ + + /* Arithmetic. */ +- set_optab_libfunc (add_optab, HFmode, NULL); +- set_optab_libfunc (sdiv_optab, HFmode, NULL); +- set_optab_libfunc (smul_optab, HFmode, NULL); +- set_optab_libfunc (neg_optab, HFmode, NULL); +- set_optab_libfunc (sub_optab, HFmode, NULL); ++ set_optab_libfunc (add_optab, mode, NULL); ++ set_optab_libfunc (sdiv_optab, mode, NULL); ++ set_optab_libfunc (smul_optab, mode, NULL); ++ set_optab_libfunc (neg_optab, mode, NULL); ++ set_optab_libfunc (sub_optab, mode, NULL); + + /* Comparisons. */ +- set_optab_libfunc (eq_optab, HFmode, NULL); +- set_optab_libfunc (ne_optab, HFmode, NULL); +- set_optab_libfunc (lt_optab, HFmode, NULL); +- set_optab_libfunc (le_optab, HFmode, NULL); +- set_optab_libfunc (ge_optab, HFmode, NULL); +- set_optab_libfunc (gt_optab, HFmode, NULL); +- set_optab_libfunc (unord_optab, HFmode, NULL); ++ set_optab_libfunc (eq_optab, mode, NULL); ++ set_optab_libfunc (ne_optab, mode, NULL); ++ set_optab_libfunc (lt_optab, mode, NULL); ++ set_optab_libfunc (le_optab, mode, NULL); ++ set_optab_libfunc (ge_optab, mode, NULL); ++ set_optab_libfunc (gt_optab, mode, NULL); ++ set_optab_libfunc (unord_optab, mode, NULL); ++} ++ ++static void ++riscv_init_libfuncs (void) ++{ ++ riscv_block_arith_comp_libfuncs_for_mode (HFmode); ++ riscv_block_arith_comp_libfuncs_for_mode (BFmode); ++ ++ /* Convert between BFmode and HFmode using only trunc libfunc if needed. */ ++ set_conv_libfunc (sext_optab, BFmode, HFmode, "__trunchfbf2"); ++ set_conv_libfunc (sext_optab, HFmode, BFmode, "__truncbfhf2"); ++ set_conv_libfunc (trunc_optab, BFmode, HFmode, "__trunchfbf2"); ++ set_conv_libfunc (trunc_optab, HFmode, BFmode, "__truncbfhf2"); + } + + #if CHECKING_P +diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md +index f65d54ceda4..cdbe970cab3 100644 +--- a/gcc/config/riscv/riscv.md ++++ b/gcc/config/riscv/riscv.md +@@ -199,7 +199,7 @@ + (const_string "unknown")) + + ;; Main data type used by the insn +-(define_attr "mode" "unknown,none,QI,HI,SI,DI,TI,HF,SF,DF,TF, ++(define_attr "mode" "unknown,none,QI,HI,SI,DI,TI,HF,BF,SF,DF,TF, + RVVMF64BI,RVVMF32BI,RVVMF16BI,RVVMF8BI,RVVMF4BI,RVVMF2BI,RVVM1BI, + RVVM8QI,RVVM4QI,RVVM2QI,RVVM1QI,RVVMF2QI,RVVMF4QI,RVVMF8QI, + RVVM8HI,RVVM4HI,RVVM2HI,RVVM1HI,RVVMF2HI,RVVMF4HI, +@@ -1875,12 +1875,12 @@ + (set_attr "mode" "DF")]) + + ;; 16-bit floating point moves +-(define_expand "movhf" +- [(set (match_operand:HF 0 "") +- (match_operand:HF 1 ""))] ++(define_expand "mov" ++ [(set (match_operand:HFBF 0 "") ++ (match_operand:HFBF 1 ""))] + "" + { +- if (riscv_legitimize_move (HFmode, operands[0], operands[1])) ++ if (riscv_legitimize_move (mode, operands[0], operands[1])) + DONE; + }) + +@@ -1895,16 +1895,16 @@ + (set_attr "type" "fmove,fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store") + (set_attr "mode" "HF")]) + +-(define_insn "*movhf_softfloat" +- [(set (match_operand:HF 0 "nonimmediate_operand" "=f, r,r,m,*f,*r") +- (match_operand:HF 1 "move_operand" " f,Gr,m,r,*r,*f"))] +- "!TARGET_ZFHMIN +- && (register_operand (operands[0], HFmode) +- || reg_or_0_operand (operands[1], HFmode))" ++(define_insn "*mov_softfloat" ++ [(set (match_operand:HFBF 0 "nonimmediate_operand" "=f, r,r,m,*f,*r") ++ (match_operand:HFBF 1 "move_operand" " f,Gr,m,r,*r,*f"))] ++ "((!TARGET_ZFHMIN && mode == HFmode) || (mode == BFmode)) ++ && (register_operand (operands[0], mode) ++ || reg_or_0_operand (operands[1], mode))" + { return riscv_output_move (operands[0], operands[1]); } + [(set_attr "move_type" "fmove,move,load,store,mtc,mfc") + (set_attr "type" "fmove,move,load,store,mtc,mfc") +- (set_attr "mode" "HF")]) ++ (set_attr "mode" "")]) + + (define_insn "*movhf_softfloat_boxing" + [(set (match_operand:HF 0 "register_operand" "=f") +diff --git a/gcc/testsuite/gcc.target/riscv/bf16_arithmetic.c b/gcc/testsuite/gcc.target/riscv/bf16_arithmetic.c +new file mode 100644 +index 00000000000..9e485051260 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/bf16_arithmetic.c +@@ -0,0 +1,42 @@ ++/* { dg-do compile } */ ++/* { dg-options "-march=rv32i -mabi=ilp32 -O" { target { rv32 } } } */ ++/* { dg-options "-march=rv64i -mabi=lp64 -O" { target { rv64 } } } */ ++ ++/* 1) bf -> sf (call __extendbfsf2) */ ++/* 2) sf1 [+|-|*|/] sf2 (call __[add|sub|mul|div]sf3) */ ++/* 3) sf -> bf (call __truncsfbf2) */ ++extern _Bfloat16 bf; ++extern _Bfloat16 bf1; ++extern _Bfloat16 bf2; ++ ++void bf_add_bf () { bf = bf1 + bf2; } ++ ++void bf_sub_bf () { bf = bf1 - bf2; } ++ ++void bf_mul_bf () { bf = bf1 * bf2; } ++ ++void bf_div_bf () { bf = bf1 / bf2; } ++ ++void bf_add_const () { bf = bf1 + 3.14f; } ++ ++void const_sub_bf () { bf = 3.14f - bf2; } ++ ++void bf_mul_const () { bf = bf1 * 3.14f; } ++ ++void const_div_bf () { bf = 3.14f / bf2; } ++ ++void bf_inc () { ++bf; } ++ ++void bf_dec () { --bf; } ++ ++/* { dg-final { scan-assembler-times "call\t__extendbfsf2" 16 } } */ ++/* { dg-final { scan-assembler-times "call\t__truncsfbf2" 10 } } */ ++/* { dg-final { scan-assembler-times "call\t__addsf3" 3 } } */ ++/* { dg-final { scan-assembler-times "call\t__subsf3" 3 } } */ ++/* { dg-final { scan-assembler-times "call\t__mulsf3" 2 } } */ ++/* { dg-final { scan-assembler-times "call\t__divsf3" 2 } } */ ++ ++/* { dg-final { scan-assembler-not "call\t__addbf3" } } */ ++/* { dg-final { scan-assembler-not "call\t__subbf3" } } */ ++/* { dg-final { scan-assembler-not "call\t__mulbf3" } } */ ++/* { dg-final { scan-assembler-not "call\t__divbf3" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/bf16_call.c b/gcc/testsuite/gcc.target/riscv/bf16_call.c +new file mode 100644 +index 00000000000..29f67719999 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/bf16_call.c +@@ -0,0 +1,12 @@ ++/* { dg-do compile } */ ++/* { dg-options "-march=rv32i -mabi=ilp32 -O" { target { rv32 } } } */ ++/* { dg-options "-march=rv64i -mabi=lp64 -O" { target { rv64 } } } */ ++ ++/* 1) bf -> sf (call __extendbfsf2) */ ++/* 2) sf -> bf (call __truncsfbf2) */ ++__attribute__ ((noinline)) _Bfloat16 add (_Bfloat16 a, _Bfloat16 b) { return a + b; } ++ ++_Bfloat16 test(_Bfloat16 a, _Bfloat16 b) { return add (a, b); } ++ ++/* { dg-final { scan-assembler-times "call\t__extendbfsf2" 2 } } */ ++/* { dg-final { scan-assembler-times "call\t__truncsfbf2" 1 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/bf16_comparison.c b/gcc/testsuite/gcc.target/riscv/bf16_comparison.c +new file mode 100644 +index 00000000000..69db803f403 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/bf16_comparison.c +@@ -0,0 +1,36 @@ ++/* { dg-do compile } */ ++/* { dg-options "-march=rv32i -mabi=ilp32 -O" { target { rv32 } } } */ ++/* { dg-options "-march=rv64i -mabi=lp64 -O" { target { rv64 } } } */ ++ ++/* 1) bf -> sf (call __extendbfsf2) */ ++/* 2) sf1 [<|<=|>|>=|==] sf2 (call __[lt|le|gt|ge|eq]sf2) */ ++extern _Bfloat16 bf; ++extern _Bfloat16 bf1; ++extern _Bfloat16 bf2; ++ ++void bf_lt_bf () { bf = (bf1 < bf2) ? bf1 : bf2; } ++ ++void bf_le_bf () { bf = (bf1 <= bf2) ? bf1 : bf2; } ++ ++void bf_gt_bf () { bf = (bf1 > bf2) ? bf1 : bf2; } ++ ++void bf_ge_bf () { bf = (bf1 >= bf2) ? bf1 : bf2; } ++ ++void bf_eq_bf () { bf = (bf1 == bf2) ? bf1 : bf2; } ++ ++void bf_lt_const () { bf = (bf1 < 3.14f) ? bf1 : bf2; } ++ ++void bf_le_const () { bf = (bf1 <= 3.14f) ? bf1 : bf2; } ++ ++void const_gt_bf () { bf = (3.14f > bf2) ? bf1 : bf2; } ++ ++void const_ge_bf () { bf = (3.14f >= bf2) ? bf1 : bf2; } ++ ++void bf_eq_const () { bf = (bf1 == 3.14f) ? bf1 : bf2; } ++ ++/* { dg-final { scan-assembler-times "call\t__extendbfsf2" 15 } } */ ++/* { dg-final { scan-assembler-not "call\t__ltbf2" } } */ ++/* { dg-final { scan-assembler-not "call\t__lebf2" } } */ ++/* { dg-final { scan-assembler-not "call\t__gtbf2" } } */ ++/* { dg-final { scan-assembler-not "call\t__gebf2" } } */ ++/* { dg-final { scan-assembler-not "call\t__eqbf2" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/bf16_float_libcall_convert.c b/gcc/testsuite/gcc.target/riscv/bf16_float_libcall_convert.c +new file mode 100644 +index 00000000000..ba6c6460bc2 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/bf16_float_libcall_convert.c +@@ -0,0 +1,57 @@ ++/* { dg-do compile } */ ++/* { dg-options "-march=rv32i -mabi=ilp32 -O" { target { rv32 } } } */ ++/* { dg-options "-march=rv64i -mabi=lp64 -O" { target { rv64 } } } */ ++ ++ ++/* 1) float -> BF16 ++ * hf/sf/df/tf -> bf (call __trunc[h|s|d|t]fbf2) ++*/ ++ ++/* 2) BF16 -> float ++ * bf -> hf == sf -> hf (call __truncsfhf2) ++ * bf -> sf (call __extendbfsf2) ++ * bf -> df == bf -> sf -> df (call __extendbfsf2 && __extendsfdf2) ++ * bf -> tf == bf -> sf -> tf (call __extendbfsf2 && __extendsftf2) ++*/ ++ ++extern _Bfloat16 bf; ++extern _Float16 hf; ++extern float sf; ++extern double df; ++extern long double tf; ++ ++void hf_to_bf () { bf = hf; } ++void bf_to_hf () { hf = bf; } ++ ++void sf_to_bf () { bf = sf; } ++void bf_to_sf () { sf = bf; } ++ ++void df_to_bf () { bf = df; } ++void bf_to_df () { df = bf; } ++ ++void tf_to_bf () { bf = tf; } ++void bf_to_tf () { tf = bf; } ++ ++/* { dg-final { scan-assembler-times "call\t__extendbfsf2" 3 { target { rv32 } } } } */ ++/* { dg-final { scan-assembler-times "call\t__extendbfsf2" 3 { target { rv64 } } } } */ ++ ++/* { dg-final { scan-assembler-times "call\t__extendsfdf2" 1 { target { rv32 } } } } */ ++/* { dg-final { scan-assembler-times "call\t__extendsfdf2" 1 { target { rv64 } } } } */ ++ ++/* { dg-final { scan-assembler-times "call\t__extendsftf2" 1 { target { rv32 } } } } */ ++/* { dg-final { scan-assembler-times "call\t__extendsftf2" 1 { target { rv64 } } } } */ ++ ++/* { dg-final { scan-assembler-times "call\t__truncsfhf2" 1 { target { rv32 } } } } */ ++/* { dg-final { scan-assembler-times "call\t__truncsfhf2" 1 { target { rv64 } } } } */ ++ ++/* { dg-final { scan-assembler-times "call\t__trunchfbf2" 1 { target { rv32 } } } } */ ++/* { dg-final { scan-assembler-times "call\t__trunchfbf2" 1 { target { rv64 } } } } */ ++ ++/* { dg-final { scan-assembler-times "call\t__truncsfbf2" 1 { target { rv32 } } } } */ ++/* { dg-final { scan-assembler-times "call\t__truncsfbf2" 1 { target { rv64 } } } } */ ++ ++/* { dg-final { scan-assembler-times "call\t__truncdfbf2" 1 { target { rv32 } } } } */ ++/* { dg-final { scan-assembler-times "call\t__truncdfbf2" 1 { target { rv64 } } } } */ ++ ++/* { dg-final { scan-assembler-times "call\t__trunctfbf2" 1 { target { rv32 } } } } */ ++/* { dg-final { scan-assembler-times "call\t__trunctfbf2" 1 { target { rv64 } } } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/bf16_integer_libcall_convert.c b/gcc/testsuite/gcc.target/riscv/bf16_integer_libcall_convert.c +new file mode 100644 +index 00000000000..ad714253a4a +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/bf16_integer_libcall_convert.c +@@ -0,0 +1,81 @@ ++/* { dg-do compile } */ ++/* { dg-options "-march=rv32i -mabi=ilp32 -O" { target { rv32 } } } */ ++/* { dg-options "-march=rv64i -mabi=lp64 -O" { target { rv64 } } } */ ++ ++/* 1) Integer -> BF16 ++ * qi/hi/si -> bf (call __floatsibf) ++ * uqi/uhi/usi -> bf (call __floatunsibf) ++ * di/ti -> bf (call __float[d|t]ibf) ++ * udi/uti -> bf (call __floatun[d|t]ibf) ++*/ ++ ++/* 2) BF16 -> Integer ++ * bf -> qi/hi/si (call __fixsfsi) ++ * bf -> uqi/uhi/usi (call __fixunssfsi) ++ * bf -> di/ti (call __fixsf[d|t]i) ++ * bf -> udi/uti (call __fixunssf[d|t]i) ++*/ ++ ++extern _Bfloat16 bf; ++ ++extern signed char qi; ++extern unsigned char uqi; ++extern signed short hi; ++extern unsigned short uhi; ++extern signed int si; ++extern unsigned int usi; ++extern signed long long di; ++extern unsigned long long udi; ++ ++void qi_to_bf () { bf = qi; } ++void uqi_to_bf () { bf = uqi; } ++void bf_to_qi () { qi = bf; } ++void bf_to_uqi () { uqi = bf; } ++ ++void hi_to_bf () { bf = hi; } ++void uhi_to_bf () { bf = uhi; } ++void bf_to_hi () { hi = bf; } ++void bf_to_uhi () { uhi = bf; } ++ ++void si_to_bf () { bf = si; } ++void usi_to_bf () { bf = usi; } ++void bf_to_si () { si = bf; } ++void bf_to_usi () { usi = bf; } ++ ++void di_to_bf () { bf = di; } ++void udi_to_bf () { bf = udi; } ++void bf_to_di () { di = bf; } ++void bf_to_udi () { udi = bf; } ++ ++#if __riscv_xlen == 64 ++extern signed __int128 ti; ++extern unsigned __int128 uti; ++void ti_to_bf () { bf = ti; } /* { dg-final { scan-assembler-times "call\t__floattibf" 1 { target { rv64 } } } } */ ++void uti_to_bf () { bf = uti; } /* { dg-final { scan-assembler-times "call\t__floatuntibf" 1 { target { rv64 } } } } */ ++void bf_to_ti () { ti = bf; } /* { dg-final { scan-assembler-times "call\t__fixsfti" 1 { target { rv64 } } } } */ ++void bf_to_uti () { uti = bf; } /* { dg-final { scan-assembler-times "call\t__fixunssfti" 1 { target { rv64 } } } } */ ++#endif ++ ++/* { dg-final { scan-assembler-times "call\t__fixsfsi" 3 { target { rv32 } } } } */ ++/* { dg-final { scan-assembler-times "call\t__fixsfsi" 3 { target { rv64 } } } } */ ++ ++/* { dg-final { scan-assembler-times "call\t__fixsfdi" 1 { target { rv32 } } } } */ ++/* { dg-final { scan-assembler-times "call\t__fixsfdi" 1 { target { rv64 } } } } */ ++ ++/* { dg-final { scan-assembler-times "call\t__fixunssfsi" 3 { target { rv32 } } } } */ ++/* { dg-final { scan-assembler-times "call\t__fixunssfsi" 3 { target { rv64 } } } } */ ++ ++/* { dg-final { scan-assembler-times "call\t__fixunssfdi" 1 { target { rv32 } } } } */ ++/* { dg-final { scan-assembler-times "call\t__fixunssfdi" 1 { target { rv64 } } } } */ ++ ++/* { dg-final { scan-assembler-times "call\t__floatsibf" 3 { target { rv32 } } } } */ ++/* { dg-final { scan-assembler-times "call\t__floatsibf" 3 { target { rv64 } } } } */ ++ ++/* { dg-final { scan-assembler-times "call\t__floatdibf" 1 { target { rv32 } } } } */ ++/* { dg-final { scan-assembler-times "call\t__floatdibf" 1 { target { rv64 } } } } */ ++ ++/* { dg-final { scan-assembler-times "call\t__floatunsibf" 3 { target { rv32 } } } } */ ++/* { dg-final { scan-assembler-times "call\t__floatunsibf" 3 { target { rv64 } } } } */ ++ ++/* { dg-final { scan-assembler-times "call\t__floatundibf" 1 { target { rv32 } } } } */ ++/* { dg-final { scan-assembler-times "call\t__floatundibf" 1 { target { rv64 } } } } */ +diff --git a/libgcc/config/riscv/sfp-machine.h b/libgcc/config/riscv/sfp-machine.h +index 0ad97081e88..9d3552ce48f 100644 +--- a/libgcc/config/riscv/sfp-machine.h ++++ b/libgcc/config/riscv/sfp-machine.h +@@ -41,6 +41,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + #define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_2_udiv(D,R,X,Y) + #define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_4_udiv(Q,R,X,Y) + ++#define _FP_NANFRAC_B _FP_QNANBIT_B + #define _FP_NANFRAC_H _FP_QNANBIT_H + #define _FP_NANFRAC_S _FP_QNANBIT_S + #define _FP_NANFRAC_D _FP_QNANBIT_D, 0 +@@ -64,6 +65,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + #define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_1_udiv_norm(D,R,X,Y) + #define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_2_udiv(Q,R,X,Y) + ++#define _FP_NANFRAC_B _FP_QNANBIT_B + #define _FP_NANFRAC_H _FP_QNANBIT_H + #define _FP_NANFRAC_S _FP_QNANBIT_S + #define _FP_NANFRAC_D _FP_QNANBIT_D +@@ -82,6 +84,7 @@ typedef unsigned int UTItype __attribute__ ((mode (TI))); + typedef int __gcc_CMPtype __attribute__ ((mode (__libgcc_cmp_return__))); + #define CMPtype __gcc_CMPtype + ++#define _FP_NANSIGN_B 0 + #define _FP_NANSIGN_H 0 + #define _FP_NANSIGN_S 0 + #define _FP_NANSIGN_D 0 +diff --git a/libgcc/config/riscv/t-softfp32 b/libgcc/config/riscv/t-softfp32 +index 1a3b1caa6b0..da55eb348c1 100644 +--- a/libgcc/config/riscv/t-softfp32 ++++ b/libgcc/config/riscv/t-softfp32 +@@ -42,7 +42,11 @@ softfp_extras += divsf3 divdf3 divtf3 + + endif + +-softfp_extensions += hfsf hfdf hftf +-softfp_truncations += tfhf dfhf sfhf ++softfp_extensions += hfsf hfdf hftf \ ++ bfsf ++softfp_truncations += tfhf dfhf sfhf \ ++ tfbf dfbf sfbf \ ++ hfbf bfhf + softfp_extras += fixhfsi fixhfdi fixunshfsi fixunshfdi \ +- floatsihf floatdihf floatunsihf floatundihf ++ floatsihf floatdihf floatunsihf floatundihf \ ++ floatsibf floatdibf floatunsibf floatundibf +diff --git a/libgcc/config/riscv/t-softfp64 b/libgcc/config/riscv/t-softfp64 +index c87d242d5c3..936e58e6cb1 100644 +--- a/libgcc/config/riscv/t-softfp64 ++++ b/libgcc/config/riscv/t-softfp64 +@@ -1,4 +1,5 @@ + include $(srcdir)/config/riscv/t-softfp32 + + softfp_int_modes += ti +-softfp_extras += fixhfti fixunshfti floattihf floatuntihf ++softfp_extras += fixhfti fixunshfti floattihf floatuntihf \ ++ floattibf floatuntibf +diff --git a/libgcc/soft-fp/floatsibf.c b/libgcc/soft-fp/floatsibf.c +new file mode 100644 +index 00000000000..0cb05e58fc1 +--- /dev/null ++++ b/libgcc/soft-fp/floatsibf.c +@@ -0,0 +1,45 @@ ++/* Software floating-point emulation. ++ Convert a 32bit signed integer to bfloat16 ++ Copyright (C) 2024 Free Software Foundation, Inc. ++ This file is part of the GNU C Library. ++ ++ The GNU C Library is free software; you can redistribute it and/or ++ modify it under the terms of the GNU Lesser General Public ++ License as published by the Free Software Foundation; either ++ version 2.1 of the License, or (at your option) any later version. ++ ++ In addition to the permissions in the GNU Lesser General Public ++ License, the Free Software Foundation gives you unlimited ++ permission to link the compiled version of this file into ++ combinations with other programs, and to distribute those ++ combinations without any restriction coming from the use of this ++ file. (The Lesser General Public License restrictions do apply in ++ other respects; for example, they cover modification of the file, ++ and distribution when not linked into a combine executable.) ++ ++ The GNU C Library is distributed in the hope that it will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ Lesser General Public License for more details. ++ ++ You should have received a copy of the GNU Lesser General Public ++ License along with the GNU C Library; if not, see ++ . */ ++ ++#include "soft-fp.h" ++#include "brain.h" ++ ++BFtype ++__floatsibf (SItype i) ++{ ++ FP_DECL_EX; ++ FP_DECL_B (A); ++ BFtype a; ++ ++ FP_INIT_ROUNDMODE; ++ FP_FROM_INT_B (A, i, SI_BITS, USItype); ++ FP_PACK_RAW_B (a, A); ++ FP_HANDLE_EXCEPTIONS; ++ ++ return a; ++} +diff --git a/libgcc/soft-fp/floatunsibf.c b/libgcc/soft-fp/floatunsibf.c +new file mode 100644 +index 00000000000..cd8c4bc8839 +--- /dev/null ++++ b/libgcc/soft-fp/floatunsibf.c +@@ -0,0 +1,45 @@ ++/* Software floating-point emulation. ++ Convert a 32bit unsigned integer to bfloat16 ++ Copyright (C) 2007-2024 Free Software Foundation, Inc. ++ This file is part of the GNU C Library. ++ ++ The GNU C Library is free software; you can redistribute it and/or ++ modify it under the terms of the GNU Lesser General Public ++ License as published by the Free Software Foundation; either ++ version 2.1 of the License, or (at your option) any later version. ++ ++ In addition to the permissions in the GNU Lesser General Public ++ License, the Free Software Foundation gives you unlimited ++ permission to link the compiled version of this file into ++ combinations with other programs, and to distribute those ++ combinations without any restriction coming from the use of this ++ file. (The Lesser General Public License restrictions do apply in ++ other respects; for example, they cover modification of the file, ++ and distribution when not linked into a combine executable.) ++ ++ The GNU C Library is distributed in the hope that it will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ Lesser General Public License for more details. ++ ++ You should have received a copy of the GNU Lesser General Public ++ License along with the GNU C Library; if not, see ++ . */ ++ ++#include "soft-fp.h" ++#include "brain.h" ++ ++BFtype ++__floatunsibf (USItype i) ++{ ++ FP_DECL_EX; ++ FP_DECL_B (A); ++ BFtype a; ++ ++ FP_INIT_ROUNDMODE; ++ FP_FROM_INT_B (A, i, SI_BITS, USItype); ++ FP_PACK_RAW_B (a, A); ++ FP_HANDLE_EXCEPTIONS; ++ ++ return a; ++} +-- +2.47.3 + diff --git a/1002-RISC-V-Nan-box-the-result-of-movbf-on-soft-bf16.patch b/1002-RISC-V-Nan-box-the-result-of-movbf-on-soft-bf16.patch new file mode 100644 index 0000000..3976eaf --- /dev/null +++ b/1002-RISC-V-Nan-box-the-result-of-movbf-on-soft-bf16.patch @@ -0,0 +1,182 @@ +From d9f38094bfe6a76efc3ee2f7edf0f499621c3bcc Mon Sep 17 00:00:00 2001 +From: Xiao Zeng +Date: Wed, 8 May 2024 14:00:58 -0600 +Subject: [PATCH 1002/1087] RISC-V: Nan-box the result of movbf on soft-bf16 + +commit ce51e6727c9d69bbab0e766c449e60fd41f5f2f9 upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +1 This patch implements the Nan-box of bf16. + +2 Please refer to the Nan-box implementation of hf16 in: + + +3 The discussion about Nan-box can be found on the website: + + +4 Below test are passed for this patch + * The riscv fully regression test. + +gcc/ChangeLog: + + * config/riscv/riscv.cc (riscv_legitimize_move): Expand movbf + with Nan-boxing value. + * config/riscv/riscv.md (*movbf_softfloat_boxing): New pattern. + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/_Bfloat16-nanboxing.c: New test. +--- + gcc/config/riscv/riscv.cc | 52 ++++++++++--------- + gcc/config/riscv/riscv.md | 12 ++++- + .../gcc.target/riscv/_Bfloat16-nanboxing.c | 38 ++++++++++++++ + 3 files changed, 77 insertions(+), 25 deletions(-) + create mode 100644 gcc/testsuite/gcc.target/riscv/_Bfloat16-nanboxing.c + +diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc +index 188ae18f2f4..9366c29d808 100644 +--- a/gcc/config/riscv/riscv.cc ++++ b/gcc/config/riscv/riscv.cc +@@ -3032,35 +3032,39 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx src) + } + + /* In order to fit NaN boxing, expand +- (set FP_REG (reg:HF src)) ++ (set FP_REG (reg:HF/BF src)) + to + (set (reg:SI/DI mask) (const_int -65536) +- (set (reg:SI/DI temp) (zero_extend:SI/DI (subreg:HI (reg:HF src) 0))) ++ (set (reg:SI/DI temp) (zero_extend:SI/DI (subreg:HI (reg:HF/BF src) 0))) + (set (reg:SI/DI temp) (ior:SI/DI (reg:SI/DI mask) (reg:SI/DI temp))) +- (set (reg:HF dest) (unspec:HF [ (reg:SI/DI temp) ] UNSPEC_FMV_SFP16_X)) ++ (set (reg:HF/BF dest) (unspec:HF/BF[ (reg:SI/DI temp) ] ++ UNSPEC_FMV_SFP16_X/UNSPEC_FMV_SBF16_X)) + */ + +- if (TARGET_HARD_FLOAT +- && !TARGET_ZFHMIN && mode == HFmode +- && REG_P (dest) && FP_REG_P (REGNO (dest)) +- && REG_P (src) && !FP_REG_P (REGNO (src)) +- && can_create_pseudo_p ()) +- { +- rtx mask = force_reg (word_mode, gen_int_mode (-65536, word_mode)); +- rtx temp = gen_reg_rtx (word_mode); +- emit_insn (gen_extend_insn (temp, +- simplify_gen_subreg (HImode, src, mode, 0), +- word_mode, HImode, 1)); +- if (word_mode == SImode) +- emit_insn (gen_iorsi3 (temp, mask, temp)); +- else +- emit_insn (gen_iordi3 (temp, mask, temp)); +- +- riscv_emit_move (dest, gen_rtx_UNSPEC (HFmode, gen_rtvec (1, temp), +- UNSPEC_FMV_SFP16_X)); +- +- return true; +- } ++ if (TARGET_HARD_FLOAT ++ && ((!TARGET_ZFHMIN && mode == HFmode) ++ || (!TARGET_ZFBFMIN && mode == BFmode)) ++ && REG_P (dest) && FP_REG_P (REGNO (dest)) ++ && REG_P (src) && !FP_REG_P (REGNO (src)) ++ && can_create_pseudo_p ()) ++ { ++ rtx mask = force_reg (word_mode, gen_int_mode (-65536, word_mode)); ++ rtx temp = gen_reg_rtx (word_mode); ++ emit_insn (gen_extend_insn (temp, ++ simplify_gen_subreg (HImode, src, mode, 0), ++ word_mode, HImode, 1)); ++ if (word_mode == SImode) ++ emit_insn (gen_iorsi3 (temp, mask, temp)); ++ else ++ emit_insn (gen_iordi3 (temp, mask, temp)); ++ ++ riscv_emit_move (dest, ++ gen_rtx_UNSPEC (mode, gen_rtvec (1, temp), ++ mode == HFmode ? UNSPEC_FMV_SFP16_X ++ : UNSPEC_FMV_SBF16_X)); ++ ++ return true; ++ } + + /* We need to deal with constants that would be legitimate + immediate_operands but aren't legitimate move_operands. */ +diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md +index cdbe970cab3..5f4afc4b127 100644 +--- a/gcc/config/riscv/riscv.md ++++ b/gcc/config/riscv/riscv.md +@@ -89,8 +89,9 @@ + ;; String unspecs + UNSPEC_STRLEN + +- ;; Workaround for HFmode without hardware extension ++ ;; Workaround for HFmode and BFmode without hardware extension + UNSPEC_FMV_SFP16_X ++ UNSPEC_FMV_SBF16_X + + ;; XTheadFmv moves + UNSPEC_XTHEADFMV +@@ -1914,6 +1915,15 @@ + [(set_attr "type" "fmove") + (set_attr "mode" "SF")]) + ++(define_insn "*movbf_softfloat_boxing" ++ [(set (match_operand:BF 0 "register_operand" "=f") ++ (unspec:BF [(match_operand:X 1 "register_operand" " r")] ++ UNSPEC_FMV_SBF16_X))] ++ "!TARGET_ZFBFMIN" ++ "fmv.w.x\t%0,%1" ++ [(set_attr "type" "fmove") ++ (set_attr "mode" "SF")]) ++ + ;; + ;; .................... + ;; +diff --git a/gcc/testsuite/gcc.target/riscv/_Bfloat16-nanboxing.c b/gcc/testsuite/gcc.target/riscv/_Bfloat16-nanboxing.c +new file mode 100644 +index 00000000000..11a73d22234 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/_Bfloat16-nanboxing.c +@@ -0,0 +1,38 @@ ++/* { dg-do compile } */ ++/* { dg-options "-march=rv64ifd -mabi=lp64d -mcmodel=medlow -O" } */ ++ ++_Bfloat16 gvar = 9.87654; ++union U ++{ ++ unsigned short i16; ++ _Bfloat16 f16; ++}; ++ ++_Bfloat16 ++test1 (unsigned short input) ++{ ++ union U tmp; ++ tmp.i16 = input; ++ return tmp.f16; ++} ++ ++_Bfloat16 ++test2 () ++{ ++ return 1.234f; ++} ++ ++_Bfloat16 ++test3 () ++{ ++ return gvar; ++} ++ ++_Bfloat16 ++test () ++{ ++ return 0.0f; ++} ++ ++/* { dg-final { scan-assembler-times "li\[ \t\]" 4 } } */ ++/* { dg-final { scan-assembler-times "fmv\.w\.x\[ \t\]" 4 } } */ +-- +2.47.3 + diff --git a/1003-RISC-V-Modify-_Bfloat16-to-__bf16.patch b/1003-RISC-V-Modify-_Bfloat16-to-__bf16.patch new file mode 100644 index 0000000..1e8f6a2 --- /dev/null +++ b/1003-RISC-V-Modify-_Bfloat16-to-__bf16.patch @@ -0,0 +1,208 @@ +From d42c1a8eabb0172b86d94bb7efad5e5e5c41a129 Mon Sep 17 00:00:00 2001 +From: Xiao Zeng +Date: Fri, 17 May 2024 13:48:21 +0800 +Subject: [PATCH 1003/1087] RISC-V: Modify _Bfloat16 to __bf16 + +commit 6da1d6efde2282e6582c00d1631e7457975ad998 upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +According to the description in: +, +the type representation symbol of BF16 has been corrected. + +Kito Cheng pointed out relevant information in the email: + + +gcc/ChangeLog: + + * config/riscv/riscv-builtins.cc (riscv_init_builtin_types): + Modify _Bfloat16 to __bf16. + * config/riscv/riscv.cc (riscv_mangle_type): Ditto. + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/_Bfloat16-nanboxing.c: Move to... + * gcc.target/riscv/__bf16-nanboxing.c: ...here. + * gcc.target/riscv/bf16_arithmetic.c: Modify _Bfloat16 to __bf16. + * gcc.target/riscv/bf16_call.c: Ditto. + * gcc.target/riscv/bf16_comparison.c: Ditto. + * gcc.target/riscv/bf16_float_libcall_convert.c: Ditto. + * gcc.target/riscv/bf16_integer_libcall_convert.c: Ditto. +--- + gcc/config/riscv/riscv-builtins.cc | 6 +++--- + gcc/config/riscv/riscv.cc | 2 +- + .../{_Bfloat16-nanboxing.c => __bf16-nanboxing.c} | 12 ++++++------ + gcc/testsuite/gcc.target/riscv/bf16_arithmetic.c | 6 +++--- + gcc/testsuite/gcc.target/riscv/bf16_call.c | 4 ++-- + gcc/testsuite/gcc.target/riscv/bf16_comparison.c | 6 +++--- + .../gcc.target/riscv/bf16_float_libcall_convert.c | 2 +- + .../gcc.target/riscv/bf16_integer_libcall_convert.c | 2 +- + 8 files changed, 20 insertions(+), 20 deletions(-) + rename gcc/testsuite/gcc.target/riscv/{_Bfloat16-nanboxing.c => __bf16-nanboxing.c} (83%) + +diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc +index 4c08834288a..dc54e1a59b5 100644 +--- a/gcc/config/riscv/riscv-builtins.cc ++++ b/gcc/config/riscv/riscv-builtins.cc +@@ -275,7 +275,7 @@ riscv_init_builtin_types (void) + lang_hooks.types.register_builtin_type (riscv_float16_type_node, + "_Float16"); + +- /* Provide the _Bfloat16 type and bfloat16_type_node if needed. */ ++ /* Provide the __bf16 type and bfloat16_type_node if needed. */ + if (!bfloat16_type_node) + { + riscv_bfloat16_type_node = make_node (REAL_TYPE); +@@ -286,9 +286,9 @@ riscv_init_builtin_types (void) + else + riscv_bfloat16_type_node = bfloat16_type_node; + +- if (!maybe_get_identifier ("_Bfloat16")) ++ if (!maybe_get_identifier ("__bf16")) + lang_hooks.types.register_builtin_type (riscv_bfloat16_type_node, +- "_Bfloat16"); ++ "__bf16"); + } + + /* Implement TARGET_INIT_BUILTINS. */ +diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc +index 9366c29d808..7022ec7f5bf 100644 +--- a/gcc/config/riscv/riscv.cc ++++ b/gcc/config/riscv/riscv.cc +@@ -10102,7 +10102,7 @@ riscv_asan_shadow_offset (void) + static const char * + riscv_mangle_type (const_tree type) + { +- /* Half-precision float, _Float16 is "DF16_" and _Bfloat16 is "DF16b". */ ++ /* Half-precision float, _Float16 is "DF16_" and __bf16 is "DF16b". */ + if (SCALAR_FLOAT_TYPE_P (type) && TYPE_PRECISION (type) == 16) + { + if (TYPE_MODE (type) == HFmode) +diff --git a/gcc/testsuite/gcc.target/riscv/_Bfloat16-nanboxing.c b/gcc/testsuite/gcc.target/riscv/__bf16-nanboxing.c +similarity index 83% +rename from gcc/testsuite/gcc.target/riscv/_Bfloat16-nanboxing.c +rename to gcc/testsuite/gcc.target/riscv/__bf16-nanboxing.c +index 11a73d22234..a9a586c98b9 100644 +--- a/gcc/testsuite/gcc.target/riscv/_Bfloat16-nanboxing.c ++++ b/gcc/testsuite/gcc.target/riscv/__bf16-nanboxing.c +@@ -1,14 +1,14 @@ + /* { dg-do compile } */ + /* { dg-options "-march=rv64ifd -mabi=lp64d -mcmodel=medlow -O" } */ + +-_Bfloat16 gvar = 9.87654; ++__bf16 gvar = 9.87654; + union U + { + unsigned short i16; +- _Bfloat16 f16; ++ __bf16 f16; + }; + +-_Bfloat16 ++__bf16 + test1 (unsigned short input) + { + union U tmp; +@@ -16,19 +16,19 @@ test1 (unsigned short input) + return tmp.f16; + } + +-_Bfloat16 ++__bf16 + test2 () + { + return 1.234f; + } + +-_Bfloat16 ++__bf16 + test3 () + { + return gvar; + } + +-_Bfloat16 ++__bf16 + test () + { + return 0.0f; +diff --git a/gcc/testsuite/gcc.target/riscv/bf16_arithmetic.c b/gcc/testsuite/gcc.target/riscv/bf16_arithmetic.c +index 9e485051260..190cc1d574a 100644 +--- a/gcc/testsuite/gcc.target/riscv/bf16_arithmetic.c ++++ b/gcc/testsuite/gcc.target/riscv/bf16_arithmetic.c +@@ -5,9 +5,9 @@ + /* 1) bf -> sf (call __extendbfsf2) */ + /* 2) sf1 [+|-|*|/] sf2 (call __[add|sub|mul|div]sf3) */ + /* 3) sf -> bf (call __truncsfbf2) */ +-extern _Bfloat16 bf; +-extern _Bfloat16 bf1; +-extern _Bfloat16 bf2; ++extern __bf16 bf; ++extern __bf16 bf1; ++extern __bf16 bf2; + + void bf_add_bf () { bf = bf1 + bf2; } + +diff --git a/gcc/testsuite/gcc.target/riscv/bf16_call.c b/gcc/testsuite/gcc.target/riscv/bf16_call.c +index 29f67719999..6ace1494370 100644 +--- a/gcc/testsuite/gcc.target/riscv/bf16_call.c ++++ b/gcc/testsuite/gcc.target/riscv/bf16_call.c +@@ -4,9 +4,9 @@ + + /* 1) bf -> sf (call __extendbfsf2) */ + /* 2) sf -> bf (call __truncsfbf2) */ +-__attribute__ ((noinline)) _Bfloat16 add (_Bfloat16 a, _Bfloat16 b) { return a + b; } ++__attribute__ ((noinline)) __bf16 add (__bf16 a, __bf16 b) { return a + b; } + +-_Bfloat16 test(_Bfloat16 a, _Bfloat16 b) { return add (a, b); } ++__bf16 test(__bf16 a, __bf16 b) { return add (a, b); } + + /* { dg-final { scan-assembler-times "call\t__extendbfsf2" 2 } } */ + /* { dg-final { scan-assembler-times "call\t__truncsfbf2" 1 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/bf16_comparison.c b/gcc/testsuite/gcc.target/riscv/bf16_comparison.c +index 69db803f403..2c13b8a0c9a 100644 +--- a/gcc/testsuite/gcc.target/riscv/bf16_comparison.c ++++ b/gcc/testsuite/gcc.target/riscv/bf16_comparison.c +@@ -4,9 +4,9 @@ + + /* 1) bf -> sf (call __extendbfsf2) */ + /* 2) sf1 [<|<=|>|>=|==] sf2 (call __[lt|le|gt|ge|eq]sf2) */ +-extern _Bfloat16 bf; +-extern _Bfloat16 bf1; +-extern _Bfloat16 bf2; ++extern __bf16 bf; ++extern __bf16 bf1; ++extern __bf16 bf2; + + void bf_lt_bf () { bf = (bf1 < bf2) ? bf1 : bf2; } + +diff --git a/gcc/testsuite/gcc.target/riscv/bf16_float_libcall_convert.c b/gcc/testsuite/gcc.target/riscv/bf16_float_libcall_convert.c +index ba6c6460bc2..423a071d1a5 100644 +--- a/gcc/testsuite/gcc.target/riscv/bf16_float_libcall_convert.c ++++ b/gcc/testsuite/gcc.target/riscv/bf16_float_libcall_convert.c +@@ -14,7 +14,7 @@ + * bf -> tf == bf -> sf -> tf (call __extendbfsf2 && __extendsftf2) + */ + +-extern _Bfloat16 bf; ++extern __bf16 bf; + extern _Float16 hf; + extern float sf; + extern double df; +diff --git a/gcc/testsuite/gcc.target/riscv/bf16_integer_libcall_convert.c b/gcc/testsuite/gcc.target/riscv/bf16_integer_libcall_convert.c +index ad714253a4a..2c37302e294 100644 +--- a/gcc/testsuite/gcc.target/riscv/bf16_integer_libcall_convert.c ++++ b/gcc/testsuite/gcc.target/riscv/bf16_integer_libcall_convert.c +@@ -16,7 +16,7 @@ + * bf -> udi/uti (call __fixunssf[d|t]i) + */ + +-extern _Bfloat16 bf; ++extern __bf16 bf; + + extern signed char qi; + extern unsigned char uqi; +-- +2.47.3 + diff --git a/1004-RISC-V-Add-Zfbfmin-extension-to-the-march-option.patch b/1004-RISC-V-Add-Zfbfmin-extension-to-the-march-option.patch new file mode 100644 index 0000000..e8658d6 --- /dev/null +++ b/1004-RISC-V-Add-Zfbfmin-extension-to-the-march-option.patch @@ -0,0 +1,226 @@ +From fbc6d983d8119dfe340428375b8c1ff8b1ad09d7 Mon Sep 17 00:00:00 2001 +From: Xiao Zeng +Date: Mon, 6 May 2024 15:57:37 -0600 +Subject: [PATCH 1004/1087] RISC-V: Add Zfbfmin extension to the -march= option + +commit 35224ead63732a3550ba4b1332c06e9dc7999c31 upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +This patch would like to add new sub extension (aka Zfbfmin) to the +-march= option. It introduces a new data type BF16. + +1 The Zfbfmin extension depend on 'F', and the FLH, FSH, FMV.X.H, and +FMV.H.X instructions as defined in the Zfh extension. + +2 The Zfhmin extension includes the following instructions from the +Zfh extension: FLH, FSH, FMV.X.H, FMV.H.X, FCVT.S.H, and FCVT.H.S. + +3 Zfhmin extension depend on 'F'. + +4 Simply put, just make Zfbfmin dependent on Zfhmin. + +Perhaps in the future, we could propose making the FLH, FSH, FMV.X.H, and +FMV.H.X instructions an independent extension to achieve precise dependency +relationships for the Zfbfmin. + +You can locate more information about Zfbfmin from below spec doc. + + + +gcc/ + * common/config/riscv/riscv-common.cc (riscv_implied_info): zfbfmin + implies zfhmin. + (riscv_ext_version_table, riscv_ext_flag_table): Add zfbfmin. + * config/riscv/riscv.opt (ZFBFMIN): Add optoion. + +gcc/testsuite/ + * gcc.target/riscv/arch-35.c: New test. + * gcc.target/riscv/arch-36.c: New test. + * gcc.target/riscv/predef-34.c: New test. + * gcc.target/riscv/predef-35.c: New test. +--- + gcc/common/config/riscv/riscv-common.cc | 3 ++ + gcc/config/riscv/riscv.opt | 2 + + gcc/testsuite/gcc.target/riscv/arch-35.c | 5 +++ + gcc/testsuite/gcc.target/riscv/arch-36.c | 5 +++ + gcc/testsuite/gcc.target/riscv/predef-34.c | 47 ++++++++++++++++++++++ + gcc/testsuite/gcc.target/riscv/predef-35.c | 47 ++++++++++++++++++++++ + 6 files changed, 109 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/riscv/arch-35.c + create mode 100644 gcc/testsuite/gcc.target/riscv/arch-36.c + create mode 100644 gcc/testsuite/gcc.target/riscv/predef-34.c + create mode 100644 gcc/testsuite/gcc.target/riscv/predef-35.c + +diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc +index 1c71ea43f1d..3e52b7517ba 100644 +--- a/gcc/common/config/riscv/riscv-common.cc ++++ b/gcc/common/config/riscv/riscv-common.cc +@@ -155,6 +155,7 @@ static const riscv_implied_info_t riscv_implied_info[] = + {"zvksed", "zve32x"}, + {"zvksh", "zve32x"}, + ++ {"zfbfmin", "zfhmin"}, + {"zfh", "zfhmin"}, + {"zfhmin", "f"}, + +@@ -331,6 +332,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] = + {"zvl32768b", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zvl65536b", ISA_SPEC_CLASS_NONE, 1, 0}, + ++ {"zfbfmin", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zfh", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zfhmin", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zvfbfmin", ISA_SPEC_CLASS_NONE, 1, 0}, +@@ -1614,6 +1616,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = + {"zvl32768b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL32768B}, + {"zvl65536b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL65536B}, + ++ {"zfbfmin", &gcc_options::x_riscv_zf_subext, MASK_ZFBFMIN}, + {"zfhmin", &gcc_options::x_riscv_zf_subext, MASK_ZFHMIN}, + {"zfh", &gcc_options::x_riscv_zf_subext, MASK_ZFH}, + {"zvfbfmin", &gcc_options::x_riscv_zf_subext, MASK_ZVFBFMIN}, +diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt +index 085dd616b63..9df0c26a561 100644 +--- a/gcc/config/riscv/riscv.opt ++++ b/gcc/config/riscv/riscv.opt +@@ -393,6 +393,8 @@ Mask(ZIC64B) Var(riscv_zicmo_subext) + TargetVariable + int riscv_zf_subext + ++Mask(ZFBFMIN) Var(riscv_zf_subext) ++ + Mask(ZFHMIN) Var(riscv_zf_subext) + + Mask(ZFH) Var(riscv_zf_subext) +diff --git a/gcc/testsuite/gcc.target/riscv/arch-35.c b/gcc/testsuite/gcc.target/riscv/arch-35.c +new file mode 100644 +index 00000000000..6c783769666 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/arch-35.c +@@ -0,0 +1,5 @@ ++/* { dg-do compile } */ ++/* { dg-options "-march=rv32i_zfbfmin -mabi=ilp32f" } */ ++int foo() ++{ ++} +diff --git a/gcc/testsuite/gcc.target/riscv/arch-36.c b/gcc/testsuite/gcc.target/riscv/arch-36.c +new file mode 100644 +index 00000000000..cbdccf12807 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/arch-36.c +@@ -0,0 +1,5 @@ ++/* { dg-do compile } */ ++/* { dg-options "-march=rv64i_zfbfmin -mabi=lp64f" } */ ++int foo() ++{ ++} +diff --git a/gcc/testsuite/gcc.target/riscv/predef-34.c b/gcc/testsuite/gcc.target/riscv/predef-34.c +new file mode 100644 +index 00000000000..0a993271f7f +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/predef-34.c +@@ -0,0 +1,47 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -march=rv32i_zfbfmin -mabi=ilp32f -mcmodel=medlow -misa-spec=20191213" } */ ++ ++int main () { ++ ++#ifndef __riscv_arch_test ++#error "__riscv_arch_test" ++#endif ++ ++#if __riscv_xlen != 32 ++#error "__riscv_xlen" ++#endif ++ ++#if !defined(__riscv_i) ++#error "__riscv_i" ++#endif ++ ++#if !defined(__riscv_f) ++#error "__riscv_f" ++#endif ++ ++#if !defined(__riscv_zfhmin) ++#error "__riscv_zfhmin" ++#endif ++ ++#if !defined(__riscv_zfbfmin) ++#error "__riscv_zfbfmin" ++#endif ++ ++#if defined(__riscv_v) ++#error "__riscv_v" ++#endif ++ ++#if defined(__riscv_d) ++#error "__riscv_d" ++#endif ++ ++#if defined(__riscv_c) ++#error "__riscv_c" ++#endif ++ ++#if defined(__riscv_a) ++#error "__riscv_a" ++#endif ++ ++ return 0; ++} +diff --git a/gcc/testsuite/gcc.target/riscv/predef-35.c b/gcc/testsuite/gcc.target/riscv/predef-35.c +new file mode 100644 +index 00000000000..76b328a8932 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/predef-35.c +@@ -0,0 +1,47 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -march=rv64i_zfbfmin -mabi=lp64f -mcmodel=medlow -misa-spec=20191213" } */ ++ ++int main () { ++ ++#ifndef __riscv_arch_test ++#error "__riscv_arch_test" ++#endif ++ ++#if __riscv_xlen != 64 ++#error "__riscv_xlen" ++#endif ++ ++#if !defined(__riscv_i) ++#error "__riscv_i" ++#endif ++ ++#if !defined(__riscv_f) ++#error "__riscv_f" ++#endif ++ ++#if !defined(__riscv_zfhmin) ++#error "__riscv_zfhmin" ++#endif ++ ++#if !defined(__riscv_zfbfmin) ++#error "__riscv_zfbfmin" ++#endif ++ ++#if defined(__riscv_v) ++#error "__riscv_v" ++#endif ++ ++#if defined(__riscv_d) ++#error "__riscv_d" ++#endif ++ ++#if defined(__riscv_c) ++#error "__riscv_c" ++#endif ++ ++#if defined(__riscv_a) ++#error "__riscv_a" ++#endif ++ ++ return 0; ++} +-- +2.47.3 + diff --git a/1005-RISC-V-Add-Zvfbfwma-extension-to-the-march-option.patch b/1005-RISC-V-Add-Zvfbfwma-extension-to-the-march-option.patch new file mode 100644 index 0000000..34efbe4 --- /dev/null +++ b/1005-RISC-V-Add-Zvfbfwma-extension-to-the-march-option.patch @@ -0,0 +1,245 @@ +From 68f0e0d73a27a6469a6186cc298f41bfa5ab96dd Mon Sep 17 00:00:00 2001 +From: Xiao Zeng +Date: Wed, 15 May 2024 10:03:40 +0800 +Subject: [PATCH 1005/1087] RISC-V: Add Zvfbfwma extension to the -march= + option + +commit 38dd4e26e07c6be7cf4d169141ee4f3a03f3a09d upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +This patch would like to add new sub extension (aka Zvfbfwma) to the +-march= option. It introduces a new data type BF16. + +1 In spec: "Zvfbfwma requires the Zvfbfmin extension and the Zfbfmin extension." + 1.1 In Embedded Processor: Zvfbfwma -> Zvfbfmin -> Zve32f + 1.2 In Application Processor: Zvfbfwma -> Zvfbfmin -> V + 1.3 In both scenarios, there are: Zvfbfwma -> Zfbfmin + +2 Zvfbfmin's information is in: + + +3 Zfbfmin's formation is in: + + +4 Depending on different usage scenarios, the Zvfbfwma extension may +depend on 'V' or 'Zve32f'. This patch only implements dependencies in +scenario of Embedded Processor. This is consistent with the processing +strategy in Zvfbfmin. In scenario of Application Processor, it is +necessary to explicitly indicate the dependent 'V' extension. + +5 You can locate more information about Zvfbfwma from below spec doc: + + +gcc/ChangeLog: + + * common/config/riscv/riscv-common.cc: + (riscv_implied_info): Add zvfbfwma item. + (riscv_ext_version_table): Ditto. + (riscv_ext_flag_table): Ditto. + * config/riscv/riscv.opt: + (MASK_ZVFBFWMA): New macro. + (TARGET_ZVFBFWMA): Ditto. + +gcc/testsuite/ChangeLog: + +* gcc.target/riscv/arch-37.c: New test. + * gcc.target/riscv/arch-38.c: New test. + * gcc.target/riscv/predef-36.c: New test. + * gcc.target/riscv/predef-37.c: New test. +--- + gcc/common/config/riscv/riscv-common.cc | 5 +++ + gcc/config/riscv/riscv.opt | 2 + + gcc/testsuite/gcc.target/riscv/arch-37.c | 5 +++ + gcc/testsuite/gcc.target/riscv/arch-38.c | 5 +++ + gcc/testsuite/gcc.target/riscv/predef-36.c | 48 ++++++++++++++++++++++ + gcc/testsuite/gcc.target/riscv/predef-37.c | 48 ++++++++++++++++++++++ + 6 files changed, 113 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/riscv/arch-37.c + create mode 100644 gcc/testsuite/gcc.target/riscv/arch-38.c + create mode 100644 gcc/testsuite/gcc.target/riscv/predef-36.c + create mode 100644 gcc/testsuite/gcc.target/riscv/predef-37.c + +diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc +index 3e52b7517ba..dd716166bd8 100644 +--- a/gcc/common/config/riscv/riscv-common.cc ++++ b/gcc/common/config/riscv/riscv-common.cc +@@ -162,6 +162,8 @@ static const riscv_implied_info_t riscv_implied_info[] = + {"zfa", "f"}, + + {"zvfbfmin", "zve32f"}, ++ {"zvfbfwma", "zvfbfmin"}, ++ {"zvfbfwma", "zfbfmin"}, + {"zvfhmin", "zve32f"}, + {"zvfh", "zve32f"}, + {"zvfh", "zfhmin"}, +@@ -336,6 +338,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] = + {"zfh", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zfhmin", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zvfbfmin", ISA_SPEC_CLASS_NONE, 1, 0}, ++ {"zvfbfwma", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zvfhmin", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zvfh", ISA_SPEC_CLASS_NONE, 1, 0}, + +@@ -1583,6 +1586,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = + {"zve64f", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_32}, + {"zve64d", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_64}, + {"zvfbfmin", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_BF_16}, ++ {"zvfbfwma", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_BF_16}, + {"zvfhmin", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_16}, + {"zvfh", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_16}, + +@@ -1620,6 +1624,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = + {"zfhmin", &gcc_options::x_riscv_zf_subext, MASK_ZFHMIN}, + {"zfh", &gcc_options::x_riscv_zf_subext, MASK_ZFH}, + {"zvfbfmin", &gcc_options::x_riscv_zf_subext, MASK_ZVFBFMIN}, ++ {"zvfbfwma", &gcc_options::x_riscv_zf_subext, MASK_ZVFBFWMA}, + {"zvfhmin", &gcc_options::x_riscv_zf_subext, MASK_ZVFHMIN}, + {"zvfh", &gcc_options::x_riscv_zf_subext, MASK_ZVFH}, + +diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt +index 9df0c26a561..ce7532364e5 100644 +--- a/gcc/config/riscv/riscv.opt ++++ b/gcc/config/riscv/riscv.opt +@@ -401,6 +401,8 @@ Mask(ZFH) Var(riscv_zf_subext) + + Mask(ZVFBFMIN) Var(riscv_zf_subext) + ++Mask(ZVFBFWMA) Var(riscv_zf_subext) ++ + Mask(ZVFHMIN) Var(riscv_zf_subext) + + Mask(ZVFH) Var(riscv_zf_subext) +diff --git a/gcc/testsuite/gcc.target/riscv/arch-37.c b/gcc/testsuite/gcc.target/riscv/arch-37.c +new file mode 100644 +index 00000000000..5b19a73c556 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/arch-37.c +@@ -0,0 +1,5 @@ ++/* { dg-do compile } */ ++/* { dg-options "-march=rv32i_zvfbfwma -mabi=ilp32f" } */ ++int ++foo () ++{} +diff --git a/gcc/testsuite/gcc.target/riscv/arch-38.c b/gcc/testsuite/gcc.target/riscv/arch-38.c +new file mode 100644 +index 00000000000..cee3efebe75 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/arch-38.c +@@ -0,0 +1,5 @@ ++/* { dg-do compile } */ ++/* { dg-options "-march=rv64iv_zvfbfwma -mabi=lp64d" } */ ++int ++foo () ++{} +diff --git a/gcc/testsuite/gcc.target/riscv/predef-36.c b/gcc/testsuite/gcc.target/riscv/predef-36.c +new file mode 100644 +index 00000000000..b0205b08513 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/predef-36.c +@@ -0,0 +1,48 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -march=rv32i_zvfbfwma -mabi=ilp32f -mcmodel=medlow -misa-spec=20191213" } */ ++ ++int ++main () ++{ ++#ifndef __riscv_arch_test ++#error "__riscv_arch_test" ++#endif ++ ++#if __riscv_xlen != 32 ++#error "__riscv_xlen" ++#endif ++ ++#if !defined(__riscv_i) ++#error "__riscv_i" ++#endif ++ ++#if !defined(__riscv_f) ++#error "__riscv_f" ++#endif ++ ++#if !defined(__riscv_zfbfmin) ++#error "__riscv_zfbfmin" ++#endif ++ ++#if !defined(__riscv_zvfbfwma) ++#error "__riscv_zvfbfwma" ++#endif ++ ++#if defined(__riscv_v) ++#error "__riscv_v" ++#endif ++ ++#if defined(__riscv_d) ++#error "__riscv_d" ++#endif ++ ++#if defined(__riscv_c) ++#error "__riscv_c" ++#endif ++ ++#if defined(__riscv_a) ++#error "__riscv_a" ++#endif ++ ++ return 0; ++} +diff --git a/gcc/testsuite/gcc.target/riscv/predef-37.c b/gcc/testsuite/gcc.target/riscv/predef-37.c +new file mode 100644 +index 00000000000..b5aa41102f4 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/predef-37.c +@@ -0,0 +1,48 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -march=rv64iv_zvfbfwma -mabi=lp64d -mcmodel=medlow -misa-spec=20191213" } */ ++ ++int ++main () ++{ ++#ifndef __riscv_arch_test ++#error "__riscv_arch_test" ++#endif ++ ++#if __riscv_xlen != 64 ++#error "__riscv_xlen" ++#endif ++ ++#if !defined(__riscv_i) ++#error "__riscv_i" ++#endif ++ ++#if !defined(__riscv_f) ++#error "__riscv_f" ++#endif ++ ++#if !defined(__riscv_d) ++#error "__riscv_d" ++#endif ++ ++#if !defined(__riscv_v) ++#error "__riscv_v" ++#endif ++ ++#if !defined(__riscv_zfbfmin) ++#error "__riscv_zfbfmin" ++#endif ++ ++#if !defined(__riscv_zvfbfwma) ++#error "__riscv_zvfbfwma" ++#endif ++ ++#if defined(__riscv_c) ++#error "__riscv_c" ++#endif ++ ++#if defined(__riscv_a) ++#error "__riscv_a" ++#endif ++ ++ return 0; ++} +-- +2.47.3 + diff --git a/1006-RISC-V-Fix-format-issue-for-trailing-operator-NFC.patch b/1006-RISC-V-Fix-format-issue-for-trailing-operator-NFC.patch new file mode 100644 index 0000000..9c1bf39 --- /dev/null +++ b/1006-RISC-V-Fix-format-issue-for-trailing-operator-NFC.patch @@ -0,0 +1,89 @@ +From d4c2ca8ede824a6e812920aa8f9ad31980f45c7c Mon Sep 17 00:00:00 2001 +From: Pan Li +Date: Tue, 14 May 2024 09:38:55 +0800 +Subject: [PATCH 1006/1087] RISC-V: Fix format issue for trailing operator + [NFC] + +commit upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +This patch would like to fix below format issue of trailing operator. + +=== ERROR type #1: trailing operator (4 error(s)) === +gcc/config/riscv/riscv-vector-builtins.cc:4641:39: if ((exts & +RVV_REQUIRE_ELEN_FP_16) && +gcc/config/riscv/riscv-vector-builtins.cc:4651:39: if ((exts & +RVV_REQUIRE_ELEN_FP_32) && +gcc/config/riscv/riscv-vector-builtins.cc:4661:39: if ((exts & +RVV_REQUIRE_ELEN_FP_64) && +gcc/config/riscv/riscv-vector-builtins.cc:4670:36: if ((exts & +RVV_REQUIRE_ELEN_64) && + +Passed the ./contrib/check_GNU_style.sh for this patch, and double +checked there is no other format issue of the original patch. + +Committed as format change. + +gcc/ChangeLog: + + * config/riscv/riscv-vector-builtins.cc + (validate_instance_type_required_extensions): Remove the + operator from the trailing and put it to new line. + +Signed-off-by: Pan Li +--- + gcc/config/riscv/riscv-vector-builtins.cc | 16 ++++++++-------- + 1 file changed, 8 insertions(+), 8 deletions(-) + +diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc +index 3fdb4400d70..c08d87a2680 100644 +--- a/gcc/config/riscv/riscv-vector-builtins.cc ++++ b/gcc/config/riscv/riscv-vector-builtins.cc +@@ -4638,8 +4638,8 @@ validate_instance_type_required_extensions (const rvv_type_info type, + { + uint64_t exts = type.required_extensions; + +- if ((exts & RVV_REQUIRE_ELEN_FP_16) && +- !TARGET_VECTOR_ELEN_FP_16_P (riscv_vector_elen_flags)) ++ if ((exts & RVV_REQUIRE_ELEN_FP_16) ++ && !TARGET_VECTOR_ELEN_FP_16_P (riscv_vector_elen_flags)) + { + error_at (EXPR_LOCATION (exp), + "built-in function %qE requires the " +@@ -4648,8 +4648,8 @@ validate_instance_type_required_extensions (const rvv_type_info type, + return false; + } + +- if ((exts & RVV_REQUIRE_ELEN_FP_32) && +- !TARGET_VECTOR_ELEN_FP_32_P (riscv_vector_elen_flags)) ++ if ((exts & RVV_REQUIRE_ELEN_FP_32) ++ && !TARGET_VECTOR_ELEN_FP_32_P (riscv_vector_elen_flags)) + { + error_at (EXPR_LOCATION (exp), + "built-in function %qE requires the " +@@ -4658,8 +4658,8 @@ validate_instance_type_required_extensions (const rvv_type_info type, + return false; + } + +- if ((exts & RVV_REQUIRE_ELEN_FP_64) && +- !TARGET_VECTOR_ELEN_FP_64_P (riscv_vector_elen_flags)) ++ if ((exts & RVV_REQUIRE_ELEN_FP_64) ++ && !TARGET_VECTOR_ELEN_FP_64_P (riscv_vector_elen_flags)) + { + error_at (EXPR_LOCATION (exp), + "built-in function %qE requires the zve64d or v ISA extension", +@@ -4667,8 +4667,8 @@ validate_instance_type_required_extensions (const rvv_type_info type, + return false; + } + +- if ((exts & RVV_REQUIRE_ELEN_64) && +- !TARGET_VECTOR_ELEN_64_P (riscv_vector_elen_flags)) ++ if ((exts & RVV_REQUIRE_ELEN_64) ++ && !TARGET_VECTOR_ELEN_64_P (riscv_vector_elen_flags)) + { + error_at (EXPR_LOCATION (exp), + "built-in function %qE requires the " +-- +2.47.3 + diff --git a/1007-RISC-V-Add-vector-type-of-BFloat16-format.patch b/1007-RISC-V-Add-vector-type-of-BFloat16-format.patch new file mode 100644 index 0000000..26183bb --- /dev/null +++ b/1007-RISC-V-Add-vector-type-of-BFloat16-format.patch @@ -0,0 +1,729 @@ +From bcccb7918234fd66ee63b2f70404fb178106ac3e Mon Sep 17 00:00:00 2001 +From: Feng Wang +Date: Thu, 13 Jun 2024 00:32:14 +0000 +Subject: [PATCH 1007/1087] RISC-V: Add vector type of BFloat16 format + +commit 666f167bec09d1234e6496c86b566fe1a71f61f0 upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +v3: Rebase +v2: Rebase +The vector type of BFloat16 format is added in this patch, +subsequent extensions to zvfbfmin and zvfwma need to be based +on this patch. + +Signed-off-by: Feng Wang +gcc/ChangeLog: + + * config/riscv/genrvv-type-indexer.cc (bfloat16_type): + Generate bf16 vector_type and scalar_type in DEF_RVV_TYPE_INDEX. + (bfloat16_wide_type): Ditto. + (same_ratio_eew_bf16_type): Ditto. + (main): Ditto. + * config/riscv/riscv-modes.def (ADJUST_BYTESIZE): + Add vector type for BFloat16. + (RVV_WHOLE_MODES): Add vector type for BFloat16. + (RVV_FRACT_MODE): Ditto. + (RVV_NF4_MODES): Ditto. + (RVV_NF8_MODES): Ditto. + (RVV_NF2_MODES): Ditto. + * config/riscv/riscv-vector-builtins-types.def (vbfloat16mf4_t): + Add builtin vector type for BFloat16. + (vbfloat16mf2_t): Add builtin vector type for BFloat16. + (vbfloat16m1_t): Ditto. + (vbfloat16m2_t): Ditto. + (vbfloat16m4_t): Ditto. + (vbfloat16m8_t): Ditto. + (vbfloat16mf4x2_t): Ditto. + (vbfloat16mf4x3_t): Ditto. + (vbfloat16mf4x4_t): Ditto. + (vbfloat16mf4x5_t): Ditto. + (vbfloat16mf4x6_t): Ditto. + (vbfloat16mf4x7_t): Ditto. + (vbfloat16mf4x8_t): Ditto. + (vbfloat16mf2x2_t): Ditto. + (vbfloat16mf2x3_t): Ditto. + (vbfloat16mf2x4_t): Ditto. + (vbfloat16mf2x5_t): Ditto. + (vbfloat16mf2x6_t): Ditto. + (vbfloat16mf2x7_t): Ditto. + (vbfloat16mf2x8_t): Ditto. + (vbfloat16m1x2_t): Ditto. + (vbfloat16m1x3_t): Ditto. + (vbfloat16m1x4_t): Ditto. + (vbfloat16m1x5_t): Ditto. + (vbfloat16m1x6_t): Ditto. + (vbfloat16m1x7_t): Ditto. + (vbfloat16m1x8_t): Ditto. + (vbfloat16m2x2_t): Ditto. + (vbfloat16m2x3_t): Ditto. + (vbfloat16m2x4_t): Ditto. + (vbfloat16m4x2_t): Ditto. + * config/riscv/riscv-vector-builtins.cc (check_required_extensions): + Add required_ext checking for BFloat16. + * config/riscv/riscv-vector-builtins.def (vbfloat16mf4_t): + Add vector_type for BFloat16 in builtins.def. + (vbfloat16mf4x2_t): Ditto. + (vbfloat16mf4x3_t): Ditto. + (vbfloat16mf4x4_t): Ditto. + (vbfloat16mf4x5_t): Ditto. + (vbfloat16mf4x6_t): Ditto. + (vbfloat16mf4x7_t): Ditto. + (vbfloat16mf4x8_t): Ditto. + (vbfloat16mf2_t): Ditto. + (vbfloat16mf2x2_t): Ditto. + (vbfloat16mf2x3_t): Ditto. + (vbfloat16mf2x4_t): Ditto. + (vbfloat16mf2x5_t): Ditto. + (vbfloat16mf2x6_t): Ditto. + (vbfloat16mf2x7_t): Ditto. + (vbfloat16mf2x8_t): Ditto. + (vbfloat16m1_t): Ditto. + (vbfloat16m1x2_t): Ditto. + (vbfloat16m1x3_t): Ditto. + (vbfloat16m1x4_t): Ditto. + (vbfloat16m1x5_t): Ditto. + (vbfloat16m1x6_t): Ditto. + (vbfloat16m1x7_t): Ditto. + (vbfloat16m1x8_t): Ditto. + (vbfloat16m2_t): Ditto. + (vbfloat16m2x2_t): Ditto. + (vbfloat16m2x3_t): Ditto. + (vbfloat16m2x4_t): Ditto. + (vbfloat16m4_t): Ditto. + (vbfloat16m4x2_t): Ditto. + (vbfloat16m8_t): Ditto. + (double_trunc_bfloat_scalar): Add scalar_type def for BFloat16. + (double_trunc_bfloat_vector): Add vector_type def for BFloat16. + * config/riscv/riscv-vector-builtins.h (RVV_REQUIRE_ELEN_BF_16): + Add required defination of BFloat16 ext. + * config/riscv/riscv-vector-switch.def (ENTRY): + Add vector_type information for BFloat16. + (TUPLE_ENTRY): Add tuple vector_type information for BFloat16. +--- + gcc/config/riscv/genrvv-type-indexer.cc | 115 ++++++++++++++++++ + gcc/config/riscv/riscv-modes.def | 30 ++++- + .../riscv/riscv-vector-builtins-types.def | 50 ++++++++ + gcc/config/riscv/riscv-vector-builtins.cc | 7 +- + gcc/config/riscv/riscv-vector-builtins.def | 55 ++++++++- + gcc/config/riscv/riscv-vector-builtins.h | 1 + + gcc/config/riscv/riscv-vector-switch.def | 36 ++++++ + 7 files changed, 291 insertions(+), 3 deletions(-) + +diff --git a/gcc/config/riscv/genrvv-type-indexer.cc b/gcc/config/riscv/genrvv-type-indexer.cc +index 27cbd14982c..8626ddeaaa8 100644 +--- a/gcc/config/riscv/genrvv-type-indexer.cc ++++ b/gcc/config/riscv/genrvv-type-indexer.cc +@@ -117,6 +117,42 @@ inttype (unsigned sew, int lmul_log2, unsigned nf, bool unsigned_p) + return mode.str (); + } + ++std::string ++bfloat16_type (int lmul_log2) ++{ ++ if (!valid_type (16, lmul_log2, /*float_t*/ true)) ++ return "INVALID"; ++ ++ std::stringstream mode; ++ mode << "vbfloat16" << to_lmul (lmul_log2) << "_t"; ++ return mode.str (); ++} ++ ++std::string ++bfloat16_wide_type (int lmul_log2) ++{ ++ if (!valid_type (32, lmul_log2, /*float_t*/ true)) ++ return "INVALID"; ++ ++ std::stringstream mode; ++ mode << "vfloat32" << to_lmul (lmul_log2) << "_t"; ++ return mode.str (); ++} ++ ++std::string ++bfloat16_type (int lmul_log2, unsigned nf) ++{ ++ if (!valid_type (16, lmul_log2, nf, /*float_t*/ true)) ++ return "INVALID"; ++ ++ std::stringstream mode; ++ mode << "vbfloat16" << to_lmul (lmul_log2); ++ if (nf > 1) ++ mode << "x" << nf; ++ mode << "_t"; ++ return mode.str (); ++} ++ + std::string + floattype (unsigned sew, int lmul_log2) + { +@@ -182,6 +218,15 @@ same_ratio_eew_type (unsigned sew, int lmul_log2, unsigned eew, bool unsigned_p, + return inttype (eew, elmul_log2, unsigned_p); + } + ++std::string ++same_ratio_eew_bf16_type (unsigned sew, int lmul_log2) ++{ ++ if (sew != 32) ++ return "INVALID"; ++ int elmul_log2 = lmul_log2 - 1; ++ return bfloat16_type (elmul_log2); ++} ++ + int + main (int argc, const char **argv) + { +@@ -215,6 +260,8 @@ main (int argc, const char **argv) + fprintf (fp, " /*DOUBLE_TRUNC_SIGNED*/ INVALID,\n"); + fprintf (fp, " /*DOUBLE_TRUNC_UNSIGNED*/ INVALID,\n"); + fprintf (fp, " /*DOUBLE_TRUNC_UNSIGNED_SCALAR*/ INVALID,\n"); ++ fprintf (fp, " /*DOUBLE_TRUNC_BFLOAT_SCALAR*/ INVALID,\n"); ++ fprintf (fp, " /*DOUBLE_TRUNC_BFLOAT*/ INVALID,\n"); + fprintf (fp, " /*DOUBLE_TRUNC_FLOAT*/ INVALID,\n"); + fprintf (fp, " /*FLOAT*/ INVALID,\n"); + fprintf (fp, " /*LMUL1*/ INVALID,\n"); +@@ -294,6 +341,8 @@ main (int argc, const char **argv) + same_ratio_eew_type (sew, lmul_log2, sew / 2, true, + false) + .c_str ()); ++ fprintf (fp, " /*DOUBLE_TRUNC_BFLOAT_SCALAR*/ INVALID,\n"); ++ fprintf (fp, " /*DOUBLE_TRUNC_BFLOAT*/ INVALID,\n"); + fprintf (fp, " /*DOUBLE_TRUNC_FLOAT*/ %s,\n", + same_ratio_eew_type (sew, lmul_log2, sew / 2, false, true) + .c_str ()); +@@ -341,6 +390,68 @@ main (int argc, const char **argv) + inttype (sew, lmul_log2, 1, unsigned_p).c_str ()); + fprintf (fp, ")\n"); + } ++ // Build for vbfloat16 ++ for (int lmul_log2 : {-2, -1, 0, 1, 2, 3}) ++ for (unsigned nf : {1, 2, 3, 4, 5, 6, 7, 8}) ++ { ++ if (!valid_type (16, lmul_log2, nf, /*float_t*/ true)) ++ continue; ++ ++ fprintf (fp, "DEF_RVV_TYPE_INDEX (\n"); ++ fprintf (fp, " /*VECTOR*/ %s,\n", ++ bfloat16_type (lmul_log2, nf).c_str ()); ++ fprintf (fp, " /*MASK*/ %s,\n", maskmode (16, lmul_log2).c_str ()); ++ fprintf (fp, " /*SIGNED*/ %s,\n", ++ inttype (16, lmul_log2, /*unsigned_p*/ false).c_str ()); ++ fprintf (fp, " /*UNSIGNED*/ %s,\n", ++ inttype (16, lmul_log2, /*unsigned_p*/ true).c_str ()); ++ for (unsigned eew : {8, 16, 32, 64}) ++ fprintf ( ++ fp, " /*EEW%d_INDEX*/ %s,\n", eew, ++ same_ratio_eew_type (16, lmul_log2, eew, true, false).c_str ()); ++ fprintf (fp, " /*SHIFT*/ INVALID,\n"); ++ fprintf (fp, " /*DOUBLE_TRUNC*/ %s,\n", ++ same_ratio_eew_type (16, lmul_log2, 8, false, true).c_str ()); ++ fprintf (fp, " /*QUAD_TRUNC*/ INVALID,\n"); ++ fprintf (fp, " /*OCT_TRUNC*/ INVALID,\n"); ++ fprintf (fp, " /*DOUBLE_TRUNC_SCALAR*/ %s,\n", ++ same_ratio_eew_type (16, lmul_log2, 8, false, true).c_str ()); ++ fprintf (fp, " /*DOUBLE_TRUNC_SIGNED*/ %s,\n", ++ same_ratio_eew_type (16, lmul_log2, 8, false, false).c_str ()); ++ fprintf (fp, " /*DOUBLE_TRUNC_UNSIGNED*/ %s,\n", ++ same_ratio_eew_type (16, lmul_log2, 8, true, false).c_str ()); ++ fprintf (fp, " /*DOUBLE_TRUNC_UNSIGNED_SCALAR*/ INVALID,\n"); ++ fprintf (fp, " /*DOUBLE_TRUNC_BFLOAT_SCALAR*/ INVALID,\n"); ++ fprintf (fp, " /*DOUBLE_TRUNC_BFLOAT*/ INVALID,\n"); ++ fprintf (fp, " /*DOUBLE_TRUNC_FLOAT*/ %s,\n", ++ same_ratio_eew_type (16, lmul_log2, 8, false, true).c_str ()); ++ fprintf (fp, " /*FLOAT*/ INVALID,\n"); ++ fprintf (fp, " /*LMUL1*/ %s,\n", ++ bfloat16_type (/*lmul_log2*/ 0).c_str ()); ++ fprintf (fp, " /*WLMUL1*/ %s,\n", ++ bfloat16_wide_type (/*lmul_log2*/ 0).c_str ()); ++ for (unsigned eew : {8, 16, 32, 64}) ++ fprintf (fp, " /*EEW%d_INTERPRET*/ INVALID,\n", eew); ++ ++ for (unsigned boolsize : BOOL_SIZE_LIST) ++ fprintf (fp, " /*BOOL%d_INTERPRET*/ INVALID,\n", boolsize); ++ ++ for (unsigned eew : EEW_SIZE_LIST) ++ fprintf (fp, " /*SIGNED_EEW%d_LMUL1_INTERPRET*/ INVALID,\n", eew); ++ ++ for (unsigned eew : EEW_SIZE_LIST) ++ fprintf (fp, " /*UNSIGNED_EEW%d_LMUL1_INTERPRET*/ INVALID,\n", eew); ++ ++ for (unsigned lmul_log2_offset : {1, 2, 3, 4, 5, 6}) ++ { ++ unsigned multiple_of_lmul = 1 << lmul_log2_offset; ++ fprintf (fp, " /*X%d_VLMUL_EXT*/ %s,\n", multiple_of_lmul, ++ bfloat16_type (lmul_log2 + lmul_log2_offset).c_str ()); ++ } ++ fprintf (fp, " /*TUPLE_SUBPART*/ %s\n", ++ bfloat16_type (lmul_log2, 1U).c_str ()); ++ fprintf (fp, ")\n"); ++ } + // Build for vfloat + for (unsigned sew : {16, 32, 64}) + for (int lmul_log2 : {-3, -2, -1, 0, 1, 2, 3}) +@@ -378,6 +489,10 @@ main (int argc, const char **argv) + same_ratio_eew_type (sew, lmul_log2, sew / 2, true, false) + .c_str ()); + fprintf (fp, " /*DOUBLE_TRUNC_UNSIGNED_SCALAR*/ INVALID,\n"); ++ fprintf (fp, " /*DOUBLE_TRUNC_BFLOAT_SCALAR*/ %s,\n", ++ same_ratio_eew_bf16_type (sew, lmul_log2).c_str ()); ++ fprintf (fp, " /*DOUBLE_TRUNC_BFLOAT*/ %s,\n", ++ same_ratio_eew_bf16_type (sew, lmul_log2).c_str ()); + fprintf (fp, " /*DOUBLE_TRUNC_FLOAT*/ %s,\n", + same_ratio_eew_type (sew, lmul_log2, sew / 2, false, true) + .c_str ()); +diff --git a/gcc/config/riscv/riscv-modes.def b/gcc/config/riscv/riscv-modes.def +index 6de4e440298..949317e11e4 100644 +--- a/gcc/config/riscv/riscv-modes.def ++++ b/gcc/config/riscv/riscv-modes.def +@@ -93,6 +93,7 @@ ADJUST_BYTESIZE (RVVMF64BI, riscv_v_adjust_bytesize (RVVMF64BImode, 1)); + |DF |RVVM1DF|RVVM2DF|RVVM4DF|RVVM8DF|N/A |N/A |N/A | + |SF |RVVM1SF|RVVM2SF|RVVM4SF|RVVM8SF|RVVMF2SF|N/A |N/A | + |HF |RVVM1HF|RVVM2HF|RVVM4HF|RVVM8HF|RVVMF2HF|RVVMF4HF|N/A | ++ |BF |RVVM1BF|RVVM2BF|RVVM4BF|RVVM8BF|RVVMF2BF|RVVMF4BF|N/A | + + There are the following data types for ELEN = 32. + +@@ -101,11 +102,13 @@ There are the following data types for ELEN = 32. + |HI |RVVM1HI|RVVM2HI|RVVM4HI|RVVM8HI|RVVMF2HI|N/A |N/A | + |QI |RVVM1QI|RVVM2QI|RVVM4QI|RVVM8QI|RVVMF2QI|RVVMF4QI|N/A | + |SF |RVVM1SF|RVVM2SF|RVVM4SF|RVVM8SF|N/A |N/A |N/A | +- |HF |RVVM1HF|RVVM2HF|RVVM4HF|RVVM8HF|RVVMF2HF|N/A |N/A | */ ++ |HF |RVVM1HF|RVVM2HF|RVVM4HF|RVVM8HF|RVVMF2HF|N/A |N/A | ++ |BF |RVVM1BF|RVVM2BF|RVVM4BF|RVVM8BF|RVVMF2BF|N/A |N/A | */ + + #define RVV_WHOLE_MODES(LMUL) \ + VECTOR_MODE_WITH_PREFIX (RVVM, INT, QI, LMUL, 0); \ + VECTOR_MODE_WITH_PREFIX (RVVM, INT, HI, LMUL, 0); \ ++ VECTOR_MODE_WITH_PREFIX (RVVM, FLOAT, BF, LMUL, 0); \ + VECTOR_MODE_WITH_PREFIX (RVVM, FLOAT, HF, LMUL, 0); \ + VECTOR_MODE_WITH_PREFIX (RVVM, INT, SI, LMUL, 0); \ + VECTOR_MODE_WITH_PREFIX (RVVM, FLOAT, SF, LMUL, 0); \ +@@ -120,6 +123,8 @@ There are the following data types for ELEN = 32. + riscv_v_adjust_nunits (RVVM##LMUL##SImode, false, LMUL, 1)); \ + ADJUST_NUNITS (RVVM##LMUL##DI, \ + riscv_v_adjust_nunits (RVVM##LMUL##DImode, false, LMUL, 1)); \ ++ ADJUST_NUNITS (RVVM##LMUL##BF, \ ++ riscv_v_adjust_nunits (RVVM##LMUL##BFmode, false, LMUL, 1)); \ + ADJUST_NUNITS (RVVM##LMUL##HF, \ + riscv_v_adjust_nunits (RVVM##LMUL##HFmode, false, LMUL, 1)); \ + ADJUST_NUNITS (RVVM##LMUL##SF, \ +@@ -131,6 +136,7 @@ There are the following data types for ELEN = 32. + ADJUST_ALIGNMENT (RVVM##LMUL##HI, 2); \ + ADJUST_ALIGNMENT (RVVM##LMUL##SI, 4); \ + ADJUST_ALIGNMENT (RVVM##LMUL##DI, 8); \ ++ ADJUST_ALIGNMENT (RVVM##LMUL##BF, 2); \ + ADJUST_ALIGNMENT (RVVM##LMUL##HF, 2); \ + ADJUST_ALIGNMENT (RVVM##LMUL##SF, 4); \ + ADJUST_ALIGNMENT (RVVM##LMUL##DF, 8); +@@ -153,6 +159,8 @@ RVV_FRACT_MODE (INT, QI, 4, 1) + RVV_FRACT_MODE (INT, QI, 8, 1) + RVV_FRACT_MODE (INT, HI, 2, 2) + RVV_FRACT_MODE (INT, HI, 4, 2) ++RVV_FRACT_MODE (FLOAT, BF, 2, 2) ++RVV_FRACT_MODE (FLOAT, BF, 4, 2) + RVV_FRACT_MODE (FLOAT, HF, 2, 2) + RVV_FRACT_MODE (FLOAT, HF, 4, 2) + RVV_FRACT_MODE (INT, SI, 2, 4) +@@ -174,6 +182,9 @@ RVV_FRACT_MODE (FLOAT, SF, 2, 4) + VECTOR_MODE_WITH_PREFIX (RVVMF4x, INT, HI, NF, 1); \ + VECTOR_MODE_WITH_PREFIX (RVVMF2x, INT, HI, NF, 1); \ + VECTOR_MODE_WITH_PREFIX (RVVM1x, INT, HI, NF, 1); \ ++ VECTOR_MODE_WITH_PREFIX (RVVMF4x, FLOAT, BF, NF, 1); \ ++ VECTOR_MODE_WITH_PREFIX (RVVMF2x, FLOAT, BF, NF, 1); \ ++ VECTOR_MODE_WITH_PREFIX (RVVM1x, FLOAT, BF, NF, 1); \ + VECTOR_MODE_WITH_PREFIX (RVVMF4x, FLOAT, HF, NF, 1); \ + VECTOR_MODE_WITH_PREFIX (RVVMF2x, FLOAT, HF, NF, 1); \ + VECTOR_MODE_WITH_PREFIX (RVVM1x, FLOAT, HF, NF, 1); \ +@@ -198,6 +209,12 @@ RVV_FRACT_MODE (FLOAT, SF, 2, 4) + riscv_v_adjust_nunits (RVVMF2x##NF##HImode, true, 2, NF)); \ + ADJUST_NUNITS (RVVM1x##NF##HI, \ + riscv_v_adjust_nunits (RVVM1x##NF##HImode, false, 1, NF)); \ ++ ADJUST_NUNITS (RVVMF4x##NF##BF, \ ++ riscv_v_adjust_nunits (RVVMF4x##NF##BFmode, true, 4, NF)); \ ++ ADJUST_NUNITS (RVVMF2x##NF##BF, \ ++ riscv_v_adjust_nunits (RVVMF2x##NF##BFmode, true, 2, NF)); \ ++ ADJUST_NUNITS (RVVM1x##NF##BF, \ ++ riscv_v_adjust_nunits (RVVM1x##NF##BFmode, false, 1, NF)); \ + ADJUST_NUNITS (RVVMF4x##NF##HF, \ + riscv_v_adjust_nunits (RVVMF4x##NF##HFmode, true, 4, NF)); \ + ADJUST_NUNITS (RVVMF2x##NF##HF, \ +@@ -224,6 +241,9 @@ RVV_FRACT_MODE (FLOAT, SF, 2, 4) + ADJUST_ALIGNMENT (RVVMF4x##NF##HI, 2); \ + ADJUST_ALIGNMENT (RVVMF2x##NF##HI, 2); \ + ADJUST_ALIGNMENT (RVVM1x##NF##HI, 2); \ ++ ADJUST_ALIGNMENT (RVVMF4x##NF##BF, 2); \ ++ ADJUST_ALIGNMENT (RVVMF2x##NF##BF, 2); \ ++ ADJUST_ALIGNMENT (RVVM1x##NF##BF, 2); \ + ADJUST_ALIGNMENT (RVVMF4x##NF##HF, 2); \ + ADJUST_ALIGNMENT (RVVMF2x##NF##HF, 2); \ + ADJUST_ALIGNMENT (RVVM1x##NF##HF, 2); \ +@@ -245,6 +265,7 @@ RVV_NF8_MODES (2) + #define RVV_NF4_MODES(NF) \ + VECTOR_MODE_WITH_PREFIX (RVVM2x, INT, QI, NF, 1); \ + VECTOR_MODE_WITH_PREFIX (RVVM2x, INT, HI, NF, 1); \ ++ VECTOR_MODE_WITH_PREFIX (RVVM2x, FLOAT, BF, NF, 1); \ + VECTOR_MODE_WITH_PREFIX (RVVM2x, FLOAT, HF, NF, 1); \ + VECTOR_MODE_WITH_PREFIX (RVVM2x, INT, SI, NF, 1); \ + VECTOR_MODE_WITH_PREFIX (RVVM2x, FLOAT, SF, NF, 1); \ +@@ -255,6 +276,8 @@ RVV_NF8_MODES (2) + riscv_v_adjust_nunits (RVVM2x##NF##QImode, false, 2, NF)); \ + ADJUST_NUNITS (RVVM2x##NF##HI, \ + riscv_v_adjust_nunits (RVVM2x##NF##HImode, false, 2, NF)); \ ++ ADJUST_NUNITS (RVVM2x##NF##BF, \ ++ riscv_v_adjust_nunits (RVVM2x##NF##BFmode, false, 2, NF)); \ + ADJUST_NUNITS (RVVM2x##NF##HF, \ + riscv_v_adjust_nunits (RVVM2x##NF##HFmode, false, 2, NF)); \ + ADJUST_NUNITS (RVVM2x##NF##SI, \ +@@ -268,6 +291,7 @@ RVV_NF8_MODES (2) + \ + ADJUST_ALIGNMENT (RVVM2x##NF##QI, 1); \ + ADJUST_ALIGNMENT (RVVM2x##NF##HI, 2); \ ++ ADJUST_ALIGNMENT (RVVM2x##NF##BF, 2); \ + ADJUST_ALIGNMENT (RVVM2x##NF##HF, 2); \ + ADJUST_ALIGNMENT (RVVM2x##NF##SI, 4); \ + ADJUST_ALIGNMENT (RVVM2x##NF##SF, 4); \ +@@ -281,6 +305,7 @@ RVV_NF4_MODES (4) + #define RVV_NF2_MODES(NF) \ + VECTOR_MODE_WITH_PREFIX (RVVM4x, INT, QI, NF, 1); \ + VECTOR_MODE_WITH_PREFIX (RVVM4x, INT, HI, NF, 1); \ ++ VECTOR_MODE_WITH_PREFIX (RVVM4x, FLOAT, BF, NF, 1); \ + VECTOR_MODE_WITH_PREFIX (RVVM4x, FLOAT, HF, NF, 1); \ + VECTOR_MODE_WITH_PREFIX (RVVM4x, INT, SI, NF, 1); \ + VECTOR_MODE_WITH_PREFIX (RVVM4x, FLOAT, SF, NF, 1); \ +@@ -291,6 +316,8 @@ RVV_NF4_MODES (4) + riscv_v_adjust_nunits (RVVM4x##NF##QImode, false, 4, NF)); \ + ADJUST_NUNITS (RVVM4x##NF##HI, \ + riscv_v_adjust_nunits (RVVM4x##NF##HImode, false, 4, NF)); \ ++ ADJUST_NUNITS (RVVM4x##NF##BF, \ ++ riscv_v_adjust_nunits (RVVM4x##NF##BFmode, false, 4, NF)); \ + ADJUST_NUNITS (RVVM4x##NF##HF, \ + riscv_v_adjust_nunits (RVVM4x##NF##HFmode, false, 4, NF)); \ + ADJUST_NUNITS (RVVM4x##NF##SI, \ +@@ -304,6 +331,7 @@ RVV_NF4_MODES (4) + \ + ADJUST_ALIGNMENT (RVVM4x##NF##QI, 1); \ + ADJUST_ALIGNMENT (RVVM4x##NF##HI, 2); \ ++ ADJUST_ALIGNMENT (RVVM4x##NF##BF, 2); \ + ADJUST_ALIGNMENT (RVVM4x##NF##HF, 2); \ + ADJUST_ALIGNMENT (RVVM4x##NF##SI, 4); \ + ADJUST_ALIGNMENT (RVVM4x##NF##SF, 4); \ +diff --git a/gcc/config/riscv/riscv-vector-builtins-types.def b/gcc/config/riscv/riscv-vector-builtins-types.def +index 61019a56844..e7fca4cca79 100644 +--- a/gcc/config/riscv/riscv-vector-builtins-types.def ++++ b/gcc/config/riscv/riscv-vector-builtins-types.def +@@ -397,6 +397,13 @@ DEF_RVV_U_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64) + DEF_RVV_U_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_64) + DEF_RVV_U_OPS (vuint64m8_t, RVV_REQUIRE_ELEN_64) + ++DEF_RVV_F_OPS (vbfloat16mf4_t, RVV_REQUIRE_ELEN_BF_16 | RVV_REQUIRE_MIN_VLEN_64) ++DEF_RVV_F_OPS (vbfloat16mf2_t, RVV_REQUIRE_ELEN_BF_16) ++DEF_RVV_F_OPS (vbfloat16m1_t, RVV_REQUIRE_ELEN_BF_16) ++DEF_RVV_F_OPS (vbfloat16m2_t, RVV_REQUIRE_ELEN_BF_16) ++DEF_RVV_F_OPS (vbfloat16m4_t, RVV_REQUIRE_ELEN_BF_16) ++DEF_RVV_F_OPS (vbfloat16m8_t, RVV_REQUIRE_ELEN_BF_16) ++ + DEF_RVV_F_OPS (vfloat16mf4_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64) + DEF_RVV_F_OPS (vfloat16mf2_t, RVV_REQUIRE_ELEN_FP_16) + DEF_RVV_F_OPS (vfloat16m1_t, RVV_REQUIRE_ELEN_FP_16) +@@ -999,6 +1006,11 @@ DEF_RVV_X2_VLMUL_EXT_OPS (vuint32m4_t, 0) + DEF_RVV_X2_VLMUL_EXT_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64) + DEF_RVV_X2_VLMUL_EXT_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64) + DEF_RVV_X2_VLMUL_EXT_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_64) ++DEF_RVV_X2_VLMUL_EXT_OPS (vbfloat16mf4_t, RVV_REQUIRE_ELEN_BF_16 | RVV_REQUIRE_MIN_VLEN_64) ++DEF_RVV_X2_VLMUL_EXT_OPS (vbfloat16mf2_t, RVV_REQUIRE_ELEN_BF_16) ++DEF_RVV_X2_VLMUL_EXT_OPS (vbfloat16m1_t, RVV_REQUIRE_ELEN_BF_16) ++DEF_RVV_X2_VLMUL_EXT_OPS (vbfloat16m2_t, RVV_REQUIRE_ELEN_BF_16) ++DEF_RVV_X2_VLMUL_EXT_OPS (vbfloat16m4_t, RVV_REQUIRE_ELEN_BF_16) + DEF_RVV_X2_VLMUL_EXT_OPS (vfloat16mf4_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64) + DEF_RVV_X2_VLMUL_EXT_OPS (vfloat16mf2_t, RVV_REQUIRE_ELEN_FP_16) + DEF_RVV_X2_VLMUL_EXT_OPS (vfloat16m1_t, RVV_REQUIRE_ELEN_FP_16) +@@ -1040,6 +1052,10 @@ DEF_RVV_X4_VLMUL_EXT_OPS (vuint32m1_t, 0) + DEF_RVV_X4_VLMUL_EXT_OPS (vuint32m2_t, 0) + DEF_RVV_X4_VLMUL_EXT_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64) + DEF_RVV_X4_VLMUL_EXT_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64) ++DEF_RVV_X4_VLMUL_EXT_OPS (vbfloat16mf4_t, RVV_REQUIRE_ELEN_BF_16 | RVV_REQUIRE_MIN_VLEN_64) ++DEF_RVV_X4_VLMUL_EXT_OPS (vbfloat16mf2_t, RVV_REQUIRE_ELEN_BF_16) ++DEF_RVV_X4_VLMUL_EXT_OPS (vbfloat16m1_t, RVV_REQUIRE_ELEN_BF_16) ++DEF_RVV_X4_VLMUL_EXT_OPS (vbfloat16m2_t, RVV_REQUIRE_ELEN_BF_16) + DEF_RVV_X4_VLMUL_EXT_OPS (vfloat16mf4_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64) + DEF_RVV_X4_VLMUL_EXT_OPS (vfloat16mf2_t, RVV_REQUIRE_ELEN_FP_16) + DEF_RVV_X4_VLMUL_EXT_OPS (vfloat16m1_t, RVV_REQUIRE_ELEN_FP_16) +@@ -1070,6 +1086,9 @@ DEF_RVV_X8_VLMUL_EXT_OPS (vuint16m1_t, 0) + DEF_RVV_X8_VLMUL_EXT_OPS (vuint32mf2_t, RVV_REQUIRE_MIN_VLEN_64) + DEF_RVV_X8_VLMUL_EXT_OPS (vuint32m1_t, 0) + DEF_RVV_X8_VLMUL_EXT_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64) ++DEF_RVV_X8_VLMUL_EXT_OPS (vbfloat16mf4_t, RVV_REQUIRE_ELEN_BF_16 | RVV_REQUIRE_MIN_VLEN_64) ++DEF_RVV_X8_VLMUL_EXT_OPS (vbfloat16mf2_t, RVV_REQUIRE_ELEN_BF_16) ++DEF_RVV_X8_VLMUL_EXT_OPS (vbfloat16m1_t, RVV_REQUIRE_ELEN_BF_16) + DEF_RVV_X8_VLMUL_EXT_OPS (vfloat16mf4_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64) + DEF_RVV_X8_VLMUL_EXT_OPS (vfloat16mf2_t, RVV_REQUIRE_ELEN_FP_16) + DEF_RVV_X8_VLMUL_EXT_OPS (vfloat16m1_t, RVV_REQUIRE_ELEN_FP_16) +@@ -1089,6 +1108,8 @@ DEF_RVV_X16_VLMUL_EXT_OPS (vuint8mf2_t, 0) + DEF_RVV_X16_VLMUL_EXT_OPS (vuint16mf4_t, RVV_REQUIRE_MIN_VLEN_64) + DEF_RVV_X16_VLMUL_EXT_OPS (vuint16mf2_t, 0) + DEF_RVV_X16_VLMUL_EXT_OPS (vuint32mf2_t, RVV_REQUIRE_MIN_VLEN_64) ++DEF_RVV_X16_VLMUL_EXT_OPS (vbfloat16mf4_t, RVV_REQUIRE_ELEN_BF_16 | RVV_REQUIRE_MIN_VLEN_64) ++DEF_RVV_X16_VLMUL_EXT_OPS (vbfloat16mf2_t, RVV_REQUIRE_ELEN_BF_16) + DEF_RVV_X16_VLMUL_EXT_OPS (vfloat16mf4_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64) + DEF_RVV_X16_VLMUL_EXT_OPS (vfloat16mf2_t, RVV_REQUIRE_ELEN_FP_16) + DEF_RVV_X16_VLMUL_EXT_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_MIN_VLEN_64) +@@ -1099,6 +1120,7 @@ DEF_RVV_X32_VLMUL_EXT_OPS (vint16mf4_t, RVV_REQUIRE_MIN_VLEN_64) + DEF_RVV_X32_VLMUL_EXT_OPS (vuint8mf8_t, RVV_REQUIRE_MIN_VLEN_64) + DEF_RVV_X32_VLMUL_EXT_OPS (vuint8mf4_t, 0) + DEF_RVV_X32_VLMUL_EXT_OPS (vuint16mf4_t, RVV_REQUIRE_MIN_VLEN_64) ++DEF_RVV_X32_VLMUL_EXT_OPS (vbfloat16mf4_t, RVV_REQUIRE_ELEN_BF_16 | RVV_REQUIRE_MIN_VLEN_64) + DEF_RVV_X32_VLMUL_EXT_OPS (vfloat16mf4_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64) + + DEF_RVV_X64_VLMUL_EXT_OPS (vint8mf8_t, RVV_REQUIRE_MIN_VLEN_64) +@@ -1112,6 +1134,7 @@ DEF_RVV_LMUL1_OPS (vuint8m1_t, 0) + DEF_RVV_LMUL1_OPS (vuint16m1_t, 0) + DEF_RVV_LMUL1_OPS (vuint32m1_t, 0) + DEF_RVV_LMUL1_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64) ++DEF_RVV_LMUL1_OPS (vbfloat16m1_t, RVV_REQUIRE_ELEN_BF_16) + DEF_RVV_LMUL1_OPS (vfloat16m1_t, RVV_REQUIRE_ELEN_FP_16) + DEF_RVV_LMUL1_OPS (vfloat32m1_t, RVV_REQUIRE_ELEN_FP_32) + DEF_RVV_LMUL1_OPS (vfloat64m1_t, RVV_REQUIRE_ELEN_FP_64) +@@ -1124,6 +1147,7 @@ DEF_RVV_LMUL2_OPS (vuint8m2_t, 0) + DEF_RVV_LMUL2_OPS (vuint16m2_t, 0) + DEF_RVV_LMUL2_OPS (vuint32m2_t, 0) + DEF_RVV_LMUL2_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64) ++DEF_RVV_LMUL2_OPS (vbfloat16m2_t, RVV_REQUIRE_ELEN_BF_16) + DEF_RVV_LMUL2_OPS (vfloat16m2_t, RVV_REQUIRE_ELEN_FP_16) + DEF_RVV_LMUL2_OPS (vfloat32m2_t, RVV_REQUIRE_ELEN_FP_32) + DEF_RVV_LMUL2_OPS (vfloat64m2_t, RVV_REQUIRE_ELEN_FP_64) +@@ -1137,6 +1161,7 @@ DEF_RVV_LMUL4_OPS (vuint16m4_t, 0) + DEF_RVV_LMUL4_OPS (vuint32m4_t, 0) + DEF_RVV_LMUL4_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_64) + DEF_RVV_LMUL4_OPS (vfloat16m4_t, RVV_REQUIRE_ELEN_FP_16) ++DEF_RVV_LMUL4_OPS (vbfloat16m4_t, RVV_REQUIRE_ELEN_BF_16) + DEF_RVV_LMUL4_OPS (vfloat32m4_t, RVV_REQUIRE_ELEN_FP_32) + DEF_RVV_LMUL4_OPS (vfloat64m4_t, RVV_REQUIRE_ELEN_FP_64) + +@@ -1312,6 +1337,31 @@ DEF_RVV_TUPLE_OPS (vint64m2x4_t, RVV_REQUIRE_ELEN_64) + DEF_RVV_TUPLE_OPS (vuint64m2x4_t, RVV_REQUIRE_ELEN_64) + DEF_RVV_TUPLE_OPS (vint64m4x2_t, RVV_REQUIRE_ELEN_64) + DEF_RVV_TUPLE_OPS (vuint64m4x2_t, RVV_REQUIRE_ELEN_64) ++DEF_RVV_TUPLE_OPS (vbfloat16mf4x2_t, RVV_REQUIRE_ELEN_BF_16 | RVV_REQUIRE_MIN_VLEN_64) ++DEF_RVV_TUPLE_OPS (vbfloat16mf4x3_t, RVV_REQUIRE_ELEN_BF_16 | RVV_REQUIRE_MIN_VLEN_64) ++DEF_RVV_TUPLE_OPS (vbfloat16mf4x4_t, RVV_REQUIRE_ELEN_BF_16 | RVV_REQUIRE_MIN_VLEN_64) ++DEF_RVV_TUPLE_OPS (vbfloat16mf4x5_t, RVV_REQUIRE_ELEN_BF_16 | RVV_REQUIRE_MIN_VLEN_64) ++DEF_RVV_TUPLE_OPS (vbfloat16mf4x6_t, RVV_REQUIRE_ELEN_BF_16 | RVV_REQUIRE_MIN_VLEN_64) ++DEF_RVV_TUPLE_OPS (vbfloat16mf4x7_t, RVV_REQUIRE_ELEN_BF_16 | RVV_REQUIRE_MIN_VLEN_64) ++DEF_RVV_TUPLE_OPS (vbfloat16mf4x8_t, RVV_REQUIRE_ELEN_BF_16 | RVV_REQUIRE_MIN_VLEN_64) ++DEF_RVV_TUPLE_OPS (vbfloat16mf2x2_t, RVV_REQUIRE_ELEN_BF_16) ++DEF_RVV_TUPLE_OPS (vbfloat16mf2x3_t, RVV_REQUIRE_ELEN_BF_16) ++DEF_RVV_TUPLE_OPS (vbfloat16mf2x4_t, RVV_REQUIRE_ELEN_BF_16) ++DEF_RVV_TUPLE_OPS (vbfloat16mf2x5_t, RVV_REQUIRE_ELEN_BF_16) ++DEF_RVV_TUPLE_OPS (vbfloat16mf2x6_t, RVV_REQUIRE_ELEN_BF_16) ++DEF_RVV_TUPLE_OPS (vbfloat16mf2x7_t, RVV_REQUIRE_ELEN_BF_16) ++DEF_RVV_TUPLE_OPS (vbfloat16mf2x8_t, RVV_REQUIRE_ELEN_BF_16) ++DEF_RVV_TUPLE_OPS (vbfloat16m1x2_t, RVV_REQUIRE_ELEN_BF_16) ++DEF_RVV_TUPLE_OPS (vbfloat16m1x3_t, RVV_REQUIRE_ELEN_BF_16) ++DEF_RVV_TUPLE_OPS (vbfloat16m1x4_t, RVV_REQUIRE_ELEN_BF_16) ++DEF_RVV_TUPLE_OPS (vbfloat16m1x5_t, RVV_REQUIRE_ELEN_BF_16) ++DEF_RVV_TUPLE_OPS (vbfloat16m1x6_t, RVV_REQUIRE_ELEN_BF_16) ++DEF_RVV_TUPLE_OPS (vbfloat16m1x7_t, RVV_REQUIRE_ELEN_BF_16) ++DEF_RVV_TUPLE_OPS (vbfloat16m1x8_t, RVV_REQUIRE_ELEN_BF_16) ++DEF_RVV_TUPLE_OPS (vbfloat16m2x2_t, RVV_REQUIRE_ELEN_BF_16) ++DEF_RVV_TUPLE_OPS (vbfloat16m2x3_t, RVV_REQUIRE_ELEN_BF_16) ++DEF_RVV_TUPLE_OPS (vbfloat16m2x4_t, RVV_REQUIRE_ELEN_BF_16) ++DEF_RVV_TUPLE_OPS (vbfloat16m4x2_t, RVV_REQUIRE_ELEN_BF_16) + DEF_RVV_TUPLE_OPS (vfloat16mf4x2_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64) + DEF_RVV_TUPLE_OPS (vfloat16mf4x3_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64) + DEF_RVV_TUPLE_OPS (vfloat16mf4x4_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64) +diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc +index c08d87a2680..2d7e62deb08 100644 +--- a/gcc/config/riscv/riscv-vector-builtins.cc ++++ b/gcc/config/riscv/riscv-vector-builtins.cc +@@ -2808,7 +2808,8 @@ static CONSTEXPR const function_type_info function_types[] = { + VECTOR, MASK, SIGNED, UNSIGNED, EEW8_INDEX, EEW16_INDEX, EEW32_INDEX, \ + EEW64_INDEX, SHIFT, DOUBLE_TRUNC, QUAD_TRUNC, OCT_TRUNC, \ + DOUBLE_TRUNC_SCALAR, DOUBLE_TRUNC_SIGNED, DOUBLE_TRUNC_UNSIGNED, \ +- DOUBLE_TRUNC_UNSIGNED_SCALAR, DOUBLE_TRUNC_FLOAT, FLOAT, LMUL1, WLMUL1, \ ++ DOUBLE_TRUNC_UNSIGNED_SCALAR, DOUBLE_TRUNC_BFLOAT_SCALAR, \ ++ DOUBLE_TRUNC_BFLOAT, DOUBLE_TRUNC_FLOAT, FLOAT, LMUL1, WLMUL1, \ + EEW8_INTERPRET, EEW16_INTERPRET, EEW32_INTERPRET, EEW64_INTERPRET, \ + BOOL1_INTERPRET, BOOL2_INTERPRET, BOOL4_INTERPRET, BOOL8_INTERPRET, \ + BOOL16_INTERPRET, BOOL32_INTERPRET, BOOL64_INTERPRET, \ +@@ -2845,6 +2846,8 @@ static CONSTEXPR const function_type_info function_types[] = { + VECTOR_TYPE_##DOUBLE_TRUNC_SIGNED, \ + VECTOR_TYPE_##DOUBLE_TRUNC_UNSIGNED, \ + VECTOR_TYPE_##DOUBLE_TRUNC_UNSIGNED_SCALAR, \ ++ VECTOR_TYPE_##DOUBLE_TRUNC_BFLOAT_SCALAR, \ ++ VECTOR_TYPE_##DOUBLE_TRUNC_BFLOAT, \ + VECTOR_TYPE_##DOUBLE_TRUNC_FLOAT, \ + VECTOR_TYPE_##FLOAT, \ + VECTOR_TYPE_##LMUL1, \ +@@ -3284,6 +3287,8 @@ check_required_extensions (const function_instance &instance) + + uint64_t riscv_isa_flags = 0; + ++ if (TARGET_VECTOR_ELEN_BF_16) ++ riscv_isa_flags |= RVV_REQUIRE_ELEN_BF_16; + if (TARGET_VECTOR_ELEN_FP_16) + riscv_isa_flags |= RVV_REQUIRE_ELEN_FP_16; + if (TARGET_VECTOR_ELEN_FP_32) +diff --git a/gcc/config/riscv/riscv-vector-builtins.def b/gcc/config/riscv/riscv-vector-builtins.def +index 784b54c81a4..7ff5a5acb08 100644 +--- a/gcc/config/riscv/riscv-vector-builtins.def ++++ b/gcc/config/riscv/riscv-vector-builtins.def +@@ -72,7 +72,8 @@ along with GCC; see the file COPYING3. If not see + VECTOR, MASK, SIGNED, UNSIGNED, EEW8_INDEX, EEW16_INDEX, EEW32_INDEX, \ + EEW64_INDEX, SHIFT, DOUBLE_TRUNC, QUAD_TRUNC, OCT_TRUNC, \ + DOUBLE_TRUNC_SCALAR, DOUBLE_TRUNC_SIGNED, DOUBLE_TRUNC_UNSIGNED, \ +- DOUBLE_TRUNC_UNSIGNED_SCALAR, DOUBLE_TRUNC_FLOAT, FLOAT, LMUL1, WLMUL1, \ ++ DOUBLE_TRUNC_UNSIGNED_SCALAR, DOUBLE_TRUNC_BFLOAT_SCALAR, \ ++ DOUBLE_TRUNC_BFLOAT, DOUBLE_TRUNC_FLOAT, FLOAT, LMUL1, WLMUL1, \ + EEW8_INTERPRET, EEW16_INTERPRET, EEW32_INTERPRET, EEW64_INTERPRET, \ + BOOL1_INTERPRET, BOOL2_INTERPRET, BOOL4_INTERPRET, BOOL8_INTERPRET, \ + BOOL16_INTERPRET, BOOL32_INTERPRET, BOOL64_INTERPRET, \ +@@ -436,6 +437,56 @@ DEF_RVV_TYPE (vint64m8_t, 15, __rvv_int64m8_t, int64, RVVM8DI, _i64m8, _i64, + DEF_RVV_TYPE (vuint64m8_t, 16, __rvv_uint64m8_t, uint64, RVVM8DI, _u64m8, _u64, + _e64m8) + ++/* Enabled if TARGET_VECTOR_ELEN_BF_16 && (TARGET_ZVFBFMIN or TARGET_ZVFBFWMA). */ ++/* LMUL = 1/4. */ ++DEF_RVV_TYPE (vbfloat16mf4_t, 19, __rvv_bfloat16mf4_t, bfloat16, RVVMF4BF, _bf16mf4, ++ _bf16, _e16mf4) ++/* Define tuple types for SEW = 16, LMUL = MF4. */ ++DEF_RVV_TUPLE_TYPE (vbfloat16mf4x2_t, 21, __rvv_bfloat16mf4x2_t, vbfloat16mf4_t, bfloat16, 2, _bf16mf4x2) ++DEF_RVV_TUPLE_TYPE (vbfloat16mf4x3_t, 21, __rvv_bfloat16mf4x3_t, vbfloat16mf4_t, bfloat16, 3, _bf16mf4x3) ++DEF_RVV_TUPLE_TYPE (vbfloat16mf4x4_t, 21, __rvv_bfloat16mf4x4_t, vbfloat16mf4_t, bfloat16, 4, _bf16mf4x4) ++DEF_RVV_TUPLE_TYPE (vbfloat16mf4x5_t, 21, __rvv_bfloat16mf4x5_t, vbfloat16mf4_t, bfloat16, 5, _bf16mf4x5) ++DEF_RVV_TUPLE_TYPE (vbfloat16mf4x6_t, 21, __rvv_bfloat16mf4x6_t, vbfloat16mf4_t, bfloat16, 6, _bf16mf4x6) ++DEF_RVV_TUPLE_TYPE (vbfloat16mf4x7_t, 21, __rvv_bfloat16mf4x7_t, vbfloat16mf4_t, bfloat16, 7, _bf16mf4x7) ++DEF_RVV_TUPLE_TYPE (vbfloat16mf4x8_t, 21, __rvv_bfloat16mf4x8_t, vbfloat16mf4_t, bfloat16, 8, _bf16mf4x8) ++/* LMUL = 1/2. */ ++DEF_RVV_TYPE (vbfloat16mf2_t, 19, __rvv_bfloat16mf2_t, bfloat16, RVVMF2BF, _bf16mf2, ++ _bf16, _e16mf2) ++/* Define tuple types for SEW = 16, LMUL = MF2. */ ++DEF_RVV_TUPLE_TYPE (vbfloat16mf2x2_t, 21, __rvv_bfloat16mf2x2_t, vbfloat16mf2_t, bfloat16, 2, _bf16mf2x2) ++DEF_RVV_TUPLE_TYPE (vbfloat16mf2x3_t, 21, __rvv_bfloat16mf2x3_t, vbfloat16mf2_t, bfloat16, 3, _bf16mf2x3) ++DEF_RVV_TUPLE_TYPE (vbfloat16mf2x4_t, 21, __rvv_bfloat16mf2x4_t, vbfloat16mf2_t, bfloat16, 4, _bf16mf2x4) ++DEF_RVV_TUPLE_TYPE (vbfloat16mf2x5_t, 21, __rvv_bfloat16mf2x5_t, vbfloat16mf2_t, bfloat16, 5, _bf16mf2x5) ++DEF_RVV_TUPLE_TYPE (vbfloat16mf2x6_t, 21, __rvv_bfloat16mf2x6_t, vbfloat16mf2_t, bfloat16, 6, _bf16mf2x6) ++DEF_RVV_TUPLE_TYPE (vbfloat16mf2x7_t, 21, __rvv_bfloat16mf2x7_t, vbfloat16mf2_t, bfloat16, 7, _bf16mf2x7) ++DEF_RVV_TUPLE_TYPE (vbfloat16mf2x8_t, 21, __rvv_bfloat16mf2x8_t, vbfloat16mf2_t, bfloat16, 8, _bf16mf2x8) ++/* LMUL = 1. */ ++DEF_RVV_TYPE (vbfloat16m1_t, 18, __rvv_bfloat16m1_t, bfloat16, RVVM1BF, _bf16m1, ++ _bf16, _e16m1) ++/* Define tuple types for SEW = 16, LMUL = M1. */ ++DEF_RVV_TUPLE_TYPE (vbfloat16m1x2_t, 20, __rvv_bfloat16m1x2_t, vbfloat16m1_t, bfloat16, 2, _bf16m1x2) ++DEF_RVV_TUPLE_TYPE (vbfloat16m1x3_t, 20, __rvv_bfloat16m1x3_t, vbfloat16m1_t, bfloat16, 3, _bf16m1x3) ++DEF_RVV_TUPLE_TYPE (vbfloat16m1x4_t, 20, __rvv_bfloat16m1x4_t, vbfloat16m1_t, bfloat16, 4, _bf16m1x4) ++DEF_RVV_TUPLE_TYPE (vbfloat16m1x5_t, 20, __rvv_bfloat16m1x5_t, vbfloat16m1_t, bfloat16, 5, _bf16m1x5) ++DEF_RVV_TUPLE_TYPE (vbfloat16m1x6_t, 20, __rvv_bfloat16m1x6_t, vbfloat16m1_t, bfloat16, 6, _bf16m1x6) ++DEF_RVV_TUPLE_TYPE (vbfloat16m1x7_t, 20, __rvv_bfloat16m1x7_t, vbfloat16m1_t, bfloat16, 7, _bf16m1x7) ++DEF_RVV_TUPLE_TYPE (vbfloat16m1x8_t, 20, __rvv_bfloat16m1x8_t, vbfloat16m1_t, bfloat16, 8, _bf16m1x8) ++/* LMUL = 2. */ ++DEF_RVV_TYPE (vbfloat16m2_t, 18, __rvv_bfloat16m2_t, bfloat16, RVVM2BF, _bf16m2, ++ _bf16, _e16m2) ++/* Define tuple types for SEW = 16, LMUL = M2. */ ++DEF_RVV_TUPLE_TYPE (vbfloat16m2x2_t, 20, __rvv_bfloat16m2x2_t, vbfloat16m2_t, bfloat16, 2, _bf16m2x2) ++DEF_RVV_TUPLE_TYPE (vbfloat16m2x3_t, 20, __rvv_bfloat16m2x3_t, vbfloat16m2_t, bfloat16, 3, _bf16m2x3) ++DEF_RVV_TUPLE_TYPE (vbfloat16m2x4_t, 20, __rvv_bfloat16m2x4_t, vbfloat16m2_t, bfloat16, 4, _bf16m2x4) ++/* LMUL = 4. */ ++DEF_RVV_TYPE (vbfloat16m4_t, 18, __rvv_bfloat16m4_t, bfloat16, RVVM4BF, _bf16m4, ++ _bf16, _e16m4) ++/* Define tuple types for SEW = 16, LMUL = M4. */ ++DEF_RVV_TUPLE_TYPE (vbfloat16m4x2_t, 20, __rvv_bfloat16m4x2_t, vbfloat16m4_t, bfloat16, 2, _bf16m4x2) ++/* LMUL = 8. */ ++DEF_RVV_TYPE (vbfloat16m8_t, 18, __rvv_bfloat16m8_t, bfloat16, RVVM8BF, _bf16m8, ++ _bf16, _e16m8) ++ + /* Enabled if TARGET_VECTOR_ELEN_FP_16 && (TARGET_ZVFH or TARGET_ZVFHMIN). */ + /* LMUL = 1/4. */ + DEF_RVV_TYPE (vfloat16mf4_t, 18, __rvv_float16mf4_t, float16, RVVMF4HF, _f16mf4, +@@ -630,6 +681,8 @@ DEF_RVV_BASE_TYPE (double_trunc_scalar, get_scalar_type (type_idx)) + DEF_RVV_BASE_TYPE (double_trunc_signed_vector, get_vector_type (type_idx)) + DEF_RVV_BASE_TYPE (double_trunc_unsigned_vector, get_vector_type (type_idx)) + DEF_RVV_BASE_TYPE (double_trunc_unsigned_scalar, get_scalar_type (type_idx)) ++DEF_RVV_BASE_TYPE (double_trunc_bfloat_scalar, get_scalar_type (type_idx)) ++DEF_RVV_BASE_TYPE (double_trunc_bfloat_vector, get_vector_type (type_idx)) + DEF_RVV_BASE_TYPE (double_trunc_float_vector, get_vector_type (type_idx)) + DEF_RVV_BASE_TYPE (float_vector, get_vector_type (type_idx)) + DEF_RVV_BASE_TYPE (lmul1_vector, get_vector_type (type_idx)) +diff --git a/gcc/config/riscv/riscv-vector-builtins.h b/gcc/config/riscv/riscv-vector-builtins.h +index 05d18ae1322..56dbe2cf0e2 100644 +--- a/gcc/config/riscv/riscv-vector-builtins.h ++++ b/gcc/config/riscv/riscv-vector-builtins.h +@@ -109,6 +109,7 @@ static const unsigned int CP_WRITE_CSR = 1U << 5; + #define RVV_REQUIRE_FULL_V (1 << 4) /* Require Full 'V' extension. */ + #define RVV_REQUIRE_MIN_VLEN_64 (1 << 5) /* Require TARGET_MIN_VLEN >= 64. */ + #define RVV_REQUIRE_ELEN_FP_16 (1 << 6) /* Require FP ELEN >= 32. */ ++#define RVV_REQUIRE_ELEN_BF_16 (1 << 7) /* Require BF16. */ + + /* Enumerates the required extensions. */ + enum required_ext +diff --git a/gcc/config/riscv/riscv-vector-switch.def b/gcc/config/riscv/riscv-vector-switch.def +index 452283b7416..de72e415fe8 100644 +--- a/gcc/config/riscv/riscv-vector-switch.def ++++ b/gcc/config/riscv/riscv-vector-switch.def +@@ -43,6 +43,7 @@ Encode SEW and LMUL into data types. + |DF |RVVM1DF|RVVM2DF|RVVM4DF|RVVM8DF|N/A |N/A |N/A | + |SF |RVVM1SF|RVVM2SF|RVVM4SF|RVVM8SF|RVVMF2SF|N/A |N/A | + |HF |RVVM1HF|RVVM2HF|RVVM4HF|RVVM8HF|RVVMF2HF|RVVMF4HF|N/A | ++ |BF |RVVM1BF|RVVM2BF|RVVM4BF|RVVM8BF|RVVMF2BF|RVVMF4BF|N/A | + + There are the following data types for ELEN = 32. + +@@ -52,6 +53,7 @@ There are the following data types for ELEN = 32. + |QI |RVVM1QI|RVVM2QI|RVVM4QI|RVVM8QI|RVVMF2QI|RVVMF4QI|N/A | + |SF |RVVM1SF|RVVM2SF|RVVM4SF|RVVM8SF|N/A |N/A |N/A | + |HF |RVVM1HF|RVVM2HF|RVVM4HF|RVVM8HF|RVVMF2HF|N/A |N/A | ++ |BF |RVVM1BF|RVVM2BF|RVVM4BF|RVVM8BF|RVVMF2BF|N/A |N/A | + + Encode the ratio of SEW/LMUL into the mask types. + There are the following mask types. +@@ -93,6 +95,14 @@ ENTRY (RVVM1HI, true, LMUL_1, 16) + ENTRY (RVVMF2HI, !TARGET_XTHEADVECTOR, LMUL_F2, 32) + ENTRY (RVVMF4HI, TARGET_MIN_VLEN > 32 && !TARGET_XTHEADVECTOR, LMUL_F4, 64) + ++/* Disable modes if TARGET_MIN_VLEN == 32 or !TARGET_VECTOR_ELEN_BF_16. */ ++ENTRY (RVVM8BF, TARGET_VECTOR_ELEN_BF_16, LMUL_8, 2) ++ENTRY (RVVM4BF, TARGET_VECTOR_ELEN_BF_16, LMUL_4, 4) ++ENTRY (RVVM2BF, TARGET_VECTOR_ELEN_BF_16, LMUL_2, 8) ++ENTRY (RVVM1BF, TARGET_VECTOR_ELEN_BF_16, LMUL_1, 16) ++ENTRY (RVVMF2BF, TARGET_VECTOR_ELEN_BF_16, LMUL_F2, 32) ++ENTRY (RVVMF4BF, TARGET_VECTOR_ELEN_BF_16 && TARGET_MIN_VLEN > 32, LMUL_F4, 64) ++ + /* Disable modes if TARGET_MIN_VLEN == 32 or !TARGET_VECTOR_ELEN_FP_16. */ + ENTRY (RVVM8HF, TARGET_VECTOR_ELEN_FP_16, LMUL_8, 2) + ENTRY (RVVM4HF, TARGET_VECTOR_ELEN_FP_16, LMUL_4, 4) +@@ -198,6 +208,32 @@ TUPLE_ENTRY (RVVM1x2HI, true, RVVM1HI, 2, LMUL_1, 16) + TUPLE_ENTRY (RVVMF2x2HI, !TARGET_XTHEADVECTOR, RVVMF2HI, 2, LMUL_F2, 32) + TUPLE_ENTRY (RVVMF4x2HI, TARGET_MIN_VLEN > 32 && !TARGET_XTHEADVECTOR, RVVMF4HI, 2, LMUL_F4, 64) + ++TUPLE_ENTRY (RVVM1x8BF, TARGET_VECTOR_ELEN_BF_16, RVVM1BF, 8, LMUL_1, 16) ++TUPLE_ENTRY (RVVMF2x8BF, TARGET_VECTOR_ELEN_BF_16, RVVMF2BF, 8, LMUL_F2, 32) ++TUPLE_ENTRY (RVVMF4x8BF, TARGET_VECTOR_ELEN_BF_16 && TARGET_MIN_VLEN > 32, RVVMF4BF, 8, LMUL_F4, 64) ++TUPLE_ENTRY (RVVM1x7BF, TARGET_VECTOR_ELEN_BF_16, RVVM1BF, 7, LMUL_1, 16) ++TUPLE_ENTRY (RVVMF2x7BF, TARGET_VECTOR_ELEN_BF_16, RVVMF2BF, 7, LMUL_F2, 32) ++TUPLE_ENTRY (RVVMF4x7BF, TARGET_VECTOR_ELEN_BF_16 && TARGET_MIN_VLEN > 32, RVVMF4BF, 7, LMUL_F4, 64) ++TUPLE_ENTRY (RVVM1x6BF, TARGET_VECTOR_ELEN_BF_16, RVVM1BF, 6, LMUL_1, 16) ++TUPLE_ENTRY (RVVMF2x6BF, TARGET_VECTOR_ELEN_BF_16, RVVMF2BF, 6, LMUL_F2, 32) ++TUPLE_ENTRY (RVVMF4x6BF, TARGET_VECTOR_ELEN_BF_16 && TARGET_MIN_VLEN > 32, RVVMF4BF, 6, LMUL_F4, 64) ++TUPLE_ENTRY (RVVM1x5BF, TARGET_VECTOR_ELEN_BF_16, RVVM1BF, 5, LMUL_1, 16) ++TUPLE_ENTRY (RVVMF2x5BF, TARGET_VECTOR_ELEN_BF_16, RVVMF2BF, 5, LMUL_F2, 32) ++TUPLE_ENTRY (RVVMF4x5BF, TARGET_VECTOR_ELEN_BF_16 && TARGET_MIN_VLEN > 32, RVVMF4BF, 5, LMUL_F4, 64) ++TUPLE_ENTRY (RVVM2x4BF, TARGET_VECTOR_ELEN_BF_16, RVVM2BF, 4, LMUL_2, 8) ++TUPLE_ENTRY (RVVM1x4BF, TARGET_VECTOR_ELEN_BF_16, RVVM1BF, 4, LMUL_1, 16) ++TUPLE_ENTRY (RVVMF2x4BF, TARGET_VECTOR_ELEN_BF_16, RVVMF2BF, 4, LMUL_F2, 32) ++TUPLE_ENTRY (RVVMF4x4BF, TARGET_VECTOR_ELEN_BF_16 && TARGET_MIN_VLEN > 32, RVVMF4BF, 4, LMUL_F4, 64) ++TUPLE_ENTRY (RVVM2x3BF, TARGET_VECTOR_ELEN_BF_16, RVVM2BF, 3, LMUL_2, 8) ++TUPLE_ENTRY (RVVM1x3BF, TARGET_VECTOR_ELEN_BF_16, RVVM1BF, 3, LMUL_1, 16) ++TUPLE_ENTRY (RVVMF2x3BF, TARGET_VECTOR_ELEN_BF_16, RVVMF2BF, 3, LMUL_F2, 32) ++TUPLE_ENTRY (RVVMF4x3BF, TARGET_VECTOR_ELEN_BF_16 && TARGET_MIN_VLEN > 32, RVVMF4BF, 3, LMUL_F4, 64) ++TUPLE_ENTRY (RVVM4x2BF, TARGET_VECTOR_ELEN_BF_16, RVVM4BF, 2, LMUL_4, 4) ++TUPLE_ENTRY (RVVM2x2BF, TARGET_VECTOR_ELEN_BF_16, RVVM2BF, 2, LMUL_2, 8) ++TUPLE_ENTRY (RVVM1x2BF, TARGET_VECTOR_ELEN_BF_16, RVVM1BF, 2, LMUL_1, 16) ++TUPLE_ENTRY (RVVMF2x2BF, TARGET_VECTOR_ELEN_BF_16, RVVMF2BF, 2, LMUL_F2, 32) ++TUPLE_ENTRY (RVVMF4x2BF, TARGET_VECTOR_ELEN_BF_16 && TARGET_MIN_VLEN > 32, RVVMF4BF, 2, LMUL_F4, 64) ++ + TUPLE_ENTRY (RVVM1x8HF, TARGET_VECTOR_ELEN_FP_16, RVVM1HF, 8, LMUL_1, 16) + TUPLE_ENTRY (RVVMF2x8HF, TARGET_VECTOR_ELEN_FP_16 && !TARGET_XTHEADVECTOR, RVVMF2HF, 8, LMUL_F2, 32) + TUPLE_ENTRY (RVVMF4x8HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32 && !TARGET_XTHEADVECTOR, RVVMF4HF, 8, LMUL_F4, 64) +-- +2.47.3 + diff --git a/1008-RISC-V-Add-md-files-for-vector-BFloat16.patch b/1008-RISC-V-Add-md-files-for-vector-BFloat16.patch new file mode 100644 index 0000000..28482b7 --- /dev/null +++ b/1008-RISC-V-Add-md-files-for-vector-BFloat16.patch @@ -0,0 +1,935 @@ +From c642ca824a49c16750d5da859e51a6088be3feb5 Mon Sep 17 00:00:00 2001 +From: Feng Wang +Date: Tue, 18 Jun 2024 06:13:35 +0000 +Subject: [PATCH 1008/1087] RISC-V: Add md files for vector BFloat16 + +commit 9f521632dd9ce71ce28ff1da9c161f76bc20fe3e upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +V3: Add Bfloat16 vector insn in generic-vector-ooo.md +v2: Rebase +Accroding to the BFloat16 spec, some vector iterators and new pattern +are added in md files. + +Signed-off-by: Feng Wang +gcc/ChangeLog: + + * config/riscv/generic-vector-ooo.md: Add def_insn_reservation for vector BFloat16. + * config/riscv/riscv.md: Add new insn name for vector BFloat16. + * config/riscv/vector-iterators.md: Add some iterators for vector BFloat16. + * config/riscv/vector.md: Add some attribute for vector BFloat16. + * config/riscv/vector-bfloat16.md: New file. Add insn pattern vector BFloat16. +--- + gcc/config/riscv/generic-vector-ooo.md | 4 +- + gcc/config/riscv/riscv.md | 13 +- + gcc/config/riscv/vector-bfloat16.md | 135 ++++++++++++++++++++ + gcc/config/riscv/vector-iterators.md | 169 ++++++++++++++++++++++++- + gcc/config/riscv/vector.md | 103 +++++++++++++-- + 5 files changed, 407 insertions(+), 17 deletions(-) + create mode 100644 gcc/config/riscv/vector-bfloat16.md + +diff --git a/gcc/config/riscv/generic-vector-ooo.md b/gcc/config/riscv/generic-vector-ooo.md +index 96cb1a0be29..6c1ef9d7470 100644 +--- a/gcc/config/riscv/generic-vector-ooo.md ++++ b/gcc/config/riscv/generic-vector-ooo.md +@@ -53,7 +53,7 @@ + (define_insn_reservation "vec_fcmp" 3 + (eq_attr "type" "vfrecp,vfminmax,vfcmp,vfsgnj,vfclass,vfcvtitof,\ + vfcvtftoi,vfwcvtitof,vfwcvtftoi,vfwcvtftof,vfncvtitof,\ +- vfncvtftoi,vfncvtftof") ++ vfncvtftoi,vfncvtftof,vfncvtbf16,vfwcvtbf16") + "vxu_ooo_issue,vxu_ooo_alu") + + ;; Vector integer multiplication. +@@ -69,7 +69,7 @@ + + ;; Vector float multiplication and FMA. + (define_insn_reservation "vec_fmul" 6 +- (eq_attr "type" "vfmul,vfwmul,vfmuladd,vfwmuladd") ++ (eq_attr "type" "vfmul,vfwmul,vfmuladd,vfwmuladd,vfwmaccbf16") + "vxu_ooo_issue,vxu_ooo_alu") + + ;; Vector crypto, assumed to be a generic operation for now. +diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md +index 5f4afc4b127..d2764a0409a 100644 +--- a/gcc/config/riscv/riscv.md ++++ b/gcc/config/riscv/riscv.md +@@ -204,6 +204,7 @@ + RVVMF64BI,RVVMF32BI,RVVMF16BI,RVVMF8BI,RVVMF4BI,RVVMF2BI,RVVM1BI, + RVVM8QI,RVVM4QI,RVVM2QI,RVVM1QI,RVVMF2QI,RVVMF4QI,RVVMF8QI, + RVVM8HI,RVVM4HI,RVVM2HI,RVVM1HI,RVVMF2HI,RVVMF4HI, ++ RVVM8BF,RVVM4BF,RVVM2BF,RVVM1BF,RVVMF2BF,RVVMF4BF, + RVVM8HF,RVVM4HF,RVVM2HF,RVVM1HF,RVVMF2HF,RVVMF4HF, + RVVM8SI,RVVM4SI,RVVM2SI,RVVM1SI,RVVMF2SI, + RVVM8SF,RVVM4SF,RVVM2SF,RVVM1SF,RVVMF2SF, +@@ -223,6 +224,11 @@ + RVVM2x4HI,RVVM1x4HI,RVVMF2x4HI,RVVMF4x4HI, + RVVM2x3HI,RVVM1x3HI,RVVMF2x3HI,RVVMF4x3HI, + RVVM4x2HI,RVVM2x2HI,RVVM1x2HI,RVVMF2x2HI,RVVMF4x2HI, ++ RVVM1x8BF,RVVMF2x8BF,RVVMF4x8BF,RVVM1x7BF,RVVMF2x7BF, ++ RVVMF4x7BF,RVVM1x6BF,RVVMF2x6BF,RVVMF4x6BF,RVVM1x5BF, ++ RVVMF2x5BF,RVVMF4x5BF,RVVM2x4BF,RVVM1x4BF,RVVMF2x4BF, ++ RVVMF4x4BF,RVVM2x3BF,RVVM1x3BF,RVVMF2x3BF,RVVMF4x3BF, ++ RVVM4x2BF,RVVM2x2BF,RVVM1x2BF,RVVMF2x2BF,RVVMF4x2BF, + RVVM1x8HF,RVVMF2x8HF,RVVMF4x8HF,RVVM1x7HF,RVVMF2x7HF, + RVVMF4x7HF,RVVM1x6HF,RVVMF2x6HF,RVVMF4x6HF,RVVM1x5HF, + RVVMF2x5HF,RVVMF4x5HF,RVVM2x4HF,RVVM1x4HF,RVVMF2x4HF, +@@ -466,6 +472,10 @@ + ;; vsm4r crypto vector SM4 Rounds instructions + ;; vsm3me crypto vector SM3 Message Expansion instructions + ;; vsm3c crypto vector SM3 Compression instructions ++;; 18.Vector BF16 instrctions ++;; vfncvtbf16 vector narrowing single floating-point to brain floating-point instruction ++;; vfwcvtbf16 vector widening brain floating-point to single floating-point instruction ++;; vfwmaccbf16 vector BF16 widening multiply-accumulate + (define_attr "type" + "unknown,branch,jump,jalr,ret,call,load,fpload,store,fpstore, + mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul, +@@ -487,7 +497,7 @@ + vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down, + vgather,vcompress,vmov,vector,vandn,vbrev,vbrev8,vrev8,vclz,vctz,vcpop,vrol,vror,vwsll, + vclmul,vclmulh,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,vaeskf1,vaeskf2,vaesz, +- vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c" ++ vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c,vfncvtbf16,vfwcvtbf16,vfwmaccbf16" + (cond [(eq_attr "got" "load") (const_string "load") + + ;; If a doubleword move uses these expensive instructions, +@@ -3836,6 +3846,7 @@ + (include "generic-ooo.md") + (include "vector.md") + (include "vector-crypto.md") ++(include "vector-bfloat16.md") + (include "zicond.md") + (include "sfb.md") + (include "zc.md") +diff --git a/gcc/config/riscv/vector-bfloat16.md b/gcc/config/riscv/vector-bfloat16.md +new file mode 100644 +index 00000000000..562aa8ee5ed +--- /dev/null ++++ b/gcc/config/riscv/vector-bfloat16.md +@@ -0,0 +1,135 @@ ++;; Machine description for RISC-V bfloat16 extensions. ++;; Copyright (C) 2024 Free Software Foundation, Inc. ++ ++;; This file is part of GCC. ++ ++;; GCC is free software; you can redistribute it and/or modify ++;; it under the terms of the GNU General Public License as published by ++;; the Free Software Foundation; either version 3, or (at your option) ++;; any later version. ++ ++;; GCC is distributed in the hope that it will be useful, ++;; but WITHOUT ANY WARRANTY; without even the implied warranty of ++;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++;; GNU General Public License for more details. ++ ++;; You should have received a copy of the GNU General Public License ++;; along with GCC; see the file COPYING3. If not see ++;; . ++ ++(define_mode_iterator VWEXTF_ZVFBF [ ++ (RVVM8SF "TARGET_VECTOR_ELEN_BF_16 && TARGET_VECTOR_ELEN_FP_32") ++ (RVVM4SF "TARGET_VECTOR_ELEN_BF_16 && TARGET_VECTOR_ELEN_FP_32") ++ (RVVM2SF "TARGET_VECTOR_ELEN_BF_16 && TARGET_VECTOR_ELEN_FP_32") ++ (RVVM1SF "TARGET_VECTOR_ELEN_BF_16 && TARGET_VECTOR_ELEN_FP_32") ++ (RVVMF2SF "TARGET_VECTOR_ELEN_BF_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") ++]) ++ ++(define_mode_attr V_FP32TOBF16_TRUNC [ ++ (RVVM8SF "RVVM4BF") (RVVM4SF "RVVM2BF") (RVVM2SF "RVVM1BF") (RVVM1SF "RVVMF2BF") (RVVMF2SF "RVVMF4BF") ++]) ++ ++(define_mode_attr VF32_SUBEL [ ++ (RVVM8SF "BF") (RVVM4SF "BF") (RVVM2SF "BF") (RVVM1SF "BF") (RVVMF2SF "BF")]) ++ ++;; Zvfbfmin extension ++ ++(define_insn "@pred_trunc_to_bf16" ++ [(set (match_operand: 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr") ++ (if_then_else: ++ (unspec: ++ [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1") ++ (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK") ++ (match_operand 5 "const_int_operand" " i, i, i, i, i, i") ++ (match_operand 6 "const_int_operand" " i, i, i, i, i, i") ++ (match_operand 7 "const_int_operand" " i, i, i, i, i, i") ++ (match_operand 8 "const_int_operand" " i, i, i, i, i, i") ++ (reg:SI VL_REGNUM) ++ (reg:SI VTYPE_REGNUM) ++ (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) ++ (float_truncate: ++ (match_operand:VWEXTF_ZVFBF 3 "register_operand" " 0, 0, 0, 0, vr, vr")) ++ (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))] ++ "TARGET_ZVFBFMIN" ++ "vfncvtbf16.f.f.w\t%0,%3%p1" ++ [(set_attr "type" "vfncvtbf16") ++ (set_attr "mode" "") ++ (set (attr "frm_mode") ++ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))]) ++ ++(define_insn "@pred_extend_bf16_to_" ++ [(set (match_operand:VWEXTF_ZVFBF 0 "register_operand" "=&vr, &vr") ++ (if_then_else:VWEXTF_ZVFBF ++ (unspec: ++ [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") ++ (match_operand 4 "vector_length_operand" " rK, rK") ++ (match_operand 5 "const_int_operand" " i, i") ++ (match_operand 6 "const_int_operand" " i, i") ++ (match_operand 7 "const_int_operand" " i, i") ++ (reg:SI VL_REGNUM) ++ (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) ++ (float_extend:VWEXTF_ZVFBF ++ (match_operand: 3 "register_operand" " vr, vr")) ++ (match_operand:VWEXTF_ZVFBF 2 "vector_merge_operand" " vu, 0")))] ++ "TARGET_ZVFBFMIN" ++ "vfwcvtbf16.f.f.v\t%0,%3%p1" ++ [(set_attr "type" "vfwcvtbf16") ++ (set_attr "mode" "")]) ++ ++ ++(define_insn "@pred_widen_bf16_mul_" ++ [(set (match_operand:VWEXTF_ZVFBF 0 "register_operand" "=&vr") ++ (if_then_else:VWEXTF_ZVFBF ++ (unspec: ++ [(match_operand: 1 "vector_mask_operand" "vmWc1") ++ (match_operand 5 "vector_length_operand" " rK") ++ (match_operand 6 "const_int_operand" " i") ++ (match_operand 7 "const_int_operand" " i") ++ (match_operand 8 "const_int_operand" " i") ++ (match_operand 9 "const_int_operand" " i") ++ (reg:SI VL_REGNUM) ++ (reg:SI VTYPE_REGNUM) ++ (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) ++ (plus:VWEXTF_ZVFBF ++ (mult:VWEXTF_ZVFBF ++ (float_extend:VWEXTF_ZVFBF ++ (match_operand: 3 "register_operand" " vr")) ++ (float_extend:VWEXTF_ZVFBF ++ (match_operand: 4 "register_operand" " vr"))) ++ (match_operand:VWEXTF_ZVFBF 2 "register_operand" " 0")) ++ (match_dup 2)))] ++ "TARGET_ZVFBFWMA" ++ "vfwmaccbf16.vv\t%0,%3,%4%p1" ++ [(set_attr "type" "vfwmaccbf16") ++ (set_attr "mode" "") ++ (set (attr "frm_mode") ++ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))]) ++ ++(define_insn "@pred_widen_bf16_mul__scalar" ++ [(set (match_operand:VWEXTF_ZVFBF 0 "register_operand" "=&vr") ++ (if_then_else:VWEXTF_ZVFBF ++ (unspec: ++ [(match_operand: 1 "vector_mask_operand" "vmWc1") ++ (match_operand 5 "vector_length_operand" " rK") ++ (match_operand 6 "const_int_operand" " i") ++ (match_operand 7 "const_int_operand" " i") ++ (match_operand 8 "const_int_operand" " i") ++ (match_operand 9 "const_int_operand" " i") ++ (reg:SI VL_REGNUM) ++ (reg:SI VTYPE_REGNUM) ++ (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) ++ (plus:VWEXTF_ZVFBF ++ (mult:VWEXTF_ZVFBF ++ (float_extend:VWEXTF_ZVFBF ++ (vec_duplicate: ++ (match_operand: 3 "register_operand" " f"))) ++ (float_extend:VWEXTF_ZVFBF ++ (match_operand: 4 "register_operand" " vr"))) ++ (match_operand:VWEXTF_ZVFBF 2 "register_operand" " 0")) ++ (match_dup 2)))] ++ "TARGET_ZVFBFWMA" ++ "vfwmaccbf16.vf\t%0,%3,%4%p1" ++ [(set_attr "type" "vfwmaccbf16") ++ (set_attr "mode" "") ++ (set (attr "frm_mode") ++ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))]) +diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md +index 8c908c1e1a5..c6057d8b1cb 100644 +--- a/gcc/config/riscv/vector-iterators.md ++++ b/gcc/config/riscv/vector-iterators.md +@@ -159,6 +159,15 @@ + (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64") + ]) + ++(define_mode_iterator VF_ZVFBF16 [ ++ (RVVM8BF "TARGET_VECTOR_ELEN_BF_16") ++ (RVVM4BF "TARGET_VECTOR_ELEN_BF_16") ++ (RVVM2BF "TARGET_VECTOR_ELEN_BF_16") ++ (RVVM1BF "TARGET_VECTOR_ELEN_BF_16") ++ (RVVMF2BF "TARGET_VECTOR_ELEN_BF_16") ++ (RVVMF4BF "TARGET_VECTOR_ELEN_BF_16 && TARGET_MIN_VLEN > 32") ++]) ++ + (define_mode_iterator VF_ZVFHMIN [ + (RVVM8HF "TARGET_VECTOR_ELEN_FP_16") (RVVM4HF "TARGET_VECTOR_ELEN_FP_16") (RVVM2HF "TARGET_VECTOR_ELEN_FP_16") + (RVVM1HF "TARGET_VECTOR_ELEN_FP_16") (RVVMF2HF "TARGET_VECTOR_ELEN_FP_16") +@@ -294,6 +303,10 @@ + (define_mode_iterator VEEWEXT2 [ + RVVM8HI RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32") + ++ (RVVM8BF "TARGET_VECTOR_ELEN_BF_16") (RVVM4BF "TARGET_VECTOR_ELEN_BF_16") (RVVM2BF "TARGET_VECTOR_ELEN_BF_16") ++ (RVVM1BF "TARGET_VECTOR_ELEN_BF_16") (RVVMF2BF "TARGET_VECTOR_ELEN_BF_16") ++ (RVVMF4BF "TARGET_VECTOR_ELEN_BF_16 && TARGET_MIN_VLEN > 32") ++ + (RVVM8HF "TARGET_VECTOR_ELEN_FP_16") (RVVM4HF "TARGET_VECTOR_ELEN_FP_16") (RVVM2HF "TARGET_VECTOR_ELEN_FP_16") + (RVVM1HF "TARGET_VECTOR_ELEN_FP_16") (RVVMF2HF "TARGET_VECTOR_ELEN_FP_16") + (RVVMF4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") +@@ -336,6 +349,10 @@ + + RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32") + ++ (RVVM4BF "TARGET_VECTOR_ELEN_BF_16") (RVVM2BF "TARGET_VECTOR_ELEN_BF_16") ++ (RVVM1BF "TARGET_VECTOR_ELEN_BF_16") (RVVMF2BF "TARGET_VECTOR_ELEN_BF_16") ++ (RVVMF4BF "TARGET_VECTOR_ELEN_BF_16 && TARGET_MIN_VLEN > 32") ++ + (RVVM4HF "TARGET_VECTOR_ELEN_FP_16") (RVVM2HF "TARGET_VECTOR_ELEN_FP_16") + (RVVM1HF "TARGET_VECTOR_ELEN_FP_16") (RVVMF2HF "TARGET_VECTOR_ELEN_FP_16") + (RVVMF4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") +@@ -359,6 +376,11 @@ + (RVVMF2HI "TARGET_64BIT") + (RVVMF4HI "TARGET_MIN_VLEN > 32 && TARGET_64BIT") + ++ (RVVM2BF "TARGET_VECTOR_ELEN_BF_16") ++ (RVVM1BF "TARGET_VECTOR_ELEN_BF_16") ++ (RVVMF2BF "TARGET_VECTOR_ELEN_FP_16") ++ (RVVMF4BF "TARGET_VECTOR_ELEN_BF_16 && TARGET_MIN_VLEN > 32 && TARGET_64BIT") ++ + (RVVM2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_64BIT") + (RVVM1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_64BIT") + (RVVMF2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_64BIT") +@@ -781,6 +803,7 @@ + (RVVMF4HI "TARGET_MIN_VLEN > 32") + (RVVMF2SI "TARGET_MIN_VLEN > 32") + (RVVM1DI "TARGET_VECTOR_ELEN_64") ++ (RVVMF4BF "TARGET_VECTOR_ELEN_BF_16 && TARGET_MIN_VLEN > 32") + (RVVMF4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") + (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") + (RVVM1DF "TARGET_VECTOR_ELEN_FP_64") +@@ -791,6 +814,7 @@ + RVVMF2HI + RVVM1SI + (RVVM2DI "TARGET_VECTOR_ELEN_64") ++ (RVVMF2BF "TARGET_VECTOR_ELEN_BF_16") + (RVVMF2HF "TARGET_VECTOR_ELEN_FP_16") + (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") + (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") +@@ -801,6 +825,7 @@ + RVVM1HI + RVVM2SI + (RVVM4DI "TARGET_VECTOR_ELEN_64") ++ (RVVM1BF "TARGET_VECTOR_ELEN_BF_16") + (RVVM1HF "TARGET_VECTOR_ELEN_FP_16") + (RVVM2SF "TARGET_VECTOR_ELEN_FP_32") + (RVVM4DF "TARGET_VECTOR_ELEN_FP_64") +@@ -811,6 +836,7 @@ + RVVM2HI + RVVM4SI + (RVVM8DI "TARGET_VECTOR_ELEN_64") ++ (RVVM2BF "TARGET_VECTOR_ELEN_BF_16") + (RVVM2HF "TARGET_VECTOR_ELEN_FP_16") + (RVVM4SF "TARGET_VECTOR_ELEN_FP_32") + (RVVM8DF "TARGET_VECTOR_ELEN_FP_64") +@@ -820,6 +846,7 @@ + RVVM2QI + RVVM4HI + RVVM8SI ++ (RVVM4BF "TARGET_VECTOR_ELEN_BF_16") + (RVVM4HF "TARGET_VECTOR_ELEN_FP_16") + (RVVM8SF "TARGET_VECTOR_ELEN_FP_32") + ]) +@@ -827,6 +854,7 @@ + (define_mode_iterator RATIO2 [ + RVVM4QI + RVVM8HI ++ (RVVM8BF "TARGET_VECTOR_ELEN_BF_16") + (RVVM8HF "TARGET_VECTOR_ELEN_FP_16") + ]) + +@@ -878,6 +906,9 @@ + + RVVM8HI RVVM4HI RVVM2HI RVVM1HI + ++ (RVVM8BF "TARGET_VECTOR_ELEN_BF_16") (RVVM4BF "TARGET_VECTOR_ELEN_BF_16") ++ (RVVM2BF "TARGET_VECTOR_ELEN_BF_16") (RVVM1BF "TARGET_VECTOR_ELEN_BF_16") ++ + (RVVM8HF "TARGET_VECTOR_ELEN_FP_16") (RVVM4HF "TARGET_VECTOR_ELEN_FP_16") + (RVVM2HF "TARGET_VECTOR_ELEN_FP_16") (RVVM1HF "TARGET_VECTOR_ELEN_FP_16") + +@@ -898,6 +929,8 @@ + + RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32") + ++ (RVVMF2BF "TARGET_VECTOR_ELEN_BF_16") (RVVMF4BF "TARGET_VECTOR_ELEN_BF_16 && TARGET_MIN_VLEN > 32") ++ + (RVVMF2HF "TARGET_VECTOR_ELEN_FP_16") (RVVMF4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") + + (RVVMF2SI "TARGET_MIN_VLEN > 32") +@@ -1155,6 +1188,13 @@ + (RVVM1x6DI "TARGET_VECTOR_ELEN_64") + (RVVM1x7DI "TARGET_VECTOR_ELEN_64") + (RVVM1x8DI "TARGET_VECTOR_ELEN_64") ++ (RVVMF4x2BF "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_BF_16") ++ (RVVMF4x3BF "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_BF_16") ++ (RVVMF4x4BF "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_BF_16") ++ (RVVMF4x5BF "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_BF_16") ++ (RVVMF4x6BF "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_BF_16") ++ (RVVMF4x7BF "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_BF_16") ++ (RVVMF4x8BF "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_BF_16") + (RVVMF4x2HF "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_FP_16") + (RVVMF4x3HF "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_FP_16") + (RVVMF4x4HF "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_FP_16") +@@ -1203,6 +1243,13 @@ + (RVVM2x2DI "TARGET_VECTOR_ELEN_64") + (RVVM2x3DI "TARGET_VECTOR_ELEN_64") + (RVVM2x4DI "TARGET_VECTOR_ELEN_64") ++ (RVVMF2x2BF "TARGET_VECTOR_ELEN_BF_16") ++ (RVVMF2x3BF "TARGET_VECTOR_ELEN_BF_16") ++ (RVVMF2x4BF "TARGET_VECTOR_ELEN_BF_16") ++ (RVVMF2x5BF "TARGET_VECTOR_ELEN_BF_16") ++ (RVVMF2x6BF "TARGET_VECTOR_ELEN_BF_16") ++ (RVVMF2x7BF "TARGET_VECTOR_ELEN_BF_16") ++ (RVVMF2x8BF "TARGET_VECTOR_ELEN_BF_16") + (RVVMF2x2HF "TARGET_VECTOR_ELEN_FP_16") + (RVVMF2x3HF "TARGET_VECTOR_ELEN_FP_16") + (RVVMF2x4HF "TARGET_VECTOR_ELEN_FP_16") +@@ -1241,6 +1288,13 @@ + RVVM2x3SI + RVVM2x4SI + (RVVM4x2DI "TARGET_VECTOR_ELEN_64") ++ (RVVM1x2BF "TARGET_VECTOR_ELEN_BF_16") ++ (RVVM1x3BF "TARGET_VECTOR_ELEN_BF_16") ++ (RVVM1x4BF "TARGET_VECTOR_ELEN_BF_16") ++ (RVVM1x5BF "TARGET_VECTOR_ELEN_BF_16") ++ (RVVM1x6BF "TARGET_VECTOR_ELEN_BF_16") ++ (RVVM1x7BF "TARGET_VECTOR_ELEN_BF_16") ++ (RVVM1x8BF "TARGET_VECTOR_ELEN_BF_16") + (RVVM1x2HF "TARGET_VECTOR_ELEN_FP_16") + (RVVM1x3HF "TARGET_VECTOR_ELEN_FP_16") + (RVVM1x4HF "TARGET_VECTOR_ELEN_FP_16") +@@ -1266,6 +1320,9 @@ + RVVM2x3HI + RVVM2x4HI + RVVM4x2SI ++ (RVVM2x2BF "TARGET_VECTOR_ELEN_BF_16") ++ (RVVM2x3BF "TARGET_VECTOR_ELEN_BF_16") ++ (RVVM2x4BF "TARGET_VECTOR_ELEN_BF_16") + (RVVM2x2HF "TARGET_VECTOR_ELEN_FP_16") + (RVVM2x3HF "TARGET_VECTOR_ELEN_FP_16") + (RVVM2x4HF "TARGET_VECTOR_ELEN_FP_16") +@@ -1277,6 +1334,7 @@ + RVVM2x3QI + RVVM2x4QI + RVVM4x2HI ++ (RVVM4x2BF "TARGET_VECTOR_ELEN_BF_16") + (RVVM4x2HF "TARGET_VECTOR_ELEN_FP_16") + ]) + +@@ -1488,6 +1546,13 @@ + (RVVM2DI "TARGET_VECTOR_ELEN_64 && TARGET_64BIT") + (RVVM1DI "TARGET_VECTOR_ELEN_64 && TARGET_64BIT") + ++ (RVVM8BF "TARGET_VECTOR_ELEN_BF_16") ++ (RVVM4BF "TARGET_VECTOR_ELEN_BF_16") ++ (RVVM2BF "TARGET_VECTOR_ELEN_BF_16") ++ (RVVM1BF "TARGET_VECTOR_ELEN_BF_16") ++ (RVVMF2BF "TARGET_VECTOR_ELEN_BF_16") ++ (RVVMF4BF "TARGET_VECTOR_ELEN_BF_16 && TARGET_MIN_VLEN > 32") ++ + (RVVM8HF "TARGET_ZVFH") (RVVM4HF "TARGET_ZVFH") (RVVM2HF "TARGET_ZVFH") + (RVVM1HF "TARGET_ZVFH") (RVVMF2HF "TARGET_ZVFH") + (RVVMF4HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32") +@@ -1589,7 +1654,7 @@ + + (define_mode_iterator VLS_ZVFH [VLSI VLSF]) + +-(define_mode_iterator V [VI VF_ZVFHMIN]) ++(define_mode_iterator V [VI VF_ZVFBF16 VF_ZVFHMIN]) + + (define_mode_iterator V_ZVFH [VI VF]) + +@@ -1601,7 +1666,7 @@ + + (define_mode_iterator V_VLSF [VF VLSF]) + +-(define_mode_iterator V_VLSF_ZVFHMIN [VF_ZVFHMIN VLSF_ZVFHMIN]) ++(define_mode_iterator V_VLSF_ZVFHMIN [VF_ZVFBF16 VF_ZVFHMIN VLSF_ZVFHMIN]) + + (define_mode_iterator VT [V1T V2T V4T V8T V16T V32T]) + +@@ -1686,6 +1751,8 @@ + + (RVVM8HI "RVVM8HI") (RVVM4HI "RVVM4HI") (RVVM2HI "RVVM2HI") (RVVM1HI "RVVM1HI") (RVVMF2HI "RVVMF2HI") (RVVMF4HI "RVVMF4HI") + ++ (RVVM8BF "RVVM8HI") (RVVM4BF "RVVM4HI") (RVVM2BF "RVVM2HI") (RVVM1BF "RVVM1HI") (RVVMF2BF "RVVMF2HI") (RVVMF4BF "RVVMF4HI") ++ + (RVVM8HF "RVVM8HI") (RVVM4HF "RVVM4HI") (RVVM2HF "RVVM2HI") (RVVM1HF "RVVM1HI") (RVVMF2HF "RVVMF2HI") (RVVMF4HF "RVVMF4HI") + + (RVVM8SI "RVVM8SI") (RVVM4SI "RVVM4SI") (RVVM2SI "RVVM2SI") (RVVM1SI "RVVM1SI") (RVVMF2SI "RVVMF2SI") +@@ -1877,6 +1944,8 @@ + + (RVVM8HI "RVVMF2BI") (RVVM4HI "RVVMF4BI") (RVVM2HI "RVVMF8BI") (RVVM1HI "RVVMF16BI") (RVVMF2HI "RVVMF32BI") (RVVMF4HI "RVVMF64BI") + ++ (RVVM8BF "RVVMF2BI") (RVVM4BF "RVVMF4BI") (RVVM2BF "RVVMF8BI") (RVVM1BF "RVVMF16BI") (RVVMF2BF "RVVMF32BI") (RVVMF4BF "RVVMF64BI") ++ + (RVVM8HF "RVVMF2BI") (RVVM4HF "RVVMF4BI") (RVVM2HF "RVVMF8BI") (RVVM1HF "RVVMF16BI") (RVVMF2HF "RVVMF32BI") (RVVMF4HF "RVVMF64BI") + + (RVVM8SI "RVVMF4BI") (RVVM4SI "RVVMF8BI") (RVVM2SI "RVVMF16BI") (RVVM1SI "RVVMF32BI") (RVVMF2SI "RVVMF64BI") +@@ -1903,6 +1972,14 @@ + (RVVM2x3HI "RVVMF8BI") (RVVM1x3HI "RVVMF16BI") (RVVMF2x3HI "RVVMF32BI") (RVVMF4x3HI "RVVMF64BI") + (RVVM4x2HI "RVVMF4BI") (RVVM2x2HI "RVVMF8BI") (RVVM1x2HI "RVVMF16BI") (RVVMF2x2HI "RVVMF32BI") (RVVMF4x2HI "RVVMF64BI") + ++ (RVVM1x8BF "RVVMF16BI") (RVVMF2x8BF "RVVMF32BI") (RVVMF4x8BF "RVVMF64BI") ++ (RVVM1x7BF "RVVMF16BI") (RVVMF2x7BF "RVVMF32BI") (RVVMF4x7BF "RVVMF64BI") ++ (RVVM1x6BF "RVVMF16BI") (RVVMF2x6BF "RVVMF32BI") (RVVMF4x6BF "RVVMF64BI") ++ (RVVM1x5BF "RVVMF16BI") (RVVMF2x5BF "RVVMF32BI") (RVVMF4x5BF "RVVMF64BI") ++ (RVVM2x4BF "RVVMF8BI") (RVVM1x4BF "RVVMF16BI") (RVVMF2x4BF "RVVMF32BI") (RVVMF4x4BF "RVVMF64BI") ++ (RVVM2x3BF "RVVMF8BI") (RVVM1x3BF "RVVMF16BI") (RVVMF2x3BF "RVVMF32BI") (RVVMF4x3BF "RVVMF64BI") ++ (RVVM4x2BF "RVVMF4BI") (RVVM2x2BF "RVVMF8BI") (RVVM1x2BF "RVVMF16BI") (RVVMF2x2BF "RVVMF32BI") (RVVMF4x2BF "RVVMF64BI") ++ + (RVVM1x8HF "RVVMF16BI") (RVVMF2x8HF "RVVMF32BI") (RVVMF4x8HF "RVVMF64BI") + (RVVM1x7HF "RVVMF16BI") (RVVMF2x7HF "RVVMF32BI") (RVVMF4x7HF "RVVMF64BI") + (RVVM1x6HF "RVVMF16BI") (RVVMF2x6HF "RVVMF32BI") (RVVMF4x6HF "RVVMF64BI") +@@ -1978,6 +2055,8 @@ + + (RVVM8HI "rvvmf2bi") (RVVM4HI "rvvmf4bi") (RVVM2HI "rvvmf8bi") (RVVM1HI "rvvmf16bi") (RVVMF2HI "rvvmf32bi") (RVVMF4HI "rvvmf64bi") + ++ (RVVM8BF "rvvmf2bi") (RVVM4BF "rvvmf4bi") (RVVM2BF "rvvmf8bi") (RVVM1BF "rvvmf16bi") (RVVMF2BF "rvvmf32bi") (RVVMF4BF "rvvmf64bi") ++ + (RVVM8HF "rvvmf2bi") (RVVM4HF "rvvmf4bi") (RVVM2HF "rvvmf8bi") (RVVM1HF "rvvmf16bi") (RVVMF2HF "rvvmf32bi") (RVVMF4HF "rvvmf64bi") + + (RVVM8SI "rvvmf4bi") (RVVM4SI "rvvmf8bi") (RVVM2SI "rvvmf16bi") (RVVM1SI "rvvmf32bi") (RVVMF2SI "rvvmf64bi") +@@ -2004,6 +2083,14 @@ + (RVVM2x3HI "rvvmf8bi") (RVVM1x3HI "rvvmf16bi") (RVVMF2x3HI "rvvmf32bi") (RVVMF4x3HI "rvvmf64bi") + (RVVM4x2HI "rvvmf4bi") (RVVM2x2HI "rvvmf8bi") (RVVM1x2HI "rvvmf16bi") (RVVMF2x2HI "rvvmf32bi") (RVVMF4x2HI "rvvmf64bi") + ++ (RVVM1x8BF "rvvmf16bi") (RVVMF2x8BF "rvvmf32bi") (RVVMF4x8BF "rvvmf64bi") ++ (RVVM1x7BF "rvvmf16bi") (RVVMF2x7BF "rvvmf32bi") (RVVMF4x7BF "rvvmf64bi") ++ (RVVM1x6BF "rvvmf16bi") (RVVMF2x6BF "rvvmf32bi") (RVVMF4x6BF "rvvmf64bi") ++ (RVVM1x5BF "rvvmf16bi") (RVVMF2x5BF "rvvmf32bi") (RVVMF4x5BF "rvvmf64bi") ++ (RVVM2x4BF "rvvmf8bi") (RVVM1x4BF "rvvmf16bi") (RVVMF2x4BF "rvvmf32bi") (RVVMF4x4BF "rvvmf64bi") ++ (RVVM2x3BF "rvvmf8bi") (RVVM1x3BF "rvvmf16bi") (RVVMF2x3BF "rvvmf32bi") (RVVMF4x3BF "rvvmf64bi") ++ (RVVM4x2BF "rvvmf4bi") (RVVM2x2BF "rvvmf8bi") (RVVM1x2BF "rvvmf16bi") (RVVMF2x2BF "rvvmf32bi") (RVVMF4x2BF "rvvmf64bi") ++ + (RVVM1x8HF "rvvmf16bi") (RVVMF2x8HF "rvvmf32bi") (RVVMF4x8HF "rvvmf64bi") + (RVVM1x7HF "rvvmf16bi") (RVVMF2x7HF "rvvmf32bi") (RVVMF4x7HF "rvvmf64bi") + (RVVM1x6HF "rvvmf16bi") (RVVMF2x6HF "rvvmf32bi") (RVVMF4x6HF "rvvmf64bi") +@@ -2079,6 +2166,8 @@ + + (RVVM8HI "HI") (RVVM4HI "HI") (RVVM2HI "HI") (RVVM1HI "HI") (RVVMF2HI "HI") (RVVMF4HI "HI") + ++ (RVVM8BF "BF") (RVVM4BF "BF") (RVVM2BF "BF") (RVVM1BF "BF") (RVVMF2BF "BF") (RVVMF4BF "BF") ++ + (RVVM8HF "HF") (RVVM4HF "HF") (RVVM2HF "HF") (RVVM1HF "HF") (RVVMF2HF "HF") (RVVMF4HF "HF") + + (RVVM8SI "SI") (RVVM4SI "SI") (RVVM2SI "SI") (RVVM1SI "SI") (RVVMF2SI "SI") +@@ -2176,6 +2265,8 @@ + + (RVVM8HI "hi") (RVVM4HI "hi") (RVVM2HI "hi") (RVVM1HI "hi") (RVVMF2HI "hi") (RVVMF4HI "hi") + ++ (RVVM8BF "bf") (RVVM4BF "bf") (RVVM2BF "bf") (RVVM1BF "bf") (RVVMF2BF "bf") (RVVMF4BF "bf") ++ + (RVVM8HF "hf") (RVVM4HF "hf") (RVVM2HF "hf") (RVVM1HF "hf") (RVVMF2HF "hf") (RVVMF4HF "hf") + + (RVVM8SI "si") (RVVM4SI "si") (RVVM2SI "si") (RVVM1SI "si") (RVVMF2SI "si") +@@ -2218,6 +2309,32 @@ + (RVVM2x3HI "rvvm2hi") (RVVM1x3HI "rvvm1hi") (RVVMF2x3HI "rvvmf2hi") (RVVMF4x3HI "rvvmf4hi") + (RVVM4x2HI "rvvm4hi") (RVVM2x2HI "rvvm2hi") (RVVM1x2HI "rvvm1hi") (RVVMF2x2HI "rvvmf2hi") (RVVMF4x2HI "rvvmf4hi") + ++ (RVVM1x8BF "rvvm1bf") ++ (RVVMF2x8BF "rvvmf2bf") ++ (RVVMF4x8BF "rvvmf4bf") ++ (RVVM1x7BF "rvvm1bf") ++ (RVVMF2x7BF "rvvmf2bf") ++ (RVVMF4x7BF "rvvmf4bf") ++ (RVVM1x6BF "rvvm1bf") ++ (RVVMF2x6BF "rvvmf2bf") ++ (RVVMF4x6BF "rvvmf4bf") ++ (RVVM1x5BF "rvvm1bf") ++ (RVVMF2x5BF "rvvmf2bf") ++ (RVVMF4x5BF "rvvmf4bf") ++ (RVVM2x4BF "rvvm2bf") ++ (RVVM1x4BF "rvvm1bf") ++ (RVVMF2x4BF "rvvmf2bf") ++ (RVVMF4x4BF "rvvmf4bf") ++ (RVVM2x3BF "rvvm2bf") ++ (RVVM1x3BF "rvvm1bf") ++ (RVVMF2x3BF "rvvmf2bf") ++ (RVVMF4x3BF "rvvmf4bf") ++ (RVVM4x2BF "rvvm4bf") ++ (RVVM2x2BF "rvvm2bf") ++ (RVVM1x2BF "rvvm1bf") ++ (RVVMF2x2BF "rvvmf2bf") ++ (RVVMF4x2BF "rvvmf4bf") ++ + (RVVM1x8HF "rvvm1hf") + (RVVMF2x8HF "rvvmf2hf") + (RVVMF4x8HF "rvvmf4hf") +@@ -2354,6 +2471,14 @@ + (RVVM2x3HI "3") (RVVM1x3HI "3") (RVVMF2x3HI "3") (RVVMF4x3HI "3") + (RVVM4x2HI "2") (RVVM2x2HI "2") (RVVM1x2HI "2") (RVVMF2x2HI "2") (RVVMF4x2HI "2") + ++ (RVVM1x8BF "8") (RVVMF2x8BF "8") (RVVMF4x8BF "8") ++ (RVVM1x7BF "7") (RVVMF2x7BF "7") (RVVMF4x7BF "7") ++ (RVVM1x6BF "6") (RVVMF2x6BF "6") (RVVMF4x6BF "6") ++ (RVVM1x5BF "5") (RVVMF2x5BF "5") (RVVMF4x5BF "5") ++ (RVVM2x4BF "4") (RVVM1x4BF "4") (RVVMF2x4BF "4") (RVVMF4x4BF "4") ++ (RVVM2x3BF "3") (RVVM1x3BF "3") (RVVMF2x3BF "3") (RVVMF4x3BF "3") ++ (RVVM4x2BF "2") (RVVM2x2BF "2") (RVVM1x2BF "2") (RVVMF2x2BF "2") (RVVMF4x2BF "2") ++ + (RVVM1x8HF "8") (RVVMF2x8HF "8") (RVVMF4x8HF "8") + (RVVM1x7HF "7") (RVVMF2x7HF "7") (RVVMF4x7HF "7") + (RVVM1x6HF "6") (RVVMF2x6HF "6") (RVVMF4x6HF "6") +@@ -2408,6 +2533,8 @@ + + (RVVM8HI "16") (RVVM4HI "16") (RVVM2HI "16") (RVVM1HI "16") (RVVMF2HI "16") (RVVMF4HI "16") + ++ (RVVM8BF "16") (RVVM4BF "16") (RVVM2BF "16") (RVVM1BF "16") (RVVMF2BF "16") (RVVMF4BF "16") ++ + (RVVM8HF "16") (RVVM4HF "16") (RVVM2HF "16") (RVVM1HF "16") (RVVMF2HF "16") (RVVMF4HF "16") + + (RVVM8SI "32") (RVVM4SI "32") (RVVM2SI "32") (RVVM1SI "32") (RVVMF2SI "32") +@@ -2434,6 +2561,14 @@ + (RVVM2x3HI "16") (RVVM1x3HI "16") (RVVMF2x3HI "16") (RVVMF4x3HI "16") + (RVVM4x2HI "16") (RVVM2x2HI "16") (RVVM1x2HI "16") (RVVMF2x2HI "16") (RVVMF4x2HI "16") + ++ (RVVM1x8BF "16") (RVVMF2x8BF "16") (RVVMF4x8BF "16") ++ (RVVM1x7BF "16") (RVVMF2x7BF "16") (RVVMF4x7BF "16") ++ (RVVM1x6BF "16") (RVVMF2x6BF "16") (RVVMF4x6BF "16") ++ (RVVM1x5BF "16") (RVVMF2x5BF "16") (RVVMF4x5BF "16") ++ (RVVM2x4BF "16") (RVVM1x4BF "16") (RVVMF2x4BF "16") (RVVMF4x4BF "16") ++ (RVVM2x3BF "16") (RVVM1x3BF "16") (RVVMF2x3BF "16") (RVVMF4x3BF "16") ++ (RVVM4x2BF "16") (RVVM2x2BF "16") (RVVM1x2BF "16") (RVVMF2x2BF "16") (RVVMF4x2BF "16") ++ + (RVVM1x8HF "16") (RVVMF2x8HF "16") (RVVMF4x8HF "16") + (RVVM1x7HF "16") (RVVMF2x7HF "16") (RVVMF4x7HF "16") + (RVVM1x6HF "16") (RVVMF2x6HF "16") (RVVMF4x6HF "16") +@@ -2500,6 +2635,8 @@ + (define_mode_attr double_trunc_sew [ + (RVVM8HI "8") (RVVM4HI "8") (RVVM2HI "8") (RVVM1HI "8") (RVVMF2HI "8") (RVVMF4HI "8") + ++ (RVVM8BF "8") (RVVM4BF "8") (RVVM2BF "8") (RVVM1BF "8") (RVVMF2BF "8") (RVVMF4BF "8") ++ + (RVVM8HF "8") (RVVM4HF "8") (RVVM2HF "8") (RVVM1HF "8") (RVVMF2HF "8") (RVVMF4HF "8") + + (RVVM8SI "16") (RVVM4SI "16") (RVVM2SI "16") (RVVM1SI "16") (RVVMF2SI "16") +@@ -2532,6 +2669,8 @@ + + (RVVM4HI "32") (RVVM2HI "32") (RVVM1HI "32") (RVVMF2HI "32") (RVVMF4HI "32") + ++ (RVVM4BF "32") (RVVM2BF "32") (RVVM1BF "32") (RVVMF2BF "32") (RVVMF4BF "32") ++ + (RVVM4HF "32") (RVVM2HF "32") (RVVM1HF "32") (RVVMF2HF "32") (RVVMF4HF "32") + + (RVVM4SI "64") (RVVM2SI "64") (RVVM1SI "64") (RVVMF2SI "64") +@@ -2866,6 +3005,8 @@ + (define_mode_attr VINDEX_DOUBLE_TRUNC [ + (RVVM8HI "RVVM4QI") (RVVM4HI "RVVM2QI") (RVVM2HI "RVVM1QI") (RVVM1HI "RVVMF2QI") (RVVMF2HI "RVVMF4QI") (RVVMF4HI "RVVMF8QI") + ++ (RVVM8BF "RVVM4QI") (RVVM4BF "RVVM2QI") (RVVM2BF "RVVM1QI") (RVVM1BF "RVVMF2QI") (RVVMF2BF "RVVMF4QI") (RVVMF4BF "RVVMF8QI") ++ + (RVVM8HF "RVVM4QI") (RVVM4HF "RVVM2QI") (RVVM2HF "RVVM1QI") (RVVM1HF "RVVMF2QI") (RVVMF2HF "RVVMF4QI") (RVVMF4HF "RVVMF8QI") + + (RVVM8SI "RVVM4HI") (RVVM4SI "RVVM2HI") (RVVM2SI "RVVM1HI") (RVVM1SI "RVVMF2HI") (RVVMF2SI "RVVMF4HI") +@@ -2898,6 +3039,8 @@ + + (RVVM4HI "RVVM8SI") (RVVM2HI "RVVM4SI") (RVVM1HI "RVVM2SI") (RVVMF2HI "RVVM1SI") (RVVMF4HI "RVVMF2SI") + ++ (RVVM4BF "RVVM8SI") (RVVM2BF "RVVM4SI") (RVVM1BF "RVVM2SI") (RVVMF2BF "RVVM1SI") (RVVMF4BF "RVVMF2SI") ++ + (RVVM4HF "RVVM8SI") (RVVM2HF "RVVM4SI") (RVVM1HF "RVVM2SI") (RVVMF2HF "RVVM1SI") (RVVMF4HF "RVVMF2SI") + + (RVVM4SI "RVVM8DI") (RVVM2SI "RVVM4DI") (RVVM1SI "RVVM2DI") (RVVMF2SI "RVVM1DI") +@@ -2910,6 +3053,8 @@ + + (RVVM2HI "RVVM8DI") (RVVM1HI "RVVM4DI") (RVVMF2HI "RVVM2DI") (RVVMF4HI "RVVM1DI") + ++ (RVVM2BF "RVVM8DI") (RVVM1BF "RVVM4DI") (RVVMF2BF "RVVM2DI") (RVVMF4BF "RVVM1DI") ++ + (RVVM2HF "RVVM8DI") (RVVM1HF "RVVM4DI") (RVVMF2HF "RVVM2DI") (RVVMF4HF "RVVM1DI") + ]) + +@@ -3414,6 +3559,10 @@ + (RVVM2HI "vector_eew16_stride_operand") (RVVM1HI "vector_eew16_stride_operand") + (RVVMF2HI "vector_eew16_stride_operand") (RVVMF4HI "vector_eew16_stride_operand") + ++ (RVVM8BF "vector_eew16_stride_operand") (RVVM4BF "vector_eew16_stride_operand") ++ (RVVM2BF "vector_eew16_stride_operand") (RVVM1BF "vector_eew16_stride_operand") ++ (RVVMF2BF "vector_eew16_stride_operand") (RVVMF4BF "vector_eew16_stride_operand") ++ + (RVVM8HF "vector_eew16_stride_operand") (RVVM4HF "vector_eew16_stride_operand") + (RVVM2HF "vector_eew16_stride_operand") (RVVM1HF "vector_eew16_stride_operand") + (RVVMF2HF "vector_eew16_stride_operand") (RVVMF4HF "vector_eew16_stride_operand") +@@ -3443,6 +3592,10 @@ + (RVVM2HI "rJ,rJ,rJ,c02,c02,c02") (RVVM1HI "rJ,rJ,rJ,c02,c02,c02") + (RVVMF2HI "rJ,rJ,rJ,c02,c02,c02") (RVVMF4HI "rJ,rJ,rJ,c02,c02,c02") + ++ (RVVM8BF "rJ,rJ,rJ,c02,c02,c02") (RVVM4BF "rJ,rJ,rJ,c02,c02,c02") ++ (RVVM2BF "rJ,rJ,rJ,c02,c02,c02") (RVVM1BF "rJ,rJ,rJ,c02,c02,c02") ++ (RVVMF2BF "rJ,rJ,rJ,c02,c02,c02") (RVVMF4BF "rJ,rJ,rJ,c02,c02,c02") ++ + (RVVM8HF "rJ,rJ,rJ,c02,c02,c02") (RVVM4HF "rJ,rJ,rJ,c02,c02,c02") + (RVVM2HF "rJ,rJ,rJ,c02,c02,c02") (RVVM1HF "rJ,rJ,rJ,c02,c02,c02") + (RVVMF2HF "rJ,rJ,rJ,c02,c02,c02") (RVVMF4HF "rJ,rJ,rJ,c02,c02,c02") +@@ -3472,6 +3625,10 @@ + (RVVM2HI "rJ,c02") (RVVM1HI "rJ,c02") + (RVVMF2HI "rJ,c02") (RVVMF4HI "rJ,c02") + ++ (RVVM8BF "rJ,c02") (RVVM4BF "rJ,c02") ++ (RVVM2BF "rJ,c02") (RVVM1BF "rJ,c02") ++ (RVVMF2BF "rJ,c02") (RVVMF4BF "rJ,c02") ++ + (RVVM8HF "rJ,c02") (RVVM4HF "rJ,c02") + (RVVM2HF "rJ,c02") (RVVM1HF "rJ,c02") + (RVVMF2HF "rJ,c02") (RVVMF4HF "rJ,c02") +@@ -3500,6 +3657,10 @@ + (RVVM2HI "immediate_operand") (RVVM1HI "immediate_operand") + (RVVMF2HI "immediate_operand") (RVVMF4HI "immediate_operand") + ++ (RVVM8BF "const_1_operand") (RVVM4BF "vector_gs_extension_operand") ++ (RVVM2BF "immediate_operand") (RVVM1BF "immediate_operand") ++ (RVVMF2BF "immediate_operand") (RVVMF4BF "immediate_operand") ++ + (RVVM8HF "const_1_operand") (RVVM4HF "vector_gs_extension_operand") + (RVVM2HF "immediate_operand") (RVVM1HF "immediate_operand") + (RVVMF2HF "immediate_operand") (RVVMF4HF "immediate_operand") +@@ -3526,6 +3687,10 @@ + (RVVM2HI "const_1_or_2_operand") (RVVM1HI "const_1_or_2_operand") + (RVVMF2HI "const_1_or_2_operand") (RVVMF4HI "const_1_or_2_operand") + ++ (RVVM8BF "const_1_operand") (RVVM4BF "vector_gs_scale_operand_16_rv32") ++ (RVVM2BF "const_1_or_2_operand") (RVVM1BF "const_1_or_2_operand") ++ (RVVMF2BF "const_1_or_2_operand") (RVVMF4BF "const_1_or_2_operand") ++ + (RVVM8HF "const_1_operand") (RVVM4HF "vector_gs_scale_operand_16_rv32") + (RVVM2HF "const_1_or_2_operand") (RVVM1HF "const_1_or_2_operand") + (RVVMF2HF "const_1_or_2_operand") (RVVMF4HF "const_1_or_2_operand") +diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md +index 80d810fbca7..ec87a13579a 100644 +--- a/gcc/config/riscv/vector.md ++++ b/gcc/config/riscv/vector.md +@@ -55,7 +55,8 @@ + vgather,vcompress,vlsegde,vssegte,vlsegds,vssegts,vlsegdux,vlsegdox,\ + vssegtux,vssegtox,vlsegdff,vandn,vbrev,vbrev8,vrev8,vclz,vctz,vrol,\ + vror,vwsll,vclmul,vclmulh,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,\ +- vaeskf1,vaeskf2,vaesz,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c") ++ vaeskf1,vaeskf2,vaesz,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c,\ ++ vfncvtbf16,vfwcvtbf16,vfwmaccbf16") + (const_string "true")] + (const_string "false"))) + +@@ -79,7 +80,8 @@ + vgather,vcompress,vlsegde,vssegte,vlsegds,vssegts,vlsegdux,vlsegdox,\ + vssegtux,vssegtox,vlsegdff,vandn,vbrev,vbrev8,vrev8,vclz,vctz,vrol,\ + vror,vwsll,vclmul,vclmulh,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,\ +- vaeskf1,vaeskf2,vaesz,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c") ++ vaeskf1,vaeskf2,vaesz,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c,\ ++ vfncvtbf16,vfwcvtbf16,vfwmaccbf16") + (const_string "true")] + (const_string "false"))) + +@@ -120,6 +122,14 @@ + RVVM2x4HI,RVVM1x4HI,RVVMF2x4HI,RVVMF4x4HI,\ + RVVM2x3HI,RVVM1x3HI,RVVMF2x3HI,RVVMF4x3HI,\ + RVVM4x2HI,RVVM2x2HI,RVVM1x2HI,RVVMF2x2HI,RVVMF4x2HI,\ ++ RVVM8BF,RVVM4BF,RVVM2BF,RVVM1BF,RVVMF2BF,RVVMF4BF,\ ++ RVVM1x8BF,RVVMF2x8BF,RVVMF4x8BF,\ ++ RVVM1x7BF,RVVMF2x7BF,RVVMF4x7BF,\ ++ RVVM1x6BF,RVVMF2x6BF,RVVMF4x6BF,\ ++ RVVM1x5BF,RVVMF2x5BF,RVVMF4x5BF,\ ++ RVVM2x4BF,RVVM1x4BF,RVVMF2x4BF,RVVMF4x4BF,\ ++ RVVM2x3BF,RVVM1x3BF,RVVMF2x3BF,RVVMF4x3BF,\ ++ RVVM4x2BF,RVVM2x2BF,RVVM1x2BF,RVVMF2x2BF,RVVMF4x2BF,\ + RVVM8HF,RVVM4HF,RVVM2HF,RVVM1HF,RVVMF2HF,RVVMF4HF,\ + RVVM1x8HF,RVVMF2x8HF,RVVMF4x8HF,\ + RVVM1x7HF,RVVMF2x7HF,RVVMF4x7HF,\ +@@ -181,6 +191,12 @@ + (eq_attr "mode" "RVVM1HI") (symbol_ref "riscv_vector::LMUL_1") + (eq_attr "mode" "RVVMF2HI") (symbol_ref "riscv_vector::LMUL_F2") + (eq_attr "mode" "RVVMF4HI") (symbol_ref "riscv_vector::LMUL_F4") ++ (eq_attr "mode" "RVVM8BF") (symbol_ref "riscv_vector::LMUL_8") ++ (eq_attr "mode" "RVVM4BF") (symbol_ref "riscv_vector::LMUL_4") ++ (eq_attr "mode" "RVVM2BF") (symbol_ref "riscv_vector::LMUL_2") ++ (eq_attr "mode" "RVVM1BF") (symbol_ref "riscv_vector::LMUL_1") ++ (eq_attr "mode" "RVVMF2BF") (symbol_ref "riscv_vector::LMUL_F2") ++ (eq_attr "mode" "RVVMF4BF") (symbol_ref "riscv_vector::LMUL_F4") + (eq_attr "mode" "RVVM8HF") (symbol_ref "riscv_vector::LMUL_8") + (eq_attr "mode" "RVVM4HF") (symbol_ref "riscv_vector::LMUL_4") + (eq_attr "mode" "RVVM2HF") (symbol_ref "riscv_vector::LMUL_2") +@@ -262,6 +278,31 @@ + (eq_attr "mode" "RVVM1x2HI") (symbol_ref "riscv_vector::LMUL_1") + (eq_attr "mode" "RVVMF2x2HI") (symbol_ref "riscv_vector::LMUL_F2") + (eq_attr "mode" "RVVMF4x2HI") (symbol_ref "riscv_vector::LMUL_F4") ++ (eq_attr "mode" "RVVM1x8BF") (symbol_ref "riscv_vector::LMUL_1") ++ (eq_attr "mode" "RVVMF2x8BF") (symbol_ref "riscv_vector::LMUL_F2") ++ (eq_attr "mode" "RVVMF4x8BF") (symbol_ref "riscv_vector::LMUL_F4") ++ (eq_attr "mode" "RVVM1x7BF") (symbol_ref "riscv_vector::LMUL_1") ++ (eq_attr "mode" "RVVMF2x7BF") (symbol_ref "riscv_vector::LMUL_F2") ++ (eq_attr "mode" "RVVMF4x7BF") (symbol_ref "riscv_vector::LMUL_F4") ++ (eq_attr "mode" "RVVM1x6BF") (symbol_ref "riscv_vector::LMUL_1") ++ (eq_attr "mode" "RVVMF2x6BF") (symbol_ref "riscv_vector::LMUL_F2") ++ (eq_attr "mode" "RVVMF4x6BF") (symbol_ref "riscv_vector::LMUL_F4") ++ (eq_attr "mode" "RVVM1x5BF") (symbol_ref "riscv_vector::LMUL_1") ++ (eq_attr "mode" "RVVMF2x5BF") (symbol_ref "riscv_vector::LMUL_F2") ++ (eq_attr "mode" "RVVMF4x5BF") (symbol_ref "riscv_vector::LMUL_F4") ++ (eq_attr "mode" "RVVM2x4BF") (symbol_ref "riscv_vector::LMUL_2") ++ (eq_attr "mode" "RVVM1x4BF") (symbol_ref "riscv_vector::LMUL_1") ++ (eq_attr "mode" "RVVMF2x4BF") (symbol_ref "riscv_vector::LMUL_F2") ++ (eq_attr "mode" "RVVMF4x4BF") (symbol_ref "riscv_vector::LMUL_F4") ++ (eq_attr "mode" "RVVM2x3BF") (symbol_ref "riscv_vector::LMUL_2") ++ (eq_attr "mode" "RVVM1x3BF") (symbol_ref "riscv_vector::LMUL_1") ++ (eq_attr "mode" "RVVMF2x3BF") (symbol_ref "riscv_vector::LMUL_F2") ++ (eq_attr "mode" "RVVMF4x3BF") (symbol_ref "riscv_vector::LMUL_F4") ++ (eq_attr "mode" "RVVM4x2BF") (symbol_ref "riscv_vector::LMUL_4") ++ (eq_attr "mode" "RVVM2x2BF") (symbol_ref "riscv_vector::LMUL_2") ++ (eq_attr "mode" "RVVM1x2BF") (symbol_ref "riscv_vector::LMUL_1") ++ (eq_attr "mode" "RVVMF2x2BF") (symbol_ref "riscv_vector::LMUL_F2") ++ (eq_attr "mode" "RVVMF4x2BF") (symbol_ref "riscv_vector::LMUL_F4") + (eq_attr "mode" "RVVM1x8HF") (symbol_ref "riscv_vector::LMUL_1") + (eq_attr "mode" "RVVMF2x8HF") (symbol_ref "riscv_vector::LMUL_F2") + (eq_attr "mode" "RVVMF4x8HF") (symbol_ref "riscv_vector::LMUL_F4") +@@ -447,7 +488,7 @@ + vandn,vbrev,vbrev8,vrev8,vclz,vctz,vrol,vror,vwsll,\ + vclmul,vclmulh,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,\ + vaeskf1,vaeskf2,vaesz,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,\ +- vsm3me,vsm3c") ++ vsm3me,vsm3c,vfncvtbf16,vfwcvtbf16,vfwmaccbf16") + (const_int INVALID_ATTRIBUTE) + (and (eq_attr "type" "vlde,vste,vlsegde,vssegte,vlsegds,vssegts,\ + vlsegdff,vssegtux,vlsegdox,vlsegdux") +@@ -466,6 +507,12 @@ + (eq_attr "mode" "RVVM1HI") (const_int 16) + (eq_attr "mode" "RVVMF2HI") (const_int 32) + (eq_attr "mode" "RVVMF4HI") (const_int 64) ++ (eq_attr "mode" "RVVM8BF") (const_int 2) ++ (eq_attr "mode" "RVVM4BF") (const_int 4) ++ (eq_attr "mode" "RVVM2BF") (const_int 8) ++ (eq_attr "mode" "RVVM1BF") (const_int 16) ++ (eq_attr "mode" "RVVMF2BF") (const_int 32) ++ (eq_attr "mode" "RVVMF4BF") (const_int 64) + (eq_attr "mode" "RVVM8HF") (const_int 2) + (eq_attr "mode" "RVVM4HF") (const_int 4) + (eq_attr "mode" "RVVM2HF") (const_int 8) +@@ -547,6 +594,31 @@ + (eq_attr "mode" "RVVM1x2HI") (const_int 16) + (eq_attr "mode" "RVVMF2x2HI") (const_int 32) + (eq_attr "mode" "RVVMF4x2HI") (const_int 64) ++ (eq_attr "mode" "RVVM1x8BF") (const_int 16) ++ (eq_attr "mode" "RVVMF2x8BF") (const_int 32) ++ (eq_attr "mode" "RVVMF4x8BF") (const_int 64) ++ (eq_attr "mode" "RVVM1x7BF") (const_int 16) ++ (eq_attr "mode" "RVVMF2x7BF") (const_int 32) ++ (eq_attr "mode" "RVVMF4x7BF") (const_int 64) ++ (eq_attr "mode" "RVVM1x6BF") (const_int 16) ++ (eq_attr "mode" "RVVMF2x6BF") (const_int 32) ++ (eq_attr "mode" "RVVMF4x6BF") (const_int 64) ++ (eq_attr "mode" "RVVM1x5BF") (const_int 16) ++ (eq_attr "mode" "RVVMF2x5BF") (const_int 32) ++ (eq_attr "mode" "RVVMF4x5BF") (const_int 64) ++ (eq_attr "mode" "RVVM2x4BF") (const_int 8) ++ (eq_attr "mode" "RVVM1x4BF") (const_int 16) ++ (eq_attr "mode" "RVVMF2x4BF") (const_int 32) ++ (eq_attr "mode" "RVVMF4x4BF") (const_int 64) ++ (eq_attr "mode" "RVVM2x3BF") (const_int 8) ++ (eq_attr "mode" "RVVM1x3BF") (const_int 16) ++ (eq_attr "mode" "RVVMF2x3BF") (const_int 32) ++ (eq_attr "mode" "RVVMF4x3BF") (const_int 64) ++ (eq_attr "mode" "RVVM4x2BF") (const_int 4) ++ (eq_attr "mode" "RVVM2x2BF") (const_int 8) ++ (eq_attr "mode" "RVVM1x2BF") (const_int 16) ++ (eq_attr "mode" "RVVMF2x2BF") (const_int 32) ++ (eq_attr "mode" "RVVMF4x2BF") (const_int 64) + (eq_attr "mode" "RVVM1x8HF") (const_int 16) + (eq_attr "mode" "RVVMF2x8HF") (const_int 32) + (eq_attr "mode" "RVVMF4x8HF") (const_int 64) +@@ -724,7 +796,8 @@ + vired,viwred,vfredu,vfredo,vfwredu,vfwredo,vimovxv,vfmovfv,\ + vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down,\ + vgather,vldff,viwmuladd,vfwmuladd,vlsegde,vlsegds,vlsegdux,vlsegdox,vlsegdff,\ +- vandn,vbrev,vbrev8,vrev8,vrol,vror,vwsll,vclmul,vclmulh") ++ vandn,vbrev,vbrev8,vrev8,vrol,vror,vwsll,vclmul,vclmulh,\ ++ vfncvtbf16,vfwcvtbf16,vfwmaccbf16") + (const_int 2) + + (eq_attr "type" "vimerge,vfmerge,vcompress,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,\ +@@ -768,7 +841,8 @@ + vfcvtftoi,vfwcvtitof,vfwcvtftoi,vfwcvtftof,vfncvtitof,\ + vfncvtftoi,vfncvtftof,vfclass,vimovxv,vfmovfv,vcompress,\ + vlsegde,vssegts,vssegtux,vssegtox,vlsegdff,vbrev,vbrev8,vrev8,\ +- vghsh,vaeskf1,vaeskf2,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm3me,vsm3c") ++ vghsh,vaeskf1,vaeskf2,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm3me,vsm3c,\ ++ vfncvtbf16,vfwcvtbf16") + (const_int 4) + + ;; If operands[3] of "vlds" is not vector mode, it is pred_broadcast. +@@ -784,7 +858,7 @@ + vfsgnj,vfmerge,vired,viwred,vfredu,vfredo,vfwredu,vfwredo,\ + vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down,\ + vgather,viwmuladd,vfwmuladd,vlsegds,vlsegdux,vlsegdox,vandn,vrol,\ +- vror,vwsll,vclmul,vclmulh") ++ vror,vwsll,vclmul,vclmulh,vfwmaccbf16") + (const_int 5) + + (eq_attr "type" "vicmp,vimuladd,vfcmp,vfmuladd") +@@ -801,7 +875,8 @@ + vfcvtitof,vfcvtftoi,vfwcvtitof,vfwcvtftoi,vfwcvtftof,\ + vfncvtitof,vfncvtftoi,vfncvtftof,vfclass,vimovxv,vfmovfv,\ + vcompress,vldff,vlsegde,vlsegdff,vbrev,vbrev8,vrev8,vghsh,\ +- vaeskf1,vaeskf2,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm3me,vsm3c") ++ vaeskf1,vaeskf2,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm3me,vsm3c,\ ++ vfncvtbf16,vfwcvtbf16") + (symbol_ref "riscv_vector::get_ta(operands[5])") + + ;; If operands[3] of "vlds" is not vector mode, it is pred_broadcast. +@@ -817,7 +892,8 @@ + vfwalu,vfwmul,vfsgnj,vfmerge,vired,viwred,vfredu,\ + vfredo,vfwredu,vfwredo,vslideup,vslidedown,vislide1up,\ + vislide1down,vfslide1up,vfslide1down,vgather,viwmuladd,vfwmuladd,\ +- vlsegds,vlsegdux,vlsegdox,vandn,vrol,vror,vwsll,vclmul,vclmulh") ++ vlsegds,vlsegdux,vlsegdox,vandn,vrol,vror,vwsll,vclmul,vclmulh,\ ++ vfwmaccbf16") + (symbol_ref "riscv_vector::get_ta(operands[6])") + + (eq_attr "type" "vimuladd,vfmuladd") +@@ -831,7 +907,8 @@ + (define_attr "ma" "" + (cond [(eq_attr "type" "vlde,vext,vmiota,vfsqrt,vfrecp,vfcvtitof,vfcvtftoi,\ + vfwcvtitof,vfwcvtftoi,vfwcvtftof,vfncvtitof,vfncvtftoi,\ +- vfncvtftof,vfclass,vldff,vlsegde,vlsegdff,vbrev,vbrev8,vrev8") ++ vfncvtftof,vfclass,vldff,vlsegde,vlsegdff,vbrev,vbrev8,vrev8,\ ++ vfncvtbf16,vfwcvtbf16") + (symbol_ref "riscv_vector::get_ma(operands[6])") + + ;; If operands[3] of "vlds" is not vector mode, it is pred_broadcast. +@@ -847,7 +924,7 @@ + vfwalu,vfwmul,vfsgnj,vfcmp,vslideup,vslidedown,\ + vislide1up,vislide1down,vfslide1up,vfslide1down,vgather,\ + viwmuladd,vfwmuladd,vlsegds,vlsegdux,vlsegdox,vandn,vrol,\ +- vror,vwsll,vclmul,vclmulh") ++ vror,vwsll,vclmul,vclmulh,vfwmaccbf16") + (symbol_ref "riscv_vector::get_ma(operands[7])") + + (eq_attr "type" "vimuladd,vfmuladd") +@@ -863,7 +940,8 @@ + vfsqrt,vfrecp,vfmerge,vfcvtitof,vfcvtftoi,vfwcvtitof,\ + vfwcvtftoi,vfwcvtftof,vfncvtitof,vfncvtftoi,vfncvtftof,\ + vfclass,vired,viwred,vfredu,vfredo,vfwredu,vfwredo,\ +- vimovxv,vfmovfv,vlsegde,vlsegdff,vmiota,vbrev,vbrev8,vrev8") ++ vimovxv,vfmovfv,vlsegde,vlsegdff,vmiota,vbrev,vbrev8,vrev8,\ ++ vfncvtbf16,vfwcvtbf16") + (const_int 7) + (eq_attr "type" "vldm,vstm,vmalu,vmalu,vgmul,vaesef,vaesem,vaesdf,vaesdm,vaesz,\ + vsm4r") +@@ -881,7 +959,8 @@ + vnclip,vicmp,vfalu,vfmul,vfminmax,vfdiv,vfwalu,vfwmul,\ + vfsgnj,vfcmp,vslideup,vslidedown,vislide1up,\ + vislide1down,vfslide1up,vfslide1down,vgather,viwmuladd,vfwmuladd,\ +- vlsegds,vlsegdux,vlsegdox,vandn,vrol,vror,vclmul,vclmulh,vwsll") ++ vlsegds,vlsegdux,vlsegdox,vandn,vrol,vror,vclmul,vclmulh,vwsll,\ ++ vfwmaccbf16") + (const_int 8) + (eq_attr "type" "vstux,vstox,vssegts,vssegtux,vssegtox") + (const_int 5) +-- +2.47.3 + diff --git a/1009-RISC-V-Add-Zvfbfmin-and-Zvfbfwma-intrinsic.patch b/1009-RISC-V-Add-Zvfbfmin-and-Zvfbfwma-intrinsic.patch new file mode 100644 index 0000000..9587c6f --- /dev/null +++ b/1009-RISC-V-Add-Zvfbfmin-and-Zvfbfwma-intrinsic.patch @@ -0,0 +1,480 @@ +From bc78ca771cfc4abd7dc6d01764ae275d7fdafe47 Mon Sep 17 00:00:00 2001 +From: Feng Wang +Date: Mon, 17 Jun 2024 01:59:57 +0000 +Subject: [PATCH 1009/1087] RISC-V: Add Zvfbfmin and Zvfbfwma intrinsic + +commit 281f021ed4fbf9c2336048e34b6b40c6f7119baa upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +v3: Modify warning message in riscv.cc +v2: Rebase +Accroding to the intrinsic doc, the 'Zvfbfmin' and 'Zvfbfwma' intrinsic +functions are added by this patch. + +Signed-off-by: Feng Wang +gcc/ChangeLog: + + * config/riscv/riscv-vector-builtins-bases.cc (class vfncvtbf16_f): + Add 'Zvfbfmin' intrinsic in bases. + (class vfwcvtbf16_f): Ditto. + (class vfwmaccbf16): Add 'Zvfbfwma' intrinsic in bases. + (BASE): Add BASE macro for 'Zvfbfmin' and 'Zvfbfwma'. + * config/riscv/riscv-vector-builtins-bases.h: Add declaration for 'Zvfbfmin' and 'Zvfbfwma'. + * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS): + Add builtins def for 'Zvfbfmin' and 'Zvfbfwma'. + (vfncvtbf16_f): Ditto. + (vfncvtbf16_f_frm): Ditto. + (vfwcvtbf16_f): Ditto. + (vfwmaccbf16): Ditto. + (vfwmaccbf16_frm): Ditto. + * config/riscv/riscv-vector-builtins-shapes.cc (supports_vectype_p): + Add vector intrinsic build judgment for BFloat16. + (build_all): Ditto. + (BASE_NAME_MAX_LEN): Adjust max length. + * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_F32_OPS): + Add new operand type for BFloat16. + (vfloat32mf2_t): Ditto. + (vfloat32m1_t): Ditto. + (vfloat32m2_t): Ditto. + (vfloat32m4_t): Ditto. + (vfloat32m8_t): Ditto. + * config/riscv/riscv-vector-builtins.cc (DEF_RVV_F32_OPS): Ditto. + (validate_instance_type_required_extensions): + Add required_ext checking for 'Zvfbfmin' and 'Zvfbfwma'. + * config/riscv/riscv-vector-builtins.h (enum required_ext): + Add required_ext declaration for 'Zvfbfmin' and 'Zvfbfwma'. + (reqired_ext_to_isa_name): Ditto. + (required_extensions_specified): Ditto. + (struct function_group_info): Add match case for 'Zvfbfmin' and 'Zvfbfwma'. + * config/riscv/riscv.cc (riscv_validate_vector_type): + Add required_ext checking for 'Zvfbfmin' and 'Zvfbfwma'. +--- + .../riscv/riscv-vector-builtins-bases.cc | 69 +++++++++++++++++++ + .../riscv/riscv-vector-builtins-bases.h | 7 ++ + .../riscv/riscv-vector-builtins-functions.def | 15 ++++ + .../riscv/riscv-vector-builtins-shapes.cc | 31 ++++++++- + .../riscv/riscv-vector-builtins-types.def | 13 ++++ + gcc/config/riscv/riscv-vector-builtins.cc | 67 ++++++++++++++++++ + gcc/config/riscv/riscv-vector-builtins.h | 34 ++++++--- + gcc/config/riscv/riscv.cc | 13 ++-- + 8 files changed, 232 insertions(+), 17 deletions(-) + +diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc +index 3450c69979c..12f8438675b 100644 +--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc ++++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc +@@ -2428,6 +2428,60 @@ public: + } + }; + ++/* Implements vfncvtbf16_f. */ ++template ++class vfncvtbf16_f : public function_base ++{ ++public: ++ bool has_rounding_mode_operand_p () const override ++ { ++ return FRM_OP == HAS_FRM; ++ } ++ ++ bool may_require_frm_p () const override { return true; } ++ ++ rtx expand (function_expander &e) const override ++ { ++ return e.use_exact_insn (code_for_pred_trunc_to_bf16 (e.vector_mode ())); ++ } ++}; ++ ++/* Implements vfwcvtbf16_f. */ ++class vfwcvtbf16_f : public function_base ++{ ++public: ++ rtx expand (function_expander &e) const override ++ { ++ return e.use_exact_insn (code_for_pred_extend_bf16_to (e.vector_mode ())); ++ } ++}; ++ ++/* Implements vfwmaccbf16. */ ++template ++class vfwmaccbf16 : public function_base ++{ ++public: ++ bool has_rounding_mode_operand_p () const override ++ { ++ return FRM_OP == HAS_FRM; ++ } ++ ++ bool may_require_frm_p () const override { return true; } ++ ++ bool has_merge_operand_p () const override { return false; } ++ ++ rtx expand (function_expander &e) const override ++ { ++ if (e.op_info->op == OP_TYPE_vf) ++ return e.use_widen_ternop_insn ( ++ code_for_pred_widen_bf16_mul_scalar (e.vector_mode ())); ++ if (e.op_info->op == OP_TYPE_vv) ++ return e.use_widen_ternop_insn ( ++ code_for_pred_widen_bf16_mul (e.vector_mode ())); ++ gcc_unreachable (); ++ } ++}; ++ + static CONSTEXPR const vsetvl vsetvl_obj; + static CONSTEXPR const vsetvl vsetvlmax_obj; + static CONSTEXPR const loadstore vle_obj; +@@ -2745,6 +2799,14 @@ static CONSTEXPR const crypto_vv vsm4r_obj; + static CONSTEXPR const vsm3me vsm3me_obj; + static CONSTEXPR const vaeskf2_vsm3c vsm3c_obj; + ++/* Zvfbfmin */ ++static CONSTEXPR const vfncvtbf16_f vfncvtbf16_f_obj; ++static CONSTEXPR const vfncvtbf16_f vfncvtbf16_f_frm_obj; ++static CONSTEXPR const vfwcvtbf16_f vfwcvtbf16_f_obj; ++/* Zvfbfwma; */ ++static CONSTEXPR const vfwmaccbf16 vfwmaccbf16_obj; ++static CONSTEXPR const vfwmaccbf16 vfwmaccbf16_frm_obj; ++ + /* Declare the function base NAME, pointing it to an instance + of class _obj. */ + #define BASE(NAME) \ +@@ -3065,4 +3127,11 @@ BASE (vsm4k) + BASE (vsm4r) + BASE (vsm3me) + BASE (vsm3c) ++/* Zvfbfmin */ ++BASE (vfncvtbf16_f) ++BASE (vfncvtbf16_f_frm) ++BASE (vfwcvtbf16_f) ++/* Zvfbfwma */ ++BASE (vfwmaccbf16) ++BASE (vfwmaccbf16_frm) + } // end namespace riscv_vector +diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h +index 1f2c94d3541..af1cb1af50f 100644 +--- a/gcc/config/riscv/riscv-vector-builtins-bases.h ++++ b/gcc/config/riscv/riscv-vector-builtins-bases.h +@@ -339,6 +339,13 @@ extern const function_base *const vsm4k; + extern const function_base *const vsm4r; + extern const function_base *const vsm3me; + extern const function_base *const vsm3c; ++/* Zvfbfmin*/ ++extern const function_base *const vfncvtbf16_f; ++extern const function_base *const vfncvtbf16_f_frm; ++extern const function_base *const vfwcvtbf16_f; ++/* Zvfbfwma */ ++extern const function_base *const vfwmaccbf16; ++extern const function_base *const vfwmaccbf16_frm; + } + + } // end namespace riscv_vector +diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def +index f742c98be8a..b69cf3cae29 100644 +--- a/gcc/config/riscv/riscv-vector-builtins-functions.def ++++ b/gcc/config/riscv/riscv-vector-builtins-functions.def +@@ -747,4 +747,19 @@ DEF_RVV_FUNCTION (vsm4r, crypto_vv, none_tu_preds, u_vvs_crypto_sew32_lmul_x16_o + DEF_RVV_FUNCTION (vsm3me, no_mask_policy, none_tu_preds, u_vvv_crypto_sew32_ops) + DEF_RVV_FUNCTION (vsm3c, crypto_vi, none_tu_preds, u_vvv_size_crypto_sew32_ops) + #undef REQUIRED_EXTENSIONS ++ ++//Zvfbfmin ++#define REQUIRED_EXTENSIONS ZVFBFMIN_EXT ++DEF_RVV_FUNCTION (vfncvtbf16_f, narrow_alu, full_preds, f32_to_bf16_f_w_ops) ++DEF_RVV_FUNCTION (vfncvtbf16_f_frm, narrow_alu_frm, full_preds, f32_to_bf16_f_w_ops) ++DEF_RVV_FUNCTION (vfwcvtbf16_f, alu, full_preds, bf16_to_f32_f_v_ops) ++#undef REQUIRED_EXTENSIONS ++ ++/* Zvfbfwma */ ++#define REQUIRED_EXTENSIONS ZVFBFWMA_EXT ++DEF_RVV_FUNCTION (vfwmaccbf16, alu, full_preds, f32_wwvv_ops) ++DEF_RVV_FUNCTION (vfwmaccbf16, alu, full_preds, f32_wwfv_ops) ++DEF_RVV_FUNCTION (vfwmaccbf16_frm, alu_frm, full_preds, f32_wwvv_ops) ++DEF_RVV_FUNCTION (vfwmaccbf16_frm, alu_frm, full_preds, f32_wwfv_ops) ++#undef REQUIRED_EXTENSIONS + #undef DEF_RVV_FUNCTION +diff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.cc b/gcc/config/riscv/riscv-vector-builtins-shapes.cc +index a3ffa92e967..33395414aae 100644 +--- a/gcc/config/riscv/riscv-vector-builtins-shapes.cc ++++ b/gcc/config/riscv/riscv-vector-builtins-shapes.cc +@@ -78,6 +78,30 @@ build_one (function_builder &b, const function_group_info &group, + argument_types, group.required_extensions); + } + ++/* Determine whether the intrinsic supports the currently ++ processed vector type */ ++static bool ++supports_vectype_p (const function_group_info &group, unsigned int vec_type_idx) ++{ ++ int index = group.ops_infos.types[vec_type_idx].index; ++ if (index < VECTOR_TYPE_vbfloat16mf4_t || index > VECTOR_TYPE_vbfloat16m8_t) ++ return true; ++ /* Only judge for bf16 vector type */ ++ if (*group.shape == shapes::loadstore ++ || *group.shape == shapes::indexed_loadstore ++ || *group.shape == shapes::vundefined ++ || *group.shape == shapes::misc ++ || *group.shape == shapes::vset ++ || *group.shape == shapes::vget ++ || *group.shape == shapes::vcreate ++ || *group.shape == shapes::fault_load ++ || *group.shape == shapes::seg_loadstore ++ || *group.shape == shapes::seg_indexed_loadstore ++ || *group.shape == shapes::seg_fault_load) ++ return true; ++ return false; ++} ++ + /* Add a function instance for every operand && predicate && args + combination in GROUP. Take the function base name from GROUP && operand + suffix from operand_suffixes && mode suffix from type_suffixes && predication +@@ -91,7 +115,10 @@ build_all (function_builder &b, const function_group_info &group) + for (unsigned int vec_type_idx = 0; + group.ops_infos.types[vec_type_idx].index != NUM_VECTOR_TYPES; + ++vec_type_idx) +- build_one (b, group, pred_idx, vec_type_idx); ++ { ++ if (supports_vectype_p (group, vec_type_idx)) ++ build_one (b, group, pred_idx, vec_type_idx); ++ } + } + + /* Declare the function shape NAME, pointing it to an instance +@@ -100,7 +127,7 @@ build_all (function_builder &b, const function_group_info &group) + static CONSTEXPR const DEF##_def VAR##_obj; \ + namespace shapes { const function_shape *const VAR = &VAR##_obj; } + +-#define BASE_NAME_MAX_LEN 16 ++#define BASE_NAME_MAX_LEN 17 + + /* Base class for build. */ + struct build_base : public function_shape +diff --git a/gcc/config/riscv/riscv-vector-builtins-types.def b/gcc/config/riscv/riscv-vector-builtins-types.def +index e7fca4cca79..e85ca27bcf5 100644 +--- a/gcc/config/riscv/riscv-vector-builtins-types.def ++++ b/gcc/config/riscv/riscv-vector-builtins-types.def +@@ -133,6 +133,12 @@ along with GCC; see the file COPYING3. If not see + #define DEF_RVV_WCONVERT_F_OPS(TYPE, REQUIRE) + #endif + ++/* Use "DEF_RVV_F32_OPS" macro include all float32 vector type that will be ++ used in the bfloat16 intrinsic */ ++#ifndef DEF_RVV_F32_OPS ++#define DEF_RVV_F32_OPS(TYPE, REQUIRE) ++#endif ++ + /* Use "DEF_RVV_WI_OPS" macro include all signed integer can be widened which + will be iterated and registered as intrinsic functions. */ + #ifndef DEF_RVV_WI_OPS +@@ -615,6 +621,12 @@ DEF_RVV_WCONVERT_F_OPS (vfloat64m2_t, RVV_REQUIRE_ELEN_FP_64) + DEF_RVV_WCONVERT_F_OPS (vfloat64m4_t, RVV_REQUIRE_ELEN_FP_64) + DEF_RVV_WCONVERT_F_OPS (vfloat64m8_t, RVV_REQUIRE_ELEN_FP_64) + ++DEF_RVV_F32_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_MIN_VLEN_64) ++DEF_RVV_F32_OPS (vfloat32m1_t, RVV_REQUIRE_ELEN_FP_32) ++DEF_RVV_F32_OPS (vfloat32m2_t, RVV_REQUIRE_ELEN_FP_32) ++DEF_RVV_F32_OPS (vfloat32m4_t, RVV_REQUIRE_ELEN_FP_32) ++DEF_RVV_F32_OPS (vfloat32m8_t, RVV_REQUIRE_ELEN_FP_32) ++ + DEF_RVV_WI_OPS (vint8mf8_t, RVV_REQUIRE_MIN_VLEN_64) + DEF_RVV_WI_OPS (vint8mf4_t, 0) + DEF_RVV_WI_OPS (vint8mf2_t, 0) +@@ -1481,3 +1493,4 @@ DEF_RVV_CRYPTO_SEW64_OPS (vuint64m8_t, RVV_REQUIRE_ELEN_64) + #undef DEF_RVV_TUPLE_OPS + #undef DEF_RVV_CRYPTO_SEW32_OPS + #undef DEF_RVV_CRYPTO_SEW64_OPS ++#undef DEF_RVV_F32_OPS +diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc +index 2d7e62deb08..b9938973832 100644 +--- a/gcc/config/riscv/riscv-vector-builtins.cc ++++ b/gcc/config/riscv/riscv-vector-builtins.cc +@@ -242,6 +242,12 @@ static const rvv_type_info wconvert_f_ops[] = { + #include "riscv-vector-builtins-types.def" + {NUM_VECTOR_TYPES, 0}}; + ++/* A list of all floating-point will be registered for intrinsic functions. */ ++static const rvv_type_info f32_ops[] = { ++#define DEF_RVV_F32_OPS(TYPE, REQUIRE) {VECTOR_TYPE_##TYPE, REQUIRE}, ++#include "riscv-vector-builtins-types.def" ++ {NUM_VECTOR_TYPES, 0}}; ++ + /* A list of all integer will be registered for intrinsic functions. */ + static const rvv_type_info iu_ops[] = { + #define DEF_RVV_I_OPS(TYPE, REQUIRE) {VECTOR_TYPE_##TYPE, REQUIRE}, +@@ -757,6 +763,25 @@ static CONSTEXPR const rvv_arg_type_info trunc_f_v_args[] + static CONSTEXPR const rvv_arg_type_info w_v_args[] + = {rvv_arg_type_info (RVV_BASE_double_trunc_vector), rvv_arg_type_info_end}; + ++/* A list of args for vector_type func (vector_type) function. */ ++static CONSTEXPR const rvv_arg_type_info bf_w_v_args[] ++ = {rvv_arg_type_info (RVV_BASE_double_trunc_bfloat_vector), ++ rvv_arg_type_info_end}; ++ ++/* A list of args for vector_type func (vector_type) function. */ ++static CONSTEXPR const rvv_arg_type_info bf_wwvv_args[] ++ = {rvv_arg_type_info (RVV_BASE_vector), ++ rvv_arg_type_info (RVV_BASE_double_trunc_bfloat_vector), ++ rvv_arg_type_info (RVV_BASE_double_trunc_bfloat_vector), ++ rvv_arg_type_info_end}; ++ ++/* A list of args for vector_type func (vector_type) function. */ ++static CONSTEXPR const rvv_arg_type_info bf_wwxv_args[] ++ = {rvv_arg_type_info (RVV_BASE_vector), ++ rvv_arg_type_info (RVV_BASE_double_trunc_bfloat_scalar), ++ rvv_arg_type_info (RVV_BASE_double_trunc_bfloat_vector), ++ rvv_arg_type_info_end}; ++ + /* A list of args for vector_type func (vector_type) function. */ + static CONSTEXPR const rvv_arg_type_info m_args[] + = {rvv_arg_type_info (RVV_BASE_mask), rvv_arg_type_info_end}; +@@ -1749,6 +1774,38 @@ static CONSTEXPR const rvv_op_info f_to_nf_f_w_ops + rvv_arg_type_info (RVV_BASE_double_trunc_float_vector), /* Return type */ + v_args /* Args */}; + ++/* A static operand information for vector_type func (vector_type) ++ * function registration. */ ++static CONSTEXPR const rvv_op_info f32_to_bf16_f_w_ops ++ = {f32_ops, /* Types */ ++ OP_TYPE_f_w, /* Suffix */ ++ rvv_arg_type_info (RVV_BASE_double_trunc_bfloat_vector), /* Return type */ ++ v_args /* Args */}; ++ ++/* A static operand information for vector_type func (vector_type) ++ * function registration. */ ++static CONSTEXPR const rvv_op_info bf16_to_f32_f_v_ops ++ = {f32_ops, /* Types */ ++ OP_TYPE_f_v, /* Suffix */ ++ rvv_arg_type_info (RVV_BASE_vector), /* Return type */ ++ bf_w_v_args /* Args */}; ++ ++/* A static operand information for vector_type func (vector_type, double demote ++ * type, double demote type) function registration. */ ++static CONSTEXPR const rvv_op_info f32_wwvv_ops ++ = {f32_ops, /* Types */ ++ OP_TYPE_vv, /* Suffix */ ++ rvv_arg_type_info (RVV_BASE_vector), /* Return type */ ++ bf_wwvv_args /* Args */}; ++ ++/* A static operand information for vector_type func (vector_type, double demote ++ * scalar_type, double demote type) function registration. */ ++static CONSTEXPR const rvv_op_info f32_wwfv_ops ++ = {f32_ops, /* Types */ ++ OP_TYPE_vf, /* Suffix */ ++ rvv_arg_type_info (RVV_BASE_vector), /* Return type */ ++ bf_wwxv_args /* Args */}; ++ + /* A static operand information for vector_type func (vector_type) + * function registration. */ + static CONSTEXPR const rvv_op_info all_v_ops +@@ -4643,6 +4700,16 @@ validate_instance_type_required_extensions (const rvv_type_info type, + { + uint64_t exts = type.required_extensions; + ++ if ((exts & RVV_REQUIRE_ELEN_BF_16) ++ && !TARGET_VECTOR_ELEN_BF_16_P (riscv_vector_elen_flags)) ++ { ++ error_at (EXPR_LOCATION (exp), ++ "built-in function %qE requires the " ++ "zvfbfmin or zvfbfwma ISA extension", ++ exp); ++ return false; ++ } ++ + if ((exts & RVV_REQUIRE_ELEN_FP_16) + && !TARGET_VECTOR_ELEN_FP_16_P (riscv_vector_elen_flags)) + { +diff --git a/gcc/config/riscv/riscv-vector-builtins.h b/gcc/config/riscv/riscv-vector-builtins.h +index 56dbe2cf0e2..ef4148380c2 100644 +--- a/gcc/config/riscv/riscv-vector-builtins.h ++++ b/gcc/config/riscv/riscv-vector-builtins.h +@@ -114,17 +114,19 @@ static const unsigned int CP_WRITE_CSR = 1U << 5; + /* Enumerates the required extensions. */ + enum required_ext + { +- VECTOR_EXT, /* Vector extension */ +- ZVBB_EXT, /* Cryto vector Zvbb sub-ext */ +- ZVBB_OR_ZVKB_EXT, /* Cryto vector Zvbb or zvkb sub-ext */ +- ZVBC_EXT, /* Crypto vector Zvbc sub-ext */ +- ZVKG_EXT, /* Crypto vector Zvkg sub-ext */ +- ZVKNED_EXT, /* Crypto vector Zvkned sub-ext */ ++ VECTOR_EXT, /* Vector extension */ ++ ZVBB_EXT, /* Cryto vector Zvbb sub-ext */ ++ ZVBB_OR_ZVKB_EXT, /* Cryto vector Zvbb or zvkb sub-ext */ ++ ZVBC_EXT, /* Crypto vector Zvbc sub-ext */ ++ ZVKG_EXT, /* Crypto vector Zvkg sub-ext */ ++ ZVKNED_EXT, /* Crypto vector Zvkned sub-ext */ + ZVKNHA_OR_ZVKNHB_EXT, /* Crypto vector Zvknh[ab] sub-ext */ +- ZVKNHB_EXT, /* Crypto vector Zvknhb sub-ext */ +- ZVKSED_EXT, /* Crypto vector Zvksed sub-ext */ +- ZVKSH_EXT, /* Crypto vector Zvksh sub-ext */ +- XTHEADVECTOR_EXT, /* XTheadVector extension */ ++ ZVKNHB_EXT, /* Crypto vector Zvknhb sub-ext */ ++ ZVKSED_EXT, /* Crypto vector Zvksed sub-ext */ ++ ZVKSH_EXT, /* Crypto vector Zvksh sub-ext */ ++ XTHEADVECTOR_EXT, /* XTheadVector extension */ ++ ZVFBFMIN_EXT, /* Zvfbfmin externsion */ ++ ZVFBFWMA_EXT, /* Zvfbfwma extension */ + /* Please update below to isa_name func when add or remove enum type(s). */ + }; + +@@ -154,6 +156,10 @@ static inline const char * reqired_ext_to_isa_name (enum required_ext required) + return "zvksh"; + case XTHEADVECTOR_EXT: + return "xthreadvector"; ++ case ZVFBFMIN_EXT: ++ return "zvfbfmin"; ++ case ZVFBFWMA_EXT: ++ return "zvfbfwma"; + default: + gcc_unreachable (); + } +@@ -187,6 +193,10 @@ static inline bool required_extensions_specified (enum required_ext required) + return TARGET_ZVKSH; + case XTHEADVECTOR_EXT: + return TARGET_XTHEADVECTOR; ++ case ZVFBFMIN_EXT: ++ return TARGET_ZVFBFMIN; ++ case ZVFBFWMA_EXT: ++ return TARGET_ZVFBFWMA; + default: + gcc_unreachable (); + } +@@ -323,6 +333,10 @@ struct function_group_info + return TARGET_ZVKSH; + case XTHEADVECTOR_EXT: + return TARGET_XTHEADVECTOR; ++ case ZVFBFMIN_EXT: ++ return TARGET_ZVFBFMIN; ++ case ZVFBFWMA_EXT: ++ return TARGET_ZVFBFWMA; + default: + gcc_unreachable (); + } +diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc +index 7022ec7f5bf..f9fb830b933 100644 +--- a/gcc/config/riscv/riscv.cc ++++ b/gcc/config/riscv/riscv.cc +@@ -5644,11 +5644,14 @@ riscv_validate_vector_type (const_tree type, const char *hint) + bool float_type_p = riscv_vector_float_type_p (type); + + if (float_type_p && element_bitsize == 16 +- && !TARGET_VECTOR_ELEN_FP_16_P (riscv_vector_elen_flags)) +- { +- error_at (input_location, +- "%s %qT requires the zvfhmin or zvfh ISA extension", +- hint, type); ++ && (!TARGET_VECTOR_ELEN_FP_16_P (riscv_vector_elen_flags) ++ && !TARGET_VECTOR_ELEN_BF_16_P (riscv_vector_elen_flags))) ++ { ++ const char *name = IDENTIFIER_POINTER (DECL_NAME (TYPE_NAME (type))); ++ if (strstr (name, "vfloat")) ++ error_at (input_location, ++ "%s %qT requires the zvfhmin or zvfh ISA extension", ++ hint, type); + return; + } + +-- +2.47.3 + diff --git a/1010-RISC-V-Fix-ICE-for-vector-single-width-integer-multi.patch b/1010-RISC-V-Fix-ICE-for-vector-single-width-integer-multi.patch new file mode 100644 index 0000000..1e088d4 --- /dev/null +++ b/1010-RISC-V-Fix-ICE-for-vector-single-width-integer-multi.patch @@ -0,0 +1,288 @@ +From dd129ccbae1377f0ca22092720320933f57d1d17 Mon Sep 17 00:00:00 2001 +From: Jin Ma +Date: Sat, 17 Aug 2024 10:18:03 -0600 +Subject: [PATCH 1010/1087] RISC-V: Fix ICE for vector single-width integer + multiply-add intrinsics + +commit 6d734ba485547329599f12bea63842a4fba8d72c upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +When rs1 is the immediate 0, the following ICE occurs: + +error: unrecognizable insn: +(insn 8 5 12 2 (set (reg:RVVM1DI 134 [ ]) + (if_then_else:RVVM1DI (unspec:RVVMF64BI [ + (const_vector:RVVMF64BI repeat [ + (const_int 1 [0x1]) + ]) + (reg/v:DI 137 [ vl ]) + (const_int 2 [0x2]) repeated x2 + (const_int 0 [0]) + (reg:SI 66 vl) + (reg:SI 67 vtype) + ] UNSPEC_VPREDICATE) + (plus:RVVM1DI (mult:RVVM1DI (vec_duplicate:RVVM1DI (const_int 0 [0])) + (reg/v:RVVM1DI 136 [ vs2 ])) + (reg/v:RVVM1DI 135 [ vd ])) + (reg/v:RVVM1DI 135 [ vd ]))) + +gcc/ChangeLog: + + * config/riscv/vector.md: Allow scalar operand to be 0. + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/rvv/base/bug-7.c: New test. + * gcc.target/riscv/rvv/base/bug-8.c: New test. +--- + gcc/config/riscv/vector.md | 80 +++++++++---------- + .../gcc.target/riscv/rvv/base/bug-7.c | 26 ++++++ + .../gcc.target/riscv/rvv/base/bug-8.c | 26 ++++++ + 3 files changed, 92 insertions(+), 40 deletions(-) + create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/bug-7.c + create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/bug-8.c + +diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md +index ec87a13579a..db6425f71a5 100644 +--- a/gcc/config/riscv/vector.md ++++ b/gcc/config/riscv/vector.md +@@ -5665,16 +5665,16 @@ + (plus:V_VLSI + (mult:V_VLSI + (vec_duplicate:V_VLSI +- (match_operand: 2 "register_operand" " r, r, r, r")) ++ (match_operand: 2 "reg_or_0_operand" " rJ, rJ, rJ, rJ")) + (match_operand:V_VLSI 3 "register_operand" " 0, vr, 0, vr")) + (match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr")) + (match_dup 3)))] + "TARGET_VECTOR" + "@ +- vmadd.vx\t%0,%2,%4%p1 +- vmv%m3r.v\t%0,%3\;vmadd.vx\t%0,%2,%4%p1 +- vmadd.vx\t%0,%2,%4%p1 +- vmv%m3r.v\t%0,%3\;vmadd.vx\t%0,%2,%4%p1" ++ vmadd.vx\t%0,%z2,%4%p1 ++ vmv%m3r.v\t%0,%3\;vmadd.vx\t%0,%z2,%4%p1 ++ vmadd.vx\t%0,%z2,%4%p1 ++ vmv%m3r.v\t%0,%3\;vmadd.vx\t%0,%z2,%4%p1" + [(set_attr "type" "vimuladd") + (set_attr "mode" "") + (set_attr "merge_op_idx" "3") +@@ -5697,16 +5697,16 @@ + (plus:V_VLSI + (mult:V_VLSI + (vec_duplicate:V_VLSI +- (match_operand: 2 "register_operand" " r, r, r, r")) ++ (match_operand: 2 "reg_or_0_operand" " rJ, rJ, rJ, rJ")) + (match_operand:V_VLSI 3 "register_operand" " vr, vr, vr, vr")) + (match_operand:V_VLSI 4 "register_operand" " 0, vr, 0, vr")) + (match_dup 4)))] + "TARGET_VECTOR" + "@ +- vmacc.vx\t%0,%2,%3%p1 +- vmv%m4r.v\t%0,%4\;vmacc.vx\t%0,%2,%3%p1 +- vmacc.vx\t%0,%2,%3%p1 +- vmv%m4r.v\t%0,%4\;vmacc.vx\t%0,%2,%3%p1" ++ vmacc.vx\t%0,%z2,%3%p1 ++ vmv%m4r.v\t%0,%4\;vmacc.vx\t%0,%z2,%3%p1 ++ vmacc.vx\t%0,%z2,%3%p1 ++ vmv%m4r.v\t%0,%4\;vmacc.vx\t%0,%z2,%3%p1" + [(set_attr "type" "vimuladd") + (set_attr "mode" "") + (set_attr "merge_op_idx" "4") +@@ -5765,16 +5765,16 @@ + (mult:V_VLSI_D + (vec_duplicate:V_VLSI_D + (sign_extend: +- (match_operand: 2 "register_operand" " r, r, r, r"))) ++ (match_operand: 2 "reg_or_0_operand" " rJ, rJ, rJ, rJ"))) + (match_operand:V_VLSI_D 3 "register_operand" " 0, vr, 0, vr")) + (match_operand:V_VLSI_D 4 "register_operand" " vr, vr, vr, vr")) + (match_dup 3)))] + "TARGET_VECTOR && !TARGET_64BIT" + "@ +- vmadd.vx\t%0,%2,%4%p1 +- vmv%m2r.v\t%0,%2\;vmadd.vx\t%0,%2,%4%p1 +- vmadd.vx\t%0,%2,%4%p1 +- vmv%m2r.v\t%0,%2\;vmadd.vx\t%0,%2,%4%p1" ++ vmadd.vx\t%0,%z2,%4%p1 ++ vmv%m2r.v\t%0,%z2\;vmadd.vx\t%0,%z2,%4%p1 ++ vmadd.vx\t%0,%z2,%4%p1 ++ vmv%m2r.v\t%0,%z2\;vmadd.vx\t%0,%z2,%4%p1" + [(set_attr "type" "vimuladd") + (set_attr "mode" "") + (set_attr "merge_op_idx" "3") +@@ -5798,16 +5798,16 @@ + (mult:V_VLSI_D + (vec_duplicate:V_VLSI_D + (sign_extend: +- (match_operand: 2 "register_operand" " r, r, r, r"))) ++ (match_operand: 2 "reg_or_0_operand" " rJ, rJ, rJ, rJ"))) + (match_operand:V_VLSI_D 3 "register_operand" " vr, vr, vr, vr")) + (match_operand:V_VLSI_D 4 "register_operand" " 0, vr, 0, vr")) + (match_dup 4)))] + "TARGET_VECTOR && !TARGET_64BIT" + "@ +- vmacc.vx\t%0,%2,%3%p1 +- vmv%m4r.v\t%0,%4\;vmacc.vx\t%0,%2,%3%p1 +- vmacc.vx\t%0,%2,%3%p1 +- vmv%m4r.v\t%0,%4\;vmacc.vx\t%0,%2,%3%p1" ++ vmacc.vx\t%0,%z2,%3%p1 ++ vmv%m4r.v\t%0,%4\;vmacc.vx\t%0,%z2,%3%p1 ++ vmacc.vx\t%0,%z2,%3%p1 ++ vmv%m4r.v\t%0,%4\;vmacc.vx\t%0,%z2,%3%p1" + [(set_attr "type" "vimuladd") + (set_attr "mode" "") + (set_attr "merge_op_idx" "4") +@@ -5964,15 +5964,15 @@ + (match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr") + (mult:V_VLSI + (vec_duplicate:V_VLSI +- (match_operand: 2 "register_operand" " r, r, r, r")) ++ (match_operand: 2 "reg_or_0_operand" " rJ, rJ, rJ, rJ")) + (match_operand:V_VLSI 3 "register_operand" " 0, vr, 0, vr"))) + (match_dup 3)))] + "TARGET_VECTOR" + "@ +- vnmsub.vx\t%0,%2,%4%p1 +- vmv%m3r.v\t%0,%3\;vnmsub.vx\t%0,%2,%4%p1 +- vnmsub.vx\t%0,%2,%4%p1 +- vmv%m3r.v\t%0,%3\;vnmsub.vx\t%0,%2,%4%p1" ++ vnmsub.vx\t%0,%z2,%4%p1 ++ vmv%m3r.v\t%0,%3\;vnmsub.vx\t%0,%z2,%4%p1 ++ vnmsub.vx\t%0,%z2,%4%p1 ++ vmv%m3r.v\t%0,%3\;vnmsub.vx\t%0,%z2,%4%p1" + [(set_attr "type" "vimuladd") + (set_attr "mode" "") + (set_attr "merge_op_idx" "3") +@@ -5996,15 +5996,15 @@ + (match_operand:V_VLSI 4 "register_operand" " 0, vr, 0, vr") + (mult:V_VLSI + (vec_duplicate:V_VLSI +- (match_operand: 2 "register_operand" " r, r, r, r")) ++ (match_operand: 2 "reg_or_0_operand" " rJ, rJ, rJ, rJ")) + (match_operand:V_VLSI 3 "register_operand" " vr, vr, vr, vr"))) + (match_dup 4)))] + "TARGET_VECTOR" + "@ +- vnmsac.vx\t%0,%2,%3%p1 +- vmv%m4r.v\t%0,%4\;vnmsac.vx\t%0,%2,%3%p1 +- vnmsac.vx\t%0,%2,%3%p1 +- vmv%m4r.v\t%0,%4\;vnmsac.vx\t%0,%2,%3%p1" ++ vnmsac.vx\t%0,%z2,%3%p1 ++ vmv%m4r.v\t%0,%4\;vnmsac.vx\t%0,%z2,%3%p1 ++ vnmsac.vx\t%0,%z2,%3%p1 ++ vmv%m4r.v\t%0,%4\;vnmsac.vx\t%0,%z2,%3%p1" + [(set_attr "type" "vimuladd") + (set_attr "mode" "") + (set_attr "merge_op_idx" "4") +@@ -6064,15 +6064,15 @@ + (mult:V_VLSI_D + (vec_duplicate:V_VLSI_D + (sign_extend: +- (match_operand: 2 "register_operand" " r, r, r, r"))) ++ (match_operand: 2 "reg_or_0_operand" " rJ, rJ, rJ, rJ"))) + (match_operand:V_VLSI_D 3 "register_operand" " 0, vr, 0, vr"))) + (match_dup 3)))] + "TARGET_VECTOR && !TARGET_64BIT" + "@ +- vnmsub.vx\t%0,%2,%4%p1 +- vmv%m3r.v\t%0,%3\;vnmsub.vx\t%0,%2,%4%p1 +- vnmsub.vx\t%0,%2,%4%p1 +- vmv%m3r.v\t%0,%3\;vnmsub.vx\t%0,%2,%4%p1" ++ vnmsub.vx\t%0,%z2,%4%p1 ++ vmv%m3r.v\t%0,%3\;vnmsub.vx\t%0,%z2,%4%p1 ++ vnmsub.vx\t%0,%z2,%4%p1 ++ vmv%m3r.v\t%0,%3\;vnmsub.vx\t%0,%z2,%4%p1" + [(set_attr "type" "vimuladd") + (set_attr "mode" "") + (set_attr "merge_op_idx" "3") +@@ -6097,15 +6097,15 @@ + (mult:V_VLSI_D + (vec_duplicate:V_VLSI_D + (sign_extend: +- (match_operand: 2 "register_operand" " r, r, r, r"))) ++ (match_operand: 2 "reg_or_0_operand" " rJ, rJ, rJ, rJ"))) + (match_operand:V_VLSI_D 3 "register_operand" " vr, vr, vr, vr"))) + (match_dup 4)))] + "TARGET_VECTOR && !TARGET_64BIT" + "@ +- vnmsac.vx\t%0,%2,%3%p1 +- vmv%m4r.v\t%0,%4\;vnmsac.vx\t%0,%2,%3%p1 +- vnmsac.vx\t%0,%2,%3%p1 +- vmv%m4r.v\t%0,%4\;vnmsac.vx\t%0,%2,%3%p1" ++ vnmsac.vx\t%0,%z2,%3%p1 ++ vmv%m4r.v\t%0,%4\;vnmsac.vx\t%0,%z2,%3%p1 ++ vnmsac.vx\t%0,%z2,%3%p1 ++ vmv%m4r.v\t%0,%4\;vnmsac.vx\t%0,%z2,%3%p1" + [(set_attr "type" "vimuladd") + (set_attr "mode" "") + (set_attr "merge_op_idx" "4") +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-7.c +new file mode 100644 +index 00000000000..28766ce860f +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-7.c +@@ -0,0 +1,26 @@ ++/* Test that we do not have ice when compile */ ++/* { dg-do assemble } */ ++/* { dg-options "-march=rv64gcv -mabi=lp64d -O2" { target { rv64 } } } */ ++/* { dg-options "-march=rv32gcv -mabi=ilp32d -O2" { target { rv32 } } } */ ++ ++#include ++ ++vint64m1_t f1 (vint64m1_t vd, vint64m1_t vs2, size_t vl) ++{ ++ return __riscv_vmacc_vx_i64m1 (vd, 0, vs2, vl); ++} ++ ++vint64m1_t f2 (vint64m1_t vd, vint64m1_t vs2, size_t vl) ++{ ++ return __riscv_vnmsac_vx_i64m1 (vd, 0, vs2, vl); ++} ++ ++vint64m8_t f3 (vint64m8_t vd, vint64m8_t vs2, size_t vl) ++{ ++ return __riscv_vmadd_vx_i64m8 (vd, 0, vs2, vl); ++} ++ ++vint64m1_t f4 (vint64m1_t vd, vint64m1_t vs2, size_t vl) ++{ ++ return __riscv_vnmsub_vx_i64m1 (vd, 0, vs2, vl); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-8.c +new file mode 100644 +index 00000000000..975f75581a1 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-8.c +@@ -0,0 +1,26 @@ ++/* Test that we do not have ice when compile */ ++/* { dg-do assemble } */ ++/* { dg-options "-march=rv64gcv -mabi=lp64d -O0" { target { rv64 } } } */ ++/* { dg-options "-march=rv32gcv -mabi=ilp32d -O0" { target { rv32 } } } */ ++ ++#include ++ ++vint64m1_t f1 (vint64m1_t vd, vint64m1_t vs2, size_t vl) ++{ ++ return __riscv_vmacc_vx_i64m1 (vd, 0, vs2, vl); ++} ++ ++vint64m1_t f2 (vint64m1_t vd, vint64m1_t vs2, size_t vl) ++{ ++ return __riscv_vnmsac_vx_i64m1 (vd, 0, vs2, vl); ++} ++ ++vint64m8_t f3 (vint64m8_t vd, vint64m8_t vs2, size_t vl) ++{ ++ return __riscv_vmadd_vx_i64m8 (vd, 0, vs2, vl); ++} ++ ++vint64m1_t f4 (vint64m1_t vd, vint64m1_t vs2, size_t vl) ++{ ++ return __riscv_vnmsub_vx_i64m1 (vd, 0, vs2, vl); ++} +-- +2.47.3 + diff --git a/1011-RISC-V-Minimal-support-for-Zimop-extension.patch b/1011-RISC-V-Minimal-support-for-Zimop-extension.patch new file mode 100644 index 0000000..96efaf2 --- /dev/null +++ b/1011-RISC-V-Minimal-support-for-Zimop-extension.patch @@ -0,0 +1,108 @@ +From 17551de9083a34c520c8b39501625f5ba623faf1 Mon Sep 17 00:00:00 2001 +From: Jiawei +Date: Fri, 2 Aug 2024 23:23:14 +0800 +Subject: [PATCH 1011/1087] RISC-V: Minimal support for Zimop extension. + +commit c8f3fdd53871a20838be532b58ef610bf1dd75e1 upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +This patch support Zimop and Zcmop extension[1].To enable GCC to recognize +and process Zimop and Zcmop extension correctly at compile time. + +https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc + +gcc/ChangeLog: + + * common/config/riscv/riscv-common.cc: New extension. + * config/riscv/riscv.opt: New mask. + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/arch-42.c: New test. + * gcc.target/riscv/arch-43.c: New test. +--- + gcc/common/config/riscv/riscv-common.cc | 8 ++++++++ + gcc/config/riscv/riscv.opt | 7 +++++++ + gcc/testsuite/gcc.target/riscv/arch-42.c | 5 +++++ + gcc/testsuite/gcc.target/riscv/arch-43.c | 5 +++++ + 4 files changed, 25 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/riscv/arch-42.c + create mode 100644 gcc/testsuite/gcc.target/riscv/arch-43.c + +diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc +index dd716166bd8..06600b8ca69 100644 +--- a/gcc/common/config/riscv/riscv-common.cc ++++ b/gcc/common/config/riscv/riscv-common.cc +@@ -83,6 +83,8 @@ static const riscv_implied_info_t riscv_implied_info[] = + {"zfinx", "zicsr"}, + {"zdinx", "zicsr"}, + ++ {"zcmop", "zca"}, ++ + {"zk", "zkn"}, + {"zk", "zkr"}, + {"zk", "zkt"}, +@@ -289,6 +291,9 @@ static const struct riscv_ext_version riscv_ext_version_table[] = + {"zicclsm", ISA_SPEC_CLASS_NONE, 1, 0}, + {"ziccrse", ISA_SPEC_CLASS_NONE, 1, 0}, + ++ {"zimop", ISA_SPEC_CLASS_NONE, 1, 0}, ++ {"zcmop", ISA_SPEC_CLASS_NONE, 1, 0}, ++ + {"zicntr", ISA_SPEC_CLASS_NONE, 2, 0}, + {"zihpm", ISA_SPEC_CLASS_NONE, 2, 0}, + +@@ -1569,6 +1574,9 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = + {"zicbop", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOP}, + {"zic64b", &gcc_options::x_riscv_zicmo_subext, MASK_ZIC64B}, + ++ {"zimop", &gcc_options::x_riscv_mop_subext, MASK_ZIMOP}, ++ {"zcmop", &gcc_options::x_riscv_mop_subext, MASK_ZCMOP}, ++ + {"zve32x", &gcc_options::x_target_flags, MASK_VECTOR}, + {"zve32f", &gcc_options::x_target_flags, MASK_VECTOR}, + {"zve64x", &gcc_options::x_target_flags, MASK_VECTOR}, +diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt +index ce7532364e5..ad5046e20fb 100644 +--- a/gcc/config/riscv/riscv.opt ++++ b/gcc/config/riscv/riscv.opt +@@ -390,6 +390,13 @@ Mask(ZICBOP) Var(riscv_zicmo_subext) + + Mask(ZIC64B) Var(riscv_zicmo_subext) + ++TargetVariable ++int riscv_mop_subext ++ ++Mask(ZIMOP) Var(riscv_mop_subext) ++ ++Mask(ZCMOP) Var(riscv_mop_subext) ++ + TargetVariable + int riscv_zf_subext + +diff --git a/gcc/testsuite/gcc.target/riscv/arch-42.c b/gcc/testsuite/gcc.target/riscv/arch-42.c +new file mode 100644 +index 00000000000..83f78d28dbe +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/arch-42.c +@@ -0,0 +1,5 @@ ++/* { dg-do compile } */ ++/* { dg-options "-march=rv64i_zimop -mabi=lp64" } */ ++int foo() ++{ ++} +diff --git a/gcc/testsuite/gcc.target/riscv/arch-43.c b/gcc/testsuite/gcc.target/riscv/arch-43.c +new file mode 100644 +index 00000000000..4a300a165fd +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/arch-43.c +@@ -0,0 +1,5 @@ ++/* { dg-do compile } */ ++/* { dg-options "-march=rv64i_zcmop -mabi=lp64" } */ ++int foo() ++{ ++} +-- +2.47.3 + diff --git a/1012-driver-Fix-multilib_os_dir-and-multiarch_dir-for-tho.patch b/1012-driver-Fix-multilib_os_dir-and-multiarch_dir-for-tho.patch new file mode 100644 index 0000000..996a8aa --- /dev/null +++ b/1012-driver-Fix-multilib_os_dir-and-multiarch_dir-for-tho.patch @@ -0,0 +1,195 @@ +From cdd2e7ba74ceaa142a2a0b0101fc348f4aad1327 Mon Sep 17 00:00:00 2001 +From: Kito Cheng +Date: Mon, 10 Mar 2025 16:26:04 +0800 +Subject: [PATCH 1012/1087] driver: Fix multilib_os_dir and multiarch_dir for + those target use TARGET_COMPUTE_MULTILIB + +commit 447156e4d143d7f513c488dd0b44037524a01fba upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +This patch fixes the multilib_os_dir and multiarch_dir for those targets +that use TARGET_COMPUTE_MULTILIB, since the TARGET_COMPUTE_MULTILIB hook +only update/fix the multilib_dir but not the multilib_os_dir and multiarch_dir, +so the multilib_os_dir and multiarch_dir are not set correctly for those targets. + +Use RISC-V linux target (riscv64-unknown-linux-gnu) as an example: + +``` +$ riscv64-unknown-linux-gnu-gcc -print-multi-lib +.; +lib32/ilp32;@march=rv32imac@mabi=ilp32 +lib32/ilp32d;@march=rv32imafdc@mabi=ilp32d +lib64/lp64;@march=rv64imac@mabi=lp64 +lib64/lp64d;@march=rv64imafdc@mabi=lp64d +``` + +If we use the exactly same -march and -mabi options to compile a source file, +the multilib_os_dir and multiarch_dir are set correctly: + +``` +$ riscv64-unknown-linux-gnu-gcc -print-multi-os-directory -march=rv64imafdc -mabi=lp64d +../lib64/lp64d +$ riscv64-unknown-linux-gnu-gcc -print-multi-directory -march=rv64imafdc -mabi=lp64d +lib64/lp64d +``` + +However if we use the -march=rv64imafdcv -mabi=lp64d option to compile a source +file, the multilib_os_dir and multiarch_dir are not set correctly: +``` +$ riscv64-unknown-linux-gnu-gcc -print-multi-os-directory -march=rv64imafdc -mabi=lp64d +lib64/lp64d +$ riscv64-unknown-linux-gnu-gcc -print-multi-directory -march=rv64imafdc -mabi=lp64d +lib64/lp64d +``` + +That's because the TARGET_COMPUTE_MULTILIB hook only update/fix the multilib_dir +but not the multilib_os_dir, so the multilib_os_dir is blank and will use same +value as multilib_dir, but that is not correct. + +So we introduce second chance to fix the multilib_os_dir if it's not set, we do +also try to fix the multiarch_dir, because it may also not set correctly if +multilib_os_dir is not set. + +Changes since v1: +- Fix non-multilib build. +- Fix fix indentation. + +gcc/ChangeLog: + + * gcc.cc (find_multilib_os_dir_by_multilib_dir): New. + (set_multilib_dir): Fix multilib_os_dir and multiarch_dir + if multilib_os_dir is not set. +--- + gcc/gcc.cc | 108 ++++++++++++++++++++++++++++++++++++++++++++++++++++- + 1 file changed, 107 insertions(+), 1 deletion(-) + +diff --git a/gcc/gcc.cc b/gcc/gcc.cc +index fc9f1f545dc..13f3cb718d2 100644 +--- a/gcc/gcc.cc ++++ b/gcc/gcc.cc +@@ -9727,6 +9727,103 @@ default_arg (const char *p, int len) + return 0; + } + ++/* Use multilib_dir as key to find corresponding multilib_os_dir and ++ multiarch_dir. */ ++ ++static void ++find_multilib_os_dir_by_multilib_dir (const char *multilib_dir, ++ const char **p_multilib_os_dir, ++ const char **p_multiarch_dir) ++{ ++ const char *p = multilib_select; ++ unsigned int this_path_len; ++ const char *this_path; ++ int ok = 0; ++ ++ while (*p != '\0') ++ { ++ /* Ignore newlines. */ ++ if (*p == '\n') ++ { ++ ++p; ++ continue; ++ } ++ ++ /* Get the initial path. */ ++ this_path = p; ++ while (*p != ' ') ++ { ++ if (*p == '\0') ++ { ++ fatal_error (input_location, "multilib select %qs %qs is invalid", ++ multilib_select, multilib_reuse); ++ } ++ ++p; ++ } ++ this_path_len = p - this_path; ++ ++ ok = 0; ++ ++ /* Skip any arguments, we don't care at this stage. */ ++ while (*++p != ';'); ++ ++ if (this_path_len != 1 ++ || this_path[0] != '.') ++ { ++ char *new_multilib_dir = XNEWVEC (char, this_path_len + 1); ++ char *q; ++ ++ strncpy (new_multilib_dir, this_path, this_path_len); ++ new_multilib_dir[this_path_len] = '\0'; ++ q = strchr (new_multilib_dir, ':'); ++ if (q != NULL) ++ *q = '\0'; ++ ++ if (strcmp (new_multilib_dir, multilib_dir) == 0) ++ ok = 1; ++ } ++ ++ /* Found matched multilib_dir, update multilib_os_dir and ++ multiarch_dir. */ ++ if (ok) ++ { ++ const char *q = this_path, *end = this_path + this_path_len; ++ ++ while (q < end && *q != ':') ++ q++; ++ if (q < end) ++ { ++ const char *q2 = q + 1, *ml_end = end; ++ char *new_multilib_os_dir; ++ ++ while (q2 < end && *q2 != ':') ++ q2++; ++ if (*q2 == ':') ++ ml_end = q2; ++ if (ml_end - q == 1) ++ *p_multilib_os_dir = xstrdup ("."); ++ else ++ { ++ new_multilib_os_dir = XNEWVEC (char, ml_end - q); ++ memcpy (new_multilib_os_dir, q + 1, ml_end - q - 1); ++ new_multilib_os_dir[ml_end - q - 1] = '\0'; ++ *p_multilib_os_dir = new_multilib_os_dir; ++ } ++ ++ if (q2 < end && *q2 == ':') ++ { ++ char *new_multiarch_dir = XNEWVEC (char, end - q2); ++ memcpy (new_multiarch_dir, q2 + 1, end - q2 - 1); ++ new_multiarch_dir[end - q2 - 1] = '\0'; ++ *p_multiarch_dir = new_multiarch_dir; ++ } ++ break; ++ } ++ } ++ ++p; ++ } ++} ++ + /* Work out the subdirectory to use based on the options. The format of + multilib_select is a list of elements. Each element is a subdirectory + name followed by a list of options followed by a semicolon. The format +@@ -10005,7 +10102,16 @@ set_multilib_dir (void) + multilib_os_dir = NULL; + } + else if (multilib_dir != NULL && multilib_os_dir == NULL) +- multilib_os_dir = multilib_dir; ++ { ++ /* Give second chance to search matched multilib_os_dir again by matching ++ the multilib_dir since some target may use TARGET_COMPUTE_MULTILIB ++ hook rather than the builtin way. */ ++ find_multilib_os_dir_by_multilib_dir (multilib_dir, &multilib_os_dir, ++ &multiarch_dir); ++ ++ if (multilib_os_dir == NULL) ++ multilib_os_dir = multilib_dir; ++ } + } + + /* Print out the multiple library subdirectory selection +-- +2.47.3 + diff --git a/1013-RISC-V-Bugfix-for-RVV-rounding-intrinsic-ICE-in-func.patch b/1013-RISC-V-Bugfix-for-RVV-rounding-intrinsic-ICE-in-func.patch new file mode 100644 index 0000000..89ef75f --- /dev/null +++ b/1013-RISC-V-Bugfix-for-RVV-rounding-intrinsic-ICE-in-func.patch @@ -0,0 +1,115 @@ +From d8a2ed6a849da1d93cd26484ea30ada815bffe1a Mon Sep 17 00:00:00 2001 +From: Jin Ma +Date: Sat, 17 Aug 2024 09:29:11 -0600 +Subject: [PATCH 1013/1087] RISC-V: Bugfix for RVV rounding intrinsic ICE in + function checker + +commit 3f51684ac05f065a87c53d9506400cbe97af6b79 upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +When compiling an interface for rounding of type 'vfloat16*' without using zvfh +or zvfhmin, it is not enough to use FLOAT_MODE_P because the type does not +support it. Although the subsequent riscv_validate_vector_type checks will +still fail and throw exceptions, I don't think we should have ICE here. + +internal compiler error: in check, at config/riscv/riscv-vector-builtins-shapes.cc:444 + 10 | return __riscv_vfadd_vv_f16m1_rm (vs2, vs1, 0, vl); + | ^~~~~~ +0x4191794 internal_error(char const*, ...) + /iothome/jin.ma/code/master/gcc/gcc/diagnostic-global-context.cc:491 +0x416ebf5 fancy_abort(char const*, int, char const*) + /iothome/jin.ma/code/master/gcc/gcc/diagnostic.cc:1772 +0x220aae6 riscv_vector::build_frm_base::check(riscv_vector::function_checker&) const + /iothome/jin.ma/code/master/gcc/gcc/config/riscv/riscv-vector-builtins-shapes.cc:444 +0x2205323 riscv_vector::function_checker::check() + /iothome/jin.ma/code/master/gcc/gcc/config/riscv/riscv-vector-builtins.cc:4414 + +gcc/ChangeLog: + + * config/riscv/riscv-protos.h (riscv_vector_float_type_p): New. + * config/riscv/riscv-vector-builtins.cc (function_instance::any_type_float_p): + Use riscv_vector_float_type_p instead of FLOAT_MODE_P for judgment. + * config/riscv/riscv.cc (riscv_vector_int_type_p): Change static to extern. + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/rvv/base/bug-9.c: New test. +--- + gcc/config/riscv/riscv-protos.h | 1 + + gcc/config/riscv/riscv-vector-builtins.cc | 4 ++-- + gcc/config/riscv/riscv.cc | 5 ++++- + gcc/testsuite/gcc.target/riscv/rvv/base/bug-9.c | 13 +++++++++++++ + 4 files changed, 20 insertions(+), 3 deletions(-) + create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/bug-9.c + +diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h +index 99277e4e7c2..aa603301fdc 100644 +--- a/gcc/config/riscv/riscv-protos.h ++++ b/gcc/config/riscv/riscv-protos.h +@@ -165,6 +165,7 @@ extern bool riscv_shamt_matches_mask_p (int, HOST_WIDE_INT); + extern void riscv_subword_address (rtx, rtx *, rtx *, rtx *, rtx *); + extern void riscv_lshift_subword (machine_mode, rtx, rtx, rtx *); + extern enum memmodel riscv_union_memmodels (enum memmodel, enum memmodel); ++extern bool riscv_vector_float_type_p (const_tree type); + + /* Routines implemented in riscv-c.cc. */ + void riscv_cpu_cpp_builtins (cpp_reader *); +diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc +index b9938973832..3c189fd0d99 100644 +--- a/gcc/config/riscv/riscv-vector-builtins.cc ++++ b/gcc/config/riscv/riscv-vector-builtins.cc +@@ -3497,11 +3497,11 @@ function_instance::operator== (const function_instance &other) const + bool + function_instance::any_type_float_p () const + { +- if (FLOAT_MODE_P (TYPE_MODE (get_return_type ()))) ++ if (riscv_vector_float_type_p (get_return_type ())) + return true; + + for (int i = 0; op_info->args[i].base_type != NUM_BASE_TYPES; ++i) +- if (FLOAT_MODE_P (TYPE_MODE (get_arg_type (i)))) ++ if (riscv_vector_float_type_p (get_arg_type (i))) + return true; + + return false; +diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc +index f9fb830b933..ae37f26dbc6 100644 +--- a/gcc/config/riscv/riscv.cc ++++ b/gcc/config/riscv/riscv.cc +@@ -5547,9 +5547,12 @@ riscv_vector_int_type_p (const_tree type) + return strstr (name, "int") != NULL || strstr (name, "uint") != NULL; + } + +-static bool ++bool + riscv_vector_float_type_p (const_tree type) + { ++ if (!riscv_vector_type_p (type)) ++ return false; ++ + machine_mode mode = TYPE_MODE (type); + + if (VECTOR_MODE_P (mode)) +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-9.c +new file mode 100644 +index 00000000000..20ae9ebf6f2 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-9.c +@@ -0,0 +1,13 @@ ++/* Test that we do not have ice when compile */ ++/* { dg-do assemble } */ ++/* { dg-options "-march=rv64gcv -mabi=lp64d -O2" { target { rv64 } } } */ ++/* { dg-options "-march=rv32gcv -mabi=ilp32d -O2" { target { rv32 } } } */ ++ ++#include ++ ++vfloat16m1_t f0 (vfloat16m1_t vs2, vfloat16m1_t vs1, size_t vl) ++{ ++ return __riscv_vfadd_vv_f16m1_rm (vs2, vs1, 0, vl); ++} ++ ++/* { dg-error "return type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA extension" "" { target { "riscv*-*-*" } } 0 } */ +-- +2.47.3 + diff --git a/1014-RISC-V-Add-Zfbfmin-extension.patch b/1014-RISC-V-Add-Zfbfmin-extension.patch new file mode 100644 index 0000000..0a3251a --- /dev/null +++ b/1014-RISC-V-Add-Zfbfmin-extension.patch @@ -0,0 +1,371 @@ +From ae7ad84b00ea8bc0a81cba4dce2999507b4f2d22 Mon Sep 17 00:00:00 2001 +From: Xiao Zeng +Date: Wed, 15 May 2024 13:56:42 +0800 +Subject: [PATCH 1014/1087] RISC-V: Add Zfbfmin extension + +commit 4638e508aa814d4aa2e204c3ab041c6a56aad2bd +1 In the previous patch, the libcall for BF16 was implemented: + + +2 Riscv provides Zfbfmin extension, which completes the "Scalar BF16 Converts": + + +3 Implemented replacing libcall with Zfbfmin extension instruction. + +4 Reused previous testcases in: + +gcc/ChangeLog: + + * config/riscv/iterators.md: Add mode_iterator between + floating-point modes and BFmode. + * config/riscv/riscv.cc (riscv_output_move): Handle BFmode move + for zfbfmin. + * config/riscv/riscv.md (truncbf2): New pattern for BFmode. + (extendbfsf2): Dotto. + (*movhf_hardfloat): Add BFmode. + (*mov_hardfloat): Dotto. + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/zfbfmin-bf16_arithmetic.c: New test. + * gcc.target/riscv/zfbfmin-bf16_comparison.c: New test. + * gcc.target/riscv/zfbfmin-bf16_float_libcall_convert.c: New test. + * gcc.target/riscv/zfbfmin-bf16_integer_libcall_convert.c: New test. +--- + gcc/config/riscv/iterators.md | 6 +- + gcc/config/riscv/riscv.cc | 4 +- + gcc/config/riscv/riscv.md | 49 ++++++++++++-- + .../riscv/zfbfmin-bf16_arithmetic.c | 35 ++++++++++ + .../riscv/zfbfmin-bf16_comparison.c | 33 ++++++++++ + .../zfbfmin-bf16_float_libcall_convert.c | 45 +++++++++++++ + .../zfbfmin-bf16_integer_libcall_convert.c | 66 +++++++++++++++++++ + 7 files changed, 228 insertions(+), 10 deletions(-) + create mode 100644 gcc/testsuite/gcc.target/riscv/zfbfmin-bf16_arithmetic.c + create mode 100644 gcc/testsuite/gcc.target/riscv/zfbfmin-bf16_comparison.c + create mode 100644 gcc/testsuite/gcc.target/riscv/zfbfmin-bf16_float_libcall_convert.c + create mode 100644 gcc/testsuite/gcc.target/riscv/zfbfmin-bf16_integer_libcall_convert.c + +diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md +index 40bf20f42bb..e2898ba0b51 100644 +--- a/gcc/config/riscv/iterators.md ++++ b/gcc/config/riscv/iterators.md +@@ -75,9 +75,13 @@ + ;; Iterator for floating-point modes that can be loaded into X registers. + (define_mode_iterator SOFTF [SF (DF "TARGET_64BIT") (HF "TARGET_ZFHMIN")]) + +-;; Iterator for floating-point modes of BF16 ++;; Iterator for floating-point modes of BF16. + (define_mode_iterator HFBF [HF BF]) + ++;; Conversion between floating-point modes and BF16. ++;; SF to BF16 have hardware instructions. ++(define_mode_iterator FBF [HF DF TF]) ++ + ;; ------------------------------------------------------------------- + ;; Mode attributes + ;; ------------------------------------------------------------------- +diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc +index ae37f26dbc6..edff4f677a0 100644 +--- a/gcc/config/riscv/riscv.cc ++++ b/gcc/config/riscv/riscv.cc +@@ -3955,7 +3955,7 @@ riscv_output_move (rtx dest, rtx src) + switch (width) + { + case 2: +- if (TARGET_ZFHMIN) ++ if (TARGET_ZFHMIN || TARGET_ZFBFMIN) + return "fmv.x.h\t%0,%1"; + /* Using fmv.x.s + sign-extend to emulate fmv.x.h. */ + return "fmv.x.s\t%0,%1;slli\t%0,%0,16;srai\t%0,%0,16"; +@@ -4011,7 +4011,7 @@ riscv_output_move (rtx dest, rtx src) + switch (width) + { + case 2: +- if (TARGET_ZFHMIN) ++ if (TARGET_ZFHMIN || TARGET_ZFBFMIN) + return "fmv.h.x\t%0,%z1"; + /* High 16 bits should be all-1, otherwise HW will treated + as a n-bit canonical NaN, but isn't matter for softfloat. */ +diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md +index d2764a0409a..03c564d9d29 100644 +--- a/gcc/config/riscv/riscv.md ++++ b/gcc/config/riscv/riscv.md +@@ -1722,6 +1722,31 @@ + [(set_attr "type" "fcvt") + (set_attr "mode" "HF")]) + ++(define_insn "truncsfbf2" ++ [(set (match_operand:BF 0 "register_operand" "=f") ++ (float_truncate:BF ++ (match_operand:SF 1 "register_operand" " f")))] ++ "TARGET_ZFBFMIN" ++ "fcvt.bf16.s\t%0,%1" ++ [(set_attr "type" "fcvt") ++ (set_attr "mode" "BF")]) ++ ++;; The conversion of HF/DF/TF to BF needs to be done with SF if there is a ++;; chance to generate at least one instruction, otherwise just using ++;; libfunc __trunc[h|d|t]fbf2. ++(define_expand "truncbf2" ++ [(set (match_operand:BF 0 "register_operand" "=f") ++ (float_truncate:BF ++ (match_operand:FBF 1 "register_operand" " f")))] ++ "TARGET_ZFBFMIN" ++ { ++ convert_move (operands[0], ++ convert_modes (SFmode, mode, operands[1], 0), 0); ++ DONE; ++ } ++ [(set_attr "type" "fcvt") ++ (set_attr "mode" "BF")]) ++ + ;; + ;; .................... + ;; +@@ -1866,6 +1891,15 @@ + [(set_attr "type" "fcvt") + (set_attr "mode" "SF")]) + ++(define_insn "extendbfsf2" ++ [(set (match_operand:SF 0 "register_operand" "=f") ++ (float_extend:SF ++ (match_operand:BF 1 "register_operand" " f")))] ++ "TARGET_ZFBFMIN" ++ "fcvt.s.bf16\t%0,%1" ++ [(set_attr "type" "fcvt") ++ (set_attr "mode" "SF")]) ++ + (define_insn "extendsfdf2" + [(set (match_operand:DF 0 "register_operand" "=f") + (float_extend:DF +@@ -1895,16 +1929,17 @@ + DONE; + }) + +-(define_insn "*movhf_hardfloat" +- [(set (match_operand:HF 0 "nonimmediate_operand" "=f, f,f,f,m,m,*f,*r, *r,*r,*m") +- (match_operand:HF 1 "move_operand" " f,zfli,G,m,f,G,*r,*f,*G*r,*m,*r"))] +- "TARGET_ZFHMIN +- && (register_operand (operands[0], HFmode) +- || reg_or_0_operand (operands[1], HFmode))" ++(define_insn "*mov_hardfloat" ++ [(set (match_operand:HFBF 0 "nonimmediate_operand" "=f, f,f,f,m,m,*f,*r, *r,*r,*m") ++ (match_operand:HFBF 1 "move_operand" " f,zfli,G,m,f,G,*r,*f,*G*r,*m,*r"))] ++ "((TARGET_ZFHMIN && mode == HFmode) ++ || (TARGET_ZFBFMIN && mode == BFmode)) ++ && (register_operand (operands[0], mode) ++ || reg_or_0_operand (operands[1], mode))" + { return riscv_output_move (operands[0], operands[1]); } + [(set_attr "move_type" "fmove,fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store") + (set_attr "type" "fmove,fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store") +- (set_attr "mode" "HF")]) ++ (set_attr "mode" "")]) + + (define_insn "*mov_softfloat" + [(set (match_operand:HFBF 0 "nonimmediate_operand" "=f, r,r,m,*f,*r") +diff --git a/gcc/testsuite/gcc.target/riscv/zfbfmin-bf16_arithmetic.c b/gcc/testsuite/gcc.target/riscv/zfbfmin-bf16_arithmetic.c +new file mode 100644 +index 00000000000..2ca170345af +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/zfbfmin-bf16_arithmetic.c +@@ -0,0 +1,35 @@ ++/* { dg-do compile } */ ++/* { dg-options "-march=rv32i_zfbfmin -mabi=ilp32f -mcmodel=medany -O" { target { rv32 } } } */ ++/* { dg-options "-march=rv64i_zfbfmin -mabi=lp64f -mcmodel=medany -O" { target { rv64 } } } */ ++ ++/* 1) bf -> sf fcvt.s.bf16 */ ++/* 2) sf1 [+|-|*|/] sf2 f[add|sub|mul|div].s */ ++/* 3) sf -> bf fcvt.bf16.s */ ++extern __bf16 bf; ++extern __bf16 bf1; ++extern __bf16 bf2; ++ ++void bf_add_bf () { bf = bf1 + bf2; } ++ ++void bf_sub_bf () { bf = bf1 - bf2; } ++ ++void bf_mul_bf () { bf = bf1 * bf2; } ++ ++void bf_div_bf () { bf = bf1 / bf2; } ++ ++void bf_add_const () { bf = bf1 + 3.14f; } ++ ++void const_sub_bf () { bf = 3.14f - bf2; } ++ ++void bf_mul_const () { bf = bf1 * 3.14f; } ++ ++void const_div_bf () { bf = 3.14f / bf2; } ++ ++void bf_inc () { ++bf; } ++ ++void bf_dec () { --bf; } ++ ++/* { dg-final { scan-assembler-times "fcvt.s.bf16" 14 } } */ ++/* { dg-final { scan-assembler-times "fcvt.bf16.s" 10 } } */ ++ ++/* { dg-final { scan-assembler-not "call" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/zfbfmin-bf16_comparison.c b/gcc/testsuite/gcc.target/riscv/zfbfmin-bf16_comparison.c +new file mode 100644 +index 00000000000..62d532063c4 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/zfbfmin-bf16_comparison.c +@@ -0,0 +1,33 @@ ++/* { dg-do compile } */ ++/* { dg-options "-march=rv32i_zfbfmin -mabi=ilp32f -O" { target { rv32 } } } */ ++/* { dg-options "-march=rv64i_zfbfmin -mabi=lp64f -O" { target { rv64 } } } */ ++ ++/* 1) bf -> sf fcvt.s.bf16 */ ++/* 2) sf1 [<|<=|>|>=|==] sf2 f[lt|le|gt|ge|eq].s */ ++extern __bf16 bf; ++extern __bf16 bf1; ++extern __bf16 bf2; ++ ++void bf_lt_bf () { bf = (bf1 < bf2) ? bf1 : bf2; } ++ ++void bf_le_bf () { bf = (bf1 <= bf2) ? bf1 : bf2; } ++ ++void bf_gt_bf () { bf = (bf1 > bf2) ? bf1 : bf2; } ++ ++void bf_ge_bf () { bf = (bf1 >= bf2) ? bf1 : bf2; } ++ ++void bf_eq_bf () { bf = (bf1 == bf2) ? bf1 : bf2; } ++ ++void bf_lt_const () { bf = (bf1 < 3.14f) ? bf1 : bf2; } ++ ++void bf_le_const () { bf = (bf1 <= 3.14f) ? bf1 : bf2; } ++ ++void const_gt_bf () { bf = (3.14f > bf2) ? bf1 : bf2; } ++ ++void const_ge_bf () { bf = (3.14f >= bf2) ? bf1 : bf2; } ++ ++void bf_eq_const () { bf = (bf1 == 3.14f) ? bf1 : bf2; } ++ ++/* { dg-final { scan-assembler-times "fcvt.s.bf16" 15 } } */ ++ ++/* { dg-final { scan-assembler-not "call" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/zfbfmin-bf16_float_libcall_convert.c b/gcc/testsuite/gcc.target/riscv/zfbfmin-bf16_float_libcall_convert.c +new file mode 100644 +index 00000000000..95e65996e28 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/zfbfmin-bf16_float_libcall_convert.c +@@ -0,0 +1,45 @@ ++/* { dg-do compile } */ ++/* { dg-options "-march=rv32i_zfbfmin -mabi=ilp32f -O" { target { rv32 } } } */ ++/* { dg-options "-march=rv64i_zfbfmin -mabi=lp64f -O" { target { rv64 } } } */ ++ ++ ++/* 1) float -> BF16 ++ * hf -> bf == hf -> sf -> bf fcvt.h.s + fcvt.bf16.s ++ * sf -> bf == sf -> bf fcvt.bf16.s ++ * df -> bf == df -> sf -> bf __truncdfsf2 + fcvt.bf16.s ++ * tf -> bf == tf -> sf -> bf __trunctfsf2 + fcvt.bf16.s ++*/ ++ ++/* 2) BF16 -> float ++ * bf -> hf == bf -> sf -> hf fcvt.s.bf16 + fcvt.s.h ++ * bf -> sf == bf -> sf fcvt.s.bf16 ++ * bf -> df == bf -> sf -> df fcvt.s.bf16 + __extendsfdf2 ++ * bf -> tf == bf -> sf -> tf fcvt.s.bf16 + __extendsftf2 ++*/ ++ ++extern __bf16 bf; ++extern _Float16 hf; ++extern float sf; ++extern double df; ++extern long double tf; ++ ++void hf_to_bf () { bf = hf; } ++void bf_to_hf () { hf = bf; } ++ ++void sf_to_bf () { bf = sf; } ++void bf_to_sf () { sf = bf; } ++ ++void df_to_bf () { bf = df; } ++void bf_to_df () { df = bf; } ++ ++void tf_to_bf () { bf = tf; } ++void bf_to_tf () { tf = bf; } ++ ++/* { dg-final { scan-assembler-times "fcvt.bf16.s" 4 } } */ ++/* { dg-final { scan-assembler-times "fcvt.s.bf16" 4 } } */ ++/* { dg-final { scan-assembler-times "fcvt.h.s" 1 } } */ ++/* { dg-final { scan-assembler-times "fcvt.s.h" 1 } } */ ++/* { dg-final { scan-assembler-times "call\t__truncdfsf2" 1 } } */ ++/* { dg-final { scan-assembler-times "call\t__trunctfsf2" 1 } } */ ++/* { dg-final { scan-assembler-times "call\t__extendsfdf2" 1 } } */ ++/* { dg-final { scan-assembler-times "call\t__extendsftf2" 1 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/zfbfmin-bf16_integer_libcall_convert.c b/gcc/testsuite/gcc.target/riscv/zfbfmin-bf16_integer_libcall_convert.c +new file mode 100644 +index 00000000000..1a998bfe2f8 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/zfbfmin-bf16_integer_libcall_convert.c +@@ -0,0 +1,66 @@ ++/* { dg-do compile } */ ++/* { dg-options "-march=rv32i_zfbfmin -mabi=ilp32f -O" { target { rv32 } } } */ ++/* { dg-options "-march=rv64i_zfbfmin -mabi=lp64f -O" { target { rv64 } } } */ ++ ++/* 1) Integer -> BF16 ++ * qi/hi -> bf fcvt.s.w + fcvt.bf16.s ++ * uqi/uhi -> bf fcvt.s.wu + fcvt.bf16.s ++ * ++ * si/di/ti -> bf __float[s|d|t]ibf ++ * usi/udi/uti -> bf __floatun[s|d|t]ibf ++*/ ++ ++/* 2) BF16 -> Integer ++ * bf -> qi/hi/si/di fcvt.s.bf16 + fcvt.[w|l].s ++ * bf -> uqi/uhi/usi/udi fcvt.s.bf16 + fcvt.[w|l]u.s ++ * bf -> ti/uti fcvt.s.bf16 + __fix[uns]sfti ++*/ ++ ++extern __bf16 bf; ++ ++extern signed char qi; ++extern unsigned char uqi; ++extern signed short hi; ++extern unsigned short uhi; ++extern signed int si; ++extern unsigned int usi; ++extern signed long long di; ++extern unsigned long long udi; ++ ++void qi_to_bf () { bf = qi; } ++void uqi_to_bf () { bf = uqi; } ++void bf_to_qi () { qi = bf; } ++void bf_to_uqi () { uqi = bf; } ++ ++void hi_to_bf () { bf = hi; } ++void uhi_to_bf () { bf = uhi; } ++void bf_to_hi () { hi = bf; } ++void bf_to_uhi () { uhi = bf; } ++ ++void si_to_bf () { bf = si; } ++void usi_to_bf () { bf = usi; } ++void bf_to_si () { si = bf; } ++void bf_to_usi () { usi = bf; } ++ ++void di_to_bf () { bf = di; } ++void udi_to_bf () { bf = udi; } ++void bf_to_di () { di = bf; } ++void bf_to_udi () { udi = bf; } ++ ++#if __riscv_xlen == 64 ++extern signed __int128 ti; ++extern unsigned __int128 uti; ++void ti_to_bf () { bf = ti; } /* { dg-final { scan-assembler-times "call\t__floattibf" 1 { target { rv64 } } } } */ ++void uti_to_bf () { bf = uti; } /* { dg-final { scan-assembler-times "call\t__floatuntibf" 1 { target { rv64 } } } } */ ++void bf_to_ti () { ti = bf; } /* { dg-final { scan-assembler-times "call\t__fixsfti" 1 { target { rv64 } } } } */ ++void bf_to_uti () { uti = bf; } /* { dg-final { scan-assembler-times "call\t__fixunssfti" 1 { target { rv64 } } } } */ ++#endif ++ ++/* { dg-final { scan-assembler-times "fcvt.bf16.s" 4 } } */ ++/* { dg-final { scan-assembler-times "fcvt.s.bf16" 8 { target { rv32 } } } } */ ++/* { dg-final { scan-assembler-times "fcvt.s.bf16" 10 { target { rv64 } } } } */ ++ ++/* { dg-final { scan-assembler-times "call\t__floatsibf" 1 } } */ ++/* { dg-final { scan-assembler-times "call\t__floatunsibf" 1 } } */ ++/* { dg-final { scan-assembler-times "call\t__floatdibf" 1 } } */ ++/* { dg-final { scan-assembler-times "call\t__floatundibf" 1 } } */ +-- +2.47.3 + diff --git a/1015-RISC-V-Use-widening-shift-for-scatter-gather-if-appl.patch b/1015-RISC-V-Use-widening-shift-for-scatter-gather-if-appl.patch new file mode 100644 index 0000000..e387767 --- /dev/null +++ b/1015-RISC-V-Use-widening-shift-for-scatter-gather-if-appl.patch @@ -0,0 +1,370 @@ +From 3483c7fdb9c26d9be4b3b3ce3836442d0f4720bf Mon Sep 17 00:00:00 2001 +From: Robin Dapp +Date: Fri, 10 May 2024 13:37:03 +0200 +Subject: [PATCH 1015/1087] RISC-V: Use widening shift for scatter/gather if + applicable. + +commit 309ee005aa871286c8daccbce7586f82be347440 upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +With the zvbb extension we can emit a widening shift for scatter/gather +index preparation in case we need to multiply by 2 and zero extend. + +The patch also adds vwsll to the mode_idx attribute and removes the +mode from shift-count operand of the insn pattern. + +gcc/ChangeLog: + + * config/riscv/riscv-v.cc (expand_gather_scatter): Use vwsll if + applicable. + * config/riscv/vector-crypto.md: Remove mode from vwsll shift + count operator. + * config/riscv/vector.md: Add vwsll to mode iterator. + +gcc/testsuite/ChangeLog: + + * lib/target-supports.exp: Add zvbb. + * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-12-zvbb.c: New test. +--- + gcc/config/riscv/riscv-v.cc | 42 +++++-- + gcc/config/riscv/vector-crypto.md | 4 +- + gcc/config/riscv/vector.md | 4 +- + .../gather-scatter/gather_load_64-12-zvbb.c | 113 ++++++++++++++++++ + gcc/testsuite/lib/target-supports.exp | 48 +++++++- + 5 files changed, 193 insertions(+), 18 deletions(-) + create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-12-zvbb.c + +diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc +index bb38d8b42c7..4371971507c 100644 +--- a/gcc/config/riscv/riscv-v.cc ++++ b/gcc/config/riscv/riscv-v.cc +@@ -4060,7 +4060,7 @@ expand_gather_scatter (rtx *ops, bool is_load) + { + rtx ptr, vec_offset, vec_reg; + bool zero_extend_p; +- int scale_log2; ++ int shift; + rtx mask = ops[5]; + rtx len = ops[6]; + if (is_load) +@@ -4069,7 +4069,7 @@ expand_gather_scatter (rtx *ops, bool is_load) + ptr = ops[1]; + vec_offset = ops[2]; + zero_extend_p = INTVAL (ops[3]); +- scale_log2 = exact_log2 (INTVAL (ops[4])); ++ shift = exact_log2 (INTVAL (ops[4])); + } + else + { +@@ -4077,7 +4077,7 @@ expand_gather_scatter (rtx *ops, bool is_load) + ptr = ops[0]; + vec_offset = ops[1]; + zero_extend_p = INTVAL (ops[2]); +- scale_log2 = exact_log2 (INTVAL (ops[3])); ++ shift = exact_log2 (INTVAL (ops[3])); + } + + machine_mode vec_mode = GET_MODE (vec_reg); +@@ -4087,9 +4087,12 @@ expand_gather_scatter (rtx *ops, bool is_load) + poly_int64 nunits = GET_MODE_NUNITS (vec_mode); + bool is_vlmax = is_vlmax_len_p (vec_mode, len); + ++ bool use_widening_shift = false; ++ + /* Extend the offset element to address width. */ + if (inner_offsize < BITS_PER_WORD) + { ++ use_widening_shift = TARGET_ZVBB && zero_extend_p && shift == 1; + /* 7.2. Vector Load/Store Addressing Modes. + If the vector offset elements are narrower than XLEN, they are + zero-extended to XLEN before adding to the ptr effective address. If +@@ -4098,8 +4101,8 @@ expand_gather_scatter (rtx *ops, bool is_load) + raise an illegal instruction exception if the EEW is not supported for + offset elements. + +- RVV spec only refers to the scale_log == 0 case. */ +- if (!zero_extend_p || scale_log2 != 0) ++ RVV spec only refers to the shift == 0 case. */ ++ if (!zero_extend_p || shift) + { + if (zero_extend_p) + inner_idx_mode +@@ -4108,19 +4111,32 @@ expand_gather_scatter (rtx *ops, bool is_load) + inner_idx_mode = int_mode_for_size (BITS_PER_WORD, 0).require (); + machine_mode new_idx_mode + = get_vector_mode (inner_idx_mode, nunits).require (); +- rtx tmp = gen_reg_rtx (new_idx_mode); +- emit_insn (gen_extend_insn (tmp, vec_offset, new_idx_mode, idx_mode, +- zero_extend_p ? true : false)); +- vec_offset = tmp; ++ if (!use_widening_shift) ++ { ++ rtx tmp = gen_reg_rtx (new_idx_mode); ++ emit_insn (gen_extend_insn (tmp, vec_offset, new_idx_mode, idx_mode, ++ zero_extend_p ? true : false)); ++ vec_offset = tmp; ++ } + idx_mode = new_idx_mode; + } + } + +- if (scale_log2 != 0) ++ if (shift) + { +- rtx tmp = expand_binop (idx_mode, ashl_optab, vec_offset, +- gen_int_mode (scale_log2, Pmode), NULL_RTX, 0, +- OPTAB_DIRECT); ++ rtx tmp; ++ if (!use_widening_shift) ++ tmp = expand_binop (idx_mode, ashl_optab, vec_offset, ++ gen_int_mode (shift, Pmode), NULL_RTX, 0, ++ OPTAB_DIRECT); ++ else ++ { ++ tmp = gen_reg_rtx (idx_mode); ++ insn_code icode = code_for_pred_vwsll_scalar (idx_mode); ++ rtx ops[] = {tmp, vec_offset, const1_rtx}; ++ emit_vlmax_insn (icode, BINARY_OP, ops); ++ } ++ + vec_offset = tmp; + } + +diff --git a/gcc/config/riscv/vector-crypto.md b/gcc/config/riscv/vector-crypto.md +index e474ddf5da7..f86adafc84e 100755 +--- a/gcc/config/riscv/vector-crypto.md ++++ b/gcc/config/riscv/vector-crypto.md +@@ -295,7 +295,7 @@ + (ashift:VWEXTI + (zero_extend:VWEXTI + (match_operand: 3 "register_operand" "vr")) +- (match_operand: 4 "register_operand" "vr")) ++ (match_operand: 4 "vector_shift_operand" "vrvk")) + (match_operand:VWEXTI 2 "vector_merge_operand" "0vu")))] + "TARGET_ZVBB" + "vwsll.vv\t%0,%3,%4%p1" +@@ -316,7 +316,7 @@ + (ashift:VWEXTI + (zero_extend:VWEXTI + (match_operand: 3 "register_operand" " vr, vr")) +- (match_operand: 4 "pmode_reg_or_uimm5_operand" " rK, rK")) ++ (match_operand 4 "pmode_reg_or_uimm5_operand" " rK, rK")) + (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0")))] + "TARGET_ZVBB" + "vwsll.v%o4\t%0,%3,%4%p1" +diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md +index db6425f71a5..21aea257d0e 100644 +--- a/gcc/config/riscv/vector.md ++++ b/gcc/config/riscv/vector.md +@@ -824,10 +824,10 @@ + (const_int 1) + + (eq_attr "type" "vssegte,vmpop,vmffs") +- (const_int 2) ++ (const_int 2) + + (eq_attr "type" "vstux,vstox,vssegts,vssegtux,vssegtox,vfcvtftoi,vfwcvtitof,vfwcvtftoi, +- vfwcvtftof,vmsfs,vired,viwred,vfredu,vfredo,vfwredu,vfwredo") ++ vfwcvtftof,vmsfs,vired,viwred,vfredu,vfredo,vfwredu,vfwredo,vwsll") + (const_int 3) + + (eq_attr "type" "viwalu,viwmul,viwmuladd,vfwalu,vfwmul,vfwmuladd") +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-12-zvbb.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-12-zvbb.c +new file mode 100644 +index 00000000000..11a4031f47b +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-12-zvbb.c +@@ -0,0 +1,113 @@ ++/* { dg-do compile } */ ++/* { dg-add-options "riscv_v" } */ ++/* { dg-add-options "riscv_zvbb" } */ ++/* { dg-additional-options "-fno-vect-cost-model -fdump-tree-vect-details -mrvv-max-lmul=m4" } */ ++ ++#include ++ ++#define TEST_LOOP(DATA_TYPE, INDEX_TYPE) \ ++ void __attribute__ ((noinline, noclone)) \ ++ f_##DATA_TYPE##_##INDEX_TYPE (DATA_TYPE *restrict y, DATA_TYPE *restrict x, \ ++ INDEX_TYPE *restrict index) \ ++ { \ ++ for (int i = 0; i < 100; ++i) \ ++ { \ ++ y[i * 2] = x[index[i * 2]] + 1; \ ++ y[i * 2 + 1] = x[index[i * 2 + 1]] + 2; \ ++ } \ ++ } ++ ++TEST_LOOP (int8_t, int8_t) ++TEST_LOOP (uint8_t, int8_t) ++TEST_LOOP (int16_t, int8_t) ++TEST_LOOP (uint16_t, int8_t) ++TEST_LOOP (int32_t, int8_t) ++TEST_LOOP (uint32_t, int8_t) ++TEST_LOOP (int64_t, int8_t) ++TEST_LOOP (uint64_t, int8_t) ++TEST_LOOP (_Float16, int8_t) ++TEST_LOOP (float, int8_t) ++TEST_LOOP (double, int8_t) ++TEST_LOOP (int8_t, int16_t) ++TEST_LOOP (uint8_t, int16_t) ++TEST_LOOP (int16_t, int16_t) ++TEST_LOOP (uint16_t, int16_t) ++TEST_LOOP (int32_t, int16_t) ++TEST_LOOP (uint32_t, int16_t) ++TEST_LOOP (int64_t, int16_t) ++TEST_LOOP (uint64_t, int16_t) ++TEST_LOOP (_Float16, int16_t) ++TEST_LOOP (float, int16_t) ++TEST_LOOP (double, int16_t) ++TEST_LOOP (int8_t, int32_t) ++TEST_LOOP (uint8_t, int32_t) ++TEST_LOOP (int16_t, int32_t) ++TEST_LOOP (uint16_t, int32_t) ++TEST_LOOP (int32_t, int32_t) ++TEST_LOOP (uint32_t, int32_t) ++TEST_LOOP (int64_t, int32_t) ++TEST_LOOP (uint64_t, int32_t) ++TEST_LOOP (_Float16, int32_t) ++TEST_LOOP (float, int32_t) ++TEST_LOOP (double, int32_t) ++TEST_LOOP (int8_t, int64_t) ++TEST_LOOP (uint8_t, int64_t) ++TEST_LOOP (int16_t, int64_t) ++TEST_LOOP (uint16_t, int64_t) ++TEST_LOOP (int32_t, int64_t) ++TEST_LOOP (uint32_t, int64_t) ++TEST_LOOP (int64_t, int64_t) ++TEST_LOOP (uint64_t, int64_t) ++TEST_LOOP (_Float16, int64_t) ++TEST_LOOP (float, int64_t) ++TEST_LOOP (double, int64_t) ++TEST_LOOP (int8_t, uint8_t) ++TEST_LOOP (uint8_t, uint8_t) ++TEST_LOOP (int16_t, uint8_t) ++TEST_LOOP (uint16_t, uint8_t) ++TEST_LOOP (int32_t, uint8_t) ++TEST_LOOP (uint32_t, uint8_t) ++TEST_LOOP (int64_t, uint8_t) ++TEST_LOOP (uint64_t, uint8_t) ++TEST_LOOP (_Float16, uint8_t) ++TEST_LOOP (float, uint8_t) ++TEST_LOOP (double, uint8_t) ++TEST_LOOP (int8_t, uint16_t) ++TEST_LOOP (uint8_t, uint16_t) ++TEST_LOOP (int16_t, uint16_t) ++TEST_LOOP (uint16_t, uint16_t) ++TEST_LOOP (int32_t, uint16_t) ++TEST_LOOP (uint32_t, uint16_t) ++TEST_LOOP (int64_t, uint16_t) ++TEST_LOOP (uint64_t, uint16_t) ++TEST_LOOP (_Float16, uint16_t) ++TEST_LOOP (float, uint16_t) ++TEST_LOOP (double, uint16_t) ++TEST_LOOP (int8_t, uint32_t) ++TEST_LOOP (uint8_t, uint32_t) ++TEST_LOOP (int16_t, uint32_t) ++TEST_LOOP (uint16_t, uint32_t) ++TEST_LOOP (int32_t, uint32_t) ++TEST_LOOP (uint32_t, uint32_t) ++TEST_LOOP (int64_t, uint32_t) ++TEST_LOOP (uint64_t, uint32_t) ++TEST_LOOP (_Float16, uint32_t) ++TEST_LOOP (float, uint32_t) ++TEST_LOOP (double, uint32_t) ++TEST_LOOP (int8_t, uint64_t) ++TEST_LOOP (uint8_t, uint64_t) ++TEST_LOOP (int16_t, uint64_t) ++TEST_LOOP (uint16_t, uint64_t) ++TEST_LOOP (int32_t, uint64_t) ++TEST_LOOP (uint32_t, uint64_t) ++TEST_LOOP (int64_t, uint64_t) ++TEST_LOOP (uint64_t, uint64_t) ++TEST_LOOP (_Float16, uint64_t) ++TEST_LOOP (float, uint64_t) ++TEST_LOOP (double, uint64_t) ++ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 88 "vect" } } */ ++/* { dg-final { scan-tree-dump " \.MASK_LEN_GATHER_LOAD" "vect" } } */ ++/* { dg-final { scan-tree-dump-not " \.GATHER_LOAD" "vect" } } */ ++/* { dg-final { scan-tree-dump-not " \.MASK_GATHER_LOAD" "vect" } } */ ++/* { dg-final { scan-assembler "vwsll.vi" } } */ +diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp +index d176c024f6d..4cada7f94fb 100644 +--- a/gcc/testsuite/lib/target-supports.exp ++++ b/gcc/testsuite/lib/target-supports.exp +@@ -2016,6 +2016,17 @@ proc check_effective_target_riscv_zbb { } { + }] + } + ++# Return 1 if the target arch supports the Zbb extension, 0 otherwise. ++# Cache the result. ++ ++proc check_effective_target_riscv_zvbb { } { ++ return [check_no_compiler_messages riscv_ext_zvbb assembly { ++ #ifndef __riscv_zvbb ++ #error "Not __riscv_zvbb" ++ #endif ++ }] ++} ++ + # Return 1 if the target arch supports the XTheadVector extension, 0 otherwise. + # Cache the result. + +@@ -2104,10 +2115,33 @@ proc check_effective_target_riscv_zvfh_ok { } { + return 0 + } + ++proc check_effective_target_riscv_zvbb_ok { } { ++ # If the target already supports v without any added options, ++ # we may assume we can execute just fine. ++ if { [check_effective_target_riscv_zvbb] } { ++ return 1 ++ } ++ ++ # check if we can execute vector insns with the given hardware or ++ # simulator ++ set gcc_march [regsub {[[:alnum:]]*} [riscv_get_arch] &zvbb] ++ if { [check_runtime ${gcc_march}_zvbb_exec { ++ int main() ++ { ++ asm ("vsetivli zero,8,e16,m1,ta,ma"); ++ asm ("vwsll.vi v8,v16,2" : : : "v8"); ++ return 0; ++ } } "-march=${gcc_march}"] } { ++ return 1 ++ } ++ ++ return 0 ++} ++ + proc riscv_get_arch { } { + set gcc_march "" + # ??? do we neeed to add more extensions to the list below? +- foreach ext { i m a f d q c v zicsr zifencei zfh zba zbb zbc zbs zvfh ztso } { ++ foreach ext { i m a f d q c v zicsr zifencei zfh zba zbb zbc zbs zvbb zvfh ztso } { + if { [check_no_compiler_messages riscv_ext_$ext assembly [string map [list DEF __riscv_$ext] { + #ifndef DEF + #error "Not DEF" +@@ -2202,6 +2236,18 @@ proc add_options_for_riscv_zvfh { flags } { + return "$flags -march=[riscv_get_arch]_zvfh" + } + ++proc add_options_for_riscv_zvbb { flags } { ++ if { [lsearch $flags -march=*] >= 0 } { ++ # If there are multiple -march flags, we have to adjust all of them. ++ set flags [regsub -all -- {(?:^|[[:space:]])-march=[[:alnum:]_.]*} $flags &_zvbb ] ++ return [regsub -all -- {((?:^|[[:space:]])-march=[[:alnum:]_.]*_zvbb[[:alnum:]_.]*)_zvbb} $flags \\1 ] ++ } ++ if { [check_effective_target_riscv_zvbb] } { ++ return "$flags" ++ } ++ return "$flags -march=[riscv_get_arch]_zvbb" ++} ++ + # Return 1 if the target OS supports running SSE executables, 0 + # otherwise. Cache the result. + +-- +2.47.3 + diff --git a/1016-RISC-V-Introduce-mvector-strict-align.patch b/1016-RISC-V-Introduce-mvector-strict-align.patch new file mode 100644 index 0000000..4c48fc0 --- /dev/null +++ b/1016-RISC-V-Introduce-mvector-strict-align.patch @@ -0,0 +1,409 @@ +From fb8a80551bbb13922b4ccd9d83ca1f5c6ce6f13e Mon Sep 17 00:00:00 2001 +From: Robin Dapp +Date: Tue, 28 May 2024 21:19:26 +0200 +Subject: [PATCH 1016/1087] RISC-V: Introduce -mvector-strict-align. + +commit 68b0742a49de7122d5023f0bf46460ff2fb3e3dd upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +this patch disables movmisalign by default and introduces +the -mno-vector-strict-align option to override it and re-enable +movmisalign. For now, generic-ooo is the only uarch that supports +misaligned vector access. + +The patch also adds a check_effective_target_riscv_v_misalign_ok to +the testsuite which enables or disables the vector misalignment tests +depending on whether the target under test can execute a misaligned +vle32. + +Changes from v3: + - Adressed Kito's comments. + - Made -mscalar-strict-align a real alias. + +gcc/ChangeLog: + + * config/riscv/riscv-opts.h (TARGET_VECTOR_MISALIGN_SUPPORTED): + Move from here... + * config/riscv/riscv.h (TARGET_VECTOR_MISALIGN_SUPPORTED): + ...to here and map to riscv_vector_unaligned_access_p. + * config/riscv/riscv.opt: Add -mvector-strict-align. + * config/riscv/riscv.cc (struct riscv_tune_param): Add + vector_unaligned_access. + (riscv_override_options_internal): Set + riscv_vector_unaligned_access_p. + * doc/invoke.texi: Document -mvector-strict-align. + +gcc/testsuite/ChangeLog: + + * lib/target-supports.exp: Add + check_effective_target_riscv_v_misalign_ok. + * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-7.c: Add + -mno-vector-strict-align. + * gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-10.c: Ditto. + * gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-11.c: Ditto. + * gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-12.c: Ditto. + * gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-8.c: Ditto. + * gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-9.c: Ditto. + * gcc.target/riscv/rvv/autovec/vls/misalign-1.c: Ditto. +--- + gcc/config/riscv/riscv-opts.h | 3 -- + gcc/config/riscv/riscv.cc | 20 +++++++++++ + gcc/config/riscv/riscv.h | 5 +++ + gcc/config/riscv/riscv.opt | 8 +++++ + gcc/doc/invoke.texi | 16 +++++++++ + .../costmodel/riscv/rvv/dynamic-lmul2-7.c | 2 +- + .../vect/costmodel/riscv/rvv/vla_vs_vls-10.c | 2 +- + .../vect/costmodel/riscv/rvv/vla_vs_vls-11.c | 2 +- + .../vect/costmodel/riscv/rvv/vla_vs_vls-12.c | 2 +- + .../vect/costmodel/riscv/rvv/vla_vs_vls-8.c | 2 +- + .../vect/costmodel/riscv/rvv/vla_vs_vls-9.c | 2 +- + .../riscv/rvv/autovec/vls/misalign-1.c | 2 +- + gcc/testsuite/lib/target-supports.exp | 35 +++++++++++++++++-- + 13 files changed, 89 insertions(+), 12 deletions(-) + +diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h +index 1b2dd5757a8..f58a07abffc 100644 +--- a/gcc/config/riscv/riscv-opts.h ++++ b/gcc/config/riscv/riscv-opts.h +@@ -147,9 +147,6 @@ enum rvv_vector_bits_enum { + ? 0 \ + : 32 << (__builtin_popcount (opts->x_riscv_zvl_flags) - 1)) + +-/* TODO: Enable RVV movmisalign by default for now. */ +-#define TARGET_VECTOR_MISALIGN_SUPPORTED 1 +- + /* The maximmum LMUL according to user configuration. */ + #define TARGET_MAX_LMUL \ + (int) (rvv_max_lmul == RVV_DYNAMIC ? RVV_M8 : rvv_max_lmul) +diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc +index edff4f677a0..2e95bc2f0ee 100644 +--- a/gcc/config/riscv/riscv.cc ++++ b/gcc/config/riscv/riscv.cc +@@ -286,6 +286,7 @@ struct riscv_tune_param + unsigned short memory_cost; + unsigned short fmv_cost; + bool slow_unaligned_access; ++ bool vector_unaligned_access; + bool use_divmod_expansion; + unsigned int fusible_ops; + const struct cpu_vector_cost *vec_costs; +@@ -297,6 +298,10 @@ struct riscv_tune_param + /* Whether unaligned accesses execute very slowly. */ + bool riscv_slow_unaligned_access_p; + ++/* Whether misaligned vector accesses are supported (i.e. do not ++ throw an exception). */ ++bool riscv_vector_unaligned_access_p; ++ + /* Whether user explicitly passed -mstrict-align. */ + bool riscv_user_wants_strict_align; + +@@ -425,6 +430,7 @@ static const struct riscv_tune_param rocket_tune_info = { + 5, /* memory_cost */ + 8, /* fmv_cost */ + true, /* slow_unaligned_access */ ++ false, /* vector_unaligned_access */ + false, /* use_divmod_expansion */ + RISCV_FUSE_NOTHING, /* fusible_ops */ + NULL, /* vector cost */ +@@ -442,6 +448,7 @@ static const struct riscv_tune_param sifive_7_tune_info = { + 3, /* memory_cost */ + 8, /* fmv_cost */ + true, /* slow_unaligned_access */ ++ false, /* vector_unaligned_access */ + false, /* use_divmod_expansion */ + RISCV_FUSE_NOTHING, /* fusible_ops */ + NULL, /* vector cost */ +@@ -459,6 +466,7 @@ static const struct riscv_tune_param sifive_p400_tune_info = { + 3, /* memory_cost */ + 4, /* fmv_cost */ + true, /* slow_unaligned_access */ ++ false, /* vector_unaligned_access */ + false, /* use_divmod_expansion */ + RISCV_FUSE_LUI_ADDI | RISCV_FUSE_AUIPC_ADDI, /* fusible_ops */ + &generic_vector_cost, /* vector cost */ +@@ -476,6 +484,7 @@ static const struct riscv_tune_param sifive_p600_tune_info = { + 3, /* memory_cost */ + 4, /* fmv_cost */ + true, /* slow_unaligned_access */ ++ false, /* vector_unaligned_access */ + false, /* use_divmod_expansion */ + RISCV_FUSE_LUI_ADDI | RISCV_FUSE_AUIPC_ADDI, /* fusible_ops */ + &generic_vector_cost, /* vector cost */ +@@ -493,6 +502,7 @@ static const struct riscv_tune_param thead_c906_tune_info = { + 5, /* memory_cost */ + 8, /* fmv_cost */ + false, /* slow_unaligned_access */ ++ false, /* vector_unaligned_access */ + false, /* use_divmod_expansion */ + RISCV_FUSE_NOTHING, /* fusible_ops */ + NULL, /* vector cost */ +@@ -510,6 +520,7 @@ static const struct riscv_tune_param xiangshan_nanhu_tune_info = { + 3, /* memory_cost */ + 3, /* fmv_cost */ + true, /* slow_unaligned_access */ ++ false, /* vector_unaligned_access */ + false, /* use_divmod_expansion */ + RISCV_FUSE_ZEXTW | RISCV_FUSE_ZEXTH, /* fusible_ops */ + NULL, /* vector cost */ +@@ -527,6 +538,7 @@ static const struct riscv_tune_param generic_ooo_tune_info = { + 4, /* memory_cost */ + 4, /* fmv_cost */ + false, /* slow_unaligned_access */ ++ true, /* vector_unaligned_access */ + false, /* use_divmod_expansion */ + RISCV_FUSE_NOTHING, /* fusible_ops */ + &generic_vector_cost, /* vector cost */ +@@ -544,6 +556,7 @@ static const struct riscv_tune_param optimize_size_tune_info = { + 2, /* memory_cost */ + 8, /* fmv_cost */ + false, /* slow_unaligned_access */ ++ false, /* vector_unaligned_access */ + false, /* use_divmod_expansion */ + RISCV_FUSE_NOTHING, /* fusible_ops */ + NULL, /* vector cost */ +@@ -9293,6 +9306,13 @@ riscv_override_options_internal (struct gcc_options *opts) + riscv_slow_unaligned_access_p = (cpu->tune_param->slow_unaligned_access + || TARGET_STRICT_ALIGN); + ++ /* Make a note if user explicity passed -mstrict-align for later ++ /* By default, when -mno-vector-strict-align is not specified, do not allow ++ unaligned vector memory accesses except if -mtune's setting explicitly ++ allows it. */ ++ riscv_vector_unaligned_access_p = opts->x_rvv_vector_strict_align == 0 ++ || cpu->tune_param->vector_unaligned_access; ++ + /* Make a note if user explicity passed -mstrict-align for later + builtin macro generation. Can't use target_flags_explicitly since + it is set even for -mno-strict-align. */ +diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h +index 9f782c9db2c..35953dab924 100644 +--- a/gcc/config/riscv/riscv.h ++++ b/gcc/config/riscv/riscv.h +@@ -912,6 +912,10 @@ extern enum riscv_cc get_riscv_cc (const rtx use); + || (riscv_microarchitecture == sifive_p400) \ + || (riscv_microarchitecture == sifive_p600)) + ++/* True if the target supports misaligned vector loads and stores. */ ++#define TARGET_VECTOR_MISALIGN_SUPPORTED \ ++ riscv_vector_unaligned_access_p ++ + #define LOGICAL_OP_NON_SHORT_CIRCUIT 0 + + /* Control the assembler format that we output. */ +@@ -1139,6 +1143,7 @@ while (0) + #ifndef USED_FOR_TARGET + extern const enum reg_class riscv_regno_to_class[]; + extern bool riscv_slow_unaligned_access_p; ++extern bool riscv_vector_unaligned_access_p; + extern bool riscv_user_wants_strict_align; + extern unsigned riscv_stack_boundary; + extern unsigned riscv_bytes_per_vector_chunk; +diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt +index ad5046e20fb..235166d4679 100644 +--- a/gcc/config/riscv/riscv.opt ++++ b/gcc/config/riscv/riscv.opt +@@ -128,6 +128,14 @@ mstrict-align + Target Mask(STRICT_ALIGN) Save + Do not generate unaligned memory accesses. + ++mscalar-strict-align ++Target Save Alias(mstrict-align) ++Do not generate unaligned scalar memory accesses. ++ ++mvector-strict-align ++Target Save Var(rvv_vector_strict_align) Init(1) ++Do not create element-misaligned vector memory accesses. ++ + Enum + Name(code_model) Type(enum riscv_code_model) + Known code models (for use with the -mcmodel= option): +diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi +index 64728fead51..2df8555c625 100644 +--- a/gcc/doc/invoke.texi ++++ b/gcc/doc/invoke.texi +@@ -31123,6 +31123,22 @@ Do not or do generate unaligned memory accesses. The default is set depending + on whether the processor we are optimizing for supports fast unaligned access + or not. + ++@opindex mscalar-strict-align ++@opindex mno-scalar-strict-align ++@item -mscalar-strict-align ++@itemx -mno-scalar-strict-align ++Do not or do generate unaligned memory accesses. The default is set depending ++on whether the processor we are optimizing for supports fast unaligned access ++or not. This is an alias for @option{-mstrict-align}. ++ ++@opindex mvector-strict-align ++@opindex mno-vector-strict-align ++@item -mvector-strict-align ++@itemx -mno-vector-strict-align ++Do not or do generate unaligned vector memory accesses. The default is set ++to off unless the processor we are optimizing for explicitly supports ++element-misaligned vector memory access. ++ + @opindex mcmodel=medlow + @item -mcmodel=medlow + Generate code for the medium-low code model. The program and its statically +diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-7.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-7.c +index 49ea3c2cf72..754f84ae0a0 100644 +--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-7.c ++++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-7.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -mrvv-max-lmul=dynamic" } */ ++/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -mno-vector-strict-align" } */ + + int + x264_pixel_8x8 (unsigned char *pix1, unsigned char *pix2, int i_stride_pix2) +diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-10.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-10.c +index 144479324d7..d0a0f4208ee 100644 +--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-10.c ++++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-10.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-max-lmul=m4 -fno-schedule-insns -fno-schedule-insns2" } */ ++/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-max-lmul=m4 -fno-schedule-insns -fno-schedule-insns2 -mno-vector-strict-align" } */ + + #include + +diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-11.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-11.c +index 13ae8bd3bcf..5a779a9ee75 100644 +--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-11.c ++++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-11.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fno-schedule-insns -fno-schedule-insns2" } */ ++/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fno-schedule-insns -fno-schedule-insns2 -mno-vector-strict-align" } */ + + #include + +diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-12.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-12.c +index 1f9fa48264e..e7e4e841bb8 100644 +--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-12.c ++++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-12.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-max-lmul=dynamic -fno-schedule-insns -fno-schedule-insns2" } */ ++/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-max-lmul=dynamic -fno-schedule-insns -fno-schedule-insns2 -mno-vector-strict-align" } */ + + #include + +diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-8.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-8.c +index ea6a7cbe2b1..0e5b4522de5 100644 +--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-8.c ++++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-8.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ ++/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mno-vector-strict-align" } */ + + #include + +diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-9.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-9.c +index cb4abeca989..5276e0b2f6c 100644 +--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-9.c ++++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-9.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-max-lmul=m2" } */ ++/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-max-lmul=m2 -mno-vector-strict-align" } */ + + #include + +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/misalign-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/misalign-1.c +index 1a076cbcd0f..5184a295e16 100644 +--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/misalign-1.c ++++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/misalign-1.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m4 -fno-tree-loop-distribute-patterns" } */ ++/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m4 -fno-tree-loop-distribute-patterns -mno-vector-strict-align" } */ + + #include + +diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp +index 4cada7f94fb..7979f0a17eb 100644 +--- a/gcc/testsuite/lib/target-supports.exp ++++ b/gcc/testsuite/lib/target-supports.exp +@@ -2102,7 +2102,7 @@ proc check_effective_target_riscv_zvfh_ok { } { + # check if we can execute vector insns with the given hardware or + # simulator + set gcc_march [regsub {[[:alnum:]]*} [riscv_get_arch] &v] +- if { [check_runtime ${gcc_march}_exec { ++ if { [check_runtime ${gcc_march}_zvfh_exec { + int main() + { + asm ("vsetivli zero,8,e16,m1,ta,ma"); +@@ -2115,6 +2115,8 @@ proc check_effective_target_riscv_zvfh_ok { } { + return 0 + } + ++# Return 1 if we can execute code when using dg-add-options riscv_zvbb ++ + proc check_effective_target_riscv_zvbb_ok { } { + # If the target already supports v without any added options, + # we may assume we can execute just fine. +@@ -2134,6 +2136,28 @@ proc check_effective_target_riscv_zvbb_ok { } { + } } "-march=${gcc_march}"] } { + return 1 + } ++ return 0 ++} ++ ++# Return 1 if we can load a vector from a 1-byte aligned address. ++ ++proc check_effective_target_riscv_v_misalign_ok { } { ++ ++ if { ![check_effective_target_riscv_v_ok] } { ++ return 0 ++ } ++ ++ set gcc_march [riscv_get_arch] ++ if { [check_runtime ${gcc_march}_misalign_exec { ++ int main() { ++ unsigned char a[16] ++ = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15}; ++ asm ("vsetivli zero,7,e8,m1,ta,ma"); ++ asm ("addi a7,%0,1" : : "r" (a) : "a7" ); ++ asm ("vle8.v v8,0(a7)" : : : "v8"); ++ return 0; } } "-march=${gcc_march}"] } { ++ return 1 ++ } + + return 0 + } +@@ -8498,7 +8522,6 @@ proc check_effective_target_vect_hw_misalign { } { + || ([istarget mips*-*-*] && [et-is-effective-target mips_msa]) + || ([istarget s390*-*-*] + && [check_effective_target_s390_vx]) +- || ([istarget riscv*-*-*]) + || ([istarget loongarch*-*-*]) + || [istarget amdgcn*-*-*] } { + return 1 +@@ -8507,6 +8530,11 @@ proc check_effective_target_vect_hw_misalign { } { + && ![check_effective_target_arm_vect_no_misalign] } { + return 1 + } ++ if { [istarget riscv*-*-*] ++ && [check_effective_target_riscv_v_misalign_ok] } { ++ return 1 ++ } ++ + return 0 + }] + } +@@ -11924,6 +11952,9 @@ proc check_vect_support_and_set_flags { } { + } elseif [istarget riscv*-*-*] { + if [check_effective_target_riscv_v] { + set dg-do-what-default run ++ if [check_effective_target_riscv_v_misalign_ok] { ++ lappend DEFAULT_VECTCFLAGS "-mno-vector-strict-align" ++ } + } else { + foreach item [add_options_for_riscv_v ""] { + lappend DEFAULT_VECTCFLAGS $item +-- +2.47.3 + diff --git a/1017-RISC-V-Disable-misaligned-vector-access-in-hook-risc.patch b/1017-RISC-V-Disable-misaligned-vector-access-in-hook-risc.patch new file mode 100644 index 0000000..0e2a181 --- /dev/null +++ b/1017-RISC-V-Disable-misaligned-vector-access-in-hook-risc.patch @@ -0,0 +1,111 @@ +From b722a1fb28fef49bf15e1a523932b55ac4cc90fb Mon Sep 17 00:00:00 2001 +From: xuli +Date: Thu, 11 Jul 2024 04:29:11 +0000 +Subject: [PATCH 1017/1087] RISC-V: Disable misaligned vector access in hook + riscv_slow_unaligned_access[PR115862] + +commit upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +The reason is that in the following code, icode = movmisalignv8si has +already been rejected by TARGET_VECTOR_MISALIGN_SUPPORTED, but it is +allowed by targetm.slow_unaligned_access,which is contradictory. + +(((icode = optab_handler (movmisalign_optab, mode)) + != CODE_FOR_nothing) + || targetm.slow_unaligned_access (mode, align)) + +misaligned vector access should be enabled by -mno-vector-strict-align option. + + PR target/115862 + +gcc/ChangeLog: + + * config/riscv/riscv.cc (riscv_slow_unaligned_access): Disable vector misalign. + +Signed-off-by: Li Xu +--- + gcc/config/riscv/riscv.cc | 5 +- + .../gcc.target/riscv/rvv/base/pr115862.c | 52 +++++++++++++++++++ + 2 files changed, 55 insertions(+), 2 deletions(-) + create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr115862.c + +diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc +index 2e95bc2f0ee..e610e1970da 100644 +--- a/gcc/config/riscv/riscv.cc ++++ b/gcc/config/riscv/riscv.cc +@@ -9903,9 +9903,10 @@ riscv_cannot_copy_insn_p (rtx_insn *insn) + /* Implement TARGET_SLOW_UNALIGNED_ACCESS. */ + + static bool +-riscv_slow_unaligned_access (machine_mode, unsigned int) ++riscv_slow_unaligned_access (machine_mode mode, unsigned int) + { +- return riscv_slow_unaligned_access_p; ++ return VECTOR_MODE_P (mode) ? TARGET_VECTOR_MISALIGN_SUPPORTED ++ : riscv_slow_unaligned_access_p; + } + + /* Implement TARGET_CAN_CHANGE_MODE_CLASS. */ +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr115862.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115862.c +new file mode 100644 +index 00000000000..3cbc3c3a0ea +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115862.c +@@ -0,0 +1,52 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -march=rv64gcv_zvl512b -mabi=lp64d" } */ ++ ++struct mallinfo2 ++{ ++ int arena; ++ int ordblks; ++ int smblks; ++ int hblks; ++ int hblkhd; ++ int usmblks; ++ int fsmblks; ++ int uordblks; ++ int fordblks; ++ int keepcost; ++}; ++ ++struct mallinfo ++{ ++ int arena; ++ int ordblks; ++ int smblks; ++ int hblks; ++ int hblkhd; ++ int usmblks; ++ int fsmblks; ++ int uordblks; ++ int fordblks; ++ int keepcost; ++}; ++ ++struct mallinfo ++__libc_mallinfo (void) ++{ ++ struct mallinfo m; ++ struct mallinfo2 m2; ++ ++ m.arena = m2.arena; ++ m.ordblks = m2.ordblks; ++ m.smblks = m2.smblks; ++ m.hblks = m2.hblks; ++ m.hblkhd = m2.hblkhd; ++ m.usmblks = m2.usmblks; ++ m.fsmblks = m2.fsmblks; ++ m.uordblks = m2.uordblks; ++ m.fordblks = m2.fordblks; ++ m.keepcost = m2.keepcost; ++ ++ return m; ++} ++ ++/* { dg-final { scan-assembler {vle32\.v} } } */ +-- +2.47.3 + diff --git a/1018-expr-Export-clear_by_pieces.patch b/1018-expr-Export-clear_by_pieces.patch new file mode 100644 index 0000000..6fa0df8 --- /dev/null +++ b/1018-expr-Export-clear_by_pieces.patch @@ -0,0 +1,64 @@ +From b50b322e4ae65151b9e1002f94c070bb61cf224d Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Christoph=20M=C3=BCllner?= +Date: Tue, 14 May 2024 09:19:13 -0600 +Subject: [PATCH 1018/1087] expr: Export clear_by_pieces() + +commit e6e41b68fd805ab126895a20bb9670442b198f62 upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +Make clear_by_pieces() available to other parts of the compiler, +similar to store_by_pieces(). + +gcc/ChangeLog: + + * expr.cc (clear_by_pieces): Remove static from clear_by_pieces. + * expr.h (clear_by_pieces): Add prototype for clear_by_pieces. +--- + gcc/expr.cc | 6 +----- + gcc/expr.h | 5 +++++ + 2 files changed, 6 insertions(+), 5 deletions(-) + +diff --git a/gcc/expr.cc b/gcc/expr.cc +index 034d036b188..aae5697c591 100644 +--- a/gcc/expr.cc ++++ b/gcc/expr.cc +@@ -85,7 +85,6 @@ static void emit_block_move_via_sized_loop (rtx, rtx, rtx, unsigned, unsigned); + static void emit_block_move_via_oriented_loop (rtx, rtx, rtx, unsigned, unsigned); + static rtx emit_block_cmp_via_loop (rtx, rtx, rtx, tree, rtx, bool, + unsigned, unsigned); +-static void clear_by_pieces (rtx, unsigned HOST_WIDE_INT, unsigned int); + static rtx_insn *compress_float_constant (rtx, rtx); + static rtx get_subtarget (rtx); + static rtx store_field (rtx, poly_int64, poly_int64, poly_uint64, poly_uint64, +@@ -1840,10 +1839,7 @@ store_by_pieces (rtx to, unsigned HOST_WIDE_INT len, + return to; + } + +-/* Generate several move instructions to clear LEN bytes of block TO. (A MEM +- rtx with BLKmode). ALIGN is maximum alignment we can assume. */ +- +-static void ++void + clear_by_pieces (rtx to, unsigned HOST_WIDE_INT len, unsigned int align) + { + if (len == 0) +diff --git a/gcc/expr.h b/gcc/expr.h +index 64956f63029..75181584108 100644 +--- a/gcc/expr.h ++++ b/gcc/expr.h +@@ -245,6 +245,11 @@ extern bool can_store_by_pieces (unsigned HOST_WIDE_INT, + extern rtx store_by_pieces (rtx, unsigned HOST_WIDE_INT, by_pieces_constfn, + void *, unsigned int, bool, memop_ret); + ++/* Generate several move instructions to clear LEN bytes of block TO. (A MEM ++ rtx with BLKmode). ALIGN is maximum alignment we can assume. */ ++ ++extern void clear_by_pieces (rtx, unsigned HOST_WIDE_INT, unsigned int); ++ + /* If can_store_by_pieces passes for worst-case values near MAX_LEN, call + store_by_pieces within conditionals so as to handle variable LEN efficiently, + storing VAL, if non-NULL_RTX, or valc instead. */ +-- +2.47.3 + diff --git a/1019-RISC-V-testsuite-Make-cmo-tests-LTO-safe.patch b/1019-RISC-V-testsuite-Make-cmo-tests-LTO-safe.patch new file mode 100644 index 0000000..997fe29 --- /dev/null +++ b/1019-RISC-V-testsuite-Make-cmo-tests-LTO-safe.patch @@ -0,0 +1,108 @@ +From c7c9996d42a14d63809f9311bd2db9234219054b Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Christoph=20M=C3=BCllner?= +Date: Tue, 14 May 2024 09:20:18 -0600 +Subject: [PATCH 1019/1087] RISC-V: testsuite: Make cmo tests LTO safe + +commit 21855f960141c1811d6a5f6ad3b2065f20d4b353 upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +Let's add '\t' to the instruction match pattern to avoid false positive +matches when compiling with -flto. + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/cmo-zicbom-1.c: Add \t to test pattern. + * gcc.target/riscv/cmo-zicbom-2.c: Likewise. + * gcc.target/riscv/cmo-zicbop-1.c: Likewise. + * gcc.target/riscv/cmo-zicbop-2.c: Likewise. + * gcc.target/riscv/cmo-zicboz-1.c: Likewise. + * gcc.target/riscv/cmo-zicboz-2.c: Likewise. +--- + gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c | 6 +++--- + gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c | 6 +++--- + gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c | 6 +++--- + gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c | 6 +++--- + gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c | 2 +- + gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c | 2 +- + 6 files changed, 14 insertions(+), 14 deletions(-) + +diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c b/gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c +index 6341f7874d3..02c38e201fa 100644 +--- a/gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c ++++ b/gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c +@@ -24,6 +24,6 @@ void foo3() + __builtin_riscv_zicbom_cbo_inval((void*)0x111); + } + +-/* { dg-final { scan-assembler-times "cbo.clean" 3 } } */ +-/* { dg-final { scan-assembler-times "cbo.flush" 3 } } */ +-/* { dg-final { scan-assembler-times "cbo.inval" 3 } } */ ++/* { dg-final { scan-assembler-times "cbo.clean\t" 3 } } */ ++/* { dg-final { scan-assembler-times "cbo.flush\t" 3 } } */ ++/* { dg-final { scan-assembler-times "cbo.inval\t" 3 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c b/gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c +index a04f106c8b0..040b96952bc 100644 +--- a/gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c ++++ b/gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c +@@ -24,6 +24,6 @@ void foo3() + __builtin_riscv_zicbom_cbo_inval((void*)0x111); + } + +-/* { dg-final { scan-assembler-times "cbo.clean" 3 } } */ +-/* { dg-final { scan-assembler-times "cbo.flush" 3 } } */ +-/* { dg-final { scan-assembler-times "cbo.inval" 3 } } */ ++/* { dg-final { scan-assembler-times "cbo.clean\t" 3 } } */ ++/* { dg-final { scan-assembler-times "cbo.flush\t" 3 } } */ ++/* { dg-final { scan-assembler-times "cbo.inval\t" 3 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c +index c5d78c1763d..97181154d85 100644 +--- a/gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c ++++ b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c +@@ -18,6 +18,6 @@ int foo1() + return __builtin_riscv_zicbop_cbo_prefetchi(1); + } + +-/* { dg-final { scan-assembler-times "prefetch.i" 1 } } */ +-/* { dg-final { scan-assembler-times "prefetch.r" 4 } } */ +-/* { dg-final { scan-assembler-times "prefetch.w" 4 } } */ ++/* { dg-final { scan-assembler-times "prefetch.i\t" 1 } } */ ++/* { dg-final { scan-assembler-times "prefetch.r\t" 4 } } */ ++/* { dg-final { scan-assembler-times "prefetch.w\t" 4 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c +index 6576365b39c..4871a97b21a 100644 +--- a/gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c ++++ b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c +@@ -18,6 +18,6 @@ int foo1() + return __builtin_riscv_zicbop_cbo_prefetchi(1); + } + +-/* { dg-final { scan-assembler-times "prefetch.i" 1 } } */ +-/* { dg-final { scan-assembler-times "prefetch.r" 4 } } */ +-/* { dg-final { scan-assembler-times "prefetch.w" 4 } } */ ++/* { dg-final { scan-assembler-times "prefetch.i\t" 1 } } */ ++/* { dg-final { scan-assembler-times "prefetch.r\t" 4 } } */ ++/* { dg-final { scan-assembler-times "prefetch.w\t" 4 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c b/gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c +index 5eb78ab94b5..63b8782bf89 100644 +--- a/gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c ++++ b/gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c +@@ -10,4 +10,4 @@ void foo1() + __builtin_riscv_zicboz_cbo_zero((void*)0x121); + } + +-/* { dg-final { scan-assembler-times "cbo.zero" 3 } } */ ++/* { dg-final { scan-assembler-times "cbo.zero\t" 3 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c b/gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c +index fdc9c719669..cc3bd505ec0 100644 +--- a/gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c ++++ b/gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c +@@ -10,4 +10,4 @@ void foo1() + __builtin_riscv_zicboz_cbo_zero((void*)0x121); + } + +-/* { dg-final { scan-assembler-times "cbo.zero" 3 } } */ ++/* { dg-final { scan-assembler-times "cbo.zero\t" 3 } } */ +-- +2.47.3 + diff --git a/1020-RISC-V-Add-memset-zero-expansion-to-cbo.zero.patch b/1020-RISC-V-Add-memset-zero-expansion-to-cbo.zero.patch new file mode 100644 index 0000000..62f3b12 --- /dev/null +++ b/1020-RISC-V-Add-memset-zero-expansion-to-cbo.zero.patch @@ -0,0 +1,200 @@ +From 2f11a995da7b41cbb9fc68981b32b3093c31b433 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Christoph=20M=C3=BCllner?= +Date: Tue, 14 May 2024 09:21:17 -0600 +Subject: [PATCH 1020/1087] RISC-V: Add memset-zero expansion to cbo.zero + +commit 54ba8d44bbd703bca6984700b4d6f978890097e2 upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +The Zicboz extension offers the cbo.zero instruction, which can be used +to clean a memory region corresponding to a cache block. +The Zic64b extension defines the cache block size to 64 byte. +If both extensions are available, it is possible to use cbo.zero +to clear memory, if the alignment and size constraints are met. +This patch implements this. + +gcc/ChangeLog: + + * config/riscv/riscv-protos.h (riscv_expand_block_clear): New prototype. + * config/riscv/riscv-string.cc (riscv_expand_block_clear_zicboz_zic64b): + New function to expand a block-clear with cbo.zero. + (riscv_expand_block_clear): New RISC-V block-clear expansion function. + * config/riscv/riscv.md (setmem): New setmem expansion. +--- + gcc/config/riscv/riscv-protos.h | 1 + + gcc/config/riscv/riscv-string.cc | 59 +++++++++++++++++++ + gcc/config/riscv/riscv.md | 24 ++++++++ + .../gcc.target/riscv/cmo-zicboz-zic64-1.c | 43 ++++++++++++++ + 4 files changed, 127 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicboz-zic64-1.c + +diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h +index aa603301fdc..ec1c053564d 100644 +--- a/gcc/config/riscv/riscv-protos.h ++++ b/gcc/config/riscv/riscv-protos.h +@@ -190,6 +190,7 @@ rtl_opt_pass * make_pass_vsetvl (gcc::context *ctxt); + + /* Routines implemented in riscv-string.c. */ + extern bool riscv_expand_block_move (rtx, rtx, rtx); ++extern bool riscv_expand_block_clear (rtx, rtx); + + /* Information about one CPU we know about. */ + struct riscv_cpu_info { +diff --git a/gcc/config/riscv/riscv-string.cc b/gcc/config/riscv/riscv-string.cc +index 1cb9f832bb5..29c272850fa 100644 +--- a/gcc/config/riscv/riscv-string.cc ++++ b/gcc/config/riscv/riscv-string.cc +@@ -787,6 +787,65 @@ riscv_expand_block_move (rtx dest, rtx src, rtx length) + return false; + } + ++/* Expand a block-clear instruction via cbo.zero instructions. */ ++ ++static bool ++riscv_expand_block_clear_zicboz_zic64b (rtx dest, rtx length) ++{ ++ unsigned HOST_WIDE_INT hwi_length; ++ unsigned HOST_WIDE_INT align; ++ const unsigned HOST_WIDE_INT cbo_bytes = 64; ++ ++ gcc_assert (TARGET_ZICBOZ && TARGET_ZIC64B); ++ ++ if (!CONST_INT_P (length)) ++ return false; ++ ++ hwi_length = UINTVAL (length); ++ if (hwi_length < cbo_bytes) ++ return false; ++ ++ align = MEM_ALIGN (dest) / BITS_PER_UNIT; ++ if (align < cbo_bytes) ++ return false; ++ ++ /* We don't emit loops. Instead apply move-bytes limitation. */ ++ unsigned HOST_WIDE_INT max_bytes = RISCV_MAX_MOVE_BYTES_STRAIGHT / ++ UNITS_PER_WORD * cbo_bytes; ++ if (hwi_length > max_bytes) ++ return false; ++ ++ unsigned HOST_WIDE_INT offset = 0; ++ while (offset + cbo_bytes <= hwi_length) ++ { ++ rtx mem = adjust_address (dest, BLKmode, offset); ++ rtx addr = force_reg (Pmode, XEXP (mem, 0)); ++ emit_insn (gen_riscv_zero_di (addr)); ++ offset += cbo_bytes; ++ } ++ ++ if (offset < hwi_length) ++ { ++ rtx mem = adjust_address (dest, BLKmode, offset); ++ clear_by_pieces (mem, hwi_length - offset, align); ++ } ++ ++ return true; ++} ++ ++bool ++riscv_expand_block_clear (rtx dest, rtx length) ++{ ++ /* Only use setmem-zero expansion for Zicboz + Zic64b. */ ++ if (!TARGET_ZICBOZ || !TARGET_ZIC64B) ++ return false; ++ ++ if (optimize_function_for_size_p (cfun)) ++ return false; ++ ++ return riscv_expand_block_clear_zicboz_zic64b (dest, length); ++} ++ + /* --- Vector expanders --- */ + + namespace riscv_vector { +diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md +index 03c564d9d29..faaf660bf30 100644 +--- a/gcc/config/riscv/riscv.md ++++ b/gcc/config/riscv/riscv.md +@@ -2457,6 +2457,30 @@ + FAIL; + }) + ++;; Fill memory with constant byte. ++;; Argument 0 is the destination ++;; Argument 1 is the constant byte ++;; Argument 2 is the length ++;; Argument 3 is the alignment ++ ++(define_expand "setmem" ++ [(parallel [(set (match_operand:BLK 0 "memory_operand") ++ (match_operand:QI 2 "const_int_operand")) ++ (use (match_operand:P 1 "")) ++ (use (match_operand:SI 3 "const_int_operand"))])] ++ "" ++ { ++ /* If value to set is not zero, use the library routine. */ ++ if (operands[2] != const0_rtx) ++ FAIL; ++ ++ if (riscv_expand_block_clear (operands[0], operands[1])) ++ DONE; ++ else ++ FAIL; ++}) ++ ++ + ;; Expand in-line code to clear the instruction cache between operand[0] and + ;; operand[1]. + (define_expand "clear_cache" +diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicboz-zic64-1.c b/gcc/testsuite/gcc.target/riscv/cmo-zicboz-zic64-1.c +new file mode 100644 +index 00000000000..c2d79eb7ae6 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/cmo-zicboz-zic64-1.c +@@ -0,0 +1,43 @@ ++/* { dg-do compile } */ ++/* { dg-options "-march=rv64gc_zic64b_zicboz" { target { rv64 } } } */ ++/* { dg-options "-march=rv32gc_zic64b_zicboz" { target { rv32 } } } */ ++/* { dg-skip-if "" { *-*-* } {"-O0" "-Os" "-Og" "-Oz" "-flto" } } */ ++/* { dg-final { check-function-bodies "**" "" } } */ ++/* { dg-allow-blank-lines-in-output 1 } */ ++ ++/* ++**clear_buf_123: ++** ... ++** cbo\.zero\t0\(a[0-9]+\) ++** sd\tzero,64\(a[0-9]+\) ++** sd\tzero,72\(a[0-9]+\) ++** sd\tzero,80\(a[0-9]+\) ++** sd\tzero,88\(a[0-9]+\) ++** sd\tzero,96\(a[0-9]+\) ++** sd\tzero,104\(a[0-9]+\) ++** sd\tzero,112\(a[0-9]+\) ++** sh\tzero,120\(a[0-9]+\) ++** sb\tzero,122\(a[0-9]+\) ++** ... ++*/ ++int ++clear_buf_123 (void *p) ++{ ++ p = __builtin_assume_aligned(p, 64); ++ __builtin_memset (p, 0, 123); ++} ++ ++/* ++**clear_buf_128: ++** ... ++** cbo\.zero\t0\(a[0-9]+\) ++** addi\ta[0-9]+,a[0-9]+,64 ++** cbo\.zero\t0\(a[0-9]+\) ++** ... ++*/ ++int ++clear_buf_128 (void *p) ++{ ++ p = __builtin_assume_aligned(p, 64); ++ __builtin_memset (p, 0, 128); ++} +-- +2.47.3 + diff --git a/1021-RISC-V-Refine-the-condition-for-add-additional-vars-.patch b/1021-RISC-V-Refine-the-condition-for-add-additional-vars-.patch new file mode 100644 index 0000000..58774a4 --- /dev/null +++ b/1021-RISC-V-Refine-the-condition-for-add-additional-vars-.patch @@ -0,0 +1,113 @@ +From 5173ba26948e6254d75117c81968dcc98f5fcd37 Mon Sep 17 00:00:00 2001 +From: "demin.han" +Date: Tue, 26 Mar 2024 16:52:12 +0800 +Subject: [PATCH 1021/1087] RISC-V: Refine the condition for add additional + vars in RVV cost model + +commit ca2f531cc5db4f1020d4329976610356033e0246 upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +The adjacent_dr_p is sufficient and unnecessary condition for contiguous access. +So unnecessary live-ranges are added and result in smaller LMUL. + +This patch uses MEMORY_ACCESS_TYPE as condition and constrains segment +load/store. + +Tested on RV64 and no regression. + + PR target/114506 + +gcc/ChangeLog: + + * config/riscv/riscv-vector-costs.cc (non_contiguous_memory_access_p): Rename + (need_additional_vector_vars_p): Rename and refine condition + +gcc/testsuite/ChangeLog: + + * gcc.dg/vect/costmodel/riscv/rvv/pr114506.c: New test. + +Signed-off-by: demin.han +--- + gcc/config/riscv/riscv-vector-costs.cc | 23 ++++++++++++------- + .../vect/costmodel/riscv/rvv/pr114506.c | 23 +++++++++++++++++++ + 2 files changed, 38 insertions(+), 8 deletions(-) + create mode 100644 gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr114506.c + +diff --git a/gcc/config/riscv/riscv-vector-costs.cc b/gcc/config/riscv/riscv-vector-costs.cc +index d27bb68a7b9..4582b0db425 100644 +--- a/gcc/config/riscv/riscv-vector-costs.cc ++++ b/gcc/config/riscv/riscv-vector-costs.cc +@@ -563,14 +563,24 @@ get_store_value (gimple *stmt) + return gimple_assign_rhs1 (stmt); + } + +-/* Return true if it is non-contiguous load/store. */ ++/* Return true if addtional vector vars needed. */ + static bool +-non_contiguous_memory_access_p (stmt_vec_info stmt_info) ++need_additional_vector_vars_p (stmt_vec_info stmt_info) + { + enum stmt_vec_info_type type + = STMT_VINFO_TYPE (vect_stmt_to_vectorize (stmt_info)); +- return ((type == load_vec_info_type || type == store_vec_info_type) +- && !adjacent_dr_p (STMT_VINFO_DATA_REF (stmt_info))); ++ if (type == load_vec_info_type || type == store_vec_info_type) ++ { ++ if (STMT_VINFO_GATHER_SCATTER_P (stmt_info) ++ && STMT_VINFO_MEMORY_ACCESS_TYPE (stmt_info) == VMAT_GATHER_SCATTER) ++ return true; ++ ++ machine_mode mode = TYPE_MODE (STMT_VINFO_VECTYPE (stmt_info)); ++ int lmul = riscv_get_v_regno_alignment (mode); ++ if (DR_GROUP_SIZE (stmt_info) * lmul > RVV_M8) ++ return true; ++ } ++ return false; + } + + /* Return the LMUL of the current analysis. */ +@@ -739,10 +749,7 @@ update_local_live_ranges ( + stmt_vec_info stmt_info = vinfo->lookup_stmt (gsi_stmt (si)); + enum stmt_vec_info_type type + = STMT_VINFO_TYPE (vect_stmt_to_vectorize (stmt_info)); +- if (non_contiguous_memory_access_p (stmt_info) +- /* LOAD_LANES/STORE_LANES doesn't need a perm indice. */ +- && STMT_VINFO_MEMORY_ACCESS_TYPE (stmt_info) +- != VMAT_LOAD_STORE_LANES) ++ if (need_additional_vector_vars_p (stmt_info)) + { + /* For non-adjacent load/store STMT, we will potentially + convert it into: +diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr114506.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr114506.c +new file mode 100644 +index 00000000000..a88d24b2d2d +--- /dev/null ++++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr114506.c +@@ -0,0 +1,23 @@ ++/* { dg-do compile } */ ++/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */ ++ ++float a[32000], b[32000], c[32000], d[32000]; ++float aa[256][256], bb[256][256], cc[256][256]; ++ ++void ++s2275 () ++{ ++ for (int i = 0; i < 256; i++) ++ { ++ for (int j = 0; j < 256; j++) ++ { ++ aa[j][i] = aa[j][i] + bb[j][i] * cc[j][i]; ++ } ++ a[i] = b[i] + c[i] * d[i]; ++ } ++} ++ ++/* { dg-final { scan-assembler-times {e32,m8} 1 } } */ ++/* { dg-final { scan-assembler-not {e32,m4} } } */ ++/* { dg-final { scan-assembler-not {csrr} } } */ ++/* { dg-final { scan-tree-dump-not "Preferring smaller LMUL loop because it has unexpected spills" "vect" } } */ +-- +2.47.3 + diff --git a/1022-Fix-detection-of-store-pair-fusion-cases.patch b/1022-Fix-detection-of-store-pair-fusion-cases.patch new file mode 100644 index 0000000..d1c4dca --- /dev/null +++ b/1022-Fix-detection-of-store-pair-fusion-cases.patch @@ -0,0 +1,104 @@ +From 838db196931a95a423f065f6c1a12bdd9c1ad42f Mon Sep 17 00:00:00 2001 +From: Jeff Law +Date: Wed, 1 May 2024 11:28:41 -0600 +Subject: [PATCH 1022/1087] Fix detection of store pair fusion cases + +commit fad93e7617ce1aafb006983a71b6edc9ae1eb2d1 upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +We've got the ability to count the number of store pair fusions happening in +the front-end of the pipeline. When comparing some code from last year vs the +current trunk we saw a fairly dramatic drop. + +The problem is the store pair fusion detection code was actively harmful due to +a minor bug in checking offsets. So instead of pairing up 8 byte stores such +as sp+0 with sp+8, it tried to pair up sp+8 and sp+16. + +Given uarch sensitivity I didn't try to pull together a testcase. But we could +certainly see the undesirable behavior in benchmarks as simplistic as dhrystone +up through spec2017. + +Anyway, bootstrapped a while back. Also verified through our performance +counters that store pair fusion rates are back up. Regression tested with +crosses a few minutes ago. + +gcc/ + * config/riscv/riscv.cc (riscv_macro_fusion_pair_p): Break out + tests for easier debugging in store pair fusion case. Fix offset + check in same. +--- + gcc/config/riscv/riscv.cc | 57 +++++++++++++++++++++++++-------------- + 1 file changed, 37 insertions(+), 20 deletions(-) + +diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc +index e610e1970da..4513650855f 100644 +--- a/gcc/config/riscv/riscv.cc ++++ b/gcc/config/riscv/riscv.cc +@@ -8901,26 +8901,43 @@ riscv_macro_fusion_pair_p (rtx_insn *prev, rtx_insn *curr) + extract_base_offset_in_addr (SET_DEST (prev_set), &base_prev, &offset_prev); + extract_base_offset_in_addr (SET_DEST (curr_set), &base_curr, &offset_curr); + +- /* The two stores must be contained within opposite halves of the same +- 16 byte aligned block of memory. We know that the stack pointer and +- the frame pointer have suitable alignment. So we just need to check +- the offsets of the two stores for suitable alignment. +- +- Originally the thought was to check MEM_ALIGN, but that was reporting +- incorrect alignments, even for SP/FP accesses, so we gave up on that +- approach. */ +- if (base_prev != NULL_RTX +- && base_curr != NULL_RTX +- && REG_P (base_prev) +- && REG_P (base_curr) +- && REGNO (base_prev) == REGNO (base_curr) +- && (REGNO (base_prev) == STACK_POINTER_REGNUM +- || REGNO (base_prev) == HARD_FRAME_POINTER_REGNUM) +- && ((INTVAL (offset_prev) == INTVAL (offset_curr) + 8 +- && (INTVAL (offset_prev) % 16) == 0) +- || ((INTVAL (offset_curr) == INTVAL (offset_prev) + 8) +- && (INTVAL (offset_curr) % 16) == 0))) +- return true; ++ /* Fail if we did not find both bases. */ ++ if (base_prev == NULL_RTX || base_curr == NULL_RTX) ++ return false; ++ ++ /* Fail if either base is not a register. */ ++ if (!REG_P (base_prev) || !REG_P (base_curr)) ++ return false; ++ ++ /* Fail if the bases are not the same register. */ ++ if (REGNO (base_prev) != REGNO (base_curr)) ++ return false; ++ ++ /* Originally the thought was to check MEM_ALIGN, but that was ++ reporting incorrect alignments, even for SP/FP accesses, so we ++ gave up on that approach. Instead just check for stack/hfp ++ which we know are aligned. */ ++ if (REGNO (base_prev) != STACK_POINTER_REGNUM ++ && REGNO (base_prev) != HARD_FRAME_POINTER_REGNUM) ++ return false; ++ ++ /* The two stores must be contained within opposite halves of the ++ same 16 byte aligned block of memory. We know that the stack ++ pointer and the frame pointer have suitable alignment. So we ++ just need to check the offsets of the two stores for suitable ++ alignment. */ ++ /* Get the smaller offset into OFFSET_PREV. */ ++ if (INTVAL (offset_prev) > INTVAL (offset_curr)) ++ std::swap (offset_prev, offset_curr); ++ ++ /* If the smaller offset (OFFSET_PREV) is not 16 byte aligned, ++ then fail. */ ++ if ((INTVAL (offset_prev) % 16) != 0) ++ return false; ++ ++ /* The higher offset must be 8 bytes more than the lower ++ offset. */ ++ return (INTVAL (offset_prev) + 8 == INTVAL (offset_curr)); + } + } + +-- +2.47.3 + diff --git a/1023-Improve-constant-synthesis-for-constants-with-2-bits.patch b/1023-Improve-constant-synthesis-for-constants-with-2-bits.patch new file mode 100644 index 0000000..41167de --- /dev/null +++ b/1023-Improve-constant-synthesis-for-constants-with-2-bits.patch @@ -0,0 +1,2248 @@ +From 7aeddc0bfae8b4cc8d42efa51920bf27e5fea99c Mon Sep 17 00:00:00 2001 +From: Jeff Law +Date: Thu, 2 May 2024 14:06:22 -0600 +Subject: [PATCH 1023/1087] Improve constant synthesis for constants with 2 + bits set + +commit 9b54bea455e54fd138bf2b045bdcc133ed4e8a84 upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +In doing some preparation work for using zbkb's pack instructions for constant +synthesis I figured it would be wise to get a sense of how well our constant +synthesis is actually working and address any clear issues. + +So the first glaring inefficiency is in our handling of constants with a small +number of bits set. Let's start with just two bits set. There are 2016 +distinct constants in that space (rv64). With Zbs enabled the absolute worst +we should ever do is two instructions (bseti+bseti). Yet we have 503 cases +where we're generating 3+ instructions when there's just two bits set in the +constant. A constant like 0x8000000000001000 generates 4 instructions! + +This patch adds bseti (and indirectly binvi if we needed it) as a first class +citizen for constant synthesis. There's two components to this change. + +First, we can't generate an IOR with a constant like (1 << 45) as an operand. +The IOR/XOR define_insn is in riscv.md. The constant argument for those +patterns must match an arith_operand which means its not really usable for +generating bseti directly in the cases we care about (at least one of the bits +will be in the 32..63 range and thus won't match arith_operand). + +We have a few things we could do. One would be to extend the existing pattern +to incorporate bseti cases. But I suspect folks like the separation of the +base architecture (riscv.md) from the Zb* extensions (bitmanip.md). We could +also try to generate the RTL for bseti +directly, bypassing gen_fmt_ee (which forces undesirable constants into registers based on the predicate of the appropriate define_insn). Neither of these seemed particularly appealing to me. + +So what I've done instead is to make ior/xor a define_expand and have the +expander allow a wider set of constant operands when Zbs is enabled. That +allows us to keep the bulk of Zb* support inside bitmanip.md and continue to +use gen_fmt_ee in the constant synthesis paths. + +Note the code generation in this case is designed to first set as many bits as +we can with lui, then with addi since those can both set multiple bits at a +time. If there are any residual bits left to set we can emit bseti +instructions up to the current cost ceiling. + +This results in fixing all of the 503 2-bit set cases where we emitted too many +instructions. It also significantly helps other scenarios with more bits set. + +The testcase I'm including verifies the number of instructions we generate for +the full set of 2016 possible cases. Obviously this won't be possible as we +increase the number of bits (there are something like 48k cases with just 3 +bits set). + +gcc/ + + * config/riscv/predicates.md (arith_or_zbs_operand): New predicate. + * config/riscv/riscv.cc (riscv_build_integer_one): Use bseti to set + single bits when profitable. + * config/riscv/riscv.md (*3): Renamed with '*' prefix. + (3): New expander for IOR/XOR. + +gcc/testsuite + * gcc.target/riscv/synthesis-1.c: New test. +--- + gcc/config/riscv/predicates.md | 8 + + gcc/config/riscv/riscv.cc | 65 +- + gcc/config/riscv/riscv.md | 17 +- + gcc/testsuite/gcc.target/riscv/synthesis-1.c | 2034 ++++++++++++++++++ + 4 files changed, 2110 insertions(+), 14 deletions(-) + create mode 100644 gcc/testsuite/gcc.target/riscv/synthesis-1.c + +diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md +index 1e2df96707a..6a895a6970c 100644 +--- a/gcc/config/riscv/predicates.md ++++ b/gcc/config/riscv/predicates.md +@@ -386,6 +386,14 @@ + (and (match_code "const_int") + (match_test "SINGLE_BIT_MASK_OPERAND (UINTVAL (op))"))) + ++;; Register, small constant or single bit constant for use in ++;; bseti/binvi. ++(define_predicate "arith_or_zbs_operand" ++ (ior (match_operand 0 "const_arith_operand") ++ (match_operand 0 "register_operand") ++ (and (match_test "TARGET_ZBS") ++ (match_operand 0 "single_bit_mask_operand")))) ++ + (define_predicate "not_single_bit_mask_operand" + (and (match_code "const_int") + (match_test "SINGLE_BIT_MASK_OPERAND (~UINTVAL (op))"))) +diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc +index 4513650855f..62e733175df 100644 +--- a/gcc/config/riscv/riscv.cc ++++ b/gcc/config/riscv/riscv.cc +@@ -747,6 +747,9 @@ riscv_build_integer_1 (struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS], + HOST_WIDE_INT low_part = CONST_LOW_PART (value); + int cost = RISCV_MAX_INTEGER_OPS + 1, alt_cost; + struct riscv_integer_op alt_codes[RISCV_MAX_INTEGER_OPS]; ++ int upper_trailing_ones = ctz_hwi (~value >> 32); ++ int lower_leading_ones = clz_hwi (~value << 32); ++ + + if (SMALL_OPERAND (value) || LUI_OPERAND (value)) + { +@@ -847,22 +850,58 @@ riscv_build_integer_1 (struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS], + cost = 2; + } + /* Handle the case where the 11 bit range of zero bits wraps around. */ +- else ++ else if (upper_trailing_ones < 32 && lower_leading_ones < 32 ++ && ((64 - upper_trailing_ones - lower_leading_ones) < 12)) + { +- int upper_trailing_ones = ctz_hwi (~value >> 32); +- int lower_leading_ones = clz_hwi (~value << 32); ++ codes[0].code = UNKNOWN; ++ /* The sign-bit might be zero, so just rotate to be safe. */ ++ codes[0].value = ((value << (32 - upper_trailing_ones)) ++ | ((unsigned HOST_WIDE_INT) value ++ >> (32 + upper_trailing_ones))); ++ codes[1].code = ROTATERT; ++ codes[1].value = 32 - upper_trailing_ones; ++ cost = 2; ++ } ++ /* Final cases, particularly focused on bseti. */ ++ else if (cost > 2 && TARGET_ZBS) ++ { ++ int i = 0; ++ ++ /* First handle any bits set by LUI. Be careful of the ++ SImode sign bit!. */ ++ if (value & 0x7ffff800) ++ { ++ alt_codes[i].code = (i == 0 ? UNKNOWN : IOR); ++ alt_codes[i].value = value & 0x7ffff800; ++ value &= ~0x7ffff800; ++ i++; ++ } ++ ++ /* Next, any bits we can handle with addi. */ ++ if (value & 0x7ff) ++ { ++ alt_codes[i].code = (i == 0 ? UNKNOWN : PLUS); ++ alt_codes[i].value = value & 0x7ff; ++ value &= ~0x7ff; ++ i++; ++ } ++ ++ /* And any residuals with bseti. */ ++ while (i < cost && value) ++ { ++ HOST_WIDE_INT bit = ctz_hwi (value); ++ alt_codes[i].code = (i == 0 ? UNKNOWN : IOR); ++ alt_codes[i].value = 1UL << bit; ++ value &= ~(1ULL << bit); ++ i++; ++ } + +- if (upper_trailing_ones < 32 && lower_leading_ones < 32 +- && ((64 - upper_trailing_ones - lower_leading_ones) < 12)) ++ /* If LUI+ADDI+BSETI resulted in a more efficient ++ sequence, then use it. */ ++ if (i < cost) + { +- codes[0].code = UNKNOWN; +- /* The sign-bit might be zero, so just rotate to be safe. */ +- codes[0].value = ((value << (32 - upper_trailing_ones)) +- | ((unsigned HOST_WIDE_INT) value +- >> (32 + upper_trailing_ones))); +- codes[1].code = ROTATERT; +- codes[1].value = 32 - upper_trailing_ones; +- cost = 2; ++ memcpy (codes, alt_codes, sizeof (alt_codes)); ++ cost = i; + } + } + } +diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md +index faaf660bf30..dcce06b6704 100644 +--- a/gcc/config/riscv/riscv.md ++++ b/gcc/config/riscv/riscv.md +@@ -1653,7 +1653,22 @@ + [(set_attr "type" "logical") + (set_attr "mode" "")]) + +-(define_insn "3" ++;; When we construct constants we may want to twiddle a single bit ++;; by generating an IOR. But the constant likely doesn't fit ++;; arith_operand. So the generic code will reload the constant into ++;; a register. Post-reload we won't have the chance to squash things ++;; back into a Zbs insn. ++;; ++;; So indirect through a define_expand. That allows us to have a ++;; predicate that conditionally accepts single bit constants without ++;; putting the details of Zbs instructions in here. ++(define_expand "3" ++ [(set (match_operand:X 0 "register_operand") ++ (any_or:X (match_operand:X 1 "register_operand" "") ++ (match_operand:X 2 "arith_or_zbs_operand" "")))] ++ "") ++ ++(define_insn "*3" + [(set (match_operand:X 0 "register_operand" "=r,r") + (any_or:X (match_operand:X 1 "register_operand" "%r,r") + (match_operand:X 2 "arith_operand" " r,I")))] +diff --git a/gcc/testsuite/gcc.target/riscv/synthesis-1.c b/gcc/testsuite/gcc.target/riscv/synthesis-1.c +new file mode 100644 +index 00000000000..3384e488ade +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/synthesis-1.c +@@ -0,0 +1,2034 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target rv64 } */ ++/* We aggressively skip as we really just need to test the basic synthesis ++ which shouldn't vary based on the optimization level. -O1 seems to work ++ and eliminates the usual sources of extraneous dead code that would throw ++ off the counts. */ ++/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O2" "-O3" "-Os" "-Oz" "-flto" } } */ ++/* { dg-options "-march=rv64gc_zba_zbb_zbs" } */ ++ ++/* Rather than test for a specific synthesis of all these constants or ++ having thousands of tests each testing one variant, we just test the ++ total number of instructions. ++ ++ This isn't expected to change much and any change is worthy of a look. */ ++/* { dg-final { scan-assembler-times "\\t(add|addi|bseti|li|ret|slli)" 5822 } } */ ++ ++ unsigned long foo_0x3(void) { return 0x3UL; } ++ unsigned long foo_0x5(void) { return 0x5UL; } ++ unsigned long foo_0x9(void) { return 0x9UL; } ++ unsigned long foo_0x11(void) { return 0x11UL; } ++ unsigned long foo_0x21(void) { return 0x21UL; } ++ unsigned long foo_0x41(void) { return 0x41UL; } ++ unsigned long foo_0x81(void) { return 0x81UL; } ++ unsigned long foo_0x101(void) { return 0x101UL; } ++ unsigned long foo_0x201(void) { return 0x201UL; } ++ unsigned long foo_0x401(void) { return 0x401UL; } ++ unsigned long foo_0x801(void) { return 0x801UL; } ++ unsigned long foo_0x1001(void) { return 0x1001UL; } ++ unsigned long foo_0x2001(void) { return 0x2001UL; } ++ unsigned long foo_0x4001(void) { return 0x4001UL; } ++ unsigned long foo_0x8001(void) { return 0x8001UL; } ++ unsigned long foo_0x10001(void) { return 0x10001UL; } ++ unsigned long foo_0x20001(void) { return 0x20001UL; } ++ unsigned long foo_0x40001(void) { return 0x40001UL; } ++ unsigned long foo_0x80001(void) { return 0x80001UL; } ++ unsigned long foo_0x100001(void) { return 0x100001UL; } ++ unsigned long foo_0x200001(void) { return 0x200001UL; } ++ unsigned long foo_0x400001(void) { return 0x400001UL; } ++ unsigned long foo_0x800001(void) { return 0x800001UL; } ++ unsigned long foo_0x1000001(void) { return 0x1000001UL; } ++ unsigned long foo_0x2000001(void) { return 0x2000001UL; } ++ unsigned long foo_0x4000001(void) { return 0x4000001UL; } ++ unsigned long foo_0x8000001(void) { return 0x8000001UL; } ++ unsigned long foo_0x10000001(void) { return 0x10000001UL; } ++ unsigned long foo_0x20000001(void) { return 0x20000001UL; } ++ unsigned long foo_0x40000001(void) { return 0x40000001UL; } ++ unsigned long foo_0x80000001(void) { return 0x80000001UL; } ++ unsigned long foo_0x100000001(void) { return 0x100000001UL; } ++ unsigned long foo_0x200000001(void) { return 0x200000001UL; } ++ unsigned long foo_0x400000001(void) { return 0x400000001UL; } ++ unsigned long foo_0x800000001(void) { return 0x800000001UL; } ++ unsigned long foo_0x1000000001(void) { return 0x1000000001UL; } ++ unsigned long foo_0x2000000001(void) { return 0x2000000001UL; } ++ unsigned long foo_0x4000000001(void) { return 0x4000000001UL; } ++ unsigned long foo_0x8000000001(void) { return 0x8000000001UL; } ++ unsigned long foo_0x10000000001(void) { return 0x10000000001UL; } ++ unsigned long foo_0x20000000001(void) { return 0x20000000001UL; } ++ unsigned long foo_0x40000000001(void) { return 0x40000000001UL; } ++ unsigned long foo_0x80000000001(void) { return 0x80000000001UL; } ++ unsigned long foo_0x100000000001(void) { return 0x100000000001UL; } ++ unsigned long foo_0x200000000001(void) { return 0x200000000001UL; } ++ unsigned long foo_0x400000000001(void) { return 0x400000000001UL; } ++ unsigned long foo_0x800000000001(void) { return 0x800000000001UL; } ++ unsigned long foo_0x1000000000001(void) { return 0x1000000000001UL; } ++ unsigned long foo_0x2000000000001(void) { return 0x2000000000001UL; } ++ unsigned long foo_0x4000000000001(void) { return 0x4000000000001UL; } ++ unsigned long foo_0x8000000000001(void) { return 0x8000000000001UL; } ++ unsigned long foo_0x10000000000001(void) { return 0x10000000000001UL; } ++ unsigned long foo_0x20000000000001(void) { return 0x20000000000001UL; } ++ unsigned long foo_0x40000000000001(void) { return 0x40000000000001UL; } ++ unsigned long foo_0x80000000000001(void) { return 0x80000000000001UL; } ++ unsigned long foo_0x100000000000001(void) { return 0x100000000000001UL; } ++ unsigned long foo_0x200000000000001(void) { return 0x200000000000001UL; } ++ unsigned long foo_0x400000000000001(void) { return 0x400000000000001UL; } ++ unsigned long foo_0x800000000000001(void) { return 0x800000000000001UL; } ++ unsigned long foo_0x1000000000000001(void) { return 0x1000000000000001UL; } ++ unsigned long foo_0x2000000000000001(void) { return 0x2000000000000001UL; } ++ unsigned long foo_0x4000000000000001(void) { return 0x4000000000000001UL; } ++ unsigned long foo_0x8000000000000001(void) { return 0x8000000000000001UL; } ++ unsigned long foo_0x6(void) { return 0x6UL; } ++ unsigned long foo_0xa(void) { return 0xaUL; } ++ unsigned long foo_0x12(void) { return 0x12UL; } ++ unsigned long foo_0x22(void) { return 0x22UL; } ++ unsigned long foo_0x42(void) { return 0x42UL; } ++ unsigned long foo_0x82(void) { return 0x82UL; } ++ unsigned long foo_0x102(void) { return 0x102UL; } ++ unsigned long foo_0x202(void) { return 0x202UL; } ++ unsigned long foo_0x402(void) { return 0x402UL; } ++ unsigned long foo_0x802(void) { return 0x802UL; } ++ unsigned long foo_0x1002(void) { return 0x1002UL; } ++ unsigned long foo_0x2002(void) { return 0x2002UL; } ++ unsigned long foo_0x4002(void) { return 0x4002UL; } ++ unsigned long foo_0x8002(void) { return 0x8002UL; } ++ unsigned long foo_0x10002(void) { return 0x10002UL; } ++ unsigned long foo_0x20002(void) { return 0x20002UL; } ++ unsigned long foo_0x40002(void) { return 0x40002UL; } ++ unsigned long foo_0x80002(void) { return 0x80002UL; } ++ unsigned long foo_0x100002(void) { return 0x100002UL; } ++ unsigned long foo_0x200002(void) { return 0x200002UL; } ++ unsigned long foo_0x400002(void) { return 0x400002UL; } ++ unsigned long foo_0x800002(void) { return 0x800002UL; } ++ unsigned long foo_0x1000002(void) { return 0x1000002UL; } ++ unsigned long foo_0x2000002(void) { return 0x2000002UL; } ++ unsigned long foo_0x4000002(void) { return 0x4000002UL; } ++ unsigned long foo_0x8000002(void) { return 0x8000002UL; } ++ unsigned long foo_0x10000002(void) { return 0x10000002UL; } ++ unsigned long foo_0x20000002(void) { return 0x20000002UL; } ++ unsigned long foo_0x40000002(void) { return 0x40000002UL; } ++ unsigned long foo_0x80000002(void) { return 0x80000002UL; } ++ unsigned long foo_0x100000002(void) { return 0x100000002UL; } ++ unsigned long foo_0x200000002(void) { return 0x200000002UL; } ++ unsigned long foo_0x400000002(void) { return 0x400000002UL; } ++ unsigned long foo_0x800000002(void) { return 0x800000002UL; } ++ unsigned long foo_0x1000000002(void) { return 0x1000000002UL; } ++ unsigned long foo_0x2000000002(void) { return 0x2000000002UL; } ++ unsigned long foo_0x4000000002(void) { return 0x4000000002UL; } ++ unsigned long foo_0x8000000002(void) { return 0x8000000002UL; } ++ unsigned long foo_0x10000000002(void) { return 0x10000000002UL; } ++ unsigned long foo_0x20000000002(void) { return 0x20000000002UL; } ++ unsigned long foo_0x40000000002(void) { return 0x40000000002UL; } ++ unsigned long foo_0x80000000002(void) { return 0x80000000002UL; } ++ unsigned long foo_0x100000000002(void) { return 0x100000000002UL; } ++ unsigned long foo_0x200000000002(void) { return 0x200000000002UL; } ++ unsigned long foo_0x400000000002(void) { return 0x400000000002UL; } ++ unsigned long foo_0x800000000002(void) { return 0x800000000002UL; } ++ unsigned long foo_0x1000000000002(void) { return 0x1000000000002UL; } ++ unsigned long foo_0x2000000000002(void) { return 0x2000000000002UL; } ++ unsigned long foo_0x4000000000002(void) { return 0x4000000000002UL; } ++ unsigned long foo_0x8000000000002(void) { return 0x8000000000002UL; } ++ unsigned long foo_0x10000000000002(void) { return 0x10000000000002UL; } ++ unsigned long foo_0x20000000000002(void) { return 0x20000000000002UL; } ++ unsigned long foo_0x40000000000002(void) { return 0x40000000000002UL; } ++ unsigned long foo_0x80000000000002(void) { return 0x80000000000002UL; } ++ unsigned long foo_0x100000000000002(void) { return 0x100000000000002UL; } ++ unsigned long foo_0x200000000000002(void) { return 0x200000000000002UL; } ++ unsigned long foo_0x400000000000002(void) { return 0x400000000000002UL; } ++ unsigned long foo_0x800000000000002(void) { return 0x800000000000002UL; } ++ unsigned long foo_0x1000000000000002(void) { return 0x1000000000000002UL; } ++ unsigned long foo_0x2000000000000002(void) { return 0x2000000000000002UL; } ++ unsigned long foo_0x4000000000000002(void) { return 0x4000000000000002UL; } ++ unsigned long foo_0x8000000000000002(void) { return 0x8000000000000002UL; } ++ unsigned long foo_0xc(void) { return 0xcUL; } ++ unsigned long foo_0x14(void) { return 0x14UL; } ++ unsigned long foo_0x24(void) { return 0x24UL; } ++ unsigned long foo_0x44(void) { return 0x44UL; } ++ unsigned long foo_0x84(void) { return 0x84UL; } ++ unsigned long foo_0x104(void) { return 0x104UL; } ++ unsigned long foo_0x204(void) { return 0x204UL; } ++ unsigned long foo_0x404(void) { return 0x404UL; } ++ unsigned long foo_0x804(void) { return 0x804UL; } ++ unsigned long foo_0x1004(void) { return 0x1004UL; } ++ unsigned long foo_0x2004(void) { return 0x2004UL; } ++ unsigned long foo_0x4004(void) { return 0x4004UL; } ++ unsigned long foo_0x8004(void) { return 0x8004UL; } ++ unsigned long foo_0x10004(void) { return 0x10004UL; } ++ unsigned long foo_0x20004(void) { return 0x20004UL; } ++ unsigned long foo_0x40004(void) { return 0x40004UL; } ++ unsigned long foo_0x80004(void) { return 0x80004UL; } ++ unsigned long foo_0x100004(void) { return 0x100004UL; } ++ unsigned long foo_0x200004(void) { return 0x200004UL; } ++ unsigned long foo_0x400004(void) { return 0x400004UL; } ++ unsigned long foo_0x800004(void) { return 0x800004UL; } ++ unsigned long foo_0x1000004(void) { return 0x1000004UL; } ++ unsigned long foo_0x2000004(void) { return 0x2000004UL; } ++ unsigned long foo_0x4000004(void) { return 0x4000004UL; } ++ unsigned long foo_0x8000004(void) { return 0x8000004UL; } ++ unsigned long foo_0x10000004(void) { return 0x10000004UL; } ++ unsigned long foo_0x20000004(void) { return 0x20000004UL; } ++ unsigned long foo_0x40000004(void) { return 0x40000004UL; } ++ unsigned long foo_0x80000004(void) { return 0x80000004UL; } ++ unsigned long foo_0x100000004(void) { return 0x100000004UL; } ++ unsigned long foo_0x200000004(void) { return 0x200000004UL; } ++ unsigned long foo_0x400000004(void) { return 0x400000004UL; } ++ unsigned long foo_0x800000004(void) { return 0x800000004UL; } ++ unsigned long foo_0x1000000004(void) { return 0x1000000004UL; } ++ unsigned long foo_0x2000000004(void) { return 0x2000000004UL; } ++ unsigned long foo_0x4000000004(void) { return 0x4000000004UL; } ++ unsigned long foo_0x8000000004(void) { return 0x8000000004UL; } ++ unsigned long foo_0x10000000004(void) { return 0x10000000004UL; } ++ unsigned long foo_0x20000000004(void) { return 0x20000000004UL; } ++ unsigned long foo_0x40000000004(void) { return 0x40000000004UL; } ++ unsigned long foo_0x80000000004(void) { return 0x80000000004UL; } ++ unsigned long foo_0x100000000004(void) { return 0x100000000004UL; } ++ unsigned long foo_0x200000000004(void) { return 0x200000000004UL; } ++ unsigned long foo_0x400000000004(void) { return 0x400000000004UL; } ++ unsigned long foo_0x800000000004(void) { return 0x800000000004UL; } ++ unsigned long foo_0x1000000000004(void) { return 0x1000000000004UL; } ++ unsigned long foo_0x2000000000004(void) { return 0x2000000000004UL; } ++ unsigned long foo_0x4000000000004(void) { return 0x4000000000004UL; } ++ unsigned long foo_0x8000000000004(void) { return 0x8000000000004UL; } ++ unsigned long foo_0x10000000000004(void) { return 0x10000000000004UL; } ++ unsigned long foo_0x20000000000004(void) { return 0x20000000000004UL; } ++ unsigned long foo_0x40000000000004(void) { return 0x40000000000004UL; } ++ unsigned long foo_0x80000000000004(void) { return 0x80000000000004UL; } ++ unsigned long foo_0x100000000000004(void) { return 0x100000000000004UL; } ++ unsigned long foo_0x200000000000004(void) { return 0x200000000000004UL; } ++ unsigned long foo_0x400000000000004(void) { return 0x400000000000004UL; } ++ unsigned long foo_0x800000000000004(void) { return 0x800000000000004UL; } ++ unsigned long foo_0x1000000000000004(void) { return 0x1000000000000004UL; } ++ unsigned long foo_0x2000000000000004(void) { return 0x2000000000000004UL; } ++ unsigned long foo_0x4000000000000004(void) { return 0x4000000000000004UL; } ++ unsigned long foo_0x8000000000000004(void) { return 0x8000000000000004UL; } ++ unsigned long foo_0x18(void) { return 0x18UL; } ++ unsigned long foo_0x28(void) { return 0x28UL; } ++ unsigned long foo_0x48(void) { return 0x48UL; } ++ unsigned long foo_0x88(void) { return 0x88UL; } ++ unsigned long foo_0x108(void) { return 0x108UL; } ++ unsigned long foo_0x208(void) { return 0x208UL; } ++ unsigned long foo_0x408(void) { return 0x408UL; } ++ unsigned long foo_0x808(void) { return 0x808UL; } ++ unsigned long foo_0x1008(void) { return 0x1008UL; } ++ unsigned long foo_0x2008(void) { return 0x2008UL; } ++ unsigned long foo_0x4008(void) { return 0x4008UL; } ++ unsigned long foo_0x8008(void) { return 0x8008UL; } ++ unsigned long foo_0x10008(void) { return 0x10008UL; } ++ unsigned long foo_0x20008(void) { return 0x20008UL; } ++ unsigned long foo_0x40008(void) { return 0x40008UL; } ++ unsigned long foo_0x80008(void) { return 0x80008UL; } ++ unsigned long foo_0x100008(void) { return 0x100008UL; } ++ unsigned long foo_0x200008(void) { return 0x200008UL; } ++ unsigned long foo_0x400008(void) { return 0x400008UL; } ++ unsigned long foo_0x800008(void) { return 0x800008UL; } ++ unsigned long foo_0x1000008(void) { return 0x1000008UL; } ++ unsigned long foo_0x2000008(void) { return 0x2000008UL; } ++ unsigned long foo_0x4000008(void) { return 0x4000008UL; } ++ unsigned long foo_0x8000008(void) { return 0x8000008UL; } ++ unsigned long foo_0x10000008(void) { return 0x10000008UL; } ++ unsigned long foo_0x20000008(void) { return 0x20000008UL; } ++ unsigned long foo_0x40000008(void) { return 0x40000008UL; } ++ unsigned long foo_0x80000008(void) { return 0x80000008UL; } ++ unsigned long foo_0x100000008(void) { return 0x100000008UL; } ++ unsigned long foo_0x200000008(void) { return 0x200000008UL; } ++ unsigned long foo_0x400000008(void) { return 0x400000008UL; } ++ unsigned long foo_0x800000008(void) { return 0x800000008UL; } ++ unsigned long foo_0x1000000008(void) { return 0x1000000008UL; } ++ unsigned long foo_0x2000000008(void) { return 0x2000000008UL; } ++ unsigned long foo_0x4000000008(void) { return 0x4000000008UL; } ++ unsigned long foo_0x8000000008(void) { return 0x8000000008UL; } ++ unsigned long foo_0x10000000008(void) { return 0x10000000008UL; } ++ unsigned long foo_0x20000000008(void) { return 0x20000000008UL; } ++ unsigned long foo_0x40000000008(void) { return 0x40000000008UL; } ++ unsigned long foo_0x80000000008(void) { return 0x80000000008UL; } ++ unsigned long foo_0x100000000008(void) { return 0x100000000008UL; } ++ unsigned long foo_0x200000000008(void) { return 0x200000000008UL; } ++ unsigned long foo_0x400000000008(void) { return 0x400000000008UL; } ++ unsigned long foo_0x800000000008(void) { return 0x800000000008UL; } ++ unsigned long foo_0x1000000000008(void) { return 0x1000000000008UL; } ++ unsigned long foo_0x2000000000008(void) { return 0x2000000000008UL; } ++ unsigned long foo_0x4000000000008(void) { return 0x4000000000008UL; } ++ unsigned long foo_0x8000000000008(void) { return 0x8000000000008UL; } ++ unsigned long foo_0x10000000000008(void) { return 0x10000000000008UL; } ++ unsigned long foo_0x20000000000008(void) { return 0x20000000000008UL; } ++ unsigned long foo_0x40000000000008(void) { return 0x40000000000008UL; } ++ unsigned long foo_0x80000000000008(void) { return 0x80000000000008UL; } ++ unsigned long foo_0x100000000000008(void) { return 0x100000000000008UL; } ++ unsigned long foo_0x200000000000008(void) { return 0x200000000000008UL; } ++ unsigned long foo_0x400000000000008(void) { return 0x400000000000008UL; } ++ unsigned long foo_0x800000000000008(void) { return 0x800000000000008UL; } ++ unsigned long foo_0x1000000000000008(void) { return 0x1000000000000008UL; } ++ unsigned long foo_0x2000000000000008(void) { return 0x2000000000000008UL; } ++ unsigned long foo_0x4000000000000008(void) { return 0x4000000000000008UL; } ++ unsigned long foo_0x8000000000000008(void) { return 0x8000000000000008UL; } ++ unsigned long foo_0x30(void) { return 0x30UL; } ++ unsigned long foo_0x50(void) { return 0x50UL; } ++ unsigned long foo_0x90(void) { return 0x90UL; } ++ unsigned long foo_0x110(void) { return 0x110UL; } ++ unsigned long foo_0x210(void) { return 0x210UL; } ++ unsigned long foo_0x410(void) { return 0x410UL; } ++ unsigned long foo_0x810(void) { return 0x810UL; } ++ unsigned long foo_0x1010(void) { return 0x1010UL; } ++ unsigned long foo_0x2010(void) { return 0x2010UL; } ++ unsigned long foo_0x4010(void) { return 0x4010UL; } ++ unsigned long foo_0x8010(void) { return 0x8010UL; } ++ unsigned long foo_0x10010(void) { return 0x10010UL; } ++ unsigned long foo_0x20010(void) { return 0x20010UL; } ++ unsigned long foo_0x40010(void) { return 0x40010UL; } ++ unsigned long foo_0x80010(void) { return 0x80010UL; } ++ unsigned long foo_0x100010(void) { return 0x100010UL; } ++ unsigned long foo_0x200010(void) { return 0x200010UL; } ++ unsigned long foo_0x400010(void) { return 0x400010UL; } ++ unsigned long foo_0x800010(void) { return 0x800010UL; } ++ unsigned long foo_0x1000010(void) { return 0x1000010UL; } ++ unsigned long foo_0x2000010(void) { return 0x2000010UL; } ++ unsigned long foo_0x4000010(void) { return 0x4000010UL; } ++ unsigned long foo_0x8000010(void) { return 0x8000010UL; } ++ unsigned long foo_0x10000010(void) { return 0x10000010UL; } ++ unsigned long foo_0x20000010(void) { return 0x20000010UL; } ++ unsigned long foo_0x40000010(void) { return 0x40000010UL; } ++ unsigned long foo_0x80000010(void) { return 0x80000010UL; } ++ unsigned long foo_0x100000010(void) { return 0x100000010UL; } ++ unsigned long foo_0x200000010(void) { return 0x200000010UL; } ++ unsigned long foo_0x400000010(void) { return 0x400000010UL; } ++ unsigned long foo_0x800000010(void) { return 0x800000010UL; } ++ unsigned long foo_0x1000000010(void) { return 0x1000000010UL; } ++ unsigned long foo_0x2000000010(void) { return 0x2000000010UL; } ++ unsigned long foo_0x4000000010(void) { return 0x4000000010UL; } ++ unsigned long foo_0x8000000010(void) { return 0x8000000010UL; } ++ unsigned long foo_0x10000000010(void) { return 0x10000000010UL; } ++ unsigned long foo_0x20000000010(void) { return 0x20000000010UL; } ++ unsigned long foo_0x40000000010(void) { return 0x40000000010UL; } ++ unsigned long foo_0x80000000010(void) { return 0x80000000010UL; } ++ unsigned long foo_0x100000000010(void) { return 0x100000000010UL; } ++ unsigned long foo_0x200000000010(void) { return 0x200000000010UL; } ++ unsigned long foo_0x400000000010(void) { return 0x400000000010UL; } ++ unsigned long foo_0x800000000010(void) { return 0x800000000010UL; } ++ unsigned long foo_0x1000000000010(void) { return 0x1000000000010UL; } ++ unsigned long foo_0x2000000000010(void) { return 0x2000000000010UL; } ++ unsigned long foo_0x4000000000010(void) { return 0x4000000000010UL; } ++ unsigned long foo_0x8000000000010(void) { return 0x8000000000010UL; } ++ unsigned long foo_0x10000000000010(void) { return 0x10000000000010UL; } ++ unsigned long foo_0x20000000000010(void) { return 0x20000000000010UL; } ++ unsigned long foo_0x40000000000010(void) { return 0x40000000000010UL; } ++ unsigned long foo_0x80000000000010(void) { return 0x80000000000010UL; } ++ unsigned long foo_0x100000000000010(void) { return 0x100000000000010UL; } ++ unsigned long foo_0x200000000000010(void) { return 0x200000000000010UL; } ++ unsigned long foo_0x400000000000010(void) { return 0x400000000000010UL; } ++ unsigned long foo_0x800000000000010(void) { return 0x800000000000010UL; } ++ unsigned long foo_0x1000000000000010(void) { return 0x1000000000000010UL; } ++ unsigned long foo_0x2000000000000010(void) { return 0x2000000000000010UL; } ++ unsigned long foo_0x4000000000000010(void) { return 0x4000000000000010UL; } ++ unsigned long foo_0x8000000000000010(void) { return 0x8000000000000010UL; } ++ unsigned long foo_0x60(void) { return 0x60UL; } ++ unsigned long foo_0xa0(void) { return 0xa0UL; } ++ unsigned long foo_0x120(void) { return 0x120UL; } ++ unsigned long foo_0x220(void) { return 0x220UL; } ++ unsigned long foo_0x420(void) { return 0x420UL; } ++ unsigned long foo_0x820(void) { return 0x820UL; } ++ unsigned long foo_0x1020(void) { return 0x1020UL; } ++ unsigned long foo_0x2020(void) { return 0x2020UL; } ++ unsigned long foo_0x4020(void) { return 0x4020UL; } ++ unsigned long foo_0x8020(void) { return 0x8020UL; } ++ unsigned long foo_0x10020(void) { return 0x10020UL; } ++ unsigned long foo_0x20020(void) { return 0x20020UL; } ++ unsigned long foo_0x40020(void) { return 0x40020UL; } ++ unsigned long foo_0x80020(void) { return 0x80020UL; } ++ unsigned long foo_0x100020(void) { return 0x100020UL; } ++ unsigned long foo_0x200020(void) { return 0x200020UL; } ++ unsigned long foo_0x400020(void) { return 0x400020UL; } ++ unsigned long foo_0x800020(void) { return 0x800020UL; } ++ unsigned long foo_0x1000020(void) { return 0x1000020UL; } ++ unsigned long foo_0x2000020(void) { return 0x2000020UL; } ++ unsigned long foo_0x4000020(void) { return 0x4000020UL; } ++ unsigned long foo_0x8000020(void) { return 0x8000020UL; } ++ unsigned long foo_0x10000020(void) { return 0x10000020UL; } ++ unsigned long foo_0x20000020(void) { return 0x20000020UL; } ++ unsigned long foo_0x40000020(void) { return 0x40000020UL; } ++ unsigned long foo_0x80000020(void) { return 0x80000020UL; } ++ unsigned long foo_0x100000020(void) { return 0x100000020UL; } ++ unsigned long foo_0x200000020(void) { return 0x200000020UL; } ++ unsigned long foo_0x400000020(void) { return 0x400000020UL; } ++ unsigned long foo_0x800000020(void) { return 0x800000020UL; } ++ unsigned long foo_0x1000000020(void) { return 0x1000000020UL; } ++ unsigned long foo_0x2000000020(void) { return 0x2000000020UL; } ++ unsigned long foo_0x4000000020(void) { return 0x4000000020UL; } ++ unsigned long foo_0x8000000020(void) { return 0x8000000020UL; } ++ unsigned long foo_0x10000000020(void) { return 0x10000000020UL; } ++ unsigned long foo_0x20000000020(void) { return 0x20000000020UL; } ++ unsigned long foo_0x40000000020(void) { return 0x40000000020UL; } ++ unsigned long foo_0x80000000020(void) { return 0x80000000020UL; } ++ unsigned long foo_0x100000000020(void) { return 0x100000000020UL; } ++ unsigned long foo_0x200000000020(void) { return 0x200000000020UL; } ++ unsigned long foo_0x400000000020(void) { return 0x400000000020UL; } ++ unsigned long foo_0x800000000020(void) { return 0x800000000020UL; } ++ unsigned long foo_0x1000000000020(void) { return 0x1000000000020UL; } ++ unsigned long foo_0x2000000000020(void) { return 0x2000000000020UL; } ++ unsigned long foo_0x4000000000020(void) { return 0x4000000000020UL; } ++ unsigned long foo_0x8000000000020(void) { return 0x8000000000020UL; } ++ unsigned long foo_0x10000000000020(void) { return 0x10000000000020UL; } ++ unsigned long foo_0x20000000000020(void) { return 0x20000000000020UL; } ++ unsigned long foo_0x40000000000020(void) { return 0x40000000000020UL; } ++ unsigned long foo_0x80000000000020(void) { return 0x80000000000020UL; } ++ unsigned long foo_0x100000000000020(void) { return 0x100000000000020UL; } ++ unsigned long foo_0x200000000000020(void) { return 0x200000000000020UL; } ++ unsigned long foo_0x400000000000020(void) { return 0x400000000000020UL; } ++ unsigned long foo_0x800000000000020(void) { return 0x800000000000020UL; } ++ unsigned long foo_0x1000000000000020(void) { return 0x1000000000000020UL; } ++ unsigned long foo_0x2000000000000020(void) { return 0x2000000000000020UL; } ++ unsigned long foo_0x4000000000000020(void) { return 0x4000000000000020UL; } ++ unsigned long foo_0x8000000000000020(void) { return 0x8000000000000020UL; } ++ unsigned long foo_0xc0(void) { return 0xc0UL; } ++ unsigned long foo_0x140(void) { return 0x140UL; } ++ unsigned long foo_0x240(void) { return 0x240UL; } ++ unsigned long foo_0x440(void) { return 0x440UL; } ++ unsigned long foo_0x840(void) { return 0x840UL; } ++ unsigned long foo_0x1040(void) { return 0x1040UL; } ++ unsigned long foo_0x2040(void) { return 0x2040UL; } ++ unsigned long foo_0x4040(void) { return 0x4040UL; } ++ unsigned long foo_0x8040(void) { return 0x8040UL; } ++ unsigned long foo_0x10040(void) { return 0x10040UL; } ++ unsigned long foo_0x20040(void) { return 0x20040UL; } ++ unsigned long foo_0x40040(void) { return 0x40040UL; } ++ unsigned long foo_0x80040(void) { return 0x80040UL; } ++ unsigned long foo_0x100040(void) { return 0x100040UL; } ++ unsigned long foo_0x200040(void) { return 0x200040UL; } ++ unsigned long foo_0x400040(void) { return 0x400040UL; } ++ unsigned long foo_0x800040(void) { return 0x800040UL; } ++ unsigned long foo_0x1000040(void) { return 0x1000040UL; } ++ unsigned long foo_0x2000040(void) { return 0x2000040UL; } ++ unsigned long foo_0x4000040(void) { return 0x4000040UL; } ++ unsigned long foo_0x8000040(void) { return 0x8000040UL; } ++ unsigned long foo_0x10000040(void) { return 0x10000040UL; } ++ unsigned long foo_0x20000040(void) { return 0x20000040UL; } ++ unsigned long foo_0x40000040(void) { return 0x40000040UL; } ++ unsigned long foo_0x80000040(void) { return 0x80000040UL; } ++ unsigned long foo_0x100000040(void) { return 0x100000040UL; } ++ unsigned long foo_0x200000040(void) { return 0x200000040UL; } ++ unsigned long foo_0x400000040(void) { return 0x400000040UL; } ++ unsigned long foo_0x800000040(void) { return 0x800000040UL; } ++ unsigned long foo_0x1000000040(void) { return 0x1000000040UL; } ++ unsigned long foo_0x2000000040(void) { return 0x2000000040UL; } ++ unsigned long foo_0x4000000040(void) { return 0x4000000040UL; } ++ unsigned long foo_0x8000000040(void) { return 0x8000000040UL; } ++ unsigned long foo_0x10000000040(void) { return 0x10000000040UL; } ++ unsigned long foo_0x20000000040(void) { return 0x20000000040UL; } ++ unsigned long foo_0x40000000040(void) { return 0x40000000040UL; } ++ unsigned long foo_0x80000000040(void) { return 0x80000000040UL; } ++ unsigned long foo_0x100000000040(void) { return 0x100000000040UL; } ++ unsigned long foo_0x200000000040(void) { return 0x200000000040UL; } ++ unsigned long foo_0x400000000040(void) { return 0x400000000040UL; } ++ unsigned long foo_0x800000000040(void) { return 0x800000000040UL; } ++ unsigned long foo_0x1000000000040(void) { return 0x1000000000040UL; } ++ unsigned long foo_0x2000000000040(void) { return 0x2000000000040UL; } ++ unsigned long foo_0x4000000000040(void) { return 0x4000000000040UL; } ++ unsigned long foo_0x8000000000040(void) { return 0x8000000000040UL; } ++ unsigned long foo_0x10000000000040(void) { return 0x10000000000040UL; } ++ unsigned long foo_0x20000000000040(void) { return 0x20000000000040UL; } ++ unsigned long foo_0x40000000000040(void) { return 0x40000000000040UL; } ++ unsigned long foo_0x80000000000040(void) { return 0x80000000000040UL; } ++ unsigned long foo_0x100000000000040(void) { return 0x100000000000040UL; } ++ unsigned long foo_0x200000000000040(void) { return 0x200000000000040UL; } ++ unsigned long foo_0x400000000000040(void) { return 0x400000000000040UL; } ++ unsigned long foo_0x800000000000040(void) { return 0x800000000000040UL; } ++ unsigned long foo_0x1000000000000040(void) { return 0x1000000000000040UL; } ++ unsigned long foo_0x2000000000000040(void) { return 0x2000000000000040UL; } ++ unsigned long foo_0x4000000000000040(void) { return 0x4000000000000040UL; } ++ unsigned long foo_0x8000000000000040(void) { return 0x8000000000000040UL; } ++ unsigned long foo_0x180(void) { return 0x180UL; } ++ unsigned long foo_0x280(void) { return 0x280UL; } ++ unsigned long foo_0x480(void) { return 0x480UL; } ++ unsigned long foo_0x880(void) { return 0x880UL; } ++ unsigned long foo_0x1080(void) { return 0x1080UL; } ++ unsigned long foo_0x2080(void) { return 0x2080UL; } ++ unsigned long foo_0x4080(void) { return 0x4080UL; } ++ unsigned long foo_0x8080(void) { return 0x8080UL; } ++ unsigned long foo_0x10080(void) { return 0x10080UL; } ++ unsigned long foo_0x20080(void) { return 0x20080UL; } ++ unsigned long foo_0x40080(void) { return 0x40080UL; } ++ unsigned long foo_0x80080(void) { return 0x80080UL; } ++ unsigned long foo_0x100080(void) { return 0x100080UL; } ++ unsigned long foo_0x200080(void) { return 0x200080UL; } ++ unsigned long foo_0x400080(void) { return 0x400080UL; } ++ unsigned long foo_0x800080(void) { return 0x800080UL; } ++ unsigned long foo_0x1000080(void) { return 0x1000080UL; } ++ unsigned long foo_0x2000080(void) { return 0x2000080UL; } ++ unsigned long foo_0x4000080(void) { return 0x4000080UL; } ++ unsigned long foo_0x8000080(void) { return 0x8000080UL; } ++ unsigned long foo_0x10000080(void) { return 0x10000080UL; } ++ unsigned long foo_0x20000080(void) { return 0x20000080UL; } ++ unsigned long foo_0x40000080(void) { return 0x40000080UL; } ++ unsigned long foo_0x80000080(void) { return 0x80000080UL; } ++ unsigned long foo_0x100000080(void) { return 0x100000080UL; } ++ unsigned long foo_0x200000080(void) { return 0x200000080UL; } ++ unsigned long foo_0x400000080(void) { return 0x400000080UL; } ++ unsigned long foo_0x800000080(void) { return 0x800000080UL; } ++ unsigned long foo_0x1000000080(void) { return 0x1000000080UL; } ++ unsigned long foo_0x2000000080(void) { return 0x2000000080UL; } ++ unsigned long foo_0x4000000080(void) { return 0x4000000080UL; } ++ unsigned long foo_0x8000000080(void) { return 0x8000000080UL; } ++ unsigned long foo_0x10000000080(void) { return 0x10000000080UL; } ++ unsigned long foo_0x20000000080(void) { return 0x20000000080UL; } ++ unsigned long foo_0x40000000080(void) { return 0x40000000080UL; } ++ unsigned long foo_0x80000000080(void) { return 0x80000000080UL; } ++ unsigned long foo_0x100000000080(void) { return 0x100000000080UL; } ++ unsigned long foo_0x200000000080(void) { return 0x200000000080UL; } ++ unsigned long foo_0x400000000080(void) { return 0x400000000080UL; } ++ unsigned long foo_0x800000000080(void) { return 0x800000000080UL; } ++ unsigned long foo_0x1000000000080(void) { return 0x1000000000080UL; } ++ unsigned long foo_0x2000000000080(void) { return 0x2000000000080UL; } ++ unsigned long foo_0x4000000000080(void) { return 0x4000000000080UL; } ++ unsigned long foo_0x8000000000080(void) { return 0x8000000000080UL; } ++ unsigned long foo_0x10000000000080(void) { return 0x10000000000080UL; } ++ unsigned long foo_0x20000000000080(void) { return 0x20000000000080UL; } ++ unsigned long foo_0x40000000000080(void) { return 0x40000000000080UL; } ++ unsigned long foo_0x80000000000080(void) { return 0x80000000000080UL; } ++ unsigned long foo_0x100000000000080(void) { return 0x100000000000080UL; } ++ unsigned long foo_0x200000000000080(void) { return 0x200000000000080UL; } ++ unsigned long foo_0x400000000000080(void) { return 0x400000000000080UL; } ++ unsigned long foo_0x800000000000080(void) { return 0x800000000000080UL; } ++ unsigned long foo_0x1000000000000080(void) { return 0x1000000000000080UL; } ++ unsigned long foo_0x2000000000000080(void) { return 0x2000000000000080UL; } ++ unsigned long foo_0x4000000000000080(void) { return 0x4000000000000080UL; } ++ unsigned long foo_0x8000000000000080(void) { return 0x8000000000000080UL; } ++ unsigned long foo_0x300(void) { return 0x300UL; } ++ unsigned long foo_0x500(void) { return 0x500UL; } ++ unsigned long foo_0x900(void) { return 0x900UL; } ++ unsigned long foo_0x1100(void) { return 0x1100UL; } ++ unsigned long foo_0x2100(void) { return 0x2100UL; } ++ unsigned long foo_0x4100(void) { return 0x4100UL; } ++ unsigned long foo_0x8100(void) { return 0x8100UL; } ++ unsigned long foo_0x10100(void) { return 0x10100UL; } ++ unsigned long foo_0x20100(void) { return 0x20100UL; } ++ unsigned long foo_0x40100(void) { return 0x40100UL; } ++ unsigned long foo_0x80100(void) { return 0x80100UL; } ++ unsigned long foo_0x100100(void) { return 0x100100UL; } ++ unsigned long foo_0x200100(void) { return 0x200100UL; } ++ unsigned long foo_0x400100(void) { return 0x400100UL; } ++ unsigned long foo_0x800100(void) { return 0x800100UL; } ++ unsigned long foo_0x1000100(void) { return 0x1000100UL; } ++ unsigned long foo_0x2000100(void) { return 0x2000100UL; } ++ unsigned long foo_0x4000100(void) { return 0x4000100UL; } ++ unsigned long foo_0x8000100(void) { return 0x8000100UL; } ++ unsigned long foo_0x10000100(void) { return 0x10000100UL; } ++ unsigned long foo_0x20000100(void) { return 0x20000100UL; } ++ unsigned long foo_0x40000100(void) { return 0x40000100UL; } ++ unsigned long foo_0x80000100(void) { return 0x80000100UL; } ++ unsigned long foo_0x100000100(void) { return 0x100000100UL; } ++ unsigned long foo_0x200000100(void) { return 0x200000100UL; } ++ unsigned long foo_0x400000100(void) { return 0x400000100UL; } ++ unsigned long foo_0x800000100(void) { return 0x800000100UL; } ++ unsigned long foo_0x1000000100(void) { return 0x1000000100UL; } ++ unsigned long foo_0x2000000100(void) { return 0x2000000100UL; } ++ unsigned long foo_0x4000000100(void) { return 0x4000000100UL; } ++ unsigned long foo_0x8000000100(void) { return 0x8000000100UL; } ++ unsigned long foo_0x10000000100(void) { return 0x10000000100UL; } ++ unsigned long foo_0x20000000100(void) { return 0x20000000100UL; } ++ unsigned long foo_0x40000000100(void) { return 0x40000000100UL; } ++ unsigned long foo_0x80000000100(void) { return 0x80000000100UL; } ++ unsigned long foo_0x100000000100(void) { return 0x100000000100UL; } ++ unsigned long foo_0x200000000100(void) { return 0x200000000100UL; } ++ unsigned long foo_0x400000000100(void) { return 0x400000000100UL; } ++ unsigned long foo_0x800000000100(void) { return 0x800000000100UL; } ++ unsigned long foo_0x1000000000100(void) { return 0x1000000000100UL; } ++ unsigned long foo_0x2000000000100(void) { return 0x2000000000100UL; } ++ unsigned long foo_0x4000000000100(void) { return 0x4000000000100UL; } ++ unsigned long foo_0x8000000000100(void) { return 0x8000000000100UL; } ++ unsigned long foo_0x10000000000100(void) { return 0x10000000000100UL; } ++ unsigned long foo_0x20000000000100(void) { return 0x20000000000100UL; } ++ unsigned long foo_0x40000000000100(void) { return 0x40000000000100UL; } ++ unsigned long foo_0x80000000000100(void) { return 0x80000000000100UL; } ++ unsigned long foo_0x100000000000100(void) { return 0x100000000000100UL; } ++ unsigned long foo_0x200000000000100(void) { return 0x200000000000100UL; } ++ unsigned long foo_0x400000000000100(void) { return 0x400000000000100UL; } ++ unsigned long foo_0x800000000000100(void) { return 0x800000000000100UL; } ++ unsigned long foo_0x1000000000000100(void) { return 0x1000000000000100UL; } ++ unsigned long foo_0x2000000000000100(void) { return 0x2000000000000100UL; } ++ unsigned long foo_0x4000000000000100(void) { return 0x4000000000000100UL; } ++ unsigned long foo_0x8000000000000100(void) { return 0x8000000000000100UL; } ++ unsigned long foo_0x600(void) { return 0x600UL; } ++ unsigned long foo_0xa00(void) { return 0xa00UL; } ++ unsigned long foo_0x1200(void) { return 0x1200UL; } ++ unsigned long foo_0x2200(void) { return 0x2200UL; } ++ unsigned long foo_0x4200(void) { return 0x4200UL; } ++ unsigned long foo_0x8200(void) { return 0x8200UL; } ++ unsigned long foo_0x10200(void) { return 0x10200UL; } ++ unsigned long foo_0x20200(void) { return 0x20200UL; } ++ unsigned long foo_0x40200(void) { return 0x40200UL; } ++ unsigned long foo_0x80200(void) { return 0x80200UL; } ++ unsigned long foo_0x100200(void) { return 0x100200UL; } ++ unsigned long foo_0x200200(void) { return 0x200200UL; } ++ unsigned long foo_0x400200(void) { return 0x400200UL; } ++ unsigned long foo_0x800200(void) { return 0x800200UL; } ++ unsigned long foo_0x1000200(void) { return 0x1000200UL; } ++ unsigned long foo_0x2000200(void) { return 0x2000200UL; } ++ unsigned long foo_0x4000200(void) { return 0x4000200UL; } ++ unsigned long foo_0x8000200(void) { return 0x8000200UL; } ++ unsigned long foo_0x10000200(void) { return 0x10000200UL; } ++ unsigned long foo_0x20000200(void) { return 0x20000200UL; } ++ unsigned long foo_0x40000200(void) { return 0x40000200UL; } ++ unsigned long foo_0x80000200(void) { return 0x80000200UL; } ++ unsigned long foo_0x100000200(void) { return 0x100000200UL; } ++ unsigned long foo_0x200000200(void) { return 0x200000200UL; } ++ unsigned long foo_0x400000200(void) { return 0x400000200UL; } ++ unsigned long foo_0x800000200(void) { return 0x800000200UL; } ++ unsigned long foo_0x1000000200(void) { return 0x1000000200UL; } ++ unsigned long foo_0x2000000200(void) { return 0x2000000200UL; } ++ unsigned long foo_0x4000000200(void) { return 0x4000000200UL; } ++ unsigned long foo_0x8000000200(void) { return 0x8000000200UL; } ++ unsigned long foo_0x10000000200(void) { return 0x10000000200UL; } ++ unsigned long foo_0x20000000200(void) { return 0x20000000200UL; } ++ unsigned long foo_0x40000000200(void) { return 0x40000000200UL; } ++ unsigned long foo_0x80000000200(void) { return 0x80000000200UL; } ++ unsigned long foo_0x100000000200(void) { return 0x100000000200UL; } ++ unsigned long foo_0x200000000200(void) { return 0x200000000200UL; } ++ unsigned long foo_0x400000000200(void) { return 0x400000000200UL; } ++ unsigned long foo_0x800000000200(void) { return 0x800000000200UL; } ++ unsigned long foo_0x1000000000200(void) { return 0x1000000000200UL; } ++ unsigned long foo_0x2000000000200(void) { return 0x2000000000200UL; } ++ unsigned long foo_0x4000000000200(void) { return 0x4000000000200UL; } ++ unsigned long foo_0x8000000000200(void) { return 0x8000000000200UL; } ++ unsigned long foo_0x10000000000200(void) { return 0x10000000000200UL; } ++ unsigned long foo_0x20000000000200(void) { return 0x20000000000200UL; } ++ unsigned long foo_0x40000000000200(void) { return 0x40000000000200UL; } ++ unsigned long foo_0x80000000000200(void) { return 0x80000000000200UL; } ++ unsigned long foo_0x100000000000200(void) { return 0x100000000000200UL; } ++ unsigned long foo_0x200000000000200(void) { return 0x200000000000200UL; } ++ unsigned long foo_0x400000000000200(void) { return 0x400000000000200UL; } ++ unsigned long foo_0x800000000000200(void) { return 0x800000000000200UL; } ++ unsigned long foo_0x1000000000000200(void) { return 0x1000000000000200UL; } ++ unsigned long foo_0x2000000000000200(void) { return 0x2000000000000200UL; } ++ unsigned long foo_0x4000000000000200(void) { return 0x4000000000000200UL; } ++ unsigned long foo_0x8000000000000200(void) { return 0x8000000000000200UL; } ++ unsigned long foo_0xc00(void) { return 0xc00UL; } ++ unsigned long foo_0x1400(void) { return 0x1400UL; } ++ unsigned long foo_0x2400(void) { return 0x2400UL; } ++ unsigned long foo_0x4400(void) { return 0x4400UL; } ++ unsigned long foo_0x8400(void) { return 0x8400UL; } ++ unsigned long foo_0x10400(void) { return 0x10400UL; } ++ unsigned long foo_0x20400(void) { return 0x20400UL; } ++ unsigned long foo_0x40400(void) { return 0x40400UL; } ++ unsigned long foo_0x80400(void) { return 0x80400UL; } ++ unsigned long foo_0x100400(void) { return 0x100400UL; } ++ unsigned long foo_0x200400(void) { return 0x200400UL; } ++ unsigned long foo_0x400400(void) { return 0x400400UL; } ++ unsigned long foo_0x800400(void) { return 0x800400UL; } ++ unsigned long foo_0x1000400(void) { return 0x1000400UL; } ++ unsigned long foo_0x2000400(void) { return 0x2000400UL; } ++ unsigned long foo_0x4000400(void) { return 0x4000400UL; } ++ unsigned long foo_0x8000400(void) { return 0x8000400UL; } ++ unsigned long foo_0x10000400(void) { return 0x10000400UL; } ++ unsigned long foo_0x20000400(void) { return 0x20000400UL; } ++ unsigned long foo_0x40000400(void) { return 0x40000400UL; } ++ unsigned long foo_0x80000400(void) { return 0x80000400UL; } ++ unsigned long foo_0x100000400(void) { return 0x100000400UL; } ++ unsigned long foo_0x200000400(void) { return 0x200000400UL; } ++ unsigned long foo_0x400000400(void) { return 0x400000400UL; } ++ unsigned long foo_0x800000400(void) { return 0x800000400UL; } ++ unsigned long foo_0x1000000400(void) { return 0x1000000400UL; } ++ unsigned long foo_0x2000000400(void) { return 0x2000000400UL; } ++ unsigned long foo_0x4000000400(void) { return 0x4000000400UL; } ++ unsigned long foo_0x8000000400(void) { return 0x8000000400UL; } ++ unsigned long foo_0x10000000400(void) { return 0x10000000400UL; } ++ unsigned long foo_0x20000000400(void) { return 0x20000000400UL; } ++ unsigned long foo_0x40000000400(void) { return 0x40000000400UL; } ++ unsigned long foo_0x80000000400(void) { return 0x80000000400UL; } ++ unsigned long foo_0x100000000400(void) { return 0x100000000400UL; } ++ unsigned long foo_0x200000000400(void) { return 0x200000000400UL; } ++ unsigned long foo_0x400000000400(void) { return 0x400000000400UL; } ++ unsigned long foo_0x800000000400(void) { return 0x800000000400UL; } ++ unsigned long foo_0x1000000000400(void) { return 0x1000000000400UL; } ++ unsigned long foo_0x2000000000400(void) { return 0x2000000000400UL; } ++ unsigned long foo_0x4000000000400(void) { return 0x4000000000400UL; } ++ unsigned long foo_0x8000000000400(void) { return 0x8000000000400UL; } ++ unsigned long foo_0x10000000000400(void) { return 0x10000000000400UL; } ++ unsigned long foo_0x20000000000400(void) { return 0x20000000000400UL; } ++ unsigned long foo_0x40000000000400(void) { return 0x40000000000400UL; } ++ unsigned long foo_0x80000000000400(void) { return 0x80000000000400UL; } ++ unsigned long foo_0x100000000000400(void) { return 0x100000000000400UL; } ++ unsigned long foo_0x200000000000400(void) { return 0x200000000000400UL; } ++ unsigned long foo_0x400000000000400(void) { return 0x400000000000400UL; } ++ unsigned long foo_0x800000000000400(void) { return 0x800000000000400UL; } ++ unsigned long foo_0x1000000000000400(void) { return 0x1000000000000400UL; } ++ unsigned long foo_0x2000000000000400(void) { return 0x2000000000000400UL; } ++ unsigned long foo_0x4000000000000400(void) { return 0x4000000000000400UL; } ++ unsigned long foo_0x8000000000000400(void) { return 0x8000000000000400UL; } ++ unsigned long foo_0x1800(void) { return 0x1800UL; } ++ unsigned long foo_0x2800(void) { return 0x2800UL; } ++ unsigned long foo_0x4800(void) { return 0x4800UL; } ++ unsigned long foo_0x8800(void) { return 0x8800UL; } ++ unsigned long foo_0x10800(void) { return 0x10800UL; } ++ unsigned long foo_0x20800(void) { return 0x20800UL; } ++ unsigned long foo_0x40800(void) { return 0x40800UL; } ++ unsigned long foo_0x80800(void) { return 0x80800UL; } ++ unsigned long foo_0x100800(void) { return 0x100800UL; } ++ unsigned long foo_0x200800(void) { return 0x200800UL; } ++ unsigned long foo_0x400800(void) { return 0x400800UL; } ++ unsigned long foo_0x800800(void) { return 0x800800UL; } ++ unsigned long foo_0x1000800(void) { return 0x1000800UL; } ++ unsigned long foo_0x2000800(void) { return 0x2000800UL; } ++ unsigned long foo_0x4000800(void) { return 0x4000800UL; } ++ unsigned long foo_0x8000800(void) { return 0x8000800UL; } ++ unsigned long foo_0x10000800(void) { return 0x10000800UL; } ++ unsigned long foo_0x20000800(void) { return 0x20000800UL; } ++ unsigned long foo_0x40000800(void) { return 0x40000800UL; } ++ unsigned long foo_0x80000800(void) { return 0x80000800UL; } ++ unsigned long foo_0x100000800(void) { return 0x100000800UL; } ++ unsigned long foo_0x200000800(void) { return 0x200000800UL; } ++ unsigned long foo_0x400000800(void) { return 0x400000800UL; } ++ unsigned long foo_0x800000800(void) { return 0x800000800UL; } ++ unsigned long foo_0x1000000800(void) { return 0x1000000800UL; } ++ unsigned long foo_0x2000000800(void) { return 0x2000000800UL; } ++ unsigned long foo_0x4000000800(void) { return 0x4000000800UL; } ++ unsigned long foo_0x8000000800(void) { return 0x8000000800UL; } ++ unsigned long foo_0x10000000800(void) { return 0x10000000800UL; } ++ unsigned long foo_0x20000000800(void) { return 0x20000000800UL; } ++ unsigned long foo_0x40000000800(void) { return 0x40000000800UL; } ++ unsigned long foo_0x80000000800(void) { return 0x80000000800UL; } ++ unsigned long foo_0x100000000800(void) { return 0x100000000800UL; } ++ unsigned long foo_0x200000000800(void) { return 0x200000000800UL; } ++ unsigned long foo_0x400000000800(void) { return 0x400000000800UL; } ++ unsigned long foo_0x800000000800(void) { return 0x800000000800UL; } ++ unsigned long foo_0x1000000000800(void) { return 0x1000000000800UL; } ++ unsigned long foo_0x2000000000800(void) { return 0x2000000000800UL; } ++ unsigned long foo_0x4000000000800(void) { return 0x4000000000800UL; } ++ unsigned long foo_0x8000000000800(void) { return 0x8000000000800UL; } ++ unsigned long foo_0x10000000000800(void) { return 0x10000000000800UL; } ++ unsigned long foo_0x20000000000800(void) { return 0x20000000000800UL; } ++ unsigned long foo_0x40000000000800(void) { return 0x40000000000800UL; } ++ unsigned long foo_0x80000000000800(void) { return 0x80000000000800UL; } ++ unsigned long foo_0x100000000000800(void) { return 0x100000000000800UL; } ++ unsigned long foo_0x200000000000800(void) { return 0x200000000000800UL; } ++ unsigned long foo_0x400000000000800(void) { return 0x400000000000800UL; } ++ unsigned long foo_0x800000000000800(void) { return 0x800000000000800UL; } ++ unsigned long foo_0x1000000000000800(void) { return 0x1000000000000800UL; } ++ unsigned long foo_0x2000000000000800(void) { return 0x2000000000000800UL; } ++ unsigned long foo_0x4000000000000800(void) { return 0x4000000000000800UL; } ++ unsigned long foo_0x8000000000000800(void) { return 0x8000000000000800UL; } ++ unsigned long foo_0x3000(void) { return 0x3000UL; } ++ unsigned long foo_0x5000(void) { return 0x5000UL; } ++ unsigned long foo_0x9000(void) { return 0x9000UL; } ++ unsigned long foo_0x11000(void) { return 0x11000UL; } ++ unsigned long foo_0x21000(void) { return 0x21000UL; } ++ unsigned long foo_0x41000(void) { return 0x41000UL; } ++ unsigned long foo_0x81000(void) { return 0x81000UL; } ++ unsigned long foo_0x101000(void) { return 0x101000UL; } ++ unsigned long foo_0x201000(void) { return 0x201000UL; } ++ unsigned long foo_0x401000(void) { return 0x401000UL; } ++ unsigned long foo_0x801000(void) { return 0x801000UL; } ++ unsigned long foo_0x1001000(void) { return 0x1001000UL; } ++ unsigned long foo_0x2001000(void) { return 0x2001000UL; } ++ unsigned long foo_0x4001000(void) { return 0x4001000UL; } ++ unsigned long foo_0x8001000(void) { return 0x8001000UL; } ++ unsigned long foo_0x10001000(void) { return 0x10001000UL; } ++ unsigned long foo_0x20001000(void) { return 0x20001000UL; } ++ unsigned long foo_0x40001000(void) { return 0x40001000UL; } ++ unsigned long foo_0x80001000(void) { return 0x80001000UL; } ++ unsigned long foo_0x100001000(void) { return 0x100001000UL; } ++ unsigned long foo_0x200001000(void) { return 0x200001000UL; } ++ unsigned long foo_0x400001000(void) { return 0x400001000UL; } ++ unsigned long foo_0x800001000(void) { return 0x800001000UL; } ++ unsigned long foo_0x1000001000(void) { return 0x1000001000UL; } ++ unsigned long foo_0x2000001000(void) { return 0x2000001000UL; } ++ unsigned long foo_0x4000001000(void) { return 0x4000001000UL; } ++ unsigned long foo_0x8000001000(void) { return 0x8000001000UL; } ++ unsigned long foo_0x10000001000(void) { return 0x10000001000UL; } ++ unsigned long foo_0x20000001000(void) { return 0x20000001000UL; } ++ unsigned long foo_0x40000001000(void) { return 0x40000001000UL; } ++ unsigned long foo_0x80000001000(void) { return 0x80000001000UL; } ++ unsigned long foo_0x100000001000(void) { return 0x100000001000UL; } ++ unsigned long foo_0x200000001000(void) { return 0x200000001000UL; } ++ unsigned long foo_0x400000001000(void) { return 0x400000001000UL; } ++ unsigned long foo_0x800000001000(void) { return 0x800000001000UL; } ++ unsigned long foo_0x1000000001000(void) { return 0x1000000001000UL; } ++ unsigned long foo_0x2000000001000(void) { return 0x2000000001000UL; } ++ unsigned long foo_0x4000000001000(void) { return 0x4000000001000UL; } ++ unsigned long foo_0x8000000001000(void) { return 0x8000000001000UL; } ++ unsigned long foo_0x10000000001000(void) { return 0x10000000001000UL; } ++ unsigned long foo_0x20000000001000(void) { return 0x20000000001000UL; } ++ unsigned long foo_0x40000000001000(void) { return 0x40000000001000UL; } ++ unsigned long foo_0x80000000001000(void) { return 0x80000000001000UL; } ++ unsigned long foo_0x100000000001000(void) { return 0x100000000001000UL; } ++ unsigned long foo_0x200000000001000(void) { return 0x200000000001000UL; } ++ unsigned long foo_0x400000000001000(void) { return 0x400000000001000UL; } ++ unsigned long foo_0x800000000001000(void) { return 0x800000000001000UL; } ++ unsigned long foo_0x1000000000001000(void) { return 0x1000000000001000UL; } ++ unsigned long foo_0x2000000000001000(void) { return 0x2000000000001000UL; } ++ unsigned long foo_0x4000000000001000(void) { return 0x4000000000001000UL; } ++ unsigned long foo_0x8000000000001000(void) { return 0x8000000000001000UL; } ++ unsigned long foo_0x6000(void) { return 0x6000UL; } ++ unsigned long foo_0xa000(void) { return 0xa000UL; } ++ unsigned long foo_0x12000(void) { return 0x12000UL; } ++ unsigned long foo_0x22000(void) { return 0x22000UL; } ++ unsigned long foo_0x42000(void) { return 0x42000UL; } ++ unsigned long foo_0x82000(void) { return 0x82000UL; } ++ unsigned long foo_0x102000(void) { return 0x102000UL; } ++ unsigned long foo_0x202000(void) { return 0x202000UL; } ++ unsigned long foo_0x402000(void) { return 0x402000UL; } ++ unsigned long foo_0x802000(void) { return 0x802000UL; } ++ unsigned long foo_0x1002000(void) { return 0x1002000UL; } ++ unsigned long foo_0x2002000(void) { return 0x2002000UL; } ++ unsigned long foo_0x4002000(void) { return 0x4002000UL; } ++ unsigned long foo_0x8002000(void) { return 0x8002000UL; } ++ unsigned long foo_0x10002000(void) { return 0x10002000UL; } ++ unsigned long foo_0x20002000(void) { return 0x20002000UL; } ++ unsigned long foo_0x40002000(void) { return 0x40002000UL; } ++ unsigned long foo_0x80002000(void) { return 0x80002000UL; } ++ unsigned long foo_0x100002000(void) { return 0x100002000UL; } ++ unsigned long foo_0x200002000(void) { return 0x200002000UL; } ++ unsigned long foo_0x400002000(void) { return 0x400002000UL; } ++ unsigned long foo_0x800002000(void) { return 0x800002000UL; } ++ unsigned long foo_0x1000002000(void) { return 0x1000002000UL; } ++ unsigned long foo_0x2000002000(void) { return 0x2000002000UL; } ++ unsigned long foo_0x4000002000(void) { return 0x4000002000UL; } ++ unsigned long foo_0x8000002000(void) { return 0x8000002000UL; } ++ unsigned long foo_0x10000002000(void) { return 0x10000002000UL; } ++ unsigned long foo_0x20000002000(void) { return 0x20000002000UL; } ++ unsigned long foo_0x40000002000(void) { return 0x40000002000UL; } ++ unsigned long foo_0x80000002000(void) { return 0x80000002000UL; } ++ unsigned long foo_0x100000002000(void) { return 0x100000002000UL; } ++ unsigned long foo_0x200000002000(void) { return 0x200000002000UL; } ++ unsigned long foo_0x400000002000(void) { return 0x400000002000UL; } ++ unsigned long foo_0x800000002000(void) { return 0x800000002000UL; } ++ unsigned long foo_0x1000000002000(void) { return 0x1000000002000UL; } ++ unsigned long foo_0x2000000002000(void) { return 0x2000000002000UL; } ++ unsigned long foo_0x4000000002000(void) { return 0x4000000002000UL; } ++ unsigned long foo_0x8000000002000(void) { return 0x8000000002000UL; } ++ unsigned long foo_0x10000000002000(void) { return 0x10000000002000UL; } ++ unsigned long foo_0x20000000002000(void) { return 0x20000000002000UL; } ++ unsigned long foo_0x40000000002000(void) { return 0x40000000002000UL; } ++ unsigned long foo_0x80000000002000(void) { return 0x80000000002000UL; } ++ unsigned long foo_0x100000000002000(void) { return 0x100000000002000UL; } ++ unsigned long foo_0x200000000002000(void) { return 0x200000000002000UL; } ++ unsigned long foo_0x400000000002000(void) { return 0x400000000002000UL; } ++ unsigned long foo_0x800000000002000(void) { return 0x800000000002000UL; } ++ unsigned long foo_0x1000000000002000(void) { return 0x1000000000002000UL; } ++ unsigned long foo_0x2000000000002000(void) { return 0x2000000000002000UL; } ++ unsigned long foo_0x4000000000002000(void) { return 0x4000000000002000UL; } ++ unsigned long foo_0x8000000000002000(void) { return 0x8000000000002000UL; } ++ unsigned long foo_0xc000(void) { return 0xc000UL; } ++ unsigned long foo_0x14000(void) { return 0x14000UL; } ++ unsigned long foo_0x24000(void) { return 0x24000UL; } ++ unsigned long foo_0x44000(void) { return 0x44000UL; } ++ unsigned long foo_0x84000(void) { return 0x84000UL; } ++ unsigned long foo_0x104000(void) { return 0x104000UL; } ++ unsigned long foo_0x204000(void) { return 0x204000UL; } ++ unsigned long foo_0x404000(void) { return 0x404000UL; } ++ unsigned long foo_0x804000(void) { return 0x804000UL; } ++ unsigned long foo_0x1004000(void) { return 0x1004000UL; } ++ unsigned long foo_0x2004000(void) { return 0x2004000UL; } ++ unsigned long foo_0x4004000(void) { return 0x4004000UL; } ++ unsigned long foo_0x8004000(void) { return 0x8004000UL; } ++ unsigned long foo_0x10004000(void) { return 0x10004000UL; } ++ unsigned long foo_0x20004000(void) { return 0x20004000UL; } ++ unsigned long foo_0x40004000(void) { return 0x40004000UL; } ++ unsigned long foo_0x80004000(void) { return 0x80004000UL; } ++ unsigned long foo_0x100004000(void) { return 0x100004000UL; } ++ unsigned long foo_0x200004000(void) { return 0x200004000UL; } ++ unsigned long foo_0x400004000(void) { return 0x400004000UL; } ++ unsigned long foo_0x800004000(void) { return 0x800004000UL; } ++ unsigned long foo_0x1000004000(void) { return 0x1000004000UL; } ++ unsigned long foo_0x2000004000(void) { return 0x2000004000UL; } ++ unsigned long foo_0x4000004000(void) { return 0x4000004000UL; } ++ unsigned long foo_0x8000004000(void) { return 0x8000004000UL; } ++ unsigned long foo_0x10000004000(void) { return 0x10000004000UL; } ++ unsigned long foo_0x20000004000(void) { return 0x20000004000UL; } ++ unsigned long foo_0x40000004000(void) { return 0x40000004000UL; } ++ unsigned long foo_0x80000004000(void) { return 0x80000004000UL; } ++ unsigned long foo_0x100000004000(void) { return 0x100000004000UL; } ++ unsigned long foo_0x200000004000(void) { return 0x200000004000UL; } ++ unsigned long foo_0x400000004000(void) { return 0x400000004000UL; } ++ unsigned long foo_0x800000004000(void) { return 0x800000004000UL; } ++ unsigned long foo_0x1000000004000(void) { return 0x1000000004000UL; } ++ unsigned long foo_0x2000000004000(void) { return 0x2000000004000UL; } ++ unsigned long foo_0x4000000004000(void) { return 0x4000000004000UL; } ++ unsigned long foo_0x8000000004000(void) { return 0x8000000004000UL; } ++ unsigned long foo_0x10000000004000(void) { return 0x10000000004000UL; } ++ unsigned long foo_0x20000000004000(void) { return 0x20000000004000UL; } ++ unsigned long foo_0x40000000004000(void) { return 0x40000000004000UL; } ++ unsigned long foo_0x80000000004000(void) { return 0x80000000004000UL; } ++ unsigned long foo_0x100000000004000(void) { return 0x100000000004000UL; } ++ unsigned long foo_0x200000000004000(void) { return 0x200000000004000UL; } ++ unsigned long foo_0x400000000004000(void) { return 0x400000000004000UL; } ++ unsigned long foo_0x800000000004000(void) { return 0x800000000004000UL; } ++ unsigned long foo_0x1000000000004000(void) { return 0x1000000000004000UL; } ++ unsigned long foo_0x2000000000004000(void) { return 0x2000000000004000UL; } ++ unsigned long foo_0x4000000000004000(void) { return 0x4000000000004000UL; } ++ unsigned long foo_0x8000000000004000(void) { return 0x8000000000004000UL; } ++ unsigned long foo_0x18000(void) { return 0x18000UL; } ++ unsigned long foo_0x28000(void) { return 0x28000UL; } ++ unsigned long foo_0x48000(void) { return 0x48000UL; } ++ unsigned long foo_0x88000(void) { return 0x88000UL; } ++ unsigned long foo_0x108000(void) { return 0x108000UL; } ++ unsigned long foo_0x208000(void) { return 0x208000UL; } ++ unsigned long foo_0x408000(void) { return 0x408000UL; } ++ unsigned long foo_0x808000(void) { return 0x808000UL; } ++ unsigned long foo_0x1008000(void) { return 0x1008000UL; } ++ unsigned long foo_0x2008000(void) { return 0x2008000UL; } ++ unsigned long foo_0x4008000(void) { return 0x4008000UL; } ++ unsigned long foo_0x8008000(void) { return 0x8008000UL; } ++ unsigned long foo_0x10008000(void) { return 0x10008000UL; } ++ unsigned long foo_0x20008000(void) { return 0x20008000UL; } ++ unsigned long foo_0x40008000(void) { return 0x40008000UL; } ++ unsigned long foo_0x80008000(void) { return 0x80008000UL; } ++ unsigned long foo_0x100008000(void) { return 0x100008000UL; } ++ unsigned long foo_0x200008000(void) { return 0x200008000UL; } ++ unsigned long foo_0x400008000(void) { return 0x400008000UL; } ++ unsigned long foo_0x800008000(void) { return 0x800008000UL; } ++ unsigned long foo_0x1000008000(void) { return 0x1000008000UL; } ++ unsigned long foo_0x2000008000(void) { return 0x2000008000UL; } ++ unsigned long foo_0x4000008000(void) { return 0x4000008000UL; } ++ unsigned long foo_0x8000008000(void) { return 0x8000008000UL; } ++ unsigned long foo_0x10000008000(void) { return 0x10000008000UL; } ++ unsigned long foo_0x20000008000(void) { return 0x20000008000UL; } ++ unsigned long foo_0x40000008000(void) { return 0x40000008000UL; } ++ unsigned long foo_0x80000008000(void) { return 0x80000008000UL; } ++ unsigned long foo_0x100000008000(void) { return 0x100000008000UL; } ++ unsigned long foo_0x200000008000(void) { return 0x200000008000UL; } ++ unsigned long foo_0x400000008000(void) { return 0x400000008000UL; } ++ unsigned long foo_0x800000008000(void) { return 0x800000008000UL; } ++ unsigned long foo_0x1000000008000(void) { return 0x1000000008000UL; } ++ unsigned long foo_0x2000000008000(void) { return 0x2000000008000UL; } ++ unsigned long foo_0x4000000008000(void) { return 0x4000000008000UL; } ++ unsigned long foo_0x8000000008000(void) { return 0x8000000008000UL; } ++ unsigned long foo_0x10000000008000(void) { return 0x10000000008000UL; } ++ unsigned long foo_0x20000000008000(void) { return 0x20000000008000UL; } ++ unsigned long foo_0x40000000008000(void) { return 0x40000000008000UL; } ++ unsigned long foo_0x80000000008000(void) { return 0x80000000008000UL; } ++ unsigned long foo_0x100000000008000(void) { return 0x100000000008000UL; } ++ unsigned long foo_0x200000000008000(void) { return 0x200000000008000UL; } ++ unsigned long foo_0x400000000008000(void) { return 0x400000000008000UL; } ++ unsigned long foo_0x800000000008000(void) { return 0x800000000008000UL; } ++ unsigned long foo_0x1000000000008000(void) { return 0x1000000000008000UL; } ++ unsigned long foo_0x2000000000008000(void) { return 0x2000000000008000UL; } ++ unsigned long foo_0x4000000000008000(void) { return 0x4000000000008000UL; } ++ unsigned long foo_0x8000000000008000(void) { return 0x8000000000008000UL; } ++ unsigned long foo_0x30000(void) { return 0x30000UL; } ++ unsigned long foo_0x50000(void) { return 0x50000UL; } ++ unsigned long foo_0x90000(void) { return 0x90000UL; } ++ unsigned long foo_0x110000(void) { return 0x110000UL; } ++ unsigned long foo_0x210000(void) { return 0x210000UL; } ++ unsigned long foo_0x410000(void) { return 0x410000UL; } ++ unsigned long foo_0x810000(void) { return 0x810000UL; } ++ unsigned long foo_0x1010000(void) { return 0x1010000UL; } ++ unsigned long foo_0x2010000(void) { return 0x2010000UL; } ++ unsigned long foo_0x4010000(void) { return 0x4010000UL; } ++ unsigned long foo_0x8010000(void) { return 0x8010000UL; } ++ unsigned long foo_0x10010000(void) { return 0x10010000UL; } ++ unsigned long foo_0x20010000(void) { return 0x20010000UL; } ++ unsigned long foo_0x40010000(void) { return 0x40010000UL; } ++ unsigned long foo_0x80010000(void) { return 0x80010000UL; } ++ unsigned long foo_0x100010000(void) { return 0x100010000UL; } ++ unsigned long foo_0x200010000(void) { return 0x200010000UL; } ++ unsigned long foo_0x400010000(void) { return 0x400010000UL; } ++ unsigned long foo_0x800010000(void) { return 0x800010000UL; } ++ unsigned long foo_0x1000010000(void) { return 0x1000010000UL; } ++ unsigned long foo_0x2000010000(void) { return 0x2000010000UL; } ++ unsigned long foo_0x4000010000(void) { return 0x4000010000UL; } ++ unsigned long foo_0x8000010000(void) { return 0x8000010000UL; } ++ unsigned long foo_0x10000010000(void) { return 0x10000010000UL; } ++ unsigned long foo_0x20000010000(void) { return 0x20000010000UL; } ++ unsigned long foo_0x40000010000(void) { return 0x40000010000UL; } ++ unsigned long foo_0x80000010000(void) { return 0x80000010000UL; } ++ unsigned long foo_0x100000010000(void) { return 0x100000010000UL; } ++ unsigned long foo_0x200000010000(void) { return 0x200000010000UL; } ++ unsigned long foo_0x400000010000(void) { return 0x400000010000UL; } ++ unsigned long foo_0x800000010000(void) { return 0x800000010000UL; } ++ unsigned long foo_0x1000000010000(void) { return 0x1000000010000UL; } ++ unsigned long foo_0x2000000010000(void) { return 0x2000000010000UL; } ++ unsigned long foo_0x4000000010000(void) { return 0x4000000010000UL; } ++ unsigned long foo_0x8000000010000(void) { return 0x8000000010000UL; } ++ unsigned long foo_0x10000000010000(void) { return 0x10000000010000UL; } ++ unsigned long foo_0x20000000010000(void) { return 0x20000000010000UL; } ++ unsigned long foo_0x40000000010000(void) { return 0x40000000010000UL; } ++ unsigned long foo_0x80000000010000(void) { return 0x80000000010000UL; } ++ unsigned long foo_0x100000000010000(void) { return 0x100000000010000UL; } ++ unsigned long foo_0x200000000010000(void) { return 0x200000000010000UL; } ++ unsigned long foo_0x400000000010000(void) { return 0x400000000010000UL; } ++ unsigned long foo_0x800000000010000(void) { return 0x800000000010000UL; } ++ unsigned long foo_0x1000000000010000(void) { return 0x1000000000010000UL; } ++ unsigned long foo_0x2000000000010000(void) { return 0x2000000000010000UL; } ++ unsigned long foo_0x4000000000010000(void) { return 0x4000000000010000UL; } ++ unsigned long foo_0x8000000000010000(void) { return 0x8000000000010000UL; } ++ unsigned long foo_0x60000(void) { return 0x60000UL; } ++ unsigned long foo_0xa0000(void) { return 0xa0000UL; } ++ unsigned long foo_0x120000(void) { return 0x120000UL; } ++ unsigned long foo_0x220000(void) { return 0x220000UL; } ++ unsigned long foo_0x420000(void) { return 0x420000UL; } ++ unsigned long foo_0x820000(void) { return 0x820000UL; } ++ unsigned long foo_0x1020000(void) { return 0x1020000UL; } ++ unsigned long foo_0x2020000(void) { return 0x2020000UL; } ++ unsigned long foo_0x4020000(void) { return 0x4020000UL; } ++ unsigned long foo_0x8020000(void) { return 0x8020000UL; } ++ unsigned long foo_0x10020000(void) { return 0x10020000UL; } ++ unsigned long foo_0x20020000(void) { return 0x20020000UL; } ++ unsigned long foo_0x40020000(void) { return 0x40020000UL; } ++ unsigned long foo_0x80020000(void) { return 0x80020000UL; } ++ unsigned long foo_0x100020000(void) { return 0x100020000UL; } ++ unsigned long foo_0x200020000(void) { return 0x200020000UL; } ++ unsigned long foo_0x400020000(void) { return 0x400020000UL; } ++ unsigned long foo_0x800020000(void) { return 0x800020000UL; } ++ unsigned long foo_0x1000020000(void) { return 0x1000020000UL; } ++ unsigned long foo_0x2000020000(void) { return 0x2000020000UL; } ++ unsigned long foo_0x4000020000(void) { return 0x4000020000UL; } ++ unsigned long foo_0x8000020000(void) { return 0x8000020000UL; } ++ unsigned long foo_0x10000020000(void) { return 0x10000020000UL; } ++ unsigned long foo_0x20000020000(void) { return 0x20000020000UL; } ++ unsigned long foo_0x40000020000(void) { return 0x40000020000UL; } ++ unsigned long foo_0x80000020000(void) { return 0x80000020000UL; } ++ unsigned long foo_0x100000020000(void) { return 0x100000020000UL; } ++ unsigned long foo_0x200000020000(void) { return 0x200000020000UL; } ++ unsigned long foo_0x400000020000(void) { return 0x400000020000UL; } ++ unsigned long foo_0x800000020000(void) { return 0x800000020000UL; } ++ unsigned long foo_0x1000000020000(void) { return 0x1000000020000UL; } ++ unsigned long foo_0x2000000020000(void) { return 0x2000000020000UL; } ++ unsigned long foo_0x4000000020000(void) { return 0x4000000020000UL; } ++ unsigned long foo_0x8000000020000(void) { return 0x8000000020000UL; } ++ unsigned long foo_0x10000000020000(void) { return 0x10000000020000UL; } ++ unsigned long foo_0x20000000020000(void) { return 0x20000000020000UL; } ++ unsigned long foo_0x40000000020000(void) { return 0x40000000020000UL; } ++ unsigned long foo_0x80000000020000(void) { return 0x80000000020000UL; } ++ unsigned long foo_0x100000000020000(void) { return 0x100000000020000UL; } ++ unsigned long foo_0x200000000020000(void) { return 0x200000000020000UL; } ++ unsigned long foo_0x400000000020000(void) { return 0x400000000020000UL; } ++ unsigned long foo_0x800000000020000(void) { return 0x800000000020000UL; } ++ unsigned long foo_0x1000000000020000(void) { return 0x1000000000020000UL; } ++ unsigned long foo_0x2000000000020000(void) { return 0x2000000000020000UL; } ++ unsigned long foo_0x4000000000020000(void) { return 0x4000000000020000UL; } ++ unsigned long foo_0x8000000000020000(void) { return 0x8000000000020000UL; } ++ unsigned long foo_0xc0000(void) { return 0xc0000UL; } ++ unsigned long foo_0x140000(void) { return 0x140000UL; } ++ unsigned long foo_0x240000(void) { return 0x240000UL; } ++ unsigned long foo_0x440000(void) { return 0x440000UL; } ++ unsigned long foo_0x840000(void) { return 0x840000UL; } ++ unsigned long foo_0x1040000(void) { return 0x1040000UL; } ++ unsigned long foo_0x2040000(void) { return 0x2040000UL; } ++ unsigned long foo_0x4040000(void) { return 0x4040000UL; } ++ unsigned long foo_0x8040000(void) { return 0x8040000UL; } ++ unsigned long foo_0x10040000(void) { return 0x10040000UL; } ++ unsigned long foo_0x20040000(void) { return 0x20040000UL; } ++ unsigned long foo_0x40040000(void) { return 0x40040000UL; } ++ unsigned long foo_0x80040000(void) { return 0x80040000UL; } ++ unsigned long foo_0x100040000(void) { return 0x100040000UL; } ++ unsigned long foo_0x200040000(void) { return 0x200040000UL; } ++ unsigned long foo_0x400040000(void) { return 0x400040000UL; } ++ unsigned long foo_0x800040000(void) { return 0x800040000UL; } ++ unsigned long foo_0x1000040000(void) { return 0x1000040000UL; } ++ unsigned long foo_0x2000040000(void) { return 0x2000040000UL; } ++ unsigned long foo_0x4000040000(void) { return 0x4000040000UL; } ++ unsigned long foo_0x8000040000(void) { return 0x8000040000UL; } ++ unsigned long foo_0x10000040000(void) { return 0x10000040000UL; } ++ unsigned long foo_0x20000040000(void) { return 0x20000040000UL; } ++ unsigned long foo_0x40000040000(void) { return 0x40000040000UL; } ++ unsigned long foo_0x80000040000(void) { return 0x80000040000UL; } ++ unsigned long foo_0x100000040000(void) { return 0x100000040000UL; } ++ unsigned long foo_0x200000040000(void) { return 0x200000040000UL; } ++ unsigned long foo_0x400000040000(void) { return 0x400000040000UL; } ++ unsigned long foo_0x800000040000(void) { return 0x800000040000UL; } ++ unsigned long foo_0x1000000040000(void) { return 0x1000000040000UL; } ++ unsigned long foo_0x2000000040000(void) { return 0x2000000040000UL; } ++ unsigned long foo_0x4000000040000(void) { return 0x4000000040000UL; } ++ unsigned long foo_0x8000000040000(void) { return 0x8000000040000UL; } ++ unsigned long foo_0x10000000040000(void) { return 0x10000000040000UL; } ++ unsigned long foo_0x20000000040000(void) { return 0x20000000040000UL; } ++ unsigned long foo_0x40000000040000(void) { return 0x40000000040000UL; } ++ unsigned long foo_0x80000000040000(void) { return 0x80000000040000UL; } ++ unsigned long foo_0x100000000040000(void) { return 0x100000000040000UL; } ++ unsigned long foo_0x200000000040000(void) { return 0x200000000040000UL; } ++ unsigned long foo_0x400000000040000(void) { return 0x400000000040000UL; } ++ unsigned long foo_0x800000000040000(void) { return 0x800000000040000UL; } ++ unsigned long foo_0x1000000000040000(void) { return 0x1000000000040000UL; } ++ unsigned long foo_0x2000000000040000(void) { return 0x2000000000040000UL; } ++ unsigned long foo_0x4000000000040000(void) { return 0x4000000000040000UL; } ++ unsigned long foo_0x8000000000040000(void) { return 0x8000000000040000UL; } ++ unsigned long foo_0x180000(void) { return 0x180000UL; } ++ unsigned long foo_0x280000(void) { return 0x280000UL; } ++ unsigned long foo_0x480000(void) { return 0x480000UL; } ++ unsigned long foo_0x880000(void) { return 0x880000UL; } ++ unsigned long foo_0x1080000(void) { return 0x1080000UL; } ++ unsigned long foo_0x2080000(void) { return 0x2080000UL; } ++ unsigned long foo_0x4080000(void) { return 0x4080000UL; } ++ unsigned long foo_0x8080000(void) { return 0x8080000UL; } ++ unsigned long foo_0x10080000(void) { return 0x10080000UL; } ++ unsigned long foo_0x20080000(void) { return 0x20080000UL; } ++ unsigned long foo_0x40080000(void) { return 0x40080000UL; } ++ unsigned long foo_0x80080000(void) { return 0x80080000UL; } ++ unsigned long foo_0x100080000(void) { return 0x100080000UL; } ++ unsigned long foo_0x200080000(void) { return 0x200080000UL; } ++ unsigned long foo_0x400080000(void) { return 0x400080000UL; } ++ unsigned long foo_0x800080000(void) { return 0x800080000UL; } ++ unsigned long foo_0x1000080000(void) { return 0x1000080000UL; } ++ unsigned long foo_0x2000080000(void) { return 0x2000080000UL; } ++ unsigned long foo_0x4000080000(void) { return 0x4000080000UL; } ++ unsigned long foo_0x8000080000(void) { return 0x8000080000UL; } ++ unsigned long foo_0x10000080000(void) { return 0x10000080000UL; } ++ unsigned long foo_0x20000080000(void) { return 0x20000080000UL; } ++ unsigned long foo_0x40000080000(void) { return 0x40000080000UL; } ++ unsigned long foo_0x80000080000(void) { return 0x80000080000UL; } ++ unsigned long foo_0x100000080000(void) { return 0x100000080000UL; } ++ unsigned long foo_0x200000080000(void) { return 0x200000080000UL; } ++ unsigned long foo_0x400000080000(void) { return 0x400000080000UL; } ++ unsigned long foo_0x800000080000(void) { return 0x800000080000UL; } ++ unsigned long foo_0x1000000080000(void) { return 0x1000000080000UL; } ++ unsigned long foo_0x2000000080000(void) { return 0x2000000080000UL; } ++ unsigned long foo_0x4000000080000(void) { return 0x4000000080000UL; } ++ unsigned long foo_0x8000000080000(void) { return 0x8000000080000UL; } ++ unsigned long foo_0x10000000080000(void) { return 0x10000000080000UL; } ++ unsigned long foo_0x20000000080000(void) { return 0x20000000080000UL; } ++ unsigned long foo_0x40000000080000(void) { return 0x40000000080000UL; } ++ unsigned long foo_0x80000000080000(void) { return 0x80000000080000UL; } ++ unsigned long foo_0x100000000080000(void) { return 0x100000000080000UL; } ++ unsigned long foo_0x200000000080000(void) { return 0x200000000080000UL; } ++ unsigned long foo_0x400000000080000(void) { return 0x400000000080000UL; } ++ unsigned long foo_0x800000000080000(void) { return 0x800000000080000UL; } ++ unsigned long foo_0x1000000000080000(void) { return 0x1000000000080000UL; } ++ unsigned long foo_0x2000000000080000(void) { return 0x2000000000080000UL; } ++ unsigned long foo_0x4000000000080000(void) { return 0x4000000000080000UL; } ++ unsigned long foo_0x8000000000080000(void) { return 0x8000000000080000UL; } ++ unsigned long foo_0x300000(void) { return 0x300000UL; } ++ unsigned long foo_0x500000(void) { return 0x500000UL; } ++ unsigned long foo_0x900000(void) { return 0x900000UL; } ++ unsigned long foo_0x1100000(void) { return 0x1100000UL; } ++ unsigned long foo_0x2100000(void) { return 0x2100000UL; } ++ unsigned long foo_0x4100000(void) { return 0x4100000UL; } ++ unsigned long foo_0x8100000(void) { return 0x8100000UL; } ++ unsigned long foo_0x10100000(void) { return 0x10100000UL; } ++ unsigned long foo_0x20100000(void) { return 0x20100000UL; } ++ unsigned long foo_0x40100000(void) { return 0x40100000UL; } ++ unsigned long foo_0x80100000(void) { return 0x80100000UL; } ++ unsigned long foo_0x100100000(void) { return 0x100100000UL; } ++ unsigned long foo_0x200100000(void) { return 0x200100000UL; } ++ unsigned long foo_0x400100000(void) { return 0x400100000UL; } ++ unsigned long foo_0x800100000(void) { return 0x800100000UL; } ++ unsigned long foo_0x1000100000(void) { return 0x1000100000UL; } ++ unsigned long foo_0x2000100000(void) { return 0x2000100000UL; } ++ unsigned long foo_0x4000100000(void) { return 0x4000100000UL; } ++ unsigned long foo_0x8000100000(void) { return 0x8000100000UL; } ++ unsigned long foo_0x10000100000(void) { return 0x10000100000UL; } ++ unsigned long foo_0x20000100000(void) { return 0x20000100000UL; } ++ unsigned long foo_0x40000100000(void) { return 0x40000100000UL; } ++ unsigned long foo_0x80000100000(void) { return 0x80000100000UL; } ++ unsigned long foo_0x100000100000(void) { return 0x100000100000UL; } ++ unsigned long foo_0x200000100000(void) { return 0x200000100000UL; } ++ unsigned long foo_0x400000100000(void) { return 0x400000100000UL; } ++ unsigned long foo_0x800000100000(void) { return 0x800000100000UL; } ++ unsigned long foo_0x1000000100000(void) { return 0x1000000100000UL; } ++ unsigned long foo_0x2000000100000(void) { return 0x2000000100000UL; } ++ unsigned long foo_0x4000000100000(void) { return 0x4000000100000UL; } ++ unsigned long foo_0x8000000100000(void) { return 0x8000000100000UL; } ++ unsigned long foo_0x10000000100000(void) { return 0x10000000100000UL; } ++ unsigned long foo_0x20000000100000(void) { return 0x20000000100000UL; } ++ unsigned long foo_0x40000000100000(void) { return 0x40000000100000UL; } ++ unsigned long foo_0x80000000100000(void) { return 0x80000000100000UL; } ++ unsigned long foo_0x100000000100000(void) { return 0x100000000100000UL; } ++ unsigned long foo_0x200000000100000(void) { return 0x200000000100000UL; } ++ unsigned long foo_0x400000000100000(void) { return 0x400000000100000UL; } ++ unsigned long foo_0x800000000100000(void) { return 0x800000000100000UL; } ++ unsigned long foo_0x1000000000100000(void) { return 0x1000000000100000UL; } ++ unsigned long foo_0x2000000000100000(void) { return 0x2000000000100000UL; } ++ unsigned long foo_0x4000000000100000(void) { return 0x4000000000100000UL; } ++ unsigned long foo_0x8000000000100000(void) { return 0x8000000000100000UL; } ++ unsigned long foo_0x600000(void) { return 0x600000UL; } ++ unsigned long foo_0xa00000(void) { return 0xa00000UL; } ++ unsigned long foo_0x1200000(void) { return 0x1200000UL; } ++ unsigned long foo_0x2200000(void) { return 0x2200000UL; } ++ unsigned long foo_0x4200000(void) { return 0x4200000UL; } ++ unsigned long foo_0x8200000(void) { return 0x8200000UL; } ++ unsigned long foo_0x10200000(void) { return 0x10200000UL; } ++ unsigned long foo_0x20200000(void) { return 0x20200000UL; } ++ unsigned long foo_0x40200000(void) { return 0x40200000UL; } ++ unsigned long foo_0x80200000(void) { return 0x80200000UL; } ++ unsigned long foo_0x100200000(void) { return 0x100200000UL; } ++ unsigned long foo_0x200200000(void) { return 0x200200000UL; } ++ unsigned long foo_0x400200000(void) { return 0x400200000UL; } ++ unsigned long foo_0x800200000(void) { return 0x800200000UL; } ++ unsigned long foo_0x1000200000(void) { return 0x1000200000UL; } ++ unsigned long foo_0x2000200000(void) { return 0x2000200000UL; } ++ unsigned long foo_0x4000200000(void) { return 0x4000200000UL; } ++ unsigned long foo_0x8000200000(void) { return 0x8000200000UL; } ++ unsigned long foo_0x10000200000(void) { return 0x10000200000UL; } ++ unsigned long foo_0x20000200000(void) { return 0x20000200000UL; } ++ unsigned long foo_0x40000200000(void) { return 0x40000200000UL; } ++ unsigned long foo_0x80000200000(void) { return 0x80000200000UL; } ++ unsigned long foo_0x100000200000(void) { return 0x100000200000UL; } ++ unsigned long foo_0x200000200000(void) { return 0x200000200000UL; } ++ unsigned long foo_0x400000200000(void) { return 0x400000200000UL; } ++ unsigned long foo_0x800000200000(void) { return 0x800000200000UL; } ++ unsigned long foo_0x1000000200000(void) { return 0x1000000200000UL; } ++ unsigned long foo_0x2000000200000(void) { return 0x2000000200000UL; } ++ unsigned long foo_0x4000000200000(void) { return 0x4000000200000UL; } ++ unsigned long foo_0x8000000200000(void) { return 0x8000000200000UL; } ++ unsigned long foo_0x10000000200000(void) { return 0x10000000200000UL; } ++ unsigned long foo_0x20000000200000(void) { return 0x20000000200000UL; } ++ unsigned long foo_0x40000000200000(void) { return 0x40000000200000UL; } ++ unsigned long foo_0x80000000200000(void) { return 0x80000000200000UL; } ++ unsigned long foo_0x100000000200000(void) { return 0x100000000200000UL; } ++ unsigned long foo_0x200000000200000(void) { return 0x200000000200000UL; } ++ unsigned long foo_0x400000000200000(void) { return 0x400000000200000UL; } ++ unsigned long foo_0x800000000200000(void) { return 0x800000000200000UL; } ++ unsigned long foo_0x1000000000200000(void) { return 0x1000000000200000UL; } ++ unsigned long foo_0x2000000000200000(void) { return 0x2000000000200000UL; } ++ unsigned long foo_0x4000000000200000(void) { return 0x4000000000200000UL; } ++ unsigned long foo_0x8000000000200000(void) { return 0x8000000000200000UL; } ++ unsigned long foo_0xc00000(void) { return 0xc00000UL; } ++ unsigned long foo_0x1400000(void) { return 0x1400000UL; } ++ unsigned long foo_0x2400000(void) { return 0x2400000UL; } ++ unsigned long foo_0x4400000(void) { return 0x4400000UL; } ++ unsigned long foo_0x8400000(void) { return 0x8400000UL; } ++ unsigned long foo_0x10400000(void) { return 0x10400000UL; } ++ unsigned long foo_0x20400000(void) { return 0x20400000UL; } ++ unsigned long foo_0x40400000(void) { return 0x40400000UL; } ++ unsigned long foo_0x80400000(void) { return 0x80400000UL; } ++ unsigned long foo_0x100400000(void) { return 0x100400000UL; } ++ unsigned long foo_0x200400000(void) { return 0x200400000UL; } ++ unsigned long foo_0x400400000(void) { return 0x400400000UL; } ++ unsigned long foo_0x800400000(void) { return 0x800400000UL; } ++ unsigned long foo_0x1000400000(void) { return 0x1000400000UL; } ++ unsigned long foo_0x2000400000(void) { return 0x2000400000UL; } ++ unsigned long foo_0x4000400000(void) { return 0x4000400000UL; } ++ unsigned long foo_0x8000400000(void) { return 0x8000400000UL; } ++ unsigned long foo_0x10000400000(void) { return 0x10000400000UL; } ++ unsigned long foo_0x20000400000(void) { return 0x20000400000UL; } ++ unsigned long foo_0x40000400000(void) { return 0x40000400000UL; } ++ unsigned long foo_0x80000400000(void) { return 0x80000400000UL; } ++ unsigned long foo_0x100000400000(void) { return 0x100000400000UL; } ++ unsigned long foo_0x200000400000(void) { return 0x200000400000UL; } ++ unsigned long foo_0x400000400000(void) { return 0x400000400000UL; } ++ unsigned long foo_0x800000400000(void) { return 0x800000400000UL; } ++ unsigned long foo_0x1000000400000(void) { return 0x1000000400000UL; } ++ unsigned long foo_0x2000000400000(void) { return 0x2000000400000UL; } ++ unsigned long foo_0x4000000400000(void) { return 0x4000000400000UL; } ++ unsigned long foo_0x8000000400000(void) { return 0x8000000400000UL; } ++ unsigned long foo_0x10000000400000(void) { return 0x10000000400000UL; } ++ unsigned long foo_0x20000000400000(void) { return 0x20000000400000UL; } ++ unsigned long foo_0x40000000400000(void) { return 0x40000000400000UL; } ++ unsigned long foo_0x80000000400000(void) { return 0x80000000400000UL; } ++ unsigned long foo_0x100000000400000(void) { return 0x100000000400000UL; } ++ unsigned long foo_0x200000000400000(void) { return 0x200000000400000UL; } ++ unsigned long foo_0x400000000400000(void) { return 0x400000000400000UL; } ++ unsigned long foo_0x800000000400000(void) { return 0x800000000400000UL; } ++ unsigned long foo_0x1000000000400000(void) { return 0x1000000000400000UL; } ++ unsigned long foo_0x2000000000400000(void) { return 0x2000000000400000UL; } ++ unsigned long foo_0x4000000000400000(void) { return 0x4000000000400000UL; } ++ unsigned long foo_0x8000000000400000(void) { return 0x8000000000400000UL; } ++ unsigned long foo_0x1800000(void) { return 0x1800000UL; } ++ unsigned long foo_0x2800000(void) { return 0x2800000UL; } ++ unsigned long foo_0x4800000(void) { return 0x4800000UL; } ++ unsigned long foo_0x8800000(void) { return 0x8800000UL; } ++ unsigned long foo_0x10800000(void) { return 0x10800000UL; } ++ unsigned long foo_0x20800000(void) { return 0x20800000UL; } ++ unsigned long foo_0x40800000(void) { return 0x40800000UL; } ++ unsigned long foo_0x80800000(void) { return 0x80800000UL; } ++ unsigned long foo_0x100800000(void) { return 0x100800000UL; } ++ unsigned long foo_0x200800000(void) { return 0x200800000UL; } ++ unsigned long foo_0x400800000(void) { return 0x400800000UL; } ++ unsigned long foo_0x800800000(void) { return 0x800800000UL; } ++ unsigned long foo_0x1000800000(void) { return 0x1000800000UL; } ++ unsigned long foo_0x2000800000(void) { return 0x2000800000UL; } ++ unsigned long foo_0x4000800000(void) { return 0x4000800000UL; } ++ unsigned long foo_0x8000800000(void) { return 0x8000800000UL; } ++ unsigned long foo_0x10000800000(void) { return 0x10000800000UL; } ++ unsigned long foo_0x20000800000(void) { return 0x20000800000UL; } ++ unsigned long foo_0x40000800000(void) { return 0x40000800000UL; } ++ unsigned long foo_0x80000800000(void) { return 0x80000800000UL; } ++ unsigned long foo_0x100000800000(void) { return 0x100000800000UL; } ++ unsigned long foo_0x200000800000(void) { return 0x200000800000UL; } ++ unsigned long foo_0x400000800000(void) { return 0x400000800000UL; } ++ unsigned long foo_0x800000800000(void) { return 0x800000800000UL; } ++ unsigned long foo_0x1000000800000(void) { return 0x1000000800000UL; } ++ unsigned long foo_0x2000000800000(void) { return 0x2000000800000UL; } ++ unsigned long foo_0x4000000800000(void) { return 0x4000000800000UL; } ++ unsigned long foo_0x8000000800000(void) { return 0x8000000800000UL; } ++ unsigned long foo_0x10000000800000(void) { return 0x10000000800000UL; } ++ unsigned long foo_0x20000000800000(void) { return 0x20000000800000UL; } ++ unsigned long foo_0x40000000800000(void) { return 0x40000000800000UL; } ++ unsigned long foo_0x80000000800000(void) { return 0x80000000800000UL; } ++ unsigned long foo_0x100000000800000(void) { return 0x100000000800000UL; } ++ unsigned long foo_0x200000000800000(void) { return 0x200000000800000UL; } ++ unsigned long foo_0x400000000800000(void) { return 0x400000000800000UL; } ++ unsigned long foo_0x800000000800000(void) { return 0x800000000800000UL; } ++ unsigned long foo_0x1000000000800000(void) { return 0x1000000000800000UL; } ++ unsigned long foo_0x2000000000800000(void) { return 0x2000000000800000UL; } ++ unsigned long foo_0x4000000000800000(void) { return 0x4000000000800000UL; } ++ unsigned long foo_0x8000000000800000(void) { return 0x8000000000800000UL; } ++ unsigned long foo_0x3000000(void) { return 0x3000000UL; } ++ unsigned long foo_0x5000000(void) { return 0x5000000UL; } ++ unsigned long foo_0x9000000(void) { return 0x9000000UL; } ++ unsigned long foo_0x11000000(void) { return 0x11000000UL; } ++ unsigned long foo_0x21000000(void) { return 0x21000000UL; } ++ unsigned long foo_0x41000000(void) { return 0x41000000UL; } ++ unsigned long foo_0x81000000(void) { return 0x81000000UL; } ++ unsigned long foo_0x101000000(void) { return 0x101000000UL; } ++ unsigned long foo_0x201000000(void) { return 0x201000000UL; } ++ unsigned long foo_0x401000000(void) { return 0x401000000UL; } ++ unsigned long foo_0x801000000(void) { return 0x801000000UL; } ++ unsigned long foo_0x1001000000(void) { return 0x1001000000UL; } ++ unsigned long foo_0x2001000000(void) { return 0x2001000000UL; } ++ unsigned long foo_0x4001000000(void) { return 0x4001000000UL; } ++ unsigned long foo_0x8001000000(void) { return 0x8001000000UL; } ++ unsigned long foo_0x10001000000(void) { return 0x10001000000UL; } ++ unsigned long foo_0x20001000000(void) { return 0x20001000000UL; } ++ unsigned long foo_0x40001000000(void) { return 0x40001000000UL; } ++ unsigned long foo_0x80001000000(void) { return 0x80001000000UL; } ++ unsigned long foo_0x100001000000(void) { return 0x100001000000UL; } ++ unsigned long foo_0x200001000000(void) { return 0x200001000000UL; } ++ unsigned long foo_0x400001000000(void) { return 0x400001000000UL; } ++ unsigned long foo_0x800001000000(void) { return 0x800001000000UL; } ++ unsigned long foo_0x1000001000000(void) { return 0x1000001000000UL; } ++ unsigned long foo_0x2000001000000(void) { return 0x2000001000000UL; } ++ unsigned long foo_0x4000001000000(void) { return 0x4000001000000UL; } ++ unsigned long foo_0x8000001000000(void) { return 0x8000001000000UL; } ++ unsigned long foo_0x10000001000000(void) { return 0x10000001000000UL; } ++ unsigned long foo_0x20000001000000(void) { return 0x20000001000000UL; } ++ unsigned long foo_0x40000001000000(void) { return 0x40000001000000UL; } ++ unsigned long foo_0x80000001000000(void) { return 0x80000001000000UL; } ++ unsigned long foo_0x100000001000000(void) { return 0x100000001000000UL; } ++ unsigned long foo_0x200000001000000(void) { return 0x200000001000000UL; } ++ unsigned long foo_0x400000001000000(void) { return 0x400000001000000UL; } ++ unsigned long foo_0x800000001000000(void) { return 0x800000001000000UL; } ++ unsigned long foo_0x1000000001000000(void) { return 0x1000000001000000UL; } ++ unsigned long foo_0x2000000001000000(void) { return 0x2000000001000000UL; } ++ unsigned long foo_0x4000000001000000(void) { return 0x4000000001000000UL; } ++ unsigned long foo_0x8000000001000000(void) { return 0x8000000001000000UL; } ++ unsigned long foo_0x6000000(void) { return 0x6000000UL; } ++ unsigned long foo_0xa000000(void) { return 0xa000000UL; } ++ unsigned long foo_0x12000000(void) { return 0x12000000UL; } ++ unsigned long foo_0x22000000(void) { return 0x22000000UL; } ++ unsigned long foo_0x42000000(void) { return 0x42000000UL; } ++ unsigned long foo_0x82000000(void) { return 0x82000000UL; } ++ unsigned long foo_0x102000000(void) { return 0x102000000UL; } ++ unsigned long foo_0x202000000(void) { return 0x202000000UL; } ++ unsigned long foo_0x402000000(void) { return 0x402000000UL; } ++ unsigned long foo_0x802000000(void) { return 0x802000000UL; } ++ unsigned long foo_0x1002000000(void) { return 0x1002000000UL; } ++ unsigned long foo_0x2002000000(void) { return 0x2002000000UL; } ++ unsigned long foo_0x4002000000(void) { return 0x4002000000UL; } ++ unsigned long foo_0x8002000000(void) { return 0x8002000000UL; } ++ unsigned long foo_0x10002000000(void) { return 0x10002000000UL; } ++ unsigned long foo_0x20002000000(void) { return 0x20002000000UL; } ++ unsigned long foo_0x40002000000(void) { return 0x40002000000UL; } ++ unsigned long foo_0x80002000000(void) { return 0x80002000000UL; } ++ unsigned long foo_0x100002000000(void) { return 0x100002000000UL; } ++ unsigned long foo_0x200002000000(void) { return 0x200002000000UL; } ++ unsigned long foo_0x400002000000(void) { return 0x400002000000UL; } ++ unsigned long foo_0x800002000000(void) { return 0x800002000000UL; } ++ unsigned long foo_0x1000002000000(void) { return 0x1000002000000UL; } ++ unsigned long foo_0x2000002000000(void) { return 0x2000002000000UL; } ++ unsigned long foo_0x4000002000000(void) { return 0x4000002000000UL; } ++ unsigned long foo_0x8000002000000(void) { return 0x8000002000000UL; } ++ unsigned long foo_0x10000002000000(void) { return 0x10000002000000UL; } ++ unsigned long foo_0x20000002000000(void) { return 0x20000002000000UL; } ++ unsigned long foo_0x40000002000000(void) { return 0x40000002000000UL; } ++ unsigned long foo_0x80000002000000(void) { return 0x80000002000000UL; } ++ unsigned long foo_0x100000002000000(void) { return 0x100000002000000UL; } ++ unsigned long foo_0x200000002000000(void) { return 0x200000002000000UL; } ++ unsigned long foo_0x400000002000000(void) { return 0x400000002000000UL; } ++ unsigned long foo_0x800000002000000(void) { return 0x800000002000000UL; } ++ unsigned long foo_0x1000000002000000(void) { return 0x1000000002000000UL; } ++ unsigned long foo_0x2000000002000000(void) { return 0x2000000002000000UL; } ++ unsigned long foo_0x4000000002000000(void) { return 0x4000000002000000UL; } ++ unsigned long foo_0x8000000002000000(void) { return 0x8000000002000000UL; } ++ unsigned long foo_0xc000000(void) { return 0xc000000UL; } ++ unsigned long foo_0x14000000(void) { return 0x14000000UL; } ++ unsigned long foo_0x24000000(void) { return 0x24000000UL; } ++ unsigned long foo_0x44000000(void) { return 0x44000000UL; } ++ unsigned long foo_0x84000000(void) { return 0x84000000UL; } ++ unsigned long foo_0x104000000(void) { return 0x104000000UL; } ++ unsigned long foo_0x204000000(void) { return 0x204000000UL; } ++ unsigned long foo_0x404000000(void) { return 0x404000000UL; } ++ unsigned long foo_0x804000000(void) { return 0x804000000UL; } ++ unsigned long foo_0x1004000000(void) { return 0x1004000000UL; } ++ unsigned long foo_0x2004000000(void) { return 0x2004000000UL; } ++ unsigned long foo_0x4004000000(void) { return 0x4004000000UL; } ++ unsigned long foo_0x8004000000(void) { return 0x8004000000UL; } ++ unsigned long foo_0x10004000000(void) { return 0x10004000000UL; } ++ unsigned long foo_0x20004000000(void) { return 0x20004000000UL; } ++ unsigned long foo_0x40004000000(void) { return 0x40004000000UL; } ++ unsigned long foo_0x80004000000(void) { return 0x80004000000UL; } ++ unsigned long foo_0x100004000000(void) { return 0x100004000000UL; } ++ unsigned long foo_0x200004000000(void) { return 0x200004000000UL; } ++ unsigned long foo_0x400004000000(void) { return 0x400004000000UL; } ++ unsigned long foo_0x800004000000(void) { return 0x800004000000UL; } ++ unsigned long foo_0x1000004000000(void) { return 0x1000004000000UL; } ++ unsigned long foo_0x2000004000000(void) { return 0x2000004000000UL; } ++ unsigned long foo_0x4000004000000(void) { return 0x4000004000000UL; } ++ unsigned long foo_0x8000004000000(void) { return 0x8000004000000UL; } ++ unsigned long foo_0x10000004000000(void) { return 0x10000004000000UL; } ++ unsigned long foo_0x20000004000000(void) { return 0x20000004000000UL; } ++ unsigned long foo_0x40000004000000(void) { return 0x40000004000000UL; } ++ unsigned long foo_0x80000004000000(void) { return 0x80000004000000UL; } ++ unsigned long foo_0x100000004000000(void) { return 0x100000004000000UL; } ++ unsigned long foo_0x200000004000000(void) { return 0x200000004000000UL; } ++ unsigned long foo_0x400000004000000(void) { return 0x400000004000000UL; } ++ unsigned long foo_0x800000004000000(void) { return 0x800000004000000UL; } ++ unsigned long foo_0x1000000004000000(void) { return 0x1000000004000000UL; } ++ unsigned long foo_0x2000000004000000(void) { return 0x2000000004000000UL; } ++ unsigned long foo_0x4000000004000000(void) { return 0x4000000004000000UL; } ++ unsigned long foo_0x8000000004000000(void) { return 0x8000000004000000UL; } ++ unsigned long foo_0x18000000(void) { return 0x18000000UL; } ++ unsigned long foo_0x28000000(void) { return 0x28000000UL; } ++ unsigned long foo_0x48000000(void) { return 0x48000000UL; } ++ unsigned long foo_0x88000000(void) { return 0x88000000UL; } ++ unsigned long foo_0x108000000(void) { return 0x108000000UL; } ++ unsigned long foo_0x208000000(void) { return 0x208000000UL; } ++ unsigned long foo_0x408000000(void) { return 0x408000000UL; } ++ unsigned long foo_0x808000000(void) { return 0x808000000UL; } ++ unsigned long foo_0x1008000000(void) { return 0x1008000000UL; } ++ unsigned long foo_0x2008000000(void) { return 0x2008000000UL; } ++ unsigned long foo_0x4008000000(void) { return 0x4008000000UL; } ++ unsigned long foo_0x8008000000(void) { return 0x8008000000UL; } ++ unsigned long foo_0x10008000000(void) { return 0x10008000000UL; } ++ unsigned long foo_0x20008000000(void) { return 0x20008000000UL; } ++ unsigned long foo_0x40008000000(void) { return 0x40008000000UL; } ++ unsigned long foo_0x80008000000(void) { return 0x80008000000UL; } ++ unsigned long foo_0x100008000000(void) { return 0x100008000000UL; } ++ unsigned long foo_0x200008000000(void) { return 0x200008000000UL; } ++ unsigned long foo_0x400008000000(void) { return 0x400008000000UL; } ++ unsigned long foo_0x800008000000(void) { return 0x800008000000UL; } ++ unsigned long foo_0x1000008000000(void) { return 0x1000008000000UL; } ++ unsigned long foo_0x2000008000000(void) { return 0x2000008000000UL; } ++ unsigned long foo_0x4000008000000(void) { return 0x4000008000000UL; } ++ unsigned long foo_0x8000008000000(void) { return 0x8000008000000UL; } ++ unsigned long foo_0x10000008000000(void) { return 0x10000008000000UL; } ++ unsigned long foo_0x20000008000000(void) { return 0x20000008000000UL; } ++ unsigned long foo_0x40000008000000(void) { return 0x40000008000000UL; } ++ unsigned long foo_0x80000008000000(void) { return 0x80000008000000UL; } ++ unsigned long foo_0x100000008000000(void) { return 0x100000008000000UL; } ++ unsigned long foo_0x200000008000000(void) { return 0x200000008000000UL; } ++ unsigned long foo_0x400000008000000(void) { return 0x400000008000000UL; } ++ unsigned long foo_0x800000008000000(void) { return 0x800000008000000UL; } ++ unsigned long foo_0x1000000008000000(void) { return 0x1000000008000000UL; } ++ unsigned long foo_0x2000000008000000(void) { return 0x2000000008000000UL; } ++ unsigned long foo_0x4000000008000000(void) { return 0x4000000008000000UL; } ++ unsigned long foo_0x8000000008000000(void) { return 0x8000000008000000UL; } ++ unsigned long foo_0x30000000(void) { return 0x30000000UL; } ++ unsigned long foo_0x50000000(void) { return 0x50000000UL; } ++ unsigned long foo_0x90000000(void) { return 0x90000000UL; } ++ unsigned long foo_0x110000000(void) { return 0x110000000UL; } ++ unsigned long foo_0x210000000(void) { return 0x210000000UL; } ++ unsigned long foo_0x410000000(void) { return 0x410000000UL; } ++ unsigned long foo_0x810000000(void) { return 0x810000000UL; } ++ unsigned long foo_0x1010000000(void) { return 0x1010000000UL; } ++ unsigned long foo_0x2010000000(void) { return 0x2010000000UL; } ++ unsigned long foo_0x4010000000(void) { return 0x4010000000UL; } ++ unsigned long foo_0x8010000000(void) { return 0x8010000000UL; } ++ unsigned long foo_0x10010000000(void) { return 0x10010000000UL; } ++ unsigned long foo_0x20010000000(void) { return 0x20010000000UL; } ++ unsigned long foo_0x40010000000(void) { return 0x40010000000UL; } ++ unsigned long foo_0x80010000000(void) { return 0x80010000000UL; } ++ unsigned long foo_0x100010000000(void) { return 0x100010000000UL; } ++ unsigned long foo_0x200010000000(void) { return 0x200010000000UL; } ++ unsigned long foo_0x400010000000(void) { return 0x400010000000UL; } ++ unsigned long foo_0x800010000000(void) { return 0x800010000000UL; } ++ unsigned long foo_0x1000010000000(void) { return 0x1000010000000UL; } ++ unsigned long foo_0x2000010000000(void) { return 0x2000010000000UL; } ++ unsigned long foo_0x4000010000000(void) { return 0x4000010000000UL; } ++ unsigned long foo_0x8000010000000(void) { return 0x8000010000000UL; } ++ unsigned long foo_0x10000010000000(void) { return 0x10000010000000UL; } ++ unsigned long foo_0x20000010000000(void) { return 0x20000010000000UL; } ++ unsigned long foo_0x40000010000000(void) { return 0x40000010000000UL; } ++ unsigned long foo_0x80000010000000(void) { return 0x80000010000000UL; } ++ unsigned long foo_0x100000010000000(void) { return 0x100000010000000UL; } ++ unsigned long foo_0x200000010000000(void) { return 0x200000010000000UL; } ++ unsigned long foo_0x400000010000000(void) { return 0x400000010000000UL; } ++ unsigned long foo_0x800000010000000(void) { return 0x800000010000000UL; } ++ unsigned long foo_0x1000000010000000(void) { return 0x1000000010000000UL; } ++ unsigned long foo_0x2000000010000000(void) { return 0x2000000010000000UL; } ++ unsigned long foo_0x4000000010000000(void) { return 0x4000000010000000UL; } ++ unsigned long foo_0x8000000010000000(void) { return 0x8000000010000000UL; } ++ unsigned long foo_0x60000000(void) { return 0x60000000UL; } ++ unsigned long foo_0xa0000000(void) { return 0xa0000000UL; } ++ unsigned long foo_0x120000000(void) { return 0x120000000UL; } ++ unsigned long foo_0x220000000(void) { return 0x220000000UL; } ++ unsigned long foo_0x420000000(void) { return 0x420000000UL; } ++ unsigned long foo_0x820000000(void) { return 0x820000000UL; } ++ unsigned long foo_0x1020000000(void) { return 0x1020000000UL; } ++ unsigned long foo_0x2020000000(void) { return 0x2020000000UL; } ++ unsigned long foo_0x4020000000(void) { return 0x4020000000UL; } ++ unsigned long foo_0x8020000000(void) { return 0x8020000000UL; } ++ unsigned long foo_0x10020000000(void) { return 0x10020000000UL; } ++ unsigned long foo_0x20020000000(void) { return 0x20020000000UL; } ++ unsigned long foo_0x40020000000(void) { return 0x40020000000UL; } ++ unsigned long foo_0x80020000000(void) { return 0x80020000000UL; } ++ unsigned long foo_0x100020000000(void) { return 0x100020000000UL; } ++ unsigned long foo_0x200020000000(void) { return 0x200020000000UL; } ++ unsigned long foo_0x400020000000(void) { return 0x400020000000UL; } ++ unsigned long foo_0x800020000000(void) { return 0x800020000000UL; } ++ unsigned long foo_0x1000020000000(void) { return 0x1000020000000UL; } ++ unsigned long foo_0x2000020000000(void) { return 0x2000020000000UL; } ++ unsigned long foo_0x4000020000000(void) { return 0x4000020000000UL; } ++ unsigned long foo_0x8000020000000(void) { return 0x8000020000000UL; } ++ unsigned long foo_0x10000020000000(void) { return 0x10000020000000UL; } ++ unsigned long foo_0x20000020000000(void) { return 0x20000020000000UL; } ++ unsigned long foo_0x40000020000000(void) { return 0x40000020000000UL; } ++ unsigned long foo_0x80000020000000(void) { return 0x80000020000000UL; } ++ unsigned long foo_0x100000020000000(void) { return 0x100000020000000UL; } ++ unsigned long foo_0x200000020000000(void) { return 0x200000020000000UL; } ++ unsigned long foo_0x400000020000000(void) { return 0x400000020000000UL; } ++ unsigned long foo_0x800000020000000(void) { return 0x800000020000000UL; } ++ unsigned long foo_0x1000000020000000(void) { return 0x1000000020000000UL; } ++ unsigned long foo_0x2000000020000000(void) { return 0x2000000020000000UL; } ++ unsigned long foo_0x4000000020000000(void) { return 0x4000000020000000UL; } ++ unsigned long foo_0x8000000020000000(void) { return 0x8000000020000000UL; } ++ unsigned long foo_0xc0000000(void) { return 0xc0000000UL; } ++ unsigned long foo_0x140000000(void) { return 0x140000000UL; } ++ unsigned long foo_0x240000000(void) { return 0x240000000UL; } ++ unsigned long foo_0x440000000(void) { return 0x440000000UL; } ++ unsigned long foo_0x840000000(void) { return 0x840000000UL; } ++ unsigned long foo_0x1040000000(void) { return 0x1040000000UL; } ++ unsigned long foo_0x2040000000(void) { return 0x2040000000UL; } ++ unsigned long foo_0x4040000000(void) { return 0x4040000000UL; } ++ unsigned long foo_0x8040000000(void) { return 0x8040000000UL; } ++ unsigned long foo_0x10040000000(void) { return 0x10040000000UL; } ++ unsigned long foo_0x20040000000(void) { return 0x20040000000UL; } ++ unsigned long foo_0x40040000000(void) { return 0x40040000000UL; } ++ unsigned long foo_0x80040000000(void) { return 0x80040000000UL; } ++ unsigned long foo_0x100040000000(void) { return 0x100040000000UL; } ++ unsigned long foo_0x200040000000(void) { return 0x200040000000UL; } ++ unsigned long foo_0x400040000000(void) { return 0x400040000000UL; } ++ unsigned long foo_0x800040000000(void) { return 0x800040000000UL; } ++ unsigned long foo_0x1000040000000(void) { return 0x1000040000000UL; } ++ unsigned long foo_0x2000040000000(void) { return 0x2000040000000UL; } ++ unsigned long foo_0x4000040000000(void) { return 0x4000040000000UL; } ++ unsigned long foo_0x8000040000000(void) { return 0x8000040000000UL; } ++ unsigned long foo_0x10000040000000(void) { return 0x10000040000000UL; } ++ unsigned long foo_0x20000040000000(void) { return 0x20000040000000UL; } ++ unsigned long foo_0x40000040000000(void) { return 0x40000040000000UL; } ++ unsigned long foo_0x80000040000000(void) { return 0x80000040000000UL; } ++ unsigned long foo_0x100000040000000(void) { return 0x100000040000000UL; } ++ unsigned long foo_0x200000040000000(void) { return 0x200000040000000UL; } ++ unsigned long foo_0x400000040000000(void) { return 0x400000040000000UL; } ++ unsigned long foo_0x800000040000000(void) { return 0x800000040000000UL; } ++ unsigned long foo_0x1000000040000000(void) { return 0x1000000040000000UL; } ++ unsigned long foo_0x2000000040000000(void) { return 0x2000000040000000UL; } ++ unsigned long foo_0x4000000040000000(void) { return 0x4000000040000000UL; } ++ unsigned long foo_0x8000000040000000(void) { return 0x8000000040000000UL; } ++ unsigned long foo_0x180000000(void) { return 0x180000000UL; } ++ unsigned long foo_0x280000000(void) { return 0x280000000UL; } ++ unsigned long foo_0x480000000(void) { return 0x480000000UL; } ++ unsigned long foo_0x880000000(void) { return 0x880000000UL; } ++ unsigned long foo_0x1080000000(void) { return 0x1080000000UL; } ++ unsigned long foo_0x2080000000(void) { return 0x2080000000UL; } ++ unsigned long foo_0x4080000000(void) { return 0x4080000000UL; } ++ unsigned long foo_0x8080000000(void) { return 0x8080000000UL; } ++ unsigned long foo_0x10080000000(void) { return 0x10080000000UL; } ++ unsigned long foo_0x20080000000(void) { return 0x20080000000UL; } ++ unsigned long foo_0x40080000000(void) { return 0x40080000000UL; } ++ unsigned long foo_0x80080000000(void) { return 0x80080000000UL; } ++ unsigned long foo_0x100080000000(void) { return 0x100080000000UL; } ++ unsigned long foo_0x200080000000(void) { return 0x200080000000UL; } ++ unsigned long foo_0x400080000000(void) { return 0x400080000000UL; } ++ unsigned long foo_0x800080000000(void) { return 0x800080000000UL; } ++ unsigned long foo_0x1000080000000(void) { return 0x1000080000000UL; } ++ unsigned long foo_0x2000080000000(void) { return 0x2000080000000UL; } ++ unsigned long foo_0x4000080000000(void) { return 0x4000080000000UL; } ++ unsigned long foo_0x8000080000000(void) { return 0x8000080000000UL; } ++ unsigned long foo_0x10000080000000(void) { return 0x10000080000000UL; } ++ unsigned long foo_0x20000080000000(void) { return 0x20000080000000UL; } ++ unsigned long foo_0x40000080000000(void) { return 0x40000080000000UL; } ++ unsigned long foo_0x80000080000000(void) { return 0x80000080000000UL; } ++ unsigned long foo_0x100000080000000(void) { return 0x100000080000000UL; } ++ unsigned long foo_0x200000080000000(void) { return 0x200000080000000UL; } ++ unsigned long foo_0x400000080000000(void) { return 0x400000080000000UL; } ++ unsigned long foo_0x800000080000000(void) { return 0x800000080000000UL; } ++ unsigned long foo_0x1000000080000000(void) { return 0x1000000080000000UL; } ++ unsigned long foo_0x2000000080000000(void) { return 0x2000000080000000UL; } ++ unsigned long foo_0x4000000080000000(void) { return 0x4000000080000000UL; } ++ unsigned long foo_0x8000000080000000(void) { return 0x8000000080000000UL; } ++ unsigned long foo_0x300000000(void) { return 0x300000000UL; } ++ unsigned long foo_0x500000000(void) { return 0x500000000UL; } ++ unsigned long foo_0x900000000(void) { return 0x900000000UL; } ++ unsigned long foo_0x1100000000(void) { return 0x1100000000UL; } ++ unsigned long foo_0x2100000000(void) { return 0x2100000000UL; } ++ unsigned long foo_0x4100000000(void) { return 0x4100000000UL; } ++ unsigned long foo_0x8100000000(void) { return 0x8100000000UL; } ++ unsigned long foo_0x10100000000(void) { return 0x10100000000UL; } ++ unsigned long foo_0x20100000000(void) { return 0x20100000000UL; } ++ unsigned long foo_0x40100000000(void) { return 0x40100000000UL; } ++ unsigned long foo_0x80100000000(void) { return 0x80100000000UL; } ++ unsigned long foo_0x100100000000(void) { return 0x100100000000UL; } ++ unsigned long foo_0x200100000000(void) { return 0x200100000000UL; } ++ unsigned long foo_0x400100000000(void) { return 0x400100000000UL; } ++ unsigned long foo_0x800100000000(void) { return 0x800100000000UL; } ++ unsigned long foo_0x1000100000000(void) { return 0x1000100000000UL; } ++ unsigned long foo_0x2000100000000(void) { return 0x2000100000000UL; } ++ unsigned long foo_0x4000100000000(void) { return 0x4000100000000UL; } ++ unsigned long foo_0x8000100000000(void) { return 0x8000100000000UL; } ++ unsigned long foo_0x10000100000000(void) { return 0x10000100000000UL; } ++ unsigned long foo_0x20000100000000(void) { return 0x20000100000000UL; } ++ unsigned long foo_0x40000100000000(void) { return 0x40000100000000UL; } ++ unsigned long foo_0x80000100000000(void) { return 0x80000100000000UL; } ++ unsigned long foo_0x100000100000000(void) { return 0x100000100000000UL; } ++ unsigned long foo_0x200000100000000(void) { return 0x200000100000000UL; } ++ unsigned long foo_0x400000100000000(void) { return 0x400000100000000UL; } ++ unsigned long foo_0x800000100000000(void) { return 0x800000100000000UL; } ++ unsigned long foo_0x1000000100000000(void) { return 0x1000000100000000UL; } ++ unsigned long foo_0x2000000100000000(void) { return 0x2000000100000000UL; } ++ unsigned long foo_0x4000000100000000(void) { return 0x4000000100000000UL; } ++ unsigned long foo_0x8000000100000000(void) { return 0x8000000100000000UL; } ++ unsigned long foo_0x600000000(void) { return 0x600000000UL; } ++ unsigned long foo_0xa00000000(void) { return 0xa00000000UL; } ++ unsigned long foo_0x1200000000(void) { return 0x1200000000UL; } ++ unsigned long foo_0x2200000000(void) { return 0x2200000000UL; } ++ unsigned long foo_0x4200000000(void) { return 0x4200000000UL; } ++ unsigned long foo_0x8200000000(void) { return 0x8200000000UL; } ++ unsigned long foo_0x10200000000(void) { return 0x10200000000UL; } ++ unsigned long foo_0x20200000000(void) { return 0x20200000000UL; } ++ unsigned long foo_0x40200000000(void) { return 0x40200000000UL; } ++ unsigned long foo_0x80200000000(void) { return 0x80200000000UL; } ++ unsigned long foo_0x100200000000(void) { return 0x100200000000UL; } ++ unsigned long foo_0x200200000000(void) { return 0x200200000000UL; } ++ unsigned long foo_0x400200000000(void) { return 0x400200000000UL; } ++ unsigned long foo_0x800200000000(void) { return 0x800200000000UL; } ++ unsigned long foo_0x1000200000000(void) { return 0x1000200000000UL; } ++ unsigned long foo_0x2000200000000(void) { return 0x2000200000000UL; } ++ unsigned long foo_0x4000200000000(void) { return 0x4000200000000UL; } ++ unsigned long foo_0x8000200000000(void) { return 0x8000200000000UL; } ++ unsigned long foo_0x10000200000000(void) { return 0x10000200000000UL; } ++ unsigned long foo_0x20000200000000(void) { return 0x20000200000000UL; } ++ unsigned long foo_0x40000200000000(void) { return 0x40000200000000UL; } ++ unsigned long foo_0x80000200000000(void) { return 0x80000200000000UL; } ++ unsigned long foo_0x100000200000000(void) { return 0x100000200000000UL; } ++ unsigned long foo_0x200000200000000(void) { return 0x200000200000000UL; } ++ unsigned long foo_0x400000200000000(void) { return 0x400000200000000UL; } ++ unsigned long foo_0x800000200000000(void) { return 0x800000200000000UL; } ++ unsigned long foo_0x1000000200000000(void) { return 0x1000000200000000UL; } ++ unsigned long foo_0x2000000200000000(void) { return 0x2000000200000000UL; } ++ unsigned long foo_0x4000000200000000(void) { return 0x4000000200000000UL; } ++ unsigned long foo_0x8000000200000000(void) { return 0x8000000200000000UL; } ++ unsigned long foo_0xc00000000(void) { return 0xc00000000UL; } ++ unsigned long foo_0x1400000000(void) { return 0x1400000000UL; } ++ unsigned long foo_0x2400000000(void) { return 0x2400000000UL; } ++ unsigned long foo_0x4400000000(void) { return 0x4400000000UL; } ++ unsigned long foo_0x8400000000(void) { return 0x8400000000UL; } ++ unsigned long foo_0x10400000000(void) { return 0x10400000000UL; } ++ unsigned long foo_0x20400000000(void) { return 0x20400000000UL; } ++ unsigned long foo_0x40400000000(void) { return 0x40400000000UL; } ++ unsigned long foo_0x80400000000(void) { return 0x80400000000UL; } ++ unsigned long foo_0x100400000000(void) { return 0x100400000000UL; } ++ unsigned long foo_0x200400000000(void) { return 0x200400000000UL; } ++ unsigned long foo_0x400400000000(void) { return 0x400400000000UL; } ++ unsigned long foo_0x800400000000(void) { return 0x800400000000UL; } ++ unsigned long foo_0x1000400000000(void) { return 0x1000400000000UL; } ++ unsigned long foo_0x2000400000000(void) { return 0x2000400000000UL; } ++ unsigned long foo_0x4000400000000(void) { return 0x4000400000000UL; } ++ unsigned long foo_0x8000400000000(void) { return 0x8000400000000UL; } ++ unsigned long foo_0x10000400000000(void) { return 0x10000400000000UL; } ++ unsigned long foo_0x20000400000000(void) { return 0x20000400000000UL; } ++ unsigned long foo_0x40000400000000(void) { return 0x40000400000000UL; } ++ unsigned long foo_0x80000400000000(void) { return 0x80000400000000UL; } ++ unsigned long foo_0x100000400000000(void) { return 0x100000400000000UL; } ++ unsigned long foo_0x200000400000000(void) { return 0x200000400000000UL; } ++ unsigned long foo_0x400000400000000(void) { return 0x400000400000000UL; } ++ unsigned long foo_0x800000400000000(void) { return 0x800000400000000UL; } ++ unsigned long foo_0x1000000400000000(void) { return 0x1000000400000000UL; } ++ unsigned long foo_0x2000000400000000(void) { return 0x2000000400000000UL; } ++ unsigned long foo_0x4000000400000000(void) { return 0x4000000400000000UL; } ++ unsigned long foo_0x8000000400000000(void) { return 0x8000000400000000UL; } ++ unsigned long foo_0x1800000000(void) { return 0x1800000000UL; } ++ unsigned long foo_0x2800000000(void) { return 0x2800000000UL; } ++ unsigned long foo_0x4800000000(void) { return 0x4800000000UL; } ++ unsigned long foo_0x8800000000(void) { return 0x8800000000UL; } ++ unsigned long foo_0x10800000000(void) { return 0x10800000000UL; } ++ unsigned long foo_0x20800000000(void) { return 0x20800000000UL; } ++ unsigned long foo_0x40800000000(void) { return 0x40800000000UL; } ++ unsigned long foo_0x80800000000(void) { return 0x80800000000UL; } ++ unsigned long foo_0x100800000000(void) { return 0x100800000000UL; } ++ unsigned long foo_0x200800000000(void) { return 0x200800000000UL; } ++ unsigned long foo_0x400800000000(void) { return 0x400800000000UL; } ++ unsigned long foo_0x800800000000(void) { return 0x800800000000UL; } ++ unsigned long foo_0x1000800000000(void) { return 0x1000800000000UL; } ++ unsigned long foo_0x2000800000000(void) { return 0x2000800000000UL; } ++ unsigned long foo_0x4000800000000(void) { return 0x4000800000000UL; } ++ unsigned long foo_0x8000800000000(void) { return 0x8000800000000UL; } ++ unsigned long foo_0x10000800000000(void) { return 0x10000800000000UL; } ++ unsigned long foo_0x20000800000000(void) { return 0x20000800000000UL; } ++ unsigned long foo_0x40000800000000(void) { return 0x40000800000000UL; } ++ unsigned long foo_0x80000800000000(void) { return 0x80000800000000UL; } ++ unsigned long foo_0x100000800000000(void) { return 0x100000800000000UL; } ++ unsigned long foo_0x200000800000000(void) { return 0x200000800000000UL; } ++ unsigned long foo_0x400000800000000(void) { return 0x400000800000000UL; } ++ unsigned long foo_0x800000800000000(void) { return 0x800000800000000UL; } ++ unsigned long foo_0x1000000800000000(void) { return 0x1000000800000000UL; } ++ unsigned long foo_0x2000000800000000(void) { return 0x2000000800000000UL; } ++ unsigned long foo_0x4000000800000000(void) { return 0x4000000800000000UL; } ++ unsigned long foo_0x8000000800000000(void) { return 0x8000000800000000UL; } ++ unsigned long foo_0x3000000000(void) { return 0x3000000000UL; } ++ unsigned long foo_0x5000000000(void) { return 0x5000000000UL; } ++ unsigned long foo_0x9000000000(void) { return 0x9000000000UL; } ++ unsigned long foo_0x11000000000(void) { return 0x11000000000UL; } ++ unsigned long foo_0x21000000000(void) { return 0x21000000000UL; } ++ unsigned long foo_0x41000000000(void) { return 0x41000000000UL; } ++ unsigned long foo_0x81000000000(void) { return 0x81000000000UL; } ++ unsigned long foo_0x101000000000(void) { return 0x101000000000UL; } ++ unsigned long foo_0x201000000000(void) { return 0x201000000000UL; } ++ unsigned long foo_0x401000000000(void) { return 0x401000000000UL; } ++ unsigned long foo_0x801000000000(void) { return 0x801000000000UL; } ++ unsigned long foo_0x1001000000000(void) { return 0x1001000000000UL; } ++ unsigned long foo_0x2001000000000(void) { return 0x2001000000000UL; } ++ unsigned long foo_0x4001000000000(void) { return 0x4001000000000UL; } ++ unsigned long foo_0x8001000000000(void) { return 0x8001000000000UL; } ++ unsigned long foo_0x10001000000000(void) { return 0x10001000000000UL; } ++ unsigned long foo_0x20001000000000(void) { return 0x20001000000000UL; } ++ unsigned long foo_0x40001000000000(void) { return 0x40001000000000UL; } ++ unsigned long foo_0x80001000000000(void) { return 0x80001000000000UL; } ++ unsigned long foo_0x100001000000000(void) { return 0x100001000000000UL; } ++ unsigned long foo_0x200001000000000(void) { return 0x200001000000000UL; } ++ unsigned long foo_0x400001000000000(void) { return 0x400001000000000UL; } ++ unsigned long foo_0x800001000000000(void) { return 0x800001000000000UL; } ++ unsigned long foo_0x1000001000000000(void) { return 0x1000001000000000UL; } ++ unsigned long foo_0x2000001000000000(void) { return 0x2000001000000000UL; } ++ unsigned long foo_0x4000001000000000(void) { return 0x4000001000000000UL; } ++ unsigned long foo_0x8000001000000000(void) { return 0x8000001000000000UL; } ++ unsigned long foo_0x6000000000(void) { return 0x6000000000UL; } ++ unsigned long foo_0xa000000000(void) { return 0xa000000000UL; } ++ unsigned long foo_0x12000000000(void) { return 0x12000000000UL; } ++ unsigned long foo_0x22000000000(void) { return 0x22000000000UL; } ++ unsigned long foo_0x42000000000(void) { return 0x42000000000UL; } ++ unsigned long foo_0x82000000000(void) { return 0x82000000000UL; } ++ unsigned long foo_0x102000000000(void) { return 0x102000000000UL; } ++ unsigned long foo_0x202000000000(void) { return 0x202000000000UL; } ++ unsigned long foo_0x402000000000(void) { return 0x402000000000UL; } ++ unsigned long foo_0x802000000000(void) { return 0x802000000000UL; } ++ unsigned long foo_0x1002000000000(void) { return 0x1002000000000UL; } ++ unsigned long foo_0x2002000000000(void) { return 0x2002000000000UL; } ++ unsigned long foo_0x4002000000000(void) { return 0x4002000000000UL; } ++ unsigned long foo_0x8002000000000(void) { return 0x8002000000000UL; } ++ unsigned long foo_0x10002000000000(void) { return 0x10002000000000UL; } ++ unsigned long foo_0x20002000000000(void) { return 0x20002000000000UL; } ++ unsigned long foo_0x40002000000000(void) { return 0x40002000000000UL; } ++ unsigned long foo_0x80002000000000(void) { return 0x80002000000000UL; } ++ unsigned long foo_0x100002000000000(void) { return 0x100002000000000UL; } ++ unsigned long foo_0x200002000000000(void) { return 0x200002000000000UL; } ++ unsigned long foo_0x400002000000000(void) { return 0x400002000000000UL; } ++ unsigned long foo_0x800002000000000(void) { return 0x800002000000000UL; } ++ unsigned long foo_0x1000002000000000(void) { return 0x1000002000000000UL; } ++ unsigned long foo_0x2000002000000000(void) { return 0x2000002000000000UL; } ++ unsigned long foo_0x4000002000000000(void) { return 0x4000002000000000UL; } ++ unsigned long foo_0x8000002000000000(void) { return 0x8000002000000000UL; } ++ unsigned long foo_0xc000000000(void) { return 0xc000000000UL; } ++ unsigned long foo_0x14000000000(void) { return 0x14000000000UL; } ++ unsigned long foo_0x24000000000(void) { return 0x24000000000UL; } ++ unsigned long foo_0x44000000000(void) { return 0x44000000000UL; } ++ unsigned long foo_0x84000000000(void) { return 0x84000000000UL; } ++ unsigned long foo_0x104000000000(void) { return 0x104000000000UL; } ++ unsigned long foo_0x204000000000(void) { return 0x204000000000UL; } ++ unsigned long foo_0x404000000000(void) { return 0x404000000000UL; } ++ unsigned long foo_0x804000000000(void) { return 0x804000000000UL; } ++ unsigned long foo_0x1004000000000(void) { return 0x1004000000000UL; } ++ unsigned long foo_0x2004000000000(void) { return 0x2004000000000UL; } ++ unsigned long foo_0x4004000000000(void) { return 0x4004000000000UL; } ++ unsigned long foo_0x8004000000000(void) { return 0x8004000000000UL; } ++ unsigned long foo_0x10004000000000(void) { return 0x10004000000000UL; } ++ unsigned long foo_0x20004000000000(void) { return 0x20004000000000UL; } ++ unsigned long foo_0x40004000000000(void) { return 0x40004000000000UL; } ++ unsigned long foo_0x80004000000000(void) { return 0x80004000000000UL; } ++ unsigned long foo_0x100004000000000(void) { return 0x100004000000000UL; } ++ unsigned long foo_0x200004000000000(void) { return 0x200004000000000UL; } ++ unsigned long foo_0x400004000000000(void) { return 0x400004000000000UL; } ++ unsigned long foo_0x800004000000000(void) { return 0x800004000000000UL; } ++ unsigned long foo_0x1000004000000000(void) { return 0x1000004000000000UL; } ++ unsigned long foo_0x2000004000000000(void) { return 0x2000004000000000UL; } ++ unsigned long foo_0x4000004000000000(void) { return 0x4000004000000000UL; } ++ unsigned long foo_0x8000004000000000(void) { return 0x8000004000000000UL; } ++ unsigned long foo_0x18000000000(void) { return 0x18000000000UL; } ++ unsigned long foo_0x28000000000(void) { return 0x28000000000UL; } ++ unsigned long foo_0x48000000000(void) { return 0x48000000000UL; } ++ unsigned long foo_0x88000000000(void) { return 0x88000000000UL; } ++ unsigned long foo_0x108000000000(void) { return 0x108000000000UL; } ++ unsigned long foo_0x208000000000(void) { return 0x208000000000UL; } ++ unsigned long foo_0x408000000000(void) { return 0x408000000000UL; } ++ unsigned long foo_0x808000000000(void) { return 0x808000000000UL; } ++ unsigned long foo_0x1008000000000(void) { return 0x1008000000000UL; } ++ unsigned long foo_0x2008000000000(void) { return 0x2008000000000UL; } ++ unsigned long foo_0x4008000000000(void) { return 0x4008000000000UL; } ++ unsigned long foo_0x8008000000000(void) { return 0x8008000000000UL; } ++ unsigned long foo_0x10008000000000(void) { return 0x10008000000000UL; } ++ unsigned long foo_0x20008000000000(void) { return 0x20008000000000UL; } ++ unsigned long foo_0x40008000000000(void) { return 0x40008000000000UL; } ++ unsigned long foo_0x80008000000000(void) { return 0x80008000000000UL; } ++ unsigned long foo_0x100008000000000(void) { return 0x100008000000000UL; } ++ unsigned long foo_0x200008000000000(void) { return 0x200008000000000UL; } ++ unsigned long foo_0x400008000000000(void) { return 0x400008000000000UL; } ++ unsigned long foo_0x800008000000000(void) { return 0x800008000000000UL; } ++ unsigned long foo_0x1000008000000000(void) { return 0x1000008000000000UL; } ++ unsigned long foo_0x2000008000000000(void) { return 0x2000008000000000UL; } ++ unsigned long foo_0x4000008000000000(void) { return 0x4000008000000000UL; } ++ unsigned long foo_0x8000008000000000(void) { return 0x8000008000000000UL; } ++ unsigned long foo_0x30000000000(void) { return 0x30000000000UL; } ++ unsigned long foo_0x50000000000(void) { return 0x50000000000UL; } ++ unsigned long foo_0x90000000000(void) { return 0x90000000000UL; } ++ unsigned long foo_0x110000000000(void) { return 0x110000000000UL; } ++ unsigned long foo_0x210000000000(void) { return 0x210000000000UL; } ++ unsigned long foo_0x410000000000(void) { return 0x410000000000UL; } ++ unsigned long foo_0x810000000000(void) { return 0x810000000000UL; } ++ unsigned long foo_0x1010000000000(void) { return 0x1010000000000UL; } ++ unsigned long foo_0x2010000000000(void) { return 0x2010000000000UL; } ++ unsigned long foo_0x4010000000000(void) { return 0x4010000000000UL; } ++ unsigned long foo_0x8010000000000(void) { return 0x8010000000000UL; } ++ unsigned long foo_0x10010000000000(void) { return 0x10010000000000UL; } ++ unsigned long foo_0x20010000000000(void) { return 0x20010000000000UL; } ++ unsigned long foo_0x40010000000000(void) { return 0x40010000000000UL; } ++ unsigned long foo_0x80010000000000(void) { return 0x80010000000000UL; } ++ unsigned long foo_0x100010000000000(void) { return 0x100010000000000UL; } ++ unsigned long foo_0x200010000000000(void) { return 0x200010000000000UL; } ++ unsigned long foo_0x400010000000000(void) { return 0x400010000000000UL; } ++ unsigned long foo_0x800010000000000(void) { return 0x800010000000000UL; } ++ unsigned long foo_0x1000010000000000(void) { return 0x1000010000000000UL; } ++ unsigned long foo_0x2000010000000000(void) { return 0x2000010000000000UL; } ++ unsigned long foo_0x4000010000000000(void) { return 0x4000010000000000UL; } ++ unsigned long foo_0x8000010000000000(void) { return 0x8000010000000000UL; } ++ unsigned long foo_0x60000000000(void) { return 0x60000000000UL; } ++ unsigned long foo_0xa0000000000(void) { return 0xa0000000000UL; } ++ unsigned long foo_0x120000000000(void) { return 0x120000000000UL; } ++ unsigned long foo_0x220000000000(void) { return 0x220000000000UL; } ++ unsigned long foo_0x420000000000(void) { return 0x420000000000UL; } ++ unsigned long foo_0x820000000000(void) { return 0x820000000000UL; } ++ unsigned long foo_0x1020000000000(void) { return 0x1020000000000UL; } ++ unsigned long foo_0x2020000000000(void) { return 0x2020000000000UL; } ++ unsigned long foo_0x4020000000000(void) { return 0x4020000000000UL; } ++ unsigned long foo_0x8020000000000(void) { return 0x8020000000000UL; } ++ unsigned long foo_0x10020000000000(void) { return 0x10020000000000UL; } ++ unsigned long foo_0x20020000000000(void) { return 0x20020000000000UL; } ++ unsigned long foo_0x40020000000000(void) { return 0x40020000000000UL; } ++ unsigned long foo_0x80020000000000(void) { return 0x80020000000000UL; } ++ unsigned long foo_0x100020000000000(void) { return 0x100020000000000UL; } ++ unsigned long foo_0x200020000000000(void) { return 0x200020000000000UL; } ++ unsigned long foo_0x400020000000000(void) { return 0x400020000000000UL; } ++ unsigned long foo_0x800020000000000(void) { return 0x800020000000000UL; } ++ unsigned long foo_0x1000020000000000(void) { return 0x1000020000000000UL; } ++ unsigned long foo_0x2000020000000000(void) { return 0x2000020000000000UL; } ++ unsigned long foo_0x4000020000000000(void) { return 0x4000020000000000UL; } ++ unsigned long foo_0x8000020000000000(void) { return 0x8000020000000000UL; } ++ unsigned long foo_0xc0000000000(void) { return 0xc0000000000UL; } ++ unsigned long foo_0x140000000000(void) { return 0x140000000000UL; } ++ unsigned long foo_0x240000000000(void) { return 0x240000000000UL; } ++ unsigned long foo_0x440000000000(void) { return 0x440000000000UL; } ++ unsigned long foo_0x840000000000(void) { return 0x840000000000UL; } ++ unsigned long foo_0x1040000000000(void) { return 0x1040000000000UL; } ++ unsigned long foo_0x2040000000000(void) { return 0x2040000000000UL; } ++ unsigned long foo_0x4040000000000(void) { return 0x4040000000000UL; } ++ unsigned long foo_0x8040000000000(void) { return 0x8040000000000UL; } ++ unsigned long foo_0x10040000000000(void) { return 0x10040000000000UL; } ++ unsigned long foo_0x20040000000000(void) { return 0x20040000000000UL; } ++ unsigned long foo_0x40040000000000(void) { return 0x40040000000000UL; } ++ unsigned long foo_0x80040000000000(void) { return 0x80040000000000UL; } ++ unsigned long foo_0x100040000000000(void) { return 0x100040000000000UL; } ++ unsigned long foo_0x200040000000000(void) { return 0x200040000000000UL; } ++ unsigned long foo_0x400040000000000(void) { return 0x400040000000000UL; } ++ unsigned long foo_0x800040000000000(void) { return 0x800040000000000UL; } ++ unsigned long foo_0x1000040000000000(void) { return 0x1000040000000000UL; } ++ unsigned long foo_0x2000040000000000(void) { return 0x2000040000000000UL; } ++ unsigned long foo_0x4000040000000000(void) { return 0x4000040000000000UL; } ++ unsigned long foo_0x8000040000000000(void) { return 0x8000040000000000UL; } ++ unsigned long foo_0x180000000000(void) { return 0x180000000000UL; } ++ unsigned long foo_0x280000000000(void) { return 0x280000000000UL; } ++ unsigned long foo_0x480000000000(void) { return 0x480000000000UL; } ++ unsigned long foo_0x880000000000(void) { return 0x880000000000UL; } ++ unsigned long foo_0x1080000000000(void) { return 0x1080000000000UL; } ++ unsigned long foo_0x2080000000000(void) { return 0x2080000000000UL; } ++ unsigned long foo_0x4080000000000(void) { return 0x4080000000000UL; } ++ unsigned long foo_0x8080000000000(void) { return 0x8080000000000UL; } ++ unsigned long foo_0x10080000000000(void) { return 0x10080000000000UL; } ++ unsigned long foo_0x20080000000000(void) { return 0x20080000000000UL; } ++ unsigned long foo_0x40080000000000(void) { return 0x40080000000000UL; } ++ unsigned long foo_0x80080000000000(void) { return 0x80080000000000UL; } ++ unsigned long foo_0x100080000000000(void) { return 0x100080000000000UL; } ++ unsigned long foo_0x200080000000000(void) { return 0x200080000000000UL; } ++ unsigned long foo_0x400080000000000(void) { return 0x400080000000000UL; } ++ unsigned long foo_0x800080000000000(void) { return 0x800080000000000UL; } ++ unsigned long foo_0x1000080000000000(void) { return 0x1000080000000000UL; } ++ unsigned long foo_0x2000080000000000(void) { return 0x2000080000000000UL; } ++ unsigned long foo_0x4000080000000000(void) { return 0x4000080000000000UL; } ++ unsigned long foo_0x8000080000000000(void) { return 0x8000080000000000UL; } ++ unsigned long foo_0x300000000000(void) { return 0x300000000000UL; } ++ unsigned long foo_0x500000000000(void) { return 0x500000000000UL; } ++ unsigned long foo_0x900000000000(void) { return 0x900000000000UL; } ++ unsigned long foo_0x1100000000000(void) { return 0x1100000000000UL; } ++ unsigned long foo_0x2100000000000(void) { return 0x2100000000000UL; } ++ unsigned long foo_0x4100000000000(void) { return 0x4100000000000UL; } ++ unsigned long foo_0x8100000000000(void) { return 0x8100000000000UL; } ++ unsigned long foo_0x10100000000000(void) { return 0x10100000000000UL; } ++ unsigned long foo_0x20100000000000(void) { return 0x20100000000000UL; } ++ unsigned long foo_0x40100000000000(void) { return 0x40100000000000UL; } ++ unsigned long foo_0x80100000000000(void) { return 0x80100000000000UL; } ++ unsigned long foo_0x100100000000000(void) { return 0x100100000000000UL; } ++ unsigned long foo_0x200100000000000(void) { return 0x200100000000000UL; } ++ unsigned long foo_0x400100000000000(void) { return 0x400100000000000UL; } ++ unsigned long foo_0x800100000000000(void) { return 0x800100000000000UL; } ++ unsigned long foo_0x1000100000000000(void) { return 0x1000100000000000UL; } ++ unsigned long foo_0x2000100000000000(void) { return 0x2000100000000000UL; } ++ unsigned long foo_0x4000100000000000(void) { return 0x4000100000000000UL; } ++ unsigned long foo_0x8000100000000000(void) { return 0x8000100000000000UL; } ++ unsigned long foo_0x600000000000(void) { return 0x600000000000UL; } ++ unsigned long foo_0xa00000000000(void) { return 0xa00000000000UL; } ++ unsigned long foo_0x1200000000000(void) { return 0x1200000000000UL; } ++ unsigned long foo_0x2200000000000(void) { return 0x2200000000000UL; } ++ unsigned long foo_0x4200000000000(void) { return 0x4200000000000UL; } ++ unsigned long foo_0x8200000000000(void) { return 0x8200000000000UL; } ++ unsigned long foo_0x10200000000000(void) { return 0x10200000000000UL; } ++ unsigned long foo_0x20200000000000(void) { return 0x20200000000000UL; } ++ unsigned long foo_0x40200000000000(void) { return 0x40200000000000UL; } ++ unsigned long foo_0x80200000000000(void) { return 0x80200000000000UL; } ++ unsigned long foo_0x100200000000000(void) { return 0x100200000000000UL; } ++ unsigned long foo_0x200200000000000(void) { return 0x200200000000000UL; } ++ unsigned long foo_0x400200000000000(void) { return 0x400200000000000UL; } ++ unsigned long foo_0x800200000000000(void) { return 0x800200000000000UL; } ++ unsigned long foo_0x1000200000000000(void) { return 0x1000200000000000UL; } ++ unsigned long foo_0x2000200000000000(void) { return 0x2000200000000000UL; } ++ unsigned long foo_0x4000200000000000(void) { return 0x4000200000000000UL; } ++ unsigned long foo_0x8000200000000000(void) { return 0x8000200000000000UL; } ++ unsigned long foo_0xc00000000000(void) { return 0xc00000000000UL; } ++ unsigned long foo_0x1400000000000(void) { return 0x1400000000000UL; } ++ unsigned long foo_0x2400000000000(void) { return 0x2400000000000UL; } ++ unsigned long foo_0x4400000000000(void) { return 0x4400000000000UL; } ++ unsigned long foo_0x8400000000000(void) { return 0x8400000000000UL; } ++ unsigned long foo_0x10400000000000(void) { return 0x10400000000000UL; } ++ unsigned long foo_0x20400000000000(void) { return 0x20400000000000UL; } ++ unsigned long foo_0x40400000000000(void) { return 0x40400000000000UL; } ++ unsigned long foo_0x80400000000000(void) { return 0x80400000000000UL; } ++ unsigned long foo_0x100400000000000(void) { return 0x100400000000000UL; } ++ unsigned long foo_0x200400000000000(void) { return 0x200400000000000UL; } ++ unsigned long foo_0x400400000000000(void) { return 0x400400000000000UL; } ++ unsigned long foo_0x800400000000000(void) { return 0x800400000000000UL; } ++ unsigned long foo_0x1000400000000000(void) { return 0x1000400000000000UL; } ++ unsigned long foo_0x2000400000000000(void) { return 0x2000400000000000UL; } ++ unsigned long foo_0x4000400000000000(void) { return 0x4000400000000000UL; } ++ unsigned long foo_0x8000400000000000(void) { return 0x8000400000000000UL; } ++ unsigned long foo_0x1800000000000(void) { return 0x1800000000000UL; } ++ unsigned long foo_0x2800000000000(void) { return 0x2800000000000UL; } ++ unsigned long foo_0x4800000000000(void) { return 0x4800000000000UL; } ++ unsigned long foo_0x8800000000000(void) { return 0x8800000000000UL; } ++ unsigned long foo_0x10800000000000(void) { return 0x10800000000000UL; } ++ unsigned long foo_0x20800000000000(void) { return 0x20800000000000UL; } ++ unsigned long foo_0x40800000000000(void) { return 0x40800000000000UL; } ++ unsigned long foo_0x80800000000000(void) { return 0x80800000000000UL; } ++ unsigned long foo_0x100800000000000(void) { return 0x100800000000000UL; } ++ unsigned long foo_0x200800000000000(void) { return 0x200800000000000UL; } ++ unsigned long foo_0x400800000000000(void) { return 0x400800000000000UL; } ++ unsigned long foo_0x800800000000000(void) { return 0x800800000000000UL; } ++ unsigned long foo_0x1000800000000000(void) { return 0x1000800000000000UL; } ++ unsigned long foo_0x2000800000000000(void) { return 0x2000800000000000UL; } ++ unsigned long foo_0x4000800000000000(void) { return 0x4000800000000000UL; } ++ unsigned long foo_0x8000800000000000(void) { return 0x8000800000000000UL; } ++ unsigned long foo_0x3000000000000(void) { return 0x3000000000000UL; } ++ unsigned long foo_0x5000000000000(void) { return 0x5000000000000UL; } ++ unsigned long foo_0x9000000000000(void) { return 0x9000000000000UL; } ++ unsigned long foo_0x11000000000000(void) { return 0x11000000000000UL; } ++ unsigned long foo_0x21000000000000(void) { return 0x21000000000000UL; } ++ unsigned long foo_0x41000000000000(void) { return 0x41000000000000UL; } ++ unsigned long foo_0x81000000000000(void) { return 0x81000000000000UL; } ++ unsigned long foo_0x101000000000000(void) { return 0x101000000000000UL; } ++ unsigned long foo_0x201000000000000(void) { return 0x201000000000000UL; } ++ unsigned long foo_0x401000000000000(void) { return 0x401000000000000UL; } ++ unsigned long foo_0x801000000000000(void) { return 0x801000000000000UL; } ++ unsigned long foo_0x1001000000000000(void) { return 0x1001000000000000UL; } ++ unsigned long foo_0x2001000000000000(void) { return 0x2001000000000000UL; } ++ unsigned long foo_0x4001000000000000(void) { return 0x4001000000000000UL; } ++ unsigned long foo_0x8001000000000000(void) { return 0x8001000000000000UL; } ++ unsigned long foo_0x6000000000000(void) { return 0x6000000000000UL; } ++ unsigned long foo_0xa000000000000(void) { return 0xa000000000000UL; } ++ unsigned long foo_0x12000000000000(void) { return 0x12000000000000UL; } ++ unsigned long foo_0x22000000000000(void) { return 0x22000000000000UL; } ++ unsigned long foo_0x42000000000000(void) { return 0x42000000000000UL; } ++ unsigned long foo_0x82000000000000(void) { return 0x82000000000000UL; } ++ unsigned long foo_0x102000000000000(void) { return 0x102000000000000UL; } ++ unsigned long foo_0x202000000000000(void) { return 0x202000000000000UL; } ++ unsigned long foo_0x402000000000000(void) { return 0x402000000000000UL; } ++ unsigned long foo_0x802000000000000(void) { return 0x802000000000000UL; } ++ unsigned long foo_0x1002000000000000(void) { return 0x1002000000000000UL; } ++ unsigned long foo_0x2002000000000000(void) { return 0x2002000000000000UL; } ++ unsigned long foo_0x4002000000000000(void) { return 0x4002000000000000UL; } ++ unsigned long foo_0x8002000000000000(void) { return 0x8002000000000000UL; } ++ unsigned long foo_0xc000000000000(void) { return 0xc000000000000UL; } ++ unsigned long foo_0x14000000000000(void) { return 0x14000000000000UL; } ++ unsigned long foo_0x24000000000000(void) { return 0x24000000000000UL; } ++ unsigned long foo_0x44000000000000(void) { return 0x44000000000000UL; } ++ unsigned long foo_0x84000000000000(void) { return 0x84000000000000UL; } ++ unsigned long foo_0x104000000000000(void) { return 0x104000000000000UL; } ++ unsigned long foo_0x204000000000000(void) { return 0x204000000000000UL; } ++ unsigned long foo_0x404000000000000(void) { return 0x404000000000000UL; } ++ unsigned long foo_0x804000000000000(void) { return 0x804000000000000UL; } ++ unsigned long foo_0x1004000000000000(void) { return 0x1004000000000000UL; } ++ unsigned long foo_0x2004000000000000(void) { return 0x2004000000000000UL; } ++ unsigned long foo_0x4004000000000000(void) { return 0x4004000000000000UL; } ++ unsigned long foo_0x8004000000000000(void) { return 0x8004000000000000UL; } ++ unsigned long foo_0x18000000000000(void) { return 0x18000000000000UL; } ++ unsigned long foo_0x28000000000000(void) { return 0x28000000000000UL; } ++ unsigned long foo_0x48000000000000(void) { return 0x48000000000000UL; } ++ unsigned long foo_0x88000000000000(void) { return 0x88000000000000UL; } ++ unsigned long foo_0x108000000000000(void) { return 0x108000000000000UL; } ++ unsigned long foo_0x208000000000000(void) { return 0x208000000000000UL; } ++ unsigned long foo_0x408000000000000(void) { return 0x408000000000000UL; } ++ unsigned long foo_0x808000000000000(void) { return 0x808000000000000UL; } ++ unsigned long foo_0x1008000000000000(void) { return 0x1008000000000000UL; } ++ unsigned long foo_0x2008000000000000(void) { return 0x2008000000000000UL; } ++ unsigned long foo_0x4008000000000000(void) { return 0x4008000000000000UL; } ++ unsigned long foo_0x8008000000000000(void) { return 0x8008000000000000UL; } ++ unsigned long foo_0x30000000000000(void) { return 0x30000000000000UL; } ++ unsigned long foo_0x50000000000000(void) { return 0x50000000000000UL; } ++ unsigned long foo_0x90000000000000(void) { return 0x90000000000000UL; } ++ unsigned long foo_0x110000000000000(void) { return 0x110000000000000UL; } ++ unsigned long foo_0x210000000000000(void) { return 0x210000000000000UL; } ++ unsigned long foo_0x410000000000000(void) { return 0x410000000000000UL; } ++ unsigned long foo_0x810000000000000(void) { return 0x810000000000000UL; } ++ unsigned long foo_0x1010000000000000(void) { return 0x1010000000000000UL; } ++ unsigned long foo_0x2010000000000000(void) { return 0x2010000000000000UL; } ++ unsigned long foo_0x4010000000000000(void) { return 0x4010000000000000UL; } ++ unsigned long foo_0x8010000000000000(void) { return 0x8010000000000000UL; } ++ unsigned long foo_0x60000000000000(void) { return 0x60000000000000UL; } ++ unsigned long foo_0xa0000000000000(void) { return 0xa0000000000000UL; } ++ unsigned long foo_0x120000000000000(void) { return 0x120000000000000UL; } ++ unsigned long foo_0x220000000000000(void) { return 0x220000000000000UL; } ++ unsigned long foo_0x420000000000000(void) { return 0x420000000000000UL; } ++ unsigned long foo_0x820000000000000(void) { return 0x820000000000000UL; } ++ unsigned long foo_0x1020000000000000(void) { return 0x1020000000000000UL; } ++ unsigned long foo_0x2020000000000000(void) { return 0x2020000000000000UL; } ++ unsigned long foo_0x4020000000000000(void) { return 0x4020000000000000UL; } ++ unsigned long foo_0x8020000000000000(void) { return 0x8020000000000000UL; } ++ unsigned long foo_0xc0000000000000(void) { return 0xc0000000000000UL; } ++ unsigned long foo_0x140000000000000(void) { return 0x140000000000000UL; } ++ unsigned long foo_0x240000000000000(void) { return 0x240000000000000UL; } ++ unsigned long foo_0x440000000000000(void) { return 0x440000000000000UL; } ++ unsigned long foo_0x840000000000000(void) { return 0x840000000000000UL; } ++ unsigned long foo_0x1040000000000000(void) { return 0x1040000000000000UL; } ++ unsigned long foo_0x2040000000000000(void) { return 0x2040000000000000UL; } ++ unsigned long foo_0x4040000000000000(void) { return 0x4040000000000000UL; } ++ unsigned long foo_0x8040000000000000(void) { return 0x8040000000000000UL; } ++ unsigned long foo_0x180000000000000(void) { return 0x180000000000000UL; } ++ unsigned long foo_0x280000000000000(void) { return 0x280000000000000UL; } ++ unsigned long foo_0x480000000000000(void) { return 0x480000000000000UL; } ++ unsigned long foo_0x880000000000000(void) { return 0x880000000000000UL; } ++ unsigned long foo_0x1080000000000000(void) { return 0x1080000000000000UL; } ++ unsigned long foo_0x2080000000000000(void) { return 0x2080000000000000UL; } ++ unsigned long foo_0x4080000000000000(void) { return 0x4080000000000000UL; } ++ unsigned long foo_0x8080000000000000(void) { return 0x8080000000000000UL; } ++ unsigned long foo_0x300000000000000(void) { return 0x300000000000000UL; } ++ unsigned long foo_0x500000000000000(void) { return 0x500000000000000UL; } ++ unsigned long foo_0x900000000000000(void) { return 0x900000000000000UL; } ++ unsigned long foo_0x1100000000000000(void) { return 0x1100000000000000UL; } ++ unsigned long foo_0x2100000000000000(void) { return 0x2100000000000000UL; } ++ unsigned long foo_0x4100000000000000(void) { return 0x4100000000000000UL; } ++ unsigned long foo_0x8100000000000000(void) { return 0x8100000000000000UL; } ++ unsigned long foo_0x600000000000000(void) { return 0x600000000000000UL; } ++ unsigned long foo_0xa00000000000000(void) { return 0xa00000000000000UL; } ++ unsigned long foo_0x1200000000000000(void) { return 0x1200000000000000UL; } ++ unsigned long foo_0x2200000000000000(void) { return 0x2200000000000000UL; } ++ unsigned long foo_0x4200000000000000(void) { return 0x4200000000000000UL; } ++ unsigned long foo_0x8200000000000000(void) { return 0x8200000000000000UL; } ++ unsigned long foo_0xc00000000000000(void) { return 0xc00000000000000UL; } ++ unsigned long foo_0x1400000000000000(void) { return 0x1400000000000000UL; } ++ unsigned long foo_0x2400000000000000(void) { return 0x2400000000000000UL; } ++ unsigned long foo_0x4400000000000000(void) { return 0x4400000000000000UL; } ++ unsigned long foo_0x8400000000000000(void) { return 0x8400000000000000UL; } ++ unsigned long foo_0x1800000000000000(void) { return 0x1800000000000000UL; } ++ unsigned long foo_0x2800000000000000(void) { return 0x2800000000000000UL; } ++ unsigned long foo_0x4800000000000000(void) { return 0x4800000000000000UL; } ++ unsigned long foo_0x8800000000000000(void) { return 0x8800000000000000UL; } ++ unsigned long foo_0x3000000000000000(void) { return 0x3000000000000000UL; } ++ unsigned long foo_0x5000000000000000(void) { return 0x5000000000000000UL; } ++ unsigned long foo_0x9000000000000000(void) { return 0x9000000000000000UL; } ++ unsigned long foo_0x6000000000000000(void) { return 0x6000000000000000UL; } ++ unsigned long foo_0xa000000000000000(void) { return 0xa000000000000000UL; } ++ unsigned long foo_0xc000000000000000(void) { return 0xc000000000000000UL; } ++ ++ +-- +2.47.3 + diff --git a/1024-This-is-almost-exclusively-Jivan-s-work.-His-origina.patch b/1024-This-is-almost-exclusively-Jivan-s-work.-His-origina.patch new file mode 100644 index 0000000..05ed538 --- /dev/null +++ b/1024-This-is-almost-exclusively-Jivan-s-work.-His-origina.patch @@ -0,0 +1,630 @@ +From 844f886f63bf559faf66ef9f251c9b408c22bcc1 Mon Sep 17 00:00:00 2001 +From: Jivan Hakobyan +Date: Tue, 30 Apr 2024 09:44:02 -0600 +Subject: [PATCH 1024/1087] This is almost exclusively Jivan's work. His + original post: + +commit upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +> https://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg336483.html + +This patch is primarily meant to improve the code we generate for FP rounding +such as ceil/floor. It also addresses some unnecessary sign extensions in the +same areas. + +RISC-V's FP conversions have a bit of undesirable behavior that make them +non-suitable as-is for ceil/floor and other related functions. These +deficiencies are addressed in the Zfa extension, but there's no reason not to +pick up a nice improvement when we can. + +Basically we can still use the basic FP conversions for floor/ceil and friends +when we don't care about inexact exceptions by checking for the special cases +first, then emitting the conversion when the special cases don't apply. That's +still much faster than calling into glibc. + +The redundant sign extensions are eliminated using the same trick Jivan added +last year, just in a few more places ;-) + +This eliminates roughly 10% of the dynamic instruction count for imagick. But +more importantly it's about a 17% performance improvement for that workload +within spec. + +This has been bootstrapped as well as regression tested in a cross environment. +It's also successfully built & run specint/specfp correctly. + +Pushing to the trunk and the coordination branch momentarily. + +gcc/ + * config/riscv/iterators.md (fix_ops, fix_uns): New iterators. + (RINT, rint_pattern, rint_rm): Remove unused iterators. + * config/riscv/riscv-protos.h (get_fp_rounding_coefficient): Prototype. + * config/riscv/riscv-v.cc (get_fp_rounding_coefficient): Externalize. + external linkage. + * config/riscv/riscv.md (UNSPEC_LROUND): Remove. + (fix_trunc2): Replace with ... + (_truncsi2): New expander & associated insn. + (_truncsi2_ext): New insn. + (_truncdi2): Likewise. + (l2): Replace with ... + (lrintsi2): New expander and associated insn. + (lrintsi2_ext, lrintdi2): New insns. + (2): Replace with.... + (lsi2): New expander and associated insn. + (lsi2_sext): New insn. + (ldi2): Likewise. + (2): New expander. + +gcc/testsuite/ + * gcc.target/riscv/fix.c: New test. + * gcc.target/riscv/round.c: New test. + * gcc.target/riscv/round_32.c: New test. + * gcc.target/riscv/round_64.c: New test. +--- + gcc/config/riscv/iterators.md | 12 +- + gcc/config/riscv/riscv-protos.h | 1 + + gcc/config/riscv/riscv-v.cc | 2 +- + gcc/config/riscv/riscv.md | 211 ++++++++++++++++++++-- + gcc/testsuite/gcc.target/riscv/fix.c | 34 ++++ + gcc/testsuite/gcc.target/riscv/round.c | 144 +++++++++++++++ + gcc/testsuite/gcc.target/riscv/round_32.c | 22 +++ + gcc/testsuite/gcc.target/riscv/round_64.c | 23 +++ + 8 files changed, 427 insertions(+), 22 deletions(-) + create mode 100644 gcc/testsuite/gcc.target/riscv/fix.c + create mode 100644 gcc/testsuite/gcc.target/riscv/round.c + create mode 100644 gcc/testsuite/gcc.target/riscv/round_32.c + create mode 100644 gcc/testsuite/gcc.target/riscv/round_64.c + +diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md +index e2898ba0b51..bad9ba19933 100644 +--- a/gcc/config/riscv/iterators.md ++++ b/gcc/config/riscv/iterators.md +@@ -202,6 +202,13 @@ + + (define_code_iterator bitmanip_rotate [rotate rotatert]) + ++;; These code iterators allow the signed and unsigned fix operations to use ++;; the same template. ++(define_code_iterator fix_ops [fix unsigned_fix]) ++ ++(define_code_attr fix_uns [(fix "fix") (unsigned_fix "fixuns")]) ++ ++ + ;; ------------------------------------------------------------------- + ;; Code Attributes + ;; ------------------------------------------------------------------- +@@ -318,11 +325,6 @@ + ;; Int Iterators. + ;; ------------------------------------------------------------------- + +-;; Iterator and attributes for floating-point rounding instructions. +-(define_int_iterator RINT [UNSPEC_LRINT UNSPEC_LROUND]) +-(define_int_attr rint_pattern [(UNSPEC_LRINT "rint") (UNSPEC_LROUND "round")]) +-(define_int_attr rint_rm [(UNSPEC_LRINT "dyn") (UNSPEC_LROUND "rmm")]) +- + ;; Iterator and attributes for quiet comparisons. + (define_int_iterator QUIET_COMPARISON [UNSPEC_FLT_QUIET UNSPEC_FLE_QUIET]) + (define_int_attr quiet_pattern [(UNSPEC_FLT_QUIET "lt") (UNSPEC_FLE_QUIET "le")]) +diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h +index ec1c053564d..2f6f783f289 100644 +--- a/gcc/config/riscv/riscv-protos.h ++++ b/gcc/config/riscv/riscv-protos.h +@@ -717,6 +717,7 @@ bool gather_scatter_valid_offset_p (machine_mode); + HOST_WIDE_INT estimated_poly_value (poly_int64, unsigned int); + bool whole_reg_to_reg_move_p (rtx *, machine_mode, int); + bool splat_to_scalar_move_p (rtx *); ++rtx get_fp_rounding_coefficient (machine_mode); + } + + /* We classify builtin types into two classes: +diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc +index 4371971507c..cb7a0bb3d3d 100644 +--- a/gcc/config/riscv/riscv-v.cc ++++ b/gcc/config/riscv/riscv-v.cc +@@ -4571,7 +4571,7 @@ vls_mode_valid_p (machine_mode vls_mode) + All double floating point will be unchanged for ceil if it is + greater than and equal to 4503599627370496. + */ +-static rtx ++rtx + get_fp_rounding_coefficient (machine_mode inner_mode) + { + REAL_VALUE_TYPE real; +diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md +index dcce06b6704..9ee8a11c1cf 100644 +--- a/gcc/config/riscv/riscv.md ++++ b/gcc/config/riscv/riscv.md +@@ -66,7 +66,6 @@ + UNSPEC_ROUNDEVEN + UNSPEC_NEARBYINT + UNSPEC_LRINT +- UNSPEC_LROUND + UNSPEC_FMIN + UNSPEC_FMAX + UNSPEC_FMINM +@@ -1991,21 +1990,48 @@ + ;; + ;; .................... + +-(define_insn "fix_trunc2" +- [(set (match_operand:GPR 0 "register_operand" "=r") +- (fix:GPR ++(define_expand "_truncsi2" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (fix_ops:SI + (match_operand:ANYF 1 "register_operand" " f")))] + "TARGET_HARD_FLOAT || TARGET_ZFINX" +- "fcvt.. %0,%1,rtz" ++{ ++ if (TARGET_64BIT) ++ { ++ rtx t = gen_reg_rtx (DImode); ++ emit_insn (gen__truncsi2_sext (t, operands[1])); ++ t = gen_lowpart (SImode, t); ++ SUBREG_PROMOTED_VAR_P (t) = 1; ++ SUBREG_PROMOTED_SET (t, SRP_SIGNED); ++ emit_move_insn (operands[0], t); ++ DONE; ++ } ++}) ++ ++(define_insn "*_truncsi2" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (fix_ops:SI ++ (match_operand:ANYF 1 "register_operand" " f")))] ++ "TARGET_HARD_FLOAT || TARGET_ZFINX" ++ "fcvt.w. %0,%1,rtz" ++ [(set_attr "type" "fcvt_f2i") ++ (set_attr "mode" "")]) ++ ++(define_insn "_truncsi2_sext" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (sign_extend:DI (fix_ops:SI ++ (match_operand:ANYF 1 "register_operand" " f"))))] ++ "TARGET_64BIT && (TARGET_HARD_FLOAT || TARGET_ZFINX)" ++ "fcvt.w. %0,%1,rtz" + [(set_attr "type" "fcvt_f2i") + (set_attr "mode" "")]) + +-(define_insn "fixuns_trunc2" +- [(set (match_operand:GPR 0 "register_operand" "=r") +- (unsigned_fix:GPR ++(define_insn "_truncdi2" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (fix_ops:DI + (match_operand:ANYF 1 "register_operand" " f")))] +- "TARGET_HARD_FLOAT || TARGET_ZFINX" +- "fcvt.u. %0,%1,rtz" ++ "TARGET_64BIT && (TARGET_HARD_FLOAT || TARGET_ZFINX)" ++ "fcvt.l. %0,%1,rtz" + [(set_attr "type" "fcvt_f2i") + (set_attr "mode" "")]) + +@@ -2027,17 +2053,170 @@ + [(set_attr "type" "fcvt_i2f") + (set_attr "mode" "")]) + +-(define_insn "l2" +- [(set (match_operand:GPR 0 "register_operand" "=r") +- (unspec:GPR ++(define_expand "lrintsi2" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (unspec:SI + [(match_operand:ANYF 1 "register_operand" " f")] +- RINT))] ++ UNSPEC_LRINT))] + "TARGET_HARD_FLOAT || TARGET_ZFINX" +- "fcvt.. %0,%1," ++{ ++ if (TARGET_64BIT) ++ { ++ rtx t = gen_reg_rtx (DImode); ++ emit_insn (gen_lrintsi2_sext (t, operands[1])); ++ t = gen_lowpart (SImode, t); ++ SUBREG_PROMOTED_VAR_P (t) = 1; ++ SUBREG_PROMOTED_SET (t, SRP_SIGNED); ++ emit_move_insn (operands[0], t); ++ DONE; ++ } ++}) ++ ++(define_insn "*lrintsi2" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (unspec:SI ++ [(match_operand:ANYF 1 "register_operand" " f")] ++ UNSPEC_LRINT))] ++ "TARGET_HARD_FLOAT || TARGET_ZFINX" ++ "fcvt.w. %0,%1,dyn" ++ [(set_attr "type" "fcvt_f2i") ++ (set_attr "mode" "")]) ++ ++(define_insn "lrintsi2_sext" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (sign_extend:DI (unspec:SI ++ [(match_operand:ANYF 1 "register_operand" " f")] ++ UNSPEC_LRINT)))] ++ "TARGET_64BIT && (TARGET_HARD_FLOAT || TARGET_ZFINX)" ++ "fcvt.w. %0,%1,dyn" + [(set_attr "type" "fcvt_f2i") + (set_attr "mode" "")]) + +-(define_insn "2" ++(define_insn "lrintdi2" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (unspec:DI ++ [(match_operand:ANYF 1 "register_operand" " f")] ++ UNSPEC_LRINT))] ++ "TARGET_64BIT && (TARGET_HARD_FLOAT || TARGET_ZFINX)" ++ "fcvt.l. %0,%1,dyn" ++ [(set_attr "type" "fcvt_f2i") ++ (set_attr "mode" "")]) ++ ++(define_expand "lsi2" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (unspec:SI ++ [(match_operand:ANYF 1 "register_operand" " f")] ++ ROUND))] ++ "TARGET_HARD_FLOAT || TARGET_ZFINX" ++{ ++ if (TARGET_64BIT) ++ { ++ rtx t = gen_reg_rtx (DImode); ++ emit_insn (gen_lsi2_sext (t, operands[1])); ++ t = gen_lowpart (SImode, t); ++ SUBREG_PROMOTED_VAR_P (t) = 1; ++ SUBREG_PROMOTED_SET (t, SRP_SIGNED); ++ emit_move_insn (operands[0], t); ++ DONE; ++ } ++}) ++ ++(define_insn "*lsi2" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (unspec:SI ++ [(match_operand:ANYF 1 "register_operand" " f")] ++ ROUND))] ++ "TARGET_HARD_FLOAT || TARGET_ZFINX" ++ "fcvt.w. %0,%1," ++ [(set_attr "type" "fcvt_f2i") ++ (set_attr "mode" "")]) ++ ++(define_insn "lsi2_sext" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (sign_extend:DI (unspec:SI ++ [(match_operand:ANYF 1 "register_operand" " f")] ++ ROUND)))] ++ "TARGET_64BIT && (TARGET_HARD_FLOAT || TARGET_ZFINX)" ++ "fcvt.w. %0,%1," ++ [(set_attr "type" "fcvt_f2i") ++ (set_attr "mode" "")]) ++ ++(define_insn "ldi2" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (unspec:DI ++ [(match_operand:ANYF 1 "register_operand" " f")] ++ ROUND))] ++ "TARGET_64BIT && (TARGET_HARD_FLOAT || TARGET_ZFINX)" ++ "fcvt.l. %0,%1," ++ [(set_attr "type" "fcvt_f2i") ++ (set_attr "mode" "")]) ++ ++(define_expand "2" ++ [(set (match_operand:ANYF 0 "register_operand" "=f") ++ (unspec:ANYF ++ [(match_operand:ANYF 1 "register_operand" " f")] ++ ROUND))] ++ "TARGET_HARD_FLOAT && (TARGET_ZFA ++ || flag_fp_int_builtin_inexact || !flag_trapping_math)" ++{ ++ if (TARGET_ZFA) ++ emit_insn (gen__zfa2 (operands[0], ++ operands[1])); ++ else ++ { ++ rtx reg; ++ rtx label = gen_label_rtx (); ++ rtx end_label = gen_label_rtx (); ++ rtx abs_reg = gen_reg_rtx (mode); ++ rtx coeff_reg = gen_reg_rtx (mode); ++ rtx tmp_reg = gen_reg_rtx (mode); ++ ++ riscv_emit_move (tmp_reg, operands[1]); ++ riscv_emit_move (coeff_reg, ++ riscv_vector::get_fp_rounding_coefficient (mode)); ++ emit_insn (gen_abs2 (abs_reg, operands[1])); ++ ++ riscv_expand_conditional_branch (label, LT, abs_reg, coeff_reg); ++ ++ emit_jump_insn (gen_jump (end_label)); ++ emit_barrier (); ++ ++ emit_label (label); ++ switch (mode) ++ { ++ case SFmode: ++ reg = gen_reg_rtx (SImode); ++ emit_insn (gen_lsfsi2 (reg, operands[1])); ++ emit_insn (gen_floatsisf2 (abs_reg, reg)); ++ break; ++ case DFmode: ++ if (TARGET_64BIT) ++ { ++ reg = gen_reg_rtx (DImode); ++ emit_insn (gen_ldfdi2 (reg, operands[1])); ++ emit_insn (gen_floatdidf2 (abs_reg, reg)); ++ } ++ else ++ { ++ reg = gen_reg_rtx (SImode); ++ emit_insn (gen_ldfsi2 (reg, operands[1])); ++ emit_insn (gen_floatsidf2 (abs_reg, reg)); ++ } ++ break; ++ default: ++ gcc_unreachable (); ++ } ++ ++ emit_insn (gen_copysign3 (tmp_reg, abs_reg, operands[1])); ++ ++ emit_label (end_label); ++ riscv_emit_move (operands[0], tmp_reg); ++ } ++ ++ DONE; ++}) ++ ++(define_insn "_zfa2" + [(set (match_operand:ANYF 0 "register_operand" "=f") + (unspec:ANYF + [(match_operand:ANYF 1 "register_operand" " f")] +diff --git a/gcc/testsuite/gcc.target/riscv/fix.c b/gcc/testsuite/gcc.target/riscv/fix.c +new file mode 100644 +index 00000000000..265a7da1fc5 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/fix.c +@@ -0,0 +1,34 @@ ++/* { dg-do compile } */ ++/* { dg-options "-march=rv64gc -mabi=lp64d" } */ ++/* { dg-skip-if "" { *-*-* } { "-O0" } } */ ++ ++int ++foo (double n) ++{ ++ return n; ++} ++ ++int ++foo_1 (float n) ++{ ++ return n; ++} ++ ++unsigned int ++foo_2 (double n) ++{ ++ return n; ++} ++ ++unsigned int ++foo_3 (float n) ++{ ++ return n; ++} ++ ++/* { dg-final { scan-assembler-times {\mfcvt.w.d} 1 } } */ ++/* { dg-final { scan-assembler-times {\mfcvt.w.s} 1 } } */ ++/* { dg-final { scan-assembler-times {\mfcvt.wu.d} 1 } } */ ++/* { dg-final { scan-assembler-times {\mfcvt.wu.s} 1 } } */ ++/* { dg-final { scan-assembler-not "\\ssext.w\\s" } } */ ++ +diff --git a/gcc/testsuite/gcc.target/riscv/round.c b/gcc/testsuite/gcc.target/riscv/round.c +new file mode 100644 +index 00000000000..decfc82a390 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/round.c +@@ -0,0 +1,144 @@ ++#include ++ ++extern void abort (void); ++extern void exit (int); ++ ++#define NEQ(a, b) (fabs((a) - (b)) > 0.000001) ++ ++#define DECL_FUNC(TYPE1, TYPE2, ROUND) \ ++ __attribute__ ((noinline, noclone)) TYPE2 \ ++ convert_##TYPE1##_to_##TYPE2##_##ROUND (TYPE1 N) \ ++ { \ ++ return ROUND (N); \ ++ } ++ ++#define DECL_ALL_ROUNDS_FOR(ROUND_FUNC) \ ++ DECL_FUNC(float, float, ROUND_FUNC) \ ++ DECL_FUNC(double, double, ROUND_FUNC) \ ++ DECL_FUNC(double, int, ROUND_FUNC) \ ++ DECL_FUNC(double, long, ROUND_FUNC) \ ++ DECL_FUNC(float, int, ROUND_FUNC) \ ++ DECL_FUNC(float, long, ROUND_FUNC) ++ ++ ++DECL_ALL_ROUNDS_FOR(round) ++DECL_ALL_ROUNDS_FOR(ceil) ++DECL_ALL_ROUNDS_FOR(floor) ++DECL_ALL_ROUNDS_FOR(trunc) ++DECL_ALL_ROUNDS_FOR(nearbyint) ++ ++#define TEST_ROUND(TYPE1, TYPE2, N, N_R, ROUND) \ ++ if (NEQ (convert_##TYPE1##_to_##TYPE2##_##ROUND (N), N_R)) \ ++ abort (); ++ ++ ++int main () { ++ ++ /* Round */ ++ TEST_ROUND(double, double, -4.8, -5.0, round); ++ TEST_ROUND(double, double, -4.2, -4.0, round); ++ TEST_ROUND(double, double, 4.8, 5.0, round); ++ TEST_ROUND(double, double, 4.2, 4.0, round); ++ ++ TEST_ROUND(double, int, -4.8, -5, round); ++ TEST_ROUND(double, int, -4.2, -4, round); ++ TEST_ROUND(double, int, 4.8, 5, round); ++ TEST_ROUND(double, int, 4.2, 4, round); ++ ++ TEST_ROUND(double, long, -4.8, -5, round); ++ TEST_ROUND(double, long, -4.2, -4, round); ++ TEST_ROUND(double, long, 4.8, 5, round); ++ TEST_ROUND(double, long, 4.2, 4, round); ++ ++ TEST_ROUND(float, long, -4.8, -5, round); ++ TEST_ROUND(float, long, -4.2, -4, round); ++ TEST_ROUND(float, long, 4.8, 5, round); ++ TEST_ROUND(float, long, 4.2, 4, round); ++ ++ /* Ceil */ ++ TEST_ROUND(double, double, -4.8, -4.0, ceil); ++ TEST_ROUND(double, double, -4.2, -4.0, ceil); ++ TEST_ROUND(double, double, 4.8, 5.0, ceil); ++ TEST_ROUND(double, double, 4.2, 5.0, ceil); ++ ++ TEST_ROUND(double, int, -4.8, -4, ceil); ++ TEST_ROUND(double, int, -4.2, -4, ceil); ++ TEST_ROUND(double, int, 4.8, 5, ceil); ++ TEST_ROUND(double, int, 4.2, 5, ceil); ++ ++ TEST_ROUND(double, long, -4.8, -4, ceil); ++ TEST_ROUND(double, long, -4.2, -4, ceil); ++ TEST_ROUND(double, long, 4.8, 5, ceil); ++ TEST_ROUND(double, long, 4.2, 5, ceil); ++ ++ TEST_ROUND(float, long, -4.8, -4, ceil); ++ TEST_ROUND(float, long, -4.2, -4, ceil); ++ TEST_ROUND(float, long, 4.8, 5, ceil); ++ TEST_ROUND(float, long, 4.2, 5, ceil); ++ ++ /* Floor */ ++ TEST_ROUND(double, double, -4.8, -5.0, floor); ++ TEST_ROUND(double, double, -4.2, -5.0, floor); ++ TEST_ROUND(double, double, 4.8, 4.0, floor); ++ TEST_ROUND(double, double, 4.2, 4.0, floor); ++ ++ TEST_ROUND(double, int, -4.8, -5, floor); ++ TEST_ROUND(double, int, -4.2, -5, floor); ++ TEST_ROUND(double, int, 4.8, 4, floor); ++ TEST_ROUND(double, int, 4.2, 4, floor); ++ ++ TEST_ROUND(double, long, -4.8, -5, floor); ++ TEST_ROUND(double, long, -4.2, -5, floor); ++ TEST_ROUND(double, long, 4.8, 4, floor); ++ TEST_ROUND(double, long, 4.2, 4, floor); ++ ++ TEST_ROUND(float, long, -4.8, -5, floor); ++ TEST_ROUND(float, long, -4.2, -5, floor); ++ TEST_ROUND(float, long, 4.8, 4, floor); ++ TEST_ROUND(float, long, 4.2, 4, floor); ++ ++ /* Trunc */ ++ TEST_ROUND(double, double, -4.8, -4.0, trunc); ++ TEST_ROUND(double, double, -4.2, -4.0, trunc); ++ TEST_ROUND(double, double, 4.8, 4.0, trunc); ++ TEST_ROUND(double, double, 4.2, 4.0, trunc); ++ ++ TEST_ROUND(double, int, -4.8, -4, trunc); ++ TEST_ROUND(double, int, -4.2, -4, trunc); ++ TEST_ROUND(double, int, 4.8, 4, trunc); ++ TEST_ROUND(double, int, 4.2, 4, trunc); ++ ++ TEST_ROUND(double, long, -4.8, -4, trunc); ++ TEST_ROUND(double, long, -4.2, -4, trunc); ++ TEST_ROUND(double, long, 4.8, 4, trunc); ++ TEST_ROUND(double, long, 4.2, 4, trunc); ++ ++ TEST_ROUND(float, long, -4.8, -4, trunc); ++ TEST_ROUND(float, long, -4.2, -4, trunc); ++ TEST_ROUND(float, long, 4.8, 4, trunc); ++ TEST_ROUND(float, long, 4.2, 4, trunc); ++ ++ /* Nearbyint */ ++ TEST_ROUND(double, double, -4.8, -5.0, nearbyint); ++ TEST_ROUND(double, double, -4.2, -4.0, nearbyint); ++ TEST_ROUND(double, double, 4.8, 5.0, nearbyint); ++ TEST_ROUND(double, double, 4.2, 4.0, nearbyint); ++ ++ TEST_ROUND(double, int, -4.8, -5, nearbyint); ++ TEST_ROUND(double, int, -4.2, -4, nearbyint); ++ TEST_ROUND(double, int, 4.8, 5, nearbyint); ++ TEST_ROUND(double, int, 4.2, 4, nearbyint); ++ ++ TEST_ROUND(double, long, -4.8, -5, nearbyint); ++ TEST_ROUND(double, long, -4.2, -4, nearbyint); ++ TEST_ROUND(double, long, 4.8, 5, nearbyint); ++ TEST_ROUND(double, long, 4.2, 4, nearbyint); ++ ++ TEST_ROUND(float, long, -4.8, -5, nearbyint); ++ TEST_ROUND(float, long, -4.2, -4, nearbyint); ++ TEST_ROUND(float, long, 4.8, 5, nearbyint); ++ TEST_ROUND(float, long, 4.2, 4, nearbyint); ++ ++ exit(0); ++} ++ +diff --git a/gcc/testsuite/gcc.target/riscv/round_32.c b/gcc/testsuite/gcc.target/riscv/round_32.c +new file mode 100644 +index 00000000000..f9fea70ad55 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/round_32.c +@@ -0,0 +1,22 @@ ++/* { dg-do compile { target { riscv32*-*-* } } } */ ++/* { dg-options "-march=rv32gc -mabi=ilp32d -fno-math-errno -funsafe-math-optimizations -fno-inline" } */ ++/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ ++ ++#include "round.c" ++ ++/* { dg-final { scan-assembler-times {\mfcvt.w.s} 15 } } */ ++/* { dg-final { scan-assembler-times {\mfcvt.s.w} 5 } } */ ++/* { dg-final { scan-assembler-times {\mfcvt.d.w} 65 } } */ ++/* { dg-final { scan-assembler-times {\mfcvt.w.d} 15 } } */ ++/* { dg-final { scan-assembler-times {,rup} 6 } } */ ++/* { dg-final { scan-assembler-times {,rmm} 6 } } */ ++/* { dg-final { scan-assembler-times {,rdn} 6 } } */ ++/* { dg-final { scan-assembler-times {,rtz} 6 } } */ ++/* { dg-final { scan-assembler-not {\mfcvt.l.d} } } */ ++/* { dg-final { scan-assembler-not {\mfcvt.d.l} } } */ ++/* { dg-final { scan-assembler-not "\\sceil\\s" } } */ ++/* { dg-final { scan-assembler-not "\\sfloor\\s" } } */ ++/* { dg-final { scan-assembler-not "\\sround\\s" } } */ ++/* { dg-final { scan-assembler-not "\\snearbyint\\s" } } */ ++/* { dg-final { scan-assembler-not "\\srint\\s" } } */ ++/* { dg-final { scan-assembler-not "\\stail\\s" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/round_64.c b/gcc/testsuite/gcc.target/riscv/round_64.c +new file mode 100644 +index 00000000000..e79690979a5 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/round_64.c +@@ -0,0 +1,23 @@ ++/* { dg-do compile { target { riscv64*-*-* } } } */ ++/* { dg-options "-march=rv64gc -mabi=lp64d -fno-math-errno -funsafe-math-optimizations -fno-inline" } */ ++/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ ++ ++#include "round.c" ++ ++/* { dg-final { scan-assembler-times {\mfcvt.w.s} 10 } } */ ++/* { dg-final { scan-assembler-times {\mfcvt.s.w} 5 } } */ ++/* { dg-final { scan-assembler-times {\mfcvt.l.d} 10 } } */ ++/* { dg-final { scan-assembler-times {\mfcvt.d.l} 45 } } */ ++/* { dg-final { scan-assembler-times {\mfcvt.w.d} 5 } } */ ++/* { dg-final { scan-assembler-times {,rup} 6 } } */ ++/* { dg-final { scan-assembler-times {,rmm} 6 } } */ ++/* { dg-final { scan-assembler-times {,rdn} 6 } } */ ++/* { dg-final { scan-assembler-times {,rtz} 6 } } */ ++/* { dg-final { scan-assembler-not "\\sceil\\s" } } */ ++/* { dg-final { scan-assembler-not "\\sfloor\\s" } } */ ++/* { dg-final { scan-assembler-not "\\sround\\s" } } */ ++/* { dg-final { scan-assembler-not "\\snearbyint\\s" } } */ ++/* { dg-final { scan-assembler-not "\\srint\\s" } } */ ++/* { dg-final { scan-assembler-not "\\stail\\s" } } */ ++/* { dg-final { scan-assembler-not "\\ssext.w\\s" } } */ ++ +-- +2.47.3 + diff --git a/1025-Fix-nearbyint-failure-on-rv32-and-formatting-nits.patch b/1025-Fix-nearbyint-failure-on-rv32-and-formatting-nits.patch new file mode 100644 index 0000000..d8977fe --- /dev/null +++ b/1025-Fix-nearbyint-failure-on-rv32-and-formatting-nits.patch @@ -0,0 +1,138 @@ +From 43913e6e35bcc8aa9c6b4a4f11bf0b84b1b7da4c Mon Sep 17 00:00:00 2001 +From: Jeff Law +Date: Thu, 2 May 2024 17:13:12 -0600 +Subject: [PATCH 1025/1087] Fix nearbyint failure on rv32 and formatting nits + +commit 8367c996e55b2c54aeee25e446357a1015a1d11d upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +The CI system tripped an execution failure for rv32 with the ceil/round patch. + +The fundamental problem is the FP->INT step in these sequences requires the +input size to match the output size. The output size was based on rv32/rv64. +Meaning that we'd try to do DF->SI->DF. + +That doesn't preserve the semantics we want in at least two ways. + +The net is we can't use this trick for DF values on rv32. While inside the +code I realized we had a similar problem for HF modes. HF modes we can support +only for Zfa. So I fixed that proactively. + +The CI system also pointed out various formatting nits. I think this fixes all +but one overly long line. + +Note I could have factored the TARGET_ZFA test. But I think as-written it's +clearer what the desired cases to transform are. + +gcc/ + * config/riscv/riscv.md (2): Adjust + condition to match what can be properly implemented. Fix various + formatting issues. + (lsi2_sext): Fix formatting +--- + gcc/config/riscv/riscv.md | 65 ++++++++++++++++++++------------------- + 1 file changed, 34 insertions(+), 31 deletions(-) + +diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md +index 9ee8a11c1cf..40bc0ab2295 100644 +--- a/gcc/config/riscv/riscv.md ++++ b/gcc/config/riscv/riscv.md +@@ -2134,8 +2134,8 @@ + (define_insn "lsi2_sext" + [(set (match_operand:DI 0 "register_operand" "=r") + (sign_extend:DI (unspec:SI +- [(match_operand:ANYF 1 "register_operand" " f")] +- ROUND)))] ++ [(match_operand:ANYF 1 "register_operand" " f")] ++ ROUND)))] + "TARGET_64BIT && (TARGET_HARD_FLOAT || TARGET_ZFINX)" + "fcvt.w. %0,%1," + [(set_attr "type" "fcvt_f2i") +@@ -2151,13 +2151,25 @@ + [(set_attr "type" "fcvt_f2i") + (set_attr "mode" "")]) + ++;; There are a couple non-obvious restrictions to be aware of. ++;; ++;; We'll do a FP-INT conversion in the sequence. But we don't ++;; have a .l (64bit) variant of those instructions for rv32. ++;; To preserve proper semantics we must reject DFmode inputs ++;; for rv32 unless Zfa is enabled. ++;; ++;; The ANYF iterator allows HFmode. We don't have all the ++;; necessary patterns defined for HFmode. So restrict HFmode ++;; to TARGET_ZFA. + (define_expand "2" + [(set (match_operand:ANYF 0 "register_operand" "=f") +- (unspec:ANYF +- [(match_operand:ANYF 1 "register_operand" " f")] +- ROUND))] +- "TARGET_HARD_FLOAT && (TARGET_ZFA +- || flag_fp_int_builtin_inexact || !flag_trapping_math)" ++ (unspec:ANYF ++ [(match_operand:ANYF 1 "register_operand" " f")] ++ ROUND))] ++ "(TARGET_HARD_FLOAT ++ && (TARGET_ZFA || flag_fp_int_builtin_inexact || !flag_trapping_math) ++ && (TARGET_ZFA || TARGET_64BIT || mode != DFmode) ++ && (TARGET_ZFA || mode != HFmode))" + { + if (TARGET_ZFA) + emit_insn (gen__zfa2 (operands[0], +@@ -2173,7 +2185,7 @@ + + riscv_emit_move (tmp_reg, operands[1]); + riscv_emit_move (coeff_reg, +- riscv_vector::get_fp_rounding_coefficient (mode)); ++ riscv_vector::get_fp_rounding_coefficient (mode)); + emit_insn (gen_abs2 (abs_reg, operands[1])); + + riscv_expand_conditional_branch (label, LT, abs_reg, coeff_reg); +@@ -2183,29 +2195,20 @@ + + emit_label (label); + switch (mode) +- { +- case SFmode: +- reg = gen_reg_rtx (SImode); +- emit_insn (gen_lsfsi2 (reg, operands[1])); +- emit_insn (gen_floatsisf2 (abs_reg, reg)); +- break; +- case DFmode: +- if (TARGET_64BIT) +- { +- reg = gen_reg_rtx (DImode); +- emit_insn (gen_ldfdi2 (reg, operands[1])); +- emit_insn (gen_floatdidf2 (abs_reg, reg)); +- } +- else +- { +- reg = gen_reg_rtx (SImode); +- emit_insn (gen_ldfsi2 (reg, operands[1])); +- emit_insn (gen_floatsidf2 (abs_reg, reg)); +- } +- break; +- default: +- gcc_unreachable (); +- } ++ { ++ case SFmode: ++ reg = gen_reg_rtx (SImode); ++ emit_insn (gen_lsfsi2 (reg, operands[1])); ++ emit_insn (gen_floatsisf2 (abs_reg, reg)); ++ break; ++ case DFmode: ++ reg = gen_reg_rtx (DImode); ++ emit_insn (gen_ldfdi2 (reg, operands[1])); ++ emit_insn (gen_floatdidf2 (abs_reg, reg)); ++ break; ++ default: ++ gcc_unreachable (); ++ } + + emit_insn (gen_copysign3 (tmp_reg, abs_reg, operands[1])); + +-- +2.47.3 + diff --git a/1026-Don-t-run-new-rounding-tests-on-newlib-risc-v-target.patch b/1026-Don-t-run-new-rounding-tests-on-newlib-risc-v-target.patch new file mode 100644 index 0000000..838d687 --- /dev/null +++ b/1026-Don-t-run-new-rounding-tests-on-newlib-risc-v-target.patch @@ -0,0 +1,51 @@ +From b9dabb87ebc15c8d92efa21060473d4aa553ba3f Mon Sep 17 00:00:00 2001 +From: Jeff Law +Date: Thu, 2 May 2024 08:42:32 -0600 +Subject: [PATCH 1026/1087] Don't run new rounding tests on newlib risc-v + targets + +commit 1e29da0b6508b23a7a6b14a7fb643b917a195003 upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +The new round_32.c and round_64.c tests depend on the optimizers to recognize +the conversions feeding the floor/ceil calls and convert them into ceilf, +floorf and the like. + +Those transformations only occur when the target indicates the C library has +the appropriate routines (fnclass == function_c99_misc). While newlib has +these routines, they are not exposed as available to the compiler and thus the +transformation the tests depend on do not happen. Naturally the scan-tests then +fail. + +gcc/testsuite + * gcc.target/riscv/round_32.c: Add require-effective-target glibc. + * gcc.target/riscv/round_64.c: Likewise. +--- + gcc/testsuite/gcc.target/riscv/round_32.c | 1 + + gcc/testsuite/gcc.target/riscv/round_64.c | 1 + + 2 files changed, 2 insertions(+) + +diff --git a/gcc/testsuite/gcc.target/riscv/round_32.c b/gcc/testsuite/gcc.target/riscv/round_32.c +index f9fea70ad55..88ff77aff2e 100644 +--- a/gcc/testsuite/gcc.target/riscv/round_32.c ++++ b/gcc/testsuite/gcc.target/riscv/round_32.c +@@ -1,4 +1,5 @@ + /* { dg-do compile { target { riscv32*-*-* } } } */ ++/* { dg-require-effective-target glibc } */ + /* { dg-options "-march=rv32gc -mabi=ilp32d -fno-math-errno -funsafe-math-optimizations -fno-inline" } */ + /* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/round_64.c b/gcc/testsuite/gcc.target/riscv/round_64.c +index e79690979a5..5e13bccdcd2 100644 +--- a/gcc/testsuite/gcc.target/riscv/round_64.c ++++ b/gcc/testsuite/gcc.target/riscv/round_64.c +@@ -1,4 +1,5 @@ + /* { dg-do compile { target { riscv64*-*-* } } } */ ++/* { dg-require-effective-target glibc } */ + /* { dg-options "-march=rv64gc -mabi=lp64d -fno-math-errno -funsafe-math-optimizations -fno-inline" } */ + /* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ + +-- +2.47.3 + diff --git a/1027-RISC-V-miscll-comment-fixes-NFC.patch b/1027-RISC-V-miscll-comment-fixes-NFC.patch new file mode 100644 index 0000000..d090870 --- /dev/null +++ b/1027-RISC-V-miscll-comment-fixes-NFC.patch @@ -0,0 +1,59 @@ +From 7a6d90623adf0de8f4089dfbda697e414c674211 Mon Sep 17 00:00:00 2001 +From: Vineet Gupta +Date: Tue, 1 Mar 2022 03:45:19 -0800 +Subject: [PATCH 1027/1087] RISC-V: miscll comment fixes [NFC] + +commit upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +gcc/ChangeLog: + * config/riscv/riscv.cc: Comment updates. + * config/riscv/riscv.h: Ditto. + +Signed-off-by: Vineet Gupta +--- + gcc/config/riscv/riscv.cc | 6 ++++-- + gcc/config/riscv/riscv.h | 2 +- + 2 files changed, 5 insertions(+), 3 deletions(-) + +diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc +index 62e733175df..cbcd95c43b5 100644 +--- a/gcc/config/riscv/riscv.cc ++++ b/gcc/config/riscv/riscv.cc +@@ -1280,7 +1280,9 @@ riscv_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x) + return riscv_const_insns (x) > 0; + } + +-/* Implement TARGET_CANNOT_FORCE_CONST_MEM. */ ++/* Implement TARGET_CANNOT_FORCE_CONST_MEM. ++ Return true if X cannot (or should not) be spilled to the ++ constant pool. */ + + static bool + riscv_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x) +@@ -8651,7 +8653,7 @@ riscv_modes_tieable_p (machine_mode mode1, machine_mode mode2) + && GET_MODE_CLASS (mode2) == MODE_FLOAT)); + } + +-/* Implement CLASS_MAX_NREGS. */ ++/* Implement TARGET_CLASS_MAX_NREGS. */ + + static unsigned char + riscv_class_max_nregs (reg_class_t rclass, machine_mode mode) +diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h +index 35953dab924..9bd5b26cb2f 100644 +--- a/gcc/config/riscv/riscv.h ++++ b/gcc/config/riscv/riscv.h +@@ -315,7 +315,7 @@ ASM_MISA_SPEC + - FRAME_POINTER_REGNUM + - 1 vl register + - 1 vtype register +- - 30 unused registers for future expansion ++ - 28 unused registers for future expansion + - 32 vector registers */ + + #define FIRST_PSEUDO_REGISTER 128 +-- +2.47.3 + diff --git a/1028-So-another-constant-synthesis-improvement.patch b/1028-So-another-constant-synthesis-improvement.patch new file mode 100644 index 0000000..e9d3c1e --- /dev/null +++ b/1028-So-another-constant-synthesis-improvement.patch @@ -0,0 +1,1708 @@ +From 1fe86ef245c948679a653b7d7ca9a46266543db1 Mon Sep 17 00:00:00 2001 +From: Jeff Law +Date: Mon, 6 May 2024 15:27:43 -0600 +Subject: [PATCH 1028/1087] So another constant synthesis improvement. + +commit 975bb17e2f6bc90d366237ab1c5dc9b8df2dee69 upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +In this patch we're looking at cases where we'd like to be able to use +lui+slli, but can't because of the sign extending nature of lui on +TARGET_64BIT. For example: 0x8001100000020UL. The trunk currently generates 4 +instructions for that constant, when it can be done with 3 (lui+slli.uw+addi). + +When Zba is enabled, we can use lui+slli.uw as the slli.uw masks off the bits +32..63 before shifting, giving us the precise semantics we want. + +I strongly suspect we'll want to do the same for a set of constants with +lui+add.uw, lui+shNadd.uw, so you'll see the beginnings of generalizing support +for lui followed by a "uw" instruction. + +The new test just tests the set of cases that showed up while exploring a +particular space of the constant synthesis problem. It's not meant to be +exhaustive (failure to use shadd when profitable). + +gcc/ + + * config/riscv/riscv.cc (riscv_integer_op): Add field tracking if we + want to use a "uw" instruction variant. + (riscv_build_integer_1): Initialize the new field in various places. + Use lui+slli.uw for some constants. + (riscv_move_integer): Handle slli.uw. + +gcc/testsuite/ + + * gcc.target/riscv/synthesis-2.c: New test. +--- + gcc/config/riscv/riscv.cc | 60 +- + gcc/testsuite/gcc.target/riscv/synthesis-2.c | 1481 ++++++++++++++++++ + 2 files changed, 1539 insertions(+), 2 deletions(-) + create mode 100644 gcc/testsuite/gcc.target/riscv/synthesis-2.c + +diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc +index cbcd95c43b5..b6239c38582 100644 +--- a/gcc/config/riscv/riscv.cc ++++ b/gcc/config/riscv/riscv.cc +@@ -249,6 +249,7 @@ struct riscv_arg_info { + where A is an accumulator, each CODE[i] is a binary rtl operation + and each VALUE[i] is a constant integer. CODE[0] is undefined. */ + struct riscv_integer_op { ++ bool use_uw; + enum rtx_code code; + unsigned HOST_WIDE_INT value; + }; +@@ -756,6 +757,7 @@ riscv_build_integer_1 (struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS], + /* Simply ADDI or LUI. */ + codes[0].code = UNKNOWN; + codes[0].value = value; ++ codes[0].use_uw = false; + return 1; + } + if (TARGET_ZBS && SINGLE_BIT_MASK_OPERAND (value)) +@@ -763,6 +765,7 @@ riscv_build_integer_1 (struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS], + /* Simply BSETI. */ + codes[0].code = UNKNOWN; + codes[0].value = value; ++ codes[0].use_uw = false; + + /* RISC-V sign-extends all 32bit values that live in a 32bit + register. To avoid paradoxes, we thus need to use the +@@ -791,6 +794,7 @@ riscv_build_integer_1 (struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS], + { + alt_codes[alt_cost-1].code = PLUS; + alt_codes[alt_cost-1].value = low_part; ++ alt_codes[alt_cost-1].use_uw = false; + memcpy (codes, alt_codes, sizeof (alt_codes)); + cost = alt_cost; + } +@@ -804,6 +808,7 @@ riscv_build_integer_1 (struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS], + { + alt_codes[alt_cost-1].code = XOR; + alt_codes[alt_cost-1].value = low_part; ++ alt_codes[alt_cost-1].use_uw = false; + memcpy (codes, alt_codes, sizeof (alt_codes)); + cost = alt_cost; + } +@@ -814,17 +819,37 @@ riscv_build_integer_1 (struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS], + { + int shift = ctz_hwi (value); + unsigned HOST_WIDE_INT x = value; ++ bool use_uw = false; + x = sext_hwi (x >> shift, HOST_BITS_PER_WIDE_INT - shift); + + /* Don't eliminate the lower 12 bits if LUI might apply. */ +- if (shift > IMM_BITS && !SMALL_OPERAND (x) && LUI_OPERAND (x << IMM_BITS)) ++ if (shift > IMM_BITS ++ && !SMALL_OPERAND (x) ++ && (LUI_OPERAND (x << IMM_BITS) ++ || (TARGET_64BIT ++ && TARGET_ZBA ++ && LUI_OPERAND ((x << IMM_BITS) ++ & ~HOST_WIDE_INT_C (0x80000000))))) + shift -= IMM_BITS, x <<= IMM_BITS; + ++ /* Adjust X if it isn't a LUI operand in isolation, but we can use ++ a subsequent "uw" instruction form to mask off the undesirable ++ bits. */ ++ if (!LUI_OPERAND (x) ++ && TARGET_64BIT ++ && TARGET_ZBA ++ && LUI_OPERAND (x & ~HOST_WIDE_INT_C (0x80000000UL))) ++ { ++ x = sext_hwi (x, 32); ++ use_uw = true; ++ } ++ + alt_cost = 1 + riscv_build_integer_1 (alt_codes, x, mode); + if (alt_cost < cost) + { + alt_codes[alt_cost-1].code = ASHIFT; + alt_codes[alt_cost-1].value = shift; ++ alt_codes[alt_cost-1].use_uw = use_uw; + memcpy (codes, alt_codes, sizeof (alt_codes)); + cost = alt_cost; + } +@@ -845,8 +870,10 @@ riscv_build_integer_1 (struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS], + /* The sign-bit might be zero, so just rotate to be safe. */ + codes[0].value = (((unsigned HOST_WIDE_INT) value >> trailing_ones) + | (value << (64 - trailing_ones))); ++ codes[0].use_uw = false; + codes[1].code = ROTATERT; + codes[1].value = 64 - trailing_ones; ++ codes[1].use_uw = false; + cost = 2; + } + /* Handle the case where the 11 bit range of zero bits wraps around. */ +@@ -858,8 +885,10 @@ riscv_build_integer_1 (struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS], + codes[0].value = ((value << (32 - upper_trailing_ones)) + | ((unsigned HOST_WIDE_INT) value + >> (32 + upper_trailing_ones))); ++ codes[0].use_uw = false; + codes[1].code = ROTATERT; + codes[1].value = 32 - upper_trailing_ones; ++ codes[1].use_uw = false; + cost = 2; + } + /* Final cases, particularly focused on bseti. */ +@@ -873,6 +902,7 @@ riscv_build_integer_1 (struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS], + { + alt_codes[i].code = (i == 0 ? UNKNOWN : IOR); + alt_codes[i].value = value & 0x7ffff800; ++ alt_codes[i].use_uw = false; + value &= ~0x7ffff800; + i++; + } +@@ -882,6 +912,7 @@ riscv_build_integer_1 (struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS], + { + alt_codes[i].code = (i == 0 ? UNKNOWN : PLUS); + alt_codes[i].value = value & 0x7ff; ++ alt_codes[i].use_uw = false; + value &= ~0x7ff; + i++; + } +@@ -892,6 +923,7 @@ riscv_build_integer_1 (struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS], + HOST_WIDE_INT bit = ctz_hwi (value); + alt_codes[i].code = (i == 0 ? UNKNOWN : IOR); + alt_codes[i].value = 1UL << bit; ++ alt_codes[i].use_uw = false; + value &= ~(1ULL << bit); + i++; + } +@@ -933,6 +965,7 @@ riscv_build_integer (struct riscv_integer_op *codes, HOST_WIDE_INT value, + { + alt_codes[alt_cost-1].code = LSHIFTRT; + alt_codes[alt_cost-1].value = shift; ++ alt_codes[alt_cost-1].use_uw = false; + memcpy (codes, alt_codes, sizeof (alt_codes)); + cost = alt_cost; + } +@@ -944,6 +977,7 @@ riscv_build_integer (struct riscv_integer_op *codes, HOST_WIDE_INT value, + { + alt_codes[alt_cost-1].code = LSHIFTRT; + alt_codes[alt_cost-1].value = shift; ++ alt_codes[alt_cost-1].use_uw = false; + memcpy (codes, alt_codes, sizeof (alt_codes)); + cost = alt_cost; + } +@@ -2500,7 +2534,29 @@ riscv_move_integer (rtx temp, rtx dest, HOST_WIDE_INT value, + else + x = force_reg (mode, x); + codes[i].value = trunc_int_for_mode (codes[i].value, mode); +- x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value)); ++ /* If the sequence requires using a "uw" form of an insn, we're ++ going to have to construct the RTL ourselves and put it in ++ a register to avoid force_reg/force_operand from mucking things ++ up. */ ++ if (codes[i].use_uw) ++ { ++ gcc_assert (TARGET_64BIT || TARGET_ZBA); ++ rtx t = can_create_pseudo_p () ? gen_reg_rtx (mode) : temp; ++ ++ /* Create the proper mask for the slli.uw instruction. */ ++ unsigned HOST_WIDE_INT value = 0xffffffff; ++ value <<= codes[i].value; ++ ++ /* Right now the only "uw" form we use is slli, we may add more ++ in the future. */ ++ x = gen_rtx_fmt_ee (codes[i].code, mode, ++ x, GEN_INT (codes[i].value)); ++ x = gen_rtx_fmt_ee (AND, mode, x, GEN_INT (value)); ++ x = riscv_emit_set (t, x); ++ } ++ else ++ x = gen_rtx_fmt_ee (codes[i].code, mode, ++ x, GEN_INT (codes[i].value)); + } + } + +diff --git a/gcc/testsuite/gcc.target/riscv/synthesis-2.c b/gcc/testsuite/gcc.target/riscv/synthesis-2.c +new file mode 100644 +index 00000000000..b88374da3c4 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/synthesis-2.c +@@ -0,0 +1,1481 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target rv64 } */ ++/* We aggressively skip as we really just need to test the basic synthesis ++ which shouldn't vary based on the optimization level. -O1 seems to work ++ and eliminates the usual sources of extraneous dead code that would throw ++ off the counts. */ ++/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O2" "-O3" "-Os" "-Oz" "-flto" } } */ ++/* { dg-options "-march=rv64gc_zba_zbb_zbs" } */ ++ ++/* All these cases have the same form. lui+slli.uw+addi ++/* { dg-final { scan-assembler-times "\\tadd" 367 } } */ ++/* { dg-final { scan-assembler-times "\\tslli.uw" 367 } } */ ++/* { dg-final { scan-assembler-times "\\taddi" 367 } } */ ++ ++unsigned long foo_0x480008001(void) { ++ return 0x480008001UL; ++} ++ ++unsigned long foo_0x1080020001(void) { ++ return 0x1080020001UL; ++} ++ ++unsigned long foo_0x2800040001(void) { ++ return 0x2800040001UL; ++} ++ ++unsigned long foo_0x4080080001(void) { ++ return 0x4080080001UL; ++} ++ ++unsigned long foo_0x6000080001(void) { ++ return 0x6000080001UL; ++} ++ ++unsigned long foo_0x8800100001(void) { ++ return 0x8800100001UL; ++} ++ ++unsigned long foo_0x10080200001(void) { ++ return 0x10080200001UL; ++} ++ ++unsigned long foo_0x12000200001(void) { ++ return 0x12000200001UL; ++} ++ ++unsigned long foo_0x20800400001(void) { ++ return 0x20800400001UL; ++} ++ ++unsigned long foo_0x40080800001(void) { ++ return 0x40080800001UL; ++} ++ ++unsigned long foo_0x42000800001(void) { ++ return 0x42000800001UL; ++} ++ ++unsigned long foo_0x80801000001(void) { ++ return 0x80801000001UL; ++} ++ ++unsigned long foo_0xa0001000001(void) { ++ return 0xa0001000001UL; ++} ++ ++unsigned long foo_0x100082000001(void) { ++ return 0x100082000001UL; ++} ++ ++unsigned long foo_0x102002000001(void) { ++ return 0x102002000001UL; ++} ++ ++unsigned long foo_0x180002000001(void) { ++ return 0x180002000001UL; ++} ++ ++unsigned long foo_0x200804000001(void) { ++ return 0x200804000001UL; ++} ++ ++unsigned long foo_0x220004000001(void) { ++ return 0x220004000001UL; ++} ++ ++unsigned long foo_0x400088000001(void) { ++ return 0x400088000001UL; ++} ++ ++unsigned long foo_0x402008000001(void) { ++ return 0x402008000001UL; ++} ++ ++unsigned long foo_0x480008000001(void) { ++ return 0x480008000001UL; ++} ++ ++unsigned long foo_0x800810000001(void) { ++ return 0x800810000001UL; ++} ++ ++unsigned long foo_0x820010000001(void) { ++ return 0x820010000001UL; ++} ++ ++unsigned long foo_0x10000a0000001(void) { ++ return 0x10000a0000001UL; ++} ++ ++unsigned long foo_0x1002020000001(void) { ++ return 0x1002020000001UL; ++} ++ ++unsigned long foo_0x1080020000001(void) { ++ return 0x1080020000001UL; ++} ++ ++unsigned long foo_0x2000840000001(void) { ++ return 0x2000840000001UL; ++} ++ ++unsigned long foo_0x2020040000001(void) { ++ return 0x2020040000001UL; ++} ++ ++unsigned long foo_0x2800040000001(void) { ++ return 0x2800040000001UL; ++} ++ ++unsigned long foo_0x4002080000001(void) { ++ return 0x4002080000001UL; ++} ++ ++unsigned long foo_0x4080080000001(void) { ++ return 0x4080080000001UL; ++} ++ ++unsigned long foo_0x6000080000001(void) { ++ return 0x6000080000001UL; ++} ++ ++unsigned long foo_0x8000900000001(void) { ++ return 0x8000900000001UL; ++} ++ ++unsigned long foo_0x8020100000001(void) { ++ return 0x8020100000001UL; ++} ++ ++unsigned long foo_0x8800100000001(void) { ++ return 0x8800100000001UL; ++} ++ ++unsigned long foo_0x10002200000001(void) { ++ return 0x10002200000001UL; ++} ++ ++unsigned long foo_0x10080200000001(void) { ++ return 0x10080200000001UL; ++} ++ ++unsigned long foo_0x12000200000001(void) { ++ return 0x12000200000001UL; ++} ++ ++unsigned long foo_0x20000c00000001(void) { ++ return 0x20000c00000001UL; ++} ++ ++unsigned long foo_0x20020400000001(void) { ++ return 0x20020400000001UL; ++} ++ ++unsigned long foo_0x20800400000001(void) { ++ return 0x20800400000001UL; ++} ++ ++unsigned long foo_0x40002800000001(void) { ++ return 0x40002800000001UL; ++} ++ ++unsigned long foo_0x40080800000001(void) { ++ return 0x40080800000001UL; ++} ++ ++unsigned long foo_0x42000800000001(void) { ++ return 0x42000800000001UL; ++} ++ ++unsigned long foo_0x80021000000001(void) { ++ return 0x80021000000001UL; ++} ++ ++unsigned long foo_0x80801000000001(void) { ++ return 0x80801000000001UL; ++} ++ ++unsigned long foo_0xa0001000000001(void) { ++ return 0xa0001000000001UL; ++} ++ ++unsigned long foo_0x100082000000001(void) { ++ return 0x100082000000001UL; ++} ++ ++unsigned long foo_0x102002000000001(void) { ++ return 0x102002000000001UL; ++} ++ ++unsigned long foo_0x180002000000001(void) { ++ return 0x180002000000001UL; ++} ++ ++unsigned long foo_0x200024000000001(void) { ++ return 0x200024000000001UL; ++} ++ ++unsigned long foo_0x200804000000001(void) { ++ return 0x200804000000001UL; ++} ++ ++unsigned long foo_0x220004000000001(void) { ++ return 0x220004000000001UL; ++} ++ ++unsigned long foo_0x400088000000001(void) { ++ return 0x400088000000001UL; ++} ++ ++unsigned long foo_0x402008000000001(void) { ++ return 0x402008000000001UL; ++} ++ ++unsigned long foo_0x480008000000001(void) { ++ return 0x480008000000001UL; ++} ++ ++unsigned long foo_0x800030000000001(void) { ++ return 0x800030000000001UL; ++} ++ ++unsigned long foo_0x800810000000001(void) { ++ return 0x800810000000001UL; ++} ++ ++unsigned long foo_0x820010000000001(void) { ++ return 0x820010000000001UL; ++} ++ ++unsigned long foo_0x10000a0000000001(void) { ++ return 0x10000a0000000001UL; ++} ++ ++unsigned long foo_0x1002020000000001(void) { ++ return 0x1002020000000001UL; ++} ++ ++unsigned long foo_0x1080020000000001(void) { ++ return 0x1080020000000001UL; ++} ++ ++unsigned long foo_0x2000840000000001(void) { ++ return 0x2000840000000001UL; ++} ++ ++unsigned long foo_0x2020040000000001(void) { ++ return 0x2020040000000001UL; ++} ++ ++unsigned long foo_0x2800040000000001(void) { ++ return 0x2800040000000001UL; ++} ++ ++unsigned long foo_0x4002080000000001(void) { ++ return 0x4002080000000001UL; ++} ++ ++unsigned long foo_0x4080080000000001(void) { ++ return 0x4080080000000001UL; ++} ++ ++unsigned long foo_0x6000080000000001(void) { ++ return 0x6000080000000001UL; ++} ++ ++unsigned long foo_0x900010002(void) { ++ return 0x900010002UL; ++} ++ ++unsigned long foo_0x2100040002(void) { ++ return 0x2100040002UL; ++} ++ ++unsigned long foo_0x5000080002(void) { ++ return 0x5000080002UL; ++} ++ ++unsigned long foo_0x8100100002(void) { ++ return 0x8100100002UL; ++} ++ ++unsigned long foo_0xc000100002(void) { ++ return 0xc000100002UL; ++} ++ ++unsigned long foo_0x11000200002(void) { ++ return 0x11000200002UL; ++} ++ ++unsigned long foo_0x20100400002(void) { ++ return 0x20100400002UL; ++} ++ ++unsigned long foo_0x24000400002(void) { ++ return 0x24000400002UL; ++} ++ ++unsigned long foo_0x41000800002(void) { ++ return 0x41000800002UL; ++} ++ ++unsigned long foo_0x80101000002(void) { ++ return 0x80101000002UL; ++} ++ ++unsigned long foo_0x84001000002(void) { ++ return 0x84001000002UL; ++} ++ ++unsigned long foo_0x101002000002(void) { ++ return 0x101002000002UL; ++} ++ ++unsigned long foo_0x140002000002(void) { ++ return 0x140002000002UL; ++} ++ ++unsigned long foo_0x200104000002(void) { ++ return 0x200104000002UL; ++} ++ ++unsigned long foo_0x204004000002(void) { ++ return 0x204004000002UL; ++} ++ ++unsigned long foo_0x300004000002(void) { ++ return 0x300004000002UL; ++} ++ ++unsigned long foo_0x401008000002(void) { ++ return 0x401008000002UL; ++} ++ ++unsigned long foo_0x440008000002(void) { ++ return 0x440008000002UL; ++} ++ ++unsigned long foo_0x800110000002(void) { ++ return 0x800110000002UL; ++} ++ ++unsigned long foo_0x804010000002(void) { ++ return 0x804010000002UL; ++} ++ ++unsigned long foo_0x900010000002(void) { ++ return 0x900010000002UL; ++} ++ ++unsigned long foo_0x1001020000002(void) { ++ return 0x1001020000002UL; ++} ++ ++unsigned long foo_0x1040020000002(void) { ++ return 0x1040020000002UL; ++} ++ ++unsigned long foo_0x2000140000002(void) { ++ return 0x2000140000002UL; ++} ++ ++unsigned long foo_0x2004040000002(void) { ++ return 0x2004040000002UL; ++} ++ ++unsigned long foo_0x2100040000002(void) { ++ return 0x2100040000002UL; ++} ++ ++unsigned long foo_0x4001080000002(void) { ++ return 0x4001080000002UL; ++} ++ ++unsigned long foo_0x4040080000002(void) { ++ return 0x4040080000002UL; ++} ++ ++unsigned long foo_0x5000080000002(void) { ++ return 0x5000080000002UL; ++} ++ ++unsigned long foo_0x8004100000002(void) { ++ return 0x8004100000002UL; ++} ++ ++unsigned long foo_0x8100100000002(void) { ++ return 0x8100100000002UL; ++} ++ ++unsigned long foo_0xc000100000002(void) { ++ return 0xc000100000002UL; ++} ++ ++unsigned long foo_0x10001200000002(void) { ++ return 0x10001200000002UL; ++} ++ ++unsigned long foo_0x10040200000002(void) { ++ return 0x10040200000002UL; ++} ++ ++unsigned long foo_0x11000200000002(void) { ++ return 0x11000200000002UL; ++} ++ ++unsigned long foo_0x20004400000002(void) { ++ return 0x20004400000002UL; ++} ++ ++unsigned long foo_0x20100400000002(void) { ++ return 0x20100400000002UL; ++} ++ ++unsigned long foo_0x24000400000002(void) { ++ return 0x24000400000002UL; ++} ++ ++unsigned long foo_0x40001800000002(void) { ++ return 0x40001800000002UL; ++} ++ ++unsigned long foo_0x40040800000002(void) { ++ return 0x40040800000002UL; ++} ++ ++unsigned long foo_0x41000800000002(void) { ++ return 0x41000800000002UL; ++} ++ ++unsigned long foo_0x80005000000002(void) { ++ return 0x80005000000002UL; ++} ++ ++unsigned long foo_0x80101000000002(void) { ++ return 0x80101000000002UL; ++} ++ ++unsigned long foo_0x84001000000002(void) { ++ return 0x84001000000002UL; ++} ++ ++unsigned long foo_0x100042000000002(void) { ++ return 0x100042000000002UL; ++} ++ ++unsigned long foo_0x101002000000002(void) { ++ return 0x101002000000002UL; ++} ++ ++unsigned long foo_0x140002000000002(void) { ++ return 0x140002000000002UL; ++} ++ ++unsigned long foo_0x200104000000002(void) { ++ return 0x200104000000002UL; ++} ++ ++unsigned long foo_0x204004000000002(void) { ++ return 0x204004000000002UL; ++} ++ ++unsigned long foo_0x300004000000002(void) { ++ return 0x300004000000002UL; ++} ++ ++unsigned long foo_0x400048000000002(void) { ++ return 0x400048000000002UL; ++} ++ ++unsigned long foo_0x401008000000002(void) { ++ return 0x401008000000002UL; ++} ++ ++unsigned long foo_0x440008000000002(void) { ++ return 0x440008000000002UL; ++} ++ ++unsigned long foo_0x800110000000002(void) { ++ return 0x800110000000002UL; ++} ++ ++unsigned long foo_0x804010000000002(void) { ++ return 0x804010000000002UL; ++} ++ ++unsigned long foo_0x900010000000002(void) { ++ return 0x900010000000002UL; ++} ++ ++unsigned long foo_0x1000060000000002(void) { ++ return 0x1000060000000002UL; ++} ++ ++unsigned long foo_0x1001020000000002(void) { ++ return 0x1001020000000002UL; ++} ++ ++unsigned long foo_0x1040020000000002(void) { ++ return 0x1040020000000002UL; ++} ++ ++unsigned long foo_0x2000140000000002(void) { ++ return 0x2000140000000002UL; ++} ++ ++unsigned long foo_0x2004040000000002(void) { ++ return 0x2004040000000002UL; ++} ++ ++unsigned long foo_0x2100040000000002(void) { ++ return 0x2100040000000002UL; ++} ++ ++unsigned long foo_0x4001080000000002(void) { ++ return 0x4001080000000002UL; ++} ++ ++unsigned long foo_0x4040080000000002(void) { ++ return 0x4040080000000002UL; ++} ++ ++unsigned long foo_0x5000080000000002(void) { ++ return 0x5000080000000002UL; ++} ++ ++unsigned long foo_0x600008004(void) { ++ return 0x600008004UL; ++} ++ ++unsigned long foo_0x880010004(void) { ++ return 0x880010004UL; ++} ++ ++unsigned long foo_0x1200020004(void) { ++ return 0x1200020004UL; ++} ++ ++unsigned long foo_0x2080040004(void) { ++ return 0x2080040004UL; ++} ++ ++unsigned long foo_0x4200080004(void) { ++ return 0x4200080004UL; ++} ++ ++unsigned long foo_0x8080100004(void) { ++ return 0x8080100004UL; ++} ++ ++unsigned long foo_0xa000100004(void) { ++ return 0xa000100004UL; ++} ++ ++unsigned long foo_0x10200200004(void) { ++ return 0x10200200004UL; ++} ++ ++unsigned long foo_0x18000200004(void) { ++ return 0x18000200004UL; ++} ++ ++unsigned long foo_0x20080400004(void) { ++ return 0x20080400004UL; ++} ++ ++unsigned long foo_0x22000400004(void) { ++ return 0x22000400004UL; ++} ++ ++unsigned long foo_0x40200800004(void) { ++ return 0x40200800004UL; ++} ++ ++unsigned long foo_0x48000800004(void) { ++ return 0x48000800004UL; ++} ++ ++unsigned long foo_0x80081000004(void) { ++ return 0x80081000004UL; ++} ++ ++unsigned long foo_0x82001000004(void) { ++ return 0x82001000004UL; ++} ++ ++unsigned long foo_0x100202000004(void) { ++ return 0x100202000004UL; ++} ++ ++unsigned long foo_0x108002000004(void) { ++ return 0x108002000004UL; ++} ++ ++unsigned long foo_0x200084000004(void) { ++ return 0x200084000004UL; ++} ++ ++unsigned long foo_0x202004000004(void) { ++ return 0x202004000004UL; ++} ++ ++unsigned long foo_0x280004000004(void) { ++ return 0x280004000004UL; ++} ++ ++unsigned long foo_0x400208000004(void) { ++ return 0x400208000004UL; ++} ++ ++unsigned long foo_0x408008000004(void) { ++ return 0x408008000004UL; ++} ++ ++unsigned long foo_0x600008000004(void) { ++ return 0x600008000004UL; ++} ++ ++unsigned long foo_0x800090000004(void) { ++ return 0x800090000004UL; ++} ++ ++unsigned long foo_0x802010000004(void) { ++ return 0x802010000004UL; ++} ++ ++unsigned long foo_0x880010000004(void) { ++ return 0x880010000004UL; ++} ++ ++unsigned long foo_0x1000220000004(void) { ++ return 0x1000220000004UL; ++} ++ ++unsigned long foo_0x1008020000004(void) { ++ return 0x1008020000004UL; ++} ++ ++unsigned long foo_0x1200020000004(void) { ++ return 0x1200020000004UL; ++} ++ ++unsigned long foo_0x20000c0000004(void) { ++ return 0x20000c0000004UL; ++} ++ ++unsigned long foo_0x2002040000004(void) { ++ return 0x2002040000004UL; ++} ++ ++unsigned long foo_0x2080040000004(void) { ++ return 0x2080040000004UL; ++} ++ ++unsigned long foo_0x4000280000004(void) { ++ return 0x4000280000004UL; ++} ++ ++unsigned long foo_0x4008080000004(void) { ++ return 0x4008080000004UL; ++} ++ ++unsigned long foo_0x4200080000004(void) { ++ return 0x4200080000004UL; ++} ++ ++unsigned long foo_0x8002100000004(void) { ++ return 0x8002100000004UL; ++} ++ ++unsigned long foo_0x8080100000004(void) { ++ return 0x8080100000004UL; ++} ++ ++unsigned long foo_0xa000100000004(void) { ++ return 0xa000100000004UL; ++} ++ ++unsigned long foo_0x10008200000004(void) { ++ return 0x10008200000004UL; ++} ++ ++unsigned long foo_0x10200200000004(void) { ++ return 0x10200200000004UL; ++} ++ ++unsigned long foo_0x18000200000004(void) { ++ return 0x18000200000004UL; ++} ++ ++unsigned long foo_0x20002400000004(void) { ++ return 0x20002400000004UL; ++} ++ ++unsigned long foo_0x20080400000004(void) { ++ return 0x20080400000004UL; ++} ++ ++unsigned long foo_0x22000400000004(void) { ++ return 0x22000400000004UL; ++} ++ ++unsigned long foo_0x40008800000004(void) { ++ return 0x40008800000004UL; ++} ++ ++unsigned long foo_0x40200800000004(void) { ++ return 0x40200800000004UL; ++} ++ ++unsigned long foo_0x48000800000004(void) { ++ return 0x48000800000004UL; ++} ++ ++unsigned long foo_0x80003000000004(void) { ++ return 0x80003000000004UL; ++} ++ ++unsigned long foo_0x80081000000004(void) { ++ return 0x80081000000004UL; ++} ++ ++unsigned long foo_0x82001000000004(void) { ++ return 0x82001000000004UL; ++} ++ ++unsigned long foo_0x10000a000000004(void) { ++ return 0x10000a000000004UL; ++} ++ ++unsigned long foo_0x100202000000004(void) { ++ return 0x100202000000004UL; ++} ++ ++unsigned long foo_0x108002000000004(void) { ++ return 0x108002000000004UL; ++} ++ ++unsigned long foo_0x200084000000004(void) { ++ return 0x200084000000004UL; ++} ++ ++unsigned long foo_0x202004000000004(void) { ++ return 0x202004000000004UL; ++} ++ ++unsigned long foo_0x280004000000004(void) { ++ return 0x280004000000004UL; ++} ++ ++unsigned long foo_0x400208000000004(void) { ++ return 0x400208000000004UL; ++} ++ ++unsigned long foo_0x408008000000004(void) { ++ return 0x408008000000004UL; ++} ++ ++unsigned long foo_0x600008000000004(void) { ++ return 0x600008000000004UL; ++} ++ ++unsigned long foo_0x800090000000004(void) { ++ return 0x800090000000004UL; ++} ++ ++unsigned long foo_0x802010000000004(void) { ++ return 0x802010000000004UL; ++} ++ ++unsigned long foo_0x880010000000004(void) { ++ return 0x880010000000004UL; ++} ++ ++unsigned long foo_0x1000220000000004(void) { ++ return 0x1000220000000004UL; ++} ++ ++unsigned long foo_0x1008020000000004(void) { ++ return 0x1008020000000004UL; ++} ++ ++unsigned long foo_0x1200020000000004(void) { ++ return 0x1200020000000004UL; ++} ++ ++unsigned long foo_0x20000c0000000004(void) { ++ return 0x20000c0000000004UL; ++} ++ ++unsigned long foo_0x2002040000000004(void) { ++ return 0x2002040000000004UL; ++} ++ ++unsigned long foo_0x2080040000000004(void) { ++ return 0x2080040000000004UL; ++} ++ ++unsigned long foo_0x4000280000000004(void) { ++ return 0x4000280000000004UL; ++} ++ ++unsigned long foo_0x4008080000000004(void) { ++ return 0x4008080000000004UL; ++} ++ ++unsigned long foo_0x4200080000000004(void) { ++ return 0x4200080000000004UL; ++} ++ ++unsigned long foo_0x500008008(void) { ++ return 0x500008008UL; ++} ++ ++unsigned long foo_0xc00010008(void) { ++ return 0xc00010008UL; ++} ++ ++unsigned long foo_0x1100020008(void) { ++ return 0x1100020008UL; ++} ++ ++unsigned long foo_0x2400040008(void) { ++ return 0x2400040008UL; ++} ++ ++unsigned long foo_0x4100080008(void) { ++ return 0x4100080008UL; ++} ++ ++unsigned long foo_0x8400100008(void) { ++ return 0x8400100008UL; ++} ++ ++unsigned long foo_0x10100200008(void) { ++ return 0x10100200008UL; ++} ++ ++unsigned long foo_0x14000200008(void) { ++ return 0x14000200008UL; ++} ++ ++unsigned long foo_0x20400400008(void) { ++ return 0x20400400008UL; ++} ++ ++unsigned long foo_0x30000400008(void) { ++ return 0x30000400008UL; ++} ++ ++unsigned long foo_0x40100800008(void) { ++ return 0x40100800008UL; ++} ++ ++unsigned long foo_0x44000800008(void) { ++ return 0x44000800008UL; ++} ++ ++unsigned long foo_0x80401000008(void) { ++ return 0x80401000008UL; ++} ++ ++unsigned long foo_0x90001000008(void) { ++ return 0x90001000008UL; ++} ++ ++unsigned long foo_0x100102000008(void) { ++ return 0x100102000008UL; ++} ++ ++unsigned long foo_0x104002000008(void) { ++ return 0x104002000008UL; ++} ++ ++unsigned long foo_0x200404000008(void) { ++ return 0x200404000008UL; ++} ++ ++unsigned long foo_0x210004000008(void) { ++ return 0x210004000008UL; ++} ++ ++unsigned long foo_0x400108000008(void) { ++ return 0x400108000008UL; ++} ++ ++unsigned long foo_0x404008000008(void) { ++ return 0x404008000008UL; ++} ++ ++unsigned long foo_0x500008000008(void) { ++ return 0x500008000008UL; ++} ++ ++unsigned long foo_0x800410000008(void) { ++ return 0x800410000008UL; ++} ++ ++unsigned long foo_0x810010000008(void) { ++ return 0x810010000008UL; ++} ++ ++unsigned long foo_0xc00010000008(void) { ++ return 0xc00010000008UL; ++} ++ ++unsigned long foo_0x1000120000008(void) { ++ return 0x1000120000008UL; ++} ++ ++unsigned long foo_0x1004020000008(void) { ++ return 0x1004020000008UL; ++} ++ ++unsigned long foo_0x1100020000008(void) { ++ return 0x1100020000008UL; ++} ++ ++unsigned long foo_0x2000440000008(void) { ++ return 0x2000440000008UL; ++} ++ ++unsigned long foo_0x2010040000008(void) { ++ return 0x2010040000008UL; ++} ++ ++unsigned long foo_0x2400040000008(void) { ++ return 0x2400040000008UL; ++} ++ ++unsigned long foo_0x4000180000008(void) { ++ return 0x4000180000008UL; ++} ++ ++unsigned long foo_0x4004080000008(void) { ++ return 0x4004080000008UL; ++} ++ ++unsigned long foo_0x4100080000008(void) { ++ return 0x4100080000008UL; ++} ++ ++unsigned long foo_0x8000500000008(void) { ++ return 0x8000500000008UL; ++} ++ ++unsigned long foo_0x8010100000008(void) { ++ return 0x8010100000008UL; ++} ++ ++unsigned long foo_0x8400100000008(void) { ++ return 0x8400100000008UL; ++} ++ ++unsigned long foo_0x10004200000008(void) { ++ return 0x10004200000008UL; ++} ++ ++unsigned long foo_0x10100200000008(void) { ++ return 0x10100200000008UL; ++} ++ ++unsigned long foo_0x14000200000008(void) { ++ return 0x14000200000008UL; ++} ++ ++unsigned long foo_0x20010400000008(void) { ++ return 0x20010400000008UL; ++} ++ ++unsigned long foo_0x20400400000008(void) { ++ return 0x20400400000008UL; ++} ++ ++unsigned long foo_0x30000400000008(void) { ++ return 0x30000400000008UL; ++} ++ ++unsigned long foo_0x40004800000008(void) { ++ return 0x40004800000008UL; ++} ++ ++unsigned long foo_0x40100800000008(void) { ++ return 0x40100800000008UL; ++} ++ ++unsigned long foo_0x44000800000008(void) { ++ return 0x44000800000008UL; ++} ++ ++unsigned long foo_0x80011000000008(void) { ++ return 0x80011000000008UL; ++} ++ ++unsigned long foo_0x80401000000008(void) { ++ return 0x80401000000008UL; ++} ++ ++unsigned long foo_0x90001000000008(void) { ++ return 0x90001000000008UL; ++} ++ ++unsigned long foo_0x100006000000008(void) { ++ return 0x100006000000008UL; ++} ++ ++unsigned long foo_0x100102000000008(void) { ++ return 0x100102000000008UL; ++} ++ ++unsigned long foo_0x104002000000008(void) { ++ return 0x104002000000008UL; ++} ++ ++unsigned long foo_0x200014000000008(void) { ++ return 0x200014000000008UL; ++} ++ ++unsigned long foo_0x200404000000008(void) { ++ return 0x200404000000008UL; ++} ++ ++unsigned long foo_0x210004000000008(void) { ++ return 0x210004000000008UL; ++} ++ ++unsigned long foo_0x400108000000008(void) { ++ return 0x400108000000008UL; ++} ++ ++unsigned long foo_0x404008000000008(void) { ++ return 0x404008000000008UL; ++} ++ ++unsigned long foo_0x500008000000008(void) { ++ return 0x500008000000008UL; ++} ++ ++unsigned long foo_0x800410000000008(void) { ++ return 0x800410000000008UL; ++} ++ ++unsigned long foo_0x810010000000008(void) { ++ return 0x810010000000008UL; ++} ++ ++unsigned long foo_0xc00010000000008(void) { ++ return 0xc00010000000008UL; ++} ++ ++unsigned long foo_0x1000120000000008(void) { ++ return 0x1000120000000008UL; ++} ++ ++unsigned long foo_0x1004020000000008(void) { ++ return 0x1004020000000008UL; ++} ++ ++unsigned long foo_0x1100020000000008(void) { ++ return 0x1100020000000008UL; ++} ++ ++unsigned long foo_0x2000440000000008(void) { ++ return 0x2000440000000008UL; ++} ++ ++unsigned long foo_0x2010040000000008(void) { ++ return 0x2010040000000008UL; ++} ++ ++unsigned long foo_0x2400040000000008(void) { ++ return 0x2400040000000008UL; ++} ++ ++unsigned long foo_0x4000180000000008(void) { ++ return 0x4000180000000008UL; ++} ++ ++unsigned long foo_0x4004080000000008(void) { ++ return 0x4004080000000008UL; ++} ++ ++unsigned long foo_0x4100080000000008(void) { ++ return 0x4100080000000008UL; ++} ++ ++unsigned long foo_0xa00010010(void) { ++ return 0xa00010010UL; ++} ++ ++unsigned long foo_0x1800020010(void) { ++ return 0x1800020010UL; ++} ++ ++unsigned long foo_0x2200040010(void) { ++ return 0x2200040010UL; ++} ++ ++unsigned long foo_0x4800080010(void) { ++ return 0x4800080010UL; ++} ++ ++unsigned long foo_0x8200100010(void) { ++ return 0x8200100010UL; ++} ++ ++unsigned long foo_0x10800200010(void) { ++ return 0x10800200010UL; ++} ++ ++unsigned long foo_0x20200400010(void) { ++ return 0x20200400010UL; ++} ++ ++unsigned long foo_0x28000400010(void) { ++ return 0x28000400010UL; ++} ++ ++unsigned long foo_0x40800800010(void) { ++ return 0x40800800010UL; ++} ++ ++unsigned long foo_0x60000800010(void) { ++ return 0x60000800010UL; ++} ++ ++unsigned long foo_0x80201000010(void) { ++ return 0x80201000010UL; ++} ++ ++unsigned long foo_0x88001000010(void) { ++ return 0x88001000010UL; ++} ++ ++unsigned long foo_0x100802000010(void) { ++ return 0x100802000010UL; ++} ++ ++unsigned long foo_0x120002000010(void) { ++ return 0x120002000010UL; ++} ++ ++unsigned long foo_0x200204000010(void) { ++ return 0x200204000010UL; ++} ++ ++unsigned long foo_0x208004000010(void) { ++ return 0x208004000010UL; ++} ++ ++unsigned long foo_0x400808000010(void) { ++ return 0x400808000010UL; ++} ++ ++unsigned long foo_0x420008000010(void) { ++ return 0x420008000010UL; ++} ++ ++unsigned long foo_0x800210000010(void) { ++ return 0x800210000010UL; ++} ++ ++unsigned long foo_0x808010000010(void) { ++ return 0x808010000010UL; ++} ++ ++unsigned long foo_0xa00010000010(void) { ++ return 0xa00010000010UL; ++} ++ ++unsigned long foo_0x1000820000010(void) { ++ return 0x1000820000010UL; ++} ++ ++unsigned long foo_0x1020020000010(void) { ++ return 0x1020020000010UL; ++} ++ ++unsigned long foo_0x1800020000010(void) { ++ return 0x1800020000010UL; ++} ++ ++unsigned long foo_0x2000240000010(void) { ++ return 0x2000240000010UL; ++} ++ ++unsigned long foo_0x2008040000010(void) { ++ return 0x2008040000010UL; ++} ++ ++unsigned long foo_0x2200040000010(void) { ++ return 0x2200040000010UL; ++} ++ ++unsigned long foo_0x4000880000010(void) { ++ return 0x4000880000010UL; ++} ++ ++unsigned long foo_0x4020080000010(void) { ++ return 0x4020080000010UL; ++} ++ ++unsigned long foo_0x4800080000010(void) { ++ return 0x4800080000010UL; ++} ++ ++unsigned long foo_0x8000300000010(void) { ++ return 0x8000300000010UL; ++} ++ ++unsigned long foo_0x8008100000010(void) { ++ return 0x8008100000010UL; ++} ++ ++unsigned long foo_0x8200100000010(void) { ++ return 0x8200100000010UL; ++} ++ ++unsigned long foo_0x10000a00000010(void) { ++ return 0x10000a00000010UL; ++} ++ ++unsigned long foo_0x10020200000010(void) { ++ return 0x10020200000010UL; ++} ++ ++unsigned long foo_0x10800200000010(void) { ++ return 0x10800200000010UL; ++} ++ ++unsigned long foo_0x20008400000010(void) { ++ return 0x20008400000010UL; ++} ++ ++unsigned long foo_0x20200400000010(void) { ++ return 0x20200400000010UL; ++} ++ ++unsigned long foo_0x28000400000010(void) { ++ return 0x28000400000010UL; ++} ++ ++unsigned long foo_0x40020800000010(void) { ++ return 0x40020800000010UL; ++} ++ ++unsigned long foo_0x40800800000010(void) { ++ return 0x40800800000010UL; ++} ++ ++unsigned long foo_0x60000800000010(void) { ++ return 0x60000800000010UL; ++} ++ ++unsigned long foo_0x80009000000010(void) { ++ return 0x80009000000010UL; ++} ++ ++unsigned long foo_0x80201000000010(void) { ++ return 0x80201000000010UL; ++} ++ ++unsigned long foo_0x88001000000010(void) { ++ return 0x88001000000010UL; ++} ++ ++unsigned long foo_0x100022000000010(void) { ++ return 0x100022000000010UL; ++} ++ ++unsigned long foo_0x100802000000010(void) { ++ return 0x100802000000010UL; ++} ++ ++unsigned long foo_0x120002000000010(void) { ++ return 0x120002000000010UL; ++} ++ ++unsigned long foo_0x20000c000000010(void) { ++ return 0x20000c000000010UL; ++} ++ ++unsigned long foo_0x200204000000010(void) { ++ return 0x200204000000010UL; ++} ++ ++unsigned long foo_0x208004000000010(void) { ++ return 0x208004000000010UL; ++} ++ ++unsigned long foo_0x400028000000010(void) { ++ return 0x400028000000010UL; ++} ++ ++unsigned long foo_0x400808000000010(void) { ++ return 0x400808000000010UL; ++} ++ ++unsigned long foo_0x420008000000010(void) { ++ return 0x420008000000010UL; ++} ++ ++unsigned long foo_0x800210000000010(void) { ++ return 0x800210000000010UL; ++} ++ ++unsigned long foo_0x808010000000010(void) { ++ return 0x808010000000010UL; ++} ++ ++unsigned long foo_0xa00010000000010(void) { ++ return 0xa00010000000010UL; ++} ++ ++unsigned long foo_0x1000820000000010(void) { ++ return 0x1000820000000010UL; ++} ++ ++unsigned long foo_0x1020020000000010(void) { ++ return 0x1020020000000010UL; ++} ++ ++unsigned long foo_0x1800020000000010(void) { ++ return 0x1800020000000010UL; ++} ++ ++unsigned long foo_0x2000240000000010(void) { ++ return 0x2000240000000010UL; ++} ++ ++unsigned long foo_0x2008040000000010(void) { ++ return 0x2008040000000010UL; ++} ++ ++unsigned long foo_0x2200040000000010(void) { ++ return 0x2200040000000010UL; ++} ++ ++unsigned long foo_0x4000880000000010(void) { ++ return 0x4000880000000010UL; ++} ++ ++unsigned long foo_0x4020080000000010(void) { ++ return 0x4020080000000010UL; ++} ++ ++unsigned long foo_0x4800080000000010(void) { ++ return 0x4800080000000010UL; ++} ++ ++unsigned long foo_0x1400020020(void) { ++ return 0x1400020020UL; ++} ++ ++unsigned long foo_0x3000040020(void) { ++ return 0x3000040020UL; ++} ++ ++unsigned long foo_0x4400080020(void) { ++ return 0x4400080020UL; ++} ++ ++unsigned long foo_0x9000100020(void) { ++ return 0x9000100020UL; ++} ++ ++unsigned long foo_0x10400200020(void) { ++ return 0x10400200020UL; ++} ++ ++unsigned long foo_0x21000400020(void) { ++ return 0x21000400020UL; ++} ++ ++unsigned long foo_0x40400800020(void) { ++ return 0x40400800020UL; ++} ++ ++unsigned long foo_0x50000800020(void) { ++ return 0x50000800020UL; ++} ++ ++unsigned long foo_0x81001000020(void) { ++ return 0x81001000020UL; ++} ++ ++unsigned long foo_0xc0001000020(void) { ++ return 0xc0001000020UL; ++} ++ ++unsigned long foo_0x100402000020(void) { ++ return 0x100402000020UL; ++} ++ ++unsigned long foo_0x110002000020(void) { ++ return 0x110002000020UL; ++} ++ ++unsigned long foo_0x201004000020(void) { ++ return 0x201004000020UL; ++} ++ ++unsigned long foo_0x240004000020(void) { ++ return 0x240004000020UL; ++} ++ ++unsigned long foo_0x400408000020(void) { ++ return 0x400408000020UL; ++} ++ ++unsigned long foo_0x410008000020(void) { ++ return 0x410008000020UL; ++} ++ ++unsigned long foo_0x801010000020(void) { ++ return 0x801010000020UL; ++} ++ ++unsigned long foo_0x840010000020(void) { ++ return 0x840010000020UL; ++} ++ ++unsigned long foo_0x1000420000020(void) { ++ return 0x1000420000020UL; ++} ++ ++unsigned long foo_0x1010020000020(void) { ++ return 0x1010020000020UL; ++} ++ ++unsigned long foo_0x1400020000020(void) { ++ return 0x1400020000020UL; ++} ++ ++unsigned long foo_0x2001040000020(void) { ++ return 0x2001040000020UL; ++} ++ ++unsigned long foo_0x2040040000020(void) { ++ return 0x2040040000020UL; ++} ++ ++unsigned long foo_0x3000040000020(void) { ++ return 0x3000040000020UL; ++} ++ ++unsigned long foo_0x4000480000020(void) { ++ return 0x4000480000020UL; ++} ++ ++unsigned long foo_0x4010080000020(void) { ++ return 0x4010080000020UL; ++} ++ ++unsigned long foo_0x4400080000020(void) { ++ return 0x4400080000020UL; ++} ++ ++unsigned long foo_0x8001100000020(void) { ++ return 0x8001100000020UL; ++} +-- +2.47.3 + diff --git a/1029-RISC-V-Document-mcmodel-large.patch b/1029-RISC-V-Document-mcmodel-large.patch new file mode 100644 index 0000000..fd7255b --- /dev/null +++ b/1029-RISC-V-Document-mcmodel-large.patch @@ -0,0 +1,46 @@ +From 961054ffcbbdca5541e745a66edd819d9137794d Mon Sep 17 00:00:00 2001 +From: Palmer Dabbelt +Date: Mon, 6 May 2024 15:34:26 -0600 +Subject: [PATCH 1029/1087] RISC-V: Document -mcmodel=large + +commit 6ffea3e37380860507cce08af42a997fbdb5d754 upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + + This slipped through the cracks. Probably also NEWS-worthy. + +gcc/ChangeLog: + + * doc/invoke.texi (RISC-V): Add -mcmodel=large. +--- + gcc/doc/invoke.texi | 7 ++++++- + 1 file changed, 6 insertions(+), 1 deletion(-) + +diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi +index 2df8555c625..d2ae11f0fd0 100644 +--- a/gcc/doc/invoke.texi ++++ b/gcc/doc/invoke.texi +@@ -1252,7 +1252,7 @@ See RS/6000 and PowerPC Options. + -msave-restore -mno-save-restore + -mshorten-memrefs -mno-shorten-memrefs + -mstrict-align -mno-strict-align +--mcmodel=medlow -mcmodel=medany ++-mcmodel=medlow -mcmodel=medany -mcmodel=large + -mexplicit-relocs -mno-explicit-relocs + -mrelax -mno-relax + -mriscv-attribute -mno-riscv-attribute +@@ -31156,6 +31156,11 @@ The code generated by the medium-any code model is position-independent, but is + not guaranteed to function correctly when linked into position-independent + executables or libraries. + ++@opindex -mcmodel=large ++@item -mcmodel=large ++Generate code for a large code model, which has no restrictions on size or ++placement of symbols. ++ + @item -mexplicit-relocs + @itemx -mno-exlicit-relocs + Use or do not use assembler relocation operators when dealing with symbolic +-- +2.47.3 + diff --git a/1030-Enable-inlining-str-by-default.patch b/1030-Enable-inlining-str-by-default.patch new file mode 100644 index 0000000..b5b19f9 --- /dev/null +++ b/1030-Enable-inlining-str-by-default.patch @@ -0,0 +1,106 @@ +From 7aca24f00ad7735785363d77cfab1b36e910e48a Mon Sep 17 00:00:00 2001 +From: Jeff Law +Date: Tue, 7 May 2024 11:43:09 -0600 +Subject: [PATCH 1030/1087] Enable inlining str* by default + +commit upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +So with Chrstoph's patches from late 2022 we've had the ability to inline +strlen, and str[n]cmp (scalar). However, we never actually turned this +capability on by default! + +This patch flips the those default to allow inlinining by default. It also +fixes one bug exposed by our internal testing when NBYTES is zero for strncmp. +I don't think that case happens enough to try and optimize it, we just disable +inline expansion for that instance. + +This has been bootstrapped and regression tested on rv64gc at various times as +well as cross tested on rv64gc more times than I can probably count (we've have +this patch internally for a while). More importantly, I just successfully +tested it on rv64gc and rv32gcv elf configurations with the trunk + +gcc/ + + * config/riscv/riscv-string.cc (riscv_expand_strcmp): Do not inline + strncmp with zero size. + (emit_strcmp_scalar_compare_subword): Adjust rotation for rv32 vs rv64. + * config/riscv/riscv.opt (var_inline_strcmp): Enable by default. + (vriscv_inline_strncmp, riscv_inline_strlen): Likewise. + +gcc/testsuite + + * gcc.target/riscv/zbb-strlen-disabled-2.c: Turn off inlining. +--- + gcc/config/riscv/riscv-string.cc | 9 ++++++++- + gcc/config/riscv/riscv.opt | 6 +++--- + gcc/testsuite/gcc.target/riscv/zbb-strlen-disabled-2.c | 4 ++-- + 3 files changed, 13 insertions(+), 6 deletions(-) + +diff --git a/gcc/config/riscv/riscv-string.cc b/gcc/config/riscv/riscv-string.cc +index 29c272850fa..7968fe8b8a6 100644 +--- a/gcc/config/riscv/riscv-string.cc ++++ b/gcc/config/riscv/riscv-string.cc +@@ -153,7 +153,7 @@ emit_strcmp_scalar_compare_subword (rtx data1, rtx data2, rtx orc1, + rtx imask = gen_rtx_CONST_INT (Xmode, im); + rtx m_reg = gen_reg_rtx (Xmode); + emit_insn (gen_rtx_SET (m_reg, imask)); +- do_rotr3 (m_reg, m_reg, GEN_INT (64 - cmp_bytes * BITS_PER_UNIT)); ++ do_rotr3 (m_reg, m_reg, GEN_INT (BITS_PER_WORD - cmp_bytes * BITS_PER_UNIT)); + do_and3 (data1, m_reg, data1); + do_and3 (data2, m_reg, data2); + if (TARGET_ZBB) +@@ -497,6 +497,13 @@ riscv_expand_strcmp (rtx result, rtx src1, rtx src2, + return false; + nbytes = UINTVAL (bytes_rtx); + ++ /* If NBYTES is zero the result of strncmp will always be zero, ++ but that would require special casing in the caller. So for ++ now just don't do an inline expansion. This probably rarely ++ happens in practice, but it is tested by the testsuite. */ ++ if (nbytes == 0) ++ return false; ++ + /* We don't emit parts of a strncmp() call. */ + if (nbytes > compare_max) + return false; +diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt +index 235166d4679..bdaa1c87cdc 100644 +--- a/gcc/config/riscv/riscv.opt ++++ b/gcc/config/riscv/riscv.opt +@@ -534,15 +534,15 @@ Target Var(TARGET_INLINE_SUBWORD_ATOMIC) Init(1) + Always inline subword atomic operations. + + minline-strcmp +-Target Var(riscv_inline_strcmp) Init(0) ++Target Var(riscv_inline_strcmp) Init(1) + Inline strcmp calls if possible. + + minline-strncmp +-Target Var(riscv_inline_strncmp) Init(0) ++Target Var(riscv_inline_strncmp) Init(1) + Inline strncmp calls if possible. + + minline-strlen +-Target Var(riscv_inline_strlen) Init(0) ++Target Var(riscv_inline_strlen) Init(1) + Inline strlen calls if possible. + + -param=riscv-strcmp-inline-limit= +diff --git a/gcc/testsuite/gcc.target/riscv/zbb-strlen-disabled-2.c b/gcc/testsuite/gcc.target/riscv/zbb-strlen-disabled-2.c +index a481068aa0c..1295aeb0086 100644 +--- a/gcc/testsuite/gcc.target/riscv/zbb-strlen-disabled-2.c ++++ b/gcc/testsuite/gcc.target/riscv/zbb-strlen-disabled-2.c +@@ -1,6 +1,6 @@ + /* { dg-do compile } */ +-/* { dg-options "-march=rv32gc_zbb" { target { rv32 } } } */ +-/* { dg-options "-march=rv64gc_zbb" { target { rv64 } } } */ ++/* { dg-options "-mno-inline-strlen -march=rv32gc_zbb" { target { rv32 } } } */ ++/* { dg-options "-mno-inline-strlen -march=rv64gc_zbb" { target { rv64 } } } */ + /* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Og" "-Oz" } } */ + + typedef long unsigned int size_t; +-- +2.47.3 + diff --git a/1031-Reassociate-constants-in-logical-ops.patch b/1031-Reassociate-constants-in-logical-ops.patch new file mode 100644 index 0000000..28e0b04 --- /dev/null +++ b/1031-Reassociate-constants-in-logical-ops.patch @@ -0,0 +1,120 @@ +From 86f73dddfd0105598ebdd574745d58f8f9248891 Mon Sep 17 00:00:00 2001 +From: Lyut Nersisyan +Date: Sun, 26 May 2024 21:24:40 -0600 +Subject: [PATCH 1031/1087] Reassociate constants in logical ops + +commit 160929406f0c44df5b0d377a014ebfe5027fe4e7 upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +This patch from Lyut will reassociate operands when we have shifted logical +operations. This can simplify a constant that may not be fit in a simm12 into +a form that does fit into a simm12. + +The basic work was done by Lyut. I generalized it to handle XOR/OR. + +It stands on its own, but also helps the upcoming Zbkb work from Lyut. + +This has survived Ventana's CI system as well as my tester. Obviously I'll +wait for a verdict from the Rivos CI system before moving forward. + +gcc/ + + * config/riscv/riscv.md (_shift_reverse): New pattern. + +gcc/testsuite + + * gcc.target/riscv/and-shift32.c: New test. + * gcc.target/riscv/and-shift64.c: New test. + + Co-authored-by: Jeffrey A Law +--- + gcc/config/riscv/riscv.md | 28 ++++++++++++++++++++ + gcc/testsuite/gcc.target/riscv/and-shift32.c | 13 +++++++++ + gcc/testsuite/gcc.target/riscv/and-shift64.c | 13 +++++++++ + 3 files changed, 54 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/riscv/and-shift32.c + create mode 100644 gcc/testsuite/gcc.target/riscv/and-shift64.c + +diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md +index 40bc0ab2295..e5e7cd80ef4 100644 +--- a/gcc/config/riscv/riscv.md ++++ b/gcc/config/riscv/riscv.md +@@ -2829,6 +2829,34 @@ + [(set_attr "type" "shift") + (set_attr "mode" "SI")]) + ++;; We can reassociate the shift and bitwise operator which may allow us to ++;; reduce the immediate operand of the bitwise operator into a range that ++;; fits in a simm12. ++;; ++;; We need to make sure that shifting does not lose any bits, particularly ++;; for IOR/XOR. It probably doesn't matter for AND. ++;; ++;; We also don't want to do this if the immediate already fits in a simm12 ++;; field. ++(define_insn_and_split "_shift_reverse" ++ [(set (match_operand:X 0 "register_operand" "=r") ++ (any_bitwise:X (ashift:X (match_operand:X 1 "register_operand" "r") ++ (match_operand 2 "immediate_operand" "n")) ++ (match_operand 3 "immediate_operand" "n")))] ++ "(!SMALL_OPERAND (INTVAL (operands[3])) ++ && SMALL_OPERAND (INTVAL (operands[3]) >> INTVAL (operands[2])) ++ && (popcount_hwi (INTVAL (operands[3])) ++ <= popcount_hwi (INTVAL (operands[3]) >> INTVAL (operands[2]))))" ++ "#" ++ "&& 1" ++ [(set (match_dup 0) (any_bitwise:X (match_dup 1) (match_dup 3))) ++ (set (match_dup 0) (ashift:X (match_dup 0) (match_dup 2)))] ++ { ++ operands[3] = GEN_INT (INTVAL (operands[3]) >> INTVAL (operands[2])); ++ } ++ [(set_attr "type" "shift") ++ (set_attr "mode" "")]) ++ + ;; Non-canonical, but can be formed by ree when combine is not successful at + ;; producing one of the two canonical patterns below. + (define_insn "*lshrsi3_zero_extend_1" +diff --git a/gcc/testsuite/gcc.target/riscv/and-shift32.c b/gcc/testsuite/gcc.target/riscv/and-shift32.c +new file mode 100644 +index 00000000000..38ee63e8d79 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/and-shift32.c +@@ -0,0 +1,13 @@ ++/* { dg-do compile } */ ++/* { dg-options "-march=rv32gc -mabi=ilp32" } */ ++/* { dg-skip-if "" { *-*-* } { "-O0" "-g" } } */ ++ ++int foo(int a) ++{ ++ return (a << 8) & 24320; ++} ++ ++/* { dg-final { scan-assembler-times "\\sandi\\s" 1 } } */ ++/* { dg-final { scan-assembler-times "\\sslli\\s" 1 } } */ ++/* { dg-final { scan-assembler-not "\\sli\\s" } } */ ++/* { dg-final { scan-assembler-not "\\saddi\\s" } } */ +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/riscv/and-shift64.c b/gcc/testsuite/gcc.target/riscv/and-shift64.c +new file mode 100644 +index 00000000000..ccfaedd508a +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/and-shift64.c +@@ -0,0 +1,13 @@ ++/* { dg-do compile } */ ++/* { dg-options "-march=rv64gc -mabi=lp64" } */ ++/* { dg-skip-if "" { *-*-* } { "-O0" "-g" } } */ ++ ++long long foo(long long a) ++{ ++ return (a << 8) & 24320; ++} ++ ++/* { dg-final { scan-assembler-times "\\sandi\\s" 1 } } */ ++/* { dg-final { scan-assembler-times "\\sslli\\s" 1 } } */ ++/* { dg-final { scan-assembler-not "\\sli\\s" } } */ ++/* { dg-final { scan-assembler-not "\\saddi\\s" } } */ +\ No newline at end of file +-- +2.47.3 + diff --git a/1032-Some-basic-patterns-for-zbkb-code-generation.patch b/1032-Some-basic-patterns-for-zbkb-code-generation.patch new file mode 100644 index 0000000..a3aa884 --- /dev/null +++ b/1032-Some-basic-patterns-for-zbkb-code-generation.patch @@ -0,0 +1,288 @@ +From b6e6400d078ee1187706a45cab9f499516f5cb62 Mon Sep 17 00:00:00 2001 +From: Lyut Nersisyan +Date: Tue, 28 May 2024 09:17:50 -0600 +Subject: [PATCH 1032/1087] Some basic patterns for zbkb code generation + +commit 236116068151bbc72aaaf53d0f223fe06f7e3bac upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +And here's Lyut's basic Zbkb support. Essentially it's four new patterns for +packh, packw, pack plus a bridge pattern needed for packh. + +packw is a bit ugly as we need to match a sign extension in an inconvenient +location. We pull it out so that the extension is exposed in a convenient +place for subsequent sign extension elimination. + +We need a bridge pattern to get packh. Thankfully the bridge pattern is a +degenerate packh where one operand is x0, so it works as-is without splitting +and provides the bridge to the more general form of packh. + +This patch also refines the condition for the constant reassociation patch to +avoid a few more cases than can be handled efficiently with other preexisting +patterns and one bugfix to avoid losing bits, particularly in the xor/ior case. + +Lyut did the core work here. I think I did some minor cleanups and the bridge +pattern to work with gcc-15 and beyond. + +This is a prerequisite for using zbkb in constant synthesis. It also stands on +its own. I know we've seen it trigger in spec without the constant synthesis +bits. + +It's been through our internal CI and my tester. I'll obviously wait for the +upstream CI to finish before taking further action. + +gcc/ + * config/riscv/crypto.md: Add new combiner patterns to generate + pack, packh, packw instrutions. + * config/riscv/iterators.md (HX): New iterator for half X mode. + * config/riscv/riscv.md (_shift_reverse): Tighten + cases to avoid. Do not lose bits for XOR/IOR. + +gcc/testsuite + + * gcc.target/riscv/pack32.c: New test. + * gcc.target/riscv/pack64.c: New test. + * gcc.target/riscv/packh32.c: New test. + * gcc.target/riscv/packh64.c: New test. + * gcc.target/riscv/packw.c: New test. + + Co-authored-by: Jeffrey A Law +--- + gcc/config/riscv/crypto.md | 63 ++++++++++++++++++++++++ + gcc/config/riscv/iterators.md | 3 ++ + gcc/config/riscv/riscv.md | 9 ++-- + gcc/testsuite/gcc.target/riscv/pack32.c | 18 +++++++ + gcc/testsuite/gcc.target/riscv/pack64.c | 17 +++++++ + gcc/testsuite/gcc.target/riscv/packh32.c | 13 +++++ + gcc/testsuite/gcc.target/riscv/packh64.c | 6 +++ + gcc/testsuite/gcc.target/riscv/packw.c | 13 +++++ + 8 files changed, 139 insertions(+), 3 deletions(-) + create mode 100644 gcc/testsuite/gcc.target/riscv/pack32.c + create mode 100644 gcc/testsuite/gcc.target/riscv/pack64.c + create mode 100644 gcc/testsuite/gcc.target/riscv/packh32.c + create mode 100644 gcc/testsuite/gcc.target/riscv/packh64.c + create mode 100644 gcc/testsuite/gcc.target/riscv/packw.c + +diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md +index dd2bc94ee88..b632312ade2 100644 +--- a/gcc/config/riscv/crypto.md ++++ b/gcc/config/riscv/crypto.md +@@ -104,6 +104,19 @@ + "pack\t%0,%1,%2" + [(set_attr "type" "crypto")]) + ++;; This is slightly more complex than the other pack patterns ++;; that fully expose the RTL as it needs to self-adjust to ++;; rv32 and rv64. But it's not that hard. ++(define_insn "*riscv_xpack__2" ++ [(set (match_operand:X 0 "register_operand" "=r") ++ (ior:X (ashift:X (match_operand:X 1 "register_operand" "r") ++ (match_operand 2 "immediate_operand" "n")) ++ (zero_extend:X ++ (match_operand:HX 3 "register_operand" "r"))))] ++ "TARGET_ZBKB && INTVAL (operands[2]) == BITS_PER_WORD / 2" ++ "pack\t%0,%3,%1" ++ [(set_attr "type" "crypto")]) ++ + (define_insn "riscv_packh_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:QI 1 "register_operand" "r") +@@ -113,6 +126,29 @@ + "packh\t%0,%1,%2" + [(set_attr "type" "crypto")]) + ++;; So this is both a useful pattern unto itself and a bridge to the ++;; general packh pattern below. ++(define_insn "*riscv_packh__2" ++ [(set (match_operand:X 0 "register_operand" "=r") ++ (and:X (ashift:X (match_operand:X 1 "register_operand" "r") ++ (const_int 8)) ++ (const_int 65280)))] ++ "TARGET_ZBKB" ++ "packh\t%0,x0,%1" ++ [(set_attr "type" "crypto")]) ++ ++;; While the two operands of the IOR could be swapped, this appears ++;; to be the canonical form. The other form doesn't seem to trigger. ++(define_insn "*riscv_packh__3" ++ [(set (match_operand:X 0 "register_operand" "=r") ++ (ior:X (and:X (ashift:X (match_operand:X 1 "register_operand" "r") ++ (const_int 8)) ++ (const_int 65280)) ++ (zero_extend:X (match_operand:QI 2 "register_operand" "r"))))] ++ "TARGET_ZBKB" ++ "packh\t%0,%2,%1" ++ [(set_attr "type" "crypto")]) ++ + (define_insn "riscv_packw" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:HI 1 "register_operand" "r") +@@ -122,6 +158,33 @@ + "packw\t%0,%1,%2" + [(set_attr "type" "crypto")]) + ++;; Implemented as a splitter for initial recognition. It generates ++;; new RTL with the extension moved to the outer position. This ++;; allows later code to eliminate subsequent explicit sign extensions. ++(define_split ++ [(set (match_operand:DI 0 "register_operand") ++ (ior:DI (ashift:DI ++ (sign_extend:DI (match_operand:HI 1 "register_operand")) ++ (const_int 16)) ++ (zero_extend:DI (match_operand:HI 2 "register_operand"))))] ++ "TARGET_ZBKB && TARGET_64BIT" ++ [(set (match_dup 0) ++ (sign_extend:DI (ior:SI (ashift:SI (match_dup 1) (const_int 16)) ++ (zero_extend:SI (match_dup 2)))))] ++ "operands[1] = gen_lowpart (SImode, operands[1]);") ++ ++;; And this patches the result of the splitter above. ++(define_insn "*riscv_packw_2" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (sign_extend:DI ++ (ior:SI ++ (ashift:SI (match_operand:SI 1 "register_operand" "r") ++ (const_int 16)) ++ (zero_extend:SI (match_operand:HI 2 "register_operand" "r")))))] ++ "TARGET_ZBKB && TARGET_64BIT" ++ "packw\t%0,%2,%1" ++ [(set_attr "type" "crypto")]) ++ + ;; ZBKX extension + + (define_insn "riscv_xperm4_" +diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md +index bad9ba19933..72d19c55efb 100644 +--- a/gcc/config/riscv/iterators.md ++++ b/gcc/config/riscv/iterators.md +@@ -37,6 +37,9 @@ + ;; Likewise, but for XLEN-sized quantities. + (define_mode_iterator X [(SI "!TARGET_64BIT") (DI "TARGET_64BIT")]) + ++;; Likewise, but for XLEN/2 -sized quantities. ++(define_mode_iterator HX [(HI "!TARGET_64BIT") (SI "TARGET_64BIT")]) ++ + ;; Branches operate on XLEN-sized quantities, but for RV64 we accept + ;; QImode values so we can force zero-extension. + (define_mode_iterator BR [(QI "TARGET_64BIT") SI (DI "TARGET_64BIT")]) +diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md +index e5e7cd80ef4..8c453ecbd05 100644 +--- a/gcc/config/riscv/riscv.md ++++ b/gcc/config/riscv/riscv.md +@@ -2844,9 +2844,12 @@ + (match_operand 2 "immediate_operand" "n")) + (match_operand 3 "immediate_operand" "n")))] + "(!SMALL_OPERAND (INTVAL (operands[3])) +- && SMALL_OPERAND (INTVAL (operands[3]) >> INTVAL (operands[2])) +- && (popcount_hwi (INTVAL (operands[3])) +- <= popcount_hwi (INTVAL (operands[3]) >> INTVAL (operands[2]))))" ++ && SMALL_OPERAND (INTVAL (operands[3]) >> INTVAL (operands[2])) ++ && popcount_hwi (INTVAL (operands[3])) > 1 ++ && (!TARGET_64BIT ++ || (exact_log2 ((INTVAL (operands[3]) >> INTVAL (operands[2])) + 1) ++ == -1)) ++ && (INTVAL (operands[3]) & ((1ULL << INTVAL (operands[2])) - 1)) == 0)" + "#" + "&& 1" + [(set (match_dup 0) (any_bitwise:X (match_dup 1) (match_dup 3))) +diff --git a/gcc/testsuite/gcc.target/riscv/pack32.c b/gcc/testsuite/gcc.target/riscv/pack32.c +new file mode 100644 +index 00000000000..24304d6b614 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/pack32.c +@@ -0,0 +1,18 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -march=rv32gc_zbkb -mabi=ilp32" } */ ++/* { dg-skip-if "" { *-*-* } { "-g" "-flto" "-O0" } } */ ++ ++#include ++ ++uint32_t foo1(uint32_t rs1, uint32_t rs2) ++{ ++ return (rs1 << 16) | ((rs2 << 16) >> 16); ++} ++ ++uint32_t foo2(uint32_t rs1, uint32_t rs2) ++{ ++ return (rs1 << 16) | (rs2 & 65535); ++} ++ ++/* { dg-final { scan-assembler-times "\\spack\\s" 2 } } */ ++ +diff --git a/gcc/testsuite/gcc.target/riscv/pack64.c b/gcc/testsuite/gcc.target/riscv/pack64.c +new file mode 100644 +index 00000000000..7f54baabb2c +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/pack64.c +@@ -0,0 +1,17 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -march=rv64gc_zbkb -mabi=lp64" } */ ++/* { dg-skip-if "" { *-*-* } { "-g" "-flto" "-O0" } } */ ++#include ++ ++uint64_t foo1(uint64_t rs1, uint64_t rs2) ++{ ++ return (rs1 << 32) | ((rs2 << 32) >> 32); ++} ++ ++uint64_t foo2(uint64_t rs1, uint64_t rs2) ++{ ++ return (rs1 << 32) | (rs2 & 4294967295); ++} ++ ++/* { dg-final { scan-assembler-times "\\spack\\s" 2 } } */ ++ +diff --git a/gcc/testsuite/gcc.target/riscv/packh32.c b/gcc/testsuite/gcc.target/riscv/packh32.c +new file mode 100644 +index 00000000000..803224189d5 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/packh32.c +@@ -0,0 +1,13 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -march=rv32gc_zbkb -mabi=ilp32" } */ ++/* { dg-skip-if "" { *-*-* } { "-g" "-flto" "-O0" } } */ ++ ++#include ++ ++int32_t foo1(int32_t rs1, int32_t rs2) ++{ ++ return (rs1 & 255) | ((rs2 & 255) << 8); ++} ++ ++/* { dg-final { scan-assembler-times "\\spackh\\s" 1 } } */ ++ +diff --git a/gcc/testsuite/gcc.target/riscv/packh64.c b/gcc/testsuite/gcc.target/riscv/packh64.c +new file mode 100644 +index 00000000000..b91d4014c9a +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/packh64.c +@@ -0,0 +1,6 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -march=rv64gc_zbkb -mabi=lp64" } */ ++/* { dg-skip-if "" { *-*-* } { "-g" "-flto" "-O0" } } */ ++#include "packh32.c" ++/* { dg-final { scan-assembler-times "\\spackh\\s" 1 } } */ ++ +diff --git a/gcc/testsuite/gcc.target/riscv/packw.c b/gcc/testsuite/gcc.target/riscv/packw.c +new file mode 100644 +index 00000000000..c178738a43b +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/packw.c +@@ -0,0 +1,13 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -march=rv64gc_zbkb -mabi=lp64" } */ ++/* { dg-skip-if "" { *-*-* } { "-g" "-flto" "-O0" } } */ ++#include ++ ++uint32_t foo1(uint32_t rs1, uint32_t rs2) ++{ ++ return (rs1 << 16) | ((rs2 << 16) >> 16); ++} ++ ++/* { dg-final { scan-assembler-times "\\spackw\\s" 1 } } */ ++/* { dg-final { scan-assembler-not "\\ssext\\s" } } */ ++ +-- +2.47.3 + diff --git a/1033-OpenMP-Fix-for-ICE-in-tree-nested.cc.patch b/1033-OpenMP-Fix-for-ICE-in-tree-nested.cc.patch new file mode 100644 index 0000000..b79ce46 --- /dev/null +++ b/1033-OpenMP-Fix-for-ICE-in-tree-nested.cc.patch @@ -0,0 +1,42 @@ +From 29f66e7dc6b87ebec7403f1c40095621646d8499 Mon Sep 17 00:00:00 2001 +From: Sandra Loosemore +Date: Mon, 22 Apr 2024 18:24:25 +0000 +Subject: [PATCH 1033/1087] OpenMP: Fix for ICE in tree-nested.cc. + +commit 80c03ac8041340b29325f86ed58ea8bd40a55b99 upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +Use gimple_omp_target_clauses() instead of gimple_omp_taskreg_clauses() +when stmt is GIMPLE_OMP_TARGET, to avoid an as_a<> ICE. The code +immediately following this is already conditionalized in the same way. + +gcc/ChangeLog + * tree-nested.cc (convert_tramp_reference_stmt): Use the correct + accessor for GIMPLE_OMP_TARGET clauses. +--- + gcc/tree-nested.cc | 8 +++++--- + 1 file changed, 5 insertions(+), 3 deletions(-) + +diff --git a/gcc/tree-nested.cc b/gcc/tree-nested.cc +index 4e5f3be7676..fc0495d6443 100644 +--- a/gcc/tree-nested.cc ++++ b/gcc/tree-nested.cc +@@ -2906,9 +2906,11 @@ convert_tramp_reference_stmt (gimple_stmt_iterator *gsi, bool *handled_ops_p, + continue; + decl = i ? get_chain_decl (info) : info->frame_decl; + /* Don't add CHAIN.* or FRAME.* twice. */ +- for (c = gimple_omp_taskreg_clauses (stmt); +- c; +- c = OMP_CLAUSE_CHAIN (c)) ++ if (gimple_code (stmt) == GIMPLE_OMP_TARGET) ++ c = gimple_omp_target_clauses (stmt); ++ else ++ c = gimple_omp_taskreg_clauses (stmt); ++ for (; c; c = OMP_CLAUSE_CHAIN (c)) + if ((OMP_CLAUSE_CODE (c) == OMP_CLAUSE_FIRSTPRIVATE + || OMP_CLAUSE_CODE (c) == OMP_CLAUSE_SHARED) + && OMP_CLAUSE_DECL (c) == decl) +-- +2.47.3 + diff --git a/1034-c-ICE-in-build_deduction_guide-for-invalid-template-.patch b/1034-c-ICE-in-build_deduction_guide-for-invalid-template-.patch new file mode 100644 index 0000000..cd3a085 --- /dev/null +++ b/1034-c-ICE-in-build_deduction_guide-for-invalid-template-.patch @@ -0,0 +1,66 @@ +From 6f33eb5bf2a741db8b4dcb4874bb548897c29fcb Mon Sep 17 00:00:00 2001 +From: Simon Martin +Date: Mon, 6 May 2024 15:20:10 +0200 +Subject: [PATCH 1034/1087] c++: ICE in build_deduction_guide for invalid + template [PR105760] + +commit upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +We currently ICE upon the following invalid snippet because we fail to +properly handle tsubst_arg_types returning error_mark_node in +build_deduction_guide. + +== cut == +template +struct A { A(Ts...); }; +A a; +== cut == + +This patch fixes this, and has been successfully tested on x86_64-pc-linux-gnu. + + PR c++/105760 + +gcc/cp/ChangeLog: + + * pt.cc (build_deduction_guide): Check for error_mark_node + result from tsubst_arg_types. + +gcc/testsuite/ChangeLog: + + * g++.dg/parse/error66.C: New test. +--- + gcc/cp/pt.cc | 2 ++ + gcc/testsuite/g++.dg/parse/error66.C | 6 ++++++ + 2 files changed, 8 insertions(+) + create mode 100644 gcc/testsuite/g++.dg/parse/error66.C + +diff --git a/gcc/cp/pt.cc b/gcc/cp/pt.cc +index 65fa85b0610..a0a3cdbc5e8 100644 +--- a/gcc/cp/pt.cc ++++ b/gcc/cp/pt.cc +@@ -30172,6 +30172,8 @@ build_deduction_guide (tree type, tree ctor, tree outer_args, tsubst_flags_t com + references to members of an unknown specialization. */ + cp_evaluated ev; + fparms = tsubst_arg_types (fparms, targs, NULL_TREE, complain, ctor); ++ if (fparms == error_mark_node) ++ ok = false; + fargs = tsubst (fargs, targs, complain, ctor); + if (ci) + { +diff --git a/gcc/testsuite/g++.dg/parse/error66.C b/gcc/testsuite/g++.dg/parse/error66.C +new file mode 100644 +index 00000000000..82f4b8b8a53 +--- /dev/null ++++ b/gcc/testsuite/g++.dg/parse/error66.C +@@ -0,0 +1,6 @@ ++// PR c++/105760 ++// { dg-do compile { target c++17 } } ++ ++template // { dg-error "must be at the end of the template parameter list" } ++struct A { A(Ts...); }; ++A a; +-- +2.47.3 + diff --git a/1035-Fix-rv32-issues-with-recent-zicboz-work.patch b/1035-Fix-rv32-issues-with-recent-zicboz-work.patch new file mode 100644 index 0000000..a774a42 --- /dev/null +++ b/1035-Fix-rv32-issues-with-recent-zicboz-work.patch @@ -0,0 +1,82 @@ +From 20f1a4dfd72309b774e305624241509e1ff35817 Mon Sep 17 00:00:00 2001 +From: Jeff Law +Date: Tue, 14 May 2024 22:50:15 -0600 +Subject: [PATCH 1035/1087] Fix rv32 issues with recent zicboz work + +commit e410ad74e5e4589aeb666aa298b2f933e7b5d9e7 upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +I should have double-checked the CI system before pushing Christoph's patches +for memset-zero. While I thought I'd checked CI state, I must have been +looking at the wrong patch from Christoph. + +Anyway, this fixes the rv32 ICEs and disables one of the tests for rv32. + +The test would need a revamp for rv32 as the expected output is all rv64 code +using "sd" instructions. I'm just not vested deeply enough into rv32 to adjust +the test to work in that environment though it should be fairly trivial to copy +the test and provide new expected output if someone cares enough. + +Verified this fixes the rv32 failures in my tester: +> New tests that FAIL (6 tests): +> +> unix/-march=rv32gcv: gcc: gcc.target/riscv/cmo-zicboz-zic64-1.c -O1 (internal compiler error: in extract_insn, at recog.cc:2812) +> unix/-march=rv32gcv: gcc: gcc.target/riscv/cmo-zicboz-zic64-1.c -O1 (test for excess errors) +> unix/-march=rv32gcv: gcc: gcc.target/riscv/cmo-zicboz-zic64-1.c -O2 (internal compiler error: in extract_insn, at recog.cc:2812) +> unix/-march=rv32gcv: gcc: gcc.target/riscv/cmo-zicboz-zic64-1.c -O2 (test for excess errors) +> unix/-march=rv32gcv: gcc: gcc.target/riscv/cmo-zicboz-zic64-1.c -O3 -g (internal compiler error: in extract_insn, at recog.cc:2812) +> unix/-march=rv32gcv: gcc: gcc.target/riscv/cmo-zicboz-zic64-1.c -O3 -g (test for excess errors) + +And after the ICE is fixed, these are eliminated by only running the test for +rv64: + +> New tests that FAIL (3 tests): +> +> unix/-march=rv32gcv: gcc: gcc.target/riscv/cmo-zicboz-zic64-1.c -O1 check-function-bodies clear_buf_123 +> unix/-march=rv32gcv: gcc: gcc.target/riscv/cmo-zicboz-zic64-1.c -O2 check-function-bodies clear_buf_123 +> unix/-march=rv32gcv: gcc: gcc.target/riscv/cmo-zicboz-zic64-1.c -O3 -g check-function-bodies clear_buf_123 + +gcc/ + * config/riscv/riscv-string.cc + (riscv_expand_block_clear_zicboz_zic64b): Handle rv32 correctly. + +gcc/testsuite + + * gcc.target/riscv/cmo-zicboz-zic64-1.c: Don't run on rv32. +--- + gcc/config/riscv/riscv-string.cc | 5 ++++- + gcc/testsuite/gcc.target/riscv/cmo-zicboz-zic64-1.c | 3 +-- + 2 files changed, 5 insertions(+), 3 deletions(-) + +diff --git a/gcc/config/riscv/riscv-string.cc b/gcc/config/riscv/riscv-string.cc +index 7968fe8b8a6..241dcd04e87 100644 +--- a/gcc/config/riscv/riscv-string.cc ++++ b/gcc/config/riscv/riscv-string.cc +@@ -827,7 +827,10 @@ riscv_expand_block_clear_zicboz_zic64b (rtx dest, rtx length) + { + rtx mem = adjust_address (dest, BLKmode, offset); + rtx addr = force_reg (Pmode, XEXP (mem, 0)); +- emit_insn (gen_riscv_zero_di (addr)); ++ if (TARGET_64BIT) ++ emit_insn (gen_riscv_zero_di (addr)); ++ else ++ emit_insn (gen_riscv_zero_si (addr)); + offset += cbo_bytes; + } + +diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicboz-zic64-1.c b/gcc/testsuite/gcc.target/riscv/cmo-zicboz-zic64-1.c +index c2d79eb7ae6..6d4535287d0 100644 +--- a/gcc/testsuite/gcc.target/riscv/cmo-zicboz-zic64-1.c ++++ b/gcc/testsuite/gcc.target/riscv/cmo-zicboz-zic64-1.c +@@ -1,6 +1,5 @@ + /* { dg-do compile } */ +-/* { dg-options "-march=rv64gc_zic64b_zicboz" { target { rv64 } } } */ +-/* { dg-options "-march=rv32gc_zic64b_zicboz" { target { rv32 } } } */ ++/* { dg-options "-march=rv64gc_zic64b_zicboz -mabi=lp64d" } */ + /* { dg-skip-if "" { *-*-* } {"-O0" "-Os" "-Og" "-Oz" "-flto" } } */ + /* { dg-final { check-function-bodies "**" "" } } */ + /* { dg-allow-blank-lines-in-output 1 } */ +-- +2.47.3 + diff --git a/1036-Avoid-ICE-in-except.cc-on-targets-that-don-t-support.patch b/1036-Avoid-ICE-in-except.cc-on-targets-that-don-t-support.patch new file mode 100644 index 0000000..81dc4cc --- /dev/null +++ b/1036-Avoid-ICE-in-except.cc-on-targets-that-don-t-support.patch @@ -0,0 +1,68 @@ +From 2b54c2a45d71362615f4f9400663244a9b728c35 Mon Sep 17 00:00:00 2001 +From: Roger Sayle +Date: Wed, 22 May 2024 13:48:52 +0100 +Subject: [PATCH 1036/1087] Avoid ICE in except.cc on targets that don't + support exceptions. + +commit 26df7b4684e201e66c09dd018603a248ddc5f437 upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +A number of testcases currently fail on nvptx with the ICE: + +during RTL pass: final +openmp-simd-2.c: In function 'foo': +openmp-simd-2.c:28:1: internal compiler error: in get_personality_function, at expr.cc:14037 + 28 | } + | ^ +0x98a38f get_personality_function(tree_node*) + /home/roger/GCC/nvptx-none/gcc/gcc/expr.cc:14037 +0x969d3b output_function_exception_table(int) + /home/roger/GCC/nvptx-none/gcc/gcc/except.cc:3226 +0x9b760d rest_of_handle_final + /home/roger/GCC/nvptx-none/gcc/gcc/final.cc:4252 + +The simple oversight in output_function_exception_table is that it calls +get_personality_function (immediately) before checking the target's +except_unwind_info hook (which on nvptx always returns UI_NONE). +The (perhaps obvious) fix is to move the assignments of fname and +personality after the tests that they are needed, and before their +first use. + +2024-05-22 Roger Sayle + +gcc/ChangeLog + * except.cc (output_function_exception_table): Move call to + get_personality_function after targetm_common.except_unwind_info + check, to avoid ICE on targets that don't support exceptions. +--- + gcc/except.cc | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/gcc/except.cc b/gcc/except.cc +index c6c9c80d286..e0a9d5e686e 100644 +--- a/gcc/except.cc ++++ b/gcc/except.cc +@@ -3224,9 +3224,6 @@ output_one_function_exception_table (int section) + void + output_function_exception_table (int section) + { +- const char *fnname = get_fnname_from_decl (current_function_decl); +- rtx personality = get_personality_function (current_function_decl); +- + /* Not all functions need anything. */ + if (!crtl->uses_eh_lsda + || targetm_common.except_unwind_info (&global_options) == UI_NONE) +@@ -3236,6 +3233,9 @@ output_function_exception_table (int section) + if (section == 1 && !crtl->eh.call_site_record_v[1]) + return; + ++ const char *fnname = get_fnname_from_decl (current_function_decl); ++ rtx personality = get_personality_function (current_function_decl); ++ + if (personality) + { + assemble_external_libcall (personality); +-- +2.47.3 + diff --git a/1037-Fix-PR-c-109958-ICE-taking-the-address-of-bound-stat.patch b/1037-Fix-PR-c-109958-ICE-taking-the-address-of-bound-stat.patch new file mode 100644 index 0000000..c932835 --- /dev/null +++ b/1037-Fix-PR-c-109958-ICE-taking-the-address-of-bound-stat.patch @@ -0,0 +1,77 @@ +From f9f12e7f8af5c1591fbba45e8497c94fcd24c893 Mon Sep 17 00:00:00 2001 +From: Simon Martin +Date: Sun, 2 Jun 2024 17:45:04 +0200 +Subject: [PATCH 1037/1087] Fix PR c++/109958: ICE taking the address of bound + static member function brought into derived class by using-declaration + +commit 47827293551a3ec339617678c8e938c8ca3790f1 upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +We currently ICE upon the following because we don't properly handle the +overload created for B::f through the using statement. + +=== cut here === +struct B { static int f(); }; +struct D : B { using B::f; }; +void f(D d) { &d.f; } +=== cut here === + +This patch makes build_class_member_access_expr and cp_build_addr_expr_1 handle +such overloads, and fixes the PR. + +Successfully tested on x86_64-pc-linux-gnu. + + PR c++/109958 + +gcc/cp/ChangeLog: + + * typeck.cc (build_class_member_access_expr): Handle single OVERLOADs. + (cp_build_addr_expr_1): Likewise. + +gcc/testsuite/ChangeLog: + + * g++.dg/overload/using6.C: New test. +--- + gcc/cp/typeck.cc | 5 +++++ + gcc/testsuite/g++.dg/overload/using6.C | 5 +++++ + 2 files changed, 10 insertions(+) + create mode 100644 gcc/testsuite/g++.dg/overload/using6.C + +diff --git a/gcc/cp/typeck.cc b/gcc/cp/typeck.cc +index 0db294a552e..ab7bcfa14e4 100644 +--- a/gcc/cp/typeck.cc ++++ b/gcc/cp/typeck.cc +@@ -3019,6 +3019,8 @@ build_class_member_access_expr (cp_expr object, tree member, + know the type of the expression. Otherwise, we must wait + until overload resolution has been performed. */ + functions = BASELINK_FUNCTIONS (member); ++ if (TREE_CODE (functions) == OVERLOAD && OVL_SINGLE_P (functions)) ++ functions = OVL_FIRST (functions); + if (TREE_CODE (functions) == FUNCTION_DECL + && DECL_STATIC_FUNCTION_P (functions)) + type = TREE_TYPE (functions); +@@ -7354,6 +7356,9 @@ cp_build_addr_expr_1 (tree arg, bool strict_lvalue, tsubst_flags_t complain) + { + tree fn = BASELINK_FUNCTIONS (TREE_OPERAND (arg, 1)); + ++ if (TREE_CODE (fn) == OVERLOAD && OVL_SINGLE_P (fn)) ++ fn = OVL_FIRST (fn); ++ + /* We can only get here with a single static member + function. */ + gcc_assert (TREE_CODE (fn) == FUNCTION_DECL +diff --git a/gcc/testsuite/g++.dg/overload/using6.C b/gcc/testsuite/g++.dg/overload/using6.C +new file mode 100644 +index 00000000000..4f89f68a30f +--- /dev/null ++++ b/gcc/testsuite/g++.dg/overload/using6.C +@@ -0,0 +1,5 @@ ++// PR c++/109958 ++ ++struct B { static int f(); }; ++struct D : B { using B::f; }; ++void f(D d) { &d.f; } +-- +2.47.3 + diff --git a/1038-Avoid-ICE-with-pointer-reduction.patch b/1038-Avoid-ICE-with-pointer-reduction.patch new file mode 100644 index 0000000..7652fcb --- /dev/null +++ b/1038-Avoid-ICE-with-pointer-reduction.patch @@ -0,0 +1,39 @@ +From 32337ea4ed47c060f434c8ba2a2d2e43d6e78073 Mon Sep 17 00:00:00 2001 +From: Richard Biener +Date: Fri, 31 May 2024 15:17:10 +0200 +Subject: [PATCH 1038/1087] Avoid ICE with pointer reduction + +commit a1810364cd0c36d6408a4c386bdc504a021d68c7 upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +There's another case where we can refer to neutral_op before +eventually converting it from pointer to integer so simply +do that unconditionally. + + * tree-vect-loop.cc (get_initial_defs_for_reduction): + Always convert neutral_op. +--- + gcc/tree-vect-loop.cc | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/gcc/tree-vect-loop.cc b/gcc/tree-vect-loop.cc +index 75fbcdf46d0..83757b8a2cf 100644 +--- a/gcc/tree-vect-loop.cc ++++ b/gcc/tree-vect-loop.cc +@@ -5635,6 +5635,12 @@ get_initial_defs_for_reduction (loop_vec_info loop_vinfo, + tree_vector_builder elts (vector_type, nunits, 1); + elts.quick_grow (nunits); + gimple_seq ctor_seq = NULL; ++ if (neutral_op ++ && !useless_type_conversion_p (TREE_TYPE (vector_type), ++ TREE_TYPE (neutral_op))) ++ neutral_op = gimple_convert (&ctor_seq, ++ TREE_TYPE (vector_type), ++ neutral_op); + for (j = 0; j < nunits * number_of_vectors; ++j) + { + tree op; +-- +2.47.3 + diff --git a/1039-RISC-V-Add-basic-Zaamo-and-Zalrsc-support.patch b/1039-RISC-V-Add-basic-Zaamo-and-Zalrsc-support.patch new file mode 100644 index 0000000..d659ff9 --- /dev/null +++ b/1039-RISC-V-Add-basic-Zaamo-and-Zalrsc-support.patch @@ -0,0 +1,335 @@ +From 8f2263b63023eb9846de0364d6583109b7283bf5 Mon Sep 17 00:00:00 2001 +From: Edwin Lu +Date: Wed, 7 Feb 2024 16:30:28 -0800 +Subject: [PATCH 1039/1087] RISC-V: Add basic Zaamo and Zalrsc support + +commit af139b3fc19fbdd7caa649bcb2cb75cc5a254143 upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +There is a proposal to split the A extension into two parts: Zaamo and Zalrsc. +This patch adds basic support by making the A extension imply Zaamo and +Zalrsc. + +Proposal: https://github.com/riscv/riscv-zaamo-zalrsc/tags + +gcc/ChangeLog: + + * common/config/riscv/riscv-common.cc: Add Zaamo and Zalrsc. + * config/riscv/arch-canonicalize: Make A imply Zaamo and Zalrsc. + * config/riscv/riscv.opt: Add Zaamo and Zalrsc + * config/riscv/sync.md: Convert TARGET_ATOMIC to TARGET_ZAAMO and + TARGET_ZALRSC. + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/attribute-15.c: Adjust expected arch string. + * gcc.target/riscv/attribute-16.c: Ditto. + * gcc.target/riscv/attribute-17.c: Ditto. + * gcc.target/riscv/attribute-18.c: Ditto. + * gcc.target/riscv/pr110696.c: Ditto. + * gcc.target/riscv/rvv/base/pr114352-1.c: Ditto. + * gcc.target/riscv/rvv/base/pr114352-3.c: Ditto. + +Signed-off-by: Edwin Lu +Co-authored-by: Patrick O'Neill +--- + gcc/common/config/riscv/riscv-common.cc | 11 +++++-- + gcc/config/riscv/arch-canonicalize | 1 + + gcc/config/riscv/riscv.opt | 6 +++- + gcc/config/riscv/sync.md | 30 +++++++++---------- + gcc/testsuite/gcc.target/riscv/attribute-15.c | 2 +- + gcc/testsuite/gcc.target/riscv/attribute-16.c | 2 +- + gcc/testsuite/gcc.target/riscv/attribute-17.c | 2 +- + gcc/testsuite/gcc.target/riscv/attribute-18.c | 2 +- + gcc/testsuite/gcc.target/riscv/pr110696.c | 2 +- + .../gcc.target/riscv/rvv/base/pr114352-1.c | 4 +-- + .../gcc.target/riscv/rvv/base/pr114352-3.c | 8 ++--- + 11 files changed, 41 insertions(+), 29 deletions(-) + +diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc +index 06600b8ca69..043dab5da87 100644 +--- a/gcc/common/config/riscv/riscv-common.cc ++++ b/gcc/common/config/riscv/riscv-common.cc +@@ -79,6 +79,9 @@ static const riscv_implied_info_t riscv_implied_info[] = + {"f", "zicsr"}, + {"d", "zicsr"}, + ++ {"a", "zaamo"}, ++ {"a", "zalrsc"}, ++ + {"zdinx", "zfinx"}, + {"zfinx", "zicsr"}, + {"zdinx", "zicsr"}, +@@ -257,6 +260,8 @@ static const struct riscv_ext_version riscv_ext_version_table[] = + {"za64rs", ISA_SPEC_CLASS_NONE, 1, 0}, + {"za128rs", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zawrs", ISA_SPEC_CLASS_NONE, 1, 0}, ++ {"zaamo", ISA_SPEC_CLASS_NONE, 1, 0}, ++ {"zalrsc", ISA_SPEC_CLASS_NONE, 1, 0}, + + {"zba", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zbb", ISA_SPEC_CLASS_NONE, 1, 0}, +@@ -1537,9 +1542,11 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = + {"zifencei", &gcc_options::x_riscv_zi_subext, MASK_ZIFENCEI}, + {"zicond", &gcc_options::x_riscv_zi_subext, MASK_ZICOND}, + +- {"za64rs", &gcc_options::x_riscv_za_subext, MASK_ZA64RS}, ++ {"za64rs", &gcc_options::x_riscv_za_subext, MASK_ZA64RS}, + {"za128rs", &gcc_options::x_riscv_za_subext, MASK_ZA128RS}, +- {"zawrs", &gcc_options::x_riscv_za_subext, MASK_ZAWRS}, ++ {"zawrs", &gcc_options::x_riscv_za_subext, MASK_ZAWRS}, ++ {"zaamo", &gcc_options::x_riscv_za_subext, MASK_ZAAMO}, ++ {"zalrsc", &gcc_options::x_riscv_za_subext, MASK_ZALRSC}, + + {"zba", &gcc_options::x_riscv_zb_subext, MASK_ZBA}, + {"zbb", &gcc_options::x_riscv_zb_subext, MASK_ZBB}, +diff --git a/gcc/config/riscv/arch-canonicalize b/gcc/config/riscv/arch-canonicalize +index 8f7d040cdeb..6c10d1aa81b 100755 +--- a/gcc/config/riscv/arch-canonicalize ++++ b/gcc/config/riscv/arch-canonicalize +@@ -40,6 +40,7 @@ LONG_EXT_PREFIXES = ['z', 's', 'h', 'x'] + # + IMPLIED_EXT = { + "d" : ["f", "zicsr"], ++ "a" : ["zaamo", "zalrsc"], + "f" : ["zicsr"], + "zdinx" : ["zfinx", "zicsr"], + "zfinx" : ["zicsr"], +diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt +index bdaa1c87cdc..29522940172 100644 +--- a/gcc/config/riscv/riscv.opt ++++ b/gcc/config/riscv/riscv.opt +@@ -256,7 +256,11 @@ Mask(ZICCRSE) Var(riscv_zi_subext) + TargetVariable + int riscv_za_subext + +-Mask(ZAWRS) Var(riscv_za_subext) ++Mask(ZAWRS) Var(riscv_za_subext) ++ ++Mask(ZAAMO) Var(riscv_za_subext) ++ ++Mask(ZALRSC) Var(riscv_za_subext) + + Mask(ZA64RS) Var(riscv_za_subext) + +diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md +index be31ddb9798..f44c69d34f7 100644 +--- a/gcc/config/riscv/sync.md ++++ b/gcc/config/riscv/sync.md +@@ -93,7 +93,7 @@ + (match_operand:GPR 1 "reg_or_0_operand" "rJ")) + (match_operand:SI 2 "const_int_operand")] ;; model + UNSPEC_SYNC_OLD_OP))] +- "TARGET_ATOMIC" ++ "TARGET_ZAAMO" + "amo.%A2\tzero,%z1,%0" + [(set_attr "type" "atomic") + (set (attr "length") (const_int 4))]) +@@ -107,7 +107,7 @@ + (match_operand:GPR 2 "reg_or_0_operand" "rJ")) + (match_operand:SI 3 "const_int_operand")] ;; model + UNSPEC_SYNC_OLD_OP))] +- "TARGET_ATOMIC" ++ "TARGET_ZAAMO" + "amo.%A3\t%0,%z2,%1" + [(set_attr "type" "atomic") + (set (attr "length") (const_int 4))]) +@@ -125,7 +125,7 @@ + (match_operand:SI 5 "register_operand" "rI") ;; not_mask + (clobber (match_scratch:SI 6 "=&r")) ;; tmp_1 + (clobber (match_scratch:SI 7 "=&r"))] ;; tmp_2 +- "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" ++ "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC" + { + return "1:\;" + "lr.w%I3\t%0, %1\;" +@@ -144,7 +144,7 @@ + (not:SHORT (and:SHORT (match_operand:SHORT 1 "memory_operand") ;; mem location + (match_operand:SHORT 2 "reg_or_0_operand"))) ;; value for op + (match_operand:SI 3 "const_int_operand")] ;; model +- "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" ++ "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC" + { + /* We have no QImode/HImode atomics, so form a mask, then use + subword_atomic_fetch_strong_nand to implement a LR/SC version of the +@@ -192,7 +192,7 @@ + (match_operand:SI 5 "register_operand" "rI") ;; not_mask + (clobber (match_scratch:SI 6 "=&r")) ;; tmp_1 + (clobber (match_scratch:SI 7 "=&r"))] ;; tmp_2 +- "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" ++ "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC" + { + return "1:\;" + "lr.w%I3\t%0, %1\;" +@@ -212,7 +212,7 @@ + (any_atomic:SHORT (match_operand:SHORT 1 "memory_operand") ;; mem location + (match_operand:SHORT 2 "reg_or_0_operand")) ;; value for op + (match_operand:SI 3 "const_int_operand")] ;; model +- "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" ++ "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC" + { + /* We have no QImode/HImode atomics, so form a mask, then use + subword_atomic_fetch_strong_ to implement a LR/SC version of the +@@ -256,7 +256,7 @@ + UNSPEC_SYNC_EXCHANGE)) + (set (match_dup 1) + (match_operand:GPR 2 "register_operand" "0"))] +- "TARGET_ATOMIC" ++ "TARGET_ZAAMO" + "amoswap.%A3\t%0,%z2,%1" + [(set_attr "type" "atomic") + (set (attr "length") (const_int 4))]) +@@ -266,7 +266,7 @@ + (match_operand:SHORT 1 "memory_operand") ;; mem location + (match_operand:SHORT 2 "register_operand") ;; value + (match_operand:SI 3 "const_int_operand")] ;; model +- "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" ++ "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC" + { + rtx old = gen_reg_rtx (SImode); + rtx mem = operands[1]; +@@ -304,7 +304,7 @@ + UNSPEC_SYNC_EXCHANGE_SUBWORD)) + (match_operand:SI 4 "reg_or_0_operand" "rI") ;; not_mask + (clobber (match_scratch:SI 5 "=&r"))] ;; tmp_1 +- "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" ++ "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC" + { + return "1:\;" + "lr.w%I3\t%0, %1\;" +@@ -326,7 +326,7 @@ + (match_operand:SI 5 "const_int_operand")] ;; mod_f + UNSPEC_COMPARE_AND_SWAP)) + (clobber (match_scratch:GPR 6 "=&r"))] +- "TARGET_ATOMIC" ++ "TARGET_ZALRSC" + { + enum memmodel model_success = (enum memmodel) INTVAL (operands[4]); + enum memmodel model_failure = (enum memmodel) INTVAL (operands[5]); +@@ -352,7 +352,7 @@ + (match_operand:SI 5 "const_int_operand" "") ;; is_weak + (match_operand:SI 6 "const_int_operand" "") ;; mod_s + (match_operand:SI 7 "const_int_operand" "")] ;; mod_f +- "TARGET_ATOMIC" ++ "TARGET_ZALRSC" + { + if (word_mode != mode && operands[3] != const0_rtx) + { +@@ -395,7 +395,7 @@ + (match_operand:SI 5 "const_int_operand") ;; is_weak + (match_operand:SI 6 "const_int_operand") ;; mod_s + (match_operand:SI 7 "const_int_operand")] ;; mod_f +- "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" ++ "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC" + { + emit_insn (gen_atomic_cas_value_strong (operands[1], operands[2], + operands[3], operands[4], +@@ -440,7 +440,7 @@ + (match_operand:SI 4 "const_int_operand") ;; mod_s + (match_operand:SI 5 "const_int_operand") ;; mod_f + (match_scratch:SHORT 6)] +- "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" ++ "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC" + { + /* We have no QImode/HImode atomics, so form a mask, then use + subword_atomic_cas_strong to implement a LR/SC version of the +@@ -498,7 +498,7 @@ + (match_operand:SI 5 "register_operand" "rI") ;; mask + (match_operand:SI 6 "register_operand" "rI") ;; not_mask + (clobber (match_scratch:SI 7 "=&r"))] ;; tmp_1 +- "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" ++ "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC" + { + return "1:\;" + "lr.w%I4\t%0, %1\;" +@@ -517,7 +517,7 @@ + [(match_operand:QI 0 "register_operand" "") ;; bool output + (match_operand:QI 1 "memory_operand" "+A") ;; memory + (match_operand:SI 2 "const_int_operand" "")] ;; model +- "TARGET_ATOMIC" ++ "TARGET_ZALRSC" + { + /* We have no QImode atomics, so use the address LSBs to form a mask, + then use an aligned SImode atomic. */ +diff --git a/gcc/testsuite/gcc.target/riscv/attribute-15.c b/gcc/testsuite/gcc.target/riscv/attribute-15.c +index 59efeb6ea45..a2e394b6489 100644 +--- a/gcc/testsuite/gcc.target/riscv/attribute-15.c ++++ b/gcc/testsuite/gcc.target/riscv/attribute-15.c +@@ -3,4 +3,4 @@ + int foo() + { + } +-/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0\"" } } */ ++/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zaamo1p0_zalrsc1p0\"" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/attribute-16.c b/gcc/testsuite/gcc.target/riscv/attribute-16.c +index 26f961efb48..d2b18160cb5 100644 +--- a/gcc/testsuite/gcc.target/riscv/attribute-16.c ++++ b/gcc/testsuite/gcc.target/riscv/attribute-16.c +@@ -3,4 +3,4 @@ + int foo() + { + } +-/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_m2p0_a2p0_f2p2_d2p2_c2p0_zicsr2p0" } } */ ++/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_m2p0_a2p0_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0\"" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/attribute-17.c b/gcc/testsuite/gcc.target/riscv/attribute-17.c +index 0abff3705d9..fc2f488a3ac 100644 +--- a/gcc/testsuite/gcc.target/riscv/attribute-17.c ++++ b/gcc/testsuite/gcc.target/riscv/attribute-17.c +@@ -3,4 +3,4 @@ + int foo() + { + } +-/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0" } } */ ++/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0\"" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/attribute-18.c b/gcc/testsuite/gcc.target/riscv/attribute-18.c +index fddbf15fc3e..eefd602103d 100644 +--- a/gcc/testsuite/gcc.target/riscv/attribute-18.c ++++ b/gcc/testsuite/gcc.target/riscv/attribute-18.c +@@ -1,4 +1,4 @@ + /* { dg-do compile } */ + /* { dg-options "-mriscv-attribute -march=rv64imafdc -mabi=lp64d -misa-spec=2.2" } */ + int foo() {} +-/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0\"" } } */ ++/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zaamo1p0_zalrsc1p0\"" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/pr110696.c b/gcc/testsuite/gcc.target/riscv/pr110696.c +index a630f04e74f..08682a047e0 100644 +--- a/gcc/testsuite/gcc.target/riscv/pr110696.c ++++ b/gcc/testsuite/gcc.target/riscv/pr110696.c +@@ -4,4 +4,4 @@ int foo() + { + } + +-/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0\"" } } */ ++/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0\"" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c +index b3f1f20fb79..faeb406498d 100644 +--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c ++++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c +@@ -54,5 +54,5 @@ test_3 (int *a, int *b, int *out, unsigned count) + out[i] = a[i] + b[i]; + } + +-/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0\"" } } */ +-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */ ++/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0\"" } } */ ++/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c +index e7af4223d6a..38815ef5bd0 100644 +--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c ++++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c +@@ -107,7 +107,7 @@ test_6 (_Float16 *a, _Float16 *b, _Float16 *out, unsigned count) + out[i] = a[i] + b[i]; + } + +-/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0\"" } } */ +-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */ +-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zbb1p0" } } */ +-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zfh1p0_zfhmin1p0" } } */ ++/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0\"" } } */ ++/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */ ++/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zbb1p0" } } */ ++/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zfh1p0_zfhmin1p0" } } */ +-- +2.47.3 + diff --git a/1040-RISC-V-Add-Zalrsc-and-Zaamo-testsuite-support.patch b/1040-RISC-V-Add-Zalrsc-and-Zaamo-testsuite-support.patch new file mode 100644 index 0000000..cb1d45d --- /dev/null +++ b/1040-RISC-V-Add-Zalrsc-and-Zaamo-testsuite-support.patch @@ -0,0 +1,626 @@ +From 2b7cea75c837a99391cdddf8ed855e55459b7715 Mon Sep 17 00:00:00 2001 +From: Patrick O'Neill +Date: Mon, 10 Jun 2024 14:12:40 -0700 +Subject: [PATCH 1040/1087] RISC-V: Add Zalrsc and Zaamo testsuite support + +commit 0fea902b1b5311c8b34ae8e789f1733bd8429904 upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +Convert testsuite infrastructure to use Zalrsc and Zaamo rather than A. + +gcc/ChangeLog: + + * doc/sourcebuild.texi: Add docs for atomic extension testsuite infra. + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/amo-table-a-6-amo-add-1.c: Use Zaamo rather than A. + * gcc.target/riscv/amo-table-a-6-amo-add-2.c: Ditto. + * gcc.target/riscv/amo-table-a-6-amo-add-3.c: Ditto. + * gcc.target/riscv/amo-table-a-6-amo-add-4.c: Ditto. + * gcc.target/riscv/amo-table-a-6-amo-add-5.c: Ditto. + * gcc.target/riscv/amo-table-a-6-compare-exchange-1.c: Use Zalrsc rather + than A. + * gcc.target/riscv/amo-table-a-6-compare-exchange-2.c: Ditto. + * gcc.target/riscv/amo-table-a-6-compare-exchange-3.c: Ditto. + * gcc.target/riscv/amo-table-a-6-compare-exchange-4.c: Ditto. + * gcc.target/riscv/amo-table-a-6-compare-exchange-5.c: Ditto. + * gcc.target/riscv/amo-table-a-6-compare-exchange-6.c: Ditto. + * gcc.target/riscv/amo-table-a-6-compare-exchange-7.c: Ditto. + * gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c: Use Zaamo rather + than A. + * gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c: Ditto. + * gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c: Ditto. + * gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c: Ditto. + * gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c: Ditto. + * gcc.target/riscv/amo-table-ztso-amo-add-1.c: Add Zaamo option. + * gcc.target/riscv/amo-table-ztso-amo-add-2.c: Ditto. + * gcc.target/riscv/amo-table-ztso-amo-add-3.c: Ditto. + * gcc.target/riscv/amo-table-ztso-amo-add-4.c: Ditto. + * gcc.target/riscv/amo-table-ztso-amo-add-5.c: Ditto. + * gcc.target/riscv/amo-table-ztso-compare-exchange-1.c: Use Zalrsc rather + than A. + * gcc.target/riscv/amo-table-ztso-compare-exchange-2.c: Ditto. + * gcc.target/riscv/amo-table-ztso-compare-exchange-3.c: Ditto. + * gcc.target/riscv/amo-table-ztso-compare-exchange-4.c: Ditto. + * gcc.target/riscv/amo-table-ztso-compare-exchange-5.c: Ditto. + * gcc.target/riscv/amo-table-ztso-compare-exchange-6.c: Ditto. + * gcc.target/riscv/amo-table-ztso-compare-exchange-7.c: Ditto. + * gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c: Ditto. + * gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c: Ditto. + * gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c: Ditto. + * gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c: Ditto. + * gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c: Ditto. + * lib/target-supports.exp: Add testsuite infrastructure support for + Zaamo and Zalrsc. + +Signed-off-by: Patrick O'Neill +--- + gcc/doc/sourcebuild.texi | 16 +++++- + .../riscv/amo-table-a-6-amo-add-1.c | 2 +- + .../riscv/amo-table-a-6-amo-add-2.c | 2 +- + .../riscv/amo-table-a-6-amo-add-3.c | 2 +- + .../riscv/amo-table-a-6-amo-add-4.c | 2 +- + .../riscv/amo-table-a-6-amo-add-5.c | 2 +- + .../riscv/amo-table-a-6-compare-exchange-1.c | 2 +- + .../riscv/amo-table-a-6-compare-exchange-2.c | 2 +- + .../riscv/amo-table-a-6-compare-exchange-3.c | 2 +- + .../riscv/amo-table-a-6-compare-exchange-4.c | 2 +- + .../riscv/amo-table-a-6-compare-exchange-5.c | 2 +- + .../riscv/amo-table-a-6-compare-exchange-6.c | 2 +- + .../riscv/amo-table-a-6-compare-exchange-7.c | 2 +- + .../riscv/amo-table-a-6-subword-amo-add-1.c | 2 +- + .../riscv/amo-table-a-6-subword-amo-add-2.c | 2 +- + .../riscv/amo-table-a-6-subword-amo-add-3.c | 2 +- + .../riscv/amo-table-a-6-subword-amo-add-4.c | 2 +- + .../riscv/amo-table-a-6-subword-amo-add-5.c | 2 +- + .../riscv/amo-table-ztso-amo-add-1.c | 2 +- + .../riscv/amo-table-ztso-amo-add-2.c | 2 +- + .../riscv/amo-table-ztso-amo-add-3.c | 2 +- + .../riscv/amo-table-ztso-amo-add-4.c | 2 +- + .../riscv/amo-table-ztso-amo-add-5.c | 2 +- + .../riscv/amo-table-ztso-compare-exchange-1.c | 2 +- + .../riscv/amo-table-ztso-compare-exchange-2.c | 2 +- + .../riscv/amo-table-ztso-compare-exchange-3.c | 2 +- + .../riscv/amo-table-ztso-compare-exchange-4.c | 2 +- + .../riscv/amo-table-ztso-compare-exchange-5.c | 2 +- + .../riscv/amo-table-ztso-compare-exchange-6.c | 2 +- + .../riscv/amo-table-ztso-compare-exchange-7.c | 2 +- + .../riscv/amo-table-ztso-subword-amo-add-1.c | 2 +- + .../riscv/amo-table-ztso-subword-amo-add-2.c | 2 +- + .../riscv/amo-table-ztso-subword-amo-add-3.c | 2 +- + .../riscv/amo-table-ztso-subword-amo-add-4.c | 2 +- + .../riscv/amo-table-ztso-subword-amo-add-5.c | 2 +- + gcc/testsuite/lib/target-supports.exp | 49 ++++++++++++++++++- + 36 files changed, 96 insertions(+), 37 deletions(-) + +diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi +index c8130dc1ba9..f1f723b5d70 100644 +--- a/gcc/doc/sourcebuild.texi ++++ b/gcc/doc/sourcebuild.texi +@@ -2507,8 +2507,17 @@ Test system has an integer register width of 32 bits. + @item rv64 + Test system has an integer register width of 64 bits. + +-@item cv_bi +-Test system has support for the CORE-V BI extension. ++@item riscv_a ++Test target architecture has support for the A extension. ++ ++@item riscv_zaamo ++Test target architecture has support for the zaamo extension. ++ ++@item riscv_zlrsc ++Test target architecture has support for the zalrsc extension. ++ ++@item riscv_ztso ++Test target architecture has support for the ztso extension. + + @end table + +@@ -2528,6 +2537,9 @@ Test system has support for the CORE-V ELW extension. + @item cv_simd + Test system has support for the CORE-V SIMD extension. + ++@item cv_bi ++Test system has support for the CORE-V BI extension. ++ + @end table + + @subsubsection Other hardware attributes +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c +index 8ab1a02b40c..9c2ba39789a 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c +@@ -1,7 +1,7 @@ + /* { dg-do compile } */ + /* Verify that atomic op mappings match Table A.6's recommended mapping. */ + /* { dg-options "-O3" } */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zaamo } */ + /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + /* { dg-final { check-function-bodies "**" "" } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c +index a5a841abdcd..b7682a5bab4 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c +@@ -1,7 +1,7 @@ + /* { dg-do compile } */ + /* Verify that atomic op mappings match Table A.6's recommended mapping. */ + /* { dg-options "-O3" } */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zaamo } */ + /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + /* { dg-final { check-function-bodies "**" "" } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c +index f523821b658..c8776872d91 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c +@@ -1,7 +1,7 @@ + /* { dg-do compile } */ + /* Verify that atomic op mappings match Table A.6's recommended mapping. */ + /* { dg-options "-O3" } */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zaamo } */ + /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + /* { dg-final { check-function-bodies "**" "" } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c +index f1561b52c89..b37c4c3f242 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c +@@ -1,7 +1,7 @@ + /* { dg-do compile } */ + /* Verify that atomic op mappings match Table A.6's recommended mapping. */ + /* { dg-options "-O3" } */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zaamo } */ + /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + /* { dg-final { check-function-bodies "**" "" } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c +index 81f876ee625..8d45ca7a347 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c +@@ -1,7 +1,7 @@ + /* { dg-do compile } */ + /* Verify that atomic op mappings match Table A.6's recommended mapping. */ + /* { dg-options "-O3" } */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zaamo } */ + /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + /* { dg-final { check-function-bodies "**" "" } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c +index dc445f0316a..4917cd6bd2b 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c +@@ -1,6 +1,6 @@ + /* { dg-do compile } */ + /* Verify that compare exchange mappings match Table A.6's recommended mapping. */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zalrsc } */ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c +index 7e8ab7bb5ef..121936507e3 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c +@@ -1,6 +1,6 @@ + /* { dg-do compile } */ + /* Verify that compare exchange mappings match Table A.6's recommended mapping. */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zalrsc } */ + /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c +index 4cb6c422213..649c7d2b1fe 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c +@@ -1,6 +1,6 @@ + /* { dg-do compile } */ + /* Verify that compare exchange mappings match Table A.6's recommended mapping. */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zalrsc } */ + /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c +index da81c34b92c..5f7fdeb1b21 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c +@@ -1,6 +1,6 @@ + /* { dg-do compile } */ + /* Verify that compare exchange mappings match Table A.6's recommended mapping. */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zalrsc } */ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c +index bb16ccc754c..f4bd7d6d842 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c +@@ -1,6 +1,6 @@ + /* { dg-do compile } */ + /* Verify that compare exchange mappings match Table A.6's recommended mapping. */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zalrsc } */ + /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-6.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-6.c +index 0f3f0b49d95..154764425ae 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-6.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-6.c +@@ -1,6 +1,6 @@ + /* { dg-do compile } */ + /* Verify that compare exchange mappings match Table A.6's recommended mapping. */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zalrsc } */ + /* Mixed mappings need to be unioned. */ + /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-7.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-7.c +index d51de56cc78..16712540919 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-7.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-7.c +@@ -1,6 +1,6 @@ + /* { dg-do compile } */ + /* Verify that compare exchange mappings match Table A.6's recommended mapping. */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zalrsc } */ + /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c +index ca8aa715bed..4174fdee352 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c +@@ -1,6 +1,6 @@ + /* { dg-do compile } */ + /* Verify that subword atomic op mappings match Table A.6's recommended mapping. */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zalrsc } */ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c +index e64759a54ae..4c06c90b558 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c +@@ -1,6 +1,6 @@ + /* { dg-do compile } */ + /* Verify that subword atomic op mappings match Table A.6's recommended mapping. */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zalrsc } */ + /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c +index 9d3f69264fa..7e791c901b6 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c +@@ -1,6 +1,6 @@ + /* { dg-do compile } */ + /* Verify that subword atomic op mappings match Table A.6's recommended mapping. */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zalrsc } */ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c +index ba32ed59c2f..76f3be27110 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c +@@ -1,6 +1,6 @@ + /* { dg-do compile } */ + /* Verify that subword atomic op mappings match Table A.6's recommended mapping. */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zalrsc } */ + /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c +index f9be8c5e628..8dbfa9c4fc8 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c +@@ -1,6 +1,6 @@ + /* { dg-do compile } */ + /* Verify that subword atomic op mappings match Table A.6's recommended mapping. */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zalrsc } */ + /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-1.c +index a9edc33ff39..82169390925 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-1.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-1.c +@@ -1,7 +1,7 @@ + /* { dg-do compile } */ + /* Verify that atomic op mappings match the Ztso suggested mapping. */ + /* { dg-options "-O3" } */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zaamo } */ + /* { dg-add-options riscv_ztso } */ + /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + /* { dg-final { check-function-bodies "**" "" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-2.c +index ad843402bcc..a238c6f4403 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-2.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-2.c +@@ -1,7 +1,7 @@ + /* { dg-do compile } */ + /* Verify that atomic op mappings the Ztso suggested mapping. */ + /* { dg-options "-O3" } */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zaamo } */ + /* { dg-add-options riscv_ztso } */ + /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + /* { dg-final { check-function-bodies "**" "" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-3.c +index bdae5bb83a6..c97bf467c63 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-3.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-3.c +@@ -1,7 +1,7 @@ + /* { dg-do compile } */ + /* Verify that atomic op mappings match the Ztso suggested mapping. */ + /* { dg-options "-O3" } */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zaamo } */ + /* { dg-add-options riscv_ztso } */ + /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + /* { dg-final { check-function-bodies "**" "" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-4.c +index 815a72f1e56..14e632ba2f2 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-4.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-4.c +@@ -1,7 +1,7 @@ + /* { dg-do compile } */ + /* Verify that atomic op mappings match the Ztso suggested mapping. */ + /* { dg-options "-O3" } */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zaamo } */ + /* { dg-add-options riscv_ztso } */ + /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + /* { dg-final { check-function-bodies "**" "" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-5.c +index eda6f01096e..74d8df99ddc 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-5.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-5.c +@@ -1,7 +1,7 @@ + /* { dg-do compile } */ + /* Verify that atomic op mappings match the Ztso suggested mapping. */ + /* { dg-options "-O3" } */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zaamo } */ + /* { dg-add-options riscv_ztso } */ + /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + /* { dg-final { check-function-bodies "**" "" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-1.c +index b6315c45e85..46a9f0c918a 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-1.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-1.c +@@ -1,6 +1,6 @@ + /* { dg-do compile } */ + /* Verify that compare exchange mappings match the Ztso suggested mapping. */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zalrsc } */ + /* { dg-add-options riscv_ztso } */ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-2.c +index e487184f6cf..20e325f2e7c 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-2.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-2.c +@@ -1,6 +1,6 @@ + /* { dg-do compile } */ + /* Verify that compare exchange mappings match the Ztso suggested mapping. */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zalrsc } */ + /* { dg-add-options riscv_ztso } */ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-3.c +index e9c925f0923..0a443b461f3 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-3.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-3.c +@@ -1,6 +1,6 @@ + /* { dg-do compile } */ + /* Verify that compare exchange mappings match the Ztso suggested mapping. */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zalrsc } */ + /* { dg-add-options riscv_ztso } */ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-4.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-4.c +index 6b454559633..35e01cdc8be 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-4.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-4.c +@@ -1,6 +1,6 @@ + /* { dg-do compile } */ + /* Verify that compare exchange mappings match the Ztso suggested mapping. */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zalrsc } */ + /* { dg-add-options riscv_ztso } */ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-5.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-5.c +index 02c9f0ada77..cd884931bdf 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-5.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-5.c +@@ -1,6 +1,6 @@ + /* { dg-do compile } */ + /* Verify that compare exchange mappings match the Ztso suggested mapping. */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zalrsc } */ + /* { dg-add-options riscv_ztso } */ + /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-6.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-6.c +index 75abd5d3dfb..7da3b1dce48 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-6.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-6.c +@@ -1,6 +1,6 @@ + /* { dg-do compile } */ + /* Verify that compare exchange mappings match the Ztso suggested mapping. */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zalrsc } */ + /* { dg-add-options riscv_ztso } */ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-7.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-7.c +index 33928c0eac4..53f6e6ace0b 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-7.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-7.c +@@ -1,6 +1,6 @@ + /* { dg-do compile } */ + /* Verify that compare exchange mappings match the Ztso suggested mapping. */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zalrsc } */ + /* { dg-add-options riscv_ztso } */ + /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c +index 2a40d6b1376..5c0a8b8f6e9 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c +@@ -1,6 +1,6 @@ + /* { dg-do compile } */ + /* Verify that subword atomic op mappings match the Ztso suggested mapping. */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zalrsc } */ + /* { dg-add-options riscv_ztso } */ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c +index c79380f2611..551078186ec 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c +@@ -1,6 +1,6 @@ + /* { dg-do compile } */ + /* Verify that subword atomic op mappings match the Ztso suggested mapping. */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zalrsc } */ + /* { dg-add-options riscv_ztso } */ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c +index d1a94eccfa8..5f0f7870721 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c +@@ -1,6 +1,6 @@ + /* { dg-do compile } */ + /* Verify that subword atomic op mappings match the Ztso suggested mapping. */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zalrsc } */ + /* { dg-add-options riscv_ztso } */ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c +index 3d65bc2f64a..24f4f02dcea 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c +@@ -1,6 +1,6 @@ + /* { dg-do compile } */ + /* Verify that subword atomic op mappings match the Ztso suggested mapping. */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zalrsc } */ + /* { dg-add-options riscv_ztso } */ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c +index 10354387a13..405e498fb40 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c +@@ -1,6 +1,6 @@ + /* { dg-do compile } */ + /* Verify that subword atomic op mappings match the Ztso suggested mapping. */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zalrsc } */ + /* { dg-add-options riscv_ztso } */ + /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ +diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp +index 7979f0a17eb..764d36718f8 100644 +--- a/gcc/testsuite/lib/target-supports.exp ++++ b/gcc/testsuite/lib/target-supports.exp +@@ -1910,6 +1910,29 @@ proc check_effective_target_riscv_a { } { + }] + } + ++ ++# Return 1 if the target arch supports the atomic LRSC extension, 0 otherwise. ++# Cache the result. ++ ++proc check_effective_target_riscv_zalrsc { } { ++ return [check_no_compiler_messages riscv_ext_zalrsc assembly { ++ #ifndef __riscv_zalrsc ++ #error "Not __riscv_zalrsc" ++ #endif ++ }] ++} ++ ++# Return 1 if the target arch supports the atomic AMO extension, 0 otherwise. ++# Cache the result. ++ ++proc check_effective_target_riscv_zaamo { } { ++ return [check_no_compiler_messages riscv_ext_zaamo assembly { ++ #ifndef __riscv_zaamo ++ #error "Not __riscv_zaamo" ++ #endif ++ }] ++} ++ + # Return 1 if the target arch supports the double precision floating point + # extension, 0 otherwise. Cache the result. + +@@ -2165,7 +2188,7 @@ proc check_effective_target_riscv_v_misalign_ok { } { + proc riscv_get_arch { } { + set gcc_march "" + # ??? do we neeed to add more extensions to the list below? +- foreach ext { i m a f d q c v zicsr zifencei zfh zba zbb zbc zbs zvbb zvfh ztso } { ++ foreach ext { i m a f d q c v zicsr zifencei zfh zba zbb zbc zbs zvbb zvfh ztso zaamo zalrsc } { + if { [check_no_compiler_messages riscv_ext_$ext assembly [string map [list DEF __riscv_$ext] { + #ifndef DEF + #error "Not DEF" +@@ -2224,6 +2247,30 @@ proc add_options_for_riscv_v { flags } { + return "$flags -march=[regsub {[[:alnum:]]*} [riscv_get_arch] &v]" + } + ++proc add_options_for_riscv_zaamo { flags } { ++ if { [lsearch $flags -march=*] >= 0 } { ++ # If there are multiple -march flags, we have to adjust all of them. ++ set flags [regsub -all -- {(?:^|[[:space:]])-march=[[:alnum:]_.]*} $flags &_zaamo ] ++ return [regsub -all -- {((?:^|[[:space:]])-march=[[:alnum:]_.]*_zaamo[[:alnum:]_.]*)_zaamo} $flags \\1 ] ++ } ++ if { [check_effective_target_riscv_zaamo] } { ++ return "$flags" ++ } ++ return "$flags -march=[riscv_get_arch]_zaamo" ++} ++ ++proc add_options_for_riscv_zalrsc { flags } { ++ if { [lsearch $flags -march=*] >= 0 } { ++ # If there are multiple -march flags, we have to adjust all of them. ++ set flags [regsub -all -- {(?:^|[[:space:]])-march=[[:alnum:]_.]*} $flags &_zalrsc ] ++ return [regsub -all -- {((?:^|[[:space:]])-march=[[:alnum:]_.]*_zalrsc[[:alnum:]_.]*)_zalrsc} $flags \\1 ] ++ } ++ if { [check_effective_target_riscv_zalrsc] } { ++ return "$flags" ++ } ++ return "$flags -march=[riscv_get_arch]_zalrsc" ++} ++ + proc add_options_for_riscv_zfh { flags } { + if { [lsearch $flags -march=*] >= 0 } { + # If there are multiple -march flags, we have to adjust all of them. +-- +2.47.3 + diff --git a/1041-RISC-V-Add-Zalrsc-amo-op-patterns.patch b/1041-RISC-V-Add-Zalrsc-amo-op-patterns.patch new file mode 100644 index 0000000..14bd9e2 --- /dev/null +++ b/1041-RISC-V-Add-Zalrsc-amo-op-patterns.patch @@ -0,0 +1,378 @@ +From 7588bb7444817327181cbfb6705c05794f4ce1ef Mon Sep 17 00:00:00 2001 +From: Patrick O'Neill +Date: Wed, 7 Feb 2024 16:30:30 -0800 +Subject: [PATCH 1041/1087] RISC-V: Add Zalrsc amo-op patterns + +commit 1588983be6112561c805a50eb7a3c585865beffa upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +All amo patterns can be represented with lrsc sequences. +Add these patterns as a fallback when Zaamo is not enabled. + +gcc/ChangeLog: + + * config/riscv/sync.md (atomic_): New expand pattern. + (amo_atomic_): Rename amo pattern. + (atomic_fetch_): New lrsc sequence pattern. + (lrsc_atomic_): New expand pattern. + (amo_atomic_fetch_): Rename amo pattern. + (lrsc_atomic_fetch_): New lrsc sequence pattern. + (atomic_exchange): New expand pattern. + (amo_atomic_exchange): Rename amo pattern. + (lrsc_atomic_exchange): New lrsc sequence pattern. + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/amo-zaamo-preferred-over-zalrsc.c: New test. + * gcc.target/riscv/amo-zalrsc-amo-add-1.c: New test. + * gcc.target/riscv/amo-zalrsc-amo-add-2.c: New test. + * gcc.target/riscv/amo-zalrsc-amo-add-3.c: New test. + * gcc.target/riscv/amo-zalrsc-amo-add-4.c: New test. + * gcc.target/riscv/amo-zalrsc-amo-add-5.c: New test. + +Signed-off-by: Patrick O'Neill +--- + gcc/config/riscv/sync.md | 124 +++++++++++++++++- + .../riscv/amo-zaamo-preferred-over-zalrsc.c | 17 +++ + .../gcc.target/riscv/amo-zalrsc-amo-add-1.c | 19 +++ + .../gcc.target/riscv/amo-zalrsc-amo-add-2.c | 19 +++ + .../gcc.target/riscv/amo-zalrsc-amo-add-3.c | 19 +++ + .../gcc.target/riscv/amo-zalrsc-amo-add-4.c | 19 +++ + .../gcc.target/riscv/amo-zalrsc-amo-add-5.c | 19 +++ + 7 files changed, 231 insertions(+), 5 deletions(-) + create mode 100644 gcc/testsuite/gcc.target/riscv/amo-zaamo-preferred-over-zalrsc.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-1.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-2.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-3.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-4.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-5.c + +diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md +index f44c69d34f7..ee45040cfb6 100644 +--- a/gcc/config/riscv/sync.md ++++ b/gcc/config/riscv/sync.md +@@ -86,7 +86,24 @@ + DONE; + }) + +-(define_insn "atomic_" ++;; AMO ops ++ ++(define_expand "atomic_" ++ [(any_atomic:GPR (match_operand:GPR 0 "memory_operand") ;; mem location ++ (match_operand:GPR 1 "reg_or_0_operand")) ;; value for op ++ (match_operand:SI 2 "const_int_operand")] ;; model ++ "TARGET_ZAAMO || TARGET_ZALRSC" ++{ ++ if (TARGET_ZAAMO) ++ emit_insn (gen_amo_atomic_ (operands[0], operands[1], ++ operands[2])); ++ else ++ emit_insn (gen_lrsc_atomic_ (operands[0], operands[1], ++ operands[2])); ++ DONE; ++}) ++ ++(define_insn "amo_atomic_" + [(set (match_operand:GPR 0 "memory_operand" "+A") + (unspec_volatile:GPR + [(any_atomic:GPR (match_dup 0) +@@ -98,7 +115,44 @@ + [(set_attr "type" "atomic") + (set (attr "length") (const_int 4))]) + +-(define_insn "atomic_fetch_" ++(define_insn "lrsc_atomic_" ++ [(set (match_operand:GPR 0 "memory_operand" "+A") ++ (unspec_volatile:GPR ++ [(any_atomic:GPR (match_dup 0) ++ (match_operand:GPR 1 "reg_or_0_operand" "rJ")) ++ (match_operand:SI 2 "const_int_operand")] ;; model ++ UNSPEC_SYNC_OLD_OP)) ++ (clobber (match_scratch:GPR 3 "=&r"))] ;; tmp_1 ++ "!TARGET_ZAAMO && TARGET_ZALRSC" ++ { ++ return "1:\;" ++ "lr.%I2\t%3, %0\;" ++ "\t%3, %3, %1\;" ++ "sc.%J2\t%3, %3, %0\;" ++ "bnez\t%3, 1b"; ++ } ++ [(set_attr "type" "atomic") ++ (set (attr "length") (const_int 16))]) ++ ++;; AMO fetch ops ++ ++(define_expand "atomic_fetch_" ++ [(match_operand:GPR 0 "register_operand") ;; old value at mem ++ (any_atomic:GPR (match_operand:GPR 1 "memory_operand") ;; mem location ++ (match_operand:GPR 2 "reg_or_0_operand")) ;; value for op ++ (match_operand:SI 3 "const_int_operand")] ;; model ++ "TARGET_ZAAMO || TARGET_ZALRSC" ++ { ++ if (TARGET_ZAAMO) ++ emit_insn (gen_amo_atomic_fetch_ (operands[0], operands[1], ++ operands[2], operands[3])); ++ else ++ emit_insn (gen_lrsc_atomic_fetch_ (operands[0], operands[1], ++ operands[2], operands[3])); ++ DONE; ++ }) ++ ++(define_insn "amo_atomic_fetch_" + [(set (match_operand:GPR 0 "register_operand" "=&r") + (match_operand:GPR 1 "memory_operand" "+A")) + (set (match_dup 1) +@@ -112,6 +166,27 @@ + [(set_attr "type" "atomic") + (set (attr "length") (const_int 4))]) + ++(define_insn "lrsc_atomic_fetch_" ++ [(set (match_operand:GPR 0 "register_operand" "=&r") ++ (match_operand:GPR 1 "memory_operand" "+A")) ++ (set (match_dup 1) ++ (unspec_volatile:GPR ++ [(any_atomic:GPR (match_dup 1) ++ (match_operand:GPR 2 "reg_or_0_operand" "rJ")) ++ (match_operand:SI 3 "const_int_operand")] ;; model ++ UNSPEC_SYNC_OLD_OP)) ++ (clobber (match_scratch:GPR 4 "=&r"))] ;; tmp_1 ++ "!TARGET_ZAAMO && TARGET_ZALRSC" ++ { ++ return "1:\;" ++ "lr.%I3\t%0, %1\;" ++ "\t%4, %0, %2\;" ++ "sc.%J3\t%4, %4, %1\;" ++ "bnez\t%4, 1b"; ++ } ++ [(set_attr "type" "atomic") ++ (set (attr "length") (const_int 20))]) ++ + (define_insn "subword_atomic_fetch_strong_" + [(set (match_operand:SI 0 "register_operand" "=&r") ;; old value at mem + (match_operand:SI 1 "memory_operand" "+A")) ;; mem location +@@ -248,7 +323,23 @@ + DONE; + }) + +-(define_insn "atomic_exchange" ++(define_expand "atomic_exchange" ++ [(match_operand:GPR 0 "register_operand") ;; old value at mem ++ (match_operand:GPR 1 "memory_operand") ;; mem location ++ (match_operand:GPR 2 "register_operand") ;; value for op ++ (match_operand:SI 3 "const_int_operand")] ;; model ++ "TARGET_ZAAMO || TARGET_ZALRSC" ++ { ++ if (TARGET_ZAAMO) ++ emit_insn (gen_amo_atomic_exchange (operands[0], operands[1], ++ operands[2], operands[3])); ++ else ++ emit_insn (gen_lrsc_atomic_exchange (operands[0], operands[1], ++ operands[2], operands[3])); ++ DONE; ++ }) ++ ++(define_insn "amo_atomic_exchange" + [(set (match_operand:GPR 0 "register_operand" "=&r") + (unspec_volatile:GPR + [(match_operand:GPR 1 "memory_operand" "+A") +@@ -261,6 +352,26 @@ + [(set_attr "type" "atomic") + (set (attr "length") (const_int 4))]) + ++(define_insn "lrsc_atomic_exchange" ++ [(set (match_operand:GPR 0 "register_operand" "=&r") ++ (unspec_volatile:GPR ++ [(match_operand:GPR 1 "memory_operand" "+A") ++ (match_operand:SI 3 "const_int_operand")] ;; model ++ UNSPEC_SYNC_EXCHANGE)) ++ (set (match_dup 1) ++ (match_operand:GPR 2 "register_operand" "0")) ++ (clobber (match_scratch:GPR 4 "=&r"))] ;; tmp_1 ++ "!TARGET_ZAAMO && TARGET_ZALRSC" ++ { ++ return "1:\;" ++ "lr.%I3\t%4, %1\;" ++ "sc.%J3\t%0, %0, %1\;" ++ "bnez\t%0, 1b\;" ++ "mv\t%0, %4"; ++ } ++ [(set_attr "type" "atomic") ++ (set (attr "length") (const_int 20))]) ++ + (define_expand "atomic_exchange" + [(match_operand:SHORT 0 "register_operand") ;; old value at mem + (match_operand:SHORT 1 "memory_operand") ;; mem location +@@ -517,7 +628,7 @@ + [(match_operand:QI 0 "register_operand" "") ;; bool output + (match_operand:QI 1 "memory_operand" "+A") ;; memory + (match_operand:SI 2 "const_int_operand" "")] ;; model +- "TARGET_ZALRSC" ++ "TARGET_ZAAMO || TARGET_ZALRSC" + { + /* We have no QImode atomics, so use the address LSBs to form a mask, + then use an aligned SImode atomic. */ +@@ -538,7 +649,10 @@ + rtx shifted_set = gen_reg_rtx (SImode); + riscv_lshift_subword (QImode, set, shift, &shifted_set); + +- emit_insn (gen_atomic_fetch_orsi (old, aligned_mem, shifted_set, model)); ++ if (TARGET_ZAAMO) ++ emit_insn (gen_amo_atomic_fetch_orsi (old, aligned_mem, shifted_set, model)); ++ else if (TARGET_ZALRSC) ++ emit_insn (gen_lrsc_atomic_fetch_orsi (old, aligned_mem, shifted_set, model)); + + emit_move_insn (old, gen_rtx_ASHIFTRT (SImode, old, + gen_lowpart (QImode, shift))); +diff --git a/gcc/testsuite/gcc.target/riscv/amo-zaamo-preferred-over-zalrsc.c b/gcc/testsuite/gcc.target/riscv/amo-zaamo-preferred-over-zalrsc.c +new file mode 100644 +index 00000000000..1c124c2b8b1 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo-zaamo-preferred-over-zalrsc.c +@@ -0,0 +1,17 @@ ++/* { dg-do compile } */ ++/* Ensure that AMO ops are emitted when both zalrsc and zaamo are enabled. */ ++/* { dg-options "-O3" } */ ++/* { dg-add-options riscv_zalrsc } */ ++/* { dg-add-options riscv_zaamo } */ ++/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ ++/* { dg-final { check-function-bodies "**" "" } } */ ++ ++/* ++** foo: ++** amoadd\.w\tzero,a1,0\(a0\) ++** ret ++*/ ++void foo (int* bar, int* baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_RELAXED); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-1.c +new file mode 100644 +index 00000000000..3fa74332433 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-1.c +@@ -0,0 +1,19 @@ ++/* { dg-do compile } */ ++/* Verify that lrsc atomic op mappings match Table A.6's recommended mapping. */ ++/* { dg-options "-O3 -march=rv64id_zalrsc -mabi=lp64d" } */ ++/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ ++/* { dg-final { check-function-bodies "**" "" } } */ ++ ++/* ++** foo: ++** 1: ++** lr.w\t[atx][0-9]+, 0\(a0\) ++** add\t[atx][0-9]+, [atx][0-9]+, a1 ++** sc.w\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) ++** bnez\t[atx][0-9]+, 1b ++** ret ++*/ ++void foo (int* bar, int* baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_RELAXED); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-2.c +new file mode 100644 +index 00000000000..af0a2d50d38 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-2.c +@@ -0,0 +1,19 @@ ++/* { dg-do compile } */ ++/* Verify that lrsc atomic op mappings match Table A.6's recommended mapping. */ ++/* { dg-options "-O3 -march=rv64id_zalrsc -mabi=lp64d" } */ ++/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ ++/* { dg-final { check-function-bodies "**" "" } } */ ++ ++/* ++** foo: ++** 1: ++** lr.w.aq\t[atx][0-9]+, 0\(a0\) ++** add\t[atx][0-9]+, [atx][0-9]+, a1 ++** sc.w\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) ++** bnez\t[atx][0-9]+, 1b ++** ret ++*/ ++void foo (int* bar, int* baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_ACQUIRE); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-3.c +new file mode 100644 +index 00000000000..521869b2165 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-3.c +@@ -0,0 +1,19 @@ ++/* { dg-do compile } */ ++/* Verify that lrsc atomic op mappings match Table A.6's recommended mapping. */ ++/* { dg-options "-O3 -march=rv64id_zalrsc -mabi=lp64d" } */ ++/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ ++/* { dg-final { check-function-bodies "**" "" } } */ ++ ++/* ++** foo: ++** 1: ++** lr.w\t[atx][0-9]+, 0\(a0\) ++** add\t[atx][0-9]+, [atx][0-9]+, a1 ++** sc.w.rl\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) ++** bnez\t[atx][0-9]+, 1b ++** ret ++*/ ++void foo (int* bar, int* baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_RELEASE); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-4.c +new file mode 100644 +index 00000000000..8b6e7579f6f +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-4.c +@@ -0,0 +1,19 @@ ++/* { dg-do compile } */ ++/* Verify that lrsc atomic op mappings match Table A.6's recommended mapping. */ ++/* { dg-options "-O3 -march=rv64id_zalrsc -mabi=lp64d" } */ ++/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ ++/* { dg-final { check-function-bodies "**" "" } } */ ++ ++/* ++** foo: ++** 1: ++** lr.w.aq\t[atx][0-9]+, 0\(a0\) ++** add\t[atx][0-9]+, [atx][0-9]+, a1 ++** sc.w.rl\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) ++** bnez\t[atx][0-9]+, 1b ++** ret ++*/ ++void foo (int* bar, int* baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_ACQ_REL); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-5.c +new file mode 100644 +index 00000000000..0bdc47d5c46 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-5.c +@@ -0,0 +1,19 @@ ++/* { dg-do compile } */ ++/* Verify that lrsc atomic op mappings match Table A.6's recommended mapping. */ ++/* { dg-options "-O3 -march=rv64id_zalrsc -mabi=lp64d" } */ ++/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ ++/* { dg-final { check-function-bodies "**" "" } } */ ++ ++/* ++** foo: ++** 1: ++** lr.w.aqrl\t[atx][0-9]+, 0\(a0\) ++** add\t[atx][0-9]+, [atx][0-9]+, a1 ++** sc.w.rl\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) ++** bnez\t[atx][0-9]+, 1b ++** ret ++*/ ++void foo (int* bar, int* baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_SEQ_CST); ++} +-- +2.47.3 + diff --git a/1042-RISC-V-Move-amo-tests-into-subfolder.patch b/1042-RISC-V-Move-amo-tests-into-subfolder.patch new file mode 100644 index 0000000..7b25910 --- /dev/null +++ b/1042-RISC-V-Move-amo-tests-into-subfolder.patch @@ -0,0 +1,648 @@ +From c791648672eefc0231536291513c8ef68f93e789 Mon Sep 17 00:00:00 2001 +From: Patrick O'Neill +Date: Mon, 10 Jun 2024 16:32:11 -0700 +Subject: [PATCH 1042/1087] RISC-V: Move amo tests into subfolder + +commit 8c944f2559ff279ed7e04c2a75881c04c0c31a9b upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +There's a large number of atomic related testcases in the riscv folder. +Move them into a subfolder similar to what was done for rvv testcases. + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/amo-table-a-6-amo-add-1.c: Move to... + * gcc.target/riscv/amo/amo-table-a-6-amo-add-1.c: ...here. + * gcc.target/riscv/amo-table-a-6-amo-add-2.c: Move to... + * gcc.target/riscv/amo/amo-table-a-6-amo-add-2.c: ...here. + * gcc.target/riscv/amo-table-a-6-amo-add-3.c: Move to... + * gcc.target/riscv/amo/amo-table-a-6-amo-add-3.c: ...here. + * gcc.target/riscv/amo-table-a-6-amo-add-4.c: Move to... + * gcc.target/riscv/amo/amo-table-a-6-amo-add-4.c: ...here. + * gcc.target/riscv/amo-table-a-6-amo-add-5.c: Move to... + * gcc.target/riscv/amo/amo-table-a-6-amo-add-5.c: ...here. + * gcc.target/riscv/amo-table-a-6-compare-exchange-1.c: Move to... + * gcc.target/riscv/amo/amo-table-a-6-compare-exchange-1.c: ...here. + * gcc.target/riscv/amo-table-a-6-compare-exchange-2.c: Move to... + * gcc.target/riscv/amo/amo-table-a-6-compare-exchange-2.c: ...here. + * gcc.target/riscv/amo-table-a-6-compare-exchange-3.c: Move to... + * gcc.target/riscv/amo/amo-table-a-6-compare-exchange-3.c: ...here. + * gcc.target/riscv/amo-table-a-6-compare-exchange-4.c: Move to... + * gcc.target/riscv/amo/amo-table-a-6-compare-exchange-4.c: ...here. + * gcc.target/riscv/amo-table-a-6-compare-exchange-5.c: Move to... + * gcc.target/riscv/amo/amo-table-a-6-compare-exchange-5.c: ...here. + * gcc.target/riscv/amo-table-a-6-compare-exchange-6.c: Move to... + * gcc.target/riscv/amo/amo-table-a-6-compare-exchange-6.c: ...here. + * gcc.target/riscv/amo-table-a-6-compare-exchange-7.c: Move to... + * gcc.target/riscv/amo/amo-table-a-6-compare-exchange-7.c: ...here. + * gcc.target/riscv/amo-table-a-6-fence-1.c: Move to... + * gcc.target/riscv/amo/amo-table-a-6-fence-1.c: ...here. + * gcc.target/riscv/amo-table-a-6-fence-2.c: Move to... + * gcc.target/riscv/amo/amo-table-a-6-fence-2.c: ...here. + * gcc.target/riscv/amo-table-a-6-fence-3.c: Move to... + * gcc.target/riscv/amo/amo-table-a-6-fence-3.c: ...here. + * gcc.target/riscv/amo-table-a-6-fence-4.c: Move to... + * gcc.target/riscv/amo/amo-table-a-6-fence-4.c: ...here. + * gcc.target/riscv/amo-table-a-6-fence-5.c: Move to... + * gcc.target/riscv/amo/amo-table-a-6-fence-5.c: ...here. + * gcc.target/riscv/amo-table-a-6-load-1.c: Move to... + * gcc.target/riscv/amo/amo-table-a-6-load-1.c: ...here. + * gcc.target/riscv/amo-table-a-6-load-2.c: Move to... + * gcc.target/riscv/amo/amo-table-a-6-load-2.c: ...here. + * gcc.target/riscv/amo-table-a-6-load-3.c: Move to... + * gcc.target/riscv/amo/amo-table-a-6-load-3.c: ...here. + * gcc.target/riscv/amo-table-a-6-store-1.c: Move to... + * gcc.target/riscv/amo/amo-table-a-6-store-1.c: ...here. + * gcc.target/riscv/amo-table-a-6-store-2.c: Move to... + * gcc.target/riscv/amo/amo-table-a-6-store-2.c: ...here. + * gcc.target/riscv/amo-table-a-6-store-compat-3.c: Move to... + * gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c: ...here. + * gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c: Move to... + * gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-1.c: ...here. + * gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c: Move to... + * gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-2.c: ...here. + * gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c: Move to... + * gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-3.c: ...here. + * gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c: Move to... + * gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-4.c: ...here. + * gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c: Move to... + * gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-5.c: ...here. + * gcc.target/riscv/amo-table-ztso-amo-add-1.c: Move to... + * gcc.target/riscv/amo/amo-table-ztso-amo-add-1.c: ...here. + * gcc.target/riscv/amo-table-ztso-amo-add-2.c: Move to... + * gcc.target/riscv/amo/amo-table-ztso-amo-add-2.c: ...here. + * gcc.target/riscv/amo-table-ztso-amo-add-3.c: Move to... + * gcc.target/riscv/amo/amo-table-ztso-amo-add-3.c: ...here. + * gcc.target/riscv/amo-table-ztso-amo-add-4.c: Move to... + * gcc.target/riscv/amo/amo-table-ztso-amo-add-4.c: ...here. + * gcc.target/riscv/amo-table-ztso-amo-add-5.c: Move to... + * gcc.target/riscv/amo/amo-table-ztso-amo-add-5.c: ...here. + * gcc.target/riscv/amo-table-ztso-compare-exchange-1.c: Move to... + * gcc.target/riscv/amo/amo-table-ztso-compare-exchange-1.c: ...here. + * gcc.target/riscv/amo-table-ztso-compare-exchange-2.c: Move to... + * gcc.target/riscv/amo/amo-table-ztso-compare-exchange-2.c: ...here. + * gcc.target/riscv/amo-table-ztso-compare-exchange-3.c: Move to... + * gcc.target/riscv/amo/amo-table-ztso-compare-exchange-3.c: ...here. + * gcc.target/riscv/amo-table-ztso-compare-exchange-4.c: Move to... + * gcc.target/riscv/amo/amo-table-ztso-compare-exchange-4.c: ...here. + * gcc.target/riscv/amo-table-ztso-compare-exchange-5.c: Move to... + * gcc.target/riscv/amo/amo-table-ztso-compare-exchange-5.c: ...here. + * gcc.target/riscv/amo-table-ztso-compare-exchange-6.c: Move to... + * gcc.target/riscv/amo/amo-table-ztso-compare-exchange-6.c: ...here. + * gcc.target/riscv/amo-table-ztso-compare-exchange-7.c: Move to... + * gcc.target/riscv/amo/amo-table-ztso-compare-exchange-7.c: ...here. + * gcc.target/riscv/amo-table-ztso-fence-1.c: Move to... + * gcc.target/riscv/amo/amo-table-ztso-fence-1.c: ...here. + * gcc.target/riscv/amo-table-ztso-fence-2.c: Move to... + * gcc.target/riscv/amo/amo-table-ztso-fence-2.c: ...here. + * gcc.target/riscv/amo-table-ztso-fence-3.c: Move to... + * gcc.target/riscv/amo/amo-table-ztso-fence-3.c: ...here. + * gcc.target/riscv/amo-table-ztso-fence-4.c: Move to... + * gcc.target/riscv/amo/amo-table-ztso-fence-4.c: ...here. + * gcc.target/riscv/amo-table-ztso-fence-5.c: Move to... + * gcc.target/riscv/amo/amo-table-ztso-fence-5.c: ...here. + * gcc.target/riscv/amo-table-ztso-load-1.c: Move to... + * gcc.target/riscv/amo/amo-table-ztso-load-1.c: ...here. + * gcc.target/riscv/amo-table-ztso-load-2.c: Move to... + * gcc.target/riscv/amo/amo-table-ztso-load-2.c: ...here. + * gcc.target/riscv/amo-table-ztso-load-3.c: Move to... + * gcc.target/riscv/amo/amo-table-ztso-load-3.c: ...here. + * gcc.target/riscv/amo-table-ztso-store-1.c: Move to... + * gcc.target/riscv/amo/amo-table-ztso-store-1.c: ...here. + * gcc.target/riscv/amo-table-ztso-store-2.c: Move to... + * gcc.target/riscv/amo/amo-table-ztso-store-2.c: ...here. + * gcc.target/riscv/amo-table-ztso-store-3.c: Move to... + * gcc.target/riscv/amo/amo-table-ztso-store-3.c: ...here. + * gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c: Move to... + * gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-1.c: ...here. + * gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c: Move to... + * gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-2.c: ...here. + * gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c: Move to... + * gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-3.c: ...here. + * gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c: Move to... + * gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-4.c: ...here. + * gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c: Move to... + * gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-5.c: ...here. + * gcc.target/riscv/amo-zaamo-preferred-over-zalrsc.c: Move to... + * gcc.target/riscv/amo/amo-zaamo-preferred-over-zalrsc.c: ...here. + * gcc.target/riscv/amo-zalrsc-amo-add-1.c: Move to... + * gcc.target/riscv/amo/amo-zalrsc-amo-add-1.c: ...here. + * gcc.target/riscv/amo-zalrsc-amo-add-2.c: Move to... + * gcc.target/riscv/amo/amo-zalrsc-amo-add-2.c: ...here. + * gcc.target/riscv/amo-zalrsc-amo-add-3.c: Move to... + * gcc.target/riscv/amo/amo-zalrsc-amo-add-3.c: ...here. + * gcc.target/riscv/amo-zalrsc-amo-add-4.c: Move to... + * gcc.target/riscv/amo/amo-zalrsc-amo-add-4.c: ...here. + * gcc.target/riscv/amo-zalrsc-amo-add-5.c: Move to... + * gcc.target/riscv/amo/amo-zalrsc-amo-add-5.c: ...here. + * gcc.target/riscv/inline-atomics-1.c: Move to... + * gcc.target/riscv/amo/inline-atomics-1.c: ...here. + * gcc.target/riscv/inline-atomics-2.c: Move to... + * gcc.target/riscv/amo/inline-atomics-2.c: ...here. + * gcc.target/riscv/inline-atomics-3.c: Move to... + * gcc.target/riscv/amo/inline-atomics-3.c: ...here. + * gcc.target/riscv/inline-atomics-4.c: Move to... + * gcc.target/riscv/amo/inline-atomics-4.c: ...here. + * gcc.target/riscv/inline-atomics-5.c: Move to... + * gcc.target/riscv/amo/inline-atomics-5.c: ...here. + * gcc.target/riscv/inline-atomics-6.c: Move to... + * gcc.target/riscv/amo/inline-atomics-6.c: ...here. + * gcc.target/riscv/inline-atomics-7.c: Move to... + * gcc.target/riscv/amo/inline-atomics-7.c: ...here. + * gcc.target/riscv/inline-atomics-8.c: Move to... + * gcc.target/riscv/amo/inline-atomics-8.c: ...here. + * gcc.target/riscv/pr114130.c: Move to... + * gcc.target/riscv/amo/pr114130.c: ...here. + * gcc.target/riscv/pr89835.c: Move to... + * gcc.target/riscv/amo/pr89835.c: ...here. + * gcc.target/riscv/amo/amo.exp: New file. + +Signed-off-by: Patrick O'Neill +--- + .../riscv/{ => amo}/amo-table-a-6-amo-add-1.c | 0 + .../riscv/{ => amo}/amo-table-a-6-amo-add-2.c | 0 + .../riscv/{ => amo}/amo-table-a-6-amo-add-3.c | 0 + .../riscv/{ => amo}/amo-table-a-6-amo-add-4.c | 0 + .../riscv/{ => amo}/amo-table-a-6-amo-add-5.c | 0 + .../amo-table-a-6-compare-exchange-1.c | 0 + .../amo-table-a-6-compare-exchange-2.c | 0 + .../amo-table-a-6-compare-exchange-3.c | 0 + .../amo-table-a-6-compare-exchange-4.c | 0 + .../amo-table-a-6-compare-exchange-5.c | 0 + .../amo-table-a-6-compare-exchange-6.c | 0 + .../amo-table-a-6-compare-exchange-7.c | 0 + .../riscv/{ => amo}/amo-table-a-6-fence-1.c | 0 + .../riscv/{ => amo}/amo-table-a-6-fence-2.c | 0 + .../riscv/{ => amo}/amo-table-a-6-fence-3.c | 0 + .../riscv/{ => amo}/amo-table-a-6-fence-4.c | 0 + .../riscv/{ => amo}/amo-table-a-6-fence-5.c | 0 + .../riscv/{ => amo}/amo-table-a-6-load-1.c | 0 + .../riscv/{ => amo}/amo-table-a-6-load-2.c | 0 + .../riscv/{ => amo}/amo-table-a-6-load-3.c | 0 + .../riscv/{ => amo}/amo-table-a-6-store-1.c | 0 + .../riscv/{ => amo}/amo-table-a-6-store-2.c | 0 + .../{ => amo}/amo-table-a-6-store-compat-3.c | 0 + .../amo-table-a-6-subword-amo-add-1.c | 0 + .../amo-table-a-6-subword-amo-add-2.c | 0 + .../amo-table-a-6-subword-amo-add-3.c | 0 + .../amo-table-a-6-subword-amo-add-4.c | 0 + .../amo-table-a-6-subword-amo-add-5.c | 0 + .../{ => amo}/amo-table-ztso-amo-add-1.c | 0 + .../{ => amo}/amo-table-ztso-amo-add-2.c | 0 + .../{ => amo}/amo-table-ztso-amo-add-3.c | 0 + .../{ => amo}/amo-table-ztso-amo-add-4.c | 0 + .../{ => amo}/amo-table-ztso-amo-add-5.c | 0 + .../amo-table-ztso-compare-exchange-1.c | 0 + .../amo-table-ztso-compare-exchange-2.c | 0 + .../amo-table-ztso-compare-exchange-3.c | 0 + .../amo-table-ztso-compare-exchange-4.c | 0 + .../amo-table-ztso-compare-exchange-5.c | 0 + .../amo-table-ztso-compare-exchange-6.c | 0 + .../amo-table-ztso-compare-exchange-7.c | 0 + .../riscv/{ => amo}/amo-table-ztso-fence-1.c | 0 + .../riscv/{ => amo}/amo-table-ztso-fence-2.c | 0 + .../riscv/{ => amo}/amo-table-ztso-fence-3.c | 0 + .../riscv/{ => amo}/amo-table-ztso-fence-4.c | 0 + .../riscv/{ => amo}/amo-table-ztso-fence-5.c | 0 + .../riscv/{ => amo}/amo-table-ztso-load-1.c | 0 + .../riscv/{ => amo}/amo-table-ztso-load-2.c | 0 + .../riscv/{ => amo}/amo-table-ztso-load-3.c | 0 + .../riscv/{ => amo}/amo-table-ztso-store-1.c | 0 + .../riscv/{ => amo}/amo-table-ztso-store-2.c | 0 + .../riscv/{ => amo}/amo-table-ztso-store-3.c | 0 + .../amo-table-ztso-subword-amo-add-1.c | 0 + .../amo-table-ztso-subword-amo-add-2.c | 0 + .../amo-table-ztso-subword-amo-add-3.c | 0 + .../amo-table-ztso-subword-amo-add-4.c | 0 + .../amo-table-ztso-subword-amo-add-5.c | 0 + .../amo-zaamo-preferred-over-zalrsc.c | 0 + .../riscv/{ => amo}/amo-zalrsc-amo-add-1.c | 0 + .../riscv/{ => amo}/amo-zalrsc-amo-add-2.c | 0 + .../riscv/{ => amo}/amo-zalrsc-amo-add-3.c | 0 + .../riscv/{ => amo}/amo-zalrsc-amo-add-4.c | 0 + .../riscv/{ => amo}/amo-zalrsc-amo-add-5.c | 0 + gcc/testsuite/gcc.target/riscv/amo/amo.exp | 41 +++++++++++++++++++ + .../riscv/{ => amo}/inline-atomics-1.c | 0 + .../riscv/{ => amo}/inline-atomics-2.c | 0 + .../riscv/{ => amo}/inline-atomics-3.c | 0 + .../riscv/{ => amo}/inline-atomics-4.c | 0 + .../riscv/{ => amo}/inline-atomics-5.c | 0 + .../riscv/{ => amo}/inline-atomics-6.c | 0 + .../riscv/{ => amo}/inline-atomics-7.c | 0 + .../riscv/{ => amo}/inline-atomics-8.c | 0 + .../gcc.target/riscv/{ => amo}/pr114130.c | 0 + .../gcc.target/riscv/{ => amo}/pr89835.c | 0 + 73 files changed, 41 insertions(+) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-a-6-amo-add-1.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-a-6-amo-add-2.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-a-6-amo-add-3.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-a-6-amo-add-4.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-a-6-amo-add-5.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-a-6-compare-exchange-1.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-a-6-compare-exchange-2.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-a-6-compare-exchange-3.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-a-6-compare-exchange-4.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-a-6-compare-exchange-5.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-a-6-compare-exchange-6.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-a-6-compare-exchange-7.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-a-6-fence-1.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-a-6-fence-2.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-a-6-fence-3.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-a-6-fence-4.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-a-6-fence-5.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-a-6-load-1.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-a-6-load-2.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-a-6-load-3.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-a-6-store-1.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-a-6-store-2.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-a-6-store-compat-3.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-a-6-subword-amo-add-1.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-a-6-subword-amo-add-2.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-a-6-subword-amo-add-3.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-a-6-subword-amo-add-4.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-a-6-subword-amo-add-5.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-ztso-amo-add-1.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-ztso-amo-add-2.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-ztso-amo-add-3.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-ztso-amo-add-4.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-ztso-amo-add-5.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-ztso-compare-exchange-1.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-ztso-compare-exchange-2.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-ztso-compare-exchange-3.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-ztso-compare-exchange-4.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-ztso-compare-exchange-5.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-ztso-compare-exchange-6.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-ztso-compare-exchange-7.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-ztso-fence-1.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-ztso-fence-2.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-ztso-fence-3.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-ztso-fence-4.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-ztso-fence-5.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-ztso-load-1.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-ztso-load-2.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-ztso-load-3.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-ztso-store-1.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-ztso-store-2.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-ztso-store-3.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-ztso-subword-amo-add-1.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-ztso-subword-amo-add-2.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-ztso-subword-amo-add-3.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-ztso-subword-amo-add-4.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-ztso-subword-amo-add-5.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-zaamo-preferred-over-zalrsc.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-zalrsc-amo-add-1.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-zalrsc-amo-add-2.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-zalrsc-amo-add-3.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-zalrsc-amo-add-4.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-zalrsc-amo-add-5.c (100%) + create mode 100644 gcc/testsuite/gcc.target/riscv/amo/amo.exp + rename gcc/testsuite/gcc.target/riscv/{ => amo}/inline-atomics-1.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/inline-atomics-2.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/inline-atomics-3.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/inline-atomics-4.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/inline-atomics-5.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/inline-atomics-6.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/inline-atomics-7.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/inline-atomics-8.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/pr114130.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/pr89835.c (100%) + +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-1.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-1.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-2.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-2.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-3.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-3.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-4.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-4.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-5.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-5.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-1.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-1.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-2.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-2.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-3.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-3.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-4.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-4.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-5.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-5.c +diff --git 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to gcc/testsuite/gcc.target/riscv/amo/amo-zaamo-preferred-over-zalrsc.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-1.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-1.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-1.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-2.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-2.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-2.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-3.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-3.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-3.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-4.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-4.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-4.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-5.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-5.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-5.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo.exp b/gcc/testsuite/gcc.target/riscv/amo/amo.exp +new file mode 100644 +index 00000000000..2806f4bda7a +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo.exp +@@ -0,0 +1,41 @@ ++# Copyright (C) 2024-2024 Free Software Foundation, Inc. ++ ++# This program is free software; you can redistribute it and/or modify ++# it under the terms of the GNU General Public License as published by ++# the Free Software Foundation; either version 3 of the License, or ++# (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with GCC; see the file COPYING3. If not see ++# . ++ ++# GCC testsuite that uses the `dg.exp' driver. ++ ++# Exit immediately if this isn't a RISC-V target. ++if ![istarget riscv*-*-*] then { ++ return ++} ++ ++# Load support procs. ++load_lib gcc-dg.exp ++ ++# If a testcase doesn't have special options, use these. ++global DEFAULT_CFLAGS ++if ![info exists DEFAULT_CFLAGS] then { ++ set DEFAULT_CFLAGS " -ansi -pedantic-errors" ++} ++ ++# Initialize `dg'. ++dg-init ++ ++# Main loop. ++dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \ ++ "" $DEFAULT_CFLAGS ++ ++# All done. ++dg-finish +diff --git a/gcc/testsuite/gcc.target/riscv/inline-atomics-1.c b/gcc/testsuite/gcc.target/riscv/amo/inline-atomics-1.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/inline-atomics-1.c +rename to gcc/testsuite/gcc.target/riscv/amo/inline-atomics-1.c +diff --git a/gcc/testsuite/gcc.target/riscv/inline-atomics-2.c b/gcc/testsuite/gcc.target/riscv/amo/inline-atomics-2.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/inline-atomics-2.c +rename to gcc/testsuite/gcc.target/riscv/amo/inline-atomics-2.c +diff --git a/gcc/testsuite/gcc.target/riscv/inline-atomics-3.c b/gcc/testsuite/gcc.target/riscv/amo/inline-atomics-3.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/inline-atomics-3.c +rename to gcc/testsuite/gcc.target/riscv/amo/inline-atomics-3.c +diff --git a/gcc/testsuite/gcc.target/riscv/inline-atomics-4.c b/gcc/testsuite/gcc.target/riscv/amo/inline-atomics-4.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/inline-atomics-4.c +rename to gcc/testsuite/gcc.target/riscv/amo/inline-atomics-4.c +diff --git a/gcc/testsuite/gcc.target/riscv/inline-atomics-5.c b/gcc/testsuite/gcc.target/riscv/amo/inline-atomics-5.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/inline-atomics-5.c +rename to gcc/testsuite/gcc.target/riscv/amo/inline-atomics-5.c +diff --git a/gcc/testsuite/gcc.target/riscv/inline-atomics-6.c b/gcc/testsuite/gcc.target/riscv/amo/inline-atomics-6.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/inline-atomics-6.c +rename to gcc/testsuite/gcc.target/riscv/amo/inline-atomics-6.c +diff --git a/gcc/testsuite/gcc.target/riscv/inline-atomics-7.c b/gcc/testsuite/gcc.target/riscv/amo/inline-atomics-7.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/inline-atomics-7.c +rename to gcc/testsuite/gcc.target/riscv/amo/inline-atomics-7.c +diff --git a/gcc/testsuite/gcc.target/riscv/inline-atomics-8.c b/gcc/testsuite/gcc.target/riscv/amo/inline-atomics-8.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/inline-atomics-8.c +rename to gcc/testsuite/gcc.target/riscv/amo/inline-atomics-8.c +diff --git a/gcc/testsuite/gcc.target/riscv/pr114130.c b/gcc/testsuite/gcc.target/riscv/amo/pr114130.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/pr114130.c +rename to gcc/testsuite/gcc.target/riscv/amo/pr114130.c +diff --git a/gcc/testsuite/gcc.target/riscv/pr89835.c b/gcc/testsuite/gcc.target/riscv/amo/pr89835.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/pr89835.c +rename to gcc/testsuite/gcc.target/riscv/amo/pr89835.c +-- +2.47.3 + diff --git a/1043-RISC-V-Fix-amoadd-call-arguments.patch b/1043-RISC-V-Fix-amoadd-call-arguments.patch new file mode 100644 index 0000000..07e2983 --- /dev/null +++ b/1043-RISC-V-Fix-amoadd-call-arguments.patch @@ -0,0 +1,413 @@ +From 54e64ef0a3880fe53e73743128d646c3e914e21b Mon Sep 17 00:00:00 2001 +From: Patrick O'Neill +Date: Mon, 10 Jun 2024 16:58:12 -0700 +Subject: [PATCH 1043/1087] RISC-V: Fix amoadd call arguments + +commit 6343adcef7de1a1214c9b6dd845810aa4a0d19e5 upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +Update __atomic_add_fetch arguments to be a pointer and value rather +than two pointers. + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/amo/amo-table-a-6-amo-add-1.c: Update + __atomic_add_fetch args. + * gcc.target/riscv/amo/amo-table-a-6-amo-add-2.c: Ditto. + * gcc.target/riscv/amo/amo-table-a-6-amo-add-3.c: Ditto. + * gcc.target/riscv/amo/amo-table-a-6-amo-add-4.c: Ditto. + * gcc.target/riscv/amo/amo-table-a-6-amo-add-5.c: Ditto. + * gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-1.c: Ditto. + * gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-2.c: Ditto. + * gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-3.c: Ditto. + * gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-4.c: Ditto. + * gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-5.c: Ditto. + * gcc.target/riscv/amo/amo-table-ztso-amo-add-1.c: Ditto. + * gcc.target/riscv/amo/amo-table-ztso-amo-add-2.c: Ditto. + * gcc.target/riscv/amo/amo-table-ztso-amo-add-3.c: Ditto. + * gcc.target/riscv/amo/amo-table-ztso-amo-add-4.c: Ditto. + * gcc.target/riscv/amo/amo-table-ztso-amo-add-5.c: Ditto. + * gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-1.c: Ditto. + * gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-2.c: Ditto. + * gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-3.c: Ditto. + * gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-4.c: Ditto. + * gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-5.c: Ditto. + * gcc.target/riscv/amo/amo-zaamo-preferred-over-zalrsc.c: Ditto. + * gcc.target/riscv/amo/amo-zalrsc-amo-add-1.c: Ditto. + * gcc.target/riscv/amo/amo-zalrsc-amo-add-2.c: Ditto. + * gcc.target/riscv/amo/amo-zalrsc-amo-add-3.c: Ditto. + * gcc.target/riscv/amo/amo-zalrsc-amo-add-4.c: Ditto. + * gcc.target/riscv/amo/amo-zalrsc-amo-add-5.c: Ditto. + +Signed-off-by: Patrick O'Neill +--- + gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-1.c | 2 +- + gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-2.c | 2 +- + gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-3.c | 2 +- + gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-4.c | 2 +- + gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-5.c | 2 +- + .../gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-1.c | 2 +- + .../gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-2.c | 2 +- + .../gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-3.c | 2 +- + .../gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-4.c | 2 +- + .../gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-5.c | 2 +- + gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-1.c | 2 +- + gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-2.c | 2 +- + gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-3.c | 2 +- + gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-4.c | 2 +- + gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-5.c | 2 +- + .../gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-1.c | 2 +- + .../gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-2.c | 2 +- + .../gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-3.c | 2 +- + .../gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-4.c | 2 +- + .../gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-5.c | 2 +- + .../gcc.target/riscv/amo/amo-zaamo-preferred-over-zalrsc.c | 2 +- + gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-1.c | 2 +- + gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-2.c | 2 +- + gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-3.c | 2 +- + gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-4.c | 2 +- + gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-5.c | 2 +- + 26 files changed, 26 insertions(+), 26 deletions(-) + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-1.c +index 9c2ba39789a..2e53abf28aa 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-1.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-1.c +@@ -10,7 +10,7 @@ + ** amoadd\.w\tzero,a1,0\(a0\) + ** ret + */ +-void foo (int* bar, int* baz) ++void foo (int* bar, int baz) + { + __atomic_add_fetch(bar, baz, __ATOMIC_RELAXED); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-2.c +index b7682a5bab4..14d6b7e4b1b 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-2.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-2.c +@@ -10,7 +10,7 @@ + ** amoadd\.w\.aq\tzero,a1,0\(a0\) + ** ret + */ +-void foo (int* bar, int* baz) ++void foo (int* bar, int baz) + { + __atomic_add_fetch(bar, baz, __ATOMIC_ACQUIRE); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-3.c +index c8776872d91..937a00daf4c 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-3.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-3.c +@@ -10,7 +10,7 @@ + ** amoadd\.w\.rl\tzero,a1,0\(a0\) + ** ret + */ +-void foo (int* bar, int* baz) ++void foo (int* bar, int baz) + { + __atomic_add_fetch(bar, baz, __ATOMIC_RELEASE); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-4.c +index b37c4c3f242..7d7f4e11dd4 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-4.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-4.c +@@ -10,7 +10,7 @@ + ** amoadd\.w\.aqrl\tzero,a1,0\(a0\) + ** ret + */ +-void foo (int* bar, int* baz) ++void foo (int* bar, int baz) + { + __atomic_add_fetch(bar, baz, __ATOMIC_ACQ_REL); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-5.c +index 8d45ca7a347..e5cf1e2e9cf 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-5.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-5.c +@@ -10,7 +10,7 @@ + ** amoadd\.w\.aqrl\tzero,a1,0\(a0\) + ** ret + */ +-void foo (int* bar, int* baz) ++void foo (int* bar, int baz) + { + __atomic_add_fetch(bar, baz, __ATOMIC_SEQ_CST); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-1.c +index 4174fdee352..348b9c8db9c 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-1.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-1.c +@@ -4,7 +4,7 @@ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ + +-void foo (short* bar, short* baz) ++void foo (short* bar, short baz) + { + __atomic_add_fetch(bar, baz, __ATOMIC_RELAXED); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-2.c +index 4c06c90b558..31011580684 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-2.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-2.c +@@ -4,7 +4,7 @@ + /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ + +-void foo (short* bar, short* baz) ++void foo (short* bar, short baz) + { + __atomic_add_fetch(bar, baz, __ATOMIC_ACQUIRE); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-3.c +index 7e791c901b6..38bedcd6b41 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-3.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-3.c +@@ -4,7 +4,7 @@ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ + +-void foo (short* bar, short* baz) ++void foo (short* bar, short baz) + { + __atomic_add_fetch(bar, baz, __ATOMIC_RELEASE); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-4.c +index 76f3be27110..d69610e2d9e 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-4.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-4.c +@@ -4,7 +4,7 @@ + /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ + +-void foo (short* bar, short* baz) ++void foo (short* bar, short baz) + { + __atomic_add_fetch(bar, baz, __ATOMIC_ACQ_REL); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-5.c +index 8dbfa9c4fc8..976f8909bdd 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-5.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-5.c +@@ -4,7 +4,7 @@ + /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ + +-void foo (short* bar, short* baz) ++void foo (short* bar, short baz) + { + __atomic_add_fetch(bar, baz, __ATOMIC_SEQ_CST); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-1.c +index 82169390925..000407a2583 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-1.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-1.c +@@ -11,7 +11,7 @@ + ** amoadd\.w\tzero,a1,0\(a0\) + ** ret + */ +-void foo (int* bar, int* baz) ++void foo (int* bar, int baz) + { + __atomic_add_fetch(bar, baz, __ATOMIC_RELAXED); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-2.c +index a238c6f4403..3e441cadbf3 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-2.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-2.c +@@ -11,7 +11,7 @@ + ** amoadd\.w\tzero,a1,0\(a0\) + ** ret + */ +-void foo (int* bar, int* baz) ++void foo (int* bar, int baz) + { + __atomic_add_fetch(bar, baz, __ATOMIC_ACQUIRE); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-3.c +index c97bf467c63..8af1a2f79a4 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-3.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-3.c +@@ -11,7 +11,7 @@ + ** amoadd\.w\tzero,a1,0\(a0\) + ** ret + */ +-void foo (int* bar, int* baz) ++void foo (int* bar, int baz) + { + __atomic_add_fetch(bar, baz, __ATOMIC_RELEASE); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-4.c +index 14e632ba2f2..0b3a7e59689 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-4.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-4.c +@@ -11,7 +11,7 @@ + ** amoadd\.w\tzero,a1,0\(a0\) + ** ret + */ +-void foo (int* bar, int* baz) ++void foo (int* bar, int baz) + { + __atomic_add_fetch(bar, baz, __ATOMIC_ACQ_REL); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-5.c +index 74d8df99ddc..f189827d6cf 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-5.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-5.c +@@ -11,7 +11,7 @@ + ** amoadd\.w\tzero,a1,0\(a0\) + ** ret + */ +-void foo (int* bar, int* baz) ++void foo (int* bar, int baz) + { + __atomic_add_fetch(bar, baz, __ATOMIC_SEQ_CST); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-1.c +index 5c0a8b8f6e9..a44d6980ece 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-1.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-1.c +@@ -5,7 +5,7 @@ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ + +-void foo (short* bar, short* baz) ++void foo (short* bar, short baz) + { + __atomic_add_fetch(bar, baz, __ATOMIC_RELAXED); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-2.c +index 551078186ec..8d28569c79c 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-2.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-2.c +@@ -5,7 +5,7 @@ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ + +-void foo (short* bar, short* baz) ++void foo (short* bar, short baz) + { + __atomic_add_fetch(bar, baz, __ATOMIC_ACQUIRE); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-3.c +index 5f0f7870721..fb803ab9cbf 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-3.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-3.c +@@ -5,7 +5,7 @@ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ + +-void foo (short* bar, short* baz) ++void foo (short* bar, short baz) + { + __atomic_add_fetch(bar, baz, __ATOMIC_RELEASE); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-4.c +index 24f4f02dcea..a88e409063a 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-4.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-4.c +@@ -5,7 +5,7 @@ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ + +-void foo (short* bar, short* baz) ++void foo (short* bar, short baz) + { + __atomic_add_fetch(bar, baz, __ATOMIC_ACQ_REL); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-5.c +index 405e498fb40..d851e5e5944 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-5.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-5.c +@@ -5,7 +5,7 @@ + /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ + +-void foo (short* bar, short* baz) ++void foo (short* bar, short baz) + { + __atomic_add_fetch(bar, baz, __ATOMIC_SEQ_CST); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-zaamo-preferred-over-zalrsc.c b/gcc/testsuite/gcc.target/riscv/amo/amo-zaamo-preferred-over-zalrsc.c +index 1c124c2b8b1..dae30c32e01 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-zaamo-preferred-over-zalrsc.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-zaamo-preferred-over-zalrsc.c +@@ -11,7 +11,7 @@ + ** amoadd\.w\tzero,a1,0\(a0\) + ** ret + */ +-void foo (int* bar, int* baz) ++void foo (int* bar, int baz) + { + __atomic_add_fetch(bar, baz, __ATOMIC_RELAXED); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-1.c +index 3fa74332433..49c1a181d69 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-1.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-1.c +@@ -13,7 +13,7 @@ + ** bnez\t[atx][0-9]+, 1b + ** ret + */ +-void foo (int* bar, int* baz) ++void foo (int* bar, int baz) + { + __atomic_add_fetch(bar, baz, __ATOMIC_RELAXED); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-2.c +index af0a2d50d38..af93c9a182b 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-2.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-2.c +@@ -13,7 +13,7 @@ + ** bnez\t[atx][0-9]+, 1b + ** ret + */ +-void foo (int* bar, int* baz) ++void foo (int* bar, int baz) + { + __atomic_add_fetch(bar, baz, __ATOMIC_ACQUIRE); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-3.c +index 521869b2165..ce68af841ea 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-3.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-3.c +@@ -13,7 +13,7 @@ + ** bnez\t[atx][0-9]+, 1b + ** ret + */ +-void foo (int* bar, int* baz) ++void foo (int* bar, int baz) + { + __atomic_add_fetch(bar, baz, __ATOMIC_RELEASE); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-4.c +index 8b6e7579f6f..be9f847782e 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-4.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-4.c +@@ -13,7 +13,7 @@ + ** bnez\t[atx][0-9]+, 1b + ** ret + */ +-void foo (int* bar, int* baz) ++void foo (int* bar, int baz) + { + __atomic_add_fetch(bar, baz, __ATOMIC_ACQ_REL); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-5.c +index 0bdc47d5c46..b31170c15db 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-5.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-5.c +@@ -13,7 +13,7 @@ + ** bnez\t[atx][0-9]+, 1b + ** ret + */ +-void foo (int* bar, int* baz) ++void foo (int* bar, int baz) + { + __atomic_add_fetch(bar, baz, __ATOMIC_SEQ_CST); + } +-- +2.47.3 + diff --git a/1044-RISC-V-Allow-any-temp-register-to-be-used-in-amo-tes.patch b/1044-RISC-V-Allow-any-temp-register-to-be-used-in-amo-tes.patch new file mode 100644 index 0000000..8b34a55 --- /dev/null +++ b/1044-RISC-V-Allow-any-temp-register-to-be-used-in-amo-tes.patch @@ -0,0 +1,232 @@ +From 7080c5ee549d9e9103621f9a90c65627f4c24c72 Mon Sep 17 00:00:00 2001 +From: Patrick O'Neill +Date: Mon, 10 Jun 2024 17:00:38 -0700 +Subject: [PATCH 1044/1087] RISC-V: Allow any temp register to be used in amo + tests + +commit 439c0cc9f7f6e83b898cabbd2e34f98484b432d3 upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +We artifically restrict the temp registers to be a[0-9]+ when other +registers like t[0-9]+ are valid too. Update to make the regex +accept any register for the temp value. + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/amo/amo-table-a-6-load-1.c: Update temp register regex. + * gcc.target/riscv/amo/amo-table-a-6-load-2.c: Ditto. + * gcc.target/riscv/amo/amo-table-a-6-load-3.c: Ditto. + * gcc.target/riscv/amo/amo-table-a-6-store-1.c: Ditto. + * gcc.target/riscv/amo/amo-table-a-6-store-2.c: Ditto. + * gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c: Ditto. + * gcc.target/riscv/amo/amo-table-ztso-load-1.c: Ditto. + * gcc.target/riscv/amo/amo-table-ztso-load-2.c: Ditto. + * gcc.target/riscv/amo/amo-table-ztso-load-3.c: Ditto. + * gcc.target/riscv/amo/amo-table-ztso-store-1.c: Ditto. + * gcc.target/riscv/amo/amo-table-ztso-store-2.c: Ditto. + * gcc.target/riscv/amo/amo-table-ztso-store-3.c: Ditto. + +Signed-off-by: Patrick O'Neill +--- + gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-1.c | 4 ++-- + gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-2.c | 4 ++-- + gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-3.c | 4 ++-- + gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-1.c | 4 ++-- + gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-2.c | 4 ++-- + .../gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c | 4 ++-- + gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-1.c | 4 ++-- + gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-2.c | 4 ++-- + gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-3.c | 4 ++-- + gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-1.c | 4 ++-- + gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-2.c | 4 ++-- + gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-3.c | 4 ++-- + 12 files changed, 24 insertions(+), 24 deletions(-) + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-1.c +index 3c79035e46d..53dd5234452 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-1.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-1.c +@@ -6,8 +6,8 @@ + + /* + ** foo: +-** lw\ta[0-9]+,0\(a0\) +-** sw\ta[0-9]+,0\(a1\) ++** lw\t[atx][0-9]+,0\(a0\) ++** sw\t[atx][0-9]+,0\(a1\) + ** ret + */ + void foo (int* bar, int* baz) +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-2.c +index 7d74841846f..dda0f541515 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-2.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-2.c +@@ -6,9 +6,9 @@ + + /* + ** foo: +-** lw\ta[0-9]+,0\(a0\) ++** lw\t[atx][0-9]+,0\(a0\) + ** fence\tr,rw +-** sw\ta[0-9]+,0\(a1\) ++** sw\t[atx][0-9]+,0\(a1\) + ** ret + */ + void foo (int* bar, int* baz) +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-3.c +index ab95fa660d2..3279557fa4a 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-3.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-3.c +@@ -7,9 +7,9 @@ + /* + ** foo: + ** fence\trw,rw +-** lw\ta[0-9]+,0\(a0\) ++** lw\t[atx][0-9]+,0\(a0\) + ** fence\tr,rw +-** sw\ta[0-9]+,0\(a1\) ++** sw\t[atx][0-9]+,0\(a1\) + ** ret + */ + void foo (int* bar, int* baz) +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-1.c +index d852fddf03d..6b05429520b 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-1.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-1.c +@@ -6,8 +6,8 @@ + + /* + ** foo: +-** lw\ta[0-9]+,0\(a1\) +-** sw\ta[0-9]+,0\(a0\) ++** lw\t[atx][0-9]+,0\(a1\) ++** sw\t[atx][0-9]+,0\(a0\) + ** ret + */ + void foo (int* bar, int* baz) +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-2.c +index ccb5e2af7cc..1ad7dede931 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-2.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-2.c +@@ -6,9 +6,9 @@ + + /* + ** foo: +-** lw\ta[0-9]+,0\(a1\) ++** lw\t[atx][0-9]+,0\(a1\) + ** fence\trw,w +-** sw\ta[0-9]+,0\(a0\) ++** sw\t[atx][0-9]+,0\(a0\) + ** ret + */ + void foo (int* bar, int* baz) +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c +index 761889f18cf..b16b2058413 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c +@@ -6,9 +6,9 @@ + + /* + ** foo: +-** lw\ta[0-9]+,0\(a1\) ++** lw\t[atx][0-9]+,0\(a1\) + ** fence\trw,w +-** sw\ta[0-9]+,0\(a0\) ++** sw\t[atx][0-9]+,0\(a0\) + ** fence\trw,rw + ** ret + */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-1.c +index 631977985bd..ebb0a2e1d38 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-1.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-1.c +@@ -7,8 +7,8 @@ + + /* + ** foo: +-** lw\ta[0-9]+,0\(a0\) +-** sw\ta[0-9]+,0\(a1\) ++** lw\t[atx][0-9]+,0\(a0\) ++** sw\t[atx][0-9]+,0\(a1\) + ** ret + */ + void foo (int* bar, int* baz) +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-2.c +index 2c24f10fb44..c88c4be5aea 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-2.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-2.c +@@ -7,8 +7,8 @@ + + /* + ** foo: +-** lw\ta[0-9]+,0\(a0\) +-** sw\ta[0-9]+,0\(a1\) ++** lw\t[atx][0-9]+,0\(a0\) ++** sw\t[atx][0-9]+,0\(a1\) + ** ret + */ + void foo (int* bar, int* baz) +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-3.c +index 7d2166d29c0..8713729c378 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-3.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-3.c +@@ -8,8 +8,8 @@ + /* + ** foo: + ** fence\trw,rw +-** lw\ta[0-9]+,0\(a0\) +-** sw\ta[0-9]+,0\(a1\) ++** lw\t[atx][0-9]+,0\(a0\) ++** sw\t[atx][0-9]+,0\(a1\) + ** ret + */ + void foo (int* bar, int* baz) +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-1.c +index 29a770285ef..ca8d5ed7515 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-1.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-1.c +@@ -7,8 +7,8 @@ + + /* + ** foo: +-** lw\ta[0-9]+,0\(a1\) +-** sw\ta[0-9]+,0\(a0\) ++** lw\t[atx][0-9]+,0\(a1\) ++** sw\t[atx][0-9]+,0\(a0\) + ** ret + */ + void foo (int* bar, int* baz) +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-2.c +index fb82360ad33..23957198cfb 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-2.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-2.c +@@ -7,8 +7,8 @@ + + /* + ** foo: +-** lw\ta[0-9]+,0\(a1\) +-** sw\ta[0-9]+,0\(a0\) ++** lw\t[atx][0-9]+,0\(a1\) ++** sw\t[atx][0-9]+,0\(a0\) + ** ret + */ + void foo (int* bar, int* baz) +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-3.c +index 88d8432d8c9..11c12f0ca1a 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-3.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-3.c +@@ -7,8 +7,8 @@ + + /* + ** foo: +-** lw\ta[0-9]+,0\(a1\) +-** sw\ta[0-9]+,0\(a0\) ++** lw\t[atx][0-9]+,0\(a1\) ++** sw\t[atx][0-9]+,0\(a0\) + ** fence\trw,rw + ** ret + */ +-- +2.47.3 + diff --git a/1045-RISC-V-Add-support-for-subword-atomic-loads-stores.patch b/1045-RISC-V-Add-support-for-subword-atomic-loads-stores.patch new file mode 100644 index 0000000..34c0dd7 --- /dev/null +++ b/1045-RISC-V-Add-support-for-subword-atomic-loads-stores.patch @@ -0,0 +1,999 @@ +From 5f7d06902314c48e44c6db566734bc3791761e84 Mon Sep 17 00:00:00 2001 +From: Patrick O'Neill +Date: Wed, 12 Jun 2024 17:10:13 -0700 +Subject: [PATCH 1045/1087] RISC-V: Add support for subword atomic loads/stores + +commit 5476853b225e1327ec857ee34fdec64429af84f6 upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +Andrea Parri recently pointed out that we were emitting overly conservative +fences for seq_cst atomic loads/stores. This adds support for the optimized +fences specified in the PSABI: +https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/2092568f7896ceaa1ec0f02569b19eaa42cd51c9/riscv-atomic.adoc + +gcc/ChangeLog: + + * config/riscv/sync-rvwmo.md: Add support for subword fenced + loads/stores. + * config/riscv/sync-ztso.md: Ditto. + * config/riscv/sync.md: Ditto. + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/amo/amo-table-a-6-load-1.c: Increase test coverage to + include longs, shorts, chars, and bools. + * gcc.target/riscv/amo/amo-table-a-6-load-2.c: Ditto. + * gcc.target/riscv/amo/amo-table-a-6-load-3.c: Ditto. + * gcc.target/riscv/amo/amo-table-a-6-store-1.c: Ditto. + * gcc.target/riscv/amo/amo-table-a-6-store-2.c: Ditto. + * gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c: Ditto. + * gcc.target/riscv/amo/amo-table-ztso-load-1.c: Ditto. + * gcc.target/riscv/amo/amo-table-ztso-load-2.c: Ditto. + * gcc.target/riscv/amo/amo-table-ztso-load-3.c: Ditto. + * gcc.target/riscv/amo/amo-table-ztso-store-1.c: Ditto. + * gcc.target/riscv/amo/amo-table-ztso-store-2.c: Ditto. + * gcc.target/riscv/amo/amo-table-ztso-store-3.c: Ditto. + +Signed-off-by: Patrick O'Neill +Tested-by: Andrea Parri +--- + gcc/config/riscv/sync-rvwmo.md | 24 ++++---- + gcc/config/riscv/sync-ztso.md | 20 +++---- + gcc/config/riscv/sync.md | 8 +-- + .../riscv/amo/amo-table-a-6-load-1.c | 48 +++++++++++++++- + .../riscv/amo/amo-table-a-6-load-2.c | 52 ++++++++++++++++- + .../riscv/amo/amo-table-a-6-load-3.c | 56 ++++++++++++++++++- + .../riscv/amo/amo-table-a-6-store-1.c | 48 +++++++++++++++- + .../riscv/amo/amo-table-a-6-store-2.c | 52 ++++++++++++++++- + .../riscv/amo/amo-table-a-6-store-compat-3.c | 56 ++++++++++++++++++- + .../riscv/amo/amo-table-ztso-load-1.c | 48 +++++++++++++++- + .../riscv/amo/amo-table-ztso-load-2.c | 48 +++++++++++++++- + .../riscv/amo/amo-table-ztso-load-3.c | 52 ++++++++++++++++- + .../riscv/amo/amo-table-ztso-store-1.c | 48 +++++++++++++++- + .../riscv/amo/amo-table-ztso-store-2.c | 48 +++++++++++++++- + .../riscv/amo/amo-table-ztso-store-3.c | 52 ++++++++++++++++- + 15 files changed, 610 insertions(+), 50 deletions(-) + +diff --git a/gcc/config/riscv/sync-rvwmo.md b/gcc/config/riscv/sync-rvwmo.md +index d4fd26069f7..22dbc38306d 100644 +--- a/gcc/config/riscv/sync-rvwmo.md ++++ b/gcc/config/riscv/sync-rvwmo.md +@@ -47,9 +47,9 @@ + ;; Atomic memory operations. + + (define_insn "atomic_load_rvwmo" +- [(set (match_operand:GPR 0 "register_operand" "=r") +- (unspec_volatile:GPR +- [(match_operand:GPR 1 "memory_operand" "A") ++ [(set (match_operand:ANYI 0 "register_operand" "=r") ++ (unspec_volatile:ANYI ++ [(match_operand:ANYI 1 "memory_operand" "A") + (match_operand:SI 2 "const_int_operand")] ;; model + UNSPEC_ATOMIC_LOAD))] + "!TARGET_ZTSO" +@@ -59,13 +59,13 @@ + + if (model == MEMMODEL_SEQ_CST) + return "fence\trw,rw\;" +- "l\t%0,%1\;" ++ "\t%0,%1\;" + "fence\tr,rw"; + if (model == MEMMODEL_ACQUIRE) +- return "l\t%0,%1\;" ++ return "\t%0,%1\;" + "fence\tr,rw"; + else +- return "l\t%0,%1"; ++ return "\t%0,%1"; + } + [(set_attr "type" "multi") + (set (attr "length") (const_int 12))]) +@@ -73,9 +73,9 @@ + ;; Implement atomic stores with conservative fences. + ;; This allows us to be compatible with the ISA manual Table A.6 and Table A.7. + (define_insn "atomic_store_rvwmo" +- [(set (match_operand:GPR 0 "memory_operand" "=A") +- (unspec_volatile:GPR +- [(match_operand:GPR 1 "reg_or_0_operand" "rJ") ++ [(set (match_operand:ANYI 0 "memory_operand" "=A") ++ (unspec_volatile:ANYI ++ [(match_operand:ANYI 1 "reg_or_0_operand" "rJ") + (match_operand:SI 2 "const_int_operand")] ;; model + UNSPEC_ATOMIC_STORE))] + "!TARGET_ZTSO" +@@ -85,13 +85,13 @@ + + if (model == MEMMODEL_SEQ_CST) + return "fence\trw,w\;" +- "s\t%z1,%0\;" ++ "\t%z1,%0\;" + "fence\trw,rw"; + if (model == MEMMODEL_RELEASE) + return "fence\trw,w\;" +- "s\t%z1,%0"; ++ "\t%z1,%0"; + else +- return "s\t%z1,%0"; ++ return "\t%z1,%0"; + } + [(set_attr "type" "multi") + (set (attr "length") (const_int 12))]) +diff --git a/gcc/config/riscv/sync-ztso.md b/gcc/config/riscv/sync-ztso.md +index 0a866d2906b..f99a21b45ca 100644 +--- a/gcc/config/riscv/sync-ztso.md ++++ b/gcc/config/riscv/sync-ztso.md +@@ -41,9 +41,9 @@ + ;; Atomic memory operations. + + (define_insn "atomic_load_ztso" +- [(set (match_operand:GPR 0 "register_operand" "=r") +- (unspec_volatile:GPR +- [(match_operand:GPR 1 "memory_operand" "A") ++ [(set (match_operand:ANYI 0 "register_operand" "=r") ++ (unspec_volatile:ANYI ++ [(match_operand:ANYI 1 "memory_operand" "A") + (match_operand:SI 2 "const_int_operand")] ;; model + UNSPEC_ATOMIC_LOAD))] + "TARGET_ZTSO" +@@ -53,17 +53,17 @@ + + if (model == MEMMODEL_SEQ_CST) + return "fence\trw,rw\;" +- "l\t%0,%1"; ++ "\t%0,%1"; + else +- return "l\t%0,%1"; ++ return "\t%0,%1"; + } + [(set_attr "type" "multi") + (set (attr "length") (const_int 12))]) + + (define_insn "atomic_store_ztso" +- [(set (match_operand:GPR 0 "memory_operand" "=A") +- (unspec_volatile:GPR +- [(match_operand:GPR 1 "reg_or_0_operand" "rJ") ++ [(set (match_operand:ANYI 0 "memory_operand" "=A") ++ (unspec_volatile:ANYI ++ [(match_operand:ANYI 1 "reg_or_0_operand" "rJ") + (match_operand:SI 2 "const_int_operand")] ;; model + UNSPEC_ATOMIC_STORE))] + "TARGET_ZTSO" +@@ -72,10 +72,10 @@ + model = memmodel_base (model); + + if (model == MEMMODEL_SEQ_CST) +- return "s\t%z1,%0\;" ++ return "\t%z1,%0\;" + "fence\trw,rw"; + else +- return "s\t%z1,%0"; ++ return "\t%z1,%0"; + } + [(set_attr "type" "multi") + (set (attr "length") (const_int 8))]) +diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md +index ee45040cfb6..0c97ae85975 100644 +--- a/gcc/config/riscv/sync.md ++++ b/gcc/config/riscv/sync.md +@@ -57,8 +57,8 @@ + ;; Atomic memory operations. + + (define_expand "atomic_load" +- [(match_operand:GPR 0 "register_operand") +- (match_operand:GPR 1 "memory_operand") ++ [(match_operand:ANYI 0 "register_operand") ++ (match_operand:ANYI 1 "memory_operand") + (match_operand:SI 2 "const_int_operand")] ;; model + "" + { +@@ -72,8 +72,8 @@ + }) + + (define_expand "atomic_store" +- [(match_operand:GPR 0 "memory_operand") +- (match_operand:GPR 1 "reg_or_0_operand") ++ [(match_operand:ANYI 0 "memory_operand") ++ (match_operand:ANYI 1 "reg_or_0_operand") + (match_operand:SI 2 "const_int_operand")] ;; model + "" + { +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-1.c +index 53dd5234452..948fece6125 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-1.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-1.c +@@ -5,12 +5,56 @@ + /* { dg-final { check-function-bodies "**" "" } } */ + + /* +-** foo: ++** atomic_load_long_relaxed: ++** l[wd]\t[atx][0-9]+,0\(a0\) ++** s[wd]\t[atx][0-9]+,0\(a1\) ++** ret ++*/ ++void atomic_load_long_relaxed (long* bar, long* baz) ++{ ++ __atomic_load(bar, baz, __ATOMIC_RELAXED); ++} ++ ++/* ++** atomic_load_int_relaxed: + ** lw\t[atx][0-9]+,0\(a0\) + ** sw\t[atx][0-9]+,0\(a1\) + ** ret + */ +-void foo (int* bar, int* baz) ++void atomic_load_int_relaxed (int* bar, int* baz) ++{ ++ __atomic_load(bar, baz, __ATOMIC_RELAXED); ++} ++ ++/* ++** atomic_load_short_relaxed: ++** lh\t[atx][0-9]+,0\(a0\) ++** sh\t[atx][0-9]+,0\(a1\) ++** ret ++*/ ++void atomic_load_short_relaxed (short* bar, short* baz) ++{ ++ __atomic_load(bar, baz, __ATOMIC_RELAXED); ++} ++ ++/* ++** atomic_load_char_relaxed: ++** lb\t[atx][0-9]+,0\(a0\) ++** sb\t[atx][0-9]+,0\(a1\) ++** ret ++*/ ++void atomic_load_char_relaxed (char* bar, char* baz) ++{ ++ __atomic_load(bar, baz, __ATOMIC_RELAXED); ++} ++ ++/* ++** atomic_load_bool_relaxed: ++** lb\t[atx][0-9]+,0\(a0\) ++** sb\t[atx][0-9]+,0\(a1\) ++** ret ++*/ ++void atomic_load_bool_relaxed (_Bool* bar, _Bool* baz) + { + __atomic_load(bar, baz, __ATOMIC_RELAXED); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-2.c +index dda0f541515..e855db9b761 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-2.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-2.c +@@ -5,13 +5,61 @@ + /* { dg-final { check-function-bodies "**" "" } } */ + + /* +-** foo: ++** atomic_load_long_acquire: ++** l[wd]\t[atx][0-9]+,0\(a0\) ++** fence\tr,rw ++** s[wd]\t[atx][0-9]+,0\(a1\) ++** ret ++*/ ++void atomic_load_long_acquire (long* bar, long* baz) ++{ ++ __atomic_load(bar, baz, __ATOMIC_ACQUIRE); ++} ++ ++/* ++** atomic_load_int_acquire: + ** lw\t[atx][0-9]+,0\(a0\) + ** fence\tr,rw + ** sw\t[atx][0-9]+,0\(a1\) + ** ret + */ +-void foo (int* bar, int* baz) ++void atomic_load_int_acquire (int* bar, int* baz) ++{ ++ __atomic_load(bar, baz, __ATOMIC_ACQUIRE); ++} ++ ++/* ++** atomic_load_short_acquire: ++** lh\t[atx][0-9]+,0\(a0\) ++** fence\tr,rw ++** sh\t[atx][0-9]+,0\(a1\) ++** ret ++*/ ++void atomic_load_short_acquire (short* bar, short* baz) ++{ ++ __atomic_load(bar, baz, __ATOMIC_ACQUIRE); ++} ++ ++/* ++** atomic_load_char_acquire: ++** lb\t[atx][0-9]+,0\(a0\) ++** fence\tr,rw ++** sb\t[atx][0-9]+,0\(a1\) ++** ret ++*/ ++void atomic_load_char_acquire (char* bar, char* baz) ++{ ++ __atomic_load(bar, baz, __ATOMIC_ACQUIRE); ++} ++ ++/* ++** atomic_load_bool_acquire: ++** lb\t[atx][0-9]+,0\(a0\) ++** fence\tr,rw ++** sb\t[atx][0-9]+,0\(a1\) ++** ret ++*/ ++void atomic_load_bool_acquire (_Bool* bar, _Bool* baz) + { + __atomic_load(bar, baz, __ATOMIC_ACQUIRE); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-3.c +index 3279557fa4a..6e79ca72abc 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-3.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-3.c +@@ -5,14 +5,66 @@ + /* { dg-final { check-function-bodies "**" "" } } */ + + /* +-** foo: ++** atomic_load_long_seq_cst: ++** fence\trw,rw ++** l[wd]\t[atx][0-9]+,0\(a0\) ++** fence\tr,rw ++** s[wd]\t[atx][0-9]+,0\(a1\) ++** ret ++*/ ++void atomic_load_long_seq_cst (long* bar, long* baz) ++{ ++ __atomic_load(bar, baz, __ATOMIC_SEQ_CST); ++} ++ ++/* ++** atomic_load_int_seq_cst: + ** fence\trw,rw + ** lw\t[atx][0-9]+,0\(a0\) + ** fence\tr,rw + ** sw\t[atx][0-9]+,0\(a1\) + ** ret + */ +-void foo (int* bar, int* baz) ++void atomic_load_int_seq_cst (int* bar, int* baz) ++{ ++ __atomic_load(bar, baz, __ATOMIC_SEQ_CST); ++} ++ ++/* ++** atomic_load_short_seq_cst: ++** fence\trw,rw ++** lh\t[atx][0-9]+,0\(a0\) ++** fence\tr,rw ++** sh\t[atx][0-9]+,0\(a1\) ++** ret ++*/ ++void atomic_load_short_seq_cst (short* bar, short* baz) ++{ ++ __atomic_load(bar, baz, __ATOMIC_SEQ_CST); ++} ++ ++/* ++** atomic_load_char_seq_cst: ++** fence\trw,rw ++** lb\t[atx][0-9]+,0\(a0\) ++** fence\tr,rw ++** sb\t[atx][0-9]+,0\(a1\) ++** ret ++*/ ++void atomic_load_char_seq_cst (char* bar, char* baz) ++{ ++ __atomic_load(bar, baz, __ATOMIC_SEQ_CST); ++} ++ ++/* ++** atomic_load_bool_seq_cst: ++** fence\trw,rw ++** lb\t[atx][0-9]+,0\(a0\) ++** fence\tr,rw ++** sb\t[atx][0-9]+,0\(a1\) ++** ret ++*/ ++void atomic_load_bool_seq_cst (_Bool* bar, _Bool* baz) + { + __atomic_load(bar, baz, __ATOMIC_SEQ_CST); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-1.c +index 6b05429520b..ee7e7dbc8ee 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-1.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-1.c +@@ -5,12 +5,56 @@ + /* { dg-final { check-function-bodies "**" "" } } */ + + /* +-** foo: ++** atomic_store_long_relaxed: ++** l[wd]\t[atx][0-9]+,0\(a1\) ++** s[wd]\t[atx][0-9]+,0\(a0\) ++** ret ++*/ ++void atomic_store_long_relaxed (long* bar, long* baz) ++{ ++ __atomic_store(bar, baz, __ATOMIC_RELAXED); ++} ++ ++/* ++** atomic_store_int_relaxed: + ** lw\t[atx][0-9]+,0\(a1\) + ** sw\t[atx][0-9]+,0\(a0\) + ** ret + */ +-void foo (int* bar, int* baz) ++void atomic_store_int_relaxed (int* bar, int* baz) ++{ ++ __atomic_store(bar, baz, __ATOMIC_RELAXED); ++} ++ ++/* ++** atomic_store_short_relaxed: ++** lhu\t[atx][0-9]+,0\(a1\) ++** sh\t[atx][0-9]+,0\(a0\) ++** ret ++*/ ++void atomic_store_short_relaxed (short* bar, short* baz) ++{ ++ __atomic_store(bar, baz, __ATOMIC_RELAXED); ++} ++ ++/* ++** atomic_store_char_relaxed: ++** lbu\t[atx][0-9]+,0\(a1\) ++** sb\t[atx][0-9]+,0\(a0\) ++** ret ++*/ ++void atomic_store_char_relaxed (char* bar, char* baz) ++{ ++ __atomic_store(bar, baz, __ATOMIC_RELAXED); ++} ++ ++/* ++** atomic_store_bool_relaxed: ++** lbu\t[atx][0-9]+,0\(a1\) ++** sb\t[atx][0-9]+,0\(a0\) ++** ret ++*/ ++void atomic_store_bool_relaxed (_Bool* bar, _Bool* baz) + { + __atomic_store(bar, baz, __ATOMIC_RELAXED); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-2.c +index 1ad7dede931..5110512e1ad 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-2.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-2.c +@@ -5,13 +5,61 @@ + /* { dg-final { check-function-bodies "**" "" } } */ + + /* +-** foo: ++** atomic_store_long_release: ++** l[wd]\t[atx][0-9]+,0\(a1\) ++** fence\trw,w ++** s[wd]\t[atx][0-9]+,0\(a0\) ++** ret ++*/ ++void atomic_store_long_release (long* bar, long* baz) ++{ ++ __atomic_store(bar, baz, __ATOMIC_RELEASE); ++} ++ ++/* ++** atomic_store_int_release: + ** lw\t[atx][0-9]+,0\(a1\) + ** fence\trw,w + ** sw\t[atx][0-9]+,0\(a0\) + ** ret + */ +-void foo (int* bar, int* baz) ++void atomic_store_int_release (int* bar, int* baz) ++{ ++ __atomic_store(bar, baz, __ATOMIC_RELEASE); ++} ++ ++/* ++** atomic_store_short_release: ++** lhu\t[atx][0-9]+,0\(a1\) ++** fence\trw,w ++** sh\t[atx][0-9]+,0\(a0\) ++** ret ++*/ ++void atomic_store_short_release (short* bar, short* baz) ++{ ++ __atomic_store(bar, baz, __ATOMIC_RELEASE); ++} ++ ++/* ++** atomic_store_char_release: ++** lbu\t[atx][0-9]+,0\(a1\) ++** fence\trw,w ++** sb\t[atx][0-9]+,0\(a0\) ++** ret ++*/ ++void atomic_store_char_release (char* bar, char* baz) ++{ ++ __atomic_store(bar, baz, __ATOMIC_RELEASE); ++} ++ ++/* ++** atomic_store_bool_release: ++** lbu\t[atx][0-9]+,0\(a1\) ++** fence\trw,w ++** sb\t[atx][0-9]+,0\(a0\) ++** ret ++*/ ++void atomic_store_bool_release (_Bool* bar, _Bool* baz) + { + __atomic_store(bar, baz, __ATOMIC_RELEASE); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c +index b16b2058413..016e5dec87d 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c +@@ -5,14 +5,66 @@ + /* { dg-final { check-function-bodies "**" "" } } */ + + /* +-** foo: ++** atomic_store_long_seq_cst: ++** l[wd]\t[atx][0-9]+,0\(a1\) ++** fence\trw,w ++** s[wd]\t[atx][0-9]+,0\(a0\) ++** fence\trw,rw ++** ret ++*/ ++void atomic_store_long_seq_cst (long* bar, long* baz) ++{ ++ __atomic_store(bar, baz, __ATOMIC_SEQ_CST); ++} ++ ++/* ++** atomic_store_int_seq_cst: + ** lw\t[atx][0-9]+,0\(a1\) + ** fence\trw,w + ** sw\t[atx][0-9]+,0\(a0\) + ** fence\trw,rw + ** ret + */ +-void foo (int* bar, int* baz) ++void atomic_store_int_seq_cst (int* bar, int* baz) ++{ ++ __atomic_store(bar, baz, __ATOMIC_SEQ_CST); ++} ++ ++/* ++** atomic_store_short_seq_cst: ++** lhu\t[atx][0-9]+,0\(a1\) ++** fence\trw,w ++** sh\t[atx][0-9]+,0\(a0\) ++** fence\trw,rw ++** ret ++*/ ++void atomic_store_short_seq_cst (short* bar, short* baz) ++{ ++ __atomic_store(bar, baz, __ATOMIC_SEQ_CST); ++} ++ ++/* ++** atomic_store_char_seq_cst: ++** lbu\t[atx][0-9]+,0\(a1\) ++** fence\trw,w ++** sb\t[atx][0-9]+,0\(a0\) ++** fence\trw,rw ++** ret ++*/ ++void atomic_store_char_seq_cst (char* bar, char* baz) ++{ ++ __atomic_store(bar, baz, __ATOMIC_SEQ_CST); ++} ++ ++/* ++** atomic_store_bool_seq_cst: ++** lbu\t[atx][0-9]+,0\(a1\) ++** fence\trw,w ++** sb\t[atx][0-9]+,0\(a0\) ++** fence\trw,rw ++** ret ++*/ ++void atomic_store_bool_seq_cst (_Bool* bar, _Bool* baz) + { + __atomic_store(bar, baz, __ATOMIC_SEQ_CST); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-1.c +index ebb0a2e1d38..ef5dee6ee60 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-1.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-1.c +@@ -6,12 +6,56 @@ + /* { dg-final { check-function-bodies "**" "" } } */ + + /* +-** foo: ++** atomic_load_long_relaxed: ++** l[wd]\t[atx][0-9]+,0\(a0\) ++** s[wd]\t[atx][0-9]+,0\(a1\) ++** ret ++*/ ++void atomic_load_long_relaxed (long* bar, long* baz) ++{ ++ __atomic_load(bar, baz, __ATOMIC_RELAXED); ++} ++ ++/* ++** atomic_load_int_relaxed: + ** lw\t[atx][0-9]+,0\(a0\) + ** sw\t[atx][0-9]+,0\(a1\) + ** ret + */ +-void foo (int* bar, int* baz) ++void atomic_load_int_relaxed (int* bar, int* baz) ++{ ++ __atomic_load(bar, baz, __ATOMIC_RELAXED); ++} ++ ++/* ++** atomic_load_short_relaxed: ++** lh\t[atx][0-9]+,0\(a0\) ++** sh\t[atx][0-9]+,0\(a1\) ++** ret ++*/ ++void atomic_load_short_relaxed (short* bar, short* baz) ++{ ++ __atomic_load(bar, baz, __ATOMIC_RELAXED); ++} ++ ++/* ++** atomic_load_char_relaxed: ++** lb\t[atx][0-9]+,0\(a0\) ++** sb\t[atx][0-9]+,0\(a1\) ++** ret ++*/ ++void atomic_load_char_relaxed (char* bar, char* baz) ++{ ++ __atomic_load(bar, baz, __ATOMIC_RELAXED); ++} ++ ++/* ++** atomic_load_bool_relaxed: ++** lb\t[atx][0-9]+,0\(a0\) ++** sb\t[atx][0-9]+,0\(a1\) ++** ret ++*/ ++void atomic_load_bool_relaxed (_Bool* bar, _Bool* baz) + { + __atomic_load(bar, baz, __ATOMIC_RELAXED); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-2.c +index c88c4be5aea..4e94191812b 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-2.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-2.c +@@ -6,12 +6,56 @@ + /* { dg-final { check-function-bodies "**" "" } } */ + + /* +-** foo: ++** atomic_load_long_acquire: ++** l[wd]\t[atx][0-9]+,0\(a0\) ++** s[wd]\t[atx][0-9]+,0\(a1\) ++** ret ++*/ ++void atomic_load_long_acquire (long* bar, long* baz) ++{ ++ __atomic_load(bar, baz, __ATOMIC_ACQUIRE); ++} ++ ++/* ++** atomic_load_int_acquire: + ** lw\t[atx][0-9]+,0\(a0\) + ** sw\t[atx][0-9]+,0\(a1\) + ** ret + */ +-void foo (int* bar, int* baz) ++void atomic_load_int_acquire (int* bar, int* baz) ++{ ++ __atomic_load(bar, baz, __ATOMIC_ACQUIRE); ++} ++ ++/* ++** atomic_load_short_acquire: ++** lh\t[atx][0-9]+,0\(a0\) ++** sh\t[atx][0-9]+,0\(a1\) ++** ret ++*/ ++void atomic_load_short_acquire (short* bar, short* baz) ++{ ++ __atomic_load(bar, baz, __ATOMIC_ACQUIRE); ++} ++ ++/* ++** atomic_load_char_acquire: ++** lb\t[atx][0-9]+,0\(a0\) ++** sb\t[atx][0-9]+,0\(a1\) ++** ret ++*/ ++void atomic_load_char_acquire (char* bar, char* baz) ++{ ++ __atomic_load(bar, baz, __ATOMIC_ACQUIRE); ++} ++ ++/* ++** atomic_load_bool_acquire: ++** lb\t[atx][0-9]+,0\(a0\) ++** sb\t[atx][0-9]+,0\(a1\) ++** ret ++*/ ++void atomic_load_bool_acquire (_Bool* bar, _Bool* baz) + { + __atomic_load(bar, baz, __ATOMIC_ACQUIRE); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-3.c +index 8713729c378..93cd8bb909c 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-3.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-3.c +@@ -6,13 +6,61 @@ + /* { dg-final { check-function-bodies "**" "" } } */ + + /* +-** foo: ++** atomic_load_long_seq_cst: ++** fence\trw,rw ++** l[wd]\t[atx][0-9]+,0\(a0\) ++** s[wd]\t[atx][0-9]+,0\(a1\) ++** ret ++*/ ++void atomic_load_long_seq_cst (long* bar, long* baz) ++{ ++ __atomic_load(bar, baz, __ATOMIC_SEQ_CST); ++} ++ ++/* ++** atomic_load_int_seq_cst: + ** fence\trw,rw + ** lw\t[atx][0-9]+,0\(a0\) + ** sw\t[atx][0-9]+,0\(a1\) + ** ret + */ +-void foo (int* bar, int* baz) ++void atomic_load_int_seq_cst (int* bar, int* baz) ++{ ++ __atomic_load(bar, baz, __ATOMIC_SEQ_CST); ++} ++ ++/* ++** atomic_load_short_seq_cst: ++** fence\trw,rw ++** lh\t[atx][0-9]+,0\(a0\) ++** sh\t[atx][0-9]+,0\(a1\) ++** ret ++*/ ++void atomic_load_short_seq_cst (short* bar, short* baz) ++{ ++ __atomic_load(bar, baz, __ATOMIC_SEQ_CST); ++} ++ ++/* ++** atomic_load_char_seq_cst: ++** fence\trw,rw ++** lb\t[atx][0-9]+,0\(a0\) ++** sb\t[atx][0-9]+,0\(a1\) ++** ret ++*/ ++void atomic_load_char_seq_cst (char* bar, char* baz) ++{ ++ __atomic_load(bar, baz, __ATOMIC_SEQ_CST); ++} ++ ++/* ++** atomic_load_bool_seq_cst: ++** fence\trw,rw ++** lb\t[atx][0-9]+,0\(a0\) ++** sb\t[atx][0-9]+,0\(a1\) ++** ret ++*/ ++void atomic_load_bool_seq_cst (_Bool* bar, _Bool* baz) + { + __atomic_load(bar, baz, __ATOMIC_SEQ_CST); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-1.c +index ca8d5ed7515..2f46470ae15 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-1.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-1.c +@@ -6,12 +6,56 @@ + /* { dg-final { check-function-bodies "**" "" } } */ + + /* +-** foo: ++** atomic_store_long_relaxed: ++** l[wd]\t[atx][0-9]+,0\(a1\) ++** s[wd]\t[atx][0-9]+,0\(a0\) ++** ret ++*/ ++void atomic_store_long_relaxed (long* bar, long* baz) ++{ ++ __atomic_store(bar, baz, __ATOMIC_RELAXED); ++} ++ ++/* ++** atomic_store_int_relaxed: + ** lw\t[atx][0-9]+,0\(a1\) + ** sw\t[atx][0-9]+,0\(a0\) + ** ret + */ +-void foo (int* bar, int* baz) ++void atomic_store_int_relaxed (int* bar, int* baz) ++{ ++ __atomic_store(bar, baz, __ATOMIC_RELAXED); ++} ++ ++/* ++** atomic_store_short_relaxed: ++** lhu\t[atx][0-9]+,0\(a1\) ++** sh\t[atx][0-9]+,0\(a0\) ++** ret ++*/ ++void atomic_store_short_relaxed (short* bar, short* baz) ++{ ++ __atomic_store(bar, baz, __ATOMIC_RELAXED); ++} ++ ++/* ++** atomic_store_char_relaxed: ++** lbu\t[atx][0-9]+,0\(a1\) ++** sb\t[atx][0-9]+,0\(a0\) ++** ret ++*/ ++void atomic_store_char_relaxed (char* bar, char* baz) ++{ ++ __atomic_store(bar, baz, __ATOMIC_RELAXED); ++} ++ ++/* ++** atomic_store_bool_relaxed: ++** lbu\t[atx][0-9]+,0\(a1\) ++** sb\t[atx][0-9]+,0\(a0\) ++** ret ++*/ ++void atomic_store_bool_relaxed (_Bool* bar, _Bool* baz) + { + __atomic_store(bar, baz, __ATOMIC_RELAXED); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-2.c +index 23957198cfb..dd2db3a7878 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-2.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-2.c +@@ -6,12 +6,56 @@ + /* { dg-final { check-function-bodies "**" "" } } */ + + /* +-** foo: ++** atomic_store_long_release: ++** l[wd]\t[atx][0-9]+,0\(a1\) ++** s[wd]\t[atx][0-9]+,0\(a0\) ++** ret ++*/ ++void atomic_store_long_release (long* bar, long* baz) ++{ ++ __atomic_store(bar, baz, __ATOMIC_RELEASE); ++} ++ ++/* ++** atomic_store_int_release: + ** lw\t[atx][0-9]+,0\(a1\) + ** sw\t[atx][0-9]+,0\(a0\) + ** ret + */ +-void foo (int* bar, int* baz) ++void atomic_store_int_release (int* bar, int* baz) ++{ ++ __atomic_store(bar, baz, __ATOMIC_RELEASE); ++} ++ ++/* ++** atomic_store_short_release: ++** lhu\t[atx][0-9]+,0\(a1\) ++** sh\t[atx][0-9]+,0\(a0\) ++** ret ++*/ ++void atomic_store_short_release (short* bar, short* baz) ++{ ++ __atomic_store(bar, baz, __ATOMIC_RELEASE); ++} ++ ++/* ++** atomic_store_char_release: ++** lbu\t[atx][0-9]+,0\(a1\) ++** sb\t[atx][0-9]+,0\(a0\) ++** ret ++*/ ++void atomic_store_char_release (char* bar, char* baz) ++{ ++ __atomic_store(bar, baz, __ATOMIC_RELEASE); ++} ++ ++/* ++** atomic_store_bool_release: ++** lbu\t[atx][0-9]+,0\(a1\) ++** sb\t[atx][0-9]+,0\(a0\) ++** ret ++*/ ++void atomic_store_bool_release (_Bool* bar, _Bool* baz) + { + __atomic_store(bar, baz, __ATOMIC_RELEASE); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-3.c +index 11c12f0ca1a..e32cfb1a3cb 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-3.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-3.c +@@ -6,13 +6,61 @@ + /* { dg-final { check-function-bodies "**" "" } } */ + + /* +-** foo: ++** atomic_store_long_seq_cst: ++** l[wd]\t[atx][0-9]+,0\(a1\) ++** s[wd]\t[atx][0-9]+,0\(a0\) ++** fence\trw,rw ++** ret ++*/ ++void atomic_store_long_seq_cst (long* bar, long* baz) ++{ ++ __atomic_store(bar, baz, __ATOMIC_SEQ_CST); ++} ++ ++/* ++** atomic_store_int_seq_cst: + ** lw\t[atx][0-9]+,0\(a1\) + ** sw\t[atx][0-9]+,0\(a0\) + ** fence\trw,rw + ** ret + */ +-void foo (int* bar, int* baz) ++void atomic_store_int_seq_cst (int* bar, int* baz) ++{ ++ __atomic_store(bar, baz, __ATOMIC_SEQ_CST); ++} ++ ++/* ++** atomic_store_short_seq_cst: ++** lhu\t[atx][0-9]+,0\(a1\) ++** sh\t[atx][0-9]+,0\(a0\) ++** fence\trw,rw ++** ret ++*/ ++void atomic_store_short_seq_cst (short* bar, short* baz) ++{ ++ __atomic_store(bar, baz, __ATOMIC_SEQ_CST); ++} ++ ++/* ++** atomic_store_char_seq_cst: ++** lbu\t[atx][0-9]+,0\(a1\) ++** sb\t[atx][0-9]+,0\(a0\) ++** fence\trw,rw ++** ret ++*/ ++void atomic_store_char_seq_cst (char* bar, char* baz) ++{ ++ __atomic_store(bar, baz, __ATOMIC_SEQ_CST); ++} ++ ++/* ++** atomic_store_bool_seq_cst: ++** lbu\t[atx][0-9]+,0\(a1\) ++** sb\t[atx][0-9]+,0\(a0\) ++** fence\trw,rw ++** ret ++*/ ++void atomic_store_bool_seq_cst (_Bool* bar, _Bool* baz) + { + __atomic_store(bar, baz, __ATOMIC_SEQ_CST); + } +-- +2.47.3 + diff --git a/1046-RISC-V-Add-configure-check-for-Zaamo-Zalrsc-assemble.patch b/1046-RISC-V-Add-configure-check-for-Zaamo-Zalrsc-assemble.patch new file mode 100644 index 0000000..12e1d23 --- /dev/null +++ b/1046-RISC-V-Add-configure-check-for-Zaamo-Zalrsc-assemble.patch @@ -0,0 +1,147 @@ +From d64cc92f052ae69fce96f89ff4c0b2eb1bff0786 Mon Sep 17 00:00:00 2001 +From: Patrick O'Neill +Date: Mon, 17 Jun 2024 09:46:05 -0700 +Subject: [PATCH 1046/1087] RISC-V: Add configure check for Zaamo/Zalrsc + assembler support + +commit 4f18f75c5648d0b46a72f18e321bec279a6964be upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +Binutils 2.42 and before don't support Zaamo/Zalrsc. Add a configure +check to prevent emitting Zaamo/Zalrsc in the arch string when the +assember does not support it. + +gcc/ChangeLog: + + * common/config/riscv/riscv-common.cc + (riscv_subset_list::to_string): Skip zaamo/zalrsc when not + supported by the assembler. + * config.in: Regenerate. + * configure: Regenerate. + * configure.ac: Add zaamo/zalrsc assmeber check. + +Signed-off-by: Patrick O'Neill +Acked-by: Palmer Dabbelt # RISC-V +Reviewed-by: Palmer Dabbelt # RISC-V +--- + gcc/common/config/riscv/riscv-common.cc | 11 +++++++++ + gcc/config.in | 6 +++++ + gcc/configure | 31 +++++++++++++++++++++++++ + gcc/configure.ac | 5 ++++ + 4 files changed, 53 insertions(+) + +diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc +index 043dab5da87..1660fcb0ac0 100644 +--- a/gcc/common/config/riscv/riscv-common.cc ++++ b/gcc/common/config/riscv/riscv-common.cc +@@ -831,6 +831,7 @@ riscv_subset_list::to_string (bool version_p) const + riscv_subset_t *subset; + + bool skip_zifencei = false; ++ bool skip_zaamo_zalrsc = false; + bool skip_zicsr = false; + bool i2p0 = false; + +@@ -858,6 +859,10 @@ riscv_subset_list::to_string (bool version_p) const + a mistake in that binutils 2.35 supports zicsr but not zifencei. */ + skip_zifencei = true; + #endif ++#ifndef HAVE_AS_MARCH_ZAAMO_ZALRSC ++ /* Skip since binutils 2.42 and earlier don't recognize zaamo/zalrsc. */ ++ skip_zaamo_zalrsc = true; ++#endif + + for (subset = m_head; subset != NULL; subset = subset->next) + { +@@ -869,6 +874,12 @@ riscv_subset_list::to_string (bool version_p) const + subset->name == "zicsr") + continue; + ++ if (skip_zaamo_zalrsc && subset->name == "zaamo") ++ continue; ++ ++ if (skip_zaamo_zalrsc && subset->name == "zalrsc") ++ continue; ++ + /* For !version_p, we only separate extension with underline for + multi-letter extension. */ + if (!first && +diff --git a/gcc/config.in b/gcc/config.in +index 3daa90be0e8..21a7e12376b 100644 +--- a/gcc/config.in ++++ b/gcc/config.in +@@ -629,6 +629,12 @@ + #endif + + ++/* Define if the assembler understands -march=rv*_zaamo_zalrsc. */ ++#ifndef USED_FOR_TARGET ++#undef HAVE_AS_MARCH_ZAAMO_ZALRSC ++#endif ++ ++ + /* Define if the assembler understands -march=rv*_zifencei. */ + #ifndef USED_FOR_TARGET + #undef HAVE_AS_MARCH_ZIFENCEI +diff --git a/gcc/configure b/gcc/configure +index a4dcd131783..c0dd02ffff5 100755 +--- a/gcc/configure ++++ b/gcc/configure +@@ -31069,6 +31069,37 @@ if test $gcc_cv_as_riscv_march_zifencei = yes; then + + $as_echo "#define HAVE_AS_MARCH_ZIFENCEI 1" >>confdefs.h + ++fi ++ ++ { $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for -march=rv32i_zaamo_zalrsc support" >&5 ++$as_echo_n "checking assembler for -march=rv32i_zaamo_zalrsc support... " >&6; } ++if ${gcc_cv_as_riscv_march_zaamo_zalrsc+:} false; then : ++ $as_echo_n "(cached) " >&6 ++else ++ gcc_cv_as_riscv_march_zaamo_zalrsc=no ++ if test x$gcc_cv_as != x; then ++ $as_echo '' > conftest.s ++ if { ac_try='$gcc_cv_as $gcc_cv_as_flags -march=rv32i_zaamo_zalrsc -o conftest.o conftest.s >&5' ++ { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5 ++ (eval $ac_try) 2>&5 ++ ac_status=$? ++ $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 ++ test $ac_status = 0; }; } ++ then ++ gcc_cv_as_riscv_march_zaamo_zalrsc=yes ++ else ++ echo "configure: failed program was" >&5 ++ cat conftest.s >&5 ++ fi ++ rm -f conftest.o conftest.s ++ fi ++fi ++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_as_riscv_march_zaamo_zalrsc" >&5 ++$as_echo "$gcc_cv_as_riscv_march_zaamo_zalrsc" >&6; } ++if test $gcc_cv_as_riscv_march_zaamo_zalrsc = yes; then ++ ++$as_echo "#define HAVE_AS_MARCH_ZAAMO_ZALRSC 1" >>confdefs.h ++ + fi + + ;; +diff --git a/gcc/configure.ac b/gcc/configure.ac +index cb743b5a875..09ffd6bca3c 100644 +--- a/gcc/configure.ac ++++ b/gcc/configure.ac +@@ -5518,6 +5518,11 @@ configured with --enable-newlib-nano-formatted-io.]) + [-march=rv32i_zifencei2p0],,, + [AC_DEFINE(HAVE_AS_MARCH_ZIFENCEI, 1, + [Define if the assembler understands -march=rv*_zifencei.])]) ++ gcc_GAS_CHECK_FEATURE([-march=rv32i_zaamo_zalrsc support], ++ gcc_cv_as_riscv_march_zaamo_zalrsc, ++ [-march=rv32i_zaamo_zalrsc],,, ++ [AC_DEFINE(HAVE_AS_MARCH_ZAAMO_ZALRSC, 1, ++ [Define if the assembler understands -march=rv*_zaamo_zalrsc.])]) + ;; + loongarch*-*-*) + gcc_GAS_CHECK_FEATURE([.dtprelword support], +-- +2.47.3 + diff --git a/1047-RISC-V-Promote-Zaamo-Zalrsc-to-a-when-using-an-old-b.patch b/1047-RISC-V-Promote-Zaamo-Zalrsc-to-a-when-using-an-old-b.patch new file mode 100644 index 0000000..aac8d37 --- /dev/null +++ b/1047-RISC-V-Promote-Zaamo-Zalrsc-to-a-when-using-an-old-b.patch @@ -0,0 +1,42 @@ +From 6d6ff188950c0b8226f8c93bf0925ab521ce00cc Mon Sep 17 00:00:00 2001 +From: Patrick O'Neill +Date: Tue, 18 Jun 2024 14:40:15 -0700 +Subject: [PATCH 1047/1087] RISC-V: Promote Zaamo/Zalrsc to a when using an old + binutils + +commit e03583e7ee99552276a90a4094776fda55ab2e02 upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +Binutils 2.42 and before don't support Zaamo/Zalrsc. When users specify +both Zaamo and Zalrsc, promote them to 'a' in the -march string. + +This does not affect testsuite results for users with old versions of binutils. +Testcases that failed due to 'call'/isa string continue to fail after this PATCH +when using an old version of binutils. + +gcc/ChangeLog: + + * common/config/riscv/riscv-common.cc: Add 'a' extension to + riscv_combine_info. + +Signed-off-by: Patrick O'Neill +--- + gcc/common/config/riscv/riscv-common.cc | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc +index 1660fcb0ac0..f0a25966316 100644 +--- a/gcc/common/config/riscv/riscv-common.cc ++++ b/gcc/common/config/riscv/riscv-common.cc +@@ -406,6 +406,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] = + /* Combine extensions defined in this table */ + static const struct riscv_ext_version riscv_combine_info[] = + { ++ {"a", ISA_SPEC_CLASS_20191213, 2, 1}, + {"zk", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zkn", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zks", ISA_SPEC_CLASS_NONE, 1, 0}, +-- +2.47.3 + diff --git a/1048-RISC-V-Add-dg-remove-option-for-z-extensions.patch b/1048-RISC-V-Add-dg-remove-option-for-z-extensions.patch new file mode 100644 index 0000000..320f022 --- /dev/null +++ b/1048-RISC-V-Add-dg-remove-option-for-z-extensions.patch @@ -0,0 +1,856 @@ +From bd90cd5ddb68e5a6b8514c91d985ec57c9d816d5 Mon Sep 17 00:00:00 2001 +From: Patrick O'Neill +Date: Mon, 24 Jun 2024 12:06:15 -0700 +Subject: [PATCH 1048/1087] RISC-V: Add dg-remove-option for z* extensions + +commit upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +This introduces testsuite support infra for removing extensions. +Since z* extensions don't have ordering requirements the logic for +adding/removing those extensions has also been consolidated. + +This fixes RVWMO compile testcases failing on Ztso targets by removing +the extension from the -march string. + +gcc/ChangeLog: + + * doc/sourcebuild.texi (dg-remove-option): Add documentation. + (dg-add-option): Add documentation for riscv_{a,zaamo,zalrsc,ztso} + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/amo/amo-table-a-6-amo-add-1.c: Add dg-remove-options + for ztso. + * gcc.target/riscv/amo/amo-table-a-6-amo-add-2.c: Ditto. + * gcc.target/riscv/amo/amo-table-a-6-amo-add-3.c: Ditto. + * gcc.target/riscv/amo/amo-table-a-6-amo-add-4.c: Ditto. + * gcc.target/riscv/amo/amo-table-a-6-amo-add-5.c: Ditto. + * gcc.target/riscv/amo/amo-table-a-6-compare-exchange-1.c: Ditto. + * gcc.target/riscv/amo/amo-table-a-6-compare-exchange-2.c: Ditto. + * gcc.target/riscv/amo/amo-table-a-6-compare-exchange-3.c: Ditto. + * gcc.target/riscv/amo/amo-table-a-6-compare-exchange-4.c: Ditto. + * gcc.target/riscv/amo/amo-table-a-6-compare-exchange-5.c: Ditto. + * gcc.target/riscv/amo/amo-table-a-6-compare-exchange-6.c: Ditto. + * gcc.target/riscv/amo/amo-table-a-6-compare-exchange-7.c: Ditto. + * gcc.target/riscv/amo/amo-table-a-6-fence-1.c: Ditto. + * gcc.target/riscv/amo/amo-table-a-6-fence-2.c: Ditto. + * gcc.target/riscv/amo/amo-table-a-6-fence-3.c: Ditto. + * gcc.target/riscv/amo/amo-table-a-6-fence-4.c: Ditto. + * gcc.target/riscv/amo/amo-table-a-6-fence-5.c: Ditto. + * gcc.target/riscv/amo/amo-table-a-6-load-1.c: Ditto. + * gcc.target/riscv/amo/amo-table-a-6-load-2.c: Ditto. + * gcc.target/riscv/amo/amo-table-a-6-load-3.c: Ditto. + * gcc.target/riscv/amo/amo-table-a-6-store-1.c: Ditto. + * gcc.target/riscv/amo/amo-table-a-6-store-2.c: Ditto. + * gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c: Ditto. + * gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-1.c: Ditto. + * gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-2.c: Ditto. + * gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-3.c: Ditto. + * gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-4.c: Ditto. + * gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-5.c: Ditto. + * gcc.target/riscv/amo/amo-zalrsc-amo-add-1.c: Replace manually + specified -march string with dg-add/remove-options directives. + * gcc.target/riscv/amo/amo-zalrsc-amo-add-2.c: Ditto. + * gcc.target/riscv/amo/amo-zalrsc-amo-add-3.c: Ditto. + * gcc.target/riscv/amo/amo-zalrsc-amo-add-4.c: Ditto. + * gcc.target/riscv/amo/amo-zalrsc-amo-add-5.c: Ditto. + * lib/target-supports-dg.exp: Add dg-remove-options. + * lib/target-supports.exp: Add dg-remove-options and consolidate z* + extension add/remove-option code. + +Signed-off-by: Patrick O'Neill +--- + gcc/doc/sourcebuild.texi | 43 +++++ + .../riscv/amo/amo-table-a-6-amo-add-1.c | 1 + + .../riscv/amo/amo-table-a-6-amo-add-2.c | 1 + + .../riscv/amo/amo-table-a-6-amo-add-3.c | 1 + + .../riscv/amo/amo-table-a-6-amo-add-4.c | 1 + + .../riscv/amo/amo-table-a-6-amo-add-5.c | 1 + + .../amo/amo-table-a-6-compare-exchange-1.c | 1 + + .../amo/amo-table-a-6-compare-exchange-2.c | 1 + + .../amo/amo-table-a-6-compare-exchange-3.c | 1 + + .../amo/amo-table-a-6-compare-exchange-4.c | 1 + + .../amo/amo-table-a-6-compare-exchange-5.c | 1 + + .../amo/amo-table-a-6-compare-exchange-6.c | 1 + + .../amo/amo-table-a-6-compare-exchange-7.c | 1 + + .../riscv/amo/amo-table-a-6-fence-1.c | 1 + + .../riscv/amo/amo-table-a-6-fence-2.c | 1 + + .../riscv/amo/amo-table-a-6-fence-3.c | 1 + + .../riscv/amo/amo-table-a-6-fence-4.c | 1 + + .../riscv/amo/amo-table-a-6-fence-5.c | 1 + + .../riscv/amo/amo-table-a-6-load-1.c | 1 + + .../riscv/amo/amo-table-a-6-load-2.c | 1 + + .../riscv/amo/amo-table-a-6-load-3.c | 1 + + .../riscv/amo/amo-table-a-6-store-1.c | 1 + + .../riscv/amo/amo-table-a-6-store-2.c | 1 + + .../riscv/amo/amo-table-a-6-store-compat-3.c | 1 + + .../amo/amo-table-a-6-subword-amo-add-1.c | 1 + + .../amo/amo-table-a-6-subword-amo-add-2.c | 1 + + .../amo/amo-table-a-6-subword-amo-add-3.c | 1 + + .../amo/amo-table-a-6-subword-amo-add-4.c | 1 + + .../amo/amo-table-a-6-subword-amo-add-5.c | 1 + + .../riscv/amo/amo-zalrsc-amo-add-1.c | 5 +- + .../riscv/amo/amo-zalrsc-amo-add-2.c | 5 +- + .../riscv/amo/amo-zalrsc-amo-add-3.c | 5 +- + .../riscv/amo/amo-zalrsc-amo-add-4.c | 5 +- + .../riscv/amo/amo-zalrsc-amo-add-5.c | 5 +- + gcc/testsuite/lib/target-supports-dg.exp | 16 ++ + gcc/testsuite/lib/target-supports.exp | 182 ++++++++++++++---- + 36 files changed, 248 insertions(+), 46 deletions(-) + +diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi +index f1f723b5d70..4a671c8a295 100644 +--- a/gcc/doc/sourcebuild.texi ++++ b/gcc/doc/sourcebuild.texi +@@ -1015,6 +1015,7 @@ FIXME: discuss non-C testsuites here. + * Selectors:: Selecting targets to which a test applies. + * Effective-Target Keywords:: Keywords describing target attributes. + * Add Options:: Features for @code{dg-add-options} ++* Remove Options:: Features for @code{dg-remove-options} + * Require Support:: Variants of @code{dg-require-@var{support}} + * Final Actions:: Commands for use in @code{dg-final} + @end menu +@@ -1085,6 +1086,13 @@ default, or that don't provide them at all. It must come after + all @code{dg-options} directives. + For supported values of @var{feature} see @ref{Add Options, ,}. + ++@item @{ dg-remove-options @var{feature} @dots{} @} ++Remove any compiler options that are needed to access certain features. ++This directive does nothing on targets that disable the features by ++default, or that don't provide them at all. It must come after ++all @code{dg-options} and @code{dg-add-options} directives. ++For supported values of @var{feature} see @ref{Remove Options, ,}. ++ + @item @{ dg-additional-options @var{options} [@{ target @var{selector} @}] @} + This directive provides a list of compiler options, to be used + if the target system matches @var{selector}, that are added to the default +@@ -3272,6 +3280,18 @@ compliance mode. + @code{mips16} function attributes. + Only MIPS targets support this feature, and only then in certain modes. + ++@item riscv_a ++Add the 'A' extension to the -march string on RISC-V targets. ++ ++@item riscv_zaamo ++Add the zaamo extension to the -march string on RISC-V targets. ++ ++@item riscv_zalrsc ++Add the zalrsc extension to the -march string on RISC-V targets. ++ ++@item riscv_ztso ++Add the ztso extension to the -march string on RISC-V targets. ++ + @item stack_size + @anchor{stack_size_ao} + Add the flags needed to define macro STACK_SIZE and set it to the stack size +@@ -3294,6 +3314,29 @@ a target, if any. This requires the target to have an implementation of the + Add the flags needed to enable support for weak undefined symbols. + @end table + ++@node Remove Options ++@subsection Features for @code{dg-remove-options} ++ ++The supported values of @var{feature} for directive @code{dg-remove-options} ++are: ++ ++@table @code ++@item riscv_a ++Remove the 'A' extension and all implied extensions from the -march string on ++RISC-V targets. ++ ++@item riscv_zaamo ++Remove the zaamo extension from the -march string on RISC-V. If the 'A' ++extension is present downgrade it to zalrsc. ++ ++@item riscv_zalrsc ++Remove the zalrsc extension from the -march string on RISC-V. If the 'A' ++extension is present downgrade it to zaamo. ++ ++@item riscv_ztso ++Remove the ztso extension from the -march string on RISC-V targets. ++@end table ++ + @node Require Support + @subsection Variants of @code{dg-require-@var{support}} + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-1.c +index 2e53abf28aa..2acad7d44bf 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-1.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-1.c +@@ -2,6 +2,7 @@ + /* Verify that atomic op mappings match Table A.6's recommended mapping. */ + /* { dg-options "-O3" } */ + /* { dg-add-options riscv_zaamo } */ ++/* { dg-remove-options riscv_ztso } */ + /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + /* { dg-final { check-function-bodies "**" "" } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-2.c +index 14d6b7e4b1b..ab21f079eaa 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-2.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-2.c +@@ -2,6 +2,7 @@ + /* Verify that atomic op mappings match Table A.6's recommended mapping. */ + /* { dg-options "-O3" } */ + /* { dg-add-options riscv_zaamo } */ ++/* { dg-remove-options riscv_ztso } */ + /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + /* { dg-final { check-function-bodies "**" "" } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-3.c +index 937a00daf4c..919ff37d096 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-3.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-3.c +@@ -2,6 +2,7 @@ + /* Verify that atomic op mappings match Table A.6's recommended mapping. */ + /* { dg-options "-O3" } */ + /* { dg-add-options riscv_zaamo } */ ++/* { dg-remove-options riscv_ztso } */ + /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + /* { dg-final { check-function-bodies "**" "" } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-4.c +index 7d7f4e11dd4..1531d3763b7 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-4.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-4.c +@@ -2,6 +2,7 @@ + /* Verify that atomic op mappings match Table A.6's recommended mapping. */ + /* { dg-options "-O3" } */ + /* { dg-add-options riscv_zaamo } */ ++/* { dg-remove-options riscv_ztso } */ + /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + /* { dg-final { check-function-bodies "**" "" } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-5.c +index e5cf1e2e9cf..03b70111a74 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-5.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-5.c +@@ -2,6 +2,7 @@ + /* Verify that atomic op mappings match Table A.6's recommended mapping. */ + /* { dg-options "-O3" } */ + /* { dg-add-options riscv_zaamo } */ ++/* { dg-remove-options riscv_ztso } */ + /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + /* { dg-final { check-function-bodies "**" "" } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-1.c +index 4917cd6bd2b..fd8a8bfe9c6 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-1.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-1.c +@@ -1,6 +1,7 @@ + /* { dg-do compile } */ + /* Verify that compare exchange mappings match Table A.6's recommended mapping. */ + /* { dg-add-options riscv_zalrsc } */ ++/* { dg-remove-options riscv_ztso } */ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-2.c +index 121936507e3..b3cffad005d 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-2.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-2.c +@@ -1,6 +1,7 @@ + /* { dg-do compile } */ + /* Verify that compare exchange mappings match Table A.6's recommended mapping. */ + /* { dg-add-options riscv_zalrsc } */ ++/* { dg-remove-options riscv_ztso } */ + /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-3.c +index 649c7d2b1fe..70107c40a53 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-3.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-3.c +@@ -1,6 +1,7 @@ + /* { dg-do compile } */ + /* Verify that compare exchange mappings match Table A.6's recommended mapping. */ + /* { dg-add-options riscv_zalrsc } */ ++/* { dg-remove-options riscv_ztso } */ + /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-4.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-4.c +index 5f7fdeb1b21..faab1ab728c 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-4.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-4.c +@@ -1,6 +1,7 @@ + /* { dg-do compile } */ + /* Verify that compare exchange mappings match Table A.6's recommended mapping. */ + /* { dg-add-options riscv_zalrsc } */ ++/* { dg-remove-options riscv_ztso } */ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-5.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-5.c +index f4bd7d6d842..a1435a07a21 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-5.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-5.c +@@ -1,6 +1,7 @@ + /* { dg-do compile } */ + /* Verify that compare exchange mappings match Table A.6's recommended mapping. */ + /* { dg-add-options riscv_zalrsc } */ ++/* { dg-remove-options riscv_ztso } */ + /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-6.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-6.c +index 154764425ae..0cbc89c617c 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-6.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-6.c +@@ -1,6 +1,7 @@ + /* { dg-do compile } */ + /* Verify that compare exchange mappings match Table A.6's recommended mapping. */ + /* { dg-add-options riscv_zalrsc } */ ++/* { dg-remove-options riscv_ztso } */ + /* Mixed mappings need to be unioned. */ + /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-7.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-7.c +index 16712540919..957aa3c0afd 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-7.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-7.c +@@ -1,6 +1,7 @@ + /* { dg-do compile } */ + /* Verify that compare exchange mappings match Table A.6's recommended mapping. */ + /* { dg-add-options riscv_zalrsc } */ ++/* { dg-remove-options riscv_ztso } */ + /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-1.c +index bf590489c39..202479a005e 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-1.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-1.c +@@ -1,6 +1,7 @@ + /* { dg-do compile } */ + /* Verify that fence mappings match Table A.6's recommended mapping. */ + /* { dg-options "-O3" } */ ++/* { dg-remove-options riscv_ztso } */ + /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + /* { dg-final { check-function-bodies "**" "" } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-2.c +index 9848f8cae31..7d6c73a6b50 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-2.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-2.c +@@ -1,6 +1,7 @@ + /* { dg-do compile } */ + /* Verify that fence mappings match Table A.6's recommended mapping. */ + /* { dg-options "-O3" } */ ++/* { dg-remove-options riscv_ztso } */ + /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + /* { dg-final { check-function-bodies "**" "" } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-3.c +index 3c3ce6e0d18..a53889a4fa1 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-3.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-3.c +@@ -1,6 +1,7 @@ + /* { dg-do compile } */ + /* Verify that fence mappings match Table A.6's recommended mapping. */ + /* { dg-options "-O3" } */ ++/* { dg-remove-options riscv_ztso } */ + /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + /* { dg-final { check-function-bodies "**" "" } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-4.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-4.c +index 12d71717085..63a3a234d43 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-4.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-4.c +@@ -1,6 +1,7 @@ + /* { dg-do compile } */ + /* Verify that fence mappings match Table A.6's recommended mapping. */ + /* { dg-options "-O3" } */ ++/* { dg-remove-options riscv_ztso } */ + /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + /* { dg-final { check-function-bodies "**" "" } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-5.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-5.c +index 9567b604c2c..78040bd11e9 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-5.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-5.c +@@ -1,6 +1,7 @@ + /* { dg-do compile } */ + /* Verify that fence mappings match Table A.6's recommended mapping. */ + /* { dg-options "-O3" } */ ++/* { dg-remove-options riscv_ztso } */ + /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + /* { dg-final { check-function-bodies "**" "" } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-1.c +index 948fece6125..7b99db06d75 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-1.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-1.c +@@ -1,6 +1,7 @@ + /* { dg-do compile } */ + /* Verify that load mappings match Table A.6's recommended mapping. */ + /* { dg-options "-O3" } */ ++/* { dg-remove-options riscv_ztso } */ + /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + /* { dg-final { check-function-bodies "**" "" } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-2.c +index e855db9b761..f9871b92c0b 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-2.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-2.c +@@ -1,6 +1,7 @@ + /* { dg-do compile } */ + /* Verify that load mappings match Table A.6's recommended mapping. */ + /* { dg-options "-O3" } */ ++/* { dg-remove-options riscv_ztso } */ + /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + /* { dg-final { check-function-bodies "**" "" } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-3.c +index 6e79ca72abc..35f196c23c0 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-3.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-3.c +@@ -1,6 +1,7 @@ + /* { dg-do compile } */ + /* Verify that load mappings match Table A.6's recommended mapping. */ + /* { dg-options "-O3" } */ ++/* { dg-remove-options riscv_ztso } */ + /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + /* { dg-final { check-function-bodies "**" "" } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-1.c +index ee7e7dbc8ee..eb67d1968e0 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-1.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-1.c +@@ -1,6 +1,7 @@ + /* { dg-do compile } */ + /* Verify that store mappings match Table A.6's recommended mapping. */ + /* { dg-options "-O3" } */ ++/* { dg-remove-options riscv_ztso } */ + /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + /* { dg-final { check-function-bodies "**" "" } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-2.c +index 5110512e1ad..25a998b86eb 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-2.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-2.c +@@ -1,6 +1,7 @@ + /* { dg-do compile } */ + /* Verify that store mappings match Table A.6's recommended mapping. */ + /* { dg-options "-O3" } */ ++/* { dg-remove-options riscv_ztso } */ + /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + /* { dg-final { check-function-bodies "**" "" } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c +index 016e5dec87d..43880b9734a 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c +@@ -1,6 +1,7 @@ + /* { dg-do compile } */ + /* Verify that store mapping are compatible with Table A.6 & A.7. */ + /* { dg-options "-O3" } */ ++/* { dg-remove-options riscv_ztso } */ + /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + /* { dg-final { check-function-bodies "**" "" } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-1.c +index 348b9c8db9c..50009f021dc 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-1.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-1.c +@@ -1,6 +1,7 @@ + /* { dg-do compile } */ + /* Verify that subword atomic op mappings match Table A.6's recommended mapping. */ + /* { dg-add-options riscv_zalrsc } */ ++/* { dg-remove-options riscv_ztso } */ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-2.c +index 31011580684..782ffcb0a70 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-2.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-2.c +@@ -1,6 +1,7 @@ + /* { dg-do compile } */ + /* Verify that subword atomic op mappings match Table A.6's recommended mapping. */ + /* { dg-add-options riscv_zalrsc } */ ++/* { dg-remove-options riscv_ztso } */ + /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-3.c +index 38bedcd6b41..76ec8a81d1f 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-3.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-3.c +@@ -1,6 +1,7 @@ + /* { dg-do compile } */ + /* Verify that subword atomic op mappings match Table A.6's recommended mapping. */ + /* { dg-add-options riscv_zalrsc } */ ++/* { dg-remove-options riscv_ztso } */ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-4.c +index d69610e2d9e..3f5fa20c87c 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-4.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-4.c +@@ -1,6 +1,7 @@ + /* { dg-do compile } */ + /* Verify that subword atomic op mappings match Table A.6's recommended mapping. */ + /* { dg-add-options riscv_zalrsc } */ ++/* { dg-remove-options riscv_ztso } */ + /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-5.c +index 976f8909bdd..7417a67f692 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-5.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-5.c +@@ -1,6 +1,7 @@ + /* { dg-do compile } */ + /* Verify that subword atomic op mappings match Table A.6's recommended mapping. */ + /* { dg-add-options riscv_zalrsc } */ ++/* { dg-remove-options riscv_ztso } */ + /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-1.c +index 49c1a181d69..582e96534de 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-1.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-1.c +@@ -1,6 +1,9 @@ + /* { dg-do compile } */ + /* Verify that lrsc atomic op mappings match Table A.6's recommended mapping. */ +-/* { dg-options "-O3 -march=rv64id_zalrsc -mabi=lp64d" } */ ++/* { dg-options "-O3" } */ ++/* { dg-add-options riscv_zalrsc } */ ++/* { dg-remove-options riscv_zaamo } */ ++/* { dg-remove-options riscv_ztso } */ + /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + /* { dg-final { check-function-bodies "**" "" } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-2.c +index af93c9a182b..987429640de 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-2.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-2.c +@@ -1,6 +1,9 @@ + /* { dg-do compile } */ + /* Verify that lrsc atomic op mappings match Table A.6's recommended mapping. */ +-/* { dg-options "-O3 -march=rv64id_zalrsc -mabi=lp64d" } */ ++/* { dg-options "-O3" } */ ++/* { dg-add-options riscv_zalrsc } */ ++/* { dg-remove-options riscv_zaamo } */ ++/* { dg-remove-options riscv_ztso } */ + /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + /* { dg-final { check-function-bodies "**" "" } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-3.c +index ce68af841ea..b29966ce7d7 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-3.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-3.c +@@ -1,6 +1,9 @@ + /* { dg-do compile } */ + /* Verify that lrsc atomic op mappings match Table A.6's recommended mapping. */ +-/* { dg-options "-O3 -march=rv64id_zalrsc -mabi=lp64d" } */ ++/* { dg-options "-O3" } */ ++/* { dg-add-options riscv_zalrsc } */ ++/* { dg-remove-options riscv_zaamo } */ ++/* { dg-remove-options riscv_ztso } */ + /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + /* { dg-final { check-function-bodies "**" "" } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-4.c +index be9f847782e..5dfb7ac2bac 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-4.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-4.c +@@ -1,6 +1,9 @@ + /* { dg-do compile } */ + /* Verify that lrsc atomic op mappings match Table A.6's recommended mapping. */ +-/* { dg-options "-O3 -march=rv64id_zalrsc -mabi=lp64d" } */ ++/* { dg-options "-O3" } */ ++/* { dg-add-options riscv_zalrsc } */ ++/* { dg-remove-options riscv_zaamo } */ ++/* { dg-remove-options riscv_ztso } */ + /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + /* { dg-final { check-function-bodies "**" "" } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-5.c +index b31170c15db..fcc64131fec 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-5.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-5.c +@@ -1,6 +1,9 @@ + /* { dg-do compile } */ + /* Verify that lrsc atomic op mappings match Table A.6's recommended mapping. */ +-/* { dg-options "-O3 -march=rv64id_zalrsc -mabi=lp64d" } */ ++/* { dg-options "-O3" } */ ++/* { dg-add-options riscv_zalrsc } */ ++/* { dg-remove-options riscv_zaamo } */ ++/* { dg-remove-options riscv_ztso } */ + /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + /* { dg-final { check-function-bodies "**" "" } } */ + +diff --git a/gcc/testsuite/lib/target-supports-dg.exp b/gcc/testsuite/lib/target-supports-dg.exp +index 6dce9fdc1ce..a098beb368e 100644 +--- a/gcc/testsuite/lib/target-supports-dg.exp ++++ b/gcc/testsuite/lib/target-supports-dg.exp +@@ -321,6 +321,22 @@ proc dg-add-options { args } { + } + } + ++# Remove any target-specific flags needed for accessing the given list ++# of features. This must come after all dg-options. ++ ++proc dg-remove-options { args } { ++ upvar dg-extra-tool-flags extra-tool-flags ++ ++ foreach arg [lrange $args 1 end] { ++ if { [info procs remove_options_for_$arg] != "" } { ++ set extra-tool-flags \ ++ [eval [list remove_options_for_$arg ${extra-tool-flags}]] ++ } else { ++ error "Unrecognized option type: $arg" ++ } ++ } ++} ++ + # Compare flags for a test directive against flags that will be used to + # compile the test: multilib flags, flags for torture options, and either + # the default flags for this group of tests or flags specified with a +diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp +index 764d36718f8..bd1d46a0fc7 100644 +--- a/gcc/testsuite/lib/target-supports.exp ++++ b/gcc/testsuite/lib/target-supports.exp +@@ -2215,7 +2215,7 @@ proc riscv_get_arch { } { + + proc add_options_for_riscv_a { flags } { + if { [lsearch $flags -march=*] >= 0 } { +- # If there are multiple -march flags, we have to adjust all of them. ++ # If there are any -march flags, we have to adjust all of them. + set expanded_flags [regsub -all -- {((?:^|[[:space:]])-march=rv[[:digit:]]*)g+} $flags \\1imafd ] + return [regsub -all -- {((?:^|[[:space:]])-march=rv[[:digit:]]*[b-eg-rt-wy]*)a*} $expanded_flags \\1a ] + } +@@ -2225,9 +2225,41 @@ proc add_options_for_riscv_a { flags } { + return "$flags -march=[regsub {(rv[[:digit:]]*[b-eg-rt-wy]*)a*} [riscv_get_arch] &a]" + } + ++proc remove_options_for_riscv_a_only { flags } { ++ # Only remove the 'a' extension. Useful when removing zalrsc/zaamo. ++ if { [lsearch $flags -march=*] >= 0 } { ++ # If there are any -march flags, we have to adjust all of them. ++ set expanded_flags [regsub -all -- {((?:^|[[:space:]])-march=rv[[:digit:]]*)g+} $flags \\1imafd ] ++ set modified_flags [regsub -all -- {((?:^|[[:space:]])-march=rv[[:digit:]]*[b-eg-rt-wy]*)a*} $expanded_flags \\1 ] ++ return $modified_flags ++ } ++ if { [check_effective_target_riscv_a] } { ++ # Manually specify the -march and remove it with another call ++ return [remove_options_for_riscv_a_only "$flags -march=[riscv_get_arch]"] ++ } ++ return $flags ++} ++ ++proc remove_options_for_riscv_a { flags } { ++ # Remove the 'a' extension and implied zalrsc/zaamo extensions. ++ if { [lsearch $flags -march=*] >= 0 } { ++ # If there are any -march flags, we have to adjust all of them. ++ set modified_flags [remove_options_for_riscv_a_only $flags] ++ # Also removed implied extensions ++ set modified_flags [remove_options_for_riscv_z_ext zaamo $flags] ++ set modified_flags [remove_options_for_riscv_z_ext zalrsc $flags] ++ return $modified_flags ++ } ++ if { [check_effective_target_riscv_a] } { ++ # Manually specify the -march and remove it with another call ++ return [remove_options_for_riscv_a "$flags -march=[riscv_get_arch]"] ++ } ++ return $flags ++} ++ + proc add_options_for_riscv_d { flags } { + if { [lsearch $flags -march=*] >= 0 } { +- # If there are multiple -march flags, we have to adjust all of them. ++ # If there are any -march flags, we have to adjust all of them. + return [regsub -all -- {((?:^|[[:space:]])-march=rv[[:digit:]]*[a-ce-rt-wy]*)d*} $flags \\1d ] + } + if { [check_effective_target_riscv_d] } { +@@ -2236,9 +2268,21 @@ proc add_options_for_riscv_d { flags } { + return "$flags -march=[regsub {[[:alnum:]]*} [riscv_get_arch] &d]" + } + ++proc remove_options_for_riscv_d { flags } { ++ if { [lsearch $flags -march=*] >= 0 } { ++ # If there are any -march flags, we have to adjust all of them. ++ return [regsub -all -- {((?:^|[[:space:]])-march=rv[[:digit:]]*[a-ce-rt-wy]*)d*} $flags \\1d ] ++ } ++ if { [check_effective_target_riscv_d] } { ++ # Manually specify the -march and remove it with another call ++ return [remove_options_for_riscv_d "$flags -march=[riscv_get_arch]"] ++ } ++ return $flags ++} ++ + proc add_options_for_riscv_v { flags } { + if { [lsearch $flags -march=*] >= 0 } { +- # If there are multiple -march flags, we have to adjust all of them. ++ # If there are any -march flags, we have to adjust all of them. + return [regsub -all -- {((?:^|[[:space:]])-march=rv[[:digit:]]*[a-rt-uwy]*)v*} $flags \\1v ] + } + if { [check_effective_target_riscv_v] } { +@@ -2247,64 +2291,120 @@ proc add_options_for_riscv_v { flags } { + return "$flags -march=[regsub {[[:alnum:]]*} [riscv_get_arch] &v]" + } + +-proc add_options_for_riscv_zaamo { flags } { ++proc remove_options_for_riscv_v { flags } { + if { [lsearch $flags -march=*] >= 0 } { +- # If there are multiple -march flags, we have to adjust all of them. +- set flags [regsub -all -- {(?:^|[[:space:]])-march=[[:alnum:]_.]*} $flags &_zaamo ] +- return [regsub -all -- {((?:^|[[:space:]])-march=[[:alnum:]_.]*_zaamo[[:alnum:]_.]*)_zaamo} $flags \\1 ] ++ # If there are any -march flags, we have to adjust all of them. ++ return [regsub -all -- {((?:^|[[:space:]])-march=rv[[:digit:]]*[a-rt-uwy]*)v*} $flags \\1 ] + } +- if { [check_effective_target_riscv_zaamo] } { +- return "$flags" ++ if { [check_effective_target_riscv_v] } { ++ # Manually specify the -march and remove it with another call ++ return [remove_options_for_riscv_v "$flags -march=[riscv_get_arch]"] + } +- return "$flags -march=[riscv_get_arch]_zaamo" ++ return $flags + } + +-proc add_options_for_riscv_zalrsc { flags } { +- if { [lsearch $flags -march=*] >= 0 } { +- # If there are multiple -march flags, we have to adjust all of them. +- set flags [regsub -all -- {(?:^|[[:space:]])-march=[[:alnum:]_.]*} $flags &_zalrsc ] +- return [regsub -all -- {((?:^|[[:space:]])-march=[[:alnum:]_.]*_zalrsc[[:alnum:]_.]*)_zalrsc} $flags \\1 ] ++proc add_options_for_riscv_z_ext { ext flags } { ++ if {[lsearch $flags "-march=*"] >= 0} { ++ # If there are any -march flags, we have to adjust all of them. ++ set modified_flags {} ++ foreach flag $flags { ++ if {[regexp {^-march=(\S+)} $flag match march_name]} { ++ if {![string match "*_${ext}*" $march_name]} { ++ set march_name "${march_name}_${ext}" ++ } ++ lappend modified_flags "-march=$march_name" ++ } else { ++ lappend modified_flags $flag ++ } ++ } ++ return [join $modified_flags " "] + } +- if { [check_effective_target_riscv_zalrsc] } { ++ if { [check_effective_target_riscv_$ext] } { + return "$flags" + } +- return "$flags -march=[riscv_get_arch]_zalrsc" ++ return "$flags -march=[riscv_get_arch]_${ext}" + } + +-proc add_options_for_riscv_zfh { flags } { ++proc remove_options_for_riscv_z_ext { ext flags } { + if { [lsearch $flags -march=*] >= 0 } { + # If there are multiple -march flags, we have to adjust all of them. +- set flags [regsub -all -- {(?:^|[[:space:]])-march=[[:alnum:]_.]*} $flags &_zfh ] +- return [regsub -all -- {((?:^|[[:space:]])-march=[[:alnum:]_.]*_zfh[[:alnum:]_.]*)_zfh} $flags \\1 ] ++ set modified_flags "" ++ foreach flag $flags { ++ if {[regexp {^-march=(\S+)} $flag -> march_name]} { ++ # Remove "_ext" from the march_name if present ++ set march_name [string map [list _${ext} {}] $march_name] ++ lappend modified_flags "-march=$march_name" ++ } else { ++ lappend modified_flags $flag ++ } ++ } ++ return [join $modified_flags " "] + } +- if { [check_effective_target_riscv_zfh] } { +- return "$flags" ++ if { [check_effective_target_riscv_$ext] } { ++ # Manually specify the -march and remove it with another call ++ return [remove_options_for_riscv_z_ext $ext "$flags -march=[riscv_get_arch]"] + } +- return "$flags -march=[riscv_get_arch]_zfh" ++ return $flags + } + +-proc add_options_for_riscv_ztso { flags } { +- if { [lsearch $flags -march=*] >= 0 } { +- # If there are multiple -march flags, we have to adjust all of them. +- set flags [regsub -all -- {(?:^|[[:space:]])-march=[[:alnum:]_.]*} $flags &_ztso ] +- return [regsub -all -- {((?:^|[[:space:]])-march=[[:alnum:]_.]*_ztso[[:alnum:]_.]*)_ztso} $flags \\1 ] +- } +- if { [check_effective_target_riscv_ztso] } { +- return "$flags" +- } +- return "$flags -march=[riscv_get_arch]_ztso" ++proc add_options_for_riscv_zaamo { flags } { ++ return [add_options_for_riscv_z_ext zaamo $flags] + } + +-proc add_options_for_riscv_zvfh { flags } { +- if { [lsearch $flags -march=*] >= 0 } { +- # If there are multiple -march flags, we have to adjust all of them. +- set flags [regsub -all -- {(?:^|[[:space:]])-march=[[:alnum:]_.]*} $flags &_zvfh ] +- return [regsub -all -- {((?:^|[[:space:]])-march=[[:alnum:]_.]*_zvfh[[:alnum:]_.]*)_zvfh} $flags \\1 ] ++proc remove_options_for_riscv_zaamo { flags } { ++ set modified_flags [remove_options_for_riscv_z_ext zaamo $flags] ++ # If 'a' is set then zaamo will be implied. We need to downgrade instances ++ # of 'a' to 'zalrsc' ++ set no_a_flags [remove_options_for_riscv_a_only [split $modified_flags]] ++ if {![string equal $modified_flags $no_a_flags]} { ++ # 'a' was removed, add 'zalrsc' since it was previously implied ++ set modified_flags [add_options_for_riscv_zalrsc [split $no_a_flags]] + } +- if { [check_effective_target_riscv_zvfh] } { +- return "$flags" ++ return $modified_flags ++} ++ ++proc add_options_for_riscv_zalrsc { flags } { ++ return [add_options_for_riscv_z_ext zalrsc $flags] ++} ++ ++proc remove_options_for_riscv_zalrsc { flags } { ++ set modified_flags [remove_options_for_riscv_z_ext zalrsc $flags] ++ # If 'a' is set then zalrsc will be implied. We need to downgrade instances ++ # of 'a' to 'zaamo' ++ set no_a_flags [remove_options_for_riscv_a_only [split $modified_flags]] ++ if {![string equal $modified_flags $no_a_flags]} { ++ # 'a' was removed, add 'zalrsc' since it was previously implied ++ set modified_flags [add_options_for_riscv_zalrsc [split $no_a_flags]] + } +- return "$flags -march=[riscv_get_arch]_zvfh" ++ return $modified_flags ++} ++ ++proc add_options_for_riscv_zfh { flags } { ++ return [add_options_for_riscv_z_ext zfh $flags] ++} ++ ++proc remove_options_for_riscv_zfh { flags } { ++ return [remove_options_for_riscv_z_ext zfh $flags] ++} ++ ++proc add_options_for_riscv_ztso { flags } { ++ return [add_options_for_riscv_z_ext ztso $flags] ++} ++ ++proc remove_options_for_riscv_ztso { flags } { ++ return [remove_options_for_riscv_z_ext ztso $flags] ++} ++ ++proc remove_options_for_riscv_zvfh { flags } { ++ return [add_options_for_riscv_z_ext zvfh $flags] ++} ++ ++proc add_options_for_riscv_zvbb { flags } { ++ return [add_options_for_riscv_z_ext zvbb $flags] ++} ++ ++proc remove_options_for_riscv_zvbb { flags } { ++ return [add_options_for_riscv_z_ext zvbb $flags] + } + + proc add_options_for_riscv_zvbb { flags } { +-- +2.47.3 + diff --git a/1049-RISC-V-Rename-amo-testcases.patch b/1049-RISC-V-Rename-amo-testcases.patch new file mode 100644 index 0000000..647d687 --- /dev/null +++ b/1049-RISC-V-Rename-amo-testcases.patch @@ -0,0 +1,318 @@ +From e5f199886ff160fd2b8ac7d8be4c27ab6d272f86 Mon Sep 17 00:00:00 2001 +From: Patrick O'Neill +Date: Tue, 25 Jun 2024 14:14:16 -0700 +Subject: [PATCH 1049/1087] RISC-V: Rename amo testcases + +commit 08498f81f0595eb8a90ea33afd7dab44bb76b293 upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +Rename riscv/amo/ testcases to follow a '{ext}-{model}-{name}-{memory order}.c' +naming convention. + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/amo/amo-table-a-6-load-2.c: Move to... + * gcc.target/riscv/amo/a-rvwmo-load-acquire.c: ...here. + * gcc.target/riscv/amo/amo-table-a-6-load-1.c: Move to... + * gcc.target/riscv/amo/a-rvwmo-load-relaxed.c: ...here. + * gcc.target/riscv/amo/amo-table-a-6-load-3.c: Move to... + * gcc.target/riscv/amo/a-rvwmo-load-seq-cst.c: ...here. + * gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c: Move to... + * gcc.target/riscv/amo/a-rvwmo-store-compat-seq-cst.c: ...here. + * gcc.target/riscv/amo/amo-table-a-6-store-1.c: Move to... + * gcc.target/riscv/amo/a-rvwmo-store-relaxed.c: ...here. + * gcc.target/riscv/amo/amo-table-a-6-store-2.c: Move to... + * gcc.target/riscv/amo/a-rvwmo-store-release.c: ...here. + * gcc.target/riscv/amo/amo-table-ztso-load-2.c: Move to... + * gcc.target/riscv/amo/a-ztso-load-acquire.c: ...here. + * gcc.target/riscv/amo/amo-table-ztso-load-1.c: Move to... + * gcc.target/riscv/amo/a-ztso-load-relaxed.c: ...here. + * gcc.target/riscv/amo/amo-table-ztso-load-3.c: Move to... + * gcc.target/riscv/amo/a-ztso-load-seq-cst.c: ...here. + * gcc.target/riscv/amo/amo-table-ztso-store-3.c: Move to... + * gcc.target/riscv/amo/a-ztso-store-compat-seq-cst.c: ...here. + * gcc.target/riscv/amo/amo-table-ztso-store-1.c: Move to... + * gcc.target/riscv/amo/a-ztso-store-relaxed.c: ...here. + * gcc.target/riscv/amo/amo-table-ztso-store-2.c: Move to... + * gcc.target/riscv/amo/a-ztso-store-release.c: ...here. + * gcc.target/riscv/amo/amo-zaamo-preferred-over-zalrsc.c: Move to... + * gcc.target/riscv/amo/zaamo-preferred-over-zalrsc.c: ...here. + * gcc.target/riscv/amo/amo-table-a-6-compare-exchange-6.c: Move to... + * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire-release.c: ...here. + * gcc.target/riscv/amo/amo-table-a-6-compare-exchange-3.c: Move to... + * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire.c: ...here. + * gcc.target/riscv/amo/amo-table-a-6-compare-exchange-2.c: Move to... + * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-consume.c: ...here. + * gcc.target/riscv/amo/amo-table-a-6-compare-exchange-1.c: Move to... + * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-relaxed.c: ...here. + * gcc.target/riscv/amo/amo-table-a-6-compare-exchange-4.c: Move to... + * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-release.c: ...here. + * gcc.target/riscv/amo/amo-table-a-6-compare-exchange-7.c: Move to... + * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst-relaxed.c: ...here. + * gcc.target/riscv/amo/amo-table-a-6-compare-exchange-5.c: Move to... + * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst.c: ...here. + * gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-4.c: Move to... + * gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acq-rel.c: ...here. + * gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-2.c: Move to... + * gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acquire.c: ...here. + * gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-1.c: Move to... + * gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-relaxed.c: ...here. + * gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-3.c: Move to... + * gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-release.c: ...here. + * gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-5.c: Move to... + * gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-seq-cst.c: ...here. + * gcc.target/riscv/amo/amo-table-ztso-compare-exchange-6.c: Move to... + * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire-release.c: ...here. + * gcc.target/riscv/amo/amo-table-ztso-compare-exchange-3.c: Move to... + * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire.c: ...here. + * gcc.target/riscv/amo/amo-table-ztso-compare-exchange-2.c: Move to... + * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-consume.c: ...here. + * gcc.target/riscv/amo/amo-table-ztso-compare-exchange-1.c: Move to... + * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-relaxed.c: ...here. + * gcc.target/riscv/amo/amo-table-ztso-compare-exchange-4.c: Move to... + * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-release.c: ...here. + * gcc.target/riscv/amo/amo-table-ztso-compare-exchange-7.c: Move to... + * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst-relaxed.c: ...here. + * gcc.target/riscv/amo/amo-table-ztso-compare-exchange-5.c: Move to... + * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst.c: ...here. + * gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-4.c: Move to... + * gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acq-rel.c: ...here. + * gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-2.c: Move to... + * gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acquire.c: ...here. + * gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-1.c: Move to... + * gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-relaxed.c: ...here. + * gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-3.c: Move to... + * gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-release.c: ...here. + * gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-5.c: Move to... + * gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-seq-cst.c: ...here. + +Signed-off-by: Patrick O'Neill +--- + .../riscv/amo/{amo-table-a-6-load-2.c => a-rvwmo-load-acquire.c} | 0 + .../riscv/amo/{amo-table-a-6-load-1.c => a-rvwmo-load-relaxed.c} | 0 + .../riscv/amo/{amo-table-a-6-load-3.c => a-rvwmo-load-seq-cst.c} | 0 + ...-table-a-6-store-compat-3.c => a-rvwmo-store-compat-seq-cst.c} | 0 + .../amo/{amo-table-a-6-store-1.c => a-rvwmo-store-relaxed.c} | 0 + .../amo/{amo-table-a-6-store-2.c => a-rvwmo-store-release.c} | 0 + .../riscv/amo/{amo-table-ztso-load-2.c => a-ztso-load-acquire.c} | 0 + .../riscv/amo/{amo-table-ztso-load-1.c => a-ztso-load-relaxed.c} | 0 + .../riscv/amo/{amo-table-ztso-load-3.c => a-ztso-load-seq-cst.c} | 0 + .../{amo-table-ztso-store-3.c => a-ztso-store-compat-seq-cst.c} | 0 + .../amo/{amo-table-ztso-store-1.c => a-ztso-store-relaxed.c} | 0 + .../amo/{amo-table-ztso-store-2.c => a-ztso-store-release.c} | 0 + ...aamo-preferred-over-zalrsc.c => zaamo-preferred-over-zalrsc.c} | 0 + ...ge-6.c => zalrsc-rvwmo-compare-exchange-int-acquire-release.c} | 0 + ...e-exchange-3.c => zalrsc-rvwmo-compare-exchange-int-acquire.c} | 0 + ...e-exchange-2.c => zalrsc-rvwmo-compare-exchange-int-consume.c} | 0 + ...e-exchange-1.c => zalrsc-rvwmo-compare-exchange-int-relaxed.c} | 0 + ...e-exchange-4.c => zalrsc-rvwmo-compare-exchange-int-release.c} | 0 + ...ge-7.c => zalrsc-rvwmo-compare-exchange-int-seq-cst-relaxed.c} | 0 + ...e-exchange-5.c => zalrsc-rvwmo-compare-exchange-int-seq-cst.c} | 0 + ...rd-amo-add-4.c => zalrsc-rvwmo-subword-amo-add-char-acq-rel.c} | 0 + ...rd-amo-add-2.c => zalrsc-rvwmo-subword-amo-add-char-acquire.c} | 0 + ...rd-amo-add-1.c => zalrsc-rvwmo-subword-amo-add-char-relaxed.c} | 0 + ...rd-amo-add-3.c => zalrsc-rvwmo-subword-amo-add-char-release.c} | 0 + ...rd-amo-add-5.c => zalrsc-rvwmo-subword-amo-add-char-seq-cst.c} | 0 + ...nge-6.c => zalrsc-ztso-compare-exchange-int-acquire-release.c} | 0 + ...re-exchange-3.c => zalrsc-ztso-compare-exchange-int-acquire.c} | 0 + ...re-exchange-2.c => zalrsc-ztso-compare-exchange-int-consume.c} | 0 + ...re-exchange-1.c => zalrsc-ztso-compare-exchange-int-relaxed.c} | 0 + ...re-exchange-4.c => zalrsc-ztso-compare-exchange-int-release.c} | 0 + ...nge-7.c => zalrsc-ztso-compare-exchange-int-seq-cst-relaxed.c} | 0 + ...re-exchange-5.c => zalrsc-ztso-compare-exchange-int-seq-cst.c} | 0 + ...ord-amo-add-4.c => zalrsc-ztso-subword-amo-add-char-acq-rel.c} | 0 + ...ord-amo-add-2.c => zalrsc-ztso-subword-amo-add-char-acquire.c} | 0 + ...ord-amo-add-1.c => zalrsc-ztso-subword-amo-add-char-relaxed.c} | 0 + ...ord-amo-add-3.c => zalrsc-ztso-subword-amo-add-char-release.c} | 0 + ...ord-amo-add-5.c => zalrsc-ztso-subword-amo-add-char-seq-cst.c} | 0 + 37 files changed, 0 insertions(+), 0 deletions(-) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-a-6-load-2.c => a-rvwmo-load-acquire.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-a-6-load-1.c => a-rvwmo-load-relaxed.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-a-6-load-3.c => a-rvwmo-load-seq-cst.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-a-6-store-compat-3.c => a-rvwmo-store-compat-seq-cst.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-a-6-store-1.c => a-rvwmo-store-relaxed.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-a-6-store-2.c => a-rvwmo-store-release.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-ztso-load-2.c => a-ztso-load-acquire.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-ztso-load-1.c => a-ztso-load-relaxed.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-ztso-load-3.c => a-ztso-load-seq-cst.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-ztso-store-3.c => a-ztso-store-compat-seq-cst.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-ztso-store-1.c => a-ztso-store-relaxed.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-ztso-store-2.c => a-ztso-store-release.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-zaamo-preferred-over-zalrsc.c => zaamo-preferred-over-zalrsc.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-a-6-compare-exchange-6.c => zalrsc-rvwmo-compare-exchange-int-acquire-release.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-a-6-compare-exchange-3.c => zalrsc-rvwmo-compare-exchange-int-acquire.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-a-6-compare-exchange-2.c => zalrsc-rvwmo-compare-exchange-int-consume.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-a-6-compare-exchange-1.c => zalrsc-rvwmo-compare-exchange-int-relaxed.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-a-6-compare-exchange-4.c => zalrsc-rvwmo-compare-exchange-int-release.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-a-6-compare-exchange-7.c => zalrsc-rvwmo-compare-exchange-int-seq-cst-relaxed.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-a-6-compare-exchange-5.c => zalrsc-rvwmo-compare-exchange-int-seq-cst.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-a-6-subword-amo-add-4.c => zalrsc-rvwmo-subword-amo-add-char-acq-rel.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-a-6-subword-amo-add-2.c => zalrsc-rvwmo-subword-amo-add-char-acquire.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-a-6-subword-amo-add-1.c => zalrsc-rvwmo-subword-amo-add-char-relaxed.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-a-6-subword-amo-add-3.c => zalrsc-rvwmo-subword-amo-add-char-release.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-a-6-subword-amo-add-5.c => zalrsc-rvwmo-subword-amo-add-char-seq-cst.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-ztso-compare-exchange-6.c => zalrsc-ztso-compare-exchange-int-acquire-release.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-ztso-compare-exchange-3.c => zalrsc-ztso-compare-exchange-int-acquire.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-ztso-compare-exchange-2.c => zalrsc-ztso-compare-exchange-int-consume.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-ztso-compare-exchange-1.c => zalrsc-ztso-compare-exchange-int-relaxed.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-ztso-compare-exchange-4.c => zalrsc-ztso-compare-exchange-int-release.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-ztso-compare-exchange-7.c => zalrsc-ztso-compare-exchange-int-seq-cst-relaxed.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-ztso-compare-exchange-5.c => zalrsc-ztso-compare-exchange-int-seq-cst.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-ztso-subword-amo-add-4.c => zalrsc-ztso-subword-amo-add-char-acq-rel.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-ztso-subword-amo-add-2.c => zalrsc-ztso-subword-amo-add-char-acquire.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-ztso-subword-amo-add-1.c => zalrsc-ztso-subword-amo-add-char-relaxed.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-ztso-subword-amo-add-3.c => zalrsc-ztso-subword-amo-add-char-release.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-ztso-subword-amo-add-5.c => zalrsc-ztso-subword-amo-add-char-seq-cst.c} (100%) + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-2.c b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-acquire.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-2.c +rename to gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-acquire.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-1.c b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-relaxed.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-1.c +rename to gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-relaxed.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-3.c b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-seq-cst.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-3.c +rename to gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-seq-cst.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-compat-seq-cst.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c +rename to gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-compat-seq-cst.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-1.c b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-relaxed.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-1.c +rename to gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-relaxed.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-2.c b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-release.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-2.c +rename to gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-release.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-2.c b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-acquire.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-2.c +rename to gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-acquire.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-1.c b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-relaxed.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-1.c +rename to gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-relaxed.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-3.c b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-seq-cst.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-3.c +rename to gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-seq-cst.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-3.c b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-compat-seq-cst.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-3.c +rename to gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-compat-seq-cst.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-1.c b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-relaxed.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-1.c +rename to gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-relaxed.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-2.c b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-release.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-2.c +rename to gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-release.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-zaamo-preferred-over-zalrsc.c b/gcc/testsuite/gcc.target/riscv/amo/zaamo-preferred-over-zalrsc.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-zaamo-preferred-over-zalrsc.c +rename to gcc/testsuite/gcc.target/riscv/amo/zaamo-preferred-over-zalrsc.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-6.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire-release.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-6.c +rename to gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire-release.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-3.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-3.c +rename to gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-2.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-consume.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-2.c +rename to gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-consume.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-1.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-relaxed.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-1.c +rename to gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-relaxed.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-4.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-release.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-4.c +rename to gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-release.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-7.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst-relaxed.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-7.c +rename to gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst-relaxed.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-5.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-5.c +rename to gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acq-rel.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-4.c +rename to gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acq-rel.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acquire.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-2.c +rename to gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acquire.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-relaxed.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-1.c +rename to gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-relaxed.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-release.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-3.c +rename to gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-release.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-seq-cst.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-5.c +rename to gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-seq-cst.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-compare-exchange-6.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire-release.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-compare-exchange-6.c +rename to gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire-release.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-compare-exchange-3.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-compare-exchange-3.c +rename to gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-compare-exchange-2.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-consume.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-compare-exchange-2.c +rename to gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-consume.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-compare-exchange-1.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-relaxed.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-compare-exchange-1.c +rename to gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-relaxed.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-compare-exchange-4.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-release.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-compare-exchange-4.c +rename to gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-release.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-compare-exchange-7.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst-relaxed.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-compare-exchange-7.c +rename to gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst-relaxed.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-compare-exchange-5.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-compare-exchange-5.c +rename to gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acq-rel.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-4.c +rename to gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acq-rel.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acquire.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-2.c +rename to gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acquire.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-relaxed.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-1.c +rename to gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-relaxed.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-release.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-3.c +rename to gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-release.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-seq-cst.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-5.c +rename to gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-seq-cst.c +-- +2.47.3 + diff --git a/1050-RISC-V-Consolidate-amo-testcase-variants.patch b/1050-RISC-V-Consolidate-amo-testcase-variants.patch new file mode 100644 index 0000000..f58e474 --- /dev/null +++ b/1050-RISC-V-Consolidate-amo-testcase-variants.patch @@ -0,0 +1,1118 @@ +From d2fb532da9ed8ce341700d21341cc5229ce9db9e Mon Sep 17 00:00:00 2001 +From: Patrick O'Neill +Date: Tue, 25 Jun 2024 14:14:17 -0700 +Subject: [PATCH 1050/1087] RISC-V: Consolidate amo testcase variants + +commit aa89e86f70ac65e2d51f33ac45849d05a4f30524 upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +Many riscv/amo/ testcases use check-function-bodies. These testcases can be +consolidated with related testcases (memory ordering variants) without affecting +the assertions. + +Give functions descriptive names so testsuite failures are obvious from the +'FAIL:' line. + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/amo/amo-table-a-6-amo-add-1.c: Removed. + * gcc.target/riscv/amo/amo-table-a-6-amo-add-2.c: Removed. + * gcc.target/riscv/amo/amo-table-a-6-amo-add-3.c: Removed. + * gcc.target/riscv/amo/amo-table-a-6-amo-add-4.c: Removed. + * gcc.target/riscv/amo/amo-table-a-6-amo-add-5.c: Removed. + * gcc.target/riscv/amo/amo-table-a-6-fence-1.c: Removed. + * gcc.target/riscv/amo/amo-table-a-6-fence-2.c: Removed. + * gcc.target/riscv/amo/amo-table-a-6-fence-3.c: Removed. + * gcc.target/riscv/amo/amo-table-a-6-fence-4.c: Removed. + * gcc.target/riscv/amo/amo-table-a-6-fence-5.c: Removed. + * gcc.target/riscv/amo/amo-table-ztso-amo-add-1.c: Removed. + * gcc.target/riscv/amo/amo-table-ztso-amo-add-2.c: Removed. + * gcc.target/riscv/amo/amo-table-ztso-amo-add-3.c: Removed. + * gcc.target/riscv/amo/amo-table-ztso-amo-add-4.c: Removed. + * gcc.target/riscv/amo/amo-table-ztso-amo-add-5.c: Removed. + * gcc.target/riscv/amo/amo-table-ztso-fence-1.c: Removed. + * gcc.target/riscv/amo/amo-table-ztso-fence-2.c: Removed. + * gcc.target/riscv/amo/amo-table-ztso-fence-3.c: Removed. + * gcc.target/riscv/amo/amo-table-ztso-fence-4.c: Removed. + * gcc.target/riscv/amo/amo-table-ztso-fence-5.c: Removed. + * gcc.target/riscv/amo/amo-zalrsc-amo-add-1.c: Removed. + * gcc.target/riscv/amo/amo-zalrsc-amo-add-2.c: Removed. + * gcc.target/riscv/amo/amo-zalrsc-amo-add-3.c: Removed. + * gcc.target/riscv/amo/amo-zalrsc-amo-add-4.c: Removed. + * gcc.target/riscv/amo/amo-zalrsc-amo-add-5.c: Removed. + * gcc.target/riscv/amo/a-rvwmo-fence.c: New test. + * gcc.target/riscv/amo/a-ztso-fence.c: New test. + * gcc.target/riscv/amo/zaamo-rvwmo-amo-add-int.c: New test. + * gcc.target/riscv/amo/zaamo-ztso-amo-add-int.c: New test. + * gcc.target/riscv/amo/zalrsc-rvwmo-amo-add-int.c: New test. + * gcc.target/riscv/amo/zalrsc-ztso-amo-add-int.c: New test. + +Signed-off-by: Patrick O'Neill +--- + .../gcc.target/riscv/amo/a-rvwmo-fence.c | 56 +++++++++++++ + .../gcc.target/riscv/amo/a-ztso-fence.c | 52 +++++++++++++ + .../riscv/amo/amo-table-a-6-amo-add-1.c | 17 ---- + .../riscv/amo/amo-table-a-6-amo-add-2.c | 17 ---- + .../riscv/amo/amo-table-a-6-amo-add-3.c | 17 ---- + .../riscv/amo/amo-table-a-6-amo-add-4.c | 17 ---- + .../riscv/amo/amo-table-a-6-amo-add-5.c | 17 ---- + .../riscv/amo/amo-table-a-6-fence-1.c | 15 ---- + .../riscv/amo/amo-table-a-6-fence-2.c | 16 ---- + .../riscv/amo/amo-table-a-6-fence-3.c | 16 ---- + .../riscv/amo/amo-table-a-6-fence-4.c | 16 ---- + .../riscv/amo/amo-table-a-6-fence-5.c | 16 ---- + .../riscv/amo/amo-table-ztso-amo-add-1.c | 17 ---- + .../riscv/amo/amo-table-ztso-amo-add-2.c | 17 ---- + .../riscv/amo/amo-table-ztso-amo-add-3.c | 17 ---- + .../riscv/amo/amo-table-ztso-amo-add-4.c | 17 ---- + .../riscv/amo/amo-table-ztso-amo-add-5.c | 17 ---- + .../riscv/amo/amo-table-ztso-fence-1.c | 15 ---- + .../riscv/amo/amo-table-ztso-fence-2.c | 15 ---- + .../riscv/amo/amo-table-ztso-fence-3.c | 15 ---- + .../riscv/amo/amo-table-ztso-fence-4.c | 15 ---- + .../riscv/amo/amo-table-ztso-fence-5.c | 16 ---- + .../riscv/amo/amo-zalrsc-amo-add-1.c | 22 ------ + .../riscv/amo/amo-zalrsc-amo-add-2.c | 22 ------ + .../riscv/amo/amo-zalrsc-amo-add-3.c | 22 ------ + .../riscv/amo/amo-zalrsc-amo-add-4.c | 22 ------ + .../riscv/amo/amo-zalrsc-amo-add-5.c | 22 ------ + .../riscv/amo/zaamo-rvwmo-amo-add-int.c | 57 ++++++++++++++ + .../riscv/amo/zaamo-ztso-amo-add-int.c | 57 ++++++++++++++ + .../riscv/amo/zalrsc-rvwmo-amo-add-int.c | 78 +++++++++++++++++++ + .../riscv/amo/zalrsc-ztso-amo-add-int.c | 78 +++++++++++++++++++ + 31 files changed, 378 insertions(+), 435 deletions(-) + create mode 100644 gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-fence.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo/a-ztso-fence.c + delete mode 100644 gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-1.c + delete mode 100644 gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-2.c + delete mode 100644 gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-3.c + delete mode 100644 gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-4.c + delete mode 100644 gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-5.c + delete mode 100644 gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-1.c + delete mode 100644 gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-2.c + delete mode 100644 gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-3.c + delete mode 100644 gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-4.c + delete mode 100644 gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-5.c + delete mode 100644 gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-1.c + delete mode 100644 gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-2.c + delete mode 100644 gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-3.c + delete mode 100644 gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-4.c + delete mode 100644 gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-5.c + delete mode 100644 gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-fence-1.c + delete mode 100644 gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-fence-2.c + delete mode 100644 gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-fence-3.c + delete mode 100644 gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-fence-4.c + delete mode 100644 gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-fence-5.c + delete mode 100644 gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-1.c + delete mode 100644 gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-2.c + delete mode 100644 gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-3.c + delete mode 100644 gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-4.c + delete mode 100644 gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-5.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo/zaamo-rvwmo-amo-add-int.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo/zaamo-ztso-amo-add-int.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-amo-add-int.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-amo-add-int.c + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-fence.c b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-fence.c +new file mode 100644 +index 00000000000..5b9400f7da8 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-fence.c +@@ -0,0 +1,56 @@ ++/* { dg-do compile } */ ++/* Verify that fence mappings match Table A.6's recommended mapping. */ ++/* { dg-options "-O3" } */ ++/* { dg-remove-options riscv_ztso } */ ++/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ ++/* { dg-final { check-function-bodies "**" "" } } */ ++ ++/* ++** fence_relaxed: ++** ret ++*/ ++void fence_relaxed() ++{ ++ __atomic_thread_fence(__ATOMIC_RELAXED); ++} ++ ++/* ++** fence_acquire: ++** fence\tr,rw ++** ret ++*/ ++void fence_acquire() ++{ ++ __atomic_thread_fence(__ATOMIC_ACQUIRE); ++} ++ ++/* ++** fence_release: ++** fence\trw,w ++** ret ++*/ ++void fence_release() ++{ ++ __atomic_thread_fence(__ATOMIC_RELEASE); ++} ++ ++/* ++** fence_acq_rel: ++** fence\.tso ++** ret ++*/ ++void fence_acq_rel() ++{ ++ __atomic_thread_fence(__ATOMIC_ACQ_REL); ++} ++ ++/* ++** fence_seq_cst: ++** fence\trw,rw ++** ret ++*/ ++void fence_seq_cst() ++{ ++ __atomic_thread_fence(__ATOMIC_SEQ_CST); ++} ++ +diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-fence.c b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-fence.c +new file mode 100644 +index 00000000000..37daeda8354 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-fence.c +@@ -0,0 +1,52 @@ ++/* { dg-do compile } */ ++/* Verify that fence mappings match the Ztso suggested mapping. */ ++/* { dg-options "-O3" } */ ++/* { dg-add-options riscv_ztso } */ ++/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ ++/* { dg-final { check-function-bodies "**" "" } } */ ++ ++/* ++** fence_relaxed: ++** ret ++*/ ++void fence_relaxed() ++{ ++ __atomic_thread_fence(__ATOMIC_RELAXED); ++} ++ ++/* ++** fence_acquire: ++** ret ++*/ ++void fence_acquire() ++{ ++ __atomic_thread_fence(__ATOMIC_ACQUIRE); ++} ++ ++/* ++** fence_release: ++** ret ++*/ ++void fence_release() ++{ ++ __atomic_thread_fence(__ATOMIC_RELEASE); ++} ++ ++/* ++** fence_acq_rel: ++** ret ++*/ ++void fence_acq_rel() ++{ ++ __atomic_thread_fence(__ATOMIC_ACQ_REL); ++} ++ ++/* ++** fence_seq_cst: ++** fence\trw,rw ++** ret ++*/ ++void fence_seq_cst() ++{ ++ __atomic_thread_fence(__ATOMIC_SEQ_CST); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-1.c +deleted file mode 100644 +index 2acad7d44bf..00000000000 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-1.c ++++ /dev/null +@@ -1,17 +0,0 @@ +-/* { dg-do compile } */ +-/* Verify that atomic op mappings match Table A.6's recommended mapping. */ +-/* { dg-options "-O3" } */ +-/* { dg-add-options riscv_zaamo } */ +-/* { dg-remove-options riscv_ztso } */ +-/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +-/* { dg-final { check-function-bodies "**" "" } } */ +- +-/* +-** foo: +-** amoadd\.w\tzero,a1,0\(a0\) +-** ret +-*/ +-void foo (int* bar, int baz) +-{ +- __atomic_add_fetch(bar, baz, __ATOMIC_RELAXED); +-} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-2.c +deleted file mode 100644 +index ab21f079eaa..00000000000 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-2.c ++++ /dev/null +@@ -1,17 +0,0 @@ +-/* { dg-do compile } */ +-/* Verify that atomic op mappings match Table A.6's recommended mapping. */ +-/* { dg-options "-O3" } */ +-/* { dg-add-options riscv_zaamo } */ +-/* { dg-remove-options riscv_ztso } */ +-/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +-/* { dg-final { check-function-bodies "**" "" } } */ +- +-/* +-** foo: +-** amoadd\.w\.aq\tzero,a1,0\(a0\) +-** ret +-*/ +-void foo (int* bar, int baz) +-{ +- __atomic_add_fetch(bar, baz, __ATOMIC_ACQUIRE); +-} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-3.c +deleted file mode 100644 +index 919ff37d096..00000000000 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-3.c ++++ /dev/null +@@ -1,17 +0,0 @@ +-/* { dg-do compile } */ +-/* Verify that atomic op mappings match Table A.6's recommended mapping. */ +-/* { dg-options "-O3" } */ +-/* { dg-add-options riscv_zaamo } */ +-/* { dg-remove-options riscv_ztso } */ +-/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +-/* { dg-final { check-function-bodies "**" "" } } */ +- +-/* +-** foo: +-** amoadd\.w\.rl\tzero,a1,0\(a0\) +-** ret +-*/ +-void foo (int* bar, int baz) +-{ +- __atomic_add_fetch(bar, baz, __ATOMIC_RELEASE); +-} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-4.c +deleted file mode 100644 +index 1531d3763b7..00000000000 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-4.c ++++ /dev/null +@@ -1,17 +0,0 @@ +-/* { dg-do compile } */ +-/* Verify that atomic op mappings match Table A.6's recommended mapping. */ +-/* { dg-options "-O3" } */ +-/* { dg-add-options riscv_zaamo } */ +-/* { dg-remove-options riscv_ztso } */ +-/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +-/* { dg-final { check-function-bodies "**" "" } } */ +- +-/* +-** foo: +-** amoadd\.w\.aqrl\tzero,a1,0\(a0\) +-** ret +-*/ +-void foo (int* bar, int baz) +-{ +- __atomic_add_fetch(bar, baz, __ATOMIC_ACQ_REL); +-} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-5.c +deleted file mode 100644 +index 03b70111a74..00000000000 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-5.c ++++ /dev/null +@@ -1,17 +0,0 @@ +-/* { dg-do compile } */ +-/* Verify that atomic op mappings match Table A.6's recommended mapping. */ +-/* { dg-options "-O3" } */ +-/* { dg-add-options riscv_zaamo } */ +-/* { dg-remove-options riscv_ztso } */ +-/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +-/* { dg-final { check-function-bodies "**" "" } } */ +- +-/* +-** foo: +-** amoadd\.w\.aqrl\tzero,a1,0\(a0\) +-** ret +-*/ +-void foo (int* bar, int baz) +-{ +- __atomic_add_fetch(bar, baz, __ATOMIC_SEQ_CST); +-} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-1.c +deleted file mode 100644 +index 202479a005e..00000000000 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-1.c ++++ /dev/null +@@ -1,15 +0,0 @@ +-/* { dg-do compile } */ +-/* Verify that fence mappings match Table A.6's recommended mapping. */ +-/* { dg-options "-O3" } */ +-/* { dg-remove-options riscv_ztso } */ +-/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +-/* { dg-final { check-function-bodies "**" "" } } */ +- +-/* +-** foo: +-** ret +-*/ +-void foo() +-{ +- __atomic_thread_fence(__ATOMIC_RELAXED); +-} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-2.c +deleted file mode 100644 +index 7d6c73a6b50..00000000000 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-2.c ++++ /dev/null +@@ -1,16 +0,0 @@ +-/* { dg-do compile } */ +-/* Verify that fence mappings match Table A.6's recommended mapping. */ +-/* { dg-options "-O3" } */ +-/* { dg-remove-options riscv_ztso } */ +-/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +-/* { dg-final { check-function-bodies "**" "" } } */ +- +-/* +-** foo: +-** fence\tr,rw +-** ret +-*/ +-void foo() +-{ +- __atomic_thread_fence(__ATOMIC_ACQUIRE); +-} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-3.c +deleted file mode 100644 +index a53889a4fa1..00000000000 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-3.c ++++ /dev/null +@@ -1,16 +0,0 @@ +-/* { dg-do compile } */ +-/* Verify that fence mappings match Table A.6's recommended mapping. */ +-/* { dg-options "-O3" } */ +-/* { dg-remove-options riscv_ztso } */ +-/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +-/* { dg-final { check-function-bodies "**" "" } } */ +- +-/* +-** foo: +-** fence\trw,w +-** ret +-*/ +-void foo() +-{ +- __atomic_thread_fence(__ATOMIC_RELEASE); +-} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-4.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-4.c +deleted file mode 100644 +index 63a3a234d43..00000000000 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-4.c ++++ /dev/null +@@ -1,16 +0,0 @@ +-/* { dg-do compile } */ +-/* Verify that fence mappings match Table A.6's recommended mapping. */ +-/* { dg-options "-O3" } */ +-/* { dg-remove-options riscv_ztso } */ +-/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +-/* { dg-final { check-function-bodies "**" "" } } */ +- +-/* +-** foo: +-** fence\.tso +-** ret +-*/ +-void foo() +-{ +- __atomic_thread_fence(__ATOMIC_ACQ_REL); +-} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-5.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-5.c +deleted file mode 100644 +index 78040bd11e9..00000000000 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-5.c ++++ /dev/null +@@ -1,16 +0,0 @@ +-/* { dg-do compile } */ +-/* Verify that fence mappings match Table A.6's recommended mapping. */ +-/* { dg-options "-O3" } */ +-/* { dg-remove-options riscv_ztso } */ +-/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +-/* { dg-final { check-function-bodies "**" "" } } */ +- +-/* +-** foo: +-** fence\trw,rw +-** ret +-*/ +-void foo() +-{ +- __atomic_thread_fence(__ATOMIC_SEQ_CST); +-} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-1.c +deleted file mode 100644 +index 000407a2583..00000000000 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-1.c ++++ /dev/null +@@ -1,17 +0,0 @@ +-/* { dg-do compile } */ +-/* Verify that atomic op mappings match the Ztso suggested mapping. */ +-/* { dg-options "-O3" } */ +-/* { dg-add-options riscv_zaamo } */ +-/* { dg-add-options riscv_ztso } */ +-/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +-/* { dg-final { check-function-bodies "**" "" } } */ +- +-/* +-** foo: +-** amoadd\.w\tzero,a1,0\(a0\) +-** ret +-*/ +-void foo (int* bar, int baz) +-{ +- __atomic_add_fetch(bar, baz, __ATOMIC_RELAXED); +-} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-2.c +deleted file mode 100644 +index 3e441cadbf3..00000000000 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-2.c ++++ /dev/null +@@ -1,17 +0,0 @@ +-/* { dg-do compile } */ +-/* Verify that atomic op mappings the Ztso suggested mapping. */ +-/* { dg-options "-O3" } */ +-/* { dg-add-options riscv_zaamo } */ +-/* { dg-add-options riscv_ztso } */ +-/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +-/* { dg-final { check-function-bodies "**" "" } } */ +- +-/* +-** foo: +-** amoadd\.w\tzero,a1,0\(a0\) +-** ret +-*/ +-void foo (int* bar, int baz) +-{ +- __atomic_add_fetch(bar, baz, __ATOMIC_ACQUIRE); +-} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-3.c +deleted file mode 100644 +index 8af1a2f79a4..00000000000 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-3.c ++++ /dev/null +@@ -1,17 +0,0 @@ +-/* { dg-do compile } */ +-/* Verify that atomic op mappings match the Ztso suggested mapping. */ +-/* { dg-options "-O3" } */ +-/* { dg-add-options riscv_zaamo } */ +-/* { dg-add-options riscv_ztso } */ +-/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +-/* { dg-final { check-function-bodies "**" "" } } */ +- +-/* +-** foo: +-** amoadd\.w\tzero,a1,0\(a0\) +-** ret +-*/ +-void foo (int* bar, int baz) +-{ +- __atomic_add_fetch(bar, baz, __ATOMIC_RELEASE); +-} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-4.c +deleted file mode 100644 +index 0b3a7e59689..00000000000 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-4.c ++++ /dev/null +@@ -1,17 +0,0 @@ +-/* { dg-do compile } */ +-/* Verify that atomic op mappings match the Ztso suggested mapping. */ +-/* { dg-options "-O3" } */ +-/* { dg-add-options riscv_zaamo } */ +-/* { dg-add-options riscv_ztso } */ +-/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +-/* { dg-final { check-function-bodies "**" "" } } */ +- +-/* +-** foo: +-** amoadd\.w\tzero,a1,0\(a0\) +-** ret +-*/ +-void foo (int* bar, int baz) +-{ +- __atomic_add_fetch(bar, baz, __ATOMIC_ACQ_REL); +-} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-5.c +deleted file mode 100644 +index f189827d6cf..00000000000 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-5.c ++++ /dev/null +@@ -1,17 +0,0 @@ +-/* { dg-do compile } */ +-/* Verify that atomic op mappings match the Ztso suggested mapping. */ +-/* { dg-options "-O3" } */ +-/* { dg-add-options riscv_zaamo } */ +-/* { dg-add-options riscv_ztso } */ +-/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +-/* { dg-final { check-function-bodies "**" "" } } */ +- +-/* +-** foo: +-** amoadd\.w\tzero,a1,0\(a0\) +-** ret +-*/ +-void foo (int* bar, int baz) +-{ +- __atomic_add_fetch(bar, baz, __ATOMIC_SEQ_CST); +-} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-fence-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-fence-1.c +deleted file mode 100644 +index ec008d25794..00000000000 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-fence-1.c ++++ /dev/null +@@ -1,15 +0,0 @@ +-/* { dg-do compile } */ +-/* Verify that fence mappings match the Ztso suggested mapping. */ +-/* { dg-options "-O3" } */ +-/* { dg-add-options riscv_ztso } */ +-/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +-/* { dg-final { check-function-bodies "**" "" } } */ +- +-/* +-** foo: +-** ret +-*/ +-void foo() +-{ +- __atomic_thread_fence(__ATOMIC_RELAXED); +-} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-fence-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-fence-2.c +deleted file mode 100644 +index acef911573f..00000000000 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-fence-2.c ++++ /dev/null +@@ -1,15 +0,0 @@ +-/* { dg-do compile } */ +-/* Verify that fence mappings match the Ztso suggested mapping. */ +-/* { dg-options "-O3" } */ +-/* { dg-add-options riscv_ztso } */ +-/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +-/* { dg-final { check-function-bodies "**" "" } } */ +- +-/* +-** foo: +-** ret +-*/ +-void foo() +-{ +- __atomic_thread_fence(__ATOMIC_ACQUIRE); +-} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-fence-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-fence-3.c +deleted file mode 100644 +index 6931ba0a799..00000000000 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-fence-3.c ++++ /dev/null +@@ -1,15 +0,0 @@ +-/* { dg-do compile } */ +-/* Verify that fence mappings match the Ztso suggested mapping. */ +-/* { dg-options "-O3" } */ +-/* { dg-add-options riscv_ztso } */ +-/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +-/* { dg-final { check-function-bodies "**" "" } } */ +- +-/* +-** foo: +-** ret +-*/ +-void foo() +-{ +- __atomic_thread_fence(__ATOMIC_RELEASE); +-} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-fence-4.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-fence-4.c +deleted file mode 100644 +index b5a04294ad0..00000000000 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-fence-4.c ++++ /dev/null +@@ -1,15 +0,0 @@ +-/* { dg-do compile } */ +-/* Verify that fence mappings match the Ztso suggested mapping. */ +-/* { dg-options "-O3" } */ +-/* { dg-add-options riscv_ztso } */ +-/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +-/* { dg-final { check-function-bodies "**" "" } } */ +- +-/* +-** foo: +-** ret +-*/ +-void foo() +-{ +- __atomic_thread_fence(__ATOMIC_ACQ_REL); +-} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-fence-5.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-fence-5.c +deleted file mode 100644 +index 860fb978cbc..00000000000 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-fence-5.c ++++ /dev/null +@@ -1,16 +0,0 @@ +-/* { dg-do compile } */ +-/* Verify that fence mappings match the Ztso suggested mapping. */ +-/* { dg-options "-O3" } */ +-/* { dg-add-options riscv_ztso } */ +-/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +-/* { dg-final { check-function-bodies "**" "" } } */ +- +-/* +-** foo: +-** fence\trw,rw +-** ret +-*/ +-void foo() +-{ +- __atomic_thread_fence(__ATOMIC_SEQ_CST); +-} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-1.c +deleted file mode 100644 +index 582e96534de..00000000000 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-1.c ++++ /dev/null +@@ -1,22 +0,0 @@ +-/* { dg-do compile } */ +-/* Verify that lrsc atomic op mappings match Table A.6's recommended mapping. */ +-/* { dg-options "-O3" } */ +-/* { dg-add-options riscv_zalrsc } */ +-/* { dg-remove-options riscv_zaamo } */ +-/* { dg-remove-options riscv_ztso } */ +-/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +-/* { dg-final { check-function-bodies "**" "" } } */ +- +-/* +-** foo: +-** 1: +-** lr.w\t[atx][0-9]+, 0\(a0\) +-** add\t[atx][0-9]+, [atx][0-9]+, a1 +-** sc.w\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) +-** bnez\t[atx][0-9]+, 1b +-** ret +-*/ +-void foo (int* bar, int baz) +-{ +- __atomic_add_fetch(bar, baz, __ATOMIC_RELAXED); +-} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-2.c +deleted file mode 100644 +index 987429640de..00000000000 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-2.c ++++ /dev/null +@@ -1,22 +0,0 @@ +-/* { dg-do compile } */ +-/* Verify that lrsc atomic op mappings match Table A.6's recommended mapping. */ +-/* { dg-options "-O3" } */ +-/* { dg-add-options riscv_zalrsc } */ +-/* { dg-remove-options riscv_zaamo } */ +-/* { dg-remove-options riscv_ztso } */ +-/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +-/* { dg-final { check-function-bodies "**" "" } } */ +- +-/* +-** foo: +-** 1: +-** lr.w.aq\t[atx][0-9]+, 0\(a0\) +-** add\t[atx][0-9]+, [atx][0-9]+, a1 +-** sc.w\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) +-** bnez\t[atx][0-9]+, 1b +-** ret +-*/ +-void foo (int* bar, int baz) +-{ +- __atomic_add_fetch(bar, baz, __ATOMIC_ACQUIRE); +-} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-3.c +deleted file mode 100644 +index b29966ce7d7..00000000000 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-3.c ++++ /dev/null +@@ -1,22 +0,0 @@ +-/* { dg-do compile } */ +-/* Verify that lrsc atomic op mappings match Table A.6's recommended mapping. */ +-/* { dg-options "-O3" } */ +-/* { dg-add-options riscv_zalrsc } */ +-/* { dg-remove-options riscv_zaamo } */ +-/* { dg-remove-options riscv_ztso } */ +-/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +-/* { dg-final { check-function-bodies "**" "" } } */ +- +-/* +-** foo: +-** 1: +-** lr.w\t[atx][0-9]+, 0\(a0\) +-** add\t[atx][0-9]+, [atx][0-9]+, a1 +-** sc.w.rl\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) +-** bnez\t[atx][0-9]+, 1b +-** ret +-*/ +-void foo (int* bar, int baz) +-{ +- __atomic_add_fetch(bar, baz, __ATOMIC_RELEASE); +-} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-4.c +deleted file mode 100644 +index 5dfb7ac2bac..00000000000 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-4.c ++++ /dev/null +@@ -1,22 +0,0 @@ +-/* { dg-do compile } */ +-/* Verify that lrsc atomic op mappings match Table A.6's recommended mapping. */ +-/* { dg-options "-O3" } */ +-/* { dg-add-options riscv_zalrsc } */ +-/* { dg-remove-options riscv_zaamo } */ +-/* { dg-remove-options riscv_ztso } */ +-/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +-/* { dg-final { check-function-bodies "**" "" } } */ +- +-/* +-** foo: +-** 1: +-** lr.w.aq\t[atx][0-9]+, 0\(a0\) +-** add\t[atx][0-9]+, [atx][0-9]+, a1 +-** sc.w.rl\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) +-** bnez\t[atx][0-9]+, 1b +-** ret +-*/ +-void foo (int* bar, int baz) +-{ +- __atomic_add_fetch(bar, baz, __ATOMIC_ACQ_REL); +-} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-5.c +deleted file mode 100644 +index fcc64131fec..00000000000 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-5.c ++++ /dev/null +@@ -1,22 +0,0 @@ +-/* { dg-do compile } */ +-/* Verify that lrsc atomic op mappings match Table A.6's recommended mapping. */ +-/* { dg-options "-O3" } */ +-/* { dg-add-options riscv_zalrsc } */ +-/* { dg-remove-options riscv_zaamo } */ +-/* { dg-remove-options riscv_ztso } */ +-/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +-/* { dg-final { check-function-bodies "**" "" } } */ +- +-/* +-** foo: +-** 1: +-** lr.w.aqrl\t[atx][0-9]+, 0\(a0\) +-** add\t[atx][0-9]+, [atx][0-9]+, a1 +-** sc.w.rl\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) +-** bnez\t[atx][0-9]+, 1b +-** ret +-*/ +-void foo (int* bar, int baz) +-{ +- __atomic_add_fetch(bar, baz, __ATOMIC_SEQ_CST); +-} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zaamo-rvwmo-amo-add-int.c b/gcc/testsuite/gcc.target/riscv/amo/zaamo-rvwmo-amo-add-int.c +new file mode 100644 +index 00000000000..22187243314 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo/zaamo-rvwmo-amo-add-int.c +@@ -0,0 +1,57 @@ ++/* { dg-do compile } */ ++/* Verify that atomic op mappings match Table A.6's recommended mapping. */ ++/* { dg-options "-O3" } */ ++/* { dg-add-options riscv_zaamo } */ ++/* { dg-remove-options riscv_ztso } */ ++/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ ++/* { dg-final { check-function-bodies "**" "" } } */ ++ ++/* ++** atomic_add_fetch_int_relaxed: ++** amoadd\.w\tzero,a1,0\(a0\) ++** ret ++*/ ++void atomic_add_fetch_int_relaxed (int* bar, int baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_RELAXED); ++} ++ ++/* ++** atomic_add_fetch_int_acquire: ++** amoadd\.w\.aq\tzero,a1,0\(a0\) ++** ret ++*/ ++void atomic_add_fetch_int_acquire (int* bar, int baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_ACQUIRE); ++} ++ ++/* ++** atomic_add_fetch_int_release: ++** amoadd\.w\.rl\tzero,a1,0\(a0\) ++** ret ++*/ ++void atomic_add_fetch_int_release (int* bar, int baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_RELEASE); ++} ++ ++/* ++** atomic_add_fetch_int_acq_rel: ++** amoadd\.w\.aqrl\tzero,a1,0\(a0\) ++** ret ++*/ ++void atomic_add_fetch_int_acq_rel (int* bar, int baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_ACQ_REL); ++} ++ ++/* ++** atomic_add_fetch_int_seq_cst: ++** amoadd\.w\.aqrl\tzero,a1,0\(a0\) ++** ret ++*/ ++void atomic_add_fetch_int_seq_cst (int* bar, int baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_SEQ_CST); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zaamo-ztso-amo-add-int.c b/gcc/testsuite/gcc.target/riscv/amo/zaamo-ztso-amo-add-int.c +new file mode 100644 +index 00000000000..8cfd601f12a +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo/zaamo-ztso-amo-add-int.c +@@ -0,0 +1,57 @@ ++/* { dg-do compile } */ ++/* Verify that atomic op mappings match Table A.6's recommended mapping. */ ++/* { dg-options "-O3" } */ ++/* { dg-add-options riscv_zaamo } */ ++/* { dg-add-options riscv_ztso } */ ++/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ ++/* { dg-final { check-function-bodies "**" "" } } */ ++ ++/* ++** atomic_add_fetch_int_relaxed: ++** amoadd\.w\tzero,a1,0\(a0\) ++** ret ++*/ ++void atomic_add_fetch_int_relaxed (int* bar, int baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_RELAXED); ++} ++ ++/* ++** atomic_add_fetch_int_acquire: ++** amoadd\.w\tzero,a1,0\(a0\) ++** ret ++*/ ++void atomic_add_fetch_int_acquire (int* bar, int baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_ACQUIRE); ++} ++ ++/* ++** atomic_add_fetch_int_release: ++** amoadd\.w\tzero,a1,0\(a0\) ++** ret ++*/ ++void atomic_add_fetch_int_release (int* bar, int baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_RELEASE); ++} ++ ++/* ++** atomic_add_fetch_int_acq_rel: ++** amoadd\.w\tzero,a1,0\(a0\) ++** ret ++*/ ++void atomic_add_fetch_int_acq_rel (int* bar, int baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_ACQ_REL); ++} ++ ++/* ++** atomic_add_fetch_int_seq_cst: ++** amoadd\.w\tzero,a1,0\(a0\) ++** ret ++*/ ++void atomic_add_fetch_int_seq_cst (int* bar, int baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_SEQ_CST); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-amo-add-int.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-amo-add-int.c +new file mode 100644 +index 00000000000..4cf617d6035 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-amo-add-int.c +@@ -0,0 +1,78 @@ ++/* { dg-do compile } */ ++/* Verify that lrsc atomic op mappings match the PSABI doc's recommended mapping. */ ++/* { dg-options "-O3" } */ ++/* { dg-add-options riscv_zalrsc } */ ++/* { dg-remove-options riscv_zaamo } */ ++/* { dg-remove-options riscv_ztso } */ ++/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ ++/* { dg-final { check-function-bodies "**" "" } } */ ++ ++/* ++** atomic_add_fetch_int_relaxed: ++** 1: ++** lr.w\t[atx][0-9]+, 0\(a0\) ++** add\t[atx][0-9]+, [atx][0-9]+, a1 ++** sc.w\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) ++** bnez\t[atx][0-9]+, 1b ++** ret ++*/ ++void atomic_add_fetch_int_relaxed (int* bar, int baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_RELAXED); ++} ++ ++/* ++** atomic_add_fetch_int_acquire: ++** 1: ++** lr.w.aq\t[atx][0-9]+, 0\(a0\) ++** add\t[atx][0-9]+, [atx][0-9]+, a1 ++** sc.w\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) ++** bnez\t[atx][0-9]+, 1b ++** ret ++*/ ++void atomic_add_fetch_int_acquire (int* bar, int baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_ACQUIRE); ++} ++ ++/* ++** atomic_add_fetch_int_release: ++** 1: ++** lr.w\t[atx][0-9]+, 0\(a0\) ++** add\t[atx][0-9]+, [atx][0-9]+, a1 ++** sc.w.rl\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) ++** bnez\t[atx][0-9]+, 1b ++** ret ++*/ ++void atomic_add_fetch_int_release (int* bar, int baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_RELEASE); ++} ++ ++/* ++** atomic_add_fetch_int_acq_rel: ++** 1: ++** lr.w.aq\t[atx][0-9]+, 0\(a0\) ++** add\t[atx][0-9]+, [atx][0-9]+, a1 ++** sc.w.rl\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) ++** bnez\t[atx][0-9]+, 1b ++** ret ++*/ ++void atomic_add_fetch_int_acq_rel (int* bar, int baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_ACQ_REL); ++} ++ ++/* ++** atomic_add_fetch_int_seq_cst: ++** 1: ++** lr.w.aqrl\t[atx][0-9]+, 0\(a0\) ++** add\t[atx][0-9]+, [atx][0-9]+, a1 ++** sc.w.rl\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) ++** bnez\t[atx][0-9]+, 1b ++** ret ++*/ ++void atomic_add_fetch_int_seq_cst (int* bar, int baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_SEQ_CST); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-amo-add-int.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-amo-add-int.c +new file mode 100644 +index 00000000000..3fb16c01191 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-amo-add-int.c +@@ -0,0 +1,78 @@ ++/* { dg-do compile } */ ++/* Verify that lrsc atomic op mappings match the PSABI doc's recommended mapping. */ ++/* { dg-options "-O3" } */ ++/* { dg-add-options riscv_zalrsc } */ ++/* { dg-add-options riscv_ztso } */ ++/* { dg-remove-options riscv_zaamo } */ ++/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ ++/* { dg-final { check-function-bodies "**" "" } } */ ++ ++/* ++** atomic_add_fetch_int_relaxed: ++** 1: ++** lr.w\t[atx][0-9]+, 0\(a0\) ++** add\t[atx][0-9]+, [atx][0-9]+, a1 ++** sc.w\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) ++** bnez\t[atx][0-9]+, 1b ++** ret ++*/ ++void atomic_add_fetch_int_relaxed (int* bar, int baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_RELAXED); ++} ++ ++/* ++** atomic_add_fetch_int_acquire: ++** 1: ++** lr.w\t[atx][0-9]+, 0\(a0\) ++** add\t[atx][0-9]+, [atx][0-9]+, a1 ++** sc.w\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) ++** bnez\t[atx][0-9]+, 1b ++** ret ++*/ ++void atomic_add_fetch_int_acquire (int* bar, int baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_ACQUIRE); ++} ++ ++/* ++** atomic_add_fetch_int_release: ++** 1: ++** lr.w\t[atx][0-9]+, 0\(a0\) ++** add\t[atx][0-9]+, [atx][0-9]+, a1 ++** sc.w\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) ++** bnez\t[atx][0-9]+, 1b ++** ret ++*/ ++void atomic_add_fetch_int_release (int* bar, int baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_RELEASE); ++} ++ ++/* ++** atomic_add_fetch_int_acq_rel: ++** 1: ++** lr.w\t[atx][0-9]+, 0\(a0\) ++** add\t[atx][0-9]+, [atx][0-9]+, a1 ++** sc.w\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) ++** bnez\t[atx][0-9]+, 1b ++** ret ++*/ ++void atomic_add_fetch_int_acq_rel (int* bar, int baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_ACQ_REL); ++} ++ ++/* ++** atomic_add_fetch_int_seq_cst: ++** 1: ++** lr.w.aqrl\t[atx][0-9]+, 0\(a0\) ++** add\t[atx][0-9]+, [atx][0-9]+, a1 ++** sc.w.rl\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) ++** bnez\t[atx][0-9]+, 1b ++** ret ++*/ ++void atomic_add_fetch_int_seq_cst (int* bar, int baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_SEQ_CST); ++} +-- +2.47.3 + diff --git a/1051-RISC-V-Update-testcase-comments-to-point-to-PSABI-ra.patch b/1051-RISC-V-Update-testcase-comments-to-point-to-PSABI-ra.patch new file mode 100644 index 0000000..1603deb --- /dev/null +++ b/1051-RISC-V-Update-testcase-comments-to-point-to-PSABI-ra.patch @@ -0,0 +1,548 @@ +From c276cc18e0aa77c2a77c8e5a849433d37ce1332e Mon Sep 17 00:00:00 2001 +From: Patrick O'Neill +Date: Tue, 25 Jun 2024 14:14:18 -0700 +Subject: [PATCH 1051/1087] RISC-V: Update testcase comments to point to PSABI + rather than Table A.6 + +commit 86a3dbeb6c6a36f8cf97c66cef83c9bc3ad82027 upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +Table A.6 was originally the source of truth for the recommended mappings. +Point to the PSABI doc since the memory model mappings have been moved there. + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/amo/a-rvwmo-fence.c: Replace A.6 reference with PSABI. + * gcc.target/riscv/amo/a-rvwmo-load-acquire.c: Ditto. + * gcc.target/riscv/amo/a-rvwmo-load-relaxed.c: Ditto. + * gcc.target/riscv/amo/a-rvwmo-load-seq-cst.c: Ditto. + * gcc.target/riscv/amo/a-rvwmo-store-compat-seq-cst.c: Ditto. + * gcc.target/riscv/amo/a-rvwmo-store-relaxed.c: Ditto. + * gcc.target/riscv/amo/a-rvwmo-store-release.c: Ditto. + * gcc.target/riscv/amo/a-ztso-fence.c: Ditto. + * gcc.target/riscv/amo/a-ztso-load-acquire.c: Ditto. + * gcc.target/riscv/amo/a-ztso-load-relaxed.c: Ditto. + * gcc.target/riscv/amo/a-ztso-load-seq-cst.c: Ditto. + * gcc.target/riscv/amo/a-ztso-store-compat-seq-cst.c: Ditto. + * gcc.target/riscv/amo/a-ztso-store-relaxed.c: Ditto. + * gcc.target/riscv/amo/a-ztso-store-release.c: Ditto. + * gcc.target/riscv/amo/zaamo-rvwmo-amo-add-int.c: Ditto. + * gcc.target/riscv/amo/zaamo-ztso-amo-add-int.c: Ditto. + * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire-release.c: Ditto. + * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire.c: Ditto. + * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-consume.c: Ditto. + * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-relaxed.c: Ditto. + * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-release.c: Ditto. + * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst-relaxed.c: Ditto. + * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst.c: Ditto. + * gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acq-rel.c: Ditto. + * gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acquire.c: Ditto. + * gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-relaxed.c: Ditto. + * gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-release.c: Ditto. + * gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-seq-cst.c: Ditto. + * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire-release.c: Ditto. + * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire.c: Ditto. + * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-consume.c: Ditto. + * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-relaxed.c: Ditto. + * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-release.c: Ditto. + * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst-relaxed.c: Ditto. + * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst.c: Ditto. + * gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acq-rel.c: Ditto. + * gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acquire.c: Ditto. + * gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-relaxed.c: Ditto. + * gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-release.c: Ditto. + * gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-seq-cst.c: Ditto. + +Signed-off-by: Patrick O'Neill +--- + gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-fence.c | 2 +- + gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-acquire.c | 2 +- + gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-relaxed.c | 2 +- + gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-seq-cst.c | 2 +- + .../gcc.target/riscv/amo/a-rvwmo-store-compat-seq-cst.c | 3 ++- + gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-relaxed.c | 2 +- + gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-release.c | 2 +- + gcc/testsuite/gcc.target/riscv/amo/a-ztso-fence.c | 2 +- + gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-acquire.c | 2 +- + gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-relaxed.c | 2 +- + gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-seq-cst.c | 2 +- + .../gcc.target/riscv/amo/a-ztso-store-compat-seq-cst.c | 3 ++- + gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-relaxed.c | 2 +- + gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-release.c | 2 +- + gcc/testsuite/gcc.target/riscv/amo/zaamo-rvwmo-amo-add-int.c | 2 +- + gcc/testsuite/gcc.target/riscv/amo/zaamo-ztso-amo-add-int.c | 2 +- + .../amo/zalrsc-rvwmo-compare-exchange-int-acquire-release.c | 2 +- + .../riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire.c | 2 +- + .../riscv/amo/zalrsc-rvwmo-compare-exchange-int-consume.c | 2 +- + .../riscv/amo/zalrsc-rvwmo-compare-exchange-int-relaxed.c | 2 +- + .../riscv/amo/zalrsc-rvwmo-compare-exchange-int-release.c | 2 +- + .../amo/zalrsc-rvwmo-compare-exchange-int-seq-cst-relaxed.c | 3 ++- + .../riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst.c | 2 +- + .../riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acq-rel.c | 2 +- + .../riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acquire.c | 2 +- + .../riscv/amo/zalrsc-rvwmo-subword-amo-add-char-relaxed.c | 2 +- + .../riscv/amo/zalrsc-rvwmo-subword-amo-add-char-release.c | 2 +- + .../riscv/amo/zalrsc-rvwmo-subword-amo-add-char-seq-cst.c | 2 +- + .../amo/zalrsc-ztso-compare-exchange-int-acquire-release.c | 3 ++- + .../riscv/amo/zalrsc-ztso-compare-exchange-int-acquire.c | 2 +- + .../riscv/amo/zalrsc-ztso-compare-exchange-int-consume.c | 2 +- + .../riscv/amo/zalrsc-ztso-compare-exchange-int-relaxed.c | 2 +- + .../riscv/amo/zalrsc-ztso-compare-exchange-int-release.c | 2 +- + .../amo/zalrsc-ztso-compare-exchange-int-seq-cst-relaxed.c | 3 ++- + .../riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst.c | 2 +- + .../riscv/amo/zalrsc-ztso-subword-amo-add-char-acq-rel.c | 2 +- + .../riscv/amo/zalrsc-ztso-subword-amo-add-char-acquire.c | 2 +- + .../riscv/amo/zalrsc-ztso-subword-amo-add-char-relaxed.c | 2 +- + .../riscv/amo/zalrsc-ztso-subword-amo-add-char-release.c | 2 +- + .../riscv/amo/zalrsc-ztso-subword-amo-add-char-seq-cst.c | 2 +- + 40 files changed, 45 insertions(+), 40 deletions(-) + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-fence.c b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-fence.c +index 5b9400f7da8..6803bf92aa3 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-fence.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-fence.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* Verify that fence mappings match Table A.6's recommended mapping. */ ++/* Verify that fence mappings match the PSABI doc's recommended mapping. */ + /* { dg-options "-O3" } */ + /* { dg-remove-options riscv_ztso } */ + /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-acquire.c b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-acquire.c +index f9871b92c0b..93a0c68ae8a 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-acquire.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-acquire.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* Verify that load mappings match Table A.6's recommended mapping. */ ++/* Verify that load mappings match the PSABI doc's recommended mapping. */ + /* { dg-options "-O3" } */ + /* { dg-remove-options riscv_ztso } */ + /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-relaxed.c b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-relaxed.c +index 7b99db06d75..2403d53c131 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-relaxed.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-relaxed.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* Verify that load mappings match Table A.6's recommended mapping. */ ++/* Verify that load mappings match the PSABI doc's recommended mapping. */ + /* { dg-options "-O3" } */ + /* { dg-remove-options riscv_ztso } */ + /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-seq-cst.c b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-seq-cst.c +index 35f196c23c0..31b35cf9f6a 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-seq-cst.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-seq-cst.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* Verify that load mappings match Table A.6's recommended mapping. */ ++/* Verify that load mappings match the PSABI doc's recommended mapping. */ + /* { dg-options "-O3" } */ + /* { dg-remove-options riscv_ztso } */ + /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-compat-seq-cst.c b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-compat-seq-cst.c +index 43880b9734a..45c9abb1425 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-compat-seq-cst.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-compat-seq-cst.c +@@ -1,5 +1,6 @@ + /* { dg-do compile } */ +-/* Verify that store mapping are compatible with Table A.6 & A.7. */ ++/* Verify that store mappings match the PSABI doc's recommended compatibility ++ mapping. */ + /* { dg-options "-O3" } */ + /* { dg-remove-options riscv_ztso } */ + /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-relaxed.c b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-relaxed.c +index eb67d1968e0..4b321b2b75f 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-relaxed.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-relaxed.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* Verify that store mappings match Table A.6's recommended mapping. */ ++/* Verify that store mappings match the PSABI doc's recommended mapping. */ + /* { dg-options "-O3" } */ + /* { dg-remove-options riscv_ztso } */ + /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-release.c b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-release.c +index 25a998b86eb..a2a617c4d15 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-release.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-release.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* Verify that store mappings match Table A.6's recommended mapping. */ ++/* Verify that store mappings match the PSABI doc's recommended mapping. */ + /* { dg-options "-O3" } */ + /* { dg-remove-options riscv_ztso } */ + /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-fence.c b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-fence.c +index 37daeda8354..153f6ef8a3d 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-fence.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-fence.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* Verify that fence mappings match the Ztso suggested mapping. */ ++/* Verify that fence mappings match the PSABI doc's recommended mapping. */ + /* { dg-options "-O3" } */ + /* { dg-add-options riscv_ztso } */ + /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-acquire.c b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-acquire.c +index 4e94191812b..76a12059f39 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-acquire.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-acquire.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* Verify that load mappings match the Ztso suggested mapping. */ ++/* Verify that load mappings match the PSABI doc's recommended mapping. */ + /* { dg-options "-O3" } */ + /* { dg-add-options riscv_ztso } */ + /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-relaxed.c b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-relaxed.c +index ef5dee6ee60..c4ee56e2cc0 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-relaxed.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-relaxed.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* Verify that load mappings match the Ztso suggested mapping. */ ++/* Verify that load mappings match the PSABI doc's recommended mapping. */ + /* { dg-options "-O3" } */ + /* { dg-add-options riscv_ztso } */ + /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-seq-cst.c b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-seq-cst.c +index 93cd8bb909c..7163311433c 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-seq-cst.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-seq-cst.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* Verify that load mappings match the Ztso suggested mapping. */ ++/* Verify that load mappings match the PSABI doc's recommended mapping. */ + /* { dg-options "-O3" } */ + /* { dg-add-options riscv_ztso } */ + /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-compat-seq-cst.c b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-compat-seq-cst.c +index e32cfb1a3cb..2f4c9124aaf 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-compat-seq-cst.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-compat-seq-cst.c +@@ -1,5 +1,6 @@ + /* { dg-do compile } */ +-/* Verify that store mappings match the Ztso suggested mapping. */ ++/* Verify that store mappings match the PSABI doc's recommended compatibility ++ mapping. */ + /* { dg-options "-O3" } */ + /* { dg-add-options riscv_ztso } */ + /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-relaxed.c b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-relaxed.c +index 2f46470ae15..d469bf348d9 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-relaxed.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-relaxed.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* Verify that store mappings match the Ztso suggested mapping. */ ++/* Verify that store mappings match the PSABI doc's recommended mapping. */ + /* { dg-options "-O3" } */ + /* { dg-add-options riscv_ztso } */ + /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-release.c b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-release.c +index dd2db3a7878..3a275740401 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-release.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-release.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* Verify that store mappings match the Ztso suggested mapping. */ ++/* Verify that store mappings match the PSABI doc's recommended mapping. */ + /* { dg-options "-O3" } */ + /* { dg-add-options riscv_ztso } */ + /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zaamo-rvwmo-amo-add-int.c b/gcc/testsuite/gcc.target/riscv/amo/zaamo-rvwmo-amo-add-int.c +index 22187243314..ca40a49f9b5 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/zaamo-rvwmo-amo-add-int.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/zaamo-rvwmo-amo-add-int.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* Verify that atomic op mappings match Table A.6's recommended mapping. */ ++/* Verify that atomic op mappings match the PSABI doc's recommended mapping. */ + /* { dg-options "-O3" } */ + /* { dg-add-options riscv_zaamo } */ + /* { dg-remove-options riscv_ztso } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zaamo-ztso-amo-add-int.c b/gcc/testsuite/gcc.target/riscv/amo/zaamo-ztso-amo-add-int.c +index 8cfd601f12a..8ebdc61992e 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/zaamo-ztso-amo-add-int.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/zaamo-ztso-amo-add-int.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* Verify that atomic op mappings match Table A.6's recommended mapping. */ ++/* Verify that atomic op mappings match the PSABI doc's recommended mapping. */ + /* { dg-options "-O3" } */ + /* { dg-add-options riscv_zaamo } */ + /* { dg-add-options riscv_ztso } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire-release.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire-release.c +index 0cbc89c617c..49eeda9cb33 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire-release.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire-release.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* Verify that compare exchange mappings match Table A.6's recommended mapping. */ ++/* Verify that compare exchange mappings match the PSABI doc's recommended mapping. */ + /* { dg-add-options riscv_zalrsc } */ + /* { dg-remove-options riscv_ztso } */ + /* Mixed mappings need to be unioned. */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire.c +index 70107c40a53..b9e3adece8d 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* Verify that compare exchange mappings match Table A.6's recommended mapping. */ ++/* Verify that compare exchange mappings match the PSABI doc's recommended mapping. */ + /* { dg-add-options riscv_zalrsc } */ + /* { dg-remove-options riscv_ztso } */ + /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-consume.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-consume.c +index b3cffad005d..11839d84f14 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-consume.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-consume.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* Verify that compare exchange mappings match Table A.6's recommended mapping. */ ++/* Verify that compare exchange mappings match the PSABI doc's recommended mapping. */ + /* { dg-add-options riscv_zalrsc } */ + /* { dg-remove-options riscv_ztso } */ + /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-relaxed.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-relaxed.c +index fd8a8bfe9c6..852ec99df76 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-relaxed.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-relaxed.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* Verify that compare exchange mappings match Table A.6's recommended mapping. */ ++/* Verify that compare exchange mappings match the PSABI doc's recommended mapping. */ + /* { dg-add-options riscv_zalrsc } */ + /* { dg-remove-options riscv_ztso } */ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-release.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-release.c +index faab1ab728c..9c51a082d0b 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-release.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-release.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* Verify that compare exchange mappings match Table A.6's recommended mapping. */ ++/* Verify that compare exchange mappings match the PSABI doc's recommended mapping. */ + /* { dg-add-options riscv_zalrsc } */ + /* { dg-remove-options riscv_ztso } */ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst-relaxed.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst-relaxed.c +index 957aa3c0afd..d985e2cef8b 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst-relaxed.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst-relaxed.c +@@ -1,5 +1,6 @@ + /* { dg-do compile } */ +-/* Verify that compare exchange mappings match Table A.6's recommended mapping. */ ++/* Verify that compare exchange mappings match the PSABI doc's recommended mapping. */ ++/* Mixed mappings need to be unioned. */ + /* { dg-add-options riscv_zalrsc } */ + /* { dg-remove-options riscv_ztso } */ + /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst.c +index a1435a07a21..6efd232ce21 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* Verify that compare exchange mappings match Table A.6's recommended mapping. */ ++/* Verify that compare exchange mappings match the PSABI doc's recommended mapping. */ + /* { dg-add-options riscv_zalrsc } */ + /* { dg-remove-options riscv_ztso } */ + /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acq-rel.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acq-rel.c +index 3f5fa20c87c..2c2df133a28 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acq-rel.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acq-rel.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* Verify that subword atomic op mappings match Table A.6's recommended mapping. */ ++/* Verify that subword atomic op mappings match the PSABI doc's recommended mapping. */ + /* { dg-add-options riscv_zalrsc } */ + /* { dg-remove-options riscv_ztso } */ + /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acquire.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acquire.c +index 782ffcb0a70..abfbf63902c 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acquire.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acquire.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* Verify that subword atomic op mappings match Table A.6's recommended mapping. */ ++/* Verify that subword atomic op mappings match the PSABI doc's recommended mapping. */ + /* { dg-add-options riscv_zalrsc } */ + /* { dg-remove-options riscv_ztso } */ + /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-relaxed.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-relaxed.c +index 50009f021dc..1f61c89da88 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-relaxed.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-relaxed.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* Verify that subword atomic op mappings match Table A.6's recommended mapping. */ ++/* Verify that subword atomic op mappings match the PSABI doc's recommended mapping. */ + /* { dg-add-options riscv_zalrsc } */ + /* { dg-remove-options riscv_ztso } */ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-release.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-release.c +index 76ec8a81d1f..343503ce79c 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-release.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-release.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* Verify that subword atomic op mappings match Table A.6's recommended mapping. */ ++/* Verify that subword atomic op mappings match the PSABI doc's recommended mapping. */ + /* { dg-add-options riscv_zalrsc } */ + /* { dg-remove-options riscv_ztso } */ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-seq-cst.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-seq-cst.c +index 7417a67f692..045434b2579 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-seq-cst.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-seq-cst.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* Verify that subword atomic op mappings match Table A.6's recommended mapping. */ ++/* Verify that subword atomic op mappings match the PSABI doc's recommended mapping. */ + /* { dg-add-options riscv_zalrsc } */ + /* { dg-remove-options riscv_ztso } */ + /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire-release.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire-release.c +index 7da3b1dce48..9761a955ede 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire-release.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire-release.c +@@ -1,5 +1,6 @@ + /* { dg-do compile } */ +-/* Verify that compare exchange mappings match the Ztso suggested mapping. */ ++/* Verify that compare exchange mappings match the PSABI doc's recommended mapping. */ ++/* Mixed mappings need to be unioned. */ + /* { dg-add-options riscv_zalrsc } */ + /* { dg-add-options riscv_ztso } */ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire.c +index 0a443b461f3..3303f8021e1 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* Verify that compare exchange mappings match the Ztso suggested mapping. */ ++/* Verify that compare exchange mappings match the PSABI doc's recommended mapping. */ + /* { dg-add-options riscv_zalrsc } */ + /* { dg-add-options riscv_ztso } */ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-consume.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-consume.c +index 20e325f2e7c..7474e832bb1 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-consume.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-consume.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* Verify that compare exchange mappings match the Ztso suggested mapping. */ ++/* Verify that compare exchange mappings match the PSABI doc's recommended mapping. */ + /* { dg-add-options riscv_zalrsc } */ + /* { dg-add-options riscv_ztso } */ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-relaxed.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-relaxed.c +index 46a9f0c918a..e43193820f2 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-relaxed.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-relaxed.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* Verify that compare exchange mappings match the Ztso suggested mapping. */ ++/* Verify that compare exchange mappings match the PSABI doc's recommended mapping. */ + /* { dg-add-options riscv_zalrsc } */ + /* { dg-add-options riscv_ztso } */ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-release.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-release.c +index 35e01cdc8be..a0d5872e1bd 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-release.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-release.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* Verify that compare exchange mappings match the Ztso suggested mapping. */ ++/* Verify that compare exchange mappings match the PSABI doc's recommended mapping. */ + /* { dg-add-options riscv_zalrsc } */ + /* { dg-add-options riscv_ztso } */ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst-relaxed.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst-relaxed.c +index 53f6e6ace0b..fc464ab1ff5 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst-relaxed.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst-relaxed.c +@@ -1,5 +1,6 @@ + /* { dg-do compile } */ +-/* Verify that compare exchange mappings match the Ztso suggested mapping. */ ++/* Verify that compare exchange mappings match the PSABI doc's recommended mapping. */ ++/* Mixed mappings need to be unioned. */ + /* { dg-add-options riscv_zalrsc } */ + /* { dg-add-options riscv_ztso } */ + /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst.c +index cd884931bdf..152806cfde3 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* Verify that compare exchange mappings match the Ztso suggested mapping. */ ++/* Verify that compare exchange mappings match the PSABI doc's recommended mapping. */ + /* { dg-add-options riscv_zalrsc } */ + /* { dg-add-options riscv_ztso } */ + /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acq-rel.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acq-rel.c +index a88e409063a..f64b10a076a 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acq-rel.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acq-rel.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* Verify that subword atomic op mappings match the Ztso suggested mapping. */ ++/* Verify that subword atomic op mappings match the PSABI doc's suggested mapping. */ + /* { dg-add-options riscv_zalrsc } */ + /* { dg-add-options riscv_ztso } */ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acquire.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acquire.c +index 8d28569c79c..5d743f0ab83 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acquire.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acquire.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* Verify that subword atomic op mappings match the Ztso suggested mapping. */ ++/* Verify that subword atomic op mappings match the PSABI doc's suggested mapping. */ + /* { dg-add-options riscv_zalrsc } */ + /* { dg-add-options riscv_ztso } */ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-relaxed.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-relaxed.c +index a44d6980ece..3e7dda9c8c4 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-relaxed.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-relaxed.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* Verify that subword atomic op mappings match the Ztso suggested mapping. */ ++/* Verify that subword atomic op mappings match the PSABI doc's suggested mapping. */ + /* { dg-add-options riscv_zalrsc } */ + /* { dg-add-options riscv_ztso } */ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-release.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-release.c +index fb803ab9cbf..ffd832eef78 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-release.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-release.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* Verify that subword atomic op mappings match the Ztso suggested mapping. */ ++/* Verify that subword atomic op mappings match the PSABI doc's suggested mapping. */ + /* { dg-add-options riscv_zalrsc } */ + /* { dg-add-options riscv_ztso } */ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-seq-cst.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-seq-cst.c +index d851e5e5944..e9ea3f5ff3b 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-seq-cst.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-seq-cst.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* Verify that subword atomic op mappings match the Ztso suggested mapping. */ ++/* Verify that subword atomic op mappings match the PSABI doc's suggested mapping. */ + /* { dg-add-options riscv_zalrsc } */ + /* { dg-add-options riscv_ztso } */ + /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */ +-- +2.47.3 + diff --git a/1052-RISC-V-Add-support-for-Zabha-extension.patch b/1052-RISC-V-Add-support-for-Zabha-extension.patch new file mode 100644 index 0000000..a917d41 --- /dev/null +++ b/1052-RISC-V-Add-support-for-Zabha-extension.patch @@ -0,0 +1,1001 @@ +From e6b390f9101d541e28a6a593873f713553348b0e Mon Sep 17 00:00:00 2001 +From: Gianluca Guida +Date: Tue, 2 Jul 2024 18:05:14 -0700 +Subject: [PATCH 1052/1087] RISC-V: Add support for Zabha extension + +commit 7b2b2e3d660edc8ef3a8cfbdfc2b0fd499459601 upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +The Zabha extension adds support for subword Zaamo ops. + +Extension: https://github.com/riscv/riscv-zabha.git +Ratification: https://jira.riscv.org/browse/RVS-1685 + +gcc/ChangeLog: + + * common/config/riscv/riscv-common.cc + (riscv_subset_list::to_string): Skip zabha when not supported by + the assembler. + * config.in: Regenerate. + * config/riscv/arch-canonicalize: Make zabha imply zaamo. + * config/riscv/iterators.md (amobh): Add iterator for amo + byte/halfword. + * config/riscv/riscv.opt: Add zabha. + * config/riscv/sync.md (atomic_): Add + subword atomic op pattern. + (zabha_atomic_fetch_): Add subword + atomic_fetch op pattern. + (lrsc_atomic_fetch_): Prefer zabha over lrsc + for subword atomic ops. + (zabha_atomic_exchange): Add subword atomic exchange + pattern. + (lrsc_atomic_exchange): Prefer zabha over lrsc for subword + atomic exchange ops. + * configure: Regenerate. + * configure.ac: Add zabha assembler check. + * doc/sourcebuild.texi: Add zabha documentation. + +gcc/testsuite/ChangeLog: + + * lib/target-supports.exp: Add zabha testsuite infra support. + * gcc.target/riscv/amo/inline-atomics-1.c: Remove zabha to continue to + test the lr/sc subword patterns. + * gcc.target/riscv/amo/inline-atomics-2.c: Ditto. + * gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acq-rel.c: Ditto. + * gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acquire.c: Ditto. + * gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-relaxed.c: Ditto. + * gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-release.c: Ditto. + * gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-seq-cst.c: Ditto. + * gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acq-rel.c: Ditto. + * gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acquire.c: Ditto. + * gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-relaxed.c: Ditto. + * gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-release.c: Ditto. + * gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-seq-cst.c: Ditto. + * gcc.target/riscv/amo/zabha-all-amo-ops-char-run.c: New test. + * gcc.target/riscv/amo/zabha-all-amo-ops-short-run.c: New test. + * gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-char.c: New test. + * gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-short.c: New test. + * gcc.target/riscv/amo/zabha-rvwmo-amo-add-char.c: New test. + * gcc.target/riscv/amo/zabha-rvwmo-amo-add-short.c: New test. + * gcc.target/riscv/amo/zabha-ztso-amo-add-char.c: New test. + * gcc.target/riscv/amo/zabha-ztso-amo-add-short.c: New test. + +Co-Authored-By: Patrick O'Neill +Signed-Off-By: Gianluca Guida +Tested-by: Andrea Parri +--- + gcc/common/config/riscv/riscv-common.cc | 12 +++ + gcc/config.in | 6 ++ + gcc/config/riscv/arch-canonicalize | 3 + + gcc/config/riscv/iterators.md | 3 + + gcc/config/riscv/riscv.opt | 2 + + gcc/config/riscv/sync.md | 81 ++++++++++++++++++- + gcc/configure | 31 +++++++ + gcc/configure.ac | 5 ++ + gcc/doc/sourcebuild.texi | 12 ++- + .../gcc.target/riscv/amo/inline-atomics-1.c | 1 + + .../gcc.target/riscv/amo/inline-atomics-2.c | 1 + + .../riscv/amo/zabha-all-amo-ops-char-run.c | 5 ++ + .../riscv/amo/zabha-all-amo-ops-short-run.c | 5 ++ + .../riscv/amo/zabha-rvwmo-all-amo-ops-char.c | 23 ++++++ + .../riscv/amo/zabha-rvwmo-all-amo-ops-short.c | 23 ++++++ + .../riscv/amo/zabha-rvwmo-amo-add-char.c | 57 +++++++++++++ + .../riscv/amo/zabha-rvwmo-amo-add-short.c | 57 +++++++++++++ + .../riscv/amo/zabha-ztso-amo-add-char.c | 57 +++++++++++++ + .../riscv/amo/zabha-ztso-amo-add-short.c | 57 +++++++++++++ + ...alrsc-rvwmo-subword-amo-add-char-acq-rel.c | 1 + + ...alrsc-rvwmo-subword-amo-add-char-acquire.c | 1 + + ...alrsc-rvwmo-subword-amo-add-char-relaxed.c | 1 + + ...alrsc-rvwmo-subword-amo-add-char-release.c | 1 + + ...alrsc-rvwmo-subword-amo-add-char-seq-cst.c | 1 + + ...zalrsc-ztso-subword-amo-add-char-acq-rel.c | 1 + + ...zalrsc-ztso-subword-amo-add-char-acquire.c | 1 + + ...zalrsc-ztso-subword-amo-add-char-relaxed.c | 1 + + ...zalrsc-ztso-subword-amo-add-char-release.c | 1 + + ...zalrsc-ztso-subword-amo-add-char-seq-cst.c | 1 + + gcc/testsuite/lib/target-supports.exp | 33 ++++++-- + 30 files changed, 476 insertions(+), 8 deletions(-) + create mode 100644 gcc/testsuite/gcc.target/riscv/amo/zabha-all-amo-ops-char-run.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo/zabha-all-amo-ops-short-run.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-char.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-short.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-amo-add-char.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-amo-add-short.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo/zabha-ztso-amo-add-char.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo/zabha-ztso-amo-add-short.c + +diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc +index f0a25966316..854fa8b5905 100644 +--- a/gcc/common/config/riscv/riscv-common.cc ++++ b/gcc/common/config/riscv/riscv-common.cc +@@ -82,6 +82,8 @@ static const riscv_implied_info_t riscv_implied_info[] = + {"a", "zaamo"}, + {"a", "zalrsc"}, + ++ {"zabha", "zaamo"}, ++ + {"zdinx", "zfinx"}, + {"zfinx", "zicsr"}, + {"zdinx", "zicsr"}, +@@ -262,6 +264,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] = + {"zawrs", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zaamo", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zalrsc", ISA_SPEC_CLASS_NONE, 1, 0}, ++ {"zabha", ISA_SPEC_CLASS_NONE, 1, 0}, + + {"zba", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zbb", ISA_SPEC_CLASS_NONE, 1, 0}, +@@ -833,6 +836,7 @@ riscv_subset_list::to_string (bool version_p) const + + bool skip_zifencei = false; + bool skip_zaamo_zalrsc = false; ++ bool skip_zabha = false; + bool skip_zicsr = false; + bool i2p0 = false; + +@@ -864,6 +868,10 @@ riscv_subset_list::to_string (bool version_p) const + /* Skip since binutils 2.42 and earlier don't recognize zaamo/zalrsc. */ + skip_zaamo_zalrsc = true; + #endif ++#ifndef HAVE_AS_MARCH_ZABHA ++ /* Skip since binutils 2.42 and earlier don't recognize zabha. */ ++ skip_zabha = true; ++#endif + + for (subset = m_head; subset != NULL; subset = subset->next) + { +@@ -881,6 +889,9 @@ riscv_subset_list::to_string (bool version_p) const + if (skip_zaamo_zalrsc && subset->name == "zalrsc") + continue; + ++ if (skip_zabha && subset->name == "zabha") ++ continue; ++ + /* For !version_p, we only separate extension with underline for + multi-letter extension. */ + if (!first && +@@ -1559,6 +1570,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = + {"zawrs", &gcc_options::x_riscv_za_subext, MASK_ZAWRS}, + {"zaamo", &gcc_options::x_riscv_za_subext, MASK_ZAAMO}, + {"zalrsc", &gcc_options::x_riscv_za_subext, MASK_ZALRSC}, ++ {"zabha", &gcc_options::x_riscv_za_subext, MASK_ZABHA}, + + {"zba", &gcc_options::x_riscv_zb_subext, MASK_ZBA}, + {"zbb", &gcc_options::x_riscv_zb_subext, MASK_ZBB}, +diff --git a/gcc/config.in b/gcc/config.in +index 21a7e12376b..557783b5a22 100644 +--- a/gcc/config.in ++++ b/gcc/config.in +@@ -635,6 +635,12 @@ + #endif + + ++/* Define if the assembler understands -march=rv*_zabha. */ ++#ifndef USED_FOR_TARGET ++#undef HAVE_AS_MARCH_ZABHA ++#endif ++ ++ + /* Define if the assembler understands -march=rv*_zifencei. */ + #ifndef USED_FOR_TARGET + #undef HAVE_AS_MARCH_ZIFENCEI +diff --git a/gcc/config/riscv/arch-canonicalize b/gcc/config/riscv/arch-canonicalize +index 6c10d1aa81b..35a7fe4455a 100755 +--- a/gcc/config/riscv/arch-canonicalize ++++ b/gcc/config/riscv/arch-canonicalize +@@ -40,7 +40,10 @@ LONG_EXT_PREFIXES = ['z', 's', 'h', 'x'] + # + IMPLIED_EXT = { + "d" : ["f", "zicsr"], ++ + "a" : ["zaamo", "zalrsc"], ++ "zabha" : ["zaamo"], ++ + "f" : ["zicsr"], + "zdinx" : ["zfinx", "zicsr"], + "zfinx" : ["zicsr"], +diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md +index 72d19c55efb..eb8fe14b58e 100644 +--- a/gcc/config/riscv/iterators.md ++++ b/gcc/config/riscv/iterators.md +@@ -122,6 +122,9 @@ + ;; This attribute gives the format suffix for atomic memory operations. + (define_mode_attr amo [(SI "w") (DI "d")]) + ++;; This attribute gives the format suffix for byte and halfword atomic memory operations. ++(define_mode_attr amobh [(QI "b") (HI "h")]) ++ + ;; This attribute gives the upper-case mode name for one unit of a + ;; floating-point mode. + (define_mode_attr UNITMODE [(HF "HF") (SF "SF") (DF "DF")]) +diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt +index 29522940172..8a655e9ab63 100644 +--- a/gcc/config/riscv/riscv.opt ++++ b/gcc/config/riscv/riscv.opt +@@ -262,6 +262,8 @@ Mask(ZAAMO) Var(riscv_za_subext) + + Mask(ZALRSC) Var(riscv_za_subext) + ++Mask(ZABHA) Var(riscv_za_subext) ++ + Mask(ZA64RS) Var(riscv_za_subext) + + Mask(ZA128RS) Var(riscv_za_subext) +diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md +index 0c97ae85975..6128b0ebc4e 100644 +--- a/gcc/config/riscv/sync.md ++++ b/gcc/config/riscv/sync.md +@@ -24,8 +24,10 @@ + UNSPEC_COMPARE_AND_SWAP_SUBWORD + UNSPEC_SYNC_OLD_OP + UNSPEC_SYNC_OLD_OP_SUBWORD ++ UNSPEC_SYNC_OLD_OP_ZABHA + UNSPEC_SYNC_EXCHANGE + UNSPEC_SYNC_EXCHANGE_SUBWORD ++ UNSPEC_SYNC_EXCHANGE_ZABHA + UNSPEC_ATOMIC_LOAD + UNSPEC_ATOMIC_STORE + UNSPEC_MEMORY_BARRIER +@@ -88,6 +90,18 @@ + + ;; AMO ops + ++(define_insn "atomic_" ++ [(set (match_operand:SHORT 0 "memory_operand" "+A") ++ (unspec_volatile:SHORT ++ [(any_atomic:SHORT (match_dup 0) ++ (match_operand:SHORT 1 "reg_or_0_operand" "rJ")) ++ (match_operand:SI 2 "const_int_operand")] ;; model ++ UNSPEC_SYNC_OLD_OP_ZABHA))] ++ "TARGET_ZABHA" ++ "amo.%A2\tzero,%z1,%0" ++ [(set_attr "type" "atomic") ++ (set (attr "length") (const_int 4))]) ++ + (define_expand "atomic_" + [(any_atomic:GPR (match_operand:GPR 0 "memory_operand") ;; mem location + (match_operand:GPR 1 "reg_or_0_operand")) ;; value for op +@@ -287,7 +301,37 @@ + (any_atomic:SHORT (match_operand:SHORT 1 "memory_operand") ;; mem location + (match_operand:SHORT 2 "reg_or_0_operand")) ;; value for op + (match_operand:SI 3 "const_int_operand")] ;; model +- "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC" ++ "(TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC) || TARGET_ZABHA" ++{ ++ if (TARGET_ZABHA) ++ emit_insn(gen_zabha_atomic_fetch_ (operands[0], operands[1], ++ operands[2], operands[3])); ++ else ++ emit_insn(gen_lrsc_atomic_fetch_ (operands[0], operands[1], ++ operands[2], operands[3])); ++ DONE; ++}) ++ ++(define_insn "zabha_atomic_fetch_" ++ [(set (match_operand:SHORT 0 "register_operand" "=&r") ++ (match_operand:SHORT 1 "memory_operand" "+A")) ++ (set (match_dup 1) ++ (unspec_volatile:SHORT ++ [(any_atomic:SHORT (match_dup 1) ++ (match_operand:SHORT 2 "reg_or_0_operand" "rJ")) ++ (match_operand:SI 3 "const_int_operand")] ;; model ++ UNSPEC_SYNC_OLD_OP_ZABHA))] ++ "TARGET_ZABHA" ++ "amo.%A3\t%0,%z2,%1" ++ [(set_attr "type" "atomic") ++ (set (attr "length") (const_int 4))]) ++ ++(define_expand "lrsc_atomic_fetch_" ++ [(match_operand:SHORT 0 "register_operand") ;; old value at mem ++ (any_atomic:SHORT (match_operand:SHORT 1 "memory_operand") ;; mem location ++ (match_operand:SHORT 2 "reg_or_0_operand")) ;; value for op ++ (match_operand:SI 3 "const_int_operand")] ;; model ++ "!TARGET_ZABHA && TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC" + { + /* We have no QImode/HImode atomics, so form a mask, then use + subword_atomic_fetch_strong_ to implement a LR/SC version of the +@@ -323,6 +367,8 @@ + DONE; + }) + ++; Atomic exchange ops ++ + (define_expand "atomic_exchange" + [(match_operand:GPR 0 "register_operand") ;; old value at mem + (match_operand:GPR 1 "memory_operand") ;; mem location +@@ -377,7 +423,36 @@ + (match_operand:SHORT 1 "memory_operand") ;; mem location + (match_operand:SHORT 2 "register_operand") ;; value + (match_operand:SI 3 "const_int_operand")] ;; model +- "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC" ++ "(TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC) || TARGET_ZABHA" ++{ ++ if (TARGET_ZABHA) ++ emit_insn(gen_zabha_atomic_exchange(operands[0], operands[1], ++ operands[2], operands[3])); ++ else ++ emit_insn(gen_lrsc_atomic_exchange(operands[0], operands[1], ++ operands[2], operands[3])); ++ DONE; ++}) ++ ++(define_insn "zabha_atomic_exchange" ++ [(set (match_operand:SHORT 0 "register_operand" "=&r") ++ (unspec_volatile:SHORT ++ [(match_operand:SHORT 1 "memory_operand" "+A") ++ (match_operand:SI 3 "const_int_operand")] ;; model ++ UNSPEC_SYNC_EXCHANGE_ZABHA)) ++ (set (match_dup 1) ++ (match_operand:SHORT 2 "register_operand" "0"))] ++ "TARGET_ZABHA" ++ "amoswap.%A3\t%0,%z2,%1" ++ [(set_attr "type" "atomic") ++ (set (attr "length") (const_int 4))]) ++ ++(define_expand "lrsc_atomic_exchange" ++ [(match_operand:SHORT 0 "register_operand") ;; old value at mem ++ (match_operand:SHORT 1 "memory_operand") ;; mem location ++ (match_operand:SHORT 2 "register_operand") ;; value ++ (match_operand:SI 3 "const_int_operand")] ;; model ++ "!TARGET_ZABHA && TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC" + { + rtx old = gen_reg_rtx (SImode); + rtx mem = operands[1]; +@@ -427,6 +502,8 @@ + [(set_attr "type" "multi") + (set (attr "length") (const_int 20))]) + ++; Atomic CAS ops ++ + (define_insn "atomic_cas_value_strong" + [(set (match_operand:GPR 0 "register_operand" "=&r") + (match_operand:GPR 1 "memory_operand" "+A")) +diff --git a/gcc/configure b/gcc/configure +index c0dd02ffff5..764e8e21075 100755 +--- a/gcc/configure ++++ b/gcc/configure +@@ -31100,6 +31100,37 @@ if test $gcc_cv_as_riscv_march_zaamo_zalrsc = yes; then + + $as_echo "#define HAVE_AS_MARCH_ZAAMO_ZALRSC 1" >>confdefs.h + ++fi ++ ++ { $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for -march=rv32i_zabha support" >&5 ++$as_echo_n "checking assembler for -march=rv32i_zabha support... " >&6; } ++if ${gcc_cv_as_riscv_march_zabha+:} false; then : ++ $as_echo_n "(cached) " >&6 ++else ++ gcc_cv_as_riscv_march_zabha=no ++ if test x$gcc_cv_as != x; then ++ $as_echo '' > conftest.s ++ if { ac_try='$gcc_cv_as $gcc_cv_as_flags -march=rv32i_zabha -o conftest.o conftest.s >&5' ++ { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5 ++ (eval $ac_try) 2>&5 ++ ac_status=$? ++ $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 ++ test $ac_status = 0; }; } ++ then ++ gcc_cv_as_riscv_march_zabha=yes ++ else ++ echo "configure: failed program was" >&5 ++ cat conftest.s >&5 ++ fi ++ rm -f conftest.o conftest.s ++ fi ++fi ++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_as_riscv_march_zabha" >&5 ++$as_echo "$gcc_cv_as_riscv_march_zabha" >&6; } ++if test $gcc_cv_as_riscv_march_zabha = yes; then ++ ++$as_echo "#define HAVE_AS_MARCH_ZABHA 1" >>confdefs.h ++ + fi + + ;; +diff --git a/gcc/configure.ac b/gcc/configure.ac +index 09ffd6bca3c..2a0f7440eaa 100644 +--- a/gcc/configure.ac ++++ b/gcc/configure.ac +@@ -5523,6 +5523,11 @@ configured with --enable-newlib-nano-formatted-io.]) + [-march=rv32i_zaamo_zalrsc],,, + [AC_DEFINE(HAVE_AS_MARCH_ZAAMO_ZALRSC, 1, + [Define if the assembler understands -march=rv*_zaamo_zalrsc.])]) ++ gcc_GAS_CHECK_FEATURE([-march=rv32i_zabha support], ++ gcc_cv_as_riscv_march_zabha, ++ [-march=rv32i_zabha],,, ++ [AC_DEFINE(HAVE_AS_MARCH_ZABHA, 1, ++ [Define if the assembler understands -march=rv*_zabha.])]) + ;; + loongarch*-*-*) + gcc_GAS_CHECK_FEATURE([.dtprelword support], +diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi +index 4a671c8a295..b7b98b1bd10 100644 +--- a/gcc/doc/sourcebuild.texi ++++ b/gcc/doc/sourcebuild.texi +@@ -2521,7 +2521,10 @@ Test target architecture has support for the A extension. + @item riscv_zaamo + Test target architecture has support for the zaamo extension. + +-@item riscv_zlrsc ++@item riscv_zabha ++Test target architecture has support for the zabha extension. ++ ++@item riscv_zalrsc + Test target architecture has support for the zalrsc extension. + + @item riscv_ztso +@@ -3286,6 +3289,9 @@ Add the 'A' extension to the -march string on RISC-V targets. + @item riscv_zaamo + Add the zaamo extension to the -march string on RISC-V targets. + ++@item riscv_zabha ++Add the zabha extension to the -march string on RISC-V targets. ++ + @item riscv_zalrsc + Add the zalrsc extension to the -march string on RISC-V targets. + +@@ -3329,6 +3335,10 @@ RISC-V targets. + Remove the zaamo extension from the -march string on RISC-V. If the 'A' + extension is present downgrade it to zalrsc. + ++@item riscv_zabha ++Remove the zabha extension and implied zaamo extension from the -march string ++on RISC-V. ++ + @item riscv_zalrsc + Remove the zalrsc extension from the -march string on RISC-V. If the 'A' + extension is present downgrade it to zaamo. +diff --git a/gcc/testsuite/gcc.target/riscv/amo/inline-atomics-1.c b/gcc/testsuite/gcc.target/riscv/amo/inline-atomics-1.c +index 5c5623d9b2f..8556637d17d 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/inline-atomics-1.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/inline-atomics-1.c +@@ -1,5 +1,6 @@ + /* { dg-do compile } */ + /* { dg-options "-mno-inline-atomics" } */ ++/* { dg-remove-options riscv_zabha } */ + /* { dg-message "note: '__sync_fetch_and_nand' changed semantics in GCC 4.4" "fetch_and_nand" { target *-*-* } 0 } */ + /* { dg-final { scan-assembler "\tcall\t__sync_fetch_and_add_1" } } */ + /* { dg-final { scan-assembler "\tcall\t__sync_fetch_and_nand_1" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo/inline-atomics-2.c b/gcc/testsuite/gcc.target/riscv/amo/inline-atomics-2.c +index 76c99829f33..8ec07b0e0e4 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/inline-atomics-2.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/inline-atomics-2.c +@@ -2,6 +2,7 @@ + /* Verify that subword atomics do not generate calls. */ + /* { dg-options "-minline-atomics" } */ + /* { dg-add-options riscv_a } */ ++/* { dg-remove-options riscv_zabha } */ + /* { dg-message "note: '__sync_fetch_and_nand' changed semantics in GCC 4.4" "fetch_and_nand" { target *-*-* } 0 } */ + /* { dg-final { scan-assembler-not "\tcall\t__sync_fetch_and_add_1" } } */ + /* { dg-final { scan-assembler-not "\tcall\t__sync_fetch_and_nand_1" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zabha-all-amo-ops-char-run.c b/gcc/testsuite/gcc.target/riscv/amo/zabha-all-amo-ops-char-run.c +new file mode 100644 +index 00000000000..039318b6ca7 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo/zabha-all-amo-ops-char-run.c +@@ -0,0 +1,5 @@ ++/* Test __atomic routines for existence on 1 byte values with each valid memory model. */ ++/* { dg-do run { target { riscv_zabha } } } */ ++/* { dg-options "-Wno-address-of-packed-member" } */ ++ ++#include "inline-atomics-3.c" +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zabha-all-amo-ops-short-run.c b/gcc/testsuite/gcc.target/riscv/amo/zabha-all-amo-ops-short-run.c +new file mode 100644 +index 00000000000..7639537893c +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo/zabha-all-amo-ops-short-run.c +@@ -0,0 +1,5 @@ ++/* Test __atomic routines for execution on 2 byte values with each valid memory model. */ ++/* { dg-do run { target { riscv_zabha } } } */ ++/* { dg-options "-Wno-address-of-packed-member" } */ ++ ++#include "inline-atomics-4.c" +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-char.c b/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-char.c +new file mode 100644 +index 00000000000..85841fd7036 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-char.c +@@ -0,0 +1,23 @@ ++/* Test __atomic routines for existence on 2 byte values with each valid memory model. */ ++/* { dg-compile } */ ++/* { dg-options "-Wno-address-of-packed-member" } */ ++/* { dg-add-options riscv_zabha } */ ++/* { dg-remove-options riscv_ztso } */ ++/* { dg-final { scan-assembler "\tamoadd.b" } } */ ++/* { dg-final { scan-assembler "\tamoadd.b.aq" } } */ ++/* { dg-final { scan-assembler "\tamoadd.b.rl" } } */ ++/* { dg-final { scan-assembler "\tamoadd.b.aqrl" } } */ ++/* { dg-final { scan-assembler "\tamoand.b" } } */ ++/* { dg-final { scan-assembler "\tamoand.b.aq" } } */ ++/* { dg-final { scan-assembler "\tamoand.b.rl" } } */ ++/* { dg-final { scan-assembler "\tamoand.b.aqrl" } } */ ++/* { dg-final { scan-assembler "\tamoxor.b" } } */ ++/* { dg-final { scan-assembler "\tamoxor.b.aq" } } */ ++/* { dg-final { scan-assembler "\tamoxor.b.rl" } } */ ++/* { dg-final { scan-assembler "\tamoxor.b.aqrl" } } */ ++/* { dg-final { scan-assembler "\tamoor.b" } } */ ++/* { dg-final { scan-assembler "\tamoor.b.aq" } } */ ++/* { dg-final { scan-assembler "\tamoor.b.rl" } } */ ++/* { dg-final { scan-assembler "\tamoor.b.aqrl" } } */ ++ ++#include "inline-atomics-3.c" +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-short.c b/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-short.c +new file mode 100644 +index 00000000000..edc0a2c8f8e +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-short.c +@@ -0,0 +1,23 @@ ++/* Test __atomic routines for existence on 2 byte values with each valid memory model. */ ++/* { dg-compile } */ ++/* { dg-options "-Wno-address-of-packed-member" } */ ++/* { dg-add-options riscv_zabha } */ ++/* { dg-remove-options riscv_ztso } */ ++/* { dg-final { scan-assembler "\tamoadd.h" } } */ ++/* { dg-final { scan-assembler "\tamoadd.h.aq" } } */ ++/* { dg-final { scan-assembler "\tamoadd.h.rl" } } */ ++/* { dg-final { scan-assembler "\tamoadd.h.aqrl" } } */ ++/* { dg-final { scan-assembler "\tamoand.h" } } */ ++/* { dg-final { scan-assembler "\tamoand.h.aq" } } */ ++/* { dg-final { scan-assembler "\tamoand.h.rl" } } */ ++/* { dg-final { scan-assembler "\tamoand.h.aqrl" } } */ ++/* { dg-final { scan-assembler "\tamoxor.h" } } */ ++/* { dg-final { scan-assembler "\tamoxor.h.aq" } } */ ++/* { dg-final { scan-assembler "\tamoxor.h.rl" } } */ ++/* { dg-final { scan-assembler "\tamoxor.h.aqrl" } } */ ++/* { dg-final { scan-assembler "\tamoor.h" } } */ ++/* { dg-final { scan-assembler "\tamoor.h.aq" } } */ ++/* { dg-final { scan-assembler "\tamoor.h.rl" } } */ ++/* { dg-final { scan-assembler "\tamoor.h.aqrl" } } */ ++ ++#include "inline-atomics-4.c" +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-amo-add-char.c b/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-amo-add-char.c +new file mode 100644 +index 00000000000..a75c102196d +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-amo-add-char.c +@@ -0,0 +1,57 @@ ++/* Verify that atomic op mappings match the PSABI doc's recommended mapping. */ ++/* { dg-do compile } */ ++/* { dg-options "-O3" } */ ++/* { dg-add-options riscv_zabha } */ ++/* { dg-remove-options riscv_ztso } */ ++/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ ++/* { dg-final { check-function-bodies "**" "" } } */ ++ ++/* ++** atomic_add_fetch_char_relaxed: ++** amoadd\.b\tzero,a1,0\(a0\) ++** ret ++*/ ++void atomic_add_fetch_char_relaxed (char* bar, char baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_RELAXED); ++} ++ ++/* ++** atomic_add_fetch_char_acquire: ++** amoadd\.b\.aq\tzero,a1,0\(a0\) ++** ret ++*/ ++void atomic_add_fetch_char_acquire (char* bar, char baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_ACQUIRE); ++} ++ ++/* ++** atomic_add_fetch_char_release: ++** amoadd\.b\.rl\tzero,a1,0\(a0\) ++** ret ++*/ ++void atomic_add_fetch_char_release (char* bar, char baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_RELEASE); ++} ++ ++/* ++** atomic_add_fetch_char_acq_rel: ++** amoadd\.b\.aqrl\tzero,a1,0\(a0\) ++** ret ++*/ ++void atomic_add_fetch_char_acq_rel (char* bar, char baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_ACQ_REL); ++} ++ ++/* ++** atomic_add_fetch_char_seq_cst: ++** amoadd\.b\.aqrl\tzero,a1,0\(a0\) ++** ret ++*/ ++void atomic_add_fetch_char_seq_cst (char* bar, char baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_SEQ_CST); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-amo-add-short.c b/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-amo-add-short.c +new file mode 100644 +index 00000000000..7755bb84784 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-amo-add-short.c +@@ -0,0 +1,57 @@ ++/* Verify that atomic op mappings match the PSABI doc's recommended mapping. */ ++/* { dg-do compile } */ ++/* { dg-options "-O3" } */ ++/* { dg-add-options riscv_zabha } */ ++/* { dg-remove-options riscv_ztso } */ ++/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ ++/* { dg-final { check-function-bodies "**" "" } } */ ++ ++/* ++** atomic_add_fetch_short_relaxed: ++** amoadd\.h\tzero,a1,0\(a0\) ++** ret ++*/ ++void atomic_add_fetch_short_relaxed (short* bar, short baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_RELAXED); ++} ++ ++/* ++** atomic_add_fetch_short_acquire: ++** amoadd\.h\.aq\tzero,a1,0\(a0\) ++** ret ++*/ ++void atomic_add_fetch_short_acquire (short* bar, short baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_ACQUIRE); ++} ++ ++/* ++** atomic_add_fetch_short_release: ++** amoadd\.h\.rl\tzero,a1,0\(a0\) ++** ret ++*/ ++void atomic_add_fetch_short_release (short* bar, short baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_RELEASE); ++} ++ ++/* ++** atomic_add_fetch_short_acq_rel: ++** amoadd\.h\.aqrl\tzero,a1,0\(a0\) ++** ret ++*/ ++void atomic_add_fetch_short_acq_rel (short* bar, short baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_ACQ_REL); ++} ++ ++/* ++** atomic_add_fetch_short_seq_cst: ++** amoadd\.h\.aqrl\tzero,a1,0\(a0\) ++** ret ++*/ ++void atomic_add_fetch_short_seq_cst (short* bar, short baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_SEQ_CST); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zabha-ztso-amo-add-char.c b/gcc/testsuite/gcc.target/riscv/amo/zabha-ztso-amo-add-char.c +new file mode 100644 +index 00000000000..bcd7477c673 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo/zabha-ztso-amo-add-char.c +@@ -0,0 +1,57 @@ ++/* Verify that atomic op mappings match the PSABI doc's recommended mapping. */ ++/* { dg-do compile } */ ++/* { dg-options "-O3" } */ ++/* { dg-add-options riscv_ztso } */ ++/* { dg-add-options riscv_zabha } */ ++/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ ++/* { dg-final { check-function-bodies "**" "" } } */ ++ ++/* ++** atomic_add_fetch_char_relaxed: ++** amoadd\.b\tzero,a1,0\(a0\) ++** ret ++*/ ++void atomic_add_fetch_char_relaxed (char* bar, char baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_RELAXED); ++} ++ ++/* ++** atomic_add_fetch_char_acquire: ++** amoadd\.b\tzero,a1,0\(a0\) ++** ret ++*/ ++void atomic_add_fetch_char_acquire (char* bar, char baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_ACQUIRE); ++} ++ ++/* ++** atomic_add_fetch_char_release: ++** amoadd\.b\tzero,a1,0\(a0\) ++** ret ++*/ ++void atomic_add_fetch_char_release (char* bar, char baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_RELEASE); ++} ++ ++/* ++** atomic_add_fetch_char_acq_rel: ++** amoadd\.b\tzero,a1,0\(a0\) ++** ret ++*/ ++void atomic_add_fetch_char_acq_rel (char* bar, char baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_ACQ_REL); ++} ++ ++/* ++** atomic_add_fetch_char_seq_cst: ++** amoadd\.b\tzero,a1,0\(a0\) ++** ret ++*/ ++void atomic_add_fetch_char_seq_cst (char* bar, char baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_SEQ_CST); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zabha-ztso-amo-add-short.c b/gcc/testsuite/gcc.target/riscv/amo/zabha-ztso-amo-add-short.c +new file mode 100644 +index 00000000000..c4e8c9cf3ef +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo/zabha-ztso-amo-add-short.c +@@ -0,0 +1,57 @@ ++/* Verify that atomic op mappings match the PSABI doc's recommended mapping. */ ++/* { dg-do compile } */ ++/* { dg-options "-O3" } */ ++/* { dg-add-options riscv_ztso } */ ++/* { dg-add-options riscv_zabha } */ ++/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ ++/* { dg-final { check-function-bodies "**" "" } } */ ++ ++/* ++** atomic_add_fetch_short_relaxed: ++** amoadd\.h\tzero,a1,0\(a0\) ++** ret ++*/ ++void atomic_add_fetch_short_relaxed (short* bar, short baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_RELAXED); ++} ++ ++/* ++** atomic_add_fetch_short_acquire: ++** amoadd\.h\tzero,a1,0\(a0\) ++** ret ++*/ ++void atomic_add_fetch_short_acquire (short* bar, short baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_ACQUIRE); ++} ++ ++/* ++** atomic_add_fetch_short_release: ++** amoadd\.h\tzero,a1,0\(a0\) ++** ret ++*/ ++void atomic_add_fetch_short_release (short* bar, short baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_RELEASE); ++} ++ ++/* ++** atomic_add_fetch_short_acq_rel: ++** amoadd\.h\tzero,a1,0\(a0\) ++** ret ++*/ ++void atomic_add_fetch_short_acq_rel (short* bar, short baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_ACQ_REL); ++} ++ ++/* ++** atomic_add_fetch_short_seq_cst: ++** amoadd\.h\tzero,a1,0\(a0\) ++** ret ++*/ ++void atomic_add_fetch_short_seq_cst (short* bar, short baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_SEQ_CST); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acq-rel.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acq-rel.c +index 2c2df133a28..33b70acb15c 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acq-rel.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acq-rel.c +@@ -2,6 +2,7 @@ + /* Verify that subword atomic op mappings match the PSABI doc's recommended mapping. */ + /* { dg-add-options riscv_zalrsc } */ + /* { dg-remove-options riscv_ztso } */ ++/* { dg-remove-options riscv_zabha } */ + /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acquire.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acquire.c +index abfbf63902c..e173296bcfc 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acquire.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acquire.c +@@ -2,6 +2,7 @@ + /* Verify that subword atomic op mappings match the PSABI doc's recommended mapping. */ + /* { dg-add-options riscv_zalrsc } */ + /* { dg-remove-options riscv_ztso } */ ++/* { dg-remove-options riscv_zabha } */ + /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-relaxed.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-relaxed.c +index 1f61c89da88..f544d677219 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-relaxed.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-relaxed.c +@@ -2,6 +2,7 @@ + /* Verify that subword atomic op mappings match the PSABI doc's recommended mapping. */ + /* { dg-add-options riscv_zalrsc } */ + /* { dg-remove-options riscv_ztso } */ ++/* { dg-remove-options riscv_zabha } */ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-release.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-release.c +index 343503ce79c..bb34873feeb 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-release.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-release.c +@@ -2,6 +2,7 @@ + /* Verify that subword atomic op mappings match the PSABI doc's recommended mapping. */ + /* { dg-add-options riscv_zalrsc } */ + /* { dg-remove-options riscv_ztso } */ ++/* { dg-remove-options riscv_zabha } */ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-seq-cst.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-seq-cst.c +index 045434b2579..d8991ee1a84 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-seq-cst.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-seq-cst.c +@@ -2,6 +2,7 @@ + /* Verify that subword atomic op mappings match the PSABI doc's recommended mapping. */ + /* { dg-add-options riscv_zalrsc } */ + /* { dg-remove-options riscv_ztso } */ ++/* { dg-remove-options riscv_zabha } */ + /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acq-rel.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acq-rel.c +index f64b10a076a..7c9187e52b5 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acq-rel.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acq-rel.c +@@ -2,6 +2,7 @@ + /* Verify that subword atomic op mappings match the PSABI doc's suggested mapping. */ + /* { dg-add-options riscv_zalrsc } */ + /* { dg-add-options riscv_ztso } */ ++/* { dg-remove-options riscv_zabha } */ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acquire.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acquire.c +index 5d743f0ab83..675043f9c61 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acquire.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acquire.c +@@ -2,6 +2,7 @@ + /* Verify that subword atomic op mappings match the PSABI doc's suggested mapping. */ + /* { dg-add-options riscv_zalrsc } */ + /* { dg-add-options riscv_ztso } */ ++/* { dg-remove-options riscv_zabha } */ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-relaxed.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-relaxed.c +index 3e7dda9c8c4..7bf9eb0a7f7 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-relaxed.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-relaxed.c +@@ -2,6 +2,7 @@ + /* Verify that subword atomic op mappings match the PSABI doc's suggested mapping. */ + /* { dg-add-options riscv_zalrsc } */ + /* { dg-add-options riscv_ztso } */ ++/* { dg-remove-options riscv_zabha } */ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-release.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-release.c +index ffd832eef78..6b78ce74b00 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-release.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-release.c +@@ -2,6 +2,7 @@ + /* Verify that subword atomic op mappings match the PSABI doc's suggested mapping. */ + /* { dg-add-options riscv_zalrsc } */ + /* { dg-add-options riscv_ztso } */ ++/* { dg-remove-options riscv_zabha } */ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-seq-cst.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-seq-cst.c +index e9ea3f5ff3b..14fadf1e3fe 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-seq-cst.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-seq-cst.c +@@ -2,6 +2,7 @@ + /* Verify that subword atomic op mappings match the PSABI doc's suggested mapping. */ + /* { dg-add-options riscv_zalrsc } */ + /* { dg-add-options riscv_ztso } */ ++/* { dg-remove-options riscv_zabha } */ + /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ + +diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp +index bd1d46a0fc7..ec6cbf01f2c 100644 +--- a/gcc/testsuite/lib/target-supports.exp ++++ b/gcc/testsuite/lib/target-supports.exp +@@ -1933,6 +1933,17 @@ proc check_effective_target_riscv_zaamo { } { + }] + } + ++# Return 1 if the target arch supports the atomic BHA extension, 0 otherwise. ++# Cache the result. ++ ++proc check_effective_target_riscv_zabha { } { ++ return [check_no_compiler_messages riscv_ext_zabha assembly { ++ #ifndef __riscv_zabha ++ #error "Not __riscv_zabha" ++ #endif ++ }] ++} ++ + # Return 1 if the target arch supports the double precision floating point + # extension, 0 otherwise. Cache the result. + +@@ -2188,7 +2199,7 @@ proc check_effective_target_riscv_v_misalign_ok { } { + proc riscv_get_arch { } { + set gcc_march "" + # ??? do we neeed to add more extensions to the list below? +- foreach ext { i m a f d q c v zicsr zifencei zfh zba zbb zbc zbs zvbb zvfh ztso zaamo zalrsc } { ++ foreach ext { i m a f d q c v zicsr zifencei zfh zba zbb zbc zbs zvbb zvfh ztso zaamo zalrsc zabha } { + if { [check_no_compiler_messages riscv_ext_$ext assembly [string map [list DEF __riscv_$ext] { + #ifndef DEF + #error "Not DEF" +@@ -2353,12 +2364,15 @@ proc add_options_for_riscv_zaamo { flags } { + + proc remove_options_for_riscv_zaamo { flags } { + set modified_flags [remove_options_for_riscv_z_ext zaamo $flags] ++ # If zabha is set then zaamo will be implied. We need to remove zabha ++ # as well. ++ set modified_flags [remove_options_for_riscv_z_ext zabha $modified_flags] + # If 'a' is set then zaamo will be implied. We need to downgrade instances + # of 'a' to 'zalrsc' +- set no_a_flags [remove_options_for_riscv_a_only [split $modified_flags]] ++ set no_a_flags [remove_options_for_riscv_a_only $modified_flags] + if {![string equal $modified_flags $no_a_flags]} { + # 'a' was removed, add 'zalrsc' since it was previously implied +- set modified_flags [add_options_for_riscv_zalrsc [split $no_a_flags]] ++ set modified_flags [add_options_for_riscv_zalrsc $no_a_flags] + } + return $modified_flags + } +@@ -2371,14 +2385,23 @@ proc remove_options_for_riscv_zalrsc { flags } { + set modified_flags [remove_options_for_riscv_z_ext zalrsc $flags] + # If 'a' is set then zalrsc will be implied. We need to downgrade instances + # of 'a' to 'zaamo' +- set no_a_flags [remove_options_for_riscv_a_only [split $modified_flags]] ++ set no_a_flags [remove_options_for_riscv_a_only $modified_flags] + if {![string equal $modified_flags $no_a_flags]} { + # 'a' was removed, add 'zalrsc' since it was previously implied +- set modified_flags [add_options_for_riscv_zalrsc [split $no_a_flags]] ++ set modified_flags [add_options_for_riscv_zalrsc $no_a_flags] + } + return $modified_flags + } + ++proc add_options_for_riscv_zabha { flags } { ++ return [add_options_for_riscv_z_ext zabha $flags] ++} ++ ++proc remove_options_for_riscv_zabha { flags } { ++ set modified_flags [remove_options_for_riscv_zaamo $flags] ++ return [remove_options_for_riscv_z_ext zabha $modified_flags] ++} ++ + proc add_options_for_riscv_zfh { flags } { + return [add_options_for_riscv_z_ext zfh $flags] + } +-- +2.47.3 + diff --git a/1053-RISC-V-Add-support-for-B-standard-extension.patch b/1053-RISC-V-Add-support-for-B-standard-extension.patch new file mode 100644 index 0000000..63293c5 --- /dev/null +++ b/1053-RISC-V-Add-support-for-B-standard-extension.patch @@ -0,0 +1,73 @@ +From 0cb3721a1eaa1682567287b933b2e345413ad56b Mon Sep 17 00:00:00 2001 +From: Edwin Lu +Date: Wed, 10 Jul 2024 09:44:48 -0700 +Subject: [PATCH 1053/1087] RISC-V: Add support for B standard extension + +commit 2a90c41a131080e5fdd2b5554fcdba5c654cb93f upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +This patch adds support for recognizing the B standard extension to be the +collection of Zba, Zbb, Zbs extensions for consistency and conciseness +across toolchains + +https://github.com/riscv/riscv-b/tags + +gcc/ChangeLog: + + * common/config/riscv/riscv-common.cc: Add imply rules for B extension + * config/riscv/arch-canonicalize: Ditto + +Signed-off-by: Edwin Lu +--- + gcc/common/config/riscv/riscv-common.cc | 7 +++++++ + gcc/config/riscv/arch-canonicalize | 1 + + 2 files changed, 8 insertions(+) + +diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc +index 854fa8b5905..ed7d72fc76e 100644 +--- a/gcc/common/config/riscv/riscv-common.cc ++++ b/gcc/common/config/riscv/riscv-common.cc +@@ -84,6 +84,10 @@ static const riscv_implied_info_t riscv_implied_info[] = + + {"zabha", "zaamo"}, + ++ {"b", "zba"}, ++ {"b", "zbb"}, ++ {"b", "zbs"}, ++ + {"zdinx", "zfinx"}, + {"zfinx", "zicsr"}, + {"zdinx", "zicsr"}, +@@ -247,6 +251,8 @@ static const struct riscv_ext_version riscv_ext_version_table[] = + {"c", ISA_SPEC_CLASS_20190608, 2, 0}, + {"c", ISA_SPEC_CLASS_2P2, 2, 0}, + ++ {"b", ISA_SPEC_CLASS_NONE, 1, 0}, ++ + {"h", ISA_SPEC_CLASS_NONE, 1, 0}, + + {"v", ISA_SPEC_CLASS_NONE, 1, 0}, +@@ -410,6 +416,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] = + static const struct riscv_ext_version riscv_combine_info[] = + { + {"a", ISA_SPEC_CLASS_20191213, 2, 1}, ++ {"b", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zk", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zkn", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zks", ISA_SPEC_CLASS_NONE, 1, 0}, +diff --git a/gcc/config/riscv/arch-canonicalize b/gcc/config/riscv/arch-canonicalize +index 35a7fe4455a..2ea514dd986 100755 +--- a/gcc/config/riscv/arch-canonicalize ++++ b/gcc/config/riscv/arch-canonicalize +@@ -45,6 +45,7 @@ IMPLIED_EXT = { + "zabha" : ["zaamo"], + + "f" : ["zicsr"], ++ "b" : ["zba", "zbb", "zbs"], + "zdinx" : ["zfinx", "zicsr"], + "zfinx" : ["zicsr"], + "zhinx" : ["zhinxmin", "zfinx", "zicsr"], +-- +2.47.3 + diff --git a/1054-RISC-V-Update-testsuite-to-use-b.patch b/1054-RISC-V-Update-testsuite-to-use-b.patch new file mode 100644 index 0000000..d46ddd6 --- /dev/null +++ b/1054-RISC-V-Update-testsuite-to-use-b.patch @@ -0,0 +1,81 @@ +From 86ccbe30d95525bea752679232b898295d87a3d5 Mon Sep 17 00:00:00 2001 +From: Edwin Lu +Date: Wed, 3 Jul 2024 17:17:27 -0700 +Subject: [PATCH 1054/1087] RISC-V: Update testsuite to use b + +commit 04df2a924bba38c271bfe4ed0e94af1877413818 upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +Update all instances of zba_zbb_zbs in the testsuite to use b instead + +gcc/testsuite/ChangeLog: + + * g++.target/riscv/redundant-bitmap-1.C: Use gcb instead of + zba_zbb_zbs + * g++.target/riscv/redundant-bitmap-2.C: Ditto + * g++.target/riscv/redundant-bitmap-3.C: Ditto + * g++.target/riscv/redundant-bitmap-4.C: Ditto + * gcc.target/riscv/shift-add-1.c: Ditto + * gcc.target/riscv/shift-add-2.c: Ditto + * gcc.target/riscv/synthesis-1.c: Ditto + * gcc.target/riscv/synthesis-2.c: Ditto + * gcc.target/riscv/synthesis-3.c: Ditto + * gcc.target/riscv/synthesis-4.c: Ditto + * gcc.target/riscv/synthesis-5.c: Ditto + * gcc.target/riscv/synthesis-6.c: Ditto + * gcc.target/riscv/synthesis-7.c: Ditto + * gcc.target/riscv/synthesis-8.c: Ditto + * gcc.target/riscv/zba_zbs_and-1.c: Ditto + * gcc.target/riscv/zbs-zext-3.c: Ditto + * lib/target-supports.exp: Add b to riscv_get_arch + +Signed-off-by: Edwin Lu +--- + gcc/testsuite/gcc.target/riscv/synthesis-1.c | 2 +- + gcc/testsuite/gcc.target/riscv/synthesis-2.c | 2 +- + gcc/testsuite/lib/target-supports.exp | 2 +- + 3 files changed, 3 insertions(+), 3 deletions(-) + +diff --git a/gcc/testsuite/gcc.target/riscv/synthesis-1.c b/gcc/testsuite/gcc.target/riscv/synthesis-1.c +index 3384e488ade..da16cc54d53 100644 +--- a/gcc/testsuite/gcc.target/riscv/synthesis-1.c ++++ b/gcc/testsuite/gcc.target/riscv/synthesis-1.c +@@ -5,7 +5,7 @@ + and eliminates the usual sources of extraneous dead code that would throw + off the counts. */ + /* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O2" "-O3" "-Os" "-Oz" "-flto" } } */ +-/* { dg-options "-march=rv64gc_zba_zbb_zbs" } */ ++/* { dg-options "-march=rv64gcb" } */ + + /* Rather than test for a specific synthesis of all these constants or + having thousands of tests each testing one variant, we just test the +diff --git a/gcc/testsuite/gcc.target/riscv/synthesis-2.c b/gcc/testsuite/gcc.target/riscv/synthesis-2.c +index b88374da3c4..82383408f77 100644 +--- a/gcc/testsuite/gcc.target/riscv/synthesis-2.c ++++ b/gcc/testsuite/gcc.target/riscv/synthesis-2.c +@@ -5,7 +5,7 @@ + and eliminates the usual sources of extraneous dead code that would throw + off the counts. */ + /* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O2" "-O3" "-Os" "-Oz" "-flto" } } */ +-/* { dg-options "-march=rv64gc_zba_zbb_zbs" } */ ++/* { dg-options "-march=rv64gcb" } */ + + /* All these cases have the same form. lui+slli.uw+addi + /* { dg-final { scan-assembler-times "\\tadd" 367 } } */ +diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp +index ec6cbf01f2c..5a74883c066 100644 +--- a/gcc/testsuite/lib/target-supports.exp ++++ b/gcc/testsuite/lib/target-supports.exp +@@ -2199,7 +2199,7 @@ proc check_effective_target_riscv_v_misalign_ok { } { + proc riscv_get_arch { } { + set gcc_march "" + # ??? do we neeed to add more extensions to the list below? +- foreach ext { i m a f d q c v zicsr zifencei zfh zba zbb zbc zbs zvbb zvfh ztso zaamo zalrsc zabha } { ++ foreach ext { i m a f d q c b v zicsr zifencei zfh zba zbb zbc zbs zvbb zvfh ztso zaamo zalrsc zabha } { + if { [check_no_compiler_messages riscv_ext_$ext assembly [string map [list DEF __riscv_$ext] { + #ifndef DEF + #error "Not DEF" +-- +2.47.3 + diff --git a/1055-RISC-V-c-implies-zca-and-conditionally-zcf-zcd.patch b/1055-RISC-V-c-implies-zca-and-conditionally-zcf-zcd.patch new file mode 100644 index 0000000..4db7a43 --- /dev/null +++ b/1055-RISC-V-c-implies-zca-and-conditionally-zcf-zcd.patch @@ -0,0 +1,204 @@ +From a5d2c52a913dd2e01555ad03fbb219cd2e0e1f85 Mon Sep 17 00:00:00 2001 +From: Fei Gao +Date: Wed, 10 Jul 2024 10:12:02 +0000 +Subject: [PATCH 1055/1087] RISC-V: c implies zca, and conditionally zcf & zcd + +commit 36e5e409190e595638cec053ea034d20d5c74d6b upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +According to Zc-1.0.4-3.pdf from +https://github.com/riscvarchive/riscv-code-size-reduction/releases/tag/v1.0.4-3 +The rule is that: +- C always implies Zca +- C+F implies Zcf (RV32 only) +- C+D implies Zcd + +Signed-off-by: Fei Gao +gcc/ChangeLog: + + * common/config/riscv/riscv-common.cc: + c implies zca, and conditionally zcf & zcd. + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/attribute-15.c: adapt TC. + * gcc.target/riscv/attribute-16.c: likewise. + * gcc.target/riscv/attribute-17.c: likewise. + * gcc.target/riscv/attribute-18.c: likewise. + * gcc.target/riscv/pr110696.c: likewise. + * gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c: likewise. + * gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c: likewise. + * gcc.target/riscv/rvv/base/pr114352-1.c: likewise. + * gcc.target/riscv/rvv/base/pr114352-3.c: likewise. + * gcc.target/riscv/arch-39.c: New test. + * gcc.target/riscv/arch-40.c: New test. +--- + gcc/common/config/riscv/riscv-common.cc | 12 ++++++++++++ + gcc/testsuite/gcc.target/riscv/arch-39.c | 7 +++++++ + gcc/testsuite/gcc.target/riscv/arch-40.c | 7 +++++++ + gcc/testsuite/gcc.target/riscv/attribute-15.c | 2 +- + gcc/testsuite/gcc.target/riscv/attribute-16.c | 2 +- + gcc/testsuite/gcc.target/riscv/attribute-17.c | 2 +- + gcc/testsuite/gcc.target/riscv/attribute-18.c | 2 +- + gcc/testsuite/gcc.target/riscv/pr110696.c | 2 +- + .../riscv/rvv/base/abi-callee-saved-1-zcmp.c | 2 +- + .../riscv/rvv/base/abi-callee-saved-2-zcmp.c | 2 +- + gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c | 4 ++-- + gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c | 8 ++++---- + 12 files changed, 39 insertions(+), 13 deletions(-) + create mode 100644 gcc/testsuite/gcc.target/riscv/arch-39.c + create mode 100644 gcc/testsuite/gcc.target/riscv/arch-40.c + +diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc +index ed7d72fc76e..7e34bcd97fc 100644 +--- a/gcc/common/config/riscv/riscv-common.cc ++++ b/gcc/common/config/riscv/riscv-common.cc +@@ -82,6 +82,18 @@ static const riscv_implied_info_t riscv_implied_info[] = + {"a", "zaamo"}, + {"a", "zalrsc"}, + ++ {"c", "zca"}, ++ {"c", "zcf", ++ [] (const riscv_subset_list *subset_list) -> bool ++ { ++ return subset_list->xlen () == 32 && subset_list->lookup ("f"); ++ }}, ++ {"c", "zcd", ++ [] (const riscv_subset_list *subset_list) -> bool ++ { ++ return subset_list->lookup ("d"); ++ }}, ++ + {"zabha", "zaamo"}, + + {"b", "zba"}, +diff --git a/gcc/testsuite/gcc.target/riscv/arch-39.c b/gcc/testsuite/gcc.target/riscv/arch-39.c +new file mode 100644 +index 00000000000..beeb81e44c5 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/arch-39.c +@@ -0,0 +1,7 @@ ++/* { dg-do compile } */ ++/* { dg-options "-march=rv64idc_zcmt -mabi=lp64d" } */ ++int ++foo () ++{} ++ ++/* { dg-error "zcd conflicts with zcmt" "" { target *-*-* } 0 } */ +diff --git a/gcc/testsuite/gcc.target/riscv/arch-40.c b/gcc/testsuite/gcc.target/riscv/arch-40.c +new file mode 100644 +index 00000000000..eaefaf1d0d7 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/arch-40.c +@@ -0,0 +1,7 @@ ++/* { dg-do compile } */ ++/* { dg-options "-march=rv64idc_zcmp -mabi=lp64d" } */ ++int ++foo () ++{} ++ ++/* { dg-error "zcd conflicts with zcmp" "" { target *-*-* } 0 } */ +diff --git a/gcc/testsuite/gcc.target/riscv/attribute-15.c b/gcc/testsuite/gcc.target/riscv/attribute-15.c +index a2e394b6489..ac6caaecd4f 100644 +--- a/gcc/testsuite/gcc.target/riscv/attribute-15.c ++++ b/gcc/testsuite/gcc.target/riscv/attribute-15.c +@@ -3,4 +3,4 @@ + int foo() + { + } +-/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zaamo1p0_zalrsc1p0\"" } } */ ++/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0\"" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/attribute-16.c b/gcc/testsuite/gcc.target/riscv/attribute-16.c +index d2b18160cb5..539e426ca97 100644 +--- a/gcc/testsuite/gcc.target/riscv/attribute-16.c ++++ b/gcc/testsuite/gcc.target/riscv/attribute-16.c +@@ -3,4 +3,4 @@ + int foo() + { + } +-/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_m2p0_a2p0_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0\"" } } */ ++/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_m2p0_a2p0_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0\"" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/attribute-17.c b/gcc/testsuite/gcc.target/riscv/attribute-17.c +index fc2f488a3ac..30928cb5b68 100644 +--- a/gcc/testsuite/gcc.target/riscv/attribute-17.c ++++ b/gcc/testsuite/gcc.target/riscv/attribute-17.c +@@ -3,4 +3,4 @@ + int foo() + { + } +-/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0\"" } } */ ++/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0\"" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/attribute-18.c b/gcc/testsuite/gcc.target/riscv/attribute-18.c +index eefd602103d..9f7199f331a 100644 +--- a/gcc/testsuite/gcc.target/riscv/attribute-18.c ++++ b/gcc/testsuite/gcc.target/riscv/attribute-18.c +@@ -1,4 +1,4 @@ + /* { dg-do compile } */ + /* { dg-options "-mriscv-attribute -march=rv64imafdc -mabi=lp64d -misa-spec=2.2" } */ + int foo() {} +-/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zaamo1p0_zalrsc1p0\"" } } */ ++/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0\"" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/pr110696.c b/gcc/testsuite/gcc.target/riscv/pr110696.c +index 08682a047e0..aae2afc6b28 100644 +--- a/gcc/testsuite/gcc.target/riscv/pr110696.c ++++ b/gcc/testsuite/gcc.target/riscv/pr110696.c +@@ -4,4 +4,4 @@ int foo() + { + } + +-/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0\"" } } */ ++/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0\"" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c +index dedcef9b353..b6b708f1a58 100644 +--- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c ++++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* { dg-options "-O1 -march=rv64gcv_zfh_zca_zcmp -mabi=lp64d -fno-shrink-wrap-separate" } */ ++/* { dg-options "-O1 -march=rv64gv_zfh_zca_zcmp -mabi=lp64d -fno-shrink-wrap-separate" } */ + /* { dg-final { check-function-bodies "**" "" } } */ + + #include +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c +index 14fb2c400a4..5f8f96f86a9 100644 +--- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c ++++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* { dg-options "-O1 -march=rv64gcv_zfh_zca_zcmp -mabi=lp64d -fno-shrink-wrap-separate" } */ ++/* { dg-options "-O1 -march=rv64gv_zfh_zca_zcmp -mabi=lp64d -fno-shrink-wrap-separate" } */ + /* { dg-final { check-function-bodies "**" "" } } */ + + #include +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c +index faeb406498d..300d87324c6 100644 +--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c ++++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c +@@ -54,5 +54,5 @@ test_3 (int *a, int *b, int *out, unsigned count) + out[i] = a[i] + b[i]; + } + +-/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0\"" } } */ +-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */ ++/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0\"" } } */ ++/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c +index 38815ef5bd0..da7a44ba08a 100644 +--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c ++++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c +@@ -107,7 +107,7 @@ test_6 (_Float16 *a, _Float16 *b, _Float16 *out, unsigned count) + out[i] = a[i] + b[i]; + } + +-/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0\"" } } */ +-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */ +-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zbb1p0" } } */ +-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zfh1p0_zfhmin1p0" } } */ ++/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0\"" } } */ ++/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */ ++/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zbb1p0" } } */ ++/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zfh1p0_zfhmin1p0_zca1p0_zcd1p0" } } */ +-- +2.47.3 + diff --git a/1056-RISC-V-Implement-locality-for-__builtin_prefetch.patch b/1056-RISC-V-Implement-locality-for-__builtin_prefetch.patch new file mode 100644 index 0000000..1aff50e --- /dev/null +++ b/1056-RISC-V-Implement-locality-for-__builtin_prefetch.patch @@ -0,0 +1,124 @@ +From 5ec3b5f053b05cf90387585c7270a847735f014f Mon Sep 17 00:00:00 2001 +From: Monk Chiang +Date: Thu, 6 Jul 2023 14:05:17 +0800 +Subject: [PATCH 1056/1087] RISC-V: Implement locality for __builtin_prefetch + +commit bf26413fc4081dfd18b915580b35bdb71481327e upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +The patch add the Zihintntl instructions in the prefetch pattern. +Zicbop has prefetch instructions. Zihintntl has NTL instructions. +Insert NTL instructions before prefetch instruction, if target +has Zihintntl extension. + +gcc/ChangeLog: + + * config/riscv/riscv.cc (riscv_print_operand): Add 'L' letter + to print zihintntl instructions string. + * config/riscv/riscv.md (prefetch): Add zihintntl instructions. + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/prefetch-zicbop.c: New test. + * gcc.target/riscv/prefetch-zihintntl.c: New test. +--- + gcc/config/riscv/riscv.cc | 1 + + gcc/config/riscv/riscv.md | 10 +++++++--- + .../gcc.target/riscv/prefetch-zicbop.c | 20 +++++++++++++++++++ + .../gcc.target/riscv/prefetch-zihintntl.c | 20 +++++++++++++++++++ + 4 files changed, 48 insertions(+), 3 deletions(-) + create mode 100644 gcc/testsuite/gcc.target/riscv/prefetch-zicbop.c + create mode 100644 gcc/testsuite/gcc.target/riscv/prefetch-zihintntl.c + +diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc +index b6239c38582..87bd5a89b19 100644 +--- a/gcc/config/riscv/riscv.cc ++++ b/gcc/config/riscv/riscv.cc +@@ -6231,6 +6231,7 @@ riscv_asm_output_opcode (FILE *asm_out_file, const char *p) + 'A' Print the atomic operation suffix for memory model OP. + 'I' Print the LR suffix for memory model OP. + 'J' Print the SC suffix for memory model OP. ++ 'L' Print a non-temporal locality hints instruction. + 'z' Print x0 if OP is zero, otherwise print OP normally. + 'i' Print i if the operand is not a register. + 'S' Print shift-index of single-bit mask OP. +diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md +index 8c453ecbd05..0a98d862b5b 100644 +--- a/gcc/config/riscv/riscv.md ++++ b/gcc/config/riscv/riscv.md +@@ -3986,12 +3986,16 @@ + { + switch (INTVAL (operands[1])) + { +- case 0: return "prefetch.r\t%a0"; +- case 1: return "prefetch.w\t%a0"; ++ case 0: return TARGET_ZIHINTNTL ? "%L2prefetch.r\t%a0" : "prefetch.r\t%a0"; ++ case 1: return TARGET_ZIHINTNTL ? "%L2prefetch.w\t%a0" : "prefetch.w\t%a0"; + default: gcc_unreachable (); + } + } +- [(set_attr "type" "store")]) ++ [(set_attr "type" "store") ++ (set (attr "length") (if_then_else (and (match_test "TARGET_ZIHINTNTL") ++ (match_test "IN_RANGE (INTVAL (operands[2]), 0, 2)")) ++ (const_string "8") ++ (const_string "4")))]) + + (define_insn "riscv_prefetchi_" + [(unspec_volatile:X [(match_operand:X 0 "address_operand" "r") +diff --git a/gcc/testsuite/gcc.target/riscv/prefetch-zicbop.c b/gcc/testsuite/gcc.target/riscv/prefetch-zicbop.c +new file mode 100644 +index 00000000000..0faa120f1f7 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/prefetch-zicbop.c +@@ -0,0 +1,20 @@ ++/* { dg-do compile target { { rv64-*-*}}} */ ++/* { dg-options "-march=rv64gc_zicbop -mabi=lp64" } */ ++ ++void foo (char *p) ++{ ++ __builtin_prefetch (p, 0, 0); ++ __builtin_prefetch (p, 0, 1); ++ __builtin_prefetch (p, 0, 2); ++ __builtin_prefetch (p, 0, 3); ++ __builtin_prefetch (p, 1, 0); ++ __builtin_prefetch (p, 1, 1); ++ __builtin_prefetch (p, 1, 2); ++ __builtin_prefetch (p, 1, 3); ++} ++ ++/* { dg-final { scan-assembler-not "ntl.all\t" } } */ ++/* { dg-final { scan-assembler-not "ntl.pall\t" } } */ ++/* { dg-final { scan-assembler-not "ntl.p1\t" } } */ ++/* { dg-final { scan-assembler-times "prefetch.r" 4 } } */ ++/* { dg-final { scan-assembler-times "prefetch.w" 4 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/prefetch-zihintntl.c b/gcc/testsuite/gcc.target/riscv/prefetch-zihintntl.c +new file mode 100644 +index 00000000000..78a3afe6833 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/prefetch-zihintntl.c +@@ -0,0 +1,20 @@ ++/* { dg-do compile target { { rv64-*-*}}} */ ++/* { dg-options "-march=rv64gc_zicbop_zihintntl -mabi=lp64" } */ ++ ++void foo (char *p) ++{ ++ __builtin_prefetch (p, 0, 0); ++ __builtin_prefetch (p, 0, 1); ++ __builtin_prefetch (p, 0, 2); ++ __builtin_prefetch (p, 0, 3); ++ __builtin_prefetch (p, 1, 0); ++ __builtin_prefetch (p, 1, 1); ++ __builtin_prefetch (p, 1, 2); ++ __builtin_prefetch (p, 1, 3); ++} ++ ++/* { dg-final { scan-assembler-times "ntl.all" 2 } } */ ++/* { dg-final { scan-assembler-times "ntl.pall" 2 } } */ ++/* { dg-final { scan-assembler-times "ntl.p1" 2 } } */ ++/* { dg-final { scan-assembler-times "prefetch.r" 4 } } */ ++/* { dg-final { scan-assembler-times "prefetch.w" 4 } } */ +-- +2.47.3 + diff --git a/1057-RISC-V-Remove-configure-check-for-zabha.patch b/1057-RISC-V-Remove-configure-check-for-zabha.patch new file mode 100644 index 0000000..bc4958b --- /dev/null +++ b/1057-RISC-V-Remove-configure-check-for-zabha.patch @@ -0,0 +1,146 @@ +From f1a357d8be26891ab500050bdced6df24a737937 Mon Sep 17 00:00:00 2001 +From: Patrick O'Neill +Date: Mon, 29 Jul 2024 19:52:02 -0700 +Subject: [PATCH 1057/1087] RISC-V: Remove configure check for zabha + +commit c0af64af636a801850fc8fabee12635ec73daa22 upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +This patch removes the zabha configure check since it's not a breaking change +and updates the existing zaamo/zalrsc comment. + +gcc/ChangeLog: + + * common/config/riscv/riscv-common.cc + (riscv_subset_list::to_string): Remove zabha configure check + handling and clarify zaamo/zalrsc comment. + * config.in: Regenerate. + * configure: Regenerate. + * configure.ac: Remove zabha configure check. + +Signed-off-by: Patrick O'Neill +--- + gcc/common/config/riscv/riscv-common.cc | 12 +++------- + gcc/config.in | 6 ----- + gcc/configure | 31 ------------------------- + gcc/configure.ac | 5 ---- + 4 files changed, 3 insertions(+), 51 deletions(-) + +diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc +index 7e34bcd97fc..59a3bfae42a 100644 +--- a/gcc/common/config/riscv/riscv-common.cc ++++ b/gcc/common/config/riscv/riscv-common.cc +@@ -855,7 +855,6 @@ riscv_subset_list::to_string (bool version_p) const + + bool skip_zifencei = false; + bool skip_zaamo_zalrsc = false; +- bool skip_zabha = false; + bool skip_zicsr = false; + bool i2p0 = false; + +@@ -884,13 +883,11 @@ riscv_subset_list::to_string (bool version_p) const + skip_zifencei = true; + #endif + #ifndef HAVE_AS_MARCH_ZAAMO_ZALRSC +- /* Skip since binutils 2.42 and earlier don't recognize zaamo/zalrsc. */ ++ /* Skip since binutils 2.42 and earlier don't recognize zaamo/zalrsc. ++ Expanding 'a' to zaamo/zalrsc would otherwise break compilations ++ for users with an older version of binutils. */ + skip_zaamo_zalrsc = true; + #endif +-#ifndef HAVE_AS_MARCH_ZABHA +- /* Skip since binutils 2.42 and earlier don't recognize zabha. */ +- skip_zabha = true; +-#endif + + for (subset = m_head; subset != NULL; subset = subset->next) + { +@@ -908,9 +905,6 @@ riscv_subset_list::to_string (bool version_p) const + if (skip_zaamo_zalrsc && subset->name == "zalrsc") + continue; + +- if (skip_zabha && subset->name == "zabha") +- continue; +- + /* For !version_p, we only separate extension with underline for + multi-letter extension. */ + if (!first && +diff --git a/gcc/config.in b/gcc/config.in +index 557783b5a22..21a7e12376b 100644 +--- a/gcc/config.in ++++ b/gcc/config.in +@@ -635,12 +635,6 @@ + #endif + + +-/* Define if the assembler understands -march=rv*_zabha. */ +-#ifndef USED_FOR_TARGET +-#undef HAVE_AS_MARCH_ZABHA +-#endif +- +- + /* Define if the assembler understands -march=rv*_zifencei. */ + #ifndef USED_FOR_TARGET + #undef HAVE_AS_MARCH_ZIFENCEI +diff --git a/gcc/configure b/gcc/configure +index 764e8e21075..c0dd02ffff5 100755 +--- a/gcc/configure ++++ b/gcc/configure +@@ -31100,37 +31100,6 @@ if test $gcc_cv_as_riscv_march_zaamo_zalrsc = yes; then + + $as_echo "#define HAVE_AS_MARCH_ZAAMO_ZALRSC 1" >>confdefs.h + +-fi +- +- { $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for -march=rv32i_zabha support" >&5 +-$as_echo_n "checking assembler for -march=rv32i_zabha support... " >&6; } +-if ${gcc_cv_as_riscv_march_zabha+:} false; then : +- $as_echo_n "(cached) " >&6 +-else +- gcc_cv_as_riscv_march_zabha=no +- if test x$gcc_cv_as != x; then +- $as_echo '' > conftest.s +- if { ac_try='$gcc_cv_as $gcc_cv_as_flags -march=rv32i_zabha -o conftest.o conftest.s >&5' +- { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5 +- (eval $ac_try) 2>&5 +- ac_status=$? +- $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 +- test $ac_status = 0; }; } +- then +- gcc_cv_as_riscv_march_zabha=yes +- else +- echo "configure: failed program was" >&5 +- cat conftest.s >&5 +- fi +- rm -f conftest.o conftest.s +- fi +-fi +-{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_as_riscv_march_zabha" >&5 +-$as_echo "$gcc_cv_as_riscv_march_zabha" >&6; } +-if test $gcc_cv_as_riscv_march_zabha = yes; then +- +-$as_echo "#define HAVE_AS_MARCH_ZABHA 1" >>confdefs.h +- + fi + + ;; +diff --git a/gcc/configure.ac b/gcc/configure.ac +index 2a0f7440eaa..09ffd6bca3c 100644 +--- a/gcc/configure.ac ++++ b/gcc/configure.ac +@@ -5523,11 +5523,6 @@ configured with --enable-newlib-nano-formatted-io.]) + [-march=rv32i_zaamo_zalrsc],,, + [AC_DEFINE(HAVE_AS_MARCH_ZAAMO_ZALRSC, 1, + [Define if the assembler understands -march=rv*_zaamo_zalrsc.])]) +- gcc_GAS_CHECK_FEATURE([-march=rv32i_zabha support], +- gcc_cv_as_riscv_march_zabha, +- [-march=rv32i_zabha],,, +- [AC_DEFINE(HAVE_AS_MARCH_ZABHA, 1, +- [Define if the assembler understands -march=rv*_zabha.])]) + ;; + loongarch*-*-*) + gcc_GAS_CHECK_FEATURE([.dtprelword support], +-- +2.47.3 + diff --git a/1058-RISC-V-Add-basic-support-for-the-Zacas-extension.patch b/1058-RISC-V-Add-basic-support-for-the-Zacas-extension.patch new file mode 100644 index 0000000..823bbb0 --- /dev/null +++ b/1058-RISC-V-Add-basic-support-for-the-Zacas-extension.patch @@ -0,0 +1,1564 @@ +From d58eac0e6b0b88074b8622184b4fec976b2c34a2 Mon Sep 17 00:00:00 2001 +From: Gianluca Guida +Date: Mon, 29 Jul 2024 15:13:46 -0700 +Subject: [PATCH 1058/1087] RISC-V: Add basic support for the Zacas extension + +commit 11c2453a16b725b7fb67778e1ab4636a51a1217d upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +This patch adds support for amocas.{b|h|w|d}. Support for amocas.q +(64/128 bit cas for rv32/64) will be added in a future patch. + +Extension: https://github.com/riscv/riscv-zacas +Ratification: https://jira.riscv.org/browse/RVS-680 + +gcc/ChangeLog: + + * common/config/riscv/riscv-common.cc: Add zacas extension. + * config/riscv/arch-canonicalize: Make zacas imply zaamo. + * config/riscv/riscv.opt: Add zacas. + * config/riscv/sync.md (zacas_atomic_cas_value): New pattern. + (atomic_compare_and_swap): Use new pattern for compare-and-swap ops. + (zalrsc_atomic_cas_value_strong): Rename atomic_cas_value_strong. + * doc/sourcebuild.texi: Add Zacas documentation. + +gcc/testsuite/ChangeLog: + + * lib/target-supports.exp: Add zacas testsuite infra support. + * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire-release.c: + Remove zacas to continue to test the lr/sc pairs. + * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire.c: Ditto. + * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-consume.c: Ditto. + * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-relaxed.c: Ditto. + * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-release.c: Ditto. + * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst-relaxed.c: Ditto. + * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst.c: Ditto. + * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire-release.c: Ditto. + * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire.c: Ditto. + * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-consume.c: Ditto. + * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-relaxed.c: Ditto. + * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-release.c: Ditto. + * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst-relaxed.c: Ditto. + * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst.c: Ditto. + * gcc.target/riscv/amo/zabha-zacas-preferred-over-zalrsc.c: New test. + * gcc.target/riscv/amo/zacas-char-requires-zabha.c: New test. + * gcc.target/riscv/amo/zacas-char-requires-zacas.c: New test. + * gcc.target/riscv/amo/zacas-preferred-over-zalrsc.c: New test. + * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-acq-rel.c: New test. + * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-acquire.c: New test. + * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-relaxed.c: New test. + * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-release.c: New test. + * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-seq-cst.c: New test. + * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-compatability-mapping-no-fence.c: + New test. + * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-compatability-mapping.cc: New test. + * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-acq-rel.c: New test. + * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-acquire.c: New test. + * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-relaxed.c: New test. + * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-release.c: New test. + * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-seq-cst.c: New test. + * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-acq-rel.c: New test. + * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-acquire.c: New test. + * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-relaxed.c: New test. + * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-release.c: New test. + * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-seq-cst.c: New test. + * gcc.target/riscv/amo/zacas-ztso-compare-exchange-char-seq-cst.c: New test. + * gcc.target/riscv/amo/zacas-ztso-compare-exchange-char.c: New test. + * gcc.target/riscv/amo/zacas-ztso-compare-exchange-compatability-mapping-no-fence.c: + New test. + * gcc.target/riscv/amo/zacas-ztso-compare-exchange-compatability-mapping.cc: New test. + * gcc.target/riscv/amo/zacas-ztso-compare-exchange-int-seq-cst.c: New test. + * gcc.target/riscv/amo/zacas-ztso-compare-exchange-int.c: New test. + * gcc.target/riscv/amo/zacas-ztso-compare-exchange-short-seq-cst.c: New test. + * gcc.target/riscv/amo/zacas-ztso-compare-exchange-short.c: New test. + +Co-authored-by: Patrick O'Neill +Tested-by: Andrea Parri +Signed-Off-By: Gianluca Guida +--- + gcc/common/config/riscv/riscv-common.cc | 3 + + gcc/config/riscv/arch-canonicalize | 1 + + gcc/config/riscv/riscv.opt | 2 + + gcc/config/riscv/sync.md | 111 ++++++++++++++++-- + gcc/doc/sourcebuild.texi | 10 ++ + .../amo/zabha-zacas-preferred-over-zalrsc.c | 21 ++++ + .../riscv/amo/zacas-char-requires-zabha.c | 17 +++ + .../riscv/amo/zacas-char-requires-zacas.c | 17 +++ + .../riscv/amo/zacas-preferred-over-zalrsc.c | 20 ++++ + ...acas-rvwmo-compare-exchange-char-acq-rel.c | 20 ++++ + ...acas-rvwmo-compare-exchange-char-acquire.c | 20 ++++ + ...acas-rvwmo-compare-exchange-char-relaxed.c | 20 ++++ + ...acas-rvwmo-compare-exchange-char-release.c | 20 ++++ + ...acas-rvwmo-compare-exchange-char-seq-cst.c | 20 ++++ + ...-exchange-compatability-mapping-no-fence.c | 30 +++++ + ...-compare-exchange-compatability-mapping.cc | 58 +++++++++ + ...zacas-rvwmo-compare-exchange-int-acq-rel.c | 19 +++ + ...zacas-rvwmo-compare-exchange-int-acquire.c | 19 +++ + ...zacas-rvwmo-compare-exchange-int-relaxed.c | 19 +++ + ...zacas-rvwmo-compare-exchange-int-release.c | 19 +++ + ...zacas-rvwmo-compare-exchange-int-seq-cst.c | 19 +++ + ...cas-rvwmo-compare-exchange-short-acq-rel.c | 20 ++++ + ...cas-rvwmo-compare-exchange-short-acquire.c | 20 ++++ + ...cas-rvwmo-compare-exchange-short-relaxed.c | 20 ++++ + ...cas-rvwmo-compare-exchange-short-release.c | 20 ++++ + ...cas-rvwmo-compare-exchange-short-seq-cst.c | 20 ++++ + ...zacas-ztso-compare-exchange-char-seq-cst.c | 19 +++ + .../amo/zacas-ztso-compare-exchange-char.c | 49 ++++++++ + ...-exchange-compatability-mapping-no-fence.c | 30 +++++ + ...-compare-exchange-compatability-mapping.cc | 58 +++++++++ + .../zacas-ztso-compare-exchange-int-seq-cst.c | 18 +++ + .../amo/zacas-ztso-compare-exchange-int.c | 48 ++++++++ + ...acas-ztso-compare-exchange-short-seq-cst.c | 19 +++ + .../amo/zacas-ztso-compare-exchange-short.c | 49 ++++++++ + ...wmo-compare-exchange-int-acquire-release.c | 1 + + ...alrsc-rvwmo-compare-exchange-int-acquire.c | 1 + + ...alrsc-rvwmo-compare-exchange-int-consume.c | 1 + + ...alrsc-rvwmo-compare-exchange-int-relaxed.c | 1 + + ...alrsc-rvwmo-compare-exchange-int-release.c | 1 + + ...wmo-compare-exchange-int-seq-cst-relaxed.c | 1 + + ...alrsc-rvwmo-compare-exchange-int-seq-cst.c | 1 + + ...tso-compare-exchange-int-acquire-release.c | 1 + + ...zalrsc-ztso-compare-exchange-int-acquire.c | 1 + + ...zalrsc-ztso-compare-exchange-int-consume.c | 1 + + ...zalrsc-ztso-compare-exchange-int-relaxed.c | 1 + + ...zalrsc-ztso-compare-exchange-int-release.c | 1 + + ...tso-compare-exchange-int-seq-cst-relaxed.c | 1 + + ...zalrsc-ztso-compare-exchange-int-seq-cst.c | 1 + + gcc/testsuite/lib/target-supports.exp | 25 +++- + 49 files changed, 901 insertions(+), 13 deletions(-) + create mode 100644 gcc/testsuite/gcc.target/riscv/amo/zabha-zacas-preferred-over-zalrsc.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo/zacas-char-requires-zabha.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo/zacas-char-requires-zacas.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo/zacas-preferred-over-zalrsc.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-acq-rel.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-acquire.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-relaxed.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-release.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-seq-cst.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-compatability-mapping-no-fence.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-compatability-mapping.cc + create mode 100644 gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-acq-rel.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-acquire.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-relaxed.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-release.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-seq-cst.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-acq-rel.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-acquire.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-relaxed.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-release.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-seq-cst.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-char-seq-cst.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-char.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-compatability-mapping-no-fence.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-compatability-mapping.cc + create mode 100644 gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-int-seq-cst.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-int.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-short-seq-cst.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-short.c + +diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc +index 59a3bfae42a..e13f0922b7f 100644 +--- a/gcc/common/config/riscv/riscv-common.cc ++++ b/gcc/common/config/riscv/riscv-common.cc +@@ -95,6 +95,7 @@ static const riscv_implied_info_t riscv_implied_info[] = + }}, + + {"zabha", "zaamo"}, ++ {"zacas", "zaamo"}, + + {"b", "zba"}, + {"b", "zbb"}, +@@ -283,6 +284,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] = + {"zaamo", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zalrsc", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zabha", ISA_SPEC_CLASS_NONE, 1, 0}, ++ {"zacas", ISA_SPEC_CLASS_NONE, 1, 0}, + + {"zba", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zbb", ISA_SPEC_CLASS_NONE, 1, 0}, +@@ -1584,6 +1586,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = + {"zaamo", &gcc_options::x_riscv_za_subext, MASK_ZAAMO}, + {"zalrsc", &gcc_options::x_riscv_za_subext, MASK_ZALRSC}, + {"zabha", &gcc_options::x_riscv_za_subext, MASK_ZABHA}, ++ {"zacas", &gcc_options::x_riscv_za_subext, MASK_ZACAS}, + + {"zba", &gcc_options::x_riscv_zb_subext, MASK_ZBA}, + {"zbb", &gcc_options::x_riscv_zb_subext, MASK_ZBB}, +diff --git a/gcc/config/riscv/arch-canonicalize b/gcc/config/riscv/arch-canonicalize +index 2ea514dd986..35e0f46b6bd 100755 +--- a/gcc/config/riscv/arch-canonicalize ++++ b/gcc/config/riscv/arch-canonicalize +@@ -43,6 +43,7 @@ IMPLIED_EXT = { + + "a" : ["zaamo", "zalrsc"], + "zabha" : ["zaamo"], ++ "zacas" : ["zaamo"], + + "f" : ["zicsr"], + "b" : ["zba", "zbb", "zbs"], +diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt +index 8a655e9ab63..a13c2ff53a0 100644 +--- a/gcc/config/riscv/riscv.opt ++++ b/gcc/config/riscv/riscv.opt +@@ -264,6 +264,8 @@ Mask(ZALRSC) Var(riscv_za_subext) + + Mask(ZABHA) Var(riscv_za_subext) + ++Mask(ZACAS) Var(riscv_za_subext) ++ + Mask(ZA64RS) Var(riscv_za_subext) + + Mask(ZA128RS) Var(riscv_za_subext) +diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md +index 6128b0ebc4e..2bd1775b133 100644 +--- a/gcc/config/riscv/sync.md ++++ b/gcc/config/riscv/sync.md +@@ -504,7 +504,7 @@ + + ; Atomic CAS ops + +-(define_insn "atomic_cas_value_strong" ++(define_insn "zalrsc_atomic_cas_value_strong" + [(set (match_operand:GPR 0 "register_operand" "=&r") + (match_operand:GPR 1 "memory_operand" "+A")) + (set (match_dup 1) +@@ -531,16 +531,48 @@ + [(set_attr "type" "multi") + (set (attr "length") (const_int 16))]) + ++;; Implement compare_exchange with a conservative leading fence when ++;; model_failure is seq_cst. ++;; This allows us to be compatible with the ISA manual Table A.6 and Table A.7 ++;; (A6C and A7). ++;; More details: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/444 ++(define_insn "zacas_atomic_cas_value_strong" ++ [(set (match_operand:GPR 0 "register_operand" "=&r") ;; val output ++ (match_operand:GPR 1 "memory_operand" "+A")) ;; memory ++ (set (match_dup 1) ++ (unspec_volatile:GPR [(match_operand:GPR 2 "register_operand" "0") ;; expected val ++ (match_operand:GPR 3 "reg_or_0_operand" "rJ") ;; desired val ++ (match_operand:SI 4 "const_int_operand") ;; mod_s ++ (match_operand:SI 5 "const_int_operand")] ;; mod_f ++ UNSPEC_COMPARE_AND_SWAP))] ++ "TARGET_ZACAS" ++ { ++ enum memmodel model_success = (enum memmodel) INTVAL (operands[4]); ++ enum memmodel model_failure = (enum memmodel) INTVAL (operands[5]); ++ /* Find the union of the two memory models so we can satisfy both success ++ and failure memory models. */ ++ operands[4] = GEN_INT (riscv_union_memmodels (model_success, model_failure)); ++ ++ if (model_failure == MEMMODEL_SEQ_CST) ++ return "fence\trw,rw\;" ++ "amocas.%A4\t%0,%z3,%1"; ++ else ++ return "amocas.%A4\t%0,%z3,%1"; ++ } ++ [(set_attr "type" "atomic") ++ (set (attr "length") ++ (symbol_ref "is_mm_seq_cst(memmodel_from_int(INTVAL (operands[5]))) ? 8 : 4"))]) ++ + (define_expand "atomic_compare_and_swap" + [(match_operand:SI 0 "register_operand" "") ;; bool output + (match_operand:GPR 1 "register_operand" "") ;; val output + (match_operand:GPR 2 "memory_operand" "") ;; memory +- (match_operand:GPR 3 "reg_or_0_operand" "") ;; expected value ++ (match_operand:GPR 3 "register_operand" "") ;; expected value + (match_operand:GPR 4 "reg_or_0_operand" "") ;; desired value + (match_operand:SI 5 "const_int_operand" "") ;; is_weak + (match_operand:SI 6 "const_int_operand" "") ;; mod_s + (match_operand:SI 7 "const_int_operand" "")] ;; mod_f +- "TARGET_ZALRSC" ++ "TARGET_ZALRSC || TARGET_ZACAS" + { + if (word_mode != mode && operands[3] != const0_rtx) + { +@@ -551,9 +583,20 @@ + operands[3] = simplify_gen_subreg (mode, tmp0, word_mode, 0); + } + +- emit_insn (gen_atomic_cas_value_strong (operands[1], operands[2], +- operands[3], operands[4], +- operands[6], operands[7])); ++ if (TARGET_ZACAS) ++ emit_insn (gen_zacas_atomic_cas_value_strong (operands[1], ++ operands[2], ++ operands[3], ++ operands[4], ++ operands[6], ++ operands[7])); ++ else ++ emit_insn (gen_zalrsc_atomic_cas_value_strong (operands[1], ++ operands[2], ++ operands[3], ++ operands[4], ++ operands[6], ++ operands[7])); + + rtx compare = operands[1]; + if (operands[3] != const0_rtx) +@@ -574,20 +617,64 @@ + DONE; + }) + ++;; Implement compare_exchange with a conservative leading fence when ++;; model_failure is seq_cst. ++;; This allows us to be compatible with the ISA manual Table A.6 and Table A.7 ++;; (A6C and A7). ++;; More details: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/444 ++(define_insn "zacas_atomic_cas_value_strong" ++ [(set (match_operand:SHORT 0 "register_operand" "=&r") ;; val output ++ (match_operand:SHORT 1 "memory_operand" "+A")) ;; memory ++ (set (match_dup 1) ++ (unspec_volatile:SHORT [(match_operand:SHORT 2 "register_operand" "0") ;; expected_val ++ (match_operand:SHORT 3 "register_operand" "rJ") ;; desired_val ++ (match_operand:SI 4 "const_int_operand") ;; mod_s ++ (match_operand:SI 5 "const_int_operand")] ;; mod_f ++ UNSPEC_COMPARE_AND_SWAP))] ++ "TARGET_ZACAS && TARGET_ZABHA" ++ { ++ enum memmodel model_success = (enum memmodel) INTVAL (operands[4]); ++ enum memmodel model_failure = (enum memmodel) INTVAL (operands[5]); ++ /* Find the union of the two memory models so we can satisfy both success ++ and failure memory models. */ ++ operands[4] = GEN_INT (riscv_union_memmodels (model_success, model_failure)); ++ ++ if (model_failure == MEMMODEL_SEQ_CST) ++ return "fence\trw,rw\;" ++ "amocas.%A4\t%0,%z3,%1"; ++ else ++ return "amocas.%A4\t%0,%z3,%1"; ++ } ++ [(set_attr "type" "atomic") ++ (set (attr "length") ++ (symbol_ref "is_mm_seq_cst(memmodel_from_int(INTVAL (operands[5]))) ? 8 : 4"))]) ++ + (define_expand "atomic_compare_and_swap" + [(match_operand:SI 0 "register_operand") ;; bool output + (match_operand:SHORT 1 "register_operand") ;; val output + (match_operand:SHORT 2 "memory_operand") ;; memory +- (match_operand:SHORT 3 "reg_or_0_operand") ;; expected value ++ (match_operand:SHORT 3 "register_operand") ;; expected value + (match_operand:SHORT 4 "reg_or_0_operand") ;; desired value + (match_operand:SI 5 "const_int_operand") ;; is_weak + (match_operand:SI 6 "const_int_operand") ;; mod_s + (match_operand:SI 7 "const_int_operand")] ;; mod_f +- "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC" ++ "(TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC) || (TARGET_ZACAS && TARGET_ZABHA)" + { +- emit_insn (gen_atomic_cas_value_strong (operands[1], operands[2], +- operands[3], operands[4], +- operands[6], operands[7])); ++ ++ if (TARGET_ZACAS && TARGET_ZABHA) ++ emit_insn (gen_zacas_atomic_cas_value_strong (operands[1], ++ operands[2], ++ operands[3], ++ operands[4], ++ operands[6], ++ operands[7])); ++ else ++ emit_insn (gen_zalrsc_atomic_cas_value_strong (operands[1], ++ operands[2], ++ operands[3], ++ operands[4], ++ operands[6], ++ operands[7])); + + rtx val = gen_reg_rtx (SImode); + if (operands[1] != const0_rtx) +@@ -620,7 +707,7 @@ + DONE; + }) + +-(define_expand "atomic_cas_value_strong" ++(define_expand "zalrsc_atomic_cas_value_strong" + [(match_operand:SHORT 0 "register_operand") ;; val output + (match_operand:SHORT 1 "memory_operand") ;; memory + (match_operand:SHORT 2 "reg_or_0_operand") ;; expected value +diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi +index b7b98b1bd10..d26356bcdaf 100644 +--- a/gcc/doc/sourcebuild.texi ++++ b/gcc/doc/sourcebuild.texi +@@ -2524,6 +2524,9 @@ Test target architecture has support for the zaamo extension. + @item riscv_zabha + Test target architecture has support for the zabha extension. + ++@item riscv_zacas ++Test target architecture has support for the zacas extension. ++ + @item riscv_zalrsc + Test target architecture has support for the zalrsc extension. + +@@ -3292,6 +3295,9 @@ Add the zaamo extension to the -march string on RISC-V targets. + @item riscv_zabha + Add the zabha extension to the -march string on RISC-V targets. + ++@item riscv_zacas ++Add the zacas extension to the -march string on RISC-V targets. ++ + @item riscv_zalrsc + Add the zalrsc extension to the -march string on RISC-V targets. + +@@ -3339,6 +3345,10 @@ extension is present downgrade it to zalrsc. + Remove the zabha extension and implied zaamo extension from the -march string + on RISC-V. + ++@item riscv_zacas ++Remove the zacas extension and implied zaamo extension from the -march string ++on RISC-V. ++ + @item riscv_zalrsc + Remove the zalrsc extension from the -march string on RISC-V. If the 'A' + extension is present downgrade it to zaamo. +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zabha-zacas-preferred-over-zalrsc.c b/gcc/testsuite/gcc.target/riscv/amo/zabha-zacas-preferred-over-zalrsc.c +new file mode 100644 +index 00000000000..a06e195c6d4 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo/zabha-zacas-preferred-over-zalrsc.c +@@ -0,0 +1,21 @@ ++/* { dg-do compile } */ ++/* Ensure that AMO ops are emitted for subword cas when both zalrsc and ++ zacas/zabha are enabled. */ ++/* { dg-options "-O3" } */ ++/* { dg-add-options riscv_zalrsc } */ ++/* { dg-add-options riscv_zacas } */ ++/* { dg-add-options riscv_zabha } */ ++/* { dg-final { scan-assembler-not "\tlr\.w" } } */ ++/* { dg-final { scan-assembler-not "\tsc\.w" } } */ ++/* { dg-final { scan-assembler-times "amocas\.b\t" 2 } } */ ++ ++ ++void atomic_compare_exchange_weak_char_relaxed (char *bar, char *baz, char qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 0, __ATOMIC_RELAXED, __ATOMIC_RELAXED); ++} ++ ++void atomic_compare_exchange_strong_char_relaxed (char *bar, char *baz, char qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 1, __ATOMIC_RELAXED, __ATOMIC_RELAXED); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zacas-char-requires-zabha.c b/gcc/testsuite/gcc.target/riscv/amo/zacas-char-requires-zabha.c +new file mode 100644 +index 00000000000..c7d6e7c578b +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-char-requires-zabha.c +@@ -0,0 +1,17 @@ ++/* { dg-do compile } */ ++/* Ensure subword zacas is not emitted unless both zacas and zabha are ++ present. */ ++/* { dg-options "-O3" } */ ++/* { dg-add-options riscv_zacas } */ ++/* { dg-remove-options riscv_zabha } */ ++/* { dg-remove-options riscv_zalrsc } */ ++/* { dg-final { scan-assembler "\tcall\t" } } */ ++/* { dg-final { scan-assembler-not "\tlr\.w" } } */ ++/* { dg-final { scan-assembler-not "\tsc\.w" } } */ ++/* { dg-final { scan-assembler-not "amocas\.b\t" } } */ ++ ++ ++void atomic_compare_exchange_char_relaxed (char *bar, char *baz, char qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 1, __ATOMIC_RELAXED, __ATOMIC_RELAXED); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zacas-char-requires-zacas.c b/gcc/testsuite/gcc.target/riscv/amo/zacas-char-requires-zacas.c +new file mode 100644 +index 00000000000..d0cf14432fe +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-char-requires-zacas.c +@@ -0,0 +1,17 @@ ++/* { dg-do compile } */ ++/* Ensure subword zacas is not emitted unless both zacas and zabha are ++ present. */ ++/* { dg-options "-O3" } */ ++/* { dg-add-options riscv_zabha } */ ++/* { dg-remove-options riscv_zacas } */ ++/* { dg-remove-options riscv_zalrsc } */ ++/* { dg-final { scan-assembler "\tcall\t" } } */ ++/* { dg-final { scan-assembler-not "\tlr\.w" } } */ ++/* { dg-final { scan-assembler-not "\tsc\.w" } } */ ++/* { dg-final { scan-assembler-not "amocas\.b\t" } } */ ++ ++ ++void atomic_compare_exchange_char_relaxed (char *bar, char *baz, char qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 1, __ATOMIC_RELAXED, __ATOMIC_RELAXED); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zacas-preferred-over-zalrsc.c b/gcc/testsuite/gcc.target/riscv/amo/zacas-preferred-over-zalrsc.c +new file mode 100644 +index 00000000000..9a995cca37f +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-preferred-over-zalrsc.c +@@ -0,0 +1,20 @@ ++/* { dg-do compile } */ ++/* Ensure that AMO ops are emitted for subword cas when both zalrsc and ++ zacas/zabha are enabled. */ ++/* { dg-options "-O3" } */ ++/* { dg-add-options riscv_zalrsc } */ ++/* { dg-add-options riscv_zacas } */ ++/* { dg-final { scan-assembler-not "\tlr\.w" } } */ ++/* { dg-final { scan-assembler-not "\tsc\.w" } } */ ++/* { dg-final { scan-assembler-times "amocas\.w\t" 2 } } */ ++ ++ ++void atomic_compare_exchange_weak_int_relaxed (int *bar, int *baz, int qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 0, __ATOMIC_RELAXED, __ATOMIC_RELAXED); ++} ++ ++void atomic_compare_exchange_strong_int_relaxed (int *bar, int *baz, int qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 1, __ATOMIC_RELAXED, __ATOMIC_RELAXED); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-acq-rel.c b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-acq-rel.c +new file mode 100644 +index 00000000000..b76385b4d26 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-acq-rel.c +@@ -0,0 +1,20 @@ ++/* Verify that atomic op mappings match the PSABI doc's recommended mapping. */ ++/* { dg-do compile } */ ++/* { dg-options "-O3" } */ ++/* { dg-add-options riscv_zabha } */ ++/* { dg-add-options riscv_zacas } */ ++/* { dg-remove-options riscv_ztso } */ ++/* { dg-final { scan-assembler-not "\tlr\.w" } } */ ++/* { dg-final { scan-assembler-not "\tsc\.w" } } */ ++/* { dg-final { scan-assembler-times "amocas\.b\.aqrl\t" 2 } } */ ++ ++ ++void atomic_compare_exchange_weak_char_acq_rel (char *bar, char *baz, char qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 0, __ATOMIC_ACQ_REL, __ATOMIC_RELAXED); ++} ++ ++void atomic_compare_exchange_strong_char_acq_rel (char *bar, char *baz, char qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 1, __ATOMIC_ACQ_REL, __ATOMIC_RELAXED); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-acquire.c b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-acquire.c +new file mode 100644 +index 00000000000..62ecf7b5fff +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-acquire.c +@@ -0,0 +1,20 @@ ++/* Verify that atomic op mappings match the PSABI doc's recommended mapping. */ ++/* { dg-do compile } */ ++/* { dg-options "-O3" } */ ++/* { dg-add-options riscv_zabha } */ ++/* { dg-add-options riscv_zacas } */ ++/* { dg-remove-options riscv_ztso } */ ++/* { dg-final { scan-assembler-not "\tlr\.w" } } */ ++/* { dg-final { scan-assembler-not "\tsc\.w" } } */ ++/* { dg-final { scan-assembler-times "amocas\.b\.aq\t" 2 } } */ ++ ++ ++void atomic_compare_exchange_weak_char_acquire (char *bar, char *baz, char qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 0, __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE); ++} ++ ++void atomic_compare_exchange_strong_char_acquire (char *bar, char *baz, char qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 1, __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-relaxed.c b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-relaxed.c +new file mode 100644 +index 00000000000..21c960c893b +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-relaxed.c +@@ -0,0 +1,20 @@ ++/* Verify that atomic op mappings match the PSABI doc's recommended mapping. */ ++/* { dg-do compile } */ ++/* { dg-options "-O3" } */ ++/* { dg-add-options riscv_zabha } */ ++/* { dg-add-options riscv_zacas } */ ++/* { dg-remove-options riscv_ztso } */ ++/* { dg-final { scan-assembler-not "\tlr\.w" } } */ ++/* { dg-final { scan-assembler-not "\tsc\.w" } } */ ++/* { dg-final { scan-assembler-times "amocas\.b\t" 2 } } */ ++ ++ ++void atomic_compare_exchange_weak_char_relaxed (char *bar, char *baz, char qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 0, __ATOMIC_RELAXED, __ATOMIC_RELAXED); ++} ++ ++void atomic_compare_exchange_strong_char_relaxed (char *bar, char *baz, char qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 1, __ATOMIC_RELAXED, __ATOMIC_RELAXED); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-release.c b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-release.c +new file mode 100644 +index 00000000000..6b4083376ee +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-release.c +@@ -0,0 +1,20 @@ ++/* Verify that atomic op mappings match the PSABI doc's recommended mapping. */ ++/* { dg-do compile } */ ++/* { dg-options "-O3" } */ ++/* { dg-add-options riscv_zabha } */ ++/* { dg-add-options riscv_zacas } */ ++/* { dg-remove-options riscv_ztso } */ ++/* { dg-final { scan-assembler-not "\tlr\.w" } } */ ++/* { dg-final { scan-assembler-not "\tsc\.w" } } */ ++/* { dg-final { scan-assembler-times "amocas\.b\.rl\t" 2 } } */ ++ ++ ++void atomic_compare_exchange_weak_char_release (char *bar, char *baz, char qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 0, __ATOMIC_RELEASE, __ATOMIC_RELAXED); ++} ++ ++void atomic_compare_exchange_strong_char_release (char *bar, char *baz, char qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 1, __ATOMIC_RELEASE, __ATOMIC_RELAXED); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-seq-cst.c b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-seq-cst.c +new file mode 100644 +index 00000000000..289bdf44e9f +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-seq-cst.c +@@ -0,0 +1,20 @@ ++/* Verify that atomic op mappings match the PSABI doc's recommended mapping. */ ++/* { dg-do compile } */ ++/* { dg-options "-O3" } */ ++/* { dg-add-options riscv_zabha } */ ++/* { dg-add-options riscv_zacas } */ ++/* { dg-remove-options riscv_ztso } */ ++/* { dg-final { scan-assembler-not "\tlr\.w" } } */ ++/* { dg-final { scan-assembler-not "\tsc\.w" } } */ ++/* { dg-final { scan-assembler-times "amocas\.b\.aqrl\t" 2 } } */ ++ ++ ++void atomic_compare_exchange_weak_char_seq_cst (char *bar, char *baz, char qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 0, __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST); ++} ++ ++void atomic_compare_exchange_strong_char_seq_cst (char *bar, char *baz, char qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 1, __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-compatability-mapping-no-fence.c b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-compatability-mapping-no-fence.c +new file mode 100644 +index 00000000000..99fd7577a48 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-compatability-mapping-no-fence.c +@@ -0,0 +1,30 @@ ++/* ++** Verify that atomic op mappings match the PSABI doc's recommended mapping. ++** compare_exchange ops without a seq_cst failure ordering do *not* need a ++** leading fence. ++*/ ++/* { dg-do compile } */ ++/* { dg-options "-O3" } */ ++/* { dg-add-options riscv_zacas } */ ++/* { dg-remove-options riscv_ztso } */ ++/* { dg-final { scan-assembler-not "\tfence" } } */ ++ ++void atomic_compare_exchange_weak_int_seq_cst_relaxed (int *bar, int *baz, int qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 0, __ATOMIC_SEQ_CST, __ATOMIC_RELAXED); ++} ++ ++void atomic_compare_exchange_weak_int_seq_cst_acquire (int *bar, int *baz, int qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 0, __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE); ++} ++ ++void atomic_compare_exchange_strong_int_seq_cst_relaxed (int *bar, int *baz, int qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 1, __ATOMIC_SEQ_CST, __ATOMIC_RELAXED); ++} ++ ++void atomic_compare_exchange_strong_int_seq_cst_acquire (int *bar, int *baz, int qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 1, __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-compatability-mapping.cc b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-compatability-mapping.cc +new file mode 100644 +index 00000000000..c8d81299197 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-compatability-mapping.cc +@@ -0,0 +1,58 @@ ++/* ++** Verify that atomic op mappings match the PSABI doc's recommended mapping. ++** compare_exchange ops with seq_cst failure ordering need a leading fence ++** to remain compatible with Table A.6 (A6C). ++*/ ++/* { dg-do compile } */ ++/* { dg-options "-O3 -std=c++17" } */ ++/* { dg-add-options riscv_zacas } */ ++/* { dg-remove-options riscv_ztso } */ ++/* { dg-final { check-function-bodies "**" "" } } */ ++ ++/* ++** atomic_compare_exchange_weak_int_relaxed_seq_cst: ++** ... ++** fence\trw,rw ++** amoadd\.w\.aqrl\t[atx][0-9]+,a2,0\(a0\) ++** ... ++*/ ++void atomic_compare_exchange_weak_int_relaxed_seq_cst (int *bar, int *baz, int qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 0, __ATOMIC_RELAXED, __ATOMIC_SEQ_CST); ++} ++ ++/* ++** atomic_compare_exchange_weak_int_seq_cst_seq_cst: ++** ... ++** fence\trw,rw ++** amoadd\.w\.aqrl\t[atx][0-9]+,a2,0\(a0\) ++** ... ++*/ ++void atomic_compare_exchange_weak_int_seq_cst_seq_cst (int *bar, int *baz, int qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 0, __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST); ++} ++ ++/* ++** atomic_compare_exchange_strong_int_relaxed_seq_cst: ++** ... ++** fence\trw,rw ++** amoadd\.w\.aqrl\t[atx][0-9]+,a2,0\(a0\) ++** ... ++*/ ++void atomic_compare_exchange_strong_int_relaxed_seq_cst (int *bar, int *baz, int qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 1, __ATOMIC_RELAXED, __ATOMIC_SEQ_CST); ++} ++ ++/* ++** atomic_compare_exchange_strong_int_seq_cst_seq_cst: ++** ... ++** fence\trw,rw ++** amoadd\.w\.aqrl\t[atx][0-9]+,a2,0\(a0\) ++** ... ++*/ ++void atomic_compare_exchange_strong_int_seq_cst_seq_cst (int *bar, int *baz, int qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 1, __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-acq-rel.c b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-acq-rel.c +new file mode 100644 +index 00000000000..1b55c934962 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-acq-rel.c +@@ -0,0 +1,19 @@ ++/* Verify that atomic op mappings match the PSABI doc's recommended mapping. */ ++/* { dg-do compile } */ ++/* { dg-options "-O3" } */ ++/* { dg-add-options riscv_zacas } */ ++/* { dg-remove-options riscv_ztso } */ ++/* { dg-final { scan-assembler-not "\tlr\.w" } } */ ++/* { dg-final { scan-assembler-not "\tsc\.w" } } */ ++/* { dg-final { scan-assembler-times "amocas\.w\.aqrl\t" 2 } } */ ++ ++ ++void atomic_compare_exchange_weak_int_acq_rel (int *bar, int *baz, int qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 0, __ATOMIC_ACQ_REL, __ATOMIC_RELAXED); ++} ++ ++void atomic_compare_exchange_strong_int_acq_rel (int *bar, int *baz, int qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 1, __ATOMIC_ACQ_REL, __ATOMIC_RELAXED); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-acquire.c b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-acquire.c +new file mode 100644 +index 00000000000..8182360f244 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-acquire.c +@@ -0,0 +1,19 @@ ++/* Verify that atomic op mappings match the PSABI doc's recommended mapping. */ ++/* { dg-do compile } */ ++/* { dg-options "-O3" } */ ++/* { dg-add-options riscv_zacas } */ ++/* { dg-remove-options riscv_ztso } */ ++/* { dg-final { scan-assembler-not "\tlr\.w" } } */ ++/* { dg-final { scan-assembler-not "\tsc\.w" } } */ ++/* { dg-final { scan-assembler-times "amocas\.w\.aq\t" 2 } } */ ++ ++ ++void atomic_compare_exchange_weak_int_acquire (int *bar, int *baz, int qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 0, __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE); ++} ++ ++void atomic_compare_exchange_strong_int_acquire (int *bar, int *baz, int qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 1, __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-relaxed.c b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-relaxed.c +new file mode 100644 +index 00000000000..fb2a7b4f55a +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-relaxed.c +@@ -0,0 +1,19 @@ ++/* Verify that atomic op mappings match the PSABI doc's recommended mapping. */ ++/* { dg-do compile } */ ++/* { dg-options "-O3" } */ ++/* { dg-add-options riscv_zacas } */ ++/* { dg-remove-options riscv_ztso } */ ++/* { dg-final { scan-assembler-not "\tlr\.w" } } */ ++/* { dg-final { scan-assembler-not "\tsc\.w" } } */ ++/* { dg-final { scan-assembler-times "amocas\.w\t" 2 } } */ ++ ++ ++void atomic_compare_exchange_weak_int_relaxed (int *bar, int *baz, int qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 0, __ATOMIC_RELAXED, __ATOMIC_RELAXED); ++} ++ ++void atomic_compare_exchange_strong_int_relaxed (int *bar, int *baz, int qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 1, __ATOMIC_RELAXED, __ATOMIC_RELAXED); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-release.c b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-release.c +new file mode 100644 +index 00000000000..756f5cbe7d1 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-release.c +@@ -0,0 +1,19 @@ ++/* Verify that atomic op mappings match the PSABI doc's recommended mapping. */ ++/* { dg-do compile } */ ++/* { dg-options "-O3" } */ ++/* { dg-add-options riscv_zacas } */ ++/* { dg-remove-options riscv_ztso } */ ++/* { dg-final { scan-assembler-not "\tlr\.w" } } */ ++/* { dg-final { scan-assembler-not "\tsc\.w" } } */ ++/* { dg-final { scan-assembler-times "amocas\.w\.rl\t" 2 } } */ ++ ++ ++void atomic_compare_exchange_weak_int_release (int *bar, int *baz, int qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 0, __ATOMIC_RELEASE, __ATOMIC_RELAXED); ++} ++ ++void atomic_compare_exchange_strong_int_release (int *bar, int *baz, int qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 1, __ATOMIC_RELEASE, __ATOMIC_RELAXED); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-seq-cst.c b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-seq-cst.c +new file mode 100644 +index 00000000000..1c5b4ac0e2f +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-seq-cst.c +@@ -0,0 +1,19 @@ ++/* Verify that atomic op mappings match the PSABI doc's recommended mapping. */ ++/* { dg-do compile } */ ++/* { dg-options "-O3" } */ ++/* { dg-add-options riscv_zacas } */ ++/* { dg-remove-options riscv_ztso } */ ++/* { dg-final { scan-assembler-not "\tlr\.w" } } */ ++/* { dg-final { scan-assembler-not "\tsc\.w" } } */ ++/* { dg-final { scan-assembler-times "amocas\.w\.aqrl\t" 2 } } */ ++ ++ ++void atomic_compare_exchange_weak_int_seq_cst (int *bar, int *baz, int qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 0, __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST); ++} ++ ++void atomic_compare_exchange_strong_int_seq_cst (int *bar, int *baz, int qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 1, __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-acq-rel.c b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-acq-rel.c +new file mode 100644 +index 00000000000..2987eb3615d +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-acq-rel.c +@@ -0,0 +1,20 @@ ++/* Verify that atomic op mappings match the PSABI doc's recommended mapping. */ ++/* { dg-do compile } */ ++/* { dg-options "-O3" } */ ++/* { dg-add-options riscv_zabha } */ ++/* { dg-add-options riscv_zacas } */ ++/* { dg-remove-options riscv_ztso } */ ++/* { dg-final { scan-assembler-not "\tlr\.w" } } */ ++/* { dg-final { scan-assembler-not "\tsc\.w" } } */ ++/* { dg-final { scan-assembler-times "amocas\.h\.aqrl\t" 2 } } */ ++ ++ ++void atomic_compare_exchange_weak_short_acq_rel (short *bar, short *baz, short qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 0, __ATOMIC_ACQ_REL, __ATOMIC_RELAXED); ++} ++ ++void atomic_compare_exchange_strong_short_acq_rel (short *bar, short *baz, short qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 1, __ATOMIC_ACQ_REL, __ATOMIC_RELAXED); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-acquire.c b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-acquire.c +new file mode 100644 +index 00000000000..505791090be +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-acquire.c +@@ -0,0 +1,20 @@ ++/* Verify that atomic op mappings match the PSABI doc's recommended mapping. */ ++/* { dg-do compile } */ ++/* { dg-options "-O3" } */ ++/* { dg-add-options riscv_zabha } */ ++/* { dg-add-options riscv_zacas } */ ++/* { dg-remove-options riscv_ztso } */ ++/* { dg-final { scan-assembler-not "\tlr\.w" } } */ ++/* { dg-final { scan-assembler-not "\tsc\.w" } } */ ++/* { dg-final { scan-assembler-times "amocas\.h\.aq\t" 2 } } */ ++ ++ ++void atomic_compare_exchange_weak_short_acquire (short *bar, short *baz, short qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 0, __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE); ++} ++ ++void atomic_compare_exchange_strong_short_acquire (short *bar, short *baz, short qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 1, __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-relaxed.c b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-relaxed.c +new file mode 100644 +index 00000000000..a85694e26c8 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-relaxed.c +@@ -0,0 +1,20 @@ ++/* Verify that atomic op mappings match the PSABI doc's recommended mapping. */ ++/* { dg-do compile } */ ++/* { dg-options "-O3" } */ ++/* { dg-add-options riscv_zabha } */ ++/* { dg-add-options riscv_zacas } */ ++/* { dg-remove-options riscv_ztso } */ ++/* { dg-final { scan-assembler-not "\tlr\.w" } } */ ++/* { dg-final { scan-assembler-not "\tsc\.w" } } */ ++/* { dg-final { scan-assembler-times "amocas\.h\t" 2 } } */ ++ ++ ++void atomic_compare_exchange_weak_short_relaxed (short *bar, short *baz, short qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 0, __ATOMIC_RELAXED, __ATOMIC_RELAXED); ++} ++ ++void atomic_compare_exchange_strong_short_relaxed (short *bar, short *baz, short qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 1, __ATOMIC_RELAXED, __ATOMIC_RELAXED); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-release.c b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-release.c +new file mode 100644 +index 00000000000..e8e9aae0265 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-release.c +@@ -0,0 +1,20 @@ ++/* Verify that atomic op mappings match the PSABI doc's recommended mapping. */ ++/* { dg-do compile } */ ++/* { dg-options "-O3" } */ ++/* { dg-add-options riscv_zabha } */ ++/* { dg-add-options riscv_zacas } */ ++/* { dg-remove-options riscv_ztso } */ ++/* { dg-final { scan-assembler-not "\tlr\.w" } } */ ++/* { dg-final { scan-assembler-not "\tsc\.w" } } */ ++/* { dg-final { scan-assembler-times "amocas\.h\.rl\t" 2 } } */ ++ ++ ++void atomic_compare_exchange_weak_short_release (short *bar, short *baz, short qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 0, __ATOMIC_RELEASE, __ATOMIC_RELAXED); ++} ++ ++void atomic_compare_exchange_strong_short_release (short *bar, short *baz, short qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 1, __ATOMIC_RELEASE, __ATOMIC_RELAXED); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-seq-cst.c b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-seq-cst.c +new file mode 100644 +index 00000000000..d676d378e06 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-seq-cst.c +@@ -0,0 +1,20 @@ ++/* Verify that atomic op mappings match the PSABI doc's recommended mapping. */ ++/* { dg-do compile } */ ++/* { dg-options "-O3" } */ ++/* { dg-add-options riscv_zabha } */ ++/* { dg-add-options riscv_zacas } */ ++/* { dg-remove-options riscv_ztso } */ ++/* { dg-final { scan-assembler-not "\tlr\.w" } } */ ++/* { dg-final { scan-assembler-not "\tsc\.w" } } */ ++/* { dg-final { scan-assembler-times "amocas\.h\.aqrl\t" 2 } } */ ++ ++ ++void atomic_compare_exchange_weak_short_seq_cst (short *bar, short *baz, short qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 0, __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST); ++} ++ ++void atomic_compare_exchange_strong_short_seq_cst (short *bar, short *baz, short qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 1, __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-char-seq-cst.c b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-char-seq-cst.c +new file mode 100644 +index 00000000000..e219bd14b15 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-char-seq-cst.c +@@ -0,0 +1,19 @@ ++/* Verify that atomic op mappings match the PSABI doc's recommended mapping. */ ++/* { dg-do compile } */ ++/* { dg-options "-O3" } */ ++/* { dg-add-options riscv_zabha } */ ++/* { dg-add-options riscv_zacas } */ ++/* { dg-add-options riscv_ztso } */ ++/* { dg-final { scan-assembler-not "\tlr\.w" } } */ ++/* { dg-final { scan-assembler-not "\tsc\.w" } } */ ++/* { dg-final { scan-assembler-times "amocas\.b\t" 2 } } */ ++ ++void atomic_compare_exchange_weak_char_seq_cst (char *bar, char *baz, char qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 0, __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST); ++} ++ ++void atomic_compare_exchange_strong_char_seq_cst (char *bar, char *baz, char qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 1, __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-char.c b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-char.c +new file mode 100644 +index 00000000000..183dc4020c7 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-char.c +@@ -0,0 +1,49 @@ ++/* Verify that atomic op mappings match the PSABI doc's recommended mapping. */ ++/* { dg-do compile } */ ++/* { dg-options "-O3" } */ ++/* { dg-add-options riscv_zabha } */ ++/* { dg-add-options riscv_zacas } */ ++/* { dg-add-options riscv_ztso } */ ++/* { dg-final { scan-assembler-not "\tlr\.w" } } */ ++/* { dg-final { scan-assembler-not "\tsc\.w" } } */ ++/* { dg-final { scan-assembler-times "amocas\.b\t" 8 } } */ ++ ++void atomic_compare_exchange_weak_char_relaxed (char *bar, char *baz, char qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 0, __ATOMIC_RELAXED, __ATOMIC_RELAXED); ++} ++ ++void atomic_compare_exchange_strong_char_relaxed (char *bar, char *baz, char qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 1, __ATOMIC_RELAXED, __ATOMIC_RELAXED); ++} ++ ++void atomic_compare_exchange_weak_char_acquire (char *bar, char *baz, char qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 0, __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE); ++} ++ ++void atomic_compare_exchange_strong_char_acquire (char *bar, char *baz, char qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 1, __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE); ++} ++ ++void atomic_compare_exchange_weak_char_release (char *bar, char *baz, char qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 0, __ATOMIC_RELEASE, __ATOMIC_RELAXED); ++} ++ ++void atomic_compare_exchange_strong_char_release (char *bar, char *baz, char qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 1, __ATOMIC_RELEASE, __ATOMIC_RELAXED); ++} ++ ++void atomic_compare_exchange_weak_char_acq_rel (char *bar, char *baz, char qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 0, __ATOMIC_ACQ_REL, __ATOMIC_RELAXED); ++} ++ ++void atomic_compare_exchange_strong_char_acq_rel (char *bar, char *baz, char qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 1, __ATOMIC_ACQ_REL, __ATOMIC_RELAXED); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-compatability-mapping-no-fence.c b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-compatability-mapping-no-fence.c +new file mode 100644 +index 00000000000..2712eff5107 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-compatability-mapping-no-fence.c +@@ -0,0 +1,30 @@ ++/* ++** Verify that atomic op mappings match the PSABI doc's recommended mapping. ++** compare_exchange ops without a seq_cst failure ordering do *not* need a ++** leading fence. ++*/ ++/* { dg-do compile } */ ++/* { dg-options "-O3" } */ ++/* { dg-add-options riscv_zacas } */ ++/* { dg-add-options riscv_ztso } */ ++/* { dg-final { scan-assembler-not "\tfence" } } */ ++ ++void atomic_compare_exchange_weak_int_seq_cst_relaxed (int *bar, int *baz, int qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 0, __ATOMIC_SEQ_CST, __ATOMIC_RELAXED); ++} ++ ++void atomic_compare_exchange_weak_int_seq_cst_acquire (int *bar, int *baz, int qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 0, __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE); ++} ++ ++void atomic_compare_exchange_strong_int_seq_cst_relaxed (int *bar, int *baz, int qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 1, __ATOMIC_SEQ_CST, __ATOMIC_RELAXED); ++} ++ ++void atomic_compare_exchange_strong_int_seq_cst_acquire (int *bar, int *baz, int qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 1, __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-compatability-mapping.cc b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-compatability-mapping.cc +new file mode 100644 +index 00000000000..560172bfbed +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-compatability-mapping.cc +@@ -0,0 +1,58 @@ ++/* ++** Verify that atomic op mappings match the PSABI doc's recommended mapping. ++** compare_exchange ops with seq_cst failure ordering need a leading fence ++** to remain compatible with Table A.6 (A6C). ++*/ ++/* { dg-do compile } */ ++/* { dg-options "-O3 -std=c++17" } */ ++/* { dg-add-options riscv_zacas } */ ++/* { dg-add-options riscv_ztso } */ ++/* { dg-final { check-function-bodies "**" "" } } */ ++ ++/* ++** atomic_compare_exchange_weak_int_relaxed_seq_cst: ++** ... ++** fence\trw,rw ++** amoadd\.w\t[atx][0-9]+,a2,0\(a0\) ++** ... ++*/ ++void atomic_compare_exchange_weak_int_relaxed_seq_cst (int *bar, int *baz, int qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 0, __ATOMIC_RELAXED, __ATOMIC_SEQ_CST); ++} ++ ++/* ++** atomic_compare_exchange_weak_int_seq_cst_seq_cst: ++** ... ++** fence\trw,rw ++** amoadd\.w\t[atx][0-9]+,a2,0\(a0\) ++** ... ++*/ ++void atomic_compare_exchange_weak_int_seq_cst_seq_cst (int *bar, int *baz, int qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 0, __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST); ++} ++ ++/* ++** atomic_compare_exchange_strong_int_relaxed_seq_cst: ++** ... ++** fence\trw,rw ++** amoadd\.w\t[atx][0-9]+,a2,0\(a0\) ++** ... ++*/ ++void atomic_compare_exchange_strong_int_relaxed_seq_cst (int *bar, int *baz, int qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 1, __ATOMIC_RELAXED, __ATOMIC_SEQ_CST); ++} ++ ++/* ++** atomic_compare_exchange_strong_int_seq_cst_seq_cst: ++** ... ++** fence\trw,rw ++** amoadd\.w\t[atx][0-9]+,a2,0\(a0\) ++** ... ++*/ ++void atomic_compare_exchange_strong_int_seq_cst_seq_cst (int *bar, int *baz, int qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 1, __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-int-seq-cst.c b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-int-seq-cst.c +new file mode 100644 +index 00000000000..1ee6cc20218 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-int-seq-cst.c +@@ -0,0 +1,18 @@ ++/* Verify that atomic op mappings match the PSABI doc's recommended mapping. */ ++/* { dg-do compile } */ ++/* { dg-options "-O3" } */ ++/* { dg-add-options riscv_zacas } */ ++/* { dg-add-options riscv_ztso } */ ++/* { dg-final { scan-assembler-not "\tlr\.w" } } */ ++/* { dg-final { scan-assembler-not "\tsc\.w" } } */ ++/* { dg-final { scan-assembler-times "amocas\.w\t" 2 } } */ ++ ++void atomic_compare_exchange_weak_int_seq_cst (int *bar, int *baz, int qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 0, __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST); ++} ++ ++void atomic_compare_exchange_strong_int_seq_cst (int *bar, int *baz, int qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 1, __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-int.c b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-int.c +new file mode 100644 +index 00000000000..2c332623a95 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-int.c +@@ -0,0 +1,48 @@ ++/* Verify that atomic op mappings match the PSABI doc's recommended mapping. */ ++/* { dg-do compile } */ ++/* { dg-options "-O3" } */ ++/* { dg-add-options riscv_zacas } */ ++/* { dg-add-options riscv_ztso } */ ++/* { dg-final { scan-assembler-not "\tlr\.w" } } */ ++/* { dg-final { scan-assembler-not "\tsc\.w" } } */ ++/* { dg-final { scan-assembler-times "amocas\.w\t" 8 } } */ ++ ++void atomic_compare_exchange_weak_int_relaxed (int *bar, int *baz, int qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 0, __ATOMIC_RELAXED, __ATOMIC_RELAXED); ++} ++ ++void atomic_compare_exchange_strong_int_relaxed (int *bar, int *baz, int qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 1, __ATOMIC_RELAXED, __ATOMIC_RELAXED); ++} ++ ++void atomic_compare_exchange_weak_int_acquire (int *bar, int *baz, int qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 0, __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE); ++} ++ ++void atomic_compare_exchange_strong_int_acquire (int *bar, int *baz, int qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 1, __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE); ++} ++ ++void atomic_compare_exchange_weak_int_release (int *bar, int *baz, int qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 0, __ATOMIC_RELEASE, __ATOMIC_RELAXED); ++} ++ ++void atomic_compare_exchange_strong_int_release (int *bar, int *baz, int qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 1, __ATOMIC_RELEASE, __ATOMIC_RELAXED); ++} ++ ++void atomic_compare_exchange_weak_int_acq_rel (int *bar, int *baz, int qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 0, __ATOMIC_ACQ_REL, __ATOMIC_RELAXED); ++} ++ ++void atomic_compare_exchange_strong_int_acq_rel (int *bar, int *baz, int qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 1, __ATOMIC_ACQ_REL, __ATOMIC_RELAXED); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-short-seq-cst.c b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-short-seq-cst.c +new file mode 100644 +index 00000000000..1938448183c +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-short-seq-cst.c +@@ -0,0 +1,19 @@ ++/* Verify that atomic op mappings match the PSABI doc's recommended mapping. */ ++/* { dg-do compile } */ ++/* { dg-options "-O3" } */ ++/* { dg-add-options riscv_zabha } */ ++/* { dg-add-options riscv_zacas } */ ++/* { dg-add-options riscv_ztso } */ ++/* { dg-final { scan-assembler-not "\tlr\.w" } } */ ++/* { dg-final { scan-assembler-not "\tsc\.w" } } */ ++/* { dg-final { scan-assembler-times "amocas\.h\t" 2 } } */ ++ ++void atomic_compare_exchange_weak_short_seq_cst (short *bar, short *baz, short qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 0, __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST); ++} ++ ++void atomic_compare_exchange_strong_short_seq_cst (short *bar, short *baz, short qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 1, __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-short.c b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-short.c +new file mode 100644 +index 00000000000..69fe5ae3eac +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-short.c +@@ -0,0 +1,49 @@ ++/* Verify that atomic op mappings match the PSABI doc's recommended mapping. */ ++/* { dg-do compile } */ ++/* { dg-options "-O3" } */ ++/* { dg-add-options riscv_zabha } */ ++/* { dg-add-options riscv_zacas } */ ++/* { dg-add-options riscv_ztso } */ ++/* { dg-final { scan-assembler-not "\tlr\.w" } } */ ++/* { dg-final { scan-assembler-not "\tsc\.w" } } */ ++/* { dg-final { scan-assembler-times "amocas\.h\t" 8 } } */ ++ ++void atomic_compare_exchange_weak_short_relaxed (short *bar, short *baz, short qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 0, __ATOMIC_RELAXED, __ATOMIC_RELAXED); ++} ++ ++void atomic_compare_exchange_strong_short_relaxed (short *bar, short *baz, short qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 1, __ATOMIC_RELAXED, __ATOMIC_RELAXED); ++} ++ ++void atomic_compare_exchange_weak_short_acquire (short *bar, short *baz, short qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 0, __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE); ++} ++ ++void atomic_compare_exchange_strong_short_acquire (short *bar, short *baz, short qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 1, __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE); ++} ++ ++void atomic_compare_exchange_weak_short_release (short *bar, short *baz, short qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 0, __ATOMIC_RELEASE, __ATOMIC_RELAXED); ++} ++ ++void atomic_compare_exchange_strong_short_release (short *bar, short *baz, short qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 1, __ATOMIC_RELEASE, __ATOMIC_RELAXED); ++} ++ ++void atomic_compare_exchange_weak_short_acq_rel (short *bar, short *baz, short qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 0, __ATOMIC_ACQ_REL, __ATOMIC_RELAXED); ++} ++ ++void atomic_compare_exchange_strong_short_acq_rel (short *bar, short *baz, short qux) ++{ ++ __atomic_compare_exchange_n(bar, baz, qux, 1, __ATOMIC_ACQ_REL, __ATOMIC_RELAXED); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire-release.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire-release.c +index 49eeda9cb33..9a5616f8916 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire-release.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire-release.c +@@ -2,6 +2,7 @@ + /* Verify that compare exchange mappings match the PSABI doc's recommended mapping. */ + /* { dg-add-options riscv_zalrsc } */ + /* { dg-remove-options riscv_ztso } */ ++/* { dg-remove-options riscv_zacas } */ + /* Mixed mappings need to be unioned. */ + /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire.c +index b9e3adece8d..a24234855e9 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire.c +@@ -2,6 +2,7 @@ + /* Verify that compare exchange mappings match the PSABI doc's recommended mapping. */ + /* { dg-add-options riscv_zalrsc } */ + /* { dg-remove-options riscv_ztso } */ ++/* { dg-remove-options riscv_zacas } */ + /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-consume.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-consume.c +index 11839d84f14..18f53c83a38 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-consume.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-consume.c +@@ -2,6 +2,7 @@ + /* Verify that compare exchange mappings match the PSABI doc's recommended mapping. */ + /* { dg-add-options riscv_zalrsc } */ + /* { dg-remove-options riscv_ztso } */ ++/* { dg-remove-options riscv_zacas } */ + /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-relaxed.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-relaxed.c +index 852ec99df76..c7a43ecd323 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-relaxed.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-relaxed.c +@@ -2,6 +2,7 @@ + /* Verify that compare exchange mappings match the PSABI doc's recommended mapping. */ + /* { dg-add-options riscv_zalrsc } */ + /* { dg-remove-options riscv_ztso } */ ++/* { dg-remove-options riscv_zacas } */ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-release.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-release.c +index 9c51a082d0b..302fca2ca17 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-release.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-release.c +@@ -2,6 +2,7 @@ + /* Verify that compare exchange mappings match the PSABI doc's recommended mapping. */ + /* { dg-add-options riscv_zalrsc } */ + /* { dg-remove-options riscv_ztso } */ ++/* { dg-remove-options riscv_zacas } */ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst-relaxed.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst-relaxed.c +index d985e2cef8b..e62002d267a 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst-relaxed.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst-relaxed.c +@@ -3,6 +3,7 @@ + /* Mixed mappings need to be unioned. */ + /* { dg-add-options riscv_zalrsc } */ + /* { dg-remove-options riscv_ztso } */ ++/* { dg-remove-options riscv_zacas } */ + /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst.c +index 6efd232ce21..c047d509aaf 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst.c +@@ -2,6 +2,7 @@ + /* Verify that compare exchange mappings match the PSABI doc's recommended mapping. */ + /* { dg-add-options riscv_zalrsc } */ + /* { dg-remove-options riscv_ztso } */ ++/* { dg-remove-options riscv_zacas } */ + /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire-release.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire-release.c +index 9761a955ede..496af8bfd7d 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire-release.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire-release.c +@@ -3,6 +3,7 @@ + /* Mixed mappings need to be unioned. */ + /* { dg-add-options riscv_zalrsc } */ + /* { dg-add-options riscv_ztso } */ ++/* { dg-remove-options riscv_zacas } */ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire.c +index 3303f8021e1..737e3eb3d68 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire.c +@@ -2,6 +2,7 @@ + /* Verify that compare exchange mappings match the PSABI doc's recommended mapping. */ + /* { dg-add-options riscv_zalrsc } */ + /* { dg-add-options riscv_ztso } */ ++/* { dg-remove-options riscv_zacas } */ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-consume.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-consume.c +index 7474e832bb1..51b3b5a8dc7 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-consume.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-consume.c +@@ -2,6 +2,7 @@ + /* Verify that compare exchange mappings match the PSABI doc's recommended mapping. */ + /* { dg-add-options riscv_zalrsc } */ + /* { dg-add-options riscv_ztso } */ ++/* { dg-remove-options riscv_zacas } */ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-relaxed.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-relaxed.c +index e43193820f2..9a41410a57b 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-relaxed.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-relaxed.c +@@ -2,6 +2,7 @@ + /* Verify that compare exchange mappings match the PSABI doc's recommended mapping. */ + /* { dg-add-options riscv_zalrsc } */ + /* { dg-add-options riscv_ztso } */ ++/* { dg-remove-options riscv_zacas } */ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-release.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-release.c +index a0d5872e1bd..ee778a760d1 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-release.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-release.c +@@ -2,6 +2,7 @@ + /* Verify that compare exchange mappings match the PSABI doc's recommended mapping. */ + /* { dg-add-options riscv_zalrsc } */ + /* { dg-add-options riscv_ztso } */ ++/* { dg-remove-options riscv_zacas } */ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst-relaxed.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst-relaxed.c +index fc464ab1ff5..6fbe943b316 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst-relaxed.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst-relaxed.c +@@ -3,6 +3,7 @@ + /* Mixed mappings need to be unioned. */ + /* { dg-add-options riscv_zalrsc } */ + /* { dg-add-options riscv_ztso } */ ++/* { dg-remove-options riscv_zacas } */ + /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst.c +index 152806cfde3..a361c10086d 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst.c +@@ -2,6 +2,7 @@ + /* Verify that compare exchange mappings match the PSABI doc's recommended mapping. */ + /* { dg-add-options riscv_zalrsc } */ + /* { dg-add-options riscv_ztso } */ ++/* { dg-remove-options riscv_zacas } */ + /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ + +diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp +index 5a74883c066..99af59a4ae1 100644 +--- a/gcc/testsuite/lib/target-supports.exp ++++ b/gcc/testsuite/lib/target-supports.exp +@@ -1944,6 +1944,17 @@ proc check_effective_target_riscv_zabha { } { + }] + } + ++# Return 1 if the target arch supports the atomic CAS extension, 0 otherwise. ++# Cache the result. ++ ++proc check_effective_target_riscv_zacas { } { ++ return [check_no_compiler_messages riscv_ext_zacas assembly { ++ #ifndef __riscv_zacas ++ #error "Not __riscv_zacas" ++ #endif ++ }] ++} ++ + # Return 1 if the target arch supports the double precision floating point + # extension, 0 otherwise. Cache the result. + +@@ -2199,7 +2210,7 @@ proc check_effective_target_riscv_v_misalign_ok { } { + proc riscv_get_arch { } { + set gcc_march "" + # ??? do we neeed to add more extensions to the list below? +- foreach ext { i m a f d q c b v zicsr zifencei zfh zba zbb zbc zbs zvbb zvfh ztso zaamo zalrsc zabha } { ++ foreach ext { i m a f d q c b v zicsr zifencei zfh zba zbb zbc zbs zvbb zvfh ztso zaamo zalrsc zabha zacas } { + if { [check_no_compiler_messages riscv_ext_$ext assembly [string map [list DEF __riscv_$ext] { + #ifndef DEF + #error "Not DEF" +@@ -2367,6 +2378,9 @@ proc remove_options_for_riscv_zaamo { flags } { + # If zabha is set then zaamo will be implied. We need to remove zabha + # as well. + set modified_flags [remove_options_for_riscv_z_ext zabha $modified_flags] ++ # If zacas is set then zaamo will be implied. We need to remove zacas ++ # as well. ++ set modified_flags [remove_options_for_riscv_z_ext zacas $modified_flags] + # If 'a' is set then zaamo will be implied. We need to downgrade instances + # of 'a' to 'zalrsc' + set no_a_flags [remove_options_for_riscv_a_only $modified_flags] +@@ -2402,6 +2416,15 @@ proc remove_options_for_riscv_zabha { flags } { + return [remove_options_for_riscv_z_ext zabha $modified_flags] + } + ++proc add_options_for_riscv_zacas { flags } { ++ return [add_options_for_riscv_z_ext zacas $flags] ++} ++ ++proc remove_options_for_riscv_zacas { flags } { ++ set modified_flags [remove_options_for_riscv_zaamo $flags] ++ return [remove_options_for_riscv_z_ext zacas $modified_flags] ++} ++ + proc add_options_for_riscv_zfh { flags } { + return [add_options_for_riscv_z_ext zfh $flags] + } +-- +2.47.3 + diff --git a/1059-RISC-V-Add-configure-check-for-B-extention-support.patch b/1059-RISC-V-Add-configure-check-for-B-extention-support.patch new file mode 100644 index 0000000..29124e9 --- /dev/null +++ b/1059-RISC-V-Add-configure-check-for-B-extention-support.patch @@ -0,0 +1,140 @@ +From 41178ff020149dda6d4dee4fcb80603158f57e1c Mon Sep 17 00:00:00 2001 +From: Edwin Lu +Date: Wed, 24 Jul 2024 16:37:18 -0700 +Subject: [PATCH 1059/1087] RISC-V: Add configure check for B extention support + +commit 7ef8a9d4b1cea3fea3791859074df79b71abd549 upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +Binutils 2.42 and before don't recognize the b extension in the march +strings even though it supports zba_zbb_zbs. Add a configure check to +ignore the b in the march string if found. + +gcc/ChangeLog: + + * common/config/riscv/riscv-common.cc (riscv_subset_list::to_string): + Skip b in march string + * config.in: Regenerate. + * configure: Regenerate. + * configure.ac: Add B assembler check + +Signed-off-by: Edwin Lu +--- + gcc/common/config/riscv/riscv-common.cc | 8 +++++++ + gcc/config.in | 6 +++++ + gcc/configure | 31 +++++++++++++++++++++++++ + gcc/configure.ac | 5 ++++ + 4 files changed, 50 insertions(+) + +diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc +index e13f0922b7f..7c172a039d2 100644 +--- a/gcc/common/config/riscv/riscv-common.cc ++++ b/gcc/common/config/riscv/riscv-common.cc +@@ -858,6 +858,7 @@ riscv_subset_list::to_string (bool version_p) const + bool skip_zifencei = false; + bool skip_zaamo_zalrsc = false; + bool skip_zicsr = false; ++ bool skip_b = false; + bool i2p0 = false; + + /* For RISC-V ISA version 2.2 or earlier version, zicsr and zifencei is +@@ -890,6 +891,10 @@ riscv_subset_list::to_string (bool version_p) const + for users with an older version of binutils. */ + skip_zaamo_zalrsc = true; + #endif ++#ifndef HAVE_AS_MARCH_B ++ /* Skip since binutils 2.42 and earlier don't recognize b. */ ++ skip_b = true; ++#endif + + for (subset = m_head; subset != NULL; subset = subset->next) + { +@@ -907,6 +912,9 @@ riscv_subset_list::to_string (bool version_p) const + if (skip_zaamo_zalrsc && subset->name == "zalrsc") + continue; + ++ if (skip_b && subset->name == "b") ++ continue; ++ + /* For !version_p, we only separate extension with underline for + multi-letter extension. */ + if (!first && +diff --git a/gcc/config.in b/gcc/config.in +index 21a7e12376b..c2dad93a53a 100644 +--- a/gcc/config.in ++++ b/gcc/config.in +@@ -629,6 +629,12 @@ + #endif + + ++/* Define if the assembler understands -march=rv*_b. */ ++#ifndef USED_FOR_TARGET ++#undef HAVE_AS_MARCH_B ++#endif ++ ++ + /* Define if the assembler understands -march=rv*_zaamo_zalrsc. */ + #ifndef USED_FOR_TARGET + #undef HAVE_AS_MARCH_ZAAMO_ZALRSC +diff --git a/gcc/configure b/gcc/configure +index c0dd02ffff5..ded2d1078e1 100755 +--- a/gcc/configure ++++ b/gcc/configure +@@ -31100,6 +31100,37 @@ if test $gcc_cv_as_riscv_march_zaamo_zalrsc = yes; then + + $as_echo "#define HAVE_AS_MARCH_ZAAMO_ZALRSC 1" >>confdefs.h + ++fi ++ ++ { $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for -march=rv32i_b support" >&5 ++$as_echo_n "checking assembler for -march=rv32i_b support... " >&6; } ++if ${gcc_cv_as_riscv_march_b+:} false; then : ++ $as_echo_n "(cached) " >&6 ++else ++ gcc_cv_as_riscv_march_b=no ++ if test x$gcc_cv_as != x; then ++ $as_echo '' > conftest.s ++ if { ac_try='$gcc_cv_as $gcc_cv_as_flags -march=rv32i_b -o conftest.o conftest.s >&5' ++ { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5 ++ (eval $ac_try) 2>&5 ++ ac_status=$? ++ $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 ++ test $ac_status = 0; }; } ++ then ++ gcc_cv_as_riscv_march_b=yes ++ else ++ echo "configure: failed program was" >&5 ++ cat conftest.s >&5 ++ fi ++ rm -f conftest.o conftest.s ++ fi ++fi ++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_as_riscv_march_b" >&5 ++$as_echo "$gcc_cv_as_riscv_march_b" >&6; } ++if test $gcc_cv_as_riscv_march_b = yes; then ++ ++$as_echo "#define HAVE_AS_MARCH_B 1" >>confdefs.h ++ + fi + + ;; +diff --git a/gcc/configure.ac b/gcc/configure.ac +index 09ffd6bca3c..f8e6e66b872 100644 +--- a/gcc/configure.ac ++++ b/gcc/configure.ac +@@ -5523,6 +5523,11 @@ configured with --enable-newlib-nano-formatted-io.]) + [-march=rv32i_zaamo_zalrsc],,, + [AC_DEFINE(HAVE_AS_MARCH_ZAAMO_ZALRSC, 1, + [Define if the assembler understands -march=rv*_zaamo_zalrsc.])]) ++ gcc_GAS_CHECK_FEATURE([-march=rv32i_b support], ++ gcc_cv_as_riscv_march_b, ++ [-march=rv32i_b],,, ++ [AC_DEFINE(HAVE_AS_MARCH_B, 1, ++ [Define if the assembler understands -march=rv*_b.])]) + ;; + loongarch*-*-*) + gcc_GAS_CHECK_FEATURE([.dtprelword support], +-- +2.47.3 + diff --git a/1060-testsuite-fix-dg-compile-typos.patch b/1060-testsuite-fix-dg-compile-typos.patch new file mode 100644 index 0000000..8bc16b1 --- /dev/null +++ b/1060-testsuite-fix-dg-compile-typos.patch @@ -0,0 +1,414 @@ +From 623ff1b439a667c9855f7990dba6006ddbdf847f Mon Sep 17 00:00:00 2001 +From: Sam James +Date: Tue, 30 Jul 2024 20:04:40 +0100 +Subject: [PATCH 1060/1087] testsuite: fix 'dg-compile' typos + +commit acc70606c59e3f14072cc8a164362e728d8df5d6 upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +'dg-compile' is not a thing, replace it with 'dg-do compile'. + + PR target/68015 + PR c++/83979 + * c-c++-common/goacc/loop-shape.c: Fix 'dg-compile' typo. + * g++.dg/pr83979.C: Likewise. + * g++.target/aarch64/sve/acle/general-c++/attributes_2.C: Likewise. + * gcc.dg/tree-ssa/builtin-sprintf-7.c: Likewise. + * gcc.dg/tree-ssa/builtin-sprintf-8.c: Likewise. + * gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-char.c: Likewise. + * gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-short.c: Likewise. + * gcc.target/s390/20181024-1.c: Likewise. + * gcc.target/s390/addr-constraints-1.c: Likewise. + * gcc.target/s390/arch12/aghsghmgh-1.c: Likewise. + * gcc.target/s390/arch12/mul-1.c: Likewise. + * gcc.target/s390/arch13/bitops-1.c: Likewise. + * gcc.target/s390/arch13/bitops-2.c: Likewise. + * gcc.target/s390/arch13/fp-signedint-convert-1.c: Likewise. + * gcc.target/s390/arch13/fp-unsignedint-convert-1.c: Likewise. + * gcc.target/s390/arch13/popcount-1.c: Likewise. + * gcc.target/s390/pr68015.c: Likewise. + * gcc.target/s390/vector/fp-signedint-convert-1.c: Likewise. + * gcc.target/s390/vector/fp-unsignedint-convert-1.c: Likewise. + * gcc.target/s390/vector/reverse-elements-1.c: Likewise. + * gcc.target/s390/vector/reverse-elements-2.c: Likewise. + * gcc.target/s390/vector/reverse-elements-3.c: Likewise. + * gcc.target/s390/vector/reverse-elements-4.c: Likewise. + * gcc.target/s390/vector/reverse-elements-5.c: Likewise. + * gcc.target/s390/vector/reverse-elements-6.c: Likewise. + * gcc.target/s390/vector/reverse-elements-7.c: Likewise. + * gnat.dg/alignment15.adb: Likewise. + * gnat.dg/debug4.adb: Likewise. + * gnat.dg/inline21.adb: Likewise. + * gnat.dg/inline22.adb: Likewise. + * gnat.dg/opt37.adb: Likewise. + * gnat.dg/warn13.adb: Likewise. +--- + gcc/testsuite/c-c++-common/goacc/loop-shape.c | 2 +- + gcc/testsuite/g++.dg/pr83979.C | 2 +- + .../g++.target/aarch64/sve/acle/general-c++/attributes_2.C | 2 +- + gcc/testsuite/gcc.dg/tree-ssa/builtin-sprintf-7.c | 2 +- + gcc/testsuite/gcc.dg/tree-ssa/builtin-sprintf-8.c | 2 +- + .../gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-char.c | 2 +- + .../gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-short.c | 2 +- + gcc/testsuite/gcc.target/s390/20181024-1.c | 2 +- + gcc/testsuite/gcc.target/s390/addr-constraints-1.c | 2 +- + gcc/testsuite/gcc.target/s390/arch12/aghsghmgh-1.c | 2 +- + gcc/testsuite/gcc.target/s390/arch12/mul-1.c | 2 +- + gcc/testsuite/gcc.target/s390/arch13/bitops-1.c | 2 +- + gcc/testsuite/gcc.target/s390/arch13/bitops-2.c | 2 +- + gcc/testsuite/gcc.target/s390/arch13/fp-signedint-convert-1.c | 2 +- + gcc/testsuite/gcc.target/s390/arch13/fp-unsignedint-convert-1.c | 2 +- + gcc/testsuite/gcc.target/s390/arch13/popcount-1.c | 2 +- + gcc/testsuite/gcc.target/s390/pr68015.c | 2 +- + gcc/testsuite/gcc.target/s390/vector/fp-signedint-convert-1.c | 2 +- + gcc/testsuite/gcc.target/s390/vector/fp-unsignedint-convert-1.c | 2 +- + gcc/testsuite/gcc.target/s390/vector/reverse-elements-1.c | 2 +- + gcc/testsuite/gcc.target/s390/vector/reverse-elements-2.c | 2 +- + gcc/testsuite/gcc.target/s390/vector/reverse-elements-3.c | 2 +- + gcc/testsuite/gcc.target/s390/vector/reverse-elements-4.c | 2 +- + gcc/testsuite/gcc.target/s390/vector/reverse-elements-5.c | 2 +- + gcc/testsuite/gcc.target/s390/vector/reverse-elements-6.c | 2 +- + gcc/testsuite/gcc.target/s390/vector/reverse-elements-7.c | 2 +- + gcc/testsuite/gnat.dg/alignment15.adb | 2 +- + gcc/testsuite/gnat.dg/debug4.adb | 2 +- + gcc/testsuite/gnat.dg/inline21.adb | 2 +- + gcc/testsuite/gnat.dg/inline22.adb | 2 +- + gcc/testsuite/gnat.dg/opt37.adb | 2 +- + gcc/testsuite/gnat.dg/warn13.adb | 2 +- + 32 files changed, 32 insertions(+), 32 deletions(-) + +diff --git a/gcc/testsuite/c-c++-common/goacc/loop-shape.c b/gcc/testsuite/c-c++-common/goacc/loop-shape.c +index 9708f7bf5eb..b3199b4044d 100644 +--- a/gcc/testsuite/c-c++-common/goacc/loop-shape.c ++++ b/gcc/testsuite/c-c++-common/goacc/loop-shape.c +@@ -1,7 +1,7 @@ + /* Exercise *_parser_oacc_shape_clause by checking various combinations + of gang, worker and vector clause arguments. */ + +-/* { dg-compile } */ ++/* { dg-do compile } */ + + int main () + { +diff --git a/gcc/testsuite/g++.dg/pr83979.C b/gcc/testsuite/g++.dg/pr83979.C +index a39b1ea6ab9..0ef754d1e48 100644 +--- a/gcc/testsuite/g++.dg/pr83979.C ++++ b/gcc/testsuite/g++.dg/pr83979.C +@@ -1,4 +1,4 @@ +-/* { dg-compile } */ ++/* { dg-do compile } */ + + int + foo (char* p) +diff --git a/gcc/testsuite/g++.target/aarch64/sve/acle/general-c++/attributes_2.C b/gcc/testsuite/g++.target/aarch64/sve/acle/general-c++/attributes_2.C +index b55be02ecca..c8f1ad403e6 100644 +--- a/gcc/testsuite/g++.target/aarch64/sve/acle/general-c++/attributes_2.C ++++ b/gcc/testsuite/g++.target/aarch64/sve/acle/general-c++/attributes_2.C +@@ -1,4 +1,4 @@ +-// { dg-compile } ++// { dg-do compile } + // { dg-additional-options "-msve-vector-bits=512" } + + #include +diff --git a/gcc/testsuite/gcc.dg/tree-ssa/builtin-sprintf-7.c b/gcc/testsuite/gcc.dg/tree-ssa/builtin-sprintf-7.c +index 29954aabfdb..eca4e908092 100644 +--- a/gcc/testsuite/gcc.dg/tree-ssa/builtin-sprintf-7.c ++++ b/gcc/testsuite/gcc.dg/tree-ssa/builtin-sprintf-7.c +@@ -1,6 +1,6 @@ + /* PR tree-optimization/77671 - missing -Wformat-overflow warning + on sprintf overflow with "%s" +- { dg-compile } ++ { dg-do compile } + { dg-options "-O2 -Wformat -Wno-format-zero-length -fdump-tree-optimized" } */ + + void sink (char*); +diff --git a/gcc/testsuite/gcc.dg/tree-ssa/builtin-sprintf-8.c b/gcc/testsuite/gcc.dg/tree-ssa/builtin-sprintf-8.c +index 2d38d12bcc2..da1088c5fff 100644 +--- a/gcc/testsuite/gcc.dg/tree-ssa/builtin-sprintf-8.c ++++ b/gcc/testsuite/gcc.dg/tree-ssa/builtin-sprintf-8.c +@@ -5,7 +5,7 @@ + be transformed into calls to other functions (such as memcpy) + are preserved. + +- { dg-compile } ++ { dg-do compile } + { dg-options "-O2 -Wformat -Wno-format-truncation -Wno-format-zero-length -fdump-tree-optimized" } */ + + void sink (char*, ...); +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-char.c b/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-char.c +index 85841fd7036..58211207186 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-char.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-char.c +@@ -1,5 +1,5 @@ + /* Test __atomic routines for existence on 2 byte values with each valid memory model. */ +-/* { dg-compile } */ ++/* { dg-do compile } */ + /* { dg-options "-Wno-address-of-packed-member" } */ + /* { dg-add-options riscv_zabha } */ + /* { dg-remove-options riscv_ztso } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-short.c b/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-short.c +index edc0a2c8f8e..c846ca48d72 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-short.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-short.c +@@ -1,5 +1,5 @@ + /* Test __atomic routines for existence on 2 byte values with each valid memory model. */ +-/* { dg-compile } */ ++/* { dg-do compile } */ + /* { dg-options "-Wno-address-of-packed-member" } */ + /* { dg-add-options riscv_zabha } */ + /* { dg-remove-options riscv_ztso } */ +diff --git a/gcc/testsuite/gcc.target/s390/20181024-1.c b/gcc/testsuite/gcc.target/s390/20181024-1.c +index 830ab5b927c..66415ce9ce2 100644 +--- a/gcc/testsuite/gcc.target/s390/20181024-1.c ++++ b/gcc/testsuite/gcc.target/s390/20181024-1.c +@@ -1,5 +1,5 @@ + /* Make sure s390_check_qrst_address () correctly handles UNSPEC rtxs. */ +-/* { dg-compile } */ ++/* { dg-do compile } */ + /* { dg-options "-march=z196 -O2 -fPIC" } */ + + int a, b, g, h; +diff --git a/gcc/testsuite/gcc.target/s390/addr-constraints-1.c b/gcc/testsuite/gcc.target/s390/addr-constraints-1.c +index fbb48f282b3..165a0828cc4 100644 +--- a/gcc/testsuite/gcc.target/s390/addr-constraints-1.c ++++ b/gcc/testsuite/gcc.target/s390/addr-constraints-1.c +@@ -1,4 +1,4 @@ +-/* { dg-compile } */ ++/* { dg-do compile } */ + /* { dg-options "-O2" } */ + + static inline unsigned long +diff --git a/gcc/testsuite/gcc.target/s390/arch12/aghsghmgh-1.c b/gcc/testsuite/gcc.target/s390/arch12/aghsghmgh-1.c +index fc844c3e404..29cbecb691c 100644 +--- a/gcc/testsuite/gcc.target/s390/arch12/aghsghmgh-1.c ++++ b/gcc/testsuite/gcc.target/s390/arch12/aghsghmgh-1.c +@@ -1,4 +1,4 @@ +-/* { dg-compile } */ ++/* { dg-do compile } */ + + long long + agh (long long a, short int *p) +diff --git a/gcc/testsuite/gcc.target/s390/arch12/mul-1.c b/gcc/testsuite/gcc.target/s390/arch12/mul-1.c +index ef395356b72..da0421b8385 100644 +--- a/gcc/testsuite/gcc.target/s390/arch12/mul-1.c ++++ b/gcc/testsuite/gcc.target/s390/arch12/mul-1.c +@@ -1,4 +1,4 @@ +-/* { dg-compile } */ ++/* { dg-do compile } */ + + int + msrkc (int unused, int a, int b) +diff --git a/gcc/testsuite/gcc.target/s390/arch13/bitops-1.c b/gcc/testsuite/gcc.target/s390/arch13/bitops-1.c +index fd49fb97630..8d84655f71c 100644 +--- a/gcc/testsuite/gcc.target/s390/arch13/bitops-1.c ++++ b/gcc/testsuite/gcc.target/s390/arch13/bitops-1.c +@@ -1,4 +1,4 @@ +-/* { dg-compile } */ ++/* { dg-do compile } */ + + /* and with complement */ + +diff --git a/gcc/testsuite/gcc.target/s390/arch13/bitops-2.c b/gcc/testsuite/gcc.target/s390/arch13/bitops-2.c +index fde96034c55..1bfada3b05a 100644 +--- a/gcc/testsuite/gcc.target/s390/arch13/bitops-2.c ++++ b/gcc/testsuite/gcc.target/s390/arch13/bitops-2.c +@@ -1,4 +1,4 @@ +-/* { dg-compile } */ ++/* { dg-do compile } */ + + /* Check if the instruction are being used also for compares. */ + +diff --git a/gcc/testsuite/gcc.target/s390/arch13/fp-signedint-convert-1.c b/gcc/testsuite/gcc.target/s390/arch13/fp-signedint-convert-1.c +index 9801da86cf3..9c9ea2a5504 100644 +--- a/gcc/testsuite/gcc.target/s390/arch13/fp-signedint-convert-1.c ++++ b/gcc/testsuite/gcc.target/s390/arch13/fp-signedint-convert-1.c +@@ -1,4 +1,4 @@ +-/* { dg-compile } */ ++/* { dg-do compile } */ + + typedef int __attribute__((vector_size(16))) v4si; + typedef float __attribute__((vector_size(16))) v4sf; +diff --git a/gcc/testsuite/gcc.target/s390/arch13/fp-unsignedint-convert-1.c b/gcc/testsuite/gcc.target/s390/arch13/fp-unsignedint-convert-1.c +index b93b95daf25..1369ad6ff46 100644 +--- a/gcc/testsuite/gcc.target/s390/arch13/fp-unsignedint-convert-1.c ++++ b/gcc/testsuite/gcc.target/s390/arch13/fp-unsignedint-convert-1.c +@@ -1,4 +1,4 @@ +-/* { dg-compile } */ ++/* { dg-do compile } */ + + typedef unsigned int __attribute__((vector_size(16))) v4si; + typedef float __attribute__((vector_size(16))) v4sf; +diff --git a/gcc/testsuite/gcc.target/s390/arch13/popcount-1.c b/gcc/testsuite/gcc.target/s390/arch13/popcount-1.c +index c98a3272a02..92d5acb93dc 100644 +--- a/gcc/testsuite/gcc.target/s390/arch13/popcount-1.c ++++ b/gcc/testsuite/gcc.target/s390/arch13/popcount-1.c +@@ -1,4 +1,4 @@ +-/* { dg-compile } */ ++/* { dg-do compile } */ + + unsigned int ui; + unsigned long ul; +diff --git a/gcc/testsuite/gcc.target/s390/pr68015.c b/gcc/testsuite/gcc.target/s390/pr68015.c +index b0d1f35ad1a..47adc63d7f7 100644 +--- a/gcc/testsuite/gcc.target/s390/pr68015.c ++++ b/gcc/testsuite/gcc.target/s390/pr68015.c +@@ -1,4 +1,4 @@ +-/* { dg-compile } */ ++/* { dg-do compile } */ + /* { dg-options "-O2 -march=z196" } */ + + extern long useme (long, ...); +diff --git a/gcc/testsuite/gcc.target/s390/vector/fp-signedint-convert-1.c b/gcc/testsuite/gcc.target/s390/vector/fp-signedint-convert-1.c +index 536817aa5af..69dddf22267 100644 +--- a/gcc/testsuite/gcc.target/s390/vector/fp-signedint-convert-1.c ++++ b/gcc/testsuite/gcc.target/s390/vector/fp-signedint-convert-1.c +@@ -1,4 +1,4 @@ +-/* { dg-compile } */ ++/* { dg-do compile } */ + /* { dg-options "-O3 -march=z13 -mzarch" } */ + + typedef long long __attribute__((vector_size(16))) v2di; +diff --git a/gcc/testsuite/gcc.target/s390/vector/fp-unsignedint-convert-1.c b/gcc/testsuite/gcc.target/s390/vector/fp-unsignedint-convert-1.c +index 61409bcfc73..578e72f5682 100644 +--- a/gcc/testsuite/gcc.target/s390/vector/fp-unsignedint-convert-1.c ++++ b/gcc/testsuite/gcc.target/s390/vector/fp-unsignedint-convert-1.c +@@ -1,4 +1,4 @@ +-/* { dg-compile } */ ++/* { dg-do compile } */ + /* { dg-options "-O3 -march=z13 -mzarch" } */ + + typedef unsigned long long __attribute__((vector_size(16))) v2di; +diff --git a/gcc/testsuite/gcc.target/s390/vector/reverse-elements-1.c b/gcc/testsuite/gcc.target/s390/vector/reverse-elements-1.c +index 4a2541b7ae6..39e4a9b3e28 100644 +--- a/gcc/testsuite/gcc.target/s390/vector/reverse-elements-1.c ++++ b/gcc/testsuite/gcc.target/s390/vector/reverse-elements-1.c +@@ -1,4 +1,4 @@ +-/* { dg-compile } */ ++/* { dg-do compile } */ + /* { dg-options "-O3 -mzarch -march=z13" } */ + /* { dg-require-effective-target s390_vx } */ + /* { dg-final { scan-assembler-times {\tvpdi\t} 4 } } */ +diff --git a/gcc/testsuite/gcc.target/s390/vector/reverse-elements-2.c b/gcc/testsuite/gcc.target/s390/vector/reverse-elements-2.c +index ec0d1da7d57..25597042ee8 100644 +--- a/gcc/testsuite/gcc.target/s390/vector/reverse-elements-2.c ++++ b/gcc/testsuite/gcc.target/s390/vector/reverse-elements-2.c +@@ -1,4 +1,4 @@ +-/* { dg-compile } */ ++/* { dg-do compile } */ + /* { dg-options "-O3 -mzarch -march=z14" } */ + /* { dg-require-effective-target s390_vxe } */ + /* { dg-final { scan-assembler-times {\tvpdi\t} 1 } } */ +diff --git a/gcc/testsuite/gcc.target/s390/vector/reverse-elements-3.c b/gcc/testsuite/gcc.target/s390/vector/reverse-elements-3.c +index 3f69db8831c..ad0b8e6e604 100644 +--- a/gcc/testsuite/gcc.target/s390/vector/reverse-elements-3.c ++++ b/gcc/testsuite/gcc.target/s390/vector/reverse-elements-3.c +@@ -1,4 +1,4 @@ +-/* { dg-compile } */ ++/* { dg-do compile } */ + /* { dg-options "-O3 -mzarch -march=z14" } */ + /* { dg-require-effective-target s390_vxe } */ + /* { dg-final { scan-assembler-times {\tvpdi\t} 5 } } */ +diff --git a/gcc/testsuite/gcc.target/s390/vector/reverse-elements-4.c b/gcc/testsuite/gcc.target/s390/vector/reverse-elements-4.c +index 5027ed55f50..f386d559174 100644 +--- a/gcc/testsuite/gcc.target/s390/vector/reverse-elements-4.c ++++ b/gcc/testsuite/gcc.target/s390/vector/reverse-elements-4.c +@@ -1,4 +1,4 @@ +-/* { dg-compile } */ ++/* { dg-do compile } */ + /* { dg-options "-O3 -mzarch -march=z15" } */ + /* { dg-require-effective-target s390_vxe2 } */ + /* { dg-final { scan-assembler-times {\tvlbrq\t} 1 } } */ +diff --git a/gcc/testsuite/gcc.target/s390/vector/reverse-elements-5.c b/gcc/testsuite/gcc.target/s390/vector/reverse-elements-5.c +index 8c250aa681b..f7403784bfe 100644 +--- a/gcc/testsuite/gcc.target/s390/vector/reverse-elements-5.c ++++ b/gcc/testsuite/gcc.target/s390/vector/reverse-elements-5.c +@@ -1,4 +1,4 @@ +-/* { dg-compile } */ ++/* { dg-do compile } */ + /* { dg-options "-O3 -mzarch -march=z14" } */ + /* { dg-require-effective-target s390_vxe } */ + /* { dg-final { scan-assembler-times {\tvpdi\t} 5 } } */ +diff --git a/gcc/testsuite/gcc.target/s390/vector/reverse-elements-6.c b/gcc/testsuite/gcc.target/s390/vector/reverse-elements-6.c +index 7e2b2356788..a73109170d4 100644 +--- a/gcc/testsuite/gcc.target/s390/vector/reverse-elements-6.c ++++ b/gcc/testsuite/gcc.target/s390/vector/reverse-elements-6.c +@@ -1,4 +1,4 @@ +-/* { dg-compile } */ ++/* { dg-do compile } */ + /* { dg-options "-O3 -mzarch -march=z15" } */ + /* { dg-require-effective-target s390_vxe2 } */ + /* { dg-final { scan-assembler-times {\tvstbrq\t} 1 } } */ +diff --git a/gcc/testsuite/gcc.target/s390/vector/reverse-elements-7.c b/gcc/testsuite/gcc.target/s390/vector/reverse-elements-7.c +index 046fcc0790a..453b870a5a5 100644 +--- a/gcc/testsuite/gcc.target/s390/vector/reverse-elements-7.c ++++ b/gcc/testsuite/gcc.target/s390/vector/reverse-elements-7.c +@@ -1,4 +1,4 @@ +-/* { dg-compile } */ ++/* { dg-do compile } */ + /* { dg-options "-O3 -mzarch -march=z15" } */ + /* { dg-require-effective-target s390_vxe2 } */ + /* { dg-final { scan-assembler-times {\tvstbrq\t} 1 } } */ +diff --git a/gcc/testsuite/gnat.dg/alignment15.adb b/gcc/testsuite/gnat.dg/alignment15.adb +index e58243d2908..72d3746dff8 100644 +--- a/gcc/testsuite/gnat.dg/alignment15.adb ++++ b/gcc/testsuite/gnat.dg/alignment15.adb +@@ -1,4 +1,4 @@ +--- { dg-compile } ++-- { dg-do compile } + + procedure Alignment15 is + type T0 is record +diff --git a/gcc/testsuite/gnat.dg/debug4.adb b/gcc/testsuite/gnat.dg/debug4.adb +index 1ec37c2aa3b..1543cdca81c 100644 +--- a/gcc/testsuite/gnat.dg/debug4.adb ++++ b/gcc/testsuite/gnat.dg/debug4.adb +@@ -1,4 +1,4 @@ +--- { dg-compile } ++-- { dg-do compile } + -- { dg-options "-g" } + + with Debug4_Pkg; +diff --git a/gcc/testsuite/gnat.dg/inline21.adb b/gcc/testsuite/gnat.dg/inline21.adb +index 5df569158eb..5cdd3626898 100644 +--- a/gcc/testsuite/gnat.dg/inline21.adb ++++ b/gcc/testsuite/gnat.dg/inline21.adb +@@ -1,4 +1,4 @@ +--- { dg-compile } ++-- { dg-do compile } + -- { dg-options "-O -gnatn" } + + with Inline21_Q; +diff --git a/gcc/testsuite/gnat.dg/inline22.adb b/gcc/testsuite/gnat.dg/inline22.adb +index 5812c2f04df..00f94c8789b 100644 +--- a/gcc/testsuite/gnat.dg/inline22.adb ++++ b/gcc/testsuite/gnat.dg/inline22.adb +@@ -1,4 +1,4 @@ +--- { dg-compile } ++-- { dg-do compile } + + procedure Inline22 (L, U : Integer) is + +diff --git a/gcc/testsuite/gnat.dg/opt37.adb b/gcc/testsuite/gnat.dg/opt37.adb +index 0e3ee53a158..52585af77f0 100644 +--- a/gcc/testsuite/gnat.dg/opt37.adb ++++ b/gcc/testsuite/gnat.dg/opt37.adb +@@ -1,4 +1,4 @@ +--- { dg-compile } ++-- { dg-do compile } + -- { dg-options "-O2 -gnato -fdump-tree-optimized" } + + package body Opt37 is +diff --git a/gcc/testsuite/gnat.dg/warn13.adb b/gcc/testsuite/gnat.dg/warn13.adb +index 2a9c4e392cc..6fcd11a0c94 100644 +--- a/gcc/testsuite/gnat.dg/warn13.adb ++++ b/gcc/testsuite/gnat.dg/warn13.adb +@@ -1,4 +1,4 @@ +--- { dg-compile } ++-- { dg-do compile } + + procedure Warn13 is + +-- +2.47.3 + diff --git a/1061-RISC-V-NFC-Do-not-use-zicond-for-pr105314-testcases.patch b/1061-RISC-V-NFC-Do-not-use-zicond-for-pr105314-testcases.patch new file mode 100644 index 0000000..858cb55 --- /dev/null +++ b/1061-RISC-V-NFC-Do-not-use-zicond-for-pr105314-testcases.patch @@ -0,0 +1,64 @@ +From d7d1c922aaaf0f710d697a6e489cb1b7f056f12c Mon Sep 17 00:00:00 2001 +From: Xiao Zeng +Date: Thu, 25 Jul 2024 09:50:03 +0800 +Subject: [PATCH 1061/1087] RISC-V: NFC: Do not use zicond for pr105314 + testcases + +commit edad1b05010fedc7224515570592b2bd2153b21a upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/pr105314-rtl.c: Skip zicond. + * gcc.target/riscv/pr105314-rtl32.c: Ditto. + * gcc.target/riscv/pr105314.c: Ditto. + +Signed-off-by: Xiao Zeng +--- + gcc/testsuite/gcc.target/riscv/pr105314-rtl.c | 2 +- + gcc/testsuite/gcc.target/riscv/pr105314-rtl32.c | 2 +- + gcc/testsuite/gcc.target/riscv/pr105314.c | 2 +- + 3 files changed, 3 insertions(+), 3 deletions(-) + +diff --git a/gcc/testsuite/gcc.target/riscv/pr105314-rtl.c b/gcc/testsuite/gcc.target/riscv/pr105314-rtl.c +index 693291f4dbd..570918f9d9a 100644 +--- a/gcc/testsuite/gcc.target/riscv/pr105314-rtl.c ++++ b/gcc/testsuite/gcc.target/riscv/pr105314-rtl.c +@@ -1,7 +1,7 @@ + /* PR rtl-optimization/105314 */ + /* { dg-do compile } */ + /* { dg-require-effective-target rv64 } */ +-/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" "-flto" } } */ ++/* { dg-skip-if "" { *-*-* } { "-march=*zicond*" "-O0" "-Og" "-Os" "-Oz" "-flto" } } */ + /* { dg-options "-fdump-rtl-ce1" } */ + + long __RTL (startwith ("ce1")) +diff --git a/gcc/testsuite/gcc.target/riscv/pr105314-rtl32.c b/gcc/testsuite/gcc.target/riscv/pr105314-rtl32.c +index 9f9600f7679..018b6c43095 100644 +--- a/gcc/testsuite/gcc.target/riscv/pr105314-rtl32.c ++++ b/gcc/testsuite/gcc.target/riscv/pr105314-rtl32.c +@@ -1,7 +1,7 @@ + /* PR rtl-optimization/105314 */ + /* { dg-do compile } */ + /* { dg-require-effective-target rv32 } */ +-/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" "-flto" } } */ ++/* { dg-skip-if "" { *-*-* } { "-march=*zicond*" "-O0" "-Og" "-Os" "-Oz" "-flto" } } */ + /* { dg-options "-fdump-rtl-ce1" } */ + + long __RTL (startwith ("ce1")) +diff --git a/gcc/testsuite/gcc.target/riscv/pr105314.c b/gcc/testsuite/gcc.target/riscv/pr105314.c +index 1a7ea671791..75f6ecda2bb 100644 +--- a/gcc/testsuite/gcc.target/riscv/pr105314.c ++++ b/gcc/testsuite/gcc.target/riscv/pr105314.c +@@ -1,6 +1,6 @@ + /* PR rtl-optimization/105314 */ + /* { dg-do compile } */ +-/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ ++/* { dg-skip-if "" { *-*-* } { "-march=*zicond*" "-O0" "-Og" "-Os" "-Oz" } } */ + /* { dg-options "-fdump-rtl-ce1" } */ + + long +-- +2.47.3 + diff --git a/1062-RISC-V-Minimal-support-for-Zimop-extension.patch b/1062-RISC-V-Minimal-support-for-Zimop-extension.patch new file mode 100644 index 0000000..678230f --- /dev/null +++ b/1062-RISC-V-Minimal-support-for-Zimop-extension.patch @@ -0,0 +1,43 @@ +From 5e6e285a3217246d3161c4c7adef1dc696e66489 Mon Sep 17 00:00:00 2001 +From: Jiawei +Date: Fri, 2 Aug 2024 23:23:14 +0800 +Subject: [PATCH 1062/1087] RISC-V: Minimal support for Zimop extension. + +commit c8f3fdd53871a20838be532b58ef610bf1dd75e1 upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +This patch support Zimop and Zcmop extension[1].To enable GCC to recognize +and process Zimop and Zcmop extension correctly at compile time. + +https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc + +gcc/ChangeLog: + + * common/config/riscv/riscv-common.cc: New extension. + * config/riscv/riscv.opt: New mask. + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/arch-42.c: New test. + * gcc.target/riscv/arch-43.c: New test. +--- + gcc/common/config/riscv/riscv-common.cc | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc +index 7c172a039d2..4b65b608331 100644 +--- a/gcc/common/config/riscv/riscv-common.cc ++++ b/gcc/common/config/riscv/riscv-common.cc +@@ -97,6 +97,8 @@ static const riscv_implied_info_t riscv_implied_info[] = + {"zabha", "zaamo"}, + {"zacas", "zaamo"}, + ++ {"zcmop", "zca"}, ++ + {"b", "zba"}, + {"b", "zbb"}, + {"b", "zbs"}, +-- +2.47.3 + diff --git a/1063-RISC-V-testsuite-xtheadfmemidx-Rename-test-and-add-s.patch b/1063-RISC-V-testsuite-xtheadfmemidx-Rename-test-and-add-s.patch new file mode 100644 index 0000000..02d6281 --- /dev/null +++ b/1063-RISC-V-testsuite-xtheadfmemidx-Rename-test-and-add-s.patch @@ -0,0 +1,106 @@ +From 7b12c5471bc251964d383da53fa33e8118d71dec Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Christoph=20M=C3=BCllner?= +Date: Tue, 6 Aug 2024 07:24:07 +0200 +Subject: [PATCH 1063/1087] RISC-V: testsuite: xtheadfmemidx: Rename test and + add similar Zfa test +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +commit 8e6bc6dd2bb476fa97586b477bc98c670a3fcaf0 upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +Test file xtheadfmemidx-medany.c has been added in b79cd204c780 as a +test case that provoked an ICE when loading DFmode registers via two +SImode register loads followed by a SI->DF[63:32] move from XTheadFmv. +Since Zfa is affected in the same way as XTheadFmv, even if both +have slightly different instructions, let's add a test for Zfa as well +and give the tests proper names. + +Let's also add a test into the test files that counts the SI->DF moves +from XTheadFmv/Zfa. + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/xtheadfmemidx-medany.c: Move to... + * gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c: ...here. + * gcc.target/riscv/xtheadfmemidx-zfa-medany.c: New test. + +Signed-off-by: Christoph Müllner +--- + ...any.c => xtheadfmemidx-xtheadfmv-medany.c} | 5 ++- + .../riscv/xtheadfmemidx-zfa-medany.c | 39 +++++++++++++++++++ + 2 files changed, 42 insertions(+), 2 deletions(-) + rename gcc/testsuite/gcc.target/riscv/{xtheadfmemidx-medany.c => xtheadfmemidx-xtheadfmv-medany.c} (71%) + create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c + +diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-medany.c b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c +similarity index 71% +rename from gcc/testsuite/gcc.target/riscv/xtheadfmemidx-medany.c +rename to gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c +index 0c8060d0632..7c70b775824 100644 +--- a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-medany.c ++++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c +@@ -1,6 +1,6 @@ + /* { dg-do compile } */ +-/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-O3" "-Og" "-Os" "-Oz"} } */ +-/* { dg-options "-march=rv32gc_xtheadfmemidx_xtheadfmv_xtheadmemidx -mabi=ilp32d -mcmodel=medany -O2" } */ ++/* { dg-skip-if "" { *-*-* } { "-flto" "-O0" "-O1" "-Og" "-Os" "-Oz" } } */ ++/* { dg-options "-march=rv32gc_xtheadfmemidx_xtheadfmv_xtheadmemidx -mabi=ilp32d -mcmodel=medany" } */ + + typedef union { + double v; +@@ -36,3 +36,4 @@ double foo (int i, int j) + } + + /* { dg-final { scan-assembler-times {\mth\.flrd\M} 1 } } */ ++/* { dg-final { scan-assembler-times {\mth\.fmv\.hw\.x\M} 3 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c +new file mode 100644 +index 00000000000..4215eab1195 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c +@@ -0,0 +1,39 @@ ++/* { dg-do compile } */ ++/* { dg-skip-if "" { *-*-* } { "-flto" "-O0" "-O1" "-Og" "-Os" "-Oz" } } */ ++/* { dg-options "-march=rv32gc_zfa_xtheadfmemidx_xtheadmemidx -mabi=ilp32d -mcmodel=medany" } */ ++ ++typedef union { ++ double v; ++ unsigned w; ++} my_t; ++ ++double z; ++ ++double foo (int i, int j) ++{ ++ ++ if (j) ++ { ++ switch (i) ++ { ++ case 0: ++ return 1; ++ case 1: ++ return 0; ++ case 2: ++ return 3.0; ++ } ++ } ++ ++ if (i == 1) ++ { ++ my_t u; ++ u.v = z; ++ u.w = 1; ++ z = u.v; ++ } ++ return z; ++} ++ ++/* { dg-final { scan-assembler-times {\mth\.flrd\M} 1 } } */ ++/* { dg-final { scan-assembler-times {\mfmvp\.d\.x\M} 3 } } */ +-- +2.47.3 + diff --git a/1064-RISC-V-Add-intrinsic-support-for-the-CMOs-extensions.patch b/1064-RISC-V-Add-intrinsic-support-for-the-CMOs-extensions.patch new file mode 100644 index 0000000..3d6d96b --- /dev/null +++ b/1064-RISC-V-Add-intrinsic-support-for-the-CMOs-extensions.patch @@ -0,0 +1,126 @@ +From dcb38554c6d72908e4ec31db31fdf3b3971a79c2 Mon Sep 17 00:00:00 2001 +From: yulong +Date: Tue, 29 Oct 2024 08:43:42 -0600 +Subject: [PATCH 1064/1087] RISC-V:Add intrinsic support for the CMOs + extensions + +commit d2c8548e0ce51dac6bc51d37236c50f98fca82f0 upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +gcc/ChangeLog: + + * config.gcc: Add riscv_cmo.h. + * config/riscv/riscv_cmo.h: New file. +--- + gcc/config.gcc | 2 +- + gcc/config/riscv/riscv_cmo.h | 84 ++++++++++++++++++++++++++++++++++++ + 2 files changed, 85 insertions(+), 1 deletion(-) + create mode 100644 gcc/config/riscv/riscv_cmo.h + +diff --git a/gcc/config.gcc b/gcc/config.gcc +index a3566f5c77d..6cdaa1e80a6 100644 +--- a/gcc/config.gcc ++++ b/gcc/config.gcc +@@ -553,7 +553,7 @@ riscv*) + extra_objs="${extra_objs} riscv-vector-builtins.o riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o" + extra_objs="${extra_objs} thead.o riscv-target-attr.o" + d_target_objs="riscv-d.o" +- extra_headers="riscv_vector.h riscv_crypto.h riscv_bitmanip.h riscv_th_vector.h" ++ extra_headers="riscv_vector.h riscv_crypto.h riscv_bitmanip.h riscv_th_vector.h riscv_cmo.h" + target_gtfiles="$target_gtfiles \$(srcdir)/config/riscv/riscv-vector-builtins.cc" + target_gtfiles="$target_gtfiles \$(srcdir)/config/riscv/riscv-vector-builtins.h" + ;; +diff --git a/gcc/config/riscv/riscv_cmo.h b/gcc/config/riscv/riscv_cmo.h +new file mode 100644 +index 00000000000..3514fd3f0fe +--- /dev/null ++++ b/gcc/config/riscv/riscv_cmo.h +@@ -0,0 +1,84 @@ ++/* RISC-V CMO Extension intrinsics include file. ++ Copyright (C) 2024 Free Software Foundation, Inc. ++ ++ This file is part of GCC. ++ ++ GCC is free software; you can redistribute it and/or modify it ++ under the terms of the GNU General Public License as published ++ by the Free Software Foundation; either version 3, or (at your ++ option) any later version. ++ ++ GCC is distributed in the hope that it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY ++ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public ++ License for more details. ++ ++ Under Section 7 of GPL version 3, you are granted additional ++ permissions described in the GCC Runtime Library Exception, version ++ 3.1, as published by the Free Software Foundation. ++ ++ You should have received a copy of the GNU General Public License and ++ a copy of the GCC Runtime Library Exception along with this program; ++ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see ++ . */ ++ ++#ifndef __RISCV_CMO_H ++#define __RISCV_CMO_H ++ ++#if defined (__riscv_zicbom) ++ ++extern __inline void ++__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) ++__riscv_cmo_clean (void *addr) ++{ ++ __builtin_riscv_zicbom_cbo_clean (addr); ++} ++ ++extern __inline void ++__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) ++__riscv_cmo_flush (void *addr) ++{ ++ __builtin_riscv_zicbom_cbo_flush (addr); ++} ++ ++extern __inline void ++__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) ++__riscv_cmo_inval (void *addr) ++{ ++ __builtin_riscv_zicbom_cbo_inval (addr); ++} ++ ++#endif // __riscv_zicbom ++ ++#if defined (__riscv_zicbop) ++ ++# define rnum 1 ++ ++extern __inline void ++__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) ++__riscv_cmo_prefetch (void *addr, const int vs1, const int vs2) ++{ ++ __builtin_prefetch (addr,vs1,vs2); ++} ++ ++extern __inline int ++__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) ++__riscv_cmo_prefetchi () ++{ ++ return __builtin_riscv_zicbop_cbo_prefetchi (rnum); ++} ++ ++#endif // __riscv_zicbop ++ ++#if defined (__riscv_zicboz) ++ ++extern __inline void ++__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) ++__riscv_cmo_zero (void *addr) ++{ ++ __builtin_riscv_zicboz_cbo_zero (addr); ++} ++ ++#endif // __riscv_zicboz ++ ++#endif // __RISCV_CMO_H +-- +2.47.3 + diff --git a/1065-RISC-V-Add-intrinsic-cases-for-the-CMOs-extensions.patch b/1065-RISC-V-Add-intrinsic-cases-for-the-CMOs-extensions.patch new file mode 100644 index 0000000..1894d16 --- /dev/null +++ b/1065-RISC-V-Add-intrinsic-cases-for-the-CMOs-extensions.patch @@ -0,0 +1,151 @@ +From 2d52560898e79493ea1424b41961812c13730cac Mon Sep 17 00:00:00 2001 +From: yulong +Date: Tue, 29 Oct 2024 08:44:45 -0600 +Subject: [PATCH 1065/1087] RISC-V:Add intrinsic cases for the CMOs extensions + +commit b22d9c8f8216d15773dee4f9677c6b26aff507fd upstream + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/cmo-32.c: New test. + * gcc.target/riscv/cmo-64.c: New test. +--- + gcc/testsuite/gcc.target/riscv/cmo-32.c | 58 +++++++++++++++++++++++++ + gcc/testsuite/gcc.target/riscv/cmo-64.c | 58 +++++++++++++++++++++++++ + 2 files changed, 116 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-32.c + create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-64.c + +diff --git a/gcc/testsuite/gcc.target/riscv/cmo-32.c b/gcc/testsuite/gcc.target/riscv/cmo-32.c +new file mode 100644 +index 00000000000..8e733cc05fc +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/cmo-32.c +@@ -0,0 +1,58 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target rv32} */ ++/* { dg-options "-march=rv32gc_zicbom_zicbop_zicboz -mabi=ilp32" } */ ++ ++#include "riscv_cmo.h" ++ ++void foo1 (void *addr) ++{ ++ __riscv_cmo_clean(0); ++ __riscv_cmo_clean(addr); ++ __riscv_cmo_clean((void*)0x111); ++} ++ ++void foo2 (void *addr) ++{ ++ __riscv_cmo_flush(0); ++ __riscv_cmo_flush(addr); ++ __riscv_cmo_flush((void*)0x111); ++} ++ ++void foo3 (void *addr) ++{ ++ __riscv_cmo_inval(0); ++ __riscv_cmo_inval(addr); ++ __riscv_cmo_inval((void*)0x111); ++} ++ ++void foo4 (void *addr) ++{ ++ __riscv_cmo_prefetch(addr,0,0); ++ __riscv_cmo_prefetch(addr,0,1); ++ __riscv_cmo_prefetch(addr,0,2); ++ __riscv_cmo_prefetch(addr,0,3); ++ __riscv_cmo_prefetch(addr,1,0); ++ __riscv_cmo_prefetch(addr,1,1); ++ __riscv_cmo_prefetch(addr,1,2); ++ __riscv_cmo_prefetch(addr,1,3); ++} ++ ++int foo5 (int num) ++{ ++ return __riscv_cmo_prefetchi(num); ++} ++ ++void foo6 (void *addr) ++{ ++ __riscv_cmo_zero(0); ++ __riscv_cmo_zero(addr); ++ __riscv_cmo_zero((void*)0x121); ++} ++ ++/* { dg-final { scan-assembler-times "cbo.clean\t" 3 } } */ ++/* { dg-final { scan-assembler-times "cbo.flush\t" 3 } } */ ++/* { dg-final { scan-assembler-times "cbo.inval\t" 3 } } */ ++/* { dg-final { scan-assembler-times "prefetch.r\t" 4 } } */ ++/* { dg-final { scan-assembler-times "prefetch.w\t" 4 } } */ ++/* { dg-final { scan-assembler-times "prefetch.i\t" 1 } } */ ++/* { dg-final { scan-assembler-times "cbo.zero\t" 3 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/cmo-64.c b/gcc/testsuite/gcc.target/riscv/cmo-64.c +new file mode 100644 +index 00000000000..e83eddbeb6f +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/cmo-64.c +@@ -0,0 +1,58 @@ ++/* { dg-do compile } */ ++/* { dg-require-effective-target rv64 } */ ++/* { dg-options "-march=rv64gc_zicbom_zicbop_zicboz -mabi=lp64d" } */ ++ ++#include "riscv_cmo.h" ++ ++void foo1 (void *addr) ++{ ++ __riscv_cmo_clean(0); ++ __riscv_cmo_clean(addr); ++ __riscv_cmo_clean((void*)0x111); ++} ++ ++void foo2 (void *addr) ++{ ++ __riscv_cmo_flush(0); ++ __riscv_cmo_flush(addr); ++ __riscv_cmo_flush((void*)0x111); ++} ++ ++void foo3 (void *addr) ++{ ++ __riscv_cmo_inval(0); ++ __riscv_cmo_inval(addr); ++ __riscv_cmo_inval((void*)0x111); ++} ++ ++void foo4 (void *addr) ++{ ++ __riscv_cmo_prefetch(addr,0,0); ++ __riscv_cmo_prefetch(addr,0,1); ++ __riscv_cmo_prefetch(addr,0,2); ++ __riscv_cmo_prefetch(addr,0,3); ++ __riscv_cmo_prefetch(addr,1,0); ++ __riscv_cmo_prefetch(addr,1,1); ++ __riscv_cmo_prefetch(addr,1,2); ++ __riscv_cmo_prefetch(addr,1,3); ++} ++ ++int foo5 (int num) ++{ ++ return __riscv_cmo_prefetchi(num); ++} ++ ++void foo6 (void *addr) ++{ ++ __riscv_cmo_zero(0); ++ __riscv_cmo_zero(addr); ++ __riscv_cmo_zero((void*)0x121); ++} ++ ++/* { dg-final { scan-assembler-times "cbo.clean\t" 3 } } */ ++/* { dg-final { scan-assembler-times "cbo.flush\t" 3 } } */ ++/* { dg-final { scan-assembler-times "cbo.inval\t" 3 } } */ ++/* { dg-final { scan-assembler-times "prefetch.r\t" 4 } } */ ++/* { dg-final { scan-assembler-times "prefetch.w\t" 4 } } */ ++/* { dg-final { scan-assembler-times "prefetch.i\t" 1 } } */ ++/* { dg-final { scan-assembler-times "cbo.zero\t" 3 } } */ +-- +2.47.3 + diff --git a/1066-RISC-V-Add-implication-for-M-extension.patch b/1066-RISC-V-Add-implication-for-M-extension.patch new file mode 100644 index 0000000..28bf8a2 --- /dev/null +++ b/1066-RISC-V-Add-implication-for-M-extension.patch @@ -0,0 +1,306 @@ +From dff87a37011c03a31d17da94dd6f9bb0aaa65395 Mon Sep 17 00:00:00 2001 +From: Tsung Chun Lin +Date: Tue, 29 Oct 2024 09:47:57 -0600 +Subject: [PATCH 1066/1087] RISC-V: Add implication for M extension. + +That M implies Zmmul. + +gcc/ChangeLog: + + * common/config/riscv/riscv-common.cc: M implies Zmmul. + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/attribute-15.c: Add _zmmul1p0 to arch string. + * gcc.target/riscv/attribute-16.c: Ditto. + * gcc.target/riscv/attribute-17.c: Ditto. + * gcc.target/riscv/attribute-18.c: Ditto. + * gcc.target/riscv/attribute-19.c: Ditto. + * gcc.target/riscv/pr110696.c: Ditto. + * gcc.target/riscv/target-attr-01.c: Ditto. + * gcc.target/riscv/target-attr-02.c: Ditto. + * gcc.target/riscv/target-attr-03.c: Ditto. + * gcc.target/riscv/target-attr-04.c: Ditto. + * gcc.target/riscv/target-attr-08.c: Ditto. + * gcc.target/riscv/target-attr-11.c: Ditto. + * gcc.target/riscv/target-attr-14.c: Ditto. + * gcc.target/riscv/target-attr-15.c: Ditto. + * gcc.target/riscv/target-attr-16.c: Ditto. + * gcc.target/riscv/rvv/base/pr114352-1.c: Likewise. + * gcc.target/riscv/rvv/base/pr114352-3.c: Likewise. + * gcc.dg/pr90838.c: Fix search string for rv64. + + Co-Authored-By: Jeff Law +--- + gcc/common/config/riscv/riscv-common.cc | 2 ++ + gcc/testsuite/gcc.dg/pr90838.c | 2 +- + gcc/testsuite/gcc.target/riscv/attribute-15.c | 2 +- + gcc/testsuite/gcc.target/riscv/attribute-16.c | 2 +- + gcc/testsuite/gcc.target/riscv/attribute-17.c | 2 +- + gcc/testsuite/gcc.target/riscv/attribute-18.c | 2 +- + gcc/testsuite/gcc.target/riscv/attribute-19.c | 2 +- + gcc/testsuite/gcc.target/riscv/pr110696.c | 2 +- + gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c | 4 ++-- + gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c | 8 ++++---- + gcc/testsuite/gcc.target/riscv/target-attr-01.c | 2 +- + gcc/testsuite/gcc.target/riscv/target-attr-02.c | 2 +- + gcc/testsuite/gcc.target/riscv/target-attr-03.c | 2 +- + gcc/testsuite/gcc.target/riscv/target-attr-04.c | 2 +- + gcc/testsuite/gcc.target/riscv/target-attr-08.c | 2 +- + gcc/testsuite/gcc.target/riscv/target-attr-11.c | 2 +- + gcc/testsuite/gcc.target/riscv/target-attr-14.c | 4 ++-- + gcc/testsuite/gcc.target/riscv/target-attr-15.c | 4 ++-- + gcc/testsuite/gcc.target/riscv/target-attr-16.c | 4 ++-- + 19 files changed, 27 insertions(+), 25 deletions(-) + +diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc +index 4b65b608331..edfe65aa488 100644 +--- a/gcc/common/config/riscv/riscv-common.cc ++++ b/gcc/common/config/riscv/riscv-common.cc +@@ -75,6 +75,8 @@ struct riscv_implied_info_t + /* Implied ISA info, must end with NULL sentinel. */ + static const riscv_implied_info_t riscv_implied_info[] = + { ++ {"m", "zmmul"}, ++ + {"d", "f"}, + {"f", "zicsr"}, + {"d", "zicsr"}, +diff --git a/gcc/testsuite/gcc.dg/pr90838.c b/gcc/testsuite/gcc.dg/pr90838.c +index 40aad70499d..db7bcec3ea9 100644 +--- a/gcc/testsuite/gcc.dg/pr90838.c ++++ b/gcc/testsuite/gcc.dg/pr90838.c +@@ -77,7 +77,7 @@ int ctz4 (unsigned long x) + /* { dg-final { scan-assembler-times "ctz\t" 1 { target { rv64 } } } } */ + /* { dg-final { scan-assembler-times "ctzw\t" 3 { target { rv64 } } } } */ + /* { dg-final { scan-assembler-times "andi\t" 2 { target { rv64 } } } } */ +-/* { dg-final { scan-assembler-not "mul" { target { rv64 } } } } */ ++/* { dg-final { scan-assembler-not "mul\t" { target { rv64 } } } } */ + + /* { dg-final { scan-tree-dump-times {= \.CTZ} 3 "forwprop2" { target { rv32 } } } } */ + /* { dg-final { scan-assembler-times "ctz\t" 3 { target { rv32 } } } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/attribute-15.c b/gcc/testsuite/gcc.target/riscv/attribute-15.c +index ac6caaecd4f..d7a70e86aa1 100644 +--- a/gcc/testsuite/gcc.target/riscv/attribute-15.c ++++ b/gcc/testsuite/gcc.target/riscv/attribute-15.c +@@ -3,4 +3,4 @@ + int foo() + { + } +-/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0\"" } } */ ++/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0\"" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/attribute-16.c b/gcc/testsuite/gcc.target/riscv/attribute-16.c +index 539e426ca97..4818cbe90d4 100644 +--- a/gcc/testsuite/gcc.target/riscv/attribute-16.c ++++ b/gcc/testsuite/gcc.target/riscv/attribute-16.c +@@ -3,4 +3,4 @@ + int foo() + { + } +-/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_m2p0_a2p0_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0\"" } } */ ++/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_m2p0_a2p0_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0\"" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/attribute-17.c b/gcc/testsuite/gcc.target/riscv/attribute-17.c +index 30928cb5b68..64b11b6a28c 100644 +--- a/gcc/testsuite/gcc.target/riscv/attribute-17.c ++++ b/gcc/testsuite/gcc.target/riscv/attribute-17.c +@@ -3,4 +3,4 @@ + int foo() + { + } +-/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0\"" } } */ ++/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0\"" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/attribute-18.c b/gcc/testsuite/gcc.target/riscv/attribute-18.c +index 9f7199f331a..43ae37b5089 100644 +--- a/gcc/testsuite/gcc.target/riscv/attribute-18.c ++++ b/gcc/testsuite/gcc.target/riscv/attribute-18.c +@@ -1,4 +1,4 @@ + /* { dg-do compile } */ + /* { dg-options "-mriscv-attribute -march=rv64imafdc -mabi=lp64d -misa-spec=2.2" } */ + int foo() {} +-/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0\"" } } */ ++/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0\"" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/attribute-19.c b/gcc/testsuite/gcc.target/riscv/attribute-19.c +index 8150452f5b1..c9301589a19 100644 +--- a/gcc/testsuite/gcc.target/riscv/attribute-19.c ++++ b/gcc/testsuite/gcc.target/riscv/attribute-19.c +@@ -1,4 +1,4 @@ + /* { dg-do compile } */ + /* { dg-options "-mriscv-attribute -march=rv64im -mabi=lp64 -misa-spec=2.2" } */ + int foo() {} +-/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p0_m2p0\"" } } */ ++/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p0_m2p0_zmmul1p0\"" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/pr110696.c b/gcc/testsuite/gcc.target/riscv/pr110696.c +index aae2afc6b28..8fb373d6c6b 100644 +--- a/gcc/testsuite/gcc.target/riscv/pr110696.c ++++ b/gcc/testsuite/gcc.target/riscv/pr110696.c +@@ -4,4 +4,4 @@ int foo() + { + } + +-/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0\"" } } */ ++/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0\"" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c +index 300d87324c6..c21be05889e 100644 +--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c ++++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c +@@ -54,5 +54,5 @@ test_3 (int *a, int *b, int *out, unsigned count) + out[i] = a[i] + b[i]; + } + +-/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0\"" } } */ +-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */ ++/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0\"" } } */ ++/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c +index da7a44ba08a..a764afbbbc1 100644 +--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c ++++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c +@@ -107,7 +107,7 @@ test_6 (_Float16 *a, _Float16 *b, _Float16 *out, unsigned count) + out[i] = a[i] + b[i]; + } + +-/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0\"" } } */ +-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */ +-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zbb1p0" } } */ +-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zfh1p0_zfhmin1p0_zca1p0_zcd1p0" } } */ ++/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0\"" } } */ ++/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */ ++/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zbb1p0" } } */ ++/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zfh1p0_zfhmin1p0_zca1p0_zcd1p0" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/target-attr-01.c b/gcc/testsuite/gcc.target/riscv/target-attr-01.c +index 1bf108e9d72..9830ab2f1b6 100644 +--- a/gcc/testsuite/gcc.target/riscv/target-attr-01.c ++++ b/gcc/testsuite/gcc.target/riscv/target-attr-01.c +@@ -9,7 +9,7 @@ + ** sh1add\s*a0,a1,a0 + ** ... + */ +-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zba1p0" } } */ ++/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0" } } */ + long foo () __attribute__((target("arch=rv64gc_zba"))); + long foo (long a, long b) + { +diff --git a/gcc/testsuite/gcc.target/riscv/target-attr-02.c b/gcc/testsuite/gcc.target/riscv/target-attr-02.c +index 3d0c8a72f59..3338ae46942 100644 +--- a/gcc/testsuite/gcc.target/riscv/target-attr-02.c ++++ b/gcc/testsuite/gcc.target/riscv/target-attr-02.c +@@ -9,7 +9,7 @@ + ** sh1add\s*a0,a1,a0 + ** ... + */ +-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zba1p0" } } */ ++/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0" } } */ + long foo () __attribute__((target("arch=+zba"))); + long foo (long a, long b) + { +diff --git a/gcc/testsuite/gcc.target/riscv/target-attr-03.c b/gcc/testsuite/gcc.target/riscv/target-attr-03.c +index 1cba2c25744..673c0670106 100644 +--- a/gcc/testsuite/gcc.target/riscv/target-attr-03.c ++++ b/gcc/testsuite/gcc.target/riscv/target-attr-03.c +@@ -10,7 +10,7 @@ + ** add\s*a0,a1,a0 + ** ... + */ +-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0" } } */ ++/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0" } } */ + long foo () __attribute__((target("arch=rv64gc"))); + long foo (long a, long b) + { +diff --git a/gcc/testsuite/gcc.target/riscv/target-attr-04.c b/gcc/testsuite/gcc.target/riscv/target-attr-04.c +index 1193dcfa30e..58c1698fac3 100644 +--- a/gcc/testsuite/gcc.target/riscv/target-attr-04.c ++++ b/gcc/testsuite/gcc.target/riscv/target-attr-04.c +@@ -12,7 +12,7 @@ + ** add\s*a0,a1,a0 + ** ... + */ +-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0" } } */ ++/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zmmul1p0_zaamo1p0_zalrsc1p0" } } */ + long foo () __attribute__((target("cpu=sifive-u74"))); + long foo (long a, long b) + { +diff --git a/gcc/testsuite/gcc.target/riscv/target-attr-08.c b/gcc/testsuite/gcc.target/riscv/target-attr-08.c +index 43c7141139e..3cab5ff803c 100644 +--- a/gcc/testsuite/gcc.target/riscv/target-attr-08.c ++++ b/gcc/testsuite/gcc.target/riscv/target-attr-08.c +@@ -13,7 +13,7 @@ __attribute__((target("arch=rv64gc_zba"))); + ** sh1add\s*a0,a1,a0 + ** ... + */ +-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zba1p0" } } */ ++/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0" } } */ + long foo (long a, long b) + { + return a + (b * 2); +diff --git a/gcc/testsuite/gcc.target/riscv/target-attr-11.c b/gcc/testsuite/gcc.target/riscv/target-attr-11.c +index b79e6de6468..0a215b4ae9c 100644 +--- a/gcc/testsuite/gcc.target/riscv/target-attr-11.c ++++ b/gcc/testsuite/gcc.target/riscv/target-attr-11.c +@@ -15,7 +15,7 @@ __attribute__((target("arch=rv64gc_zba"))); + ** sh1add\s*a0,a1,a0 + ** ... + */ +-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zba1p0" } } */ ++/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0" } } */ + long foo (long a, long b) + { + return a + (b * 2); +diff --git a/gcc/testsuite/gcc.target/riscv/target-attr-14.c b/gcc/testsuite/gcc.target/riscv/target-attr-14.c +index ad42c389287..4e615dbb323 100644 +--- a/gcc/testsuite/gcc.target/riscv/target-attr-14.c ++++ b/gcc/testsuite/gcc.target/riscv/target-attr-14.c +@@ -9,7 +9,7 @@ + ** sh1add\s*a0,a1,a0 + ** ... + */ +-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zba1p0" } } */ ++/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0" } } */ + long foo () __attribute__((target("arch=rv64gc_zba"))); + long foo (long a, long b) + { +@@ -34,7 +34,7 @@ long bar (long a, long b) + ** th.addsl\s*a0,a0,a1,1 + ** ... + */ +-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_xtheadba1p0" } } */ ++/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_xtheadba1p0" } } */ + long foo_th () __attribute__((target("arch=rv64gc_xtheadba"))); + long foo_th (long a, long b) + { +diff --git a/gcc/testsuite/gcc.target/riscv/target-attr-15.c b/gcc/testsuite/gcc.target/riscv/target-attr-15.c +index 586cc581c86..bccb81aaad9 100644 +--- a/gcc/testsuite/gcc.target/riscv/target-attr-15.c ++++ b/gcc/testsuite/gcc.target/riscv/target-attr-15.c +@@ -9,7 +9,7 @@ + ** sh1add\s*a0,a1,a0 + ** ... + */ +-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zba1p0" } } */ ++/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0" } } */ + long foo () __attribute__((target("arch=rv64gc_zba"))); + long foo (long a, long b) + { +@@ -34,7 +34,7 @@ long bar (long a, long b) + ** th.addsl\s*a0,a0,a1,1 + ** ... + */ +-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_xtheadba1p0" } } */ ++/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_xtheadba1p0" } } */ + long foo_th () __attribute__((target("arch=+xtheadba"))); + long foo_th (long a, long b) + { +diff --git a/gcc/testsuite/gcc.target/riscv/target-attr-16.c b/gcc/testsuite/gcc.target/riscv/target-attr-16.c +index 81ef2d72792..9c5c9617ea0 100644 +--- a/gcc/testsuite/gcc.target/riscv/target-attr-16.c ++++ b/gcc/testsuite/gcc.target/riscv/target-attr-16.c +@@ -24,5 +24,5 @@ void bar (void) + { + } + +-/* { dg-final { scan-assembler-times ".option arch, rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zba1p0_zbb1p0" 4 { target { rv32 } } } } */ +-/* { dg-final { scan-assembler-times ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zba1p0_zbb1p0" 4 { target { rv64 } } } } */ ++/* { dg-final { scan-assembler-times ".option arch, rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0_zbb1p0" 4 { target { rv32 } } } } */ ++/* { dg-final { scan-assembler-times ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0_zbb1p0" 4 { target { rv64 } } } } */ +-- +2.47.3 + diff --git a/1067-RISC-V-Error-early-with-V-and-no-M-extension.patch b/1067-RISC-V-Error-early-with-V-and-no-M-extension.patch new file mode 100644 index 0000000..1edeedd --- /dev/null +++ b/1067-RISC-V-Error-early-with-V-and-no-M-extension.patch @@ -0,0 +1,116 @@ +From 70e298a9056f459702e427fad9e29cc84e194bb3 Mon Sep 17 00:00:00 2001 +From: Robin Dapp +Date: Wed, 24 Jul 2024 09:08:00 +0200 +Subject: [PATCH 1067/1087] RISC-V: Error early with V and no M extension. + +commit e589ffb6d78881572ddea21df0d9b6c2641d574d upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +For calculating the value of a poly_int at runtime we use a +multiplication instruction that requires the M extension. +Instead of just asserting and ICEing this patch emits an early +error at option-parsing time. + +gcc/ChangeLog: + + PR target/116036 + + * config/riscv/riscv.cc (riscv_override_options_internal): Error + with TARGET_VECTOR && !TARGET_MUL. + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/arch-31.c: Add m to arch string and expect it. + * gcc.target/riscv/arch-32.c: Ditto. + * gcc.target/riscv/arch-37.c: Ditto. + * gcc.target/riscv/arch-38.c: Ditto. + * gcc.target/riscv/predef-14.c: Ditto. + * gcc.target/riscv/predef-15.c: Ditto. + * gcc.target/riscv/predef-16.c: Ditto. + * gcc.target/riscv/predef-26.c: Ditto. + * gcc.target/riscv/predef-27.c: Ditto. + * gcc.target/riscv/predef-32.c: Ditto. + * gcc.target/riscv/predef-33.c: Ditto. + * gcc.target/riscv/predef-36.c: Ditto. + * gcc.target/riscv/predef-37.c: Ditto. + * gcc.target/riscv/rvv/autovec/pr111486.c: Add m to arch string. + * gcc.target/riscv/compare-debug-1.c: Ditto. + * gcc.target/riscv/compare-debug-2.c: Ditto. + * gcc.target/riscv/rvv/base/pr116036.c: New test. +--- + gcc/testsuite/gcc.target/riscv/arch-37.c | 2 +- + gcc/testsuite/gcc.target/riscv/arch-38.c | 2 +- + gcc/testsuite/gcc.target/riscv/predef-36.c | 6 +++++- + gcc/testsuite/gcc.target/riscv/predef-37.c | 6 +++++- + 4 files changed, 12 insertions(+), 4 deletions(-) + +diff --git a/gcc/testsuite/gcc.target/riscv/arch-37.c b/gcc/testsuite/gcc.target/riscv/arch-37.c +index 5b19a73c556..b56ba77b973 100644 +--- a/gcc/testsuite/gcc.target/riscv/arch-37.c ++++ b/gcc/testsuite/gcc.target/riscv/arch-37.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* { dg-options "-march=rv32i_zvfbfwma -mabi=ilp32f" } */ ++/* { dg-options "-march=rv32im_zvfbfwma -mabi=ilp32f" } */ + int + foo () + {} +diff --git a/gcc/testsuite/gcc.target/riscv/arch-38.c b/gcc/testsuite/gcc.target/riscv/arch-38.c +index cee3efebe75..164a91e38a3 100644 +--- a/gcc/testsuite/gcc.target/riscv/arch-38.c ++++ b/gcc/testsuite/gcc.target/riscv/arch-38.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* { dg-options "-march=rv64iv_zvfbfwma -mabi=lp64d" } */ ++/* { dg-options "-march=rv64imv_zvfbfwma -mabi=lp64d" } */ + int + foo () + {} +diff --git a/gcc/testsuite/gcc.target/riscv/predef-36.c b/gcc/testsuite/gcc.target/riscv/predef-36.c +index b0205b08513..7c87a42f3d3 100644 +--- a/gcc/testsuite/gcc.target/riscv/predef-36.c ++++ b/gcc/testsuite/gcc.target/riscv/predef-36.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* { dg-options "-O2 -march=rv32i_zvfbfwma -mabi=ilp32f -mcmodel=medlow -misa-spec=20191213" } */ ++/* { dg-options "-O2 -march=rv32im_zvfbfwma -mabi=ilp32f -mcmodel=medlow -misa-spec=20191213" } */ + + int + main () +@@ -16,6 +16,10 @@ main () + #error "__riscv_i" + #endif + ++#if !defined(__riscv_m) ++#error "__riscv_m" ++#endif ++ + #if !defined(__riscv_f) + #error "__riscv_f" + #endif +diff --git a/gcc/testsuite/gcc.target/riscv/predef-37.c b/gcc/testsuite/gcc.target/riscv/predef-37.c +index b5aa41102f4..150150e3246 100644 +--- a/gcc/testsuite/gcc.target/riscv/predef-37.c ++++ b/gcc/testsuite/gcc.target/riscv/predef-37.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* { dg-options "-O2 -march=rv64iv_zvfbfwma -mabi=lp64d -mcmodel=medlow -misa-spec=20191213" } */ ++/* { dg-options "-O2 -march=rv64imv_zvfbfwma -mabi=lp64d -mcmodel=medlow -misa-spec=20191213" } */ + + int + main () +@@ -16,6 +16,10 @@ main () + #error "__riscv_i" + #endif + ++#if !defined(__riscv_m) ++#error "__riscv_m" ++#endif ++ + #if !defined(__riscv_f) + #error "__riscv_f" + #endif +-- +2.47.3 + diff --git a/1068-RISC-V-Fix-program-logic-errors-caused-by-data-trunc.patch b/1068-RISC-V-Fix-program-logic-errors-caused-by-data-trunc.patch new file mode 100644 index 0000000..ed40706 --- /dev/null +++ b/1068-RISC-V-Fix-program-logic-errors-caused-by-data-trunc.patch @@ -0,0 +1,80 @@ +From c26fefda3c788d7b29c60fa48051969e28ef23b7 Mon Sep 17 00:00:00 2001 +From: Jin Ma +Date: Mon, 13 Jan 2025 10:10:22 -0700 +Subject: [PATCH 1068/1087] RISC-V: Fix program logic errors caused by data + truncation on 32-bit host for zbs, such as i386 + +commit ecf688edc217472774817cc1284e75a9f72fe1b4 upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +Correct logic on 64-bit host: + ... + bseti a5,zero,38 + bseti a5,a5,63 + addi a5,a5,-1 + and a4,a4,a5 + ... + +Wrong logic on 32-bit host: + ... + li a5,64 + bseti a5,a5,31 + addi a5,a5,-1 + and a4,a4,a5 + ... + +gcc/ChangeLog: + + * config/riscv/riscv.cc (riscv_build_integer_1): Change + 1UL/1ULL to HOST_WIDE_INT_1U. + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/zbs-bug.c: New test. +--- + gcc/config/riscv/riscv.cc | 4 ++-- + gcc/testsuite/gcc.target/riscv/zbs-bug.c | 15 +++++++++++++++ + 2 files changed, 17 insertions(+), 2 deletions(-) + create mode 100644 gcc/testsuite/gcc.target/riscv/zbs-bug.c + +diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc +index 87bd5a89b19..1e9b77b81ca 100644 +--- a/gcc/config/riscv/riscv.cc ++++ b/gcc/config/riscv/riscv.cc +@@ -922,9 +922,9 @@ riscv_build_integer_1 (struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS], + { + HOST_WIDE_INT bit = ctz_hwi (value); + alt_codes[i].code = (i == 0 ? UNKNOWN : IOR); +- alt_codes[i].value = 1UL << bit; ++ alt_codes[i].value = HOST_WIDE_INT_1U << bit; + alt_codes[i].use_uw = false; +- value &= ~(1ULL << bit); ++ value &= ~(HOST_WIDE_INT_1U << bit); + i++; + } + +diff --git a/gcc/testsuite/gcc.target/riscv/zbs-bug.c b/gcc/testsuite/gcc.target/riscv/zbs-bug.c +new file mode 100644 +index 00000000000..10dde580133 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/zbs-bug.c +@@ -0,0 +1,15 @@ ++/* { dg-do compile { target { rv64 } } } */ ++/* { dg-skip-if "" { *-*-* } { "-O1" "-O2" "-O3" "-Og" "-Os" "-Oz" } } */ ++/* { dg-options "-march=rv64gc_zbb_zbs -mabi=lp64d -O0" } */ ++ ++struct a { ++ unsigned : 29; ++ signed : 6; ++ signed b : 25; ++}; ++ ++void c() { ++ struct a d = {808}; ++} ++ ++/* { dg-final { scan-assembler-not "bseti.*31" } }*/ +-- +2.47.3 + diff --git a/1069-RISC-V-Add-vector-popcount-clz-ctz.patch b/1069-RISC-V-Add-vector-popcount-clz-ctz.patch new file mode 100644 index 0000000..c12f6ba --- /dev/null +++ b/1069-RISC-V-Add-vector-popcount-clz-ctz.patch @@ -0,0 +1,649 @@ +From a09e9608f27220077e80ac1d6a2f045408f31c2d Mon Sep 17 00:00:00 2001 +From: Robin Dapp +Date: Wed, 15 May 2024 17:41:07 +0200 +Subject: [PATCH 1069/1087] RISC-V: Add vector popcount, clz, ctz. + +commit 6fa4b0135439d64c0ea1816594d7dc830e836376 upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +This patch adds the zvbb vcpop, vclz and vctz to the autovec machinery +as well as tests for them. + +gcc/ChangeLog: + + * config/riscv/autovec.md (ctz2): New expander. + (clz2): Ditto. + * config/riscv/generic-vector-ooo.md: Add bitmanip ops to insn + reservation. + * config/riscv/vector-crypto.md: Add VLS modes to insns. + * config/riscv/vector.md: Add bitmanip ops to mode_idx and other + attributes. + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/rvv/autovec/unop/popcount-1.c: Adjust check + for zvbb. + * gcc.target/riscv/rvv/autovec/unop/popcount-run-1.c: Ditto. + * gcc.target/riscv/rvv/autovec/unop/popcount-2.c: Ditto. + * gcc.target/riscv/rvv/autovec/unop/popcount-3.c: New test. + * gcc.target/riscv/rvv/autovec/unop/popcount-template.h: New test. + * gcc.target/riscv/rvv/autovec/unop/clz-1.c: New test. + * gcc.target/riscv/rvv/autovec/unop/clz-run.c: New test. + * gcc.target/riscv/rvv/autovec/unop/clz-template.h: New test. + * gcc.target/riscv/rvv/autovec/unop/ctz-1.c: New test. + * gcc.target/riscv/rvv/autovec/unop/ctz-run.c: New test. + * gcc.target/riscv/rvv/autovec/unop/ctz-template.h: New test. +--- + gcc/config/riscv/autovec.md | 30 +++- + gcc/config/riscv/generic-vector-ooo.md | 2 +- + gcc/config/riscv/vector-crypto.md | 135 +++++++++--------- + gcc/config/riscv/vector.md | 12 +- + .../gcc.target/riscv/rvv/autovec/unop/clz-1.c | 8 ++ + .../riscv/rvv/autovec/unop/clz-run.c | 36 +++++ + .../riscv/rvv/autovec/unop/clz-template.h | 21 +++ + .../gcc.target/riscv/rvv/autovec/unop/ctz-1.c | 8 ++ + .../riscv/rvv/autovec/unop/ctz-run.c | 36 +++++ + .../riscv/rvv/autovec/unop/ctz-template.h | 21 +++ + .../riscv/rvv/autovec/unop/popcount-1.c | 4 +- + .../riscv/rvv/autovec/unop/popcount-2.c | 4 +- + .../riscv/rvv/autovec/unop/popcount-3.c | 8 ++ + .../riscv/rvv/autovec/unop/popcount-run-1.c | 3 +- + .../rvv/autovec/unop/popcount-template.h | 21 +++ + 15 files changed, 270 insertions(+), 79 deletions(-) + create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/clz-1.c + create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/clz-run.c + create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/clz-template.h + create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/ctz-1.c + create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/ctz-run.c + create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/ctz-template.h + create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-3.c + create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-template.h + +diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md +index 12107e2d152..e4e595c0a87 100644 +--- a/gcc/config/riscv/autovec.md ++++ b/gcc/config/riscv/autovec.md +@@ -1610,7 +1610,7 @@ + }) + + ;; ------------------------------------------------------------------------------- +-;; - [INT] POPCOUNT. ++;; - [INT] POPCOUNT, CTZ and CLZ. + ;; ------------------------------------------------------------------------------- + + (define_expand "popcount2" +@@ -1618,10 +1618,36 @@ + (match_operand:V_VLSI 1 "register_operand")] + "TARGET_VECTOR" + { +- riscv_vector::expand_popcount (operands); ++ if (!TARGET_ZVBB) ++ riscv_vector::expand_popcount (operands); ++ else ++ { ++ riscv_vector::emit_vlmax_insn (code_for_pred_v (POPCOUNT, mode), ++ riscv_vector::CPOP_OP, operands); ++ } + DONE; + }) + ++(define_expand "ctz2" ++ [(match_operand:V_VLSI 0 "register_operand") ++ (match_operand:V_VLSI 1 "register_operand")] ++ "TARGET_ZVBB" ++ { ++ riscv_vector::emit_vlmax_insn (code_for_pred_v (CTZ, mode), ++ riscv_vector::CPOP_OP, operands); ++ DONE; ++}) ++ ++(define_expand "clz2" ++ [(match_operand:V_VLSI 0 "register_operand") ++ (match_operand:V_VLSI 1 "register_operand")] ++ "TARGET_ZVBB" ++ { ++ riscv_vector::emit_vlmax_insn (code_for_pred_v (CLZ, mode), ++ riscv_vector::CPOP_OP, operands); ++ DONE; ++}) ++ + + ;; ------------------------------------------------------------------------- + ;; ---- [INT] Highpart multiplication +diff --git a/gcc/config/riscv/generic-vector-ooo.md b/gcc/config/riscv/generic-vector-ooo.md +index 6c1ef9d7470..efe6bc41e86 100644 +--- a/gcc/config/riscv/generic-vector-ooo.md ++++ b/gcc/config/riscv/generic-vector-ooo.md +@@ -74,7 +74,7 @@ + + ;; Vector crypto, assumed to be a generic operation for now. + (define_insn_reservation "vec_crypto" 4 +- (eq_attr "type" "crypto") ++ (eq_attr "type" "crypto,vclz,vctz,vcpop") + "vxu_ooo_issue,vxu_ooo_alu") + + ;; Vector crypto, AES +diff --git a/gcc/config/riscv/vector-crypto.md b/gcc/config/riscv/vector-crypto.md +index f86adafc84e..b01d3af0179 100755 +--- a/gcc/config/riscv/vector-crypto.md ++++ b/gcc/config/riscv/vector-crypto.md +@@ -99,42 +99,43 @@ + ;; vror.vv vror.vx vror.vi + ;; vwsll.vv vwsll.vx vwsll.vi + (define_insn "@pred_vandn" +- [(set (match_operand:VI 0 "register_operand" "=vd, vr, vd, vr") +- (if_then_else:VI ++ [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vr, vd, vr") ++ (if_then_else:V_VLSI + (unspec: +- [(match_operand: 1 "vector_mask_operand" "vm,Wc1, vm,Wc1") +- (match_operand 5 "vector_length_operand" "rK, rK, rK, rK") +- (match_operand 6 "const_int_operand" " i, i, i, i") +- (match_operand 7 "const_int_operand" " i, i, i, i") +- (match_operand 8 "const_int_operand" " i, i, i, i") ++ [(match_operand: 1 "vector_mask_operand" "vm,Wc1, vm,Wc1") ++ (match_operand 5 "vector_length_operand" "rK, rK, rK, rK") ++ (match_operand 6 "const_int_operand" " i, i, i, i") ++ (match_operand 7 "const_int_operand" " i, i, i, i") ++ (match_operand 8 "const_int_operand" " i, i, i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) +- (and:VI +- (not:VI (match_operand:VI 4 "register_operand" "vr, vr, vr, vr")) +- (match_operand:VI 3 "register_operand" "vr, vr, vr, vr")) +- (match_operand:VI 2 "vector_merge_operand" "vu, vu, 0, 0")))] ++ (and:V_VLSI ++ (not:V_VLSI ++ (match_operand:V_VLSI 4 "register_operand" "vr, vr, vr, vr")) ++ (match_operand:V_VLSI 3 "register_operand" "vr, vr, vr, vr")) ++ (match_operand:V_VLSI 2 "vector_merge_operand" "vu, vu, 0, 0")))] + "TARGET_ZVBB || TARGET_ZVKB" + "vandn.vv\t%0,%3,%4%p1" + [(set_attr "type" "vandn") + (set_attr "mode" "")]) + + (define_insn "@pred_vandn_scalar" +- [(set (match_operand:VI_QHS 0 "register_operand" "=vd, vr,vd, vr") +- (if_then_else:VI_QHS ++ [(set (match_operand:V_VLSI_QHS 0 "register_operand" "=vd, vr,vd, vr") ++ (if_then_else:V_VLSI_QHS + (unspec: +- [(match_operand: 1 "vector_mask_operand" " vm,Wc1,vm,Wc1") +- (match_operand 5 "vector_length_operand" " rK, rK,rK, rK") +- (match_operand 6 "const_int_operand" " i, i, i, i") +- (match_operand 7 "const_int_operand" " i, i, i, i") +- (match_operand 8 "const_int_operand" " i, i, i, i") ++ [(match_operand: 1 "vector_mask_operand" " vm,Wc1,vm,Wc1") ++ (match_operand 5 "vector_length_operand" " rK, rK,rK, rK") ++ (match_operand 6 "const_int_operand" " i, i, i, i") ++ (match_operand 7 "const_int_operand" " i, i, i, i") ++ (match_operand 8 "const_int_operand" " i, i, i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) +- (and:VI_QHS +- (not:VI_QHS +- (vec_duplicate:VI_QHS +- (match_operand: 4 "register_operand" " r, r, r, r"))) +- (match_operand:VI_QHS 3 "register_operand" "vr, vr,vr, vr")) +- (match_operand:VI_QHS 2 "vector_merge_operand" "vu, vu, 0, 0")))] ++ (and:V_VLSI_QHS ++ (not:V_VLSI_QHS ++ (vec_duplicate:V_VLSI_QHS ++ (match_operand: 4 "register_operand" " r, r, r, r"))) ++ (match_operand:V_VLSI_QHS 3 "register_operand" "vr, vr,vr, vr")) ++ (match_operand:V_VLSI_QHS 2 "vector_merge_operand" "vu, vu, 0, 0")))] + "TARGET_ZVBB || TARGET_ZVKB" + "vandn.vx\t%0,%3,%4%p1" + [(set_attr "type" "vandn") +@@ -143,8 +144,8 @@ + ;; Handle GET_MODE_INNER (mode) = DImode. We need to split them since + ;; we need to deal with SEW = 64 in RV32 system. + (define_expand "@pred_vandn_scalar" +- [(set (match_operand:VI_D 0 "register_operand") +- (if_then_else:VI_D ++ [(set (match_operand:V_VLSI_D 0 "register_operand") ++ (if_then_else:V_VLSI_D + (unspec: + [(match_operand: 1 "vector_mask_operand") + (match_operand 5 "vector_length_operand") +@@ -153,12 +154,12 @@ + (match_operand 8 "const_int_operand") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) +- (and:VI_D +- (not:VI_D +- (vec_duplicate:VI_D ++ (and:V_VLSI_D ++ (not:V_VLSI_D ++ (vec_duplicate:V_VLSI_D + (match_operand: 4 "reg_or_int_operand"))) +- (match_operand:VI_D 3 "register_operand")) +- (match_operand:VI_D 2 "vector_merge_operand")))] ++ (match_operand:V_VLSI_D 3 "register_operand")) ++ (match_operand:V_VLSI_D 2 "vector_merge_operand")))] + "TARGET_ZVBB || TARGET_ZVKB" + { + if (riscv_vector::sew64_scalar_helper ( +@@ -177,30 +178,30 @@ + }) + + (define_insn "*pred_vandn_scalar" +- [(set (match_operand:VI_D 0 "register_operand" "=vd, vr,vd, vr") +- (if_then_else:VI_D ++ [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd, vr,vd, vr") ++ (if_then_else:V_VLSI_D + (unspec: +- [(match_operand: 1 "vector_mask_operand" " vm,Wc1,vm,Wc1") +- (match_operand 5 "vector_length_operand" " rK, rK,rK, rK") +- (match_operand 6 "const_int_operand" " i, i, i, i") +- (match_operand 7 "const_int_operand" " i, i, i, i") +- (match_operand 8 "const_int_operand" " i, i, i, i") ++ [(match_operand: 1 "vector_mask_operand" " vm,Wc1,vm,Wc1") ++ (match_operand 5 "vector_length_operand" " rK, rK,rK, rK") ++ (match_operand 6 "const_int_operand" " i, i, i, i") ++ (match_operand 7 "const_int_operand" " i, i, i, i") ++ (match_operand 8 "const_int_operand" " i, i, i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) +- (and:VI_D +- (not:VI_D +- (vec_duplicate:VI_D +- (match_operand: 4 "reg_or_0_operand" " rJ, rJ,rJ, rJ"))) +- (match_operand:VI_D 3 "register_operand" " vr, vr,vr, vr")) +- (match_operand:VI_D 2 "vector_merge_operand" " vu, vu, 0, 0")))] ++ (and:V_VLSI_D ++ (not:V_VLSI_D ++ (vec_duplicate:V_VLSI_D ++ (match_operand: 4 "reg_or_0_operand" " rJ, rJ,rJ, rJ"))) ++ (match_operand:V_VLSI_D 3 "register_operand" " vr, vr,vr, vr")) ++ (match_operand:V_VLSI_D 2 "vector_merge_operand" " vu, vu, 0, 0")))] + "TARGET_ZVBB || TARGET_ZVKB" + "vandn.vx\t%0,%3,%z4%p1" + [(set_attr "type" "vandn") + (set_attr "mode" "")]) + + (define_insn "*pred_vandn_extended_scalar" +- [(set (match_operand:VI_D 0 "register_operand" "=vd, vr,vd, vr") +- (if_then_else:VI_D ++ [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd, vr,vd, vr") ++ (if_then_else:V_VLSI_D + (unspec: + [(match_operand: 1 "vector_mask_operand" " vm,Wc1,vm,Wc1") + (match_operand 5 "vector_length_operand" " rK, rK,rK, rK") +@@ -209,13 +210,13 @@ + (match_operand 8 "const_int_operand" " i, i, i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) +- (and:VI_D +- (not:VI_D +- (vec_duplicate:VI_D ++ (and:V_VLSI_D ++ (not:V_VLSI_D ++ (vec_duplicate:V_VLSI_D + (sign_extend: + (match_operand: 4 "reg_or_0_operand" " rJ, rJ,rJ, rJ")))) +- (match_operand:VI_D 3 "register_operand" " vr, vr,vr, vr")) +- (match_operand:VI_D 2 "vector_merge_operand" " vu, vu, 0, 0")))] ++ (match_operand:V_VLSI_D 3 "register_operand" " vr, vr,vr, vr")) ++ (match_operand:V_VLSI_D 2 "vector_merge_operand" " vu, vu, 0, 0")))] + "TARGET_ZVBB || TARGET_ZVKB" + "vandn.vx\t%0,%3,%z4%p1" + [(set_attr "type" "vandn") +@@ -325,19 +326,19 @@ + + ;; vbrev.v vbrev8.v vrev8.v + (define_insn "@pred_v" +- [(set (match_operand:VI 0 "register_operand" "=vd,vr,vd,vr") +- (if_then_else:VI ++ [(set (match_operand:V_VLSI 0 "register_operand" "=vd,vr,vd,vr") ++ (if_then_else:V_VLSI + (unspec: +- [(match_operand: 1 "vector_mask_operand" "vm,Wc1,vm,Wc1") +- (match_operand 4 "vector_length_operand" "rK,rK, rK, rK") +- (match_operand 5 "const_int_operand" "i, i, i, i") +- (match_operand 6 "const_int_operand" "i, i, i, i") +- (match_operand 7 "const_int_operand" "i, i, i, i") ++ [(match_operand: 1 "vector_mask_operand" "vm,Wc1,vm,Wc1") ++ (match_operand 4 "vector_length_operand" "rK,rK, rK, rK") ++ (match_operand 5 "const_int_operand" "i, i, i, i") ++ (match_operand 6 "const_int_operand" "i, i, i, i") ++ (match_operand 7 "const_int_operand" "i, i, i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) +- (unspec:VI +- [(match_operand:VI 3 "register_operand" "vr,vr, vr, vr")]UNSPEC_VRBB8) +- (match_operand:VI 2 "vector_merge_operand" "vu,vu, 0, 0")))] ++ (unspec:V_VLSI ++ [(match_operand:V_VLSI 3 "register_operand" "vr,vr, vr, vr")]UNSPEC_VRBB8) ++ (match_operand:V_VLSI 2 "vector_merge_operand" "vu,vu, 0, 0")))] + "TARGET_ZVBB || TARGET_ZVKB" + "v.v\t%0,%3%p1" + [(set_attr "type" "v") +@@ -345,14 +346,14 @@ + + ;; vclz.v vctz.v + (define_insn "@pred_v" +- [(set (match_operand:VI 0 "register_operand" "=vd, vr") +- (clz_ctz_pcnt:VI ++ [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vr") ++ (clz_ctz_pcnt:V_VLSI + (parallel +- [(match_operand:VI 2 "register_operand" "vr, vr") ++ [(match_operand:V_VLSI 2 "register_operand" " vr, vr") + (unspec: +- [(match_operand: 1 "vector_mask_operand" "vm,Wc1") +- (match_operand 3 "vector_length_operand" "rK, rK") +- (match_operand 4 "const_int_operand" " i, i") ++ [(match_operand: 1 "vector_mask_operand" " vm,Wc1") ++ (match_operand 3 "vector_length_operand" " rK, rK") ++ (match_operand 4 "const_int_operand" " i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)])))] + "TARGET_ZVBB" +diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md +index 21aea257d0e..49e68c990d3 100644 +--- a/gcc/config/riscv/vector.md ++++ b/gcc/config/riscv/vector.md +@@ -53,7 +53,7 @@ + vmalu,vmpop,vmffs,vmsfs,vmiota,vmidx,vimovvx,vimovxv,vfmovvf,vfmovfv,\ + vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down,\ + vgather,vcompress,vlsegde,vssegte,vlsegds,vssegts,vlsegdux,vlsegdox,\ +- vssegtux,vssegtox,vlsegdff,vandn,vbrev,vbrev8,vrev8,vclz,vctz,vrol,\ ++ vssegtux,vssegtox,vlsegdff,vandn,vbrev,vbrev8,vrev8,vcpop,vclz,vctz,vrol,\ + vror,vwsll,vclmul,vclmulh,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,\ + vaeskf1,vaeskf2,vaesz,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c,\ + vfncvtbf16,vfwcvtbf16,vfwmaccbf16") +@@ -78,7 +78,7 @@ + vmalu,vmpop,vmffs,vmsfs,vmiota,vmidx,vimovxv,vfmovfv,\ + vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down,\ + vgather,vcompress,vlsegde,vssegte,vlsegds,vssegts,vlsegdux,vlsegdox,\ +- vssegtux,vssegtox,vlsegdff,vandn,vbrev,vbrev8,vrev8,vclz,vctz,vrol,\ ++ vssegtux,vssegtox,vlsegdff,vandn,vbrev,vbrev8,vrev8,vcpop,vclz,vctz,vrol,\ + vror,vwsll,vclmul,vclmulh,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,\ + vaeskf1,vaeskf2,vaesz,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c,\ + vfncvtbf16,vfwcvtbf16,vfwmaccbf16") +@@ -485,7 +485,7 @@ + vimovxv,vfmovvf,vfmovfv,vslideup,vslidedown,\ + vislide1up,vislide1down,vfslide1up,vfslide1down,\ + vgather,vcompress,vlsegdux,vlsegdox,vssegtux,vssegtox,\ +- vandn,vbrev,vbrev8,vrev8,vclz,vctz,vrol,vror,vwsll,\ ++ vandn,vbrev,vbrev8,vrev8,vcpop,vclz,vctz,vrol,vror,vwsll,\ + vclmul,vclmulh,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,\ + vaeskf1,vaeskf2,vaesz,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,\ + vsm3me,vsm3c,vfncvtbf16,vfwcvtbf16,vfwmaccbf16") +@@ -864,8 +864,8 @@ + (eq_attr "type" "vicmp,vimuladd,vfcmp,vfmuladd") + (const_int 6) + +- (eq_attr "type" "vmpop,vmffs,vmidx,vssegte,vclz,vctz,vgmul,vaesef,vaesem,vaesdf,vaesdm,\ +- vaesz,vsm4r") ++ (eq_attr "type" "vmpop,vmffs,vmidx,vssegte,vcpop,vclz,vctz,vgmul,vaesef,vaesem,vaesdf,\ ++ vaesdm,vaesz,vsm4r") + (const_int 3)] + (const_int INVALID_ATTRIBUTE))) + +@@ -972,7 +972,7 @@ + vsm4k,vsm3me,vsm3c") + (const_int 6) + +- (eq_attr "type" "vmpop,vmffs,vssegte,vclz,vctz") ++ (eq_attr "type" "vmpop,vmffs,vssegte,vcpop,vclz,vctz") + (const_int 4)] + (const_int INVALID_ATTRIBUTE))) + +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/clz-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/clz-1.c +new file mode 100644 +index 00000000000..c27d9d399b9 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/clz-1.c +@@ -0,0 +1,8 @@ ++/* { dg-do compile } */ ++/* { dg-add-options "riscv_v" } */ ++/* { dg-add-options "riscv_zvbb" } */ ++/* { dg-additional-options "-std=c99 -fno-vect-cost-model" } */ ++ ++#include "clz-template.h" ++ ++/* { dg-final { scan-assembler-times {\tvclz.v} 8 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/clz-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/clz-run.c +new file mode 100644 +index 00000000000..df6f893b8fb +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/clz-run.c +@@ -0,0 +1,36 @@ ++/* { dg-do run { target { riscv_v } } } */ ++/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */ ++ ++#include "clz-template.h" ++ ++#include ++#include ++ ++#define SZ 128 ++ ++#define RUN(TYPE) \ ++ TYPE dst##TYPE[SZ]; \ ++ TYPE a##TYPE[SZ]; \ ++ for (int i = 0; i < SZ; i++) \ ++ { \ ++ dst##TYPE[i] = 0; \ ++ a##TYPE[i] = i; \ ++ } \ ++ vclz_##TYPE (dst##TYPE, a##TYPE, SZ); \ ++ for (int i = 0; i < SZ; i++) \ ++ assert (dst##TYPE[i] == __builtin_clz (a##TYPE[i])); ++ ++#define RUN_ALL() \ ++ RUN (int8_t) \ ++ RUN (uint8_t) \ ++ RUN (int16_t) \ ++ RUN (uint16_t) \ ++ RUN (int32_t) \ ++ RUN (uint32_t) \ ++ RUN (int64_t) \ ++ RUN (uint64_t) ++ ++int main () ++{ ++ RUN_ALL() ++} +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/clz-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/clz-template.h +new file mode 100644 +index 00000000000..1cde9fbc32c +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/clz-template.h +@@ -0,0 +1,21 @@ ++#include ++ ++#define TEST_TYPE(TYPE) \ ++ __attribute__ ((noipa)) void vclz_##TYPE (TYPE *restrict dst, \ ++ TYPE *restrict a, int n) \ ++ { \ ++ for (int i = 0; i < n; i++) \ ++ dst[i] = __builtin_clz (a[i]); \ ++ } ++ ++#define TEST_ALL() \ ++ TEST_TYPE (int8_t) \ ++ TEST_TYPE (uint8_t) \ ++ TEST_TYPE (int16_t) \ ++ TEST_TYPE (uint16_t) \ ++ TEST_TYPE (int32_t) \ ++ TEST_TYPE (uint32_t) \ ++ TEST_TYPE (int64_t) \ ++ TEST_TYPE (uint64_t) ++ ++TEST_ALL() +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/ctz-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/ctz-1.c +new file mode 100644 +index 00000000000..d5989bd5aad +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/ctz-1.c +@@ -0,0 +1,8 @@ ++/* { dg-do compile } */ ++/* { dg-add-options "riscv_v" } */ ++/* { dg-add-options "riscv_zvbb" } */ ++/* { dg-additional-options "-std=c99 -fno-vect-cost-model" } */ ++ ++#include "ctz-template.h" ++ ++/* { dg-final { scan-assembler-times {\tvctz.v} 8 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/ctz-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/ctz-run.c +new file mode 100644 +index 00000000000..9a74ba20a73 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/ctz-run.c +@@ -0,0 +1,36 @@ ++/* { dg-do run { target { riscv_v } } } */ ++/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */ ++ ++#include "ctz-template.h" ++ ++#include ++#include ++ ++#define SZ 126 ++ ++#define RUN(TYPE) \ ++ TYPE dst##TYPE[SZ]; \ ++ TYPE a##TYPE[SZ]; \ ++ for (int i = 0; i < SZ; i++) \ ++ { \ ++ dst##TYPE[i] = 0; \ ++ a##TYPE[i] = i + 1; \ ++ } \ ++ vctz_##TYPE (dst##TYPE, a##TYPE, SZ); \ ++ for (int i = 0; i < SZ; i++) \ ++ assert (dst##TYPE[i] == __builtin_ctz (a##TYPE[i]));\ ++ ++#define RUN_ALL() \ ++ RUN (uint8_t) \ ++ RUN (int8_t) \ ++ RUN (int16_t) \ ++ RUN (uint16_t) \ ++ RUN (int32_t) \ ++ RUN (uint32_t) \ ++ //RUN (int64_t) \ ++ //RUN (uint64_t) ++ ++int main () ++{ ++ RUN_ALL() ++} +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/ctz-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/ctz-template.h +new file mode 100644 +index 00000000000..c47fc19935d +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/ctz-template.h +@@ -0,0 +1,21 @@ ++#include ++ ++#define TEST_TYPE(TYPE) \ ++ __attribute__ ((noipa)) void vctz_##TYPE (TYPE *restrict dst, \ ++ TYPE *restrict a, int n) \ ++ { \ ++ for (int i = 0; i < n; i++) \ ++ dst[i] = __builtin_ctz (a[i]); \ ++ } ++ ++#define TEST_ALL() \ ++ TEST_TYPE (int8_t) \ ++ TEST_TYPE (uint8_t) \ ++ TEST_TYPE (int16_t) \ ++ TEST_TYPE (uint16_t) \ ++ TEST_TYPE (int32_t) \ ++ TEST_TYPE (uint32_t) \ ++ TEST_TYPE (int64_t) \ ++ TEST_TYPE (uint64_t) ++ ++TEST_ALL() +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-1.c +index fad528a842e..1396e46ec8c 100644 +--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-1.c ++++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-1.c +@@ -1,5 +1,6 @@ + /* { dg-do compile } */ +-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-vect-details" } */ ++/* { dg-add-options "riscv_v" } */ ++/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-vect-details" } */ + + #include + +@@ -18,3 +19,4 @@ popcount_64 (uint64_t *restrict dst, uint64_t *restrict src, int size) + } + + /* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 2 "vect" } } */ ++/* { dg-final { scan-assembler-times "vcpop.v" 2 { target { riscv_zvbb } } } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-2.c +index 0199f8cb515..116cc304da3 100644 +--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-2.c ++++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-2.c +@@ -1,5 +1,6 @@ + /* { dg-do compile } */ +-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-slp-details" } */ ++/* { dg-add-options "riscv_v" } */ ++/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-slp-details" } */ + + int x[8]; + int y[8]; +@@ -17,3 +18,4 @@ void foo () + } + + /* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "slp2" } } */ ++/* { dg-final { scan-assembler "vcpop.v" { target { riscv_zvbb } } } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-3.c +new file mode 100644 +index 00000000000..00b87a07fd8 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-3.c +@@ -0,0 +1,8 @@ ++/* { dg-do compile } */ ++/* { dg-add-options "riscv_v" } */ ++/* { dg-add-options "riscv_zvbb" } */ ++/* { dg-additional-options "-std=c99 -fno-vect-cost-model" } */ ++ ++#include "popcount-template.h" ++ ++/* { dg-final { scan-assembler-times {\tvcpop.v} 8 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-run-1.c +index 38f1633da99..8ddb1783dd0 100644 +--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-run-1.c ++++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-run-1.c +@@ -1,4 +1,5 @@ +-/* { dg-do run { target { riscv_v } } } */ ++/* { dg-do run { target { riscv_v_ok } } } */ ++/* { dg-add-options "riscv_v" } */ + + #include "popcount-1.c" + +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-template.h +new file mode 100644 +index 00000000000..28399565bb3 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-template.h +@@ -0,0 +1,21 @@ ++#include ++ ++#define TEST_TYPE(TYPE) \ ++ __attribute__ ((noipa)) void vpopcount_##TYPE (TYPE *restrict dst, \ ++ TYPE *restrict a, int n) \ ++ { \ ++ for (int i = 0; i < n; i++) \ ++ dst[i] = __builtin_popcount (a[i]); \ ++ } ++ ++#define TEST_ALL() \ ++ TEST_TYPE (int8_t) \ ++ TEST_TYPE (uint8_t) \ ++ TEST_TYPE (int16_t) \ ++ TEST_TYPE (uint16_t) \ ++ TEST_TYPE (int32_t) \ ++ TEST_TYPE (uint32_t) \ ++ TEST_TYPE (int64_t) \ ++ TEST_TYPE (uint64_t) ++ ++TEST_ALL() +-- +2.47.3 + diff --git a/1070-RISC-V-Fix-the-result-error-caused-by-not-updating-r.patch b/1070-RISC-V-Fix-the-result-error-caused-by-not-updating-r.patch new file mode 100644 index 0000000..ec0cabe --- /dev/null +++ b/1070-RISC-V-Fix-the-result-error-caused-by-not-updating-r.patch @@ -0,0 +1,66 @@ +From e436e8c2e681cb10f682877cfc1752e391b22544 Mon Sep 17 00:00:00 2001 +From: Jin Ma +Date: Mon, 13 Jan 2025 11:15:55 -0700 +Subject: [PATCH 1070/1087] RISC-V: Fix the result error caused by not updating + ratio when using "use_max_sew" to merge vsetvl + +commit 8d577a01cdbe02a23724b710b579b7811c983c33 upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +When the vsetvl instructions of the two RVV instructions are merged +using "use_max_sew", it is possible to update the sew of prev if +prev.sew < next.sew, but keep the original ratio, which is obviously +wrong. when the subsequent instructions are equal to the wrong ratio, +it is possible to generate the wrong "vsetvli zero,zero" instruction, +which will lead to unknown avl. + +gcc/ChangeLog: + + * config/riscv/riscv-vsetvl.cc (demand_system::use_max_sew): Also + set the ratio for PREV. + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/rvv/base/bug-10.c: New test. +--- + gcc/config/riscv/riscv-vsetvl.cc | 1 + + gcc/testsuite/gcc.target/riscv/rvv/base/bug-10.c | 14 ++++++++++++++ + 2 files changed, 15 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/bug-10.c + +diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc +index 97578f8c4c2..8d332309212 100644 +--- a/gcc/config/riscv/riscv-vsetvl.cc ++++ b/gcc/config/riscv/riscv-vsetvl.cc +@@ -1730,6 +1730,7 @@ private: + { + int max_sew = MAX (prev.get_sew (), next.get_sew ()); + prev.set_sew (max_sew); ++ prev.set_ratio (calculate_ratio (prev.get_sew (), prev.get_vlmul ())); + use_min_of_max_sew (prev, next); + } + inline void use_next_sew_lmul (vsetvl_info &prev, const vsetvl_info &next) +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-10.c b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-10.c +new file mode 100644 +index 00000000000..af3a8610d63 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-10.c +@@ -0,0 +1,14 @@ ++/* { dg-do compile { target { rv64 } } } */ ++/* { dg-options " -march=rv64gcv_zvfh -mabi=lp64d -O2 --param=vsetvl-strategy=optim -fno-schedule-insns -fno-schedule-insns2 -fno-schedule-fusion " } */ ++ ++#include ++ ++void ++foo (uint8_t *ptr, vfloat16m4_t *v1, vuint32m8_t *v2, vuint8m2_t *v3, size_t vl) ++{ ++ *v1 = __riscv_vfmv_s_f_f16m4 (1, vl); ++ *v2 = __riscv_vmv_s_x_u32m8 (2963090659u, vl); ++ *v3 = __riscv_vsll_vx_u8m2 (__riscv_vid_v_u8m2 (vl), 2, vl); ++} ++ ++/* { dg-final { scan-assembler-not {vsetvli.*zero,zero} } }*/ +-- +2.47.3 + diff --git a/1071-RISC-V-Implement-TARGET_CAN_INLINE_P.patch b/1071-RISC-V-Implement-TARGET_CAN_INLINE_P.patch new file mode 100644 index 0000000..cd0710a --- /dev/null +++ b/1071-RISC-V-Implement-TARGET_CAN_INLINE_P.patch @@ -0,0 +1,548 @@ +From 2e9dc26e4126eaf05d76c5b42d00ba8b98ff1319 Mon Sep 17 00:00:00 2001 +From: Yangyu Chen +Date: Tue, 8 Oct 2024 11:08:44 -0600 +Subject: [PATCH 1071/1087] RISC-V: Implement TARGET_CAN_INLINE_P + +commit 517d344e416c762a942a3633b6ec73a1d018016e upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +Currently, we lack support for TARGET_CAN_INLINE_P on the RISC-V +ISA. As a result, certain functions cannot be optimized with inlining +when specific options, such as __attribute__((target("arch=+v"))) . +This can lead to potential performance issues when building +retargetable binaries for RISC-V. + +To address this, I have implemented the riscv_can_inline_p function. +This addition enables inlining when the callee either has no special +options or when the some options match, and also ensuring that the +callee's ISA is a subset of the caller's. I also check some other +options when there is no always_inline set. + +gcc/ChangeLog: + + * common/config/riscv/riscv-common.cc (cl_opt_var_ref_t): Add + cl_opt_var_ref_t pointer to member of cl_target_option. + (struct riscv_ext_flag_table_t): Add new cl_opt_var_ref_t field. + (RISCV_EXT_FLAG_ENTRY): New macro to simplify the definition of + riscv_ext_flag_table. + (riscv_ext_is_subset): New function to check if the callee's ISA + is a subset of the caller's. + (riscv_x_target_flags_isa_mask): New function to get the mask of + ISA extension in x_target_flags of gcc_options. + * config/riscv/riscv-subset.h (riscv_ext_is_subset): Declare + riscv_ext_is_subset function. + (riscv_x_target_flags_isa_mask): Declare + riscv_x_target_flags_isa_mask function. + * config/riscv/riscv.cc (riscv_can_inline_p): New function. + (TARGET_CAN_INLINE_P): Implement TARGET_CAN_INLINE_P. +--- + gcc/common/config/riscv/riscv-common.cc | 366 +++++++++++++----------- + gcc/config/riscv/riscv-subset.h | 3 + + gcc/config/riscv/riscv.cc | 66 +++++ + 3 files changed, 273 insertions(+), 162 deletions(-) + +diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc +index edfe65aa488..171808fe367 100644 +--- a/gcc/common/config/riscv/riscv-common.cc ++++ b/gcc/common/config/riscv/riscv-common.cc +@@ -1566,188 +1566,193 @@ riscv_arch_str (bool version_p) + return std::string(); + } + +-/* Type for pointer to member of gcc_options. */ ++/* Type for pointer to member of gcc_options and cl_target_option. */ + typedef int (gcc_options::*opt_var_ref_t); ++typedef int (cl_target_option::*cl_opt_var_ref_t); + + /* Types for recording extension to internal flag. */ + struct riscv_ext_flag_table_t { + const char *ext; + opt_var_ref_t var_ref; ++ cl_opt_var_ref_t cl_var_ref; + int mask; + }; + ++#define RISCV_EXT_FLAG_ENTRY(NAME, VAR, MASK) \ ++ {NAME, &gcc_options::VAR, &cl_target_option::VAR, MASK} ++ + /* Mapping table between extension to internal flag. */ + static const riscv_ext_flag_table_t riscv_ext_flag_table[] = + { +- {"e", &gcc_options::x_target_flags, MASK_RVE}, +- {"m", &gcc_options::x_target_flags, MASK_MUL}, +- {"a", &gcc_options::x_target_flags, MASK_ATOMIC}, +- {"f", &gcc_options::x_target_flags, MASK_HARD_FLOAT}, +- {"d", &gcc_options::x_target_flags, MASK_DOUBLE_FLOAT}, +- {"c", &gcc_options::x_target_flags, MASK_RVC}, +- {"v", &gcc_options::x_target_flags, MASK_FULL_V}, +- {"v", &gcc_options::x_target_flags, MASK_VECTOR}, +- +- {"zicsr", &gcc_options::x_riscv_zi_subext, MASK_ZICSR}, +- {"zifencei", &gcc_options::x_riscv_zi_subext, MASK_ZIFENCEI}, +- {"zicond", &gcc_options::x_riscv_zi_subext, MASK_ZICOND}, +- +- {"za64rs", &gcc_options::x_riscv_za_subext, MASK_ZA64RS}, +- {"za128rs", &gcc_options::x_riscv_za_subext, MASK_ZA128RS}, +- {"zawrs", &gcc_options::x_riscv_za_subext, MASK_ZAWRS}, +- {"zaamo", &gcc_options::x_riscv_za_subext, MASK_ZAAMO}, +- {"zalrsc", &gcc_options::x_riscv_za_subext, MASK_ZALRSC}, +- {"zabha", &gcc_options::x_riscv_za_subext, MASK_ZABHA}, +- {"zacas", &gcc_options::x_riscv_za_subext, MASK_ZACAS}, +- +- {"zba", &gcc_options::x_riscv_zb_subext, MASK_ZBA}, +- {"zbb", &gcc_options::x_riscv_zb_subext, MASK_ZBB}, +- {"zbc", &gcc_options::x_riscv_zb_subext, MASK_ZBC}, +- {"zbs", &gcc_options::x_riscv_zb_subext, MASK_ZBS}, +- +- {"zfinx", &gcc_options::x_riscv_zinx_subext, MASK_ZFINX}, +- {"zdinx", &gcc_options::x_riscv_zinx_subext, MASK_ZDINX}, +- {"zhinx", &gcc_options::x_riscv_zinx_subext, MASK_ZHINX}, +- {"zhinxmin", &gcc_options::x_riscv_zinx_subext, MASK_ZHINXMIN}, +- +- {"zbkb", &gcc_options::x_riscv_zk_subext, MASK_ZBKB}, +- {"zbkc", &gcc_options::x_riscv_zk_subext, MASK_ZBKC}, +- {"zbkx", &gcc_options::x_riscv_zk_subext, MASK_ZBKX}, +- {"zknd", &gcc_options::x_riscv_zk_subext, MASK_ZKND}, +- {"zkne", &gcc_options::x_riscv_zk_subext, MASK_ZKNE}, +- {"zknh", &gcc_options::x_riscv_zk_subext, MASK_ZKNH}, +- {"zkr", &gcc_options::x_riscv_zk_subext, MASK_ZKR}, +- {"zksed", &gcc_options::x_riscv_zk_subext, MASK_ZKSED}, +- {"zksh", &gcc_options::x_riscv_zk_subext, MASK_ZKSH}, +- {"zkt", &gcc_options::x_riscv_zk_subext, MASK_ZKT}, +- +- {"zihintntl", &gcc_options::x_riscv_zi_subext, MASK_ZIHINTNTL}, +- {"zihintpause", &gcc_options::x_riscv_zi_subext, MASK_ZIHINTPAUSE}, +- {"ziccamoa", &gcc_options::x_riscv_zi_subext, MASK_ZICCAMOA}, +- {"ziccif", &gcc_options::x_riscv_zi_subext, MASK_ZICCIF}, +- {"zicclsm", &gcc_options::x_riscv_zi_subext, MASK_ZICCLSM}, +- {"ziccrse", &gcc_options::x_riscv_zi_subext, MASK_ZICCRSE}, +- +- {"zicboz", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOZ}, +- {"zicbom", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOM}, +- {"zicbop", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOP}, +- {"zic64b", &gcc_options::x_riscv_zicmo_subext, MASK_ZIC64B}, +- +- {"zimop", &gcc_options::x_riscv_mop_subext, MASK_ZIMOP}, +- {"zcmop", &gcc_options::x_riscv_mop_subext, MASK_ZCMOP}, +- +- {"zve32x", &gcc_options::x_target_flags, MASK_VECTOR}, +- {"zve32f", &gcc_options::x_target_flags, MASK_VECTOR}, +- {"zve64x", &gcc_options::x_target_flags, MASK_VECTOR}, +- {"zve64f", &gcc_options::x_target_flags, MASK_VECTOR}, +- {"zve64d", &gcc_options::x_target_flags, MASK_VECTOR}, ++ RISCV_EXT_FLAG_ENTRY ("e", x_target_flags, MASK_RVE), ++ RISCV_EXT_FLAG_ENTRY ("m", x_target_flags, MASK_MUL), ++ RISCV_EXT_FLAG_ENTRY ("a", x_target_flags, MASK_ATOMIC), ++ RISCV_EXT_FLAG_ENTRY ("f", x_target_flags, MASK_HARD_FLOAT), ++ RISCV_EXT_FLAG_ENTRY ("d", x_target_flags, MASK_DOUBLE_FLOAT), ++ RISCV_EXT_FLAG_ENTRY ("c", x_target_flags, MASK_RVC), ++ RISCV_EXT_FLAG_ENTRY ("v", x_target_flags, MASK_FULL_V), ++ RISCV_EXT_FLAG_ENTRY ("v", x_target_flags, MASK_VECTOR), ++ ++ RISCV_EXT_FLAG_ENTRY ("zicsr", x_riscv_zi_subext, MASK_ZICSR), ++ RISCV_EXT_FLAG_ENTRY ("zifencei", x_riscv_zi_subext, MASK_ZIFENCEI), ++ RISCV_EXT_FLAG_ENTRY ("zicond", x_riscv_zi_subext, MASK_ZICOND), ++ ++ RISCV_EXT_FLAG_ENTRY ("za64rs", x_riscv_za_subext, MASK_ZA64RS), ++ RISCV_EXT_FLAG_ENTRY ("za128rs", x_riscv_za_subext, MASK_ZA128RS), ++ RISCV_EXT_FLAG_ENTRY ("zawrs", x_riscv_za_subext, MASK_ZAWRS), ++ RISCV_EXT_FLAG_ENTRY ("zaamo", x_riscv_za_subext, MASK_ZAAMO), ++ RISCV_EXT_FLAG_ENTRY ("zalrsc", x_riscv_za_subext, MASK_ZALRSC), ++ RISCV_EXT_FLAG_ENTRY ("zabha", x_riscv_za_subext, MASK_ZABHA), ++ RISCV_EXT_FLAG_ENTRY ("zacas", x_riscv_za_subext, MASK_ZACAS), ++ ++ RISCV_EXT_FLAG_ENTRY ("zba", x_riscv_zb_subext, MASK_ZBA), ++ RISCV_EXT_FLAG_ENTRY ("zbb", x_riscv_zb_subext, MASK_ZBB), ++ RISCV_EXT_FLAG_ENTRY ("zbc", x_riscv_zb_subext, MASK_ZBC), ++ RISCV_EXT_FLAG_ENTRY ("zbs", x_riscv_zb_subext, MASK_ZBS), ++ ++ RISCV_EXT_FLAG_ENTRY ("zfinx", x_riscv_zinx_subext, MASK_ZFINX), ++ RISCV_EXT_FLAG_ENTRY ("zdinx", x_riscv_zinx_subext, MASK_ZDINX), ++ RISCV_EXT_FLAG_ENTRY ("zhinx", x_riscv_zinx_subext, MASK_ZHINX), ++ RISCV_EXT_FLAG_ENTRY ("zhinxmin", x_riscv_zinx_subext, MASK_ZHINXMIN), ++ ++ RISCV_EXT_FLAG_ENTRY ("zbkb", x_riscv_zk_subext, MASK_ZBKB), ++ RISCV_EXT_FLAG_ENTRY ("zbkc", x_riscv_zk_subext, MASK_ZBKC), ++ RISCV_EXT_FLAG_ENTRY ("zbkx", x_riscv_zk_subext, MASK_ZBKX), ++ RISCV_EXT_FLAG_ENTRY ("zknd", x_riscv_zk_subext, MASK_ZKND), ++ RISCV_EXT_FLAG_ENTRY ("zkne", x_riscv_zk_subext, MASK_ZKNE), ++ RISCV_EXT_FLAG_ENTRY ("zknh", x_riscv_zk_subext, MASK_ZKNH), ++ RISCV_EXT_FLAG_ENTRY ("zkr", x_riscv_zk_subext, MASK_ZKR), ++ RISCV_EXT_FLAG_ENTRY ("zksed", x_riscv_zk_subext, MASK_ZKSED), ++ RISCV_EXT_FLAG_ENTRY ("zksh", x_riscv_zk_subext, MASK_ZKSH), ++ RISCV_EXT_FLAG_ENTRY ("zkt", x_riscv_zk_subext, MASK_ZKT), ++ ++ RISCV_EXT_FLAG_ENTRY ("zihintntl", x_riscv_zi_subext, MASK_ZIHINTNTL), ++ RISCV_EXT_FLAG_ENTRY ("zihintpause", x_riscv_zi_subext, MASK_ZIHINTPAUSE), ++ RISCV_EXT_FLAG_ENTRY ("ziccamoa", x_riscv_zi_subext, MASK_ZICCAMOA), ++ RISCV_EXT_FLAG_ENTRY ("ziccif", x_riscv_zi_subext, MASK_ZICCIF), ++ RISCV_EXT_FLAG_ENTRY ("zicclsm", x_riscv_zi_subext, MASK_ZICCLSM), ++ RISCV_EXT_FLAG_ENTRY ("ziccrse", x_riscv_zi_subext, MASK_ZICCRSE), ++ ++ RISCV_EXT_FLAG_ENTRY ("zicboz", x_riscv_zicmo_subext, MASK_ZICBOZ), ++ RISCV_EXT_FLAG_ENTRY ("zicbom", x_riscv_zicmo_subext, MASK_ZICBOM), ++ RISCV_EXT_FLAG_ENTRY ("zicbop", x_riscv_zicmo_subext, MASK_ZICBOP), ++ RISCV_EXT_FLAG_ENTRY ("zic64b", x_riscv_zicmo_subext, MASK_ZIC64B), ++ ++ RISCV_EXT_FLAG_ENTRY ("zimop", x_riscv_mop_subext, MASK_ZIMOP), ++ RISCV_EXT_FLAG_ENTRY ("zcmop", x_riscv_mop_subext, MASK_ZCMOP), ++ ++ RISCV_EXT_FLAG_ENTRY ("zve32x", x_target_flags, MASK_VECTOR), ++ RISCV_EXT_FLAG_ENTRY ("zve32f", x_target_flags, MASK_VECTOR), ++ RISCV_EXT_FLAG_ENTRY ("zve64x", x_target_flags, MASK_VECTOR), ++ RISCV_EXT_FLAG_ENTRY ("zve64f", x_target_flags, MASK_VECTOR), ++ RISCV_EXT_FLAG_ENTRY ("zve64d", x_target_flags, MASK_VECTOR), + + /* We don't need to put complete ELEN/ELEN_FP info here, due to the + implication relation of vector extension. + e.g. v -> zve64d ... zve32x, so v has set MASK_VECTOR_ELEN_FP_64, + MASK_VECTOR_ELEN_FP_32, MASK_VECTOR_ELEN_64 and MASK_VECTOR_ELEN_32 + due to the extension implication. */ +- {"zve32x", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_32}, +- {"zve32f", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_32}, +- {"zve64x", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_64}, +- {"zve64f", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_32}, +- {"zve64d", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_64}, +- {"zvfbfmin", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_BF_16}, +- {"zvfbfwma", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_BF_16}, +- {"zvfhmin", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_16}, +- {"zvfh", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_16}, +- +- {"zvbb", &gcc_options::x_riscv_zvb_subext, MASK_ZVBB}, +- {"zvbc", &gcc_options::x_riscv_zvb_subext, MASK_ZVBC}, +- {"zvkb", &gcc_options::x_riscv_zvb_subext, MASK_ZVKB}, +- {"zvkg", &gcc_options::x_riscv_zvk_subext, MASK_ZVKG}, +- {"zvkned", &gcc_options::x_riscv_zvk_subext, MASK_ZVKNED}, +- {"zvknha", &gcc_options::x_riscv_zvk_subext, MASK_ZVKNHA}, +- {"zvknhb", &gcc_options::x_riscv_zvk_subext, MASK_ZVKNHB}, +- {"zvksed", &gcc_options::x_riscv_zvk_subext, MASK_ZVKSED}, +- {"zvksh", &gcc_options::x_riscv_zvk_subext, MASK_ZVKSH}, +- {"zvkn", &gcc_options::x_riscv_zvk_subext, MASK_ZVKN}, +- {"zvknc", &gcc_options::x_riscv_zvk_subext, MASK_ZVKNC}, +- {"zvkng", &gcc_options::x_riscv_zvk_subext, MASK_ZVKNG}, +- {"zvks", &gcc_options::x_riscv_zvk_subext, MASK_ZVKS}, +- {"zvksc", &gcc_options::x_riscv_zvk_subext, MASK_ZVKSC}, +- {"zvksg", &gcc_options::x_riscv_zvk_subext, MASK_ZVKSG}, +- {"zvkt", &gcc_options::x_riscv_zvk_subext, MASK_ZVKT}, +- +- {"zvl32b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL32B}, +- {"zvl64b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL64B}, +- {"zvl128b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL128B}, +- {"zvl256b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL256B}, +- {"zvl512b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL512B}, +- {"zvl1024b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL1024B}, +- {"zvl2048b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL2048B}, +- {"zvl4096b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL4096B}, +- {"zvl8192b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL8192B}, +- {"zvl16384b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL16384B}, +- {"zvl32768b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL32768B}, +- {"zvl65536b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL65536B}, +- +- {"zfbfmin", &gcc_options::x_riscv_zf_subext, MASK_ZFBFMIN}, +- {"zfhmin", &gcc_options::x_riscv_zf_subext, MASK_ZFHMIN}, +- {"zfh", &gcc_options::x_riscv_zf_subext, MASK_ZFH}, +- {"zvfbfmin", &gcc_options::x_riscv_zf_subext, MASK_ZVFBFMIN}, +- {"zvfbfwma", &gcc_options::x_riscv_zf_subext, MASK_ZVFBFWMA}, +- {"zvfhmin", &gcc_options::x_riscv_zf_subext, MASK_ZVFHMIN}, +- {"zvfh", &gcc_options::x_riscv_zf_subext, MASK_ZVFH}, +- +- {"zfa", &gcc_options::x_riscv_zfa_subext, MASK_ZFA}, +- +- {"zmmul", &gcc_options::x_riscv_zm_subext, MASK_ZMMUL}, ++ RISCV_EXT_FLAG_ENTRY ("zve32x", x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_32), ++ RISCV_EXT_FLAG_ENTRY ("zve32f", x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_32), ++ RISCV_EXT_FLAG_ENTRY ("zve64x", x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_64), ++ RISCV_EXT_FLAG_ENTRY ("zve64f", x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_32), ++ RISCV_EXT_FLAG_ENTRY ("zve64d", x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_64), ++ RISCV_EXT_FLAG_ENTRY ("zvfbfmin", x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_BF_16), ++ RISCV_EXT_FLAG_ENTRY ("zvfbfwma", x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_BF_16), ++ RISCV_EXT_FLAG_ENTRY ("zvfhmin", x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_16), ++ RISCV_EXT_FLAG_ENTRY ("zvfh", x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_16), ++ ++ RISCV_EXT_FLAG_ENTRY ("zvbb", x_riscv_zvb_subext, MASK_ZVBB), ++ RISCV_EXT_FLAG_ENTRY ("zvbc", x_riscv_zvb_subext, MASK_ZVBC), ++ RISCV_EXT_FLAG_ENTRY ("zvkb", x_riscv_zvb_subext, MASK_ZVKB), ++ RISCV_EXT_FLAG_ENTRY ("zvkg", x_riscv_zvk_subext, MASK_ZVKG), ++ RISCV_EXT_FLAG_ENTRY ("zvkned", x_riscv_zvk_subext, MASK_ZVKNED), ++ RISCV_EXT_FLAG_ENTRY ("zvknha", x_riscv_zvk_subext, MASK_ZVKNHA), ++ RISCV_EXT_FLAG_ENTRY ("zvknhb", x_riscv_zvk_subext, MASK_ZVKNHB), ++ RISCV_EXT_FLAG_ENTRY ("zvksed", x_riscv_zvk_subext, MASK_ZVKSED), ++ RISCV_EXT_FLAG_ENTRY ("zvksh", x_riscv_zvk_subext, MASK_ZVKSH), ++ RISCV_EXT_FLAG_ENTRY ("zvkn", x_riscv_zvk_subext, MASK_ZVKN), ++ RISCV_EXT_FLAG_ENTRY ("zvknc", x_riscv_zvk_subext, MASK_ZVKNC), ++ RISCV_EXT_FLAG_ENTRY ("zvkng", x_riscv_zvk_subext, MASK_ZVKNG), ++ RISCV_EXT_FLAG_ENTRY ("zvks", x_riscv_zvk_subext, MASK_ZVKS), ++ RISCV_EXT_FLAG_ENTRY ("zvksc", x_riscv_zvk_subext, MASK_ZVKSC), ++ RISCV_EXT_FLAG_ENTRY ("zvksg", x_riscv_zvk_subext, MASK_ZVKSG), ++ RISCV_EXT_FLAG_ENTRY ("zvkt", x_riscv_zvk_subext, MASK_ZVKT), ++ ++ RISCV_EXT_FLAG_ENTRY ("zvl32b", x_riscv_zvl_flags, MASK_ZVL32B), ++ RISCV_EXT_FLAG_ENTRY ("zvl64b", x_riscv_zvl_flags, MASK_ZVL64B), ++ RISCV_EXT_FLAG_ENTRY ("zvl128b", x_riscv_zvl_flags, MASK_ZVL128B), ++ RISCV_EXT_FLAG_ENTRY ("zvl256b", x_riscv_zvl_flags, MASK_ZVL256B), ++ RISCV_EXT_FLAG_ENTRY ("zvl512b", x_riscv_zvl_flags, MASK_ZVL512B), ++ RISCV_EXT_FLAG_ENTRY ("zvl1024b", x_riscv_zvl_flags, MASK_ZVL1024B), ++ RISCV_EXT_FLAG_ENTRY ("zvl2048b", x_riscv_zvl_flags, MASK_ZVL2048B), ++ RISCV_EXT_FLAG_ENTRY ("zvl4096b", x_riscv_zvl_flags, MASK_ZVL4096B), ++ RISCV_EXT_FLAG_ENTRY ("zvl8192b", x_riscv_zvl_flags, MASK_ZVL8192B), ++ RISCV_EXT_FLAG_ENTRY ("zvl16384b", x_riscv_zvl_flags, MASK_ZVL16384B), ++ RISCV_EXT_FLAG_ENTRY ("zvl32768b", x_riscv_zvl_flags, MASK_ZVL32768B), ++ RISCV_EXT_FLAG_ENTRY ("zvl65536b", x_riscv_zvl_flags, MASK_ZVL65536B), ++ ++ RISCV_EXT_FLAG_ENTRY ("zfbfmin", x_riscv_zf_subext, MASK_ZFBFMIN), ++ RISCV_EXT_FLAG_ENTRY ("zfhmin", x_riscv_zf_subext, MASK_ZFHMIN), ++ RISCV_EXT_FLAG_ENTRY ("zfh", x_riscv_zf_subext, MASK_ZFH), ++ RISCV_EXT_FLAG_ENTRY ("zvfbfmin", x_riscv_zf_subext, MASK_ZVFBFMIN), ++ RISCV_EXT_FLAG_ENTRY ("zvfbfwma", x_riscv_zf_subext, MASK_ZVFBFWMA), ++ RISCV_EXT_FLAG_ENTRY ("zvfhmin", x_riscv_zf_subext, MASK_ZVFHMIN), ++ RISCV_EXT_FLAG_ENTRY ("zvfh", x_riscv_zf_subext, MASK_ZVFH), ++ ++ RISCV_EXT_FLAG_ENTRY ("zfa", x_riscv_zfa_subext, MASK_ZFA), ++ ++ RISCV_EXT_FLAG_ENTRY ("zmmul", x_riscv_zm_subext, MASK_ZMMUL), + + /* Code-size reduction extensions. */ +- {"zca", &gcc_options::x_riscv_zc_subext, MASK_ZCA}, +- {"zcb", &gcc_options::x_riscv_zc_subext, MASK_ZCB}, +- {"zce", &gcc_options::x_riscv_zc_subext, MASK_ZCE}, +- {"zcf", &gcc_options::x_riscv_zc_subext, MASK_ZCF}, +- {"zcd", &gcc_options::x_riscv_zc_subext, MASK_ZCD}, +- {"zcmp", &gcc_options::x_riscv_zc_subext, MASK_ZCMP}, +- {"zcmt", &gcc_options::x_riscv_zc_subext, MASK_ZCMT}, +- +- {"svinval", &gcc_options::x_riscv_sv_subext, MASK_SVINVAL}, +- {"svnapot", &gcc_options::x_riscv_sv_subext, MASK_SVNAPOT}, +- +- {"ztso", &gcc_options::x_riscv_ztso_subext, MASK_ZTSO}, +- +- {"xcvmac", &gcc_options::x_riscv_xcv_subext, MASK_XCVMAC}, +- {"xcvalu", &gcc_options::x_riscv_xcv_subext, MASK_XCVALU}, +- {"xcvelw", &gcc_options::x_riscv_xcv_subext, MASK_XCVELW}, +- {"xcvsimd", &gcc_options::x_riscv_xcv_subext, MASK_XCVSIMD}, +- {"xcvbi", &gcc_options::x_riscv_xcv_subext, MASK_XCVBI}, +- +- {"xtheadba", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBA}, +- {"xtheadbb", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBB}, +- {"xtheadbs", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBS}, +- {"xtheadcmo", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADCMO}, +- {"xtheadcondmov", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADCONDMOV}, +- {"xtheadfmemidx", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADFMEMIDX}, +- {"xtheadfmv", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADFMV}, +- {"xtheadint", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADINT}, +- {"xtheadmac", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADMAC}, +- {"xtheadmemidx", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADMEMIDX}, +- {"xtheadmempair", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADMEMPAIR}, +- {"xtheadsync", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADSYNC}, +- {"xtheadvector", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADVECTOR}, +- {"xtheadvector", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_32}, +- {"xtheadvector", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_64}, +- {"xtheadvector", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_32}, +- {"xtheadvector", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_64}, +- {"xtheadvector", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_16}, +- {"xtheadvector", &gcc_options::x_riscv_zvl_flags, MASK_ZVL32B}, +- {"xtheadvector", &gcc_options::x_riscv_zvl_flags, MASK_ZVL64B}, +- {"xtheadvector", &gcc_options::x_riscv_zvl_flags, MASK_ZVL128B}, +- {"xtheadvector", &gcc_options::x_riscv_zf_subext, MASK_ZVFHMIN}, +- {"xtheadvector", &gcc_options::x_riscv_zf_subext, MASK_ZVFH}, +- {"xtheadvector", &gcc_options::x_target_flags, MASK_FULL_V}, +- {"xtheadvector", &gcc_options::x_target_flags, MASK_VECTOR}, +- +- {"xventanacondops", &gcc_options::x_riscv_xventana_subext, MASK_XVENTANACONDOPS}, +- +- {NULL, NULL, 0} ++ RISCV_EXT_FLAG_ENTRY ("zca", x_riscv_zc_subext, MASK_ZCA), ++ RISCV_EXT_FLAG_ENTRY ("zcb", x_riscv_zc_subext, MASK_ZCB), ++ RISCV_EXT_FLAG_ENTRY ("zce", x_riscv_zc_subext, MASK_ZCE), ++ RISCV_EXT_FLAG_ENTRY ("zcf", x_riscv_zc_subext, MASK_ZCF), ++ RISCV_EXT_FLAG_ENTRY ("zcd", x_riscv_zc_subext, MASK_ZCD), ++ RISCV_EXT_FLAG_ENTRY ("zcmp", x_riscv_zc_subext, MASK_ZCMP), ++ RISCV_EXT_FLAG_ENTRY ("zcmt", x_riscv_zc_subext, MASK_ZCMT), ++ ++ RISCV_EXT_FLAG_ENTRY ("svinval", x_riscv_sv_subext, MASK_SVINVAL), ++ RISCV_EXT_FLAG_ENTRY ("svnapot", x_riscv_sv_subext, MASK_SVNAPOT), ++ ++ RISCV_EXT_FLAG_ENTRY ("ztso", x_riscv_ztso_subext, MASK_ZTSO), ++ ++ RISCV_EXT_FLAG_ENTRY ("xcvmac", x_riscv_xcv_subext, MASK_XCVMAC), ++ RISCV_EXT_FLAG_ENTRY ("xcvalu", x_riscv_xcv_subext, MASK_XCVALU), ++ RISCV_EXT_FLAG_ENTRY ("xcvelw", x_riscv_xcv_subext, MASK_XCVELW), ++ RISCV_EXT_FLAG_ENTRY ("xcvsimd", x_riscv_xcv_subext, MASK_XCVSIMD), ++ RISCV_EXT_FLAG_ENTRY ("xcvbi", x_riscv_xcv_subext, MASK_XCVBI), ++ ++ RISCV_EXT_FLAG_ENTRY ("xtheadba", x_riscv_xthead_subext, MASK_XTHEADBA), ++ RISCV_EXT_FLAG_ENTRY ("xtheadbb", x_riscv_xthead_subext, MASK_XTHEADBB), ++ RISCV_EXT_FLAG_ENTRY ("xtheadbs", x_riscv_xthead_subext, MASK_XTHEADBS), ++ RISCV_EXT_FLAG_ENTRY ("xtheadcmo", x_riscv_xthead_subext, MASK_XTHEADCMO), ++ RISCV_EXT_FLAG_ENTRY ("xtheadcondmov", x_riscv_xthead_subext, MASK_XTHEADCONDMOV), ++ RISCV_EXT_FLAG_ENTRY ("xtheadfmemidx", x_riscv_xthead_subext, MASK_XTHEADFMEMIDX), ++ RISCV_EXT_FLAG_ENTRY ("xtheadfmv", x_riscv_xthead_subext, MASK_XTHEADFMV), ++ RISCV_EXT_FLAG_ENTRY ("xtheadint", x_riscv_xthead_subext, MASK_XTHEADINT), ++ RISCV_EXT_FLAG_ENTRY ("xtheadmac", x_riscv_xthead_subext, MASK_XTHEADMAC), ++ RISCV_EXT_FLAG_ENTRY ("xtheadmemidx", x_riscv_xthead_subext, MASK_XTHEADMEMIDX), ++ RISCV_EXT_FLAG_ENTRY ("xtheadmempair", x_riscv_xthead_subext, MASK_XTHEADMEMPAIR), ++ RISCV_EXT_FLAG_ENTRY ("xtheadsync", x_riscv_xthead_subext, MASK_XTHEADSYNC), ++ RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_xthead_subext, MASK_XTHEADVECTOR), ++ RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_32), ++ RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_64), ++ RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_32), ++ RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_64), ++ RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_16), ++ RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_zvl_flags, MASK_ZVL32B), ++ RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_zvl_flags, MASK_ZVL64B), ++ RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_zvl_flags, MASK_ZVL128B), ++ RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_zf_subext, MASK_ZVFHMIN), ++ RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_zf_subext, MASK_ZVFH), ++ RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_target_flags, MASK_FULL_V), ++ RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_target_flags, MASK_VECTOR), ++ ++ RISCV_EXT_FLAG_ENTRY ("xventanacondops", x_riscv_xventana_subext, MASK_XVENTANACONDOPS), ++ ++ {NULL, NULL, NULL, 0} + }; + + /* Apply SUBSET_LIST to OPTS if OPTS is not null. */ +@@ -1779,6 +1784,43 @@ riscv_set_arch_by_subset_list (riscv_subset_list *subset_list, + } + } + ++/* Check if the ISA extension of the "subset" is a subset of the "opts". */ ++ ++bool ++riscv_ext_is_subset (struct cl_target_option *opts, ++ struct cl_target_option *subset) ++{ ++ const riscv_ext_flag_table_t *arch_ext_flag_tab; ++ for (arch_ext_flag_tab = &riscv_ext_flag_table[0]; ++ arch_ext_flag_tab->ext; ++ ++arch_ext_flag_tab) ++ { ++ if (subset->*arch_ext_flag_tab->cl_var_ref & arch_ext_flag_tab->mask) ++ { ++ if (!(opts->*arch_ext_flag_tab->cl_var_ref & arch_ext_flag_tab->mask)) ++ return false; ++ } ++ } ++ return true; ++} ++ ++/* Return the mask of ISA extension in x_target_flags of gcc_options. */ ++ ++int ++riscv_x_target_flags_isa_mask (void) ++{ ++ int mask = 0; ++ const riscv_ext_flag_table_t *arch_ext_flag_tab; ++ for (arch_ext_flag_tab = &riscv_ext_flag_table[0]; ++ arch_ext_flag_tab->ext; ++ ++arch_ext_flag_tab) ++ { ++ if (arch_ext_flag_tab->var_ref == &gcc_options::x_target_flags) ++ mask |= arch_ext_flag_tab->mask; ++ } ++ return mask; ++} ++ + /* Parse a RISC-V ISA string into an option mask. Must clear or set all arch + dependent mask bits, in case more than one -march string is passed. */ + +diff --git a/gcc/config/riscv/riscv-subset.h b/gcc/config/riscv/riscv-subset.h +index 4d2bf9d9201..0132dcb193a 100644 +--- a/gcc/config/riscv/riscv-subset.h ++++ b/gcc/config/riscv/riscv-subset.h +@@ -120,5 +120,8 @@ public: + extern const riscv_subset_list *riscv_cmdline_subset_list (void); + extern void + riscv_set_arch_by_subset_list (riscv_subset_list *, struct gcc_options *); ++extern bool ++riscv_ext_is_subset (struct cl_target_option *, struct cl_target_option *); ++extern int riscv_x_target_flags_isa_mask (void); + + #endif /* ! GCC_RISCV_SUBSET_H */ +diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc +index 1e9b77b81ca..a5698818b9b 100644 +--- a/gcc/config/riscv/riscv.cc ++++ b/gcc/config/riscv/riscv.cc +@@ -7160,6 +7160,69 @@ riscv_compute_frame_info (void) + /* Next points the incoming stack pointer and any incoming arguments. */ + } + ++/* Implement TARGET_CAN_INLINE_P. Determine whether inlining the function ++ CALLER into the function CALLEE is safe. Inlining should be rejected if ++ there is no always_inline attribute and the target options differ except ++ for differences in ISA extensions or performance tuning options like the ++ code model, TLS dialect, and stack protector, etc. Inlining is ++ permissible when the non-ISA extension options are identical and the ISA ++ extensions of CALLEE are a subset of those of CALLER, thereby improving ++ the performance of Function Multi-Versioning. */ ++ ++static bool ++riscv_can_inline_p (tree caller, tree callee) ++{ ++ tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET (callee); ++ tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET (caller); ++ ++ /* It's safe to inline if callee has no opts. */ ++ if (! callee_tree) ++ return true; ++ ++ if (! caller_tree) ++ caller_tree = target_option_default_node; ++ ++ struct cl_target_option *callee_opts = TREE_TARGET_OPTION (callee_tree); ++ struct cl_target_option *caller_opts = TREE_TARGET_OPTION (caller_tree); ++ ++ int isa_flag_mask = riscv_x_target_flags_isa_mask (); ++ ++ /* Callee and caller should have the same target options except for ISA. */ ++ int callee_target_flags = callee_opts->x_target_flags & ~isa_flag_mask; ++ int caller_target_flags = caller_opts->x_target_flags & ~isa_flag_mask; ++ ++ if (callee_target_flags != caller_target_flags) ++ return false; ++ ++ /* Callee's ISA should be a subset of the caller's ISA. */ ++ if (! riscv_ext_is_subset (caller_opts, callee_opts)) ++ return false; ++ ++ /* If the callee has always_inline set, we can ignore the rest attributes. */ ++ if (lookup_attribute ("always_inline", DECL_ATTRIBUTES (callee))) ++ return true; ++ ++ if (caller_opts->x_riscv_cmodel != callee_opts->x_riscv_cmodel) ++ return false; ++ ++ if (caller_opts->x_riscv_tls_dialect != callee_opts->x_riscv_tls_dialect) ++ return false; ++ ++ if (caller_opts->x_riscv_stack_protector_guard_reg ++ != callee_opts->x_riscv_stack_protector_guard_reg) ++ return false; ++ ++ if (caller_opts->x_riscv_stack_protector_guard_offset ++ != callee_opts->x_riscv_stack_protector_guard_offset) ++ return false; ++ ++ if (caller_opts->x_rvv_vector_strict_align ++ != callee_opts->x_rvv_vector_strict_align) ++ return false; ++ ++ return true; ++} ++ + /* Make sure that we're not trying to eliminate to the wrong hard frame + pointer. */ + +@@ -11413,6 +11476,9 @@ riscv_get_raw_result_mode (int regno) + #undef TARGET_LEGITIMATE_ADDRESS_P + #define TARGET_LEGITIMATE_ADDRESS_P riscv_legitimate_address_p + ++#undef TARGET_CAN_INLINE_P ++#define TARGET_CAN_INLINE_P riscv_can_inline_p ++ + #undef TARGET_CAN_ELIMINATE + #define TARGET_CAN_ELIMINATE riscv_can_eliminate + +-- +2.47.3 + diff --git a/1072-RISC-V-Add-Zicfiss-ISA-extension.patch b/1072-RISC-V-Add-Zicfiss-ISA-extension.patch new file mode 100644 index 0000000..3164182 --- /dev/null +++ b/1072-RISC-V-Add-Zicfiss-ISA-extension.patch @@ -0,0 +1,606 @@ +From ab921694a4f9e707c7db607ddeb02713821ce568 Mon Sep 17 00:00:00 2001 +From: Monk Chiang +Date: Fri, 15 Nov 2024 13:38:48 +0800 +Subject: [PATCH 1072/1087] RISC-V: Add Zicfiss ISA extension. + +commit dc76aa0e4d5398104b6b26f08b46524b97de5100 upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +This patch is implemented according to the RISC-V CFI specification. +It supports the generation of shadow stack instructions in the prologue, +epilogue, non-local gotos, and unwinding. + +RISC-V CFI SPEC: https://github.com/riscv/riscv-cfi + +gcc/ChangeLog: + * common/config/riscv/riscv-common.cc: Add ZICFISS ISA string. + * config/riscv/predicates.md: New predicate x1x5_operand. + * config/riscv/riscv.cc + (riscv_expand_prologue): Insert shadow stack instructions. + (riscv_expand_epilogue): Likewise. + (riscv_for_each_saved_reg): Assign t0 or ra register for + sspopchk instruction. + (need_shadow_stack_push_pop_p): New function. Omit shadow + stack operation on leaf function. + * config/riscv/riscv.h + (need_shadow_stack_push_pop_p): Define. + * config/riscv/riscv.md: Add shadow stack patterns. + (save_stack_nonlocal): Add shadow stack instructions for setjump. + (restore_stack_nonlocal): Add shadow stack instructions for longjump. + * config/riscv/riscv.opt (TARGET_ZICFISS): Define. + +libgcc/ChangeLog: + * config/riscv/linux-unwind.h: Include shadow-stack-unwind.h. + * config/riscv/shadow-stack-unwind.h + (_Unwind_Frames_Extra): Define. + (_Unwind_Frames_Increment): Define. + +gcc/testsuite/ChangeLog: + * gcc.target/riscv/ssp-1.c: New test. + * gcc.target/riscv/ssp-2.c: New test. + + Co-Developed-by: Greg McGary , + Kito Cheng +--- + gcc/common/config/riscv/riscv-common.cc | 7 ++ + gcc/config/riscv/predicates.md | 6 ++ + gcc/config/riscv/riscv.cc | 60 +++++++++-- + gcc/config/riscv/riscv.h | 1 + + gcc/config/riscv/riscv.md | 126 +++++++++++++++++++++- + gcc/config/riscv/riscv.opt | 2 + + gcc/testsuite/gcc.target/riscv/ssp-1.c | 41 +++++++ + gcc/testsuite/gcc.target/riscv/ssp-2.c | 10 ++ + libgcc/config/riscv/linux-unwind.h | 5 + + libgcc/config/riscv/shadow-stack-unwind.h | 74 +++++++++++++ + 10 files changed, 322 insertions(+), 10 deletions(-) + create mode 100644 gcc/testsuite/gcc.target/riscv/ssp-1.c + create mode 100644 gcc/testsuite/gcc.target/riscv/ssp-2.c + create mode 100644 libgcc/config/riscv/shadow-stack-unwind.h + +diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc +index 171808fe367..a800821641c 100644 +--- a/gcc/common/config/riscv/riscv-common.cc ++++ b/gcc/common/config/riscv/riscv-common.cc +@@ -111,6 +111,9 @@ static const riscv_implied_info_t riscv_implied_info[] = + + {"zcmop", "zca"}, + ++ {"zicfiss", "zicsr"}, ++ {"zicfiss", "zimop"}, ++ + {"zk", "zkn"}, + {"zk", "zkr"}, + {"zk", "zkt"}, +@@ -323,6 +326,8 @@ static const struct riscv_ext_version riscv_ext_version_table[] = + {"zicclsm", ISA_SPEC_CLASS_NONE, 1, 0}, + {"ziccrse", ISA_SPEC_CLASS_NONE, 1, 0}, + ++ {"zicfiss", ISA_SPEC_CLASS_NONE, 1, 0}, ++ + {"zimop", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zcmop", ISA_SPEC_CLASS_NONE, 1, 0}, + +@@ -1638,6 +1643,8 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = + RISCV_EXT_FLAG_ENTRY ("zicbop", x_riscv_zicmo_subext, MASK_ZICBOP), + RISCV_EXT_FLAG_ENTRY ("zic64b", x_riscv_zicmo_subext, MASK_ZIC64B), + ++ RISCV_EXT_FLAG_ENTRY ("zicfiss", x_riscv_zi_subext, MASK_ZICFISS), ++ + RISCV_EXT_FLAG_ENTRY ("zimop", x_riscv_mop_subext, MASK_ZIMOP), + RISCV_EXT_FLAG_ENTRY ("zcmop", x_riscv_mop_subext, MASK_ZCMOP), + +diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md +index 6a895a6970c..9aecdecdbb8 100644 +--- a/gcc/config/riscv/predicates.md ++++ b/gcc/config/riscv/predicates.md +@@ -668,3 +668,9 @@ + return (riscv_symbolic_constant_p (op, &type) + && type == SYMBOL_PCREL); + }) ++ ++;; Shadow stack operands only allow x1, x5 registers ++(define_predicate "x1x5_operand" ++ (and (match_operand 0 "register_operand") ++ (match_test "REGNO (op) == RETURN_ADDR_REGNUM ++ || REGNO (op) == T0_REGNUM"))) +diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc +index a5698818b9b..2a7af441199 100644 +--- a/gcc/config/riscv/riscv.cc ++++ b/gcc/config/riscv/riscv.cc +@@ -6852,6 +6852,9 @@ riscv_save_reg_p (unsigned int regno) + if (regno == GP_REGNUM || regno == THREAD_POINTER_REGNUM) + return false; + ++ if (regno == RETURN_ADDR_REGNUM && TARGET_ZICFISS) ++ return true; ++ + /* We must save every register used in this function. If this is not a + leaf function, then we must save all temporary registers. */ + if (df_regs_ever_live_p (regno) +@@ -7386,7 +7389,7 @@ riscv_is_eh_return_data_register (unsigned int regno) + + static void + riscv_for_each_saved_reg (poly_int64 sp_offset, riscv_save_restore_fn fn, +- bool epilogue, bool maybe_eh_return) ++ bool epilogue, bool maybe_eh_return, bool sibcall_p) + { + HOST_WIDE_INT offset, first_fp_offset; + unsigned int regno, num_masked_fp = 0; +@@ -7472,7 +7475,14 @@ riscv_for_each_saved_reg (poly_int64 sp_offset, riscv_save_restore_fn fn, + } + } + +- riscv_save_restore_reg (word_mode, regno, offset, fn); ++ if (need_shadow_stack_push_pop_p () && epilogue && !sibcall_p ++ && !(maybe_eh_return && crtl->calls_eh_return) ++ && (regno == RETURN_ADDR_REGNUM) ++ && !cfun->machine->interrupt_handler_p) ++ riscv_save_restore_reg (word_mode, RISCV_PROLOGUE_TEMP_REGNUM, ++ offset, fn); ++ else ++ riscv_save_restore_reg (word_mode, regno, offset, fn); + } + + /* This loop must iterate over the same space as its companion in +@@ -7779,7 +7789,10 @@ riscv_expand_prologue (void) + if (cfun->machine->naked_p) + return; + +- /* prefer muti-push to save-restore libcall. */ ++ if (need_shadow_stack_push_pop_p ()) ++ emit_insn (gen_sspush (Pmode, gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM))); ++ ++ /* prefer multi-push to save-restore libcall. */ + if (riscv_use_multi_push (frame)) + { + remaining_size -= frame->multi_push_adj_base; +@@ -7822,7 +7835,7 @@ riscv_expand_prologue (void) + = get_multi_push_fpr_mask (multi_push_additional / UNITS_PER_WORD); + frame->fmask &= mask_fprs_push; + riscv_for_each_saved_reg (remaining_size, riscv_save_reg, false, +- false); ++ false, false); + frame->fmask = fmask & ~mask_fprs_push; /* mask for the rest FPRs. */ + } + } +@@ -7873,7 +7886,8 @@ riscv_expand_prologue (void) + GEN_INT (-step1)); + RTX_FRAME_RELATED_P (emit_insn (insn)) = 1; + } +- riscv_for_each_saved_reg (remaining_size, riscv_save_reg, false, false); ++ riscv_for_each_saved_reg (remaining_size, riscv_save_reg, ++ false, false, false); + } + + /* Undo the above fib. */ +@@ -8052,6 +8066,7 @@ riscv_expand_epilogue (int style) + = use_multi_pop ? frame->multi_push_adj_base + frame->multi_push_adj_addi + : 0; + rtx ra = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM); ++ rtx t0 = gen_rtx_REG (Pmode, RISCV_PROLOGUE_TEMP_REGNUM); + unsigned th_int_mask = 0; + rtx insn; + +@@ -8231,7 +8246,8 @@ riscv_expand_epilogue (int style) + riscv_for_each_saved_v_reg (step2, riscv_restore_reg, false); + riscv_for_each_saved_reg (frame->total_size - step2 - libcall_size + - multipop_size, +- riscv_restore_reg, true, style == EXCEPTION_RETURN); ++ riscv_restore_reg, true, style == EXCEPTION_RETURN, ++ style == SIBCALL_RETURN); + + if (th_int_mask && TH_INT_INTERRUPT (cfun)) + { +@@ -8271,7 +8287,8 @@ riscv_expand_epilogue (int style) + riscv_for_each_saved_reg (frame->total_size - libcall_size + - multipop_size, + riscv_restore_reg, true, +- style == EXCEPTION_RETURN); ++ style == EXCEPTION_RETURN, false); ++ + /* Undo the above fib. */ + frame->mask = mask; + frame->fmask = fmask; +@@ -8296,6 +8313,17 @@ riscv_expand_epilogue (int style) + emit_insn (gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx, + EH_RETURN_STACKADJ_RTX)); + ++ if (need_shadow_stack_push_pop_p () ++ && !((style == EXCEPTION_RETURN) && crtl->calls_eh_return)) ++ { ++ if (BITSET_P (cfun->machine->frame.mask, RETURN_ADDR_REGNUM) ++ && style != SIBCALL_RETURN ++ && !cfun->machine->interrupt_handler_p) ++ emit_insn (gen_sspopchk (Pmode, t0)); ++ else ++ emit_insn (gen_sspopchk (Pmode, ra)); ++ } ++ + /* Return from interrupt. */ + if (cfun->machine->interrupt_handler_p) + { +@@ -8313,7 +8341,15 @@ riscv_expand_epilogue (int style) + emit_jump_insn (gen_riscv_uret ()); + } + else if (style != SIBCALL_RETURN) +- emit_jump_insn (gen_simple_return_internal (ra)); ++ { ++ if (need_shadow_stack_push_pop_p () ++ && !((style == EXCEPTION_RETURN) && crtl->calls_eh_return) ++ && BITSET_P (cfun->machine->frame.mask, RETURN_ADDR_REGNUM) ++ && !cfun->machine->interrupt_handler_p) ++ emit_jump_insn (gen_simple_return_internal (t0)); ++ else ++ emit_jump_insn (gen_simple_return_internal (ra)); ++ } + } + + /* Implement EPILOGUE_USES. */ +@@ -8510,7 +8546,8 @@ bool + riscv_can_use_return_insn (void) + { + return (reload_completed && known_eq (cfun->machine->frame.total_size, 0) +- && ! cfun->machine->interrupt_handler_p); ++ && ! cfun->machine->interrupt_handler_p ++ && ! need_shadow_stack_push_pop_p ()); + } + + /* Given that there exists at least one variable that is set (produced) +@@ -11328,6 +11365,11 @@ riscv_get_raw_result_mode (int regno) + return default_get_reg_raw_mode (regno); + } + ++bool need_shadow_stack_push_pop_p () ++{ ++ return TARGET_ZICFISS && riscv_save_return_addr_reg_p (); ++} ++ + /* Initialize the GCC target structure. */ + #undef TARGET_ASM_ALIGNED_HI_OP + #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" +diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h +index 9bd5b26cb2f..829c10988dc 100644 +--- a/gcc/config/riscv/riscv.h ++++ b/gcc/config/riscv/riscv.h +@@ -1152,6 +1152,7 @@ extern poly_int64 riscv_v_adjust_nunits (enum machine_mode, int); + extern poly_int64 riscv_v_adjust_nunits (machine_mode, bool, int, int); + extern poly_int64 riscv_v_adjust_precision (enum machine_mode, int); + extern poly_int64 riscv_v_adjust_bytesize (enum machine_mode, int); ++extern bool need_shadow_stack_push_pop_p (); + /* The number of bits and bytes in a RVV vector. */ + #define BITS_PER_RISCV_VECTOR (poly_uint16 (riscv_vector_chunks * riscv_bytes_per_vector_chunk * 8)) + #define BYTES_PER_RISCV_VECTOR (poly_uint16 (riscv_vector_chunks * riscv_bytes_per_vector_chunk)) +diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md +index 0a98d862b5b..e3d66c584d5 100644 +--- a/gcc/config/riscv/riscv.md ++++ b/gcc/config/riscv/riscv.md +@@ -133,6 +133,12 @@ + ;; Zihintpause unspec + UNSPECV_PAUSE + ++ ;; ZICFISS ++ UNSPECV_SSPUSH ++ UNSPECV_SSPOPCHK ++ UNSPECV_SSRDP ++ UNSPECV_SSP ++ + ;; XTheadInt unspec + UNSPECV_XTHEADINT_PUSH + UNSPECV_XTHEADINT_POP +@@ -3848,6 +3854,30 @@ + (set_attr "length" "0")] + ) + ++(define_expand "save_stack_nonlocal" ++ [(set (match_operand 0 "memory_operand") ++ (match_operand 1 "register_operand"))] ++ "" ++{ ++ rtx stack_slot; ++ ++ if (need_shadow_stack_push_pop_p ()) ++ { ++ /* Copy shadow stack pointer to the first slot ++ and stack pointer to the second slot. */ ++ rtx ssp_slot = adjust_address (operands[0], word_mode, 0); ++ stack_slot = adjust_address (operands[0], Pmode, UNITS_PER_WORD); ++ ++ rtx reg_ssp = force_reg (word_mode, const0_rtx); ++ emit_insn (gen_ssrdp (word_mode, reg_ssp)); ++ emit_move_insn (ssp_slot, reg_ssp); ++ } ++ else ++ stack_slot = adjust_address (operands[0], Pmode, 0); ++ emit_move_insn (stack_slot, operands[1]); ++ DONE; ++}) ++ + ;; This fixes a failure with gcc.c-torture/execute/pr64242.c at -O2 for a + ;; 32-bit target when using -mtune=sifive-7-series. The first sched pass + ;; runs before register elimination, and we have a non-obvious dependency +@@ -3858,7 +3888,70 @@ + (match_operand 1 "memory_operand")] + "" + { +- emit_move_insn (operands[0], operands[1]); ++ rtx stack_slot; ++ ++ if (need_shadow_stack_push_pop_p ()) ++ { ++ rtx t0 = gen_rtx_REG (Pmode, RISCV_PROLOGUE_TEMP_REGNUM); ++ /* Restore shadow stack pointer from the first slot ++ and stack pointer from the second slot. */ ++ rtx ssp_slot = adjust_address (operands[1], word_mode, 0); ++ stack_slot = adjust_address (operands[1], Pmode, UNITS_PER_WORD); ++ ++ /* Get the current shadow stack pointer. */ ++ rtx cur_ssp = force_reg (word_mode, const0_rtx); ++ emit_insn (gen_ssrdp (word_mode, cur_ssp)); ++ ++ /* Compare and jump over adjustment code. */ ++ rtx noadj_label = gen_label_rtx (); ++ emit_cmp_and_jump_insns (cur_ssp, const0_rtx, EQ, NULL_RTX, ++ word_mode, 1, noadj_label); ++ ++ rtx loop_label = gen_label_rtx (); ++ emit_label (loop_label); ++ LABEL_NUSES (loop_label) = 1; ++ ++ /* Check if current ssp less than jump buffer ssp, ++ so no loop is needed. */ ++ emit_cmp_and_jump_insns (ssp_slot, cur_ssp, LE, NULL_RTX, ++ ptr_mode, 1, noadj_label); ++ ++ /* Advance by a maximum of 4K at a time to avoid unwinding ++ past bounds of the shadow stack. */ ++ rtx reg_4096 = force_reg (word_mode, GEN_INT (4096)); ++ rtx cmp_ssp = gen_reg_rtx (word_mode); ++ cmp_ssp = expand_simple_binop (ptr_mode, MINUS, ++ ssp_slot, cur_ssp, ++ cmp_ssp, 1, OPTAB_DIRECT); ++ ++ /* Update curr_ssp from jump buffer ssp. */ ++ emit_move_insn (cur_ssp, ssp_slot); ++ emit_insn (gen_write_ssp (word_mode, cur_ssp)); ++ emit_jump_insn (gen_jump (loop_label)); ++ emit_barrier (); ++ ++ /* Adjust the ssp in a loop. */ ++ rtx cmp_4k_label = gen_label_rtx (); ++ emit_label (cmp_4k_label); ++ LABEL_NUSES (cmp_4k_label) = 1; ++ ++ /* Add 4k for curr_ssp. */ ++ cur_ssp = expand_simple_binop (ptr_mode, PLUS, ++ cur_ssp, reg_4096, ++ cur_ssp, 1, OPTAB_DIRECT); ++ emit_insn (gen_write_ssp (word_mode, cur_ssp)); ++ emit_insn (gen_sspush (Pmode, t0)); ++ emit_insn (gen_sspopchk (Pmode, t0)); ++ emit_jump_insn (gen_jump (loop_label)); ++ emit_barrier (); ++ ++ emit_label (noadj_label); ++ LABEL_NUSES (noadj_label) = 1; ++ } ++ else ++ stack_slot = adjust_address (operands[1], Pmode, 0); ++ ++ emit_move_insn (operands[0], stack_slot); + /* Prevent the following hard fp restore from being moved before the move + insn above which uses a copy of the soft fp reg. */ + emit_clobber (gen_rtx_MEM (BLKmode, hard_frame_pointer_rtx)); +@@ -4121,6 +4214,37 @@ + [(set_attr "type" "load") + (set (attr "length") (const_int 8))]) + ++;; Shadow stack ++ ++(define_insn "@sspush" ++ [(unspec_volatile [(match_operand:P 0 "x1x5_operand" "r")] UNSPECV_SSPUSH)] ++ "TARGET_ZICFISS" ++ "sspush\t%0" ++ [(set_attr "type" "arith") ++ (set_attr "mode" "")]) ++ ++(define_insn "@sspopchk" ++ [(unspec_volatile [(match_operand:P 0 "x1x5_operand" "r")] UNSPECV_SSPOPCHK)] ++ "TARGET_ZICFISS" ++ "sspopchk\t%0" ++ [(set_attr "type" "arith") ++ (set_attr "mode" "")]) ++ ++(define_insn "@ssrdp" ++ [(set (match_operand:P 0 "register_operand" "=r") ++ (unspec_volatile [(const_int 0)] UNSPECV_SSRDP))] ++ "TARGET_ZICFISS" ++ "ssrdp\t%0" ++ [(set_attr "type" "arith") ++ (set_attr "mode" "")]) ++ ++(define_insn "@write_ssp" ++ [(unspec_volatile [(match_operand:P 0 "register_operand" "r")] UNSPECV_SSP)] ++ "TARGET_ZICFISS" ++ "csrw\tssp, %0" ++ [(set_attr "type" "arith") ++ (set_attr "mode" "")]) ++ + (include "bitmanip.md") + (include "crypto.md") + (include "sync.md") +diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt +index a13c2ff53a0..896e35733bd 100644 +--- a/gcc/config/riscv/riscv.opt ++++ b/gcc/config/riscv/riscv.opt +@@ -253,6 +253,8 @@ Mask(ZICCLSM) Var(riscv_zi_subext) + + Mask(ZICCRSE) Var(riscv_zi_subext) + ++Mask(ZICFISS) Var(riscv_zi_subext) ++ + TargetVariable + int riscv_za_subext + +diff --git a/gcc/testsuite/gcc.target/riscv/ssp-1.c b/gcc/testsuite/gcc.target/riscv/ssp-1.c +new file mode 100644 +index 00000000000..abf47ec6442 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/ssp-1.c +@@ -0,0 +1,41 @@ ++/* { dg-do compile { target { riscv64*-*-* } } } */ ++/* { dg-options "-O2 -march=rv64gc_zicfiss -mabi=lp64d" } */ ++/* { dg-skip-if "" { *-*-* } { "-O0" } } */ ++struct ad { ++ void *ae; ++}; ++struct af { ++ union { ++ int *ai; ++ int *aj; ++ struct ad *ak; ++ } u; ++ struct { ++ struct { ++ long al : 1; ++ long am : 1; ++ long : 21; ++ } b; ++ long i; ++ } s; ++}; ++void fdes (struct af *, void *, long *); ++ ++void foo (struct af *bv, long *bw) { ++ bw[0] = bw[1] = 0; ++ if (bv->s.b.al) ++ fdes (bv, bv->u.ak->ae, bw); ++ else if (bv->s.b.am) { ++ int **p = (int**)bv->u.aj; ++ for (; *p; ++p) ++ fdes (bv, *p, bw); ++ } else ++ fdes (bv, bv->u.ai, bw); ++} ++ ++/* { dg-final { scan-assembler-times "ld\tt0" 1 } } */ ++/* { dg-final { scan-assembler-times "sspopchk\tt0" 1 } } */ ++/* { dg-final { scan-assembler-times "jr\tt0" 1 } } */ ++/* { dg-final { scan-assembler-times "ld\tra" 2 } } */ ++/* { dg-final { scan-assembler-times "sspopchk\tra" 2 } } */ ++/* { dg-final { scan-assembler-times "tail" 2 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/ssp-2.c b/gcc/testsuite/gcc.target/riscv/ssp-2.c +new file mode 100644 +index 00000000000..7c6098357e9 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/ssp-2.c +@@ -0,0 +1,10 @@ ++/* { dg-do compile { target { riscv64*-*-* } } } */ ++/* { dg-options "-O0 -march=rv64gc_zicfiss -mabi=lp64d" } */ ++ ++void __attribute__ ((interrupt)) ++foo (void) ++{ ++} ++/* { dg-final { scan-assembler-times "sd\tra" 1 } } */ ++/* { dg-final { scan-assembler-times "ld\tra" 1 } } */ ++/* { dg-final { scan-assembler-times "sspopchk\tra" 1 } } */ +diff --git a/libgcc/config/riscv/linux-unwind.h b/libgcc/config/riscv/linux-unwind.h +index 28b195661fc..b4d47b8161e 100644 +--- a/libgcc/config/riscv/linux-unwind.h ++++ b/libgcc/config/riscv/linux-unwind.h +@@ -19,6 +19,11 @@ + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + . */ + ++/* Unwind shadow stack. */ ++#if defined(__riscv_zicfiss) ++# include "config/riscv/shadow-stack-unwind.h" ++#endif ++ + #ifndef inhibit_libc + + #include +diff --git a/libgcc/config/riscv/shadow-stack-unwind.h b/libgcc/config/riscv/shadow-stack-unwind.h +new file mode 100644 +index 00000000000..a978a54a4ca +--- /dev/null ++++ b/libgcc/config/riscv/shadow-stack-unwind.h +@@ -0,0 +1,74 @@ ++/* _Unwind_Frames_Extra with shadow stack. ++ Copyright (C) 2016-2025 Free Software Foundation, Inc. ++ ++This file is part of GCC. ++ ++GCC is free software; you can redistribute it and/or modify ++it under the terms of the GNU General Public License as published by ++the Free Software Foundation; either version 3, or (at your option) ++any later version. ++ ++GCC is distributed in the hope that it will be useful, ++but WITHOUT ANY WARRANTY; without even the implied warranty of ++MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++GNU General Public License for more details. ++ ++Under Section 7 of GPL version 3, you are granted additional ++permissions described in the GCC Runtime Library Exception, version ++3.1, as published by the Free Software Foundation. ++ ++You should have received a copy of the GNU General Public License and ++a copy of the GCC Runtime Library Exception along with this program; ++see the files COPYING3 and COPYING.RUNTIME respectively. If not, see ++. */ ++ ++#define LIBGCC2_UNITS_PER_WORD (__riscv_xlen / 8) ++ ++/* Unwind the shadow stack for EH. */ ++#undef _Unwind_Frames_Extra ++#define _Unwind_Frames_Extra(x) \ ++ do \ ++ { \ ++ _Unwind_Word ssp = 0; \ ++ asm volatile ("ssrdp %0" : "=r"(ssp)); \ ++ if (ssp != 0) \ ++ { \ ++ _Unwind_Word tmp = (x); \ ++ tmp = tmp * LIBGCC2_UNITS_PER_WORD; \ ++ while (tmp > 4096) \ ++ { \ ++ ssp += 4096; \ ++ tmp -= 4096; \ ++ asm volatile ("csrw ssp, %0" :: "r"(ssp)); \ ++ asm volatile ("sspush x5\n" \ ++ "sspopchk x5" : : : "x5"); \ ++ } \ ++ \ ++ if (tmp > 0) \ ++ { \ ++ ssp += tmp; \ ++ asm volatile ("csrw ssp, %0" :: "r"(ssp)); \ ++ } \ ++ } \ ++ } \ ++ while (0) ++ ++#undef _Unwind_Frames_Increment ++#define _Unwind_Frames_Increment(exc, context, frames) \ ++ { \ ++ frames++; \ ++ if (exc->exception_class != 0 \ ++ && _Unwind_GetIP (context) != 0 \ ++ && !_Unwind_IsSignalFrame (context)) \ ++ { \ ++ _Unwind_Word ssp; \ ++ asm volatile ("ssrdp %0" : "=r"(ssp)); \ ++ if (ssp != 0) \ ++ { \ ++ ssp += LIBGCC2_UNITS_PER_WORD * frames; \ ++ _Unwind_Word ra = *(_Unwind_Word *) ssp; \ ++ if (ra != _Unwind_GetIP (context)) \ ++ return _URC_FATAL_PHASE2_ERROR; \ ++ } \ ++ } \ ++ } +-- +2.47.3 + diff --git a/1073-RISC-V-Add-Zicfilp-ISA-extension.patch b/1073-RISC-V-Add-Zicfilp-ISA-extension.patch new file mode 100644 index 0000000..860308f --- /dev/null +++ b/1073-RISC-V-Add-Zicfilp-ISA-extension.patch @@ -0,0 +1,761 @@ +From a98f52c90642234ccaf7949d2d525b2e8c192058 Mon Sep 17 00:00:00 2001 +From: Monk Chiang +Date: Fri, 22 Mar 2024 21:00:24 +0800 +Subject: [PATCH 1073/1087] RISC-V: Add Zicfilp ISA extension. + +commit 805a052d0083e8e76c720fd7ac52cb3ccc36c310 upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +This patch only support landing pad value is 0. +The next version will implement function signature based labeling +scheme. + +RISC-V CFI SPEC: https://github.com/riscv/riscv-cfi + +gcc/ChangeLog: + * common/config/riscv/riscv-common.cc: Add ZICFILP ISA + string. + * config.gcc: Add riscv-zicfilp.o + * config/riscv/riscv-passes.def (INSERT_PASS_BEFORE): + Insert landing pad instructions. + * config/riscv/riscv-protos.h (make_pass_insert_landing_pad): + Declare. + * config/riscv/riscv-zicfilp.cc: New file. + * config/riscv/riscv.cc + (riscv_trampoline_init): Add landing pad instructions. + (riscv_legitimize_call_address): Likewise. + (riscv_output_mi_thunk): Likewise. + * config/riscv/riscv.h: Update. + * config/riscv/riscv.md: Add landing pad patterns. + * config/riscv/riscv.opt (TARGET_ZICFILP): Define. + * config/riscv/t-riscv: Add build rule for + riscv-zicfilp.o + +gcc/testsuite/ChangeLog: + * gcc.target/riscv/interrupt-no-lpad.c: New test. + * gcc.target/riscv/zicfilp-call.c: New test. + + Co-Developed-by: Greg McGary , + Kito Cheng +--- + gcc/common/config/riscv/riscv-common.cc | 3 + + gcc/config.gcc | 2 +- + gcc/config/riscv/riscv-passes.def | 1 + + gcc/config/riscv/riscv-protos.h | 1 + + gcc/config/riscv/riscv-zicfilp.cc | 169 ++++++++++++++++++ + gcc/config/riscv/riscv.cc | 145 ++++++++++++--- + gcc/config/riscv/riscv.h | 13 +- + gcc/config/riscv/riscv.md | 73 +++++++- + gcc/config/riscv/riscv.opt | 2 + + gcc/config/riscv/t-riscv | 9 + + .../gcc.target/riscv/interrupt-no-lpad.c | 7 + + gcc/testsuite/gcc.target/riscv/zicfilp-call.c | 14 ++ + 12 files changed, 402 insertions(+), 37 deletions(-) + create mode 100644 gcc/config/riscv/riscv-zicfilp.cc + create mode 100644 gcc/testsuite/gcc.target/riscv/interrupt-no-lpad.c + create mode 100644 gcc/testsuite/gcc.target/riscv/zicfilp-call.c + +diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc +index a800821641c..b382ef4366c 100644 +--- a/gcc/common/config/riscv/riscv-common.cc ++++ b/gcc/common/config/riscv/riscv-common.cc +@@ -113,6 +113,7 @@ static const riscv_implied_info_t riscv_implied_info[] = + + {"zicfiss", "zicsr"}, + {"zicfiss", "zimop"}, ++ {"zicfilp", "zicsr"}, + + {"zk", "zkn"}, + {"zk", "zkr"}, +@@ -327,6 +328,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] = + {"ziccrse", ISA_SPEC_CLASS_NONE, 1, 0}, + + {"zicfiss", ISA_SPEC_CLASS_NONE, 1, 0}, ++ {"zicfilp", ISA_SPEC_CLASS_NONE, 1, 0}, + + {"zimop", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zcmop", ISA_SPEC_CLASS_NONE, 1, 0}, +@@ -1644,6 +1646,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = + RISCV_EXT_FLAG_ENTRY ("zic64b", x_riscv_zicmo_subext, MASK_ZIC64B), + + RISCV_EXT_FLAG_ENTRY ("zicfiss", x_riscv_zi_subext, MASK_ZICFISS), ++ RISCV_EXT_FLAG_ENTRY ("zicfilp", x_riscv_zi_subext, MASK_ZICFILP), + + RISCV_EXT_FLAG_ENTRY ("zimop", x_riscv_mop_subext, MASK_ZIMOP), + RISCV_EXT_FLAG_ENTRY ("zcmop", x_riscv_mop_subext, MASK_ZCMOP), +diff --git a/gcc/config.gcc b/gcc/config.gcc +index 6cdaa1e80a6..e5dfa561f5d 100644 +--- a/gcc/config.gcc ++++ b/gcc/config.gcc +@@ -551,7 +551,7 @@ riscv*) + extra_objs="riscv-builtins.o riscv-c.o riscv-sr.o riscv-shorten-memrefs.o riscv-selftests.o riscv-string.o" + extra_objs="${extra_objs} riscv-v.o riscv-vsetvl.o riscv-vector-costs.o riscv-avlprop.o" + extra_objs="${extra_objs} riscv-vector-builtins.o riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o" +- extra_objs="${extra_objs} thead.o riscv-target-attr.o" ++ extra_objs="${extra_objs} thead.o riscv-target-attr.o riscv-zicfilp.o" + d_target_objs="riscv-d.o" + extra_headers="riscv_vector.h riscv_crypto.h riscv_bitmanip.h riscv_th_vector.h riscv_cmo.h" + target_gtfiles="$target_gtfiles \$(srcdir)/config/riscv/riscv-vector-builtins.cc" +diff --git a/gcc/config/riscv/riscv-passes.def b/gcc/config/riscv/riscv-passes.def +index 32b79a78f0b..189a8e87188 100644 +--- a/gcc/config/riscv/riscv-passes.def ++++ b/gcc/config/riscv/riscv-passes.def +@@ -20,3 +20,4 @@ + INSERT_PASS_AFTER (pass_rtl_store_motion, 1, pass_shorten_memrefs); + INSERT_PASS_AFTER (pass_split_all_insns, 1, pass_avlprop); + INSERT_PASS_BEFORE (pass_fast_rtl_dce, 1, pass_vsetvl); ++INSERT_PASS_BEFORE (pass_shorten_branches, 1, pass_insert_landing_pad); +diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h +index 2f6f783f289..73add1684d4 100644 +--- a/gcc/config/riscv/riscv-protos.h ++++ b/gcc/config/riscv/riscv-protos.h +@@ -187,6 +187,7 @@ extern bool riscv_hard_regno_rename_ok (unsigned, unsigned); + rtl_opt_pass * make_pass_shorten_memrefs (gcc::context *ctxt); + rtl_opt_pass * make_pass_avlprop (gcc::context *ctxt); + rtl_opt_pass * make_pass_vsetvl (gcc::context *ctxt); ++rtl_opt_pass * make_pass_insert_landing_pad (gcc::context *ctxt); + + /* Routines implemented in riscv-string.c. */ + extern bool riscv_expand_block_move (rtx, rtx, rtx); +diff --git a/gcc/config/riscv/riscv-zicfilp.cc b/gcc/config/riscv/riscv-zicfilp.cc +new file mode 100644 +index 00000000000..42b129920b3 +--- /dev/null ++++ b/gcc/config/riscv/riscv-zicfilp.cc +@@ -0,0 +1,169 @@ ++/* Branch Target Identification for RISCV architecture. ++ Copyright (C) 2019-2025 Free Software Foundation, Inc. ++ Based on ARM target. ++ ++ This file is part of GCC. ++ ++ GCC is free software; you can redistribute it and/or modify it ++ under the terms of the GNU General Public License as published by ++ the Free Software Foundation; either version 3, or (at your option) ++ any later version. ++ ++ GCC is distributed in the hope that it will be useful, but ++ WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with GCC; see the file COPYING3. If not see ++ . */ ++ ++#define IN_TARGET_CODE 1 ++ ++#include "config.h" ++#define INCLUDE_STRING ++#include "system.h" ++#include "coretypes.h" ++#include "backend.h" ++#include "target.h" ++#include "rtl.h" ++#include "tree.h" ++#include "memmodel.h" ++#include "gimple.h" ++#include "tm_p.h" ++#include "stringpool.h" ++#include "attribs.h" ++#include "expr.h" ++#include "emit-rtl.h" ++#include "gimplify.h" ++#include "gimple-iterator.h" ++#include "dumpfile.h" ++#include "rtl-iter.h" ++#include "cfgrtl.h" ++#include "tree-pass.h" ++#include "cgraph.h" ++#include "output.h" ++ ++/* This pass implements forward-CFI landing pad checks for RISCV. This is ++ a security feature similar to BTI (branch target identification) in ++ AArch64 and IBT (indirect branch tracking)in X86. A LPAD (landing-pad ++ check) instruction is used to guard against the execution of ++ instructions which are not the intended target of an indirect branch. ++ ++ When forward-CFI is disabled or unimplemented in the CPU, the ++ landing-pad check label instructions behave as NOP. When implemented in ++ the CPU, and enabled, the destination of an indirect branch must be ++ LPAD insn. Otherwise, the CPU reaises an exception. ++ ++ In order to enable this mechanism, this pass iterates through the ++ control flow of the code and adds appropriate LPAD instructions at the ++ beginning of any function that can be called indirectly, and for targets ++ of indirect jumps, i.e., jump table targets, non-local goto targets, and ++ labels that might be referenced by variables, constant pools, etc ++ (NOTE_INSN_DELETED_LABEL). */ ++ ++namespace { ++ ++const pass_data pass_data_insert_landing_pad = ++{ ++ RTL_PASS, /* type. */ ++ "zisslpcfi", /* name. */ ++ OPTGROUP_NONE, /* optinfo_flags. */ ++ TV_MACH_DEP, /* tv_id. */ ++ 0, /* properties_required. */ ++ 0, /* properties_provided. */ ++ 0, /* properties_destroyed. */ ++ 0, /* todo_flags_start. */ ++ 0, /* todo_flags_finish. */ ++}; ++ ++static bool ++is_interrupt_handler_p (tree type) ++{ ++ return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type)) != NULL; ++} ++ ++/* Insert landing-pad check instructions. This is a late RTL pass that runs ++ before branch shortening. */ ++static unsigned int ++rest_of_insert_landing_pad (void) ++{ ++ timevar_push (TV_MACH_DEP); ++ ++ struct cgraph_node *c_node; ++ rtx lpad_insn; ++ rtx_insn *insn; ++ basic_block bb; ++ ++ bb = 0; ++ FOR_EACH_BB_FN (bb, cfun) ++ { ++ for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); ++ insn = NEXT_INSN (insn)) ++ { ++ /* If a label is marked to be preserved or can be a non-local goto ++ target, it must be protected with a lpad instruction. */ ++ if (LABEL_P (insn) ++ && (LABEL_PRESERVE_P (insn) ++ || bb->flags & BB_NON_LOCAL_GOTO_TARGET)) ++ { ++ emit_insn_before (gen_lpad_align (), insn); ++ emit_insn_after (gen_lpad (const0_rtx), insn); ++ continue; ++ } ++ ++ if (INSN_P (insn) && INSN_CODE (insn) == CODE_FOR_gpr_save) ++ { ++ emit_move_insn (RISCV_CALL_ADDRESS_LPAD (Pmode), const0_rtx); ++ emit_insn_before (gen_lpad_align (), insn); ++ emit_insn_after (gen_lpad (const0_rtx), insn); ++ continue; ++ } ++ ++ if (INSN_P (insn) && INSN_CODE (insn) == CODE_FOR_gpr_restore) ++ emit_move_insn (RISCV_CALL_ADDRESS_LPAD (Pmode), const0_rtx); ++ ++ } ++ } ++ ++ c_node = cgraph_node::get (cfun->decl); ++ if (!c_node->only_called_directly_p () ++ && !is_interrupt_handler_p (TREE_TYPE (cfun->decl))) ++ { ++ bb = ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb; ++ insn = BB_HEAD (bb); ++ lpad_insn = gen_lpad (const0_rtx); ++ emit_insn_before (lpad_insn, insn); ++ } ++ ++ timevar_pop (TV_MACH_DEP); ++ return 0; ++} ++ ++class pass_insert_landing_pad : public rtl_opt_pass ++{ ++public: ++ pass_insert_landing_pad (gcc::context *ctxt) ++ : rtl_opt_pass (pass_data_insert_landing_pad, ctxt) ++ {} ++ ++ /* opt_pass methods: */ ++ virtual bool gate (function *) ++ { ++ return TARGET_ZICFILP; ++ } ++ ++ virtual unsigned int execute (function *) ++ { ++ return rest_of_insert_landing_pad (); ++ } ++ ++}; // class pass_insert_landing_pad ++ ++} // anon namespace ++ ++rtl_opt_pass * ++make_pass_insert_landing_pad (gcc::context *ctxt) ++{ ++ return new pass_insert_landing_pad (ctxt); ++} +diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc +index 2a7af441199..090df379de6 100644 +--- a/gcc/config/riscv/riscv.cc ++++ b/gcc/config/riscv/riscv.cc +@@ -6063,8 +6063,20 @@ riscv_legitimize_call_address (rtx addr) + { + rtx reg = RISCV_CALL_ADDRESS_TEMP (Pmode); + riscv_emit_move (reg, addr); ++ ++ if (TARGET_ZICFILP) ++ { ++ rtx sw_guarded = RISCV_CALL_ADDRESS_LPAD (Pmode); ++ emit_insn (gen_set_guarded (Pmode, reg)); ++ return sw_guarded; ++ } ++ + return reg; + } ++ ++ if (TARGET_ZICFILP && REG_P (addr)) ++ emit_insn (gen_set_lpl (Pmode, const0_rtx)); ++ + return addr; + } + +@@ -9348,6 +9360,9 @@ riscv_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, + /* Mark the end of the (empty) prologue. */ + emit_note (NOTE_INSN_PROLOGUE_END); + ++ if (TARGET_ZICFILP) ++ emit_insn(gen_lpad (const0_rtx)); ++ + /* Determine if we can use a sibcall to call FUNCTION directly. */ + fnaddr = gen_rtx_MEM (FUNCTION_MODE, XEXP (DECL_RTL (function), 0)); + +@@ -9816,12 +9831,17 @@ riscv_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) + { + rtx addr, end_addr, mem; + uint32_t trampoline[4]; ++ uint32_t trampoline_cfi[6]; + unsigned int i; + HOST_WIDE_INT static_chain_offset, target_function_offset; ++ HOST_WIDE_INT lp_value = 0; + + /* Work out the offsets of the pointers from the start of the + trampoline code. */ +- gcc_assert (ARRAY_SIZE (trampoline) * 4 == TRAMPOLINE_CODE_SIZE); ++ if (!TARGET_ZICFILP) ++ gcc_assert (ARRAY_SIZE (trampoline) * 4 == TRAMPOLINE_CODE_SIZE); ++ else ++ gcc_assert (ARRAY_SIZE (trampoline_cfi) * 4 == TRAMPOLINE_CODE_SIZE); + + /* Get pointers to the beginning and end of the code block. */ + addr = force_reg (Pmode, XEXP (m_tramp, 0)); +@@ -9843,6 +9863,17 @@ riscv_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) + unsigned HOST_WIDE_INT lo_chain_code, lo_func_code; + + rtx uimm_mask = force_reg (SImode, gen_int_mode (-IMM_REACH, SImode)); ++ unsigned insn_count = 0; ++ ++ /* Insert lpad, if zicfilp is enabled. */ ++ if (TARGET_ZICFILP) ++ { ++ unsigned HOST_WIDE_INT lpad_code; ++ lpad_code = OPCODE_AUIPC | (0 << SHIFT_RD) | (lp_value << IMM_BITS); ++ mem = adjust_address (m_tramp, SImode, 0); ++ riscv_emit_move (mem, gen_int_mode (lpad_code, SImode)); ++ insn_count++; ++ } + + /* 0xfff. */ + rtx imm12_mask = gen_reg_rtx (SImode); +@@ -9856,11 +9887,14 @@ riscv_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) + hi_chain = riscv_force_binary (SImode, AND, hi_chain, + uimm_mask); + lui_hi_chain_code = OPCODE_LUI | (STATIC_CHAIN_REGNUM << SHIFT_RD); ++ rtx lui_hi_chain_value = force_reg (SImode, gen_int_mode (lui_hi_chain_code, ++ SImode)); + rtx lui_hi_chain = riscv_force_binary (SImode, IOR, hi_chain, +- gen_int_mode (lui_hi_chain_code, SImode)); +- +- mem = adjust_address (m_tramp, SImode, 0); ++ lui_hi_chain_value); ++ mem = adjust_address (m_tramp, SImode, ++ insn_count * GET_MODE_SIZE (SImode)); + riscv_emit_move (mem, riscv_swap_instruction (lui_hi_chain)); ++ insn_count++; + + /* Gen lui t0, hi(func). */ + rtx hi_func = riscv_force_binary (SImode, PLUS, target_function, +@@ -9871,8 +9905,10 @@ riscv_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) + rtx lui_hi_func = riscv_force_binary (SImode, IOR, hi_func, + gen_int_mode (lui_hi_func_code, SImode)); + +- mem = adjust_address (m_tramp, SImode, 1 * GET_MODE_SIZE (SImode)); ++ mem = adjust_address (m_tramp, SImode, ++ insn_count * GET_MODE_SIZE (SImode)); + riscv_emit_move (mem, riscv_swap_instruction (lui_hi_func)); ++ insn_count++; + + /* Gen addi t2, t2, lo(chain). */ + rtx lo_chain = riscv_force_binary (SImode, AND, chain_value, +@@ -9886,8 +9922,23 @@ riscv_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) + rtx addi_lo_chain = riscv_force_binary (SImode, IOR, lo_chain, + force_reg (SImode, GEN_INT (lo_chain_code))); + +- mem = adjust_address (m_tramp, SImode, 2 * GET_MODE_SIZE (SImode)); ++ mem = adjust_address (m_tramp, SImode, ++ insn_count * GET_MODE_SIZE (SImode)); + riscv_emit_move (mem, riscv_swap_instruction (addi_lo_chain)); ++ insn_count++; ++ ++ /* For zicfilp only, insert lui t2, 1, because use jr t0. */ ++ if (TARGET_ZICFILP) ++ { ++ unsigned HOST_WIDE_INT set_lpl_code; ++ set_lpl_code = OPCODE_LUI ++ | (RISCV_CALL_ADDRESS_LPAD_REGNUM << SHIFT_RD) ++ | (lp_value << IMM_BITS); ++ mem = adjust_address (m_tramp, SImode, ++ insn_count * GET_MODE_SIZE (SImode)); ++ riscv_emit_move (mem, gen_int_mode (set_lpl_code, SImode)); ++ insn_count++; ++ } + + /* Gen jr t0, lo(func). */ + rtx lo_func = riscv_force_binary (SImode, AND, target_function, +@@ -9899,7 +9950,7 @@ riscv_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) + rtx jr_lo_func = riscv_force_binary (SImode, IOR, lo_func, + force_reg (SImode, GEN_INT (lo_func_code))); + +- mem = adjust_address (m_tramp, SImode, 3 * GET_MODE_SIZE (SImode)); ++ mem = adjust_address (m_tramp, SImode, insn_count * GET_MODE_SIZE (SImode)); + riscv_emit_move (mem, riscv_swap_instruction (jr_lo_func)); + } + else +@@ -9907,29 +9958,65 @@ riscv_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) + static_chain_offset = TRAMPOLINE_CODE_SIZE; + target_function_offset = static_chain_offset + GET_MODE_SIZE (ptr_mode); + +- /* auipc t2, 0 +- l[wd] t0, target_function_offset(t2) +- l[wd] t2, static_chain_offset(t2) +- jr t0 +- */ +- trampoline[0] = OPCODE_AUIPC | (STATIC_CHAIN_REGNUM << SHIFT_RD); +- trampoline[1] = (Pmode == DImode ? OPCODE_LD : OPCODE_LW) +- | (RISCV_PROLOGUE_TEMP_REGNUM << SHIFT_RD) +- | (STATIC_CHAIN_REGNUM << SHIFT_RS1) +- | (target_function_offset << SHIFT_IMM); +- trampoline[2] = (Pmode == DImode ? OPCODE_LD : OPCODE_LW) +- | (STATIC_CHAIN_REGNUM << SHIFT_RD) +- | (STATIC_CHAIN_REGNUM << SHIFT_RS1) +- | (static_chain_offset << SHIFT_IMM); +- trampoline[3] = OPCODE_JALR | (RISCV_PROLOGUE_TEMP_REGNUM << SHIFT_RS1); +- +- /* Copy the trampoline code. */ +- for (i = 0; i < ARRAY_SIZE (trampoline); i++) ++ if (!TARGET_ZICFILP) + { +- if (BYTES_BIG_ENDIAN) +- trampoline[i] = __builtin_bswap32(trampoline[i]); +- mem = adjust_address (m_tramp, SImode, i * GET_MODE_SIZE (SImode)); +- riscv_emit_move (mem, gen_int_mode (trampoline[i], SImode)); ++ /* auipc t2, 0 ++ l[wd] t0, (target_function_offset)(t2) ++ l[wd] t2, (static_chain_offset)(t2) ++ jr t0 ++ */ ++ trampoline[0] = OPCODE_AUIPC | (STATIC_CHAIN_REGNUM << SHIFT_RD); ++ trampoline[1] = (Pmode == DImode ? OPCODE_LD : OPCODE_LW) ++ | (RISCV_PROLOGUE_TEMP_REGNUM << SHIFT_RD) ++ | (STATIC_CHAIN_REGNUM << SHIFT_RS1) ++ | (target_function_offset << SHIFT_IMM); ++ trampoline[2] = (Pmode == DImode ? OPCODE_LD : OPCODE_LW) ++ | (STATIC_CHAIN_REGNUM << SHIFT_RD) ++ | (STATIC_CHAIN_REGNUM << SHIFT_RS1) ++ | (static_chain_offset << SHIFT_IMM); ++ trampoline[3] = OPCODE_JALR | (RISCV_PROLOGUE_TEMP_REGNUM << SHIFT_RS1); ++ ++ /* Copy the trampoline code. */ ++ for (i = 0; i < ARRAY_SIZE (trampoline); i++) ++ { ++ if (BYTES_BIG_ENDIAN) ++ trampoline[i] = __builtin_bswap32 (trampoline[i]); ++ mem = adjust_address (m_tramp, SImode, i * GET_MODE_SIZE (SImode)); ++ riscv_emit_move (mem, gen_int_mode (trampoline[i], SImode)); ++ } ++ } ++ else ++ { ++ /* lpad 1 ++ auipc t3, 0 ++ l[wd] t0, (target_function_offset - 4)(t3) ++ l[wd] t3, (static_chain_offset - 4)(t3) ++ lui t2, 1 ++ jr t0 ++ */ ++ trampoline_cfi[0] = OPCODE_AUIPC | (0 << SHIFT_RD) | (lp_value << IMM_BITS); ++ trampoline_cfi[1] = OPCODE_AUIPC | (STATIC_CHAIN_REGNUM << SHIFT_RD); ++ trampoline_cfi[2] = (Pmode == DImode ? OPCODE_LD : OPCODE_LW) ++ | (RISCV_PROLOGUE_TEMP_REGNUM << SHIFT_RD) ++ | (STATIC_CHAIN_REGNUM << SHIFT_RS1) ++ | ((target_function_offset - 4) << SHIFT_IMM); ++ trampoline_cfi[3] = (Pmode == DImode ? OPCODE_LD : OPCODE_LW) ++ | (STATIC_CHAIN_REGNUM << SHIFT_RD) ++ | (STATIC_CHAIN_REGNUM << SHIFT_RS1) ++ | ((static_chain_offset - 4) << SHIFT_IMM); ++ trampoline_cfi[4] = OPCODE_LUI ++ | (RISCV_CALL_ADDRESS_LPAD_REGNUM << SHIFT_RD) ++ | (lp_value << IMM_BITS); ++ trampoline_cfi[5] = OPCODE_JALR | (RISCV_PROLOGUE_TEMP_REGNUM << SHIFT_RS1); ++ ++ /* Copy the trampoline code. */ ++ for (i = 0; i < ARRAY_SIZE (trampoline_cfi); i++) ++ { ++ if (BYTES_BIG_ENDIAN) ++ trampoline_cfi[i] = __builtin_bswap32 (trampoline_cfi[i]); ++ mem = adjust_address (m_tramp, SImode, i * GET_MODE_SIZE (SImode)); ++ riscv_emit_move (mem, gen_int_mode (trampoline_cfi[i], SImode)); ++ } + } + + /* Set up the static chain pointer field. */ +diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h +index 829c10988dc..faa01d27c71 100644 +--- a/gcc/config/riscv/riscv.h ++++ b/gcc/config/riscv/riscv.h +@@ -196,7 +196,8 @@ ASM_MISA_SPEC + #define PARM_BOUNDARY BITS_PER_WORD + + /* Allocation boundary (in *bits*) for the code of a function. */ +-#define FUNCTION_BOUNDARY ((TARGET_RVC || TARGET_ZCA) ? 16 : 32) ++#define FUNCTION_BOUNDARY \ ++ (((TARGET_RVC || TARGET_ZCA) && !TARGET_ZICFILP) ? 16 : 32) + + /* The smallest supported stack boundary the calling convention supports. */ + #define STACK_BOUNDARY \ +@@ -419,7 +420,8 @@ ASM_MISA_SPEC + #define RISCV_DWARF_VLENB (4096 + 0xc22) + + /* Register in which static-chain is passed to a function. */ +-#define STATIC_CHAIN_REGNUM (GP_TEMP_FIRST + 2) ++#define STATIC_CHAIN_REGNUM \ ++ ((TARGET_ZICFILP) ? (GP_TEMP_FIRST + 23) : (GP_TEMP_FIRST + 2)) + + /* Registers used as temporaries in prologue/epilogue code. + +@@ -437,6 +439,10 @@ ASM_MISA_SPEC + #define RISCV_CALL_ADDRESS_TEMP(MODE) \ + gen_rtx_REG (MODE, RISCV_CALL_ADDRESS_TEMP_REGNUM) + ++#define RISCV_CALL_ADDRESS_LPAD_REGNUM (GP_TEMP_FIRST + 2) ++#define RISCV_CALL_ADDRESS_LPAD(MODE) \ ++ gen_rtx_REG (MODE, RISCV_CALL_ADDRESS_LPAD_REGNUM) ++ + #define RETURN_ADDR_MASK (1 << RETURN_ADDR_REGNUM) + #define S0_MASK (1 << S0_REGNUM) + #define S1_MASK (1 << S1_REGNUM) +@@ -782,7 +788,8 @@ extern enum riscv_cc get_riscv_cc (const rtx use); + + /* Trampolines are a block of code followed by two pointers. */ + +-#define TRAMPOLINE_CODE_SIZE 16 ++#define TRAMPOLINE_CODE_SIZE ((TARGET_ZICFILP) ? 24 : 16) ++ + #define TRAMPOLINE_SIZE \ + ((Pmode == SImode) \ + ? TRAMPOLINE_CODE_SIZE \ +diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md +index e3d66c584d5..ea016554b4d 100644 +--- a/gcc/config/riscv/riscv.md ++++ b/gcc/config/riscv/riscv.md +@@ -139,6 +139,12 @@ + UNSPECV_SSRDP + UNSPECV_SSP + ++ ;; ZICFILP ++ UNSPECV_LPAD ++ UNSPECV_SETLPL ++ UNSPECV_LPAD_ALIGN ++ UNSPECV_SET_GUARDED ++ + ;; XTheadInt unspec + UNSPECV_XTHEADINT_PUSH + UNSPECV_XTHEADINT_POP +@@ -151,6 +157,7 @@ + (TP_REGNUM 4) + (T0_REGNUM 5) + (T1_REGNUM 6) ++ (T2_REGNUM 7) + (S0_REGNUM 8) + (S1_REGNUM 9) + (A0_REGNUM 10) +@@ -3441,11 +3448,18 @@ + [(set (pc) (match_operand 0 "register_operand"))] + "" + { ++ if (TARGET_ZICFILP) ++ emit_insn (gen_set_lpl (Pmode, const0_rtx)); ++ + operands[0] = force_reg (Pmode, operands[0]); ++ if (TARGET_ZICFILP) ++ emit_use (gen_rtx_REG (Pmode, T2_REGNUM)); ++ + if (Pmode == SImode) + emit_jump_insn (gen_indirect_jumpsi (operands[0])); + else + emit_jump_insn (gen_indirect_jumpdi (operands[0])); ++ + DONE; + }) + +@@ -3466,21 +3480,42 @@ + gen_rtx_LABEL_REF (Pmode, operands[1]), + NULL_RTX, 0, OPTAB_DIRECT); + +- if (CASE_VECTOR_PC_RELATIVE && Pmode == DImode) +- emit_jump_insn (gen_tablejumpdi (operands[0], operands[1])); ++ if (TARGET_ZICFILP) ++ { ++ rtx t2 = RISCV_CALL_ADDRESS_LPAD (GET_MODE (operands[0])); ++ emit_move_insn (t2, operands[0]); ++ ++ if (CASE_VECTOR_PC_RELATIVE && Pmode == DImode) ++ emit_jump_insn (gen_tablejump_cfidi (operands[1])); ++ else ++ emit_jump_insn (gen_tablejump_cfisi (operands[1])); ++ } + else +- emit_jump_insn (gen_tablejumpsi (operands[0], operands[1])); ++ { ++ if (CASE_VECTOR_PC_RELATIVE && Pmode == DImode) ++ emit_jump_insn (gen_tablejumpdi (operands[0], operands[1])); ++ else ++ emit_jump_insn (gen_tablejumpsi (operands[0], operands[1])); ++ } + DONE; + }) + + (define_insn "tablejump" + [(set (pc) (match_operand:GPR 0 "register_operand" "l")) + (use (label_ref (match_operand 1 "" "")))] +- "" ++ "!TARGET_ZICFILP" + "jr\t%0" + [(set_attr "type" "jalr") + (set_attr "mode" "none")]) + ++(define_insn "tablejump_cfi" ++ [(set (pc) (reg:GPR T2_REGNUM)) ++ (use (label_ref (match_operand 0 "")))] ++ "TARGET_ZICFILP" ++ "jr\tt2" ++ [(set_attr "type" "jalr") ++ (set_attr "mode" "none")]) ++ + ;; + ;; .................... + ;; +@@ -4245,6 +4280,36 @@ + [(set_attr "type" "arith") + (set_attr "mode" "")]) + ++;; Lading pad. ++ ++(define_insn "lpad" ++ [(unspec_volatile [(match_operand 0 "immediate_operand" "i")] UNSPECV_LPAD)] ++ "TARGET_ZICFILP" ++ "lpad\t%0" ++ [(set_attr "type" "auipc")]) ++ ++(define_insn "@set_lpl" ++ [(set (reg:GPR T2_REGNUM) ++ (unspec_volatile [(match_operand:GPR 0 "immediate_operand" "i")] UNSPECV_SETLPL))] ++ "TARGET_ZICFILP" ++ "lui\tt2,%0" ++ [(set_attr "type" "const") ++ (set_attr "mode" "")]) ++ ++(define_insn "lpad_align" ++ [(unspec_volatile [(const_int 0)] UNSPECV_LPAD_ALIGN)] ++ "TARGET_ZICFILP" ++ ".align 2" ++ [(set_attr "type" "nop")]) ++ ++(define_insn "@set_guarded" ++ [(set (reg:GPR T2_REGNUM) ++ (unspec_volatile [(match_operand:GPR 0 "register_operand" "r")] UNSPECV_SET_GUARDED))] ++ "TARGET_ZICFILP" ++ "mv\tt2,%0" ++ [(set_attr "type" "move") ++ (set_attr "mode" "")]) ++ + (include "bitmanip.md") + (include "crypto.md") + (include "sync.md") +diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt +index 896e35733bd..7d7d85203c6 100644 +--- a/gcc/config/riscv/riscv.opt ++++ b/gcc/config/riscv/riscv.opt +@@ -255,6 +255,8 @@ Mask(ZICCRSE) Var(riscv_zi_subext) + + Mask(ZICFISS) Var(riscv_zi_subext) + ++Mask(ZICFILP) Var(riscv_zi_subext) ++ + TargetVariable + int riscv_za_subext + +diff --git a/gcc/config/riscv/t-riscv b/gcc/config/riscv/t-riscv +index 38494320d8b..b36181dc995 100644 +--- a/gcc/config/riscv/t-riscv ++++ b/gcc/config/riscv/t-riscv +@@ -127,6 +127,15 @@ thead.o: $(srcdir)/config/riscv/thead.cc \ + $(COMPILE) $< + $(POSTCOMPILE) + ++riscv-zicfilp.o: $(srcdir)/config/riscv/riscv-zicfilp.cc \ ++ $(CONFIG_H) $(SYSTEM_H) $(TM_H) $(REGS_H) insn-config.h $(RTL_BASE_H) \ ++ dominance.h cfg.h cfganal.h $(BASIC_BLOCK_H) $(INSN_ATTR_H) $(RECOG_H) \ ++ output.h hash-map.h $(DF_H) $(OBSTACK_H) $(TARGET_H) $(RTL_H) \ ++ $(CONTEXT_H) $(TREE_PASS_H) regrename.h \ ++ $(srcdir)/config/riscv/riscv-protos.h ++ $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \ ++ $(srcdir)/config/riscv/riscv-zicfilp.cc ++ + PASSES_EXTRA += $(srcdir)/config/riscv/riscv-passes.def + + $(common_out_file): $(srcdir)/config/riscv/riscv-cores.def \ +diff --git a/gcc/testsuite/gcc.target/riscv/interrupt-no-lpad.c b/gcc/testsuite/gcc.target/riscv/interrupt-no-lpad.c +new file mode 100644 +index 00000000000..ff512b98c61 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/interrupt-no-lpad.c +@@ -0,0 +1,7 @@ ++/* { dg-do compile { target { riscv64*-*-* } } } */ ++/* { dg-options "-march=rv64gc_zicfilp -mabi=lp64d" } */ ++void __attribute__ ((interrupt)) ++foo (void) ++{ ++} ++/* { dg-final { scan-assembler-not "lpad\t" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/zicfilp-call.c b/gcc/testsuite/gcc.target/riscv/zicfilp-call.c +new file mode 100644 +index 00000000000..75c8b32faa3 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/zicfilp-call.c +@@ -0,0 +1,14 @@ ++/* { dg-do compile { target { riscv64*-*-* } } } */ ++/* { dg-options "-O2 -fPIE -march=rv64gc_zicfilp -mabi=lp64d" } */ ++/* { dg-skip-if "" { *-*-* } { "-O0" } } */ ++ ++extern void _dl_find_object_init (void); ++ ++void ++_dl_non_dynamic_init (void) ++{ ++ extern __typeof__ (_dl_find_object_init) _dl_find_object_init __attribute__ ((weak)); ++ (_dl_find_object_init != ((void *) 0) ? _dl_find_object_init () : (void)0); ++} ++ ++/* { dg-final { scan-assembler-times "mv\tt2" 1 } } */ +-- +2.47.3 + diff --git a/1074-RISC-V-Add-.note.gnu.property-for-ZICFILP-and-ZICFIS.patch b/1074-RISC-V-Add-.note.gnu.property-for-ZICFILP-and-ZICFIS.patch new file mode 100644 index 0000000..9f830a2 --- /dev/null +++ b/1074-RISC-V-Add-.note.gnu.property-for-ZICFILP-and-ZICFIS.patch @@ -0,0 +1,249 @@ +From 71402c67d97c96990fc58eb22ea7e18bbc9d78e7 Mon Sep 17 00:00:00 2001 +From: Monk Chiang +Date: Fri, 22 Mar 2024 21:10:07 +0800 +Subject: [PATCH 1074/1087] RISC-V: Add .note.gnu.property for ZICFILP and + ZICFISS ISA extension + +commit 2b3efe793e9ecf0f98da1daa85a091e931b4ca04 upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +gcc/ChangeLog: + * config/riscv/riscv.cc + (riscv_file_end): Add .note.gnu.property. + +libgcc/ChangeLog: + * config/riscv/crti.S: Add lpad instructions. + * config/riscv/crtn.S: Likewise. + * config/riscv/save-restore.S: Likewise. + * config/riscv/riscv-asm.h: Add GNU_PROPERTY for ZICFILP, + ZICFISS. + +Co-Developed-by: Jesse Huang +--- + gcc/config/riscv/riscv.cc | 52 +++++++++++++++++++++- + libgcc/config/riscv/crti.S | 2 + + libgcc/config/riscv/crtn.S | 2 + + libgcc/config/riscv/riscv-asm.h | 69 +++++++++++++++++++++++++++++- + libgcc/config/riscv/save-restore.S | 5 +++ + 5 files changed, 128 insertions(+), 2 deletions(-) + +diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc +index 090df379de6..d2b924b3b81 100644 +--- a/gcc/config/riscv/riscv.cc ++++ b/gcc/config/riscv/riscv.cc +@@ -9340,6 +9340,56 @@ riscv_file_start (void) + riscv_emit_attribute (); + } + ++void ++riscv_file_end () ++{ ++ file_end_indicate_exec_stack (); ++ long GNU_PROPERTY_RISCV_FEATURE_1_AND = 0; ++ unsigned long feature_1_and = 0; ++ ++ if (TARGET_ZICFISS) ++ feature_1_and |= 0x1 << 0; ++ ++ if (TARGET_ZICFILP) ++ feature_1_and |= 0x1 << 1; ++ ++ if (feature_1_and) ++ { ++ /* Generate .note.gnu.property section. */ ++ switch_to_section (get_section (".note.gnu.property", ++ SECTION_NOTYPE, NULL)); ++ ++ /* The program property descriptor is aligned to 4 bytes in 32-bit ++ objects and 8 bytes in 64-bit objects. */ ++ unsigned p2align = TARGET_64BIT ? 3 : 2; ++ ++ fprintf (asm_out_file, "\t.p2align\t%u\n", p2align); ++ /* name length. */ ++ fprintf (asm_out_file, "\t.long\t1f - 0f\n"); ++ /* data length. */ ++ fprintf (asm_out_file, "\t.long\t5f - 2f\n"); ++ /* note type. */ ++ fprintf (asm_out_file, "\t.long\t5\n"); ++ fprintf (asm_out_file, "0:\n"); ++ /* vendor name: "GNU". */ ++ fprintf (asm_out_file, "\t.asciz\t\"GNU\"\n"); ++ fprintf (asm_out_file, "1:\n"); ++ ++ /* pr_type. */ ++ fprintf (asm_out_file, "\t.p2align\t3\n"); ++ fprintf (asm_out_file, "2:\n"); ++ fprintf (asm_out_file, "\t.long\t0xc0000000\n"); ++ /* pr_datasz. */ ++ fprintf (asm_out_file, "\t.long\t4f - 3f\n"); ++ fprintf (asm_out_file, "3:\n"); ++ /* zicfiss, zicfilp. */ ++ fprintf (asm_out_file, "\t.long\t%x\n", feature_1_and); ++ fprintf (asm_out_file, "4:\n"); ++ fprintf (asm_out_file, "\t.p2align\t%u\n", p2align); ++ fprintf (asm_out_file, "5:\n"); ++ } ++} ++ + /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text + in order to avoid duplicating too much logic from elsewhere. */ + +@@ -11517,7 +11567,7 @@ bool need_shadow_stack_push_pop_p () + #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE + #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true + #undef TARGET_ASM_FILE_END +-#define TARGET_ASM_FILE_END file_end_indicate_exec_stack ++#define TARGET_ASM_FILE_END riscv_file_end + + #undef TARGET_EXPAND_BUILTIN_VA_START + #define TARGET_EXPAND_BUILTIN_VA_START riscv_va_start +diff --git a/libgcc/config/riscv/crti.S b/libgcc/config/riscv/crti.S +index 89bac706c63..3a67fd77156 100644 +--- a/libgcc/config/riscv/crti.S ++++ b/libgcc/config/riscv/crti.S +@@ -1 +1,3 @@ + /* crti.S is empty because .init_array/.fini_array are used exclusively. */ ++ ++#include "riscv-asm.h" +diff --git a/libgcc/config/riscv/crtn.S b/libgcc/config/riscv/crtn.S +index ca6ee7b6fba..cb80782bb55 100644 +--- a/libgcc/config/riscv/crtn.S ++++ b/libgcc/config/riscv/crtn.S +@@ -1 +1,3 @@ + /* crtn.S is empty because .init_array/.fini_array are used exclusively. */ ++ ++#include "riscv-asm.h" +diff --git a/libgcc/config/riscv/riscv-asm.h b/libgcc/config/riscv/riscv-asm.h +index f09b306bc06..933190089e2 100644 +--- a/libgcc/config/riscv/riscv-asm.h ++++ b/libgcc/config/riscv/riscv-asm.h +@@ -23,9 +23,11 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + #define FUNC_SIZE(X) .size X,.-X + + #define FUNC_BEGIN(X) \ ++ .align 2; \ + .globl X; \ + FUNC_TYPE (X); \ +-X: ++X: \ ++ LPAD + + #define FUNC_END(X) \ + FUNC_SIZE(X) +@@ -39,3 +41,68 @@ X: + #define HIDDEN_JUMPTARGET(X) CONCAT1(__hidden_, X) + #define HIDDEN_DEF(X) FUNC_ALIAS(HIDDEN_JUMPTARGET(X), X); \ + .hidden HIDDEN_JUMPTARGET(X) ++ ++/* GNU_PROPERTY_RISCV64_* macros from elf.h for use in asm code. */ ++#define FEATURE_1_AND 0xc0000000 ++#define FEATURE_1_FCFI 1 ++#define FEATURE_1_BCFI 2 ++ ++/* Add a NT_GNU_PROPERTY_TYPE_0 note. */ ++#if __riscv_xlen == 32 ++# define GNU_PROPERTY(type, value) \ ++ .section .note.gnu.property, "a"; \ ++ .p2align 2; \ ++ .word 4; \ ++ .word 12; \ ++ .word 5; \ ++ .asciz "GNU"; \ ++ .word type; \ ++ .word 4; \ ++ .word value; \ ++ .text ++#else ++# define GNU_PROPERTY(type, value) \ ++ .section .note.gnu.property, "a"; \ ++ .p2align 3; \ ++ .word 4; \ ++ .word 16; \ ++ .word 5; \ ++ .asciz "GNU"; \ ++ .word type; \ ++ .word 4; \ ++ .word value; \ ++ .word 0; \ ++ .text ++#endif ++ ++/* Add GNU property note with the supported features to all asm code ++ where sysdep.h is included. */ ++#undef __VALUE_FOR_FEATURE_1_AND ++#if defined (__riscv_zicfilp) || defined (__riscv_zicfiss) ++# if defined (__riscv_zicfilp) ++# if defined (__riscv_zicfiss) ++# define __VALUE_FOR_FEATURE_1_AND 0x3 ++# else ++# define __VALUE_FOR_FEATURE_1_AND 0x1 ++# endif ++# else ++# if defined (__riscv_zicfiss) ++# define __VALUE_FOR_FEATURE_1_AND 0x2 ++# else ++# error "What?" ++# endif ++# endif ++#endif ++ ++#if defined (__VALUE_FOR_FEATURE_1_AND) ++GNU_PROPERTY (FEATURE_1_AND, __VALUE_FOR_FEATURE_1_AND) ++#endif ++#undef __VALUE_FOR_FEATURE_1_AND ++ ++#ifdef __riscv_zicfilp ++# define SET_LPAD lui t2, 0 ++# define LPAD lpad 0 ++#else ++# define SET_LPAD ++# define LPAD ++#endif +diff --git a/libgcc/config/riscv/save-restore.S b/libgcc/config/riscv/save-restore.S +index 9bf42d111bc..850178034d8 100644 +--- a/libgcc/config/riscv/save-restore.S ++++ b/libgcc/config/riscv/save-restore.S +@@ -137,6 +137,7 @@ FUNC_BEGIN (__riscv_save_2) + # CFA info is not correct in next 2 instruction since t1's + # value is depend on how may register really save. + add sp, sp, t1 ++ SET_LPAD + jr t0 + .cfi_endproc + FUNC_END (__riscv_save_12) +@@ -162,6 +163,7 @@ FUNC_BEGIN (__riscv_save_0) + .cfi_offset 8, -16 + sd ra, 8(sp) + .cfi_offset 1, -8 ++ SET_LPAD + jr t0 + .cfi_endproc + FUNC_END (__riscv_save_1) +@@ -310,6 +312,7 @@ FUNC_BEGIN(__riscv_save_0) + .cfi_offset 8, -8 + sw ra, 8(sp) + .cfi_offset 1, 0 ++ SET_LPAD + jr t0 + .cfi_endproc + FUNC_END(__riscv_save_2) +@@ -399,6 +402,7 @@ FUNC_BEGIN (__riscv_save_4) + # CFA info is not correct in next 2 instruction since t1's + # value is depend on how may register really save. + sub sp, sp, t1 ++ SET_LPAD + jr t0 + .cfi_endproc + FUNC_END (__riscv_save_12) +@@ -427,6 +431,7 @@ FUNC_BEGIN (__riscv_save_0) + .cfi_offset 8, -8 + sw ra, 12(sp) + .cfi_offset 1, -4 ++ SET_LPAD + jr t0 + .cfi_endproc + FUNC_END (__riscv_save_3) +-- +2.47.3 + diff --git a/1075-RISC-V-Add-fcf-protection-full-branch-return-to-enab.patch b/1075-RISC-V-Add-fcf-protection-full-branch-return-to-enab.patch new file mode 100644 index 0000000..73bcea8 --- /dev/null +++ b/1075-RISC-V-Add-fcf-protection-full-branch-return-to-enab.patch @@ -0,0 +1,414 @@ +From db5fdc952a17d533eba9a9bcdd1a7973c8184a6e Mon Sep 17 00:00:00 2001 +From: Monk Chiang +Date: Fri, 15 Nov 2024 18:18:36 +0800 +Subject: [PATCH 1075/1087] RISC-V: Add -fcf-protection=[full|branch|return] to + enable zicfiss, zicfilp. + +commit upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +gcc/ChangeLog: + * config/riscv/riscv.cc + (is_zicfilp_p): New function. + (is_zicfiss_p): New function. + * config/riscv/riscv-zicfilp.cc: Update. + * config/riscv/riscv.h: Update. + * config/riscv/riscv.md: Update. + * config/riscv/riscv-c.cc: Add CFI predefine marco. + +gcc/testsuite/ChangeLog: + * c-c++-common/fcf-protection-1.c: Update. + * c-c++-common/fcf-protection-2.c: Update. + * c-c++-common/fcf-protection-3.c: Update. + * c-c++-common/fcf-protection-4.c: Update. + * c-c++-common/fcf-protection-5.c: Update. + * c-c++-common/fcf-protection-6.c: Update. + * c-c++-common/fcf-protection-7.c: Update. + * gcc.target/riscv/ssp-1.c: Update. + * gcc.target/riscv/ssp-2.c: Update. + * gcc.target/riscv/zicfilp-call.c: Update. + * gcc.target/riscv/interrupt-no-lpad.c: Update. +--- + gcc/config/riscv/riscv-c.cc | 9 ++++ + gcc/config/riscv/riscv-zicfilp.cc | 2 +- + gcc/config/riscv/riscv.cc | 52 +++++++++++++++---- + gcc/config/riscv/riscv.h | 8 +-- + gcc/config/riscv/riscv.md | 10 ++-- + gcc/testsuite/c-c++-common/fcf-protection-1.c | 1 + + gcc/testsuite/c-c++-common/fcf-protection-2.c | 1 + + gcc/testsuite/c-c++-common/fcf-protection-3.c | 1 + + gcc/testsuite/c-c++-common/fcf-protection-4.c | 1 + + gcc/testsuite/c-c++-common/fcf-protection-5.c | 1 + + gcc/testsuite/c-c++-common/fcf-protection-6.c | 1 + + gcc/testsuite/c-c++-common/fcf-protection-7.c | 1 + + .../gcc.target/riscv/interrupt-no-lpad.c | 2 +- + gcc/testsuite/gcc.target/riscv/ssp-1.c | 2 +- + gcc/testsuite/gcc.target/riscv/ssp-2.c | 2 +- + gcc/testsuite/gcc.target/riscv/zicfilp-call.c | 2 +- + 16 files changed, 72 insertions(+), 24 deletions(-) + +diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc +index c59f408d3a8..52b92b6ad14 100644 +--- a/gcc/config/riscv/riscv-c.cc ++++ b/gcc/config/riscv/riscv-c.cc +@@ -223,6 +223,15 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile) + /* Define architecture extension test macros. */ + builtin_define_with_int_value ("__riscv_arch_test", 1); + ++ if (TARGET_ZICFISS && ((flag_cf_protection & CF_RETURN) == CF_RETURN)) ++ builtin_define ("__riscv_shadow_stack"); ++ ++ if (TARGET_ZICFILP && ((flag_cf_protection & CF_BRANCH) == CF_BRANCH)) ++ { ++ builtin_define ("__riscv_landing_pad"); ++ builtin_define ("__riscv_landing_pad_unlabeled"); ++ } ++ + const riscv_subset_list *subset_list = riscv_cmdline_subset_list (); + if (!subset_list) + return; +diff --git a/gcc/config/riscv/riscv-zicfilp.cc b/gcc/config/riscv/riscv-zicfilp.cc +index 42b129920b3..834d6e5c778 100644 +--- a/gcc/config/riscv/riscv-zicfilp.cc ++++ b/gcc/config/riscv/riscv-zicfilp.cc +@@ -150,7 +150,7 @@ public: + /* opt_pass methods: */ + virtual bool gate (function *) + { +- return TARGET_ZICFILP; ++ return is_zicfilp_p (); + } + + virtual unsigned int execute (function *) +diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc +index d2b924b3b81..4f75c49ccd9 100644 +--- a/gcc/config/riscv/riscv.cc ++++ b/gcc/config/riscv/riscv.cc +@@ -6064,7 +6064,7 @@ riscv_legitimize_call_address (rtx addr) + rtx reg = RISCV_CALL_ADDRESS_TEMP (Pmode); + riscv_emit_move (reg, addr); + +- if (TARGET_ZICFILP) ++ if (is_zicfilp_p ()) + { + rtx sw_guarded = RISCV_CALL_ADDRESS_LPAD (Pmode); + emit_insn (gen_set_guarded (Pmode, reg)); +@@ -6074,7 +6074,7 @@ riscv_legitimize_call_address (rtx addr) + return reg; + } + +- if (TARGET_ZICFILP && REG_P (addr)) ++ if (is_zicfilp_p () && REG_P (addr)) + emit_insn (gen_set_lpl (Pmode, const0_rtx)); + + return addr; +@@ -6864,7 +6864,7 @@ riscv_save_reg_p (unsigned int regno) + if (regno == GP_REGNUM || regno == THREAD_POINTER_REGNUM) + return false; + +- if (regno == RETURN_ADDR_REGNUM && TARGET_ZICFISS) ++ if (regno == RETURN_ADDR_REGNUM && is_zicfiss_p ()) + return true; + + /* We must save every register used in this function. If this is not a +@@ -9347,10 +9347,10 @@ riscv_file_end () + long GNU_PROPERTY_RISCV_FEATURE_1_AND = 0; + unsigned long feature_1_and = 0; + +- if (TARGET_ZICFISS) ++ if (is_zicfilp_p ()) + feature_1_and |= 0x1 << 0; + +- if (TARGET_ZICFILP) ++ if (is_zicfiss_p ()) + feature_1_and |= 0x1 << 1; + + if (feature_1_and) +@@ -9410,7 +9410,7 @@ riscv_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, + /* Mark the end of the (empty) prologue. */ + emit_note (NOTE_INSN_PROLOGUE_END); + +- if (TARGET_ZICFILP) ++ if (is_zicfilp_p ()) + emit_insn(gen_lpad (const0_rtx)); + + /* Determine if we can use a sibcall to call FUNCTION directly. */ +@@ -9622,6 +9622,20 @@ riscv_override_options_internal (struct gcc_options *opts) + + /* Convert -march and -mrvv-vector-bits to a chunks count. */ + riscv_vector_chunks = riscv_convert_vector_chunks (opts); ++ ++ if (opts->x_flag_cf_protection != CF_NONE) ++ { ++ if ((opts->x_flag_cf_protection & CF_RETURN) == CF_RETURN ++ && !TARGET_ZICFISS) ++ error ("%<-fcf-protection%> is not compatible with this target"); ++ ++ if ((opts->x_flag_cf_protection & CF_BRANCH) == CF_BRANCH ++ && !TARGET_ZICFILP) ++ error ("%<-fcf-protection%> is not compatible with this target"); ++ ++ opts->x_flag_cf_protection ++ = (cf_protection_level) (opts->x_flag_cf_protection | CF_SET); ++ } + } + + /* Implement TARGET_OPTION_OVERRIDE. */ +@@ -9888,7 +9902,7 @@ riscv_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) + + /* Work out the offsets of the pointers from the start of the + trampoline code. */ +- if (!TARGET_ZICFILP) ++ if (!is_zicfilp_p ()) + gcc_assert (ARRAY_SIZE (trampoline) * 4 == TRAMPOLINE_CODE_SIZE); + else + gcc_assert (ARRAY_SIZE (trampoline_cfi) * 4 == TRAMPOLINE_CODE_SIZE); +@@ -9916,7 +9930,7 @@ riscv_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) + unsigned insn_count = 0; + + /* Insert lpad, if zicfilp is enabled. */ +- if (TARGET_ZICFILP) ++ if (is_zicfilp_p ()) + { + unsigned HOST_WIDE_INT lpad_code; + lpad_code = OPCODE_AUIPC | (0 << SHIFT_RD) | (lp_value << IMM_BITS); +@@ -9978,7 +9992,7 @@ riscv_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) + insn_count++; + + /* For zicfilp only, insert lui t2, 1, because use jr t0. */ +- if (TARGET_ZICFILP) ++ if (is_zicfilp_p ()) + { + unsigned HOST_WIDE_INT set_lpl_code; + set_lpl_code = OPCODE_LUI +@@ -10008,7 +10022,7 @@ riscv_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) + static_chain_offset = TRAMPOLINE_CODE_SIZE; + target_function_offset = static_chain_offset + GET_MODE_SIZE (ptr_mode); + +- if (!TARGET_ZICFILP) ++ if (!is_zicfilp_p ()) + { + /* auipc t2, 0 + l[wd] t0, (target_function_offset)(t2) +@@ -11502,9 +11516,25 @@ riscv_get_raw_result_mode (int regno) + return default_get_reg_raw_mode (regno); + } + ++bool is_zicfiss_p () ++{ ++ if (TARGET_ZICFISS && (flag_cf_protection & CF_RETURN)) ++ return true; ++ ++ return false; ++} ++ ++bool is_zicfilp_p () ++{ ++ if (TARGET_ZICFILP && (flag_cf_protection & CF_BRANCH)) ++ return true; ++ ++ return false; ++} ++ + bool need_shadow_stack_push_pop_p () + { +- return TARGET_ZICFISS && riscv_save_return_addr_reg_p (); ++ return is_zicfiss_p () && riscv_save_return_addr_reg_p (); + } + + /* Initialize the GCC target structure. */ +diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h +index faa01d27c71..9f0fe70d5f0 100644 +--- a/gcc/config/riscv/riscv.h ++++ b/gcc/config/riscv/riscv.h +@@ -197,7 +197,7 @@ ASM_MISA_SPEC + + /* Allocation boundary (in *bits*) for the code of a function. */ + #define FUNCTION_BOUNDARY \ +- (((TARGET_RVC || TARGET_ZCA) && !TARGET_ZICFILP) ? 16 : 32) ++ (((TARGET_RVC || TARGET_ZCA) && !is_zicfilp_p ()) ? 16 : 32) + + /* The smallest supported stack boundary the calling convention supports. */ + #define STACK_BOUNDARY \ +@@ -421,7 +421,7 @@ ASM_MISA_SPEC + + /* Register in which static-chain is passed to a function. */ + #define STATIC_CHAIN_REGNUM \ +- ((TARGET_ZICFILP) ? (GP_TEMP_FIRST + 23) : (GP_TEMP_FIRST + 2)) ++ ((is_zicfilp_p ()) ? (GP_TEMP_FIRST + 23) : (GP_TEMP_FIRST + 2)) + + /* Registers used as temporaries in prologue/epilogue code. + +@@ -788,7 +788,7 @@ extern enum riscv_cc get_riscv_cc (const rtx use); + + /* Trampolines are a block of code followed by two pointers. */ + +-#define TRAMPOLINE_CODE_SIZE ((TARGET_ZICFILP) ? 24 : 16) ++#define TRAMPOLINE_CODE_SIZE ((is_zicfilp_p ()) ? 24 : 16) + + #define TRAMPOLINE_SIZE \ + ((Pmode == SImode) \ +@@ -1159,6 +1159,8 @@ extern poly_int64 riscv_v_adjust_nunits (enum machine_mode, int); + extern poly_int64 riscv_v_adjust_nunits (machine_mode, bool, int, int); + extern poly_int64 riscv_v_adjust_precision (enum machine_mode, int); + extern poly_int64 riscv_v_adjust_bytesize (enum machine_mode, int); ++extern bool is_zicfiss_p (); ++extern bool is_zicfilp_p (); + extern bool need_shadow_stack_push_pop_p (); + /* The number of bits and bytes in a RVV vector. */ + #define BITS_PER_RISCV_VECTOR (poly_uint16 (riscv_vector_chunks * riscv_bytes_per_vector_chunk * 8)) +diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md +index ea016554b4d..890312f4a80 100644 +--- a/gcc/config/riscv/riscv.md ++++ b/gcc/config/riscv/riscv.md +@@ -3448,11 +3448,11 @@ + [(set (pc) (match_operand 0 "register_operand"))] + "" + { +- if (TARGET_ZICFILP) ++ if (is_zicfilp_p ()) + emit_insn (gen_set_lpl (Pmode, const0_rtx)); + + operands[0] = force_reg (Pmode, operands[0]); +- if (TARGET_ZICFILP) ++ if (is_zicfilp_p ()) + emit_use (gen_rtx_REG (Pmode, T2_REGNUM)); + + if (Pmode == SImode) +@@ -3480,7 +3480,7 @@ + gen_rtx_LABEL_REF (Pmode, operands[1]), + NULL_RTX, 0, OPTAB_DIRECT); + +- if (TARGET_ZICFILP) ++ if (is_zicfilp_p ()) + { + rtx t2 = RISCV_CALL_ADDRESS_LPAD (GET_MODE (operands[0])); + emit_move_insn (t2, operands[0]); +@@ -3503,7 +3503,7 @@ + (define_insn "tablejump" + [(set (pc) (match_operand:GPR 0 "register_operand" "l")) + (use (label_ref (match_operand 1 "" "")))] +- "!TARGET_ZICFILP" ++ "!is_zicfilp_p ()" + "jr\t%0" + [(set_attr "type" "jalr") + (set_attr "mode" "none")]) +@@ -3511,7 +3511,7 @@ + (define_insn "tablejump_cfi" + [(set (pc) (reg:GPR T2_REGNUM)) + (use (label_ref (match_operand 0 "")))] +- "TARGET_ZICFILP" ++ "is_zicfilp_p ()" + "jr\tt2" + [(set_attr "type" "jalr") + (set_attr "mode" "none")]) +diff --git a/gcc/testsuite/c-c++-common/fcf-protection-1.c b/gcc/testsuite/c-c++-common/fcf-protection-1.c +index f59a8fbdfdc..cc30c921a16 100644 +--- a/gcc/testsuite/c-c++-common/fcf-protection-1.c ++++ b/gcc/testsuite/c-c++-common/fcf-protection-1.c +@@ -1,3 +1,4 @@ + /* { dg-do compile } */ + /* { dg-options "-fcf-protection=full" } */ ++/* { dg-skip-if "" { "riscv*-*-*" } } */ + /* { dg-error "'-fcf-protection=full' is not supported for this target" "" { target { ! "i?86-*-* x86_64-*-*" } } 0 } */ +diff --git a/gcc/testsuite/c-c++-common/fcf-protection-2.c b/gcc/testsuite/c-c++-common/fcf-protection-2.c +index 61059725af6..e318989f290 100644 +--- a/gcc/testsuite/c-c++-common/fcf-protection-2.c ++++ b/gcc/testsuite/c-c++-common/fcf-protection-2.c +@@ -1,3 +1,4 @@ + /* { dg-do compile } */ + /* { dg-options "-fcf-protection=branch" } */ ++/* { dg-skip-if "" { "riscv*-*-*" } } */ + /* { dg-error "'-fcf-protection=branch' is not supported for this target" "" { target { ! "i?86-*-* x86_64-*-*" } } 0 } */ +diff --git a/gcc/testsuite/c-c++-common/fcf-protection-3.c b/gcc/testsuite/c-c++-common/fcf-protection-3.c +index 257e944c4a6..dd60017dde0 100644 +--- a/gcc/testsuite/c-c++-common/fcf-protection-3.c ++++ b/gcc/testsuite/c-c++-common/fcf-protection-3.c +@@ -1,3 +1,4 @@ + /* { dg-do compile } */ + /* { dg-options "-fcf-protection=return" } */ ++/* { dg-skip-if "" { "riscv*-*-*" } } */ + /* { dg-error "'-fcf-protection=return' is not supported for this target" "" { target { ! "i?86-*-* x86_64-*-*" } } 0 } */ +diff --git a/gcc/testsuite/c-c++-common/fcf-protection-4.c b/gcc/testsuite/c-c++-common/fcf-protection-4.c +index af4fc0b2812..2bde6e1e767 100644 +--- a/gcc/testsuite/c-c++-common/fcf-protection-4.c ++++ b/gcc/testsuite/c-c++-common/fcf-protection-4.c +@@ -1,2 +1,3 @@ + /* { dg-do compile } */ ++/* { dg-skip-if "" { "riscv*-*-*" } } */ + /* { dg-options "-fcf-protection=none" } */ +diff --git a/gcc/testsuite/c-c++-common/fcf-protection-5.c b/gcc/testsuite/c-c++-common/fcf-protection-5.c +index dc317f84b07..8c675c5f483 100644 +--- a/gcc/testsuite/c-c++-common/fcf-protection-5.c ++++ b/gcc/testsuite/c-c++-common/fcf-protection-5.c +@@ -1,3 +1,4 @@ + /* { dg-do compile } */ + /* { dg-options "-fcf-protection" } */ ++/* { dg-skip-if "" { "riscv*-*-*" } } */ + /* { dg-error "'-fcf-protection=full' is not supported for this target" "" { target { ! "i?86-*-* x86_64-*-*" } } 0 } */ +diff --git a/gcc/testsuite/c-c++-common/fcf-protection-6.c b/gcc/testsuite/c-c++-common/fcf-protection-6.c +index 61059725af6..e318989f290 100644 +--- a/gcc/testsuite/c-c++-common/fcf-protection-6.c ++++ b/gcc/testsuite/c-c++-common/fcf-protection-6.c +@@ -1,3 +1,4 @@ + /* { dg-do compile } */ + /* { dg-options "-fcf-protection=branch" } */ ++/* { dg-skip-if "" { "riscv*-*-*" } } */ + /* { dg-error "'-fcf-protection=branch' is not supported for this target" "" { target { ! "i?86-*-* x86_64-*-*" } } 0 } */ +diff --git a/gcc/testsuite/c-c++-common/fcf-protection-7.c b/gcc/testsuite/c-c++-common/fcf-protection-7.c +index 257e944c4a6..dd60017dde0 100644 +--- a/gcc/testsuite/c-c++-common/fcf-protection-7.c ++++ b/gcc/testsuite/c-c++-common/fcf-protection-7.c +@@ -1,3 +1,4 @@ + /* { dg-do compile } */ + /* { dg-options "-fcf-protection=return" } */ ++/* { dg-skip-if "" { "riscv*-*-*" } } */ + /* { dg-error "'-fcf-protection=return' is not supported for this target" "" { target { ! "i?86-*-* x86_64-*-*" } } 0 } */ +diff --git a/gcc/testsuite/gcc.target/riscv/interrupt-no-lpad.c b/gcc/testsuite/gcc.target/riscv/interrupt-no-lpad.c +index ff512b98c61..1290b373f08 100644 +--- a/gcc/testsuite/gcc.target/riscv/interrupt-no-lpad.c ++++ b/gcc/testsuite/gcc.target/riscv/interrupt-no-lpad.c +@@ -1,5 +1,5 @@ + /* { dg-do compile { target { riscv64*-*-* } } } */ +-/* { dg-options "-march=rv64gc_zicfilp -mabi=lp64d" } */ ++/* { dg-options "-march=rv64gc_zicfilp -mabi=lp64d -fcf-protection=branch" } */ + void __attribute__ ((interrupt)) + foo (void) + { +diff --git a/gcc/testsuite/gcc.target/riscv/ssp-1.c b/gcc/testsuite/gcc.target/riscv/ssp-1.c +index abf47ec6442..24e3010c3cc 100644 +--- a/gcc/testsuite/gcc.target/riscv/ssp-1.c ++++ b/gcc/testsuite/gcc.target/riscv/ssp-1.c +@@ -1,5 +1,5 @@ + /* { dg-do compile { target { riscv64*-*-* } } } */ +-/* { dg-options "-O2 -march=rv64gc_zicfiss -mabi=lp64d" } */ ++/* { dg-options "-O2 -march=rv64gc_zicfiss -mabi=lp64d -fcf-protection=return" } */ + /* { dg-skip-if "" { *-*-* } { "-O0" } } */ + struct ad { + void *ae; +diff --git a/gcc/testsuite/gcc.target/riscv/ssp-2.c b/gcc/testsuite/gcc.target/riscv/ssp-2.c +index 7c6098357e9..9d3d6b27038 100644 +--- a/gcc/testsuite/gcc.target/riscv/ssp-2.c ++++ b/gcc/testsuite/gcc.target/riscv/ssp-2.c +@@ -1,5 +1,5 @@ + /* { dg-do compile { target { riscv64*-*-* } } } */ +-/* { dg-options "-O0 -march=rv64gc_zicfiss -mabi=lp64d" } */ ++/* { dg-options "-O0 -march=rv64gc_zicfiss -mabi=lp64d -fcf-protection=return" } */ + + void __attribute__ ((interrupt)) + foo (void) +diff --git a/gcc/testsuite/gcc.target/riscv/zicfilp-call.c b/gcc/testsuite/gcc.target/riscv/zicfilp-call.c +index 75c8b32faa3..eb9e1468e7f 100644 +--- a/gcc/testsuite/gcc.target/riscv/zicfilp-call.c ++++ b/gcc/testsuite/gcc.target/riscv/zicfilp-call.c +@@ -1,5 +1,5 @@ + /* { dg-do compile { target { riscv64*-*-* } } } */ +-/* { dg-options "-O2 -fPIE -march=rv64gc_zicfilp -mabi=lp64d" } */ ++/* { dg-options "-O2 -fPIE -march=rv64gc_zicfilp -mabi=lp64d -fcf-protection=branch" } */ + /* { dg-skip-if "" { *-*-* } { "-O0" } } */ + + extern void _dl_find_object_init (void); +-- +2.47.3 + diff --git a/1076-RISC-V-Adjust-LMUL-when-using-maximum-SEW-PR117955.patch b/1076-RISC-V-Adjust-LMUL-when-using-maximum-SEW-PR117955.patch new file mode 100644 index 0000000..9fa1bc6 --- /dev/null +++ b/1076-RISC-V-Adjust-LMUL-when-using-maximum-SEW-PR117955.patch @@ -0,0 +1,264 @@ +From 876d0a0a78b8da4cd905ff44de99211d171ea550 Mon Sep 17 00:00:00 2001 +From: Robin Dapp +Date: Thu, 6 Mar 2025 10:28:44 +0800 +Subject: [PATCH 1076/1087] RISC-V: Adjust LMUL when using maximum SEW + [PR117955]. + +commit upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +Hi, + +when merging two vsetvls that both only demand "SEW >=3D ..." we +use their maximum SEW and keep the LMUL. That may lead to invalid +vector configurations like + e64, mf4. +As we make sure that the SEW requirements overlap we can use the SEW +and LMUL of the configuration with the larger SEW. + +Ma Jin already touched this merge rule some weeks ago and fixed the +ratio calculation (r15-6873). Calculating the ratio from an invalid +SEW/LMUL combination lead to an overflow in the ratio variable, though. +I'd argue the proper fix is to update SEW and LMUL, keeping the ratio +as before. This "breaks" bug-10.c but its check only checked for a +workaround anyway so I turned it into a run test. + +For V2, Ma Jin helped minify the PR's test and provided a larger test +case for bug-10. + +Regtested on rv64gcv_zvl512b. + +Regards + Robin + + PR target/117955 + +gcc/ChangeLog: + + * config/riscv/riscv-vsetvl.cc: Use LMUL/ratio from vsetvl with + larger SEW. + +gcc/testsuite/ChangeLog: + +* gcc.target/riscv/rvv/base/bug-10.c: Convert to run test. + * gcc.target/riscv/rvv/base/bug-10-2.c: New test. + * gcc.target/riscv/rvv/base/pr117955.c: New test. +--- + gcc/config/riscv/riscv-vsetvl.cc | 8 +- + .../gcc.target/riscv/rvv/base/bug-10-2.c | 92 +++++++++++++++++++ + .../gcc.target/riscv/rvv/base/bug-10.c | 46 ++++++++-- + .../gcc.target/riscv/rvv/base/pr117955.c | 26 ++++++ + 4 files changed, 159 insertions(+), 13 deletions(-) + create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/bug-10-2.c + create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr117955.c + +diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc +index 8d332309212..1be99c0c2b8 100644 +--- a/gcc/config/riscv/riscv-vsetvl.cc ++++ b/gcc/config/riscv/riscv-vsetvl.cc +@@ -1728,9 +1728,11 @@ private: + } + inline void use_max_sew (vsetvl_info &prev, const vsetvl_info &next) + { +- int max_sew = MAX (prev.get_sew (), next.get_sew ()); +- prev.set_sew (max_sew); +- prev.set_ratio (calculate_ratio (prev.get_sew (), prev.get_vlmul ())); ++ bool prev_sew_larger = prev.get_sew () >= next.get_sew (); ++ const vsetvl_info from = prev_sew_larger ? prev : next; ++ prev.set_sew (from.get_sew ()); ++ prev.set_vlmul (from.get_vlmul ()); ++ prev.set_ratio (from.get_ratio ()); + use_min_of_max_sew (prev, next); + } + inline void use_next_sew_lmul (vsetvl_info &prev, const vsetvl_info &next) +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-10-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-10-2.c +new file mode 100644 +index 00000000000..7e65cc66dd4 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-10-2.c +@@ -0,0 +1,92 @@ ++/* { dg-do compile { target { rv64 } } } */ ++/* { dg-require-effective-target rv64 } */ ++/* { dg-require-effective-target riscv_v } */ ++/* { dg-options " -march=rv64gcv_zvfh -mabi=lp64d -O2" } */ ++ ++#include ++ ++int8_t a[1]; ++uint16_t b[1]; ++float c[1], n[1]; ++uint16_t d[1]; ++uint8_t e[1]; ++uint16_t f[1]; ++_Float16 g[1], k[1], m[1], p[1]; ++uint16_t i[1]; ++int8_t j[1]; ++uint8_t o[1]; ++uint32_t l[1]; ++uint16_t q[1]; ++uint32_t r[1]; ++uint32_t s[1]; ++int16_t t[1]; ++int main() ++{ ++ int u = 25; ++ int8_t *v = a; ++ uint32_t *w; ++ uint16_t *aa = b; ++ float *ab = c, *as = n; ++ uint32_t *ad; ++ uint16_t *ah = f; ++ _Float16 *ai = g, *aj = k, *an = m, *au = p; ++ int32_t *ak; ++ int16_t *al; ++ uint16_t *am = i; ++ int8_t *ao = j; ++ uint8_t *ap = o; ++ uint32_t *aq = l; ++ uint16_t *ar = q; ++ uint32_t *at = r; ++ uint32_t *av = s; ++ int32_t *ax; ++ int16_t *ay = t; ++ for (size_t az; u; u -= az) ++ { ++ az = __riscv_vsetvl_e32m8(u); ++ vint8m2_t ba = __riscv_vle8_v_i8m2(v, az); ++ vbool4_t bb = __riscv_vmseq_vx_i8m2_b4(ba, 1, az); ++ vuint16m4_t bc = __riscv_vsll_vx_u16m4(__riscv_vid_v_u16m4(az), 2, az); ++ vuint32m8_t bd = __riscv_vsll_vx_u32m8(__riscv_vid_v_u32m8(az), 1, az); ++ vuint32m8_t be = __riscv_vluxei16_v_u32m8_m(bb, w, bc, az); ++ vuint16m4_t bf; ++ __riscv_vsuxei16_v_u32m8_m(bb, aq, bf, be, az); ++ vuint8m2_t bg = __riscv_vsll_vx_u8m2(__riscv_vid_v_u8m2(az), 1, az); ++ vuint16m4_t bh = __riscv_vloxei8_v_u16m4(aa, bg, az); ++ vfloat16m4_t bi; ++ vuint16m4_t bj = __riscv_vsll_vx_u16m4(__riscv_vid_v_u16m4(az), 1, az); ++ vint16m4_t bk = __riscv_vloxei32_v_i16m4_m(bb, al, bd, az); ++ __riscv_vsse16_v_u16m4(ar, 2, bh, az); ++ vuint16m4_t bl = __riscv_vloxei16_v_u16m4(d, bj, az); ++ vfloat16m4_t bm = __riscv_vle16_v_f16m4(ai, az); ++ vuint16m4_t bn = __riscv_vlse16_v_u16m4(ah, 2, az); ++ vint32m8_t bo = __riscv_vle32_v_i32m8_m(bb, ak, az); ++ vfloat16m1_t bp = __riscv_vle16_v_f16m1(aj, az); ++ vuint16m4_t bq = __riscv_vrgatherei16_vv_u16m4(bl, bn, az); ++ __riscv_vse16_v_u16m4(am, bq, az); ++ vfloat16m1_t br = __riscv_vfredusum_vs_f16m4_f16m1_m(bb, bm, bp, az); ++ vuint8m2_t bs; ++ vuint32m8_t bt; ++ __riscv_vse16_v_f16m1(an, br, az); ++ vfloat32m8_t bu = __riscv_vloxei8_v_f32m8(ab, bs, az); ++ __riscv_vse16_v_i16m4(ay, bk, az); ++ bi = __riscv_vfmv_s_f_f16m4(1, az); ++ __riscv_vse16_v_f16m4(au, bi, az); ++ vuint16m4_t bw = __riscv_vsll_vx_u16m4(__riscv_vid_v_u16m4(az), 0, az); ++ vuint32m8_t by = __riscv_vle32_v_u32m8_m(bb, ad, az); ++ bt = __riscv_vmv_s_x_u32m8(3090659, az); ++ __riscv_vse32_v_u32m8(at, bt, az); ++ vuint8m2_t bz = __riscv_vloxei16_v_u8m2(e, bw, az); ++ __riscv_vse32_v_u32m8(av, by, az); ++ vint8m2_t cd; ++ __riscv_vse8_v_i8m2(ao, cd, az); ++ __riscv_vsse32_v_i32m8_m(bb, ax, 4, bo, az); ++ __riscv_vse32_v_f32m8(as, bu, az); ++ vuint16m4_t cf; ++ __riscv_vsoxei16_v_u32m8(aq, cf, be, az); ++ vuint8m2_t cg = __riscv_vmulhu_vx_u8m2(bz, 0, az); ++ vuint32m8_t ch = __riscv_vsll_vx_u32m8(__riscv_vid_v_u32m8(az), 0, az); ++ __riscv_vsoxei32_v_u8m2(ap, ch, cg, az); ++ } ++ return 0; ++} +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-10.c b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-10.c +index af3a8610d63..c9974f25926 100644 +--- a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-10.c ++++ b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-10.c +@@ -1,14 +1,40 @@ + /* { dg-do compile { target { rv64 } } } */ +-/* { dg-options " -march=rv64gcv_zvfh -mabi=lp64d -O2 --param=vsetvl-strategy=optim -fno-schedule-insns -fno-schedule-insns2 -fno-schedule-fusion " } */ ++/* { dg-require-effective-target rv64 } */ ++/* { dg-require-effective-target riscv_v } */ ++ /* { dg-options " -march=rv64gcv_zvfh -mabi=lp64d -O2 --param=vsetvl-strategy=optim -fno-schedule-insns -fno-schedule-insns2 -fno-schedule-fusion " } */ ++ ++ #include ++ ++ void ++__attribute__ ((noipa)) ++foo (vfloat16m4_t *v1, vuint32m8_t *v2, vuint8m2_t *v3, size_t vl) ++ { ++ *v1 = __riscv_vfmv_s_f_f16m4 (1, vl); ++ *v2 = __riscv_vmv_s_x_u32m8 (2963090659u, vl); ++ *v3 = __riscv_vsll_vx_u8m2 (__riscv_vid_v_u8m2 (vl), 2, vl); ++ } + +-#include +- +-void +-foo (uint8_t *ptr, vfloat16m4_t *v1, vuint32m8_t *v2, vuint8m2_t *v3, size_t vl) ++int ++main () + { +- *v1 = __riscv_vfmv_s_f_f16m4 (1, vl); +- *v2 = __riscv_vmv_s_x_u32m8 (2963090659u, vl); +- *v3 = __riscv_vsll_vx_u8m2 (__riscv_vid_v_u8m2 (vl), 2, vl); +-} ++ vfloat16m4_t v1; ++ vuint32m8_t v2; ++ vuint8m2_t v3; ++ int vl = 4; ++ foo (&v1, &v2, &v3, vl); ++ ++ _Float16 val1 = ((_Float16 *)&v1)[0]; ++ if (val1 - 1.0000f > 0.00001f) ++ __builtin_abort (); ++ ++ uint32_t val2 = ((uint32_t *)&v2)[0]; ++ if (val2 != 2963090659u) ++ __builtin_abort (); + +-/* { dg-final { scan-assembler-not {vsetvli.*zero,zero} } }*/ ++ for (int i = 0; i < vl; i++) ++ { ++ uint8_t val = ((uint8_t *)&v3)[i]; ++ if (val != i << 2) ++ __builtin_abort (); ++ } ++} +\ No newline at end of file +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr117955.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr117955.c +new file mode 100644 +index 00000000000..81e3a6ed8eb +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr117955.c +@@ -0,0 +1,26 @@ ++/* { dg-do compile { target { rv64 } } } */ ++/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3" } */ ++ ++#include ++ ++_Float16 a (uint64_t); ++int8_t b () { ++ int c = 100; ++ double *d; ++ _Float16 *e; ++ for (size_t f;; c -= f) ++ { ++ f = c; ++ __riscv_vsll_vx_u8mf8 (__riscv_vid_v_u8mf8 (f), 2, f); ++ vfloat16mf4_t g; ++ a (1); ++ g = __riscv_vfmv_s_f_f16mf4 (2, f); ++ vfloat64m1_t i = __riscv_vfmv_s_f_f64m1 (30491, f); ++ vuint16mf4_t j; ++ __riscv_vsoxei16_v_f16mf4 (e, j, g, f); ++ vuint8mf8_t k = __riscv_vsll_vx_u8mf8 (__riscv_vid_v_u8mf8 (f), 3, f); ++ __riscv_vsoxei8_v_f64m1 (d, k, i, f); ++ } ++} ++ ++/* { dg-final { scan-assembler-not "e64,mf4" } } */ +-- +2.47.3 + diff --git a/1077-RISC-V-Eliminate-latter-vsetvl-when-fused.patch b/1077-RISC-V-Eliminate-latter-vsetvl-when-fused.patch new file mode 100644 index 0000000..344da08 --- /dev/null +++ b/1077-RISC-V-Eliminate-latter-vsetvl-when-fused.patch @@ -0,0 +1,82 @@ +From 356d962f0bec79d472a3854871588bd2e17f9259 Mon Sep 17 00:00:00 2001 +From: Bohan Lei +Date: Thu, 12 Sep 2024 10:28:03 +0800 +Subject: [PATCH 1077/1087] RISC-V: Eliminate latter vsetvl when fused + +commit 3f212eabbba3edc1827d6da53cf6d5a64c6524f0 upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +Hi all, + +A simple assembly check has been added in this version. Previous version: +https://gcc.gnu.org/pipermail/gcc-patches/2024-September/662783.html + +Thanks, +Bohan + +------ + +The current vsetvl pass eliminates a vsetvl instruction when the previous +info is "available," but does not when "compatible." This can lead to not +only redundancy, but also incorrect behaviors when the previous info happens +to be compatible with a later vector instruction, which ends of using the +vsetvl info that should have been eliminated, as is shown in the testcase. +This patch eliminates the vsetvl when the previous info is "compatible." + +gcc/ChangeLog: + + * config/riscv/riscv-vsetvl.cc (pre_vsetvl::fuse_local_vsetvl_info): + Delete vsetvl insn when `prev_info` is compatible + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/rvv/vsetvl/vsetvl_bug-4.c: New test. +--- + gcc/config/riscv/riscv-vsetvl.cc | 3 +++ + .../riscv/rvv/vsetvl/vsetvl_bug-4.c | 19 +++++++++++++++++++ + 2 files changed, 22 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-4.c + +diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc +index 1be99c0c2b8..45bb658b1a3 100644 +--- a/gcc/config/riscv/riscv-vsetvl.cc ++++ b/gcc/config/riscv/riscv-vsetvl.cc +@@ -2819,6 +2819,9 @@ pre_vsetvl::fuse_local_vsetvl_info () + curr_info.dump (dump_file, " "); + } + m_dem.merge (prev_info, curr_info); ++ if (!curr_info.vl_used_by_non_rvv_insn_p () ++ && vsetvl_insn_p (curr_info.get_insn ()->rtl ())) ++ m_delete_list.safe_push (curr_info); + if (curr_info.get_read_vl_insn ()) + prev_info.set_read_vl_insn (curr_info.get_read_vl_insn ()); + if (dump_file && (dump_flags & TDF_DETAILS)) +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-4.c +new file mode 100644 +index 00000000000..04a8ff2945a +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-4.c +@@ -0,0 +1,19 @@ ++/* { dg-do compile } */ ++/* { dg-options "-march=rv64gcv -mabi=lp64d -O2 -fno-schedule-insns -fdump-rtl-vsetvl-details" } */ ++ ++#include ++ ++vuint16m1_t ++foo (vuint16m1_t a, vuint16m1_t b, size_t avl) ++{ ++ size_t vl; ++ vuint16m1_t ret; ++ uint16_t c = __riscv_vmv_x_s_u16m1_u16(a); ++ vl = __riscv_vsetvl_e8mf2 (avl); ++ ret = __riscv_vadd_vx_u16m1 (a, c, avl); ++ ret = __riscv_vadd_vv_u16m1 (ret, a, vl); ++ return ret; ++} ++ ++/* { dg-final { scan-rtl-dump "Eliminate insn" "vsetvl" } } */ ++/* { dg-final { scan-assembler-times {vsetvli} 2 } } */ +-- +2.47.3 + diff --git a/1078-RISC-V-Fix-ratio-in-vsetvl-fuse-rule-PR115703.patch b/1078-RISC-V-Fix-ratio-in-vsetvl-fuse-rule-PR115703.patch new file mode 100644 index 0000000..70561f2 --- /dev/null +++ b/1078-RISC-V-Fix-ratio-in-vsetvl-fuse-rule-PR115703.patch @@ -0,0 +1,176 @@ +From a5c094ec9bb6e432dd68084612c71664f3659cac Mon Sep 17 00:00:00 2001 +From: Robin Dapp +Date: Thu, 6 Feb 2025 14:43:17 +0100 +Subject: [PATCH 1078/1087] RISC-V: Fix ratio in vsetvl fuse rule [PR115703]. + +commit upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +In PR115703 we fuse two vsetvls: + + Fuse curr info since prev info compatible with it: + prev_info: VALID (insn 438, bb 2) + Demand fields: demand_ge_sew demand_non_zero_avl + SEW=32, VLMUL=m1, RATIO=32, MAX_SEW=64 + TAIL_POLICY=agnostic, MASK_POLICY=agnostic + AVL=(reg:DI 0 zero) + VL=(reg:DI 9 s1 [312]) + curr_info: VALID (insn 92, bb 20) + Demand fields: demand_ratio_and_ge_sew demand_avl + SEW=64, VLMUL=m1, RATIO=64, MAX_SEW=64 + TAIL_POLICY=agnostic, MASK_POLICY=agnostic + AVL=(const_int 4 [0x4]) + VL=(nil) + prev_info after fused: VALID (insn 438, bb 2) + Demand fields: demand_ratio_and_ge_sew demand_avl + SEW=64, VLMUL=mf2, RATIO=64, MAX_SEW=64 + TAIL_POLICY=agnostic, MASK_POLICY=agnostic + AVL=(const_int 4 [0x4]) + VL=(nil). + +The result is vsetvl zero, zero, e64, mf2, ta, ma. The previous vsetvl +set vl = 4 but here we wrongly set it to vl = 2. As all the following +vsetvls only ever change the ratio we never recover. + +The issue is quite difficult to trigger because we can often +deduce the value of d at runtime. Then very check for the value of +d will be optimized away. + +The last known bad commit is r15-3458-g5326306e7d9d36. With that commit +the output is wrong but -fno-schedule-insns makes it correct. From the +next commit on the issue is latent. I still added the PR's test as scan +and run check even if they don't trigger right now. Not sure if the +run test will ever fail but well. I verified that the +patch fixes the issue when applied on top of r15-3458-g5326306e7d9d36. + + PR target/115703 + +gcc/ChangeLog: + + * config/riscv/riscv-vsetvl.cc: Use max_sew for calculating the + new LMUL. + +gcc/testsuite/ChangeLog: + +* gcc.target/riscv/rvv/autovec/pr115703-run.c: New test. + * gcc.target/riscv/rvv/autovec/pr115703.c: New test. +--- + gcc/config/riscv/riscv-vsetvl.cc | 3 +- + .../riscv/rvv/autovec/pr115703-run.c | 44 +++++++++++++++++++ + .../gcc.target/riscv/rvv/autovec/pr115703.c | 38 ++++++++++++++++ + 3 files changed, 84 insertions(+), 1 deletion(-) + create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr115703-run.c + create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr115703.c + +diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc +index 45bb658b1a3..a1aa8e87f98 100644 +--- a/gcc/config/riscv/riscv-vsetvl.cc ++++ b/gcc/config/riscv/riscv-vsetvl.cc +@@ -1757,7 +1757,8 @@ private: + inline void use_max_sew_and_lmul_with_next_ratio (vsetvl_info &prev, + const vsetvl_info &next) + { +- prev.set_vlmul (calculate_vlmul (prev.get_sew (), next.get_ratio ())); ++ int max_sew = MAX (prev.get_sew (), next.get_sew ()); ++ prev.set_vlmul (calculate_vlmul (max_sew, next.get_ratio ())); + use_max_sew (prev, next); + prev.set_ratio (next.get_ratio ()); + } +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr115703-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr115703-run.c +new file mode 100644 +index 00000000000..0c2c3d7d4fc +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr115703-run.c +@@ -0,0 +1,44 @@ ++/* { dg-do run } */ ++/* { dg-require-effective-target rvv_zvl256b_ok } */ ++/* { dg-options "-O3 -march=rv64gcv_zvl256b -mabi=lp64d -fwhole-program -fwrapv" } */ ++ ++int a, i; ++unsigned long b; ++unsigned c, f; ++long long d = 1; ++short e, m; ++long g, h; ++ ++__attribute__ ((noipa)) ++void check (unsigned long long x) ++{ ++ if (x != 13667643351234938049ull) ++ __builtin_abort (); ++} ++ ++int main() { ++ for (int q = 0; q < 2; q += 1) { ++ for (short r = 0; r < 2; r += 1) ++ for (char s = 0; s < 6; s++) ++ for (short t = 0; t < 011; t += 12081 - 12080) ++ for (short u = 0; u < 11; u++) { ++ a = ({ a > 1 ? a : 1; }); ++ b = ({ b > 5 ? b : 5; }); ++ for (short j = 0; j < 2; j = 2080) ++ c = ({ c > 030 ? c : 030; }); ++ for (short k = 0; k < 2; k += 2080) ++ d *= 7; ++ e *= 10807; ++ f = ({ f > 3 ? f : 3; }); ++ } ++ for (int l = 0; l < 21; l += 1) ++ for (int n = 0; n < 16; n++) { ++ g = ({ m ? g : m; }); ++ for (char o = 0; o < 7; o += 1) ++ h *= 3; ++ i = ({ i < 0 ? i : 0; }); ++ } ++ } ++ ++ check (d); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr115703.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr115703.c +new file mode 100644 +index 00000000000..207ff3c86ec +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr115703.c +@@ -0,0 +1,38 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O3 -march=rv64gcv_zvl256b -mabi=lp64d -fwhole-program -fwrapv" } */ ++ ++int a, i; ++unsigned long b; ++unsigned c, f; ++long long d = 1; ++short e, m; ++long g, h; ++ ++int main() { ++ for (int q = 0; q < 2; q += 1) { ++ for (short r = 0; r < 2; r += 1) ++ for (char s = 0; s < 6; s++) ++ for (short t = 0; t < 011; t += 12081 - 12080) ++ for (short u = 0; u < 11; u++) { ++ a = ({ a > 1 ? a : 1; }); ++ b = ({ b > 5 ? b : 5; }); ++ for (short j = 0; j < 2; j = 2080) ++ c = ({ c > 030 ? c : 030; }); ++ for (short k = 0; k < 2; k += 2080) ++ d *= 7; ++ e *= 10807; ++ f = ({ f > 3 ? f : 3; }); ++ } ++ for (int l = 0; l < 21; l += 1) ++ for (int n = 0; n < 16; n++) { ++ g = ({ m ? g : m; }); ++ for (char o = 0; o < 7; o += 1) ++ h *= 3; ++ i = ({ i < 0 ? i : 0; }); ++ } ++ } ++ ++ __builtin_printf ("%llu\n", d); ++} ++ ++/* { dg-final { scan-assembler-not "vset.*e64,mf2" } } */ +-- +2.47.3 + diff --git a/1079-Drop-undesirable-two-instruction-macc-alternatives.patch b/1079-Drop-undesirable-two-instruction-macc-alternatives.patch new file mode 100644 index 0000000..011baa6 --- /dev/null +++ b/1079-Drop-undesirable-two-instruction-macc-alternatives.patch @@ -0,0 +1,640 @@ +From 3c0f36aea0158a8caafec4632417656b2c405c58 Mon Sep 17 00:00:00 2001 +From: Jeff Law +Date: Tue, 12 Nov 2024 07:05:02 -0700 +Subject: [PATCH 1079/1087] Drop undesirable two instruction macc alternatives + +commit 705a21035bddc856c1e434d5502f69758e82c7e9 upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +So I was looking at sub_dct a little while ago and was surprised to see +us emit two instructions out of a single pattern. We generally try to +avoid that -- it's not always possible, but as a general rule of thumb +it should be avoided. Specifically I saw: + +> vmv1r.v v4,v2 # 138 [c=4 l=4] *pred_mul_plusrvvm1hi_undef/5 +> vmacc.vv v4,v8,v1 + +When we emit multiple instructions out of a single pattern we can't +build a good schedule as we can't really describe the two instructions +well and we can't split them up -- they move as an atomic unit. + +These cases can also raise correctness issues if the pattern doesn't +properly account for both instructions in its length computation. + +Note the length, 4 bytes. So this is both a performance and latent +correctness issue. + +It appears that these alternatives are meant to deal with the case when +we have three source inputs and a non-matching output. The author did +put in "?" to slightly disparage these alternatives, but a "!" would +have been better. The best solution is to just remove those +alternatives and let the allocator manage the matching operand issue. + +That's precisely what this patch does. For the various integer +multiply-add/multiply-accumulate patterns we drop the alternatives which +don't require a match between the output and one of the inputs. + +That fixes the correctness issue and should shave a cycle or two off our +sub_dct code. Essentially the move bubbles up into an empty slot and we +can schedule around the vmacc sensibly. + +Interestingly enough this fixes a scan-assembler test in my tester for +both rv32 and rv64. + +> Tests that now work, but didn't before (10 tests): +> +> unix/-march=rv32gcv: gcc: gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c scan-assembler-times \\tvmacc\\.vv 8 +> unix/-march=rv32gcv: gcc: gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c scan-assembler-times \\tvmacc\\.vv 8 +> unix/-march=rv32gcv: gcc: gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c scan-assembler-times \\tvmacc\\.vv 8 +> unix/-march=rv32gcv: gcc: gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c scan-assembler-times \\tvmacc\\.vv 8 +> unix/-march=rv32gcv: gcc: gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c scan-assembler-times \\tvmacc\\.vv 8 +> unix/-march=rv32gcv: gcc: gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c scan-assembler-times \\tvmacc\\.vv 8 +> unix/-march=rv32gcv: gcc: gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c scan-assembler-times \\tvmacc\\.vv 8 +> unix/-march=rv32gcv: gcc: gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c scan-assembler-times \\tvmacc\\.vv 8 +> unix/-march=rv32gcv: gcc: gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c scan-assembler-times \\tvmacc\\.vv 8 +> unix/-march=rv32gcv: gcc: gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c scan-assembler-times \\tvmacc\\.vv 8 + +My BPI is already in a bootstrap test, so this patch won't hit the BPI +for bootstrapping until Wednesday, meaning no data until Thursday. Will +wait for the pre-commit tester though. + +gcc/ + * config/riscv/vector.md (pred_mul_plus_undef): Drop alternatives + where output doesn't have to match input. + (pred_madd, pred_macc): Likewise. + (pred_madd_scalar, pred_macc_scalar): Likewise. + (pred_madd_exended_scalar): Likewise. + (pred_macc_exended_scalar): Likewise. + (pred_minus_mul_undef): Likewise. + (pred_nmsub, pred_nmsac): Likewise. + (pred_nmsub_scalar, pred_nmsac_scalar): Likewise. + (pred_nmsub_exended_scalar): Likewise. + (pred_nmsac_exended_scalar): Likewise. +--- + gcc/config/riscv/vector.md | 310 +++++++++++++++++-------------------- + 1 file changed, 140 insertions(+), 170 deletions(-) + +diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md +index 49e68c990d3..d6af53766f4 100644 +--- a/gcc/config/riscv/vector.md ++++ b/gcc/config/riscv/vector.md +@@ -5541,56 +5541,52 @@ + }) + + (define_insn "*pred_mul_plus_undef" +- [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vd,?&vd, vr, vr,?&vr") ++ [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vd, vr, vr") + (if_then_else:V_VLSI + (unspec: +- [(match_operand: 1 "vector_mask_operand" " vm, vm, vm,Wc1,Wc1, Wc1") +- (match_operand 6 "vector_length_operand" "rvl,rvl, rvl,rvl,rvl, rvl") +- (match_operand 7 "const_int_operand" " i, i, i, i, i, i") +- (match_operand 8 "const_int_operand" " i, i, i, i, i, i") +- (match_operand 9 "const_int_operand" " i, i, i, i, i, i") ++ [(match_operand: 1 "vector_mask_operand" " vm, vm, Wc1,Wc1") ++ (match_operand 6 "vector_length_operand" " rK, rK, rK, rK") ++ (match_operand 7 "const_int_operand" " i, i, i, i") ++ (match_operand 8 "const_int_operand" " i, i, i, i") ++ (match_operand 9 "const_int_operand" " i, i, i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (plus:V_VLSI + (mult:V_VLSI +- (match_operand:V_VLSI 3 "register_operand" " 0, vr, vr, 0, vr, vr") +- (match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr, vr, vr")) +- (match_operand:V_VLSI 5 "register_operand" " vr, 0, vr, vr, 0, vr")) ++ (match_operand:V_VLSI 3 "register_operand" " 0, vr, 0, vr") ++ (match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr")) ++ (match_operand:V_VLSI 5 "register_operand" " vr, 0, vr, 0")) + (match_operand:V_VLSI 2 "vector_undef_operand")))] + "TARGET_VECTOR" + "@ + vmadd.vv\t%0,%4,%5%p1 + vmacc.vv\t%0,%3,%4%p1 +- vmv%m4r.v\t%0,%4\;vmacc.vv\t%0,%3,%4%p1 + vmadd.vv\t%0,%4,%5%p1 +- vmacc.vv\t%0,%3,%4%p1 +- vmv%m5r.v\t%0,%5\;vmacc.vv\t%0,%3,%4%p1" ++ vmacc.vv\t%0,%3,%4%p1" + [(set_attr "type" "vimuladd") + (set_attr "mode" "")]) + + (define_insn "*pred_madd" +- [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr") ++ [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vr") + (if_then_else:V_VLSI + (unspec: +- [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1, Wc1") +- (match_operand 5 "vector_length_operand" "rvl, rvl,rvl, rvl") +- (match_operand 6 "const_int_operand" " i, i, i, i") +- (match_operand 7 "const_int_operand" " i, i, i, i") +- (match_operand 8 "const_int_operand" " i, i, i, i") ++ [(match_operand: 1 "vector_mask_operand" " vm,Wc1") ++ (match_operand 5 "vector_length_operand" " rK, rK") ++ (match_operand 6 "const_int_operand" " i, i") ++ (match_operand 7 "const_int_operand" " i, i") ++ (match_operand 8 "const_int_operand" " i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (plus:V_VLSI + (mult:V_VLSI +- (match_operand:V_VLSI 2 "register_operand" " 0, vr, 0, vr") +- (match_operand:V_VLSI 3 "register_operand" " vr, vr, vr, vr")) +- (match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr")) ++ (match_operand:V_VLSI 2 "register_operand" " 0, 0") ++ (match_operand:V_VLSI 3 "register_operand" " vr, vr")) ++ (match_operand:V_VLSI 4 "register_operand" " vr, vr")) + (match_dup 2)))] + "TARGET_VECTOR" + "@ + vmadd.vv\t%0,%3,%4%p1 +- vmv%m2r.v\t%0,%2\;vmadd.vv\t%0,%3,%4%p1 +- vmadd.vv\t%0,%3,%4%p1 +- vmv%m2r.v\t%0,%2\;vmadd.vv\t%0,%3,%4%p1" ++ vmadd.vv\t%0,%3,%4%p1" + [(set_attr "type" "vimuladd") + (set_attr "mode" "") + (set_attr "merge_op_idx" "2") +@@ -5600,28 +5596,24 @@ + (set (attr "avl_type_idx") (const_int 8))]) + + (define_insn "*pred_macc" +- [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr") ++ [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vr") + (if_then_else:V_VLSI + (unspec: +- [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1, Wc1") +- (match_operand 5 "vector_length_operand" "rvl, rvl,rvl, rvl") +- (match_operand 6 "const_int_operand" " i, i, i, i") +- (match_operand 7 "const_int_operand" " i, i, i, i") +- (match_operand 8 "const_int_operand" " i, i, i, i") ++ [(match_operand: 1 "vector_mask_operand" " vm,Wc1") ++ (match_operand 5 "vector_length_operand" " rK, rK") ++ (match_operand 6 "const_int_operand" " i, i") ++ (match_operand 7 "const_int_operand" " i, i") ++ (match_operand 8 "const_int_operand" " i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (plus:V_VLSI + (mult:V_VLSI +- (match_operand:V_VLSI 2 "register_operand" " vr, vr, vr, vr") +- (match_operand:V_VLSI 3 "register_operand" " vr, vr, vr, vr")) +- (match_operand:V_VLSI 4 "register_operand" " 0, vr, 0, vr")) ++ (match_operand:V_VLSI 2 "register_operand" " vr, vr") ++ (match_operand:V_VLSI 3 "register_operand" " vr, vr")) ++ (match_operand:V_VLSI 4 "register_operand" " 0, 0")) + (match_dup 4)))] + "TARGET_VECTOR" +- "@ +- vmacc.vv\t%0,%2,%3%p1 +- vmv%m4r.v\t%0,%4;vmacc.vv\t%0,%2,%3%p1 +- vmacc.vv\t%0,%2,%3%p1 +- vmv%m4r.v\t%0,%4\;vmacc.vv\t%0,%2,%3%p1" ++ "vmacc.vv\t%0,%2,%3%p1" + [(set_attr "type" "vimuladd") + (set_attr "mode" "") + (set_attr "merge_op_idx" "4") +@@ -5652,29 +5644,27 @@ + {}) + + (define_insn "*pred_madd_scalar" +- [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr") ++ [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vr") + (if_then_else:V_VLSI + (unspec: +- [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1, Wc1") +- (match_operand 5 "vector_length_operand" "rvl, rvl,rvl, rvl") +- (match_operand 6 "const_int_operand" " i, i, i, i") +- (match_operand 7 "const_int_operand" " i, i, i, i") +- (match_operand 8 "const_int_operand" " i, i, i, i") ++ [(match_operand: 1 "vector_mask_operand" " vm,Wc1") ++ (match_operand 5 "vector_length_operand" " rK, rK") ++ (match_operand 6 "const_int_operand" " i, i") ++ (match_operand 7 "const_int_operand" " i, i") ++ (match_operand 8 "const_int_operand" " i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (plus:V_VLSI + (mult:V_VLSI + (vec_duplicate:V_VLSI +- (match_operand: 2 "reg_or_0_operand" " rJ, rJ, rJ, rJ")) +- (match_operand:V_VLSI 3 "register_operand" " 0, vr, 0, vr")) +- (match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr")) ++ (match_operand: 2 "reg_or_0_operand" " rJ, rJ")) ++ (match_operand:V_VLSI 3 "register_operand" " 0, 0")) ++ (match_operand:V_VLSI 4 "register_operand" " vr, vr")) + (match_dup 3)))] + "TARGET_VECTOR" + "@ + vmadd.vx\t%0,%z2,%4%p1 +- vmv%m3r.v\t%0,%3\;vmadd.vx\t%0,%z2,%4%p1 +- vmadd.vx\t%0,%z2,%4%p1 +- vmv%m3r.v\t%0,%3\;vmadd.vx\t%0,%z2,%4%p1" ++ vmadd.vx\t%0,%z2,%4%p1" + [(set_attr "type" "vimuladd") + (set_attr "mode" "") + (set_attr "merge_op_idx" "3") +@@ -5684,29 +5674,27 @@ + (set (attr "avl_type_idx") (const_int 8))]) + + (define_insn "*pred_macc_scalar" +- [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr") ++ [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vr") + (if_then_else:V_VLSI + (unspec: +- [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1, Wc1") +- (match_operand 5 "vector_length_operand" "rvl, rvl,rvl, rvl") +- (match_operand 6 "const_int_operand" " i, i, i, i") +- (match_operand 7 "const_int_operand" " i, i, i, i") +- (match_operand 8 "const_int_operand" " i, i, i, i") ++ [(match_operand: 1 "vector_mask_operand" " vm,Wc1") ++ (match_operand 5 "vector_length_operand" " rK, rK") ++ (match_operand 6 "const_int_operand" " i, i") ++ (match_operand 7 "const_int_operand" " i, i") ++ (match_operand 8 "const_int_operand" " i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (plus:V_VLSI + (mult:V_VLSI + (vec_duplicate:V_VLSI +- (match_operand: 2 "reg_or_0_operand" " rJ, rJ, rJ, rJ")) +- (match_operand:V_VLSI 3 "register_operand" " vr, vr, vr, vr")) +- (match_operand:V_VLSI 4 "register_operand" " 0, vr, 0, vr")) ++ (match_operand: 2 "reg_or_0_operand" " rJ, rJ")) ++ (match_operand:V_VLSI 3 "register_operand" " vr, vr")) ++ (match_operand:V_VLSI 4 "register_operand" " 0, 0")) + (match_dup 4)))] + "TARGET_VECTOR" + "@ + vmacc.vx\t%0,%z2,%3%p1 +- vmv%m4r.v\t%0,%4\;vmacc.vx\t%0,%z2,%3%p1 +- vmacc.vx\t%0,%z2,%3%p1 +- vmv%m4r.v\t%0,%4\;vmacc.vx\t%0,%z2,%3%p1" ++ vmacc.vx\t%0,%z2,%3%p1" + [(set_attr "type" "vimuladd") + (set_attr "mode" "") + (set_attr "merge_op_idx" "4") +@@ -5751,30 +5739,28 @@ + }) + + (define_insn "*pred_madd_extended_scalar" +- [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,?&vd, vr,?&vr") ++ [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd, vr") + (if_then_else:V_VLSI_D + (unspec: +- [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1, Wc1") +- (match_operand 5 "vector_length_operand" "rvl, rvl,rvl, rvl") +- (match_operand 6 "const_int_operand" " i, i, i, i") +- (match_operand 7 "const_int_operand" " i, i, i, i") +- (match_operand 8 "const_int_operand" " i, i, i, i") ++ [(match_operand: 1 "vector_mask_operand" " vm,Wc1") ++ (match_operand 5 "vector_length_operand" " rK, rK") ++ (match_operand 6 "const_int_operand" " i, i") ++ (match_operand 7 "const_int_operand" " i, i") ++ (match_operand 8 "const_int_operand" " i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (plus:V_VLSI_D + (mult:V_VLSI_D + (vec_duplicate:V_VLSI_D + (sign_extend: +- (match_operand: 2 "reg_or_0_operand" " rJ, rJ, rJ, rJ"))) +- (match_operand:V_VLSI_D 3 "register_operand" " 0, vr, 0, vr")) +- (match_operand:V_VLSI_D 4 "register_operand" " vr, vr, vr, vr")) ++ (match_operand: 2 "reg_or_0_operand" " rJ, rJ"))) ++ (match_operand:V_VLSI_D 3 "register_operand" " 0, 0")) ++ (match_operand:V_VLSI_D 4 "register_operand" " vr, vr")) + (match_dup 3)))] + "TARGET_VECTOR && !TARGET_64BIT" + "@ + vmadd.vx\t%0,%z2,%4%p1 +- vmv%m2r.v\t%0,%z2\;vmadd.vx\t%0,%z2,%4%p1 +- vmadd.vx\t%0,%z2,%4%p1 +- vmv%m2r.v\t%0,%z2\;vmadd.vx\t%0,%z2,%4%p1" ++ vmadd.vx\t%0,%z2,%4%p1" + [(set_attr "type" "vimuladd") + (set_attr "mode" "") + (set_attr "merge_op_idx" "3") +@@ -5784,30 +5770,28 @@ + (set (attr "avl_type_idx") (const_int 8))]) + + (define_insn "*pred_macc_extended_scalar" +- [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,?&vd, vr,?&vr") ++ [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd, vr") + (if_then_else:V_VLSI_D + (unspec: +- [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1, Wc1") +- (match_operand 5 "vector_length_operand" "rvl, rvl,rvl, rvl") +- (match_operand 6 "const_int_operand" " i, i, i, i") +- (match_operand 7 "const_int_operand" " i, i, i, i") +- (match_operand 8 "const_int_operand" " i, i, i, i") ++ [(match_operand: 1 "vector_mask_operand" " vm,Wc1") ++ (match_operand 5 "vector_length_operand" " rK, rK") ++ (match_operand 6 "const_int_operand" " i, i") ++ (match_operand 7 "const_int_operand" " i, i") ++ (match_operand 8 "const_int_operand" " i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (plus:V_VLSI_D + (mult:V_VLSI_D + (vec_duplicate:V_VLSI_D + (sign_extend: +- (match_operand: 2 "reg_or_0_operand" " rJ, rJ, rJ, rJ"))) +- (match_operand:V_VLSI_D 3 "register_operand" " vr, vr, vr, vr")) +- (match_operand:V_VLSI_D 4 "register_operand" " 0, vr, 0, vr")) ++ (match_operand: 2 "reg_or_0_operand" " rJ, rJ"))) ++ (match_operand:V_VLSI_D 3 "register_operand" " vr, vr")) ++ (match_operand:V_VLSI_D 4 "register_operand" " 0, 0")) + (match_dup 4)))] + "TARGET_VECTOR && !TARGET_64BIT" + "@ + vmacc.vx\t%0,%z2,%3%p1 +- vmv%m4r.v\t%0,%4\;vmacc.vx\t%0,%z2,%3%p1 +- vmacc.vx\t%0,%z2,%3%p1 +- vmv%m4r.v\t%0,%4\;vmacc.vx\t%0,%z2,%3%p1" ++ vmacc.vx\t%0,%z2,%3%p1" + [(set_attr "type" "vimuladd") + (set_attr "mode" "") + (set_attr "merge_op_idx" "4") +@@ -5839,56 +5823,52 @@ + }) + + (define_insn "*pred_minus_mul_undef" +- [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vd,?&vd, vr, vr,?&vr") ++ [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vd, vr, vr") + (if_then_else:V_VLSI + (unspec: +- [(match_operand: 1 "vector_mask_operand" " vm, vm, vm,Wc1,Wc1, Wc1") +- (match_operand 6 "vector_length_operand" "rvl,rvl, rvl,rvl,rvl, rvl") +- (match_operand 7 "const_int_operand" " i, i, i, i, i, i") +- (match_operand 8 "const_int_operand" " i, i, i, i, i, i") +- (match_operand 9 "const_int_operand" " i, i, i, i, i, i") ++ [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") ++ (match_operand 6 "vector_length_operand" " rK, rK, rK, rK") ++ (match_operand 7 "const_int_operand" " i, i, i, i") ++ (match_operand 8 "const_int_operand" " i, i, i, i") ++ (match_operand 9 "const_int_operand" " i, i, i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (minus:V_VLSI +- (match_operand:V_VLSI 5 "register_operand" " vr, 0, vr, vr, 0, vr") ++ (match_operand:V_VLSI 5 "register_operand" " vr, 0, vr, 0") + (mult:V_VLSI +- (match_operand:V_VLSI 3 "register_operand" " 0, vr, vr, 0, vr, vr") +- (match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr, vr, vr"))) ++ (match_operand:V_VLSI 3 "register_operand" " 0, vr, 0, vr") ++ (match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr"))) + (match_operand:V_VLSI 2 "vector_undef_operand")))] + "TARGET_VECTOR" + "@ + vnmsub.vv\t%0,%4,%5%p1 + vnmsac.vv\t%0,%3,%4%p1 +- vmv%m3r.v\t%0,%3\;vnmsub.vv\t%0,%4,%5%p1 + vnmsub.vv\t%0,%4,%5%p1 +- vnmsac.vv\t%0,%3,%4%p1 +- vmv%m3r.v\t%0,%3\;vnmsub.vv\t%0,%4,%5%p1" ++ vnmsac.vv\t%0,%3,%4%p1" + [(set_attr "type" "vimuladd") + (set_attr "mode" "")]) + + (define_insn "*pred_nmsub" +- [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr") ++ [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vr") + (if_then_else:V_VLSI + (unspec: +- [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1, Wc1") +- (match_operand 5 "vector_length_operand" "rvl, rvl,rvl, rvl") +- (match_operand 6 "const_int_operand" " i, i, i, i") +- (match_operand 7 "const_int_operand" " i, i, i, i") +- (match_operand 8 "const_int_operand" " i, i, i, i") ++ [(match_operand: 1 "vector_mask_operand" " vm,Wc1") ++ (match_operand 5 "vector_length_operand" " rK, rK") ++ (match_operand 6 "const_int_operand" " i, i") ++ (match_operand 7 "const_int_operand" " i, i") ++ (match_operand 8 "const_int_operand" " i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (minus:V_VLSI +- (match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr") ++ (match_operand:V_VLSI 4 "register_operand" " vr, vr") + (mult:V_VLSI +- (match_operand:V_VLSI 2 "register_operand" " 0, vr, 0, vr") +- (match_operand:V_VLSI 3 "register_operand" " vr, vr, vr, vr"))) ++ (match_operand:V_VLSI 2 "register_operand" " 0, 0") ++ (match_operand:V_VLSI 3 "register_operand" " vr, vr"))) + (match_dup 2)))] + "TARGET_VECTOR" + "@ + vnmsub.vv\t%0,%3,%4%p1 +- vmv%m2r.v\t%0,%2\;vnmsub.vv\t%0,%3,%4%p1 +- vnmsub.vv\t%0,%3,%4%p1 +- vmv%m2r.v\t%0,%2\;vnmsub.vv\t%0,%3,%4%p1" ++ vnmsub.vv\t%0,%3,%4%p1" + [(set_attr "type" "vimuladd") + (set_attr "mode" "") + (set_attr "merge_op_idx" "2") +@@ -5898,28 +5878,26 @@ + (set (attr "avl_type_idx") (const_int 8))]) + + (define_insn "*pred_nmsac" +- [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr") ++ [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vr") + (if_then_else:V_VLSI + (unspec: +- [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1, Wc1") +- (match_operand 5 "vector_length_operand" "rvl, rvl,rvl, rvl") +- (match_operand 6 "const_int_operand" " i, i, i, i") +- (match_operand 7 "const_int_operand" " i, i, i, i") +- (match_operand 8 "const_int_operand" " i, i, i, i") ++ [(match_operand: 1 "vector_mask_operand" " vm,Wc1") ++ (match_operand 5 "vector_length_operand" " rK, rK") ++ (match_operand 6 "const_int_operand" " i, i") ++ (match_operand 7 "const_int_operand" " i, i") ++ (match_operand 8 "const_int_operand" " i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (minus:V_VLSI +- (match_operand:V_VLSI 4 "register_operand" " 0, vr, 0, vr") ++ (match_operand:V_VLSI 4 "register_operand" " 0, 0") + (mult:V_VLSI +- (match_operand:V_VLSI 2 "register_operand" " vr, vr, vr, vr") +- (match_operand:V_VLSI 3 "register_operand" " vr, vr, vr, vr"))) ++ (match_operand:V_VLSI 2 "register_operand" " vr, vr") ++ (match_operand:V_VLSI 3 "register_operand" " vr, vr"))) + (match_dup 4)))] + "TARGET_VECTOR" + "@ + vnmsac.vv\t%0,%2,%3%p1 +- vmv%m4r.v\t%0,%4\;vnmsac.vv\t%0,%2,%3%p1 +- vnmsac.vv\t%0,%2,%3%p1 +- vmv%m4r.v\t%0,%4\;vnmsac.vv\t%0,%2,%3%p1" ++ vnmsac.vv\t%0,%2,%3%p1" + [(set_attr "type" "vimuladd") + (set_attr "mode" "") + (set_attr "merge_op_idx" "4") +@@ -5950,29 +5928,27 @@ + {}) + + (define_insn "*pred_nmsub_scalar" +- [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr") ++ [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vr") + (if_then_else:V_VLSI + (unspec: +- [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1, Wc1") +- (match_operand 5 "vector_length_operand" "rvl, rvl,rvl, rvl") +- (match_operand 6 "const_int_operand" " i, i, i, i") +- (match_operand 7 "const_int_operand" " i, i, i, i") +- (match_operand 8 "const_int_operand" " i, i, i, i") ++ [(match_operand: 1 "vector_mask_operand" " vm,Wc1") ++ (match_operand 5 "vector_length_operand" " rK, rK") ++ (match_operand 6 "const_int_operand" " i, i") ++ (match_operand 7 "const_int_operand" " i, i") ++ (match_operand 8 "const_int_operand" " i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (minus:V_VLSI +- (match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr") ++ (match_operand:V_VLSI 4 "register_operand" " vr, vr") + (mult:V_VLSI + (vec_duplicate:V_VLSI +- (match_operand: 2 "reg_or_0_operand" " rJ, rJ, rJ, rJ")) +- (match_operand:V_VLSI 3 "register_operand" " 0, vr, 0, vr"))) ++ (match_operand: 2 "reg_or_0_operand" " rJ, rJ")) ++ (match_operand:V_VLSI 3 "register_operand" " 0, 0"))) + (match_dup 3)))] + "TARGET_VECTOR" + "@ + vnmsub.vx\t%0,%z2,%4%p1 +- vmv%m3r.v\t%0,%3\;vnmsub.vx\t%0,%z2,%4%p1 +- vnmsub.vx\t%0,%z2,%4%p1 +- vmv%m3r.v\t%0,%3\;vnmsub.vx\t%0,%z2,%4%p1" ++ vnmsub.vx\t%0,%z2,%4%p1" + [(set_attr "type" "vimuladd") + (set_attr "mode" "") + (set_attr "merge_op_idx" "3") +@@ -5982,29 +5958,27 @@ + (set (attr "avl_type_idx") (const_int 8))]) + + (define_insn "*pred_nmsac_scalar" +- [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr") ++ [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vr") + (if_then_else:V_VLSI + (unspec: +- [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1, Wc1") +- (match_operand 5 "vector_length_operand" "rvl, rvl,rvl, rvl") +- (match_operand 6 "const_int_operand" " i, i, i, i") +- (match_operand 7 "const_int_operand" " i, i, i, i") +- (match_operand 8 "const_int_operand" " i, i, i, i") ++ [(match_operand: 1 "vector_mask_operand" " vm,Wc1") ++ (match_operand 5 "vector_length_operand" " rK, rK") ++ (match_operand 6 "const_int_operand" " i, i") ++ (match_operand 7 "const_int_operand" " i, i") ++ (match_operand 8 "const_int_operand" " i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (minus:V_VLSI +- (match_operand:V_VLSI 4 "register_operand" " 0, vr, 0, vr") ++ (match_operand:V_VLSI 4 "register_operand" " 0, 0") + (mult:V_VLSI + (vec_duplicate:V_VLSI +- (match_operand: 2 "reg_or_0_operand" " rJ, rJ, rJ, rJ")) +- (match_operand:V_VLSI 3 "register_operand" " vr, vr, vr, vr"))) ++ (match_operand: 2 "reg_or_0_operand" " rJ, rJ")) ++ (match_operand:V_VLSI 3 "register_operand" " vr, vr"))) + (match_dup 4)))] + "TARGET_VECTOR" + "@ + vnmsac.vx\t%0,%z2,%3%p1 +- vmv%m4r.v\t%0,%4\;vnmsac.vx\t%0,%z2,%3%p1 +- vnmsac.vx\t%0,%z2,%3%p1 +- vmv%m4r.v\t%0,%4\;vnmsac.vx\t%0,%z2,%3%p1" ++ vnmsac.vx\t%0,%z2,%3%p1" + [(set_attr "type" "vimuladd") + (set_attr "mode" "") + (set_attr "merge_op_idx" "4") +@@ -6049,30 +6023,28 @@ + }) + + (define_insn "*pred_nmsub_extended_scalar" +- [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,?&vd, vr,?&vr") ++ [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd, vr") + (if_then_else:V_VLSI_D + (unspec: +- [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1, Wc1") +- (match_operand 5 "vector_length_operand" "rvl, rvl,rvl, rvl") +- (match_operand 6 "const_int_operand" " i, i, i, i") +- (match_operand 7 "const_int_operand" " i, i, i, i") +- (match_operand 8 "const_int_operand" " i, i, i, i") ++ [(match_operand: 1 "vector_mask_operand" " vm,Wc1") ++ (match_operand 5 "vector_length_operand" " rK, rK") ++ (match_operand 6 "const_int_operand" " i, i") ++ (match_operand 7 "const_int_operand" " i, i") ++ (match_operand 8 "const_int_operand" " i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (minus:V_VLSI_D +- (match_operand:V_VLSI_D 4 "register_operand" " vr, vr, vr, vr") ++ (match_operand:V_VLSI_D 4 "register_operand" " vr, vr") + (mult:V_VLSI_D + (vec_duplicate:V_VLSI_D + (sign_extend: +- (match_operand: 2 "reg_or_0_operand" " rJ, rJ, rJ, rJ"))) +- (match_operand:V_VLSI_D 3 "register_operand" " 0, vr, 0, vr"))) ++ (match_operand: 2 "reg_or_0_operand" " rJ, rJ"))) ++ (match_operand:V_VLSI_D 3 "register_operand" " 0, 0"))) + (match_dup 3)))] + "TARGET_VECTOR && !TARGET_64BIT" + "@ + vnmsub.vx\t%0,%z2,%4%p1 +- vmv%m3r.v\t%0,%3\;vnmsub.vx\t%0,%z2,%4%p1 +- vnmsub.vx\t%0,%z2,%4%p1 +- vmv%m3r.v\t%0,%3\;vnmsub.vx\t%0,%z2,%4%p1" ++ vnmsub.vx\t%0,%z2,%4%p1" + [(set_attr "type" "vimuladd") + (set_attr "mode" "") + (set_attr "merge_op_idx" "3") +@@ -6082,30 +6054,28 @@ + (set (attr "avl_type_idx") (const_int 8))]) + + (define_insn "*pred_nmsac_extended_scalar" +- [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,?&vd, vr,?&vr") ++ [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd, vr") + (if_then_else:V_VLSI_D + (unspec: +- [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1, Wc1") +- (match_operand 5 "vector_length_operand" "rvl, rvl,rvl, rvl") +- (match_operand 6 "const_int_operand" " i, i, i, i") +- (match_operand 7 "const_int_operand" " i, i, i, i") +- (match_operand 8 "const_int_operand" " i, i, i, i") ++ [(match_operand: 1 "vector_mask_operand" " vm,Wc1") ++ (match_operand 5 "vector_length_operand" " rK, rK") ++ (match_operand 6 "const_int_operand" " i, i") ++ (match_operand 7 "const_int_operand" " i, i") ++ (match_operand 8 "const_int_operand" " i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (minus:V_VLSI_D +- (match_operand:V_VLSI_D 4 "register_operand" " 0, vr, 0, vr") ++ (match_operand:V_VLSI_D 4 "register_operand" " 0, 0") + (mult:V_VLSI_D + (vec_duplicate:V_VLSI_D + (sign_extend: +- (match_operand: 2 "reg_or_0_operand" " rJ, rJ, rJ, rJ"))) +- (match_operand:V_VLSI_D 3 "register_operand" " vr, vr, vr, vr"))) ++ (match_operand: 2 "reg_or_0_operand" " rJ, rJ"))) ++ (match_operand:V_VLSI_D 3 "register_operand" " vr, vr"))) + (match_dup 4)))] + "TARGET_VECTOR && !TARGET_64BIT" + "@ + vnmsac.vx\t%0,%z2,%3%p1 +- vmv%m4r.v\t%0,%4\;vnmsac.vx\t%0,%z2,%3%p1 +- vnmsac.vx\t%0,%z2,%3%p1 +- vmv%m4r.v\t%0,%4\;vnmsac.vx\t%0,%z2,%3%p1" ++ vnmsac.vx\t%0,%z2,%3%p1" + [(set_attr "type" "vimuladd") + (set_attr "mode" "") + (set_attr "merge_op_idx" "4") +-- +2.47.3 + diff --git a/1080-RISC-V-Prefer-Python3-usage-to-avoid-SyntaxError-wit.patch b/1080-RISC-V-Prefer-Python3-usage-to-avoid-SyntaxError-wit.patch new file mode 100644 index 0000000..e6f5283 --- /dev/null +++ b/1080-RISC-V-Prefer-Python3-usage-to-avoid-SyntaxError-wit.patch @@ -0,0 +1,33 @@ +From 17b83d55f5119100a8134c1177269be02a020d7a Mon Sep 17 00:00:00 2001 +From: Jin Ma +Date: Tue, 29 Jul 2025 11:00:00 +0800 +Subject: [PATCH 1080/1087] RISC-V: Prefer Python3 usage to avoid SyntaxError + with print_function + +commit upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +gcc/ChangeLog: + + * config.gcc: Priority Search python3. +--- + gcc/config.gcc | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/gcc/config.gcc b/gcc/config.gcc +index e5dfa561f5d..09d137a4e91 100644 +--- a/gcc/config.gcc ++++ b/gcc/config.gcc +@@ -4745,7 +4745,7 @@ case "${target}" in + exit 1 + ;; + esac +- PYTHON=`which python || which python3 || which python2` ++ PYTHON=`which python3 || which python || which python2` + if test "x${PYTHON}" != x; then + with_arch=`${PYTHON} ${srcdir}/config/riscv/arch-canonicalize -misa-spec=${with_isa_spec} ${with_arch}` + fi +-- +2.47.3 + diff --git a/1081-RISC-V-Fix-type-validation-for-RVV-fixed-length-vari.patch b/1081-RISC-V-Fix-type-validation-for-RVV-fixed-length-vari.patch new file mode 100644 index 0000000..0410a89 --- /dev/null +++ b/1081-RISC-V-Fix-type-validation-for-RVV-fixed-length-vari.patch @@ -0,0 +1,120 @@ +From c8adf72edcbf803bb37f328e7966672ae88b60f9 Mon Sep 17 00:00:00 2001 +From: Jin Ma +Date: Tue, 29 Jul 2025 11:04:10 +0800 +Subject: [PATCH 1081/1087] RISC-V: Fix type validation for RVV fixed-length + variable declarations + +commit upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +gcc/ChangeLog: + + * config/riscv/riscv-vector-builtins.cc (verify_type_context): + Return true if Non-variable length type. + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/rvv/base/rvv_fixed.c: New test. + * gcc.target/riscv/rvv/base/rvv_fixed_run.c: New test. +--- + gcc/config/riscv/riscv-vector-builtins.cc | 4 ++ + .../gcc.target/riscv/rvv/base/rvv_fixed.c | 19 ++++++++ + .../gcc.target/riscv/rvv/base/rvv_fixed_run.c | 44 +++++++++++++++++++ + 3 files changed, 67 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv_fixed.c + create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv_fixed_run.c + +diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc +index 3c189fd0d99..e691bd364a4 100644 +--- a/gcc/config/riscv/riscv-vector-builtins.cc ++++ b/gcc/config/riscv/riscv-vector-builtins.cc +@@ -4542,6 +4542,10 @@ verify_type_context (location_t loc, type_context_kind context, const_tree type, + if (!sizeless_type_p (type)) + return true; + ++ /* Non-variable length type do not do things. */ ++ if (GET_MODE_SIZE (TYPE_MODE (type)).is_constant ()) ++ return true; ++ + switch (context) + { + case TCTX_SIZEOF: +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv_fixed.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv_fixed.c +new file mode 100644 +index 00000000000..049d5d92133 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv_fixed.c +@@ -0,0 +1,19 @@ ++/* { dg-do compile } */ ++/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -mrvv-vector-bits=zvl" { target { rv32 } } } */ ++/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -mrvv-vector-bits=zvl" { target { rv64 } } } */ ++ ++#include ++ ++/* Sizeless objects with global scope. */ ++ ++vint8m1_t global_rvv_sc; ++static vint8m1_t local_rvv_sc; ++extern vint8m1_t extern_rvv_sc; ++__thread vint8m1_t tls_rvv_sc; ++_Atomic vint8m1_t atomic_rvv_sc; ++ ++struct rvv_fixed ++{ ++ vfloat32m1_t a; ++ vfloat32m1_t b; ++}x; +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv_fixed_run.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv_fixed_run.c +new file mode 100644 +index 00000000000..84905985332 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv_fixed_run.c +@@ -0,0 +1,44 @@ ++/* { dg-do run { target { riscv_v } } } ++/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -mrvv-vector-bits=zvl" { target { rv32 } } } */ ++/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -mrvv-vector-bits=zvl" { target { rv64 } } } */ ++ ++#include ++#include ++ ++int32_t a[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; ++ ++struct rvv_fixed ++{ ++ size_t gvl; ++ vint32m1_t va; ++ vint32m1_t vb; ++ vint32m1_t vc; ++}; ++ ++// Vector version. ++void __attribute__((noinline)) add_vectorized(int32_t *c, int32_t *a, int32_t *b, int N) { ++ struct rvv_fixed x; ++ for (; N > 0; N -= x.gvl) { ++ x.gvl = __riscv_vsetvl_e32m1(N); ++ x.va = __riscv_vle32_v_i32m1(a, x.gvl); ++ a += x.gvl; ++ x.vb = __riscv_vle32_v_i32m1(b, x.gvl); ++ b += x.gvl; ++ x.vc = __riscv_vadd_vv_i32m1(x.va, x.vb, x.gvl); ++ __riscv_vse32_v_i32m1(c, x.vc, x.gvl); ++ c += x.gvl; ++ } ++} ++ ++int main() { ++ int N = 16; ++ int32_t vector[N]; ++ add_vectorized(vector, a, a, N); ++ for (int i = 0; i < N; i++) ++ printf("%d ", vector[i]); ++ printf("\n"); ++ return 0; ++} ++ ++/* { dg-output "2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 \r\n" } */ ++ +-- +2.47.3 + diff --git a/1082-RISC-V-Fix-ICE-for-amo.patch b/1082-RISC-V-Fix-ICE-for-amo.patch new file mode 100644 index 0000000..c92dad0 --- /dev/null +++ b/1082-RISC-V-Fix-ICE-for-amo.patch @@ -0,0 +1,35 @@ +From bdd2b3ae685bce4567fb7cb67750828a11bbcdc8 Mon Sep 17 00:00:00 2001 +From: Jin Ma +Date: Tue, 29 Jul 2025 11:09:56 +0800 +Subject: [PATCH 1082/1087] RISC-V: Fix ICE for amo. + +commit upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +Dozens of failure cases are already included in "gcc/testsuite/gcc.dg/atomic", +so there is no need to add additional testcases. + +gcc/ChangeLog: + + * config/riscv/sync.md: Add zero to predicate. +--- + gcc/config/riscv/sync.md | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md +index 2bd1775b133..31a64f662bc 100644 +--- a/gcc/config/riscv/sync.md ++++ b/gcc/config/riscv/sync.md +@@ -627,7 +627,7 @@ + (match_operand:SHORT 1 "memory_operand" "+A")) ;; memory + (set (match_dup 1) + (unspec_volatile:SHORT [(match_operand:SHORT 2 "register_operand" "0") ;; expected_val +- (match_operand:SHORT 3 "register_operand" "rJ") ;; desired_val ++ (match_operand:SHORT 3 "reg_or_0_operand" "rJ") ;; desired_val + (match_operand:SI 4 "const_int_operand") ;; mod_s + (match_operand:SI 5 "const_int_operand")] ;; mod_f + UNSPEC_COMPARE_AND_SWAP))] +-- +2.47.3 + diff --git a/1083-RISC-V-Implement-vcpop-intrinsics-for-Zvbb-extension.patch b/1083-RISC-V-Implement-vcpop-intrinsics-for-Zvbb-extension.patch new file mode 100644 index 0000000..71fc370 --- /dev/null +++ b/1083-RISC-V-Implement-vcpop-intrinsics-for-Zvbb-extension.patch @@ -0,0 +1,85 @@ +From 19bd118c8a3895759e2a4c5740f4be12307ca101 Mon Sep 17 00:00:00 2001 +From: Jin Ma +Date: Tue, 29 Jul 2025 11:12:36 +0800 +Subject: [PATCH 1083/1087] RISC-V: Implement vcpop intrinsics for Zvbb + extension + +commit upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +gcc/ChangeLog: + + * config/riscv/generic-vector-ooo.md: Add vcpop for pipeline. + * config/riscv/riscv-vector-builtins-bases.cc: Likewise. + * config/riscv/riscv-vector-builtins-functions.def (vcpop): Likewise. + * config/riscv/vector-crypto.md: Likewise. +--- + gcc/config/riscv/generic-vector-ooo.md | 2 +- + gcc/config/riscv/riscv-vector-builtins-bases.cc | 10 +++++++++- + gcc/config/riscv/riscv-vector-builtins-functions.def | 1 + + gcc/config/riscv/vector-crypto.md | 2 +- + 4 files changed, 12 insertions(+), 3 deletions(-) + +diff --git a/gcc/config/riscv/generic-vector-ooo.md b/gcc/config/riscv/generic-vector-ooo.md +index efe6bc41e86..3e130c63e23 100644 +--- a/gcc/config/riscv/generic-vector-ooo.md ++++ b/gcc/config/riscv/generic-vector-ooo.md +@@ -46,7 +46,7 @@ + (define_insn_reservation "vec_alu" 3 + (eq_attr "type" "vialu,viwalu,vext,vicalu,vshift,vnshift,viminmax,vicmp,\ + vimov,vsalu,vaalu,vsshift,vnclip,vmov,vfmov,vector,\ +- vandn,vbrev,vbrev8,vrev8,vclz,vctz,vrol,vror,vwsll") ++ vandn,vbrev,vbrev8,vrev8,vclz,vctz,vcpop,vrol,vror,vwsll") + "vxu_ooo_issue,vxu_ooo_alu") + + ;; Vector float comparison, conversion etc. +diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc +index 12f8438675b..b7a755b7840 100644 +--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc ++++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc +@@ -988,7 +988,15 @@ public: + + rtx expand (function_expander &e) const override + { +- return e.use_exact_insn (code_for_pred_popcount (e.vector_mode (), Pmode)); ++ switch (e.op_info->op) ++ { ++ case OP_TYPE_v: ++ return e.use_exact_insn (code_for_pred_v (POPCOUNT, e.vector_mode ())); ++ case OP_TYPE_m: ++ return e.use_exact_insn (code_for_pred_popcount (e.vector_mode (), Pmode)); ++ default: ++ gcc_unreachable (); ++ } + } + }; + +diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def +index b69cf3cae29..583e674ead6 100644 +--- a/gcc/config/riscv/riscv-vector-builtins-functions.def ++++ b/gcc/config/riscv/riscv-vector-builtins-functions.def +@@ -659,6 +659,7 @@ DEF_RVV_FUNCTION (vlsegff, seg_fault_load, full_preds, tuple_v_scalar_const_ptr_ + DEF_RVV_FUNCTION (vbrev, alu, full_preds, u_vv_ops) + DEF_RVV_FUNCTION (vclz, alu, none_m_preds, u_vv_ops) + DEF_RVV_FUNCTION (vctz, alu, none_m_preds, u_vv_ops) ++DEF_RVV_FUNCTION (vcpop, alu, none_m_preds, u_vv_ops) + DEF_RVV_FUNCTION (vwsll, alu, full_preds, u_wvv_ops) + DEF_RVV_FUNCTION (vwsll, alu, full_preds, u_shift_wvx_ops) + #undef REQUIRED_EXTENSIONS +diff --git a/gcc/config/riscv/vector-crypto.md b/gcc/config/riscv/vector-crypto.md +index b01d3af0179..b19e512ba62 100755 +--- a/gcc/config/riscv/vector-crypto.md ++++ b/gcc/config/riscv/vector-crypto.md +@@ -344,7 +344,7 @@ + [(set_attr "type" "v") + (set_attr "mode" "")]) + +-;; vclz.v vctz.v ++;; vclz.v vctz.v vcpop.v + (define_insn "@pred_v" + [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vr") + (clz_ctz_pcnt:V_VLSI +-- +2.47.3 + diff --git a/1084-RISC-V-Add-missing-overlaps-for-vector-crypto.patch b/1084-RISC-V-Add-missing-overlaps-for-vector-crypto.patch new file mode 100644 index 0000000..e02b9eb --- /dev/null +++ b/1084-RISC-V-Add-missing-overlaps-for-vector-crypto.patch @@ -0,0 +1,54 @@ +From 826993278ff926f19833fa79405c7859f41b19bb Mon Sep 17 00:00:00 2001 +From: Jin Ma +Date: Tue, 29 Jul 2025 11:15:38 +0800 +Subject: [PATCH 1084/1087] RISC-V: Add missing overlaps for vector crypto + +commit upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +According to RVV spec, the following instructions need to be overlaps +restricted, otherwise illegal instructions will appear. +vsm3me.vv/vaeskf2.vi/vsm3c.vi/vsha2ms.vv/vsha2ch.vv/vsha2cl.vv/vghsh.vv + +gcc/ChangeLog: + + * config/riscv/vector-crypto.md: Add &. +--- + gcc/config/riscv/vector-crypto.md | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/gcc/config/riscv/vector-crypto.md b/gcc/config/riscv/vector-crypto.md +index b19e512ba62..b5ead8fdbd0 100755 +--- a/gcc/config/riscv/vector-crypto.md ++++ b/gcc/config/riscv/vector-crypto.md +@@ -464,7 +464,7 @@ + ;; zvknh[ab] and zvkg instructions patterns. + ;; vsha2ms.vv vsha2ch.vv vsha2cl.vv vghsh.vv + (define_insn "@pred_v" +- [(set (match_operand:VQEXTI 0 "register_operand" "=vr") ++ [(set (match_operand:VQEXTI 0 "register_operand" "=&vr") + (if_then_else:VQEXTI + (unspec: + [(match_operand 4 "vector_length_operand" "rK") +@@ -615,7 +615,7 @@ + + ;; vaeskf2.vi vsm3c.vi + (define_insn "@pred_vi_nomaskedoff_scalar" +- [(set (match_operand:VSI 0 "register_operand" "=vr") ++ [(set (match_operand:VSI 0 "register_operand" "=&vr") + (if_then_else:VSI + (unspec: + [(match_operand 4 "vector_length_operand" "rK") +@@ -636,7 +636,7 @@ + ;; zvksh instructions patterns. + ;; vsm3me.vv + (define_insn "@pred_vsm3me" +- [(set (match_operand:VSI 0 "register_operand" "=vr, vr") ++ [(set (match_operand:VSI 0 "register_operand" "=&vr, vr") + (if_then_else:VSI + (unspec: + [(match_operand 4 "vector_length_operand" " rK, rK") +-- +2.47.3 + diff --git a/1085-RISC-V-Fix-the-wrong-vmul-for-vector-crypto.patch b/1085-RISC-V-Fix-the-wrong-vmul-for-vector-crypto.patch new file mode 100644 index 0000000..7007d43 --- /dev/null +++ b/1085-RISC-V-Fix-the-wrong-vmul-for-vector-crypto.patch @@ -0,0 +1,87 @@ +From aca0d3d97e5ee6d235b649f823535ecfc021cad2 Mon Sep 17 00:00:00 2001 +From: Jin Ma +Date: Tue, 29 Jul 2025 11:20:41 +0800 +Subject: [PATCH 1085/1087] RISC-V: Fix the wrong vmul for vector crypto + +commit upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +Because the wrong mode is not pattern, vsetvl is generated. +Vtype error at the time of the instruction, causing a program +exception. + +gcc/ChangeLog: + + * config/riscv/vector-crypto.md: Corrected mode. + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/rvv/base/bug-zvkned.c: New test. +--- + gcc/config/riscv/vector-crypto.md | 8 ++++---- + gcc/testsuite/gcc.target/riscv/rvv/base/bug-zvkned.c | 12 ++++++++++++ + 2 files changed, 16 insertions(+), 4 deletions(-) + create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/bug-zvkned.c + +diff --git a/gcc/config/riscv/vector-crypto.md b/gcc/config/riscv/vector-crypto.md +index b5ead8fdbd0..ec705111581 100755 +--- a/gcc/config/riscv/vector-crypto.md ++++ b/gcc/config/riscv/vector-crypto.md +@@ -538,7 +538,7 @@ + "TARGET_ZVKNED || TARGET_ZVKSED" + "v.\t%0,%2" + [(set_attr "type" "v") +- (set_attr "mode" "")]) ++ (set_attr "mode" "")]) + + (define_insn "@pred_crypto_vvx4_scalar" + [(set (match_operand: 0 "register_operand" "=&vr") +@@ -556,7 +556,7 @@ + "TARGET_ZVKNED || TARGET_ZVKSED" + "v.\t%0,%2" + [(set_attr "type" "v") +- (set_attr "mode" "")]) ++ (set_attr "mode" "")]) + + (define_insn "@pred_crypto_vvx8_scalar" + [(set (match_operand: 0 "register_operand" "=&vr") +@@ -574,7 +574,7 @@ + "TARGET_ZVKNED || TARGET_ZVKSED" + "v.\t%0,%2" + [(set_attr "type" "v") +- (set_attr "mode" "")]) ++ (set_attr "mode" "")]) + + (define_insn "@pred_crypto_vvx16_scalar" + [(set (match_operand: 0 "register_operand" "=&vr") +@@ -592,7 +592,7 @@ + "TARGET_ZVKNED || TARGET_ZVKSED" + "v.\t%0,%2" + [(set_attr "type" "v") +- (set_attr "mode" "")]) ++ (set_attr "mode" "")]) + + ;; vaeskf1.vi vsm4k.vi + (define_insn "@pred_crypto_vi_scalar" +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-zvkned.c b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-zvkned.c +new file mode 100644 +index 00000000000..26a7eb4dd28 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-zvkned.c +@@ -0,0 +1,12 @@ ++/* { dg-do assemble { target { rv64 } } } */ ++/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-O3" "-Og" "-Os" "-Oz" } } */ ++/* { dg-options "-march=rv64gcv_zvkned -mabi=lp64d -O2 -save-temps" } */ ++ ++#include ++ ++vuint32m8_t foo (vuint32m8_t vd, vuint32m1_t vs2, size_t vl) ++{ ++ return __riscv_vaesef_vs_u32m1_u32m8 (vd, vs2, vl); ++} ++ ++/* { dg-final { scan-assembler-times "vsetvli.*e32,m8" 1 } } */ +-- +2.47.3 + diff --git a/1086-RISC-V-XuanTie-Add-xt-c930-support-for-mcpu.patch b/1086-RISC-V-XuanTie-Add-xt-c930-support-for-mcpu.patch new file mode 100644 index 0000000..5e3d646 --- /dev/null +++ b/1086-RISC-V-XuanTie-Add-xt-c930-support-for-mcpu.patch @@ -0,0 +1,192 @@ +From 730c6df526f260bcdcc7f9f6bfa0e7f76b325ae9 Mon Sep 17 00:00:00 2001 +From: Jin Ma +Date: Tue, 29 Jul 2025 11:22:58 +0800 +Subject: [PATCH 1086/1087] RISC-V: XuanTie: Add xt-c930 support for -mcpu + +commit upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +gcc/ChangeLog: + + * config/riscv/riscv-cores.def (RISCV_TUNE): New CPU + (RISCV_CORE): Likewise. + * config/riscv/riscv.cc: Likewise. + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/mcpu-xt-c930.c: New test. +--- + gcc/config/riscv/riscv-cores.def | 15 +++ + gcc/config/riscv/riscv.cc | 18 ++++ + gcc/testsuite/gcc.target/riscv/mcpu-xt-c930.c | 96 +++++++++++++++++++ + 3 files changed, 129 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-xt-c930.c + +diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def +index 2f5efe3be86..609aed7aa3d 100644 +--- a/gcc/config/riscv/riscv-cores.def ++++ b/gcc/config/riscv/riscv-cores.def +@@ -40,6 +40,7 @@ RISCV_TUNE("sifive-7-series", sifive_7, sifive_7_tune_info) + RISCV_TUNE("sifive-p400-series", sifive_p400, sifive_p400_tune_info) + RISCV_TUNE("sifive-p600-series", sifive_p600, sifive_p600_tune_info) + RISCV_TUNE("thead-c906", generic, thead_c906_tune_info) ++RISCV_TUNE("xt-c930", generic, xt_c930_tune_info) + RISCV_TUNE("xiangshan-nanhu", xiangshan, xiangshan_nanhu_tune_info) + RISCV_TUNE("generic-ooo", generic_ooo, generic_ooo_tune_info) + RISCV_TUNE("size", generic, optimize_size_tune_info) +@@ -92,6 +93,20 @@ RISCV_CORE("thead-c906", "rv64imafdc_xtheadba_xtheadbb_xtheadbs_xtheadcmo_" + "xtheadmemidx_xtheadmempair_xtheadsync", + "thead-c906") + ++RISCV_CORE("xt-c930", "rv64imafdcbvh_zic64b_zicbom_zicbop_zicboz_" ++ "ziccamoa_ziccif_zicclsm_ziccrse_zicfilp_zicfiss_" ++ "zicntr_zicond_zicsr_zifencei_zihintntl_" ++ "zihintpause_zihpm_zimop_zmmul_za64rs_zaamo_" ++ "zabha_zacas_zalrsc_zawrs_zfa_zfbfmin_" ++ "zfh_zfhmin_zca_zcb_zcd_zba_zbb_zbc_zbs_" ++ "zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_" ++ "zve64x_zvfbfmin_zvfbfwma_zvfh_zvfhmin_zvkb_" ++ "zvkg_zvkn_zvknc_zvkned_zvkng_zvknha_zvknhb_" ++ "zvks_zvksc_zvksed_zvksg_zvksh_zvkt_zvl128b_zvl256b_" ++ "zvl32b_zvl64b_smaia_smepmp_ssaia_sscofpmf_" ++ "ssstateen_sstc_svinval_svnapot_svpbmt", ++ "xt-c930") ++ + RISCV_CORE("xiangshan-nanhu", "rv64imafdc_zba_zbb_zbc_zbs_" + "zbkb_zbkc_zbkx_zknd_zkne_zknh_zksed_zksh_" + "svinval_zicbom_zicboz", +diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc +index 4f75c49ccd9..6444e5a19fe 100644 +--- a/gcc/config/riscv/riscv.cc ++++ b/gcc/config/riscv/riscv.cc +@@ -509,6 +509,24 @@ static const struct riscv_tune_param thead_c906_tune_info = { + NULL, /* vector cost */ + }; + ++/* Costs to use when optimizing for T-HEAD c930. */ ++const struct riscv_tune_param xt_c930_tune_info = { ++ {COSTS_N_INSNS (2), COSTS_N_INSNS (2)}, /* fp_add */ ++ {COSTS_N_INSNS (3), COSTS_N_INSNS (3)}, /* fp_mul */ ++ {COSTS_N_INSNS (8), COSTS_N_INSNS (13)}, /* fp_div */ ++ {COSTS_N_INSNS (2), COSTS_N_INSNS (2)}, /* int_mul */ ++ {COSTS_N_INSNS (12), COSTS_N_INSNS (12)}, /* int_div */ ++ 8, /* issue_rate */ ++ 2, /* branch_cost */ ++ 5, /* memory_cost */ ++ 2, /* fmv_cost */ ++ false, /* slow_unaligned_access */ ++ false, /* vector_unaligned_access */ ++ true, /* use_divmod_expansion */ ++ RISCV_FUSE_NOTHING, /* fusible_ops */ ++ &generic_vector_cost, /* vector cost */ ++}; ++ + /* Costs to use when optimizing for xiangshan nanhu. */ + static const struct riscv_tune_param xiangshan_nanhu_tune_info = { + {COSTS_N_INSNS (3), COSTS_N_INSNS (3)}, /* fp_add */ +diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c930.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c930.c +new file mode 100644 +index 00000000000..b570dec6094 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c930.c +@@ -0,0 +1,96 @@ ++/* { dg-do compile } */ ++/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */ ++/* { dg-options "-mcpu=xt-c930 -mabi=lp64d" } */ ++/* xt-c930 = rv64imafdcbvh_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_zicfilp_zicfiss_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zmmul_za64rs_zaamo_zabha_zacas_zalrsc_zawrs_zfa_zfbfmin_zfh_zfhmin_zca_zcb_zcd_zba_zbb_zbc_zbs_zkr_zkt_zvbb_zvbc_zve32f_zve32x_zve64d_zve64f_zve64x_zvfbfmin_zvfbfwma_zvfh_zvfhmin_zvkb_zvkg_zvkn_zvknc_zvkned_zvkng_zvknha_zvknhb_zvks_zvksc_zvksed_zvksg_zvksh_zvkt_zvl128b_zvl256b_zvl32b_zvl64b_smaia_smepmp_ssaia_sscofpmf_ssstateen_sstc_svinval_svnapot_svpbmt -mabi=lp64d */ ++ ++#if !((__riscv_xlen == 64) \ ++ && defined(__riscv_float_abi_double) \ ++ && defined(__riscv_mul) \ ++ && defined(__riscv_atomic) \ ++ && defined(__riscv_compressed) \ ++ && defined(__riscv_flen) \ ++ && defined(__riscv_vector) \ ++ && __riscv_v_min_vlen == 256 \ ++ && defined(__riscv_zic64b) \ ++ && defined(__riscv_zicbom) \ ++ && defined(__riscv_zicbop) \ ++ && defined(__riscv_zicboz) \ ++ && defined(__riscv_ziccamoa) \ ++ && defined(__riscv_ziccif) \ ++ && defined(__riscv_zicclsm) \ ++ && defined(__riscv_ziccrse) \ ++ && defined(__riscv_zicfilp) \ ++ && defined(__riscv_zicfiss) \ ++ && defined(__riscv_zicntr) \ ++ && defined(__riscv_zicond) \ ++ && defined(__riscv_zicsr) \ ++ && defined(__riscv_zifencei) \ ++ && defined(__riscv_zihintntl) \ ++ && defined(__riscv_zihintpause) \ ++ && defined(__riscv_zihpm) \ ++ && defined(__riscv_zimop) \ ++ && defined(__riscv_zmmul) \ ++ && defined(__riscv_za64rs) \ ++ && defined(__riscv_zaamo) \ ++ && defined(__riscv_zabha) \ ++ && defined(__riscv_zacas) \ ++ && defined(__riscv_zalrsc) \ ++ && defined(__riscv_zawrs) \ ++ && defined(__riscv_zfa) \ ++ && defined(__riscv_zfbfmin) \ ++ && defined(__riscv_zfh) \ ++ && defined(__riscv_zfhmin) \ ++ && defined(__riscv_zca) \ ++ && defined(__riscv_zcb) \ ++ && defined(__riscv_zcd) \ ++ && defined(__riscv_zba) \ ++ && defined(__riscv_zbb) \ ++ && defined(__riscv_zbc) \ ++ && defined(__riscv_zbs) \ ++ && defined(__riscv_zkr) \ ++ && defined(__riscv_zkt) \ ++ && defined(__riscv_zvbb) \ ++ && defined(__riscv_zvbc) \ ++ && defined(__riscv_zve32f) \ ++ && defined(__riscv_zve32x) \ ++ && defined(__riscv_zve64d) \ ++ && defined(__riscv_zve64f) \ ++ && defined(__riscv_zve64x) \ ++ && defined(__riscv_zvfbfmin) \ ++ && defined(__riscv_zvfbfwma) \ ++ && defined(__riscv_zvfh) \ ++ && defined(__riscv_zvfhmin) \ ++ && defined(__riscv_zvkb) \ ++ && defined(__riscv_zvkg) \ ++ && defined(__riscv_zvkn) \ ++ && defined(__riscv_zvknc) \ ++ && defined(__riscv_zvkned) \ ++ && defined(__riscv_zvkng) \ ++ && defined(__riscv_zvknha) \ ++ && defined(__riscv_zvknhb) \ ++ && defined(__riscv_zvks) \ ++ && defined(__riscv_zvksc) \ ++ && defined(__riscv_zvksed) \ ++ && defined(__riscv_zvksg) \ ++ && defined(__riscv_zvksh) \ ++ && defined(__riscv_zvkt) \ ++ && defined(__riscv_zvl128b) \ ++ && defined(__riscv_zvl256b) \ ++ && defined(__riscv_zvl32b) \ ++ && defined(__riscv_zvl64b) \ ++ && defined(__riscv_smaia) \ ++ && defined(__riscv_smepmp) \ ++ && defined(__riscv_ssaia) \ ++ && defined(__riscv_sscofpmf) \ ++ && defined(__riscv_ssstateen) \ ++ && defined(__riscv_sstc) \ ++ && defined(__riscv_svinval) \ ++ && defined(__riscv_svnapot) \ ++ && defined(__riscv_svpbmt)) ++#error "unexpected arch" ++#endif ++ ++int main() ++{ ++ return 0; ++} +-- +2.47.3 + diff --git a/1087-RISC-V-XuanTie-Add-xt-c930-pipeline-description.patch b/1087-RISC-V-XuanTie-Add-xt-c930-pipeline-description.patch new file mode 100644 index 0000000..64a7868 --- /dev/null +++ b/1087-RISC-V-XuanTie-Add-xt-c930-pipeline-description.patch @@ -0,0 +1,471 @@ +From 86785529ea049cf9d3fa4f44a504d37f2b912109 Mon Sep 17 00:00:00 2001 +From: Jin Ma +Date: Tue, 29 Jul 2025 11:24:05 +0800 +Subject: [PATCH 1087/1087] RISC-V: XuanTie: Add xt-c930 pipeline description + +commit upstream. + +cherry-pick from vers https://code.risc-vers.cn/risc-verse/toolchain/gcc/-/merge_requests/1. + +gcc/ChangeLog: + + * config/riscv/riscv-cores.def (RISCV_TUNE): New TUNE. + * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type): Likewise. + * config/riscv/riscv.md (no,yes"): Likewise. + * config/riscv/xt-c930.md: New file. +--- + gcc/config/riscv/riscv-cores.def | 2 +- + gcc/config/riscv/riscv-opts.h | 3 +- + gcc/config/riscv/riscv.md | 3 +- + gcc/config/riscv/xt-c930.md | 394 +++++++++++++++++++++++++++++++ + 4 files changed, 399 insertions(+), 3 deletions(-) + create mode 100644 gcc/config/riscv/xt-c930.md + +diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def +index 609aed7aa3d..b5b9ae61426 100644 +--- a/gcc/config/riscv/riscv-cores.def ++++ b/gcc/config/riscv/riscv-cores.def +@@ -40,7 +40,7 @@ RISCV_TUNE("sifive-7-series", sifive_7, sifive_7_tune_info) + RISCV_TUNE("sifive-p400-series", sifive_p400, sifive_p400_tune_info) + RISCV_TUNE("sifive-p600-series", sifive_p600, sifive_p600_tune_info) + RISCV_TUNE("thead-c906", generic, thead_c906_tune_info) +-RISCV_TUNE("xt-c930", generic, xt_c930_tune_info) ++RISCV_TUNE("xt-c930", xt_c930, xt_c930_tune_info) + RISCV_TUNE("xiangshan-nanhu", xiangshan, xiangshan_nanhu_tune_info) + RISCV_TUNE("generic-ooo", generic_ooo, generic_ooo_tune_info) + RISCV_TUNE("size", generic, optimize_size_tune_info) +diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h +index f58a07abffc..8a854d2dc10 100644 +--- a/gcc/config/riscv/riscv-opts.h ++++ b/gcc/config/riscv/riscv-opts.h +@@ -58,7 +58,8 @@ enum riscv_microarchitecture_type { + sifive_p400, + sifive_p600, + xiangshan, +- generic_ooo ++ generic_ooo, ++ xt_c930 + }; + extern enum riscv_microarchitecture_type riscv_microarchitecture; + +diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md +index 890312f4a80..19300ff29ad 100644 +--- a/gcc/config/riscv/riscv.md ++++ b/gcc/config/riscv/riscv.md +@@ -662,7 +662,7 @@ + ;; Microarchitectures we know how to tune for. + ;; Keep this in sync with enum riscv_microarchitecture. + (define_attr "tune" +- "generic,sifive_7,sifive_p400,sifive_p600,xiangshan,generic_ooo" ++ "generic,sifive_7,sifive_p400,sifive_p600,xiangshan,generic_ooo,xt_c930" + (const (symbol_ref "((enum attr_tune) riscv_microarchitecture)"))) + + ;; Describe a user's asm statement. +@@ -4332,3 +4332,4 @@ + (include "zc.md") + (include "corev.md") + (include "xiangshan.md") ++(include "xt-c930.md") +diff --git a/gcc/config/riscv/xt-c930.md b/gcc/config/riscv/xt-c930.md +new file mode 100644 +index 00000000000..d1564036050 +--- /dev/null ++++ b/gcc/config/riscv/xt-c930.md +@@ -0,0 +1,394 @@ ++;; Scheduling description for XT-C930. ++;; Copyright (C) 2025 Free Software Foundation, Inc. ++; Contributed by Alibaba Damo Academy Xuantie Team. ++ ++;; This file is part of GCC. ++ ++;; GCC is free software; you can redistribute it and/or modify ++;; it under the terms of the GNU General Public License as published by ++;; the Free Software Foundation; either version 3, or (at your option) ++;; any later version. ++ ++;; GCC is distributed in the hope that it will be useful, ++;; but WITHOUT ANY WARRANTY; without even the implied warranty of ++;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++;; GNU General Public License for more details. ++ ++;; You should have received a copy of the GNU General Public License ++;; along with GCC; see the file COPYING3. If not see ++;; . ++ ++(define_automaton "xt_c930") ++(define_automaton "xt_c930_fv") ++(define_automaton "xt_c930_lsu") ++ ++(define_cpu_unit "xt_c930_sx0, xt_c930_sx1, xt_c930_sx2, xt_c930_sx3" "xt_c930") ++(define_cpu_unit "xt_c930_mx4, xt_c930_mx5" "xt_c930") ++(define_cpu_unit "xt_c930_branch_0, xt_c930_branch_1" "xt_c930") ++(define_cpu_unit "xt_c930_loadstore_0" "xt_c930_lsu") ++(define_cpu_unit "xt_c930_load_1, xt_c930_load_2" "xt_c930_lsu") ++(define_cpu_unit "xt_c930_store_3" "xt_c930_lsu") ++ ++(define_cpu_unit "xt_c930_vfp_0, xt_c930_vfp_1" "xt_c930_fv") ++(define_cpu_unit "xt_c930_fp_2, xt_c930_fp_3" "xt_c930_fv") ++ ++;; UNKNOWN ++ ++(define_insn_reservation "xt_c930_atomic" 20 ++ (and (eq_attr "tune" "xt_c930") ++ (eq_attr "type" "atomic")) ++ "xt_c930_loadstore_0 * 3, nothing *16, xt_c930_loadstore_0") ++ ++;; scalar integer ++ ++(define_reservation "xt_c930_mx_cycle" "(xt_c930_mx4 | xt_c930_mx5)") ++ ++(define_insn_reservation "xt_c930_alu" 1 ++ (and (eq_attr "tune" "xt_c930") ++ (eq_attr "type" "unknown,arith,shift,logical,mtc,mfc,move,slt,multi,nop,ghost,const,bitmanip,sfb_alu,rotate,max,min,minu,maxu,clz,ctz,condmove,mvpair,zicond")) ++ "(xt_c930_sx0 | xt_c930_sx1 | xt_c930_sx2 | xt_c930_sx3 | xt_c930_mx4 | xt_c930_mx5)") ++ ++(define_insn_reservation "xt_c930_cru_insn" 2 ++ (and (eq_attr "tune" "xt_c930") ++ (eq_attr "type" "trap,rdvlenb,rdvl,wrvxrm,wrfrm,rdfrm,vsetvl_pre")) ++ "xt_c930_mx4") ++ ++(define_insn_reservation "xt_c930_mx_misc_insn" 1 ++ (and (eq_attr "tune" "xt_c930") ++ (eq_attr "type" "auipc,vsetvl")) ++ "xt_c930_mx_cycle") ++ ++(define_insn_reservation "xt_c930_mul" 2 ++ (and (eq_attr "tune" "xt_c930") ++ (eq_attr "type" "imul,clmul,cpop,crypto")) ++ "xt_c930_mx_cycle") ++ ++(define_insn_reservation "xt_c930_div" 12 ++ (and (eq_attr "tune" "xt_c930") ++ (eq_attr "type" "idiv")) ++ "xt_c930_mx4 * 12") ++ ++;; actually, the cost of branch insn is 1, but the condition move is also 1, ++;; consider the branch miss, set the cost to 2 to generate more condition move ++;; insn. ++(define_insn_reservation "xt_c930_branch" 2 ++ (and (eq_attr "tune" "xt_c930") ++ (eq_attr "type" "branch")) ++ "(xt_c930_branch_0 | xt_c930_branch_1)") ++ ++(define_insn_reservation "xt_c930_jump" 1 ++ (and (eq_attr "tune" "xt_c930") ++ (eq_attr "type" "jump,call,jalr,ret")) ++ "(xt_c930_branch_0 | xt_c930_branch_1)") ++ ++;; scalar ld/st/set ++ ++(define_reservation "xt_c930_load_cycle" "(xt_c930_loadstore_0 | xt_c930_load_1 | xt_c930_load_2)") ++ ++(define_insn_reservation "xt_c930_scalar_store" 1 ++ (and (eq_attr "tune" "xt_c930") ++ (eq_attr "type" "store,fpstore")) ++ "(xt_c930_loadstore_0 | xt_c930_store_3)") ++ ++(define_insn_reservation "xt_c930_scalar_load_int" 4 ++ (and (eq_attr "tune" "xt_c930") ++ (eq_attr "type" "load")) ++ "xt_c930_load_cycle") ++ ++(define_insn_reservation "xt_c930_scalar_load_fp" 5 ++ (and (eq_attr "tune" "xt_c930") ++ (eq_attr "type" "fpload")) ++ "xt_c930_load_cycle") ++ ++;; scalar fp ++ ++(define_reservation "xt_c930_v_fp_cycle" "(xt_c930_vfp_0 | xt_c930_vfp_1 | xt_c930_fp_2 | xt_c930_fp_3)") ++(define_reservation "xt_c930_v_cycle" "(xt_c930_vfp_0 | xt_c930_vfp_1)") ++ ++(define_insn_reservation "xt_c930_fv_fadd" 2 ++ (and (eq_attr "tune" "xt_c930") ++ (eq_attr "type" "fadd,fmove")) ++ "xt_c930_v_fp_cycle") ++ ++(define_insn_reservation "xt_c930_fv_fcvt" 3 ++ (and (eq_attr "tune" "xt_c930") ++ (eq_attr "type" "fcvt,fcvt_i2f,fcvt_f2i")) ++ "(xt_c930_vfp_1 | xt_c930_fp_3)") ++ ++(define_insn_reservation "xt_c930_fv_fcmp" 3 ++ (and (eq_attr "tune" "xt_c930") ++ (eq_attr "type" "fcmp")) ++ "xt_c930_v_cycle") ++ ++(define_insn_reservation "xt_c930_fv_hfmul" 3 ++ (and (eq_attr "tune" "xt_c930") ++ (and (eq_attr "type" "fmul") ++ (eq_attr "mode" "HF,SF"))) ++ "xt_c930_v_fp_cycle") ++ ++(define_insn_reservation "xt_c930_fv_mul" 3 ++ (and (eq_attr "tune" "xt_c930") ++ (and (eq_attr "type" "fmul") ++ (eq_attr "mode" "DF"))) ++ "xt_c930_vfp_1") ++ ++(define_insn_reservation "xt_c930_fv_fmadd" 4 ++ (and (eq_attr "tune" "xt_c930") ++ (eq_attr "type" "fmadd")) ++ "xt_c930_v_fp_cycle") ++ ++(define_insn_reservation "xt_c930_vfpu_hfdiv" 6 ++ (and (eq_attr "tune" "xt_c930") ++ (and (eq_attr "type" "fdiv,fsqrt") ++ (eq_attr "mode" "HF"))) ++ "xt_c930_vfp_1") ++ ++(define_insn_reservation "xt_c930_vfpu_sfdiv" 8 ++ (and (eq_attr "tune" "xt_c930") ++ (and (eq_attr "type" "fdiv,fsqrt") ++ (eq_attr "mode" "SF"))) ++ "xt_c930_vfp_1") ++ ++(define_insn_reservation "xt_c930_vfpu_dfdiv" 13 ++ (and (eq_attr "tune" "xt_c930") ++ (and (eq_attr "type" "fdiv") ++ (eq_attr "mode" "DF"))) ++ "xt_c930_vfp_1") ++ ++(define_insn_reservation "xt_c930_vfpu_dfsqrt" 12 ++ (and (eq_attr "tune" "xt_c930") ++ (and (eq_attr "type" "fsqrt") ++ (eq_attr "mode" "DF"))) ++ "xt_c930_vfp_1") ++ ++;; vector integer ++;; There is no information about vimovvx,vimovxv,vfmovvf,vfmovfv ++;; in Software Optimization Manual, so take them into vperm unit. ++ ++(define_insn_reservation "xt_c930_vector_0" 2 ++ (and (eq_attr "tune" "xt_c930") ++ (eq_attr "type" "vialu,viwalu,vicalu,vshift,vnshift,vicmp,viminmax,vimerge,vmov,vimov,vsalu,vaalu,vsshift,vnclip,vmalu,vandn,vbrev,vbrev8,vrev8,vclz,vctz,vcpop,vrol,vror,vwsll,vclmul,vclmulh,vghsh,vgmul,vaesef,vaesdf,vaeskf1,vaeskf2,vaesz")) ++ "xt_c930_v_cycle") ++ ++(define_insn_reservation "xt_c930_vector_1" 3 ++ (and (eq_attr "tune" "xt_c930") ++ (eq_attr "type" "vaesem,vaesdm,vector")) ++ "xt_c930_v_cycle") ++ ++(define_insn_reservation "xt_c930_vector_2" 2 ++ (and (eq_attr "tune" "xt_c930") ++ (eq_attr "type" "vfslide1up,vfslide1down,vext,vmpop,vmffs,vmsfs,vmiota,vmidx")) ++ "xt_c930_vfp_1") ++ ++(define_insn_reservation "xt_c930_vector_3" 3 ++ (and (eq_attr "tune" "xt_c930") ++ (eq_attr "type" "vimovvx,vimovxv,vslideup,vslidedown,vislide1up,vislide1down,vgather,vcompress,vsha2ms,vsha2ch,vsha2cl,vsm3me,vsm3c")) ++ "xt_c930_vfp_1") ++ ++(define_insn_reservation "xt_c930_vector_4" 4 ++ (and (eq_attr "tune" "xt_c930") ++ (eq_attr "type" "vsm4k,vsm4r")) ++ "xt_c930_vfp_1") ++ ++(define_insn_reservation "xt_c930_vector_imul_sew8_16" 4 ++ (and (eq_attr "tune" "xt_c930") ++ (and (eq_attr "type" "vimul,viwmul,vimuladd,viwmuladd") ++ (eq_attr "sew" "8,16"))) ++ "xt_c930_v_cycle") ++ ++(define_insn_reservation "xt_c930_vector_imul_sew32" 3 ++ (and (eq_attr "tune" "xt_c930") ++ (and (eq_attr "type" "vimul,viwmul") ++ (eq_attr "sew" "32"))) ++ "xt_c930_v_cycle") ++ ++(define_insn_reservation "xt_c930_vector_imuladd_sew32" 4 ++ (and (eq_attr "tune" "xt_c930") ++ (and (eq_attr "type" "vimuladd,viwmuladd") ++ (eq_attr "sew" "32"))) ++ "xt_c930_v_cycle") ++ ++(define_insn_reservation "xt_c930_vector_imul_sew64" 4 ++ (and (eq_attr "tune" "xt_c930") ++ (and (eq_attr "type" "vimul,viwmul,vimuladd,viwmuladd") ++ (eq_attr "sew" "64"))) ++ "xt_c930_vfp_0") ++ ++(define_insn_reservation "xt_c930_vector_vsmul_sew8_16" 3 ++ (and (eq_attr "tune" "xt_c930") ++ (and (eq_attr "type" "vsmul") ++ (eq_attr "sew" "8,16"))) ++ "xt_c930_v_cycle") ++ ++(define_insn_reservation "xt_c930_vector_vsmul_sew32" 4 ++ (and (eq_attr "tune" "xt_c930") ++ (and (eq_attr "type" "vsmul") ++ (eq_attr "sew" "32"))) ++ "xt_c930_v_cycle") ++ ++(define_insn_reservation "xt_c930_vector_vsmul_sew64" 4 ++ (and (eq_attr "tune" "xt_c930") ++ (and (eq_attr "type" "vsmul") ++ (eq_attr "sew" "64"))) ++ "xt_c930_vfp_0") ++ ++(define_insn_reservation "xt_c930_vector_ireduce" 6 ++ (and (eq_attr "tune" "xt_c930") ++ (and (eq_attr "type" "vired,viwred") ++ (eq_attr "sew" "8,16,32"))) ++ "xt_c930_v_cycle") ++ ++(define_insn_reservation "xt_c930_vector_ireduce_sew64" 6 ++ (and (eq_attr "tune" "xt_c930") ++ (and (eq_attr "type" "vired,viwred") ++ (eq_attr "sew" "64"))) ++ "xt_c930_vfp_1") ++ ++(define_insn_reservation "xt_c930_vector_div" 10 ++ (and (eq_attr "tune" "xt_c930") ++ (eq_attr "type" "vidiv")) ++ "xt_c930_vfp_1") ++ ++;; vector ld/st ++ ++(define_insn_reservation "xt_c930_vector_store" 1 ++ (and (eq_attr "tune" "xt_c930") ++ (eq_attr "type" "vste,vstm,vssegte,vssegtox,vssegts,vssegtux,vstox,vstr,vstux")) ++ "xt_c930_loadstore_0") ++ ++(define_insn_reservation "xt_c930_vector_strided_store_sew8" 32 ++ (and (eq_attr "tune" "xt_c930") ++ (and (eq_attr "type" "vsts") ++ (eq_attr "sew" "8"))) ++ "xt_c930_loadstore_0 * 32") ++ ++(define_insn_reservation "xt_c930_vector_strided_store_sew16" 16 ++ (and (eq_attr "tune" "xt_c930") ++ (and (eq_attr "type" "vsts") ++ (eq_attr "sew" "16"))) ++ "xt_c930_loadstore_0 * 16") ++ ++(define_insn_reservation "xt_c930_vector_strided_store_sew32" 8 ++ (and (eq_attr "tune" "xt_c930") ++ (and (eq_attr "type" "vsts") ++ (eq_attr "sew" "32"))) ++ "xt_c930_loadstore_0 * 8") ++ ++(define_insn_reservation "xt_c930_vector_strided_store_sew64" 4 ++ (and (eq_attr "tune" "xt_c930") ++ (and (eq_attr "type" "vsts") ++ (eq_attr "sew" "64"))) ++ "xt_c930_loadstore_0 * 4") ++ ++(define_insn_reservation "xt_c930_vector_load" 5 ++ (and (eq_attr "tune" "xt_c930") ++ (eq_attr "type" "vlde,vldm,vldff,vldox,vldr,vldux,vlsegde,vlsegdff,vlsegdox,vlsegds,vlsegdux")) ++ "(xt_c930_loadstore_0 | xt_c930_load_1)") ++ ++(define_insn_reservation "xt_c930_vector_strided_load_sew8" 51 ++ (and (eq_attr "tune" "xt_c930") ++ (and (eq_attr "type" "vlds") ++ (eq_attr "sew" "8"))) ++ "(xt_c930_loadstore_0 * 16 | xt_c930_load_1 * 16)") ++ ++(define_insn_reservation "xt_c930_vector_strided_load_sew16" 27 ++ (and (eq_attr "tune" "xt_c930") ++ (and (eq_attr "type" "vlds") ++ (eq_attr "sew" "16"))) ++ "(xt_c930_loadstore_0 * 8 | xt_c930_load_1 * 8)") ++ ++(define_insn_reservation "xt_c930_vector_strided_load_sew32" 15 ++ (and (eq_attr "tune" "xt_c930") ++ (and (eq_attr "type" "vlds") ++ (eq_attr "sew" "32"))) ++ "(xt_c930_loadstore_0 * 4 | xt_c930_load_1 * 4)") ++ ++(define_insn_reservation "xt_c930_vector_strided_load_sew64" 8 ++ (and (eq_attr "tune" "xt_c930") ++ (and (eq_attr "type" "vlds") ++ (eq_attr "sew" "64"))) ++ "(xt_c930_loadstore_0 * 2 | xt_c930_load_1 * 2)") ++ ++;; vector float ++ ++(define_insn_reservation "xt_c930_vector_fp_0" 2 ++ (and (eq_attr "tune" "xt_c930") ++ (eq_attr "type" "vfalu,vfwalu,vfsgnj,vfcmp,vfminmax,vfclass,vfmerge,vfmov")) ++ "xt_c930_v_cycle") ++ ++(define_insn_reservation "xt_c930_vector_fp_1" 3 ++ (and (eq_attr "tune" "xt_c930") ++ (eq_attr "type" "vfmovvf,vfmovfv,vfrecp,vfcvtitof,vfcvtftoi,vfwcvtitof,vfwcvtftoi,vfwcvtftof,vfncvtitof,vfncvtftoi,vfncvtftof")) ++ "xt_c930_vfp_1") ++ ++(define_insn_reservation "xt_c930_vector_fp_mul" 3 ++ (and (eq_attr "tune" "xt_c930") ++ (eq_attr "type" "vfmul,vfwmul")) ++ "xt_c930_v_cycle") ++ ++(define_insn_reservation "xt_c930_vector_fp_muladd" 4 ++ (and (eq_attr "tune" "xt_c930") ++ (eq_attr "type" "vfmuladd,vfwmuladd")) ++ "xt_c930_v_cycle") ++ ++(define_insn_reservation "xt_c930_vector_fp_vfredu" 7 ++ (and (eq_attr "tune" "xt_c930") ++ (eq_attr "type" "vfredu,vfwredu")) ++ "xt_c930_v_cycle") ++ ++(define_insn_reservation "xt_c930_vector_fp_vfredo_sew64" 2 ++ (and (eq_attr "tune" "xt_c930") ++ (and (eq_attr "type" "vfredo") ++ (eq_attr "sew" "64"))) ++ "xt_c930_v_cycle") ++ ++(define_insn_reservation "xt_c930_vector_fp_vfredo_sew32" 9 ++ (and (eq_attr "tune" "xt_c930") ++ (and (eq_attr "type" "vfredo") ++ (eq_attr "sew" "32"))) ++ "xt_c930_vfp_1 * 9") ++ ++(define_insn_reservation "xt_c930_vector_fp_vfredo_sew16" 17 ++ (and (eq_attr "tune" "xt_c930") ++ (and (eq_attr "type" "vfredo") ++ (eq_attr "sew" "16"))) ++ "xt_c930_vfp_1 * 17") ++ ++(define_insn_reservation "xt_c930_vector_fp_vfwredo_sew32" 5 ++ (and (eq_attr "tune" "xt_c930") ++ (and (eq_attr "type" "vfwredo") ++ (eq_attr "sew" "32"))) ++ "xt_c930_vfp_1 * 5") ++ ++(define_insn_reservation "xt_c930_vector_fp_vfwredo_sew16" 9 ++ (and (eq_attr "tune" "xt_c930") ++ (and (eq_attr "type" "vfwredo") ++ (eq_attr "sew" "16"))) ++ "xt_c930_vfp_1 * 9") ++ ++(define_insn_reservation "xt_c930_vector_fp_div_sew64" 16 ++ (and (eq_attr "tune" "xt_c930") ++ (and (eq_attr "type" "vfdiv,vfsqrt") ++ (eq_attr "sew" "64"))) ++ "xt_c930_vfp_1") ++ ++(define_insn_reservation "xt_c930_vector_fp_div_sew32" 15 ++ (and (eq_attr "tune" "xt_c930") ++ (and (eq_attr "type" "vfdiv,vfsqrt") ++ (eq_attr "sew" "32"))) ++ "xt_c930_vfp_1") ++ ++(define_insn_reservation "xt_c930_vector_fp_div_sew16" 21 ++ (and (eq_attr "tune" "xt_c930") ++ (and (eq_attr "type" "vfdiv,vfsqrt") ++ (eq_attr "sew" "16"))) ++ "xt_c930_vfp_1") ++ ++;; xt_c930 has a special acceleration for div and mod. When a div/mod instruction ++;; is given after another mod/div and they use a common divisor and divisor, ++;; and no extra cycles are needed for this current div/mod instruction. ++ ++(define_insn_reservation "xt_c930_divmod" 12 ++ (and (eq_attr "tune" "xt_c930") ++ (eq_attr "type" "idiv")) ++ "xt_c930_mx4 * 12") +-- +2.47.3 + diff --git a/gcc.spec b/gcc.spec index 2104b50..3d11971 100644 --- a/gcc.spec +++ b/gcc.spec @@ -1,4 +1,4 @@ -%define anolis_release 1 +%define anolis_release 2 %global DATE 20250731 %global gitrev b3f5a0d53b84ed27cf00cfa2b9c3e2c78935c07d @@ -83,6 +83,95 @@ URL: http://gcc.gnu.org Patch0000: gcc14-libtool-no-rpath.patch +# RISC-V extensions +Patch1001: 1001-Add-support-for-_Bfloat16.patch +Patch1002: 1002-RISC-V-Nan-box-the-result-of-movbf-on-soft-bf16.patch +Patch1003: 1003-RISC-V-Modify-_Bfloat16-to-__bf16.patch +Patch1004: 1004-RISC-V-Add-Zfbfmin-extension-to-the-march-option.patch +Patch1005: 1005-RISC-V-Add-Zvfbfwma-extension-to-the-march-option.patch +Patch1006: 1006-RISC-V-Fix-format-issue-for-trailing-operator-NFC.patch +Patch1007: 1007-RISC-V-Add-vector-type-of-BFloat16-format.patch +Patch1008: 1008-RISC-V-Add-md-files-for-vector-BFloat16.patch +Patch1009: 1009-RISC-V-Add-Zvfbfmin-and-Zvfbfwma-intrinsic.patch +Patch1010: 1010-RISC-V-Fix-ICE-for-vector-single-width-integer-multi.patch +Patch1011: 1011-RISC-V-Minimal-support-for-Zimop-extension.patch +Patch1012: 1012-driver-Fix-multilib_os_dir-and-multiarch_dir-for-tho.patch +Patch1013: 1013-RISC-V-Bugfix-for-RVV-rounding-intrinsic-ICE-in-func.patch +Patch1014: 1014-RISC-V-Add-Zfbfmin-extension.patch +Patch1015: 1015-RISC-V-Use-widening-shift-for-scatter-gather-if-appl.patch +Patch1016: 1016-RISC-V-Introduce-mvector-strict-align.patch +Patch1017: 1017-RISC-V-Disable-misaligned-vector-access-in-hook-risc.patch +Patch1018: 1018-expr-Export-clear_by_pieces.patch +Patch1019: 1019-RISC-V-testsuite-Make-cmo-tests-LTO-safe.patch +Patch1020: 1020-RISC-V-Add-memset-zero-expansion-to-cbo.zero.patch +Patch1021: 1021-RISC-V-Refine-the-condition-for-add-additional-vars-.patch +Patch1022: 1022-Fix-detection-of-store-pair-fusion-cases.patch +Patch1023: 1023-Improve-constant-synthesis-for-constants-with-2-bits.patch +Patch1024: 1024-This-is-almost-exclusively-Jivan-s-work.-His-origina.patch +Patch1025: 1025-Fix-nearbyint-failure-on-rv32-and-formatting-nits.patch +Patch1026: 1026-Don-t-run-new-rounding-tests-on-newlib-risc-v-target.patch +Patch1027: 1027-RISC-V-miscll-comment-fixes-NFC.patch +Patch1028: 1028-So-another-constant-synthesis-improvement.patch +Patch1029: 1029-RISC-V-Document-mcmodel-large.patch +Patch1030: 1030-Enable-inlining-str-by-default.patch +Patch1031: 1031-Reassociate-constants-in-logical-ops.patch +Patch1032: 1032-Some-basic-patterns-for-zbkb-code-generation.patch +Patch1033: 1033-OpenMP-Fix-for-ICE-in-tree-nested.cc.patch +Patch1034: 1034-c-ICE-in-build_deduction_guide-for-invalid-template-.patch +Patch1035: 1035-Fix-rv32-issues-with-recent-zicboz-work.patch +Patch1036: 1036-Avoid-ICE-in-except.cc-on-targets-that-don-t-support.patch +Patch1037: 1037-Fix-PR-c-109958-ICE-taking-the-address-of-bound-stat.patch +Patch1038: 1038-Avoid-ICE-with-pointer-reduction.patch +Patch1039: 1039-RISC-V-Add-basic-Zaamo-and-Zalrsc-support.patch +Patch1040: 1040-RISC-V-Add-Zalrsc-and-Zaamo-testsuite-support.patch +Patch1041: 1041-RISC-V-Add-Zalrsc-amo-op-patterns.patch +Patch1042: 1042-RISC-V-Move-amo-tests-into-subfolder.patch +Patch1043: 1043-RISC-V-Fix-amoadd-call-arguments.patch +Patch1044: 1044-RISC-V-Allow-any-temp-register-to-be-used-in-amo-tes.patch +Patch1045: 1045-RISC-V-Add-support-for-subword-atomic-loads-stores.patch +Patch1046: 1046-RISC-V-Add-configure-check-for-Zaamo-Zalrsc-assemble.patch +Patch1047: 1047-RISC-V-Promote-Zaamo-Zalrsc-to-a-when-using-an-old-b.patch +Patch1048: 1048-RISC-V-Add-dg-remove-option-for-z-extensions.patch +Patch1049: 1049-RISC-V-Rename-amo-testcases.patch +Patch1050: 1050-RISC-V-Consolidate-amo-testcase-variants.patch +Patch1051: 1051-RISC-V-Update-testcase-comments-to-point-to-PSABI-ra.patch +Patch1052: 1052-RISC-V-Add-support-for-Zabha-extension.patch +Patch1053: 1053-RISC-V-Add-support-for-B-standard-extension.patch +Patch1054: 1054-RISC-V-Update-testsuite-to-use-b.patch +Patch1055: 1055-RISC-V-c-implies-zca-and-conditionally-zcf-zcd.patch +Patch1056: 1056-RISC-V-Implement-locality-for-__builtin_prefetch.patch +Patch1057: 1057-RISC-V-Remove-configure-check-for-zabha.patch +Patch1058: 1058-RISC-V-Add-basic-support-for-the-Zacas-extension.patch +Patch1059: 1059-RISC-V-Add-configure-check-for-B-extention-support.patch +Patch1060: 1060-testsuite-fix-dg-compile-typos.patch +Patch1061: 1061-RISC-V-NFC-Do-not-use-zicond-for-pr105314-testcases.patch +Patch1062: 1062-RISC-V-Minimal-support-for-Zimop-extension.patch +Patch1063: 1063-RISC-V-testsuite-xtheadfmemidx-Rename-test-and-add-s.patch +Patch1064: 1064-RISC-V-Add-intrinsic-support-for-the-CMOs-extensions.patch +Patch1065: 1065-RISC-V-Add-intrinsic-cases-for-the-CMOs-extensions.patch +Patch1066: 1066-RISC-V-Add-implication-for-M-extension.patch +Patch1067: 1067-RISC-V-Error-early-with-V-and-no-M-extension.patch +Patch1068: 1068-RISC-V-Fix-program-logic-errors-caused-by-data-trunc.patch +Patch1069: 1069-RISC-V-Add-vector-popcount-clz-ctz.patch +Patch1070: 1070-RISC-V-Fix-the-result-error-caused-by-not-updating-r.patch +Patch1071: 1071-RISC-V-Implement-TARGET_CAN_INLINE_P.patch +Patch1072: 1072-RISC-V-Add-Zicfiss-ISA-extension.patch +Patch1073: 1073-RISC-V-Add-Zicfilp-ISA-extension.patch +Patch1074: 1074-RISC-V-Add-.note.gnu.property-for-ZICFILP-and-ZICFIS.patch +Patch1075: 1075-RISC-V-Add-fcf-protection-full-branch-return-to-enab.patch +Patch1076: 1076-RISC-V-Adjust-LMUL-when-using-maximum-SEW-PR117955.patch +Patch1077: 1077-RISC-V-Eliminate-latter-vsetvl-when-fused.patch +Patch1078: 1078-RISC-V-Fix-ratio-in-vsetvl-fuse-rule-PR115703.patch +Patch1079: 1079-Drop-undesirable-two-instruction-macc-alternatives.patch +Patch1080: 1080-RISC-V-Prefer-Python3-usage-to-avoid-SyntaxError-wit.patch +Patch1081: 1081-RISC-V-Fix-type-validation-for-RVV-fixed-length-vari.patch +Patch1082: 1082-RISC-V-Fix-ICE-for-amo.patch +Patch1083: 1083-RISC-V-Implement-vcpop-intrinsics-for-Zvbb-extension.patch +Patch1084: 1084-RISC-V-Add-missing-overlaps-for-vector-crypto.patch +Patch1085: 1085-RISC-V-Fix-the-wrong-vmul-for-vector-crypto.patch +Patch1086: 1086-RISC-V-XuanTie-Add-xt-c930-support-for-mcpu.patch +Patch1087: 1087-RISC-V-XuanTie-Add-xt-c930-pipeline-description.patch + BuildRequires: binutils >= 2.31 gcc gcc-c++ make gdb BuildRequires: glibc-static BuildRequires: gettext dejagnu bison flex sharutils texinfo texinfo-tex @@ -694,6 +783,95 @@ The %{name}-doc package contains documentation files for %{name}. %patch0 -p 1 +# for RISC-V extensions +%patch1001 -p 1 +%patch1002 -p 1 +%patch1003 -p 1 +%patch1004 -p 1 +%patch1005 -p 1 +%patch1006 -p 1 +%patch1007 -p 1 +%patch1008 -p 1 +%patch1009 -p 1 +%patch1010 -p 1 +%patch1011 -p 1 +%patch1012 -p 1 +%patch1013 -p 1 +%patch1014 -p 1 +%patch1015 -p 1 +%patch1016 -p 1 +%patch1017 -p 1 +%patch1018 -p 1 +%patch1019 -p 1 +%patch1020 -p 1 +%patch1021 -p 1 +%patch1022 -p 1 +%patch1023 -p 1 +%patch1024 -p 1 +%patch1025 -p 1 +%patch1026 -p 1 +%patch1027 -p 1 +%patch1028 -p 1 +%patch1029 -p 1 +%patch1030 -p 1 +%patch1031 -p 1 +%patch1032 -p 1 +%patch1033 -p 1 +%patch1034 -p 1 +%patch1035 -p 1 +%patch1036 -p 1 +%patch1037 -p 1 +%patch1038 -p 1 +%patch1039 -p 1 +%patch1040 -p 1 +%patch1041 -p 1 +%patch1042 -p 1 +%patch1043 -p 1 +%patch1044 -p 1 +%patch1045 -p 1 +%patch1046 -p 1 +%patch1047 -p 1 +%patch1048 -p 1 +%patch1049 -p 1 +%patch1050 -p 1 +%patch1051 -p 1 +%patch1052 -p 1 +%patch1053 -p 1 +%patch1054 -p 1 +%patch1055 -p 1 +%patch1056 -p 1 +%patch1057 -p 1 +%patch1058 -p 1 +%patch1059 -p 1 +%patch1060 -p 1 +%patch1061 -p 1 +%patch1062 -p 1 +%patch1063 -p 1 +%patch1064 -p 1 +%patch1065 -p 1 +%patch1066 -p 1 +%patch1067 -p 1 +%patch1068 -p 1 +%patch1069 -p 1 +%patch1070 -p 1 +%patch1071 -p 1 +%patch1072 -p 1 +%patch1073 -p 1 +%patch1074 -p 1 +%patch1075 -p 1 +%patch1076 -p 1 +%patch1077 -p 1 +%patch1078 -p 1 +%patch1079 -p 1 +%patch1080 -p 1 +%patch1081 -p 1 +%patch1082 -p 1 +%patch1083 -p 1 +%patch1084 -p 1 +%patch1085 -p 1 +%patch1086 -p 1 +%patch1087 -p 1 + rm -f libphobos/testsuite/libphobos.gc/forkgc2.d echo 'Anolis OS %{version}-%{anolis_release}' > gcc/DEV-PHASE @@ -2436,5 +2614,8 @@ end %changelog +* Fri Aug 1 2025 Weisson - 14.3.0-2 +- Add RISC-V ISA extensions. + * Thu Jul 31 2025 Weisson - 14.3.0-1 - Create code base from gcc-14.3.0. -- Gitee