From c07772ab6d2eeac852d90e3267bda44b3a86afe5 Mon Sep 17 00:00:00 2001 From: limeidan Date: Fri, 27 Oct 2023 14:37:11 +0800 Subject: [PATCH] LoongArch64: add support for RegABI, and add new relocations, bug fixes. --- ...time-internal-atomic-Implementing-xc.patch | 53 + ...time-internal-atomic-Implementing-xa.patch | 54 + ...time-internal-atomic-Implementing-An.patch | 91 + ...-loong64-correct-the-instruction-for.patch | 76 + ...-loong64-recheck-jump-offset-boundar.patch | 108 + ...l-loong64-correct-the-glibc-dynamic-.patch | 29 + ...l-loadelf-correct-the-relocation-siz.patch | 34 + ...internal-runtime-change-the-register.patch | 3008 +++++++++++++++++ ...ABI-register-definations-for-loong64.patch | 74 + ...internal-runtime-change-registers-on.patch | 402 +++ ...-abi-define-loong64-regABI-constants.patch | 39 + ...rnal-add-register-info-for-loong64-r.patch | 73 + ...rnal-add-spill-support-for-loong64-r.patch | 78 + ...-cmd-compile-update-loong64-CALL-ops.patch | 75 + ...ff-device-as-ABIInternal-for-loong64.patch | 58 + ...regABI-and-add-spill-functions-in-ru.patch | 448 +++ ...add-reflect-support-for-regABI-on-lo.patch | 130 + ...-add-regABI-support-in-bytealg-funct.patch | 304 ++ ...BI-support-in-memclr-and-memmove-fun.patch | 92 + ...-set-morestack-arg-spilling-and-rega.patch | 57 + ...d-compile-fix-If-lowering-on-loong64.patch | 89 + ...-syscall-use-ABIInternal-for-Syscall.patch | 84 + ...rnal-buildcfg-enable-regABI-on-loong.patch | 66 + ...ernal-buildcfg-always-enable-registe.patch | 59 + ...ong64-non-register-ABI-fallback-path.patch | 493 +++ ...-loong64-using-LookupABI-to-find-duf.patch | 33 + ...-link-unify-the-relocation-naming-st.patch | 409 +++ ...l-loadelf-remove-useless-relocation-.patch | 31 + ...l-loadelf-add-additional-relocations.patch | 39 + ...-relocations-numbered-101-to-109-for.patch | 86 + ...cations-numbered-101-to-109-for-loon.patch | 43 + golang.spec | 69 +- 32 files changed, 6782 insertions(+), 2 deletions(-) create mode 100644 0063-cmd-compiler-runtime-internal-atomic-Implementing-xc.patch create mode 100644 0064-cmd-compiler-runtime-internal-atomic-Implementing-xa.patch create mode 100644 0065-cmd-compiler-runtime-internal-atomic-Implementing-An.patch create mode 100644 0066-cmd-internal-obj-loong64-correct-the-instruction-for.patch create mode 100644 0067-cmd-internal-obj-loong64-recheck-jump-offset-boundar.patch create mode 100644 0068-cmd-link-internal-loong64-correct-the-glibc-dynamic-.patch create mode 100644 0069-cmd-link-internal-loadelf-correct-the-relocation-siz.patch create mode 100644 0070-cmd-compile-cmd-internal-runtime-change-the-register.patch create mode 100644 0071-cmd-compile-add-ABI-register-definations-for-loong64.patch create mode 100644 0072-cmd-compile-cmd-internal-runtime-change-registers-on.patch create mode 100644 0073-internal-abi-define-loong64-regABI-constants.patch create mode 100644 0074-cmd-compile-internal-add-register-info-for-loong64-r.patch create mode 100644 0075-cmd-compile-internal-add-spill-support-for-loong64-r.patch create mode 100644 0076-cmd-compile-update-loong64-CALL-ops.patch create mode 100644 0077-runtime-make-duff-device-as-ABIInternal-for-loong64.patch create mode 100644 0078-runtime-support-regABI-and-add-spill-functions-in-ru.patch create mode 100644 0079-reflect-runtime-add-reflect-support-for-regABI-on-lo.patch create mode 100644 0080-internal-bytealg-add-regABI-support-in-bytealg-funct.patch create mode 100644 0081-runtime-add-regABI-support-in-memclr-and-memmove-fun.patch create mode 100644 0082-cmd-internal-obj-set-morestack-arg-spilling-and-rega.patch create mode 100644 0083-cmd-compile-fix-If-lowering-on-loong64.patch create mode 100644 0084-runtime-internal-syscall-use-ABIInternal-for-Syscall.patch create mode 100644 0085-cmd-compile-internal-buildcfg-enable-regABI-on-loong.patch create mode 100644 0086-internal-abi-internal-buildcfg-always-enable-registe.patch create mode 100644 0087-all-delete-loong64-non-register-ABI-fallback-path.patch create mode 100644 0088-cmd-internal-obj-loong64-using-LookupABI-to-find-duf.patch create mode 100644 0089-cmd-internal-cmd-link-unify-the-relocation-naming-st.patch create mode 100644 0090-cmd-link-internal-loadelf-remove-useless-relocation-.patch create mode 100644 0091-cmd-link-internal-loadelf-add-additional-relocations.patch create mode 100644 0092-cmd-link-add-new-relocations-numbered-101-to-109-for.patch create mode 100644 0093-api-add-new-relocations-numbered-101-to-109-for-loon.patch diff --git a/0063-cmd-compiler-runtime-internal-atomic-Implementing-xc.patch b/0063-cmd-compiler-runtime-internal-atomic-Implementing-xc.patch new file mode 100644 index 0000000..43a338f --- /dev/null +++ b/0063-cmd-compiler-runtime-internal-atomic-Implementing-xc.patch @@ -0,0 +1,53 @@ +From b8c48ca3b93279f5a20006695eebe94ce604c92b Mon Sep 17 00:00:00 2001 +From: Guoqi Chen +Date: Thu, 15 Jun 2023 12:34:55 +0800 +Subject: [PATCH 01/30] cmd/compiler,runtime/internal/atomic: Implementing + xchg{,64} using amswapdb{w,d} on loong64 + +Change-Id: If9cb20c2388b0e5de012d01ce45c49a80c902947 +--- + src/cmd/compile/internal/loong64/ssa.go | 4 ++-- + src/runtime/internal/atomic/atomic_loong64.s | 4 ++-- + 2 files changed, 4 insertions(+), 4 deletions(-) + +diff --git a/src/cmd/compile/internal/loong64/ssa.go b/src/cmd/compile/internal/loong64/ssa.go +index b992024bca..d3fe1d1441 100644 +--- a/src/cmd/compile/internal/loong64/ssa.go ++++ b/src/cmd/compile/internal/loong64/ssa.go +@@ -495,9 +495,9 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { + s.Prog(loong64.ADBAR) + case ssa.OpLOONG64LoweredAtomicExchange32, ssa.OpLOONG64LoweredAtomicExchange64: + // AMSWAPx Rarg1, (Rarg0), Rout +- amswapx := loong64.AAMSWAPV ++ amswapx := loong64.AAMSWAPDBV + if v.Op == ssa.OpLOONG64LoweredAtomicExchange32 { +- amswapx = loong64.AAMSWAPW ++ amswapx = loong64.AAMSWAPDBW + } + p := s.Prog(amswapx) + p.From.Type = obj.TYPE_REG +diff --git a/src/runtime/internal/atomic/atomic_loong64.s b/src/runtime/internal/atomic/atomic_loong64.s +index 1d4d4b4b37..e3f2d07858 100644 +--- a/src/runtime/internal/atomic/atomic_loong64.s ++++ b/src/runtime/internal/atomic/atomic_loong64.s +@@ -120,7 +120,7 @@ TEXT ·Xadd64(SB), NOSPLIT, $0-24 + TEXT ·Xchg(SB), NOSPLIT, $0-20 + MOVV ptr+0(FP), R4 + MOVW new+8(FP), R5 +- AMSWAPW R5, (R4), R6 ++ AMSWAPDBW R5, (R4), R6 + MOVW R6, ret+16(FP) + RET + +@@ -128,7 +128,7 @@ TEXT ·Xchg(SB), NOSPLIT, $0-20 + TEXT ·Xchg64(SB), NOSPLIT, $0-24 + MOVV ptr+0(FP), R4 + MOVV new+8(FP), R5 +- AMSWAPV R5, (R4), R6 ++ AMSWAPDBV R5, (R4), R6 + MOVV R6, ret+16(FP) + RET + +-- +2.38.1 + diff --git a/0064-cmd-compiler-runtime-internal-atomic-Implementing-xa.patch b/0064-cmd-compiler-runtime-internal-atomic-Implementing-xa.patch new file mode 100644 index 0000000..93a228b --- /dev/null +++ b/0064-cmd-compiler-runtime-internal-atomic-Implementing-xa.patch @@ -0,0 +1,54 @@ +From c0349ed75465b9cc9ba428591e0bb6e6f5477fc7 Mon Sep 17 00:00:00 2001 +From: Guoqi Chen +Date: Thu, 15 Jun 2023 12:37:00 +0800 +Subject: [PATCH 02/30] cmd/compiler,runtime/internal/atomic: Implementing + xadd{,64} using amadddb{w,d} on loong64 + +Change-Id: Ie1f2f1e6861c1805cc562f87cb7ee13dba4f63d1 +--- + src/cmd/compile/internal/loong64/ssa.go | 4 ++-- + src/runtime/internal/atomic/atomic_loong64.s | 4 ++-- + 2 files changed, 4 insertions(+), 4 deletions(-) + +diff --git a/src/cmd/compile/internal/loong64/ssa.go b/src/cmd/compile/internal/loong64/ssa.go +index d3fe1d1441..f81152c7b5 100644 +--- a/src/cmd/compile/internal/loong64/ssa.go ++++ b/src/cmd/compile/internal/loong64/ssa.go +@@ -517,10 +517,10 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { + case ssa.OpLOONG64LoweredAtomicAdd32, ssa.OpLOONG64LoweredAtomicAdd64: + // AMADDx Rarg1, (Rarg0), Rout + // ADDxU Rarg1, Rout, Rout +- amaddx := loong64.AAMADDV ++ amaddx := loong64.AAMADDDBV + addx := loong64.AADDVU + if v.Op == ssa.OpLOONG64LoweredAtomicAdd32 { +- amaddx = loong64.AAMADDW ++ amaddx = loong64.AAMADDDBW + addx = loong64.AADDU + } + p := s.Prog(amaddx) +diff --git a/src/runtime/internal/atomic/atomic_loong64.s b/src/runtime/internal/atomic/atomic_loong64.s +index e3f2d07858..531993e8b7 100644 +--- a/src/runtime/internal/atomic/atomic_loong64.s ++++ b/src/runtime/internal/atomic/atomic_loong64.s +@@ -102,7 +102,7 @@ TEXT ·Casp1(SB), NOSPLIT, $0-25 + TEXT ·Xadd(SB), NOSPLIT, $0-20 + MOVV ptr+0(FP), R4 + MOVW delta+8(FP), R5 +- AMADDW R5, (R4), R6 ++ AMADDDBW R5, (R4), R6 + ADDU R6, R5, R4 + MOVW R4, ret+16(FP) + RET +@@ -111,7 +111,7 @@ TEXT ·Xadd(SB), NOSPLIT, $0-20 + TEXT ·Xadd64(SB), NOSPLIT, $0-24 + MOVV ptr+0(FP), R4 + MOVV delta+8(FP), R5 +- AMADDV R5, (R4), R6 ++ AMADDDBV R5, (R4), R6 + ADDVU R6, R5, R4 + MOVV R4, ret+16(FP) + RET +-- +2.38.1 + diff --git a/0065-cmd-compiler-runtime-internal-atomic-Implementing-An.patch b/0065-cmd-compiler-runtime-internal-atomic-Implementing-An.patch new file mode 100644 index 0000000..57fec4d --- /dev/null +++ b/0065-cmd-compiler-runtime-internal-atomic-Implementing-An.patch @@ -0,0 +1,91 @@ +From 6556d808f7e31d8b64c4fdb37cd8f543dcd2ee3e Mon Sep 17 00:00:00 2001 +From: Guoqi Chen +Date: Thu, 15 Jun 2023 12:40:55 +0800 +Subject: [PATCH 03/30] cmd/compiler,runtime/internal/atomic: Implementing + {And,Or}{32,8} using am{and,or}dbw on loong64 + +Change-Id: I15a3adaf97a90deaf5fc2faf66e912431f20c852 +--- + src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go | 4 ++-- + src/cmd/compile/internal/ssa/opGen.go | 4 ++-- + src/runtime/internal/atomic/atomic_loong64.s | 8 ++++---- + 3 files changed, 8 insertions(+), 8 deletions(-) + +diff --git a/src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go b/src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go +index 8043ad2aa7..14ffb542cf 100644 +--- a/src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go ++++ b/src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go +@@ -382,8 +382,8 @@ func init() { + + // Atomic 32 bit AND/OR. + // *arg0 &= (|=) arg1. arg2=mem. returns nil. +- {name: "LoweredAtomicAnd32", argLength: 3, reg: gpxchg, asm: "AMANDW", faultOnNilArg0: true, hasSideEffects: true}, +- {name: "LoweredAtomicOr32", argLength: 3, reg: gpxchg, asm: "AMORW", faultOnNilArg0: true, hasSideEffects: true}, ++ {name: "LoweredAtomicAnd32", argLength: 3, reg: gpxchg, asm: "AMANDDBW", faultOnNilArg0: true, hasSideEffects: true}, ++ {name: "LoweredAtomicOr32", argLength: 3, reg: gpxchg, asm: "AMORDBW", faultOnNilArg0: true, hasSideEffects: true}, + + // atomic add. + // *arg0 += arg1. arg2=mem. returns . +diff --git a/src/cmd/compile/internal/ssa/opGen.go b/src/cmd/compile/internal/ssa/opGen.go +index 6ba5fe891a..ff0e1c6ca7 100644 +--- a/src/cmd/compile/internal/ssa/opGen.go ++++ b/src/cmd/compile/internal/ssa/opGen.go +@@ -24408,7 +24408,7 @@ var opcodeTable = [...]opInfo{ + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, +- asm: loong64.AAMANDW, ++ asm: loong64.AAMANDDBW, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 +@@ -24424,7 +24424,7 @@ var opcodeTable = [...]opInfo{ + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, +- asm: loong64.AAMORW, ++ asm: loong64.AAMORDBW, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 +diff --git a/src/runtime/internal/atomic/atomic_loong64.s b/src/runtime/internal/atomic/atomic_loong64.s +index 531993e8b7..c36b603793 100644 +--- a/src/runtime/internal/atomic/atomic_loong64.s ++++ b/src/runtime/internal/atomic/atomic_loong64.s +@@ -191,7 +191,7 @@ TEXT ·Or8(SB), NOSPLIT, $0-9 + SLLV $3, R7 + // Shift val for aligned ptr. R5 = val << R4 + SLLV R7, R5 +- AMORW R5, (R6), R0 ++ AMORDBW R5, (R6), R0 + RET + + // void And8(byte volatile*, byte); +@@ -210,21 +210,21 @@ TEXT ·And8(SB), NOSPLIT, $0-9 + SLLV R7, R8 + NOR R0, R8 + OR R8, R5 +- AMANDW R5, (R6), R0 ++ AMANDDBW R5, (R6), R0 + RET + + // func Or(addr *uint32, v uint32) + TEXT ·Or(SB), NOSPLIT, $0-12 + MOVV ptr+0(FP), R4 + MOVW val+8(FP), R5 +- AMORW R5, (R4), R0 ++ AMORDBW R5, (R4), R0 + RET + + // func And(addr *uint32, v uint32) + TEXT ·And(SB), NOSPLIT, $0-12 + MOVV ptr+0(FP), R4 + MOVW val+8(FP), R5 +- AMANDW R5, (R4), R0 ++ AMANDDBW R5, (R4), R0 + RET + + // uint32 runtime∕internal∕atomic·Load(uint32 volatile* ptr) +-- +2.38.1 + diff --git a/0066-cmd-internal-obj-loong64-correct-the-instruction-for.patch b/0066-cmd-internal-obj-loong64-correct-the-instruction-for.patch new file mode 100644 index 0000000..a8409f1 --- /dev/null +++ b/0066-cmd-internal-obj-loong64-correct-the-instruction-for.patch @@ -0,0 +1,76 @@ +From aaf5a5199e2f2babf26c0ed0445a67beefdca60f Mon Sep 17 00:00:00 2001 +From: chenguoqi +Date: Thu, 27 Jul 2023 15:57:16 +0800 +Subject: [PATCH 04/30] cmd/internal/obj/loong64: correct the instruction + format of plan9 assembly NOOP + +Signed-off-by: chenguoqi +Change-Id: I54bcf1b6a75715a351471195096695ab8e529bd9 +--- + src/cmd/internal/obj/loong64/asm.go | 27 +++++++++++++++++++++------ + 1 file changed, 21 insertions(+), 6 deletions(-) + +diff --git a/src/cmd/internal/obj/loong64/asm.go b/src/cmd/internal/obj/loong64/asm.go +index c2efe0eef1..70a804f7ea 100644 +--- a/src/cmd/internal/obj/loong64/asm.go ++++ b/src/cmd/internal/obj/loong64/asm.go +@@ -591,7 +591,7 @@ func span0(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { + v := pcAlignPadLength(p.Pc, alignedValue, c.ctxt) + for i = 0; i < int32(v/4); i++ { + // emit ANOOP instruction by the padding size +- c.ctxt.Arch.ByteOrder.PutUint32(bp, c.opi(ANOOP)) ++ c.ctxt.Arch.ByteOrder.PutUint32(bp, c.op0(ANOOP)) + bp = bp[4:] + } + continue +@@ -1331,7 +1331,13 @@ func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) { + o1 = OP_12IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.To.Reg)) + + case 5: // syscall +- o1 = c.opi(p.As) ++ switch p.As { ++ case ANOOP: ++ o1 = c.op0(p.As) ++ default: ++ v := c.regoff(&p.From) ++ o1 = OP_I(c.opi(p.As), uint32(v)) ++ } + + case 6: // beq r1,[r2],sbra + v := int32(0) +@@ -2065,6 +2071,18 @@ func (c *ctxt0) oprr(a obj.As) uint32 { + return 0 + } + ++func (c *ctxt0) op0(a obj.As) uint32 { ++ switch a { ++ case ANOOP: ++ // andi r0, r0, 0 ++ return 0x03400000 ++ } ++ ++ c.ctxt.Diag("bad op0 opcode %v", a) ++ ++ return 0 ++} ++ + func (c *ctxt0) opi(a obj.As) uint32 { + switch a { + case ASYSCALL: +@@ -2073,12 +2091,9 @@ func (c *ctxt0) opi(a obj.As) uint32 { + return 0x54 << 15 + case ADBAR: + return 0x70e4 << 15 +- case ANOOP: +- // andi r0, r0, 0 +- return 0x03400000 + } + +- c.ctxt.Diag("bad ic opcode %v", a) ++ c.ctxt.Diag("bad opi opcode %v", a) + + return 0 + } +-- +2.38.1 + diff --git a/0067-cmd-internal-obj-loong64-recheck-jump-offset-boundar.patch b/0067-cmd-internal-obj-loong64-recheck-jump-offset-boundar.patch new file mode 100644 index 0000000..58790eb --- /dev/null +++ b/0067-cmd-internal-obj-loong64-recheck-jump-offset-boundar.patch @@ -0,0 +1,108 @@ +From a4221e4ce2563eceb06d9b2d1eccf1430f0282ad Mon Sep 17 00:00:00 2001 +From: chenguoqi +Date: Thu, 17 Aug 2023 08:35:15 +0800 +Subject: [PATCH 05/30] cmd/internal/obj/loong64: recheck jump offset boundary + after auto-aligning loop heads + +After the alignment of the loop header is performed, the offset of the checked +conditional branch instruction may overflow, so it needs to be checked again. + +When checking whether the offset of the branch jump instruction overflows, it +can be classified and processed according to the range of the immediate field +of the specific instruction, which can reduce the introduction of unnecessary +jump instructions. + +Fixes #61819 + +Change-Id: Ica4c4ade43bf106c7035a1c02b89d3347a414b41 +--- + src/cmd/internal/obj/loong64/asm.go | 32 ++++++++++++++++++----------- + 1 file changed, 20 insertions(+), 12 deletions(-) + +diff --git a/src/cmd/internal/obj/loong64/asm.go b/src/cmd/internal/obj/loong64/asm.go +index 70a804f7ea..34b0ff94e4 100644 +--- a/src/cmd/internal/obj/loong64/asm.go ++++ b/src/cmd/internal/obj/loong64/asm.go +@@ -495,18 +495,14 @@ func span0(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { + * generate extra passes putting branches + * around jmps to fix. this is rare. + */ +- bflag := 1 +- +- var otxt int64 +- var q *obj.Prog + iters := 0 +- for bflag != 0 { ++ for { ++ rescan := false + iters++ + if iters > 200 { + ctxt.Diag("layout pass doesn't converge") + break + } +- bflag = 0 + pc = 0 + prev := c.cursym.Func().Text + for p = prev.Link; p != nil; prev, p = p, p.Link { +@@ -515,9 +511,16 @@ func span0(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { + + // very large conditional branches + if o.type_ == 6 && p.To.Target() != nil { +- otxt = p.To.Target().Pc - pc +- if otxt < -(1<<17)+10 || otxt >= (1<<17)-10 { +- q = c.newprog() ++ otxt := p.To.Target().Pc - pc ++ bound := int64(1 << (18 - 1)) ++ ++ switch p.As { ++ case -ABEQ, -ABNE, ABFPT, ABFPF: ++ bound = int64(1 << (23 - 1)) ++ } ++ ++ if otxt < -bound || otxt >= bound { ++ q := c.newprog() + q.Link = p.Link + p.Link = q + q.As = AJMP +@@ -532,14 +535,14 @@ func span0(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { + q.Pos = p.Pos + q.To.Type = obj.TYPE_BRANCH + q.To.SetTarget(q.Link.Link) +- bflag = 1 ++ rescan = true + } + } + + // loop heads that need padding + // prepend a PCALIGN $16 to such progs + if p.Mark&branchLoopHead != 0 && pc&(loopAlign-1) != 0 { +- q = c.newprog() ++ q := c.newprog() + prev.Link = q + q.Link = p + q.As = obj.APCALIGN +@@ -548,7 +551,7 @@ func span0(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { + // don't associate the synthesized PCALIGN + // with the original source position + // q.Pos = p.Pos +- bflag = 1 ++ rescan = true + } + + m = int(o.size) +@@ -569,7 +572,12 @@ func span0(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { + } + + c.cursym.Size = pc ++ ++ if !rescan { ++ break ++ } + } ++ + pc += -pc & (FuncAlign - 1) + c.cursym.Size = pc + +-- +2.38.1 + diff --git a/0068-cmd-link-internal-loong64-correct-the-glibc-dynamic-.patch b/0068-cmd-link-internal-loong64-correct-the-glibc-dynamic-.patch new file mode 100644 index 0000000..ce5b037 --- /dev/null +++ b/0068-cmd-link-internal-loong64-correct-the-glibc-dynamic-.patch @@ -0,0 +1,29 @@ +From 89943b95e053ed6e8adcbf0cd9e668608b33cdc9 Mon Sep 17 00:00:00 2001 +From: limeidan +Date: Fri, 8 Sep 2023 00:37:17 +0800 +Subject: [PATCH 06/30] cmd/link/internal/loong64: correct the glibc dynamic + linker path. + +Ref: https://loongson.github.io/LoongArch-Documentation/LoongArch-ELF-ABI-EN.html#_program_interpreter_path + +Change-Id: Ic2598110cc091362cb09f877b6b86433cacf32c6 +--- + src/cmd/link/internal/loong64/obj.go | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/cmd/link/internal/loong64/obj.go b/src/cmd/link/internal/loong64/obj.go +index 4865c695b9..c82504176e 100644 +--- a/src/cmd/link/internal/loong64/obj.go ++++ b/src/cmd/link/internal/loong64/obj.go +@@ -31,7 +31,7 @@ func Init() (*sys.Arch, ld.Arch) { + Machoreloc1: machoreloc1, + Gentext: gentext, + +- Linuxdynld: "/lib64/ld.so.1", ++ Linuxdynld: "/lib64/ld-linux-loongarch-lp64d.so.1", + LinuxdynldMusl: "/lib64/ld-musl-loongarch.so.1", + Freebsddynld: "XXX", + Openbsddynld: "XXX", +-- +2.38.1 + diff --git a/0069-cmd-link-internal-loadelf-correct-the-relocation-siz.patch b/0069-cmd-link-internal-loadelf-correct-the-relocation-siz.patch new file mode 100644 index 0000000..85e55df --- /dev/null +++ b/0069-cmd-link-internal-loadelf-correct-the-relocation-siz.patch @@ -0,0 +1,34 @@ +From 9cb2c9498325eda8ce76a22e16fab5916ab4def0 Mon Sep 17 00:00:00 2001 +From: limeidan +Date: Thu, 14 Sep 2023 20:11:07 +0800 +Subject: [PATCH 07/30] cmd/link/internal/loadelf: correct the relocation size + of R_LARCH_64 + +(cherry picked from commit 55c5e3a84e77430b692cdac16082ab1b46a232ef) +Change-Id: I693dc0115a030cee202e5ece39563fe80c6782b3 +--- + src/cmd/link/internal/loadelf/ldelf.go | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/src/cmd/link/internal/loadelf/ldelf.go b/src/cmd/link/internal/loadelf/ldelf.go +index 7ac7699996..156d9a5616 100644 +--- a/src/cmd/link/internal/loadelf/ldelf.go ++++ b/src/cmd/link/internal/loadelf/ldelf.go +@@ -1007,11 +1007,13 @@ func relSize(arch *sys.Arch, pn string, elftype uint32) (uint8, uint8, error) { + LOONG64 | uint32(elf.R_LARCH_SOP_PUSH_ABSOLUTE)<<16, + LOONG64 | uint32(elf.R_LARCH_MARK_LA)<<16, + LOONG64 | uint32(elf.R_LARCH_SOP_POP_32_S_0_10_10_16_S2)<<16, +- LOONG64 | uint32(elf.R_LARCH_64)<<16, + LOONG64 | uint32(elf.R_LARCH_MARK_PCREL)<<16, + LOONG64 | uint32(elf.R_LARCH_32_PCREL)<<16: + return 4, 4, nil + ++ case LOONG64 | uint32(elf.R_LARCH_64)<<16: ++ return 8, 8, nil ++ + case S390X | uint32(elf.R_390_8)<<16: + return 1, 1, nil + +-- +2.38.1 + diff --git a/0070-cmd-compile-cmd-internal-runtime-change-the-register.patch b/0070-cmd-compile-cmd-internal-runtime-change-the-register.patch new file mode 100644 index 0000000..206d8b8 --- /dev/null +++ b/0070-cmd-compile-cmd-internal-runtime-change-the-register.patch @@ -0,0 +1,3008 @@ +From e31062143c39a13705b26c653942ea78049d8beb Mon Sep 17 00:00:00 2001 +From: Guoqi Chen +Date: Thu, 17 Aug 2023 03:58:10 +0800 +Subject: [PATCH 08/30] cmd/compile, cmd/internal, runtime: change the + registers used by the duff device for loong64 + +Add R21 to the allocatable registers, use R20 and R21 in duff +device. This CL is in preparation for subsequent regABI support. + +Change-Id: I81384ddf769520f005fb9da1d24e98801e9a64d0 +--- + src/cmd/compile/internal/loong64/ssa.go | 2 +- + .../compile/internal/ssa/_gen/LOONG64Ops.go | 44 +- + src/cmd/compile/internal/ssa/opGen.go | 438 +++--- + src/cmd/internal/obj/loong64/a.out.go | 8 +- + src/runtime/duff_loong64.s | 1280 ++++++++--------- + src/runtime/mkduff.go | 10 +- + 6 files changed, 891 insertions(+), 891 deletions(-) + +diff --git a/src/cmd/compile/internal/loong64/ssa.go b/src/cmd/compile/internal/loong64/ssa.go +index f81152c7b5..68fc5d105c 100644 +--- a/src/cmd/compile/internal/loong64/ssa.go ++++ b/src/cmd/compile/internal/loong64/ssa.go +@@ -362,7 +362,7 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { + p.To.Type = obj.TYPE_REG + p.To.Reg = v.Reg() + case ssa.OpLOONG64DUFFZERO: +- // runtime.duffzero expects start address in R19 ++ // runtime.duffzero expects start address in R20 + p := s.Prog(obj.ADUFFZERO) + p.To.Type = obj.TYPE_MEM + p.To.Name = obj.NAME_EXTERN +diff --git a/src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go b/src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go +index 14ffb542cf..d2beaa1193 100644 +--- a/src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go ++++ b/src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go +@@ -123,7 +123,7 @@ func init() { + + // Common individual register masks + var ( +- gp = buildReg("R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31") // R1 is LR, R2 is thread pointer, R3 is stack pointer, R21-unused, R22 is g, R30 is REGTMP ++ gp = buildReg("R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31") // R1 is LR, R2 is thread pointer, R3 is stack pointer, R22 is g, R30 is REGTMP + gpg = gp | buildReg("g") + gpsp = gp | buildReg("SP") + gpspg = gpg | buildReg("SP") +@@ -283,21 +283,21 @@ func init() { + // arg1 = mem + // auxint = offset into duffzero code to start executing + // returns mem +- // R19 aka loong64.REGRT1 changed as side effect ++ // R20 aka loong64.REGRT1 changed as side effect + { + name: "DUFFZERO", + aux: "Int64", + argLength: 2, + reg: regInfo{ +- inputs: []regMask{buildReg("R19")}, +- clobbers: buildReg("R19 R1"), ++ inputs: []regMask{buildReg("R20")}, ++ clobbers: buildReg("R20 R1"), + }, + faultOnNilArg0: true, + }, + + // duffcopy +- // arg0 = address of dst memory (in R20, changed as side effect) REGRT2 +- // arg1 = address of src memory (in R19, changed as side effect) REGRT1 ++ // arg0 = address of dst memory (in R21, changed as side effect) REGRT2 ++ // arg1 = address of src memory (in R20, changed as side effect) REGRT1 + // arg2 = mem + // auxint = offset into duffcopy code to start executing + // returns mem +@@ -306,53 +306,53 @@ func init() { + aux: "Int64", + argLength: 3, + reg: regInfo{ +- inputs: []regMask{buildReg("R20"), buildReg("R19")}, +- clobbers: buildReg("R19 R20 R1"), ++ inputs: []regMask{buildReg("R21"), buildReg("R20")}, ++ clobbers: buildReg("R20 R21 R1"), + }, + faultOnNilArg0: true, + faultOnNilArg1: true, + }, + + // large or unaligned zeroing +- // arg0 = address of memory to zero (in R19, changed as side effect) ++ // arg0 = address of memory to zero (in R20, changed as side effect) + // arg1 = address of the last element to zero + // arg2 = mem + // auxint = alignment + // returns mem +- // MOVx R0, (R19) +- // ADDV $sz, R19 +- // BGEU Rarg1, R19, -2(PC) ++ // MOVx R0, (R20) ++ // ADDV $sz, R20 ++ // BGEU Rarg1, R20, -2(PC) + { + name: "LoweredZero", + aux: "Int64", + argLength: 3, + reg: regInfo{ +- inputs: []regMask{buildReg("R19"), gp}, +- clobbers: buildReg("R19"), ++ inputs: []regMask{buildReg("R20"), gp}, ++ clobbers: buildReg("R20"), + }, + typ: "Mem", + faultOnNilArg0: true, + }, + + // large or unaligned move +- // arg0 = address of dst memory (in R20, changed as side effect) +- // arg1 = address of src memory (in R19, changed as side effect) ++ // arg0 = address of dst memory (in R21, changed as side effect) ++ // arg1 = address of src memory (in R20, changed as side effect) + // arg2 = address of the last element of src + // arg3 = mem + // auxint = alignment + // returns mem +- // MOVx (R19), Rtmp +- // MOVx Rtmp, (R20) +- // ADDV $sz, R19 ++ // MOVx (R20), Rtmp ++ // MOVx Rtmp, (R21) + // ADDV $sz, R20 +- // BGEU Rarg2, R19, -4(PC) ++ // ADDV $sz, R21 ++ // BGEU Rarg2, R20, -4(PC) + { + name: "LoweredMove", + aux: "Int64", + argLength: 4, + reg: regInfo{ +- inputs: []regMask{buildReg("R20"), buildReg("R19"), gp}, +- clobbers: buildReg("R19 R20"), ++ inputs: []regMask{buildReg("R21"), buildReg("R20"), gp}, ++ clobbers: buildReg("R20 R21"), + }, + typ: "Mem", + faultOnNilArg0: true, +diff --git a/src/cmd/compile/internal/ssa/opGen.go b/src/cmd/compile/internal/ssa/opGen.go +index ff0e1c6ca7..63c8cc329a 100644 +--- a/src/cmd/compile/internal/ssa/opGen.go ++++ b/src/cmd/compile/internal/ssa/opGen.go +@@ -22867,11 +22867,11 @@ var opcodeTable = [...]opInfo{ + asm: loong64.AADDVU, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 +- {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -22882,10 +22882,10 @@ var opcodeTable = [...]opInfo{ + asm: loong64.AADDVU, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 1072693244}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1073741820}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -22895,11 +22895,11 @@ var opcodeTable = [...]opInfo{ + asm: loong64.ASUBVU, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 +- {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -22910,10 +22910,10 @@ var opcodeTable = [...]opInfo{ + asm: loong64.ASUBVU, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -22924,11 +22924,11 @@ var opcodeTable = [...]opInfo{ + asm: loong64.AMULV, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 +- {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -22939,11 +22939,11 @@ var opcodeTable = [...]opInfo{ + asm: loong64.AMULHV, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 +- {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -22954,11 +22954,11 @@ var opcodeTable = [...]opInfo{ + asm: loong64.AMULHVU, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 +- {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -22968,11 +22968,11 @@ var opcodeTable = [...]opInfo{ + asm: loong64.ADIVV, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 +- {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -22982,11 +22982,11 @@ var opcodeTable = [...]opInfo{ + asm: loong64.ADIVVU, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 +- {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -22996,11 +22996,11 @@ var opcodeTable = [...]opInfo{ + asm: loong64.AREMV, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 +- {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -23010,11 +23010,11 @@ var opcodeTable = [...]opInfo{ + asm: loong64.AREMVU, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 +- {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -23141,11 +23141,11 @@ var opcodeTable = [...]opInfo{ + asm: loong64.AAND, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 +- {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -23156,10 +23156,10 @@ var opcodeTable = [...]opInfo{ + asm: loong64.AAND, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -23170,11 +23170,11 @@ var opcodeTable = [...]opInfo{ + asm: loong64.AOR, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 +- {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -23185,10 +23185,10 @@ var opcodeTable = [...]opInfo{ + asm: loong64.AOR, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -23199,11 +23199,11 @@ var opcodeTable = [...]opInfo{ + asm: loong64.AXOR, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 +- {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -23214,10 +23214,10 @@ var opcodeTable = [...]opInfo{ + asm: loong64.AXOR, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -23228,11 +23228,11 @@ var opcodeTable = [...]opInfo{ + asm: loong64.ANOR, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 +- {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -23243,10 +23243,10 @@ var opcodeTable = [...]opInfo{ + asm: loong64.ANOR, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -23255,10 +23255,10 @@ var opcodeTable = [...]opInfo{ + argLen: 1, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -23320,11 +23320,11 @@ var opcodeTable = [...]opInfo{ + asm: loong64.AMASKEQZ, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 +- {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -23334,11 +23334,11 @@ var opcodeTable = [...]opInfo{ + asm: loong64.AMASKNEZ, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 +- {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -23348,11 +23348,11 @@ var opcodeTable = [...]opInfo{ + asm: loong64.ASLLV, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 +- {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -23363,10 +23363,10 @@ var opcodeTable = [...]opInfo{ + asm: loong64.ASLLV, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -23376,11 +23376,11 @@ var opcodeTable = [...]opInfo{ + asm: loong64.ASRLV, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 +- {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -23391,10 +23391,10 @@ var opcodeTable = [...]opInfo{ + asm: loong64.ASRLV, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -23404,11 +23404,11 @@ var opcodeTable = [...]opInfo{ + asm: loong64.ASRAV, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 +- {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -23419,10 +23419,10 @@ var opcodeTable = [...]opInfo{ + asm: loong64.ASRAV, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -23432,11 +23432,11 @@ var opcodeTable = [...]opInfo{ + asm: loong64.AROTR, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 +- {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -23446,11 +23446,11 @@ var opcodeTable = [...]opInfo{ + asm: loong64.AROTRV, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 +- {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -23461,10 +23461,10 @@ var opcodeTable = [...]opInfo{ + asm: loong64.AROTR, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -23475,10 +23475,10 @@ var opcodeTable = [...]opInfo{ + asm: loong64.AROTRV, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -23488,11 +23488,11 @@ var opcodeTable = [...]opInfo{ + asm: loong64.ASGT, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 +- {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -23503,10 +23503,10 @@ var opcodeTable = [...]opInfo{ + asm: loong64.ASGT, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -23516,11 +23516,11 @@ var opcodeTable = [...]opInfo{ + asm: loong64.ASGTU, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 +- {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -23531,10 +23531,10 @@ var opcodeTable = [...]opInfo{ + asm: loong64.ASGTU, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -23612,7 +23612,7 @@ var opcodeTable = [...]opInfo{ + asm: loong64.AMOVV, + reg: regInfo{ + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -23652,7 +23652,7 @@ var opcodeTable = [...]opInfo{ + {0, 4611686018427387908}, // SP SB + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -23665,10 +23665,10 @@ var opcodeTable = [...]opInfo{ + asm: loong64.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB ++ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -23681,10 +23681,10 @@ var opcodeTable = [...]opInfo{ + asm: loong64.AMOVBU, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB ++ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -23697,10 +23697,10 @@ var opcodeTable = [...]opInfo{ + asm: loong64.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB ++ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -23713,10 +23713,10 @@ var opcodeTable = [...]opInfo{ + asm: loong64.AMOVHU, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB ++ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -23729,10 +23729,10 @@ var opcodeTable = [...]opInfo{ + asm: loong64.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB ++ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -23745,10 +23745,10 @@ var opcodeTable = [...]opInfo{ + asm: loong64.AMOVWU, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB ++ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -23761,10 +23761,10 @@ var opcodeTable = [...]opInfo{ + asm: loong64.AMOVV, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB ++ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -23777,7 +23777,7 @@ var opcodeTable = [...]opInfo{ + asm: loong64.AMOVF, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB ++ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 +@@ -23793,7 +23793,7 @@ var opcodeTable = [...]opInfo{ + asm: loong64.AMOVD, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB ++ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 +@@ -23809,8 +23809,8 @@ var opcodeTable = [...]opInfo{ + asm: loong64.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ +- {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 +- {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB ++ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + }, + }, +@@ -23823,8 +23823,8 @@ var opcodeTable = [...]opInfo{ + asm: loong64.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ +- {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 +- {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB ++ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + }, + }, +@@ -23837,8 +23837,8 @@ var opcodeTable = [...]opInfo{ + asm: loong64.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ +- {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 +- {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB ++ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + }, + }, +@@ -23851,8 +23851,8 @@ var opcodeTable = [...]opInfo{ + asm: loong64.AMOVV, + reg: regInfo{ + inputs: []inputInfo{ +- {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 +- {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB ++ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + }, + }, +@@ -23865,7 +23865,7 @@ var opcodeTable = [...]opInfo{ + asm: loong64.AMOVF, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB ++ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, +@@ -23879,7 +23879,7 @@ var opcodeTable = [...]opInfo{ + asm: loong64.AMOVD, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB ++ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, +@@ -23893,7 +23893,7 @@ var opcodeTable = [...]opInfo{ + asm: loong64.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB ++ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + }, + }, +@@ -23906,7 +23906,7 @@ var opcodeTable = [...]opInfo{ + asm: loong64.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB ++ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + }, + }, +@@ -23919,7 +23919,7 @@ var opcodeTable = [...]opInfo{ + asm: loong64.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB ++ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + }, + }, +@@ -23932,7 +23932,7 @@ var opcodeTable = [...]opInfo{ + asm: loong64.AMOVV, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB ++ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + }, + }, +@@ -23942,10 +23942,10 @@ var opcodeTable = [...]opInfo{ + asm: loong64.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -23955,10 +23955,10 @@ var opcodeTable = [...]opInfo{ + asm: loong64.AMOVBU, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -23968,10 +23968,10 @@ var opcodeTable = [...]opInfo{ + asm: loong64.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -23981,10 +23981,10 @@ var opcodeTable = [...]opInfo{ + asm: loong64.AMOVHU, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -23994,10 +23994,10 @@ var opcodeTable = [...]opInfo{ + asm: loong64.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -24007,10 +24007,10 @@ var opcodeTable = [...]opInfo{ + asm: loong64.AMOVWU, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -24020,10 +24020,10 @@ var opcodeTable = [...]opInfo{ + asm: loong64.AMOVV, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -24033,10 +24033,10 @@ var opcodeTable = [...]opInfo{ + resultInArg0: true, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -24177,7 +24177,7 @@ var opcodeTable = [...]opInfo{ + clobberFlags: true, + call: true, + reg: regInfo{ +- clobbers: 4611686018426339320, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 ++ clobbers: 4611686018427387896, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + { +@@ -24188,7 +24188,7 @@ var opcodeTable = [...]opInfo{ + call: true, + tailCall: true, + reg: regInfo{ +- clobbers: 4611686018426339320, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 ++ clobbers: 4611686018427387896, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + { +@@ -24200,9 +24200,9 @@ var opcodeTable = [...]opInfo{ + reg: regInfo{ + inputs: []inputInfo{ + {1, 268435456}, // R29 +- {0, 1070596092}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644668}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, +- clobbers: 4611686018426339320, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 ++ clobbers: 4611686018427387896, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + { +@@ -24213,9 +24213,9 @@ var opcodeTable = [...]opInfo{ + call: true, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, +- clobbers: 4611686018426339320, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 ++ clobbers: 4611686018427387896, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + { +@@ -24225,9 +24225,9 @@ var opcodeTable = [...]opInfo{ + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 262144}, // R19 ++ {0, 524288}, // R20 + }, +- clobbers: 262146, // R1 R19 ++ clobbers: 524290, // R1 R20 + }, + }, + { +@@ -24238,10 +24238,10 @@ var opcodeTable = [...]opInfo{ + faultOnNilArg1: true, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 524288}, // R20 +- {1, 262144}, // R19 ++ {0, 1048576}, // R21 ++ {1, 524288}, // R20 + }, +- clobbers: 786434, // R1 R19 R20 ++ clobbers: 1572866, // R1 R20 R21 + }, + }, + { +@@ -24251,10 +24251,10 @@ var opcodeTable = [...]opInfo{ + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 262144}, // R19 +- {1, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 524288}, // R20 ++ {1, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, +- clobbers: 262144, // R19 ++ clobbers: 524288, // R20 + }, + }, + { +@@ -24265,11 +24265,11 @@ var opcodeTable = [...]opInfo{ + faultOnNilArg1: true, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 524288}, // R20 +- {1, 262144}, // R19 +- {2, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1048576}, // R21 ++ {1, 524288}, // R20 ++ {2, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, +- clobbers: 786432, // R19 R20 ++ clobbers: 1572864, // R20 R21 + }, + }, + { +@@ -24278,10 +24278,10 @@ var opcodeTable = [...]opInfo{ + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB ++ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -24291,10 +24291,10 @@ var opcodeTable = [...]opInfo{ + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB ++ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -24304,10 +24304,10 @@ var opcodeTable = [...]opInfo{ + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB ++ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -24318,8 +24318,8 @@ var opcodeTable = [...]opInfo{ + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ +- {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 +- {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB ++ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + }, + }, +@@ -24330,8 +24330,8 @@ var opcodeTable = [...]opInfo{ + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ +- {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 +- {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB ++ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + }, + }, +@@ -24342,8 +24342,8 @@ var opcodeTable = [...]opInfo{ + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ +- {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 +- {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB ++ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + }, + }, +@@ -24354,7 +24354,7 @@ var opcodeTable = [...]opInfo{ + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB ++ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + }, + }, +@@ -24365,7 +24365,7 @@ var opcodeTable = [...]opInfo{ + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB ++ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + }, + }, +@@ -24378,11 +24378,11 @@ var opcodeTable = [...]opInfo{ + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ +- {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 +- {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB ++ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -24395,11 +24395,11 @@ var opcodeTable = [...]opInfo{ + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ +- {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 +- {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB ++ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -24411,11 +24411,11 @@ var opcodeTable = [...]opInfo{ + asm: loong64.AAMANDDBW, + reg: regInfo{ + inputs: []inputInfo{ +- {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 +- {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB ++ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -24427,11 +24427,11 @@ var opcodeTable = [...]opInfo{ + asm: loong64.AAMORDBW, + reg: regInfo{ + inputs: []inputInfo{ +- {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 +- {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB ++ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -24444,11 +24444,11 @@ var opcodeTable = [...]opInfo{ + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ +- {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 +- {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB ++ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -24461,11 +24461,11 @@ var opcodeTable = [...]opInfo{ + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ +- {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 +- {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB ++ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -24479,10 +24479,10 @@ var opcodeTable = [...]opInfo{ + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB ++ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -24496,10 +24496,10 @@ var opcodeTable = [...]opInfo{ + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB ++ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -24512,12 +24512,12 @@ var opcodeTable = [...]opInfo{ + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ +- {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 +- {2, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 +- {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB ++ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {2, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -24530,12 +24530,12 @@ var opcodeTable = [...]opInfo{ + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ +- {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 +- {2, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 +- {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB ++ {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {2, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -24546,7 +24546,7 @@ var opcodeTable = [...]opInfo{ + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -24555,7 +24555,7 @@ var opcodeTable = [...]opInfo{ + argLen: 1, + reg: regInfo{ + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -24564,7 +24564,7 @@ var opcodeTable = [...]opInfo{ + argLen: 1, + reg: regInfo{ + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -24584,7 +24584,7 @@ var opcodeTable = [...]opInfo{ + rematerializeable: true, + reg: regInfo{ + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -24594,7 +24594,7 @@ var opcodeTable = [...]opInfo{ + rematerializeable: true, + reg: regInfo{ + outputs: []outputInfo{ +- {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 ++ {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, + }, +@@ -39976,16 +39976,16 @@ var registersLOONG64 = [...]Register{ + {17, loong64.REG_R18, 14, "R18"}, + {18, loong64.REG_R19, 15, "R19"}, + {19, loong64.REG_R20, 16, "R20"}, +- {20, loong64.REG_R21, -1, "R21"}, ++ {20, loong64.REG_R21, 17, "R21"}, + {21, loong64.REGG, -1, "g"}, +- {22, loong64.REG_R23, 17, "R23"}, +- {23, loong64.REG_R24, 18, "R24"}, +- {24, loong64.REG_R25, 19, "R25"}, +- {25, loong64.REG_R26, 20, "R26"}, +- {26, loong64.REG_R27, 21, "R27"}, +- {27, loong64.REG_R28, 22, "R28"}, +- {28, loong64.REG_R29, 23, "R29"}, +- {29, loong64.REG_R31, 24, "R31"}, ++ {22, loong64.REG_R23, 18, "R23"}, ++ {23, loong64.REG_R24, 19, "R24"}, ++ {24, loong64.REG_R25, 20, "R25"}, ++ {25, loong64.REG_R26, 21, "R26"}, ++ {26, loong64.REG_R27, 22, "R27"}, ++ {27, loong64.REG_R28, 23, "R28"}, ++ {28, loong64.REG_R29, 24, "R29"}, ++ {29, loong64.REG_R31, 25, "R31"}, + {30, loong64.REG_F0, -1, "F0"}, + {31, loong64.REG_F1, -1, "F1"}, + {32, loong64.REG_F2, -1, "F2"}, +@@ -40022,7 +40022,7 @@ var registersLOONG64 = [...]Register{ + } + var paramIntRegLOONG64 = []int8{3, 4, 5, 6, 7, 8, 9, 10} + var paramFloatRegLOONG64 = []int8{30, 31, 32, 33, 34, 35, 36, 37} +-var gpRegMaskLOONG64 = regMask(1070596088) ++var gpRegMaskLOONG64 = regMask(1071644664) + var fpRegMaskLOONG64 = regMask(4611686017353646080) + var specialRegMaskLOONG64 = regMask(0) + var framepointerRegLOONG64 = int8(-1) +diff --git a/src/cmd/internal/obj/loong64/a.out.go b/src/cmd/internal/obj/loong64/a.out.go +index 3ed15fc7e7..8df48a1e01 100644 +--- a/src/cmd/internal/obj/loong64/a.out.go ++++ b/src/cmd/internal/obj/loong64/a.out.go +@@ -157,14 +157,14 @@ const ( + REGZERO = REG_R0 // set to zero + REGLINK = REG_R1 + REGSP = REG_R3 +- REGRET = REG_R19 ++ REGRET = REG_R20 // not use + REGARG = -1 // -1 disables passing the first argument in register +- REGRT1 = REG_R19 // reserved for runtime, duffzero and duffcopy +- REGRT2 = REG_R20 // reserved for runtime, duffcopy ++ REGRT1 = REG_R20 // reserved for runtime, duffzero and duffcopy ++ REGRT2 = REG_R21 // reserved for runtime, duffcopy + REGCTXT = REG_R29 // context for closures + REGG = REG_R22 // G in loong64 + REGTMP = REG_R30 // used by the assembler +- FREGRET = REG_F0 ++ FREGRET = REG_F0 // not use + ) + + var LOONG64DWARFRegisters = map[int16]int16{} +diff --git a/src/runtime/duff_loong64.s b/src/runtime/duff_loong64.s +index 63fa3bcca1..df8b653965 100644 +--- a/src/runtime/duff_loong64.s ++++ b/src/runtime/duff_loong64.s +@@ -5,903 +5,903 @@ + #include "textflag.h" + + TEXT runtime·duffzero(SB), NOSPLIT|NOFRAME, $0-0 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 +- MOVV R0, (R19) +- ADDV $8, R19 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 ++ MOVV R0, (R20) ++ ADDV $8, R20 + RET + + TEXT runtime·duffcopy(SB), NOSPLIT|NOFRAME, $0-0 +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + +- MOVV (R19), R30 +- ADDV $8, R19 +- MOVV R30, (R20) ++ MOVV (R20), R30 + ADDV $8, R20 ++ MOVV R30, (R21) ++ ADDV $8, R21 + + RET +diff --git a/src/runtime/mkduff.go b/src/runtime/mkduff.go +index eb2b9c07ba..982321ead7 100644 +--- a/src/runtime/mkduff.go ++++ b/src/runtime/mkduff.go +@@ -183,8 +183,8 @@ func zeroLOONG64(w io.Writer) { + // On return, R19 points to the last zeroed dword. + fmt.Fprintln(w, "TEXT runtime·duffzero(SB), NOSPLIT|NOFRAME, $0-0") + for i := 0; i < 128; i++ { +- fmt.Fprintln(w, "\tMOVV\tR0, (R19)") +- fmt.Fprintln(w, "\tADDV\t$8, R19") ++ fmt.Fprintln(w, "\tMOVV\tR0, (R20)") ++ fmt.Fprintln(w, "\tADDV\t$8, R20") + } + fmt.Fprintln(w, "\tRET") + } +@@ -192,10 +192,10 @@ func zeroLOONG64(w io.Writer) { + func copyLOONG64(w io.Writer) { + fmt.Fprintln(w, "TEXT runtime·duffcopy(SB), NOSPLIT|NOFRAME, $0-0") + for i := 0; i < 128; i++ { +- fmt.Fprintln(w, "\tMOVV\t(R19), R30") +- fmt.Fprintln(w, "\tADDV\t$8, R19") +- fmt.Fprintln(w, "\tMOVV\tR30, (R20)") ++ fmt.Fprintln(w, "\tMOVV\t(R20), R30") + fmt.Fprintln(w, "\tADDV\t$8, R20") ++ fmt.Fprintln(w, "\tMOVV\tR30, (R21)") ++ fmt.Fprintln(w, "\tADDV\t$8, R21") + fmt.Fprintln(w) + } + fmt.Fprintln(w, "\tRET") +-- +2.38.1 + diff --git a/0071-cmd-compile-add-ABI-register-definations-for-loong64.patch b/0071-cmd-compile-add-ABI-register-definations-for-loong64.patch new file mode 100644 index 0000000..f500ac2 --- /dev/null +++ b/0071-cmd-compile-add-ABI-register-definations-for-loong64.patch @@ -0,0 +1,74 @@ +From 60a2d7c5551282cfff88fe94d276ae42712d7aa7 Mon Sep 17 00:00:00 2001 +From: Guoqi Chen +Date: Tue, 15 Aug 2023 17:11:19 +0800 +Subject: [PATCH 09/30] cmd/compile: add ABI register definations for loong64 + +Change-Id: If919cb5427f47a764afa8fca1765092411ba9ed6 +--- + src/cmd/compile/abi-internal.md | 50 +++++++++++++++++++++++++++++++++ + 1 file changed, 50 insertions(+) + +diff --git a/src/cmd/compile/abi-internal.md b/src/cmd/compile/abi-internal.md +index 14464ed904..db5197fb72 100644 +--- a/src/cmd/compile/abi-internal.md ++++ b/src/cmd/compile/abi-internal.md +@@ -633,6 +633,56 @@ modifying or saving the FPCR. + Functions are allowed to modify it between calls (as long as they + restore it), but as of this writing Go code never does. + ++### loong64 architecture ++ ++The loong64 architecture uses R4 – R19 for integer arguments and integer results. ++ ++It uses F0 – F15 for floating-point arguments and results. ++ ++Registers R20 - R21, R23 – R28, R30, F16 – F31 are permanent scratch registers. ++ ++Register R2 is reserved and never used. ++ ++Register R20, R21 is Used by runtime.duffcopy, runtime.duffzero. ++ ++Special-purpose registers used within Go generated code and Go assembly code ++are as follows: ++ ++| Register | Call meaning | Return meaning | Body meaning | ++| --- | --- | --- | --- | ++| R0 | Zero value | Same | Same | ++| R1 | Link register | Link register | Scratch | ++| R3 | Stack pointer | Same | Same | ++| R20,R21 | Scratch | Scratch | Used by duffcopy, duffzero | ++| R22 | Current goroutine | Same | Same | ++| R29 | Closure context pointer | Same | Same | ++| R30 | used by the assembler | Same | Same | ++ ++*Rationale*: These register meanings are compatible with Go’s stack-based ++calling convention. ++ ++#### Stack layout ++ ++The stack pointer, R3, grows down and is aligned to 8 bytes. ++ ++A function's stack frame, after the frame is created, is laid out as ++follows: ++ ++ +------------------------------+ ++ | ... locals ... | ++ | ... outgoing arguments ... | ++ | return PC | ← R3 points to ++ +------------------------------+ ↓ lower addresses ++ ++This stack layout is used by both register-based (ABIInternal) and ++stack-based (ABI0) calling conventions. ++ ++The "return PC" is loaded to the link register, R1, as part of the ++loong64 `JAL` operation. ++ ++#### Flags ++All bits in CSR are system flags and are not modified by Go. ++ + ### ppc64 architecture + + The ppc64 architecture uses R3 – R10 and R14 – R17 for integer arguments +-- +2.38.1 + diff --git a/0072-cmd-compile-cmd-internal-runtime-change-registers-on.patch b/0072-cmd-compile-cmd-internal-runtime-change-registers-on.patch new file mode 100644 index 0000000..1440c50 --- /dev/null +++ b/0072-cmd-compile-cmd-internal-runtime-change-registers-on.patch @@ -0,0 +1,402 @@ +From 19f263cb7f34f02da0d226278d785b82a0713a62 Mon Sep 17 00:00:00 2001 +From: Guoqi Chen +Date: Tue, 15 Aug 2023 19:23:51 +0800 +Subject: [PATCH 10/30] cmd/compile,cmd/internal,runtime: change registers on + loong64 to avoid regABI arguments + +Change-Id: Id05d498df2b4f83fda4772bccbf93f5be03b13a0 +--- + .../compile/internal/ssa/_gen/LOONG64Ops.go | 8 +- + src/cmd/compile/internal/ssa/opGen.go | 12 +-- + src/cmd/internal/obj/loong64/obj.go | 68 ++++++++--------- + src/runtime/asm_loong64.s | 74 +++++++++---------- + 4 files changed, 81 insertions(+), 81 deletions(-) + +diff --git a/src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go b/src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go +index d2beaa1193..3a30d9645d 100644 +--- a/src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go ++++ b/src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go +@@ -130,10 +130,10 @@ func init() { + gpspsbg = gpspg | buildReg("SB") + fp = buildReg("F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31") + callerSave = gp | fp | buildReg("g") // runtime.setg (and anything calling it) may clobber g +- r1 = buildReg("R19") +- r2 = buildReg("R18") +- r3 = buildReg("R17") +- r4 = buildReg("R4") ++ r1 = buildReg("R20") ++ r2 = buildReg("R21") ++ r3 = buildReg("R23") ++ r4 = buildReg("R24") + ) + // Common regInfo + var ( +diff --git a/src/cmd/compile/internal/ssa/opGen.go b/src/cmd/compile/internal/ssa/opGen.go +index 63c8cc329a..6df524fef3 100644 +--- a/src/cmd/compile/internal/ssa/opGen.go ++++ b/src/cmd/compile/internal/ssa/opGen.go +@@ -24619,8 +24619,8 @@ var opcodeTable = [...]opInfo{ + call: true, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 65536}, // R17 +- {1, 8}, // R4 ++ {0, 4194304}, // R23 ++ {1, 8388608}, // R24 + }, + }, + }, +@@ -24631,8 +24631,8 @@ var opcodeTable = [...]opInfo{ + call: true, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 131072}, // R18 +- {1, 65536}, // R17 ++ {0, 1048576}, // R21 ++ {1, 4194304}, // R23 + }, + }, + }, +@@ -24643,8 +24643,8 @@ var opcodeTable = [...]opInfo{ + call: true, + reg: regInfo{ + inputs: []inputInfo{ +- {0, 262144}, // R19 +- {1, 131072}, // R18 ++ {0, 524288}, // R20 ++ {1, 1048576}, // R21 + }, + }, + }, +diff --git a/src/cmd/internal/obj/loong64/obj.go b/src/cmd/internal/obj/loong64/obj.go +index 5d7213d8c7..803dd45de7 100644 +--- a/src/cmd/internal/obj/loong64/obj.go ++++ b/src/cmd/internal/obj/loong64/obj.go +@@ -395,13 +395,13 @@ func preprocess(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { + if c.cursym.Func().Text.From.Sym.Wrapper() && c.cursym.Func().Text.Mark&LEAF == 0 { + // if(g->panic != nil && g->panic->argp == FP) g->panic->argp = bottom-of-frame + // +- // MOV g_panic(g), R1 +- // BEQ R1, end +- // MOV panic_argp(R1), R2 +- // ADD $(autosize+FIXED_FRAME), R29, R3 +- // BNE R2, R3, end +- // ADD $FIXED_FRAME, R29, R2 +- // MOV R2, panic_argp(R1) ++ // MOV g_panic(g), R20 ++ // BEQ R20, end ++ // MOV panic_argp(R20), R24 ++ // ADD $(autosize+FIXED_FRAME), R3, R30 ++ // BNE R24, R30, end ++ // ADD $FIXED_FRAME, R3, R24 ++ // MOV R24, panic_argp(R20) + // end: + // NOP + // +@@ -418,12 +418,12 @@ func preprocess(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { + q.From.Reg = REGG + q.From.Offset = 4 * int64(c.ctxt.Arch.PtrSize) // G.panic + q.To.Type = obj.TYPE_REG +- q.To.Reg = REG_R19 ++ q.To.Reg = REG_R20 + + q = obj.Appendp(q, newprog) + q.As = ABEQ + q.From.Type = obj.TYPE_REG +- q.From.Reg = REG_R19 ++ q.From.Reg = REG_R20 + q.To.Type = obj.TYPE_BRANCH + q.Mark |= BRANCH + p1 = q +@@ -431,10 +431,10 @@ func preprocess(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { + q = obj.Appendp(q, newprog) + q.As = mov + q.From.Type = obj.TYPE_MEM +- q.From.Reg = REG_R19 ++ q.From.Reg = REG_R20 + q.From.Offset = 0 // Panic.argp + q.To.Type = obj.TYPE_REG +- q.To.Reg = REG_R4 ++ q.To.Reg = REG_R24 + + q = obj.Appendp(q, newprog) + q.As = add +@@ -442,13 +442,13 @@ func preprocess(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { + q.From.Offset = int64(autosize) + ctxt.Arch.FixedFrameSize + q.Reg = REGSP + q.To.Type = obj.TYPE_REG +- q.To.Reg = REG_R5 ++ q.To.Reg = REG_R30 + + q = obj.Appendp(q, newprog) + q.As = ABNE + q.From.Type = obj.TYPE_REG +- q.From.Reg = REG_R4 +- q.Reg = REG_R5 ++ q.From.Reg = REG_R24 ++ q.Reg = REG_R30 + q.To.Type = obj.TYPE_BRANCH + q.Mark |= BRANCH + p2 = q +@@ -459,14 +459,14 @@ func preprocess(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { + q.From.Offset = ctxt.Arch.FixedFrameSize + q.Reg = REGSP + q.To.Type = obj.TYPE_REG +- q.To.Reg = REG_R4 ++ q.To.Reg = REG_R24 + + q = obj.Appendp(q, newprog) + q.As = mov + q.From.Type = obj.TYPE_REG +- q.From.Reg = REG_R4 ++ q.From.Reg = REG_R24 + q.To.Type = obj.TYPE_MEM +- q.To.Reg = REG_R19 ++ q.To.Reg = REG_R20 + q.To.Offset = 0 // Panic.argp + + q = obj.Appendp(q, newprog) +@@ -689,7 +689,7 @@ func (c *ctxt0) stacksplit(p *obj.Prog, framesize int32) *obj.Prog { + // Jump back to here after morestack returns. + startPred := p + +- // MOV g_stackguard(g), R19 ++ // MOV g_stackguard(g), R20 + p = obj.Appendp(p, c.newprog) + + p.As = mov +@@ -700,7 +700,7 @@ func (c *ctxt0) stacksplit(p *obj.Prog, framesize int32) *obj.Prog { + p.From.Offset = 3 * int64(c.ctxt.Arch.PtrSize) // G.stackguard1 + } + p.To.Type = obj.TYPE_REG +- p.To.Reg = REG_R19 ++ p.To.Reg = REG_R20 + + // Mark the stack bound check and morestack call async nonpreemptible. + // If we get preempted here, when resumed the preemption request is +@@ -711,15 +711,15 @@ func (c *ctxt0) stacksplit(p *obj.Prog, framesize int32) *obj.Prog { + var q *obj.Prog + if framesize <= objabi.StackSmall { + // small stack: SP < stackguard +- // AGTU SP, stackguard, R19 ++ // AGTU SP, stackguard, R20 + p = obj.Appendp(p, c.newprog) + + p.As = ASGTU + p.From.Type = obj.TYPE_REG + p.From.Reg = REGSP +- p.Reg = REG_R19 ++ p.Reg = REG_R20 + p.To.Type = obj.TYPE_REG +- p.To.Reg = REG_R19 ++ p.To.Reg = REG_R20 + } else { + // large stack: SP-framesize < stackguard-StackSmall + offset := int64(framesize) - objabi.StackSmall +@@ -731,8 +731,8 @@ func (c *ctxt0) stacksplit(p *obj.Prog, framesize int32) *obj.Prog { + // stack guard to incorrectly succeed. We explicitly + // guard against underflow. + // +- // SGTU $(framesize-StackSmall), SP, R4 +- // BNE R4, label-of-call-to-morestack ++ // SGTU $(framesize-StackSmall), SP, R24 ++ // BNE R24, label-of-call-to-morestack + + p = obj.Appendp(p, c.newprog) + p.As = ASGTU +@@ -740,13 +740,13 @@ func (c *ctxt0) stacksplit(p *obj.Prog, framesize int32) *obj.Prog { + p.From.Offset = offset + p.Reg = REGSP + p.To.Type = obj.TYPE_REG +- p.To.Reg = REG_R4 ++ p.To.Reg = REG_R24 + + p = obj.Appendp(p, c.newprog) + q = p + p.As = ABNE + p.From.Type = obj.TYPE_REG +- p.From.Reg = REG_R4 ++ p.From.Reg = REG_R24 + p.To.Type = obj.TYPE_BRANCH + p.Mark |= BRANCH + } +@@ -758,35 +758,35 @@ func (c *ctxt0) stacksplit(p *obj.Prog, framesize int32) *obj.Prog { + p.From.Offset = -offset + p.Reg = REGSP + p.To.Type = obj.TYPE_REG +- p.To.Reg = REG_R4 ++ p.To.Reg = REG_R24 + + p = obj.Appendp(p, c.newprog) + p.As = ASGTU + p.From.Type = obj.TYPE_REG +- p.From.Reg = REG_R4 +- p.Reg = REG_R19 ++ p.From.Reg = REG_R24 ++ p.Reg = REG_R20 + p.To.Type = obj.TYPE_REG +- p.To.Reg = REG_R19 ++ p.To.Reg = REG_R20 + } + +- // q1: BNE R19, done ++ // q1: BNE R20, done + p = obj.Appendp(p, c.newprog) + q1 := p + + p.As = ABNE + p.From.Type = obj.TYPE_REG +- p.From.Reg = REG_R19 ++ p.From.Reg = REG_R20 + p.To.Type = obj.TYPE_BRANCH + p.Mark |= BRANCH + +- // MOV LINK, R5 ++ // MOV LINK, R30 + p = obj.Appendp(p, c.newprog) + + p.As = mov + p.From.Type = obj.TYPE_REG + p.From.Reg = REGLINK + p.To.Type = obj.TYPE_REG +- p.To.Reg = REG_R5 ++ p.To.Reg = REG_R30 + if q != nil { + q.To.SetTarget(p) + p.Mark |= LABEL +diff --git a/src/runtime/asm_loong64.s b/src/runtime/asm_loong64.s +index d82c688925..4a21860316 100644 +--- a/src/runtime/asm_loong64.s ++++ b/src/runtime/asm_loong64.s +@@ -214,7 +214,7 @@ noswitch: + + // Called during function prolog when more stack is needed. + // Caller has already loaded: +-// loong64: R5: LR ++// loong64: R30: LR + // + // The traceback routines see morestack on a g0 as being + // the top of a stack (for example, morestack calling newstack +@@ -238,12 +238,12 @@ TEXT runtime·morestack(SB),NOSPLIT|NOFRAME,$0-0 + // Set g->sched to context in f. + MOVV R3, (g_sched+gobuf_sp)(g) + MOVV R1, (g_sched+gobuf_pc)(g) +- MOVV R5, (g_sched+gobuf_lr)(g) ++ MOVV R30, (g_sched+gobuf_lr)(g) + MOVV REGCTXT, (g_sched+gobuf_ctxt)(g) + + // Called from f. + // Set m->morebuf to f's caller. +- MOVV R5, (m_morebuf+gobuf_pc)(R7) // f's caller's PC ++ MOVV R30, (m_morebuf+gobuf_pc)(R7) // f's caller's PC + MOVV R3, (m_morebuf+gobuf_sp)(R7) // f's caller's SP + MOVV g, (m_morebuf+gobuf_g)(R7) + +@@ -741,70 +741,70 @@ flush: + // then tail call to the corresponding runtime handler. + // The tail call makes these stubs disappear in backtraces. + TEXT runtime·panicIndex(SB),NOSPLIT,$0-16 +- MOVV R19, x+0(FP) +- MOVV R18, y+8(FP) ++ MOVV R20, x+0(FP) ++ MOVV R21, y+8(FP) + JMP runtime·goPanicIndex(SB) + TEXT runtime·panicIndexU(SB),NOSPLIT,$0-16 +- MOVV R19, x+0(FP) +- MOVV R18, y+8(FP) ++ MOVV R20, x+0(FP) ++ MOVV R21, y+8(FP) + JMP runtime·goPanicIndexU(SB) + TEXT runtime·panicSliceAlen(SB),NOSPLIT,$0-16 +- MOVV R18, x+0(FP) +- MOVV R17, y+8(FP) ++ MOVV R21, x+0(FP) ++ MOVV R23, y+8(FP) + JMP runtime·goPanicSliceAlen(SB) + TEXT runtime·panicSliceAlenU(SB),NOSPLIT,$0-16 +- MOVV R18, x+0(FP) +- MOVV R17, y+8(FP) ++ MOVV R21, x+0(FP) ++ MOVV R23, y+8(FP) + JMP runtime·goPanicSliceAlenU(SB) + TEXT runtime·panicSliceAcap(SB),NOSPLIT,$0-16 +- MOVV R18, x+0(FP) +- MOVV R17, y+8(FP) ++ MOVV R21, x+0(FP) ++ MOVV R23, y+8(FP) + JMP runtime·goPanicSliceAcap(SB) + TEXT runtime·panicSliceAcapU(SB),NOSPLIT,$0-16 +- MOVV R18, x+0(FP) +- MOVV R17, y+8(FP) ++ MOVV R21, x+0(FP) ++ MOVV R23, y+8(FP) + JMP runtime·goPanicSliceAcapU(SB) + TEXT runtime·panicSliceB(SB),NOSPLIT,$0-16 +- MOVV R19, x+0(FP) +- MOVV R18, y+8(FP) ++ MOVV R20, x+0(FP) ++ MOVV R21, y+8(FP) + JMP runtime·goPanicSliceB(SB) + TEXT runtime·panicSliceBU(SB),NOSPLIT,$0-16 +- MOVV R19, x+0(FP) +- MOVV R18, y+8(FP) ++ MOVV R20, x+0(FP) ++ MOVV R21, y+8(FP) + JMP runtime·goPanicSliceBU(SB) + TEXT runtime·panicSlice3Alen(SB),NOSPLIT,$0-16 +- MOVV R17, x+0(FP) +- MOVV R4, y+8(FP) ++ MOVV R23, x+0(FP) ++ MOVV R24, y+8(FP) + JMP runtime·goPanicSlice3Alen(SB) + TEXT runtime·panicSlice3AlenU(SB),NOSPLIT,$0-16 +- MOVV R17, x+0(FP) +- MOVV R4, y+8(FP) ++ MOVV R23, x+0(FP) ++ MOVV R24, y+8(FP) + JMP runtime·goPanicSlice3AlenU(SB) + TEXT runtime·panicSlice3Acap(SB),NOSPLIT,$0-16 +- MOVV R17, x+0(FP) +- MOVV R4, y+8(FP) ++ MOVV R23, x+0(FP) ++ MOVV R24, y+8(FP) + JMP runtime·goPanicSlice3Acap(SB) + TEXT runtime·panicSlice3AcapU(SB),NOSPLIT,$0-16 +- MOVV R17, x+0(FP) +- MOVV R4, y+8(FP) ++ MOVV R23, x+0(FP) ++ MOVV R24, y+8(FP) + JMP runtime·goPanicSlice3AcapU(SB) + TEXT runtime·panicSlice3B(SB),NOSPLIT,$0-16 +- MOVV R18, x+0(FP) +- MOVV R17, y+8(FP) ++ MOVV R21, x+0(FP) ++ MOVV R23, y+8(FP) + JMP runtime·goPanicSlice3B(SB) + TEXT runtime·panicSlice3BU(SB),NOSPLIT,$0-16 +- MOVV R18, x+0(FP) +- MOVV R17, y+8(FP) ++ MOVV R21, x+0(FP) ++ MOVV R23, y+8(FP) + JMP runtime·goPanicSlice3BU(SB) + TEXT runtime·panicSlice3C(SB),NOSPLIT,$0-16 +- MOVV R19, x+0(FP) +- MOVV R18, y+8(FP) ++ MOVV R20, x+0(FP) ++ MOVV R21, y+8(FP) + JMP runtime·goPanicSlice3C(SB) + TEXT runtime·panicSlice3CU(SB),NOSPLIT,$0-16 +- MOVV R19, x+0(FP) +- MOVV R18, y+8(FP) ++ MOVV R20, x+0(FP) ++ MOVV R21, y+8(FP) + JMP runtime·goPanicSlice3CU(SB) + TEXT runtime·panicSliceConvert(SB),NOSPLIT,$0-16 +- MOVV R17, x+0(FP) +- MOVV R4, y+8(FP) ++ MOVV R23, x+0(FP) ++ MOVV R24, y+8(FP) + JMP runtime·goPanicSliceConvert(SB) +-- +2.38.1 + diff --git a/0073-internal-abi-define-loong64-regABI-constants.patch b/0073-internal-abi-define-loong64-regABI-constants.patch new file mode 100644 index 0000000..c591d73 --- /dev/null +++ b/0073-internal-abi-define-loong64-regABI-constants.patch @@ -0,0 +1,39 @@ +From 77cb007971a25238c6a3dc5e9344ce5b4a4e85ff Mon Sep 17 00:00:00 2001 +From: Guoqi Chen +Date: Tue, 15 Aug 2023 19:38:33 +0800 +Subject: [PATCH 11/30] internal/abi: define loong64 regABI constants + +Change-Id: Ie927aafc5d2ebb42fb9c59a1f4c3a1323da4c27a +--- + src/internal/abi/abi_loong64.go | 19 +++++++++++++++++++ + 1 file changed, 19 insertions(+) + create mode 100644 src/internal/abi/abi_loong64.go + +diff --git a/src/internal/abi/abi_loong64.go b/src/internal/abi/abi_loong64.go +new file mode 100644 +index 0000000000..c2306ae8d8 +--- /dev/null ++++ b/src/internal/abi/abi_loong64.go +@@ -0,0 +1,19 @@ ++// Copyright 2023 The Go Authors. All rights reserved. ++// Use of this source code is governed by a BSD-style ++// license that can be found in the LICENSE file. ++ ++//go:build goexperiment.regabiargs ++ ++package abi ++ ++const ( ++ // See abi_generic.go. ++ ++ // R4 - R19 ++ IntArgRegs = 16 ++ ++ // F0 - F15 ++ FloatArgRegs = 16 ++ ++ EffectiveFloatRegSize = 8 ++) +-- +2.38.1 + diff --git a/0074-cmd-compile-internal-add-register-info-for-loong64-r.patch b/0074-cmd-compile-internal-add-register-info-for-loong64-r.patch new file mode 100644 index 0000000..5fd208a --- /dev/null +++ b/0074-cmd-compile-internal-add-register-info-for-loong64-r.patch @@ -0,0 +1,73 @@ +From 537f7393b3d52214a5be503e2efc2c27bea20414 Mon Sep 17 00:00:00 2001 +From: Guoqi Chen +Date: Tue, 15 Aug 2023 19:54:51 +0800 +Subject: [PATCH 12/30] cmd/compile/internal: add register info for loong64 + regABI + +Change-Id: I178c1a706bde9158a1ab05b12c5c228e24b36962 +--- + src/cmd/compile/internal/loong64/ssa.go | 2 ++ + src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go | 4 ++-- + src/cmd/compile/internal/ssa/config.go | 2 ++ + src/cmd/compile/internal/ssa/opGen.go | 4 ++-- + 4 files changed, 8 insertions(+), 4 deletions(-) + +diff --git a/src/cmd/compile/internal/loong64/ssa.go b/src/cmd/compile/internal/loong64/ssa.go +index 68fc5d105c..98685ca43b 100644 +--- a/src/cmd/compile/internal/loong64/ssa.go ++++ b/src/cmd/compile/internal/loong64/ssa.go +@@ -144,6 +144,8 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { + p.From.Type = obj.TYPE_REG + p.From.Reg = r + ssagen.AddrAuto(&p.To, v) ++ case ssa.OpArgIntReg, ssa.OpArgFloatReg: ++ ssagen.CheckArgReg(v) + case ssa.OpLOONG64ADDV, + ssa.OpLOONG64SUBV, + ssa.OpLOONG64AND, +diff --git a/src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go b/src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go +index 3a30d9645d..722d69e8e3 100644 +--- a/src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go ++++ b/src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go +@@ -465,8 +465,8 @@ func init() { + blocks: blocks, + regnames: regNamesLOONG64, + // TODO: support register ABI on loong64 +- ParamIntRegNames: "R4 R5 R6 R7 R8 R9 R10 R11", +- ParamFloatRegNames: "F0 F1 F2 F3 F4 F5 F6 F7", ++ ParamIntRegNames: "R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19", ++ ParamFloatRegNames: "F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15", + gpregmask: gp, + fpregmask: fp, + framepointerreg: -1, // not used +diff --git a/src/cmd/compile/internal/ssa/config.go b/src/cmd/compile/internal/ssa/config.go +index ed844306c1..98a78e0c4a 100644 +--- a/src/cmd/compile/internal/ssa/config.go ++++ b/src/cmd/compile/internal/ssa/config.go +@@ -278,6 +278,8 @@ func NewConfig(arch string, types Types, ctxt *obj.Link, optimize, softfloat boo + c.registers = registersLOONG64[:] + c.gpRegMask = gpRegMaskLOONG64 + c.fpRegMask = fpRegMaskLOONG64 ++ // c.intParamRegs = paramIntRegLOONG64 ++ // c.floatParamRegs = paramFloatRegLOONG64 + c.FPReg = framepointerRegLOONG64 + c.LinkReg = linkRegLOONG64 + c.hasGReg = true +diff --git a/src/cmd/compile/internal/ssa/opGen.go b/src/cmd/compile/internal/ssa/opGen.go +index 6df524fef3..8893df9140 100644 +--- a/src/cmd/compile/internal/ssa/opGen.go ++++ b/src/cmd/compile/internal/ssa/opGen.go +@@ -40020,8 +40020,8 @@ var registersLOONG64 = [...]Register{ + {61, loong64.REG_F31, -1, "F31"}, + {62, 0, -1, "SB"}, + } +-var paramIntRegLOONG64 = []int8{3, 4, 5, 6, 7, 8, 9, 10} +-var paramFloatRegLOONG64 = []int8{30, 31, 32, 33, 34, 35, 36, 37} ++var paramIntRegLOONG64 = []int8{3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18} ++var paramFloatRegLOONG64 = []int8{30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45} + var gpRegMaskLOONG64 = regMask(1071644664) + var fpRegMaskLOONG64 = regMask(4611686017353646080) + var specialRegMaskLOONG64 = regMask(0) +-- +2.38.1 + diff --git a/0075-cmd-compile-internal-add-spill-support-for-loong64-r.patch b/0075-cmd-compile-internal-add-spill-support-for-loong64-r.patch new file mode 100644 index 0000000..3d3d05d --- /dev/null +++ b/0075-cmd-compile-internal-add-spill-support-for-loong64-r.patch @@ -0,0 +1,78 @@ +From a67c19b91b764e21106876cf859b14aeca62ac0c Mon Sep 17 00:00:00 2001 +From: Guoqi Chen +Date: Tue, 15 Aug 2023 20:10:33 +0800 +Subject: [PATCH 13/30] cmd/compile/internal: add spill support for loong64 + regABI + +Change-Id: I9fef78e5ff1b7518142bcf62aa79e666c10d3442 +--- + src/cmd/compile/internal/loong64/galign.go | 2 ++ + src/cmd/compile/internal/loong64/ssa.go | 30 ++++++++++++++++++++++ + 2 files changed, 32 insertions(+) + +diff --git a/src/cmd/compile/internal/loong64/galign.go b/src/cmd/compile/internal/loong64/galign.go +index 99ab7bdfb5..a613165054 100644 +--- a/src/cmd/compile/internal/loong64/galign.go ++++ b/src/cmd/compile/internal/loong64/galign.go +@@ -20,4 +20,6 @@ func Init(arch *ssagen.ArchInfo) { + arch.SSAMarkMoves = func(s *ssagen.State, b *ssa.Block) {} + arch.SSAGenValue = ssaGenValue + arch.SSAGenBlock = ssaGenBlock ++ arch.LoadRegResult = loadRegResult ++ arch.SpillArgReg = spillArgReg + } +diff --git a/src/cmd/compile/internal/loong64/ssa.go b/src/cmd/compile/internal/loong64/ssa.go +index 98685ca43b..3453e7bf06 100644 +--- a/src/cmd/compile/internal/loong64/ssa.go ++++ b/src/cmd/compile/internal/loong64/ssa.go +@@ -10,6 +10,7 @@ import ( + "cmd/compile/internal/base" + "cmd/compile/internal/ir" + "cmd/compile/internal/logopt" ++ "cmd/compile/internal/objw" + "cmd/compile/internal/ssa" + "cmd/compile/internal/ssagen" + "cmd/compile/internal/types" +@@ -145,6 +146,16 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { + p.From.Reg = r + ssagen.AddrAuto(&p.To, v) + case ssa.OpArgIntReg, ssa.OpArgFloatReg: ++ // The assembler needs to wrap the entry safepoint/stack growth code with spill/unspill ++ // The loop only runs once. ++ for _, a := range v.Block.Func.RegArgs { ++ // Pass the spill/unspill information along to the assembler, offset by size of ++ // the saved LR slot. ++ addr := ssagen.SpillSlotAddr(a, loong64.REGSP, base.Ctxt.Arch.FixedFrameSize) ++ s.FuncInfo().AddSpill( ++ obj.RegSpill{Reg: a.Reg, Addr: addr, Unspill: loadByType(a.Type, a.Reg), Spill: storeByType(a.Type, a.Reg)}) ++ } ++ v.Block.Func.RegArgs = nil + ssagen.CheckArgReg(v) + case ssa.OpLOONG64ADDV, + ssa.OpLOONG64SUBV, +@@ -762,3 +773,22 @@ func ssaGenBlock(s *ssagen.State, b, next *ssa.Block) { + b.Fatalf("branch not implemented: %s", b.LongString()) + } + } ++ ++func loadRegResult(s *ssagen.State, f *ssa.Func, t *types.Type, reg int16, n *ir.Name, off int64) *obj.Prog { ++ p := s.Prog(loadByType(t, reg)) ++ p.From.Type = obj.TYPE_MEM ++ p.From.Name = obj.NAME_AUTO ++ p.From.Sym = n.Linksym() ++ p.From.Offset = n.FrameOffset() + off ++ p.To.Type = obj.TYPE_REG ++ p.To.Reg = reg ++ return p ++} ++ ++func spillArgReg(pp *objw.Progs, p *obj.Prog, f *ssa.Func, t *types.Type, reg int16, n *ir.Name, off int64) *obj.Prog { ++ p = pp.Append(p, storeByType(t, reg), obj.TYPE_REG, reg, 0, obj.TYPE_MEM, 0, n.FrameOffset()+off) ++ p.To.Name = obj.NAME_PARAM ++ p.To.Sym = n.Linksym() ++ p.Pos = p.Pos.WithNotStmt() ++ return p ++} +-- +2.38.1 + diff --git a/0076-cmd-compile-update-loong64-CALL-ops.patch b/0076-cmd-compile-update-loong64-CALL-ops.patch new file mode 100644 index 0000000..0fe200a --- /dev/null +++ b/0076-cmd-compile-update-loong64-CALL-ops.patch @@ -0,0 +1,75 @@ +From e9dc5fa492dbe9859b3a34657ac5e40749ec25bb Mon Sep 17 00:00:00 2001 +From: Guoqi Chen +Date: Tue, 15 Aug 2023 20:23:46 +0800 +Subject: [PATCH 14/30] cmd/compile: update loong64 CALL* ops + +allow the loong64 CALL* ops to take variable number of args + +Change-Id: I405e418a2084ec14f9d3b0f776a7454e198e3281 +--- + src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go | 8 ++++---- + src/cmd/compile/internal/ssa/opGen.go | 8 ++++---- + 2 files changed, 8 insertions(+), 8 deletions(-) + +diff --git a/src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go b/src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go +index 722d69e8e3..90e8832c71 100644 +--- a/src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go ++++ b/src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go +@@ -273,10 +273,10 @@ func init() { + {name: "MOVDF", argLength: 1, reg: fp11, asm: "MOVDF"}, // float64 -> float32 + + // function calls +- {name: "CALLstatic", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call static function aux.(*obj.LSym). arg0=mem, auxint=argsize, returns mem +- {name: "CALLtail", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true, tailCall: true}, // tail call static function aux.(*obj.LSym). arg0=mem, auxint=argsize, returns mem +- {name: "CALLclosure", argLength: 3, reg: regInfo{inputs: []regMask{gpsp, buildReg("R29"), 0}, clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call function via closure. arg0=codeptr, arg1=closure, arg2=mem, auxint=argsize, returns mem +- {name: "CALLinter", argLength: 2, reg: regInfo{inputs: []regMask{gp}, clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call fn by pointer. arg0=codeptr, arg1=mem, auxint=argsize, returns mem ++ {name: "CALLstatic", argLength: -1, reg: regInfo{clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call static function aux.(*obj.LSym). last arg=mem, auxint=argsize, returns mem ++ {name: "CALLtail", argLength: -1, reg: regInfo{clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true, tailCall: true}, // tail call static function aux.(*obj.LSym). last arg=mem, auxint=argsize, returns mem ++ {name: "CALLclosure", argLength: -1, reg: regInfo{inputs: []regMask{gpsp, buildReg("R29"), 0}, clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call function via closure. arg0=codeptr, arg1=closure, last arg=mem, auxint=argsize, returns mem ++ {name: "CALLinter", argLength: -1, reg: regInfo{inputs: []regMask{gp}, clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call fn by pointer. arg0=codeptr, last arg=mem, auxint=argsize, returns mem + + // duffzero + // arg0 = address of memory to zero +diff --git a/src/cmd/compile/internal/ssa/opGen.go b/src/cmd/compile/internal/ssa/opGen.go +index 8893df9140..eef5087061 100644 +--- a/src/cmd/compile/internal/ssa/opGen.go ++++ b/src/cmd/compile/internal/ssa/opGen.go +@@ -24173,7 +24173,7 @@ var opcodeTable = [...]opInfo{ + { + name: "CALLstatic", + auxType: auxCallOff, +- argLen: 1, ++ argLen: -1, + clobberFlags: true, + call: true, + reg: regInfo{ +@@ -24183,7 +24183,7 @@ var opcodeTable = [...]opInfo{ + { + name: "CALLtail", + auxType: auxCallOff, +- argLen: 1, ++ argLen: -1, + clobberFlags: true, + call: true, + tailCall: true, +@@ -24194,7 +24194,7 @@ var opcodeTable = [...]opInfo{ + { + name: "CALLclosure", + auxType: auxCallOff, +- argLen: 3, ++ argLen: -1, + clobberFlags: true, + call: true, + reg: regInfo{ +@@ -24208,7 +24208,7 @@ var opcodeTable = [...]opInfo{ + { + name: "CALLinter", + auxType: auxCallOff, +- argLen: 2, ++ argLen: -1, + clobberFlags: true, + call: true, + reg: regInfo{ +-- +2.38.1 + diff --git a/0077-runtime-make-duff-device-as-ABIInternal-for-loong64.patch b/0077-runtime-make-duff-device-as-ABIInternal-for-loong64.patch new file mode 100644 index 0000000..4e7c925 --- /dev/null +++ b/0077-runtime-make-duff-device-as-ABIInternal-for-loong64.patch @@ -0,0 +1,58 @@ +From 5c0b0651374fada6fd94984df8cfecc6e0fe9f9c Mon Sep 17 00:00:00 2001 +From: Guoqi Chen +Date: Tue, 15 Aug 2023 20:54:16 +0800 +Subject: [PATCH 15/30] runtime: make duff device as ABIInternal for loong64 + +Change-Id: I822ed1e88e7acbeaf8b321ad79036a940c0f9711 +--- + src/runtime/duff_loong64.s | 4 ++-- + src/runtime/mkduff.go | 4 ++-- + 2 files changed, 4 insertions(+), 4 deletions(-) + +diff --git a/src/runtime/duff_loong64.s b/src/runtime/duff_loong64.s +index df8b653965..b05502d91d 100644 +--- a/src/runtime/duff_loong64.s ++++ b/src/runtime/duff_loong64.s +@@ -4,7 +4,7 @@ + + #include "textflag.h" + +-TEXT runtime·duffzero(SB), NOSPLIT|NOFRAME, $0-0 ++TEXT runtime·duffzero(SB), NOSPLIT|NOFRAME, $0-0 + MOVV R0, (R20) + ADDV $8, R20 + MOVV R0, (R20) +@@ -263,7 +263,7 @@ TEXT runtime·duffzero(SB), NOSPLIT|NOFRAME, $0-0 + ADDV $8, R20 + RET + +-TEXT runtime·duffcopy(SB), NOSPLIT|NOFRAME, $0-0 ++TEXT runtime·duffcopy(SB), NOSPLIT|NOFRAME, $0-0 + MOVV (R20), R30 + ADDV $8, R20 + MOVV R30, (R21) +diff --git a/src/runtime/mkduff.go b/src/runtime/mkduff.go +index 982321ead7..5fee3f95b6 100644 +--- a/src/runtime/mkduff.go ++++ b/src/runtime/mkduff.go +@@ -181,7 +181,7 @@ func zeroLOONG64(w io.Writer) { + // R0: always zero + // R19 (aka REGRT1): ptr to memory to be zeroed + // On return, R19 points to the last zeroed dword. +- fmt.Fprintln(w, "TEXT runtime·duffzero(SB), NOSPLIT|NOFRAME, $0-0") ++ fmt.Fprintln(w, "TEXT runtime·duffzero(SB), NOSPLIT|NOFRAME, $0-0") + for i := 0; i < 128; i++ { + fmt.Fprintln(w, "\tMOVV\tR0, (R20)") + fmt.Fprintln(w, "\tADDV\t$8, R20") +@@ -190,7 +190,7 @@ func zeroLOONG64(w io.Writer) { + } + + func copyLOONG64(w io.Writer) { +- fmt.Fprintln(w, "TEXT runtime·duffcopy(SB), NOSPLIT|NOFRAME, $0-0") ++ fmt.Fprintln(w, "TEXT runtime·duffcopy(SB), NOSPLIT|NOFRAME, $0-0") + for i := 0; i < 128; i++ { + fmt.Fprintln(w, "\tMOVV\t(R20), R30") + fmt.Fprintln(w, "\tADDV\t$8, R20") +-- +2.38.1 + diff --git a/0078-runtime-support-regABI-and-add-spill-functions-in-ru.patch b/0078-runtime-support-regABI-and-add-spill-functions-in-ru.patch new file mode 100644 index 0000000..c86b7c4 --- /dev/null +++ b/0078-runtime-support-regABI-and-add-spill-functions-in-ru.patch @@ -0,0 +1,448 @@ +From 1687b48c49d741fa04cfd90fbe737320f761e8f5 Mon Sep 17 00:00:00 2001 +From: Guoqi Chen +Date: Tue, 15 Aug 2023 21:09:16 +0800 +Subject: [PATCH 16/30] runtime: support regABI and add spill functions in + runtime for loong64 + +Change-Id: I9786ffeaa3ca587280b4a4126f6f6409067f6c1d +--- + src/runtime/asm_loong64.s | 293 ++++++++++++++++++++++++++++------- + src/runtime/stubs_loong64.go | 8 + + 2 files changed, 243 insertions(+), 58 deletions(-) + +diff --git a/src/runtime/asm_loong64.s b/src/runtime/asm_loong64.s +index 4a21860316..cda90ca473 100644 +--- a/src/runtime/asm_loong64.s ++++ b/src/runtime/asm_loong64.s +@@ -72,7 +72,7 @@ nocgo: + MOVV R0, 1(R0) + RET + +-DATA runtime·mainPC+0(SB)/8,$runtime·main(SB) ++DATA runtime·mainPC+0(SB)/8,$runtime·main(SB) + GLOBL runtime·mainPC(SB),RODATA,$8 + + TEXT runtime·breakpoint(SB),NOSPLIT|NOFRAME,$0-0 +@@ -123,26 +123,31 @@ TEXT gogo<>(SB), NOSPLIT|NOFRAME, $0 + // Switch to m->g0's stack, call fn(g). + // Fn must never return. It should gogo(&g->sched) + // to keep running g. +-TEXT runtime·mcall(SB), NOSPLIT|NOFRAME, $0-8 ++TEXT runtime·mcall(SB), NOSPLIT|NOFRAME, $0-8 ++#ifdef GOEXPERIMENT_regabiargs ++ MOVV R4, REGCTXT ++#else ++ MOVV fn+0(FP), REGCTXT ++#endif ++ + // Save caller state in g->sched + MOVV R3, (g_sched+gobuf_sp)(g) + MOVV R1, (g_sched+gobuf_pc)(g) + MOVV R0, (g_sched+gobuf_lr)(g) + + // Switch to m->g0 & its stack, call fn. +- MOVV g, R19 +- MOVV g_m(g), R4 +- MOVV m_g0(R4), g ++ MOVV g, R4 // arg = g ++ MOVV g_m(g), R20 ++ MOVV m_g0(R20), g + JAL runtime·save_g(SB) +- BNE g, R19, 2(PC) ++ BNE g, R4, 2(PC) + JMP runtime·badmcall(SB) +- MOVV fn+0(FP), REGCTXT // context +- MOVV 0(REGCTXT), R5 // code pointer ++ MOVV 0(REGCTXT), R20 // code pointer + MOVV (g_sched+gobuf_sp)(g), R3 // sp = m->g0->sched.sp + ADDV $-16, R3 +- MOVV R19, 8(R3) ++ MOVV R4, 8(R3) + MOVV R0, 0(R3) +- JAL (R5) ++ JAL (R20) + JMP runtime·badmcall2(SB) + + // systemstack_switch is a dummy routine that systemstack leaves at the bottom +@@ -272,7 +277,7 @@ TEXT runtime·morestack_noctxt(SB),NOSPLIT|NOFRAME,$0-0 + JMP runtime·morestack(SB) + + // reflectcall: call a function with the given argument list +-// func call(argtype *_type, f *FuncVal, arg *byte, argsize, retoffset uint32). ++// func call(stackArgsType *_type, f *FuncVal, stackArgs *byte, stackArgsSize, stackRetOffset, frameSize uint32, regArgs *abi.RegArgs). + // we don't have variable-sized frames, so we use a small number + // of constant-sized-frame functions to encode a few bits of size in the pc. + // Caution: ugly multiline assembly macros in your future! +@@ -286,7 +291,7 @@ TEXT runtime·morestack_noctxt(SB),NOSPLIT|NOFRAME,$0-0 + // Note: can't just "BR NAME(SB)" - bad inlining results. + + TEXT ·reflectcall(SB), NOSPLIT|NOFRAME, $0-48 +- MOVWU stackArgsSize+24(FP), R19 ++ MOVWU frameSize+32(FP), R19 + DISPATCH(runtime·call32, 32) + DISPATCH(runtime·call64, 64) + DISPATCH(runtime·call128, 128) +@@ -317,7 +322,7 @@ TEXT ·reflectcall(SB), NOSPLIT|NOFRAME, $0-48 + JMP (R4) + + #define CALLFN(NAME,MAXSIZE) \ +-TEXT NAME(SB), WRAPPER, $MAXSIZE-24; \ ++TEXT NAME(SB), WRAPPER, $MAXSIZE-48; \ + NO_LOCAL_POINTERS; \ + /* copy arguments to stack */ \ + MOVV arg+16(FP), R4; \ +@@ -331,12 +336,17 @@ TEXT NAME(SB), WRAPPER, $MAXSIZE-24; \ + MOVBU R6, (R12); \ + ADDV $1, R12; \ + JMP -5(PC); \ ++ /* set up argument registers */ \ ++ MOVV regArgs+40(FP), R25; \ ++ JAL ·unspillArgs(SB); \ + /* call function */ \ + MOVV f+8(FP), REGCTXT; \ +- MOVV (REGCTXT), R6; \ ++ MOVV (REGCTXT), R25; \ + PCDATA $PCDATA_StackMapIndex, $0; \ +- JAL (R6); \ ++ JAL (R25); \ + /* copy return values back */ \ ++ MOVV regArgs+40(FP), R25; \ ++ JAL ·spillArgs(SB); \ + MOVV argtype+0(FP), R7; \ + MOVV arg+16(FP), R4; \ + MOVWU n+24(FP), R5; \ +@@ -352,11 +362,13 @@ TEXT NAME(SB), WRAPPER, $MAXSIZE-24; \ + // separate function so it can allocate stack space for the arguments + // to reflectcallmove. It does not follow the Go ABI; it expects its + // arguments in registers. +-TEXT callRet<>(SB), NOSPLIT, $32-0 ++TEXT callRet<>(SB), NOSPLIT, $40-0 ++ NO_LOCAL_POINTERS + MOVV R7, 8(R3) + MOVV R4, 16(R3) + MOVV R12, 24(R3) + MOVV R5, 32(R3) ++ MOVV R25, 40(R3) + JAL runtime·reflectcallmove(SB) + RET + +@@ -580,14 +592,14 @@ TEXT runtime·abort(SB),NOSPLIT|NOFRAME,$0-0 + UNDEF + + // AES hashing not implemented for loong64 +-TEXT runtime·memhash(SB),NOSPLIT|NOFRAME,$0-32 +- JMP runtime·memhashFallback(SB) +-TEXT runtime·strhash(SB),NOSPLIT|NOFRAME,$0-24 +- JMP runtime·strhashFallback(SB) +-TEXT runtime·memhash32(SB),NOSPLIT|NOFRAME,$0-24 +- JMP runtime·memhash32Fallback(SB) +-TEXT runtime·memhash64(SB),NOSPLIT|NOFRAME,$0-24 +- JMP runtime·memhash64Fallback(SB) ++TEXT runtime·memhash(SB),NOSPLIT|NOFRAME,$0-32 ++ JMP runtime·memhashFallback(SB) ++TEXT runtime·strhash(SB),NOSPLIT|NOFRAME,$0-24 ++ JMP runtime·strhashFallback(SB) ++TEXT runtime·memhash32(SB),NOSPLIT|NOFRAME,$0-24 ++ JMP runtime·memhash32Fallback(SB) ++TEXT runtime·memhash64(SB),NOSPLIT|NOFRAME,$0-24 ++ JMP runtime·memhash64Fallback(SB) + + TEXT runtime·return0(SB), NOSPLIT, $0 + MOVW $0, R19 +@@ -633,6 +645,86 @@ TEXT ·checkASM(SB),NOSPLIT,$0-1 + MOVB R19, ret+0(FP) + RET + ++#ifdef GOEXPERIMENT_regabiargs ++// spillArgs stores return values from registers to a *internal/abi.RegArgs in R25. ++TEXT ·spillArgs(SB),NOSPLIT,$0-0 ++ MOVV R4, (0*8)(R25) ++ MOVV R5, (1*8)(R25) ++ MOVV R6, (2*8)(R25) ++ MOVV R7, (3*8)(R25) ++ MOVV R8, (4*8)(R25) ++ MOVV R9, (5*8)(R25) ++ MOVV R10, (6*8)(R25) ++ MOVV R11, (7*8)(R25) ++ MOVV R12, (8*8)(R25) ++ MOVV R13, (9*8)(R25) ++ MOVV R14, (10*8)(R25) ++ MOVV R15, (11*8)(R25) ++ MOVV R16, (12*8)(R25) ++ MOVV R17, (13*8)(R25) ++ MOVV R18, (14*8)(R25) ++ MOVV R19, (15*8)(R25) ++ MOVD F0, (16*8)(R25) ++ MOVD F1, (17*8)(R25) ++ MOVD F2, (18*8)(R25) ++ MOVD F3, (19*8)(R25) ++ MOVD F4, (20*8)(R25) ++ MOVD F5, (21*8)(R25) ++ MOVD F6, (22*8)(R25) ++ MOVD F7, (23*8)(R25) ++ MOVD F8, (24*8)(R25) ++ MOVD F9, (25*8)(R25) ++ MOVD F10, (26*8)(R25) ++ MOVD F11, (27*8)(R25) ++ MOVD F12, (28*8)(R25) ++ MOVD F13, (29*8)(R25) ++ MOVD F14, (30*8)(R25) ++ MOVD F15, (31*8)(R25) ++ RET ++ ++// unspillArgs loads args into registers from a *internal/abi.RegArgs in R25. ++TEXT ·unspillArgs(SB),NOSPLIT,$0-0 ++ MOVV (0*8)(R25), R4 ++ MOVV (1*8)(R25), R5 ++ MOVV (2*8)(R25), R6 ++ MOVV (3*8)(R25), R7 ++ MOVV (4*8)(R25), R8 ++ MOVV (5*8)(R25), R9 ++ MOVV (6*8)(R25), R10 ++ MOVV (7*8)(R25), R11 ++ MOVV (8*8)(R25), R12 ++ MOVV (9*8)(R25), R13 ++ MOVV (10*8)(R25), R14 ++ MOVV (11*8)(R25), R15 ++ MOVV (12*8)(R25), R16 ++ MOVV (13*8)(R25), R17 ++ MOVV (14*8)(R25), R18 ++ MOVV (15*8)(R25), R19 ++ MOVD (16*8)(R25), F0 ++ MOVD (17*8)(R25), F1 ++ MOVD (18*8)(R25), F2 ++ MOVD (19*8)(R25), F3 ++ MOVD (20*8)(R25), F4 ++ MOVD (21*8)(R25), F5 ++ MOVD (22*8)(R25), F6 ++ MOVD (23*8)(R25), F7 ++ MOVD (24*8)(R25), F8 ++ MOVD (25*8)(R25), F9 ++ MOVD (26*8)(R25), F10 ++ MOVD (27*8)(R25), F11 ++ MOVD (28*8)(R25), F12 ++ MOVD (29*8)(R25), F13 ++ MOVD (30*8)(R25), F14 ++ MOVD (31*8)(R25), F15 ++ RET ++#else ++TEXT ·spillArgs(SB),NOSPLIT,$0-0 ++ RET ++ ++TEXT ·unspillArgs(SB),NOSPLIT,$0-0 ++ RET ++#endif ++ + // gcWriteBarrier performs a heap pointer write and informs the GC. + // + // gcWriteBarrier does NOT follow the Go ABI. It takes two arguments: +@@ -740,71 +832,156 @@ flush: + // in the caller's stack frame. These stubs write the args into that stack space and + // then tail call to the corresponding runtime handler. + // The tail call makes these stubs disappear in backtraces. +-TEXT runtime·panicIndex(SB),NOSPLIT,$0-16 ++TEXT runtime·panicIndex(SB),NOSPLIT,$0-16 ++#ifdef GOEXPERIMENT_regabiargs ++ MOVV R20, R4 ++ MOVV R21, R5 ++#else + MOVV R20, x+0(FP) + MOVV R21, y+8(FP) +- JMP runtime·goPanicIndex(SB) +-TEXT runtime·panicIndexU(SB),NOSPLIT,$0-16 ++#endif ++ JMP runtime·goPanicIndex(SB) ++TEXT runtime·panicIndexU(SB),NOSPLIT,$0-16 ++#ifdef GOEXPERIMENT_regabiargs ++ MOVV R20, R4 ++ MOVV R21, R5 ++#else + MOVV R20, x+0(FP) + MOVV R21, y+8(FP) +- JMP runtime·goPanicIndexU(SB) +-TEXT runtime·panicSliceAlen(SB),NOSPLIT,$0-16 ++#endif ++ JMP runtime·goPanicIndexU(SB) ++TEXT runtime·panicSliceAlen(SB),NOSPLIT,$0-16 ++#ifdef GOEXPERIMENT_regabiargs ++ MOVV R21, R4 ++ MOVV R23, R5 ++#else + MOVV R21, x+0(FP) + MOVV R23, y+8(FP) +- JMP runtime·goPanicSliceAlen(SB) +-TEXT runtime·panicSliceAlenU(SB),NOSPLIT,$0-16 ++#endif ++ JMP runtime·goPanicSliceAlen(SB) ++TEXT runtime·panicSliceAlenU(SB),NOSPLIT,$0-16 ++#ifdef GOEXPERIMENT_regabiargs ++ MOVV R21, R4 ++ MOVV R23, R5 ++#else + MOVV R21, x+0(FP) + MOVV R23, y+8(FP) +- JMP runtime·goPanicSliceAlenU(SB) +-TEXT runtime·panicSliceAcap(SB),NOSPLIT,$0-16 ++#endif ++ JMP runtime·goPanicSliceAlenU(SB) ++TEXT runtime·panicSliceAcap(SB),NOSPLIT,$0-16 ++#ifdef GOEXPERIMENT_regabiargs ++ MOVV R21, R4 ++ MOVV R23, R5 ++#else + MOVV R21, x+0(FP) + MOVV R23, y+8(FP) +- JMP runtime·goPanicSliceAcap(SB) +-TEXT runtime·panicSliceAcapU(SB),NOSPLIT,$0-16 ++#endif ++ JMP runtime·goPanicSliceAcap(SB) ++TEXT runtime·panicSliceAcapU(SB),NOSPLIT,$0-16 ++#ifdef GOEXPERIMENT_regabiargs ++ MOVV R21, R4 ++ MOVV R23, R5 ++#else + MOVV R21, x+0(FP) + MOVV R23, y+8(FP) +- JMP runtime·goPanicSliceAcapU(SB) +-TEXT runtime·panicSliceB(SB),NOSPLIT,$0-16 ++#endif ++ JMP runtime·goPanicSliceAcapU(SB) ++TEXT runtime·panicSliceB(SB),NOSPLIT,$0-16 ++#ifdef GOEXPERIMENT_regabiargs ++ MOVV R20, R4 ++ MOVV R21, R5 ++#else + MOVV R20, x+0(FP) + MOVV R21, y+8(FP) +- JMP runtime·goPanicSliceB(SB) +-TEXT runtime·panicSliceBU(SB),NOSPLIT,$0-16 ++#endif ++ JMP runtime·goPanicSliceB(SB) ++TEXT runtime·panicSliceBU(SB),NOSPLIT,$0-16 ++#ifdef GOEXPERIMENT_regabiargs ++ MOVV R20, R4 ++ MOVV R21, R5 ++#else + MOVV R20, x+0(FP) + MOVV R21, y+8(FP) +- JMP runtime·goPanicSliceBU(SB) +-TEXT runtime·panicSlice3Alen(SB),NOSPLIT,$0-16 ++#endif ++ JMP runtime·goPanicSliceBU(SB) ++TEXT runtime·panicSlice3Alen(SB),NOSPLIT,$0-16 ++#ifdef GOEXPERIMENT_regabiargs ++ MOVV R23, R4 ++ MOVV R24, R5 ++#else + MOVV R23, x+0(FP) + MOVV R24, y+8(FP) +- JMP runtime·goPanicSlice3Alen(SB) +-TEXT runtime·panicSlice3AlenU(SB),NOSPLIT,$0-16 ++#endif ++ JMP runtime·goPanicSlice3Alen(SB) ++TEXT runtime·panicSlice3AlenU(SB),NOSPLIT,$0-16 ++#ifdef GOEXPERIMENT_regabiargs ++ MOVV R23, R4 ++ MOVV R24, R5 ++#else + MOVV R23, x+0(FP) + MOVV R24, y+8(FP) +- JMP runtime·goPanicSlice3AlenU(SB) +-TEXT runtime·panicSlice3Acap(SB),NOSPLIT,$0-16 ++#endif ++ JMP runtime·goPanicSlice3AlenU(SB) ++TEXT runtime·panicSlice3Acap(SB),NOSPLIT,$0-16 ++#ifdef GOEXPERIMENT_regabiargs ++ MOVV R23, R4 ++ MOVV R24, R5 ++#else + MOVV R23, x+0(FP) + MOVV R24, y+8(FP) +- JMP runtime·goPanicSlice3Acap(SB) +-TEXT runtime·panicSlice3AcapU(SB),NOSPLIT,$0-16 ++#endif ++ JMP runtime·goPanicSlice3Acap(SB) ++TEXT runtime·panicSlice3AcapU(SB),NOSPLIT,$0-16 ++#ifdef GOEXPERIMENT_regabiargs ++ MOVV R23, R4 ++ MOVV R24, R5 ++#else + MOVV R23, x+0(FP) + MOVV R24, y+8(FP) +- JMP runtime·goPanicSlice3AcapU(SB) +-TEXT runtime·panicSlice3B(SB),NOSPLIT,$0-16 ++#endif ++ JMP runtime·goPanicSlice3AcapU(SB) ++TEXT runtime·panicSlice3B(SB),NOSPLIT,$0-16 ++#ifdef GOEXPERIMENT_regabiargs ++ MOVV R21, R4 ++ MOVV R23, R5 ++#else + MOVV R21, x+0(FP) + MOVV R23, y+8(FP) +- JMP runtime·goPanicSlice3B(SB) +-TEXT runtime·panicSlice3BU(SB),NOSPLIT,$0-16 ++#endif ++ JMP runtime·goPanicSlice3B(SB) ++TEXT runtime·panicSlice3BU(SB),NOSPLIT,$0-16 ++#ifdef GOEXPERIMENT_regabiargs ++ MOVV R21, R4 ++ MOVV R23, R5 ++#else + MOVV R21, x+0(FP) + MOVV R23, y+8(FP) +- JMP runtime·goPanicSlice3BU(SB) +-TEXT runtime·panicSlice3C(SB),NOSPLIT,$0-16 ++#endif ++ JMP runtime·goPanicSlice3BU(SB) ++TEXT runtime·panicSlice3C(SB),NOSPLIT,$0-16 ++#ifdef GOEXPERIMENT_regabiargs ++ MOVV R20, R4 ++ MOVV R21, R5 ++#else + MOVV R20, x+0(FP) + MOVV R21, y+8(FP) +- JMP runtime·goPanicSlice3C(SB) +-TEXT runtime·panicSlice3CU(SB),NOSPLIT,$0-16 ++#endif ++ JMP runtime·goPanicSlice3C(SB) ++TEXT runtime·panicSlice3CU(SB),NOSPLIT,$0-16 ++#ifdef GOEXPERIMENT_regabiargs ++ MOVV R20, R4 ++ MOVV R21, R5 ++#else + MOVV R20, x+0(FP) + MOVV R21, y+8(FP) +- JMP runtime·goPanicSlice3CU(SB) +-TEXT runtime·panicSliceConvert(SB),NOSPLIT,$0-16 ++#endif ++ JMP runtime·goPanicSlice3CU(SB) ++TEXT runtime·panicSliceConvert(SB),NOSPLIT,$0-16 ++#ifdef GOEXPERIMENT_regabiargs ++ MOVV R23, R4 ++ MOVV R24, R5 ++#else + MOVV R23, x+0(FP) + MOVV R24, y+8(FP) +- JMP runtime·goPanicSliceConvert(SB) ++#endif ++ JMP runtime·goPanicSliceConvert(SB) +diff --git a/src/runtime/stubs_loong64.go b/src/runtime/stubs_loong64.go +index 22366f508c..bb3df20421 100644 +--- a/src/runtime/stubs_loong64.go ++++ b/src/runtime/stubs_loong64.go +@@ -9,3 +9,11 @@ package runtime + // Called from assembly only; declared for go vet. + func load_g() + func save_g() ++ ++// Used by reflectcall and the reflect package. ++// ++// Spills/loads arguments in registers to/from an internal/abi.RegArgs ++// respectively. Does not follow the Go ABI. ++func spillArgs() ++func unspillArgs() ++ +-- +2.38.1 + diff --git a/0079-reflect-runtime-add-reflect-support-for-regABI-on-lo.patch b/0079-reflect-runtime-add-reflect-support-for-regABI-on-lo.patch new file mode 100644 index 0000000..6de96fc --- /dev/null +++ b/0079-reflect-runtime-add-reflect-support-for-regABI-on-lo.patch @@ -0,0 +1,130 @@ +From 5ff9ea06431efd6b35461e925b558cd426c99a73 Mon Sep 17 00:00:00 2001 +From: Guoqi Chen +Date: Wed, 16 Aug 2023 08:28:28 +0800 +Subject: [PATCH 17/30] reflect, runtime: add reflect support for regABI on + loong64 + +Change-Id: If355469bd716dbf08033d42319462b6cedaab884 +--- + src/reflect/asm_loong64.s | 77 ++++++++++++++++++++++++++++++++------- + src/runtime/stkframe.go | 2 +- + 2 files changed, 64 insertions(+), 15 deletions(-) + +diff --git a/src/reflect/asm_loong64.s b/src/reflect/asm_loong64.s +index 341a6d55c1..520f0afdd5 100644 +--- a/src/reflect/asm_loong64.s ++++ b/src/reflect/asm_loong64.s +@@ -7,34 +7,83 @@ + + #define REGCTXT R29 + ++// The frames of each of the two functions below contain two locals, at offsets ++// that are known to the runtime. ++// ++// The first local is a bool called retValid with a whole pointer-word reserved ++// for it on the stack. The purpose of this word is so that the runtime knows ++// whether the stack-allocated return space contains valid values for stack ++// scanning. ++// ++// The second local is an abi.RegArgs value whose offset is also known to the ++// runtime, so that a stack map for it can be constructed, since it contains ++// pointers visible to the GC. ++#define LOCAL_RETVALID 40 ++#define LOCAL_REGARGS 48 ++ ++// The frame size of the functions below is ++// 32 (args of callReflect) + 8 (bool + padding) + 392 (abi.RegArgs) = 432. ++ + // makeFuncStub is the code half of the function returned by MakeFunc. + // See the comment on the declaration of makeFuncStub in makefunc.go + // for more details. + // No arg size here, runtime pulls arg map out of the func value. +-TEXT ·makeFuncStub(SB),(NOSPLIT|WRAPPER),$40 ++TEXT ·makeFuncStub(SB),(NOSPLIT|WRAPPER),$432 + NO_LOCAL_POINTERS ++ ADDV $LOCAL_REGARGS, R3, R25 // spillArgs using R25 ++ JAL runtime·spillArgs(SB) ++ MOVV REGCTXT, 32(R3) // save REGCTXT > args of moveMakeFuncArgPtrs < LOCAL_REGARGS ++ ++#ifdef GOEXPERIMENT_regabiargs ++ MOVV REGCTXT, R4 ++ MOVV R25, R5 ++#else + MOVV REGCTXT, 8(R3) +- MOVV $argframe+0(FP), R19 +- MOVV R19, 16(R3) +- MOVB R0, 40(R3) +- ADDV $40, R3, R19 +- MOVV R19, 24(R3) +- MOVV R0, 32(R3) ++ MOVV R25, 16(R3) ++#endif ++ JAL ·moveMakeFuncArgPtrs(SB) ++ MOVV 32(R3), REGCTXT // restore REGCTXT ++ ++ MOVV REGCTXT, 8(R3) ++ MOVV $argframe+0(FP), R20 ++ MOVV R20, 16(R3) ++ MOVV R0, LOCAL_RETVALID(R3) ++ ADDV $LOCAL_RETVALID, R3, R20 ++ MOVV R20, 24(R3) ++ ADDV $LOCAL_REGARGS, R3, R20 ++ MOVV R20, 32(R3) + JAL ·callReflect(SB) ++ ADDV $LOCAL_REGARGS, R3, R25 //unspillArgs using R25 ++ JAL runtime·unspillArgs(SB) + RET + + // methodValueCall is the code half of the function returned by makeMethodValue. + // See the comment on the declaration of methodValueCall in makefunc.go + // for more details. + // No arg size here; runtime pulls arg map out of the func value. +-TEXT ·methodValueCall(SB),(NOSPLIT|WRAPPER),$40 ++TEXT ·methodValueCall(SB),(NOSPLIT|WRAPPER),$432 + NO_LOCAL_POINTERS ++ ADDV $LOCAL_REGARGS, R3, R25 // spillArgs using R25 ++ JAL runtime·spillArgs(SB) ++ MOVV REGCTXT, 32(R3) // save REGCTXT > args of moveMakeFuncArgPtrs < LOCAL_REGARGS ++#ifdef GOEXPERIMENT_regabiargs ++ MOVV REGCTXT, R4 ++ MOVV R25, R5 ++#else ++ MOVV REGCTXT, 8(R3) ++ MOVV R25, 16(R3) ++#endif ++ JAL ·moveMakeFuncArgPtrs(SB) ++ MOVV 32(R3), REGCTXT // restore REGCTXT + MOVV REGCTXT, 8(R3) +- MOVV $argframe+0(FP), R19 +- MOVV R19, 16(R3) +- MOVB R0, 40(R3) +- ADDV $40, R3, R19 +- MOVV R19, 24(R3) +- MOVV R0, 32(R3) ++ MOVV $argframe+0(FP), R20 ++ MOVV R20, 16(R3) ++ MOVB R0, LOCAL_RETVALID(R3) ++ ADDV $LOCAL_RETVALID, R3, R20 ++ MOVV R20, 24(R3) ++ ADDV $LOCAL_REGARGS, R3, R20 ++ MOVV R20, 32(R3) // frame size to 32+SP as callreflect args) + JAL ·callMethod(SB) ++ ADDV $LOCAL_REGARGS, R3, R25 // unspillArgs using R25 ++ JAL runtime·unspillArgs(SB) + RET +diff --git a/src/runtime/stkframe.go b/src/runtime/stkframe.go +index 3ecf3a828c..527db75b88 100644 +--- a/src/runtime/stkframe.go ++++ b/src/runtime/stkframe.go +@@ -234,7 +234,7 @@ func (frame *stkframe) getStackMap(cache *pcvalueCache, debug bool) (locals, arg + } + + // stack objects. +- if (GOARCH == "amd64" || GOARCH == "arm64" || GOARCH == "ppc64" || GOARCH == "ppc64le" || GOARCH == "riscv64") && ++ if (GOARCH == "amd64" || GOARCH == "arm64" || GOARCH == "loong64" || GOARCH == "ppc64" || GOARCH == "ppc64le" || GOARCH == "riscv64") && + unsafe.Sizeof(abi.RegArgs{}) > 0 && isReflect { + // For reflect.makeFuncStub and reflect.methodValueCall, + // we need to fake the stack object record. +-- +2.38.1 + diff --git a/0080-internal-bytealg-add-regABI-support-in-bytealg-funct.patch b/0080-internal-bytealg-add-regABI-support-in-bytealg-funct.patch new file mode 100644 index 0000000..52eb4ce --- /dev/null +++ b/0080-internal-bytealg-add-regABI-support-in-bytealg-funct.patch @@ -0,0 +1,304 @@ +From b34e459cedf1f60c0ce708519150c3b07e943f84 Mon Sep 17 00:00:00 2001 +From: Guoqi Chen +Date: Wed, 16 Aug 2023 08:55:13 +0800 +Subject: [PATCH 18/30] internal/bytealg: add regABI support in bytealg + functions on loong64 + +Change-Id: I4b71cffc9352a099b25879d64128fdc6e337e792 +--- + src/internal/bytealg/compare_loong64.s | 95 ++++++++++++++---------- + src/internal/bytealg/equal_loong64.s | 21 +++++- + src/internal/bytealg/indexbyte_loong64.s | 32 ++++++-- + 3 files changed, 101 insertions(+), 47 deletions(-) + +diff --git a/src/internal/bytealg/compare_loong64.s b/src/internal/bytealg/compare_loong64.s +index c89c5a9256..311449ab18 100644 +--- a/src/internal/bytealg/compare_loong64.s ++++ b/src/internal/bytealg/compare_loong64.s +@@ -5,83 +5,102 @@ + #include "go_asm.h" + #include "textflag.h" + +-TEXT ·Compare(SB),NOSPLIT,$0-56 +- MOVV a_base+0(FP), R6 +- MOVV b_base+24(FP), R7 +- MOVV a_len+8(FP), R4 +- MOVV b_len+32(FP), R5 ++TEXT ·Compare(SB),NOSPLIT,$0-56 ++#ifndef GOEXPERIMENT_regabiargs ++ MOVV a_base+0(FP), R4 ++ MOVV a_len+8(FP), R5 ++ MOVV b_base+24(FP), R6 ++ MOVV b_len+32(FP), R7 + MOVV $ret+48(FP), R13 ++#else ++ // R4 = a_base ++ // R5 = a_len ++ // R6 = a_cap (unused) ++ // R7 = b_base (want in R6) ++ // R8 = b_len (want in R7) ++ // R9 = b_cap (unused) ++ MOVV R7, R6 ++ MOVV R8, R7 ++#endif + JMP cmpbody<>(SB) + +-TEXT runtime·cmpstring(SB),NOSPLIT,$0-40 +- MOVV a_base+0(FP), R6 +- MOVV b_base+16(FP), R7 +- MOVV a_len+8(FP), R4 +- MOVV b_len+24(FP), R5 ++TEXT runtime·cmpstring(SB),NOSPLIT,$0-40 ++#ifndef GOEXPERIMENT_regabiargs ++ MOVV a_base+0(FP), R4 ++ MOVV b_base+16(FP), R6 ++ MOVV a_len+8(FP), R5 ++ MOVV b_len+24(FP), R7 + MOVV $ret+32(FP), R13 ++#endif ++ // R4 = a_base ++ // R5 = a_len ++ // R6 = b_base ++ // R7 = b_len + JMP cmpbody<>(SB) + + // On entry: +-// R4 length of a +-// R5 length of b +-// R6 points to the start of a +-// R7 points to the start of b ++// R5 length of a ++// R7 length of b ++// R4 points to the start of a ++// R6 points to the start of b + // R13 points to the return value (-1/0/1) + TEXT cmpbody<>(SB),NOSPLIT|NOFRAME,$0 +- BEQ R6, R7, samebytes // same start of a and b ++ BEQ R4, R6, samebytes // same start of a and b + +- SGTU R4, R5, R9 ++ SGTU R5, R7, R9 + BNE R0, R9, r2_lt_r1 +- MOVV R4, R14 ++ MOVV R5, R14 + JMP entry + r2_lt_r1: +- MOVV R5, R14 // R14 is min(R4, R5) ++ MOVV R7, R14 // R14 is min(R4, R5) + entry: +- ADDV R6, R14, R12 // R6 start of a, R14 end of a +- BEQ R6, R12, samebytes // length is 0 ++ ADDV R4, R14, R12 // R6 start of a, R14 end of a ++ BEQ R4, R12, samebytes // length is 0 + + SRLV $4, R14 // R14 is number of chunks + BEQ R0, R14, byte_loop + + // make sure both a and b are aligned. +- OR R6, R7, R15 ++ OR R4, R6, R15 + AND $7, R15 + BNE R0, R15, byte_loop + + PCALIGN $16 + chunk16_loop: + BEQ R0, R14, byte_loop +- MOVV (R6), R8 +- MOVV (R7), R9 ++ MOVV (R4), R8 ++ MOVV (R6), R9 + BNE R8, R9, byte_loop +- MOVV 8(R6), R16 +- MOVV 8(R7), R17 ++ MOVV 8(R4), R16 ++ MOVV 8(R6), R17 ++ ADDV $16, R4 + ADDV $16, R6 +- ADDV $16, R7 + SUBVU $1, R14 + BEQ R16, R17, chunk16_loop ++ SUBV $8, R4 + SUBV $8, R6 +- SUBV $8, R7 + + byte_loop: +- BEQ R6, R12, samebytes +- MOVBU (R6), R8 ++ BEQ R4, R12, samebytes ++ MOVBU (R4), R8 ++ ADDVU $1, R4 ++ MOVBU (R6), R9 + ADDVU $1, R6 +- MOVBU (R7), R9 +- ADDVU $1, R7 + BEQ R8, R9, byte_loop + + byte_cmp: +- SGTU R8, R9, R12 // R12 = 1 if (R8 > R9) +- BNE R0, R12, ret +- MOVV $-1, R12 ++ SGTU R8, R9, R4 // R12 = 1 if (R8 > R9) ++ BNE R0, R4, ret ++ MOVV $-1, R4 + JMP ret + + samebytes: +- SGTU R4, R5, R8 +- SGTU R5, R4, R9 +- SUBV R9, R8, R12 ++ SGTU R5, R7, R8 ++ SGTU R7, R5, R9 ++ SUBV R9, R8, R4 + + ret: +- MOVV R12, (R13) ++#ifndef GOEXPERIMENT_regabiargs ++ MOVV R4, (R13) ++#endif + RET +diff --git a/src/internal/bytealg/equal_loong64.s b/src/internal/bytealg/equal_loong64.s +index ba2a5578c3..a3ad5c1b35 100644 +--- a/src/internal/bytealg/equal_loong64.s ++++ b/src/internal/bytealg/equal_loong64.s +@@ -8,17 +8,21 @@ + #define REGCTXT R29 + + // memequal(a, b unsafe.Pointer, size uintptr) bool +-TEXT runtime·memequal(SB),NOSPLIT|NOFRAME,$0-25 ++TEXT runtime·memequal(SB),NOSPLIT|NOFRAME,$0-25 ++#ifndef GOEXPERIMENT_regabiargs + MOVV a+0(FP), R4 + MOVV b+8(FP), R5 +- BEQ R4, R5, eq + MOVV size+16(FP), R6 ++#endif ++ BEQ R4, R5, eq + ADDV R4, R6, R7 + PCALIGN $16 + loop: + BNE R4, R7, test + MOVV $1, R4 ++#ifndef GOEXPERIMENT_regabiargs + MOVB R4, ret+24(FP) ++#endif + RET + test: + MOVBU (R4), R9 +@@ -27,17 +31,24 @@ test: + ADDV $1, R5 + BEQ R9, R10, loop + ++ MOVB R0, R4 ++#ifndef GOEXPERIMENT_regabiargs + MOVB R0, ret+24(FP) ++#endif + RET + eq: + MOVV $1, R4 ++#ifndef GOEXPERIMENT_regabiargs + MOVB R4, ret+24(FP) ++#endif + RET + + // memequal_varlen(a, b unsafe.Pointer) bool +-TEXT runtime·memequal_varlen(SB),NOSPLIT,$40-17 ++TEXT runtime·memequal_varlen(SB),NOSPLIT,$40-17 ++#ifndef GOEXPERIMENT_regabiargs + MOVV a+0(FP), R4 + MOVV b+8(FP), R5 ++#endif + BEQ R4, R5, eq + MOVV 8(REGCTXT), R6 // compiler stores size at offset 8 in the closure + MOVV R4, 8(R3) +@@ -45,9 +56,13 @@ TEXT runtime·memequal_varlen(SB),NOSPLIT,$40-17 + MOVV R6, 24(R3) + JAL runtime·memequal(SB) + MOVBU 32(R3), R4 ++#ifndef GOEXPERIMENT_regabiargs + MOVB R4, ret+16(FP) ++#endif + RET + eq: + MOVV $1, R4 ++#ifndef GOEXPERIMENT_regabiargs + MOVB R4, ret+16(FP) ++#endif + RET +diff --git a/src/internal/bytealg/indexbyte_loong64.s b/src/internal/bytealg/indexbyte_loong64.s +index 604970549f..03e0660973 100644 +--- a/src/internal/bytealg/indexbyte_loong64.s ++++ b/src/internal/bytealg/indexbyte_loong64.s +@@ -5,11 +5,18 @@ + #include "go_asm.h" + #include "textflag.h" + +-TEXT ·IndexByte(SB),NOSPLIT,$0-40 ++TEXT ·IndexByte(SB),NOSPLIT,$0-40 ++#ifndef GOEXPERIMENT_regabiargs + MOVV b_base+0(FP), R4 + MOVV b_len+8(FP), R5 +- MOVBU c+24(FP), R6 // byte to find +- MOVV R4, R7 // store base for later ++ MOVBU c+24(FP), R7 // byte to find ++#endif ++ // R4 = b_base ++ // R5 = b_len ++ // R6 = b_cap (unused) ++ // R7 = byte to find ++ AND $0xff, R7 ++ MOVV R4, R6 // store base for later + ADDV R4, R5 // end + ADDV $-1, R4 + +@@ -18,21 +25,30 @@ loop: + ADDV $1, R4 + BEQ R4, R5, notfound + MOVBU (R4), R8 +- BNE R6, R8, loop ++ BNE R7, R8, loop + +- SUBV R7, R4 // remove base ++ SUBV R6, R4 // remove base ++#ifndef GOEXPERIMENT_regabiargs + MOVV R4, ret+32(FP) ++#endif + RET + + notfound: + MOVV $-1, R4 ++#ifndef GOEXPERIMENT_regabiargs + MOVV R4, ret+32(FP) ++#endif + RET + +-TEXT ·IndexByteString(SB),NOSPLIT,$0-32 ++TEXT ·IndexByteString(SB),NOSPLIT,$0-32 ++#ifndef GOEXPERIMENT_regabiargs + MOVV s_base+0(FP), R4 + MOVV s_len+8(FP), R5 + MOVBU c+16(FP), R6 // byte to find ++#endif ++ // R4 = s_base ++ // R5 = s_len ++ // R6 = byte to find + MOVV R4, R7 // store base for later + ADDV R4, R5 // end + ADDV $-1, R4 +@@ -45,10 +61,14 @@ loop: + BNE R6, R8, loop + + SUBV R7, R4 // remove base ++#ifndef GOEXPERIMENT_regabiargs + MOVV R4, ret+24(FP) ++#endif + RET + + notfound: + MOVV $-1, R4 ++#ifndef GOEXPERIMENT_regabiargs + MOVV R4, ret+24(FP) ++#endif + RET +-- +2.38.1 + diff --git a/0081-runtime-add-regABI-support-in-memclr-and-memmove-fun.patch b/0081-runtime-add-regABI-support-in-memclr-and-memmove-fun.patch new file mode 100644 index 0000000..9a5df53 --- /dev/null +++ b/0081-runtime-add-regABI-support-in-memclr-and-memmove-fun.patch @@ -0,0 +1,92 @@ +From 56fdf60cc13f6257bd82fd433c1001007b91b71b Mon Sep 17 00:00:00 2001 +From: Guoqi Chen +Date: Wed, 16 Aug 2023 09:05:30 +0800 +Subject: [PATCH 19/30] runtime: add regABI support in memclr and memmove + functions on loong64 + +Change-Id: Iae416015604826cd5e0c4573b64bfab8efa6017a +--- + src/runtime/memclr_loong64.s | 32 +++++++++++++++++--------------- + src/runtime/memmove_loong64.s | 4 +++- + 2 files changed, 20 insertions(+), 16 deletions(-) + +diff --git a/src/runtime/memclr_loong64.s b/src/runtime/memclr_loong64.s +index 7bb6f3dfc9..313e4d4f33 100644 +--- a/src/runtime/memclr_loong64.s ++++ b/src/runtime/memclr_loong64.s +@@ -6,37 +6,39 @@ + #include "textflag.h" + + // func memclrNoHeapPointers(ptr unsafe.Pointer, n uintptr) +-TEXT runtime·memclrNoHeapPointers(SB),NOSPLIT,$0-16 +- MOVV ptr+0(FP), R6 +- MOVV n+8(FP), R7 +- ADDV R6, R7, R4 ++TEXT runtime·memclrNoHeapPointers(SB),NOSPLIT,$0-16 ++#ifndef GOEXPERIMENT_regabiargs ++ MOVV ptr+0(FP), R4 ++ MOVV n+8(FP), R5 ++#endif ++ ADDV R4, R5, R6 + + // if less than 8 bytes, do one byte at a time +- SGTU $8, R7, R8 ++ SGTU $8, R5, R8 + BNE R8, out + + // do one byte at a time until 8-aligned +- AND $7, R6, R8 ++ AND $7, R4, R8 + BEQ R8, words +- MOVB R0, (R6) +- ADDV $1, R6 ++ MOVB R0, (R4) ++ ADDV $1, R4 + JMP -4(PC) + + words: + // do 8 bytes at a time if there is room +- ADDV $-7, R4, R7 ++ ADDV $-7, R6, R5 + + PCALIGN $16 +- SGTU R7, R6, R8 ++ SGTU R5, R4, R8 + BEQ R8, out +- MOVV R0, (R6) +- ADDV $8, R6 ++ MOVV R0, (R4) ++ ADDV $8, R4 + JMP -4(PC) + + out: +- BEQ R6, R4, done +- MOVB R0, (R6) +- ADDV $1, R6 ++ BEQ R4, R6, done ++ MOVB R0, (R4) ++ ADDV $1, R4 + JMP -3(PC) + done: + RET +diff --git a/src/runtime/memmove_loong64.s b/src/runtime/memmove_loong64.s +index 0f139bcc13..5b7aeba698 100644 +--- a/src/runtime/memmove_loong64.s ++++ b/src/runtime/memmove_loong64.s +@@ -7,10 +7,12 @@ + // See memmove Go doc for important implementation constraints. + + // func memmove(to, from unsafe.Pointer, n uintptr) +-TEXT runtime·memmove(SB), NOSPLIT|NOFRAME, $0-24 ++TEXT runtime·memmove(SB), NOSPLIT|NOFRAME, $0-24 ++#ifndef GOEXPERIMENT_regabiargs + MOVV to+0(FP), R4 + MOVV from+8(FP), R5 + MOVV n+16(FP), R6 ++#endif + BNE R6, check + RET + +-- +2.38.1 + diff --git a/0082-cmd-internal-obj-set-morestack-arg-spilling-and-rega.patch b/0082-cmd-internal-obj-set-morestack-arg-spilling-and-rega.patch new file mode 100644 index 0000000..0506435 --- /dev/null +++ b/0082-cmd-internal-obj-set-morestack-arg-spilling-and-rega.patch @@ -0,0 +1,57 @@ +From 6845fd9e11557565de8f1d465963c3aaa8088957 Mon Sep 17 00:00:00 2001 +From: Guoqi Chen +Date: Wed, 16 Aug 2023 09:16:21 +0800 +Subject: [PATCH 20/30] cmd/internal/obj: set morestack arg spilling and regabi + prologue on loong64 + +Change-Id: If963fa399c4a44be0c0d7856c653863f7b163506 +--- + src/cmd/internal/obj/loong64/obj.go | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +diff --git a/src/cmd/internal/obj/loong64/obj.go b/src/cmd/internal/obj/loong64/obj.go +index 803dd45de7..3e133c0c5a 100644 +--- a/src/cmd/internal/obj/loong64/obj.go ++++ b/src/cmd/internal/obj/loong64/obj.go +@@ -619,6 +619,10 @@ func (c *ctxt0) stacksplit(p *obj.Prog, framesize int32) *obj.Prog { + + p = c.ctxt.StartUnsafePoint(p, c.newprog) + ++ // Spill Arguments. This has to happen before we open ++ // any more frame space. ++ p = c.cursym.Func().SpillRegisterArgs(p, c.newprog) ++ + // MOV REGLINK, -8/-16(SP) + p = obj.Appendp(p, c.newprog) + p.As = mov +@@ -683,6 +687,8 @@ func (c *ctxt0) stacksplit(p *obj.Prog, framesize int32) *obj.Prog { + p.To.Reg = REGSP + p.Spadj = int32(-frameSize) + ++ // Unspill arguments ++ p = c.cursym.Func().UnspillRegisterArgs(p, c.newprog) + p = c.ctxt.EndUnsafePoint(p, c.newprog, -1) + } + +@@ -794,6 +800,10 @@ func (c *ctxt0) stacksplit(p *obj.Prog, framesize int32) *obj.Prog { + + p = c.ctxt.EmitEntryStackMap(c.cursym, p, c.newprog) + ++ // Spill the register args that could be clobbered by the ++ // morestack code ++ p = c.cursym.Func().SpillRegisterArgs(p, c.newprog) ++ + // JAL runtime.morestack(SB) + p = obj.Appendp(p, c.newprog) + +@@ -808,6 +818,7 @@ func (c *ctxt0) stacksplit(p *obj.Prog, framesize int32) *obj.Prog { + } + p.Mark |= BRANCH + ++ p = c.cursym.Func().UnspillRegisterArgs(p, c.newprog) + p = c.ctxt.EndUnsafePoint(p, c.newprog, -1) + + // JMP start +-- +2.38.1 + diff --git a/0083-cmd-compile-fix-If-lowering-on-loong64.patch b/0083-cmd-compile-fix-If-lowering-on-loong64.patch new file mode 100644 index 0000000..13bf9d7 --- /dev/null +++ b/0083-cmd-compile-fix-If-lowering-on-loong64.patch @@ -0,0 +1,89 @@ +From 035d2523f37bfd4d2aab041b2df19a5b2d410c13 Mon Sep 17 00:00:00 2001 +From: Guoqi Chen +Date: Wed, 16 Aug 2023 10:22:13 +0800 +Subject: [PATCH 21/30] cmd/compile: fix If lowering on loong64 + +Change-Id: I859e9d534fdf8b7e4d3aa16b330dbe09a2477eae +--- + .../compile/internal/ssa/_gen/LOONG64.rules | 3 ++- + .../compile/internal/ssa/rewriteLOONG64.go | 27 +++++++++++++++++-- + 2 files changed, 27 insertions(+), 3 deletions(-) + +diff --git a/src/cmd/compile/internal/ssa/_gen/LOONG64.rules b/src/cmd/compile/internal/ssa/_gen/LOONG64.rules +index b4bce73637..820193a256 100644 +--- a/src/cmd/compile/internal/ssa/_gen/LOONG64.rules ++++ b/src/cmd/compile/internal/ssa/_gen/LOONG64.rules +@@ -434,7 +434,7 @@ + (GetCallerSP ...) => (LoweredGetCallerSP ...) + (GetCallerPC ...) => (LoweredGetCallerPC ...) + +-(If cond yes no) => (NE cond yes no) ++(If cond yes no) => (NE (MOVBUreg cond) yes no) + + // Write barrier. + (WB ...) => (LoweredWB ...) +@@ -468,6 +468,7 @@ + (EQ (SGTconst [0] x) yes no) => (GEZ x yes no) + (NE (SGT x (MOVVconst [0])) yes no) => (GTZ x yes no) + (EQ (SGT x (MOVVconst [0])) yes no) => (LEZ x yes no) ++(MOVBUreg x:((SGT|SGTU) _ _)) => x + + // fold offset into address + (ADDVconst [off1] (MOVVaddr [off2] {sym} ptr)) && is32Bit(off1+int64(off2)) => (MOVVaddr [int32(off1)+int32(off2)] {sym} ptr) +diff --git a/src/cmd/compile/internal/ssa/rewriteLOONG64.go b/src/cmd/compile/internal/ssa/rewriteLOONG64.go +index 5c1d30b0bb..a3f41b31b7 100644 +--- a/src/cmd/compile/internal/ssa/rewriteLOONG64.go ++++ b/src/cmd/compile/internal/ssa/rewriteLOONG64.go +@@ -1823,6 +1823,26 @@ func rewriteValueLOONG64_OpLOONG64MOVBUload(v *Value) bool { + } + func rewriteValueLOONG64_OpLOONG64MOVBUreg(v *Value) bool { + v_0 := v.Args[0] ++ // match: (MOVBUreg x:(SGT _ _)) ++ // result: x ++ for { ++ x := v_0 ++ if x.Op != OpLOONG64SGT { ++ break ++ } ++ v.copyOf(x) ++ return true ++ } ++ // match: (MOVBUreg x:(SGTU _ _)) ++ // result: x ++ for { ++ x := v_0 ++ if x.Op != OpLOONG64SGTU { ++ break ++ } ++ v.copyOf(x) ++ return true ++ } + // match: (MOVBUreg x:(MOVBUload _ _)) + // result: (MOVVreg x) + for { +@@ -7695,6 +7715,7 @@ func rewriteValueLOONG64_OpZero(v *Value) bool { + return false + } + func rewriteBlockLOONG64(b *Block) bool { ++ typ := &b.Func.Config.Types + switch b.Kind { + case BlockLOONG64EQ: + // match: (EQ (FPFlagTrue cmp) yes no) +@@ -7894,10 +7915,12 @@ func rewriteBlockLOONG64(b *Block) bool { + } + case BlockIf: + // match: (If cond yes no) +- // result: (NE cond yes no) ++ // result: (NE (MOVBUreg cond) yes no) + for { + cond := b.Controls[0] +- b.resetWithControl(BlockLOONG64NE, cond) ++ v0 := b.NewValue0(cond.Pos, OpLOONG64MOVBUreg, typ.UInt64) ++ v0.AddArg(cond) ++ b.resetWithControl(BlockLOONG64NE, v0) + return true + } + case BlockLOONG64LEZ: +-- +2.38.1 + diff --git a/0084-runtime-internal-syscall-use-ABIInternal-for-Syscall.patch b/0084-runtime-internal-syscall-use-ABIInternal-for-Syscall.patch new file mode 100644 index 0000000..c4006b1 --- /dev/null +++ b/0084-runtime-internal-syscall-use-ABIInternal-for-Syscall.patch @@ -0,0 +1,84 @@ +From 52326434c2d584ef3f762e50722aaee64bdb3b47 Mon Sep 17 00:00:00 2001 +From: Guoqi Chen +Date: Tue, 22 Aug 2023 19:50:03 +0800 +Subject: [PATCH 22/30] runtime/internal/syscall: use ABIInternal for Syscall6 + on loong64 + +Change-Id: I472b673e4f0d6de5c524c19936d4164971f7764b +--- + .../internal/syscall/asm_linux_loong64.s | 41 ++++++++++++++++++- + 1 file changed, 40 insertions(+), 1 deletion(-) + +diff --git a/src/runtime/internal/syscall/asm_linux_loong64.s b/src/runtime/internal/syscall/asm_linux_loong64.s +index d6a33f90a7..11c5bc2468 100644 +--- a/src/runtime/internal/syscall/asm_linux_loong64.s ++++ b/src/runtime/internal/syscall/asm_linux_loong64.s +@@ -5,7 +5,32 @@ + #include "textflag.h" + + // func Syscall6(num, a1, a2, a3, a4, a5, a6 uintptr) (r1, r2, errno uintptr) +-TEXT ·Syscall6(SB),NOSPLIT,$0-80 ++// ++// We need to convert to the syscall ABI. ++// ++// arg | ABIInternal | Syscall ++// --------------------------- ++// num | R4 | R11 ++// a1 | R5 | R4 ++// a2 | R6 | R5 ++// a3 | R7 | R6 ++// a4 | R8 | R7 ++// a5 | R9 | R8 ++// a6 | R10 | R9 ++// ++// r1 | R4 | R4 ++// r2 | R5 | R5 ++// err | R6 | part of R4 ++TEXT ·Syscall6(SB),NOSPLIT,$0-80 ++#ifdef GOEXPERIMENT_regabiargs ++ MOVV R4, R11 // syscall entry ++ MOVV R5, R4 ++ MOVV R6, R5 ++ MOVV R7, R6 ++ MOVV R8, R7 ++ MOVV R9, R8 ++ MOVV R10, R9 ++#else + MOVV num+0(FP), R11 // syscall entry + MOVV a1+8(FP), R4 + MOVV a2+16(FP), R5 +@@ -13,7 +38,15 @@ TEXT ·Syscall6(SB),NOSPLIT,$0-80 + MOVV a4+32(FP), R7 + MOVV a5+40(FP), R8 + MOVV a6+48(FP), R9 ++#endif + SYSCALL ++#ifdef GOEXPERIMENT_regabiargs ++ MOVV R0, R5 // r2 is not used. Always set to 0. ++ MOVW $-4096, R12 ++ BGEU R12, R4, ok ++ SUBVU R4, R0, R6 // errno ++ MOVV $-1, R4 // r1 ++#else + MOVW $-4096, R12 + BGEU R12, R4, ok + MOVV $-1, R12 +@@ -21,9 +54,15 @@ TEXT ·Syscall6(SB),NOSPLIT,$0-80 + MOVV R0, r2+64(FP) + SUBVU R4, R0, R4 + MOVV R4, errno+72(FP) ++#endif + RET + ok: ++#ifdef GOEXPERIMENT_regabiargs ++ // r1 already in R4 ++ MOVV R0, R6 // errno ++#else + MOVV R4, r1+56(FP) + MOVV R0, r2+64(FP) // r2 is not used. Always set to 0. + MOVV R0, errno+72(FP) ++#endif + RET +-- +2.38.1 + diff --git a/0085-cmd-compile-internal-buildcfg-enable-regABI-on-loong.patch b/0085-cmd-compile-internal-buildcfg-enable-regABI-on-loong.patch new file mode 100644 index 0000000..9269f04 --- /dev/null +++ b/0085-cmd-compile-internal-buildcfg-enable-regABI-on-loong.patch @@ -0,0 +1,66 @@ +From b1fedf19694befd18ac63bca9ed0cbba272394b5 Mon Sep 17 00:00:00 2001 +From: Guoqi Chen +Date: Wed, 16 Aug 2023 10:39:38 +0800 +Subject: [PATCH 23/30] cmd/compile, internal/buildcfg: enable regABI on + loong64, and add loong64 in test func hasRegisterABI + +Change-Id: I6881258971f3c68f05583500a5e5cafc740de421 +--- + src/cmd/compile/internal/ssa/config.go | 4 ++-- + src/cmd/compile/internal/ssa/debug_lines_test.go | 2 +- + src/internal/buildcfg/exp.go | 4 +++- + 3 files changed, 6 insertions(+), 4 deletions(-) + +diff --git a/src/cmd/compile/internal/ssa/config.go b/src/cmd/compile/internal/ssa/config.go +index 98a78e0c4a..c5aafdc037 100644 +--- a/src/cmd/compile/internal/ssa/config.go ++++ b/src/cmd/compile/internal/ssa/config.go +@@ -278,8 +278,8 @@ func NewConfig(arch string, types Types, ctxt *obj.Link, optimize, softfloat boo + c.registers = registersLOONG64[:] + c.gpRegMask = gpRegMaskLOONG64 + c.fpRegMask = fpRegMaskLOONG64 +- // c.intParamRegs = paramIntRegLOONG64 +- // c.floatParamRegs = paramFloatRegLOONG64 ++ c.intParamRegs = paramIntRegLOONG64 ++ c.floatParamRegs = paramFloatRegLOONG64 + c.FPReg = framepointerRegLOONG64 + c.LinkReg = linkRegLOONG64 + c.hasGReg = true +diff --git a/src/cmd/compile/internal/ssa/debug_lines_test.go b/src/cmd/compile/internal/ssa/debug_lines_test.go +index 6678a96e77..03ae306146 100644 +--- a/src/cmd/compile/internal/ssa/debug_lines_test.go ++++ b/src/cmd/compile/internal/ssa/debug_lines_test.go +@@ -45,7 +45,7 @@ func testGoArch() string { + + func hasRegisterABI() bool { + switch testGoArch() { +- case "amd64", "arm64", "ppc64", "ppc64le", "riscv": ++ case "amd64", "arm64", "loong64", "ppc64", "ppc64le", "riscv": + return true + } + return false +diff --git a/src/internal/buildcfg/exp.go b/src/internal/buildcfg/exp.go +index 71f8f5648d..7f8d9a4d77 100644 +--- a/src/internal/buildcfg/exp.go ++++ b/src/internal/buildcfg/exp.go +@@ -65,6 +65,8 @@ func ParseGOEXPERIMENT(goos, goarch, goexp string) (*ExperimentFlags, error) { + case "amd64", "arm64", "ppc64le", "ppc64", "riscv64": + regabiAlwaysOn = true + regabiSupported = true ++ case "loong64": ++ regabiSupported = true + } + + baseline := goexperiment.Flags{ +@@ -130,7 +132,7 @@ func ParseGOEXPERIMENT(goos, goarch, goexp string) (*ExperimentFlags, error) { + flags.RegabiWrappers = true + flags.RegabiArgs = true + } +- // regabi is only supported on amd64, arm64, riscv64, ppc64 and ppc64le. ++ // regabi is only supported on amd64, arm64, loong64, riscv64, ppc64 and ppc64le. + if !regabiSupported { + flags.RegabiWrappers = false + flags.RegabiArgs = false +-- +2.38.1 + diff --git a/0086-internal-abi-internal-buildcfg-always-enable-registe.patch b/0086-internal-abi-internal-buildcfg-always-enable-registe.patch new file mode 100644 index 0000000..1e11c91 --- /dev/null +++ b/0086-internal-abi-internal-buildcfg-always-enable-registe.patch @@ -0,0 +1,59 @@ +From bad1641e43bcbf881cab8426b68911cef5c7a9d1 Mon Sep 17 00:00:00 2001 +From: Guoqi Chen +Date: Wed, 30 Aug 2023 17:08:22 +0800 +Subject: [PATCH 24/30] internal/abi, internal/buildcfg: always enable register + ABI on loong64 + +Change-Id: Ie788e36c203dab1c4dd4a874a44f56641d9446da +--- + src/internal/abi/abi_generic.go | 2 +- + src/internal/abi/abi_loong64.go | 2 -- + src/internal/buildcfg/exp.go | 4 +--- + 3 files changed, 2 insertions(+), 6 deletions(-) + +diff --git a/src/internal/abi/abi_generic.go b/src/internal/abi/abi_generic.go +index 76ef2e2898..a08d3208d4 100644 +--- a/src/internal/abi/abi_generic.go ++++ b/src/internal/abi/abi_generic.go +@@ -2,7 +2,7 @@ + // Use of this source code is governed by a BSD-style + // license that can be found in the LICENSE file. + +-//go:build !goexperiment.regabiargs && !amd64 && !arm64 && !ppc64 && !ppc64le && !riscv64 ++//go:build !goexperiment.regabiargs && !amd64 && !arm64 && !loong64 && !ppc64 && !ppc64le && !riscv64 + + package abi + +diff --git a/src/internal/abi/abi_loong64.go b/src/internal/abi/abi_loong64.go +index c2306ae8d8..10ad89815b 100644 +--- a/src/internal/abi/abi_loong64.go ++++ b/src/internal/abi/abi_loong64.go +@@ -2,8 +2,6 @@ + // Use of this source code is governed by a BSD-style + // license that can be found in the LICENSE file. + +-//go:build goexperiment.regabiargs +- + package abi + + const ( +diff --git a/src/internal/buildcfg/exp.go b/src/internal/buildcfg/exp.go +index 7f8d9a4d77..4b47090ca4 100644 +--- a/src/internal/buildcfg/exp.go ++++ b/src/internal/buildcfg/exp.go +@@ -62,11 +62,9 @@ func ParseGOEXPERIMENT(goos, goarch, goexp string) (*ExperimentFlags, error) { + // always on. + var regabiSupported, regabiAlwaysOn bool + switch goarch { +- case "amd64", "arm64", "ppc64le", "ppc64", "riscv64": ++ case "amd64", "arm64", "loong64", "ppc64le", "ppc64", "riscv64": + regabiAlwaysOn = true + regabiSupported = true +- case "loong64": +- regabiSupported = true + } + + baseline := goexperiment.Flags{ +-- +2.38.1 + diff --git a/0087-all-delete-loong64-non-register-ABI-fallback-path.patch b/0087-all-delete-loong64-non-register-ABI-fallback-path.patch new file mode 100644 index 0000000..cbb0281 --- /dev/null +++ b/0087-all-delete-loong64-non-register-ABI-fallback-path.patch @@ -0,0 +1,493 @@ +From b2df2cb1acaa382cbf8d796c4f4487331e28261d Mon Sep 17 00:00:00 2001 +From: Guoqi Chen +Date: Wed, 30 Aug 2023 17:49:55 +0800 +Subject: [PATCH 25/30] all: delete loong64 non-register ABI fallback path + +Change-Id: Iff4daa8d8d60765aa1f78c8c9f984214ea9c9159 +--- + src/internal/bytealg/compare_loong64.s | 18 ---- + src/internal/bytealg/equal_loong64.s | 24 ----- + src/internal/bytealg/indexbyte_loong64.s | 22 ----- + src/reflect/asm_loong64.s | 10 -- + src/runtime/asm_loong64.s | 98 ------------------- + .../internal/syscall/asm_linux_loong64.s | 26 ----- + src/runtime/memclr_loong64.s | 4 - + src/runtime/memmove_loong64.s | 5 - + 8 files changed, 207 deletions(-) + +diff --git a/src/internal/bytealg/compare_loong64.s b/src/internal/bytealg/compare_loong64.s +index 311449ab18..df72a1122b 100644 +--- a/src/internal/bytealg/compare_loong64.s ++++ b/src/internal/bytealg/compare_loong64.s +@@ -6,13 +6,6 @@ + #include "textflag.h" + + TEXT ·Compare(SB),NOSPLIT,$0-56 +-#ifndef GOEXPERIMENT_regabiargs +- MOVV a_base+0(FP), R4 +- MOVV a_len+8(FP), R5 +- MOVV b_base+24(FP), R6 +- MOVV b_len+32(FP), R7 +- MOVV $ret+48(FP), R13 +-#else + // R4 = a_base + // R5 = a_len + // R6 = a_cap (unused) +@@ -21,17 +14,9 @@ TEXT ·Compare(SB),NOSPLIT,$0-56 + // R9 = b_cap (unused) + MOVV R7, R6 + MOVV R8, R7 +-#endif + JMP cmpbody<>(SB) + + TEXT runtime·cmpstring(SB),NOSPLIT,$0-40 +-#ifndef GOEXPERIMENT_regabiargs +- MOVV a_base+0(FP), R4 +- MOVV b_base+16(FP), R6 +- MOVV a_len+8(FP), R5 +- MOVV b_len+24(FP), R7 +- MOVV $ret+32(FP), R13 +-#endif + // R4 = a_base + // R5 = a_len + // R6 = b_base +@@ -100,7 +85,4 @@ samebytes: + SUBV R9, R8, R4 + + ret: +-#ifndef GOEXPERIMENT_regabiargs +- MOVV R4, (R13) +-#endif + RET +diff --git a/src/internal/bytealg/equal_loong64.s b/src/internal/bytealg/equal_loong64.s +index a3ad5c1b35..830b09bd2c 100644 +--- a/src/internal/bytealg/equal_loong64.s ++++ b/src/internal/bytealg/equal_loong64.s +@@ -9,20 +9,12 @@ + + // memequal(a, b unsafe.Pointer, size uintptr) bool + TEXT runtime·memequal(SB),NOSPLIT|NOFRAME,$0-25 +-#ifndef GOEXPERIMENT_regabiargs +- MOVV a+0(FP), R4 +- MOVV b+8(FP), R5 +- MOVV size+16(FP), R6 +-#endif + BEQ R4, R5, eq + ADDV R4, R6, R7 + PCALIGN $16 + loop: + BNE R4, R7, test + MOVV $1, R4 +-#ifndef GOEXPERIMENT_regabiargs +- MOVB R4, ret+24(FP) +-#endif + RET + test: + MOVBU (R4), R9 +@@ -32,23 +24,13 @@ test: + BEQ R9, R10, loop + + MOVB R0, R4 +-#ifndef GOEXPERIMENT_regabiargs +- MOVB R0, ret+24(FP) +-#endif + RET + eq: + MOVV $1, R4 +-#ifndef GOEXPERIMENT_regabiargs +- MOVB R4, ret+24(FP) +-#endif + RET + + // memequal_varlen(a, b unsafe.Pointer) bool + TEXT runtime·memequal_varlen(SB),NOSPLIT,$40-17 +-#ifndef GOEXPERIMENT_regabiargs +- MOVV a+0(FP), R4 +- MOVV b+8(FP), R5 +-#endif + BEQ R4, R5, eq + MOVV 8(REGCTXT), R6 // compiler stores size at offset 8 in the closure + MOVV R4, 8(R3) +@@ -56,13 +38,7 @@ TEXT runtime·memequal_varlen(SB),NOSPLIT,$40-17 + MOVV R6, 24(R3) + JAL runtime·memequal(SB) + MOVBU 32(R3), R4 +-#ifndef GOEXPERIMENT_regabiargs +- MOVB R4, ret+16(FP) +-#endif + RET + eq: + MOVV $1, R4 +-#ifndef GOEXPERIMENT_regabiargs +- MOVB R4, ret+16(FP) +-#endif + RET +diff --git a/src/internal/bytealg/indexbyte_loong64.s b/src/internal/bytealg/indexbyte_loong64.s +index 03e0660973..c9591b3cda 100644 +--- a/src/internal/bytealg/indexbyte_loong64.s ++++ b/src/internal/bytealg/indexbyte_loong64.s +@@ -6,11 +6,6 @@ + #include "textflag.h" + + TEXT ·IndexByte(SB),NOSPLIT,$0-40 +-#ifndef GOEXPERIMENT_regabiargs +- MOVV b_base+0(FP), R4 +- MOVV b_len+8(FP), R5 +- MOVBU c+24(FP), R7 // byte to find +-#endif + // R4 = b_base + // R5 = b_len + // R6 = b_cap (unused) +@@ -28,24 +23,13 @@ loop: + BNE R7, R8, loop + + SUBV R6, R4 // remove base +-#ifndef GOEXPERIMENT_regabiargs +- MOVV R4, ret+32(FP) +-#endif + RET + + notfound: + MOVV $-1, R4 +-#ifndef GOEXPERIMENT_regabiargs +- MOVV R4, ret+32(FP) +-#endif + RET + + TEXT ·IndexByteString(SB),NOSPLIT,$0-32 +-#ifndef GOEXPERIMENT_regabiargs +- MOVV s_base+0(FP), R4 +- MOVV s_len+8(FP), R5 +- MOVBU c+16(FP), R6 // byte to find +-#endif + // R4 = s_base + // R5 = s_len + // R6 = byte to find +@@ -61,14 +45,8 @@ loop: + BNE R6, R8, loop + + SUBV R7, R4 // remove base +-#ifndef GOEXPERIMENT_regabiargs +- MOVV R4, ret+24(FP) +-#endif + RET + + notfound: + MOVV $-1, R4 +-#ifndef GOEXPERIMENT_regabiargs +- MOVV R4, ret+24(FP) +-#endif + RET +diff --git a/src/reflect/asm_loong64.s b/src/reflect/asm_loong64.s +index 520f0afdd5..c0dc244497 100644 +--- a/src/reflect/asm_loong64.s ++++ b/src/reflect/asm_loong64.s +@@ -34,13 +34,8 @@ TEXT ·makeFuncStub(SB),(NOSPLIT|WRAPPER),$432 + JAL runtime·spillArgs(SB) + MOVV REGCTXT, 32(R3) // save REGCTXT > args of moveMakeFuncArgPtrs < LOCAL_REGARGS + +-#ifdef GOEXPERIMENT_regabiargs + MOVV REGCTXT, R4 + MOVV R25, R5 +-#else +- MOVV REGCTXT, 8(R3) +- MOVV R25, 16(R3) +-#endif + JAL ·moveMakeFuncArgPtrs(SB) + MOVV 32(R3), REGCTXT // restore REGCTXT + +@@ -66,13 +61,8 @@ TEXT ·methodValueCall(SB),(NOSPLIT|WRAPPER),$432 + ADDV $LOCAL_REGARGS, R3, R25 // spillArgs using R25 + JAL runtime·spillArgs(SB) + MOVV REGCTXT, 32(R3) // save REGCTXT > args of moveMakeFuncArgPtrs < LOCAL_REGARGS +-#ifdef GOEXPERIMENT_regabiargs + MOVV REGCTXT, R4 + MOVV R25, R5 +-#else +- MOVV REGCTXT, 8(R3) +- MOVV R25, 16(R3) +-#endif + JAL ·moveMakeFuncArgPtrs(SB) + MOVV 32(R3), REGCTXT // restore REGCTXT + MOVV REGCTXT, 8(R3) +diff --git a/src/runtime/asm_loong64.s b/src/runtime/asm_loong64.s +index cda90ca473..11ff884d43 100644 +--- a/src/runtime/asm_loong64.s ++++ b/src/runtime/asm_loong64.s +@@ -124,12 +124,7 @@ TEXT gogo<>(SB), NOSPLIT|NOFRAME, $0 + // Fn must never return. It should gogo(&g->sched) + // to keep running g. + TEXT runtime·mcall(SB), NOSPLIT|NOFRAME, $0-8 +-#ifdef GOEXPERIMENT_regabiargs + MOVV R4, REGCTXT +-#else +- MOVV fn+0(FP), REGCTXT +-#endif +- + // Save caller state in g->sched + MOVV R3, (g_sched+gobuf_sp)(g) + MOVV R1, (g_sched+gobuf_pc)(g) +@@ -645,7 +640,6 @@ TEXT ·checkASM(SB),NOSPLIT,$0-1 + MOVB R19, ret+0(FP) + RET + +-#ifdef GOEXPERIMENT_regabiargs + // spillArgs stores return values from registers to a *internal/abi.RegArgs in R25. + TEXT ·spillArgs(SB),NOSPLIT,$0-0 + MOVV R4, (0*8)(R25) +@@ -717,13 +711,6 @@ TEXT ·unspillArgs(SB),NOSPLIT,$0-0 + MOVD (30*8)(R25), F14 + MOVD (31*8)(R25), F15 + RET +-#else +-TEXT ·spillArgs(SB),NOSPLIT,$0-0 +- RET +- +-TEXT ·unspillArgs(SB),NOSPLIT,$0-0 +- RET +-#endif + + // gcWriteBarrier performs a heap pointer write and informs the GC. + // +@@ -833,155 +820,70 @@ flush: + // then tail call to the corresponding runtime handler. + // The tail call makes these stubs disappear in backtraces. + TEXT runtime·panicIndex(SB),NOSPLIT,$0-16 +-#ifdef GOEXPERIMENT_regabiargs + MOVV R20, R4 + MOVV R21, R5 +-#else +- MOVV R20, x+0(FP) +- MOVV R21, y+8(FP) +-#endif + JMP runtime·goPanicIndex(SB) + TEXT runtime·panicIndexU(SB),NOSPLIT,$0-16 +-#ifdef GOEXPERIMENT_regabiargs + MOVV R20, R4 + MOVV R21, R5 +-#else +- MOVV R20, x+0(FP) +- MOVV R21, y+8(FP) +-#endif + JMP runtime·goPanicIndexU(SB) + TEXT runtime·panicSliceAlen(SB),NOSPLIT,$0-16 +-#ifdef GOEXPERIMENT_regabiargs + MOVV R21, R4 + MOVV R23, R5 +-#else +- MOVV R21, x+0(FP) +- MOVV R23, y+8(FP) +-#endif + JMP runtime·goPanicSliceAlen(SB) + TEXT runtime·panicSliceAlenU(SB),NOSPLIT,$0-16 +-#ifdef GOEXPERIMENT_regabiargs + MOVV R21, R4 + MOVV R23, R5 +-#else +- MOVV R21, x+0(FP) +- MOVV R23, y+8(FP) +-#endif + JMP runtime·goPanicSliceAlenU(SB) + TEXT runtime·panicSliceAcap(SB),NOSPLIT,$0-16 +-#ifdef GOEXPERIMENT_regabiargs + MOVV R21, R4 + MOVV R23, R5 +-#else +- MOVV R21, x+0(FP) +- MOVV R23, y+8(FP) +-#endif + JMP runtime·goPanicSliceAcap(SB) + TEXT runtime·panicSliceAcapU(SB),NOSPLIT,$0-16 +-#ifdef GOEXPERIMENT_regabiargs + MOVV R21, R4 + MOVV R23, R5 +-#else +- MOVV R21, x+0(FP) +- MOVV R23, y+8(FP) +-#endif + JMP runtime·goPanicSliceAcapU(SB) + TEXT runtime·panicSliceB(SB),NOSPLIT,$0-16 +-#ifdef GOEXPERIMENT_regabiargs + MOVV R20, R4 + MOVV R21, R5 +-#else +- MOVV R20, x+0(FP) +- MOVV R21, y+8(FP) +-#endif + JMP runtime·goPanicSliceB(SB) + TEXT runtime·panicSliceBU(SB),NOSPLIT,$0-16 +-#ifdef GOEXPERIMENT_regabiargs + MOVV R20, R4 + MOVV R21, R5 +-#else +- MOVV R20, x+0(FP) +- MOVV R21, y+8(FP) +-#endif + JMP runtime·goPanicSliceBU(SB) + TEXT runtime·panicSlice3Alen(SB),NOSPLIT,$0-16 +-#ifdef GOEXPERIMENT_regabiargs + MOVV R23, R4 + MOVV R24, R5 +-#else +- MOVV R23, x+0(FP) +- MOVV R24, y+8(FP) +-#endif + JMP runtime·goPanicSlice3Alen(SB) + TEXT runtime·panicSlice3AlenU(SB),NOSPLIT,$0-16 +-#ifdef GOEXPERIMENT_regabiargs + MOVV R23, R4 + MOVV R24, R5 +-#else +- MOVV R23, x+0(FP) +- MOVV R24, y+8(FP) +-#endif + JMP runtime·goPanicSlice3AlenU(SB) + TEXT runtime·panicSlice3Acap(SB),NOSPLIT,$0-16 +-#ifdef GOEXPERIMENT_regabiargs + MOVV R23, R4 + MOVV R24, R5 +-#else +- MOVV R23, x+0(FP) +- MOVV R24, y+8(FP) +-#endif + JMP runtime·goPanicSlice3Acap(SB) + TEXT runtime·panicSlice3AcapU(SB),NOSPLIT,$0-16 +-#ifdef GOEXPERIMENT_regabiargs + MOVV R23, R4 + MOVV R24, R5 +-#else +- MOVV R23, x+0(FP) +- MOVV R24, y+8(FP) +-#endif + JMP runtime·goPanicSlice3AcapU(SB) + TEXT runtime·panicSlice3B(SB),NOSPLIT,$0-16 +-#ifdef GOEXPERIMENT_regabiargs + MOVV R21, R4 + MOVV R23, R5 +-#else +- MOVV R21, x+0(FP) +- MOVV R23, y+8(FP) +-#endif + JMP runtime·goPanicSlice3B(SB) + TEXT runtime·panicSlice3BU(SB),NOSPLIT,$0-16 +-#ifdef GOEXPERIMENT_regabiargs + MOVV R21, R4 + MOVV R23, R5 +-#else +- MOVV R21, x+0(FP) +- MOVV R23, y+8(FP) +-#endif + JMP runtime·goPanicSlice3BU(SB) + TEXT runtime·panicSlice3C(SB),NOSPLIT,$0-16 +-#ifdef GOEXPERIMENT_regabiargs + MOVV R20, R4 + MOVV R21, R5 +-#else +- MOVV R20, x+0(FP) +- MOVV R21, y+8(FP) +-#endif + JMP runtime·goPanicSlice3C(SB) + TEXT runtime·panicSlice3CU(SB),NOSPLIT,$0-16 +-#ifdef GOEXPERIMENT_regabiargs + MOVV R20, R4 + MOVV R21, R5 +-#else +- MOVV R20, x+0(FP) +- MOVV R21, y+8(FP) +-#endif + JMP runtime·goPanicSlice3CU(SB) + TEXT runtime·panicSliceConvert(SB),NOSPLIT,$0-16 +-#ifdef GOEXPERIMENT_regabiargs + MOVV R23, R4 + MOVV R24, R5 +-#else +- MOVV R23, x+0(FP) +- MOVV R24, y+8(FP) +-#endif + JMP runtime·goPanicSliceConvert(SB) +diff --git a/src/runtime/internal/syscall/asm_linux_loong64.s b/src/runtime/internal/syscall/asm_linux_loong64.s +index 11c5bc2468..ff8ad75b05 100644 +--- a/src/runtime/internal/syscall/asm_linux_loong64.s ++++ b/src/runtime/internal/syscall/asm_linux_loong64.s +@@ -22,7 +22,6 @@ + // r2 | R5 | R5 + // err | R6 | part of R4 + TEXT ·Syscall6(SB),NOSPLIT,$0-80 +-#ifdef GOEXPERIMENT_regabiargs + MOVV R4, R11 // syscall entry + MOVV R5, R4 + MOVV R6, R5 +@@ -30,39 +29,14 @@ TEXT ·Syscall6(SB),NOSPLIT,$0-80 + MOVV R8, R7 + MOVV R9, R8 + MOVV R10, R9 +-#else +- MOVV num+0(FP), R11 // syscall entry +- MOVV a1+8(FP), R4 +- MOVV a2+16(FP), R5 +- MOVV a3+24(FP), R6 +- MOVV a4+32(FP), R7 +- MOVV a5+40(FP), R8 +- MOVV a6+48(FP), R9 +-#endif + SYSCALL +-#ifdef GOEXPERIMENT_regabiargs + MOVV R0, R5 // r2 is not used. Always set to 0. + MOVW $-4096, R12 + BGEU R12, R4, ok + SUBVU R4, R0, R6 // errno + MOVV $-1, R4 // r1 +-#else +- MOVW $-4096, R12 +- BGEU R12, R4, ok +- MOVV $-1, R12 +- MOVV R12, r1+56(FP) +- MOVV R0, r2+64(FP) +- SUBVU R4, R0, R4 +- MOVV R4, errno+72(FP) +-#endif + RET + ok: +-#ifdef GOEXPERIMENT_regabiargs + // r1 already in R4 + MOVV R0, R6 // errno +-#else +- MOVV R4, r1+56(FP) +- MOVV R0, r2+64(FP) // r2 is not used. Always set to 0. +- MOVV R0, errno+72(FP) +-#endif + RET +diff --git a/src/runtime/memclr_loong64.s b/src/runtime/memclr_loong64.s +index 313e4d4f33..1d45e82d49 100644 +--- a/src/runtime/memclr_loong64.s ++++ b/src/runtime/memclr_loong64.s +@@ -7,10 +7,6 @@ + + // func memclrNoHeapPointers(ptr unsafe.Pointer, n uintptr) + TEXT runtime·memclrNoHeapPointers(SB),NOSPLIT,$0-16 +-#ifndef GOEXPERIMENT_regabiargs +- MOVV ptr+0(FP), R4 +- MOVV n+8(FP), R5 +-#endif + ADDV R4, R5, R6 + + // if less than 8 bytes, do one byte at a time +diff --git a/src/runtime/memmove_loong64.s b/src/runtime/memmove_loong64.s +index 5b7aeba698..a94cf999bc 100644 +--- a/src/runtime/memmove_loong64.s ++++ b/src/runtime/memmove_loong64.s +@@ -8,11 +8,6 @@ + + // func memmove(to, from unsafe.Pointer, n uintptr) + TEXT runtime·memmove(SB), NOSPLIT|NOFRAME, $0-24 +-#ifndef GOEXPERIMENT_regabiargs +- MOVV to+0(FP), R4 +- MOVV from+8(FP), R5 +- MOVV n+16(FP), R6 +-#endif + BNE R6, check + RET + +-- +2.38.1 + diff --git a/0088-cmd-internal-obj-loong64-using-LookupABI-to-find-duf.patch b/0088-cmd-internal-obj-loong64-using-LookupABI-to-find-duf.patch new file mode 100644 index 0000000..c37e68f --- /dev/null +++ b/0088-cmd-internal-obj-loong64-using-LookupABI-to-find-duf.patch @@ -0,0 +1,33 @@ +From 06572760d04e774572a0bee9713df70aa29b08bd Mon Sep 17 00:00:00 2001 +From: chenguoqi +Date: Mon, 9 Oct 2023 16:07:01 +0800 +Subject: [PATCH 26/30] cmd/internal/obj/loong64: using LookupABI to find + duff{copy,zero} when rewriting GOT + +Because register-passing parameters have been enabled, using Lookup +to find duffcopy and duffzero fails and returns incorrect values. + +Change-Id: Ic041bf0f830fa01f245e248c7fa85a1facb38b9e +--- + src/cmd/internal/obj/loong64/obj.go | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/src/cmd/internal/obj/loong64/obj.go b/src/cmd/internal/obj/loong64/obj.go +index 3e133c0c5a..513917d58a 100644 +--- a/src/cmd/internal/obj/loong64/obj.go ++++ b/src/cmd/internal/obj/loong64/obj.go +@@ -99,9 +99,9 @@ func rewriteToUseGot(ctxt *obj.Link, p *obj.Prog, newprog obj.ProgAlloc) { + if p.As == obj.ADUFFCOPY || p.As == obj.ADUFFZERO { + var sym *obj.LSym + if p.As == obj.ADUFFZERO { +- sym = ctxt.Lookup("runtime.duffzero") ++ sym = ctxt.LookupABI("runtime.duffzero", obj.ABIInternal) + } else { +- sym = ctxt.Lookup("runtime.duffcopy") ++ sym = ctxt.LookupABI("runtime.duffcopy", obj.ABIInternal) + } + offset := p.To.Offset + p.As = AMOVV +-- +2.38.1 + diff --git a/0089-cmd-internal-cmd-link-unify-the-relocation-naming-st.patch b/0089-cmd-internal-cmd-link-unify-the-relocation-naming-st.patch new file mode 100644 index 0000000..fcfdef4 --- /dev/null +++ b/0089-cmd-internal-cmd-link-unify-the-relocation-naming-st.patch @@ -0,0 +1,409 @@ +From 32139d3ee893387fa694d26d3c9e67342d1aa816 Mon Sep 17 00:00:00 2001 +From: limeidan +Date: Wed, 11 Oct 2023 18:01:59 +0800 +Subject: [PATCH 27/30] cmd/internal, cmd/link: unify the relocation naming + style of loong64 + +Change-Id: Ica24a7c351b26a4375bbc52b719c69b78e89c5df +--- + src/cmd/internal/obj/loong64/asm.go | 30 +++++----- + src/cmd/internal/objabi/reloctype.go | 30 +++++----- + src/cmd/internal/objabi/reloctype_string.go | 16 +++--- + src/cmd/link/internal/loong64/asm.go | 62 ++++++++++----------- + 4 files changed, 68 insertions(+), 70 deletions(-) + +diff --git a/src/cmd/internal/obj/loong64/asm.go b/src/cmd/internal/obj/loong64/asm.go +index 34b0ff94e4..fe091b72ae 100644 +--- a/src/cmd/internal/obj/loong64/asm.go ++++ b/src/cmd/internal/obj/loong64/asm.go +@@ -1670,7 +1670,7 @@ func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) { + rel.Siz = 4 + rel.Sym = p.To.Sym + rel.Add = p.To.Offset +- rel.Type = objabi.R_ADDRLOONG64U ++ rel.Type = objabi.R_LOONG64_ADDR_HI + + o2 = OP_12IRR(c.opirr(p.As), uint32(0), uint32(REGTMP), uint32(p.From.Reg)) + rel2 := obj.Addrel(c.cursym) +@@ -1678,7 +1678,7 @@ func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) { + rel2.Siz = 4 + rel2.Sym = p.To.Sym + rel2.Add = p.To.Offset +- rel2.Type = objabi.R_ADDRLOONG64 ++ rel2.Type = objabi.R_LOONG64_ADDR_LO + + case 51: // mov addr,r ==> pcalau12i + lw + o1 = OP_IR(c.opir(APCALAU12I), uint32(0), uint32(REGTMP)) +@@ -1687,14 +1687,14 @@ func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) { + rel.Siz = 4 + rel.Sym = p.From.Sym + rel.Add = p.From.Offset +- rel.Type = objabi.R_ADDRLOONG64U ++ rel.Type = objabi.R_LOONG64_ADDR_HI + o2 = OP_12IRR(c.opirr(-p.As), uint32(0), uint32(REGTMP), uint32(p.To.Reg)) + rel2 := obj.Addrel(c.cursym) + rel2.Off = int32(c.pc + 4) + rel2.Siz = 4 + rel2.Sym = p.From.Sym + rel2.Add = p.From.Offset +- rel2.Type = objabi.R_ADDRLOONG64 ++ rel2.Type = objabi.R_LOONG64_ADDR_LO + + case 52: // mov $lext, r + // NOTE: this case does not use REGTMP. If it ever does, +@@ -1705,14 +1705,14 @@ func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) { + rel.Siz = 4 + rel.Sym = p.From.Sym + rel.Add = p.From.Offset +- rel.Type = objabi.R_ADDRLOONG64U ++ rel.Type = objabi.R_LOONG64_ADDR_HI + o2 = OP_12IRR(c.opirr(add), uint32(0), uint32(p.To.Reg), uint32(p.To.Reg)) + rel2 := obj.Addrel(c.cursym) + rel2.Off = int32(c.pc + 4) + rel2.Siz = 4 + rel2.Sym = p.From.Sym + rel2.Add = p.From.Offset +- rel2.Type = objabi.R_ADDRLOONG64 ++ rel2.Type = objabi.R_LOONG64_ADDR_LO + + case 53: // mov r, tlsvar ==> lu12i.w + ori + add r2, regtmp + sw o(regtmp) + // NOTE: this case does not use REGTMP. If it ever does, +@@ -1723,14 +1723,14 @@ func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) { + rel.Siz = 4 + rel.Sym = p.To.Sym + rel.Add = p.To.Offset +- rel.Type = objabi.R_ADDRLOONG64TLSU ++ rel.Type = objabi.R_LOONG64_TLS_LE_HI + o2 = OP_12IRR(c.opirr(AOR), uint32(0), uint32(REGTMP), uint32(REGTMP)) + rel2 := obj.Addrel(c.cursym) + rel2.Off = int32(c.pc + 4) + rel2.Siz = 4 + rel2.Sym = p.To.Sym + rel2.Add = p.To.Offset +- rel2.Type = objabi.R_ADDRLOONG64TLS ++ rel2.Type = objabi.R_LOONG64_TLS_LE_LO + o3 = OP_RRR(c.oprrr(AADDV), uint32(REG_R2), uint32(REGTMP), uint32(REGTMP)) + o4 = OP_12IRR(c.opirr(p.As), uint32(0), uint32(REGTMP), uint32(p.From.Reg)) + +@@ -1743,14 +1743,14 @@ func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) { + rel.Siz = 4 + rel.Sym = p.From.Sym + rel.Add = p.From.Offset +- rel.Type = objabi.R_ADDRLOONG64TLSU ++ rel.Type = objabi.R_LOONG64_TLS_LE_HI + o2 = OP_12IRR(c.opirr(AOR), uint32(0), uint32(REGTMP), uint32(REGTMP)) + rel2 := obj.Addrel(c.cursym) + rel2.Off = int32(c.pc + 4) + rel2.Siz = 4 + rel2.Sym = p.From.Sym + rel2.Add = p.From.Offset +- rel2.Type = objabi.R_ADDRLOONG64TLS ++ rel2.Type = objabi.R_LOONG64_TLS_LE_LO + o3 = OP_RRR(c.oprrr(AADDV), uint32(REG_R2), uint32(REGTMP), uint32(REGTMP)) + o4 = OP_12IRR(c.opirr(-p.As), uint32(0), uint32(REGTMP), uint32(p.To.Reg)) + +@@ -1763,14 +1763,14 @@ func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) { + rel.Siz = 4 + rel.Sym = p.From.Sym + rel.Add = p.From.Offset +- rel.Type = objabi.R_ADDRLOONG64TLSU ++ rel.Type = objabi.R_LOONG64_TLS_LE_HI + o2 = OP_12IRR(c.opirr(AOR), uint32(0), uint32(REGTMP), uint32(REGTMP)) + rel2 := obj.Addrel(c.cursym) + rel2.Off = int32(c.pc + 4) + rel2.Siz = 4 + rel2.Sym = p.From.Sym + rel2.Add = p.From.Offset +- rel2.Type = objabi.R_ADDRLOONG64TLS ++ rel2.Type = objabi.R_LOONG64_TLS_LE_LO + o3 = OP_RRR(c.oprrr(AADDV), uint32(REG_R2), uint32(REGTMP), uint32(p.To.Reg)) + + case 56: // mov r, tlsvar IE model ==> (pcalau12i + ld.d)tlsvar@got + add.d + st.d +@@ -1780,7 +1780,7 @@ func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) { + rel.Siz = 4 + rel.Sym = p.To.Sym + rel.Add = 0x0 +- rel.Type = objabi.R_LOONG64_TLS_IE_PCREL_HI ++ rel.Type = objabi.R_LOONG64_TLS_IE_HI + o2 = OP_12IRR(c.opirr(-p.As), uint32(0), uint32(REGTMP), uint32(REGTMP)) + rel2 := obj.Addrel(c.cursym) + rel2.Off = int32(c.pc + 4) +@@ -1798,7 +1798,7 @@ func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) { + rel.Siz = 4 + rel.Sym = p.From.Sym + rel.Add = 0x0 +- rel.Type = objabi.R_LOONG64_TLS_IE_PCREL_HI ++ rel.Type = objabi.R_LOONG64_TLS_IE_HI + o2 = OP_12IRR(c.opirr(-p.As), uint32(0), uint32(REGTMP), uint32(REGTMP)) + rel2 := obj.Addrel(c.cursym) + rel2.Off = int32(c.pc + 4) +@@ -1849,7 +1849,7 @@ func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) { + rel.Off = int32(c.pc) + rel.Siz = 4 + rel.Sym = p.From.Sym +- rel.Type = objabi.R_LOONG64_GOTPCREL_HI ++ rel.Type = objabi.R_LOONG64_GOT_HI + rel.Add = 0x0 + o2 = OP_12IRR(c.opirr(-p.As), uint32(0), uint32(p.To.Reg), uint32(p.To.Reg)) + rel2 := obj.Addrel(c.cursym) +diff --git a/src/cmd/internal/objabi/reloctype.go b/src/cmd/internal/objabi/reloctype.go +index aaefd15663..e481d6c803 100644 +--- a/src/cmd/internal/objabi/reloctype.go ++++ b/src/cmd/internal/objabi/reloctype.go +@@ -290,34 +290,32 @@ const ( + + // Loong64. + +- // R_ADDRLOONG64 resolves to the low 12 bits of an external address, by encoding +- // it into the instruction. +- R_ADDRLOONG64 +- +- // R_ADDRLOONG64U resolves to the sign-adjusted "upper" 20 bits (bit 5-24) of an ++ // R_LOONG64_ADDR_HI resolves to the sign-adjusted "upper" 20 bits (bit 5-24) of an + // external address, by encoding it into the instruction. +- R_ADDRLOONG64U ++ // R_LOONG64_ADDR_LO resolves to the low 12 bits of an external address, by encoding ++ // it into the instruction. ++ R_LOONG64_ADDR_HI ++ R_LOONG64_ADDR_LO + +- // R_ADDRLOONG64TLS resolves to the low 12 bits of a TLS address (offset from ++ // R_LOONG64_TLS_LE_HI resolves to the high 20 bits of a TLS address (offset from + // thread pointer), by encoding it into the instruction. +- R_ADDRLOONG64TLS +- +- // R_ADDRLOONG64TLSU resolves to the high 20 bits of a TLS address (offset from ++ // R_LOONG64_TLS_LE_LO resolves to the low 12 bits of a TLS address (offset from + // thread pointer), by encoding it into the instruction. +- R_ADDRLOONG64TLSU ++ R_LOONG64_TLS_LE_HI ++ R_LOONG64_TLS_LE_LO + + // R_CALLLOONG64 resolves to non-PC-relative target address of a CALL (BL/JIRL) + // instruction, by encoding the address into the instruction. + R_CALLLOONG64 + +- // R_LOONG64_TLS_IE_PCREL_HI and R_LOONG64_TLS_IE_LO relocates an pcalau12i, ld.d pair to compute +- // the address of the GOT slot of the tls symbol. +- R_LOONG64_TLS_IE_PCREL_HI ++ // R_LOONG64_TLS_IE_HI and R_LOONG64_TLS_IE_LO relocates a pcalau12i, ld.d ++ // pair to compute the address of the GOT slot of the tls symbol. ++ R_LOONG64_TLS_IE_HI + R_LOONG64_TLS_IE_LO + +- // R_LOONG64_GOTPCREL_HI and R_LOONG64_GOT_LO relocates an pcalau12i, ld.d pair to compute ++ // R_LOONG64_GOT_HI and R_LOONG64_GOT_LO relocates an pcalau12i, ld.d pair to compute + // the address of the GOT slot of the referenced symbol. +- R_LOONG64_GOTPCREL_HI ++ R_LOONG64_GOT_HI + R_LOONG64_GOT_LO + + // R_JMPLOONG64 resolves to non-PC-relative target address of a JMP instruction, +diff --git a/src/cmd/internal/objabi/reloctype_string.go b/src/cmd/internal/objabi/reloctype_string.go +index 53104c76b3..132cc12d8b 100644 +--- a/src/cmd/internal/objabi/reloctype_string.go ++++ b/src/cmd/internal/objabi/reloctype_string.go +@@ -74,14 +74,14 @@ func _() { + _ = x[R_RISCV_TLS_IE_ITYPE-64] + _ = x[R_RISCV_TLS_IE_STYPE-65] + _ = x[R_PCRELDBL-66] +- _ = x[R_ADDRLOONG64-67] +- _ = x[R_ADDRLOONG64U-68] +- _ = x[R_ADDRLOONG64TLS-69] +- _ = x[R_ADDRLOONG64TLSU-70] ++ _ = x[R_LOONG64_ADDR_HI-67] ++ _ = x[R_LOONG64_ADDR_LO-68] ++ _ = x[R_LOONG64_TLS_LE_HI-69] ++ _ = x[R_LOONG64_TLS_LE_LO-70] + _ = x[R_CALLLOONG64-71] +- _ = x[R_LOONG64_TLS_IE_PCREL_HI-72] ++ _ = x[R_LOONG64_TLS_IE_HI-72] + _ = x[R_LOONG64_TLS_IE_LO-73] +- _ = x[R_LOONG64_GOTPCREL_HI-74] ++ _ = x[R_LOONG64_GOT_HI-74] + _ = x[R_LOONG64_GOT_LO-75] + _ = x[R_JMPLOONG64-76] + _ = x[R_ADDRMIPSU-77] +@@ -91,9 +91,9 @@ func _() { + _ = x[R_XCOFFREF-81] + } + +-const _RelocType_name = "R_ADDRR_ADDRPOWERR_ADDRARM64R_ADDRMIPSR_ADDROFFR_SIZER_CALLR_CALLARMR_CALLARM64R_CALLINDR_CALLPOWERR_CALLMIPSR_CONSTR_PCRELR_TLS_LER_TLS_IER_GOTOFFR_PLT0R_PLT1R_PLT2R_USEFIELDR_USETYPER_USEIFACER_USEIFACEMETHODR_USEGENERICIFACEMETHODR_METHODOFFR_KEEPR_POWER_TOCR_GOTPCRELR_JMPMIPSR_DWARFSECREFR_DWARFFILEREFR_ARM64_TLS_LER_ARM64_TLS_IER_ARM64_GOTPCRELR_ARM64_GOTR_ARM64_PCRELR_ARM64_PCREL_LDST8R_ARM64_PCREL_LDST16R_ARM64_PCREL_LDST32R_ARM64_PCREL_LDST64R_ARM64_LDST8R_ARM64_LDST16R_ARM64_LDST32R_ARM64_LDST64R_ARM64_LDST128R_POWER_TLS_LER_POWER_TLS_IER_POWER_TLSR_POWER_TLS_IE_PCREL34R_POWER_TLS_LE_TPREL34R_ADDRPOWER_DSR_ADDRPOWER_GOTR_ADDRPOWER_GOT_PCREL34R_ADDRPOWER_PCRELR_ADDRPOWER_TOCRELR_ADDRPOWER_TOCREL_DSR_ADDRPOWER_D34R_ADDRPOWER_PCREL34R_RISCV_CALLR_RISCV_CALL_TRAMPR_RISCV_PCREL_ITYPER_RISCV_PCREL_STYPER_RISCV_TLS_IE_ITYPER_RISCV_TLS_IE_STYPER_PCRELDBLR_ADDRLOONG64R_ADDRLOONG64UR_ADDRLOONG64TLSR_ADDRLOONG64TLSUR_CALLLOONG64R_LOONG64_TLS_IE_PCREL_HIR_LOONG64_TLS_IE_LOR_LOONG64_GOTPCREL_HIR_LOONG64_GOT_LOR_JMPLOONG64R_ADDRMIPSUR_ADDRMIPSTLSR_ADDRCUOFFR_WASMIMPORTR_XCOFFREF" ++const _RelocType_name = "R_ADDRR_ADDRPOWERR_ADDRARM64R_ADDRMIPSR_ADDROFFR_SIZER_CALLR_CALLARMR_CALLARM64R_CALLINDR_CALLPOWERR_CALLMIPSR_CONSTR_PCRELR_TLS_LER_TLS_IER_GOTOFFR_PLT0R_PLT1R_PLT2R_USEFIELDR_USETYPER_USEIFACER_USEIFACEMETHODR_USEGENERICIFACEMETHODR_METHODOFFR_KEEPR_POWER_TOCR_GOTPCRELR_JMPMIPSR_DWARFSECREFR_DWARFFILEREFR_ARM64_TLS_LER_ARM64_TLS_IER_ARM64_GOTPCRELR_ARM64_GOTR_ARM64_PCRELR_ARM64_PCREL_LDST8R_ARM64_PCREL_LDST16R_ARM64_PCREL_LDST32R_ARM64_PCREL_LDST64R_ARM64_LDST8R_ARM64_LDST16R_ARM64_LDST32R_ARM64_LDST64R_ARM64_LDST128R_POWER_TLS_LER_POWER_TLS_IER_POWER_TLSR_POWER_TLS_IE_PCREL34R_POWER_TLS_LE_TPREL34R_ADDRPOWER_DSR_ADDRPOWER_GOTR_ADDRPOWER_GOT_PCREL34R_ADDRPOWER_PCRELR_ADDRPOWER_TOCRELR_ADDRPOWER_TOCREL_DSR_ADDRPOWER_D34R_ADDRPOWER_PCREL34R_RISCV_CALLR_RISCV_CALL_TRAMPR_RISCV_PCREL_ITYPER_RISCV_PCREL_STYPER_RISCV_TLS_IE_ITYPER_RISCV_TLS_IE_STYPER_PCRELDBLR_LOONG64_ADDR_HIR_LOONG64_ADDR_LOR_LOONG64_TLS_LE_HIR_LOONG64_TLS_LE_LOR_CALLLOONG64R_LOONG64_TLS_IE_HIR_LOONG64_TLS_IE_LOR_LOONG64_GOT_HIR_LOONG64_GOT_LOR_JMPLOONG64R_ADDRMIPSUR_ADDRMIPSTLSR_ADDRCUOFFR_WASMIMPORTR_XCOFFREF" + +-var _RelocType_index = [...]uint16{0, 6, 17, 28, 38, 47, 53, 59, 68, 79, 88, 99, 109, 116, 123, 131, 139, 147, 153, 159, 165, 175, 184, 194, 210, 233, 244, 250, 261, 271, 280, 293, 307, 321, 335, 351, 362, 375, 394, 414, 434, 454, 467, 481, 495, 509, 524, 538, 552, 563, 585, 607, 621, 636, 659, 676, 694, 715, 730, 749, 761, 779, 798, 817, 837, 857, 867, 880, 894, 910, 927, 940, 965, 984, 1005, 1021, 1033, 1044, 1057, 1068, 1080, 1090} ++var _RelocType_index = [...]uint16{0, 6, 17, 28, 38, 47, 53, 59, 68, 79, 88, 99, 109, 116, 123, 131, 139, 147, 153, 159, 165, 175, 184, 194, 210, 233, 244, 250, 261, 271, 280, 293, 307, 321, 335, 351, 362, 375, 394, 414, 434, 454, 467, 481, 495, 509, 524, 538, 552, 563, 585, 607, 621, 636, 659, 676, 694, 715, 730, 749, 761, 779, 798, 817, 837, 857, 867, 884, 901, 920, 939, 952, 971, 990, 1006, 1022, 1034, 1045, 1058, 1069, 1081, 1091} + + func (i RelocType) String() string { + i -= 1 +diff --git a/src/cmd/link/internal/loong64/asm.go b/src/cmd/link/internal/loong64/asm.go +index a4c48e64cd..7f7872a28c 100644 +--- a/src/cmd/link/internal/loong64/asm.go ++++ b/src/cmd/link/internal/loong64/asm.go +@@ -26,18 +26,18 @@ func gentext(ctxt *ld.Link, ldr *loader.Loader) { + + // 0: pcalau12i r4, $0 + // +- // 0: R_ADDRLOONG64U ++ // 0: R_LOONG64_ADDR_HI + // + // 4: addi.d r4, r4, $0 + // +- // 4: R_ADDRLOONG64 ++ // 4: R_LOONG64_ADDR_LO + o(0x1a000004) +- rel, _ := initfunc.AddRel(objabi.R_ADDRLOONG64U) ++ rel, _ := initfunc.AddRel(objabi.R_LOONG64_ADDR_HI) + rel.SetOff(0) + rel.SetSiz(4) + rel.SetSym(ctxt.Moduledata) + o(0x02c00084) +- rel2, _ := initfunc.AddRel(objabi.R_ADDRLOONG64) ++ rel2, _ := initfunc.AddRel(objabi.R_LOONG64_ADDR_LO) + rel2.SetOff(4) + rel2.SetSiz(4) + rel2.SetSym(ctxt.Moduledata) +@@ -80,12 +80,12 @@ func elfreloc1(ctxt *ld.Link, out *ld.OutBuf, ldr *loader.Loader, s loader.Sym, + default: + return false + } +- case objabi.R_ADDRLOONG64TLS: ++ case objabi.R_LOONG64_TLS_LE_LO: + out.Write64(uint64(sectoff)) + out.Write64(uint64(elf.R_LARCH_TLS_LE_LO12) | uint64(elfsym)<<32) + out.Write64(uint64(r.Xadd)) + +- case objabi.R_ADDRLOONG64TLSU: ++ case objabi.R_LOONG64_TLS_LE_HI: + out.Write64(uint64(sectoff)) + out.Write64(uint64(elf.R_LARCH_TLS_LE_HI20) | uint64(elfsym)<<32) + out.Write64(uint64(r.Xadd)) +@@ -95,7 +95,7 @@ func elfreloc1(ctxt *ld.Link, out *ld.OutBuf, ldr *loader.Loader, s loader.Sym, + out.Write64(uint64(elf.R_LARCH_B26) | uint64(elfsym)<<32) + out.Write64(uint64(r.Xadd)) + +- case objabi.R_LOONG64_TLS_IE_PCREL_HI: ++ case objabi.R_LOONG64_TLS_IE_HI: + out.Write64(uint64(sectoff)) + out.Write64(uint64(elf.R_LARCH_TLS_IE_PC_HI20) | uint64(elfsym)<<32) + out.Write64(uint64(0x0)) +@@ -105,7 +105,7 @@ func elfreloc1(ctxt *ld.Link, out *ld.OutBuf, ldr *loader.Loader, s loader.Sym, + out.Write64(uint64(elf.R_LARCH_TLS_IE_PC_LO12) | uint64(elfsym)<<32) + out.Write64(uint64(0x0)) + +- case objabi.R_LOONG64_GOTPCREL_HI: ++ case objabi.R_LOONG64_GOT_HI: + out.Write64(uint64(sectoff)) + out.Write64(uint64(elf.R_LARCH_GOT_PC_HI20) | uint64(elfsym)<<32) + out.Write64(uint64(0x0)) +@@ -120,12 +120,12 @@ func elfreloc1(ctxt *ld.Link, out *ld.OutBuf, ldr *loader.Loader, s loader.Sym, + // signed 12-bit immediate operand. The 0x800 (addr+U12 <=> addr+0x800+S12) is introduced + // to do sign extending from 12 bits. The 0x804 is 0x800 + 4, 4 is instruction bit + // width on Loong64 and is used to correct the PC of the addi.d instruction. +- case objabi.R_ADDRLOONG64: ++ case objabi.R_LOONG64_ADDR_LO: + out.Write64(uint64(sectoff)) + out.Write64(uint64(elf.R_LARCH_PCALA_LO12) | uint64(elfsym)<<32) + out.Write64(uint64(r.Xadd)) + +- case objabi.R_ADDRLOONG64U: ++ case objabi.R_LOONG64_ADDR_HI: + out.Write64(uint64(sectoff)) + out.Write64(uint64(elf.R_LARCH_PCALA_HI20) | uint64(elfsym)<<32) + out.Write64(uint64(r.Xadd)) +@@ -148,8 +148,8 @@ func archreloc(target *ld.Target, ldr *loader.Loader, syms *ld.ArchSyms, r loade + switch r.Type() { + default: + return val, 0, false +- case objabi.R_ADDRLOONG64, +- objabi.R_ADDRLOONG64U: ++ case objabi.R_LOONG64_ADDR_HI, ++ objabi.R_LOONG64_ADDR_LO: + // set up addend for eventual relocation via outer symbol. + rs, _ := ld.FoldSubSymbolOffset(ldr, rs) + rst := ldr.SymType(rs) +@@ -157,14 +157,14 @@ func archreloc(target *ld.Target, ldr *loader.Loader, syms *ld.ArchSyms, r loade + ldr.Errorf(s, "missing section for %s", ldr.SymName(rs)) + } + return val, 1, true +- case objabi.R_ADDRLOONG64TLS, +- objabi.R_ADDRLOONG64TLSU, ++ case objabi.R_LOONG64_TLS_LE_HI, ++ objabi.R_LOONG64_TLS_LE_LO, + objabi.R_CALLLOONG64, + objabi.R_JMPLOONG64, +- objabi.R_LOONG64_TLS_IE_PCREL_HI, +- objabi.R_LOONG64_GOTPCREL_HI, +- objabi.R_LOONG64_TLS_IE_LO, +- objabi.R_LOONG64_GOT_LO: ++ objabi.R_LOONG64_GOT_HI, ++ objabi.R_LOONG64_GOT_LO, ++ objabi.R_LOONG64_TLS_IE_HI, ++ objabi.R_LOONG64_TLS_IE_LO: + return val, 1, true + } + } +@@ -177,18 +177,18 @@ func archreloc(target *ld.Target, ldr *loader.Loader, syms *ld.ArchSyms, r loade + return r.Add(), noExtReloc, isOk + case objabi.R_GOTOFF: + return ldr.SymValue(r.Sym()) + r.Add() - ldr.SymValue(syms.GOT), noExtReloc, isOk +- case objabi.R_ADDRLOONG64, +- objabi.R_ADDRLOONG64U: ++ case objabi.R_LOONG64_ADDR_HI, ++ objabi.R_LOONG64_ADDR_LO: + pc := ldr.SymValue(s) + int64(r.Off()) + t := calculatePCAlignedReloc(r.Type(), ldr.SymAddr(rs)+r.Add(), pc) +- if r.Type() == objabi.R_ADDRLOONG64 { ++ if r.Type() == objabi.R_LOONG64_ADDR_LO { + return int64(val&0xffc003ff | (t << 10)), noExtReloc, isOk + } + return int64(val&0xfe00001f | (t << 5)), noExtReloc, isOk +- case objabi.R_ADDRLOONG64TLS, +- objabi.R_ADDRLOONG64TLSU: ++ case objabi.R_LOONG64_TLS_LE_HI, ++ objabi.R_LOONG64_TLS_LE_LO: + t := ldr.SymAddr(rs) + r.Add() +- if r.Type() == objabi.R_ADDRLOONG64TLS { ++ if r.Type() == objabi.R_LOONG64_TLS_LE_LO { + return int64(val&0xffc003ff | ((t & 0xfff) << 10)), noExtReloc, isOk + } + return int64(val&0xfe00001f | (((t) >> 12 << 5) & 0x1ffffe0)), noExtReloc, isOk +@@ -208,20 +208,20 @@ func archrelocvariant(*ld.Target, *loader.Loader, loader.Reloc, sym.RelocVariant + + func extreloc(target *ld.Target, ldr *loader.Loader, r loader.Reloc, s loader.Sym) (loader.ExtReloc, bool) { + switch r.Type() { +- case objabi.R_ADDRLOONG64, +- objabi.R_ADDRLOONG64U, +- objabi.R_LOONG64_GOTPCREL_HI, ++ case objabi.R_LOONG64_ADDR_HI, ++ objabi.R_LOONG64_ADDR_LO, ++ objabi.R_LOONG64_GOT_HI, + objabi.R_LOONG64_GOT_LO: + + return ld.ExtrelocViaOuterSym(ldr, r, s), true + +- case objabi.R_ADDRLOONG64TLS, +- objabi.R_ADDRLOONG64TLSU, ++ case objabi.R_LOONG64_TLS_LE_HI, ++ objabi.R_LOONG64_TLS_LE_LO, + objabi.R_CONST, + objabi.R_GOTOFF, + objabi.R_CALLLOONG64, + objabi.R_JMPLOONG64, +- objabi.R_LOONG64_TLS_IE_PCREL_HI, ++ objabi.R_LOONG64_TLS_IE_HI, + objabi.R_LOONG64_TLS_IE_LO: + return ld.ExtrelocSimple(ldr, r), true + } +@@ -230,7 +230,7 @@ func extreloc(target *ld.Target, ldr *loader.Loader, r loader.Reloc, s loader.Sy + + func isRequestingLowPageBits(t objabi.RelocType) bool { + switch t { +- case objabi.R_ADDRLOONG64: ++ case objabi.R_LOONG64_ADDR_LO: + return true + } + return false +-- +2.38.1 + diff --git a/0090-cmd-link-internal-loadelf-remove-useless-relocation-.patch b/0090-cmd-link-internal-loadelf-remove-useless-relocation-.patch new file mode 100644 index 0000000..9dcc0ce --- /dev/null +++ b/0090-cmd-link-internal-loadelf-remove-useless-relocation-.patch @@ -0,0 +1,31 @@ +From 753953758b77b325ddf3edba216c49de35663141 Mon Sep 17 00:00:00 2001 +From: limeidan +Date: Tue, 24 Oct 2023 19:48:36 +0800 +Subject: [PATCH 28/30] cmd/link/internal/loadelf: remove useless relocation + size information of loong64 + +Change-Id: I7e9d04b1961e11583e97e759a6f6fa636bedc6a2 +--- + src/cmd/link/internal/loadelf/ldelf.go | 6 +----- + 1 file changed, 1 insertion(+), 5 deletions(-) + +diff --git a/src/cmd/link/internal/loadelf/ldelf.go b/src/cmd/link/internal/loadelf/ldelf.go +index 156d9a5616..2e88b43c24 100644 +--- a/src/cmd/link/internal/loadelf/ldelf.go ++++ b/src/cmd/link/internal/loadelf/ldelf.go +@@ -1002,11 +1002,7 @@ func relSize(arch *sys.Arch, pn string, elftype uint32) (uint8, uint8, error) { + MIPS64 | uint32(elf.R_MIPS_GOT_DISP)<<16: + return 4, 4, nil + +- case LOONG64 | uint32(elf.R_LARCH_SOP_PUSH_PCREL)<<16, +- LOONG64 | uint32(elf.R_LARCH_SOP_PUSH_GPREL)<<16, +- LOONG64 | uint32(elf.R_LARCH_SOP_PUSH_ABSOLUTE)<<16, +- LOONG64 | uint32(elf.R_LARCH_MARK_LA)<<16, +- LOONG64 | uint32(elf.R_LARCH_SOP_POP_32_S_0_10_10_16_S2)<<16, ++ case LOONG64 | uint32(elf.R_LARCH_MARK_LA)<<16, + LOONG64 | uint32(elf.R_LARCH_MARK_PCREL)<<16, + LOONG64 | uint32(elf.R_LARCH_32_PCREL)<<16: + return 4, 4, nil +-- +2.38.1 + diff --git a/0091-cmd-link-internal-loadelf-add-additional-relocations.patch b/0091-cmd-link-internal-loadelf-add-additional-relocations.patch new file mode 100644 index 0000000..f7cd8c3 --- /dev/null +++ b/0091-cmd-link-internal-loadelf-add-additional-relocations.patch @@ -0,0 +1,39 @@ +From 1c8bc36ba2dbfa37a8584d0b6e10e07d081183a0 Mon Sep 17 00:00:00 2001 +From: Guoqi Chen +Date: Wed, 25 Oct 2023 17:54:51 +0800 +Subject: [PATCH 29/30] cmd/link/internal/loadelf: add additional relocations + for loong64 + +The Linker Relaxation feature on Loong64 is already supported in binutils 2.41. +The intermediate code generated after enabling this feature introduces three +reloc types. + +elf.R_LARCH_B26 +elf.R_LARCH_ADD32 +elf.R_LARCH_SUB32 + +Fixes #63725 + +Signed-off-by: Guoqi Chen +Change-Id: I7643a9aa4891356340ea26b1256b5f8e62c8938d +--- + src/cmd/link/internal/loadelf/ldelf.go | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/src/cmd/link/internal/loadelf/ldelf.go b/src/cmd/link/internal/loadelf/ldelf.go +index 2e88b43c24..e32db7ddcc 100644 +--- a/src/cmd/link/internal/loadelf/ldelf.go ++++ b/src/cmd/link/internal/loadelf/ldelf.go +@@ -1004,6 +1004,9 @@ func relSize(arch *sys.Arch, pn string, elftype uint32) (uint8, uint8, error) { + + case LOONG64 | uint32(elf.R_LARCH_MARK_LA)<<16, + LOONG64 | uint32(elf.R_LARCH_MARK_PCREL)<<16, ++ LOONG64 | uint32(elf.R_LARCH_ADD32)<<16, ++ LOONG64 | uint32(elf.R_LARCH_SUB32)<<16, ++ LOONG64 | uint32(elf.R_LARCH_B26)<<16, + LOONG64 | uint32(elf.R_LARCH_32_PCREL)<<16: + return 4, 4, nil + +-- +2.38.1 + diff --git a/0092-cmd-link-add-new-relocations-numbered-101-to-109-for.patch b/0092-cmd-link-add-new-relocations-numbered-101-to-109-for.patch new file mode 100644 index 0000000..364c077 --- /dev/null +++ b/0092-cmd-link-add-new-relocations-numbered-101-to-109-for.patch @@ -0,0 +1,86 @@ +From 0e57010dbc158c196cf8ba1f98a0519280094ee0 Mon Sep 17 00:00:00 2001 +From: Guoqi Chen +Date: Thu, 26 Oct 2023 15:12:29 +0800 +Subject: [PATCH 30/30] cmd/link: add new relocations numbered 101 to 109 for + loong64 + +Signed-off-by: Guoqi Chen +Change-Id: Ib9b9ad922a4b561ca7261bd90107d746fd9f298f +--- + src/cmd/link/internal/loadelf/ldelf.go | 15 ++++++++++++++- + src/debug/elf/elf.go | 18 ++++++++++++++++++ + 2 files changed, 32 insertions(+), 1 deletion(-) + +diff --git a/src/cmd/link/internal/loadelf/ldelf.go b/src/cmd/link/internal/loadelf/ldelf.go +index e32db7ddcc..825ebb35e9 100644 +--- a/src/cmd/link/internal/loadelf/ldelf.go ++++ b/src/cmd/link/internal/loadelf/ldelf.go +@@ -1002,15 +1002,28 @@ func relSize(arch *sys.Arch, pn string, elftype uint32) (uint8, uint8, error) { + MIPS64 | uint32(elf.R_MIPS_GOT_DISP)<<16: + return 4, 4, nil + ++ case LOONG64 | uint32(elf.R_LARCH_ADD8)<<16, ++ LOONG64 | uint32(elf.R_LARCH_SUB8)<<16: ++ return 1, 1, nil ++ ++ case LOONG64 | uint32(elf.R_LARCH_ADD16)<<16, ++ LOONG64 | uint32(elf.R_LARCH_SUB16)<<16: ++ return 2, 2, nil ++ + case LOONG64 | uint32(elf.R_LARCH_MARK_LA)<<16, + LOONG64 | uint32(elf.R_LARCH_MARK_PCREL)<<16, ++ LOONG64 | uint32(elf.R_LARCH_ADD24)<<16, + LOONG64 | uint32(elf.R_LARCH_ADD32)<<16, ++ LOONG64 | uint32(elf.R_LARCH_SUB24)<<16, + LOONG64 | uint32(elf.R_LARCH_SUB32)<<16, + LOONG64 | uint32(elf.R_LARCH_B26)<<16, + LOONG64 | uint32(elf.R_LARCH_32_PCREL)<<16: + return 4, 4, nil + +- case LOONG64 | uint32(elf.R_LARCH_64)<<16: ++ case LOONG64 | uint32(elf.R_LARCH_64)<<16, ++ LOONG64 | uint32(elf.R_LARCH_ADD64)<<16, ++ LOONG64 | uint32(elf.R_LARCH_SUB64)<<16, ++ LOONG64 | uint32(elf.R_LARCH_64_PCREL)<<16: + return 8, 8, nil + + case S390X | uint32(elf.R_390_8)<<16: +diff --git a/src/debug/elf/elf.go b/src/debug/elf/elf.go +index 02cda16510..8712764607 100644 +--- a/src/debug/elf/elf.go ++++ b/src/debug/elf/elf.go +@@ -2245,6 +2245,15 @@ const ( + R_LARCH_TLS_GD_HI20 R_LARCH = 98 + R_LARCH_32_PCREL R_LARCH = 99 + R_LARCH_RELAX R_LARCH = 100 ++ R_LARCH_DELETE R_LARCH = 101 ++ R_LARCH_ALIGN R_LARCH = 102 ++ R_LARCH_PCREL20_S2 R_LARCH = 103 ++ R_LARCH_CFA R_LARCH = 104 ++ R_LARCH_ADD6 R_LARCH = 105 ++ R_LARCH_SUB6 R_LARCH = 106 ++ R_LARCH_ADD_ULEB128 R_LARCH = 107 ++ R_LARCH_SUB_ULEB128 R_LARCH = 108 ++ R_LARCH_64_PCREL R_LARCH = 109 + ) + + var rlarchStrings = []intName{ +@@ -2337,6 +2346,15 @@ var rlarchStrings = []intName{ + {98, "R_LARCH_TLS_GD_HI20"}, + {99, "R_LARCH_32_PCREL"}, + {100, "R_LARCH_RELAX"}, ++ {101, "R_LARCH_DELETE"}, ++ {102, "R_LARCH_ALIGN"}, ++ {103, "R_LARCH_PCREL20_S2"}, ++ {104, "R_LARCH_CFA"}, ++ {105, "R_LARCH_ADD6"}, ++ {106, "R_LARCH_SUB6"}, ++ {107, "R_LARCH_ADD_ULEB128"}, ++ {108, "R_LARCH_SUB_ULEB128"}, ++ {109, "R_LARCH_64_PCREL"}, + } + + func (i R_LARCH) String() string { return stringName(uint32(i), rlarchStrings, false) } +-- +2.38.1 + diff --git a/0093-api-add-new-relocations-numbered-101-to-109-for-loon.patch b/0093-api-add-new-relocations-numbered-101-to-109-for-loon.patch new file mode 100644 index 0000000..261cc00 --- /dev/null +++ b/0093-api-add-new-relocations-numbered-101-to-109-for-loon.patch @@ -0,0 +1,43 @@ +From a532a9af590b57661436e42bc0f718cb8d02b79f Mon Sep 17 00:00:00 2001 +From: chenguoqi +Date: Fri, 27 Oct 2023 16:10:20 +0800 +Subject: [PATCH] api: add new relocations numbered 101 to 109 for loong64 + +Signed-off-by: chenguoqi +Change-Id: I1fc6718b1906d3b9371bdc10bdef592764e448ce +--- + api/go1.20.txt | 18 ++++++++++++++++++ + 1 file changed, 18 insertions(+) + +diff --git a/api/go1.20.txt b/api/go1.20.txt +index fd6800ee26..936a6cef8a 100644 +--- a/api/go1.20.txt ++++ b/api/go1.20.txt +@@ -118,6 +118,24 @@ pkg debug/elf, const R_LARCH_TLS_LE_HI20 = 83 #54222 + pkg debug/elf, const R_LARCH_TLS_LE_HI20 R_LARCH #54222 + pkg debug/elf, const R_LARCH_TLS_LE_LO12 = 84 #54222 + pkg debug/elf, const R_LARCH_TLS_LE_LO12 R_LARCH #54222 ++pkg debug/elf, const R_LARCH_DELETE = 101 #54222 ++pkg debug/elf, const R_LARCH_DELETE R_LARCH #54222 ++pkg debug/elf, const R_LARCH_ALIGN = 102 #54222 ++pkg debug/elf, const R_LARCH_ALIGN R_LARCH #54222 ++pkg debug/elf, const R_LARCH_PCREL20_S2 = 103 #54222 ++pkg debug/elf, const R_LARCH_PCREL20_S2 R_LARCH #54222 ++pkg debug/elf, const R_LARCH_CFA = 104 #54222 ++pkg debug/elf, const R_LARCH_CFA R_LARCH #54222 ++pkg debug/elf, const R_LARCH_ADD6 = 105 #54222 ++pkg debug/elf, const R_LARCH_ADD6 R_LARCH #54222 ++pkg debug/elf, const R_LARCH_SUB6 = 106 #54222 ++pkg debug/elf, const R_LARCH_SUB6 R_LARCH #54222 ++pkg debug/elf, const R_LARCH_ADD_ULEB128 = 107 #54222 ++pkg debug/elf, const R_LARCH_ADD_ULEB128 R_LARCH #54222 ++pkg debug/elf, const R_LARCH_SUB_ULEB128 = 108 #54222 ++pkg debug/elf, const R_LARCH_SUB_ULEB128 R_LARCH #54222 ++pkg debug/elf, const R_LARCH_64_PCREL = 109 #54222 ++pkg debug/elf, const R_LARCH_64_PCREL R_LARCH #54222 + pkg debug/elf, const R_PPC64_ADDR16_HIGHER34 = 136 #54345 + pkg debug/elf, const R_PPC64_ADDR16_HIGHER34 R_PPC64 #54345 + pkg debug/elf, const R_PPC64_ADDR16_HIGHERA34 = 137 #54345 +-- +2.38.1 + diff --git a/golang.spec b/golang.spec index 0a0a77e..aa26e41 100644 --- a/golang.spec +++ b/golang.spec @@ -1,4 +1,4 @@ -%define anolis_release 2 +%define anolis_release 3 # Disable debuginfo packages %global debug_package %{nil} @@ -35,7 +35,7 @@ %bcond_with bootstrap # Controls what ever we fail on failed tests -%ifarch aarch64 +%ifarch aarch64 loongarch64 %bcond_with fail_on_tests %else %bcond_without fail_on_tests @@ -165,6 +165,37 @@ Patch59: 0059-cmd-compiler-runtime-internal-atomic-optimize-And-32.patch Patch60: 0060-Revert-cmd-link-workaround-linkshared-test-errors-on.patch Patch61: 0061-syscall-implement-Ptrace-Set-Get-Regs-using-PTRACE_-.patch Patch62: 0062-cmd-internal-obj-loong64-remove-the-invalid-plan9-fo.patch +Patch63: 0063-cmd-compiler-runtime-internal-atomic-Implementing-xc.patch +Patch64: 0064-cmd-compiler-runtime-internal-atomic-Implementing-xa.patch +Patch65: 0065-cmd-compiler-runtime-internal-atomic-Implementing-An.patch +Patch66: 0066-cmd-internal-obj-loong64-correct-the-instruction-for.patch +Patch67: 0067-cmd-internal-obj-loong64-recheck-jump-offset-boundar.patch +Patch68: 0068-cmd-link-internal-loong64-correct-the-glibc-dynamic-.patch +Patch69: 0069-cmd-link-internal-loadelf-correct-the-relocation-siz.patch +Patch70: 0070-cmd-compile-cmd-internal-runtime-change-the-register.patch +Patch71: 0071-cmd-compile-add-ABI-register-definations-for-loong64.patch +Patch72: 0072-cmd-compile-cmd-internal-runtime-change-registers-on.patch +Patch73: 0073-internal-abi-define-loong64-regABI-constants.patch +Patch74: 0074-cmd-compile-internal-add-register-info-for-loong64-r.patch +Patch75: 0075-cmd-compile-internal-add-spill-support-for-loong64-r.patch +Patch76: 0076-cmd-compile-update-loong64-CALL-ops.patch +Patch77: 0077-runtime-make-duff-device-as-ABIInternal-for-loong64.patch +Patch78: 0078-runtime-support-regABI-and-add-spill-functions-in-ru.patch +Patch79: 0079-reflect-runtime-add-reflect-support-for-regABI-on-lo.patch +Patch80: 0080-internal-bytealg-add-regABI-support-in-bytealg-funct.patch +Patch81: 0081-runtime-add-regABI-support-in-memclr-and-memmove-fun.patch +Patch82: 0082-cmd-internal-obj-set-morestack-arg-spilling-and-rega.patch +Patch83: 0083-cmd-compile-fix-If-lowering-on-loong64.patch +Patch84: 0084-runtime-internal-syscall-use-ABIInternal-for-Syscall.patch +Patch85: 0085-cmd-compile-internal-buildcfg-enable-regABI-on-loong.patch +Patch86: 0086-internal-abi-internal-buildcfg-always-enable-registe.patch +Patch87: 0087-all-delete-loong64-non-register-ABI-fallback-path.patch +Patch88: 0088-cmd-internal-obj-loong64-using-LookupABI-to-find-duf.patch +Patch89: 0089-cmd-internal-cmd-link-unify-the-relocation-naming-st.patch +Patch90: 0090-cmd-link-internal-loadelf-remove-useless-relocation-.patch +Patch91: 0091-cmd-link-internal-loadelf-add-additional-relocations.patch +Patch92: 0092-cmd-link-add-new-relocations-numbered-101-to-109-for.patch +Patch93: 0093-api-add-new-relocations-numbered-101-to-109-for-loon.patch Source100: golang-gdbinit @@ -597,6 +628,40 @@ fi %files docs -f go-docs.list %changelog +* Fri Oct 27 2023 Meidan Li - 1.20.9-3 +- api: add new relocations numbered 101 to 109 for loong64 +- cmd/link: add new relocations numbered 101 to 109 for loong64 +- cmd/link/internal/loadelf: add additional relocations for loong64 +- cmd/link/internal/loadelf: remove useless relocation size information of loong64 +- cmd/internal, cmd/link: unify the relocation naming style of loong64 +- cmd/internal/obj/loong64: using LookupABI to find duff{copy,zero} when rewriting GOT +- all: delete loong64 non-register ABI fallback path +- internal/abi, internal/buildcfg: always enable register ABI on loong64 +- cmd/compile, internal/buildcfg: enable regABI on loong64, and add loong64 in test func hasRegisterABI +- runtime/internal/syscall: use ABIInternal for Syscall6 on loong64 +- cmd/compile: fix If lowering on loong64 +- cmd/internal/obj: set morestack arg spilling and regabi prologue on loong64 +- runtime: add regABI support in memclr and memmove functions on loong64 +- internal/bytealg: add regABI support in bytealg functions on loong64 +- reflect, runtime: add reflect support for regABI on loong64 +- runtime: support regABI and add spill functions in runtime for loong64 +- runtime: make duff device as ABIInternal for loong64 +- cmd/compile: update loong64 CALL* ops +- cmd/compile/internal: add spill support for loong64 regABI +- cmd/compile/internal: add register info for loong64 regABI +- internal/abi: define loong64 regABI constants +- cmd/compile,cmd/internal,runtime: change registers on loong64 to avoid regABI arguments +- cmd/compile: add ABI register definations for loong64 +- cmd/compile, cmd/internal, runtime: change the registers used by the duff device for loong64 +- cmd/link/internal/loadelf: correct the relocation size of R_LARCH_64 +- cmd/link/internal/loong64: correct the glibc dynamic linker path. +- cmd/internal/obj/loong64: recheck jump offset boundary after auto-aligning loop heads +- cmd/internal/obj/loong64: correct the instruction format of plan9 assembly NOOP +- cmd/compiler,runtime/internal/atomic: Implementing {And,Or}{32,8} using am{and,or}dbw on loong64 +- cmd/compiler,runtime/internal/atomic: Implementing xadd{,64} using amadddb{w,d} on loong64 +- cmd/compiler,runtime/internal/atomic: Implementing xchg{,64} using amswapdb{w,d} on loong64 +- internal/sysinfo: print cpu type from cpuinfo when internal cpu name is empty on Linux + * Wed Oct 18 2023 Meidan Li - 1.20.9-2 - cmd/asm: add RDTIME{L,H}.W, RDTIME.D support for loong64 - runtime: implement cputicks with the stable counter on loong64 -- Gitee