diff --git a/LoongArch64.patch b/LoongArch64.patch index 0cc36eb6234025378fc8540089740354afebbe39..3feb37829321e97246fbae1a3a8baafc11d3217a 100644 --- a/LoongArch64.patch +++ b/LoongArch64.patch @@ -1,8 +1,8 @@ diff --git a/make/CompileJavaModules.gmk b/make/CompileJavaModules.gmk -index 40c7e06f54..142485c05a 100644 +index 46fb9b4219..c6d8b24fc4 100644 --- a/make/CompileJavaModules.gmk +++ b/make/CompileJavaModules.gmk -@@ -434,6 +434,7 @@ jdk.internal.vm.ci_ADD_JAVAC_FLAGS += -parameters -Xlint:-exports -XDstringConca +@@ -430,6 +430,7 @@ jdk.internal.vm.ci_ADD_JAVAC_FLAGS += -parameters -Xlint:-exports -XDstringConca jdk.internal.vm.compiler_ADD_JAVAC_FLAGS += -parameters -XDstringConcat=inline \ --add-exports jdk.internal.vm.ci/jdk.vm.ci.aarch64=jdk.internal.vm.compiler \ @@ -10,7 +10,7 @@ index 40c7e06f54..142485c05a 100644 --add-exports jdk.internal.vm.ci/jdk.vm.ci.amd64=jdk.internal.vm.compiler \ --add-exports jdk.internal.vm.ci/jdk.vm.ci.code=jdk.internal.vm.compiler \ --add-exports jdk.internal.vm.ci/jdk.vm.ci.code.site=jdk.internal.vm.compiler \ -@@ -441,6 +442,7 @@ jdk.internal.vm.compiler_ADD_JAVAC_FLAGS += -parameters -XDstringConcat=inline \ +@@ -437,6 +438,7 @@ jdk.internal.vm.compiler_ADD_JAVAC_FLAGS += -parameters -XDstringConcat=inline \ --add-exports jdk.internal.vm.ci/jdk.vm.ci.common=jdk.internal.vm.compiler \ --add-exports jdk.internal.vm.ci/jdk.vm.ci.hotspot=jdk.internal.vm.compiler \ --add-exports jdk.internal.vm.ci/jdk.vm.ci.hotspot.aarch64=jdk.internal.vm.compiler \ @@ -18,7 +18,7 @@ index 40c7e06f54..142485c05a 100644 --add-exports jdk.internal.vm.ci/jdk.vm.ci.hotspot.amd64=jdk.internal.vm.compiler \ --add-exports jdk.internal.vm.ci/jdk.vm.ci.hotspot.sparc=jdk.internal.vm.compiler \ --add-exports jdk.internal.vm.ci/jdk.vm.ci.meta=jdk.internal.vm.compiler \ -@@ -460,6 +462,7 @@ jdk.internal.vm.compiler_EXCLUDES += \ +@@ -456,6 +458,7 @@ jdk.internal.vm.compiler_EXCLUDES += \ org.graalvm.compiler.api.directives.test \ org.graalvm.compiler.api.test \ org.graalvm.compiler.asm.aarch64.test \ @@ -438,10 +438,10 @@ index 0000000000..0412b99537 + diff --git a/src/hotspot/cpu/loongarch/assembler_loongarch.cpp b/src/hotspot/cpu/loongarch/assembler_loongarch.cpp new file mode 100644 -index 0000000000..67c9a859aa +index 0000000000..e6e62cccad --- /dev/null +++ b/src/hotspot/cpu/loongarch/assembler_loongarch.cpp -@@ -0,0 +1,850 @@ +@@ -0,0 +1,849 @@ +/* + * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2015, 2021, Loongson Technology. All rights reserved. @@ -853,7 +853,6 @@ index 0000000000..67c9a859aa + ldx_w(dst, base, AT); + } + } -+//Disassembler::decode(pc()-32, pc(), tty); +} + +void Assembler::ld_wu(Register rd, Address src){ @@ -1294,10 +1293,10 @@ index 0000000000..67c9a859aa +} diff --git a/src/hotspot/cpu/loongarch/assembler_loongarch.hpp b/src/hotspot/cpu/loongarch/assembler_loongarch.hpp new file mode 100644 -index 0000000000..9f50e46138 +index 0000000000..179da7bd0e --- /dev/null +++ b/src/hotspot/cpu/loongarch/assembler_loongarch.hpp -@@ -0,0 +1,2804 @@ +@@ -0,0 +1,2827 @@ +/* + * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2015, 2021, Loongson Technology. All rights reserved. @@ -2614,6 +2613,15 @@ index 0000000000..9f50e46138 + static int high6 (int x) { return high(x, 6); } + + ++ static ALWAYSINLINE void patch(address a, int length, uint32_t val) { ++ guarantee(val < (1ULL << length), "Field too big for insn"); ++ guarantee(length > 0, "length > 0"); ++ unsigned target = *(unsigned *)a; ++ target = (target >> length) << length; ++ target |= val; ++ *(unsigned *)a = target; ++ } ++ + protected: + // help methods for instruction ejection + @@ -2859,10 +2867,20 @@ index 0000000000..9f50e46138 + AbstractAssembler::flush(); + } + -+ inline void emit_int32(int); ++ inline void emit_int32(int x) { ++ AbstractAssembler::emit_int32(x); ++ } ++ + inline void emit_data(int x) { emit_int32(x); } -+ inline void emit_data(int, RelocationHolder const&); -+ inline void emit_data(int, relocInfo::relocType rtype); ++ inline void emit_data(int x, relocInfo::relocType rtype) { ++ relocate(rtype); ++ emit_int32(x); ++ } ++ ++ inline void emit_data(int x, RelocationHolder const& rspec) { ++ relocate(rspec); ++ emit_int32(x); ++ } + + + // Generic instructions @@ -3317,18 +3335,25 @@ index 0000000000..9f50e46138 + void bceqz(ConditionalFlagRegister cj, Label& L) { bceqz(cj, target(L)); } + void bcnez(ConditionalFlagRegister cj, Label& L) { bcnez(cj, target(L)); } + -+ // Now Membar_mask_bits is 0,Need to fix it after LA6000 + typedef enum { -+ StoreStore = 0, -+ LoadStore = 0, -+ StoreLoad = 0, -+ LoadLoad = 0, -+ AnyAny = 0 ++ // hint[4] ++ Completion = 0, ++ Ordering = (1 << 4), ++ ++ // The bitwise-not of the below constants is corresponding to the hint. This is convenient for OR operation. ++ // hint[3:2] and hint[1:0] ++ LoadLoad = ((1 << 3) | (1 << 1)), ++ LoadStore = ((1 << 3) | (1 << 0)), ++ StoreLoad = ((1 << 2) | (1 << 1)), ++ StoreStore = ((1 << 2) | (1 << 0)), ++ AnyAny = ((3 << 2) | (3 << 0)), + } Membar_mask_bits; + + // Serializes memory and blows flags + void membar(Membar_mask_bits hint) { -+ dbar(hint); ++ assert((hint & (3 << 0)) != 0, "membar mask unsupported!"); ++ assert((hint & (3 << 2)) != 0, "membar mask unsupported!"); ++ dbar(Ordering | (~hint & 0xf)); + } + + // LSX and LASX @@ -4098,16 +4123,13 @@ index 0000000000..9f50e46138 + static address locate_next_instruction(address inst); +}; + -+ -+#include "assembler_loongarch.inline.hpp" -+ +#endif // CPU_LOONGARCH_ASSEMBLER_LOONGARCH_HPP diff --git a/src/hotspot/cpu/loongarch/assembler_loongarch.inline.hpp b/src/hotspot/cpu/loongarch/assembler_loongarch.inline.hpp new file mode 100644 -index 0000000000..616cd9efe2 +index 0000000000..9ca0cd4504 --- /dev/null +++ b/src/hotspot/cpu/loongarch/assembler_loongarch.inline.hpp -@@ -0,0 +1,47 @@ +@@ -0,0 +1,33 @@ +/* + * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. @@ -4140,20 +4162,6 @@ index 0000000000..616cd9efe2 +#include "asm/codeBuffer.hpp" +#include "code/codeCache.hpp" + -+inline void Assembler::emit_int32(int x) { -+ AbstractAssembler::emit_int32(x); -+} -+ -+inline void Assembler::emit_data(int x, relocInfo::relocType rtype) { -+ relocate(rtype); -+ emit_int32(x); -+} -+ -+inline void Assembler::emit_data(int x, RelocationHolder const& rspec) { -+ relocate(rspec); -+ emit_int32(x); -+} -+ +#endif // CPU_LOONGARCH_ASSEMBLER_LOONGARCH_INLINE_HPP diff --git a/src/hotspot/cpu/loongarch/bytes_loongarch.hpp b/src/hotspot/cpu/loongarch/bytes_loongarch.hpp new file mode 100644 @@ -13692,10 +13700,10 @@ index 0000000000..1ddc038eea +#endif // CPU_LOONGARCH_FRAME_LOONGARCH_INLINE_HPP diff --git a/src/hotspot/cpu/loongarch/gc/g1/g1BarrierSetAssembler_loongarch.cpp b/src/hotspot/cpu/loongarch/gc/g1/g1BarrierSetAssembler_loongarch.cpp new file mode 100644 -index 0000000000..2cdf3dddb7 +index 0000000000..e1e4748c49 --- /dev/null +++ b/src/hotspot/cpu/loongarch/gc/g1/g1BarrierSetAssembler_loongarch.cpp -@@ -0,0 +1,520 @@ +@@ -0,0 +1,523 @@ +/* + * Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2021, Loongson Technology. All rights reserved. @@ -13741,7 +13749,7 @@ index 0000000000..2cdf3dddb7 +#define __ masm-> + +void G1BarrierSetAssembler::gen_write_ref_array_pre_barrier(MacroAssembler* masm, DecoratorSet decorators, -+ Register addr, Register count) { ++ Register addr, Register count, RegSet saved_regs) { + bool dest_uninitialized = (decorators & IS_DEST_UNINITIALIZED) != 0; + + if (!dest_uninitialized) { @@ -13764,7 +13772,7 @@ index 0000000000..2cdf3dddb7 + + __ beqz(AT, filtered); + -+ __ pushad(); // push registers ++ __ push(saved_regs); + if (count == A0) { + if (addr == A1) { + __ move(AT, A0); @@ -13783,15 +13791,15 @@ index 0000000000..2cdf3dddb7 + } else { + __ call_VM_leaf(CAST_FROM_FN_PTR(address, G1BarrierSetRuntime::write_ref_array_pre_oop_entry), 2); + } -+ __ popad(); ++ __ pop(saved_regs); + + __ bind(filtered); + } +} + +void G1BarrierSetAssembler::gen_write_ref_array_post_barrier(MacroAssembler* masm, DecoratorSet decorators, -+ Register addr, Register count, Register tmp) { -+ __ pushad(); // push registers (overkill) ++ Register addr, Register count, Register tmp, RegSet saved_regs) { ++ __ push(saved_regs); + if (count == A0) { + assert_different_registers(A1, addr); + __ move(A1, count); @@ -13802,7 +13810,7 @@ index 0000000000..2cdf3dddb7 + __ move(A1, count); + } + __ call_VM_leaf(CAST_FROM_FN_PTR(address, G1BarrierSetRuntime::write_ref_array_post_entry), 2); -+ __ popad(); ++ __ pop(saved_regs); +} + +void G1BarrierSetAssembler::load_at(MacroAssembler* masm, DecoratorSet decorators, BasicType type, @@ -13817,6 +13825,8 @@ index 0000000000..2cdf3dddb7 +#ifndef OPT_THREAD + __ get_thread(thread); +#endif ++ // RA is live. It must be saved around calls. ++ __ enter(); // barrier may call runtime + // Generate the G1 pre-barrier code to log the value of + // the referent field in an SATB buffer. + g1_write_barrier_pre(masm /* masm */, @@ -13826,6 +13836,7 @@ index 0000000000..2cdf3dddb7 + tmp1 /* tmp */, + true /* tosca_live */, + true /* expand_call */); ++ __ leave(); + } +} + @@ -14218,13 +14229,13 @@ index 0000000000..2cdf3dddb7 +#endif // COMPILER1 diff --git a/src/hotspot/cpu/loongarch/gc/g1/g1BarrierSetAssembler_loongarch.hpp b/src/hotspot/cpu/loongarch/gc/g1/g1BarrierSetAssembler_loongarch.hpp new file mode 100644 -index 0000000000..2c48629d95 +index 0000000000..745046ac0c --- /dev/null +++ b/src/hotspot/cpu/loongarch/gc/g1/g1BarrierSetAssembler_loongarch.hpp @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2021, Loongson Technology. All rights reserved. ++ * Copyright (c) 2022, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -14260,8 +14271,8 @@ index 0000000000..2c48629d95 + +class G1BarrierSetAssembler: public ModRefBarrierSetAssembler { + protected: -+ virtual void gen_write_ref_array_pre_barrier(MacroAssembler* masm, DecoratorSet decorators, Register addr, Register count); -+ virtual void gen_write_ref_array_post_barrier(MacroAssembler* masm, DecoratorSet decorators, Register addr, Register count, Register tmp); ++ virtual void gen_write_ref_array_pre_barrier(MacroAssembler* masm, DecoratorSet decorators, Register addr, Register count, RegSet saved_regs); ++ virtual void gen_write_ref_array_post_barrier(MacroAssembler* masm, DecoratorSet decorators, Register addr, Register count, Register tmp, RegSet saved_regs); + + void g1_write_barrier_pre(MacroAssembler* masm, + Register obj, @@ -14295,10 +14306,10 @@ index 0000000000..2c48629d95 +#endif // CPU_LOONGARCH_GC_G1_G1BARRIERSETASSEMBLER_LOONGARCH_HPP diff --git a/src/hotspot/cpu/loongarch/gc/shared/barrierSetAssembler_loongarch.cpp b/src/hotspot/cpu/loongarch/gc/shared/barrierSetAssembler_loongarch.cpp new file mode 100644 -index 0000000000..c54721e46f +index 0000000000..a890cd3f62 --- /dev/null +++ b/src/hotspot/cpu/loongarch/gc/shared/barrierSetAssembler_loongarch.cpp -@@ -0,0 +1,253 @@ +@@ -0,0 +1,255 @@ +/* + * Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2018, 2022, Loongson Technology. All rights reserved. @@ -14335,6 +14346,8 @@ index 0000000000..c54721e46f + +void BarrierSetAssembler::load_at(MacroAssembler* masm, DecoratorSet decorators, BasicType type, + Register dst, Address src, Register tmp1, Register tmp_thread) { ++ // RA is live. It must be saved around calls. ++ + bool in_heap = (decorators & IN_HEAP) != 0; + bool in_native = (decorators & IN_NATIVE) != 0; + bool is_not_null = (decorators & IS_NOT_NULL) != 0; @@ -14554,13 +14567,13 @@ index 0000000000..c54721e46f +} diff --git a/src/hotspot/cpu/loongarch/gc/shared/barrierSetAssembler_loongarch.hpp b/src/hotspot/cpu/loongarch/gc/shared/barrierSetAssembler_loongarch.hpp new file mode 100644 -index 0000000000..9830c610c5 +index 0000000000..a7ebbfaabb --- /dev/null +++ b/src/hotspot/cpu/loongarch/gc/shared/barrierSetAssembler_loongarch.hpp @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2018, 2021, Loongson Technology. All rights reserved. ++ * Copyright (c) 2018, 2022, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -14602,9 +14615,9 @@ index 0000000000..9830c610c5 + +public: + virtual void arraycopy_prologue(MacroAssembler* masm, DecoratorSet decorators, bool is_oop, -+ Register dst, Register count, Register scratch = NOREG) {} ++ Register dst, Register count, RegSet saved_regs) {} + virtual void arraycopy_epilogue(MacroAssembler* masm, DecoratorSet decorators, bool is_oop, -+ Register dst, Register count, Register scratch = NOREG) {} ++ Register dst, Register count, Register scratch, RegSet saved_regs) {} + + virtual void load_at(MacroAssembler* masm, DecoratorSet decorators, BasicType type, + Register dst, Address src, Register tmp1, Register tmp_thread); @@ -14648,10 +14661,10 @@ index 0000000000..9830c610c5 +#endif // CPU_LOONGARCH_GC_SHARED_BARRIERSETASSEMBLER_LOONGARCH_HPP diff --git a/src/hotspot/cpu/loongarch/gc/shared/cardTableBarrierSetAssembler_loongarch.cpp b/src/hotspot/cpu/loongarch/gc/shared/cardTableBarrierSetAssembler_loongarch.cpp new file mode 100644 -index 0000000000..06e5a455eb +index 0000000000..749d3a3f79 --- /dev/null +++ b/src/hotspot/cpu/loongarch/gc/shared/cardTableBarrierSetAssembler_loongarch.cpp -@@ -0,0 +1,141 @@ +@@ -0,0 +1,142 @@ +/* + * Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2018, Loongson Technology. All rights reserved. @@ -14699,7 +14712,8 @@ index 0000000000..06e5a455eb +#define TIMES_OOP (UseCompressedOops ? Address::times_4 : Address::times_8) + +void CardTableBarrierSetAssembler::gen_write_ref_array_post_barrier(MacroAssembler* masm, DecoratorSet decorators, -+ Register addr, Register count, Register tmp) { ++ Register addr, Register count, Register tmp, ++ RegSet saved_regs) { + BarrierSet *bs = BarrierSet::barrier_set(); + CardTableBarrierSet* ctbs = barrier_set_cast(bs); + CardTable* ct = ctbs->card_table(); @@ -14795,13 +14809,13 @@ index 0000000000..06e5a455eb +} diff --git a/src/hotspot/cpu/loongarch/gc/shared/cardTableBarrierSetAssembler_loongarch.hpp b/src/hotspot/cpu/loongarch/gc/shared/cardTableBarrierSetAssembler_loongarch.hpp new file mode 100644 -index 0000000000..eb649cb654 +index 0000000000..b37c2ba0bc --- /dev/null +++ b/src/hotspot/cpu/loongarch/gc/shared/cardTableBarrierSetAssembler_loongarch.hpp -@@ -0,0 +1,42 @@ +@@ -0,0 +1,44 @@ +/* + * Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2018, 2021, Loongson Technology. All rights reserved. ++ * Copyright (c) 2018, 2022, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -14834,7 +14848,9 @@ index 0000000000..eb649cb654 +protected: + void store_check(MacroAssembler* masm, Register obj, Address dst); + -+ virtual void gen_write_ref_array_post_barrier(MacroAssembler* masm, DecoratorSet decorators, Register addr, Register count, Register tmp); ++ virtual void gen_write_ref_array_post_barrier(MacroAssembler* masm, DecoratorSet decorators, ++ Register addr, Register count, Register tmp, ++ RegSet saved_regs); + + virtual void oop_store_at(MacroAssembler* masm, DecoratorSet decorators, BasicType type, + Address dst, Register val, Register tmp1, Register tmp2); @@ -14843,13 +14859,13 @@ index 0000000000..eb649cb654 +#endif // CPU_LOONGARCH_GC_SHARED_CARDTABLEBARRIERSETASSEMBLER_LOONGARCH_HPP diff --git a/src/hotspot/cpu/loongarch/gc/shared/modRefBarrierSetAssembler_loongarch.cpp b/src/hotspot/cpu/loongarch/gc/shared/modRefBarrierSetAssembler_loongarch.cpp new file mode 100644 -index 0000000000..049ec24e27 +index 0000000000..14c41ea790 --- /dev/null +++ b/src/hotspot/cpu/loongarch/gc/shared/modRefBarrierSetAssembler_loongarch.cpp @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2018, 2021, Loongson Technology. All rights reserved. ++ * Copyright (c) 2018, 2022, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -14879,16 +14895,16 @@ index 0000000000..049ec24e27 +#define __ masm-> + +void ModRefBarrierSetAssembler::arraycopy_prologue(MacroAssembler* masm, DecoratorSet decorators, bool is_oop, -+ Register dst, Register count, Register scratch) { ++ Register dst, Register count, RegSet saved_regs) { + if (is_oop) { -+ gen_write_ref_array_pre_barrier(masm, decorators, dst, count); ++ gen_write_ref_array_pre_barrier(masm, decorators, dst, count, saved_regs); + } +} + +void ModRefBarrierSetAssembler::arraycopy_epilogue(MacroAssembler* masm, DecoratorSet decorators, bool is_oop, -+ Register dst, Register count, Register scratch) { ++ Register dst, Register count, Register scratch, RegSet saved_regs) { + if (is_oop) { -+ gen_write_ref_array_post_barrier(masm, decorators, dst, count, scratch); ++ gen_write_ref_array_post_barrier(masm, decorators, dst, count, scratch, saved_regs); + } +} + @@ -14902,13 +14918,13 @@ index 0000000000..049ec24e27 +} diff --git a/src/hotspot/cpu/loongarch/gc/shared/modRefBarrierSetAssembler_loongarch.hpp b/src/hotspot/cpu/loongarch/gc/shared/modRefBarrierSetAssembler_loongarch.hpp new file mode 100644 -index 0000000000..18a6f92bc2 +index 0000000000..8043220eff --- /dev/null +++ b/src/hotspot/cpu/loongarch/gc/shared/modRefBarrierSetAssembler_loongarch.hpp @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2018, 2021, Loongson Technology. All rights reserved. ++ * Copyright (c) 2018, 2022, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -14944,16 +14960,16 @@ index 0000000000..18a6f92bc2 +class ModRefBarrierSetAssembler: public BarrierSetAssembler { +protected: + virtual void gen_write_ref_array_pre_barrier(MacroAssembler* masm, DecoratorSet decorators, -+ Register addr, Register count) {} ++ Register addr, Register count, RegSet saved_regs) {} + virtual void gen_write_ref_array_post_barrier(MacroAssembler* masm, DecoratorSet decorators, -+ Register addr, Register count, Register tmp) {} ++ Register addr, Register count, Register tmp, RegSet saved_regs) {} + virtual void oop_store_at(MacroAssembler* masm, DecoratorSet decorators, BasicType type, + Address dst, Register val, Register tmp1, Register tmp2) = 0; +public: + virtual void arraycopy_prologue(MacroAssembler* masm, DecoratorSet decorators, bool is_oop, -+ Register dst, Register count, Register scratch = NOREG); ++ Register dst, Register count, RegSet saved_regs); + virtual void arraycopy_epilogue(MacroAssembler* masm, DecoratorSet decorators, bool is_oop, -+ Register dst, Register count, Register scratch = NOREG); ++ Register dst, Register count, Register scratch, RegSet saved_regs); + + virtual void store_at(MacroAssembler* masm, DecoratorSet decorators, BasicType type, + Address dst, Register val, Register tmp1, Register tmp2); @@ -18105,10 +18121,10 @@ index 0000000000..6814fa44a0 +#endif // CPU_LOONGARCH_JAVAFRAMEANCHOR_LOONGARCH_HPP diff --git a/src/hotspot/cpu/loongarch/jniFastGetField_loongarch_64.cpp b/src/hotspot/cpu/loongarch/jniFastGetField_loongarch_64.cpp new file mode 100644 -index 0000000000..114e47b053 +index 0000000000..dbcdb7a6a4 --- /dev/null +++ b/src/hotspot/cpu/loongarch/jniFastGetField_loongarch_64.cpp -@@ -0,0 +1,165 @@ +@@ -0,0 +1,166 @@ +/* + * Copyright (c) 2004, 2010, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2015, 2021, Loongson Technology. All rights reserved. @@ -18136,6 +18152,7 @@ index 0000000000..114e47b053 + +#include "precompiled.hpp" +#include "asm/macroAssembler.hpp" ++#include "code/codeBlob.hpp" +#include "gc/shared/barrierSet.hpp" +#include "gc/shared/barrierSetAssembler.hpp" +#include "memory/resourceArea.hpp" @@ -32574,13 +32591,13 @@ index 0000000000..a5fb5f7b85 + diff --git a/src/hotspot/cpu/loongarch/macroAssembler_loongarch.cpp b/src/hotspot/cpu/loongarch/macroAssembler_loongarch.cpp new file mode 100644 -index 0000000000..74cda82963 +index 0000000000..9720fd176d --- /dev/null +++ b/src/hotspot/cpu/loongarch/macroAssembler_loongarch.cpp -@@ -0,0 +1,4531 @@ +@@ -0,0 +1,4567 @@ +/* + * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2017, 2022, Loongson Technology. All rights reserved. ++ * Copyright (c) 2017, 2023, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -34406,7 +34423,7 @@ index 0000000000..74cda82963 + + bind(fail); + if (barrier) -+ membar(LoadLoad); ++ dbar(0x700); + if (retold && oldval != R0) + move(oldval, resflag); + move(resflag, R0); @@ -34429,7 +34446,7 @@ index 0000000000..74cda82963 + + bind(neq); + if (barrier) -+ membar(LoadLoad); ++ dbar(0x700); + if (retold && oldval != R0) + move(oldval, tmp); + if (fail) @@ -34454,7 +34471,7 @@ index 0000000000..74cda82963 + + bind(fail); + if (barrier) -+ membar(LoadLoad); ++ dbar(0x700); + if (retold && oldval != R0) + move(oldval, resflag); + move(resflag, R0); @@ -34479,7 +34496,7 @@ index 0000000000..74cda82963 + + bind(neq); + if (barrier) -+ membar(LoadLoad); ++ dbar(0x700); + if (retold && oldval != R0) + move(oldval, tmp); + if (fail) @@ -34857,7 +34874,7 @@ index 0000000000..74cda82963 + move(AT, R0); + bnez(scrReg, DONE_SET); + -+ membar(Assembler::Membar_mask_bits(LoadLoad|LoadStore)); ++ membar(Assembler::Membar_mask_bits(LoadStore|StoreStore)); + st_d(R0, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes() - 2)); + li(resReg, 1); + b(DONE); @@ -34981,6 +34998,38 @@ index 0000000000..74cda82963 + addi_d(SP, SP, 16); +} + ++void MacroAssembler::push(unsigned int bitset) { ++ unsigned char regs[31]; ++ int count = 0; ++ ++ bitset >>= 1; ++ for (int reg = 1; reg < 31; reg++) { ++ if (1 & bitset) ++ regs[count++] = reg; ++ bitset >>= 1; ++ } ++ ++ addi_d(SP, SP, -align_up(count, 2) * wordSize); ++ for (int i = 0; i < count; i ++) ++ st_d(as_Register(regs[i]), SP, i * wordSize); ++} ++ ++void MacroAssembler::pop(unsigned int bitset) { ++ unsigned char regs[31]; ++ int count = 0; ++ ++ bitset >>= 1; ++ for (int reg = 1; reg < 31; reg++) { ++ if (1 & bitset) ++ regs[count++] = reg; ++ bitset >>= 1; ++ } ++ ++ for (int i = 0; i < count; i ++) ++ ld_d(as_Register(regs[i]), SP, i * wordSize); ++ addi_d(SP, SP, align_up(count, 2) * wordSize); ++} ++ +// for UseCompressedOops Option +void MacroAssembler::load_klass(Register dst, Register src) { + if(UseCompressedClassPointers){ @@ -37030,10 +37079,14 @@ index 0000000000..74cda82963 + address last = code()->last_insn(); + if (last != NULL && ((NativeInstruction*)last)->is_sync() && prev == last) { + code()->set_last_insn(NULL); ++ NativeMembar *membar = (NativeMembar*)prev; ++ // merged membar ++ // e.g. LoadLoad and LoadLoad|LoadStore to LoadLoad|LoadStore ++ membar->set_hint(membar->get_hint() & (~hint & 0xF)); + block_comment("merged membar"); + } else { + code()->set_last_insn(pc()); -+ dbar(hint); ++ Assembler::membar(hint); + } +} + @@ -37111,10 +37164,10 @@ index 0000000000..74cda82963 + diff --git a/src/hotspot/cpu/loongarch/macroAssembler_loongarch.hpp b/src/hotspot/cpu/loongarch/macroAssembler_loongarch.hpp new file mode 100644 -index 0000000000..d49cf2e680 +index 0000000000..1f96557543 --- /dev/null +++ b/src/hotspot/cpu/loongarch/macroAssembler_loongarch.hpp -@@ -0,0 +1,820 @@ +@@ -0,0 +1,825 @@ +/* + * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. @@ -37700,6 +37753,8 @@ index 0000000000..d49cf2e680 + void popad(); + void pushad_except_v0(); + void popad_except_v0(); ++ void push(RegSet regs) { if (regs.bits()) push(regs.bits()); } ++ void pop(RegSet regs) { if (regs.bits()) pop(regs.bits()); } + + void li(Register rd, jlong value); + void li(Register rd, address addr) { li(rd, (long)addr); } @@ -37870,6 +37925,9 @@ index 0000000000..d49cf2e680 +#endif + +private: ++ void push(unsigned int bitset); ++ void pop(unsigned int bitset); ++ + template + void loadstore_t(T reg, int base, int index, int scale, int disp, int type) { + if (index != 0) { @@ -40246,10 +40304,10 @@ index 0000000000..f84337424b + } diff --git a/src/hotspot/cpu/loongarch/nativeInst_loongarch.cpp b/src/hotspot/cpu/loongarch/nativeInst_loongarch.cpp new file mode 100644 -index 0000000000..0ee3fba75b +index 0000000000..9234befae3 --- /dev/null +++ b/src/hotspot/cpu/loongarch/nativeInst_loongarch.cpp -@@ -0,0 +1,505 @@ +@@ -0,0 +1,511 @@ +/* + * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2015, 2021, Loongson Technology. All rights reserved. @@ -40287,6 +40345,10 @@ index 0000000000..0ee3fba75b +#include "runtime/stubRoutines.hpp" +#include "utilities/ostream.hpp" + ++#ifndef PRODUCT ++#include "compiler/disassembler.hpp" ++#endif ++ +#include + +#define T0 RT0 @@ -40588,7 +40650,9 @@ index 0000000000..0ee3fba75b + return Assembler::simm12((int_at(0) >> 10) & 0xfff); + } + -+ //Disassembler::decode(addr_at(0), addr_at(0) + 16, tty); ++#ifndef PRODUCT ++ Disassembler::decode(addr_at(0), addr_at(0) + 16, tty); ++#endif + fatal("not a mov reg, imm52"); + return 0; // unreachable +} @@ -40757,10 +40821,10 @@ index 0000000000..0ee3fba75b +} diff --git a/src/hotspot/cpu/loongarch/nativeInst_loongarch.hpp b/src/hotspot/cpu/loongarch/nativeInst_loongarch.hpp new file mode 100644 -index 0000000000..195a2df580 +index 0000000000..a6e9d4dd3c --- /dev/null +++ b/src/hotspot/cpu/loongarch/nativeInst_loongarch.hpp -@@ -0,0 +1,521 @@ +@@ -0,0 +1,528 @@ +/* + * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2015, 2021, Loongson Technology. All rights reserved. @@ -41281,6 +41345,13 @@ index 0000000000..195a2df580 + assert(ni->is_NativeCallTrampolineStub_at(), "no call trampoline found"); + return (NativeCallTrampolineStub*)addr; +} ++ ++class NativeMembar : public NativeInstruction { ++public: ++ unsigned int get_hint() { return Assembler::low(insn_word(), 4); } ++ void set_hint(int hint) { Assembler::patch(addr_at(0), 4, hint); } ++}; ++ +#endif // CPU_LOONGARCH_NATIVEINST_LOONGARCH_HPP diff --git a/src/hotspot/cpu/loongarch/registerMap_loongarch.hpp b/src/hotspot/cpu/loongarch/registerMap_loongarch.hpp new file mode 100644 @@ -41511,13 +41582,13 @@ index 0000000000..54d90167a5 +} diff --git a/src/hotspot/cpu/loongarch/register_loongarch.hpp b/src/hotspot/cpu/loongarch/register_loongarch.hpp new file mode 100644 -index 0000000000..8d99dc9688 +index 0000000000..da876a5083 --- /dev/null +++ b/src/hotspot/cpu/loongarch/register_loongarch.hpp -@@ -0,0 +1,428 @@ +@@ -0,0 +1,495 @@ +/* + * Copyright (c) 2000, 2012, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2021, Loongson Technology. All rights reserved. ++ * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -41942,6 +42013,73 @@ index 0000000000..8d99dc9688 + static const int max_fpr; +}; + ++// A set of registers ++template ++class AbstractRegSet { ++ uint32_t _bitset; ++ ++ AbstractRegSet(uint32_t bitset) : _bitset(bitset) { } ++ ++public: ++ ++ AbstractRegSet() : _bitset(0) { } ++ ++ AbstractRegSet(RegImpl r1) : _bitset(1 << r1->encoding()) { } ++ ++ AbstractRegSet operator+(const AbstractRegSet aSet) const { ++ AbstractRegSet result(_bitset | aSet._bitset); ++ return result; ++ } ++ ++ AbstractRegSet operator-(const AbstractRegSet aSet) const { ++ AbstractRegSet result(_bitset & ~aSet._bitset); ++ return result; ++ } ++ ++ AbstractRegSet &operator+=(const AbstractRegSet aSet) { ++ *this = *this + aSet; ++ return *this; ++ } ++ ++ AbstractRegSet &operator-=(const AbstractRegSet aSet) { ++ *this = *this - aSet; ++ return *this; ++ } ++ ++ static AbstractRegSet of(RegImpl r1) { ++ return AbstractRegSet(r1); ++ } ++ ++ static AbstractRegSet of(RegImpl r1, RegImpl r2) { ++ return of(r1) + r2; ++ } ++ ++ static AbstractRegSet of(RegImpl r1, RegImpl r2, RegImpl r3) { ++ return of(r1, r2) + r3; ++ } ++ ++ static AbstractRegSet of(RegImpl r1, RegImpl r2, RegImpl r3, RegImpl r4) { ++ return of(r1, r2, r3) + r4; ++ } ++ ++ static AbstractRegSet of(RegImpl r1, RegImpl r2, RegImpl r3, RegImpl r4, RegImpl r5) { ++ return of(r1, r2, r3, r4) + r5; ++ } ++ ++ static AbstractRegSet range(RegImpl start, RegImpl end) { ++ uint32_t bits = ~0; ++ bits <<= start->encoding(); ++ bits <<= 31 - end->encoding(); ++ bits >>= 31 - end->encoding(); ++ ++ return AbstractRegSet(bits); ++ } ++ ++ uint32_t bits() const { return _bitset; } ++}; ++ ++typedef AbstractRegSet RegSet; ++ +#endif //CPU_LOONGARCH_REGISTER_LOONGARCH_HPP diff --git a/src/hotspot/cpu/loongarch/relocInfo_loongarch.cpp b/src/hotspot/cpu/loongarch/relocInfo_loongarch.cpp new file mode 100644 @@ -45957,10 +46095,10 @@ index 0000000000..736ed0a85f +extern "C" int SpinPause() {return 0;} diff --git a/src/hotspot/cpu/loongarch/stubGenerator_loongarch_64.cpp b/src/hotspot/cpu/loongarch/stubGenerator_loongarch_64.cpp new file mode 100644 -index 0000000000..7b5c23b8b5 +index 0000000000..0549c3c58f --- /dev/null +++ b/src/hotspot/cpu/loongarch/stubGenerator_loongarch_64.cpp -@@ -0,0 +1,4827 @@ +@@ -0,0 +1,4804 @@ +/* + * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. @@ -48025,7 +48163,7 @@ index 0000000000..7b5c23b8b5 + __ st_d(RA, SP, 0 * wordSize); + + bs = BarrierSet::barrier_set()->barrier_set_assembler(); -+ bs->arraycopy_prologue(_masm, decorators, is_oop, A1, A2); ++ bs->arraycopy_prologue(_masm, decorators, is_oop, A1, A2, RegSet()); + + __ ld_d(A2, SP, 3 * wordSize); + __ ld_d(A1, SP, 2 * wordSize); @@ -48069,7 +48207,7 @@ index 0000000000..7b5c23b8b5 + __ ld_d(A2, SP, 3 * wordSize); + __ ld_d(A1, SP, 2 * wordSize); + -+ bs->arraycopy_epilogue(_masm, decorators, is_oop, A1, A2, T1); ++ bs->arraycopy_epilogue(_masm, decorators, is_oop, A1, A2, T1, RegSet()); + + __ ld_d(RA, SP, 0 * wordSize); + __ addi_d(SP, SP, 4 * wordSize); @@ -48340,6 +48478,9 @@ index 0000000000..7b5c23b8b5 + const Register ckoff = A3; // super_check_offset + const Register ckval = A4; // super_klass + ++ RegSet wb_pre_saved_regs = RegSet::range(A0, A4); ++ RegSet wb_post_saved_regs = RegSet::of(count); ++ + // Registers used as temps (S0, S1, S2, S3 are save-on-entry) + const Register copied_oop = S0; // actual oop copied + const Register count_save = S1; // orig elementscount @@ -48371,12 +48512,7 @@ index 0000000000..7b5c23b8b5 + // Empty array: Nothing to do. + __ beqz(count, L_done); + -+ __ addi_d(SP, SP, -6 * wordSize); -+ __ st_d(S0, SP, 0 * wordSize); -+ __ st_d(S1, SP, 1 * wordSize); -+ __ st_d(S2, SP, 2 * wordSize); -+ __ st_d(S3, SP, 3 * wordSize); -+ __ st_d(S4, SP, 4 * wordSize); ++ __ push(RegSet::of(S0, S1, S2, S3, RA)); + +#ifdef ASSERT + __ block_comment("assert consistent ckoff/ckval"); @@ -48397,20 +48533,8 @@ index 0000000000..7b5c23b8b5 + decorators |= IS_DEST_UNINITIALIZED; + } + -+ __ move(S0, A0); -+ __ move(S1, A1); -+ __ move(S2, A2); -+ __ move(S3, A3); -+ __ move(S4, A4); -+ + BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler(); -+ bs->arraycopy_prologue(_masm, decorators, is_oop, to, count); -+ -+ __ move(A0, S0); -+ __ move(A1, S1); -+ __ move(A2, S2); -+ __ move(A3, S3); -+ __ move(A4, S4); ++ bs->arraycopy_prologue(_masm, decorators, is_oop, to, count, wb_pre_saved_regs); + + // save the original count + __ move(count_save, count); @@ -48455,19 +48579,10 @@ index 0000000000..7b5c23b8b5 + + __ bind(L_do_card_marks); + -+ __ move(S0, count); -+ -+ bs->arraycopy_epilogue(_masm, decorators, is_oop, start_to, count_save, tmp2); -+ -+ __ move(count, S0); ++ bs->arraycopy_epilogue(_masm, decorators, is_oop, start_to, count_save, tmp2, wb_post_saved_regs); + + __ bind(L_done_pop); -+ __ ld_d(S0, SP, 0 * wordSize); -+ __ ld_d(S1, SP, 1 * wordSize); -+ __ ld_d(S2, SP, 2 * wordSize); -+ __ ld_d(S3, SP, 3 * wordSize); -+ __ ld_d(S4, SP, 4 * wordSize); -+ __ addi_d(SP, SP, 6 * wordSize); ++ __ pop(RegSet::of(S0, S1, S2, S3, RA)); + +#ifndef PRODUCT + __ li(SCR2, (address)&SharedRuntime::_checkcast_array_copy_ctr); @@ -51047,10 +51162,10 @@ index 0000000000..1a6ea3bcde +}; diff --git a/src/hotspot/cpu/loongarch/templateInterpreterGenerator_loongarch.cpp b/src/hotspot/cpu/loongarch/templateInterpreterGenerator_loongarch.cpp new file mode 100644 -index 0000000000..ee2e522466 +index 0000000000..be1d28d4b8 --- /dev/null +++ b/src/hotspot/cpu/loongarch/templateInterpreterGenerator_loongarch.cpp -@@ -0,0 +1,2224 @@ +@@ -0,0 +1,2269 @@ +/* + * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. @@ -51078,6 +51193,7 @@ index 0000000000..ee2e522466 + +#include "precompiled.hpp" +#include "asm/macroAssembler.hpp" ++#include "gc/shared/barrierSetAssembler.hpp" +#include "interpreter/bytecodeHistogram.hpp" +#include "interpreter/interpreter.hpp" +#include "interpreter/interpreterRuntime.hpp" @@ -52061,10 +52177,54 @@ index 0000000000..ee2e522466 + +// Method entry for java.lang.ref.Reference.get. +address TemplateInterpreterGenerator::generate_Reference_get_entry(void) { ++ // Code: _aload_0, _getfield, _areturn ++ // parameter size = 1 ++ // ++ // The code that gets generated by this routine is split into 2 parts: ++ // 1. The "intrinsified" code for G1 (or any SATB based GC), ++ // 2. The slow path - which is an expansion of the regular method entry. ++ // ++ // Notes:- ++ // * In the G1 code we do not check whether we need to block for ++ // a safepoint. If G1 is enabled then we must execute the specialized ++ // code for Reference.get (except when the Reference object is null) ++ // so that we can log the value in the referent field with an SATB ++ // update buffer. ++ // If the code for the getfield template is modified so that the ++ // G1 pre-barrier code is executed when the current method is ++ // Reference.get() then going through the normal method entry ++ // will be fine. ++ // * The G1 code can, however, check the receiver object (the instance ++ // of java.lang.Reference) and jump to the slow path if null. If the ++ // Reference object is null then we obviously cannot fetch the referent ++ // and so we don't need to call the G1 pre-barrier. Thus we can use the ++ // regular method entry code to generate the NPE. ++ // ++ // This code is based on generate_accessor_entry. ++ // ++ // Rmethod: Method* ++ // Rsender: senderSP must preserve for slow path, set SP to it on fast path ++ // RA is live. It must be saved around calls. + + address entry = __ pc(); ++ ++ const int referent_offset = java_lang_ref_Reference::referent_offset; ++ + Label slow_path; -+ __ b(slow_path); ++ const Register local_0 = A0; ++ // Check if local 0 != NULL ++ // If the receiver is null then it is OK to jump to the slow path. ++ __ ld_d(local_0, Address(SP, 0)); ++ __ beqz(local_0, slow_path); ++ ++ // Load the value of the referent field. ++ const Address field_address(local_0, referent_offset); ++ BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler(); ++ bs->load_at(_masm, IN_HEAP | ON_WEAK_OOP_REF, T_OBJECT, local_0, field_address, /*tmp1*/ T4, /*tmp2*/ noreg); ++ ++ // areturn ++ __ move(SP, Rsender); ++ __ jr(RA); + + // generate a vanilla interpreter entry as the slow path + __ bind(slow_path); @@ -53326,10 +53486,10 @@ index 0000000000..ddb38faf44 +#endif // CPU_LOONGARCH_TEMPLATETABLE_LOONGARCH_64_HPP diff --git a/src/hotspot/cpu/loongarch/templateTable_loongarch_64.cpp b/src/hotspot/cpu/loongarch/templateTable_loongarch_64.cpp new file mode 100644 -index 0000000000..8ad7c5f76e +index 0000000000..4f1d226a1a --- /dev/null +++ b/src/hotspot/cpu/loongarch/templateTable_loongarch_64.cpp -@@ -0,0 +1,4147 @@ +@@ -0,0 +1,4115 @@ +/* + * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. @@ -55574,38 +55734,6 @@ index 0000000000..8ad7c5f76e + __ jr(T4); +} + -+// ---------------------------------------------------------------------------- -+// Volatile variables demand their effects be made known to all CPU's -+// in order. Store buffers on most chips allow reads & writes to -+// reorder; the JMM's ReadAfterWrite.java test fails in -Xint mode -+// without some kind of memory barrier (i.e., it's not sufficient that -+// the interpreter does not reorder volatile references, the hardware -+// also must not reorder them). -+// -+// According to the new Java Memory Model (JMM): -+// (1) All volatiles are serialized wrt to each other. ALSO reads & -+// writes act as aquire & release, so: -+// (2) A read cannot let unrelated NON-volatile memory refs that -+// happen after the read float up to before the read. It's OK for -+// non-volatile memory refs that happen before the volatile read to -+// float down below it. -+// (3) Similar a volatile write cannot let unrelated NON-volatile -+// memory refs that happen BEFORE the write float down to after the -+// write. It's OK for non-volatile memory refs that happen after the -+// volatile write to float up before it. -+// -+// We only put in barriers around volatile refs (they are expensive), -+// not _between_ memory refs (that would require us to track the -+// flavor of the previous memory refs). Requirements (2) and (3) -+// require some barriers before volatile stores and after volatile -+// loads. These nearly cover requirement (1) but miss the -+// volatile-store-volatile-load case. This final case is placed after -+// volatile-stores although it could just as well go before -+// volatile-loads. -+void TemplateTable::volatile_barrier() { -+ if(os::is_MP()) __ membar(__ StoreLoad); -+} -+ +// we dont shift left 2 bits in get_cache_and_index_at_bcp +// for we always need shift the index we use it. the ConstantPoolCacheEntry +// is 16-byte long, index is the index in @@ -55801,7 +55929,7 @@ index 0000000000..8ad7c5f76e + + Label notVolatile; + __ beq(scratch, R0, notVolatile); -+ volatile_barrier(); ++ __ membar(MacroAssembler::AnyAny); + __ bind(notVolatile); + } + @@ -55947,7 +56075,7 @@ index 0000000000..8ad7c5f76e + { + Label notVolatile; + __ beq(scratch, R0, notVolatile); -+ volatile_barrier(); ++ __ membar(Assembler::Membar_mask_bits(__ LoadLoad | __ LoadStore)); + __ bind(notVolatile); + } +} @@ -56063,7 +56191,7 @@ index 0000000000..8ad7c5f76e + + Label notVolatile; + __ beq(scratch, R0, notVolatile); -+ volatile_barrier(); ++ __ membar(Assembler::Membar_mask_bits(__ StoreStore | __ LoadStore)); + __ bind(notVolatile); + } + @@ -56235,7 +56363,7 @@ index 0000000000..8ad7c5f76e + { + Label notVolatile; + __ beq(scratch, R0, notVolatile); -+ volatile_barrier(); ++ __ membar(Assembler::Membar_mask_bits(__ StoreLoad | __ StoreStore)); + __ bind(notVolatile); + } +} @@ -56344,7 +56472,7 @@ index 0000000000..8ad7c5f76e + + Label notVolatile; + __ beq(scratch, R0, notVolatile); -+ volatile_barrier(); ++ __ membar(Assembler::Membar_mask_bits(__ StoreStore | __ LoadStore)); + __ bind(notVolatile); + } + @@ -56393,7 +56521,7 @@ index 0000000000..8ad7c5f76e + { + Label notVolatile; + __ beq(scratch, R0, notVolatile); -+ volatile_barrier(); ++ __ membar(Assembler::Membar_mask_bits(__ StoreLoad | __ StoreStore)); + __ bind(notVolatile); + } +} @@ -56444,7 +56572,7 @@ index 0000000000..8ad7c5f76e + + Label notVolatile; + __ beq(scratch, R0, notVolatile); -+ volatile_barrier(); ++ __ membar(MacroAssembler::AnyAny); + __ bind(notVolatile); + } + @@ -56488,7 +56616,7 @@ index 0000000000..8ad7c5f76e + { + Label notVolatile; + __ beq(scratch, R0, notVolatile); -+ volatile_barrier(); ++ __ membar(Assembler::Membar_mask_bits(__ LoadLoad | __ LoadStore)); + __ bind(notVolatile); + } +} @@ -56518,7 +56646,7 @@ index 0000000000..8ad7c5f76e + + Label notVolatile; + __ beq(scratch, R0, notVolatile); -+ volatile_barrier(); ++ __ membar(MacroAssembler::AnyAny); + __ bind(notVolatile); + } + @@ -56543,7 +56671,7 @@ index 0000000000..8ad7c5f76e + { + Label notVolatile; + __ beq(scratch, R0, notVolatile); -+ volatile_barrier(); ++ __ membar(Assembler::Membar_mask_bits(__ LoadLoad | __ LoadStore)); + __ bind(notVolatile); + } +} @@ -57697,10 +57825,10 @@ index 0000000000..1a93123134 +#endif // CPU_LOONGARCH_VM_VERSION_EXT_LOONGARCH_HPP diff --git a/src/hotspot/cpu/loongarch/vm_version_loongarch.cpp b/src/hotspot/cpu/loongarch/vm_version_loongarch.cpp new file mode 100644 -index 0000000000..b954fa3e1a +index 0000000000..0a9b55d17e --- /dev/null +++ b/src/hotspot/cpu/loongarch/vm_version_loongarch.cpp -@@ -0,0 +1,414 @@ +@@ -0,0 +1,397 @@ +/* + * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2015, 2021, Loongson Technology. All rights reserved. @@ -57739,7 +57867,6 @@ index 0000000000..b954fa3e1a + +#define T5 RT5 + -+int VM_Version::_cpuFeatures; +const char* VM_Version::_features_str = ""; +VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, }; +bool VM_Version::_cpu_info_is_initialized = false; @@ -57833,27 +57960,9 @@ index 0000000000..b954fa3e1a + } else if (_cpuid_info.cpucfg_info_id1.bits.ARCH == 0b10 ) { + result |= CPU_LA64; + } -+ if (_cpuid_info.cpucfg_info_id1.bits.UAL != 0) -+ result |= CPU_UAL; + + if (_cpuid_info.cpucfg_info_id2.bits.FP_CFG != 0) + result |= CPU_FP; -+ if (_cpuid_info.cpucfg_info_id2.bits.LSX != 0) -+ result |= CPU_LSX; -+ if (_cpuid_info.cpucfg_info_id2.bits.LASX != 0) -+ result |= CPU_LASX; -+ if (_cpuid_info.cpucfg_info_id2.bits.COMPLEX != 0) -+ result |= CPU_COMPLEX; -+ if (_cpuid_info.cpucfg_info_id2.bits.CRYPTO != 0) -+ result |= CPU_CRYPTO; -+ if (_cpuid_info.cpucfg_info_id2.bits.LBT_X86 != 0) -+ result |= CPU_LBT_X86; -+ if (_cpuid_info.cpucfg_info_id2.bits.LBT_ARM != 0) -+ result |= CPU_LBT_ARM; -+ if (_cpuid_info.cpucfg_info_id2.bits.LBT_MIPS != 0) -+ result |= CPU_LBT_MIPS; -+ if (_cpuid_info.cpucfg_info_id2.bits.LAM != 0) -+ result |= CPU_LAM; + + if (_cpuid_info.cpucfg_info_id3.bits.CCDMA != 0) + result |= CPU_CCDMA; @@ -57873,8 +57982,10 @@ index 0000000000..b954fa3e1a + + clean_cpuFeatures(); + ++ get_os_cpu_info(); ++ + get_cpu_info_stub(&_cpuid_info); -+ _cpuFeatures = get_feature_flags_by_cpucfg(); ++ _features |= get_feature_flags_by_cpucfg(); + + _supports_cx8 = true; + @@ -58117,13 +58228,13 @@ index 0000000000..b954fa3e1a +} diff --git a/src/hotspot/cpu/loongarch/vm_version_loongarch.hpp b/src/hotspot/cpu/loongarch/vm_version_loongarch.hpp new file mode 100644 -index 0000000000..8b5bc4a4c8 +index 0000000000..00b8e608a1 --- /dev/null +++ b/src/hotspot/cpu/loongarch/vm_version_loongarch.hpp @@ -0,0 +1,292 @@ +/* + * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2021, Loongson Technology. All rights reserved. ++ * Copyright (c) 2015, 2023, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -58321,30 +58432,30 @@ index 0000000000..8b5bc4a4c8 +protected: + + enum { -+ CPU_LA32 = (1 << 1), -+ CPU_LA64 = (1 << 2), -+ CPU_LLEXC = (1 << 3), -+ CPU_SCDLY = (1 << 4), -+ CPU_LLDBAR = (1 << 5), -+ CPU_LBT_X86 = (1 << 6), -+ CPU_LBT_ARM = (1 << 7), -+ CPU_LBT_MIPS = (1 << 8), -+ CPU_CCDMA = (1 << 9), -+ CPU_COMPLEX = (1 << 10), -+ CPU_FP = (1 << 11), -+ CPU_CRYPTO = (1 << 14), -+ CPU_LSX = (1 << 15), -+ CPU_LASX = (1 << 17), -+ CPU_LAM = (1 << 21), -+ CPU_LLSYNC = (1 << 23), -+ CPU_TGTSYNC = (1 << 24), -+ CPU_ULSYNC = (1 << 25), -+ CPU_UAL = (1 << 26), ++ CPU_LAM = (1 << 1), ++ CPU_UAL = (1 << 2), ++ CPU_LSX = (1 << 4), ++ CPU_LASX = (1 << 5), ++ CPU_COMPLEX = (1 << 7), ++ CPU_CRYPTO = (1 << 8), ++ CPU_LBT_X86 = (1 << 10), ++ CPU_LBT_ARM = (1 << 11), ++ CPU_LBT_MIPS = (1 << 12), ++ // flags above must follow Linux HWCAP ++ CPU_LA32 = (1 << 13), ++ CPU_LA64 = (1 << 14), ++ CPU_FP = (1 << 15), ++ CPU_LLEXC = (1 << 16), ++ CPU_SCDLY = (1 << 17), ++ CPU_LLDBAR = (1 << 18), ++ CPU_CCDMA = (1 << 19), ++ CPU_LLSYNC = (1 << 20), ++ CPU_TGTSYNC = (1 << 21), ++ CPU_ULSYNC = (1 << 22), + + //////////////////////add some other feature here////////////////// + } cpuFeatureFlags; + -+ static int _cpuFeatures; + static const char* _features_str; + static bool _cpu_info_is_initialized; + @@ -58367,8 +58478,8 @@ index 0000000000..8b5bc4a4c8 + static CpuidInfo _cpuid_info; + + static uint32_t get_feature_flags_by_cpucfg(); -+ static int get_feature_flags_by_cpuinfo(int features); + static void get_processor_features(); ++ static void get_os_cpu_info(); + +public: + // Offsets for cpuid asm stub @@ -58385,26 +58496,26 @@ index 0000000000..8b5bc4a4c8 + static ByteSize Loongson_Cpucfg_id13_offset() { return byte_offset_of(CpuidInfo, cpucfg_info_id13); } + static ByteSize Loongson_Cpucfg_id14_offset() { return byte_offset_of(CpuidInfo, cpucfg_info_id14); } + -+ static void clean_cpuFeatures() { _cpuFeatures = 0; } ++ static void clean_cpuFeatures() { _features = 0; } + + // Initialization + static void initialize(); + + static bool cpu_info_is_initialized() { return _cpu_info_is_initialized; } + -+ static bool is_la32() { return _cpuFeatures & CPU_LA32; } -+ static bool is_la64() { return _cpuFeatures & CPU_LA64; } -+ static bool supports_crypto() { return _cpuFeatures & CPU_CRYPTO; } -+ static bool supports_lsx() { return _cpuFeatures & CPU_LSX; } -+ static bool supports_lasx() { return _cpuFeatures & CPU_LASX; } -+ static bool supports_lam() { return _cpuFeatures & CPU_LAM; } -+ static bool supports_llexc() { return _cpuFeatures & CPU_LLEXC; } -+ static bool supports_scdly() { return _cpuFeatures & CPU_SCDLY; } -+ static bool supports_lldbar() { return _cpuFeatures & CPU_LLDBAR; } -+ static bool supports_ual() { return _cpuFeatures & CPU_UAL; } -+ static bool supports_lbt_x86() { return _cpuFeatures & CPU_LBT_X86; } -+ static bool supports_lbt_arm() { return _cpuFeatures & CPU_LBT_ARM; } -+ static bool supports_lbt_mips() { return _cpuFeatures & CPU_LBT_MIPS; } ++ static bool is_la32() { return _features & CPU_LA32; } ++ static bool is_la64() { return _features & CPU_LA64; } ++ static bool supports_crypto() { return _features & CPU_CRYPTO; } ++ static bool supports_lsx() { return _features & CPU_LSX; } ++ static bool supports_lasx() { return _features & CPU_LASX; } ++ static bool supports_lam() { return _features & CPU_LAM; } ++ static bool supports_llexc() { return _features & CPU_LLEXC; } ++ static bool supports_scdly() { return _features & CPU_SCDLY; } ++ static bool supports_lldbar() { return _features & CPU_LLDBAR; } ++ static bool supports_ual() { return _features & CPU_UAL; } ++ static bool supports_lbt_x86() { return _features & CPU_LBT_X86; } ++ static bool supports_lbt_arm() { return _features & CPU_LBT_ARM; } ++ static bool supports_lbt_mips() { return _features & CPU_LBT_MIPS; } + static bool needs_llsync() { return !supports_lldbar(); } + static bool needs_tgtsync() { return 1; } + static bool needs_ulsync() { return 1; } @@ -59049,10 +59160,10 @@ index 0000000000..73f021c9b7 + diff --git a/src/hotspot/cpu/mips/assembler_mips.cpp b/src/hotspot/cpu/mips/assembler_mips.cpp new file mode 100644 -index 0000000000..5f02077d0e +index 0000000000..c8c7a5d4df --- /dev/null +++ b/src/hotspot/cpu/mips/assembler_mips.cpp -@@ -0,0 +1,733 @@ +@@ -0,0 +1,759 @@ +/* + * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. @@ -59092,6 +59203,9 @@ index 0000000000..5f02077d0e +#include "runtime/sharedRuntime.hpp" +#include "runtime/stubRoutines.hpp" +#include "utilities/macros.hpp" ++#ifndef PRODUCT ++#include "compiler/disassembler.hpp" ++#endif + +#ifdef PRODUCT +#define BLOCK_COMMENT(str) /* nothing */ @@ -59786,12 +59900,35 @@ index 0000000000..5f02077d0e + emit_long((jal_op<<26) | dest); + has_delay_slot(); +} ++ ++void Assembler::emit_long(int x) { // shadows AbstractAssembler::emit_long ++ check_delay(); ++ AbstractAssembler::emit_int32(x); ++} ++ ++inline void Assembler::emit_data(int x) { emit_long(x); } ++inline void Assembler::emit_data(int x, relocInfo::relocType rtype) { ++ relocate(rtype); ++ emit_long(x); ++} ++ ++inline void Assembler::emit_data(int x, RelocationHolder const& rspec) { ++ relocate(rspec); ++ emit_long(x); ++} ++ ++inline void Assembler::check_delay() { ++#ifdef CHECK_DELAY ++ guarantee(delay_state != at_delay_slot, "must say delayed() when filling delay slot"); ++ delay_state = no_delay; ++#endif ++} diff --git a/src/hotspot/cpu/mips/assembler_mips.hpp b/src/hotspot/cpu/mips/assembler_mips.hpp new file mode 100644 -index 0000000000..7ef33cf592 +index 0000000000..102a7ba52f --- /dev/null +++ b/src/hotspot/cpu/mips/assembler_mips.hpp -@@ -0,0 +1,1792 @@ +@@ -0,0 +1,1789 @@ +/* + * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. @@ -60761,11 +60898,11 @@ index 0000000000..7ef33cf592 + AbstractAssembler::flush(); + } + -+ inline void emit_long(int); // shadows AbstractAssembler::emit_long -+ inline void emit_data(int x) { emit_long(x); } -+ inline void emit_data(int, RelocationHolder const&); -+ inline void emit_data(int, relocInfo::relocType rtype); -+ inline void check_delay(); ++ void emit_long(int); // shadows AbstractAssembler::emit_long ++ void emit_data(int); ++ void emit_data(int, RelocationHolder const&); ++ void emit_data(int, relocInfo::relocType rtype); ++ void check_delay(); + + + // Generic instructions @@ -61580,16 +61717,13 @@ index 0000000000..7ef33cf592 + static address locate_next_instruction(address inst); +}; + -+ -+#include "assembler_mips.inline.hpp" -+ +#endif // CPU_MIPS_VM_ASSEMBLER_MIPS_HPP diff --git a/src/hotspot/cpu/mips/assembler_mips.inline.hpp b/src/hotspot/cpu/mips/assembler_mips.inline.hpp new file mode 100644 -index 0000000000..21c8a76156 +index 0000000000..f35a06fc4e --- /dev/null +++ b/src/hotspot/cpu/mips/assembler_mips.inline.hpp -@@ -0,0 +1,60 @@ +@@ -0,0 +1,33 @@ +/* + * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2015, 2018, Loongson Technology. All rights reserved. @@ -61621,33 +61755,6 @@ index 0000000000..21c8a76156 +#include "asm/assembler.inline.hpp" +#include "asm/codeBuffer.hpp" +#include "code/codeCache.hpp" -+#ifndef PRODUCT -+#include "compiler/disassembler.hpp" -+#endif -+ -+ -+ -+inline void Assembler::check_delay() { -+# ifdef CHECK_DELAY -+ guarantee(delay_state != at_delay_slot, "must say delayed() when filling delay slot"); -+ delay_state = no_delay; -+# endif -+} -+ -+inline void Assembler::emit_long(int x) { -+ check_delay(); -+ AbstractAssembler::emit_int32(x); -+} -+ -+inline void Assembler::emit_data(int x, relocInfo::relocType rtype) { -+ relocate(rtype); -+ emit_long(x); -+} -+ -+inline void Assembler::emit_data(int x, RelocationHolder const& rspec) { -+ relocate(rspec); -+ emit_long(x); -+} + +#endif // CPU_MIPS_VM_ASSEMBLER_MIPS_INLINE_HPP diff --git a/src/hotspot/cpu/mips/bytes_mips.hpp b/src/hotspot/cpu/mips/bytes_mips.hpp @@ -67809,10 +67916,10 @@ index 0000000000..dccdf6a019 +#endif // CPU_MIPS_VM_JAVAFRAMEANCHOR_MIPS_HPP diff --git a/src/hotspot/cpu/mips/jniFastGetField_mips_64.cpp b/src/hotspot/cpu/mips/jniFastGetField_mips_64.cpp new file mode 100644 -index 0000000000..46c8889f99 +index 0000000000..bba5b7eee8 --- /dev/null +++ b/src/hotspot/cpu/mips/jniFastGetField_mips_64.cpp -@@ -0,0 +1,166 @@ +@@ -0,0 +1,167 @@ +/* + * Copyright (c) 2004, 2010, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2015, 2021, Loongson Technology. All rights reserved. @@ -67840,6 +67947,7 @@ index 0000000000..46c8889f99 + +#include "precompiled.hpp" +#include "asm/macroAssembler.hpp" ++#include "code/codeBlob.hpp" +#include "gc/shared/barrierSet.hpp" +#include "gc/shared/barrierSetAssembler.hpp" +#include "memory/resourceArea.hpp" @@ -86188,10 +86296,10 @@ index 0000000000..b4acbd83f7 + diff --git a/src/hotspot/cpu/mips/nativeInst_mips.cpp b/src/hotspot/cpu/mips/nativeInst_mips.cpp new file mode 100644 -index 0000000000..514298bd8b +index 0000000000..96a147eaa5 --- /dev/null +++ b/src/hotspot/cpu/mips/nativeInst_mips.cpp -@@ -0,0 +1,1820 @@ +@@ -0,0 +1,1821 @@ +/* + * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. @@ -86220,6 +86328,7 @@ index 0000000000..514298bd8b +#include "precompiled.hpp" +#include "asm/macroAssembler.hpp" +#include "compiler/disassembler.hpp" ++#include "code/codeCache.hpp" +#include "code/compiledIC.hpp" +#include "memory/resourceArea.hpp" +#include "nativeInst_mips.hpp" @@ -104676,7 +104785,7 @@ index 3687754e71..791e4ed43f 100644 void generate_c1_load_barrier_stub(LIR_Assembler* ce, ZLoadBarrierStubC1* stub) const; diff --git a/src/hotspot/os/linux/os_linux.cpp b/src/hotspot/os/linux/os_linux.cpp -index f89a8c360b..68a2a3e4fa 100644 +index 74945999e7..2b8ac3dd2a 100644 --- a/src/hotspot/os/linux/os_linux.cpp +++ b/src/hotspot/os/linux/os_linux.cpp @@ -23,6 +23,12 @@ @@ -104692,7 +104801,7 @@ index f89a8c360b..68a2a3e4fa 100644 // no precompiled headers #include "jvm.h" #include "classfile/classLoader.hpp" -@@ -3977,6 +3983,8 @@ size_t os::Linux::find_large_page_size() { +@@ -3966,6 +3972,8 @@ size_t os::Linux::find_large_page_size() { IA64_ONLY(256 * M) PPC_ONLY(4 * M) S390_ONLY(1 * M) @@ -104733,13 +104842,13 @@ index 0000000000..30719a0340 + */ diff --git a/src/hotspot/os_cpu/linux_loongarch/atomic_linux_loongarch.hpp b/src/hotspot/os_cpu/linux_loongarch/atomic_linux_loongarch.hpp new file mode 100644 -index 0000000000..86f8c963f5 +index 0000000000..8403e7838a --- /dev/null +++ b/src/hotspot/os_cpu/linux_loongarch/atomic_linux_loongarch.hpp @@ -0,0 +1,160 @@ +/* + * Copyright (c) 1999, 2013, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2021, Loongson Technology. All rights reserved. ++ * Copyright (c) 2015, 2023, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -104858,7 +104967,7 @@ index 0000000000..86f8c963f5 + " sc.w %[__cmp], %[__dest] \n\t" + " beqz %[__cmp], 1b \n\t" + "2: \n\t" -+ " dbar 0 \n\t" ++ " dbar 0x700 \n\t" + + : [__prev] "=&r" (__prev), [__cmp] "=&r" (__cmp) + : [__dest] "ZC" (*(volatile jint*)dest), [__old] "r" (compare_value), [__new] "r" (exchange_value) @@ -104886,7 +104995,7 @@ index 0000000000..86f8c963f5 + " sc.d %[__cmp], %[__dest] \n\t" + " beqz %[__cmp], 1b \n\t" + "2: \n\t" -+ " dbar 0 \n\t" ++ " dbar 0x700 \n\t" + + : [__prev] "=&r" (__prev), [__cmp] "=&r" (__cmp) + : [__dest] "ZC" (*(volatile jlong*)dest), [__old] "r" (compare_value), [__new] "r" (exchange_value) @@ -105153,7 +105262,7 @@ index 0000000000..ebd73af0c5 + diff --git a/src/hotspot/os_cpu/linux_loongarch/orderAccess_linux_loongarch.hpp b/src/hotspot/os_cpu/linux_loongarch/orderAccess_linux_loongarch.hpp new file mode 100644 -index 0000000000..295d20e19e +index 0000000000..5429a1055a --- /dev/null +++ b/src/hotspot/os_cpu/linux_loongarch/orderAccess_linux_loongarch.hpp @@ -0,0 +1,51 @@ @@ -105190,19 +105299,19 @@ index 0000000000..295d20e19e +// Included in orderAccess.hpp header file. + +// Implementation of class OrderAccess. -+#define inlasm_sync() if (os::is_ActiveCoresMP()) \ ++#define inlasm_sync(v) if (os::is_ActiveCoresMP()) \ + __asm__ __volatile__ ("nop" : : : "memory"); \ + else \ -+ __asm__ __volatile__ ("dbar 0" : : : "memory"); ++ __asm__ __volatile__ ("dbar %0" : :"K"(v) : "memory"); + -+inline void OrderAccess::loadload() { inlasm_sync(); } -+inline void OrderAccess::storestore() { inlasm_sync(); } -+inline void OrderAccess::loadstore() { inlasm_sync(); } -+inline void OrderAccess::storeload() { inlasm_sync(); } ++inline void OrderAccess::loadload() { inlasm_sync(0x15); } ++inline void OrderAccess::storestore() { inlasm_sync(0x1a); } ++inline void OrderAccess::loadstore() { inlasm_sync(0x16); } ++inline void OrderAccess::storeload() { inlasm_sync(0x19); } + -+inline void OrderAccess::acquire() { inlasm_sync(); } -+inline void OrderAccess::release() { inlasm_sync(); } -+inline void OrderAccess::fence() { inlasm_sync(); } ++inline void OrderAccess::acquire() { inlasm_sync(0x14); } ++inline void OrderAccess::release() { inlasm_sync(0x12); } ++inline void OrderAccess::fence() { inlasm_sync(0x10); } + + +#undef inlasm_sync @@ -106285,6 +106394,105 @@ index 0000000000..a39cb79bb1 +#define VM_LONG_CONSTANTS_OS_CPU(declare_constant, declare_preprocessor_constant, declare_c1_constant, declare_c2_constant, declare_c2_preprocessor_constant) + +#endif // OS_CPU_LINUX_LOONGARCH_VMSTRUCTS_LINUX_LOONGARCH_HPP +diff --git a/src/hotspot/os_cpu/linux_loongarch/vm_version_linux_loongarch.cpp b/src/hotspot/os_cpu/linux_loongarch/vm_version_linux_loongarch.cpp +new file mode 100644 +index 0000000000..edc148ef91 +--- /dev/null ++++ b/src/hotspot/os_cpu/linux_loongarch/vm_version_linux_loongarch.cpp +@@ -0,0 +1,93 @@ ++/* ++ * Copyright (c) 2006, 2021, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2015, 2023, Loongson Technology. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#include "precompiled.hpp" ++#include "runtime/os.hpp" ++#include "runtime/vm_version.hpp" ++ ++#include ++#include ++ ++#ifndef HWCAP_LOONGARCH_LAM ++#define HWCAP_LOONGARCH_LAM (1 << 1) ++#endif ++ ++#ifndef HWCAP_LOONGARCH_UAL ++#define HWCAP_LOONGARCH_UAL (1 << 2) ++#endif ++ ++#ifndef HWCAP_LOONGARCH_LSX ++#define HWCAP_LOONGARCH_LSX (1 << 4) ++#endif ++ ++#ifndef HWCAP_LOONGARCH_LASX ++#define HWCAP_LOONGARCH_LASX (1 << 5) ++#endif ++ ++#ifndef HWCAP_LOONGARCH_COMPLEX ++#define HWCAP_LOONGARCH_COMPLEX (1 << 7) ++#endif ++ ++#ifndef HWCAP_LOONGARCH_CRYPTO ++#define HWCAP_LOONGARCH_CRYPTO (1 << 8) ++#endif ++ ++#ifndef HWCAP_LOONGARCH_LBT_X86 ++#define HWCAP_LOONGARCH_LBT_X86 (1 << 10) ++#endif ++ ++#ifndef HWCAP_LOONGARCH_LBT_ARM ++#define HWCAP_LOONGARCH_LBT_ARM (1 << 11) ++#endif ++ ++#ifndef HWCAP_LOONGARCH_LBT_MIPS ++#define HWCAP_LOONGARCH_LBT_MIPS (1 << 12) ++#endif ++ ++void VM_Version::get_os_cpu_info() { ++ ++ uint64_t auxv = getauxval(AT_HWCAP); ++ ++ STATIC_ASSERT(CPU_LAM == HWCAP_LOONGARCH_LAM); ++ STATIC_ASSERT(CPU_UAL == HWCAP_LOONGARCH_UAL); ++ STATIC_ASSERT(CPU_LSX == HWCAP_LOONGARCH_LSX); ++ STATIC_ASSERT(CPU_LASX == HWCAP_LOONGARCH_LASX); ++ STATIC_ASSERT(CPU_COMPLEX == HWCAP_LOONGARCH_COMPLEX); ++ STATIC_ASSERT(CPU_CRYPTO == HWCAP_LOONGARCH_CRYPTO); ++ STATIC_ASSERT(CPU_LBT_X86 == HWCAP_LOONGARCH_LBT_X86); ++ STATIC_ASSERT(CPU_LBT_ARM == HWCAP_LOONGARCH_LBT_ARM); ++ STATIC_ASSERT(CPU_LBT_MIPS == HWCAP_LOONGARCH_LBT_MIPS); ++ ++ _features = auxv & ( ++ HWCAP_LOONGARCH_LAM | ++ HWCAP_LOONGARCH_UAL | ++ HWCAP_LOONGARCH_LSX | ++ HWCAP_LOONGARCH_LASX | ++ HWCAP_LOONGARCH_COMPLEX | ++ HWCAP_LOONGARCH_CRYPTO | ++ HWCAP_LOONGARCH_LBT_X86 | ++ HWCAP_LOONGARCH_LBT_ARM | ++ HWCAP_LOONGARCH_LBT_MIPS); ++} diff --git a/src/hotspot/os_cpu/linux_mips/assembler_linux_mips.cpp b/src/hotspot/os_cpu/linux_mips/assembler_linux_mips.cpp new file mode 100644 index 0000000000..30719a0340 @@ -116376,7 +116584,7 @@ index 7990c49a1f..025048c6b0 100644 } } diff --git a/test/jdk/sun/security/pkcs11/PKCS11Test.java b/test/jdk/sun/security/pkcs11/PKCS11Test.java -index 7ae0b68401..19689722d2 100644 +index 5d4ee095f7..de622b128b 100644 --- a/test/jdk/sun/security/pkcs11/PKCS11Test.java +++ b/test/jdk/sun/security/pkcs11/PKCS11Test.java @@ -21,6 +21,12 @@ @@ -116403,7 +116611,7 @@ index 7ae0b68401..19689722d2 100644 osMap.put("Windows-x86-32", new String[] {}); osMap.put("Windows-amd64-64", new String[] {}); diff --git a/test/lib/jdk/test/lib/Platform.java b/test/lib/jdk/test/lib/Platform.java -index 739c351806..0ade89fff1 100644 +index f4ee0546c7..a600d15b61 100644 --- a/test/lib/jdk/test/lib/Platform.java +++ b/test/lib/jdk/test/lib/Platform.java @@ -21,6 +21,12 @@ @@ -116419,7 +116627,7 @@ index 739c351806..0ade89fff1 100644 package jdk.test.lib; import java.io.FileNotFoundException; -@@ -225,6 +231,14 @@ public class Platform { +@@ -226,6 +232,14 @@ public class Platform { return isArch("(i386)|(x86(?!_64))"); } diff --git a/java-11-openjdk.spec b/java-11-openjdk.spec index f33da502ed2eeb8f9a2d6f80ca31eefdcb23a47e..92fbb2da48b8d2e5bc5dac1d342682180b4faa81 100644 --- a/java-11-openjdk.spec +++ b/java-11-openjdk.spec @@ -1,4 +1,4 @@ -%define anolis_release .0.1 +%define anolis_release .0.2 # RPM conditionals so as to be able to dynamically produce # slowdebug/release builds. See: # http://rpm.org/user_doc/conditional_builds.html @@ -122,7 +122,7 @@ # Set of architectures for which we build slowdebug builds %global debug_arches %{ix86} x86_64 sparcv9 sparc64 %{aarch64} %{power64} s390x loongarch64 # Set of architectures for which we build fastdebug builds -%global fastdebug_arches x86_64 ppc64le aarch64 +%global fastdebug_arches x86_64 ppc64le aarch64 loongarch64 # Set of architectures with a Just-In-Time (JIT) compiler %global jit_arches %{arm} %{aarch64} %{ix86} %{power64} s390x sparcv9 sparc64 x86_64 loongarch64 # Set of architectures which use the Zero assembler port (!jit_arches) @@ -148,7 +148,7 @@ # Set of architectures where we verify backtraces with gdb %global gdb_arches %{jit_arches} %{zero_arches} # Set of architectures for which we have a portable build -%global portable_build_arches %{aarch64} %{ix86} %{power64} s390x x86_64 +%global portable_build_arches %{aarch64} %{ix86} %{power64} s390x x86_64 loongarch64 # By default, we build a slowdebug build during main build on JIT architectures %if %{with slowdebug} @@ -385,8 +385,8 @@ %global buildver 7 %global rpmrelease 4 # Settings used by the portable build -%global portablerelease 2 -%global portablesuffix el8 +%global portablerelease 2%{anolis_release} +%global portablesuffix an8 %global portablebuilddir /builddir/build/BUILD #%%global tagsuffix %%{nil} @@ -2528,6 +2528,10 @@ end %endif %changelog +* Fri Aug 04 2023 Pan Xuefeng - 1:11.0.19.0.7-4.0.2 +- Update LoongArch src to jdk-11.0.19+7-ls-2 +- Update portable pkg dist + * Sat Jul 01 2023 Liwei Ge - 1:11.0.19.0.7-4.0.1 - LoongArch64 init support (aoqi ) - Adjust loongarch64 patch (geliwei@openanolis.org)