diff --git a/0015-cpu-Add-new-Chengdu-CPU-model.patch b/0015-cpu-Add-new-Chengdu-CPU-model.patch
new file mode 100644
index 0000000000000000000000000000000000000000..51c4168d6f2f310a68c8de6c0af185b1f65579c2
--- /dev/null
+++ b/0015-cpu-Add-new-Chengdu-CPU-model.patch
@@ -0,0 +1,148 @@
+From 4afc98f73a70bd5d7fb1f9815ac86764241374e0 Mon Sep 17 00:00:00 2001
+From: Yanjing Zhou <zhouyanjing@hygon.cn>
+Date: Wed, 28 May 2025 17:05:54 +0800
+Subject: [PATCH] cpu: Add new Chengdu CPU model
+
+Add Hygon Chengdu CPU model to the processor model.
+
+Signed-off-by: Yanjing Zhou <zhouyanjing@hygon.cn>
+---
+ src/cpu_map/index.xml       |   1 +
+ src/cpu_map/meson.build     |   1 +
+ src/cpu_map/x86_Chengdu.xml | 100 ++++++++++++++++++++++++++++++++++++
+ 3 files changed, 102 insertions(+)
+ create mode 100644 src/cpu_map/x86_Chengdu.xml
+
+diff --git a/src/cpu_map/index.xml b/src/cpu_map/index.xml
+index fed5fe3..af47897 100644
+--- a/src/cpu_map/index.xml
++++ b/src/cpu_map/index.xml
+@@ -75,6 +75,7 @@
+     <!-- Hygon CPU models -->
+     <include filename='x86_Dhyana.xml'/>
+     <include filename='x86_Dharma.xml'/>
++    <include filename='x86_Chengdu.xml'/>
+   </arch>
+
+   <arch name='ppc64'>
+diff --git a/src/cpu_map/meson.build b/src/cpu_map/meson.build
+index 98d74bc..fd8d833 100644
+--- a/src/cpu_map/meson.build
++++ b/src/cpu_map/meson.build
+@@ -36,6 +36,7 @@ cpumap_data = [
+   'x86_coreduo.xml',
+   'x86_cpu64-rhel5.xml',
+   'x86_cpu64-rhel6.xml',
++  'x86_Chengdu.xml',
+   'x86_Dharma.xml',
+   'x86_Dhyana.xml',
+   'x86_EPYC-IBPB.xml',
+diff --git a/src/cpu_map/x86_Chengdu.xml b/src/cpu_map/x86_Chengdu.xml
+new file mode 100644
+index 0000000..ab6cf26
+--- /dev/null
++++ b/src/cpu_map/x86_Chengdu.xml
+@@ -0,0 +1,100 @@
++<cpus>
++  <model name='Chengdu'>
++    <decode host='on' guest='on'/>
++    <signature family='24' model='7'/>
++    <vendor name='Hygon'/>
++    <feature name='3dnowprefetch'/>
++    <feature name='abm'/>
++    <feature name='adx'/>
++    <feature name='aes'/>
++    <feature name='amd-ssbd'/>
++    <feature name='amd-stibp'/>
++    <feature name='apic'/>
++    <feature name='arat'/>
++    <feature name='avx'/>
++    <feature name='avx2'/>
++    <feature name='avx512-bf16'/>
++    <feature name='avx512-vpopcntdq'/>
++    <feature name='avx512bitalg'/>
++    <feature name='avx512bw'/>
++    <feature name='avx512cd'/>
++    <feature name='avx512dq'/>
++    <feature name='avx512f'/>
++    <feature name='avx512ifma'/>
++    <feature name='avx512vbmi'/>
++    <feature name='avx512vbmi2'/>
++    <feature name='avx512vl'/>
++    <feature name='avx512vnni'/>
++    <feature name='bmi1'/>
++    <feature name='bmi2'/>
++    <feature name='clflush'/>
++    <feature name='clflushopt'/>
++    <feature name='clwb'/>
++    <feature name='clzero'/>
++    <feature name='cmov'/>
++    <feature name='cr8legacy'/>
++    <feature name='cx16'/>
++    <feature name='cx8'/>
++    <feature name='de'/>
++    <feature name='f16c'/>
++    <feature name='fma'/>
++    <feature name='fpu'/>
++    <feature name='fsgsbase'/>
++    <feature name='fxsr'/>
++    <feature name='fxsr_opt'/>
++    <feature name='gfni'/>
++    <feature name='ibpb'/>
++    <feature name='ibrs'/>
++    <feature name='lahf_lm'/>
++    <feature name='lm'/>
++    <feature name='mca'/>
++    <feature name='mce'/>
++    <feature name='misalignsse'/>
++    <feature name='mmx'/>
++    <feature name='mmxext'/>
++    <feature name='monitor' removed='yes'/>
++    <feature name='movbe'/>
++    <feature name='msr'/>
++    <feature name='mtrr'/>
++    <feature name='npt'/>
++    <feature name='nrip-save'/>
++    <feature name='nx'/>
++    <feature name='osvw'/>
++    <feature name='pae'/>
++    <feature name='pat'/>
++    <feature name='pclmuldq'/>
++    <feature name='pdpe1gb'/>
++    <feature name='perfctr_core'/>
++    <feature name='pge'/>
++    <feature name='pni'/>
++    <feature name='popcnt'/>
++    <feature name='pse'/>
++    <feature name='pse36'/>
++    <feature name='rdrand'/>
++    <feature name='rdseed'/>
++    <feature name='rdtscp'/>
++    <feature name='sep'/>
++    <feature name='sha-ni'/>
++    <feature name='smap'/>
++    <feature name='smep'/>
++    <feature name='sse'/>
++    <feature name='sse2'/>
++    <feature name='sse4.1'/>
++    <feature name='sse4.2'/>
++    <feature name='sse4a'/>
++    <feature name='ssse3'/>
++    <feature name='svm'/>
++    <feature name='syscall'/>
++    <feature name='tsc'/>
++    <feature name='umip'/>
++    <feature name='vaes'/>
++    <feature name='vme'/>
++    <feature name='vpclmulqdq'/>
++    <feature name='wbnoinvd'/>
++    <feature name='xgetbv1'/>
++    <feature name='xsave'/>
++    <feature name='xsavec'/>
++    <feature name='xsaveerptr'/>
++    <feature name='xsaveopt'/>
++  </model>
++</cpus>
+--
+2.41.0
+
diff --git a/libvirt.spec b/libvirt.spec
index cfb5a900c70eddcc0bf6e60b14084965c62530ff..bd8d3ad7b995f8efb3256db41b93ea63ec62873e 100644
--- a/libvirt.spec
+++ b/libvirt.spec
@@ -1,4 +1,4 @@
-%define anolis_release 12
+%define anolis_release 13
 
 %define arches_qemu_kvm         x86_64 aarch64 loongarch64 sw_64 riscv64
 
@@ -178,6 +178,7 @@ Patch0012: Add-sw64-architecture-support-for-libvirt-9.10.0.patch
 Patch0013: 0013-conf-qemu-Fix-some-code-about-Reuse-ASID-for-Hygon-C.patch
 # Support provide blobs for secret injection for Hygon Confidential VMs
 Patch0014: 0014-conf-qemu-support-provide-inject-secret-for-Hygon-CS.patch
+Patch0015: 0015-cpu-Add-new-Chengdu-CPU-model.patch
 
 Requires: libvirt-daemon = %{version}-%{release}
 Requires: libvirt-daemon-config-network = %{version}-%{release}
@@ -2158,6 +2159,9 @@ exit 0
 
 
 %changelog
+* Wed May 28 2025 Yanjing Zhou <zhouyanjing@hygon.cn> - 9.10.0-13
+- Add new Chengdu CPU model
+
 * Wed May 7 2025 Yihao Yan <yan.yihao@zte.com.cn> - 9.10.0-12
 - add support for riscv64