diff --git a/1000-gallium-llvmpipe-pass-MCPU-mips64r2-to-LLVM-on-mips.patch b/1000-gallium-llvmpipe-pass-MCPU-mips64r2-to-LLVM-on-mips.patch new file mode 100644 index 0000000000000000000000000000000000000000..c3f56c371eeaebf22d7a441136ec0620805d65d6 --- /dev/null +++ b/1000-gallium-llvmpipe-pass-MCPU-mips64r2-to-LLVM-on-mips.patch @@ -0,0 +1,127 @@ +From 9fc3cfd1683cedf1628cc2f965d5629f39c4b5ca Mon Sep 17 00:00:00 2001 +From: Liwei Ge +Date: Wed, 12 Oct 2022 10:39:26 +0800 +Subject: [PATCH 1000/1012] gallium: llvmpipe: pass MCPU = mips64r2 to LLVM on + mips + +According to LLVM, the MSA SIMD requires MIPS64 revision 5 or greater, +but MSA instruction set is actually implemented on ls3a4000. + +This patch add support to detect if MSA is available, and force to enable +MSA SIMD on LS3A4000 CPU. So we override the MCPU to mips64r5 if MSA is +implemented, feedback to mips64r2 for all other ordinaries. + +Otherwise, it complains when running 3D application: + +'generic' is not a recognized processor for this target (ignoring processor) +'generic' is not a recognized processor for this target (ignoring processor) +... +'generic' is not a recognized processor for this target (ignoring processor) +'generic' is not a recognized processor for this target (ignoring processor + +see: + [1] http://huonw.github.io/llvmint/llvmint/mips/index.html + [2] https://gitlab.freedesktop.org/mesa/mesa/-/commit/385ee7c3d0536424eb9822fe873d4410b831cbfe +--- + src/gallium/auxiliary/gallivm/lp_bld_misc.cpp | 13 ++++++++- + src/gallium/include/pipe/p_config.h | 6 ++++ + src/util/u_cpu_detect.c | 28 +++++++++++++++++++ + 3 files changed, 46 insertions(+), 1 deletion(-) + +diff --git a/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp b/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp +index be288ab..1375a27 100644 +--- a/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp ++++ b/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp +@@ -470,6 +470,17 @@ lp_build_create_jit_compiler_for_module(LLVMExecutionEngineRef *OutJIT, + MAttrs.push_back("+fp64"); + #endif + ++#if defined(PIPE_ARCH_MIPS64) ++ /* MSA requires a 64-bit FPU register file */ ++ MAttrs.push_back(util_cpu_caps.has_msa ? "+msa" : "-msa"); ++ /* Support 64-bit FP registers. */ ++ MAttrs.push_back("+fp64"); ++ /* General Purpose Registers are 64-bit wide */ ++ MAttrs.push_back("+gp64"); ++ /* Pointers are 64-bit wide */ ++ MAttrs.push_back("+ptr64"); ++#endif ++ + builder.setMAttrs(MAttrs); + + if (gallivm_debug & (GALLIVM_DEBUG_IR | GALLIVM_DEBUG_ASM | GALLIVM_DEBUG_DUMP_BC)) { +@@ -531,7 +542,7 @@ lp_build_create_jit_compiler_for_module(LLVMExecutionEngineRef *OutJIT, + * mips CPU currently. So we override the MCPU to mips64r5 if MSA is + * implemented, feedback to mips64r2 for all other ordinary mips64 cpu. + */ +- if (MCPU == "generic") ++ if (MCPU == "generic" || MCPU == "loongson3a") + MCPU = util_get_cpu_caps()->has_msa ? "mips64r5" : "mips64r2"; + #endif + +diff --git a/src/gallium/include/pipe/p_config.h b/src/gallium/include/pipe/p_config.h +index 978aa45..deb4712 100644 +--- a/src/gallium/include/pipe/p_config.h ++++ b/src/gallium/include/pipe/p_config.h +@@ -130,6 +130,12 @@ + #define PIPE_ARCH_MIPS + #endif + ++#if defined(__mips64) && defined(__LP64__) ++#define PIPE_ARCH_MIPS64 ++#elif defined(__mips__) ++#define PIPE_ARCH_MIPS ++#endif ++ + /* + * Endian detection. + */ +diff --git a/src/util/u_cpu_detect.c b/src/util/u_cpu_detect.c +index 955d087..8d91eae 100644 +--- a/src/util/u_cpu_detect.c ++++ b/src/util/u_cpu_detect.c +@@ -457,6 +457,30 @@ check_os_mips64_support(void) + #endif /* PIPE_ARCH_MIPS64 */ + + ++#if defined(PIPE_ARCH_MIPS64) ++static void ++check_os_mips64_support(void) ++{ ++#if defined(PIPE_OS_LINUX) ++ Elf64_auxv_t aux; ++ int fd; ++ ++ fd = open("/proc/self/auxv", O_RDONLY | O_CLOEXEC); ++ if (fd >= 0) { ++ while (read(fd, &aux, sizeof(Elf64_auxv_t)) == sizeof(Elf64_auxv_t)) { ++ if (aux.a_type == AT_HWCAP) { ++ uint64_t hwcap = aux.a_un.a_val; ++ ++ util_cpu_caps.has_msa = (hwcap >> 1) & 1; ++ break; ++ } ++ } ++ close (fd); ++ } ++#endif /* PIPE_OS_LINUX */ ++} ++#endif ++ + static void + get_cpu_topology(void) + { +@@ -805,6 +829,10 @@ util_cpu_detect_once(void) + check_os_arm_support(); + #endif + ++#if defined(PIPE_ARCH_MIPS64) ++ check_os_mips64_support(); ++#endif ++ + #if defined(PIPE_ARCH_PPC) + check_os_altivec_support(); + #endif /* PIPE_ARCH_PPC */ +-- +2.27.0 + diff --git a/1001-gallivm-Return-true-from-arch_rounding_available-if-.patch b/1001-gallivm-Return-true-from-arch_rounding_available-if-.patch new file mode 100644 index 0000000000000000000000000000000000000000..c72c2de4ffbed0debd8a2d2639ba1ea68d9869df --- /dev/null +++ b/1001-gallivm-Return-true-from-arch_rounding_available-if-.patch @@ -0,0 +1,59 @@ +From 82998b72bed2bf71a7036af4161aea054ed914e2 Mon Sep 17 00:00:00 2001 +From: suijingfeng +Date: Thu, 13 May 2021 15:56:59 +0800 +Subject: [PATCH 1001/1012] gallivm: Return true from arch_rounding_available() + if MSA is available + +LLVM uses the single instruction "FRINTI" to implement llvm.nearbyint. +Fix the rounding test of lp_test_arit. + +See upstream patches and bug for reference: + [1] https://gitlab.freedesktop.org/mesa/mesa/-/commit/70a7ece035785978167fe0019b6ff603415b1f3b + [2] https://bugs.gentoo.org/665570 + +Signed-off-by: Weining Lu +Signed-off-by: suijingfeng +--- + src/gallium/auxiliary/gallivm/lp_bld_arit.c | 5 ++++- + src/gallium/drivers/llvmpipe/lp_test_arit.c | 2 +- + 2 files changed, 5 insertions(+), 2 deletions(-) + +diff --git a/src/gallium/auxiliary/gallivm/lp_bld_arit.c b/src/gallium/auxiliary/gallivm/lp_bld_arit.c +index 1c71c05..9e44c1c 100644 +--- a/src/gallium/auxiliary/gallivm/lp_bld_arit.c ++++ b/src/gallium/auxiliary/gallivm/lp_bld_arit.c +@@ -1887,6 +1887,9 @@ arch_rounding_available(const struct lp_type type) + return TRUE; + else if (util_get_cpu_caps()->has_neon) + return TRUE; ++ else if (util_get_cpu_caps()->has_msa && ++ (type.width * type.length == 128)) ++ return TRUE; + + return FALSE; + } +@@ -1994,7 +1997,7 @@ lp_build_round_arch(struct lp_build_context *bld, + LLVMValueRef a, + enum lp_build_round_mode mode) + { +- if (util_get_cpu_caps()->has_sse4_1 || util_get_cpu_caps()->has_neon) { ++ if (util_get_cpu_caps()->has_sse4_1 || util_get_cpu_caps()->has_neon || util_get_cpu_caps()->has_msa) { + LLVMBuilderRef builder = bld->gallivm->builder; + const struct lp_type type = bld->type; + const char *intrinsic_root; +diff --git a/src/gallium/drivers/llvmpipe/lp_test_arit.c b/src/gallium/drivers/llvmpipe/lp_test_arit.c +index cbea1e2..5d64132 100644 +--- a/src/gallium/drivers/llvmpipe/lp_test_arit.c ++++ b/src/gallium/drivers/llvmpipe/lp_test_arit.c +@@ -479,7 +479,7 @@ test_unary(unsigned verbose, FILE *fp, const struct unary_test_t *test, unsigned + continue; + } + +- if (!util_get_cpu_caps()->has_neon && ++ if (!util_get_cpu_caps()->has_neon && !util_get_cpu_caps()->has_msa && + test->ref == &nearbyintf && length == 2 && + ref != roundf(testval)) { + /* FIXME: The generic (non SSE) path in lp_build_iround, which is +-- +2.27.0 + diff --git a/1002-gallivm-add-more-optlevel-for-debug-purpose-on-mips6.patch b/1002-gallivm-add-more-optlevel-for-debug-purpose-on-mips6.patch new file mode 100644 index 0000000000000000000000000000000000000000..1b8452a6a1efd0a31dbb3b739712dc35777fdec0 --- /dev/null +++ b/1002-gallivm-add-more-optlevel-for-debug-purpose-on-mips6.patch @@ -0,0 +1,67 @@ +From 6c1734b6939b2f1411afdc5c3d638063c67025f7 Mon Sep 17 00:00:00 2001 +From: Liwei Ge +Date: Wed, 12 Oct 2022 10:47:13 +0800 +Subject: [PATCH 1002/1012] gallivm: add more optlevel for debug purpose on + mips64 + +This patch also set the default optlevel to None as enable shader +compiling optimization on ls3a4000 is still problematic. +--- + src/gallium/auxiliary/gallivm/lp_bld_debug.h | 6 ++++++ + src/gallium/auxiliary/gallivm/lp_bld_init.c | 16 ++++++++++++++++ + 2 files changed, 22 insertions(+) + +diff --git a/src/gallium/auxiliary/gallivm/lp_bld_debug.h b/src/gallium/auxiliary/gallivm/lp_bld_debug.h +index a5dd7b8..7edf865 100644 +--- a/src/gallium/auxiliary/gallivm/lp_bld_debug.h ++++ b/src/gallium/auxiliary/gallivm/lp_bld_debug.h +@@ -49,6 +49,12 @@ + #define GALLIVM_PERF_NO_OPT (1 << 3) + #define GALLIVM_PERF_NO_AOS_SAMPLING (1 << 4) + ++#if defined(PIPE_ARCH_MIPS64) ++#define GALLIVM_PERF_OPT_O1 (1 << 5) ++#define GALLIVM_PERF_OPT_O2 (1 << 6) ++#define GALLIVM_PERF_OPT_O3 (1 << 7) ++#endif ++ + #ifdef __cplusplus + extern "C" { + #endif +diff --git a/src/gallium/auxiliary/gallivm/lp_bld_init.c b/src/gallium/auxiliary/gallivm/lp_bld_init.c +index 3f040ac..e380d6f 100644 +--- a/src/gallium/auxiliary/gallivm/lp_bld_init.c ++++ b/src/gallium/auxiliary/gallivm/lp_bld_init.c +@@ -60,6 +60,11 @@ static const struct debug_named_value lp_bld_perf_flags[] = { + { "no_quad_lod", GALLIVM_PERF_NO_QUAD_LOD, "disable quad_lod optimization" }, + { "no_aos_sampling", GALLIVM_PERF_NO_AOS_SAMPLING, "disable aos sampling optimization" }, + { "nopt", GALLIVM_PERF_NO_OPT, "disable optimization passes to speed up shader compilation" }, ++#if defined(PIPE_ARCH_MIPS64) ++ { "o3", GALLIVM_PERF_OPT_O3, "enable aggressive optimization passes" }, ++ { "o2", GALLIVM_PERF_OPT_O2, "enable medium optimization passes" }, ++ { "o1", GALLIVM_PERF_OPT_O1, "enable less optimization passes" }, ++#endif + DEBUG_NAMED_VALUE_END + }; + +@@ -270,6 +275,17 @@ init_gallivm_engine(struct gallivm_state *gallivm) + optlevel = Default; + } + ++#if defined(PIPE_ARCH_MIPS64) ++ if (gallivm_perf & GALLIVM_PERF_OPT_O3) ++ optlevel = Aggressive; ++ else if (gallivm_perf & GALLIVM_PERF_OPT_O2) ++ optlevel = Default; ++ else if (gallivm_perf & GALLIVM_PERF_OPT_O1) ++ optlevel = Less; ++ else ++ optlevel = None; ++#endif ++ + ret = lp_build_create_jit_compiler_for_module(&gallivm->engine, + &gallivm->code, + gallivm->cache, +-- +2.27.0 + diff --git a/1003-disable-madd4-on-mips64.patch b/1003-disable-madd4-on-mips64.patch new file mode 100644 index 0000000000000000000000000000000000000000..34b00fd3384d4db6b5c879a8b7e032f664d5f603 --- /dev/null +++ b/1003-disable-madd4-on-mips64.patch @@ -0,0 +1,27 @@ +From 3f434ec4f4e4258d61f07e7805c644fe19db2964 Mon Sep 17 00:00:00 2001 +From: suijingfeng +Date: Sat, 10 Jul 2021 23:09:11 +0800 +Subject: [PATCH 1003/1012] disable madd4 on mips64 + +--- + src/gallium/auxiliary/gallivm/lp_bld_init.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/src/gallium/auxiliary/gallivm/lp_bld_init.c b/src/gallium/auxiliary/gallivm/lp_bld_init.c +index e380d6f..5d0127b 100644 +--- a/src/gallium/auxiliary/gallivm/lp_bld_init.c ++++ b/src/gallium/auxiliary/gallivm/lp_bld_init.c +@@ -638,6 +638,10 @@ gallivm_compile_module(struct gallivm_state *gallivm) + LLVMAddTargetDependentFunctionAttr(func, "no-frame-pointer-elim-non-leaf", "true"); + #endif + ++#if defined(PIPE_ARCH_MIPS64) ++ LLVMAddTargetDependentFunctionAttr(func, "target-features", "+nomadd4"); ++#endif ++ + LLVMRunFunctionPassManager(gallivm->passmgr, func); + func = LLVMGetNextFunction(func); + } +-- +2.27.0 + diff --git a/1004-kmsro-Extend-to-include-loongson-drm-support.patch b/1004-kmsro-Extend-to-include-loongson-drm-support.patch new file mode 100644 index 0000000000000000000000000000000000000000..a9069d447d8ef4257bb06185b1237533ff11f580 --- /dev/null +++ b/1004-kmsro-Extend-to-include-loongson-drm-support.patch @@ -0,0 +1,73 @@ +From c8fd7aed1b51cf5da7564cdbacacd9f37931b3c8 Mon Sep 17 00:00:00 2001 +From: Liwei Ge +Date: Wed, 12 Oct 2022 10:59:56 +0800 +Subject: [PATCH 1004/1012] kmsro: Extend to include loongson-drm support + +This enables Mesa to work with Loongson SoCs through the use of the +loongson-drm modesetting driver along with the render-only drivers, +such as Etnaviv on the LS2K1000 SoC and LS7A1000 bridge. + +GC1000 in LS7A1000 north bridge is a PCI device, its PCI device id +is 0x7a15, 0x0014 is vendor id of Loongson coporation. + +LS7A1000 north bridge also have a display controller intergrated, +its PCI device id is 0x7a06. +--- + src/gallium/targets/dri/meson.build | 1 + + src/gallium/targets/dri/target.c | 1 + + src/loader/pci_id_driver_map.h | 8 ++++++++ + 3 files changed, 10 insertions(+) + +diff --git a/src/gallium/targets/dri/meson.build b/src/gallium/targets/dri/meson.build +index 86f66a6..6496088 100644 +--- a/src/gallium/targets/dri/meson.build ++++ b/src/gallium/targets/dri/meson.build +@@ -76,6 +76,7 @@ foreach d : [[with_gallium_kmsro, [ + 'imx-dcss_dri.so', + 'ingenic-drm_dri.so', + 'kirin_dri.so', ++ 'loongson-drm_dri.so', + 'mali-dp_dri.so', + 'mcde_dri.so', + 'mediatek_dri.so', +diff --git a/src/gallium/targets/dri/target.c b/src/gallium/targets/dri/target.c +index 30c9ee9..cfb2c7a 100644 +--- a/src/gallium/targets/dri/target.c ++++ b/src/gallium/targets/dri/target.c +@@ -105,6 +105,7 @@ DEFINE_LOADER_DRM_ENTRYPOINT(imx_drm) + DEFINE_LOADER_DRM_ENTRYPOINT(imx_dcss) + DEFINE_LOADER_DRM_ENTRYPOINT(ingenic_drm) + DEFINE_LOADER_DRM_ENTRYPOINT(kirin) ++DEFINE_LOADER_DRM_ENTRYPOINT(loongson_drm) + DEFINE_LOADER_DRM_ENTRYPOINT(mali_dp) + DEFINE_LOADER_DRM_ENTRYPOINT(mcde) + DEFINE_LOADER_DRM_ENTRYPOINT(mediatek) +diff --git a/src/loader/pci_id_driver_map.h b/src/loader/pci_id_driver_map.h +index d75b2cc..df3811a 100644 +--- a/src/loader/pci_id_driver_map.h ++++ b/src/loader/pci_id_driver_map.h +@@ -68,6 +68,13 @@ static const int vmwgfx_chip_ids[] = { + #undef CHIPSET + }; + ++static const int ls7a_chip_ids[] = { ++#define CHIPSET(chip, name, family) chip, ++#include "pci_ids/ls7a1000_pci_ids.h" ++#undef CHIPSET ++}; ++ ++ + bool is_nouveau_vieux(int fd); + bool is_kernel_i915(int fd); + +@@ -90,6 +97,7 @@ static const struct { + { 0x1002, "radeonsi", NULL, -1 }, + { 0x10de, "nouveau_vieux", NULL, -1, is_nouveau_vieux }, + { 0x10de, "nouveau", NULL, -1, }, ++ { 0x0014, "loongson-drm", ls7a_chip_ids, ARRAY_SIZE(ls7a_chip_ids) }, + { 0x1af4, "virtio_gpu", virtio_gpu_chip_ids, ARRAY_SIZE(virtio_gpu_chip_ids) }, + { 0x15ad, "vmwgfx", vmwgfx_chip_ids, ARRAY_SIZE(vmwgfx_chip_ids) }, + }; +-- +2.27.0 + diff --git a/1005-meson-add-loongarch64-build-support.patch b/1005-meson-add-loongarch64-build-support.patch new file mode 100644 index 0000000000000000000000000000000000000000..9a116f8809656dea53cc5fadcf8d443e77f61917 --- /dev/null +++ b/1005-meson-add-loongarch64-build-support.patch @@ -0,0 +1,46 @@ +From b430ea6feb0e20c86937c9619c076ee102376107 Mon Sep 17 00:00:00 2001 +From: Liwei Ge +Date: Wed, 12 Oct 2022 11:01:13 +0800 +Subject: [PATCH 1005/1012] meson: add loongarch64 build support + +--- + meson.build | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/meson.build b/meson.build +index 0aea312..f47b98a 100644 +--- a/meson.build ++++ b/meson.build +@@ -176,6 +176,8 @@ if dri_drivers.contains('auto') + dri_drivers = [] + elif ['mips', 'mips64', 'riscv32', 'riscv64'].contains(host_machine.cpu_family()) + dri_drivers = ['r100', 'r200', 'nouveau'] ++ elif ['loongarch64'].contains(host_machine.cpu_family()) ++ dri_drivers = [] + else + error('Unknown architecture @0@. Please pass -Ddri-drivers to set driver options. Patches gladly accepted to fix this.'.format( + host_machine.cpu_family())) +@@ -215,6 +217,11 @@ if gallium_drivers.contains('auto') + gallium_drivers = [ + 'r300', 'r600', 'radeonsi', 'nouveau', 'virgl', 'swrast' + ] ++ elif ['loongarch64'].contains(host_machine.cpu_family()) ++ gallium_drivers = [ ++ 'r300', 'r600', 'radeonsi', 'nouveau', 'etnaviv', 'kmsro', 'swrast', ++ 'virgl' ++ ] + else + error('Unknown architecture @0@. Please pass -Dgallium-drivers to set driver options. Patches gladly accepted to fix this.'.format( + host_machine.cpu_family())) +@@ -268,6 +275,8 @@ if _vulkan_drivers.contains('auto') + _vulkan_drivers = ['swrast'] + elif ['mips', 'mips64', 'riscv32', 'riscv64'].contains(host_machine.cpu_family()) + _vulkan_drivers = ['amd', 'swrast'] ++ elif ['loongarch64'].contains(host_machine.cpu_family()) ++ _vulkan_drivers = ['amd', 'swrast'] + else + error('Unknown architecture @0@. Please pass -Dvulkan-drivers to set driver options. Patches gladly accepted to fix this.'.format( + host_machine.cpu_family())) +-- +2.27.0 + diff --git a/1006-gallivm-temporary-disable-coroutines-on-loongarch64-.patch b/1006-gallivm-temporary-disable-coroutines-on-loongarch64-.patch new file mode 100644 index 0000000000000000000000000000000000000000..3cfe4aa1e16f8ca10acc14457af82f0dc55bf3e3 --- /dev/null +++ b/1006-gallivm-temporary-disable-coroutines-on-loongarch64-.patch @@ -0,0 +1,53 @@ +From c6d13fa9f54f568c353df9da76b2f29efb0fc75e Mon Sep 17 00:00:00 2001 +From: suijingfeng +Date: Sun, 11 Jul 2021 06:12:17 +0800 +Subject: [PATCH 1006/1012] gallivm: temporary disable coroutines on + loongarch64 and mips64 + +Signed-off-by: suijingfeng +--- + src/gallium/auxiliary/gallivm/lp_bld.h | 4 ++++ + src/gallium/auxiliary/gallivm/lp_bld_init.c | 4 ++-- + 2 files changed, 6 insertions(+), 2 deletions(-) + +diff --git a/src/gallium/auxiliary/gallivm/lp_bld.h b/src/gallium/auxiliary/gallivm/lp_bld.h +index 9144428..2fd50dd 100644 +--- a/src/gallium/auxiliary/gallivm/lp_bld.h ++++ b/src/gallium/auxiliary/gallivm/lp_bld.h +@@ -82,7 +82,11 @@ + #define LLVMCreateBuilder ILLEGAL_LLVM_FUNCTION + + #if LLVM_VERSION_MAJOR >= 8 ++#if defined(__loongarch__) || defined(__mips__) ++#define GALLIVM_HAVE_CORO 0 ++#else + #define GALLIVM_HAVE_CORO 1 ++#endif + #else + #define GALLIVM_HAVE_CORO 0 + #endif +diff --git a/src/gallium/auxiliary/gallivm/lp_bld_init.c b/src/gallium/auxiliary/gallivm/lp_bld_init.c +index 5d0127b..bc3d75e 100644 +--- a/src/gallium/auxiliary/gallivm/lp_bld_init.c ++++ b/src/gallium/auxiliary/gallivm/lp_bld_init.c +@@ -46,7 +46,7 @@ + #endif + #include + #if GALLIVM_HAVE_CORO +-#if LLVM_VERSION_MAJOR <= 8 && (defined(PIPE_ARCH_AARCH64) || defined (PIPE_ARCH_ARM) || defined(PIPE_ARCH_S390) || defined(PIPE_ARCH_MIPS64)) ++#if LLVM_VERSION_MAJOR <= 8 && (defined(PIPE_ARCH_AARCH64) || defined (PIPE_ARCH_ARM) || defined(PIPE_ARCH_S390) || defined(PIPE_ARCH_MIPS64) || defined(PIPE_ARCH_LOONGARCH64)) + #include + #endif + #include +@@ -140,7 +140,7 @@ create_pass_manager(struct gallivm_state *gallivm) + } + + #if GALLIVM_HAVE_CORO +-#if LLVM_VERSION_MAJOR <= 8 && (defined(PIPE_ARCH_AARCH64) || defined (PIPE_ARCH_ARM) || defined(PIPE_ARCH_S390) || defined(PIPE_ARCH_MIPS64)) ++#if LLVM_VERSION_MAJOR <= 8 && (defined(PIPE_ARCH_AARCH64) || defined (PIPE_ARCH_ARM) || defined(PIPE_ARCH_S390) || defined(PIPE_ARCH_MIPS64) || defined(PIPE_ARCH_LOONGARCH64)) + LLVMAddArgumentPromotionPass(gallivm->cgpassmgr); + LLVMAddFunctionAttrsPass(gallivm->cgpassmgr); + #endif +-- +2.27.0 + diff --git a/1007-gallivm-detect-loongarch-lsx-and-lasx-instruction-se.patch b/1007-gallivm-detect-loongarch-lsx-and-lasx-instruction-se.patch new file mode 100644 index 0000000000000000000000000000000000000000..5ee9e8be3bf71b0359f62b898b049681b72ed8a9 --- /dev/null +++ b/1007-gallivm-detect-loongarch-lsx-and-lasx-instruction-se.patch @@ -0,0 +1,159 @@ +From ba29960f28b79e2ec5d0b89c0f6cd449853a7cd1 Mon Sep 17 00:00:00 2001 +From: Liwei Ge +Date: Wed, 12 Oct 2022 11:05:23 +0800 +Subject: [PATCH 1007/1012] gallivm: detect loongarch lsx and lasx instruction + set + +--- + src/gallium/auxiliary/gallivm/lp_bld_arit.c | 9 +++++- + src/gallium/auxiliary/gallivm/lp_bld_misc.cpp | 11 +++++++ + src/gallium/include/pipe/p_config.h | 6 ++++ + src/util/u_cpu_detect.c | 31 +++++++++++++++++++ + src/util/u_cpu_detect.h | 2 ++ + 5 files changed, 58 insertions(+), 1 deletion(-) + +diff --git a/src/gallium/auxiliary/gallivm/lp_bld_arit.c b/src/gallium/auxiliary/gallivm/lp_bld_arit.c +index 9e44c1c..2039b3f 100644 +--- a/src/gallium/auxiliary/gallivm/lp_bld_arit.c ++++ b/src/gallium/auxiliary/gallivm/lp_bld_arit.c +@@ -1890,6 +1890,12 @@ arch_rounding_available(const struct lp_type type) + else if (util_get_cpu_caps()->has_msa && + (type.width * type.length == 128)) + return TRUE; ++ else if (util_get_cpu_caps()->has_lsx && ++ (type.width * type.length == 128)) ++ return TRUE; ++ else if (util_get_cpu_caps()->has_lasx && ++ (type.width * type.length == 256)) ++ return TRUE; + + return FALSE; + } +@@ -1997,7 +2003,8 @@ lp_build_round_arch(struct lp_build_context *bld, + LLVMValueRef a, + enum lp_build_round_mode mode) + { +- if (util_get_cpu_caps()->has_sse4_1 || util_get_cpu_caps()->has_neon || util_get_cpu_caps()->has_msa) { ++ if (util_get_cpu_caps()->has_sse4_1 || util_get_cpu_caps()->has_neon || util_get_cpu_caps()->has_msa ++ || util_get_cpu_caps()->has_lsx || util_get_cpu_caps()->has_lasx) { + LLVMBuilderRef builder = bld->gallivm->builder; + const struct lp_type type = bld->type; + const char *intrinsic_root; +diff --git a/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp b/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp +index 1375a27..9f9a3dd 100644 +--- a/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp ++++ b/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp +@@ -481,6 +481,12 @@ lp_build_create_jit_compiler_for_module(LLVMExecutionEngineRef *OutJIT, + MAttrs.push_back("+ptr64"); + #endif + ++#if defined(PIPE_ARCH_LOONGARCH64) ++// Our llvm compilor is not ready for this now ++// MAttrs.push_back(util_get_cpu_caps()->has_lsx ? "+lsx" : "-lsx"); ++// MAttrs.push_back(util_get_cpu_caps()->has_lasx ? "+lasx" : "-lasx"); ++#endif ++ + builder.setMAttrs(MAttrs); + + if (gallivm_debug & (GALLIVM_DEBUG_IR | GALLIVM_DEBUG_ASM | GALLIVM_DEBUG_DUMP_BC)) { +@@ -546,6 +552,11 @@ lp_build_create_jit_compiler_for_module(LLVMExecutionEngineRef *OutJIT, + MCPU = util_get_cpu_caps()->has_msa ? "mips64r5" : "mips64r2"; + #endif + ++#if defined(PIPE_ARCH_LOONGARCH64) ++ if (MCPU == "generic") ++ MCPU = "gs464v"; ++#endif ++ + builder.setMCPU(MCPU); + if (gallivm_debug & (GALLIVM_DEBUG_IR | GALLIVM_DEBUG_ASM | GALLIVM_DEBUG_DUMP_BC)) { + debug_printf("llc -mcpu option: %s\n", MCPU.str().c_str()); +diff --git a/src/gallium/include/pipe/p_config.h b/src/gallium/include/pipe/p_config.h +index deb4712..87f6d61 100644 +--- a/src/gallium/include/pipe/p_config.h ++++ b/src/gallium/include/pipe/p_config.h +@@ -136,6 +136,12 @@ + #define PIPE_ARCH_MIPS + #endif + ++#if defined(__loongarch64__) || defined(__loongarch64) ++#define PIPE_ARCH_LOONGARCH64 ++#elif defined(__loongarch__) ++#define PIPE_ARCH_LOONGARCH ++#endif ++ + /* + * Endian detection. + */ +diff --git a/src/util/u_cpu_detect.c b/src/util/u_cpu_detect.c +index 8d91eae..7d29689 100644 +--- a/src/util/u_cpu_detect.c ++++ b/src/util/u_cpu_detect.c +@@ -481,6 +481,31 @@ check_os_mips64_support(void) + } + #endif + ++#if defined(PIPE_ARCH_LOONGARCH64) ++static void ++check_os_loongarch64_support(void) ++{ ++#if defined(PIPE_OS_LINUX) ++ Elf64_auxv_t aux; ++ int fd; ++ ++ fd = open("/proc/self/auxv", O_RDONLY | O_CLOEXEC); ++ if (fd >= 0) { ++ while (read(fd, &aux, sizeof(Elf64_auxv_t)) == sizeof(Elf64_auxv_t)) { ++ if (aux.a_type == AT_HWCAP) { ++ uint64_t hwcap = aux.a_un.a_val; ++ ++ util_cpu_caps.has_lsx = (hwcap >> 2) & 1; ++ util_cpu_caps.has_lasx = (hwcap >> 3) & 1; ++ break; ++ } ++ } ++ close (fd); ++ } ++#endif /* PIPE_OS_LINUX */ ++} ++#endif ++ + static void + get_cpu_topology(void) + { +@@ -833,6 +858,10 @@ util_cpu_detect_once(void) + check_os_mips64_support(); + #endif + ++#if defined(PIPE_ARCH_LOONGARCH64) ++ check_os_loongarch64_support(); ++#endif ++ + #if defined(PIPE_ARCH_PPC) + check_os_altivec_support(); + #endif /* PIPE_ARCH_PPC */ +@@ -869,6 +898,8 @@ util_cpu_detect_once(void) + printf("util_cpu_caps.has_vsx = %u\n", util_cpu_caps.has_vsx); + printf("util_cpu_caps.has_neon = %u\n", util_cpu_caps.has_neon); + printf("util_cpu_caps.has_msa = %u\n", util_cpu_caps.has_msa); ++ printf("util_cpu_caps.has_lsx = %u\n", util_cpu_caps.has_lsx); ++ printf("util_cpu_caps.has_lasx = %u\n", util_cpu_caps.has_lasx); + printf("util_cpu_caps.has_daz = %u\n", util_cpu_caps.has_daz); + printf("util_cpu_caps.has_avx512f = %u\n", util_cpu_caps.has_avx512f); + printf("util_cpu_caps.has_avx512dq = %u\n", util_cpu_caps.has_avx512dq); +diff --git a/src/util/u_cpu_detect.h b/src/util/u_cpu_detect.h +index 59dd230..cd4319e 100644 +--- a/src/util/u_cpu_detect.h ++++ b/src/util/u_cpu_detect.h +@@ -103,6 +103,8 @@ struct util_cpu_caps_t { + unsigned has_daz:1; + unsigned has_neon:1; + unsigned has_msa:1; ++ unsigned has_lsx:1; ++ unsigned has_lasx:1; + + unsigned has_avx512f:1; + unsigned has_avx512dq:1; +-- +2.27.0 + diff --git a/1008-gallivm-arit-use-LLVMBuildFPToUI-when-the-float-is-n.patch b/1008-gallivm-arit-use-LLVMBuildFPToUI-when-the-float-is-n.patch new file mode 100644 index 0000000000000000000000000000000000000000..6a1371de9e4e70aabd0cc5bb6372565734c977a8 --- /dev/null +++ b/1008-gallivm-arit-use-LLVMBuildFPToUI-when-the-float-is-n.patch @@ -0,0 +1,29 @@ +From 7652b91076a0d13ab697e7383f04e24b8f9d7d99 Mon Sep 17 00:00:00 2001 +From: suijingfeng +Date: Mon, 16 Aug 2021 14:42:57 +0800 +Subject: [PATCH 1008/1012] gallivm: arit: use LLVMBuildFPToUI when the float + is not signed + +--- + src/gallium/auxiliary/gallivm/lp_bld_arit.c | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +diff --git a/src/gallium/auxiliary/gallivm/lp_bld_arit.c b/src/gallium/auxiliary/gallivm/lp_bld_arit.c +index 2039b3f..cc48d46 100644 +--- a/src/gallium/auxiliary/gallivm/lp_bld_arit.c ++++ b/src/gallium/auxiliary/gallivm/lp_bld_arit.c +@@ -2413,7 +2413,10 @@ lp_build_iround(struct lp_build_context *bld, + res = LLVMBuildFAdd(builder, a, half, ""); + } + +- res = LLVMBuildFPToSI(builder, res, int_vec_type, ""); ++ if (type.sign) ++ res = LLVMBuildFPToSI(builder, res, int_vec_type, ""); ++ else ++ res = LLVMBuildFPToUI(builder, res, int_vec_type, ""); + + return res; + } +-- +2.27.0 + diff --git a/1009-gallivm-disable-use-lp_build_round_arch-on-default.patch b/1009-gallivm-disable-use-lp_build_round_arch-on-default.patch new file mode 100644 index 0000000000000000000000000000000000000000..8fcc23ed35810f4c2b4ff49075ed57294ff0f686 --- /dev/null +++ b/1009-gallivm-disable-use-lp_build_round_arch-on-default.patch @@ -0,0 +1,73 @@ +From b1f9699280510d406166226c37bcd266ab4ea0c4 Mon Sep 17 00:00:00 2001 +From: suijingfeng +Date: Mon, 16 Aug 2021 16:13:53 +0800 +Subject: [PATCH 1009/1012] gallivm: disable use lp_build_round_arch() on + default + +As it kill performance of the application due to poor optimization +of nearbyintf function previded by GLIBC on MIPS64 and LOONGARCH64. + +But is still possible to use lp_build_round_arch() by pass the +GALLIVM_PERF=use_arch_rounding commnad line on the front of run +a 3D app. + +take glmark2 for example: + +$ GALLIVM_PERF=use_arch_rounding glmark2 + +Signed-off-by: suijingfeng +--- + src/gallium/auxiliary/gallivm/lp_bld_arit.c | 6 +++--- + src/gallium/auxiliary/gallivm/lp_bld_debug.h | 2 ++ + src/gallium/auxiliary/gallivm/lp_bld_init.c | 1 + + 3 files changed, 6 insertions(+), 3 deletions(-) + +diff --git a/src/gallium/auxiliary/gallivm/lp_bld_arit.c b/src/gallium/auxiliary/gallivm/lp_bld_arit.c +index cc48d46..25d85e6 100644 +--- a/src/gallium/auxiliary/gallivm/lp_bld_arit.c ++++ b/src/gallium/auxiliary/gallivm/lp_bld_arit.c +@@ -1889,13 +1889,13 @@ arch_rounding_available(const struct lp_type type) + return TRUE; + else if (util_get_cpu_caps()->has_msa && + (type.width * type.length == 128)) +- return TRUE; ++ return ((gallivm_perf & GALLIVM_PERF_USE_ARCH_ROUNDING) ? TRUE : FALSE); + else if (util_get_cpu_caps()->has_lsx && + (type.width * type.length == 128)) +- return TRUE; ++ return ((gallivm_perf & GALLIVM_PERF_USE_ARCH_ROUNDING) ? TRUE : FALSE); + else if (util_get_cpu_caps()->has_lasx && + (type.width * type.length == 256)) +- return TRUE; ++ return ((gallivm_perf & GALLIVM_PERF_USE_ARCH_ROUNDING) ? TRUE : FALSE); + + return FALSE; + } +diff --git a/src/gallium/auxiliary/gallivm/lp_bld_debug.h b/src/gallium/auxiliary/gallivm/lp_bld_debug.h +index 7edf865..1e8b5c7 100644 +--- a/src/gallium/auxiliary/gallivm/lp_bld_debug.h ++++ b/src/gallium/auxiliary/gallivm/lp_bld_debug.h +@@ -55,6 +55,8 @@ + #define GALLIVM_PERF_OPT_O3 (1 << 7) + #endif + ++#define GALLIVM_PERF_USE_ARCH_ROUNDING (1 << 8) ++ + #ifdef __cplusplus + extern "C" { + #endif +diff --git a/src/gallium/auxiliary/gallivm/lp_bld_init.c b/src/gallium/auxiliary/gallivm/lp_bld_init.c +index bc3d75e..0c1bce0 100644 +--- a/src/gallium/auxiliary/gallivm/lp_bld_init.c ++++ b/src/gallium/auxiliary/gallivm/lp_bld_init.c +@@ -65,6 +65,7 @@ static const struct debug_named_value lp_bld_perf_flags[] = { + { "o2", GALLIVM_PERF_OPT_O2, "enable medium optimization passes" }, + { "o1", GALLIVM_PERF_OPT_O1, "enable less optimization passes" }, + #endif ++ { "use_arch_rounding", GALLIVM_PERF_USE_ARCH_ROUNDING, "use poor arch rounding function provided by glibc" }, + DEBUG_NAMED_VALUE_END + }; + +-- +2.27.0 + diff --git a/1010-gallivm-add-more-optlevel-for-debuging-perpose-on.patch b/1010-gallivm-add-more-optlevel-for-debuging-perpose-on.patch new file mode 100644 index 0000000000000000000000000000000000000000..953d68e14b83d8a3f528328fd637bbf4cf909da2 --- /dev/null +++ b/1010-gallivm-add-more-optlevel-for-debuging-perpose-on.patch @@ -0,0 +1,71 @@ +From 2c6d151b5cca396ca06949c74c94caff4fc2896b Mon Sep 17 00:00:00 2001 +From: Liwei Ge +Date: Wed, 12 Oct 2022 11:08:17 +0800 +Subject: [PATCH 1010/1012] gallivm: add more optlevel for debuging perpose on + +This patch add more optlevel for shader compiling optimization on +loongarch. +--- + src/gallium/auxiliary/gallivm/lp_bld_debug.h | 2 +- + src/gallium/auxiliary/gallivm/lp_bld_init.c | 24 +++++++++----------- + 2 files changed, 12 insertions(+), 14 deletions(-) + +diff --git a/src/gallium/auxiliary/gallivm/lp_bld_debug.h b/src/gallium/auxiliary/gallivm/lp_bld_debug.h +index 1e8b5c7..6c22dc2 100644 +--- a/src/gallium/auxiliary/gallivm/lp_bld_debug.h ++++ b/src/gallium/auxiliary/gallivm/lp_bld_debug.h +@@ -49,7 +49,7 @@ + #define GALLIVM_PERF_NO_OPT (1 << 3) + #define GALLIVM_PERF_NO_AOS_SAMPLING (1 << 4) + +-#if defined(PIPE_ARCH_MIPS64) ++#if defined(PIPE_ARCH_MIPS64) || defined(PIPE_ARCH_LOONGARCH64) + #define GALLIVM_PERF_OPT_O1 (1 << 5) + #define GALLIVM_PERF_OPT_O2 (1 << 6) + #define GALLIVM_PERF_OPT_O3 (1 << 7) +diff --git a/src/gallium/auxiliary/gallivm/lp_bld_init.c b/src/gallium/auxiliary/gallivm/lp_bld_init.c +index 0c1bce0..e866e46 100644 +--- a/src/gallium/auxiliary/gallivm/lp_bld_init.c ++++ b/src/gallium/auxiliary/gallivm/lp_bld_init.c +@@ -60,7 +60,7 @@ static const struct debug_named_value lp_bld_perf_flags[] = { + { "no_quad_lod", GALLIVM_PERF_NO_QUAD_LOD, "disable quad_lod optimization" }, + { "no_aos_sampling", GALLIVM_PERF_NO_AOS_SAMPLING, "disable aos sampling optimization" }, + { "nopt", GALLIVM_PERF_NO_OPT, "disable optimization passes to speed up shader compilation" }, +-#if defined(PIPE_ARCH_MIPS64) ++#if defined(PIPE_ARCH_MIPS64) || defined(PIPE_ARCH_LOONGARCH64) + { "o3", GALLIVM_PERF_OPT_O3, "enable aggressive optimization passes" }, + { "o2", GALLIVM_PERF_OPT_O2, "enable medium optimization passes" }, + { "o1", GALLIVM_PERF_OPT_O1, "enable less optimization passes" }, +@@ -273,19 +273,17 @@ init_gallivm_engine(struct gallivm_state *gallivm) + optlevel = None; + } + else { +- optlevel = Default; +- } +- +-#if defined(PIPE_ARCH_MIPS64) +- if (gallivm_perf & GALLIVM_PERF_OPT_O3) +- optlevel = Aggressive; +- else if (gallivm_perf & GALLIVM_PERF_OPT_O2) +- optlevel = Default; +- else if (gallivm_perf & GALLIVM_PERF_OPT_O1) +- optlevel = Less; +- else +- optlevel = None; ++#if defined(PIPE_ARCH_MIPS64) || defined(PIPE_ARCH_LOONGARCH64) ++ if (gallivm_perf & GALLIVM_PERF_OPT_O3) ++ optlevel = Aggressive; ++ else if (gallivm_perf & GALLIVM_PERF_OPT_O2) ++ optlevel = Default; ++ else if (gallivm_perf & GALLIVM_PERF_OPT_O1) ++ optlevel = Less; ++ else + #endif ++ optlevel = Default; ++ } + + ret = lp_build_create_jit_compiler_for_module(&gallivm->engine, + &gallivm->code, +-- +2.27.0 + diff --git a/1011-gallivm-enable-lsx-and-lasx-on-loongarch-when-LLVM-e.patch b/1011-gallivm-enable-lsx-and-lasx-on-loongarch-when-LLVM-e.patch new file mode 100644 index 0000000000000000000000000000000000000000..d28635c001e694a0566664b380cee0394a5c8cab --- /dev/null +++ b/1011-gallivm-enable-lsx-and-lasx-on-loongarch-when-LLVM-e.patch @@ -0,0 +1,119 @@ +From ec771cd114005ac46a970c23e75191e9a8080f02 Mon Sep 17 00:00:00 2001 +From: suijingfeng +Date: Fri, 27 Aug 2021 10:09:28 +0800 +Subject: [PATCH 1011/1012] gallivm: enable lsx and lasx on loongarch when LLVM + expose it + + llvmpipe will crash when enable it with previous llvm release( +--- + src/gallium/auxiliary/gallivm/lp_bld_init.c | 9 ++++- + src/gallium/auxiliary/gallivm/lp_bld_misc.cpp | 34 +++++++++++++++---- + src/gallium/auxiliary/gallivm/lp_bld_misc.h | 3 ++ + 3 files changed, 38 insertions(+), 8 deletions(-) + +diff --git a/src/gallium/auxiliary/gallivm/lp_bld_init.c b/src/gallium/auxiliary/gallivm/lp_bld_init.c +index e866e46..228cfbf 100644 +--- a/src/gallium/auxiliary/gallivm/lp_bld_init.c ++++ b/src/gallium/auxiliary/gallivm/lp_bld_init.c +@@ -465,7 +465,14 @@ lp_build_init(void) + + if (util_get_cpu_caps()->has_avx2 || util_get_cpu_caps()->has_avx) { + lp_native_vector_width = 256; +- } else { ++ } else if (util_get_cpu_caps()->has_lasx) { ++#if defined(PIPE_ARCH_LOONGARCH64) ++ if (lp_probe_lasx()) ++ lp_native_vector_width = 256; ++ else ++#endif ++ lp_native_vector_width = 128; ++ } else { + /* Leave it at 128, even when no SIMD extensions are available. + * Really needs to be a multiple of 128 so can fit 4 floats. + */ +diff --git a/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp b/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp +index 9f9a3dd..2442740 100644 +--- a/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp ++++ b/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp +@@ -376,7 +376,7 @@ lp_build_create_jit_compiler_for_module(LLVMExecutionEngineRef *OutJIT, + + llvm::SmallVector MAttrs; + +-#if LLVM_VERSION_MAJOR >= 4 && (defined(PIPE_ARCH_X86) || defined(PIPE_ARCH_X86_64) || defined(PIPE_ARCH_ARM)) ++#if LLVM_VERSION_MAJOR >= 4 && (defined(PIPE_ARCH_X86) || defined(PIPE_ARCH_X86_64) || defined(PIPE_ARCH_ARM) || defined(PIPE_ARCH_LOONGARCH64)) + /* llvm-3.3+ implements sys::getHostCPUFeatures for Arm + * and llvm-3.7+ for x86, which allows us to enable/disable + * code generation based on the results of cpuid on these +@@ -481,12 +481,6 @@ lp_build_create_jit_compiler_for_module(LLVMExecutionEngineRef *OutJIT, + MAttrs.push_back("+ptr64"); + #endif + +-#if defined(PIPE_ARCH_LOONGARCH64) +-// Our llvm compilor is not ready for this now +-// MAttrs.push_back(util_get_cpu_caps()->has_lsx ? "+lsx" : "-lsx"); +-// MAttrs.push_back(util_get_cpu_caps()->has_lasx ? "+lasx" : "-lasx"); +-#endif +- + builder.setMAttrs(MAttrs); + + if (gallivm_debug & (GALLIVM_DEBUG_IR | GALLIVM_DEBUG_ASM | GALLIVM_DEBUG_DUMP_BC)) { +@@ -596,6 +590,32 @@ lp_build_create_jit_compiler_for_module(LLVMExecutionEngineRef *OutJIT, + } + + ++#if defined(PIPE_ARCH_LOONGARCH64) ++extern "C" ++LLVMBool ++lp_probe_lasx(void) ++{ ++ using namespace llvm; ++ /* our llvm-8+ implements sys::getHostCPUFeatures for loongarch, ++ * which allows us to enable/disable code generation based ++ * on the results of cpucfg. ++ */ ++ llvm::StringMap features; ++ llvm::sys::getHostCPUFeatures(features); ++ ++ for (StringMapIterator f = features.begin(); ++ f != features.end(); ++ ++f) { ++ ++ if ((*f).first() == "lasx" && (*f).second) ++ return 1; ++ } ++ ++ return 0; ++} ++#endif ++ ++ + extern "C" + void + lp_free_generated_code(struct lp_generated_code *code) +diff --git a/src/gallium/auxiliary/gallivm/lp_bld_misc.h b/src/gallium/auxiliary/gallivm/lp_bld_misc.h +index fa0ce90..f9eb530 100644 +--- a/src/gallium/auxiliary/gallivm/lp_bld_misc.h ++++ b/src/gallium/auxiliary/gallivm/lp_bld_misc.h +@@ -64,6 +64,9 @@ gallivm_dispose_target_library_info(LLVMTargetLibraryInfoRef library_info); + extern void + lp_set_target_options(void); + ++#if defined(PIPE_ARCH_LOONGARCH64) ++extern LLVMBool lp_probe_lasx(void); ++#endif + + extern int + lp_build_create_jit_compiler_for_module(LLVMExecutionEngineRef *OutJIT, +-- +2.27.0 + diff --git a/1012-num_L3_caches-happend-to-be-6-32-offset-now.patch b/1012-num_L3_caches-happend-to-be-6-32-offset-now.patch new file mode 100644 index 0000000000000000000000000000000000000000..fa66a5e3aec9a002b05bd3810d50147722cfa1f7 --- /dev/null +++ b/1012-num_L3_caches-happend-to-be-6-32-offset-now.patch @@ -0,0 +1,37 @@ +From 3e8e384880144559c75d22bafcc3e087fdb669fa Mon Sep 17 00:00:00 2001 +From: Liwei Ge +Date: Wed, 12 Oct 2022 15:35:31 +0800 +Subject: [PATCH 1012/1012] num_L3_caches happend to be 6 * 32 offset now + +--- + include/pci_ids/ls7a1000_pci_ids.h | 2 ++ + src/gallium/drivers/llvmpipe/lp_screen.c | 4 ++-- + 2 files changed, 4 insertions(+), 2 deletions(-) + create mode 100644 include/pci_ids/ls7a1000_pci_ids.h + +diff --git a/include/pci_ids/ls7a1000_pci_ids.h b/include/pci_ids/ls7a1000_pci_ids.h +new file mode 100644 +index 0000000..22a57cf +--- /dev/null ++++ b/include/pci_ids/ls7a1000_pci_ids.h +@@ -0,0 +1,2 @@ ++CHIPSET(0x7A15, GC1000, LOONGSON) ++CHIPSET(0x7A06, DC, LOONGSON) +diff --git a/src/gallium/drivers/llvmpipe/lp_screen.c b/src/gallium/drivers/llvmpipe/lp_screen.c +index 839902b..c1ce1cf 100644 +--- a/src/gallium/drivers/llvmpipe/lp_screen.c ++++ b/src/gallium/drivers/llvmpipe/lp_screen.c +@@ -897,8 +897,8 @@ static void update_cache_sha1_cpu(struct mesa_sha1 *ctx) + * Don't need the cpu cache affinity stuff. The rest + * is contained in first 5 dwords. + */ +- STATIC_ASSERT(offsetof(struct util_cpu_caps_t, num_L3_caches) == 5 * sizeof(uint32_t)); +- _mesa_sha1_update(ctx, cpu_caps, 5 * sizeof(uint32_t)); ++ STATIC_ASSERT(offsetof(struct util_cpu_caps_t, num_L3_caches) == 6 * sizeof(uint32_t)); ++ _mesa_sha1_update(ctx, cpu_caps, 6 * sizeof(uint32_t)); + } + + static void lp_disk_cache_create(struct llvmpipe_screen *screen) +-- +2.27.0 + diff --git a/mesa.spec b/mesa.spec index fcf33902931f5910047ff9a6e871489e7939427f..6cf546fe6ebd990c5b2ba4ce347d8e2f24bcdfd1 100644 --- a/mesa.spec +++ b/mesa.spec @@ -63,6 +63,21 @@ Patch0: lavapipe-disable-env-var.patch # https://bugzilla.redhat.com/show_bug.cgi?id=2040771 Patch0001: 0001-iris-implement-inter-context-busy-tracking.patch + +Patch1000: 1000-gallium-llvmpipe-pass-MCPU-mips64r2-to-LLVM-on-mips.patch +Patch1001: 1001-gallivm-Return-true-from-arch_rounding_available-if-.patch +Patch1002: 1002-gallivm-add-more-optlevel-for-debug-purpose-on-mips6.patch +Patch1003: 1003-disable-madd4-on-mips64.patch +Patch1004: 1004-kmsro-Extend-to-include-loongson-drm-support.patch +Patch1005: 1005-meson-add-loongarch64-build-support.patch +Patch1006: 1006-gallivm-temporary-disable-coroutines-on-loongarch64-.patch +Patch1007: 1007-gallivm-detect-loongarch-lsx-and-lasx-instruction-se.patch +Patch1008: 1008-gallivm-arit-use-LLVMBuildFPToUI-when-the-float-is-n.patch +Patch1009: 1009-gallivm-disable-use-lp_build_round_arch-on-default.patch +Patch1010: 1010-gallivm-add-more-optlevel-for-debuging-perpose-on.patch +Patch1011: 1011-gallivm-enable-lsx-and-lasx-on-loongarch-when-LLVM-e.patch +Patch1012: 1012-num_L3_caches-happend-to-be-6-32-offset-now.patch + BuildRequires: gcc BuildRequires: gcc-c++ @@ -553,6 +568,9 @@ done %endif %changelog +* Wed Oct 12 2022 Liwei Ge - 21.3.4-1.0.2 +- Support loongarch64 + * Sun Apr 24 2022 Bo Ren - 21.3.4-1.0.1 - Rebuild with llvm13