From be6d1e41e58d58fbf27451fca96ed69f049e0f71 Mon Sep 17 00:00:00 2001 From: Liwei Ge Date: Wed, 5 Jan 2022 17:45:18 +0800 Subject: [PATCH 1/2] dri: support loongarch64 platform Signed-off-by: Liwei Ge --- ...e-pass-MCPU-mips64r2-to-LLVM-on-mips.patch | 171 ++++++++++++++++++ ...rue-from-arch_rounding_available-if-.patch | 59 ++++++ ...fix-coroutines-on-mips64-with-llvm-8.patch | 53 ++++++ ...-optlevel-for-debug-purpose-on-mips6.patch | 68 +++++++ 0006-disable-madd4-on-mips64.patch | 27 +++ 0007-meson-add-mips-asm-flags.patch | 28 +++ ...tend-to-include-loongson-drm-support.patch | 85 +++++++++ ...-meson-add-loongarch64-build-support.patch | 47 +++++ ...y-disable-coroutines-on-loongarch64-.patch | 53 ++++++ ...oongarch-lsx-and-lasx-instruction-se.patch | 159 ++++++++++++++++ ...k-add-mips-platform-specific-symbols.patch | 35 ++++ ...-LLVMBuildFPToUI-when-the-float-is-n.patch | 29 +++ ...e-use-lp_build_round_arch-on-default.patch | 72 ++++++++ ...-optlevel-for-debuging-perpose-on-mi.patch | 74 ++++++++ ...sx-and-lasx-on-loongarch-when-LLVM-e.patch | 119 ++++++++++++ mesa.spec | 22 ++- 16 files changed, 1100 insertions(+), 1 deletion(-) create mode 100644 0002-gallium-llvmpipe-pass-MCPU-mips64r2-to-LLVM-on-mips.patch create mode 100644 0003-gallivm-Return-true-from-arch_rounding_available-if-.patch create mode 100644 0004-gallivm-fix-coroutines-on-mips64-with-llvm-8.patch create mode 100644 0005-gallivm-add-more-optlevel-for-debug-purpose-on-mips6.patch create mode 100644 0006-disable-madd4-on-mips64.patch create mode 100644 0007-meson-add-mips-asm-flags.patch create mode 100644 0008-kmsro-Extend-to-include-loongson-drm-support.patch create mode 100644 0009-meson-add-loongarch64-build-support.patch create mode 100644 0010-gallivm-temporary-disable-coroutines-on-loongarch64-.patch create mode 100644 0011-gallivm-detect-loongarch-lsx-and-lasx-instruction-se.patch create mode 100644 0012-symbols-check-add-mips-platform-specific-symbols.patch create mode 100644 0013-gallivm-arit-use-LLVMBuildFPToUI-when-the-float-is-n.patch create mode 100644 0014-gallivm-disable-use-lp_build_round_arch-on-default.patch create mode 100644 0015-gallivm-add-more-optlevel-for-debuging-perpose-on-mi.patch create mode 100644 0016-gallivm-enable-lsx-and-lasx-on-loongarch-when-LLVM-e.patch diff --git a/0002-gallium-llvmpipe-pass-MCPU-mips64r2-to-LLVM-on-mips.patch b/0002-gallium-llvmpipe-pass-MCPU-mips64r2-to-LLVM-on-mips.patch new file mode 100644 index 0000000..e8b7846 --- /dev/null +++ b/0002-gallium-llvmpipe-pass-MCPU-mips64r2-to-LLVM-on-mips.patch @@ -0,0 +1,171 @@ +From 232aecf040e696c281c1f5f8b1ce141a1955030c Mon Sep 17 00:00:00 2001 +From: suijingfeng +Date: Fri, 30 Apr 2021 00:16:39 +0800 +Subject: [PATCH 02/16] gallium: llvmpipe: pass MCPU = "mips64r2" to LLVM on + mips + +According to LLVM, the MSA SIMD requires MIPS64 revision 5 or greater, +but MSA instruction set is actually implemented on ls3a4000. + +This patch add support to detect if MSA is available, and force to enable +MSA SIMD on LS3A4000 CPU. So we override the MCPU to mips64r5 if MSA is +implemented, feedback to mips64r2 for all other ordinaries. + +Otherwise, it complains when running 3D application: + +'generic' is not a recognized processor for this target (ignoring processor) +'generic' is not a recognized processor for this target (ignoring processor) +... +'generic' is not a recognized processor for this target (ignoring processor) +'generic' is not a recognized processor for this target (ignoring processor + +see: + [1] http://huonw.github.io/llvmint/llvmint/mips/index.html + [2] https://gitlab.freedesktop.org/mesa/mesa/-/commit/385ee7c3d0536424eb9822fe873d4410b831cbfe + +Signed-off-by: suijingfeng +--- + src/gallium/auxiliary/gallivm/lp_bld_misc.cpp | 34 +++++++++++++++++++ + src/gallium/include/pipe/p_config.h | 6 ++++ + src/util/u_cpu_detect.c | 29 ++++++++++++++++ + src/util/u_cpu_detect.h | 1 + + 4 files changed, 70 insertions(+) + +diff --git a/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp b/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp +index df7196190c5..334269941b1 100644 +--- a/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp ++++ b/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp +@@ -433,6 +433,17 @@ lp_build_create_jit_compiler_for_module(LLVMExecutionEngineRef *OutJIT, + #endif + #endif + ++#if defined(PIPE_ARCH_MIPS64) ++ /* MSA requires a 64-bit FPU register file */ ++ MAttrs.push_back(util_cpu_caps.has_msa ? "+msa" : "-msa"); ++ /* Support 64-bit FP registers. */ ++ MAttrs.push_back("+fp64"); ++ /* General Purpose Registers are 64-bit wide */ ++ MAttrs.push_back("+gp64"); ++ /* Pointers are 64-bit wide */ ++ MAttrs.push_back("+ptr64"); ++#endif ++ + builder.setMAttrs(MAttrs); + + if (gallivm_debug & (GALLIVM_DEBUG_IR | GALLIVM_DEBUG_ASM | GALLIVM_DEBUG_DUMP_BC)) { +@@ -485,6 +496,29 @@ lp_build_create_jit_compiler_for_module(LLVMExecutionEngineRef *OutJIT, + MCPU = "pwr8"; + #endif + #endif ++ ++#if defined(PIPE_ARCH_MIPS64) ++ /* ++ * LS3A4000 and LS2K1000 is mips64r5 compatible and MSA SIMD instruction ++ * set, while LS3A3000 is mips64r2 compatible only. ++ * ++ * Due to lacking llvm support for loongson CPU, llvm::sys::getHostCPUName(). ++ * return "generic" on all loongson mips CPU. So we feedback to mips64r2 ++ * If llvm::sys::getHostCPUName() failed to return a name. This is true ++ * for community released llvm. ++ * ++ * However, loongson maintained llvm 8 return loongson3a on all loongson ++ * MIPS cpu(including ls3a4000, ls3a3000, ...). This is bad, ls3a4000 is ++ * mips64r5, ls3a3000 is mips64r2. ++ * we set the MCPU type to mips64r5 in order to MSA SIMD can be used on ++ * ls3a4000. ++ */ ++ if (MCPU == "generic") ++ MCPU = util_cpu_caps.has_msa ? "mips64r5" : "mips64r2"; ++ else if (MCPU == "loongson3a") ++ MCPU = util_cpu_caps.has_msa ? "mips64r5" : "mips64r2"; ++#endif ++ + builder.setMCPU(MCPU); + if (gallivm_debug & (GALLIVM_DEBUG_IR | GALLIVM_DEBUG_ASM | GALLIVM_DEBUG_DUMP_BC)) { + debug_printf("llc -mcpu option: %s\n", MCPU.str().c_str()); +diff --git a/src/gallium/include/pipe/p_config.h b/src/gallium/include/pipe/p_config.h +index 2c1698d0e9c..bf7cc217e85 100644 +--- a/src/gallium/include/pipe/p_config.h ++++ b/src/gallium/include/pipe/p_config.h +@@ -122,6 +122,12 @@ + #define PIPE_ARCH_AARCH64 + #endif + ++#if defined(__mips64) && defined(__LP64__) ++#define PIPE_ARCH_MIPS64 ++#elif defined(__mips__) ++#define PIPE_ARCH_MIPS ++#endif ++ + /* + * Endian detection. + */ +diff --git a/src/util/u_cpu_detect.c b/src/util/u_cpu_detect.c +index ab064957382..3187ecac094 100644 +--- a/src/util/u_cpu_detect.c ++++ b/src/util/u_cpu_detect.c +@@ -429,6 +429,30 @@ check_os_arm_support(void) + } + #endif /* PIPE_ARCH_ARM || PIPE_ARCH_AARCH64 */ + ++#if defined(PIPE_ARCH_MIPS64) ++static void ++check_os_mips64_support(void) ++{ ++#if defined(PIPE_OS_LINUX) ++ Elf64_auxv_t aux; ++ int fd; ++ ++ fd = open("/proc/self/auxv", O_RDONLY | O_CLOEXEC); ++ if (fd >= 0) { ++ while (read(fd, &aux, sizeof(Elf64_auxv_t)) == sizeof(Elf64_auxv_t)) { ++ if (aux.a_type == AT_HWCAP) { ++ uint64_t hwcap = aux.a_un.a_val; ++ ++ util_cpu_caps.has_msa = (hwcap >> 1) & 1; ++ break; ++ } ++ } ++ close (fd); ++ } ++#endif /* PIPE_OS_LINUX */ ++} ++#endif ++ + static void + get_cpu_topology(void) + { +@@ -600,6 +624,10 @@ util_cpu_detect_once(void) + check_os_arm_support(); + #endif + ++#if defined(PIPE_ARCH_MIPS64) ++ check_os_mips64_support(); ++#endif ++ + #if defined(PIPE_ARCH_PPC) + check_os_altivec_support(); + #endif /* PIPE_ARCH_PPC */ +@@ -633,6 +661,7 @@ util_cpu_detect_once(void) + debug_printf("util_cpu_caps.has_vsx = %u\n", util_cpu_caps.has_vsx); + debug_printf("util_cpu_caps.has_neon = %u\n", util_cpu_caps.has_neon); + debug_printf("util_cpu_caps.has_daz = %u\n", util_cpu_caps.has_daz); ++ debug_printf("util_cpu_caps.has_msa = %u\n", util_cpu_caps.has_msa); + debug_printf("util_cpu_caps.has_avx512f = %u\n", util_cpu_caps.has_avx512f); + debug_printf("util_cpu_caps.has_avx512dq = %u\n", util_cpu_caps.has_avx512dq); + debug_printf("util_cpu_caps.has_avx512ifma = %u\n", util_cpu_caps.has_avx512ifma); +diff --git a/src/util/u_cpu_detect.h b/src/util/u_cpu_detect.h +index a09aca8fbac..6d53b5af121 100644 +--- a/src/util/u_cpu_detect.h ++++ b/src/util/u_cpu_detect.h +@@ -74,6 +74,7 @@ struct util_cpu_caps { + unsigned has_vsx:1; + unsigned has_daz:1; + unsigned has_neon:1; ++ unsigned has_msa:1; + + unsigned has_avx512f:1; + unsigned has_avx512dq:1; +-- +2.27.0 + diff --git a/0003-gallivm-Return-true-from-arch_rounding_available-if-.patch b/0003-gallivm-Return-true-from-arch_rounding_available-if-.patch new file mode 100644 index 0000000..7c2b501 --- /dev/null +++ b/0003-gallivm-Return-true-from-arch_rounding_available-if-.patch @@ -0,0 +1,59 @@ +From 2440bb2a3bea1e798332c4f28e878d5bd2a2abed Mon Sep 17 00:00:00 2001 +From: suijingfeng +Date: Thu, 13 May 2021 15:56:59 +0800 +Subject: [PATCH 03/16] gallivm: Return true from arch_rounding_available() if + MSA is available + +LLVM uses the single instruction "FRINTI" to implement llvm.nearbyint. +Fix the rounding test of lp_test_arit. + +See upstream patches and bug for reference: + [1] https://gitlab.freedesktop.org/mesa/mesa/-/commit/70a7ece035785978167fe0019b6ff603415b1f3b + [2] https://bugs.gentoo.org/665570 + +Signed-off-by: Weining Lu +Signed-off-by: suijingfeng +--- + src/gallium/auxiliary/gallivm/lp_bld_arit.c | 5 ++++- + src/gallium/drivers/llvmpipe/lp_test_arit.c | 2 +- + 2 files changed, 5 insertions(+), 2 deletions(-) + +diff --git a/src/gallium/auxiliary/gallivm/lp_bld_arit.c b/src/gallium/auxiliary/gallivm/lp_bld_arit.c +index 53ee00e6767..e81910a8ae6 100644 +--- a/src/gallium/auxiliary/gallivm/lp_bld_arit.c ++++ b/src/gallium/auxiliary/gallivm/lp_bld_arit.c +@@ -1907,6 +1907,9 @@ arch_rounding_available(const struct lp_type type) + return TRUE; + else if (util_get_cpu_caps()->has_neon) + return TRUE; ++ else if (util_get_cpu_caps()->has_msa && ++ (type.width * type.length == 128)) ++ return TRUE; + + return FALSE; + } +@@ -2011,7 +2014,7 @@ lp_build_round_arch(struct lp_build_context *bld, + LLVMValueRef a, + enum lp_build_round_mode mode) + { +- if (util_get_cpu_caps()->has_sse4_1 || util_get_cpu_caps()->has_neon) { ++ if (util_get_cpu_caps()->has_sse4_1 || util_get_cpu_caps()->has_neon || util_get_cpu_caps()->has_msa) { + LLVMBuilderRef builder = bld->gallivm->builder; + const struct lp_type type = bld->type; + const char *intrinsic_root; +diff --git a/src/gallium/drivers/llvmpipe/lp_test_arit.c b/src/gallium/drivers/llvmpipe/lp_test_arit.c +index 184e50089f7..9ec24145e9b 100644 +--- a/src/gallium/drivers/llvmpipe/lp_test_arit.c ++++ b/src/gallium/drivers/llvmpipe/lp_test_arit.c +@@ -458,7 +458,7 @@ test_unary(unsigned verbose, FILE *fp, const struct unary_test_t *test, unsigned + continue; + } + +- if (!util_get_cpu_caps()->has_neon && ++ if (!util_get_cpu_caps()->has_neon && !util_get_cpu_caps()->has_msa && + test->ref == &nearbyintf && length == 2 && + ref != roundf(testval)) { + /* FIXME: The generic (non SSE) path in lp_build_iround, which is +-- +2.27.0 + diff --git a/0004-gallivm-fix-coroutines-on-mips64-with-llvm-8.patch b/0004-gallivm-fix-coroutines-on-mips64-with-llvm-8.patch new file mode 100644 index 0000000..00efef0 --- /dev/null +++ b/0004-gallivm-fix-coroutines-on-mips64-with-llvm-8.patch @@ -0,0 +1,53 @@ +From 060e687b26681a31946c25c2ba720f89eceefc42 Mon Sep 17 00:00:00 2001 +From: suijingfeng +Date: Fri, 9 Jul 2021 14:45:17 +0800 +Subject: [PATCH 04/16] gallivm: fix coroutines on mips64 with llvm 8 + +The coroutine split pass is missing a dependency before LLVM 9.0, +and fails to initialise properly if the CallGraphWrapperPass hasn't +be initialised earlier (x86 does it due to some of it's passes +requiring it). + +This is a workaround for llvm 8 (coroutines are only supported in 8 +and higher). It adds another pass that has a dependency on the pass +the coroutines split requires. This pass shouldn't have any raal +effects. + +Fixes: d32690b4 + + (gallivm: add coroutine pass manager support) + +See also: + +[1] https://gitlab.freedesktop.org/mesa/mesa/-/commit/f59ff014b199af118ac9b90e3a67f15f4c37110e + +Signed-off-by: suijingfeng +--- + src/gallium/auxiliary/gallivm/lp_bld_init.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/src/gallium/auxiliary/gallivm/lp_bld_init.c b/src/gallium/auxiliary/gallivm/lp_bld_init.c +index e3fd26cd2ec..1731c2d7d4e 100644 +--- a/src/gallium/auxiliary/gallivm/lp_bld_init.c ++++ b/src/gallium/auxiliary/gallivm/lp_bld_init.c +@@ -46,7 +46,7 @@ + #endif + #include + #if GALLIVM_HAVE_CORO +-#if LLVM_VERSION_MAJOR <= 8 && (defined(PIPE_ARCH_AARCH64) || defined (PIPE_ARCH_ARM) || defined(PIPE_ARCH_S390)) ++#if LLVM_VERSION_MAJOR <= 8 && (defined(PIPE_ARCH_AARCH64) || defined (PIPE_ARCH_ARM) || defined(PIPE_ARCH_S390) || defined(PIPE_ARCH_MIPS64)) + #include + #endif + #include +@@ -137,7 +137,7 @@ create_pass_manager(struct gallivm_state *gallivm) + } + + #if GALLIVM_HAVE_CORO +-#if LLVM_VERSION_MAJOR <= 8 && (defined(PIPE_ARCH_AARCH64) || defined (PIPE_ARCH_ARM) || defined(PIPE_ARCH_S390)) ++#if LLVM_VERSION_MAJOR <= 8 && (defined(PIPE_ARCH_AARCH64) || defined (PIPE_ARCH_ARM) || defined(PIPE_ARCH_S390) || defined(PIPE_ARCH_MIPS64)) + LLVMAddArgumentPromotionPass(gallivm->cgpassmgr); + LLVMAddFunctionAttrsPass(gallivm->cgpassmgr); + #endif +-- +2.27.0 + diff --git a/0005-gallivm-add-more-optlevel-for-debug-purpose-on-mips6.patch b/0005-gallivm-add-more-optlevel-for-debug-purpose-on-mips6.patch new file mode 100644 index 0000000..ceb1dcd --- /dev/null +++ b/0005-gallivm-add-more-optlevel-for-debug-purpose-on-mips6.patch @@ -0,0 +1,68 @@ +From c0b4b0b26a11bb2c13f3a1bd0cdefe9bfc92c02d Mon Sep 17 00:00:00 2001 +From: suijingfeng +Date: Fri, 9 Jul 2021 15:25:06 +0800 +Subject: [PATCH 05/16] gallivm: add more optlevel for debug purpose on mips64 + +This patch also set the default optlevel to None as enable shader +compiling optimization on ls3a4000 is still problematic. + +Signed-off-by: suijingfeng +--- + src/gallium/auxiliary/gallivm/lp_bld_debug.h | 6 ++++++ + src/gallium/auxiliary/gallivm/lp_bld_init.c | 16 ++++++++++++++++ + 2 files changed, 22 insertions(+) + +diff --git a/src/gallium/auxiliary/gallivm/lp_bld_debug.h b/src/gallium/auxiliary/gallivm/lp_bld_debug.h +index 1ea13326458..592da0b5180 100644 +--- a/src/gallium/auxiliary/gallivm/lp_bld_debug.h ++++ b/src/gallium/auxiliary/gallivm/lp_bld_debug.h +@@ -49,6 +49,12 @@ + #define GALLIVM_PERF_NO_OPT (1 << 3) + #define GALLIVM_PERF_NO_AOS_SAMPLING (1 << 4) + ++#if defined(PIPE_ARCH_MIPS64) ++#define GALLIVM_PERF_OPT_O1 (1 << 5) ++#define GALLIVM_PERF_OPT_O2 (1 << 6) ++#define GALLIVM_PERF_OPT_O3 (1 << 7) ++#endif ++ + #ifdef __cplusplus + extern "C" { + #endif +diff --git a/src/gallium/auxiliary/gallivm/lp_bld_init.c b/src/gallium/auxiliary/gallivm/lp_bld_init.c +index 1731c2d7d4e..c365e6e88a6 100644 +--- a/src/gallium/auxiliary/gallivm/lp_bld_init.c ++++ b/src/gallium/auxiliary/gallivm/lp_bld_init.c +@@ -62,6 +62,11 @@ static const struct debug_named_value lp_bld_perf_flags[] = { + { "nopt", GALLIVM_PERF_NO_OPT, "disable optimization passes to speed up shader compilation" }, + { "no_filter_hacks", GALLIVM_PERF_NO_BRILINEAR | GALLIVM_PERF_NO_RHO_APPROX | + GALLIVM_PERF_NO_QUAD_LOD, "disable filter optimization hacks" }, ++#if defined(PIPE_ARCH_MIPS64) ++ { "o3", GALLIVM_PERF_OPT_O3, "enable aggressive optimization passes" }, ++ { "o2", GALLIVM_PERF_OPT_O2, "enable medium optimization passes" }, ++ { "o1", GALLIVM_PERF_OPT_O1, "enable less optimization passes" }, ++#endif + DEBUG_NAMED_VALUE_END + }; + +@@ -263,6 +268,17 @@ init_gallivm_engine(struct gallivm_state *gallivm) + optlevel = Default; + } + ++#if defined(PIPE_ARCH_MIPS64) ++ if (gallivm_perf & GALLIVM_PERF_OPT_O3) ++ optlevel = Aggressive; ++ else if (gallivm_perf & GALLIVM_PERF_OPT_O2) ++ optlevel = Default; ++ else if (gallivm_perf & GALLIVM_PERF_OPT_O1) ++ optlevel = Less; ++ else ++ optlevel = None; ++#endif ++ + ret = lp_build_create_jit_compiler_for_module(&gallivm->engine, + &gallivm->code, + gallivm->cache, +-- +2.27.0 + diff --git a/0006-disable-madd4-on-mips64.patch b/0006-disable-madd4-on-mips64.patch new file mode 100644 index 0000000..27c1325 --- /dev/null +++ b/0006-disable-madd4-on-mips64.patch @@ -0,0 +1,27 @@ +From cffa827f78b51faaef04fde02dc41a76e63c9846 Mon Sep 17 00:00:00 2001 +From: suijingfeng +Date: Sat, 10 Jul 2021 23:09:11 +0800 +Subject: [PATCH 06/16] disable madd4 on mips64 + +--- + src/gallium/auxiliary/gallivm/lp_bld_init.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/src/gallium/auxiliary/gallivm/lp_bld_init.c b/src/gallium/auxiliary/gallivm/lp_bld_init.c +index c365e6e88a6..abd641db496 100644 +--- a/src/gallium/auxiliary/gallivm/lp_bld_init.c ++++ b/src/gallium/auxiliary/gallivm/lp_bld_init.c +@@ -620,6 +620,10 @@ gallivm_compile_module(struct gallivm_state *gallivm) + LLVMAddTargetDependentFunctionAttr(func, "no-frame-pointer-elim-non-leaf", "true"); + #endif + ++#if defined(PIPE_ARCH_MIPS64) ++ LLVMAddTargetDependentFunctionAttr(func, "target-features", "+nomadd4"); ++#endif ++ + LLVMRunFunctionPassManager(gallivm->passmgr, func); + func = LLVMGetNextFunction(func); + } +-- +2.27.0 + diff --git a/0007-meson-add-mips-asm-flags.patch b/0007-meson-add-mips-asm-flags.patch new file mode 100644 index 0000000..738c289 --- /dev/null +++ b/0007-meson-add-mips-asm-flags.patch @@ -0,0 +1,28 @@ +From 8ccd22a9b506abd63ed4901d19c072c67404458b Mon Sep 17 00:00:00 2001 +From: suijingfeng +Date: Sun, 11 Jul 2021 01:01:56 +0800 +Subject: [PATCH 07/16] meson: add mips asm flags + +--- + meson.build | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/meson.build b/meson.build +index af6d195b5c3..0e4dfb22bc4 100644 +--- a/meson.build ++++ b/meson.build +@@ -1145,6 +1145,11 @@ elif host_machine.cpu_family().startswith('ppc64') and host_machine.endian() == + with_asm_arch = 'ppc64le' + pre_args += ['-DUSE_PPC64LE_ASM'] + endif ++elif host_machine.cpu_family() == 'mips64' and host_machine.endian() == 'little' ++ if system_has_kms_drm ++ with_asm_arch = 'mips64el' ++ pre_args += ['-DUSE_MIPS64EL_ASM'] ++ endif + endif + + # Check for standard headers and functions +-- +2.27.0 + diff --git a/0008-kmsro-Extend-to-include-loongson-drm-support.patch b/0008-kmsro-Extend-to-include-loongson-drm-support.patch new file mode 100644 index 0000000..9ab5b95 --- /dev/null +++ b/0008-kmsro-Extend-to-include-loongson-drm-support.patch @@ -0,0 +1,85 @@ +From d50cdbfe5d751b64a132e982d44cf3b7bdb8ff50 Mon Sep 17 00:00:00 2001 +From: suijingfeng +Date: Sun, 11 Jul 2021 02:25:10 +0800 +Subject: [PATCH 08/16] kmsro: Extend to include loongson-drm support + +This enables Mesa to work with Loongson SoCs through the use of the +loongson-drm modesetting driver along with the render-only drivers, +such as Etnaviv on the LS2K1000 SoC and LS7A1000 bridge. + +GC1000 in LS7A1000 north bridge is a PCI device, its PCI device id +is 0x7a15, 0x0014 is vendor id of Loongson coporation. + +LS7A1000 north bridge also have a display controller intergrated, +its PCI device id is 0x7a06. + +Signed-off-by: suijingfeng +--- + include/pci_ids/ls7a1000_pci_ids.h | 2 ++ + src/gallium/targets/dri/meson.build | 1 + + src/gallium/targets/dri/target.c | 1 + + src/loader/pci_id_driver_map.h | 8 ++++++++ + 4 files changed, 12 insertions(+) + create mode 100644 include/pci_ids/ls7a1000_pci_ids.h + +diff --git a/include/pci_ids/ls7a1000_pci_ids.h b/include/pci_ids/ls7a1000_pci_ids.h +new file mode 100644 +index 00000000000..22a57cffae0 +--- /dev/null ++++ b/include/pci_ids/ls7a1000_pci_ids.h +@@ -0,0 +1,2 @@ ++CHIPSET(0x7A15, GC1000, LOONGSON) ++CHIPSET(0x7A06, DC, LOONGSON) +diff --git a/src/gallium/targets/dri/meson.build b/src/gallium/targets/dri/meson.build +index 8da21b3394a..3751c1d4925 100644 +--- a/src/gallium/targets/dri/meson.build ++++ b/src/gallium/targets/dri/meson.build +@@ -74,6 +74,7 @@ foreach d : [[with_gallium_kmsro, [ + 'imx-drm_dri.so', + 'imx-dcss_dri.so', + 'ingenic-drm_dri.so', ++ 'loongson-drm_dri.so', + 'mcde_dri.so', + 'mediatek_dri.so', + 'meson_dri.so', +diff --git a/src/gallium/targets/dri/target.c b/src/gallium/targets/dri/target.c +index f71f690a70e..f36ec8c76df 100644 +--- a/src/gallium/targets/dri/target.c ++++ b/src/gallium/targets/dri/target.c +@@ -99,6 +99,7 @@ DEFINE_LOADER_DRM_ENTRYPOINT(ili9225) + DEFINE_LOADER_DRM_ENTRYPOINT(imx_drm) + DEFINE_LOADER_DRM_ENTRYPOINT(imx_dcss) + DEFINE_LOADER_DRM_ENTRYPOINT(ingenic_drm) ++DEFINE_LOADER_DRM_ENTRYPOINT(loongson_drm) + DEFINE_LOADER_DRM_ENTRYPOINT(mcde) + DEFINE_LOADER_DRM_ENTRYPOINT(mediatek) + DEFINE_LOADER_DRM_ENTRYPOINT(meson) +diff --git a/src/loader/pci_id_driver_map.h b/src/loader/pci_id_driver_map.h +index 1dc07be390c..708cb091773 100644 +--- a/src/loader/pci_id_driver_map.h ++++ b/src/loader/pci_id_driver_map.h +@@ -56,6 +56,13 @@ static const int vmwgfx_chip_ids[] = { + #undef CHIPSET + }; + ++static const int ls7a_chip_ids[] = { ++#define CHIPSET(chip, name, family) chip, ++#include "pci_ids/ls7a1000_pci_ids.h" ++#undef CHIPSET ++}; ++ ++ + bool is_nouveau_vieux(int fd); + bool is_kernel_i915(int fd); + +@@ -76,6 +83,7 @@ static const struct { + { 0x1002, "radeonsi", NULL, -1 }, + { 0x10de, "nouveau_vieux", NULL, -1, is_nouveau_vieux }, + { 0x10de, "nouveau", NULL, -1, }, ++ { 0x0014, "loongson-drm", ls7a_chip_ids, ARRAY_SIZE(ls7a_chip_ids) }, + { 0x1af4, "virtio_gpu", virtio_gpu_chip_ids, ARRAY_SIZE(virtio_gpu_chip_ids) }, + { 0x15ad, "vmwgfx", vmwgfx_chip_ids, ARRAY_SIZE(vmwgfx_chip_ids) }, + }; +-- +2.27.0 + diff --git a/0009-meson-add-loongarch64-build-support.patch b/0009-meson-add-loongarch64-build-support.patch new file mode 100644 index 0000000..8910a43 --- /dev/null +++ b/0009-meson-add-loongarch64-build-support.patch @@ -0,0 +1,47 @@ +From bac2b443828f2a02fe4ba041337cf90d78cefb10 Mon Sep 17 00:00:00 2001 +From: suijingfeng +Date: Sun, 11 Jul 2021 04:23:59 +0800 +Subject: [PATCH 09/16] meson: add loongarch64 build support + +Signed-off-by: suijingfeng +--- + meson.build | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/meson.build b/meson.build +index 0e4dfb22bc4..b399d7632d7 100644 +--- a/meson.build ++++ b/meson.build +@@ -144,6 +144,8 @@ if dri_drivers.contains('auto') + dri_drivers = [] + elif ['mips', 'mips64'].contains(host_machine.cpu_family()) + dri_drivers = ['r100', 'r200', 'nouveau'] ++ elif ['loongarch64'].contains(host_machine.cpu_family()) ++ dri_drivers = [] + else + error('Unknown architecture @0@. Please pass -Ddri-drivers to set driver options. Patches gladly accepted to fix this.'.format( + host_machine.cpu_family())) +@@ -185,6 +187,11 @@ if gallium_drivers.contains('auto') + gallium_drivers = [ + 'r300', 'r600', 'radeonsi', 'nouveau', 'virgl', 'swrast' + ] ++ elif ['loongarch64'].contains(host_machine.cpu_family()) ++ gallium_drivers = [ ++ 'r300', 'r600', 'radeonsi', 'nouveau', 'etnaviv', 'kmsro', 'swrast', ++ 'virgl' ++ ] + else + error('Unknown architecture @0@. Please pass -Dgallium-drivers to set driver options. Patches gladly accepted to fix this.'.format( + host_machine.cpu_family())) +@@ -239,6 +246,8 @@ if _vulkan_drivers.contains('auto') + _vulkan_drivers = ['swrast'] + elif ['mips', 'mips64'].contains(host_machine.cpu_family()) + _vulkan_drivers = ['amd', 'swrast'] ++ elif ['loongarch64'].contains(host_machine.cpu_family()) ++ _vulkan_drivers = ['amd', 'swrast'] + else + error('Unknown architecture @0@. Please pass -Dvulkan-drivers to set driver options. Patches gladly accepted to fix this.'.format( + host_machine.cpu_family())) +-- +2.27.0 + diff --git a/0010-gallivm-temporary-disable-coroutines-on-loongarch64-.patch b/0010-gallivm-temporary-disable-coroutines-on-loongarch64-.patch new file mode 100644 index 0000000..e5d9b73 --- /dev/null +++ b/0010-gallivm-temporary-disable-coroutines-on-loongarch64-.patch @@ -0,0 +1,53 @@ +From ec10f895aadda824f67e6ac9e9bf02b8c009bc13 Mon Sep 17 00:00:00 2001 +From: suijingfeng +Date: Sun, 11 Jul 2021 06:12:17 +0800 +Subject: [PATCH 10/16] gallivm: temporary disable coroutines on loongarch64 + and mips64 + +Signed-off-by: suijingfeng +--- + src/gallium/auxiliary/gallivm/lp_bld.h | 4 ++++ + src/gallium/auxiliary/gallivm/lp_bld_init.c | 4 ++-- + 2 files changed, 6 insertions(+), 2 deletions(-) + +diff --git a/src/gallium/auxiliary/gallivm/lp_bld.h b/src/gallium/auxiliary/gallivm/lp_bld.h +index 9144428c8e1..2fd50ddda0b 100644 +--- a/src/gallium/auxiliary/gallivm/lp_bld.h ++++ b/src/gallium/auxiliary/gallivm/lp_bld.h +@@ -82,7 +82,11 @@ + #define LLVMCreateBuilder ILLEGAL_LLVM_FUNCTION + + #if LLVM_VERSION_MAJOR >= 8 ++#if defined(__loongarch__) || defined(__mips__) ++#define GALLIVM_HAVE_CORO 0 ++#else + #define GALLIVM_HAVE_CORO 1 ++#endif + #else + #define GALLIVM_HAVE_CORO 0 + #endif +diff --git a/src/gallium/auxiliary/gallivm/lp_bld_init.c b/src/gallium/auxiliary/gallivm/lp_bld_init.c +index abd641db496..1b1a28bbf6b 100644 +--- a/src/gallium/auxiliary/gallivm/lp_bld_init.c ++++ b/src/gallium/auxiliary/gallivm/lp_bld_init.c +@@ -46,7 +46,7 @@ + #endif + #include + #if GALLIVM_HAVE_CORO +-#if LLVM_VERSION_MAJOR <= 8 && (defined(PIPE_ARCH_AARCH64) || defined (PIPE_ARCH_ARM) || defined(PIPE_ARCH_S390) || defined(PIPE_ARCH_MIPS64)) ++#if LLVM_VERSION_MAJOR <= 8 && (defined(PIPE_ARCH_AARCH64) || defined (PIPE_ARCH_ARM) || defined(PIPE_ARCH_S390) || defined(PIPE_ARCH_MIPS64) || defined(PIPE_ARCH_LOONGARCH64)) + #include + #endif + #include +@@ -142,7 +142,7 @@ create_pass_manager(struct gallivm_state *gallivm) + } + + #if GALLIVM_HAVE_CORO +-#if LLVM_VERSION_MAJOR <= 8 && (defined(PIPE_ARCH_AARCH64) || defined (PIPE_ARCH_ARM) || defined(PIPE_ARCH_S390) || defined(PIPE_ARCH_MIPS64)) ++#if LLVM_VERSION_MAJOR <= 8 && (defined(PIPE_ARCH_AARCH64) || defined (PIPE_ARCH_ARM) || defined(PIPE_ARCH_S390) || defined(PIPE_ARCH_MIPS64) || defined(PIPE_ARCH_LOONGARCH64)) + LLVMAddArgumentPromotionPass(gallivm->cgpassmgr); + LLVMAddFunctionAttrsPass(gallivm->cgpassmgr); + #endif +-- +2.27.0 + diff --git a/0011-gallivm-detect-loongarch-lsx-and-lasx-instruction-se.patch b/0011-gallivm-detect-loongarch-lsx-and-lasx-instruction-se.patch new file mode 100644 index 0000000..567b791 --- /dev/null +++ b/0011-gallivm-detect-loongarch-lsx-and-lasx-instruction-se.patch @@ -0,0 +1,159 @@ +From 7a6f3277da59d4847c2d06c808e693d61f1a1797 Mon Sep 17 00:00:00 2001 +From: suijingfeng +Date: Sun, 11 Jul 2021 08:04:43 +0800 +Subject: [PATCH 11/16] gallivm: detect loongarch lsx and lasx instruction set + +Signed-off-by: suijingfeng +--- + src/gallium/auxiliary/gallivm/lp_bld_arit.c | 9 +++++- + src/gallium/auxiliary/gallivm/lp_bld_misc.cpp | 11 +++++++ + src/gallium/include/pipe/p_config.h | 6 ++++ + src/util/u_cpu_detect.c | 31 +++++++++++++++++++ + src/util/u_cpu_detect.h | 2 ++ + 5 files changed, 58 insertions(+), 1 deletion(-) + +diff --git a/src/gallium/auxiliary/gallivm/lp_bld_arit.c b/src/gallium/auxiliary/gallivm/lp_bld_arit.c +index e81910a8ae6..b99be32fda2 100644 +--- a/src/gallium/auxiliary/gallivm/lp_bld_arit.c ++++ b/src/gallium/auxiliary/gallivm/lp_bld_arit.c +@@ -1907,6 +1907,12 @@ arch_rounding_available(const struct lp_type type) + else if (util_get_cpu_caps()->has_msa && + (type.width * type.length == 128)) + return TRUE; ++ else if (util_get_cpu_caps()->has_lsx && ++ (type.width * type.length == 128)) ++ return TRUE; ++ else if (util_get_cpu_caps()->has_lasx && ++ (type.width * type.length == 256)) ++ return TRUE; + + return FALSE; + } +@@ -2014,7 +2020,8 @@ lp_build_round_arch(struct lp_build_context *bld, + LLVMValueRef a, + enum lp_build_round_mode mode) + { +- if (util_get_cpu_caps()->has_sse4_1 || util_get_cpu_caps()->has_neon || util_get_cpu_caps()->has_msa) { ++ if (util_get_cpu_caps()->has_sse4_1 || util_get_cpu_caps()->has_neon || util_get_cpu_caps()->has_msa ++ || util_get_cpu_caps()->has_lsx || util_get_cpu_caps()->has_lasx) { + LLVMBuilderRef builder = bld->gallivm->builder; + const struct lp_type type = bld->type; + const char *intrinsic_root; +diff --git a/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp b/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp +index 334269941b1..4b75c933263 100644 +--- a/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp ++++ b/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp +@@ -444,6 +444,12 @@ lp_build_create_jit_compiler_for_module(LLVMExecutionEngineRef *OutJIT, + MAttrs.push_back("+ptr64"); + #endif + ++#if defined(PIPE_ARCH_LOONGARCH64) ++// Our llvm compilor is not ready for this now ++// MAttrs.push_back(util_get_cpu_caps()->has_lsx ? "+lsx" : "-lsx"); ++// MAttrs.push_back(util_get_cpu_caps()->has_lasx ? "+lasx" : "-lasx"); ++#endif ++ + builder.setMAttrs(MAttrs); + + if (gallivm_debug & (GALLIVM_DEBUG_IR | GALLIVM_DEBUG_ASM | GALLIVM_DEBUG_DUMP_BC)) { +@@ -519,6 +525,11 @@ lp_build_create_jit_compiler_for_module(LLVMExecutionEngineRef *OutJIT, + MCPU = util_cpu_caps.has_msa ? "mips64r5" : "mips64r2"; + #endif + ++#if defined(PIPE_ARCH_LOONGARCH64) ++ if (MCPU == "generic") ++ MCPU = "gs464v"; ++#endif ++ + builder.setMCPU(MCPU); + if (gallivm_debug & (GALLIVM_DEBUG_IR | GALLIVM_DEBUG_ASM | GALLIVM_DEBUG_DUMP_BC)) { + debug_printf("llc -mcpu option: %s\n", MCPU.str().c_str()); +diff --git a/src/gallium/include/pipe/p_config.h b/src/gallium/include/pipe/p_config.h +index bf7cc217e85..5f36c643ed9 100644 +--- a/src/gallium/include/pipe/p_config.h ++++ b/src/gallium/include/pipe/p_config.h +@@ -128,6 +128,12 @@ + #define PIPE_ARCH_MIPS + #endif + ++#if defined(__loongarch64__) || defined(__loongarch64) ++#define PIPE_ARCH_LOONGARCH64 ++#elif defined(__loongarch__) ++#define PIPE_ARCH_LOONGARCH ++#endif ++ + /* + * Endian detection. + */ +diff --git a/src/util/u_cpu_detect.c b/src/util/u_cpu_detect.c +index 3187ecac094..592a06a4861 100644 +--- a/src/util/u_cpu_detect.c ++++ b/src/util/u_cpu_detect.c +@@ -453,6 +453,31 @@ check_os_mips64_support(void) + } + #endif + ++#if defined(PIPE_ARCH_LOONGARCH64) ++static void ++check_os_loongarch64_support(void) ++{ ++#if defined(PIPE_OS_LINUX) ++ Elf64_auxv_t aux; ++ int fd; ++ ++ fd = open("/proc/self/auxv", O_RDONLY | O_CLOEXEC); ++ if (fd >= 0) { ++ while (read(fd, &aux, sizeof(Elf64_auxv_t)) == sizeof(Elf64_auxv_t)) { ++ if (aux.a_type == AT_HWCAP) { ++ uint64_t hwcap = aux.a_un.a_val; ++ ++ util_cpu_caps.has_lsx = (hwcap >> 2) & 1; ++ util_cpu_caps.has_lasx = (hwcap >> 3) & 1; ++ break; ++ } ++ } ++ close (fd); ++ } ++#endif /* PIPE_OS_LINUX */ ++} ++#endif ++ + static void + get_cpu_topology(void) + { +@@ -628,6 +653,10 @@ util_cpu_detect_once(void) + check_os_mips64_support(); + #endif + ++#if defined(PIPE_ARCH_LOONGARCH64) ++ check_os_loongarch64_support(); ++#endif ++ + #if defined(PIPE_ARCH_PPC) + check_os_altivec_support(); + #endif /* PIPE_ARCH_PPC */ +@@ -662,6 +691,8 @@ util_cpu_detect_once(void) + debug_printf("util_cpu_caps.has_neon = %u\n", util_cpu_caps.has_neon); + debug_printf("util_cpu_caps.has_daz = %u\n", util_cpu_caps.has_daz); + debug_printf("util_cpu_caps.has_msa = %u\n", util_cpu_caps.has_msa); ++ debug_printf("util_cpu_caps.has_lsx = %u\n", util_cpu_caps.has_lsx); ++ debug_printf("util_cpu_caps.has_lasx = %u\n", util_cpu_caps.has_lasx); + debug_printf("util_cpu_caps.has_avx512f = %u\n", util_cpu_caps.has_avx512f); + debug_printf("util_cpu_caps.has_avx512dq = %u\n", util_cpu_caps.has_avx512dq); + debug_printf("util_cpu_caps.has_avx512ifma = %u\n", util_cpu_caps.has_avx512ifma); +diff --git a/src/util/u_cpu_detect.h b/src/util/u_cpu_detect.h +index 6d53b5af121..225384fa29d 100644 +--- a/src/util/u_cpu_detect.h ++++ b/src/util/u_cpu_detect.h +@@ -75,6 +75,8 @@ struct util_cpu_caps { + unsigned has_daz:1; + unsigned has_neon:1; + unsigned has_msa:1; ++ unsigned has_lsx:1; ++ unsigned has_lasx:1; + + unsigned has_avx512f:1; + unsigned has_avx512dq:1; +-- +2.27.0 + diff --git a/0012-symbols-check-add-mips-platform-specific-symbols.patch b/0012-symbols-check-add-mips-platform-specific-symbols.patch new file mode 100644 index 0000000..025c3ad --- /dev/null +++ b/0012-symbols-check-add-mips-platform-specific-symbols.patch @@ -0,0 +1,35 @@ +From e29937045e63e2b9087ce1db18edc3cb9b05a301 Mon Sep 17 00:00:00 2001 +From: suijingfeng +Date: Sun, 11 Jul 2021 13:29:47 +0800 +Subject: [PATCH 12/16] symbols-check: add mips platform specific symbols + +fix the following symbols check: + +mesa:gbm / gbm-symbols-check FAIL 0.15 s (exit status 1) + +src/gbm/libgbm.so.1.0.0: missing symbol: _fbss +src/gbm/libgbm.so.1.0.0: missing symbol: _fdata +src/gbm/libgbm.so.1.0.0: missing symbol: _ftext + +Signed-off-by: suijingfeng +--- + bin/symbols-check.py | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/bin/symbols-check.py b/bin/symbols-check.py +index 0d56a19561e..b9847f76841 100644 +--- a/bin/symbols-check.py ++++ b/bin/symbols-check.py +@@ -16,6 +16,9 @@ PLATFORM_SYMBOLS = [ + '_end', + '_fini', + '_init', ++ '_fbss', ++ '_fdata', ++ '_ftext', + ] + + def get_symbols_nm(nm, lib): +-- +2.27.0 + diff --git a/0013-gallivm-arit-use-LLVMBuildFPToUI-when-the-float-is-n.patch b/0013-gallivm-arit-use-LLVMBuildFPToUI-when-the-float-is-n.patch new file mode 100644 index 0000000..453b82b --- /dev/null +++ b/0013-gallivm-arit-use-LLVMBuildFPToUI-when-the-float-is-n.patch @@ -0,0 +1,29 @@ +From 3c4ddfa87ee31cd20f998f19864c760a05791584 Mon Sep 17 00:00:00 2001 +From: suijingfeng +Date: Mon, 16 Aug 2021 14:42:57 +0800 +Subject: [PATCH 13/16] gallivm: arit: use LLVMBuildFPToUI when the float is + not signed + +--- + src/gallium/auxiliary/gallivm/lp_bld_arit.c | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +diff --git a/src/gallium/auxiliary/gallivm/lp_bld_arit.c b/src/gallium/auxiliary/gallivm/lp_bld_arit.c +index b99be32fda2..efab01a8c56 100644 +--- a/src/gallium/auxiliary/gallivm/lp_bld_arit.c ++++ b/src/gallium/auxiliary/gallivm/lp_bld_arit.c +@@ -2420,7 +2420,10 @@ lp_build_iround(struct lp_build_context *bld, + res = LLVMBuildFAdd(builder, a, half, ""); + } + +- res = LLVMBuildFPToSI(builder, res, int_vec_type, ""); ++ if (type.sign) ++ res = LLVMBuildFPToSI(builder, res, int_vec_type, ""); ++ else ++ res = LLVMBuildFPToUI(builder, res, int_vec_type, ""); + + return res; + } +-- +2.27.0 + diff --git a/0014-gallivm-disable-use-lp_build_round_arch-on-default.patch b/0014-gallivm-disable-use-lp_build_round_arch-on-default.patch new file mode 100644 index 0000000..96b2024 --- /dev/null +++ b/0014-gallivm-disable-use-lp_build_round_arch-on-default.patch @@ -0,0 +1,72 @@ +From 6c7619124921e40d4ef60bde7a108d4821a2430c Mon Sep 17 00:00:00 2001 +From: suijingfeng +Date: Mon, 16 Aug 2021 16:13:53 +0800 +Subject: [PATCH 14/16] gallivm: disable use lp_build_round_arch() on default + +As it kill performance of the application due to poor optimization +of nearbyintf function previded by GLIBC on MIPS64 and LOONGARCH64. + +But is still possible to use lp_build_round_arch() by pass the +GALLIVM_PERF=use_arch_rounding commnad line on the front of run +a 3D app. + +take glmark2 for example: + +$ GALLIVM_PERF=use_arch_rounding glmark2 + +Signed-off-by: suijingfeng +--- + src/gallium/auxiliary/gallivm/lp_bld_arit.c | 6 +++--- + src/gallium/auxiliary/gallivm/lp_bld_debug.h | 2 ++ + src/gallium/auxiliary/gallivm/lp_bld_init.c | 1 + + 3 files changed, 6 insertions(+), 3 deletions(-) + +diff --git a/src/gallium/auxiliary/gallivm/lp_bld_arit.c b/src/gallium/auxiliary/gallivm/lp_bld_arit.c +index efab01a8c56..a401fea04b8 100644 +--- a/src/gallium/auxiliary/gallivm/lp_bld_arit.c ++++ b/src/gallium/auxiliary/gallivm/lp_bld_arit.c +@@ -1906,13 +1906,13 @@ arch_rounding_available(const struct lp_type type) + return TRUE; + else if (util_get_cpu_caps()->has_msa && + (type.width * type.length == 128)) +- return TRUE; ++ return ((gallivm_perf & GALLIVM_PERF_USE_ARCH_ROUNDING) ? TRUE : FALSE); + else if (util_get_cpu_caps()->has_lsx && + (type.width * type.length == 128)) +- return TRUE; ++ return ((gallivm_perf & GALLIVM_PERF_USE_ARCH_ROUNDING) ? TRUE : FALSE); + else if (util_get_cpu_caps()->has_lasx && + (type.width * type.length == 256)) +- return TRUE; ++ return ((gallivm_perf & GALLIVM_PERF_USE_ARCH_ROUNDING) ? TRUE : FALSE); + + return FALSE; + } +diff --git a/src/gallium/auxiliary/gallivm/lp_bld_debug.h b/src/gallium/auxiliary/gallivm/lp_bld_debug.h +index 592da0b5180..7f1964667d2 100644 +--- a/src/gallium/auxiliary/gallivm/lp_bld_debug.h ++++ b/src/gallium/auxiliary/gallivm/lp_bld_debug.h +@@ -55,6 +55,8 @@ + #define GALLIVM_PERF_OPT_O3 (1 << 7) + #endif + ++#define GALLIVM_PERF_USE_ARCH_ROUNDING (1 << 8) ++ + #ifdef __cplusplus + extern "C" { + #endif +diff --git a/src/gallium/auxiliary/gallivm/lp_bld_init.c b/src/gallium/auxiliary/gallivm/lp_bld_init.c +index 1b1a28bbf6b..f6bd2821600 100644 +--- a/src/gallium/auxiliary/gallivm/lp_bld_init.c ++++ b/src/gallium/auxiliary/gallivm/lp_bld_init.c +@@ -67,6 +67,7 @@ static const struct debug_named_value lp_bld_perf_flags[] = { + { "o2", GALLIVM_PERF_OPT_O2, "enable medium optimization passes" }, + { "o1", GALLIVM_PERF_OPT_O1, "enable less optimization passes" }, + #endif ++ { "use_arch_rounding", GALLIVM_PERF_USE_ARCH_ROUNDING, "use poor arch rounding function provided by glibc" }, + DEBUG_NAMED_VALUE_END + }; + +-- +2.27.0 + diff --git a/0015-gallivm-add-more-optlevel-for-debuging-perpose-on-mi.patch b/0015-gallivm-add-more-optlevel-for-debuging-perpose-on-mi.patch new file mode 100644 index 0000000..e16d82a --- /dev/null +++ b/0015-gallivm-add-more-optlevel-for-debuging-perpose-on-mi.patch @@ -0,0 +1,74 @@ +From 4e0ad6386e06e2ce5422e69176a92b41ede37e44 Mon Sep 17 00:00:00 2001 +From: suijingfeng +Date: Mon, 16 Aug 2021 16:41:06 +0800 +Subject: [PATCH 15/16] gallivm: add more optlevel for debuging perpose on + mips64 + +This patch add more optlevel for shader compiling optimization on +loongarch. + +Signed-off-by: suijingfeng +--- + src/gallium/auxiliary/gallivm/lp_bld_debug.h | 2 +- + src/gallium/auxiliary/gallivm/lp_bld_init.c | 24 +++++++++----------- + 2 files changed, 12 insertions(+), 14 deletions(-) + +diff --git a/src/gallium/auxiliary/gallivm/lp_bld_debug.h b/src/gallium/auxiliary/gallivm/lp_bld_debug.h +index 7f1964667d2..63ca28a40de 100644 +--- a/src/gallium/auxiliary/gallivm/lp_bld_debug.h ++++ b/src/gallium/auxiliary/gallivm/lp_bld_debug.h +@@ -49,7 +49,7 @@ + #define GALLIVM_PERF_NO_OPT (1 << 3) + #define GALLIVM_PERF_NO_AOS_SAMPLING (1 << 4) + +-#if defined(PIPE_ARCH_MIPS64) ++#if defined(PIPE_ARCH_MIPS64) || defined(PIPE_ARCH_LOONGARCH64) + #define GALLIVM_PERF_OPT_O1 (1 << 5) + #define GALLIVM_PERF_OPT_O2 (1 << 6) + #define GALLIVM_PERF_OPT_O3 (1 << 7) +diff --git a/src/gallium/auxiliary/gallivm/lp_bld_init.c b/src/gallium/auxiliary/gallivm/lp_bld_init.c +index f6bd2821600..beb74cdbcc5 100644 +--- a/src/gallium/auxiliary/gallivm/lp_bld_init.c ++++ b/src/gallium/auxiliary/gallivm/lp_bld_init.c +@@ -62,7 +62,7 @@ static const struct debug_named_value lp_bld_perf_flags[] = { + { "nopt", GALLIVM_PERF_NO_OPT, "disable optimization passes to speed up shader compilation" }, + { "no_filter_hacks", GALLIVM_PERF_NO_BRILINEAR | GALLIVM_PERF_NO_RHO_APPROX | + GALLIVM_PERF_NO_QUAD_LOD, "disable filter optimization hacks" }, +-#if defined(PIPE_ARCH_MIPS64) ++#if defined(PIPE_ARCH_MIPS64) || defined(PIPE_ARCH_LOONGARCH64) + { "o3", GALLIVM_PERF_OPT_O3, "enable aggressive optimization passes" }, + { "o2", GALLIVM_PERF_OPT_O2, "enable medium optimization passes" }, + { "o1", GALLIVM_PERF_OPT_O1, "enable less optimization passes" }, +@@ -266,19 +266,17 @@ init_gallivm_engine(struct gallivm_state *gallivm) + optlevel = None; + } + else { +- optlevel = Default; +- } +- +-#if defined(PIPE_ARCH_MIPS64) +- if (gallivm_perf & GALLIVM_PERF_OPT_O3) +- optlevel = Aggressive; +- else if (gallivm_perf & GALLIVM_PERF_OPT_O2) +- optlevel = Default; +- else if (gallivm_perf & GALLIVM_PERF_OPT_O1) +- optlevel = Less; +- else +- optlevel = None; ++#if defined(PIPE_ARCH_MIPS64) || defined(PIPE_ARCH_LOONGARCH64) ++ if (gallivm_perf & GALLIVM_PERF_OPT_O3) ++ optlevel = Aggressive; ++ else if (gallivm_perf & GALLIVM_PERF_OPT_O2) ++ optlevel = Default; ++ else if (gallivm_perf & GALLIVM_PERF_OPT_O1) ++ optlevel = Less; ++ else + #endif ++ optlevel = Default; ++ } + + ret = lp_build_create_jit_compiler_for_module(&gallivm->engine, + &gallivm->code, +-- +2.27.0 + diff --git a/0016-gallivm-enable-lsx-and-lasx-on-loongarch-when-LLVM-e.patch b/0016-gallivm-enable-lsx-and-lasx-on-loongarch-when-LLVM-e.patch new file mode 100644 index 0000000..05ca967 --- /dev/null +++ b/0016-gallivm-enable-lsx-and-lasx-on-loongarch-when-LLVM-e.patch @@ -0,0 +1,119 @@ +From 1b298a404e9d6d89150a5e853afd99d8022e1c27 Mon Sep 17 00:00:00 2001 +From: suijingfeng +Date: Fri, 27 Aug 2021 10:09:28 +0800 +Subject: [PATCH 16/16] gallivm: enable lsx and lasx on loongarch when LLVM + expose it + + llvmpipe will crash when enable it with previous llvm release( +--- + src/gallium/auxiliary/gallivm/lp_bld_init.c | 9 ++++- + src/gallium/auxiliary/gallivm/lp_bld_misc.cpp | 34 +++++++++++++++---- + src/gallium/auxiliary/gallivm/lp_bld_misc.h | 3 ++ + 3 files changed, 38 insertions(+), 8 deletions(-) + +diff --git a/src/gallium/auxiliary/gallivm/lp_bld_init.c b/src/gallium/auxiliary/gallivm/lp_bld_init.c +index beb74cdbcc5..e7289bbf852 100644 +--- a/src/gallium/auxiliary/gallivm/lp_bld_init.c ++++ b/src/gallium/auxiliary/gallivm/lp_bld_init.c +@@ -452,7 +452,14 @@ lp_build_init(void) + + if (util_get_cpu_caps()->has_avx2 || util_get_cpu_caps()->has_avx) { + lp_native_vector_width = 256; +- } else { ++ } else if (util_get_cpu_caps()->has_lasx) { ++#if defined(PIPE_ARCH_LOONGARCH64) ++ if (lp_probe_lasx()) ++ lp_native_vector_width = 256; ++ else ++#endif ++ lp_native_vector_width = 128; ++ } else { + /* Leave it at 128, even when no SIMD extensions are available. + * Really needs to be a multiple of 128 so can fit 4 floats. + */ +diff --git a/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp b/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp +index 4b75c933263..82673bb2a7b 100644 +--- a/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp ++++ b/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp +@@ -345,7 +345,7 @@ lp_build_create_jit_compiler_for_module(LLVMExecutionEngineRef *OutJIT, + + llvm::SmallVector MAttrs; + +-#if LLVM_VERSION_MAJOR >= 4 && (defined(PIPE_ARCH_X86) || defined(PIPE_ARCH_X86_64) || defined(PIPE_ARCH_ARM)) ++#if LLVM_VERSION_MAJOR >= 4 && (defined(PIPE_ARCH_X86) || defined(PIPE_ARCH_X86_64) || defined(PIPE_ARCH_ARM) || defined(PIPE_ARCH_LOONGARCH64)) + /* llvm-3.3+ implements sys::getHostCPUFeatures for Arm + * and llvm-3.7+ for x86, which allows us to enable/disable + * code generation based on the results of cpuid on these +@@ -444,12 +444,6 @@ lp_build_create_jit_compiler_for_module(LLVMExecutionEngineRef *OutJIT, + MAttrs.push_back("+ptr64"); + #endif + +-#if defined(PIPE_ARCH_LOONGARCH64) +-// Our llvm compilor is not ready for this now +-// MAttrs.push_back(util_get_cpu_caps()->has_lsx ? "+lsx" : "-lsx"); +-// MAttrs.push_back(util_get_cpu_caps()->has_lasx ? "+lasx" : "-lasx"); +-#endif +- + builder.setMAttrs(MAttrs); + + if (gallivm_debug & (GALLIVM_DEBUG_IR | GALLIVM_DEBUG_ASM | GALLIVM_DEBUG_DUMP_BC)) { +@@ -562,6 +556,32 @@ lp_build_create_jit_compiler_for_module(LLVMExecutionEngineRef *OutJIT, + } + + ++#if defined(PIPE_ARCH_LOONGARCH64) ++extern "C" ++LLVMBool ++lp_probe_lasx(void) ++{ ++ using namespace llvm; ++ /* our llvm-8+ implements sys::getHostCPUFeatures for loongarch, ++ * which allows us to enable/disable code generation based ++ * on the results of cpucfg. ++ */ ++ llvm::StringMap features; ++ llvm::sys::getHostCPUFeatures(features); ++ ++ for (StringMapIterator f = features.begin(); ++ f != features.end(); ++ ++f) { ++ ++ if ((*f).first() == "lasx" && (*f).second) ++ return 1; ++ } ++ ++ return 0; ++} ++#endif ++ ++ + extern "C" + void + lp_free_generated_code(struct lp_generated_code *code) +diff --git a/src/gallium/auxiliary/gallivm/lp_bld_misc.h b/src/gallium/auxiliary/gallivm/lp_bld_misc.h +index 363fbded728..8e2300d9692 100644 +--- a/src/gallium/auxiliary/gallivm/lp_bld_misc.h ++++ b/src/gallium/auxiliary/gallivm/lp_bld_misc.h +@@ -52,6 +52,9 @@ gallivm_dispose_target_library_info(LLVMTargetLibraryInfoRef library_info); + extern void + lp_set_target_options(void); + ++#if defined(PIPE_ARCH_LOONGARCH64) ++extern LLVMBool lp_probe_lasx(void); ++#endif + + extern int + lp_build_create_jit_compiler_for_module(LLVMExecutionEngineRef *OutJIT, +-- +2.27.0 + diff --git a/mesa.spec b/mesa.spec index 64bb68e..a946d56 100644 --- a/mesa.spec +++ b/mesa.spec @@ -1,3 +1,4 @@ +%define anolis_release .0.1 %global llvm_toolset %{nil} %global llvm_pkg_prefix %{nil} @@ -40,7 +41,7 @@ Name: mesa Summary: Mesa graphics libraries Version: 21.1.5 -Release: 1%{?rctag:.%{rctag}}%{?dist} +Release: 1%{?rctag:.%{rctag}}%{anolis_release}%{?dist} License: MIT URL: http://www.mesa3d.org @@ -57,6 +58,22 @@ Source4: Mesa-MLAA-License-Clarification-Email.txt Patch0: lavapipe-disable-env-var.patch Patch1: mesa-vk-wsi-sw-fixes.patch +Patch1002: 0002-gallium-llvmpipe-pass-MCPU-mips64r2-to-LLVM-on-mips.patch +Patch1003: 0003-gallivm-Return-true-from-arch_rounding_available-if-.patch +Patch1004: 0004-gallivm-fix-coroutines-on-mips64-with-llvm-8.patch +Patch1005: 0005-gallivm-add-more-optlevel-for-debug-purpose-on-mips6.patch +Patch1006: 0006-disable-madd4-on-mips64.patch +Patch1007: 0007-meson-add-mips-asm-flags.patch +Patch1008: 0008-kmsro-Extend-to-include-loongson-drm-support.patch +Patch1009: 0009-meson-add-loongarch64-build-support.patch +Patch1010: 0010-gallivm-temporary-disable-coroutines-on-loongarch64-.patch +Patch1011: 0011-gallivm-detect-loongarch-lsx-and-lasx-instruction-se.patch +Patch1012: 0012-symbols-check-add-mips-platform-specific-symbols.patch +Patch1013: 0013-gallivm-arit-use-LLVMBuildFPToUI-when-the-float-is-n.patch +Patch1014: 0014-gallivm-disable-use-lp_build_round_arch-on-default.patch +Patch1015: 0015-gallivm-add-more-optlevel-for-debuging-perpose-on-mi.patch +Patch1016: 0016-gallivm-enable-lsx-and-lasx-on-loongarch-when-LLVM-e.patch + BuildRequires: gcc BuildRequires: gcc-c++ @@ -547,6 +564,9 @@ done %endif %changelog +* Wed Jan 5 2022 Liwei Ge - 21.1.5-1.0.1 +- Support loongarch64 + * Thu Jul 22 2021 Dave Airlie - 21.1.5-1 - Fix vulkan sw with wayland, pull in .4 + .5 fixes -- Gitee From 911c54e81ab9d8313743a39cff9f80c3e2dcc618 Mon Sep 17 00:00:00 2001 From: Liwei Ge Date: Fri, 18 Feb 2022 15:24:11 +0800 Subject: [PATCH 2/2] dri: fix build issue on other platform Signed-off-by: Liwei Ge --- ...garch-leave-changes-no-bothor-others.patch | 143 ++++++++++++++++++ mesa.spec | 1 + 2 files changed, 144 insertions(+) create mode 100644 1017-loongarch-leave-changes-no-bothor-others.patch diff --git a/1017-loongarch-leave-changes-no-bothor-others.patch b/1017-loongarch-leave-changes-no-bothor-others.patch new file mode 100644 index 0000000..a08bd07 --- /dev/null +++ b/1017-loongarch-leave-changes-no-bothor-others.patch @@ -0,0 +1,143 @@ +From 9d2f9b5fa5cfbc3a96bf63686c94e6fdd795e6a6 Mon Sep 17 00:00:00 2001 +From: Liwei Ge +Date: Fri, 18 Feb 2022 15:08:22 +0800 +Subject: [PATCH] loongarch: leave changes no bothor others + +Signed-off-by: Liwei Ge +--- + src/gallium/auxiliary/gallivm/lp_bld_arit.c | 19 +++++++++++++++++-- + src/gallium/auxiliary/gallivm/lp_bld_init.c | 8 +++++--- + src/gallium/drivers/llvmpipe/lp_test_arit.c | 5 ++++- + src/util/u_cpu_detect.c | 6 ++++++ + src/util/u_cpu_detect.h | 6 ++++++ + 5 files changed, 38 insertions(+), 6 deletions(-) + +diff --git a/src/gallium/auxiliary/gallivm/lp_bld_arit.c b/src/gallium/auxiliary/gallivm/lp_bld_arit.c +index 0dc4cdd..e8e5ff4 100644 +--- a/src/gallium/auxiliary/gallivm/lp_bld_arit.c ++++ b/src/gallium/auxiliary/gallivm/lp_bld_arit.c +@@ -1906,15 +1906,21 @@ arch_rounding_available(const struct lp_type type) + return TRUE; + else if (util_get_cpu_caps()->has_neon) + return TRUE; ++#if defined(PIPE_ARCH_MIPS64) + else if (util_get_cpu_caps()->has_msa && + (type.width * type.length == 128)) + return ((gallivm_perf & GALLIVM_PERF_USE_ARCH_ROUNDING) ? TRUE : FALSE); ++#endif ++#if defined(PIPE_ARCH_LOONGARCH) + else if (util_get_cpu_caps()->has_lsx && + (type.width * type.length == 128)) + return ((gallivm_perf & GALLIVM_PERF_USE_ARCH_ROUNDING) ? TRUE : FALSE); ++#endif ++#if defined(PIPE_ARCH_LOONGARCH64) + else if (util_get_cpu_caps()->has_lasx && + (type.width * type.length == 256)) + return ((gallivm_perf & GALLIVM_PERF_USE_ARCH_ROUNDING) ? TRUE : FALSE); ++#endif + + return FALSE; + } +@@ -2022,8 +2028,17 @@ lp_build_round_arch(struct lp_build_context *bld, + LLVMValueRef a, + enum lp_build_round_mode mode) + { +- if (util_get_cpu_caps()->has_sse4_1 || util_get_cpu_caps()->has_neon || util_get_cpu_caps()->has_msa +- || util_get_cpu_caps()->has_lsx || util_get_cpu_caps()->has_lasx) { ++ if (util_get_cpu_caps()->has_sse4_1 || util_get_cpu_caps()->has_neon ++#if defined(PIPE_ARCH_MIPS64) ++ || util_get_cpu_caps()->has_msa ++#endif ++#if defined(PIPE_ARCH_LOONGARCH) ++ || util_get_cpu_caps()->has_lsx ++#endif ++#if defined(PIPE_ARCH_LOONGARCH64) ++ || util_get_cpu_caps()->has_lasx ++#endif ++ ) { + LLVMBuilderRef builder = bld->gallivm->builder; + const struct lp_type type = bld->type; + const char *intrinsic_root; +diff --git a/src/gallium/auxiliary/gallivm/lp_bld_init.c b/src/gallium/auxiliary/gallivm/lp_bld_init.c +index 53254da..24a9458 100644 +--- a/src/gallium/auxiliary/gallivm/lp_bld_init.c ++++ b/src/gallium/auxiliary/gallivm/lp_bld_init.c +@@ -463,14 +463,16 @@ lp_build_init(void) + + if (util_get_cpu_caps()->has_avx2 || util_get_cpu_caps()->has_avx) { + lp_native_vector_width = 256; +- } else if (util_get_cpu_caps()->has_lasx) { ++ } + #if defined(PIPE_ARCH_LOONGARCH64) ++ else if (util_get_cpu_caps()->has_lasx) { + if (lp_probe_lasx()) + lp_native_vector_width = 256; + else +-#endif + lp_native_vector_width = 128; +- } else { ++ } ++#endif ++ else { + /* Leave it at 128, even when no SIMD extensions are available. + * Really needs to be a multiple of 128 so can fit 4 floats. + */ +diff --git a/src/gallium/drivers/llvmpipe/lp_test_arit.c b/src/gallium/drivers/llvmpipe/lp_test_arit.c +index d58770c..b7a3189 100644 +--- a/src/gallium/drivers/llvmpipe/lp_test_arit.c ++++ b/src/gallium/drivers/llvmpipe/lp_test_arit.c +@@ -479,7 +479,10 @@ test_unary(unsigned verbose, FILE *fp, const struct unary_test_t *test, unsigned + continue; + } + +- if (!util_get_cpu_caps()->has_neon && !util_get_cpu_caps()->has_msa && ++ if (!util_get_cpu_caps()->has_neon && ++#if defined(PIPE_ARCH_MIPS64) ++ !util_get_cpu_caps()->has_msa && ++#endif + test->ref == &nearbyintf && length == 2 && + ref != roundf(testval)) { + /* FIXME: The generic (non SSE) path in lp_build_iround, which is +diff --git a/src/util/u_cpu_detect.c b/src/util/u_cpu_detect.c +index 6d79ebd..9ce8042 100644 +--- a/src/util/u_cpu_detect.c ++++ b/src/util/u_cpu_detect.c +@@ -804,9 +804,15 @@ util_cpu_detect_once(void) + debug_printf("util_cpu_caps.has_vsx = %u\n", util_cpu_caps.has_vsx); + debug_printf("util_cpu_caps.has_neon = %u\n", util_cpu_caps.has_neon); + debug_printf("util_cpu_caps.has_daz = %u\n", util_cpu_caps.has_daz); ++#if defined(PIPE_ARCH_MIPS64) + debug_printf("util_cpu_caps.has_msa = %u\n", util_cpu_caps.has_msa); ++#endif ++#if defined(PIPE_ARCH_LOONGARCH) + debug_printf("util_cpu_caps.has_lsx = %u\n", util_cpu_caps.has_lsx); ++#endif ++#if defined(PIPE_ARCH_LOONGARCH64) + debug_printf("util_cpu_caps.has_lasx = %u\n", util_cpu_caps.has_lasx); ++#endif + debug_printf("util_cpu_caps.has_avx512f = %u\n", util_cpu_caps.has_avx512f); + debug_printf("util_cpu_caps.has_avx512dq = %u\n", util_cpu_caps.has_avx512dq); + debug_printf("util_cpu_caps.has_avx512ifma = %u\n", util_cpu_caps.has_avx512ifma); +diff --git a/src/util/u_cpu_detect.h b/src/util/u_cpu_detect.h +index 0a42e6f..4c2d29f 100644 +--- a/src/util/u_cpu_detect.h ++++ b/src/util/u_cpu_detect.h +@@ -85,9 +85,15 @@ struct util_cpu_caps_t { + unsigned has_vsx:1; + unsigned has_daz:1; + unsigned has_neon:1; ++#if defined(PIPE_ARCH_MIPS64) + unsigned has_msa:1; ++#endif ++#if defined(PIPE_ARCH_LOONGARCH) + unsigned has_lsx:1; ++#endif ++#if defined(PIPE_ARCH_LOONGARCH64) + unsigned has_lasx:1; ++#endif + + unsigned has_avx512f:1; + unsigned has_avx512dq:1; +-- +2.27.0 + diff --git a/mesa.spec b/mesa.spec index a946d56..5143156 100644 --- a/mesa.spec +++ b/mesa.spec @@ -73,6 +73,7 @@ Patch1013: 0013-gallivm-arit-use-LLVMBuildFPToUI-when-the-float-is-n.patch Patch1014: 0014-gallivm-disable-use-lp_build_round_arch-on-default.patch Patch1015: 0015-gallivm-add-more-optlevel-for-debuging-perpose-on-mi.patch Patch1016: 0016-gallivm-enable-lsx-and-lasx-on-loongarch-when-LLVM-e.patch +Patch1017: 1017-loongarch-leave-changes-no-bothor-others.patch BuildRequires: gcc BuildRequires: gcc-c++ -- Gitee