diff --git a/Add-lbt-support-for-kvm.patch b/Add-lbt-support-for-kvm.patch new file mode 100644 index 0000000000000000000000000000000000000000..d2d6ef431a23b865d7986ca9d52a2b8bbfa9785b --- /dev/null +++ b/Add-lbt-support-for-kvm.patch @@ -0,0 +1,154 @@ +From 02aacf8cfbe627c0012bf38a007a8a8ec9f95cb5 Mon Sep 17 00:00:00 2001 +From: lixianglai +Date: Mon, 29 May 2023 08:00:52 -0400 +Subject: [PATCH 13/14] Add lbt support for kvm + +Signed-off-by: lixianglai +--- + hw/loongarch/larch_3a.c | 4 ++-- + linux-headers/asm-loongarch64/kvm.h | 10 ++++++++- + target/loongarch64/cpu.h | 10 +++++++++ + target/loongarch64/kvm.c | 35 +++++++++++++++++++++++++++++ + 4 files changed, 56 insertions(+), 3 deletions(-) + +diff --git a/hw/loongarch/larch_3a.c b/hw/loongarch/larch_3a.c +index 8fc79546d..2affc5048 100644 +--- a/hw/loongarch/larch_3a.c ++++ b/hw/loongarch/larch_3a.c +@@ -348,8 +348,8 @@ struct kvm_cpucfg ls3a5k_cpucfgs = { + CPUCFG1_IOCSRBRD, + .cpucfg[LOONGARCH_CPUCFG2] = CPUCFG2_FP | CPUCFG2_FPSP | CPUCFG2_FPDP | + CPUCFG2_FPVERS | CPUCFG2_LSX | CPUCFG2_LASX | CPUCFG2_COMPLEX | +- CPUCFG2_CRYPTO | CPUCFG2_LLFTP | CPUCFG2_LLFTPREV | CPUCFG2_LSPW | +- CPUCFG2_LAM, ++ CPUCFG2_CRYPTO | CPUCFG2_LLFTP | CPUCFG2_LLFTPREV | CPUCFG2_X86BT | ++ CPUCFG2_ARMBT | CPUCFG2_MIPSBT | CPUCFG2_LSPW | CPUCFG2_LAM, + .cpucfg[LOONGARCH_CPUCFG3] = CPUCFG3_CCDMA | CPUCFG3_SFB | CPUCFG3_UCACC | + CPUCFG3_LLEXC | CPUCFG3_SCDLY | CPUCFG3_LLDBAR | CPUCFG3_ITLBT | + CPUCFG3_ICACHET | CPUCFG3_SPW_LVL | CPUCFG3_SPW_HG_HF | CPUCFG3_RVA | +diff --git a/linux-headers/asm-loongarch64/kvm.h b/linux-headers/asm-loongarch64/kvm.h +index 799af7594..3687a358f 100644 +--- a/linux-headers/asm-loongarch64/kvm.h ++++ b/linux-headers/asm-loongarch64/kvm.h +@@ -77,6 +77,7 @@ struct kvm_fpu { + * Register set = 2: KVM specific registers (see definitions below). + * + * Register set = 3: FPU / MSA registers (see definitions below). ++ * Register set = 4: LBT registers (see definitions below). + * + * Other sets registers may be added in the future. Each set would + * have its own identifier in bits[31..16]. +@@ -86,7 +87,7 @@ struct kvm_fpu { + #define KVM_REG_LOONGARCH_CSR (KVM_REG_LOONGARCH | 0x0000000000010000ULL) + #define KVM_REG_LOONGARCH_KVM (KVM_REG_LOONGARCH | 0x0000000000020000ULL) + #define KVM_REG_LOONGARCH_FPU (KVM_REG_LOONGARCH | 0x0000000000030000ULL) +- ++#define KVM_REG_LOONGARCH_LBT (KVM_REG_LOONGARCH | 0x0000000000040000ULL) + + /* + * KVM_REG_LOONGARCH_GP - General purpose registers from kvm_regs. +@@ -168,6 +169,13 @@ struct kvm_fpu { + + #define KVM_REG_LOONGARCH_VCPU_RESET (KVM_REG_LOONGARCH_KVM | KVM_REG_SIZE_U64 | 4) + ++#define KVM_REG_LBT_SCR0 (KVM_REG_LOONGARCH_LBT | KVM_REG_SIZE_U64 | 1) ++#define KVM_REG_LBT_SCR1 (KVM_REG_LOONGARCH_LBT | KVM_REG_SIZE_U64 | 2) ++#define KVM_REG_LBT_SCR2 (KVM_REG_LOONGARCH_LBT | KVM_REG_SIZE_U64 | 3) ++#define KVM_REG_LBT_SCR3 (KVM_REG_LOONGARCH_LBT | KVM_REG_SIZE_U64 | 4) ++#define KVM_REG_LBT_FLAGS (KVM_REG_LOONGARCH_LBT | KVM_REG_SIZE_U64 | 5) ++#define KVM_REG_LBT_FTOP (KVM_REG_LOONGARCH_LBT | KVM_REG_SIZE_U64 | 6) ++ + struct kvm_iocsr_entry { + __u32 addr; + __u32 pad; +diff --git a/target/loongarch64/cpu.h b/target/loongarch64/cpu.h +index 078556a22..ab88658e4 100644 +--- a/target/loongarch64/cpu.h ++++ b/target/loongarch64/cpu.h +@@ -55,6 +55,7 @@ typedef struct CPULOONGARCHFPUContext { + uint32_t fcsr0; + uint32_t fcsr0_rw_bitmask; + uint32_t vcsr16; ++ uint64_t ftop; + } CPULOONGARCHFPUContext; + + /* fp control and status register definition */ +@@ -167,6 +168,15 @@ struct CPULOONGARCHState { + struct { + uint64_t guest_addr; + } st; ++ struct { ++ /* scratch registers */ ++ unsigned long scr0; ++ unsigned long scr1; ++ unsigned long scr2; ++ unsigned long scr3; ++ /* loongarch eflag */ ++ unsigned long eflag; ++ } lbt; + }; + + +diff --git a/target/loongarch64/kvm.c b/target/loongarch64/kvm.c +index b6711da91..0eaabe394 100644 +--- a/target/loongarch64/kvm.c ++++ b/target/loongarch64/kvm.c +@@ -1295,6 +1295,39 @@ int kvm_loongarch_get_pvtime(LOONGARCHCPU *cpu) + return 0; + } + ++ ++static int kvm_loongarch_put_lbt_registers(CPUState *cs) ++{ ++ int ret = 0; ++ LOONGARCHCPU *cpu = LOONGARCH_CPU(cs); ++ CPULOONGARCHState *env = &cpu->env; ++ ++ ret |= kvm_larch_putq(cs, KVM_REG_LBT_SCR0, &env->lbt.scr0); ++ ret |= kvm_larch_putq(cs, KVM_REG_LBT_SCR1, &env->lbt.scr1); ++ ret |= kvm_larch_putq(cs, KVM_REG_LBT_SCR2, &env->lbt.scr2); ++ ret |= kvm_larch_putq(cs, KVM_REG_LBT_SCR3, &env->lbt.scr3); ++ ret |= kvm_larch_putq(cs, KVM_REG_LBT_FLAGS, &env->lbt.eflag); ++ ret |= kvm_larch_putq(cs, KVM_REG_LBT_FTOP, &env->active_fpu.ftop); ++ ++ return ret; ++} ++ ++static int kvm_loongarch_get_lbt_registers(CPUState *cs) ++{ ++ int ret = 0; ++ LOONGARCHCPU *cpu = LOONGARCH_CPU(cs); ++ CPULOONGARCHState *env = &cpu->env; ++ ++ ret |= kvm_larch_getq(cs, KVM_REG_LBT_SCR0, &env->lbt.scr0); ++ ret |= kvm_larch_getq(cs, KVM_REG_LBT_SCR1, &env->lbt.scr1); ++ ret |= kvm_larch_getq(cs, KVM_REG_LBT_SCR2, &env->lbt.scr2); ++ ret |= kvm_larch_getq(cs, KVM_REG_LBT_SCR3, &env->lbt.scr3); ++ ret |= kvm_larch_getq(cs, KVM_REG_LBT_FLAGS, &env->lbt.eflag); ++ ret |= kvm_larch_getq(cs, KVM_REG_LBT_FTOP, &env->active_fpu.ftop); ++ ++ return ret; ++} ++ + int kvm_arch_put_registers(CPUState *cs, int level) + { + LOONGARCHCPU *cpu = LOONGARCH_CPU(cs); +@@ -1326,6 +1359,7 @@ int kvm_arch_put_registers(CPUState *cs, int level) + return ret; + } + ++ kvm_loongarch_put_lbt_registers(cs); + return ret; + } + +@@ -1352,6 +1386,7 @@ int kvm_arch_get_registers(CPUState *cs) + + kvm_loongarch_get_csr_registers(cs); + kvm_loongarch_get_fpu_registers(cs); ++ kvm_loongarch_get_lbt_registers(cs); + + return ret; + } +-- +2.27.0 + diff --git a/Fix-irq-routing-and-fpu-option-to-compat-with-kernel.patch b/Fix-irq-routing-and-fpu-option-to-compat-with-kernel.patch new file mode 100644 index 0000000000000000000000000000000000000000..8937b8d5d83b319260a3dd66a162ee30361c9d00 --- /dev/null +++ b/Fix-irq-routing-and-fpu-option-to-compat-with-kernel.patch @@ -0,0 +1,31 @@ +From 889d874e72cec80244363d3c4f9594d14f05d529 Mon Sep 17 00:00:00 2001 +From: lixianglai +Date: Mon, 29 May 2023 07:38:26 -0400 +Subject: [PATCH 07/14] Fix irq routing and fpu option to compat with kernel + v6.4 + +Fix set irq routing and enable fpu for kvm to compat +with kernel v6.4 + +Signed-off-by: lixianglai +--- + target/loongarch64/kvm.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/target/loongarch64/kvm.c b/target/loongarch64/kvm.c +index 6885ec6c9..b6711da91 100644 +--- a/target/loongarch64/kvm.c ++++ b/target/loongarch64/kvm.c +@@ -107,6 +107,9 @@ int kvm_arch_init_vcpu(CPUState *cs) + CPULOONGARCHState *env = &cpu->env; + int ret = 0; + ++ kvm_vcpu_enable_cap(cs, KVM_CAP_LOONGARCH_FPU, 0, 0); ++ kvm_vcpu_enable_cap(cs, KVM_CAP_LOONGARCH_LSX, 0, 0); ++ + cpu->cpuStateEntry = qemu_add_vm_change_state_handler(kvm_loongarch_update_state, cs); + cpu->kvm_csr_buf = g_malloc0(CSR_BUF_SIZE + CSR_BUF_SIZE); + +-- +2.27.0 + diff --git a/Fix-smp.cores-value.patch b/Fix-smp.cores-value.patch new file mode 100644 index 0000000000000000000000000000000000000000..26f4b7bad86b2810ad5d5b735a339846996a83cc --- /dev/null +++ b/Fix-smp.cores-value.patch @@ -0,0 +1,35 @@ +From 509d230669e65fd45bd3a58f3167e4a12a74877e Mon Sep 17 00:00:00 2001 +From: lixianglai +Date: Mon, 29 May 2023 07:55:12 -0400 +Subject: [PATCH 12/14] Fix smp.cores value + +The smp.cores should use the default value passed from +qemu start command, and the argument is cores_per_socket. + +Signed-off-by: lixianglai +--- + hw/loongarch/larch_3a.c | 7 ------- + 1 file changed, 7 deletions(-) + +diff --git a/hw/loongarch/larch_3a.c b/hw/loongarch/larch_3a.c +index b1501e0ea..8fc79546d 100644 +--- a/hw/loongarch/larch_3a.c ++++ b/hw/loongarch/larch_3a.c +@@ -1211,14 +1211,7 @@ static void loongarch_build_smbios(LoongarchMachineState *lsms) + uint8_t *smbios_tables, *smbios_anchor; + size_t smbios_tables_len, smbios_anchor_len; + const char *product = "QEMU Virtual Machine"; +- int nb_numa_nodes, smp_cpus; + +- smp_cpus = ms->smp.cpus; +- nb_numa_nodes = ms->numa_state->num_nodes; +- if (nb_numa_nodes == 0) { +- nb_numa_nodes = 1; +- } +- ms->smp.cores = smp_cpus / nb_numa_nodes; + if (!lsms->fw_cfg) { + return; + } +-- +2.27.0 + diff --git a/Modify-smbios-option-lack-and-Modify-the-maximum-num.patch b/Modify-smbios-option-lack-and-Modify-the-maximum-num.patch new file mode 100644 index 0000000000000000000000000000000000000000..959dd7edc09375f9c335b2c73c9cd28d7bf9c84e --- /dev/null +++ b/Modify-smbios-option-lack-and-Modify-the-maximum-num.patch @@ -0,0 +1,44 @@ +From 5fb830ad315907fca8a30551c1160632001fc6fb Mon Sep 17 00:00:00 2001 +From: lixianglai +Date: Mon, 29 May 2023 05:48:46 -0400 +Subject: [PATCH 01/14] Modify smbios option lack and Modify the maximum number + of CPUs supported by the virtual machine. + +Add smbios option support for loongarch. +The number of virtual CPUs can be greater than the number of CPUs of the host machine. + +Signed-off-by: lixianglai +--- + accel/kvm/kvm-all.c | 2 +- + qemu-options.hx | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c +index 8f2a53438..e7d1e9ace 100644 +--- a/accel/kvm/kvm-all.c ++++ b/accel/kvm/kvm-all.c +@@ -2423,7 +2423,7 @@ static int kvm_init(MachineState *ms) + soft_vcpus_limit = kvm_recommended_vcpus(s); + hard_vcpus_limit = kvm_max_vcpus(s); + +-#ifdef HOST_PPC64 ++#if defined(HOST_PPC64) || defined(HOST_LOONGARCH) + /* + * On POWER, the kernel advertises a soft limit based on the + * number of CPU threads on the host. We want to allow exceeding +diff --git a/qemu-options.hx b/qemu-options.hx +index 4b7798088..8997969d5 100644 +--- a/qemu-options.hx ++++ b/qemu-options.hx +@@ -2480,7 +2480,7 @@ DEF("smbios", HAS_ARG, QEMU_OPTION_smbios, + " specify SMBIOS type 17 fields\n" + "-smbios type=41[,designation=str][,kind=str][,instance=%d][,pcidev=str]\n" + " specify SMBIOS type 41 fields\n", +- QEMU_ARCH_I386 | QEMU_ARCH_ARM) ++ QEMU_ARCH_I386 | QEMU_ARCH_ARM | QEMU_ARCH_LOONGARCH64) + SRST + ``-smbios file=binary`` + Load SMBIOS entry from binary file. +-- +2.27.0 + diff --git a/Modify-the-ioctl-command-of-kvm.patch b/Modify-the-ioctl-command-of-kvm.patch new file mode 100644 index 0000000000000000000000000000000000000000..9927a6306619d3aa46d21eaa978c9b43e6e441c8 --- /dev/null +++ b/Modify-the-ioctl-command-of-kvm.patch @@ -0,0 +1,32 @@ +From 01a90be04dd6dd7edb3f49feca1ff1500ccb551b Mon Sep 17 00:00:00 2001 +From: lixianglai +Date: Mon, 29 May 2023 08:44:26 -0400 +Subject: [PATCH 14/14] Modify the ioctl command of kvm. + +Signed-off-by: lixianglai +--- + linux-headers/linux/kvm.h | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h +index f99455294..1e6aed0fb 100644 +--- a/linux-headers/linux/kvm.h ++++ b/linux-headers/linux/kvm.h +@@ -2057,10 +2057,10 @@ struct kvm_loongarch_vcpu_state { + __u64 core_ext_ioisr[4]; + }; + +-#define KVM_CAP_LOONGARCH_FPU 165 +-#define KVM_CAP_LOONGARCH_LSX 166 +-#define KVM_CAP_LOONGARCH_VZ 167 +-#define KVM_REG_LOONGARCH 0x8000000000000000ULL ++#define KVM_CAP_LOONGARCH_FPU 800 ++#define KVM_CAP_LOONGARCH_LSX 801 ++#define KVM_CAP_LOONGARCH_VZ 802 ++#define KVM_REG_LOONGARCH 0x9000000000000000ULL + #define KVM_LARCH_GET_VCPU_STATE _IOR(KVMIO, 0xc0, struct kvm_loongarch_vcpu_state) + #define KVM_LARCH_SET_VCPU_STATE _IOW(KVMIO, 0xc1, struct kvm_loongarch_vcpu_state) + #define KVM_LARCH_GET_CPUCFG _IOR(KVMIO, 0xc2, struct kvm_cpucfg) +-- +2.27.0 + diff --git a/Support-TPM.patch b/Support-TPM.patch new file mode 100644 index 0000000000000000000000000000000000000000..6601bce96e9d6fceb0bf324d8611bad5aadc1825 --- /dev/null +++ b/Support-TPM.patch @@ -0,0 +1,518 @@ +From e7b5a4aea5499e793ef769d1c39161ab33870bb2 Mon Sep 17 00:00:00 2001 +From: lixianglai +Date: Mon, 29 May 2023 07:16:34 -0400 +Subject: [PATCH 04/14] Support TPM. + +Signed-off-by: lixianglai +--- + hw/loongarch/acpi-build.c | 44 +++++++ + hw/loongarch/larch_3a.c | 53 ++++++++- + hw/loongarch/larch_hotplug.c | 16 ++- + hw/loongarch/meson.build | 1 + + hw/loongarch/sysbus-fdt.c | 183 ++++++++++++++++++++++++++++++ + include/hw/loongarch/larch.h | 1 + + include/hw/loongarch/ls7a.h | 5 + + include/hw/loongarch/sysbus-fdt.h | 37 ++++++ + 8 files changed, 333 insertions(+), 7 deletions(-) + create mode 100644 hw/loongarch/sysbus-fdt.c + create mode 100644 include/hw/loongarch/sysbus-fdt.h + +diff --git a/hw/loongarch/acpi-build.c b/hw/loongarch/acpi-build.c +index 6ba637be5..682e016be 100644 +--- a/hw/loongarch/acpi-build.c ++++ b/hw/loongarch/acpi-build.c +@@ -58,6 +58,7 @@ + #include "hw/acpi/aml-build.h" + #include "hw/loongarch/larch.h" + #include "hw/loongarch/ls7a.h" ++#include "hw/platform-bus.h" + + #include "hw/acpi/ipmi.h" + #include "hw/acpi/ls7a.h" +@@ -474,7 +475,40 @@ static void build_ls7a_uart_device_aml(Aml *table) + aml_append(scope, dev); + aml_append(table, scope); + } ++#ifdef CONFIG_TPM ++static void acpi_dsdt_add_tpm(Aml *scope, LoongarchMachineState *vms) ++{ ++ PlatformBusDevice *pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev); ++ hwaddr pbus_base = VIRT_PLATFORM_BUS_BASEADDRESS; ++ SysBusDevice *sbdev = SYS_BUS_DEVICE(tpm_find()); ++ MemoryRegion *sbdev_mr; ++ hwaddr tpm_base; ++ ++ if (!sbdev) { ++ return; ++ } ++ ++ tpm_base = platform_bus_get_mmio_addr(pbus, sbdev, 0); ++ assert(tpm_base != -1); + ++ tpm_base += pbus_base; ++ ++ sbdev_mr = sysbus_mmio_get_region(sbdev, 0); ++ ++ Aml *dev = aml_device("TPM0"); ++ aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); ++ aml_append(dev, aml_name_decl("_STR", aml_string("TPM 2.0 Device"))); ++ aml_append(dev, aml_name_decl("_UID", aml_int(0))); ++ ++ Aml *crs = aml_resource_template(); ++ aml_append(crs, ++ aml_memory32_fixed(tpm_base, ++ (uint32_t)memory_region_size(sbdev_mr), ++ AML_READ_WRITE)); ++ aml_append(dev, aml_name_decl("_CRS", crs)); ++ aml_append(scope, dev); ++} ++#endif + static void + build_dsdt(GArray *table_data, BIOSLinker *linker, MachineState *machine) + { +@@ -500,6 +534,10 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, MachineState *machine) + aml_append(dev, aml_name_decl("_UID", aml_int(1))); + aml_append(dev, build_ls7a_osc_method()); + aml_append(sb_scope, dev); ++ ++#ifdef CONFIG_TPM ++ acpi_dsdt_add_tpm(sb_scope, lsms); ++#endif + aml_append(dsdt, sb_scope); + + build_ls7a_pci0_int(dsdt); +@@ -633,6 +671,12 @@ void acpi_build(AcpiBuildTables *tables, MachineState *machine) + lsms->oem_table_id); + } + ++ if (tpm_get_version(tpm_find()) == TPM_VERSION_2_0) { ++ acpi_add_table(table_offsets, tables_blob); ++ build_tpm2(tables_blob, tables->linker, tables->tcpalog, ++ lsms->oem_id, lsms->oem_table_id); ++ } ++ + /* Build mcfg */ + acpi_add_table(table_offsets, tables_blob); + { +diff --git a/hw/loongarch/larch_3a.c b/hw/loongarch/larch_3a.c +index 3194a822c..6c2602050 100644 +--- a/hw/loongarch/larch_3a.c ++++ b/hw/loongarch/larch_3a.c +@@ -52,6 +52,7 @@ + #include "hw/rtc/mc146818rtc.h" + #include "hw/irq.h" + #include "net/net.h" ++#include "hw/platform-bus.h" + #include "hw/timer/i8254.h" + #include "hw/loongarch/larch.h" + #include "hw/loongarch/ls7a.h" +@@ -65,6 +66,8 @@ + #include "sysemu/device_tree.h" + #include "qapi/visitor.h" + #include "qapi/qapi-visit-common.h" ++#include "sysemu/tpm.h" ++#include "hw/loongarch/sysbus-fdt.h" + + #include + +@@ -1235,6 +1238,19 @@ void loongarch_machine_done(Notifier *notifier, void *data) + { + LoongarchMachineState *lsms = container_of(notifier, + LoongarchMachineState, machine_done); ++ ++ platform_bus_add_all_fdt_nodes(lsms->fdt, NULL, ++ VIRT_PLATFORM_BUS_BASEADDRESS, ++ VIRT_PLATFORM_BUS_SIZE, ++ VIRT_PLATFORM_BUS_IRQ); ++ ++ qemu_fdt_dumpdtb(lsms->fdt, lsms->fdt_size); ++ /* load fdt */ ++ MemoryRegion *fdt_rom = g_new(MemoryRegion, 1); ++ memory_region_init_rom(fdt_rom, NULL, "fdt", LS_FDT_SIZE, &error_fatal); ++ memory_region_add_subregion(get_system_memory(), LS_FDT_BASE, fdt_rom); ++ rom_add_blob_fixed("fdt", lsms->fdt, lsms->fdt_size, LS_FDT_BASE); ++ + loongarch_acpi_setup(); + loongarch_build_smbios(lsms); + } +@@ -1562,7 +1578,31 @@ static void fdt_add_pcie_node(const LoongarchMachineState *lsms) + 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, + 2, base_mmio, 2, size_mmio); + g_free(nodename); +- qemu_fdt_dumpdtb(lsms->fdt, lsms->fdt_size); ++} ++ ++static void create_platform_bus(LoongarchMachineState *s, qemu_irq *pic) ++{ ++ DeviceState *dev; ++ SysBusDevice *sysbus; ++ int i; ++ MemoryRegion *sysmem = get_system_memory(); ++ ++ dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); ++ dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); ++ qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS); ++ qdev_prop_set_uint32(dev, "mmio_size", VIRT_PLATFORM_BUS_SIZE); ++ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); ++ s->platform_bus_dev = dev; ++ ++ sysbus = SYS_BUS_DEVICE(dev); ++ for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) { ++ int irq = VIRT_PLATFORM_BUS_IRQ + i; ++ sysbus_connect_irq(sysbus, i, pic[irq - LOONGARCH_PCH_IRQ_BASE]); ++ } ++ ++ memory_region_add_subregion(sysmem, ++ VIRT_PLATFORM_BUS_BASEADDRESS, ++ sysbus_mmio_get_region(sysbus, 0)); + } + + static void ls3a5k_init(MachineState *args) +@@ -1784,6 +1824,8 @@ static void ls3a5k_init(MachineState *args) + object_property_set_link(OBJECT(machine), LOONGARCH_MACHINE_ACPI_DEVICE_PROP, + OBJECT(ls7a_dev), &error_abort); + ++ create_platform_bus(lsms, ls7a_apic); ++ + #ifdef CONFIG_KVM + if (kvm_enabled()) { + kvm_direct_msi_allowed = (kvm_check_extension(kvm_state, +@@ -1835,11 +1877,6 @@ static void ls3a5k_init(MachineState *args) + + fdt_add_pcie_node(lsms); + +- /* load fdt */ +- MemoryRegion *fdt_rom = g_new(MemoryRegion, 1); +- memory_region_init_rom(fdt_rom, NULL, "fdt", LS_FDT_SIZE, &error_fatal); +- memory_region_add_subregion(get_system_memory(), LS_FDT_BASE, fdt_rom); +- rom_add_blob_fixed("fdt", lsms->fdt, lsms->fdt_size, LS_FDT_BASE); + } + + static const CPUArchIdList *loongarch_possible_cpu_arch_ids(MachineState *ms) +@@ -1986,6 +2023,10 @@ static void loongarch_class_init(ObjectClass *oc, void *data) + mc->default_cpu_type = LOONGARCH_CPU_TYPE_NAME("Loongson-3A5000"); + mc->default_ram_id = "loongarch_ls3a.ram"; + ++#ifdef CONFIG_TPM ++ machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); ++#endif ++ + mc->reset = ls3a_board_reset; + mc->max_cpus = LOONGARCH_MAX_VCPUS; + hc->pre_plug = loongarch_machine_device_pre_plug; +diff --git a/hw/loongarch/larch_hotplug.c b/hw/loongarch/larch_hotplug.c +index 7bce95712..bb3e9826b 100644 +--- a/hw/loongarch/larch_hotplug.c ++++ b/hw/loongarch/larch_hotplug.c +@@ -32,6 +32,7 @@ + #include "hw/loongarch/larch.h" + #include "hw/cpu/core.h" + #include "hw/nvram/fw_cfg.h" ++#include "hw/platform-bus.h" + + /* find cpu slot in machine->possible_cpus by core_id */ + static CPUArchId *loongarch_find_cpu_slot(MachineState *ms, uint32_t id, +@@ -327,7 +328,8 @@ HotplugHandler *loongarch_get_hotpug_handler(MachineState *machine, + DeviceState *dev) + { + if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || +- object_dynamic_cast(OBJECT(dev), TYPE_LOONGARCH_CPU)) { ++ object_dynamic_cast(OBJECT(dev), TYPE_LOONGARCH_CPU) || ++ object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE)) { + return HOTPLUG_HANDLER(machine); + } + return NULL; +@@ -346,6 +348,18 @@ void loongarch_machine_device_pre_plug(HotplugHandler *hotplug_dev, + void loongarch_machine_device_plug(HotplugHandler *hotplug_dev, + DeviceState *dev, Error **errp) + { ++ LoongarchMachineState *lsms = LoongarchMACHINE(hotplug_dev); ++ ++ if (lsms->platform_bus_dev) { ++ MachineClass *mc = MACHINE_GET_CLASS(lsms); ++ ++ if (device_is_dynamic_sysbus(mc, dev)) { ++ platform_bus_link_device( ++ PLATFORM_BUS_DEVICE(lsms->platform_bus_dev), ++ SYS_BUS_DEVICE(dev)); ++ } ++ } ++ + if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { + loongarch_memory_plug(hotplug_dev, dev, errp); + } else if (object_dynamic_cast(OBJECT(dev), TYPE_LOONGARCH_CPU)) { +diff --git a/hw/loongarch/meson.build b/hw/loongarch/meson.build +index 81ee99a02..47d886ddd 100644 +--- a/hw/loongarch/meson.build ++++ b/hw/loongarch/meson.build +@@ -9,6 +9,7 @@ loongarch_ss.add(files( + 'ipi.c', + 'apic.c', + 'iocsr.c', ++ 'sysbus-fdt.c', + )) + + hw_arch += {'loongarch64': loongarch_ss} +diff --git a/hw/loongarch/sysbus-fdt.c b/hw/loongarch/sysbus-fdt.c +new file mode 100644 +index 000000000..f750ad6b6 +--- /dev/null ++++ b/hw/loongarch/sysbus-fdt.c +@@ -0,0 +1,183 @@ ++/* ++ * Loongarch Platform Bus device tree generation helpers ++ * ++ * Copyright (c) 2014 Linaro Limited ++ * ++ * Authors: ++ * Alex Graf ++ * Eric Auger ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2 or later, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program. If not, see . ++ * ++ */ ++ ++#include "qemu/osdep.h" ++#include "qapi/error.h" ++#include ++#include "qemu/error-report.h" ++#include "sysemu/device_tree.h" ++#include "hw/platform-bus.h" ++#include "hw/display/ramfb.h" ++#include "hw/loongarch/sysbus-fdt.h" ++#include "sysemu/tpm.h" ++ ++/* ++ * internal struct that contains the information to create dynamic ++ * sysbus device node ++ */ ++typedef struct PlatformBusFDTData { ++ void *fdt; /* device tree handle */ ++ int irq_start; /* index of the first IRQ usable by platform bus devices */ ++ const char *pbus_node_name; /* name of the platform bus node */ ++ PlatformBusDevice *pbus; ++} PlatformBusFDTData; ++ ++/* struct that allows to match a device and create its FDT node */ ++typedef struct BindingEntry { ++ const char *typename; ++ const char *compat; ++ int (*add_fn)(SysBusDevice *sbdev, void *opaque); ++ bool (*match_fn)(SysBusDevice *sbdev, const struct BindingEntry *combo); ++} BindingEntry; ++ ++ ++ ++static int no_fdt_node(SysBusDevice *sbdev, void *opaque) ++{ ++ return 0; ++} ++ ++/* Device type based matching */ ++static bool type_match(SysBusDevice *sbdev, const BindingEntry *entry) ++{ ++ return !strcmp(object_get_typename(OBJECT(sbdev)), entry->typename); ++} ++ ++#define TYPE_BINDING(type, add_fn) {(type), NULL, (add_fn), NULL} ++ ++#ifdef CONFIG_TPM ++/* ++ * add_tpm_tis_fdt_node: Create a DT node for TPM TIS ++ * ++ * See kernel documentation: ++ * Documentation/devicetree/bindings/security/tpm/tpm_tis_mmio.txt ++ * Optional interrupt for command completion is not exposed ++ */ ++static int add_tpm_tis_fdt_node(SysBusDevice *sbdev, void *opaque) ++{ ++ PlatformBusFDTData *data = opaque; ++ PlatformBusDevice *pbus = data->pbus; ++ void *fdt = data->fdt; ++ const char *parent_node = data->pbus_node_name; ++ char *nodename; ++ uint32_t reg_attr[2]; ++ uint64_t mmio_base; ++ ++ mmio_base = platform_bus_get_mmio_addr(pbus, sbdev, 0); ++ nodename = g_strdup_printf("%s/tpm_tis@%" PRIx64, parent_node, mmio_base); ++ qemu_fdt_add_subnode(fdt, nodename); ++ ++ qemu_fdt_setprop_string(fdt, nodename, "compatible", "tcg,tpm-tis-mmio"); ++ ++ reg_attr[0] = cpu_to_be32(mmio_base); ++ reg_attr[1] = cpu_to_be32(0x5000); ++ qemu_fdt_setprop(fdt, nodename, "reg", reg_attr, 2 * sizeof(uint32_t)); ++ ++ g_free(nodename); ++ ++ return 0; ++} ++#endif ++ ++/* list of supported dynamic sysbus bindings */ ++static const BindingEntry bindings[] = { ++#ifdef CONFIG_TPM ++ TYPE_BINDING(TYPE_TPM_TIS_SYSBUS, add_tpm_tis_fdt_node), ++#endif ++ TYPE_BINDING(TYPE_RAMFB_DEVICE, no_fdt_node), ++ TYPE_BINDING("", NULL), /* last element */ ++}; ++ ++/* Generic Code */ ++ ++/** ++ * add_fdt_node - add the device tree node of a dynamic sysbus device ++ * ++ * @sbdev: handle to the sysbus device ++ * @opaque: handle to the PlatformBusFDTData ++ * ++ * Checks the sysbus type belongs to the list of device types that ++ * are dynamically instantiable and if so call the node creation ++ * function. ++ */ ++static void add_fdt_node(SysBusDevice *sbdev, void *opaque) ++{ ++ int i, ret; ++ ++ for (i = 0; i < ARRAY_SIZE(bindings); i++) { ++ const BindingEntry *iter = &bindings[i]; ++ ++ if (type_match(sbdev, iter)) { ++ if (!iter->match_fn || iter->match_fn(sbdev, iter)) { ++ ret = iter->add_fn(sbdev, opaque); ++ assert(!ret); ++ return; ++ } ++ } ++ } ++ error_report("Device %s can not be dynamically instantiated", ++ qdev_fw_name(DEVICE(sbdev))); ++ exit(1); ++} ++ ++void platform_bus_add_all_fdt_nodes(void *fdt, const char *intc, hwaddr addr, ++ hwaddr bus_size, int irq_start) ++{ ++ const char platcomp[] = "qemu,platform\0simple-bus"; ++ PlatformBusDevice *pbus; ++ DeviceState *dev; ++ gchar *node; ++ ++ assert(fdt); ++ ++ node = g_strdup_printf("/platform@%"PRIx64, addr); ++ ++ /* Create a /platform node that we can put all devices into */ ++ qemu_fdt_add_subnode(fdt, node); ++ qemu_fdt_setprop(fdt, node, "compatible", platcomp, sizeof(platcomp)); ++ ++ /* ++ * Our platform bus region is less than 32bits, so 1 cell is enough for ++ * address and size ++ */ ++ qemu_fdt_setprop_cells(fdt, node, "#size-cells", 1); ++ qemu_fdt_setprop_cells(fdt, node, "#address-cells", 1); ++ qemu_fdt_setprop_cells(fdt, node, "ranges", 0, addr >> 32, addr, bus_size); ++ if (intc != NULL) { ++ qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", intc); ++ } ++ dev = qdev_find_recursive(sysbus_get_default(), TYPE_PLATFORM_BUS_DEVICE); ++ pbus = PLATFORM_BUS_DEVICE(dev); ++ ++ PlatformBusFDTData data = { ++ .fdt = fdt, ++ .irq_start = irq_start, ++ .pbus_node_name = node, ++ .pbus = pbus, ++ }; ++ ++ /* Loop through all dynamic sysbus devices and create their node */ ++ foreach_dynamic_sysbus_device(add_fdt_node, &data); ++ ++ g_free(node); ++} +diff --git a/include/hw/loongarch/larch.h b/include/hw/loongarch/larch.h +index 62e2830e2..81dcb78f4 100644 +--- a/include/hw/loongarch/larch.h ++++ b/include/hw/loongarch/larch.h +@@ -103,6 +103,7 @@ typedef struct LoongarchMachineState { + void *fdt; + int fdt_size; + unsigned int hotpluged_cpu_num; ++ DeviceState *platform_bus_dev; + OnOffAuto acpi; + char *oem_id; + char *oem_table_id; +diff --git a/include/hw/loongarch/ls7a.h b/include/hw/loongarch/ls7a.h +index 686af763a..fc78083be 100644 +--- a/include/hw/loongarch/ls7a.h ++++ b/include/hw/loongarch/ls7a.h +@@ -121,6 +121,11 @@ + #define INT_ROUTER_REGS_CORE2_INTISR 0x50 + #define INT_ROUTER_REGS_CORE3_INTISR 0x58 + ++#define VIRT_PLATFORM_BUS_BASEADDRESS 0x16000000 ++#define VIRT_PLATFORM_BUS_SIZE 0x2000000 ++#define VIRT_PLATFORM_BUS_NUM_IRQS 2 ++#define VIRT_PLATFORM_BUS_IRQ 69 ++ + typedef struct LS7APCIState LS7APCIState; + typedef struct LS7APCIEHost { + PCIExpressHost parent_obj; +diff --git a/include/hw/loongarch/sysbus-fdt.h b/include/hw/loongarch/sysbus-fdt.h +new file mode 100644 +index 000000000..340c382cd +--- /dev/null ++++ b/include/hw/loongarch/sysbus-fdt.h +@@ -0,0 +1,37 @@ ++/* ++ * Dynamic sysbus device tree node generation API ++ * ++ * Copyright Linaro Limited, 2014 ++ * ++ * Authors: ++ * Alex Graf ++ * Eric Auger ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2 or later, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program. If not, see . ++ * ++ */ ++ ++#ifndef HW_ARM_SYSBUS_FDT_H ++#define HW_ARM_SYSBUS_FDT_H ++ ++#include "exec/hwaddr.h" ++ ++/** ++ * platform_bus_add_all_fdt_nodes - create all the platform bus nodes ++ * ++ * builds the parent platform bus node and all the nodes of dynamic ++ * sysbus devices attached to it. ++ */ ++void platform_bus_add_all_fdt_nodes(void *fdt, const char *intc, hwaddr addr, ++ hwaddr bus_size, int irq_start); ++#endif +-- +2.27.0 + diff --git a/Support-vfio-config.patch b/Support-vfio-config.patch new file mode 100644 index 0000000000000000000000000000000000000000..6ae48b9e6f294de12b92be1c7df4ad7491c45a7b --- /dev/null +++ b/Support-vfio-config.patch @@ -0,0 +1,47 @@ +From 16268ffb6e5abbb5369a6a6bda9c60cd5fff22c9 Mon Sep 17 00:00:00 2001 +From: lixianglai +Date: Mon, 29 May 2023 07:41:14 -0400 +Subject: [PATCH 08/14] Support vfio config + +Signed-off-by: lixianglai +--- + configs/devices/loongarch64-softmmu/default.mak | 9 +++++++++ + .../loongarch64-softmmu/loongarch64-rh-devices.mak | 8 ++++++++ + 2 files changed, 17 insertions(+) + +diff --git a/configs/devices/loongarch64-softmmu/default.mak b/configs/devices/loongarch64-softmmu/default.mak +index fcb7e45dd..b4994d8a6 100644 +--- a/configs/devices/loongarch64-softmmu/default.mak ++++ b/configs/devices/loongarch64-softmmu/default.mak +@@ -152,3 +152,12 @@ CONFIG_PLATFORM_BUS=y + CONFIG_TPM_TIS_SYSBUS=y + CONFIG_ACPI_LOONGARCH=y + CONFIG_LS7A_RTC=y ++ ++#vfio config ++CONFIG_VFIO=y ++CONFIG_VFIO_PCI=y ++CONFIG_VFIO_PLATFORM=y ++CONFIG_VFIO_XGMAC=y ++CONFIG_VFIO_AMD_XGBE=y ++ ++ +diff --git a/configs/devices/loongarch64-softmmu/loongarch64-rh-devices.mak b/configs/devices/loongarch64-softmmu/loongarch64-rh-devices.mak +index e7b5bdc8e..696ee9b72 100644 +--- a/configs/devices/loongarch64-softmmu/loongarch64-rh-devices.mak ++++ b/configs/devices/loongarch64-softmmu/loongarch64-rh-devices.mak +@@ -153,3 +153,11 @@ CONFIG_PLATFORM_BUS=y + CONFIG_TPM_TIS_SYSBUS=y + CONFIG_ACPI_LOONGARCH=y + CONFIG_LS7A_RTC=y ++ ++#vfio config ++CONFIG_VFIO=y ++CONFIG_VFIO_PCI=y ++CONFIG_VFIO_PLATFORM=y ++CONFIG_VFIO_XGMAC=y ++CONFIG_VFIO_AMD_XGBE=y ++ +-- +2.27.0 + diff --git a/address-space-code-cleanup-on-7A-virt-machine.patch b/address-space-code-cleanup-on-7A-virt-machine.patch new file mode 100644 index 0000000000000000000000000000000000000000..1e64b4c5c64f52aa35ef8c94672f8055f4ac614e --- /dev/null +++ b/address-space-code-cleanup-on-7A-virt-machine.patch @@ -0,0 +1,276 @@ +From fe4009a9b0ddc2058793d3dc782778c95164ef39 Mon Sep 17 00:00:00 2001 +From: lixianglai +Date: Mon, 29 May 2023 07:33:26 -0400 +Subject: [PATCH 06/14] address space code cleanup on 7A virt-machine. + +Signed-off-by: lixianglai +--- + hw/loongarch/larch_3a.c | 16 +++----- + hw/loongarch/ls7a_nb.c | 49 ------------------------- + include/hw/loongarch/larch.h | 1 - + include/hw/loongarch/ls7a.h | 71 ++++++++++++++++-------------------- + 4 files changed, 37 insertions(+), 100 deletions(-) + +diff --git a/hw/loongarch/larch_3a.c b/hw/loongarch/larch_3a.c +index 6c2602050..6eaa53d74 100644 +--- a/hw/loongarch/larch_3a.c ++++ b/hw/loongarch/larch_3a.c +@@ -88,10 +88,8 @@ + + #ifdef CONFIG_KVM + #define LS_ISA_IO_SIZE 0x02000000 +-#define LS_ISA_MEM_SIZE 0x40000000 + #else + #define LS_ISA_IO_SIZE 0x00010000 +-#define LS_ISA_MEM_SIZE 0x01000000 + #endif + + #ifdef CONFIG_KVM +@@ -626,8 +624,8 @@ static struct irq_source_routing_table *init_irq_source(void *g_irq_source) + irq_info->ht_enable = 0x0000d17b; + irq_info->node_id = 0; + +- irq_info->pci_mem_start_addr = LS_ISA_MEM_BASE; +- irq_info->pci_mem_end_addr = irq_info->pci_mem_start_addr + LS_ISA_MEM_SIZE - 1; ++ irq_info->pci_mem_start_addr = PCIE_MEMORY_BASE; ++ irq_info->pci_mem_end_addr = irq_info->pci_mem_start_addr + PCIE_MEMORY_SIZE - 1; + + if (strstr(lsmc->cpu_name, "5000")) { + irq_info->pci_io_start_addr = LS3A5K_ISA_IO_BASE; +@@ -1551,8 +1549,8 @@ static void fdt_add_fw_cfg_node(const LoongarchMachineState *lsms) + static void fdt_add_pcie_node(const LoongarchMachineState *lsms) + { + char *nodename; +- hwaddr base_mmio = LS_ISA_MEM_BASE; +- hwaddr size_mmio = LS_ISA_MEM_SIZE; ++ hwaddr base_mmio = PCIE_MEMORY_BASE; ++ hwaddr size_mmio = PCIE_MEMORY_SIZE; + hwaddr base_pio = LS3A5K_ISA_IO_BASE; + hwaddr size_pio = LS_ISA_IO_SIZE; + hwaddr base_pcie = LS_PCIECFG_BASE; +@@ -1650,7 +1648,6 @@ static void ls3a5k_init(MachineState *args) + create_fdt(lsms); + + DPRINTF("isa 0x%lx\n", lsmc->isa_io_base); +- DPRINTF("ht1lo 0x%lx\n", lsmc->ht1lo_pcicfg_base); + DPRINTF("cpu_name %s bridge_name %s\n", + lsmc->cpu_name, lsmc->bridge_name); + +@@ -1800,9 +1797,9 @@ static void ls3a5k_init(MachineState *args) + + memory_region_init_alias(isa_io, NULL, "isa-io", + get_system_io(), 0, LS_ISA_IO_SIZE); +- memory_region_init(isa_mem, NULL, "isa-mem", LS_ISA_MEM_SIZE); ++ memory_region_init(isa_mem, NULL, "isa-mem", PCIE_MEMORY_SIZE); + memory_region_add_subregion(get_system_memory(), lsmc->isa_io_base, isa_io); +- memory_region_add_subregion(get_system_memory(), LS_ISA_MEM_BASE, isa_mem); ++ memory_region_add_subregion(get_system_memory(), PCIE_MEMORY_BASE, isa_mem); + + if (!strcmp(lsmc->bridge_name, "ls7a")) { + /*Initialize the 7A IO interrupt subsystem*/ +@@ -1950,7 +1947,6 @@ static void ls3a5k_ls7a_machine_options(MachineClass *m) + m->alias = "loongson7a"; + m->is_default = 1; + lsmc->isa_io_base = LS3A5K_ISA_IO_BASE; +- lsmc->ht1lo_pcicfg_base = LS3A5K_HT1LO_PCICFG_BASE; + lsmc->pciecfg_base = LS_PCIECFG_BASE; + lsmc->ls7a_ioapic_reg_base = LS3A5K_LS7A_IOAPIC_REG_BASE; + lsmc->node_shift = 44; +diff --git a/hw/loongarch/ls7a_nb.c b/hw/loongarch/ls7a_nb.c +index 5a500fbd5..5a231e6f0 100644 +--- a/hw/loongarch/ls7a_nb.c ++++ b/hw/loongarch/ls7a_nb.c +@@ -108,7 +108,6 @@ static const VMStateDescription vmstate_ls7a_pcie = { + .fields = (VMStateField[]) { + VMSTATE_PCI_DEVICE(dev, LS7APCIState), + VMSTATE_STRUCT(pm, LS7APCIState, 0, vmstate_ls7a_pm, LS7APCIPMRegs), +- VMSTATE_UINT32_ARRAY(regs, LS7APCIState, LS7A_REGS), + VMSTATE_END_OF_LIST() + } + }; +@@ -153,47 +152,6 @@ static void ls7a_pcie_realize(PCIDevice *dev, Error **errp) + qemu_register_reset(ls7a_reset, s); + } + +-static void pci_ls7a_config_write(void *opaque, hwaddr addr, +- uint64_t val, unsigned size) +-{ +- hwaddr tmp_addr; +- tmp_addr = addr & 0xffffff; +- +- pci_data_write(opaque, tmp_addr, val, size); +-} +- +-static uint64_t pci_ls7a_config_read(void *opaque, +- hwaddr addr, unsigned size) +-{ +- uint64_t val; +- hwaddr tmp_addr; +- +- tmp_addr = addr & 0xffffff; +- val = pci_data_read(opaque, tmp_addr, size); +- +- if (addr & 0x3c) { +- DPRINTF(TARGET_FMT_plx" val %lx\n", addr, val); +- } +- return val; +-} +- +-static const MemoryRegionOps pci_ls7a_config_ops = { +- .read = pci_ls7a_config_read, +- .write = pci_ls7a_config_write, +- /* Set to access 64bits data, because default to 32bits*/ +- .valid = { +- .min_access_size = 1, +- .max_access_size = 4, +- }, +- /* Set to access 64bits data, because default to 32bits*/ +- .impl = { +- .min_access_size = 1, +- .max_access_size = 4, +- }, +- .endianness = DEVICE_NATIVE_ENDIAN, +- +-}; +- + static AddressSpace *ls7a_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn) + { + return &address_space_memory; +@@ -205,12 +163,9 @@ static PCIBus *pci_ls7a_init(MachineState *machine, DeviceState *dev, + LoongarchMachineState *lsms = LoongarchMACHINE(machine); + LoongarchMachineClass *lsmc = LoongarchMACHINE_GET_CLASS(lsms); + PCIExpressHost *e; +- SysBusDevice *sysbus; +- MemoryRegion *iomem = g_new(MemoryRegion, 1); + PCIHostState *phb; + + e = PCIE_HOST_BRIDGE(dev); +- sysbus = SYS_BUS_DEVICE(e); + phb = PCI_HOST_BRIDGE(e); + phb->bus = pci_register_root_bus(dev, "pcie.0", pci_ls7a_set_irq, + pci_ls7a_map_irq, pic, +@@ -220,10 +175,6 @@ static PCIBus *pci_ls7a_init(MachineState *machine, DeviceState *dev, + DPRINTF("------ %d\n", __LINE__); + + pci_bus_set_route_irq_fn(phb->bus, ls7a_route_intx_pin_to_irq); +- memory_region_init_io(iomem, NULL, &pci_ls7a_config_ops, phb->bus, +- "ls7a_pci_conf", HT1LO_PCICFG_SIZE); +- sysbus_init_mmio(sysbus, iomem); +- sysbus_mmio_map(sysbus, 0, lsmc->ht1lo_pcicfg_base); + + return phb->bus; + } +diff --git a/include/hw/loongarch/larch.h b/include/hw/loongarch/larch.h +index 81dcb78f4..b8f28e330 100644 +--- a/include/hw/loongarch/larch.h ++++ b/include/hw/loongarch/larch.h +@@ -64,7 +64,6 @@ typedef struct LoongarchMachineClass { + uint64_t ht_control_regs_base; + uint64_t hpet_mmio_addr; + uint64_t smbus_cfg_base; +- uint64_t ht1lo_pcicfg_base; + uint64_t pciecfg_base; + uint64_t ls7a_ioapic_reg_base; + uint32_t node_shift; +diff --git a/include/hw/loongarch/ls7a.h b/include/hw/loongarch/ls7a.h +index fc78083be..63a070296 100644 +--- a/include/hw/loongarch/ls7a.h ++++ b/include/hw/loongarch/ls7a.h +@@ -39,44 +39,33 @@ + #define ACPI_IO_SIZE (LS7A_ACPI_IO_SIZE) + #define ACPI_SCI_IRQ (LS7A_SCI_IRQ) + +-#define LS3A5K_ISA_IO_BASE 0x18000000UL +-#define LS_ISA_MEM_BASE 0x40000000 +-#define LS3A5K_HT1LO_PCICFG_BASE 0x1a000000 +-#define HT1LO_PCICFG_SIZE 0x02000000 ++#define VIRT_PLATFORM_BUS_BASEADDRESS 0x16000000 ++#define VIRT_PLATFORM_BUS_SIZE 0x02000000 ++#define VIRT_PLATFORM_BUS_NUM_IRQS 2 ++#define VIRT_PLATFORM_BUS_IRQ (LOONGARCH_PCH_IRQ_BASE + 5) ++ ++#define LS3A5K_ISA_IO_BASE 0x18000000UL + #define LS_BIOS_BASE 0x1c000000 + #define LS_BIOS_VAR_BASE 0x1c3a0000 +-#define LS_BIOS_SIZE (4 * 1024 * 1024) +- +-#define FW_CFG_ADDR 0x1e020000 +-#define LS7A_REG_BASE 0x1FE00000 +-#define LS7A_PCICONFIG_BASE (LS7A_REG_BASE + 0x30) +-#define LS7A_PCICONFIG_SIZE (0x100) +-#define LS7A_INTERNAL_REG_BASE (LS7A_REG_BASE + 0x100) +-#define LS7A_INTERNAL_REG_SIZE (0xE0) +-#define LS7A_REGS (0xE0 >> 2) +-#define LS7A_UART_BASE 0x1fe001e0 +-#define LS7A_UART_LEN 0x8 +- +-#define LS_FDT_BASE 0x1c400000 +-#define LS_FDT_SIZE 0x100000 +- +-#define LS_PCIECFG_BASE 0x20000000 +-#define LS_PCIECFG_SIZE 0x08000000 +-#define MSI_ADDR_LOW 0x2FF00000 +-#define MSI_ADDR_HI 0x0 +- ++#define LS_BIOS_SIZE (4 * 1024 * 1024) ++#define LS_FDT_BASE 0x1c400000 ++#define LS_FDT_SIZE 0x00100000 ++ ++#define FW_CFG_ADDR 0x1e020000 ++#define LS7A_REG_BASE 0x1FE00000 ++#define LS7A_UART_BASE 0x1fe001e0 ++#define LS7A_UART_LEN 0x8 + #define SMP_GIPI_MAILBOX 0x1f000000ULL +-#define CORE0_STATUS_OFF 0x000 +-#define CORE0_EN_OFF 0x004 +-#define CORE0_SET_OFF 0x008 +-#define CORE0_CLEAR_OFF 0x00c +-#define CORE0_BUF_20 0x020 +-#define CORE0_BUF_28 0x028 +-#define CORE0_BUF_30 0x030 +-#define CORE0_BUF_38 0x038 +-#define CORE0_IPI_SEND 0x040 +-#define CORE0_MAIL_SEND 0x048 +- ++#define CORE0_STATUS_OFF 0x000 ++#define CORE0_EN_OFF 0x004 ++#define CORE0_SET_OFF 0x008 ++#define CORE0_CLEAR_OFF 0x00c ++#define CORE0_BUF_20 0x020 ++#define CORE0_BUF_28 0x028 ++#define CORE0_BUF_30 0x030 ++#define CORE0_BUF_38 0x038 ++#define CORE0_IPI_SEND 0x040 ++#define CORE0_MAIL_SEND 0x048 + #define INT_ROUTER_REGS_BASE 0x1fe01400UL + #define INT_ROUTER_REGS_SIZE 0x100 + #define INT_ROUTER_REGS_SYS_INT0 0x00 +@@ -121,10 +110,13 @@ + #define INT_ROUTER_REGS_CORE2_INTISR 0x50 + #define INT_ROUTER_REGS_CORE3_INTISR 0x58 + +-#define VIRT_PLATFORM_BUS_BASEADDRESS 0x16000000 +-#define VIRT_PLATFORM_BUS_SIZE 0x2000000 +-#define VIRT_PLATFORM_BUS_NUM_IRQS 2 +-#define VIRT_PLATFORM_BUS_IRQ 69 ++#define LS_PCIECFG_BASE 0x20000000 ++#define LS_PCIECFG_SIZE 0x08000000 ++#define MSI_ADDR_LOW 0x2FF00000 ++#define MSI_ADDR_HI 0x0 ++ ++#define PCIE_MEMORY_BASE 0x40000000 ++#define PCIE_MEMORY_SIZE 0x40000000 + + typedef struct LS7APCIState LS7APCIState; + typedef struct LS7APCIEHost { +@@ -136,7 +128,6 @@ struct LS7APCIState { + PCIDevice dev; + + LS7APCIEHost *pciehost; +- uint32_t regs[LS7A_REGS]; + + /* LS7A registers */ + MemoryRegion iomem; +-- +2.27.0 + diff --git a/code-cleanup-for-loongarch-kvm.patch b/code-cleanup-for-loongarch-kvm.patch new file mode 100644 index 0000000000000000000000000000000000000000..a4bbf4bfcbe820eb16c9a58cf024abd7da16992b --- /dev/null +++ b/code-cleanup-for-loongarch-kvm.patch @@ -0,0 +1,34 @@ +From 1ab7b25cd4b5d827e8b04c981293b135059681ad Mon Sep 17 00:00:00 2001 +From: lixianglai +Date: Mon, 29 May 2023 07:04:10 -0400 +Subject: [PATCH 03/14] code cleanup for loongarch kvm. + +Signed-off-by: lixianglai +--- + linux-headers/asm-loongarch64/kvm.h | 10 +--------- + 1 file changed, 1 insertion(+), 9 deletions(-) + +diff --git a/linux-headers/asm-loongarch64/kvm.h b/linux-headers/asm-loongarch64/kvm.h +index a24375ee5..799af7594 100644 +--- a/linux-headers/asm-loongarch64/kvm.h ++++ b/linux-headers/asm-loongarch64/kvm.h +@@ -72,15 +72,7 @@ struct kvm_fpu { + * + * Register set = 0: GP registers from kvm_regs (see definitions below). + * +- * Register set = 1: CP0 registers. +- * bits[15..8] - COP0 register set. +- * +- * COP0 register set = 0: Main CP0 registers. +- * bits[7..3] - Register 'rd' index. +- * bits[2..0] - Register 'sel' index. +- * +- * COP0 register set = 1: MAARs. +- * bits[7..0] - MAAR index. ++ * Register set = 1: CSR registers. + * + * Register set = 2: KVM specific registers (see definitions below). + * +-- +2.27.0 + diff --git a/fix-smbios-type4-info-for-numa-support.patch b/fix-smbios-type4-info-for-numa-support.patch new file mode 100644 index 0000000000000000000000000000000000000000..948aab789f2967cd5d15ced74b604804bcc70053 --- /dev/null +++ b/fix-smbios-type4-info-for-numa-support.patch @@ -0,0 +1,44 @@ +From d68ddb24ed08459b9641615e00cec50e6d025a5e Mon Sep 17 00:00:00 2001 +From: lixianglai +Date: Mon, 29 May 2023 07:53:36 -0400 +Subject: [PATCH 11/14] fix smbios type4 info for numa support. + +Signed-off-by: lixianglai +--- + hw/loongarch/larch_3a.c | 12 +++++++++++- + 1 file changed, 11 insertions(+), 1 deletion(-) + +diff --git a/hw/loongarch/larch_3a.c b/hw/loongarch/larch_3a.c +index 5e271f339..b1501e0ea 100644 +--- a/hw/loongarch/larch_3a.c ++++ b/hw/loongarch/larch_3a.c +@@ -1211,8 +1211,14 @@ static void loongarch_build_smbios(LoongarchMachineState *lsms) + uint8_t *smbios_tables, *smbios_anchor; + size_t smbios_tables_len, smbios_anchor_len; + const char *product = "QEMU Virtual Machine"; +- ms->smp.cores = 4; ++ int nb_numa_nodes, smp_cpus; + ++ smp_cpus = ms->smp.cpus; ++ nb_numa_nodes = ms->numa_state->num_nodes; ++ if (nb_numa_nodes == 0) { ++ nb_numa_nodes = 1; ++ } ++ ms->smp.cores = smp_cpus / nb_numa_nodes; + if (!lsms->fw_cfg) { + return; + } +@@ -2004,6 +2010,10 @@ static int64_t ls3a_get_default_cpu_node_id(const MachineState *ms, int idx) + { + int nb_numa_nodes = ms->numa_state->num_nodes; + int smp_cores = ms->smp.cores; ++ ++ if (nb_numa_nodes == 0) { ++ nb_numa_nodes = 1; ++ } + return idx / smp_cores % nb_numa_nodes; + } + +-- +2.27.0 + diff --git a/fixup-can-t-find-cpu-type.patch b/fixup-can-t-find-cpu-type.patch new file mode 100644 index 0000000000000000000000000000000000000000..b9dbf89716c2f1827dc95e2632e0b160aab32302 --- /dev/null +++ b/fixup-can-t-find-cpu-type.patch @@ -0,0 +1,34 @@ +From e2d6998cad687af9d0efcc54139b28b0ff990b57 Mon Sep 17 00:00:00 2001 +From: lixianglai +Date: Mon, 29 May 2023 07:51:55 -0400 +Subject: [PATCH 10/14] fixup can't find cpu type. + +Signed-off-by: lixianglai +--- + hw/loongarch/larch_3a.c | 10 +++++++++- + 1 file changed, 9 insertions(+), 1 deletion(-) + +diff --git a/hw/loongarch/larch_3a.c b/hw/loongarch/larch_3a.c +index f83bd3750..5e271f339 100644 +--- a/hw/loongarch/larch_3a.c ++++ b/hw/loongarch/larch_3a.c +@@ -547,7 +547,15 @@ static char *get_host_cpu_model_name(void) + fprintf(stderr, "read err...\n"); + } + close(fd); +- buf_p = strstr(buf, "name"); ++ buf_p = strstr(buf, "Name"); ++ if (!buf_p) { ++ buf_p = strstr(buf, "name"); ++ } ++ if (!buf_p) { ++ fprintf(stderr, "Can't find cpu name\n"); ++ return 0; ++ } ++ + + while (*buf_p != ':') { + buf_p++; +-- +2.27.0 + diff --git a/kvm-csr-save-and-restore-optimization.patch b/kvm-csr-save-and-restore-optimization.patch new file mode 100644 index 0000000000000000000000000000000000000000..8a609980a78df48b9fb94b19242d06ab04b587cc --- /dev/null +++ b/kvm-csr-save-and-restore-optimization.patch @@ -0,0 +1,599 @@ +From d28802932e2379a474e86010581390dbacfab8f2 Mon Sep 17 00:00:00 2001 +From: lixianglai +Date: Mon, 29 May 2023 07:25:52 -0400 +Subject: [PATCH 05/14] kvm csr save and restore optimization. + +Signed-off-by: lixianglai +--- + target/loongarch64/kvm.c | 547 +++++++++++---------------------------- + 1 file changed, 153 insertions(+), 394 deletions(-) + +diff --git a/target/loongarch64/kvm.c b/target/loongarch64/kvm.c +index b5c655812..6885ec6c9 100644 +--- a/target/loongarch64/kvm.c ++++ b/target/loongarch64/kvm.c +@@ -95,19 +95,165 @@ int kvm_arch_irqchip_create(KVMState *s) + return 0; + } + ++static void kvm_csr_set_addr(uint64_t **addr, uint32_t index, uint64_t *p) ++{ ++ addr[index] = p; ++} ++ + int kvm_arch_init_vcpu(CPUState *cs) + { + LOONGARCHCPU *cpu = LOONGARCH_CPU(cs); ++ uint64_t **addr; ++ CPULOONGARCHState *env = &cpu->env; + int ret = 0; + + cpu->cpuStateEntry = qemu_add_vm_change_state_handler(kvm_loongarch_update_state, cs); +- cpu->kvm_csr_buf = g_malloc0(CSR_BUF_SIZE); ++ cpu->kvm_csr_buf = g_malloc0(CSR_BUF_SIZE + CSR_BUF_SIZE); ++ ++ addr = (void *)cpu->kvm_csr_buf + CSR_BUF_SIZE; ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_CRMD, &env->CSR_CRMD); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_PRMD, &env->CSR_PRMD); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_EUEN, &env->CSR_EUEN); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_MISC, &env->CSR_MISC); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_ECFG, &env->CSR_ECFG); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_ESTAT, &env->CSR_ESTAT); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_ERA, &env->CSR_ERA); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_BADV, &env->CSR_BADV); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_BADI, &env->CSR_BADI); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_EEPN, &env->CSR_EEPN); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_TLBIDX, &env->CSR_TLBIDX); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_TLBEHI, &env->CSR_TLBEHI); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_TLBELO0, &env->CSR_TLBELO0); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_TLBELO1, &env->CSR_TLBELO1); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_GTLBC, &env->CSR_GTLBC); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_TRGP, &env->CSR_TRGP); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_ASID, &env->CSR_ASID); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_PGDL, &env->CSR_PGDL); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_PGDH, &env->CSR_PGDH); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_PGD, &env->CSR_PGD); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_PWCTL0, &env->CSR_PWCTL0); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_PWCTL1, &env->CSR_PWCTL1); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_STLBPGSIZE, &env->CSR_STLBPGSIZE); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_RVACFG, &env->CSR_RVACFG); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_CPUID, &env->CSR_CPUID); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_PRCFG1, &env->CSR_PRCFG1); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_PRCFG2, &env->CSR_PRCFG2); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_PRCFG3, &env->CSR_PRCFG3); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_KS0, &env->CSR_KS0); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_KS1, &env->CSR_KS1); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_KS2, &env->CSR_KS2); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_KS3, &env->CSR_KS3); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_KS4, &env->CSR_KS4); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_KS5, &env->CSR_KS5); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_KS6, &env->CSR_KS6); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_KS7, &env->CSR_KS7); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_TMID, &env->CSR_TMID); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_CNTC, &env->CSR_CNTC); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_TINTCLR, &env->CSR_TINTCLR); ++ ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_GSTAT, &env->CSR_GSTAT); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_GCFG, &env->CSR_GCFG); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_GINTC, &env->CSR_GINTC); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_GCNTC, &env->CSR_GCNTC); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_LLBCTL, &env->CSR_LLBCTL); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_IMPCTL1, &env->CSR_IMPCTL1); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_IMPCTL2, &env->CSR_IMPCTL2); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_GNMI, &env->CSR_GNMI); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_TLBRENT, &env->CSR_TLBRENT); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_TLBRBADV, &env->CSR_TLBRBADV); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_TLBRERA, &env->CSR_TLBRERA); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_TLBRSAVE, &env->CSR_TLBRSAVE); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_TLBRELO0, &env->CSR_TLBRELO0); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_TLBRELO1, &env->CSR_TLBRELO1); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_TLBREHI, &env->CSR_TLBREHI); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_TLBRPRMD, &env->CSR_TLBRPRMD); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_ERRCTL, &env->CSR_ERRCTL); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_ERRINFO, &env->CSR_ERRINFO); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_ERRINFO1, &env->CSR_ERRINFO1); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_ERRENT, &env->CSR_ERRENT); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_ERRERA, &env->CSR_ERRERA); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_ERRSAVE, &env->CSR_ERRSAVE); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_CTAG, &env->CSR_CTAG); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_DMWIN0, &env->CSR_DMWIN0); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_DMWIN1, &env->CSR_DMWIN1); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_DMWIN2, &env->CSR_DMWIN2); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_DMWIN3, &env->CSR_DMWIN3); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_PERFCTRL0, &env->CSR_PERFCTRL0); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_PERFCNTR0, &env->CSR_PERFCNTR0); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_PERFCTRL1, &env->CSR_PERFCTRL1); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_PERFCNTR1, &env->CSR_PERFCNTR1); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_PERFCTRL2, &env->CSR_PERFCTRL2); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_PERFCNTR2, &env->CSR_PERFCNTR2); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_PERFCTRL3, &env->CSR_PERFCTRL3); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_PERFCNTR3, &env->CSR_PERFCNTR3); ++ ++ /* debug */ ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_MWPC, &env->CSR_MWPC); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_MWPS, &env->CSR_MWPS); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_DB0ADDR, &env->CSR_DB0ADDR); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_DB0MASK, &env->CSR_DB0MASK); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_DB0CTL, &env->CSR_DB0CTL); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_DB0ASID, &env->CSR_DB0ASID); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_DB1ADDR, &env->CSR_DB1ADDR); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_DB1MASK, &env->CSR_DB1MASK); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_DB1CTL, &env->CSR_DB1CTL); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_DB1ASID, &env->CSR_DB1ASID); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_DB2ADDR, &env->CSR_DB2ADDR); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_DB2MASK, &env->CSR_DB2MASK); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_DB2CTL, &env->CSR_DB2CTL); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_DB2ASID, &env->CSR_DB2ASID); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_DB3ADDR, &env->CSR_DB3ADDR); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_DB3MASK, &env->CSR_DB3MASK); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_DB3CTL, &env->CSR_DB3CTL); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_DB3ASID, &env->CSR_DB3ASID); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_FWPC, &env->CSR_FWPC); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_FWPS, &env->CSR_FWPS); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_IB0ADDR, &env->CSR_IB0ADDR); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_IB0MASK, &env->CSR_IB0MASK); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_IB0CTL, &env->CSR_IB0CTL); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_IB0ASID, &env->CSR_IB0ASID); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_IB1ADDR, &env->CSR_IB1ADDR); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_IB1MASK, &env->CSR_IB1MASK); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_IB1CTL, &env->CSR_IB1CTL); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_IB1ASID, &env->CSR_IB1ASID); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_IB2ADDR, &env->CSR_IB2ADDR); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_IB2MASK, &env->CSR_IB2MASK); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_IB2CTL, &env->CSR_IB2CTL); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_IB2ASID, &env->CSR_IB2ASID); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_IB3ADDR, &env->CSR_IB3ADDR); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_IB3MASK, &env->CSR_IB3MASK); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_IB3CTL, &env->CSR_IB3CTL); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_IB3ASID, &env->CSR_IB3ASID); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_IB4ADDR, &env->CSR_IB4ADDR); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_IB4MASK, &env->CSR_IB4MASK); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_IB4CTL, &env->CSR_IB4CTL); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_IB4ASID, &env->CSR_IB4ASID); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_IB5ADDR, &env->CSR_IB5ADDR); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_IB5MASK, &env->CSR_IB5MASK); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_IB5CTL, &env->CSR_IB5CTL); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_IB5ASID, &env->CSR_IB5ASID); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_IB6ADDR, &env->CSR_IB6ADDR); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_IB6MASK, &env->CSR_IB6MASK); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_IB6CTL, &env->CSR_IB6CTL); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_IB6ASID, &env->CSR_IB6ASID); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_IB7ADDR, &env->CSR_IB7ADDR); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_IB7MASK, &env->CSR_IB7MASK); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_IB7CTL, &env->CSR_IB7CTL); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_IB7ASID, &env->CSR_IB7ASID); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_DEBUG, &env->CSR_DEBUG); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_DERA, &env->CSR_DERA); ++ kvm_csr_set_addr(addr, LOONGARCH_CSR_DESAVE, &env->CSR_DESAVE); ++ + DPRINTF("%s\n", __func__); + return ret; + } + + int kvm_arch_destroy_vcpu(CPUState *cs) + { ++ LOONGARCHCPU *cpu = LOONGARCH_CPU(cs); ++ ++ g_free(cpu->kvm_csr_buf); ++ cpu->kvm_csr_buf = NULL; + return 0; + } + +@@ -936,8 +1082,10 @@ static int kvm_loongarch_get_csr_registers(CPUState *cs) + CPULOONGARCHState *env = &cpu->env; + int ret = 0, i; + struct kvm_csr_entry *csrs = cpu->kvm_csr_buf->entries; ++ uint64_t **addr; + + kvm_csr_buf_reset(cpu); ++ addr = (void *)cpu->kvm_csr_buf + CSR_BUF_SIZE; + + kvm_csr_entry_add(cpu, LOONGARCH_CSR_CRMD, 0); + kvm_csr_entry_add(cpu, LOONGARCH_CSR_PRMD, 0); +@@ -1082,399 +1230,10 @@ static int kvm_loongarch_get_csr_registers(CPUState *cs) + + for (i = 0; i < ret; i++) { + uint32_t index = csrs[i].index; +- +- switch (index) { +- case LOONGARCH_CSR_CRMD: +- env->CSR_CRMD = csrs[i].data; +- break; +- case LOONGARCH_CSR_PRMD: +- env->CSR_PRMD = csrs[i].data; +- break; +- case LOONGARCH_CSR_EUEN: +- env->CSR_EUEN = csrs[i].data; +- break; +- case LOONGARCH_CSR_MISC: +- env->CSR_MISC = csrs[i].data; +- break; +- case LOONGARCH_CSR_ECFG: +- env->CSR_ECFG = csrs[i].data; +- break; +- case LOONGARCH_CSR_ESTAT: +- env->CSR_ESTAT = csrs[i].data; +- break; +- case LOONGARCH_CSR_ERA: +- env->CSR_ERA = csrs[i].data; +- break; +- case LOONGARCH_CSR_BADV: +- env->CSR_BADV = csrs[i].data; +- break; +- case LOONGARCH_CSR_BADI: +- env->CSR_BADI = csrs[i].data; +- break; +- case LOONGARCH_CSR_EEPN: +- env->CSR_EEPN = csrs[i].data; +- break; +- case LOONGARCH_CSR_TLBIDX: +- env->CSR_TLBIDX = csrs[i].data; +- break; +- case LOONGARCH_CSR_TLBEHI: +- env->CSR_TLBEHI = csrs[i].data; +- break; +- case LOONGARCH_CSR_TLBELO0: +- env->CSR_TLBELO0 = csrs[i].data; +- break; +- case LOONGARCH_CSR_TLBELO1: +- env->CSR_TLBELO1 = csrs[i].data; +- break; +- case LOONGARCH_CSR_GTLBC: +- env->CSR_GTLBC = csrs[i].data; +- break; +- case LOONGARCH_CSR_TRGP: +- env->CSR_TRGP = csrs[i].data; +- break; +- case LOONGARCH_CSR_ASID: +- env->CSR_ASID = csrs[i].data; +- break; +- case LOONGARCH_CSR_PGDL: +- env->CSR_PGDL = csrs[i].data; +- break; +- case LOONGARCH_CSR_PGDH: +- env->CSR_PGDH = csrs[i].data; +- break; +- case LOONGARCH_CSR_PGD: +- env->CSR_PGD = csrs[i].data; +- break; +- case LOONGARCH_CSR_PWCTL0: +- env->CSR_PWCTL0 = csrs[i].data; +- break; +- case LOONGARCH_CSR_PWCTL1: +- env->CSR_PWCTL1 = csrs[i].data; +- break; +- case LOONGARCH_CSR_STLBPGSIZE: +- env->CSR_STLBPGSIZE = csrs[i].data; +- break; +- case LOONGARCH_CSR_RVACFG: +- env->CSR_RVACFG = csrs[i].data; +- break; +- case LOONGARCH_CSR_CPUID: +- env->CSR_CPUID = csrs[i].data; +- break; +- case LOONGARCH_CSR_PRCFG1: +- env->CSR_PRCFG1 = csrs[i].data; +- break; +- case LOONGARCH_CSR_PRCFG2: +- env->CSR_PRCFG2 = csrs[i].data; +- break; +- case LOONGARCH_CSR_PRCFG3: +- env->CSR_PRCFG3 = csrs[i].data; +- break; +- case LOONGARCH_CSR_KS0: +- env->CSR_KS0 = csrs[i].data; +- break; +- case LOONGARCH_CSR_KS1: +- env->CSR_KS1 = csrs[i].data; +- break; +- case LOONGARCH_CSR_KS2: +- env->CSR_KS2 = csrs[i].data; +- break; +- case LOONGARCH_CSR_KS3: +- env->CSR_KS3 = csrs[i].data; +- break; +- case LOONGARCH_CSR_KS4: +- env->CSR_KS4 = csrs[i].data; +- break; +- case LOONGARCH_CSR_KS5: +- env->CSR_KS5 = csrs[i].data; +- break; +- case LOONGARCH_CSR_KS6: +- env->CSR_KS6 = csrs[i].data; +- break; +- case LOONGARCH_CSR_KS7: +- env->CSR_KS7 = csrs[i].data; +- break; +- +- case LOONGARCH_CSR_TMID: +- env->CSR_TMID = csrs[i].data; +- break; +- case LOONGARCH_CSR_CNTC: +- env->CSR_CNTC = csrs[i].data; +- break; +- case LOONGARCH_CSR_TINTCLR: +- env->CSR_TINTCLR = csrs[i].data; +- break; +- case LOONGARCH_CSR_GSTAT: +- env->CSR_GSTAT = csrs[i].data; +- break; +- case LOONGARCH_CSR_GCFG: +- env->CSR_GCFG = csrs[i].data; +- break; +- case LOONGARCH_CSR_GINTC: +- env->CSR_GINTC = csrs[i].data; +- break; +- case LOONGARCH_CSR_GCNTC: +- env->CSR_GCNTC = csrs[i].data; +- break; +- case LOONGARCH_CSR_LLBCTL: +- env->CSR_LLBCTL = csrs[i].data; +- break; +- case LOONGARCH_CSR_IMPCTL1: +- env->CSR_IMPCTL1 = csrs[i].data; +- break; +- case LOONGARCH_CSR_IMPCTL2: +- env->CSR_IMPCTL2 = csrs[i].data; +- break; +- case LOONGARCH_CSR_GNMI: +- env->CSR_GNMI = csrs[i].data; +- break; +- case LOONGARCH_CSR_TLBRENT: +- env->CSR_TLBRENT = csrs[i].data; +- break; +- case LOONGARCH_CSR_TLBRBADV: +- env->CSR_TLBRBADV = csrs[i].data; +- break; +- case LOONGARCH_CSR_TLBRERA: +- env->CSR_TLBRERA = csrs[i].data; +- break; +- case LOONGARCH_CSR_TLBRSAVE: +- env->CSR_TLBRSAVE = csrs[i].data; +- break; +- case LOONGARCH_CSR_TLBRELO0: +- env->CSR_TLBRELO0 = csrs[i].data; +- break; +- case LOONGARCH_CSR_TLBRELO1: +- env->CSR_TLBRELO1 = csrs[i].data; +- break; +- case LOONGARCH_CSR_TLBREHI: +- env->CSR_TLBREHI = csrs[i].data; +- break; +- case LOONGARCH_CSR_TLBRPRMD: +- env->CSR_TLBRPRMD = csrs[i].data; +- break; +- case LOONGARCH_CSR_ERRCTL: +- env->CSR_ERRCTL = csrs[i].data; +- break; +- case LOONGARCH_CSR_ERRINFO: +- env->CSR_ERRINFO = csrs[i].data; +- break; +- case LOONGARCH_CSR_ERRINFO1: +- env->CSR_ERRINFO1 = csrs[i].data; +- break; +- case LOONGARCH_CSR_ERRENT: +- env->CSR_ERRENT = csrs[i].data; +- break; +- case LOONGARCH_CSR_ERRERA: +- env->CSR_ERRERA = csrs[i].data; +- break; +- case LOONGARCH_CSR_ERRSAVE: +- env->CSR_ERRSAVE = csrs[i].data; +- break; +- case LOONGARCH_CSR_CTAG: +- env->CSR_CTAG = csrs[i].data; +- break; +- case LOONGARCH_CSR_DMWIN0: +- env->CSR_DMWIN0 = csrs[i].data; +- break; +- case LOONGARCH_CSR_DMWIN1: +- env->CSR_DMWIN1 = csrs[i].data; +- break; +- case LOONGARCH_CSR_DMWIN2: +- env->CSR_DMWIN2 = csrs[i].data; +- break; +- case LOONGARCH_CSR_DMWIN3: +- env->CSR_DMWIN3 = csrs[i].data; +- break; +- case LOONGARCH_CSR_PERFCTRL0: +- env->CSR_PERFCTRL0 = csrs[i].data; +- break; +- case LOONGARCH_CSR_PERFCNTR0: +- env->CSR_PERFCNTR0 = csrs[i].data; +- break; +- case LOONGARCH_CSR_PERFCTRL1: +- env->CSR_PERFCTRL1 = csrs[i].data; +- break; +- case LOONGARCH_CSR_PERFCNTR1: +- env->CSR_PERFCNTR1 = csrs[i].data; +- break; +- case LOONGARCH_CSR_PERFCTRL2: +- env->CSR_PERFCTRL2 = csrs[i].data; +- break; +- case LOONGARCH_CSR_PERFCNTR2: +- env->CSR_PERFCNTR2 = csrs[i].data; +- break; +- case LOONGARCH_CSR_PERFCTRL3: +- env->CSR_PERFCTRL3 = csrs[i].data; +- break; +- case LOONGARCH_CSR_PERFCNTR3: +- env->CSR_PERFCNTR3 = csrs[i].data; +- break; +- +- case LOONGARCH_CSR_MWPC: +- env->CSR_MWPC = csrs[i].data; +- break; +- case LOONGARCH_CSR_MWPS: +- env->CSR_MWPS = csrs[i].data; +- break; +- case LOONGARCH_CSR_DB0ADDR: +- env->CSR_DB0ADDR = csrs[i].data; +- break; +- case LOONGARCH_CSR_DB0MASK: +- env->CSR_DB0MASK = csrs[i].data; +- break; +- case LOONGARCH_CSR_DB0CTL: +- env->CSR_DB0CTL = csrs[i].data; +- break; +- case LOONGARCH_CSR_DB0ASID: +- env->CSR_DB0ASID = csrs[i].data; +- break; +- case LOONGARCH_CSR_DB1ADDR: +- env->CSR_DB1ADDR = csrs[i].data; +- break; +- case LOONGARCH_CSR_DB1MASK: +- env->CSR_DB1MASK = csrs[i].data; +- break; +- case LOONGARCH_CSR_DB1CTL: +- env->CSR_DB1CTL = csrs[i].data; +- break; +- case LOONGARCH_CSR_DB1ASID: +- env->CSR_DB1ASID = csrs[i].data; +- break; +- case LOONGARCH_CSR_DB2ADDR: +- env->CSR_DB2ADDR = csrs[i].data; +- break; +- case LOONGARCH_CSR_DB2MASK: +- env->CSR_DB2MASK = csrs[i].data; +- break; +- case LOONGARCH_CSR_DB2CTL: +- env->CSR_DB2CTL = csrs[i].data; +- break; +- case LOONGARCH_CSR_DB2ASID: +- env->CSR_DB2ASID = csrs[i].data; +- break; +- case LOONGARCH_CSR_DB3ADDR: +- env->CSR_DB3ADDR = csrs[i].data; +- break; +- case LOONGARCH_CSR_DB3MASK: +- env->CSR_DB3MASK = csrs[i].data; +- break; +- case LOONGARCH_CSR_DB3CTL: +- env->CSR_DB3CTL = csrs[i].data; +- break; +- case LOONGARCH_CSR_DB3ASID: +- env->CSR_DB3ASID = csrs[i].data; +- break; +- case LOONGARCH_CSR_FWPC: +- env->CSR_FWPC = csrs[i].data; +- break; +- case LOONGARCH_CSR_FWPS: +- env->CSR_FWPS = csrs[i].data; +- break; +- case LOONGARCH_CSR_IB0ADDR: +- env->CSR_IB0ADDR = csrs[i].data; +- break; +- case LOONGARCH_CSR_IB0MASK: +- env->CSR_IB0MASK = csrs[i].data; +- break; +- case LOONGARCH_CSR_IB0CTL: +- env->CSR_IB0CTL = csrs[i].data; +- break; +- case LOONGARCH_CSR_IB0ASID: +- env->CSR_IB0ASID = csrs[i].data; +- break; +- case LOONGARCH_CSR_IB1ADDR: +- env->CSR_IB1ADDR = csrs[i].data; +- break; +- case LOONGARCH_CSR_IB1MASK: +- env->CSR_IB1MASK = csrs[i].data; +- break; +- case LOONGARCH_CSR_IB1CTL: +- env->CSR_IB1CTL = csrs[i].data; +- break; +- case LOONGARCH_CSR_IB1ASID: +- env->CSR_IB1ASID = csrs[i].data; +- break; +- case LOONGARCH_CSR_IB2ADDR: +- env->CSR_IB2ADDR = csrs[i].data; +- break; +- case LOONGARCH_CSR_IB2MASK: +- env->CSR_IB2MASK = csrs[i].data; +- break; +- case LOONGARCH_CSR_IB2CTL: +- env->CSR_IB2CTL = csrs[i].data; +- break; +- case LOONGARCH_CSR_IB2ASID: +- env->CSR_IB2ASID = csrs[i].data; +- break; +- case LOONGARCH_CSR_IB3ADDR: +- env->CSR_IB3ADDR = csrs[i].data; +- break; +- case LOONGARCH_CSR_IB3MASK: +- env->CSR_IB3MASK = csrs[i].data; +- break; +- case LOONGARCH_CSR_IB3CTL: +- env->CSR_IB3CTL = csrs[i].data; +- break; +- case LOONGARCH_CSR_IB3ASID: +- env->CSR_IB3ASID = csrs[i].data; +- break; +- case LOONGARCH_CSR_IB4ADDR: +- env->CSR_IB4ADDR = csrs[i].data; +- break; +- case LOONGARCH_CSR_IB4MASK: +- env->CSR_IB4MASK = csrs[i].data; +- break; +- case LOONGARCH_CSR_IB4CTL: +- env->CSR_IB4CTL = csrs[i].data; +- break; +- case LOONGARCH_CSR_IB4ASID: +- env->CSR_IB4ASID = csrs[i].data; +- break; +- case LOONGARCH_CSR_IB5ADDR: +- env->CSR_IB5ADDR = csrs[i].data; +- break; +- case LOONGARCH_CSR_IB5MASK: +- env->CSR_IB5MASK = csrs[i].data; +- break; +- case LOONGARCH_CSR_IB5CTL: +- env->CSR_IB5CTL = csrs[i].data; +- break; +- case LOONGARCH_CSR_IB5ASID: +- env->CSR_IB5ASID = csrs[i].data; +- break; +- case LOONGARCH_CSR_IB6ADDR: +- env->CSR_IB6ADDR = csrs[i].data; +- break; +- case LOONGARCH_CSR_IB6MASK: +- env->CSR_IB6MASK = csrs[i].data; +- break; +- case LOONGARCH_CSR_IB6CTL: +- env->CSR_IB6CTL = csrs[i].data; +- break; +- case LOONGARCH_CSR_IB6ASID: +- env->CSR_IB6ASID = csrs[i].data; +- break; +- case LOONGARCH_CSR_IB7ADDR: +- env->CSR_IB7ADDR = csrs[i].data; +- break; +- case LOONGARCH_CSR_IB7MASK: +- env->CSR_IB7MASK = csrs[i].data; +- break; +- case LOONGARCH_CSR_IB7CTL: +- env->CSR_IB7CTL = csrs[i].data; +- break; +- case LOONGARCH_CSR_IB7ASID: +- env->CSR_IB7ASID = csrs[i].data; +- break; +- case LOONGARCH_CSR_DEBUG: +- env->CSR_DEBUG = csrs[i].data; +- break; +- case LOONGARCH_CSR_DERA: +- env->CSR_DERA = csrs[i].data; +- break; +- case LOONGARCH_CSR_DESAVE: +- env->CSR_DESAVE = csrs[i].data; +- break; +- default: +- break; ++ if (addr[index]) { ++ *addr[index] = csrs[i].data; ++ } else { ++ printf("Failed to get addr CSR 0x%"PRIx32"\n", i); + } + } + +-- +2.27.0 + diff --git a/loongarch_bios.bin b/loongarch_bios.bin index 3aa4f36a853b0d605d6a6dd61d933fa43084c580..d6330c6f0532effe458726efa18222166a444839 100644 Binary files a/loongarch_bios.bin and b/loongarch_bios.bin differ diff --git a/pass-to-make-check.patch b/pass-to-make-check.patch new file mode 100644 index 0000000000000000000000000000000000000000..a0bc8ca87f423b4e70fed7eb398ce32efdbee33a --- /dev/null +++ b/pass-to-make-check.patch @@ -0,0 +1,164 @@ +From b30eda522b141cf4b26a2fb22c2123d487f4169d Mon Sep 17 00:00:00 2001 +From: lixianglai +Date: Mon, 29 May 2023 07:49:06 -0400 +Subject: [PATCH 09/14] pass to make check. + +With this patch, when running make check command, qemu passes to +compile. + +Signed-off-by: lixianglai +--- + hw/loongarch/apic.c | 4 ++-- + hw/loongarch/ioapic.c | 4 ++-- + hw/loongarch/iocsr.c | 20 ++++++++++++++++++-- + hw/loongarch/ipi.c | 4 ++-- + hw/loongarch/larch_3a.c | 3 --- + target/loongarch64/machine.c | 7 +++++++ + 6 files changed, 31 insertions(+), 11 deletions(-) + +diff --git a/hw/loongarch/apic.c b/hw/loongarch/apic.c +index d6ba2a2ce..67994d201 100644 +--- a/hw/loongarch/apic.c ++++ b/hw/loongarch/apic.c +@@ -64,7 +64,7 @@ static int ext_irq_pre_save(void *opaque) + struct kvm_loongarch_ls3a_extirq_state *kstate; + int ret, length, i, vcpuid; + #endif +- if (!kvm_irqchip_in_kernel()) { ++ if ((!kvm_enabled()) || (!kvm_irqchip_in_kernel())) { + return 0; + } + #ifdef CONFIG_KVM +@@ -112,7 +112,7 @@ static int ext_irq_post_load(void *opaque, int version) + struct kvm_loongarch_ls3a_extirq_state *kstate; + int ret, length, i, vcpuid; + #endif +- if (!kvm_irqchip_in_kernel()) { ++ if ((!kvm_enabled()) || (!kvm_irqchip_in_kernel())) { + return 0; + } + #ifdef CONFIG_KVM +diff --git a/hw/loongarch/ioapic.c b/hw/loongarch/ioapic.c +index 3de0ed88d..60abff855 100644 +--- a/hw/loongarch/ioapic.c ++++ b/hw/loongarch/ioapic.c +@@ -253,7 +253,7 @@ static int kvm_ls7a_pre_save(void *opaque) + struct ls7a_ioapic_state *state; + int ret, i, length; + +- if (!kvm_irqchip_in_kernel()) { ++ if ((!kvm_enabled()) || (!kvm_irqchip_in_kernel())) { + return 0; + } + +@@ -297,7 +297,7 @@ static int kvm_ls7a_post_load(void *opaque, int version) + struct ls7a_ioapic_state *state; + int ret, i, length; + +- if (!kvm_irqchip_in_kernel()) { ++ if ((!kvm_enabled()) || (!kvm_irqchip_in_kernel())) { + return 0; + } + length = sizeof(struct loongarch_kvm_irqchip) + sizeof(struct ls7a_ioapic_state); +diff --git a/hw/loongarch/iocsr.c b/hw/loongarch/iocsr.c +index 60daafd6e..13d356d80 100644 +--- a/hw/loongarch/iocsr.c ++++ b/hw/loongarch/iocsr.c +@@ -95,6 +95,11 @@ static int kvm_iocsr_pre_save(void *opaque) + IOCSRState *s = opaque; + struct kvm_iocsr_entry entry; + int i = 0; ++ ++ if ((!kvm_enabled())) { ++ return 0; ++ } ++ + for (i = 0; i < IOCSR_MAX; i++) { + entry.addr = iocsr_array[i]; + kvm_vm_ioctl(kvm_state, KVM_LOONGARCH_GET_IOCSR, &entry); +@@ -172,8 +177,19 @@ static void iocsr_instance_init(Object *obj) + { + IOCSRState *s = IOCSR(obj); + int i; +- LoongarchMachineState *lsms = LoongarchMACHINE(qdev_get_machine()); +- LoongarchMachineClass *lsmc = LoongarchMACHINE_GET_CLASS(lsms); ++ LoongarchMachineState *lsms; ++ LoongarchMachineClass *lsmc; ++ Object *machine = qdev_get_machine(); ++ ObjectClass *mc = object_get_class(machine); ++ ++ ++ /* 'lams' should be initialized */ ++ if (!strcmp(MACHINE_CLASS(mc)->name, "none")) { ++ return; ++ } ++ ++ lsms = LoongarchMACHINE(machine); ++ lsmc = LoongarchMACHINE_GET_CLASS(lsms); + + init_vendor_cpuname((uint64_t *)&iocsr_init.iocsr_val[IOCSR_VENDOR], + (uint64_t *)&iocsr_init.iocsr_val[IOCSR_CPUNAME], +diff --git a/hw/loongarch/ipi.c b/hw/loongarch/ipi.c +index ade182abc..59186f1de 100644 +--- a/hw/loongarch/ipi.c ++++ b/hw/loongarch/ipi.c +@@ -25,7 +25,7 @@ static int gipi_pre_save(void *opaque) + int ret, i, j, length; + #endif + +- if (!kvm_irqchip_in_kernel()) { ++ if ((!kvm_enabled()) || (!kvm_irqchip_in_kernel())) { + return 0; + } + +@@ -67,7 +67,7 @@ static int gipi_post_load(void *opaque, int version) + int ret, i, j, length; + #endif + +- if (!kvm_irqchip_in_kernel()) { ++ if ((!kvm_enabled()) || (!kvm_irqchip_in_kernel())) { + return 0; + } + +diff --git a/hw/loongarch/larch_3a.c b/hw/loongarch/larch_3a.c +index 6eaa53d74..f83bd3750 100644 +--- a/hw/loongarch/larch_3a.c ++++ b/hw/loongarch/larch_3a.c +@@ -1435,9 +1435,6 @@ static void ls3a5k_bios_init(LoongarchMachineState *lsms, + + if (kernel_filename) { + lsms->reset_info[0]->vector = load_kernel(); +- } else { +- error_report("Please specify at lease one of -bios and -kernel"); +- exit(1); + } + } + } +diff --git a/target/loongarch64/machine.c b/target/loongarch64/machine.c +index b69bca6a9..dea6a7034 100644 +--- a/target/loongarch64/machine.c ++++ b/target/loongarch64/machine.c +@@ -15,6 +15,10 @@ static int cpu_post_load(void *opaque, int version_id) + CPULOONGARCHState *env = &cpu->env; + int r = 0; + ++ if (!kvm_enabled()) { ++ return 0; ++ } ++ + #ifdef CONFIG_KVM + struct kvm_loongarch_vcpu_state vcpu_state; + int i; +@@ -48,6 +52,9 @@ static int cpu_pre_save(void *opaque) + LOONGARCHCPU *cpu = opaque; + struct kvm_loongarch_vcpu_state vcpu_state; + int i, r = 0; ++ if (!kvm_enabled()) { ++ return 0; ++ } + + r = kvm_vcpu_ioctl(CPU(cpu), KVM_LARCH_GET_VCPU_STATE, &vcpu_state); + if (r < 0) { +-- +2.27.0 + diff --git a/qemu-kvm.spec b/qemu-kvm.spec index 00d92bc0125b8d1e0f4d6a50934c594371617c3c..6a6857ec9e264ac1fa81624b86f55cc6aba34fc6 100644 --- a/qemu-kvm.spec +++ b/qemu-kvm.spec @@ -1,4 +1,4 @@ -%define anolis_release .0.1 +%define anolis_release .0.2 %global SLOF_gittagdate 20191022 %global SLOF_gittagcommit 899d9883 @@ -470,6 +470,21 @@ Patch1006: 0006-Add-disas-gdb.patch Patch1007: 0007-Modify-kvm-cpu-vga-qapi.patch Patch1008: 0008-Modify-compile-script.patch Patch1009: 0009-Add-loongarch64-rh-devices.mak.patch +Patch1010: Modify-smbios-option-lack-and-Modify-the-maximum-num.patch +Patch1011: rename-kvm_msr_buf-with-kvm_csr_buf.patch +Patch1012: code-cleanup-for-loongarch-kvm.patch +Patch1013: Support-TPM.patch +Patch1014: kvm-csr-save-and-restore-optimization.patch +Patch1015: address-space-code-cleanup-on-7A-virt-machine.patch +Patch1016: Fix-irq-routing-and-fpu-option-to-compat-with-kernel.patch +Patch1017: Support-vfio-config.patch +Patch1018: pass-to-make-check.patch +Patch1019: fixup-can-t-find-cpu-type.patch +Patch1020: fix-smbios-type4-info-for-numa-support.patch +Patch1021: Fix-smp.cores-value.patch +Patch1022: Add-lbt-support-for-kvm.patch +Patch1023: Modify-the-ioctl-command-of-kvm.patch + BuildRequires: wget BuildRequires: rpm-build @@ -1708,6 +1723,22 @@ sh %{_sysconfdir}/sysconfig/modules/kvm.modules &> /dev/null || : %endif %changelog +* Tue May 23 2023 xianglai li - 6.2.0-22.0.2.2 +- Modify-smbios-option-lack-and-Modify-the-maximum-num.patch +- rename-kvm_msr_buf-with-kvm_csr_buf.patch +- code-cleanup-for-loongarch-kvm.patch +- Support-TPM.patch +- kvm-csr-save-and-restore-optimization.patch +- address-space-code-cleanup-on-7A-virt-machine.patch +- Fix-irq-routing-and-fpu-option-to-compat-with-kernel.patch +- Support-vfio-config.patch +- pass-to-make-check.patch +- fixup-can-t-find-cpu-type.patch +- fix-smbios-type4-info-for-numa-support.patch +- Fix-smp.cores-value.patch +- Add-lbt-support-for-kvm.patch +- Modify-the-ioctl-command-of-kvm.patch + * Thu Apr 06 2023 Jacob Wang - 6.2.0-22.0.1.2 - Adjust limit for virtiofsd minor version - Add loongarch supporti (lixianglai@loongson.cn) diff --git a/rename-kvm_msr_buf-with-kvm_csr_buf.patch b/rename-kvm_msr_buf-with-kvm_csr_buf.patch new file mode 100644 index 0000000000000000000000000000000000000000..4ebe9fdaa9a4cbab27d2f9b813cf246a81ddcee2 --- /dev/null +++ b/rename-kvm_msr_buf-with-kvm_csr_buf.patch @@ -0,0 +1,638 @@ +From be136658b2055e4835f1d41c0729dba7b68cba16 Mon Sep 17 00:00:00 2001 +From: lixianglai +Date: Mon, 29 May 2023 05:57:27 -0400 +Subject: [PATCH 02/14] rename kvm_msr_buf with kvm_csr_buf. + +Signed-off-by: lixianglai +--- + target/loongarch64/cpu.h | 2 +- + target/loongarch64/kvm.c | 564 +++++++++++++++++++-------------------- + 2 files changed, 283 insertions(+), 283 deletions(-) + +diff --git a/target/loongarch64/cpu.h b/target/loongarch64/cpu.h +index 10facb3b7..078556a22 100644 +--- a/target/loongarch64/cpu.h ++++ b/target/loongarch64/cpu.h +@@ -200,7 +200,7 @@ struct LOONGARCHCPU { + VMChangeStateEntry *cpuStateEntry; + int32_t node_id; /* NUMA node this CPU belongs to */ + int32_t core_id; +- struct kvm_msrs *kvm_msr_buf; ++ struct kvm_msrs *kvm_csr_buf; + /* 'compatible' string for this CPU for Linux device trees */ + const char *dtb_compatible; + }; +diff --git a/target/loongarch64/kvm.c b/target/loongarch64/kvm.c +index 404a605eb..b5c655812 100644 +--- a/target/loongarch64/kvm.c ++++ b/target/loongarch64/kvm.c +@@ -31,7 +31,7 @@ + #define DEBUG_KVM 0 + /* A 16384-byte buffer can hold the 8-byte kvm_msrs header, plus + * 2047 kvm_msr_entry structs */ +-#define MSR_BUF_SIZE 16384 ++#define CSR_BUF_SIZE 16384 + + #define DPRINTF(fmt, ...) \ + do { if (DEBUG_KVM) { fprintf(stderr, fmt, ## __VA_ARGS__); } } while (0) +@@ -101,7 +101,7 @@ int kvm_arch_init_vcpu(CPUState *cs) + int ret = 0; + + cpu->cpuStateEntry = qemu_add_vm_change_state_handler(kvm_loongarch_update_state, cs); +- cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE); ++ cpu->kvm_csr_buf = g_malloc0(CSR_BUF_SIZE); + DPRINTF("%s\n", __func__); + return ret; + } +@@ -111,15 +111,15 @@ int kvm_arch_destroy_vcpu(CPUState *cs) + return 0; + } + +-static void kvm_msr_buf_reset(LOONGARCHCPU *cpu) ++static void kvm_csr_buf_reset(LOONGARCHCPU *cpu) + { +- memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE); ++ memset(cpu->kvm_csr_buf, 0, CSR_BUF_SIZE); + } + +-static void kvm_msr_entry_add(LOONGARCHCPU *cpu, uint32_t index, uint64_t value) ++static void kvm_csr_entry_add(LOONGARCHCPU *cpu, uint32_t index, uint64_t value) + { +- struct kvm_msrs *msrs = cpu->kvm_msr_buf; +- void *limit = ((void *)msrs) + MSR_BUF_SIZE; ++ struct kvm_msrs *msrs = cpu->kvm_csr_buf; ++ void *limit = ((void *)msrs) + CSR_BUF_SIZE; + struct kvm_csr_entry *entry = &msrs->entries[msrs->ncsrs]; + + assert((void *)(entry + 1) <= limit); +@@ -767,144 +767,144 @@ static int kvm_loongarch_put_csr_registers(CPUState *cs, int level) + + (void)level; + +- kvm_msr_buf_reset(cpu); +- +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_CRMD, env->CSR_CRMD); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_PRMD, env->CSR_PRMD); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_EUEN, env->CSR_EUEN); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_MISC, env->CSR_MISC); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_ECFG, env->CSR_ECFG); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_ESTAT, env->CSR_ESTAT); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_ERA, env->CSR_ERA); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_BADV, env->CSR_BADV); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_BADI, env->CSR_BADI); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_EEPN, env->CSR_EEPN); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_TLBIDX, env->CSR_TLBIDX); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_TLBEHI, env->CSR_TLBEHI); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_TLBELO0, env->CSR_TLBELO0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_TLBELO1, env->CSR_TLBELO1); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_GTLBC, env->CSR_GTLBC); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_TRGP, env->CSR_TRGP); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_ASID, env->CSR_ASID); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_PGDL, env->CSR_PGDL); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_PGDH, env->CSR_PGDH); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_PGD, env->CSR_PGD); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_PWCTL0, env->CSR_PWCTL0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_PWCTL1, env->CSR_PWCTL1); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_STLBPGSIZE, env->CSR_STLBPGSIZE); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_RVACFG, env->CSR_RVACFG); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_CPUID, env->CSR_CPUID); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_PRCFG1, env->CSR_PRCFG1); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_PRCFG2, env->CSR_PRCFG2); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_PRCFG3, env->CSR_PRCFG3); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_KS0, env->CSR_KS0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_KS1, env->CSR_KS1); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_KS2, env->CSR_KS2); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_KS3, env->CSR_KS3); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_KS4, env->CSR_KS4); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_KS5, env->CSR_KS5); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_KS6, env->CSR_KS6); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_KS7, env->CSR_KS7); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_TMID, env->CSR_TMID); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_CNTC, env->CSR_CNTC); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_TINTCLR, env->CSR_TINTCLR); +- +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_GSTAT, env->CSR_GSTAT); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_GCFG, env->CSR_GCFG); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_GINTC, env->CSR_GINTC); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_GCNTC, env->CSR_GCNTC); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_LLBCTL, env->CSR_LLBCTL); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IMPCTL1, env->CSR_IMPCTL1); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IMPCTL2, env->CSR_IMPCTL2); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_GNMI, env->CSR_GNMI); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_TLBRENT, env->CSR_TLBRENT); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_TLBRBADV, env->CSR_TLBRBADV); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_TLBRERA, env->CSR_TLBRERA); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_TLBRSAVE, env->CSR_TLBRSAVE); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_TLBRELO0, env->CSR_TLBRELO0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_TLBRELO1, env->CSR_TLBRELO1); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_TLBREHI, env->CSR_TLBREHI); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_TLBRPRMD, env->CSR_TLBRPRMD); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_ERRCTL, env->CSR_ERRCTL); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_ERRINFO, env->CSR_ERRINFO); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_ERRINFO1, env->CSR_ERRINFO1); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_ERRENT, env->CSR_ERRENT); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_ERRERA, env->CSR_ERRERA); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_ERRSAVE, env->CSR_ERRSAVE); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_CTAG, env->CSR_CTAG); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_DMWIN0, env->CSR_DMWIN0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_DMWIN1, env->CSR_DMWIN1); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_DMWIN2, env->CSR_DMWIN2); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_DMWIN3, env->CSR_DMWIN3); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_PERFCTRL0, env->CSR_PERFCTRL0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_PERFCNTR0, env->CSR_PERFCNTR0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_PERFCTRL1, env->CSR_PERFCTRL1); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_PERFCNTR1, env->CSR_PERFCNTR1); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_PERFCTRL2, env->CSR_PERFCTRL2); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_PERFCNTR2, env->CSR_PERFCNTR2); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_PERFCTRL3, env->CSR_PERFCTRL3); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_PERFCNTR3, env->CSR_PERFCNTR3); ++ kvm_csr_buf_reset(cpu); ++ ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_CRMD, env->CSR_CRMD); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_PRMD, env->CSR_PRMD); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_EUEN, env->CSR_EUEN); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_MISC, env->CSR_MISC); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_ECFG, env->CSR_ECFG); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_ESTAT, env->CSR_ESTAT); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_ERA, env->CSR_ERA); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_BADV, env->CSR_BADV); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_BADI, env->CSR_BADI); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_EEPN, env->CSR_EEPN); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_TLBIDX, env->CSR_TLBIDX); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_TLBEHI, env->CSR_TLBEHI); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_TLBELO0, env->CSR_TLBELO0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_TLBELO1, env->CSR_TLBELO1); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_GTLBC, env->CSR_GTLBC); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_TRGP, env->CSR_TRGP); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_ASID, env->CSR_ASID); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_PGDL, env->CSR_PGDL); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_PGDH, env->CSR_PGDH); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_PGD, env->CSR_PGD); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_PWCTL0, env->CSR_PWCTL0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_PWCTL1, env->CSR_PWCTL1); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_STLBPGSIZE, env->CSR_STLBPGSIZE); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_RVACFG, env->CSR_RVACFG); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_CPUID, env->CSR_CPUID); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_PRCFG1, env->CSR_PRCFG1); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_PRCFG2, env->CSR_PRCFG2); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_PRCFG3, env->CSR_PRCFG3); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_KS0, env->CSR_KS0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_KS1, env->CSR_KS1); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_KS2, env->CSR_KS2); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_KS3, env->CSR_KS3); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_KS4, env->CSR_KS4); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_KS5, env->CSR_KS5); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_KS6, env->CSR_KS6); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_KS7, env->CSR_KS7); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_TMID, env->CSR_TMID); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_CNTC, env->CSR_CNTC); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_TINTCLR, env->CSR_TINTCLR); ++ ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_GSTAT, env->CSR_GSTAT); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_GCFG, env->CSR_GCFG); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_GINTC, env->CSR_GINTC); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_GCNTC, env->CSR_GCNTC); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_LLBCTL, env->CSR_LLBCTL); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IMPCTL1, env->CSR_IMPCTL1); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IMPCTL2, env->CSR_IMPCTL2); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_GNMI, env->CSR_GNMI); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_TLBRENT, env->CSR_TLBRENT); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_TLBRBADV, env->CSR_TLBRBADV); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_TLBRERA, env->CSR_TLBRERA); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_TLBRSAVE, env->CSR_TLBRSAVE); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_TLBRELO0, env->CSR_TLBRELO0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_TLBRELO1, env->CSR_TLBRELO1); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_TLBREHI, env->CSR_TLBREHI); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_TLBRPRMD, env->CSR_TLBRPRMD); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_ERRCTL, env->CSR_ERRCTL); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_ERRINFO, env->CSR_ERRINFO); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_ERRINFO1, env->CSR_ERRINFO1); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_ERRENT, env->CSR_ERRENT); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_ERRERA, env->CSR_ERRERA); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_ERRSAVE, env->CSR_ERRSAVE); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_CTAG, env->CSR_CTAG); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_DMWIN0, env->CSR_DMWIN0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_DMWIN1, env->CSR_DMWIN1); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_DMWIN2, env->CSR_DMWIN2); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_DMWIN3, env->CSR_DMWIN3); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_PERFCTRL0, env->CSR_PERFCTRL0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_PERFCNTR0, env->CSR_PERFCNTR0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_PERFCTRL1, env->CSR_PERFCTRL1); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_PERFCNTR1, env->CSR_PERFCNTR1); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_PERFCTRL2, env->CSR_PERFCTRL2); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_PERFCNTR2, env->CSR_PERFCNTR2); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_PERFCTRL3, env->CSR_PERFCTRL3); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_PERFCNTR3, env->CSR_PERFCNTR3); + + /* debug */ +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_MWPC, env->CSR_MWPC); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_MWPS, env->CSR_MWPS); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_DB0ADDR, env->CSR_DB0ADDR); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_DB0MASK, env->CSR_DB0MASK); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_DB0CTL, env->CSR_DB0CTL); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_DB0ASID, env->CSR_DB0ASID); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_DB1ADDR, env->CSR_DB1ADDR); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_DB1MASK, env->CSR_DB1MASK); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_DB1CTL, env->CSR_DB1CTL); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_DB1ASID, env->CSR_DB1ASID); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_DB2ADDR, env->CSR_DB2ADDR); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_DB2MASK, env->CSR_DB2MASK); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_DB2CTL, env->CSR_DB2CTL); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_DB2ASID, env->CSR_DB2ASID); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_DB3ADDR, env->CSR_DB3ADDR); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_DB3MASK, env->CSR_DB3MASK); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_DB3CTL, env->CSR_DB3CTL); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_DB3ASID, env->CSR_DB3ASID); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_FWPC, env->CSR_FWPC); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_FWPS, env->CSR_FWPS); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB0ADDR, env->CSR_IB0ADDR); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB0MASK, env->CSR_IB0MASK); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB0CTL, env->CSR_IB0CTL); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB0ASID, env->CSR_IB0ASID); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB1ADDR, env->CSR_IB1ADDR); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB1MASK, env->CSR_IB1MASK); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB1CTL, env->CSR_IB1CTL); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB1ASID, env->CSR_IB1ASID); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB2ADDR, env->CSR_IB2ADDR); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB2MASK, env->CSR_IB2MASK); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB2CTL, env->CSR_IB2CTL); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB2ASID, env->CSR_IB2ASID); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB3ADDR, env->CSR_IB3ADDR); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB3MASK, env->CSR_IB3MASK); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB3CTL, env->CSR_IB3CTL); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB3ASID, env->CSR_IB3ASID); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB4ADDR, env->CSR_IB4ADDR); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB4MASK, env->CSR_IB4MASK); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB4CTL, env->CSR_IB4CTL); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB4ASID, env->CSR_IB4ASID); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB5ADDR, env->CSR_IB5ADDR); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB5MASK, env->CSR_IB5MASK); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB5CTL, env->CSR_IB5CTL); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB5ASID, env->CSR_IB5ASID); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB6ADDR, env->CSR_IB6ADDR); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB6MASK, env->CSR_IB6MASK); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB6CTL, env->CSR_IB6CTL); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB6ASID, env->CSR_IB6ASID); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB7ADDR, env->CSR_IB7ADDR); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB7MASK, env->CSR_IB7MASK); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB7CTL, env->CSR_IB7CTL); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB7ASID, env->CSR_IB7ASID); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_DEBUG, env->CSR_DEBUG); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_DERA, env->CSR_DERA); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_DESAVE, env->CSR_DESAVE); +- +- ret = kvm_vcpu_ioctl(cs, KVM_SET_MSRS, cpu->kvm_msr_buf); +- if (ret < cpu->kvm_msr_buf->ncsrs) { +- struct kvm_csr_entry *e = &cpu->kvm_msr_buf->entries[ret]; ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_MWPC, env->CSR_MWPC); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_MWPS, env->CSR_MWPS); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_DB0ADDR, env->CSR_DB0ADDR); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_DB0MASK, env->CSR_DB0MASK); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_DB0CTL, env->CSR_DB0CTL); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_DB0ASID, env->CSR_DB0ASID); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_DB1ADDR, env->CSR_DB1ADDR); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_DB1MASK, env->CSR_DB1MASK); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_DB1CTL, env->CSR_DB1CTL); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_DB1ASID, env->CSR_DB1ASID); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_DB2ADDR, env->CSR_DB2ADDR); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_DB2MASK, env->CSR_DB2MASK); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_DB2CTL, env->CSR_DB2CTL); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_DB2ASID, env->CSR_DB2ASID); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_DB3ADDR, env->CSR_DB3ADDR); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_DB3MASK, env->CSR_DB3MASK); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_DB3CTL, env->CSR_DB3CTL); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_DB3ASID, env->CSR_DB3ASID); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_FWPC, env->CSR_FWPC); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_FWPS, env->CSR_FWPS); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB0ADDR, env->CSR_IB0ADDR); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB0MASK, env->CSR_IB0MASK); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB0CTL, env->CSR_IB0CTL); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB0ASID, env->CSR_IB0ASID); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB1ADDR, env->CSR_IB1ADDR); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB1MASK, env->CSR_IB1MASK); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB1CTL, env->CSR_IB1CTL); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB1ASID, env->CSR_IB1ASID); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB2ADDR, env->CSR_IB2ADDR); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB2MASK, env->CSR_IB2MASK); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB2CTL, env->CSR_IB2CTL); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB2ASID, env->CSR_IB2ASID); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB3ADDR, env->CSR_IB3ADDR); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB3MASK, env->CSR_IB3MASK); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB3CTL, env->CSR_IB3CTL); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB3ASID, env->CSR_IB3ASID); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB4ADDR, env->CSR_IB4ADDR); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB4MASK, env->CSR_IB4MASK); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB4CTL, env->CSR_IB4CTL); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB4ASID, env->CSR_IB4ASID); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB5ADDR, env->CSR_IB5ADDR); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB5MASK, env->CSR_IB5MASK); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB5CTL, env->CSR_IB5CTL); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB5ASID, env->CSR_IB5ASID); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB6ADDR, env->CSR_IB6ADDR); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB6MASK, env->CSR_IB6MASK); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB6CTL, env->CSR_IB6CTL); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB6ASID, env->CSR_IB6ASID); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB7ADDR, env->CSR_IB7ADDR); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB7MASK, env->CSR_IB7MASK); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB7CTL, env->CSR_IB7CTL); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB7ASID, env->CSR_IB7ASID); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_DEBUG, env->CSR_DEBUG); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_DERA, env->CSR_DERA); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_DESAVE, env->CSR_DESAVE); ++ ++ ret = kvm_vcpu_ioctl(cs, KVM_SET_MSRS, cpu->kvm_csr_buf); ++ if (ret < cpu->kvm_csr_buf->ncsrs) { ++ struct kvm_csr_entry *e = &cpu->kvm_csr_buf->entries[ret]; + printf("error: failed to set CSR 0x%" PRIx32 " to 0x%" PRIx64"\n", + (uint32_t)e->index, (uint64_t)e->data); + } +@@ -935,147 +935,147 @@ static int kvm_loongarch_get_csr_registers(CPUState *cs) + LOONGARCHCPU *cpu = LOONGARCH_CPU(cs); + CPULOONGARCHState *env = &cpu->env; + int ret = 0, i; +- struct kvm_csr_entry *csrs = cpu->kvm_msr_buf->entries; +- +- kvm_msr_buf_reset(cpu); +- +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_CRMD, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_PRMD, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_EUEN, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_MISC, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_ECFG, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_ESTAT, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_ERA, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_BADV, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_BADI, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_EEPN, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_TLBIDX, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_TLBEHI, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_TLBELO0, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_TLBELO1, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_GTLBC, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_TRGP, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_ASID, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_PGDL, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_PGDH, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_PGD, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_PWCTL0, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_PWCTL1, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_STLBPGSIZE, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_RVACFG, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_CPUID, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_PRCFG1, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_PRCFG2, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_PRCFG3, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_KS0, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_KS1, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_KS2, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_KS3, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_KS4, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_KS5, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_KS6, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_KS7, 0); +- +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_TMID, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_CNTC, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_TINTCLR, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_GSTAT, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_GCFG, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_GINTC, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_GCNTC, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_LLBCTL, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IMPCTL1, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IMPCTL2, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_GNMI, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_TLBRENT, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_TLBRBADV, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_TLBRERA, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_TLBRSAVE, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_TLBRELO0, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_TLBRELO1, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_TLBREHI, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_TLBRPRMD, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_ERRCTL, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_ERRINFO, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_ERRINFO1, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_ERRENT, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_ERRERA, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_ERRSAVE, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_CTAG, 0); +- +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_DMWIN0, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_DMWIN1, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_DMWIN2, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_DMWIN3, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_PERFCTRL0, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_PERFCNTR0, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_PERFCTRL1, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_PERFCNTR1, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_PERFCTRL2, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_PERFCNTR2, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_PERFCTRL3, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_PERFCNTR3, 0); ++ struct kvm_csr_entry *csrs = cpu->kvm_csr_buf->entries; ++ ++ kvm_csr_buf_reset(cpu); ++ ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_CRMD, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_PRMD, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_EUEN, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_MISC, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_ECFG, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_ESTAT, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_ERA, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_BADV, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_BADI, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_EEPN, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_TLBIDX, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_TLBEHI, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_TLBELO0, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_TLBELO1, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_GTLBC, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_TRGP, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_ASID, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_PGDL, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_PGDH, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_PGD, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_PWCTL0, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_PWCTL1, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_STLBPGSIZE, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_RVACFG, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_CPUID, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_PRCFG1, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_PRCFG2, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_PRCFG3, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_KS0, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_KS1, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_KS2, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_KS3, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_KS4, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_KS5, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_KS6, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_KS7, 0); ++ ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_TMID, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_CNTC, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_TINTCLR, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_GSTAT, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_GCFG, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_GINTC, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_GCNTC, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_LLBCTL, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IMPCTL1, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IMPCTL2, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_GNMI, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_TLBRENT, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_TLBRBADV, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_TLBRERA, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_TLBRSAVE, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_TLBRELO0, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_TLBRELO1, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_TLBREHI, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_TLBRPRMD, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_ERRCTL, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_ERRINFO, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_ERRINFO1, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_ERRENT, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_ERRERA, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_ERRSAVE, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_CTAG, 0); ++ ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_DMWIN0, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_DMWIN1, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_DMWIN2, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_DMWIN3, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_PERFCTRL0, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_PERFCNTR0, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_PERFCTRL1, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_PERFCNTR1, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_PERFCTRL2, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_PERFCNTR2, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_PERFCTRL3, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_PERFCNTR3, 0); + + /* debug */ +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_MWPC, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_MWPS, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_DB0ADDR, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_DB0MASK, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_DB0CTL, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_DB0ASID, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_DB1ADDR, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_DB1MASK, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_DB1CTL, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_DB1ASID, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_DB2ADDR, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_DB2MASK, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_DB2CTL, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_DB2ASID, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_DB3ADDR, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_DB3MASK, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_DB3CTL, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_DB3ASID, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_FWPC, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_FWPS, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB0ADDR, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB0MASK, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB0CTL, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB0ASID, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB1ADDR, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB1MASK, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB1CTL, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB1ASID, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB2ADDR, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB2MASK, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB2CTL, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB2ASID, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB3ADDR, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB3MASK, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB3CTL, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB3ASID, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB4ADDR, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB4MASK, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB4CTL, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB4ASID, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB5ADDR, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB5MASK, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB5CTL, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB5ASID, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB6ADDR, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB6MASK, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB6CTL, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB6ASID, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB7ADDR, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB7MASK, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB7CTL, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_IB7ASID, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_DEBUG, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_DERA, 0); +- kvm_msr_entry_add(cpu, LOONGARCH_CSR_DESAVE, 0); +- +- ret = kvm_vcpu_ioctl(cs, KVM_GET_MSRS, cpu->kvm_msr_buf); +- if (ret < cpu->kvm_msr_buf->ncsrs) { +- struct kvm_csr_entry *e = &cpu->kvm_msr_buf->entries[ret]; ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_MWPC, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_MWPS, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_DB0ADDR, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_DB0MASK, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_DB0CTL, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_DB0ASID, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_DB1ADDR, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_DB1MASK, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_DB1CTL, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_DB1ASID, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_DB2ADDR, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_DB2MASK, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_DB2CTL, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_DB2ASID, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_DB3ADDR, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_DB3MASK, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_DB3CTL, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_DB3ASID, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_FWPC, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_FWPS, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB0ADDR, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB0MASK, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB0CTL, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB0ASID, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB1ADDR, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB1MASK, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB1CTL, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB1ASID, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB2ADDR, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB2MASK, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB2CTL, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB2ASID, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB3ADDR, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB3MASK, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB3CTL, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB3ASID, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB4ADDR, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB4MASK, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB4CTL, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB4ASID, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB5ADDR, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB5MASK, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB5CTL, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB5ASID, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB6ADDR, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB6MASK, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB6CTL, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB6ASID, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB7ADDR, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB7MASK, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB7CTL, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_IB7ASID, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_DEBUG, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_DERA, 0); ++ kvm_csr_entry_add(cpu, LOONGARCH_CSR_DESAVE, 0); ++ ++ ret = kvm_vcpu_ioctl(cs, KVM_GET_MSRS, cpu->kvm_csr_buf); ++ if (ret < cpu->kvm_csr_buf->ncsrs) { ++ struct kvm_csr_entry *e = &cpu->kvm_csr_buf->entries[ret]; + printf("error: failed to get CSR 0x%" PRIx32"\n", + (uint32_t)e->index); + } +-- +2.27.0 +