diff --git a/0350-cpus-stop-vm-in-suspended-runstate.patch b/0350-cpus-stop-vm-in-suspended-runstate.patch new file mode 100644 index 0000000000000000000000000000000000000000..59bfd666efd1e3b77593f670c03cea46a24189e8 --- /dev/null +++ b/0350-cpus-stop-vm-in-suspended-runstate.patch @@ -0,0 +1,243 @@ +From 6c242ff0ac6f0bde07212e7ee2a08d563c16d5d6 Mon Sep 17 00:00:00 2001 +From: Steve Sistare +Date: Wed, 3 Jan 2024 12:05:31 -0800 +Subject: [PATCH] cpus: stop vm in suspended runstate + +commit b9ae473d80302519a7b89f98795a80abfea1deea upstream + +Currently, a vm in the suspended state is not completely stopped. The VCPUs +have been paused, but the cpu clock still runs, and runstate notifiers for +the transition to stopped have not been called. This causes problems for +live migration. Stale cpu timers_state is saved to the migration stream, +causing time errors in the guest when it wakes from suspend, and state that +would have been modified by runstate notifiers is wrong. + +Modify vm_stop to completely stop the vm if the current state is suspended, +transition to RUN_STATE_PAUSED, and remember that the machine was suspended. +Modify vm_start to restore the suspended state. + +This affects all callers of vm_stop and vm_start, notably, the qapi stop and +cont commands: + + old behavior: + RUN_STATE_SUSPENDED --> stop --> RUN_STATE_SUSPENDED + + new behavior: + RUN_STATE_SUSPENDED --> stop --> RUN_STATE_PAUSED + RUN_STATE_PAUSED --> cont --> RUN_STATE_SUSPENDED + +For example: + + (qemu) info status + VM status: paused (suspended) + + (qemu) stop + (qemu) info status + VM status: paused + + (qemu) system_wakeup + Error: Unable to wake up: guest is not in suspended state + + (qemu) cont + (qemu) info status + VM status: paused (suspended) + + (qemu) system_wakeup + (qemu) info status + VM status: running + +Suggested-by: Peter Xu +Signed-off-by: Steve Sistare +Reviewed-by: Peter Xu +Link: https://lore.kernel.org/r/1704312341-66640-3-git-send-email-steven.sistare@oracle.com +Signed-off-by: Peter Xu +Signed-off-by: priyanka-mani +Signed-off-by: mohanasv +--- + include/sysemu/runstate.h | 9 +++++++++ + qapi/misc.json | 11 +++++++++-- + qapi/run-state.json | 6 +++--- + system/cpus.c | 23 +++++++++++++++-------- + system/runstate.c | 3 +++ + 5 files changed, 39 insertions(+), 13 deletions(-) + +diff --git a/include/sysemu/runstate.h b/include/sysemu/runstate.h +index 88a67e22b0..618eb491af 100644 +--- a/include/sysemu/runstate.h ++++ b/include/sysemu/runstate.h +@@ -40,6 +40,15 @@ static inline bool shutdown_caused_by_guest(ShutdownCause cause) + return cause >= SHUTDOWN_CAUSE_GUEST_SHUTDOWN; + } + ++/* ++ * In a "live" state, the vcpu clock is ticking, and the runstate notifiers ++ * think we are running. ++ */ ++static inline bool runstate_is_live(RunState state) ++{ ++ return state == RUN_STATE_RUNNING || state == RUN_STATE_SUSPENDED; ++} ++ + void vm_start(void); + + /** +diff --git a/qapi/misc.json b/qapi/misc.json +index cda2effa81..3622d98d01 100644 +--- a/qapi/misc.json ++++ b/qapi/misc.json +@@ -134,7 +134,7 @@ + ## + # @stop: + # +-# Stop all guest VCPU execution. ++# Stop guest VM execution. + # + # Since: 0.14 + # +@@ -143,6 +143,9 @@ + # the guest remains paused once migration finishes, as if the -S + # option was passed on the command line. + # ++# In the "suspended" state, it will completely stop the VM and ++# cause a transition to the "paused" state. (Since 9.0) ++# + # Example: + # + # -> { "execute": "stop" } +@@ -153,7 +156,7 @@ + ## + # @cont: + # +-# Resume guest VCPU execution. ++# Resume guest VM execution. + # + # Since: 0.14 + # +@@ -165,6 +168,10 @@ + # guest starts once migration finishes, removing the effect of the + # -S command line option if it was passed. + # ++# If the VM was previously suspended, and not been reset or woken, ++# this command will transition back to the "suspended" state. ++# (Since 9.0) ++# + # Example: + # + # -> { "execute": "cont" } +diff --git a/qapi/run-state.json b/qapi/run-state.json +index f216ba54ec..ca05502e0a 100644 +--- a/qapi/run-state.json ++++ b/qapi/run-state.json +@@ -102,7 +102,7 @@ + ## + # @StatusInfo: + # +-# Information about VCPU run state ++# Information about VM run state + # + # @running: true if all VCPUs are runnable, false if not runnable + # +@@ -130,9 +130,9 @@ + ## + # @query-status: + # +-# Query the run status of all VCPUs ++# Query the run status of the VM + # +-# Returns: @StatusInfo reflecting all VCPUs ++# Returns: @StatusInfo reflecting the VM + # + # Since: 0.14 + # +diff --git a/system/cpus.c b/system/cpus.c +index 67e6350207..061d1509ee 100644 +--- a/system/cpus.c ++++ b/system/cpus.c +@@ -291,11 +291,15 @@ bool vm_get_suspended(void) + static int do_vm_stop(RunState state, bool send_stop) + { + int ret = 0; ++ RunState oldstate = runstate_get(); + +- if (runstate_is_running()) { ++ if (runstate_is_live(oldstate)) { ++ vm_was_suspended = (oldstate == RUN_STATE_SUSPENDED); + runstate_set(state); + cpu_disable_ticks(); +- pause_all_vcpus(); ++ if (oldstate == RUN_STATE_RUNNING) { ++ pause_all_vcpus(); ++ } + vm_state_notify(0, state); + if (send_stop) { + qapi_event_send_stop(); +@@ -708,11 +712,13 @@ int vm_stop(RunState state) + + /** + * Prepare for (re)starting the VM. +- * Returns -1 if the vCPUs are not to be restarted (e.g. if they are already +- * running or in case of an error condition), 0 otherwise. ++ * Returns 0 if the vCPUs should be restarted, -1 on an error condition, ++ * and 1 otherwise. + */ + int vm_prepare_start(bool step_pending) + { ++ int ret = vm_was_suspended ? 1 : 0; ++ RunState state = vm_was_suspended ? RUN_STATE_SUSPENDED : RUN_STATE_RUNNING; + RunState requested; + + qemu_vmstop_requested(&requested); +@@ -743,9 +749,10 @@ int vm_prepare_start(bool step_pending) + qapi_event_send_resume(); + + cpu_enable_ticks(); +- runstate_set(RUN_STATE_RUNNING); +- vm_state_notify(1, RUN_STATE_RUNNING); +- return 0; ++ runstate_set(state); ++ vm_state_notify(1, state); ++ vm_was_suspended = false; ++ return ret; + } + + void vm_start(void) +@@ -759,7 +766,7 @@ void vm_start(void) + current state is forgotten forever */ + int vm_stop_force_state(RunState state) + { +- if (runstate_is_running()) { ++ if (runstate_is_live(runstate_get())) { + return vm_stop(state); + } else { + int ret; +diff --git a/system/runstate.c b/system/runstate.c +index 365f2f44b9..0465505447 100644 +--- a/system/runstate.c ++++ b/system/runstate.c +@@ -108,6 +108,7 @@ static const RunStateTransition runstate_transitions_def[] = { + { RUN_STATE_PAUSED, RUN_STATE_POSTMIGRATE }, + { RUN_STATE_PAUSED, RUN_STATE_PRELAUNCH }, + { RUN_STATE_PAUSED, RUN_STATE_COLO}, ++ { RUN_STATE_PAUSED, RUN_STATE_SUSPENDED}, + + { RUN_STATE_POSTMIGRATE, RUN_STATE_RUNNING }, + { RUN_STATE_POSTMIGRATE, RUN_STATE_FINISH_MIGRATE }, +@@ -161,6 +162,7 @@ static const RunStateTransition runstate_transitions_def[] = { + { RUN_STATE_SUSPENDED, RUN_STATE_FINISH_MIGRATE }, + { RUN_STATE_SUSPENDED, RUN_STATE_PRELAUNCH }, + { RUN_STATE_SUSPENDED, RUN_STATE_COLO}, ++ { RUN_STATE_SUSPENDED, RUN_STATE_PAUSED}, + + { RUN_STATE_WATCHDOG, RUN_STATE_RUNNING }, + { RUN_STATE_WATCHDOG, RUN_STATE_FINISH_MIGRATE }, +@@ -506,6 +508,7 @@ void qemu_system_reset(ShutdownCause reason) + cpu_synchronize_all_post_reset(); + + cpus_control_post_system_reset(); ++ vm_set_suspended(false); + } + + /* +-- +2.43.0 + diff --git a/0351-runstate-skip-initial-cpu-reset-if-reset-is-not-actu.patch b/0351-runstate-skip-initial-cpu-reset-if-reset-is-not-actu.patch new file mode 100644 index 0000000000000000000000000000000000000000..739e661d234728be35d7f3d5bb4fdcc89f8dfd49 --- /dev/null +++ b/0351-runstate-skip-initial-cpu-reset-if-reset-is-not-actu.patch @@ -0,0 +1,63 @@ +From a15277902f2e1486f986211fb5a8d2e67afaf008 Mon Sep 17 00:00:00 2001 +From: Paolo Bonzini +Date: Mon, 18 Mar 2024 17:45:56 -0400 +Subject: [PATCH] runstate: skip initial CPU reset if reset is not actually + possible +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +commit 08b2d15cdd0d3fbbe37ce23bf192b770db3a7539 upstream + +Right now, the system reset is concluded by a call to +cpu_synchronize_all_post_reset() in order to sync any changes +that the machine reset callback applied to the CPU state. + +However, for VMs with encrypted state such as SEV-ES guests (currently +the only case of guests with non-resettable CPUs) this cannot be done, +because guest state has already been finalized by machine-init-done notifiers. +cpu_synchronize_all_post_reset() does nothing on these guests, and actually +we would like to make it fail if called once guest has been encrypted. +So, assume that boards that support non-resettable CPUs do not touch +CPU state and that all such setup is done before, at the time of +cpu_synchronize_all_post_init(). + +Reviewed-by: Philippe Mathieu-Daudé +Signed-off-by: Paolo Bonzini +Signed-off-by: priyanka-mani +Signed-off-by: mohanasv +--- + system/runstate.c | 15 ++++++++++++++- + 1 file changed, 14 insertions(+), 1 deletion(-) + +diff --git a/system/runstate.c b/system/runstate.c +index 0465505447..cbdac6597a 100644 +--- a/system/runstate.c ++++ b/system/runstate.c +@@ -505,9 +505,22 @@ void qemu_system_reset(ShutdownCause reason) + default: + qapi_event_send_reset(shutdown_caused_by_guest(reason), reason); + } +- cpu_synchronize_all_post_reset(); + + cpus_control_post_system_reset(); ++ ++ /* ++ * Some boards use the machine reset callback to point CPUs to the firmware ++ * entry point. Assume that this is not the case for boards that support ++ * non-resettable CPUs (currently used only for confidential guests), in ++ * which case cpu_synchronize_all_post_init() is enough because ++ * it does _more_ than cpu_synchronize_all_post_reset(). ++ */ ++ if (cpus_are_resettable()) { ++ cpu_synchronize_all_post_reset(); ++ } else { ++ assert(runstate_check(RUN_STATE_PRELAUNCH)); ++ } ++ + vm_set_suspended(false); + } + +-- +2.43.0 + diff --git a/0352-migration-prevent-migration-when-vm-has-poisoned-mem.patch b/0352-migration-prevent-migration-when-vm-has-poisoned-mem.patch new file mode 100644 index 0000000000000000000000000000000000000000..bc67d4e4d075620780bd69eda815cf9e20cad93a --- /dev/null +++ b/0352-migration-prevent-migration-when-vm-has-poisoned-mem.patch @@ -0,0 +1,113 @@ +From 6cba231a7e727f8e86fbfd3a8ffe97b6859ef3fe Mon Sep 17 00:00:00 2001 +From: William Roche +Date: Tue, 30 Jan 2024 19:06:40 +0000 +Subject: [PATCH] migration: prevent migration when VM has poisoned memory + +commit 06152b89db64bc5ccec1e54576706ba891654df9 upstream + +A memory page poisoned from the hypervisor level is no longer readable. +The migration of a VM will crash Qemu when it tries to read the +memory address space and stumbles on the poisoned page with a similar +stack trace: + +Program terminated with signal SIGBUS, Bus error. + +To avoid this VM crash during the migration, prevent the migration +when a known hardware poison exists on the VM. + +Signed-off-by: William Roche +Link: https://lore.kernel.org/r/20240130190640.139364-2-william.roche@oracle.com +Signed-off-by: Peter Xu +Signed-off-by: priyanka-mani +Signed-off-by: mohanasv +--- + accel/kvm/kvm-all.c | 10 ++++++++++ + accel/stubs/kvm-stub.c | 5 +++++ + include/sysemu/kvm.h | 6 ++++++ + migration/migration.c | 7 +++++++ + 4 files changed, 28 insertions(+) + +diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c +index 0fddb20921..aaee470b8a 100644 +--- a/accel/kvm/kvm-all.c ++++ b/accel/kvm/kvm-all.c +@@ -1168,6 +1168,11 @@ int kvm_vm_check_extension(KVMState *s, unsigned int extension) + return ret; + } + ++/* ++ * We track the poisoned pages to be able to: ++ * - replace them on VM reset ++ * - block a migration for a VM with a poisoned page ++ */ + typedef struct HWPoisonPage { + ram_addr_t ram_addr; + QLIST_ENTRY(HWPoisonPage) list; +@@ -1201,6 +1206,11 @@ void kvm_hwpoison_page_add(ram_addr_t ram_addr) + QLIST_INSERT_HEAD(&hwpoison_page_list, page, list); + } + ++bool kvm_hwpoisoned_mem(void) ++{ ++ return !QLIST_EMPTY(&hwpoison_page_list); ++} ++ + static uint32_t adjust_ioeventfd_endianness(uint32_t val, uint32_t size) + { + #if HOST_BIG_ENDIAN != TARGET_BIG_ENDIAN +diff --git a/accel/stubs/kvm-stub.c b/accel/stubs/kvm-stub.c +index b90d516755..c2e7c2f660 100644 +--- a/accel/stubs/kvm-stub.c ++++ b/accel/stubs/kvm-stub.c +@@ -127,3 +127,8 @@ uint32_t kvm_dirty_ring_size(void) + { + return 0; + } ++ ++bool kvm_hwpoisoned_mem(void) ++{ ++ return false; ++} +diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h +index 1f7d36f4d3..fa1e42f085 100644 +--- a/include/sysemu/kvm.h ++++ b/include/sysemu/kvm.h +@@ -589,4 +589,10 @@ uint32_t kvm_dirty_ring_size(void); + + int kvm_load_user_data(hwaddr loader_start, hwaddr image_end, hwaddr initrd_start, hwaddr dtb_end, hwaddr ram_size, + struct kvm_numa_info *numa_info); ++ ++/** ++ * kvm_hwpoisoned_mem - indicate if there is any hwpoisoned page ++ * reported for the VM. ++ */ ++bool kvm_hwpoisoned_mem(void); + #endif +diff --git a/migration/migration.c b/migration/migration.c +index 982ab85f04..8b1b47836f 100644 +--- a/migration/migration.c ++++ b/migration/migration.c +@@ -67,6 +67,7 @@ + #include "options.h" + #include "sysemu/dirtylimit.h" + #include "qemu/sockets.h" ++#include "sysemu/kvm.h" + + static NotifierList migration_state_notifiers = + NOTIFIER_LIST_INITIALIZER(migration_state_notifiers); +@@ -1900,6 +1901,12 @@ static bool migrate_prepare(MigrationState *s, bool blk, bool blk_inc, + return false; + } + ++ if (kvm_hwpoisoned_mem()) { ++ error_setg(errp, "Can't migrate this vm with hardware poisoned memory, " ++ "please reboot the vm and try again"); ++ return false; ++ } ++ + if (migration_is_blocked(errp)) { + return false; + } +-- +2.43.0 + diff --git a/0353-scripts-update-linux-header-sh-be-more-src-tree-frie.patch b/0353-scripts-update-linux-header-sh-be-more-src-tree-frie.patch new file mode 100644 index 0000000000000000000000000000000000000000..01211860ddf0a713b2c83b13fd8dadc05cbb5aba --- /dev/null +++ b/0353-scripts-update-linux-header-sh-be-more-src-tree-frie.patch @@ -0,0 +1,181 @@ +From 63419b20345b2d2d69efad4d7412c2e84db24cae Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Alex=20Benn=C3=A9e?= +Date: Tue, 14 May 2024 18:42:44 +0100 +Subject: [PATCH] scripts/update-linux-header.sh: be more src tree friendly +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +commit b51ddd937f11f76614d4b36d14d8778df242661c upstream + +Running "install_headers" in the Linux source tree is fairly +unfriendly as out-of-tree builds will start complaining about the +kernel source being non-pristine. As we have a temporary directory for +the install we should also do the build step here. So now we have: + + $tmpdir/ + $blddir/ + $hdrdir/ + +Reviewed-by: Pierrick Bouvier +Reviewed-by: Michael S. Tsirkin +Signed-off-by: Alex Bennée +Message-Id: <20240514174253.694591-3-alex.bennee@linaro.org> +--- + scripts/update-linux-headers.sh | 81 +++++++++++++++++---------------- + 1 file changed, 43 insertions(+), 38 deletions(-) + +diff --git a/scripts/update-linux-headers.sh b/scripts/update-linux-headers.sh +index 4153a00957..746573d80c 100755 +--- a/scripts/update-linux-headers.sh ++++ b/scripts/update-linux-headers.sh +@@ -27,6 +27,8 @@ + # types like "__u64". This work is done in the cp_portable function. + + tmpdir=$(mktemp -d) ++hdrdir="$tmpdir/headers" ++blddir="$tmpdir/build" + linux="$1" + output="$2" + +@@ -111,58 +113,61 @@ for arch in $ARCHLIST; do + arch_var=ARCH + fi + +- make -C "$linux" INSTALL_HDR_PATH="$tmpdir" $arch_var=$arch headers_install ++ make -C "$linux" O="$blddir" INSTALL_HDR_PATH="$hdrdir" $arch_var=$arch headers_install + + rm -rf "$output/linux-headers/asm-$arch" + mkdir -p "$output/linux-headers/asm-$arch" + for header in kvm.h unistd.h bitsperlong.h mman.h; do +- cp "$tmpdir/include/asm/$header" "$output/linux-headers/asm-$arch" ++ cp "$hdrdir/include/asm/$header" "$output/linux-headers/asm-$arch" + done + + if [ $arch = mips ]; then +- cp "$tmpdir/include/asm/sgidefs.h" "$output/linux-headers/asm-mips/" +- cp "$tmpdir/include/asm/unistd_o32.h" "$output/linux-headers/asm-mips/" +- cp "$tmpdir/include/asm/unistd_n32.h" "$output/linux-headers/asm-mips/" +- cp "$tmpdir/include/asm/unistd_n64.h" "$output/linux-headers/asm-mips/" ++ cp "$hdrdir/include/asm/sgidefs.h" "$output/linux-headers/asm-mips/" ++ cp "$hdrdir/include/asm/unistd_o32.h" "$output/linux-headers/asm-mips/" ++ cp "$hdrdir/include/asm/unistd_n32.h" "$output/linux-headers/asm-mips/" ++ cp "$hdrdir/include/asm/unistd_n64.h" "$output/linux-headers/asm-mips/" + fi + if [ $arch = powerpc ]; then +- cp "$tmpdir/include/asm/unistd_32.h" "$output/linux-headers/asm-powerpc/" +- cp "$tmpdir/include/asm/unistd_64.h" "$output/linux-headers/asm-powerpc/" ++ cp "$hdrdir/include/asm/unistd_32.h" "$output/linux-headers/asm-powerpc/" ++ cp "$hdrdir/include/asm/unistd_64.h" "$output/linux-headers/asm-powerpc/" + fi + + rm -rf "$output/include/standard-headers/asm-$arch" + mkdir -p "$output/include/standard-headers/asm-$arch" + if [ $arch = s390 ]; then +- cp_portable "$tmpdir/include/asm/virtio-ccw.h" "$output/include/standard-headers/asm-s390/" +- cp "$tmpdir/include/asm/unistd_32.h" "$output/linux-headers/asm-s390/" +- cp "$tmpdir/include/asm/unistd_64.h" "$output/linux-headers/asm-s390/" ++ cp_portable "$hdrdir/include/asm/virtio-ccw.h" "$output/include/standard-headers/asm-s390/" ++ cp "$hdrdir/include/asm/unistd_32.h" "$output/linux-headers/asm-s390/" ++ cp "$hdrdir/include/asm/unistd_64.h" "$output/linux-headers/asm-s390/" + fi + if [ $arch = arm ]; then +- cp "$tmpdir/include/asm/unistd-eabi.h" "$output/linux-headers/asm-arm/" +- cp "$tmpdir/include/asm/unistd-oabi.h" "$output/linux-headers/asm-arm/" +- cp "$tmpdir/include/asm/unistd-common.h" "$output/linux-headers/asm-arm/" ++ cp "$hdrdir/include/asm/unistd-eabi.h" "$output/linux-headers/asm-arm/" ++ cp "$hdrdir/include/asm/unistd-oabi.h" "$output/linux-headers/asm-arm/" ++ cp "$hdrdir/include/asm/unistd-common.h" "$output/linux-headers/asm-arm/" + fi + if [ $arch = arm64 ]; then +- cp "$tmpdir/include/asm/sve_context.h" "$output/linux-headers/asm-arm64/" ++ cp "$hdrdir/include/asm/sve_context.h" "$output/linux-headers/asm-arm64/" + fi + if [ $arch = x86 ]; then +- cp "$tmpdir/include/asm/unistd_32.h" "$output/linux-headers/asm-x86/" +- cp "$tmpdir/include/asm/unistd_x32.h" "$output/linux-headers/asm-x86/" +- cp "$tmpdir/include/asm/unistd_64.h" "$output/linux-headers/asm-x86/" +- cp_portable "$tmpdir/include/asm/kvm_para.h" "$output/include/standard-headers/asm-$arch" ++ cp "$hdrdir/include/asm/unistd_32.h" "$output/linux-headers/asm-x86/" ++ cp "$hdrdir/include/asm/unistd_x32.h" "$output/linux-headers/asm-x86/" ++ cp "$hdrdir/include/asm/unistd_64.h" "$output/linux-headers/asm-x86/" ++ cp_portable "$hdrdir/include/asm/kvm_para.h" "$output/include/standard-headers/asm-$arch" + # Remove everything except the macros from bootparam.h avoiding the + # unnecessary import of several video/ist/etc headers + sed -e '/__ASSEMBLY__/,/__ASSEMBLY__/d' \ +- "$tmpdir/include/asm/bootparam.h" > "$tmpdir/bootparam.h" +- cp_portable "$tmpdir/bootparam.h" \ ++ "$hdrdir/include/asm/bootparam.h" > "$hdrdir/bootparam.h" ++ cp_portable "$hdrdir/bootparam.h" \ + "$output/include/standard-headers/asm-$arch" +- cp_portable "$tmpdir/include/asm/setup_data.h" \ ++ cp_portable "$hdrdir/include/asm/setup_data.h" \ + "$output/standard-headers/asm-x86" + fi + if [ $arch = loongarch ]; then + cp "$hdrdir/include/asm/kvm_para.h" "$output/linux-headers/asm-loongarch/" + cp "$hdrdir/include/asm/unistd_64.h" "$output/linux-headers/asm-loongarch/" + fi ++ if [ $arch = riscv ]; then ++ cp "$hdrdir/include/asm/ptrace.h" "$output/linux-headers/asm-riscv/" ++ fi + done + arch= + +@@ -171,13 +176,13 @@ mkdir -p "$output/linux-headers/linux" + for header in const.h stddef.h kvm.h vfio.h vfio_ccw.h vfio_zdev.h vhost.h \ + psci.h psp-sev.h userfaultfd.h memfd.h mman.h nvme_ioctl.h \ + vduse.h iommufd.h bits.h; do +- cp "$tmpdir/include/linux/$header" "$output/linux-headers/linux" ++ cp "$hdrdir/include/linux/$header" "$output/linux-headers/linux" + done + + rm -rf "$output/linux-headers/asm-generic" + mkdir -p "$output/linux-headers/asm-generic" + for header in unistd.h bitsperlong.h mman-common.h mman.h hugetlb_encode.h; do +- cp "$tmpdir/include/asm-generic/$header" "$output/linux-headers/asm-generic" ++ cp "$hdrdir/include/asm-generic/$header" "$output/linux-headers/asm-generic" + done + + if [ -L "$linux/source" ]; then +@@ -212,23 +217,23 @@ EOF + + rm -rf "$output/include/standard-headers/linux" + mkdir -p "$output/include/standard-headers/linux" +-for i in "$tmpdir"/include/linux/*virtio*.h \ +- "$tmpdir/include/linux/qemu_fw_cfg.h" \ +- "$tmpdir/include/linux/fuse.h" \ +- "$tmpdir/include/linux/input.h" \ +- "$tmpdir/include/linux/input-event-codes.h" \ +- "$tmpdir/include/linux/udmabuf.h" \ +- "$tmpdir/include/linux/pci_regs.h" \ +- "$tmpdir/include/linux/ethtool.h" \ +- "$tmpdir/include/linux/const.h" \ +- "$tmpdir/include/linux/kernel.h" \ +- "$tmpdir/include/linux/vhost_types.h" \ +- "$tmpdir/include/linux/sysinfo.h" \ +- "$tmpdir/include/misc/pvpanic.h"; do ++for i in "$hdrdir"/include/linux/*virtio*.h \ ++ "$hdrdir/include/linux/qemu_fw_cfg.h" \ ++ "$hdrdir/include/linux/fuse.h" \ ++ "$hdrdir/include/linux/input.h" \ ++ "$hdrdir/include/linux/input-event-codes.h" \ ++ "$hdrdir/include/linux/udmabuf.h" \ ++ "$hdrdir/include/linux/pci_regs.h" \ ++ "$hdrdir/include/linux/ethtool.h" \ ++ "$hdrdir/include/linux/const.h" \ ++ "$hdrdir/include/linux/kernel.h" \ ++ "$hdrdir/include/linux/vhost_types.h" \ ++ "$hdrdir/include/linux/sysinfo.h" \ ++ "$hdrdir/include/misc/pvpanic.h"; do + cp_portable "$i" "$output/include/standard-headers/linux" + done + mkdir -p "$output/include/standard-headers/drm" +-cp_portable "$tmpdir/include/drm/drm_fourcc.h" \ ++cp_portable "$hdrdir/include/drm/drm_fourcc.h" \ + "$output/include/standard-headers/drm" + + rm -rf "$output/include/standard-headers/drivers/infiniband/hw/vmw_pvrdma" +-- +2.43.0 + diff --git a/0354-scripts-update-linux-headers-sh-remove-temporary-dir.patch b/0354-scripts-update-linux-headers-sh-remove-temporary-dir.patch new file mode 100644 index 0000000000000000000000000000000000000000..3d33a69d2f92a64b6d2ae5274dd7427e19fba548 --- /dev/null +++ b/0354-scripts-update-linux-headers-sh-remove-temporary-dir.patch @@ -0,0 +1,34 @@ +From 2a406ef928b7ed9f40217396f99be24ec9a5009e Mon Sep 17 00:00:00 2001 +From: Thomas Huth +Date: Mon, 27 May 2024 08:02:43 +0200 +Subject: [PATCH] scripts/update-linux-headers.sh: Remove temporary directory + inbetween + +We are reusing the same temporary directory for installing the headers +of all targets, so there could be stale files here when switching from +one target to another. Make sure to delete the folder before installing +a new set of target headers into it. + +Message-ID: <20240527060243.12647-1-thuth@redhat.com> +Reviewed-by: Michael S. Tsirkin +Acked-by: Cornelia Huck +Signed-off-by: Thomas Huth +--- + scripts/update-linux-headers.sh | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/scripts/update-linux-headers.sh b/scripts/update-linux-headers.sh +index 746573d80c..2c9b787740 100755 +--- a/scripts/update-linux-headers.sh ++++ b/scripts/update-linux-headers.sh +@@ -113,6 +113,7 @@ for arch in $ARCHLIST; do + arch_var=ARCH + fi + ++ rm -rf "$hdrdir" + make -C "$linux" O="$blddir" INSTALL_HDR_PATH="$hdrdir" $arch_var=$arch headers_install + + rm -rf "$output/linux-headers/asm-$arch" +-- +2.43.0 + diff --git a/0355-scripts-update-linux-headers-sh-fix-the-path-of-setu.patch b/0355-scripts-update-linux-headers-sh-fix-the-path-of-setu.patch new file mode 100644 index 0000000000000000000000000000000000000000..48ec71abb58a850661839b97b3b0f02be0857a52 --- /dev/null +++ b/0355-scripts-update-linux-headers-sh-fix-the-path-of-setu.patch @@ -0,0 +1,36 @@ +From 5c975b3bafda772be20b21b121706503ab696532 Mon Sep 17 00:00:00 2001 +From: Thomas Huth +Date: Mon, 27 May 2024 08:01:26 +0200 +Subject: [PATCH] scripts/update-linux-headers.sh: Fix the path of setup_data.h + +When running the update-linx-headers.sh script, it currently fails with: + +scripts/update-linux-headers.sh: line 73: .../qemu/standard-headers/asm-x86/setup_data.h: No such file or directory + +The "include" folder is obviously missing here - no clue how this could +have worked before? + +Fixes: 66210a1a30 ("scripts/update-linux-headers: Add setup_data.h to import list") +Message-ID: <20240527060126.12578-1-thuth@redhat.com> +Reviewed-by: Cornelia Huck +Signed-off-by: Thomas Huth +--- + scripts/update-linux-headers.sh | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/scripts/update-linux-headers.sh b/scripts/update-linux-headers.sh +index 2c9b787740..895a2c1722 100755 +--- a/scripts/update-linux-headers.sh ++++ b/scripts/update-linux-headers.sh +@@ -160,7 +160,7 @@ for arch in $ARCHLIST; do + cp_portable "$hdrdir/bootparam.h" \ + "$output/include/standard-headers/asm-$arch" + cp_portable "$hdrdir/include/asm/setup_data.h" \ +- "$output/standard-headers/asm-x86" ++ "$output/include/standard-headers/asm-x86" + fi + if [ $arch = loongarch ]; then + cp "$hdrdir/include/asm/kvm_para.h" "$output/linux-headers/asm-loongarch/" +-- +2.43.0 + diff --git a/0356-util-add-interfaces-to-read-midr-on-aarch64.patch b/0356-util-add-interfaces-to-read-midr-on-aarch64.patch new file mode 100644 index 0000000000000000000000000000000000000000..bee0f34d2cc575ca819ac44083ca15ece9235b8f --- /dev/null +++ b/0356-util-add-interfaces-to-read-midr-on-aarch64.patch @@ -0,0 +1,171 @@ +From 7827ed7eb6a2e0aeaae9ee28bb0d9ee54f5eaf3d Mon Sep 17 00:00:00 2001 +From: Peng Mengguang +Date: Fri, 10 Jan 2025 15:47:42 -0500 +Subject: [PATCH] util: add interfaces to read midr on aarch64 + +Add interfaces to judge the cpu platform. + +Signed-off-by: Peng Mengguang +--- + include/qemu/aarch64-cpuid.h | 51 ++++++++++++++++++++++++ + util/aarch64-cpuid.c | 77 ++++++++++++++++++++++++++++++++++++ + util/meson.build | 1 + + 3 files changed, 129 insertions(+) + create mode 100644 include/qemu/aarch64-cpuid.h + create mode 100644 util/aarch64-cpuid.c + +diff --git a/include/qemu/aarch64-cpuid.h b/include/qemu/aarch64-cpuid.h +new file mode 100644 +index 0000000000..ec68e6d575 +--- /dev/null ++++ b/include/qemu/aarch64-cpuid.h +@@ -0,0 +1,51 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * aarch64-cpuid.h: Macros to identify the MIDR of aarch64. ++ * ++ * This work is licensed under the terms of the GNU GPL, version 2 or later. ++ * See the COPYING file in the top-level directory. ++ */ ++ ++#ifndef QEMU_AARCH64_CPUID_H ++#define QEMU_AARCH64_CPUID_H ++ ++#define MIDR_REVISION_MASK 0xf ++#define MIDR_REVISION(midr) ((midr) & MIDR_REVISION_MASK) ++#define MIDR_PARTNUM_SHIFT 4 ++#define MIDR_PARTNUM_MASK (0xfff << MIDR_PARTNUM_SHIFT) ++#define MIDR_PARTNUM(midr) \ ++ (((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT) ++#define MIDR_ARCHITECTURE_SHIFT 16 ++#define MIDR_ARCHITECTURE_MASK (0xf << MIDR_ARCHITECTURE_SHIFT) ++#define MIDR_ARCHITECTURE(midr) \ ++ (((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT) ++#define MIDR_VARIANT_SHIFT 20 ++#define MIDR_VARIANT_MASK (0xf << MIDR_VARIANT_SHIFT) ++#define MIDR_VARIANT(midr) \ ++ (((midr) & MIDR_VARIANT_MASK) >> MIDR_VARIANT_SHIFT) ++#define MIDR_IMPLEMENTOR_SHIFT 24 ++#define MIDR_IMPLEMENTOR_MASK (0xffU << MIDR_IMPLEMENTOR_SHIFT) ++#define MIDR_IMPLEMENTOR(midr) \ ++ (((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT) ++#define MIDR_CPU_MODEL(imp, partnum) \ ++ (((imp) << MIDR_IMPLEMENTOR_SHIFT) | \ ++ (0xf << MIDR_ARCHITECTURE_SHIFT) | \ ++ ((partnum) << MIDR_PARTNUM_SHIFT)) ++ ++#define MIDR_CPU_VAR_REV(var, rev) \ ++ (((var) << MIDR_VARIANT_SHIFT) | (rev)) ++ ++#define MIDR_CPU_MODEL_MASK (MIDR_IMPLEMENTOR_MASK | MIDR_PARTNUM_MASK | \ ++ MIDR_ARCHITECTURE_MASK) ++ ++#define ARM_CPU_IMP_PHYTIUM 0x70 ++#define PHYTIUM_CPU_PART_FTC662 0x662 ++#define PHYTIUM_CPU_PART_FTC663 0x663 ++#define PHYTIUM_CPU_PART_FTC862 0x862 ++ ++uint64_t qemu_read_cpuid_id(void); ++uint8_t qemu_read_cpuid_implementor(void); ++uint16_t qemu_read_cpuid_part_number(void); ++bool is_phytium_cpu(void); ++ ++#endif +diff --git a/util/aarch64-cpuid.c b/util/aarch64-cpuid.c +new file mode 100644 +index 0000000000..568f28b283 +--- /dev/null ++++ b/util/aarch64-cpuid.c +@@ -0,0 +1,77 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Dealing with arm cpu identification information. ++ * ++ * Copyright (C) 2024 Phytium, Inc. ++ * ++ * Authors: ++ * Peng Meng Guang ++ * ++ * This work is licensed under the terms of the GNU LGPL, version 2.1 ++ * or later. See the COPYING.LIB file in the top-level directory. ++ */ ++ ++#include ++#include "qemu/osdep.h" ++#include "qemu/cutils.h" ++#include "qemu/aarch64-cpuid.h" ++ ++#if defined(__aarch64__) ++uint64_t qemu_read_cpuid_id(void) ++{ ++#ifdef CONFIG_LINUX ++ const char *file = "/sys/devices/system/cpu/cpu0/regs/identification/midr_el1"; ++ char *buf; ++ uint64_t midr = 0; ++ ++#define BUF_SIZE 32 ++ buf = g_malloc0(BUF_SIZE); ++ if (!buf) { ++ return 0; ++ } ++ ++ if (!g_file_get_contents(file, &buf, 0, NULL)) { ++ goto out; ++ } ++ ++ if (qemu_strtoul(buf, NULL, 0, &midr) < 0) { ++ goto out; ++ } ++ ++out: ++ g_free(buf); ++ ++ return midr; ++#else ++ return 0; ++#endif ++} ++ ++uint8_t qemu_read_cpuid_implementor(void) ++{ ++#ifdef CONFIG_LINUX ++ uint64_t aarch64_midr = qemu_read_cpuid_id(); ++ ++ return MIDR_IMPLEMENTOR(aarch64_midr); ++#else ++ return 0; ++#endif ++} ++ ++uint16_t qemu_read_cpuid_part_number(void) ++{ ++#ifdef CONFIG_LINUX ++ uint64_t aarch64_midr = qemu_read_cpuid_id(); ++ ++ return MIDR_PARTNUM(aarch64_midr); ++#else ++ return 0; ++#endif ++} ++ ++bool is_phytium_cpu(void) ++{ ++ return qemu_read_cpuid_implementor() == ARM_CPU_IMP_PHYTIUM; ++} ++ ++#endif +diff --git a/util/meson.build b/util/meson.build +index c2322ef6e7..5ca44750da 100644 +--- a/util/meson.build ++++ b/util/meson.build +@@ -63,6 +63,7 @@ util_ss.add(files('int128.c')) + util_ss.add(files('memalign.c')) + util_ss.add(files('interval-tree.c')) + util_ss.add(files('lockcnt.c')) ++util_ss.add(files('aarch64-cpuid.c')) + + if have_user + util_ss.add(files('selfmap.c')) +-- +2.43.0 + diff --git a/0357-cpu-add-phytium-v-cpu-support.patch b/0357-cpu-add-phytium-v-cpu-support.patch new file mode 100644 index 0000000000000000000000000000000000000000..619357a48838b84818f9214d36606011a6fcb6ad --- /dev/null +++ b/0357-cpu-add-phytium-v-cpu-support.patch @@ -0,0 +1,184 @@ +From be9e40ef448b4cd2ba906cc9189b10fcabd38b5e Mon Sep 17 00:00:00 2001 +From: Peng Mengguang +Date: Mon, 13 Jan 2025 18:03:16 -0500 +Subject: [PATCH] cpu: add phytium-v cpu support + +phytium-v as a minimal set of phytium server features. +this model is only used for live migration. + +Signed-off-by: Peng Mengguang +--- + hw/arm/virt.c | 1 + + target/arm/cpu64.c | 13 ++++++ + target/arm/kvm64.c | 101 +++++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 115 insertions(+) + +diff --git a/hw/arm/virt.c b/hw/arm/virt.c +index 6087207f38..eaf29f5c94 100644 +--- a/hw/arm/virt.c ++++ b/hw/arm/virt.c +@@ -222,6 +222,7 @@ static const char *valid_cpus[] = { + ARM_CPU_TYPE_NAME("cortex-a57"), + ARM_CPU_TYPE_NAME("host"), + ARM_CPU_TYPE_NAME("max"), ++ ARM_CPU_TYPE_NAME("phytium-v"), + }; + + static bool cpu_type_valid(const char *cpu) +diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c +index 1e9c6c85ae..b4326ce8ba 100644 +--- a/target/arm/cpu64.c ++++ b/target/arm/cpu64.c +@@ -741,10 +741,23 @@ static void aarch64_max_initfn(Object *obj) + } + } + ++static void aarch64_phytium_v_initfn(Object *obj) ++{ ++ ARMCPU *cpu = ARM_CPU(obj); ++ ++ if (kvm_enabled()) { ++ kvm_arm_set_cpu_features_from_host(cpu); ++ } else { ++ aarch64_a53_initfn(obj); ++ cpu->midr = 0x701f6622; ++ } ++} ++ + static const ARMCPUInfo aarch64_cpus[] = { + { .name = "cortex-a57", .initfn = aarch64_a57_initfn }, + { .name = "cortex-a53", .initfn = aarch64_a53_initfn }, + { .name = "max", .initfn = aarch64_max_initfn }, ++ { .name = "phytium-v", .initfn = aarch64_phytium_v_initfn }, + #if defined(CONFIG_KVM) || defined(CONFIG_HVF) + { .name = "host", .initfn = aarch64_host_initfn }, + #endif +diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c +index a09347254f..45493065ef 100644 +--- a/target/arm/kvm64.c ++++ b/target/arm/kvm64.c +@@ -31,6 +31,7 @@ + #include "cpu-features.h" + #include "hw/acpi/acpi.h" + #include "hw/acpi/ghes.h" ++#include "qemu/aarch64-cpuid.h" + + static bool have_guest_debug; + +@@ -553,6 +554,92 @@ static int kvm_arm_sve_set_vls(CPUState *cs) + + #define ARM_CPU_ID_MPIDR 3, 0, 0, 0, 5 + ++#define SYS_ID_PFR0_EL1 ARM64_SYS_REG(3, 0, 0, 1, 0) ++#define SYS_ID_PFR1_EL1 ARM64_SYS_REG(3, 0, 0, 1, 1) ++#define SYS_ID_PFR2_EL1 ARM64_SYS_REG(3, 0, 0, 3, 4) ++#define SYS_ID_DFR0_EL1 ARM64_SYS_REG(3, 0, 0, 1, 2) ++#define SYS_ID_MMFR0_EL1 ARM64_SYS_REG(3, 0, 0, 1, 4) ++#define SYS_ID_MMFR1_EL1 ARM64_SYS_REG(3, 0, 0, 1, 5) ++#define SYS_ID_MMFR2_EL1 ARM64_SYS_REG(3, 0, 0, 1, 6) ++#define SYS_ID_MMFR3_EL1 ARM64_SYS_REG(3, 0, 0, 1, 7) ++#define SYS_ID_MMFR4_EL1 ARM64_SYS_REG(3, 0, 0, 2, 6) ++#define SYS_ID_ISAR0_EL1 ARM64_SYS_REG(3, 0, 0, 2, 0) ++#define SYS_ID_ISAR1_EL1 ARM64_SYS_REG(3, 0, 0, 2, 1) ++#define SYS_ID_ISAR2_EL1 ARM64_SYS_REG(3, 0, 0, 2, 2) ++#define SYS_ID_ISAR3_EL1 ARM64_SYS_REG(3, 0, 0, 2, 3) ++#define SYS_ID_ISAR4_EL1 ARM64_SYS_REG(3, 0, 0, 2, 4) ++#define SYS_ID_ISAR5_EL1 ARM64_SYS_REG(3, 0, 0, 2, 5) ++#define SYS_ID_ISAR6_EL1 ARM64_SYS_REG(3, 0, 0, 2, 7) ++#define SYS_MVFR0_EL1 ARM64_SYS_REG(3, 0, 0, 3, 0) ++#define SYS_MVFR1_EL1 ARM64_SYS_REG(3, 0, 0, 3, 1) ++#define SYS_MVFR2_EL1 ARM64_SYS_REG(3, 0, 0, 3, 2) ++#define SYS_ID_AA64PFR0_EL1 ARM64_SYS_REG(3, 0, 0, 4, 0) ++#define SYS_ID_AA64PFR1_EL1 ARM64_SYS_REG(3, 0, 0, 4, 1) ++#define SYS_ID_AA64DFR0_EL1 ARM64_SYS_REG(3, 0, 0, 5, 0) ++#define SYS_ID_AA64ISAR0_EL1 ARM64_SYS_REG(3, 0, 0, 6, 0) ++#define SYS_ID_AA64ISAR1_EL1 ARM64_SYS_REG(3, 0, 0, 6, 1) ++#define SYS_ID_AA64MMFR0_EL1 ARM64_SYS_REG(3, 0, 0, 7, 0) ++#define SYS_ID_AA64MMFR1_EL1 ARM64_SYS_REG(3, 0, 0, 7, 1) ++#define SYS_ID_AA64MMFR2_EL1 ARM64_SYS_REG(3, 0, 0, 7, 2) ++ ++struct SysRegInfo { ++ const char *name; ++ uint64_t reg; ++ uint64_t value; ++}; ++ ++const struct SysRegInfo sys_regs_info[] = { ++ { "ID_PFR0_EL1", SYS_ID_PFR0_EL1, 0 }, ++ { "ID_PFR1_EL1", SYS_ID_PFR1_EL1, 0 }, ++ { "ID_PFR2_EL1", SYS_ID_PFR2_EL1, 0 }, ++ { "ID_DFR0_EL1", SYS_ID_DFR0_EL1, 0 }, ++ { "ID_MMFR0_EL1", SYS_ID_MMFR0_EL1, 0 }, ++ { "ID_MMFR1_EL1", SYS_ID_MMFR1_EL1, 0 }, ++ { "ID_MMFR2_EL1", SYS_ID_MMFR2_EL1, 0 }, ++ { "ID_MMFR3_EL1", SYS_ID_MMFR3_EL1, 0 }, ++ { "ID_MMFR4_EL1", SYS_ID_MMFR4_EL1, 0 }, ++ { "ID_ISAR0_EL1", SYS_ID_ISAR0_EL1, 0 }, ++ { "ID_ISAR1_EL1", SYS_ID_ISAR1_EL1, 0 }, ++ { "ID_ISAR2_EL1", SYS_ID_ISAR2_EL1, 0 }, ++ { "ID_ISAR3_EL1", SYS_ID_ISAR3_EL1, 0 }, ++ { "ID_ISAR4_EL1", SYS_ID_ISAR4_EL1, 0 }, ++ { "ID_ISAR5_EL1", SYS_ID_ISAR5_EL1, 0 }, ++ { "ID_ISAR6_EL1", SYS_ID_ISAR6_EL1, 0 }, ++ { "MVFR0_EL1", SYS_MVFR0_EL1, 0 }, ++ { "MVFR1_EL1", SYS_MVFR1_EL1, 0 }, ++ { "MVFR2_EL1", SYS_MVFR2_EL1, 0 }, ++ { "ID_AA64PFR0_EL1", SYS_ID_AA64PFR0_EL1, 0x01001111 }, ++ { "ID_AA64PFR1_EL1", SYS_ID_AA64PFR1_EL1, 0 }, ++ { "ID_AA64DFR0_EL1", SYS_ID_AA64DFR0_EL1, 0x10305106 }, ++ { "ID_AA64ISAR0_EL1", SYS_ID_AA64ISAR0_EL1, 0x10000 }, ++ { "ID_AA64ISAR1_EL1", SYS_ID_AA64ISAR1_EL1, 0 }, ++ { "ID_AA64MMFR0_EL1", SYS_ID_AA64MMFR0_EL1, 0x1124 }, ++ { "ID_AA64MMFR1_EL1", SYS_ID_AA64MMFR1_EL1, 0 }, ++ { "ID_AA64MMFR2_EL1", SYS_ID_AA64MMFR2_EL1, 0 }, ++}; ++ ++/* PHYTIUM : modify sys_regs for phytium-v. */ ++static int modify_arm_vcpu_regs_for_phytium_v(ARMCPU *cpu) ++{ ++ int ret = 0; ++ CPUState *cs = CPU(cpu); ++ Object *obj = OBJECT(cpu); ++ ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); ++ ++ if (NULL != acc->info && 0 == strcmp(acc->info->name, "phytium-v")) { ++ uint64_t val = 0; ++ for (int i = 0; i < ARRAY_SIZE(sys_regs_info); i++) { ++ val = sys_regs_info[i].value; ++ ret = kvm_set_one_reg(cs, sys_regs_info[i].reg, &val); ++ if (ret) { ++ break; ++ } ++ } ++ } ++ ++ return ret; ++} ++ + int kvm_arch_init_vcpu(CPUState *cs) + { + int ret; +@@ -604,6 +691,20 @@ int kvm_arch_init_vcpu(CPUState *cs) + return ret; + } + ++ /* ++ * For Phytium only, we'll modify registers' value like ID_AA64ISAR0_EL1 ++ * before the virtual machine used for live-migration is started to ensure ++ * that the virtual machine is successfully migrated between different ++ * models of Phytium servers. ++ * Of course, the above will only happen if the CPU model "phytium-v" ++ * is selected during live migration. ++ */ ++ if (is_phytium_cpu()) { ++ ret = modify_arm_vcpu_regs_for_phytium_v(cpu); ++ if (ret < 0) ++ return ret; ++ } ++ + if (cpu_isar_feature(aa64_sve, cpu)) { + ret = kvm_arm_sve_set_vls(cs); + if (ret) { +-- +2.43.0 + diff --git a/0358-target-arm-support-vm-live-migration-between-phytium.patch b/0358-target-arm-support-vm-live-migration-between-phytium.patch new file mode 100644 index 0000000000000000000000000000000000000000..a10dd6869fa1f3d26dbba0fdd9d275318382d702 --- /dev/null +++ b/0358-target-arm-support-vm-live-migration-between-phytium.patch @@ -0,0 +1,154 @@ +From 8dcf74338705adc39055f4d55d9cbccbf54578e0 Mon Sep 17 00:00:00 2001 +From: Peng Mengguang +Date: Tue, 14 Jan 2025 10:14:10 -0500 +Subject: [PATCH] target/arm: support vm live migration between phytium and + kp920 + +Support for migration between phytium and kp920 +when using phytium-v cpu model. +Support for migration from low to high versions +when using host-passthrough mode. + +Signed-off-by: Peng Mengguang +--- + hw/intc/arm_gicv3_common.c | 5 +++ + hw/intc/arm_gicv3_kvm.c | 8 +++++ + include/hw/intc/arm_gicv3_common.h | 1 + + target/arm/kvm.c | 53 +++++++++++++++++++++++++++++- + 4 files changed, 66 insertions(+), 1 deletion(-) + +diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c +index 2ebf880ead..8b9c4b2f1f 100644 +--- a/hw/intc/arm_gicv3_common.c ++++ b/hw/intc/arm_gicv3_common.c +@@ -88,6 +88,11 @@ static int gicv3_post_load(void *opaque, int version_id) + gicv3_gicd_no_migration_shift_bug_post_load(s); + + if (c->post_load) { ++ /* load origin value of reg icc_ctrl_el1 when migrate vm */ ++ for (int ncpu = 0; ncpu < s->num_cpu; ncpu++) { ++ GICv3CPUState *cs = &s->cpu[ncpu]; ++ cs->icc_ctlr_el1[GICV3_NS] = cs->icc_ctlr_el1_origin[GICV3_NS]; ++ } + c->post_load(s); + } + return 0; +diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c +index 77eb37e131..367589141c 100644 +--- a/hw/intc/arm_gicv3_kvm.c ++++ b/hw/intc/arm_gicv3_kvm.c +@@ -700,6 +700,8 @@ static void arm_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri) + KVM_VGIC_ATTR(ICC_CTLR_EL1, c->gicr_typer), + &c->icc_ctlr_el1[GICV3_NS], false, &error_abort); + ++ /* save origin value of reg icc_ctrl_el1 for vm migration to use */ ++ c->icc_ctlr_el1_origin[GICV3_S] = c->icc_ctlr_el1[GICV3_NS]; + c->icc_ctlr_el1[GICV3_S] = c->icc_ctlr_el1[GICV3_NS]; + } + +@@ -720,6 +722,12 @@ static void kvm_arm_gicv3_reset_hold(Object *obj) + } + + kvm_arm_gicv3_put(s); ++ ++ /* save origin value of reg icc_ctrl_el1 */ ++ for (int ncpu = 0; ncpu < s->num_cpu; ncpu++) { ++ GICv3CPUState *c = &s->cpu[ncpu]; ++ c->icc_ctlr_el1_origin[GICV3_NS] = c->icc_ctlr_el1[GICV3_NS]; ++ } + } + + /* +diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h +index 4e2fb518e7..a9b6d7f7b0 100644 +--- a/include/hw/intc/arm_gicv3_common.h ++++ b/include/hw/intc/arm_gicv3_common.h +@@ -181,6 +181,7 @@ struct GICv3CPUState { + /* CPU interface */ + uint64_t icc_sre_el1; + uint64_t icc_ctlr_el1[2]; ++ uint64_t icc_ctlr_el1_origin[2]; + uint64_t icc_pmr_el1; + uint64_t icc_bpr[3]; + uint64_t icc_apr[3][4]; +diff --git a/target/arm/kvm.c b/target/arm/kvm.c +index a42ddcc855..fb0ced115f 100644 +--- a/target/arm/kvm.c ++++ b/target/arm/kvm.c +@@ -32,6 +32,7 @@ + #include "hw/irq.h" + #include "qapi/visitor.h" + #include "qemu/log.h" ++#include "qemu/aarch64-cpuid.h" + + const KVMCapabilityInfo kvm_arch_required_capabilities[] = { + KVM_CAP_LAST_INFO +@@ -469,6 +470,56 @@ static uint64_t *kvm_arm_get_cpreg_ptr(ARMCPU *cpu, uint64_t regidx) + return &cpu->cpreg_values[res - cpu->cpreg_indexes]; + } + ++/* PHYTIUM: check compatibility for live migration. */ ++static bool check_compatibility_for_phytium(ARMCPU *cpu) ++{ ++ Object *obj = OBJECT(cpu); ++ ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); ++ ++ int i; ++ bool ret = true; ++ uint8_t src_impl = 0; ++ uint16_t src_partnum = 0; ++ uint64_t src_midr = 0; ++ ++ if (NULL != acc->info && 0 == strcmp(acc->info->name, "phytium-v")) ++ ret = true; ++ else { ++ for (i = 0; i < cpu->cpreg_array_len; i++) { ++ uint64_t regidx = cpu->cpreg_indexes[i]; ++ if (regidx == ARM64_SYS_REG(3, 0, 0, 0, 0)) { ++ src_midr = cpu->cpreg_values[i]; ++ src_impl = (src_midr >> 24) & 0xff; ++ src_partnum = (src_midr >> 4) & 0x0fff; ++ break; ++ } ++ } ++ ++ if (src_impl == ARM_CPU_IMP_PHYTIUM) { ++ if (is_phytium_cpu()) { ++ if (qemu_read_cpuid_part_number() >= src_partnum) { ++ ret = true; ++ } else { ++ ret = false; ++ } ++ } else if (qemu_read_cpuid_implementor() == 0x48) { ++ if (src_partnum == PHYTIUM_CPU_PART_FTC662 ++ || src_partnum == PHYTIUM_CPU_PART_FTC663) { ++ ret = true; ++ } else { ++ ret = false; ++ } ++ } else { ++ ret = false; ++ } ++ } else { ++ ret = false; ++ } ++ } ++ ++ return ret; ++} ++ + /* Initialize the ARMCPU cpreg list according to the kernel's + * definition of what CPU registers it knows about (and throw away + * the previous TCG-created cpreg list). +@@ -612,7 +663,7 @@ bool write_list_to_kvmstate(ARMCPU *cpu, int level) + * "you tried to set a register which is constant with + * a different value from what it actually contains". + */ +- ok = false; ++ ok = check_compatibility_for_phytium(cpu); + } + } + return ok; +-- +2.43.0 + diff --git a/0359-cpu-add-tengyun-s5000c-cpu-support.patch b/0359-cpu-add-tengyun-s5000c-cpu-support.patch new file mode 100644 index 0000000000000000000000000000000000000000..f74d6622c8cd9e8684a69c3b9ab5b4950db2dfee --- /dev/null +++ b/0359-cpu-add-tengyun-s5000c-cpu-support.patch @@ -0,0 +1,62 @@ +From aba69912bf0a2eb0fa99a8e6bf6773c235159384 Mon Sep 17 00:00:00 2001 +From: wangzhimin +Date: Tue, 15 Apr 2025 11:13:52 +0800 +Subject: [PATCH] cpu: add Tengyun-S5000C cpu support + +Add the Tengyun-S5000C CPU model. + +Signed-off-by: Peng Mengguang +Signed-off-by: Wang Zhimin +--- + hw/arm/virt.c | 1 + + target/arm/cpu64.c | 17 +++++++++++++++++ + 2 files changed, 18 insertions(+) + +diff --git a/hw/arm/virt.c b/hw/arm/virt.c +index eaf29f5c94..9b9fe821d5 100644 +--- a/hw/arm/virt.c ++++ b/hw/arm/virt.c +@@ -220,6 +220,7 @@ static const char *valid_cpus[] = { + #endif + ARM_CPU_TYPE_NAME("cortex-a53"), + ARM_CPU_TYPE_NAME("cortex-a57"), ++ ARM_CPU_TYPE_NAME("Tengyun-S5000C"), + ARM_CPU_TYPE_NAME("host"), + ARM_CPU_TYPE_NAME("max"), + ARM_CPU_TYPE_NAME("phytium-v"), +diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c +index b4326ce8ba..71c11ae49e 100644 +--- a/target/arm/cpu64.c ++++ b/target/arm/cpu64.c +@@ -753,11 +753,28 @@ static void aarch64_phytium_v_initfn(Object *obj) + } + } + ++static void aarch64_tengyun_s5000c_initfn(Object *obj) ++{ ++ ARMCPU *cpu = ARM_CPU(obj); ++ ++ if (kvm_enabled()) { ++ kvm_arm_set_cpu_features_from_host(cpu); ++ } else { ++ aarch64_a53_initfn(obj); ++ cpu->midr = 0x700f8620; ++ } ++ if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { ++ aarch64_add_sve_properties(obj); ++ aarch64_add_pauth_properties(obj); ++ } ++} ++ + static const ARMCPUInfo aarch64_cpus[] = { + { .name = "cortex-a57", .initfn = aarch64_a57_initfn }, + { .name = "cortex-a53", .initfn = aarch64_a53_initfn }, + { .name = "max", .initfn = aarch64_max_initfn }, + { .name = "phytium-v", .initfn = aarch64_phytium_v_initfn }, ++ { .name = "Tengyun-S5000C", .initfn = aarch64_tengyun_s5000c_initfn }, + #if defined(CONFIG_KVM) || defined(CONFIG_HVF) + { .name = "host", .initfn = aarch64_host_initfn }, + #endif +-- +2.43.0 + diff --git a/0360-sync-header-file-from-upstream.patch b/0360-sync-header-file-from-upstream.patch new file mode 100644 index 0000000000000000000000000000000000000000..2c154506d250123b9c0d5fc13f56642b0de66d89 --- /dev/null +++ b/0360-sync-header-file-from-upstream.patch @@ -0,0 +1,138 @@ +From f4c27a80b5fb0a9a004397b64347adc92378e3f7 Mon Sep 17 00:00:00 2001 +From: Xianglai Li +Date: Mon, 26 May 2025 16:58:25 +0800 +Subject: [PATCH] sync header file from upstream + +The local interrupt controller simulation header file is inconsistent +with the upstream header file. To ensure uapi compatibility, +the upstream interrupt controller simulation header file is now +synchronized. + +Signed-off-by: Xianglai Li +--- + hw/intc/loongarch_extioi_kvm.c | 2 +- + hw/intc/loongarch_ipi_kvm.c | 2 +- + hw/intc/loongarch_pch_pic_kvm.c | 2 +- + linux-headers/asm-loongarch/kvm.h | 15 ++++++--------- + linux-headers/linux/kvm.h | 13 +++++++------ + target/loongarch/kvm/kvm.c | 4 ---- + 6 files changed, 16 insertions(+), 22 deletions(-) + +diff --git a/hw/intc/loongarch_extioi_kvm.c b/hw/intc/loongarch_extioi_kvm.c +index e7699ad2ea..a7ee0a8ad7 100644 +--- a/hw/intc/loongarch_extioi_kvm.c ++++ b/hw/intc/loongarch_extioi_kvm.c +@@ -115,7 +115,7 @@ static void kvm_loongarch_extioi_realize(DeviceState *dev, Error **errp) + } + + if (!extioi_class->is_created) { +- cd.type = KVM_DEV_TYPE_LA_EXTIOI; ++ cd.type = KVM_DEV_TYPE_LOONGARCH_EIOINTC; + ret = kvm_vm_ioctl(kvm_state, KVM_CREATE_DEVICE, &cd); + if (ret < 0) { + error_setg_errno(errp, errno, +diff --git a/hw/intc/loongarch_ipi_kvm.c b/hw/intc/loongarch_ipi_kvm.c +index fd308eb0c0..57fc05db77 100644 +--- a/hw/intc/loongarch_ipi_kvm.c ++++ b/hw/intc/loongarch_ipi_kvm.c +@@ -128,7 +128,7 @@ static void kvm_loongarch_ipi_realize(DeviceState *dev, Error **errp) + } + + if (!ipi_class->is_created) { +- cd.type = KVM_DEV_TYPE_LA_IPI; ++ cd.type = KVM_DEV_TYPE_LOONGARCH_IPI; + ret = kvm_vm_ioctl(kvm_state, KVM_CREATE_DEVICE, &cd); + if (ret < 0) { + error_setg_errno(errp, errno, "Creating the KVM device failed"); +diff --git a/hw/intc/loongarch_pch_pic_kvm.c b/hw/intc/loongarch_pch_pic_kvm.c +index 8f66d9a01f..e9cef02f9a 100644 +--- a/hw/intc/loongarch_pch_pic_kvm.c ++++ b/hw/intc/loongarch_pch_pic_kvm.c +@@ -113,7 +113,7 @@ static void kvm_loongarch_pch_pic_realize(DeviceState *dev, Error **errp) + } + + if (!pch_pic_class->is_created) { +- cd.type = KVM_DEV_TYPE_LA_PCH_PIC; ++ cd.type = KVM_DEV_TYPE_LOONGARCH_PCHPIC; + ret = kvm_vm_ioctl(kvm_state, KVM_CREATE_DEVICE, &cd); + if (ret < 0) { + error_setg_errno(errp, errno, +diff --git a/linux-headers/asm-loongarch/kvm.h b/linux-headers/asm-loongarch/kvm.h +index 92c32b7ec9..bc37a986f2 100644 +--- a/linux-headers/asm-loongarch/kvm.h ++++ b/linux-headers/asm-loongarch/kvm.h +@@ -134,26 +134,23 @@ struct kvm_iocsr_entry { + #define KVM_IRQCHIP_NUM_PINS 64 + #define KVM_MAX_CORES 256 + +-#define KVM_LOONGARCH_VM_HAVE_IRQCHIP 0x40000001 ++#define KVM_DEV_LOONGARCH_IPI_GRP_REGS 0x40000001 + +-#define KVM_DEV_LOONGARCH_IPI_GRP_REGS 0x40000002 ++#define KVM_DEV_LOONGARCH_EXTIOI_GRP_REGS 0x40000002 + +-#define KVM_DEV_LOONGARCH_EXTIOI_GRP_REGS 0x40000003 +- +-#define KVM_DEV_LOONGARCH_EXTIOI_GRP_SW_STATUS 0x40000006 ++#define KVM_DEV_LOONGARCH_EXTIOI_GRP_SW_STATUS 0x40000003 + #define KVM_DEV_LOONGARCH_EXTIOI_SW_STATUS_NUM_CPU 0x0 + #define KVM_DEV_LOONGARCH_EXTIOI_SW_STATUS_FEATURE 0x1 + #define KVM_DEV_LOONGARCH_EXTIOI_SW_STATUS_STATE 0x2 + +-#define KVM_DEV_LOONGARCH_EXTIOI_GRP_CTRL 0x40000007 ++#define KVM_DEV_LOONGARCH_EXTIOI_GRP_CTRL 0x40000004 + #define KVM_DEV_LOONGARCH_EXTIOI_CTRL_INIT_NUM_CPU 0x0 + #define KVM_DEV_LOONGARCH_EXTIOI_CTRL_INIT_FEATURE 0x1 + #define KVM_DEV_LOONGARCH_EXTIOI_CTRL_LOAD_FINISHED 0x3 + + +-#define KVM_DEV_LOONGARCH_PCH_PIC_GRP_CTRL 0x40000004 +-#define KVM_DEV_LOONGARCH_PCH_PIC_CTRL_INIT 0 +- + #define KVM_DEV_LOONGARCH_PCH_PIC_GRP_REGS 0x40000005 ++#define KVM_DEV_LOONGARCH_PCH_PIC_GRP_CTRL 0x40000006 ++#define KVM_DEV_LOONGARCH_PCH_PIC_CTRL_INIT 0 + + #endif /* __UAPI_ASM_LOONGARCH_KVM_H */ +diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h +index d2f6007fb8..656b6163e6 100644 +--- a/linux-headers/linux/kvm.h ++++ b/linux-headers/linux/kvm.h +@@ -1154,12 +1154,13 @@ enum kvm_device_type { + #define KVM_DEV_TYPE_ARM_PV_TIME KVM_DEV_TYPE_ARM_PV_TIME + KVM_DEV_TYPE_RISCV_AIA, + #define KVM_DEV_TYPE_RISCV_AIA KVM_DEV_TYPE_RISCV_AIA +- KVM_DEV_TYPE_LA_PCH_PIC = 0x100, +-#define KVM_DEV_TYPE_LA_PCH_PIC KVM_DEV_TYPE_LA_PCH_PIC +- KVM_DEV_TYPE_LA_IPI, +-#define KVM_DEV_TYPE_LA_IPI KVM_DEV_TYPE_LA_IPI +- KVM_DEV_TYPE_LA_EXTIOI, +-#define KVM_DEV_TYPE_LA_EXTIOI KVM_DEV_TYPE_LA_EXTIOI ++ KVM_DEV_TYPE_LOONGARCH_IPI, ++#define KVM_DEV_TYPE_LOONGARCH_IPI KVM_DEV_TYPE_LOONGARCH_IPI ++ KVM_DEV_TYPE_LOONGARCH_EIOINTC, ++#define KVM_DEV_TYPE_LOONGARCH_EIOINTC KVM_DEV_TYPE_LOONGARCH_EIOINTC ++ KVM_DEV_TYPE_LOONGARCH_PCHPIC, ++#define KVM_DEV_TYPE_LOONGARCH_PCHPIC KVM_DEV_TYPE_LOONGARCH_PCHPIC ++ + KVM_DEV_TYPE_MAX, + }; + +diff --git a/target/loongarch/kvm/kvm.c b/target/loongarch/kvm/kvm.c +index 22177b6220..f42b92d7c8 100644 +--- a/target/loongarch/kvm/kvm.c ++++ b/target/loongarch/kvm/kvm.c +@@ -973,10 +973,6 @@ int kvm_arch_get_default_type(MachineState *ms) + int kvm_arch_init(MachineState *ms, KVMState *s) + { + cap_has_mp_state = kvm_check_extension(s, KVM_CAP_MP_STATE); +- if(!kvm_vm_check_attr(kvm_state, KVM_LOONGARCH_VM_HAVE_IRQCHIP, KVM_LOONGARCH_VM_HAVE_IRQCHIP)) { +- s->kernel_irqchip_allowed = false; +- } +- + return 0; + } + +-- +2.43.0 + diff --git a/0361-target-i386-add-new-hygon-chengdu-cpu-model.patch b/0361-target-i386-add-new-hygon-chengdu-cpu-model.patch new file mode 100644 index 0000000000000000000000000000000000000000..ee883623ae6a1543d5e23106f2b519ffb09c996a --- /dev/null +++ b/0361-target-i386-add-new-hygon-chengdu-cpu-model.patch @@ -0,0 +1,89 @@ +From 28d03f930c3cfa0b10c4baa027a271af3ae3de24 Mon Sep 17 00:00:00 2001 +From: Yanjing Zhou +Date: Tue, 27 May 2025 15:00:20 +0800 +Subject: [PATCH] target/i386: Add new Hygon 'Chengdu' CPU model + +Add the following feature bits compare to Dhyana CPU model: +avx512f, avx512dq, avx512ifma, clwb, avx512cd, avx512bw, gfni, +avx512vl, avx512_bf16, wbnoinvd, avx512vbmi, avx512_vbmi2, +vaes, vpclmulqdq, avx512_vnni, avx512_bitalg,avx512_vpopcntdq + +Signed-off-by: Yanjing Zhou +--- + target/i386/cpu.c | 60 +++++++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 60 insertions(+) + +diff --git a/target/i386/cpu.c b/target/i386/cpu.c +index 6dbca44be1..efe8bf0948 100644 +--- a/target/i386/cpu.c ++++ b/target/i386/cpu.c +@@ -5324,6 +5324,66 @@ static const X86CPUDefinition builtin_x86_defs[] = { + .model_id = "Hygon Dharma Processor", + .cache_info = &dharma_cache_info, + }, ++ { ++ .name = "Chengdu", ++ .level = 0xd, ++ .vendor = CPUID_VENDOR_HYGON, ++ .family = 24, ++ .model = 7, ++ .stepping = 0, ++ .features[FEAT_1_EDX] = ++ CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | ++ CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | ++ CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | ++ CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | ++ CPUID_VME | CPUID_FP87, ++ .features[FEAT_1_ECX] = ++ CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | ++ CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | ++ CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | ++ CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | ++ CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, ++ .features[FEAT_8000_0001_EDX] = ++ CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | ++ CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | ++ CPUID_EXT2_SYSCALL, ++ .features[FEAT_8000_0001_ECX] = ++ CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | ++ CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | ++ CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | ++ CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, ++ .features[FEAT_8000_0008_EBX] = ++ CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | ++ CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | ++ CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | ++ CPUID_8000_0008_EBX_AMD_SSBD, ++ .features[FEAT_7_0_EBX] = ++ CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | ++ CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_AVX512F | ++ CPUID_7_0_EBX_AVX512DQ | CPUID_7_0_EBX_RDSEED | ++ CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_AVX512IFMA | ++ CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | ++ CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | ++ CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, ++ .features[FEAT_7_0_ECX] = ++ CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | ++ CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | ++ CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | ++ CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | ++ CPUID_7_0_ECX_AVX512_VPOPCNTDQ, ++ .features[FEAT_7_1_EAX] = ++ CPUID_7_1_EAX_AVX512_BF16, ++ .features[FEAT_XSAVE] = ++ CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | ++ CPUID_XSAVE_XGETBV1, ++ .features[FEAT_6_EAX] = ++ CPUID_6_EAX_ARAT, ++ .features[FEAT_SVM] = ++ CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, ++ .xlevel = 0x80000020, ++ .model_id = "Hygon Chengdu Processor", ++ .cache_info = &dharma_cache_info, ++ }, + }; + + /* +-- +2.43.0 + diff --git a/qemu.spec b/qemu.spec index 91ffd0dfe45fb6dda9dec63350910ad570742288..1e31cb98f3004471f41a79f4d1ddd753e7d37b1d 100644 --- a/qemu.spec +++ b/qemu.spec @@ -1,4 +1,4 @@ -%define anolis_release 27 +%define anolis_release 28 %bcond_with check %global all_system_emu_support 0 @@ -632,6 +632,18 @@ Patch0346: 0346-target-arm-support-vm-live-migration-between-phytium.patch Patch0347: 0347-cpu-add-tengyun-s5000c-cpu-support.patch Patch0348: 0348-sync-header-file-from-upstream.patch Patch0349: 0349-target-i386-add-new-hygon-chengdu-cpu-model.patch +Patch0350: 0350-cpus-stop-vm-in-suspended-runstate.patch +Patch0351: 0351-runstate-skip-initial-cpu-reset-if-reset-is-not-actu.patch +Patch0352: 0352-migration-prevent-migration-when-vm-has-poisoned-mem.patch +Patch0353: 0353-scripts-update-linux-header-sh-be-more-src-tree-frie.patch +Patch0354: 0354-scripts-update-linux-headers-sh-remove-temporary-dir.patch +Patch0355: 0355-scripts-update-linux-headers-sh-fix-the-path-of-setu.patch +Patch0356: 0356-util-add-interfaces-to-read-midr-on-aarch64.patch +Patch0357: 0357-cpu-add-phytium-v-cpu-support.patch +Patch0358: 0358-target-arm-support-vm-live-migration-between-phytium.patch +Patch0359: 0359-cpu-add-tengyun-s5000c-cpu-support.patch +Patch0360: 0360-sync-header-file-from-upstream.patch +Patch0361: 0361-target-i386-add-new-hygon-chengdu-cpu-model.patch ExclusiveArch: x86_64 aarch64 loongarch64 @@ -2193,6 +2205,9 @@ useradd -r -u 107 -g qemu -G kvm -d / -s /sbin/nologin \ %endif %changelog +* Mon Jun 09 2025 wh02252983 - 2:8.2.0-28 +- Auto-generated patch updates + * Fri May 30 2025 wh02252983 - 2:8.2.0-27 - target/i386: Add new Hygon 'Chengdu' CPU model