diff --git a/valgrind-3.21.0-Add-SW64-Linux-support.patch b/valgrind-3.21.0-Add-SW64-Linux-support.patch new file mode 100644 index 0000000000000000000000000000000000000000..93fd41a148accd272ff964a64495619703bd01d5 --- /dev/null +++ b/valgrind-3.21.0-Add-SW64-Linux-support.patch @@ -0,0 +1,222080 @@ +From e8a479bb0919be06a3d8fe6c22fcea8b8e8670cd Mon Sep 17 00:00:00 2001 +From: zlh +Date: Tue, 11 Feb 2025 09:55:32 +0000 +Subject: [PATCH] Add SW64 Linux support + +--- + Makefile.all.am | 7 + + Makefile.tool.am | 11 + + Makefile.vex.am | 12 +- + VEX/auxprogs/genoffsets.c | 40 +- + VEX/priv/guest_generic_bb_to_IR.c | 2 +- + VEX/priv/guest_sw64_defs.h | 81 + + VEX/priv/guest_sw64_helpers.c | 312 + + VEX/priv/guest_sw64_toIR.c | 3496 ++ + VEX/priv/host_amd64_defs.c | 2 +- + VEX/priv/host_amd64_defs.h | 2 +- + VEX/priv/host_arm64_defs.c | 2 +- + VEX/priv/host_arm64_defs.h | 2 +- + VEX/priv/host_arm_defs.c | 2 +- + VEX/priv/host_arm_defs.h | 2 +- + VEX/priv/host_mips_defs.c | 2 +- + VEX/priv/host_mips_defs.h | 2 +- + VEX/priv/host_nanomips_defs.c | 2 +- + VEX/priv/host_nanomips_defs.h | 2 +- + VEX/priv/host_ppc_defs.c | 2 +- + VEX/priv/host_ppc_defs.h | 2 +- + VEX/priv/host_s390_defs.c | 3 +- + VEX/priv/host_s390_defs.h | 4 +- + VEX/priv/host_sw64_defs.c | 3169 ++ + VEX/priv/host_sw64_defs.h | 687 + + VEX/priv/host_sw64_isel.c | 2591 ++ + VEX/priv/host_x86_defs.c | 2 +- + VEX/priv/host_x86_defs.h | 2 +- + VEX/priv/ir_defs.c | 16 + + VEX/priv/ir_opt.c | 26 + + VEX/priv/main_main.c | 138 +- + VEX/pub/libvex.h | 18 + + VEX/pub/libvex_basictypes.h | 4 + + VEX/pub/libvex_guest_sw64.h | 163 + + VEX/pub/libvex_ir.h | 10 + + cachegrind/cg_arch.c | 6 + + cachegrind/cg_branchpred.c | 3 +- + cachegrind/tests/cgout-test2 | 3543 ++ + configure.ac | 47 +- + coregrind/Makefile.am | 6 + + coregrind/launcher-linux.c | 5 +- + coregrind/m_aspacemgr/aspacemgr-common.c | 3 +- + coregrind/m_aspacemgr/aspacemgr-linux.c | 1 + + coregrind/m_cache.c | 3 +- + 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+ create mode 100644 none/tests/sw64/8a-misc.stdout.exp + create mode 100644 none/tests/sw64/8a-misc.vgtest + create mode 100644 none/tests/sw64/Makefile + create mode 100644 none/tests/sw64/Makefile.am + create mode 100644 none/tests/sw64/Makefile.in + create mode 100755 none/tests/sw64/allexec + create mode 120000 none/tests/sw64/allexec.c + create mode 100755 none/tests/sw64/arith-fp + create mode 100644 none/tests/sw64/arith-fp.c + create mode 100644 none/tests/sw64/arith-fp.stderr.exp + create mode 100644 none/tests/sw64/arith-fp.stdout.exp + create mode 100644 none/tests/sw64/arith-fp.stdout.exp-8a + create mode 100644 none/tests/sw64/arith-fp.vgtest + create mode 100755 none/tests/sw64/arith-int-imm + create mode 100644 none/tests/sw64/arith-int-imm.c + create mode 100644 none/tests/sw64/arith-int-imm.stderr.exp + create mode 100644 none/tests/sw64/arith-int-imm.stdout.exp + create mode 100644 none/tests/sw64/arith-int-imm.vgtest + create mode 100755 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none/tests/sw64/rounding + create mode 100644 none/tests/sw64/rounding.c + create mode 100644 none/tests/sw64/rounding.stderr.exp + create mode 100644 none/tests/sw64/rounding.stdout.exp + create mode 100644 none/tests/sw64/rounding.vgtest + create mode 100755 none/tests/sw64/rtc + create mode 100644 none/tests/sw64/rtc.c + create mode 100644 none/tests/sw64/rtc.stderr.exp + create mode 100644 none/tests/sw64/rtc.vgtest + create mode 100755 none/tests/sw64/simd-fp + create mode 100644 none/tests/sw64/simd-fp.c + create mode 100644 none/tests/sw64/simd-fp.stderr.exp + create mode 100644 none/tests/sw64/simd-fp.stdout.exp + create mode 100644 none/tests/sw64/simd-fp.vgtest.disable + create mode 100755 none/tests/sw64/simd-int + create mode 100644 none/tests/sw64/simd-int.c + create mode 100644 none/tests/sw64/simd-int.stderr.exp + create mode 100644 none/tests/sw64/simd-int.stdout.exp + create mode 100644 none/tests/sw64/simd-int.vgtest.disable + create mode 100755 none/tests/sw64/stack + create mode 100644 none/tests/sw64/stack.c + create mode 100644 none/tests/sw64/stack.stderr.exp + create mode 100644 none/tests/sw64/stack.stdout.exp + create mode 100644 none/tests/sw64/stack.vgtest + create mode 100755 none/tests/sw64/unique + create mode 100644 none/tests/sw64/unique.c + create mode 100644 none/tests/sw64/unique.stderr.exp + create mode 100644 none/tests/sw64/unique.stdout.exp + create mode 100644 none/tests/sw64/unique.vgtest + +diff --git a/Makefile.all.am b/Makefile.all.am +index 1de1f13a7..88a0b1c49 100755 +--- a/Makefile.all.am ++++ b/Makefile.all.am +@@ -290,6 +290,12 @@ AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ + $(AM_CFLAGS_PSO_BASE) + AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g + ++AM_FLAG_M3264_SW64_LINUX = @FLAG_M64@ ++AM_CFLAGS_SW64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) ++AM_CFLAGS_PSO_SW64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ ++ $(AM_CFLAGS_PSO_BASE) ++AM_CCASFLAGS_SW64_LINUX = @FLAG_M64@ -g ++ + AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ + AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ + $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ +@@ -350,6 +356,7 @@ PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ + PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ + PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ + PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ ++PRELOAD_LDFLAGS_SW64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ + PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ + PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ + +diff --git a/Makefile.tool.am b/Makefile.tool.am +index df9502913..ce22127ff 100644 +--- a/Makefile.tool.am ++++ b/Makefile.tool.am +@@ -80,6 +80,9 @@ TOOL_LDFLAGS_ARM64_LINUX = \ + TOOL_LDFLAGS_S390X_LINUX = \ + $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@ + ++TOOL_LDFLAGS_SW64_LINUX = \ ++ $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@ ++ + TOOL_LDFLAGS_X86_DARWIN = \ + $(TOOL_LDFLAGS_COMMON_DARWIN) -arch i386 + +@@ -167,6 +170,9 @@ LIBREPLACEMALLOC_MIPS32_LINUX = \ + LIBREPLACEMALLOC_MIPS64_LINUX = \ + $(top_builddir)/coregrind/libreplacemalloc_toolpreload-mips64-linux.a + ++LIBREPLACEMALLOC_SW64_LINUX = \ ++ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-sw64-linux.a ++ + LIBREPLACEMALLOC_X86_SOLARIS = \ + $(top_builddir)/coregrind/libreplacemalloc_toolpreload-x86-solaris.a + +@@ -239,6 +245,11 @@ LIBREPLACEMALLOC_LDFLAGS_MIPS64_LINUX = \ + $(LIBREPLACEMALLOC_MIPS64_LINUX) \ + -Wl,--no-whole-archive + ++LIBREPLACEMALLOC_LDFLAGS_SW64_LINUX = \ ++ -Wl,--whole-archive \ ++ $(LIBREPLACEMALLOC_SW64_LINUX) \ ++ -Wl,--no-whole-archive ++ + LIBREPLACEMALLOC_LDFLAGS_X86_SOLARIS = \ + -Wl,--whole-archive \ + $(LIBREPLACEMALLOC_X86_SOLARIS) \ +diff --git a/Makefile.vex.am b/Makefile.vex.am +index 98d848359..0cc863833 100644 +--- a/Makefile.vex.am ++++ b/Makefile.vex.am +@@ -26,6 +26,7 @@ pkginclude_HEADERS = \ + pub/libvex_guest_s390x.h \ + pub/libvex_guest_mips32.h \ + pub/libvex_guest_mips64.h \ ++ pub/libvex_guest_sw64.h \ + pub/libvex_s390x_common.h \ + pub/libvex_ir.h \ + pub/libvex_trc_values.h \ +@@ -47,6 +48,7 @@ noinst_HEADERS = \ + priv/guest_arm64_defs.h \ + priv/guest_s390_defs.h \ + priv/guest_mips_defs.h \ ++ priv/guest_sw64_defs.h \ + priv/mips_defs.h \ + priv/guest_nanomips_defs.h \ + priv/host_generic_regs.h \ +@@ -60,6 +62,7 @@ noinst_HEADERS = \ + priv/host_arm_defs.h \ + priv/host_arm64_defs.h \ + priv/host_s390_defs.h \ ++ priv/host_sw64_defs.h \ + priv/s390_disasm.h \ + priv/s390_defs.h \ + priv/host_mips_defs.h \ +@@ -93,7 +96,8 @@ pub/libvex_guest_offsets.h: auxprogs/genoffsets.c \ + pub/libvex_guest_arm64.h \ + pub/libvex_guest_s390x.h \ + pub/libvex_guest_mips32.h \ +- pub/libvex_guest_mips64.h ++ pub/libvex_guest_mips64.h \ ++ pub/libvex_guest_sw64.h + rm -f auxprogs/genoffsets.s + $(mkdir_p) auxprogs pub + $(CC) $(CFLAGS_FOR_GENOFFSETS) \ +@@ -151,6 +155,8 @@ LIBVEX_SOURCES_COMMON = \ + priv/guest_mips_toIR.c \ + priv/guest_nanomips_helpers.c \ + priv/guest_nanomips_toIR.c \ ++ priv/guest_sw64_helpers.c \ ++ priv/guest_sw64_toIR.c \ + priv/host_generic_regs.c \ + priv/host_generic_simd64.c \ + priv/host_generic_simd128.c \ +@@ -174,7 +180,9 @@ LIBVEX_SOURCES_COMMON = \ + priv/host_mips_defs.c \ + priv/host_nanomips_defs.c \ + priv/host_mips_isel.c \ +- priv/host_nanomips_isel.c ++ priv/host_nanomips_isel.c \ ++ priv/host_sw64_isel.c \ ++ priv/host_sw64_defs.c + + LIBVEXMULTIARCH_SOURCES = priv/multiarch_main_main.c + +diff --git a/VEX/auxprogs/genoffsets.c b/VEX/auxprogs/genoffsets.c +index 54376dc90..ff595ffba 100644 +--- a/VEX/auxprogs/genoffsets.c ++++ b/VEX/auxprogs/genoffsets.c +@@ -53,6 +53,7 @@ + #include "../pub/libvex_guest_s390x.h" + #include "../pub/libvex_guest_mips32.h" + #include "../pub/libvex_guest_mips64.h" ++#include "../pub/libvex_guest_sw64.h" + + #define VG_STRINGIFZ(__str) #__str + #define VG_STRINGIFY(__str) VG_STRINGIFZ(__str) +@@ -206,7 +207,7 @@ void foo ( void ) + GENOFFSET(MIPS32,mips32,r13); + GENOFFSET(MIPS32,mips32,r14); + GENOFFSET(MIPS32,mips32,r15); +- GENOFFSET(MIPS32,mips32,r15); ++ GENOFFSET(MIPS32,mips32,r16); + GENOFFSET(MIPS32,mips32,r17); + GENOFFSET(MIPS32,mips32,r18); + GENOFFSET(MIPS32,mips32,r19); +@@ -243,7 +244,7 @@ void foo ( void ) + GENOFFSET(MIPS64,mips64,r13); + GENOFFSET(MIPS64,mips64,r14); + GENOFFSET(MIPS64,mips64,r15); +- GENOFFSET(MIPS64,mips64,r15); ++ GENOFFSET(MIPS64,mips64,r16); + GENOFFSET(MIPS64,mips64,r17); + GENOFFSET(MIPS64,mips64,r18); + GENOFFSET(MIPS64,mips64,r19); +@@ -262,6 +263,41 @@ void foo ( void ) + GENOFFSET(MIPS64,mips64,PC); + GENOFFSET(MIPS64,mips64,HI); + GENOFFSET(MIPS64,mips64,LO); ++ ++ //sw64 ++ GENOFFSET(SW64,sw64,r0); ++ GENOFFSET(SW64,sw64,r1); ++ GENOFFSET(SW64,sw64,r2); ++ GENOFFSET(SW64,sw64,r3); ++ GENOFFSET(SW64,sw64,r4); ++ GENOFFSET(SW64,sw64,r5); ++ GENOFFSET(SW64,sw64,r6); ++ GENOFFSET(SW64,sw64,r7); ++ GENOFFSET(SW64,sw64,r8); ++ GENOFFSET(SW64,sw64,r9); ++ GENOFFSET(SW64,sw64,r10); ++ GENOFFSET(SW64,sw64,r11); ++ GENOFFSET(SW64,sw64,r12); ++ GENOFFSET(SW64,sw64,r13); ++ GENOFFSET(SW64,sw64,r14); ++ GENOFFSET(SW64,sw64,r15); ++ GENOFFSET(SW64,sw64,r16); ++ GENOFFSET(SW64,sw64,r17); ++ GENOFFSET(SW64,sw64,r18); ++ GENOFFSET(SW64,sw64,r19); ++ GENOFFSET(SW64,sw64,r20); ++ GENOFFSET(SW64,sw64,r21); ++ GENOFFSET(SW64,sw64,r22); ++ GENOFFSET(SW64,sw64,r23); ++ GENOFFSET(SW64,sw64,r24); ++ GENOFFSET(SW64,sw64,r25); ++ GENOFFSET(SW64,sw64,r26); ++ GENOFFSET(SW64,sw64,r27); ++ GENOFFSET(SW64,sw64,r28); ++ GENOFFSET(SW64,sw64,r29); ++ GENOFFSET(SW64,sw64,r30); ++ GENOFFSET(SW64,sw64,r31); ++ GENOFFSET(SW64,sw64,PC); + } + + /*--------------------------------------------------------------------*/ +diff --git a/VEX/priv/guest_generic_bb_to_IR.c b/VEX/priv/guest_generic_bb_to_IR.c +index 1e72ddacd..c0cd2fc21 100644 +--- a/VEX/priv/guest_generic_bb_to_IR.c ++++ b/VEX/priv/guest_generic_bb_to_IR.c +@@ -994,7 +994,7 @@ static IRSB* disassemble_basic_block_till_stop( + imark->Ist.IMark.len = dres.len; + + /* Print the resulting IR, if needed. */ +- if (vex_traceflags & VEX_TRACE_FE) { ++ if (vex_traceflags & VEX_TRACE_FE /* debug logger */) { + for (Int i = first_stmt_idx; i < irbb->stmts_used; i++) { + vex_printf(" "); + ppIRStmt(irbb->stmts[i]); +diff --git a/VEX/priv/guest_sw64_defs.h b/VEX/priv/guest_sw64_defs.h +new file mode 100644 +index 000000000..0fe137bb8 +--- /dev/null ++++ b/VEX/priv/guest_sw64_defs.h +@@ -0,0 +1,81 @@ ++/*---------------------------------------------------------------*/ ++/*--- begin guest_sw64_defs.h ---*/ ++/*---------------------------------------------------------------*/ ++/* ++ This file is part of Valgrind, a dynamic binary instrumentation ++ framework. ++ ++ Copyright (C) 2013-2017 OpenWorks ++ info@open-works.net ++ ++ This program is free software; you can redistribute it and/or ++ modify it under the terms of the GNU General Public License as ++ published by the Free Software Foundation; either version 2 of the ++ License, or (at your option) any later version. ++ ++ This program is distributed in the hope that it will be useful, but ++ WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with this program; if not, see . ++ ++ The GNU General Public License is contained in the file COPYING. ++*/ ++ ++#ifndef __VEX_GUEST_SW64_DEFS_H ++#define __VEX_GUEST_SW64_DEFS_H ++ ++#include "libvex_basictypes.h" ++#include "libvex_guest_sw64.h" // VexGuestSW64State ++#include "guest_generic_bb_to_IR.h" // DisResult ++ ++/*---------------------------------------------------------*/ ++/*--- sw64 to IR conversion ---*/ ++/*---------------------------------------------------------*/ ++ ++/* Convert one SW64 insn to IR. See the type DisOneInstrFn in ++ guest_generic_bb_to_IR.h. */ ++ ++/* SW_NOT_COMPLETE */ ++extern ++DisResult disInstr_SW64 ( IRSB* irbb, ++ const UChar* guest_code, ++ Long delta, ++ Addr guest_IP, ++ VexArch guest_arch, ++ const VexArchInfo* archinfo, ++ const VexAbiInfo* abiinfo, ++ VexEndness host_endness, ++ Bool sigill_diag ); ++ ++extern ++Bool guest_sw64_state_requires_precise_mem_exns (Int, Int, ++ VexRegisterUpdates ); ++ ++extern IRExpr *guest_sw64_spechelper ( const HChar * function_name, ++ IRExpr ** args, ++ IRStmt ** precedingStmts, ++ Int n_precedingStmts); ++ ++extern void sw64_dirtyhelper_write_lockflag(void* gs, ULong src); ++ ++extern ULong sw64_dirtyhelper_rtc(void* gs); ++extern ULong sw64_dirtyhelper_rcid(void* gs); ++extern ULong sw64_dirtyhelper_calc_crc32b ( ULong acc, ULong bits ); ++extern ULong sw64_dirtyhelper_calc_crc32h ( ULong acc, ULong bits ); ++extern ULong sw64_dirtyhelper_calc_crc32w ( ULong acc, ULong bits ); ++extern ULong sw64_dirtyhelper_calc_crc32l ( ULong acc, ULong bits ); ++extern ULong sw64_dirtyhelper_calc_crc32cb ( ULong acc, ULong bits ); ++extern ULong sw64_dirtyhelper_calc_crc32ch ( ULong acc, ULong bits ); ++extern ULong sw64_dirtyhelper_calc_crc32cw ( ULong acc, ULong bits ); ++extern ULong sw64_dirtyhelper_calc_crc32cl ( ULong acc, ULong bits ); ++ ++extern VexGuestLayout sw64Guest_layout; ++ ++#endif /* __VEX_GUEST_SW64_DEFS_H */ ++ ++/*---------------------------------------------------------------*/ ++/*--- end guest_sw64_defs.h ---*/ ++/*---------------------------------------------------------------*/ +diff --git a/VEX/priv/guest_sw64_helpers.c b/VEX/priv/guest_sw64_helpers.c +new file mode 100644 +index 000000000..5ae65e4f5 +--- /dev/null ++++ b/VEX/priv/guest_sw64_helpers.c +@@ -0,0 +1,312 @@ ++ ++/*---------------------------------------------------------------*/ ++/*--- begin guest_sw64_helpers.c ---*/ ++/*---------------------------------------------------------------*/ ++ ++/* ++ This file is part of Valgrind, a dynamic binary instrumentation ++ framework. ++ ++ Copyright (C) 2010-2017 RT-RK ++ ++ This program is free software; you can redistribute it and/or ++ modify it under the terms of the GNU General Public License as ++ published by the Free Software Foundation; either version 2 of the ++ License, or (at your option) any later version. ++ ++ This program is distributed in the hope that it will be useful, but ++ WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with this program; if not, see . ++ ++ The GNU General Public License is contained in the file COPYING. ++*/ ++ ++#include "libvex_basictypes.h" ++#include "libvex_guest_sw64.h" ++#include "libvex_ir.h" ++#include "libvex.h" ++ ++#include "main_util.h" ++#include "main_globals.h" ++#include "guest_generic_bb_to_IR.h" ++#include "guest_sw64_defs.h" ++ ++void LibVEX_GuestSW64_initialise ( /*OUT*/ VexGuestSW64State * vex_state ) ++{ ++ vex_state->guest_r0 = 0; /* Values for function returns */ ++ vex_state->guest_r1 = 0; /* Temporaries */ /* t0-t7 */ ++ vex_state->guest_r2 = 0; ++ vex_state->guest_r3 = 0; ++ vex_state->guest_r4 = 0; ++ vex_state->guest_r5 = 0; ++ vex_state->guest_r6 = 0; ++ vex_state->guest_r7 = 0; ++ vex_state->guest_r8 = 0; ++ vex_state->guest_r9 = 0; /* Saved temporaries */ /* s0-s5 */ ++ vex_state->guest_r10 = 0; ++ vex_state->guest_r11 = 0; ++ vex_state->guest_r12 = 0; ++ vex_state->guest_r13 = 0; ++ vex_state->guest_r14 = 0; ++ vex_state->guest_r15 = 0; /* Frame pointer */ ++ vex_state->guest_r16 = 0; /* Function arguments */ /* a0-a5 */ ++ vex_state->guest_r17 = 0; ++ vex_state->guest_r18 = 0; ++ vex_state->guest_r19 = 0; ++ vex_state->guest_r20 = 0; ++ vex_state->guest_r21 = 0; ++ vex_state->guest_r22 = 0; /* Temporaries */ /* t8-t11 */ ++ vex_state->guest_r23 = 0; ++ vex_state->guest_r24 = 0; ++ vex_state->guest_r25 = 0; ++ vex_state->guest_r26 = 0; /* Return address */ ++ vex_state->guest_r27 = 0; /* Procedure value */ ++ vex_state->guest_r28 = 0; /* Assembler temporary */ ++ vex_state->guest_r29 = 0; /* Global pointer */ ++ vex_state->guest_r30 = 0; /* Stack pointer */ ++ vex_state->guest_r31 = 0; /* Hardwired to 0. */ ++ vex_state->guest_PC = 0; /* Program counter */ ++ vex_state->guest_CSR = 0; ++ ++ /* FPU Registers */ ++ vex_state->guest_f0 = 0x7ff800007ff80000ULL; /* Floting point registers */ ++ vex_state->guest_f1 = 0x7ff800007ff80000ULL; ++ vex_state->guest_f2 = 0x7ff800007ff80000ULL; ++ vex_state->guest_f3 = 0x7ff800007ff80000ULL; ++ vex_state->guest_f4 = 0x7ff800007ff80000ULL; ++ vex_state->guest_f5 = 0x7ff800007ff80000ULL; ++ vex_state->guest_f6 = 0x7ff800007ff80000ULL; ++ vex_state->guest_f7 = 0x7ff800007ff80000ULL; ++ vex_state->guest_f8 = 0x7ff800007ff80000ULL; ++ vex_state->guest_f9 = 0x7ff800007ff80000ULL; ++ vex_state->guest_f10 = 0x7ff800007ff80000ULL; ++ vex_state->guest_f11 = 0x7ff800007ff80000ULL; ++ vex_state->guest_f12 = 0x7ff800007ff80000ULL; ++ vex_state->guest_f13 = 0x7ff800007ff80000ULL; ++ vex_state->guest_f14 = 0x7ff800007ff80000ULL; ++ vex_state->guest_f15 = 0x7ff800007ff80000ULL; ++ vex_state->guest_f16 = 0x7ff800007ff80000ULL; ++ vex_state->guest_f17 = 0x7ff800007ff80000ULL; ++ vex_state->guest_f18 = 0x7ff800007ff80000ULL; ++ vex_state->guest_f19 = 0x7ff800007ff80000ULL; ++ vex_state->guest_f20 = 0x7ff800007ff80000ULL; ++ vex_state->guest_f21 = 0x7ff800007ff80000ULL; ++ vex_state->guest_f22 = 0x7ff800007ff80000ULL; ++ vex_state->guest_f23 = 0x7ff800007ff80000ULL; ++ vex_state->guest_f24 = 0x7ff800007ff80000ULL; ++ vex_state->guest_f25 = 0x7ff800007ff80000ULL; ++ vex_state->guest_f26 = 0x7ff800007ff80000ULL; ++ vex_state->guest_f27 = 0x7ff800007ff80000ULL; ++ vex_state->guest_f28 = 0x7ff800007ff80000ULL; ++ vex_state->guest_f29 = 0x7ff800007ff80000ULL; ++ vex_state->guest_f30 = 0x7ff800007ff80000ULL; ++ vex_state->guest_f31 = 0x7ff800007ff80000ULL; ++ ++ vex_state->guest_FPCR = 0x680e000000000000ULL; /* FP control/status register */ ++ ++ /* Various pseudo-regs mandated by Vex or Valgrind. */ ++ /* Emulation notes */ ++ vex_state->guest_EMNOTE = 0; ++ ++ /* For clflush: record start and length of area to invalidate */ ++ vex_state->guest_CMSTART = 0; ++ vex_state->guest_CMLEN = 0; ++ vex_state->host_EvC_COUNTER = 0; ++ vex_state->host_EvC_FAILADDR = 0; ++ ++ /* Used to record the unredirected guest address at the start of ++ a translation whose start has been redirected. By reading ++ this pseudo-register shortly afterwards, the translation can ++ find out what the corresponding no-redirection address was. ++ Note, this is only set for wrap-style redirects, not for ++ replace-style ones. */ ++ vex_state->guest_NRADDR = 0; ++} ++ ++Bool guest_sw64_state_requires_precise_mem_exns ( ++ Int minoff, Int maxoff, VexRegisterUpdates pxControl ++ ) ++{ ++ Int sp_min = offsetof(VexGuestSW64State, guest_r30); ++ Int sp_max = sp_min + 8 - 1; ++ Int pc_min = offsetof(VexGuestSW64State, guest_PC); ++ Int pc_max = pc_min + 8 - 1; ++ ++ if ( maxoff < sp_min || minoff > sp_max ) { ++ /* no overlap with sp */ ++ if (pxControl == VexRegUpdSpAtMemAccess) ++ return False; /* We only need to check stack pointer. */ ++ } else { ++ return True; ++ } ++ ++ if ( maxoff < pc_min || minoff > pc_max ) { ++ /* no overlap with pc */ ++ } else { ++ return True; ++ } ++ ++ Int fp_min = offsetof(VexGuestSW64State, guest_r15); ++ Int fp_max = fp_min + 8 - 1; ++ ++ if ( maxoff < fp_min || minoff > fp_max ) { ++ /* no overlap with fp */ ++ } else { ++ return True; ++ } ++ ++ return False; ++} ++ ++IRExpr *guest_sw64_spechelper ( const HChar * function_name, IRExpr ** args, ++ IRStmt ** precedingStmts, ++ Int n_precedingStmts ) ++{ ++ return NULL; ++} ++ ++ ++#define ALWAYSDEFD64(field) \ ++ { offsetof(VexGuestSW64State, field), \ ++ (sizeof ((VexGuestSW64State*)0)->field) } ++VexGuestLayout sw64Guest_layout = { ++ /* Total size of the guest state, in bytes. */ ++ .total_sizeB = sizeof(VexGuestSW64State), ++ /* Describe the stack pointer. */ ++ .offset_SP = offsetof(VexGuestSW64State, guest_r30), ++ .sizeof_SP = 8, ++ /* Describe the frame pointer. */ ++ .offset_FP = offsetof(VexGuestSW64State, guest_r15), ++ .sizeof_FP = 8, ++ /* Describe the instruction pointer. */ ++ .offset_IP = offsetof(VexGuestSW64State, guest_PC), ++ .sizeof_IP = 8, ++ /* Describe any sections to be regarded by Memcheck as ++ 'always-defined'. */ ++ .n_alwaysDefd = 6, ++ /* ? :( */ ++ .alwaysDefd = { ++ /* 0 */ ALWAYSDEFD64 (guest_r31), ++ /* 1 */ ALWAYSDEFD64 (guest_f31), ++ /* 2 */ ALWAYSDEFD64 (guest_EMNOTE), ++ /* 3 */ ALWAYSDEFD64 (guest_CMSTART), ++ /* 4 */ ALWAYSDEFD64 (guest_CMLEN), ++ /* 5 */ ALWAYSDEFD64 (guest_NRADDR), ++ } ++}; ++#undef ALWAYSDEFD64 ++ ++extern void sw64_dirtyhelper_write_lockflag(void* gs, ULong src) ++{ ++ VexGuestSW64State *guest_state = (VexGuestSW64State *)gs; ++ ULong *addr = (ULong*)&guest_state->guest_r0; ++#if defined(VGP_sw64_linux) ++ __asm__ volatile ( ++ ".set noreorder" "\n\t" ++ "wr_f %0" "\n\t" ++ : ++ : "r" ((addr[src])) ++ ); ++#endif ++} ++ ++/* On non-sw64 platforms, return 1. */ ++ULong sw64_dirtyhelper_rtc(void* gs) { ++#if defined(VGP_sw64_linux) ++ ULong tc = 0; ++ __asm__ volatile ("rtc %0" : "=r" (tc) : :); ++ return tc; ++#else ++ return 1UL; ++#endif ++} ++ ++ULong sw64_dirtyhelper_rcid(void* gs) { ++#if defined(VGP_sw64_linux) ++ ULong cid = 0; ++ __asm__ volatile ("rcid %0" : "=r" (cid) : :); ++ return cid; ++#else ++ return 0UL; ++#endif ++} ++ ++ULong sw64_dirtyhelper_calc_crc32b ( ULong acc, ULong bits ) ++{ ++ UInt i; ++ ULong crc = (bits & 0xFFULL) ^ (acc & 0xFFFFFFFFULL); ++ for (i = 0; i < 8; i++) ++ crc = (crc >> 1) ^ ((crc & 1) ? 0xEDB88320ULL : 0); ++ return crc; ++} ++ ++ULong sw64_dirtyhelper_calc_crc32h ( ULong acc, ULong bits ) ++{ ++ UInt i; ++ ULong crc = (bits & 0xFFFFULL) ^ (acc & 0xFFFFFFFFULL); ++ for (i = 0; i < 16; i++) ++ crc = (crc >> 1) ^ ((crc & 1) ? 0xEDB88320ULL : 0); ++ return crc; ++} ++ ++ULong sw64_dirtyhelper_calc_crc32w ( ULong acc, ULong bits ) ++{ ++ UInt i; ++ ULong crc = (bits & 0xFFFFFFFFULL) ^ (acc & 0xFFFFFFFFULL); ++ for (i = 0; i < 32; i++) ++ crc = (crc >> 1) ^ ((crc & 1) ? 0xEDB88320ULL : 0); ++ return crc; ++} ++ ++ULong sw64_dirtyhelper_calc_crc32l ( ULong acc, ULong bits ) ++{ ++ UInt i; ++ ULong crc = bits ^ (acc & 0xFFFFFFFFULL); ++ for (i = 0; i < 64; i++) ++ crc = (crc >> 1) ^ ((crc & 1) ? 0xEDB88320ULL : 0); ++ return crc; ++} ++ ++ULong sw64_dirtyhelper_calc_crc32cb ( ULong acc, ULong bits ) ++{ ++ UInt i; ++ ULong crc = (bits & 0xFFULL) ^ (acc & 0xFFFFFFFFULL); ++ for (i = 0; i < 8; i++) ++ crc = (crc >> 1) ^ ((crc & 1) ? 0x82F63B78ULL : 0); ++ return crc; ++} ++ ++ULong sw64_dirtyhelper_calc_crc32ch ( ULong acc, ULong bits ) ++{ ++ UInt i; ++ ULong crc = (bits & 0xFFFFULL) ^ (acc & 0xFFFFFFFFULL); ++ for (i = 0; i < 16; i++) ++ crc = (crc >> 1) ^ ((crc & 1) ? 0x82F63B78ULL : 0); ++ return crc; ++} ++ ++ULong sw64_dirtyhelper_calc_crc32cw ( ULong acc, ULong bits ) ++{ ++ UInt i; ++ ULong crc = (bits & 0xFFFFFFFFULL) ^ (acc & 0xFFFFFFFFULL); ++ for (i = 0; i < 32; i++) ++ crc = (crc >> 1) ^ ((crc & 1) ? 0x82F63B78ULL : 0); ++ return crc; ++} ++ ++ULong sw64_dirtyhelper_calc_crc32cl ( ULong acc, ULong bits ) ++{ ++ UInt i; ++ ULong crc = bits ^ (acc & 0xFFFFFFFFULL); ++ for (i = 0; i < 64; i++) ++ crc = (crc >> 1) ^ ((crc & 1) ? 0x82F63B78ULL : 0); ++ return crc; ++} ++ ++/*---------------------------------------------------------------*/ ++/*--- end guest_sw64_helpers.c ---*/ ++/*---------------------------------------------------------------*/ +diff --git a/VEX/priv/guest_sw64_toIR.c b/VEX/priv/guest_sw64_toIR.c +new file mode 100644 +index 000000000..2e3244191 +--- /dev/null ++++ b/VEX/priv/guest_sw64_toIR.c +@@ -0,0 +1,3496 @@ ++ ++/*--------------------------------------------------------------------*/ ++/*--- begin guest_arm64_toIR.c ---*/ ++/*--------------------------------------------------------------------*/ ++ ++/* ++ This file is part of Valgrind, a dynamic binary instrumentation ++ framework. ++ ++ Copyright (C) 2013-2017 OpenWorks ++ info@open-works.net ++ ++ This program is free software; you can redistribute it and/or ++ modify it under the terms of the GNU General Public License as ++ published by the Free Software Foundation; either version 2 of the ++ License, or (at your option) any later version. ++ ++ This program is distributed in the hope that it will be useful, but ++ WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with this program; if not, see . ++ ++ The GNU General Public License is contained in the file COPYING. ++*/ ++ ++/* Translates SW64 code to IR. */ ++ ++#include "libvex_basictypes.h" ++#include "libvex_ir.h" ++#include "libvex.h" ++#include "libvex_guest_sw64.h" ++ ++#include "main_util.h" ++#include "main_globals.h" ++#include "guest_generic_bb_to_IR.h" ++#include "guest_sw64_defs.h" ++ ++/*------------------------------------------------------------*/ ++/*--- Globals ---*/ ++/*------------------------------------------------------------*/ ++ ++/* These are set at the start of the translation of a instruction, so ++ that we don't have to pass them around endlessly. CONST means does ++ not change during translation of the instruction. ++*/ ++ ++/* CONST: what is the host's endianness? We need to know this in ++ order to do sub-register accesses to the SIMD/FP registers ++ correctly. */ ++static VexEndness host_endness; ++ ++/* CONST: The guest address for the instruction currently being ++ translated. */ ++static Addr64 guest_PC_curr_instr; ++ ++/* MOD: The IRSB* into which we're generating code. */ ++static IRSB* irsb; ++ ++ ++ ++/*------------------------------------------------------------*/ ++/*--- Helpers for accessing guest registers. ---*/ ++/*------------------------------------------------------------*/ ++ ++#define OFFB_r0 offsetof(VexGuestSW64State,guest_r0) ++#define OFFB_r1 offsetof(VexGuestSW64State,guest_r1) ++#define OFFB_r2 offsetof(VexGuestSW64State,guest_r2) ++#define OFFB_r3 offsetof(VexGuestSW64State,guest_r3) ++#define OFFB_r4 offsetof(VexGuestSW64State,guest_r4) ++#define OFFB_r5 offsetof(VexGuestSW64State,guest_r5) ++#define OFFB_r6 offsetof(VexGuestSW64State,guest_r6) ++#define OFFB_r7 offsetof(VexGuestSW64State,guest_r7) ++#define OFFB_r8 offsetof(VexGuestSW64State,guest_r8) ++#define OFFB_r9 offsetof(VexGuestSW64State,guest_r9) ++#define OFFB_r10 offsetof(VexGuestSW64State,guest_r10) ++#define OFFB_r11 offsetof(VexGuestSW64State,guest_r11) ++#define OFFB_r12 offsetof(VexGuestSW64State,guest_r12) ++#define OFFB_r13 offsetof(VexGuestSW64State,guest_r13) ++#define OFFB_r14 offsetof(VexGuestSW64State,guest_r14) ++#define OFFB_r15 offsetof(VexGuestSW64State,guest_r15) ++#define OFFB_r16 offsetof(VexGuestSW64State,guest_r16) ++#define OFFB_r17 offsetof(VexGuestSW64State,guest_r17) ++#define OFFB_r18 offsetof(VexGuestSW64State,guest_r18) ++#define OFFB_r19 offsetof(VexGuestSW64State,guest_r19) ++#define OFFB_r20 offsetof(VexGuestSW64State,guest_r20) ++#define OFFB_r21 offsetof(VexGuestSW64State,guest_r21) ++#define OFFB_r22 offsetof(VexGuestSW64State,guest_r22) ++#define OFFB_r23 offsetof(VexGuestSW64State,guest_r23) ++#define OFFB_r24 offsetof(VexGuestSW64State,guest_r24) ++#define OFFB_r25 offsetof(VexGuestSW64State,guest_r25) ++#define OFFB_r26 offsetof(VexGuestSW64State,guest_r26) ++#define OFFB_r27 offsetof(VexGuestSW64State,guest_r27) ++#define OFFB_r28 offsetof(VexGuestSW64State,guest_r28) ++#define OFFB_r29 offsetof(VexGuestSW64State,guest_r29) ++#define OFFB_r30 offsetof(VexGuestSW64State,guest_r30) ++#define OFFB_r31 offsetof(VexGuestSW64State,guest_r31) ++#define OFFB_PC offsetof(VexGuestSW64State,guest_PC) ++#define OFFB_CSR offsetof(VexGuestSW64State,guest_CSR) ++ ++#define OFFB_f0 offsetof(VexGuestSW64State,guest_f0) ++#define OFFB_f1 offsetof(VexGuestSW64State,guest_f1) ++#define OFFB_f2 offsetof(VexGuestSW64State,guest_f2) ++#define OFFB_f3 offsetof(VexGuestSW64State,guest_f3) ++#define OFFB_f4 offsetof(VexGuestSW64State,guest_f4) ++#define OFFB_f5 offsetof(VexGuestSW64State,guest_f5) ++#define OFFB_f6 offsetof(VexGuestSW64State,guest_f6) ++#define OFFB_f7 offsetof(VexGuestSW64State,guest_f7) ++#define OFFB_f8 offsetof(VexGuestSW64State,guest_f8) ++#define OFFB_f9 offsetof(VexGuestSW64State,guest_f9) ++#define OFFB_f10 offsetof(VexGuestSW64State,guest_f10) ++#define OFFB_f11 offsetof(VexGuestSW64State,guest_f11) ++#define OFFB_f12 offsetof(VexGuestSW64State,guest_f12) ++#define OFFB_f13 offsetof(VexGuestSW64State,guest_f13) ++#define OFFB_f14 offsetof(VexGuestSW64State,guest_f14) ++#define OFFB_f15 offsetof(VexGuestSW64State,guest_f15) ++#define OFFB_f16 offsetof(VexGuestSW64State,guest_f16) ++#define OFFB_f17 offsetof(VexGuestSW64State,guest_f17) ++#define OFFB_f18 offsetof(VexGuestSW64State,guest_f18) ++#define OFFB_f19 offsetof(VexGuestSW64State,guest_f19) ++#define OFFB_f20 offsetof(VexGuestSW64State,guest_f20) ++#define OFFB_f21 offsetof(VexGuestSW64State,guest_f21) ++#define OFFB_f22 offsetof(VexGuestSW64State,guest_f22) ++#define OFFB_f23 offsetof(VexGuestSW64State,guest_f23) ++#define OFFB_f24 offsetof(VexGuestSW64State,guest_f24) ++#define OFFB_f25 offsetof(VexGuestSW64State,guest_f25) ++#define OFFB_f26 offsetof(VexGuestSW64State,guest_f26) ++#define OFFB_f27 offsetof(VexGuestSW64State,guest_f27) ++#define OFFB_f28 offsetof(VexGuestSW64State,guest_f28) ++#define OFFB_f29 offsetof(VexGuestSW64State,guest_f29) ++#define OFFB_f30 offsetof(VexGuestSW64State,guest_f30) ++#define OFFB_f31 offsetof(VexGuestSW64State,guest_f31) ++#define OFFB_FPCR offsetof(VexGuestSW64State,guest_FPCR) ++ ++#define OFFB_EMNOTE offsetof(VexGuestSW64State,guest_EMNOTE) ++#define OFFB_CMSTART offsetof(VexGuestSW64State,guest_CMSTART) ++#define OFFB_CMLEN offsetof(VexGuestSW64State,guest_CMLEN) ++#define OFFB_NRADDR offsetof(VexGuestSW64State,guest_NRADDR) ++ ++#define OFFB_LOCKFLAG offsetof(VexGuestSW64State,guest_LOCKFLAG) ++#define OFFB_LOCKVALID offsetof(VexGuestSW64State,guest_LOCKVALID) ++#define OFFB_LOCKSUCCESS offsetof(VexGuestSW64State,guest_LOCKSUCCESS) ++#define OFFB_LOCKSIZE offsetof(VexGuestSW64State,guest_LOCKSIZE) ++#define OFFB_LOCKADDR offsetof(VexGuestSW64State,guest_LOCKADDR) ++#define OFFB_LOCKDATA offsetof(VexGuestSW64State,guest_LOCKDATA) ++ ++#define OFFB_TID offsetof(VexGuestSW64State, guest_TID) ++ ++/* ---------------- Integer registers ---------------- */ ++ ++static Int offsetIReg ( UInt iregNo ) ++{ ++ switch (iregNo) { ++ case 0: return OFFB_r0; ++ case 1: return OFFB_r1; ++ case 2: return OFFB_r2; ++ case 3: return OFFB_r3; ++ case 4: return OFFB_r4; ++ case 5: return OFFB_r5; ++ case 6: return OFFB_r6; ++ case 7: return OFFB_r7; ++ case 8: return OFFB_r8; ++ case 9: return OFFB_r9; ++ case 10: return OFFB_r10; ++ case 11: return OFFB_r11; ++ case 12: return OFFB_r12; ++ case 13: return OFFB_r13; ++ case 14: return OFFB_r14; ++ case 15: return OFFB_r15; ++ case 16: return OFFB_r16; ++ case 17: return OFFB_r17; ++ case 18: return OFFB_r18; ++ case 19: return OFFB_r19; ++ case 20: return OFFB_r20; ++ case 21: return OFFB_r21; ++ case 22: return OFFB_r22; ++ case 23: return OFFB_r23; ++ case 24: return OFFB_r24; ++ case 25: return OFFB_r25; ++ case 26: return OFFB_r26; ++ case 27: return OFFB_r27; ++ case 28: return OFFB_r28; ++ case 29: return OFFB_r29; ++ case 30: return OFFB_r30; ++ case 31: return OFFB_r31; ++ default: vassert(0); ++ } ++} ++ ++/* ---------------- Float registers ---------------- */ ++ ++static Int offsetFReg ( UInt iregNo ) ++{ ++ switch (iregNo) { ++ case 0: return OFFB_f0; ++ case 1: return OFFB_f1; ++ case 2: return OFFB_f2; ++ case 3: return OFFB_f3; ++ case 4: return OFFB_f4; ++ case 5: return OFFB_f5; ++ case 6: return OFFB_f6; ++ case 7: return OFFB_f7; ++ case 8: return OFFB_f8; ++ case 9: return OFFB_f9; ++ case 10: return OFFB_f10; ++ case 11: return OFFB_f11; ++ case 12: return OFFB_f12; ++ case 13: return OFFB_f13; ++ case 14: return OFFB_f14; ++ case 15: return OFFB_f15; ++ case 16: return OFFB_f16; ++ case 17: return OFFB_f17; ++ case 18: return OFFB_f18; ++ case 19: return OFFB_f19; ++ case 20: return OFFB_f20; ++ case 21: return OFFB_f21; ++ case 22: return OFFB_f22; ++ case 23: return OFFB_f23; ++ case 24: return OFFB_f24; ++ case 25: return OFFB_f25; ++ case 26: return OFFB_f26; ++ case 27: return OFFB_f27; ++ case 28: return OFFB_f28; ++ case 29: return OFFB_f29; ++ case 30: return OFFB_f30; ++ case 31: return OFFB_f31; ++ default: vassert(0); ++ } ++} ++ ++/*------------------------------------------------------------*/ ++/*--- Debugging output ---*/ ++/*------------------------------------------------------------*/ ++ ++#define DIP(format, args...) \ ++ if (vex_traceflags & VEX_TRACE_FE) \ ++ vex_printf(format, ## args) ++ ++#define DIS(buf, format, args...) \ ++ if (vex_traceflags & VEX_TRACE_FE) \ ++ vex_sprintf(buf, format, ## args) ++ ++/*------------------------------------------------------------*/ ++/*--- Helper bits and pieces for deconstructing the ---*/ ++/*--- arm insn stream. ---*/ ++/*------------------------------------------------------------*/ ++ ++/* Do a little-endian load of a 32-bit word, regardless of the ++ endianness of the underlying host. */ ++static inline UInt fetch32 ( const UChar* p ) ++{ ++ UInt w = 0; ++ w = (w << 8) | p[3]; ++ w = (w << 8) | p[2]; ++ w = (w << 8) | p[1]; ++ w = (w << 8) | p[0]; ++ return w; ++} ++ ++/* Sign extend a N-bit value up to 64 bits, by copying ++ bit N-1 into all higher positions. */ ++static ULong SEXT_to_64 ( ULong x, UInt n ) ++{ ++ vassert(n > 1 && n < 64); ++ x <<= (64-n); ++ Long r = (Long)x; ++ r >>= (64-n); ++ return (ULong)r; ++} ++ ++static inline UInt extract(UInt instr, Int l, Int r) ++{ ++ vassert(l >= 0 && l <= 31); ++ vassert(r >= 0 && r <= 31); ++ vassert(l >= r); ++ return (instr << (31 - l)) >> (r + 31 - l); ++} ++ ++/*------------------------------------------------------------*/ ++/*--- Helper bits and pieces for getting imm, ra, rb, disp ---*/ ++/*------------------------ in different intructions format.---*/ ++/*------------------------------------------------------------*/ ++///branch insn format ++ /*|31 26 | 25 21 | 20 0|*/ ++ /*| opcode | ra | disp |*/ ++ ++///load/store insn format ++ /*|31 26 | 25 21 | 20 16| 15 0|*/ ++ /*| opcode | ra | rb | disp |*/ ++ ++///simple calculate insn format ++ /*|31 26 | 25 21 | 20 16| 15 13 |12 5| 4 0|*/ ++ /*| opcode | ra | rb | 000 | function | rc |*/ //register ++ /*| opcode | ra | imm | function | rc |*/ //immediate ++ ++///complex integer calculate insn format ++ /*|31 26 | 25 21 | 20 16| 15 13 |12 10| 9 5 | 4 0 |*/ ++ /*| opcode | ra | rb | 000 | function | rc | rd |*/ //register ++ /*| opcode | ra | imm | function | rc | rd |*/ //immediate ++ ++///complex float calculate insn format ++ /*|31 26 | 25 21 | 20 16| 15 10 |9 5| 4 0|*/ ++ /*| opcode | fa | fb | func | fc | fd |*/ //register ++ /*| opcode | fa | fb | func | imm | fd |*/ //immediate ++ ++/*------------------------------------------------------------*/ ++/*--- Helper bits and pieces for creating IR fragments. ---*/ ++/*------------------------------------------------------------*/ ++ ++static IRExpr* mkU8 ( UInt i ) ++{ ++ vassert(i < 256); ++ return IRExpr_Const(IRConst_U8( (UChar)i )); ++} ++static IRExpr* mkU32 ( UInt i ) ++{ ++ return IRExpr_Const(IRConst_U32(i)); ++} ++static IRExpr* mkU64 ( ULong i ) ++{ ++ return IRExpr_Const(IRConst_U64(i)); ++} ++static IRExpr* mkF64 ( Double i ) ++{ ++ return IRExpr_Const(IRConst_F64(i)); ++} ++/* Generate a new temporary of the given type. */ ++static IRTemp newTemp ( IRType ty ) ++{ ++ vassert(isPlausibleIRType(ty)); ++ return newIRTemp( irsb->tyenv, ty ); ++} ++static IRExpr* mkexpr ( IRTemp tmp ) ++{ ++ return IRExpr_RdTmp(tmp); ++} ++static IRExpr* unop ( IROp op, IRExpr* a ) ++{ ++ return IRExpr_Unop(op, a); ++} ++ ++static IRExpr* binop ( IROp op, IRExpr* a1, IRExpr* a2 ) ++{ ++ return IRExpr_Binop(op, a1, a2); ++} ++ ++static IRExpr* triop ( IROp op, IRExpr* a1, IRExpr* a2, IRExpr* a3 ) ++{ ++ return IRExpr_Triop(op, a1, a2, a3); ++} ++ ++static IRExpr* quaop( IROp op, IRExpr* a1, IRExpr* a2, IRExpr* a3, IRExpr* a4 ) ++{ ++ return IRExpr_Qop(op, a1, a2, a3, a4); ++} ++ ++static IRExpr* mkshiftbits( IRExpr* e ) ++{ ++ vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I64); ++ return binop(Iop_And8, unop(Iop_64to8, e), mkU8(0x3F)); ++} ++ ++static IRExpr* mkshiftbits32( IRExpr* e ) ++{ ++ vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I64); ++ return binop(Iop_And8, unop(Iop_64to8, e), mkU8(0x1F)); ++} ++ ++/*------------------------------------------------------------*/ ++/*--- Helper pieces of statement and expression. ---*/ ++/*------------------------------------------------------------*/ ++/* Add a statement to the list held by "irbb". */ ++static void stmt ( IRStmt* st ) ++{ ++ addStmtToIRSB( irsb, st ); ++} ++ ++static void assign ( IRTemp dst, IRExpr* e ) ++{ ++ stmt( IRStmt_WrTmp(dst, e) ); ++} ++ ++static void putPC ( IRExpr* e ) ++{ ++ vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I64); ++ stmt( IRStmt_Put(OFFB_PC, e) ); ++} ++ ++static IRExpr* getIReg ( UInt iregNo ) ++{ ++ vassert(iregNo < 32); ++ if(iregNo == 31) ++ return mkU64(0); ++ else ++ return IRExpr_Get( offsetIReg(iregNo), Ity_I64 ); ++} ++ ++static void putIReg ( UInt iregNo, IRExpr* e ) ++{ ++ vassert(iregNo < 32); ++ vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I64); ++ if (iregNo == 31) ++ stmt( IRStmt_NoOp() ); ++ else ++ stmt( IRStmt_Put(offsetIReg(iregNo), e) ); ++} ++ ++static IRExpr* getFReg ( UInt fegNo ) ++{ ++ vassert(fegNo < 32); ++ if(fegNo == 31) ++ return mkF64(0); ++ else ++ return IRExpr_Get( offsetFReg(fegNo), Ity_F64 ); ++} ++ ++static void putFReg ( UInt fegNo, IRExpr* e ) ++{ ++ vassert(fegNo < 32); ++ vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_F64); ++ if (fegNo == 31) ++ stmt( IRStmt_NoOp() ); ++ else ++ stmt( IRStmt_Put(offsetFReg(fegNo), e) ); ++} ++ ++static inline IRExpr* load(IRType ty, IRExpr* addr) ++{ ++ return IRExpr_Load(Iend_LE, ty, addr); ++} ++static inline void store(IRExpr* addr, IRExpr* data) ++{ ++ stmt( IRStmt_Store(Iend_LE, addr, data)); ++} ++ ++/* U-widen 8/16/32/64 bit int expr to 64. */ ++static IRExpr* widenUto64 ( IRType srcTy, IRExpr* e ) ++{ ++ switch (srcTy) { ++ case Ity_I64: return e; ++ case Ity_I32: return unop(Iop_32Uto64, e); ++ case Ity_I16: return unop(Iop_16Uto64, e); ++ case Ity_I8: return unop(Iop_8Uto64, e); ++ default: vpanic("widenUto64(sw64)"); ++ } ++} ++ ++/* Narrow 64 bit int expr to 8/16/32/64. Clearly only some ++ of these combinations make sense. */ ++static IRExpr* narrowFrom64 ( IRType dstTy, IRExpr* e ) ++{ ++ switch (dstTy) { ++ case Ity_I64: return e; ++ case Ity_I32: return unop(Iop_64to32, e); ++ case Ity_I16: return unop(Iop_64to16, e); ++ case Ity_I8: return unop(Iop_64to8, e); ++ default: vpanic("narrowFrom64(sw64)"); ++ } ++} ++ ++static void condexit(IRExpr *cond, Addr iftrue) ++{ ++ vassert(typeOfIRExpr(irsb->tyenv, cond) == Ity_I1); ++ stmt(IRStmt_Exit(cond, ++ Ijk_Boring, ++ IRConst_U64(iftrue), ++ OFFB_PC)); ++} ++ ++/* ++ Check instruction is any one of below ++ 00 f0 fe af stl $r31,-4096(sp) ++ 00 d0 fe af stl $r31,-12288(sp) ++ 00 b0 fe af stl $r31,-20480(sp) ++ 00 90 fe af stl $r31,-28672(sp) ++ ++ Or is this sequence ++ 00 e0 f6 af stl $r31,-8192($r22) ++ 37 21 e0 4a subl $r23,0x1,$r23 ++ 00 e0 d6 fa ldi $r22,-8192($r22) ++ fc ff ff c6 bne $r23,-4 ++ ?? ?? d6 fb ldi sp,-n($r22) ++*/ ++static Bool is_stack_probe(const UChar* instr) ++{ ++ if (fetch32(instr) == 0xaffef000) { ++ return True; ++ } ++ if (fetch32(instr) == 0xaffed000) { ++ return True; ++ } ++ if (fetch32(instr) == 0xaffeb000) { ++ return True; ++ } ++ if (fetch32(instr) == 0xaffe9000) { ++ return True; ++ } ++ ++ if (fetch32(instr + 0) == 0xaff6e000 && ++ fetch32(instr + 4) == 0x4ae02137 && ++ fetch32(instr + 8) == 0xfad6e000 && ++ fetch32(instr + 12) == 0xc6fffffc && ++ fetch32(instr + 16) >> 16 == 0xfbd6) { ++ return True; ++ } ++ ++ return False; ++} ++ ++/* Generate IR for ((x & mask) >>u sh) | ((x << sh) & mask) */ ++static IRTemp math_SWAPHELPER ( IRTemp x, ULong mask, Int sh ) ++{ ++ IRTemp maskT = newTemp(Ity_I64); ++ IRTemp res = newTemp(Ity_I64); ++ vassert(sh >= 1 && sh <= 63); ++ assign(maskT, mkU64(mask)); ++ assign( res, ++ binop(Iop_Or64, ++ binop(Iop_Shr64, ++ binop(Iop_And64,mkexpr(x),mkexpr(maskT)), ++ mkU8(sh)), ++ binop(Iop_And64, ++ binop(Iop_Shl64,mkexpr(x),mkU8(sh)), ++ mkexpr(maskT)) ++ ) ++ ); ++ return res; ++} ++ ++/*------------------------------------------------------------*/ ++/*--- Front-End translate ---*/ ++/*------------------------------------------------------------*/ ++ ++static Bool dis_SW64_syscall(DisResult* dres, UInt insn) ++{ ++ UInt hmc = extract(insn, 7, 0); ++ ++ HChar const *desc; ++ switch (hmc) { ++ case 0x83: desc = "syscall"; break; ++ case 0x9e: desc = "read_unique"; break; ++ case 0x9f: desc = "write_unique"; break; ++ case 0x87: desc = "rwreg"; break; ++ case 0x86: desc = "imb"; break; ++ case 0x81: desc = "bugchk"; break; ++ case 0x80: desc = "bpt"; break; ++ case 0xaa: desc = "gentrap"; break; ++ case 0x02: desc = "draina"; break; ++ case 0x00: desc = "halt"; break; ++ default: return False; ++ } ++ ++ DIP("sys_call 0x%x: %s\n", hmc, desc); ++ ++ switch (hmc) { ++ case 0x83: /* syscall */ ++ putPC(mkU64(guest_PC_curr_instr + 4)); ++ dres->jk_StopHere = Ijk_Sys_syscall; ++ dres->whatNext = Dis_StopHere; ++ break; ++ case 0x9e: /* read_unique: r0 <- unique */ ++ putIReg(0, IRExpr_Get(OFFB_TID, Ity_I64)); ++ break; ++ case 0x9f: /* write_unique: unique <- r16 */ ++ stmt(IRStmt_Put(OFFB_TID, getIReg(16))); ++ break; ++ case 0x86: /* imb */ ++ stmt(IRStmt_MBE(Imbe_Fence)); ++ break; ++ case 0xaa: /* gentrap: raise SIGFPE */ ++ putPC(mkU64(guest_PC_curr_instr + 4)); ++ dres->whatNext = Dis_StopHere; ++ dres->jk_StopHere = Ijk_SigFPE_IntDiv; ++ break; ++ case 0x87: /* rwreg: marked as deprecated */ ++ case 0x81: /* bugchk: not implemented in kernel */ ++ case 0x80: /* bpt: not implemented in kernel */ ++ case 0x02: /* draina: not used and will not be implemented */ ++ case 0x00: /* halt: simply do nothings */ ++ stmt(IRStmt_NoOp()); ++ break; ++ default: ++ return False; ++ } ++ ++ return True; ++} ++ ++static Bool dis_SW64_branch(DisResult* dres, UInt insn) ++{ ++ UInt opcode = extract(insn, 31, 26); ++ UInt ra = extract(insn, 25, 21); ++ UInt disp = extract(insn, 20, 0); ++ UInt longdisp = extract(insn, 25, 0); ++ ++ ULong nextpc = guest_PC_curr_instr + 4; ++ ULong targpc = nextpc + (SEXT_to_64(disp, 21) << 2); ++ HChar const *nm = NULL; ++ IRExpr *cond = NULL; ++ switch(opcode) { ++ case 0x4: ++ nm = "BR"; ++ break; ++ case 0x5: ++ nm = "BSR"; ++ break; ++ case 0x1D: ++ nm = "LBR"; ++ targpc = nextpc + (SEXT_to_64(longdisp, 26) << 2); ++ break; ++ case 0x30: ++ nm = "BEQ"; ++ cond = binop(Iop_CmpEQ64, getIReg(ra), mkU64(0)); ++ break; ++ case 0x31: ++ nm = "BNE"; ++ cond = binop(Iop_CmpNE64, getIReg(ra), mkU64(0)); ++ break; ++ case 0x32: ++ nm = "BLT"; ++ cond = binop(Iop_CmpLT64S, getIReg(ra), mkU64(0)); ++ break; ++ case 0x33: ++ nm = "BLE"; ++ cond = binop(Iop_CmpLE64S, getIReg(ra), mkU64(0)); ++ break; ++ case 0x34: ++ nm = "BGT"; ++ cond = binop(Iop_CmpLT64S, mkU64(0), getIReg(ra)); ++ break; ++ case 0x35: ++ nm = "BGE"; ++ cond = binop(Iop_CmpLE64S, mkU64(0), getIReg(ra)); ++ break; ++ case 0x36: ++ nm = "BLBC"; ++ cond = binop(Iop_CmpEQ64, ++ binop(Iop_And64, getIReg(ra), mkU64(0x1)), mkU64(0)); ++ break; ++ case 0x37: ++ nm = "BLBS"; ++ cond = binop(Iop_CmpNE64, ++ binop(Iop_And64, getIReg(ra), mkU64(0x1)), mkU64(0)); ++ break; ++ case 0x38: ++ nm = "FBEQ"; ++ cond = binop(Iop_CmpFEQ64, getFReg(ra), mkF64(0)); ++ break; ++ case 0x39: ++ nm = "FBNE"; ++ cond = binop(Iop_CmpFNE64, getFReg(ra), mkF64(0)); ++ break; ++ case 0x3a: ++ nm = "FBLT"; ++ cond = binop(Iop_CmpFLT64, getFReg(ra), mkF64(0)); ++ break; ++ case 0x3b: ++ nm = "FBLE"; ++ cond = binop(Iop_CmpFLE64, getFReg(ra), mkF64(0)); ++ break; ++ case 0x3c: ++ nm = "FBGT"; ++ cond = binop(Iop_CmpFGT64, getFReg(ra), mkF64(0)); ++ break; ++ case 0x3d: ++ nm = "FBGE"; ++ cond = binop(Iop_CmpFGE64, getFReg(ra), mkF64(0)); ++ break; ++ default: ++ return False; ++ } ++ ++ /* optmize for 'BR 0' : no need to branch, just read PC */ ++ if (!cond && nextpc == targpc && opcode != 0x1D) { ++ DIP("%s r%u 0x%llx (READ PC)\n", nm, ra, targpc); ++ putIReg(ra, mkU64(nextpc)); ++ return True; ++ } ++ ++ if (opcode != 0x1D) { ++ DIP("%s r%u 0x%llx\n", nm, ra, targpc); ++ } else { ++ DIP("%s 0x%llx\n", nm, targpc); ++ } ++ ++ if (cond) { ++ /* condiction branch */ ++ condexit(cond, targpc); ++ putPC(mkU64(nextpc)); ++ } else { ++ /* uncondction branch */ ++ if (opcode != 0x1D) { ++ putIReg(ra, mkU64(nextpc)); ++ } ++ putPC(mkU64(targpc)); ++ } ++ ++ dres->whatNext = Dis_StopHere; ++ dres->jk_StopHere = Ijk_Boring; ++ return True; ++} ++ ++static Bool dis_SW64_jump(DisResult* dres, UInt insn) ++{ ++ UInt opcode = extract(insn, 31, 26); ++ UInt ra = extract(insn, 25, 21); ++ UInt rb = extract(insn, 20, 16); ++ ULong nextpc = guest_PC_curr_instr + 4; ++ ++ HChar const *nm; ++ IRJumpKind jk; ++ switch (opcode) { ++ case 0x1: ++ nm = "CALL"; ++ jk = Ijk_Call; ++ break; ++ case 0x2: ++ nm = "RET"; ++ jk = Ijk_Ret; ++ break; ++ case 0x3: ++ nm = "JMP"; ++ jk = Ijk_Boring; ++ break; ++ default: ++ return False; ++ } ++ ++ DIP("%s r%u, (r%u)\n", nm, ra, rb); ++ ++ /* ra 与 rb 可能指定了同一个寄存器，需将 rb 的运算结果保存至 IRTemp 后， ++ 才可更新 ra 的值，否则后续 PC 值不正确 */ ++ IRTemp vaddr = newTemp(Ity_I64); ++ assign(vaddr, binop(Iop_And64, ++ getIReg(rb), ++ unop(Iop_Not64, mkU64(0x3)))); ++ ++ putIReg(ra, mkU64(nextpc)); ++ putPC(mkexpr(vaddr)); ++ ++ dres->whatNext = Dis_StopHere; ++ dres->jk_StopHere = jk; ++ return True; ++} ++ ++static Bool dis_SW64_load_imm(DisResult* dres, UInt insn) ++{ ++ UInt opcode = extract(insn, 31, 26); ++ UInt ra = extract(insn, 25, 21); ++ UInt rb = extract(insn, 20, 16); ++ UInt disp = extract(insn, 15, 0); ++ ++ HChar const *nm; ++ ULong imm; ++ switch (opcode) { ++ case 0x3E: nm = "LDI"; imm = SEXT_to_64(disp, 16); break; ++ case 0x3F: nm = "LDIH"; imm = SEXT_to_64(disp, 16) << 16; break; ++ default: return False; ++ } ++ ++ DIP("%s r%u, 0x%x(r%u)\n", nm, ra, disp, rb); ++ ++ putIReg(ra, binop(Iop_Add64, getIReg(rb), mkU64(imm))); ++ return True; ++} ++ ++static Bool dis_SW64_integer_load(UInt opcode, UInt ra, UInt rb, UInt disp, ++ Bool autoinc) ++{ ++ IROp widen; ++ Bool align; ++ HChar const *nm; ++ IRType ity; ++ if (autoinc) { ++ switch (opcode) { ++ case 0x0: nm = "LDBU_A"; ity = Ity_I8; widen = Iop_8Uto64; align = True; break; ++ case 0x1: nm = "LDHU_A"; ity = Ity_I16; widen = Iop_16Uto64; align = True; break; ++ case 0x2: nm = "LDW_A"; ity = Ity_I32; widen = Iop_32Sto64; align = True; break; ++ case 0x3: nm = "LDL_A"; ity = Ity_I64; widen = Iop_INVALID; align = True; break; ++ default: return False; ++ } ++ } else { ++ switch (opcode) { ++ case 0x20: nm = "LDBU"; ity = Ity_I8; widen = Iop_8Uto64; align = True; break; ++ case 0x21: nm = "LDHU"; ity = Ity_I16; widen = Iop_16Uto64; align = True; break; ++ case 0x22: nm = "LDW"; ity = Ity_I32; widen = Iop_32Sto64; align = True; break; ++ case 0x23: nm = "LDL"; ity = Ity_I64; widen = Iop_INVALID; align = True; break; ++ case 0x24: nm = "LDL_U"; ity = Ity_I64; widen = Iop_INVALID; align = False; break; ++ default: return False; ++ } ++ } ++ ++ if (ra == 31 && !autoinc) { ++ DIP("%s r%u, 0x%x(r%u) (Ra == 31, NOP)\n", nm, ra, disp, rb); ++ stmt( IRStmt_NoOp() ); ++ return True; ++ } ++ ++ DIP("%s r%u, 0x%x(r%u)\n", nm, ra, disp, rb); ++ ++ IRExpr *vaddr; ++ if (autoinc) { ++ vaddr = getIReg(rb); ++ } else { ++ vaddr = binop(Iop_Add64, ++ getIReg(rb), ++ mkU64(SEXT_to_64(disp, 16))); ++ } ++ ++ if (!align) { ++ vaddr = binop(Iop_And64, vaddr, unop(Iop_Not64, mkU64(0x7))); ++ } ++ ++ IRExpr *e = load(ity, vaddr); ++ ++ if (widen != Iop_INVALID) { ++ e = unop(widen, e); ++ } ++ ++ putIReg(ra, e); ++ ++ if (autoinc) { ++ putIReg(rb, binop(Iop_Add64, getIReg(rb), mkU64(SEXT_to_64(disp, 12)))); ++ } ++ ++ return True; ++} ++ ++static Bool dis_SW64_integer_store(UInt opcode, UInt ra, UInt rb, UInt disp, ++ Bool autoinc) ++{ ++ IRType ity; ++ Bool align; ++ HChar const *nm; ++ if (autoinc) { ++ switch (opcode) { ++ case 0x6: nm = "STB_A"; ity = Ity_I8; align = True; break; ++ case 0x7: nm = "STH_A"; ity = Ity_I16; align = True; break; ++ case 0x8: nm = "STW_A"; ity = Ity_I32; align = True; break; ++ case 0x9: nm = "STL_A"; ity = Ity_I64; align = True; break; ++ default: return False; ++ } ++ } else { ++ switch (opcode) { ++ case 0x28: nm = "STB"; ity = Ity_I8; align = True; break; ++ case 0x29: nm = "STH"; ity = Ity_I16; align = True; break; ++ case 0x2A: nm = "STW"; ity = Ity_I32; align = True; break; ++ case 0x2B: nm = "STL"; ity = Ity_I64; align = True; break; ++ case 0x2C: nm = "STL_U"; ity = Ity_I64; align = False; break; ++ default: return False; ++ } ++ } ++ ++ if (!autoinc && is_stack_probe((const UChar *)guest_PC_curr_instr)) { ++ DIP("STL r%u, 0x%x(r%u) (stack probe, ignored)\n", ra, disp, rb); ++ stmt(IRStmt_NoOp()); ++ return True; ++ } ++ ++ DIP("%s r%u, 0x%x(r%u)\n", nm, ra, disp, rb); ++ ++ IRExpr *vaddr; ++ if (autoinc) { ++ vaddr = getIReg(rb); ++ } else { ++ vaddr = binop(Iop_Add64, ++ getIReg(rb), ++ mkU64(SEXT_to_64(disp, 16))); ++ } ++ ++ if (!align) { ++ vaddr = binop(Iop_And64, vaddr, unop(Iop_Not64, mkU64(0x7))); ++ } ++ ++ store(vaddr, narrowFrom64(ity, getIReg(ra))); ++ ++ if (autoinc) { ++ putIReg(rb, binop(Iop_Add64, getIReg(rb), mkU64(SEXT_to_64(disp, 12)))); ++ } ++ ++ return True; ++} ++ ++static Bool dis_SW64_float_load(UInt opcode, UInt fa, UInt rb, UInt disp, ++ Bool autoinc) ++{ ++ IRType ty; ++ HChar const *nm; ++ if (autoinc) { ++ switch (opcode) { ++ case 0x4: nm = "FLDS_A"; ty = Ity_F32; break; ++ case 0x5: nm = "FLDD_A"; ty = Ity_F64; break; ++ default: return False; ++ } ++ } else { ++ switch (opcode) { ++ case 0x26: nm = "FLDS"; ty = Ity_F32; break; ++ case 0x27: nm = "FLDD"; ty = Ity_F64; break; ++ default: return False; ++ } ++ } ++ ++ if (!autoinc && fa == 31) { ++ DIP("%s f%u, 0x%x(r%u) (Fa == 31, NOP)\n", nm, fa, disp, rb); ++ stmt( IRStmt_NoOp() ); ++ return True; ++ } ++ ++ DIP("%s f%u, 0x%x(r%u)\n", nm, fa, disp, rb); ++ ++ IRExpr *vaddr; ++ if (autoinc) { ++ vaddr = getIReg(rb); ++ } else { ++ vaddr = binop(Iop_Add64, ++ getIReg(rb), ++ mkU64(SEXT_to_64(disp, 16))); ++ } ++ ++ IRExpr *e = (ty == Ity_F32) ? unop(Iop_F32toF64, load(Ity_F32, vaddr)) : ++ (ty == Ity_F64) ? load(Ity_F64, vaddr) : ++ (vassert(0), NULL); ++ ++ putFReg(fa, e); ++ ++ if (autoinc) { ++ putIReg(rb, binop(Iop_Add64, getIReg(rb), mkU64(SEXT_to_64(disp, 12)))); ++ } ++ ++ return True; ++} ++ ++static Bool dis_SW64_float_store(UInt opcode, UInt fa, UInt rb, UInt disp, ++ Bool autoinc) ++{ ++ IRType ty; ++ HChar const *nm; ++ if (autoinc) { ++ switch (opcode) { ++ case 0xA: nm = "FSTS_A"; ty = Ity_F32; break; ++ case 0xB: nm = "FSTD_A"; ty = Ity_F64; break; ++ default: return False; ++ } ++ } else { ++ switch (opcode) { ++ case 0x2E: nm = "FSTS"; ty = Ity_F32; break; ++ case 0x2F: nm = "FSTD"; ty = Ity_F64; break; ++ default: return False; ++ } ++ } ++ ++ DIP("%s f%u, 0x%x(r%u)\n", nm, fa, disp, rb); ++ ++ IRExpr *vaddr; ++ if (autoinc) { ++ vaddr = getIReg(rb); ++ } else { ++ vaddr = binop(Iop_Add64, ++ getIReg(rb), ++ mkU64(SEXT_to_64(disp, 16))); ++ } ++ ++ IRExpr *e = (ty == Ity_F32) ? unop(Iop_TruncF64asF32, getFReg(fa)) : ++ (ty == Ity_F64) ? getFReg(fa) : ++ (vassert(0), NULL); ++ ++ store(vaddr, e); ++ ++ if (autoinc) { ++ putIReg(rb, binop(Iop_Add64, getIReg(rb), mkU64(SEXT_to_64(disp, 12)))); ++ } ++ ++ return True; ++} ++ ++static Bool dis_SW64_nc_load(UInt func, UInt ra, UInt rb, UInt uimm12) ++{ ++ IRExpr *vaddr = binop(Iop_Add64, ++ getIReg(rb), ++ mkU64(SEXT_to_64(uimm12, 12))); ++ switch (func) { ++ case 0xa: ++ DIP("LDW_NC r%u, 0x%x(r%u)\n", ra, uimm12, rb); ++ putIReg(ra, unop(Iop_32Sto64, load(Ity_I32, vaddr))); ++ return True; ++ case 0xb: ++ DIP("LDL_NC r%u, 0x%x(r%u)\n", ra, uimm12, rb); ++ putIReg(ra, load(Ity_I64, vaddr)); ++ return True; ++ case 0xc: ++ DIP("LDD_NC f%u, 0x%x(r%u)\n", ra, uimm12, rb); ++ putFReg(ra, load(Ity_F64, vaddr)); ++ return True; ++ default: ++ return False; ++ } ++} ++ ++static Bool dis_SW64_nc_store(UInt func, UInt ra, UInt rb, UInt uimm12) ++{ ++ IRExpr *vaddr = binop(Iop_Add64, ++ getIReg(rb), ++ mkU64(SEXT_to_64(uimm12, 12))); ++ switch (func) { ++ case 0xd: ++ DIP("STW_NC r%u, 0x%x(r%u)\n", ra, uimm12, rb); ++ store(vaddr, unop(Iop_64to32, getIReg(ra))); ++ return True; ++ case 0xe: ++ DIP("STL_NC r%u, 0x%x(r%u)\n", ra, uimm12, rb); ++ store(vaddr, getIReg(ra)); ++ return True; ++ case 0xf: ++ DIP("STD_NC f%u, 0x%x(r%u)\n", ra, uimm12, rb); ++ store(vaddr, getFReg(ra)); ++ return True; ++ default: ++ return False; ++ } ++} ++ ++static Bool dis_SW64_integer_add_sub(UInt opcode, UInt func, UInt ra, UInt rb, ++ UInt rc, UInt uimm8) ++{ ++ IROp iop; ++ UInt width, sbits; ++ HChar const *nm; ++ switch (func) { ++ case 0x0: iop = Iop_Add32; width = 32; sbits = 0; nm = "ADDW"; break; ++ case 0x1: iop = Iop_Sub32; width = 32; sbits = 0; nm = "SUBW"; break; ++ case 0x2: iop = Iop_Add32; width = 32; sbits = 2; nm = "S4ADDW"; break; ++ case 0x3: iop = Iop_Sub32; width = 32; sbits = 2; nm = "S4SUBW"; break; ++ case 0x4: iop = Iop_Add32; width = 32; sbits = 3; nm = "S8ADDW"; break; ++ case 0x5: iop = Iop_Sub32; width = 32; sbits = 3; nm = "S8SUBW"; break; ++ case 0x8: iop = Iop_Add64; width = 64; sbits = 0; nm = "ADDL"; break; ++ case 0x9: iop = Iop_Sub64; width = 64; sbits = 0; nm = "SUBL"; break; ++ case 0xA: iop = Iop_Add64; width = 64; sbits = 2; nm = "S4ADDL"; break; ++ case 0xB: iop = Iop_Sub64; width = 64; sbits = 2; nm = "S4SUBL"; break; ++ case 0xC: iop = Iop_Add64; width = 64; sbits = 3; nm = "S8ADDL"; break; ++ case 0xD: iop = Iop_Sub64; width = 64; sbits = 3; nm = "S8SUBL"; break; ++ default: return False; ++ } ++ ++ IRExpr *rbv; ++ if (opcode == 0x10) { ++ DIP("%s r%u, r%u, r%u\n", nm, ra, rb, rc); ++ rbv = getIReg(rb); ++ } else if (opcode == 0x12) { ++ DIP("%s r%u, %u, r%u\n", nm, ra, uimm8, rc); ++ rbv = mkU64(uimm8); ++ } else { ++ return False; ++ } ++ ++ IRExpr *rav = getIReg(ra); ++ if (sbits) ++ rav = binop(Iop_Shl64, rav, mkU8(sbits)); ++ ++ if (width == 64) ++ putIReg(rc, binop(iop, rav, rbv)); ++ else ++ putIReg(rc, unop(Iop_32Sto64, ++ binop(iop, ++ unop(Iop_64to32, rav), ++ unop(Iop_64to32, rbv)))); ++ ++ return True; ++} ++ ++static Bool dis_SW64_integer_mul(UInt opcode, UInt func, UInt ra, UInt rb, ++ UInt rc, UInt uimm8) ++{ ++ IRExpr *rbv; ++ if (opcode == 0x10) { ++ rbv = getIReg(rb); ++ } else if (opcode == 0x12) { ++ rbv = mkU64(uimm8); ++ } else { ++ return False; ++ } ++ ++ const HChar *nm; ++ IRExpr *expr; ++ switch(func) { ++ case 0x10: ++ nm = "MULW"; ++ expr = unop(Iop_32Sto64, binop(Iop_Mul32, ++ unop(Iop_64to32, getIReg(ra)), ++ unop(Iop_64to32, rbv))); ++ break; ++ case 0x18: ++ nm = "MULL"; ++ expr = binop(Iop_Mul64, getIReg(ra), rbv); ++ break; ++ case 0x19: ++ nm = "UMULH"; ++ expr = unop(Iop_128HIto64, binop(Iop_MullU64, ++ getIReg(ra), ++ rbv)); ++ break; ++ default: ++ return False; ++ } ++ ++ if (opcode == 0x10) { ++ DIP("%s r%u, r%u, r%u\n", nm, ra, rb, rc); ++ } else { ++ DIP("%s r%u, %u, r%u\n", nm, ra, uimm8, rc); ++ } ++ ++ putIReg(rc, expr); ++ return True; ++} ++ ++static Bool dis_SW64_integer_div(UInt func, UInt ra, UInt rb, UInt rc) ++{ ++ const HChar *nm; ++ IRExpr *expr; ++ switch(func) { ++ case 0x11: ++ nm = "DIVW"; ++ expr = unop(Iop_32Sto64, binop(Iop_DivS32, ++ unop(Iop_64to32, getIReg(ra)), ++ unop(Iop_64to32, getIReg(rb)))); ++ break; ++ case 0x12: ++ nm = "UDIVW"; ++ expr = unop(Iop_32Uto64, binop(Iop_DivU32, ++ unop(Iop_64to32, getIReg(ra)), ++ unop(Iop_64to32, getIReg(rb)))); ++ break; ++ case 0x13: ++ nm = "REMW"; ++ expr = unop(Iop_32Sto64, unop(Iop_64HIto32, ++ binop(Iop_DivModS32to32, ++ unop(Iop_64to32, getIReg(ra)), ++ unop(Iop_64to32, getIReg(rb))))); ++ break; ++ case 0x14: ++ nm = "UREMW"; ++ expr = unop(Iop_32Uto64, unop(Iop_64HIto32, ++ binop(Iop_DivModU32to32, ++ unop(Iop_64to32, getIReg(ra)), ++ unop(Iop_64to32, getIReg(rb))))); ++ break; ++ case 0x1A: ++ nm = "DIVL"; ++ expr = binop(Iop_DivS64, getIReg(ra), getIReg(rb)); ++ break; ++ case 0x1B: ++ nm = "UDIVL"; ++ expr = binop(Iop_DivU64, getIReg(ra), getIReg(rb)); ++ break; ++ case 0x1C: ++ nm = "REML"; ++ expr = unop(Iop_128HIto64, binop(Iop_DivModS64to64, getIReg(ra), getIReg(rb))); ++ break; ++ case 0x1D: ++ nm = "UREML"; ++ expr = unop(Iop_128HIto64, binop(Iop_DivModU64to64, getIReg(ra), getIReg(rb))); ++ break; ++ default: ++ return False; ++ } ++ ++ DIP("%s r%u, r%u, r%u\n", nm, ra, rb, rc); ++ putIReg(rc, expr); ++ return True; ++} ++ ++static Bool dis_SW64_addpi(UInt func, UInt rc, UInt imm13) ++{ ++ const HChar *nm; ++ IRExpr *expr; ++ ULong nextpc = guest_PC_curr_instr + 4; ++ ULong simm13 = SEXT_to_64(imm13, 13); ++ switch (func) { ++ case 0x1E: ++ nm = "ADDPI"; ++ expr = binop(Iop_Add64, ++ mkU64(nextpc), ++ binop(Iop_Shl64, mkU64(simm13), mkU8(2))); ++ break; ++ case 0x1F: ++ nm = "ADDPIS"; ++ expr = binop(Iop_Add64, ++ mkU64(nextpc & ~0xFFFFULL), ++ binop(Iop_Shl64, mkU64(simm13), mkU8(16))); ++ break; ++ default: return False; ++ } ++ ++ DIP("%s %u r%u\n", nm, imm13, rc); ++ putIReg(rc, expr); ++ return True; ++} ++ ++static Bool dis_SW64_crc32(UInt func, UInt ra, UInt rb, UInt rc) ++{ ++ HChar const *nm; ++ ULong (*fp)(ULong, ULong); ++ switch (func) { ++ case 0x20: nm = "CRC32B"; fp = &sw64_dirtyhelper_calc_crc32b; break; ++ case 0x21: nm = "CRC32H"; fp = &sw64_dirtyhelper_calc_crc32h; break; ++ case 0x22: nm = "CRC32W"; fp = &sw64_dirtyhelper_calc_crc32w; break; ++ case 0x23: nm = "CRC32L"; fp = &sw64_dirtyhelper_calc_crc32l; break; ++ case 0x24: nm = "CRC32CB"; fp = &sw64_dirtyhelper_calc_crc32cb; break; ++ case 0x25: nm = "CRC32CH"; fp = &sw64_dirtyhelper_calc_crc32ch; break; ++ case 0x26: nm = "CRC32CW"; fp = &sw64_dirtyhelper_calc_crc32cw; break; ++ case 0x27: nm = "CRC32CL"; fp = &sw64_dirtyhelper_calc_crc32cl; break; ++ default: return False; ++ } ++ ++ DIP("%s r%u, r%u, r%u\n", nm, ra, rb, rc); ++ ++ IRTemp dst = newTemp(Ity_I64); ++ stmt(IRStmt_Dirty(unsafeIRDirty_1_N(dst, 0, nm, fp, ++ mkIRExprVec_2(getIReg(ra), getIReg(rb))))); ++ ++ putIReg(rc, mkexpr(dst)); ++ return True; ++} ++ ++static Bool dis_SW64_integer_cmp(UInt opcode, UInt func, UInt ra, UInt rb, ++ UInt rc, UInt uimm8) ++{ ++ IROp iop; ++ HChar const *nm; ++ switch (func) { ++ case 0x28: iop = Iop_CmpEQ64; nm = "CMPEQ"; break; ++ case 0x29: iop = Iop_CmpLT64S; nm = "CMPLT"; break; ++ case 0x2A: iop = Iop_CmpLE64S; nm = "CMPLE"; break; ++ case 0x2B: iop = Iop_CmpLT64U; nm = "CMPULT"; break; ++ case 0x2C: iop = Iop_CmpLE64U; nm = "CMPULE"; break; ++ default: return False; ++ } ++ ++ IRExpr *rbv; ++ if (opcode == 0x10) { ++ DIP("%s r%u, r%u, r%u\n", nm, ra, rb, rc); ++ rbv = getIReg(rb); ++ } else if (opcode == 0x12) { ++ DIP("%s r%u, %u, r%u\n", nm, ra, uimm8, rc); ++ rbv = mkU64(uimm8); ++ } else { ++ return False; ++ } ++ ++ putIReg(rc, unop(Iop_1Uto64, binop(iop, getIReg(ra), rbv))); ++ return True; ++} ++ ++static Bool dis_SW64_bit_setclear(UInt opcode, UInt func, UInt ra, UInt rb, ++ UInt rc, UInt uimm8) ++{ ++ IRExpr *rbv; ++ if (opcode == 0x10) { ++ rbv = getIReg(rb); ++ } else if (opcode == 0x12) { ++ rbv = mkU64(uimm8); ++ } else { ++ return False; ++ } ++ ++ const HChar *nm; ++ UInt not; ++ IROp iop; ++ switch(func) { ++ case 0x2D: nm = "SBT"; iop = Iop_Or64; not = 0; break; ++ case 0x2E: nm = "CBT"; iop = Iop_And64; not = 1; break; ++ default: return False; ++ } ++ ++ IRExpr *mask = binop(Iop_Shl64, mkU64(1), mkshiftbits(rbv)); ++ if (not) { ++ mask = unop(Iop_Not64, mask); ++ } ++ ++ if (opcode == 0x10) { ++ DIP("%s r%u, r%u, r%u\n", nm, ra, rb, rc); ++ } else { ++ DIP("%s r%u, %u, r%u\n", nm, ra, uimm8, rc); ++ } ++ ++ putIReg(rc, binop(iop, getIReg(ra), mask)); ++ return True; ++} ++ ++static Bool dis_SW64_bits_logical(UInt opcode, UInt func, UInt ra, UInt rb, ++ UInt rc, UInt uimm8) ++{ ++ IRExpr *rbv; ++ if (opcode == 0x10) { ++ rbv = getIReg(rb); ++ } else if (opcode == 0x12) { ++ rbv = mkU64(uimm8); ++ } else { ++ return False; ++ } ++ ++ const HChar *nm; ++ UInt not; ++ IROp iop; ++ switch(func) { ++ case 0x38: nm = "AND"; iop = Iop_And64; not = 0; break; ++ case 0x39: nm = "BIC"; iop = Iop_And64; not = 1; break; ++ case 0x3A: nm = "BIS"; iop = Iop_Or64; not = 0; break; ++ case 0x3B: nm = "ORNOT"; iop = Iop_Or64; not = 1; break; ++ case 0x3C: nm = "XOR"; iop = Iop_Xor64; not = 0; break; ++ case 0x3D: nm = "EQV"; iop = Iop_Xor64; not = 1; break; ++ default: return False; ++ } ++ ++ if (not) { ++ rbv = unop(Iop_Not64, rbv); ++ } ++ ++ if (opcode == 0x10) { ++ DIP("%s r%u, r%u, r%u\n", nm, ra, rb, rc); ++ } else { ++ DIP("%s r%u, %u, r%u\n", nm, ra, uimm8, rc); ++ } ++ ++ putIReg(rc, binop(iop, getIReg(ra), rbv)); ++ return True; ++} ++ ++ ++static Bool dis_SW64_bits_shift(UInt opcode, UInt func, UInt ra, UInt rb, ++ UInt rc, UInt uimm8) ++{ ++ const HChar *nm; ++ IROp iop; ++ Int bits; ++ switch (func) { ++ case 0x48: iop = Iop_Shl64; bits = 64; nm = "SLL"; break; ++ case 0x49: iop = Iop_Shr64; bits = 64; nm = "SRL"; break; ++ case 0x4A: iop = Iop_Sar64; bits = 64; nm = "SRA"; break; ++ case 0x4B: iop = Iop_INVALID; bits = -1; nm = "ROLL"; break; ++ case 0x4C: iop = Iop_Shl32; bits = 32; nm = "SLLW"; break; ++ case 0x4D: iop = Iop_Shr32; bits = 32; nm = "SRLW"; break; ++ case 0x4E: iop = Iop_Sar32; bits = 32; nm = "SRAW"; break; ++ case 0x4F: iop = Iop_INVALID; bits = -1; nm = "ROLW"; break; ++ default: return False; ++ } ++ ++ IRExpr *rbv; ++ if (opcode == 0x10) { ++ DIP("%s r%u, r%u, r%u\n", nm, ra, rb, rc); ++ rbv = getIReg(rb); ++ } else if (opcode == 0x12) { ++ DIP("%s r%u, %u, r%u\n", nm, ra, uimm8, rc); ++ rbv = mkU64(uimm8); ++ } else { ++ return False; ++ } ++ ++ if (func == 0x4B) { ++ putIReg(rc, binop(Iop_Or64, ++ binop(Iop_Shl64, getIReg(ra), mkshiftbits(rbv)), ++ binop(Iop_Shr64, getIReg(ra), mkshiftbits(binop(Iop_Sub64, mkU64(0), rbv))))); ++ } else if (func == 0x4F) { ++ putIReg(rc, unop(Iop_32Sto64, ++ binop(Iop_Or32, ++ binop(Iop_Shl32, ++ unop(Iop_64to32, getIReg(ra)), ++ mkshiftbits32(rbv)), ++ binop(Iop_Shr32, ++ unop(Iop_64to32, getIReg(ra)), ++ mkshiftbits32(binop(Iop_Sub64, mkU64(0), rbv)))))); ++ } else { ++ if (bits == 64) { ++ putIReg(rc, binop(iop, getIReg(ra), mkshiftbits(rbv))); ++ } else { ++ putIReg(rc, unop(Iop_32Sto64, binop(iop, unop(Iop_64to32, getIReg(ra)), mkshiftbits32(rbv)))); ++ } ++ } ++ ++ return True; ++} ++ ++ ++static Bool dis_SW64_bits_pop(UInt opcode, UInt func, UInt ra, UInt rb, ++ UInt rc, UInt uimm8) ++{ ++ if (opcode != 0x10) /* no immediate version for those instructions */ ++ return False; ++ ++ const HChar *nm; ++ IROp iop; ++ switch (func) { ++ case 0x58: iop = Iop_PopCount64; nm = "CTPOP"; break; ++ case 0x59: iop = Iop_ClzNat64; nm = "CTLZ"; break; ++ case 0x5A: iop = Iop_CtzNat64; nm = "CTTZ"; break; ++ default: return False; ++ } ++ ++ DIP("%s r%u, r%u\n", nm, rb, rc); ++ ++ putIReg(rc, unop(iop, getIReg(rb))); ++ return True; ++} ++ ++ ++static Bool dis_SW64_byte_swap(UInt func, UInt rb, UInt rc) ++{ ++ const HChar *nm; ++ UInt sz; ++ switch (func) { ++ case 0x5B: sz = 16; nm = "REVBH"; break; ++ case 0x5C: sz = 32; nm = "REVBW"; break; ++ case 0x5D: sz = 64; nm = "REVBL"; break; ++ default: return False; ++ } ++ ++ DIP("%s r%u, r%u\n", nm, rb, rc); ++ ++ IRTemp val = newTemp(Ity_I64); ++ assign(val, getIReg(rb)); ++ ++ if (sz == 16) { ++ val = math_SWAPHELPER(val, 0xFF00, 8); ++ } else if (sz == 32) { ++ val = math_SWAPHELPER(val, 0xFF00FF00ULL, 8); ++ val = math_SWAPHELPER(val, 0xFFFF0000ULL, 16); ++ } else if (sz == 64) { ++ val = math_SWAPHELPER(val, 0xFF00FF00FF00FF00ULL, 8); ++ val = math_SWAPHELPER(val, 0xFFFF0000FFFF0000ULL, 16); ++ val = math_SWAPHELPER(val, 0xFFFFFFFF00000000ULL, 32); ++ } else { ++ vassert(0); ++ } ++ ++ if (sz == 32) { ++ /* result of REVBW require sign-extended */ ++ putIReg(rc, unop(Iop_32Sto64, narrowFrom64(Ity_I32, mkexpr(val)))); ++ } else { ++ putIReg(rc, mkexpr(val)); ++ } ++ return True; ++} ++ ++static Bool dis_SW64_bits_zap(UInt opcode, UInt func, UInt ra, UInt rb, ++ UInt rc, UInt uimm8) ++{ ++ static const HChar* nms[5] = {"ZAP", "ZAPNOT", "SEXTB", "SEXTH", "CMPGEB"}; ++ if (func < 0x68 || func > 0x6c) ++ return False; ++ ++ IRExpr *rbv; ++ if (opcode == 0x10) { ++ DIP("%s r%u, r%u, r%u\n", nms[func - 0x68], ra, rb, rc); ++ rbv = getIReg(rb); ++ } else if (opcode == 0x12) { ++ DIP("%s r%u, %u, r%u\n", nms[func - 0x68], ra, uimm8, rc); ++ rbv = mkU64(uimm8); ++ } else { ++ return False; ++ } ++ ++ /* fast path for: ++ ZAPNOT Ra, 0xf, Rc ++ ZAPNOT Ra, 0x3, Rc ++ ZAPNOT Ra, 0x1, Rc ++ */ ++ if (func == 0x69 && opcode == 0x12 && ++ (uimm8 == 0xf || uimm8 == 0x3 || uimm8 == 0x1)) { ++ ++ IRExpr *rav = getIReg(ra); ++ IRExpr *e; ++ switch (uimm8) { ++ case 0xf: e = unop(Iop_32Uto64, unop(Iop_64to32, rav)); break; ++ case 0x3: e = unop(Iop_16Uto64, unop(Iop_64to16, rav)); break; ++ case 0x1: e = unop(Iop_8Uto64, unop(Iop_64to8, rav)); break; ++ default: return False; ++ } ++ putIReg(rc, e); ++ return True; ++ } ++ ++ switch (func) { ++ /* ZAP ZAPNOT */ ++ case 0x68: ++ case 0x69: { ++ /* ++ if x > 0 and x <= 0x7F, ++ x<<42 | x<<35 | x<<28 | x<<21 | x<<14 | x<<7 | x ++ is equal to ++ x<<42 + x<<35 + x<<28 + x<<21 + x<<14 + x<<7 + x ++ is equal to ++ x*2^42 + x*2^35 + x*2^28 + x*2^21 + x*2^14 + x*2^7 + x ++ is equal to ++ x * (2^42 + 2^35 + 2^28 + 2^21 + 2^14 + 2^7 + 1) ++ is equal to ++ x * 4432676798593 ++ */ ++ IRTemp t0 = newTemp(Ity_I64); ++ assign(t0, binop(Iop_And64, ++ mkU64(0x0101010101010101ULL), ++ binop(Iop_Or64, ++ binop(Iop_Shl64, ++ rbv, ++ mkU8(49)), ++ binop(Iop_Mul64, ++ mkU64(4432676798593ULL), ++ binop(Iop_And64, ++ mkU64(0x7F), ++ rbv))))); ++ ++ IRTemp t1 = newTemp(Ity_I64); ++ assign(t1, binop(Iop_Or64, ++ mkexpr(t0), ++ binop(Iop_Shl64, ++ mkexpr(t0), ++ mkU8(1)))); ++ ++ IRTemp t2 = newTemp(Ity_I64); ++ assign(t2, binop(Iop_Or64, ++ mkexpr(t1), ++ binop(Iop_Shl64, ++ mkexpr(t1), ++ mkU8(2)))); ++ ++ IRExpr *e = binop(Iop_Or64, ++ mkexpr(t2), ++ binop(Iop_Shl64, ++ mkexpr(t2), ++ mkU8(4))); ++ ++ if (func == 0x68) ++ e = unop(Iop_Not64, e); /* ZAP */ ++ ++ putIReg(rc, binop(Iop_And64, getIReg(ra), e)); ++ return True; ++ } ++ ++ /* SEXTB */ ++ case 0x6A: { ++ putIReg(rc, unop(Iop_8Sto64, unop(Iop_64to8, rbv))); ++ return True; ++ } ++ ++ /* SEXTH */ ++ case 0x6B: { ++ putIReg(rc, unop(Iop_16Sto64, unop(Iop_64to16, rbv))); ++ return True; ++ } ++ ++ /* CMPGEB */ ++ case 0x6C: { ++ IRTemp res = newTemp(Ity_I64); ++ assign(res, mkU64(0)); ++ for(int i=0; i<8; i++) ++ { ++ IRTemp tmp = newTemp(Ity_I64); ++ assign(tmp, binop(Iop_Or64, mkexpr(res), ++ binop(Iop_Shl64, ++ unop(Iop_1Uto64, binop(Iop_CmpLE64U, ++ binop(Iop_And64, rbv, mkU64(0xFFULL << (i * 8))), ++ binop(Iop_And64, getIReg(ra), mkU64(0xFFULL << (i * 8))))), ++ mkU8(i)))); ++ res = tmp; ++ } ++ putIReg(rc, mkexpr(res)); ++ return True; ++ } ++ ++ default: ++ return False; ++ } ++} ++ ++ ++static Bool dis_SW64_bits_insert(UInt opcode, UInt func, UInt ra, UInt rb, ++ UInt rc, UInt uimm8) ++{ ++ Bool toleft; ++ UInt sz; ++ const HChar *nm; ++ switch (func) { ++ case 0x40: toleft = True; sz = 8; nm = "INSLB"; break; ++ case 0x41: toleft = True; sz = 16; nm = "INSLH"; break; ++ case 0x42: toleft = True; sz = 32; nm = "INSLW"; break; ++ case 0x43: toleft = True; sz = 64; nm = "INSLL"; break; ++ case 0x44: toleft = False; sz = 8; nm = "INSHB"; break; ++ case 0x45: toleft = False; sz = 16; nm = "INSHH"; break; ++ case 0x46: toleft = False; sz = 32; nm = "INSHW"; break; ++ case 0x47: toleft = False; sz = 64; nm = "INSHL"; break; ++ default: return False; ++ } ++ ++ IRExpr *rbv; ++ if (opcode == 0x10) { ++ DIP("%s r%u, r%u, r%u\n", nm, ra, rb, rc); ++ rbv = getIReg(rb); ++ } else if (opcode == 0x12) { ++ DIP("%s r%u, %u, r%u\n", nm, ra, uimm8, rc); ++ rbv = mkU64(uimm8); ++ } else { ++ return False; ++ } ++ ++ IRExpr *rav; ++ if (sz == 8) { ++ rav = unop(Iop_8Uto64, unop(Iop_64to8, getIReg(ra))); ++ } else if (sz == 16) { ++ rav = unop(Iop_16Uto64, unop(Iop_64to16, getIReg(ra))); ++ } else if (sz == 32) { ++ rav = unop(Iop_32Uto64, unop(Iop_64to32, getIReg(ra))); ++ } else { ++ rav = getIReg(ra); ++ } ++ ++ if (toleft) { ++ /* rc = rav << ((rbv << 3) & 0x3F) */ ++ putIReg(rc, binop(Iop_Shl64, ++ rav, ++ mkshiftbits(binop(Iop_Shl64, ++ rbv, ++ mkU8(3))))); ++ } else { ++ /* rc = (rav >> 8) >> ((-8 - (rbv << 3)) & 0x3F) */ ++ putIReg(rc, binop(Iop_Shr64, ++ binop(Iop_Shr64, ++ rav, ++ mkU8(8)), ++ mkshiftbits(binop(Iop_Sub64, ++ mkU64(-8), ++ binop(Iop_Shl64, ++ rbv, ++ mkU8(3)))))); ++ } ++ ++ return True; ++} ++ ++static Bool dis_SW64_bits_extract(UInt opcode, UInt func, UInt ra, UInt rb, ++ UInt rc, UInt uimm8) ++{ ++ Bool toright; ++ UInt sz; ++ const HChar *nm; ++ switch (func) { ++ case 0x50: toright = True; sz = 8; nm = "EXTLB"; break; ++ case 0x51: toright = True; sz = 16; nm = "EXTLH"; break; ++ case 0x52: toright = True; sz = 32; nm = "EXTLW"; break; ++ case 0x53: toright = True; sz = 64; nm = "EXTLL"; break; ++ case 0x54: toright = False; sz = 8; nm = "EXTHB"; break; ++ case 0x55: toright = False; sz = 16; nm = "EXTHH"; break; ++ case 0x56: toright = False; sz = 32; nm = "EXTHW"; break; ++ case 0x57: toright = False; sz = 64; nm = "EXTHL"; break; ++ default: return False; ++ } ++ ++ IRExpr *rbv; ++ if (opcode == 0x10) { ++ DIP("%s r%u, r%u, r%u\n", nm, ra, rb, rc); ++ rbv = getIReg(rb); ++ } else if (opcode == 0x12) { ++ DIP("%s r%u, %u, r%u\n", nm, ra, uimm8, rc); ++ rbv = mkU64(uimm8); ++ } else { ++ return False; ++ } ++ ++ IRExpr *e; ++ if (toright) { ++ /* sbits = (rbv << 3) & 0x3F */ ++ IRExpr *sbits = binop(Iop_And8, ++ unop(Iop_64to8, ++ binop(Iop_Shl64, ++ rbv, ++ mkU8(3))), ++ mkU8(0x3F)); ++ e = binop(Iop_Shr64, getIReg(ra), sbits); ++ } else { ++ /* sbits = (0 - (rbv << 3)) & 0x3F */ ++ IRExpr *sbits = binop(Iop_And8, ++ unop(Iop_64to8, ++ binop(Iop_Sub64, ++ mkU64(0), ++ binop(Iop_Shl64, ++ rbv, ++ mkU8(3)))), ++ mkU8(0x3F)); ++ e = binop(Iop_Shl64, getIReg(ra), sbits); ++ } ++ ++ if (sz == 8) { ++ e = unop(Iop_8Uto64, unop(Iop_64to8, e)); ++ } else if (sz == 16) { ++ e = unop(Iop_16Uto64, unop(Iop_64to16, e)); ++ } else if (sz == 32) { ++ e = unop(Iop_32Uto64, unop(Iop_64to32, e)); ++ } ++ ++ putIReg(rc, e); ++ return True; ++} ++ ++static Bool dis_SW64_bits_mask(UInt opcode, UInt func, UInt ra, UInt rb, ++ UInt rc, UInt uimm8) ++{ ++ Bool lo; ++ ULong mask; ++ const HChar *nm; ++ switch (func) { ++ case 0x60: lo = True; mask = 0x00000000000000FF; nm = "MASKLB"; break; ++ case 0x61: lo = True; mask = 0x000000000000FFFF; nm = "MASKLH"; break; ++ case 0x62: lo = True; mask = 0x00000000FFFFFFFF; nm = "MASKLW"; break; ++ case 0x63: lo = True; mask = 0xFFFFFFFFFFFFFFFF; nm = "MASKLL"; break; ++ case 0x64: lo = False; mask = 0x0000000000000000; nm = "MASKHB"; break; ++ case 0x65: lo = False; mask = 0x00000000000000FF; nm = "MASKHH"; break; ++ case 0x66: lo = False; mask = 0x0000000000FFFFFF; nm = "MASKHW"; break; ++ case 0x67: lo = False; mask = 0x00FFFFFFFFFFFFFF; nm = "MASKHL"; break; ++ default: return False; ++ } ++ ++ IRExpr *rbv; ++ if (opcode == 0x10) { ++ DIP("%s r%u, r%u, r%u\n", nm, ra, rb, rc); ++ rbv = getIReg(rb); ++ } else if (opcode == 0x12) { ++ DIP("%s r%u, %u, r%u\n", nm, ra, uimm8, rc); ++ rbv = mkU64(uimm8); ++ } else { ++ return False; ++ } ++ ++ IRExpr *t; ++ if (lo) { ++ /* t = mask >> ((Rbv & 0x7) * 8) */ ++ t = binop(Iop_Shl64, ++ mkU64(mask), ++ unop(Iop_64to8, ++ binop(Iop_Shl64, ++ binop(Iop_And64, ++ rbv, ++ mkU64(0x7)), ++ mkU8(3)))); ++ } else { ++ /* t = mask >> (56 - (Rbv & 0x7) * 8) */ ++ t = binop(Iop_Shr64, ++ mkU64(mask), ++ unop(Iop_64to8, ++ binop(Iop_Sub64, ++ mkU64(56), ++ binop(Iop_Shl64, ++ binop(Iop_And64, ++ rbv, ++ mkU64(0x7)), ++ mkU8(3))))); ++ } ++ ++ /* rc = AndNot(Rav, t) */ ++ putIReg(rc, binop(Iop_And64, getIReg(ra), unop(Iop_Not64, t))); ++ return True; ++} ++ ++static Bool dis_SW64_sel(UInt insn) ++{ ++ /* |31 26 | 25 21 | 20 16| 15 13 |12 10| 9 5 | 4 0 | */ ++ /* | opcode | ra | rb | 000 | function | rc | rd | */ ++ /* | opcode | ra | imm | function | rc | rd | */ ++ UInt opcode = extract(insn, 31, 26); ++ UInt func = extract(insn, 12, 10); ++ UInt ra = extract(insn, 25, 21); ++ UInt rb = extract(insn, 20, 16); ++ UInt rc = extract(insn, 9, 5); ++ UInt rd = extract(insn, 4, 0); ++ UInt imm = extract(insn, 20, 13); ++ ++ const HChar *nm; ++ IRExpr *guard; ++ switch(func) { ++ case 0x0: ++ nm = "SELEQ"; ++ guard = binop(Iop_CmpEQ64, getIReg(ra), mkU64(0)); ++ break; ++ case 0x1: ++ nm = "SELGE"; ++ guard = binop(Iop_CmpLE64S, mkU64(0), getIReg(ra)); ++ break; ++ case 0x2: ++ nm = "SELGT"; ++ guard = binop(Iop_CmpLT64S, mkU64(0), getIReg(ra)); ++ break; ++ case 0x3: ++ nm = "SELLE"; ++ guard = binop(Iop_CmpLE64S, getIReg(ra), mkU64(0)); ++ break; ++ case 0x4: ++ nm = "SELLT"; ++ guard = binop(Iop_CmpLT64S, getIReg(ra), mkU64(0)); ++ break; ++ case 0x5: ++ nm = "SELNE"; ++ guard = binop(Iop_CmpNE64, getIReg(ra), mkU64(0)); ++ break; ++ case 0x6: ++ nm = "SELLBC"; ++ guard = binop(Iop_CmpEQ64, ++ binop(Iop_And64, getIReg(ra), mkU64(0x1)), ++ mkU64(0)); ++ break; ++ case 0x7: ++ nm = "SELLBS"; ++ guard = binop(Iop_CmpEQ64, ++ binop(Iop_And64, getIReg(ra), mkU64(0x1)), ++ mkU64(1)); ++ break; ++ default: ++ return False; ++ } ++ ++ IRExpr *rbv; ++ if (opcode == 0x11) { ++ DIP("%s, r%u, r%u, r%u, r%u\n", nm, ra, rb, rc, rd); ++ rbv = getIReg(rb); ++ } else if (opcode == 0x13) { ++ DIP("%s, r%u, %u, r%u, r%u\n", nm, ra, imm, rc, rd); ++ rbv = mkU64(imm); ++ } else { ++ return False; ++ } ++ ++ putIReg(rd, IRExpr_ITE(guard, rbv, getIReg(rc))); ++ return True; ++} ++ ++/* ---------------- FPCR round mode ---------------- */ ++ ++/* Generate IR to get hold of the rounding mode bits in FPCR, and ++ convert them to IR format. Bind the final result to the ++ returned temp. */ ++static IRTemp mk_get_IR_rounding_mode ( void ) ++{ ++ /* The sw64 encoding for rounding mode bits is: ++ 00 to zero ++ 01 to -infinity ++ 10 to nearest ++ 11 to +infinity ++ We need to convert that to the IR encoding: ++ 00 to nearest (the default) ++ 10 to +infinity ++ 01 to -infinity ++ 11 to zero ++ ++ Boss Yu say: ++ IREncd = 0b11 & (0b10000111 >> ((sw_fpcr >> 57) & 0b110)); ++ */ ++ ++ IRTemp IREncd = newTemp(Ity_I32); ++ assign(IREncd, unop(Iop_64to32, ++ binop(Iop_And64, ++ mkU64(0b11), ++ binop(Iop_Shr64, ++ mkU64(0b10000111), ++ unop(Iop_64to8, ++ binop(Iop_And64, ++ binop(Iop_Shr64, ++ IRExpr_Get(OFFB_FPCR, Ity_I64), ++ mkU8(57)), ++ mkU64(0b110))))))); ++ ++ return IREncd; ++} ++ ++static Bool dis_SW64_float_arith(UInt func, UInt fa, UInt fb, UInt fc) ++{ ++ IROp iop; ++ HChar const *nm; ++ UInt sz; ++ switch (func) { ++ case 0x0: nm = "FADDS"; iop = Iop_AddF64; sz = 32; break; ++ case 0x1: nm = "FADDD"; iop = Iop_AddF64; sz = 64; break; ++ case 0x2: nm = "FSUBS"; iop = Iop_SubF64; sz = 32; break; ++ case 0x3: nm = "FSUBD"; iop = Iop_SubF64; sz = 64; break; ++ case 0x4: nm = "FMULS"; iop = Iop_MulF64; sz = 32; break; ++ case 0x5: nm = "FMULD"; iop = Iop_MulF64; sz = 64; break; ++ case 0x6: nm = "FDIVS"; iop = Iop_DivF64; sz = 32; break; ++ case 0x7: nm = "FDIVD"; iop = Iop_DivF64; sz = 64; break; ++ default: return False; ++ } ++ ++ DIP("%s f%u, f%u, f%u\n", nm, fa, fb, fc); ++ ++ IRExpr *e = triop(iop, ++ mkexpr(mk_get_IR_rounding_mode()), ++ getFReg(fa), ++ getFReg(fb)); ++ ++ if (sz == 32) ++ e = binop(Iop_RoundF64toF32, mkexpr(mk_get_IR_rounding_mode()), e); ++ ++ putFReg(fc, e); ++ return True; ++} ++ ++ ++static Bool dis_SW64_fsqrt(UInt func, UInt fb, UInt fc) ++{ ++ IROp iop; ++ HChar const *nm; ++ UInt sz; ++ switch (func) { ++ case 0x8: nm = "FSQRTS"; iop = Iop_SqrtF64; sz = 32; break; ++ case 0x9: nm = "FSQRTD"; iop = Iop_SqrtF64; sz = 64; break; ++ default: return False; ++ } ++ ++ DIP("%s f%u, f%u\n", nm, fb, fc); ++ ++ IRExpr *e = binop(iop, ++ mkexpr(mk_get_IR_rounding_mode()), ++ getFReg(fb)); ++ ++ if (sz == 32) ++ e = binop(Iop_RoundF64toF32, mkexpr(mk_get_IR_rounding_mode()), e); ++ ++ putFReg(fc, e); ++ return True; ++} ++ ++ ++static Bool dis_SW64_fcmp(UInt func, UInt fa, UInt fb, UInt fc) ++{ ++ IROp iop; ++ HChar const *nm; ++ switch(func) { ++ case 0x10: nm = "FCMPEQ"; iop = Iop_CmpFEQ64; break; ++ case 0x11: nm = "FCMPLE"; iop = Iop_CmpFLE64; break; ++ case 0x12: nm = "FCMPLT"; iop = Iop_CmpFLT64; break; ++ case 0x13: nm = "FCMPUN"; iop = Iop_CmpFUN64; break; ++ default: return False; ++ } ++ ++ DIP("%s f%u, f%u, f%u\n", nm, fa, fb, fc); ++ ++ putFReg(fc, IRExpr_ITE(binop(iop, getFReg(fa), getFReg(fb)), ++ mkF64(2), ++ mkF64(0))); ++ return True; ++} ++ ++ ++static Bool dis_SW64_fcvt(UInt func, UInt fb, UInt fc) ++{ ++ /* FCVTSD */ ++ if (func == 0x20) { ++ DIP("FCVTSD f%u, f%u\n", fb, fc); ++ putFReg(fc, unop(Iop_F32toF64, ++ unop(Iop_TruncF64asF32, getFReg(fb)))); ++ return True; ++ } ++ ++ /* FCVTDS */ ++ if (func == 0x21) { ++ DIP("FCVTDS f%u, f%u\n", fb, fc); ++ putFReg(fc, binop(Iop_RoundF64toF32, ++ mkexpr(mk_get_IR_rounding_mode()), ++ getFReg(fb))); ++ return True; ++ } ++ ++ /* FCVTDL_x */ ++ if (func >= 0x22 && func <= 0x25) { ++ HChar const *nm; ++ UInt rm; ++ switch (func) { ++ case 0x22: nm = "FCVTDL_G"; rm = Irrm_NEAREST; break; ++ case 0x23: nm = "FCVTDL_P"; rm = Irrm_PosINF; break; ++ case 0x24: nm = "FCVTDL_Z"; rm = Irrm_ZERO; break; ++ case 0x25: nm = "FCVTDL_N"; rm = Irrm_NegINF; break; ++ } ++ DIP("%s f%u, f%u\n", nm, fb, fc); ++ putFReg(fc, unop(Iop_ReinterpI64asF64, ++ binop(Iop_F64toI64S, ++ mkU32(rm), ++ getFReg(fb)))); ++ return True; ++ } ++ ++ /* FCVTDL */ ++ if (func == 0x27) { ++ DIP("FCVTDL f%u, f%u\n", fb, fc); ++ putFReg(fc, unop(Iop_ReinterpI64asF64, ++ binop(Iop_F64toI64S, ++ mkexpr(mk_get_IR_rounding_mode()), ++ getFReg(fb)))); ++ return True; ++ } ++ ++ ++ else if (func == 0x28) //FCVTWL ++ { ++ DIP("FCVTWL f%u, f%u\n", fb, fc); ++ IRTemp fbv = newTemp(Ity_I64); ++ assign(fbv, unop(Iop_ReinterpF64asI64,getFReg(fb))); ++ IRTemp fcv_31_0 = newTemp(Ity_I64); //fbv->fcv_31_0 ++ assign(fcv_31_0, binop(Iop_Or64, ++ binop(Iop_Shr64, ++ binop(Iop_And64, mkexpr(fbv), mkU64(0xC000000000000000ULL)), //63:62 ++ mkU8(32)), ++ binop(Iop_Shr64, ++ binop(Iop_And64, mkexpr(fbv), mkU64(0x07FFFFFFE0000000ULL)), //58:29 ++ mkU8(29)))); ++ putFReg(fc, unop(Iop_ReinterpI64asF64,binop(Iop_Sar64, ++ binop(Iop_Shl64, mkexpr(fcv_31_0), mkU8(32)), ++ mkU8(32)))); ++ ++ return True; ++ } ++ else if(func == 0x29) //FCVTLW ++ { ++ DIP("FCVTLW f%u, f%u\n", fb, fc); ++ IRTemp fbv = newTemp(Ity_I64); ++ assign(fbv, unop(Iop_ReinterpF64asI64,getFReg(fb))); ++ IRTemp fcv = newTemp(Ity_I64); //fbv->fcv ++ assign(fcv, binop(Iop_Or64, ++ binop(Iop_Or64, ++ binop(Iop_Shl64, ++ binop(Iop_And64, mkexpr(fbv), mkU64(0xC0000000ULL)), //31:30 ++ mkU8(32)), ++ binop(Iop_Shl64, ++ binop(Iop_And64, mkexpr(fbv), mkU64(0x3FFFFFFFULL)), //29:0 ++ mkU8(29))), ++ mkU64(0ULL))); ++ putFReg(fc, unop(Iop_ReinterpI64asF64, mkexpr(fcv))); ++ return True; ++ } ++ else if(func == 0x2D) //FCVTLS ++ { ++ DIP("FCVTLS f%u, f%u\n", fb, fc); ++ putFReg(fc, binop(Iop_RoundF64toF32, ++ mkexpr(mk_get_IR_rounding_mode()), ++ binop(Iop_I64StoF64, ++ mkexpr(mk_get_IR_rounding_mode()), ++ unop(Iop_ReinterpF64asI64, getFReg(fb))))); ++ return True; ++ } ++ else if(func == 0x2F) //FCVTLD ++ { ++ DIP("FCVTLD f%u, f%u\n", fb, fc); ++ putFReg(fc, binop(Iop_I64StoF64, ++ mkexpr(mk_get_IR_rounding_mode()), ++ unop(Iop_ReinterpF64asI64,getFReg(fb)))); ++ return True; ++ } ++ ++ return False; ++} ++ ++static Bool dis_SW64_fcpy(UInt func, UInt fa, UInt fb, UInt fc) ++{ ++ /* FCPYS */ ++ if (func == 0x30) { ++ DIP("FCPYS f%u, f%u, f%u\n", fa, fb, fc); ++ ++ /* "fcpys fa, fa, fc" is same as "mov fa, fc" */ ++ if (fa == fb) { ++ putFReg(fc, getFReg(fa)); ++ return True; ++ } ++ ++ /* "fcpys f31, fb, fc" is same as "abs fb, fc" */ ++ if (fa == 31) { ++ putFReg(fc, unop(Iop_AbsF64, getFReg(fb))); ++ return True; ++ } ++ ++ putFReg(fc, unop(Iop_ReinterpI64asF64, ++ binop(Iop_Or64, ++ binop(Iop_And64, ++ unop(Iop_ReinterpF64asI64, getFReg(fa)), ++ mkU64(0x8000000000000000ULL)), //63 ++ binop(Iop_And64, ++ unop(Iop_ReinterpF64asI64, getFReg(fb)), ++ mkU64(0x7FFFFFFFFFFFFFFFULL))))); //62:0 ++ return True; ++ } ++ ++ /* FCPYSE */ ++ if (func == 0x31) { ++ DIP("FCPYSE f%u, f%u, f%u\n", fa, fb, fc); ++ putFReg(fc, unop(Iop_ReinterpI64asF64, ++ binop(Iop_Or64, ++ binop(Iop_And64, ++ unop(Iop_ReinterpF64asI64, getFReg(fa)), ++ mkU64(0xFFF0000000000000ULL)), //63:52 ++ binop(Iop_And64, ++ unop(Iop_ReinterpF64asI64, getFReg(fb)), ++ mkU64(0xFFFFFFFFFFFFFULL))))); //51:0 ++ return True; ++ } ++ ++ /* FCPYSN */ ++ if (func == 0x32) { ++ DIP("FCPYSN f%u, f%u, f%u\n", fa, fb, fc); ++ ++ /* "fcpysn fa, fa, fc" is same as "neg fa, fc" */ ++ if (fa == fb) { ++ putFReg(fc, unop(Iop_NegF64, getFReg(fa))); ++ return True; ++ } ++ ++ putFReg(fc, unop(Iop_ReinterpI64asF64, ++ binop(Iop_Or64, ++ binop(Iop_And64, ++ unop(Iop_Not64, ++ unop(Iop_ReinterpF64asI64, getFReg(fa))), ++ mkU64(0x8000000000000000ULL)), //63 ++ binop(Iop_And64, ++ unop(Iop_ReinterpF64asI64, getFReg(fb)), ++ mkU64(0x7FFFFFFFFFFFFFFFULL))))); //62:0 ++ return True; ++ } ++ ++ return False; ++} ++ ++static Bool dis_SW64_intflt_transfer(UInt opcode, UInt func, UInt ra, UInt rc) ++{ ++ /* IFMOVS */ ++ if (opcode == 0x18 && func == 0x40) { ++ DIP("IFMOVS r%u, f%u\n", ra, rc); ++ putFReg(rc, unop(Iop_F32toF64, ++ unop(Iop_ReinterpI32asF32, ++ unop(Iop_64to32, getIReg(ra))))); ++ return True; ++ } ++ ++ /* IFMOVD */ ++ if (opcode == 0x18 && func == 0x41) { ++ DIP("IFMOVD r%u, f%u\n", ra, rc); ++ putFReg(rc, unop(Iop_ReinterpI64asF64,getIReg(ra))); ++ return True; ++ } ++ ++ /* FIMOVS */ ++ if (opcode == 0x10 && func == 0x70) { ++ DIP("FIMOVS f%u, r%u\n", ra, rc); ++ putIReg(rc, unop(Iop_32Sto64, ++ unop(Iop_ReinterpF32asI32, ++ unop(Iop_TruncF64asF32, getFReg(ra))))); ++ return True; ++ } ++ ++ /* FIMOVD */ ++ if (opcode == 0x10 && func == 0x78) { ++ DIP("FIMOVD f%u, r%u", ra, rc); ++ putIReg(rc, unop(Iop_ReinterpF64asI64, getFReg(ra))); ++ return True; ++ } ++ ++ return False; ++} ++ ++static Bool dis_SW64_intflt_convert(UInt opcode, UInt func, UInt rb, UInt fc) ++{ ++ IROp iop; ++ HChar const *nm; ++ UInt sbits, dbits; ++ switch(func) { ++ case 0x48: nm = "CMOVLS"; iop = Iop_I64StoF64; sbits = 64; dbits = 32; break; ++ case 0x49: nm = "CMOVWS"; iop = Iop_I32StoF64; sbits = 32; dbits = 32; break; ++ case 0x4a: nm = "CMOVLD"; iop = Iop_I64StoF64; sbits = 64; dbits = 64; break; ++ case 0x4b: nm = "CMOVWD"; iop = Iop_I32StoF64; sbits = 32; dbits = 64; break; ++ case 0x4c: nm = "CMOVULS"; iop = Iop_I64UtoF64; sbits = 64; dbits = 32; break; ++ case 0x4d: nm = "CMOVUWS"; iop = Iop_I32UtoF64; sbits = 32; dbits = 32; break; ++ case 0x4e: nm = "CMOVULD"; iop = Iop_I64UtoF64; sbits = 64; dbits = 64; break; ++ case 0x4f: nm = "CMOVUWD"; iop = Iop_I32UtoF64; sbits = 32; dbits = 64; break; ++ default: return False; ++ } ++ ++ DIP("%s r%u, f%u\n", nm, rb, fc); ++ ++ IRTemp rm = mk_get_IR_rounding_mode(); ++ ++ IRExpr *e = getIReg(rb); ++ ++ if (sbits == 32) ++ e = narrowFrom64(Ity_I32, e); ++ ++ if (sbits == 32) ++ e = unop(iop, e); ++ else ++ e = binop(iop, mkexpr(rm), e); ++ ++ if (dbits == 32) ++ e = binop(Iop_RoundF64toF32, mkexpr(rm), e); ++ ++ putFReg(fc, e); ++ return True; ++} ++ ++static Bool dis_SW64_fltint_convert(UInt opcode, UInt func, UInt fb, UInt rc) ++{ ++ HChar const *nm; ++ IROp iop; ++ IROp widen; ++ Int rm; ++ switch(func) { ++ case 0x72: nm = "CMOVDL"; iop = Iop_F64toI64S; widen = Iop_INVALID; rm = -1; break; ++ case 0x74: nm = "CMOVDL_G"; iop = Iop_F64toI64S; widen = Iop_INVALID; rm = Irrm_NEAREST; break; ++ case 0x7a: nm = "CMOVDL_P"; iop = Iop_F64toI64S; widen = Iop_INVALID; rm = Irrm_PosINF; break; ++ case 0x7c: nm = "CMOVDL_Z"; iop = Iop_F64toI64S; widen = Iop_INVALID; rm = Irrm_ZERO; break; ++ case 0x80: nm = "CMOVDL_N"; iop = Iop_F64toI64S; widen = Iop_INVALID; rm = Irrm_NegINF; break; ++ case 0x81: nm = "CMOVDLU"; iop = Iop_F64toI64U; widen = Iop_INVALID; rm = -1; break; ++ case 0x82: nm = "CMOVDLU_G"; iop = Iop_F64toI64U; widen = Iop_INVALID; rm = Irrm_NEAREST; break; ++ case 0x83: nm = "CMOVDLU_P"; iop = Iop_F64toI64U; widen = Iop_INVALID; rm = Irrm_PosINF; break; ++ case 0x84: nm = "CMOVDLU_Z"; iop = Iop_F64toI64U; widen = Iop_INVALID; rm = Irrm_ZERO; break; ++ case 0x85: nm = "CMOVDLU_N"; iop = Iop_F64toI64U; widen = Iop_INVALID; rm = Irrm_NegINF; break; ++ case 0x86: nm = "CMOVDWU"; iop = Iop_F64toI32U; widen = Iop_32Uto64; rm = -1; break; ++ case 0x87: nm = "CMOVDWU_G"; iop = Iop_F64toI32U; widen = Iop_32Uto64; rm = Irrm_NEAREST; break; ++ case 0x88: nm = "CMOVDWU_P"; iop = Iop_F64toI32U; widen = Iop_32Uto64; rm = Irrm_PosINF; break; ++ case 0x89: nm = "CMOVDWU_Z"; iop = Iop_F64toI32U; widen = Iop_32Uto64; rm = Irrm_ZERO; break; ++ case 0x8a: nm = "CMOVDWU_N"; iop = Iop_F64toI32U; widen = Iop_32Uto64; rm = Irrm_NegINF; break; ++ case 0x8b: nm = "CMOVDW"; iop = Iop_F64toI32S; widen = Iop_32Sto64; rm = -1; break; ++ case 0x8c: nm = "CMOVDW_G"; iop = Iop_F64toI32S; widen = Iop_32Sto64; rm = Irrm_NEAREST; break; ++ case 0x8d: nm = "CMOVDW_P"; iop = Iop_F64toI32S; widen = Iop_32Sto64; rm = Irrm_PosINF; break; ++ case 0x8e: nm = "CMOVDW_Z"; iop = Iop_F64toI32S; widen = Iop_32Sto64; rm = Irrm_ZERO; break; ++ case 0x8f: nm = "CMOVDW_N"; iop = Iop_F64toI32S; widen = Iop_32Sto64; rm = Irrm_NegINF; break; ++ default: return False; ++ } ++ ++ DIP("%s f%u, r%u\n", nm, fb, rc); ++ ++ IRTemp irrm; ++ if (rm == -1) { ++ irrm = mk_get_IR_rounding_mode(); ++ } else { ++ irrm = newTemp(Ity_I32); ++ assign(irrm, mkU32(rm)); ++ } ++ ++ IRExpr *e = binop(iop, mkexpr(irrm), getFReg(fb)); ++ ++ if (widen != Iop_INVALID) ++ e = unop(widen, e); ++ ++ putIReg(rc, e); ++ return True; ++} ++ ++static Bool dis_SW64_fpcr(UInt insn, UInt func) ++{ ++ /* ++ floating-point exception is not supported in Valgrind ++ always return 0 in exception flag bits ++ always return 1 in exception trapping bits ++ SETFPECx are No-Op ++ ++ floating-point rouding have a limited support ++ set and return those bits as-is ++ */ ++ UInt fa = extract(insn, 25, 21); ++ ++ /* RFPCR */ ++ if (func == 0x50) { ++ IRExpr *e; ++ DIP("RFPCR f%u\n", fa); ++ ++ e = IRExpr_Get(OFFB_FPCR, Ity_I64); ++ ++ /* clear bits other than rouding mode */ ++ e = binop(Iop_And64, mkU64(0xc00000000000000ULL), e); ++ ++ /* set exception trapping disable */ ++ e = binop(Iop_Or64, mkU64(0x600e000000000000ULL), e); ++ ++ putFReg(fa, unop(Iop_ReinterpI64asF64, e)); ++ return True; ++ } ++ ++ /* WFPCR */ ++ if (func == 0x51) { ++ IRExpr *e; ++ DIP("WFPCR f%u\n", fa); ++ ++ e = unop(Iop_ReinterpF64asI64, getFReg(fa)); ++ ++ /* clear bits other than rouding mode */ ++ e = binop(Iop_And64, mkU64(0xc00000000000000ULL), e); ++ ++ /* set exception trapping disable */ ++ e = binop(Iop_Or64, mkU64(0x600e000000000000ULL), e); ++ ++ stmt( IRStmt_Put(OFFB_FPCR, e) ); ++ return True; ++ } ++ ++ /* SETFPEC0 ~ SETFPEC3 */ ++ if (func >= 0x54 && func <= 0x57) { ++ DIP("SETFPEC%u\n", func - 0x54); ++ stmt(IRStmt_NoOp()); ++ return True; ++ } ++ ++ return False; ++} ++ ++static Bool dis_SW64_fpround(UInt func, UInt fb, UInt fc) ++{ ++ HChar const *nm; ++ UInt sz; ++ Int rm; ++ switch (func) { ++ case 0x5a: nm = "FRIS"; sz = 32; rm = -1; break; ++ case 0x5b: nm = "FRIS_G"; sz = 32; rm = Irrm_NEAREST; break; ++ case 0x5c: nm = "FRIS_P"; sz = 32; rm = Irrm_PosINF; break; ++ case 0x5d: nm = "FRIS_Z"; sz = 32; rm = Irrm_ZERO; break; ++ case 0x5f: nm = "FRIS_N"; sz = 32; rm = Irrm_NegINF; break; ++ case 0x60: nm = "FRID"; sz = 64; rm = -1; break; ++ case 0x61: nm = "FRID_G"; sz = 64; rm = Irrm_NEAREST; break; ++ case 0x62: nm = "FRID_P"; sz = 64; rm = Irrm_PosINF; break; ++ case 0x63: nm = "FRID_Z"; sz = 64; rm = Irrm_ZERO; break; ++ case 0x64: nm = "FRID_N"; sz = 64; rm = Irrm_NegINF; break; ++ default: return False; ++ } ++ ++ DIP("%s f%u, r%u\n", nm, fb, fc); ++ ++ IRTemp irrm; ++ if (rm == -1) { ++ irrm = mk_get_IR_rounding_mode(); ++ } else { ++ irrm = newTemp(Ity_I32); ++ assign(irrm, mkU32(rm)); ++ } ++ ++ IRExpr *e = binop(Iop_RoundF64toInt, mkexpr(irrm), getFReg(fb)); ++ ++ if (sz == 32) ++ e = binop(Iop_RoundF64toF32, mkexpr(irrm), e); ++ ++ putFReg(fc, e); ++ return True; ++} ++ ++static Bool dis_SW64_frec(UInt func, UInt fa, UInt fc) ++{ ++ HChar const *nm; ++ UInt sz; ++ ++ switch (func) { ++ case 0x58: nm = "FRECS"; sz = 32; break; ++ case 0x59: nm = "FRECD"; sz = 64; break; ++ default: return False; ++ } ++ ++ DIP("%s f%u, r%u\n", nm, fa, fc); ++ ++ IRExpr *e = triop(Iop_DivF64, mkU32(Irrm_ZERO), mkF64(1.0), getFReg(fa)); ++ if (sz == 32) ++ e = binop(Iop_RoundF64toF32, mkU32(Irrm_ZERO), e); ++ ++ putFReg(fc, e); ++ return True; ++} ++ ++static Bool dis_SW64_fma(UInt func, UInt fa, UInt fb, UInt fc, UInt fd) ++{ ++ IROp iop; ++ HChar const *nm; ++ Bool neg; ++ UInt sz; ++ switch (func) { ++ case 0x0: nm = "FMAS"; neg = False; iop = Iop_MAddF64; sz = 32; break; ++ case 0x1: nm = "FMAD"; neg = False; iop = Iop_MAddF64; sz = 64; break; ++ case 0x2: nm = "FMSS"; neg = False; iop = Iop_MSubF64; sz = 32; break; ++ case 0x3: nm = "FMSD"; neg = False; iop = Iop_MSubF64; sz = 64; break; ++ case 0x4: nm = "FNMAS"; neg = True; iop = Iop_MAddF64; sz = 32; break; ++ case 0x5: nm = "FNMAD"; neg = True; iop = Iop_MAddF64; sz = 64; break; ++ case 0x6: nm = "FNMSS"; neg = True; iop = Iop_MSubF64; sz = 32; break; ++ case 0x7: nm = "FNMSD"; neg = True; iop = Iop_MSubF64; sz = 64; break; ++ default: return False; ++ } ++ ++ DIP("%s f%u, f%u, f%u, f%u\n", nm, fa, fb, fc, fd); ++ ++ IRExpr *rav = getFReg(fa); ++ if (neg) ++ rav = unop(Iop_NegF64, rav); ++ ++ IRExpr *e = quaop(iop, ++ mkexpr(mk_get_IR_rounding_mode()), ++ rav, ++ getFReg(fb), ++ getFReg(fc)); ++ ++ if (sz == 32) ++ e = binop(Iop_RoundF64toF32, mkexpr(mk_get_IR_rounding_mode()), e); ++ ++ putFReg(fd, e); ++ return True; ++} ++ ++static Bool dis_SW64_fsel(UInt func, UInt fa, UInt fb, UInt fc, UInt fd) ++{ ++ IROp iop; ++ HChar const *nm; ++ switch (func) { ++ case 0x10: nm = "FSELEQ"; iop = Iop_CmpFEQ64; break; ++ case 0x11: nm = "FSELNE"; iop = Iop_CmpFNE64; break; ++ case 0x12: nm = "FSELLT"; iop = Iop_CmpFLT64; break; ++ case 0x13: nm = "FSELLE"; iop = Iop_CmpFLE64; break; ++ case 0x14: nm = "FSELGT"; iop = Iop_CmpFGT64; break; ++ case 0x15: nm = "FSELGE"; iop = Iop_CmpFGE64; break; ++ default: return False; ++ } ++ ++ DIP("%s f%u, f%u, f%u, f%u\n", nm, fa, fb, fc, fd); ++ ++ putFReg(fd, IRExpr_ITE(binop(iop, getFReg(fa), mkF64(0)), ++ getFReg(fb), ++ getFReg(fc))); ++ ++ return True; ++} ++ ++static Bool dis_SW64_lockload_fallback(UInt func, UInt ra, UInt rb, UInt disp) ++{ ++ IRType ty; ++ if (func == 0x0) { ++ DIP("LLDW r%u, 0x%x(r%u)\n", ra, disp, rb); ++ ty = Ity_I32; ++ } else if (func == 0x1) { ++ DIP("LLDL r%u, 0x%x(r%u)\n", ra, disp, rb); ++ ty = Ity_I64; ++ } else { ++ vassert(0); ++ } ++ ++ IRTemp vaddr = newTemp(Ity_I64); ++ assign(vaddr, binop(Iop_Add64, getIReg(rb), mkU64(disp))); ++ ++ IRTemp data = newTemp(Ity_I64); ++ if (ty == Ity_I32) ++ assign(data, unop(Iop_32Sto64, load(ty, mkexpr(vaddr)))); ++ else ++ assign(data, load(ty, mkexpr(vaddr))); ++ ++ /* ++ lock_valid <- 1 ++ lock_addr <- vaddr ++ lock_data <- data ++ lock_size <- 4 or 8 dependent on lldw or lldl ++ */ ++ stmt( IRStmt_Put(OFFB_LOCKVALID, mkU64(1)) ); ++ stmt( IRStmt_Put(OFFB_LOCKSIZE, mkU64(sizeofIRType(ty))) ); ++ stmt( IRStmt_Put(OFFB_LOCKADDR, mkexpr(vaddr)) ); ++ stmt( IRStmt_Put(OFFB_LOCKDATA, mkexpr(data)) ); ++ ++ /* changed in 8A (forward compatible with 6B): ++ lock_valid <- 1 */ ++ stmt( IRStmt_Put(OFFB_LOCKFLAG, mkU64(1)) ); ++ ++ putIReg(ra, mkexpr(data)); ++ return True; ++} ++ ++ ++static Bool dis_SW64_lockstore_fallback(UInt func, UInt ra, UInt rb, UInt disp) ++{ ++ /* ++ lock store go failed if any condition meet: ++ - state.lock_addr != lock_addr ++ - state.lock_size != lock_size ++ - state.lock_valid == 0 ++ - state.lock_flag == 0 ++ */ ++ ULong failaddr = guest_PC_curr_instr + 4; ++ ++ IRType ty; ++ if (func == 0x8) { ++ DIP("LSTW r%u, 0x%x(r%u)\n", ra, disp, rb); ++ ty = Ity_I32; ++ } else if (func == 0x9) { ++ DIP("LSTL r%u, 0x%x(r%u)\n", ra, disp, rb); ++ ty = Ity_I64; ++ } else { ++ vassert(0); ++ } ++ ++ IRTemp vaddr = newTemp(Ity_I64); ++ assign(vaddr, binop(Iop_Add64, getIReg(rb), mkU64(disp))); ++ ++ IRTemp storedata = newTemp(ty); ++ assign(storedata, narrowFrom64(ty, getIReg(ra))); ++ ++ /* set flags as failed first */ ++ stmt(IRStmt_Put(OFFB_LOCKSUCCESS, mkU64(0))); ++ /* Update Ra in 8A (not fully forward compatible to 6B) */ ++ putIReg(ra, mkU64(0)); ++ ++ condexit(binop(Iop_CmpEQ64, ++ IRExpr_Get(OFFB_LOCKVALID, Ity_I64), ++ mkU64(0)), failaddr); ++ ++ condexit(binop(Iop_CmpEQ64, ++ IRExpr_Get(OFFB_LOCKFLAG, Ity_I64), ++ mkU64(0)), failaddr); ++ ++ condexit(binop(Iop_CmpNE64, ++ IRExpr_Get(OFFB_LOCKSIZE, Ity_I64), ++ mkU64(sizeofIRType(ty))), failaddr); ++ ++ condexit(binop(Iop_CmpNE64, ++ IRExpr_Get(OFFB_LOCKADDR, Ity_I64), ++ mkexpr(vaddr)), failaddr); ++ ++ stmt( IRStmt_Put(OFFB_LOCKVALID, mkU64(0)) ); ++ stmt( IRStmt_Put(OFFB_LOCKFLAG, mkU64(0)) ); ++ ++ ++ // Try to CAS the new value in. ++ IRTemp old = newTemp(ty); ++ IRTemp expd = newTemp(ty); ++ assign(expd, narrowFrom64(ty, IRExpr_Get(OFFB_LOCKDATA, Ity_I64))); ++ stmt( IRStmt_CAS(mkIRCAS(IRTemp_INVALID, old, ++ Iend_LE, mkexpr(vaddr), ++ NULL, mkexpr(expd), ++ NULL, mkexpr(storedata) ++ ))); ++ ++ // Fail if the CAS failed (viz, old != expd) ++ condexit(binop(Iop_CmpNE64, ++ widenUto64(ty, mkexpr(old)), ++ widenUto64(ty, mkexpr(expd))), failaddr); ++ ++ // Otherwise we succeeded (!) ++ stmt( IRStmt_Put(OFFB_LOCKSUCCESS, mkU64(0x1)) ); ++ ++ /* Update Ra in 8A (not fully forward compatible to 6B) */ ++ putIReg(ra, mkU64(1)); ++ ++ return True; ++} ++ ++static Bool dis_SW64_memb_and_rtc_insn(UInt insn) ++{ ++ UInt func = extract(insn, 15, 0); ++ UInt ra = extract(insn, 25, 21); ++ ++ if (func == 0x0 || func == 0x1 || func == 0x2) { ++ /* there is only IRStmt_MBE(Imbe_Fence) in VEX IR. ++ All SW MEMB is convert to IRStmt_MBE(Imbe_Fence) */ ++ const HChar *nm = (func == 0x0) ? "MEMB" : ++ (func == 0x1) ? "IMEMB" : ++ (func == 0x2) ? "WMEMB" : ++ (vassert(0), NULL); ++ DIP("%s\n", nm); ++ stmt(IRStmt_MBE(Imbe_Fence)); ++ return True; ++ } ++ ++ if (func == 0x20) { ++ DIP("RTC r%u\n", ra); ++ IRDirty *d; ++ IRTemp v0 = newTemp(Ity_I64); ++ d = unsafeIRDirty_1_N(v0, 0, ++ "sw64_dirtyhelper_rtc", ++ &sw64_dirtyhelper_rtc, ++ mkIRExprVec_1(IRExpr_GSPTR())); ++ d->nFxState = 1; ++ vex_bzero(&d->fxState, sizeof(d->fxState)); ++ d->fxState[0].fx = Ifx_Read; /* read */ ++ d->fxState[0].offset = offsetof(VexGuestSW64State, guest_r0); ++ d->fxState[0].size = sizeof(ULong); ++ stmt(IRStmt_Dirty(d)); ++ putIReg(ra, mkexpr(v0)); ++ return True; ++ } ++ ++ if (func == 0x40) { ++ DIP("RCID r%u\n", ra); ++ IRDirty *d; ++ IRTemp v0 = newTemp(Ity_I64); ++ d = unsafeIRDirty_1_N(v0, 0, ++ "sw64_dirtyhelper_rcid", ++ &sw64_dirtyhelper_rcid, ++ mkIRExprVec_1(IRExpr_GSPTR())); ++ d->nFxState = 1; ++ vex_bzero(&d->fxState, sizeof(d->fxState)); ++ d->fxState[0].fx = Ifx_Read; /* read */ ++ d->fxState[0].offset = offsetof(VexGuestSW64State, guest_r0); ++ d->fxState[0].size = sizeof(ULong); ++ stmt(IRStmt_Dirty(d)); ++ putIReg(ra, mkexpr(v0)); ++ return True; ++ } ++ ++ if (func == 0x80) { ++ DIP("HALT\n"); ++ stmt(IRStmt_NoOp()); /* HALT is ignored */ ++ return True; ++ } ++ ++ if (func == 0x1000) { ++ DIP("RD_F r%u\n", ra); ++ putIReg(ra, IRExpr_Get(OFFB_LOCKSUCCESS, Ity_I64)); ++ return True; ++ } ++ ++ if (func == 0x1020) { ++ DIP("WR_F r%u\n", ra); ++ stmt(IRStmt_Put(OFFB_LOCKFLAG, getIReg(ra))); ++ return True; ++ } ++ ++ if (func == 0x1040) { ++ DIP("RTID r%u\n", ra); ++ putIReg(ra, IRExpr_Get(OFFB_TID, Ity_I64)); ++ return True; ++ } ++ ++ if (func >= 0xfc00 && func <= 0xffff) { ++ DIP("CSRWS/CSRWC/CSRR/CSRW (privilege, go failed)\n"); ++ return False; ++ } ++ ++ return False; ++} ++ ++static Bool dis_SW64_prefetch(UInt insn) ++{ ++ UInt opcode = extract(insn, 31, 26); ++ UInt ra = extract(insn, 25, 21); ++ UInt rb = extract(insn, 20, 16); ++ UInt disp = extract(insn, 15, 0); ++ ++ HChar const *nm; ++ switch (opcode) { ++ case 0x22: nm = "S_FILLCS"; break; /* S_FILLCS: LDW */ ++ case 0x23: nm = "S_FILLDE"; break; /* S_FILLDE: LDL */ ++ case 0x26: nm = "FILLDE"; break; /* FILLDE: FLDS */ ++ case 0x27: nm = "FILLDE_E"; break; /* FILLDE_E: FLDD */ ++ case 0x9: nm = "FILLCS"; break; /* FILLCS: LDWE */ ++ case 0xB: nm = "FILLCS_E"; break; /* FILLCS_E: LDDE */ ++ case 0xA: nm = "E_FILLCS"; break; /* E_FILLCS: LDSE */ ++ case 0xC: nm = "E_FILLDE"; break; /* E_FILLDE: VLDS */ ++ case 0x20: nm = "FLUSHD"; break; /* FLUSHD: LDBU */ ++ case 0x24: nm = "EVICTDL"; break; /* EVICTDL: LDL_U */ ++ case 0x21: nm = "EVICTDG"; break; /* EVICTDG: LDHU */ ++ case 0x1E: { ++ UInt func = extract(insn, 15, 12); ++ nm = (func == 0xE) ? "DPFHR" : ++ (func == 0xF) ? "DPFHR" : ++ (vassert(0), NULL); ++ disp = extract(insn, 11, 0); ++ break; ++ } ++ default: return False; ++ } ++ ++ vassert(ra == 31); ++ ++ DIP("%s %x(r%u) (prefetch)\n", nm, disp, rb); ++ stmt(IRStmt_NoOp()); /* can't do anything with prefetch */ ++ ++ return True; ++} ++ ++static Bool dis_SW64_cas(UInt opcode, UInt func, UInt ra, UInt rb, ++ UInt rc) ++{ ++ HChar const *nm; ++ IRType ty; ++ switch (func) { ++ case 0x5E: ty = Ity_I32; nm = "CASW"; break; ++ case 0x5F: ty = Ity_I64; nm = "CASL"; break; ++ default: return False; ++ } ++ ++ DIP("%s r%u r%u r%u\n", nm, ra, rb, rc); ++ ++ IRTemp old = newTemp(ty); ++ IRExpr *exp = getIReg(ra); ++ IRExpr *addr = getIReg(rb); ++ IRExpr *data = getIReg(rc); ++ ++ if (ty == Ity_I32) { ++ data = unop(Iop_64to32, data); ++ exp = unop(Iop_64to32, exp); ++ } ++ ++ stmt(IRStmt_CAS(mkIRCAS(IRTemp_INVALID, old, Iend_LE, addr, NULL, exp, NULL, data))); ++ ++ if (ty == Ity_I32) { ++ putIReg(rc, unop(Iop_32Sto64, mkexpr(old))); ++ } else { ++ putIReg(rc, mkexpr(old)); ++ } ++ ++ return True; ++} ++ ++/* Spot "Special" instructions (see valgrind.h). */ ++static Bool handle_special_instr(DisResult* dres) ++{ ++ const UChar* code = (const UChar *)guest_PC_curr_instr; ++ ++ /* 16-bytes preamble: ++ 4BE0691F sll $31,3, $31 ++ 4BE1A91F sll $31,13,$31 ++ 4BE3A91F sll $31,29,$31 ++ 4BE2691F sll $31,19,$31 ++ */ ++ if (fetch32(code + 0) != 0x4BE0691F) ++ return False; ++ if (fetch32(code + 4) != 0x4BE1A91F) ++ return False; ++ if (fetch32(code + 8) != 0x4BE3A91F) ++ return False; ++ if (fetch32(code + 12) != 0x4BE2691F) ++ return False; ++ ++ /* 4-bytes type: ++ r4 = client_request ( r5 ): ++ 40C60746 bis $6, $6, $6 ++ ++ r4 = guest_NRADDR: ++ 40E70747 bis $7, $7, $7 ++ ++ branch-and-link-to-noredir r27: ++ 41080748 bis $8, $8, $8 ++ ++ IR injection: ++ 40840744 bis $4, $4, $4 ++ */ ++ UInt type = fetch32(code + 16); ++ ++ if (type == 0x40C60746) { ++ DIP("r4 = client_request ( r5 )\n"); ++ putPC(mkU64( guest_PC_curr_instr + 20 )); ++ dres->len = 20; ++ dres->jk_StopHere = Ijk_ClientReq; ++ dres->whatNext = Dis_StopHere; ++ return True; ++ } ++ ++ if (type == 0x40E70747) { ++ DIP("r4 = guest_NRADDR\n"); ++ putIReg(4, IRExpr_Get( OFFB_NRADDR, Ity_I64 )); ++ dres->len = 20; ++ dres->jk_StopHere = Ijk_INVALID; ++ dres->whatNext = Dis_Continue; ++ return True; ++ } ++ ++ if (type == 0x41080748) { ++ DIP("branch-and-link-to-noredir r27\n"); ++ putIReg(26, mkU64(guest_PC_curr_instr + 20)); ++ putPC(getIReg(27)); ++ dres->len = 20; ++ dres->jk_StopHere = Ijk_NoRedir; ++ dres->whatNext = Dis_StopHere; ++ return True; ++ } ++ ++ if (type == 0x40840744) { ++ DIP("IR injection\n"); ++ vex_inject_ir(irsb, Iend_LE); ++ // Invalidate the current insn. The reason is that the IRop we're ++ // injecting here can change. In which case the translation has to ++ // be redone. For ease of handling, we simply invalidate all the ++ // time. ++ stmt(IRStmt_Put(OFFB_CMSTART, mkU64(guest_PC_curr_instr))); ++ stmt(IRStmt_Put(OFFB_CMLEN, mkU64(20))); ++ putPC(mkU64( guest_PC_curr_instr + 20 )); ++ dres->len = 20; ++ dres->whatNext = Dis_StopHere; ++ dres->jk_StopHere = Ijk_InvalICache; ++ return True; ++ } ++ ++ return False; ++} ++ ++ ++/*------------------------------------------------------------*/ ++/*--- Disassemble a single SW64 instruction ---*/ ++/*------------------------------------------------------------*/ ++ ++/* Disassemble a single SW64 instruction into IR. The instruction ++ has is located at |guest_instr| and has guest IP of ++ |guest_PC_curr_instr|, which will have been set before the call ++ here. Returns True iff the instruction was decoded, in which case ++ *dres will be set accordingly, or False, in which case *dres should ++ be ignored by the caller. */ ++ ++static ++Bool disInstr_SW64_WRK ( ++ /*MB_OUT*/DisResult* dres, ++ const UChar* guest_instr, ++ const VexArchInfo* archinfo, ++ const VexAbiInfo* abiinfo, ++ Bool sigill_diag ++ ) ++{ ++ /* At least this is simple on SW64: insns are all 4 bytes long, and ++ 4-aligned. So just fish the whole thing out of memory right now ++ and have done. */ ++ UInt insn = fetch32( guest_instr ); ++ ++ DIP("\t(sw64) 0x%llx: ", (ULong)guest_PC_curr_instr); ++ ++ if (handle_special_instr(dres)) { ++ return True; ++ } ++ ++ /* Main SW64 instruction decoder starts here. */ ++ ++ UInt opcode = extract(insn, 31, 26); ++ ++ switch (opcode) { ++ /* SYSCALL */ ++ case 0x0: { ++ return dis_SW64_syscall(dres, insn); ++ } ++ ++ /* CALL RET JMP */ ++ case 0x1: ++ case 0x2: ++ case 0x3: { ++ return dis_SW64_jump(dres, insn); ++ } ++ ++ /* BR BSR */ ++ case 0x4: ++ case 0x5: ++ /* LBR */ ++ case 0x1D: ++ /* BEQ BNE BLT BLE BGT BGE BLBC BLBS */ ++ case 0x30: ++ case 0x31: ++ case 0x32: ++ case 0x33: ++ case 0x34: ++ case 0x35: ++ case 0x36: ++ case 0x37: ++ /* FBEQ FBNE FBLT FBLE FBGT FBGE */ ++ case 0x38: ++ case 0x39: ++ case 0x3A: ++ case 0x3B: ++ case 0x3C: ++ case 0x3D: { ++ return dis_SW64_branch(dres, insn); ++ } ++ ++ case 0x6: { ++ return dis_SW64_memb_and_rtc_insn(insn); ++ } ++ ++ /* LL/SC ATOM NC*/ ++ case 0x8: { ++ UInt ra = extract(insn, 25,21); ++ UInt rb = extract(insn, 20,16); ++ UInt func = extract(insn, 15,12); ++ UInt disp = extract(insn, 11,0); ++ ++ switch (func) { ++ /* LLDW LLDL */ ++ case 0x0: ++ case 0x1: { ++ return dis_SW64_lockload_fallback(func, ra, rb, disp); ++ } ++ ++ /* LSTW LSTL */ ++ case 0x8: ++ case 0x9: { ++ return dis_SW64_lockstore_fallback(func, ra, rb, disp); ++ } ++ ++ /* LDW_INC LDL_INC LDW_DEC LDL_DEC LDW_SET LDL_SET */ ++ case 0x2: ++ case 0x3: ++ case 0x4: ++ case 0x5: ++ case 0x6: ++ case 0x7: { ++ /* Removed in SW6B */ ++ return False; ++ } ++ ++ /* LDW_NC LDL_NC LDD_NC */ ++ case 0xA: ++ case 0xB: ++ case 0xC: { ++ return dis_SW64_nc_load(func, ra, rb, disp); ++ } ++ ++ /* STW_NC STL_NC STD_NC */ ++ case 0xD: ++ case 0xE: ++ case 0xF: { ++ return dis_SW64_nc_store(func, ra, rb, disp); ++ } ++ ++ default: { ++ return False; ++ } ++ } ++ } ++ ++ /* LDWE LDSE LDDE VLDS VLDD */ ++ case 0x9: ++ case 0xA: ++ case 0xB: ++ case 0xC: ++ case 0xD: { ++ UInt ra = extract(insn, 25, 21); ++ if (ra == 31) ++ return dis_SW64_prefetch(insn); ++ else ++ return False; /* TODO: SW64_SIMD */ ++ } ++ ++ /* VSTS VSTD */ ++ case 0xE: ++ case 0xF: { ++ return False; /* TODO: SW64_SIMD */ ++ } ++ ++ /* integer arthimetics: 3 register */ ++ case 0x10: ++ /* integer arthimetics: 2 register + 1 imm */ ++ case 0x12: { ++ UInt ra = extract(insn, 25, 21); ++ UInt rb = extract(insn, 20, 16); ++ UInt imm = extract(insn, 20, 13); ++ UInt func = extract(insn, 12, 5); ++ UInt rc = extract(insn, 4, 0); ++ ++ switch (func) { ++ /* ADDW SUBW S4ADDW S4SUBW S8ADDW S8SUBW */ ++ case 0x0: ++ case 0x1: ++ case 0x2: ++ case 0x3: ++ case 0x4: ++ case 0x5: ++ /* ADDW SUBW S4ADDW S4SUBW S8ADDW S8SUBW */ ++ case 0x8: ++ case 0x9: ++ case 0xA: ++ case 0xB: ++ case 0xC: ++ case 0xD: { ++ return dis_SW64_integer_add_sub(opcode, func, ra, rb, rc, imm); ++ } ++ ++ case 0x10: ++ case 0x18: ++ case 0x19: { ++ return dis_SW64_integer_mul(opcode, func, ra, rb, rc, imm); ++ } ++ ++ case 0x11: ++ case 0x12: ++ case 0x13: ++ case 0x14: ++ case 0x1A: ++ case 0x1B: ++ case 0x1C: ++ case 0x1D: { ++ if (opcode == 0x12) { ++ /* no immediate variant */ ++ return False; ++ } ++ return dis_SW64_integer_div(func, ra, rb, rc); ++ } ++ ++ case 0x1E: ++ case 0x1F: { ++ if (opcode == 0x10) { ++ /* only immediate variant, and used 0x10 as opcode */ ++ return dis_SW64_addpi(func, rc, extract(insn, 25, 13)); ++ } ++ return False; ++ } ++ ++ case 0x20: ++ case 0x21: ++ case 0x22: ++ case 0x23: ++ case 0x24: ++ case 0x25: ++ case 0x26: ++ case 0x27: { ++ if (opcode == 0x12) { ++ /* no immediate variant */ ++ return False; ++ } ++ return dis_SW64_crc32(func, ra, rb, rc); ++ } ++ ++ case 0x28: ++ case 0x29: ++ case 0x2A: ++ case 0x2B: ++ case 0x2C: { ++ return dis_SW64_integer_cmp(opcode, func, ra, rb, rc, imm); ++ } ++ ++ case 0x2D: ++ case 0x2E: { ++ return dis_SW64_bit_setclear(opcode, func, ra, rb, rc, imm); ++ } ++ ++ case 0x38: ++ case 0x39: ++ case 0x3A: ++ case 0x3B: ++ case 0x3C: ++ case 0x3D: { ++ return dis_SW64_bits_logical(opcode, func, ra, rb, rc, imm); ++ } ++ ++ case 0x40: ++ case 0x41: ++ case 0x42: ++ case 0x43: ++ case 0x44: ++ case 0x45: ++ case 0x46: ++ case 0x47: { ++ return dis_SW64_bits_insert(opcode, func, ra, rb, rc, imm); ++ } ++ ++ case 0x48: ++ case 0x49: ++ case 0x4A: ++ case 0x4B: ++ case 0x4C: ++ case 0x4D: ++ case 0x4E: ++ case 0x4F: { ++ return dis_SW64_bits_shift(opcode, func, ra, rb, rc, imm); ++ } ++ ++ case 0x50: ++ case 0x51: ++ case 0x52: ++ case 0x53: ++ case 0x54: ++ case 0x55: ++ case 0x56: ++ case 0x57: { ++ return dis_SW64_bits_extract(opcode, func, ra, rb, rc, imm); ++ } ++ ++ case 0x58: ++ case 0x59: ++ case 0x5A: { ++ return dis_SW64_bits_pop(opcode, func, ra, rb, rc, imm); ++ } ++ ++ case 0x5B: ++ case 0x5C: ++ case 0x5D: { ++ if (opcode == 0x12) { ++ /* no immediate variant */ ++ return False; ++ } ++ return dis_SW64_byte_swap(func, rb, rc); ++ } ++ ++ case 0x5E: ++ case 0x5F: { ++ return dis_SW64_cas(opcode, func, ra, rb, rc); ++ } ++ ++ case 0x60: ++ case 0x61: ++ case 0x62: ++ case 0x63: ++ case 0x64: ++ case 0x65: ++ case 0x66: ++ case 0x67: { ++ return dis_SW64_bits_mask(opcode, func, ra, rb, rc, imm); ++ } ++ ++ case 0x68: ++ case 0x69: ++ case 0x6A: ++ case 0x6B: ++ case 0x6C: { ++ return dis_SW64_bits_zap(opcode, func, ra, rb, rc, imm); ++ } ++ ++ case 0x70: ++ case 0x78: { ++ return dis_SW64_intflt_transfer(opcode, func, ra, rc); ++ } ++ ++ case 0x72: ++ case 0x74: ++ case 0x7a: ++ case 0x7c: ++ case 0x80: ++ case 0x81: ++ case 0x82: ++ case 0x83: ++ case 0x84: ++ case 0x85: ++ case 0x86: ++ case 0x87: ++ case 0x88: ++ case 0x89: ++ case 0x8a: ++ case 0x8b: ++ case 0x8c: ++ case 0x8d: ++ case 0x8e: ++ case 0x8f: { ++ return dis_SW64_fltint_convert(opcode, func, rb, rc); ++ } ++ ++ default: { ++ return False; ++ } ++ } ++ } ++ ++ /* SELxx */ ++ case 0x11: ++ /* SELIxx*/ ++ case 0x13: { ++ return dis_SW64_sel(insn); ++ } ++ ++ /* VLOGzz */ ++ case 0x14: ++ case 0x15: ++ case 0x16: ++ case 0x17: { ++ return False; /* TODO: SW64_SIMD */ ++ } ++ ++ /* float calculation - 3 register */ ++ case 0x18: { ++ UInt func = extract(insn, 12, 5); ++ UInt fa = extract(insn, 25, 21); ++ UInt fb = extract(insn, 20, 16); ++ UInt fc = extract(insn, 4, 0); ++ switch (func) { ++ /* FADDS FADDD FSUBS FSUBD */ ++ case 0x0: ++ case 0x1: ++ case 0x2: ++ case 0x3: ++ /* FMULS FMULD FDIVS FDIVD */ ++ case 0x4: ++ case 0x5: ++ case 0x6: ++ case 0x7: { ++ return dis_SW64_float_arith(func, fa, fb, fc); ++ } ++ ++ /* FSQRTS FSQRTD */ ++ case 0x8: ++ case 0x9: { ++ return dis_SW64_fsqrt(func, fb, fc); ++ } ++ ++ /* FCMPEQ FCMPLE FCMPLT FCMPUN */ ++ case 0x10: ++ case 0x11: ++ case 0x12: ++ case 0x13: { ++ return dis_SW64_fcmp(func, fa, fb, fc); ++ } ++ ++ /* FCVTSD FCVTDS */ ++ case 0x20: ++ case 0x21: ++ /* FCVTDL_G FCVTDL_P FCVTDL_Z FCVTDL_N */ ++ case 0x22: ++ case 0x23: ++ case 0x24: ++ case 0x25: ++ /* FCVTDL FCVTWL FCVTLW */ ++ case 0x27: ++ case 0x28: ++ case 0x29: ++ /* FCVTLS FCVTLD */ ++ case 0x2D: ++ case 0x2F: { ++ return dis_SW64_fcvt(func, fb, fc); ++ } ++ ++ /* FCPYS FCPYSE FCPYSN */ ++ case 0x30: ++ case 0x31: ++ case 0x32: { ++ return dis_SW64_fcpy(func, fa, fb, fc); ++ } ++ ++ /* IFMOVS IFMOVD */ ++ case 0x40: ++ case 0x41: { ++ return dis_SW64_intflt_transfer(opcode, func, fa, fc); ++ } ++ ++ /* CMOVLS CMOVWS CMOVLD CMOVWD CMOVULS CMOVUWS CMOVULD CMOVUWD */ ++ case 0x48: ++ case 0x49: ++ case 0x4a: ++ case 0x4b: ++ case 0x4c: ++ case 0x4d: ++ case 0x4e: ++ case 0x4f: { ++ return dis_SW64_intflt_convert(opcode, func, fb, fc); ++ } ++ ++ /* RFPCR WFPCR SETFPEC0 SETFPEC1 SETFPEC2 SETFPEC3 */ ++ case 0x50: ++ case 0x51: ++ case 0x54: ++ case 0x55: ++ case 0x56: ++ case 0x57: { ++ return dis_SW64_fpcr(insn, func); ++ } ++ ++ /* FRECS FRECD */ ++ case 0x58: ++ case 0x59: { ++ return dis_SW64_frec(func, fa, fc); ++ } ++ ++ /* FRIS FRID FRIS_x FRID_x */ ++ case 0x5a: ++ case 0x5b: ++ case 0x5c: ++ case 0x5d: ++ case 0x5f: ++ case 0x60: ++ case 0x61: ++ case 0x62: ++ case 0x63: ++ case 0x64: { ++ return dis_SW64_fpround(func, fb, fc); ++ } ++ ++ default: { ++ return False; ++ } ++ } /* switch (func) */ ++ } ++ ++ /* float calculation - 4 register */ ++ case 0x19: { ++ UInt func = extract(insn, 15, 10); ++ UInt fa = extract(insn, 25, 21); ++ UInt fb = extract(insn, 20, 16); ++ UInt fc = extract(insn, 9, 5); ++ UInt fd = extract(insn, 4, 0); ++ switch (func) { ++ /* FMAS FMAD FMSS FMSD */ ++ case 0x0: ++ case 0x1: ++ case 0x2: ++ case 0x3: ++ /* FNMAS FNMAD FNMSS FNMSD */ ++ case 0x4: ++ case 0x5: ++ case 0x6: ++ case 0x7: { ++ return dis_SW64_fma(func, fa, fb, fc, fd); ++ } ++ ++ /* FSELEQ FSELNE FSELLT FSELLE FSELGT FSELGE */ ++ case 0x10: ++ case 0x11: ++ case 0x12: ++ case 0x13: ++ case 0x14: ++ case 0x15: { ++ return dis_SW64_fsel(func, fa, fb, fc, fd); ++ } ++ ++ default: { ++ return False; ++ } ++ } ++ } ++ ++ /* SIMD calculation - 3 register */ ++ case 0x1A: { ++ return False; /* TODO: SW64_SIMD */ ++ } ++ ++ /* SIMD calculation - 4 register */ ++ case 0x1B: { ++ return False; /* TODO: SW64_SIMD */ ++ } ++ ++ /* SIMD load/store - with function code */ ++ case 0x1C: { ++ return False; /* TODO: SW64_SIMD */ ++ } ++ ++ /* scalar load/store - with auto address increasing */ ++ case 0x1E: { ++ UInt ra = extract(insn, 25, 21); ++ UInt rb = extract(insn, 20, 16); ++ UInt func = extract(insn, 15, 12); ++ UInt disp = extract(insn, 11, 0); ++ switch (func) { ++ case 0x0: ++ case 0x1: ++ case 0x2: ++ case 0x3: { ++ return dis_SW64_integer_load(func, ra, rb, disp, True); ++ } ++ case 0x4: ++ case 0x5: { ++ return dis_SW64_float_load(func, ra, rb, disp, True); ++ } ++ case 0x6: ++ case 0x7: ++ case 0x8: ++ case 0x9: { ++ return dis_SW64_integer_store(func, ra, rb, disp, True); ++ } ++ case 0xA: ++ case 0xB: { ++ return dis_SW64_float_store(func, ra, rb, disp, True); ++ } ++ case 0xE: ++ case 0xF: { ++ return dis_SW64_prefetch(insn); ++ } ++ default: return False; ++ } ++ } ++ ++ /* LDBU LDHU LDW LDL LDL_U */ ++ case 0x20: ++ case 0x21: ++ case 0x22: ++ case 0x23: ++ case 0x24: { ++ UInt ra = extract(insn, 25, 21); ++ UInt rb = extract(insn, 20, 16); ++ UInt disp = extract(insn, 15, 0); ++ if (ra == 31) ++ return dis_SW64_prefetch(insn); ++ else ++ return dis_SW64_integer_load(opcode, ra, rb, disp, False); ++ } ++ ++ /* PRI_RET PRI_LD PRI_ST */ ++ case 0x7: ++ case 0x25: ++ case 0x2D: { ++ /* */ ++ return False; ++ } ++ ++ /* FLDS FLDD */ ++ case 0x26: ++ case 0x27: { ++ UInt fa = extract(insn, 25, 21); ++ UInt rb = extract(insn, 20, 16); ++ UInt disp = extract(insn, 15, 0); ++ if (fa == 31) ++ return dis_SW64_prefetch(insn); ++ else ++ return dis_SW64_float_load(opcode, fa, rb, disp, False); ++ } ++ ++ /* STB STH STW STL STL_U */ ++ case 0x28: ++ case 0x29: ++ case 0x2A: ++ case 0x2B: ++ case 0x2C: { ++ UInt ra = extract(insn, 25, 21); ++ UInt rb = extract(insn, 20, 16); ++ UInt disp = extract(insn, 15, 0); ++ return dis_SW64_integer_store(opcode, ra, rb, disp, False); ++ } ++ ++ /* FSTS FSTD */ ++ case 0x2E: ++ case 0x2F: { ++ UInt fa = extract(insn, 25, 21); ++ UInt rb = extract(insn, 20, 16); ++ UInt disp = extract(insn, 15, 0); ++ return dis_SW64_float_store(opcode, fa, rb, disp, False); ++ } ++ ++ /* LDI LDIH */ ++ case 0x3E: ++ case 0x3F: { ++ return dis_SW64_load_imm(dres, insn); ++ } ++ ++ default: { ++ return False; ++ } ++ } ++} ++ ++ ++/*------------------------------------------------------------*/ ++/*--- Top-level fn ---*/ ++/*------------------------------------------------------------*/ ++ ++/* Disassemble a single instruction into IR. The instruction ++ is located in host memory at &guest_code[delta]. */ ++ ++DisResult disInstr_SW64 ( IRSB* irsb_IN, ++ const UChar* guest_code_IN, ++ Long delta_IN, ++ Addr guest_IP, ++ VexArch guest_arch, ++ const VexArchInfo* archinfo, ++ const VexAbiInfo* abiinfo, ++ VexEndness host_endness_IN, ++ Bool sigill_diag_IN ) ++{ ++ DisResult dres; ++ vex_bzero(&dres, sizeof(dres)); ++ ++ /* Set globals (see top of this file) */ ++ vassert(guest_arch == VexArchSW64); ++ ++ /* instructions should already aligned to 4-bytes in guest memory */ ++ vassert(0 == (guest_IP & 3ULL)); ++ ++ irsb = irsb_IN; ++ host_endness = host_endness_IN; ++ guest_PC_curr_instr = (Addr64)guest_IP; ++ ++ dres.len = 4; ++ dres.jk_StopHere = Ijk_INVALID; ++ dres.whatNext = Dis_Continue; ++ dres.hint = Dis_HintNone; ++ ++ /* Try to decode */ ++ Bool ok = disInstr_SW64_WRK( &dres, ++ &guest_code_IN[delta_IN], ++ archinfo, abiinfo, sigill_diag_IN ); ++ ++ if (ok) { ++ /* All decode successes end up here. */ ++ vassert(dres.len == 4 || dres.len == 20); ++ switch (dres.whatNext) { ++ case Dis_Continue: ++ putPC( mkU64(dres.len + guest_PC_curr_instr) ); ++ break; ++ case Dis_StopHere: ++ break; ++ default: ++ vassert(0); ++ } ++ DIP("\n"); ++ } else { ++ /* All decode failures end up here. */ ++ if (sigill_diag_IN) { ++ vex_printf("disInstr(sw64): unhandled instruction: %02x %02x %02x %02x (opcode: %x)\n", ++ guest_code_IN[delta_IN + 0], ++ guest_code_IN[delta_IN + 1], ++ guest_code_IN[delta_IN + 2], ++ guest_code_IN[delta_IN + 3], ++ ((UInt)guest_code_IN[delta_IN + 3]) >> 2); ++ } ++ ++ /* Tell the dispatcher that this insn cannot be decoded, and so ++ has not been executed, and (is currently) the next to be ++ executed. PC should be up-to-date since it is made so at the ++ start of each insn, but nevertheless be paranoid and update ++ it again right now. */ ++ putPC( mkU64(guest_PC_curr_instr) ); ++ dres.len = 0; ++ dres.whatNext = Dis_StopHere; ++ dres.jk_StopHere = Ijk_NoDecode; ++ } ++ return dres; ++} ++ ++ ++/*--------------------------------------------------------------------*/ ++/*--- end guest_sw64_toIR.c ---*/ ++/*--------------------------------------------------------------------*/ +diff --git a/VEX/priv/host_amd64_defs.c b/VEX/priv/host_amd64_defs.c +index 69afab739..4dbff80ae 100644 +--- a/VEX/priv/host_amd64_defs.c ++++ b/VEX/priv/host_amd64_defs.c +@@ -2529,7 +2529,7 @@ static UChar* do_ffree_st ( UChar* p, Int n ) + instruction was a profiler inc, set *is_profInc to True, else + leave it unchanged. */ + +-Int emit_AMD64Instr ( /*MB_MOD*/Bool* is_profInc, ++Int emit_AMD64Instr ( /*MB_MOD*/Bool* is_profInc, /*MB_MOD*/Bool* is_8aligned, + UChar* buf, Int nbuf, const AMD64Instr* i, + Bool mode64, VexEndness endness_host, + const void* disp_cp_chain_me_to_slowEP, +diff --git a/VEX/priv/host_amd64_defs.h b/VEX/priv/host_amd64_defs.h +index e2ed2613b..25a9f57c0 100644 +--- a/VEX/priv/host_amd64_defs.h ++++ b/VEX/priv/host_amd64_defs.h +@@ -814,7 +814,7 @@ extern void ppAMD64Instr ( const AMD64Instr*, Bool ); + of the underlying instruction set. */ + extern void getRegUsage_AMD64Instr ( HRegUsage*, const AMD64Instr*, Bool ); + extern void mapRegs_AMD64Instr ( HRegRemap*, AMD64Instr*, Bool ); +-extern Int emit_AMD64Instr ( /*MB_MOD*/Bool* is_profInc, ++extern Int emit_AMD64Instr ( /*MB_MOD*/Bool* is_profInc, /*MB_MOD*/Bool* is_8aligned, + UChar* buf, Int nbuf, + const AMD64Instr* i, + Bool mode64, +diff --git a/VEX/priv/host_arm64_defs.c b/VEX/priv/host_arm64_defs.c +index 39c6aaa46..f4a083744 100644 +--- a/VEX/priv/host_arm64_defs.c ++++ b/VEX/priv/host_arm64_defs.c +@@ -3621,7 +3621,7 @@ static UInt* do_load_or_store64 ( UInt* p, + instruction was a profiler inc, set *is_profInc to True, else + leave it unchanged. */ + +-Int emit_ARM64Instr ( /*MB_MOD*/Bool* is_profInc, ++Int emit_ARM64Instr ( /*MB_MOD*/Bool* is_profInc, /*MB_MOD*/Bool* is_8aligned, + UChar* buf, Int nbuf, const ARM64Instr* i, + Bool mode64, VexEndness endness_host, + const void* disp_cp_chain_me_to_slowEP, +diff --git a/VEX/priv/host_arm64_defs.h b/VEX/priv/host_arm64_defs.h +index dc686dff7..6fadcf5d9 100644 +--- a/VEX/priv/host_arm64_defs.h ++++ b/VEX/priv/host_arm64_defs.h +@@ -1109,7 +1109,7 @@ extern void ppARM64Instr ( const ARM64Instr* ); + of the underlying instruction set. */ + extern void getRegUsage_ARM64Instr ( HRegUsage*, const ARM64Instr*, Bool ); + extern void mapRegs_ARM64Instr ( HRegRemap*, ARM64Instr*, Bool ); +-extern Int emit_ARM64Instr ( /*MB_MOD*/Bool* is_profInc, ++extern Int emit_ARM64Instr ( /*MB_MOD*/Bool* is_profInc, /*MB_MOD*/Bool* is_8aligned, + UChar* buf, Int nbuf, const ARM64Instr* i, + Bool mode64, + VexEndness endness_host, +diff --git a/VEX/priv/host_arm_defs.c b/VEX/priv/host_arm_defs.c +index 6f972a41b..a29ca38a6 100644 +--- a/VEX/priv/host_arm_defs.c ++++ b/VEX/priv/host_arm_defs.c +@@ -3067,7 +3067,7 @@ static UInt* do_load_or_store32 ( UInt* p, + instruction was a profiler inc, set *is_profInc to True, else + leave it unchanged. */ + +-Int emit_ARMInstr ( /*MB_MOD*/Bool* is_profInc, ++Int emit_ARMInstr ( /*MB_MOD*/Bool* is_profInc, /*MB_MOD*/Bool* is_8aligned, + UChar* buf, Int nbuf, const ARMInstr* i, + Bool mode64, VexEndness endness_host, + const void* disp_cp_chain_me_to_slowEP, +diff --git a/VEX/priv/host_arm_defs.h b/VEX/priv/host_arm_defs.h +index 0f4b51951..32bf07407 100644 +--- a/VEX/priv/host_arm_defs.h ++++ b/VEX/priv/host_arm_defs.h +@@ -1054,7 +1054,7 @@ extern void ppARMInstr ( const ARMInstr* ); + of the underlying instruction set. */ + extern void getRegUsage_ARMInstr ( HRegUsage*, const ARMInstr*, Bool ); + extern void mapRegs_ARMInstr ( HRegRemap*, ARMInstr*, Bool ); +-extern Int emit_ARMInstr ( /*MB_MOD*/Bool* is_profInc, ++extern Int emit_ARMInstr ( /*MB_MOD*/Bool* is_profInc, /*MB_MOD*/Bool* is_8aligned, + UChar* buf, Int nbuf, const ARMInstr* i, + Bool mode64, + VexEndness endness_host, +diff --git a/VEX/priv/host_mips_defs.c b/VEX/priv/host_mips_defs.c +index 5af3b8565..8f0487f22 100644 +--- a/VEX/priv/host_mips_defs.c ++++ b/VEX/priv/host_mips_defs.c +@@ -3765,7 +3765,7 @@ static UChar *mkMoveReg(UChar * p, UInt r_dst, UInt r_src) + imperative to emit position-independent code. If the emitted + instruction was a profiler inc, set *is_profInc to True, else + leave it unchanged. */ +-Int emit_MIPSInstr ( /*MB_MOD*/Bool* is_profInc, ++Int emit_MIPSInstr ( /*MB_MOD*/Bool* is_profInc,/*MB_MOD*/Bool* is_8aligned, + UChar* buf, Int nbuf, const MIPSInstr* i, + Bool mode64, + VexEndness endness_host, +diff --git a/VEX/priv/host_mips_defs.h b/VEX/priv/host_mips_defs.h +index 96ab2f9a4..326af2c60 100644 +--- a/VEX/priv/host_mips_defs.h ++++ b/VEX/priv/host_mips_defs.h +@@ -1003,7 +1003,7 @@ extern void ppMIPSInstr(const MIPSInstr *, Bool mode64); + of the underlying instruction set. */ + extern void getRegUsage_MIPSInstr (HRegUsage *, const MIPSInstr *, Bool); + extern void mapRegs_MIPSInstr (HRegRemap *, MIPSInstr *, Bool mode64); +-extern Int emit_MIPSInstr (/*MB_MOD*/Bool* is_profInc, ++extern Int emit_MIPSInstr (/*MB_MOD*/Bool* is_profInc,/*MB_MOD*/Bool* is_8aligned, + UChar* buf, Int nbuf, const MIPSInstr* i, + Bool mode64, + VexEndness endness_host, +diff --git a/VEX/priv/host_nanomips_defs.c b/VEX/priv/host_nanomips_defs.c +index b356d09d8..4ee9f90e8 100755 +--- a/VEX/priv/host_nanomips_defs.c ++++ b/VEX/priv/host_nanomips_defs.c +@@ -1341,7 +1341,7 @@ static UChar *mkLoadImm(UChar * p, UInt r_dst, UInt imm) + imperative to emit position-independent code. If the emitted + instruction was a profiler inc, set *is_profInc to True, else + leave it unchanged. */ +-Int emit_NANOMIPSInstr ( /*MB_MOD*/Bool* is_profInc, ++Int emit_NANOMIPSInstr ( /*MB_MOD*/Bool* is_profInc,/*MB_MOD*/Bool* is_8aligned, + UChar* buf, Int nbuf, + const NANOMIPSInstr* i, + Bool mode64, +diff --git a/VEX/priv/host_nanomips_defs.h b/VEX/priv/host_nanomips_defs.h +index 87219dab5..1df04f383 100644 +--- a/VEX/priv/host_nanomips_defs.h ++++ b/VEX/priv/host_nanomips_defs.h +@@ -391,7 +391,7 @@ extern HInstrArray *iselSB_NANOMIPS(const IRSB*, + Bool chainingAllowed, + Bool addProfInc, + Addr max_ga); +-extern Int emit_NANOMIPSInstr (/*MB_MOD*/Bool* is_profInc, ++extern Int emit_NANOMIPSInstr (/*MB_MOD*/Bool* is_profInc,/*MB_MOD*/Bool* is_8aligned, + UChar* buf, Int nbuf, + const NANOMIPSInstr* i, + Bool mode64, +diff --git a/VEX/priv/host_ppc_defs.c b/VEX/priv/host_ppc_defs.c +index 4222b4786..5923db660 100644 +--- a/VEX/priv/host_ppc_defs.c ++++ b/VEX/priv/host_ppc_defs.c +@@ -4152,7 +4152,7 @@ static UChar* mkFormVA ( UChar* p, UInt opc1, UInt r1, UInt r2, + instruction was a profiler inc, set *is_profInc to True, else leave + it unchanged. + */ +-Int emit_PPCInstr ( /*MB_MOD*/Bool* is_profInc, ++Int emit_PPCInstr ( /*MB_MOD*/Bool* is_profInc,/*MB_MOD*/Bool* is_8aligned, + UChar* buf, Int nbuf, const PPCInstr* i, + Bool mode64, VexEndness endness_host, + const void* disp_cp_chain_me_to_slowEP, +diff --git a/VEX/priv/host_ppc_defs.h b/VEX/priv/host_ppc_defs.h +index 39dca08a2..3b3c0ad2c 100644 +--- a/VEX/priv/host_ppc_defs.h ++++ b/VEX/priv/host_ppc_defs.h +@@ -1266,7 +1266,7 @@ extern void ppPPCInstr(const PPCInstr*, Bool mode64); + of the underlying instruction set. */ + extern void getRegUsage_PPCInstr ( HRegUsage*, const PPCInstr*, Bool mode64 ); + extern void mapRegs_PPCInstr ( HRegRemap*, PPCInstr* , Bool mode64); +-extern Int emit_PPCInstr ( /*MB_MOD*/Bool* is_profInc, ++extern Int emit_PPCInstr ( /*MB_MOD*/Bool* is_profInc,/*MB_MOD*/Bool* is_8aligned, + UChar* buf, Int nbuf, const PPCInstr* i, + Bool mode64, + VexEndness endness_host, +diff --git a/VEX/priv/host_s390_defs.c b/VEX/priv/host_s390_defs.c +index c811dc5b8..64d75f3ed 100644 +--- a/VEX/priv/host_s390_defs.c ++++ b/VEX/priv/host_s390_defs.c +@@ -11766,7 +11766,8 @@ s390_insn_vec_replicate_emit(UChar *buf, const s390_insn *insn) + + + Int +-emit_S390Instr(Bool *is_profinc, UChar *buf, Int nbuf, const s390_insn *insn, ++emit_S390Instr(Bool *is_profinc, /*MB_MOD*/Bool* is_8aligned, ++ UChar *buf, Int nbuf, const s390_insn *insn, + Bool mode64, VexEndness endness_host, + const void *disp_cp_chain_me_to_slowEP, + const void *disp_cp_chain_me_to_fastEP, +diff --git a/VEX/priv/host_s390_defs.h b/VEX/priv/host_s390_defs.h +index 375cc8402..2d96e52d0 100644 +--- a/VEX/priv/host_s390_defs.h ++++ b/VEX/priv/host_s390_defs.h +@@ -877,8 +877,8 @@ UInt ppHRegS390(HReg); + of the underlying instruction set. */ + void getRegUsage_S390Instr( HRegUsage *, const s390_insn *, Bool ); + void mapRegs_S390Instr ( HRegRemap *, s390_insn *, Bool ); +-Int emit_S390Instr ( Bool *, UChar *, Int, const s390_insn *, Bool, +- VexEndness, const void *, const void *, ++Int emit_S390Instr ( Bool *, Bool *, UChar *, Int, const s390_insn *, ++ Bool, VexEndness, const void *, const void *, + const void *, const void *); + const RRegUniverse *getRRegUniverse_S390( void ); + void genSpill_S390 ( HInstr **, HInstr **, HReg , Int , Bool ); +diff --git a/VEX/priv/host_sw64_defs.c b/VEX/priv/host_sw64_defs.c +new file mode 100644 +index 000000000..45ec45e60 +--- /dev/null ++++ b/VEX/priv/host_sw64_defs.c +@@ -0,0 +1,3169 @@ ++/*---------------------------------------------------------------*/ ++/*--- begin host_sw64_defs.c ---*/ ++/*---------------------------------------------------------------*/ ++ ++/* ++ This file is part of Valgrind, a dynamic binary instrumentation ++ framework. ++ ++ Copyright (C) 2013-2017 OpenWorks ++ info@open-works.net ++ ++ This program is free software; you can redistribute it and/or ++ modify it under the terms of the GNU General Public License as ++ published by the Free Software Foundation; either version 2 of the ++ License, or (at your option) any later version. ++ ++ This program is distributed in the hope that it will be useful, but ++ WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with this program; if not, see . ++ ++ The GNU General Public License is contained in the file COPYING. ++*/ ++ ++#include "libvex_basictypes.h" ++#include "libvex.h" ++#include "libvex_trc_values.h" ++ ++#include "main_util.h" ++#include "host_generic_regs.h" ++#include "host_sw64_defs.h" ++ ++/* --------- Registers. --------- */ ++ ++/* The usual HReg abstraction. We use the following classes only: ++ R regs (64 bit int) ++ F regs (64 bit float, also used for 32 bit float) ++*/ ++ ++const RRegUniverse* getRRegUniverse_SW64 ( void ) ++{ ++ /* The real-register universe is a big constant, so we just want to ++ initialise it once. ++ rRegUniverse_SW64_initted values: 0=not initted, 1=initted */ ++ static RRegUniverse rRegUniverse_SW64; ++ static Bool rRegUniverse_SW64_initted = False; ++ ++ /* Handy shorthand, nothing more */ ++ RRegUniverse* ru = &rRegUniverse_SW64; ++ ++ /* This isn't thread-safe. Sigh. */ ++ if (LIKELY(rRegUniverse_SW64_initted)) ++ return ru; ++ ++ RRegUniverse__init(ru); ++ ++ /* Add the registers. The initial segment of this array must be ++ those available for allocation by reg-alloc, and those that ++ follow are not available for allocation. */ ++ ru->allocable_start[HRcInt64] = ru->size; ++ ru->regs[ru->size++] = hregSW64_R16(); ++ ru->regs[ru->size++] = hregSW64_R17(); ++ ru->regs[ru->size++] = hregSW64_R18(); ++ ru->regs[ru->size++] = hregSW64_R19(); ++ ru->regs[ru->size++] = hregSW64_R20(); ++ ru->regs[ru->size++] = hregSW64_R21(); ++ ru->regs[ru->size++] = hregSW64_R22(); ++ ru->regs[ru->size++] = hregSW64_R23(); ++ ru->regs[ru->size++] = hregSW64_R24(); ++ ru->regs[ru->size++] = hregSW64_R25(); ++ ru->regs[ru->size++] = hregSW64_R3(); ++ ru->regs[ru->size++] = hregSW64_R4(); ++ ru->regs[ru->size++] = hregSW64_R5(); ++ ru->regs[ru->size++] = hregSW64_R6(); ++ ru->regs[ru->size++] = hregSW64_R7(); ++ ru->regs[ru->size++] = hregSW64_R8(); ++ ru->regs[ru->size++] = hregSW64_R9(); ++ ru->regs[ru->size++] = hregSW64_R10(); ++ ru->regs[ru->size++] = hregSW64_R11(); ++ ru->regs[ru->size++] = hregSW64_R12(); ++ ru->allocable_end[HRcInt64] = ru->size - 1; ++ ++ /* F64 regs, all of which are callee-saved */ ++ ru->allocable_start[HRcFlt64] = ru->size; ++ ru->regs[ru->size++] = hregSW64_F2(); ++ ru->regs[ru->size++] = hregSW64_F3(); ++ ru->regs[ru->size++] = hregSW64_F4(); ++ ru->regs[ru->size++] = hregSW64_F5(); ++ ru->regs[ru->size++] = hregSW64_F6(); ++ ru->regs[ru->size++] = hregSW64_F7(); ++ ru->regs[ru->size++] = hregSW64_F8(); ++ ru->regs[ru->size++] = hregSW64_F9(); ++ ru->allocable_end[HRcFlt64] = ru->size - 1; ++ ++ ru->allocable = ru->size; ++ ++ /* And other regs, not available to the allocator. */ ++ ++ /* temporary, may use in ProcInc XDirect XIndir XAssisted LoadImm etc... */ ++ ru->regs[ru->size++] = hregSW64_R0(); ++ ru->regs[ru->size++] = hregSW64_R1(); ++ ru->regs[ru->size++] = hregSW64_R2(); ++ ++ /* reserved for future use */ ++ ru->regs[ru->size++] = hregSW64_R13(); ++ ru->regs[ru->size++] = hregSW64_R14(); ++ ++ /* used as guest pointer */ ++ ru->regs[ru->size++] = hregSW64_R15(); ++ ++ /* not available to allocator, of cause */ ++ ru->regs[ru->size++] = hregSW64_R26(); ++ ru->regs[ru->size++] = hregSW64_R27(); ++ ru->regs[ru->size++] = hregSW64_R28(); ++ ru->regs[ru->size++] = hregSW64_R29(); ++ ru->regs[ru->size++] = hregSW64_R30(); ++ ru->regs[ru->size++] = hregSW64_R31(); ++ ru->regs[ru->size++] = hregSW64_F31(); ++ ++ rRegUniverse_SW64_initted = True; ++ ++ RRegUniverse__check_is_sane(ru); ++ return ru; ++} ++ ++UInt ppHRegSW64(HReg reg) ++{ ++ Int r; ++ /* Be generic for all virtual regs. */ ++ if (hregIsVirtual(reg)) { ++ return ppHReg(reg); ++ } ++ /* But specific for real regs. */ ++ switch (hregClass(reg)) { ++ case HRcInt64: ++ r = hregEncoding(reg); ++ vassert(r >= 0 && r < 32); ++ if (r == 30) return vex_printf("sp"); ++ if (r == 29) return vex_printf("gp"); ++ if (r == 15) return vex_printf("fp"); ++ return vex_printf("r%d", r); ++ case HRcFlt64: ++ r = hregEncoding(reg); ++ vassert(r >= 0 && r < 32); ++ return vex_printf("f%d", r); ++ default: ++ vpanic("ppHRegSW64"); ++ } ++} ++ ++/* --------- SW64AMode: memory address expressions. --------- */ ++ ++SW64AModeRI *SW64AModeRI_IR(Int disp, HReg base) ++{ ++ SW64AModeRI *am = LibVEX_Alloc_inline(sizeof(SW64AModeRI)); ++ am->base = base; ++ am->disp = disp; ++ return am; ++} ++ ++void ppSW64AModeRI(SW64AModeRI * am) ++{ ++ if (am->disp == 0) ++ vex_printf("("); ++ else ++ vex_printf("%d(", (Int) am->disp); ++ ppHRegSW64(am->base); ++ vex_printf(")"); ++ return; ++} ++ ++/* --------- Helpers for register allocation. --------- */ ++ ++static void addRegUsage_SW64AModeRI(HRegUsage * u, SW64AModeRI * am) ++{ ++ addHRegUse(u, HRmRead, am->base); ++} ++ ++static void addRegUsage_SW64Cond(HRegUsage * u, SW64Cond * cond) ++{ ++ if (cond->code != SW64cc_AL) ++ addHRegUse(u, HRmRead, cond->reg); ++} ++ ++static void mapRegs_SW64AModeRI(HRegRemap * m, SW64AModeRI * am) ++{ ++ am->base = lookupHRegRemap(m, am->base); ++} ++ ++static void mapRegs_SW64Cond(HRegRemap * m, SW64Cond * cond) ++{ ++ if (cond->code != SW64cc_AL) ++ cond->reg = lookupHRegRemap(m, cond->reg); ++} ++ ++/* --------- Operand, which can be a reg or a u8. --------- */ ++ ++SW64RI8 *SW64RI8_Imm(UChar imm8) ++{ ++ SW64RI8 *op = LibVEX_Alloc_inline(sizeof(SW64RI8)); ++ op->tag = Sri8_Imm; ++ op->Sri8.Imm.imm8 = imm8; ++ return op; ++} ++ ++SW64RI8 *SW64RI8_Reg(HReg reg) ++{ ++ SW64RI8 *op = LibVEX_Alloc_inline(sizeof(SW64RI8)); ++ op->tag = Sri8_Reg; ++ op->Sri8.Reg.reg = reg; ++ return op; ++} ++ ++void ppSW64RI8(SW64RI8 * op) ++{ ++ SW64RI8Tag tag = op->tag; ++ switch (tag) { ++ case Sri8_Imm: ++ vex_printf("%u", (UInt)op->Sri8.Imm.imm8); ++ return; ++ case Sri8_Reg: ++ ppHRegSW64(op->Sri8.Reg.reg); ++ return; ++ default: ++ vpanic("ppSW64RI8"); ++ break; ++ } ++} ++ ++/* An SW64RH can only be used in a "read" context (what would it mean ++ to write or modify a literal?) and so we enumerate its registers ++ accordingly. */ ++static void addRegUsage_SW64RI8(HRegUsage * u, SW64RI8 * op) ++{ ++ switch (op->tag) { ++ case Sri8_Imm: ++ return; ++ case Sri8_Reg: ++ addHRegUse(u, HRmRead, op->Sri8.Reg.reg); ++ return; ++ default: ++ vpanic("addRegUsage_SW64RI8"); ++ break; ++ } ++} ++ ++static void mapRegs_SW64RI8(HRegRemap * m, SW64RI8 * op) ++{ ++ switch (op->tag) { ++ case Sri8_Imm: ++ return; ++ case Sri8_Reg: ++ op->Sri8.Reg.reg = lookupHRegRemap(m, op->Sri8.Reg.reg); ++ return; ++ default: ++ vpanic("mapRegs_SW64RI8"); ++ break; ++ } ++} ++ ++/*-----Integer load and store------*/ ++SW64Instr *SW64Instr_Load(SW64LoadOp op, HReg dst, SW64AModeRI *addr) ++{ ++ SW64Instr *i = LibVEX_Alloc_inline(sizeof(SW64Instr)); ++ i->tag = SW64in_Load; ++ i->SW64in.Load.op = op; ++ i->SW64in.Load.dst = dst; ++ i->SW64in.Load.addr = addr; ++ return i; ++} ++ ++SW64Instr *SW64Instr_Store(SW64StoreOp op, HReg src, SW64AModeRI *addr) ++{ ++ SW64Instr *i = LibVEX_Alloc_inline(sizeof(SW64Instr)); ++ i->tag = SW64in_Store; ++ i->SW64in.Store.op = op; ++ i->SW64in.Store.src = src; ++ i->SW64in.Store.addr = addr; ++ return i; ++} ++ ++/*-----Float load and store------*/ ++SW64Instr *SW64Instr_FpLoad(SW64FpLoadOp op, HReg dst, SW64AModeRI *addr) ++{ ++ SW64Instr *i = LibVEX_Alloc_inline(sizeof(SW64Instr)); ++ i->tag = SW64in_FpLoad; ++ i->SW64in.FpLoad.op = op; ++ i->SW64in.FpLoad.dst = dst; ++ i->SW64in.FpLoad.addr = addr; ++ return i; ++} ++ ++SW64Instr *SW64Instr_FpStore(SW64FpStoreOp op, HReg src, SW64AModeRI *addr) ++{ ++ SW64Instr *i = LibVEX_Alloc_inline(sizeof(SW64Instr)); ++ i->tag = SW64in_FpStore; ++ i->SW64in.FpStore.op = op; ++ i->SW64in.FpStore.src = src; ++ i->SW64in.FpStore.addr = addr; ++ return i; ++} ++ ++SW64Instr *SW64Instr_LoadImm(HReg dst, ULong imm64) ++{ ++ SW64Instr *i = LibVEX_Alloc_inline(sizeof(SW64Instr)); ++ i->tag = SW64in_LoadImm; ++ i->SW64in.LoadImm.imm64 = imm64; ++ i->SW64in.LoadImm.dst = dst; ++ return i; ++} ++ ++SW64Instr *SW64Instr_Cas(UChar sz, HReg res, HReg old, HReg addr, HReg expd, HReg data) ++{ ++ SW64Instr *i = LibVEX_Alloc_inline(sizeof(SW64Instr)); ++ i->tag = SW64in_CAS; ++ i->SW64in.Cas.sz = sz; ++ i->SW64in.Cas.old = old; ++ i->SW64in.Cas.addr = addr; ++ i->SW64in.Cas.expd = expd; ++ i->SW64in.Cas.data = data; ++ return i; ++} ++ ++SW64Instr *SW64Instr_UnOperate(SW64UnOp op, HReg dst, HReg src) ++{ ++ SW64Instr *i = LibVEX_Alloc_inline(sizeof(SW64Instr)); ++ i->tag = SW64in_UnOperate; ++ i->SW64in.UnOperate.op = op; ++ i->SW64in.UnOperate.src = src; ++ i->SW64in.UnOperate.dst = dst; ++ return i; ++} ++ ++SW64Instr *SW64Instr_FpArith(SW64FpArithOp op, HReg dst, HReg srcL, HReg srcR) ++{ ++ SW64Instr *i = LibVEX_Alloc_inline(sizeof(SW64Instr)); ++ i->tag = SW64in_FpArith; ++ i->SW64in.FpArith.op = op; ++ i->SW64in.FpArith.dst = dst; ++ i->SW64in.FpArith.srcL = srcL; ++ i->SW64in.FpArith.srcR = srcR; ++ return i; ++} ++ ++SW64Instr *SW64Instr_FpCpy(SW64FpCpyOp op, HReg dst, HReg src1, HReg src2) ++{ ++ SW64Instr *i = LibVEX_Alloc_inline(sizeof(SW64Instr)); ++ i->tag = SW64in_FpCpy; ++ i->SW64in.FpCpy.op = op; ++ i->SW64in.FpCpy.dst = dst; ++ i->SW64in.FpCpy.src1 = src1; ++ i->SW64in.FpCpy.src2 = src2; ++ return i; ++} ++ ++SW64Instr *SW64Instr_FpQuary(SW64FpQuaryOp op, HReg dst, HReg src1, HReg src2, HReg src3) ++{ ++ SW64Instr *i = LibVEX_Alloc_inline(sizeof(SW64Instr)); ++ i->tag = SW64in_FpQuary; ++ i->SW64in.FpQuary.op = op; ++ i->SW64in.FpQuary.dst = dst; ++ i->SW64in.FpQuary.src1 = src1; ++ i->SW64in.FpQuary.src2 = src2; ++ i->SW64in.FpQuary.src3 = src3; ++ return i; ++} ++ ++SW64Instr *SW64Instr_FpUnary(SW64FpUnaryOp op, HReg dst, HReg src) ++{ ++ SW64Instr *i = LibVEX_Alloc_inline(sizeof(SW64Instr)); ++ i->tag = SW64in_FpUnary; ++ i->SW64in.FpUnary.op = op; ++ i->SW64in.FpUnary.dst = dst; ++ i->SW64in.FpUnary.src = src; ++ return i; ++} ++ ++SW64Instr *SW64Instr_FpGpMove(SW64FpGpMoveOp op, HReg dst, HReg src) ++{ ++ SW64Instr *i = LibVEX_Alloc_inline(sizeof(SW64Instr)); ++ i->tag = SW64in_FpGpMove; ++ i->SW64in.FpGpMove.op = op; ++ i->SW64in.FpGpMove.src = src; ++ i->SW64in.FpGpMove.dst = dst; ++ return i; ++} ++ ++SW64Instr *SW64Instr_FpSel(SW64FpSelOp op, HReg dst, HReg iftrue, HReg iffalse, HReg cond ) ++{ ++ SW64Instr *i = LibVEX_Alloc_inline(sizeof(SW64Instr)); ++ i->tag = SW64in_FpSel; ++ i->SW64in.FpSel.op = op; ++ i->SW64in.FpSel.cond = cond; ++ i->SW64in.FpSel.dst = dst; ++ i->SW64in.FpSel.iftrue = iftrue; ++ i->SW64in.FpSel.iffalse = iffalse; ++ return i; ++} ++ ++SW64Instr *SW64Instr_FpCmp(SW64FpCmpOp op, HReg dst, HReg srcL, HReg srcR) ++{ ++ SW64Instr *i = LibVEX_Alloc_inline(sizeof(SW64Instr)); ++ i->tag = SW64in_FpCmp; ++ i->SW64in.FpCmp.op = op; ++ i->SW64in.FpCmp.dst = dst; ++ i->SW64in.FpCmp.srcL = srcL; ++ i->SW64in.FpCmp.srcR = srcR; ++ return i; ++} ++ ++SW64Instr *SW64Instr_FpCvt(SW64FpCvtOp op, HReg dst, HReg src) ++{ ++ SW64Instr *i = LibVEX_Alloc_inline(sizeof(SW64Instr)); ++ i->tag = SW64in_FpCvt; ++ i->SW64in.FpCvt.op = op; ++ i->SW64in.FpCvt.src = src; ++ i->SW64in.FpCvt.dst = dst; ++ return i; ++} ++ ++SW64Instr *SW64Instr_RFPCR (HReg dst) ++{ ++ SW64Instr *i = LibVEX_Alloc_inline(sizeof(SW64Instr)); ++ i->tag = SW64in_RFPCR; ++ i->SW64in.RFPCR.dst = dst; ++ return i; ++} ++ ++SW64Instr *SW64Instr_WFPCR (HReg src) ++{ ++ SW64Instr *i = LibVEX_Alloc_inline(sizeof(SW64Instr)); ++ i->tag = SW64in_WFPCR; ++ i->SW64in.WFPCR.src = src; ++ return i; ++} ++ ++SW64Instr *SW64Instr_Logic(SW64LogicOp op, HReg dst, HReg srcL, SW64RI8 * srcR) ++{ ++ SW64Instr *i = LibVEX_Alloc_inline(sizeof(SW64Instr)); ++ i->tag = SW64in_Logic; ++ i->SW64in.Logic.op = op; ++ i->SW64in.Logic.dst = dst; ++ i->SW64in.Logic.srcL = srcL; ++ i->SW64in.Logic.srcR = srcR; ++ return i; ++} ++ ++SW64Instr *SW64Instr_Cmp(SW64CmpOp op, HReg dst, HReg srcL, SW64RI8 * srcR) ++{ ++ SW64Instr *i = LibVEX_Alloc_inline(sizeof(SW64Instr)); ++ i->tag = SW64in_Cmp; ++ i->SW64in.Cmp.op = op; ++ i->SW64in.Cmp.dst = dst; ++ i->SW64in.Cmp.srcL = srcL; ++ i->SW64in.Cmp.srcR = srcR; ++ return i; ++} ++ ++SW64Instr *SW64Instr_Shft(SW64ShftOp op, HReg dst, HReg srcL, SW64RI8 *srcR) ++{ ++ SW64Instr *i = LibVEX_Alloc_inline(sizeof(SW64Instr)); ++ i->tag = SW64in_Shft; ++ i->SW64in.Shft.op = op; ++ i->SW64in.Shft.dst = dst; ++ i->SW64in.Shft.srcL = srcL; ++ i->SW64in.Shft.srcR = srcR; ++ return i; ++} ++ ++SW64Instr *SW64Instr_Arith(SW64ArithOp op, HReg dst, HReg srcL, SW64RI8 *srcR) ++{ ++ SW64Instr *i = LibVEX_Alloc_inline(sizeof(SW64Instr)); ++ i->tag = SW64in_Arith; ++ i->SW64in.Arith.op = op; ++ i->SW64in.Arith.dst = dst; ++ i->SW64in.Arith.srcL = srcL; ++ i->SW64in.Arith.srcR = srcR; ++ return i; ++} ++ ++SW64Instr *SW64Instr_IntDiv(SW64IntDivOp op, HReg dst, HReg srcL, HReg srcR) ++{ ++ SW64Instr *i = LibVEX_Alloc_inline(sizeof(SW64Instr)); ++ i->tag = SW64in_IntDiv; ++ i->SW64in.IntDiv.op = op; ++ i->SW64in.IntDiv.dst = dst; ++ i->SW64in.IntDiv.srcL = srcL; ++ i->SW64in.IntDiv.srcR = srcR; ++ return i; ++} ++ ++SW64Instr *SW64Instr_XDirect ( Addr64 dstGA, SW64AModeRI* amPC, ++ SW64Cond* cond, Bool toFastEP ) { ++ SW64Instr* i = LibVEX_Alloc_inline(sizeof(SW64Instr)); ++ i->tag = SW64in_XDirect; ++ i->SW64in.XDirect.dstGA = dstGA; ++ i->SW64in.XDirect.amPC = amPC; ++ i->SW64in.XDirect.cond = cond; ++ i->SW64in.XDirect.toFastEP = toFastEP; ++ return i; ++} ++ ++SW64Instr *SW64Instr_XIndir ( HReg dstGA, SW64AModeRI* amPC, ++ SW64Cond* cond ) { ++ SW64Instr* i = LibVEX_Alloc_inline(sizeof(SW64Instr)); ++ i->tag = SW64in_XIndir; ++ i->SW64in.XIndir.dstGA = dstGA; ++ i->SW64in.XIndir.amPC = amPC; ++ i->SW64in.XIndir.cond = cond; ++ return i; ++} ++ ++SW64Instr *SW64Instr_XAssisted ( HReg dstGA, SW64AModeRI* amPC, ++ SW64Cond* cond, IRJumpKind jk ) { ++ SW64Instr* i = LibVEX_Alloc_inline(sizeof(SW64Instr)); ++ i->tag = SW64in_XAssisted; ++ i->SW64in.XAssisted.dstGA = dstGA; ++ i->SW64in.XAssisted.amPC = amPC; ++ i->SW64in.XAssisted.cond = cond; ++ i->SW64in.XAssisted.jk = jk; ++ return i; ++} ++ ++SW64Instr* SW64Instr_CondSel ( SW64CondSelOp op, HReg dst, HReg iftrue, HReg iffalse, HReg cond) ++{ ++ SW64Instr* i = LibVEX_Alloc_inline(sizeof(SW64Instr)); ++ i->tag = SW64in_CondSel; ++ i->SW64in.CondSel.op = op; ++ i->SW64in.CondSel.dst = dst; ++ i->SW64in.CondSel.iftrue = iftrue; ++ i->SW64in.CondSel.iffalse = iffalse; ++ i->SW64in.CondSel.cond = cond; ++ return i; ++} ++ ++SW64Instr *SW64Instr_EvCheck ( SW64AModeRI* amCounter, SW64AModeRI* amFailAddr ) ++{ ++ SW64Instr* i = LibVEX_Alloc_inline(sizeof(SW64Instr)); ++ i->tag = SW64in_EvCheck; ++ i->SW64in.EvCheck.amCounter = amCounter; ++ i->SW64in.EvCheck.amFailAddr = amFailAddr; ++ return i; ++} ++ ++SW64Instr* SW64Instr_ProfInc ( void ) ++{ ++ SW64Instr* i = LibVEX_Alloc_inline(sizeof(SW64Instr)); ++ i->tag = SW64in_ProfInc; ++ return i; ++} ++ ++SW64Instr *SW64Instr_Call ( SW64Cond* cond, ++ Addr64 target, UInt argiregs, RetLoc rloc ) ++{ ++ UInt mask; ++ SW64Instr *i = LibVEX_Alloc_inline(sizeof(SW64Instr)); ++ i->tag = SW64in_Call; ++ i->SW64in.Call.cond = cond; ++ i->SW64in.Call.target = target; ++ i->SW64in.Call.argiregs = argiregs; ++ i->SW64in.Call.rloc = rloc; ++ /* Only $16 .. $21 inclusive may be used as arg regs. */ ++ UInt base = 16; ++ mask = (1 << (16-base)) | (1 << (17-base)) | (1 << (18-base)) | (1 << (19-base)) | (1 << (20-base)) | (1 << (21-base)); ++ vassert(0 == (argiregs & ~mask)); ++ vassert(is_sane_RetLoc(rloc)); ++ return i; ++} ++ ++SW64Instr* SW64Instr_MFence(void) ++{ ++ SW64Instr* i = LibVEX_Alloc_inline(sizeof(SW64Instr)); ++ i->tag = SW64in_Mfence; ++ return i; ++} ++ ++SW64Cond *SW64Cond_Cond(SW64CondCode code, HReg reg) ++{ ++ SW64Cond* c = LibVEX_Alloc_inline(sizeof(SW64Cond)); ++ c->code = code; ++ c->reg = reg; ++ return c; ++} ++ ++SW64Cond *SW64Cond_ALWAYS(void) ++{ ++ SW64Cond* c = LibVEX_Alloc_inline(sizeof(SW64Cond)); ++ c->code = SW64cc_AL; ++ c->reg = INVALID_HREG; ++ return c; ++} ++ ++void ppSW64Cond(const SW64Cond *cond) ++{ ++ if (cond->code == SW64cc_AL) { ++ vex_printf("if (true) "); ++ } else { ++ const char *str = (cond->code == SW64cc_EQ ) ? " == 0)" : ++ (cond->code == SW64cc_NE ) ? " != 0)" : ++ (cond->code == SW64cc_LT ) ? " < 0)" : ++ (cond->code == SW64cc_LE ) ? " <= 0)" : ++ (cond->code == SW64cc_GT ) ? " > 0)" : ++ (cond->code == SW64cc_GE ) ? " >= 0)" : ++ (cond->code == SW64cc_FEQ) ? " == 0.0)" : ++ (cond->code == SW64cc_FNE) ? " != 0.0)" : ++ (cond->code == SW64cc_FLT) ? " < 0.0)" : ++ (cond->code == SW64cc_FLE) ? " <= 0.0)" : ++ (cond->code == SW64cc_FGT) ? " > 0.0)" : ++ (cond->code == SW64cc_FGE) ? " >= 0.0)" : ++ (vassert(0), NULL); ++ vex_printf("if ("); ++ ppHRegSW64(cond->reg); ++ vex_printf("%s ", str); ++ } ++} ++ ++const HChar *showSW64LoadOp(SW64LoadOp op) ++{ ++ switch (op) { ++ case SW64in_LDBU: return "ldbu"; ++ case SW64in_LDHU: return "ldhu"; ++ case SW64in_LDW: return "ldw"; ++ case SW64in_LDL: return "ldl"; ++ default: vpanic("showSW64LoadOp"); ++ } ++} ++ ++const HChar *showSW64StoreOp(SW64StoreOp op) ++{ ++ switch (op) { ++ case SW64in_STB: return "stb"; ++ case SW64in_STH: return "sth"; ++ case SW64in_STW: return "stw"; ++ case SW64in_STL: return "stl"; ++ default: vpanic("showSW64StoreOp"); ++ } ++} ++ ++const HChar *showSW64FpLoadOp(SW64FpLoadOp op) ++{ ++ switch (op) { ++ case SW64in_FLDS: return "flds"; ++ case SW64in_FLDD: return "fldd"; ++ default: vpanic("showSW64FpLoadOp"); ++ } ++} ++ ++const HChar *showSW64FpStoreOp(SW64FpStoreOp op) ++{ ++ switch (op) { ++ case SW64in_FSTS: return "fsts"; ++ case SW64in_FSTD: return "fstd"; ++ default: vpanic("showSW64FpStoreOp"); ++ } ++} ++ ++const HChar *showSW64CmpOp(SW64CmpOp op) ++{ ++ switch(op) { ++ case SW64in_CMPEQ: return "cmpeq"; ++ case SW64in_CMPLT: return "cmplt"; ++ case SW64in_CMPLE: return "cmple"; ++ case SW64in_CMPULT: return "cmpult"; ++ case SW64in_CMPULE: return "cmpule"; ++ default: vpanic("showSW64CmpOp"); ++ } ++} ++ ++const HChar *showSW64CondSelOp(SW64CondSelOp op) ++{ ++ switch(op) { ++ case SW64in_SELEQ: return "seleq"; ++ case SW64in_SELGE: return "selge"; ++ case SW64in_SELGT: return "selgt"; ++ case SW64in_SELLE: return "selle"; ++ case SW64in_SELLT: return "sellt"; ++ case SW64in_SELNE: return "selne"; ++ case SW64in_SELLBC: return "sellbc"; ++ case SW64in_SELLBS: return "sellbs"; ++ default: vpanic("showSW64CondSelOp"); ++ } ++} ++ ++const HChar *showSW64LogicOp(SW64LogicOp op) ++{ ++ switch (op) { ++ case SW64in_AND: return "and"; ++ case SW64in_OR: return "bis"; ++ case SW64in_XOR: return "xor"; ++ case SW64in_ORNOT: return "ornot"; ++ case SW64in_BIC: return "bic"; ++ default: vpanic("showSW64LogicOp"); ++ } ++} ++ ++const HChar *showSW64ArithOp(SW64ArithOp op) ++{ ++ switch (op) { ++ case SW64in_ADDW: return "addw"; ++ case SW64in_SUBW: return "subw"; ++ case SW64in_S4ADDW: return "s4addw"; ++ case SW64in_S4SUBW: return "s4subw"; ++ case SW64in_S8ADDW: return "s8addw"; ++ case SW64in_S8SUBW: return "s8subw"; ++ case SW64in_ADDL: return "addl"; ++ case SW64in_SUBL: return "subl"; ++ case SW64in_S4ADDL: return "s4addl"; ++ case SW64in_S4SUBL: return "s4subl"; ++ case SW64in_S8ADDL: return "s8addl"; ++ case SW64in_S8SUBL: return "s8subl"; ++ case SW64in_MULW: return "mulw"; ++ case SW64in_MULL: return "mull"; ++ case SW64in_UMULH: return "umulh"; ++ case SW64in_ZAP: return "zap"; ++ case SW64in_ZAPNOT: return "zapnot"; ++ case SW64in_SEXTB: return "sextb"; ++ case SW64in_SEXTH: return "sexth"; ++ default: vpanic("showSW64ArithOp"); ++ } ++} ++ ++const HChar *showSW64IntDivOp(SW64IntDivOp op) ++{ ++ switch (op) { ++ case SW64in_DIVW: return "divw"; ++ case SW64in_UDIVW: return "udivw"; ++ case SW64in_REMW: return "remw"; ++ case SW64in_UREMW: return "uremw"; ++ case SW64in_DIVL: return "divl"; ++ case SW64in_UDIVL: return "udivl"; ++ case SW64in_REML: return "reml"; ++ case SW64in_UREML: return "ureml"; ++ default: vpanic("showSW64IntDivOp"); ++ } ++} ++ ++const HChar *showSW64UnaryOp(SW64UnOp op) ++{ ++ switch (op) { ++ case SW64in_POP: return "ctpop"; ++ case SW64in_CLZ: return "ctlz"; ++ case SW64in_CTZ: return "cttz"; ++ default: vpanic("showSW64UnaryOp"); ++ } ++} ++ ++const HChar *showSW64ShftOp(SW64ShftOp op) ++{ ++ switch (op) { ++ case SW64in_SLL: return "sll"; ++ case SW64in_SRL: return "srl"; ++ case SW64in_SRA: return "sra"; ++ default: vpanic("showSW64ShftOp"); ++ } ++} ++ ++const HChar *showSW64FpArithOp(SW64FpArithOp op) ++{ ++ switch (op) { ++ case SW64in_FADDS: return "fadds"; ++ case SW64in_FADDD: return "faddd"; ++ case SW64in_FSUBS: return "fsubs"; ++ case SW64in_FSUBD: return "fsubd"; ++ case SW64in_FMULS: return "fmuls"; ++ case SW64in_FMULD: return "fmuld"; ++ case SW64in_FDIVS: return "fdivs"; ++ case SW64in_FDIVD: return "fdivd"; ++ default: vpanic("showSW64FpArithOp"); ++ } ++} ++ ++const HChar *showSW64FpGpMoveOp(SW64FpGpMoveOp op) ++{ ++ switch (op) { ++ case SW64in_FIMOVS: return "fimovs"; ++ case SW64in_FIMOVD: return "fimovd"; ++ case SW64in_IFMOVS: return "ifmovs"; ++ case SW64in_IFMOVD: return "ifmovd"; ++ case SW64in_CMOVDL: return "cmovdl"; ++ case SW64in_CMOVDL_G: return "cmovdl_g"; ++ case SW64in_CMOVDL_P: return "cmovdl_p"; ++ case SW64in_CMOVDL_Z: return "cmovdl_z"; ++ case SW64in_CMOVDL_N: return "cmovdl_n"; ++ case SW64in_CMOVDLU: return "cmovdlu"; ++ case SW64in_CMOVDLU_G: return "cmovdlu_g"; ++ case SW64in_CMOVDLU_P: return "cmovdlu_p"; ++ case SW64in_CMOVDLU_Z: return "cmovdlu_z"; ++ case SW64in_CMOVDLU_N: return "cmovdlu_n"; ++ case SW64in_CMOVDWU: return "cmovdwu"; ++ case SW64in_CMOVDWU_G: return "cmovdwu_g"; ++ case SW64in_CMOVDWU_P: return "cmovdwu_p"; ++ case SW64in_CMOVDWU_Z: return "cmovdwu_z"; ++ case SW64in_CMOVDWU_N: return "cmovdwu_n"; ++ case SW64in_CMOVDW: return "cmovdw"; ++ case SW64in_CMOVDW_G: return "cmovdw_g"; ++ case SW64in_CMOVDW_P: return "cmovdw_p"; ++ case SW64in_CMOVDW_Z: return "cmovdw_z"; ++ case SW64in_CMOVDW_N: return "cmovdw_n"; ++ case SW64in_CMOVLS: return "cmovls"; ++ case SW64in_CMOVWS: return "cmovws"; ++ case SW64in_CMOVLD: return "cmovld"; ++ case SW64in_CMOVWD: return "cmovwd"; ++ case SW64in_CMOVULS: return "cmovuls"; ++ case SW64in_CMOVUWS: return "cmovuws"; ++ case SW64in_CMOVULD: return "cmovuld"; ++ case SW64in_CMOVUWD: return "cmovuwd"; ++ default: vpanic("showSW64FpGpMoveOp"); ++ } ++} ++ ++const HChar *showSW64FpCpyOp(SW64FpCpyOp op) ++{ ++ switch (op) { ++ case SW64in_FCPYS: return "fcpys"; ++ case SW64in_FCPYSE: return "fcpyse"; ++ case SW64in_FCPYSN: return "fcpysn"; ++ default: vpanic("showSW64FpCpyOp"); ++ } ++} ++ ++const HChar *showSW64FpQuaryOp(SW64FpQuaryOp op) ++{ ++ switch (op) { ++ case SW64in_MADDS: return "madds"; ++ case SW64in_MADDD: return "maddd"; ++ case SW64in_MSUBS: return "msubs"; ++ case SW64in_MSUBD: return "msubd"; ++ default: vpanic("showSW64FpQuaryOp"); ++ } ++} ++ ++const HChar *showSW64FpUnaryOp(SW64FpUnaryOp op) ++{ ++ switch (op) { ++ case SW64in_FSQRTS: return "fsqrts"; ++ case SW64in_FSQRTD: return "fsqrtd"; ++ case SW64in_FRECS: return "frecs"; ++ case SW64in_FRECD: return "frecd"; ++ case SW64in_FRIS: return "fris"; ++ case SW64in_FRIS_G: return "fris_g"; ++ case SW64in_FRIS_P: return "fris_p"; ++ case SW64in_FRIS_Z: return "fris_z"; ++ case SW64in_FRIS_N: return "fris_n"; ++ case SW64in_FRID: return "frid"; ++ case SW64in_FRID_G: return "frid_g"; ++ case SW64in_FRID_P: return "frid_p"; ++ case SW64in_FRID_Z: return "frid_z"; ++ case SW64in_FRID_N: return "frid_n"; ++ default: vpanic("showSW64FpUnaryOp"); ++ } ++} ++ ++const HChar *showSW64FpCmpOp(SW64FpCmpOp op) ++{ ++ switch (op) { ++ case SW64in_CMPFEQ: return "fcmpeq"; ++ case SW64in_CMPFLE: return "fcmple"; ++ case SW64in_CMPFLT: return "fcmplt"; ++ case SW64in_CMPFUN: return "fcmpun"; ++ default: vpanic("showSW64FpCmpOp"); ++ } ++} ++ ++const HChar *showSW64FpSelOp(SW64FpSelOp op) ++{ ++ switch(op) { ++ case SW64in_FSELEQ: return "fseleq"; ++ case SW64in_FSELNE: return "fselne"; ++ case SW64in_FSELLT: return "fsellt"; ++ case SW64in_FSELLE: return "fselle"; ++ case SW64in_FSELGT: return "fselgt"; ++ case SW64in_FSELGE: return "fselge"; ++ default: vpanic("showSW64FpSelOp"); ++ } ++} ++ ++const HChar *showSW64FpCvtOp(SW64FpCvtOp op) ++{ ++ switch (op) { ++ case SW64in_FCVTSD: return "fcvtsd"; ++ case SW64in_FCVTDS: return "fcvtds"; ++ case SW64in_FCVTDL: return "fcvtdl"; ++ case SW64in_FCVTLS: return "fcvtls"; ++ case SW64in_FCVTLD: return "fcvtld"; ++ case SW64in_FCVTDL_G: return "fcvtdl_g"; ++ case SW64in_FCVTDL_P: return "fcvtdl_p"; ++ case SW64in_FCVTDL_Z: return "fcvtdl_z"; ++ case SW64in_FCVTDL_N: return "fcvtdl_n"; ++ default: vpanic("showSW64FpCvtOp"); ++ } ++} ++ ++/*-----print sw64 instr----*/ ++void ppSW64Instr(const SW64Instr *i) ++{ ++ switch(i->tag) ++ { ++ case SW64in_Load: ++ { ++ vex_printf("%s ", showSW64LoadOp(i->SW64in.Load.op)); ++ ppHRegSW64(i->SW64in.Load.dst); ++ vex_printf(","); ++ ppSW64AModeRI(i->SW64in.Load.addr); ++ return; ++ } ++ case SW64in_Store: ++ { ++ vex_printf("%s ", showSW64StoreOp(i->SW64in.Store.op)); ++ ppHRegSW64(i->SW64in.Store.src); ++ vex_printf(","); ++ ppSW64AModeRI(i->SW64in.Store.addr); ++ return; ++ } ++ case SW64in_FpLoad: ++ { ++ vex_printf("%s ", showSW64FpLoadOp(i->SW64in.FpLoad.op)); ++ ppHRegSW64(i->SW64in.FpLoad.dst); ++ vex_printf(","); ++ ppSW64AModeRI(i->SW64in.FpLoad.addr); ++ return; ++ } ++ case SW64in_FpStore: ++ { ++ vex_printf("%s ", showSW64FpStoreOp(i->SW64in.FpStore.op)); ++ ppHRegSW64(i->SW64in.FpStore.src); ++ vex_printf(","); ++ ppSW64AModeRI(i->SW64in.FpStore.addr); ++ return; ++ } ++ case SW64in_LoadImm: ++ { ++ vex_printf("ldi "); ++ ppHRegSW64(i->SW64in.LoadImm.dst); ++ vex_printf(",0x%016llx($31)", i->SW64in.LoadImm.imm64); ++ return; ++ } ++ case SW64in_CAS: ++ { ++ /* ++ 0: lld* %[old], 0(%[addr]) ++ cmpeq %[old], %[expd], $1 ++ wr_f $1 ++ mov %[data], $2 ++ lst* $2, 0(%[addr]) ++ rd_f $2 ++ beq $1, 1f ++ beq $2, 0b ++ 1: ++ */ ++ UChar sz = i->SW64in.Cas.sz; ++ vassert(sz == 4 || sz == 8); ++ ++ vex_printf("0: lld%c ", sz == 4 ? 'w' : 'l'); ++ ppHRegSW64(i->SW64in.Cas.old); ++ vex_printf(", 0("); ++ ppHRegSW64(i->SW64in.Cas.addr); ++ vex_printf(")\n"); ++ ++ vex_printf(" cmpeq "); ++ ppHRegSW64(i->SW64in.Cas.old); ++ vex_printf(", "); ++ ppHRegSW64(i->SW64in.Cas.expd); ++ vex_printf(", r1\n"); ++ ++ vex_printf(" wr_f r1\n"); ++ ++ vex_printf(" mov "); ++ ppHRegSW64(i->SW64in.Cas.data); ++ vex_printf(", r2\n"); ++ ++ vex_printf(" lst%c r2, 0(", sz == 4 ? 'w' : 'l'); ++ ppHRegSW64(i->SW64in.Cas.addr); ++ vex_printf(")\n"); ++ ++ vex_printf(" rd_f r2\n"); ++ ++ vex_printf(" beq r1, 1f\n"); ++ ++ vex_printf(" beq r2, 0b\n"); ++ ++ vex_printf("1: "); ++ return; ++ } ++ case SW64in_UnOperate: ++ { ++ vex_printf("%s ", showSW64UnaryOp(i->SW64in.UnOperate.op)); ++ ppHRegSW64(i->SW64in.UnOperate.src); ++ vex_printf(","); ++ ppHRegSW64(i->SW64in.UnOperate.dst); ++ return; ++ } ++ case SW64in_Logic: ++ { ++ vex_printf("%s ", showSW64LogicOp(i->SW64in.Logic.op)); ++ ppHRegSW64(i->SW64in.Logic.srcL); ++ vex_printf(","); ++ ppSW64RI8(i->SW64in.Logic.srcR); ++ vex_printf(","); ++ ppHRegSW64(i->SW64in.Logic.dst); ++ return; ++ } ++ case SW64in_Cmp: ++ { ++ vex_printf("%s ", showSW64CmpOp(i->SW64in.Cmp.op)); ++ ppHRegSW64(i->SW64in.Cmp.srcL); ++ vex_printf(","); ++ ppSW64RI8(i->SW64in.Cmp.srcR); ++ vex_printf(","); ++ ppHRegSW64(i->SW64in.Cmp.dst); ++ return; ++ } ++ case SW64in_Shft: ++ { ++ vex_printf("%s ", showSW64ShftOp(i->SW64in.Shft.op)); ++ ppHRegSW64(i->SW64in.Shft.srcL); ++ vex_printf(","); ++ ppSW64RI8(i->SW64in.Shft.srcR); ++ vex_printf(","); ++ ppHRegSW64(i->SW64in.Shft.dst); ++ return; ++ } ++ case SW64in_Arith: ++ { ++ vex_printf("%s ", showSW64ArithOp(i->SW64in.Arith.op)); ++ ppHRegSW64(i->SW64in.Arith.srcL); ++ vex_printf(","); ++ ppSW64RI8(i->SW64in.Arith.srcR); ++ vex_printf(","); ++ ppHRegSW64(i->SW64in.Arith.dst); ++ return; ++ } ++ case SW64in_IntDiv: ++ { ++ vex_printf("%s ", showSW64IntDivOp(i->SW64in.IntDiv.op)); ++ ppHRegSW64(i->SW64in.IntDiv.srcL); ++ vex_printf(","); ++ ppHRegSW64(i->SW64in.IntDiv.srcR); ++ vex_printf(","); ++ ppHRegSW64(i->SW64in.IntDiv.dst); ++ return; ++ } ++ case SW64in_CondSel: ++ { ++ vex_printf("%s ", showSW64CondSelOp(i->SW64in.CondSel.op)); ++ ppHRegSW64(i->SW64in.CondSel.cond); ++ vex_printf(","); ++ ppHRegSW64(i->SW64in.CondSel.iftrue); ++ vex_printf(","); ++ ppHRegSW64(i->SW64in.CondSel.iffalse); ++ vex_printf(","); ++ ppHRegSW64(i->SW64in.CondSel.dst); ++ return; ++ } ++ case SW64in_FpArith: ++ { ++ vex_printf("%s ", showSW64FpArithOp(i->SW64in.FpArith.op)); ++ ppHRegSW64(i->SW64in.FpArith.srcL); ++ vex_printf(","); ++ ppHRegSW64(i->SW64in.FpArith.srcR); ++ vex_printf(","); ++ ppHRegSW64(i->SW64in.FpArith.dst); ++ return; ++ } ++ case SW64in_FpCpy: ++ { ++ vex_printf("%s ", showSW64FpCpyOp(i->SW64in.FpCpy.op)); ++ ppHRegSW64(i->SW64in.FpCpy.src1); ++ vex_printf(","); ++ ppHRegSW64(i->SW64in.FpCpy.src2); ++ vex_printf(","); ++ ppHRegSW64(i->SW64in.FpCpy.dst); ++ return; ++ } ++ case SW64in_FpQuary: ++ { ++ vex_printf("%s ", showSW64FpQuaryOp(i->SW64in.FpQuary.op)); ++ ppHRegSW64(i->SW64in.FpQuary.src1); ++ vex_printf(","); ++ ppHRegSW64(i->SW64in.FpQuary.src2); ++ vex_printf(","); ++ ppHRegSW64(i->SW64in.FpQuary.src3); ++ vex_printf(","); ++ ppHRegSW64(i->SW64in.FpQuary.dst); ++ return; ++ } ++ case SW64in_FpUnary: ++ { ++ vex_printf("%s ", showSW64FpUnaryOp(i->SW64in.FpUnary.op)); ++ ppHRegSW64(i->SW64in.FpUnary.dst); ++ vex_printf(","); ++ ppHRegSW64(i->SW64in.FpUnary.src); ++ return; ++ } ++ case SW64in_FpGpMove: ++ { ++ vex_printf("%s ", showSW64FpGpMoveOp(i->SW64in.FpGpMove.op)); ++ ppHRegSW64(i->SW64in.FpGpMove.src); ++ vex_printf(","); ++ ppHRegSW64(i->SW64in.FpGpMove.dst); ++ return; ++ } ++ case SW64in_FpSel: ++ { ++ vex_printf("%s ", showSW64FpSelOp(i->SW64in.FpSel.op)); ++ ppHRegSW64(i->SW64in.FpSel.cond); ++ vex_printf(","); ++ ppHRegSW64(i->SW64in.FpSel.iftrue); ++ vex_printf(","); ++ ppHRegSW64(i->SW64in.FpSel.iffalse); ++ vex_printf(","); ++ ppHRegSW64(i->SW64in.FpSel.dst); ++ return; ++ } ++ case SW64in_FpCmp: ++ { ++ vex_printf("%s ", showSW64FpCmpOp(i->SW64in.FpCmp.op)); ++ ppHRegSW64(i->SW64in.FpCmp.srcL); ++ vex_printf(","); ++ ppHRegSW64(i->SW64in.FpCmp.srcR); ++ vex_printf(","); ++ ppHRegSW64(i->SW64in.FpCmp.dst); ++ return; ++ } ++ case SW64in_FpCvt: ++ { ++ vex_printf("%s ", showSW64FpCvtOp(i->SW64in.FpCvt.op)); ++ ppHRegSW64(i->SW64in.FpCvt.src); ++ vex_printf(","); ++ ppHRegSW64(i->SW64in.FpCvt.dst); ++ return; ++ } ++ case SW64in_RFPCR: ++ { ++ vex_printf("rfpcr "); ++ ppHRegSW64(i->SW64in.RFPCR.dst); ++ return; ++ } ++ case SW64in_WFPCR: ++ { ++ vex_printf("wfpcr "); ++ ppHRegSW64(i->SW64in.WFPCR.src); ++ return; ++ } ++ case SW64in_XDirect: ++ { ++ vex_printf("(xDirect) "); ++ ppSW64Cond(i->SW64in.XDirect.cond); ++ vex_printf("{ ldi r2, 0x%llx", i->SW64in.XDirect.dstGA); ++ vex_printf("; stl r2, "); ++ ppSW64AModeRI(i->SW64in.XDirect.amPC); ++ vex_printf("; ldi r2, disp_cp_chain_me_to_%sEP; jmp r1, (r2); }", ++ i->SW64in.XDirect.toFastEP ? "fast" : "slow"); ++ return; ++ } ++ case SW64in_XIndir: ++ { ++ vex_printf("(xIndir) "); ++ ppSW64Cond(i->SW64in.XIndir.cond); ++ vex_printf("{ stl "); ++ ppHRegSW64(i->SW64in.XIndir.dstGA); ++ vex_printf(", "); ++ ppSW64AModeRI(i->SW64in.XIndir.amPC); ++ vex_printf("; ldi r2, disp_indir; jmp r31, (r2); }"); ++ return; ++ } ++ case SW64in_XAssisted: ++ { ++ vex_printf("(xAssisted) "); ++ ppSW64Cond(i->SW64in.XAssisted.cond); ++ vex_printf("{ stl "); ++ ppHRegSW64(i->SW64in.XAssisted.dstGA); ++ vex_printf(", "); ++ ppSW64AModeRI(i->SW64in.XAssisted.amPC); ++ vex_printf("; ldi r0, IRJumpKind_to_TRCVAL(%d)", ++ (Int)i->SW64in.XAssisted.jk); ++ vex_printf("; ldi r2, disp_assisted; jmp r31, (r2);}"); ++ return; ++ } ++ case SW64in_EvCheck: ++ { ++ vex_printf("(evCheck) ldw r2, "); ++ ppSW64AModeRI(i->SW64in.EvCheck.amCounter); ++ vex_printf("; subl r2,1,r2"); ++ vex_printf("; stw r2, "); ++ ppSW64AModeRI(i->SW64in.EvCheck.amCounter); ++ vex_printf("; bgez r2, nofail"); ++ vex_printf("; ldl r2, "); ++ ppSW64AModeRI(i->SW64in.EvCheck.amFailAddr); ++ vex_printf("; jmp r31, (r2)"); ++ vex_printf("; nofail:"); ++ return; ++ } ++ case SW64in_ProfInc: ++ { ++ vex_printf("(profInc) ldi r2, ($NotKnownYet); " ++ "ldl r1, 0(r2); " ++ "addl r1, 1, r1; " ++ "stl r1, 0(r2); "); ++ return; ++ } ++ case SW64in_Call: ++ { ++ Int n; ++ vex_printf("call: "); ++ ppSW64Cond(i->SW64in.Call.cond); ++ vex_printf("{ ldi "); ++ ppHRegSW64(hregSW64_R27()); ++ vex_printf(",0x%016llx($31)", i->SW64in.Call.target); ++ ++ vex_printf(" ; JMP $26, $27; # args ["); ++ for (n = 16; n < 32; n++) { ++ if (i->SW64in.Call.argiregs & (1 << (n-16))) { ++ vex_printf("$%d", n); ++ if ((i->SW64in.Call.argiregs >> (n-16)) > 1) ++ vex_printf(","); ++ } ++ } ++ vex_printf("]; "); ++ ++ break; ++ } ++ case SW64in_Mfence: ++ { ++ vex_printf("MEMB;"); ++ vex_printf("IMEMB;\n"); ++ } ++ default: ++ break; ++ } ++} ++ ++/* --------- Helpers for register allocation. --------- */ ++ ++void getRegUsage_SW64Instr(HRegUsage * u, const SW64Instr * i) ++{ ++ initHRegUsage(u); ++ switch (i->tag) ++ { ++ /*----load/store----*/ ++ case SW64in_Load: ++ addHRegUse(u, HRmWrite, i->SW64in.Load.dst); ++ addRegUsage_SW64AModeRI(u, i->SW64in.Load.addr); ++ return; ++ case SW64in_Store: ++ addHRegUse(u, HRmRead, i->SW64in.Store.src); ++ addRegUsage_SW64AModeRI(u, i->SW64in.Store.addr); ++ return; ++ case SW64in_FpLoad: ++ addHRegUse(u, HRmWrite, i->SW64in.FpLoad.dst); ++ addRegUsage_SW64AModeRI(u, i->SW64in.FpLoad.addr); ++ return; ++ case SW64in_FpStore: ++ addHRegUse(u, HRmRead, i->SW64in.FpStore.src); ++ addRegUsage_SW64AModeRI(u, i->SW64in.FpStore.addr); ++ return; ++ case SW64in_LoadImm: ++ addHRegUse(u, HRmWrite, i->SW64in.LoadImm.dst); ++ return; ++ ++ case SW64in_CAS: ++ addHRegUse(u, HRmWrite, i->SW64in.Cas.old); ++ addHRegUse(u, HRmRead, i->SW64in.Cas.expd); ++ addHRegUse(u, HRmRead, i->SW64in.Cas.data); ++ addHRegUse(u, HRmRead, i->SW64in.Cas.addr); ++ return; ++ ++ /*----unop data process----*/ ++ case SW64in_UnOperate: ++ addHRegUse(u, HRmRead, i->SW64in.UnOperate.src); ++ addHRegUse(u, HRmWrite, i->SW64in.UnOperate.dst); ++ return; ++ ++ /*----integer data process----*/ ++ case SW64in_Logic: ++ addHRegUse(u, HRmRead, i->SW64in.Logic.srcL); ++ addRegUsage_SW64RI8(u, i->SW64in.Logic.srcR); ++ addHRegUse(u, HRmWrite, i->SW64in.Logic.dst); ++ return; ++ case SW64in_Cmp: ++ addHRegUse(u, HRmRead, i->SW64in.Cmp.srcL); ++ addRegUsage_SW64RI8(u, i->SW64in.Cmp.srcR); ++ addHRegUse(u, HRmWrite, i->SW64in.Cmp.dst); ++ return; ++ case SW64in_Shft: ++ addHRegUse(u, HRmRead, i->SW64in.Shft.srcL); ++ addRegUsage_SW64RI8(u, i->SW64in.Shft.srcR); ++ addHRegUse(u, HRmWrite, i->SW64in.Shft.dst); ++ return; ++ case SW64in_Arith: ++ addHRegUse(u, HRmRead, i->SW64in.Arith.srcL); ++ addRegUsage_SW64RI8(u, i->SW64in.Arith.srcR); ++ addHRegUse(u, HRmWrite, i->SW64in.Arith.dst); ++ return; ++ case SW64in_IntDiv: ++ addHRegUse(u, HRmRead, i->SW64in.IntDiv.srcL); ++ addHRegUse(u, HRmRead, i->SW64in.IntDiv.srcR); ++ addHRegUse(u, HRmWrite, i->SW64in.IntDiv.dst); ++ return; ++ ++ /*----float data process----*/ ++ case SW64in_FpArith: ++ addHRegUse(u, HRmRead, i->SW64in.FpArith.srcL); ++ addHRegUse(u, HRmRead, i->SW64in.FpArith.srcR); ++ addHRegUse(u, HRmWrite, i->SW64in.FpArith.dst); ++ return; ++ case SW64in_FpGpMove: ++ addHRegUse(u, HRmRead, i->SW64in.FpGpMove.src); ++ addHRegUse(u, HRmWrite, i->SW64in.FpGpMove.dst); ++ return; ++ case SW64in_FpCpy: ++ addHRegUse(u, HRmRead, i->SW64in.FpCpy.src1); ++ addHRegUse(u, HRmRead, i->SW64in.FpCpy.src2); ++ addHRegUse(u, HRmWrite, i->SW64in.FpCpy.dst); ++ return; ++ case SW64in_FpQuary: ++ addHRegUse(u, HRmRead, i->SW64in.FpQuary.src1); ++ addHRegUse(u, HRmRead, i->SW64in.FpQuary.src2); ++ addHRegUse(u, HRmRead, i->SW64in.FpQuary.src3); ++ addHRegUse(u, HRmWrite, i->SW64in.FpQuary.dst); ++ return; ++ case SW64in_FpUnary: ++ addHRegUse(u, HRmRead, i->SW64in.FpUnary.src); ++ addHRegUse(u, HRmWrite, i->SW64in.FpUnary.dst); ++ return; ++ case SW64in_FpSel: ++ addHRegUse(u, HRmRead, i->SW64in.FpSel.iftrue); ++ addHRegUse(u, HRmRead, i->SW64in.FpSel.iffalse); ++ addHRegUse(u, HRmRead, i->SW64in.FpSel.cond); ++ addHRegUse(u, HRmWrite, i->SW64in.FpSel.dst); ++ return; ++ case SW64in_FpCmp: ++ addHRegUse(u, HRmRead, i->SW64in.FpCmp.srcL); ++ addHRegUse(u, HRmRead, i->SW64in.FpCmp.srcR); ++ addHRegUse(u, HRmWrite, i->SW64in.FpCmp.dst); ++ return; ++ case SW64in_FpCvt: ++ addHRegUse(u, HRmRead, i->SW64in.FpCvt.src); ++ addHRegUse(u, HRmWrite, i->SW64in.FpCvt.dst); ++ return; ++ case SW64in_RFPCR: ++ addHRegUse(u, HRmWrite, i->SW64in.RFPCR.dst); ++ return; ++ case SW64in_WFPCR: ++ addHRegUse(u, HRmRead, i->SW64in.WFPCR.src); ++ return; ++ ++ /*----code link----*/ ++ case SW64in_XDirect: ++ addRegUsage_SW64AModeRI(u, i->SW64in.XDirect.amPC); ++ addRegUsage_SW64Cond(u, i->SW64in.XDirect.cond); ++ return; ++ case SW64in_XIndir: ++ addHRegUse(u, HRmRead, i->SW64in.XIndir.dstGA); ++ addRegUsage_SW64AModeRI(u, i->SW64in.XIndir.amPC); ++ addRegUsage_SW64Cond(u, i->SW64in.XIndir.cond); ++ return; ++ case SW64in_XAssisted: ++ addHRegUse(u, HRmRead, i->SW64in.XAssisted.dstGA); ++ addRegUsage_SW64AModeRI(u, i->SW64in.XAssisted.amPC); ++ addRegUsage_SW64Cond(u, i->SW64in.XAssisted.cond); ++ return; ++ ++ /*----cond select ----*/ ++ case SW64in_CondSel: ++ addHRegUse(u, HRmRead, i->SW64in.CondSel.iftrue); ++ addHRegUse(u, HRmRead, i->SW64in.CondSel.iffalse); ++ addHRegUse(u, HRmRead, i->SW64in.CondSel.cond); ++ addHRegUse(u, HRmWrite, i->SW64in.CondSel.dst); ++ return; ++ ++ /*----other ----*/ ++ case SW64in_EvCheck: ++ /* We expect both amodes only to mention %ebp, so this is in ++ fact pointless, since %ebp isn't allocatable, but anyway.. */ ++ addRegUsage_SW64AModeRI(u, i->SW64in.EvCheck.amCounter); ++ addRegUsage_SW64AModeRI(u, i->SW64in.EvCheck.amFailAddr); ++ return; ++ case SW64in_ProfInc: ++ /* does not use any registers. */ ++ return; ++ case SW64in_Call: ++ { ++ /* Logic and comments copied/modified from x86, ppc and arm back end. ++ First off, claim it trashes all the caller-saved regs ++ which fall within the register allocator's jurisdiction. */ ++ addRegUsage_SW64Cond(u, i->SW64in.Call.cond); ++ ++ UInt argir; ++ addHRegUse(u, HRmWrite, hregSW64_R31()); ++ ++ addHRegUse(u, HRmWrite, hregSW64_R28()); ++ addHRegUse(u, HRmWrite, hregSW64_R0()); ++ ++ addHRegUse(u, HRmWrite, hregSW64_R16()); ++ addHRegUse(u, HRmWrite, hregSW64_R17()); ++ addHRegUse(u, HRmWrite, hregSW64_R18()); ++ addHRegUse(u, HRmWrite, hregSW64_R19()); ++ addHRegUse(u, HRmWrite, hregSW64_R20()); ++ addHRegUse(u, HRmWrite, hregSW64_R21()); ++ ++ addHRegUse(u, HRmWrite, hregSW64_R1()); ++ addHRegUse(u, HRmWrite, hregSW64_R2()); ++ addHRegUse(u, HRmWrite, hregSW64_R3()); ++ addHRegUse(u, HRmWrite, hregSW64_R4()); ++ addHRegUse(u, HRmWrite, hregSW64_R5()); ++ addHRegUse(u, HRmWrite, hregSW64_R6()); ++ addHRegUse(u, HRmWrite, hregSW64_R7()); ++ addHRegUse(u, HRmWrite, hregSW64_R8()); ++ addHRegUse(u, HRmWrite, hregSW64_R22()); ++ addHRegUse(u, HRmWrite, hregSW64_R23()); ++ addHRegUse(u, HRmWrite, hregSW64_R24()); ++ addHRegUse(u, HRmWrite, hregSW64_R25()); ++ ++ addHRegUse(u, HRmWrite, hregSW64_R26()); ++ ++ /* Now we have to state any parameter-carrying registers ++ which might be read. This depends on the argiregs field. */ ++ argir = i->SW64in.Call.argiregs; ++ UInt base = 16; ++ if (argir & (1<<(21-base))) addHRegUse(u, HRmRead, hregSW64_R21()); ++ if (argir & (1<<(20-base))) addHRegUse(u, HRmRead, hregSW64_R20()); ++ if (argir & (1<<(19-base))) addHRegUse(u, HRmRead, hregSW64_R19()); ++ if (argir & (1<<(18-base))) addHRegUse(u, HRmRead, hregSW64_R18()); ++ if (argir & (1<<(17-base))) addHRegUse(u, HRmRead, hregSW64_R17()); ++ if (argir & (1<<(16-base))) addHRegUse(u, HRmRead, hregSW64_R16()); ++ ++ vassert(0 == (argir & ~((1 << 0) | (1 << 1) | (1 << 2) ++ | (1 << 3) | (1 << 4) | (1 << 5) ))); ++ ++ return; ++ } ++ ++ case SW64in_Mfence: ++ /* does not use any registers. */ ++ return; ++ ++ default: ++ break; ++ } ++} ++ ++/* local helper */ ++static void mapReg(HRegRemap * m, HReg * r) ++{ ++ *r = lookupHRegRemap(m, *r); ++} ++ ++void mapRegs_SW64Instr(HRegRemap * m, SW64Instr * i) ++{ ++ switch (i->tag) ++ { ++ /*----load/store----*/ ++ case SW64in_Load: ++ mapReg(m, &i->SW64in.Load.dst); ++ mapRegs_SW64AModeRI(m, i->SW64in.Load.addr); ++ return; ++ case SW64in_Store: ++ mapReg(m, &i->SW64in.Store.src); ++ mapRegs_SW64AModeRI(m, i->SW64in.Store.addr); ++ return; ++ case SW64in_FpLoad: ++ mapReg(m, &i->SW64in.FpLoad.dst); ++ mapRegs_SW64AModeRI(m, i->SW64in.FpLoad.addr); ++ return; ++ case SW64in_FpStore: ++ mapReg(m, &i->SW64in.FpStore.src); ++ mapRegs_SW64AModeRI(m, i->SW64in.FpStore.addr); ++ return; ++ case SW64in_LoadImm: ++ mapReg(m, &i->SW64in.LoadImm.dst); ++ return; ++ ++ case SW64in_CAS: ++ mapReg(m, &i->SW64in.Cas.old); ++ mapReg(m, &i->SW64in.Cas.data); ++ mapReg(m, &i->SW64in.Cas.expd); ++ mapReg(m, &i->SW64in.Cas.addr); ++ return; ++ ++ /*----unop data process----*/ ++ case SW64in_UnOperate: ++ mapReg(m, &i->SW64in.UnOperate.src); ++ mapReg(m, &i->SW64in.UnOperate.dst); ++ return; ++ ++ /*----integer data process----*/ ++ case SW64in_Logic: ++ mapReg(m, &i->SW64in.Logic.srcL); ++ mapRegs_SW64RI8(m, i->SW64in.Logic.srcR); ++ mapReg(m, &i->SW64in.Logic.dst); ++ return; ++ case SW64in_Cmp: ++ mapReg(m, &i->SW64in.Cmp.srcL); ++ mapRegs_SW64RI8(m, i->SW64in.Cmp.srcR); ++ mapReg(m, &i->SW64in.Cmp.dst); ++ return; ++ case SW64in_Shft: ++ mapReg(m, &i->SW64in.Shft.srcL); ++ mapRegs_SW64RI8(m, i->SW64in.Shft.srcR); ++ mapReg(m, &i->SW64in.Shft.dst); ++ return; ++ case SW64in_Arith: ++ mapReg(m, &i->SW64in.Arith.srcL); ++ mapRegs_SW64RI8(m, i->SW64in.Arith.srcR); ++ mapReg(m, &i->SW64in.Arith.dst); ++ return; ++ case SW64in_IntDiv: ++ mapReg(m, &i->SW64in.IntDiv.srcL); ++ mapReg(m, &i->SW64in.IntDiv.srcR); ++ mapReg(m, &i->SW64in.IntDiv.dst); ++ return; ++ ++ /*----float data process----*/ ++ case SW64in_FpArith: ++ mapReg(m, &i->SW64in.FpArith.srcL); ++ mapReg(m, &i->SW64in.FpArith.srcR); ++ mapReg(m, &i->SW64in.FpArith.dst); ++ return; ++ case SW64in_FpGpMove: ++ mapReg(m, &i->SW64in.FpGpMove.src); ++ mapReg(m, &i->SW64in.FpGpMove.dst); ++ return; ++ case SW64in_FpCpy: ++ mapReg(m, &i->SW64in.FpCpy.src1); ++ mapReg(m, &i->SW64in.FpCpy.src2); ++ mapReg(m, &i->SW64in.FpCpy.dst); ++ return; ++ case SW64in_FpQuary: ++ mapReg(m, &i->SW64in.FpQuary.src1); ++ mapReg(m, &i->SW64in.FpQuary.src2); ++ mapReg(m, &i->SW64in.FpQuary.src3); ++ mapReg(m, &i->SW64in.FpQuary.dst); ++ return; ++ case SW64in_FpUnary: ++ mapReg(m, &i->SW64in.FpUnary.src); ++ mapReg(m, &i->SW64in.FpUnary.dst); ++ return; ++ case SW64in_FpSel: ++ mapReg(m, &i->SW64in.FpSel.iftrue); ++ mapReg(m, &i->SW64in.FpSel.iffalse); ++ mapReg(m, &i->SW64in.FpSel.cond); ++ mapReg(m, &i->SW64in.FpSel.dst); ++ return; ++ case SW64in_FpCmp: ++ mapReg(m, &i->SW64in.FpCmp.srcL); ++ mapReg(m, &i->SW64in.FpCmp.srcR); ++ mapReg(m, &i->SW64in.FpCmp.dst); ++ return; ++ case SW64in_FpCvt: ++ mapReg(m, &i->SW64in.FpCvt.src); ++ mapReg(m, &i->SW64in.FpCvt.dst); ++ return; ++ case SW64in_RFPCR: ++ mapReg(m, &i->SW64in.RFPCR.dst); ++ return; ++ case SW64in_WFPCR: ++ mapReg(m, &i->SW64in.WFPCR.src); ++ return; ++ ++ /*----code link----*/ ++ case SW64in_XDirect: ++ mapRegs_SW64AModeRI(m, i->SW64in.XDirect.amPC); ++ mapRegs_SW64Cond(m, i->SW64in.XDirect.cond); ++ return; ++ case SW64in_XIndir: ++ mapReg(m, &i->SW64in.XIndir.dstGA); ++ mapRegs_SW64AModeRI(m, i->SW64in.XIndir.amPC); ++ mapRegs_SW64Cond(m, i->SW64in.XIndir.cond); ++ return; ++ case SW64in_XAssisted: ++ mapReg(m, &i->SW64in.XAssisted.dstGA); ++ mapRegs_SW64AModeRI(m, i->SW64in.XAssisted.amPC); ++ mapRegs_SW64Cond(m, i->SW64in.XAssisted.cond); ++ return; ++ ++ /*----cond select ----*/ ++ case SW64in_CondSel: ++ mapReg(m, &i->SW64in.CondSel.iftrue); ++ mapReg(m, &i->SW64in.CondSel.iffalse); ++ mapReg(m, &i->SW64in.CondSel.cond); ++ mapReg(m, &i->SW64in.CondSel.dst); ++ return; ++ ++ /*----other ----*/ ++ case SW64in_EvCheck: ++ /* We expect both modes only to mention %ebp, so this is in ++ fact pointless, since %ebp isn't allocatable, but anyway.. */ ++ mapRegs_SW64AModeRI(m, i->SW64in.EvCheck.amCounter); ++ mapRegs_SW64AModeRI(m, i->SW64in.EvCheck.amFailAddr); ++ return; ++ case SW64in_ProfInc: ++ /* does not use any registers. */ ++ return; ++ ++ case SW64in_Call: ++ mapRegs_SW64Cond(m, i->SW64in.Call.cond); ++ return; ++ ++ case SW64in_Mfence: ++ /* does not use any registers. */ ++ return; ++ ++ default: ++ ppSW64Instr(i); ++ vpanic("mapRegs_SW64Instr"); ++ break; ++ } ++} ++ ++/* Generate sw64 spill/reload instructions under the direction of the ++ register allocator. */ ++void genSpill_SW64( /*OUT*/ HInstr ** i1, /*OUT*/ HInstr ** i2, HReg rreg, ++ Int offsetB) ++{ ++ vassert(offsetB >= 0); ++ vassert(!hregIsVirtual(rreg)); ++ *i1 = *i2 = NULL; ++ SW64AModeRI *addr = SW64AModeRI_IR(offsetB, SW64GuestStateHreg()); ++ ++ switch (hregClass(rreg)) { ++ case HRcInt64: ++ *i1 = SW64Instr_Store(SW64in_STL, rreg, addr); ++ break; ++ case HRcFlt64: ++ *i1 = SW64Instr_FpStore(SW64in_FSTD, rreg, addr); ++ break; ++ default: ++ ppHRegClass(hregClass(rreg)); ++ vpanic("genSpill_SW64: unimplemented regclass"); ++ break; ++ } ++} ++ ++void genReload_SW64( /*OUT*/ HInstr ** i1, /*OUT*/ HInstr ** i2, HReg rreg, ++ Int offsetB) ++{ ++ vassert(!hregIsVirtual(rreg)); ++ SW64AModeRI *addr = SW64AModeRI_IR(offsetB, SW64GuestStateHreg()); ++ ++ switch (hregClass(rreg)) ++ { ++ case HRcInt64: ++ *i1 = SW64Instr_Load(SW64in_LDL, rreg, addr); ++ break; ++ case HRcFlt64: ++ *i1 = SW64Instr_FpLoad(SW64in_FLDD, rreg, addr); ++ break; ++ default: ++ ppHRegClass(hregClass(rreg)); ++ vpanic("genReload_SW64: unimplemented regclass"); ++ break; ++ } ++} ++ ++SW64Instr* genMove_SW64(HReg from, HReg to) ++{ ++ switch (hregClass(from)) ++ { ++ case HRcInt32: ++ case HRcInt64: ++ return SW64Instr_Logic(SW64in_OR, to, from, SW64RI8_Imm(0)); ++ default: ++ ppHRegClass(hregClass(from)); ++ vpanic("genMove_SW64: unimplemented regclass"); ++ } ++} ++ ++/* --------- The sw64 assembler --------- */ ++ ++inline static UInt iregNo(HReg r) ++{ ++ UInt n; ++ vassert(hregClass(r) == HRcInt64); ++ vassert(!hregIsVirtual(r)); ++ n = hregEncoding(r); ++ vassert(n <= 32); ++ return n; ++} ++ ++inline static UInt fregNo(HReg r) ++{ ++ UInt n; ++ vassert(hregClass(r) == HRcFlt64); ++ vassert(!hregIsVirtual(r)); ++ n = hregEncoding(r); ++ vassert(n <= 31); ++ return n; ++} ++ ++inline static UInt toImm(Int simm, Int bits) ++{ ++ vassert(bits <= 31); ++ vassert(simm >= -(1 << (bits - 1)) && simm < (1 << (bits - 1))); ++ return simm & ((1u << bits) - 1); ++} ++ ++/* Emit 32bit instruction */ ++static UChar *emit32(UChar * p, UInt w32) ++{ ++ *p++ = toUChar(w32 & 0x000000FF); ++ *p++ = toUChar((w32 >> 8) & 0x000000FF); ++ *p++ = toUChar((w32 >> 16) & 0x000000FF); ++ *p++ = toUChar((w32 >> 24) & 0x000000FF); ++ return p; ++} ++ ++static Bool is_8_aligned(const UChar* p) ++{ ++ ULong tmp = (((ULong)(p)) & ((ULong)0x7)); ++ return (0 == tmp); ++} ++ ++/* Fetch an instruction */ ++static UInt fetch32 (const UChar* p) ++{ ++ UInt w32 = 0; ++ w32 |= ((0xFF & (UInt)p[0]) << 0); ++ w32 |= ((0xFF & (UInt)p[1]) << 8); ++ w32 |= ((0xFF & (UInt)p[2]) << 16); ++ w32 |= ((0xFF & (UInt)p[3]) << 24); ++ return w32; ++} ++ ++///branch insn format ++/*|31 26 | 25 21 | 20 0|*/ ++/*| opcode | ra | disp |*/ ++static inline UInt X_branch_6_5_21(UInt op, UInt ra, UInt disp) ++{ ++ vassert(6+5+21 == 32); ++ vassert(op < (1<<6)); ++ vassert(ra < (1<<5)); ++ vassert(disp < (1<<21)); ++ UInt w = 0; ++ w = (w << 6) | op; ++ w = (w << 5) | ra; ++ w = (w << 21) | disp; ++ return w; ++} ++ ++///load/store insn format ++/*|31 26 | 25 21 | 20 16| 15 0|*/ ++/*| opcode | ra | rb | disp |*/ ++static inline UInt X_ldst_6_5_5_16(UInt op, UInt ra, UInt rb, UInt disp) ++{ ++ vassert(6+5+5+16 == 32); ++ vassert(op < (1<<6)); ++ vassert(ra < (1<<5)); ++ vassert(rb < (1<<5)); ++ vassert(disp < (1<<16)); ++ UInt w = 0; ++ w = (w << 6) | op; ++ w = (w << 5) | ra; ++ w = (w << 5) | rb; ++ w = (w << 16) | disp; ++ return w; ++} ++ ++///load/store with func insn format ++/*|31 26 | 25 21 | 20 16| 15 12| 11 0|*/ ++/*| opcode | ra | rb | func | disp |*/ ++static inline UInt X_ldst_6_5_5_4_12(UInt op, UInt ra, UInt rb, UInt func, UInt disp) ++{ ++ vassert(6+5+5+4+12 == 32); ++ vassert(op < (1<<6)); ++ vassert(ra < (1<<5)); ++ vassert(rb < (1<<5)); ++ vassert(func < (1<<4)); ++ vassert(disp < (1<<12)); ++ UInt w = 0; ++ w = (w << 6) | op; ++ w = (w << 5) | ra; ++ w = (w << 5) | rb; ++ w = (w << 4) | func; ++ w = (w << 12) | disp; ++ return w; ++} ++ ++///simple calculate insn format ++ /*|31 26 | 25 21 | 20 16| 15 13 |12 5| 4 0|*/ ++ /*| opcode | ra | rb | 000 | function | rc |*/ //register ++static inline UInt X_simreg_6_5_5_3_8_5(UInt op, UInt ra, UInt rb, ++ UInt func, UInt rc) ++{ ++ vassert(op == 0x10 || op == 0x18); ++ vassert(6+5+5+3+8+5 == 32); ++ vassert(op < (1<<6)); ++ vassert(ra < (1<<5)); ++ vassert(rb < (1<<5)); ++ vassert(func < (1<<8)); ++ vassert(rc < (1<<5)); ++ UInt w = 0; ++ w = (w << 6) | op; ++ w = (w << 5) | ra; ++ w = (w << 5) | rb; ++ w = (w << 3) | 0; ++ w = (w << 8) | func; ++ w = (w << 5) | rc; ++ return w; ++} ++ ++///simple calculate insn format ++ /*|31 26 | 25 21 | 20 16| 15 13 |12 5| 4 0|*/ ++ /*| opcode | ra | imm | function | rc |*/ //immediate ++static inline UInt X_simimm_6_5_8_8_5(UInt op, UInt ra, UInt imm, ++ UInt func, UInt rc) ++{ ++ vassert(op == 0x12); ++ vassert(6+5+8+8+5 == 32); ++ vassert(op < (1<<6)); ++ vassert(ra < (1<<5)); ++ vassert(imm < (1<<8)); ++ vassert(func < (1<<8)); ++ vassert(rc < (1<<5)); ++ UInt w = 0; ++ w = (w << 6) | op; ++ w = (w << 5) | ra; ++ w = (w << 8) | imm; ++ w = (w << 8) | func; ++ w = (w << 5) | rc; ++ return w; ++} ++ ++///complex integer calculate insn format ++ /*|31 26 | 25 21 | 20 16| 15 13 |12 10| 9 5 | 4 0 |*/ ++ /*| opcode | ra | rb | 000 | function | rc | rd |*/ //register ++static inline UInt X_comreg_6_5_5_3_3_5_5(UInt op, UInt ra, UInt rb, ++ UInt func, UInt rc, UInt rd) ++{ ++ vassert(op == 0x11); ++ vassert(6+5+5+3+3+5+5 == 32); ++ vassert(op < (1<<6)); ++ vassert(ra < (1<<5)); ++ vassert(rb < (1<<5)); ++ vassert(func < (1<<3)); ++ vassert(rc < (1<<5)); ++ vassert(rd < (1<<5)); ++ UInt w = 0; ++ w = (w << 6) | op; ++ w = (w << 5) | ra; ++ w = (w << 5) | rb; ++ w = (w << 3) | 0; ++ w = (w << 3) | func; ++ w = (w << 5) | rc; ++ w = (w << 5) | rd; ++ return w; ++} ++ ++///complex integer calculate insn format ++ /*|31 26 | 25 21 | 20 16| 15 13 |12 10| 9 5 | 4 0 |*/ ++ /*| opcode | ra | imm | function | rc | rd |*/ //immediate ++static inline UInt X_comimm_6_5_8_3_5_5(UInt op, UInt ra, UInt imm, ++ UInt func, UInt rc, UInt rd) ++{ ++ vassert(op == 0x13); ++ vassert(6+5+8+3+5+5 == 32); ++ vassert(op < (1<<6)); ++ vassert(ra < (1<<5)); ++ vassert(imm < (1<<8)); ++ vassert(func < (1<<3)); ++ vassert(rc < (1<<5)); ++ vassert(rd < (1<<5)); ++ UInt w = 0; ++ w = (w << 6) | op; ++ w = (w << 5) | ra; ++ w = (w << 8) | imm; ++ w = (w << 3) | func; ++ w = (w << 5) | rc; ++ w = (w << 5) | rd; ++ return w; ++} ++ ++///complex float calculate insn format ++ /*|31 26 | 25 21 | 20 16| 15 10 |9 5| 4 0|*/ ++ /*| opcode | fa | fb | func | fc | fd |*/ //register ++static inline UInt X_comfloat_6_5_5_6_5_5(UInt op, UInt fa, UInt fb, ++ UInt func, UInt fc, UInt fd) ++{ ++ vassert(op == 0x19); ++ vassert(6+5+5+6+5+5 == 32); ++ vassert(op < (1<<6)); ++ vassert(fa < (1<<5)); ++ vassert(fb < (1<<5)); ++ vassert(func < (1<<6)); ++ vassert(fc < (1<<5)); ++ vassert(fd < (1<<5)); ++ UInt w = 0; ++ w = (w << 6) | op; ++ w = (w << 5) | fa; ++ w = (w << 5) | fb; ++ w = (w << 6) | func; ++ w = (w << 5) | fc; ++ w = (w << 5) | fd; ++ return w; ++} ++ ++static inline UInt X_nop(void) ++{ ++ /* nop: bis $31, 0, $31 */ ++ return X_simimm_6_5_8_8_5(0x12, 31, 0x0, 0x3A, 31); ++} ++ ++/* Load any 64-bit immediate number, with instructions not above 5, ++ If `fixedsize' is True, emit 5 instructions (20 bytes) exactly. ++ ++ emit instructions below: ++ ++ ldih ra, x3(r31) ++ ldi ra, x2(ra) ++ sll ra, 32, ra ++ ldih ra, x1(ra) ++ ldi ra, x0(ra) ++ ++ Instruction that have no effect will be skipped, which means number of ++ emit instructions may less than 5 if `fixedsize' is False. ++ ++*/ ++static UChar *do_load_imm(UChar * p, UInt ra, ULong imm64, Bool fixedsize) ++{ ++ UChar *begin = p; ++ ++ /* The only crucial part is, ++ how to calculate x[0], x[1], x[2], x[3] from `imm64' ++ ++ ldi/ldih is signed-extend, if x[i] is negative, 0xffffffffffffffff will ++ add higher bits. ++ ++ For cancel out this effect of signed-extend, if x[i] is negative, ++ x[i+1] need to add by one. ++ ++ But this `add-by-1' caused tow tricky problems: ++ 1. add-by-1 may produced a carry, THIS CARRY MUST BE TRANSMITTED TO ++ ALL HIGHER BITS. So, treat all higher bits as a whole number when ++ doing this add-by-1. ++ 2. Because of carry is transmitted to all higher bits, the signed-bit ++ of x[i+1] x[i+2] x[i+3] may changed too. Use this changed value, ++ not origin value, as judging condition of negativity. Because ++ signed-extend is perform on changed value, not origin value. ++ */ ++ UShort x[4]; ++ for (Int i = 0; i < 4; i++) { ++ x[i] = imm64; ++ imm64 >>= 16; ++ if (x[i] >= 0x8000) ++ imm64++; ++ } ++ ++ if (x[3]) ++ p = emit32(p, X_ldst_6_5_5_16(0x3F, ra, begin == p ? 31 : ra, x[3])); ++ ++ if (x[2]) ++ p = emit32(p, X_ldst_6_5_5_16(0x3E, ra, begin == p ? 31 : ra, x[2])); ++ ++ if (p != begin) ++ p = emit32(p, X_simimm_6_5_8_8_5(0x12, ra, 32, 0x48, ra)); ++ ++ if (x[1]) ++ p = emit32(p, X_ldst_6_5_5_16(0x3F, ra, begin == p ? 31 : ra, x[1])); ++ ++ if (x[0] || p == begin) ++ p = emit32(p, X_ldst_6_5_5_16(0x3E, ra, begin == p ? 31 : ra, x[0])); ++ ++ /* Use NOP as padding, which not making extra value dependency */ ++ if (fixedsize) ++ while (p < begin + 20) ++ p = emit32(p, X_nop()); ++ ++ return p; ++} ++ ++static Bool is_load_imm(UChar * p, UInt ra, ULong imm64, Bool fixedsize) ++{ ++ UChar expected[20]; ++ UChar *end = do_load_imm(expected, ra, imm64, fixedsize); ++ ++ for (UInt i = 0; i < end - expected; i += 4) { ++ if (fetch32(p + i) != fetch32(expected + i)) ++ return False; ++ } ++ ++ return True; ++} ++ ++static UChar *do_condition_code_link(UChar *p, ULong delta, SW64Cond *cond) ++{ ++ vassert(fetch32(p) == 0); ++ ++ delta = delta / 4 - 1; ++ vassert(delta >= 0 && delta <= 40); ++ ++ /* condition is reversed */ ++ UInt opc; ++ UInt regNo; ++ switch (cond->code) { ++ case SW64cc_EQ: opc = 0x31; regNo = iregNo(cond->reg); break; ++ case SW64cc_NE: opc = 0x30; regNo = iregNo(cond->reg); break; ++ case SW64cc_LT: opc = 0x35; regNo = iregNo(cond->reg); break; ++ case SW64cc_LE: opc = 0x34; regNo = iregNo(cond->reg); break; ++ case SW64cc_GT: opc = 0x33; regNo = iregNo(cond->reg); break; ++ case SW64cc_GE: opc = 0x32; regNo = iregNo(cond->reg); break; ++ case SW64cc_FEQ: opc = 0x39; regNo = fregNo(cond->reg); break; ++ case SW64cc_FNE: opc = 0x38; regNo = fregNo(cond->reg); break; ++ case SW64cc_FLT: opc = 0x3D; regNo = fregNo(cond->reg); break; ++ case SW64cc_FLE: opc = 0x3C; regNo = fregNo(cond->reg); break; ++ case SW64cc_FGT: opc = 0x3B; regNo = fregNo(cond->reg); break; ++ case SW64cc_FGE: opc = 0x3A; regNo = fregNo(cond->reg); break; ++ default: ++ vassert(0); ++ } ++ ++ return emit32(p, X_branch_6_5_21(opc, regNo, delta)); ++} ++ ++Int emit_SW64Instr ( /*MB_MOD*/Bool* is_profInc, ++ /*MB_MOD*/Bool* is_8aligned, ++ UChar* buf, Int nbuf, const SW64Instr* i, ++ Bool mode64, VexEndness endness_host, ++ const void* disp_cp_chain_me_to_slowEP, ++ const void* disp_cp_chain_me_to_fastEP, ++ const void* disp_cp_xindir, ++ const void* disp_cp_xassisted ) ++{ ++ UChar *p = &buf[0]; ++ vassert(nbuf >= 32); ++ ++ switch (i->tag) ++ { ++ /*----load/store----*/ ++ case SW64in_Load: ++ { ++ UInt dst = iregNo(i->SW64in.Load.dst); ++ UInt base = iregNo(i->SW64in.Load.addr->base); ++ UInt disp = toImm(i->SW64in.Load.addr->disp, 16); ++ UInt opcode = (i->SW64in.Load.op == SW64in_LDBU) ? 0x20 : ++ (i->SW64in.Load.op == SW64in_LDHU) ? 0x21 : ++ (i->SW64in.Load.op == SW64in_LDW) ? 0x22 : ++ (i->SW64in.Load.op == SW64in_LDL) ? 0x23 : ++ (vassert(0), 0); ++ p = emit32(p, X_ldst_6_5_5_16(opcode, dst, base, disp)); ++ goto done; ++ } ++ case SW64in_Store: ++ { ++ UInt src = iregNo(i->SW64in.Store.src); ++ UInt base = iregNo(i->SW64in.Store.addr->base); ++ UInt disp = toImm(i->SW64in.Store.addr->disp, 16); ++ UInt opcode = (i->SW64in.Store.op == SW64in_STB) ? 0x28 : ++ (i->SW64in.Store.op == SW64in_STH) ? 0x29 : ++ (i->SW64in.Store.op == SW64in_STW) ? 0x2A : ++ (i->SW64in.Store.op == SW64in_STL) ? 0x2B : ++ (vassert(0), 0); ++ p = emit32(p, X_ldst_6_5_5_16(opcode, src, base, disp)); ++ goto done; ++ } ++ case SW64in_FpLoad: ++ { ++ UInt dst = fregNo(i->SW64in.FpLoad.dst); ++ UInt base = iregNo(i->SW64in.FpLoad.addr->base); ++ UInt disp = toImm(i->SW64in.FpLoad.addr->disp, 16); ++ UInt opcode = (i->SW64in.FpLoad.op == SW64in_FLDS) ? 0x26 : ++ (i->SW64in.FpLoad.op == SW64in_FLDD) ? 0x27 : ++ (vassert(0), 0); ++ p = emit32(p, X_ldst_6_5_5_16(opcode, dst, base, disp)); ++ goto done; ++ } ++ case SW64in_FpStore: ++ { ++ UInt src = fregNo(i->SW64in.FpStore.src); ++ UInt base = iregNo(i->SW64in.FpStore.addr->base); ++ UInt disp = toImm(i->SW64in.FpStore.addr->disp, 16); ++ UInt opcode = (i->SW64in.FpStore.op == SW64in_FSTS) ? 0x2E : ++ (i->SW64in.FpStore.op == SW64in_FSTD) ? 0x2F : ++ (vassert(0), 0); ++ p = emit32(p, X_ldst_6_5_5_16(opcode, src, base, disp)); ++ goto done; ++ } ++ case SW64in_LoadImm: ++ { ++ UInt rDst = iregNo(i->SW64in.LoadImm.dst); ++ p = do_load_imm(p, rDst, i->SW64in.LoadImm.imm64, False); ++ goto done; ++ } ++ ++ case SW64in_CAS: ++ { ++ vassert(!(*is_8aligned)); ++ vassert(!sameHReg(i->SW64in.Cas.old, i->SW64in.Cas.data)); ++ vassert(!sameHReg(i->SW64in.Cas.old, i->SW64in.Cas.expd)); ++ vassert(!sameHReg(i->SW64in.Cas.old, i->SW64in.Cas.addr)); ++ ++ UInt old = iregNo(i->SW64in.Cas.old); ++ UInt expd = iregNo(i->SW64in.Cas.expd); ++ UInt data = iregNo(i->SW64in.Cas.data); ++ UInt addr = iregNo(i->SW64in.Cas.addr); ++ Bool isSize4 = toBool(i->SW64in.Cas.sz == 4); ++ ++ /* */ ++ if (!is_8_aligned(p)) { ++ p = emit32(p, X_nop()); ++ } ++ ++ /* ++ 0: lld* %[old], 0(%[addr]) ++ cmpeq %[old], %[expd], $1 ++ wr_f $1 ++ mov %[data], $2 ++ lst* $2, 0(%[addr]) ++ rd_f $2 ++ beq $1, 1f # data != expd, fail ++ beq $2, 0b # CAS failed, try again ++ 1: ++ */ ++ p = emit32(p, X_ldst_6_5_5_4_12(0x08, old, addr, isSize4? 0x0: 0x1, 0x0)); ++ p = emit32(p, X_simreg_6_5_5_3_8_5(0x10, old, expd, 0x28, 1)); ++ p = emit32(p, X_ldst_6_5_5_16(0x06, 1, 31, 0x1020)); ++ p = emit32(p, X_simimm_6_5_8_8_5(0x12, data, 0x0, 0x3A, 2)); ++ p = emit32(p, X_ldst_6_5_5_4_12(0x08, 2, addr, isSize4? 0x8: 0x9, 0x0)); ++ p = emit32(p, X_ldst_6_5_5_16(0x06, 2, 31, 0x1000)); ++ p = emit32(p, X_branch_6_5_21(0x30, 1, 0x1)); ++ p = emit32(p, X_branch_6_5_21(0x30, 2, 0x1ffff8)); ++ ++ *is_8aligned = True; ++ goto done; ++ } ++ ++ /*----unop data process----*/ ++ case SW64in_UnOperate: ++ { ++ UInt rDst = iregNo(i->SW64in.UnOperate.dst); ++ UInt rSrc = iregNo(i->SW64in.UnOperate.src); ++ switch (i->SW64in.UnOperate.op) ++ { ++ case SW64in_POP: ++ { ++ /*CTPOP rb(src), rc(dst) */ ++ /*opcode=0x10, func=0x58 */ ++ UInt instr = X_simreg_6_5_5_3_8_5(0x10, 0, rSrc, 0x58, rDst); ++ p = emit32(p, instr); ++ goto done; ++ } ++ case SW64in_CLZ: ++ { ++ /*CTLZ rb(src), rc(dst)*/ ++ /*opcode=0x10, func=0x59 */ ++ UInt instr = X_simreg_6_5_5_3_8_5(0x10, 0, rSrc, 0x59, rDst); ++ p = emit32(p, instr); ++ goto done; ++ } ++ case SW64in_CTZ: ++ { ++ /*CTTZ rb(src), rc(dst) */ ++ /*opcode=0x10, func=0x5A */ ++ UInt instr = X_simreg_6_5_5_3_8_5(0x10, 0, rSrc, 0x5A, rDst); ++ p = emit32(p, instr); ++ goto done; ++ } ++ default: ++ break; ++ } ++ goto bad; ++ } ++ ++ /*----integer data process----*/ ++ case SW64in_Logic: ++ { ++ UInt rSrcL = iregNo(i->SW64in.Logic.srcL); ++ UInt rDst = iregNo(i->SW64in.Logic.dst); ++ vassert(rSrcL < 32); ++ vassert(rDst < 32); ++ SW64RI8* srcR = i->SW64in.Logic.srcR; ++ ++ UInt func = 0x00; /* invalid */ ++ switch (i->SW64in.Logic.op) ++ { ++ case SW64in_AND: func = 0x38; break; ++ case SW64in_BIC: func = 0x39; break; ++ case SW64in_OR: func = 0x3A; break; ++ case SW64in_ORNOT: func = 0x3B; break; ++ case SW64in_XOR: func = 0x3C; break; ++ default: break; ++ } ++ vassert(func != 0); ++ switch(srcR->tag) ++ { ++ case Sri8_Imm: ++ { ++ UInt opcode = 0x12; ++ UInt imm = (UInt)srcR->Sri8.Imm.imm8; ++ UInt instr = X_simimm_6_5_8_8_5(opcode, rSrcL, imm, func, rDst); ++ p = emit32(p, instr); ++ goto done; ++ } ++ case Sri8_Reg: ++ { ++ UInt opcode = 0x10; ++ UInt rb = iregNo(srcR->Sri8.Reg.reg); ++ UInt instr = X_simreg_6_5_5_3_8_5(opcode, rSrcL, rb, func, rDst); ++ p = emit32(p, instr); ++ goto done; ++ } ++ default: break; ++ } ++ ++ goto bad; ++ } ++ case SW64in_Cmp: ++ { ++ UInt rSrcL = iregNo(i->SW64in.Cmp.srcL); ++ UInt rDst = iregNo(i->SW64in.Cmp.dst); ++ vassert(rSrcL < 32); ++ vassert(rDst < 32); ++ ++ SW64RI8 *srcR = i->SW64in.Cmp.srcR; ++ vassert(srcR->tag == Sri8_Reg || srcR->tag == Sri8_Imm); ++ ++ UInt func; ++ switch (i->SW64in.Cmp.op) { ++ case SW64in_CMPEQ: func = 0x28; break; ++ case SW64in_CMPLT: func = 0x29; break; ++ case SW64in_CMPLE: func = 0x2A; break; ++ case SW64in_CMPULT: func = 0x2B; break; ++ case SW64in_CMPULE: func = 0x2C; break; ++ default: vassert(0); ++ } ++ ++ if (srcR->tag == Sri8_Reg) { ++ UInt rSrcR = iregNo(srcR->Sri8.Reg.reg); ++ p = emit32(p, X_simreg_6_5_5_3_8_5(0x10, rSrcL, rSrcR, func, rDst)); ++ } else { ++ UInt imm = srcR->Sri8.Imm.imm8; ++ p = emit32(p, X_simimm_6_5_8_8_5(0x12, rSrcL, imm, func, rDst)); ++ } ++ ++ goto done; ++ } ++ case SW64in_Shft: ++ { ++ UInt rSrcL = iregNo(i->SW64in.Shft.srcL); ++ UInt rDst = iregNo(i->SW64in.Shft.dst); ++ vassert(rSrcL < 32); ++ vassert(rDst < 32); ++ SW64RI8* srcR = i->SW64in.Shft.srcR; ++ ++ UInt func = 0x00; /* invalid */ ++ switch (i->SW64in.Shft.op) ++ { ++ case SW64in_SLL: func = 0x48; break; ++ case SW64in_SRL: func = 0x49; break; ++ case SW64in_SRA: func = 0x4A; break; ++ default: break; ++ } ++ vassert(func != 0); ++ switch(srcR->tag) ++ { ++ case Sri8_Imm: ++ { ++ UInt opcode = 0x12; ++ UInt imm = (UInt)srcR->Sri8.Imm.imm8; ++ UInt instr = X_simimm_6_5_8_8_5(opcode, rSrcL, imm, func, rDst); ++ p = emit32(p, instr); ++ goto done; ++ } ++ case Sri8_Reg: ++ { ++ UInt opcode = 0x10; ++ UInt rb = iregNo(srcR->Sri8.Reg.reg); ++ UInt instr = X_simreg_6_5_5_3_8_5(opcode, rSrcL, rb, func, rDst); ++ p = emit32(p, instr); ++ goto done; ++ } ++ default: break; ++ } ++ ++ goto bad; ++ } ++ case SW64in_Arith: ++ { ++ UInt rSrcL = iregNo(i->SW64in.Arith.srcL); ++ UInt rDst = iregNo(i->SW64in.Arith.dst); ++ vassert(rSrcL < 32); ++ vassert(rDst < 32); ++ SW64RI8* srcR = i->SW64in.Arith.srcR; ++ ++ UInt func = 0xFF; /* invalid */ ++ switch (i->SW64in.Arith.op) ++ { ++ case SW64in_ADDW: func = 0x00; break; ++ case SW64in_SUBW: func = 0x01; break; ++ case SW64in_S4ADDW: func = 0x02; break; ++ case SW64in_S4SUBW: func = 0x03; break; ++ case SW64in_S8ADDW: func = 0x04; break; ++ case SW64in_S8SUBW: func = 0x05; break; ++ case SW64in_ADDL: func = 0x08; break; ++ case SW64in_SUBL: func = 0x09; break; ++ case SW64in_S4ADDL: func = 0x0A; break; ++ case SW64in_S4SUBL: func = 0x0B; break; ++ case SW64in_S8ADDL: func = 0x0C; break; ++ case SW64in_S8SUBL: func = 0x0D; break; ++ case SW64in_MULW: func = 0x10; break; ++ case SW64in_MULL: func = 0x18; break; ++ case SW64in_UMULH: func = 0x19; break; ++ case SW64in_ZAP: func = 0x68; break; ++ case SW64in_ZAPNOT: func = 0x69; break; ++ case SW64in_SEXTB: func = 0x6A; break; ++ case SW64in_SEXTH: func = 0x6B; break; ++ default: break; ++ } ++ vassert(func != 0xFF); ++ switch(srcR->tag) ++ { ++ case Sri8_Imm: ++ { ++ UInt opcode = 0x12; ++ UInt imm = (UInt)srcR->Sri8.Imm.imm8; ++ UInt instr = X_simimm_6_5_8_8_5(opcode, rSrcL, imm, func, rDst); ++ p = emit32(p, instr); ++ goto done; ++ } ++ case Sri8_Reg: ++ { ++ UInt opcode = 0x10; ++ UInt rb = iregNo(srcR->Sri8.Reg.reg); ++ UInt instr = X_simreg_6_5_5_3_8_5(opcode, rSrcL, rb, func, rDst); ++ p = emit32(p, instr); ++ goto done; ++ } ++ default: break; ++ } ++ ++ goto bad; ++ } ++ case SW64in_IntDiv: ++ { ++ UInt rSrcL = iregNo(i->SW64in.IntDiv.srcL); ++ UInt rSrcR = iregNo(i->SW64in.IntDiv.srcR); ++ UInt rDst = iregNo(i->SW64in.IntDiv.dst); ++ ++ vassert(rSrcL < 32); ++ vassert(rSrcR < 32); ++ vassert(rDst < 32); ++ ++ UInt func = 0xFF; /* invalid */ ++ switch (i->SW64in.IntDiv.op) ++ { ++ case SW64in_DIVW: func = 0x11; break; ++ case SW64in_UDIVW: func = 0x12; break; ++ case SW64in_REMW: func = 0x13; break; ++ case SW64in_UREMW: func = 0x14; break; ++ case SW64in_DIVL: func = 0x1A; break; ++ case SW64in_UDIVL: func = 0x1B; break; ++ case SW64in_REML: func = 0x1C; break; ++ case SW64in_UREML: func = 0x1D; break; ++ default: break; ++ } ++ vassert(func != 0xFF); ++ ++ UInt opcode = 0x10; ++ UInt instr = X_simreg_6_5_5_3_8_5(opcode, rSrcL, rSrcR, func, rDst); ++ p = emit32(p, instr); ++ goto done; ++ } ++ ++ /*----float data process----*/ ++ case SW64in_FpArith: ++ { ++ UInt rSrcL = fregNo(i->SW64in.FpArith.srcL); ++ UInt rSrcR = fregNo(i->SW64in.FpArith.srcR); ++ UInt rDst = fregNo(i->SW64in.FpArith.dst); ++ vassert(rSrcL < 32); ++ vassert(rSrcR < 32); ++ vassert(rDst < 32); ++ vassert(rSrcL != rDst && rSrcR != rDst); ++ ++ UInt opcode = 0x18; ++ UInt func = 0xFF; /* INVALID */ ++ switch (i->SW64in.FpArith.op) ++ { ++ case SW64in_FADDS: func = 0x00; break; ++ case SW64in_FADDD: func = 0x01; break; ++ case SW64in_FSUBS: func = 0x02; break; ++ case SW64in_FSUBD: func = 0x03; break; ++ case SW64in_FMULS: func = 0x04; break; ++ case SW64in_FMULD: func = 0x05; break; ++ case SW64in_FDIVS: func = 0x06; break; ++ case SW64in_FDIVD: func = 0x07; break; ++ default: break; ++ } ++ vassert(func != 0xFF); ++ ++ /*op fa, fb, fc*/ ++ UInt instr = X_simreg_6_5_5_3_8_5(opcode, rSrcL, rSrcR, func, rDst); ++ p = emit32(p, instr); ++ goto done; ++ } ++ ++ /* move/convert between GPR and FPR */ ++ case SW64in_FpGpMove: ++ { ++ UInt rSrc = 32; ++ UInt rDst = 32; ++ UInt opcode = 0xFF; ++ switch(i->SW64in.FpGpMove.op) ++ { ++ case SW64in_FIMOVS: ++ case SW64in_FIMOVD: ++ case SW64in_CMOVDL: ++ case SW64in_CMOVDL_G: ++ case SW64in_CMOVDL_P: ++ case SW64in_CMOVDL_Z: ++ case SW64in_CMOVDL_N: ++ case SW64in_CMOVDLU: ++ case SW64in_CMOVDLU_G: ++ case SW64in_CMOVDLU_P: ++ case SW64in_CMOVDLU_Z: ++ case SW64in_CMOVDLU_N: ++ case SW64in_CMOVDWU: ++ case SW64in_CMOVDWU_G: ++ case SW64in_CMOVDWU_P: ++ case SW64in_CMOVDWU_Z: ++ case SW64in_CMOVDWU_N: ++ case SW64in_CMOVDW: ++ case SW64in_CMOVDW_G: ++ case SW64in_CMOVDW_P: ++ case SW64in_CMOVDW_Z: ++ case SW64in_CMOVDW_N: ++ { ++ rSrc = fregNo(i->SW64in.FpGpMove.src); ++ rDst = iregNo(i->SW64in.FpGpMove.dst); ++ opcode = 0x10; ++ break; ++ } ++ case SW64in_IFMOVS: ++ case SW64in_IFMOVD: ++ case SW64in_CMOVLS: ++ case SW64in_CMOVWS: ++ case SW64in_CMOVLD: ++ case SW64in_CMOVWD: ++ case SW64in_CMOVULS: ++ case SW64in_CMOVUWS: ++ case SW64in_CMOVULD: ++ case SW64in_CMOVUWD: ++ { ++ rSrc = iregNo(i->SW64in.FpGpMove.src); ++ rDst = fregNo(i->SW64in.FpGpMove.dst); ++ opcode = 0x18; ++ break; ++ } ++ default: break; ++ } ++ vassert(rSrc < 32); ++ vassert(rDst < 32); ++ vassert(opcode != 0xFF); ++ ++ UInt func; ++ UInt ra = 0; ++ UInt rb = 0; ++ switch (i->SW64in.FpGpMove.op) ++ { ++ case SW64in_FIMOVS: func = 0x70; ra = rSrc; break; ++ case SW64in_FIMOVD: func = 0x78; ra = rSrc; break; ++ case SW64in_IFMOVS: func = 0x40; ra = rSrc; break; ++ case SW64in_IFMOVD: func = 0x41; ra = rSrc; break; ++ case SW64in_CMOVDL: func = 0x72; rb = rSrc; break; ++ case SW64in_CMOVDL_G: func = 0x74; rb = rSrc; break; ++ case SW64in_CMOVDL_P: func = 0x7a; rb = rSrc; break; ++ case SW64in_CMOVDL_Z: func = 0x7c; rb = rSrc; break; ++ case SW64in_CMOVDL_N: func = 0x80; rb = rSrc; break; ++ case SW64in_CMOVDLU: func = 0x81; rb = rSrc; break; ++ case SW64in_CMOVDLU_G: func = 0x82; rb = rSrc; break; ++ case SW64in_CMOVDLU_P: func = 0x83; rb = rSrc; break; ++ case SW64in_CMOVDLU_Z: func = 0x84; rb = rSrc; break; ++ case SW64in_CMOVDLU_N: func = 0x85; rb = rSrc; break; ++ case SW64in_CMOVDWU: func = 0x86; rb = rSrc; break; ++ case SW64in_CMOVDWU_G: func = 0x87; rb = rSrc; break; ++ case SW64in_CMOVDWU_P: func = 0x88; rb = rSrc; break; ++ case SW64in_CMOVDWU_Z: func = 0x89; rb = rSrc; break; ++ case SW64in_CMOVDWU_N: func = 0x8a; rb = rSrc; break; ++ case SW64in_CMOVDW: func = 0x8b; rb = rSrc; break; ++ case SW64in_CMOVDW_G: func = 0x8c; rb = rSrc; break; ++ case SW64in_CMOVDW_P: func = 0x8d; rb = rSrc; break; ++ case SW64in_CMOVDW_Z: func = 0x8e; rb = rSrc; break; ++ case SW64in_CMOVDW_N: func = 0x8f; rb = rSrc; break; ++ case SW64in_CMOVLS: func = 0x48; rb = rSrc; break; ++ case SW64in_CMOVWS: func = 0x49; rb = rSrc; break; ++ case SW64in_CMOVLD: func = 0x4a; rb = rSrc; break; ++ case SW64in_CMOVWD: func = 0x4b; rb = rSrc; break; ++ case SW64in_CMOVULS: func = 0x4c; rb = rSrc; break; ++ case SW64in_CMOVUWS: func = 0x4d; rb = rSrc; break; ++ case SW64in_CMOVULD: func = 0x4e; rb = rSrc; break; ++ case SW64in_CMOVUWD: func = 0x4f; rb = rSrc; break; ++ default: vassert(0); ++ } ++ ++ UInt instr = X_simreg_6_5_5_3_8_5(opcode, ra, rb, func, rDst); ++ p = emit32(p, instr); ++ goto done; ++ } ++ case SW64in_FpCpy: ++ { ++ UInt rSrcA = fregNo(i->SW64in.FpCpy.src1); ++ UInt rSrcB = fregNo(i->SW64in.FpCpy.src2); ++ UInt rDst = fregNo(i->SW64in.FpCpy.dst); ++ vassert(rSrcA < 32); ++ vassert(rSrcB < 32); ++ vassert(rDst < 32); ++ vassert(rSrcA != rDst && rSrcB != rDst); ++ ++ SW64FpCpyOp op = i->SW64in.FpCpy.op; ++ UInt func = (op == SW64in_FCPYS) ? 0x30 : ++ (op == SW64in_FCPYSE) ? 0x31 : ++ (op == SW64in_FCPYSN) ? 0x32 : ++ (vassert(0), 0); ++ ++ UInt instr = X_simreg_6_5_5_3_8_5(0x18, rSrcA, rSrcB, func, rDst); ++ p = emit32(p, instr); ++ goto done; ++ } ++ case SW64in_FpQuary: ++ { ++ UInt rSrc1 = fregNo(i->SW64in.FpQuary.src1); //fa ++ UInt rSrc2 = fregNo(i->SW64in.FpQuary.src2); //fb ++ UInt rSrc3 = fregNo(i->SW64in.FpQuary.src3); //fc ++ UInt rDst = fregNo(i->SW64in.FpQuary.dst); //fd ++ vassert(rSrc1 < 32); ++ vassert(rSrc2 < 32); ++ vassert(rSrc3 < 32); ++ vassert(rDst < 32); ++ vassert(rSrc1 != rDst && rSrc2 != rDst && rSrc3 != rDst); ++ ++ UInt opcode = 0x19; ++ UInt func = 0xFF; /* INVALID */ ++ switch (i->SW64in.FpQuary.op) ++ { ++ case SW64in_MADDS: func = 0x00; break; ++ case SW64in_MSUBS: func = 0x02; break; ++ case SW64in_MADDD: func = 0x01; break; ++ case SW64in_MSUBD: func = 0x03; break; ++ default: break; ++ } ++ vassert(func != 0xFF); ++ ++ /*op fa, fb, fc, fd*/ ++ UInt instr = X_comfloat_6_5_5_6_5_5(opcode, rSrc1, rSrc2, ++ func, rSrc3, rDst); ++ p = emit32(p, instr); ++ goto done; ++ } ++ case SW64in_FpUnary: ++ { ++ UInt rSrc = fregNo(i->SW64in.FpUnary.src); /* fb */ ++ UInt rDst = fregNo(i->SW64in.FpUnary.dst); /* fc */ ++ vassert(rSrc < 32); ++ vassert(rDst < 32); ++ vassert(rSrc != rDst); ++ ++ SW64FpUnaryOp op = i->SW64in.FpUnary.op; ++ UInt func = (op == SW64in_FSQRTS) ? 0x8 : ++ (op == SW64in_FSQRTD) ? 0x9 : ++ (op == SW64in_FRECS) ? 0x58 : ++ (op == SW64in_FRECD) ? 0x59 : ++ (op == SW64in_FRIS) ? 0x5a : ++ (op == SW64in_FRIS_G) ? 0x5b : ++ (op == SW64in_FRIS_P) ? 0x5c : ++ (op == SW64in_FRIS_Z) ? 0x5d : ++ (op == SW64in_FRIS_N) ? 0x5f : ++ (op == SW64in_FRID) ? 0x60 : ++ (op == SW64in_FRID_G) ? 0x61 : ++ (op == SW64in_FRID_P) ? 0x62 : ++ (op == SW64in_FRID_Z) ? 0x63 : ++ (op == SW64in_FRID_N) ? 0x64 : ++ (vassert(0), 0); ++ ++ UInt instr = X_simreg_6_5_5_3_8_5(0x18, rSrc, rSrc, func, rDst); ++ p = emit32(p, instr); ++ goto done; ++ } ++ case SW64in_FpCmp: ++ { ++ UInt rSrcL = fregNo(i->SW64in.FpCmp.srcL); ++ UInt rSrcR = fregNo(i->SW64in.FpCmp.srcR); ++ UInt rDst = fregNo(i->SW64in.FpCmp.dst); ++ vassert(rSrcL < 32); ++ vassert(rSrcR < 32); ++ vassert(rDst < 32); ++ vassert(rSrcL != rDst && rSrcR != rDst); ++ ++ UInt opcode = 0x18; ++ UInt func = 0xFF; /* INVALID */ ++ switch (i->SW64in.FpCmp.op) ++ { ++ case SW64in_CMPFEQ: func = 0x10; break; ++ case SW64in_CMPFLE: func = 0x11; break; ++ case SW64in_CMPFLT: func = 0x12; break; ++ case SW64in_CMPFUN: func = 0x13; break; ++ default: break; ++ } ++ vassert(func != 0xFF); ++ ++ /*op fa, fb, fc*/ ++ UInt instr = X_simreg_6_5_5_3_8_5(opcode, rSrcL, rSrcR, func, rDst); ++ p = emit32(p, instr); ++ ++ goto done; ++ } ++ case SW64in_FpCvt: ++ { ++ UInt rSrc = fregNo(i->SW64in.FpCvt.src); ++ UInt rDst = fregNo(i->SW64in.FpCvt.dst); ++ vassert(rSrc < 32); ++ vassert(rDst < 32); ++ vassert(rSrc != rDst); ++ ++ UInt opcode = 0x18; ++ UInt func = 0xFF; /* INVALID */ ++ switch (i->SW64in.FpCvt.op) ++ { ++ case SW64in_FCVTSD: func = 0x20; break; ++ case SW64in_FCVTDS: func = 0x21; break; ++ case SW64in_FCVTDL: func = 0x27; break; ++ case SW64in_FCVTLS: func = 0x2D; break; ++ case SW64in_FCVTLD: func = 0x2F; break; ++ case SW64in_FCVTDL_G: func = 0x22; break; ++ case SW64in_FCVTDL_P: func = 0x23; break; ++ case SW64in_FCVTDL_Z: func = 0x24; break; ++ case SW64in_FCVTDL_N: func = 0x25; break; ++ default: break; ++ } ++ vassert(func != 0xFF); ++ UInt instr = X_simreg_6_5_5_3_8_5(opcode, 0, rSrc, func, rDst); ++ p = emit32(p, instr); ++ goto done; ++ } ++ case SW64in_RFPCR: ++ { ++ UInt rDst = fregNo(i->SW64in.RFPCR.dst); ++ UInt instr = X_simreg_6_5_5_3_8_5(0x18, rDst, 0, 0x50, 0); ++ p = emit32(p, instr); ++ goto done; ++ } ++ case SW64in_WFPCR: ++ { ++ UInt rSrc = fregNo(i->SW64in.WFPCR.src); ++ UInt instr = X_simreg_6_5_5_3_8_5(0x18, rSrc, 0, 0x51, 0); ++ p = emit32(p, instr); ++ goto done; ++ } ++ ++ /*----code link----*/ ++ case SW64in_XDirect: ++ { ++ /* NB: what goes on here has to be very closely coordinated ++ with the chainXDirect_SW64 and unchainXDirect_SW64 below. */ ++ /* We're generating chain-me requests here, so we need to be ++ sure this is actually allowed -- no-redir translations ++ can't use chain-me's. Hence: */ ++ vassert(disp_cp_chain_me_to_slowEP != NULL); ++ vassert(disp_cp_chain_me_to_fastEP != NULL); ++ ++ /* Use ptmp for backpatching conditional jumps. */ ++ UChar *ptmp = NULL; ++ ++ /* First off, if this is conditional, create a conditional ++ jump over the rest of it. Or at least, leave a space for ++ it that we will shortly fill in. */ ++ if (i->SW64in.XDirect.cond->code != SW64cc_AL) ++ { ++ ptmp = p; ++ p = emit32(p, 0); ++ } ++ ++ /* Update the guest PC. */ ++ /* ldi r2, XDirect.dstGA */ ++ p = do_load_imm(p, 2, i->SW64in.XDirect.dstGA, False); ++ ++ /* stl r2, XDirect.amPC */ ++ p = emit32(p, X_ldst_6_5_5_16(0x2B, 2, ++ iregNo(i->SW64in.XDirect.amPC->base), ++ toImm(i->SW64in.XDirect.amPC->disp, 16))); ++ ++ /* --- FIRST PATCHABLE BYTE follows --- */ ++ /* VG_(disp_cp_chain_me_to_{slowEP,fastEP}) (where we're ++ calling to) backs up the return address, so as to find the ++ address of the first patchable byte. So: don't change the ++ number of instructions (3) below. */ ++ /* move r2, VG_(disp_cp_chain_me_to_{slowEP,fastEP}) */ ++ ++ const void* disp_cp_chain_me ++ = i->SW64in.XDirect.toFastEP ? disp_cp_chain_me_to_fastEP ++ : disp_cp_chain_me_to_slowEP; ++ ++ /* ldi r2, disp_cp_chain_me */ ++ p = do_load_imm(p, 2, (Addr)disp_cp_chain_me, True); ++ ++ /* jmp r1, (r2) */ ++ UInt instr = X_ldst_6_5_5_16(0x3, 1, 2, 0); ++ p = emit32(p, instr); ++ /* --- END of PATCHABLE BYTES --- */ ++ ++ /* Fix up the conditional jump, if there was one. */ ++ if (i->SW64in.XDirect.cond->code != SW64cc_AL) ++ do_condition_code_link(ptmp, p - ptmp, ++ i->SW64in.XDirect.cond); ++ ++ goto done; ++ } ++ case SW64in_XIndir: ++ { ++ /* We're generating transfers that could lead indirectly to a ++ chain-me, so we need to be sure this is actually allowed -- ++ no-redir translations are not allowed to reach normal ++ translations without going through the scheduler. That means ++ no XDirects or XIndirs out from no-redir translations. ++ Hence: */ ++ vassert(disp_cp_xindir != NULL); ++ ++ /* Use ptmp for backpatching conditional jumps. */ ++ UChar *ptmp = NULL; ++ ++ /* First off, if this is conditional, create a conditional ++ jump over the rest of it. */ ++ if (i->SW64in.XIndir.cond->code != SW64cc_AL) { ++ ptmp = p; ++ p = emit32(p, 0); ++ } ++ ++ /* stl XIndir.dstGA, XIndir.amPC */ ++ p = emit32(p, X_ldst_6_5_5_16(0x2B, iregNo(i->SW64in.XIndir.dstGA), ++ iregNo(i->SW64in.XIndir.amPC->base), ++ toImm(i->SW64in.XIndir.amPC->disp, 16))); ++ ++ /* ldi r2, disp_cp_xindir */ ++ p = do_load_imm(p, 2, (ULong)disp_cp_xindir, False); ++ ++ /* jmp r31, (r2) */ ++ UInt instr = X_ldst_6_5_5_16(0x3, 31, 2, 0); ++ p = emit32(p, instr); ++ ++ /* Fix up the conditional jump, if there was one. */ ++ if (i->SW64in.XIndir.cond->code != SW64cc_AL) ++ do_condition_code_link(ptmp, p - ptmp, ++ i->SW64in.XIndir.cond); ++ ++ goto done; ++ } ++ case SW64in_XAssisted: ++ { ++ /* Use ptmp for backpatching conditional jumps. */ ++ UChar *ptmp = NULL; ++ ++ /* First off, if this is conditional, create a conditional ++ jump over the rest of it. */ ++ if (i->SW64in.XAssisted.cond->code != SW64cc_AL) ++ { ++ ptmp = p; ++ p = emit32(p, 0); ++ } ++ ++ /* stl XAssisted.dstGA, XAssisted.amPC */ ++ p = emit32(p, X_ldst_6_5_5_16(0x2B, iregNo(i->SW64in.XAssisted.dstGA), ++ iregNo(i->SW64in.XAssisted.amPC->base), ++ toImm(i->SW64in.XAssisted.amPC->disp, 16))); ++ ++ /* imm32/64 r31, $magic_number */ ++ UInt trcval = 0; ++ switch (i->SW64in.XAssisted.jk) { ++ case Ijk_ClientReq: trcval = VEX_TRC_JMP_CLIENTREQ; break; ++ case Ijk_Sys_syscall: trcval = VEX_TRC_JMP_SYS_SYSCALL; break; ++ /* case Ijk_Sys_int128: trcval = VEX_TRC_JMP_SYS_INT128; break; */ ++ case Ijk_Yield: trcval = VEX_TRC_JMP_YIELD; break; ++ case Ijk_EmWarn: trcval = VEX_TRC_JMP_EMWARN; break; ++ case Ijk_EmFail: trcval = VEX_TRC_JMP_EMFAIL; break; ++ /* case Ijk_MapFail: trcval = VEX_TRC_JMP_MAPFAIL; break; */ ++ case Ijk_NoDecode: trcval = VEX_TRC_JMP_NODECODE; break; ++ case Ijk_InvalICache: trcval = VEX_TRC_JMP_INVALICACHE; break; ++ case Ijk_NoRedir: trcval = VEX_TRC_JMP_NOREDIR; break; ++ case Ijk_SigILL: trcval = VEX_TRC_JMP_SIGILL; break; ++ case Ijk_SigTRAP: trcval = VEX_TRC_JMP_SIGTRAP; break; ++ /* case Ijk_SigSEGV: trcval = VEX_TRC_JMP_SIGSEGV; break; */ ++ case Ijk_SigBUS: trcval = VEX_TRC_JMP_SIGBUS; break; ++ case Ijk_SigFPE_IntDiv: trcval = VEX_TRC_JMP_SIGFPE_INTDIV; break; ++ case Ijk_SigFPE_IntOvf: trcval = VEX_TRC_JMP_SIGFPE_INTOVF; break; ++ case Ijk_Boring: trcval = VEX_TRC_JMP_BORING; break; ++ /* We don't expect to see the following being assisted. ++ case Ijk_Ret: ++ case Ijk_Call: ++ fallthrough */ ++ default: ++ ppIRJumpKind(i->SW64in.XAssisted.jk); ++ vpanic("emit_SW64Instr.SW64in_XAssisted: unexpected jump kind"); ++ } ++ vassert(trcval != 0); ++ ++ p = do_load_imm(p, SW64GuestStateRegno(), trcval, False); ++ ++ /* ldi r2, disp_cp_xassisted */ ++ p = do_load_imm(p, 2, (ULong)disp_cp_xassisted, False); ++ ++ /* jmp r31, (r2) */ ++ UInt instr = X_ldst_6_5_5_16(0x3, 31, 2, 0); ++ p = emit32(p, instr); ++ ++ /* Fix up the conditional jump, if there was one. */ ++ if (i->SW64in.XAssisted.cond->code != SW64cc_AL) ++ do_condition_code_link(ptmp, p - ptmp, ++ i->SW64in.XAssisted.cond); ++ ++ goto done; ++ } ++ ++ /*----cond select ----*/ ++ case SW64in_CondSel: ++ { ++ UInt rIftrue = iregNo(i->SW64in.CondSel.iftrue); ++ UInt rIffalse = iregNo(i->SW64in.CondSel.iffalse); ++ UInt rCond = iregNo(i->SW64in.CondSel.cond); ++ UInt rDst = iregNo(i->SW64in.CondSel.dst); ++ vassert(rCond < 32); ++ vassert(rIftrue < 32); ++ vassert(rIffalse < 32); ++ vassert(rDst < 32); ++ ++ UInt opcode; ++ switch (i->SW64in.CondSel.op) { ++ case SW64in_SELEQ: opcode = 0x0; break; ++ case SW64in_SELGE: opcode = 0x1; break; ++ case SW64in_SELGT: opcode = 0x2; break; ++ case SW64in_SELLE: opcode = 0x3; break; ++ case SW64in_SELLT: opcode = 0x4; break; ++ case SW64in_SELNE: opcode = 0x5; break; ++ case SW64in_SELLBC: opcode = 0x6; break; ++ case SW64in_SELLBS: opcode = 0x7; break; ++ default: vassert(0); ++ } ++ ++ UInt instr = X_comreg_6_5_5_3_3_5_5(0x11, rCond, rIftrue, opcode, rIffalse, rDst); ++ p = emit32(p, instr); ++ goto done; ++ } ++ case SW64in_FpSel: ++ { ++ UInt rcond = fregNo(i->SW64in.FpSel.cond); //cond, Ity_F64 ++ UInt rIftrue = fregNo(i->SW64in.FpSel.iftrue); ++ UInt rIffalse = fregNo(i->SW64in.FpSel.iffalse); ++ UInt rDst = fregNo(i->SW64in.FpSel.dst); ++ vassert(rcond < 32); ++ vassert(rIftrue < 32); ++ vassert(rIffalse < 32); ++ vassert(rDst < 32); ++ ++ UInt func = (i->SW64in.FpSel.op == SW64in_FSELEQ) ? 0x10 : ++ (i->SW64in.FpSel.op == SW64in_FSELNE) ? 0x11 : ++ (i->SW64in.FpSel.op == SW64in_FSELLT) ? 0x12 : ++ (i->SW64in.FpSel.op == SW64in_FSELLE) ? 0x13 : ++ (i->SW64in.FpSel.op == SW64in_FSELGT) ? 0x14 : ++ (i->SW64in.FpSel.op == SW64in_FSELGE) ? 0x15 : ++ (vassert(0), 0); ++ ++ UInt instr = X_comfloat_6_5_5_6_5_5(0x19, rcond, rIftrue, func, rIffalse, rDst); ++ p = emit32(p, instr); ++ goto done; ++ } ++ ++ /*----other ----*/ ++ case SW64in_EvCheck: ++ { ++ /* This requires a 32-bit dec/test in 32 mode. */ ++ /* We generate: ++ ldw r2, amCounter ++ subl r2, 1, r2 ++ stw r2, amCounter ++ bge r2, nofail ++ ldl r2, amFailAddr ++ jmp r31, (r2) ++ nofail: ++ */ ++ UChar* p0 = p; ++ UInt instr = 0; ++ /* ldw r2, amCounter */ ++ p = emit32(p, X_ldst_6_5_5_16(0x22, 2, ++ iregNo(i->SW64in.EvCheck.amCounter->base), ++ toImm(i->SW64in.EvCheck.amCounter->disp, 16))); ++ ++ /* subl r2, 1, r2 */ ++ instr = X_simimm_6_5_8_8_5(0x12, 2, 1, 0x09, 2); ++ p = emit32(p, instr); ++ ++ /* stw r2, amCounter */ ++ p = emit32(p, X_ldst_6_5_5_16(0x2A, 2, ++ iregNo(i->SW64in.EvCheck.amCounter->base), ++ toImm(i->SW64in.EvCheck.amCounter->disp, 16))); ++ ++ /* bge r2, nofail */ ++ instr = X_branch_6_5_21(0x35, 2, 2); ++ p = emit32(p, instr); ++ ++ /* ldl r2, amFailAddr */ ++ p = emit32(p, X_ldst_6_5_5_16(0x23, 2, ++ iregNo(i->SW64in.EvCheck.amFailAddr->base), ++ toImm(i->SW64in.EvCheck.amFailAddr->disp, 16))); ++ ++ /* jmp r31, (r2) */ ++ instr = X_ldst_6_5_5_16(0x3, 31, 2, 0); ++ p = emit32(p, instr); ++ /* nofail: */ ++ ++ /* Crosscheck */ ++ vassert(evCheckSzB_SW64() == (UChar*)p - (UChar*)p0); ++ goto done; ++ } ++ case SW64in_ProfInc: ++ { ++ /* Generate a code template to increment a memory location whose ++ address will be known later as an immediate value. This code ++ template will be patched once the memory location is known. ++ For now we do this with address == 0x65556555. */ ++ ++ /* 64-bit: ++ move r2, 0x6555655565556555ULL ++ ldl r1, 0(r2) ++ addl r1, 1, r1 ++ stl r1, 0(r2) */ ++ ++ UInt instr = 0; ++ ++ /* move r2, 0x6555655565556555ULL */ ++ p = do_load_imm(p, 2, 0x6555655565556555ULL, True); ++ ++ /* ldl r1, 0(r2) */ ++ instr = X_ldst_6_5_5_16(0x23, 1, 2, 0); ++ p = emit32(p, instr); ++ ++ /* addl r1, 1, r1 */ ++ instr = X_simimm_6_5_8_8_5(0x12, 1, 1, 0x08, 1); ++ p = emit32(p, instr); ++ ++ /* stl r1, 0(r2) */ ++ instr = X_ldst_6_5_5_16(0x2B, 1, 2, 0); ++ p = emit32(p, instr); ++ ++ /* Tell the caller .. */ ++ vassert(!(*is_profInc)); ++ *is_profInc = True; ++ goto done; ++ } ++ ++ case SW64in_Call: ++ { ++ if (i->SW64in.Call.cond->code != SW64cc_AL ++ && i->SW64in.Call.rloc.pri != RLPri_None) ++ { ++ /* The call might not happen (it isn't unconditional) and ++ it returns a result. In this case we will need to ++ generate a control flow diamond to put 0x555..555 in ++ the return register(s) in the case where the call ++ doesn't happen. If this ever becomes necessary, maybe ++ copy code from the ARM equivalent. Until that day, ++ just give up. */ ++ goto bad; ++ } ++ ++ /* Use ptmp for backpatching conditional jumps. */ ++ UChar *ptmp = NULL; ++ ++ /* First off, if this is conditional, create a conditional ++ jump over the rest of it. */ ++ if (i->SW64in.Call.cond->code != SW64cc_AL) ++ { ++ ptmp = p; ++ p = emit32(p, 0); ++ } ++ ++ /* ldi $27, target */ ++ p = do_load_imm(p, 27, i->SW64in.Call.target, False); ++ ++ /* prefer use call, not jmp, for better return address prediction */ ++ /* call $26, ($27) */ ++ p = emit32(p, X_ldst_6_5_5_16(0x1, 26, 27, 0)); ++ ++ /* Fix up the conditional jump, if there was one. */ ++ if (i->SW64in.Call.cond->code != SW64cc_AL) ++ do_condition_code_link(ptmp, p - ptmp, ++ i->SW64in.Call.cond); ++ ++ goto done; ++ } ++ ++ case SW64in_Mfence: ++ { ++ /* MEMB */ ++ UInt instr = X_ldst_6_5_5_16(0x06, 0x0, 0x0, 0x0); ++ p = emit32(p, instr); ++ /* IMEMB */ ++ instr = X_ldst_6_5_5_16(0x06, 0x0, 0x0, 0x1); ++ p = emit32(p, instr); ++ goto done; ++ } ++ ++ default: ++ goto bad; ++ } ++ ++ bad: ++ vex_printf("\n=> "); ++ ppSW64Instr(i); ++ vpanic("emit_SW64Instr"); ++ /* NOTREACHED */ ++ done: ++ /* debug logger */ ++ // vex_printf("\n=> "); ++ // ppSW64Instr(i); ++ ++ /* vex_printf("p-&buf[0] = %ld\n", (p - &buf[0])); */ ++ vassert(p - &buf[0] <= 256); ++ return (p - &buf[0]); ++} ++ ++ ++/* How big is an event check? See case for Min_EvCheck in ++ emit_SW64Instr just above. That crosschecks what this returns, so ++ we can tell if we're inconsistent. */ ++Int evCheckSzB_SW64 (void) ++{ ++ UInt kInstrSize = 4; ++ return 6 * kInstrSize; ++} ++ ++/* NB: what goes on here has to be very closely coordinated with the ++ emitInstr case for XDirect, above. */ ++VexInvalRange chainXDirect_SW64 ( VexEndness endness_host, ++ void* place_to_chain, ++ const void* disp_cp_chain_me_EXPECTED, ++ const void* place_to_jump_to) ++{ ++ vassert(endness_host == VexEndnessLE); ++ UChar* p = (UChar*)place_to_chain; ++ vassert(0 == (3 & (HWord)p)); ++ ++ /* What we're expecting to see is: ++ --- ++ ldi r2, disp_cp_chain_me # 20 bytes ++ jmp r1, (r2) # 4 bytes ++ --- ++ And we patch them to either: ++ --- (prefer, faster) ++ br place_to_jump_to ++ nop ++ nop ++ nop ++ nop ++ nop ++ --- (fallback) ++ ldi r2, place_to_jump_to # 20 bytes ++ jmp r31, (r2) # 4 bytes ++ --- ++ */ ++ ++ vassert(is_load_imm(p, 2, (Addr)disp_cp_chain_me_EXPECTED, True)); ++ vassert(fetch32(p + 20) == X_ldst_6_5_5_16(0x3, 1, 2, 0)); ++ ++ ULong disp = (ULong)place_to_jump_to - (ULong)place_to_chain - 4; ++ vassert((disp & 0x3) == 0); ++ disp >>= 2; ++ ++ if (disp >= ~0xFFFFFULL || disp <= 0xFFFFFULL) { ++ p = emit32(p, X_branch_6_5_21(0x4, 31, disp)); ++ p = emit32(p, X_nop()); ++ p = emit32(p, X_nop()); ++ p = emit32(p, X_nop()); ++ p = emit32(p, X_nop()); ++ p = emit32(p, X_nop()); ++ } else { ++ p = do_load_imm(p, 2, (Addr)place_to_jump_to, True); ++ p = emit32(p, X_ldst_6_5_5_16(0x3, 31, 2, 0)); ++ } ++ ++ UInt len = p - (UChar*)place_to_chain; ++ vassert(len == 24); /* stay sane */ ++ VexInvalRange vir = {(HWord)place_to_chain, len}; ++ return vir; ++} ++ ++/* NB: what goes on here has to be very closely coordinated with the ++ emitInstr case for XDirect, above. */ ++VexInvalRange unchainXDirect_SW64 ( VexEndness endness_host, ++ void* place_to_unchain, ++ const void* place_to_jump_to_EXPECTED, ++ const void* disp_cp_chain_me) ++{ ++ vassert(endness_host == VexEndnessLE); ++ UChar* p = (UChar*)place_to_unchain; ++ vassert(0 == (3 & (HWord)p)); ++ ++ /* What we're expecting to see is either: ++ --- ++ br place_to_jump_to ++ nop ++ nop ++ nop ++ nop ++ nop ++ --- or ++ ldi r2, place_to_jump_to # 20 bytes ++ jmp r31, (r2) # 4 bytes ++ --- ++ And we patch them to: ++ --- ++ ldi r2, disp_cp_chain_me # 20 bytes ++ jmp r1, (r2) # 4 bytes ++ --- ++ */ ++ ++ ULong disp = (ULong)place_to_jump_to_EXPECTED - (ULong)place_to_unchain - 4; ++ vassert((disp & 0x3) == 0); ++ disp >>= 2; ++ ++ if (disp >= ~0xFFFFFULL || disp <= 0xFFFFFULL) { ++ vassert(fetch32(p + 0) == X_branch_6_5_21(0x4, 31, disp)); ++ vassert(fetch32(p + 4) == X_nop()); ++ vassert(fetch32(p + 8) == X_nop()); ++ vassert(fetch32(p + 12) == X_nop()); ++ vassert(fetch32(p + 16) == X_nop()); ++ vassert(fetch32(p + 20) == X_nop()); ++ } else { ++ vassert(is_load_imm(p, 2, (Addr)place_to_jump_to_EXPECTED, True)); ++ vassert(fetch32(p + 20) == X_ldst_6_5_5_16(0x3, 31, 2, 0)); ++ } ++ ++ p = do_load_imm(p, 2, (Addr)disp_cp_chain_me, True); ++ p = emit32(p, X_ldst_6_5_5_16(0x3, 1, 2, 0)); ++ ++ UInt len = p - (UChar*)place_to_unchain; ++ vassert(len == 24); /* stay sane */ ++ VexInvalRange vir = {(HWord)place_to_unchain, len}; ++ return vir; ++} ++ ++/* Patch the counter address into a profile inc point, as previously ++ created by the Min_ProfInc case for emit_MIPSInstr. */ ++VexInvalRange patchProfInc_SW64 ( VexEndness endness_host, ++ void* place_to_patch, ++ const ULong* location_of_counter) ++{ ++ vassert(endness_host == VexEndnessLE); ++ vassert(sizeof(ULong*) == 8); ++ ++ UChar* p = (UChar*)place_to_patch; ++ vassert(0 == (3 & (HWord)p)); ++ ++ /* What we're expecting to see is: ++ <20 bytes generated by do_load_imm> # ldi r2, 0x6555655565556555 ++ 0x8C220000 # ldl r1, 0(r2) ++ 0x48202101 # addl r1, 1, r1 ++ 0xAC220000 # stl r1, 0(r2) ++ */ ++ vassert(is_load_imm(p, 2, 0x6555655565556555ULL, True)); ++ vassert(fetch32(p + 20 + 0) == 0x8C220000); ++ vassert(fetch32(p + 20 + 4) == 0x48202101); ++ vassert(fetch32(p + 20 + 8) == 0xAC220000); ++ ++ p = do_load_imm(p, 2, (Addr)location_of_counter, True); ++ ++ VexInvalRange vir = {(HWord)p, 8}; ++ return vir; ++} ++/*---------------------------------------------------------------*/ ++/*--- end host_sw64_defs.c ---*/ ++/*---------------------------------------------------------------*/ +diff --git a/VEX/priv/host_sw64_defs.h b/VEX/priv/host_sw64_defs.h +new file mode 100644 +index 000000000..b4b81818e +--- /dev/null ++++ b/VEX/priv/host_sw64_defs.h +@@ -0,0 +1,687 @@ ++ ++/*---------------------------------------------------------------*/ ++/*--- begin host_arm64_defs.h ---*/ ++/*---------------------------------------------------------------*/ ++ ++/* ++ This file is part of Valgrind, a dynamic binary instrumentation ++ framework. ++ ++ Copyright (C) 2013-2017 OpenWorks ++ info@open-works.net ++ ++ This program is free software; you can redistribute it and/or ++ modify it under the terms of the GNU General Public License as ++ published by the Free Software Foundation; either version 2 of the ++ License, or (at your option) any later version. ++ ++ This program is distributed in the hope that it will be useful, but ++ WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with this program; if not, see . ++ ++ The GNU General Public License is contained in the file COPYING. ++*/ ++ ++#ifndef __VEX_HOST_SW64_DEFS_H ++#define __VEX_HOST_SW64_DEFS_H ++ ++#include "libvex_basictypes.h" ++#include "libvex.h" // VexArch ++#include "host_generic_regs.h" // HReg ++#include "libvex_guest_sw64.h" // VexGuestSW64State ++#include "main_util.h" // offsetof ++ ++/* --------- Registers. --------- */ ++/* ++ r0 - r2 temporary, reserved for temporary use ++ r3 - r8 temporary, available to reg-alloc ++ r9 - r12 saved, available to reg-alloc ++ r13 saved, reserved for future use ++ r14 saved, reserved for saving host fpcr ++ r15 saved, reserved for VexGuestState pointer ++ r16 - r25 temporary, available to reg-alloc ++ r26 - r27 reserved for dirty call ++ r28 - r30 reserved belong to host ++*/ ++#define ST_IN static inline ++ ++ST_IN HReg hregSW64_R16 ( void ) { return mkHReg(False, HRcInt64, 16, 0); } ++ST_IN HReg hregSW64_R17 ( void ) { return mkHReg(False, HRcInt64, 17, 1); } ++ST_IN HReg hregSW64_R18 ( void ) { return mkHReg(False, HRcInt64, 18, 2); } ++ST_IN HReg hregSW64_R19 ( void ) { return mkHReg(False, HRcInt64, 19, 3); } ++ST_IN HReg hregSW64_R20 ( void ) { return mkHReg(False, HRcInt64, 20, 4); } ++ST_IN HReg hregSW64_R21 ( void ) { return mkHReg(False, HRcInt64, 21, 5); } ++ST_IN HReg hregSW64_R22 ( void ) { return mkHReg(False, HRcInt64, 22, 6); } ++ST_IN HReg hregSW64_R23 ( void ) { return mkHReg(False, HRcInt64, 23, 7); } ++ST_IN HReg hregSW64_R24 ( void ) { return mkHReg(False, HRcInt64, 24, 8); } ++ST_IN HReg hregSW64_R25 ( void ) { return mkHReg(False, HRcInt64, 25, 9); } ++ST_IN HReg hregSW64_R3 ( void ) { return mkHReg(False, HRcInt64, 3, 10); } ++ST_IN HReg hregSW64_R4 ( void ) { return mkHReg(False, HRcInt64, 4, 11); } ++ST_IN HReg hregSW64_R5 ( void ) { return mkHReg(False, HRcInt64, 5, 12); } ++ST_IN HReg hregSW64_R6 ( void ) { return mkHReg(False, HRcInt64, 6, 13); } ++ST_IN HReg hregSW64_R7 ( void ) { return mkHReg(False, HRcInt64, 7, 14); } ++ST_IN HReg hregSW64_R8 ( void ) { return mkHReg(False, HRcInt64, 8, 15); } ++ST_IN HReg hregSW64_R9 ( void ) { return mkHReg(False, HRcInt64, 9, 16); } ++ST_IN HReg hregSW64_R10 ( void ) { return mkHReg(False, HRcInt64, 10, 17); } ++ST_IN HReg hregSW64_R11 ( void ) { return mkHReg(False, HRcInt64, 11, 18); } ++ST_IN HReg hregSW64_R12 ( void ) { return mkHReg(False, HRcInt64, 12, 19); } ++ ++ST_IN HReg hregSW64_F2 ( void ) { return mkHReg(False, HRcFlt64, 2, 20); } ++ST_IN HReg hregSW64_F3 ( void ) { return mkHReg(False, HRcFlt64, 3, 21); } ++ST_IN HReg hregSW64_F4 ( void ) { return mkHReg(False, HRcFlt64, 4, 22); } ++ST_IN HReg hregSW64_F5 ( void ) { return mkHReg(False, HRcFlt64, 5, 23); } ++ST_IN HReg hregSW64_F6 ( void ) { return mkHReg(False, HRcFlt64, 6, 24); } ++ST_IN HReg hregSW64_F7 ( void ) { return mkHReg(False, HRcFlt64, 7, 25); } ++ST_IN HReg hregSW64_F8 ( void ) { return mkHReg(False, HRcFlt64, 8, 26); } ++ST_IN HReg hregSW64_F9 ( void ) { return mkHReg(False, HRcFlt64, 9, 27); } ++ ++ST_IN HReg hregSW64_R0 ( void ) { return mkHReg(False, HRcInt64, 0, 28); } ++ST_IN HReg hregSW64_R1 ( void ) { return mkHReg(False, HRcInt64, 1, 29); } ++ST_IN HReg hregSW64_R2 ( void ) { return mkHReg(False, HRcInt64, 2, 30); } ++ST_IN HReg hregSW64_R13 ( void ) { return mkHReg(False, HRcInt64, 13, 31); } ++ST_IN HReg hregSW64_R14 ( void ) { return mkHReg(False, HRcInt64, 14, 32); } ++ST_IN HReg hregSW64_R15 ( void ) { return mkHReg(False, HRcInt64, 15, 33); } ++ ++ST_IN HReg hregSW64_R26 ( void ) { return mkHReg(False, HRcInt64, 26, 34); } ++ST_IN HReg hregSW64_R27 ( void ) { return mkHReg(False, HRcInt64, 27, 35); } ++ST_IN HReg hregSW64_R28 ( void ) { return mkHReg(False, HRcInt64, 28, 36); } ++ST_IN HReg hregSW64_R29 ( void ) { return mkHReg(False, HRcInt64, 29, 37); } ++ST_IN HReg hregSW64_R30 ( void ) { return mkHReg(False, HRcInt64, 30, 38); } ++ST_IN HReg hregSW64_R31 ( void ) { return mkHReg(False, HRcInt64, 31, 39); } ++ ++ST_IN HReg hregSW64_F31 ( void ) { return mkHReg(False, HRcFlt64, 31, 40); } ++ ++#undef ST_IN ++ ++#define SW64GuestStateHreg() hregSW64_R15() ++#define SW64GuestStateRegno() iregNo(SW64GuestStateHreg()) ++#define SW64Zero() hregSW64_R31() ++#define SW64StackPointer() hregSW64_R30() ++#define SW64_R31_OFFSET() offsetof(VexGuestSW64State, guest_r31) ++#define SW64_F31_OFFSET() offsetof(VexGuestSW64State, guest_f31) ++#define SW64_LOCKFLAG_OFFSET() offsetof(VexGuestSW64State, guest_LOCKFLAG) ++ ++/* Number of registers used arg passing in function calls */ ++#define SW64_N_ARGREGS 6 /* a0 .. a5 */ ++ ++extern UInt ppHRegSW64 ( HReg ); ++ ++/* --------- Memory address expressions (amodes). --------- */ ++ ++/*! SW64 偏移寻址模式. ++ * SW64 6B 仅支持这种寻址模式，即 <欲访问的内存地址> = <基址寄存器的值> + <偏移量立即数> ++ * 其中基址寄存器可以是任何整形通用寄存器，偏移量立即数可以是 16 位有符号整数， ++ * 若寄存器为 $r31 则退化为绝对寻址，若偏移量为 0 则退化为间接寻址 ++ */ ++typedef struct { ++ HReg base; ++ Int disp; ++} SW64AModeRI; ++ ++extern SW64AModeRI *SW64AModeRI_IR(Int, HReg); ++extern void ppSW64AModeRI (SW64AModeRI *); ++ ++//--------------------------------------------INTRUCTION---------------------------------------// ++typedef enum { ++ SW64cc_EQ, /* BEQ SELEQ */ ++ SW64cc_NE, /* BNE SELNE */ ++ SW64cc_LT, /* BLT SELLT */ ++ SW64cc_LE, /* BLE SELLE */ ++ SW64cc_GT, /* BGT SELGT */ ++ SW64cc_GE, /* BGE SELGE */ ++ SW64cc_FEQ, /* FBEQ FSELEQ */ ++ SW64cc_FNE, /* FBNE FSELNE */ ++ SW64cc_FLT, /* FBLT FSELLT */ ++ SW64cc_FLE, /* FBLE FSELLE */ ++ SW64cc_FGT, /* FBGT FSELGT */ ++ SW64cc_FGE, /* FBGE FSELGE */ ++ SW64cc_AL, /* always (unconditional) */ ++} SW64CondCode; ++ ++ ++typedef struct { ++ SW64CondCode code; ++ HReg reg; ++} SW64Cond; ++ ++extern SW64Cond *SW64Cond_Cond(SW64CondCode code, HReg reg); ++extern SW64Cond *SW64Cond_ALWAYS(void); ++ ++extern void ppSW64Cond(const SW64Cond *); ++ ++ ++/* --------- Operand, which can be a reg or a u16/s16. --------- */ ++/* ("RI8" == "Register or byte immediate") */ ++typedef enum { ++ Sri8_Imm, ++ Sri8_Reg ++} SW64RI8Tag; ++ ++typedef struct { ++ SW64RI8Tag tag; ++ union { ++ struct { ++ UChar imm8; ++ } Imm; ++ struct { ++ HReg reg; ++ } Reg; ++ } Sri8; ++} SW64RI8; ++extern void ppSW64RI8(SW64RI8 *); ++ ++extern SW64RI8 *SW64RI8_Imm(UChar); ++extern SW64RI8 *SW64RI8_Reg(HReg); ++ ++/* ----- Each Classes Instruction tags ----- */ ++ ++typedef enum { ++ SW64in_LDBU, SW64in_LDHU, SW64in_LDW, SW64in_LDL ++} SW64LoadOp; ++extern const HChar *showSW64LoadOp(SW64LoadOp); ++ ++typedef enum { ++ SW64in_STB, SW64in_STH, SW64in_STW, SW64in_STL ++} SW64StoreOp; ++extern const HChar *showSW64StoreOp(SW64StoreOp); ++ ++typedef enum { ++ SW64in_FLDS, SW64in_FLDD ++} SW64FpLoadOp; ++extern const HChar *showSW64FpLoadOp(SW64FpLoadOp); ++ ++typedef enum { ++ SW64in_FSTS, SW64in_FSTD ++} SW64FpStoreOp; ++extern const HChar *showSW64FpStoreOp(SW64FpStoreOp); ++ ++ ++typedef enum { ++ SW64in_AND, SW64in_OR, SW64in_XOR, SW64in_BIC, SW64in_ORNOT ++} SW64LogicOp; ++extern const HChar *showSW64LogicOp(SW64LogicOp); ++ ++typedef enum { ++ SW64in_ADDW, SW64in_ADDL, SW64in_SUBW, SW64in_SUBL, ++ SW64in_S4ADDW, SW64in_S4ADDL, SW64in_S4SUBW, SW64in_S4SUBL, ++ SW64in_S8ADDW, SW64in_S8ADDL, SW64in_S8SUBW, SW64in_S8SUBL, ++ SW64in_MULW, SW64in_MULL, ++ SW64in_UMULH, SW64in_ZAP, ++ SW64in_ZAPNOT, SW64in_SEXTB, SW64in_SEXTH ++} SW64ArithOp; ++extern const HChar *showSW64ArithOp(SW64ArithOp); ++ ++typedef enum { ++ SW64in_DIVW, SW64in_UDIVW, SW64in_DIVL, SW64in_UDIVL, ++ SW64in_REMW, SW64in_UREMW, SW64in_REML, SW64in_UREML, ++} SW64IntDivOp; ++extern const HChar *showSW64IntDivOp(SW64IntDivOp); ++ ++typedef enum { ++ SW64in_CMPEQ, ++ SW64in_CMPLT, SW64in_CMPLE, ++ SW64in_CMPULT, SW64in_CMPULE ++} SW64CmpOp; ++extern const HChar *showSW64CmpOp(SW64CmpOp); ++ ++typedef enum{ ++ SW64in_POP, SW64in_CLZ, SW64in_CTZ ++} SW64UnOp; ++extern const HChar *showSW64UnaryOp(SW64UnOp); ++ ++typedef enum{ ++ SW64in_SLL, SW64in_SRL, SW64in_SRA ++} SW64ShftOp; ++extern const HChar *showSW64ShftOp(SW64ShftOp); ++ ++typedef enum{ ++ SW64in_SELEQ, SW64in_SELGE, SW64in_SELGT, SW64in_SELLE, ++ SW64in_SELLT, SW64in_SELNE, SW64in_SELLBC, SW64in_SELLBS ++} SW64CondSelOp; ++extern const HChar *showSW64CondSelOp(SW64CondSelOp); ++ ++typedef enum{ ++ SW64in_FADDS, SW64in_FADDD, SW64in_FSUBS, SW64in_FSUBD, ++ SW64in_FMULS, SW64in_FMULD, SW64in_FDIVS, SW64in_FDIVD ++} SW64FpArithOp; ++extern const HChar *showSW64FpArithOp(SW64FpArithOp); ++ ++typedef enum{ ++ SW64in_FIMOVS, SW64in_FIMOVD, SW64in_IFMOVS, SW64in_IFMOVD, ++ SW64in_CMOVDL, SW64in_CMOVDL_G, SW64in_CMOVDL_P, SW64in_CMOVDL_Z, SW64in_CMOVDL_N, ++ SW64in_CMOVDLU, SW64in_CMOVDLU_G, SW64in_CMOVDLU_P, SW64in_CMOVDLU_Z, SW64in_CMOVDLU_N, ++ SW64in_CMOVDWU, SW64in_CMOVDWU_G, SW64in_CMOVDWU_P, SW64in_CMOVDWU_Z, SW64in_CMOVDWU_N, ++ SW64in_CMOVDW, SW64in_CMOVDW_G, SW64in_CMOVDW_P, SW64in_CMOVDW_Z, SW64in_CMOVDW_N, ++ SW64in_CMOVLS, SW64in_CMOVWS, SW64in_CMOVLD, SW64in_CMOVWD, ++ SW64in_CMOVULS, SW64in_CMOVUWS, SW64in_CMOVULD, SW64in_CMOVUWD ++} SW64FpGpMoveOp; ++extern const HChar *showSW64FpGpMoveOp(SW64FpGpMoveOp); ++ ++typedef enum{ ++ SW64in_FCPYS, SW64in_FCPYSE, SW64in_FCPYSN ++} SW64FpCpyOp; ++extern const HChar *showSW64FpCpyOp(SW64FpCpyOp); ++ ++typedef enum{ ++ SW64in_MADDS, SW64in_MSUBS, SW64in_MADDD, SW64in_MSUBD ++} SW64FpQuaryOp; ++extern const HChar *showSW64FpQuaryOp(SW64FpQuaryOp); ++ ++typedef enum{ ++ SW64in_FSQRTS, SW64in_FSQRTD, ++ SW64in_FRECS, SW64in_FRECD, ++ SW64in_FRIS, SW64in_FRIS_G, SW64in_FRIS_P, SW64in_FRIS_Z, SW64in_FRIS_N, ++ SW64in_FRID, SW64in_FRID_G, SW64in_FRID_P, SW64in_FRID_Z, SW64in_FRID_N ++} SW64FpUnaryOp; ++extern const HChar *showSW64FpUnaryOp(SW64FpUnaryOp); ++ ++typedef enum{ ++ SW64in_CMPFEQ, SW64in_CMPFLE, SW64in_CMPFLT, SW64in_CMPFUN ++} SW64FpCmpOp; ++extern const HChar *showSW64FpCmpOp(SW64FpCmpOp); ++ ++typedef enum{ ++ SW64in_FSELEQ, SW64in_FSELNE, SW64in_FSELLT, SW64in_FSELLE, ++ SW64in_FSELGT, SW64in_FSELGE ++} SW64FpSelOp; ++extern const HChar *showSW64FpSelOp(SW64FpSelOp); ++ ++typedef enum{ ++ SW64in_FCVTSD, SW64in_FCVTDS, SW64in_FCVTDL, SW64in_FCVTLS, SW64in_FCVTLD, ++ SW64in_FCVTDL_G, SW64in_FCVTDL_P, SW64in_FCVTDL_Z, SW64in_FCVTDL_N ++} SW64FpCvtOp; ++extern const HChar *showSW64FpCvtOp(SW64FpCvtOp); ++ ++/* ----- Instruction tags ----- */ ++typedef enum { ++ ++ /*----load/store----*/ ++ SW64in_Load, ++ SW64in_Store, ++ SW64in_FpLoad, ++ SW64in_FpStore, ++ SW64in_LoadImm, //load imm ++ ++ /*----unop data process----*/ ++ SW64in_UnOperate, ++ ++ /*----integer data process----*/ ++ SW64in_Logic, ++ SW64in_Cmp, ++ SW64in_Shft, ++ SW64in_Arith, ++ SW64in_IntDiv, ++ ++ /*----float data process----*/ ++ SW64in_FpArith, ++ SW64in_FpGpMove, ++ SW64in_FpCpy, ++ SW64in_FpQuary, ++ SW64in_FpUnary, ++ SW64in_FpSel, ++ SW64in_FpCmp, ++ SW64in_FpCvt, ++ SW64in_RFPCR, ++ SW64in_WFPCR, ++ ++ /*----code link----*/ ++ SW64in_XDirect, ++ SW64in_XIndir, ++ SW64in_XAssisted, ++ ++ /*----cond select ----*/ ++ SW64in_CondSel, ++ ++ /*----other ----*/ ++ SW64in_EvCheck, ++ SW64in_ProfInc, ++ SW64in_Call, ++ SW64in_Mfence, ++ SW64in_CAS ++} SW64InstrTag; ++ ++ ++/*--------- Structure for instructions ----------*/ ++/* Destinations are on the LEFT (first operand) */ ++ ++typedef struct { ++ SW64InstrTag tag; ++ union{ ++ /* 64/32/16/8 bit stores */ ++ struct { ++ SW64LoadOp op; ++ HReg dst; ++ SW64AModeRI *addr; ++ } Load; ++ struct { ++ SW64StoreOp op; ++ HReg src; ++ SW64AModeRI *addr; ++ } Store; ++ struct { ++ SW64FpLoadOp op; ++ HReg dst; ++ SW64AModeRI *addr; ++ } FpLoad; ++ struct { ++ SW64FpStoreOp op; ++ HReg src; ++ SW64AModeRI *addr; ++ } FpStore; ++ ++ struct{ ++ UChar sz; /* 4|8 */ ++ HReg old; ++ HReg addr; ++ HReg expd; ++ HReg data; ++ } Cas; ++ ++ struct{ ++ HReg dst; //dst ++ ULong imm64; //imm ++ } LoadImm; ++ ++ struct{ ++ HReg dst; ++ HReg src; ++ SW64UnOp op; ++ } ++ UnOperate; ++ ++ /* Integer and/or/xor. Limitations: ++ - For and/or/xor, the immediate, if it exists, ++ is an unsigned 16. ++ */ ++ struct { ++ SW64LogicOp op; ++ HReg dst; ++ HReg srcL; ++ SW64RI8 *srcR; ++ } Logic; ++ ++ /* Integer Compare, CMPEQ, CMPLT, CMPLE, CMPULT, CMPULE ++ */ ++ struct{ ++ SW64CmpOp op; ++ HReg dst; ++ HReg srcL; ++ SW64RI8* srcR; ++ } Cmp; ++ ++ /* Integer shift, SLL, SRL, SRA ++ */ ++ struct{ ++ SW64ShftOp op; ++ HReg dst; ++ HReg srcL; ++ SW64RI8* srcR; ++ } Shft; ++ ++ /* Integer arith, ADD, SUB, MUL ++ */ ++ struct{ ++ SW64ArithOp op; ++ HReg dst; ++ HReg srcL; ++ SW64RI8* srcR; ++ } Arith; ++ ++ /* Integer division, DIV, REM ++ */ ++ struct{ ++ SW64IntDivOp op; ++ HReg dst; ++ HReg srcL; ++ HReg srcR; ++ } IntDiv; ++ ++ /* Float arith, ADD, SUB, MUL, DIV, SQRT ++ */ ++ struct{ ++ SW64FpArithOp op; ++ HReg dst; ++ HReg srcL; ++ HReg srcR; ++ } FpArith; ++ ++ struct{ ++ SW64FpCpyOp op; ++ HReg dst; ++ HReg src1; ++ HReg src2; ++ } FpCpy; ++ ++ struct{ ++ SW64FpQuaryOp op; ++ HReg dst; ++ HReg src1; ++ HReg src2; ++ HReg src3; ++ } FpQuary; ++ ++ struct{ ++ SW64FpUnaryOp op; ++ HReg dst; ++ HReg src; ++ } FpUnary; ++ ++ /* move/convert between GPR and FPR */ ++ struct { ++ SW64FpGpMoveOp op; ++ HReg dst; ++ HReg src; ++ } FpGpMove; ++ ++ /*float compare for branch and select*/ ++ struct { ++ SW64FpSelOp op; ++ HReg cond; ++ HReg dst; ++ HReg iftrue; ++ HReg iffalse; ++ } FpSel; ++ ++ /*float compare*/ ++ struct { ++ SW64FpCmpOp op; ++ HReg dst; ++ HReg srcL; ++ HReg srcR; ++ } FpCmp; ++ ++ /* convert from/to fpr to/from gpr */ ++ struct { ++ SW64FpCvtOp op; ++ HReg dst; ++ HReg src; ++ } FpCvt; ++ ++ /* read FPCR to GP register */ ++ struct{ ++ HReg dst; ++ } RFPCR; ++ ++ /* write GP register to FPCR*/ ++ struct{ ++ HReg src; ++ } WFPCR; ++ ++ /* Update the guest EIP value, then exit requesting to chain ++ to it. May be conditional. Urr, use of Addr32 implicitly ++ assumes that wordsize(guest) == wordsize(host). */ ++ struct { ++ Addr64 dstGA; /* next guest address */ ++ SW64AModeRI* amPC; /* amode in guest state for PC */ ++ SW64Cond* cond; /* condiction execution */ ++ Bool toFastEP; /* chain to the slow or fast point? */ ++ } XDirect; ++ /* Boring transfer to a guest address not known at JIT time. ++ Not chainable. May be conditional. */ ++ struct { ++ HReg dstGA; ++ SW64AModeRI* amPC; ++ SW64Cond* cond; ++ } XIndir; ++ /* Assisted transfer to a guest address, most general case. ++ Not chainable. May be conditional. */ ++ struct { ++ HReg dstGA; ++ SW64AModeRI* amPC; ++ SW64Cond* cond; ++ IRJumpKind jk; ++ } XAssisted; ++ ++ /* CSEL: dst = if cond then argL else argR. cond may be anything. */ ++ struct { ++ SW64CondSelOp op; ++ HReg dst; ++ HReg iftrue; ++ HReg iffalse; ++ HReg cond; ++ } CondSel; ++ ++ struct { ++ SW64AModeRI* amCounter; ++ SW64AModeRI* amFailAddr; ++ } EvCheck; ++ struct { ++ /* No fields. The address of the counter to inc is ++ installed later, post-translation, by patching it in, ++ as it is not known at translation time. */ ++ } ProfInc; ++ ++ /* Pseudo-insn. Call target (an absolute address), on given ++ condition (which could be Mcc_ALWAYS). argiregs indicates ++ which of $16 .. $21 (sw64) ++ carries argument values for this call, ++ using a bit mask (1<. ++ ++ The GNU General Public License is contained in the file COPYING. ++*/ ++ ++#include "libvex_basictypes.h" ++#include "libvex_ir.h" ++#include "libvex.h" ++ ++#include "main_util.h" ++#include "main_globals.h" ++#include "host_generic_regs.h" ++#include "host_sw64_defs.h" ++ ++ ++/*---------------------------------------------------------*/ ++/*--- ISelEnv ---*/ ++/*---------------------------------------------------------*/ ++ ++/* This carries around: ++ ++ - A mapping from IRTemp to IRType, giving the type of any IRTemp we ++ might encounter. This is computed before insn selection starts, ++ and does not change. ++ ++ - A mapping from IRTemp to HReg. This tells the insn selector ++ which virtual register is associated with each IRTemp temporary. ++ This is computed before insn selection starts, and does not ++ change. We expect this mapping to map precisely the same set of ++ IRTemps as the type mapping does. ++ ++ |vregmap| holds the primary register for the IRTemp. ++ |vregmapHI| is only used for 128-bit integer-typed ++ IRTemps. It holds the identity of a second ++ 64-bit virtual HReg, which holds the high half ++ of the value. ++ ++ - The code array, that is, the insns selected so far. ++ ++ - A counter, for generating new virtual registers. ++ ++ - The host hardware capabilities word. This is set at the start ++ and does not change. ++ ++ - A Bool for indicating whether we may generate chain-me ++ instructions for control flow transfers, or whether we must use ++ XAssisted. ++ ++ - The maximum guest address of any guest insn in this block. ++ Actually, the address of the highest-addressed byte from any insn ++ in this block. Is set at the start and does not change. This is ++ used for detecting jumps which are definitely forward-edges from ++ this block, and therefore can be made (chained) to the fast entry ++ point of the destination, thereby avoiding the destination's ++ event check. ++ ++ - An IRExpr*, which may be NULL, holding the IR expression (an ++ IRRoundingMode-encoded value) to which the FPU's rounding mode ++ was most recently set. Setting to NULL is always safe. Used to ++ avoid redundant settings of the FPU's rounding mode, as ++ described in set_FPCR_rounding_mode below. ++ ++ Note, this is all (well, mostly) host-independent. ++*/ ++ ++typedef ++ struct { ++ /* Constant -- are set at the start and do not change. */ ++ IRTypeEnv* type_env; //A mapping from IRTemp to IRType ++ ++ HReg* vregmap; //A mapping from IRTemp to HReg ++ HReg* vregmapHI; //is only used for 128-bit integer-typed ++ Int n_vregmap; ++ ++ UInt hwcaps; ++ ++ Bool chainingAllowed; ++ Addr64 max_ga; ++ ++ /* These are modified as we go along. */ ++ HInstrArray* code; ++ Int vreg_ctr; ++ ++ IRExpr* previous_rm; ++ } ++ ISelEnv; ++ ++static SW64Cond *iselIntExpr_Cond_wrk(ISelEnv * env, IRExpr * e); ++static SW64Cond *iselIntExpr_Cond(ISelEnv * env, IRExpr * e); ++ ++static SW64AModeRI *iselWordExpr_AMode_wrk(ISelEnv * env, IRExpr * e); ++static SW64AModeRI *iselWordExpr_AMode(ISelEnv * env, IRExpr * e); ++ ++static HReg iselIntExpr_HReg(ISelEnv * env, IRExpr * e, HReg INVALID_HREG); ++static HReg iselIntExpr(ISelEnv * env, IRExpr * e); ++ ++static SW64RI8 *iselIntExpr_RI8_wrk(ISelEnv * env, IRExpr * e); ++static SW64RI8 *iselIntExpr_RI8(ISelEnv * env, IRExpr * e); ++ ++static void iselInt128Expr_wrk ( HReg* rHi, HReg* rLo, ISelEnv* env, IRExpr* e ); ++static void iselInt128Expr ( HReg* rHi, HReg* rLo, ISelEnv* env, IRExpr* e ); ++ ++static HReg iselFltExpr_HReg(ISelEnv * env, IRExpr * e, HReg INVALID_HREG); ++static HReg iselFltExpr(ISelEnv * env, IRExpr * e); ++ ++static ++Bool doHelperCall ( /*OUT*/UInt* stackAdjustAfterCall, ++ /*OUT*/RetLoc* retloc, ++ ISelEnv* env, ++ IRExpr* guard, ++ IRCallee* cee, IRType retTy, IRExpr** args ); ++ ++ ++/* Create Integer HReg */ ++static HReg newVRegI( ISelEnv * env) ++{ ++ HReg reg = mkHReg(True /*virtual reg*/, HRcInt64, 0, env->vreg_ctr); ++ env->vreg_ctr++; ++ return reg; ++} ++/* Create Float HReg */ ++static HReg newVRegF( ISelEnv * env) ++{ ++ HReg reg = mkHReg(True /*virtual reg*/, HRcFlt64, 0, env->vreg_ctr); ++ env->vreg_ctr++; ++ return reg; ++} ++ ++static void addInstr(ISelEnv * env, SW64Instr * instr) ++{ ++ addHInstr(env->code, instr); ++ if (vex_traceflags & VEX_TRACE_VCODE) { ++ ppSW64Instr(instr); ++ vex_printf("\n"); ++ } ++} ++ ++static Bool const_equal_to(IRExpr *e, ULong v) ++{ ++ if (e->tag != Iex_Const) ++ return False; ++ ++ if (e->Iex.Const.con->tag == Ico_U64) ++ return e->Iex.Const.con->Ico.U64 == v; ++ ++ if (e->Iex.Const.con->tag == Ico_U32) ++ return e->Iex.Const.con->Ico.U32 == v; ++ ++ if (e->Iex.Const.con->tag == Ico_U16) ++ return e->Iex.Const.con->Ico.U16 == v; ++ ++ if (e->Iex.Const.con->tag == Ico_U8) ++ return e->Iex.Const.con->Ico.U8 == v; ++ ++ return False; ++} ++ ++static Bool const_equal_to_float(IRExpr *e, double v) ++{ ++ if (e->tag != Iex_Const) ++ return False; ++ ++ if (e->Iex.Const.con->tag == Ico_F64) ++ return e->Iex.Const.con->Ico.F64 == v; ++ ++ if (e->Iex.Const.con->tag == Ico_F32) ++ return e->Iex.Const.con->Ico.F32 == v; ++ ++ return False; ++} ++ ++static IRExpr *foldF64ArithToF32(IRExpr const *e) ++{ ++ IRExpr *ret = deepCopyIRExpr(e); ++ IROp *op; ++ ++ switch (e->tag) { ++ case Iex_Qop: op = &ret->Iex.Qop.details->op; break; ++ case Iex_Triop: op = &ret->Iex.Triop.details->op; break; ++ case Iex_Binop: op = &ret->Iex.Binop.op; break; ++ case Iex_Unop: op = &ret->Iex.Unop.op; break; ++ default: return NULL; ++ } ++ ++ switch (*op) { ++ case Iop_AddF64: *op = Iop_AddF32; break; ++ case Iop_SubF64: *op = Iop_SubF32; break; ++ case Iop_MulF64: *op = Iop_MulF32; break; ++ case Iop_DivF64: *op = Iop_DivF32; break; ++ case Iop_MSubF64: *op = Iop_MSubF32; break; ++ case Iop_MAddF64: *op = Iop_MAddF32; break; ++ case Iop_SqrtF64: *op = Iop_SqrtF32; break; ++ case Iop_I64StoF64: *op = Iop_I64StoF32; break; ++ case Iop_I64UtoF64: *op = Iop_I64UtoF32; break; ++ default: return NULL; ++ } ++ ++ return ret; ++} ++ ++static HReg lookupIRTemp(ISelEnv * env, IRTemp tmp) ++{ ++ vassert(tmp < env->n_vregmap); ++ return env->vregmap[tmp]; ++} ++static void ++lookupIRTempPair(HReg * vrHI, HReg * vrLO, ISelEnv * env, IRTemp tmp) ++{ ++ vassert(tmp < env->n_vregmap); ++ vassert(! hregIsInvalid(env->vregmapHI[tmp])); ++ *vrLO = env->vregmap[tmp]; ++ *vrHI = env->vregmapHI[tmp]; ++} ++ ++static void set_SW64_rounding_default(ISelEnv * env) ++{ ++ HReg fpcr = newVRegF(env); ++ ++ /* restore fpcr from r14 */ ++ addInstr(env, SW64Instr_FpGpMove(SW64in_IFMOVD, fpcr, hregSW64_R14())); ++ addInstr(env, SW64Instr_WFPCR(fpcr)); ++} ++ ++static void set_SW64_rounding_mode(ISelEnv * env, IRExpr * mode) ++{ ++ /* ++ rounding mode | SW64| IR ++ ------------------------ ++ to nearest | 10 | 00 ++ to zero | 00 | 11 ++ to +infinity | 11 | 10 ++ to -infinity | 01 | 01 ++ */ ++ HReg irrm = iselIntExpr(env, mode); ++ HReg swrm = newVRegI(env); ++ HReg newfpcr = newVRegI(env); ++ HReg fpcr = newVRegF(env); ++ ++ /* save fpcr to r14 */ ++ addInstr(env, SW64Instr_RFPCR(fpcr)); ++ addInstr(env, SW64Instr_FpGpMove(SW64in_FIMOVD, hregSW64_R14(), fpcr)); ++ ++ /* swrm = 0b11 & ((0b110110) >> (irrm << 1)) */ ++ addInstr(env, SW64Instr_LoadImm(swrm, 0b110110)); ++ addInstr(env, SW64Instr_Shft(SW64in_SLL, irrm, irrm, SW64RI8_Imm(1))); ++ addInstr(env, SW64Instr_Shft(SW64in_SRL, swrm, swrm, SW64RI8_Reg(irrm))); ++ addInstr(env, SW64Instr_Logic(SW64in_AND, swrm, swrm, SW64RI8_Imm(0b11))); ++ /* newfpcr = swrm << 58 | swrm */ ++ addInstr(env, SW64Instr_Shft(SW64in_SLL, swrm, swrm, SW64RI8_Imm(58))); ++ addInstr(env, SW64Instr_LoadImm(newfpcr, 0x600fa00000000000)); ++ addInstr(env, SW64Instr_Logic(SW64in_OR, newfpcr, newfpcr, SW64RI8_Reg(swrm))); ++ /* set fpcr */ ++ addInstr(env, SW64Instr_FpGpMove(SW64in_IFMOVD, fpcr, newfpcr)); ++ addInstr(env, SW64Instr_WFPCR(fpcr)); ++} ++ ++ ++static HReg iselIntExpr(ISelEnv * env, IRExpr * e) ++{ ++ HReg r = iselIntExpr_HReg(env, e, INVALID_HREG); ++ /* sanity checks ... */ ++ vassert(hregClass(r) == HRcInt64); ++ vassert(hregIsVirtual(r) || sameHReg(r, SW64Zero())); ++ return r; ++} ++ ++/*! ++ * IR 表达式指令选择. ++ * 将 IR 表达式翻译为 SW64 指令序列，并将 IR 表达式的计算结果返回值写入指定的 HReg. ++ * 警告：不要修改返回的 HReg 中的值，具体而言有两点原因： ++ * 1: 若 IR 表达式求值结果为 0，此函数可能会返回 $r31，修改此寄存器没有意义 ++ * 2: 此函数可能会返回 IRTemp 中的 HReg，按照 Valgrind IR 的定义，IRTemp 是只读的，修改 ++ * IRTemp 将导致无法预料的行为 ++ * 注意：如果 IR 表达式的类型大小小于 64 位 (例如 Ity_I8 Ity_I16 Ity_I32)，寄存器中的高位部分 ++ * 是不确定的，不要依赖这些的值。但对于 Ity_I1 有例外，Ity_I1 的寄存器的高位部分应为全零。 ++ * ++ * @param[in] env 上下文环境 ++ * @param[in] e IR 表达式 ++ * @param[out] d 指定的 HReg，若为 INVALID_HREG，则新分配一个 ++ * @return 保存了该 IR 表达式计算结果的 HReg ++ */ ++static HReg iselIntExpr_HReg(ISelEnv *env, IRExpr *e, HReg d) ++{ ++ IRType ty = typeOfIRExpr(env->type_env, e); ++ vassert(ty == Ity_I8 || ty == Ity_I16 || ty == Ity_I32 || ty == Ity_I1 ++ || ty == Ity_F32 || ty == Ity_I64 || ty == Ity_I128); ++ ++ switch(e->tag) { ++ case Iex_RdTmp: { ++ HReg src = lookupIRTemp(env, e->Iex.RdTmp.tmp); ++ if (hregIsInvalid(d)) { ++ return src; ++ } else { ++ addInstr(env, SW64Instr_Logic(SW64in_AND, d, src, SW64RI8_Reg(src))); ++ return d; ++ } ++ } ++ ++ case Iex_Const: { ++ HReg dst; ++ ULong val = 0; ++ IRConst* con = e->Iex.Const.con; ++ switch (con->tag) { ++ case Ico_U64: val = con->Ico.U64; break; ++ case Ico_U32: val = con->Ico.U32; break; ++ case Ico_U16: val = con->Ico.U16; break; ++ case Ico_U8: val = con->Ico.U8; break; ++ case Ico_U1: val = con->Ico.U1 ? 1:0; break; ++ default: ppIRExpr(e); vpanic("iselIntExpr_R.Iex_Const(sw64)"); ++ } ++ ++ if (val == 0 && hregIsInvalid(d)) { ++ return SW64Zero(); ++ } ++ ++ dst = hregIsInvalid(d) ? newVRegI(env) : d; ++ addInstr(env, SW64Instr_LoadImm(dst, val)); ++ return dst; ++ } ++ ++ case Iex_Load: ++ case Iex_Get: { ++ if (ty != Ity_I8 && ty != Ity_I16 && ty != Ity_I32 && ty != Ity_I64) ++ goto irreducible; ++ ++ if(e->tag == Iex_Load && e->Iex.Load.end != Iend_LE) ++ goto irreducible; ++ ++ HReg dst = hregIsInvalid(d) ? newVRegI(env) : d; ++ ++ SW64AModeRI *addr = (e->tag == Iex_Load) ++ ? iselWordExpr_AMode(env, e->Iex.Load.addr) ++ : SW64AModeRI_IR(e->Iex.Get.offset, ++ SW64GuestStateHreg()); ++ ++ SW64LoadOp op = (ty == Ity_I8) ? SW64in_LDBU : ++ (ty == Ity_I16) ? SW64in_LDHU : ++ (ty == Ity_I32) ? SW64in_LDW : ++ (ty == Ity_I64) ? SW64in_LDL : ++ (vassert(0), 0); ++ ++ addInstr(env, SW64Instr_Load(op, dst, addr)); ++ return dst; ++ } ++ ++ case Iex_Unop: { ++ IROp op = e->Iex.Unop.op; ++ IRExpr *arg = e->Iex.Unop.arg; ++ ++ switch(op) { ++ /* 1-bit widening */ ++ case Iop_1Uto8: ++ case Iop_1Uto32: ++ case Iop_1Uto64: { ++ /* higher bits of Ity_I1 are all zero, just return as-is */ ++ return iselIntExpr_HReg(env, arg, d); ++ } ++ case Iop_1Sto8: ++ case Iop_1Sto16: ++ case Iop_1Sto32: ++ case Iop_1Sto64: { ++ HReg dst = hregIsInvalid(d) ? newVRegI(env) : d; ++ HReg src = iselIntExpr(env, arg); ++ /* Iop_1Sto64(x) = ((uint64_t)0 - x) */ ++ addInstr(env, SW64Instr_Arith(SW64in_SUBL, dst, hregSW64_R31(), SW64RI8_Reg(src))); ++ return dst; ++ } ++ ++ /* 8-bits widening */ ++ case Iop_8Uto16: ++ case Iop_8Uto32: ++ case Iop_8Uto64: { ++ if (arg->tag == Iex_Load && arg->Iex.Load.ty == Ity_I8) { ++ /* already zero-extend, no need to extend again */ ++ return iselIntExpr_HReg(env, arg, d); ++ } ++ HReg dst = hregIsInvalid(d) ? newVRegI(env) : d; ++ HReg src = iselIntExpr(env, arg); ++ addInstr(env, SW64Instr_Arith(SW64in_ZAPNOT, dst, src, SW64RI8_Imm(0x1))); ++ return dst; ++ } ++ case Iop_8Sto16: ++ case Iop_8Sto32: ++ case Iop_8Sto64: { ++ HReg dst = hregIsInvalid(d) ? newVRegI(env) : d; ++ HReg src = iselIntExpr(env, arg); ++ addInstr(env, SW64Instr_Arith(SW64in_SEXTB, dst, hregSW64_R31(), SW64RI8_Reg(src))); ++ return dst; ++ } ++ ++ /* 16-bits widening */ ++ case Iop_16Uto32: ++ case Iop_16Uto64: { ++ if (arg->tag == Iex_Load && arg->Iex.Load.ty == Ity_I16) { ++ /* already zero-extend, no need to extend again */ ++ return iselIntExpr_HReg(env, arg, d); ++ } ++ HReg dst = hregIsInvalid(d) ? newVRegI(env) : d; ++ HReg src = iselIntExpr(env, arg); ++ addInstr(env, SW64Instr_Arith(SW64in_ZAPNOT, dst, src, SW64RI8_Imm(0x3))); ++ return dst; ++ } ++ case Iop_16Sto32: ++ case Iop_16Sto64: { ++ HReg dst = hregIsInvalid(d) ? newVRegI(env) : d; ++ HReg src = iselIntExpr(env, arg); ++ addInstr(env, SW64Instr_Arith(SW64in_SEXTH, dst, hregSW64_R31(), SW64RI8_Reg(src))); ++ return dst; ++ } ++ ++ /* 32-bits widening */ ++ case Iop_32Uto64: { ++ HReg dst = hregIsInvalid(d) ? newVRegI(env) : d; ++ HReg src = iselIntExpr(env, arg); ++ addInstr(env, SW64Instr_Arith(SW64in_ZAPNOT, dst, src, SW64RI8_Imm(0xf))); ++ return dst; ++ } ++ case Iop_32Sto64: { ++ if ((arg->tag == Iex_Binop && (arg->Iex.Binop.op == Iop_Add32 || ++ arg->Iex.Binop.op == Iop_Sub32 || ++ arg->Iex.Binop.op == Iop_Mul32)) || ++ (arg->tag == Iex_Load && arg->Iex.Load.ty == Ity_I32)) { ++ /* already signed-extend, no need to extend again */ ++ return iselIntExpr_HReg(env, arg, d); ++ } ++ HReg dst = hregIsInvalid(d) ? newVRegI(env) : d; ++ HReg src = iselIntExpr(env, arg); ++ addInstr(env, SW64Instr_Arith(SW64in_ADDW, dst, hregSW64_R31(), SW64RI8_Reg(src))); ++ return dst; ++ } ++ ++ /* narrowing */ ++ case Iop_64to8: ++ case Iop_64to16: ++ case Iop_64to32: { ++ /* higher bits of Ity_I32 Ity_I16 Ity_I8 may be undefined ++ so there is a No-op */ ++ return iselIntExpr_HReg(env, arg, d); ++ } ++ ++ case Iop_Not1: { ++ HReg dst = hregIsInvalid(d) ? newVRegI(env) : d; ++ HReg src = iselIntExpr(env, arg); ++ /* higher bits of Ity_I1 are all zero, so Iop_Not1(x) = x ^ 1 */ ++ addInstr(env, SW64Instr_Logic(SW64in_XOR, dst, src, SW64RI8_Imm(0x1))); ++ return dst; ++ } ++ ++ case Iop_Not8: ++ case Iop_Not16: ++ case Iop_Not32: ++ case Iop_Not64: { ++ HReg dst = hregIsInvalid(d) ? newVRegI(env) : d; ++ HReg src = iselIntExpr(env, arg); ++ ++ addInstr(env, SW64Instr_Logic(SW64in_ORNOT, dst, hregSW64_R31(), SW64RI8_Reg(src))); ++ return dst; ++ } ++ ++ case Iop_ClzNat64: ++ case Iop_CtzNat64: ++ case Iop_PopCount64: { ++ HReg dst = hregIsInvalid(d) ? newVRegI(env) : d; ++ HReg src = iselIntExpr(env, arg); ++ SW64UnOp unop = (op == Iop_ClzNat64) ? SW64in_CLZ : ++ (op == Iop_CtzNat64) ? SW64in_CTZ : ++ (op == Iop_PopCount64) ? SW64in_POP : ++ (vassert(0), 0); ++ ++ addInstr(env, SW64Instr_UnOperate(unop, dst, src)); ++ return dst; ++ } ++ ++ case Iop_Left32: ++ case Iop_Left64: { ++ /* Left64(src) = src | -src. Left32 can use the same ++ implementation since in that case we don't care what ++ the upper 32 bits become. */ ++ HReg dst = hregIsInvalid(d) ? newVRegI(env) : d; ++ HReg src = iselIntExpr(env, arg); ++ ++ addInstr(env, SW64Instr_Arith(SW64in_SUBL, dst, hregSW64_R31(), SW64RI8_Reg(src))); ++ addInstr(env, SW64Instr_Logic(SW64in_OR, dst, dst, SW64RI8_Reg(src))); ++ return dst; ++ } ++ ++ case Iop_CmpNEZ8: ++ case Iop_CmpNEZ16: ++ case Iop_CmpNEZ32: { ++ HReg dst = hregIsInvalid(d) ? newVRegI(env) : d; ++ HReg src = iselIntExpr(env, arg); ++ UInt mask = (op == Iop_CmpNEZ8) ? 0x1 : ++ (op == Iop_CmpNEZ16) ? 0x3 : ++ (op == Iop_CmpNEZ32) ? 0xf : ++ (vassert(0), 0); ++ /* clear higher bits, then compare */ ++ addInstr(env, SW64Instr_Arith(SW64in_ZAPNOT, dst, src, SW64RI8_Imm(mask))); ++ addInstr(env, SW64Instr_Cmp(SW64in_CMPULT, dst, hregSW64_R31(), SW64RI8_Reg(dst))); ++ return dst; ++ } ++ ++ case Iop_CmpNEZ64: { ++ HReg dst = hregIsInvalid(d) ? newVRegI(env) : d; ++ HReg src = iselIntExpr(env, arg); ++ /* Iop_CmpNEZ64(x) = x > 0 */ ++ addInstr(env, SW64Instr_Cmp(SW64in_CMPULT, dst, hregSW64_R31(), SW64RI8_Reg(src))); ++ return dst; ++ } ++ ++ case Iop_CmpwNEZ32: ++ { ++ HReg dst = hregIsInvalid(d) ? newVRegI(env) : d; ++ HReg src = iselIntExpr(env, e->Iex.Unop.arg); ++ /* Iop_CmpwNEZ32(x) = (0 - (x > 0)), need to clear higher bits */ ++ addInstr(env, SW64Instr_Arith(SW64in_ZAPNOT, dst, src, SW64RI8_Imm(0xf))); ++ addInstr(env, SW64Instr_Cmp(SW64in_CMPULT, dst, hregSW64_R31(), SW64RI8_Reg(dst))); ++ addInstr(env, SW64Instr_Arith(SW64in_SUBW, dst, hregSW64_R31(), SW64RI8_Reg(dst))); ++ return dst; ++ } ++ case Iop_CmpwNEZ64: ++ { ++ HReg dst = hregIsInvalid(d) ? newVRegI(env) : d; ++ HReg src = iselIntExpr(env, e->Iex.Unop.arg); ++ /* Iop_CmpwNEZ64(x) = (0 - (x > 0)) */ ++ addInstr(env, SW64Instr_Cmp(SW64in_CMPULT, dst, hregSW64_R31(), SW64RI8_Reg(src))); ++ addInstr(env, SW64Instr_Arith(SW64in_SUBL, dst, hregSW64_R31(), SW64RI8_Reg(dst))); ++ return dst; ++ } ++ ++ case Iop_64HIto32: { ++ HReg dst = hregIsInvalid(d) ? newVRegI(env) : d; ++ HReg src = iselIntExpr(env, e->Iex.Unop.arg); ++ addInstr(env, SW64Instr_Shft(SW64in_SRA, dst, src, SW64RI8_Imm(32))); ++ return dst; ++ } ++ ++ case Iop_128HIto64: { ++ HReg rHi, rLo; ++ iselInt128Expr(&rHi, &rLo, env, arg); ++ ++ /* abandon rLo */ ++ if (hregIsInvalid(d)) { ++ return rHi; ++ } else { ++ addInstr(env, SW64Instr_Logic(SW64in_AND, d, rHi, SW64RI8_Reg(rHi))); ++ return d; ++ } ++ } ++ ++ case Iop_128to64: { ++ HReg rHi, rLo; ++ iselInt128Expr(&rHi, &rLo, env, arg); ++ ++ /* abandon rHi */ ++ if (hregIsInvalid(d)) { ++ return rLo; ++ } else { ++ addInstr(env, SW64Instr_Logic(SW64in_AND, d, rLo, SW64RI8_Reg(rLo))); ++ return d; ++ } ++ } ++ ++ case Iop_ReinterpF32asI32: ++ case Iop_ReinterpF64asI64: { ++ HReg dst = newVRegI(env); ++ HReg src = iselFltExpr(env, arg); ++ SW64FpGpMoveOp movop = (op == Iop_ReinterpF32asI32) ? SW64in_FIMOVS : ++ (op == Iop_ReinterpF64asI64) ? SW64in_FIMOVD : ++ (vassert(0), 0); ++ ++ addInstr(env, SW64Instr_FpGpMove(movop, dst, src)); ++ if (hregIsInvalid(d)) { ++ return dst; ++ } else { ++ addInstr(env, SW64Instr_Logic(SW64in_OR, d, dst, SW64RI8_Reg(dst))); ++ return d; ++ } ++ } ++ ++ default: ++ goto irreducible; ++ } /* switch(op) */ ++ ++ } /* case Iex_Unop: */ ++ ++ ++ case Iex_Binop: { ++ IROp op = e->Iex.Binop.op; ++ IRExpr *arg1 = e->Iex.Binop.arg1; ++ IRExpr *arg2 = e->Iex.Binop.arg2; ++ ++ switch (op) { ++ case Iop_Or1: ++ case Iop_Or8: ++ case Iop_Or16: ++ case Iop_Or32: ++ case Iop_Or64: { ++ HReg dst = hregIsInvalid(d) ? newVRegI(env) : d; ++ HReg srcL = iselIntExpr(env, arg1); ++ SW64RI8 *srcR = iselIntExpr_RI8(env, arg2); ++ ++ addInstr(env, SW64Instr_Logic(SW64in_OR, dst, srcL, srcR)); ++ return dst; ++ } ++ ++ case Iop_And1: ++ case Iop_And8: ++ case Iop_And16: ++ case Iop_And32: ++ case Iop_And64: { ++ HReg dst = hregIsInvalid(d) ? newVRegI(env) : d; ++ HReg srcL = iselIntExpr(env, arg1); ++ SW64RI8 *srcR; ++ ++ if (arg2->tag == Iex_Const) { ++ IRConst *con = arg2->Iex.Const.con; ++ if (con->tag == Ico_U64) { ++ /* optmize for ++ And64(x, 0xFFFF:I64) ++ And64(x, 0xFFFFFFFF:I64) ++ transform to ++ Zapnot(x, 0x3:I64) ++ Zapnot(x, 0xf:I64) ++ */ ++ if (con->Ico.U64 == 0xFFFF) { ++ addInstr(env, SW64Instr_Arith(SW64in_ZAPNOT, dst, srcL, SW64RI8_Imm(0x3))); ++ return dst; ++ } ++ if (con->Ico.U64 == 0xFFFFFFFF) { ++ addInstr(env, SW64Instr_Arith(SW64in_ZAPNOT, dst, srcL, SW64RI8_Imm(0xf))); ++ return dst; ++ } ++ /* optmize for ++ And64(x, 0xFFFFFFFFFFFFFF00) ++ transform to ++ AndNot64(x, 0xFF) ++ */ ++ if (con->Ico.U64 >= 0xFFFFFFFFFFFFFF00 && con->Ico.U64 <= 0xFFFFFFFFFFFFFFFF) { ++ addInstr(env, SW64Instr_Logic(SW64in_BIC, dst, srcL, SW64RI8_Imm(~con->Ico.U64))); ++ return dst; ++ } ++ } ++ } ++ ++ srcR = iselIntExpr_RI8(env, arg2); ++ addInstr(env, SW64Instr_Logic(SW64in_AND, dst, srcL, srcR)); ++ return dst; ++ } ++ ++ case Iop_Xor8: ++ case Iop_Xor16: ++ case Iop_Xor32: ++ case Iop_Xor64: { ++ HReg dst = hregIsInvalid(d) ? newVRegI(env) : d; ++ HReg srcL = iselIntExpr(env, arg1); ++ SW64RI8 *srcR = iselIntExpr_RI8(env, arg2); ++ ++ addInstr(env, SW64Instr_Logic(SW64in_XOR, dst, srcL, srcR)); ++ return dst; ++ } ++ ++ case Iop_Add32: ++ case Iop_Add64: ++ case Iop_Sub32: ++ case Iop_Sub64: { ++ HReg dst = hregIsInvalid(d) ? newVRegI(env) : d; ++ SW64RI8 *srcR = iselIntExpr_RI8(env, arg2); ++ ++ if (arg1->tag == Iex_Binop && arg1->Iex.Binop.op == Iop_Shl64) { ++ if (const_equal_to(arg1->Iex.Binop.arg2, 3)) { ++ /* S8ADDW S8ADDL S8SUBW S8SUBL */ ++ HReg srcL = iselIntExpr(env, arg1->Iex.Binop.arg1); ++ SW64ArithOp ariop = (op == Iop_Add32) ? SW64in_S8ADDW : ++ (op == Iop_Add64) ? SW64in_S8ADDL : ++ (op == Iop_Sub32) ? SW64in_S8SUBW : ++ (op == Iop_Sub64) ? SW64in_S8SUBL : ++ (vassert(0), 0); ++ addInstr(env, SW64Instr_Arith(ariop, dst, srcL, srcR)); ++ return dst; ++ } ++ if (const_equal_to(arg1->Iex.Binop.arg2, 2)) { ++ /* S4ADDW S4ADDL S4SUBW S4SUBL */ ++ HReg srcL = iselIntExpr(env, arg1->Iex.Binop.arg1); ++ SW64ArithOp ariop = (op == Iop_Add32) ? SW64in_S4ADDW : ++ (op == Iop_Add64) ? SW64in_S4ADDL : ++ (op == Iop_Sub32) ? SW64in_S4SUBW : ++ (op == Iop_Sub64) ? SW64in_S4SUBL : ++ (vassert(0), 0); ++ addInstr(env, SW64Instr_Arith(ariop, dst, srcL, srcR)); ++ return dst; ++ } ++ } ++ ++ HReg srcL = iselIntExpr(env, arg1); ++ SW64ArithOp ariop = (op == Iop_Add32) ? SW64in_ADDW : ++ (op == Iop_Add64) ? SW64in_ADDL : ++ (op == Iop_Sub32) ? SW64in_SUBW : ++ (op == Iop_Sub64) ? SW64in_SUBL : ++ (vassert(0), 0); ++ addInstr(env, SW64Instr_Arith(ariop, dst, srcL, srcR)); ++ return dst; ++ } ++ ++ case Iop_Mul32: ++ case Iop_Mul64: { ++ HReg dst = hregIsInvalid(d) ? newVRegI(env) : d; ++ HReg srcL = iselIntExpr(env, arg1); ++ SW64RI8 *srcR = iselIntExpr_RI8(env, arg2); ++ SW64ArithOp ariop = (op == Iop_Mul32) ? SW64in_MULW : ++ (op == Iop_Mul64) ? SW64in_MULL : ++ (vassert(0), 0); ++ addInstr(env, SW64Instr_Arith(ariop, dst, srcL, srcR)); ++ return dst; ++ } ++ ++ case Iop_DivS32: ++ case Iop_DivU32: ++ case Iop_DivS64: ++ case Iop_DivU64: { ++ HReg dst = hregIsInvalid(d) ? newVRegI(env) : d; ++ HReg srcL = iselIntExpr(env, arg1); ++ HReg srcR = iselIntExpr(env, arg2); ++ SW64IntDivOp divop = (op == Iop_DivS32) ? SW64in_DIVW : ++ (op == Iop_DivU32) ? SW64in_UDIVW : ++ (op == Iop_DivS64) ? SW64in_DIVL : ++ (op == Iop_DivU64) ? SW64in_UDIVL : ++ (vassert(0), 0); ++ addInstr(env, SW64Instr_IntDiv(divop, dst, srcL, srcR)); ++ return dst; ++ } ++ ++ case Iop_DivModS32to32: ++ case Iop_DivModU32to32: { ++ HReg dst = hregIsInvalid(d) ? newVRegI(env) : d; ++ HReg srcL = iselIntExpr(env, arg1); ++ HReg srcR = iselIntExpr(env, arg2); ++ HReg div = newVRegI(env); ++ HReg mod = newVRegI(env); ++ if (e->Iex.Binop.op == Iop_DivModS32to32) { ++ addInstr(env, SW64Instr_IntDiv(SW64in_DIVW, div, srcL, srcR)); ++ addInstr(env, SW64Instr_IntDiv(SW64in_REMW, mod, srcL, srcR)); ++ addInstr(env, SW64Instr_Arith(SW64in_ZAPNOT, div, div, SW64RI8_Imm(0xf))); ++ } else { ++ addInstr(env, SW64Instr_IntDiv(SW64in_UDIVW, div, srcL, srcR)); ++ addInstr(env, SW64Instr_IntDiv(SW64in_UREMW, mod, srcL, srcR)); ++ } ++ addInstr(env, SW64Instr_Shft(SW64in_SLL, mod, mod, SW64RI8_Imm(32))); ++ addInstr(env, SW64Instr_Logic(SW64in_OR, dst, div, SW64RI8_Reg(mod))); ++ return dst; ++ } ++ ++ case Iop_Shl32: ++ case Iop_Shl64: ++ case Iop_Shr32: ++ case Iop_Shr64: ++ case Iop_Sar32: ++ case Iop_Sar64: { ++ HReg dst = hregIsInvalid(d) ? newVRegI(env) : d; ++ HReg srcL = iselIntExpr(env, arg1); ++ SW64RI8 *srcR; ++ SW64ShftOp shop = (op == Iop_Shl32) ? SW64in_SLL : ++ (op == Iop_Shl64) ? SW64in_SLL : ++ (op == Iop_Shr32) ? SW64in_SRL : ++ (op == Iop_Shr64) ? SW64in_SRL : ++ (op == Iop_Sar32) ? SW64in_SRA : ++ (op == Iop_Sar64) ? SW64in_SRA : ++ (vassert(0), 0); ++ ++ /* fast path for ++ t0 = Shl64(t1, And8(64to8(t2), 0x3f)) ++ is equal to ++ sll %vR1, %vR2, %vR0 ++ */ ++ if (arg2->tag == Iex_Binop && arg2->Iex.Binop.op == Iop_And8 && ++ const_equal_to(arg2->Iex.Binop.arg2, 0x3F)) { ++ srcR = iselIntExpr_RI8(env, arg2->Iex.Binop.arg1); ++ } else { ++ srcR = iselIntExpr_RI8(env, arg2); ++ } ++ ++ /* becare, high 32 bit may contains garbage bits, signed-extend ++ or zero-extend dependent on arithmetic shift or logical shift */ ++ /* HReg returnd by iselIntExpr() is modify here, but this is safe, ++ because higher bits is undefined and free to modify. */ ++ if (op == Iop_Sar32) { ++ addInstr(env, SW64Instr_Arith(SW64in_ADDW, srcL, srcL, SW64RI8_Reg(SW64Zero()))); ++ } else if (op == Iop_Shr32) { ++ addInstr(env, SW64Instr_Arith(SW64in_ZAPNOT, srcL, srcL, SW64RI8_Imm(0xf))); ++ } ++ ++ addInstr(env, SW64Instr_Shft(shop, dst, srcL, srcR)); ++ return dst; ++ } ++ ++ case Iop_Max32U: { ++ HReg dst = hregIsInvalid(d) ? newVRegI(env) : d; ++ HReg srcL = iselIntExpr(env, arg1); ++ HReg srcR = iselIntExpr(env, arg2); ++ /* HReg returnd by iselIntExpr() is modify here, but this is safe, ++ because higher bits is undefined and free to modify. */ ++ addInstr(env, SW64Instr_Arith(SW64in_ZAPNOT, srcL, srcL, SW64RI8_Imm(0xf))); ++ addInstr(env, SW64Instr_Arith(SW64in_ZAPNOT, srcR, srcR, SW64RI8_Imm(0xf))); ++ addInstr(env, SW64Instr_Cmp(SW64in_CMPULE, dst, srcL, SW64RI8_Reg(srcR))); ++ addInstr(env, SW64Instr_CondSel(SW64in_SELNE, dst, srcR, srcL, dst)); ++ return dst; ++ } ++ ++ /* 32-bit compare */ ++ case Iop_CmpLT32S: ++ case Iop_CmpLT32U: ++ case Iop_CmpLE32S: ++ case Iop_CmpLE32U:{ ++ HReg dst = hregIsInvalid(d) ? newVRegI(env) : d; ++ HReg srcL = iselIntExpr(env, arg1); ++ HReg srcR = iselIntExpr(env, arg2); ++ SW64CmpOp cmp = (op == Iop_CmpLT64S) ? SW64in_CMPLT : ++ (op == Iop_CmpLT64U) ? SW64in_CMPULT : ++ (op == Iop_CmpLE64S) ? SW64in_CMPLE : ++ (op == Iop_CmpLE64U) ? SW64in_CMPULE : ++ (vassert(0), 0); ++ /* HReg returnd by iselIntExpr() is modify here, but this is safe, ++ because higher bits is undefined and free to modify. */ ++ addInstr(env, SW64Instr_Arith(SW64in_ZAPNOT, srcL, srcL, SW64RI8_Imm(0xf))); ++ addInstr(env, SW64Instr_Arith(SW64in_ZAPNOT, srcR, srcR, SW64RI8_Imm(0xf))); ++ addInstr(env, SW64Instr_Cmp(cmp, dst, srcL, SW64RI8_Reg(srcR))); ++ return dst; ++ } ++ case Iop_CmpEQ32: ++ case Iop_CasCmpEQ32: { ++ HReg dst = hregIsInvalid(d) ? newVRegI(env) : d; ++ HReg srcL = iselIntExpr(env, arg1); ++ SW64RI8 *srcR = iselIntExpr_RI8(env, arg2); ++ /* signed-extend to 64-bits, then compare */ ++ addInstr(env, SW64Instr_Arith(SW64in_SUBW, dst, srcL, srcR)); ++ addInstr(env, SW64Instr_Cmp(SW64in_CMPEQ, dst, hregSW64_R31(), SW64RI8_Reg(dst))); ++ return dst; ++ } ++ case Iop_CmpNE32: ++ case Iop_CasCmpNE32: { ++ HReg dst = hregIsInvalid(d) ? newVRegI(env) : d; ++ HReg srcL = iselIntExpr(env, arg1); ++ SW64RI8 *srcR = iselIntExpr_RI8(env, arg2); ++ /* signed-extend to 64-bits, then compare */ ++ addInstr(env, SW64Instr_Arith(SW64in_SUBW, dst, srcL, srcR)); ++ addInstr(env, SW64Instr_Cmp(SW64in_CMPULT, dst, hregSW64_R31(), SW64RI8_Reg(dst))); ++ return dst; ++ } ++ ++ /* 64-bit compare */ ++ case Iop_CmpEQ64: ++ case Iop_CmpLT64S: ++ case Iop_CmpLT64U: ++ case Iop_CmpLE64S: ++ case Iop_CmpLE64U: ++ case Iop_CasCmpEQ64: { ++ HReg dst = hregIsInvalid(d) ? newVRegI(env) : d; ++ HReg srcL = iselIntExpr(env, arg1); ++ SW64RI8 *srcR = iselIntExpr_RI8(env, arg2); ++ SW64CmpOp cmp = (op == Iop_CmpEQ64) ? SW64in_CMPEQ : ++ (op == Iop_CmpLT64S) ? SW64in_CMPLT : ++ (op == Iop_CmpLT64U) ? SW64in_CMPULT : ++ (op == Iop_CmpLE64S) ? SW64in_CMPLE : ++ (op == Iop_CmpLE64U) ? SW64in_CMPULE : ++ (op == Iop_CasCmpEQ64) ? SW64in_CMPEQ : ++ (vassert(0), 0); ++ ++ addInstr(env, SW64Instr_Cmp(cmp, dst, srcL, srcR)); ++ return dst; ++ } ++ ++ case Iop_CmpNE64: ++ case Iop_CasCmpNE64: { ++ HReg dst = hregIsInvalid(d) ? newVRegI(env) : d; ++ HReg srcL = iselIntExpr(env, arg1); ++ SW64RI8 *srcR = iselIntExpr_RI8(env, arg2); ++ /* Iop_CmpNE64(x, y) = (x == y) ^ 1 */ ++ addInstr(env, SW64Instr_Cmp(SW64in_CMPEQ, dst, srcL, srcR)); ++ addInstr(env, SW64Instr_Logic(SW64in_XOR, dst, dst, SW64RI8_Imm(1))); ++ return dst; ++ } ++ ++ case Iop_CmpFEQ64: ++ case Iop_CmpFNE64: ++ case Iop_CmpFLT64: ++ case Iop_CmpFLE64: ++ case Iop_CmpFGT64: ++ case Iop_CmpFGE64: ++ case Iop_CmpFUN64: { ++ HReg srcL, srcR; ++ SW64FpCmpOp fcmp; ++ Bool swap, rev; ++ ++ switch (op) { ++ case Iop_CmpFEQ64: fcmp = SW64in_CMPFEQ; swap = 0; rev = 0; break; ++ case Iop_CmpFNE64: fcmp = SW64in_CMPFEQ; swap = 0; rev = 1; break; ++ case Iop_CmpFLT64: fcmp = SW64in_CMPFLT; swap = 0; rev = 0; break; ++ case Iop_CmpFLE64: fcmp = SW64in_CMPFLE; swap = 0; rev = 0; break; ++ case Iop_CmpFGT64: fcmp = SW64in_CMPFLT; swap = 1; rev = 0; break; ++ case Iop_CmpFGE64: fcmp = SW64in_CMPFLE; swap = 1; rev = 0; break; ++ case Iop_CmpFUN64: fcmp = SW64in_CMPFUN; swap = 0; rev = 0; break; ++ default: vassert(0); ++ } ++ ++ HReg dst = hregIsInvalid(d) ? newVRegI(env) : d; ++ HReg tmp = newVRegF(env); ++ ++ if (swap == 0) { ++ srcL = iselFltExpr(env, e->Iex.Binop.arg1); ++ srcR = iselFltExpr(env, e->Iex.Binop.arg2); ++ } else { ++ srcL = iselFltExpr(env, e->Iex.Binop.arg2); ++ srcR = iselFltExpr(env, e->Iex.Binop.arg1); ++ } ++ ++ /* compare, and move the result in floatint point register to integer register */ ++ addInstr(env, SW64Instr_FpCmp(fcmp, tmp, srcL, srcR)); ++ addInstr(env, SW64Instr_FpGpMove(SW64in_FIMOVD, dst, tmp)); ++ /* { 0.0F, 2.0F } to { 0x0, 0x1 }*/ ++ if (rev) ++ addInstr(env, SW64Instr_Cmp(SW64in_CMPEQ, dst, hregSW64_R31(), SW64RI8_Reg(dst))); ++ else ++ addInstr(env, SW64Instr_Cmp(SW64in_CMPULT, dst, hregSW64_R31(), SW64RI8_Reg(dst))); ++ ++ return dst; ++ } ++ ++ case Iop_F64toI64S: ++ { ++ HReg dst = hregIsInvalid(d) ? newVRegI(env) : d; ++ HReg tmpF = newVRegF(env); ++ HReg valF = iselFltExpr(env, e->Iex.Binop.arg2); ++ ++ if (const_equal_to(e->Iex.Binop.arg1, Irrm_NEAREST)) { ++ addInstr(env, SW64Instr_FpCvt(SW64in_FCVTDL_G, tmpF, valF)); ++ } else if (const_equal_to(e->Iex.Binop.arg1, Irrm_PosINF)) { ++ addInstr(env, SW64Instr_FpCvt(SW64in_FCVTDL_P, tmpF, valF)); ++ } else if (const_equal_to(e->Iex.Binop.arg1, Irrm_ZERO)) { ++ addInstr(env, SW64Instr_FpCvt(SW64in_FCVTDL_Z, tmpF, valF)); ++ } else if (const_equal_to(e->Iex.Binop.arg1, Irrm_NegINF)) { ++ addInstr(env, SW64Instr_FpCvt(SW64in_FCVTDL_N, tmpF, valF)); ++ } else { ++ /* IR rounding mode is dynamic */ ++ set_SW64_rounding_mode(env, e->Iex.Binop.arg1); ++ addInstr(env, SW64Instr_FpCvt(SW64in_FCVTDL, tmpF, valF)); ++ set_SW64_rounding_default(env); ++ } ++ ++ addInstr(env, SW64Instr_FpGpMove(SW64in_FIMOVD, dst, tmpF)); ++ return dst; ++ } ++ ++ case Iop_F64toI64U: { ++ HReg dst = hregIsInvalid(d) ? newVRegI(env) : d; ++ HReg valF = iselFltExpr(env, e->Iex.Binop.arg2); ++ if (const_equal_to(e->Iex.Binop.arg1, Irrm_NEAREST)) { ++ addInstr(env, SW64Instr_FpGpMove(SW64in_CMOVDLU_G, dst, valF)); ++ } else if (const_equal_to(e->Iex.Binop.arg1, Irrm_PosINF)) { ++ addInstr(env, SW64Instr_FpGpMove(SW64in_CMOVDLU_P, dst, valF)); ++ } else if (const_equal_to(e->Iex.Binop.arg1, Irrm_ZERO)) { ++ addInstr(env, SW64Instr_FpGpMove(SW64in_CMOVDLU_Z, dst, valF)); ++ } else if (const_equal_to(e->Iex.Binop.arg1, Irrm_NegINF)) { ++ addInstr(env, SW64Instr_FpGpMove(SW64in_CMOVDLU_N, dst, valF)); ++ } else { ++ /* IR rounding mode is dynamic */ ++ set_SW64_rounding_mode(env, e->Iex.Binop.arg1); ++ addInstr(env, SW64Instr_FpGpMove(SW64in_CMOVDLU, dst, valF)); ++ set_SW64_rounding_default(env); ++ } ++ return dst; ++ } ++ ++ case Iop_F64toI32U: { ++ HReg dst = hregIsInvalid(d) ? newVRegI(env) : d; ++ HReg valF = iselFltExpr(env, e->Iex.Binop.arg2); ++ if (const_equal_to(e->Iex.Binop.arg1, Irrm_NEAREST)) { ++ addInstr(env, SW64Instr_FpGpMove(SW64in_CMOVDWU_G, dst, valF)); ++ } else if (const_equal_to(e->Iex.Binop.arg1, Irrm_PosINF)) { ++ addInstr(env, SW64Instr_FpGpMove(SW64in_CMOVDWU_P, dst, valF)); ++ } else if (const_equal_to(e->Iex.Binop.arg1, Irrm_ZERO)) { ++ addInstr(env, SW64Instr_FpGpMove(SW64in_CMOVDWU_Z, dst, valF)); ++ } else if (const_equal_to(e->Iex.Binop.arg1, Irrm_NegINF)) { ++ addInstr(env, SW64Instr_FpGpMove(SW64in_CMOVDWU_N, dst, valF)); ++ } else { ++ /* IR rounding mode is dynamic */ ++ set_SW64_rounding_mode(env, e->Iex.Binop.arg1); ++ addInstr(env, SW64Instr_FpGpMove(SW64in_CMOVDWU, dst, valF)); ++ set_SW64_rounding_default(env); ++ } ++ return dst; ++ } ++ ++ case Iop_F64toI32S: { ++ HReg dst = hregIsInvalid(d) ? newVRegI(env) : d; ++ HReg valF = iselFltExpr(env, e->Iex.Binop.arg2); ++ if (const_equal_to(e->Iex.Binop.arg1, Irrm_NEAREST)) { ++ addInstr(env, SW64Instr_FpGpMove(SW64in_CMOVDW_G, dst, valF)); ++ } else if (const_equal_to(e->Iex.Binop.arg1, Irrm_PosINF)) { ++ addInstr(env, SW64Instr_FpGpMove(SW64in_CMOVDW_P, dst, valF)); ++ } else if (const_equal_to(e->Iex.Binop.arg1, Irrm_ZERO)) { ++ addInstr(env, SW64Instr_FpGpMove(SW64in_CMOVDW_Z, dst, valF)); ++ } else if (const_equal_to(e->Iex.Binop.arg1, Irrm_NegINF)) { ++ addInstr(env, SW64Instr_FpGpMove(SW64in_CMOVDW_N, dst, valF)); ++ } else { ++ /* IR rounding mode is dynamic */ ++ set_SW64_rounding_mode(env, e->Iex.Binop.arg1); ++ addInstr(env, SW64Instr_FpGpMove(SW64in_CMOVDW, dst, valF)); ++ set_SW64_rounding_default(env); ++ } ++ return dst; ++ } ++ ++ case Iop_32HLto64: ++ { ++ HReg dst = hregIsInvalid(d) ? newVRegI(env) : d; ++ HReg tHi = iselIntExpr(env, e->Iex.Binop.arg1); ++ HReg tLo = iselIntExpr(env, e->Iex.Binop.arg2); ++ HReg tLo_1 = newVRegI(env); ++ HReg tHi_1 = newVRegI(env); ++ HReg mask = newVRegI(env); ++ addInstr(env, SW64Instr_Shft(SW64in_SLL, tHi_1, tHi, SW64RI8_Imm(32))); ++ addInstr(env, SW64Instr_LoadImm(mask, 0xffffffff)); ++ addInstr(env, SW64Instr_Logic(SW64in_AND, tLo_1, tLo, SW64RI8_Reg(mask))); ++ addInstr(env, SW64Instr_Logic(SW64in_OR, dst, tHi_1, SW64RI8_Reg(tLo_1))); ++ return dst; ++ } ++ ++ default: ++ goto irreducible; ++ } /* switch(op) */ ++ ++ } /* case Iex_Binop */ ++ ++ case Iex_CCall: { ++ vassert(ty == e->Iex.CCall.retty); ++ ++ /* be very restrictive for now. Only 64-bit ints allowed for ++ args, and 64 bits for return type. Don't forget to change ++ the RetLoc if more types are allowed in future. */ ++ if (e->Iex.CCall.retty != Ity_I64) ++ goto irreducible; ++ ++ /* Marshal args, do the call, clear stack. */ ++ HReg dst = hregIsInvalid(d) ? newVRegI(env) : d; ++ UInt addToSp = 0; ++ RetLoc rloc = mk_RetLoc_INVALID(); ++ Bool ok = doHelperCall( &addToSp, &rloc, env, NULL/*guard*/, ++ e->Iex.CCall.cee, e->Iex.CCall.retty, ++ e->Iex.CCall.args ); ++ ++ if (ok) { ++ vassert(is_sane_RetLoc(rloc)); ++ vassert(rloc.pri == RLPri_Int); ++ vassert(addToSp == 0); ++ addInstr(env, SW64Instr_Logic(SW64in_OR, dst, hregSW64_R0(), SW64RI8_Imm(0x0) )); ++ } ++ ++ return dst; ++ } /* case Iex_CCall */ ++ ++ case Iex_ITE: { ++ vassert(ty == Ity_I64 || ty == Ity_I32); ++ vassert(typeOfIRExpr(env->type_env, e->Iex.ITE.cond) == Ity_I1); ++ ++ HReg dst = hregIsInvalid(d) ? newVRegI(env) : d; ++ HReg iftrue = iselIntExpr(env, e->Iex.ITE.iftrue); ++ HReg iffalse = iselIntExpr(env, e->Iex.ITE.iffalse); ++ ++ SW64Cond *cond = iselIntExpr_Cond_wrk(env, e->Iex.ITE.cond); ++ ++ SW64CondSelOp op = (cond->code == SW64cc_EQ) ? SW64in_SELEQ : ++ (cond->code == SW64cc_GE) ? SW64in_SELGE : ++ (cond->code == SW64cc_GT) ? SW64in_SELGT : ++ (cond->code == SW64cc_LE) ? SW64in_SELLE : ++ (cond->code == SW64cc_LT) ? SW64in_SELLT : ++ (cond->code == SW64cc_NE) ? SW64in_SELNE : ++ (vassert(0), 0); ++ ++ addInstr(env, SW64Instr_CondSel(op, dst, iftrue, iffalse, cond->reg)); ++ return dst; ++ } /* case Iex_ITE */ ++ ++ default: ++ goto irreducible; ++ } /* switch (e->tag) */ ++ ++/* We get here if no pattern matched. */ ++irreducible: ++ vex_printf("--------------->\n"); ++ ppIRExpr(e); ++ vpanic("iselIntExpr(sw64): cannot isel word expr"); ++} ++ ++ ++ ++/* DO NOT CALL THIS DIRECTLY ! */ ++static void iselInt128Expr_wrk ( HReg* rHi, HReg* rLo, ++ ISelEnv* env, IRExpr* e ) ++{ ++ vassert(e); ++ vassert(typeOfIRExpr(env->type_env,e) == Ity_I128); ++ ++ /* --------- TEMP --------- */ ++ if (e->tag == Iex_RdTmp) { ++ lookupIRTempPair(rHi, rLo, env, e->Iex.RdTmp.tmp); ++ return; ++ } ++ ++ // /* --------- CONST --------- */ ++ // if (e->tag == Iex_Const) { ++ // IRConst* c = e->Iex.Const.con; ++ // vassert(c->tag == Ico_U128); ++ // if (c->Ico.U128 == 0) { ++ // // The only case we need to handle (so far) ++ // HReg zero = newVRegI(env); ++ // addInstr(env, ARM64Instr_Imm64(zero, 0)); ++ // *rHi = *rLo = zero; ++ // return; ++ // } ++ // } ++ ++ /* --------- BINARY ops --------- */ ++ if (e->tag == Iex_Binop) { ++ switch (e->Iex.Binop.op) { ++ /* 64 x 64 -> 128 multiply */ ++ case Iop_MullU64: ++ { ++ HReg argL = iselIntExpr(env, e->Iex.Binop.arg1); ++ SW64RI8* argR = iselIntExpr_RI8(env, e->Iex.Binop.arg2); ++ HReg dstLo = newVRegI(env); ++ HReg dstHi = newVRegI(env); ++ addInstr(env, SW64Instr_Arith(SW64in_MULL, dstLo, argL, argR)); ++ addInstr(env, SW64Instr_Arith(SW64in_UMULH, dstHi, argL, argR)); ++ *rHi = dstHi; ++ *rLo = dstLo; ++ return; ++ } ++ ++ /* I64,I64 -> I128, of which LO is div and HI is mod */ ++ case Iop_DivModS64to64: ++ case Iop_DivModU64to64: { ++ HReg argL = iselIntExpr(env, e->Iex.Binop.arg1); ++ HReg argR = iselIntExpr(env, e->Iex.Binop.arg2); ++ HReg dstLo = newVRegI(env); ++ HReg dstHi = newVRegI(env); ++ if (e->Iex.Binop.op == Iop_DivModS64to64) { ++ addInstr(env, SW64Instr_IntDiv(SW64in_DIVL, dstLo, argL, argR)); ++ addInstr(env, SW64Instr_IntDiv(SW64in_REML, dstHi, argL, argR)); ++ } else { ++ addInstr(env, SW64Instr_IntDiv(SW64in_UDIVL, dstLo, argL, argR)); ++ addInstr(env, SW64Instr_IntDiv(SW64in_UREML, dstHi, argL, argR)); ++ } ++ *rHi = dstHi; ++ *rLo = dstLo; ++ return; ++ } ++ ++ /* 64HLto128(e1,e2) */ ++ case Iop_64HLto128: ++ *rHi = iselIntExpr(env, e->Iex.Binop.arg1); ++ *rLo = iselIntExpr(env, e->Iex.Binop.arg2); ++ return; ++ default: ++ break; ++ } ++ } ++ ++ ppIRExpr(e); ++ vpanic("iselInt128Expr(sw64)"); ++} ++ ++/* Compute a 128-bit value into a register pair, which is returned as ++ the first two parameters. As with iselIntExpr_R, these may be ++ either real or virtual regs; in any case they must not be changed ++ by subsequent code emitted by the caller. */ ++ ++static void iselInt128Expr ( HReg* rHi, HReg* rLo, ++ ISelEnv* env, IRExpr* e ) ++{ ++ iselInt128Expr_wrk(rHi, rLo, env, e); ++# if 0 ++ vex_printf("\n"); ppIRExpr(e); vex_printf("\n"); ++# endif ++ vassert(hregClass(*rHi) == HRcInt64); ++ vassert(hregIsVirtual(*rHi) || sameHReg(*rHi, SW64Zero())); ++ vassert(hregClass(*rLo) == HRcInt64); ++ vassert(hregIsVirtual(*rLo) || sameHReg(*rLo, SW64Zero())); ++} ++ ++ ++static HReg iselFltExpr(ISelEnv * env, IRExpr * e) ++{ ++ HReg r = iselFltExpr_HReg(env, e, INVALID_HREG); ++ vassert(hregClass(r) == HRcFlt64); ++ vassert(hregIsVirtual(r) || sameHReg(r, hregSW64_F31())); ++ return r; ++} ++ ++static HReg iselFltExpr_HReg(ISelEnv *env, IRExpr *e, HReg d) ++{ ++ IRType ty = typeOfIRExpr(env->type_env, e); ++ vassert(ty == Ity_F32 || ty == Ity_F64); ++ ++ if (!hregIsInvalid(d)) ++ vassert(hregClass(d) == HRcFlt64); ++ ++ switch (e->tag) { ++ case Iex_RdTmp: { ++ HReg src = lookupIRTemp(env, e->Iex.RdTmp.tmp); ++ if (hregIsInvalid(d)) { ++ return src; ++ } else { ++ addInstr(env, SW64Instr_FpCpy(SW64in_FCPYS, d, src, src)); ++ return d; ++ } ++ } ++ ++ case Iex_Const: { ++ /* loading 0:F64 */ ++ if (const_equal_to_float(e, 0) && hregIsInvalid(d)) { ++ return hregSW64_F31(); ++ } ++ ++ IRConst* con = e->Iex.Const.con; ++ SW64FpGpMoveOp movop; ++ union { Float f32; Double f64; ULong u64; } u; ++ vassert(sizeof(u) == 8); ++ if (con->tag == Ico_F64) { ++ u.f64 = con->Ico.F64; ++ movop = SW64in_IFMOVD; ++ } else if (con->tag == Ico_F32) { ++ u.f32 = con->Ico.F32; ++ movop = SW64in_IFMOVS; ++ } else { ++ vassert(0); ++ } ++ ++ HReg tmp = newVRegI(env); ++ HReg dst = hregIsInvalid(d) ? newVRegF(env) : d; ++ addInstr(env, SW64Instr_LoadImm(tmp, u.u64)); ++ addInstr(env, SW64Instr_FpGpMove(movop, dst, tmp)); ++ return dst; ++ } ++ ++ case Iex_Load: { ++ HReg dst = hregIsInvalid(d) ? newVRegF(env) : d; ++ SW64AModeRI *addr = iselWordExpr_AMode(env, e->Iex.Load.addr); ++ if (e->Iex.Load.ty == Ity_F64) ++ addInstr(env, SW64Instr_FpLoad(SW64in_FLDD, dst, addr)); ++ else ++ addInstr(env, SW64Instr_FpLoad(SW64in_FLDS, dst, addr)); ++ return dst; ++ } ++ ++ case Iex_Get: { ++ if (ty == Ity_F64) { ++ HReg dst = hregIsInvalid(d) ? newVRegF(env) : d; ++ SW64AModeRI *addr = SW64AModeRI_IR(e->Iex.Get.offset, SW64GuestStateHreg()); ++ addInstr(env, SW64Instr_FpLoad(SW64in_FLDD, dst, addr)); ++ return dst; ++ } ++ vassert(0); ++ } ++ ++ case Iex_Unop: { ++ IROp iop = e->Iex.Unop.op; ++ ++ switch (iop) { ++ case Iop_F32toF64: { ++ IRExpr *arg = e->Iex.Unop.arg; ++ if (arg->tag == Iex_Unop && arg->Iex.Unop.op == Iop_TruncF64asF32) { ++ HReg dst = hregIsInvalid(d) ? newVRegF(env) : d; ++ HReg src = iselFltExpr_HReg(env, e->Iex.Unop.arg, INVALID_HREG); ++ addInstr(env, SW64Instr_FpCvt(SW64in_FCVTSD, dst, src)); ++ return dst; ++ } else { ++ return iselFltExpr_HReg(env, e->Iex.Unop.arg, d); ++ } ++ } ++ ++ case Iop_I32StoF64: ++ case Iop_I32UtoF64: { ++ HReg dst = hregIsInvalid(d) ? newVRegF(env) : d; ++ HReg src = iselIntExpr(env, e->Iex.Unop.arg); ++ SW64FpGpMoveOp fpop = (iop == Iop_I32StoF64) ? SW64in_CMOVWD : ++ (iop == Iop_I32UtoF64) ? SW64in_CMOVUWD : ++ (vassert(0), 0); ++ addInstr(env, SW64Instr_FpGpMove(fpop, dst, src)); ++ return dst; ++ } ++ ++ case Iop_ReinterpI32asF32: ++ case Iop_ReinterpI64asF64: { ++ HReg dst = hregIsInvalid(d) ? newVRegF(env) : d; ++ SW64FpGpMoveOp swop = (iop == Iop_ReinterpI32asF32) ? SW64in_IFMOVS : ++ (iop == Iop_ReinterpI64asF64) ? SW64in_IFMOVD : ++ (vassert(0), 0); ++ HReg src = iselIntExpr(env, e->Iex.Unop.arg); ++ addInstr(env, SW64Instr_FpGpMove(swop, dst, src)); ++ return dst; ++ } ++ ++ case Iop_NegF32: ++ case Iop_NegF64: { ++ HReg dst = hregIsInvalid(d) ? newVRegF(env) : d; ++ HReg src = iselFltExpr_HReg(env, e->Iex.Unop.arg, INVALID_HREG); ++ addInstr(env, SW64Instr_FpCpy(SW64in_FCPYSN, dst, src, src)); ++ return dst; ++ } ++ ++ case Iop_AbsF32: ++ case Iop_AbsF64: { ++ HReg dst = hregIsInvalid(d) ? newVRegF(env) : d; ++ HReg src = iselFltExpr_HReg(env, e->Iex.Unop.arg, INVALID_HREG); ++ addInstr(env, SW64Instr_FpCpy(SW64in_FCPYS, dst, hregSW64_F31(), src)); ++ return dst; ++ } ++ ++ case Iop_TruncF64asF32: { ++ HReg src = iselFltExpr_HReg(env, e->Iex.Unop.arg, d); ++ return src; ++ } ++ ++ default: ++ vassert(0); ++ } ++ } ++ ++ case Iex_Binop: { ++ IROp iop = e->Iex.Binop.op; ++ ++ switch (iop) { ++ case Iop_SqrtF32: ++ case Iop_SqrtF64: { ++ HReg dst = hregIsInvalid(d) ? newVRegF(env) : d; ++ SW64FpUnaryOp swop = (iop == Iop_SqrtF32) ? SW64in_FSQRTS : ++ (iop == Iop_SqrtF64) ? SW64in_FSQRTD : ++ (vassert(0), 0); ++ HReg src = iselFltExpr_HReg(env, e->Iex.Binop.arg2, INVALID_HREG); ++ addInstr(env, SW64Instr_FpUnary(swop, dst, src)); ++ return dst; ++ } ++ ++ case Iop_F64toF32: { ++ HReg dst = hregIsInvalid(d) ? newVRegF(env) : d; ++ HReg src = iselFltExpr_HReg(env, e->Iex.Binop.arg2, INVALID_HREG); ++ addInstr(env, SW64Instr_FpCvt(SW64in_FCVTDS, dst, src)); ++ return dst; ++ } ++ ++ case Iop_I32StoF32: ++ case Iop_I32UtoF32: ++ case Iop_I64UtoF32: ++ case Iop_I64UtoF64: { ++ HReg dst = hregIsInvalid(d) ? newVRegF(env) : d; ++ HReg src = iselIntExpr(env, e->Iex.Binop.arg2); ++ SW64FpGpMoveOp fpop = (iop == Iop_I32StoF32) ? SW64in_CMOVWS : ++ (iop == Iop_I32UtoF32) ? SW64in_CMOVUWS : ++ (iop == Iop_I64UtoF32) ? SW64in_CMOVULS : ++ (iop == Iop_I64UtoF64) ? SW64in_CMOVULD : ++ (vassert(0), 0); ++ addInstr(env, SW64Instr_FpGpMove(fpop, dst, src)); ++ return dst; ++ } ++ ++ case Iop_I64StoF32: ++ case Iop_I64StoF64: { ++ HReg src; ++ HReg dst = hregIsInvalid(d) ? newVRegF(env) : d; ++ ++ if (e->Iex.Binop.arg2->tag == Iex_Unop && ++ e->Iex.Binop.arg2->Iex.Unop.op == Iop_ReinterpF64asI64) { ++ /* optimize for x = Iop_I64StoF64(Iop_ReinterpF64asI64(x)) */ ++ SW64FpCvtOp fpop = (iop == Iop_I64StoF32) ? SW64in_FCVTLS : ++ (iop == Iop_I64StoF64) ? SW64in_FCVTLD : ++ (vassert(0), 0); ++ src = iselFltExpr(env, e->Iex.Binop.arg2->Iex.Unop.arg); ++ addInstr(env, SW64Instr_FpCvt(fpop, dst, src)); ++ return dst; ++ } ++ ++ src = iselIntExpr(env, e->Iex.Binop.arg2); ++ ++ if (VEX_SW64_FAMILY(env->hwcaps) == VEX_SW64_CORE4) { ++ SW64FpGpMoveOp fpop = (iop == Iop_I64StoF32) ? SW64in_CMOVLS : ++ (iop == Iop_I64StoF64) ? SW64in_CMOVLD : ++ (vassert(0), 0); ++ addInstr(env, SW64Instr_FpGpMove(fpop, dst, src)); ++ } else { ++ HReg tmp = newVRegF(env); ++ SW64FpCvtOp fpop = (iop == Iop_I64StoF32) ? SW64in_FCVTLS : ++ (iop == Iop_I64StoF64) ? SW64in_FCVTLD : ++ (vassert(0), 0); ++ addInstr(env, SW64Instr_FpGpMove(SW64in_IFMOVD, tmp, src)); ++ addInstr(env, SW64Instr_FpCvt(fpop, dst, tmp)); ++ } ++ return dst; ++ } ++ ++ case Iop_RoundF64toF32: { ++ IRExpr *fold = foldF64ArithToF32(e->Iex.Binop.arg2); ++ if (fold) { ++ HReg src = iselFltExpr_HReg(env, fold, d); ++ return src; ++ } else { ++ HReg dst = hregIsInvalid(d) ? newVRegF(env) : d; ++ HReg src = iselFltExpr(env, e->Iex.Binop.arg2); ++ addInstr(env, SW64Instr_FpCvt(SW64in_FCVTDS, dst, src)); ++ return dst; ++ } ++ } ++ ++ case Iop_RoundF64toInt: { ++ HReg dst = hregIsInvalid(d) ? newVRegF(env) : d; ++ HReg valF = iselFltExpr(env, e->Iex.Binop.arg2); ++ if (const_equal_to(e->Iex.Binop.arg1, Irrm_NEAREST)) { ++ addInstr(env, SW64Instr_FpUnary(SW64in_FRID_G, dst, valF)); ++ } else if (const_equal_to(e->Iex.Binop.arg1, Irrm_PosINF)) { ++ addInstr(env, SW64Instr_FpUnary(SW64in_FRID_P, dst, valF)); ++ } else if (const_equal_to(e->Iex.Binop.arg1, Irrm_ZERO)) { ++ addInstr(env, SW64Instr_FpUnary(SW64in_FRID_Z, dst, valF)); ++ } else if (const_equal_to(e->Iex.Binop.arg1, Irrm_NegINF)) { ++ addInstr(env, SW64Instr_FpUnary(SW64in_FRID_N, dst, valF)); ++ } else { ++ /* IR rounding mode is dynamic */ ++ set_SW64_rounding_mode(env, e->Iex.Binop.arg1); ++ addInstr(env, SW64Instr_FpUnary(SW64in_FRID, dst, valF)); ++ set_SW64_rounding_default(env); ++ } ++ return dst; ++ } ++ ++ default: ++ vassert(0); ++ } ++ } ++ ++ case Iex_Triop: { ++ IROp iop = e->Iex.Triop.details->op; ++ SW64FpArithOp swop = (iop == Iop_AddF32) ? SW64in_FADDS : ++ (iop == Iop_AddF64) ? SW64in_FADDD : ++ (iop == Iop_SubF32) ? SW64in_FSUBS : ++ (iop == Iop_SubF64) ? SW64in_FSUBD : ++ (iop == Iop_MulF32) ? SW64in_FMULS : ++ (iop == Iop_MulF64) ? SW64in_FMULD : ++ (iop == Iop_DivF32) ? SW64in_FDIVS : ++ (iop == Iop_DivF64) ? SW64in_FDIVD : ++ (vassert(0), 0); ++ ++ HReg dst = hregIsInvalid(d) ? newVRegF(env) : d; ++ HReg argR = iselFltExpr_HReg(env, e->Iex.Triop.details->arg3, INVALID_HREG); ++ if (const_equal_to(e->Iex.Triop.details->arg1, Irrm_ZERO) && ++ const_equal_to_float(e->Iex.Triop.details->arg2, 1.0) && ++ VEX_SW64_FAMILY(env->hwcaps) == VEX_SW64_CORE4) { ++ if (iop == Iop_DivF64) { ++ addInstr(env, SW64Instr_FpUnary(SW64in_FRECD, dst, argR)); ++ return dst; ++ } else if (iop == Iop_DivF32) { ++ addInstr(env, SW64Instr_FpUnary(SW64in_FRECS, dst, argR)); ++ return dst; ++ } ++ /* - else - fallthrough */ ++ } ++ ++ HReg argL = iselFltExpr_HReg(env, e->Iex.Triop.details->arg2, INVALID_HREG); ++ addInstr(env, SW64Instr_FpArith(swop, dst, argL, argR)); ++ return dst; ++ } ++ ++ case Iex_Qop: { ++ IROp iop = e->Iex.Qop.details->op; ++ SW64FpQuaryOp swop = (iop == Iop_MAddF32) ? SW64in_MADDS : ++ (iop == Iop_MAddF64) ? SW64in_MADDD : ++ (iop == Iop_MSubF32) ? SW64in_MSUBS : ++ (iop == Iop_MSubF64) ? SW64in_MSUBD : ++ (vassert(0), 0); ++ ++ HReg dst = hregIsInvalid(d) ? newVRegF(env) : d; ++ HReg src1 = iselFltExpr_HReg(env, e->Iex.Qop.details->arg2, INVALID_HREG); ++ HReg src2 = iselFltExpr_HReg(env, e->Iex.Qop.details->arg3, INVALID_HREG); ++ HReg src3 = iselFltExpr_HReg(env, e->Iex.Qop.details->arg4, INVALID_HREG); ++ ++ addInstr(env, SW64Instr_FpQuary(swop, dst, src1, src2, src3)); ++ return dst; ++ } ++ ++ case Iex_ITE: { ++ vassert(typeOfIRExpr(env->type_env, e->Iex.ITE.cond) == Ity_I1); ++ HReg dst = hregIsInvalid(d) ? newVRegF(env) : d; ++ ++ /* Fast path for: ITE(CmpFxx64(x), 2, 0) ++ emit FCMPxx only, no need to emit FSELxx */ ++ if (const_equal_to_float(e->Iex.ITE.iftrue, 2) && ++ const_equal_to_float(e->Iex.ITE.iffalse, 0) && ++ e->Iex.ITE.cond->tag == Iex_Binop) { ++ IROp iop = e->Iex.ITE.cond->Iex.Binop.op; ++ SW64FpCmpOp swop = (iop == Iop_CmpFEQ64) ? SW64in_CMPFEQ : ++ (iop == Iop_CmpFLE64) ? SW64in_CMPFLE : ++ (iop == Iop_CmpFLT64) ? SW64in_CMPFLT : ++ (iop == Iop_CmpFUN64) ? SW64in_CMPFUN : ++ -1; ++ if (swop != -1) { ++ HReg argL = iselFltExpr(env, e->Iex.ITE.cond->Iex.Binop.arg1); ++ HReg argR = iselFltExpr(env, e->Iex.ITE.cond->Iex.Binop.arg2); ++ addInstr(env, SW64Instr_FpCmp(swop, dst, argL, argR)); ++ return dst; ++ } ++ } ++ ++ SW64Cond *cond = iselIntExpr_Cond(env, e->Iex.ITE.cond); ++ ++ HReg iftrue = iselFltExpr(env, e->Iex.ITE.iftrue); ++ HReg iffalse = iselFltExpr(env, e->Iex.ITE.iffalse); ++ ++ SW64FpSelOp swop; ++ switch (cond->code) { ++ case SW64cc_FEQ: swop = SW64in_FSELEQ; break; ++ case SW64cc_FNE: swop = SW64in_FSELNE; break; ++ case SW64cc_FLT: swop = SW64in_FSELLT; break; ++ case SW64cc_FLE: swop = SW64in_FSELLE; break; ++ case SW64cc_FGT: swop = SW64in_FSELGT; break; ++ case SW64cc_FGE: swop = SW64in_FSELGE; break; ++ default: { ++ /* slow path */ ++ HReg cond_I = iselIntExpr(env, e->Iex.ITE.cond); ++ HReg cond_F = newVRegF(env); ++ addInstr(env, SW64Instr_FpGpMove(SW64in_IFMOVD, cond_F, cond_I)); ++ addInstr(env, SW64Instr_FpSel(SW64in_FSELNE, dst, iftrue, iffalse, cond_F)); ++ return dst; ++ } ++ } ++ ++ addInstr(env, SW64Instr_FpSel(swop, dst, iftrue, iffalse, cond->reg)); ++ return dst; ++ } ++ ++ default: ++ vassert(0); ++ } ++} ++ ++static Bool uLong_fits_in_16_bits ( ULong u ) ++{ ++ Long i = u & 0xFFFFULL; ++ i <<= 48; ++ i >>= 48; ++ return toBool(u == (ULong) i); ++} ++ ++/*! ++ * IR 表达式指令选择，而该 IR 表达式用作内存读写的目标地址. ++ * 若表达式可以直接被 SW64 的寻址模式支持，则返回的 SW64AMode 表示了该寻址模式 ++ * 否则生成额外指令，回退为简单寄存器寻址 ++ * @param[in] env 上下文环境 ++ * @param[in] e IR 表达式，其类型应为 Ity_I64 ++ * @return SW64AMode 所表示的寻址模式 ++ */ ++static ++SW64AModeRI *iselWordExpr_AMode(ISelEnv * env, IRExpr * e) ++{ ++ SW64AModeRI *am = iselWordExpr_AMode_wrk(env, e); ++ return am; ++} ++ ++static SW64AModeRI *iselWordExpr_AMode_wrk(ISelEnv * env, IRExpr * e) ++{ ++ IRType ty = typeOfIRExpr(env->type_env, e); ++ vassert(ty == Ity_I64); ++ ++ /* Add64(expr,i), where i == sign-extend of (i & 0xFFFF) */ ++ if (e->tag == Iex_Binop && e->Iex.Binop.op == Iop_Add64 ++ && e->Iex.Binop.arg2->tag == Iex_Const ++ && e->Iex.Binop.arg2->Iex.Const.con->tag == Ico_U64 ++ && uLong_fits_in_16_bits(e->Iex.Binop.arg2->Iex.Const.con->Ico.U64)) ++ { ++ /* FIXME: 必然 overflow */ ++ return SW64AModeRI_IR((Int) e->Iex.Binop.arg2->Iex.Const.con->Ico.U64, ++ iselIntExpr(env, e->Iex.Binop.arg1)); ++ } ++ ++ /* Doesn't match anything in particular. Generate it into ++ a register and use that. */ ++ return SW64AModeRI_IR(0, iselIntExpr(env, e)); ++} ++ ++/*! ++ * IR 表达式指令选择，而该 IR 表达式用作支持立即数的操作数. ++ * 若该表示式是一个小于等于 255 的立即数，则返回的 SW64RI8 表示了该立即数， ++ * 否则 SW64RI8 中的结果是一个 HReg，该 HReg 保存了 IR 表达式的计算结果 ++ * @param[in] env 上下文环境 ++ * @param[in] e IR 表达式 ++ * @return 一个小于等于 255 的立即数，或一个保存了计算结果的 HReg ++ */ ++static SW64RI8 *iselIntExpr_RI8(ISelEnv * env, IRExpr * e) ++{ ++ SW64RI8 *ri = iselIntExpr_RI8_wrk(env, e); ++ /* sanity checks ... */ ++ switch (ri->tag) { ++ case Sri8_Imm: ++ return ri; ++ case Sri8_Reg: ++ vassert(hregClass(ri->Sri8.Reg.reg) == HRcInt64); ++ vassert(hregIsVirtual(ri->Sri8.Reg.reg)); ++ return ri; ++ default: ++ vpanic("iselIntExpr_RI8: unknown sw64 RI8 tag"); ++ } ++} ++ ++static SW64RI8 *iselIntExpr_RI8_wrk(ISelEnv * env,IRExpr * e) ++{ ++ IRType ty = typeOfIRExpr(env->type_env, e); ++ vassert(ty == Ity_I1 || ty == Ity_I8 || ty == Ity_I16 || ++ ty == Ity_I32 || ty == Ity_I64); ++ ++ /* fast path: imm less than 255 */ ++ if (e->tag == Iex_Const) { ++ ULong imm; ++ IRConst *con = e->Iex.Const.con; ++ switch (con->tag) { ++ case Ico_U64: imm = con->Ico.U64; break; ++ case Ico_U32: imm = con->Ico.U32; break; ++ case Ico_U16: imm = con->Ico.U16; break; ++ case Ico_U8: imm = con->Ico.U8; break; ++ case Ico_U1: imm = con->Ico.U1; break; ++ default: vpanic("iselIntExpr_RI8.Iex_Const(sw64)"); ++ } ++ /* just use imm instead of SW64Instr_LoadImm */ ++ if (imm <= 255) { ++ return SW64RI8_Imm(imm); ++ } ++ } ++ ++ return SW64RI8_Reg(iselIntExpr(env, e)); ++} ++ ++ ++/*! ++ * IR 表达式指令选择，而该 IR 表达式用作条件执行和条件选择的条件. ++ * 若表达式可以直接被 SW64 的条件类型支持，则返回的 SW64Cond 表示条件寄存器和条件类型 ++ * 否则生成额外指令，回退为 bne / selne 指令 ++ * @param[in] env 上下文环境 ++ * @param[in] e IR 表达式，其类型应为 Ity_I1 ++ * @param[out] code 条件执行的类型 ++ * @param[out] reg 条件执行的寄存器 ++ * return 条件执行的寄存器 ++*/ ++static SW64Cond* iselIntExpr_Cond(ISelEnv *env, IRExpr *e) ++{ ++ SW64Cond *cond; ++ ++ vassert(typeOfIRExpr(env->type_env, e) == Ity_I1); ++ ++ if (e->tag == Iex_Unop && e->Iex.Unop.op == Iop_Not1) { ++ /* fast path for: ++ if (Not1(CmpEQ(x, y))) ++ if (Not1(CmpNE(x, y))) ++ ... ++ is equal to: ++ if (CmpNE(x, y)) ++ if (CmpEQ(x, y)) ++ ... ++ */ ++ vassert(typeOfIRExpr(env->type_env, e->Iex.Unop.arg) == Ity_I1); ++ cond = iselIntExpr_Cond_wrk(env, e->Iex.Unop.arg); ++ switch (cond->code) { ++ case SW64cc_EQ: cond->code = SW64cc_NE; break; ++ case SW64cc_NE: cond->code = SW64cc_EQ; break; ++ case SW64cc_LT: cond->code = SW64cc_GE; break; ++ case SW64cc_GE: cond->code = SW64cc_LT; break; ++ case SW64cc_LE: cond->code = SW64cc_GT; break; ++ case SW64cc_GT: cond->code = SW64cc_LE; break; ++ case SW64cc_FEQ: cond->code = SW64cc_FNE; break; ++ case SW64cc_FNE: cond->code = SW64cc_FEQ; break; ++ case SW64cc_FLT: cond->code = SW64cc_FGE; break; ++ case SW64cc_FLE: cond->code = SW64cc_FGT; break; ++ case SW64cc_FGT: cond->code = SW64cc_FLE; break; ++ case SW64cc_FGE: cond->code = SW64cc_FLT; break; ++ default: vassert(0); ++ } ++ } else { ++ cond = iselIntExpr_Cond_wrk(env, e); ++ } ++ ++ vassert(hregIsVirtual(cond->reg) || sameHReg(hregSW64_R31(), cond->reg)); ++ switch (cond->code) { ++ case SW64cc_EQ: ++ case SW64cc_NE: ++ case SW64cc_LT: ++ case SW64cc_GE: ++ case SW64cc_LE: ++ case SW64cc_GT: ++ vassert(hregClass(cond->reg) == HRcInt64); break; ++ case SW64cc_FEQ: ++ case SW64cc_FNE: ++ case SW64cc_FLT: ++ case SW64cc_FLE: ++ case SW64cc_FGT: ++ case SW64cc_FGE: ++ vassert(hregClass(cond->reg) == HRcFlt64); break; ++ default: ++ vassert(0); ++ } ++ ++ return cond; ++} ++ ++static SW64Cond* iselIntExpr_Cond_wrk(ISelEnv *env, IRExpr *e) ++{ ++ if (e->tag == Iex_Binop) { ++ IROp op = e->Iex.Binop.op; ++ IRExpr *argL = e->Iex.Binop.arg1; ++ IRExpr *argR = e->Iex.Binop.arg2; ++ ++ if (const_equal_to(argR, 0)) { ++ switch (op) { ++ case Iop_CmpEQ64: return SW64Cond_Cond(SW64cc_EQ, iselIntExpr(env, argL)); ++ case Iop_CmpNE64: return SW64Cond_Cond(SW64cc_NE, iselIntExpr(env, argL)); ++ case Iop_CmpLT64S: return SW64Cond_Cond(SW64cc_LT, iselIntExpr(env, argL)); ++ case Iop_CmpLE64S: return SW64Cond_Cond(SW64cc_LE, iselIntExpr(env, argL)); ++ default: break; ++ } ++ } ++ ++ if (const_equal_to(argL, 0)) { ++ switch (op) { ++ case Iop_CmpEQ64: return SW64Cond_Cond(SW64cc_EQ, iselIntExpr(env, argR)); ++ case Iop_CmpNE64: return SW64Cond_Cond(SW64cc_NE, iselIntExpr(env, argR)); ++ case Iop_CmpLT64S: return SW64Cond_Cond(SW64cc_GT, iselIntExpr(env, argR)); ++ case Iop_CmpLE64S: return SW64Cond_Cond(SW64cc_GE, iselIntExpr(env, argR)); ++ default: ++ break; ++ } ++ } ++ ++ if (const_equal_to_float(argR, 0)) { ++ switch (op) { ++ case Iop_CmpFEQ64: return SW64Cond_Cond(SW64cc_FEQ, iselFltExpr(env, argL)); ++ case Iop_CmpFNE64: return SW64Cond_Cond(SW64cc_FNE, iselFltExpr(env, argL)); ++ case Iop_CmpFLT64: return SW64Cond_Cond(SW64cc_FLT, iselFltExpr(env, argL)); ++ case Iop_CmpFLE64: return SW64Cond_Cond(SW64cc_FLE, iselFltExpr(env, argL)); ++ case Iop_CmpFGT64: return SW64Cond_Cond(SW64cc_FGT, iselFltExpr(env, argL)); ++ case Iop_CmpFGE64: return SW64Cond_Cond(SW64cc_FGE, iselFltExpr(env, argL)); ++ default: ++ break; ++ } ++ } ++ } ++ ++ return SW64Cond_Cond(SW64cc_NE, iselIntExpr(env, e)); ++} ++ ++/*---------------------------------------------------------*/ ++/*--- ISEL: Function call helpers ---*/ ++/*---------------------------------------------------------*/ ++/* Used only in doHelperCall. See big comment in doHelperCall re ++ handling of register-parameter args. This function figures out ++ whether evaluation of an expression might require use of a fixed ++ register. If in doubt return True (safe but suboptimal). ++*/ ++static ++Bool mightRequireFixedRegs ( IRExpr* e ) ++{ ++ if (UNLIKELY(is_IRExpr_VECRET_or_GSPTR(e))) { ++ // These are always "safe" -- either a copy of SP in some ++ // arbitrary vreg, or a copy of x21, respectively. ++ return False; ++ } ++ /* Else it's a "normal" expression. */ ++ switch (e->tag) { ++ case Iex_RdTmp: case Iex_Const: case Iex_Get: ++ return False; ++ default: ++ return True; ++ } ++} ++ ++ ++/* Do a complete function call. |guard| is a Ity_Bit expression ++ indicating whether or not the call happens. If guard==NULL, the ++ call is unconditional. |retloc| is set to indicate where the ++ return value is after the call. The caller (of this fn) must ++ generate code to add |stackAdjustAfterCall| to the stack pointer ++ after the call is done. Returns True iff it managed to handle this ++ combination of arg/return types, else returns False. */ ++ ++static ++Bool doHelperCall ( /*OUT*/UInt* stackAdjustAfterCall, ++ /*OUT*/RetLoc* retloc, ++ ISelEnv* env, ++ IRExpr* guard, ++ IRCallee* cee, IRType retTy, IRExpr** args ) ++{ ++ HReg argregs[SW64_N_ARGREGS]; ++ HReg tmpregs[SW64_N_ARGREGS]; ++ Bool go_fast; ++ Int n_args, i, nextArgReg; ++ UInt argiregs; ++ Addr64 target; ++ SW64Cond* cond; ++ ++ vassert(SW64_N_ARGREGS == 6); ++ ++ /* Set default returns. We'll update them later if needed. */ ++ *stackAdjustAfterCall = 0; ++ *retloc = mk_RetLoc_INVALID(); ++ ++ /* These are used for cross-checking that IR-level constraints on ++ the use of IRExpr_VECRET() and IRExpr_GSPTR() are observed. */ ++ UInt nVECRETs = 0; ++ UInt nGSPTRs = 0; ++ ++ /* Marshal args for a call and do the call. ++ ++ This function only deals with a tiny set of possibilities, which ++ cover all helpers in practice. The restrictions are that only ++ arguments in registers are supported, hence only ++ SW64_N_ARGREGS x 64 integer bits in total can be passed. In ++ fact the only supported arg type is I64. ++ ++ The return type can be I{64,32} or V128. In the V128 case, it ++ is expected that |args| will contain the special node ++ IRExpr_VECRET(), in which case this routine generates code to ++ allocate space on the stack for the vector return value. Since ++ we are not passing any scalars on the stack, it is enough to ++ preallocate the return space before marshalling any arguments, ++ in this case. ++ ++ |args| may also contain IRExpr_GSPTR(), in which case the ++ value in x21 is passed as the corresponding argument. ++ ++ Generating code which is both efficient and correct when ++ parameters are to be passed in registers is difficult, for the ++ reasons elaborated in detail in comments attached to ++ doHelperCall() in priv/host-x86/isel.c. Here, we use a variant ++ of the method described in those comments. ++ ++ The problem is split into two cases: the fast scheme and the ++ slow scheme. In the fast scheme, arguments are computed ++ directly into the target (real) registers. This is only safe ++ when we can be sure that computation of each argument will not ++ trash any real registers set by computation of any other ++ argument. ++ ++ In the slow scheme, all args are first computed into vregs, and ++ once they are all done, they are moved to the relevant real ++ regs. This always gives correct code, but it also gives a bunch ++ of vreg-to-rreg moves which are usually redundant but are hard ++ for the register allocator to get rid of. ++ ++ To decide which scheme to use, all argument expressions are ++ first examined. If they are all so simple that it is clear they ++ will be evaluated without use of any fixed registers, use the ++ fast scheme, else use the slow scheme. Note also that only ++ unconditional calls may use the fast scheme, since having to ++ compute a condition expression could itself trash real ++ registers. ++ ++ Note this requires being able to examine an expression and ++ determine whether or not evaluation of it might use a fixed ++ register. That requires knowledge of how the rest of this insn ++ selector works. Currently just the following 3 are regarded as ++ safe -- hopefully they cover the majority of arguments in ++ practice: IRExpr_Tmp IRExpr_Const IRExpr_Get. ++ */ ++ ++ /* Note that the cee->regparms field is meaningless on ARM64 hosts ++ (since there is only one calling convention) and so we always ++ ignore it. */ ++ ++ n_args = 0; ++ for (i = 0; args[i]; i++) { ++ IRExpr* arg = args[i]; ++ if (UNLIKELY(arg->tag == Iex_VECRET)) ++ { ++ nVECRETs++; ++ } else if (UNLIKELY(arg->tag == Iex_GSPTR)) ++ { ++ nGSPTRs++; ++ } ++ n_args++; ++ } ++ ++ /* If this fails, the IR is ill-formed */ ++ vassert(nGSPTRs == 0 || nGSPTRs == 1); ++ ++ /* for sw: there is no vector*/ ++ HReg r_vecRetAddr = INVALID_HREG; ++ vassert(nVECRETs == 0); ++ ++ argregs[0] = hregSW64_R16(); ++ argregs[1] = hregSW64_R17(); ++ argregs[2] = hregSW64_R18(); ++ argregs[3] = hregSW64_R19(); ++ argregs[4] = hregSW64_R20(); ++ argregs[5] = hregSW64_R21(); ++ ++ tmpregs[0] = tmpregs[1] = tmpregs[2] = INVALID_HREG; ++ tmpregs[3] = tmpregs[4] = tmpregs[5] = INVALID_HREG; ++ ++ argiregs = 0; ++ ++ /* First decide which scheme (slow or fast) is to be used. First ++ assume the fast scheme, and select slow if any contraindications ++ (wow) appear. */ ++ ++ go_fast = True; ++ ++ if (guard) { ++ if (guard->tag == Iex_Const ++ && guard->Iex.Const.con->tag == Ico_U1 ++ && guard->Iex.Const.con->Ico.U1 == True) { ++ /* unconditional */ ++ } else { ++ /* Not manifestly unconditional -- be conservative. */ ++ go_fast = False; ++ } ++ } ++ ++ if (go_fast) { ++ for (i = 0; i < n_args; i++) { ++ if (mightRequireFixedRegs(args[i])) { ++ go_fast = False; ++ break; ++ } ++ } ++ } ++ ++ if (go_fast) { ++ if (retTy == Ity_V128 || retTy == Ity_V256) ++ go_fast = False; ++ } ++ ++ /* At this point the scheme to use has been established. Generate ++ code to get the arg values into the argument rregs. If we run ++ out of arg regs, give up. */ ++ ++ if (go_fast) { ++ ++ /* FAST SCHEME */ ++ nextArgReg = 0; ++ ++ for (i = 0; i < n_args; i++) { ++ IRExpr* arg = args[i]; ++ vassert(nextArgReg < SW64_N_ARGREGS); ++ ++ IRType aTy = Ity_INVALID; ++ if (LIKELY(!is_IRExpr_VECRET_or_GSPTR(arg))) ++ aTy = typeOfIRExpr(env->type_env, args[i]); ++ ++ if (aTy == Ity_I64) { ++ addInstr(env, SW64Instr_Logic(SW64in_OR, argregs[nextArgReg], ++ iselIntExpr(env, args[i]), ++ SW64RI8_Imm(0x0))); ++ argiregs |= (1 << (nextArgReg + 0)); ++ nextArgReg++; ++ } ++ else if (arg->tag == Iex_GSPTR) { ++ addInstr(env, SW64Instr_Logic(SW64in_OR, argregs[nextArgReg], ++ SW64GuestStateHreg(), ++ SW64RI8_Imm(0x0))); ++ nextArgReg++; ++ } ++ else if (arg->tag == Iex_VECRET) { ++ // because of the go_fast logic above, we can't get here, ++ // since vector return values makes us use the slow path ++ // instead. ++ vassert(0); ++ } ++ else ++ return False; /* unhandled arg type */ ++ } ++ ++ /* Fast scheme only applies for unconditional calls. Hence: */ ++ cond = SW64Cond_ALWAYS(); ++ } else { ++ ++ /* SLOW SCHEME; move via temporaries */ ++ nextArgReg = 0; ++ ++ for (i = 0; i < n_args; i++) { ++ IRExpr* arg = args[i]; ++ vassert(nextArgReg < SW64_N_ARGREGS); ++ ++ IRType aTy = Ity_INVALID; ++ if (LIKELY(!is_IRExpr_VECRET_or_GSPTR(arg))) ++ aTy = typeOfIRExpr(env->type_env, args[i]); ++ ++ if (aTy == Ity_I64) { ++ tmpregs[nextArgReg] = iselIntExpr(env, args[i]); ++ nextArgReg++; ++ } ++ else if (arg->tag == Iex_GSPTR) { ++ vassert(0); //ATC ++ tmpregs[nextArgReg] = SW64GuestStateHreg(); ++ nextArgReg++; ++ } ++ else if (arg->tag == Iex_VECRET) { ++ vassert(!hregIsInvalid(r_vecRetAddr)); ++ tmpregs[nextArgReg] = r_vecRetAddr; ++ nextArgReg++; ++ } ++ else ++ return False; /* unhandled arg type */ ++ } ++ ++ /* Now we can compute the condition. We can't do it earlier ++ because the argument computations could trash the condition ++ codes. Be a bit clever to handle the common case where the ++ guard is 1:Bit. */ ++ if (guard) { ++ if (guard->tag == Iex_Const ++ && guard->Iex.Const.con->tag == Ico_U1 ++ && guard->Iex.Const.con->Ico.U1 == True) { ++ cond = SW64Cond_ALWAYS(); ++ } else { ++ cond = iselIntExpr_Cond(env, guard); ++ } ++ } else { ++ cond = SW64Cond_ALWAYS(); ++ } ++ ++ /* Move the args to their final destinations. */ ++ for (i = 0; i < nextArgReg; i++) ++ { ++ vassert(!(hregIsInvalid(tmpregs[i]))); ++ /* None of these insns, including any spill code that might ++ be generated, may alter the condition codes. */ ++ argiregs |= (1 << (i + 0)); ++ addInstr( env, SW64Instr_Logic(SW64in_OR, argregs[i], tmpregs[i], SW64RI8_Imm(0x0) )); ++ } ++ ++ } ++ ++ /* Should be assured by checks above */ ++ vassert(nextArgReg <= SW64_N_ARGREGS); ++ ++ /* Do final checks, set the return values, and generate the call ++ instruction proper. */ ++ vassert(nGSPTRs == 0 || nGSPTRs == 1); ++ vassert(nVECRETs == ((retTy == Ity_V128 || retTy == Ity_V256) ? 1 : 0)); ++ vassert(*stackAdjustAfterCall == 0); ++ vassert(is_RetLoc_INVALID(*retloc)); ++ switch (retTy) { ++ case Ity_INVALID: ++ /* Function doesn't return a value. */ ++ *retloc = mk_RetLoc_simple(RLPri_None); ++ break; ++ case Ity_I64: case Ity_I32: case Ity_I16: case Ity_I8: ++ *retloc = mk_RetLoc_simple(RLPri_Int); ++ break; ++ case Ity_V128: ++ *retloc = mk_RetLoc_spRel(RLPri_V128SpRel, 0); ++ *stackAdjustAfterCall = 16; ++ break; ++ case Ity_V256: ++ vassert(0); // ATC ++ *retloc = mk_RetLoc_spRel(RLPri_V256SpRel, 0); ++ *stackAdjustAfterCall = 32; ++ break; ++ default: ++ /* IR can denote other possible return types, but we don't ++ handle those here. */ ++ vassert(0); ++ } ++ ++ /* Finally, generate the call itself. This needs the *retloc value ++ set in the switch above, which is why it's at the end. */ ++ ++ /* nextArgReg doles out argument registers. Since these are ++ assigned in the order a0 .. a5, its numeric value at this point, ++ which must be between 0 and 8 inclusive, is going to be equal to ++ the number of arg regs in use for the call. Hence bake that ++ number into the call (we'll need to know it when doing register ++ allocation, to know what regs the call reads.) */ ++ ++ target = (Addr)cee->addr; ++ addInstr(env, SW64Instr_Call(cond, target, argiregs, *retloc)); ++ ++ return True; /* success */ ++} ++ ++ ++/*---------------------------------------------------------*/ ++/*--- ISEL: Statements ---*/ ++/*---------------------------------------------------------*/ ++ ++static void iselStmt(ISelEnv * env, IRStmt * stmt) ++{ ++ if (vex_traceflags & VEX_TRACE_VCODE) /* debug logger */ ++ { ++ vex_printf("\n-- "); ++ ++ ppIRStmt(stmt); ++ vex_printf("\n"); ++ } ++ ++ switch (stmt->tag) ++ { ++ /* --------- STORE --------- */ ++ case Ist_Store: ++ case Ist_Put: ++ { ++ IRExpr *data; ++ SW64AModeRI *addr; ++ if (stmt->tag == Ist_Store) { ++ data = stmt->Ist.Store.data; ++ addr = iselWordExpr_AMode(env, stmt->Ist.Store.addr); ++ } else { ++ data = stmt->Ist.Put.data; ++ addr = SW64AModeRI_IR(stmt->Ist.Put.offset, ++ SW64GuestStateHreg()); ++ } ++ ++ IRType ty = typeOfIRExpr(env->type_env, data); ++ if (ty == Ity_I8 || ty == Ity_I16 || ty == Ity_I32 || ty == Ity_I64) { ++ HReg src = iselIntExpr(env, data); ++ SW64StoreOp op = (ty == Ity_I8) ? SW64in_STB : ++ (ty == Ity_I16) ? SW64in_STH : ++ (ty == Ity_I32) ? SW64in_STW : ++ (ty == Ity_I64) ? SW64in_STL : ++ (vassert(0), 0); ++ addInstr(env, SW64Instr_Store(op, src, addr)); ++ return; ++ } ++ ++ if (ty == Ity_F32 || ty == Ity_F64) { ++ HReg src = iselFltExpr(env, data); ++ SW64FpStoreOp op = (ty == Ity_F32) ? SW64in_FSTS : ++ (ty == Ity_F64) ? SW64in_FSTD : ++ (vassert(0), 0); ++ addInstr(env, SW64Instr_FpStore(op, src, addr)); ++ return; ++ } ++ ++ goto stmt_fail; ++ } ++ ++ /* --------- WrTmp --------- */ ++ case Ist_WrTmp: //assign statement ++ { ++ IRTemp tmp = stmt->Ist.WrTmp.tmp; ++ IRType ty = typeOfIRTemp(env->type_env, tmp); ++ HReg dst = lookupIRTemp(env, tmp); ++ ++ switch (ty) { ++ case Ity_I1: ++ case Ity_I8: ++ case Ity_I16: ++ case Ity_I32: ++ case Ity_I64: { ++ iselIntExpr_HReg(env, stmt->Ist.WrTmp.data, dst); ++ return; ++ } ++ ++ case Ity_F32: ++ case Ity_F64: { ++ iselFltExpr_HReg(env, stmt->Ist.WrTmp.data, dst); ++ return; ++ } ++ ++ default: ++ goto stmt_fail; ++ } ++ } ++ ++ /* --------- INSTR MARK --------- */ ++ /* Doesn't generate any executable code ... */ ++ case Ist_IMark: ++ return; ++ ++ /* --------- ABI HINT --------- */ ++ /* These have no meaning (denotation in the IR) and so we ignore ++ them ... if any actually made it this far. */ ++ case Ist_AbiHint: ++ return; ++ ++ /* --------- NO-OP --------- */ ++ /* Fairly self-explanatory, wouldn't you say? */ ++ case Ist_NoOp: ++ return; ++ ++ /* --------- EXIT --------- */ ++ case Ist_Exit: //cond branch ++ { ++ IRConst* dst = stmt->Ist.Exit.dst; //jmp address ++ if(dst->tag != Ico_U64) ++ vpanic("iselStmt(sw64): Ist_Exit: dst is not a 64-bit value"); ++ SW64AModeRI* amPC = SW64AModeRI_IR(stmt->Ist.Exit.offsIP, ++ SW64GuestStateHreg()); ++ ++ SW64Cond* cond = iselIntExpr_Cond(env, stmt->Ist.Exit.guard); ++ ++ /* Case: boring transfer to known address */ ++ if (stmt->Ist.Exit.jk == Ijk_Boring) ++ { ++ if (env->chainingAllowed) ++ { ++ /* .. almost always true .. */ ++ /* Skip the event check at the dst if this is a forwards edge. */ ++ Bool toFastEP = ((Addr64)dst->Ico.U64) > env->max_ga; ++ addInstr(env, SW64Instr_XDirect(dst->Ico.U64, amPC, ++ cond, toFastEP)); ++ } ++ else ++ { ++ /* .. very occasionally .. */ ++ /* We can't use chaining, so ask for an assisted transfer, ++ as that's the only alternative that is allowable. */ ++ HReg r = iselIntExpr(env, IRExpr_Const(dst)); ++ addInstr(env, SW64Instr_XAssisted(r, amPC, cond, Ijk_Boring)); ++ } ++ return; ++ } ++ ++ /* Case: assisted transfer to arbitrary address */ ++ switch (stmt->Ist.Exit.jk) ++ { ++ /* Keep this list in sync with that for iselNext below */ ++ case Ijk_ClientReq: ++ case Ijk_NoDecode: ++ case Ijk_NoRedir: ++ case Ijk_Sys_syscall: ++ case Ijk_InvalICache: ++ case Ijk_FlushDCache: ++ case Ijk_SigTRAP: ++ case Ijk_SigBUS: ++ case Ijk_Yield: ++ { ++ HReg r = iselIntExpr(env, IRExpr_Const(dst)); ++ addInstr(env, SW64Instr_XAssisted(r, amPC, cond, ++ stmt->Ist.Exit.jk)); ++ return; ++ } ++ default: ++ break; ++ } ++ ++ /* Do we ever expect to see any other kind? */ ++ goto stmt_fail; ++ } ++ ++ /* --------- Call to DIRTY helper --------- */ ++ /* call complex ("dirty") helper function */ ++ case Ist_Dirty: ++ { ++ IRDirty* d = stmt->Ist.Dirty.details; ++ ++ /* Figure out the return type, if any. */ ++ IRType retty = Ity_INVALID; ++ if (d->tmp != IRTemp_INVALID) ++ retty = typeOfIRTemp(env->type_env, d->tmp); ++ ++ Bool retty_ok = False; ++ switch (retty) ++ { ++ case Ity_INVALID: /* function doesn't return anything */ ++ case Ity_I64: case Ity_I32: case Ity_I16: case Ity_I8: ++ case Ity_V128: ++ retty_ok = True; ++ break; ++ default: ++ break; ++ } ++ if (!retty_ok) ++ break; /* will go to stmt_fail: */ ++ ++ /* Marshal args, do the call, and set the return value to 0x555..555 ++ if this is a conditional call that returns a value and the ++ call is skipped. */ ++ UInt addToSp = 0; ++ RetLoc rloc = mk_RetLoc_INVALID(); ++ doHelperCall( &addToSp, &rloc, env, d->guard, d->cee, retty, d->args ); ++ vassert(is_sane_RetLoc(rloc)); ++ ++ /* Now figure out what to do with the returned value, if any. */ ++ switch (retty) ++ { ++ case Ity_INVALID: ++ { ++ /* No return value. Nothing to do. */ ++ vassert(d->tmp == IRTemp_INVALID); ++ vassert(rloc.pri == RLPri_None); ++ vassert(addToSp == 0); ++ return; ++ } ++ case Ity_I64: case Ity_I32: case Ity_I16: case Ity_I8: ++ { ++ vassert(rloc.pri == RLPri_Int); ++ vassert(addToSp == 0); ++ /* The returned value is in v0. Park it in the register ++ associated with tmp. */ ++ HReg dst = lookupIRTemp(env, d->tmp); ++ addInstr(env, SW64Instr_Logic(SW64in_OR, dst, hregSW64_R0(), SW64RI8_Imm(0x0) )); ++ return; ++ } ++ default: ++ /*NOTREACHED*/ ++ vassert(0); ++ } ++ break; ++ } ++ ++ /* --------- MEM FENCE --------- */ ++ case Ist_MBE: ++ { ++ switch (stmt->Ist.MBE.event) ++ { ++ case Imbe_Fence: ++ addInstr(env, SW64Instr_MFence()); ++ return; ++ case Imbe_CancelReservation: ++ goto stmt_fail; ++ default: ++ /*NOTREACHED*/ ++ vassert(0); ++ } ++ } ++ ++ /* --------- LL/SC --------- */ ++ case Ist_LLSC: ++ { ++ /* 不要使用宿主机上的 LL/SC，不起作用 ++ * SW64 Core 6B 的 LL 和 SC 指令对之间不能包含任何访存指令，否则 SC 必然失败 ++ * 在 valgrind 中，几乎不可能保证两条 IRExpr 之间不包含访存指令，因为 LL 指令的结果会写入客户机的寄存器状态 ++ * 而这一步写入必然需要访存 ++ */ ++ goto stmt_fail; ++ } ++ ++ /* --------- CAS ------------ */ ++ case Ist_CAS: ++ { ++ if (stmt->Ist.CAS.details->oldHi == IRTemp_INVALID) ++ { ++ IRCAS *cas = stmt->Ist.CAS.details; ++ HReg old = lookupIRTemp(env, cas->oldLo); ++ HReg addr = iselIntExpr(env, cas->addr); ++ HReg expd = iselIntExpr(env, cas->expdLo); ++ HReg data = iselIntExpr(env, cas->dataLo); ++ HReg res = newVRegI(env); ++ ++ IRType ty = typeOfIRTemp(env->type_env, cas->oldLo); ++ if (ty == Ity_I64) ++ { ++ addInstr(env, SW64Instr_Cas(8, res, old, addr, expd, data)); ++ } ++ else if (ty == Ity_I32) ++ { ++ addInstr(env, SW64Instr_Cas(4, res, old, addr, expd, data)); ++ } ++ return; ++ } ++ goto stmt_fail; ++ } ++ ++ default: ++ break; ++ } ++ ++ stmt_fail: ++ vex_printf("stmt_fail tag: 0x%x\n", stmt->tag); ++ ppIRStmt(stmt); ++ vpanic("iselStmt:\n"); ++} ++ ++ ++/*---------------------------------------------------------*/ ++/*--- ISEL: Basic block terminators (Nexts) ---*/ ++/*---------------------------------------------------------*/ ++ ++static void iselNext ( ISelEnv* env, ++ IRExpr* next, IRJumpKind jk, Int offsIP ) ++{ ++ if (vex_traceflags & VEX_TRACE_VCODE) { ++ vex_printf( "\n-- PUT(%d) = ", offsIP); ++ ppIRExpr( next ); ++ vex_printf( "; exit-"); ++ ppIRJumpKind(jk); ++ vex_printf( "\n"); ++ } ++ ++ /* Case: boring transfer to known address */ ++ if (next->tag == Iex_Const) { ++ IRConst* cdst = next->Iex.Const.con; ++ vassert(cdst->tag == Ico_U64); ++ if (jk == Ijk_Boring || jk == Ijk_Call) { ++ /* Boring transfer to known address */ ++ SW64AModeRI* amPC = SW64AModeRI_IR(offsIP, SW64GuestStateHreg()); ++ if (env->chainingAllowed) { ++ /* .. almost always true .. */ ++ /* Skip the event check at the dst if this is a forwards edge. */ ++ Bool toFastEP = ((Addr64)cdst->Ico.U64) > ((Addr64)env->max_ga); ++// if (1) vex_printf("[%s] %s\n", __func__, toFastEP ? "X" : "."); ++ addInstr(env, SW64Instr_XDirect( ++ (Addr64)cdst->Ico.U64, ++ amPC, SW64Cond_ALWAYS(), toFastEP)); ++ } else { ++ /* .. very occasionally .. */ ++ /* We can't use chaining, so ask for an assisted transfer, ++ as that's the only alternative that is allowable. */ ++ HReg r = iselIntExpr(env, next); ++ addInstr(env, SW64Instr_XAssisted(r, amPC, SW64Cond_ALWAYS(), ++ Ijk_Boring)); ++ } ++ return; ++ } ++ } ++ ++ /* Case: call/return (==boring) transfer to any address */ ++ switch (jk) ++ { ++ case Ijk_Boring: case Ijk_Ret: case Ijk_Call: ++ { ++ HReg r = iselIntExpr(env, next); ++ SW64AModeRI* amPC = SW64AModeRI_IR(offsIP, SW64GuestStateHreg()); ++ if (env->chainingAllowed) ++ { ++ addInstr(env, SW64Instr_XIndir(r, amPC, SW64Cond_ALWAYS())); ++ } ++ else ++ { ++ addInstr(env, SW64Instr_XAssisted(r, amPC, SW64Cond_ALWAYS(), Ijk_Boring)); ++ } ++ return; ++ } ++ default: ++ break; ++ } ++ ++ /* Case: assisted transfer to arbitrary address */ ++ switch (jk) { ++ /* Keep this list in sync with that for Ist_Exit above */ ++ case Ijk_ClientReq: ++ case Ijk_EmFail: ++ case Ijk_EmWarn: ++ case Ijk_NoDecode: ++ case Ijk_NoRedir: ++ case Ijk_SigBUS: ++ case Ijk_SigILL: ++ case Ijk_SigTRAP: ++ case Ijk_SigFPE_IntDiv: ++ case Ijk_SigFPE_IntOvf: ++ case Ijk_Sys_syscall: ++ case Ijk_InvalICache: ++ { ++ HReg r = iselIntExpr(env, next); ++ SW64AModeRI* amPC = SW64AModeRI_IR(offsIP, SW64GuestStateHreg()); ++ addInstr(env, SW64Instr_XAssisted(r, amPC, SW64Cond_ALWAYS(), jk)); ++ return; ++ } ++ default: ++ break; ++ } ++ ++ vex_printf("\n-- PUT(%d) = ", offsIP); ++ ppIRExpr(next ); ++ vex_printf("; exit-"); ++ ppIRJumpKind(jk); ++ vex_printf("\n"); ++ vassert(0); /* are we expecting any other kind? */ ++} ++ ++ ++/*---------------------------------------------------------*/ ++/*--- Insn selector top-level ---*/ ++/*---------------------------------------------------------*/ ++ ++/* Translate an entire SB to sw64 code. */ ++ ++HInstrArray* iselSB_SW64 ( const IRSB* bb, ++ VexArch arch_host, ++ const VexArchInfo* archinfo_host, ++ const VexAbiInfo* vbi/*UNUSED*/, ++ Int offs_Host_EvC_Counter, ++ Int offs_Host_EvC_FailAddr, ++ Bool chainingAllowed, ++ Bool addProfInc, ++ Addr max_ga ) ++{ ++ /* sanity ... */ ++ vassert(arch_host == VexArchSW64); ++ /* Check that the host's endianness is as expected. */ ++ vassert(archinfo_host->endness == VexEndnessLE); ++ /* guard against unexpected space regressions */ ++ vassert(sizeof(SW64Instr) <= 64); ++ ++ ISelEnv* env; ++ //setup env ++ { ++ env = LibVEX_Alloc_inline(sizeof(ISelEnv)); ++ env->vreg_ctr = 0; ++ env->code = newHInstrArray(); ++ env->type_env = bb->tyenv; ++ env->n_vregmap = bb->tyenv->types_used; ++ env->vregmap = LibVEX_Alloc_inline(env->n_vregmap * sizeof(HReg)); ++ env->vregmapHI = LibVEX_Alloc_inline(env->n_vregmap * sizeof(HReg)); ++ env->chainingAllowed = chainingAllowed; ++ env->max_ga = max_ga; ++ env->hwcaps = archinfo_host->hwcaps; ++ } ++ ++ /* For each IR temporary, allocate a suitably-kinded virtual ++ register. */ ++ Int i, j; ++ HReg hreg, hregHI; ++ j = 0; ++ for (i = 0; i < env->n_vregmap; i++) ++ { ++ hregHI = hreg = INVALID_HREG; ++ switch (bb->tyenv->types[i]) { ++ case Ity_I1: ++ case Ity_I8: ++ case Ity_I16: ++ case Ity_I32: ++ case Ity_I64: ++ hreg = mkHReg(True, HRcInt64, 0, j++); ++ break; ++ case Ity_I128: ++ hreg = mkHReg(True, HRcInt64, 0, j++); ++ hregHI = mkHReg(True, HRcInt64, 0, j++); ++ break; ++ case Ity_F32: ++ case Ity_F64: ++ hreg = mkHReg(True, HRcFlt64, 0, j++); ++ break; ++ case Ity_V128: ++ // hreg = mkHReg(True, HRcVec128, 0, j++); ++ // break; ++ default: ++ ppIRType(bb->tyenv->types[i]); ++ vpanic("iselBB(sw64): IRTemp type"); ++ break; ++ } ++ env->vregmap[i] = hreg; ++ env->vregmapHI[i] = hregHI; ++ } ++ env->vreg_ctr = j; ++ ++ /* The very first instruction must be an event check. */ ++ SW64AModeRI *amCounter, *amFailAddr; ++ amCounter = SW64AModeRI_IR(offs_Host_EvC_Counter, SW64GuestStateHreg()); ++ amFailAddr = SW64AModeRI_IR(offs_Host_EvC_FailAddr, SW64GuestStateHreg()); ++ addInstr(env, SW64Instr_EvCheck(amCounter, amFailAddr)); ++ ++ /* Possibly a block counter increment (for profiling). At this ++ point we don't know the address of the counter, so just pretend ++ it is zero. It will have to be patched later, but before this ++ translation is used, by a call to LibVEX_patchProfCtr. */ ++ if (addProfInc) { ++ addInstr(env, SW64Instr_ProfInc()); ++ } ++ ++ /* Ok, finally we can iterate over the statements. */ ++ for (i = 0; i < bb->stmts_used; i++) ++ iselStmt(env, bb->stmts[i]); ++ ++ iselNext(env, bb->next, bb->jumpkind, bb->offsIP); ++ ++ /* record the number of vregs we used. */ ++ env->code->n_vregs = env->vreg_ctr; ++ return env->code; ++} ++ ++ ++/*---------------------------------------------------------------*/ ++/*--- end host_sw64_isel.c ---*/ ++/*---------------------------------------------------------------*/ ++ +diff --git a/VEX/priv/host_x86_defs.c b/VEX/priv/host_x86_defs.c +index b1c349afb..e8eac96aa 100644 +--- a/VEX/priv/host_x86_defs.c ++++ b/VEX/priv/host_x86_defs.c +@@ -2120,7 +2120,7 @@ static UChar* push_word_from_tags ( UChar* p, UShort tags ) + instruction was a profiler inc, set *is_profInc to True, else + leave it unchanged. */ + +-Int emit_X86Instr ( /*MB_MOD*/Bool* is_profInc, ++Int emit_X86Instr ( /*MB_MOD*/Bool* is_profInc,/*MB_MOD*/Bool* is_8aligned, + UChar* buf, Int nbuf, const X86Instr* i, + Bool mode64, VexEndness endness_host, + const void* disp_cp_chain_me_to_slowEP, +diff --git a/VEX/priv/host_x86_defs.h b/VEX/priv/host_x86_defs.h +index 2455b3245..2a827b50e 100644 +--- a/VEX/priv/host_x86_defs.h ++++ b/VEX/priv/host_x86_defs.h +@@ -714,7 +714,7 @@ extern void ppX86Instr ( const X86Instr*, Bool ); + of the underlying instruction set. */ + extern void getRegUsage_X86Instr ( HRegUsage*, const X86Instr*, Bool ); + extern void mapRegs_X86Instr ( HRegRemap*, X86Instr*, Bool ); +-extern Int emit_X86Instr ( /*MB_MOD*/Bool* is_profInc, ++extern Int emit_X86Instr ( /*MB_MOD*/Bool* is_profInc,/*MB_MOD*/Bool* is_8aligned, + UChar* buf, Int nbuf, const X86Instr* i, + Bool mode64, + VexEndness endness_host, +diff --git a/VEX/priv/ir_defs.c b/VEX/priv/ir_defs.c +index 2d82c41a1..96fe3a323 100644 +--- a/VEX/priv/ir_defs.c ++++ b/VEX/priv/ir_defs.c +@@ -221,6 +221,14 @@ void ppIROp ( IROp op ) + case Iop_CmpwNEZ32: vex_printf("CmpwNEZ32"); return; + case Iop_CmpwNEZ64: vex_printf("CmpwNEZ64"); return; + ++ case Iop_CmpFEQ64: vex_printf("CmpFEQ64"); return; ++ case Iop_CmpFNE64: vex_printf("CmpFNE64"); return; ++ case Iop_CmpFLT64: vex_printf("CmpFLT64"); return; ++ case Iop_CmpFLE64: vex_printf("CmpFLE64"); return; ++ case Iop_CmpFGT64: vex_printf("CmpFGT64"); return; ++ case Iop_CmpFGE64: vex_printf("CmpFGE64"); return; ++ case Iop_CmpFUN64: vex_printf("CmpFUN64"); return; ++ + case Iop_Left8: vex_printf("Left8"); return; + case Iop_Left16: vex_printf("Left16"); return; + case Iop_Left32: vex_printf("Left32"); return; +@@ -1419,6 +1427,8 @@ Bool primopMightTrap ( IROp op ) + case Iop_CmpLT32U: case Iop_CmpLT64U: case Iop_CmpLE32U: case Iop_CmpLE64U: + case Iop_CmpNEZ8: case Iop_CmpNEZ16: case Iop_CmpNEZ32: case Iop_CmpNEZ64: + case Iop_CmpwNEZ32: case Iop_CmpwNEZ64: ++ case Iop_CmpFEQ64: case Iop_CmpFNE64: case Iop_CmpFUN64: ++ case Iop_CmpFLT64: case Iop_CmpFLE64: case Iop_CmpFGT64: case Iop_CmpFGE64: + case Iop_Left8: case Iop_Left16: case Iop_Left32: case Iop_Left64: + case Iop_Max32U: case Iop_CmpORD32U: case Iop_CmpORD64U: + case Iop_CmpORD32S: case Iop_CmpORD64S: +@@ -3263,6 +3273,12 @@ void typeOfPrimop ( IROp op, + case Iop_CmpLT64U: case Iop_CmpLE64U: + COMPARISON(Ity_I64); + ++ case Iop_CmpFEQ64: case Iop_CmpFNE64: ++ case Iop_CmpFLT64: case Iop_CmpFLE64: ++ case Iop_CmpFGT64: case Iop_CmpFGE64: ++ case Iop_CmpFUN64: ++ COMPARISON(Ity_F64); ++ + case Iop_CmpNEZ8: UNARY_COMPARISON(Ity_I8); + case Iop_CmpNEZ16: UNARY_COMPARISON(Ity_I16); + case Iop_CmpNEZ32: UNARY_COMPARISON(Ity_I32); +diff --git a/VEX/priv/ir_opt.c b/VEX/priv/ir_opt.c +index 93dd6188e..e63914281 100644 +--- a/VEX/priv/ir_opt.c ++++ b/VEX/priv/ir_opt.c +@@ -2069,6 +2069,32 @@ static IRExpr* fold_Expr_WRK ( IRExpr** env, IRExpr* e ) + < (ULong)(e->Iex.Binop.arg2->Iex.Const.con->Ico.U64))))); + break; + ++ case Iop_CmpFEQ64: ++ e2 = IRExpr_Const(IRConst_U1(toBool( ++ ((Double)(e->Iex.Binop.arg1->Iex.Const.con->Ico.F64) ++ == (Double)(e->Iex.Binop.arg2->Iex.Const.con->Ico.F64))))); ++ break; ++ case Iop_CmpFLT64: ++ e2 = IRExpr_Const(IRConst_U1(toBool( ++ ((Double)(e->Iex.Binop.arg1->Iex.Const.con->Ico.F64) ++ < (Double)(e->Iex.Binop.arg2->Iex.Const.con->Ico.F64))))); ++ break; ++ case Iop_CmpFLE64: ++ e2 = IRExpr_Const(IRConst_U1(toBool( ++ ((Double)(e->Iex.Binop.arg1->Iex.Const.con->Ico.F64) ++ <= (Double)(e->Iex.Binop.arg2->Iex.Const.con->Ico.F64))))); ++ break; ++ case Iop_CmpFGT64: ++ e2 = IRExpr_Const(IRConst_U1(toBool( ++ ((Double)(e->Iex.Binop.arg1->Iex.Const.con->Ico.F64) ++ > (Double)(e->Iex.Binop.arg2->Iex.Const.con->Ico.F64))))); ++ break; ++ case Iop_CmpFGE64: ++ e2 = IRExpr_Const(IRConst_U1(toBool( ++ ((Double)(e->Iex.Binop.arg1->Iex.Const.con->Ico.F64) ++ >= (Double)(e->Iex.Binop.arg2->Iex.Const.con->Ico.F64))))); ++ break; ++ + /* -- CmpORD -- */ + case Iop_CmpORD32S: { + /* very paranoid */ +diff --git a/VEX/priv/main_main.c b/VEX/priv/main_main.c +index 482047c7a..e56089fe0 100644 +--- a/VEX/priv/main_main.c ++++ b/VEX/priv/main_main.c +@@ -43,6 +43,7 @@ + #include "libvex_guest_s390x.h" + #include "libvex_guest_mips32.h" + #include "libvex_guest_mips64.h" ++#include "libvex_guest_sw64.h" + + #include "main_globals.h" + #include "main_util.h" +@@ -57,6 +58,7 @@ + #include "host_s390_defs.h" + #include "host_mips_defs.h" + #include "host_nanomips_defs.h" ++#include "host_sw64_defs.h" + + #include "guest_generic_bb_to_IR.h" + #include "guest_x86_defs.h" +@@ -67,6 +69,7 @@ + #include "guest_s390_defs.h" + #include "guest_mips_defs.h" + #include "guest_nanomips_defs.h" ++#include "guest_sw64_defs.h" + + #include "host_generic_simd128.h" + +@@ -163,6 +166,14 @@ + #define NANOMIPSST(f) vassert(0) + #endif + ++#if defined(VGA_sw64) || defined(VEXMULTIARCH) ++#define SW64FN(f) f ++#define SW64ST(f) f ++#else ++#define SW64FN(f) NULL ++#define SW64ST(f) vassert(0) ++#endif ++ + /* This file contains the top level interface to the library. */ + + /* --------- fwds ... --------- */ +@@ -541,6 +552,23 @@ IRSB* LibVEX_FrontEnd ( /*MOD*/ VexTranslateArgs* vta, + vassert(sizeof( ((VexGuestMIPS32State*)0)->guest_NRADDR ) == 4); + break; + ++ case VexArchSW64: ++ preciseMemExnsFn ++ = SW64FN(guest_sw64_state_requires_precise_mem_exns); ++ disInstrFn = SW64FN(disInstr_SW64); ++ specHelper = SW64FN(guest_sw64_spechelper); ++ guest_layout = SW64FN(&sw64Guest_layout); ++ offB_CMSTART = offsetof(VexGuestSW64State,guest_CMSTART); ++ offB_CMLEN = offsetof(VexGuestSW64State,guest_CMLEN); ++ offB_GUEST_IP = offsetof(VexGuestSW64State,guest_PC); ++ szB_GUEST_IP = sizeof( ((VexGuestSW64State*)0)->guest_PC ); ++ vassert(vta->archinfo_guest.endness == VexEndnessLE); ++ vassert(0 == sizeof(VexGuestSW64State) % LibVEX_GUEST_STATE_ALIGN); ++ vassert(sizeof( ((VexGuestSW64State*)0)->guest_CMSTART) == 8); ++ vassert(sizeof( ((VexGuestSW64State*)0)->guest_CMLEN ) == 8); ++ vassert(sizeof( ((VexGuestSW64State*)0)->guest_NRADDR ) == 8); ++ break; ++ + default: + vpanic("LibVEX_Translate: unsupported guest insn set"); + } +@@ -745,7 +773,7 @@ static void libvex_BackEnd ( const VexTranslateArgs *vta, + HInstrArray* (*iselSB) ( const IRSB*, VexArch, const VexArchInfo*, + const VexAbiInfo*, Int, Int, Bool, Bool, + Addr ); +- Int (*emit) ( /*MB_MOD*/Bool*, ++ Int (*emit) ( /*MB_MOD*/Bool*, /*MB_MOD*/Bool*, + UChar*, Int, const HInstr*, Bool, VexEndness, + const void*, const void*, const void*, + const void* ); +@@ -759,7 +787,7 @@ static void libvex_BackEnd ( const VexTranslateArgs *vta, + Int offB_HOST_EvC_COUNTER; + Int offB_HOST_EvC_FAILADDR; + Addr max_ga; +- UChar insn_bytes[128]; ++ UChar insn_bytes[256]; /* changed from 128 */ + HInstrArray* vcode; + HInstrArray* rcode; + +@@ -878,6 +906,14 @@ static void libvex_BackEnd ( const VexTranslateArgs *vta, + offB_HOST_EvC_FAILADDR = offsetof(VexGuestMIPS32State,host_EvC_FAILADDR); + break; + ++ case VexArchSW64: ++ preciseMemExnsFn ++ = SW64FN(guest_sw64_state_requires_precise_mem_exns); ++ guest_sizeB = sizeof(VexGuestSW64State); ++ offB_HOST_EvC_COUNTER = offsetof(VexGuestSW64State,host_EvC_COUNTER); ++ offB_HOST_EvC_FAILADDR = offsetof(VexGuestSW64State,host_EvC_FAILADDR); ++ break; ++ + default: + vpanic("LibVEX_Codegen: unsupported guest insn set"); + } +@@ -1052,6 +1088,22 @@ static void libvex_BackEnd ( const VexTranslateArgs *vta, + || vta->archinfo_host.endness == VexEndnessBE); + break; + ++ case VexArchSW64: ++ mode64 = True; ++ rRegUniv = SW64FN(getRRegUniverse_SW64()); ++ getRegUsage ++ = CAST_TO_TYPEOF(getRegUsage) SW64FN(getRegUsage_SW64Instr); ++ mapRegs = CAST_TO_TYPEOF(mapRegs) SW64FN(mapRegs_SW64Instr); ++ genSpill = CAST_TO_TYPEOF(genSpill) SW64FN(genSpill_SW64); ++ genReload = CAST_TO_TYPEOF(genReload) SW64FN(genReload_SW64); ++ genMove = CAST_TO_TYPEOF(genMove) SW64FN(genMove_SW64); ++ ppInstr = CAST_TO_TYPEOF(ppInstr) SW64FN(ppSW64Instr); ++ ppReg = CAST_TO_TYPEOF(ppReg) SW64FN(ppHRegSW64); ++ iselSB = SW64FN(iselSB_SW64); ++ emit = CAST_TO_TYPEOF(emit) SW64FN(emit_SW64Instr); ++ vassert(vta->archinfo_host.endness == VexEndnessLE); ++ break; ++ + default: + vpanic("LibVEX_Translate: unsupported host insn set"); + } +@@ -1168,11 +1220,13 @@ static void libvex_BackEnd ( const VexTranslateArgs *vta, + for (i = 0; i < rcode->arr_used; i++) { + HInstr* hi = rcode->arr[i]; + Bool hi_isProfInc = False; ++ Bool hi_is8aligned = False; + if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) { + ppInstr(hi, mode64); + vex_printf("\n"); + } + j = emit( &hi_isProfInc, ++ &hi_is8aligned, /*add for sw64, some insn's addr need 8-aligned*/ + insn_bytes, sizeof insn_bytes, hi, + mode64, vta->archinfo_host.endness, + vta->disp_cp_chain_me_to_slowEP, +@@ -1197,10 +1251,39 @@ static void libvex_BackEnd ( const VexTranslateArgs *vta, + res->offs_profInc = out_used; + } + { UChar* dst = &vta->host_bytes[out_used]; +- for (k = 0; k < j; k++) { +- dst[k] = insn_bytes[k]; +- } +- out_used += j; ++ if (vta->arch_host == VexArchSW64 && hi_is8aligned) ++ { ++ //sw64: some insn's addr must be 8-aligned,such as lstl/lstw ++ Bool is_8aligned_dst = (0 == (((ULong)(dst)) & ((ULong)0x7))); ++ Bool is_8aligned_insn = (0 == (((ULong)(&insn_bytes)) & ((ULong)0x7))); ++ if (is_8aligned_dst ^ is_8aligned_insn) ++ { ++ //add nop ++ UInt w32 = 0x43ff075f; ++ dst[0] = toUChar(w32 & 0x000000FF); ++ dst[1] = toUChar((w32 >> 8) & 0x000000FF); ++ dst[2] = toUChar((w32 >> 16) & 0x000000FF); ++ dst[3] = toUChar((w32 >> 24) & 0x000000FF); ++ for (k = 0; k < j; k++) { ++ dst[k + 4] = insn_bytes[k]; ++ } ++ out_used += j + 4; ++ } ++ else ++ { ++ //original ++ for (k = 0; k < j; k++) { ++ dst[k] = insn_bytes[k]; ++ } ++ out_used += j; ++ } ++ } else { ++ //original ++ for (k = 0; k < j; k++) { ++ dst[k] = insn_bytes[k]; ++ } ++ out_used += j; ++ } + } + } + *(vta->host_bytes_used) = out_used; +@@ -1209,7 +1292,7 @@ static void libvex_BackEnd ( const VexTranslateArgs *vta, + + vexSetAllocModeTEMP_and_clear(); + +- if (vex_traceflags) { ++ if (vex_traceflags || vta->dump_expansion_ratio) { + /* Print the expansion ratio for this SB. */ + j = 0; /* total guest bytes */ + for (i = 0; i < vta->guest_extents->n_used; i++) { +@@ -1297,6 +1380,12 @@ VexInvalRange LibVEX_Chain ( VexArch arch_host, + place_to_chain, + disp_cp_chain_me_EXPECTED, + place_to_jump_to)); ++ case VexArchSW64: ++ SW64ST(return chainXDirect_SW64(endness_host, ++ place_to_chain, ++ disp_cp_chain_me_EXPECTED, ++ place_to_jump_to)); ++ + default: + vassert(0); + } +@@ -1359,6 +1448,11 @@ VexInvalRange LibVEX_UnChain ( VexArch arch_host, + place_to_unchain, + place_to_jump_to_EXPECTED, + disp_cp_chain_me)); ++ case VexArchSW64: ++ SW64ST(return unchainXDirect_SW64(endness_host, ++ place_to_unchain, ++ place_to_jump_to_EXPECTED, ++ disp_cp_chain_me)); + default: + vassert(0); + } +@@ -1387,8 +1481,10 @@ Int LibVEX_evCheckSzB ( VexArch arch_host ) + MIPS32ST(cached = evCheckSzB_MIPS()); break; + case VexArchMIPS64: + MIPS64ST(cached = evCheckSzB_MIPS()); break; +- case VexArchNANOMIPS: ++ case VexArchNANOMIPS: + NANOMIPSST(cached = evCheckSzB_NANOMIPS()); break; ++ case VexArchSW64: ++ SW64ST(cached = evCheckSzB_SW64()); break; + default: + vassert(0); + } +@@ -1432,6 +1528,9 @@ VexInvalRange LibVEX_PatchProfInc ( VexArch arch_host, + case VexArchNANOMIPS: + NANOMIPSST(return patchProfInc_NANOMIPS(endness_host, place_to_patch, + location_of_counter)); ++ case VexArchSW64: ++ SW64ST(return patchProfInc_SW64(endness_host, place_to_patch, ++ location_of_counter)); + default: + vassert(0); + } +@@ -1515,6 +1614,7 @@ const HChar* LibVEX_ppVexArch ( VexArch arch ) + case VexArchMIPS32: return "MIPS32"; + case VexArchMIPS64: return "MIPS64"; + case VexArchNANOMIPS: return "NANOMIPS"; ++ case VexArchSW64: return "SW64"; + default: return "VexArch???"; + } + } +@@ -1585,6 +1685,7 @@ static IRType arch_word_size (VexArch arch) { + case VexArchMIPS64: + case VexArchPPC64: + case VexArchS390X: ++ case VexArchSW64: + return Ity_I64; + + default: +@@ -1925,6 +2026,18 @@ static const HChar* show_hwcaps_mips64 ( UInt hwcaps ) + return "Unsupported baseline"; + } + ++static const HChar* show_hwcaps_sw64 ( UInt hwcaps ) ++{ ++ switch (VEX_SW64_FAMILY(hwcaps)) { ++ case VEX_SW64_CORE3: ++ return "SW64-CORE3"; ++ case VEX_SW64_CORE4: ++ return "SW64-CORE4"; ++ default: ++ return "Unsupported baseline"; ++ } ++} ++ + #undef NUM_HWCAPS + + /* Thie function must not return NULL. */ +@@ -1941,6 +2054,7 @@ static const HChar* show_hwcaps ( VexArch arch, UInt hwcaps ) + case VexArchS390X: return show_hwcaps_s390x(hwcaps); + case VexArchMIPS32: return show_hwcaps_mips32(hwcaps); + case VexArchMIPS64: return show_hwcaps_mips64(hwcaps); ++ case VexArchSW64: return show_hwcaps_sw64(hwcaps); + default: return NULL; + } + } +@@ -2203,6 +2317,14 @@ static void check_hwcaps ( VexArch arch, UInt hwcaps ) + return; + invalid_hwcaps(arch, hwcaps, "Unsupported baseline\n"); + ++ case VexArchSW64: ++ switch (VEX_SW64_FAMILY(hwcaps)) { ++ case VEX_SW64_CORE3: ++ case VEX_SW64_CORE4: ++ return; ++ default: ++ invalid_hwcaps(arch, hwcaps, "Unsupported baseline\n"); ++ } + default: + vpanic("unknown architecture"); + } +diff --git a/VEX/pub/libvex.h b/VEX/pub/libvex.h +index ec50d52ca..a31fbf400 100644 +--- a/VEX/pub/libvex.h ++++ b/VEX/pub/libvex.h +@@ -60,6 +60,7 @@ typedef + VexArchMIPS32, + VexArchMIPS64, + VexArchNANOMIPS, ++ VexArchSW64, + } + VexArch; + +@@ -299,6 +300,20 @@ typedef + (VEX_MIPS_PROC_ID(x) == VEX_PRID_IMP_P5600) && \ + (VEX_MIPS_HOST_FP_MODE(x))) + ++ ++/* ++ SW64 hwcaps: ++ +----------------------------------------------------+-----------------+ ++ | undefined | cpu family | ++ +----------------------------------------------------+-----------------+ ++ |31 8|7 0| ++ +----------------------------------------------------+-----------------+ ++*/ ++ ++#define VEX_SW64_FAMILY(x) (x & 0xFF) ++#define VEX_SW64_CORE3 3 ++#define VEX_SW64_CORE4 4 ++ + /* These return statically allocated strings. */ + + extern const HChar* LibVEX_ppVexArch ( VexArch ); +@@ -796,6 +811,9 @@ typedef + /* IN: debug: trace vex activity at various points */ + Int traceflags; + ++ /* IN: debug: show instruction expansion ratio */ ++ Bool dump_expansion_ratio; ++ + /* IN: debug: print diagnostics when an illegal instr is detected */ + Bool sigill_diag; + +diff --git a/VEX/pub/libvex_basictypes.h b/VEX/pub/libvex_basictypes.h +index e3f1485d5..393d05663 100644 +--- a/VEX/pub/libvex_basictypes.h ++++ b/VEX/pub/libvex_basictypes.h +@@ -198,6 +198,10 @@ typedef unsigned long HWord; + # define VEX_HOST_WORDSIZE 4 + # define VEX_REGPARM(_n) /* */ + ++#elif defined(__sw_64__) ++# define VEX_HOST_WORDSIZE 8 ++# define VEX_REGPARM(_n) /* */ ++ + #else + # error "Vex: Fatal: Can't establish the host architecture" + #endif +diff --git a/VEX/pub/libvex_guest_sw64.h b/VEX/pub/libvex_guest_sw64.h +new file mode 100644 +index 000000000..70a300bc3 +--- /dev/null ++++ b/VEX/pub/libvex_guest_sw64.h +@@ -0,0 +1,163 @@ ++/*---------------------------------------------------------------*/ ++/*--- begin libvex_guest_sw64.h ---*/ ++/*---------------------------------------------------------------*/ ++ ++/* ++ This file is part of Valgrind, a dynamic binary instrumentation ++ framework. ++ ++ Copyright (C) 2010-2017 RT-RK ++ ++ This program is free software; you can redistribute it and/or ++ modify it under the terms of the GNU General Public License as ++ published by the Free Software Foundation; either version 2 of the ++ License, or (at your option) any later version. ++ ++ This program is distributed in the hope that it will be useful, but ++ WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with this program; if not, see . ++ ++ The GNU General Public License is contained in the file COPYING. ++ ++ Neither the names of the U.S. Department of Energy nor the ++ University of California nor the names of its contributors may be ++ used to endorse or promote products derived from this software ++ without prior written permission. ++*/ ++ ++#ifndef __LIBVEX_PUB_GUEST_SW64_H ++#define __LIBVEX_PUB_GUEST_SW64_H ++ ++#include "libvex_basictypes.h" ++ ++/*---------------------------------------------------------------*/ ++/*--- Vex's representation of the SW64 CPU state. ---*/ ++/*---------------------------------------------------------------*/ ++ ++typedef ++ struct { ++ /*SW_NOT_COMPLETE*/ ++ /* 0 */ ULong host_EvC_FAILADDR; ++ /* 8 */ UInt host_EvC_COUNTER; ++ /* 12 */ UInt _padding1; ++ ++ /* 16 */ ULong guest_PC; /* Program counter */ ++ ++ /* GP Registers */ ++ /* 24 */ ULong guest_r0; /* Values for function returns */ ++ /* 32 */ ULong guest_r1; /* Temporaries */ /* t0-t7 */ ++ /* 40 */ ULong guest_r2; ++ /* 48 */ ULong guest_r3; ++ /* 56 */ ULong guest_r4; ++ /* 64 */ ULong guest_r5; ++ /* 72 */ ULong guest_r6; ++ /* 80 */ ULong guest_r7; ++ /* 88 */ ULong guest_r8; ++ /* 96 */ ULong guest_r9; /* Saved temporaries */ /* s0-s5 */ ++ /* 104 */ ULong guest_r10; ++ /* 112 */ ULong guest_r11; ++ /* 120 */ ULong guest_r12; ++ /* 128 */ ULong guest_r13; ++ /* 136 */ ULong guest_r14; ++ /* 144 */ ULong guest_r15; /* Frame pointer */ ++ /* 152 */ ULong guest_r16; /* Function arguments */ /* a0-a5 */ ++ /* 160 */ ULong guest_r17; ++ /* 168 */ ULong guest_r18; ++ /* 176 */ ULong guest_r19; ++ /* 184 */ ULong guest_r20; ++ /* 192 */ ULong guest_r21; ++ /* 200 */ ULong guest_r22; /* Temporaries */ /* t8-t11 */ ++ /* 208 */ ULong guest_r23; ++ /* 216 */ ULong guest_r24; ++ /* 224 */ ULong guest_r25; ++ /* 232 */ ULong guest_r26; /* Return address */ ++ /* 240 */ ULong guest_r27; /* Procedure value */ ++ /* 248 */ ULong guest_r28; /* Assembler temporary */ ++ /* 256 */ ULong guest_r29; /* Global pointer */ ++ /* 264 */ ULong guest_r30; /* Stack pointer */ ++ /* 272 */ ULong guest_r31; /* Hardwired to 0. */ ++ ++ /* FP Registers */ ++ /* 280 */ ULong guest_f0; /* Return f0 */ ++ /* 288 */ ULong guest_f1; /* Return f1 */ ++ /* 296 */ ULong guest_f2; /* Saved */ /* f2-f9 */ ++ /* 304 */ ULong guest_f3; ++ /* 312 */ ULong guest_f4; ++ /* 320 */ ULong guest_f5; ++ /* 328 */ ULong guest_f6; ++ /* 336 */ ULong guest_f7; ++ /* 344 */ ULong guest_f8; ++ /* 352 */ ULong guest_f9; ++ /* 360 */ ULong guest_f10; /* Temporaries */ /* f10-f15 */ ++ /* 368 */ ULong guest_f11; ++ /* 376 */ ULong guest_f12; ++ /* 384 */ ULong guest_f13; ++ /* 392 */ ULong guest_f14; ++ /* 400 */ ULong guest_f15; ++ /* 408 */ ULong guest_f16; /* Function arguments */ /* f16-f21 */ ++ /* 416 */ ULong guest_f17; ++ /* 424 */ ULong guest_f18; ++ /* 432 */ ULong guest_f19; ++ /* 440 */ ULong guest_f20; ++ /* 448 */ ULong guest_f21; ++ /* 456 */ ULong guest_f22; /* Temporaries */ /* f22-f30 */ ++ /* 464 */ ULong guest_f23; ++ /* 472 */ ULong guest_f24; ++ /* 480 */ ULong guest_f25; ++ /* 488 */ ULong guest_f26; ++ /* 496 */ ULong guest_f27; ++ /* 504 */ ULong guest_f28; ++ /* 512 */ ULong guest_f29; ++ /* 520 */ ULong guest_f30; ++ /* 528 */ ULong guest_f31; ++ ++ /* 544 */ ULong guest_FPCR; ++ /* 536 */ ULong guest_CSR; ++ /* 552 */ ULong guest_TID; ++ /* 560 */ ULong guest_LOCKFLAG; ++ /* 568 */ ULong guest_LOCKVALID; ++ /* 576 */ ULong guest_LOCKSUCCESS; ++ /* 584 */ ULong guest_LOCKSIZE; ++ /* 592 */ ULong guest_LOCKADDR; ++ /* 600 */ ULong guest_LOCKDATA; ++ ++ /* Various pseudo-regs mandated by Vex or Valgrind. */ ++ /* Emulation notes */ ++ /* 608 */ UInt guest_EMNOTE; ++ ++ /* For clflush/clinval: record start and length of area */ ++ /* 616 */ ULong guest_CMSTART; ++ /* 624 */ ULong guest_CMLEN; ++ ++ /* Used to record the unredirected guest address at the start of ++ a translation whose start has been redirected. By reading ++ this pseudo-register shortly afterwards, the translation can ++ find out what the corresponding no-redirection address was. ++ Note, this is only set for wrap-style redirects, not for ++ replace-style ones. */ ++ /* 632 */ULong guest_NRADDR; ++} VexGuestSW64State; ++ ++/*---------------------------------------------------------------*/ ++/*--- Utility functions for SW64 guest stuff. ---*/ ++/*---------------------------------------------------------------*/ ++ ++/* ALL THE FOLLOWING ARE VISIBLE TO LIBRARY CLIENT. */ ++ ++/* Initialise all guest SW64 state. */ ++ ++extern ++void LibVEX_GuestSW64_initialise ( /*OUT*/VexGuestSW64State* vex_state ); ++ ++/* FR bit of CP0_STATUS_FR register */ ++#define SW64_CP0_STATUS_FR (1ul << 26) ++ ++#endif /* ndef __LIBVEX_PUB_GUEST_SW64_H */ ++ ++/*---------------------------------------------------------------*/ ++/*--- libvex_guest_sw64.h - --*/ ++/*---------------------------------------------------------------*/ +diff --git a/VEX/pub/libvex_ir.h b/VEX/pub/libvex_ir.h +index 85805bb69..450d2e07b 100644 +--- a/VEX/pub/libvex_ir.h ++++ b/VEX/pub/libvex_ir.h +@@ -635,6 +635,16 @@ typedef + Iop_CmpF16, + Iop_CmpF128, + ++ /* ---- guest sw64 specifics, float compare ----*/ ++ /* :: F64 x F64 -> CmpResult(I1) */ ++ Iop_CmpFUN64, ++ Iop_CmpFLT64, ++ Iop_CmpFLE64, ++ Iop_CmpFGT64, ++ Iop_CmpFGE64, ++ Iop_CmpFEQ64, ++ Iop_CmpFNE64, ++ + /* --- Int to/from FP conversions. --- */ + + /* For the most part, these take a first argument :: Ity_I32 (as +diff --git a/cachegrind/cg_arch.c b/cachegrind/cg_arch.c +index 52e898218..b0f6d02e9 100644 +--- a/cachegrind/cg_arch.c ++++ b/cachegrind/cg_arch.c +@@ -469,6 +469,12 @@ configure_caches(cache_t *I1c, cache_t *D1c, cache_t *LLc, + *D1c = (cache_t) { 32768, 4, 32 }; + *LLc = (cache_t) { 524288, 8, 32 }; + ++#elif defined(VGA_sw64) ++ ++ *I1c = (cache_t) { 32768, 4, 128 }; ++ *D1c = (cache_t) { 32768, 4, 128 }; ++ *LLc = (cache_t) { 524288, 8, 128 }; ++ + #elif defined(VGA_x86) || defined(VGA_amd64) + + *I1c = (cache_t) { 65536, 2, 64 }; +diff --git a/cachegrind/cg_branchpred.c b/cachegrind/cg_branchpred.c +index ba433ec2c..fd5621a71 100644 +--- a/cachegrind/cg_branchpred.c ++++ b/cachegrind/cg_branchpred.c +@@ -44,7 +44,8 @@ + guaranteed to be zero? */ + #if defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le) \ + || defined(VGA_mips32) || defined(VGA_mips64) || defined(VGA_nanomips) \ +- || defined(VGA_arm64) ++ || defined(VGA_arm64) \ ++ || defined(VGA_sw64) + # define N_IADDR_LO_ZERO_BITS 2 + #elif defined(VGA_x86) || defined(VGA_amd64) + # define N_IADDR_LO_ZERO_BITS 0 +diff --git a/cachegrind/tests/cgout-test2 b/cachegrind/tests/cgout-test2 +new file mode 100644 +index 000000000..376a3b645 +--- /dev/null ++++ b/cachegrind/tests/cgout-test2 +@@ -0,0 +1,3543 @@ ++desc: I1 cache: 32768 B, 64 B, 8-way associative ++desc: D1 cache: 32768 B, 64 B, 8-way associative ++desc: LL cache: 19922944 B, 64 B, 19-way associative ++cmd: ./a.out ++events: Ir I1mr ILmr Dr D1mr DLmr Dw D1mw DLmw ++fl=/build/glibc-OTsEL5/glibc-2.27/csu/../csu/init-first.c ++fn=_init ++52 8 1 1 0 0 0 4 0 0 ++55 4 1 1 1 1 0 1 0 0 ++62 5 1 1 4 1 0 0 0 0 ++67 1 0 0 0 0 0 1 1 1 ++68 1 0 0 0 0 0 1 0 0 ++69 2 0 0 1 1 0 1 1 1 ++81 4 0 0 0 0 0 1 0 0 ++84 1 0 0 0 0 0 1 0 0 ++89 6 0 0 5 0 0 0 0 0 ++fl=/build/glibc-OTsEL5/glibc-2.27/csu/../csu/libc-start.c ++fn=(below main) ++137 10 2 2 0 0 0 7 0 0 ++141 4 0 0 1 0 0 1 0 0 ++239 2 0 0 0 0 0 0 0 0 ++240 4 0 0 0 0 0 1 0 0 ++262 4 1 1 2 0 0 0 0 0 ++265 2 0 0 0 0 0 0 0 0 ++266 5 0 0 4 0 0 1 0 0 ++270 4 0 0 2 0 0 0 0 0 ++285 2 1 1 0 0 0 0 0 0 ++297 2 0 0 0 0 0 1 0 0 ++298 2 0 0 0 0 0 0 0 0 ++303 2 0 0 1 1 0 1 0 0 ++304 2 0 0 1 0 0 1 0 0 ++307 2 0 0 0 0 0 1 0 0 ++310 6 1 1 5 0 0 1 0 0 ++344 2 0 0 0 0 0 1 0 0 ++fl=/build/glibc-OTsEL5/glibc-2.27/csu/../sysdeps/generic/dl-hash.h ++fn=_init ++43 1 0 0 0 0 0 0 0 0 ++44 1 0 0 0 0 0 0 0 0 ++45 13 0 0 4 1 0 0 0 0 ++48 12 0 0 0 0 0 0 0 0 ++62 16 0 0 0 0 0 0 0 0 ++67 1 0 0 0 0 0 0 0 0 ++fl=/build/glibc-OTsEL5/glibc-2.27/csu/../sysdeps/unix/sysv/linux/x86_64/init-first.c ++fn=_init ++36 7 2 2 0 0 0 3 0 0 ++38 4 0 0 0 0 0 1 0 0 ++40 3 0 0 0 0 0 0 0 0 ++41 2 1 1 1 0 0 0 0 0 ++42 1 0 0 0 0 0 1 1 1 ++44 3 0 0 0 0 0 1 0 0 ++45 2 0 0 1 0 0 0 0 0 ++46 1 0 0 0 0 0 1 0 0 ++fl=/build/glibc-OTsEL5/glibc-2.27/ctype/ctype-info.c ++fn=__ctype_init ++31 7 2 2 5 3 0 1 0 0 ++33 4 0 0 2 1 0 1 0 0 ++35 4 0 0 2 0 0 1 0 0 ++36 1 0 0 1 0 0 0 0 0 ++fl=/build/glibc-OTsEL5/glibc-2.27/dlfcn/dlerror.c ++fn=check_free ++186 5 1 1 1 0 0 2 0 0 ++187 3 0 0 1 1 0 0 0 0 ++202 6 1 1 4 0 0 0 0 0 ++fn=fini ++209 2 1 1 0 0 0 0 0 0 ++fl=/build/glibc-OTsEL5/glibc-2.27/dlfcn/dlfcn.c ++fn=init ++29 1 1 1 0 0 0 1 1 0 ++30 1 0 0 0 0 0 1 0 0 ++31 1 0 0 1 0 0 0 0 0 ++fl=/build/glibc-OTsEL5/glibc-2.27/elf/../elf/dl-runtime.c ++fn=_dl_fixup ++66 12 1 0 0 0 0 4 0 0 ++68 4 0 0 4 0 0 0 0 0 ++69 8 1 1 8 0 0 0 0 0 ++72 20 0 0 8 2 0 0 0 0 ++73 28 0 0 8 4 0 4 0 0 ++75 12 0 0 8 0 0 0 0 0 ++80 8 1 1 0 0 0 0 0 0 ++84 8 0 0 4 4 4 0 0 0 ++88 12 0 0 4 1 0 0 0 0 ++92 8 0 0 8 2 0 0 0 0 ++93 16 0 0 4 0 0 0 0 0 ++95 20 1 1 4 1 0 0 0 0 ++101 4 0 0 0 0 0 0 0 0 ++102 12 0 0 4 0 0 0 0 0 ++112 40 1 1 8 1 0 12 0 0 ++116 20 0 0 12 0 0 0 0 0 ++126 28 0 0 8 0 0 0 0 0 ++134 4 0 0 4 0 0 0 0 0 ++142 16 0 0 4 0 0 0 0 0 ++146 12 1 1 4 0 0 0 0 0 ++150 12 0 0 8 0 0 0 0 0 ++fl=/build/glibc-OTsEL5/glibc-2.27/elf/../elf/dl-sysdep.c ++fn=_dl_sysdep_start ++88 8 1 1 0 0 0 6 0 0 ++89 10 1 1 4 1 1 5 0 0 ++90 1 0 0 0 0 0 0 0 0 ++112 1 0 0 0 0 0 1 0 0 ++113 303 1 1 99 13 13 4 3 3 ++116 2 0 0 0 0 0 1 1 1 ++117 1 1 1 0 0 0 1 0 0 ++119 126 5 5 32 4 4 13 1 1 ++120 110 0 0 18 3 3 0 0 0 ++123 1 0 0 1 0 0 0 0 0 ++126 1 1 1 1 0 0 0 0 0 ++129 1 1 1 1 0 0 0 0 0 ++130 1 0 0 0 0 0 0 0 0 ++132 1 0 0 1 1 1 0 0 0 ++133 1 0 0 0 0 0 0 0 0 ++153 1 1 1 1 0 0 0 0 0 ++154 1 0 0 0 0 0 0 0 0 ++156 1 0 0 1 0 0 0 0 0 ++157 1 0 0 0 0 0 0 0 0 ++159 2 2 2 1 1 1 1 0 0 ++160 1 0 0 0 0 0 1 0 0 ++165 2 0 0 1 0 0 1 0 0 ++166 1 0 0 0 0 0 1 0 0 ++181 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0 ++2206 414 0 0 0 0 0 0 0 0 ++2211 726 0 0 0 0 0 0 0 0 ++2217 726 0 0 726 0 0 0 0 0 ++2218 726 0 0 726 0 0 0 0 0 ++2226 726 0 0 0 0 0 0 0 0 ++2227 726 0 0 726 0 0 0 0 0 ++fl=/build/glibc-OTsEL5/glibc-2.27/string/../sysdeps/x86_64/strcspn.S ++fn=strcspn ++30 2 1 1 0 0 0 0 0 0 ++37 2 0 0 0 0 0 0 0 0 ++38 2 0 0 0 0 0 0 0 0 ++40 2 0 0 0 0 0 0 0 0 ++41 2 0 0 0 0 0 0 0 0 ++42 2 0 0 0 0 0 0 0 0 ++43 2 0 0 0 0 0 0 0 0 ++44 66 0 0 0 0 0 64 4 4 ++47 4 0 0 0 0 0 0 0 0 ++54 2 0 0 2 0 0 0 0 0 ++55 2 0 0 0 0 0 0 0 0 ++56 2 0 0 0 0 0 0 0 0 ++57 2 0 0 0 0 0 2 0 0 ++59 2 0 0 2 0 0 0 0 0 ++60 2 0 0 0 0 0 0 0 0 ++61 2 1 1 0 0 0 0 0 0 ++62 2 0 0 0 0 0 2 0 0 ++64 2 0 0 2 0 0 0 0 0 ++65 2 0 0 0 0 0 0 0 0 ++66 2 0 0 0 0 0 0 0 0 ++75 6 0 0 0 0 0 0 0 0 ++87 17 0 0 0 0 0 0 0 0 ++89 17 0 0 17 0 0 0 0 0 ++90 17 0 0 17 0 0 0 0 0 ++91 17 0 0 0 0 0 0 0 0 ++93 17 0 0 17 0 0 0 0 0 ++94 17 0 0 17 0 0 0 0 0 ++95 17 0 0 0 0 0 0 0 0 ++97 17 0 0 17 0 0 0 0 0 ++98 17 0 0 17 0 0 0 0 0 ++99 17 0 0 0 0 0 0 0 0 ++101 16 0 0 16 0 0 0 0 0 ++102 16 0 0 16 0 0 0 0 0 ++103 16 0 0 0 0 0 0 0 0 ++105 1 0 0 0 0 0 0 0 0 ++106 2 0 0 0 0 0 0 0 0 ++107 2 0 0 0 0 0 0 0 0 ++109 2 0 0 0 0 0 0 0 0 ++116 2 0 0 0 0 0 0 0 0 ++120 2 0 0 2 0 0 0 0 0 ++fl=/build/glibc-OTsEL5/glibc-2.27/string/strdup.c ++fn=strdup ++40 28 1 1 0 0 0 14 0 0 ++41 14 0 0 0 0 0 7 0 0 ++42 14 0 0 0 0 0 7 0 0 ++44 14 0 0 0 0 0 0 0 0 ++47 28 0 0 0 0 0 0 0 0 ++48 21 0 0 14 0 0 0 0 0 ++fl=/build/glibc-OTsEL5/glibc-2.27/time/../sysdeps/generic/dl-hash.h ++fn=gettimeofday ++43 1 0 0 0 0 0 0 0 0 ++44 1 0 0 0 0 0 0 0 0 ++45 13 0 0 4 0 0 0 0 0 ++48 12 0 0 0 0 0 0 0 0 ++62 16 0 0 0 0 0 0 0 0 ++67 1 0 0 0 0 0 0 0 0 ++fn=time ++44 1 0 0 0 0 0 0 0 0 ++45 13 0 0 4 1 1 0 0 0 ++48 12 0 0 0 0 0 0 0 0 ++62 16 1 1 0 0 0 0 0 0 ++67 1 0 0 0 0 0 0 0 0 ++fl=/build/glibc-OTsEL5/glibc-2.27/time/../sysdeps/unix/sysv/linux/x86/gettimeofday.c ++fn=gettimeofday ++42 16 3 3 1 0 0 4 0 0 ++fl=/build/glibc-OTsEL5/glibc-2.27/time/../sysdeps/unix/sysv/linux/x86/time.c ++fn=time ++43 17 2 2 1 0 0 4 0 0 ++fl=/build/glibc-OTsEL5/glibc-2.27/wcsmbs/../sysdeps/x86_64/multiarch/ifunc-avx2.h ++fn=wcschr ++30 8 0 0 0 0 0 0 0 0 ++32 6 2 2 4 0 0 0 0 0 ++fn=wcslen ++30 4 0 0 0 0 0 0 0 0 ++32 3 2 2 2 0 0 0 0 0 ++fn=wmemchr ++30 8 0 0 0 0 0 0 0 0 ++32 6 1 1 4 0 0 0 0 0 ++fl=/build/glibc-OTsEL5/glibc-2.27/wcsmbs/../sysdeps/x86_64/multiarch/ifunc-wmemset.h ++fn=wmemset ++30 6 0 0 0 0 0 0 0 0 ++32 8 1 1 4 0 0 0 0 0 ++34 8 1 1 0 0 0 0 0 0 ++35 2 0 0 0 0 0 0 0 0 ++fl=/build/glibc-OTsEL5/glibc-2.27/wcsmbs/../sysdeps/x86_64/multiarch/wcschr.c ++fn=wcschr ++31 2 0 0 2 0 0 0 0 0 ++fl=/build/glibc-OTsEL5/glibc-2.27/wcsmbs/../sysdeps/x86_64/multiarch/wcslen.c ++fn=wcslen ++29 1 0 0 1 0 0 0 0 0 ++fl=/build/glibc-OTsEL5/glibc-2.27/wcsmbs/../sysdeps/x86_64/multiarch/wcsnlen.c ++fn=wcsnlen ++38 3 0 0 0 0 0 0 0 0 ++40 3 1 1 2 0 0 0 0 0 ++49 1 0 0 1 0 0 0 0 0 ++fl=/build/glibc-OTsEL5/glibc-2.27/wcsmbs/../sysdeps/x86_64/multiarch/wmemchr.c ++fn=wmemchr ++31 2 0 0 2 0 0 0 0 0 ++fl=/build/glibc-OTsEL5/glibc-2.27/wcsmbs/../sysdeps/x86_64/multiarch/wmemset.c ++fn=wmemset ++31 2 0 0 2 0 0 0 0 0 ++fl=a.c ++fn=main ++1 2 0 0 0 0 0 1 0 0 ++2 1 1 1 0 0 0 1 0 0 ++3 6000004 0 0 1000001 0 0 1 0 0 ++4 4000000 0 0 1000000 0 0 0 0 0 ++6 6 0 0 1 0 0 0 0 0 ++7 2 0 0 2 0 0 0 0 0 ++fl=??? ++fn=??? ++0 427 41 34 172 14 0 49 1 1 ++fn=__libc_csu_init ++0 34 2 2 8 0 0 8 0 0 ++fn=_start ++0 11 2 2 2 0 0 3 0 0 ++summary: 10229753 952 931 2057955 1918 1520 18005 745 699 +diff --git a/configure.ac b/configure.ac +index 79b17f394..a07d04021 100755 +--- a/configure.ac ++++ b/configure.ac +@@ -309,11 +309,14 @@ case "${host_cpu}" in + AC_MSG_RESULT([ok (${host_cpu})]) + ARCH_MAX="nanomips" + ;; +- +- *) +- AC_MSG_RESULT([no (${host_cpu})]) +- AC_MSG_ERROR([Unsupported host architecture. Sorry]) +- ;; ++ sw_64*) ++ AC_MSG_RESULT([ok (${host_cpu})]) ++ ARCH_MAX="sw64" ++ ;; ++ *) ++ AC_MSG_RESULT([no (${host_cpu})]) ++ AC_MSG_ERROR([Unsupported host architecture. Sorry]) ++ ;; + esac + + #---------------------------------------------------------------------------- +@@ -941,6 +944,17 @@ case "$ARCH_MAX-$VGCONF_OS" in + valt_load_address_sec_inner="0xUNSET" + AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})]) + ;; ++ sw64-linux) ++ VGCONF_ARCH_PRI="sw64" ++ VGCONF_ARCH_SEC="" ++ VGCONF_PLATFORM_PRI_CAPS="SW64_LINUX" ++ VGCONF_PLATFORM_SEC_CAPS="" ++ valt_load_address_pri_norml="0x58000000" ++ valt_load_address_pri_inner="0x38000000" ++ valt_load_address_sec_norml="0xUNSET" ++ valt_load_address_sec_inner="0xUNSET" ++ AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})]) ++ ;; + x86-solaris) + VGCONF_ARCH_PRI="x86" + VGCONF_ARCH_SEC="" +@@ -1033,6 +1047,8 @@ AM_CONDITIONAL(VGCONF_ARCHS_INCLUDE_MIPS64, + test x$VGCONF_PLATFORM_PRI_CAPS = xMIPS64_LINUX ) + AM_CONDITIONAL(VGCONF_ARCHS_INCLUDE_NANOMIPS, + test x$VGCONF_PLATFORM_PRI_CAPS = xNANOMIPS_LINUX ) ++AM_CONDITIONAL(VGCONF_ARCHS_INCLUDE_SW64, ++ test x$VGCONF_PLATFORM_PRI_CAPS = xSW64_LINUX ) + + # Set up VGCONF_PLATFORMS_INCLUDE_. Either one or two of these + # become defined. +@@ -1063,6 +1079,8 @@ AM_CONDITIONAL(VGCONF_PLATFORMS_INCLUDE_MIPS64_LINUX, + test x$VGCONF_PLATFORM_PRI_CAPS = xMIPS64_LINUX) + AM_CONDITIONAL(VGCONF_PLATFORMS_INCLUDE_NANOMIPS_LINUX, + test x$VGCONF_PLATFORM_PRI_CAPS = xNANOMIPS_LINUX) ++AM_CONDITIONAL(VGCONF_PLATFORMS_INCLUDE_SW64_LINUX, ++ test x$VGCONF_PLATFORM_PRI_CAPS = xSW64_LINUX) + AM_CONDITIONAL(VGCONF_PLATFORMS_INCLUDE_X86_FREEBSD, + test x$VGCONF_PLATFORM_PRI_CAPS = xX86_FREEBSD \ + -o x$VGCONF_PLATFORM_SEC_CAPS = xX86_FREEBSD) +@@ -1094,7 +1112,8 @@ AM_CONDITIONAL(VGCONF_OS_IS_LINUX, + -o x$VGCONF_PLATFORM_PRI_CAPS = xS390X_LINUX \ + -o x$VGCONF_PLATFORM_PRI_CAPS = xMIPS32_LINUX \ + -o x$VGCONF_PLATFORM_PRI_CAPS = xMIPS64_LINUX \ +- -o x$VGCONF_PLATFORM_PRI_CAPS = xNANOMIPS_LINUX) ++ -o x$VGCONF_PLATFORM_PRI_CAPS = xNANOMIPS_LINUX \ ++ -o x$VGCONF_PLATFORM_PRI_CAPS = xSW64_LINUX) + AM_CONDITIONAL(VGCONF_OS_IS_FREEBSD, + test x$VGCONF_PLATFORM_PRI_CAPS = xX86_FREEBSD \ + -o x$VGCONF_PLATFORM_PRI_CAPS = xAMD64_FREEBSD) +@@ -4819,8 +4838,6 @@ AC_CHECK_FUNCS([ \ + ppoll \ + preadv \ + preadv2 \ +- process_vm_readv \ +- process_vm_writev \ + pthread_barrier_init \ + pthread_condattr_setclock \ + pthread_mutex_timedlock \ +@@ -4852,6 +4869,14 @@ AC_CHECK_FUNCS([ \ + strndup \ + ]) + ++# Ignore process_vm_readv and process_vm_writev check on sw64 ++if test x$VGCONF_PLATFORM_PRI_CAPS != xSW64_LINUX; then ++ AC_CHECK_FUNCS([ \ ++ process_vm_readv \ ++ process_vm_writev \ ++ ]) ++fi ++ + # AC_CHECK_LIB adds any library found to the variable LIBS, and links these + # libraries with any shared object and/or executable. This is NOT what we + # want for e.g. vgpreload_core-x86-linux.so +@@ -4908,7 +4933,8 @@ elif test x$VGCONF_PLATFORM_PRI_CAPS = xAMD64_LINUX \ + -o x$VGCONF_PLATFORM_PRI_CAPS = xPPC64_LINUX \ + -o x$VGCONF_PLATFORM_PRI_CAPS = xARM64_LINUX \ + -o x$VGCONF_PLATFORM_PRI_CAPS = xMIPS64_LINUX \ +- -o x$VGCONF_PLATFORM_PRI_CAPS = xS390X_LINUX ; then ++ -o x$VGCONF_PLATFORM_PRI_CAPS = xS390X_LINUX \ ++ -o x$VGCONF_PLATFORM_PRI_CAPS = xSW64_LINUX ; then + mflag_primary=$FLAG_M64 + elif test x$VGCONF_PLATFORM_PRI_CAPS = xX86_DARWIN ; then + mflag_primary="$FLAG_M32 -arch i386" +@@ -5407,6 +5433,7 @@ AC_CONFIG_FILES([ + memcheck/tests/s390x/Makefile + memcheck/tests/mips32/Makefile + memcheck/tests/mips64/Makefile ++ memcheck/tests/sw64/Makefile + memcheck/tests/vbit-test/Makefile + cachegrind/Makefile + cachegrind/tests/Makefile +@@ -5443,6 +5470,8 @@ AC_CONFIG_FILES([ + none/tests/mips32/Makefile + none/tests/mips64/Makefile + none/tests/nanomips/Makefile ++ none/tests/sw64/Makefile ++ none/tests/sw64-linux/Makefile + none/tests/linux/Makefile + none/tests/darwin/Makefile + none/tests/solaris/Makefile +diff --git a/coregrind/Makefile.am b/coregrind/Makefile.am +index 80115f21f..6b3528565 100644 +--- a/coregrind/Makefile.am ++++ b/coregrind/Makefile.am +@@ -337,6 +337,7 @@ COREGRIND_SOURCES_COMMON = \ + m_stacks.c \ + m_stacktrace.c \ + m_syscall.c \ ++ m_swdiv.S \ + m_threadstate.c \ + m_tooliface.c \ + m_trampoline.S \ +@@ -387,6 +388,7 @@ COREGRIND_SOURCES_COMMON = \ + m_dispatch/dispatch-mips32-linux.S \ + m_dispatch/dispatch-mips64-linux.S \ + m_dispatch/dispatch-nanomips-linux.S \ ++ m_dispatch/dispatch-sw64-linux.S \ + m_dispatch/dispatch-x86-freebsd.S \ + m_dispatch/dispatch-amd64-freebsd.S \ + m_dispatch/dispatch-x86-darwin.S \ +@@ -411,6 +413,7 @@ COREGRIND_SOURCES_COMMON = \ + m_gdbserver/valgrind-low-mips32.c \ + m_gdbserver/valgrind-low-mips64.c \ + m_gdbserver/valgrind-low-nanomips.c \ ++ m_gdbserver/valgrind-low-sw64.c \ + m_gdbserver/version.c \ + m_initimg/initimg-linux.c \ + m_initimg/initimg-freebsd.c \ +@@ -438,6 +441,7 @@ COREGRIND_SOURCES_COMMON = \ + m_sigframe/sigframe-mips32-linux.c \ + m_sigframe/sigframe-mips64-linux.c \ + m_sigframe/sigframe-nanomips-linux.c \ ++ m_sigframe/sigframe-sw64-linux.c \ + m_sigframe/sigframe-x86-darwin.c \ + m_sigframe/sigframe-amd64-darwin.c \ + m_sigframe/sigframe-solaris.c \ +@@ -452,6 +456,7 @@ COREGRIND_SOURCES_COMMON = \ + m_syswrap/syscall-mips32-linux.S \ + m_syswrap/syscall-mips64-linux.S \ + m_syswrap/syscall-nanomips-linux.S \ ++ m_syswrap/syscall-sw64-linux.S \ + m_syswrap/syscall-x86-freebsd.S \ + m_syswrap/syscall-amd64-freebsd.S \ + m_syswrap/syscall-x86-darwin.S \ +@@ -477,6 +482,7 @@ COREGRIND_SOURCES_COMMON = \ + m_syswrap/syswrap-mips32-linux.c \ + m_syswrap/syswrap-mips64-linux.c \ + m_syswrap/syswrap-nanomips-linux.c \ ++ m_syswrap/syswrap-sw64-linux.c \ + m_syswrap/syswrap-x86-darwin.c \ + m_syswrap/syswrap-amd64-darwin.c \ + m_syswrap/syswrap-xen.c \ +diff --git a/coregrind/launcher-linux.c b/coregrind/launcher-linux.c +index bc95e3c11..80fb1b01d 100644 +--- a/coregrind/launcher-linux.c ++++ b/coregrind/launcher-linux.c +@@ -415,7 +415,8 @@ int main(int argc, char** argv, char** envp) + (0==strcmp(VG_PLATFORM,"s390x-linux")) || + (0==strcmp(VG_PLATFORM,"mips32-linux")) || + (0==strcmp(VG_PLATFORM,"mips64-linux")) || +- (0==strcmp(VG_PLATFORM,"nanomips-linux"))) ++ (0==strcmp(VG_PLATFORM,"nanomips-linux")) || ++ (0==strcmp(VG_PLATFORM,"sw64-linux"))) + default_platform = VG_PLATFORM; + # elif defined(VGO_solaris) + if ((0==strcmp(VG_PLATFORM,"x86-solaris")) || +@@ -474,7 +475,7 @@ int main(int argc, char** argv, char** envp) + launcher_name = ""; + break; + } +- if (r == bufsiz) continue; // buffer to small; retry ++ if (r == bufsiz) continue; // buffer too small; retry + + assert(r < bufsiz); // paranoia + +diff --git a/coregrind/m_aspacemgr/aspacemgr-common.c b/coregrind/m_aspacemgr/aspacemgr-common.c +index 816d2274f..93e07ceab 100644 +--- a/coregrind/m_aspacemgr/aspacemgr-common.c ++++ b/coregrind/m_aspacemgr/aspacemgr-common.c +@@ -157,7 +157,8 @@ SysRes VG_(am_do_mmap_NO_NOTIFY)( Addr start, SizeT length, UInt prot, + # elif defined(VGP_amd64_linux) \ + || defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) \ + || defined(VGP_s390x_linux) || defined(VGP_mips32_linux) \ +- || defined(VGP_mips64_linux) || defined(VGP_arm64_linux) ++ || defined(VGP_mips64_linux) || defined(VGP_arm64_linux) \ ++ || defined(VGP_sw64_linux) + res = VG_(do_syscall6)(__NR_mmap, (UWord)start, length, + prot, flags, fd, offset); + # elif defined(VGP_x86_darwin) +diff --git a/coregrind/m_aspacemgr/aspacemgr-linux.c b/coregrind/m_aspacemgr/aspacemgr-linux.c +index ae38d8bd0..ee8f6a08c 100644 +--- a/coregrind/m_aspacemgr/aspacemgr-linux.c ++++ b/coregrind/m_aspacemgr/aspacemgr-linux.c +@@ -828,6 +828,7 @@ static void sync_check_mapping_callback ( Addr addr, SizeT len, UInt prot, + # if defined(VGA_x86) || defined (VGA_s390x) || \ + defined(VGA_mips32) || defined(VGA_mips64) + sloppyXcheck = True; ++ /* TODO(Shaohua): SW_NOT_COMPLETE */ + # else + sloppyXcheck = False; + # endif +diff --git a/coregrind/m_cache.c b/coregrind/m_cache.c +index 428a4df43..0257dac94 100644 +--- a/coregrind/m_cache.c ++++ b/coregrind/m_cache.c +@@ -539,7 +539,8 @@ get_cache_info(VexArchInfo *vai) + #elif defined(VGA_arm) || defined(VGA_ppc32) || \ + defined(VGA_ppc64be) || defined(VGA_ppc64le) || \ + defined(VGA_mips32) || defined(VGA_mips64) || \ +- defined(VGA_arm64) || defined(VGA_nanomips) ++ defined(VGA_arm64) || defined(VGA_nanomips) || \ ++ defined(VGA_sw64) + static Bool + get_cache_info(VexArchInfo *vai) + { +diff --git a/coregrind/m_coredump/coredump-elf.c b/coregrind/m_coredump/coredump-elf.c +index 4a8c29c52..ab24cdbde 100644 +--- a/coregrind/m_coredump/coredump-elf.c ++++ b/coregrind/m_coredump/coredump-elf.c +@@ -246,7 +246,7 @@ static void fill_prstatus(const ThreadState *tst, + const vki_siginfo_t *si) + { + #if defined(VGP_mips32_linux) || defined(VGP_mips64_linux) \ +- || defined(VGP_nanomips_linux) ++ || defined(VGP_nanomips_linux) || defined(VGP_sw64_linux) + vki_elf_greg_t *regs; + #else + struct vki_user_regs_struct *regs; +@@ -281,7 +281,7 @@ static void fill_prstatus(const ThreadState *tst, + /* prs->pr_reg has struct type. Need to take address. */ + regs = (struct vki_user_regs_struct *)&(prs->pr_reg); + #elif defined(VGP_mips32_linux) || defined(VGP_mips64_linux) \ +- || defined(VGP_nanomips_linux) ++ || defined(VGP_nanomips_linux) || defined(VGP_sw64_linux) + regs = (vki_elf_greg_t *)prs->pr_reg; + #else + regs = (struct vki_user_regs_struct *)prs->pr_reg; +@@ -489,6 +489,14 @@ static void fill_prstatus(const ThreadState *tst, + regs[VKI_MIPS32_EF_CP0_STATUS] = arch->vex.guest_CP0_status; + regs[VKI_MIPS32_EF_CP0_EPC] = arch->vex.guest_PC; + # undef DO ++#elif defined(VGP_sw64_linux) ++# define DO(n) regs[n] = arch->vex.guest_r##n ++ DO(1); DO(2); DO(3); DO(4); DO(5); DO(6); DO(7); DO(8); ++ DO(9); DO(10); DO(11); DO(12); DO(13); DO(14); DO(15); DO(16); ++ DO(17); DO(18); DO(19); DO(20); DO(21); DO(22); DO(23); DO(24); ++ DO(25); DO(28); DO(29); DO(30); DO(31); ++ regs[32] = arch->vex.guest_PC; ++# undef DO + #elif defined(VGP_amd64_freebsd) + regs->rflags = LibVEX_GuestAMD64_get_rflags( &arch->vex ); + regs->rsp = arch->vex.guest_RSP; +@@ -654,6 +662,14 @@ static void fill_fpu(const ThreadState *tst, vki_elf_fpregset_t *fpu) + # undef DO + #elif defined(VGP_nanomips_linux) + ++#elif defined(VGP_sw64_linux) ++# define DO(n) (*fpu)[n] = *(const double*)(&arch->vex.guest_f##n) ++ DO(0); DO(1); DO(2); DO(3); DO(4); DO(5); DO(6); DO(7); ++ DO(8); DO(9); DO(10); DO(11); DO(12); DO(13); DO(14); DO(15); ++ DO(16); DO(17); DO(18); DO(19); DO(20); DO(21); DO(22); DO(23); ++ DO(24); DO(25); DO(26); DO(27); DO(28); DO(29); DO(30); DO(31); ++# undef DO ++ + #elif defined(VGP_x86_freebsd) + + #elif defined(VGP_amd64_freebsd) +diff --git a/coregrind/m_debuginfo/d3basics.c b/coregrind/m_debuginfo/d3basics.c +index e9e8944af..51048c122 100644 +--- a/coregrind/m_debuginfo/d3basics.c ++++ b/coregrind/m_debuginfo/d3basics.c +@@ -555,6 +555,9 @@ static Bool get_Dwarf_Reg( /*OUT*/Addr* a, Word regno, const RegSummary* regs ) + # elif defined(VGP_arm64_linux) + if (regno == 31) { *a = regs->sp; return True; } + if (regno == 29) { *a = regs->fp; return True; } ++# elif defined(VGP_sw64_linux) ++ if (regno == 30) { *a = regs->sp; return True; } ++ if (regno == 15) { *a = regs->fp; return True; } + # else + # error "Unknown platform" + # endif +diff --git a/coregrind/m_debuginfo/debuginfo.c b/coregrind/m_debuginfo/debuginfo.c +index 2d2accc99..2edbb72b3 100644 +--- a/coregrind/m_debuginfo/debuginfo.c ++++ b/coregrind/m_debuginfo/debuginfo.c +@@ -1262,7 +1262,8 @@ ULong VG_(di_notify_mmap)( Addr a, Bool allow_SkFileV, Int use_fd ) + is_ro_map = False; + + # if defined(VGA_x86) || defined(VGA_ppc32) || defined(VGA_mips32) \ +- || defined(VGA_mips64) || defined(VGA_nanomips) ++ || defined(VGA_mips64) || defined(VGA_nanomips) || defined(VGA_sw64) ++ /* TODO(Shaohua): SW_NOT_COMPLETE */ + is_rx_map = seg->hasR && seg->hasX; + is_rw_map = seg->hasR && seg->hasW; + # elif defined(VGA_amd64) || defined(VGA_ppc64be) || defined(VGA_ppc64le) \ +@@ -2987,7 +2988,8 @@ UWord evalCfiExpr ( const XArray* exprs, Int ix, + case Creg_S390_FP: return eec->uregs->fp; + case Creg_S390_LR: return eec->uregs->lr; + # elif defined(VGA_mips32) || defined(VGA_mips64) \ +- || defined(VGA_nanomips) ++ || defined(VGA_nanomips) || defined(VGA_sw64) ++ /* TODO(Shaohua): SW_NOT_COMPLETE */ + case Creg_IA_IP: return eec->uregs->pc; + case Creg_IA_SP: return eec->uregs->sp; + case Creg_IA_BP: return eec->uregs->fp; +@@ -3251,7 +3253,9 @@ static Addr compute_cfa ( const D3UnwindRegs* uregs, + case CFIC_IA_BPREL: + cfa = cfsi_m->cfa_off + uregs->fp; + break; +-# elif defined(VGA_mips32) || defined(VGA_mips64) || defined(VGA_nanomips) ++# elif defined(VGA_mips32) || defined(VGA_mips64) \ ++ || defined(VGA_nanomips) || defined(VGA_sw64) ++ /* TODO(Shaohua): SW_NOT_COMPLETE */ + case CFIC_IA_SPREL: + cfa = cfsi_m->cfa_off + uregs->sp; + break; +@@ -3332,7 +3336,9 @@ Addr ML_(get_CFA) ( Addr ip, Addr sp, Addr fp, + return compute_cfa(&uregs, + min_accessible, max_accessible, ce->di, ce->cfsi_m); + } +-#elif defined(VGA_mips32) || defined(VGA_mips64) ++#elif defined(VGA_mips32) || defined(VGA_mips64) \ ++ || defined(VGA_sw64) ++ /* TODO(Shaohua): SW_NOT_COMPLETE */ + { D3UnwindRegs uregs; + uregs.pc = ip; + uregs.sp = sp; +@@ -3409,7 +3415,9 @@ Bool VG_(use_CF_info) ( /*MOD*/D3UnwindRegs* uregsHere, + ipHere = uregsHere->r15; + # elif defined(VGA_s390x) + ipHere = uregsHere->ia; +-# elif defined(VGA_mips32) || defined(VGA_mips64) || defined(VGA_nanomips) ++# elif defined(VGA_mips32) || defined(VGA_mips64) || defined(VGA_nanomips) \ ++ || defined(VGA_sw64) ++ /* TODO(Shaohua): SW_NOT_COMPLETE */ + ipHere = uregsHere->pc; + # elif defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le) + # elif defined(VGP_arm64_linux) +@@ -3549,7 +3557,9 @@ Bool VG_(use_CF_info) ( /*MOD*/D3UnwindRegs* uregsHere, + COMPUTE(uregsPrev.f5, uregsHere->f5, cfsi_m->f5_how, cfsi_m->f5_off); + COMPUTE(uregsPrev.f6, uregsHere->f6, cfsi_m->f6_how, cfsi_m->f6_off); + COMPUTE(uregsPrev.f7, uregsHere->f7, cfsi_m->f7_how, cfsi_m->f7_off); +-# elif defined(VGA_mips32) || defined(VGA_mips64) || defined(VGA_nanomips) ++# elif defined(VGA_mips32) || defined(VGA_mips64) || defined(VGA_nanomips) \ ++ || defined(VGA_sw64) ++ /* TODO(Shaohua): SW_NOT_COMPLETE */ + COMPUTE(uregsPrev.pc, uregsHere->pc, cfsi_m->ra_how, cfsi_m->ra_off); + COMPUTE(uregsPrev.sp, uregsHere->sp, cfsi_m->sp_how, cfsi_m->sp_off); + COMPUTE(uregsPrev.fp, uregsHere->fp, cfsi_m->fp_how, cfsi_m->fp_off); +@@ -4824,6 +4834,16 @@ SizeT VG_(DebugInfo_get_bss_size)(const DebugInfo* di) + return di->bss_present ? di->bss_size : 0; + } + ++Addr VG_(DebugInfo_get_sbss_avma)(const DebugInfo* di) ++{ ++ return di->sbss_present ? di->sbss_avma : 0; ++} ++ ++SizeT VG_(DebugInfo_get_sbss_size)(const DebugInfo* di) ++{ ++ return di->sbss_present ? di->sbss_size : 0; ++} ++ + Addr VG_(DebugInfo_get_plt_avma)(const DebugInfo* di) + { + return di->plt_present ? di->plt_avma : 0; +diff --git a/coregrind/m_debuginfo/priv_storage.h b/coregrind/m_debuginfo/priv_storage.h +index a4b90d36b..a88b99940 100644 +--- a/coregrind/m_debuginfo/priv_storage.h ++++ b/coregrind/m_debuginfo/priv_storage.h +@@ -354,7 +354,8 @@ typedef + Int f7_off; + } + DiCfSI_m; +-#elif defined(VGA_mips32) || defined(VGA_mips64) || defined(VGA_nanomips) ++#elif defined(VGA_mips32) || defined(VGA_mips64) || defined(VGA_nanomips) \ ++ || defined(VGA_sw64) + typedef + struct { + UChar cfa_how; /* a CFIC_ value */ +diff --git a/coregrind/m_debuginfo/readdwarf.c b/coregrind/m_debuginfo/readdwarf.c +index 79d6764ea..784c79be8 100644 +--- a/coregrind/m_debuginfo/readdwarf.c ++++ b/coregrind/m_debuginfo/readdwarf.c +@@ -2066,6 +2066,10 @@ void ML_(read_debuginfo_dwarf1) ( + # define FP_REG 30 + # define SP_REG 29 + # define RA_REG_DEFAULT 31 ++#elif defined(VGP_sw64_linux) ++# define FP_REG 15 ++# define SP_REG 30 ++# define RA_REG_DEFAULT 26 + #else + # error "Unknown platform" + #endif +@@ -2076,7 +2080,8 @@ void ML_(read_debuginfo_dwarf1) ( + might exist, for Neon/VFP-v3. */ + #if defined(VGP_ppc32_linux) || defined(VGP_ppc64be_linux) \ + || defined(VGP_ppc64le_linux) || defined(VGP_mips32_linux) \ +- || defined(VGP_nanomips_linux) || defined(VGP_mips64_linux) ++ || defined(VGP_nanomips_linux) || defined(VGP_mips64_linux) \ ++ || defined(VGP_sw64_linux) + # define N_CFI_REGS 72 + #elif defined(VGP_arm_linux) + # define N_CFI_REGS 320 +@@ -2392,7 +2397,8 @@ static Bool summarise_context(/*OUT*/Addr* base, + if (ctxs->cfa_is_regoff && ctxs->cfa_reg == SP_REG) { + si_m->cfa_off = ctxs->cfa_off; + # if defined(VGA_x86) || defined(VGA_amd64) || defined(VGA_s390x) \ +- || defined(VGA_mips32) || defined(VGA_nanomips) || defined(VGA_mips64) ++ || defined(VGA_mips32) || defined(VGA_nanomips) \ ++ || defined(VGA_mips64) || defined(VGA_sw64) + si_m->cfa_how = CFIC_IA_SPREL; + # elif defined(VGA_arm) + si_m->cfa_how = CFIC_ARM_R13REL; +@@ -2406,7 +2412,8 @@ static Bool summarise_context(/*OUT*/Addr* base, + if (ctxs->cfa_is_regoff && ctxs->cfa_reg == FP_REG) { + si_m->cfa_off = ctxs->cfa_off; + # if defined(VGA_x86) || defined(VGA_amd64) || defined(VGA_s390x) \ +- || defined(VGA_mips32) || defined(VGA_nanomips) || defined(VGA_mips64) ++ || defined(VGA_mips32) || defined(VGA_nanomips) \ ++ || defined(VGA_mips64) || defined(VGA_sw64) + si_m->cfa_how = CFIC_IA_BPREL; + # elif defined(VGA_arm) + si_m->cfa_how = CFIC_ARM_R12REL; +@@ -2741,7 +2748,9 @@ static Bool summarise_context(/*OUT*/Addr* base, + + return True; + +-# elif defined(VGA_mips32) || defined(VGA_mips64) || defined(VGA_nanomips) ++# elif defined(VGA_mips32) || defined(VGA_mips64) || defined(VGA_nanomips) \ ++ || defined(VGA_sw64) ++ /* TODO(Shaohua): SW_NOT_COMPLETE */ + + /* --- entire tail of this fn specialised for mips --- */ + +@@ -2869,7 +2878,8 @@ static Int copy_convert_CfiExpr_tree ( XArray* dstxa, + if (dwreg == srcuc->ra_reg) + return ML_(CfiExpr_CfiReg)( dstxa, Creg_S390_IA ); + # elif defined(VGA_mips32) || defined(VGA_mips64) \ +- || defined(VGA_nanomips) ++ || defined(VGA_nanomips) || defined(VGA_sw64) ++ /* TODO(Shaohua): SW_NOT_COMPLETE */ + if (dwreg == SP_REG) + return ML_(CfiExpr_CfiReg)( dstxa, Creg_IA_SP ); + if (dwreg == FP_REG) +diff --git a/coregrind/m_debuginfo/readelf.c b/coregrind/m_debuginfo/readelf.c +index ce7b7998d..ee310bc82 100644 +--- a/coregrind/m_debuginfo/readelf.c ++++ b/coregrind/m_debuginfo/readelf.c +@@ -1780,7 +1780,8 @@ static HChar* readlink_path (const HChar *path) + + while (tries > 0) { + SysRes res; +-#if defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) ++#if defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) \ ++ || defined(VGP_sw64_linux) + res = VG_(do_syscall4)(__NR_readlinkat, VKI_AT_FDCWD, + (UWord)path, (UWord)buf, bufsiz); + #elif defined(VGO_linux) || defined(VGO_darwin) || defined(VGO_freebsd) +@@ -2653,6 +2654,7 @@ Bool ML_(read_elf_debug_info) ( struct _DebugInfo* di ) + || defined(VGP_arm_linux) || defined (VGP_s390x_linux) \ + || defined(VGP_mips32_linux) || defined(VGP_mips64_linux) \ + || defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) \ ++ || defined(VGP_sw64_linux) \ + || defined(VGP_x86_solaris) || defined(VGP_amd64_solaris) \ + || defined(VGP_x86_freebsd) || defined(VGP_amd64_freebsd) + /* Accept .plt where mapped as rx (code) */ +diff --git a/coregrind/m_debuginfo/storage.c b/coregrind/m_debuginfo/storage.c +index c3fa62e96..68fa2eed4 100644 +--- a/coregrind/m_debuginfo/storage.c ++++ b/coregrind/m_debuginfo/storage.c +@@ -248,7 +248,8 @@ void ML_(ppDiCfSI) ( const XArray* /* of CfiExpr */ exprs, + SHOW_HOW(si_m->f6_how, si_m->f6_off); + VG_(printf)(" F7="); + SHOW_HOW(si_m->f7_how, si_m->f7_off); +-# elif defined(VGA_mips32) || defined(VGA_mips64) || defined(VGA_nanomips) ++# elif defined(VGA_mips32) || defined(VGA_mips64) || defined(VGA_nanomips) \ ++ || defined(VGA_sw64) + VG_(printf)(" SP="); + SHOW_HOW(si_m->sp_how, si_m->sp_off); + VG_(printf)(" FP="); +diff --git a/coregrind/m_debuglog.c b/coregrind/m_debuglog.c +index 355c3caf5..d4c2542db 100644 +--- a/coregrind/m_debuglog.c ++++ b/coregrind/m_debuglog.c +@@ -601,6 +601,36 @@ static UInt local_sys_getpid ( void ) + return a0; + } + ++#elif defined(VGP_sw64_linux) ++ ++static UInt local_sys_write_stderr ( const HChar* buf, Int n ) ++{ ++ register RegWord v0 asm("$0") = __NR_write; ++ register RegWord a0 asm("$16") = 2; //stderr ++ register RegWord a1 asm("$17") = (RegWord)(Addr)buf; ++ register RegWord a2 asm("$18") = n; ++ ++ __asm__ volatile ( ++ "sys_call 0x83\n\t" //0x83 HMC_callsys in include/asm/hmcall.h ++ : "+r"(v0) ++ : "r" (v0), "r"(a0), "r"(a1), "r"(a2) ++ ); ++ if((UInt)v0 < 0) ++ return (UInt)-1; ++ return (UInt)v0; ++} ++ ++static UInt local_sys_getpid ( void ) ++{ ++ register RegWord v0 asm("$0") = __NR_getpid; ++ __asm__ volatile ( ++ "sys_call 0x83\n\t" ++ : "=r" (v0) ++ : "r" (v0) ++ ); ++ return (UInt)v0; ++} ++ + #elif defined(VGP_x86_solaris) + static UInt local_sys_write_stderr ( const HChar* buf, Int n ) + { +diff --git a/coregrind/m_dispatch/dispatch-sw64-linux.S b/coregrind/m_dispatch/dispatch-sw64-linux.S +new file mode 100644 +index 000000000..12ad4c4fc +--- /dev/null ++++ b/coregrind/m_dispatch/dispatch-sw64-linux.S +@@ -0,0 +1,314 @@ ++/*--------------------------------------------------------------------*/ ++/*--- The core dispatch loop, for jumping to a code address. ---*/ ++/*--- dispatch-sw64-linux.S ---*/ ++/*--------------------------------------------------------------------*/ ++ ++/* ++ This file is part of Valgrind, a dynamic binary instrumentation ++ framework. ++ ++ Copyright (C) 2000-2017 RT-RK ++ ++ This program is free software; you can redistribute it and/or ++ modify it under the terms of the GNU General Public License as ++ published by the Free Software Foundation; either version 2 of the ++ License, or (at your option) any later version. ++ ++ This program is distributed in the hope that it will be useful, but ++ WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with this program; if not, see . ++ ++ The GNU General Public License is contained in the file COPYING. ++*/ ++ ++#include "pub_core_basics_asm.h" ++ ++#if defined(VGP_sw64_linux) ++ ++#include "pub_core_dispatch_asm.h" ++#include "pub_core_transtab_asm.h" ++#include "libvex_guest_offsets.h" /* for OFFSET_SW_PC */ ++ ++#define GUEST_STATE_REG $15 ++ ++ ++/*------------------------------------------------------------*/ ++/*--- ---*/ ++/*--- The dispatch loop. VG_(disp_run_translations) is ---*/ ++/*--- used to run all translations, ---*/ ++/*--- including no-redir ones. ---*/ ++/*--- ---*/ ++/*------------------------------------------------------------*/ ++ ++/*----------------------------------------------------*/ ++/*--- Entry and preamble (set everything up) ---*/ ++/*----------------------------------------------------*/ ++ ++/* signature: ++void VG_(disp_run_translations)( UWord* two_words, ++ void* guest_state, ++ Addr host_addr ); ++*/ ++ ++.text ++.globl VG_(disp_run_translations) ++.ent VG_(disp_run_translations) ++VG_(disp_run_translations): ++ .frame $30, 176, $26, 0 ++ .cfi_startproc ++ ++ /* a0 ($16) holds two_words */ ++ /* a1 ($17) holds guest_state */ ++ /* a2 ($18) holds host_addr */ ++ ++ /* New stack frame. Stack must remain 16 aligned (at least) */ ++ subl $30, 176, $30 ++ .cfi_def_cfa_offset 176 ++ ++ /* Save ra */ ++ stl $26, 72($30) ++ .cfi_rel_offset 26, 72 ++ ++ /* ... and s0 - s5 */ ++ stl $9, 80($30) ++ stl $10, 88($30) ++ stl $11, 96($30) ++ stl $12, 104($30) ++ stl $13, 112($30) ++ stl $14, 120($30) ++ ++ /* ... and gp, fp */ ++ stl $29, 128($30) ++ stl $15, 136($30) ++ ++ /* Save a0 ($16) on stack. In postamble it will be restored such that the ++ return values can be written */ ++ stl $16, 144($30) ++ ++ /* Load address of guest state into guest state register */ ++ mov $17, GUEST_STATE_REG ++ ++ /* prefetch guest state into cache, may improve performance */ ++ fillde 0($17) ++ fillde 128($17) ++ ++ /* and jump into the code cache. Chained translations in ++ the code cache run, until for whatever reason, they can't ++ continue. When that happens, the translation in question ++ will jump (or call) to one of the continuation points ++ VG_(cp_...) below. */ ++ jmp $26, ($18), 0 ++ /*NOTREACHED*/ ++/*----------------------------------------------------*/ ++/*--- Postamble and exit. ---*/ ++/*----------------------------------------------------*/ ++ ++postamble: ++ /* Restore $16 from stack; holds address of two_words */ ++ ldl $16, 144($30) ++ ++ /* Save return value to two_words[] */ ++ stl $0, 0($16) /* VG_TRC_* */ ++ stl $1, 8($16) /* patching address for VG_TRC_CHAIN_* */ ++ ++ /* Restore callee-saved registers... */ ++ ++ /* Restore ra */ ++ ldl $26, 72($30) ++ .cfi_restore 26 ++ ++ /* ... and s0 - s5 */ ++ ldl $9, 80($30) ++ ldl $10, 88($30) ++ ldl $11, 96($30) ++ ldl $12, 104($30) ++ ldl $13, 112($30) ++ ldl $14, 120($30) ++ ++ /* ... and gp, fp */ ++ ldl $29, 128($30) ++ ldl $15, 136($30) ++ ++ /* ... and sp */ ++ addl $30, 176, $30 ++ .cfi_def_cfa_offset 0 ++ ++ ret $31, ($26) ++ nop ++.cfi_endproc ++.end VG_(disp_run_translations) ++ ++/*----------------------------------------------------*/ ++/*--- Continuation points ---*/ ++/*----------------------------------------------------*/ ++ ++/* ------ Chain me to slow entry point ------ */ ++.global VG_(disp_cp_chain_me_to_slowEP) ++VG_(disp_cp_chain_me_to_slowEP): ++ ldi $0, VG_TRC_CHAIN_ME_TO_SLOW_EP ++ ++ /* set $1 to patching address ++ <=== patching address start here ++ ldi r2, disp_cp_chain_me_to_slowEP # 20 bytes ++ jmp r1, (r2) # 4 bytes ++ <=== r1 set to here ++ so subtract 24 */ ++ subl $1, 24, $1 ++ br $31, postamble ++ ++/* ------ Chain me to fast entry point ------ */ ++.global VG_(disp_cp_chain_me_to_fastEP) ++VG_(disp_cp_chain_me_to_fastEP): ++ ldi $0, VG_TRC_CHAIN_ME_TO_FAST_EP ++ ++ /* set $1 to patching address ++ <=== patching address start here ++ ldi r2, disp_cp_chain_me_to_fastEP # 20 bytes ++ jmp r1, (r2) # 4 bytes ++ <=== r1 set to here ++ so subtract 24 */ ++ subl $1, 24, $1 ++ br $31, postamble ++ ++/* ------ Indirect but boring jump ------ */ ++.global VG_(disp_cp_xindir) ++VG_(disp_cp_xindir): ++ ++ /* where are we going */ ++ ldl $3, OFFSET_sw64_PC(GUEST_STATE_REG) //guest_state to $3 ++ ++ /* add aspacemgr_start */ ++ // ldi $8, 0x4000000($31) /* linux: aspacemgr_start*/ ++ // addl $3, $8, $3 ++ ++ ++ /* stats only */ ++ ldw $8, VG_(stats__n_xIndirs_32) ++ addw $8, 1, $8 ++ stw $8, VG_(stats__n_xIndirs_32) ++ ++ // Compute r9 = VG_TT_FAST_HASH(guest) ++ srl $3, 2, $9 // g2 = guest >> 2 ++ srl $3, (VG_TT_FAST_BITS + 2), $8 // (g2 >> VG_TT_FAST_BITS) ++ xor $9, $8, $9 // (g2 >> VG_TT_FAST_BITS) ^ g2 ++ ldi $8, VG_TT_FAST_MASK ++ and $9, $8, $9 // setNo ++ ++ // Compute r9 = &VG_(tt_fast)[r9] ++ ldi $8, VG_(tt_fast) ++ sll $9, VG_FAST_CACHE_SET_BITS, $9 ++ addw $9, $8, $9 ++ ++ // LIVE: GUEST_STATE_REG, r3 (guest addr), r9 (cache set) ++ // try way 0 ++ ldl $7, FCS_g0($9) // .guest0 ++ ldl $8, FCS_h0($9) // .host0 ++ cmpeq $7, $3, $1 // cmp against .guest0 ++ beq $1, 1f ++ jmp ($8), 0 // hit at way 0, goto .host0 ++ /*NOTREACHED*/ ++ .long 0x0 ++ ++1: // try way 1 ++ ldl $7, FCS_g1($9) ++ cmpeq $7, $3, $1 // cmp against .guest1 ++ beq $1, 2f ++ // hit at way 1; swap upwards ++ ldl $4, FCS_g0($9) // $11 = old .guest0 ++ ldl $5, FCS_h0($9) // $12 = old .host0 ++ ldl $6, FCS_h1($9) // $13 = old .host1 ++ stl $3, FCS_g0($9) // new .guest0 = guest ++ stl $6, FCS_h0($9) // new .host0 = old .host1 ++ stl $4, FCS_g1($9) // new .guest1 = old .guest0 ++ stl $5, FCS_h1($9) // new .host1 = old .host0 ++ // stats only ++ ldw $8, VG_(stats__n_xIndir_hits1_32) ++ addw $8, 1, $8 ++ stw $8, VG_(stats__n_xIndir_hits1_32) ++ // goto old .host1 a.k.a. new .host0 ++ jmp ($6), 0 ++ /*NOTREACHED*/ ++ .long 0x0 ++ ++2: // try way 2 ++ ldl $7, FCS_g2($9) ++ cmpeq $7, $3, $1 // cmp against .guest2 ++ beq $1, 3f ++ // hit at way 2; swap upwards ++ ldl $4, FCS_g1($9) ++ ldl $5, FCS_h1($9) ++ ldl $6, FCS_h2($9) ++ stl $3, FCS_g1($9) ++ stl $6, FCS_h1($9) ++ stl $4, FCS_g2($9) ++ stl $5, FCS_h2($9) ++ // stats only ++ ldw $8, VG_(stats__n_xIndir_hits2_32) ++ addw $8, 1, $8 ++ stw $8, VG_(stats__n_xIndir_hits2_32) ++ // goto old .host2 a.k.a. new .host1 ++ jmp ($6), 0 ++ /*NOTREACHED*/ ++ .long 0x0 ++ ++3: // try way 3 ++ ldl $7, FCS_g2($9) ++ cmpeq $7, $3, $1 // cmp against .guest3 ++ beq $1, 4f ++ // hit at way 3; swap upwards ++ ldl $4, FCS_g2($9) ++ ldl $5, FCS_h2($9) ++ ldl $6, FCS_h3($9) ++ stl $3, FCS_g2($9) ++ stl $6, FCS_h2($9) ++ stl $4, FCS_g3($9) ++ stl $5, FCS_h3($9) ++ // stats only ++ ldw $8, VG_(stats__n_xIndir_hits3_32) ++ addw $8, 1, $8 ++ stw $8, VG_(stats__n_xIndir_hits3_32) ++ // goto old .host3 a.k.a. new .host2 ++ jmp ($6), 0 ++ /*NOTREACHED*/ ++ .long 0x0 ++ ++4: // fast lookup failed: ++ /* stats only */ ++ ldw $8, VG_(stats__n_xIndir_misses_32) ++ addw $8, 1, $8 ++ stw $8, VG_(stats__n_xIndir_misses_32) ++ ++ ldi $0, VG_TRC_INNER_FASTMISS ++ ldi $1, 0 ++ br $31, postamble ++ /*NOTREACHED*/ ++ .long 0x0 ++ ++/* ------ Assisted jump ------ */ ++.global VG_(disp_cp_xassisted) ++VG_(disp_cp_xassisted): ++ mov GUEST_STATE_REG, $0 ++ ldi $1, 0 ++ br $31, postamble ++ ++/* ------ Event check failed ------ */ ++.global VG_(disp_cp_evcheck_fail) ++VG_(disp_cp_evcheck_fail): ++ ldi $0, VG_TRC_INNER_COUNTERZERO ++ ldi $1, 0 ++ br $31, postamble ++ ++.size VG_(disp_run_translations), .-VG_(disp_run_translations) ++ ++#endif // defined(VGP_sw64_linux) ++ ++/* Let the linker know we don't need an executable stack */ ++MARK_STACK_NO_EXEC ++ ++/*--------------------------------------------------------------------*/ ++/*--- end ---*/ ++/*--------------------------------------------------------------------*/ +diff --git a/coregrind/m_gdbserver/target.c b/coregrind/m_gdbserver/target.c +index 490276b6c..461b491f3 100644 +--- a/coregrind/m_gdbserver/target.c ++++ b/coregrind/m_gdbserver/target.c +@@ -867,6 +867,8 @@ void valgrind_initialize_target(void) + mips64_init_architecture(&the_low_target); + #elif defined(VGA_nanomips) + nanomips_init_architecture(&the_low_target); ++#elif defined(VGA_sw64) ++ sw64_init_architecture(&the_low_target); + #else + #error "architecture missing in target.c valgrind_initialize_target" + #endif +diff --git a/coregrind/m_gdbserver/valgrind-low-sw64.c b/coregrind/m_gdbserver/valgrind-low-sw64.c +new file mode 100644 +index 000000000..0c0bf4e7d +--- /dev/null ++++ b/coregrind/m_gdbserver/valgrind-low-sw64.c +@@ -0,0 +1,256 @@ ++/* Low level interface to valgrind, for the remote server for GDB integrated ++ in valgrind. ++ Copyright (C) 2011 ++ Free Software Foundation, Inc. ++ ++ This file is part of VALGRIND. ++ It has been inspired from a file from gdbserver in gdb 6.6. ++ ++ This program is free software; you can redistribute it and/or modify ++ it under the terms of the GNU General Public License as published by ++ the Free Software Foundation; either version 2 of the License, or ++ (at your option) any later version. ++ ++ This program is distributed in the hope that it will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ GNU General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with this program; if not, write to the Free Software ++ Foundation, Inc., 51 Franklin Street, Fifth Floor, ++ Boston, MA 02110-1301, USA. */ ++ ++#include "server.h" ++#include "target.h" ++#include "regdef.h" ++#include "regcache.h" ++ ++#include "pub_core_machine.h" ++#include "pub_core_debuginfo.h" ++#include "pub_core_threadstate.h" ++#include "pub_core_transtab.h" ++#include "pub_core_gdbserver.h" ++ ++#include "valgrind_low.h" ++ ++#include "libvex_guest_sw64.h" ++ ++static struct reg regs[] = { ++ { "r0", 0, 64 }, ++ { "r1", 64, 64 }, ++ { "r2", 128, 64 }, ++ { "r3", 192, 64 }, ++ { "r4", 256, 64 }, ++ { "r5", 320, 64 }, ++ { "r6", 384, 64 }, ++ { "r7", 448, 64 }, ++ { "r8", 512, 64 }, ++ { "r9", 576, 64 }, ++ { "r10", 640, 64 }, ++ { "r11", 704, 64 }, ++ { "r12", 768, 64 }, ++ { "r13", 832, 64 }, ++ { "r14", 896, 64 }, ++ { "r15", 960, 64 }, ++ { "r16", 1024, 64 }, ++ { "r17", 1088, 64 }, ++ { "r18", 1152, 64 }, ++ { "r19", 1216, 64 }, ++ { "r20", 1280, 64 }, ++ { "r21", 1344, 64 }, ++ { "r22", 1408, 64 }, ++ { "r23", 1472, 64 }, ++ { "r24", 1536, 64 }, ++ { "r25", 1600, 64 }, ++ { "r26", 1664, 64 }, ++ { "r27", 1728, 64 }, ++ { "r28", 1792, 64 }, ++ { "r29", 1856, 64 }, ++ { "r30", 1920, 64 }, ++ { "r31", 1984, 64 }, ++ ++ { "f0", 2048, 64 }, ++ { "f1", 2112, 64 }, ++ { "f2", 2176, 64 }, ++ { "f3", 2240, 64 }, ++ { "f4", 2304, 64 }, ++ { "f5", 2368, 64 }, ++ { "f6", 2432, 64 }, ++ { "f7", 2496, 64 }, ++ { "f8", 2560, 64 }, ++ { "f9", 2624, 64 }, ++ { "f10", 2688, 64 }, ++ { "f11", 2752, 64 }, ++ { "f12", 2816, 64 }, ++ { "f13", 2880, 64 }, ++ { "f14", 2944, 64 }, ++ { "f15", 3008, 64 }, ++ { "f16", 3072, 64 }, ++ { "f17", 3136, 64 }, ++ { "f18", 3200, 64 }, ++ { "f19", 3264, 64 }, ++ { "f20", 3328, 64 }, ++ { "f21", 3392, 64 }, ++ { "f22", 3456, 64 }, ++ { "f23", 3520, 64 }, ++ { "f24", 3584, 64 }, ++ { "f25", 3648, 64 }, ++ { "f26", 3712, 64 }, ++ { "f27", 3776, 64 }, ++ { "f28", 3840, 64 }, ++ { "f29", 3904, 64 }, ++ { "f30", 3968, 64 }, ++ { "fpcr", 4032, 64 }, ++ ++ { "pc", 4096, 64 }, ++ ++ { "", 4160, 64 }, ++ { "unique", 4224, 64 }, ++}; ++ ++static const char *expedite_regs[] = { "r15", "r30", "pc", 0 }; /* fp, sp, pc */ ++ ++#define num_regs (sizeof (regs) / sizeof (regs[0])) ++ ++static ++CORE_ADDR get_pc (void) ++{ ++ unsigned long pc; ++ ++ collect_register_by_name ("pc", &pc); ++ ++ dlog(1, "stop pc is %p\n", (void *) pc); ++ return pc; ++} ++ ++static ++void set_pc (CORE_ADDR newpc) ++{ ++ Bool mod; ++ supply_register_by_name ("pc", &newpc ); ++ if (mod) ++ dlog(1, "set pc to %p\n", C2v (newpc)); ++ else ++ dlog(1, "set pc not changed %p\n", C2v (newpc)); ++} ++ ++/* store registers in the guest state (gdbserver_to_valgrind) ++ or fetch register from the guest state (valgrind_to_gdbserver). */ ++static ++void transfer_register (ThreadId tid, int abs_regno, void * buf, ++ transfer_direction dir, int size, Bool *mod) ++{ ++ ThreadState* tst = VG_(get_ThreadState)(tid); ++ int set = abs_regno / num_regs; ++ int regno = abs_regno % num_regs; ++ *mod = False; ++ ++ VexGuestSW64State* sw = (VexGuestSW64State*) get_arch (set, tst); ++ ++ switch (regno) { ++ case 0: VG_(transfer) (&sw->guest_r0, buf, dir, size, mod); break; /* regnum = 0 */ ++ case 1: VG_(transfer) (&sw->guest_r1, buf, dir, size, mod); break; ++ case 2: VG_(transfer) (&sw->guest_r2, buf, dir, size, mod); break; ++ case 3: VG_(transfer) (&sw->guest_r3, buf, dir, size, mod); break; ++ case 4: VG_(transfer) (&sw->guest_r4, buf, dir, size, mod); break; ++ case 5: VG_(transfer) (&sw->guest_r5, buf, dir, size, mod); break; ++ case 6: VG_(transfer) (&sw->guest_r6, buf, dir, size, mod); break; ++ case 7: VG_(transfer) (&sw->guest_r7, buf, dir, size, mod); break; ++ case 8: VG_(transfer) (&sw->guest_r8, buf, dir, size, mod); break; ++ case 9: VG_(transfer) (&sw->guest_r9, buf, dir, size, mod); break; ++ case 10: VG_(transfer) (&sw->guest_r10, buf, dir, size, mod); break; ++ case 11: VG_(transfer) (&sw->guest_r11, buf, dir, size, mod); break; ++ case 12: VG_(transfer) (&sw->guest_r12, buf, dir, size, mod); break; ++ case 13: VG_(transfer) (&sw->guest_r13, buf, dir, size, mod); break; ++ case 14: VG_(transfer) (&sw->guest_r14, buf, dir, size, mod); break; ++ case 15: VG_(transfer) (&sw->guest_r15, buf, dir, size, mod); break; ++ case 16: VG_(transfer) (&sw->guest_r16, buf, dir, size, mod); break; ++ case 17: VG_(transfer) (&sw->guest_r17, buf, dir, size, mod); break; ++ case 18: VG_(transfer) (&sw->guest_r18, buf, dir, size, mod); break; ++ case 19: VG_(transfer) (&sw->guest_r19, buf, dir, size, mod); break; ++ case 20: VG_(transfer) (&sw->guest_r20, buf, dir, size, mod); break; ++ case 21: VG_(transfer) (&sw->guest_r21, buf, dir, size, mod); break; ++ case 22: VG_(transfer) (&sw->guest_r22, buf, dir, size, mod); break; ++ case 23: VG_(transfer) (&sw->guest_r23, buf, dir, size, mod); break; ++ case 24: VG_(transfer) (&sw->guest_r24, buf, dir, size, mod); break; ++ case 25: VG_(transfer) (&sw->guest_r25, buf, dir, size, mod); break; ++ case 26: VG_(transfer) (&sw->guest_r26, buf, dir, size, mod); break; ++ case 27: VG_(transfer) (&sw->guest_r27, buf, dir, size, mod); break; ++ case 28: VG_(transfer) (&sw->guest_r28, buf, dir, size, mod); break; ++ case 29: VG_(transfer) (&sw->guest_r29, buf, dir, size, mod); break; ++ case 30: VG_(transfer) (&sw->guest_r30, buf, dir, size, mod); break; ++ case 31: VG_(transfer) (&sw->guest_r31, buf, dir, size, mod); break; ++ ++ case 32: VG_(transfer) (&sw->guest_f0, buf, dir, size, mod); break; /* regnum = 32 */ ++ case 33: VG_(transfer) (&sw->guest_f1, buf, dir, size, mod); break; ++ case 34: VG_(transfer) (&sw->guest_f2, buf, dir, size, mod); break; ++ case 35: VG_(transfer) (&sw->guest_f3, buf, dir, size, mod); break; ++ case 36: VG_(transfer) (&sw->guest_f4, buf, dir, size, mod); break; ++ case 37: VG_(transfer) (&sw->guest_f5, buf, dir, size, mod); break; ++ case 38: VG_(transfer) (&sw->guest_f6, buf, dir, size, mod); break; ++ case 39: VG_(transfer) (&sw->guest_f7, buf, dir, size, mod); break; ++ case 40: VG_(transfer) (&sw->guest_f8, buf, dir, size, mod); break; ++ case 41: VG_(transfer) (&sw->guest_f9, buf, dir, size, mod); break; ++ case 42: VG_(transfer) (&sw->guest_f10, buf, dir, size, mod); break; ++ case 43: VG_(transfer) (&sw->guest_f11, buf, dir, size, mod); break; ++ case 44: VG_(transfer) (&sw->guest_f12, buf, dir, size, mod); break; ++ case 45: VG_(transfer) (&sw->guest_f13, buf, dir, size, mod); break; ++ case 46: VG_(transfer) (&sw->guest_f14, buf, dir, size, mod); break; ++ case 47: VG_(transfer) (&sw->guest_f15, buf, dir, size, mod); break; ++ case 48: VG_(transfer) (&sw->guest_f16, buf, dir, size, mod); break; ++ case 49: VG_(transfer) (&sw->guest_f17, buf, dir, size, mod); break; ++ case 50: VG_(transfer) (&sw->guest_f18, buf, dir, size, mod); break; ++ case 51: VG_(transfer) (&sw->guest_f19, buf, dir, size, mod); break; ++ case 52: VG_(transfer) (&sw->guest_f20, buf, dir, size, mod); break; ++ case 53: VG_(transfer) (&sw->guest_f21, buf, dir, size, mod); break; ++ case 54: VG_(transfer) (&sw->guest_f22, buf, dir, size, mod); break; ++ case 55: VG_(transfer) (&sw->guest_f23, buf, dir, size, mod); break; ++ case 56: VG_(transfer) (&sw->guest_f24, buf, dir, size, mod); break; ++ case 57: VG_(transfer) (&sw->guest_f25, buf, dir, size, mod); break; ++ case 58: VG_(transfer) (&sw->guest_f26, buf, dir, size, mod); break; ++ case 59: VG_(transfer) (&sw->guest_f27, buf, dir, size, mod); break; ++ case 60: VG_(transfer) (&sw->guest_f28, buf, dir, size, mod); break; ++ case 61: VG_(transfer) (&sw->guest_f29, buf, dir, size, mod); break; ++ case 62: VG_(transfer) (&sw->guest_f30, buf, dir, size, mod); break; ++ case 63: VG_(transfer) (&sw->guest_FPCR, buf, dir, size, mod); break; ++ ++ case 64: VG_(transfer) (&sw->guest_PC, buf, dir, size, mod); break; /* regnum = 64 */ ++ ++ case 65: *mod = False; break; /* regnum = 65, no name, don't know what is it */ ++ case 66: VG_(transfer) (&sw->guest_TID, buf, dir, size, mod); break; /* regnum = 66 */ ++ ++ default: VG_(printf)("regno: %d\n", regno); vg_assert(0); ++ } ++} ++ ++static ++const char* target_xml (Bool shadow_mode) ++{ ++ return NULL; ++} ++ ++static CORE_ADDR** target_get_dtv (ThreadState *tst) ++{ ++ VexGuestSW64State* sw64 = (VexGuestSW64State*)&tst->arch.vex; ++ return (CORE_ADDR**)((CORE_ADDR)sw64->guest_TID); ++} ++ ++static struct valgrind_target_ops low_target = { ++ num_regs, ++ regs, ++ 30, //sp = r30, which is register offset 30 in regs ++ transfer_register, ++ get_pc, ++ set_pc, ++ "sw64", ++ target_xml, ++ target_get_dtv ++}; ++ ++void sw64_init_architecture (struct valgrind_target_ops *target) ++{ ++ *target = low_target; ++ set_register_cache (regs, num_regs); ++ gdbserver_expedite_regs = expedite_regs; ++} +diff --git a/coregrind/m_gdbserver/valgrind_low.h b/coregrind/m_gdbserver/valgrind_low.h +index c6c0bb63b..b697b90c9 100644 +--- a/coregrind/m_gdbserver/valgrind_low.h ++++ b/coregrind/m_gdbserver/valgrind_low.h +@@ -108,5 +108,6 @@ extern void s390x_init_architecture (struct valgrind_target_ops *target); + extern void mips32_init_architecture (struct valgrind_target_ops *target); + extern void mips64_init_architecture (struct valgrind_target_ops *target); + extern void nanomips_init_architecture (struct valgrind_target_ops *target); ++extern void sw64_init_architecture (struct valgrind_target_ops *target); + + #endif +diff --git a/coregrind/m_initimg/initimg-linux.c b/coregrind/m_initimg/initimg-linux.c +index 7a7d45335..b3693ed57 100644 +--- a/coregrind/m_initimg/initimg-linux.c ++++ b/coregrind/m_initimg/initimg-linux.c +@@ -547,9 +547,9 @@ Addr setup_client_stack( void* init_sp, + vg_assert(VG_IS_PAGE_ALIGNED(resvn_start)); + vg_assert(resvn_start == clstack_end + 1 - clstack_max_size); + +-# ifdef ENABLE_INNER ++#if defined(ENABLE_INNER) || defined(VGP_sw64_linux) + inner_HACK = 1024*1024; // create 1M non-fault-extending stack +-# endif ++#endif + + if (0) + VG_(printf)("%#lx 0x%lx %#lx 0x%lx\n", +@@ -913,7 +913,8 @@ Addr setup_client_stack( void* init_sp, + && !defined(VGP_ppc64le_linux) \ + && !defined(VGP_mips32_linux) && !defined(VGP_mips64_linux) \ + && !defined(VGP_nanomips_linux) \ +- && !defined(VGP_s390x_linux) ++ && !defined(VGP_s390x_linux) \ ++ && !defined(VGP_sw64_linux) + case AT_SYSINFO_EHDR: { + /* Trash this, because we don't reproduce it */ + const NSegment* ehdrseg = VG_(am_find_nsegment)((Addr)auxv->u.a_ptr); +@@ -1173,7 +1174,7 @@ IIFinaliseImageInfo VG_(ii_create_image)( IICreateImageInfo iicii, + starting values. This is handed the IIFinaliseImageInfo created by + VG_(ii_create_image). + */ +-void VG_(ii_finalise_image)( IIFinaliseImageInfo iifii ) ++void VG_(ii_finalise_image)( IIFinaliseImageInfo iifii , IICreateImageInfo iicii ) + { + ThreadArchState* arch = &VG_(threads)[1].arch; + +@@ -1343,6 +1344,22 @@ void VG_(ii_finalise_image)( IIFinaliseImageInfo iifii ) + arch->vex.guest_r29 = iifii.initial_client_SP; + arch->vex.guest_PC = iifii.initial_client_IP; + arch->vex.guest_r31 = iifii.initial_client_SP; ++# elif defined(VGP_sw64_linux) ++ vg_assert(0 == sizeof(VexGuestSW64State) % LibVEX_GUEST_STATE_ALIGN); ++ /* Zero out the initial state, and set up the simulated FPU in a sane way. */ ++ LibVEX_GuestSW64_initialise(&arch->vex); ++ ++ /* Zero out the shadow areas. */ ++ VG_(memset)(&arch->vex_shadow1, 0, sizeof(VexGuestSW64State)); ++ VG_(memset)(&arch->vex_shadow2, 0, sizeof(VexGuestSW64State)); ++ ++ arch->vex.guest_r30 = iifii.initial_client_SP; //sp ++ // sw: the stack growth direction is from high address to lower address ++ // arch->vex.guest_r30 = iicii.clstack_end - 16; ++ // Addr* ptr = (Addr*)(iicii.clstack_end - 16); ++ // *ptr = 1; //not true ++ arch->vex.guest_PC = iifii.initial_client_IP; //pc ++ arch->vex.guest_r26 = iifii.initial_client_SP; //ra + + # else + # error Unknown platform +diff --git a/coregrind/m_libcassert.c b/coregrind/m_libcassert.c +index 35f37f88d..7e6bf017b 100644 +--- a/coregrind/m_libcassert.c ++++ b/coregrind/m_libcassert.c +@@ -264,6 +264,28 @@ + (srP)->misc.MIPS32.r31 = (UInt)ra; \ + (srP)->misc.MIPS32.r28 = (UInt)gp; \ + } ++#elif defined(VGP_sw64_linux) ++# define GET_STARTREGS(srP) \ ++ { ULong pc, sp, fp, ra, gp; \ ++ asm(" br %0, 0f\n" /* restore pc */ \ ++ "0:\n" \ ++ " mov $30, %1\n" /* restore sp */ \ ++ " mov $15, %2\n" /* restore fp */ \ ++ " mov $26, %3\n" /* restore ra */ \ ++ " mov $29, %4\n" /* restore gp */ \ ++ : "=r" (pc), \ ++ "=r" (sp), \ ++ "=r" (fp), \ ++ "=r" (ra), \ ++ "=r" (gp) \ ++ : /* reads none */ \ ++ ); \ ++ (srP)->r_pc = (ULong)pc - 4; \ ++ (srP)->r_sp = (ULong)sp; \ ++ (srP)->misc.SW64.r15 = (ULong)fp; \ ++ (srP)->misc.SW64.r26 = (ULong)ra; \ ++ (srP)->misc.SW64.r29 = (ULong)gp; \ ++ } + #else + # error Unknown platform + #endif +diff --git a/coregrind/m_libcfile.c b/coregrind/m_libcfile.c +index 5d3a349f2..062fbdede 100644 +--- a/coregrind/m_libcfile.c ++++ b/coregrind/m_libcfile.c +@@ -268,6 +268,9 @@ SysRes VG_(mknod) ( const HChar* pathname, Int mode, UWord dev ) + /* ARM64 wants to use __NR_mknodat rather than __NR_mknod. */ + SysRes res = VG_(do_syscall4)(__NR_mknodat, + VKI_AT_FDCWD, (UWord)pathname, mode, dev); ++# elif defined(VGP_sw64_linux) ++ SysRes res = VG_(do_syscall4)(__NR_mknodat, ++ VKI_AT_FDCWD, (UWord)pathname, mode, dev); + # elif defined(VGO_linux) || defined(VGO_darwin) + SysRes res = VG_(do_syscall3)(__NR_mknod, + (UWord)pathname, mode, dev); +@@ -384,7 +387,8 @@ Int VG_(pipe) ( Int fd[2] ) + } else { + return -1; + } +-# elif defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) ++# elif defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) \ ++ || defined(VGP_sw64_linux) + SysRes res = VG_(do_syscall2)(__NR_pipe2, (UWord)fd, 0); + return sr_isError(res) ? -1 : 0; + # elif defined(VGO_linux) +@@ -463,7 +467,27 @@ Off64T VG_(lseek) ( Int fd, Off64T offset, Int whence ) + /* stat/fstat support. It's uggerly. We have impedance-match into a + 'struct vg_stat' in order to have a single structure that callers + can use consistently on all platforms. */ +- ++#if defined(VGP_sw64_linux) ++#define TRANSLATE_TO_vg_stat(_p_vgstat, _p_vkistat) \ ++ do { \ ++ (_p_vgstat)->dev = (ULong)( (_p_vkistat)->st_dev ); \ ++ (_p_vgstat)->ino = (ULong)( (_p_vkistat)->st_ino ); \ ++ (_p_vgstat)->nlink = (ULong)( (_p_vkistat)->st_nlink ); \ ++ (_p_vgstat)->mode = (UInt) ( (_p_vkistat)->st_mode ); \ ++ (_p_vgstat)->uid = (UInt) ( (_p_vkistat)->st_uid ); \ ++ (_p_vgstat)->gid = (UInt) ( (_p_vkistat)->st_gid ); \ ++ (_p_vgstat)->rdev = (ULong)( (_p_vkistat)->st_rdev ); \ ++ (_p_vgstat)->size = (Long) ( (_p_vkistat)->st_size ); \ ++ (_p_vgstat)->blksize = (ULong)( (_p_vkistat)->st_blksize ); \ ++ (_p_vgstat)->blocks = (ULong)( (_p_vkistat)->st_blocks ); \ ++ (_p_vgstat)->atime = (ULong)( (_p_vkistat)->st_atime ); \ ++ (_p_vgstat)->atime_nsec = (ULong)( 0 ); \ ++ (_p_vgstat)->mtime = (ULong)( (_p_vkistat)->st_mtime ); \ ++ (_p_vgstat)->mtime_nsec = (ULong)( 0 ); \ ++ (_p_vgstat)->ctime = (ULong)( (_p_vkistat)->st_ctime ); \ ++ (_p_vgstat)->ctime_nsec = (ULong)( 0 ); \ ++ } while (0) ++#else /* if defined(VGP_sw64_linux) */ + #define TRANSLATE_TO_vg_stat(_p_vgstat, _p_vkistat) \ + do { \ + (_p_vgstat)->dev = (ULong)( (_p_vkistat)->st_dev ); \ +@@ -483,6 +507,7 @@ Off64T VG_(lseek) ( Int fd, Off64T offset, Int whence ) + (_p_vgstat)->ctime = (ULong)( (_p_vkistat)->st_ctime ); \ + (_p_vgstat)->ctime_nsec = (ULong)( (_p_vkistat)->st_ctime_nsec ); \ + } while (0) ++#endif /* if defined(VGP_sw64_linux) */ + + #define TRANSLATE_statx_TO_vg_stat(_p_vgstat, _p_vkistat) \ + do { \ +@@ -731,7 +756,8 @@ SysRes VG_(dup) ( Int oldfd ) + + SysRes VG_(dup2) ( Int oldfd, Int newfd ) + { +-# if defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) ++# if defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) \ ++ || defined(VGP_sw64_linux) + /* We only have dup3, that means we have to mimic dup2. + The only real difference is when oldfd == newfd. + dup3 always returns an error, but dup2 returns only an +@@ -774,7 +800,8 @@ Int VG_(fcntl) ( Int fd, Int cmd, Addr arg ) + + Int VG_(rename) ( const HChar* old_name, const HChar* new_name ) + { +-# if defined(VGO_solaris) || defined(VGP_arm64_linux) ++# if defined(VGO_solaris) || defined(VGP_arm64_linux) \ ++ || defined(VGP_sw64_linux) + SysRes res = VG_(do_syscall4)(__NR_renameat, VKI_AT_FDCWD, (UWord)old_name, + VKI_AT_FDCWD, (UWord)new_name); + # elif defined(VGP_nanomips_linux) +@@ -791,7 +818,8 @@ Int VG_(rename) ( const HChar* old_name, const HChar* new_name ) + + Int VG_(unlink) ( const HChar* file_name ) + { +-# if defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) ++# if defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) \ ++ || defined(VGP_sw64_linux) + SysRes res = VG_(do_syscall2)(__NR_unlinkat, VKI_AT_FDCWD, + (UWord)file_name); + # elif defined(VGO_linux) || defined(VGO_darwin) || defined(VGO_freebsd) +@@ -870,7 +898,8 @@ const HChar *VG_(get_startup_wd) ( void ) + SysRes VG_(poll) (struct vki_pollfd *fds, Int nfds, Int timeout) + { + SysRes res; +-# if defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) ++# if defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) \ ++ || defined(VGP_sw64_linux) + /* ARM64 wants to use __NR_ppoll rather than __NR_poll. */ + struct vki_timespec timeout_ts; + if (timeout >= 0) { +@@ -915,7 +944,8 @@ SSizeT VG_(readlink) (const HChar* path, HChar* buf, SizeT bufsiz) + { + SysRes res; + /* res = readlink( path, buf, bufsiz ); */ +-# if defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) ++# if defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) \ ++ || defined(VGP_sw64_linux) + res = VG_(do_syscall4)(__NR_readlinkat, VKI_AT_FDCWD, + (UWord)path, (UWord)buf, bufsiz); + # elif defined(VGO_linux) || defined(VGO_darwin) || defined(VGO_freebsd) +@@ -994,7 +1024,8 @@ Int VG_(access) ( const HChar* path, Bool irusr, Bool iwusr, Bool ixusr ) + UWord w = (irusr ? VKI_R_OK : 0) + | (iwusr ? VKI_W_OK : 0) + | (ixusr ? VKI_X_OK : 0); +-# if defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) ++# if defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) \ ++ || defined(VGP_sw64_linux) + SysRes res = VG_(do_syscall3)(__NR_faccessat, VKI_AT_FDCWD, (UWord)path, w); + # elif defined(VGO_linux) || defined(VGO_darwin) || defined(VGO_freebsd) + SysRes res = VG_(do_syscall2)(__NR_access, (UWord)path, w); +@@ -1140,7 +1171,8 @@ SysRes VG_(pread) ( Int fd, void* buf, Int count, OffT offset ) + return res; + # elif defined(VGP_amd64_linux) || defined(VGP_s390x_linux) \ + || defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) \ +- || defined(VGP_mips64_linux) || defined(VGP_arm64_linux) ++ || defined(VGP_mips64_linux) || defined(VGP_arm64_linux) \ ++ || defined(VGP_sw64_linux) + res = VG_(do_syscall4)(__NR_pread64, fd, (UWord)buf, count, offset); + return res; + # elif defined(VGP_amd64_freebsd) +@@ -1404,7 +1436,8 @@ Int VG_(socket) ( Int domain, Int type, Int protocol ) + + # elif defined(VGP_amd64_linux) || defined(VGP_arm_linux) \ + || defined(VGP_mips32_linux) || defined(VGP_mips64_linux) \ +- || defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) || defined(VGO_freebsd) ++ || defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) \ ++ || defined(VGP_sw64_linux) || defined(VGO_freebsd) + SysRes res; + res = VG_(do_syscall3)(__NR_socket, domain, type, protocol ); + return sr_isError(res) ? -1 : sr_Res(res); +@@ -1459,7 +1492,8 @@ Int my_connect ( Int sockfd, struct vki_sockaddr_in* serv_addr, Int addrlen ) + + # elif defined(VGP_amd64_linux) || defined(VGP_arm_linux) \ + || defined(VGP_mips32_linux) || defined(VGP_mips64_linux) \ +- || defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) || defined(VGO_freebsd) ++ || defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) \ ++ || defined(VGP_sw64_linux) || defined(VGO_freebsd) + SysRes res; + res = VG_(do_syscall3)(__NR_connect, sockfd, (UWord)serv_addr, addrlen); + return sr_isError(res) ? -1 : sr_Res(res); +@@ -1506,7 +1540,8 @@ Int VG_(write_socket)( Int sd, const void *msg, Int count ) + + # elif defined(VGP_amd64_linux) || defined(VGP_arm_linux) \ + || defined(VGP_mips32_linux) || defined(VGP_mips64_linux) \ +- || defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) || defined(VGO_freebsd) ++ || defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) \ ++ || defined(VGP_sw64_linux) || defined(VGO_freebsd) + SysRes res; + res = VG_(do_syscall6)(__NR_sendto, sd, (UWord)msg, + count, VKI_MSG_NOSIGNAL, 0,0); +@@ -1544,7 +1579,8 @@ Int VG_(getsockname) ( Int sd, struct vki_sockaddr *name, Int *namelen) + # elif defined(VGP_amd64_linux) || defined(VGP_arm_linux) \ + || defined(VGP_mips64_linux) || defined(VGP_arm64_linux) \ + || defined(VGP_nanomips_linux) || defined(VGO_freebsd) \ +- || defined(VGP_mips64_linux) || defined(VGP_arm64_linux) ++ || defined(VGP_mips64_linux) || defined(VGP_arm64_linux) \ ++ || defined(VGP_sw64_linux) + SysRes res; + res = VG_(do_syscall3)( __NR_getsockname, + (UWord)sd, (UWord)name, (UWord)namelen ); +@@ -1583,7 +1619,8 @@ Int VG_(getpeername) ( Int sd, struct vki_sockaddr *name, Int *namelen) + + # elif defined(VGP_amd64_linux) || defined(VGP_arm_linux) \ + || defined(VGP_mips64_linux) || defined(VGP_arm64_linux) \ +- || defined(VGP_nanomips_linux) || defined(VGO_freebsd) ++ || defined(VGP_nanomips_linux) || defined(VGO_freebsd) \ ++ || defined(VGP_sw64_linux) + SysRes res; + res = VG_(do_syscall3)( __NR_getpeername, + (UWord)sd, (UWord)name, (UWord)namelen ); +@@ -1625,7 +1662,7 @@ Int VG_(getsockopt) ( Int sd, Int level, Int optname, void *optval, + # elif defined(VGP_amd64_linux) || defined(VGP_arm_linux) \ + || defined(VGP_mips32_linux) || defined(VGP_mips64_linux) \ + || defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) \ +- || defined(VGO_freebsd) ++ || defined(VGP_sw64_linux) || defined(VGO_freebsd) + SysRes res; + res = VG_(do_syscall5)( __NR_getsockopt, + (UWord)sd, (UWord)level, (UWord)optname, +@@ -1669,7 +1706,8 @@ Int VG_(setsockopt) ( Int sd, Int level, Int optname, void *optval, + + # elif defined(VGP_amd64_linux) || defined(VGP_arm_linux) \ + || defined(VGP_mips32_linux) || defined(VGP_mips64_linux) \ +- || defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) ++ || defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) \ ++ || defined(VGP_sw64_linux) + SysRes res; + res = VG_(do_syscall5)( __NR_setsockopt, + (UWord)sd, (UWord)level, (UWord)optname, +diff --git a/coregrind/m_libcproc.c b/coregrind/m_libcproc.c +index 592d69bf1..adac64c10 100644 +--- a/coregrind/m_libcproc.c ++++ b/coregrind/m_libcproc.c +@@ -698,7 +698,8 @@ Int VG_(gettid)(void) + * the /proc/self link is pointing... + */ + +-# if defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) ++# if defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) \ ++ || defined(VGP_sw64_linux) + res = VG_(do_syscall4)(__NR_readlinkat, VKI_AT_FDCWD, + (UWord)"/proc/self", + (UWord)pid, sizeof(pid)); +@@ -753,7 +754,8 @@ Int VG_(getpid) ( void ) + Int VG_(getpgrp) ( void ) + { + /* ASSUMES SYSCALL ALWAYS SUCCEEDS */ +-# if defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) ++# if defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) \ ++ || defined(VGP_sw64_linux) + return sr_Res( VG_(do_syscall1)(__NR_getpgid, 0) ); + # elif defined(VGO_linux) || defined(VGO_darwin) || defined(VGO_freebsd) + return sr_Res( VG_(do_syscall0)(__NR_getpgrp) ); +@@ -850,7 +852,7 @@ Int VG_(getgroups)( Int size, UInt* list ) + || defined(VGO_darwin) || defined(VGP_s390x_linux) \ + || defined(VGP_mips32_linux) || defined(VGP_arm64_linux) \ + || defined(VGO_solaris) || defined(VGP_nanomips_linux) \ +- || defined(VGO_freebsd) ++ || defined(VGP_sw64_linux) || defined(VGO_freebsd) + SysRes sres; + sres = VG_(do_syscall2)(__NR_getgroups, size, (Addr)list); + if (sr_isError(sres)) +@@ -944,7 +946,8 @@ Int VG_(fork) ( void ) + fds[0] = fds[1] = -1; + } + +-# if defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) ++# if defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) \ ++ || defined(VGP_sw64_linux) + SysRes res; + res = VG_(do_syscall5)(__NR_clone, VKI_SIGCHLD, + (UWord)NULL, (UWord)NULL, (UWord)NULL, (UWord)NULL); +@@ -1422,6 +1425,12 @@ void VG_(invalidate_icache) ( void *ptr, SizeT nbytes ) + + __builtin___clear_cache(ptr, (char*)ptr + nbytes); + ++# elif defined(VGA_sw64) ++ __builtin___clear_cache(ptr, (char*)ptr + nbytes); ++ ++# else ++ VG_(core_panic)( ++ "TODO: impl invalidate_icache for this architecture"); + # endif + } + +diff --git a/coregrind/m_machine.c b/coregrind/m_machine.c +index 052b5d186..6ceae888f 100644 +--- a/coregrind/m_machine.c ++++ b/coregrind/m_machine.c +@@ -152,6 +152,15 @@ void VG_(get_UnwindStartRegs) ( /*OUT*/UnwindStartRegs* regs, + = VG_(threads)[tid].arch.vex.guest_r31; + regs->misc.MIPS64.r28 + = VG_(threads)[tid].arch.vex.guest_r28; ++# elif defined(VGA_sw64) ++ regs->r_pc = VG_(threads)[tid].arch.vex.guest_PC; ++ regs->r_sp = VG_(threads)[tid].arch.vex.guest_r30; ++ regs->misc.SW64.r15 ++ = VG_(threads)[tid].arch.vex.guest_r15; //fp ++ regs->misc.SW64.r26 ++ = VG_(threads)[tid].arch.vex.guest_r26; //ra ++ regs->misc.SW64.r29 ++ = VG_(threads)[tid].arch.vex.guest_r29; //gp + # else + # error "Unknown arch" + # endif +@@ -304,7 +313,8 @@ static void apply_to_GPs_of_tid(ThreadId tid, void (*f)(ThreadId, + (*f)(tid, "r13", vex->guest_r13); + (*f)(tid, "r14", vex->guest_r14); + (*f)(tid, "r15", vex->guest_r15); +-#elif defined(VGA_mips32) || defined(VGA_mips64) || defined(VGP_nanomips_linux) ++#elif defined(VGA_mips32) || defined(VGA_mips64) \ ++ || defined(VGP_nanomips_linux) || defined(VGA_sw64) + (*f)(tid, "r0" , vex->guest_r0 ); + (*f)(tid, "r1" , vex->guest_r1 ); + (*f)(tid, "r2" , vex->guest_r2 ); +@@ -859,6 +869,59 @@ static Bool VG_(parse_cpuinfo)(void) + + #endif /* defined(VGP_arm64_linux) */ + ++#if defined(VGP_sw64_linux) ++static Bool VG_(parse_cpuinfo)(void) ++{ ++ Int n, fh; ++ SysRes fd; ++ SizeT num_bytes, file_buf_size; ++ HChar *file_buf; ++ ++ /* Slurp contents of /proc/cpuinfo into FILE_BUF */ ++ fd = VG_(open)( "/proc/cpuinfo", 0, VKI_S_IRUSR ); ++ if ( sr_isError(fd) ) return False; ++ ++ fh = sr_Res(fd); ++ ++ /* Determine the size of /proc/cpuinfo. ++ Work around broken-ness in /proc file system implementation. ++ fstat returns a zero size for /proc/cpuinfo although it is ++ claimed to be a regular file. */ ++ num_bytes = 0; ++ file_buf_size = 1000; ++ file_buf = VG_(malloc)("cpuinfo", file_buf_size + 1); ++ while (42) { ++ n = VG_(read)(fh, file_buf, file_buf_size); ++ if (n < 0) break; ++ ++ num_bytes += n; ++ if (n < file_buf_size) break; /* reached EOF */ ++ } ++ ++ if (n < 0) num_bytes = 0; /* read error; ignore contents */ ++ ++ if (num_bytes > file_buf_size) { ++ VG_(free)( file_buf ); ++ VG_(lseek)( fh, 0, VKI_SEEK_SET ); ++ file_buf = VG_(malloc)( "cpuinfo", num_bytes + 1 ); ++ n = VG_(read)( fh, file_buf, num_bytes ); ++ if (n < 0) num_bytes = 0; ++ } ++ ++ file_buf[num_bytes] = '\0'; ++ VG_(close)(fh); ++ ++ if (VG_(strstr) (file_buf, "cpu family\t: 8\n") != NULL) { ++ vai.hwcaps |= VEX_SW64_CORE4; ++ } else { ++ vai.hwcaps |= VEX_SW64_CORE3; ++ } ++ ++ VG_(free)(file_buf); ++ return True; ++} ++#endif ++ + Bool VG_(machine_get_hwcaps)( void ) + { + vg_assert(hwcaps_done == False); +@@ -2227,6 +2290,21 @@ Bool VG_(machine_get_hwcaps)( void ) + + return True; + } ++#elif defined(VGA_sw64) ++ { ++ va = VexArchSW64; ++ vai.hwcaps = 0; ++ vai.endness = VexEndnessLE; ++ ++ if (!VG_(parse_cpuinfo)()) ++ return False; ++ ++ VG_(debugLog)(1, "machine", "hwcaps = 0x%x\n", vai.hwcaps); ++ ++ VG_(machine_get_cache_info)(&vai); ++ ++ return True; ++ } + #else + # error "Unknown arch" + #endif +@@ -2367,6 +2445,9 @@ Int VG_(machine_get_size_of_largest_guest_register) ( void ) + # elif defined(VGA_mips64) + return 8; + ++# elif defined(VGA_sw64) ++ return 8; ++ + # else + # error "Unknown arch" + # endif +@@ -2383,7 +2464,7 @@ void* VG_(fnptr_to_fnentry)( void* f ) + || defined(VGP_s390x_linux) || defined(VGP_mips32_linux) \ + || defined(VGP_mips64_linux) || defined(VGP_arm64_linux) \ + || defined(VGP_x86_solaris) || defined(VGP_amd64_solaris) \ +- || defined(VGP_nanomips_linux) ++ || defined(VGP_nanomips_linux) || defined(VGP_sw64_linux) + return f; + # elif defined(VGP_ppc64be_linux) + /* ppc64-linux uses the AIX scheme, in which f is a pointer to a +diff --git a/coregrind/m_main.c b/coregrind/m_main.c +index a857e5afe..80f46d0f2 100644 +--- a/coregrind/m_main.c ++++ b/coregrind/m_main.c +@@ -257,6 +257,10 @@ static void usage_NORETURN ( int need_help ) + " --sanity-level= level of sanity checking to do [1]\n" + " --trace-flags= show generated code? (X = 0|1) [00000000]\n" + " --profile-flags= ditto, but for profiling (X = 0|1) [00000000]\n" ++" --trace-reg= show register value? (X = 0|1) [000]\n" ++" 001 ....... show control registers\n" ++" 010 ....... show interger registers\n" ++" 100 ....... show float-point registers\n" + " --profile-interval= show profile every event checks\n" + " [0, meaning only at the end of the run]\n" + " --trace-notbelow= only show BBs above [999999999]\n" +@@ -269,6 +273,7 @@ static void usage_NORETURN ( int need_help ) + " --debug-dump=syms mimic /usr/bin/readelf --syms\n" + " --debug-dump=line mimic /usr/bin/readelf --debug-dump=line\n" + " --debug-dump=frames mimic /usr/bin/readelf --debug-dump=frames\n" ++" --dump-expansion-ratio=no|yes show instruction expansion ratio? [no]\n" + " --trace-redir=no|yes show redirection details? [no]\n" + " --trace-sched=no|yes show thread scheduler details? [no]\n" + " --profile-heap=no|yes profile Valgrind's own space use\n" +@@ -660,6 +665,8 @@ else if VG_INT_CLOM(cloPD, arg, "--scheduling-quantum", + True) {} + else if VG_XACT_CLOM(cloPD, arg, "--debug-dump=frames", + VG_(clo_debug_dump_frames), True) {} ++ else if VG_BOOL_CLOM(cloPD, arg, "--dump-expansion-ratio", ++ VG_(clo_dump_expansion_ratio)) {} + else if VG_BOOL_CLOM(cloPD, arg, "--trace-redir", VG_(clo_trace_redir)) {} + + else if VG_BOOL_CLOM(cloPD, arg, "--trace-syscalls", VG_(clo_trace_syscalls)) {} +@@ -848,6 +855,22 @@ else if VG_INT_CLOM(cloPD, arg, "--scheduling-quantum", + + else if VG_INT_CLOM (cloPD, arg, "--trace-notabove", VG_(clo_trace_notabove)) {} + ++ else if VG_STR_CLOM (cloPD, arg, "--trace-reg", tmp_str) { ++ Int j; ++ if (3 != VG_(strlen)(tmp_str)) { ++ VG_(fmsg_bad_option)(arg, ++ "--trace-reg argument must have 3 digits\n"); ++ } ++ for (j = 0; j < 3; j++) { ++ if ('0' == tmp_str[j]) { /* do nothing */ } ++ else if ('1' == tmp_str[j]) VG_(clo_trace_reg) |= (1 << (2-j)); ++ else { ++ VG_(fmsg_bad_option)(arg, ++ "--trace-reg argument can only contain 0s and 1s\n"); ++ } ++ } ++ } ++ + /* "stuvwxyz" --> stuvwxyz (binary) */ + else if VG_STR_CLOM(cloPD, arg, "--profile-flags", tmp_str) { + Int j; +@@ -2108,7 +2131,7 @@ Int valgrind_main ( Int argc, HChar **argv, HChar **envp ) + vg_assert(VG_(running_tid) == VG_INVALID_THREADID); + VG_(running_tid) = tid_main; + +- VG_(ii_finalise_image)( the_iifii ); ++ VG_(ii_finalise_image)( the_iifii, the_iicii ); + + /* Clear the running thread indicator */ + VG_(running_tid) = VG_INVALID_THREADID; +@@ -2484,6 +2507,21 @@ static void final_tidyup(ThreadId tid) + sizeof(VG_(threads)[tid].arch.vex.guest_r25)); + # endif + ++/* r27 infect sub-func r29: ++ dissembly of sub-func is: ++ void VG_NOTIFY_ON_LOAD(freeres)(Vg_FreeresToRun to_run) ++ ++ 990: 02 00 bb ff ldih $r29,2($r27) ++ 994: 80 96 bd fb ldi $r29,-27008($r29) ++*/ ++/* see also in coregrind/m_translate.c: 1370*/ ++# if defined(VGP_sw64_linux) ++ VG_(threads)[tid].arch.vex.guest_r27 = freeres_wrapper; ++ VG_TRACK(post_reg_write, Vg_CoreClientReq, tid, ++ offsetof(VexGuestSW64State, guest_r27), ++ sizeof(VG_(threads)[tid].arch.vex.guest_r27)); ++# endif ++ + /* Pass a parameter to freeres_wrapper(). */ + # if defined(VGA_x86) + Addr sp = VG_(threads)[tid].arch.vex.guest_ESP; +@@ -2519,6 +2557,11 @@ static void final_tidyup(ThreadId tid) + VG_TRACK(post_reg_write, Vg_CoreClientReq, tid, + offsetof(VexGuestMIPS64State, guest_r4), + sizeof(VG_(threads)[tid].arch.vex.guest_r4)); ++# elif defined(VGA_sw64) ++ VG_(threads)[tid].arch.vex.guest_r16 = to_run; ++ VG_TRACK(post_reg_write, Vg_CoreClientReq, tid, ++ offsetof(VexGuestSW64State, guest_r16), ++ sizeof(VG_(threads)[tid].arch.vex.guest_r16)); + # elif defined(VGA_ppc32) + VG_(threads)[tid].arch.vex.guest_GPR3 = to_run; + VG_TRACK(post_reg_write, Vg_CoreClientReq, tid, +@@ -3062,6 +3105,27 @@ asm( + ".set pop \n\t" + ".previous \n\t" + ); ++#elif defined(VGP_sw64_linux) ++asm("\n" ++ "\t.text\n" ++ "\t.set macro\n" ++ "\t.type _start,@function\n" ++ "\t.global _start\n" ++ "\t_start:\n" ++ "\tbr $29, 1f\n" ++ "\t1: ldgp $29, 0($29)\n" ++ "\tldih $0,vgPlain_interim_stack($29)!gprelhigh\n" ++ "\tldi $0, vgPlain_interim_stack($0) !gprellow\n" ++ "\tldi $1, "VG_STRINGIFY(VG_STACK_GUARD_SZB)"($31)\n" ++ "\taddl $0, $1, $0\n" ++ "\tldi $1, "VG_STRINGIFY(VG_DEFAULT_STACK_ACTIVE_SZB)"($31)\n" ++ "\taddl $0, $1, $0\n" ++ "\tldi $1, 0xFFFFFF00\n" ++ "\tand $0, $1, $0\n" ++ "\tmov $sp, $16\n" //$16 _start_in_C_linux, first arg ++ "\tmov $0, $sp\n" ++ "\tcall _start_in_C_linux\n" ++); + #else + # error "Unknown platform" + #endif +@@ -3107,7 +3171,7 @@ void _start_in_C_linux ( UWord* pArgc ) + # if defined(VGP_ppc32_linux) || defined(VGP_ppc64be_linux) \ + || defined(VGP_ppc64le_linux) || defined(VGP_arm64_linux) \ + || defined(VGP_mips32_linux) || defined(VGP_mips64_linux) \ +- || defined(VGP_nanomips_linux) ++ || defined(VGP_nanomips_linux) || defined(VGP_sw64_linux) + { + /* ppc32/ppc64, arm64, mips32/64 can be configured with different + page sizes. Determine this early. This is an ugly hack and really +diff --git a/coregrind/m_options.c b/coregrind/m_options.c +index 1483af2d9..d168f9424 100644 +--- a/coregrind/m_options.c ++++ b/coregrind/m_options.c +@@ -140,6 +140,7 @@ UChar VG_(clo_profyle_flags) = 0; // 00000000b + ULong VG_(clo_profyle_interval) = 0; + Int VG_(clo_trace_notbelow) = -1; // unspecified + Int VG_(clo_trace_notabove) = -1; // unspecified ++Int VG_(clo_trace_reg) = 0; + Bool VG_(clo_trace_syscalls) = False; + Bool VG_(clo_trace_signals) = False; + Bool VG_(clo_trace_symtab) = False; +@@ -148,6 +149,7 @@ Bool VG_(clo_trace_cfi) = False; + Bool VG_(clo_debug_dump_syms) = False; + Bool VG_(clo_debug_dump_line) = False; + Bool VG_(clo_debug_dump_frames) = False; ++Bool VG_(clo_dump_expansion_ratio) = False; + Bool VG_(clo_trace_redir) = False; + enum FairSchedType + VG_(clo_fair_sched) = disable_fair_sched; +@@ -203,7 +205,8 @@ UInt VG_(clo_unw_stack_scan_frames) = 5; + VgSmc VG_(clo_smc_check) = Vg_SmcAllNonFile; + #elif defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le) \ + || defined(VGA_arm) || defined(VGA_arm64) \ +- || defined(VGA_mips32) || defined(VGA_mips64) || defined(VGA_nanomips) ++ || defined(VGA_mips32) || defined(VGA_mips64) || defined(VGA_nanomips) \ ++ || defined(VGA_sw64) + VgSmc VG_(clo_smc_check) = Vg_SmcStack; + #else + # error "Unknown arch" +diff --git a/coregrind/m_redir.c b/coregrind/m_redir.c +index 37c67f4c1..edbbfae2c 100644 +--- a/coregrind/m_redir.c ++++ b/coregrind/m_redir.c +@@ -1668,6 +1668,23 @@ void VG_(redir_initialise) ( void ) + ); + } + ++# elif defined(VGP_sw64_linux) ++ /* If we're using memcheck, use these intercepts right from ++ the start, otherwise ld.so makes a lot of noise. */ ++ if (0==VG_(strcmp)("Memcheck", VG_(details).name)) ++ { ++ add_hardwired_spec( ++ "ld-linux.so.2", "strlen", ++ (Addr)&VG_(sw64_linux_REDIR_FOR_strlen), ++ complain_about_stripped_glibc_ldso ++ ); ++ add_hardwired_spec( ++ "ld-linux.so.2", "index", ++ (Addr)&VG_(sw64_linux_REDIR_FOR_index), ++ complain_about_stripped_glibc_ldso ++ ); ++ } ++ + # elif defined(VGP_x86_solaris) + /* If we're using memcheck, use these intercepts right from + the start, otherwise ld.so makes a lot of noise. */ +diff --git a/coregrind/m_scheduler/scheduler.c b/coregrind/m_scheduler/scheduler.c +index 3062c1afc..6f1dbdf0a 100644 +--- a/coregrind/m_scheduler/scheduler.c ++++ b/coregrind/m_scheduler/scheduler.c +@@ -56,6 +56,8 @@ + */ + + ++#include "libvex_basictypes.h" ++#include "libvex_guest_sw64.h" + #include "pub_core_basics.h" + #include "pub_core_debuglog.h" + #include "pub_core_vki.h" +@@ -145,6 +147,161 @@ static ULong stats__n_xIndir_misses = 0; + static UInt sanity_fast_count = 0; + static UInt sanity_slow_count = 0; + ++#if defined(VGP_sw64_linux) ++void VG_(print_guest_state) ( void * vex_ptr ) ++{ ++ static UWord ctr = 0; ++ ++ VexGuestSW64State *vex = (VexGuestSW64State *)vex_ptr; ++ Int trace_flag = VG_(clo_trace_reg); ++ ++ if (!trace_flag) { ++ return; ++ } ++ ++ const DiEpoch ep = VG_(current_DiEpoch)(); ++ Addr addr = (Addr)vex->guest_PC; ++ ++ VG_(printf)("VexGuestSW64State (%lu) {\n", ctr++); ++ ++ if (trace_flag & 1) { ++ VG_(printf)(" host_EvC_FAILADDR: %llx\n", vex->host_EvC_FAILADDR); ++ VG_(printf)(" host_EvC_COUNTER: %x\n", vex->host_EvC_COUNTER); ++ } ++ ++ /* print all interger registers */ ++ if (trace_flag & 2) { ++ for(int i = 0; i < 32; i++) { ++ ULong gpr; ++ ULong offset_gpr = i * sizeof(gpr) + offsetof(VexGuestSW64State, guest_r0); ++ VG_(memcpy)(&gpr, (char *)vex + offset_gpr, sizeof(gpr)); ++ ++ ULong shadow; ++ ULong offset_shadow = sizeof(VexGuestSW64State) + offset_gpr; ++ VG_(memcpy)(&shadow, (char *)vex + offset_shadow, sizeof(shadow)); ++ ++ VG_(printf)(" [%3llu]guest_r%-2d %16llx", offset_gpr, i, gpr); ++ ++ /* print diagnosis for $gp */ ++ if (i == 29) { ++ const DebugInfo *di; ++ Addr gpfixed = vex->guest_r29 - 0x8000; ++ ++ for (di = VG_(next_DebugInfo)(0); di; di = VG_(next_DebugInfo)(di)) { ++ if (VG_(DebugInfo_get_got_avma)(di) == gpfixed) { ++ Addr text_begin = VG_(DebugInfo_get_text_avma)(di); ++ Addr text_end = text_begin + VG_(DebugInfo_get_text_size)(di); ++ if (text_begin < addr && addr < text_end) { ++ VG_(printf)(" (good)"); ++ } else { ++ VG_(printf)(" (outdated)"); ++ } ++ break; ++ } ++ } ++ ++ if (!di) { ++ VG_(printf)(" (bad)"); ++ } ++ } ++ ++ if (shadow) { ++ const char *prompt = shadow == (ULong)(-1) ? "undefined" : "partial-defined"; ++ VG_(printf)(" [%3llu]shadow %16llx (%s)", offset_shadow, shadow, prompt); ++ } ++ ++ VG_(printf)("\n"); ++ } ++ } ++ ++ /* print all float registers */ ++ if (trace_flag & 4) { ++ for(int i = 0; i < 32; i++) { ++ ULong flt; ++ ULong offset_flt = i * sizeof(flt) + offsetof(VexGuestSW64State, guest_f0); ++ VG_(memcpy)(&flt, (char *)vex + offset_flt, sizeof(flt)); ++ ++ ULong shadow; ++ ULong offset_shadow = sizeof(VexGuestSW64State) + offset_flt; ++ VG_(memcpy)(&shadow, (char *)vex + offset_shadow, sizeof(shadow)); ++ ++ VG_(printf)(" [%03llu]guest_f%-2d %16llx", offset_flt, i, flt); ++ ++ if (shadow) { ++ const char *prompt = shadow == (ULong)(-1) ? "undefined" : "partial-defined"; ++ VG_(printf)(" [%3llu]shadow %16llx (%s)", offset_shadow, shadow, prompt); ++ } ++ ++ VG_(printf)("\n"); ++ } ++ ++ VG_(printf)(" guest_FPCR: %llx\n", vex->guest_FPCR); ++ } ++ ++ /* print all control registers */ ++ if (trace_flag & 1) { ++ VG_(printf)(" guest_CSR: %llx\n", vex->guest_CSR); ++ ++ VG_(printf)(" guest_EMNOTE: %x\n", vex->guest_EMNOTE); ++ VG_(printf)(" guest_CMSTART: %llx\n", vex->guest_CMSTART); ++ VG_(printf)(" guest_CMLEN: %llx\n", vex->guest_CMLEN); ++ ++ VG_(printf)(" guest_NRADDR: %llx\n", vex->guest_NRADDR); ++ VG_(printf)(" guest_LOCKFLAG: %llx\n", vex->guest_LOCKFLAG); ++ VG_(printf)(" guest_LOCKVALID: %llx\n", vex->guest_LOCKVALID); ++ VG_(printf)(" guest_LOCKSUCCESS: %llx\n", vex->guest_LOCKSUCCESS); ++ VG_(printf)(" guest_LOCKSIZE: %llx\n", vex->guest_LOCKSIZE); ++ VG_(printf)(" guest_LOCKADDR: %llx\n", vex->guest_LOCKADDR); ++ VG_(printf)(" guest_LOCKDATA: %llx\n", vex->guest_LOCKDATA); ++ ++ VG_(printf)(" guest_TID: %llx\n", vex->guest_TID); ++ } ++ ++ VG_(printf)(" guest_PC: %llx", vex->guest_PC); ++ ++ Bool fnok; ++ const HChar *fnname; ++ OffT fnoff; ++ fnok = VG_(get_fnname)(ep, addr, &fnname); ++ fnok = fnok && VG_(get_inst_offset_in_function)(ep, addr , &fnoff); ++ ++ Bool srcok; ++ HChar const *srcname; ++ UInt srcline; ++ srcok = VG_(get_filename)(ep, addr, &srcname); ++ srcok = srcok && VG_(get_linenum)(ep, addr, &srcline); ++ ++ ++ if (fnok && srcok) { ++ VG_(printf)( ++ " %s%c0x%lx (%s:%u)\n", ++ fnname, fnoff >= 0 ? '+' : '-', (UWord)(fnoff >= 0 ? fnoff : -fnoff), ++ srcname, srcline ++ ); ++ } else if (fnok) { ++ VG_(printf)( ++ " %s%c0x%lx\n", ++ fnname, fnoff >= 0 ? '+' : '-', (UWord)(fnoff >= 0 ? fnoff : -fnoff) ++ ); ++ } else if (srcok) { ++ VG_(printf)( ++ " (%s:%u)\n", ++ srcname, srcline ++ ); ++ } else { ++ VG_(printf)("\n"); ++ } ++ ++ VG_(printf)("}\n"); ++} ++#else /* #if defined(VGP_sw64_linux) */ ++ ++void VG_(print_guest_state) ( void * vex_ptr ) ++{ ++ (void) vex_ptr; ++} ++#endif ++ + void VG_(print_scheduler_stats)(void) + { + VG_(message)(Vg_DebugMsg, +@@ -1036,6 +1193,8 @@ void run_thread_for_a_while ( /*OUT*/HWord* two_words, + ) + ); + ++ VG_(print_guest_state)((void *)&tst->arch.vex); ++ + vg_assert(VG_(in_generated_code) == True); + VG_(in_generated_code) = False; + +@@ -1821,6 +1980,9 @@ void VG_(nuke_all_threads_except) ( ThreadId me, VgSchedReturnCode src ) + #elif defined(VGA_mips32) || defined(VGA_mips64) || defined(VGA_nanomips) + # define VG_CLREQ_ARGS guest_r12 + # define VG_CLREQ_RET guest_r11 ++#elif defined(VGA_sw64) ++# define VG_CLREQ_ARGS guest_r5 ++# define VG_CLREQ_RET guest_r4 + #else + # error Unknown arch + #endif +diff --git a/coregrind/m_sigframe/sigframe-sw64-linux.c b/coregrind/m_sigframe/sigframe-sw64-linux.c +new file mode 100644 +index 000000000..ced89fd2d +--- /dev/null ++++ b/coregrind/m_sigframe/sigframe-sw64-linux.c +@@ -0,0 +1,224 @@ ++ ++/*--------------------------------------------------------------------*/ ++/*--- Create/destroy signal delivery frames. ---*/ ++/*--- sigframe-sw64-linux.c ---*/ ++/*--------------------------------------------------------------------*/ ++ ++/* ++ This file is part of Valgrind, a dynamic binary instrumentation ++ framework. ++ ++ Copyright (C) 2010-2017 RT-RK ++ ++ This program is free software; you can redistribute it and/or ++ modify it under the terms of the GNU General Public License as ++ published by the Free Software Foundation; either version 2 of the ++ License, or (at your option) any later version. ++ ++ This program is distributed in the hope that it will be useful, but ++ WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with this program; if not, see . ++ ++ The GNU General Public License is contained in the file COPYING. ++*/ ++ ++#if defined(VGP_sw64_linux) ++ ++#include "pub_core_basics.h" ++#include "pub_core_vki.h" ++#include "pub_core_threadstate.h" ++#include "pub_core_aspacemgr.h" ++#include "pub_core_libcbase.h" ++#include "pub_core_libcassert.h" ++#include "pub_core_libcprint.h" ++#include "pub_core_machine.h" ++#include "pub_core_options.h" ++#include "pub_core_sigframe.h" ++#include "pub_core_signals.h" ++#include "pub_core_tooliface.h" ++#include "pub_core_trampoline.h" ++#include "priv_sigframe.h" ++ ++struct vg_sig_private { ++ UInt magicPI; ++ UInt sigNo_private; ++ VexGuestSW64State vex; ++ VexGuestSW64State vex_shadow1; ++ VexGuestSW64State vex_shadow2; ++}; ++ ++struct rt_sigframe { ++ struct vki_siginfo info; ++ struct vki_ucontext uc; ++ struct vg_sig_private vp; ++}; ++ ++/* EXPORTED */ ++void VG_(sigframe_create) ( ThreadId tid, ++ Bool on_altstack, ++ Addr sp_top_of_frame, ++ const vki_siginfo_t *siginfo, ++ const struct vki_ucontext *siguc, ++ void *handler, ++ UInt flags, ++ const vki_sigset_t *mask, ++ void *restorer ) ++{ ++ ThreadState *tst = VG_(get_ThreadState)(tid); ++ Addr sp = sp_top_of_frame; ++ Int sigNo = siginfo->si_signo; ++ UInt size = sizeof(struct rt_sigframe); ++ struct rt_sigframe *frame; ++ ++ sp -= size; ++ sp = VG_ROUNDDN(sp, 16); ++ ++ if (! ML_(sf_maybe_extend_stack)(tst, sp, size, flags)) ++ return; // Give up. No idea if this is correct ++ ++ frame = (struct rt_sigframe *)sp; ++ ++ /* save some valgrind private data */ ++ struct vg_sig_private *priv = &frame->vp; ++ priv->magicPI = 0x31415927; ++ priv->sigNo_private = siginfo->si_signo; ++ priv->vex = tst->arch.vex; ++ priv->vex_shadow1 = tst->arch.vex_shadow1; ++ priv->vex_shadow2 = tst->arch.vex_shadow2; ++ ++ /* prepard for siginfo */ ++ struct vki_siginfo *info = &frame->info; ++ VG_TRACK( pre_mem_write, Vg_CoreSignal, tst->tid, "signal handler siginfo", ++ (Addr)info, sizeof(frame->info)); ++ VG_(memcpy)(info, siginfo, sizeof(vki_siginfo_t)); ++ if (sigNo == VKI_SIGILL && siginfo->si_code > 0) { ++ frame->info._sifields._sigfault._addr ++ = (Addr*)(tst)->arch.vex.guest_PC; ++ } ++ VG_TRACK( post_mem_write, Vg_CoreSignal, tst->tid, ++ (Addr)info, sizeof(frame->info)); ++ ++ /* prepare for ucontext ++ ref: linux-4.19.y-sw/arch/sw_64/kernel/signal.c */ ++ struct vki_ucontext *uc = &frame->uc; ++ struct vki_sigcontext *sc = &uc->uc_mcontext; ++ VG_TRACK( pre_mem_write, Vg_CoreSignal, tst->tid, "signal handler frame", ++ (Addr)uc, sizeof(frame->uc)); ++ VG_(memset)(uc, 0, sizeof(*uc)); ++ uc->uc_flags = 0; ++ uc->uc_link = 0; ++ uc->uc_old_sigmask = mask->sig[0]; ++ uc->uc_sigmask = *mask; ++ uc->uc_stack = tst->altstack; ++ sc->sc_onstack = 0; ++ sc->sc_mask = mask->sig[0]; ++ sc->sc_pc = tst->arch.vex.guest_PC; ++ sc->sc_ps = 8; ++# define TO_CTX(reg) sc->sc_regs[reg] = tst->arch.vex.guest_r##reg ++ TO_CTX(0); TO_CTX(1); TO_CTX(2); TO_CTX(3); ++ TO_CTX(4); TO_CTX(5); TO_CTX(6); TO_CTX(7); ++ TO_CTX(8); TO_CTX(9); TO_CTX(10); TO_CTX(11); ++ TO_CTX(12); TO_CTX(13); TO_CTX(14); TO_CTX(15); ++ TO_CTX(16); TO_CTX(17); TO_CTX(18); TO_CTX(19); ++ TO_CTX(20); TO_CTX(21); TO_CTX(22); TO_CTX(23); ++ TO_CTX(24); TO_CTX(25); TO_CTX(26); TO_CTX(27); ++ TO_CTX(28); TO_CTX(29); TO_CTX(30); ++# undef TO_CTX ++ VG_TRACK( post_mem_write, Vg_CoreSignal, tst->tid, ++ (Addr)uc, sizeof(frame->uc)); ++ ++ /* "Return" to the handler */ ++ if (flags & VKI_SA_RESTORER) ++ tst->arch.vex.guest_r26 = (Addr)restorer; ++ else ++ tst->arch.vex.guest_r26 = (Addr)&VG_(sw64_linux_SUBST_FOR_rt_sigreturn); ++ tst->arch.vex.guest_r27 = (Addr)handler; ++ tst->arch.vex.guest_PC = (Addr)handler; ++ tst->arch.vex.guest_r16 = (Addr)sigNo; ++ if (flags & VKI_SA_SIGINFO) { ++ tst->arch.vex.guest_r17 = (Addr)&frame->info; ++ tst->arch.vex.guest_r18 = (Addr)&frame->uc; ++ } else { ++ tst->arch.vex.guest_r17 = 0; ++ tst->arch.vex.guest_r18 = (Addr)&frame->uc.uc_mcontext; ++ } ++ ++ VG_(set_SP)(tid, sp); ++ VG_TRACK( post_reg_write, Vg_CoreSignal, tid, VG_O_STACK_PTR, ++ sizeof(Addr)); ++} ++ ++ ++/*------------------------------------------------------------*/ ++/*--- Destroying signal frames ---*/ ++/*------------------------------------------------------------*/ ++ ++/* EXPORTED */ ++void VG_(sigframe_destroy)( ThreadId tid, Bool isRT ) ++{ ++ vg_assert(VG_(is_valid_tid)(tid)); ++ ++ Bool has_siginfo = isRT; ++ ThreadState* tst = VG_(get_ThreadState)(tid); ++ Addr sp = tst->arch.vex.guest_r16; ++ struct rt_sigframe* frame = (struct rt_sigframe *)sp; ++ struct vg_sig_private* priv = &frame->vp; ++ vg_assert(priv->magicPI == 0x31415927); ++ ++ tst->sig_mask = frame->uc.uc_sigmask; ++ tst->tmp_sig_mask = tst->sig_mask; ++ ++ Int sigNo = priv->sigNo_private; ++ UInt frame_size = sizeof(*frame); ++ ++ /* Restore the entire machine state from our private copy. This ++ isn't really right, but we'll now move on to pick up at least ++ some changes that the signal handler may have made to the ++ sigcontext. */ ++ tst->arch.vex = priv->vex; ++ tst->arch.vex_shadow1 = priv->vex_shadow1; ++ tst->arch.vex_shadow2 = priv->vex_shadow2; ++ ++ if (has_siginfo) { ++ /* Pick up at least some state changes from the ucontext, just ++ in case the handler changed it. The shadow values will be ++ wrong, but hey. This restores the integer registers, the ++ program counter and stack pointer. FP/Vector regs, and any ++ condition code, FP status/control bits, etc, are not ++ restored. */ ++ struct vki_sigcontext *sc =&frame->uc.uc_mcontext; ++# define FROM_CTX(reg) tst->arch.vex.guest_r##reg = sc->sc_regs[reg] ++ FROM_CTX(0); FROM_CTX(1); FROM_CTX(2); FROM_CTX(3); ++ FROM_CTX(4); FROM_CTX(5); FROM_CTX(6); FROM_CTX(7); ++ FROM_CTX(8); FROM_CTX(9); FROM_CTX(10); FROM_CTX(11); ++ FROM_CTX(12); FROM_CTX(13); FROM_CTX(14); FROM_CTX(15); ++ FROM_CTX(16); FROM_CTX(17); FROM_CTX(18); FROM_CTX(19); ++ FROM_CTX(20); FROM_CTX(21); FROM_CTX(22); FROM_CTX(23); ++ FROM_CTX(24); FROM_CTX(25); FROM_CTX(26); FROM_CTX(27); ++ FROM_CTX(28); FROM_CTX(29); FROM_CTX(30); ++# undef FROM_CTX ++ tst->arch.vex.guest_PC = sc->sc_pc; ++ } ++ ++ VG_TRACK( die_mem_stack_signal, sp - VG_STACK_REDZONE_SZB, ++ frame_size + VG_STACK_REDZONE_SZB ); ++ ++ if (VG_(clo_trace_signals)) ++ VG_(message)(Vg_DebugMsg, ++ "vg_pop_signal_frame (thread %u): " ++ "isRT=%d valid magic; PC=%#llx\n", ++ tid, has_siginfo, tst->arch.vex.guest_PC); ++ ++ /* tell the tools */ ++ VG_TRACK( post_deliver_signal, tid, sigNo ); ++} ++ ++#endif /* defined(VGP_sw64_linux) */ ++ ++/*--------------------------------------------------------------------*/ ++/*--- end sigframe-sw64-linux.c ---*/ ++/*--------------------------------------------------------------------*/ +diff --git a/coregrind/m_signals.c b/coregrind/m_signals.c +index b3c94fcc9..9bf9cd816 100644 +--- a/coregrind/m_signals.c ++++ b/coregrind/m_signals.c +@@ -628,6 +628,25 @@ VgHashTable *ht_sigchld_ignore = NULL; + (srP)->misc.MIPS32.r28 = (uc)->uc_mcontext.sc_regs[28]; \ + } + ++#elif defined(VGP_sw64_linux) ++# define VG_UCONTEXT_INSTR_PTR(uc) (((uc)->uc_mcontext.sc_pc)) ++# define VG_UCONTEXT_STACK_PTR(uc) ((uc)->uc_mcontext.sc_regs[30]) ++# define VG_UCONTEXT_FRAME_PTR(uc) ((uc)->uc_mcontext.sc_regs[15]) ++# define VG_UCONTEXT_SYSCALL_NUM(uc) ((uc)->uc_mcontext.sc_regs[0]) ++# define VG_UCONTEXT_SYSCALL_SYSRES(uc) \ ++ /* Convert the value in uc_mcontext.rax into a SysRes. */ \ ++ VG_(mk_SysRes_sw64_linux)((uc)->uc_mcontext.sc_regs[0], \ ++ (uc)->uc_mcontext.sc_regs[19], \ ++ (uc)->uc_mcontext.sc_regs[20]) ++ ++# define VG_UCONTEXT_TO_UnwindStartRegs(srP, uc) \ ++ { (srP)->r_pc = (uc)->uc_mcontext.sc_pc; \ ++ (srP)->r_sp = (uc)->uc_mcontext.sc_regs[30]; \ ++ (srP)->misc.SW64.r15 = (uc)->uc_mcontext.sc_regs[15]; \ ++ (srP)->misc.SW64.r26 = (uc)->uc_mcontext.sc_regs[26]; \ ++ (srP)->misc.SW64.r29 = (uc)->uc_mcontext.sc_regs[29]; \ ++ } ++ + #elif defined(VGP_x86_solaris) + # define VG_UCONTEXT_INSTR_PTR(uc) ((Addr)(uc)->uc_mcontext.gregs[VKI_EIP]) + # define VG_UCONTEXT_STACK_PTR(uc) ((Addr)(uc)->uc_mcontext.gregs[VKI_UESP]) +@@ -1052,6 +1071,14 @@ extern void my_sigreturn(void); + " li $t4, " #name "\n" \ + " syscall[32]\n" \ + ".previous\n" ++#elif defined(VGP_sw64_linux) ++/* Not used on sw64_linux */ ++# define _MY_SIGRETURN(name) \ ++ ".text\n" \ ++ "my_sigreturn:\n" \ ++ " ldi $0, " #name "\n" \ ++ " sys_call 0x83\n" \ ++ ".previous\n" + #elif defined(VGP_x86_solaris) || defined(VGP_amd64_solaris) + /* Not used on Solaris. */ + # define _MY_SIGRETURN(name) \ +@@ -1111,7 +1138,8 @@ static void handle_SCSS_change ( Bool force_update ) + ksa.sa_flags = skss.skss_per_sig[sig].skss_flags; + # if !defined(VGP_ppc32_linux) && \ + !defined(VGP_x86_darwin) && !defined(VGP_amd64_darwin) && \ +- !defined(VGP_mips32_linux) && !defined(VGO_solaris) && !defined(VGO_freebsd) ++ !defined(VGP_mips32_linux) && !defined(VGO_solaris) && \ ++ !defined(VGO_freebsd) && !defined(VGP_sw64_linux) + ksa.sa_restorer = my_sigreturn; + # endif + /* Re above ifdef (also the assertion below), PaulM says: +@@ -1159,7 +1187,7 @@ static void handle_SCSS_change ( Bool force_update ) + !defined(VGP_x86_darwin) && !defined(VGP_amd64_darwin) && \ + !defined(VGP_mips32_linux) && !defined(VGP_mips64_linux) && \ + !defined(VGP_nanomips_linux) && !defined(VGO_solaris) && \ +- !defined(VGO_freebsd) ++ !defined(VGO_freebsd) && !defined(VGP_sw64_linux) + vg_assert(ksa_old.sa_restorer == my_sigreturn); + # endif + VG_(sigaddset)( &ksa_old.sa_mask, VKI_SIGKILL ); +@@ -2296,8 +2324,9 @@ void VG_(synth_sigtrap)(ThreadId tid) + // Synthesise a SIGFPE. + void VG_(synth_sigfpe)(ThreadId tid, UInt code) + { +-// Only tested on mips32, mips64, s390x and nanomips. +-#if !defined(VGA_mips32) && !defined(VGA_mips64) && !defined(VGA_s390x) && !defined(VGA_nanomips) ++// Only tested on mips32, mips64, s390x, nanomips and sw64. ++#if !defined(VGA_mips32) && !defined(VGA_mips64) && !defined(VGA_s390x) && \ ++ !defined(VGA_nanomips) && !defined(VGA_sw64) + vg_assert(0); + #else + vki_siginfo_t info; +diff --git a/coregrind/m_stacktrace.c b/coregrind/m_stacktrace.c +index 308bebdd8..e7ca90850 100644 +--- a/coregrind/m_stacktrace.c ++++ b/coregrind/m_stacktrace.c +@@ -1502,6 +1502,102 @@ UInt VG_(get_StackTrace_wrk) ( ThreadId tid_if_known, + + #endif + ++/* ------------------------ sw64 ------------------------- */ ++#if defined(VGP_sw64_linux) ++UInt VG_(get_StackTrace_wrk) ( ThreadId tid_if_known, ++ /*OUT*/Addr* ips, UInt max_n_ips, ++ /*OUT*/Addr* sps, /*OUT*/Addr* fps, ++ const UnwindStartRegs* startRegs, ++ Addr fp_max_orig ) ++{ ++ Bool debug = False; ++ Int i; ++ Addr fp_max; ++ UInt n_found = 0; ++ const Int cmrf = VG_(clo_merge_recursive_frames); ++ ++ vg_assert(sizeof(Addr) == sizeof(UWord)); ++ vg_assert(sizeof(Addr) == sizeof(void*)); ++ ++ D3UnwindRegs uregs; ++ uregs.pc = startRegs->r_pc; ++ uregs.sp = startRegs->r_sp; ++ uregs.fp = startRegs->misc.SW64.r15; ++ uregs.ra = startRegs->misc.SW64.r26; ++ Addr fp_min = uregs.sp - VG_STACK_REDZONE_SZB; ++ ++ /* Snaffle IPs from the client's stack into ips[0 .. max_n_ips-1], ++ stopping when the trail goes cold, which we guess to be ++ when FP is not a reasonable stack location. */ ++ ++ fp_max = VG_PGROUNDUP(fp_max_orig); ++ if (fp_max >= sizeof(Addr)) ++ fp_max -= sizeof(Addr); ++ ++ if (debug) ++ VG_(printf)("max_n_ips=%u fp_min=0x%lx fp_max_orig=0x%lx, " ++ "fp_max=0x%lx pc=0x%lx sp=0x%lx fp=0x%lx\n", ++ max_n_ips, fp_min, fp_max_orig, fp_max, ++ uregs.pc, uregs.sp, uregs.fp); ++ ++ if (sps) sps[0] = uregs.sp; ++ if (fps) fps[0] = uregs.fp; ++ ips[0] = uregs.pc; ++ i = 1; ++ ++ /* Loop unwinding the stack. */ ++ while (True) { ++ if (debug) { ++ VG_(printf)("i: %d, pc: 0x%lx, sp: 0x%lx, ra: 0x%lx\n", ++ i, uregs.pc, uregs.sp, uregs.ra); ++ } ++ if (i >= max_n_ips) ++ break; ++ ++ D3UnwindRegs uregs_copy = uregs; ++ if (VG_(use_CF_info)( &uregs, fp_min, fp_max )) { ++ if (debug) ++ VG_(printf)("USING CFI: pc: 0x%lx, sp: 0x%lx, ra: 0x%lx\n", ++ uregs.pc, uregs.sp, uregs.ra); ++ if (0 != uregs.pc && 1 != uregs.pc) { ++ if (sps) sps[i] = uregs.sp; ++ if (fps) fps[i] = uregs.fp; ++ ips[i++] = uregs.pc - 4; ++ uregs.pc = uregs.pc - 4; ++ RECURSIVE_MERGE(cmrf,ips,i); ++ continue; ++ } else ++ uregs = uregs_copy; ++ } ++ ++ /* cfi missing, but we are in first frame, the return address should be ++ saved in RA register */ ++ if (i == 1) { ++ if (sps) { ++ sps[i] = sps[0]; ++ uregs.sp = sps[0]; ++ } ++ if (fps) { ++ fps[i] = fps[0]; ++ uregs.fp = fps[0]; ++ } ++ if (0 == uregs.ra || 1 == uregs.ra) break; ++ uregs.pc = uregs.ra; ++ ips[i++] = uregs.ra; ++ RECURSIVE_MERGE(cmrf,ips,i); ++ continue; ++ } ++ ++ /* No luck. We have to give up. */ ++ break; ++ } ++ ++ n_found = i; ++ return n_found; ++} ++ ++#endif ++ + /*------------------------------------------------------------*/ + /*--- ---*/ + /*--- END platform-dependent unwinder worker functions ---*/ +diff --git a/coregrind/m_swdiv.S b/coregrind/m_swdiv.S +new file mode 100644 +index 000000000..f9d5451b8 +--- /dev/null ++++ b/coregrind/m_swdiv.S +@@ -0,0 +1,724 @@ ++/*--------------------------------------------------------------------*/ ++/*--- sw div and rem stuff. m_swdiv.S ---*/ ++/*--------------------------------------------------------------------*/ ++ ++/* ++ This file is part of Valgrind, a dynamic binary instrumentation ++ framework. ++ ++ Copyright (C) 2000-2017 Julian Seward ++ jseward@acm.org ++ Copyright (C) 2006-2017 OpenWorks LLP ++ info@open-works.co.uk ++ ++ This program is free software; you can redistribute it and/or ++ modify it under the terms of the GNU General Public License as ++ published by the Free Software Foundation; either version 2 of the ++ License, or (at your option) any later version. ++ ++ This program is distributed in the hope that it will be useful, but ++ WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with this program; if not, see . ++ ++ The GNU General Public License is contained in the file COPYING. ++*/ ++ ++#include "pub_core_basics_asm.h" ++ ++/* ---------------- remlu divlu for sw64 ---------------- */ ++/* sw64 defined these operation in glibc: ++ reml, remlu, remw, remwu ++ divl, divlu, divw, divwu ++ we need to define these operation by self */ ++ ++#if defined(VGP_sw64_linux) ++ ++.set noat ++.globl __reml ++__reml: ++ ldi $sp,-96($sp) ++ fstd $f0,0($sp) ++ beq $r25,reml_14 ++ fstd $f1,8($sp) ++ fstd $f3,48($sp) ++ fstd $f4,56($sp) ++ fstd $f5,64($sp) ++ rfpcr $f3 ++ ifmovd $r24,$f0 ++ ifmovd $r25,$f1 ++ fcvtld $f0,$f4 ++ fcvtld $f1,$f5 ++ fdivd $f4,$f5,$f0 ++ sll $r24,0xb,$r28 ++ fldd $f1,8($sp) ++ sra $r28,0xb,$r28 ++ cmpeq $r24,$r28,$r28 ++ beq $r28,reml_1 ++ fcvtdl_z $f0,$f4 ++ wfpcr $f3 ++ fimovd $f4,$r28 ++ mull $r28,$r25,$r28 ++ fldd $f0,0($sp) ++ fldd $f3,48($sp) ++ fldd $f4,56($sp) ++ fldd $f5,64($sp) ++ ldi $sp,96($sp) ++ subl $r24,$r28,$r27 ++ ret $r31, ($r23), 0x1 ++ reml_1: ++ stl $r1,32($sp) ++ stl $r2,40($sp) ++ stl $r3,16($sp) ++ stl $r6,24($sp) ++ or $r24,$r25,$r28 ++ blt $r28,reml_12 ++ reml_2: ++ fcvtdl_z $f0,$f4 ++ fimovd $f4,$r1 ++ reml_3: ++ fldd $f0,0($sp) ++ stl $r4,0($sp) ++ mull $r1,$r25,$r4 ++ stl $r5,8($sp) ++ wfpcr $f3 ++ subl $r4,$r24,$r27 ++ mov $r25,$r2 ++ mov 0x1,$r3 ++ bgt $r27,reml_8 ++ reml_4: ++ subl $r24,$r4,$r27 ++ mov $r25,$r2 ++ mov 0x1,$r3 ++ bgt $r27,reml_10 ++ reml_5: ++ ldl $r1,32($sp) ++ ldl $r2,40($sp) ++ ldl $r3,16($sp) ++ bne $r6,reml_13 ++ reml_6: ++ ldl $r4,0($sp) ++ ldl $r5,8($sp) ++ ldl $r6,24($sp) ++ fldd $f3,48($sp) ++ fldd $f4,56($sp) ++ fldd $f5,64($sp) ++ ldi $sp,96($sp) ++ ret $r31, ($r23), 0x1 ++ reml_7: ++ addl $r2,$r2,$r2 ++ addl $r3,$r3,$r3 ++ reml_8: ++ cmpult $r2,$r27,$r28 ++ bne $r28,reml_7 ++ subl $r1,$r3,$r1 ++ subl $r4,$r2,$r4 ++ br reml_4 ++ reml_9: ++ addl $r2,$r2,$r2 ++ addl $r3,$r3,$r3 ++ reml_10: ++ cmpult $r2,$r27,$r28 ++ bne $r28,reml_9 ++ reml_11: ++ addl $r1,$r3,$r4 ++ srl $r3,0x1,$r3 ++ cmpule $r2,$r27,$r28 ++ subl $r27,$r2,$r5 ++ selne $r28,$r4,$r1,$r1 ++ selne $r28,$r5,$r27,$r27 ++ srl $r2,0x1,$r2 ++ bne $r3,reml_11 ++ br reml_5 ++ reml_12: ++ xor $r24,$r25,$r2 ++ cmplt $r24,0,$r6 ++ negl $r24,$r1 ++ selne $r6,$r1,$r24,$r24 ++ cmplt $r25,0,$r28 ++ negl $r25,$r1 ++ s4addl $r28,$r6,$r6 ++ selne $r28,$r1,$r25,$r25 ++ bge $r2,reml_2 ++ fcvtdl_z $f0,$f4 ++ fimovd $f4,$r1 ++ negl $r1,$r1 ++ br reml_3 ++ reml_13: ++ and $r6,0x4,$r28 ++ negl $r25,$r5 ++ selne $r28,$r5,$r25,$r25 ++ negl $r24,$r5 ++ sellbs $r6,$r5,$r24,$r24 ++ negl $r27,$r5 ++ sellbs $r6,$r5,$r27,$r27 ++ br reml_6 ++ reml_14: ++ mov $r16,$r27 ++ ldi $r16,-2 ++ sys_call 0xaa ++ mov $r27,$r16 ++ clr $r27 ++ ldi $sp,96($sp) ++ ret $r31, ($r23), 0x1 ++ ++ ++.globl __remw ++__remw: ++ ldi $sp,-96($sp) ++ fstd $f0,0($sp) ++ beq $r25,remw_1 ++ fstd $f1,8($sp) ++ fstd $f2,16($sp) ++ fstd $f3,40($sp) ++ fstd $f4,48($sp) ++ rfpcr $f2 ++ addw $r31,$r24,$r27 ++ addw $r31,$r25,$r28 ++ ifmovd $r27,$f0 ++ ifmovd $r28,$f1 ++ fcvtld $f0,$f3 ++ fcvtld $f1,$f4 ++ fdivd $f3,$f4,$f0 ++ fcvtdl_z $f0,$f3 ++ wfpcr $f2 ++ fimovd $f3,$r27 ++ fldd $f0,0($sp) ++ mulw $r27,$r25,$r27 ++ fldd $f1,8($sp) ++ fldd $f2,16($sp) ++ fldd $f3,40($sp) ++ fldd $f4,48($sp) ++ ldi $sp,96($sp) ++ subw $r24,$r27,$r27 ++ ret $r31, ($r23), 0x1 ++ remw_1: ++ mov $r16,$r27 ++ ldi $r16,-2 ++ sys_call 0xaa ++ mov $r27,$r16 ++ clr $r27 ++ ldi $sp,96($sp) ++ ret $r31, ($r23), 0x1 ++ ++ ++.globl __remwu ++__remwu: ++ ldi $sp,-96($sp) ++ fstd $f0,0($sp) ++ beq $r25,remwu_1 ++ fstd $f1,8($sp) ++ fstd $f2,16($sp) ++ fstd $f3,40($sp) ++ fstd $f4,48($sp) ++ rfpcr $f2 ++ zapnot $r24,0xf,$r27 ++ zapnot $r25,0xf,$r28 ++ ifmovd $r27,$f0 ++ ifmovd $r28,$f1 ++ fcvtld $f0,$f3 ++ fcvtld $f1,$f4 ++ fdivd $f3,$f4,$f0 ++ fcvtdl_z $f0,$f3 ++ wfpcr $f2 ++ fimovd $f3,$r27 ++ fldd $f0,0($sp) ++ mulw $r27,$r25,$r27 ++ fldd $f1,8($sp) ++ fldd $f2,16($sp) ++ fldd $f3,40($sp) ++ fldd $f4,48($sp) ++ ldi $sp,96($sp) ++ subw $r24,$r27,$r27 ++ ret $r31, ($r23), 0x1 ++ remwu_1: ++ mov $r16,$r27 ++ ldih $r31,0($sp) ++ ldi $r16,-2 ++ sys_call 0xaa ++ mov $r27,$r16 ++ clr $r27 ++ ldi $sp,96($sp) ++ ret $r31, ($r23), 0x1 ++ ++ ++.globl __remlu ++__remlu: ++ ldi $sp,-96($sp) ++ subl $r25,0x1,$r28 ++ fstd $f0,0($sp) ++ and $r25,$r28,$r28 ++ fstd $f1,8($sp) ++ fstd $f3,48($sp) ++ fstd $f4,56($sp) ++ fstd $f5,64($sp) ++ beq $r28,remlu_11 ++ rfpcr $f3 ++ ifmovd $r24,$f0 ++ ifmovd $r25,$f1 ++ fcvtld $f0,$f4 ++ fcvtld $f1,$f5 ++ blt $r24,remlu_1 ++ fdivd $f4,$f5,$f0 ++ fldd $f1,8($sp) ++ blt $r25,remlu_10 ++ srl $r24,0x35,$r28 ++ bne $r28,remul_2 ++ fcvtdl_z $f0,$f4 ++ wfpcr $f3 ++ fimovd $f4,$r28 ++ mull $r28,$r25,$r28 ++ fldd $f0,0($sp) ++ fldd $f3,48($sp) ++ fldd $f4,56($sp) ++ fldd $f5,64($sp) ++ ldi $sp,96($sp) ++ subl $r24,$r28,$r27 ++ ret $r31, ($r23), 0x1 ++ remlu_1: ++ ldih $r28,24448 ++ fstd $f2,24($sp) ++ fstd $f6,72($sp) ++ ifmovs $r28,$f2 ++ faddd $f4,$f2,$f6 ++ fdivd $f6,$f5,$f0 ++ fldd $f1,8($sp) ++ fldd $f2,24($sp) ++ fldd $f6,72($sp) ++ blt $r25,remlu_10 ++ remul_2: ++ stl $r1,32($sp) ++ stl $r2,40($sp) ++ stl $r3,16($sp) ++ stl $r4,24($sp) ++ fcvtdl_z $f0,$f4 ++ fimovd $f4,$r1 ++ mull $r1,$r25,$r4 ++ stl $r5,8($sp) ++ nop ++ fldd $f0,0($sp) ++ wfpcr $f3 ++ subl $r4,$r24,$r27 ++ mov $r25,$r2 ++ mov 0x1,$r3 ++ bgt $r27,remlu_6 ++ remlu_3: ++ subl $r24,$r4,$r27 ++ mov $r25,$r2 ++ mov 0x1,$r3 ++ bgt $r27,remlu_8 ++ remlu_4: ++ ldl $r5,8($sp) ++ ldl $r1,32($sp) ++ ldl $r2,40($sp) ++ ldl $r3,16($sp) ++ ldl $r4,24($sp) ++ fldd $f3,48($sp) ++ fldd $f4,56($sp) ++ fldd $f5,64($sp) ++ ldi $sp,96($sp) ++ ret $r31, ($r23), 0x1 ++ remlu_5: ++ addl $r2,$r2,$r2 ++ addl $r3,$r3,$r3 ++ remlu_6: ++ cmpult $r2,$r27,$r28 ++ bne $r28,remlu_5 ++ subl $r1,$r3,$r1 ++ subl $r4,$r2,$r4 ++ br remlu_3 ++ remlu_7: ++ addl $r2,$r2,$r2 ++ addl $r3,$r3,$r3 ++ remlu_8: ++ cmpult $r2,$r27,$r28 ++ bne $r28,remlu_7 ++ remlu_9: ++ addl $r1,$r3,$r4 ++ srl $r3,0x1,$r3 ++ cmpule $r2,$r27,$r28 ++ subl $r27,$r2,$r5 ++ selne $r28,$r4,$r1,$r1 ++ selne $r28,$r5,$r27,$r27 ++ srl $r2,0x1,$r2 ++ bne $r3,remlu_9 ++ br remlu_4 ++ remlu_10: ++ cmpule $r25,$r24,$r28 ++ wfpcr $f3 ++ subl $r24,$r25,$r27 ++ fldd $f0,0($sp) ++ fldd $f3,48($sp) ++ fldd $f4,56($sp) ++ fldd $f5,64($sp) ++ seleq $r28,$r24,$r27,$r27 ++ ldi $sp,96($sp) ++ ret $r31, ($r23), 0x1 ++ remlu_11: ++ subl $r25,0x1,$r28 ++ beq $r25,remlu_12 ++ and $r24,$r28,$r27 ++ ldi $sp,96($sp) ++ ret $r31, ($r23), 0x1 ++ remlu_12: ++ mov $r16,$r27 ++ ldi $r16,-2 ++ sys_call 0xaa ++ mov $r27,$r16 ++ clr $r27 ++ ldi $sp,96($sp) ++ ret $r31, ($r23), 0x1 ++ ++ ++.globl __divl ++__divl: ++ ldi $sp,-96($sp) ++ fstd $f0,0($sp) ++ beq $r25,divl_14 ++ fstd $f1,8($sp) ++ fstd $f3,48($sp) ++ fstd $f4,56($sp) ++ fstd $f5,64($sp) ++ rfpcr $f3 ++ ifmovd $r24,$f0 ++ ifmovd $r25,$f1 ++ fcvtld $f0,$f4 ++ fcvtld $f1,$f5 ++ fdivd $f4,$f5,$f0 ++ sll $r24,0xb,$r28 ++ fldd $f1,8($sp) ++ sra $r28,0xb,$r28 ++ cmpeq $r24,$r28,$r28 ++ beq $r28,divl_1 ++ fcvtdl_z $f0,$f4 ++ wfpcr $f3 ++ fimovd $f4,$r27 ++ fldd $f0,0($sp) ++ fldd $f3,48($sp) ++ fldd $f4,56($sp) ++ fldd $f5,64($sp) ++ ldi $sp,96($sp) ++ ret $r31, ($r23), 0x1 ++ divl_1: ++ stl $r1,32($sp) ++ stl $r2,40($sp) ++ stl $r3,16($sp) ++ stl $r6,24($sp) ++ or $r24,$r25,$r28 ++ blt $r28,divl_12 ++ divl_2: ++ fcvtdl_z $f0,$f4 ++ fimovd $f4,$r27 ++ divl_3: ++ fldd $f0,0($sp) ++ stl $r4,0($sp) ++ mull $r27,$r25,$r4 ++ stl $r5,8($sp) ++ wfpcr $f3 ++ subl $r4,$r24,$r1 ++ mov $r25,$r2 ++ mov 0x1,$r3 ++ bgt $r1,divl_8 ++ divl_4: ++ subl $r24,$r4,$r1 ++ mov $r25,$r2 ++ mov 0x1,$r3 ++ bgt $r1,divl_10 ++ divl_5: ++ ldl $r1,32($sp) ++ ldl $r2,40($sp) ++ ldl $r3,16($sp) ++ bne $r6,divl_13 ++ divl_6: ++ ldl $r4,0($sp) ++ ldl $r5,8($sp) ++ ldl $r6,24($sp) ++ fldd $f3,48($sp) ++ fldd $f4,56($sp) ++ fldd $f5,64($sp) ++ ldi $sp,96($sp) ++ ret $r31, ($r23), 0x1 ++ divl_7: ++ addl $r2,$r2,$r2 ++ addl $r3,$r3,$r3 ++ divl_8: ++ cmpult $r2,$r1,$r28 ++ bne $r28,divl_7 ++ subl $r27,$r3,$r27 ++ subl $r4,$r2,$r4 ++ br divl_4 ++ divl_9: ++ addl $r2,$r2,$r2 ++ addl $r3,$r3,$r3 ++ divl_10: ++ cmpult $r2,$r1,$r28 ++ bne $r28,divl_9 ++ divl_11: ++ addl $r27,$r3,$r4 ++ srl $r3,0x1,$r3 ++ cmpule $r2,$r1,$r28 ++ subl $r1,$r2,$r5 ++ selne $r28,$r4,$r27,$r27 ++ selne $r28,$r5,$r1,$r1 ++ srl $r2,0x1,$r2 ++ bne $r3,divl_11 ++ br divl_5 ++ divl_12: ++ xor $r24,$r25,$r28 ++ cmplt $r28,0,$r6 ++ cmplt $r24,0,$r28 ++ negl $r24,$r1 ++ s4addl $r28,$r6,$r6 ++ selne $r28,$r1,$r24,$r24 ++ cmplt $r25,0,$r28 ++ negl $r25,$r1 ++ s8addl $r28,$r6,$r6 ++ selne $r28,$r1,$r25,$r25 ++ blbc $r6,divl_2 ++ fcvtdl_z $f0,$f4 ++ fimovd $f4,$r27 ++ negl $r27,$r27 ++ br divl_3 ++ divl_13: ++ and $r6,0x8,$r28 ++ negl $r25,$r5 ++ selne $r28,$r5,$r25,$r25 ++ and $r6,0x4,$r28 ++ negl $r24,$r5 ++ selne $r28,$r5,$r24,$r24 ++ negl $r27,$r5 ++ sellbs $r6,$r5,$r27,$r27 ++ br divl_6 ++ divl_14: ++ mov $r16,$r27 ++ ldi $r16,-2 ++ sys_call 0xaa ++ mov $r27,$r16 ++ clr $r27 ++ ldi $sp,96($sp) ++ ret $r31, ($r23), 0x1 ++ ++ ++.globl __divw ++__divw: ++ ldi $sp,-96($sp) ++ fstd $f0,0($sp) ++ beq $r25,divw_1 ++ fstd $f1,8($sp) ++ fstd $f2,16($sp) ++ fstd $f3,40($sp) ++ fstd $f4,48($sp) ++ rfpcr $f2 ++ addw $r31,$r24,$r27 ++ addw $r31,$r25,$r28 ++ ifmovd $r27,$f0 ++ ifmovd $r28,$f1 ++ fcvtld $f0,$f3 ++ fcvtld $f1,$f4 ++ fdivd $f3,$f4,$f1 ++ fcvtdl_z $f1,$f0 ++ wfpcr $f2 ++ fimovd $f0,$r27 ++ fldd $f0,0($sp) ++ fldd $f1,8($sp) ++ fldd $f2,16($sp) ++ fldd $f3,40($sp) ++ fldd $f4,48($sp) ++ ldi $sp,96($sp) ++ addw $r27,0,$r27 ++ ret $r31, ($r23), 0x1 ++ ldih $r31,0($sp) ++ divw_1: ++ mov $r16,$r27 ++ ldi $r16,-2 ++ sys_call 0xaa ++ mov $r27,$r16 ++ clr $r27 ++ ldi $sp,96($sp) ++ ret $r31, ($r23), 0x1 ++ ++ ++.globl __divwu ++__divwu: ++ ldi $sp,-96($sp) ++ fstd $f0,0($sp) ++ beq $r25,divwu_1 ++ fstd $f1,8($sp) ++ fstd $f2,16($sp) ++ fstd $f3,40($sp) ++ fstd $f4,48($sp) ++ rfpcr $f2 ++ zapnot $r24,0xf,$r27 ++ zapnot $r25,0xf,$r28 ++ ifmovd $r27,$f0 ++ ifmovd $r28,$f1 ++ fcvtld $f0,$f3 ++ fcvtld $f1,$f4 ++ fdivd $f3,$f4,$f1 ++ fcvtdl_z $f1,$f0 ++ wfpcr $f2 ++ fimovd $f0,$r27 ++ fldd $f0,0($sp) ++ fldd $f1,8($sp) ++ fldd $f2,16($sp) ++ fldd $f3,40($sp) ++ fldd $f4,48($sp) ++ ldi $sp,96($sp) ++ addw $r27,0,$r27 ++ ret $r31, ($r23), 0x1 ++ divwu_1: ++ mov $r16,$r27 ++ ldi $r16,-2 ++ sys_call 0xaa ++ mov $r27,$r16 ++ ldi $sp,96($sp) ++ ret $r31, ($r23), 0x1 ++ ++ ++.globl __divlu ++__divlu: ++ ldi $sp,-96($sp) ++ fstd $f0,0($sp) ++ beq $r25,divlu_11 ++ fstd $f1,8($sp) ++ fstd $f3,48($sp) ++ fstd $f4,56($sp) ++ fstd $f5,64($sp) ++ stl $r1,32($sp) ++ stl $r2,40($sp) ++ rfpcr $f3 ++ rfpcr $f1 ++ fimovd $f1,$r1 ++ ldi $r2,3 ++ sll $r2,0x3a,$r2 ++ bic $r1,$r2,$r1 ++ ifmovd $r1,$f1 ++ wfpcr $f1 ++ ifmovd $r24,$f0 ++ ifmovd $r25,$f1 ++ fcvtld $f0,$f4 ++ fcvtld $f1,$f5 ++ blt $r24,divlu_1 ++ fdivd $f4,$f5,$f0 ++ fldd $f1,8($sp) ++ blt $r25,divlu_10 ++ srl $r24,0x35,$r28 ++ bne $r28,divlu_2 ++ fcvtdl $f0,$f4 ++ wfpcr $f3 ++ fimovd $f4,$r27 ++ ldl $r1,32($sp) ++ ldl $r2,40($sp) ++ fldd $f0,0($sp) ++ fldd $f3,48($sp) ++ fldd $f4,56($sp) ++ fldd $f5,64($sp) ++ ldi $sp,96($sp) ++ ret $r31, ($r23), 0x1 ++ ++ divlu_1: ++ ldih $r28,24448 ++ fstd $f2,24($sp) ++ fstd $f6,72($sp) ++ ifmovs $r28,$f2 ++ faddd $f4,$f2,$f6 ++ fdivd $f6,$f5,$f0 ++ fldd $f1,8($sp) ++ ldih $r31,0($sp) ++ fldd $f2,24($sp) ++ fldd $f6,72($sp) ++ blt $r25,divlu_10 ++ ++ divlu_2: ++ stl $r3,16($sp) ++ stl $r4,24($sp) ++ fcvtdl $f0,$f4 ++ fimovd $f4,$r27 ++ mull $r27,$r25,$r4 ++ stl $r5,8($sp) ++ fldd $f0,0($sp) ++ wfpcr $f3 ++ subl $r4,$r24,$r1 ++ mov $r25,$r2 ++ mov 0x1,$r3 ++ bgt $r1,divlu_6 ++ ++ divlu_3: ++ subl $r24,$r4,$r1 ++ mov $r25,$r2 ++ mov 0x1,$r3 ++ bgt $r1,divlu_8 ++ ++ divlu_4: ++ ldl $r5,8($sp) ++ ldl $r1,32($sp) ++ ldl $r2,40($sp) ++ ldl $r3,16($sp) ++ ldl $r4,24($sp) ++ fldd $f3,48($sp) ++ fldd $f4,56($sp) ++ fldd $f5,64($sp) ++ ldi $sp,96($sp) ++ ret $r31, ($r23), 0x1 ++ ++ divlu_5: ++ addl $r2,$r2,$r2 ++ addl $r3,$r3,$r3 ++ ++ divlu_6: ++ cmpult $r2,$r1,$r28 ++ bne $r28,divlu_5 ++ subl $r27,$r3,$r27 ++ subl $r4,$r2,$r4 ++ br divlu_3 ++ ++ divlu_7: ++ addl $r2,$r2,$r2 ++ addl $r3,$r3,$r3 ++ ++ divlu_8: ++ cmpult $r2,$r1,$r28 ++ bne $r28,divlu_7 ++ ++ divlu_9: ++ addl $r27,$r3,$r4 ++ srl $r3,0x1,$r3 ++ cmpule $r2,$r1,$r28 ++ subl $r1,$r2,$r5 ++ selne $r28,$r4,$r27,$r27 ++ selne $r28,$r5,$r1,$r1 ++ srl $r2,0x1,$r2 ++ bne $r3,divlu_9 ++ br divlu_4 ++ ++ divlu_10: ++ cmpule $r25,$r24,$r27 ++ wfpcr $f3 ++ fldd $f0,0($sp) ++ fldd $f3,48($sp) ++ fldd $f4,56($sp) ++ fldd $f5,64($sp) ++ ldl $r1,32($sp) ++ ldl $r2,40($sp) ++ ldi $sp,96($sp) ++ ret $r31, ($r23), 0x1 ++ ++ divlu_11: ++ mov $r16,$r27 ++ ldi $r16,-2 ++ sys_call 0xaa ++ mov $r27,$r16 ++ clr $r27 ++ ldi $sp,96($sp) ++ ret $r31, ($r23), 0x1 ++ ++#endif ++ ++/* Let the linker know we don't need an executable stack */ ++MARK_STACK_NO_EXEC ++/*--------------------------------------------------------------------*/ ++/*--- end ---*/ ++/*--------------------------------------------------------------------*/ +diff --git a/coregrind/m_syscall.c b/coregrind/m_syscall.c +index 1e49ed412..526dce922 100644 +--- a/coregrind/m_syscall.c ++++ b/coregrind/m_syscall.c +@@ -204,6 +204,15 @@ SysRes VG_(mk_SysRes_arm64_linux) ( Long val ) { + return res; + } + ++SysRes VG_(mk_SysRes_sw64_linux) ( ULong v0, ULong r19, ULong r20 ) { ++ SysRes res; ++ //sw use r19 indicats failure ++ res._isError = (r19==1); ++ res._val = v0; ++ res._valEx = r20; ++ return res; ++} ++ + /* Generic constructors. */ + SysRes VG_(mk_SysRes_Success) ( UWord res ) { + SysRes r; +@@ -1034,6 +1043,25 @@ asm ( + ".previous \n\t" + ); + ++#elif defined(VGP_sw64_linux) ++extern RegWord do_syscall_WRK ( RegWord a1, RegWord a2, RegWord a3, ++ RegWord a4, RegWord a5, RegWord a6, ++ RegWord syscall_no, RegWord* r19, RegWord* r20); ++asm ( ++ ".text \n\t" ++ ".globl do_syscall_WRK \n\t" ++ ".type do_syscall_WRK, @function \n\t" ++ "do_syscall_WRK: \n\t" ++ " ldl $0, 0($30) \n\t" ++ " sys_call 0x83 \n\t" ++ " ldl $5, 8($30) \n\t" ++ " stl $19, 0($5) \n\t" /* store r19 */ ++ " ldl $5, 16($30) \n\t" ++ " stl $20, 0($5) \n\t" /* store r20 */ ++ " ret \n\t" ++ ".previous \n\t" ++); ++ + #elif defined(VGP_x86_solaris) + + extern ULong +@@ -1274,6 +1302,12 @@ SysRes VG_(do_syscall) ( UWord sysno, RegWord a1, RegWord a2, RegWord a3, + do_syscall_WRK(a1, a2, a3, a4, a5, a6, sysno, ®_a0); + return VG_(mk_SysRes_nanomips_linux)(reg_a0); + ++#elif defined(VGP_sw64_linux) ++ RegWord r19 = 0; ++ RegWord r20 = 0; ++ RegWord v0 = do_syscall_WRK(a1, a2, a3, a4, a5, a6, sysno, &r19, &r20); ++ return VG_(mk_SysRes_sw64_linux)( v0, r19, r20 ); ++ + # elif defined(VGP_x86_solaris) + UInt val, val2, err = False; + Bool restart; +diff --git a/coregrind/m_syswrap/priv_syswrap-linux.h b/coregrind/m_syswrap/priv_syswrap-linux.h +index a73b6247e..148269e49 100644 +--- a/coregrind/m_syswrap/priv_syswrap-linux.h ++++ b/coregrind/m_syswrap/priv_syswrap-linux.h +@@ -508,6 +508,14 @@ extern UInt do_syscall_clone_nanomips_linux ( Word (*fn) (void *), /* a0 - 4 */ + Int* child_tid, /* a4 - 8 */ + Int* parent_tid, /* a5 - 9 */ + void* tls_ptr); /* a6 - 10 */ ++extern ULong do_syscall_clone_sw64_linux( Word(*fn)(void*), /*%1*/ ++ void* stack, /*%2*/ ++ Int flags, /*%3*/ ++ void* arg, /*%4*/ ++ Int* parent_tid, /*%5*/ ++ void* tls, /*%6*/ ++ Int* child_tid); /*%7*/ ++ + #endif // __PRIV_SYSWRAP_LINUX_H + + /*--------------------------------------------------------------------*/ +diff --git a/coregrind/m_syswrap/priv_types_n_macros.h b/coregrind/m_syswrap/priv_types_n_macros.h +index dd241839a..7b36af9d7 100644 +--- a/coregrind/m_syswrap/priv_types_n_macros.h ++++ b/coregrind/m_syswrap/priv_types_n_macros.h +@@ -94,7 +94,7 @@ typedef + || defined(VGP_ppc32_linux) \ + || defined(VGP_arm_linux) || defined(VGP_s390x_linux) \ + || defined(VGP_arm64_linux) \ +- || defined(VGP_nanomips_linux) ++ || defined(VGP_nanomips_linux) || defined(VGP_sw64_linux) + Int o_arg1; + Int o_arg2; + Int o_arg3; +diff --git a/coregrind/m_syswrap/syscall-sw64-linux.S b/coregrind/m_syswrap/syscall-sw64-linux.S +new file mode 100644 +index 000000000..c25062e4c +--- /dev/null ++++ b/coregrind/m_syswrap/syscall-sw64-linux.S +@@ -0,0 +1,158 @@ ++ ++/*--------------------------------------------------------------------*/ ++/*--- Support for doing system calls. syscall-sw64-linux.S ---*/ ++/*--------------------------------------------------------------------*/ ++ ++/* ++ This file is part of Valgrind, a dynamic binary instrumentation ++ framework. ++ ++ Copyright (C) 2010-2017 RT-RK ++ ++ This program is free software; you can redistribute it and/or ++ modify it under the terms of the GNU General Public License as ++ published by the Free Software Foundation; either version 2 of the ++ License, or (at your option) any later version. ++ ++ This program is distributed in the hope that it will be useful, but ++ WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with this program; if not, see . ++ ++ The GNU General Public License is contained in the file COPYING. ++*/ ++ ++#include "pub_core_basics_asm.h" ++ ++#if defined(VGP_sw64_linux) ++ ++#include "pub_core_vkiscnums_asm.h" ++#include "libvex_guest_offsets.h" ++ ++/*----------------------------------------------------------------*/ ++/* ++ Perform a syscall for the client. This will run a syscall ++ with the client's specific per-thread signal mask. ++ ++ The structure of this function is such that, if the syscall is ++ interrupted by a signal, we can determine exactly what ++ execution state we were in with respect to the execution of ++ the syscall by examining the value of PC in the signal ++ handler. This means that we can always do the appropriate ++ thing to precisely emulate the kernel's signal/syscall ++ interactions. ++ ++ The syscall number is taken from the argument, even though it ++ should also be in regs->v0. The syscall result is written ++ back to regs->v0 on completion. ++ ++ VG_(fixup_guest_state_after_syscall_interrupted) does the ++ thread state fixup in the case where we were interrupted by a ++ signal. ++ ++ Prototype: ++ ++ UWord ML_(do_syscall_for_client_WRK)( ++ Int syscallno, // $16 - a0 ++ void* guest_state, // $17 - a1 ++ const vki_sigset_t *sysmask, // $18 - a2 ++ const vki_sigset_t *postmask, // $19 - a3 ++ Int nsigwords) // $20 - a4 ++*/ ++ ++/* from vki_arch.h */ ++#define VKI_SIG_SETMASK 3 ++ ++.globl ML_(do_syscall_for_client_WRK) ++ML_(do_syscall_for_client_WRK): ++ ++ /*save regs a0-a4 on stack*/ ++ subl $30, 48, $30 ++ stl $16, 0($30) //a0 ++ stl $17, 8($30) //a1 ++ stl $18, 16($30) //a2 ++ stl $19, 24($30) //a3 ++ stl $20, 32($30) //a4 ++ ++ /*do sigprocmask*/ ++1: ldi $0, __NR_rt_sigprocmask($31) ++ ldi $16, VKI_SIG_SETMASK ++ mov $18, $17 /*sysmask*/ ++ mov $19, $18 /*postmask*/ ++ mov $20, $19 /*nsigwords*/ ++ sys_call 0x83 ++ bne $19, 7f /*r19!=0 means syscall fail*/ ++ ++ /* Actually do the client syscall */ ++ ldl $17, 8($30) /* guest_state */ ++ ldl $16, OFFSET_sw64_r16($17) /* a0 */ ++ ++ ldl $18, OFFSET_sw64_r18($17) /* a2 */ ++ ldl $19, OFFSET_sw64_r19($17) /* a3 */ ++ ldl $20, OFFSET_sw64_r20($17) /* a4 */ ++ ldl $21, OFFSET_sw64_r21($17) /* a5 */ ++ ldl $22, OFFSET_sw64_r22($17) /* a6 */ ++ ldl $23, OFFSET_sw64_r23($17) /* a7 */ ++ ++ ldl $17, OFFSET_sw64_r17($17) /* a1 */ ++ ldl $0, 0($30) /* syscallno */ ++ ++2: sys_call 0x83 ++ ++ /* Saving return values into Guest state */ ++3: ldl $17, 8($30) /* guest_state */ ++ stl $0, OFFSET_sw64_r0($17) /* v0 */ ++ stl $19, OFFSET_sw64_r19($17) /* a3 */ ++ stl $20, OFFSET_sw64_r20($17) /* a4, some syscall e.g. pipe(2) ++ use this register as 2nd return value */ ++ ++4: ldi $0, __NR_rt_sigprocmask ++ ldi $16, VKI_SIG_SETMASK ++ ldl $17, 24($30) /* postmask */ ++ mov $31, $18 /* 0 (zero) */ ++ ldl $19, 32($30) /* nsigwords */ ++ sys_call 0x83 ++ ++ bne $19, 7f /*if fail, go to error*/ ++ nop ++ ++5: /* restore 30 and return */ ++ addl $30, 48, $30 ++ jmp $31, ($26) ++ nop ++ ++ ++7: /* error */ ++ addl $30, 48, $30 ++ ldi $0, 0x8000 ++ jmp $31, ($26) ++ nop ++ ++.section .rodata ++/* export the ranges so that ++ VG_(fixup_guest_state_after_syscall_interrupted) can do the ++ right thing */ ++ ++.globl ML_(blksys_setup) ++.globl ML_(blksys_restart) ++.globl ML_(blksys_complete) ++.globl ML_(blksys_committed) ++.globl ML_(blksys_finished) ++/* those numbers are reference tags, NOT number literal */ ++ML_(blksys_setup): .quad 1b ++ML_(blksys_restart): .quad 2b ++ML_(blksys_complete): .quad 3b ++ML_(blksys_committed): .quad 4b ++ML_(blksys_finished): .quad 5b ++ ++#endif // defined(VGP_sw64_linux) ++ ++/* Let the linker know we don't need an executable stack */ ++MARK_STACK_NO_EXEC ++ ++/*--------------------------------------------------------------------*/ ++/*--- end ---*/ ++/*--------------------------------------------------------------------*/ +diff --git a/coregrind/m_syswrap/syswrap-linux.c b/coregrind/m_syswrap/syswrap-linux.c +index 26f1fbee3..c4d6a086f 100644 +--- a/coregrind/m_syswrap/syswrap-linux.c ++++ b/coregrind/m_syswrap/syswrap-linux.c +@@ -310,6 +310,16 @@ static void run_a_thread_NORETURN ( Word tidW ) + : "r" (VgTs_Empty), "n" (__NR_exit), "m" (tst->os_state.exitcode) + : "memory" , "$t4", "$a0" + ); ++#elif defined(VGP_sw64_linux) ++ asm volatile ( ++ "stw %1, %0 \n\t" /* set tst->status = VgTs_Empty (32-bit store) */ ++ "ldi $0, %2 \n\t" /* set v0 = __NR_exit */ ++ "ldl $16,%3 \n\t" /* set r16 = tst->os_state.exitcode */ ++ "sys_call 0x83 \n\t" /* exit(tst->os_state.exitcode) */ ++ "nop" ++ : "=m" (tst->status) ++ : "r" (VgTs_Empty), "n" (__NR_exit), "m" (tst->os_state.exitcode) ++ ); + #else + # error Unknown platform + #endif +@@ -535,6 +545,14 @@ static SysRes clone_new_thread ( Word (*fn)(void *), + (ML_(start_thread_NORETURN), stack, flags, ctst, + child_tidptr, parent_tidptr, NULL); + res = VG_ (mk_SysRes_nanomips_linux) (ret); ++#elif defined(VGP_sw64_linux) ++ ULong v0 = 0; ++ ctst->arch.vex.guest_r0 = 0; ++ ctst->arch.vex.guest_r19 = 0; ++ v0 = do_syscall_clone_sw64_linux ++ (ML_(start_thread_NORETURN), stack, flags, ctst, ++ parent_tidptr, NULL, child_tidptr); ++ res = VG_(mk_SysRes_sw64_linux)(v0, 0, 0); + #else + # error Unknown platform + #endif +@@ -597,6 +615,8 @@ static SysRes setup_child_tls (ThreadId ctid, Addr tlsaddr) + #elif defined(VGP_mips32_linux) || defined(VGP_nanomips_linux) + ctst->arch.vex.guest_ULR = tlsaddr; + ctst->arch.vex.guest_r27 = tlsaddr; ++#elif defined(VGP_sw64_linux) ++ ctst->arch.vex.guest_TID = tlsaddr; + #else + # error Unknown platform + #endif +@@ -759,9 +779,10 @@ static SysRes ML_(do_fork_clone) ( ThreadId tid, UInt flags, + res = VG_(do_syscall5)( __NR_clone, flags, + (UWord)NULL, (UWord)parent_tidptr, + (UWord)NULL, (UWord)child_tidptr ); +-#elif defined(VGP_amd64_linux) ++#elif defined(VGP_amd64_linux) || defined(VGP_sw64_linux) + /* note that the last two arguments are the opposite way round to x86 and + ppc32 as the amd64 kernel expects the arguments in a different order */ ++ /* also sw_64 */ + res = VG_(do_syscall5)( __NR_clone, flags, + (UWord)NULL, (UWord)parent_tidptr, + (UWord)child_tidptr, (UWord)NULL ); +@@ -828,7 +849,7 @@ PRE(sys_clone) + #define PRA_CHILD_TIDPTR PRA5 + #define ARG_TLS ARG4 + #define PRA_TLS PRA4 +-#elif defined(VGP_amd64_linux) || defined(VGP_s390x_linux) ++#elif defined(VGP_amd64_linux) || defined(VGP_s390x_linux) || defined(VGP_sw64_linux) + #define ARG_CHILD_TIDPTR ARG4 + #define PRA_CHILD_TIDPTR PRA4 + #define ARG_TLS ARG5 +@@ -4248,7 +4269,7 @@ POST(sys_sigpending) + // conditional compilation like this?) + #if defined(VGP_x86_linux) || defined(VGP_ppc32_linux) \ + || defined(VGP_arm_linux) || defined(VGP_mips32_linux) \ +- || defined(VGP_nanomips_linux) ++ || defined(VGP_nanomips_linux) || defined(VGP_sw64_linux) + PRE(sys_sigprocmask) + { + vki_old_sigset_t* set; +@@ -4435,9 +4456,12 @@ PRE(sys_rt_sigaction) + PRE_MEM_READ( "rt_sigaction(act->sa_handler)", (Addr)&sa->ksa_handler, sizeof(sa->ksa_handler)); + PRE_MEM_READ( "rt_sigaction(act->sa_mask)", (Addr)&sa->sa_mask, sizeof(sa->sa_mask)); + PRE_MEM_READ( "rt_sigaction(act->sa_flags)", (Addr)&sa->sa_flags, sizeof(sa->sa_flags)); ++ #if !defined(VGP_sw64_linux) ++ // TODO(Shaohua): Read mem + if (ML_(safe_to_deref)(sa,sizeof(vki_sigaction_toK_t)) + && (sa->sa_flags & VKI_SA_RESTORER)) + PRE_MEM_READ( "rt_sigaction(act->sa_restorer)", (Addr)&sa->sa_restorer, sizeof(sa->sa_restorer)); ++ #endif + } + if (ARG3 != 0) + PRE_MEM_WRITE( "rt_sigaction(oldact)", ARG3, sizeof(vki_sigaction_fromK_t)); +@@ -6790,7 +6814,8 @@ POST(sys_lookup_dcookie) + #endif + + #if defined(VGP_amd64_linux) || defined(VGP_s390x_linux) \ +- || defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) ++ || defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) \ ++ || defined(VGP_sw64_linux) + PRE(sys_lookup_dcookie) + { + *flags |= SfMayBlock; +@@ -7084,6 +7109,9 @@ PRE(sys_ioctl) + case VKI_FIOCLEX: + case VKI_FIONCLEX: + case VKI_TIOCNOTTY: ++#if defined(VGP_sw64_linux) ++ case VKI_TIOCGPTPEER: ++#endif + + /* linux perf_event ioctls */ + case VKI_PERF_EVENT_IOC_ENABLE: +@@ -10449,6 +10477,10 @@ POST(sys_ioctl) + break; + case VKI_TIOCNOTTY: + break; ++#if defined(VGP_sw64_linux) ++ case VKI_TIOCGPTPEER: ++ break; ++#endif + case VKI_FIOASYNC: + break; + case VKI_FIONREAD: /* identical to SIOCINQ */ +diff --git a/coregrind/m_syswrap/syswrap-main.c b/coregrind/m_syswrap/syswrap-main.c +index 4f8c0fe1c..514fa90b6 100644 +--- a/coregrind/m_syswrap/syswrap-main.c ++++ b/coregrind/m_syswrap/syswrap-main.c +@@ -70,6 +70,7 @@ + mips32 v0 a0 a1 a2 a3 stack stack n/a n/a v0 (== NUM) + mips64 v0 a0 a1 a2 a3 a4 a5 a6 a7 v0 (== NUM) + arm64 x8 x0 x1 x2 x3 x4 x5 n/a n/a x0 ?? (== ARG1??) ++ sw64 v0 a0 a1 a2 a3 a4 a5 n/a n/a v0 (== NUM) + + FreeBSD: + x86 eax +4 +8 +12 +16 +20 +24 +28 +32 edx:eax, eflags.c +@@ -703,6 +704,19 @@ void getSyscallArgsFromGuestState ( /*OUT*/SyscallArgs* canonical, + canonical->arg6 = gst->guest_r9; // a5 + canonical->arg7 = gst->guest_r10; // a6 + canonical->arg8 = gst->guest_r11; // a7 ++ ++#elif defined(VGP_sw64_linux) ++ VexGuestSW64State* gst = (VexGuestSW64State*)gst_vanilla; ++ canonical->sysno = gst->guest_r0; ++ canonical->arg1 = gst->guest_r16; ++ canonical->arg2 = gst->guest_r17; ++ canonical->arg3 = gst->guest_r18; ++ canonical->arg4 = gst->guest_r19; ++ canonical->arg5 = gst->guest_r20; ++ canonical->arg6 = gst->guest_r21; ++ canonical->arg7 = 0; ++ canonical->arg8 = 0; ++ + #elif defined(VGP_x86_darwin) + VexGuestX86State* gst = (VexGuestX86State*)gst_vanilla; + UWord *stack = (UWord *)gst->guest_ESP; +@@ -1126,6 +1140,16 @@ void putSyscallArgsIntoGuestState ( /*IN*/ SyscallArgs* canonical, + gst->guest_r10 = canonical->arg7; + gst->guest_r11 = canonical->arg8; + ++#elif defined(VGP_sw64_linux) ++ VexGuestSW64State* gst = (VexGuestSW64State*)gst_vanilla; ++ gst->guest_r0 = canonical->sysno; ++ gst->guest_r16 = canonical->arg1; ++ gst->guest_r17 = canonical->arg2; ++ gst->guest_r18 = canonical->arg3; ++ gst->guest_r19 = canonical->arg4; ++ gst->guest_r20 = canonical->arg5; ++ gst->guest_r21 = canonical->arg6; ++ + #elif defined(VGP_x86_solaris) + VexGuestX86State* gst = (VexGuestX86State*)gst_vanilla; + UWord *stack = (UWord *)gst->guest_ESP; +@@ -1240,6 +1264,15 @@ void getSyscallStatusFromGuestState ( /*OUT*/SyscallStatus* canonical, + RegWord a0 = gst->guest_r4; // a0 + canonical->sres = VG_(mk_SysRes_nanomips_linux)(a0); + canonical->what = SsComplete; ++ ++# elif defined(VGP_sw64_linux) ++ VexGuestSW64State* gst = (VexGuestSW64State*)gst_vanilla; ++ ULong v0 = gst->guest_r0; // v0 ++ ULong r19 = gst->guest_r19; // r19 ++ ULong r20 = gst->guest_r20; // r20 ++ canonical->sres = VG_(mk_SysRes_sw64_linux)(v0, r19, r20); ++ canonical->what = SsComplete; ++ + # elif defined(VGP_amd64_freebsd) + /* duplicates logic in m_signals.VG_UCONTEXT_SYSCALL_SYSRES */ + VexGuestAMD64State* gst = (VexGuestAMD64State*)gst_vanilla; +@@ -1606,6 +1639,23 @@ void putSyscallStatusIntoGuestState ( /*IN*/ ThreadId tid, + VG_TRACK( post_reg_write, Vg_CoreSysCall, tid, + OFFSET_mips32_r4, sizeof(UWord) ); + ++# elif defined(VGP_sw64_linux) ++ VexGuestSW64State* gst = (VexGuestSW64State*)gst_vanilla; ++ vg_assert(canonical->what == SsComplete); ++ if (sr_isError(canonical->sres)) { ++ gst->guest_r0 = (Long)sr_Err(canonical->sres); ++ gst->guest_r19 = (Long) 1; ++ } else { ++ gst->guest_r0 = sr_Res(canonical->sres); ++ gst->guest_r19 = 0; ++ } ++ VG_TRACK( post_reg_write, Vg_CoreSysCall, tid, ++ OFFSET_sw64_r0, sizeof(UWord) ); ++ VG_TRACK( post_reg_write, Vg_CoreSysCall, tid, ++ OFFSET_sw64_r19, sizeof(UWord) ); ++ /* sw64: Not all syscall will touch r20, keep r20 unchanged. ++ If a special syscall do that, write gst->guest_r20 in post handler */ ++ + # elif defined(VGP_x86_solaris) + VexGuestX86State* gst = (VexGuestX86State*)gst_vanilla; + SysRes sres = canonical->sres; +@@ -1798,6 +1848,17 @@ void getSyscallArgLayout ( /*OUT*/SyscallArgLayout* layout ) + layout->o_arg7 = OFFSET_mips64_r10; + layout->o_arg8 = OFFSET_mips64_r11; + ++#elif defined(VGP_sw64_linux) ++ layout->o_sysno = OFFSET_sw64_r0; ++ layout->o_arg1 = OFFSET_sw64_r16; ++ layout->o_arg2 = OFFSET_sw64_r17; ++ layout->o_arg3 = OFFSET_sw64_r18; ++ layout->o_arg4 = OFFSET_sw64_r19; ++ layout->o_arg5 = OFFSET_sw64_r20; ++ layout->o_arg6 = OFFSET_sw64_r21; ++ layout->uu_arg7 = -1; /* impossible value */ ++ layout->uu_arg8 = -1; /* impossible value */ ++ + #elif defined(VGP_x86_darwin) + layout->o_sysno = OFFSET_x86_EAX; + // syscall parameters are on stack in C convention +@@ -2899,6 +2960,26 @@ void ML_(fixup_guest_state_to_restart_syscall) ( ThreadArchState* arch ) + arch->vex.guest_PC -= 2; + } + } ++ ++#elif defined(VGP_sw64_linux) ++ /* Make sure our caller is actually sane, and we're really backing ++ back over a syscall. ++ syscall (w/o barrier) == 83 00 00 02 ++ syscall (with barrier) == 83 00 00 00 ++ */ ++ { ++ arch->vex.guest_PC -= 4; // sizeof(sw64 instr) ++ UChar *p = (UChar *)arch->vex.guest_PC; ++ if (p[0] != 0x83 || p[1] != 0x00 || p[2] != 0x00 || (p[3] != 0x02 && p[3] != 0x00)) ++ VG_(message)( ++ Vg_DebugMsg, ++ "?! restarting over syscall at %#llx %02x %02x %02x %02x\n", ++ arch->vex.guest_PC, p[0], p[1], p[2], p[3] ++ ); ++ ++ vg_assert(p[0] == 0x83 && p[1] == 0x00 && p[2] == 0x00 && (p[3] == 0x02 || p[3] == 0x00)); ++ } ++ + #elif defined(VGP_x86_solaris) + arch->vex.guest_EIP -= 2; // sizeof(int $0x91) or sizeof(syscall) + +diff --git a/coregrind/m_syswrap/syswrap-sw64-linux.c b/coregrind/m_syswrap/syswrap-sw64-linux.c +new file mode 100644 +index 000000000..80db0fbd9 +--- /dev/null ++++ b/coregrind/m_syswrap/syswrap-sw64-linux.c +@@ -0,0 +1,973 @@ ++ ++/*--------------------------------------------------------------------*/ ++/*--- Platform-specific syscalls stuff. syswrap-sw64-linux.c ----*/ ++/*--------------------------------------------------------------------*/ ++ ++/* ++ This file is part of Valgrind, a dynamic binary instrumentation ++ framework. ++ ++ Copyright (C) 2010-2017 RT-RK ++ ++ This program is free software; you can redistribute it and/or ++ modify it under the terms of the GNU General Public License as ++ published by the Free Software Foundation; either version 2 of the ++ License, or (at your option) any later version. ++ ++ This program is distributed in the hope that it will be useful, but ++ WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with this program; if not, see . ++ ++ The GNU General Public License is contained in the file COPYING. ++*/ ++ ++#if defined(VGP_sw64_linux) ++#include "libvex_guest_offsets.h" ++#include "pub_core_basics.h" ++#include "pub_core_vki.h" ++#include "pub_core_vkiscnums.h" ++#include "pub_core_threadstate.h" ++#include "pub_core_aspacemgr.h" ++#include "pub_core_debuglog.h" ++#include "pub_core_libcbase.h" ++#include "pub_core_libcassert.h" ++#include "pub_core_libcprint.h" ++#include "pub_core_libcproc.h" ++#include "pub_core_libcsignal.h" ++#include "pub_core_options.h" ++#include "pub_core_scheduler.h" ++#include "pub_core_sigframe.h" /* For VG_(sigframe_destroy)() */ ++#include "pub_core_signals.h" ++#include "pub_core_syscall.h" ++#include "pub_core_syswrap.h" ++#include "pub_core_tooliface.h" ++#include "pub_core_transtab.h" /* VG_(discard_translations) */ ++#include "priv_types_n_macros.h" ++#include "priv_syswrap-generic.h" /* for decls of generic wrappers */ ++#include "priv_syswrap-linux.h" /* for decls of linux-ish wrappers */ ++#include "priv_syswrap-main.h" ++ ++#include "pub_core_debuginfo.h" /* VG_(di_notify_*) */ ++#include "pub_core_xarray.h" ++#include "pub_core_clientstate.h" /* VG_(brk_base), VG_(brk_limit) */ ++#include "pub_core_errormgr.h" ++#include "pub_core_gdbserver.h" /* VG_(gdbserver) */ ++#include "pub_core_libcfile.h" ++#include "pub_core_machine.h" /* VG_(get_SP) */ ++#include "pub_core_mallocfree.h" ++#include "pub_core_stacktrace.h" /* For VG_(get_and_pp_StackTrace)() */ ++#include "pub_core_ume.h" ++ ++#include "config.h" ++ ++#include ++ ++/* --------------------------------------------------------------------- ++ clone() handling ++ ------------------------------------------------------------------ */ ++ ++/* Call f(arg1), but first switch stacks, using 'stack' as the new stack, and ++ use 'retaddr' as f's return-to address. Also, clear all the integer registers ++ before entering f. */ ++__attribute__ ((noreturn)) ++void ML_(call_on_new_stack_0_1) ( Addr stack, /* $16 - $a0 */ ++ Addr retaddr, /* $17 - $a1 */ ++ void (*f_desc) (Word), /* $18 - $a2 */ ++ Word arg1 ); /* $19 - $a3 */ ++asm ( ++".text\n" ++".globl vgModuleLocal_call_on_new_stack_0_1\n" ++"vgModuleLocal_call_on_new_stack_0_1:\n" ++" mov $16, $30\n" /* set stack */ ++" mov $19, $16\n" /* arg1 to $16 */ ++" mov $18, $27\n" ++" mov $17, $26\n" /* retaddr to $ra */ ++" ldi $0, 0($31)\n\t" /* zero all GP regs */ ++" ldi $1, 0($31)\n\t" ++" ldi $2, 0($31)\n\t" ++" ldi $3, 0($31)\n\t" ++" ldi $4, 0($31)\n\t" ++" ldi $5, 0($31)\n\t" ++" ldi $6, 0($31)\n\t" ++" ldi $7, 0($31)\n\t" ++" ldi $8, 0($31)\n\t" ++" ldi $9, 0($31)\n\t" ++" ldi $10,0($31)\n\t" ++" ldi $11,0($31)\n\t" ++" ldi $12,0($31)\n\t" ++" ldi $13,0($31)\n\t" ++" ldi $14,0($31)\n\t" ++" ldi $17,0($31)\n\t" ++" ldi $18,0($31)\n\t" ++" ldi $19,0($31)\n\t" ++" ldi $20,0($31)\n\t" ++" ldi $21,0($31)\n\t" ++" ldi $22,0($31)\n\t" ++" ldi $23,0($31)\n\t" ++" ldi $24,0($31)\n\t" ++" ldi $25,0($31)\n\t" ++" mov $30, $15\n\t" ++" jmp $31, ($27)\n" /* jump to f */ ++" halt\n" /* should never get here */ ++".previous\n" ++); ++ ++/* ULong do_syscall_clone_sw64_linux(Word (*fn)(void*), void *stack, Int flags, ++ void *arg, Int *parent_tid, void *tls, ++ Int *child_tid); ++ Perform a clone system call. clone is strange because it has fork()-like ++ return-twice semantics, so it needs special handling here. ++*/ ++asm( ++".text\n" ++".global do_syscall_clone_sw64_linux\n" ++".ent do_syscall_clone_sw64_linux\n" ++"do_syscall_clone_sw64_linux:\n" ++" .cfi_startproc\n" ++ ++" ldi $17, -16($17)\n" /* allocate space on child stack*/ ++" stl $16, 0($17)\n" /* save fn */ ++" stl $19, 8($17)\n" /* save arg*/ ++ ++/* arg of syscalls is clone(flags, usp, ptid, ctid, tls) ++ from /sysdeps/unix/sysv/linux/sw_64/clone.S:61 */ ++" mov $16, $1\n" ++" mov $17, $2\n" ++" mov $18, $3\n" ++" mov $19, $4\n" ++" mov $20, $5\n" ++" mov $21, $6\n" ++" ldl $7, 0($30)\n" ++" mov $3, $16\n" ++" mov $2, $17\n" ++" mov $5, $18\n" ++" mov $7, $19\n" ++" mov $6, $20\n" ++" ldi $0, " VG_STRINGIFY(__NR_clone) "\n" ++" sys_call 0x83\n" ++" bne $19, parent_or_error\n" ++" bne $0, parent_or_error\n" ++ ++/* CHILD - call thread function, then call to exit() */ ++" ldl $27, 0($30)\n" /* pop fn */ ++" ldl $16, 8($30)\n" /* pop arg */ ++" ldi $30, 16($30)\n" ++ ++" call $26, ($27), 0\n" /* call to funcion */ ++ ++" mov $0, $16\n" /* call to exit() */ ++" ldi $0, " VG_STRINGIFY(__NR_exit) "\n" ++" sys_call 0x83\n" ++ ++/* PARENT or ERROR - return */ ++"parent_or_error:\n" ++" ret $31, ($26), 0\n" ++ ++" .cfi_endproc\n" ++".end do_syscall_clone_sw64_linux\n" ++); ++ ++/* --------------------------------------------------------------------- ++ More thread stuff ++ ------------------------------------------------------------------ */ ++void VG_(cleanup_thread) ( ThreadArchState * arch ) { }; ++ ++// SysRes sys_set_tls ( ThreadId tid, Addr tlsptr ) ++// { ++// /* SW_NOT_COMPLETE */ ++// } ++ ++/* --------------------------------------------------------------------- ++ PRE/POST wrappers for sw/Linux-specific syscalls ++ ------------------------------------------------------------------ */ ++ ++#define PRE(name) DEFN_PRE_TEMPLATE(sw64_linux, name) ++#define POST(name) DEFN_POST_TEMPLATE(sw64_linux, name) ++ ++/* Add prototypes for the wrappers declared here, so that gcc doesn't harass us ++ for not having prototypes. Really this is a kludge -- the right thing to do ++ is to make these wrappers 'static' since they aren't visible outside this ++ file, but that requires even more macro magic. */ ++ ++DECL_TEMPLATE(sw64_linux, sys_ptrace); // 26 ++DECL_TEMPLATE(sw64_linux, sys_pipe); // 42 ++DECL_TEMPLATE(sw64_linux, sys_odd_sigprocmask); // 48 ++DECL_TEMPLATE(sw64_linux, sys_mmap); // 71 ++DECL_TEMPLATE(sw64_linux, sys_gethostname); // 87 ++DECL_TEMPLATE(sw64_linux, sys_sethostname); // 88 ++DECL_TEMPLATE(sw64_linux, sys_sigreturn); // 103 ++DECL_TEMPLATE(sw64_linux, sys_sigsuspend); // 111 ++DECL_TEMPLATE(sw64_linux, sys_setdomainname); // 166 ++DECL_TEMPLATE(sw64_linux, sys_sysfs); // 254 ++DECL_TEMPLATE(sw64_linux, sys_getsysinfo); // 256 ++DECL_TEMPLATE(sw64_linux, sys_setsysinfo); // 257 ++DECL_TEMPLATE(sw64_linux, sys_swapoff); // 304 ++DECL_TEMPLATE(sw64_linux, sys_reboot); // 311 ++DECL_TEMPLATE(sw64_linux, sys_swapon); // 322 ++DECL_TEMPLATE(sw64_linux, sys_ustat); // 327 ++DECL_TEMPLATE(sw64_linux, sys_sched_rr_get_interval); // 337 ++DECL_TEMPLATE(sw64_linux, sys_rt_sigreturn); // 351 ++DECL_TEMPLATE(sw64_linux, sys_fadvise64); // 413 ++DECL_TEMPLATE(sw64_linux, sys_stat64); // 425 ++DECL_TEMPLATE(sw64_linux, sys_lstat64); // 426 ++DECL_TEMPLATE(sw64_linux, sys_fstat64); // 427 ++DECL_TEMPLATE(sw64_linux, sys_fstatat64); // 455 ++DECL_TEMPLATE(sw64_linux, sys_vmsplice); // 471 ++ ++PRE(sys_ptrace) ++{ ++ PRINT("sys_ptrace ( %ld, %ld, %#" FMT_REGWORD "x, %#" FMT_REGWORD "x )", ++ SARG1, SARG2, ARG3, ARG4); ++ PRE_REG_READ4(int, "ptrace", ++ long, request, long, pid, unsigned long, addr, ++ unsigned long, data); ++ switch (ARG1) { ++ case VKI_PTRACE_PEEKTEXT: ++ case VKI_PTRACE_PEEKDATA: ++ case VKI_PTRACE_PEEKUSR: ++ PRE_MEM_WRITE("ptrace(peek)", ARG4, sizeof(long)); ++ break; ++ case VKI_PTRACE_GETEVENTMSG: ++ PRE_MEM_WRITE("ptrace(geteventmsg)", ARG4, sizeof(unsigned long)); ++ break; ++ case VKI_PTRACE_GETSIGINFO: ++ PRE_MEM_WRITE("ptrace(getsiginfo)", ARG4, sizeof(vki_siginfo_t)); ++ break; ++ case VKI_PTRACE_SETSIGINFO: ++ PRE_MEM_READ("ptrace(setsiginfo)", ARG4, sizeof(vki_siginfo_t)); ++ break; ++ case VKI_PTRACE_GETREGSET: ++ ML_(linux_PRE_getregset)(tid, ARG3, ARG4); ++ break; ++ default: ++ break; ++ } ++} ++POST(sys_ptrace) ++{ ++ switch (ARG1) { ++ case VKI_PTRACE_TRACEME: ++ ML_(linux_POST_traceme)(tid); ++ break; ++ case VKI_PTRACE_PEEKTEXT: ++ case VKI_PTRACE_PEEKDATA: ++ case VKI_PTRACE_PEEKUSR: ++ POST_MEM_WRITE (ARG4, sizeof(long)); ++ break; ++ case VKI_PTRACE_GETEVENTMSG: ++ POST_MEM_WRITE (ARG4, sizeof(unsigned long)); ++ break; ++ case VKI_PTRACE_GETSIGINFO: ++ POST_MEM_WRITE (ARG4, sizeof(vki_siginfo_t)); ++ break; ++ case VKI_PTRACE_GETREGSET: ++ ML_(linux_POST_getregset)(tid, ARG3, ARG4); ++ break; ++ default: ++ break; ++ } ++} ++ ++PRE(sys_pipe) ++{ ++ PRINT("sys_pipe ( %#" FMT_REGWORD "x )", ARG1); ++ PRE_REG_READ1(int, "pipe", int *, filedes); ++ PRE_MEM_WRITE( "pipe(filedes)", ARG1, 2*sizeof(int) ); ++} ++POST(sys_pipe) ++{ ++ Int p0, p1; ++ ThreadState *gst; ++ ++ vg_assert(SUCCESS); ++ p0 = sr_Res(status->sres); ++ p1 = sr_ResEx(status->sres); ++ ++ if (!ML_(fd_allowed)(p0, "pipe", tid, True) || ++ !ML_(fd_allowed)(p1, "pipe", tid, True)) { ++ VG_(close)(p0); ++ VG_(close)(p1); ++ SET_STATUS_Failure( VKI_EMFILE ); ++ } else { ++ if (VG_(clo_track_fds)) { ++ ML_(record_fd_open_nameless)(tid, p0); ++ ML_(record_fd_open_nameless)(tid, p1); ++ } ++ } ++ ++ gst = VG_(get_ThreadState)(tid); ++ gst->arch.vex.guest_r20 = p1; ++ VG_TRACK( post_reg_write, Vg_CoreSysCall, tid, ++ OFFSET_sw64_r20, sizeof(UWord) ); ++} ++ ++PRE(sys_odd_sigprocmask) ++{ ++ /* see linux-4.19.y-sw/arch/sw_64/kernel/signal.c ++ SYSCALL_DEFINE2(odd_sigprocmask, int, how, unsigned long, newmask) ++ ++ these code is copy from valgrind-sw/coregrind/m_syswrap/syswrap-linux.c ++ in PRE(sys_sigprocmask) ++ */ ++ vki_old_sigset_t* set; ++ vki_sigset_t bigger_set; ++ ++ PRINT("sys_odd_sigprocmask ( %ld, %#lx )", SARG1, ARG2); ++ PRE_REG_READ2(long, "sys_odd_sigprocmask", ++ int, how, vki_old_sigset_t *, set); ++ if (ARG2 != 0) ++ PRE_MEM_READ( "sigprocmask(set)", ARG2, sizeof(vki_old_sigset_t)); ++ ++ // Nb: We must convert the smaller vki_old_sigset_t params into bigger ++ // vki_sigset_t params. ++ set = (vki_old_sigset_t*)(Addr)ARG2; ++ ++ VG_(memset)(&bigger_set, 0, sizeof(vki_sigset_t)); ++ if (set) ++ bigger_set.sig[0] = *(vki_old_sigset_t*)set; ++ ++ SET_STATUS_from_SysRes( ++ VG_(do_sys_sigprocmask) ( tid, ++ ARG1 /*how*/, ++ set ? &bigger_set : NULL, /*set*/ ++ NULL) ++ ); ++ ++ if (SUCCESS) ++ *flags |= SfPollAfter; ++} ++ ++PRE(sys_mmap) ++{ ++ SysRes r; ++ PRINT("sys_mmap ( %#" FMT_REGWORD "x, %" FMT_REGWORD "u, %ld, %ld, %ld, %" ++ FMT_REGWORD "u )", ++ ARG1, ARG2, SARG3, SARG4, SARG5, ARG6); ++ PRE_REG_READ6(long, "mmap", unsigned long, start, vki_size_t, length, ++ int, prot, int, flags, int, fd, unsigned long, offset); ++ r = ML_(generic_PRE_sys_mmap)(tid, ARG1, ARG2, ARG3, ARG4, ARG5, ++ (Off64T) ARG6); ++ SET_STATUS_from_SysRes(r); ++} ++ ++PRE(sys_gethostname) ++{ ++ PRINT ("sys_gethostname ( %#" FMT_REGWORD "x, %ld )", ARG1, SARG2); ++ PRE_REG_READ2 (long, "gethostname", void *, name, int, len); ++} ++ ++PRE(sys_sethostname) ++{ ++ PRINT ("sys_sethostname ( %#" FMT_REGWORD "x, %ld )", ARG1, SARG2); ++ PRE_REG_READ2 (long, "sethostname", const void *, name, int, len); ++} ++ ++PRE(sys_sigreturn) ++{ ++ /* See comments on PRE(sys_rt_sigreturn) in syswrap-s390x-linux.c for ++ an explanation of what follows. */ ++ ThreadState* tst; ++ PRINT("sys_rt_sigreturn ( )"); ++ ++ vg_assert(VG_(is_valid_tid)(tid)); ++ vg_assert(tid >= 1 && tid < VG_N_THREADS); ++ vg_assert(VG_(is_running_thread)(tid)); ++ ++ tst = VG_(get_ThreadState)(tid); ++ ++ /* This is only so that the IA is (might be) useful to report if ++ something goes wrong in the sigreturn */ ++ ML_(fixup_guest_state_to_restart_syscall)(&tst->arch); ++ ++ /* Restore register state from frame and remove it */ ++ VG_(sigframe_destroy)(tid, False); ++ ++ /* Tell the driver not to update the guest state with the "result", ++ and set a bogus result to keep it happy. */ ++ *flags |= SfNoWriteResult; ++ SET_STATUS_Success(0); ++ ++ /* Check to see if any signals arose as a result of this. */ ++ *flags |= SfPollAfter; ++} ++ ++/* NB: This is an almost identical clone of versions for x86-linux and ++ arm-linux, which are themselves literally identical. */ ++PRE(sys_sigsuspend) ++{ ++ /* The C library interface to sigsuspend just takes a pointer to ++ a signal mask but this system call only takes the first word of ++ the signal mask as an argument so only 32 signals are supported. ++ ++ In fact glibc normally uses rt_sigsuspend if it is available as ++ that takes a pointer to the signal mask so supports more signals. ++ */ ++ *flags |= SfMayBlock; ++ PRINT("sys_sigsuspend ( %lu )", ARG1 ); ++ PRE_REG_READ1(int, "sigsuspend", vki_old_sigset_t, mask); ++} ++ ++PRE(sys_setdomainname) ++{ ++ PRINT ("sys_setdomainname ( %#" FMT_REGWORD "x, %ld )", ARG1, SARG2); ++ PRE_REG_READ2 (long, "setdomainname", const void *, name, int, len); ++} ++ ++PRE(sys_sysfs) ++{ ++ PRINT("sys_sysfs ( %ld, %#" FMT_REGWORD "x, %#" FMT_REGWORD "x )", ++ SARG1, ARG2, ARG3); ++ PRE_REG_READ3(long, "sysfs", int, flags, int, desc, const void *, path); ++} ++ ++PRE(sys_swapoff) ++{ ++ PRINT("sys_swapoff ( %#" FMT_REGWORD "x )", ARG1); ++ PRE_REG_READ1(long, "swapoff", const void *, path); ++} ++ ++PRE(sys_reboot) ++{ ++ PRINT("sys_reboot ( %ld, %" FMT_REGWORD "u, %" FMT_REGWORD "u, %#" ++ FMT_REGWORD "x )", SARG1, ARG2, ARG3, ARG4); ++ // An approximation. ARG4 is only read conditionally by the kernel ++ PRE_REG_READ4(int, "reboot", ++ int, magic1, int, magic2, unsigned int, cmd, ++ void *, arg); ++ ++ *flags |= SfMayBlock; ++} ++ ++PRE(sys_swapon) ++{ ++ PRINT("sys_swapon ( %#" FMT_REGWORD "x, %#" FMT_REGWORD "x )", ARG1, ARG2); ++ PRE_REG_READ2(long, "swapon", const void *, path, int, flags); ++} ++ ++PRE(sys_ustat) ++{ ++ PRINT("sys_ustat ( %#" FMT_REGWORD "x, %#" FMT_REGWORD "x)", ARG1, ARG2); ++ PRE_REG_READ2(long, "ustat", int, flags, const void *, path); ++} ++ ++PRE(sys_sched_rr_get_interval) ++{ ++ PRINT("sys_sched_rr_get_interval ( %ld, %#" FMT_REGWORD "x)", SARG1, ARG2); ++ PRE_REG_READ2(long, "sched_rr_get_interval", vki_pid_t, pid, ++ struct timespec *, timer); ++ *flags |= SfMayBlock; ++} ++ ++PRE(sys_rt_sigreturn) ++{ ++ /* See comments on PRE(sys_rt_sigreturn) in syswrap-s390x-linux.c for ++ an explanation of what follows. */ ++ ThreadState* tst; ++ PRINT("sys_rt_sigreturn ( )"); ++ ++ vg_assert(VG_(is_valid_tid)(tid)); ++ vg_assert(tid >= 1 && tid < VG_N_THREADS); ++ vg_assert(VG_(is_running_thread)(tid)); ++ ++ tst = VG_(get_ThreadState)(tid); ++ ++ /* This is only so that the IA is (might be) useful to report if ++ something goes wrong in the sigreturn */ ++ ML_(fixup_guest_state_to_restart_syscall)(&tst->arch); ++ ++ /* Restore register state from frame and remove it */ ++ VG_(sigframe_destroy)(tid, True); ++ ++ /* Tell the driver not to update the guest state with the "result", ++ and set a bogus result to keep it happy. */ ++ *flags |= SfNoWriteResult; ++ SET_STATUS_Success(0); ++ ++ /* Check to see if any signals arose as a result of this. */ ++ *flags |= SfPollAfter; ++} ++ ++PRE(sys_fadvise64) ++{ ++ PRINT("sys_fadvise64 ( %ld, %ld, %" FMT_REGWORD "u, %ld )", SARG1, SARG2, ++ ARG3, SARG4); ++ PRE_REG_READ4(long, "fadvise64", ++ int, fd, vki_loff_t, offset, vki_loff_t, len, int, advice); ++} ++ ++PRE(sys_stat64) ++{ ++ PRINT("sys_stat64 ( %#lx(%s), %#lx )",ARG1,(char*)ARG1,ARG2); ++ PRE_REG_READ2(long, "stat64", char *, file_name, struct stat64 *, buf); ++ PRE_MEM_RASCIIZ( "stat64(file_name)", ARG1 ); ++ PRE_MEM_WRITE( "stat64(buf)", ARG2, sizeof(struct vki_stat64) ); ++} ++ ++POST(sys_stat64) ++{ ++ POST_MEM_WRITE( ARG2, sizeof(struct vki_stat64) ); ++} ++ ++PRE(sys_lstat64) ++{ ++ PRINT("sys_lstat64 ( %#lx(%s), %#lx )",ARG1,(char*)ARG1,ARG2); ++ PRE_REG_READ2(long, "lstat64", char *, file_name, struct stat64 *, buf); ++ PRE_MEM_RASCIIZ( "lstat64(file_name)", ARG1 ); ++ PRE_MEM_WRITE( "lstat64(buf)", ARG2, sizeof(struct vki_stat64) ); ++} ++ ++POST(sys_lstat64) ++{ ++ vg_assert(SUCCESS); ++ if (RES == 0) { ++ POST_MEM_WRITE( ARG2, sizeof(struct vki_stat64) ); ++ } ++} ++ ++PRE(sys_fstat64) ++{ ++ PRINT("sys_fstat64 ( %lx, %#lx )",ARG1,ARG2); ++ PRE_REG_READ2(long, "fstat64", unsigned long, fd, struct stat64 *, buf); ++ PRE_MEM_WRITE( "fstat64(buf)", ARG2, sizeof(struct vki_stat64) ); ++} ++ ++POST(sys_fstat64) ++{ ++ POST_MEM_WRITE( ARG2, sizeof(struct vki_stat64) ); ++} ++ ++PRE(sys_fstatat64) ++{ ++ // ARG4 = int flags; Flags are or'ed together, therefore writing them ++ // as a hex constant is more meaningful. ++ PRINT("sys_fstatat64 ( %ld, %#lx(%s), %#lx, %#lx )", ++ SARG1, ARG2, (HChar*)ARG2, ARG3, ARG4); ++ PRE_REG_READ4(long, "fstatat64", ++ int, dfd, char *, file_name, struct stat64 *, buf, int, flags); ++ PRE_MEM_RASCIIZ ("fstatat64(file_name)", ARG2); ++ PRE_MEM_WRITE ("fstatat64(buf)", ARG3, sizeof (struct vki_stat64)); ++} ++POST(sys_fstatat64) ++{ ++ POST_MEM_WRITE (ARG3, sizeof (struct vki_stat64)); ++} ++ ++PRE(sys_vmsplice) ++{ ++ PRINT("sys_vmsplice ( %ld, %#" FMT_REGWORD "x, %" FMT_REGWORD "u, %ld )", ++ SARG1, ARG2, ARG3, SARG4); ++ PRE_REG_READ4(long, "sys_vmsplice", int, fdin, struct vki_iovec *, v, ++ vki_size_t, len, int, flags); ++} ++ ++// SYSCALL_DEFINE5(getsysinfo, unsigned long, op, void __user *, buffer, ++// unsigned long, nbytes, int __user *, start, void __user *, arg); ++PRE(sys_getsysinfo) ++{ ++ PRINT("sys_getsysinfo ( %ld, %#lx, %ld, %#lx, %#lx )", ++ SARG1, ARG2, SARG3, ARG4, ARG5); ++ PRE_REG_READ5(long, "sys_getsysinfo", unsigned long, op, void *, buffer, ++ unsigned long, nbytes, int *, start, void *, arg); ++} ++ ++POST(sys_getsysinfo) ++{ ++ POST_MEM_WRITE (ARG2, sizeof (unsigned long)); ++} ++ ++// SYSCALL_DEFINE5(setsysinfo, unsigned long, op, void __user *, buffer, ++// unsigned long, nbytes, int __user *, start, void __user *, arg) ++PRE(sys_setsysinfo) ++{ ++ PRINT("sys_setsysinfo ( %ld, %#lx, %ld, %#lx, %#lx )", ++ SARG1, ARG2, SARG3, ARG4, ARG5); ++ PRE_REG_READ5(long, "sys_setsysinfo", unsigned long, op, void *, buffer, ++ unsigned long, nbytes, int *, start, void *, arg); ++} ++ ++#undef PRE ++#undef POST ++ ++/* --------------------------------------------------------------------- ++ The sw64/Linux syscall table ++ ------------------------------------------------------------------ */ ++ ++/* Add an sw64-linux specific wrapper to a syscall table. */ ++#define PLAX_(sysno, name) WRAPPER_ENTRY_X_(sw64_linux, sysno, name) ++#define PLAXY(sysno, name) WRAPPER_ENTRY_XY(sw64_linux, sysno, name) ++ ++static SyscallTableEntry syscall_main_table[] = { ++ GENX_(__NR_exit, sys_exit), // 1 ++ GENX_(__NR_fork, sys_fork), // 2 ++ GENXY(__NR_read, sys_read), // 3 ++ GENX_(__NR_write, sys_write), // 4 ++ GENXY(__NR_close, sys_close), // 6 ++ GENX_(__NR_link, sys_link), // 9 ++ GENX_(__NR_unlink, sys_unlink), // 10 ++ GENX_(__NR_chdir, sys_chdir), // 12 ++ GENX_(__NR_fchdir, sys_fchdir), // 13 ++ GENX_(__NR_mknod, sys_mknod), // 14 ++ GENX_(__NR_chmod, sys_chmod), // 15 ++ GENX_(__NR_chown, sys_chown), // 16 ++ GENX_(__NR_brk, sys_brk), // 17 ++ LINX_(__NR_lseek, sys_lseek), // 19 ++ GENX_(__NR_getxpid, sys_getpid), // 20 ++ LINX_(__NR_umount2, sys_umount), // 22 ++ GENX_(__NR_setuid, sys_setuid), // 23 ++ GENX_(__NR_getxuid, sys_getuid), // 24 ++ PLAXY(__NR_ptrace, sys_ptrace), // 26 ++ GENX_(__NR_access, sys_access), // 33 ++ GENX_(__NR_sync, sys_sync), // 36 ++ GENX_(__NR_kill, sys_kill), // 37 ++ GENX_(__NR_setpgid, sys_setpgid), // 39 ++ GENXY(__NR_dup, sys_dup), // 41 ++ PLAXY(__NR_pipe, sys_pipe), // 42 ++ GENXY(__NR_open, sys_open), // 45 ++ GENX_(__NR_getxgid, sys_getgid), // 47 ++ PLAX_(__NR_odd_sigprocmask, sys_odd_sigprocmask), // 48 ++ GENX_(__NR_acct, sys_acct), // 51 ++ LINXY(__NR_sigpending, sys_sigpending), // 52 ++ LINXY(__NR_ioctl, sys_ioctl), // 54 ++ GENX_(__NR_symlink, sys_symlink), // 57 ++ GENX_(__NR_readlink, sys_readlink), // 58 ++ GENX_(__NR_execve, sys_execve), // 59 ++ GENX_(__NR_umask, sys_umask), // 60 ++ GENX_(__NR_chroot, sys_chroot), // 61 ++ GENX_(__NR_getpgrp, sys_getpgrp), // 63 ++ GENX_(__NR_vfork, sys_fork), // 66 ++ GENXY(__NR_stat, sys_newstat), // 67 ++ GENXY(__NR_lstat, sys_newlstat), // 68 ++ PLAX_(__NR_mmap, sys_mmap), // 71 ++ GENXY(__NR_munmap, sys_munmap), // 73 ++ GENXY(__NR_mprotect, sys_mprotect), // 74 ++ GENX_(__NR_madvise, sys_madvise), // 75 ++ LINX_(__NR_vhangup, sys_vhangup), // 76 ++ GENXY(__NR_getgroups, sys_getgroups), // 79 ++ GENX_(__NR_setgroups, sys_setgroups), // 80 ++ GENX_(__NR_setpgrp, sys_setpgid), // 82 ++ PLAX_(__NR_gethostname, sys_gethostname), // 87 ++ PLAX_(__NR_sethostname, sys_sethostname), // 88 ++ GENXY(__NR_dup2, sys_dup2), // 90 ++ GENXY(__NR_fstat, sys_newfstat), // 91 ++ LINXY(__NR_fcntl, sys_fcntl), // 92 ++ GENXY(__NR_poll, sys_poll), // 94 ++ GENX_(__NR_fsync, sys_fsync), // 95 ++ GENX_(__NR_setpriority, sys_setpriority), // 96 ++ LINXY(__NR_socket, sys_socket), // 97 ++ LINX_(__NR_connect, sys_connect), // 98 ++ LINXY(__NR_accept, sys_accept), // 99 ++ // _____(__NR_odd_getpriority, sys_unknow), // 100 ++ LINX_(__NR_send, sys_send), // 101 ++ LINXY(__NR_recv, sys_recv), // 102 ++ PLAX_(__NR_sigreturn, sys_sigreturn), // 103 ++ LINX_(__NR_bind, sys_bind), // 104 ++ LINX_(__NR_setsockopt, sys_setsockopt), // 105 ++ LINX_(__NR_listen, sys_listen), // 106 ++ PLAX_(__NR_sigsuspend, sys_sigsuspend), // 111 ++ LINXY(__NR_recvmsg, sys_recvmsg), // 113 ++ LINX_(__NR_sendmsg, sys_sendmsg), // 114 ++ LINXY(__NR_getsockopt, sys_getsockopt), // 118 ++ LINX_(__NR_socketcall, sys_socketcall), // 119 ++ GENXY(__NR_readv, sys_readv), // 120 ++ GENX_(__NR_writev, sys_writev), // 121 ++ GENX_(__NR_fchown, sys_fchown), // 123 ++ GENX_(__NR_fchmod, sys_fchmod), // 124 ++ LINXY(__NR_recvfrom, sys_recvfrom), // 125 ++ GENX_(__NR_setreuid, sys_setreuid), // 126 ++ GENX_(__NR_setregid, sys_setregid), // 127 ++ GENX_(__NR_rename, sys_rename), // 128 ++ GENX_(__NR_truncate, sys_truncate), // 129 ++ GENX_(__NR_ftruncate, sys_ftruncate), // 130 ++ GENX_(__NR_flock, sys_flock), // 131 ++ GENX_(__NR_setgid, sys_setgid), // 132 ++ LINX_(__NR_sendto, sys_sendto), // 133 ++ LINX_(__NR_shutdown, sys_shutdown), // 134 ++ LINXY(__NR_socketpair, sys_socketpair), // 135 ++ GENX_(__NR_mkdir, sys_mkdir), // 136 ++ GENX_(__NR_rmdir, sys_rmdir), // 137 ++ LINXY(__NR_getpeername, sys_getpeername), // 141 ++ GENXY(__NR_getrlimit, sys_getrlimit), // 144 ++ GENX_(__NR_setrlimit, sys_setrlimit), // 145 ++ GENX_(__NR_setsid, sys_setsid), // 147 ++ LINX_(__NR_quotactl, sys_quotactl), // 148 ++ LINXY(__NR_getsockname, sys_getsockname), // 150 ++ LINXY(__NR_sigaction, sys_sigaction), // 156 ++ PLAX_(__NR_setdomainname, sys_setdomainname), // 166 ++ LINXY(__NR_bpf, sys_bpf), // 170 ++ // _____(__NR_userfaultfd, sys_unknow), // 171 ++ LINX_(__NR_membarrier, sys_membarrier), // 172 ++ // _____(__NR_mlock2, sys_unknow), // 173 ++ GENX_(__NR_getpid, sys_getpid), // 174 ++ GENX_(__NR_getppid, sys_getppid), // 175 ++ GENX_(__NR_getuid, sys_getuid), // 176 ++ GENX_(__NR_geteuid, sys_geteuid), // 177 ++ GENX_(__NR_getgid, sys_getgid), // 178 ++ GENX_(__NR_getegid, sys_getegid), // 179 ++ LINXY(__NR_msgctl, sys_msgctl), // 200 ++ LINX_(__NR_msgget, sys_msgget), // 201 ++ LINXY(__NR_msgrcv, sys_msgrcv), // 202 ++ LINX_(__NR_msgsnd, sys_msgsnd), // 203 ++ LINXY(__NR_semctl, sys_semctl), // 204 ++ LINX_(__NR_semget, sys_semget), // 205 ++ LINX_(__NR_semop, sys_semop), // 206 ++ GENX_(__NR_lchown, sys_lchown), // 208 ++ LINXY(__NR_shmat, sys_shmat), // 209 ++ LINXY(__NR_shmctl, sys_shmctl), // 210 ++ LINXY(__NR_shmdt, sys_shmdt), // 211 ++ LINX_(__NR_shmget, sys_shmget), // 212 ++ GENX_(__NR_msync, sys_msync), // 217 ++ GENXY(__NR_statfs64, sys_statfs64), // 229 ++ GENXY(__NR_fstatfs64, sys_fstatfs64), // 230 ++ GENX_(__NR_getpgid, sys_getpgid), // 233 ++ GENX_(__NR_getsid, sys_getsid), // 234 ++ GENXY(__NR_sigaltstack, sys_sigaltstack), // 235 ++ PLAX_(__NR_sysfs, sys_sysfs), // 254 ++ PLAX_(__NR_getsysinfo, sys_getsysinfo), // 256 ++ PLAX_(__NR_setsysinfo, sys_setsysinfo), // 257 ++ GENX_(266, sys_ni_syscall), // 266 ++ GENX_(__NR_getpriority, sys_getpriority), // 298 ++ LINXY(__NR_sigprocmask, sys_sigprocmask), // 299 ++ // _____(__NR_bdflush, sys_unknow), //300 ++ LINX_(__NR_mount, sys_mount), // 302 ++ PLAX_(__NR_swapoff, sys_swapoff), // 304 ++ GENXY(__NR_getdents, sys_getdents), // 305 ++ GENX_(__NR_create_module, sys_ni_syscall), // 306 ++ LINX_(__NR_init_module, sys_init_module), // 307 ++ LINX_(__NR_delete_module, sys_delete_module), // 308 ++ GENX_(__NR_get_kernel_syms, sys_ni_syscall), // 309 ++ LINXY(__NR_syslog, sys_syslog), // 310 ++ PLAX_(__NR_reboot, sys_reboot), // 311 ++ LINX_(__NR_clone, sys_clone), // 312 ++ // _____(__NR_uselib, sys_unknow), // 313 ++ GENX_(__NR_mlock, sys_mlock), // 314 ++ GENX_(__NR_munlock, sys_munlock), // 315 ++ GENX_(__NR_mlockall, sys_mlockall), // 316 ++ LINX_(__NR_munlockall, sys_munlockall), // 317 ++ LINXY(__NR_sysinfo, sys_sysinfo), // 318 ++ LINXY(__NR__sysctl, sys_sysctl), // 319 ++ LINX_(__NR_oldumount, sys_oldumount), // 321 ++ PLAX_(__NR_swapon, sys_swapon), // 322 ++ GENXY(__NR_times, sys_times), // 323 ++ LINX_(__NR_personality, sys_personality), // 324 ++ LINX_(__NR_setfsuid, sys_setfsuid), // 325 ++ LINX_(__NR_setfsgid, sys_setfsgid), // 326 ++ PLAX_(__NR_ustat, sys_ustat), // 327 ++ GENXY(__NR_statfs, sys_statfs), // 328 ++ GENXY(__NR_fstatfs, sys_fstatfs), // 329 ++ LINXY(__NR_sched_setparam, sys_sched_setparam), // 330 ++ LINXY(__NR_sched_getparam, sys_sched_getparam), // 331 ++ LINX_(__NR_sched_setscheduler, sys_sched_setscheduler), // 332 ++ LINX_(__NR_sched_getscheduler, sys_sched_getscheduler), // 333 ++ LINX_(__NR_sched_yield, sys_sched_yield), // 334 ++ LINX_(__NR_sched_get_priority_max, sys_sched_get_priority_max), // 335 ++ LINX_(__NR_sched_get_priority_min, sys_sched_get_priority_min), // 336 ++ PLAX_(__NR_sched_rr_get_interval, sys_sched_rr_get_interval), // 337 ++ GENX_(__NR_afs_syscall, sys_ni_syscall), // 338 ++ GENXY(__NR_uname, sys_newuname), // 339 ++ GENXY(__NR_nanosleep, sys_nanosleep), // 340 ++ GENX_(__NR_mremap, sys_mremap), // 341 ++ GENX_(__NR_nfsservctl, sys_ni_syscall), // 342 ++ LINX_(__NR_setresuid, sys_setresuid), // 343 ++ LINXY(__NR_getresuid, sys_getresuid), // 344 ++ // _____(__NR_pciconfig_read, sys_unknow), // 345 ++ // _____(__NR_pciconfig_write, sys_unknow), // 346 ++ GENX_(__NR_query_module, sys_ni_syscall), // 347 ++ LINXY(__NR_prctl, sys_prctl), // 348 ++ GENXY(__NR_pread64, sys_pread64), // 349 ++ GENX_(__NR_pwrite64, sys_pwrite64), // 350 ++ PLAX_(__NR_rt_sigreturn, sys_rt_sigreturn), // 351 ++ LINXY(__NR_rt_sigaction, sys_rt_sigaction), // 352 ++ LINXY(__NR_rt_sigprocmask, sys_rt_sigprocmask), // 353 ++ LINXY(__NR_rt_sigpending, sys_rt_sigpending), // 354 ++ LINXY(__NR_rt_sigtimedwait, sys_rt_sigtimedwait), // 355 ++ LINXY(__NR_rt_sigqueueinfo, sys_rt_sigqueueinfo), // 356 ++ LINX_(__NR_rt_sigsuspend, sys_rt_sigsuspend), // 357 ++ GENX_(__NR_select, sys_select), // 358 ++ GENXY(__NR_gettimeofday, sys_gettimeofday), // 359 ++ GENX_(__NR_settimeofday, sys_settimeofday), // 360 ++ GENXY(__NR_getitimer, sys_getitimer), // 361 ++ GENXY(__NR_setitimer, sys_setitimer), // 362 ++ GENX_(__NR_utimes, sys_utimes), // 363 ++ GENXY(__NR_getrusage, sys_getrusage), // 364 ++ GENXY(__NR_wait4, sys_wait4), // 365 ++ LINXY(__NR_adjtimex, sys_adjtimex), // 366 ++ GENXY(__NR_getcwd, sys_getcwd), // 367 ++ LINXY(__NR_capget, sys_capget), // 368 ++ LINX_(__NR_capset, sys_capset), // 369 ++ LINXY(__NR_sendfile, sys_sendfile), // 370 ++ LINX_(__NR_setresgid, sys_setresgid), // 371 ++ LINXY(__NR_getresgid, sys_getresgid), // 372 ++ GENX_(__NR_dipc, sys_ni_syscall), // 373 ++ LINX_(__NR_pivot_root, sys_pivot_root), // 374 ++ GENXY(__NR_mincore, sys_mincore), // 375 ++ // _____(__NR_pciconfig_iobase, sys_unknow), // 376 ++ GENXY(__NR_getdents64, sys_getdents64), // 377 ++ LINX_(__NR_gettid, sys_gettid), // 378 ++ LINX_(__NR_readahead, sys_readahead), // 379 ++ LINXY(__NR_tkill, sys_tkill), // 381 ++ LINX_(__NR_setxattr, sys_setxattr), // 382 ++ LINX_(__NR_lsetxattr, sys_lsetxattr), // 383 ++ LINX_(__NR_fsetxattr, sys_fsetxattr), // 384 ++ LINXY(__NR_getxattr, sys_getxattr), // 385 ++ LINXY(__NR_lgetxattr, sys_lgetxattr), // 386 ++ LINXY(__NR_fgetxattr, sys_fgetxattr), // 387 ++ LINXY(__NR_listxattr, sys_listxattr), // 388 ++ LINXY(__NR_llistxattr, sys_llistxattr), // 389 ++ LINXY(__NR_flistxattr, sys_flistxattr), // 390 ++ LINX_(__NR_removexattr, sys_removexattr), // 391 ++ LINX_(__NR_lremovexattr, sys_lremovexattr), // 392 ++ LINX_(__NR_fremovexattr, sys_fremovexattr), // 393 ++ LINXY(__NR_futex, sys_futex), // 394 ++ LINX_(__NR_sched_setaffinity, sys_sched_setaffinity), // 395 ++ LINXY(__NR_sched_getaffinity, sys_sched_getaffinity), // 396 ++ GENX_(__NR_tuxcall, sys_ni_syscall), // 397 ++ LINXY(__NR_io_setup, sys_io_setup), // 398 ++ LINX_(__NR_io_destroy, sys_io_destroy), // 399 ++ LINXY(__NR_io_getevents, sys_io_getevents), // 400 ++ LINX_(__NR_io_submit, sys_io_submit), // 401 ++ LINXY(__NR_io_cancel, sys_io_cancel), // 402 ++ // _____(__NR_io_pgetevents, sys_unknow), // 403 ++ GENX_(__NR_rseq, sys_ni_syscall), // 404 ++ LINX_(__NR_exit_group, sys_exit_group), // 405 ++ LINXY(__NR_lookup_dcookie, sys_lookup_dcookie), // 406 ++ LINXY(__NR_epoll_create, sys_epoll_create), // 407 ++ LINX_(__NR_epoll_ctl, sys_epoll_ctl), // 408 ++ LINXY(__NR_epoll_wait, sys_epoll_wait), // 409 ++ // _____(__NR_remap_file_pages, sys_unknow), // 410 ++ LINX_(__NR_set_tid_address, sys_set_tid_address), // 411 ++ // _____(__NR_restart_syscall, sys_unknow), // 412 ++ PLAX_(__NR_fadvise64, sys_fadvise64), // 413 ++ LINXY(__NR_timer_create, sys_timer_create), // 414 ++ LINXY(__NR_timer_settime, sys_timer_settime), // 415 ++ LINXY(__NR_timer_gettime, sys_timer_gettime), // 416 ++ LINX_(__NR_timer_getoverrun, sys_timer_getoverrun), // 417 ++ LINX_(__NR_timer_delete, sys_timer_delete), // 418 ++ LINX_(__NR_clock_settime, sys_clock_settime), // 419 ++ LINXY(__NR_clock_gettime, sys_clock_gettime), // 420 ++ LINXY(__NR_clock_getres, sys_clock_getres), // 421 ++ LINXY(__NR_clock_nanosleep, sys_clock_nanosleep), // 422 ++ LINX_(__NR_semtimedop, sys_semtimedop), // 423 ++ LINX_(__NR_tgkill, sys_tgkill), // 424 ++ PLAXY(__NR_stat64, sys_stat64), // 425 ++ PLAXY(__NR_lstat64, sys_lstat64), // 426 ++ PLAXY(__NR_fstat64, sys_fstat64), // 427 ++ GENX_(__NR_vserver, sys_ni_syscall), // 428 ++ LINX_(__NR_mbind, sys_mbind), // 429 ++ LINXY(__NR_get_mempolicy, sys_get_mempolicy), // 430 ++ LINX_(__NR_set_mempolicy, sys_set_mempolicy), // 431 ++ LINXY(__NR_mq_open, sys_mq_open), // 432 ++ LINX_(__NR_mq_unlink, sys_mq_unlink), // 433 ++ LINX_(__NR_mq_timedsend, sys_mq_timedsend), // 434 ++ LINXY(__NR_mq_timedreceive, sys_mq_timedreceive), // 435 ++ LINX_(__NR_mq_notify, sys_mq_notify), // 436 ++ LINXY(__NR_mq_getsetattr, sys_mq_getsetattr), // 437 ++ LINXY(__NR_waitid, sys_waitid), // 438 ++ LINX_(__NR_add_key, sys_add_key), // 439 ++ LINX_(__NR_request_key, sys_request_key), // 440 ++ LINXY(__NR_keyctl, sys_keyctl), // 441 ++ LINX_(__NR_ioprio_set, sys_ioprio_set), // 442 ++ LINX_(__NR_ioprio_get, sys_ioprio_get), // 443 ++ LINX_(__NR_inotify_init, sys_inotify_init), // 444 ++ LINX_(__NR_inotify_add_watch, sys_inotify_add_watch), // 445 ++ LINX_(__NR_inotify_rm_watch, sys_inotify_rm_watch), // 446 ++ GENX_(__NR_fdatasync, sys_fdatasync), // 447 ++ // _____(__NR_kexec_load, sys_unknow), // 448 ++ // _____(__NR_migrate_pages, sys_unknow), // 449 ++ LINXY(__NR_openat, sys_openat), // 450 ++ LINX_(__NR_mkdirat, sys_mkdirat), // 451 ++ LINX_(__NR_mknodat, sys_mknodat), // 452 ++ LINX_(__NR_fchownat, sys_fchownat), // 453 ++ LINX_(__NR_futimesat, sys_futimesat), // 454 ++ PLAXY(__NR_fstatat64, sys_fstatat64), // 455 ++ LINX_(__NR_unlinkat, sys_unlinkat), // 456 ++ LINX_(__NR_renameat, sys_renameat), // 457 ++ LINX_(__NR_linkat, sys_linkat), // 458 ++ LINX_(__NR_symlinkat, sys_symlinkat), // 459 ++ LINX_(__NR_readlinkat, sys_readlinkat), // 460 ++ LINX_(__NR_fchmodat, sys_fchmodat), // 461 ++ LINX_(__NR_faccessat, sys_faccessat), // 462 ++ LINXY(__NR_pselect6, sys_pselect6), // 463 ++ LINXY(__NR_ppoll, sys_ppoll), // 464 ++ LINX_(__NR_unshare, sys_unshare), // 465 ++ LINX_(__NR_set_robust_list, sys_set_robust_list), // 466 ++ LINXY(__NR_get_robust_list, sys_get_robust_list), // 467 ++ LINX_(__NR_splice, sys_splice), // 468 ++ LINX_(__NR_sync_file_range, sys_sync_file_range), // 469 ++ LINX_(__NR_tee, sys_tee), // 470 ++ PLAX_(__NR_vmsplice, sys_vmsplice), // 471 ++ LINXY(__NR_move_pages, sys_move_pages), // 472 ++ LINXY(__NR_getcpu, sys_getcpu), // 473 ++ LINXY(__NR_epoll_pwait, sys_epoll_pwait), // 474 ++ LINX_(__NR_utimensat, sys_utimensat), // 475 ++ LINXY(__NR_signalfd, sys_signalfd), // 476 ++ GENX_(__NR_timerfd, sys_ni_syscall), // 477 ++ LINXY(__NR_eventfd, sys_eventfd), // 478 ++ LINXY(__NR_recvmmsg, sys_recvmmsg), // 479 ++ LINX_(__NR_fallocate, sys_fallocate), // 480 ++ LINXY(__NR_timerfd_create, sys_timerfd_create), // 481 ++ LINXY(__NR_timerfd_gettime, sys_timerfd_gettime), // 483 ++ LINXY(__NR_timerfd_settime, sys_timerfd_settime), // 482 ++ LINXY(__NR_signalfd4, sys_signalfd4), // 484 ++ LINXY(__NR_eventfd2, sys_eventfd2), // 485 ++ LINXY(__NR_epoll_create1, sys_epoll_create1), // 486 ++ LINXY(__NR_dup3, sys_dup3), // 487 ++ LINXY(__NR_pipe2, sys_pipe2), // 488 ++ LINX_(__NR_inotify_init1, sys_inotify_init1), // 489 ++ LINXY(__NR_preadv, sys_preadv), // 490 ++ LINX_(__NR_pwritev, sys_pwritev), // 491 ++ LINXY(__NR_rt_tgsigqueueinfo, sys_rt_tgsigqueueinfo), // 492 ++ LINXY(__NR_perf_event_open, sys_perf_event_open), // 493 ++ LINXY(__NR_fanotify_init, sys_fanotify_init), // 494 ++ LINX_(__NR_fanotify_mark, sys_fanotify_mark), // 495 ++ LINXY(__NR_prlimit64, sys_prlimit64), // 496 ++ LINXY(__NR_name_to_handle_at, sys_name_to_handle_at), // 497 ++ LINXY(__NR_open_by_handle_at, sys_open_by_handle_at), // 498 ++ LINXY(__NR_clock_adjtime, sys_clock_adjtime), // 499 ++ LINX_(__NR_syncfs, sys_syncfs), // 500 ++ LINX_(__NR_setns, sys_setns), // 501 ++ LINXY(__NR_accept4, sys_accept4), // 502 ++ LINXY(__NR_sendmmsg, sys_sendmmsg), // 503 ++ LINXY(__NR_process_vm_readv, sys_process_vm_readv), // 504 ++ LINX_(__NR_process_vm_writev, sys_process_vm_writev), // 505 ++ LINX_(__NR_kcmp, sys_kcmp), // 506 ++ LINX_(__NR_finit_module, sys_finit_module), // 507 ++ LINX_(__NR_sched_setattr, sys_sched_setattr), // 508 ++ LINXY(__NR_sched_getattr, sys_sched_getattr), // 509 ++ LINX_(__NR_renameat2, sys_renameat2), // 510 ++ LINXY(__NR_getrandom, sys_getrandom), // 511 ++ LINXY(__NR_memfd_create, sys_memfd_create), // 512 ++ LINX_(__NR_execveat, sys_execveat), // 513 ++ // _____(__NR_seccomp, sys_unknow), // 514 ++ LINX_(__NR_copy_file_range, sys_copy_file_range), // 515 ++ LINXY(__NR_preadv2, sys_preadv2), // 516 ++ LINX_(__NR_pwritev2, sys_pwritev2), // 517 ++ LINXY(__NR_statx, sys_statx) // 518 ++}; ++ ++SyscallTableEntry * ML_(get_linux_syscall_entry) ( UInt sysno ) ++{ ++ const UInt syscall_main_table_size ++ = sizeof(syscall_main_table) / sizeof(syscall_main_table[0]); ++ ++ /* Is it in the contiguous initial section of the table? */ ++ if (sysno < syscall_main_table_size) { ++ SyscallTableEntry* sys = &syscall_main_table[sysno]; ++ if (sys->before == NULL) ++ return NULL; /* no entry */ ++ else ++ return sys; ++ } ++ ++ /* Can't find a wrapper */ ++ return NULL; ++} ++ ++#endif /* defined(VGP_sw64_linux) */ ++ ++/*--------------------------------------------------------------------*/ ++/*--- end syswrap-sw64-linux.c ---*/ ++/*--------------------------------------------------------------------*/ +diff --git a/coregrind/m_trampoline.S b/coregrind/m_trampoline.S +index da9697232..0ba6fb849 100644 +--- a/coregrind/m_trampoline.S ++++ b/coregrind/m_trampoline.S +@@ -1520,6 +1520,67 @@ VG_(trampoline_stuff_end): + # undef UD2_1024 + # undef UD2_PAGE + ++/*---------------------- sw64-linux ----------------------*/ ++#else ++#if defined(VGP_sw64_linux) ++ ++.global VG_(trampoline_stuff_start) ++VG_(trampoline_stuff_start): ++ ++/* ref: glibc-2.28-sw/sysdeps/unix/sysv/linux/sw_64/rt_sigaction.S */ ++.global VG_(sw64_linux_SUBST_FOR_rt_sigreturn) ++VG_(sw64_linux_SUBST_FOR_rt_sigreturn): ++ mov $30, $16 ++ ldi $0,__NR_rt_sigreturn ++ sys_call 0x83 ++ nop ++ .long 0 /*illegal insn*/ ++ ++/* There's no particular reason that this needs to be handwritten ++ assembly, but since that's what this file contains, here's a ++ simple index() and strlen() implementations. ++*/ ++ ++.set noat ++.set noreorder ++ ++.global VG_(sw64_linux_REDIR_FOR_index) ++.type VG_(sw64_linux_REDIR_FOR_index), @function ++VG_(sw64_linux_REDIR_FOR_index): ++ mov $16, $0 /* current pos */ ++ and $17, 0xff, $17 /* target character */ ++1: ++ ldbu $1, 0($0) ++ cmpeq $1, $17, $2 ++ bne $2, 3f /* found */ ++ beq $1, 2f /* not found */ ++ ldi $0, 1($0) ++ br $31, 1b /* loop */ ++2: ++ mov $31, $0 ++3: ++ ret $31, ($26), 1 ++ ++.size VG_(sw64_linux_REDIR_FOR_index), .-VG_(sw64_linux_REDIR_FOR_index) ++ ++.global VG_(sw64_linux_REDIR_FOR_strlen) ++.type VG_(sw64_linux_REDIR_FOR_strlen), @function ++VG_(sw64_linux_REDIR_FOR_strlen): ++ mov $16, $0 /* current pos */ ++1: ++ ldbu $1, 0($0) ++ beq $1, 2f /* return */ ++ ldi $0, 1($0) ++ br $31, 1b /* loop */ ++2: ++ subl $0, $16, $0 ++ ret $31, ($26), 1 ++ ++.size VG_(sw64_linux_REDIR_FOR_strlen), .-VG_(sw64_linux_REDIR_FOR_strlen) ++ ++.global VG_(trampoline_stuff_end) ++VG_(trampoline_stuff_end): ++ + /*---------------- x86-solaris ----------------*/ + #else + #if defined(VGP_x86_solaris) +@@ -1699,6 +1760,74 @@ VG_(amd64_solaris_REDIR_FOR_strlen): + .global VG_(trampoline_stuff_end) + VG_(trampoline_stuff_end): + ++/*---------------------- sw_64-linux ----------------------*/ ++#else ++#if defined(VGP_sw_64_linux) ++ ++# define UD2_16 trap ; trap ; trap; trap ++# define UD2_64 UD2_16 ; UD2_16 ; UD2_16 ; UD2_16 ++# define UD2_256 UD2_64 ; UD2_64 ; UD2_64 ; UD2_64 ++# define UD2_1024 UD2_256 ; UD2_256 ; UD2_256 ; UD2_256 ++# define UD2_PAGE UD2_1024 ; UD2_1024 ; UD2_1024 ; UD2_1024 ++ ++.global VG_(trampoline_stuff_start) ++VG_(trampoline_stuff_start): ++ ++.global VG_(sw_64_linux_SUBST_FOR_rt_sigreturn) ++VG_(sw_64_linux_SUBST_FOR_rt_sigreturn): ++ ldi $16,__NR_rt_sigreturn($31) ++ sys_call 0x83 ++ nop ++ .long 0 /*illegal insn*/ ++ ++/* There's no particular reason that this needs to be handwritten ++ assembly, but since that's what this file contains, here's a ++ simple index() and strlen() implementations. ++*/ ++.set noreorder ++ ++.global VG_(sw_64_linux_REDIR_FOR_index) ++ .type VG_(sw_64_linux_REDIR_FOR_index), @function ++ VG_(sw_64_linux_REDIR_FOR_index): ++ mov $16, $18 ++ ldl $1, 0($16) ++ cmpeq $17,$1,$2 ++ beq $2, index_end ++ ++index_loop: ++ addl $18,1,$18 ++ ldl $1, 0($18) ++ cmpeq $17,$1,$2 ++ bne $2, index_loop ++ mov $18, $0 ++ ret $31,($26),1 ++index_end: ++ ldi $0,0($31) ++ ret $31,($26),1 ++.size VG_(sw_64_linux_REDIR_FOR_index), .-VG_(sw_64_linux_REDIR_FOR_index) ++ ++.global VG_(sw_64_linux_REDIR_FOR_strlen) ++ .type VG_(sw_64_linux_REDIR_FOR_strlen), @function ++ VG_(sw_64_linux_REDIR_FOR_strlen): ++ ++ ldl $1, 0($16) ++ beq $1, end ++ ldi $0, 0($31) ++loop: ++ addl $0,1,$0 ++ addl $16,1,$16 ++ ldl $1, 0($16) ++ bne $1, loop ++ ret $31,($26),1 ++end: ++ ldi $0,0($31) ++ ret $31,($26),1 ++ ++.size VG_(sw_64_linux_REDIR_FOR_strlen), .-VG_(sw_64_linux_REDIR_FOR_strlen) ++ ++.global VG_(trampoline_stuff_end) ++VG_(trampoline_stuff_end): ++ + /*---------------- unknown ----------------*/ + #else + # error Unknown platform +@@ -1719,6 +1848,8 @@ VG_(trampoline_stuff_end): + #endif + #endif + #endif ++#endif ++#endif + + /* Let the linker know we don't need an executable stack */ + MARK_STACK_NO_EXEC +diff --git a/coregrind/m_translate.c b/coregrind/m_translate.c +index 8ae06d2a6..0d0d1c2ca 100644 +--- a/coregrind/m_translate.c ++++ b/coregrind/m_translate.c +@@ -1363,6 +1363,13 @@ Bool mk_preamble__set_NRADDR_to_zero ( void* closureV, IRSB* bb ) + VgCallbackClosure* closure = (VgCallbackClosure*)closureV; + Int offB_GPR25 = offsetof(VexGuestMIPS64State, guest_r25); + addStmtToIRSB(bb, IRStmt_Put(offB_GPR25, mkU64(closure->readdr))); ++ // r27 needs to be set to point to the start of the redirected function. ++ // see also in coregrind/m_main.c:2451 ++# endif ++# if defined(VGP_sw64_linux) ++ VgCallbackClosure* closure = (VgCallbackClosure*)closureV; ++ Int offB_GPR27 = offsetof(VexGuestSW64State, guest_r27); ++ addStmtToIRSB(bb, IRStmt_Put(offB_GPR27, mkU64(closure->readdr))); + # endif + # if defined(VG_PLAT_USES_PPCTOC) + { VgCallbackClosure* closure = (VgCallbackClosure*)closureV; +@@ -1423,6 +1430,10 @@ Bool mk_preamble__set_NRADDR_to_nraddr ( void* closureV, IRSB* bb ) + Int offB_GPR25 = offsetof(VexGuestMIPS64State, guest_r25); + addStmtToIRSB(bb, IRStmt_Put(offB_GPR25, mkU64(closure->readdr))); + # endif ++# if defined(VGP_sw64_linux) ++ Int offB_GPR27 = offsetof(VexGuestSW64State, guest_r27); ++ addStmtToIRSB(bb, IRStmt_Put(offB_GPR27, mkU64(closure->readdr))); ++# endif + # if defined(VG_PLAT_USES_PPCTOC) + addStmtToIRSB( + bb, +@@ -1582,7 +1593,7 @@ Bool VG_(translate) ( ThreadId tid, + tid, "(translator)", addr, 1 ); + + /* If doing any code printing, print a basic block start marker */ +- if (VG_(clo_trace_flags) || debugging_translation) { ++ if (VG_(clo_trace_flags) || debugging_translation/*debug logger */) { + const HChar* objname = "UNKNOWN_OBJECT"; + OffT objoff = 0; + const DiEpoch ep = VG_(current_DiEpoch)(); +@@ -1796,6 +1807,7 @@ Bool VG_(translate) ( ThreadId tid, + vta.needs_self_check = needs_self_check; + vta.preamble_function = preamble_fn; + vta.traceflags = verbosity; ++ vta.dump_expansion_ratio = VG_(clo_dump_expansion_ratio); + vta.sigill_diag = VG_(clo_sigill_diag); + vta.addProfInc = VG_(clo_profyle_sbs) && kind != T_NoRedir; + +diff --git a/coregrind/m_vki.c b/coregrind/m_vki.c +index 0cc1882a1..0f2bb59e9 100644 +--- a/coregrind/m_vki.c ++++ b/coregrind/m_vki.c +@@ -43,7 +43,7 @@ + #if defined(VGP_ppc32_linux) || defined(VGP_ppc64be_linux) \ + || defined(VGP_ppc64le_linux) || defined(VGP_arm64_linux) \ + || defined(VGP_mips32_linux) || defined(VGP_mips64_linux) \ +- || defined(VGP_nanomips_linux) ++ || defined(VGP_nanomips_linux) || defined(VGP_sw64_linux) + unsigned long VKI_PAGE_SHIFT = 12; + unsigned long VKI_PAGE_SIZE = 1UL << 12; + #endif +diff --git a/coregrind/pub_core_aspacemgr.h b/coregrind/pub_core_aspacemgr.h +index b867108a2..ecd6a1691 100644 +--- a/coregrind/pub_core_aspacemgr.h ++++ b/coregrind/pub_core_aspacemgr.h +@@ -335,7 +335,8 @@ extern Bool VG_(am_relocate_nooverlap_client)( /*OUT*/Bool* need_discard, + #if defined(VGP_ppc32_linux) \ + || defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) \ + || defined(VGP_mips32_linux) || defined(VGP_mips64_linux) \ +- || defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) ++ || defined(VGP_arm64_linux) || defined(VGP_nanomips_linux) \ ++ || defined(VGP_sw64_linux) + # define VG_STACK_GUARD_SZB 65536 // 1 or 16 pages + #else + # define VG_STACK_GUARD_SZB 8192 // 2 pages +diff --git a/coregrind/pub_core_basics.h b/coregrind/pub_core_basics.h +index abc5a066a..d8d779763 100644 +--- a/coregrind/pub_core_basics.h ++++ b/coregrind/pub_core_basics.h +@@ -102,6 +102,11 @@ typedef + ULong r31; /* Return address of the last subroutine call */ + ULong r28; + } MIPS64; ++ struct { ++ ULong r15; /* fp */ ++ ULong r26; /* ra */ ++ ULong r29; /* gp */ ++ } SW64; + } misc; + } + UnwindStartRegs; +diff --git a/coregrind/pub_core_debuginfo.h b/coregrind/pub_core_debuginfo.h +index 938ed00cc..0f9890825 100644 +--- a/coregrind/pub_core_debuginfo.h ++++ b/coregrind/pub_core_debuginfo.h +@@ -128,6 +128,10 @@ typedef + Addr f4; Addr f5; Addr f6; Addr f7; } + D3UnwindRegs; + #elif defined(VGA_mips32) || defined(VGA_mips64) || defined(VGA_nanomips) ++typedef ++ struct { Addr pc; Addr sp; Addr fp; Addr ra; } ++ D3UnwindRegs; ++#elif defined(VGA_sw64) + typedef + struct { Addr pc; Addr sp; Addr fp; Addr ra; } + D3UnwindRegs; +diff --git a/coregrind/pub_core_initimg.h b/coregrind/pub_core_initimg.h +index cfbd41f8b..7718b9885 100644 +--- a/coregrind/pub_core_initimg.h ++++ b/coregrind/pub_core_initimg.h +@@ -58,7 +58,7 @@ IIFinaliseImageInfo VG_(ii_create_image)( IICreateImageInfo, + starting values. This is handed the IIFinaliseImageInfo created by + VG_(ii_create_image). */ + extern +-void VG_(ii_finalise_image)( IIFinaliseImageInfo ); ++void VG_(ii_finalise_image)( IIFinaliseImageInfo, IICreateImageInfo ); + + /* Note that both IICreateImageInfo and IIFinaliseImageInfo are + OS-specific. We now go on to give instantiations of them +diff --git a/coregrind/pub_core_machine.h b/coregrind/pub_core_machine.h +index a9b7dd8b1..e9319ae88 100644 +--- a/coregrind/pub_core_machine.h ++++ b/coregrind/pub_core_machine.h +@@ -126,6 +126,11 @@ + # define VG_ELF_MACHINE EM_NANOMIPS + # define VG_ELF_CLASS ELFCLASS32 + # undef VG_PLAT_USES_PPCTOC ++#elif defined(VGP_sw64_linux) ++# define VG_ELF_DATA2XXX ELFDATA2LSB ++# define VG_ELF_MACHINE EM_SW_64 ++# define VG_ELF_CLASS ELFCLASS64 ++# undef VG_PLAT_USES_PPCTOC + #else + # error Unknown platform + #endif +@@ -163,6 +168,10 @@ + # define VG_INSTR_PTR guest_PC + # define VG_STACK_PTR guest_r29 + # define VG_FRAME_PTR guest_r30 ++#elif defined(VGA_sw64) ++# define VG_INSTR_PTR guest_PC ++# define VG_STACK_PTR guest_r30 ++# define VG_FRAME_PTR guest_r15 + #else + # error Unknown arch + #endif +diff --git a/coregrind/pub_core_mallocfree.h b/coregrind/pub_core_mallocfree.h +index b5922ca50..61dcaf435 100644 +--- a/coregrind/pub_core_mallocfree.h ++++ b/coregrind/pub_core_mallocfree.h +@@ -83,6 +83,7 @@ typedef Int ArenaId; + defined(VGP_x86_darwin) || \ + defined(VGP_amd64_darwin) || \ + defined(VGP_arm64_linux) || \ ++ defined(VGP_sw64_linux) || \ + defined(VGP_amd64_solaris) + # define VG_MIN_MALLOC_SZB 16 + #else +diff --git a/coregrind/pub_core_options.h b/coregrind/pub_core_options.h +index e949311af..d1d1742da 100644 +--- a/coregrind/pub_core_options.h ++++ b/coregrind/pub_core_options.h +@@ -188,6 +188,8 @@ extern ULong VG_(clo_profyle_interval); + extern Int VG_(clo_trace_notbelow); + /* DEBUG: if tracing codegen, be quiet after this bb */ + extern Int VG_(clo_trace_notabove); ++/* DEBUG: print register after sched, defualt: NO */ ++extern Int VG_(clo_trace_reg); + /* DEBUG: print system calls? default: NO */ + extern Bool VG_(clo_trace_syscalls); + /* DEBUG: print signal details? default: NO */ +@@ -204,6 +206,8 @@ extern Bool VG_(clo_debug_dump_syms); + extern Bool VG_(clo_debug_dump_line); + /* DEBUG: mimic /usr/bin/readelf --debug-dump=frames? default: NO */ + extern Bool VG_(clo_debug_dump_frames); ++/* Show instruction expansion ratio. default: NO */ ++extern Bool VG_(clo_dump_expansion_ratio); + /* DEBUG: print redirection details? default: NO */ + extern Bool VG_(clo_trace_redir); + /* Enable fair scheduling on multicore systems? default: NO */ +diff --git a/coregrind/pub_core_scheduler.h b/coregrind/pub_core_scheduler.h +index d74eb0629..f8e5bf96a 100644 +--- a/coregrind/pub_core_scheduler.h ++++ b/coregrind/pub_core_scheduler.h +@@ -110,6 +110,9 @@ extern void VG_(force_vgdb_poll) ( void ); + /* Stats ... */ + extern void VG_(print_scheduler_stats) ( void ); + ++/* States */ ++extern void VG_(print_guest_state) ( void * vex_ptr ); ++ + /* If False, a fault is Valgrind-internal (ie, a bug) */ + extern Bool VG_(in_generated_code); + +diff --git a/coregrind/pub_core_syscall.h b/coregrind/pub_core_syscall.h +index 6c4f82591..6709e8f9b 100644 +--- a/coregrind/pub_core_syscall.h ++++ b/coregrind/pub_core_syscall.h +@@ -105,6 +105,7 @@ extern SysRes VG_(mk_SysRes_mips32_linux)( UWord v0, UWord v1, + extern SysRes VG_(mk_SysRes_mips64_linux)( ULong v0, ULong v1, + ULong a3 ); + extern SysRes VG_(mk_SysRes_nanomips_linux)( UWord a0); ++extern SysRes VG_(mk_SysRes_sw64_linux)( ULong v0, ULong r19, ULong r20 ); + extern SysRes VG_(mk_SysRes_x86_solaris) ( Bool isErr, UInt val, UInt val2 ); + extern SysRes VG_(mk_SysRes_amd64_solaris) ( Bool isErr, ULong val, ULong val2 ); + extern SysRes VG_(mk_SysRes_Error) ( UWord val ); +diff --git a/coregrind/pub_core_trampoline.h b/coregrind/pub_core_trampoline.h +index 54c575a72..42d6f88a2 100644 +--- a/coregrind/pub_core_trampoline.h ++++ b/coregrind/pub_core_trampoline.h +@@ -171,6 +171,12 @@ extern Char* VG_(nanomips_linux_REDIR_FOR_index)( const Char*, Int ); + extern UInt VG_(nanomips_linux_REDIR_FOR_strlen)( void* ); + #endif + ++#if defined(VGP_sw64_linux) ++extern Addr VG_(sw64_linux_SUBST_FOR_rt_sigreturn); ++extern Char* VG_(sw64_linux_REDIR_FOR_index)( const Char*, Int ); ++extern UInt VG_(sw64_linux_REDIR_FOR_strlen)( void* ); ++#endif ++ + #if defined(VGP_x86_solaris) + extern SizeT VG_(x86_solaris_REDIR_FOR_strcmp)(const HChar *, const HChar *); + extern SizeT VG_(x86_solaris_REDIR_FOR_strlen)(const HChar *); +diff --git a/coregrind/pub_core_transtab.h b/coregrind/pub_core_transtab.h +index 6cc11f658..95152ebff 100644 +--- a/coregrind/pub_core_transtab.h ++++ b/coregrind/pub_core_transtab.h +@@ -81,7 +81,8 @@ static inline UWord VG_TT_FAST_HASH ( Addr guest ) { + } + + #elif defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le) \ +- || defined(VGA_mips32) || defined(VGA_mips64) || defined(VGA_arm64) ++ || defined(VGA_mips32) || defined(VGA_mips64) || defined(VGA_arm64) \ ++ || defined(VGA_sw64) + static inline UWord VG_TT_FAST_HASH ( Addr guest ) { + // Instructions are 4-byte aligned. + UWord merged = ((UWord)guest) >> 2; +diff --git a/coregrind/pub_core_transtab_asm.h b/coregrind/pub_core_transtab_asm.h +index 8b585f17d..e4761c2e7 100644 +--- a/coregrind/pub_core_transtab_asm.h ++++ b/coregrind/pub_core_transtab_asm.h +@@ -83,7 +83,7 @@ + #if defined(VGA_amd64) || defined(VGA_arm64) \ + || defined(VGA_ppc64be) || defined(VGA_ppc64le) \ + || (defined(VGA_mips64) && defined(VGABI_64)) \ +- || defined(VGA_s390x) ++ || defined(VGA_s390x) || defined(VGA_sw64) + // And all other 64-bit hosts + # define VG_FAST_CACHE_SET_BITS 6 + // These FCS_{g,h}{0,1,2,3} are the values of +diff --git a/coregrind/vgdb-invoker-ptrace.c b/coregrind/vgdb-invoker-ptrace.c +index 78a6a168c..7cce16491 100644 +--- a/coregrind/vgdb-invoker-ptrace.c ++++ b/coregrind/vgdb-invoker-ptrace.c +@@ -874,6 +874,9 @@ Bool invoker_invoke_gdbserver (pid_t pid) + sp = p[29]; + #elif defined(VGA_mips64) + sp = user_mod.regs[29]; ++#elif defined(VGA_sw64) ++ //user defined in sys/user.h ++ sp = user_mod.regs[30]; + #else + I_die_here : (sp) architecture missing in vgdb-invoker-ptrace.c + #endif +@@ -961,6 +964,8 @@ Bool invoker_invoke_gdbserver (pid_t pid) + + #elif defined(VGA_mips64) + assert(0); // cannot vgdb a 32 bits executable with a 64 bits exe ++#elif defined(VGA_sw64) ++ assert(0); // cannot vgdb a 32 bits executable with a 64 bits exe + #else + I_die_here : architecture missing in vgdb-invoker-ptrace.c + #endif +@@ -1068,6 +1073,8 @@ Bool invoker_invoke_gdbserver (pid_t pid) + user_mod.regs[31] = bad_return; + user_mod.regs[34] = shared64->invoke_gdbserver; + user_mod.regs[25] = shared64->invoke_gdbserver; ++#elif defined(VGA_sw64) ++ /* TODO(Shaohua): SW_NOT_COMPLETE */ + #else + I_die_here: architecture missing in vgdb-invoker-ptrace.c + #endif +diff --git a/drd/drd_bitmap.h b/drd/drd_bitmap.h +index 3b71d749a..7f8cea5dd 100644 +--- a/drd/drd_bitmap.h ++++ b/drd/drd_bitmap.h +@@ -140,7 +140,8 @@ Addr make_address(const UWord a1, const UWord a0) + #define BITS_PER_BITS_PER_UWORD 5 + #elif defined(VGA_amd64) || defined(VGA_ppc64be) || defined(VGA_ppc64le) \ + || defined(VGA_s390x) || (defined(VGA_mips64) && !defined(VGABI_N32)) \ +- || defined(VGA_arm64) ++ || defined(VGA_arm64) || defined(VGA_tilegx) || defined(VGA_sw64) ++/* TODO(Shaohua): SW_NOT_COMPLETE */ + #define BITS_PER_BITS_PER_UWORD 6 + #else + #error Unknown platform. +diff --git a/drd/drd_load_store.c b/drd/drd_load_store.c +index fba1dac71..3665b3fc3 100644 +--- a/drd/drd_load_store.c ++++ b/drd/drd_load_store.c +@@ -53,6 +53,8 @@ + #define STACK_POINTER_OFFSET OFFSET_mips32_r29 + #elif defined(VGA_mips64) + #define STACK_POINTER_OFFSET OFFSET_mips64_r29 ++#elif defined(VGA_sw64) ++#define STACK_POINTER_OFFSET OFFSET_sw64_r30 + #else + #error Unknown architecture. + #endif +diff --git a/drd/drd_main.c b/drd/drd_main.c +index 2161e0316..588cc4fd5 100644 +--- a/drd/drd_main.c ++++ b/drd/drd_main.c +@@ -459,6 +459,21 @@ static void DRD_(suppress_relocation_conflicts)(const Addr a, const SizeT len) + DRD_(start_suppression)(avma, avma + size, ".plt"); + } + ++ /* ++ * Same as above, for some architecture (e.g. sw_64) place some ++ * global variable in .sbss instead of .bss ++ */ ++ avma = VG_(DebugInfo_get_sbss_avma)(di); ++ size = VG_(DebugInfo_get_sbss_size)(di); ++ tl_assert((avma && size) || (avma == 0 && size == 0)); ++ if (size > 0 && ++ VG_(strcmp)(VG_(DebugInfo_get_soname)(di), "libpthread.so.0") == 0) { ++ if (trace_sectsuppr) ++ VG_(dmsg)("Suppressing .sbss @ 0x%lx size %lu\n", avma, size); ++ tl_assert(VG_(DebugInfo_sect_kind)(NULL, avma) == Vg_SectBSS); ++ DRD_(start_suppression)(avma, avma + size, ".sbss"); ++ } ++ + avma = VG_(DebugInfo_get_gotplt_avma)(di); + size = VG_(DebugInfo_get_gotplt_size)(di); + tl_assert((avma && size) || (avma == 0 && size == 0)); +diff --git a/drd/tests/Makefile.am b/drd/tests/Makefile.am +index 7ea83cbf7..04feb1f6f 100755 +--- a/drd/tests/Makefile.am ++++ b/drd/tests/Makefile.am +@@ -309,6 +309,7 @@ EXTRA_DIST = \ + tc04_free_lock.stderr.exp-x86 \ + tc04_free_lock.stderr.exp-ppc \ + tc04_free_lock.stderr.exp-s390 \ ++ tc04_free_lock.stderr.exp-sw64 \ + tc04_free_lock.vgtest \ + tc05_simple_race.stderr.exp \ + tc05_simple_race.vgtest \ +@@ -327,6 +328,7 @@ EXTRA_DIST = \ + tc09_bad_unlock.stderr.exp-solaris \ + tc09_bad_unlock.stderr.exp-freebsd \ + tc09_bad_unlock.stderr.exp-freebsd-clang \ ++ tc09_bad_unlock.stderr.exp-sw64 \ + tc09_bad_unlock.vgtest \ + tc10_rec_lock.stderr.exp \ + tc10_rec_lock.vgtest \ +diff --git a/drd/tests/tc04_free_lock.stderr.exp-sw64 b/drd/tests/tc04_free_lock.stderr.exp-sw64 +new file mode 100644 +index 000000000..a22ea5ee9 +--- /dev/null ++++ b/drd/tests/tc04_free_lock.stderr.exp-sw64 +@@ -0,0 +1,26 @@ ++ ++Destroying locked mutex: mutex 0x........, recursion count 1, owner 1. ++ at 0x........: free (vg_replace_malloc.c:...) ++ by 0x........: main (tc04_free_lock.c:24) ++mutex 0x........ was first observed at: ++ at 0x........: pthread_mutex_init (drd_pthread_intercepts.c:?) ++ by 0x........: main (tc04_free_lock.c:20) ++ ++Destroying locked mutex: mutex 0x........, recursion count 1, owner 1. ++ at 0x........: bar (tc04_free_lock.c:40) ++ by 0x........: (below main) ++mutex 0x........ was first observed at: ++ at 0x........: pthread_mutex_lock (drd_pthread_intercepts.c:?) ++ by 0x........: bar (tc04_free_lock.c:38) ++ by 0x........: main (tc04_free_lock.c:26) ++ ++Destroying locked mutex: mutex 0x........, recursion count 1, owner 1. ++ at 0x........: foo (tc04_free_lock.c:49) ++ by 0x........: (below main) ++mutex 0x........ was first observed at: ++ at 0x........: pthread_mutex_init (drd_pthread_intercepts.c:?) ++ by 0x........: foo (tc04_free_lock.c:46) ++ by 0x........: main (tc04_free_lock.c:27) ++ ++ ++ERROR SUMMARY: 4 errors from 3 contexts (suppressed: 0 from 0) +diff --git a/drd/tests/tc09_bad_unlock.stderr.exp-sw64 b/drd/tests/tc09_bad_unlock.stderr.exp-sw64 +new file mode 100644 +index 000000000..06e322b04 +--- /dev/null ++++ b/drd/tests/tc09_bad_unlock.stderr.exp-sw64 +@@ -0,0 +1,51 @@ ++ ++Mutex not locked by calling thread: mutex 0x........, recursion count 0, owner 1. ++ at 0x........: pthread_mutex_unlock (drd_pthread_intercepts.c:?) ++ by 0x........: nearly_main (tc09_bad_unlock.c:28) ++ by 0x........: main (tc09_bad_unlock.c:52) ++mutex 0x........ was first observed at: ++ at 0x........: pthread_mutex_init (drd_pthread_intercepts.c:?) ++ by 0x........: nearly_main (tc09_bad_unlock.c:24) ++ by 0x........: main (tc09_bad_unlock.c:52) ++ ++Thread 2: ++Mutex not locked by calling thread: mutex 0x........, recursion count 1, owner 1. ++ at 0x........: pthread_mutex_unlock (drd_pthread_intercepts.c:?) ++ by 0x........: child_fn (tc09_bad_unlock.c:12) ++ by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) ++mutex 0x........ was first observed at: ++ at 0x........: pthread_mutex_init (drd_pthread_intercepts.c:?) ++ by 0x........: nearly_main (tc09_bad_unlock.c:32) ++ by 0x........: main (tc09_bad_unlock.c:52) ++ ++Thread 1: ++The object at address 0x........ is not a mutex. ++ at 0x........: pthread_mutex_unlock (drd_pthread_intercepts.c:?) ++ by 0x........: nearly_main (tc09_bad_unlock.c:43) ++ by 0x........: main (tc09_bad_unlock.c:52) ++ ++Destroying locked mutex: mutex 0x........, recursion count 1, owner 1. ++ at 0x........: nearly_main (tc09_bad_unlock.c:48) ++ by 0x........: (below main) ++mutex 0x........ was first observed at: ++ at 0x........: pthread_mutex_init (drd_pthread_intercepts.c:?) ++ by 0x........: nearly_main (tc09_bad_unlock.c:32) ++ by 0x........: main (tc09_bad_unlock.c:52) ++ ++--------------------- ++Mutex not locked by calling thread: mutex 0x........, recursion count 0, owner 1. ++ at 0x........: pthread_mutex_unlock (drd_pthread_intercepts.c:?) ++ by 0x........: nearly_main (tc09_bad_unlock.c:28) ++ by 0x........: main (tc09_bad_unlock.c:53) ++mutex 0x........ was first observed at: ++ at 0x........: pthread_mutex_init (drd_pthread_intercepts.c:?) ++ by 0x........: nearly_main (tc09_bad_unlock.c:24) ++ by 0x........: main (tc09_bad_unlock.c:53) ++ ++The object at address 0x........ is not a mutex. ++ at 0x........: pthread_mutex_unlock (drd_pthread_intercepts.c:?) ++ by 0x........: nearly_main (tc09_bad_unlock.c:43) ++ by 0x........: main (tc09_bad_unlock.c:53) ++ ++ ++ERROR SUMMARY: 8 errors from 6 contexts (suppressed: 0 from 0) +diff --git a/gdbserver_tests/Makefile.am b/gdbserver_tests/Makefile.am +index fbcb6596d..ccbfbd85e 100755 +--- a/gdbserver_tests/Makefile.am ++++ b/gdbserver_tests/Makefile.am +@@ -29,6 +29,7 @@ EXTRA_DIST = \ + hgtls.stderr.exp \ + hgtls.stdinB.gdb \ + hgtls.stdoutB.exp \ ++ hgtls.stdoutB.exp-sw64 \ + hgtls.vgtest \ + mcblocklistsearch.stderr.exp \ + mcblocklistsearch.stdinB.gdb \ +@@ -151,6 +152,7 @@ EXTRA_DIST = \ + nlvgdbsigqueue.stderr.exp \ + nlvgdbsigqueue.stdinB.gdb \ + nlvgdbsigqueue.stdoutB.exp \ ++ nlvgdbsigqueue.stdoutB.exp-sw64 \ + nlvgdbsigqueue.stdoutB.exp-solaris1 \ + nlvgdbsigqueue.stdoutB.exp-solaris2 + +diff --git a/gdbserver_tests/hgtls.stdinB.gdb b/gdbserver_tests/hgtls.stdinB.gdb +index 2541e9ea4..db165fc97 100644 +--- a/gdbserver_tests/hgtls.stdinB.gdb ++++ b/gdbserver_tests/hgtls.stdinB.gdb +@@ -34,4 +34,6 @@ continue + end + # continue till the end + continue ++continue ++continue + quit +diff --git a/gdbserver_tests/hgtls.stdoutB.exp-sw64 b/gdbserver_tests/hgtls.stdoutB.exp-sw64 +new file mode 100644 +index 000000000..0b5c9ae46 +--- /dev/null ++++ b/gdbserver_tests/hgtls.stdoutB.exp-sw64 +@@ -0,0 +1,45 @@ ++Breakpoint 1 at 0x........: file tls.c, line 55. ++Continuing. ++Breakpoint 1, tls_ptr (p=0x........) at tls.c:55 ++55 int here = 0; ++test race tls_ip 0x........ ip 0x........ equal 1 ++Breakpoint 1, tls_ptr (p=0x........) at tls.c:55 ++55 int here = 0; ++test race tls_ip 0x........ ip 0x........ equal 1 ++Breakpoint 1, tls_ptr (p=0x........) at tls.c:55 ++55 int here = 0; ++Continuing. ++Breakpoint 1, tls_ptr (p=0x........) at tls.c:55 ++55 int here = 0; ++Continuing. ++Breakpoint 1, tls_ptr (p=0x........) at tls.c:55 ++55 int here = 0; ++test global tls_ip 0x........ ip 0x........ equal 1 ++Breakpoint 1, tls_ptr (p=0x........) at tls.c:55 ++55 int here = 0; ++test global tls_ip 0x........ ip 0x........ equal 1 ++Breakpoint 1, tls_ptr (p=0x........) at tls.c:55 ++55 int here = 0; ++test static_extern tls_ip 0x........ ip 0x........ equal 1 ++Breakpoint 1, tls_ptr (p=0x........) at tls.c:55 ++55 int here = 0; ++test static_extern tls_ip 0x........ ip 0x........ equal 1 ++Breakpoint 1, tls_ptr (p=0x........) at tls.c:55 ++55 int here = 0; ++test so_extern tls_ip 0x........ ip 0x........ equal 1 ++Breakpoint 1, tls_ptr (p=0x........) at tls.c:55 ++55 int here = 0; ++test so_extern tls_ip 0x........ ip 0x........ equal 1 ++Breakpoint 1, tls_ptr (p=0x........) at tls.c:55 ++55 int here = 0; ++test so_local tls_ip 0x........ ip 0x........ equal 1 ++Breakpoint 1, tls_ptr (p=0x........) at tls.c:55 ++55 int here = 0; ++test so_local tls_ip 0x........ ip 0x........ equal 1 ++Breakpoint 1, tls_ptr (p=0x........) at tls.c:55 ++55 int here = 0; ++test so_global tls_ip 0x........ ip 0x........ equal 1 ++Breakpoint 1, tls_ptr (p=0x........) at tls.c:55 ++55 int here = 0; ++test so_global tls_ip 0x........ ip 0x........ equal 1 ++Program exited normally. +diff --git a/gdbserver_tests/nlcontrolc.vgtest b/gdbserver_tests/nlcontrolc.vgtest +index 09edfcaba..3ae8eafed 100644 +--- a/gdbserver_tests/nlcontrolc.vgtest ++++ b/gdbserver_tests/nlcontrolc.vgtest +@@ -13,7 +13,7 @@ args: 1000000000 0 100000 BSBSBSBS 1 + vgopts: --tool=none --vgdb=yes --vgdb-error=0 --vgdb-prefix=./vgdb-prefix-nlcontrolc + stderr_filter: filter_stderr + # Bug 338633 nlcontrol hangs on arm64 currently. +-prereq: test -e gdb -a -f vgdb.invoker && ! ../tests/os_test solaris ++prereq: test -e gdb -a -f vgdb.invoker && ! ../tests/os_test solaris && ! ../tests/arch_test sw64 + progB: gdb + argsB: --quiet -l 60 --nx ./sleepers + stdinB: nlcontrolc.stdinB.gdb +diff --git a/gdbserver_tests/nlvgdbsigqueue.stderr.exp b/gdbserver_tests/nlvgdbsigqueue.stderr.exp +index 52b10c9db..b63a9a988 100644 +--- a/gdbserver_tests/nlvgdbsigqueue.stderr.exp ++++ b/gdbserver_tests/nlvgdbsigqueue.stderr.exp +@@ -3,7 +3,7 @@ Nulgrind, the minimal Valgrind tool + (action at startup) vgdb me ... + + +-loops/sleep_ms/burn/threads_spec/affinity: 1000000000 1000000000 1 BSBSBSBS 1 ++loops/sleep_ms/burn/threads_spec/affinity: 1000000000 0 100000 BSBSBSBS 1 + Brussels ready to sleep and/or burn + London ready to sleep and/or burn + Petaouchnok ready to sleep and/or burn +diff --git a/gdbserver_tests/nlvgdbsigqueue.stdoutB.exp-sw64 b/gdbserver_tests/nlvgdbsigqueue.stdoutB.exp-sw64 +new file mode 100644 +index 000000000..eef4b2001 +--- /dev/null ++++ b/gdbserver_tests/nlvgdbsigqueue.stdoutB.exp-sw64 +@@ -0,0 +1,19 @@ ++continuing to have vgdb interrupted by simulate_control_c ++Continuing. ++Program received signal SIGTRAP, Trace/breakpoint trap. ++do_burn () at sleepers.c:40 ++40 for (i = 0; i < burn; i++) loopnr++; ++attachedwaitingforsigusr1 ++sending signal ++sending signal ++continuing to receive first SIGUSR1 ++Continuing. ++Program received signal SIGUSR1, User defined signal 1. ++do_burn () at sleepers.c:40 ++40 for (i = 0; i < burn; i++) loopnr++; ++continuing to receive second SIGUSR1 ++Continuing. ++Program received signal SIGTRAP, Trace/breakpoint trap. ++do_burn () at sleepers.c:40 ++40 for (i = 0; i < burn; i++) loopnr++; ++Kill the program being debugged? (y or n) [answered Y; input not from terminal] +diff --git a/gdbserver_tests/nlvgdbsigqueue.vgtest b/gdbserver_tests/nlvgdbsigqueue.vgtest +index 877568211..7b9437bdc 100644 +--- a/gdbserver_tests/nlvgdbsigqueue.vgtest ++++ b/gdbserver_tests/nlvgdbsigqueue.vgtest +@@ -3,7 +3,7 @@ + # vgdb must queue these signals and deliver them before PTRACE_DETACHing. + # sleepers is started with argument so that it will mostly sleep. + prog: sleepers +-args: 1000000000 1000000000 1 BSBSBSBS 1 ++args: 1000000000 0 100000 BSBSBSBS 1 + vgopts: --tool=none --vgdb=yes --vgdb-error=0 --vgdb-prefix=./vgdb-prefix-nlvgdbsigqueue + stderr_filter: filter_stderr + prereq: test -e gdb -a -f vgdb.invoker +diff --git a/helgrind/tests/Makefile.am b/helgrind/tests/Makefile.am +index 5338ea4d6..139c15564 100755 +--- a/helgrind/tests/Makefile.am ++++ b/helgrind/tests/Makefile.am +@@ -125,6 +125,7 @@ EXTRA_DIST = \ + tc20_verifywrap.stderr.exp-mips32-b \ + tc20_verifywrap.stderr.exp-s390x \ + tc20_verifywrap.stderr.exp-solaris \ ++ tc20_verifywrap.stderr.exp-sw64 \ + tc21_pthonce.vgtest tc21_pthonce.stdout.exp tc21_pthonce.stderr.exp \ + tc22_exit_w_lock.vgtest tc22_exit_w_lock.stdout.exp \ + tc22_exit_w_lock.stderr.exp \ +diff --git a/helgrind/tests/annotate_hbefore.c b/helgrind/tests/annotate_hbefore.c +index 259d3b64c..3e7cb179c 100644 +--- a/helgrind/tests/annotate_hbefore.c ++++ b/helgrind/tests/annotate_hbefore.c +@@ -314,6 +314,37 @@ UWord do_acasW ( UWord* addr, UWord expected, UWord nyu ) + return success; + } + ++#elif defined(VGA_sw64) ++ ++// sw64 ++/* return 1 if success, 0 if failure */ ++UWord do_acasW ( UWord* addr, UWord expected, UWord nyu ) ++{ ++ UWord succ, cmp, prev; ++ ++ __asm__ __volatile__( ++ "0: lldl %[prev], 0(%[addr])\n" ++ " cmpeq %[prev], %[exp], %[cmp]\n" ++ " wr_f %[cmp]\n" ++ " mov %[nyu], %[succ]\n" ++ " lstl %[succ], 0(%[addr])\n" ++ " rd_f %[succ]\n" ++ " beq %[cmp], 1f\n" ++ " beq %[succ], 0b\n" ++ "1:\n" ++ : [succ] "=&r"(succ), ++ [prev] "=&r"(prev), ++ [cmp] "=&r"(cmp) ++ : [nyu] "r"(nyu), ++ [addr] "r"(addr), ++ [exp] "r"(expected) ++ : "memory" ++ ); ++ ++ assert(succ == 0 || succ == 1); ++ return succ; ++} ++ + #endif + + void atomic_incW ( UWord* w ) +diff --git a/helgrind/tests/tc07_hbl1.c b/helgrind/tests/tc07_hbl1.c +index 54297dee6..d2958377e 100644 +--- a/helgrind/tests/tc07_hbl1.c ++++ b/helgrind/tests/tc07_hbl1.c +@@ -18,6 +18,7 @@ + #undef PLAT_arm64_linux + #undef PLAT_s390x_linux + #undef PLAT_mips32_linux ++#undef PLAT_sw64_linux + #undef PLAT_x86_solaris + #undef PLAT_amd64_solaris + +@@ -47,6 +48,8 @@ + # define PLAT_mips32_linux 1 + #elif defined(__linux__) && defined(__nanomips__) + # define PLAT_nanomips_linux 1 ++#elif defined(__linux__) && defined(__sw_64__) ++# define PLAT_sw64_linux 1 + #elif defined(__sun__) && defined(__i386__) + # define PLAT_x86_solaris 1 + #elif defined(__sun__) && defined(__x86_64__) +@@ -131,6 +134,22 @@ + : /*out*/ : /*in*/ "r"(&(_lval)) \ + : /*trash*/ "$t0", "$t1", "memory" \ + ) ++#elif defined(PLAT_sw64_linux) ++# define INC(_lval,_lqual) \ ++ __asm__ __volatile__ ( \ ++ "0:\n" \ ++ " lldw $5, 0(%0)\n" \ ++ " ldi $8, 1\n" \ ++ " wr_f $8\n" \ ++ " addw $5, 1, $5\n" \ ++ " memb \n" \ ++ " lstw $5, 0(%0)\n" \ ++ " rd_f $5\n" \ ++ " beq $5, 0b\n" \ ++ : /*out*/ \ ++ : /*in*/ "r"(&(_lval)) \ ++ : /*trash*/ "$5", "$8", "memory" \ ++ ) + #else + # error "Fix Me for this platform" + #endif +diff --git a/helgrind/tests/tc08_hbl2.c b/helgrind/tests/tc08_hbl2.c +index c3a2ec794..e82c44cd4 100644 +--- a/helgrind/tests/tc08_hbl2.c ++++ b/helgrind/tests/tc08_hbl2.c +@@ -35,6 +35,7 @@ + #undef PLAT_s390x_linux + #undef PLAT_mips32_linux + #undef PLAT_mips64_linux ++#undef PLAT_sw64_linux + #undef PLAT_x86_solaris + #undef PLAT_amd64_solaris + +@@ -68,6 +69,8 @@ + #endif + #elif defined(__linux__) && defined(__nanomips__) + # define PLAT_nanomips_linux 1 ++#elif defined(__linux__) && defined(__sw_64__) ++# define PLAT_sw64_linux 1 + #elif defined(__sun__) && defined(__i386__) + # define PLAT_x86_solaris 1 + #elif defined(__sun__) && defined(__x86_64__) +@@ -151,6 +154,22 @@ + : /*out*/ : /*in*/ "r"(&(_lval)) \ + : /*trash*/ "$t0", "$t1", "memory" \ + ) ++#elif defined(PLAT_sw64_linux) ++# define INC(_lval,_lqual) \ ++ __asm__ __volatile__ ( \ ++ "0:\n" \ ++ " lldw $5, 0(%0)\n" \ ++ " ldi $8, 1\n" \ ++ " wr_f $8\n" \ ++ " addw $5, 1, $5\n" \ ++ " memb \n" \ ++ " lstw $5, 0(%0)\n" \ ++ " rd_f $5\n" \ ++ " beq $5, 0b\n" \ ++ : /*out*/ \ ++ : /*in*/ "r"(&(_lval)) \ ++ : /*trash*/ "$5", "$8", "memory" \ ++ ) + #else + # error "Fix Me for this platform" + #endif +diff --git a/helgrind/tests/tc11_XCHG.c b/helgrind/tests/tc11_XCHG.c +index f6ff1c984..44e425df8 100644 +--- a/helgrind/tests/tc11_XCHG.c ++++ b/helgrind/tests/tc11_XCHG.c +@@ -20,6 +20,7 @@ + #undef PLAT_arm_linux + #undef PLAT_s390x_linux + #undef PLAT_mips32_linux ++#undef PLAT_sw64_linux + #undef PLAT_x86_solaris + #undef PLAT_amd64_solaris + +@@ -49,6 +50,8 @@ + # define PLAT_mips32_linux 1 + #elif defined(__linux__) && defined(__nanomips__) + # define PLAT_nanomips_linux 1 ++#elif defined(__linux__) && defined(__sw_64__) ++# define PLAT_sw64_linux 1 + #elif defined(__sun__) && defined(__i386__) + # define PLAT_x86_solaris 1 + #elif defined(__sun__) && defined(__x86_64__) +@@ -146,6 +149,26 @@ + # define XCHG_M_R_with_redundant_LOCK(_addr,_lval) \ + XCHG_M_R(_addr,_lval) + ++#elif defined(PLAT_sw64_linux) ++# define XCHG_M_R(_addr,_lval) \ ++ __asm__ __volatile__( \ ++ "0:\n" \ ++ " lldw $5, 0(%1)\n" \ ++ " ldi $8, 1\n" \ ++ " wr_f $8\n" \ ++ " memb \n" \ ++ " lstw %0, 0(%1)\n" \ ++ " rd_f %0\n" \ ++ " beq %0, 0b\n" \ ++ " mov $5, %0\n" \ ++ : /*out*/ "+r"(_lval) \ ++ : /*in*/ "r"(&_addr) \ ++ : "$5", "$8", "memory" \ ++ ) ++ ++# define XCHG_M_R_with_redundant_LOCK(_addr,_lval) \ ++ XCHG_M_R(_addr,_lval) ++ + #else + # error "Unsupported architecture" + +diff --git a/helgrind/tests/tc20_verifywrap.stderr.exp-sw64 b/helgrind/tests/tc20_verifywrap.stderr.exp-sw64 +new file mode 100644 +index 000000000..90e746a40 +--- /dev/null ++++ b/helgrind/tests/tc20_verifywrap.stderr.exp-sw64 +@@ -0,0 +1,250 @@ ++ ++ ++ ++------ This is output for >= glibc 2.4 ------ ++ ++---------------- pthread_create/join ---------------- ++ ++---Thread-Announcement------------------------------------------ ++ ++Thread #x is the program's root thread ++ ++---Thread-Announcement------------------------------------------ ++ ++Thread #x was created ++ ... ++ by 0x........: pthread_create@* (hg_intercepts.c:...) ++ by 0x........: main (tc20_verifywrap.c:86) ++ ++---------------------------------------------------------------- ++ ++Possible data race during write of size 2 at 0x........ by thread #x ++Locks held: none ++ at 0x........: main (tc20_verifywrap.c:88) ++ ++This conflicts with a previous write of size 2 by thread #x ++Locks held: none ++ at 0x........: racy_child (tc20_verifywrap.c:44) ++ by 0x........: mythread_wrapper (hg_intercepts.c:...) ++ ... ++ Location 0x........ is 0 bytes inside global var "unprotected" ++ declared at tc20_verifywrap.c:37 ++ ++---------------------------------------------------------------- ++ ++Thread #x's call to pthread_join failed ++ with error code 11 (EDEADLK: Resource deadlock would occur) ++ at 0x........: pthread_join_WRK (hg_intercepts.c:...) ++ by 0x........: pthread_join (hg_intercepts.c:...) ++ by 0x........: main (tc20_verifywrap.c:93) ++ ++ ++---------------- pthread_mutex_lock et al ---------------- ++ ++---------------------------------------------------------------- ++ ++Thread #x's call to pthread_mutex_init failed ++ with error code 45 (EOPNOTSUPP: Operation not supported on transport endpoint) ++ at 0x........: pthread_mutex_init (hg_intercepts.c:...) ++ by 0x........: main (tc20_verifywrap.c:107) ++ ++---------------------------------------------------------------- ++ ++Thread #x: pthread_mutex_destroy of a locked mutex ++ at 0x........: mutex_destroy_WRK (hg_intercepts.c:...) ++ by 0x........: pthread_mutex_destroy (hg_intercepts.c:...) ++ by 0x........: main (tc20_verifywrap.c:117) ++ ++---------------------------------------------------------------- ++ ++Thread #x's call to pthread_mutex_destroy failed ++ with error code 16 (EBUSY: Device or resource busy) ++ at 0x........: mutex_destroy_WRK (hg_intercepts.c:...) ++ by 0x........: pthread_mutex_destroy (hg_intercepts.c:...) ++ by 0x........: main (tc20_verifywrap.c:117) ++ ++---------------------------------------------------------------- ++ ++Thread #x's call to pthread_mutex_lock failed ++ with error code 22 (EINVAL: Invalid argument) ++ at 0x........: mutex_lock_WRK (hg_intercepts.c:...) ++ by 0x........: pthread_mutex_lock (hg_intercepts.c:...) ++ by 0x........: main (tc20_verifywrap.c:123) ++ ++---------------------------------------------------------------- ++ ++Thread #x's call to pthread_mutex_trylock failed ++ with error code 22 (EINVAL: Invalid argument) ++ at 0x........: mutex_trylock_WRK (hg_intercepts.c:...) ++ by 0x........: pthread_mutex_trylock (hg_intercepts.c:...) ++ by 0x........: main (tc20_verifywrap.c:131) ++ ++---------------------------------------------------------------- ++ ++Thread #x's call to pthread_mutex_timedlock failed ++ with error code 22 (EINVAL: Invalid argument) ++ at 0x........: mutex_timedlock_WRK (hg_intercepts.c:...) ++ by 0x........: pthread_mutex_timedlock (hg_intercepts.c:...) ++ by 0x........: main (tc20_verifywrap.c:136) ++ ++---------------------------------------------------------------- ++ ++Thread #x unlocked an invalid lock at 0x........ ++ at 0x........: mutex_unlock_WRK (hg_intercepts.c:...) ++ by 0x........: pthread_mutex_unlock (hg_intercepts.c:...) ++ by 0x........: main (tc20_verifywrap.c:140) ++ ++---------------------------------------------------------------- ++ ++Thread #x's call to pthread_mutex_unlock failed ++ with error code 22 (EINVAL: Invalid argument) ++ at 0x........: mutex_unlock_WRK (hg_intercepts.c:...) ++ by 0x........: pthread_mutex_unlock (hg_intercepts.c:...) ++ by 0x........: main (tc20_verifywrap.c:140) ++ ++ ++---------------- pthread_cond_wait et al ---------------- ++ ++---------------------------------------------------------------- ++ ++Thread #x: pthread_cond_{timed}wait called with un-held mutex ++ at 0x........: pthread_cond_wait_WRK (hg_intercepts.c:...) ++ by 0x........: pthread_cond_wait@* (hg_intercepts.c:...) ++ by 0x........: main (tc20_verifywrap.c:162) ++ ++---------------------------------------------------------------- ++ ++Thread #x's call to pthread_cond_wait failed ++ with error code 1 (EPERM: Operation not permitted) ++ at 0x........: pthread_cond_wait_WRK (hg_intercepts.c:...) ++ by 0x........: pthread_cond_wait@* (hg_intercepts.c:...) ++ by 0x........: main (tc20_verifywrap.c:162) ++ ++---------------------------------------------------------------- ++ ++Thread #x: pthread_cond_{signal,broadcast}: dubious: associated lock is not held by any thread ++ at 0x........: pthread_cond_signal_WRK (hg_intercepts.c:...) ++ by 0x........: pthread_cond_signal@* (hg_intercepts.c:...) ++ by 0x........: main (tc20_verifywrap.c:167) ++ ++ ++FIXME: can't figure out how to verify wrap of pthread_cond_signal ++ ++---------------------------------------------------------------- ++ ++Thread #x: pthread_cond_{signal,broadcast}: dubious: associated lock is not held by any thread ++ at 0x........: pthread_cond_broadcast_WRK (hg_intercepts.c:...) ++ by 0x........: pthread_cond_broadcast@* (hg_intercepts.c:...) ++ by 0x........: main (tc20_verifywrap.c:173) ++ ++ ++FIXME: can't figure out how to verify wrap of pthread_broadcast_signal ++ ++---------------------------------------------------------------- ++ ++Thread #x: pthread_cond_{timed}wait called with un-held mutex ++ at 0x........: pthread_cond_timedwait_WRK (hg_intercepts.c:...) ++ by 0x........: pthread_cond_timedwait@* (hg_intercepts.c:...) ++ by 0x........: main (tc20_verifywrap.c:180) ++ ++---------------------------------------------------------------- ++ ++Thread #x's call to pthread_cond_timedwait failed ++ with error code 22 (EINVAL: Invalid argument) ++ at 0x........: pthread_cond_timedwait_WRK (hg_intercepts.c:...) ++ by 0x........: pthread_cond_timedwait@* (hg_intercepts.c:...) ++ by 0x........: main (tc20_verifywrap.c:180) ++ ++ ++---------------- pthread_rwlock_* ---------------- ++ ++---------------------------------------------------------------- ++ ++Thread #x unlocked a not-locked lock at 0x........ ++ at 0x........: pthread_rwlock_unlock_WRK (hg_intercepts.c:...) ++ by 0x........: pthread_rwlock_unlock (hg_intercepts.c:...) ++ ... ++ by 0x........: main (tc20_verifywrap.c:194) ++ Lock at 0x........ was first observed ++ at 0x........: pthread_rwlock_init_WRK (hg_intercepts.c:...) ++ by 0x........: pthread_rwlock_init (hg_intercepts.c:...) ++ by 0x........: main (tc20_verifywrap.c:193) ++ Location 0x........ is 0 bytes inside local var "rwl" ++ declared at tc20_verifywrap.c:57, in frame #x of thread x ++ ++ ++(1) no error on next line ++(2) no error on next line ++(3) ERROR on next line ++---------------------------------------------------------------- ++ ++Thread #x unlocked a not-locked lock at 0x........ ++ at 0x........: pthread_rwlock_unlock_WRK (hg_intercepts.c:...) ++ by 0x........: pthread_rwlock_unlock (hg_intercepts.c:...) ++ ... ++ by 0x........: main (tc20_verifywrap.c:211) ++ Lock at 0x........ was first observed ++ at 0x........: pthread_rwlock_init_WRK (hg_intercepts.c:...) ++ by 0x........: pthread_rwlock_init (hg_intercepts.c:...) ++ by 0x........: main (tc20_verifywrap.c:201) ++ Location 0x........ is 0 bytes inside local var "rwl2" ++ declared at tc20_verifywrap.c:58, in frame #x of thread x ++ ++ ++(4) no error on next line ++(5) no error on next line ++(6) no error on next line ++(7) no error on next line ++(8) ERROR on next line ++---------------------------------------------------------------- ++ ++Thread #x unlocked a not-locked lock at 0x........ ++ at 0x........: pthread_rwlock_unlock_WRK (hg_intercepts.c:...) ++ by 0x........: pthread_rwlock_unlock (hg_intercepts.c:...) ++ ... ++ by 0x........: main (tc20_verifywrap.c:232) ++ Lock at 0x........ was first observed ++ at 0x........: pthread_rwlock_init_WRK (hg_intercepts.c:...) ++ by 0x........: pthread_rwlock_init (hg_intercepts.c:...) ++ by 0x........: main (tc20_verifywrap.c:201) ++ Location 0x........ is 0 bytes inside local var "rwl2" ++ declared at tc20_verifywrap.c:58, in frame #x of thread x ++ ++ ++ ++---------------- pthread_spin_* ---------------- ++ ++ ++---------------- sem_* ---------------- ++ ++---------------------------------------------------------------- ++ ++Thread #x's call to sem_init failed ++ with error code 22 (EINVAL: Invalid argument) ++ at 0x........: sem_init_WRK (hg_intercepts.c:...) ++ by 0x........: sem_init@* (hg_intercepts.c:...) ++ by 0x........: main (tc20_verifywrap.c:267) ++ ++ ++FIXME: can't figure out how to verify wrap of sem_destroy ++ ++---------------------------------------------------------------- ++ ++Thread #x: Bug in libpthread: sem_wait succeeded on semaphore without prior sem_post ++ at 0x........: sem_wait_WRK (hg_intercepts.c:...) ++ by 0x........: sem_wait (hg_intercepts.c:...) ++ by 0x........: main (tc20_verifywrap.c:281) ++ ++ ++FIXME: can't figure out how to verify wrap of sem_post ++ ++ ++------------ dealloc of mem holding locks ------------ ++ ++---------------------------------------------------------------- ++ ++Thread #x: Exiting thread still holds 1 lock ++ ... ++ ++ ++ERROR SUMMARY: 22 errors from 22 contexts (suppressed: 0 from 0) +diff --git a/include/Makefile.am b/include/Makefile.am +index 972d394b8..059bc486c 100644 +--- a/include/Makefile.am ++++ b/include/Makefile.am +@@ -63,6 +63,7 @@ nobase_pkginclude_HEADERS = \ + vki/vki-posixtypes-mips32-linux.h \ + vki/vki-posixtypes-mips64-linux.h \ + vki/vki-posixtypes-nanomips-linux.h \ ++ vki/vki-posixtypes-sw64-linux.h \ + vki/vki-amd64-linux.h \ + vki/vki-arm64-linux.h \ + vki/vki-ppc32-linux.h \ +@@ -75,6 +76,7 @@ nobase_pkginclude_HEADERS = \ + vki/vki-mips32-linux.h \ + vki/vki-mips64-linux.h \ + vki/vki-nanomips-linux.h \ ++ vki/vki-sw64-linux.h \ + vki/vki-scnums-amd64-linux.h \ + vki/vki-scnums-arm64-linux.h \ + vki/vki-scnums-ppc32-linux.h \ +@@ -86,6 +88,7 @@ nobase_pkginclude_HEADERS = \ + vki/vki-scnums-mips32-linux.h \ + vki/vki-scnums-mips64-linux.h \ + vki/vki-scnums-nanomips-linux.h \ ++ vki/vki-scnums-sw64-linux.h \ + vki/vki-scnums-darwin.h \ + vki/vki-scnums-solaris.h \ + vki/vki-scnums-shared-linux.h \ +diff --git a/include/pub_tool_basics.h b/include/pub_tool_basics.h +index d22a42523..dbc461e37 100644 +--- a/include/pub_tool_basics.h ++++ b/include/pub_tool_basics.h +@@ -208,6 +208,7 @@ typedef + struct { + Bool _isError; + UWord _val; ++ UWord _valEx; + } + SysRes; + +@@ -321,6 +322,12 @@ static inline Bool sr_EQ ( UInt sysno, SysRes sr1, SysRes sr2 ) { + && sr1._isError == sr2._isError; + } + ++#if defined(VGP_sw64_linux) ++static inline UWord sr_ResEx ( SysRes sr ) { ++ return sr._isError ? 0 : sr._valEx; ++} ++#endif ++ + #elif defined(VGO_freebsd) + + static inline Bool sr_isError ( SysRes sr ) { +@@ -442,7 +449,8 @@ static inline Bool sr_EQ ( UInt sysno, SysRes sr1, SysRes sr2 ) { + + #if defined(VGA_x86) || defined(VGA_amd64) || defined (VGA_arm) \ + || ((defined(VGA_mips32) || defined(VGA_mips64) || defined(VGA_nanomips)) \ +- && defined (_MIPSEL)) || defined(VGA_arm64) || defined(VGA_ppc64le) ++ && defined (_MIPSEL)) || defined(VGA_arm64) || defined(VGA_ppc64le) \ ++ || defined(VGA_sw64) + # define VG_LITTLEENDIAN 1 + #elif defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_s390x) \ + || ((defined(VGA_mips32) || defined(VGA_mips64) || defined(VGA_nanomips)) \ +@@ -490,7 +498,8 @@ static inline Bool sr_EQ ( UInt sysno, SysRes sr1, SysRes sr2 ) { + || defined(VGA_ppc64be) || defined(VGA_ppc64le) \ + || defined(VGA_arm) || defined(VGA_s390x) \ + || defined(VGA_mips32) || defined(VGA_mips64) \ +- || defined(VGA_arm64) || defined(VGA_nanomips) ++ || defined(VGA_arm64) || defined(VGA_nanomips) \ ++ || defined(VGA_sw64) + # define VG_REGPARM(n) /* */ + #else + # error Unknown arch +diff --git a/include/pub_tool_debuginfo.h b/include/pub_tool_debuginfo.h +index 078c562b8..e0f85209a 100644 +--- a/include/pub_tool_debuginfo.h ++++ b/include/pub_tool_debuginfo.h +@@ -270,6 +270,8 @@ Addr VG_(DebugInfo_get_text_avma) ( const DebugInfo *di ); + SizeT VG_(DebugInfo_get_text_size) ( const DebugInfo *di ); + Addr VG_(DebugInfo_get_bss_avma) ( const DebugInfo *di ); + SizeT VG_(DebugInfo_get_bss_size) ( const DebugInfo *di ); ++Addr VG_(DebugInfo_get_sbss_avma) ( const DebugInfo *di ); ++SizeT VG_(DebugInfo_get_sbss_size) ( const DebugInfo *di ); + Addr VG_(DebugInfo_get_plt_avma) ( const DebugInfo *di ); + SizeT VG_(DebugInfo_get_plt_size) ( const DebugInfo *di ); + Addr VG_(DebugInfo_get_gotplt_avma) ( const DebugInfo *di ); +diff --git a/include/pub_tool_guest.h b/include/pub_tool_guest.h +index 08a72efac..fe6671e7d 100644 +--- a/include/pub_tool_guest.h ++++ b/include/pub_tool_guest.h +@@ -62,6 +62,9 @@ + #elif defined(VGA_mips64) + # include "libvex_guest_mips64.h" + typedef VexGuestMIPS64State VexGuestArchState; ++#elif defined(VGA_sw64) ++# include "libvex_guest_sw64.h" ++ typedef VexGuestSW64State VexGuestArchState; + #else + # error Unknown arch + #endif +diff --git a/include/pub_tool_machine.h b/include/pub_tool_machine.h +index 9bdd4f514..efeb3a395 100644 +--- a/include/pub_tool_machine.h ++++ b/include/pub_tool_machine.h +@@ -108,6 +108,12 @@ + # define VG_CLREQ_SZB 20 + # define VG_STACK_REDZONE_SZB 0 + ++#elif defined(VGP_sw64_linux) ++# define VG_MIN_INSTR_SZB 4 ++# define VG_MAX_INSTR_SZB 4 ++# define VG_CLREQ_SZB 20 ++# define VG_STACK_REDZONE_SZB 0 ++ + #else + # error Unknown platform + #endif +diff --git a/include/pub_tool_vkiscnums_asm.h b/include/pub_tool_vkiscnums_asm.h +index 14b483c4d..63b5fbd17 100644 +--- a/include/pub_tool_vkiscnums_asm.h ++++ b/include/pub_tool_vkiscnums_asm.h +@@ -74,6 +74,10 @@ + # include "vki/vki-scnums-shared-linux.h" + # include "vki/vki-scnums-mips64-linux.h" + ++#elif defined(VGP_sw64_linux) ++# include "vki/vki-scnums-shared-linux.h" ++# include "vki/vki-scnums-sw64-linux.h" ++ + #elif defined(VGP_x86_freebsd) || defined(VGP_amd64_freebsd) + # include "vki/vki-scnums-freebsd.h" + +diff --git a/include/valgrind.h.in b/include/valgrind.h.in +index aa0b43125..2b4a47754 100644 +--- a/include/valgrind.h.in ++++ b/include/valgrind.h.in +@@ -125,6 +125,7 @@ + #undef PLAT_mips32_linux + #undef PLAT_mips64_linux + #undef PLAT_nanomips_linux ++#undef PLAT_sw64_linux + #undef PLAT_x86_solaris + #undef PLAT_amd64_solaris + +@@ -169,6 +170,8 @@ + # define PLAT_mips32_linux 1 + #elif defined(__linux__) && defined(__nanomips__) + # define PLAT_nanomips_linux 1 ++#elif defined(__linux__) && defined(__sw_64__) ++# define PLAT_sw64_linux 1 + #elif defined(__sun) && defined(__i386__) + # define PLAT_x86_solaris 1 + #elif defined(__sun) && defined(__x86_64__) +@@ -1057,6 +1060,79 @@ typedef + + #endif /* PLAT_mips64_linux */ + ++/* ------------------------- sw64-linux ---------------- */ ++ ++#if defined(PLAT_sw64_linux) ++ ++typedef ++ struct { ++ unsigned long nraddr; /* where's the code? */ ++ } ++ OrigFn; ++ ++/* sll $31,3, $31 ++ * sll $31,13,$31 ++ * sll $31,29,$31 ++ * sll $31,19,$31 */ ++ /* write r31 means noop, others copied and modified from mips64 */ ++#define __SPECIAL_INSTRUCTION_PREAMBLE \ ++ "sll $31,3, $31; sll $31,13,$31\n\t" \ ++ "sll $31,29,$31; sll $31,19,$31\n\t" ++ ++#define VALGRIND_DO_CLIENT_REQUEST_EXPR( \ ++ _zzq_default, _zzq_request, \ ++ _zzq_arg1, _zzq_arg2, _zzq_arg3, _zzq_arg4, _zzq_arg5) \ ++ __extension__ \ ++ ({ volatile unsigned long int _zzq_args[6]; \ ++ volatile unsigned long int _zzq_result; \ ++ _zzq_args[0] = (unsigned long int)(_zzq_request); \ ++ _zzq_args[1] = (unsigned long int)(_zzq_arg1); \ ++ _zzq_args[2] = (unsigned long int)(_zzq_arg2); \ ++ _zzq_args[3] = (unsigned long int)(_zzq_arg3); \ ++ _zzq_args[4] = (unsigned long int)(_zzq_arg4); \ ++ _zzq_args[5] = (unsigned long int)(_zzq_arg5); \ ++ __asm__ volatile("mov %1, $4\n\t" /*default*/ \ ++ "mov %2, $5\n\t" /*ptr*/ \ ++ __SPECIAL_INSTRUCTION_PREAMBLE \ ++ /* $4 = client_request ( $5 ) */ \ ++ "bis $6, $6, $6\n\t" \ ++ "mov $4, %0\n\t" /*result*/ \ ++ : "=r" (_zzq_result) \ ++ : "r" (_zzq_default), "r" (&_zzq_args[0]) \ ++ : "$4", "$5", "memory"); \ ++ _zzq_result; \ ++ }) ++ ++#define VALGRIND_GET_NR_CONTEXT(_zzq_rlval) \ ++ { volatile OrigFn* _zzq_orig = &(_zzq_rlval); \ ++ volatile unsigned long int __addr; \ ++ __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE \ ++ /* $4 = guest_NRADDR */ \ ++ "bis $7, $7, $7\n\t" \ ++ "mov $4, %0" /*result*/ \ ++ : "=r" (__addr) \ ++ : \ ++ : "$4"); \ ++ _zzq_orig->nraddr = __addr; \ ++ } ++ ++#define VALGRIND_CALL_NOREDIR_T9 \ ++ __SPECIAL_INSTRUCTION_PREAMBLE \ ++ /* branch-and-link-to-noredir r27 */ \ ++ "bis $8, $8, $8\n\t" \ ++ ".set macro\n\t" \ ++ "br $gp, 0f\n" \ ++ "0: ldgp $gp, 0($gp)\n\t" ++ ++#define VALGRIND_VEX_INJECT_IR() \ ++ do { \ ++ __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE \ ++ "bis $4, $4, $4\n\t" \ ++ ); \ ++ } while (0) ++ ++#endif /* PLAT_sw64_linux */ ++ + #if defined(PLAT_nanomips_linux) + + typedef +@@ -6603,6 +6679,443 @@ typedef + + #endif /* PLAT_mips64_linux */ + ++ ++/* ------------------------ sw64-linux ------------------------ */ ++ ++#if defined(PLAT_sw64_linux) ++ ++/* These regs are trashed by the hidden call. */ ++#define __CALLER_SAVED_REGS \ ++ "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8", \ ++ "$16", "$17", "$18", "$19", "$20", "$21", \ ++ "$22", "$23", "$24", "$25", \ ++ "$27", "$28" ++ ++/* These CALL_FN_ macros assume that on sw64-linux, ++ sizeof(long) == 8. */ ++ ++#define CALL_FN_W_v(lval, orig) \ ++ do { \ ++ volatile OrigFn _orig = (orig); \ ++ volatile unsigned long _argvec[1]; \ ++ volatile unsigned long _res; \ ++ _argvec[0] = (unsigned long)(_orig.nraddr); \ ++ __asm__ volatile( \ ++ "ldl $27, 0(%1)\n\t" \ ++ VALGRIND_CALL_NOREDIR_T9 \ ++ "mov $0, %0\n" \ ++ : /*out*/ "=r" (_res) \ ++ : /*in*/ "0" (&_argvec[0]) \ ++ : /*trash*/ "memory", __CALLER_SAVED_REGS \ ++ ); \ ++ lval = (__typeof__(lval)) (long)_res; \ ++ } while (0) ++ ++#define CALL_FN_W_W(lval, orig, arg1) \ ++ do { \ ++ volatile OrigFn _orig = (orig); \ ++ volatile unsigned long _argvec[2]; \ ++ volatile unsigned long _res; \ ++ _argvec[0] = (unsigned long)(_orig.nraddr); \ ++ _argvec[1] = (unsigned long)(arg1); \ ++ __asm__ volatile( \ ++ "ldl $16, 8(%1)\n\t" /* arg1*/ \ ++ "ldl $27, 0(%1)\n\t" \ ++ VALGRIND_CALL_NOREDIR_T9 \ ++ "mov $0, %0\n" \ ++ : /*out*/ "=r" (_res) \ ++ : /*in*/ "r" (&_argvec[0]) \ ++ : /*trash*/ "memory", __CALLER_SAVED_REGS \ ++ ); \ ++ lval = (__typeof__(lval)) (long)_res; \ ++ } while (0) ++ ++#define CALL_FN_W_WW(lval, orig, arg1,arg2) \ ++ do { \ ++ volatile OrigFn _orig = (orig); \ ++ volatile unsigned long _argvec[3]; \ ++ volatile unsigned long _res; \ ++ _argvec[0] = _orig.nraddr; \ ++ _argvec[1] = (unsigned long)(arg1); \ ++ _argvec[2] = (unsigned long)(arg2); \ ++ __asm__ volatile( \ ++ "ldl $17, 16(%1)\n\t" /* arg2 */ \ ++ "ldl $16, 8(%1)\n\t" /* arg1 */ \ ++ "ldl $27, 0(%1)\n\t" \ ++ VALGRIND_CALL_NOREDIR_T9 \ ++ "mov $0, %0\n" \ ++ : /*out*/ "=r" (_res) \ ++ : /*in*/ "r" (&_argvec[0]) \ ++ : /*trash*/ "memory", __CALLER_SAVED_REGS \ ++ ); \ ++ lval = (__typeof__(lval)) (long)_res; \ ++ } while (0) ++ ++ ++#define CALL_FN_W_WWW(lval, orig, arg1,arg2,arg3) \ ++ do { \ ++ volatile OrigFn _orig = (orig); \ ++ volatile unsigned long _argvec[4]; \ ++ volatile unsigned long _res; \ ++ _argvec[0] = _orig.nraddr; \ ++ _argvec[1] = (unsigned long)(arg1); \ ++ _argvec[2] = (unsigned long)(arg2); \ ++ _argvec[3] = (unsigned long)(arg3); \ ++ __asm__ volatile( \ ++ "ldl $18, 24(%1)\n\t" /* arg3 */ \ ++ "ldl $17, 16(%1)\n\t" /* arg2 */ \ ++ "ldl $16, 8(%1)\n\t" /* arg1 */ \ ++ "ldl $27, 0(%1)\n\t" \ ++ VALGRIND_CALL_NOREDIR_T9 \ ++ "mov $0, %0\n" \ ++ : /*out*/ "=r" (_res) \ ++ : /*in*/ "r" (&_argvec[0]) \ ++ : /*trash*/ "memory", __CALLER_SAVED_REGS \ ++ ); \ ++ lval = (__typeof__(lval)) (long)_res; \ ++ } while (0) ++ ++#define CALL_FN_W_WWWW(lval, orig, arg1,arg2,arg3,arg4) \ ++ do { \ ++ volatile OrigFn _orig = (orig); \ ++ volatile unsigned long _argvec[5]; \ ++ volatile unsigned long _res; \ ++ _argvec[0] = (unsigned long)(_orig.nraddr); \ ++ _argvec[1] = (unsigned long)(arg1); \ ++ _argvec[2] = (unsigned long)(arg2); \ ++ _argvec[3] = (unsigned long)(arg3); \ ++ _argvec[4] = (unsigned long)(arg4); \ ++ __asm__ volatile( \ ++ "ldl $19, 32(%1)\n\t" /* arg4 */ \ ++ "ldl $18, 24(%1)\n\t" /* arg3 */ \ ++ "ldl $17, 16(%1)\n\t" /* arg2 */ \ ++ "ldl $16, 8(%1)\n\t" /* arg1 */ \ ++ "ldl $27, 0(%1)\n\t" \ ++ VALGRIND_CALL_NOREDIR_T9 \ ++ "mov $0, %0\n" \ ++ : /*out*/ "=r" (_res) \ ++ : /*in*/ "r" (&_argvec[0]) \ ++ : /*trash*/ "memory", __CALLER_SAVED_REGS \ ++ ); \ ++ lval = (__typeof__(lval)) (long)_res; \ ++ } while (0) ++ ++#define CALL_FN_W_5W(lval, orig, arg1,arg2,arg3,arg4,arg5) \ ++ do { \ ++ volatile OrigFn _orig = (orig); \ ++ volatile unsigned long _argvec[6]; \ ++ volatile unsigned long _res; \ ++ _argvec[0] = (unsigned long)(_orig.nraddr); \ ++ _argvec[1] = (unsigned long)(arg1); \ ++ _argvec[2] = (unsigned long)(arg2); \ ++ _argvec[3] = (unsigned long)(arg3); \ ++ _argvec[4] = (unsigned long)(arg4); \ ++ _argvec[5] = (unsigned long)(arg5); \ ++ __asm__ volatile( \ ++ "ldl $20, 40(%1)\n\t" /* arg5 */ \ ++ "ldl $19, 32(%1)\n\t" /* arg4 */ \ ++ "ldl $18, 24(%1)\n\t" /* arg3 */ \ ++ "ldl $17, 16(%1)\n\t" /* arg2 */ \ ++ "ldl $16, 8(%1)\n\t" /* arg1 */ \ ++ "ldl $27, 0(%1)\n\t" \ ++ VALGRIND_CALL_NOREDIR_T9 \ ++ "mov $0, %0\n" \ ++ : /*out*/ "=r" (_res) \ ++ : /*in*/ "r" (&_argvec[0]) \ ++ : /*trash*/ "memory", __CALLER_SAVED_REGS \ ++ ); \ ++ lval = (__typeof__(lval)) (long)_res; \ ++ } while (0) ++ ++#define CALL_FN_W_6W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6) \ ++ do { \ ++ volatile OrigFn _orig = (orig); \ ++ volatile unsigned long _argvec[7]; \ ++ volatile unsigned long _res; \ ++ _argvec[0] = (unsigned long)(_orig.nraddr); \ ++ _argvec[1] = (unsigned long)(arg1); \ ++ _argvec[2] = (unsigned long)(arg2); \ ++ _argvec[3] = (unsigned long)(arg3); \ ++ _argvec[4] = (unsigned long)(arg4); \ ++ _argvec[5] = (unsigned long)(arg5); \ ++ _argvec[6] = (unsigned long)(arg6); \ ++ __asm__ volatile( \ ++ "ldl $21, 48(%1)\n\t" /* arg6 */ \ ++ "ldl $20, 40(%1)\n\t" /* arg5 */ \ ++ "ldl $19, 32(%1)\n\t" /* arg4 */ \ ++ "ldl $18, 24(%1)\n\t" /* arg3 */ \ ++ "ldl $17, 16(%1)\n\t" /* arg2 */ \ ++ "ldl $16, 8(%1)\n\t" /* arg1 */ \ ++ "ldl $27, 0(%1)\n\t" \ ++ VALGRIND_CALL_NOREDIR_T9 \ ++ "mov $0, %0\n" \ ++ : /*out*/ "=r" (_res) \ ++ : /*in*/ "r" (&_argvec[0]) \ ++ : /*trash*/ "memory", __CALLER_SAVED_REGS \ ++ ); \ ++ lval = (__typeof__(lval)) (long)_res; \ ++ } while (0) ++ ++#define CALL_FN_W_7W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \ ++ arg7) \ ++ do { \ ++ volatile OrigFn _orig = (orig); \ ++ volatile unsigned long _argvec[8]; \ ++ volatile unsigned long _res; \ ++ _argvec[0] = (unsigned long)(_orig.nraddr); \ ++ _argvec[1] = (unsigned long)(arg1); \ ++ _argvec[2] = (unsigned long)(arg2); \ ++ _argvec[3] = (unsigned long)(arg3); \ ++ _argvec[4] = (unsigned long)(arg4); \ ++ _argvec[5] = (unsigned long)(arg5); \ ++ _argvec[6] = (unsigned long)(arg6); \ ++ _argvec[7] = (unsigned long)(arg7); \ ++ __asm__ volatile( \ ++ "ldi $30, -64($30)\n\t" \ ++ "ldl $0, 56(%1)\n\t" /* arg7 */ \ ++ "stl $0, 0($30)\n\t" /* arg7 */ \ ++ "ldl $21, 48(%1)\n\t" /* arg6 */ \ ++ "ldl $20, 40(%1)\n\t" /* arg5 */ \ ++ "ldl $19, 32(%1)\n\t" /* arg4 */ \ ++ "ldl $18, 24(%1)\n\t" /* arg3 */ \ ++ "ldl $17, 16(%1)\n\t" /* arg2 */ \ ++ "ldl $16, 8(%1)\n\t" /* arg1 */ \ ++ "ldl $27, 0(%1)\n\t" \ ++ VALGRIND_CALL_NOREDIR_T9 \ ++ "ldi $30, 64($30)\n\t" \ ++ "mov $0, %0\n" \ ++ : /*out*/ "=r" (_res) \ ++ : /*in*/ "r" (&_argvec[0]) \ ++ : /*trash*/ "memory", __CALLER_SAVED_REGS \ ++ ); \ ++ lval = (__typeof__(lval)) (long)_res; \ ++ } while (0) ++ ++#define CALL_FN_W_8W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \ ++ arg7,arg8) \ ++ do { \ ++ volatile OrigFn _orig = (orig); \ ++ volatile unsigned long _argvec[9]; \ ++ volatile unsigned long _res; \ ++ _argvec[0] = (unsigned long)(_orig.nraddr); \ ++ _argvec[1] = (unsigned long)(arg1); \ ++ _argvec[2] = (unsigned long)(arg2); \ ++ _argvec[3] = (unsigned long)(arg3); \ ++ _argvec[4] = (unsigned long)(arg4); \ ++ _argvec[5] = (unsigned long)(arg5); \ ++ _argvec[6] = (unsigned long)(arg6); \ ++ _argvec[7] = (unsigned long)(arg7); \ ++ _argvec[8] = (unsigned long)(arg8); \ ++ __asm__ volatile( \ ++ "ldi $30, -64($30)\n\t" \ ++ "ldl $0, 64(%1)\n\t" /* arg8 */ \ ++ "stl $0, 8($30)\n\t" /* arg8 */ \ ++ "ldl $0, 56(%1)\n\t" /* arg7 */ \ ++ "stl $0, 0($30)\n\t" /* arg7 */ \ ++ "ldl $21, 48(%1)\n\t" /* arg6 */ \ ++ "ldl $20, 40(%1)\n\t" /* arg5 */ \ ++ "ldl $19, 32(%1)\n\t" /* arg4 */ \ ++ "ldl $18, 24(%1)\n\t" /* arg3 */ \ ++ "ldl $17, 16(%1)\n\t" /* arg2 */ \ ++ "ldl $16, 8(%1)\n\t" /* arg1 */ \ ++ "ldl $27, 0(%1)\n\t" \ ++ VALGRIND_CALL_NOREDIR_T9 \ ++ "ldi $30, 64($30)\n\t" \ ++ "mov $0, %0\n" \ ++ : /*out*/ "=r" (_res) \ ++ : /*in*/ "r" (&_argvec[0]) \ ++ : /*trash*/ "memory", __CALLER_SAVED_REGS \ ++ ); \ ++ lval = (__typeof__(lval)) (long)_res; \ ++ } while (0) ++ ++#define CALL_FN_W_9W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \ ++ arg7,arg8,arg9) \ ++ do { \ ++ volatile OrigFn _orig = (orig); \ ++ volatile unsigned long _argvec[10]; \ ++ volatile unsigned long _res; \ ++ _argvec[0] = (unsigned long)(_orig.nraddr); \ ++ _argvec[1] = (unsigned long)(arg1); \ ++ _argvec[2] = (unsigned long)(arg2); \ ++ _argvec[3] = (unsigned long)(arg3); \ ++ _argvec[4] = (unsigned long)(arg4); \ ++ _argvec[5] = (unsigned long)(arg5); \ ++ _argvec[6] = (unsigned long)(arg6); \ ++ _argvec[7] = (unsigned long)(arg7); \ ++ _argvec[8] = (unsigned long)(arg8); \ ++ _argvec[9] = (unsigned long)(arg9); \ ++ __asm__ volatile( \ ++ "ldi $30, -64($30)\n\t" \ ++ "ldl $0, 72(%1)\n\t" /* arg9 */ \ ++ "stl $0, 16($30)\n\t" /* arg9 */ \ ++ "ldl $0, 64(%1)\n\t" /* arg8 */ \ ++ "stl $0, 8($30)\n\t" /* arg8 */ \ ++ "ldl $0, 56(%1)\n\t" /* arg7 */ \ ++ "stl $0, 0($30)\n\t" /* arg7 */ \ ++ "ldl $21, 48(%1)\n\t" /* arg6 */ \ ++ "ldl $20, 40(%1)\n\t" /* arg5 */ \ ++ "ldl $19, 32(%1)\n\t" /* arg4 */ \ ++ "ldl $18, 24(%1)\n\t" /* arg3 */ \ ++ "ldl $17, 16(%1)\n\t" /* arg2 */ \ ++ "ldl $16, 8(%1)\n\t" /* arg1 */ \ ++ "ldl $27, 0(%1)\n\t" \ ++ VALGRIND_CALL_NOREDIR_T9 \ ++ "ldi $30, 64($30)\n\t" \ ++ "mov $0, %0\n" \ ++ : /*out*/ "=r" (_res) \ ++ : /*in*/ "r" (&_argvec[0]) \ ++ : /*trash*/ "memory", __CALLER_SAVED_REGS \ ++ ); \ ++ lval = (__typeof__(lval)) (long)_res; \ ++ } while (0) ++ ++#define CALL_FN_W_10W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \ ++ arg7,arg8,arg9,arg10) \ ++ do { \ ++ volatile OrigFn _orig = (orig); \ ++ volatile unsigned long _argvec[11]; \ ++ volatile unsigned long _res; \ ++ _argvec[0] = (unsigned long)(_orig.nraddr); \ ++ _argvec[1] = (unsigned long)(arg1); \ ++ _argvec[2] = (unsigned long)(arg2); \ ++ _argvec[3] = (unsigned long)(arg3); \ ++ _argvec[4] = (unsigned long)(arg4); \ ++ _argvec[5] = (unsigned long)(arg5); \ ++ _argvec[6] = (unsigned long)(arg6); \ ++ _argvec[7] = (unsigned long)(arg7); \ ++ _argvec[8] = (unsigned long)(arg8); \ ++ _argvec[9] = (unsigned long)(arg9); \ ++ _argvec[10] = (unsigned long)(arg10); \ ++ __asm__ volatile( \ ++ "ldi $30, -64($30)\n\t" \ ++ "ldl $0, 80(%1)\n\t" /* arg10 */ \ ++ "stl $0, 24($30)\n\t" /* arg10 */ \ ++ "ldl $0, 72(%1)\n\t" /* arg9 */ \ ++ "stl $0, 16($30)\n\t" /* arg9 */ \ ++ "ldl $0, 64(%1)\n\t" /* arg8 */ \ ++ "stl $0, 8($30)\n\t" /* arg8 */ \ ++ "ldl $0, 56(%1)\n\t" /* arg7 */ \ ++ "stl $0, 0($30)\n\t" /* arg7 */ \ ++ "ldl $21, 48(%1)\n\t" /* arg6 */ \ ++ "ldl $20, 40(%1)\n\t" /* arg5 */ \ ++ "ldl $19, 32(%1)\n\t" /* arg4 */ \ ++ "ldl $18, 24(%1)\n\t" /* arg3 */ \ ++ "ldl $17, 16(%1)\n\t" /* arg2 */ \ ++ "ldl $16, 8(%1)\n\t" /* arg1 */ \ ++ "ldl $27, 0(%1)\n\t" \ ++ VALGRIND_CALL_NOREDIR_T9 \ ++ "ldi $30, 64($30)\n\t" \ ++ "mov $0, %0\n" \ ++ : /*out*/ "=r" (_res) \ ++ : /*in*/ "r" (&_argvec[0]) \ ++ : /*trash*/ "memory", __CALLER_SAVED_REGS \ ++ ); \ ++ lval = (__typeof__(lval)) (long)_res; \ ++ } while (0) ++ ++#define CALL_FN_W_11W(lval, orig, arg1,arg2,arg3,arg4,arg5, \ ++ arg6,arg7,arg8,arg9,arg10, \ ++ arg11) \ ++ do { \ ++ volatile OrigFn _orig = (orig); \ ++ volatile unsigned long _argvec[12]; \ ++ volatile unsigned long _res; \ ++ _argvec[0] = (unsigned long)(_orig.nraddr); \ ++ _argvec[1] = (unsigned long)(arg1); \ ++ _argvec[2] = (unsigned long)(arg2); \ ++ _argvec[3] = (unsigned long)(arg3); \ ++ _argvec[4] = (unsigned long)(arg4); \ ++ _argvec[5] = (unsigned long)(arg5); \ ++ _argvec[6] = (unsigned long)(arg6); \ ++ _argvec[7] = (unsigned long)(arg7); \ ++ _argvec[8] = (unsigned long)(arg8); \ ++ _argvec[9] = (unsigned long)(arg9); \ ++ _argvec[10] = (unsigned long)(arg10); \ ++ _argvec[11] = (unsigned long)(arg11); \ ++ __asm__ volatile( \ ++ "ldi $30, -64($30)\n\t" \ ++ "ldl $0, 88(%1)\n\t" /* arg11 */ \ ++ "stl $0, 32($30)\n\t" /* arg11 */ \ ++ "ldl $0, 80(%1)\n\t" /* arg10 */ \ ++ "stl $0, 24($30)\n\t" /* arg10 */ \ ++ "ldl $0, 72(%1)\n\t" /* arg9 */ \ ++ "stl $0, 16($30)\n\t" /* arg9 */ \ ++ "ldl $0, 64(%1)\n\t" /* arg8 */ \ ++ "stl $0, 8($30)\n\t" /* arg8 */ \ ++ "ldl $0, 56(%1)\n\t" /* arg7 */ \ ++ "stl $0, 0($30)\n\t" /* arg7 */ \ ++ "ldl $21, 48(%1)\n\t" /* arg6 */ \ ++ "ldl $20, 40(%1)\n\t" /* arg5 */ \ ++ "ldl $19, 32(%1)\n\t" /* arg4 */ \ ++ "ldl $18, 24(%1)\n\t" /* arg3 */ \ ++ "ldl $17, 16(%1)\n\t" /* arg2 */ \ ++ "ldl $16, 8(%1)\n\t" /* arg1 */ \ ++ "ldl $27, 0(%1)\n\t" \ ++ VALGRIND_CALL_NOREDIR_T9 \ ++ "ldi $30, 64($30)\n\t" \ ++ "mov $0, %0\n" \ ++ : /*out*/ "=r" (_res) \ ++ : /*in*/ "r" (&_argvec[0]) \ ++ : /*trash*/ "memory", __CALLER_SAVED_REGS \ ++ ); \ ++ lval = (__typeof__(lval)) (long)_res; \ ++ } while (0) ++ ++#define CALL_FN_W_12W(lval, orig, arg1,arg2,arg3,arg4,arg5, \ ++ arg6,arg7,arg8,arg9,arg10, \ ++ arg11,arg12) \ ++ do { \ ++ volatile OrigFn _orig = (orig); \ ++ volatile unsigned long _argvec[13]; \ ++ volatile unsigned long _res; \ ++ _argvec[0] = (unsigned long)(_orig.nraddr); \ ++ _argvec[1] = (unsigned long)(arg1); \ ++ _argvec[2] = (unsigned long)(arg2); \ ++ _argvec[3] = (unsigned long)(arg3); \ ++ _argvec[4] = (unsigned long)(arg4); \ ++ _argvec[5] = (unsigned long)(arg5); \ ++ _argvec[6] = (unsigned long)(arg6); \ ++ _argvec[7] = (unsigned long)(arg7); \ ++ _argvec[8] = (unsigned long)(arg8); \ ++ _argvec[9] = (unsigned long)(arg9); \ ++ _argvec[10] = (unsigned long)(arg10); \ ++ _argvec[11] = (unsigned long)(arg11); \ ++ _argvec[12] = (unsigned long)(arg12); \ ++ __asm__ volatile( \ ++ "ldi $30, -64($30)\n\t" \ ++ "ldl $0, 96(%1)\n\t" /* arg12 */ \ ++ "stl $0, 40($30)\n\t" /* arg12 */ \ ++ "ldl $0, 88(%1)\n\t" /* arg11 */ \ ++ "stl $0, 32($30)\n\t" /* arg11 */ \ ++ "ldl $0, 80(%1)\n\t" /* arg10 */ \ ++ "stl $0, 24($30)\n\t" /* arg10 */ \ ++ "ldl $0, 72(%1)\n\t" /* arg9 */ \ ++ "stl $0, 16($30)\n\t" /* arg9 */ \ ++ "ldl $0, 64(%1)\n\t" /* arg8 */ \ ++ "stl $0, 8($30)\n\t" /* arg8 */ \ ++ "ldl $0, 56(%1)\n\t" /* arg7 */ \ ++ "stl $0, 0($30)\n\t" /* arg7 */ \ ++ "ldl $21, 48(%1)\n\t" /* arg6 */ \ ++ "ldl $20, 40(%1)\n\t" /* arg5 */ \ ++ "ldl $19, 32(%1)\n\t" /* arg4 */ \ ++ "ldl $18, 24(%1)\n\t" /* arg3 */ \ ++ "ldl $17, 16(%1)\n\t" /* arg2 */ \ ++ "ldl $16, 8(%1)\n\t" /* arg1 */ \ ++ "ldl $27, 0(%1)\n\t" \ ++ VALGRIND_CALL_NOREDIR_T9 \ ++ "ldi $30, 64($30)\n\t" \ ++ "mov $0, %0\n" \ ++ : /*out*/ "=r" (_res) \ ++ : /*in*/ "r" (&_argvec[0]) \ ++ : /*trash*/ "memory", __CALLER_SAVED_REGS \ ++ ); \ ++ lval = (__typeof__(lval)) (long)_res; \ ++ } while (0) ++ ++#endif /* PLAT_sw64_linux */ ++ ++ + /* ------------------------------------------------------------------ */ + /* ARCHITECTURE INDEPENDENT MACROS for CLIENT REQUESTS. */ + /* */ +diff --git a/include/vki/vki-linux.h b/include/vki/vki-linux.h +index be3d76690..aeea87a0b 100644 +--- a/include/vki/vki-linux.h ++++ b/include/vki/vki-linux.h +@@ -97,6 +97,8 @@ + # include "vki-posixtypes-mips64-linux.h" + #elif defined(VGA_nanomips) + # include "vki-posixtypes-nanomips-linux.h" ++#elif defined(VGA_sw64) ++# include "vki-posixtypes-sw64-linux.h" + #else + # error Unknown platform + #endif +@@ -225,6 +227,8 @@ typedef unsigned int vki_uint; + # include "vki-mips64-linux.h" + #elif defined(VGA_nanomips) + # include "vki-nanomips-linux.h" ++#elif defined(VGA_sw64) ++# include "vki-sw64-linux.h" + #else + # error Unknown platform + #endif +@@ -1317,6 +1321,13 @@ struct vki_seminfo { + #define VKI_EDOM 33 /* Math argument out of domain of func */ + #define VKI_ERANGE 34 /* Math result not representable */ + ++#if defined( VGP_sw64_linux ) ++/* From arch/sw_64/include/uapi/asm/errno.h */ ++#undef VKI_EAGAIN /* 11 in errno-base.h */ ++#define VKI_EDEADLK 11 /* Resource deadlock would occur */ ++#define VKI_EAGAIN 35 /* Try again */ ++#endif ++ + //---------------------------------------------------------------------- + // From linux-2.6.8.1/include/asm-generic/errno.h + //---------------------------------------------------------------------- +diff --git a/include/vki/vki-posixtypes-sw64-linux.h b/include/vki/vki-posixtypes-sw64-linux.h +new file mode 100644 +index 000000000..af84e6506 +--- /dev/null ++++ b/include/vki/vki-posixtypes-sw64-linux.h +@@ -0,0 +1,74 @@ ++ ++/*--------------------------------------------------------------------*/ ++/*--- sw64/Linux-specific kernel interface: posix types. ---*/ ++/*--- vki-posixtypes-sw64-linux.h ---*/ ++/*--------------------------------------------------------------------*/ ++ ++/* ++ This file is part of Valgrind, a dynamic binary instrumentation ++ framework. ++ ++ Copyright (C) 2010-2017 RT-RK ++ ++ This program is free software; you can redistribute it and/or ++ modify it under the terms of the GNU General Public License as ++ published by the Free Software Foundation; either version 2 of the ++ License, or (at your option) any later version. ++ ++ This program is distributed in the hope that it will be useful, but ++ WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with this program; if not, see . ++*/ ++ ++#ifndef __VKI_POSIXTYPES_SW64_LINUX_H ++#define __VKI_POSIXTYPES_SW64_LINUX_H ++ ++typedef unsigned int __vki_kernel_ino_t; ++typedef unsigned long __vki_kernel_sigset_t; ++ ++typedef long __vki_kernel_long_t; ++typedef unsigned long __vki_kernel_ulong_t; ++typedef unsigned int __vki_kernel_mode_t; ++ ++typedef int __vki_kernel_pid_t; ++typedef int __vki_kernel_ipc_pid_t; ++typedef unsigned int __vki_kernel_uid_t; ++typedef unsigned int __vki_kernel_gid_t; ++typedef long __vki_kernel_suseconds_t; ++typedef int __vki_kernel_daddr_t; ++typedef unsigned int __vki_kernel_uid32_t; ++typedef unsigned int __vki_kernel_gid32_t; ++typedef __vki_kernel_uid_t __vki_kernel_old_uid_t; ++typedef __vki_kernel_gid_t __vki_kernel_old_gid_t; ++typedef unsigned int __vki_kernel_old_dev_t; ++ ++typedef unsigned long __vki_kernel_size_t; ++typedef long __vki_kernel_ssize_t; ++typedef long __vki_kernel_ptrdiff_t; ++ ++ ++ ++typedef long __vki_kernel_time_t; ++typedef long long __vki_kernel_time64_t; ++typedef long __vki_kernel_clock_t; ++typedef int __vki_kernel_timer_t; ++typedef int __vki_kernel_clockid_t; ++typedef char * __vki_kernel_caddr_t; ++typedef unsigned short __vki_kernel_uid16_t; ++typedef unsigned short __vki_kernel_gid16_t; ++typedef long long __vki_kernel_loff_t; ++typedef long __vki_kernel_off_t; ++ ++typedef struct { ++ int val[2]; ++} __vki_kernel_fsid_t; ++ ++#endif // __VKI_POSIXTYPES_SW64_LINUX_H ++ ++/*--------------------------------------------------------------------*/ ++/*--- end vki-posixtypes-sw64-linux.h ---*/ ++/*--------------------------------------------------------------------*/ +diff --git a/include/vki/vki-scnums-sw64-linux.h b/include/vki/vki-scnums-sw64-linux.h +new file mode 100644 +index 000000000..e0bbec202 +--- /dev/null ++++ b/include/vki/vki-scnums-sw64-linux.h +@@ -0,0 +1,390 @@ ++ ++/*--------------------------------------------------------------------*/ ++/*--- System call numbers for sw64-linux. ---*/ ++/*--- vki-scnums-sw64-linux.h ---*/ ++/*--------------------------------------------------------------------*/ ++ ++/* ++ This file is part of Valgrind, a dynamic binary instrumentation ++ framework. ++ ++ Copyright (C) 2013-2017 OpenWorks ++ info@open-works.net ++ ++ This program is free software; you can redistribute it and/or ++ modify it under the terms of the GNU General Public License as ++ published by the Free Software Foundation; either version 2 of the ++ License, or (at your option) any later version. ++ ++ This program is distributed in the hope that it will be useful, but ++ WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with this program; if not, see . ++ ++ The GNU General Public License is contained in the file COPYING. ++*/ ++ ++#ifndef __VKI_SCNUMS_SW64_LINUX_H ++#define __VKI_SCNUMS_SW64_LINUX_H ++ ++/* ++ From linux-4.19.y/arch/sw_64/include/generated/uapi/asm/unistd_64.h ++ which is not exists in source tree, and it was generated from ++ linux-4.19.y/arch/sw_64/kernel/syscalls/syscall.tbl ++*/ ++ ++#define __NR_exit 1 ++#define __NR_fork 2 ++#define __NR_read 3 ++#define __NR_write 4 ++#define __NR_close 6 ++#define __NR_link 9 ++#define __NR_unlink 10 ++#define __NR_chdir 12 ++#define __NR_fchdir 13 ++#define __NR_mknod 14 ++#define __NR_chmod 15 ++#define __NR_chown 16 ++#define __NR_brk 17 ++#define __NR_lseek 19 ++#define __NR_getxpid 20 ++#define __NR_umount2 22 ++#define __NR_setuid 23 ++#define __NR_getxuid 24 ++#define __NR_ptrace 26 ++#define __NR_access 33 ++#define __NR_sync 36 ++#define __NR_kill 37 ++#define __NR_setpgid 39 ++#define __NR_dup 41 ++#define __NR_pipe 42 ++#define __NR_open 45 ++#define __NR_getxgid 47 ++#define __NR_odd_sigprocmask 48 ++#define __NR_acct 51 ++#define __NR_sigpending 52 ++#define __NR_ioctl 54 ++#define __NR_symlink 57 ++#define __NR_readlink 58 ++#define __NR_execve 59 ++#define __NR_umask 60 ++#define __NR_chroot 61 ++#define __NR_getpgrp 63 ++#define __NR_vfork 66 ++#define __NR_stat 67 ++#define __NR_lstat 68 ++#define __NR_mmap 71 ++#define __NR_munmap 73 ++#define __NR_mprotect 74 ++#define __NR_madvise 75 ++#define __NR_vhangup 76 ++#define __NR_getgroups 79 ++#define __NR_setgroups 80 ++#define __NR_setpgrp 82 ++#define __NR_gethostname 87 ++#define __NR_sethostname 88 ++#define __NR_dup2 90 ++#define __NR_fstat 91 ++#define __NR_fcntl 92 ++#define __NR_poll 94 ++#define __NR_fsync 95 ++#define __NR_setpriority 96 ++#define __NR_socket 97 ++#define __NR_connect 98 ++#define __NR_accept 99 ++#define __NR_odd_getpriority 100 ++#define __NR_send 101 ++#define __NR_recv 102 ++#define __NR_sigreturn 103 ++#define __NR_bind 104 ++#define __NR_setsockopt 105 ++#define __NR_listen 106 ++#define __NR_sigsuspend 111 ++#define __NR_recvmsg 113 ++#define __NR_sendmsg 114 ++#define __NR_getsockopt 118 ++#define __NR_socketcall 119 ++#define __NR_readv 120 ++#define __NR_writev 121 ++#define __NR_fchown 123 ++#define __NR_fchmod 124 ++#define __NR_recvfrom 125 ++#define __NR_setreuid 126 ++#define __NR_setregid 127 ++#define __NR_rename 128 ++#define __NR_truncate 129 ++#define __NR_ftruncate 130 ++#define __NR_flock 131 ++#define __NR_setgid 132 ++#define __NR_sendto 133 ++#define __NR_shutdown 134 ++#define __NR_socketpair 135 ++#define __NR_mkdir 136 ++#define __NR_rmdir 137 ++#define __NR_getpeername 141 ++#define __NR_getrlimit 144 ++#define __NR_setrlimit 145 ++#define __NR_setsid 147 ++#define __NR_quotactl 148 ++#define __NR_getsockname 150 ++#define __NR_sigaction 156 ++#define __NR_setdomainname 166 ++#define __NR_bpf 170 ++#define __NR_userfaultfd 171 ++#define __NR_membarrier 172 ++#define __NR_mlock2 173 ++#define __NR_getpid 174 ++#define __NR_getppid 175 ++#define __NR_getuid 176 ++#define __NR_geteuid 177 ++#define __NR_getgid 178 ++#define __NR_getegid 179 ++#define __NR_msgctl 200 ++#define __NR_msgget 201 ++#define __NR_msgrcv 202 ++#define __NR_msgsnd 203 ++#define __NR_semctl 204 ++#define __NR_semget 205 ++#define __NR_semop 206 ++#define __NR_lchown 208 ++#define __NR_shmat 209 ++#define __NR_shmctl 210 ++#define __NR_shmdt 211 ++#define __NR_shmget 212 ++#define __NR_msync 217 ++#define __NR_statfs64 229 ++#define __NR_fstatfs64 230 ++#define __NR_getpgid 233 ++#define __NR_getsid 234 ++#define __NR_sigaltstack 235 ++#define __NR_sysfs 254 ++#define __NR_getsysinfo 256 ++#define __NR_setsysinfo 257 ++#define __NR_getpriority 298 ++#define __NR_sigprocmask 299 ++#define __NR_bdflush 300 ++#define __NR_mount 302 ++#define __NR_swapoff 304 ++#define __NR_getdents 305 ++#define __NR_create_module 306 ++#define __NR_init_module 307 ++#define __NR_delete_module 308 ++#define __NR_get_kernel_syms 309 ++#define __NR_syslog 310 ++#define __NR_reboot 311 ++#define __NR_clone 312 ++#define __NR_uselib 313 ++#define __NR_mlock 314 ++#define __NR_munlock 315 ++#define __NR_mlockall 316 ++#define __NR_munlockall 317 ++#define __NR_sysinfo 318 ++#define __NR__sysctl 319 ++#define __NR_oldumount 321 ++#define __NR_swapon 322 ++#define __NR_times 323 ++#define __NR_personality 324 ++#define __NR_setfsuid 325 ++#define __NR_setfsgid 326 ++#define __NR_ustat 327 ++#define __NR_statfs 328 ++#define __NR_fstatfs 329 ++#define __NR_sched_setparam 330 ++#define __NR_sched_getparam 331 ++#define __NR_sched_setscheduler 332 ++#define __NR_sched_getscheduler 333 ++#define __NR_sched_yield 334 ++#define __NR_sched_get_priority_max 335 ++#define __NR_sched_get_priority_min 336 ++#define __NR_sched_rr_get_interval 337 ++#define __NR_afs_syscall 338 ++#define __NR_uname 339 ++#define __NR_nanosleep 340 ++#define __NR_mremap 341 ++#define __NR_nfsservctl 342 ++#define __NR_setresuid 343 ++#define __NR_getresuid 344 ++#define __NR_pciconfig_read 345 ++#define __NR_pciconfig_write 346 ++#define __NR_query_module 347 ++#define __NR_prctl 348 ++#define __NR_pread64 349 ++#define __NR_pwrite64 350 ++#define __NR_rt_sigreturn 351 ++#define __NR_rt_sigaction 352 ++#define __NR_rt_sigprocmask 353 ++#define __NR_rt_sigpending 354 ++#define __NR_rt_sigtimedwait 355 ++#define __NR_rt_sigqueueinfo 356 ++#define __NR_rt_sigsuspend 357 ++#define __NR_select 358 ++#define __NR_gettimeofday 359 ++#define __NR_settimeofday 360 ++#define __NR_getitimer 361 ++#define __NR_setitimer 362 ++#define __NR_utimes 363 ++#define __NR_getrusage 364 ++#define __NR_wait4 365 ++#define __NR_adjtimex 366 ++#define __NR_getcwd 367 ++#define __NR_capget 368 ++#define __NR_capset 369 ++#define __NR_sendfile 370 ++#define __NR_setresgid 371 ++#define __NR_getresgid 372 ++#define __NR_dipc 373 ++#define __NR_pivot_root 374 ++#define __NR_mincore 375 ++#define __NR_pciconfig_iobase 376 ++#define __NR_getdents64 377 ++#define __NR_gettid 378 ++#define __NR_readahead 379 ++#define __NR_tkill 381 ++#define __NR_setxattr 382 ++#define __NR_lsetxattr 383 ++#define __NR_fsetxattr 384 ++#define __NR_getxattr 385 ++#define __NR_lgetxattr 386 ++#define __NR_fgetxattr 387 ++#define __NR_listxattr 388 ++#define __NR_llistxattr 389 ++#define __NR_flistxattr 390 ++#define __NR_removexattr 391 ++#define __NR_lremovexattr 392 ++#define __NR_fremovexattr 393 ++#define __NR_futex 394 ++#define __NR_sched_setaffinity 395 ++#define __NR_sched_getaffinity 396 ++#define __NR_tuxcall 397 ++#define __NR_io_setup 398 ++#define __NR_io_destroy 399 ++#define __NR_io_getevents 400 ++#define __NR_io_submit 401 ++#define __NR_io_cancel 402 ++#define __NR_io_pgetevents 403 ++#define __NR_rseq 404 ++#define __NR_exit_group 405 ++#define __NR_lookup_dcookie 406 ++#define __NR_epoll_create 407 ++#define __NR_epoll_ctl 408 ++#define __NR_epoll_wait 409 ++#define __NR_remap_file_pages 410 ++#define __NR_set_tid_address 411 ++#define __NR_restart_syscall 412 ++#define __NR_fadvise64 413 ++#define __NR_timer_create 414 ++#define __NR_timer_settime 415 ++#define __NR_timer_gettime 416 ++#define __NR_timer_getoverrun 417 ++#define __NR_timer_delete 418 ++#define __NR_clock_settime 419 ++#define __NR_clock_gettime 420 ++#define __NR_clock_getres 421 ++#define __NR_clock_nanosleep 422 ++#define __NR_semtimedop 423 ++#define __NR_tgkill 424 ++#define __NR_stat64 425 ++#define __NR_lstat64 426 ++#define __NR_fstat64 427 ++#define __NR_vserver 428 ++#define __NR_mbind 429 ++#define __NR_get_mempolicy 430 ++#define __NR_set_mempolicy 431 ++#define __NR_mq_open 432 ++#define __NR_mq_unlink 433 ++#define __NR_mq_timedsend 434 ++#define __NR_mq_timedreceive 435 ++#define __NR_mq_notify 436 ++#define __NR_mq_getsetattr 437 ++#define __NR_waitid 438 ++#define __NR_add_key 439 ++#define __NR_request_key 440 ++#define __NR_keyctl 441 ++#define __NR_ioprio_set 442 ++#define __NR_ioprio_get 443 ++#define __NR_inotify_init 444 ++#define __NR_inotify_add_watch 445 ++#define __NR_inotify_rm_watch 446 ++#define __NR_fdatasync 447 ++#define __NR_kexec_load 448 ++#define __NR_migrate_pages 449 ++#define __NR_openat 450 ++#define __NR_mkdirat 451 ++#define __NR_mknodat 452 ++#define __NR_fchownat 453 ++#define __NR_futimesat 454 ++#define __NR_fstatat64 455 ++#define __NR_unlinkat 456 ++#define __NR_renameat 457 ++#define __NR_linkat 458 ++#define __NR_symlinkat 459 ++#define __NR_readlinkat 460 ++#define __NR_fchmodat 461 ++#define __NR_faccessat 462 ++#define __NR_pselect6 463 ++#define __NR_ppoll 464 ++#define __NR_unshare 465 ++#define __NR_set_robust_list 466 ++#define __NR_get_robust_list 467 ++#define __NR_splice 468 ++#define __NR_sync_file_range 469 ++#define __NR_tee 470 ++#define __NR_vmsplice 471 ++#define __NR_move_pages 472 ++#define __NR_getcpu 473 ++#define __NR_epoll_pwait 474 ++#define __NR_utimensat 475 ++#define __NR_signalfd 476 ++#define __NR_timerfd 477 ++#define __NR_eventfd 478 ++#define __NR_recvmmsg 479 ++#define __NR_fallocate 480 ++#define __NR_timerfd_create 481 ++#define __NR_timerfd_settime 482 ++#define __NR_timerfd_gettime 483 ++#define __NR_signalfd4 484 ++#define __NR_eventfd2 485 ++#define __NR_epoll_create1 486 ++#define __NR_dup3 487 ++#define __NR_pipe2 488 ++#define __NR_inotify_init1 489 ++#define __NR_preadv 490 ++#define __NR_pwritev 491 ++#define __NR_rt_tgsigqueueinfo 492 ++#define __NR_perf_event_open 493 ++#define __NR_fanotify_init 494 ++#define __NR_fanotify_mark 495 ++#define __NR_prlimit64 496 ++#define __NR_name_to_handle_at 497 ++#define __NR_open_by_handle_at 498 ++#define __NR_clock_adjtime 499 ++#define __NR_syncfs 500 ++#define __NR_setns 501 ++#define __NR_accept4 502 ++#define __NR_sendmmsg 503 ++#define __NR_process_vm_readv 504 ++#define __NR_process_vm_writev 505 ++#define __NR_kcmp 506 ++#define __NR_finit_module 507 ++#define __NR_sched_setattr 508 ++#define __NR_sched_getattr 509 ++#define __NR_renameat2 510 ++#define __NR_getrandom 511 ++#define __NR_memfd_create 512 ++#define __NR_execveat 513 ++#define __NR_seccomp 514 ++#define __NR_copy_file_range 515 ++#define __NR_preadv2 516 ++#define __NR_pwritev2 517 ++#define __NR_statx 518 ++#define NR_SYSCALLS 519 ++#define NR_syscalls NR_SYSCALLS ++ ++#endif /* __VKI_SCNUMS_SW64_LINUX_H */ ++ ++/*--------------------------------------------------------------------*/ ++/*--- end vki-scnums-sw64-linux.h ---*/ ++/*--------------------------------------------------------------------*/ +diff --git a/include/vki/vki-sw64-linux.h b/include/vki/vki-sw64-linux.h +new file mode 100644 +index 000000000..007e54e0d +--- /dev/null ++++ b/include/vki/vki-sw64-linux.h +@@ -0,0 +1,977 @@ ++ ++/*--------------------------------------------------------------------*/ ++/*--- sw64/Linux-specific kernel interface. vki-sw64-linux.h ---*/ ++/*--------------------------------------------------------------------*/ ++ ++/* ++ This file is part of Valgrind, a dynamic binary instrumentation ++ framework. ++ ++ Copyright (C) 2010-2017 RT-RK ++ ++ This program is free software; you can redistribute it and/or ++ modify it under the terms of the GNU General Public License as ++ published by the Free Software Foundation; either version 2 of the ++ License, or (at your option) any later version. ++ ++ This program is distributed in the hope that it will be useful, but ++ WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with this program; if not, see . ++*/ ++ ++#ifndef __VKI_SW64_LINUX_H ++#define __VKI_SW64_LINUX_H ++ ++#include ++ ++// sw64 endian ++#define VKI_LITTLE_ENDIAN 1 ++ ++//---------------------------------------------------------------------- ++// From linux-4.19.180/include/uapi/asm-generic/int-ll64.h ++//---------------------------------------------------------------------- ++ ++typedef __signed__ char __vki_s8; ++typedef unsigned char __vki_u8; ++ ++typedef __signed__ short __vki_s16; ++typedef unsigned short __vki_u16; ++ ++typedef __signed__ int __vki_s32; ++typedef unsigned int __vki_u32; ++ ++typedef __signed__ long long __vki_s64; ++typedef unsigned long long __vki_u64; ++ ++typedef unsigned short vki_u16; ++ ++typedef unsigned int vki_u32; ++ ++//---------------------------------------------------------------------- ++// From linux-4.19.180/arch/sw_64/include/asm/page.h ++//---------------------------------------------------------------------- ++ ++extern UWord VKI_PAGE_SHIFT; ++extern UWord VKI_PAGE_SIZE; ++#define VKI_PAGE_MASK (~(VKI_PAGE_SIZE-1)) ++#define VKI_MAX_PAGE_SHIFT 13 ++#define VKI_MAX_PAGE_SIZE (1UL << VKI_MAX_PAGE_SHIFT) ++ ++//---------------------------------------------------------------------- ++// From linux-4.19.180/arch/sw_64/include/asm/shmparam.h ++//---------------------------------------------------------------------- ++ ++#define VKI_SHMLBA VKI_PAGE_SIZE ++ ++//---------------------------------------------------------------------- ++// From linux-4.19.180/include/uapi/asm-generic/signal.h ++//---------------------------------------------------------------------- ++ ++#define _VKI_NSIG 64 ++#define _VKI_NSIG_BPW 64 ++#define _VKI_NSIG_WORDS (_VKI_NSIG / _VKI_NSIG_BPW) ++ ++#define VKI_SIGHUP 1 ++#define VKI_SIGINT 2 ++#define VKI_SIGQUIT 3 ++#define VKI_SIGILL 4 ++#define VKI_SIGTRAP 5 ++#define VKI_SIGABRT 6 ++#define VKI_SIGEMT 7 ++#define VKI_SIGFPE 8 ++#define VKI_SIGKILL 9 ++#define VKI_SIGBUS 10 ++#define VKI_SIGSEGV 11 ++#define VKI_SIGSYS 12 ++#define VKI_SIGPIPE 13 ++#define VKI_SIGALRM 14 ++#define VKI_SIGTERM 15 ++#define VKI_SIGURG 16 ++#define VKI_SIGSTOP 17 ++#define VKI_SIGTSTP 18 ++#define VKI_SIGCONT 19 ++#define VKI_SIGCHLD 20 ++#define VKI_SIGTTIN 21 ++#define VKI_SIGTTOU 22 ++#define VKI_SIGIO 23 ++#define VKI_SIGXCPU 24 ++#define VKI_SIGXFSZ 25 ++#define VKI_SIGVTALRM 26 ++#define VKI_SIGPROF 27 ++#define VKI_SIGWINCH 28 ++#define VKI_SIGINFO 29 ++#define VKI_SIGUSR1 30 ++#define VKI_SIGUSR2 31 ++ ++#define VKI_SIGPOLL VKI_SIGIO ++//#define VKI_SIGPWR VKI_SIGINFO ++#define VKI_SIGIOT VKI_SIGABRT ++ ++/* These should not be considered constants from userland. */ ++#define VKI_SIGRTMIN 32 ++#define VKI_SIGRTMAX _VKI_NSIG ++ ++/* ++ * SA_FLAGS values: ++ * ++ * SA_ONSTACK indicates that a registered stack_t will be used. ++ * SA_RESTART flag to get restarting signals (which were the default long ago) ++ * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop. ++ * SA_RESETHAND clears the handler when the signal is delivered. ++ * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies. ++ * SA_NODEFER prevents the current signal from being masked in the handler. ++ * ++ * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single ++ * Unix names RESETHAND and NODEFER respectively. ++ */ ++#define VKI_SA_ONSTACK 0x00000001 ++#define VKI_SA_RESTART 0x00000002 ++#define VKI_SA_NOCLDSTOP 0x00000004 ++#define VKI_SA_NODEFER 0x00000008 ++#define VKI_SA_RESETHAND 0x00000010 ++#define VKI_SA_NOCLDWAIT 0x00000020 ++#define VKI_SA_SIGINFO 0x00000040 ++ ++#define VKI_SA_NOMASK VKI_SA_NODEFER ++#define VKI_SA_ONESHOT VKI_SA_RESETHAND ++ ++// This is obsolete and should not be defined for new archs ++#define VKI_SA_RESTORER 0x04000000 ++ ++#define VKI_SS_ONSTACK 1 ++#define VKI_SS_DISABLE 2 ++ ++#define VKI_MINSIGSTKSZ 4096 ++#define VKI_SIGSTKSZ 16384 ++#define VKI_SIG_BLOCK 1 /* for blocking signals */ ++#define VKI_SIG_UNBLOCK 2 /* for unblocking signals */ ++#define VKI_SIG_SETMASK 3 /* for setting the signal mask */ ++ ++typedef struct { ++ unsigned long sig[_VKI_NSIG_WORDS]; ++} vki_sigset_t; ++ ++/* not actually used, but required for linux/syscalls.h */ ++typedef unsigned long vki_old_sigset_t; ++ ++typedef void __vki_signalfn_t(int); ++typedef __vki_signalfn_t __user *__vki_sighandler_t; ++ ++typedef void __vki_restorefn_t(void); ++typedef __vki_restorefn_t __user *__vki_sigrestore_t; ++ ++#define VKI_SIG_DFL ((__vki_sighandler_t)0) /* default signal handling */ ++#define VKI_SIG_IGN ((__vki_sighandler_t)1) /* ignore signal */ ++#define VKI_SIG_ERR ((__vki_sighandler_t)-1) ++ ++struct vki_sigaction_base { ++ __vki_sighandler_t ksa_handler; ++ unsigned int sa_flags; ++ vki_sigset_t sa_mask; ++ __vki_sigrestore_t sa_restorer; ++}; ++ ++/* On Linux we use the same type for passing sigactions to ++ and from the kernel. Hence: */ ++typedef struct vki_sigaction_base vki_sigaction_toK_t; ++typedef struct vki_sigaction_base vki_sigaction_fromK_t; ++ ++typedef struct vki_sigaltstack { ++ void __user *ss_sp; ++ int ss_flags; ++ vki_size_t ss_size; ++} vki_stack_t; ++ ++struct vki_old_sigaction { ++ // [[Nb: a 'k' prefix is added to "sa_handler" because ++ // bits/sigaction.h (which gets dragged in somehow via signal.h) ++ // #defines it as something else. Since that is done for glibc's ++ // purposes, which we don't care about here, we use our own name.]] ++ unsigned long sa_flags; ++ __vki_sighandler_t ksa_handler; ++ vki_old_sigset_t sa_mask; ++ __vki_sigrestore_t sa_restorer; ++}; ++ ++//---------------------------------------------------------------------- ++// From linux-4.19.180/arch/sw_64/include/upi/asm/sigcontext.h ++//---------------------------------------------------------------------- ++ ++struct vki_sigcontext { ++ /* ++ * What should we have here? I'd probably better use the same ++ * stack layout as OSF/1, just in case we ever want to try ++ * running their binaries.. ++ * ++ * This is the basic layout, but I don't know if we'll ever ++ * actually fill in all the values.. ++ */ ++ long sc_onstack; ++ long sc_mask; ++ long sc_pc; ++ long sc_ps; ++ long sc_regs[32]; ++ long sc_ownedfp; ++ long sc_fpregs[128]; /* SIMD-FP */ ++ unsigned long sc_fpcr; ++ unsigned long sc_fp_control; ++ unsigned long sc_reserved1, sc_reserved2; ++ unsigned long sc_ssize; ++ char *sc_sbase; ++ unsigned long sc_traparg_a0; ++ unsigned long sc_traparg_a1; ++ unsigned long sc_traparg_a2; ++ unsigned long sc_fp_trap_pc; ++ unsigned long sc_fp_trigger_sum; ++ unsigned long sc_fp_trigger_inst; ++}; ++ ++//---------------------------------------------------------------------- ++// From linux-4.19.180/include/uapi/asm-generic/siginfo.h ++//---------------------------------------------------------------------- ++ ++#define __VKI_ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int)) ++ ++//---------------------------------------------------------------------- ++// From linux-4.19.180/arch/sw_64/include/upi/asm/mman.h ++//---------------------------------------------------------------------- ++ ++#define VKI_PROT_READ 0x1 /* page can be read */ ++#define VKI_PROT_WRITE 0x2 /* page can be written */ ++#define VKI_PROT_EXEC 0x4 /* page can be executed */ ++#define VKI_PROT_SEM 0x8 /* page may be used for atomic ops */ ++#define VKI_PROT_NONE 0x0 /* page can not be accessed */ ++#define VKI_PROT_GROWSDOWN 0x01000000 /* mprotect flag: extend change to start ++ of growsdown vma */ ++#define VKI_PROT_GROWSUP 0x02000000 /* mprotect flag: extend change to end ++ of growsup vma */ ++ ++#define VKI_MAP_SHARED 0x01 /* Share changes */ ++#define VKI_MAP_PRIVATE 0x02 /* Changes are private */ ++#define VKI_MAP_SHARED_VALIDATE 0x03 /* share + validate extension flags */ ++//#define VKI_MAP_TYPE 0x0f /* Mask for type of mapping */ ++#define VKI_MAP_FIXED 0x100 /* Interpret addr exactly */ ++#define VKI_MAP_ANONYMOUS 0x10 /* do not use a file*/ ++#define VKI_MAP_UNINITIALIZED 0x4000000 /* For anonymous mmap, memory could be uninitialized */ ++ ++/* These are linux-specific */ ++#define VKI_MAP_GROWSDOWN 0x01000 /* stack-like segment */ ++#define VKI_MAP_DENYWRITE 0x02000 /* ETXTBSY */ ++#define VKI_MAP_EXECUTABLE 0x04000 /* mark it as an executable */ ++#define VKI_MAP_LOCKED 0x08000 /* lock the mapping */ ++#define VKI_MAP_NORESERVE 0x10000 /* don't check for reservations */ ++#define VKI_MAP_POPULATE 0x20000 /* populate (prefault) pagetables */ ++#define VKI_MAP_NONBLOCK 0x40000 /* do not block on IO */ ++#define VKI_MAP_STACK 0x80000 /* give out an address that is best suited for process/thread stacks */ ++#define VKI_MAP_HUGETLB 0x100000 /* create a huge page mapping */ ++#define VKI_MAP_FIXED_NOREPLACE 0x200000 /* MAP_FIXED which doesn't unmap underlying mapping */ ++ ++//---------------------------------------------------------------------- ++// From linux-4.19.180/include/uapi/asm-generic/fcntl.h ++//---------------------------------------------------------------------- ++#define VKI_O_RDONLY 00 ++#define VKI_O_WRONLY 01 ++#define VKI_O_RDWR 02 ++#define VKI_O_ACCMODE 03 ++ ++#define VKI_O_CREAT 01000 /* not fcntl */ ++#define VKI_O_TRUNC 02000 /* not fcntl */ ++#define VKI_O_EXCL 04000 /* not fcntl */ ++#define VKI_O_NOCTTY 010000 /* not fcntl */ ++ ++#define VKI_O_NONBLOCK 00004 ++#define VKI_O_APPEND 00010 ++#define VKI_O_DSYNC 040000 /* used to be O_SYNC, see below */ ++#define VKI_O_DIRECTORY 0100000 /* must be a directory */ ++#define VKI_O_NOFOLLOW 0200000 /* don't follow links */ ++#define VKI_O_LARGEFILE 0400000 /* will be set by the kernel on every open */ ++#define VKI_O_DIRECT 02000000 /* direct disk access - should check with OSF/1 */ ++#define VKI_O_NOATIME 04000000 ++#define VKI_O_CLOEXEC 010000000 /* set close_on_exec */ ++ ++#define VKI_AT_FDCWD -100 ++ ++#define VKI_F_DUPFD 0 /* dup */ ++#define VKI_F_GETFD 1 /* get close_on_exec */ ++#define VKI_F_SETFD 2 /* set/clear close_on_exec */ ++#define VKI_F_GETFL 3 /* get file->f_flags */ ++#define VKI_F_SETFL 4 /* set file->f_flags */ ++ ++#define VKI_F_GETLK 7 ++#define VKI_F_SETLK 8 ++#define VKI_F_SETLKW 9 ++ ++#define VKI_F_SETOWN 5 /* for sockets. */ ++#define VKI_F_GETOWN 6 /* for sockets. */ ++#define VKI_F_SETSIG 10 /* for sockets. */ ++#define VKI_F_GETSIG 11 /* for sockets. */ ++ ++#define VKI_F_GETLK64 12 /* using 'struct flock64' */ ++#define VKI_F_SETLK64 13 ++#define VKI_F_SETLKW64 14 ++ ++#define VKI_F_SETOWN_EX 15 ++#define VKI_F_GETOWN_EX 16 ++#define VKI_F_GETOWNER_UIDS 17 ++ ++#define VKI_F_OFD_GETLK 36 ++#define VKI_F_OFD_SETLK 37 ++#define VKI_F_OFD_SETLKW 38 ++ ++/* for F_[GET|SET]FL */ ++#define VKI_FD_CLOEXEC 1 /* actually anything with low bit set goes */ ++ ++#define VKI_F_LINUX_SPECIFIC_BASE 1024 ++ ++struct vki_f_owner_ex { ++ int type; ++ __vki_kernel_pid_t pid; ++}; ++ ++//---------------------------------------------------------------------- ++// From linux-4.19.180/include/uapi/asm-generic/resource.h ++//---------------------------------------------------------------------- ++ ++#define VKI_RLIMIT_DATA 2 /* max data size */ ++#define VKI_RLIMIT_STACK 3 /* max stack size */ ++#define VKI_RLIMIT_CORE 4 /* max core file size */ ++#define VKI_RLIMIT_NOFILE 6 /* max number of open files */ ++#define VKI_RLIMIT_AS 7 /* address space limit */ ++#define VKI_RLIMIT_NPROC 8 /* max number of processes */ ++#define VKI_RLIMIT_MEMLOCK 9 /* max locked-in-memory address space */ ++ ++//---------------------------------------------------------------------- ++// From linux-4.19.y/arch/sw_64/include/uapi/asm/socket.h ++//---------------------------------------------------------------------- ++ ++#define VKI_SOL_SOCKET 0xffff ++#define VKI_SO_TYPE 0x1008 ++#define VKI_SO_ATTACH_FILTER 26 ++#define VKI_SOCK_NONBLOCK 0x40000000 ++ ++//---------------------------------------------------------------------- ++// From linux-4.19.180/include/uapi/asm-generic/sockios.h ++//---------------------------------------------------------------------- ++ ++#define VKI_SIOCATMARK _VKI_IOR('s', 7, int) ++#define VKI_SIOCSPGRP _VKI_IOW('s', 8, vki_pid_t) ++#define VKI_SIOCGPGRP _VKI_IOR('s', 9, vki_pid_t) ++#define VKI_SIOCGSTAMP 0x8906 /* Get stamp (timeval) */ ++#define VKI_SIOCGSTAMPNS 0x8907 /* Get stamp (timespec) */ ++ ++//---------------------------------------------------------------------- ++// From linux-4.19.180/arch/sw_64/include/uapi/asm/stat.h ++//---------------------------------------------------------------------- ++ ++struct vki_stat { ++ unsigned int st_dev; ++ unsigned int st_ino; ++ unsigned int st_mode; ++ unsigned int st_nlink; ++ unsigned int st_uid; ++ unsigned int st_gid; ++ unsigned int st_rdev; ++ long st_size; ++ unsigned long st_atime; ++ unsigned long st_mtime; ++ unsigned long st_ctime; ++ unsigned int st_blksize; ++ unsigned int st_blocks; ++ unsigned int st_flags; ++ unsigned int st_gen; ++}; ++ ++/* The stat64 structure increases the size of dev_t, blkcnt_t, adds ++ nanosecond resolution times, and padding for expansion. */ ++ ++struct vki_stat64 { ++ unsigned long st_dev; ++ unsigned long st_ino; ++ unsigned long st_rdev; ++ long st_size; ++ unsigned long st_blocks; ++ ++ unsigned int st_mode; ++ unsigned int st_uid; ++ unsigned int st_gid; ++ unsigned int st_blksize; ++ unsigned int st_nlink; ++ unsigned int __pad0; ++ ++ unsigned long st_atime; ++ unsigned long st_atime_nsec; ++ unsigned long st_mtime; ++ unsigned long st_mtime_nsec; ++ unsigned long st_ctime; ++ unsigned long st_ctime_nsec; ++ long __unused[3]; ++}; ++ ++//---------------------------------------------------------------------- ++// From linux-4.19.180/include/uapi/asm-generic/statfs.h ++//---------------------------------------------------------------------- ++ ++struct vki_statfs { ++ long f_type; ++ long f_bsize; ++ long f_blocks; ++ long f_bfree; ++ long f_bavail; ++ long f_files; ++ long f_ffree; ++ __vki_kernel_fsid_t f_fsid; ++ long f_namelen; ++ long f_frsize; ++ long f_flags; ++ long f_spare[4]; ++}; ++ ++//---------------------------------------------------------------------- ++// From linux-4.19.180/include/uapi/asm-generic/termios.h ++//---------------------------------------------------------------------- ++ ++struct vki_winsize { ++ unsigned short ws_row; ++ unsigned short ws_col; ++ unsigned short ws_xpixel; ++ unsigned short ws_ypixel; ++}; ++ ++struct vki_sgttyb { ++ char sg_ispeed; ++ char sg_ospeed; ++ char sg_erase; ++ char sg_kill; ++ short sg_flags; ++}; ++ ++struct vki_tchars { ++ char t_intrc; ++ char t_quitc; ++ char t_startc; ++ char t_stopc; ++ char t_eofc; ++ char t_brkc; ++}; ++ ++struct vki_ltchars { ++ char t_suspc; ++ char t_dsuspc; ++ char t_rprntc; ++ char t_flushc; ++ char t_werasc; ++ char t_lnextc; ++}; ++ ++#define VKI_NCC 8 ++#define VKI_NCCS 19 /* arch/sw_64/include/uapi/asm/termbits.h */ ++ ++struct vki_termio { ++ unsigned short c_iflag; /* input mode flags */ ++ unsigned short c_oflag; /* output mode flags */ ++ unsigned short c_cflag; /* control mode flags */ ++ unsigned short c_lflag; /* local mode flags */ ++ unsigned char c_line; /* line discipline */ ++ unsigned char c_cc[VKI_NCC]; /* control characters */ ++}; ++ ++//---------------------------------------------------------------------- ++// From linux-4.19.180/arch/sw_64/include/asm/termbits.h ++//---------------------------------------------------------------------- ++ ++typedef unsigned char vki_cc_t; ++typedef unsigned int vki_speed_t; ++typedef unsigned int vki_tcflag_t; ++ ++struct vki_termios { ++ vki_tcflag_t c_iflag; /* input mode flags */ ++ vki_tcflag_t c_oflag; /* output mode flags */ ++ vki_tcflag_t c_cflag; /* control mode flags */ ++ vki_tcflag_t c_lflag; /* local mode flags */ ++ vki_cc_t c_cc[VKI_NCCS]; /* control characters */ ++ vki_cc_t c_line; /* line discipline */ ++ vki_speed_t c_ispeed; /* input speed */ ++ vki_speed_t c_ospeed; /* output speed */ ++}; ++ ++//---------------------------------------------------------------------- ++// From linux-4.19.180/arch/sw_64/include/asm/ioctl.h ++//---------------------------------------------------------------------- ++ ++#define _VKI_IOC_NRBITS 8 ++#define _VKI_IOC_TYPEBITS 8 ++#define _VKI_IOC_SIZEBITS 13 ++#define _VKI_IOC_DIRBITS 3 ++ ++#define _VKI_IOC_NRMASK ((1 << _VKI_IOC_NRBITS)-1) ++#define _VKI_IOC_TYPEMASK ((1 << _VKI_IOC_TYPEBITS)-1) ++#define _VKI_IOC_SIZEMASK ((1 << _VKI_IOC_SIZEBITS)-1) ++#define _VKI_IOC_DIRMASK ((1 << _VKI_IOC_DIRBITS)-1) ++ ++#define _VKI_IOC_NRSHIFT 0 ++#define _VKI_IOC_TYPESHIFT (_VKI_IOC_NRSHIFT+_VKI_IOC_NRBITS) ++#define _VKI_IOC_SIZESHIFT (_VKI_IOC_TYPESHIFT+_VKI_IOC_TYPEBITS) ++#define _VKI_IOC_DIRSHIFT (_VKI_IOC_SIZESHIFT+_VKI_IOC_SIZEBITS) ++ ++#define _VKI_IOC_NONE 1U ++#define _VKI_IOC_READ 2U ++#define _VKI_IOC_WRITE 4U ++ ++#define _VKI_IOC(dir,type,nr,size) \ ++ ((unsigned int) \ ++ (((dir) << _VKI_IOC_DIRSHIFT) | \ ++ ((type) << _VKI_IOC_TYPESHIFT) | \ ++ ((nr) << _VKI_IOC_NRSHIFT) | \ ++ ((size) << _VKI_IOC_SIZESHIFT))) ++ ++/* provoke compile error for invalid uses of size argument */ ++extern unsigned int __VKI_invalid_size_argument_for_IOC; ++/* used to create numbers */ ++#define _VKI_IO(type,nr) _VKI_IOC(_VKI_IOC_NONE,(type),(nr),0) ++#define _VKI_IOR(type,nr,size) _VKI_IOC(_VKI_IOC_READ,(type),(nr), sizeof(size)) ++#define _VKI_IOW(type,nr,size) _VKI_IOC(_VKI_IOC_WRITE,(type),(nr), sizeof(size)) ++#define _VKI_IOWR(type,nr,size) _VKI_IOC(_VKI_IOC_READ|_VKI_IOC_WRITE,(type), (nr), sizeof(size)) ++ ++/* used to decode ioctl numbers.. */ ++#define _VKI_IOC_DIR(nr) (((nr) >> _VKI_IOC_DIRSHIFT) & _VKI_IOC_DIRMASK) ++#define _VKI_IOC_TYPE(nr) (((nr) >> _VKI_IOC_TYPESHIFT) & _VKI_IOC_TYPEMASK) ++#define _VKI_IOC_NR(nr) (((nr) >> _VKI_IOC_NRSHIFT) & _VKI_IOC_NRMASK) ++#define _VKI_IOC_SIZE(nr) (((nr) >> _VKI_IOC_SIZESHIFT) & _VKI_IOC_SIZEMASK) ++ ++//---------------------------------------------------------------------- ++// From linux-4.19.180/arch/sw_64/include/asm/ioctls.h ++//---------------------------------------------------------------------- ++ ++#define VKI_FIOCLEX _VKI_IO('f', 1) ++#define VKI_FIONCLEX _VKI_IO('f', 2) ++#define VKI_FIOASYNC _VKI_IOW('f', 125, int) ++#define VKI_FIONBIO _VKI_IOW('f', 126, int) ++#define VKI_FIONREAD _VKI_IOR('f', 127, int) ++#define VKI_TIOCINQ VKI_FIONREAD ++#define VKI_FIOQSIZE _VKI_IOR('f', 128, vki_loff_t) ++ ++#define VKI_IOCGETP _VKI_IOR('t', 8, struct vki_sgttyb) ++#define VKI_TIOCSETP _VKI_IOW('t', 9, struct vki_sgttyb) ++#define VKI_TIOCSETN _VKI_IOW('t', 10, struct vki_sgttyb) /* TIOCSETP wo flush */ ++ ++#define VKI_TIOCSETC _VKI_IOW('t', 17, struct vki_tchars) ++#define VKI_TIOCGETC _VKI_IOR('t', 18, struct vki_tchars) ++#define VKI_TCGETS _VKI_IOR('t', 19, struct vki_termios) ++#define VKI_TCSETS _VKI_IOW('t', 20, struct vki_termios) ++#define VKI_TCSETSW _VKI_IOW('t', 21, struct vki_termios) ++#define VKI_TCSETSF _VKI_IOW('t', 22, struct vki_termios) ++ ++#define VKI_TCGETA _VKI_IOR('t', 23, struct vki_termio) ++#define VKI_TCSETA _VKI_IOW('t', 24, struct vki_termio) ++#define VKI_TCSETAW _VKI_IOW('t', 25, struct vki_termio) ++#define VKI_TCSETAF _VKI_IOW('t', 28, struct vki_termio) ++ ++#define VKI_TCSBRK _VKI_IO('t', 29) ++#define VKI_TCXONC _VKI_IO('t', 30) ++#define VKI_TCFLSH _VKI_IO('t', 31) ++ ++#define VKI_TIOCSWINSZ _VKI_IOW('t', 103, struct vki_winsize) ++#define VKI_TIOCGWINSZ _VKI_IOR('t', 104, struct vki_winsize) ++#define VKI_TIOCSTART _VKI_IO('t', 110) /* start output, like ^Q */ ++#define VKI_TIOCSTOP _VKI_IO('t', 111) /* stop output, like ^S */ ++#define VKI_TIOCOUTQ _VKI_IOR('t', 115, int) /* output queue size */ ++ ++#define VKI_TIOCGLTC _VKI_IOR('t', 116, struct vki_ltchars) ++#define VKI_TIOCSLTC _VKI_IOW('t', 117, struct vki_ltchars) ++#define VKI_TIOCSPGRP _VKI_IOW('t', 118, int) ++#define VKI_TIOCGPGRP _VKI_IOR('t', 119, int) ++ ++#define VKI_TIOCEXCL 0x540C ++#define VKI_TIOCNXCL 0x540D ++#define VKI_TIOCSCTTY 0x540E ++ ++#define VKI_TIOCSTI 0x5412 ++#define VKI_TIOCMGET 0x5415 ++#define VKI_TIOCMBIS 0x5416 ++#define VKI_TIOCMBIC 0x5417 ++#define VKI_TIOCMSET 0x5418 ++#define VKI_TIOCM_LE 0x001 ++#define VKI_TIOCM_DTR 0x002 ++#define VKI_TIOCM_RTS 0x004 ++#define VKI_TIOCM_ST 0x008 ++#define VKI_TIOCM_SR 0x010 ++#define VKI_TIOCM_CTS 0x020 ++#define VKI_TIOCM_CAR 0x040 ++#define VKI_TIOCM_RNG 0x080 ++#define VKI_TIOCM_DSR 0x100 ++#define VKI_TIOCM_CD VKI_TIOCM_CAR ++#define VKI_TIOCM_RI VKI_TIOCM_RNG ++#define VKI_TIOCM_OUT1 0x2000 ++#define VKI_TIOCM_OUT2 0x4000 ++#define VKI_TIOCM_LOOP 0x8000 ++ ++#define VKI_TIOCGSOFTCAR 0x5419 ++#define VKI_TIOCSSOFTCAR 0x541A ++#define VKI_TIOCLINUX 0x541C ++#define VKI_TIOCCONS 0x541D ++#define VKI_TIOCGSERIAL 0x541E ++#define VKI_TIOCSSERIAL 0x541F ++#define VKI_TIOCPKT 0x5420 ++#define VKI_TIOCPKT_DATA 0 ++#define VKI_TIOCPKT_FLUSHREAD 1 ++#define VKI_TIOCPKT_FLUSHWRITE 2 ++#define VKI_TIOCPKT_STOP 4 ++#define VKI_TIOCPKT_START 8 ++#define VKI_TIOCPKT_NOSTOP 16 ++#define VKI_TIOCPKT_DOSTOP 32 ++#define VKI_TIOCPKT_IOCTL 64 ++ ++ ++#define VKI_TIOCNOTTY 0x5422 ++#define VKI_TIOCSETD 0x5423 ++#define VKI_TIOCGETD 0x5424 ++#define VKI_TCSBRKP 0x5425 /* Needed for POSIX tcsendbreak() */ ++#define VKI_TIOCSBRK 0x5427 /* BSD compatibility */ ++#define VKI_TIOCCBRK 0x5428 /* BSD compatibility */ ++#define VKI_TIOCGSID 0x5429 /* Return the session ID of FD */ ++#define VKI_TIOCGRS485 _VKI_IOR('T', 0x2E, struct vki_serial_rs485) ++#define VKI_TIOCSRS485 _VKI_IOWR('T', 0x2F, struct vki_serial_rs485) ++#define VKI_TIOCGPTN _VKI_IOR('T', 0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ ++#define VKI_TIOCSPTLCK _VKI_IOW('T', 0x31, int) /* Lock/unlock Pty */ ++#define VKI_TIOCGDEV _VKI_IOR('T', 0x32, unsigned int) /* Get primary device node of /dev/console */ ++#define VKI_TIOCSIG _VKI_IOW('T', 0x36, int) /* Generate signal on Pty slave */ ++#define VKI_TIOCVHANGUP 0x5437 ++#define VKI_TIOCGPKT _VKI_IOR('T', 0x38, int) /* Get packet mode state */ ++#define VKI_TIOCGPTLCK _VKI_IOR('T', 0x39, int) /* Get Pty lock state */ ++#define VKI_TIOCGEXCL _VKI_IOR('T', 0x40, int) /* Get exclusive mode state */ ++#define VKI_TIOCGPTPEER _VKI_IO('T', 0x41) /* Safely open the slave */ ++ ++#define VKI_TIOCSERCONFIG 0x5453 ++#define VKI_TIOCSERGWILD 0x5454 ++#define VKI_TIOCSERSWILD 0x5455 ++#define VKI_TIOCGLCKTRMIOS 0x5456 ++#define VKI_TIOCSLCKTRMIOS 0x5457 ++#define VKI_TIOCSERGSTRUCT 0x5458 /* For debugging only */ ++#define VKI_TIOCSERGETLSR 0x5459 /* Get line status register */ ++/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */ ++#define VKI_TIOCSER_TEMT 0x01 /* Transmitter physically empty */ ++#define VKI_TIOCSERGETMULTI 0x545A /* Get multiport config */ ++#define VKI_TIOCSERSETMULTI 0x545B /* Set multiport config */ ++ ++#define VKI_TIOCMIWAIT 0x545C /* wait for a change on serial input line(s) */ ++#define VKI_TIOCGICOUNT 0x545D /* read serial port inline interrupt counts */ ++ ++//---------------------------------------------------------------------- ++// From asm-generic/poll.h ++//---------------------------------------------------------------------- ++ ++/* These are specified by iBCS2 */ ++#define VKI_POLLIN 0x0001 ++ ++struct vki_pollfd { ++ int fd; ++ short events; ++ short revents; ++}; ++//---------------------------------------------------------------------- ++// From linux-4.19.180/arch/sw_64/include/asm/elf.h ++//---------------------------------------------------------------------- ++ ++#define VKI_ELF_NGREG 33 /* includes nip, msr, lr, etc. */ ++#define VKI_ELF_NFPREG 32 /* includes fpscr */ ++ ++typedef unsigned long vki_elf_greg_t; ++typedef vki_elf_greg_t vki_elf_gregset_t[VKI_ELF_NGREG]; ++ ++typedef double vki_elf_fpreg_t; ++typedef vki_elf_fpreg_t vki_elf_fpregset_t[VKI_ELF_NFPREG]; ++ ++//---------------------------------------------------------------------- ++// From linux-4.19.180/arch/sw_64/include/asm/ucontext.h ++//---------------------------------------------------------------------- ++ ++struct vki_ucontext { ++ unsigned long uc_flags; ++ struct vki_ucontext *uc_link; ++ vki_old_sigset_t uc_old_sigmask; ++ vki_stack_t uc_stack; ++ struct vki_sigcontext uc_mcontext; ++ vki_sigset_t uc_sigmask; /* mask last for extensibility */ ++}; ++ ++typedef char vki_modify_ldt_t; /* ldt.h */ ++ ++//---------------------------------------------------------------------- ++// From linux-4.19.180/include/uapi/asm-generic/ipcbuf.h ++//---------------------------------------------------------------------- ++ ++struct vki_ipc64_perm { ++ __vki_kernel_key_t key; ++ __vki_kernel_uid32_t uid; ++ __vki_kernel_gid32_t gid; ++ __vki_kernel_uid32_t cuid; ++ __vki_kernel_gid32_t cgid; ++ __vki_kernel_mode_t mode; ++ unsigned char __pad1[4 - sizeof(__vki_kernel_mode_t)]; ++ unsigned short seq; ++ unsigned short __pad2; ++ __vki_kernel_ulong_t __unused1; ++ __vki_kernel_ulong_t __unused2; ++}; ++ ++//---------------------------------------------------------------------- ++// From linux-4.19.180/arch/sw_64/include/asm/sembuf.h ++//---------------------------------------------------------------------- ++ ++struct vki_semid64_ds { ++ struct vki_ipc64_perm sem_perm; /* permissions .. see ipc.h */ ++ __vki_kernel_time_t sem_otime; /* last semop time */ ++ __vki_kernel_time_t sem_ctime; /* last change time */ ++ unsigned long sem_nsems; /* no. of semaphores in array */ ++ unsigned long __unused1; ++ unsigned long __unused2; ++}; ++ ++//---------------------------------------------------------------------- ++// From linux-4.19.180/arch/sw_64/include/uapi/asm/msgbuf.h ++//---------------------------------------------------------------------- ++ ++struct vki_msqid64_ds { ++ struct vki_ipc64_perm msg_perm; ++ __vki_kernel_time_t msg_stime; /* last msgsnd time */ ++ __vki_kernel_time_t msg_rtime; /* last msgrcv time */ ++ __vki_kernel_time_t msg_ctime; /* last change time */ ++ unsigned long msg_cbytes; /* current number of bytes on queue */ ++ unsigned long msg_qnum; /* number of messages in queue */ ++ unsigned long msg_qbytes; /* max number of bytes on queue */ ++ __vki_kernel_pid_t msg_lspid; /* pid of last msgsnd */ ++ __vki_kernel_pid_t msg_lrpid; /* last receive pid */ ++ unsigned long __unused1; ++ unsigned long __unused2; ++}; ++ ++//---------------------------------------------------------------------- ++// From linux-4.19.180/include/uapi/linux/ipc.h ++//---------------------------------------------------------------------- ++ ++struct vki_ipc_kludge { ++ struct vki_msgbuf __user *msgp; ++ long msgtyp; ++}; ++ ++#define VKI_SEMOP 1 ++#define VKI_SEMGET 2 ++#define VKI_SEMCTL 3 ++#define VKI_SEMTIMEDOP 4 ++#define VKI_MSGSND 11 ++#define VKI_MSGRCV 12 ++#define VKI_MSGGET 13 ++#define VKI_MSGCTL 14 ++#define VKI_SHMAT 21 ++#define VKI_SHMDT 22 ++#define VKI_SHMGET 23 ++#define VKI_SHMCTL 24 ++ ++//---------------------------------------------------------------------- ++// From linux-4.19.180/arch/sw_64/include/uapi/asm/shmbuf.h ++//---------------------------------------------------------------------- ++ ++struct vki_shmid64_ds { ++ struct vki_ipc64_perm shm_perm; /* operation perms */ ++ vki_size_t shm_segsz; /* size of segment (bytes) */ ++ __vki_kernel_time_t shm_atime; /* last attach time */ ++ __vki_kernel_time_t shm_dtime; /* last detach time */ ++ __vki_kernel_time_t shm_ctime; /* last change time */ ++ __vki_kernel_pid_t shm_cpid; /* pid of creator */ ++ __vki_kernel_pid_t shm_lpid; /* pid of last operator */ ++ unsigned long shm_nattch; /* no. of current attaches */ ++ unsigned long __unused1; ++ unsigned long __unused2; ++}; ++ ++struct vki_shminfo64 { ++ unsigned long shmmax; ++ unsigned long shmmin; ++ unsigned long shmmni; ++ unsigned long shmseg; ++ unsigned long shmall; ++ unsigned long __unused1; ++ unsigned long __unused2; ++ unsigned long __unused3; ++ unsigned long __unused4; ++}; ++ ++//---------------------------------------------------------------------- ++// From linux-4.19.180/arch/sw_64/include/uapi/asm/ptrace.h ++//---------------------------------------------------------------------- ++ ++struct vki_pt_regs { ++ unsigned long r0; ++ unsigned long r1; ++ unsigned long r2; ++ unsigned long r3; ++ unsigned long r4; ++ unsigned long r5; ++ unsigned long r6; ++ unsigned long r7; ++ unsigned long r8; ++ unsigned long r19; ++ unsigned long r20; ++ unsigned long r21; ++ unsigned long r22; ++ unsigned long r23; ++ unsigned long r24; ++ unsigned long r25; ++ unsigned long r26; ++ unsigned long r27; ++ unsigned long r28; ++ unsigned long hae; ++/* JRP - These are the values provided to a0-a2 by HMcode */ ++ unsigned long trap_a0; ++ unsigned long trap_a1; ++ unsigned long trap_a2; ++/* These are saved by HMcode: */ ++ unsigned long ps; ++ unsigned long pc; ++ unsigned long gp; ++ unsigned long r16; ++ unsigned long r17; ++ unsigned long r18; ++}; ++ ++#define VKI_PTRACE_GETREGS 12 /* get general purpose registers */ ++#define VKI_PTRACE_SETREGS 13 /* set general purpose registers */ ++#define VKI_PTRACE_GETFPREGS 14 /* get floating-point registers */ ++#define VKI_PTRACE_SETFPREGS 15 /* set floating-point registers */ ++ ++//---------------------------------------------------------------------- ++// From linux-4.19.180/arch/sw_64/include/uapi/asm/errno.h ++//---------------------------------------------------------------------- ++ ++#define VKI_EOPNOTSUPP 45 /* Operation not supported on transport endpoint */ ++#define VKI_ENOSYS 78 /* Function not implemented */ ++#define VKI_EOVERFLOW 112 /* Value too large for defined data type */ ++ ++//---------------------------------------------------------------------- ++// From linux-4.19.180/include/uapi/asm-generic/siginfo.h ++//---------------------------------------------------------------------- ++ ++#define HAVE_ARCH_SIGINFO_T ++#define __VKI_ARCH_SI_TRAPNO ++typedef union vki_sigval { ++ int sival_int; ++ void __user *sival_ptr; ++} vki_sigval_t; ++ ++#ifndef __VKI_ARCH_SI_PREAMBLE_SIZE ++#define __VKI_ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int)) ++#endif ++ ++#define VKI_SI_MAX_SIZE 128 ++ ++#ifndef VKI_SI_PAD_SIZE ++#define VKI_SI_PAD_SIZE ((VKI_SI_MAX_SIZE - __VKI_ARCH_SI_PREAMBLE_SIZE) / sizeof(int)) ++#endif ++ ++#ifndef __VKI_ARCH_SI_UID_T ++#define __VKI_ARCH_SI_UID_T vki_uid_t ++#endif ++ ++#ifndef __VKI_ARCH_SI_BAND_T ++#define __VKI_ARCH_SI_BAND_T long ++#endif ++ ++#ifndef __VKI_ARCH_SI_CLOCK_T ++#define __VKI_ARCH_SI_CLOCK_T __vki_kernel_clock_t ++#endif ++ ++#ifndef __VKI_ARCH_SI_ATTRIBUTES ++#define __VKI_ARCH_SI_ATTRIBUTES ++#endif ++ ++typedef struct vki_siginfo { ++ int si_signo; ++ int si_errno; ++ int si_code; ++ ++ union { ++ int _pad[VKI_SI_PAD_SIZE]; ++ ++ /* kill() */ ++ struct { ++ __vki_kernel_pid_t _pid; /* sender's pid */ ++ __vki_kernel_uid32_t _uid; /* sender's uid */ ++ } _kill; ++ ++ /* POSIX.1b timers */ ++ struct { ++ __vki_kernel_timer_t _tid; /* timer id */ ++ int _overrun; /* overrun count */ ++ vki_sigval_t _sigval; /* same as below */ ++ int _sys_private; /* not to be passed to user */ ++ } _timer; ++ ++ /* POSIX.1b signals */ ++ struct { ++ __vki_kernel_pid_t _pid; /* sender's pid */ ++ __vki_kernel_uid32_t _uid; /* sender's uid */ ++ vki_sigval_t _sigval; ++ } _rt; ++ ++ /* SIGCHLD */ ++ struct { ++ __vki_kernel_pid_t _pid; /* which child */ ++ __vki_kernel_uid32_t _uid; /* sender's uid */ ++ int _status; /* exit code */ ++ __VKI_ARCH_SI_CLOCK_T _utime; ++ __VKI_ARCH_SI_CLOCK_T _stime; ++ } _sigchld; ++ ++ /* SIGILL, SIGFPE, SIGSEGV, SIGBUS, SIGTRAP, SIGEMT */ ++ struct { ++ void __user *_addr; /* faulting insn/memory ref. */ ++#ifdef __VKI_ARCH_SI_TRAPNO ++ int _trapno; /* TRAP # which caused the signal */ ++#endif ++ ++#define __VKI_ADDR_BND_PKEY_PAD (__alignof__(void *) < sizeof(short) ? \ ++ sizeof(short) : __alignof__(void *)) ++ union { ++ /* ++ * used when si_code=BUS_MCEERR_AR or ++ * used when si_code=BUS_MCEERR_AO ++ */ ++ short _addr_lsb; /* LSB of the reported address */ ++ /* used when si_code=SEGV_BNDERR */ ++ struct { ++ char _dummy_bnd[__VKI_ADDR_BND_PKEY_PAD]; ++ void __user *_lower; ++ void __user *_upper; ++ } _addr_bnd; ++ /* used when si_code=SEGV_PKUERR */ ++ struct { ++ char _dummy_pkey[__VKI_ADDR_BND_PKEY_PAD]; ++ __vki_u32 _pkey; ++ } _addr_pkey; ++ }; ++ } _sigfault; ++ ++ /* SIGPOLL */ ++ struct { ++ __VKI_ARCH_SI_BAND_T _band; /* POLL_IN, POLL_OUT, POLL_MSG */ ++ int _fd; ++ } _sigpoll; ++ ++ /* SIGSYS */ ++ struct { ++ void __user *_call_addr; /* calling user insn */ ++ int _syscall; /* triggering system call number */ ++ unsigned int _arch; /* AUDIT_ARCH_* of syscall */ ++ } _sigsys; ++ } _sifields; ++} __VKI_ARCH_SI_ATTRIBUTES vki_siginfo_t; ++ ++#endif // __VKI_SW64_LINUX_H ++ ++/*--------------------------------------------------------------------*/ ++/*--- end vki-sw64-linux.h ---*/ ++/*--------------------------------------------------------------------*/ +diff --git a/massif/tests/Makefile.am b/massif/tests/Makefile.am +index 84c9b1273..99aafdb5c 100644 +--- a/massif/tests/Makefile.am ++++ b/massif/tests/Makefile.am +@@ -9,6 +9,7 @@ EXTRA_DIST = \ + basic.post.exp basic.stderr.exp basic.vgtest \ + basic2.post.exp basic2.stderr.exp basic2.vgtest \ + big-alloc.post.exp big-alloc.post.exp-64bit big-alloc.post.exp-ppc64 \ ++ big-alloc.post.exp-sw64 \ + big-alloc.stderr.exp big-alloc.vgtest \ + big-alloc.post.exp-x86-freebsd \ + deep-A.post.exp deep-A.stderr.exp deep-A.vgtest \ +diff --git a/massif/tests/big-alloc.post.exp-sw64 b/massif/tests/big-alloc.post.exp-sw64 +new file mode 100644 +index 000000000..601ddee4f +--- /dev/null ++++ b/massif/tests/big-alloc.post.exp-sw64 +@@ -0,0 +1,54 @@ ++-------------------------------------------------------------------------------- ++Command: ./big-alloc ++Massif arguments: --stacks=no --time-unit=B --massif-out-file=massif.out --ignore-fn=__part_load_locale --ignore-fn=__time_load_locale --ignore-fn=dwarf2_unwind_dyld_add_image_hook --ignore-fn=get_or_create_key_element ++ms_print arguments: massif.out ++-------------------------------------------------------------------------------- ++ ++ ++ MB ++100.1^ : ++ | : ++ | @@@@@@@: ++ | @ : ++ | :::::::@ : ++ | : @ : ++ | :::::::: @ : ++ | : : @ : ++ | :::::::: : @ : ++ | : : : @ : ++ | :::::::: : : @ : ++ | : : : : @ : ++ | ::::::::: : : : @ : ++ | : : : : : @ : ++ | :::::::: : : : : @ : ++ | : : : : : : @ : ++ | :::::::: : : : : : @ : ++ | : : : : : : : @ : ++ | :::::::: : : : : : : @ : ++ | : : : : : : : : @ : ++ 0 +----------------------------------------------------------------------->MB ++ 0 100.1 ++ ++Number of snapshots: 11 ++ Detailed snapshots: [9] ++ ++-------------------------------------------------------------------------------- ++ n time(B) total(B) useful-heap(B) extra-heap(B) stacks(B) ++-------------------------------------------------------------------------------- ++ 0 0 0 0 0 0 ++ 1 10,493,896 10,493,896 10,485,760 8,136 0 ++ 2 20,987,792 20,987,792 20,971,520 16,272 0 ++ 3 31,481,688 31,481,688 31,457,280 24,408 0 ++ 4 41,975,584 41,975,584 41,943,040 32,544 0 ++ 5 52,469,480 52,469,480 52,428,800 40,680 0 ++ 6 62,963,376 62,963,376 62,914,560 48,816 0 ++ 7 73,457,272 73,457,272 73,400,320 56,952 0 ++ 8 83,951,168 83,951,168 83,886,080 65,088 0 ++ 9 94,445,064 94,445,064 94,371,840 73,224 0 ++99.92% (94,371,840B) (heap allocation functions) malloc/new/new[], --alloc-fns, etc. ++->99.92% (94,371,840B) 0x........: main (big-alloc.c:12) ++ ++-------------------------------------------------------------------------------- ++ n time(B) total(B) useful-heap(B) extra-heap(B) stacks(B) ++-------------------------------------------------------------------------------- ++ 10 104,938,960 104,938,960 104,857,600 81,360 0 +diff --git a/memcheck/mc_machine.c b/memcheck/mc_machine.c +index 176c8e5cb..6da932334 100644 +--- a/memcheck/mc_machine.c ++++ b/memcheck/mc_machine.c +@@ -1394,6 +1394,82 @@ static Int get_otrack_shadow_offset_wrk ( Int offset, Int szB ) + offset,szB); + tl_assert(0); + # undef GOF ++# undef SZB ++ ++ /* --------------------- sw64 --------------------- */ ++ ++# elif defined(VGA_sw64) ++ ++# define GOF(_fieldname) \ ++ (offsetof(VexGuestSW64State,guest_##_fieldname)) ++# define SZB(_fieldname) \ ++ (sizeof(((VexGuestSW64State*)0)->guest_##_fieldname)) ++ ++ Int o = offset; ++ Int sz = szB; ++ tl_assert(sz > 0); ++ tl_assert(host_is_little_endian()); ++ ++ if (o >= GOF(r0) && sz <= 8 && o <= (GOF(r31) + 8 - sz)) ++ return GOF(r0) + ((o-GOF(r0)) & -8) ; ++ ++ if (o == GOF(PC) && sz == SZB(PC)) return -1; /* slot unused */ ++ if (o == GOF(CSR) && sz == SZB(CSR)) return -1; /* slot unused */ ++ ++ if (o >= GOF(f0) && o+sz <= GOF(f0) +SZB(f0)) return GOF(f0); ++ if (o >= GOF(f1) && o+sz <= GOF(f1) +SZB(f1)) return GOF(f1); ++ if (o >= GOF(f2) && o+sz <= GOF(f2) +SZB(f2)) return GOF(f2); ++ if (o >= GOF(f3) && o+sz <= GOF(f3) +SZB(f3)) return GOF(f3); ++ if (o >= GOF(f4) && o+sz <= GOF(f4) +SZB(f4)) return GOF(f4); ++ if (o >= GOF(f5) && o+sz <= GOF(f5) +SZB(f5)) return GOF(f5); ++ if (o >= GOF(f6) && o+sz <= GOF(f6) +SZB(f6)) return GOF(f6); ++ if (o >= GOF(f7) && o+sz <= GOF(f7) +SZB(f7)) return GOF(f7); ++ if (o >= GOF(f8) && o+sz <= GOF(f8) +SZB(f8)) return GOF(f8); ++ if (o >= GOF(f9) && o+sz <= GOF(f9) +SZB(f9)) return GOF(f9); ++ if (o >= GOF(f10) && o+sz <= GOF(f10)+SZB(f10)) return GOF(f10); ++ if (o >= GOF(f11) && o+sz <= GOF(f11)+SZB(f11)) return GOF(f11); ++ if (o >= GOF(f12) && o+sz <= GOF(f12)+SZB(f12)) return GOF(f12); ++ if (o >= GOF(f13) && o+sz <= GOF(f13)+SZB(f13)) return GOF(f13); ++ if (o >= GOF(f14) && o+sz <= GOF(f14)+SZB(f14)) return GOF(f14); ++ if (o >= GOF(f15) && o+sz <= GOF(f15)+SZB(f15)) return GOF(f15); ++ if (o >= GOF(f16) && o+sz <= GOF(f16)+SZB(f16)) return GOF(f16); ++ if (o >= GOF(f17) && o+sz <= GOF(f17)+SZB(f17)) return GOF(f17); ++ if (o >= GOF(f18) && o+sz <= GOF(f18)+SZB(f18)) return GOF(f18); ++ if (o >= GOF(f19) && o+sz <= GOF(f19)+SZB(f19)) return GOF(f19); ++ if (o >= GOF(f20) && o+sz <= GOF(f20)+SZB(f20)) return GOF(f20); ++ if (o >= GOF(f21) && o+sz <= GOF(f21)+SZB(f21)) return GOF(f21); ++ if (o >= GOF(f22) && o+sz <= GOF(f22)+SZB(f22)) return GOF(f22); ++ if (o >= GOF(f23) && o+sz <= GOF(f23)+SZB(f23)) return GOF(f23); ++ if (o >= GOF(f24) && o+sz <= GOF(f24)+SZB(f24)) return GOF(f24); ++ if (o >= GOF(f25) && o+sz <= GOF(f25)+SZB(f25)) return GOF(f25); ++ if (o >= GOF(f26) && o+sz <= GOF(f26)+SZB(f26)) return GOF(f26); ++ if (o >= GOF(f27) && o+sz <= GOF(f27)+SZB(f27)) return GOF(f27); ++ if (o >= GOF(f28) && o+sz <= GOF(f28)+SZB(f28)) return GOF(f28); ++ if (o >= GOF(f29) && o+sz <= GOF(f29)+SZB(f29)) return GOF(f29); ++ if (o >= GOF(f30) && o+sz <= GOF(f30)+SZB(f30)) return GOF(f30); ++ if (o >= GOF(f31) && o+sz <= GOF(f31)+SZB(f31)) return GOF(f31); ++ ++ if (o == GOF(FPCR) && sz == SZB(FPCR)) return -1; ++ ++ if (o == GOF(EMNOTE) && sz == SZB(EMNOTE)) return -1; ++ ++ if (o == GOF(CMSTART) && sz == SZB(CMSTART)) return -1; ++ if (o == GOF(CMLEN) && sz == SZB(CMLEN)) return -1; ++ ++ if (o == GOF(NRADDR) && sz == SZB(NRADDR)) return -1; ++ if (o == GOF(LOCKFLAG) && sz == SZB(LOCKFLAG)) return -1; ++ if (o == GOF(LOCKVALID) && sz == SZB(LOCKVALID)) return -1; ++ if (o == GOF(LOCKSUCCESS) && sz == SZB(LOCKSUCCESS)) return -1; ++ if (o == GOF(LOCKSIZE) && sz == SZB(LOCKSIZE)) return -1; ++ if (o == GOF(LOCKADDR) && sz == SZB(LOCKADDR)) return -1; ++ if (o == GOF(LOCKDATA) && sz == SZB(LOCKDATA)) return -1; ++ ++ if (o == GOF(TID) && sz == SZB(TID)) return -1; ++ ++ VG_(printf)("MC_(get_otrack_shadow_offset)(sw)(off=%d,sz=%d)\n", ++ offset,szB); ++ tl_assert(0); ++# undef GOF + # undef SZB + + # else +@@ -1517,6 +1593,13 @@ IRType MC_(get_otrack_reg_array_equiv_int_type) ( IRRegArray* arr ) + VG_(printf)("\n"); + tl_assert(0); + ++ /* --------------------- sw64 --------------------- */ ++# elif defined(VGA_sw64) ++ VG_(printf)("get_reg_array_equiv_int_type(sw64): unhandled: "); ++ ppIRRegArray(arr); ++ VG_(printf)("\n"); ++ tl_assert(0); ++ + # else + # error "FIXME: not implemented for this architecture" + # endif +diff --git a/memcheck/mc_translate.c b/memcheck/mc_translate.c +index 72ccb3c8c..82f31d453 100644 +--- a/memcheck/mc_translate.c ++++ b/memcheck/mc_translate.c +@@ -4755,6 +4755,21 @@ IRAtom* expr2vbits_Binop ( MCEnv* mce, + cheap_cmp8: + return mkPCastTo(mce, Ity_I1, mkUifU8(mce, vatom1,vatom2)); + ++ ++ ////---- CmpFXX64 ++ // Iop_CmpFUN64, ++ // Iop_CmpFLT64, ++ // Iop_CmpFLE64, ++ // Iop_CmpFGT64, ++ // Iop_CmpFGE64, ++ // Iop_CmpFEQ64, ++ // Iop_CmpFNE64, ++ case Iop_CmpFEQ64: case Iop_CmpFNE64: ++ case Iop_CmpFLT64: case Iop_CmpFLE64: ++ case Iop_CmpFGT64: case Iop_CmpFGE64: ++ case Iop_CmpFUN64: ++ return mkPCastTo(mce, Ity_I1, mkUifU64(mce, vatom1,vatom2)); ++ + ////---- end CmpXX{64,32,16,8} + + case Iop_CasCmpEQ8: case Iop_CasCmpNE8: +@@ -8648,6 +8663,8 @@ IRSB* MC_(instrument) ( VgCallbackClosure* closure, + mce.dlbo.dl_CmpEQ64_CmpNE64 = DLexpensive; + # elif defined(VGA_arm) + mce.dlbo.dl_CmpEQ32_CmpNE32 = DLexpensive; ++# elif defined(VGA_sw64) ++ mce.dlbo.dl_CmpEQ64_CmpNE64 = DLexpensive; + # endif + + /* preInstrumentationAnalysis() will allocate &mce.tmpHowUsed and then +diff --git a/memcheck/tests/Makefile.am b/memcheck/tests/Makefile.am +index 9bbbe7bec..2b3d832e6 100644 +--- a/memcheck/tests/Makefile.am ++++ b/memcheck/tests/Makefile.am +@@ -25,6 +25,9 @@ endif + if VGCONF_ARCHS_INCLUDE_S390X + SUBDIRS += s390x + endif ++if VGCONF_ARCHS_INCLUDE_SW64 ++SUBDIRS += sw64 ++endif + + # OS-specific tests + if VGCONF_OS_IS_LINUX +@@ -318,10 +321,11 @@ EXTRA_DIST = \ + sh-mem-random.stdout.exp sh-mem-random.vgtest \ + sigaltstack.stderr.exp sigaltstack.vgtest \ + sigkill.stderr.exp sigkill.stderr.exp-darwin sigkill.stderr.exp-freebsd sigkill.stderr.exp-mips32 \ +- sigkill.stderr.exp-solaris \ ++ sigkill.stderr.exp-solaris sigkill.stderr.exp-sw64 \ + sigkill.stderr.exp-glibc-2.28 sigkill.vgtest \ + signal2.stderr.exp signal2.stdout.exp signal2.vgtest \ + sigprocmask.stderr.exp sigprocmask.stderr.exp2 sigprocmask.vgtest \ ++ sigprocmask.stderr.exp-sw64 \ + sized_delete.stderr.exp sized_delete.stderr.exp-x86 sized_delete.vgtest \ + static_malloc.stderr.exp static_malloc.vgtest \ + stpncpy.vgtest stpncpy.stderr.exp stpncpy.stdout.exp \ +diff --git a/memcheck/tests/atomic_incs.c b/memcheck/tests/atomic_incs.c +index 1c738c530..7a718f897 100644 +--- a/memcheck/tests/atomic_incs.c ++++ b/memcheck/tests/atomic_incs.c +@@ -245,6 +245,26 @@ __attribute__((noinline)) void atomic_add_8bit ( char* p, int n ) + ); + } while (block[2] != 1); + #endif ++#elif defined(VGA_sw64) ++ __asm__ __volatile__( ++ " bic %0, 0x7, $22\n" ++ "0: \n" ++ " lldl $5, 0($r22)\n" ++ " ldi $8, 1\n" ++ " wr_f $8\n" ++ " extlb $5, %0, $6\n" ++ " addl $6, %1, $6\n" ++ " inslb $6, %0, $6\n" ++ " masklb $5, %0, $5\n" ++ " or $5, $6, $5\n" ++ " memb \n" ++ " lstl $5, 0($22)\n" ++ " rd_f $5\n" ++ " beq $5, 0b\n" ++ : ++ : "r"(p), "r"(n) ++ : "memory", "$5", "$6", "$8", "$22" ++ ); + #else + # error "Unsupported arch" + #endif +@@ -461,6 +481,26 @@ __attribute__((noinline)) void atomic_add_16bit ( short* p, int n ) + ); + } while (block[2] != 1); + #endif ++#elif defined(VGA_sw64) ++ __asm__ __volatile__( ++ " bic %0, 0x7, $22\n" ++ "0: \n" ++ " lldl $5, 0($r22)\n" ++ " ldi $8, 1\n" ++ " wr_f $8\n" ++ " extlh $5, %0, $6\n" ++ " addl $6, %1, $6\n" ++ " inslh $6, %0, $6\n" ++ " masklh $5, %0, $5\n" ++ " or $5, $6, $5\n" ++ " memb \n" ++ " lstl $5, 0($22)\n" ++ " rd_f $5\n" ++ " beq $5, 0b\n" ++ : ++ : "r"(p), "r"(n) ++ : "memory", "$5", "$6", "$8", "$22" ++ ); + #else + # error "Unsupported arch" + #endif +@@ -616,6 +656,21 @@ __attribute__((noinline)) void atomic_add_32bit ( int* p, int n ) + : /*trash*/ "memory", "t0", "t1", "t2", "t3" + ); + } while (block[2] != 1); ++#elif defined(VGA_sw64) ++ __asm__ __volatile__ ( ++ "0:\n" ++ " lldw $5, 0(%0)\n" ++ " ldi $8, 1\n" ++ " wr_f $8\n" ++ " addw $5, %1, $5\n" ++ " memb \n" ++ " lstw $5, 0(%0)\n" ++ " rd_f $5\n" ++ " beq $5, 0b\n" ++ : /*out*/ ++ : /*in*/ "r"(p), "r"(n) ++ : /*trash*/ "$5", "$8", "memory" ++ ); + #else + # error "Unsupported arch" + #endif +@@ -718,6 +773,21 @@ __attribute__((noinline)) void atomic_add_64bit ( long long int* p, int n ) + : /*trash*/ "memory", "t0", "t1", "t2", "t3" + ); + } while (block[2] != 1); ++#elif defined(VGA_sw64) ++ __asm__ __volatile__ ( ++ "0:\n" ++ " lldl $5, 0(%0)\n" ++ " ldi $8, 1\n" ++ " wr_f $8\n" ++ " addl $5, %1, $5\n" ++ " memb \n" ++ " lstl $5, 0(%0)\n" ++ " rd_f $5\n" ++ " beq $5, 0b\n" ++ : /*out*/ ++ : /*in*/ "r"(p), "r"(n) ++ : /*trash*/ "$5", "$8", "memory" ++ ); + #else + # error "Unsupported arch" + #endif +@@ -752,6 +822,8 @@ __attribute__((noinline)) void atomic_add_128bit ( MyU128* p, + : /*trash*/ "memory", "cc", "x5", "x7", "x8", "x9", "x10", "x4" + ); + } while (block[2] != 0); ++#elif defined(VGA_sw64) ++ // TODO(Shaohua): Impl atomic_add_128bit() + #else + # error "Unsupported arch" + #endif +diff --git a/memcheck/tests/badjump2.c b/memcheck/tests/badjump2.c +index ae858e773..a6faef7d2 100644 +--- a/memcheck/tests/badjump2.c ++++ b/memcheck/tests/badjump2.c +@@ -26,7 +26,7 @@ int main(void) + memset(&sigsegv_new, 0, sizeof(sigsegv_new)); + sigsegv_new.sa_handler = SIGSEGV_handler; + sigsegv_new.sa_flags = 0; +-#if !defined(__APPLE__) && !defined(__sun) && !defined(__FreeBSD__) ++#if !defined(__APPLE__) && !defined(__sun) && !defined(__FreeBSD__) && !defined(__sw_64__) + sigsegv_new.sa_restorer = NULL; + #endif + res = sigemptyset( &sigsegv_new.sa_mask ); +diff --git a/memcheck/tests/leak-segv-jmp.c b/memcheck/tests/leak-segv-jmp.c +index 97bddaf23..444aedd61 100644 +--- a/memcheck/tests/leak-segv-jmp.c ++++ b/memcheck/tests/leak-segv-jmp.c +@@ -308,7 +308,9 @@ asm( + " ret\n" + ".previous\n" + ); +- ++#elif defined(VGP_sw64_linux) ++extern UWord do_syscall_WRK(UWord syscall_no, UWord a1, UWord a2, ++ UWord a3, UWord a4, UWord a5, UWord a6); + #else + // Ensure the file compiles even if the syscall nr is not defined. + #ifndef __NR_mprotect +@@ -324,8 +326,6 @@ UWord do_syscall_WRK (UWord syscall_no, + } + #endif + +- +- + char **b10; + char *interior_ptrs[3]; + int mprotect_result = 0; +@@ -470,3 +470,27 @@ int main(void) + + return 0; + } ++ ++/* ++ HACK: The line number recorded in .exp file will be mismatch if we put this ++ code block in top of file, so here we are ++*/ ++#if defined(VGP_sw64_linux) ++#define __NR_mprotect 74 ++asm ( ++ ".text \n\t" ++ ".globl do_syscall_WRK \n\t" ++ ".type do_syscall_WRK, @function \n\t" ++ "do_syscall_WRK: \n\t" ++ " mov $16, $0 \n\t" ++ " mov $17, $16 \n\t" ++ " mov $18, $17 \n\t" ++ " mov $19, $18 \n\t" ++ " mov $20, $19 \n\t" ++ " mov $21, $20 \n\t" ++ " ldl $21, 0($30) \n\t" ++ " sys_call 0x83 \n\t" ++ " ret \n\t" ++ ".previous \n\t" ++); ++#endif +diff --git a/memcheck/tests/leak.h b/memcheck/tests/leak.h +index 79e3cd6ac..16931d272 100644 +--- a/memcheck/tests/leak.h ++++ b/memcheck/tests/leak.h +@@ -143,6 +143,35 @@ + "$8", "$9", "$10", "$11", "$12", "$13", \ + "$14", "$15", "$24", "$25", "$31"); \ + } while (0) ++#elif defined(__sw_64__) ++#define CLEAR_CALLER_SAVED_REGS \ ++ do { \ ++ __asm__ __volatile__ ("ldi $0, 0 \n\t" /* v0 = 0 */ \ ++ "ldi $1, 0 \n\t" /* t0 = 0 */ \ ++ "ldi $2, 0 \n\t" /* t1 = 0 */ \ ++ "ldi $3, 0 \n\t" /* t2 = 0 */ \ ++ "ldi $4, 0 \n\t" /* t3 = 0 */ \ ++ "ldi $5, 0 \n\t" /* t4 = 0 */ \ ++ "ldi $6, 0 \n\t" /* t5 = 0 */ \ ++ "ldi $7, 0 \n\t" /* t6 = 0 */ \ ++ "ldi $8, 0 \n\t" /* t7 = 0 */ \ ++ "ldi $16, 0 \n\t" /* a0 = 0 */ \ ++ "ldi $17, 0 \n\t" /* a1 = 0 */ \ ++ "ldi $18, 0 \n\t" /* a2 = 0 */ \ ++ "ldi $19, 0 \n\t" /* a3 = 0 */ \ ++ "ldi $20, 0 \n\t" /* a4 = 0 */ \ ++ "ldi $21, 0 \n\t" /* a5 = 0 */ \ ++ "ldi $22, 0 \n\t" /* t8 = 0 */ \ ++ "ldi $23, 0 \n\t" /* t9 = 0 */ \ ++ "ldi $24, 0 \n\t" /* t10 = 0 */ \ ++ "ldi $25, 0 \n\t" /* t11 = 0 */ \ ++ "ldi $27, 0 \n\t" /* pv = 0 */ \ ++ "ldi $31, 0 \n\t" /* zero= 0 */ \ ++ : : : "$0", "$1", "$2", "$3", "$4", "$5", "$6", \ ++ "$7", "$8", "$16", "$17", "$18", "$19", \ ++ "$20", "$21", "$22", "$23", "$24", "$25", \ ++ "$27"); \ ++ } while (0) + #elif defined (__clang__) && defined(VGA_x86) + #define CLEAR_CALLER_SAVED_REGS \ + do { \ +diff --git a/memcheck/tests/sigkill.stderr.exp-sw64 b/memcheck/tests/sigkill.stderr.exp-sw64 +new file mode 100644 +index 000000000..f37c709c8 +--- /dev/null ++++ b/memcheck/tests/sigkill.stderr.exp-sw64 +@@ -0,0 +1,197 @@ ++ ++setting signal 1: Success ++getting signal 1: Success ++ ++setting signal 2: Success ++getting signal 2: Success ++ ++setting signal 3: Success ++getting signal 3: Success ++ ++setting signal 4: Success ++getting signal 4: Success ++ ++setting signal 5: Success ++getting signal 5: Success ++ ++setting signal 6: Success ++getting signal 6: Success ++ ++setting signal 7: Success ++getting signal 7: Success ++ ++setting signal 8: Success ++getting signal 8: Success ++ ++setting signal 9: Warning: ignored attempt to set SIGKILL handler in sigaction(); ++ the SIGKILL signal is uncatchable ++Invalid argument ++getting signal 9: Success ++ ++setting signal 10: Success ++getting signal 10: Success ++ ++setting signal 11: Success ++getting signal 11: Success ++ ++setting signal 12: Success ++getting signal 12: Success ++ ++setting signal 13: Success ++getting signal 13: Success ++ ++setting signal 14: Success ++getting signal 14: Success ++ ++setting signal 15: Success ++getting signal 15: Success ++ ++setting signal 16: Success ++getting signal 16: Success ++ ++setting signal 17: Warning: ignored attempt to set SIGSTOP handler in sigaction(); ++ the SIGSTOP signal is uncatchable ++Invalid argument ++getting signal 17: Success ++ ++setting signal 18: Success ++getting signal 18: Success ++ ++setting signal 19: Success ++getting signal 19: Success ++ ++setting signal 20: Success ++getting signal 20: Success ++ ++setting signal 21: Success ++getting signal 21: Success ++ ++setting signal 22: Success ++getting signal 22: Success ++ ++setting signal 23: Success ++getting signal 23: Success ++ ++setting signal 24: Success ++getting signal 24: Success ++ ++setting signal 25: Success ++getting signal 25: Success ++ ++setting signal 26: Success ++getting signal 26: Success ++ ++setting signal 27: Success ++getting signal 27: Success ++ ++setting signal 28: Success ++getting signal 28: Success ++ ++setting signal 29: Success ++getting signal 29: Success ++ ++setting signal 30: Success ++getting signal 30: Success ++ ++setting signal 31: Success ++getting signal 31: Success ++ ++setting signal 34: Success ++getting signal 34: Success ++ ++setting signal 35: Success ++getting signal 35: Success ++ ++setting signal 36: Success ++getting signal 36: Success ++ ++setting signal 37: Success ++getting signal 37: Success ++ ++setting signal 38: Success ++getting signal 38: Success ++ ++setting signal 39: Success ++getting signal 39: Success ++ ++setting signal 40: Success ++getting signal 40: Success ++ ++setting signal 41: Success ++getting signal 41: Success ++ ++setting signal 42: Success ++getting signal 42: Success ++ ++setting signal 43: Success ++getting signal 43: Success ++ ++setting signal 44: Success ++getting signal 44: Success ++ ++setting signal 45: Success ++getting signal 45: Success ++ ++setting signal 46: Success ++getting signal 46: Success ++ ++setting signal 47: Success ++getting signal 47: Success ++ ++setting signal 48: Success ++getting signal 48: Success ++ ++setting signal 49: Success ++getting signal 49: Success ++ ++setting signal 50: Success ++getting signal 50: Success ++ ++setting signal 51: Success ++getting signal 51: Success ++ ++setting signal 52: Success ++getting signal 52: Success ++ ++setting signal 53: Success ++getting signal 53: Success ++ ++setting signal 54: Success ++getting signal 54: Success ++ ++setting signal 55: Success ++getting signal 55: Success ++ ++setting signal 56: Success ++getting signal 56: Success ++ ++setting signal 57: Success ++getting signal 57: Success ++ ++setting signal 58: Success ++getting signal 58: Success ++ ++setting signal 59: Success ++getting signal 59: Success ++ ++setting signal 60: Success ++getting signal 60: Success ++ ++setting signal 61: Success ++getting signal 61: Success ++ ++setting signal 62: Success ++getting signal 62: Success ++ ++setting signal 65: Invalid argument ++getting signal 65: Invalid argument ++ ++ ++HEAP SUMMARY: ++ in use at exit: ... bytes in ... blocks ++ total heap usage: ... allocs, ... frees, ... bytes allocated ++ ++For a detailed leak analysis, rerun with: --leak-check=full ++ ++For lists of detected and suppressed errors, rerun with: -s ++ERROR SUMMARY: 0 errors from 0 contexts (suppressed: 0 from 0) +diff --git a/memcheck/tests/sigprocmask.stderr.exp-sw64 b/memcheck/tests/sigprocmask.stderr.exp-sw64 +new file mode 100644 +index 000000000..bf809cab6 +--- /dev/null ++++ b/memcheck/tests/sigprocmask.stderr.exp-sw64 +@@ -0,0 +1,6 @@ ++before ++11111111 89abcdef 22222222 33333333 0 44444444 ++after1 ++11111111 89abcdef 22222222 33333333 0 44444444 ++after2 ++11111111 89abcdef 22222222 33333333 89aaccef 66666666 +diff --git a/memcheck/tests/sw64/Makefile b/memcheck/tests/sw64/Makefile +new file mode 100644 +index 000000000..eb94182e9 +--- /dev/null ++++ b/memcheck/tests/sw64/Makefile +@@ -0,0 +1,871 @@ ++# Makefile.in generated by automake 1.16.5 from Makefile.am. ++# memcheck/tests/sw64/Makefile. Generated from Makefile.in by configure. ++ ++# Copyright (C) 1994-2021 Free Software Foundation, Inc. ++ ++# This Makefile.in is free software; the Free Software Foundation ++# gives unlimited permission to copy and/or distribute it, ++# with or without modifications, as long as this notice is preserved. ++ ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY, to the extent permitted by law; without ++# even the implied warranty of MERCHANTABILITY or FITNESS FOR A ++# PARTICULAR PURPOSE. ++ ++ ++ ++# This file is used for tool tests, and also in perf/Makefile.am. ++ ++# This file should be included (directly or indirectly) by every ++# Makefile.am that builds programs. And also the top-level Makefile.am. ++ ++#---------------------------------------------------------------------------- ++# Global stuff ++#---------------------------------------------------------------------------- ++ ++ ++am__is_gnu_make = { \ ++ if test -z '$(MAKELEVEL)'; then \ ++ false; \ ++ elif test -n '$(MAKE_HOST)'; then \ ++ true; \ ++ elif test -n '$(MAKE_VERSION)' && test -n '$(CURDIR)'; then \ ++ true; \ ++ else \ ++ false; \ ++ fi; \ ++} ++am__make_running_with_option = \ ++ case $${target_option-} in \ ++ ?) ;; \ ++ *) echo "am__make_running_with_option: internal error: invalid" \ ++ "target option '$${target_option-}' specified" >&2; \ ++ exit 1;; \ ++ esac; \ ++ has_opt=no; \ ++ sane_makeflags=$$MAKEFLAGS; \ ++ if $(am__is_gnu_make); then \ ++ sane_makeflags=$$MFLAGS; \ ++ else \ ++ case $$MAKEFLAGS in \ ++ *\\[\ \ ]*) \ ++ bs=\\; \ ++ sane_makeflags=`printf '%s\n' "$$MAKEFLAGS" \ ++ | sed "s/$$bs$$bs[$$bs $$bs ]*//g"`;; \ ++ esac; \ ++ fi; \ ++ skip_next=no; \ ++ strip_trailopt () \ ++ { \ ++ flg=`printf '%s\n' "$$flg" | sed "s/$$1.*$$//"`; \ ++ }; \ ++ for flg in $$sane_makeflags; do \ ++ test $$skip_next = yes && { skip_next=no; continue; }; \ ++ case $$flg in \ ++ *=*|--*) continue;; \ ++ -*I) strip_trailopt 'I'; skip_next=yes;; \ ++ -*I?*) strip_trailopt 'I';; \ ++ -*O) strip_trailopt 'O'; skip_next=yes;; \ ++ -*O?*) strip_trailopt 'O';; \ ++ -*l) strip_trailopt 'l'; skip_next=yes;; \ ++ -*l?*) strip_trailopt 'l';; \ ++ -[dEDm]) skip_next=yes;; \ ++ -[JT]) skip_next=yes;; \ ++ esac; \ ++ case $$flg in \ ++ *$$target_option*) has_opt=yes; break;; \ ++ esac; \ ++ done; \ ++ test $$has_opt = yes ++am__make_dryrun = (target_option=n; $(am__make_running_with_option)) ++am__make_keepgoing = (target_option=k; $(am__make_running_with_option)) ++pkgdatadir = $(datadir)/valgrind ++pkgincludedir = $(includedir)/valgrind ++pkglibdir = $(libdir)/valgrind ++pkglibexecdir = $(libexecdir)/valgrind ++am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd ++install_sh_DATA = $(install_sh) -c -m 644 ++install_sh_PROGRAM = $(install_sh) -c ++install_sh_SCRIPT = $(install_sh) -c ++INSTALL_HEADER = $(INSTALL_DATA) ++transform = $(program_transform_name) ++NORMAL_INSTALL = : ++PRE_INSTALL = : ++POST_INSTALL = : ++NORMAL_UNINSTALL = : ++PRE_UNINSTALL = : ++POST_UNINSTALL = : ++build_triplet = sw_64-sunway-linux-gnu ++host_triplet = sw_64-sunway-linux-gnu ++#am__append_1 = -Wno-cast-align -Wno-self-assign \ ++# -Wno-tautological-compare ++ ++##am__append_2 = -Wno-expansion-to-defined ++#am__append_3 = -DVGABI_ ++##am__append_4 = -DVGABI_ ++#am__append_5 = -Wl,-M,$(top_srcdir)/solaris/vgpreload-solaris.mapfile ++ ++# The Android toolchain includes all kinds of stdlib helpers present in ++# bionic which is bad because we are not linking with it and the Android ++# linker will panic. ++#am__append_6 = -nostdlib ++#am__append_7 = -DVGA_SEC_=1 \ ++# -DVGP_SEC_sw64_linux=1 ++ ++#am__append_8 = -DVGABI_ ++ ++# Make sure that all test programs have threaded errno. ++# Disable largefile support as there are test cases explicitly enabling it. ++#am__append_9 = -D_REENTRANT ++#am__append_10 = -Wno-format-extra-args \ ++# -Wno-literal-range \ ++# -Wno-tautological-constant-out-of-range-compare \ ++# -Wno-self-assign -Wno-string-plus-int \ ++# -Wno-uninitialized -Wno-unused-value # \ ++# clang 3.0.0 ++#am__append_11 = -Wno-unused-private-field # drd/tests/tsan_unittest.cpp ++subdir = memcheck/tests/sw64 ++ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 ++am__aclocal_m4_deps = $(top_srcdir)/configure.ac ++am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \ ++ $(ACLOCAL_M4) ++DIST_COMMON = $(srcdir)/Makefile.am $(dist_noinst_SCRIPTS) \ ++ $(am__DIST_COMMON) ++mkinstalldirs = $(install_sh) -d ++CONFIG_HEADER = $(top_builddir)/config.h ++CONFIG_CLEAN_FILES = ++CONFIG_CLEAN_VPATH_FILES = ++SCRIPTS = $(dist_noinst_SCRIPTS) ++AM_V_P = $(am__v_P_$(V)) ++am__v_P_ = $(am__v_P_$(AM_DEFAULT_VERBOSITY)) ++am__v_P_0 = false ++am__v_P_1 = : ++AM_V_GEN = $(am__v_GEN_$(V)) ++am__v_GEN_ = $(am__v_GEN_$(AM_DEFAULT_VERBOSITY)) ++am__v_GEN_0 = @echo " GEN " $@; ++am__v_GEN_1 = ++AM_V_at = $(am__v_at_$(V)) ++am__v_at_ = $(am__v_at_$(AM_DEFAULT_VERBOSITY)) ++am__v_at_0 = @ ++am__v_at_1 = ++SOURCES = ++DIST_SOURCES = ++am__can_run_installinfo = \ ++ case $$AM_UPDATE_INFO_DIR in \ ++ n|no|NO) false;; \ ++ *) (install-info --version) >/dev/null 2>&1;; \ ++ esac ++am__tagged_files = $(HEADERS) $(SOURCES) $(TAGS_FILES) $(LISP) ++am__DIST_COMMON = $(srcdir)/Makefile.in $(top_srcdir)/Makefile.all.am \ ++ $(top_srcdir)/Makefile.tool-tests.am ++DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST) ++ACLOCAL = ${SHELL} '/home/zlh/valgrind-sw/valgrind-3.19.0/missing' aclocal-1.16 ++AMTAR = $${TAR-tar} ++AM_DEFAULT_VERBOSITY = 1 ++AR = /usr/bin/ar ++AUTOCONF = ${SHELL} '/home/zlh/valgrind-sw/valgrind-3.19.0/missing' autoconf ++AUTOHEADER = ${SHELL} '/home/zlh/valgrind-sw/valgrind-3.19.0/missing' autoheader ++AUTOMAKE = ${SHELL} '/home/zlh/valgrind-sw/valgrind-3.19.0/missing' automake-1.16 ++AWK = gawk ++BOOST_CFLAGS = ++BOOST_LIBS = ++CC = gcc ++CCAS = gcc ++CCASDEPMODE = depmode=gcc3 ++CCASFLAGS = ++CCDEPMODE = depmode=gcc3 ++CFLAGS = ++CFLAGS_MPI = -g -O -fno-omit-frame-pointer -Wall -fpic ++CPP = gcc -E ++CPPFLAGS = ++CSCOPE = cscope ++CTAGS = ctags ++CXX = g++ ++CXXDEPMODE = depmode=gcc3 ++CXXFLAGS = ++CYGPATH_W = echo ++DEFAULT_SUPP = ./xfree-3.supp ./xfree-4.supp glibc-2.X-drd.supp glibc-2.X-helgrind.supp glibc-2.X.supp ++DEFS = -DHAVE_CONFIG_H ++DEPDIR = .deps ++DIFF = diff -u ++DIS_PATH = ++ECHO_C = ++ECHO_N = -n ++ECHO_T = ++EGREP = /usr/bin/grep -E ++ETAGS = etags ++EXEEXT = ++FLAG_FALIGNED_NEW = -faligned-new ++FLAG_FINLINE_FUNCTIONS = -finline-functions ++FLAG_FNO_IPA_ICF = -fno-ipa-icf ++FLAG_FNO_STACK_PROTECTOR = -fno-stack-protector ++FLAG_FSANITIZE = ++FLAG_FSIZED_DEALLOCATION = -fsized-deallocation ++FLAG_M32 = ++FLAG_M64 = ++FLAG_MLONG_DOUBLE_128 = -mlong-double-128 ++FLAG_MMMX = ++FLAG_MSA = ++FLAG_MSSE = ++FLAG_NO_BUILD_ID = ++FLAG_NO_PIE = -no-pie ++FLAG_OCTEON = ++FLAG_OCTEON2 = ++FLAG_PIE = -pie ++FLAG_T_TEXT = -Ttext-segment ++FLAG_UNLIMITED_INLINE_UNIT_GROWTH = --param inline-unit-growth=900 ++FLAG_W_CAST_ALIGN = -Wcast-align ++FLAG_W_CAST_QUAL = -Wcast-qual ++FLAG_W_EMPTY_BODY = -Wempty-body ++FLAG_W_ENUM_CONVERSION = -Wenum-conversion ++FLAG_W_EXTRA = -Wextra ++FLAG_W_FORMAT = -Wformat ++FLAG_W_FORMAT_SECURITY = -Wformat-security ++FLAG_W_FORMAT_SIGNEDNESS = -Wformat-signedness ++FLAG_W_IGNORED_QUALIFIERS = -Wignored-qualifiers ++FLAG_W_IMPLICIT_FALLTHROUGH = -Wimplicit-fallthrough=2 ++FLAG_W_LOGICAL_OP = -Wlogical-op ++FLAG_W_MISSING_PARAMETER_TYPE = -Wmissing-parameter-type ++FLAG_W_NO_EXPANSION_TO_DEFINED = -Wno-expansion-to-defined ++FLAG_W_NO_INFINITE_RECURSION = ++FLAG_W_NO_MEMSET_TRANSPOSED_ARGS = -Wno-memset-transposed-args ++FLAG_W_NO_MISMATCHED_NEW_DELETE = ++FLAG_W_NO_NONNULL = -Wno-nonnull ++FLAG_W_NO_OVERFLOW = -Wno-overflow ++FLAG_W_NO_POINTER_SIGN = -Wno-pointer-sign ++FLAG_W_NO_STATIC_LOCAL_IN_INLINE = ++FLAG_W_NO_UNINITIALIZED = -Wno-uninitialized ++FLAG_W_NO_UNUSED_FUNCTION = -Wno-unused-function ++FLAG_W_OLD_STYLE_DECLARATION = -Wold-style-declaration ++FLAG_W_WRITE_STRINGS = -Wwrite-strings ++GDB = /usr/local/bin/gdb ++GLIBC_LIBC_PATH = */lib*/libc.so.6 ++GLIBC_LIBPTHREAD_PATH = */lib*/libc.so.6 ++GLIBC_VERSION = 2.34 ++GREP = /usr/bin/grep ++HWCAP_HAS_ALTIVEC = ++HWCAP_HAS_DFP = ++HWCAP_HAS_HTM = ++HWCAP_HAS_ISA_2_05 = ++HWCAP_HAS_ISA_2_06 = ++HWCAP_HAS_ISA_2_07 = ++HWCAP_HAS_ISA_3_00 = ++HWCAP_HAS_ISA_3_1 = ++HWCAP_HAS_MMA = ++HWCAP_HAS_VSX = ++INSTALL = /usr/bin/install -c ++INSTALL_DATA = ${INSTALL} -m 644 ++INSTALL_PROGRAM = ${INSTALL} ++INSTALL_SCRIPT = ${INSTALL} ++INSTALL_STRIP_PROGRAM = $(install_sh) -c -s ++LDFLAGS = ++LDFLAGS_MPI = -fpic -shared ++LIBOBJS = ++LIBS = ++LIB_UBSAN = ++LN_S = ln -s ++LTLIBOBJS = ++LTO_AR = /usr/bin/ar ++LTO_CFLAGS = ++LTO_RANLIB = ranlib ++MAINT = # ++MAKEINFO = ${SHELL} '/home/zlh/valgrind-sw/valgrind-3.19.0/missing' makeinfo ++MKDIR_P = /usr/bin/mkdir -p ++MPI_CC = /usr/bin/mpicc ++OBJEXT = o ++PACKAGE = valgrind ++PACKAGE_BUGREPORT = valgrind-users@lists.sourceforge.net ++PACKAGE_NAME = Valgrind ++PACKAGE_STRING = Valgrind 3.19.0-sw1.0.0 ++PACKAGE_TARNAME = valgrind ++PACKAGE_URL = ++PACKAGE_VERSION = 3.19.0-sw1.0.0 ++PATH_SEPARATOR = : ++PERL = /usr/bin/perl ++PREFERRED_STACK_BOUNDARY_2 = ++RANLIB = ranlib ++SED = /usr/bin/sed ++SET_MAKE = ++SHELL = /bin/sh ++SOLARIS_UNDEF_LARGESOURCE = ++STRIP = ++VALT_LOAD_ADDRESS_PRI = 0x58000000 ++VALT_LOAD_ADDRESS_SEC = 0xUNSET ++VERSION = 3.19.0-sw1.0.0 ++VGCONF_ABI = ++VGCONF_ARCH_PRI = sw64 ++VGCONF_ARCH_SEC = ++VGCONF_OS = linux ++VGCONF_PLATFORM_PRI_CAPS = SW64_LINUX ++VGCONF_PLATFORM_SEC_CAPS = ++VGCONF_PLATVARIANT = vanilla ++VG_DATE = 11 Apr 2022 ++VG_TMPDIR = /tmp ++VG_VER_MAJOR = 3 ++VG_VER_MINOR = 19 ++XCODE_DIR = ++XCRUN = ++abs_builddir = /home/zlh/valgrind-sw/valgrind-3.19.0/memcheck/tests/sw64 ++abs_srcdir = /home/zlh/valgrind-sw/valgrind-3.19.0/memcheck/tests/sw64 ++abs_top_builddir = /home/zlh/valgrind-sw/valgrind-3.19.0 ++abs_top_srcdir = /home/zlh/valgrind-sw/valgrind-3.19.0 ++ac_ct_CC = gcc ++ac_ct_CXX = g++ ++am__include = include ++am__leading_dot = . ++am__quote = ++am__tar = $${TAR-tar} chof - "$$tardir" ++am__untar = $${TAR-tar} xf - ++bindir = ${exec_prefix}/bin ++build = sw_64-sunway-linux-gnu ++build_alias = ++build_cpu = sw_64 ++build_os = linux-gnu ++build_vendor = sunway ++builddir = . ++datadir = ${datarootdir} ++datarootdir = ${prefix}/share ++docdir = ${datarootdir}/doc/${PACKAGE_TARNAME} ++dvidir = ${docdir} ++exec_prefix = ${prefix} ++host = sw_64-sunway-linux-gnu ++host_alias = ++host_cpu = sw_64 ++host_os = linux-gnu ++host_vendor = sunway ++htmldir = ${docdir} ++includedir = ${prefix}/include ++infodir = ${datarootdir}/info ++install_sh = ${SHELL} /home/zlh/valgrind-sw/valgrind-3.19.0/install-sh ++libdir = ${exec_prefix}/lib ++libexecdir = ${exec_prefix}/libexec ++localedir = ${datarootdir}/locale ++localstatedir = ${prefix}/var ++mandir = ${datarootdir}/man ++mkdir_p = $(MKDIR_P) ++oldincludedir = /usr/include ++pdfdir = ${docdir} ++prefix = /usr/local ++program_transform_name = s,x,x, ++psdir = ${docdir} ++runstatedir = ${localstatedir}/run ++sbindir = ${exec_prefix}/sbin ++sharedstatedir = ${prefix}/com ++srcdir = . ++sysconfdir = ${prefix}/etc ++target_alias = ++top_build_prefix = ../../../ ++top_builddir = ../../.. ++top_srcdir = ../../.. ++inplacedir = $(top_builddir)/.in_place ++ ++#---------------------------------------------------------------------------- ++# Flags ++#---------------------------------------------------------------------------- ++ ++# Baseline flags for all compilations. Aim here is to maximise ++# performance and get whatever useful warnings we can out of gcc. ++# -fno-builtin is important for defeating LLVM's idiom recognition ++# that somehow causes VG_(memset) to get into infinite recursion. ++AM_CFLAGS_BASE = -O2 -g -Wall -Wmissing-prototypes -Wshadow \ ++ -Wpointer-arith -Wstrict-prototypes -Wmissing-declarations \ ++ -Wcast-align -Wcast-qual -Wwrite-strings \ ++ -Wempty-body -Wformat -Wformat-signedness \ ++ -Wformat-security -Wignored-qualifiers \ ++ -Wmissing-parameter-type -Wlogical-op \ ++ -Wenum-conversion -Wimplicit-fallthrough=2 \ ++ -Wold-style-declaration -finline-functions \ ++ -fno-stack-protector \ ++ -fno-strict-aliasing -fno-builtin $(am__append_1) \ ++ $(am__append_2) ++#ISA_3_0_BUILD_FLAG = -DHAS_XSCVHPDP -DHAS_ISA_3_00 ++ ++# Power ISA flag for use by guest_ppc_helpers.c ++##ISA_3_0_BUILD_FLAG = -DHAS_XSCVHPDP -DHAS_DARN -DHAS_ISA_3_00 ++ISA_3_0_BUILD_FLAG = ++AM_CFLAGS_PSO_BASE = -O -g -fno-omit-frame-pointer -fno-strict-aliasing \ ++ -fpic -fno-builtin -fno-ipa-icf ++ ++#AM_CFLAGS_PSO_BASE = -O -g -fno-omit-frame-pointer -fno-strict-aliasing \ ++# -fpic -fPIC -fno-builtin ++ ++ ++# These flags are used for building the preload shared objects (PSOs). ++# The aim is to give reasonable performance but also to have good ++# stack traces, since users often see stack traces extending ++# into (and through) the preloads. Also, we must use any ++# -mpreferred-stack-boundary flag to build the preload shared ++# objects, since that risks misaligning the client's stack and ++# results in segfaults like (eg) #324050. ++#AM_CFLAGS_PSO_BASE = -dynamic \ ++# -O -g -fno-omit-frame-pointer -fno-strict-aliasing \ ++# -fpic -fPIC -fno-builtin -fno-ipa-icf ++ ++ ++# Flags for specific targets. ++# ++# Nb: the AM_CPPFLAGS_* values are suitable for building tools and auxprogs. ++# For building the core, coregrind/Makefile.am files add some extra things. ++AM_CPPFLAGS_SW64_LINUX = -I$(top_srcdir) \ ++ -I$(top_srcdir)/include -I$(top_builddir)/include \ ++ -I$(top_srcdir)/VEX/pub -I$(top_builddir)/VEX/pub \ ++ -DVGA_sw64=1 -DVGO_linux=1 \ ++ -DVGP_sw64_linux=1 \ ++ -DVGPV_sw64_linux_vanilla=1 \ ++ $(am__append_3) ++#AM_CPPFLAGS_ = \ ++# -I$(top_srcdir) \ ++# -I$(top_srcdir)/include \ ++# -I$(top_builddir)/include \ ++# -I$(top_srcdir)/VEX/pub \ ++# -I$(top_builddir)/VEX/pub \ ++# -DVGA_=1 \ ++# -DVGO_linux=1 \ ++# -DVGP__linux=1 \ ++# -DVGPV__linux_vanilla=1 \ ++# $(am__append_4) ++AM_FLAG_M3264_X86_LINUX = ++AM_CFLAGS_X86_LINUX = \ ++ $(AM_CFLAGS_BASE) -fomit-frame-pointer ++ ++AM_CFLAGS_PSO_X86_LINUX = $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE) ++AM_CCASFLAGS_X86_LINUX = -g ++AM_FLAG_M3264_AMD64_LINUX = ++AM_CFLAGS_AMD64_LINUX = \ ++ $(AM_CFLAGS_BASE) -fomit-frame-pointer ++ ++AM_CFLAGS_PSO_AMD64_LINUX = $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE) ++AM_CCASFLAGS_AMD64_LINUX = -g ++AM_FLAG_M3264_PPC32_LINUX = ++AM_CFLAGS_PPC32_LINUX = $(AM_CFLAGS_BASE) ++AM_CFLAGS_PSO_PPC32_LINUX = $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE) ++AM_CCASFLAGS_PPC32_LINUX = -g ++AM_FLAG_M3264_PPC64BE_LINUX = ++AM_CFLAGS_PPC64BE_LINUX = $(AM_CFLAGS_BASE) ++AM_CFLAGS_PSO_PPC64BE_LINUX = $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE) ++AM_CCASFLAGS_PPC64BE_LINUX = -g ++AM_FLAG_M3264_PPC64LE_LINUX = ++AM_CFLAGS_PPC64LE_LINUX = $(AM_CFLAGS_BASE) $(ISA_3_0_BUILD_FLAG) ++AM_CFLAGS_PSO_PPC64LE_LINUX = $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE) ++AM_CCASFLAGS_PPC64LE_LINUX = -g ++AM_FLAG_M3264_X86_FREEBSD = ++AM_CFLAGS_X86_FREEBSD = \ ++ $(AM_CFLAGS_BASE) -fomit-frame-pointer ++ ++AM_CFLAGS_PSO_X86_FREEBSD = $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE) ++AM_CCASFLAGS_X86_FREEBSD = -g ++AM_FLAG_M3264_ARM_LINUX = ++AM_CFLAGS_ARM_LINUX = \ ++ $(AM_CFLAGS_BASE) -marm -mcpu=cortex-a8 ++ ++AM_CFLAGS_PSO_ARM_LINUX = $(AM_CFLAGS_BASE) \ ++ -marm -mcpu=cortex-a8 $(AM_CFLAGS_PSO_BASE) ++ ++AM_CCASFLAGS_ARM_LINUX = \ ++ -marm -mcpu=cortex-a8 -g ++ ++AM_FLAG_M3264_ARM64_LINUX = ++AM_CFLAGS_ARM64_LINUX = $(AM_CFLAGS_BASE) ++AM_CFLAGS_PSO_ARM64_LINUX = $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE) ++AM_CCASFLAGS_ARM64_LINUX = -g ++AM_FLAG_M3264_AMD64_FREEBSD = ++AM_CFLAGS_AMD64_FREEBSD = \ ++ $(AM_CFLAGS_BASE) -fomit-frame-pointer ++ ++AM_CFLAGS_PSO_AMD64_FREEBSD = $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE) ++AM_CCASFLAGS_AMD64_FREEBSD = -g ++AM_FLAG_M3264_X86_DARWIN = -arch i386 ++AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \ ++ -mmacosx-version-min=10.6 \ ++ -fno-pic -fno-PIC ++ ++AM_CFLAGS_PSO_X86_DARWIN = $(AM_CFLAGS_X86_DARWIN) $(AM_CFLAGS_PSO_BASE) ++AM_CCASFLAGS_X86_DARWIN = -arch i386 -g ++AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64 ++AM_CFLAGS_AMD64_DARWIN = $(WERROR) -arch x86_64 $(AM_CFLAGS_BASE) \ ++ -mmacosx-version-min=10.6 ++ ++AM_CFLAGS_PSO_AMD64_DARWIN = $(AM_CFLAGS_AMD64_DARWIN) $(AM_CFLAGS_PSO_BASE) ++AM_CCASFLAGS_AMD64_DARWIN = -arch x86_64 -g ++AM_FLAG_M3264_S390X_LINUX = ++AM_CFLAGS_S390X_LINUX = $(AM_CFLAGS_BASE) -fomit-frame-pointer ++AM_CFLAGS_PSO_S390X_LINUX = $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE) ++AM_CCASFLAGS_S390X_LINUX = -g -mzarch -march=z900 ++AM_FLAG_M3264_MIPS32_LINUX = ++AM_CFLAGS_MIPS32_LINUX = $(AM_CFLAGS_BASE) ++AM_CFLAGS_PSO_MIPS32_LINUX = $(AM_CFLAGS_BASE) \ ++ $(AM_CFLAGS_PSO_BASE) ++ ++AM_CCASFLAGS_MIPS32_LINUX = -g ++AM_FLAG_M3264_NANOMIPS_LINUX = ++AM_CFLAGS_NANOMIPS_LINUX = $(AM_CFLAGS_BASE) -mno-jump-table-opt ++AM_CFLAGS_PSO_NANOMIPS_LINUX = $(AM_CFLAGS_BASE) \ ++ $(AM_CFLAGS_PSO_BASE) ++ ++AM_CCASFLAGS_NANOMIPS_LINUX = -g ++AM_FLAG_M3264_MIPS64_LINUX = ++AM_CFLAGS_MIPS64_LINUX = $(AM_CFLAGS_BASE) ++AM_CFLAGS_PSO_MIPS64_LINUX = $(AM_CFLAGS_BASE) \ ++ $(AM_CFLAGS_PSO_BASE) ++ ++AM_CCASFLAGS_MIPS64_LINUX = -g ++AM_FLAG_M3264_SW64_LINUX = ++AM_CFLAGS_SW64_LINUX = $(AM_CFLAGS_BASE) ++AM_CFLAGS_PSO_SW64_LINUX = $(AM_CFLAGS_BASE) \ ++ $(AM_CFLAGS_PSO_BASE) ++ ++AM_CCASFLAGS_SW64_LINUX = -g ++AM_FLAG_M3264_X86_SOLARIS = ++AM_CFLAGS_X86_SOLARIS = \ ++ $(AM_CFLAGS_BASE) -fomit-frame-pointer ++ ++AM_CFLAGS_PSO_X86_SOLARIS = $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE) ++AM_CCASFLAGS_X86_SOLARIS = -g -D_ASM ++AM_FLAG_M3264_AMD64_SOLARIS = ++AM_CFLAGS_AMD64_SOLARIS = \ ++ $(AM_CFLAGS_BASE) -fomit-frame-pointer ++ ++AM_CFLAGS_PSO_AMD64_SOLARIS = $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE) ++AM_CCASFLAGS_AMD64_SOLARIS = -g -D_ASM ++ ++# Flags for the primary target. These must be used to build the ++# regtests and performance tests. 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skip_next=no; \ ++ strip_trailopt () \ ++ { \ ++ flg=`printf '%s\n' "$$flg" | sed "s/$$1.*$$//"`; \ ++ }; \ ++ for flg in $$sane_makeflags; do \ ++ test $$skip_next = yes && { skip_next=no; continue; }; \ ++ case $$flg in \ ++ *=*|--*) continue;; \ ++ -*I) strip_trailopt 'I'; skip_next=yes;; \ ++ -*I?*) strip_trailopt 'I';; \ ++ -*O) strip_trailopt 'O'; skip_next=yes;; \ ++ -*O?*) strip_trailopt 'O';; \ ++ -*l) strip_trailopt 'l'; skip_next=yes;; \ ++ -*l?*) strip_trailopt 'l';; \ ++ -[dEDm]) skip_next=yes;; \ ++ -[JT]) skip_next=yes;; \ ++ esac; \ ++ case $$flg in \ ++ *$$target_option*) has_opt=yes; break;; \ ++ esac; \ ++ done; \ ++ test $$has_opt = yes ++am__make_dryrun = (target_option=n; $(am__make_running_with_option)) ++am__make_keepgoing = (target_option=k; $(am__make_running_with_option)) ++pkgdatadir = $(datadir)/@PACKAGE@ ++pkgincludedir = $(includedir)/@PACKAGE@ ++pkglibdir = $(libdir)/@PACKAGE@ ++pkglibexecdir = $(libexecdir)/@PACKAGE@ ++am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd ++install_sh_DATA = $(install_sh) -c -m 644 ++install_sh_PROGRAM = $(install_sh) -c ++install_sh_SCRIPT = $(install_sh) -c ++INSTALL_HEADER = $(INSTALL_DATA) ++transform = $(program_transform_name) ++NORMAL_INSTALL = : ++PRE_INSTALL = : ++POST_INSTALL = : ++NORMAL_UNINSTALL = : ++PRE_UNINSTALL = : ++POST_UNINSTALL = : ++build_triplet = @build@ ++host_triplet = @host@ ++@COMPILER_IS_CLANG_TRUE@am__append_1 = -Wno-cast-align -Wno-self-assign \ ++@COMPILER_IS_CLANG_TRUE@ -Wno-tautological-compare ++ ++@COMPILER_IS_CLANG_TRUE@@VGCONF_OS_IS_DARWIN_FALSE@@VGCONF_OS_IS_FREEBSD_TRUE@am__append_2 = @FLAG_W_NO_EXPANSION_TO_DEFINED@ ++@VGCONF_HAVE_ABI_TRUE@am__append_3 = -DVGABI_@VGCONF_ABI@ ++@VGCONF_HAVE_ABI_TRUE@@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_4 = -DVGABI_@VGCONF_ABI@ ++@SOLARIS_XPG_SYMBOLS_PRESENT_TRUE@am__append_5 = -Wl,-M,$(top_srcdir)/solaris/vgpreload-solaris.mapfile ++ ++# The Android toolchain includes all kinds of stdlib helpers present in ++# bionic which is bad because we are not linking with it and the Android ++# linker will panic. ++@VGCONF_PLATVARIANT_IS_ANDROID_TRUE@am__append_6 = -nostdlib ++@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_7 = -DVGA_SEC_@VGCONF_ARCH_SEC@=1 \ ++@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_SEC_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 ++ ++@VGCONF_HAVE_ABI_TRUE@am__append_8 = -DVGABI_@VGCONF_ABI@ ++ ++# Make sure that all test programs have threaded errno. ++# Disable largefile support as there are test cases explicitly enabling it. ++@VGCONF_OS_IS_SOLARIS_TRUE@am__append_9 = -D_REENTRANT @SOLARIS_UNDEF_LARGESOURCE@ ++@COMPILER_IS_CLANG_TRUE@am__append_10 = -Wno-format-extra-args \ ++@COMPILER_IS_CLANG_TRUE@ -Wno-literal-range \ ++@COMPILER_IS_CLANG_TRUE@ -Wno-tautological-constant-out-of-range-compare \ ++@COMPILER_IS_CLANG_TRUE@ -Wno-self-assign -Wno-string-plus-int \ ++@COMPILER_IS_CLANG_TRUE@ -Wno-uninitialized -Wno-unused-value # \ ++@COMPILER_IS_CLANG_TRUE@ clang 3.0.0 ++@COMPILER_IS_CLANG_TRUE@am__append_11 = -Wno-unused-private-field # drd/tests/tsan_unittest.cpp ++subdir = memcheck/tests/sw64 ++ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 ++am__aclocal_m4_deps = $(top_srcdir)/configure.ac ++am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \ ++ $(ACLOCAL_M4) ++DIST_COMMON = $(srcdir)/Makefile.am $(dist_noinst_SCRIPTS) \ ++ $(am__DIST_COMMON) ++mkinstalldirs = $(install_sh) -d ++CONFIG_HEADER = $(top_builddir)/config.h ++CONFIG_CLEAN_FILES = ++CONFIG_CLEAN_VPATH_FILES = ++SCRIPTS = $(dist_noinst_SCRIPTS) ++AM_V_P = $(am__v_P_@AM_V@) ++am__v_P_ = $(am__v_P_@AM_DEFAULT_V@) ++am__v_P_0 = false ++am__v_P_1 = : ++AM_V_GEN = $(am__v_GEN_@AM_V@) ++am__v_GEN_ = $(am__v_GEN_@AM_DEFAULT_V@) ++am__v_GEN_0 = @echo " GEN " $@; ++am__v_GEN_1 = ++AM_V_at = $(am__v_at_@AM_V@) ++am__v_at_ = $(am__v_at_@AM_DEFAULT_V@) ++am__v_at_0 = @ ++am__v_at_1 = ++SOURCES = ++DIST_SOURCES = ++am__can_run_installinfo = \ ++ case $$AM_UPDATE_INFO_DIR in \ ++ n|no|NO) false;; \ ++ *) (install-info --version) >/dev/null 2>&1;; \ ++ esac ++am__tagged_files = $(HEADERS) $(SOURCES) $(TAGS_FILES) $(LISP) ++am__DIST_COMMON = $(srcdir)/Makefile.in $(top_srcdir)/Makefile.all.am \ ++ $(top_srcdir)/Makefile.tool-tests.am ++DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST) ++ACLOCAL = @ACLOCAL@ ++AMTAR = @AMTAR@ ++AM_DEFAULT_VERBOSITY = @AM_DEFAULT_VERBOSITY@ ++AR = @AR@ ++AUTOCONF = @AUTOCONF@ ++AUTOHEADER = @AUTOHEADER@ ++AUTOMAKE = @AUTOMAKE@ ++AWK = @AWK@ ++BOOST_CFLAGS = @BOOST_CFLAGS@ ++BOOST_LIBS = @BOOST_LIBS@ ++CC = @CC@ ++CCAS = @CCAS@ ++CCASDEPMODE = @CCASDEPMODE@ ++CCASFLAGS = @CCASFLAGS@ ++CCDEPMODE = @CCDEPMODE@ ++CFLAGS = @CFLAGS@ ++CFLAGS_MPI = @CFLAGS_MPI@ ++CPP = @CPP@ ++CPPFLAGS = @CPPFLAGS@ ++CSCOPE = @CSCOPE@ ++CTAGS = @CTAGS@ ++CXX = @CXX@ ++CXXDEPMODE = @CXXDEPMODE@ ++CXXFLAGS = @CXXFLAGS@ ++CYGPATH_W = @CYGPATH_W@ ++DEFAULT_SUPP = @DEFAULT_SUPP@ ++DEFS = @DEFS@ ++DEPDIR = @DEPDIR@ ++DIFF = @DIFF@ ++DIS_PATH = @DIS_PATH@ ++ECHO_C = @ECHO_C@ ++ECHO_N = @ECHO_N@ ++ECHO_T = @ECHO_T@ ++EGREP = @EGREP@ ++ETAGS = @ETAGS@ ++EXEEXT = @EXEEXT@ ++FLAG_FALIGNED_NEW = @FLAG_FALIGNED_NEW@ ++FLAG_FINLINE_FUNCTIONS = @FLAG_FINLINE_FUNCTIONS@ ++FLAG_FNO_IPA_ICF = @FLAG_FNO_IPA_ICF@ ++FLAG_FNO_STACK_PROTECTOR = @FLAG_FNO_STACK_PROTECTOR@ ++FLAG_FSANITIZE = @FLAG_FSANITIZE@ ++FLAG_FSIZED_DEALLOCATION = @FLAG_FSIZED_DEALLOCATION@ ++FLAG_M32 = @FLAG_M32@ ++FLAG_M64 = @FLAG_M64@ ++FLAG_MLONG_DOUBLE_128 = @FLAG_MLONG_DOUBLE_128@ ++FLAG_MMMX = @FLAG_MMMX@ ++FLAG_MSA = @FLAG_MSA@ ++FLAG_MSSE = @FLAG_MSSE@ ++FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@ ++FLAG_NO_PIE = @FLAG_NO_PIE@ ++FLAG_OCTEON = @FLAG_OCTEON@ ++FLAG_OCTEON2 = @FLAG_OCTEON2@ ++FLAG_PIE = @FLAG_PIE@ ++FLAG_T_TEXT = @FLAG_T_TEXT@ ++FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@ ++FLAG_W_CAST_ALIGN = @FLAG_W_CAST_ALIGN@ ++FLAG_W_CAST_QUAL = @FLAG_W_CAST_QUAL@ ++FLAG_W_EMPTY_BODY = @FLAG_W_EMPTY_BODY@ ++FLAG_W_ENUM_CONVERSION = @FLAG_W_ENUM_CONVERSION@ ++FLAG_W_EXTRA = @FLAG_W_EXTRA@ ++FLAG_W_FORMAT = @FLAG_W_FORMAT@ ++FLAG_W_FORMAT_SECURITY = @FLAG_W_FORMAT_SECURITY@ ++FLAG_W_FORMAT_SIGNEDNESS = @FLAG_W_FORMAT_SIGNEDNESS@ ++FLAG_W_IGNORED_QUALIFIERS = @FLAG_W_IGNORED_QUALIFIERS@ ++FLAG_W_IMPLICIT_FALLTHROUGH = @FLAG_W_IMPLICIT_FALLTHROUGH@ ++FLAG_W_LOGICAL_OP = @FLAG_W_LOGICAL_OP@ ++FLAG_W_MISSING_PARAMETER_TYPE = @FLAG_W_MISSING_PARAMETER_TYPE@ ++FLAG_W_NO_EXPANSION_TO_DEFINED = @FLAG_W_NO_EXPANSION_TO_DEFINED@ ++FLAG_W_NO_INFINITE_RECURSION = @FLAG_W_NO_INFINITE_RECURSION@ ++FLAG_W_NO_MEMSET_TRANSPOSED_ARGS = @FLAG_W_NO_MEMSET_TRANSPOSED_ARGS@ ++FLAG_W_NO_MISMATCHED_NEW_DELETE = @FLAG_W_NO_MISMATCHED_NEW_DELETE@ ++FLAG_W_NO_NONNULL = @FLAG_W_NO_NONNULL@ ++FLAG_W_NO_OVERFLOW = @FLAG_W_NO_OVERFLOW@ ++FLAG_W_NO_POINTER_SIGN = @FLAG_W_NO_POINTER_SIGN@ ++FLAG_W_NO_STATIC_LOCAL_IN_INLINE = @FLAG_W_NO_STATIC_LOCAL_IN_INLINE@ ++FLAG_W_NO_UNINITIALIZED = @FLAG_W_NO_UNINITIALIZED@ ++FLAG_W_NO_UNUSED_FUNCTION = @FLAG_W_NO_UNUSED_FUNCTION@ ++FLAG_W_OLD_STYLE_DECLARATION = @FLAG_W_OLD_STYLE_DECLARATION@ ++FLAG_W_WRITE_STRINGS = @FLAG_W_WRITE_STRINGS@ ++GDB = @GDB@ ++GLIBC_LIBC_PATH = @GLIBC_LIBC_PATH@ ++GLIBC_LIBPTHREAD_PATH = @GLIBC_LIBPTHREAD_PATH@ ++GLIBC_VERSION = @GLIBC_VERSION@ ++GREP = @GREP@ ++HWCAP_HAS_ALTIVEC = @HWCAP_HAS_ALTIVEC@ ++HWCAP_HAS_DFP = @HWCAP_HAS_DFP@ ++HWCAP_HAS_HTM = @HWCAP_HAS_HTM@ ++HWCAP_HAS_ISA_2_05 = @HWCAP_HAS_ISA_2_05@ ++HWCAP_HAS_ISA_2_06 = @HWCAP_HAS_ISA_2_06@ ++HWCAP_HAS_ISA_2_07 = @HWCAP_HAS_ISA_2_07@ ++HWCAP_HAS_ISA_3_00 = @HWCAP_HAS_ISA_3_00@ ++HWCAP_HAS_ISA_3_1 = @HWCAP_HAS_ISA_3_1@ ++HWCAP_HAS_MMA = @HWCAP_HAS_MMA@ ++HWCAP_HAS_VSX = @HWCAP_HAS_VSX@ ++INSTALL = @INSTALL@ ++INSTALL_DATA = @INSTALL_DATA@ ++INSTALL_PROGRAM = @INSTALL_PROGRAM@ ++INSTALL_SCRIPT = @INSTALL_SCRIPT@ ++INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@ ++LDFLAGS = @LDFLAGS@ ++LDFLAGS_MPI = @LDFLAGS_MPI@ ++LIBOBJS = @LIBOBJS@ ++LIBS = @LIBS@ ++LIB_UBSAN = @LIB_UBSAN@ ++LN_S = @LN_S@ ++LTLIBOBJS = @LTLIBOBJS@ ++LTO_AR = @LTO_AR@ ++LTO_CFLAGS = @LTO_CFLAGS@ ++LTO_RANLIB = @LTO_RANLIB@ ++MAINT = @MAINT@ ++MAKEINFO = @MAKEINFO@ ++MKDIR_P = @MKDIR_P@ ++MPI_CC = @MPI_CC@ ++OBJEXT = @OBJEXT@ ++PACKAGE = @PACKAGE@ ++PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@ ++PACKAGE_NAME = @PACKAGE_NAME@ ++PACKAGE_STRING = @PACKAGE_STRING@ ++PACKAGE_TARNAME = @PACKAGE_TARNAME@ ++PACKAGE_URL = @PACKAGE_URL@ ++PACKAGE_VERSION = @PACKAGE_VERSION@ ++PATH_SEPARATOR = @PATH_SEPARATOR@ ++PERL = @PERL@ ++PREFERRED_STACK_BOUNDARY_2 = @PREFERRED_STACK_BOUNDARY_2@ ++RANLIB = @RANLIB@ ++SED = @SED@ ++SET_MAKE = @SET_MAKE@ ++SHELL = @SHELL@ ++SOLARIS_UNDEF_LARGESOURCE = @SOLARIS_UNDEF_LARGESOURCE@ ++STRIP = @STRIP@ ++VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@ ++VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@ ++VERSION = @VERSION@ ++VGCONF_ABI = @VGCONF_ABI@ ++VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@ ++VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@ ++VGCONF_OS = @VGCONF_OS@ ++VGCONF_PLATFORM_PRI_CAPS = @VGCONF_PLATFORM_PRI_CAPS@ ++VGCONF_PLATFORM_SEC_CAPS = @VGCONF_PLATFORM_SEC_CAPS@ ++VGCONF_PLATVARIANT = @VGCONF_PLATVARIANT@ ++VG_DATE = @VG_DATE@ ++VG_TMPDIR = @VG_TMPDIR@ ++VG_VER_MAJOR = @VG_VER_MAJOR@ ++VG_VER_MINOR = @VG_VER_MINOR@ ++XCODE_DIR = @XCODE_DIR@ ++XCRUN = @XCRUN@ ++abs_builddir = @abs_builddir@ ++abs_srcdir = @abs_srcdir@ ++abs_top_builddir = @abs_top_builddir@ ++abs_top_srcdir = @abs_top_srcdir@ ++ac_ct_CC = @ac_ct_CC@ ++ac_ct_CXX = @ac_ct_CXX@ ++am__include = @am__include@ ++am__leading_dot = @am__leading_dot@ ++am__quote = @am__quote@ ++am__tar = @am__tar@ ++am__untar = @am__untar@ ++bindir = @bindir@ ++build = @build@ ++build_alias = @build_alias@ ++build_cpu = @build_cpu@ ++build_os = @build_os@ ++build_vendor = @build_vendor@ ++builddir = @builddir@ ++datadir = @datadir@ ++datarootdir = @datarootdir@ ++docdir = @docdir@ ++dvidir = @dvidir@ ++exec_prefix = @exec_prefix@ ++host = @host@ ++host_alias = @host_alias@ ++host_cpu = @host_cpu@ ++host_os = @host_os@ ++host_vendor = @host_vendor@ ++htmldir = @htmldir@ ++includedir = @includedir@ ++infodir = @infodir@ ++install_sh = @install_sh@ ++libdir = @libdir@ ++libexecdir = @libexecdir@ ++localedir = @localedir@ ++localstatedir = @localstatedir@ ++mandir = @mandir@ ++mkdir_p = @mkdir_p@ ++oldincludedir = @oldincludedir@ ++pdfdir = @pdfdir@ ++prefix = @prefix@ ++program_transform_name = @program_transform_name@ ++psdir = @psdir@ ++runstatedir = @runstatedir@ ++sbindir = @sbindir@ ++sharedstatedir = @sharedstatedir@ ++srcdir = @srcdir@ ++sysconfdir = @sysconfdir@ ++target_alias = @target_alias@ ++top_build_prefix = @top_build_prefix@ ++top_builddir = @top_builddir@ ++top_srcdir = @top_srcdir@ ++inplacedir = $(top_builddir)/.in_place ++ ++#---------------------------------------------------------------------------- ++# Flags ++#---------------------------------------------------------------------------- ++ ++# Baseline flags for all compilations. Aim here is to maximise ++# performance and get whatever useful warnings we can out of gcc. ++# -fno-builtin is important for defeating LLVM's idiom recognition ++# that somehow causes VG_(memset) to get into infinite recursion. ++AM_CFLAGS_BASE = -O2 -g -Wall -Wmissing-prototypes -Wshadow \ ++ -Wpointer-arith -Wstrict-prototypes -Wmissing-declarations \ ++ @FLAG_W_CAST_ALIGN@ @FLAG_W_CAST_QUAL@ @FLAG_W_WRITE_STRINGS@ \ ++ @FLAG_W_EMPTY_BODY@ @FLAG_W_FORMAT@ @FLAG_W_FORMAT_SIGNEDNESS@ \ ++ @FLAG_W_FORMAT_SECURITY@ @FLAG_W_IGNORED_QUALIFIERS@ \ ++ @FLAG_W_MISSING_PARAMETER_TYPE@ @FLAG_W_LOGICAL_OP@ \ ++ @FLAG_W_ENUM_CONVERSION@ @FLAG_W_IMPLICIT_FALLTHROUGH@ \ ++ @FLAG_W_OLD_STYLE_DECLARATION@ @FLAG_FINLINE_FUNCTIONS@ \ ++ @FLAG_FNO_STACK_PROTECTOR@ @FLAG_FSANITIZE@ \ ++ -fno-strict-aliasing -fno-builtin $(am__append_1) \ ++ $(am__append_2) ++@HAS_DARN_FALSE@@HAS_XSCVHPDP_TRUE@ISA_3_0_BUILD_FLAG = -DHAS_XSCVHPDP -DHAS_ISA_3_00 ++ ++# Power ISA flag for use by guest_ppc_helpers.c ++@HAS_DARN_TRUE@@HAS_XSCVHPDP_TRUE@ISA_3_0_BUILD_FLAG = -DHAS_XSCVHPDP -DHAS_DARN -DHAS_ISA_3_00 ++@HAS_XSCVHPDP_FALSE@ISA_3_0_BUILD_FLAG = ++@VGCONF_OS_IS_DARWIN_FALSE@@VGCONF_OS_IS_FREEBSD_FALSE@AM_CFLAGS_PSO_BASE = -O -g -fno-omit-frame-pointer -fno-strict-aliasing \ ++@VGCONF_OS_IS_DARWIN_FALSE@@VGCONF_OS_IS_FREEBSD_FALSE@ -fpic -fno-builtin @FLAG_FNO_IPA_ICF@ ++ ++@VGCONF_OS_IS_DARWIN_FALSE@@VGCONF_OS_IS_FREEBSD_TRUE@AM_CFLAGS_PSO_BASE = -O -g -fno-omit-frame-pointer -fno-strict-aliasing \ ++@VGCONF_OS_IS_DARWIN_FALSE@@VGCONF_OS_IS_FREEBSD_TRUE@ -fpic -fPIC -fno-builtin ++ ++ ++# These flags are used for building the preload shared objects (PSOs). ++# The aim is to give reasonable performance but also to have good ++# stack traces, since users often see stack traces extending ++# into (and through) the preloads. Also, we must use any ++# -mpreferred-stack-boundary flag to build the preload shared ++# objects, since that risks misaligning the client's stack and ++# results in segfaults like (eg) #324050. ++@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PSO_BASE = -dynamic \ ++@VGCONF_OS_IS_DARWIN_TRUE@ -O -g -fno-omit-frame-pointer -fno-strict-aliasing \ ++@VGCONF_OS_IS_DARWIN_TRUE@ -fpic -fPIC -fno-builtin @FLAG_FNO_IPA_ICF@ ++ ++ ++# Flags for specific targets. ++# ++# Nb: the AM_CPPFLAGS_* values are suitable for building tools and auxprogs. ++# For building the core, coregrind/Makefile.am files add some extra things. ++AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = -I$(top_srcdir) \ ++ -I$(top_srcdir)/include -I$(top_builddir)/include \ ++ -I$(top_srcdir)/VEX/pub -I$(top_builddir)/VEX/pub \ ++ -DVGA_@VGCONF_ARCH_PRI@=1 -DVGO_@VGCONF_OS@=1 \ ++ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \ ++ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1 \ ++ $(am__append_3) ++@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \ ++@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \ ++@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \ ++@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \ ++@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \ ++@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \ ++@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \ ++@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGO_@VGCONF_OS@=1 \ ++@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_@VGCONF_ARCH_SEC@_@VGCONF_OS@=1 \ ++@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGPV_@VGCONF_ARCH_SEC@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1 \ ++@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(am__append_4) ++AM_FLAG_M3264_X86_LINUX = @FLAG_M32@ ++AM_CFLAGS_X86_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ ++ $(AM_CFLAGS_BASE) -fomit-frame-pointer ++ ++AM_CFLAGS_PSO_X86_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE) ++AM_CCASFLAGS_X86_LINUX = @FLAG_M32@ -g ++AM_FLAG_M3264_AMD64_LINUX = @FLAG_M64@ ++AM_CFLAGS_AMD64_LINUX = @FLAG_M64@ \ ++ $(AM_CFLAGS_BASE) -fomit-frame-pointer ++ ++AM_CFLAGS_PSO_AMD64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE) ++AM_CCASFLAGS_AMD64_LINUX = @FLAG_M64@ -g ++AM_FLAG_M3264_PPC32_LINUX = @FLAG_M32@ ++AM_CFLAGS_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) ++AM_CFLAGS_PSO_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE) ++AM_CCASFLAGS_PPC32_LINUX = @FLAG_M32@ -g ++AM_FLAG_M3264_PPC64BE_LINUX = @FLAG_M64@ ++AM_CFLAGS_PPC64BE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) ++AM_CFLAGS_PSO_PPC64BE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE) ++AM_CCASFLAGS_PPC64BE_LINUX = @FLAG_M64@ -g ++AM_FLAG_M3264_PPC64LE_LINUX = @FLAG_M64@ ++AM_CFLAGS_PPC64LE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(ISA_3_0_BUILD_FLAG) ++AM_CFLAGS_PSO_PPC64LE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE) ++AM_CCASFLAGS_PPC64LE_LINUX = @FLAG_M64@ -g ++AM_FLAG_M3264_X86_FREEBSD = @FLAG_M32@ ++AM_CFLAGS_X86_FREEBSD = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ ++ $(AM_CFLAGS_BASE) -fomit-frame-pointer ++ ++AM_CFLAGS_PSO_X86_FREEBSD = @FLAG_M32@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE) ++AM_CCASFLAGS_X86_FREEBSD = @FLAG_M32@ -g ++AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@ ++AM_CFLAGS_ARM_LINUX = @FLAG_M32@ \ ++ $(AM_CFLAGS_BASE) -marm -mcpu=cortex-a8 ++ ++AM_CFLAGS_PSO_ARM_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) \ ++ -marm -mcpu=cortex-a8 $(AM_CFLAGS_PSO_BASE) ++ ++AM_CCASFLAGS_ARM_LINUX = @FLAG_M32@ \ ++ -marm -mcpu=cortex-a8 -g ++ ++AM_FLAG_M3264_ARM64_LINUX = @FLAG_M64@ ++AM_CFLAGS_ARM64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) ++AM_CFLAGS_PSO_ARM64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE) ++AM_CCASFLAGS_ARM64_LINUX = @FLAG_M64@ -g ++AM_FLAG_M3264_AMD64_FREEBSD = @FLAG_M64@ ++AM_CFLAGS_AMD64_FREEBSD = @FLAG_M64@ \ ++ $(AM_CFLAGS_BASE) -fomit-frame-pointer ++ ++AM_CFLAGS_PSO_AMD64_FREEBSD = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE) ++AM_CCASFLAGS_AMD64_FREEBSD = @FLAG_M64@ -g ++AM_FLAG_M3264_X86_DARWIN = -arch i386 ++AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \ ++ -mmacosx-version-min=10.6 \ ++ -fno-pic -fno-PIC ++ ++AM_CFLAGS_PSO_X86_DARWIN = $(AM_CFLAGS_X86_DARWIN) $(AM_CFLAGS_PSO_BASE) ++AM_CCASFLAGS_X86_DARWIN = -arch i386 -g ++AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64 ++AM_CFLAGS_AMD64_DARWIN = $(WERROR) -arch x86_64 $(AM_CFLAGS_BASE) \ ++ -mmacosx-version-min=10.6 ++ ++AM_CFLAGS_PSO_AMD64_DARWIN = $(AM_CFLAGS_AMD64_DARWIN) $(AM_CFLAGS_PSO_BASE) ++AM_CCASFLAGS_AMD64_DARWIN = -arch x86_64 -g ++AM_FLAG_M3264_S390X_LINUX = @FLAG_M64@ ++AM_CFLAGS_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) -fomit-frame-pointer ++AM_CFLAGS_PSO_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE) ++AM_CCASFLAGS_S390X_LINUX = @FLAG_M64@ -g -mzarch -march=z900 ++AM_FLAG_M3264_MIPS32_LINUX = @FLAG_M32@ ++AM_CFLAGS_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) ++AM_CFLAGS_PSO_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) \ ++ 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These must be used to build the ++# regtests and performance tests. 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It ++# shouldn't be needed any more, though. ++ ++#---------------------------------------------------------------------------- ++# noinst_PROGRAMS and noinst_DSYMS targets ++#---------------------------------------------------------------------------- ++ ++# On Darwin, for a program 'p', the DWARF debug info is stored in the ++# directory 'p.dSYM'. This must be generated after the executable is ++# created, with 'dsymutil p'. We could redefine LINK with a script that ++# executes 'dsymutil' after linking, but that's a pain. Instead we use this ++# hook so that every time "make check" is run, we subsequently invoke ++# 'dsymutil' on all the executables that lack a .dSYM directory, or that are ++# newer than their corresponding .dSYM directory. ++build-noinst_DSYMS: $(noinst_DSYMS) ++ for f in $(noinst_DSYMS); do \ ++ if [ ! -e $$f.dSYM -o $$f -nt $$f.dSYM ] ; then \ ++ echo "dsymutil $$f"; \ ++ dsymutil $$f; \ ++ fi; \ ++ done ++ ++# This is used by coregrind/Makefile.am and Makefile.tool.am for doing ++# "in-place" installs. It copies $(noinst_PROGRAMS) into $inplacedir. ++# It needs to be depended on by an 'all-local' rule. ++inplace-noinst_PROGRAMS: $(noinst_PROGRAMS) ++ mkdir -p $(inplacedir); \ ++ for f in $(noinst_PROGRAMS) ; do \ ++ rm -f $(inplacedir)/$$f; \ ++ ln -f -s ../$(subdir)/$$f $(inplacedir); \ ++ done ++ ++# Similar to inplace-noinst_PROGRAMS ++inplace-noinst_DSYMS: build-noinst_DSYMS ++ mkdir -p $(inplacedir); \ ++ for f in $(noinst_DSYMS); do \ ++ rm -f $(inplacedir)/$$f.dSYM; \ ++ ln -f -s ../$(subdir)/$$f.dSYM $(inplacedir); \ ++ done ++ ++# This is used by coregrind/Makefile.am and by /Makefile.am for doing ++# "make install". It copies $(noinst_PROGRAMS) into $prefix/libexec/valgrind/. ++# It needs to be depended on by an 'install-exec-local' rule. ++install-noinst_PROGRAMS: $(noinst_PROGRAMS) ++ $(mkinstalldirs) $(DESTDIR)$(pkglibexecdir); \ ++ for f in $(noinst_PROGRAMS); do \ ++ $(INSTALL_PROGRAM) $$f $(DESTDIR)$(pkglibexecdir); \ ++ done ++ ++# This is used by coregrind/Makefile.am and by /Makefile.am for doing ++# "make uninstall". It removes $(noinst_PROGRAMS) from $prefix/libexec/valgrind/. ++# It needs to be depended on by an 'uninstall-local' rule. ++uninstall-noinst_PROGRAMS: ++ for f in $(noinst_PROGRAMS); do \ ++ rm -f $(DESTDIR)$(pkglibexecdir)/$$f; \ ++ done ++ ++# Similar to install-noinst_PROGRAMS. ++# Nb: we don't use $(INSTALL_PROGRAM) here because it doesn't work with ++# directories. XXX: not sure whether the resulting permissions will be ++# correct when using 'cp -R'... ++install-noinst_DSYMS: build-noinst_DSYMS ++ $(mkinstalldirs) $(DESTDIR)$(pkglibexecdir); \ ++ for f in $(noinst_DSYMS); do \ ++ cp -R $$f.dSYM $(DESTDIR)$(pkglibexecdir); \ ++ done ++ ++# Similar to uninstall-noinst_PROGRAMS. ++uninstall-noinst_DSYMS: ++ for f in $(noinst_DSYMS); do \ ++ rm -f $(DESTDIR)$(pkglibexecdir)/$$f.dSYM; \ ++ done ++ ++# This needs to be depended on by a 'clean-local' rule. ++clean-noinst_DSYMS: ++ for f in $(noinst_DSYMS); do \ ++ rm -rf $$f.dSYM; \ ++ done ++ ++check-local: build-noinst_DSYMS ++ ++clean-local: clean-noinst_DSYMS ++ ++# Tell versions [3.59,3.63) of GNU make to not export all variables. ++# Otherwise a system limit (for SysV at least) may be exceeded. ++.NOEXPORT: +diff --git a/memcheck/tests/sw64/arith-fp.stderr.exp b/memcheck/tests/sw64/arith-fp.stderr.exp +new file mode 120000 +index 000000000..2283ae8c5 +--- /dev/null ++++ b/memcheck/tests/sw64/arith-fp.stderr.exp +@@ -0,0 +1 @@ ++../../../none/tests/sw64/arith-fp.stderr.exp +\ No newline at end of file +diff --git a/memcheck/tests/sw64/arith-fp.stdout.exp b/memcheck/tests/sw64/arith-fp.stdout.exp +new file mode 120000 +index 000000000..0aba8cf45 +--- /dev/null ++++ b/memcheck/tests/sw64/arith-fp.stdout.exp +@@ -0,0 +1 @@ ++../../../none/tests/sw64/arith-fp.stdout.exp +\ No newline at end of file +diff --git a/memcheck/tests/sw64/arith-fp.stdout.exp-8a b/memcheck/tests/sw64/arith-fp.stdout.exp-8a +new file mode 120000 +index 000000000..89062894c +--- /dev/null ++++ b/memcheck/tests/sw64/arith-fp.stdout.exp-8a +@@ -0,0 +1 @@ ++../../../none/tests/sw64/arith-fp.stdout.exp-8a +\ No newline at end of file +diff --git a/memcheck/tests/sw64/arith-fp.vgtest b/memcheck/tests/sw64/arith-fp.vgtest +new file mode 100644 +index 000000000..c1db70340 +--- /dev/null ++++ b/memcheck/tests/sw64/arith-fp.vgtest +@@ -0,0 +1,3 @@ ++prereq: test -e ../../../none/tests/sw64/arith-fp ++prog: ../../../none/tests/sw64/arith-fp ++vgopts: -q +diff --git a/memcheck/tests/sw64/arith-int-imm.stderr.exp b/memcheck/tests/sw64/arith-int-imm.stderr.exp +new file mode 120000 +index 000000000..9c380d8c0 +--- /dev/null ++++ b/memcheck/tests/sw64/arith-int-imm.stderr.exp +@@ -0,0 +1 @@ ++../../../none/tests/sw64/arith-int-imm.stderr.exp +\ No newline at end of file +diff --git a/memcheck/tests/sw64/arith-int-imm.stdout.exp b/memcheck/tests/sw64/arith-int-imm.stdout.exp +new file mode 120000 +index 000000000..bb5eb65e8 +--- /dev/null ++++ b/memcheck/tests/sw64/arith-int-imm.stdout.exp +@@ -0,0 +1 @@ ++../../../none/tests/sw64/arith-int-imm.stdout.exp +\ No newline at end of file +diff --git a/memcheck/tests/sw64/arith-int-imm.vgtest b/memcheck/tests/sw64/arith-int-imm.vgtest +new file mode 100644 +index 000000000..3104d9d2a +--- /dev/null ++++ b/memcheck/tests/sw64/arith-int-imm.vgtest +@@ -0,0 +1,3 @@ ++prereq: test -e ../../../none/tests/sw64/arith-int-imm ++prog: ../../../none/tests/sw64/arith-int-imm ++vgopts: -q +diff --git a/memcheck/tests/sw64/arith-int-reg.stderr.exp b/memcheck/tests/sw64/arith-int-reg.stderr.exp +new file mode 120000 +index 000000000..dcb40ceca +--- /dev/null ++++ b/memcheck/tests/sw64/arith-int-reg.stderr.exp +@@ -0,0 +1 @@ ++../../../none/tests/sw64/arith-int-reg.stderr.exp +\ No newline at end of file +diff --git a/memcheck/tests/sw64/arith-int-reg.stdout.exp b/memcheck/tests/sw64/arith-int-reg.stdout.exp +new file mode 120000 +index 000000000..80c58b959 +--- /dev/null ++++ b/memcheck/tests/sw64/arith-int-reg.stdout.exp +@@ -0,0 +1 @@ ++../../../none/tests/sw64/arith-int-reg.stdout.exp +\ No newline at end of file +diff --git a/memcheck/tests/sw64/arith-int-reg.vgtest b/memcheck/tests/sw64/arith-int-reg.vgtest +new file mode 100644 +index 000000000..fb7bfade6 +--- /dev/null ++++ b/memcheck/tests/sw64/arith-int-reg.vgtest +@@ -0,0 +1,3 @@ ++prereq: test -e ../../../none/tests/sw64/arith-int-reg ++prog: ../../../none/tests/sw64/arith-int-reg ++vgopts: -q +diff --git a/memcheck/tests/sw64/branch.stderr.exp b/memcheck/tests/sw64/branch.stderr.exp +new file mode 120000 +index 000000000..e1a9340ef +--- /dev/null ++++ b/memcheck/tests/sw64/branch.stderr.exp +@@ -0,0 +1 @@ ++../../../none/tests/sw64/branch.stderr.exp +\ No newline at end of file +diff --git a/memcheck/tests/sw64/branch.stdout.exp b/memcheck/tests/sw64/branch.stdout.exp +new file mode 120000 +index 000000000..f533c62f6 +--- /dev/null ++++ b/memcheck/tests/sw64/branch.stdout.exp +@@ -0,0 +1 @@ ++../../../none/tests/sw64/branch.stdout.exp +\ No newline at end of file +diff --git a/memcheck/tests/sw64/branch.vgtest b/memcheck/tests/sw64/branch.vgtest +new file mode 100644 +index 000000000..c4d9b51b4 +--- /dev/null ++++ b/memcheck/tests/sw64/branch.vgtest +@@ -0,0 +1,3 @@ ++prereq: test -e ../../../none/tests/sw64/branch ++prog: ../../../none/tests/sw64/branch ++vgopts: -q +diff --git a/memcheck/tests/sw64/filter_stderr b/memcheck/tests/sw64/filter_stderr +new file mode 100755 +index 000000000..a778e971f +--- /dev/null ++++ b/memcheck/tests/sw64/filter_stderr +@@ -0,0 +1,3 @@ ++#! /bin/sh ++ ++../filter_stderr "$@" +diff --git a/memcheck/tests/sw64/loadstore-fp.stderr.exp b/memcheck/tests/sw64/loadstore-fp.stderr.exp +new file mode 120000 +index 000000000..3b98563c9 +--- /dev/null ++++ b/memcheck/tests/sw64/loadstore-fp.stderr.exp +@@ -0,0 +1 @@ ++../../../none/tests/sw64/loadstore-fp.stderr.exp +\ No newline at end of file +diff --git a/memcheck/tests/sw64/loadstore-fp.stdout.exp b/memcheck/tests/sw64/loadstore-fp.stdout.exp +new file mode 120000 +index 000000000..2edd1ff27 +--- /dev/null ++++ b/memcheck/tests/sw64/loadstore-fp.stdout.exp +@@ -0,0 +1 @@ ++../../../none/tests/sw64/loadstore-fp.stdout.exp +\ No newline at end of file +diff --git a/memcheck/tests/sw64/loadstore-fp.vgtest b/memcheck/tests/sw64/loadstore-fp.vgtest +new file mode 100644 +index 000000000..436c8fb9c +--- /dev/null ++++ b/memcheck/tests/sw64/loadstore-fp.vgtest +@@ -0,0 +1,3 @@ ++prereq: test -e ../../../none/tests/sw64/loadstore-fp ++prog: ../../../none/tests/sw64/loadstore-fp ++vgopts: -q +diff --git a/memcheck/tests/sw64/stack.stderr.exp b/memcheck/tests/sw64/stack.stderr.exp +new file mode 120000 +index 000000000..ec63fe029 +--- /dev/null ++++ b/memcheck/tests/sw64/stack.stderr.exp +@@ -0,0 +1 @@ ++../../../none/tests/sw64/stack.stderr.exp +\ No newline at end of file +diff --git a/memcheck/tests/sw64/stack.stdout.exp b/memcheck/tests/sw64/stack.stdout.exp +new file mode 120000 +index 000000000..66be6236f +--- /dev/null ++++ b/memcheck/tests/sw64/stack.stdout.exp +@@ -0,0 +1 @@ ++../../../none/tests/sw64/stack.stdout.exp +\ No newline at end of file +diff --git a/memcheck/tests/sw64/stack.vgtest b/memcheck/tests/sw64/stack.vgtest +new file mode 100644 +index 000000000..d361c251e +--- /dev/null ++++ b/memcheck/tests/sw64/stack.vgtest +@@ -0,0 +1,3 @@ ++prereq: test -e ../../../none/tests/sw64/stack ++prog: ../../../none/tests/sw64/stack ++vgopts: -q +diff --git a/memcheck/tests/unit_libcbase.c b/memcheck/tests/unit_libcbase.c +index 0ce65be26..b61b7e034 100644 +--- a/memcheck/tests/unit_libcbase.c ++++ b/memcheck/tests/unit_libcbase.c +@@ -11,7 +11,8 @@ + + /* On PPC, MIPS and ARM64 Linux VKI_PAGE_SIZE is a variable, not a macro. */ + #if defined(VGP_ppc32_linux) || defined(VGP_ppc64be_linux) \ +- || defined(VGP_ppc64le_linux) ++ || defined(VGP_ppc64le_linux) || defined(VGP_sw64_linux) ++// TODO(Shaohua): PAGE_SIZE = 8192 on sw64 + unsigned long VKI_PAGE_SIZE = 1UL << 12; + #elif defined(VGP_arm64_linux) + unsigned long VKI_PAGE_SIZE = 1UL << 16; +diff --git a/memcheck/tests/vbit-test/irops.c b/memcheck/tests/vbit-test/irops.c +index a09470905..171fb0bca 100644 +--- a/memcheck/tests/vbit-test/irops.c ++++ b/memcheck/tests/vbit-test/irops.c +@@ -49,16 +49,16 @@ static irop_t irops[] = { + { DEFOP(Iop_Or1, UNDEF_OR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, + { DEFOP(Iop_Or8, UNDEF_OR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, + { DEFOP(Iop_Or16, UNDEF_OR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, +- { DEFOP(Iop_Or32, UNDEF_OR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, ++ { DEFOP(Iop_Or32, UNDEF_OR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .sw64 = 1 }, + { DEFOP(Iop_Or64, UNDEF_OR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts + { DEFOP(Iop_And1, UNDEF_AND), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, + { DEFOP(Iop_And8, UNDEF_AND), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, + { DEFOP(Iop_And16, UNDEF_AND), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, + { DEFOP(Iop_And32, UNDEF_AND), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, +- { DEFOP(Iop_And64, UNDEF_AND), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, ++ { DEFOP(Iop_And64, UNDEF_AND), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .sw64 = 1 }, + { DEFOP(Iop_Xor8, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, + { DEFOP(Iop_Xor16, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, +- { DEFOP(Iop_Xor32, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, ++ { DEFOP(Iop_Xor32, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .sw64 = 1 }, + { DEFOP(Iop_Xor64, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, + { DEFOP(Iop_Shl8, UNDEF_SHL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 }, + { DEFOP(Iop_Shl16, UNDEF_SHL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 }, +@@ -74,12 +74,14 @@ static irop_t irops[] = { + { DEFOP(Iop_Sar64, UNDEF_SAR), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 1, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32 asserts + { DEFOP(Iop_CmpEQ8, UNDEF_CMP_EQ_NE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, + { DEFOP(Iop_CmpEQ16, UNDEF_CMP_EQ_NE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 }, +- { DEFOP(Iop_CmpEQ32, UNDEF_CMP_EQ_NE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, +- { DEFOP(Iop_CmpEQ64, UNDEF_CMP_EQ_NE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32, mips assert ++ { DEFOP(Iop_CmpEQ32, UNDEF_CMP_EQ_NE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .sw64 = 1 }, ++ { DEFOP(Iop_CmpEQ64, UNDEF_CMP_EQ_NE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1, .sw64 = 1 }, // ppc32, mips assert ++ // + { DEFOP(Iop_CmpNE8, UNDEF_CMP_EQ_NE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, + { DEFOP(Iop_CmpNE16, UNDEF_CMP_EQ_NE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, +- { DEFOP(Iop_CmpNE32, UNDEF_CMP_EQ_NE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, +- { DEFOP(Iop_CmpNE64, UNDEF_CMP_EQ_NE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32, mips assert ++ { DEFOP(Iop_CmpNE32, UNDEF_CMP_EQ_NE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .sw64 = 1 }, ++ { DEFOP(Iop_CmpNE64, UNDEF_CMP_EQ_NE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1, .sw64 = 1 }, // ppc32, mips assert ++ // + { DEFOP(Iop_Not1, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, + { DEFOP(Iop_Not8, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, + { DEFOP(Iop_Not16, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, +@@ -119,13 +121,20 @@ static irop_t irops[] = { + { DEFOP(Iop_PopCount64, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 0 }, + { DEFOP(Iop_PopCount32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 =0, .mips64 = 0 }, + { DEFOP(Iop_CmpLT32S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 =1, .mips64 = 1 }, +- { DEFOP(Iop_CmpLT64S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 1 }, // ppc, mips assert ++ { DEFOP(Iop_CmpLT64S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 1, .sw64 = 1 }, // ppc, mips assert + { DEFOP(Iop_CmpLE32S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 =1, .mips64 = 1 }, +- { DEFOP(Iop_CmpLE64S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 1 }, // ppc, mips assert ++ { DEFOP(Iop_CmpLE64S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 1, .sw64 = 1 }, // ppc, mips assert + { DEFOP(Iop_CmpLT32U, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 =1, .mips64 = 1 }, + { DEFOP(Iop_CmpLT64U, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 1}, // ppc32, mips assert + { DEFOP(Iop_CmpLE32U, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 =1, .mips64 = 1 }, + { DEFOP(Iop_CmpLE64U, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 0 }, // ppc32 asserts ++ { DEFOP(Iop_CmpFUN64, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 0, .sw64 = 1 }, // sw64 asserts ++ { DEFOP(Iop_CmpFLT64, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 0, .sw64 = 1 }, ++ { DEFOP(Iop_CmpFLE64, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 0, .sw64 = 1 }, ++ { DEFOP(Iop_CmpFGT64, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 0, .sw64 = 1 }, ++ { DEFOP(Iop_CmpFGE64, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 0, .sw64 = 1 }, ++ { DEFOP(Iop_CmpFEQ64, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 0, .sw64 = 1 }, ++ { DEFOP(Iop_CmpFNE64, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 0, .sw64 = 1 }, + { DEFOP(Iop_CmpNEZ8, UNDEF_ALL), }, // not supported by mc_translate + { DEFOP(Iop_CmpNEZ16, UNDEF_ALL), }, // not supported by mc_translate + { DEFOP(Iop_CmpNEZ32, UNDEF_ALL), }, // not supported by mc_translate +@@ -218,7 +227,7 @@ static irop_t irops[] = { + { DEFOP(Iop_SqrtF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts + { DEFOP(Iop_SqrtF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 }, + { DEFOP(Iop_SqrtF16, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .arm64 = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, +- { DEFOP(Iop_CmpF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, ++ { DEFOP(Iop_CmpF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1, .sw64 = 1 }, + { DEFOP(Iop_CmpF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, // mips asserts + { DEFOP(Iop_CmpF16, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .arm64 = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, + { DEFOP(Iop_CmpF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, +diff --git a/memcheck/tests/vbit-test/vtest.h b/memcheck/tests/vbit-test/vtest.h +index c724f4142..81a43b1f5 100644 +--- a/memcheck/tests/vbit-test/vtest.h ++++ b/memcheck/tests/vbit-test/vtest.h +@@ -188,6 +188,7 @@ typedef struct { + unsigned x86 : 1; + unsigned mips32 : 1; + unsigned mips64 : 1; ++ unsigned sw64 : 1; + } irop_t; + + +diff --git a/none/tests/Makefile.am b/none/tests/Makefile.am +index c0dd7c21d..b3d0f7802 100644 +--- a/none/tests/Makefile.am ++++ b/none/tests/Makefile.am +@@ -35,7 +35,9 @@ endif + if VGCONF_ARCHS_INCLUDE_NANOMIPS + SUBDIRS += nanomips + endif +- ++if VGCONF_ARCHS_INCLUDE_SW64 ++SUBDIRS += sw64 ++endif + + # OS-specific tests + if VGCONF_OS_IS_LINUX +@@ -73,8 +75,12 @@ endif + if VGCONF_PLATFORMS_INCLUDE_X86_FREEBSD + SUBDIRS += x86-freebsd + endif ++if VGCONF_PLATFORMS_INCLUDE_SW64_LINUX ++SUBDIRS += sw64-linux ++endif + + DIST_SUBDIRS = x86 amd64 ppc32 ppc64 arm arm64 s390x mips32 mips64 nanomips \ ++ sw64 sw64-linux \ + linux darwin solaris freebsd amd64-linux x86-linux amd64-darwin \ + x86-darwin amd64-solaris x86-solaris x86-freebsd scripts . + +@@ -197,6 +203,7 @@ EXTRA_DIST = \ + require-text-symbol-2.stderr.exp-libcso1 \ + require-text-symbol-2.stderr.exp-libcso6 \ + require-text-symbol-2.stderr.exp-freebsd \ ++ require-text-symbol-2.stderr.exp-sw64 \ + res_search.stderr.exp res_search.stdout.exp res_search.vgtest \ + resolv.stderr.exp resolv.stdout.exp resolv.vgtest \ + rlimit_nofile.stderr.exp rlimit_nofile.stdout.exp rlimit_nofile.vgtest \ +@@ -294,8 +301,11 @@ if HAVE_ANSI + check_PROGRAMS += ansi + endif + +-if BUILD_IFUNC_TESTS +- check_PROGRAMS += ifunc ++# Disable ifunc on sw64, as glibc-2.28 does not support that attr. ++if !VGCONF_ARCHS_INCLUDE_SW64 ++ if BUILD_IFUNC_TESTS ++ check_PROGRAMS += ifunc ++ endif + endif + + AM_CFLAGS += $(AM_FLAG_M3264_PRI) +diff --git a/none/tests/allexec_prepare_prereq b/none/tests/allexec_prepare_prereq +index a541f4299..ad016f22b 100755 +--- a/none/tests/allexec_prepare_prereq ++++ b/none/tests/allexec_prepare_prereq +@@ -34,5 +34,6 @@ pair s390x_unexisting_in_32bits s390x + pair arm arm64 + pair mips32 mips64 + pair nanomips nanoMIPS_unexisting_in_64bits ++pair sw64_unexisting_in_32bits sw64 + + exit 0 +diff --git a/none/tests/cmdline2.stdout.exp b/none/tests/cmdline2.stdout.exp +index 241d33afa..7e0fdb4fd 100644 +--- a/none/tests/cmdline2.stdout.exp ++++ b/none/tests/cmdline2.stdout.exp +@@ -167,6 +167,10 @@ usage: valgrind [options] prog-and-args + --stats=no|yes show tool and core statistics [no] + --sanity-level= level of sanity checking to do [1] + --trace-flags= show generated code? (X = 0|1) [00000000] ++ --trace-reg= show register value? (X = 0|1) [000] ++ 001 ....... show control registers ++ 010 ....... show interger registers ++ 100 ....... show float-point registers + --profile-flags= ditto, but for profiling (X = 0|1) [00000000] + --profile-interval= show profile every event checks + [0, meaning only at the end of the run] +@@ -180,6 +184,7 @@ usage: valgrind [options] prog-and-args + --debug-dump=syms mimic /usr/bin/readelf --syms + --debug-dump=line mimic /usr/bin/readelf --debug-dump=line + --debug-dump=frames mimic /usr/bin/readelf --debug-dump=frames ++ --dump-expansion-ratio=no|yes show instruction expansion ratio? [no] + --trace-redir=no|yes show redirection details? [no] + --trace-sched=no|yes show thread scheduler details? [no] + --profile-heap=no|yes profile Valgrind's own space use +diff --git a/none/tests/libvex_test.c b/none/tests/libvex_test.c +index 5b57a4c2e..b3a38536e 100644 +--- a/none/tests/libvex_test.c ++++ b/none/tests/libvex_test.c +@@ -76,6 +76,8 @@ __attribute__((noinline)) static void get_guest_arch(VexArch *ga) + *ga = VexArchMIPS64; + #elif defined(VGA_nanomips) + *ga = VexArchNANOMIPS; ++#elif defined(VGA_sw64) ++ *ga = VexArchSW64; + #else + missing arch; + #endif +@@ -113,6 +115,7 @@ static VexEndness arch_endness (VexArch va) { + else + return VexEndnessBE; + } ++ case VexArchSW64: return VexEndnessLE; + default: failure_exit(); + } + } +@@ -139,6 +142,7 @@ static UInt arch_hwcaps (VexArch va) { + case VexArchMIPS64: return VEX_PRID_COMP_MIPS | VEX_MIPS_HOST_FR; + #endif + case VexArchNANOMIPS: return 0; ++ case VexArchSW64: return VEX_SW64_CORE3; + default: failure_exit(); + } + } +@@ -156,6 +160,7 @@ static Bool mode64 (VexArch va) { + case VexArchMIPS32: return False; + case VexArchMIPS64: return True; + case VexArchNANOMIPS: return False; ++ case VexArchSW64: return True; + default: failure_exit(); + } + } +diff --git a/none/tests/pause.c b/none/tests/pause.c +new file mode 100644 +index 000000000..5276aa651 +--- /dev/null ++++ b/none/tests/pause.c +@@ -0,0 +1,9 @@ ++ ++#include ++#include ++ ++int main() { ++ printf("Will pause()\n"); ++ pause(); ++ return 0; ++} +diff --git a/none/tests/require-text-symbol-2.stderr.exp-sw64 b/none/tests/require-text-symbol-2.stderr.exp-sw64 +new file mode 100644 +index 000000000..18aaa22d7 +--- /dev/null ++++ b/none/tests/require-text-symbol-2.stderr.exp-sw64 +@@ -0,0 +1,9 @@ ++ ++valgrind: Fatal error at when loading library with soname ++valgrind: libc.so.6.1 ++valgrind: Cannot find any text symbol with a name that matches the pattern ++valgrind: doesntexist ++valgrind: as required by a --require-text-symbol= specification. ++ ++valgrind: Cannot continue -- exiting now. ++ +diff --git a/none/tests/simple-func b/none/tests/simple-func +new file mode 100755 +index 0000000000000000000000000000000000000000..276693409c08829f679f81e4330011c9f44e264c +GIT binary patch +literal 9048 +zcmeHN&ubG=5T1=~Q^ndcjiwBJ+3hL)?UpBu1O|(mRx%V+mEqq(y)WIi8|fSv%KdU +z$70>mjC?=U&}!N5X*s^mWW26V0F0DN_V_3Z=Zt%zoqvbwmvEiI)qJ!AZ{9C|{x!ON +zx%U0(xlh}p=Nn(P7EW}bB#8o|fG8jehytR3C?E=m0-}H@APR^Ar=Y;jgO5kUXJ1d@ +zCb>cs5Cud5Q9u+B1w;W+Kok%KL;+Di6c7deR|V*en#_6q1e`zp>i%7E $@.lst ++ ++clean: ++ rm -rf \ ++ *.o \ ++ *.lst \ ++ $(targets) +diff --git a/none/tests/sw64-insn/README.md b/none/tests/sw64-insn/README.md +new file mode 100644 +index 000000000..327e74b36 +--- /dev/null ++++ b/none/tests/sw64-insn/README.md +@@ -0,0 +1,5 @@ ++ ++# How to ++First build all tests with `make`. ++ ++Then run `./test-all.sh` in current directory. +diff --git a/none/tests/sw64-insn/addl-48.S b/none/tests/sw64-insn/addl-48.S +new file mode 100644 +index 000000000..4c7855eae +--- /dev/null ++++ b/none/tests/sw64-insn/addl-48.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 2 ++ ldi $18, 1 ++ addl $17, $18, $16 ++ subl $16, 3, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/addli-119.S b/none/tests/sw64-insn/addli-119.S +new file mode 100644 +index 000000000..372b65721 +--- /dev/null ++++ b/none/tests/sw64-insn/addli-119.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 2 ++ addl $17, 1, $16 ++ subl $16, 3, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/addw-42.S b/none/tests/sw64-insn/addw-42.S +new file mode 100644 +index 000000000..30287b2b6 +--- /dev/null ++++ b/none/tests/sw64-insn/addw-42.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 2 ++ ldi $18, 1 ++ addw $17, $18, $16 ++ subw $16, 3, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/addwi-113.S b/none/tests/sw64-insn/addwi-113.S +new file mode 100644 +index 000000000..64c0f8d63 +--- /dev/null ++++ b/none/tests/sw64-insn/addwi-113.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 2 ++ addw $17, 1, $16 ++ subw $16, 3, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/and-62.S b/none/tests/sw64-insn/and-62.S +new file mode 100644 +index 000000000..4419e1636 +--- /dev/null ++++ b/none/tests/sw64-insn/and-62.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 2 ++ ldi $18, 1 ++ and $17, $18, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/andi-133.S b/none/tests/sw64-insn/andi-133.S +new file mode 100644 +index 000000000..79c192ada +--- /dev/null ++++ b/none/tests/sw64-insn/andi-133.S +@@ -0,0 +1,10 @@ ++ ++ .global _start ++_start: ++ ldi $17, 2 ++ and $17, 1, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/basic-insn-list b/none/tests/sw64-insn/basic-insn-list +new file mode 100644 +index 000000000..1a2fdef92 +--- /dev/null ++++ b/none/tests/sw64-insn/basic-insn-list +@@ -0,0 +1,253 @@ ++sys_call_b-1 ++sys_call-2 ++call-3 ++ret-4 ++jmp-5 ++br-6 ++bsr-7 ++memb-8 ++imemb-9 ++rtc-10 ++rcid-11 ++halt-12 ++rd_f-13 ++wr_f-14 ++rtid-15 ++pri_rcsr-16 ++pri_wcsr-17 ++pri_ret-18 ++lldw-19 ++lldl-20 ++ldw_inc-21 ++ldl_inc-22 ++ldw_dec-23 ++ldl_dec-24 ++ldw_set-25 ++ldl_set-26 ++lstw-27 ++lstl-28 ++ldw_nc-29 ++ldl_nc-30 ++ldd_nc-31 ++stw_nc-32 ++stl_nc-33 ++std_nc-34 ++addw-42 ++subw-43 ++s4addw-44 ++s4subw-45 ++s8addw-46 ++s8subw-47 ++addl-48 ++subl-49 ++s4addl-50 ++s4subl-51 ++s8addl-52 ++s8subl-53 ++mulw-54 ++mull-55 ++umulh-56 ++cmpeq-57 ++cmplt-58 ++cmple-59 ++cmpult-60 ++cmpule-61 ++and-62 ++bic-63 ++bis-64 ++ornot-65 ++xor-66 ++eqv-67 ++inslb-68 ++inslh-69 ++inslw-70 ++insll-71 ++inshb-72 ++inshh-73 ++inshw-74 ++inshl-75 ++sll-76 ++srl-77 ++sra-78 ++extlb-79 ++extlh-80 ++extlw-81 ++extll-82 ++exthb-83 ++exthh-84 ++exthw-85 ++exthl-86 ++ctpop-87 ++ctlz-88 ++cttz-89 ++masklb-90 ++masklh-91 ++masklw-92 ++maskll-93 ++maskhb-94 ++maskhh-95 ++maskhw-96 ++maskhl-97 ++zap-98 ++zapnot-99 ++sextb-100 ++sexth-101 ++cmpgeb-102 ++fimovs-103 ++fimovd-104 ++seleq-105 ++selge-106 ++selgt-107 ++selle-108 ++sellt-109 ++selne-110 ++sellbc-111 ++sellbs-112 ++addwi-113 ++subwi-114 ++s4addwi-115 ++s4subwi-116 ++s8addwi-117 ++s8subwi-118 ++addli-119 ++subli-120 ++s4addli-121 ++s4subli-122 ++s8addli-123 ++s8subli-124 ++mulwi-125 ++mulli-126 ++umulhi-127 ++cmpeqi-128 ++cmplti-129 ++cmplei-130 ++cmpulti-131 ++cmpulei-132 ++andi-133 ++bici-134 ++bisi-135 ++ornoti-136 ++xori-137 ++eqvi-138 ++inslbi-139 ++inslhi-140 ++inslwi-141 ++inslli-142 ++inshbi-143 ++inshhi-144 ++inshwi-145 ++inshli-146 ++slli-147 ++srli-148 ++srai-149 ++extlbi-150 ++extlhi-151 ++extlwi-152 ++extlli-153 ++exthbi-154 ++exthhi-155 ++exthwi-156 ++exthli-157 ++masklbi-158 ++masklhi-159 ++masklwi-160 ++masklli-161 ++maskhbi-162 ++maskhhi-163 ++maskhwi-164 ++maskhli-165 ++zapi-166 ++zapnoti-167 ++sextbi-168 ++sexthi-169 ++cmpgebi-170 ++seleqi-171 ++selgei-172 ++selgti-173 ++sellei-174 ++sellti-175 ++selnei-176 ++sellbci-177 ++sellbsi-178 ++fadds-180 ++faddd-181 ++fsubs-182 ++fsubd-183 ++fmuls-184 ++fmuld-185 ++fdivs-186 ++fdivd-187 ++fsqrts-188 ++fsqrtd-189 ++fcmpeq-190 ++fcmple-191 ++fcmplt-192 ++fcmpun-193 ++fcvtsd-194 ++fcvtds-195 ++fcvtdl_g-196 ++fcvtdl_p-197 ++fcvtdl_z-198 ++fcvtdl_n-199 ++fcvtdl-200 ++fcvtwl-201 ++fcvtlw-202 ++fcvtls-203 ++fcvtld-204 ++fcpys-205 ++fcpyse-206 ++fcpysn-207 ++ifmovs-208 ++ifmovd-209 ++rfpcr-210 ++wfpcr-211 ++setfpec0-212 ++setfpec1-213 ++setfpec2-214 ++setfpec3-215 ++fmas-216 ++fmad-217 ++fmss-218 ++fmsd-219 ++fnmas-220 ++fnmad-221 ++fnmss-222 ++fnmsd-223 ++fseleq-224 ++fselne-225 ++fsellt-226 ++fselle-227 ++fselgt-228 ++fselge-229 ++ldbu-336 ++ldhu-337 ++ldw-338 ++ldl-339 ++ldl_u-340 ++pri_ld-341 ++flds-342 ++fldd-343 ++stb-344 ++sth-345 ++stw-346 ++stl-347 ++stl_u-348 ++pri_st-349 ++fsts-350 ++fstd-351 ++beq-352 ++bne-353 ++blt-354 ++ble-355 ++bgt-356 ++bge-357 ++blbc-358 ++blbs-359 ++fbeq-360 ++fbne-361 ++fblt-362 ++fble-363 ++fbgt-364 ++fbge-365 ++ldi-366 ++ldih-367 +diff --git a/none/tests/sw64-insn/beq-352.S b/none/tests/sw64-insn/beq-352.S +new file mode 100644 +index 000000000..d70369101 +--- /dev/null ++++ b/none/tests/sw64-insn/beq-352.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 2 ++ beq $17, exit ++ ldi $16, 0 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/bge-357.S b/none/tests/sw64-insn/bge-357.S +new file mode 100644 +index 000000000..aa6d20c1f +--- /dev/null ++++ b/none/tests/sw64-insn/bge-357.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, -2 ++ bge $17, exit ++ ldi $16, 0 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/bgt-356.S b/none/tests/sw64-insn/bgt-356.S +new file mode 100644 +index 000000000..9fa0e6a98 +--- /dev/null ++++ b/none/tests/sw64-insn/bgt-356.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, -2 ++ bgt $17, exit ++ ldi $16, 0 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/bic-63.S b/none/tests/sw64-insn/bic-63.S +new file mode 100644 +index 000000000..fc6be15e1 +--- /dev/null ++++ b/none/tests/sw64-insn/bic-63.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 2 ++ ldi $18, 1 ++ bic $17, $18, $16 ++ subl $16, 2 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/bici-134.S b/none/tests/sw64-insn/bici-134.S +new file mode 100644 +index 000000000..131f46882 +--- /dev/null ++++ b/none/tests/sw64-insn/bici-134.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 2 ++ bic $17, 1, $16 ++ subl $16, 2 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/bis-64.S b/none/tests/sw64-insn/bis-64.S +new file mode 100644 +index 000000000..e4c7ff379 +--- /dev/null ++++ b/none/tests/sw64-insn/bis-64.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 2 ++ ldi $18, 1 ++ bis $17, $18, $16 ++ subl $16, 3 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/bisi-135.S b/none/tests/sw64-insn/bisi-135.S +new file mode 100644 +index 000000000..65f299879 +--- /dev/null ++++ b/none/tests/sw64-insn/bisi-135.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 2 ++ bis $17, 1, $16 ++ subl $16, 3 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/blbc-358.S b/none/tests/sw64-insn/blbc-358.S +new file mode 100644 +index 000000000..0540c7e10 +--- /dev/null ++++ b/none/tests/sw64-insn/blbc-358.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0b1001 ++ blbc $17, exit ++ ldi $16, 0 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/blbs-359.S b/none/tests/sw64-insn/blbs-359.S +new file mode 100644 +index 000000000..0540c7e10 +--- /dev/null ++++ b/none/tests/sw64-insn/blbs-359.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0b1001 ++ blbc $17, exit ++ ldi $16, 0 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/ble-355.S b/none/tests/sw64-insn/ble-355.S +new file mode 100644 +index 000000000..fa4293382 +--- /dev/null ++++ b/none/tests/sw64-insn/ble-355.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 2 ++ ble $17, exit ++ ldi $16, 0 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/blt-354.S b/none/tests/sw64-insn/blt-354.S +new file mode 100644 +index 000000000..3691ed586 +--- /dev/null ++++ b/none/tests/sw64-insn/blt-354.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 2 ++ blt $17, exit ++ ldi $16, 0 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/bne-353.S b/none/tests/sw64-insn/bne-353.S +new file mode 100644 +index 000000000..601b65caa +--- /dev/null ++++ b/none/tests/sw64-insn/bne-353.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0 ++ bne $17, exit ++ ldi $16, 0 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/br-6.S b/none/tests/sw64-insn/br-6.S +new file mode 100644 +index 000000000..407b74bc0 +--- /dev/null ++++ b/none/tests/sw64-insn/br-6.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $16, 0 ++ br exit ++ ldi $16, 1 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/bsr-7.S b/none/tests/sw64-insn/bsr-7.S +new file mode 100644 +index 000000000..28abeb3aa +--- /dev/null ++++ b/none/tests/sw64-insn/bsr-7.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $16, 0 ++ bsr $26, exit ++ ldi $16, 1 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/call-3.S b/none/tests/sw64-insn/call-3.S +new file mode 100644 +index 000000000..f0fb2cc7b +--- /dev/null ++++ b/none/tests/sw64-insn/call-3.S +@@ -0,0 +1,16 @@ ++ ++ .global _start ++_start: ++ br $29, 1f ++1: ldgp $29, 0($29) ++ subl $30, 16, $30 ++ mov 0, $15 ++ ++ ldi $16, 0 ++ call $26, exit ++ ldi $16, 1 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/cmpeq-57.S b/none/tests/sw64-insn/cmpeq-57.S +new file mode 100644 +index 000000000..aca76e65a +--- /dev/null ++++ b/none/tests/sw64-insn/cmpeq-57.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 42 ++ ldi $18, 42 ++ cmpeq $17, $18, $16 ++ subl $16, 1 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/cmpeqi-128.S b/none/tests/sw64-insn/cmpeqi-128.S +new file mode 100644 +index 000000000..7cfe65fd4 +--- /dev/null ++++ b/none/tests/sw64-insn/cmpeqi-128.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 42 ++ cmpeq $17, 42, $16 ++ subl $16, 1 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/cmpgeb-102.S b/none/tests/sw64-insn/cmpgeb-102.S +new file mode 100644 +index 000000000..e8f5c7caa +--- /dev/null ++++ b/none/tests/sw64-insn/cmpgeb-102.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0xf0f1f2 ++ ldi $18, 0xf0f2f1 ++ cmpgeb $17, $18, $16 ++ subl $16, 0xfd, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/cmpgebi-170.S b/none/tests/sw64-insn/cmpgebi-170.S +new file mode 100644 +index 000000000..dbe5c2fe2 +--- /dev/null ++++ b/none/tests/sw64-insn/cmpgebi-170.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0xf0 ++ cmpgeb $17, 0xf0, $16 ++ subl $16, 0xff, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/cmple-59.S b/none/tests/sw64-insn/cmple-59.S +new file mode 100644 +index 000000000..baf5d9919 +--- /dev/null ++++ b/none/tests/sw64-insn/cmple-59.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 42 ++ ldi $18, 42 ++ cmple $17, $18, $16 ++ subl $16, 1 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/cmplei-130.S b/none/tests/sw64-insn/cmplei-130.S +new file mode 100644 +index 000000000..b4851cc53 +--- /dev/null ++++ b/none/tests/sw64-insn/cmplei-130.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 42 ++ cmple $17, 42, $16 ++ subl $16, 1 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/cmplt-58.S b/none/tests/sw64-insn/cmplt-58.S +new file mode 100644 +index 000000000..3cee2bcd5 +--- /dev/null ++++ b/none/tests/sw64-insn/cmplt-58.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 42 ++ ldi $18, 43 ++ cmplt $17, $18, $16 ++ subl $16, 1 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/cmplti-129.S b/none/tests/sw64-insn/cmplti-129.S +new file mode 100644 +index 000000000..8822945ed +--- /dev/null ++++ b/none/tests/sw64-insn/cmplti-129.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 42 ++ cmplt $17, 43, $16 ++ subl $16, 1 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/cmpule-61.S b/none/tests/sw64-insn/cmpule-61.S +new file mode 100644 +index 000000000..5a585ae21 +--- /dev/null ++++ b/none/tests/sw64-insn/cmpule-61.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 42 ++ ldi $18, 42 ++ cmpule $17, $18, $16 ++ subl $16, 1 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/cmpulei-132.S b/none/tests/sw64-insn/cmpulei-132.S +new file mode 100644 +index 000000000..e76779678 +--- /dev/null ++++ b/none/tests/sw64-insn/cmpulei-132.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 42 ++ cmpule $17, 42, $16 ++ subl $16, 1 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/cmpult-60.S b/none/tests/sw64-insn/cmpult-60.S +new file mode 100644 +index 000000000..0bde80a7d +--- /dev/null ++++ b/none/tests/sw64-insn/cmpult-60.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 42 ++ ldi $18, 43 ++ cmpult $17, $18, $16 ++ subl $16, 1 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/cmpulti-131.S b/none/tests/sw64-insn/cmpulti-131.S +new file mode 100644 +index 000000000..6d7daffb0 +--- /dev/null ++++ b/none/tests/sw64-insn/cmpulti-131.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 42 ++ cmpult $17, 43, $16 ++ subl $16, 1 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/ctlz-88.S b/none/tests/sw64-insn/ctlz-88.S +new file mode 100644 +index 000000000..b162156d7 +--- /dev/null ++++ b/none/tests/sw64-insn/ctlz-88.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0xf0f1 ++ sll $17, 16, $17 ++ ctlz $17, $16 ++ subl $16, 32, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/ctlzow-247.S b/none/tests/sw64-insn/ctlzow-247.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/ctlzow-247.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/ctpop-87.S b/none/tests/sw64-insn/ctpop-87.S +new file mode 100644 +index 000000000..3373f00d4 +--- /dev/null ++++ b/none/tests/sw64-insn/ctpop-87.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0xf1 ++ ctpop $17, $16 ++ subl $16, 5, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/ctpopow-246.S b/none/tests/sw64-insn/ctpopow-246.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/ctpopow-246.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/cttz-89.S b/none/tests/sw64-insn/cttz-89.S +new file mode 100644 +index 000000000..90e50981f +--- /dev/null ++++ b/none/tests/sw64-insn/cttz-89.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0xf0f0 ++ cttz $17, $16 ++ subl $16, 4, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/eqv-67.S b/none/tests/sw64-insn/eqv-67.S +new file mode 100644 +index 000000000..f2860b8ee +--- /dev/null ++++ b/none/tests/sw64-insn/eqv-67.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 2 ++ ldi $18, 1 ++ eqv $17, $18, $16 ++ addl $16, 4 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/eqvi-138.S b/none/tests/sw64-insn/eqvi-138.S +new file mode 100644 +index 000000000..acf1dd856 +--- /dev/null ++++ b/none/tests/sw64-insn/eqvi-138.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 2 ++ eqv $17, 1, $16 ++ addl $16, 4 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/exthb-83.S b/none/tests/sw64-insn/exthb-83.S +new file mode 100644 +index 000000000..7bf8f50a4 +--- /dev/null ++++ b/none/tests/sw64-insn/exthb-83.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0xf0f1 ++ ldi $18, 0 ++ exthb $17, $18, $16 ++ subl $16, 0xf1 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/exthbi-154.S b/none/tests/sw64-insn/exthbi-154.S +new file mode 100644 +index 000000000..3bdf8c4d8 +--- /dev/null ++++ b/none/tests/sw64-insn/exthbi-154.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0xf0f1 ++ exthb $17, 0, $16 ++ subl $16, 0xf1 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/exthh-84.S b/none/tests/sw64-insn/exthh-84.S +new file mode 100644 +index 000000000..ba913b866 +--- /dev/null ++++ b/none/tests/sw64-insn/exthh-84.S +@@ -0,0 +1,13 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0xf0f1 ++ ldi $18, 0 ++ exthh $17, $18, $16 ++ srl $16, 8, $16 ++ subl $16, 0xf0 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/exthhi-155.S b/none/tests/sw64-insn/exthhi-155.S +new file mode 100644 +index 000000000..6acb0b981 +--- /dev/null ++++ b/none/tests/sw64-insn/exthhi-155.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0xf0f1 ++ exthh $17, 0, $16 ++ srl $16, 8, $16 ++ subl $16, 0xf0 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/exthl-86.S b/none/tests/sw64-insn/exthl-86.S +new file mode 100644 +index 000000000..f8ce13164 +--- /dev/null ++++ b/none/tests/sw64-insn/exthl-86.S +@@ -0,0 +1,13 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0xf0f1 ++ ldi $18, 7 ++ exthl $17, $18, $16 ++ srl $16, 16, $16 ++ subl $16, 0xf0 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/exthli-157.S b/none/tests/sw64-insn/exthli-157.S +new file mode 100644 +index 000000000..4c572a3e7 +--- /dev/null ++++ b/none/tests/sw64-insn/exthli-157.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0xf0f1 ++ exthl $17, 7, $16 ++ srl $16, 16, $16 ++ subl $16, 0xf0 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/exthw-85.S b/none/tests/sw64-insn/exthw-85.S +new file mode 100644 +index 000000000..e52fb45f1 +--- /dev/null ++++ b/none/tests/sw64-insn/exthw-85.S +@@ -0,0 +1,13 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0xf0f1 ++ ldi $18, 7 ++ exthw $17, $18, $16 ++ srl $16, 16, $16 ++ subl $16, 0xf0 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/exthwi-156.S b/none/tests/sw64-insn/exthwi-156.S +new file mode 100644 +index 000000000..ba5beb643 +--- /dev/null ++++ b/none/tests/sw64-insn/exthwi-156.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0xf0f1 ++ exthw $17, 7, $16 ++ srl $16, 16, $16 ++ subl $16, 0xf0 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/extlb-79.S b/none/tests/sw64-insn/extlb-79.S +new file mode 100644 +index 000000000..050cc79cb +--- /dev/null ++++ b/none/tests/sw64-insn/extlb-79.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0xf0f1 ++ ldi $18, 1 ++ extlb $17, $18, $16 ++ subl $16, 0xf0 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/extlbi-150.S b/none/tests/sw64-insn/extlbi-150.S +new file mode 100644 +index 000000000..3be682a7f +--- /dev/null ++++ b/none/tests/sw64-insn/extlbi-150.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0xf0f1 ++ extlb $17, 1, $16 ++ subl $16, 0xf0 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/extlh-80.S b/none/tests/sw64-insn/extlh-80.S +new file mode 100644 +index 000000000..fd17aabc0 +--- /dev/null ++++ b/none/tests/sw64-insn/extlh-80.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0xf0f1 ++ ldi $18, 1 ++ extlh $17, $18, $16 ++ subl $16, 0xf0 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/extlhi-151.S b/none/tests/sw64-insn/extlhi-151.S +new file mode 100644 +index 000000000..d55c60f3c +--- /dev/null ++++ b/none/tests/sw64-insn/extlhi-151.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0xf0f1 ++ extlh $17, 1, $16 ++ subl $16, 0xf0 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/extll-82.S b/none/tests/sw64-insn/extll-82.S +new file mode 100644 +index 000000000..9dc29c68e +--- /dev/null ++++ b/none/tests/sw64-insn/extll-82.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0xf0f1 ++ ldi $18, 1 ++ extll $17, $18, $16 ++ subl $16, 0xf0 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/extlli-153.S b/none/tests/sw64-insn/extlli-153.S +new file mode 100644 +index 000000000..99391ab1d +--- /dev/null ++++ b/none/tests/sw64-insn/extlli-153.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0xf0f1 ++ extll $17, 1, $16 ++ subl $16, 0xf0 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/extlw-81.S b/none/tests/sw64-insn/extlw-81.S +new file mode 100644 +index 000000000..16f45a72e +--- /dev/null ++++ b/none/tests/sw64-insn/extlw-81.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0xf0f1 ++ ldi $18, 1 ++ extlw $17, $18, $16 ++ subl $16, 0xf0 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/extlwi-152.S b/none/tests/sw64-insn/extlwi-152.S +new file mode 100644 +index 000000000..e5d038eba +--- /dev/null ++++ b/none/tests/sw64-insn/extlwi-152.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0xf0f1 ++ extlw $17, 1, $16 ++ subl $16, 0xf0 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/faddd-181.S b/none/tests/sw64-insn/faddd-181.S +new file mode 100644 +index 000000000..ffc0111f3 +--- /dev/null ++++ b/none/tests/sw64-insn/faddd-181.S +@@ -0,0 +1,15 @@ ++ .text ++ .global _start ++_start: ++ ldi $17, 42 ++ ifmovd $17, $f17 ++ fcvtld $f17, $f18 ++ faddd $f18, $f18, $f17 ++ fcvtdl $f17, $f16 ++ fimovd $f16, $16 ++ cmpeq $16, 84, $16 ++ subl $16, 1 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/fadds-180.S b/none/tests/sw64-insn/fadds-180.S +new file mode 100644 +index 000000000..f9a44f1fe +--- /dev/null ++++ b/none/tests/sw64-insn/fadds-180.S +@@ -0,0 +1,16 @@ ++ .text ++ .global _start ++_start: ++ ldi $17, 1078523331 /* 3.14 */ ++ ldi $18, 1076719780 /* 2.71 */ ++ ldi $19, 1086010164 /* 5.85 */ ++ ifmovs $17, $f17 ++ ifmovs $18, $f18 ++ fadds $f17, $f18, $f16 ++ fimovs $f16, $16 ++ cmpeq $16, $19, $16 ++ subl $16, 1 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/fbeq-360.S b/none/tests/sw64-insn/fbeq-360.S +new file mode 100644 +index 000000000..1e19ead6f +--- /dev/null ++++ b/none/tests/sw64-insn/fbeq-360.S +@@ -0,0 +1,14 @@ ++ .text ++ .global _start ++_start: ++ ldi $17, 42 ++ ifmovd $17, $f17 ++ fcvtld $f17, $f18 ++ fsubd $f18, $f18, $f17 ++ ldi $16, 0 ++ fbeq $f17, exit ++ ldi $16, 1 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/fbge-365.S b/none/tests/sw64-insn/fbge-365.S +new file mode 100644 +index 000000000..4ca2b59ed +--- /dev/null ++++ b/none/tests/sw64-insn/fbge-365.S +@@ -0,0 +1,49 @@ ++ .text ++ .global _start ++_start: ++ ++x1: ++ /* 3.1415926 = 0x400921fb4d12d84a */ ++ ldi $17, 0x400921fb ++ sll $17, 32 ++ ldi $17, 0x4d12d84a($17) ++ ifmovd $17, $f17 ++ ++x2: ++ /* 2.71828 = 0x4005bf0995aaf790 */ ++ ldi $18, 0x4005bf09 ++ sll $18, 16 ++ ldi $18, 0x95aa($18) ++ sll $18, 16 ++ ldi $18, 0xf790($18) ++ ifmovd $18, $f18 ++ ++x3: ++ /* 1.4142136 = 0x3ff6 a09e 7098 ef50 */ ++ ldi $19, 0x3ff6a09e ++ sll $19, 16 ++ ldi $19, 0x7098($19) ++ sll $19, 16 ++ ldi $19, 0xef50($19) ++ ifmovd $19, $f19 ++ ++result: ++ /* 9.9539419327280001 = 0x4023 e86b 13b6 b318 */ ++ ldi $20, 0x4023 ++ sll $20, 16 ++ ldi $20, 0xe86b($20) ++ sll $20, 16 ++ ldi $20, 0x13b6($20) ++ sll $20, 16 ++ ldi $20, 0xb318($20) ++ ifmovd $20, $f20 ++ ++run: ++ fsubd $f17, $f18, $f21 ++ ldi $16, 0 ++ fbge $f21, exit ++ ldi $16, 1 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/fbgt-364.S b/none/tests/sw64-insn/fbgt-364.S +new file mode 100644 +index 000000000..3fd4d4a79 +--- /dev/null ++++ b/none/tests/sw64-insn/fbgt-364.S +@@ -0,0 +1,49 @@ ++ .text ++ .global _start ++_start: ++ ++x1: ++ /* 3.1415926 = 0x400921fb4d12d84a */ ++ ldi $17, 0x400921fb ++ sll $17, 32 ++ ldi $17, 0x4d12d84a($17) ++ ifmovd $17, $f17 ++ ++x2: ++ /* 2.71828 = 0x4005bf0995aaf790 */ ++ ldi $18, 0x4005bf09 ++ sll $18, 16 ++ ldi $18, 0x95aa($18) ++ sll $18, 16 ++ ldi $18, 0xf790($18) ++ ifmovd $18, $f18 ++ ++x3: ++ /* 1.4142136 = 0x3ff6 a09e 7098 ef50 */ ++ ldi $19, 0x3ff6a09e ++ sll $19, 16 ++ ldi $19, 0x7098($19) ++ sll $19, 16 ++ ldi $19, 0xef50($19) ++ ifmovd $19, $f19 ++ ++result: ++ /* 9.9539419327280001 = 0x4023 e86b 13b6 b318 */ ++ ldi $20, 0x4023 ++ sll $20, 16 ++ ldi $20, 0xe86b($20) ++ sll $20, 16 ++ ldi $20, 0x13b6($20) ++ sll $20, 16 ++ ldi $20, 0xb318($20) ++ ifmovd $20, $f20 ++ ++run: ++ fsubd $f17, $f18, $f21 ++ ldi $16, 0 ++ fbgt $f21, exit ++ ldi $16, 1 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/fble-363.S b/none/tests/sw64-insn/fble-363.S +new file mode 100644 +index 000000000..86ca7d14d +--- /dev/null ++++ b/none/tests/sw64-insn/fble-363.S +@@ -0,0 +1,49 @@ ++ .text ++ .global _start ++_start: ++ ++x1: ++ /* 3.1415926 = 0x400921fb4d12d84a */ ++ ldi $17, 0x400921fb ++ sll $17, 32 ++ ldi $17, 0x4d12d84a($17) ++ ifmovd $17, $f17 ++ ++x2: ++ /* 2.71828 = 0x4005bf0995aaf790 */ ++ ldi $18, 0x4005bf09 ++ sll $18, 16 ++ ldi $18, 0x95aa($18) ++ sll $18, 16 ++ ldi $18, 0xf790($18) ++ ifmovd $18, $f18 ++ ++x3: ++ /* 1.4142136 = 0x3ff6 a09e 7098 ef50 */ ++ ldi $19, 0x3ff6a09e ++ sll $19, 16 ++ ldi $19, 0x7098($19) ++ sll $19, 16 ++ ldi $19, 0xef50($19) ++ ifmovd $19, $f19 ++ ++result: ++ /* 9.9539419327280001 = 0x4023 e86b 13b6 b318 */ ++ ldi $20, 0x4023 ++ sll $20, 16 ++ ldi $20, 0xe86b($20) ++ sll $20, 16 ++ ldi $20, 0x13b6($20) ++ sll $20, 16 ++ ldi $20, 0xb318($20) ++ ifmovd $20, $f20 ++ ++run: ++ fsubd $f18, $f17, $f21 ++ ldi $16, 0 ++ fble $f21, exit ++ ldi $16, 1 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/fblt-362.S b/none/tests/sw64-insn/fblt-362.S +new file mode 100644 +index 000000000..354fd9547 +--- /dev/null ++++ b/none/tests/sw64-insn/fblt-362.S +@@ -0,0 +1,49 @@ ++ .text ++ .global _start ++_start: ++ ++x1: ++ /* 3.1415926 = 0x400921fb4d12d84a */ ++ ldi $17, 0x400921fb ++ sll $17, 32 ++ ldi $17, 0x4d12d84a($17) ++ ifmovd $17, $f17 ++ ++x2: ++ /* 2.71828 = 0x4005bf0995aaf790 */ ++ ldi $18, 0x4005bf09 ++ sll $18, 16 ++ ldi $18, 0x95aa($18) ++ sll $18, 16 ++ ldi $18, 0xf790($18) ++ ifmovd $18, $f18 ++ ++x3: ++ /* 1.4142136 = 0x3ff6 a09e 7098 ef50 */ ++ ldi $19, 0x3ff6a09e ++ sll $19, 16 ++ ldi $19, 0x7098($19) ++ sll $19, 16 ++ ldi $19, 0xef50($19) ++ ifmovd $19, $f19 ++ ++result: ++ /* 9.9539419327280001 = 0x4023 e86b 13b6 b318 */ ++ ldi $20, 0x4023 ++ sll $20, 16 ++ ldi $20, 0xe86b($20) ++ sll $20, 16 ++ ldi $20, 0x13b6($20) ++ sll $20, 16 ++ ldi $20, 0xb318($20) ++ ifmovd $20, $f20 ++ ++run: ++ fsubd $f18, $f17, $f21 ++ ldi $16, 0 ++ fblt $f21, exit ++ ldi $16, 1 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/fbne-361.S b/none/tests/sw64-insn/fbne-361.S +new file mode 100644 +index 000000000..66adedc40 +--- /dev/null ++++ b/none/tests/sw64-insn/fbne-361.S +@@ -0,0 +1,49 @@ ++ .text ++ .global _start ++_start: ++ ++x1: ++ /* 3.1415926 = 0x400921fb4d12d84a */ ++ ldi $17, 0x400921fb ++ sll $17, 32 ++ ldi $17, 0x4d12d84a($17) ++ ifmovd $17, $f17 ++ ++x2: ++ /* 2.71828 = 0x4005bf0995aaf790 */ ++ ldi $18, 0x4005bf09 ++ sll $18, 16 ++ ldi $18, 0x95aa($18) ++ sll $18, 16 ++ ldi $18, 0xf790($18) ++ ifmovd $18, $f18 ++ ++x3: ++ /* 1.4142136 = 0x3ff6 a09e 7098 ef50 */ ++ ldi $19, 0x3ff6a09e ++ sll $19, 16 ++ ldi $19, 0x7098($19) ++ sll $19, 16 ++ ldi $19, 0xef50($19) ++ ifmovd $19, $f19 ++ ++result: ++ /* 9.9539419327280001 = 0x4023 e86b 13b6 b318 */ ++ ldi $20, 0x4023 ++ sll $20, 16 ++ ldi $20, 0xe86b($20) ++ sll $20, 16 ++ ldi $20, 0x13b6($20) ++ sll $20, 16 ++ ldi $20, 0xb318($20) ++ ifmovd $20, $f20 ++ ++run: ++ fsubd $f17, $f18, $f21 ++ ldi $16, 0 ++ fbne $f21, exit ++ ldi $16, 1 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/fcmpeq-190.S b/none/tests/sw64-insn/fcmpeq-190.S +new file mode 100644 +index 000000000..67f846286 +--- /dev/null ++++ b/none/tests/sw64-insn/fcmpeq-190.S +@@ -0,0 +1,36 @@ ++ .text ++ .global _start ++_start: ++ ++x1: ++ /* 3.1415926 = 0x400921fb4d12d84a */ ++ ldi $17, 0x400921fb ++ sll $17, 32 ++ ldi $17, 0x4d12d84a($17) ++ ifmovd $17, $f17 ++ ++x2: ++ /* 2.71828 = 0x4005bf0995aaf790 */ ++ ldi $18, 0x4005bf09 ++ sll $18, 16 ++ ldi $18, 0x95aa($18) ++ sll $18, 16 ++ ldi $18, 0xf790($18) ++ ifmovd $18, $f18 ++ ++result: ++ /* 1.7724538357881143 = 0x3ffc 5bf8 8da6 1346 */ ++ ldi $19, 0x3ffc5bf8 ++ sll $19, 16 ++ ldi $19, 0x8da6($19) ++ sll $19, 16 ++ ldi $19, 0x1346($19) ++ ifmovd $19, $f19 ++ ++run: ++ fcmpeq $f17, $f18, $f16 ++ fimovd $f16, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/fcmple-191.S b/none/tests/sw64-insn/fcmple-191.S +new file mode 100644 +index 000000000..a8915cc2f +--- /dev/null ++++ b/none/tests/sw64-insn/fcmple-191.S +@@ -0,0 +1,36 @@ ++ .text ++ .global _start ++_start: ++ ++x1: ++ /* 3.1415926 = 0x400921fb4d12d84a */ ++ ldi $17, 0x400921fb ++ sll $17, 32 ++ ldi $17, 0x4d12d84a($17) ++ ifmovd $17, $f17 ++ ++x2: ++ /* 2.71828 = 0x4005bf0995aaf790 */ ++ ldi $18, 0x4005bf09 ++ sll $18, 16 ++ ldi $18, 0x95aa($18) ++ sll $18, 16 ++ ldi $18, 0xf790($18) ++ ifmovd $18, $f18 ++ ++result: ++ /* 1.7724538357881143 = 0x3ffc 5bf8 8da6 1346 */ ++ ldi $19, 0x3ffc5bf8 ++ sll $19, 16 ++ ldi $19, 0x8da6($19) ++ sll $19, 16 ++ ldi $19, 0x1346($19) ++ ifmovd $19, $f19 ++ ++run: ++ fcmple $f17, $f18, $f16 ++ fimovd $f16, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/fcmplt-192.S b/none/tests/sw64-insn/fcmplt-192.S +new file mode 100644 +index 000000000..325c33896 +--- /dev/null ++++ b/none/tests/sw64-insn/fcmplt-192.S +@@ -0,0 +1,36 @@ ++ .text ++ .global _start ++_start: ++ ++x1: ++ /* 3.1415926 = 0x400921fb4d12d84a */ ++ ldi $17, 0x400921fb ++ sll $17, 32 ++ ldi $17, 0x4d12d84a($17) ++ ifmovd $17, $f17 ++ ++x2: ++ /* 2.71828 = 0x4005bf0995aaf790 */ ++ ldi $18, 0x4005bf09 ++ sll $18, 16 ++ ldi $18, 0x95aa($18) ++ sll $18, 16 ++ ldi $18, 0xf790($18) ++ ifmovd $18, $f18 ++ ++result: ++ /* 1.7724538357881143 = 0x3ffc 5bf8 8da6 1346 */ ++ ldi $19, 0x3ffc5bf8 ++ sll $19, 16 ++ ldi $19, 0x8da6($19) ++ sll $19, 16 ++ ldi $19, 0x1346($19) ++ ifmovd $19, $f19 ++ ++run: ++ fcmplt $f18, $f17, $f16 ++ fimovd $f16, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/fcmpun-193.S b/none/tests/sw64-insn/fcmpun-193.S +new file mode 100644 +index 000000000..9b162d2dd +--- /dev/null ++++ b/none/tests/sw64-insn/fcmpun-193.S +@@ -0,0 +1,36 @@ ++ .text ++ .global _start ++_start: ++ ++x1: ++ /* 3.1415926 = 0x400921fb4d12d84a */ ++ ldi $17, 0x400921fb ++ sll $17, 32 ++ ldi $17, 0x4d12d84a($17) ++ ifmovd $17, $f17 ++ ++x2: ++ /* 2.71828 = 0x4005bf0995aaf790 */ ++ ldi $18, 0x4005bf09 ++ sll $18, 16 ++ ldi $18, 0x95aa($18) ++ sll $18, 16 ++ ldi $18, 0xf790($18) ++ ifmovd $18, $f18 ++ ++result: ++ /* 1.7724538357881143 = 0x3ffc 5bf8 8da6 1346 */ ++ ldi $19, 0x3ffc5bf8 ++ sll $19, 16 ++ ldi $19, 0x8da6($19) ++ sll $19, 16 ++ ldi $19, 0x1346($19) ++ ifmovd $19, $f19 ++ ++run: ++ fcmpun $f17, $f18, $f16 ++ fimovd $f16, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/fcpys-205.S b/none/tests/sw64-insn/fcpys-205.S +new file mode 100644 +index 000000000..239bd20a2 +--- /dev/null ++++ b/none/tests/sw64-insn/fcpys-205.S +@@ -0,0 +1,39 @@ ++ .text ++ .global _start ++_start: ++ ++x1: ++ /* 3.1415926 = 0x400921fb4d12d84a */ ++ ldi $17, 0x400921fb ++ sll $17, 32 ++ ldi $17, 0x4d12d84a($17) ++ ifmovd $17, $f17 ++ ++x2: ++ /* 2.71828 = 0x4005bf0995aaf790 */ ++ ldi $18, 0x4005bf09 ++ sll $18, 16 ++ ldi $18, 0x95aa($18) ++ sll $18, 16 ++ ldi $18, 0xf790($18) ++ ifmovd $18, $f18 ++ ++result: ++ /* 1.772453784942627 = 0x3ffc 5bf8 8000 0000 */ ++ ldi $19, 0x3ffc5bf8 ++ sll $19, 16 ++ ldi $19, 0x8000($19) ++ sll $19, 16 ++ ldi $19, 0x0000($19) ++ ifmovd $19, $f19 ++ ++run: ++ fcpys $f17, $f18, $f20 ++ fsubd $f18, $f20, $f1 ++ ldi $16, 0 ++ fbeq $f1, exit ++ ldi $16, 1 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/fcpyse-206.S b/none/tests/sw64-insn/fcpyse-206.S +new file mode 100644 +index 000000000..c5a924ef9 +--- /dev/null ++++ b/none/tests/sw64-insn/fcpyse-206.S +@@ -0,0 +1,39 @@ ++ .text ++ .global _start ++_start: ++ ++x1: ++ /* 3.1415926 = 0x400921fb4d12d84a */ ++ ldi $17, 0x400921fb ++ sll $17, 32 ++ ldi $17, 0x4d12d84a($17) ++ ifmovd $17, $f17 ++ ++x2: ++ /* 2.71828 = 0x4005bf0995aaf790 */ ++ ldi $18, 0x4005bf09 ++ sll $18, 16 ++ ldi $18, 0x95aa($18) ++ sll $18, 16 ++ ldi $18, 0xf790($18) ++ ifmovd $18, $f18 ++ ++result: ++ /* 1.772453784942627 = 0x3ffc 5bf8 8000 0000 */ ++ ldi $19, 0x3ffc5bf8 ++ sll $19, 16 ++ ldi $19, 0x8000($19) ++ sll $19, 16 ++ ldi $19, 0x0000($19) ++ ifmovd $19, $f19 ++ ++run: ++ fcpyse $f17, $f18, $f20 ++ fsubd $f18, $f20, $f1 ++ ldi $16, 0 ++ fbeq $f1, exit ++ ldi $16, 1 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/fcpysn-207.S b/none/tests/sw64-insn/fcpysn-207.S +new file mode 100644 +index 000000000..83bd676c2 +--- /dev/null ++++ b/none/tests/sw64-insn/fcpysn-207.S +@@ -0,0 +1,39 @@ ++ .text ++ .global _start ++_start: ++ ++x1: ++ /* 3.1415926 = 0x400921fb4d12d84a */ ++ ldi $17, 0x400921fb ++ sll $17, 32 ++ ldi $17, 0x4d12d84a($17) ++ ifmovd $17, $f17 ++ ++x2: ++ /* 2.71828 = 0x4005bf0995aaf790 */ ++ ldi $18, 0x4005bf09 ++ sll $18, 16 ++ ldi $18, 0x95aa($18) ++ sll $18, 16 ++ ldi $18, 0xf790($18) ++ ifmovd $18, $f18 ++ ++result: ++ /* 1.772453784942627 = 0x3ffc 5bf8 8000 0000 */ ++ ldi $19, 0x3ffc5bf8 ++ sll $19, 16 ++ ldi $19, 0x8000($19) ++ sll $19, 16 ++ ldi $19, 0x0000($19) ++ ifmovd $19, $f19 ++ ++run: ++ fcpysn $f17, $f18, $f20 ++ faddd $f18, $f20, $f1 ++ ldi $16, 0 ++ fbeq $f1, exit ++ ldi $16, 1 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/fcvtdl-200.S b/none/tests/sw64-insn/fcvtdl-200.S +new file mode 100644 +index 000000000..a073e1b56 +--- /dev/null ++++ b/none/tests/sw64-insn/fcvtdl-200.S +@@ -0,0 +1,18 @@ ++ .text ++ .global _start ++_start: ++ ldi $17, 42 ++ ifmovd $17, $f16 ++ fcvtld $f16, $f17 ++ ldi $18, 2 ++ ifmovd $18, $f16 ++ fcvtld $f16, $f18 ++ fmuld $f17, $f18, $f19 ++ fcvtdl $f19, $f16 ++ fimovd $f16, $16 ++ cmpeq $16, 84, $16 ++ subl $16, 1 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/fcvtdl_g-196.S b/none/tests/sw64-insn/fcvtdl_g-196.S +new file mode 100644 +index 000000000..0f4ff787f +--- /dev/null ++++ b/none/tests/sw64-insn/fcvtdl_g-196.S +@@ -0,0 +1,37 @@ ++ .text ++ .global _start ++_start: ++ ++x1: ++ /* 3.1415926 = 0x400921fb4d12d84a */ ++ ldi $17, 0x400921fb ++ sll $17, 32 ++ ldi $17, 0x4d12d84a($17) ++ ifmovd $17, $f17 ++ ++x2: ++ /* 2.71828 = 0x4005bf0995aaf790 */ ++ ldi $18, 0x4005bf09 ++ sll $18, 16 ++ ldi $18, 0x95aa($18) ++ sll $18, 16 ++ ldi $18, 0xf790($18) ++ ifmovd $18, $f18 ++ ++result: ++ /* 1.7724538357881143 = 0x3ffc 5bf8 8da6 1346 */ ++ ldi $19, 0x3ffc5bf8 ++ sll $19, 16 ++ ldi $19, 0x8da6($19) ++ sll $19, 16 ++ ldi $19, 0x1346($19) ++ ifmovd $19, $f19 ++ ++run: ++ fcvtdl_g $f17, $f16 ++ fimovd $f16, $16 ++ subl $16, 3 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/fcvtdl_n-199.S b/none/tests/sw64-insn/fcvtdl_n-199.S +new file mode 100644 +index 000000000..fe99e49ad +--- /dev/null ++++ b/none/tests/sw64-insn/fcvtdl_n-199.S +@@ -0,0 +1,37 @@ ++ .text ++ .global _start ++_start: ++ ++x1: ++ /* 3.1415926 = 0x400921fb4d12d84a */ ++ ldi $17, 0x400921fb ++ sll $17, 32 ++ ldi $17, 0x4d12d84a($17) ++ ifmovd $17, $f17 ++ ++x2: ++ /* 2.71828 = 0x4005bf0995aaf790 */ ++ ldi $18, 0x4005bf09 ++ sll $18, 16 ++ ldi $18, 0x95aa($18) ++ sll $18, 16 ++ ldi $18, 0xf790($18) ++ ifmovd $18, $f18 ++ ++result: ++ /* 1.7724538357881143 = 0x3ffc 5bf8 8da6 1346 */ ++ ldi $19, 0x3ffc5bf8 ++ sll $19, 16 ++ ldi $19, 0x8da6($19) ++ sll $19, 16 ++ ldi $19, 0x1346($19) ++ ifmovd $19, $f19 ++ ++run: ++ fcvtdl_n $f17, $f16 ++ fimovd $f16, $16 ++ subl $16, 3 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/fcvtdl_p-197.S b/none/tests/sw64-insn/fcvtdl_p-197.S +new file mode 100644 +index 000000000..d872c82e4 +--- /dev/null ++++ b/none/tests/sw64-insn/fcvtdl_p-197.S +@@ -0,0 +1,37 @@ ++ .text ++ .global _start ++_start: ++ ++x1: ++ /* 3.1415926 = 0x400921fb4d12d84a */ ++ ldi $17, 0x400921fb ++ sll $17, 32 ++ ldi $17, 0x4d12d84a($17) ++ ifmovd $17, $f17 ++ ++x2: ++ /* 2.71828 = 0x4005bf0995aaf790 */ ++ ldi $18, 0x4005bf09 ++ sll $18, 16 ++ ldi $18, 0x95aa($18) ++ sll $18, 16 ++ ldi $18, 0xf790($18) ++ ifmovd $18, $f18 ++ ++result: ++ /* 1.7724538357881143 = 0x3ffc 5bf8 8da6 1346 */ ++ ldi $19, 0x3ffc5bf8 ++ sll $19, 16 ++ ldi $19, 0x8da6($19) ++ sll $19, 16 ++ ldi $19, 0x1346($19) ++ ifmovd $19, $f19 ++ ++run: ++ fcvtdl_p $f17, $f16 ++ fimovd $f16, $16 ++ subl $16, 4 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/fcvtdl_z-198.S b/none/tests/sw64-insn/fcvtdl_z-198.S +new file mode 100644 +index 000000000..7925c4081 +--- /dev/null ++++ b/none/tests/sw64-insn/fcvtdl_z-198.S +@@ -0,0 +1,37 @@ ++ .text ++ .global _start ++_start: ++ ++x1: ++ /* 3.1415926 = 0x400921fb4d12d84a */ ++ ldi $17, 0x400921fb ++ sll $17, 32 ++ ldi $17, 0x4d12d84a($17) ++ ifmovd $17, $f17 ++ ++x2: ++ /* 2.71828 = 0x4005bf0995aaf790 */ ++ ldi $18, 0x4005bf09 ++ sll $18, 16 ++ ldi $18, 0x95aa($18) ++ sll $18, 16 ++ ldi $18, 0xf790($18) ++ ifmovd $18, $f18 ++ ++result: ++ /* 1.7724538357881143 = 0x3ffc 5bf8 8da6 1346 */ ++ ldi $19, 0x3ffc5bf8 ++ sll $19, 16 ++ ldi $19, 0x8da6($19) ++ sll $19, 16 ++ ldi $19, 0x1346($19) ++ ifmovd $19, $f19 ++ ++run: ++ fcvtdl_z $f17, $f16 ++ fimovd $f16, $16 ++ subl $16, 3 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/fcvtds-195.S b/none/tests/sw64-insn/fcvtds-195.S +new file mode 100644 +index 000000000..b51203274 +--- /dev/null ++++ b/none/tests/sw64-insn/fcvtds-195.S +@@ -0,0 +1,19 @@ ++ .text ++ .global _start ++_start: ++ ++.run: ++ ldi $17, 42 ++ ifmovd $17, $f17 ++ fcvtld $f17, $f18 ++ fcvtds $f18, $f19 ++ ++ fcvtls $f17, $f20 ++ ldi $16, 0 ++ fsubd $f19, $f20, $f1 ++ fbeq $f1, .exit ++ ldi $16, 1 ++ ++.exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/fcvtld-204.S b/none/tests/sw64-insn/fcvtld-204.S +new file mode 100644 +index 000000000..a073e1b56 +--- /dev/null ++++ b/none/tests/sw64-insn/fcvtld-204.S +@@ -0,0 +1,18 @@ ++ .text ++ .global _start ++_start: ++ ldi $17, 42 ++ ifmovd $17, $f16 ++ fcvtld $f16, $f17 ++ ldi $18, 2 ++ ifmovd $18, $f16 ++ fcvtld $f16, $f18 ++ fmuld $f17, $f18, $f19 ++ fcvtdl $f19, $f16 ++ fimovd $f16, $16 ++ cmpeq $16, 84, $16 ++ subl $16, 1 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/fcvtls-203.S b/none/tests/sw64-insn/fcvtls-203.S +new file mode 100644 +index 000000000..79e0b87c1 +--- /dev/null ++++ b/none/tests/sw64-insn/fcvtls-203.S +@@ -0,0 +1,36 @@ ++ .text ++ .global _start ++_start: ++ ++x1: ++ /* 3.1415926 = 0x400921fb4d12d84a */ ++ ldi $17, 0x400921fb ++ sll $17, 32 ++ ldi $17, 0x4d12d84a($17) ++ ifmovd $17, $f17 ++ ++x2: ++ /* 2.71828 = 0x4005bf0995aaf790 */ ++ ldi $18, 0x4005bf09 ++ sll $18, 16 ++ ldi $18, 0x95aa($18) ++ sll $18, 16 ++ ldi $18, 0xf790($18) ++ ifmovd $18, $f18 ++ ++result: ++ /* 0x43d0 0248 8000 0000 */ ++ ldi $19, 0x43d00248 ++ sll $19, 16 ++ ldi $19, 0x8000($19) ++ sll $19, 16 ++ ldi $19, 0x0000($19) ++ ++run: ++ fcvtls $f17, $f16 ++ fimovd $f16, $16 ++ subl $16, $19 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/fcvtlw-202.S b/none/tests/sw64-insn/fcvtlw-202.S +new file mode 100644 +index 000000000..e63335d0f +--- /dev/null ++++ b/none/tests/sw64-insn/fcvtlw-202.S +@@ -0,0 +1,36 @@ ++ .text ++ .global _start ++_start: ++ ++x1: ++ /* 3.1415926 = 0x400921fb4d12d84a */ ++ ldi $17, 0x400921fb ++ sll $17, 32 ++ ldi $17, 0x4d12d84a($17) ++ ifmovd $17, $f17 ++ ++x2: ++ /* 2.71828 = 0x4005bf0995aaf790 */ ++ ldi $18, 0x4005bf09 ++ sll $18, 16 ++ ldi $18, 0x95aa($18) ++ sll $18, 16 ++ ldi $18, 0xf790($18) ++ ifmovd $18, $f18 ++ ++result: ++ /* 0x41a2 5b09 4000 0000 */ ++ ldi $19, 0x41a25b09 ++ sll $19, 16 ++ ldi $19, 0x4000($19) ++ sll $19, 16 ++ ldi $19, 0x0000($19) ++ ++run: ++ fcvtlw $f17, $f16 ++ fimovd $f16, $16 ++ subl $16, $19 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/fcvtsd-194.S b/none/tests/sw64-insn/fcvtsd-194.S +new file mode 100644 +index 000000000..079858291 +--- /dev/null ++++ b/none/tests/sw64-insn/fcvtsd-194.S +@@ -0,0 +1,38 @@ ++ .text ++ .global _start ++_start: ++ ++x1: ++ /* 3.1415926 = 0x400921fb4d12d84a */ ++ ldi $17, 0x400921fb ++ sll $17, 32 ++ ldi $17, 0x4d12d84a($17) ++ ifmovd $17, $f17 ++ ++x2: ++ /* 2.71828 = 0x4005bf0995aaf790 */ ++ ldi $18, 0x4005bf09 ++ sll $18, 16 ++ ldi $18, 0x95aa($18) ++ sll $18, 16 ++ ldi $18, 0xf790($18) ++ ifmovd $18, $f18 ++ ++result: ++ /* 1.7724538357881143 = 0x3ffc 5bf8 8da6 1346 */ ++ ldi $19, 0x3ffc5bf8 ++ sll $19, 16 ++ ldi $19, 0x8da6($19) ++ sll $19, 16 ++ ldi $19, 0x1346($19) ++ ifmovd $19, $f19 ++ ++run: ++ fcvtds $f17, $f1 ++ fcvtsd $f1, $f2 ++ fcmpeq $f2, $f17, $f16 ++ fimovd $f16, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/fcvtwl-201.S b/none/tests/sw64-insn/fcvtwl-201.S +new file mode 100644 +index 000000000..d45d073b1 +--- /dev/null ++++ b/none/tests/sw64-insn/fcvtwl-201.S +@@ -0,0 +1,31 @@ ++ .text ++ .global _start ++_start: ++ ++x1: ++ /* 3.1415926 = 0x400921fb4d12d84a */ ++ ldi $17, 0x400921fb ++ sll $17, 32 ++ ldi $17, 0x4d12d84a($17) ++ ifmovd $17, $f17 ++ ++x2: ++ /* 2.71828 = 0x4005bf0995aaf790 */ ++ ldi $18, 0x4005bf09 ++ sll $18, 16 ++ ldi $18, 0x95aa($18) ++ sll $18, 16 ++ ldi $18, 0xf790($18) ++ ifmovd $18, $f18 ++ ++result: ++ ldi $19, 0x40490fda ++ ++run: ++ fcvtwl $f17, $f16 ++ fimovd $f16, $16 ++ subl $16, $19 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/fdivd-187.S b/none/tests/sw64-insn/fdivd-187.S +new file mode 100644 +index 000000000..3e6e01ee0 +--- /dev/null ++++ b/none/tests/sw64-insn/fdivd-187.S +@@ -0,0 +1,18 @@ ++ .text ++ .global _start ++_start: ++ ldi $17, 42 ++ ifmovd $17, $f16 ++ fcvtld $f16, $f17 ++ ldi $18, 2 ++ ifmovd $18, $f16 ++ fcvtld $f16, $f18 ++ fdivd $f17, $f18, $f19 ++ fcvtdl $f19, $f16 ++ fimovd $f16, $16 ++ cmpeq $16, 21, $16 ++ subl $16, 1 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/fdivs-186.S b/none/tests/sw64-insn/fdivs-186.S +new file mode 100644 +index 000000000..4bd38e9ba +--- /dev/null ++++ b/none/tests/sw64-insn/fdivs-186.S +@@ -0,0 +1,42 @@ ++ .text ++ .global _start ++_start: ++ ++x1: ++ /* 3.1415926 = 0x400921fb4d12d84a */ ++ ldi $17, 0x400921fb ++ sll $17, 32 ++ ldi $17, 0x4d12d84a($17) ++ ifmovd $17, $f17 ++ ++x2: ++ /* 2.71828 = 0x4005bf0995aaf790 */ ++ ldi $18, 0x4005bf09 ++ sll $18, 16 ++ ldi $18, 0x95aa($18) ++ sll $18, 16 ++ ldi $18, 0xf790($18) ++ ifmovd $18, $f18 ++ ++result: ++ /* 1.1557279825210571 = 0x3ff27ddca0000000 */ ++ ldi $19, 0x3ff27ddc ++ sll $19, 16 ++ ldi $19, 0xa000($19) ++ sll $19, 16 ++ ldi $19, 0x0000($19) ++ ifmovd $19, $f19 ++ ++run: ++ fcvtds $f17, $f1 ++ fcvtds $f18, $f2 ++ fcvtds $f19, $f3 ++ fdivs $f1, $f2, $f4 ++ ldi $16, 0 ++ fsubs $f4, $f3, $f1 ++ fbeq $f1, exit ++ ldi $16, 1 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/fimovd-104.S b/none/tests/sw64-insn/fimovd-104.S +new file mode 100644 +index 000000000..bf5a9292c +--- /dev/null ++++ b/none/tests/sw64-insn/fimovd-104.S +@@ -0,0 +1,12 @@ ++ .text ++ .global _start ++_start: ++ ldi $17, 1078523331 ++ ifmovd $17, $f16 ++ fimovd $f16, $18 ++ cmpeq $17, $18, $16 ++ subl $16, 1 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/fimovs-103.S b/none/tests/sw64-insn/fimovs-103.S +new file mode 100644 +index 000000000..050f2b58e +--- /dev/null ++++ b/none/tests/sw64-insn/fimovs-103.S +@@ -0,0 +1,13 @@ ++ ++ .global _start ++_start: ++ ldi $17, 1078523331 ++ ifmovs $17, $f16 ++ fimovs $f16, $18 ++ cmpeq $17, $18, $16 ++ subl $16, 1 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/fldd-343.S b/none/tests/sw64-insn/fldd-343.S +new file mode 100644 +index 000000000..763a14d6f +--- /dev/null ++++ b/none/tests/sw64-insn/fldd-343.S +@@ -0,0 +1,51 @@ ++ .text ++ .global _start ++_start: ++ ++x1: ++ /* 3.1415926 = 0x400921fb4d12d84a */ ++ ldi $17, 0x400921fb ++ sll $17, 32 ++ ldi $17, 0x4d12d84a($17) ++ ifmovd $17, $f17 ++ ++x2: ++ /* 2.71828 = 0x4005bf0995aaf790 */ ++ ldi $18, 0x4005bf09 ++ sll $18, 16 ++ ldi $18, 0x95aa($18) ++ sll $18, 16 ++ ldi $18, 0xf790($18) ++ ifmovd $18, $f18 ++ ++x3: ++ /* 1.4142136 = 0x3ff6 a09e 7098 ef50 */ ++ ldi $19, 0x3ff6a09e ++ sll $19, 16 ++ ldi $19, 0x7098($19) ++ sll $19, 16 ++ ldi $19, 0xef50($19) ++ ifmovd $19, $f19 ++ ++result: ++ /* 9.9539419327280001 = 0x4023 e86b 13b6 b318 */ ++ ldi $20, 0x4023 ++ sll $20, 16 ++ ldi $20, 0xe86b($20) ++ sll $20, 16 ++ ldi $20, 0x13b6($20) ++ sll $20, 16 ++ ldi $20, 0xb318($20) ++ ifmovd $20, $f20 ++ ++run: ++ ldi $sp, -8($sp) ++ fstd $f17, 0($sp) ++ fldd $f21, 0($sp) ++ fsubd $f17, $f21, $f16 ++ fimovd $f16, $16 ++ ldi $sp, 8($sp) ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/flds-342.S b/none/tests/sw64-insn/flds-342.S +new file mode 100644 +index 000000000..1c3ff831e +--- /dev/null ++++ b/none/tests/sw64-insn/flds-342.S +@@ -0,0 +1,17 @@ ++ .text ++ .global _start ++_start: ++ ldi $sp, -8($sp) ++ ldi $17, 42 ++ ifmovd $17, $f17 ++ fcvtds $f17, $f21 ++ fsts $f21, 0($sp) ++ flds $f22, 0($sp) ++ fsubd $f22, $f21, $f16 ++ ldi $16, 0 ++ fbeq $f16, .exit ++ ldi $16, 1 ++ ++.exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/fmad-217.S b/none/tests/sw64-insn/fmad-217.S +new file mode 100644 +index 000000000..912789198 +--- /dev/null ++++ b/none/tests/sw64-insn/fmad-217.S +@@ -0,0 +1,48 @@ ++ .text ++ .global _start ++_start: ++ ++x1: ++ /* 3.1415926 = 0x400921fb4d12d84a */ ++ ldi $17, 0x400921fb ++ sll $17, 32 ++ ldi $17, 0x4d12d84a($17) ++ ifmovd $17, $f17 ++ ++x2: ++ /* 2.71828 = 0x4005bf0995aaf790 */ ++ ldi $18, 0x4005bf09 ++ sll $18, 16 ++ ldi $18, 0x95aa($18) ++ sll $18, 16 ++ ldi $18, 0xf790($18) ++ ifmovd $18, $f18 ++ ++x3: ++ /* 1.4142136 = 0x3ff6 a09e 7098 ef50 */ ++ ldi $19, 0x3ff6a09e ++ sll $19, 16 ++ ldi $19, 0x7098($19) ++ sll $19, 16 ++ ldi $19, 0xef50($19) ++ ifmovd $19, $f19 ++ ++result: ++ /* 9.9539419327280001 = 0x4023 e86b 13b6 b318 */ ++ ldi $20, 0x4023 ++ sll $20, 16 ++ ldi $20, 0xe86b($20) ++ sll $20, 16 ++ ldi $20, 0x13b6($20) ++ sll $20, 16 ++ ldi $20, 0xb318($20) ++ ifmovd $20, $f20 ++ ++run: ++ fmad $f17, $f18, $f19, $f21 ++ fsubd $f20, $f21, $f16 ++ fimovd $f16, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/fmas-216.S b/none/tests/sw64-insn/fmas-216.S +new file mode 100644 +index 000000000..d95aeeea2 +--- /dev/null ++++ b/none/tests/sw64-insn/fmas-216.S +@@ -0,0 +1,52 @@ ++ .text ++ .global _start ++_start: ++ ++x1: ++ /* 3.1415926 = 0x400921fb4d12d84a */ ++ ldi $17, 0x400921fb ++ sll $17, 32 ++ ldi $17, 0x4d12d84a($17) ++ ifmovd $17, $f17 ++ ++x2: ++ /* 2.71828 = 0x4005bf0995aaf790 */ ++ ldi $18, 0x4005bf09 ++ sll $18, 16 ++ ldi $18, 0x95aa($18) ++ sll $18, 16 ++ ldi $18, 0xf790($18) ++ ifmovd $18, $f18 ++ ++x3: ++ /* 1.4142136 = 0x3ff6 a09e 7098 ef50 */ ++ ldi $19, 0x3ff6a09e ++ sll $19, 16 ++ ldi $19, 0x7098($19) ++ sll $19, 16 ++ ldi $19, 0xef50($19) ++ ifmovd $19, $f19 ++ ++result: ++ /* 9.9539422988891602 = 0x4023 e86b 2000 0000 */ ++ ldi $20, 0x4023 ++ sll $20, 16 ++ ldi $20, 0xe86b($20) ++ sll $20, 16 ++ ldi $20, 0x2000($20) ++ sll $20, 16 ++ ldi $20, 0x0000($20) ++ ifmovd $20, $f20 ++ ++run: ++ fcvtds $f17, $f1 ++ fcvtds $f18, $f2 ++ fcvtds $f19, $f3 ++ fcvtds $f20, $f21 ++ fmas $f1, $f2, $f3, $f4 ++ fsubs $f4, $f21, $f16 ++ fimovs $f16, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/fmsd-219.S b/none/tests/sw64-insn/fmsd-219.S +new file mode 100644 +index 000000000..b9e919c33 +--- /dev/null ++++ b/none/tests/sw64-insn/fmsd-219.S +@@ -0,0 +1,48 @@ ++ .text ++ .global _start ++_start: ++ ++x1: ++ /* 3.1415926 = 0x400921fb4d12d84a */ ++ ldi $17, 0x400921fb ++ sll $17, 32 ++ ldi $17, 0x4d12d84a($17) ++ ifmovd $17, $f17 ++ ++x2: ++ /* 2.71828 = 0x4005bf0995aaf790 */ ++ ldi $18, 0x4005bf09 ++ sll $18, 16 ++ ldi $18, 0x95aa($18) ++ sll $18, 16 ++ ldi $18, 0xf790($18) ++ ifmovd $18, $f18 ++ ++x3: ++ /* 1.4142136 = 0x3ff6 a09e 7098 ef50 */ ++ ldi $19, 0x3ff6a09e ++ sll $19, 16 ++ ldi $19, 0x7098($19) ++ sll $19, 16 ++ ldi $19, 0xef50($19) ++ ifmovd $19, $f19 ++ ++result: ++ /* 7.125514732728 = 0x401c 8086 ef20 ee88 */ ++ ldi $20, 0x401c ++ sll $20, 16 ++ ldi $20, 0x8086($20) ++ sll $20, 16 ++ ldi $20, 0xef20($20) ++ sll $20, 16 ++ ldi $20, 0xee88($20) ++ ifmovd $20, $f20 ++ ++run: ++ fmsd $f17, $f18, $f19, $f21 ++ fsubd $f20, $f21, $f16 ++ fimovd $f16, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/fmss-218.S b/none/tests/sw64-insn/fmss-218.S +new file mode 100644 +index 000000000..7dd42e57c +--- /dev/null ++++ b/none/tests/sw64-insn/fmss-218.S +@@ -0,0 +1,52 @@ ++ .text ++ .global _start ++_start: ++ ++x1: ++ /* 3.1415926 = 0x400921fb4d12d84a */ ++ ldi $17, 0x400921fb ++ sll $17, 32 ++ ldi $17, 0x4d12d84a($17) ++ ifmovd $17, $f17 ++ ++x2: ++ /* 2.71828 = 0x4005bf0995aaf790 */ ++ ldi $18, 0x4005bf09 ++ sll $18, 16 ++ ldi $18, 0x95aa($18) ++ sll $18, 16 ++ ldi $18, 0xf790($18) ++ ifmovd $18, $f18 ++ ++x3: ++ /* 1.4142136 = 0x3ff6 a09e 7098 ef50 */ ++ ldi $19, 0x3ff6a09e ++ sll $19, 16 ++ ldi $19, 0x7098($19) ++ sll $19, 16 ++ ldi $19, 0xef50($19) ++ ifmovd $19, $f19 ++ ++result: ++ /* 7.1255145072937012 = 0x401c 8086 e000 0000 */ ++ ldi $20, 0x401c ++ sll $20, 16 ++ ldi $20, 0x8086($20) ++ sll $20, 16 ++ ldi $20, 0xe000($20) ++ sll $20, 16 ++ ldi $20, 0x0000($20) ++ ifmovd $20, $f20 ++ ++run: ++ fcvtds $f17, $f1 ++ fcvtds $f18, $f2 ++ fcvtds $f19, $f3 ++ fcvtds $f20, $f21 ++ fmss $f1, $f2, $f3, $f4 ++ fsubs $f4, $f21, $f16 ++ fimovs $f16, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/fmuld-185.S b/none/tests/sw64-insn/fmuld-185.S +new file mode 100644 +index 000000000..a073e1b56 +--- /dev/null ++++ b/none/tests/sw64-insn/fmuld-185.S +@@ -0,0 +1,18 @@ ++ .text ++ .global _start ++_start: ++ ldi $17, 42 ++ ifmovd $17, $f16 ++ fcvtld $f16, $f17 ++ ldi $18, 2 ++ ifmovd $18, $f16 ++ fcvtld $f16, $f18 ++ fmuld $f17, $f18, $f19 ++ fcvtdl $f19, $f16 ++ fimovd $f16, $16 ++ cmpeq $16, 84, $16 ++ subl $16, 1 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/fmuls-184.S b/none/tests/sw64-insn/fmuls-184.S +new file mode 100644 +index 000000000..9c3ca4632 +--- /dev/null ++++ b/none/tests/sw64-insn/fmuls-184.S +@@ -0,0 +1,40 @@ ++ .text ++ .global _start ++_start: ++ ++x1: ++ /* 3.1415926 = 0x400921fb4d12d84a */ ++ ldi $17, 0x400921fb ++ sll $17, 32 ++ ldi $17, 0x4d12d84a($17) ++ ifmovd $17, $f17 ++ ++x2: ++ /* 2.71828 = 0x4005bf0995aaf790 */ ++ ldi $18, 0x4005bf09 ++ sll $18, 16 ++ ldi $18, 0x95aa($18) ++ sll $18, 16 ++ ldi $18, 0xf790($18) ++ ifmovd $18, $f18 ++ ++result: ++ /* 8.5397281646728516 = 0x4021145740000000 */ ++ ldi $19, 0x40211457 ++ sll $19, 32 ++ ldi $19, 0x40000000($19) ++ ifmovd $19, $f19 ++ ++run: ++ fcvtds $f17, $f1 ++ fcvtds $f18, $f2 ++ fcvtds $f19, $f3 ++ fmuls $f1, $f2, $f4 ++ ldi $16, 0 ++ fsubs $f4, $f3, $f1 ++ fbeq $f1, exit ++ ldi $16, 1 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/fnmad-221.S b/none/tests/sw64-insn/fnmad-221.S +new file mode 100644 +index 000000000..817af484a +--- /dev/null ++++ b/none/tests/sw64-insn/fnmad-221.S +@@ -0,0 +1,48 @@ ++ .text ++ .global _start ++_start: ++ ++x1: ++ /* 3.1415926 = 0x400921fb4d12d84a */ ++ ldi $17, 0x400921fb ++ sll $17, 32 ++ ldi $17, 0x4d12d84a($17) ++ ifmovd $17, $f17 ++ ++x2: ++ /* 2.71828 = 0x4005bf0995aaf790 */ ++ ldi $18, 0x4005bf09 ++ sll $18, 16 ++ ldi $18, 0x95aa($18) ++ sll $18, 16 ++ ldi $18, 0xf790($18) ++ ifmovd $18, $f18 ++ ++x3: ++ /* 1.4142136 = 0x3ff6 a09e 7098 ef50 */ ++ ldi $19, 0x3ff6a09e ++ sll $19, 16 ++ ldi $19, 0x7098($19) ++ sll $19, 16 ++ ldi $19, 0xef50($19) ++ ifmovd $19, $f19 ++ ++result: ++ /* -7.125514732728 = 0xc01c 8086 ef20 ee88 */ ++ ldi $20, 0xc01c ++ sll $20, 16 ++ ldi $20, 0x8086($20) ++ sll $20, 16 ++ ldi $20, 0xef20($20) ++ sll $20, 16 ++ ldi $20, 0xee88($20) ++ ifmovd $20, $f20 ++ ++run: ++ fnmad $f17, $f18, $f19, $f21 ++ fsubd $f20, $f21, $f16 ++ fimovd $f16, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/fnmas-220.S b/none/tests/sw64-insn/fnmas-220.S +new file mode 100644 +index 000000000..77244870c +--- /dev/null ++++ b/none/tests/sw64-insn/fnmas-220.S +@@ -0,0 +1,52 @@ ++ .text ++ .global _start ++_start: ++ ++x1: ++ /* 3.1415926 = 0x400921fb4d12d84a */ ++ ldi $17, 0x400921fb ++ sll $17, 32 ++ ldi $17, 0x4d12d84a($17) ++ ifmovd $17, $f17 ++ ++x2: ++ /* 2.71828 = 0x4005bf0995aaf790 */ ++ ldi $18, 0x4005bf09 ++ sll $18, 16 ++ ldi $18, 0x95aa($18) ++ sll $18, 16 ++ ldi $18, 0xf790($18) ++ ifmovd $18, $f18 ++ ++x3: ++ /* 1.4142136 = 0x3ff6 a09e 7098 ef50 */ ++ ldi $19, 0x3ff6a09e ++ sll $19, 16 ++ ldi $19, 0x7098($19) ++ sll $19, 16 ++ ldi $19, 0xef50($19) ++ ifmovd $19, $f19 ++ ++result: ++ /* -7.1255145072937012 = 0xc01c 8086 e000 0000 */ ++ ldi $20, 0xc01c ++ sll $20, 16 ++ ldi $20, 0x8086($20) ++ sll $20, 16 ++ ldi $20, 0xe000($20) ++ sll $20, 16 ++ ldi $20, 0x0000($20) ++ ifmovd $20, $f20 ++ ++run: ++ fcvtds $f17, $f1 ++ fcvtds $f18, $f2 ++ fcvtds $f19, $f3 ++ fcvtds $f20, $f21 ++ fnmas $f1, $f2, $f3, $f4 ++ fsubs $f4, $f21, $f16 ++ fimovs $f16, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/fnmsd-223.S b/none/tests/sw64-insn/fnmsd-223.S +new file mode 100644 +index 000000000..472cbc2ba +--- /dev/null ++++ b/none/tests/sw64-insn/fnmsd-223.S +@@ -0,0 +1,48 @@ ++ .text ++ .global _start ++_start: ++ ++x1: ++ /* 3.1415926 = 0x400921fb4d12d84a */ ++ ldi $17, 0x400921fb ++ sll $17, 32 ++ ldi $17, 0x4d12d84a($17) ++ ifmovd $17, $f17 ++ ++x2: ++ /* 2.71828 = 0x4005bf0995aaf790 */ ++ ldi $18, 0x4005bf09 ++ sll $18, 16 ++ ldi $18, 0x95aa($18) ++ sll $18, 16 ++ ldi $18, 0xf790($18) ++ ifmovd $18, $f18 ++ ++x3: ++ /* 1.4142136 = 0x3ff6 a09e 7098 ef50 */ ++ ldi $19, 0x3ff6a09e ++ sll $19, 16 ++ ldi $19, 0x7098($19) ++ sll $19, 16 ++ ldi $19, 0xef50($19) ++ ifmovd $19, $f19 ++ ++result: ++ /* -9.9539419327280001 = 0xc023 e86b 13b6 b318 */ ++ ldi $20, 0xc023 ++ sll $20, 16 ++ ldi $20, 0xe86b($20) ++ sll $20, 16 ++ ldi $20, 0x13b6($20) ++ sll $20, 16 ++ ldi $20, 0xb318($20) ++ ifmovd $20, $f20 ++ ++run: ++ fnmsd $f17, $f18, $f19, $f21 ++ fsubd $f20, $f21, $f16 ++ fimovd $f16, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/fnmss-222.S b/none/tests/sw64-insn/fnmss-222.S +new file mode 100644 +index 000000000..c7735a762 +--- /dev/null ++++ b/none/tests/sw64-insn/fnmss-222.S +@@ -0,0 +1,52 @@ ++ .text ++ .global _start ++_start: ++ ++x1: ++ /* 3.1415926 = 0x400921fb4d12d84a */ ++ ldi $17, 0x400921fb ++ sll $17, 32 ++ ldi $17, 0x4d12d84a($17) ++ ifmovd $17, $f17 ++ ++x2: ++ /* 2.71828 = 0x4005bf0995aaf790 */ ++ ldi $18, 0x4005bf09 ++ sll $18, 16 ++ ldi $18, 0x95aa($18) ++ sll $18, 16 ++ ldi $18, 0xf790($18) ++ ifmovd $18, $f18 ++ ++x3: ++ /* 1.4142136 = 0x3ff6 a09e 7098 ef50 */ ++ ldi $19, 0x3ff6a09e ++ sll $19, 16 ++ ldi $19, 0x7098($19) ++ sll $19, 16 ++ ldi $19, 0xef50($19) ++ ifmovd $19, $f19 ++ ++result: ++ /* -9.9539422988891602 = 0xc023 e86b 2000 0000 */ ++ ldi $20, 0xc023 ++ sll $20, 16 ++ ldi $20, 0xe86b($20) ++ sll $20, 16 ++ ldi $20, 0x2000($20) ++ sll $20, 16 ++ ldi $20, 0x0000($20) ++ ifmovd $20, $f20 ++ ++run: ++ fcvtds $f17, $f1 ++ fcvtds $f18, $f2 ++ fcvtds $f19, $f3 ++ fcvtds $f20, $f21 ++ fnmss $f1, $f2, $f3, $f4 ++ fsubs $f4, $f21, $f16 ++ fimovs $f16, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/fseleq-224.S b/none/tests/sw64-insn/fseleq-224.S +new file mode 100644 +index 000000000..b1f98f0cc +--- /dev/null ++++ b/none/tests/sw64-insn/fseleq-224.S +@@ -0,0 +1,15 @@ ++ .text ++ .global _start ++_start: ++ ldi $17, 42 ++ ifmovd $17, $f17 ++ ldi $18, 0 ++ ifmovd $18, $f18 ++ fseleq $f18, $f18, $f17, $f19 ++ ldi $16, 0 ++ fbeq $f19, .exit ++ ldi $16, 1 ++ ++.exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/fselge-229.S b/none/tests/sw64-insn/fselge-229.S +new file mode 100644 +index 000000000..d41fb8e27 +--- /dev/null ++++ b/none/tests/sw64-insn/fselge-229.S +@@ -0,0 +1,49 @@ ++ .text ++ .global _start ++_start: ++ ++x1: ++ /* 3.1415926 = 0x400921fb4d12d84a */ ++ ldi $17, 0x400921fb ++ sll $17, 32 ++ ldi $17, 0x4d12d84a($17) ++ ifmovd $17, $f17 ++ ++x2: ++ /* 2.71828 = 0x4005bf0995aaf790 */ ++ ldi $18, 0x4005bf09 ++ sll $18, 16 ++ ldi $18, 0x95aa($18) ++ sll $18, 16 ++ ldi $18, 0xf790($18) ++ ifmovd $18, $f18 ++ ++x3: ++ /* 1.4142136 = 0x3ff6 a09e 7098 ef50 */ ++ ldi $19, 0x3ff6a09e ++ sll $19, 16 ++ ldi $19, 0x7098($19) ++ sll $19, 16 ++ ldi $19, 0xef50($19) ++ ifmovd $19, $f19 ++ ++result: ++ /* 9.9539419327280001 = 0x4023 e86b 13b6 b318 */ ++ ldi $20, 0x4023 ++ sll $20, 16 ++ ldi $20, 0xe86b($20) ++ sll $20, 16 ++ ldi $20, 0x13b6($20) ++ sll $20, 16 ++ ldi $20, 0xb318($20) ++ ifmovd $20, $f20 ++ ++run: ++ fsubd $f17, $f18, $f21 ++ fselge $f21, $f17, $f18, $f22 ++ fsubd $f17, $f22, $f16 ++ fimovd $f16, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/fselgt-228.S b/none/tests/sw64-insn/fselgt-228.S +new file mode 100644 +index 000000000..4c7657e14 +--- /dev/null ++++ b/none/tests/sw64-insn/fselgt-228.S +@@ -0,0 +1,49 @@ ++ .text ++ .global _start ++_start: ++ ++x1: ++ /* 3.1415926 = 0x400921fb4d12d84a */ ++ ldi $17, 0x400921fb ++ sll $17, 32 ++ ldi $17, 0x4d12d84a($17) ++ ifmovd $17, $f17 ++ ++x2: ++ /* 2.71828 = 0x4005bf0995aaf790 */ ++ ldi $18, 0x4005bf09 ++ sll $18, 16 ++ ldi $18, 0x95aa($18) ++ sll $18, 16 ++ ldi $18, 0xf790($18) ++ ifmovd $18, $f18 ++ ++x3: ++ /* 1.4142136 = 0x3ff6 a09e 7098 ef50 */ ++ ldi $19, 0x3ff6a09e ++ sll $19, 16 ++ ldi $19, 0x7098($19) ++ sll $19, 16 ++ ldi $19, 0xef50($19) ++ ifmovd $19, $f19 ++ ++result: ++ /* 9.9539419327280001 = 0x4023 e86b 13b6 b318 */ ++ ldi $20, 0x4023 ++ sll $20, 16 ++ ldi $20, 0xe86b($20) ++ sll $20, 16 ++ ldi $20, 0x13b6($20) ++ sll $20, 16 ++ ldi $20, 0xb318($20) ++ ifmovd $20, $f20 ++ ++run: ++ fsubd $f17, $f18, $f21 ++ fselgt $f21, $f17, $f18, $f22 ++ fsubd $f17, $f22, $f16 ++ fimovd $f16, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/fselle-227.S b/none/tests/sw64-insn/fselle-227.S +new file mode 100644 +index 000000000..c80328f40 +--- /dev/null ++++ b/none/tests/sw64-insn/fselle-227.S +@@ -0,0 +1,49 @@ ++ .text ++ .global _start ++_start: ++ ++x1: ++ /* 3.1415926 = 0x400921fb4d12d84a */ ++ ldi $17, 0x400921fb ++ sll $17, 32 ++ ldi $17, 0x4d12d84a($17) ++ ifmovd $17, $f17 ++ ++x2: ++ /* 2.71828 = 0x4005bf0995aaf790 */ ++ ldi $18, 0x4005bf09 ++ sll $18, 16 ++ ldi $18, 0x95aa($18) ++ sll $18, 16 ++ ldi $18, 0xf790($18) ++ ifmovd $18, $f18 ++ ++x3: ++ /* 1.4142136 = 0x3ff6 a09e 7098 ef50 */ ++ ldi $19, 0x3ff6a09e ++ sll $19, 16 ++ ldi $19, 0x7098($19) ++ sll $19, 16 ++ ldi $19, 0xef50($19) ++ ifmovd $19, $f19 ++ ++result: ++ /* 9.9539419327280001 = 0x4023 e86b 13b6 b318 */ ++ ldi $20, 0x4023 ++ sll $20, 16 ++ ldi $20, 0xe86b($20) ++ sll $20, 16 ++ ldi $20, 0x13b6($20) ++ sll $20, 16 ++ ldi $20, 0xb318($20) ++ ifmovd $20, $f20 ++ ++run: ++ fsubd $f17, $f18, $f21 ++ fselle $f21, $f17, $f18, $f22 ++ fsubd $f18, $f22, $f16 ++ fimovd $f16, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/fsellt-226.S b/none/tests/sw64-insn/fsellt-226.S +new file mode 100644 +index 000000000..ca3ba3b30 +--- /dev/null ++++ b/none/tests/sw64-insn/fsellt-226.S +@@ -0,0 +1,49 @@ ++ .text ++ .global _start ++_start: ++ ++x1: ++ /* 3.1415926 = 0x400921fb4d12d84a */ ++ ldi $17, 0x400921fb ++ sll $17, 32 ++ ldi $17, 0x4d12d84a($17) ++ ifmovd $17, $f17 ++ ++x2: ++ /* 2.71828 = 0x4005bf0995aaf790 */ ++ ldi $18, 0x4005bf09 ++ sll $18, 16 ++ ldi $18, 0x95aa($18) ++ sll $18, 16 ++ ldi $18, 0xf790($18) ++ ifmovd $18, $f18 ++ ++x3: ++ /* 1.4142136 = 0x3ff6 a09e 7098 ef50 */ ++ ldi $19, 0x3ff6a09e ++ sll $19, 16 ++ ldi $19, 0x7098($19) ++ sll $19, 16 ++ ldi $19, 0xef50($19) ++ ifmovd $19, $f19 ++ ++result: ++ /* 9.9539419327280001 = 0x4023 e86b 13b6 b318 */ ++ ldi $20, 0x4023 ++ sll $20, 16 ++ ldi $20, 0xe86b($20) ++ sll $20, 16 ++ ldi $20, 0x13b6($20) ++ sll $20, 16 ++ ldi $20, 0xb318($20) ++ ifmovd $20, $f20 ++ ++run: ++ fsubd $f17, $f18, $f21 ++ fsellt $f21, $f17, $f18, $f22 ++ fsubd $f18, $f22, $f16 ++ fimovd $f16, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/fselne-225.S b/none/tests/sw64-insn/fselne-225.S +new file mode 100644 +index 000000000..2e24d8826 +--- /dev/null ++++ b/none/tests/sw64-insn/fselne-225.S +@@ -0,0 +1,49 @@ ++ .text ++ .global _start ++_start: ++ ++x1: ++ /* 3.1415926 = 0x400921fb4d12d84a */ ++ ldi $17, 0x400921fb ++ sll $17, 32 ++ ldi $17, 0x4d12d84a($17) ++ ifmovd $17, $f17 ++ ++x2: ++ /* 2.71828 = 0x4005bf0995aaf790 */ ++ ldi $18, 0x4005bf09 ++ sll $18, 16 ++ ldi $18, 0x95aa($18) ++ sll $18, 16 ++ ldi $18, 0xf790($18) ++ ifmovd $18, $f18 ++ ++x3: ++ /* 1.4142136 = 0x3ff6 a09e 7098 ef50 */ ++ ldi $19, 0x3ff6a09e ++ sll $19, 16 ++ ldi $19, 0x7098($19) ++ sll $19, 16 ++ ldi $19, 0xef50($19) ++ ifmovd $19, $f19 ++ ++result: ++ /* 9.9539419327280001 = 0x4023 e86b 13b6 b318 */ ++ ldi $20, 0x4023 ++ sll $20, 16 ++ ldi $20, 0xe86b($20) ++ sll $20, 16 ++ ldi $20, 0x13b6($20) ++ sll $20, 16 ++ ldi $20, 0xb318($20) ++ ifmovd $20, $f20 ++ ++run: ++ fsubd $f17, $f18, $f21 ++ fselne $f21, $f17, $f18, $f22 ++ fsubd $f17, $f22, $f16 ++ fimovd $f16, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/fsqrtd-189.S b/none/tests/sw64-insn/fsqrtd-189.S +new file mode 100644 +index 000000000..8a0142297 +--- /dev/null ++++ b/none/tests/sw64-insn/fsqrtd-189.S +@@ -0,0 +1,39 @@ ++ .text ++ .global _start ++_start: ++ ++x1: ++ /* 3.1415926 = 0x400921fb4d12d84a */ ++ ldi $17, 0x400921fb ++ sll $17, 32 ++ ldi $17, 0x4d12d84a($17) ++ ifmovd $17, $f17 ++ ++x2: ++ /* 2.71828 = 0x4005bf0995aaf790 */ ++ ldi $18, 0x4005bf09 ++ sll $18, 16 ++ ldi $18, 0x95aa($18) ++ sll $18, 16 ++ ldi $18, 0xf790($18) ++ ifmovd $18, $f18 ++ ++result: ++ /* 1.7724538357881143 = 0x3ffc 5bf8 8da6 1346 */ ++ ldi $19, 0x3ffc5bf8 ++ sll $19, 16 ++ ldi $19, 0x8da6($19) ++ sll $19, 16 ++ ldi $19, 0x1346($19) ++ ifmovd $19, $f19 ++ ++run: ++ fsqrtd $f17, $f20 ++ fsubd $f20, $f19, $f16 ++ ldi $16, 0 ++ fbeq $f16, exit ++ ldi $16, 1 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/fsqrts-188.S b/none/tests/sw64-insn/fsqrts-188.S +new file mode 100644 +index 000000000..eba144a6a +--- /dev/null ++++ b/none/tests/sw64-insn/fsqrts-188.S +@@ -0,0 +1,42 @@ ++ .text ++ .global _start ++_start: ++ ++x1: ++ /* 3.1415926 = 0x400921fb4d12d84a */ ++ ldi $17, 0x400921fb ++ sll $17, 32 ++ ldi $17, 0x4d12d84a($17) ++ ifmovd $17, $f17 ++ ++x2: ++ /* 2.71828 = 0x4005bf0995aaf790 */ ++ ldi $18, 0x4005bf09 ++ sll $18, 16 ++ ldi $18, 0x95aa($18) ++ sll $18, 16 ++ ldi $18, 0xf790($18) ++ ifmovd $18, $f18 ++ ++result: ++ /* 1.772453784942627 = 0x3ffc 5bf8 8000 0000 */ ++ ldi $19, 0x3ffc5bf8 ++ sll $19, 16 ++ ldi $19, 0x8000($19) ++ sll $19, 16 ++ ldi $19, 0x0000($19) ++ ifmovd $19, $f19 ++ ++run: ++ fcvtds $f17, $f1 ++ #fcvtds $f18, $f2 ++ fcvtds $f19, $f3 ++ fsqrts $f1, $f4 ++ fsubs $f4, $f3, $f1 ++ ldi $16, 0 ++ fbeq $f1, exit ++ ldi $16, 1 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/fstd-351.S b/none/tests/sw64-insn/fstd-351.S +new file mode 100644 +index 000000000..763a14d6f +--- /dev/null ++++ b/none/tests/sw64-insn/fstd-351.S +@@ -0,0 +1,51 @@ ++ .text ++ .global _start ++_start: ++ ++x1: ++ /* 3.1415926 = 0x400921fb4d12d84a */ ++ ldi $17, 0x400921fb ++ sll $17, 32 ++ ldi $17, 0x4d12d84a($17) ++ ifmovd $17, $f17 ++ ++x2: ++ /* 2.71828 = 0x4005bf0995aaf790 */ ++ ldi $18, 0x4005bf09 ++ sll $18, 16 ++ ldi $18, 0x95aa($18) ++ sll $18, 16 ++ ldi $18, 0xf790($18) ++ ifmovd $18, $f18 ++ ++x3: ++ /* 1.4142136 = 0x3ff6 a09e 7098 ef50 */ ++ ldi $19, 0x3ff6a09e ++ sll $19, 16 ++ ldi $19, 0x7098($19) ++ sll $19, 16 ++ ldi $19, 0xef50($19) ++ ifmovd $19, $f19 ++ ++result: ++ /* 9.9539419327280001 = 0x4023 e86b 13b6 b318 */ ++ ldi $20, 0x4023 ++ sll $20, 16 ++ ldi $20, 0xe86b($20) ++ sll $20, 16 ++ ldi $20, 0x13b6($20) ++ sll $20, 16 ++ ldi $20, 0xb318($20) ++ ifmovd $20, $f20 ++ ++run: ++ ldi $sp, -8($sp) ++ fstd $f17, 0($sp) ++ fldd $f21, 0($sp) ++ fsubd $f17, $f21, $f16 ++ fimovd $f16, $16 ++ ldi $sp, 8($sp) ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/fsts-350.S b/none/tests/sw64-insn/fsts-350.S +new file mode 100644 +index 000000000..a64538159 +--- /dev/null ++++ b/none/tests/sw64-insn/fsts-350.S +@@ -0,0 +1,52 @@ ++ .text ++ .global _start ++_start: ++ ++x1: ++ /* 3.1415926 = 0x400921fb4d12d84a */ ++ ldi $17, 0x400921fb ++ sll $17, 32 ++ ldi $17, 0x4d12d84a($17) ++ ifmovd $17, $f17 ++ ++x2: ++ /* 2.71828 = 0x4005bf0995aaf790 */ ++ ldi $18, 0x4005bf09 ++ sll $18, 16 ++ ldi $18, 0x95aa($18) ++ sll $18, 16 ++ ldi $18, 0xf790($18) ++ ifmovd $18, $f18 ++ ++x3: ++ /* 1.4142136 = 0x3ff6 a09e 7098 ef50 */ ++ ldi $19, 0x3ff6a09e ++ sll $19, 16 ++ ldi $19, 0x7098($19) ++ sll $19, 16 ++ ldi $19, 0xef50($19) ++ ifmovd $19, $f19 ++ ++result: ++ /* 9.9539419327280001 = 0x4023 e86b 13b6 b318 */ ++ ldi $20, 0x4023 ++ sll $20, 16 ++ ldi $20, 0xe86b($20) ++ sll $20, 16 ++ ldi $20, 0x13b6($20) ++ sll $20, 16 ++ ldi $20, 0xb318($20) ++ ifmovd $20, $f20 ++ ++run: ++ ldi $sp, -8($sp) ++ fcvtds $f17, $f21 ++ fsts $f21, 0($sp) ++ flds $f22, 0($sp) ++ fsubd $f22, $f21, $f16 ++ fimovd $f16, $16 ++ ldi $sp, 8($sp) ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/fsubd-183.S b/none/tests/sw64-insn/fsubd-183.S +new file mode 100644 +index 000000000..6da04ae43 +--- /dev/null ++++ b/none/tests/sw64-insn/fsubd-183.S +@@ -0,0 +1,13 @@ ++ .text ++ .global _start ++_start: ++ ldi $17, 42 ++ ifmovd $17, $f17 ++ fcvtld $f17, $f18 ++ fsubd $f18, $f18, $f17 ++ fcvtdl $f17, $f16 ++ fimovd $f16, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/fsubs-182.S b/none/tests/sw64-insn/fsubs-182.S +new file mode 100644 +index 000000000..7b57b66b8 +--- /dev/null ++++ b/none/tests/sw64-insn/fsubs-182.S +@@ -0,0 +1,41 @@ ++ .text ++ .global _start ++_start: ++ ++x1: ++ /* 3.1415926 = 0x400921fb4d12d84a */ ++ ldi $17, 0x400921fb ++ sll $17, 32 ++ ldi $17, 0x4d12d84a($17) ++ ifmovd $17, $f17 ++ ++x2: ++ /* 2.71828 = 0x4005bf0995aaf790 */ ++ ldi $18, 0x4005bf09 ++ sll $18, 16 ++ ldi $18, 0x95aa($18) ++ sll $18, 16 ++ ldi $18, 0xf790($18) ++ ifmovd $18, $f18 ++ ++result: ++ /* 8.5397281646728516 = 0x4021145740000000 */ ++ ldi $19, 0x4005bf09 ++ sll $19, 16 ++ ldi $19, 0x95aa($19) ++ sll $19, 16 ++ ldi $19, 0xf790($19) ++ ifmovd $19, $f19 ++ ++ fcvtds $f17, $f1 ++ fcvtds $f18, $f2 ++ fcvtds $f19, $f3 ++ fmuls $f1, $f2, $f4 ++ ldi $16, 1 ++ fsubs $f4, $f3, $f1 ++ fbeq $f1, exit ++ ldi $16, 0 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/halt-12.S b/none/tests/sw64-insn/halt-12.S +new file mode 100644 +index 000000000..f66bb4e15 +--- /dev/null ++++ b/none/tests/sw64-insn/halt-12.S +@@ -0,0 +1,10 @@ ++ ++ .global _start ++_start: ++ unop ++ halt ++ ++exit: ++ ldi $0, 1 ++ ldi $16, 0 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/ifmovd-209.S b/none/tests/sw64-insn/ifmovd-209.S +new file mode 120000 +index 000000000..5a582e3e3 +--- /dev/null ++++ b/none/tests/sw64-insn/ifmovd-209.S +@@ -0,0 +1 @@ ++fimovd-104.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/ifmovs-208.S b/none/tests/sw64-insn/ifmovs-208.S +new file mode 120000 +index 000000000..7549c2b3b +--- /dev/null ++++ b/none/tests/sw64-insn/ifmovs-208.S +@@ -0,0 +1 @@ ++fimovs-103.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/imemb-9.S b/none/tests/sw64-insn/imemb-9.S +new file mode 100644 +index 000000000..7b1782d7e +--- /dev/null ++++ b/none/tests/sw64-insn/imemb-9.S +@@ -0,0 +1,62 @@ ++ .text ++ ++ .globl xchg_u32 ++xchg_u32: ++ ldi $30,-64($30) ++ stl $26,0($30) ++ stl $15,8($30) ++ mov $30,$15 ++ stl $16,48($15) ++ stl $17,56($15) ++ ldl $5,48($15) ++ ldl $1,56($15) ++ ldl $2,48($15) ++ memb ++ imemb ++ ldi $6, 0($2) ++ ++f1: ++ lldw $4, 0($6) ++ ldi $3, 1 ++ wr_f $3 ++ bis $31, $1, $3 ++ memb ++ imemb ++ lstw $3, 0($6) ++ rd_f $3 ++ bne $3, f2 ++ br f1 ++ ++f2: ++ mov $6,$2 ++ stl $4,56($15) ++ stl $3,32($15) ++ stl $2,40($15) ++ ldl $1,56($15) ++ mov $1,$0 ++ mov $15,$30 ++ ldl $26,0($30) ++ ldl $15,8($30) ++ ldi $30,64($30) ++ ret $31,($26),1 ++ ++ .global _start ++_start: ++ br $29, 1f ++1: ldgp $29, 0($29) ++ subl $30, 16, $30 ++ mov 0, $15 ++ ++ ldi $sp, -16($sp) ++ ldi $17, 42 ++ stl $17, 0($sp) ++ ldi $16, 0($sp) ++ ldi $17, 43 ++ call $26, xchg_u32 ++ mov $0, $16 ++ subl $16, 42 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/inshb-72.S b/none/tests/sw64-insn/inshb-72.S +new file mode 100644 +index 000000000..fe0ed2456 +--- /dev/null ++++ b/none/tests/sw64-insn/inshb-72.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0xf0f1f2 ++ ldi $18, 1 ++ inshb $17, $18, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/inshbi-143.S b/none/tests/sw64-insn/inshbi-143.S +new file mode 100644 +index 000000000..66061cc5d +--- /dev/null ++++ b/none/tests/sw64-insn/inshbi-143.S +@@ -0,0 +1,10 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0xf0f1f2 ++ inshb $17, 1, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/inshh-73.S b/none/tests/sw64-insn/inshh-73.S +new file mode 100644 +index 000000000..1bdb1ecce +--- /dev/null ++++ b/none/tests/sw64-insn/inshh-73.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0xf0f1f2 ++ ldi $18, 7 ++ inshh $17, $18, $16 ++ subl $16, 0xf1 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/inshhi-144.S b/none/tests/sw64-insn/inshhi-144.S +new file mode 100644 +index 000000000..885a0959c +--- /dev/null ++++ b/none/tests/sw64-insn/inshhi-144.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0xf0f1f2 ++ inshh $17, 7, $16 ++ subl $16, 0xf1 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/inshl-75.S b/none/tests/sw64-insn/inshl-75.S +new file mode 100644 +index 000000000..72e1bf3ac +--- /dev/null ++++ b/none/tests/sw64-insn/inshl-75.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0xf0f1f2 ++ ldi $18, 6 ++ inshl $17, $18, $16 ++ subl $16, 0xf0 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/inshli-146.S b/none/tests/sw64-insn/inshli-146.S +new file mode 100644 +index 000000000..25ab03169 +--- /dev/null ++++ b/none/tests/sw64-insn/inshli-146.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0xf0f1f2 ++ inshl $17, 6, $16 ++ subl $16, 0xf0 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/inshw-74.S b/none/tests/sw64-insn/inshw-74.S +new file mode 100644 +index 000000000..6f9051b41 +--- /dev/null ++++ b/none/tests/sw64-insn/inshw-74.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0xf0f1f2 ++ ldi $18, 6 ++ inshw $17, $18, $16 ++ subl $16, 0xf0 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/inshwi-145.S b/none/tests/sw64-insn/inshwi-145.S +new file mode 100644 +index 000000000..3b95832fe +--- /dev/null ++++ b/none/tests/sw64-insn/inshwi-145.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0xf0f1f2 ++ inshw $17, 6, $16 ++ subl $16, 0xf0 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/inslb-68.S b/none/tests/sw64-insn/inslb-68.S +new file mode 100644 +index 000000000..84c10994d +--- /dev/null ++++ b/none/tests/sw64-insn/inslb-68.S +@@ -0,0 +1,13 @@ ++ ++ .global _start ++_start: ++ ldi $17, 1 ++ ldi $18, 1 ++ inslb $17, $18, $16 ++ srl $16, 8 ++ subl $16, 1 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/inslbi-139.S b/none/tests/sw64-insn/inslbi-139.S +new file mode 100644 +index 000000000..4335feb3d +--- /dev/null ++++ b/none/tests/sw64-insn/inslbi-139.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 1 ++ inslb $17, 1, $16 ++ srl $16, 8 ++ subl $16, 1 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/inslh-69.S b/none/tests/sw64-insn/inslh-69.S +new file mode 100644 +index 000000000..f51da7de5 +--- /dev/null ++++ b/none/tests/sw64-insn/inslh-69.S +@@ -0,0 +1,13 @@ ++ ++ .global _start ++_start: ++ ldi $17, 1 ++ ldi $18, 1 ++ inslh $17, $18, $16 ++ srl $16, 8 ++ subl $16, 1 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/inslhi-140.S b/none/tests/sw64-insn/inslhi-140.S +new file mode 100644 +index 000000000..4e175d74e +--- /dev/null ++++ b/none/tests/sw64-insn/inslhi-140.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 1 ++ inslh $17, 1, $16 ++ srl $16, 8 ++ subl $16, 1 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/insll-71.S b/none/tests/sw64-insn/insll-71.S +new file mode 100644 +index 000000000..39e10ef9d +--- /dev/null ++++ b/none/tests/sw64-insn/insll-71.S +@@ -0,0 +1,13 @@ ++ ++ .global _start ++_start: ++ ldi $17, 1 ++ ldi $18, 1 ++ insll $17, $18, $16 ++ srl $16, 8 ++ subl $16, 1 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/inslli-142.S b/none/tests/sw64-insn/inslli-142.S +new file mode 100644 +index 000000000..d66643c49 +--- /dev/null ++++ b/none/tests/sw64-insn/inslli-142.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 1 ++ insll $17, 1, $16 ++ srl $16, 8 ++ subl $16, 1 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/inslw-70.S b/none/tests/sw64-insn/inslw-70.S +new file mode 100644 +index 000000000..f5ac75d09 +--- /dev/null ++++ b/none/tests/sw64-insn/inslw-70.S +@@ -0,0 +1,13 @@ ++ ++ .global _start ++_start: ++ ldi $17, 1 ++ ldi $18, 1 ++ inslw $17, $18, $16 ++ srl $16, 8 ++ subl $16, 1 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/inslwi-141.S b/none/tests/sw64-insn/inslwi-141.S +new file mode 100644 +index 000000000..557d6583a +--- /dev/null ++++ b/none/tests/sw64-insn/inslwi-141.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 1 ++ inslw $17, 1, $16 ++ srl $16, 8 ++ subl $16, 1 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/insn-list b/none/tests/sw64-insn/insn-list +new file mode 100644 +index 000000000..b9a525007 +--- /dev/null ++++ b/none/tests/sw64-insn/insn-list +@@ -0,0 +1,367 @@ ++sys_call_b-1 ++sys_call-2 ++call-3 ++ret-4 ++jmp-5 ++br-6 ++bsr-7 ++memb-8 ++imemb-9 ++rtc-10 ++rcid-11 ++halt-12 ++rd_f-13 ++wr_f-14 ++rtid-15 ++pri_rcsr-16 ++pri_wcsr-17 ++pri_ret-18 ++lldw-19 ++lldl-20 ++ldw_inc-21 ++ldl_inc-22 ++ldw_dec-23 ++ldl_dec-24 ++ldw_set-25 ++ldl_set-26 ++lstw-27 ++lstl-28 ++ldw_nc-29 ++ldl_nc-30 ++ldd_nc-31 ++stw_nc-32 ++stl_nc-33 ++std_nc-34 ++ldwe-35 ++ldse-36 ++ldde-37 ++vlds-38 ++vldd-39 ++vsts-40 ++vstd-41 ++addw-42 ++subw-43 ++s4addw-44 ++s4subw-45 ++s8addw-46 ++s8subw-47 ++addl-48 ++subl-49 ++s4addl-50 ++s4subl-51 ++s8addl-52 ++s8subl-53 ++mulw-54 ++mull-55 ++umulh-56 ++cmpeq-57 ++cmplt-58 ++cmple-59 ++cmpult-60 ++cmpule-61 ++and-62 ++bic-63 ++bis-64 ++ornot-65 ++xor-66 ++eqv-67 ++inslb-68 ++inslh-69 ++inslw-70 ++insll-71 ++inshb-72 ++inshh-73 ++inshw-74 ++inshl-75 ++sll-76 ++srl-77 ++sra-78 ++extlb-79 ++extlh-80 ++extlw-81 ++extll-82 ++exthb-83 ++exthh-84 ++exthw-85 ++exthl-86 ++ctpop-87 ++ctlz-88 ++cttz-89 ++masklb-90 ++masklh-91 ++masklw-92 ++maskll-93 ++maskhb-94 ++maskhh-95 ++maskhw-96 ++maskhl-97 ++zap-98 ++zapnot-99 ++sextb-100 ++sexth-101 ++cmpgeb-102 ++fimovs-103 ++fimovd-104 ++seleq-105 ++selge-106 ++selgt-107 ++selle-108 ++sellt-109 ++selne-110 ++sellbc-111 ++sellbs-112 ++addwi-113 ++subwi-114 ++s4addwi-115 ++s4subwi-116 ++s8addwi-117 ++s8subwi-118 ++addli-119 ++subli-120 ++s4addli-121 ++s4subli-122 ++s8addli-123 ++s8subli-124 ++mulwi-125 ++mulli-126 ++umulhi-127 ++cmpeqi-128 ++cmplti-129 ++cmplei-130 ++cmpulti-131 ++cmpulei-132 ++andi-133 ++bici-134 ++bisi-135 ++ornoti-136 ++xori-137 ++eqvi-138 ++inslbi-139 ++inslhi-140 ++inslwi-141 ++inslli-142 ++inshbi-143 ++inshhi-144 ++inshwi-145 ++inshli-146 ++slli-147 ++srli-148 ++srai-149 ++extlbi-150 ++extlhi-151 ++extlwi-152 ++extlli-153 ++exthbi-154 ++exthhi-155 ++exthwi-156 ++exthli-157 ++masklbi-158 ++masklhi-159 ++masklwi-160 ++masklli-161 ++maskhbi-162 ++maskhhi-163 ++maskhwi-164 ++maskhli-165 ++zapi-166 ++zapnoti-167 ++sextbi-168 ++sexthi-169 ++cmpgebi-170 ++seleqi-171 ++selgei-172 ++selgti-173 ++sellei-174 ++sellti-175 ++selnei-176 ++sellbci-177 ++sellbsi-178 ++vlogzz-179 ++fadds-180 ++faddd-181 ++fsubs-182 ++fsubd-183 ++fmuls-184 ++fmuld-185 ++fdivs-186 ++fdivd-187 ++fsqrts-188 ++fsqrtd-189 ++fcmpeq-190 ++fcmple-191 ++fcmplt-192 ++fcmpun-193 ++fcvtsd-194 ++fcvtds-195 ++fcvtdl_g-196 ++fcvtdl_p-197 ++fcvtdl_z-198 ++fcvtdl_n-199 ++fcvtdl-200 ++fcvtwl-201 ++fcvtlw-202 ++fcvtls-203 ++fcvtld-204 ++fcpys-205 ++fcpyse-206 ++fcpysn-207 ++ifmovs-208 ++ifmovd-209 ++rfpcr-210 ++wfpcr-211 ++setfpec0-212 ++setfpec1-213 ++setfpec2-214 ++setfpec3-215 ++fmas-216 ++fmad-217 ++fmss-218 ++fmsd-219 ++fnmas-220 ++fnmad-221 ++fnmss-222 ++fnmsd-223 ++fseleq-224 ++fselne-225 ++fsellt-226 ++fselle-227 ++fselgt-228 ++fselge-229 ++vaddw-230 ++vsubw-231 ++vcmpgew-232 ++vcmpeqw-233 ++vcmplew-234 ++vcmpltw-235 ++vcmpulew-236 ++vcmpultw-237 ++vsllw-238 ++vsrlw-239 ++vsraw-240 ++vrolw-241 ++sllow-242 ++srlow-243 ++vaddl-244 ++vsubl-245 ++ctpopow-246 ++ctlzow-247 ++vucaddw-248 ++vucsubw-249 ++vucaddh-250 ++vucsubh-251 ++vucaddb-252 ++vucsubb-253 ++vaddwi-254 ++vsubwi-255 ++vcmpgewi-256 ++vcmpeqwi-257 ++vcmplewi-258 ++vcmpltwi-259 ++vcmpulewi-260 ++vcmpultwi-261 ++vsllwi-262 ++vsrlwi-263 ++vsrawi-264 ++vrolwi-265 ++sllowi-266 ++srlowi-267 ++vaddli-268 ++vsubli-269 ++vucaddwi-270 ++vucsubwi-271 ++vucaddhi-272 ++vucsubhi-273 ++vucaddbi-274 ++vucsubbi-275 ++vadds-276 ++vaddd-277 ++vsubs-278 ++vsubd-279 ++vmuls-280 ++vmuld-281 ++vdivs-282 ++vdivd-283 ++vsqrts-284 ++vsqrtd-285 ++vfcmpeq-286 ++vfcmple-287 ++vfcmplt-288 ++vfcmpun-289 ++vcpys-290 ++vcpyse-291 ++vcpysn-292 ++vmas-293 ++vmad-294 ++vmss-295 ++vmsd-296 ++vnmas-297 ++vnmad-298 ++vnmss-299 ++vnmsd-300 ++vfseleq-301 ++vfsellt-302 ++vfselle-303 ++vseleqw-304 ++vsellbcw-305 ++vselltw-306 ++vsellew-307 ++vinsw-308 ++vinsf-309 ++vextw-310 ++vextf-311 ++vcpyw-312 ++vcpyf-313 ++vconw-314 ++vshfw-315 ++vcons-316 ++vcond-317 ++vseleqwi-318 ++vsellbcwi-319 ++vselltwi-320 ++vsellewi-321 ++vldw_u-322 ++vstw_u-323 ++vlds_u-324 ++vsts_u-325 ++vldd_u-326 ++vstd_u-327 ++vstw_ul-328 ++vstw_uh-329 ++vsts_ul-330 ++vsts_uh-331 ++vstd_ul-332 ++vstd_uh-333 ++vldd_nc-334 ++vstd_nc-335 ++ldbu-336 ++ldhu-337 ++ldw-338 ++ldl-339 ++ldl_u-340 ++pri_ld-341 ++flds-342 ++fldd-343 ++stb-344 ++sth-345 ++stw-346 ++stl-347 ++stl_u-348 ++pri_st-349 ++fsts-350 ++fstd-351 ++beq-352 ++bne-353 ++blt-354 ++ble-355 ++bgt-356 ++bge-357 ++blbc-358 ++blbs-359 ++fbeq-360 ++fbne-361 ++fblt-362 ++fble-363 ++fbgt-364 ++fbge-365 ++ldi-366 ++ldih-367 +diff --git a/none/tests/sw64-insn/jmp-5.S b/none/tests/sw64-insn/jmp-5.S +new file mode 100644 +index 000000000..75e2b2184 +--- /dev/null ++++ b/none/tests/sw64-insn/jmp-5.S +@@ -0,0 +1,16 @@ ++ ++ .global _start ++_start: ++ br $29, 1f ++1: ldgp $29, 0($29) ++ subl $30, 16, $30 ++ mov 0, $15 ++ ++ ldi $16, 0 ++ jmp $26, exit ++ ldi $16, 1 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/ldbu-336.S b/none/tests/sw64-insn/ldbu-336.S +new file mode 120000 +index 000000000..904ba1366 +--- /dev/null ++++ b/none/tests/sw64-insn/ldbu-336.S +@@ -0,0 +1 @@ ++stb-344.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/ldd_nc-31.S b/none/tests/sw64-insn/ldd_nc-31.S +new file mode 100644 +index 000000000..ed9b33f2d +--- /dev/null ++++ b/none/tests/sw64-insn/ldd_nc-31.S +@@ -0,0 +1,19 @@ ++ ++ .global _start ++_start: ++ ldgp $29,0($27) ++ unop ++ ldi $sp, -16($sp) ++ ldi $17, 42 ++ ifmovd $17, $f17 ++ std_nc $f17, 0($sp) ++ ldd_nc $f18, 0($sp) ++ ldi $sp, 16($sp) ++ fcmpeq $f17, $f18, $f16 ++ ldi $16, 0 ++ fbne $f16, exit ++ ldi $16, 1 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/ldde-37.S b/none/tests/sw64-insn/ldde-37.S +new file mode 100644 +index 000000000..584bf54ac +--- /dev/null ++++ b/none/tests/sw64-insn/ldde-37.S +@@ -0,0 +1,52 @@ ++ ++ .global _start ++_start: ++x1: ++ /* 3.1415926 = 0x400921fb4d12d84a */ ++ ldi $17, 0x400921fb ++ sll $17, 32 ++ ldi $17, 0x4d12d84a($17) ++ ifmovd $17, $f17 ++ ++x2: ++ /* 0.0 */ ++ ldi $18, 0x0 ++ ifmovd $18, $f18 ++ ++result: ++ /* 25.132740800000001 = 0x4039 21fb 4d12 d84a */ ++ ldi $19, 0x403921fb ++ sll $19, 16 ++ ldi $19, 0x4d12($19) ++ sll $19, 16 ++ ldi $19, 0xd84a($19) ++ ifmovd $19, $f19 ++ ++run: ++ ldi $sp, -256($sp) ++ fstd $f17, 0($sp) ++ ldde $f1, 0($sp) ++ vaddd $f1, $f1, $f2 /* 3.14 + 3.14 */ ++ vstd $f2, 0($sp) ++ ++sum_wrapper: ++ ldi $17, 0($sp) ++ ldi $23, 4 ++sum: ++ fldd $f2, 0($17) ++ faddd $f18, $f2 ++ subl $23, 1 ++ ldi $17, 8($17) ++ bne $23, sum ++ ++sum_end: ++ ldi $sp, 256($sp) ++ fcmpeq $f18, $f19, $f16 ++ ldi $16, 1 ++ fbeq $f16, exit ++ ldi $16, 0 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/ldhu-337.S b/none/tests/sw64-insn/ldhu-337.S +new file mode 120000 +index 000000000..9901b1edc +--- /dev/null ++++ b/none/tests/sw64-insn/ldhu-337.S +@@ -0,0 +1 @@ ++sth-345.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/ldi-366.S b/none/tests/sw64-insn/ldi-366.S +new file mode 100644 +index 000000000..f75e1fa26 +--- /dev/null ++++ b/none/tests/sw64-insn/ldi-366.S +@@ -0,0 +1,11 @@ ++ ++.text ++ .global _start ++_start: ++ ldih $29, 0($27) !gpdisp!1 ++ ldi $29, 0($29) !gpdisp!1 ++ ++exit: ++ ldi $0, 1 ++ ldi $16, 0 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/ldih-367.S b/none/tests/sw64-insn/ldih-367.S +new file mode 120000 +index 000000000..8ab4dc5e7 +--- /dev/null ++++ b/none/tests/sw64-insn/ldih-367.S +@@ -0,0 +1 @@ ++ldi-366.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/ldl-339.S b/none/tests/sw64-insn/ldl-339.S +new file mode 120000 +index 000000000..5e197a67c +--- /dev/null ++++ b/none/tests/sw64-insn/ldl-339.S +@@ -0,0 +1 @@ ++stl-347.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/ldl_dec-24.S b/none/tests/sw64-insn/ldl_dec-24.S +new file mode 120000 +index 000000000..1ec4cb5a5 +--- /dev/null ++++ b/none/tests/sw64-insn/ldl_dec-24.S +@@ -0,0 +1 @@ ++ldl_inc-22.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/ldl_inc-22.S b/none/tests/sw64-insn/ldl_inc-22.S +new file mode 100644 +index 000000000..76fca28fd +--- /dev/null ++++ b/none/tests/sw64-insn/ldl_inc-22.S +@@ -0,0 +1,17 @@ ++ ++ .global _start ++_start: ++ ldgp $29,0($27) ++ unop ++ ldi $sp, -16($sp) ++ ldl $17, 42 ++ stw $17, 0($sp) ++ #ldl_set $18, 0($sp) ++ #ldl_inc $19, 0($sp) ++ #ldl_dec $20, 0$($sp) ++ ldi $sp, 16($sp) ++ ldi $16, 0 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/ldl_nc-30.S b/none/tests/sw64-insn/ldl_nc-30.S +new file mode 100644 +index 000000000..d3b776276 +--- /dev/null ++++ b/none/tests/sw64-insn/ldl_nc-30.S +@@ -0,0 +1,16 @@ ++ ++ .global _start ++_start: ++ ldgp $29,0($27) ++ unop ++ ldi $sp, -16($sp) ++ ldi $17, 42 ++ stl_nc $17, 0($sp) ++ ldl_nc $18, 0($sp) ++ ldi $sp, 16($sp) ++ cmpeq $17, $18, $16 ++ subl $16, 1 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/ldl_set-26.S b/none/tests/sw64-insn/ldl_set-26.S +new file mode 120000 +index 000000000..1ec4cb5a5 +--- /dev/null ++++ b/none/tests/sw64-insn/ldl_set-26.S +@@ -0,0 +1 @@ ++ldl_inc-22.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/ldl_u-340.S b/none/tests/sw64-insn/ldl_u-340.S +new file mode 120000 +index 000000000..4962302c4 +--- /dev/null ++++ b/none/tests/sw64-insn/ldl_u-340.S +@@ -0,0 +1 @@ ++stl_u-348.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/ldse-36.S b/none/tests/sw64-insn/ldse-36.S +new file mode 100644 +index 000000000..44c3d5e89 +--- /dev/null ++++ b/none/tests/sw64-insn/ldse-36.S +@@ -0,0 +1,56 @@ ++ ++ .global _start ++_start: ++x1: ++ /* 3.1415926 = 0x400921fb4d12d84a */ ++ ldi $17, 0x400921fb ++ sll $17, 32 ++ ldi $17, 0x4d12d84a($17) ++ ifmovd $17, $f17 ++ ++x2: ++ /* 2.71828 = 0x4005bf0995aaf790 */ ++ ldi $18, 0x4005bf09 ++ sll $18, 16 ++ ldi $18, 0x95aa($18) ++ sll $18, 16 ++ ldi $18, 0xf790($18) ++ ifmovd $18, $f18 ++ ++result: ++ /* 1.772453784942627 = 0x3ffc 5bf8 8000 0000 */ ++ ldi $19, 0x3ffc5bf8 ++ sll $19, 16 ++ ldi $19, 0x8000($19) ++ sll $19, 16 ++ ldi $19, 0x0000($19) ++ ifmovd $19, $f19 ++ ++run: ++ ldi $sp, -256($sp) ++ fcvtds $f17, $f20 ++ fsts $f20, 0($sp) ++ ldse $f1, 0($sp) ++ vadds $f1, $f1, $f2 /* 3.14 + 3.14 */ ++ vsts $f2, 0($sp) ++ ++sum_wrapper: ++ ldi $16, 0 ++ ldi $17, 0($sp) ++ ldi $23, 8 ++sum: ++ ldw $18, 0($17) ++ addw $16, $18 ++ subl $23, 1 ++ ldi $17, 4($17) ++ bne $23, sum ++ ++sum_end: ++ ldi $sp, 256($sp) ++ ldi $17, 52707176 ++ subl $16, $17 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/ldw-338.S b/none/tests/sw64-insn/ldw-338.S +new file mode 120000 +index 000000000..56a1155d1 +--- /dev/null ++++ b/none/tests/sw64-insn/ldw-338.S +@@ -0,0 +1 @@ ++stw-346.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/ldw_dec-23.S b/none/tests/sw64-insn/ldw_dec-23.S +new file mode 120000 +index 000000000..b9dc71db5 +--- /dev/null ++++ b/none/tests/sw64-insn/ldw_dec-23.S +@@ -0,0 +1 @@ ++ldw_inc-21.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/ldw_inc-21.S b/none/tests/sw64-insn/ldw_inc-21.S +new file mode 100644 +index 000000000..ff745ee3a +--- /dev/null ++++ b/none/tests/sw64-insn/ldw_inc-21.S +@@ -0,0 +1,17 @@ ++ ++ .global _start ++_start: ++ ldgp $29,0($27) ++ unop ++ ldi $sp, -16($sp) ++ ldi $17, 42 ++ stw $17, 0($sp) ++ #ldw_set $18, 0($sp) ++ #ldw_inc $19, 0($sp) ++ #ldw_dec $20, 0$($sp) ++ ldi $sp, 16($sp) ++ ldi $16, 0 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/ldw_nc-29.S b/none/tests/sw64-insn/ldw_nc-29.S +new file mode 100644 +index 000000000..884f708d8 +--- /dev/null ++++ b/none/tests/sw64-insn/ldw_nc-29.S +@@ -0,0 +1,16 @@ ++ ++ .global _start ++_start: ++ ldgp $29,0($27) ++ unop ++ ldi $sp, -16($sp) ++ ldi $17, 42 ++ stw_nc $17, 0($sp) ++ ldw_nc $18, 0($sp) ++ ldi $sp, 16($sp) ++ cmpeq $17, $18, $16 ++ subl $16, 1 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/ldw_set-25.S b/none/tests/sw64-insn/ldw_set-25.S +new file mode 120000 +index 000000000..b9dc71db5 +--- /dev/null ++++ b/none/tests/sw64-insn/ldw_set-25.S +@@ -0,0 +1 @@ ++ldw_inc-21.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/ldwe-35.S b/none/tests/sw64-insn/ldwe-35.S +new file mode 100644 +index 000000000..7b51203d7 +--- /dev/null ++++ b/none/tests/sw64-insn/ldwe-35.S +@@ -0,0 +1,29 @@ ++ ++ .global _start ++_start: ++ ldi $sp, -256($sp) ++ ldi $17, 2 ++ stl $17, 0($sp) ++ ldwe $f1, 0($sp) ++ vaddw $f1, $f1, $f2 /* 2 + 2 = 4 */ ++ vstw_u $f2, 0($sp) ++ ++sum_wrapper: ++ ldi $16, 0 ++ ldi $17, 0($sp) ++ ldi $23, 8 ++sum: ++ ldw $18, 0($17) ++ addw $16, $18 ++ subl $23, 1 ++ ldi $17, 4($17) ++ bne $23, sum ++ ++result: ++ ldi $sp, 256($sp) ++ subl $16, 32 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/lldl-20.S b/none/tests/sw64-insn/lldl-20.S +new file mode 100644 +index 000000000..2b589a3c2 +--- /dev/null ++++ b/none/tests/sw64-insn/lldl-20.S +@@ -0,0 +1,60 @@ ++ .text ++ ++ .globl xchg_u64 ++xchg_u64: ++ ldi $30,-64($30) ++ stl $26,0($30) ++ stl $15,8($30) ++ mov $30,$15 ++ stl $16,48($15) ++ stl $17,56($15) ++ ldl $5,48($15) ++ ldl $1,56($15) ++ ldl $2,48($15) ++ memb ++ ldi $6, 0($2) ++ ++f1: ++ lldl $4, 0($6) ++ ldi $3, 1 ++ wr_f $3 ++ bis $31, $1, $3 ++ memb ++ lstl $3, 0($6) ++ rd_f $3 ++ bne $3, f2 ++ br f1 ++ ++f2: ++ mov $6,$2 ++ stl $4,56($15) ++ stl $3,32($15) ++ stl $2,40($15) ++ ldl $1,56($15) ++ mov $1,$0 ++ mov $15,$30 ++ ldl $26,0($30) ++ ldl $15,8($30) ++ ldi $30,64($30) ++ ret $31,($26),1 ++ ++ .global _start ++_start: ++ br $29, 1f ++1: ldgp $29, 0($29) ++ subl $30, 16, $30 ++ mov 0, $15 ++ ++ ldi $sp, -16($sp) ++ ldi $17, 42 ++ stl $17, 0($sp) ++ ldi $16, 0($sp) ++ ldi $17, 43 ++ call $26, xchg_u64 ++ mov $0, $16 ++ subl $16, 42 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/lldw-19.S b/none/tests/sw64-insn/lldw-19.S +new file mode 100644 +index 000000000..1b1e2d823 +--- /dev/null ++++ b/none/tests/sw64-insn/lldw-19.S +@@ -0,0 +1,60 @@ ++ .text ++ ++ .globl xchg_u32 ++xchg_u32: ++ ldi $30,-64($30) ++ stl $26,0($30) ++ stl $15,8($30) ++ mov $30,$15 ++ stl $16,48($15) ++ stl $17,56($15) ++ ldl $5,48($15) ++ ldl $1,56($15) ++ ldl $2,48($15) ++ memb ++ ldi $6, 0($2) ++ ++f1: ++ lldw $4, 0($6) ++ ldi $3, 1 ++ wr_f $3 ++ bis $31, $1, $3 ++ memb ++ lstw $3, 0($6) ++ rd_f $3 ++ bne $3, f2 ++ br f1 ++ ++f2: ++ mov $6,$2 ++ stl $4,56($15) ++ stl $3,32($15) ++ stl $2,40($15) ++ ldl $1,56($15) ++ mov $1,$0 ++ mov $15,$30 ++ ldl $26,0($30) ++ ldl $15,8($30) ++ ldi $30,64($30) ++ ret $31,($26),1 ++ ++ .global _start ++_start: ++ br $29, 1f ++1: ldgp $29, 0($29) ++ subl $30, 16, $30 ++ mov 0, $15 ++ ++ ldi $sp, -16($sp) ++ ldi $17, 42 ++ stl $17, 0($sp) ++ ldi $16, 0($sp) ++ ldi $17, 43 ++ call $26, xchg_u32 ++ mov $0, $16 ++ subl $16, 42 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/lstl-28.S b/none/tests/sw64-insn/lstl-28.S +new file mode 100644 +index 000000000..bddd21c74 +--- /dev/null ++++ b/none/tests/sw64-insn/lstl-28.S +@@ -0,0 +1,60 @@ ++ .text ++ ++ .globl xchg_u64 ++xchg_u64: ++ ldi $30,-64($30) ++ stl $26,0($30) ++ stl $15,8($30) ++ mov $30,$15 ++ stl $16,48($15) ++ stl $17,56($15) ++ ldl $5,48($15) ++ ldl $1,56($15) ++ ldl $2,48($15) ++ memb ++ ldi $6, 0($2) ++ ++f1: ++ lldl $4, 0($6) ++ ldi $3, 1 ++ wr_f $3 ++ bis $31, $1, $3 ++ memb ++ lstl $3, 0($6) ++ rd_f $3 ++ bne $3, f2 ++ br f1 ++ ++f2: ++ mov $6,$2 ++ stl $4,56($15) ++ stl $3,32($15) ++ stl $2,40($15) ++ ldl $1,56($15) ++ mov $1,$0 ++ mov $15,$30 ++ ldl $26,0($30) ++ ldl $15,8($30) ++ ldi $30,64($30) ++ ret $31,($26),1 ++ ++ .global _start ++_start: ++ br $29, 1f ++1: ldgp $29, 0($29) ++ subl $30, 16, $30 ++ mov 0, $15 ++ ++ ldi $sp, -16($sp) ++ ldi $17, 42 ++ stl $17, 0($sp) ++ ldi $16, 0($sp) ++ ldi $17, 43 ++ call $26, xchg_u64 ++ mov $0, $16 ++ subl $16, 42 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/lstw-27.S b/none/tests/sw64-insn/lstw-27.S +new file mode 100644 +index 000000000..1b1e2d823 +--- /dev/null ++++ b/none/tests/sw64-insn/lstw-27.S +@@ -0,0 +1,60 @@ ++ .text ++ ++ .globl xchg_u32 ++xchg_u32: ++ ldi $30,-64($30) ++ stl $26,0($30) ++ stl $15,8($30) ++ mov $30,$15 ++ stl $16,48($15) ++ stl $17,56($15) ++ ldl $5,48($15) ++ ldl $1,56($15) ++ ldl $2,48($15) ++ memb ++ ldi $6, 0($2) ++ ++f1: ++ lldw $4, 0($6) ++ ldi $3, 1 ++ wr_f $3 ++ bis $31, $1, $3 ++ memb ++ lstw $3, 0($6) ++ rd_f $3 ++ bne $3, f2 ++ br f1 ++ ++f2: ++ mov $6,$2 ++ stl $4,56($15) ++ stl $3,32($15) ++ stl $2,40($15) ++ ldl $1,56($15) ++ mov $1,$0 ++ mov $15,$30 ++ ldl $26,0($30) ++ ldl $15,8($30) ++ ldi $30,64($30) ++ ret $31,($26),1 ++ ++ .global _start ++_start: ++ br $29, 1f ++1: ldgp $29, 0($29) ++ subl $30, 16, $30 ++ mov 0, $15 ++ ++ ldi $sp, -16($sp) ++ ldi $17, 42 ++ stl $17, 0($sp) ++ ldi $16, 0($sp) ++ ldi $17, 43 ++ call $26, xchg_u32 ++ mov $0, $16 ++ subl $16, 42 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/maskhb-94.S b/none/tests/sw64-insn/maskhb-94.S +new file mode 100644 +index 000000000..11d6643b0 +--- /dev/null ++++ b/none/tests/sw64-insn/maskhb-94.S +@@ -0,0 +1,13 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0xf0f1 ++ ldi $18, 1 ++ maskhb $17, $18, $16 ++ srl $16, 8, $16 ++ subl $16, 0xf0, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/maskhbi-162.S b/none/tests/sw64-insn/maskhbi-162.S +new file mode 100644 +index 000000000..df326d56c +--- /dev/null ++++ b/none/tests/sw64-insn/maskhbi-162.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0xf0f1 ++ maskhb $17, 1, $16 ++ srl $16, 8, $16 ++ subl $16, 0xf0, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/maskhh-95.S b/none/tests/sw64-insn/maskhh-95.S +new file mode 100644 +index 000000000..d7ed1bb71 +--- /dev/null ++++ b/none/tests/sw64-insn/maskhh-95.S +@@ -0,0 +1,13 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0xf0f1 ++ ldi $18, 1 ++ maskhh $17, $18, $16 ++ srl $16, 8, $16 ++ subl $16, 0xf0, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/maskhhi-163.S b/none/tests/sw64-insn/maskhhi-163.S +new file mode 100644 +index 000000000..b12dc6bd1 +--- /dev/null ++++ b/none/tests/sw64-insn/maskhhi-163.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0xf0f1 ++ maskhh $17, 1, $16 ++ srl $16, 8, $16 ++ subl $16, 0xf0, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/maskhl-97.S b/none/tests/sw64-insn/maskhl-97.S +new file mode 100644 +index 000000000..29d0243ce +--- /dev/null ++++ b/none/tests/sw64-insn/maskhl-97.S +@@ -0,0 +1,13 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0xf0f1 ++ ldi $18, 1 ++ maskhl $17, $18, $16 ++ cttz $16, $16 ++ subl $16, 12, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/maskhli-165.S b/none/tests/sw64-insn/maskhli-165.S +new file mode 100644 +index 000000000..86462f0ad +--- /dev/null ++++ b/none/tests/sw64-insn/maskhli-165.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0xf0f1 ++ maskhl $17, 1, $16 ++ cttz $16, $16 ++ subl $16, 12, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/maskhw-96.S b/none/tests/sw64-insn/maskhw-96.S +new file mode 100644 +index 000000000..1cbe62404 +--- /dev/null ++++ b/none/tests/sw64-insn/maskhw-96.S +@@ -0,0 +1,13 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0xf0f1 ++ ldi $18, 1 ++ maskhw $17, $18, $16 ++ srl $16, 8, $16 ++ subl $16, 0xf0, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/maskhwi-164.S b/none/tests/sw64-insn/maskhwi-164.S +new file mode 100644 +index 000000000..f9abb0e8b +--- /dev/null ++++ b/none/tests/sw64-insn/maskhwi-164.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0xf0f1 ++ maskhw $17, 1, $16 ++ srl $16, 8, $16 ++ subl $16, 0xf0, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/masklb-90.S b/none/tests/sw64-insn/masklb-90.S +new file mode 100644 +index 000000000..63c5da1eb +--- /dev/null ++++ b/none/tests/sw64-insn/masklb-90.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0xf0f1 ++ ldi $18, 1 ++ masklb $17, $18, $16 ++ subl $16, 0xf1, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/masklbi-158.S b/none/tests/sw64-insn/masklbi-158.S +new file mode 100644 +index 000000000..f6335a188 +--- /dev/null ++++ b/none/tests/sw64-insn/masklbi-158.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0xf0f1 ++ masklb $17, 1, $16 ++ subl $16, 0xf1, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/masklh-91.S b/none/tests/sw64-insn/masklh-91.S +new file mode 100644 +index 000000000..e8a80019a +--- /dev/null ++++ b/none/tests/sw64-insn/masklh-91.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0xf0f1 ++ ldi $18, 1 ++ masklh $17, $18, $16 ++ subl $16, 0xf1, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/masklhi-159.S b/none/tests/sw64-insn/masklhi-159.S +new file mode 100644 +index 000000000..9dfcb4329 +--- /dev/null ++++ b/none/tests/sw64-insn/masklhi-159.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0xf0f1 ++ masklh $17, 1, $16 ++ subl $16, 0xf1, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/maskll-93.S b/none/tests/sw64-insn/maskll-93.S +new file mode 100644 +index 000000000..8ccf02966 +--- /dev/null ++++ b/none/tests/sw64-insn/maskll-93.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0xf0f1 ++ ldi $18, 1 ++ maskll $17, $18, $16 ++ subl $16, 0xf1, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/masklli-161.S b/none/tests/sw64-insn/masklli-161.S +new file mode 100644 +index 000000000..141929444 +--- /dev/null ++++ b/none/tests/sw64-insn/masklli-161.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0xf0f1 ++ maskll $17, 1, $16 ++ subl $16, 0xf1, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/masklw-92.S b/none/tests/sw64-insn/masklw-92.S +new file mode 100644 +index 000000000..6d5657478 +--- /dev/null ++++ b/none/tests/sw64-insn/masklw-92.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0xf0f1 ++ ldi $18, 1 ++ masklw $17, $18, $16 ++ subl $16, 0xf1, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/masklwi-160.S b/none/tests/sw64-insn/masklwi-160.S +new file mode 100644 +index 000000000..869038a97 +--- /dev/null ++++ b/none/tests/sw64-insn/masklwi-160.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0xf0f1 ++ masklw $17, 1, $16 ++ subl $16, 0xf1, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/memb-8.S b/none/tests/sw64-insn/memb-8.S +new file mode 100644 +index 000000000..1b1e2d823 +--- /dev/null ++++ b/none/tests/sw64-insn/memb-8.S +@@ -0,0 +1,60 @@ ++ .text ++ ++ .globl xchg_u32 ++xchg_u32: ++ ldi $30,-64($30) ++ stl $26,0($30) ++ stl $15,8($30) ++ mov $30,$15 ++ stl $16,48($15) ++ stl $17,56($15) ++ ldl $5,48($15) ++ ldl $1,56($15) ++ ldl $2,48($15) ++ memb ++ ldi $6, 0($2) ++ ++f1: ++ lldw $4, 0($6) ++ ldi $3, 1 ++ wr_f $3 ++ bis $31, $1, $3 ++ memb ++ lstw $3, 0($6) ++ rd_f $3 ++ bne $3, f2 ++ br f1 ++ ++f2: ++ mov $6,$2 ++ stl $4,56($15) ++ stl $3,32($15) ++ stl $2,40($15) ++ ldl $1,56($15) ++ mov $1,$0 ++ mov $15,$30 ++ ldl $26,0($30) ++ ldl $15,8($30) ++ ldi $30,64($30) ++ ret $31,($26),1 ++ ++ .global _start ++_start: ++ br $29, 1f ++1: ldgp $29, 0($29) ++ subl $30, 16, $30 ++ mov 0, $15 ++ ++ ldi $sp, -16($sp) ++ ldi $17, 42 ++ stl $17, 0($sp) ++ ldi $16, 0($sp) ++ ldi $17, 43 ++ call $26, xchg_u32 ++ mov $0, $16 ++ subl $16, 42 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/mull-55.S b/none/tests/sw64-insn/mull-55.S +new file mode 100644 +index 000000000..e115b8ede +--- /dev/null ++++ b/none/tests/sw64-insn/mull-55.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 3 ++ ldi $18, 2 ++ mull $17, $18, $16 ++ subl $16, 6, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/mulli-126.S b/none/tests/sw64-insn/mulli-126.S +new file mode 100644 +index 000000000..5db44faca +--- /dev/null ++++ b/none/tests/sw64-insn/mulli-126.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 3 ++ mull $17, 2, $16 ++ subl $16, 6, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/mulw-54.S b/none/tests/sw64-insn/mulw-54.S +new file mode 100644 +index 000000000..0b62cdbec +--- /dev/null ++++ b/none/tests/sw64-insn/mulw-54.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 3 ++ ldi $18, 2 ++ mulw $17, $18, $16 ++ subw $16, 6, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/mulwi-125.S b/none/tests/sw64-insn/mulwi-125.S +new file mode 100644 +index 000000000..0649da3a1 +--- /dev/null ++++ b/none/tests/sw64-insn/mulwi-125.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 3 ++ mulw $17, 2, $16 ++ subw $16, 6, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/not-found-insn.S b/none/tests/sw64-insn/not-found-insn.S +new file mode 100644 +index 000000000..5db70971d +--- /dev/null ++++ b/none/tests/sw64-insn/not-found-insn.S +@@ -0,0 +1,74 @@ ++ ++ .global _start ++_start: ++ addwi $16 ++ subwi $16 ++ s4addwi $16 ++ s4subwi $16 ++ s8addwi $16 ++ s8subwi $16 ++ addli $16 ++ subli $16 ++ s4addli $16 ++ s4subli $16 ++ s8addli $16 ++ s8subli $16 ++ mulwi $16 ++ mulli $16 ++ umulhi $16 ++ cmpeqi $16 ++ cmplti $16 ++ cmplei $16 ++ cmpulti $16 ++ cmpulei $16 ++ andi $16 ++ bici $16 ++ bisi $16 ++ ornoti $16 ++ xori $16 ++ eqvi $16 ++ inslbi $16 ++ inslhi $16 ++ inslwi $16 ++ inslli $16 ++ inshbi $16 ++ inshhi $16 ++ inshwi $16 ++ inshli $16 ++ slli $16 ++ srli $16 ++ srai $16 ++ extlbi $16 ++ extlhi $16 ++ extlwi $16 ++ extlli $16 ++ exthbi $16 ++ exthhi $16 ++ exthwi $16 ++ exthli $16 ++ masklbi $16 ++ masklhi $16 ++ masklwi $16 ++ masklli $16 ++ maskhbi $16 ++ maskhhi $16 ++ maskhwi $16 ++ maskhli $16 ++ zapi $16 ++ zapnoti $16 ++ sextbi $16 ++ sexthi $16 ++ cmpgebi $16 ++ seleqi $16 ++ selgei $16 ++ selgti $16 ++ sellei $16 ++ sellti $16 ++ selnei $16 ++ sellbci $16 ++ sellbsi $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/ornot-65.S b/none/tests/sw64-insn/ornot-65.S +new file mode 100644 +index 000000000..fac47d9e7 +--- /dev/null ++++ b/none/tests/sw64-insn/ornot-65.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 2 ++ ldi $18, 1 ++ ornot $17, $18, $16 ++ addl $16, 2 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/ornoti-136.S b/none/tests/sw64-insn/ornoti-136.S +new file mode 100644 +index 000000000..fd558c0cb +--- /dev/null ++++ b/none/tests/sw64-insn/ornoti-136.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 2 ++ ornot $17, 1, $16 ++ addl $16, 2 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/pri_ld-341.S b/none/tests/sw64-insn/pri_ld-341.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/pri_ld-341.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/pri_rcsr-16.S b/none/tests/sw64-insn/pri_rcsr-16.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/pri_rcsr-16.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/pri_ret-18.S b/none/tests/sw64-insn/pri_ret-18.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/pri_ret-18.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/pri_st-349.S b/none/tests/sw64-insn/pri_st-349.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/pri_st-349.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/pri_wcsr-17.S b/none/tests/sw64-insn/pri_wcsr-17.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/pri_wcsr-17.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/rcid-11.S b/none/tests/sw64-insn/rcid-11.S +new file mode 100644 +index 000000000..45eb62638 +--- /dev/null ++++ b/none/tests/sw64-insn/rcid-11.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $16, 1($31) ++ rcid $16 ++ bgt $16, exit ++ ldi $16, 0($31) ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/rd_f-13.S b/none/tests/sw64-insn/rd_f-13.S +new file mode 100644 +index 000000000..1b1e2d823 +--- /dev/null ++++ b/none/tests/sw64-insn/rd_f-13.S +@@ -0,0 +1,60 @@ ++ .text ++ ++ .globl xchg_u32 ++xchg_u32: ++ ldi $30,-64($30) ++ stl $26,0($30) ++ stl $15,8($30) ++ mov $30,$15 ++ stl $16,48($15) ++ stl $17,56($15) ++ ldl $5,48($15) ++ ldl $1,56($15) ++ ldl $2,48($15) ++ memb ++ ldi $6, 0($2) ++ ++f1: ++ lldw $4, 0($6) ++ ldi $3, 1 ++ wr_f $3 ++ bis $31, $1, $3 ++ memb ++ lstw $3, 0($6) ++ rd_f $3 ++ bne $3, f2 ++ br f1 ++ ++f2: ++ mov $6,$2 ++ stl $4,56($15) ++ stl $3,32($15) ++ stl $2,40($15) ++ ldl $1,56($15) ++ mov $1,$0 ++ mov $15,$30 ++ ldl $26,0($30) ++ ldl $15,8($30) ++ ldi $30,64($30) ++ ret $31,($26),1 ++ ++ .global _start ++_start: ++ br $29, 1f ++1: ldgp $29, 0($29) ++ subl $30, 16, $30 ++ mov 0, $15 ++ ++ ldi $sp, -16($sp) ++ ldi $17, 42 ++ stl $17, 0($sp) ++ ldi $16, 0($sp) ++ ldi $17, 43 ++ call $26, xchg_u32 ++ mov $0, $16 ++ subl $16, 42 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/ret-4.S b/none/tests/sw64-insn/ret-4.S +new file mode 100644 +index 000000000..ff188d0d1 +--- /dev/null ++++ b/none/tests/sw64-insn/ret-4.S +@@ -0,0 +1,18 @@ ++ ++ .global _start ++_start: ++ br $29, 1f ++1: ldgp $29, 0($29) ++ subl $30, 16, $30 ++ mov 0, $15 ++ ++ ldi $16, 1 ++ call $26, noop ++ ldi $16, 0 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ ++noop: ++ ret $31, ($26), 0x1 +diff --git a/none/tests/sw64-insn/rfpcr-210.S b/none/tests/sw64-insn/rfpcr-210.S +new file mode 100644 +index 000000000..8ca9cb274 +--- /dev/null ++++ b/none/tests/sw64-insn/rfpcr-210.S +@@ -0,0 +1,31 @@ ++ .text ++ .global _start ++_start: ++ ++x1: ++ ldi $1, 0x00 ++ ifmovd $1, $f1 ++ ++x2: ++ ldi $2, 0x01 ++ ifmovd $2, $f2 ++ ++x3: ++ ldi $3, 0x02 ++ ifmovd $3, $f3 ++ ++x4: ++ ldi $4, 0x03 ++ ifmovd $4, $f4 ++ ++run: ++ wfpcr $f1 ++ rfpcr $f16 ++ fsubd $f16, $f1, $f17 ++ ldi $16, 0 ++ fbeq $f17, exit ++ ldi $16, 1 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/rtc-10.S b/none/tests/sw64-insn/rtc-10.S +new file mode 100644 +index 000000000..85e63a56e +--- /dev/null ++++ b/none/tests/sw64-insn/rtc-10.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $16, -1($31) ++ rtc $16 ++ blt $16, exit ++ ldi $16, 0($31) ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/rtid-15.S b/none/tests/sw64-insn/rtid-15.S +new file mode 100644 +index 000000000..52602263c +--- /dev/null ++++ b/none/tests/sw64-insn/rtid-15.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $16, -1($31) ++ rtid $16 ++ ble $16, exit ++ ldi $16, 0($31) ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/s4addl-50.S b/none/tests/sw64-insn/s4addl-50.S +new file mode 100644 +index 000000000..3ecdb5e04 +--- /dev/null ++++ b/none/tests/sw64-insn/s4addl-50.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 2 ++ ldi $18, 1 ++ s4addl $17, $18, $16 ++ subl $16, 9, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/s4addli-121.S b/none/tests/sw64-insn/s4addli-121.S +new file mode 100644 +index 000000000..6367420ad +--- /dev/null ++++ b/none/tests/sw64-insn/s4addli-121.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 2 ++ s4addl $17, 1, $16 ++ subl $16, 9, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/s4addw-44.S b/none/tests/sw64-insn/s4addw-44.S +new file mode 100644 +index 000000000..b99135a6a +--- /dev/null ++++ b/none/tests/sw64-insn/s4addw-44.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 2 ++ ldi $18, 1 ++ s4addw $17, $18, $16 ++ subw $16, 9, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/s4addwi-115.S b/none/tests/sw64-insn/s4addwi-115.S +new file mode 100644 +index 000000000..16983f88c +--- /dev/null ++++ b/none/tests/sw64-insn/s4addwi-115.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 2 ++ s4addw $17, 1, $16 ++ subw $16, 9, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/s4subl-51.S b/none/tests/sw64-insn/s4subl-51.S +new file mode 100644 +index 000000000..7d7ff2cea +--- /dev/null ++++ b/none/tests/sw64-insn/s4subl-51.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 2 ++ ldi $18, 1 ++ s4subl $17, $18, $16 ++ subl $16, 7, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/s4subli-122.S b/none/tests/sw64-insn/s4subli-122.S +new file mode 100644 +index 000000000..f5b9f60ce +--- /dev/null ++++ b/none/tests/sw64-insn/s4subli-122.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 2 ++ s4subl $17, 1, $16 ++ subl $16, 7, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/s4subw-45.S b/none/tests/sw64-insn/s4subw-45.S +new file mode 100644 +index 000000000..c25bc8d3c +--- /dev/null ++++ b/none/tests/sw64-insn/s4subw-45.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 2 ++ ldi $18, 1 ++ s4subw $17, $18, $16 ++ subw $16, 7, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/s4subwi-116.S b/none/tests/sw64-insn/s4subwi-116.S +new file mode 100644 +index 000000000..9b5097d1e +--- /dev/null ++++ b/none/tests/sw64-insn/s4subwi-116.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 2 ++ s4subw $17, 1, $16 ++ subw $16, 7, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/s8addl-52.S b/none/tests/sw64-insn/s8addl-52.S +new file mode 100644 +index 000000000..d913eac9e +--- /dev/null ++++ b/none/tests/sw64-insn/s8addl-52.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 2 ++ ldi $18, 1 ++ s8addl $17, $18, $16 ++ subl $16, 17, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/s8addli-123.S b/none/tests/sw64-insn/s8addli-123.S +new file mode 100644 +index 000000000..570661b98 +--- /dev/null ++++ b/none/tests/sw64-insn/s8addli-123.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 2 ++ s8addl $17, 1, $16 ++ subl $16, 17, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/s8addw-46.S b/none/tests/sw64-insn/s8addw-46.S +new file mode 100644 +index 000000000..0058af6cb +--- /dev/null ++++ b/none/tests/sw64-insn/s8addw-46.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 2 ++ ldi $18, 1 ++ s8addw $17, $18, $16 ++ subw $16, 17, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/s8addwi-117.S b/none/tests/sw64-insn/s8addwi-117.S +new file mode 100644 +index 000000000..f27423ebc +--- /dev/null ++++ b/none/tests/sw64-insn/s8addwi-117.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 2 ++ s8addw $17, 1, $16 ++ subw $16, 17, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/s8subl-53.S b/none/tests/sw64-insn/s8subl-53.S +new file mode 100644 +index 000000000..cbf56ec71 +--- /dev/null ++++ b/none/tests/sw64-insn/s8subl-53.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 2 ++ ldi $18, 1 ++ s8subl $17, $18, $16 ++ subl $16, 15, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/s8subli-124.S b/none/tests/sw64-insn/s8subli-124.S +new file mode 100644 +index 000000000..3c134f28d +--- /dev/null ++++ b/none/tests/sw64-insn/s8subli-124.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 2 ++ s8subl $17, 1, $16 ++ subl $16, 15, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/s8subw-47.S b/none/tests/sw64-insn/s8subw-47.S +new file mode 100644 +index 000000000..8d770798a +--- /dev/null ++++ b/none/tests/sw64-insn/s8subw-47.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 2 ++ ldi $18, 1 ++ s8subw $17, $18, $16 ++ subw $16, 15, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/s8subwi-118.S b/none/tests/sw64-insn/s8subwi-118.S +new file mode 100644 +index 000000000..929c3831c +--- /dev/null ++++ b/none/tests/sw64-insn/s8subwi-118.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 2 ++ s8subw $17, 1, $16 ++ subw $16, 15, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/seleq-105.S b/none/tests/sw64-insn/seleq-105.S +new file mode 100644 +index 000000000..8d12907e5 +--- /dev/null ++++ b/none/tests/sw64-insn/seleq-105.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 42 ++ ldi $18, 0 ++ ldi $19, 1 ++ seleq $17, $19, $18, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/seleqi-171.S b/none/tests/sw64-insn/seleqi-171.S +new file mode 100644 +index 000000000..338ac28f5 +--- /dev/null ++++ b/none/tests/sw64-insn/seleqi-171.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 42 ++ ldi $18, 0 ++ seleq $17, 1, $18, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/selge-106.S b/none/tests/sw64-insn/selge-106.S +new file mode 100644 +index 000000000..2ee09fa30 +--- /dev/null ++++ b/none/tests/sw64-insn/selge-106.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, -42 ++ ldi $18, 0 ++ ldi $19, 3 ++ selge $17, $19, $18, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/selgei-172.S b/none/tests/sw64-insn/selgei-172.S +new file mode 100644 +index 000000000..87c603595 +--- /dev/null ++++ b/none/tests/sw64-insn/selgei-172.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, -42 ++ ldi $18, 0 ++ selge $17, 3, $18, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/selgt-107.S b/none/tests/sw64-insn/selgt-107.S +new file mode 100644 +index 000000000..1619bf441 +--- /dev/null ++++ b/none/tests/sw64-insn/selgt-107.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, -42 ++ ldi $18, 0 ++ ldi $19, 3 ++ selgt $17, $19, $18, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/selgti-173.S b/none/tests/sw64-insn/selgti-173.S +new file mode 100644 +index 000000000..8fd00be70 +--- /dev/null ++++ b/none/tests/sw64-insn/selgti-173.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, -42 ++ ldi $18, 0 ++ selgt $17, 3, $18, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/sellbc-111.S b/none/tests/sw64-insn/sellbc-111.S +new file mode 100644 +index 000000000..978a670ee +--- /dev/null ++++ b/none/tests/sw64-insn/sellbc-111.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0b1001 ++ ldi $18, 0 ++ ldi $19, 1 ++ sellbc $17, $19, $18, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/sellbci-177.S b/none/tests/sw64-insn/sellbci-177.S +new file mode 100644 +index 000000000..1d87f0f5f +--- /dev/null ++++ b/none/tests/sw64-insn/sellbci-177.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0b1001 ++ ldi $18, 0 ++ sellbc $17, 1, $18, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/sellbs-112.S b/none/tests/sw64-insn/sellbs-112.S +new file mode 100644 +index 000000000..db3ff272c +--- /dev/null ++++ b/none/tests/sw64-insn/sellbs-112.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0b1010 ++ ldi $18, 0 ++ ldi $19, 1 ++ sellbs $17, $19, $18, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/sellbsi-178.S b/none/tests/sw64-insn/sellbsi-178.S +new file mode 100644 +index 000000000..0deb3746a +--- /dev/null ++++ b/none/tests/sw64-insn/sellbsi-178.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0b1010 ++ ldi $18, 0 ++ sellbs $17, 1, $18, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/selle-108.S b/none/tests/sw64-insn/selle-108.S +new file mode 100644 +index 000000000..58a0bebad +--- /dev/null ++++ b/none/tests/sw64-insn/selle-108.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 42 ++ ldi $18, 0 ++ ldi $19, 1 ++ selle $17, $19, $18, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/sellei-174.S b/none/tests/sw64-insn/sellei-174.S +new file mode 100644 +index 000000000..59bbe5c21 +--- /dev/null ++++ b/none/tests/sw64-insn/sellei-174.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 42 ++ ldi $18, 0 ++ selle $17, 1, $18, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/sellt-109.S b/none/tests/sw64-insn/sellt-109.S +new file mode 100644 +index 000000000..a4cb2a442 +--- /dev/null ++++ b/none/tests/sw64-insn/sellt-109.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 42 ++ ldi $18, 0 ++ ldi $19, 1 ++ sellt $17, $19, $18, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/sellti-175.S b/none/tests/sw64-insn/sellti-175.S +new file mode 100644 +index 000000000..08ae05d9f +--- /dev/null ++++ b/none/tests/sw64-insn/sellti-175.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 42 ++ ldi $18, 0 ++ sellt $17, 1, $18, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/selne-110.S b/none/tests/sw64-insn/selne-110.S +new file mode 100644 +index 000000000..0e616b131 +--- /dev/null ++++ b/none/tests/sw64-insn/selne-110.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0 ++ ldi $18, 0 ++ ldi $19, 1 ++ selne $17, $19, $18, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/selnei-176.S b/none/tests/sw64-insn/selnei-176.S +new file mode 100644 +index 000000000..9d14f0b6f +--- /dev/null ++++ b/none/tests/sw64-insn/selnei-176.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0 ++ ldi $18, 0 ++ selne $17, 1, $18, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/setfpec0-212.S b/none/tests/sw64-insn/setfpec0-212.S +new file mode 100644 +index 000000000..58cd7bd1d +--- /dev/null ++++ b/none/tests/sw64-insn/setfpec0-212.S +@@ -0,0 +1,30 @@ ++ .text ++ .global _start ++_start: ++ ++x1: ++ ldi $1, 0x00 ++ ifmovd $1, $f1 ++ ++x2: ++ ldi $2, 0x01 ++ ifmovd $2, $f2 ++ ++x3: ++ ldi $3, 0x02 ++ ifmovd $3, $f3 ++ ++x4: ++ ldi $4, 0x03 ++ ifmovd $4, $f4 ++ ++run: ++ wfpcr $f1 ++ setfpec0 ++ rfpcr $f16 ++ fimovd $f16, $16 ++ subl $16, $1 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/setfpec1-213.S b/none/tests/sw64-insn/setfpec1-213.S +new file mode 100644 +index 000000000..1c7252c7d +--- /dev/null ++++ b/none/tests/sw64-insn/setfpec1-213.S +@@ -0,0 +1,30 @@ ++ .text ++ .global _start ++_start: ++ ++x1: ++ ldi $1, 0x00 ++ ifmovd $1, $f1 ++ ++x2: ++ ldi $2, 0x01 ++ ifmovd $2, $f2 ++ ++x3: ++ ldi $3, 0x02 ++ ifmovd $3, $f3 ++ ++x4: ++ ldi $4, 0x03 ++ ifmovd $4, $f4 ++ ++run: ++ wfpcr $f1 ++ setfpec1 ++ rfpcr $f16 ++ fimovd $f16, $16 ++ subl $16, $2 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/setfpec2-214.S b/none/tests/sw64-insn/setfpec2-214.S +new file mode 100644 +index 000000000..c6bac4d1d +--- /dev/null ++++ b/none/tests/sw64-insn/setfpec2-214.S +@@ -0,0 +1,30 @@ ++ .text ++ .global _start ++_start: ++ ++x1: ++ ldi $1, 0x00 ++ ifmovd $1, $f1 ++ ++x2: ++ ldi $2, 0x01 ++ ifmovd $2, $f2 ++ ++x3: ++ ldi $3, 0x02 ++ ifmovd $3, $f3 ++ ++x4: ++ ldi $4, 0x03 ++ ifmovd $4, $f4 ++ ++run: ++ wfpcr $f1 ++ setfpec2 ++ rfpcr $f16 ++ fimovd $f16, $16 ++ subl $16, $3 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/setfpec3-215.S b/none/tests/sw64-insn/setfpec3-215.S +new file mode 100644 +index 000000000..ac089f2e1 +--- /dev/null ++++ b/none/tests/sw64-insn/setfpec3-215.S +@@ -0,0 +1,30 @@ ++ .text ++ .global _start ++_start: ++ ++x1: ++ ldi $1, 0x00 ++ ifmovd $1, $f1 ++ ++x2: ++ ldi $2, 0x01 ++ ifmovd $2, $f2 ++ ++x3: ++ ldi $3, 0x02 ++ ifmovd $3, $f3 ++ ++x4: ++ ldi $4, 0x03 ++ ifmovd $4, $f4 ++ ++run: ++ wfpcr $f1 ++ setfpec3 ++ rfpcr $f16 ++ fimovd $f16, $16 ++ subl $16, $4 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/sextb-100.S b/none/tests/sw64-insn/sextb-100.S +new file mode 100644 +index 000000000..06183ca83 +--- /dev/null ++++ b/none/tests/sw64-insn/sextb-100.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0xf1 ++ sextb $17, $16 ++ addl $16, 0xf, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/sextbi-168.S b/none/tests/sw64-insn/sextbi-168.S +new file mode 100644 +index 000000000..dff7b550f +--- /dev/null ++++ b/none/tests/sw64-insn/sextbi-168.S +@@ -0,0 +1,10 @@ ++ ++ .global _start ++_start: ++ sextb 0xf1, $16 ++ addl $16, 0xf, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/sexth-101.S b/none/tests/sw64-insn/sexth-101.S +new file mode 100644 +index 000000000..f8c386cfd +--- /dev/null ++++ b/none/tests/sw64-insn/sexth-101.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0xf1 ++ sexth $17, $16 ++ addl $16, 0xf, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/sexthi-169.S b/none/tests/sw64-insn/sexthi-169.S +new file mode 100644 +index 000000000..b7fbe57c1 +--- /dev/null ++++ b/none/tests/sw64-insn/sexthi-169.S +@@ -0,0 +1,10 @@ ++ ++ .global _start ++_start: ++ sexth 0xf1, $16 ++ addl $16, 0xf, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/sll-76.S b/none/tests/sw64-insn/sll-76.S +new file mode 100644 +index 000000000..3187a3b00 +--- /dev/null ++++ b/none/tests/sw64-insn/sll-76.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 2 ++ ldi $18, 2 ++ sll $17, $18, $16 ++ subl $16, 8 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/slli-147.S b/none/tests/sw64-insn/slli-147.S +new file mode 100644 +index 000000000..221575f7b +--- /dev/null ++++ b/none/tests/sw64-insn/slli-147.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 2 ++ sll $17, 2, $16 ++ subl $16, 8 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/sllow-242.S b/none/tests/sw64-insn/sllow-242.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/sllow-242.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/sllowi-266.S b/none/tests/sw64-insn/sllowi-266.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/sllowi-266.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/sra-78.S b/none/tests/sw64-insn/sra-78.S +new file mode 100644 +index 000000000..b9e2964a0 +--- /dev/null ++++ b/none/tests/sw64-insn/sra-78.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 4 ++ ldi $18, 1 ++ sra $17, $18, $16 ++ subl $16, 2 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/srai-149.S b/none/tests/sw64-insn/srai-149.S +new file mode 100644 +index 000000000..c10a4fe64 +--- /dev/null ++++ b/none/tests/sw64-insn/srai-149.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 4 ++ sra $17, 1, $16 ++ subl $16, 2 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/srl-77.S b/none/tests/sw64-insn/srl-77.S +new file mode 100644 +index 000000000..33b428fa8 +--- /dev/null ++++ b/none/tests/sw64-insn/srl-77.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 4 ++ ldi $18, 1 ++ srl $17, $18, $16 ++ subl $16, 2 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/srli-148.S b/none/tests/sw64-insn/srli-148.S +new file mode 100644 +index 000000000..f5407e823 +--- /dev/null ++++ b/none/tests/sw64-insn/srli-148.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 4 ++ srl $17, 1, $16 ++ subl $16, 2 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/srlow-243.S b/none/tests/sw64-insn/srlow-243.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/srlow-243.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/srlowi-267.S b/none/tests/sw64-insn/srlowi-267.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/srlowi-267.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/stb-344.S b/none/tests/sw64-insn/stb-344.S +new file mode 100644 +index 000000000..e00a35aa0 +--- /dev/null ++++ b/none/tests/sw64-insn/stb-344.S +@@ -0,0 +1,16 @@ ++ ++ .global _start ++_start: ++ ldi $30, -1($30) ++ ldi $16, 42($31) ++ bis $31, $16, $17 ++ stb $16, 0($30) ++ ldbu $16, 0($30) ++ xor $17, $16, $16 ++ ldi $30, 1($30) ++ ++exit: ++ ldi $0, 1 ++ #ldi $16, 0 # Set status code to 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/std_nc-34.S b/none/tests/sw64-insn/std_nc-34.S +new file mode 100644 +index 000000000..ed9b33f2d +--- /dev/null ++++ b/none/tests/sw64-insn/std_nc-34.S +@@ -0,0 +1,19 @@ ++ ++ .global _start ++_start: ++ ldgp $29,0($27) ++ unop ++ ldi $sp, -16($sp) ++ ldi $17, 42 ++ ifmovd $17, $f17 ++ std_nc $f17, 0($sp) ++ ldd_nc $f18, 0($sp) ++ ldi $sp, 16($sp) ++ fcmpeq $f17, $f18, $f16 ++ ldi $16, 0 ++ fbne $f16, exit ++ ldi $16, 1 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/sth-345.S b/none/tests/sw64-insn/sth-345.S +new file mode 100644 +index 000000000..1c6fb6605 +--- /dev/null ++++ b/none/tests/sw64-insn/sth-345.S +@@ -0,0 +1,16 @@ ++ ++ .global _start ++_start: ++ ldi $30, -2($30) ++ ldi $16, 8770($31) ++ bis $31, $16, $17 ++ sth $16, 0($30) ++ ldhu $16, 0($30) ++ xor $17, $16, $16 ++ ldi $30, 2($30) ++ ++exit: ++ ldi $0, 1 ++ #ldi $16, 0 # Set status code to 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/stl-347.S b/none/tests/sw64-insn/stl-347.S +new file mode 100644 +index 000000000..0868878a4 +--- /dev/null ++++ b/none/tests/sw64-insn/stl-347.S +@@ -0,0 +1,23 @@ ++ ++ .section .rodata ++$BIG: ++ .quad 1311768467284833366 ++ ++ .text ++ .global _start ++_start: ++ ldi $30, -8($30) ++ # ($16) = 0x1234567890123456 ++ ldih $16, $BIG($29) !gprelhigh ++ ldi $16, $BIG($16) !gprellow ++ bis $31, $16, $17 ++ stl $16, 0($30) ++ ldl $16, 0($30) ++ xor $17, $16, $16 ++ ldi $30, 8($30) ++ ++exit: ++ ldi $0, 1 ++ #ldi $16, 0 # Set status code to 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/stl_nc-33.S b/none/tests/sw64-insn/stl_nc-33.S +new file mode 100644 +index 000000000..d3b776276 +--- /dev/null ++++ b/none/tests/sw64-insn/stl_nc-33.S +@@ -0,0 +1,16 @@ ++ ++ .global _start ++_start: ++ ldgp $29,0($27) ++ unop ++ ldi $sp, -16($sp) ++ ldi $17, 42 ++ stl_nc $17, 0($sp) ++ ldl_nc $18, 0($sp) ++ ldi $sp, 16($sp) ++ cmpeq $17, $18, $16 ++ subl $16, 1 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/stl_u-348.S b/none/tests/sw64-insn/stl_u-348.S +new file mode 100644 +index 000000000..c2e5881e1 +--- /dev/null ++++ b/none/tests/sw64-insn/stl_u-348.S +@@ -0,0 +1,23 @@ ++ ++ .section .rodata ++$BIG: ++ .quad 1311768467284833366 ++ ++ .text ++ .global _start ++_start: ++ ldi $30, -8($30) ++ # ($16) = 0x1234567890123456 ++ ldih $16, $BIG($29) !gprelhigh ++ ldi $16, $BIG($16) !gprellow ++ bis $31, $16, $17 ++ stl_u $16, 0($30) ++ ldl_u $16, 0($30) ++ xor $17, $16, $16 ++ ldi $30, 8($30) ++ ++exit: ++ ldi $0, 1 ++ #ldi $16, 0 # Set status code to 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/stw-346.S b/none/tests/sw64-insn/stw-346.S +new file mode 100644 +index 000000000..f9548b481 +--- /dev/null ++++ b/none/tests/sw64-insn/stw-346.S +@@ -0,0 +1,18 @@ ++ ++ .global _start ++_start: ++ ldi $30, -4($30) ++ # ($16) = 4220421102 ++ ldih $16, -1137($31) ++ ldi $16, -31762($16) ++ bis $31, $16, $17 ++ stw $16, 0($30) ++ ldw $16, 0($30) ++ xor $17, $16, $16 ++ ldi $30, 4($30) ++ ++exit: ++ ldi $0, 1 ++ #ldi $16, 0 # Set status code to 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/stw_nc-32.S b/none/tests/sw64-insn/stw_nc-32.S +new file mode 100644 +index 000000000..884f708d8 +--- /dev/null ++++ b/none/tests/sw64-insn/stw_nc-32.S +@@ -0,0 +1,16 @@ ++ ++ .global _start ++_start: ++ ldgp $29,0($27) ++ unop ++ ldi $sp, -16($sp) ++ ldi $17, 42 ++ stw_nc $17, 0($sp) ++ ldw_nc $18, 0($sp) ++ ldi $sp, 16($sp) ++ cmpeq $17, $18, $16 ++ subl $16, 1 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/subl-49.S b/none/tests/sw64-insn/subl-49.S +new file mode 100644 +index 000000000..02ce4b332 +--- /dev/null ++++ b/none/tests/sw64-insn/subl-49.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 2 ++ ldi $18, 1 ++ subl $17, $18, $16 ++ subl $16, 1, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/subli-120.S b/none/tests/sw64-insn/subli-120.S +new file mode 100644 +index 000000000..6b8c38441 +--- /dev/null ++++ b/none/tests/sw64-insn/subli-120.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 2 ++ subl $17, 1, $16 ++ subl $16, 1, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/subw-43.S b/none/tests/sw64-insn/subw-43.S +new file mode 100644 +index 000000000..b6ceaa78a +--- /dev/null ++++ b/none/tests/sw64-insn/subw-43.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 2 ++ ldi $18, 1 ++ subw $17, $18, $16 ++ subw $16, 1, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/subwi-114.S b/none/tests/sw64-insn/subwi-114.S +new file mode 100644 +index 000000000..8d4a0ea7f +--- /dev/null ++++ b/none/tests/sw64-insn/subwi-114.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 2 ++ subw $17, 1, $16 ++ subw $16, 1, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/sys_call-2.S b/none/tests/sw64-insn/sys_call-2.S +new file mode 100644 +index 000000000..f3ef0909d +--- /dev/null ++++ b/none/tests/sw64-insn/sys_call-2.S +@@ -0,0 +1,10 @@ ++ ++ .global _start ++_start: ++ unop ++ ++exit: ++ ldi $0, 1 ++ ldi $16, 0 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/sys_call_b-1.S b/none/tests/sw64-insn/sys_call_b-1.S +new file mode 100644 +index 000000000..2f1d96c7a +--- /dev/null ++++ b/none/tests/sw64-insn/sys_call_b-1.S +@@ -0,0 +1,10 @@ ++ ++ .global _start ++_start: ++ unop ++ ++exit: ++ ldi $0, 1 ++ ldi $16, 0 ++ sys_call/b 0x83 ++ +diff --git a/none/tests/sw64-insn/test-all.sh b/none/tests/sw64-insn/test-all.sh +new file mode 100755 +index 000000000..0acdb1181 +--- /dev/null ++++ b/none/tests/sw64-insn/test-all.sh +@@ -0,0 +1,31 @@ ++#!/bin/bash ++ ++# Colors ++readonly RED='\033[0;31m' ++readonly GREEN='\033[0;32m' ++readonly NC='\033[0m' # No Color ++ ++readonly OK_FILE=ok.log ++readonly FAILED_FILE=failed.log ++readonly TOOL=none ++ ++ ++> ${OK_FILE} ++> ${FAILED_FILE} ++ ++readonly INSN_LIST=$(dirname "${BASH_SOURCE[0]}")/insn-list ++echo "INSN_LIST: ${INSN_LIST}" ++ ++for target in $(cat ${INSN_LIST}); do ++ echo -n "Run ${target}" ++ sh -c "../../../vg-in-place --log-file=${target}.log --tool=${TOOL} ./${target}" ++ if [ x$? == x0 ]; then ++ echo -e " ${GREEN}OK${NC}" ++ echo "OK" >> ${target}.log ++ echo ${target} >> ${OK_FILE} ++ else ++ echo -e " ${RED}FAILED${NC}" ++ echo "FAILED" >> ${target}.log ++ echo ${target} >> ${FAILED_FILE} ++ fi ++done +diff --git a/none/tests/sw64-insn/test-basic.sh b/none/tests/sw64-insn/test-basic.sh +new file mode 100755 +index 000000000..96465cbfc +--- /dev/null ++++ b/none/tests/sw64-insn/test-basic.sh +@@ -0,0 +1,31 @@ ++#!/bin/bash ++ ++# Colors ++readonly RED='\033[0;31m' ++readonly GREEN='\033[0;32m' ++readonly NC='\033[0m' # No Color ++ ++readonly OK_FILE=basicok.log ++readonly FAILED_FILE=basic-failed.log ++readonly TOOL=none ++ ++ ++> ${OK_FILE} ++> ${FAILED_FILE} ++ ++readonly INSN_LIST=$(dirname "${BASH_SOURCE[0]}")/basic-insn-list ++echo "INSN_LIST: ${INSN_LIST}" ++ ++for target in $(cat ${INSN_LIST}); do ++ echo -n "Run ${target}" ++ sh -c "../../../vg-in-place --log-file=${target}.log --tool=${TOOL} ./${target}" ++ if [ x$? == x0 ]; then ++ echo -e " ${GREEN}OK${NC}" ++ echo "OK" >> ${target}.log ++ echo ${target} >> ${OK_FILE} ++ else ++ echo -e " ${RED}FAILED${NC}" ++ echo "FAILED" >> ${target}.log ++ echo ${target} >> ${FAILED_FILE} ++ fi ++done +diff --git a/none/tests/sw64-insn/tmp.S b/none/tests/sw64-insn/tmp.S +new file mode 100644 +index 000000000..d66621dfb +--- /dev/null ++++ b/none/tests/sw64-insn/tmp.S +@@ -0,0 +1,10 @@ ++ ++ .global _start ++_start: ++ nop ++ ++exit: ++ ldi $0, 1 ++ ldi $16, 1 # Set status code to 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/umulh-56.S b/none/tests/sw64-insn/umulh-56.S +new file mode 100644 +index 000000000..b9a3fc3be +--- /dev/null ++++ b/none/tests/sw64-insn/umulh-56.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 3 ++ ldi $18, 2 ++ umulh $17, $18, $16 # higher 64 part is 0 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/umulhi-127.S b/none/tests/sw64-insn/umulhi-127.S +new file mode 100644 +index 000000000..df9817648 +--- /dev/null ++++ b/none/tests/sw64-insn/umulhi-127.S +@@ -0,0 +1,10 @@ ++ ++ .global _start ++_start: ++ ldi $17, 3 ++ umulh $17, 2, $16 # higher 64 part is 0 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/vaddd-277.S b/none/tests/sw64-insn/vaddd-277.S +new file mode 100644 +index 000000000..584bf54ac +--- /dev/null ++++ b/none/tests/sw64-insn/vaddd-277.S +@@ -0,0 +1,52 @@ ++ ++ .global _start ++_start: ++x1: ++ /* 3.1415926 = 0x400921fb4d12d84a */ ++ ldi $17, 0x400921fb ++ sll $17, 32 ++ ldi $17, 0x4d12d84a($17) ++ ifmovd $17, $f17 ++ ++x2: ++ /* 0.0 */ ++ ldi $18, 0x0 ++ ifmovd $18, $f18 ++ ++result: ++ /* 25.132740800000001 = 0x4039 21fb 4d12 d84a */ ++ ldi $19, 0x403921fb ++ sll $19, 16 ++ ldi $19, 0x4d12($19) ++ sll $19, 16 ++ ldi $19, 0xd84a($19) ++ ifmovd $19, $f19 ++ ++run: ++ ldi $sp, -256($sp) ++ fstd $f17, 0($sp) ++ ldde $f1, 0($sp) ++ vaddd $f1, $f1, $f2 /* 3.14 + 3.14 */ ++ vstd $f2, 0($sp) ++ ++sum_wrapper: ++ ldi $17, 0($sp) ++ ldi $23, 4 ++sum: ++ fldd $f2, 0($17) ++ faddd $f18, $f2 ++ subl $23, 1 ++ ldi $17, 8($17) ++ bne $23, sum ++ ++sum_end: ++ ldi $sp, 256($sp) ++ fcmpeq $f18, $f19, $f16 ++ ldi $16, 1 ++ fbeq $f16, exit ++ ldi $16, 0 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/vaddl-244.S b/none/tests/sw64-insn/vaddl-244.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vaddl-244.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vaddli-268.S b/none/tests/sw64-insn/vaddli-268.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vaddli-268.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vadds-276.S b/none/tests/sw64-insn/vadds-276.S +new file mode 120000 +index 000000000..339c4856d +--- /dev/null ++++ b/none/tests/sw64-insn/vadds-276.S +@@ -0,0 +1 @@ ++ldse-36.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vaddw-230.S b/none/tests/sw64-insn/vaddw-230.S +new file mode 120000 +index 000000000..b03fca413 +--- /dev/null ++++ b/none/tests/sw64-insn/vaddw-230.S +@@ -0,0 +1 @@ ++ldwe-35.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vaddwi-254.S b/none/tests/sw64-insn/vaddwi-254.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vaddwi-254.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vcmpeqw-233.S b/none/tests/sw64-insn/vcmpeqw-233.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vcmpeqw-233.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vcmpeqwi-257.S b/none/tests/sw64-insn/vcmpeqwi-257.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vcmpeqwi-257.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vcmpgew-232.S b/none/tests/sw64-insn/vcmpgew-232.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vcmpgew-232.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vcmpgewi-256.S b/none/tests/sw64-insn/vcmpgewi-256.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vcmpgewi-256.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vcmplew-234.S b/none/tests/sw64-insn/vcmplew-234.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vcmplew-234.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vcmplewi-258.S b/none/tests/sw64-insn/vcmplewi-258.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vcmplewi-258.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vcmpltw-235.S b/none/tests/sw64-insn/vcmpltw-235.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vcmpltw-235.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vcmpltwi-259.S b/none/tests/sw64-insn/vcmpltwi-259.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vcmpltwi-259.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vcmpulew-236.S b/none/tests/sw64-insn/vcmpulew-236.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vcmpulew-236.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vcmpulewi-260.S b/none/tests/sw64-insn/vcmpulewi-260.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vcmpulewi-260.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vcmpultw-237.S b/none/tests/sw64-insn/vcmpultw-237.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vcmpultw-237.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vcmpultwi-261.S b/none/tests/sw64-insn/vcmpultwi-261.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vcmpultwi-261.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vcond-317.S b/none/tests/sw64-insn/vcond-317.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vcond-317.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vcons-316.S b/none/tests/sw64-insn/vcons-316.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vcons-316.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vconw-314.S b/none/tests/sw64-insn/vconw-314.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vconw-314.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vcpyf-313.S b/none/tests/sw64-insn/vcpyf-313.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vcpyf-313.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vcpys-290.S b/none/tests/sw64-insn/vcpys-290.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vcpys-290.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vcpyse-291.S b/none/tests/sw64-insn/vcpyse-291.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vcpyse-291.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vcpysn-292.S b/none/tests/sw64-insn/vcpysn-292.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vcpysn-292.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vcpyw-312.S b/none/tests/sw64-insn/vcpyw-312.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vcpyw-312.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vdivd-283.S b/none/tests/sw64-insn/vdivd-283.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vdivd-283.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vdivs-282.S b/none/tests/sw64-insn/vdivs-282.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vdivs-282.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vextf-311.S b/none/tests/sw64-insn/vextf-311.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vextf-311.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vextw-310.S b/none/tests/sw64-insn/vextw-310.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vextw-310.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vfcmpeq-286.S b/none/tests/sw64-insn/vfcmpeq-286.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vfcmpeq-286.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vfcmple-287.S b/none/tests/sw64-insn/vfcmple-287.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vfcmple-287.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vfcmplt-288.S b/none/tests/sw64-insn/vfcmplt-288.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vfcmplt-288.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vfcmpun-289.S b/none/tests/sw64-insn/vfcmpun-289.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vfcmpun-289.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vfseleq-301.S b/none/tests/sw64-insn/vfseleq-301.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vfseleq-301.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vfselle-303.S b/none/tests/sw64-insn/vfselle-303.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vfselle-303.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vfsellt-302.S b/none/tests/sw64-insn/vfsellt-302.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vfsellt-302.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vinsf-309.S b/none/tests/sw64-insn/vinsf-309.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vinsf-309.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vinsw-308.S b/none/tests/sw64-insn/vinsw-308.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vinsw-308.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vldd-39.S b/none/tests/sw64-insn/vldd-39.S +new file mode 100644 +index 000000000..f6736a240 +--- /dev/null ++++ b/none/tests/sw64-insn/vldd-39.S +@@ -0,0 +1,52 @@ ++ ++ .global _start ++_start: ++x1: ++ /* 3.1415926 = 0x400921fb4d12d84a */ ++ ldi $17, 0x400921fb ++ sll $17, 32 ++ ldi $17, 0x4d12d84a($17) ++ ifmovd $17, $f17 ++ ++x2: ++ /* 0.0 */ ++ ldi $18, 0x0 ++ ifmovd $18, $f18 ++ ++result: ++ /* 6.2831852000000001 = 0x4019 21fb 4d12 d84a */ ++ ldi $19, 0x401921fb ++ sll $19, 16 ++ ldi $19, 0x4d12($19) ++ sll $19, 16 ++ ldi $19, 0xd84a($19) ++ ifmovd $19, $f19 ++ ++run: ++ ldi $sp, -256($sp) ++ fstd $f17, 0($sp) ++ vldd $f1, 0($sp) ++ vaddd $f1, $f1, $f2 /* 3.14 + 3.14 */ ++ vstd $f2, 0($sp) ++ ++sum_wrapper: ++ ldi $17, 0($sp) ++ ldi $23, 4 ++sum: ++ fldd $f2, 0($17) ++ faddd $f18, $f2 ++ subl $23, 1 ++ ldi $17, 8($17) ++ bne $23, sum ++ ++sum_end: ++ ldi $sp, 256($sp) ++ fcmpeq $f18, $f19, $f16 ++ ldi $16, 1 ++ fbeq $f16, exit ++ ldi $16, 0 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/vldd_nc-334.S b/none/tests/sw64-insn/vldd_nc-334.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vldd_nc-334.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vldd_u-326.S b/none/tests/sw64-insn/vldd_u-326.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vldd_u-326.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vlds-38.S b/none/tests/sw64-insn/vlds-38.S +new file mode 100644 +index 000000000..7c4654ae9 +--- /dev/null ++++ b/none/tests/sw64-insn/vlds-38.S +@@ -0,0 +1,53 @@ ++ ++ .global _start ++_start: ++x1: ++ /* 3.1415926 = 0x400921fb4d12d84a */ ++ ldi $17, 0x400921fb ++ sll $17, 32 ++ ldi $17, 0x4d12d84a($17) ++ ifmovd $17, $f17 ++ ++x2: ++ /* 0.0 */ ++ ldi $18, 0x0 ++ ifmovd $18, $f18 ++ ++result: ++ /* 6.2831850051879883 = 0x4019 21fb 4000 0000 */ ++ ldi $19, 0x401921fb ++ sll $19, 16 ++ ldi $19, 0x4000($19) ++ sll $19, 16 ++ ldi $19, 0x0000($19) ++ ifmovd $19, $f19 ++ ++run: ++ ldi $sp, -256($sp) ++ fcvtds $f17, $f20 ++ fsts $f20, 0($sp) ++ vlds $f1, 0($sp) ++ vadds $f1, $f1, $f2 /* 3.14 + 3.14 */ ++ vsts $f2, 0($sp) ++ ++sum_wrapper: ++ ldi $17, 0($sp) ++ ldi $23, 4 ++sum: ++ flds $f2, 0($17) ++ fadds $f18, $f2 ++ subl $23, 1 ++ ldi $17, 8($17) ++ bne $23, sum ++ ++sum_end: ++ ldi $sp, 256($sp) ++ fcmpeq $f18, $f19, $f16 ++ ldi $16, 1 ++ fbeq $f16, exit ++ ldi $16, 0 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/vlds_u-324.S b/none/tests/sw64-insn/vlds_u-324.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vlds_u-324.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vldw_u-322.S b/none/tests/sw64-insn/vldw_u-322.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vldw_u-322.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vlogzz-179.S b/none/tests/sw64-insn/vlogzz-179.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vlogzz-179.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vmad-294.S b/none/tests/sw64-insn/vmad-294.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vmad-294.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vmas-293.S b/none/tests/sw64-insn/vmas-293.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vmas-293.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vmsd-296.S b/none/tests/sw64-insn/vmsd-296.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vmsd-296.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vmss-295.S b/none/tests/sw64-insn/vmss-295.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vmss-295.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vmuld-281.S b/none/tests/sw64-insn/vmuld-281.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vmuld-281.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vmuls-280.S b/none/tests/sw64-insn/vmuls-280.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vmuls-280.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vnmad-298.S b/none/tests/sw64-insn/vnmad-298.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vnmad-298.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vnmas-297.S b/none/tests/sw64-insn/vnmas-297.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vnmas-297.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vnmsd-300.S b/none/tests/sw64-insn/vnmsd-300.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vnmsd-300.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vnmss-299.S b/none/tests/sw64-insn/vnmss-299.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vnmss-299.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vrolw-241.S b/none/tests/sw64-insn/vrolw-241.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vrolw-241.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vrolwi-265.S b/none/tests/sw64-insn/vrolwi-265.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vrolwi-265.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vseleqw-304.S b/none/tests/sw64-insn/vseleqw-304.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vseleqw-304.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vseleqwi-318.S b/none/tests/sw64-insn/vseleqwi-318.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vseleqwi-318.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vsellbcw-305.S b/none/tests/sw64-insn/vsellbcw-305.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vsellbcw-305.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vsellbcwi-319.S b/none/tests/sw64-insn/vsellbcwi-319.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vsellbcwi-319.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vsellew-307.S b/none/tests/sw64-insn/vsellew-307.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vsellew-307.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vsellewi-321.S b/none/tests/sw64-insn/vsellewi-321.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vsellewi-321.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vselltw-306.S b/none/tests/sw64-insn/vselltw-306.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vselltw-306.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vselltwi-320.S b/none/tests/sw64-insn/vselltwi-320.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vselltwi-320.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vshfw-315.S b/none/tests/sw64-insn/vshfw-315.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vshfw-315.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vsllw-238.S b/none/tests/sw64-insn/vsllw-238.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vsllw-238.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vsllwi-262.S b/none/tests/sw64-insn/vsllwi-262.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vsllwi-262.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vsqrtd-285.S b/none/tests/sw64-insn/vsqrtd-285.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vsqrtd-285.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vsqrts-284.S b/none/tests/sw64-insn/vsqrts-284.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vsqrts-284.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vsraw-240.S b/none/tests/sw64-insn/vsraw-240.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vsraw-240.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vsrawi-264.S b/none/tests/sw64-insn/vsrawi-264.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vsrawi-264.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vsrlw-239.S b/none/tests/sw64-insn/vsrlw-239.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vsrlw-239.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vsrlwi-263.S b/none/tests/sw64-insn/vsrlwi-263.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vsrlwi-263.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vstd-41.S b/none/tests/sw64-insn/vstd-41.S +new file mode 100644 +index 000000000..584bf54ac +--- /dev/null ++++ b/none/tests/sw64-insn/vstd-41.S +@@ -0,0 +1,52 @@ ++ ++ .global _start ++_start: ++x1: ++ /* 3.1415926 = 0x400921fb4d12d84a */ ++ ldi $17, 0x400921fb ++ sll $17, 32 ++ ldi $17, 0x4d12d84a($17) ++ ifmovd $17, $f17 ++ ++x2: ++ /* 0.0 */ ++ ldi $18, 0x0 ++ ifmovd $18, $f18 ++ ++result: ++ /* 25.132740800000001 = 0x4039 21fb 4d12 d84a */ ++ ldi $19, 0x403921fb ++ sll $19, 16 ++ ldi $19, 0x4d12($19) ++ sll $19, 16 ++ ldi $19, 0xd84a($19) ++ ifmovd $19, $f19 ++ ++run: ++ ldi $sp, -256($sp) ++ fstd $f17, 0($sp) ++ ldde $f1, 0($sp) ++ vaddd $f1, $f1, $f2 /* 3.14 + 3.14 */ ++ vstd $f2, 0($sp) ++ ++sum_wrapper: ++ ldi $17, 0($sp) ++ ldi $23, 4 ++sum: ++ fldd $f2, 0($17) ++ faddd $f18, $f2 ++ subl $23, 1 ++ ldi $17, 8($17) ++ bne $23, sum ++ ++sum_end: ++ ldi $sp, 256($sp) ++ fcmpeq $f18, $f19, $f16 ++ ldi $16, 1 ++ fbeq $f16, exit ++ ldi $16, 0 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/vstd_nc-335.S b/none/tests/sw64-insn/vstd_nc-335.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vstd_nc-335.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vstd_u-327.S b/none/tests/sw64-insn/vstd_u-327.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vstd_u-327.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vstd_uh-333.S b/none/tests/sw64-insn/vstd_uh-333.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vstd_uh-333.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vstd_ul-332.S b/none/tests/sw64-insn/vstd_ul-332.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vstd_ul-332.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vsts-40.S b/none/tests/sw64-insn/vsts-40.S +new file mode 120000 +index 000000000..339c4856d +--- /dev/null ++++ b/none/tests/sw64-insn/vsts-40.S +@@ -0,0 +1 @@ ++ldse-36.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vsts_u-325.S b/none/tests/sw64-insn/vsts_u-325.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vsts_u-325.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vsts_uh-331.S b/none/tests/sw64-insn/vsts_uh-331.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vsts_uh-331.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vsts_ul-330.S b/none/tests/sw64-insn/vsts_ul-330.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vsts_ul-330.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vstw_u-323.S b/none/tests/sw64-insn/vstw_u-323.S +new file mode 120000 +index 000000000..b03fca413 +--- /dev/null ++++ b/none/tests/sw64-insn/vstw_u-323.S +@@ -0,0 +1 @@ ++ldwe-35.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vstw_uh-329.S b/none/tests/sw64-insn/vstw_uh-329.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vstw_uh-329.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vstw_ul-328.S b/none/tests/sw64-insn/vstw_ul-328.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vstw_ul-328.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vsubd-279.S b/none/tests/sw64-insn/vsubd-279.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vsubd-279.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vsubl-245.S b/none/tests/sw64-insn/vsubl-245.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vsubl-245.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vsubli-269.S b/none/tests/sw64-insn/vsubli-269.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vsubli-269.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vsubs-278.S b/none/tests/sw64-insn/vsubs-278.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vsubs-278.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vsubw-231.S b/none/tests/sw64-insn/vsubw-231.S +new file mode 100644 +index 000000000..40ecdd2c1 +--- /dev/null ++++ b/none/tests/sw64-insn/vsubw-231.S +@@ -0,0 +1,28 @@ ++ ++ .global _start ++_start: ++ ldi $sp, -256($sp) ++ ldi $17, 2 ++ stl $17, 0($sp) ++ ldwe $f1, 0($sp) ++ vsubw $f1, $f1, $f2 /* 2 - 2 = 0 */ ++ vstw_u $f2, 0($sp) ++ ++sum_wrapper: ++ ldi $16, 0 ++ ldi $17, 0($sp) ++ ldi $23, 8 ++sum: ++ ldw $18, 0($17) ++ addw $16, $18 ++ subl $23, 1 ++ ldi $17, 4($17) ++ bne $23, sum ++ ++result: ++ ldi $sp, 256($sp) ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/vsubwi-255.S b/none/tests/sw64-insn/vsubwi-255.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vsubwi-255.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vucaddb-252.S b/none/tests/sw64-insn/vucaddb-252.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vucaddb-252.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vucaddbi-274.S b/none/tests/sw64-insn/vucaddbi-274.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vucaddbi-274.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vucaddh-250.S b/none/tests/sw64-insn/vucaddh-250.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vucaddh-250.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vucaddhi-272.S b/none/tests/sw64-insn/vucaddhi-272.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vucaddhi-272.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vucaddw-248.S b/none/tests/sw64-insn/vucaddw-248.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vucaddw-248.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vucaddwi-270.S b/none/tests/sw64-insn/vucaddwi-270.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vucaddwi-270.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vucsubb-253.S b/none/tests/sw64-insn/vucsubb-253.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vucsubb-253.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vucsubbi-275.S b/none/tests/sw64-insn/vucsubbi-275.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vucsubbi-275.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vucsubh-251.S b/none/tests/sw64-insn/vucsubh-251.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vucsubh-251.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vucsubhi-273.S b/none/tests/sw64-insn/vucsubhi-273.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vucsubhi-273.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vucsubw-249.S b/none/tests/sw64-insn/vucsubw-249.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vucsubw-249.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/vucsubwi-271.S b/none/tests/sw64-insn/vucsubwi-271.S +new file mode 120000 +index 000000000..9fa5b2a7a +--- /dev/null ++++ b/none/tests/sw64-insn/vucsubwi-271.S +@@ -0,0 +1 @@ ++tmp.S +\ No newline at end of file +diff --git a/none/tests/sw64-insn/wfpcr-211.S b/none/tests/sw64-insn/wfpcr-211.S +new file mode 100644 +index 000000000..8ca9cb274 +--- /dev/null ++++ b/none/tests/sw64-insn/wfpcr-211.S +@@ -0,0 +1,31 @@ ++ .text ++ .global _start ++_start: ++ ++x1: ++ ldi $1, 0x00 ++ ifmovd $1, $f1 ++ ++x2: ++ ldi $2, 0x01 ++ ifmovd $2, $f2 ++ ++x3: ++ ldi $3, 0x02 ++ ifmovd $3, $f3 ++ ++x4: ++ ldi $4, 0x03 ++ ifmovd $4, $f4 ++ ++run: ++ wfpcr $f1 ++ rfpcr $f16 ++ fsubd $f16, $f1, $f17 ++ ldi $16, 0 ++ fbeq $f17, exit ++ ldi $16, 1 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 +diff --git a/none/tests/sw64-insn/wr_f-14.S b/none/tests/sw64-insn/wr_f-14.S +new file mode 100644 +index 000000000..1b1e2d823 +--- /dev/null ++++ b/none/tests/sw64-insn/wr_f-14.S +@@ -0,0 +1,60 @@ ++ .text ++ ++ .globl xchg_u32 ++xchg_u32: ++ ldi $30,-64($30) ++ stl $26,0($30) ++ stl $15,8($30) ++ mov $30,$15 ++ stl $16,48($15) ++ stl $17,56($15) ++ ldl $5,48($15) ++ ldl $1,56($15) ++ ldl $2,48($15) ++ memb ++ ldi $6, 0($2) ++ ++f1: ++ lldw $4, 0($6) ++ ldi $3, 1 ++ wr_f $3 ++ bis $31, $1, $3 ++ memb ++ lstw $3, 0($6) ++ rd_f $3 ++ bne $3, f2 ++ br f1 ++ ++f2: ++ mov $6,$2 ++ stl $4,56($15) ++ stl $3,32($15) ++ stl $2,40($15) ++ ldl $1,56($15) ++ mov $1,$0 ++ mov $15,$30 ++ ldl $26,0($30) ++ ldl $15,8($30) ++ ldi $30,64($30) ++ ret $31,($26),1 ++ ++ .global _start ++_start: ++ br $29, 1f ++1: ldgp $29, 0($29) ++ subl $30, 16, $30 ++ mov 0, $15 ++ ++ ldi $sp, -16($sp) ++ ldi $17, 42 ++ stl $17, 0($sp) ++ ldi $16, 0($sp) ++ ldi $17, 43 ++ call $26, xchg_u32 ++ mov $0, $16 ++ subl $16, 42 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/xor-66.S b/none/tests/sw64-insn/xor-66.S +new file mode 100644 +index 000000000..751c9374b +--- /dev/null ++++ b/none/tests/sw64-insn/xor-66.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 2 ++ ldi $18, 1 ++ xor $17, $18, $16 ++ subl $16, 3 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/xori-137.S b/none/tests/sw64-insn/xori-137.S +new file mode 100644 +index 000000000..4942a3bdc +--- /dev/null ++++ b/none/tests/sw64-insn/xori-137.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 2 ++ xor $17, 1, $16 ++ subl $16, 3 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/zap-98.S b/none/tests/sw64-insn/zap-98.S +new file mode 100644 +index 000000000..00efadfe5 +--- /dev/null ++++ b/none/tests/sw64-insn/zap-98.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0xf0f1 ++ ldi $18, 0b1110 ++ zap $17, $18, $16 ++ subl $16, 0xf1, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/zapi-166.S b/none/tests/sw64-insn/zapi-166.S +new file mode 100644 +index 000000000..1faf8cbdf +--- /dev/null ++++ b/none/tests/sw64-insn/zapi-166.S +@@ -0,0 +1,11 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0xf0f1 ++ zap $17, 0b1110, $16 ++ subl $16, 0xf1, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/zapnot-99.S b/none/tests/sw64-insn/zapnot-99.S +new file mode 100644 +index 000000000..ccf55c1d4 +--- /dev/null ++++ b/none/tests/sw64-insn/zapnot-99.S +@@ -0,0 +1,13 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0xf0f1 ++ ldi $18, 0b1110 ++ zapnot $17, $18, $16 ++ srl $16, 8, $16 ++ subl $16, 0xf0, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-insn/zapnoti-167.S b/none/tests/sw64-insn/zapnoti-167.S +new file mode 100644 +index 000000000..c71fb63ca +--- /dev/null ++++ b/none/tests/sw64-insn/zapnoti-167.S +@@ -0,0 +1,12 @@ ++ ++ .global _start ++_start: ++ ldi $17, 0xf0f1 ++ zapnot $17, 0b1110, $16 ++ srl $16, 8, $16 ++ subl $16, 0xf0, $16 ++ ++exit: ++ ldi $0, 1 ++ sys_call 0x83 ++ +diff --git a/none/tests/sw64-linux/.deps/getcontext.Po b/none/tests/sw64-linux/.deps/getcontext.Po +new file mode 100644 +index 000000000..5dd61b3e1 +--- /dev/null ++++ b/none/tests/sw64-linux/.deps/getcontext.Po +@@ -0,0 +1,49 @@ ++getcontext.o: getcontext.c /usr/include/stdc-predef.h \ ++ /usr/include/stdio.h /usr/include/bits/libc-header-start.h \ ++ /usr/include/features.h /usr/include/features-time64.h \ ++ /usr/include/bits/wordsize.h /usr/include/bits/timesize.h \ ++ /usr/include/sys/cdefs.h /usr/include/bits/long-double.h \ ++ /usr/include/gnu/stubs.h \ ++ /usr/lib/gcc/sw_64-linux-gnu/10.3.1/include/stddef.h \ ++ /usr/lib/gcc/sw_64-linux-gnu/10.3.1/include/stdarg.h \ ++ /usr/include/bits/types.h /usr/include/bits/typesizes.h \ ++ /usr/include/bits/time64.h /usr/include/bits/types/__fpos_t.h \ ++ /usr/include/bits/types/__mbstate_t.h \ ++ /usr/include/bits/types/__fpos64_t.h /usr/include/bits/types/__FILE.h \ ++ /usr/include/bits/types/FILE.h /usr/include/bits/types/struct_FILE.h \ ++ /usr/include/bits/stdio_lim.h /usr/include/bits/floatn.h \ ++ /usr/include/bits/floatn-common.h /usr/include/bits/stdio-ldbl.h \ ++ /usr/include/ucontext.h /usr/include/bits/indirect-return.h \ ++ /usr/include/sys/ucontext.h /usr/include/bits/types/sigset_t.h \ ++ /usr/include/bits/types/__sigset_t.h /usr/include/bits/types/stack_t.h ++/usr/include/stdc-predef.h: ++/usr/include/stdio.h: ++/usr/include/bits/libc-header-start.h: ++/usr/include/features.h: ++/usr/include/features-time64.h: ++/usr/include/bits/wordsize.h: ++/usr/include/bits/timesize.h: ++/usr/include/sys/cdefs.h: ++/usr/include/bits/long-double.h: ++/usr/include/gnu/stubs.h: ++/usr/lib/gcc/sw_64-linux-gnu/10.3.1/include/stddef.h: ++/usr/lib/gcc/sw_64-linux-gnu/10.3.1/include/stdarg.h: ++/usr/include/bits/types.h: ++/usr/include/bits/typesizes.h: ++/usr/include/bits/time64.h: ++/usr/include/bits/types/__fpos_t.h: ++/usr/include/bits/types/__mbstate_t.h: ++/usr/include/bits/types/__fpos64_t.h: ++/usr/include/bits/types/__FILE.h: ++/usr/include/bits/types/FILE.h: ++/usr/include/bits/types/struct_FILE.h: ++/usr/include/bits/stdio_lim.h: ++/usr/include/bits/floatn.h: ++/usr/include/bits/floatn-common.h: ++/usr/include/bits/stdio-ldbl.h: ++/usr/include/ucontext.h: ++/usr/include/bits/indirect-return.h: ++/usr/include/sys/ucontext.h: ++/usr/include/bits/types/sigset_t.h: ++/usr/include/bits/types/__sigset_t.h: ++/usr/include/bits/types/stack_t.h: +diff --git a/none/tests/sw64-linux/.deps/gethostname.Po b/none/tests/sw64-linux/.deps/gethostname.Po +new file mode 100644 +index 000000000..07df9561b +--- /dev/null ++++ b/none/tests/sw64-linux/.deps/gethostname.Po +@@ -0,0 +1,123 @@ ++gethostname.o: gethostname.c /usr/include/stdc-predef.h \ ++ /usr/include/stdio.h /usr/include/bits/libc-header-start.h \ ++ /usr/include/features.h /usr/include/features-time64.h \ ++ /usr/include/bits/wordsize.h /usr/include/bits/timesize.h \ ++ /usr/include/sys/cdefs.h /usr/include/bits/long-double.h \ ++ /usr/include/gnu/stubs.h \ ++ /usr/lib/gcc/sw_64-linux-gnu/10.3.1/include/stddef.h \ ++ /usr/lib/gcc/sw_64-linux-gnu/10.3.1/include/stdarg.h \ ++ /usr/include/bits/types.h /usr/include/bits/typesizes.h \ ++ /usr/include/bits/time64.h /usr/include/bits/types/__fpos_t.h \ ++ /usr/include/bits/types/__mbstate_t.h \ ++ /usr/include/bits/types/__fpos64_t.h /usr/include/bits/types/__FILE.h \ ++ /usr/include/bits/types/FILE.h /usr/include/bits/types/struct_FILE.h \ ++ /usr/include/bits/stdio_lim.h /usr/include/bits/floatn.h \ ++ /usr/include/bits/floatn-common.h /usr/include/bits/stdio-ldbl.h \ ++ /usr/include/stdlib.h /usr/include/bits/waitflags.h \ ++ /usr/include/bits/waitstatus.h /usr/include/sys/types.h \ ++ /usr/include/bits/types/clock_t.h /usr/include/bits/types/clockid_t.h \ ++ /usr/include/bits/types/time_t.h /usr/include/bits/types/timer_t.h \ ++ /usr/include/bits/stdint-intn.h /usr/include/endian.h \ ++ /usr/include/bits/endian.h /usr/include/bits/endianness.h \ ++ /usr/include/bits/byteswap.h /usr/include/bits/uintn-identity.h \ ++ /usr/include/sys/select.h /usr/include/bits/select.h \ ++ /usr/include/bits/types/sigset_t.h /usr/include/bits/types/__sigset_t.h \ ++ /usr/include/bits/types/struct_timeval.h \ ++ /usr/include/bits/types/struct_timespec.h \ ++ /usr/include/bits/pthreadtypes.h /usr/include/bits/thread-shared-types.h \ ++ /usr/include/bits/pthreadtypes-arch.h /usr/include/bits/struct_mutex.h \ ++ /usr/include/bits/struct_rwlock.h /usr/include/alloca.h \ ++ /usr/include/bits/stdlib-float.h /usr/include/bits/stdlib-ldbl.h \ ++ /usr/include/string.h /usr/include/bits/types/locale_t.h \ ++ /usr/include/bits/types/__locale_t.h /usr/include/strings.h \ ++ /usr/include/fcntl.h /usr/include/bits/fcntl.h \ ++ /usr/include/bits/fcntl-linux.h /usr/include/bits/stat.h \ ++ /usr/include/bits/struct_stat.h \ ++ /usr/lib/gcc/sw_64-linux-gnu/10.3.1/include/limits.h \ ++ /usr/lib/gcc/sw_64-linux-gnu/10.3.1/include/syslimits.h \ ++ /usr/include/limits.h /usr/include/bits/posix1_lim.h \ ++ /usr/include/bits/local_lim.h /usr/include/linux/limits.h \ ++ /usr/include/bits/pthread_stack_min-dynamic.h \ ++ /usr/include/bits/pthread_stack_min.h /usr/include/bits/posix2_lim.h \ ++ /usr/include/unistd.h /usr/include/bits/posix_opt.h \ ++ /usr/include/bits/environments.h /usr/include/bits/confname.h \ ++ /usr/include/bits/getopt_posix.h /usr/include/bits/getopt_core.h \ ++ /usr/include/bits/unistd_ext.h ++/usr/include/stdc-predef.h: ++/usr/include/stdio.h: ++/usr/include/bits/libc-header-start.h: ++/usr/include/features.h: ++/usr/include/features-time64.h: ++/usr/include/bits/wordsize.h: ++/usr/include/bits/timesize.h: ++/usr/include/sys/cdefs.h: ++/usr/include/bits/long-double.h: ++/usr/include/gnu/stubs.h: ++/usr/lib/gcc/sw_64-linux-gnu/10.3.1/include/stddef.h: ++/usr/lib/gcc/sw_64-linux-gnu/10.3.1/include/stdarg.h: ++/usr/include/bits/types.h: ++/usr/include/bits/typesizes.h: ++/usr/include/bits/time64.h: ++/usr/include/bits/types/__fpos_t.h: ++/usr/include/bits/types/__mbstate_t.h: ++/usr/include/bits/types/__fpos64_t.h: ++/usr/include/bits/types/__FILE.h: ++/usr/include/bits/types/FILE.h: ++/usr/include/bits/types/struct_FILE.h: ++/usr/include/bits/stdio_lim.h: ++/usr/include/bits/floatn.h: ++/usr/include/bits/floatn-common.h: ++/usr/include/bits/stdio-ldbl.h: ++/usr/include/stdlib.h: ++/usr/include/bits/waitflags.h: ++/usr/include/bits/waitstatus.h: ++/usr/include/sys/types.h: ++/usr/include/bits/types/clock_t.h: ++/usr/include/bits/types/clockid_t.h: ++/usr/include/bits/types/time_t.h: ++/usr/include/bits/types/timer_t.h: ++/usr/include/bits/stdint-intn.h: ++/usr/include/endian.h: ++/usr/include/bits/endian.h: ++/usr/include/bits/endianness.h: ++/usr/include/bits/byteswap.h: ++/usr/include/bits/uintn-identity.h: ++/usr/include/sys/select.h: ++/usr/include/bits/select.h: ++/usr/include/bits/types/sigset_t.h: ++/usr/include/bits/types/__sigset_t.h: ++/usr/include/bits/types/struct_timeval.h: ++/usr/include/bits/types/struct_timespec.h: ++/usr/include/bits/pthreadtypes.h: ++/usr/include/bits/thread-shared-types.h: ++/usr/include/bits/pthreadtypes-arch.h: ++/usr/include/bits/struct_mutex.h: ++/usr/include/bits/struct_rwlock.h: ++/usr/include/alloca.h: ++/usr/include/bits/stdlib-float.h: ++/usr/include/bits/stdlib-ldbl.h: ++/usr/include/string.h: ++/usr/include/bits/types/locale_t.h: ++/usr/include/bits/types/__locale_t.h: ++/usr/include/strings.h: ++/usr/include/fcntl.h: ++/usr/include/bits/fcntl.h: ++/usr/include/bits/fcntl-linux.h: ++/usr/include/bits/stat.h: ++/usr/include/bits/struct_stat.h: ++/usr/lib/gcc/sw_64-linux-gnu/10.3.1/include/limits.h: ++/usr/lib/gcc/sw_64-linux-gnu/10.3.1/include/syslimits.h: ++/usr/include/limits.h: ++/usr/include/bits/posix1_lim.h: ++/usr/include/bits/local_lim.h: ++/usr/include/linux/limits.h: ++/usr/include/bits/pthread_stack_min-dynamic.h: ++/usr/include/bits/pthread_stack_min.h: ++/usr/include/bits/posix2_lim.h: ++/usr/include/unistd.h: ++/usr/include/bits/posix_opt.h: ++/usr/include/bits/environments.h: ++/usr/include/bits/confname.h: ++/usr/include/bits/getopt_posix.h: ++/usr/include/bits/getopt_core.h: ++/usr/include/bits/unistd_ext.h: +diff --git a/none/tests/sw64-linux/.deps/prctl.Po b/none/tests/sw64-linux/.deps/prctl.Po +new file mode 100644 +index 000000000..46d2dd73d +--- /dev/null ++++ b/none/tests/sw64-linux/.deps/prctl.Po +@@ -0,0 +1,71 @@ ++prctl.o: prctl.c /usr/include/stdc-predef.h /usr/include/stdio.h \ ++ /usr/include/bits/libc-header-start.h /usr/include/features.h \ ++ /usr/include/features-time64.h /usr/include/bits/wordsize.h \ ++ /usr/include/bits/timesize.h /usr/include/sys/cdefs.h \ ++ /usr/include/bits/long-double.h /usr/include/gnu/stubs.h \ ++ /usr/lib/gcc/sw_64-linux-gnu/10.3.1/include/stddef.h \ ++ /usr/lib/gcc/sw_64-linux-gnu/10.3.1/include/stdarg.h \ ++ /usr/include/bits/types.h /usr/include/bits/typesizes.h \ ++ /usr/include/bits/time64.h /usr/include/bits/types/__fpos_t.h \ ++ /usr/include/bits/types/__mbstate_t.h \ ++ /usr/include/bits/types/__fpos64_t.h /usr/include/bits/types/__FILE.h \ ++ /usr/include/bits/types/FILE.h /usr/include/bits/types/struct_FILE.h \ ++ /usr/include/bits/stdio_lim.h /usr/include/bits/floatn.h \ ++ /usr/include/bits/floatn-common.h /usr/include/bits/stdio-ldbl.h \ ++ /usr/include/string.h /usr/include/bits/types/locale_t.h \ ++ /usr/include/bits/types/__locale_t.h /usr/include/strings.h \ ++ /usr/include/errno.h /usr/include/bits/errno.h \ ++ /usr/include/linux/errno.h /usr/include/asm/errno.h \ ++ /usr/include/asm-generic/errno-base.h /usr/include/sys/prctl.h \ ++ /usr/include/linux/prctl.h /usr/include/linux/types.h \ ++ /usr/include/asm/types.h /usr/include/asm-generic/types.h \ ++ /usr/include/asm-generic/int-ll64.h /usr/include/asm/bitsperlong.h \ ++ /usr/include/asm-generic/bitsperlong.h /usr/include/linux/posix_types.h \ ++ /usr/include/linux/stddef.h /usr/include/asm/posix_types.h \ ++ /usr/include/asm-generic/posix_types.h ++/usr/include/stdc-predef.h: ++/usr/include/stdio.h: ++/usr/include/bits/libc-header-start.h: ++/usr/include/features.h: ++/usr/include/features-time64.h: ++/usr/include/bits/wordsize.h: ++/usr/include/bits/timesize.h: ++/usr/include/sys/cdefs.h: ++/usr/include/bits/long-double.h: ++/usr/include/gnu/stubs.h: ++/usr/lib/gcc/sw_64-linux-gnu/10.3.1/include/stddef.h: ++/usr/lib/gcc/sw_64-linux-gnu/10.3.1/include/stdarg.h: ++/usr/include/bits/types.h: ++/usr/include/bits/typesizes.h: ++/usr/include/bits/time64.h: ++/usr/include/bits/types/__fpos_t.h: ++/usr/include/bits/types/__mbstate_t.h: ++/usr/include/bits/types/__fpos64_t.h: ++/usr/include/bits/types/__FILE.h: ++/usr/include/bits/types/FILE.h: ++/usr/include/bits/types/struct_FILE.h: ++/usr/include/bits/stdio_lim.h: ++/usr/include/bits/floatn.h: ++/usr/include/bits/floatn-common.h: ++/usr/include/bits/stdio-ldbl.h: ++/usr/include/string.h: ++/usr/include/bits/types/locale_t.h: ++/usr/include/bits/types/__locale_t.h: ++/usr/include/strings.h: ++/usr/include/errno.h: ++/usr/include/bits/errno.h: ++/usr/include/linux/errno.h: ++/usr/include/asm/errno.h: ++/usr/include/asm-generic/errno-base.h: ++/usr/include/sys/prctl.h: ++/usr/include/linux/prctl.h: ++/usr/include/linux/types.h: ++/usr/include/asm/types.h: ++/usr/include/asm-generic/types.h: ++/usr/include/asm-generic/int-ll64.h: ++/usr/include/asm/bitsperlong.h: ++/usr/include/asm-generic/bitsperlong.h: ++/usr/include/linux/posix_types.h: ++/usr/include/linux/stddef.h: ++/usr/include/asm/posix_types.h: ++/usr/include/asm-generic/posix_types.h: +diff --git a/none/tests/sw64-linux/.deps/readahead.Po b/none/tests/sw64-linux/.deps/readahead.Po +new file mode 100644 +index 000000000..87db80490 +--- /dev/null ++++ b/none/tests/sw64-linux/.deps/readahead.Po +@@ -0,0 +1,70 @@ ++readahead.o: readahead.c /usr/include/stdc-predef.h /usr/include/fcntl.h \ ++ /usr/include/features.h /usr/include/features-time64.h \ ++ /usr/include/bits/wordsize.h /usr/include/bits/timesize.h \ ++ /usr/include/sys/cdefs.h /usr/include/bits/long-double.h \ ++ /usr/include/gnu/stubs.h /usr/include/bits/types.h \ ++ /usr/include/bits/typesizes.h /usr/include/bits/time64.h \ ++ /usr/include/bits/fcntl.h /usr/include/bits/fcntl-linux.h \ ++ /usr/include/bits/types/struct_iovec.h \ ++ /usr/lib/gcc/sw_64-linux-gnu/10.3.1/include/stddef.h \ ++ /usr/include/linux/falloc.h /usr/include/bits/types/struct_timespec.h \ ++ /usr/include/bits/endian.h /usr/include/bits/endianness.h \ ++ /usr/include/bits/types/time_t.h /usr/include/bits/stat.h \ ++ /usr/include/bits/struct_stat.h /usr/include/unistd.h \ ++ /usr/include/bits/posix_opt.h /usr/include/bits/environments.h \ ++ /usr/include/bits/confname.h /usr/include/bits/getopt_posix.h \ ++ /usr/include/bits/getopt_core.h /usr/include/bits/unistd_ext.h \ ++ /usr/include/linux/close_range.h /usr/include/stdio.h \ ++ /usr/include/bits/libc-header-start.h \ ++ /usr/lib/gcc/sw_64-linux-gnu/10.3.1/include/stdarg.h \ ++ /usr/include/bits/types/__fpos_t.h /usr/include/bits/types/__mbstate_t.h \ ++ /usr/include/bits/types/__fpos64_t.h /usr/include/bits/types/__FILE.h \ ++ /usr/include/bits/types/FILE.h /usr/include/bits/types/struct_FILE.h \ ++ /usr/include/bits/types/cookie_io_functions_t.h \ ++ /usr/include/bits/stdio_lim.h /usr/include/bits/floatn.h \ ++ /usr/include/bits/floatn-common.h /usr/include/bits/stdio-ldbl.h ++/usr/include/stdc-predef.h: ++/usr/include/fcntl.h: ++/usr/include/features.h: ++/usr/include/features-time64.h: ++/usr/include/bits/wordsize.h: ++/usr/include/bits/timesize.h: ++/usr/include/sys/cdefs.h: ++/usr/include/bits/long-double.h: ++/usr/include/gnu/stubs.h: ++/usr/include/bits/types.h: ++/usr/include/bits/typesizes.h: ++/usr/include/bits/time64.h: ++/usr/include/bits/fcntl.h: ++/usr/include/bits/fcntl-linux.h: ++/usr/include/bits/types/struct_iovec.h: ++/usr/lib/gcc/sw_64-linux-gnu/10.3.1/include/stddef.h: ++/usr/include/linux/falloc.h: ++/usr/include/bits/types/struct_timespec.h: ++/usr/include/bits/endian.h: ++/usr/include/bits/endianness.h: ++/usr/include/bits/types/time_t.h: ++/usr/include/bits/stat.h: ++/usr/include/bits/struct_stat.h: ++/usr/include/unistd.h: ++/usr/include/bits/posix_opt.h: ++/usr/include/bits/environments.h: ++/usr/include/bits/confname.h: ++/usr/include/bits/getopt_posix.h: ++/usr/include/bits/getopt_core.h: ++/usr/include/bits/unistd_ext.h: ++/usr/include/linux/close_range.h: ++/usr/include/stdio.h: ++/usr/include/bits/libc-header-start.h: ++/usr/lib/gcc/sw_64-linux-gnu/10.3.1/include/stdarg.h: ++/usr/include/bits/types/__fpos_t.h: ++/usr/include/bits/types/__mbstate_t.h: ++/usr/include/bits/types/__fpos64_t.h: ++/usr/include/bits/types/__FILE.h: ++/usr/include/bits/types/FILE.h: ++/usr/include/bits/types/struct_FILE.h: ++/usr/include/bits/types/cookie_io_functions_t.h: ++/usr/include/bits/stdio_lim.h: ++/usr/include/bits/floatn.h: ++/usr/include/bits/floatn-common.h: ++/usr/include/bits/stdio-ldbl.h: +diff --git a/none/tests/sw64-linux/.deps/sigsuspend.Po b/none/tests/sw64-linux/.deps/sigsuspend.Po +new file mode 100644 +index 000000000..657cac6c1 +--- /dev/null ++++ b/none/tests/sw64-linux/.deps/sigsuspend.Po +@@ -0,0 +1,106 @@ ++sigsuspend.o: sigsuspend.c /usr/include/stdc-predef.h \ ++ /usr/include/unistd.h /usr/include/features.h \ ++ /usr/include/features-time64.h /usr/include/bits/wordsize.h \ ++ /usr/include/bits/timesize.h /usr/include/sys/cdefs.h \ ++ /usr/include/bits/long-double.h /usr/include/gnu/stubs.h \ ++ /usr/include/bits/posix_opt.h /usr/include/bits/environments.h \ ++ /usr/include/bits/types.h /usr/include/bits/typesizes.h \ ++ /usr/include/bits/time64.h \ ++ /usr/lib/gcc/sw_64-linux-gnu/10.3.1/include/stddef.h \ ++ /usr/include/bits/confname.h /usr/include/bits/getopt_posix.h \ ++ /usr/include/bits/getopt_core.h /usr/include/bits/unistd_ext.h \ ++ /usr/include/linux/close_range.h /usr/include/signal.h \ ++ /usr/include/bits/signum-generic.h /usr/include/bits/signum-arch.h \ ++ /usr/include/bits/types/sig_atomic_t.h \ ++ /usr/include/bits/types/sigset_t.h /usr/include/bits/types/__sigset_t.h \ ++ /usr/include/bits/types/struct_timespec.h /usr/include/bits/endian.h \ ++ /usr/include/bits/endianness.h /usr/include/bits/types/time_t.h \ ++ /usr/include/bits/types/siginfo_t.h /usr/include/bits/types/__sigval_t.h \ ++ /usr/include/bits/siginfo-arch.h /usr/include/bits/siginfo-consts.h \ ++ /usr/include/bits/siginfo-consts-arch.h \ ++ /usr/include/bits/types/sigval_t.h /usr/include/bits/types/sigevent_t.h \ ++ /usr/include/bits/sigevent-consts.h /usr/include/bits/sigaction.h \ ++ /usr/include/bits/sigcontext.h /usr/include/asm/sigcontext.h \ ++ /usr/include/bits/types/stack_t.h /usr/include/sys/ucontext.h \ ++ /usr/include/bits/sigstack.h /usr/include/bits/sigstksz.h \ ++ /usr/include/bits/ss_flags.h /usr/include/bits/types/struct_sigstack.h \ ++ /usr/include/bits/pthreadtypes.h /usr/include/bits/thread-shared-types.h \ ++ /usr/include/bits/pthreadtypes-arch.h /usr/include/bits/struct_mutex.h \ ++ /usr/include/bits/struct_rwlock.h /usr/include/bits/sigthread.h \ ++ /usr/include/bits/signal_ext.h /usr/include/stdio.h \ ++ /usr/include/bits/libc-header-start.h \ ++ /usr/lib/gcc/sw_64-linux-gnu/10.3.1/include/stdarg.h \ ++ /usr/include/bits/types/__fpos_t.h /usr/include/bits/types/__mbstate_t.h \ ++ /usr/include/bits/types/__fpos64_t.h /usr/include/bits/types/__FILE.h \ ++ /usr/include/bits/types/FILE.h /usr/include/bits/types/struct_FILE.h \ ++ /usr/include/bits/types/cookie_io_functions_t.h \ ++ /usr/include/bits/stdio_lim.h /usr/include/bits/floatn.h \ ++ /usr/include/bits/floatn-common.h /usr/include/bits/stdio-ldbl.h ++/usr/include/stdc-predef.h: ++/usr/include/unistd.h: ++/usr/include/features.h: ++/usr/include/features-time64.h: ++/usr/include/bits/wordsize.h: ++/usr/include/bits/timesize.h: ++/usr/include/sys/cdefs.h: ++/usr/include/bits/long-double.h: ++/usr/include/gnu/stubs.h: ++/usr/include/bits/posix_opt.h: ++/usr/include/bits/environments.h: ++/usr/include/bits/types.h: ++/usr/include/bits/typesizes.h: ++/usr/include/bits/time64.h: ++/usr/lib/gcc/sw_64-linux-gnu/10.3.1/include/stddef.h: ++/usr/include/bits/confname.h: ++/usr/include/bits/getopt_posix.h: ++/usr/include/bits/getopt_core.h: ++/usr/include/bits/unistd_ext.h: ++/usr/include/linux/close_range.h: ++/usr/include/signal.h: ++/usr/include/bits/signum-generic.h: ++/usr/include/bits/signum-arch.h: ++/usr/include/bits/types/sig_atomic_t.h: ++/usr/include/bits/types/sigset_t.h: ++/usr/include/bits/types/__sigset_t.h: ++/usr/include/bits/types/struct_timespec.h: ++/usr/include/bits/endian.h: ++/usr/include/bits/endianness.h: ++/usr/include/bits/types/time_t.h: ++/usr/include/bits/types/siginfo_t.h: ++/usr/include/bits/types/__sigval_t.h: ++/usr/include/bits/siginfo-arch.h: ++/usr/include/bits/siginfo-consts.h: ++/usr/include/bits/siginfo-consts-arch.h: ++/usr/include/bits/types/sigval_t.h: ++/usr/include/bits/types/sigevent_t.h: ++/usr/include/bits/sigevent-consts.h: ++/usr/include/bits/sigaction.h: ++/usr/include/bits/sigcontext.h: ++/usr/include/asm/sigcontext.h: ++/usr/include/bits/types/stack_t.h: ++/usr/include/sys/ucontext.h: ++/usr/include/bits/sigstack.h: ++/usr/include/bits/sigstksz.h: ++/usr/include/bits/ss_flags.h: ++/usr/include/bits/types/struct_sigstack.h: ++/usr/include/bits/pthreadtypes.h: ++/usr/include/bits/thread-shared-types.h: ++/usr/include/bits/pthreadtypes-arch.h: ++/usr/include/bits/struct_mutex.h: ++/usr/include/bits/struct_rwlock.h: ++/usr/include/bits/sigthread.h: ++/usr/include/bits/signal_ext.h: ++/usr/include/stdio.h: ++/usr/include/bits/libc-header-start.h: ++/usr/lib/gcc/sw_64-linux-gnu/10.3.1/include/stdarg.h: ++/usr/include/bits/types/__fpos_t.h: ++/usr/include/bits/types/__mbstate_t.h: ++/usr/include/bits/types/__fpos64_t.h: ++/usr/include/bits/types/__FILE.h: ++/usr/include/bits/types/FILE.h: ++/usr/include/bits/types/struct_FILE.h: ++/usr/include/bits/types/cookie_io_functions_t.h: ++/usr/include/bits/stdio_lim.h: ++/usr/include/bits/floatn.h: ++/usr/include/bits/floatn-common.h: ++/usr/include/bits/stdio-ldbl.h: +diff --git a/none/tests/sw64-linux/Makefile b/none/tests/sw64-linux/Makefile +new file mode 100644 +index 000000000..d4573bb38 +--- /dev/null ++++ b/none/tests/sw64-linux/Makefile +@@ -0,0 +1,1041 @@ ++# Makefile.in generated by automake 1.16.5 from Makefile.am. ++# none/tests/sw64-linux/Makefile. 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\ ++ *) (install-info --version) >/dev/null 2>&1;; \ ++ esac ++am__tagged_files = $(HEADERS) $(SOURCES) $(TAGS_FILES) $(LISP) ++# Read a list of newline-separated strings from the standard input, ++# and print each of them once, without duplicates. Input order is ++# *not* preserved. ++am__uniquify_input = $(AWK) '\ ++ BEGIN { nonempty = 0; } \ ++ { items[$$0] = 1; nonempty = 1; } \ ++ END { if (nonempty) { for (i in items) print i; }; } \ ++' ++# Make sure the list of sources is unique. This is necessary because, ++# e.g., the same source file might be shared among _SOURCES variables ++# for different programs/libraries. ++am__define_uniq_tagged_files = \ ++ list='$(am__tagged_files)'; \ ++ unique=`for i in $$list; do \ ++ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \ ++ done | $(am__uniquify_input)` ++am__DIST_COMMON = $(srcdir)/Makefile.in $(top_srcdir)/Makefile.all.am \ ++ $(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/depcomp ++DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST) ++ACLOCAL = ${SHELL} '/home/zlh/valgrind-sw/valgrind-3.19.0/missing' aclocal-1.16 ++AMTAR = $${TAR-tar} ++AM_DEFAULT_VERBOSITY = 1 ++AR = /usr/bin/ar ++AUTOCONF = ${SHELL} '/home/zlh/valgrind-sw/valgrind-3.19.0/missing' autoconf ++AUTOHEADER = ${SHELL} '/home/zlh/valgrind-sw/valgrind-3.19.0/missing' autoheader ++AUTOMAKE = ${SHELL} '/home/zlh/valgrind-sw/valgrind-3.19.0/missing' automake-1.16 ++AWK = gawk ++BOOST_CFLAGS = ++BOOST_LIBS = ++CC = gcc ++CCAS = gcc ++CCASDEPMODE = depmode=gcc3 ++CCASFLAGS = ++CCDEPMODE = depmode=gcc3 ++CFLAGS = ++CFLAGS_MPI = -g -O -fno-omit-frame-pointer -Wall -fpic ++CPP = gcc -E ++CPPFLAGS = ++CSCOPE = cscope ++CTAGS = ctags ++CXX = g++ ++CXXDEPMODE = depmode=gcc3 ++CXXFLAGS = ++CYGPATH_W = echo ++DEFAULT_SUPP = ./xfree-3.supp ./xfree-4.supp glibc-2.X-drd.supp glibc-2.X-helgrind.supp glibc-2.X.supp ++DEFS = -DHAVE_CONFIG_H ++DEPDIR = .deps ++DIFF = diff -u ++DIS_PATH = ++ECHO_C = ++ECHO_N = -n ++ECHO_T = ++EGREP = /usr/bin/grep -E ++ETAGS = etags ++EXEEXT = ++FLAG_FALIGNED_NEW = -faligned-new ++FLAG_FINLINE_FUNCTIONS = -finline-functions ++FLAG_FNO_IPA_ICF = -fno-ipa-icf ++FLAG_FNO_STACK_PROTECTOR = -fno-stack-protector ++FLAG_FSANITIZE = ++FLAG_FSIZED_DEALLOCATION = -fsized-deallocation ++FLAG_M32 = ++FLAG_M64 = ++FLAG_MLONG_DOUBLE_128 = -mlong-double-128 ++FLAG_MMMX = ++FLAG_MSA = ++FLAG_MSSE = ++FLAG_NO_BUILD_ID = ++FLAG_NO_PIE = -no-pie ++FLAG_OCTEON = ++FLAG_OCTEON2 = ++FLAG_PIE = -pie ++FLAG_T_TEXT = -Ttext-segment ++FLAG_UNLIMITED_INLINE_UNIT_GROWTH = --param inline-unit-growth=900 ++FLAG_W_CAST_ALIGN = -Wcast-align ++FLAG_W_CAST_QUAL = -Wcast-qual ++FLAG_W_EMPTY_BODY = -Wempty-body ++FLAG_W_ENUM_CONVERSION = -Wenum-conversion ++FLAG_W_EXTRA = -Wextra ++FLAG_W_FORMAT = -Wformat ++FLAG_W_FORMAT_SECURITY = -Wformat-security ++FLAG_W_FORMAT_SIGNEDNESS = -Wformat-signedness ++FLAG_W_IGNORED_QUALIFIERS = -Wignored-qualifiers ++FLAG_W_IMPLICIT_FALLTHROUGH = -Wimplicit-fallthrough=2 ++FLAG_W_LOGICAL_OP = -Wlogical-op ++FLAG_W_MISSING_PARAMETER_TYPE = -Wmissing-parameter-type ++FLAG_W_NO_EXPANSION_TO_DEFINED = -Wno-expansion-to-defined ++FLAG_W_NO_INFINITE_RECURSION = ++FLAG_W_NO_MEMSET_TRANSPOSED_ARGS = -Wno-memset-transposed-args ++FLAG_W_NO_MISMATCHED_NEW_DELETE = ++FLAG_W_NO_NONNULL = -Wno-nonnull ++FLAG_W_NO_OVERFLOW = -Wno-overflow ++FLAG_W_NO_POINTER_SIGN = -Wno-pointer-sign ++FLAG_W_NO_STATIC_LOCAL_IN_INLINE = ++FLAG_W_NO_UNINITIALIZED = -Wno-uninitialized ++FLAG_W_NO_UNUSED_FUNCTION = -Wno-unused-function ++FLAG_W_OLD_STYLE_DECLARATION = -Wold-style-declaration ++FLAG_W_WRITE_STRINGS = -Wwrite-strings ++GDB = /usr/local/bin/gdb ++GLIBC_LIBC_PATH = */lib*/libc.so.6 ++GLIBC_LIBPTHREAD_PATH = */lib*/libc.so.6 ++GLIBC_VERSION = 2.34 ++GREP = /usr/bin/grep ++HWCAP_HAS_ALTIVEC = ++HWCAP_HAS_DFP = ++HWCAP_HAS_HTM = ++HWCAP_HAS_ISA_2_05 = ++HWCAP_HAS_ISA_2_06 = ++HWCAP_HAS_ISA_2_07 = ++HWCAP_HAS_ISA_3_00 = ++HWCAP_HAS_ISA_3_1 = ++HWCAP_HAS_MMA = ++HWCAP_HAS_VSX = ++INSTALL = /usr/bin/install -c ++INSTALL_DATA = ${INSTALL} -m 644 ++INSTALL_PROGRAM = ${INSTALL} ++INSTALL_SCRIPT = ${INSTALL} ++INSTALL_STRIP_PROGRAM = $(install_sh) -c -s ++LDFLAGS = ++LDFLAGS_MPI = -fpic -shared ++LIBOBJS = ++LIBS = ++LIB_UBSAN = ++LN_S = ln -s ++LTLIBOBJS = ++LTO_AR = /usr/bin/ar ++LTO_CFLAGS = ++LTO_RANLIB = ranlib ++MAINT = # ++MAKEINFO = ${SHELL} '/home/zlh/valgrind-sw/valgrind-3.19.0/missing' makeinfo ++MKDIR_P = /usr/bin/mkdir -p ++MPI_CC = /usr/bin/mpicc ++OBJEXT = o ++PACKAGE = valgrind ++PACKAGE_BUGREPORT = valgrind-users@lists.sourceforge.net ++PACKAGE_NAME = Valgrind ++PACKAGE_STRING = Valgrind 3.19.0-sw1.0.0 ++PACKAGE_TARNAME = valgrind ++PACKAGE_URL = ++PACKAGE_VERSION = 3.19.0-sw1.0.0 ++PATH_SEPARATOR = : ++PERL = /usr/bin/perl ++PREFERRED_STACK_BOUNDARY_2 = ++RANLIB = ranlib ++SED = /usr/bin/sed ++SET_MAKE = ++SHELL = /bin/sh ++SOLARIS_UNDEF_LARGESOURCE = ++STRIP = ++VALT_LOAD_ADDRESS_PRI = 0x58000000 ++VALT_LOAD_ADDRESS_SEC = 0xUNSET ++VERSION = 3.19.0-sw1.0.0 ++VGCONF_ABI = ++VGCONF_ARCH_PRI = sw64 ++VGCONF_ARCH_SEC = ++VGCONF_OS = linux ++VGCONF_PLATFORM_PRI_CAPS = SW64_LINUX ++VGCONF_PLATFORM_SEC_CAPS = ++VGCONF_PLATVARIANT = vanilla ++VG_DATE = 11 Apr 2022 ++VG_TMPDIR = /tmp ++VG_VER_MAJOR = 3 ++VG_VER_MINOR = 19 ++XCODE_DIR = ++XCRUN = ++abs_builddir = /home/zlh/valgrind-sw/valgrind-3.19.0/none/tests/sw64-linux ++abs_srcdir = /home/zlh/valgrind-sw/valgrind-3.19.0/none/tests/sw64-linux ++abs_top_builddir = /home/zlh/valgrind-sw/valgrind-3.19.0 ++abs_top_srcdir = /home/zlh/valgrind-sw/valgrind-3.19.0 ++ac_ct_CC = gcc ++ac_ct_CXX = g++ ++am__include = include ++am__leading_dot = . ++am__quote = ++am__tar = $${TAR-tar} chof - "$$tardir" ++am__untar = $${TAR-tar} xf - ++bindir = ${exec_prefix}/bin ++build = sw_64-sunway-linux-gnu ++build_alias = ++build_cpu = sw_64 ++build_os = linux-gnu ++build_vendor = sunway ++builddir = . ++datadir = ${datarootdir} ++datarootdir = ${prefix}/share ++docdir = ${datarootdir}/doc/${PACKAGE_TARNAME} ++dvidir = ${docdir} ++exec_prefix = ${prefix} ++host = sw_64-sunway-linux-gnu ++host_alias = ++host_cpu = sw_64 ++host_os = linux-gnu ++host_vendor = sunway ++htmldir = ${docdir} ++includedir = ${prefix}/include ++infodir = ${datarootdir}/info ++install_sh = ${SHELL} /home/zlh/valgrind-sw/valgrind-3.19.0/install-sh ++libdir = ${exec_prefix}/lib ++libexecdir = ${exec_prefix}/libexec ++localedir = ${datarootdir}/locale ++localstatedir = ${prefix}/var ++mandir = ${datarootdir}/man ++mkdir_p = $(MKDIR_P) ++oldincludedir = /usr/include ++pdfdir = ${docdir} ++prefix = /usr/local ++program_transform_name = s,x,x, ++psdir = ${docdir} ++runstatedir = ${localstatedir}/run ++sbindir = ${exec_prefix}/sbin ++sharedstatedir = ${prefix}/com ++srcdir = . ++sysconfdir = ${prefix}/etc ++target_alias = ++top_build_prefix = ../../../ ++top_builddir = ../../.. ++top_srcdir = ../../.. ++inplacedir = $(top_builddir)/.in_place ++ ++#---------------------------------------------------------------------------- ++# Flags ++#---------------------------------------------------------------------------- ++ ++# Baseline flags for all compilations. Aim here is to maximise ++# performance and get whatever useful warnings we can out of gcc. ++# -fno-builtin is important for defeating LLVM's idiom recognition ++# that somehow causes VG_(memset) to get into infinite recursion. ++AM_CFLAGS_BASE = -O2 -g -Wall -Wmissing-prototypes -Wshadow \ ++ -Wpointer-arith -Wstrict-prototypes -Wmissing-declarations \ ++ -Wcast-align -Wcast-qual -Wwrite-strings \ ++ -Wempty-body -Wformat -Wformat-signedness \ ++ -Wformat-security -Wignored-qualifiers \ ++ -Wmissing-parameter-type -Wlogical-op \ ++ -Wenum-conversion -Wimplicit-fallthrough=2 \ ++ -Wold-style-declaration -finline-functions \ ++ -fno-stack-protector \ ++ -fno-strict-aliasing -fno-builtin $(am__append_1) \ ++ $(am__append_2) ++#ISA_3_0_BUILD_FLAG = -DHAS_XSCVHPDP -DHAS_ISA_3_00 ++ ++# Power ISA flag for use by guest_ppc_helpers.c ++##ISA_3_0_BUILD_FLAG = -DHAS_XSCVHPDP -DHAS_DARN -DHAS_ISA_3_00 ++ISA_3_0_BUILD_FLAG = ++AM_CFLAGS_PSO_BASE = -O -g -fno-omit-frame-pointer -fno-strict-aliasing \ ++ -fpic -fno-builtin -fno-ipa-icf ++ ++#AM_CFLAGS_PSO_BASE = -O -g -fno-omit-frame-pointer -fno-strict-aliasing \ ++# -fpic -fPIC -fno-builtin ++ ++ ++# These flags are used for building the preload shared objects (PSOs). ++# The aim is to give reasonable performance but also to have good ++# stack traces, since users often see stack traces extending ++# into (and through) the preloads. Also, we must use any ++# -mpreferred-stack-boundary flag to build the preload shared ++# objects, since that risks misaligning the client's stack and ++# results in segfaults like (eg) #324050. ++#AM_CFLAGS_PSO_BASE = -dynamic \ ++# -O -g -fno-omit-frame-pointer -fno-strict-aliasing \ ++# -fpic -fPIC -fno-builtin -fno-ipa-icf ++ ++ ++# Flags for specific targets. ++# ++# Nb: the AM_CPPFLAGS_* values are suitable for building tools and auxprogs. ++# For building the core, coregrind/Makefile.am files add some extra things. ++AM_CPPFLAGS_SW64_LINUX = -I$(top_srcdir) \ ++ -I$(top_srcdir)/include -I$(top_builddir)/include \ ++ -I$(top_srcdir)/VEX/pub -I$(top_builddir)/VEX/pub \ ++ -DVGA_sw64=1 -DVGO_linux=1 \ ++ -DVGP_sw64_linux=1 \ ++ -DVGPV_sw64_linux_vanilla=1 \ ++ $(am__append_3) ++#AM_CPPFLAGS_ = \ ++# -I$(top_srcdir) \ ++# -I$(top_srcdir)/include \ ++# -I$(top_builddir)/include \ ++# -I$(top_srcdir)/VEX/pub \ ++# -I$(top_builddir)/VEX/pub \ ++# -DVGA_=1 \ ++# -DVGO_linux=1 \ ++# -DVGP__linux=1 \ ++# -DVGPV__linux_vanilla=1 \ ++# $(am__append_4) ++AM_FLAG_M3264_X86_LINUX = ++AM_CFLAGS_X86_LINUX = \ ++ $(AM_CFLAGS_BASE) -fomit-frame-pointer ++ ++AM_CFLAGS_PSO_X86_LINUX = $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE) ++AM_CCASFLAGS_X86_LINUX = -g ++AM_FLAG_M3264_AMD64_LINUX = ++AM_CFLAGS_AMD64_LINUX = \ ++ $(AM_CFLAGS_BASE) -fomit-frame-pointer ++ ++AM_CFLAGS_PSO_AMD64_LINUX = $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE) ++AM_CCASFLAGS_AMD64_LINUX = -g ++AM_FLAG_M3264_PPC32_LINUX = ++AM_CFLAGS_PPC32_LINUX = $(AM_CFLAGS_BASE) ++AM_CFLAGS_PSO_PPC32_LINUX = $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE) ++AM_CCASFLAGS_PPC32_LINUX = -g ++AM_FLAG_M3264_PPC64BE_LINUX = ++AM_CFLAGS_PPC64BE_LINUX = $(AM_CFLAGS_BASE) ++AM_CFLAGS_PSO_PPC64BE_LINUX = $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE) ++AM_CCASFLAGS_PPC64BE_LINUX = -g ++AM_FLAG_M3264_PPC64LE_LINUX = ++AM_CFLAGS_PPC64LE_LINUX = $(AM_CFLAGS_BASE) $(ISA_3_0_BUILD_FLAG) ++AM_CFLAGS_PSO_PPC64LE_LINUX = $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE) ++AM_CCASFLAGS_PPC64LE_LINUX = -g ++AM_FLAG_M3264_X86_FREEBSD = ++AM_CFLAGS_X86_FREEBSD = \ ++ $(AM_CFLAGS_BASE) -fomit-frame-pointer ++ ++AM_CFLAGS_PSO_X86_FREEBSD = $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE) ++AM_CCASFLAGS_X86_FREEBSD = -g ++AM_FLAG_M3264_ARM_LINUX = ++AM_CFLAGS_ARM_LINUX = \ ++ $(AM_CFLAGS_BASE) -marm -mcpu=cortex-a8 ++ ++AM_CFLAGS_PSO_ARM_LINUX = $(AM_CFLAGS_BASE) \ ++ -marm -mcpu=cortex-a8 $(AM_CFLAGS_PSO_BASE) ++ ++AM_CCASFLAGS_ARM_LINUX = \ ++ -marm -mcpu=cortex-a8 -g ++ ++AM_FLAG_M3264_ARM64_LINUX = ++AM_CFLAGS_ARM64_LINUX = $(AM_CFLAGS_BASE) ++AM_CFLAGS_PSO_ARM64_LINUX = $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE) ++AM_CCASFLAGS_ARM64_LINUX = -g ++AM_FLAG_M3264_AMD64_FREEBSD = ++AM_CFLAGS_AMD64_FREEBSD = \ ++ $(AM_CFLAGS_BASE) -fomit-frame-pointer ++ ++AM_CFLAGS_PSO_AMD64_FREEBSD = $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE) ++AM_CCASFLAGS_AMD64_FREEBSD = -g ++AM_FLAG_M3264_X86_DARWIN = -arch i386 ++AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \ ++ -mmacosx-version-min=10.6 \ ++ -fno-pic -fno-PIC ++ ++AM_CFLAGS_PSO_X86_DARWIN = $(AM_CFLAGS_X86_DARWIN) $(AM_CFLAGS_PSO_BASE) ++AM_CCASFLAGS_X86_DARWIN = -arch i386 -g ++AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64 ++AM_CFLAGS_AMD64_DARWIN = $(WERROR) -arch x86_64 $(AM_CFLAGS_BASE) \ ++ -mmacosx-version-min=10.6 ++ ++AM_CFLAGS_PSO_AMD64_DARWIN = $(AM_CFLAGS_AMD64_DARWIN) $(AM_CFLAGS_PSO_BASE) ++AM_CCASFLAGS_AMD64_DARWIN = -arch x86_64 -g ++AM_FLAG_M3264_S390X_LINUX = ++AM_CFLAGS_S390X_LINUX = $(AM_CFLAGS_BASE) -fomit-frame-pointer ++AM_CFLAGS_PSO_S390X_LINUX = $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE) ++AM_CCASFLAGS_S390X_LINUX = -g -mzarch -march=z900 ++AM_FLAG_M3264_MIPS32_LINUX = ++AM_CFLAGS_MIPS32_LINUX = $(AM_CFLAGS_BASE) ++AM_CFLAGS_PSO_MIPS32_LINUX = $(AM_CFLAGS_BASE) \ ++ $(AM_CFLAGS_PSO_BASE) ++ ++AM_CCASFLAGS_MIPS32_LINUX = -g ++AM_FLAG_M3264_NANOMIPS_LINUX = ++AM_CFLAGS_NANOMIPS_LINUX = $(AM_CFLAGS_BASE) -mno-jump-table-opt ++AM_CFLAGS_PSO_NANOMIPS_LINUX = $(AM_CFLAGS_BASE) \ ++ $(AM_CFLAGS_PSO_BASE) ++ ++AM_CCASFLAGS_NANOMIPS_LINUX = -g ++AM_FLAG_M3264_MIPS64_LINUX = ++AM_CFLAGS_MIPS64_LINUX = $(AM_CFLAGS_BASE) ++AM_CFLAGS_PSO_MIPS64_LINUX = $(AM_CFLAGS_BASE) \ ++ $(AM_CFLAGS_PSO_BASE) ++ ++AM_CCASFLAGS_MIPS64_LINUX = -g ++AM_FLAG_M3264_SW64_LINUX = ++AM_CFLAGS_SW64_LINUX = $(AM_CFLAGS_BASE) ++AM_CFLAGS_PSO_SW64_LINUX = $(AM_CFLAGS_BASE) \ ++ $(AM_CFLAGS_PSO_BASE) ++ ++AM_CCASFLAGS_SW64_LINUX = -g ++AM_FLAG_M3264_X86_SOLARIS = ++AM_CFLAGS_X86_SOLARIS = \ ++ $(AM_CFLAGS_BASE) -fomit-frame-pointer ++ ++AM_CFLAGS_PSO_X86_SOLARIS = $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE) ++AM_CCASFLAGS_X86_SOLARIS = -g -D_ASM ++AM_FLAG_M3264_AMD64_SOLARIS = ++AM_CFLAGS_AMD64_SOLARIS = \ ++ $(AM_CFLAGS_BASE) -fomit-frame-pointer ++ ++AM_CFLAGS_PSO_AMD64_SOLARIS = $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE) ++AM_CCASFLAGS_AMD64_SOLARIS = -g -D_ASM ++ ++# Flags for the primary target. These must be used to build the ++# regtests and performance tests. In fact, these must be used to ++# build anything which is built only once on a dual-arch build. ++# ++AM_FLAG_M3264_PRI = $(AM_FLAG_M3264_SW64_LINUX) ++AM_CPPFLAGS_PRI = $(AM_CPPFLAGS_SW64_LINUX) ++AM_CFLAGS_PRI = $(AM_CFLAGS_SW64_LINUX) ++AM_CCASFLAGS_PRI = $(AM_CCASFLAGS_SW64_LINUX) ++AM_FLAG_M3264_SEC = ++#AM_FLAG_M3264_SEC = $(AM_FLAG_M3264_) ++ ++# Baseline link flags for making vgpreload shared objects. ++# ++PRELOAD_LDFLAGS_COMMON_LINUX = -nodefaultlibs -shared \ ++ -Wl,-z,interpose,-z,initfirst $(am__append_6) ++PRELOAD_LDFLAGS_COMMON_FREEBSD = -nodefaultlibs -shared -Wl,-z,interpose,-z,initfirst ++PRELOAD_LDFLAGS_COMMON_DARWIN = -dynamic -dynamiclib -all_load ++PRELOAD_LDFLAGS_COMMON_SOLARIS = -nodefaultlibs -shared \ ++ -Wl,-z,interpose,-z,initfirst $(am__append_5) ++PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) ++PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) ++PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) ++PRELOAD_LDFLAGS_PPC64BE_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) ++PRELOAD_LDFLAGS_PPC64LE_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) ++PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) ++PRELOAD_LDFLAGS_ARM64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) ++PRELOAD_LDFLAGS_X86_FREEBSD = $(PRELOAD_LDFLAGS_COMMON_FREEBSD) ++PRELOAD_LDFLAGS_AMD64_FREEBSD = $(PRELOAD_LDFLAGS_COMMON_FREEBSD) ++PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386 ++PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64 ++PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) ++PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) ++PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) ++PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) ++PRELOAD_LDFLAGS_SW64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) ++PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) ++PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) ++AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ ++ -I$(top_srcdir)/coregrind -I$(top_builddir)/include \ ++ -I$(top_srcdir)/VEX/pub -I$(top_builddir)/VEX/pub \ ++ -DVGA_sw64=1 -DVGO_linux=1 \ ++ -DVGP_sw64_linux=1 \ ++ -DVGPV_sw64_linux_vanilla=1 \ ++ $(am__append_7) $(am__append_8) ++ ++# Nb: Tools need to augment these flags with an arch-selection option, such ++# as $(AM_FLAG_M3264_PRI). ++AM_CFLAGS = -Winline -Wall -Wshadow -Wno-long-long -g \ ++ -fno-stack-protector $(am__append_9) $(am__append_10) \ ++ $(am__empty) ++AM_CXXFLAGS = -Winline -Wall -Wshadow -Wno-long-long -g \ ++ -fno-stack-protector $(am__append_11) ++# Include AM_CPPFLAGS in AM_CCASFLAGS to allow for older versions of ++# automake; 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++#---------------------------------------------------------------------------- ++# Flags ++#---------------------------------------------------------------------------- ++ ++# Baseline flags for all compilations. Aim here is to maximise ++# performance and get whatever useful warnings we can out of gcc. ++# -fno-builtin is important for defeating LLVM's idiom recognition ++# that somehow causes VG_(memset) to get into infinite recursion. ++AM_CFLAGS_BASE = -O2 -g -Wall -Wmissing-prototypes -Wshadow \ ++ -Wpointer-arith -Wstrict-prototypes -Wmissing-declarations \ ++ @FLAG_W_CAST_ALIGN@ @FLAG_W_CAST_QUAL@ @FLAG_W_WRITE_STRINGS@ \ ++ @FLAG_W_EMPTY_BODY@ @FLAG_W_FORMAT@ @FLAG_W_FORMAT_SIGNEDNESS@ \ ++ @FLAG_W_FORMAT_SECURITY@ @FLAG_W_IGNORED_QUALIFIERS@ \ ++ @FLAG_W_MISSING_PARAMETER_TYPE@ @FLAG_W_LOGICAL_OP@ \ ++ @FLAG_W_ENUM_CONVERSION@ @FLAG_W_IMPLICIT_FALLTHROUGH@ \ ++ @FLAG_W_OLD_STYLE_DECLARATION@ @FLAG_FINLINE_FUNCTIONS@ \ ++ @FLAG_FNO_STACK_PROTECTOR@ @FLAG_FSANITIZE@ \ ++ -fno-strict-aliasing -fno-builtin $(am__append_1) \ ++ $(am__append_2) ++@HAS_DARN_FALSE@@HAS_XSCVHPDP_TRUE@ISA_3_0_BUILD_FLAG = -DHAS_XSCVHPDP -DHAS_ISA_3_00 ++ ++# Power ISA flag for use by guest_ppc_helpers.c ++@HAS_DARN_TRUE@@HAS_XSCVHPDP_TRUE@ISA_3_0_BUILD_FLAG = -DHAS_XSCVHPDP -DHAS_DARN -DHAS_ISA_3_00 ++@HAS_XSCVHPDP_FALSE@ISA_3_0_BUILD_FLAG = ++@VGCONF_OS_IS_DARWIN_FALSE@@VGCONF_OS_IS_FREEBSD_FALSE@AM_CFLAGS_PSO_BASE = -O -g -fno-omit-frame-pointer -fno-strict-aliasing \ ++@VGCONF_OS_IS_DARWIN_FALSE@@VGCONF_OS_IS_FREEBSD_FALSE@ -fpic -fno-builtin @FLAG_FNO_IPA_ICF@ ++ ++@VGCONF_OS_IS_DARWIN_FALSE@@VGCONF_OS_IS_FREEBSD_TRUE@AM_CFLAGS_PSO_BASE = -O -g -fno-omit-frame-pointer -fno-strict-aliasing \ ++@VGCONF_OS_IS_DARWIN_FALSE@@VGCONF_OS_IS_FREEBSD_TRUE@ -fpic -fPIC -fno-builtin ++ ++ ++# These flags are used for building the preload shared objects (PSOs). ++# The aim is to give reasonable performance but also to have good ++# stack traces, since users often see stack traces extending ++# into (and through) the preloads. Also, we must use any ++# -mpreferred-stack-boundary flag to build the preload shared ++# objects, since that risks misaligning the client's stack and ++# results in segfaults like (eg) #324050. ++@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PSO_BASE = -dynamic \ ++@VGCONF_OS_IS_DARWIN_TRUE@ -O -g -fno-omit-frame-pointer -fno-strict-aliasing \ ++@VGCONF_OS_IS_DARWIN_TRUE@ -fpic -fPIC -fno-builtin @FLAG_FNO_IPA_ICF@ ++ ++ ++# Flags for specific targets. ++# ++# Nb: the AM_CPPFLAGS_* values are suitable for building tools and auxprogs. ++# For building the core, coregrind/Makefile.am files add some extra things. ++AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = -I$(top_srcdir) \ ++ -I$(top_srcdir)/include -I$(top_builddir)/include \ ++ -I$(top_srcdir)/VEX/pub -I$(top_builddir)/VEX/pub \ ++ -DVGA_@VGCONF_ARCH_PRI@=1 -DVGO_@VGCONF_OS@=1 \ ++ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \ ++ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1 \ ++ $(am__append_3) ++@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \ ++@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir) \ ++@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/include \ ++@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/include \ ++@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \ ++@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \ ++@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGA_@VGCONF_ARCH_SEC@=1 \ ++@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGO_@VGCONF_OS@=1 \ ++@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGP_@VGCONF_ARCH_SEC@_@VGCONF_OS@=1 \ ++@VGCONF_HAVE_PLATFORM_SEC_TRUE@ -DVGPV_@VGCONF_ARCH_SEC@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1 \ ++@VGCONF_HAVE_PLATFORM_SEC_TRUE@ $(am__append_4) ++AM_FLAG_M3264_X86_LINUX = @FLAG_M32@ ++AM_CFLAGS_X86_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ ++ $(AM_CFLAGS_BASE) -fomit-frame-pointer ++ ++AM_CFLAGS_PSO_X86_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE) ++AM_CCASFLAGS_X86_LINUX = @FLAG_M32@ -g ++AM_FLAG_M3264_AMD64_LINUX = @FLAG_M64@ ++AM_CFLAGS_AMD64_LINUX = @FLAG_M64@ \ ++ $(AM_CFLAGS_BASE) -fomit-frame-pointer ++ ++AM_CFLAGS_PSO_AMD64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE) ++AM_CCASFLAGS_AMD64_LINUX = @FLAG_M64@ -g ++AM_FLAG_M3264_PPC32_LINUX = @FLAG_M32@ ++AM_CFLAGS_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) ++AM_CFLAGS_PSO_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE) ++AM_CCASFLAGS_PPC32_LINUX = @FLAG_M32@ -g ++AM_FLAG_M3264_PPC64BE_LINUX = @FLAG_M64@ ++AM_CFLAGS_PPC64BE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) ++AM_CFLAGS_PSO_PPC64BE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE) ++AM_CCASFLAGS_PPC64BE_LINUX = @FLAG_M64@ -g ++AM_FLAG_M3264_PPC64LE_LINUX = @FLAG_M64@ ++AM_CFLAGS_PPC64LE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(ISA_3_0_BUILD_FLAG) ++AM_CFLAGS_PSO_PPC64LE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE) ++AM_CCASFLAGS_PPC64LE_LINUX = @FLAG_M64@ -g ++AM_FLAG_M3264_X86_FREEBSD = @FLAG_M32@ ++AM_CFLAGS_X86_FREEBSD = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ ++ $(AM_CFLAGS_BASE) -fomit-frame-pointer ++ ++AM_CFLAGS_PSO_X86_FREEBSD = @FLAG_M32@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE) ++AM_CCASFLAGS_X86_FREEBSD = @FLAG_M32@ -g ++AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@ ++AM_CFLAGS_ARM_LINUX = @FLAG_M32@ \ ++ $(AM_CFLAGS_BASE) -marm -mcpu=cortex-a8 ++ ++AM_CFLAGS_PSO_ARM_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) \ ++ -marm -mcpu=cortex-a8 $(AM_CFLAGS_PSO_BASE) ++ ++AM_CCASFLAGS_ARM_LINUX = @FLAG_M32@ \ ++ -marm -mcpu=cortex-a8 -g ++ ++AM_FLAG_M3264_ARM64_LINUX = @FLAG_M64@ ++AM_CFLAGS_ARM64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) ++AM_CFLAGS_PSO_ARM64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE) ++AM_CCASFLAGS_ARM64_LINUX = @FLAG_M64@ -g ++AM_FLAG_M3264_AMD64_FREEBSD = @FLAG_M64@ ++AM_CFLAGS_AMD64_FREEBSD = @FLAG_M64@ \ ++ $(AM_CFLAGS_BASE) -fomit-frame-pointer ++ ++AM_CFLAGS_PSO_AMD64_FREEBSD = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE) ++AM_CCASFLAGS_AMD64_FREEBSD = @FLAG_M64@ -g ++AM_FLAG_M3264_X86_DARWIN = -arch i386 ++AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \ ++ -mmacosx-version-min=10.6 \ ++ -fno-pic -fno-PIC ++ ++AM_CFLAGS_PSO_X86_DARWIN = $(AM_CFLAGS_X86_DARWIN) $(AM_CFLAGS_PSO_BASE) ++AM_CCASFLAGS_X86_DARWIN = -arch i386 -g ++AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64 ++AM_CFLAGS_AMD64_DARWIN = $(WERROR) -arch x86_64 $(AM_CFLAGS_BASE) \ ++ -mmacosx-version-min=10.6 ++ ++AM_CFLAGS_PSO_AMD64_DARWIN = $(AM_CFLAGS_AMD64_DARWIN) $(AM_CFLAGS_PSO_BASE) ++AM_CCASFLAGS_AMD64_DARWIN = -arch x86_64 -g ++AM_FLAG_M3264_S390X_LINUX = @FLAG_M64@ ++AM_CFLAGS_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) -fomit-frame-pointer ++AM_CFLAGS_PSO_S390X_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE) ++AM_CCASFLAGS_S390X_LINUX = @FLAG_M64@ -g -mzarch -march=z900 ++AM_FLAG_M3264_MIPS32_LINUX = @FLAG_M32@ ++AM_CFLAGS_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) ++AM_CFLAGS_PSO_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) \ ++ $(AM_CFLAGS_PSO_BASE) ++ ++AM_CCASFLAGS_MIPS32_LINUX = @FLAG_M32@ -g ++AM_FLAG_M3264_NANOMIPS_LINUX = @FLAG_M32@ ++AM_CFLAGS_NANOMIPS_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) -mno-jump-table-opt ++AM_CFLAGS_PSO_NANOMIPS_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) \ ++ $(AM_CFLAGS_PSO_BASE) ++ ++AM_CCASFLAGS_NANOMIPS_LINUX = @FLAG_M32@ -g ++AM_FLAG_M3264_MIPS64_LINUX = @FLAG_M64@ ++AM_CFLAGS_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) ++AM_CFLAGS_PSO_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ ++ $(AM_CFLAGS_PSO_BASE) ++ ++AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g ++AM_FLAG_M3264_SW64_LINUX = @FLAG_M64@ ++AM_CFLAGS_SW64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) ++AM_CFLAGS_PSO_SW64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) \ ++ $(AM_CFLAGS_PSO_BASE) ++ ++AM_CCASFLAGS_SW64_LINUX = @FLAG_M64@ -g ++AM_FLAG_M3264_X86_SOLARIS = @FLAG_M32@ ++AM_CFLAGS_X86_SOLARIS = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY_2@ \ ++ $(AM_CFLAGS_BASE) -fomit-frame-pointer @SOLARIS_UNDEF_LARGESOURCE@ ++ ++AM_CFLAGS_PSO_X86_SOLARIS = @FLAG_M32@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE) ++AM_CCASFLAGS_X86_SOLARIS = @FLAG_M32@ -g -D_ASM ++AM_FLAG_M3264_AMD64_SOLARIS = @FLAG_M64@ ++AM_CFLAGS_AMD64_SOLARIS = @FLAG_M64@ \ ++ $(AM_CFLAGS_BASE) -fomit-frame-pointer ++ ++AM_CFLAGS_PSO_AMD64_SOLARIS = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE) ++AM_CCASFLAGS_AMD64_SOLARIS = @FLAG_M64@ -g -D_ASM ++ ++# Flags for the primary target. These must be used to build the ++# regtests and performance tests. In fact, these must be used to ++# build anything which is built only once on a dual-arch build. ++# ++AM_FLAG_M3264_PRI = $(AM_FLAG_M3264_@VGCONF_PLATFORM_PRI_CAPS@) ++AM_CPPFLAGS_PRI = $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) ++AM_CFLAGS_PRI = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) ++AM_CCASFLAGS_PRI = $(AM_CCASFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) ++@VGCONF_HAVE_PLATFORM_SEC_FALSE@AM_FLAG_M3264_SEC = ++@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_FLAG_M3264_SEC = $(AM_FLAG_M3264_@VGCONF_PLATFORM_SEC_CAPS@) ++ ++# Baseline link flags for making vgpreload shared objects. ++# ++PRELOAD_LDFLAGS_COMMON_LINUX = -nodefaultlibs -shared \ ++ -Wl,-z,interpose,-z,initfirst $(am__append_6) ++PRELOAD_LDFLAGS_COMMON_FREEBSD = -nodefaultlibs -shared -Wl,-z,interpose,-z,initfirst ++PRELOAD_LDFLAGS_COMMON_DARWIN = -dynamic -dynamiclib -all_load ++PRELOAD_LDFLAGS_COMMON_SOLARIS = -nodefaultlibs -shared \ ++ -Wl,-z,interpose,-z,initfirst $(am__append_5) ++PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ ++PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ ++PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ ++PRELOAD_LDFLAGS_PPC64BE_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ ++PRELOAD_LDFLAGS_PPC64LE_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ ++PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ ++PRELOAD_LDFLAGS_ARM64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ ++PRELOAD_LDFLAGS_X86_FREEBSD = $(PRELOAD_LDFLAGS_COMMON_FREEBSD) @FLAG_M32@ ++PRELOAD_LDFLAGS_AMD64_FREEBSD = $(PRELOAD_LDFLAGS_COMMON_FREEBSD) @FLAG_M64@ ++PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386 ++PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64 ++PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ ++PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ ++PRELOAD_LDFLAGS_NANOMIPS_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ ++PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ ++PRELOAD_LDFLAGS_SW64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ ++PRELOAD_LDFLAGS_X86_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M32@ ++PRELOAD_LDFLAGS_AMD64_SOLARIS = $(PRELOAD_LDFLAGS_COMMON_SOLARIS) @FLAG_M64@ ++AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ ++ -I$(top_srcdir)/coregrind -I$(top_builddir)/include \ ++ -I$(top_srcdir)/VEX/pub -I$(top_builddir)/VEX/pub \ ++ -DVGA_@VGCONF_ARCH_PRI@=1 -DVGO_@VGCONF_OS@=1 \ ++ -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \ ++ -DVGPV_@VGCONF_ARCH_PRI@_@VGCONF_OS@_@VGCONF_PLATVARIANT@=1 \ ++ $(am__append_7) $(am__append_8) ++ ++# Nb: Tools need to augment these flags with an arch-selection option, such ++# as $(AM_FLAG_M3264_PRI). ++AM_CFLAGS = -Winline -Wall -Wshadow -Wno-long-long -g \ ++ @FLAG_FNO_STACK_PROTECTOR@ $(am__append_9) $(am__append_10) \ ++ @FLAG_M64@ $(am__empty) ++AM_CXXFLAGS = -Winline -Wall -Wshadow -Wno-long-long -g \ ++ @FLAG_FNO_STACK_PROTECTOR@ $(am__append_11) @FLAG_M64@ ++# Include AM_CPPFLAGS in AM_CCASFLAGS to allow for older versions of ++# automake; see comments in Makefile.all.am for more detail. ++AM_CCASFLAGS = $(AM_CPPFLAGS) @FLAG_M64@ ++@VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(check_PROGRAMS) ++dist_noinst_SCRIPTS = filter_stderr ++EXTRA_DIST = \ ++ getcontext.stderr.exp getcontext.stdout.exp getcontext.vgtest \ ++ gethostname.stderr.exp gethostname.vgtest \ ++ prctl.stderr.exp prctl.vgtest \ ++ readahead.stderr.exp readahead.vgtest \ ++ sigsuspend.stderr.exp sigsuspend.vgtest ++ ++all: all-am ++ ++.SUFFIXES: ++.SUFFIXES: .c .o .obj ++$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/Makefile.all.am $(am__configure_deps) ++ @for dep in $?; do \ ++ case '$(am__configure_deps)' in \ ++ *$$dep*) \ ++ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \ ++ && { if test -f $@; then exit 0; else break; fi; }; \ ++ exit 1;; \ ++ esac; \ ++ done; \ ++ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign none/tests/sw64-linux/Makefile'; \ ++ $(am__cd) $(top_srcdir) && \ ++ $(AUTOMAKE) --foreign none/tests/sw64-linux/Makefile ++Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status ++ @case '$?' in \ ++ *config.status*) \ ++ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; 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+++ Illegal opcode at address 0x........ +++ at 0x........: __getcontext_x (getcontext.S:99) +++ by 0x........: main (getcontext.c:7) +diff --git a/none/tests/sw64-linux/getcontext.stderr.exp b/none/tests/sw64-linux/getcontext.stderr.exp +new file mode 100644 +index 000000000..e69de29bb +diff --git a/none/tests/sw64-linux/getcontext.stderr.out b/none/tests/sw64-linux/getcontext.stderr.out +new file mode 100644 +index 000000000..b9abbdc60 +--- /dev/null ++++ b/none/tests/sw64-linux/getcontext.stderr.out +@@ -0,0 +1,5 @@ ++ ++Process terminating with default action of signal 4 (SIGILL) ++ Illegal opcode at address 0x........ ++ at 0x........: __getcontext_x (getcontext.S:99) ++ by 0x........: main (getcontext.c:7) +diff --git a/none/tests/sw64-linux/getcontext.stdout.diff b/none/tests/sw64-linux/getcontext.stdout.diff +new file mode 100644 +index 000000000..988615f47 +--- /dev/null ++++ b/none/tests/sw64-linux/getcontext.stdout.diff +@@ -0,0 +1,5 @@ ++--- getcontext.stdout.exp 2024-12-11 09:09:14.959567395 +0000 +++++ getcontext.stdout.out 2025-01-15 16:06:41.222864265 +0000 ++@@ -1,2 +0,0 @@ ++-stack: (nil) ++-getcontext() ok +diff --git a/none/tests/sw64-linux/getcontext.stdout.exp b/none/tests/sw64-linux/getcontext.stdout.exp +new file mode 100644 +index 000000000..b3a889a33 +--- /dev/null ++++ b/none/tests/sw64-linux/getcontext.stdout.exp +@@ -0,0 +1,2 @@ ++stack: (nil) ++getcontext() ok +diff --git a/none/tests/sw64-linux/getcontext.stdout.out b/none/tests/sw64-linux/getcontext.stdout.out +new file mode 100644 +index 000000000..e69de29bb +diff --git a/none/tests/sw64-linux/getcontext.vgtest b/none/tests/sw64-linux/getcontext.vgtest +new file mode 100644 +index 000000000..44a7cba09 +--- /dev/null ++++ b/none/tests/sw64-linux/getcontext.vgtest +@@ -0,0 +1,3 @@ ++prog: getcontext ++# Test srlow SIMD instruction is properly handled. ++vgopts: -q +diff --git a/none/tests/sw64-linux/gethostname b/none/tests/sw64-linux/gethostname +new file mode 100755 +index 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b/none/tests/sw64-linux/gethostname.stderr.diff +new file mode 100644 +index 000000000..fe030076d +--- /dev/null ++++ b/none/tests/sw64-linux/gethostname.stderr.diff +@@ -0,0 +1,6 @@ ++--- gethostname.stderr.exp 2024-12-11 09:09:14.959567395 +0000 +++++ gethostname.stderr.out 2025-01-15 16:06:42.382864265 +0000 ++@@ -1,3 +1,2 @@ ++ ++-gethostname() is ok ++ +diff --git a/none/tests/sw64-linux/gethostname.stderr.exp b/none/tests/sw64-linux/gethostname.stderr.exp +new file mode 100644 +index 000000000..2e0ae69fb +--- /dev/null ++++ b/none/tests/sw64-linux/gethostname.stderr.exp +@@ -0,0 +1,3 @@ ++ ++gethostname() is ok ++ +diff --git a/none/tests/sw64-linux/gethostname.stderr.out b/none/tests/sw64-linux/gethostname.stderr.out +new file mode 100644 +index 000000000..139597f9c +--- /dev/null ++++ b/none/tests/sw64-linux/gethostname.stderr.out +@@ -0,0 +1,2 @@ ++ ++ +diff --git a/none/tests/sw64-linux/gethostname.vgtest b/none/tests/sw64-linux/gethostname.vgtest +new file mode 100644 +index 000000000..d0bf6c246 +--- /dev/null ++++ b/none/tests/sw64-linux/gethostname.vgtest +@@ -0,0 +1,4 @@ ++prog: gethostname ++# test gethostname() syscall ++vgopts: ++stderr_filter: filter_stderr +diff --git a/none/tests/sw64-linux/prctl b/none/tests/sw64-linux/prctl +new file mode 100755 +index 0000000000000000000000000000000000000000..b44f785e3b37e975ee00009cb01a28f196a8b117 +GIT binary patch +literal 15160 +zcmeHOeQX@Zb)UTt-mNH-M^TnY$sfy9b|}=mBV|RVWJ%_SD3P)(QncJUaH8e$ZjX1- +z@s7URlPKAanZ`gB*S2J!aAj9Tlp-kH)Q%G%2#mB2gd~3?{eazn3O6WR1x3@Q>4(xF +zts*J9{@%>I<=yg_w*M3;aF4is^FC+h&Ft>mnc;KeM-B!ILofuyrq_tN5Ed5UVJ&!P +zhb~CokT4$L=bX*)~XF}|uB#+ds@eWTwI?GISi +z$M^tb1dK_SVEXUfG?g!FN5ImK@tsmj2*zx840hDc|0%?@;*73ut+-s%{bQ_2k;v!f +z68Ut0K3AwL#mmJw<_EQ9BYrfthmJljzW8TP75*r{>$BSre(Hq+`O=DggXU(vgFze$y`A|#VM75N7Z@5K(np&EYeb7G=~@69XdPuK7xpcw+TfA{8o +z<6Dmi@oaTq`RVgQoOnAbzWH`Q%zpc;x1WrlOuX}i?}nZsZnW+;o*6U5rRo`D_t=YD +zF5ML3ne#m;N5v)R-t73#>gT&|SF2sW!0#4*H}SiH-_P+=bzklZh5gDhFgU79r6){ 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+zPr7a?H&;QH7UoyTTp?5RM00Z`=M+=;Hv@;uh+KmQ;Qx|EZ(!WAdW}W? +zABsgZ@<0jrsH+2#)xxiUkcX)?lk-Gi3EMQE5q$#H!Y&ZC_WWK3mS8F5UH$e4Ao&lh +z6>4=a@4VovpVv>-Dw5|;97Pe|t6u*(KLwWXfkJrwt2nVeXF$IOKECxld(LBlCGdKz +zqLdFV6Fz|-t$lL)Io}1A!0#Y#KkG3*2`ySnWt#J1U}5rbqu_uq73?_wq~& +zOu&*t-j(f{@k11}y>!X{$FyWA4X%gv{r3L?0r613ROP(voTV&u^A&-spZ=-l4R{)= +z!1nz7U@_Y>z6AmA-H;A{zg@D35`yHl;GaJm;D~+I>Rs$rl)qhmU0Uw-^T_hM+Wuep +z#?a3Fy8Ua|e|?)W__4NQpi +xu}|4A>4|HB9K?_34?mYp@VvQ;GQ(^_mBK#fTrca ++#include ++#include ++#include ++ ++int main(void) { ++ const char* name = "TEST-NAME-001"; ++ const int ret = prctl(PR_SET_NAME, name, NULL, NULL); ++ if (ret == 0) { ++ fprintf(stderr, "prctl() ok\n"); ++ } else { ++ fprintf(stderr, "prctl() failed, reason: %s\n", strerror(errno)); ++ } ++ return 0; ++} +diff --git a/none/tests/sw64-linux/prctl.stderr.exp b/none/tests/sw64-linux/prctl.stderr.exp +new file mode 100644 +index 000000000..eb14fcd75 +--- /dev/null ++++ b/none/tests/sw64-linux/prctl.stderr.exp +@@ -0,0 +1,3 @@ ++ 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All rights reserved. ++// Use of this source is governed by GNU General Public License ++// that can be found in the LICENSE file. ++ ++#define _GNU_SOURCE ++#include ++#include ++#include ++ ++int main() { ++ int fd = open("/etc/passwd", O_RDONLY); ++ if (fd < 0) { ++ fprintf(stderr, "Failed to open passwd file\n"); ++ return 1; ++ } ++ const size_t kCount = 4096; ++ const ssize_t n_read = readahead(fd, 0, kCount); ++ close(fd); ++ if (n_read == 0) { ++ fprintf(stderr, "read cache ok\n"); ++ } else { ++ fprintf(stderr, "Failed to pre-read file\n"); ++ } ++ return 0; ++} +diff --git a/none/tests/sw64-linux/readahead.stderr.exp b/none/tests/sw64-linux/readahead.stderr.exp +new file mode 100644 +index 000000000..7efd4e565 +--- /dev/null ++++ b/none/tests/sw64-linux/readahead.stderr.exp +@@ -0,0 +1,3 @@ ++ ++read cache ok ++ +diff --git a/none/tests/sw64-linux/readahead.vgtest b/none/tests/sw64-linux/readahead.vgtest +new file mode 100644 +index 000000000..3603acb6e +--- /dev/null ++++ b/none/tests/sw64-linux/readahead.vgtest +@@ -0,0 +1,4 @@ ++prog: readahead ++# test SYS_readahead is wrapped ++vgopts: ++stderr_filter: filter_stderr +\ No newline at end of file +diff --git a/none/tests/sw64-linux/sigsuspend b/none/tests/sw64-linux/sigsuspend +new file mode 100755 +index 0000000000000000000000000000000000000000..c7e928c30479674205ba60d3947d5740eb3bb50f +GIT binary patch +literal 15448 +zcmeHOdu$xXd7r%pZz+<;BPmOy6-i4+uB4_sl9HlOmL>5aN~A37WjR$UN6X{gl04`h +z%snL14~U4{hH)K>M%_eqRa7W~Kn0T6d7ucADlrnbi2H!sCItkyHI$~Wv?#!$X)8;P +z*xxrZ-*RtxG>ZOF^pE?b+i$+-%zQJu`_0bq((utk0mBds0kQ67qNc;bBHXV9H+SlS +zK2jN7yxV{Regu$E~g?NF9@ +ztX^>$3!yCON^Om8Qu5d)L+Uf0(e0SknC*xpJ4@SH+K%xp-7v=7Kk6I(j%t6vvOdNK +zAtPW+x&$ZwzLcW!YuXX8v}3$QY6-!Z?M}ju+W9|)m{vTc>su`@i@JY|H7U9?>GAGN +zswDHox?TU){5=wEHjqCiKGne?aY}y2%ge +z5Rg8HoiKHs375!tY@DH!Tr#@Aycke2E +z>R*dkCuS@)4|yDgJ$l?OmQv}QT`oE)QA|%3%f)FYmlC#(m?t4j6iRkBkA(@iu|=QQu@FMbxo6A)9N2`o$XqXT6gOX9~g|9+IoFT*xV=@XyEpP|QE=DRV0 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fprintf(stderr, "sigsuspend() returned.\n"); ++ ++ return 0; ++} +diff --git a/none/tests/sw64-linux/sigsuspend.stderr.exp b/none/tests/sw64-linux/sigsuspend.stderr.exp +new file mode 100644 +index 000000000..50ce17c6d +--- /dev/null ++++ b/none/tests/sw64-linux/sigsuspend.stderr.exp +@@ -0,0 +1,2 @@ ++signal raised. ++sigsuspend() returned. +diff --git a/none/tests/sw64-linux/sigsuspend.vgtest b/none/tests/sw64-linux/sigsuspend.vgtest +new file mode 100644 +index 000000000..5d76a2288 +--- /dev/null ++++ b/none/tests/sw64-linux/sigsuspend.vgtest +@@ -0,0 +1,2 @@ ++prog: sigsuspend ++vgopts: -q +diff --git a/none/tests/sw64-linux/vgcore.2854183 b/none/tests/sw64-linux/vgcore.2854183 +new file mode 100644 +index 0000000000000000000000000000000000000000..9ab21aa6edc7c4658c87b2b4ec0deddb5e42cf65 +GIT binary patch +literal 3645440 +zcmeFa3w%`7wLiYkJTj9I$na33f}EKoBtag*XKclsnF(-$5dyUqtCGn}gCK;5Exn3N +zLV&?eLh3WUS7Z>Vu}(;CANO)^O&v7YXl+S*+nV0`7!c$kNK}-`bAI1-_C7cqvGxD^ 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