From faba6faad263daf1bdc9d7c9a9845ff2baf35975 Mon Sep 17 00:00:00 2001 From: cao-jiaju <272503532@qq.com> Date: Mon, 26 May 2025 15:48:55 +0800 Subject: [PATCH] support hip12 instructions pipeline,core definition and cost model Signed-off-by: cao-jiaju <272503532@qq.com> --- SOURCES/gcc8-hip12-support.patch | 4416 ++++++++++++++++++++++++++++++ SPECS/gcc.spec | 9 +- 2 files changed, 4423 insertions(+), 2 deletions(-) create mode 100644 SOURCES/gcc8-hip12-support.patch diff --git a/SOURCES/gcc8-hip12-support.patch b/SOURCES/gcc8-hip12-support.patch new file mode 100644 index 0000000..22e9ba2 --- /dev/null +++ b/SOURCES/gcc8-hip12-support.patch @@ -0,0 +1,4416 @@ +diff --git a/gcc/ChangeLog b/gcc/ChangeLog +index b9c7f4290..3915d4de3 100644 +--- a/gcc/ChangeLog ++++ b/gcc/ChangeLog +@@ -4988,6 +4988,32 @@ + * config/i386/i386.md (anddi_1 to andsi_1_zext splitter): + Avoid calling gen_lowpart with CONST operand. + ++2019-05-22 Matthew Malcomson ++ ++ * common/config/aarch64/aarch64-common.c ++ (struct aarch64_option_extension, struct processor_name_to_arch, ++ struct arch_to_arch_name, aarch64_parse_extension, opt_ext_cmp, ++ aarch64_contains_opt, ++ aarch64_get_extension_string_for_isa_flags): Change type of ++ variables storing flags to uint64_t. ++ * config/aarch64/aarch64-option-extensions.def (sve2, sve2-sm4, ++ sve2-aes, sve2-sha3, bitperm): New optional SVE2 extension flags. ++ * config/aarch64/aarch64.c (struct processor, ++ aarch64_parse_arch, aarch64_parse_cpu, aarch64_validate_mcpu, ++ aarch64_validate_march, aarch64_override_options, ++ aarch64_option_print, aarch64_handle_attr_isa_flags, ++ aarch64_declare_function_name, aarch64_start_file): Make flag ++ variables uint64_t. ++ * config/aarch64/aarch64.h (AARCH64_FL_SVE2, AARCH64_FL_SVE2_AES, ++ AARCH64_FL_SVE2_SM4, AARCH64_FL_SVE2_SHA3, ++ AARCH64_FL_SVE2_BITPERM): New macro feature flags. ++ * config/aarch64/aarch64.opt (aarch64_isa_flags): Make uint64_t. ++ * config/aarch64/driver-aarch64.c ++ (struct aarch64_arch_extension, struct aarch64_core_data, ++ struct aarch64_arch_driver_info, host_detect_local_cpu): Make ++ flag variables uint64_t. ++ * doc/invoke.texi: Add documentation for new arguments. ++ + 2019-05-21 Sebastian Huber + + Backported from mainline +diff --git a/gcc/Makefile.in b/gcc/Makefile.in +index a861df33c..8e2d91508 100644 +--- a/gcc/Makefile.in ++++ b/gcc/Makefile.in +@@ -1615,13 +1615,13 @@ OBJS-libcommon = diagnostic.o diagnostic-color.o diagnostic-show-locus.o \ + pretty-print.o intl.o \ + sbitmap.o \ + vec.o input.o version.o hash-table.o ggc-none.o memory-block.o \ +- selftest.o selftest-diagnostic.o ++ ai4c-infer.o ai-optimizer.o selftest.o selftest-diagnostic.o + + # Objects in libcommon-target.a, used by drivers and by the core + # compiler and containing target-dependent code. + OBJS-libcommon-target = $(common_out_object_file) prefix.o params.o \ + opts.o opts-common.o options.o vec.o hooks.o common/common-targhooks.o \ +- hash-table.o file-find.o spellcheck.o selftest.o ++ hash-table.o file-find.o spellcheck.o ai4c-infer.o ai-optimizer.o selftest.o + + # This lists all host objects for the front ends. + ALL_HOST_FRONTEND_OBJS = $(foreach v,$(CONFIG_LANGUAGES),$($(v)_OBJS)) +@@ -2146,7 +2146,7 @@ gcc-nm.c: gcc-ar.c + cp $^ $@ + + COLLECT2_OBJS = collect2.o collect2-aix.o tlink.o vec.o ggc-none.o \ +- collect-utils.o file-find.o hash-table.o selftest.o ++ collect-utils.o file-find.o hash-table.o ai4c-infer.o ai-optimizer.o selftest.o + COLLECT2_LIBS = @COLLECT2_LIBS@ + collect2$(exeext): $(COLLECT2_OBJS) $(LIBDEPS) + # Don't try modifying collect2 (aka ld) in place--it might be linking this. +@@ -3575,6 +3575,8 @@ install-plugin: installdirs lang.install-plugin s-header-vars install-gengtype + + # Install the compiler executables built during cross compilation. + install-common: native lang.install-common installdirs ++ rm -f $(DESTDIR)$(libexecdir)/gcc/*.fdata ++ cp $(srcdir)/*.fdata $(DESTDIR)$(libexecdir)/gcc/ + for file in $(COMPILERS); do \ + if [ -f $$file ] ; then \ + rm -f $(DESTDIR)$(libexecsubdir)/$$file; \ +diff --git a/gcc/ai-optimizer.c b/gcc/ai-optimizer.c +new file mode 100644 +index 000000000..4fad56c1b +--- /dev/null ++++ b/gcc/ai-optimizer.c +@@ -0,0 +1,425 @@ ++/* Lightweight AI Inference Framework. ++ Copyright (C) 2024-2024 Free Software Foundation, Inc. ++This file is part of GCC. ++GCC is free software; you can redistribute it and/or modify it under ++the terms of the GNU General Public License as published by the Free ++Software Foundation; either version 3, or (at your option) any later ++version. ++GCC is distributed in the hope that it will be useful, but WITHOUT ANY ++WARRANTY; without even the implied warranty of MERCHANTABILITY or ++FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++for more details. ++ ++You should have received a copy of the GNU General Public License ++along with GCC; see the file COPYING3. If not see ++. */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "config.h" ++#include "system.h" ++#include "ai4c-infer.h" ++ ++#define M_OPTION_SIZE 11 ++#define M_MODE_SIZE 6 ++#define NATIVE_TUNE_SIZE 128 ++#define CATS_STRINGS_ROW 35 ++#define CATS_STRINGS_COL 65 ++#define CATS_STRINGS1_ROW 10 ++#define CATS_STRINGS1_COL 65 ++#define OFFSET_ROW 6 ++#define SCALE_ROW 6 ++#define UNITY_ROW 1 ++#define COEFFICIENT_ROW 366 ++#define COEFFICIENT_COL 10 ++#define COEFFICIENT1_ROW 10 ++#define COEFFICIENT1_COL 1 ++#define INTERCEPTS_ROW 10 ++#define INTERCEPTS1_ROW 1 ++ ++/* Intermediate computation results from the ONNX model. */ ++static char cats_strings[CATS_STRINGS_ROW][CATS_STRINGS_COL]; ++static char cats_strings1[CATS_STRINGS1_ROW][CATS_STRINGS1_COL]; ++static float offset[OFFSET_ROW]; ++static float scale[SCALE_ROW]; ++static float unity[UNITY_ROW]; ++static float coefficient[COEFFICIENT_ROW][COEFFICIENT_COL]; ++static float coefficient1[COEFFICIENT1_ROW][COEFFICIENT1_COL]; ++static float intercepts[INTERCEPTS_ROW]; ++static float intercepts1[INTERCEPTS1_ROW]; ++ ++/* Return an integer that represents the comparison result of the ++ two strings. */ ++ ++static int ++compare_strings (const void *a, const void *b) ++{ ++ const char *str_a = *(const char **)a; ++ const char *str_b = *(const char **)b; ++ ++ int len = strlen (str_a) < strlen (str_b) ? strlen (str_a) : strlen (str_b); ++ for (int i = 0; i < len; i++) ++ { ++ char c1 = str_a[i]; ++ char c2 = str_b[i]; ++ if (ISUPPER (c1) && !ISUPPER (c2)) ++ return 0; ++ else if (!ISUPPER (c1) && ISUPPER (c2)) ++ return 1; ++ else if (c1 != c2) ++ return c1 < c2; ++ } ++ return strlen (str_a) > strlen (str_b); ++} ++ ++/* Return the substring before the first underscore ('_') in the input ++ string. */ ++ ++static void ++truncate_prefix (const char *str, char *result) ++{ ++ const char *underscore_pos = strchr (str, '_'); ++ if (underscore_pos == NULL) ++ { ++ strcpy (result, str); ++ return; ++ } ++ ++ size_t len = underscore_pos - str; ++ strncpy (result, str, len + 1); ++ result[len + 1] = '\0'; ++} ++ ++ ++static void ++preprocess (int argc1, const char **argv1, const char *mops, ++ int argc2, int64_t *argv2, char (*in_options)[1024], ++ int64_t *in_modes) ++{ ++ strcpy (in_options[0], mops); ++ ++ const char *output_option = "-o"; ++ const char *marco_prefix = "-D"; ++ const char *needle = "--param"; ++ const char *flag_prefix = "-"; ++ const char *default_option = "-default-option"; ++ const int default_int_val = 0; ++ int m_size = 0; ++ for (int i = 0; i < argc1; i++) ++ { ++ if (strncmp (argv1[i], marco_prefix, 2) == 0) ++ m_size ++; ++ } ++ ++ char *m_options[m_size]; ++ char output_file[1024]; ++ int m_index = 0; ++ for (int i = 0; i < argc1; i++) ++ { ++ if (strncmp (argv1[i], marco_prefix, 2) == 0) ++ { ++ m_options[m_index] = (char *)argv1[i]; ++ m_index ++; ++ } ++ if (strcmp (argv1[i], output_option) == 0) ++ truncate_prefix (argv1[i + 1], output_file); ++ } ++ ++ strcpy (in_options[1], output_file); ++ int in_options_size = 2; ++ qsort (m_options, m_size, sizeof (m_options[0]), compare_strings); ++ for (int i = 0; i < m_size && in_options_size < M_OPTION_SIZE; i++) ++ { ++ strcpy (in_options[in_options_size], m_options[i]); ++ in_options_size ++; ++ } ++ ++ for (int i = 0; i < argc1 && in_options_size < M_OPTION_SIZE; i++) ++ { ++ if (strncmp (argv1[i], marco_prefix, 2) != 0 ++ && strcmp (argv1[i], output_option) != 0 ++ && strncmp (argv1[i], needle, 7) != 0 ++ && strncmp (argv1[i], flag_prefix, 1) == 0) ++ { ++ strcpy (in_options[in_options_size], argv1[i]); ++ in_options_size ++; ++ } ++ } ++ ++ while (in_options_size < M_OPTION_SIZE) ++ { ++ strcpy (in_options[in_options_size], default_option); ++ in_options_size ++; ++ } ++ ++ /* Use sha256 to encrypt the input. */ ++ char hash[65]; ++ char input[64]; ++ for (int i = 0; i < M_OPTION_SIZE; i++) ++ { ++ execute_sha256 (in_options[i], hash, sizeof (hash)); ++ strcpy (in_options[i], hash); ++ } ++ ++ for (int i = 0; i < argc2 && i < M_MODE_SIZE; i++) ++ { ++ if (i < argc2) ++ in_modes[i] = argv2[i]; ++ else ++ in_modes[i] = default_int_val; ++ } ++} ++ ++/* To read model parameter information from optimizer.fdata and store it into ++ the appropriate arrays. */ ++ ++static void ++fill_node (const char *file_name) ++{ ++ FILE *file = fopen (file_name, "rb"); ++ ++ if (!file) ++ { ++ perror ("Can not open file."); ++ return; ++ } ++ ++ /* Read cats_strings from optimizer.fdata. */ ++ char hex_string[2]; ++ for (int i = 0; i < CATS_STRINGS_ROW; i++) ++ { ++ for (int j = 0; j < CATS_STRINGS_COL - 1; j++) ++ { ++ if (fscanf (file, "%2s", hex_string) != 1) ++ { ++ perror ("Can not read cats_strings from optimizer.fdata."); ++ return; ++ } ++ cats_strings[i][j] = (unsigned char) strtol(hex_string, NULL, 16); ++ } ++ cats_strings[i][CATS_STRINGS_COL - 1] = '\0'; ++ } ++ ++ /* Read cats_strings1 from optimizer.fdata. */ ++ for (int i = 0; i < CATS_STRINGS1_ROW; i++) ++ { ++ for (int j = 0; j < CATS_STRINGS1_COL - 1; j++) ++ { ++ if (fscanf (file, "%2s", hex_string) != 1) ++ { ++ perror ("Can not read cats_strings1 from optimizer.fdata."); ++ return; ++ } ++ cats_strings1[i][j] = (unsigned char) strtol(hex_string, NULL, 16); ++ } ++ cats_strings1[i][CATS_STRINGS1_COL - 1] = '\0'; ++ } ++ ++ /* Read offset from optimizer.fdata. */ ++ for (int i = 0; i < OFFSET_ROW; i++) ++ { ++ float result = read_float_from_file (file); ++ offset[i] = result; ++ } ++ ++ ++ /* Read scale from optimizer.fdata. */ ++ for (int i = 0; i < SCALE_ROW; i++) ++ { ++ float result = read_float_from_file (file); ++ scale[i] = result; ++ } ++ ++ /* Read unity from optimizer.fdata. */ ++ for (int i = 0; i < UNITY_ROW; i++) ++ { ++ float result = read_float_from_file (file); ++ unity[i] = result; ++ } ++ ++ /* Read coefficient from optimizer.fdata. */ ++ for (int i = 0; i < COEFFICIENT_ROW; i++) ++ for (int j = 0; j < COEFFICIENT_COL; j++) ++ { ++ float result = read_float_from_file (file); ++ coefficient[i][j] = result; ++ } ++ ++ /* Read coefficient1 from optimizer.fdata. */ ++ for (int i = 0; i < COEFFICIENT1_ROW; i++) ++ for (int j = 0; j < COEFFICIENT1_COL; j++) ++ { ++ float result = read_float_from_file (file); ++ coefficient1[i][j] = result; ++ } ++ ++ /* Read intercepts from optimizer.fdata. */ ++ for (int i = 0; i < INTERCEPTS_ROW; i++) ++ { ++ float result = read_float_from_file (file); ++ intercepts[i] = result; ++ } ++ ++ /* Read intercepts1 from optimizer.fdata. */ ++ for (int i = 0; i < INTERCEPTS1_ROW; i++) ++ { ++ float result = read_float_from_file (file); ++ intercepts1[i] = result; ++ } ++ ++ fclose (file); ++ return; ++} ++ ++/* The process of model inference. */ ++ ++static int ++graph_infer (int argc1, const char **argv1, const char *mops, ++ int argc2, int64_t *argv2) ++{ ++ char gcc_exec_prefix[512]; ++ ssize_t len = readlink ("/proc/self/exe", gcc_exec_prefix, ++ sizeof (gcc_exec_prefix) - 1); ++ if (len == -1) ++ return 0; ++ ++ char native_file[512]; ++ strncpy (native_file, gcc_exec_prefix, sizeof (native_file) - 1); ++ const char *target = "bin/gcc"; ++ const char *target_cc1 = "cc1"; ++ const char *target_gpp = "bin/g++"; ++ const char *target_cc1plus = "cc1plus"; ++ const char *target_gfortran = "bin/gfortran"; ++ const char *target_f951 = "f951"; ++ const char *replacement = "../libexec/gcc/optimizer.fdata"; ++ const char *replacement_front_end = "../../optimizer.fdata"; ++ ++ /* Replace the part of the current executable file path after the last slash ++ to locate the model file. */ ++ if (strstr (native_file, target) != NULL || ++ strstr (native_file, target_gpp) != NULL || ++ strstr (native_file, target_gfortran) != NULL) ++ { ++ char *last_slash = strrchr (native_file, '/'); ++ if (last_slash) ++ { ++ size_t prefix_len = last_slash - native_file + 1; ++ native_file[prefix_len] = '\0'; ++ strncat (native_file, replacement, sizeof (native_file) - ++ strlen (native_file) - 1); ++ } ++ } ++ else if (strstr (native_file, target_cc1) != NULL || ++ strstr (native_file, target_cc1plus) != NULL || ++ strstr (native_file, target_f951) != NULL) ++ { ++ char *last_slash = strrchr (native_file, '/'); ++ if (last_slash != NULL) ++ { ++ size_t prefix_len = last_slash - native_file + 1; ++ native_file[prefix_len] = '\0'; ++ strncat (native_file, replacement_front_end, sizeof (native_file) - ++ strlen (native_file) - 1); ++ } ++ } ++ if (access (native_file, F_OK) == 0) ++ fill_node (native_file); ++ else ++ return 0; ++ ++ static int64_t in_modes[M_MODE_SIZE]; ++ static char in_options[M_OPTION_SIZE][1024]; ++ ++ preprocess (argc1, argv1, mops, argc2, argv2, in_options, in_modes); ++ ++ /* concat_result and encoder_out are intermediate computation results from ++ the ONNX model. concat_result is a 1 × 18 matrix, and encoder_out is a ++ 1 × 12 matrix. */ ++ ++ const int concat_out_size = 360; ++ float concat_result[concat_out_size]; ++ const int encoder_out_size = 35; ++ const int encoder_last_size = 10; ++ int concat_size = 0; ++ const int size = encoder_out_size; ++ ++ for (int i = 1; i < M_OPTION_SIZE; i++) ++ { ++ float encoder_out[size]; ++ one_hot_encoder (in_options[i], cats_strings, encoder_out, size); ++ line_concat (encoder_out, size, concat_result, concat_size); ++ concat_size += size; ++ } ++ ++ float encoder_out2[encoder_last_size]; ++ one_hot_encoder (in_options[0], cats_strings1, encoder_out2, ++ encoder_last_size); ++ line_concat (encoder_out2, encoder_last_size, concat_result, concat_size); ++ concat_size += encoder_last_size; ++ ++ float variable[M_MODE_SIZE]; ++ imputer (in_modes, M_MODE_SIZE, variable); ++ float variable1[M_MODE_SIZE]; ++ scaler (variable, offset, scale, M_MODE_SIZE, variable1); ++ ++ float transformed_column[concat_out_size + M_MODE_SIZE]; ++ /* line_concat is used to stro*/ ++ line_concat (variable1, M_MODE_SIZE, transformed_column, 0); ++ line_concat (concat_result, concat_out_size, transformed_column, 6); ++ ++ /* This requires performing matrix multiplication between a 1 × 356 matrix ++ and an 356 × 10 matrix */ ++ ++ const int m = 1, k = 366, n = 10; ++ float mul_result[n]; ++ matmul (transformed_column, coefficient[0], m, k, n, mul_result); ++ ++ float add_result[n]; ++ add (mul_result, intercepts, n, add_result); ++ ++ float next_activations[n]; ++ relu (add_result, n, next_activations); ++ ++ /* This requires performing matrix multiplication between a 1 × 10 matrix ++ and an 10 × 1 matrix */ ++ ++ const int m2 = 1, k2 = 10, n2 = 1; ++ float mul_result1[n2]; ++ matmul (next_activations, coefficient1[0], m2, k2, n2, mul_result1); ++ ++ float add_result1[n2]; ++ add (mul_result1, intercepts1, n2, add_result1); ++ ++ float out_activations_result[n2]; ++ sigmoid (add_result1, n2, out_activations_result); ++ ++ float negative_class_proba[n2]; ++ sub (unity, out_activations_result, n2, negative_class_proba); ++ const int prob_size = n2 + n2; ++ float probabilities[prob_size]; ++ line_concat (negative_class_proba, n2, probabilities, 0); ++ line_concat (out_activations_result, n2, probabilities, n2); ++ ++ int argmax_output = argmax (probabilities, prob_size); ++ return argmax_output; ++} ++ ++int ++get_optimize_decision_from_optimizer (int argc, const char **argv, ++ const char *mops, int argc2, ++ int64_t *argv2) ++{ ++ int model_pred = graph_infer (argc, argv, mops, argc2, argv2); ++ if (model_pred == 1) ++ { ++ putenv ("AI_INFER_LEVEL=1"); ++ } ++ return model_pred; ++} +\ No newline at end of file +diff --git a/gcc/ai4c-infer.c b/gcc/ai4c-infer.c +new file mode 100644 +index 000000000..6ea564620 +--- /dev/null ++++ b/gcc/ai4c-infer.c +@@ -0,0 +1,184 @@ ++/* Lightweight AI Inference Framework. ++ Copyright (C) 2024-2024 Free Software Foundation, Inc. ++This file is part of GCC. ++GCC is free software; you can redistribute it and/or modify it under ++the terms of the GNU General Public License as published by the Free ++Software Foundation; either version 3, or (at your option) any later ++version. ++GCC is distributed in the hope that it will be useful, but WITHOUT ANY ++WARRANTY; without even the implied warranty of MERCHANTABILITY or ++FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++for more details. ++ ++You should have received a copy of the GNU General Public License ++along with GCC; see the file COPYING3. If not see ++. */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "ai4c-infer.h" ++#include "config.h" ++#include "system.h" ++ ++/* Read float from onnx.fdata. */ ++ ++float ++read_float_from_file (FILE* file) ++{ ++ char hex_float[8]; ++ float result; ++ ++ if (!file) ++ { ++ perror ("Can not open file."); ++ return result; ++ } ++ ++ if (fscanf (file, "%8s", hex_float) != 1) ++ { ++ perror ("Can not read hex from onnx.fdata."); ++ return result; ++ } ++ ++ unsigned char bytes[4]; ++ for (int i = 0; i < 4; i++) ++ { ++ sscanf(hex_float + 2 * i, "%2hhx", &bytes[i]); ++ } ++ ++ memcpy(&result, bytes, sizeof(float)); ++ return result; ++} ++ ++void ++matmul (const float *lhs, const float *rhs, int m, int k, int n, float *out) ++{ ++ for (int i = 0; i < m; i++) ++ { ++ for (int j = 0; j < n; j++) ++ { ++ out[i * n + j] = 0.0f; ++ for (int p = 0; p < k; p++) ++ { ++ out[i * n + j] += lhs[i * k + p] * rhs[p * n + j]; ++ } ++ } ++ } ++} ++ ++void ++add (const float *lhs, const float *rhs, int length, float *out) ++{ ++ for (int i = 0; i < length; i++) ++ { ++ out[i] = lhs[i] + rhs[i]; ++ } ++} ++ ++void ++sub (const float *lhs, const float *rhs, int length, float *out) ++{ ++ for (int i = 0; i < length; i++) ++ { ++ out[i] = lhs[i] - rhs[i]; ++ } ++} ++ ++void ++sigmoid (const float *in, int length, float *out) ++{ ++ for (int i = 0; i < length; i++) ++ { ++ out[i] = 1.0f / (1.0f + expf (-in[i])); ++ } ++} ++ ++void ++relu (const float *data, int length, float *out) ++{ ++ for (int i = 0; i < length; i++) ++ { ++ if (data[i] < 0) ++ { ++ out[i] = 0; ++ } ++ else ++ { ++ out[i] = data[i]; ++ } ++ } ++} ++ ++void ++line_concat (const float *in, int in_size, float *out, int out_size) ++{ ++ for (int i = 0; i < in_size; i++) ++ out[out_size + i] = in[i]; ++} ++ ++void ++one_hot_encoder (const char *in, const char (*cats)[65], float *out, ++ int out_size) ++{ ++ for (int i = 0; i < out_size; i++) ++ { ++ if (i < out_size && strcmp (cats[i], in) == 0) ++ { ++ out[i] = 1.0f; ++ } ++ else ++ { ++ out[i] = 0.0f; ++ } ++ } ++} ++ ++void ++imputer (const int64_t *in, int size, float *out) ++{ ++ for (int i = 0; i < size; i++) ++ out[i] = in[i] * 1.0f; ++} ++ ++void ++scaler (const float *in, const float *offset, const float *scale, int size, ++ float *out) ++{ ++ for (int i = 0; i < size; i++) ++ out[i] = (in[i] - offset[i]) * scale[i]; ++} ++ ++int ++argmax (const float *in, int in_size) ++{ ++ int out_idx = 0; ++ for (int i = 0; i < in_size; i++) ++ { ++ if (in[i] > in[out_idx]) ++ out_idx = i; ++ } ++ return out_idx; ++} ++ ++void ++execute_sha256 (const char *input, char *output, size_t output_size) ++{ ++ char command[256]; ++ snprintf (command, sizeof (command), "echo -n \"%s\" | sha256sum", input); ++ ++ FILE *pipe = popen (command, "r"); ++ if (pipe == NULL) ++ { ++ perror ("Failed to run command."); ++ return; ++ } ++ ++ fgets (output, output_size, pipe); ++ pclose (pipe); ++} +\ No newline at end of file +diff --git a/gcc/ai4c-infer.h b/gcc/ai4c-infer.h +index fde0a3d90..6033efe55 100644 +--- a/gcc/ai4c-infer.h ++++ b/gcc/ai4c-infer.h +@@ -1,1892 +1,42 @@ +-/* AI Model Inference. +- Copyright (C) 2024-2024 Free Software Foundation, Inc. +- +-This file is part of GCC. +- +-GCC is free software; you can redistribute it and/or modify it under +-the terms of the GNU General Public License as published by the Free +-Software Foundation; either version 3, or (at your option) any later +-version. +- +-GCC is distributed in the hope that it will be useful, but WITHOUT ANY +-WARRANTY; without even the implied warranty of MERCHANTABILITY or +-FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +- for more details. +- +-You should have received a copy of the GNU General Public License +-along with GCC; see the file COPYING3. If not see +-. */ +- +-#ifndef AI4C_INFER +-#define AI4C_INFER +- +-#include "system.h" +-#include +- +-#ifndef _cbmc_ +-#define __CPROVER_assume(...) do {} while (0) +-#endif +- +-#define FN_ static inline __attribute__((const)) +- +-#define M_OPTION_SIZE (11) +-#define M_MODE_SIZE (6) +- +-/* sha256 */ +-typedef struct +-{ +- uint8_t buf[64]; +- uint32_t hash[8]; +- uint32_t bits[2]; +- uint32_t len; +- uint32_t rfu__; +- uint32_t W[64]; +-} sha256_context; +- +-static const uint32_t K[64] = { +- 0x428a2f98, 0x71374491, 0xb5c0fbcf, 0xe9b5dba5, +- 0x3956c25b, 0x59f111f1, 0x923f82a4, 0xab1c5ed5, +- 0xd807aa98, 0x12835b01, 0x243185be, 0x550c7dc3, +- 0x72be5d74, 0x80deb1fe, 0x9bdc06a7, 0xc19bf174, +- 0xe49b69c1, 0xefbe4786, 0x0fc19dc6, 0x240ca1cc, +- 0x2de92c6f, 0x4a7484aa, 0x5cb0a9dc, 0x76f988da, +- 0x983e5152, 0xa831c66d, 0xb00327c8, 0xbf597fc7, +- 0xc6e00bf3, 0xd5a79147, 0x06ca6351, 0x14292967, +- 0x27b70a85, 0x2e1b2138, 0x4d2c6dfc, 0x53380d13, +- 0x650a7354, 0x766a0abb, 0x81c2c92e, 0x92722c85, +- 0xa2bfe8a1, 0xa81a664b, 0xc24b8b70, 0xc76c51a3, +- 0xd192e819, 0xd6990624, 0xf40e3585, 0x106aa070, +- 0x19a4c116, 0x1e376c08, 0x2748774c, 0x34b0bcb5, +- 0x391c0cb3, 0x4ed8aa4a, 0x5b9cca4f, 0x682e6ff3, +- 0x748f82ee, 0x78a5636f, 0x84c87814, 0x8cc70208, +- 0x90befffa, 0xa4506ceb, 0xbef9a3f7, 0xc67178f2 +-}; +- +-FN_ +-uint8_t _shb (uint32_t x, uint32_t n) +-{ +- return ((x >> (n & 31)) & 0xff); +-} // _shb +- +-FN_ +-uint32_t _shw (uint32_t x, uint32_t n) +-{ +- return ((x << (n & 31)) & 0xffffffff); +-} // _shw +- +-FN_ +-uint32_t _r (uint32_t x, uint8_t n) +-{ +- return ((x >> n) | _shw (x, 32 - n)); +-} // _r +- +-FN_ +-uint32_t _Ch (uint32_t x, uint32_t y, uint32_t z) +-{ +- return ((x & y) ^ ((~x) & z)); +-} // _Ch +- +-FN_ +-uint32_t _Ma (uint32_t x, uint32_t y, uint32_t z) +-{ +- return ((x & y) ^ (x & z) ^ (y & z)); +-} // _Ma +- +-FN_ +-uint32_t _S0 (uint32_t x) +-{ +- return (_r (x, 2) ^ _r (x, 13) ^ _r (x, 22)); +-} // _S0 +- +-FN_ +-uint32_t _S1 (uint32_t x) +-{ +- return (_r (x, 6) ^ _r (x, 11) ^ _r (x, 25)); +-} // _S1 +- +-FN_ +-uint32_t _G0 (uint32_t x) +-{ +- return (_r (x, 7) ^ _r (x, 18) ^ (x >> 3)); +-} // _G0 +- +-FN_ +-uint32_t _G1 (uint32_t x) +-{ +- return (_r (x, 17) ^ _r (x, 19) ^ (x >> 10)); +-} // _G1 +- +-FN_ +-uint32_t _word (uint8_t *c) +-{ +- return (_shw (c[0], 24) | _shw (c[1], 16) | _shw (c[2], 8) | (c[3])); +-} // _word +- +-static void +-_addbits (sha256_context *ctx, uint32_t n) +-{ +- __CPROVER_assume (__CPROVER_DYNAMIC_OBJECT (ctx)); +- +- if (ctx->bits[0] > (0xffffffff - n)) +- { +- ctx->bits[1] = (ctx->bits[1] + 1) & 0xFFFFFFFF; +- } +- ctx->bits[0] = (ctx->bits[0] + n) & 0xFFFFFFFF; +-} // _addbits +- +-static void +-_hash (sha256_context *ctx) +-{ +- __CPROVER_assume (__CPROVER_DYNAMIC_OBJECT (ctx)); +- +- register uint32_t a, b, c, d, e, f, g, h; +- uint32_t t[2]; +- +- a = ctx->hash[0]; +- b = ctx->hash[1]; +- c = ctx->hash[2]; +- d = ctx->hash[3]; +- e = ctx->hash[4]; +- f = ctx->hash[5]; +- g = ctx->hash[6]; +- h = ctx->hash[7]; +- +- for (uint32_t i = 0; i < 64; i++) +- { +- if (i < 16) +- { +- ctx->W[i] = _word (&ctx->buf[_shw (i, 2)]); +- } +- else +- { +- ctx->W[i] = _G1 (ctx->W[i - 2]) + ctx->W[i - 7] +- + _G0 (ctx->W[i - 15]) + ctx->W[i - 16]; +- } +- +- t[0] = h + _S1 (e) + _Ch (e, f, g) + K[i] + ctx->W[i]; +- t[1] = _S0 (a) + _Ma (a, b, c); +- h = g; +- g = f; +- f = e; +- e = d + t[0]; +- d = c; +- c = b; +- b = a; +- a = t[0] + t[1]; +- } +- +- ctx->hash[0] += a; +- ctx->hash[1] += b; +- ctx->hash[2] += c; +- ctx->hash[3] += d; +- ctx->hash[4] += e; +- ctx->hash[5] += f; +- ctx->hash[6] += g; +- ctx->hash[7] += h; +-} // _hash +- +-void +-sha256_init (sha256_context *ctx) +-{ +- if (ctx != NULL) +- { +- ctx->bits[0] = ctx->bits[1] = ctx->len = 0; +- ctx->hash[0] = 0x6a09e667; +- ctx->hash[1] = 0xbb67ae85; +- ctx->hash[2] = 0x3c6ef372; +- ctx->hash[3] = 0xa54ff53a; +- ctx->hash[4] = 0x510e527f; +- ctx->hash[5] = 0x9b05688c; +- ctx->hash[6] = 0x1f83d9ab; +- ctx->hash[7] = 0x5be0cd19; +- } +-} // sha256_init +- +-void +-sha256_hash (sha256_context *ctx, const void *data, size_t len) +-{ +- const uint8_t *bytes = (const uint8_t *)data; +- +- if ((ctx != NULL) && (bytes != NULL) && (ctx->len < sizeof (ctx->buf))) +- { +- __CPROVER_assume (__CPROVER_DYNAMIC_OBJECT (bytes)); +- __CPROVER_assume (__CPROVER_DYNAMIC_OBJECT (ctx)); +- for (size_t i = 0; i < len; i++) +- { +- ctx->buf[ctx->len++] = bytes[i]; +- if (ctx->len == sizeof (ctx->buf)) +- { +- _hash (ctx); +- _addbits (ctx, sizeof (ctx->buf) * 8); +- ctx->len = 0; +- } +- } +- } +-} // sha256_hash +- +-void +-sha256_done (sha256_context *ctx, uint8_t *hash) +-{ +- register uint32_t i, j; +- +- if (ctx != NULL) +- { +- j = ctx->len % sizeof (ctx->buf); +- ctx->buf[j] = 0x80; +- for (i = j + 1; i < sizeof (ctx->buf); i++) +- { +- ctx->buf[i] = 0x00; +- } +- +- if (ctx->len > 55) +- { +- _hash (ctx); +- for (j = 0; j < sizeof (ctx->buf); j++) +- { +- ctx->buf[j] = 0x00; +- } +- } +- +- _addbits (ctx, ctx->len * 8); +- ctx->buf[63] = _shb (ctx->bits[0], 0); +- ctx->buf[62] = _shb (ctx->bits[0], 8); +- ctx->buf[61] = _shb (ctx->bits[0], 16); +- ctx->buf[60] = _shb (ctx->bits[0], 24); +- ctx->buf[59] = _shb (ctx->bits[1], 0); +- ctx->buf[58] = _shb (ctx->bits[1], 8); +- ctx->buf[57] = _shb (ctx->bits[1], 16); +- ctx->buf[56] = _shb (ctx->bits[1], 24); +- _hash (ctx); +- +- if (hash != NULL) +- { +- for (i = 0, j = 24; i < 4; i++, j -= 8) +- { +- hash[i + 0] = _shb (ctx->hash[0], j); +- hash[i + 4] = _shb (ctx->hash[1], j); +- hash[i + 8] = _shb (ctx->hash[2], j); +- hash[i + 12] = _shb (ctx->hash[3], j); +- hash[i + 16] = _shb (ctx->hash[4], j); +- hash[i + 20] = _shb (ctx->hash[5], j); +- hash[i + 24] = _shb (ctx->hash[6], j); +- hash[i + 28] = _shb (ctx->hash[7], j); +- } +- } +- } +-} // sha256_done +- +-void +-sha256 (const void *data, size_t len, uint8_t *hash) +-{ +- sha256_context ctx; +- +- sha256_init (&ctx); +- sha256_hash (&ctx, data, len); +- sha256_done (&ctx, hash); +-} +-/* sha256 */ ++/* Lightweight AI Inference Framework. + +-static float coefficient[356][10] = { +- { -0.001202732790261507, 0.20421256124973297, 0.0008969634654931724, +- -0.2505858838558197, -0.004086401779204607, 0.03011753223836422, +- 0.00012006870383629575, -0.11625227332115173, -0.001972030848264694, +- 0.0018470664508640766 }, { -0.008228142745792866, 0.012081502936780453, +- 0.0029826753307133913, -0.12449272722005844, 0.0029766298830509186, +- 0.07979818433523178, 0.00489660631865263, -0.07108338922262192, +- 0.006859836168587208, 0.0070451670326292515 }, { -0.008624650537967682, +- -0.046396952122449875, -0.03131939470767975, -0.07215258479118347, +- -0.03171403333544731, -0.06464441865682602, -0.029830951243638992, +- 0.11516642570495605, -0.027210921049118042, -0.027592642232775688 }, { +- 0.007101533468812704, 0.12788672745227814, -0.015976447612047195, +- -0.05871947109699249, -0.022161206230521202, -0.12508492171764374, +- -0.03382435813546181, -0.0458468459546566, -0.016005748882889748, +- -0.02996719442307949 }, { -0.010423759929835796, 0.0421634167432785, +- -0.03137495368719101, -0.1427338570356369, -0.0142595786601305, +- -0.3891606330871582, -0.005455203354358673, -0.14104995131492615, +- -0.017540356144309044, -0.009234420023858547 }, { -0.0004962400416843593, +- 0.08799923211336136, 0.0010081625077873468, -0.10385274142026901, +- 0.001455705612897873, 0.018755201250314713, 0.0012732904870063066, +- -0.08233556151390076, 0.0008989688940346241, 0.0014089341275393963 }, { +- 0.39337393641471863, -0.29290419816970825, 0.4996858239173889, +- -0.3003338873386383, 0.5005763173103333, -0.5788354873657227, +- 0.4559592604637146, 0.1535145342350006, 0.4100588262081146, +- 0.43764257431030273 }, { 0.4433407783508301, -0.24534298479557037, +- 0.4418940246105194, -0.2674236595630646, 0.45750802755355835, +- -0.6914718747138977, 0.4248504340648651, 0.21534226834774017, +- 0.381326287984848, 0.42402878403663635 }, { 0.40570271015167236, +- -0.2965546250343323, 0.4877605438232422, -0.3061105012893677, +- 0.45858457684516907, -0.6169699430465698, 0.45162418484687805, +- 0.043029867112636566, 0.40422892570495605, 0.4498996138572693 }, { +- 0.5399827361106873, -0.23754213750362396, 0.42819300293922424, +- -0.2471727430820465, 0.4236094355583191, -0.7273492217063904, +- 0.397212415933609, 0.1800859272480011, 0.3471176326274872, 0.38948121666908264 +- }, { -0.1325892210006714, -0.2530541718006134, 0.47642746567726135, +- -0.2529260218143463, 0.5287042260169983, -0.7421981692314148, +- 0.45938733220100403, 0.3739463984966278, 0.41974151134490967, +- 0.4510754346847534 }, { -0.14016218483448029, -0.28810086846351624, +- 0.5178493857383728, -0.3065412640571594, 0.5258545875549316, +- -0.6815170645713806, 0.4928705096244812, 0.3198302388191223, 0.43727907538414, +- 0.489217072725296 }, { -0.06365948915481567, -0.2969031035900116, +- 0.49729400873184204, -0.3059382736682892, 0.4898521304130554, +- -0.7203274369239807, 0.47671565413475037, 0.1270948052406311, +- 0.41028112173080444, 0.463035523891449 }, { -0.36017751693725586, +- -0.24474093317985535, 0.4741400182247162, -0.24970588088035583, +- 0.5802808403968811, -0.7732722163200378, 0.5051204562187195, +- 0.6651050448417664, 0.4411555230617523, 0.4398174285888672 }, { +- -0.09952408075332642, -0.22142039239406586, 0.505150318145752, +- -0.2818147540092468, 0.5554866194725037, -0.7599970102310181, +- 0.4819079041481018, 0.46836376190185547, 0.4341869652271271, +- 0.43512919545173645 }, { 0.5686147212982178, -0.18401777744293213, +- 0.4294854998588562, -0.23842167854309082, 0.46184518933296204, +- -0.6931471228599548, 0.447188138961792, 0.42545783519744873, +- 0.3808431625366211, 0.405420184135437 }, { 0.37540721893310547, +- -0.29956886172294617, 0.47791191935539246, -0.3045949935913086, +- 0.45226752758026123, -0.6477946043014526, 0.4435006380081177, +- 0.04529328644275665, 0.3958480656147003, 0.4403669238090515 }, { +- 0.39132338762283325, -0.31595879793167114, 0.49054065346717834, +- -0.3178234398365021, 0.4703467786312103, -0.5904060006141663, +- 0.45879489183425903, 0.02425980195403099, 0.4105776250362396, +- 0.4531162977218628 }, { -0.006057941820472479, 0.006569928489625454, +- 0.0015440979041159153, 0.0013556998455896974, 0.005920958239585161, +- 0.00019130691362079233, 0.0015525295166298747, -0.07831747829914093, +- 0.004157649353146553, 0.001713182544335723 }, { 0.015238759107887745, +- -0.012075832113623619, 0.019996659830212593, -0.013050640933215618, +- 0.019533328711986542, 0.04019935429096222, 0.020779648795723915, +- -0.017803780734539032, 0.01775379851460457, 0.016923801973462105 }, { +- -0.00040881827590055764, 0.01769774593412876, -0.0030561434105038643, +- 0.017618050798773766, -0.003441327251493931, -0.008425338193774223, +- -0.004319507163017988, -0.040901608765125275, -0.008085516281425953, +- -0.00901162438094616 }, { -0.006333544384688139, 0.0218157060444355, +- -0.009262368083000183, 0.02132960595190525, -0.0016303389566019177, +- -0.004398090299218893, -0.010243585333228111, -0.026997482404112816, +- -0.009616672061383724, -0.0112041300162673 }, { 0.0016361094312742352, +- 0.003124030539765954, 0.002565001603215933, 0.0005618871073238552, +- 0.006878560408949852, 0.03515741601586342, 0.0034865504130721092, +- -0.06985997408628464, 0.0033802350517362356, 0.004246413242071867 }, { +- 0.0022312409710139036, -0.0017821462824940681, 0.020819153636693954, +- 0.014220071956515312, 0.023876415565609932, 0.06832368671894073, +- 0.021195560693740845, -0.054931141436100006, 0.018499089404940605, +- 0.020361075177788734 }, { -0.0015170410042628646, 0.0030387609731405973, +- 0.009525091387331486, 0.0023157033137977123, 0.012122565880417824, +- 0.05290598422288895, 0.007844913750886917, -0.03350060060620308, +- 0.007179108913987875, 0.007509269751608372 }, { 0.0026995691005140543, +- 0.01033916138112545, 0.005106386262923479, 0.013446318916976452, +- 0.017022928223013878, 0.029302654787898064, 0.0039514112286269665, +- -0.04868422821164131, 0.0026275364216417074, 0.0003789003530982882 }, { +- 0.0017787649994716048, 0.0011385915568098426, 0.006451384164392948, +- -0.0025774631649255753, 0.00652729906141758, 0.04508327320218086, +- 0.006555443163961172, -0.039301082491874695, 0.004885929170995951, +- 0.005540152080357075 }, { 0.019082074984908104, -0.024626603350043297, +- 0.03249650448560715, -0.024554960429668427, 0.034270841628313065, +- 0.17475825548171997, 0.03194909542798996, -0.03408300504088402, +- 0.031355202198028564, 0.03307552635669708 }, { -0.002374011091887951, +- 0.011019104160368443, 0.00536889536306262, 0.009987344965338707, +- 0.005368947982788086, 0.020124142989516258, 0.00080679333768785, +- -0.03276708722114563, -0.0007575554773211479, -0.0007960750954225659 }, { +- -0.004796746652573347, 0.022617409005761147, -0.006781514268368483, +- 0.02012668177485466, -0.007941807620227337, -0.04676627740263939, +- -0.005258339922875166, -0.046246204525232315, -0.0071578314527869225, +- -0.009032237343490124 }, { 0.009770474396646023, -0.011141248978674412, +- 0.019269749522209167, -0.014210346154868603, 0.020542146638035774, +- 0.048880185931921005, 0.020035162568092346, -0.03952275589108467, +- 0.01856170780956745, 0.018174735829234123 }, { -0.001620269613340497, +- 0.011470676399767399, 0.004611546639353037, 0.006774203386157751, +- 0.002739626681432128, 0.02218065969645977, 0.0017491821199655533, +- -0.03775838017463684, -0.000319438346195966, -0.0004950406146235764 }, { +- 0.0012955022975802422, -0.014817631803452969, 0.026199808344244957, +- -0.016461731866002083, 0.026273394003510475, 0.01814219355583191, +- 0.025083784013986588, -0.052376847714185715, 0.023744210600852966, +- 0.02334190532565117 }, { -0.004868587013334036, 0.0016003461787477136, +- 0.007678245659917593, 0.010228456929326057, 0.007693978026509285, +- 0.03484954312443733, 0.006526602897793055, -0.04437534511089325, +- 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}, { 0.004870634060353041, -0.0026161016430705786, +- 0.01613251492381096, -0.0059494515880942345, 0.019811052829027176, +- 0.08013129979372025, 0.015556958504021168, -0.05195259302854538, +- 0.015604502521455288, 0.014967973344027996 }, { 0.04881030321121216, +- 0.021579794585704803, -0.014629039913415909, 0.020981132984161377, +- -0.014194115065038204, -0.02374698780477047, -0.014806374907493591, +- -0.02924659475684166, -0.016147935763001442, -0.017149971798062325 }, { +- -0.0021160561591386795, -0.004959597252309322, 0.01772688701748848, +- -0.0046059261076152325, 0.015790479257702827, 0.06731697916984558, +- 0.015668079257011414, -0.03320039063692093, 0.013252184726297855, +- 0.013839546591043472 }, { 0.941993772983551, -1.5817229747772217, +- 2.0343267917633057, -1.6535866260528564, 2.232057809829712, +- -1.278427004814148, 2.059631109237671, -2.335737705230713, 1.9325844049453735, +- 1.9331965446472168 }, { 0.9436568021774292, -1.5791032314300537, +- 2.0879499912261963, -1.4951168298721313, 2.2531628608703613, +- -1.2294822931289673, 2.0839295387268066, -2.4484803676605225, +- 1.9551223516464233, 1.9740538597106934 }, { -0.22980402410030365, +- 0.9199262261390686, -1.3931411504745483, 1.0378587245941162, +- -1.7050687074661255, 4.863880964656175e-10, -1.5698068141937256, +- 0.9223605394363403, -1.335978627204895, -1.3027349710464478 }, { +- -0.3382071256637573, 0.9860741496086121, -1.6543004512786865, +- 1.0869961977005005, -1.7495276927947998, 0.1413516104221344, +- -1.6589244604110718, 0.9568116068840027, -1.2587254047393799, +- -1.316787838935852 }, { -0.08973576128482819, 1.0692839622497559, +- -1.7261924743652344, 1.1258662939071655, -2.048819065093994, +- 8.524442957069667e-11, -1.707221269607544, 0.9763411283493042, +- -1.3384802341461182, -1.5099725723266602 }, { -0.23119568824768066, +- 1.1025586128234863, -1.7083741426467896, 1.1952905654907227, +- -2.0976247787475586, 4.2183725262878724e-11, -1.6553181409835815, +- 1.043709397315979, -1.353306770324707, -1.5630202293395996 }, { +- -0.2149028778076172, 0.9034178853034973, -1.4059020280838013, +- 1.0857110023498535, -1.7785764932632446, 6.785310091572683e-10, +- -1.5982911586761475, 0.9385444521903992, -1.102957844734192, +- -1.2764172554016113 }, { -0.3442114591598511, 0.7093265652656555, +- -1.3323750495910645, 0.7892476320266724, -1.4307119846343994, +- 1.2957205308694597e-9, -1.2221505641937256, 0.7406548261642456, +- -1.0390063524246216, -1.0610798597335815 }, { -0.3801349401473999, +- 0.8477363586425781, -1.5809834003448486, 0.9098098874092102, +- -1.6288162469863892, 1.2674961080705316e-9, -1.4910979270935059, +- 0.8300457000732422, -1.1994421482086182, -1.3756306171417236 }, { +- -0.4026913046836853, 0.9909816980361938, -1.6537928581237793, +- 1.0298457145690918, -1.8706167936325073, 6.557077797397781e-11, +- -1.4875438213348389, 0.9636037945747375, -1.3140361309051514, +- -1.321130633354187 } +-}; +- +-static float intercepts[10] = { +- -0.9423781037330627, +- 2.3425614833831787, +- -1.880435824394226, +- 2.760684013366699, +- -2.1556267738342285, +- 1.9289884567260742, +- -1.943122386932373, +- 1.8524644374847412, +- -1.8369754552841187, +- -1.778485655784607 +-}; +- +-static float intercepts1[1] = { +- -0.9438958168029785 +-}; +- +-static float coefficient1[10] = { +- 4.518650531768799, +- -3.7139227390289307, +- 5.691276550292969, +- -3.7503113746643066, +- 5.436307430267334, +- -6.737155914306641, +- 5.318873405456543, +- -4.013023376464844, +- 4.771977424621582, +- 5.26296329498291 +-}; +- +-static float offset[6] = { +- 205.08018493652344, +- 10.790425300598145, +- 10.719943046569824, +- 183.248779296875, +- 2656.49658203125, +- 12.877049446105957 +-}; +- +-static float scale[6] = { +- 0.006835445761680603, +- 0.08650556206703186, +- 0.08758283406496048, +- 0.005654274486005306, +- 0.00008135510142892599, +- 0.10635864734649658 +-}; +- +-static float unity[1] = { +- 1.0 +-}; +- +-static char cats_strings[34][128] = { +- "ea75dbfdc4cd33ab059a923fd2b87d67c250a61e8ae64ff03001eb26b4a3c5f1", +- "232d26a984e4c87bf91264837eedc6b5a4a1444a93349be0ac371de77d0d8426", +- "db8c6ac43cd10145ceeb8463a1a3920697e85e7b554bd9f13c58b0b549db7af0", +- "327fa6f438c4bf9d4e01ce8230bd8c36d3f07b1d9d1b1f93ec38c8ebb0747a71", +- "5ed9c9e5e1107cde3924375a33c1250a951395b59d8472f08ac7978b6fc7ce82", +- "32a989965f70a73aa993e76f15344ec10a73ef65c32f47e16825465b246d0730", +- "6c6627b9bede7234a142d117e88d34ad04c9672a27b8fccd122a9442ad218e15", +- "d049e0300c22bf3f4bac34ad19e9b2ef00d433b0717b094bc6657ac94670f3c0", +- "f321a0cb393597da1f2e24598aa3adcb545b24a5fbaac9df87015f30aabded6e", +- "c0fabdb9eea8a2353102665eaa3211e95d3c5826fcc44bb67fc8c5fcd3503d35", +- "24801cbd57aaf8f01a2c5782d8ebeb26e382228eebdd904c9b78562defdad953", +- "6b4b7a9314efb703ba53a8316d02cd0e3408aad93760cc88b0d9b9bdd5891a1a", +- "e34b6f1266cf79b5e6ed49b1038dbe26f8da6d09bb556143ca2e4fb0a4ad065c", +- "ab3e680b0f70d8bb2df694b55c6d78e11dc82973ad20d5f376f30ee8d4a11a0a", +- "cfcaf0d89b776cab25e88e3f034a4993b16d78be249bc23af7bbb8751c7e350f", +- "cc912327aa7f363442b317507d27e4b8133989dc49e9f06c049b794a3bc0dc37", +- "819901d92b3deeb7adfd5b03b3620883abfd4cbe63a34fded376047842b78cda", +- "1763e99cd0ad99710d516d21f150cdd96da78d4a5d735d4061bb54b136f3517c", +- "26a65d430b9e68fae421cac7a9d5de333f79185b3c1db4e9d59cd501f0fd6a51", +- "0c3603e13e24a40b4bf215e3795a9a40d60a8456fb7b63c2d11e81701a231e85", +- "afd4b5db81abc1dd56d271732ed0245f8691bdc5dad3476d6f6356077b1aa1d6", +- "34a97c4109b59b73547f940c1dc8d21c0f187388f2d3a8eecfee7fd867902fd4", +- "ac31ba1c9fdf51baa2a437bfc092a1f732e2a8f066763742b0770a6e26e32f2b", +- "e5e47a373094f3f9b4188c843d5c4bea5a2a4ac4bbbdf7fac7ce39b206257377", +- "15410f23db97054b6eb270efccfb7cb4176f8268142cea16e28b21dc9598700e", +- "f1db8e9ad44e7e1841b14b125ccf35a17e8cffa8f06823bd46cf856e4af263b8", +- "aaf968ba850b4d9affbec493fa0fe0a833e9e463e87a2cce0c8c08a13ccca4a2", +- "a4169b3e9a4c13fc94c7a67ab099ce92cc68ea47abaf1688ab8a17202f8da051", +- "3c5359d2750623f244164c9f45384ef06e75360a76d4dbd04f063f608cccc780", +- "f1f1286515914da97052674ad09e256fc598dccd4d385dad588b6dd2a03e6194", +- "ca98d874b31b6b0b1e2533bc1408d0d6a8bac0a161a691221748163ddcb12103", +- "b1a11736cb8ef5565bff055f3163253813c9c4161304ea3fce55ad805eec174f", +- "8d79ca67d207ac46fde3b25b6e1d51c4daeae308e2f3aa89fc9a24b7bb8d0656", +- "29272c47115b5a93be87e3a9d8739fb2e8a1fea6aa31852af190389734c51946" +-}; +- +-static char cats_strings2[10][128] = { +- "7a917c2fad1f46426a21f8ecb64a3afbb7a763f80b2190cae4c021e8bd6c71d2", +- "a18ffc9586713699b9fcb936777d28cf9d7a4214a134c52ab6346348ff9ff3e4", +- "deeabd69f5ef24e4e8a7bb8d07fdc8fbdd4ffe702cb1b2e9e45d1010a8b5b610", +- "b2019c9be6a0087ab26f42c5de10595515176eb576277946bf04434c05bde5b7", +- "b15e2f190ad03a8869c3939ab684966a16a06ed55c9afeca4104f3544edc5378", +- "f0cac05641df3d87852f8c07eb49b9070a383c2a89287d5a32593f251002fd6a", +- "d511711f8439e1ba7592ae8330e1d2d8eaf43962b6bd2f27ed9d49c35ee47381", +- "7fc38db11d3600963a728c164a01991a1d627d2b51b7a3d957060c64aa7ec88b", +- "1cea197e5be5bb4fc161c0853cb955a50cb4d63bcd8ef9a2322773c2098ef6dc", +- "c4911d13876783e2a86ab62427e976ad8edc439a011f0d01a4e8dd2c485e4886" +-}; +- +-static void +-matmul (const float *lhs, const float *rhs, int m, int k, int n, float *out) +-{ +- for (int i = 0; i < m; i++) +- { +- for (int j = 0; j < n; j++) +- { +- out[i * n + j] = 0.0f; +- for (int p = 0; p < k; p++) +- { +- out[i * n + j] += lhs[i * k + p] * rhs[p * n + j]; +- } +- } +- } +-} +- +-static void +-add (const float *lhs, const float *rhs, int length, float *out) +-{ +- for (int i = 0; i < length; i++) +- { +- out[i] = lhs[i] + rhs[i]; +- } +-} +- +-static void +-sub (const float *lhs, const float *rhs, int length, float *out) +-{ +- for (int i = 0; i < length; i++) +- { +- out[i] = lhs[i] - rhs[i]; +- } +-} +- +-static void +-sigmoid (const float *in, int length, float *out) +-{ +- for (int i = 0; i < length; i++) +- { +- out[i] = 1.0f / (1.0f + expf (-in[i])); +- } +-} +- +-static void +-relu (const float *data, int length, float *out) +-{ +- for (int i = 0; i < length; i++) +- { +- if (data[i] < 0) +- { +- out[i] = 0; +- } +- else +- { +- out[i] = data[i]; +- } +- } +-} +- +-static void +-line_concat (const float *in, int in_size, float *out, int out_size) +-{ +- for (int i = 0; i < in_size; i++) +- { +- out[out_size + i] = in[i]; +- } +-} +- +-static void +-one_hot_encoder (const char *in, const char (*cats)[128], float *out, +- int out_size) +-{ +- for (int i = 0; i < out_size; i++) +- { +- if (i < out_size && strcmp (cats[i], in) == 0) +- { +- out[i] = 1.0f; +- } +- else +- { +- out[i] = 0.0f; +- } +- } +-} +- +-static void +-imputer (const int64_t *in, int size, float *out) +-{ +- for (int i = 0; i < size; i++) +- { +- out[i] = in[i] * 1.0f; +- } +-} +- +-static void +-scaler (const float *in, const float *offset, const float *scale, int size, +- float *out) +-{ +- for (int i = 0; i < size; i++) +- { +- out[i] = (in[i] - offset[i]) * scale[i]; +- } +-} +- +-static int +-argmax (const float *in, int in_size) +-{ +- int out_idx = 0; +- for (int i = 0; i < in_size; i++) +- { +- if (in[i] > in[out_idx]) +- { +- out_idx = i; +- } +- } +- return out_idx; +-} +- +-static int +-compare_strings (const void *a, const void *b) +-{ +- const char *str_a = *(const char **)a; +- const char *str_b = *(const char **)b; +- +- int len = strlen (str_a); +- for (int i = 0; i < len; i++) +- { +- char c1 = str_a[i]; +- char c2 = str_b[i]; +- if (ISUPPER (c1) && !ISUPPER (c2)) +- { +- return 0; +- } +- else if (!ISUPPER (c1) && ISUPPER (c2)) +- { +- return 1; +- } +- else if (c1 != c2) +- { +- return c1 < c2; +- } +- } +- return strlen (str_a) > strlen (str_b); +-} +- +-static void +-truncate_prefix (const char *str, char *result) +-{ +- const char *underscore_pos = strchr (str, '_'); +- if (underscore_pos == NULL) +- { +- strcpy (result, str); +- return; +- } +- +- size_t len = underscore_pos - str; +- strncpy (result, str, len + 1); +- result[len + 1] = '\0'; +-} +- +-static void +-preprocess (int argc1, const char **argv1, const char *mops, +- int argc2, int64_t *argv2, char (*in_options)[1024], +- int64_t * in_modes) +-{ +- strcpy (in_options[0], mops); +- +- const char *output_option = "-o"; +- const char *macro_prefix = "-D"; +- const char *needle = "--param"; +- const char *flag_prefix = "-"; +- const char *default_option = "-fdefault-option"; +- const int default_int_val = 0; +- int m_size = 0; +- for (int i = 0; i < argc1; i++) +- { +- if (strncmp (argv1[i], macro_prefix, 2) == 0) +- { +- m_size++; +- } +- } +- char *m_options[m_size]; +- char output_file[1024]; +- int m_index = 0; +- for (int i = 0; i < argc1; i++) +- { +- if (strncmp (argv1[i], macro_prefix, 2) == 0) +- { +- m_options[m_index] = (char*)argv1[i]; +- m_index++; +- } +- if (strcmp (argv1[i], output_option) == 0) +- { +- truncate_prefix (argv1[i + 1], output_file); +- } +- } +- strcpy (in_options[1], output_file); +- int in_options_size = 2; +- qsort (m_options, m_size, sizeof (m_options[0]), compare_strings); +- for (int i = 0; i < m_size && in_options_size < M_OPTION_SIZE; i++) +- { +- strcpy (in_options[in_options_size], m_options[i]); +- in_options_size++; +- } +- +- for (int i = 0; i < argc1 && in_options_size < M_OPTION_SIZE; i++) +- { +- if (strncmp (argv1[i], macro_prefix, 2) != 0 +- && strcmp (argv1[i], output_option) != 0 +- && strncmp (argv1[i], needle, 7) != 0 +- && strncmp (argv1[i], flag_prefix, 1) == 0) +- { +- strcpy (in_options[in_options_size], argv1[i]); +- in_options_size++; +- } +- } +- while (in_options_size < M_OPTION_SIZE) +- { +- strcpy (in_options[in_options_size], default_option); +- in_options_size++; +- } +- +- uint8_t hash[32]; +- for (int i = 0; i < M_OPTION_SIZE; i++) +- { +- sha256 (in_options[i], strlen (in_options[i]), hash); +- char hash_str[65]; +- for (int j = 0; j < 32; j++) +- { +- sprintf (hash_str + (j * 2), "%02x", hash[j]); +- } +- strcpy (in_options[i], hash_str); +- } +- +- for (int i = 0; i < argc2 && i < M_MODE_SIZE; i++) +- { +- if (i < argc2) +- { +- in_modes[i] = argv2[i]; +- } +- else +- { +- in_modes[i] = default_int_val; +- } +- } +-} +- +-static int +-graph_infer (int argc1, const char **argv1, const char *mops, +- int argc2, int64_t *argv2) +-{ +- static char in_options[M_OPTION_SIZE][1024]; +- static int64_t in_modes[M_MODE_SIZE]; +- +- preprocess (argc1, argv1, mops, argc2, argv2, in_options, in_modes); +- +- const int concat_out_size = 350; +- float concat_result[concat_out_size]; +- const int encoder_out_size = 34; +- const int encoder_last_size = 10; +- int concat_size = 0; +- const int size = encoder_out_size; +- for (int i = 1; i < M_OPTION_SIZE; i++) +- { +- float encoder_out[size]; +- one_hot_encoder (in_options[i], cats_strings, encoder_out, size); +- line_concat (encoder_out, size, concat_result, concat_size); +- concat_size += size; +- } +- float encoder_out2[encoder_last_size]; +- one_hot_encoder (in_options[0], cats_strings2, encoder_out2, +- encoder_last_size); +- line_concat (encoder_out2, encoder_last_size, concat_result, concat_size); +- concat_size += encoder_last_size; +- +- float variable[M_MODE_SIZE]; +- imputer (in_modes, M_MODE_SIZE, variable); +- float variable1[M_MODE_SIZE]; +- scaler (variable, offset, scale, M_MODE_SIZE, variable1); +- +- float transformed_column[concat_out_size + M_MODE_SIZE]; +- line_concat (variable1, M_MODE_SIZE, transformed_column, 0); +- line_concat (concat_result, concat_out_size, transformed_column, 6); +- +- const int m = 1, k = 356, n = 10; +- float mul_result[n]; +- matmul (transformed_column, coefficient[0], m, k, n, mul_result); +- +- float add_result[n]; +- add (mul_result, intercepts, n, add_result); +- float next_activations[n]; +- relu (add_result, n, next_activations); +- +- const int m2 = 1, k2 = 10, n2 = 1; +- float mul_result1[n2]; +- matmul (next_activations, coefficient1, m2, k2, n2, mul_result1); +- float add_result1[n2]; +- add (mul_result1, intercepts1, n2, add_result1); +- +- float out_activations_result[n2]; +- sigmoid (add_result1, n2, out_activations_result); +- +- float negative_class_proba[n2]; +- sub (unity, out_activations_result, n2, negative_class_proba); +- const int prob_size = n2 + n2; +- float probabilities[prob_size]; +- line_concat (negative_class_proba, n2, probabilities, 0); +- line_concat (out_activations_result, n2, probabilities, n2); +- +- int argmax_output = argmax (probabilities, prob_size); +- +- return argmax_output; +-} ++ Copyright (C) 2024-2024 Free Software Foundation, Inc. + +-#endif // AI4C_INFER ++ This file is part of GCC. ++ ++ GCC is free software; you can redistribute it and/or modify it under ++ the terms of the GNU General Public License as published by the Free ++ Software Foundation; either version 3, or (at your option) any later ++ version. ++ ++ GCC is distributed in the hope that it will be useful, but WITHOUT ANY ++ WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with GCC; see the file COPYING3. If not see ++ . */ ++ ++#ifndef AI4C_INFER_H ++#define AI4C_INFER_H ++ ++extern void matmul (const float *, const float *, int, int, int, float *); ++extern void add (const float *, const float *, int, float *); ++extern void sub (const float *, const float *, int, float *); ++extern void sigmoid (const float *, int, float *); ++extern void relu (const float *, int, float *); ++extern void line_concat (const float *, int, float *, int); ++extern void one_hot_encoder (const char *, const char (*)[65], float *, int); ++extern void imputer (const int64_t *, int, float *); ++extern void scaler (const float *, const float *, const float *, int, float *); ++extern int argmax (const float *, int); ++ ++extern void ++execute_sha256 (const char *, char *, size_t); ++extern float read_float_from_file (FILE*); ++ ++extern int get_optimize_decision_from_optimizer (int, const char **, ++ const char *, int , ++ int64_t *); ++#endif /* AI4C_INFER_H */ +diff --git a/gcc/common/config/aarch64/aarch64-common.c b/gcc/common/config/aarch64/aarch64-common.c +index 21e7820cd..f797f661d 100644 +--- a/gcc/common/config/aarch64/aarch64-common.c ++++ b/gcc/common/config/aarch64/aarch64-common.c +@@ -126,9 +126,9 @@ aarch64_handle_option (struct gcc_options *opts, + struct aarch64_option_extension + { + const char *const name; +- const unsigned long flag_canonical; +- const unsigned long flags_on; +- const unsigned long flags_off; ++ const uint64_t flag_canonical; ++ const uint64_t flags_on; ++ const uint64_t flags_off; + const bool is_synthetic; + }; + +@@ -157,14 +157,14 @@ struct processor_name_to_arch + { + const std::string processor_name; + const enum aarch64_arch arch; +- const unsigned long flags; ++ const uint64_t flags; + }; + + struct arch_to_arch_name + { + const enum aarch64_arch arch; + const std::string arch_name; +- const unsigned long flags; ++ const uint64_t flags; + }; + + /* Map processor names to the architecture revision they implement and +@@ -192,7 +192,7 @@ static const struct arch_to_arch_name all_architectures[] = + aarch64_parse_opt_result describing the result. */ + + enum aarch64_parse_opt_result +-aarch64_parse_extension (const char *str, unsigned long *isa_flags) ++aarch64_parse_extension (const char *str, uint64_t *isa_flags) + { + /* The extension string is parsed left to right. */ + const struct aarch64_option_extension *opt = NULL; +@@ -267,18 +267,21 @@ int opt_ext_cmp (const void* a, const void* b) + turns on as a dependency. As an example +dotprod turns on FL_DOTPROD and + FL_SIMD. As such the set of bits represented by this option is + {FL_DOTPROD, FL_SIMD}. */ +- unsigned long total_flags_a = opt_a->flag_canonical & opt_a->flags_on; +- unsigned long total_flags_b = opt_b->flag_canonical & opt_b->flags_on; ++ uint64_t total_flags_a = opt_a->flag_canonical & opt_a->flags_on; ++ uint64_t total_flags_b = opt_b->flag_canonical & opt_b->flags_on; + int popcnt_a = popcount_hwi ((HOST_WIDE_INT)total_flags_a); + int popcnt_b = popcount_hwi ((HOST_WIDE_INT)total_flags_b); + int order = popcnt_b - popcnt_a; + + /* If they have the same amount of bits set, give it a more + deterministic ordering by using the value of the bits themselves. */ +- if (order == 0) +- return total_flags_b - total_flags_a; ++ if (order != 0) ++ return order; + +- return order; ++ if (total_flags_a != total_flags_b) ++ return total_flags_a < total_flags_b ? 1 : -1; ++ ++ return 0; + } + + /* Implement TARGET_OPTION_INIT_STRUCT. */ +@@ -314,9 +317,9 @@ aarch64_option_init_struct (struct gcc_options *opts ATTRIBUTE_UNUSED) + */ + + static bool +-aarch64_contains_opt (unsigned long isa_flag_bits, opt_ext *opt) ++aarch64_contains_opt (uint64_t isa_flag_bits, opt_ext *opt) + { +- unsigned long flags_check ++ uint64_t flags_check + = opt->is_synthetic ? opt->flags_on : opt->flag_canonical; + + return (isa_flag_bits & flags_check) == flags_check; +@@ -329,13 +332,13 @@ aarch64_contains_opt (unsigned long isa_flag_bits, opt_ext *opt) + that all the "+" flags come before the "+no" flags. */ + + std::string +-aarch64_get_extension_string_for_isa_flags (unsigned long isa_flags, +- unsigned long default_arch_flags) ++aarch64_get_extension_string_for_isa_flags (uint64_t isa_flags, ++ uint64_t default_arch_flags) + { + const struct aarch64_option_extension *opt = NULL; + std::string outstr = ""; + +- unsigned long isa_flag_bits = isa_flags; ++ uint64_t isa_flag_bits = isa_flags; + + /* Pass one: Minimize the search space by reducing the set of options + to the smallest set that still turns on the same features as before in +diff --git a/gcc/config/aarch64/aarch64-arches.def b/gcc/config/aarch64/aarch64-arches.def +index 7d05cd604..f3aeb1eda 100644 +--- a/gcc/config/aarch64/aarch64-arches.def ++++ b/gcc/config/aarch64/aarch64-arches.def +@@ -36,5 +36,10 @@ AARCH64_ARCH("armv8.2-a", generic, 8_2A, 8, AARCH64_FL_FOR_ARCH8_2) + AARCH64_ARCH("armv8.3-a", generic, 8_3A, 8, AARCH64_FL_FOR_ARCH8_3) + AARCH64_ARCH("armv8.4-a", generic, 8_4A, 8, AARCH64_FL_FOR_ARCH8_4) + AARCH64_ARCH("armv8.5-a", generic, 8_5A, 8, AARCH64_FL_FOR_ARCH8_5) ++AARCH64_ARCH("armv8.6-a", generic, 8_6A, 8, AARCH64_FL_FOR_ARCH8_6) ++AARCH64_ARCH("armv8.7-a", generic, 8_7A, 8, AARCH64_FL_FOR_ARCH8_7) ++AARCH64_ARCH("armv9-a", generic, 9A , 9, AARCH64_FL_FOR_ARCH9) ++AARCH64_ARCH("armv9.1-a", generic, 9_1A , 9, AARCH64_FL_FOR_ARCH9_1) ++AARCH64_ARCH("armv9.2-a", generic, 9_2A , 9, AARCH64_FL_FOR_ARCH9_2) + + #undef AARCH64_ARCH +diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def +index dc51967d4..3ff899ebd 100644 +--- a/gcc/config/aarch64/aarch64-cores.def ++++ b/gcc/config/aarch64/aarch64-cores.def +@@ -117,4 +117,6 @@ AARCH64_CORE("cortex-a73.cortex-a53", cortexa73cortexa53, cortexa53, 8A, AARCH + + AARCH64_CORE("cortex-a75.cortex-a55", cortexa75cortexa55, cortexa53, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD, cortexa73, 0x41, AARCH64_BIG_LITTLE (0xd0a, 0xd05), -1) + ++AARCH64_CORE("hip12", hip12, hip12, 9_2A, AARCH64_FL_FOR_ARCH9_2 | AARCH64_FL_SVE | AARCH64_FL_SVE2 | AARCH64_FL_SVE2_BITPERM | AARCH64_FL_SVE2_AES | AARCH64_FL_SVE2_SM4 | AARCH64_FL_SVE2_SHA3 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_BF16 | AARCH64_FL_DOTPROD | AARCH64_FL_LSE | AARCH64_FL_SIMD | AARCH64_FL_PAUTH | AARCH64_FL_RDMA | AARCH64_FL_LS64, hip12, 0x48, 0xd06, -1) ++ + #undef AARCH64_CORE +diff --git a/gcc/config/aarch64/aarch64-cost-tables.h b/gcc/config/aarch64/aarch64-cost-tables.h +index 8a8ae7799..52a6dd06d 100644 +--- a/gcc/config/aarch64/aarch64-cost-tables.h ++++ b/gcc/config/aarch64/aarch64-cost-tables.h +@@ -334,6 +334,110 @@ const struct cpu_cost_table thunderx2t99_extra_costs = + } + }; + ++const struct cpu_cost_table hip12_extra_costs = ++{ ++ /* ALU */ ++ { ++ 0, /* arith. */ ++ 0, /* logical. */ ++ 0, /* shift. */ ++ 0, /* shift_reg. */ ++ 0, /* arith_shift. */ ++ 0, /* arith_shift_reg. */ ++ COSTS_N_INSNS (1), /* log_shift. */ ++ COSTS_N_INSNS (1), /* log_shift_reg. */ ++ COSTS_N_INSNS (1), /* extend. */ ++ 0, /* extend_arith. */ ++ 0, /* bfi. */ ++ 0, /* bfx. */ ++ 0, /* clz. */ ++ 0, /* rev. */ ++ 0, /* non_exec. */ ++ true /* non_exec_costs_exec. */ ++ }, ++ ++ { ++ /* MULT SImode */ ++ { ++ COSTS_N_INSNS (2), /* simple. */ ++ 0, /* flag_setting. */ ++ COSTS_N_INSNS (2), /* extend. */ ++ COSTS_N_INSNS (2), /* add. */ ++ COSTS_N_INSNS (2), /* extend_add. */ ++ COSTS_N_INSNS (5) /* idiv. */ ++ }, ++ /* MULT DImode */ ++ { ++ COSTS_N_INSNS (3), /* simple. */ ++ 0, /* flag_setting (N/A). */ ++ COSTS_N_INSNS (3), /* extend. */ ++ COSTS_N_INSNS (3), /* add. */ ++ COSTS_N_INSNS (3), /* extend_add. */ ++ COSTS_N_INSNS (7) /* idiv. */ ++ } ++ }, ++ /* LD/ST */ ++ { ++ COSTS_N_INSNS (3), /* load. */ ++ COSTS_N_INSNS (4), /* load_sign_extend. */ ++ COSTS_N_INSNS (3), /* ldrd. */ ++ COSTS_N_INSNS (3), /* ldm_1st. */ ++ 1, /* ldm_regs_per_insn_1st. */ ++ 2, /* ldm_regs_per_insn_subsequent. */ ++ COSTS_N_INSNS (5), /* loadf. */ ++ COSTS_N_INSNS (5), /* loadd. */ ++ COSTS_N_INSNS (4), /* load_unaligned. */ ++ 0, /* store. */ ++ 0, /* strd. */ ++ 0, /* stm_1st. */ ++ 1, /* stm_regs_per_insn_1st. */ ++ 2, /* stm_regs_per_insn_subsequent. */ ++ 0, /* storef. */ ++ 0, /* stored. */ ++ COSTS_N_INSNS (1), /* store_unaligned. */ ++ COSTS_N_INSNS (5), /* loadv. */ ++ COSTS_N_INSNS (2) /* storev. */ ++ }, ++ { ++ /* FP SFmode */ ++ { ++ COSTS_N_INSNS (5), /* div. */ ++ COSTS_N_INSNS (2), /* mult. */ ++ COSTS_N_INSNS (4), /* mult_addsub. */ ++ COSTS_N_INSNS (3), /* fma. */ ++ COSTS_N_INSNS (1), /* addsub. */ ++ COSTS_N_INSNS (1), /* fpconst. */ ++ 0, /* neg. */ ++ COSTS_N_INSNS (1), /* compare. */ ++ COSTS_N_INSNS (2), /* widen. */ ++ COSTS_N_INSNS (2), /* narrow. */ ++ COSTS_N_INSNS (2), /* toint. */ ++ COSTS_N_INSNS (3), /* fromint. */ ++ COSTS_N_INSNS (2) /* roundint. */ ++ }, ++ /* FP DFmode */ ++ { ++ COSTS_N_INSNS (7), /* div. */ ++ COSTS_N_INSNS (2), /* mult. */ ++ COSTS_N_INSNS (4), /* mult_addsub. */ ++ COSTS_N_INSNS (3), /* fma. */ ++ COSTS_N_INSNS (1), /* addsub. */ ++ COSTS_N_INSNS (1), /* fpconst. */ ++ 0, /* neg. */ ++ COSTS_N_INSNS (1), /* compare. */ ++ COSTS_N_INSNS (2), /* widen. */ ++ COSTS_N_INSNS (2), /* narrow. */ ++ COSTS_N_INSNS (2), /* toint. */ ++ COSTS_N_INSNS (3), /* fromint. */ ++ COSTS_N_INSNS (2) /* roundint. */ ++ } ++ }, ++ /* Vector */ ++ { ++ COSTS_N_INSNS (1), /* alu. */ ++ } ++}; ++ + const struct cpu_cost_table hip09_extra_costs = + { + /* ALU */ +diff --git a/gcc/config/aarch64/aarch64-option-extensions.def b/gcc/config/aarch64/aarch64-option-extensions.def +index 8246c612b..b07cd7cff 100644 +--- a/gcc/config/aarch64/aarch64-option-extensions.def ++++ b/gcc/config/aarch64/aarch64-option-extensions.def +@@ -57,17 +57,20 @@ + + /* Enabling "fp" just enables "fp". + Disabling "fp" also disables "simd", "crypto", "fp16", "aes", "sha2", +- "sha3", sm3/sm4 and "sve". */ +-AARCH64_OPT_EXTENSION("fp", AARCH64_FL_FP, 0, AARCH64_FL_SIMD | AARCH64_FL_CRYPTO | AARCH64_FL_F16 | AARCH64_FL_AES | AARCH64_FL_SHA2 | AARCH64_FL_SHA3 | AARCH64_FL_SM4 | AARCH64_FL_SVE, false, "fp") ++ "sha3", sm3/sm4, "sve", "sve2", "sve2-aes", "sve2-sha3", "sve2-sm4", and ++ "bitperm". */ ++AARCH64_OPT_EXTENSION("fp", AARCH64_FL_FP, 0, AARCH64_FL_SIMD | AARCH64_FL_CRYPTO | AARCH64_FL_F16 | AARCH64_FL_AES | AARCH64_FL_SHA2 | AARCH64_FL_SHA3 | AARCH64_FL_SM4 | AARCH64_FL_SVE | AARCH64_FL_SVE2 | AARCH64_FL_SVE2_AES | AARCH64_FL_SVE2_SHA3 | AARCH64_FL_SVE2_SM4 | AARCH64_FL_SVE2_BITPERM, false, "fp") + + /* Enabling "simd" also enables "fp". + Disabling "simd" also disables "crypto", "dotprod", "aes", "sha2", "sha3", +- "sm3/sm4" and "sve". */ +-AARCH64_OPT_EXTENSION("simd", AARCH64_FL_SIMD, AARCH64_FL_FP, AARCH64_FL_CRYPTO | AARCH64_FL_DOTPROD | AARCH64_FL_AES | AARCH64_FL_SHA2 | AARCH64_FL_SHA3 | AARCH64_FL_SM4 | AARCH64_FL_SVE, false, "asimd") ++ "sm3/sm4", "sve", "sve2", "sve2-aes", "sve2-sha3", "sve2-sm4", and "bitperm". ++ */ ++AARCH64_OPT_EXTENSION("simd", AARCH64_FL_SIMD, AARCH64_FL_FP, AARCH64_FL_CRYPTO | AARCH64_FL_DOTPROD | AARCH64_FL_AES | AARCH64_FL_SHA2 | AARCH64_FL_SHA3 | AARCH64_FL_SM4 | AARCH64_FL_SVE | AARCH64_FL_SVE2 | AARCH64_FL_SVE2_AES | AARCH64_FL_SVE2_SHA3 | AARCH64_FL_SVE2_SM4 | AARCH64_FL_SVE2_BITPERM, false, "asimd") + + /* Enabling "crypto" also enables "fp", "simd", "aes" and "sha2". +- Disabling "crypto" disables "crypto", "aes", "sha2", "sha3" and "sm3/sm4". */ +-AARCH64_OPT_EXTENSION("crypto", AARCH64_FL_CRYPTO, AARCH64_FL_FP | AARCH64_FL_SIMD | AARCH64_FL_AES | AARCH64_FL_SHA2, AARCH64_FL_AES | AARCH64_FL_SHA2 |AARCH64_FL_SHA3 | AARCH64_FL_SM4, true, "aes pmull sha1 sha2") ++ Disabling "crypto" disables "crypto", "aes", "sha2", "sha3" and "sm3/sm4", ++ "sve2-aes", "sve2-sha3", "sve2-sm4". */ ++AARCH64_OPT_EXTENSION("crypto", AARCH64_FL_CRYPTO, AARCH64_FL_FP | AARCH64_FL_SIMD | AARCH64_FL_AES | AARCH64_FL_SHA2, AARCH64_FL_AES | AARCH64_FL_SHA2 | AARCH64_FL_SHA3 | AARCH64_FL_SM4 | AARCH64_FL_SVE2_AES | AARCH64_FL_SVE2_SHA3 | AARCH64_FL_SVE2_SM4, true, "aes pmull sha1 sha2") + + /* Enabling or disabling "crc" only changes "crc". */ + AARCH64_OPT_EXTENSION("crc", AARCH64_FL_CRC, 0, 0, false, "crc32") +@@ -76,8 +79,9 @@ AARCH64_OPT_EXTENSION("crc", AARCH64_FL_CRC, 0, 0, false, "crc32") + AARCH64_OPT_EXTENSION("lse", AARCH64_FL_LSE, 0, 0, false, "atomics") + + /* Enabling "fp16" also enables "fp". +- Disabling "fp16" disables "fp16", "fp16fml" and "sve". */ +-AARCH64_OPT_EXTENSION("fp16", AARCH64_FL_F16, AARCH64_FL_FP, AARCH64_FL_F16FML | AARCH64_FL_SVE, false, "fphp asimdhp") ++ Disabling "fp16" disables "fp16", "fp16fml", "sve", "sve2", "sve2-aes", ++ "sve2-sha3", "sve2-sm4", and "bitperm". */ ++AARCH64_OPT_EXTENSION("fp16", AARCH64_FL_F16, AARCH64_FL_FP, AARCH64_FL_F16FML | AARCH64_FL_SVE | AARCH64_FL_SVE2 | AARCH64_FL_SVE2_AES | AARCH64_FL_SVE2_SHA3 | AARCH64_FL_SVE2_SM4 | AARCH64_FL_SVE2_BITPERM, false, "fphp asimdhp") + + /* Enabling or disabling "rcpc" only changes "rcpc". */ + AARCH64_OPT_EXTENSION("rcpc", AARCH64_FL_RCPC, 0, 0, false, "lrcpc") +@@ -91,28 +95,29 @@ AARCH64_OPT_EXTENSION("rdma", AARCH64_FL_RDMA, AARCH64_FL_FP | AARCH64_FL_SIMD, + AARCH64_OPT_EXTENSION("dotprod", AARCH64_FL_DOTPROD, AARCH64_FL_SIMD, 0, false, "asimddp") + + /* Enabling "aes" also enables "simd". +- Disabling "aes" just disables "aes". */ +-AARCH64_OPT_EXTENSION("aes", AARCH64_FL_AES, AARCH64_FL_SIMD, 0, false, "aes") ++ Disabling "aes" disables "aes" and "sve2-aes'. */ ++AARCH64_OPT_EXTENSION("aes", AARCH64_FL_AES, AARCH64_FL_SIMD, AARCH64_FL_SVE2_AES, false, "aes") + + /* Enabling "sha2" also enables "simd". + Disabling "sha2" just disables "sha2". */ + AARCH64_OPT_EXTENSION("sha2", AARCH64_FL_SHA2, AARCH64_FL_SIMD, 0, false, "sha1 sha2") + + /* Enabling "sha3" enables "simd" and "sha2". +- Disabling "sha3" just disables "sha3". */ +-AARCH64_OPT_EXTENSION("sha3", AARCH64_FL_SHA3, AARCH64_FL_SIMD | AARCH64_FL_SHA2, 0, false, "sha3 sha512") ++ Disabling "sha3" disables "sha3" and "sve2-sha3". */ ++AARCH64_OPT_EXTENSION("sha3", AARCH64_FL_SHA3, AARCH64_FL_SIMD | AARCH64_FL_SHA2, AARCH64_FL_SVE2_SHA3, false, "sha3 sha512") + + /* Enabling "sm4" also enables "simd". +- Disabling "sm4" just disables "sm4". */ +-AARCH64_OPT_EXTENSION("sm4", AARCH64_FL_SM4, AARCH64_FL_SIMD, 0, false, "sm3 sm4") ++ Disabling "sm4" disables "sm4" and "sve2-sm4". */ ++AARCH64_OPT_EXTENSION("sm4", AARCH64_FL_SM4, AARCH64_FL_SIMD, AARCH64_FL_SVE2_SM4, false, "sm3 sm4") + + /* Enabling "fp16fml" also enables "fp" and "fp16". + Disabling "fp16fml" just disables "fp16fml". */ + AARCH64_OPT_EXTENSION("fp16fml", AARCH64_FL_F16FML, AARCH64_FL_FP | AARCH64_FL_F16, 0, false, "asimdfml") + + /* Enabling "sve" also enables "fp16", "fp" and "simd". +- Disabling "sve" just disables "sve". */ +-AARCH64_OPT_EXTENSION("sve", AARCH64_FL_SVE, AARCH64_FL_FP | AARCH64_FL_SIMD | AARCH64_FL_F16, 0, false, "sve") ++ Disabling "sve" disables "sve", "sve2", "sve2-aes", "sve2-sha3", "sve2-sm4" ++ and "bitperm". */ ++AARCH64_OPT_EXTENSION("sve", AARCH64_FL_SVE, AARCH64_FL_FP | AARCH64_FL_SIMD | AARCH64_FL_F16, AARCH64_FL_SVE2 | AARCH64_FL_SVE2_AES | AARCH64_FL_SVE2_SHA3 | AARCH64_FL_SVE2_SM4 | AARCH64_FL_SVE2_BITPERM, false, "sve") + + /* Enabling/Disabling "rng" only changes "rng". */ + AARCH64_OPT_EXTENSION("rng", AARCH64_FL_RNG, 0, 0, false, "rng") +@@ -129,4 +134,25 @@ AARCH64_OPT_EXTENSION("ssbs", AARCH64_FL_SSBS, 0, 0, false, "ssbs") + /* Enabling/Disabling "predres" only changes "predres". */ + AARCH64_OPT_EXTENSION("predres", AARCH64_FL_PREDRES, 0, 0, false, "") + ++/* Enabling "sve2" also enables "sve", "fp16", "fp", and "simd". ++ Disabling "sve2" disables "sve2", "sve2-aes", "sve2-sha3", "sve2-sm4", and ++ "bitperm". */ ++AARCH64_OPT_EXTENSION("sve2", AARCH64_FL_SVE2, AARCH64_FL_SVE | AARCH64_FL_FP | AARCH64_FL_SIMD | AARCH64_FL_F16, AARCH64_FL_SVE2_AES | AARCH64_FL_SVE2_SHA3 | AARCH64_FL_SVE2_SM4 | AARCH64_FL_SVE2_BITPERM, false, "") ++ ++/* Enabling "sve2-sm4" also enables "sm4", "simd", "fp16", "fp", "sve", and ++ "sve2". Disabling "sve2-sm4" just disables "sve2-sm4". */ ++AARCH64_OPT_EXTENSION("sve2-sm4", AARCH64_FL_SVE2_SM4, AARCH64_FL_SM4 | AARCH64_FL_SIMD | AARCH64_FL_F16 | AARCH64_FL_FP | AARCH64_FL_SVE | AARCH64_FL_SVE2, 0, false, "") ++ ++/* Enabling "sve2-aes" also enables "aes", "simd", "fp16", "fp", "sve", and ++ "sve2". Disabling "sve2-aes" just disables "sve2-aes". */ ++AARCH64_OPT_EXTENSION("sve2-aes", AARCH64_FL_SVE2_AES, AARCH64_FL_AES | AARCH64_FL_SIMD | AARCH64_FL_F16 | AARCH64_FL_FP | AARCH64_FL_SVE | AARCH64_FL_SVE2, 0, false, "") ++ ++/* Enabling "sve2-sha3" also enables "sha3", "simd", "fp16", "fp", "sve", and ++ "sve2". Disabling "sve2-sha3" just disables "sve2-sha3". */ ++AARCH64_OPT_EXTENSION("sve2-sha3", AARCH64_FL_SVE2_SHA3, AARCH64_FL_SHA3 | AARCH64_FL_SIMD | AARCH64_FL_F16 | AARCH64_FL_FP | AARCH64_FL_SVE | AARCH64_FL_SVE2, 0, false, "") ++ ++/* Enabling "bitperm" also enables "simd", "fp16", "fp", "sve", and "sve2". ++ Disabling "bitperm" just disables "bitperm". */ ++AARCH64_OPT_EXTENSION("bitperm", AARCH64_FL_SVE2_BITPERM, AARCH64_FL_SIMD | AARCH64_FL_F16 | AARCH64_FL_FP | AARCH64_FL_SVE | AARCH64_FL_SVE2, 0, false, "") ++ + #undef AARCH64_OPT_EXTENSION +diff --git a/gcc/config/aarch64/aarch64-tune.md b/gcc/config/aarch64/aarch64-tune.md +index b7b063ad4..9c13a3ea3 100644 +--- a/gcc/config/aarch64/aarch64-tune.md ++++ b/gcc/config/aarch64/aarch64-tune.md +@@ -1,5 +1,5 @@ + ;; -*- buffer-read-only: t -*- + ;; Generated automatically by gentune.sh from aarch64-cores.def + (define_attr "tune" +- "cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,thunderxt81,thunderxt83,xgene1,falkor,qdf24xx,exynosm1,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,ares,neoversen1,hip09,saphira,zeus,neoversev1,neoverse512tvb,neoversen2,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55" ++ "cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,thunderxt81,thunderxt83,xgene1,falkor,qdf24xx,exynosm1,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,ares,neoversen1,hip09,saphira,zeus,neoversev1,neoverse512tvb,neoversen2,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55,hip12" + (const (symbol_ref "((enum attr_tune) aarch64_tune)"))) +diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c +index 2100635fd..6e0bc1a86 100644 +--- a/gcc/config/aarch64/aarch64.c ++++ b/gcc/config/aarch64/aarch64.c +@@ -215,7 +215,7 @@ unsigned aarch64_architecture_version; + enum aarch64_processor aarch64_tune = cortexa53; + + /* Mask to specify which instruction scheduling options should be used. */ +-unsigned long aarch64_tune_flags = 0; ++uint64_t aarch64_tune_flags = 0; + + /* Global flag for PC relative loads. */ + bool aarch64_pcrelative_literal_loads; +@@ -330,6 +330,22 @@ static const struct cpu_addrcost_table hip09_addrcost_table = + 0, /* imm_offset */ + }; + ++static const struct cpu_addrcost_table hip12_addrcost_table = ++{ ++ { ++ 1, /* hi */ ++ 0, /* si */ ++ 0, /* di */ ++ 1, /* ti */ ++ }, ++ 0, /* pre_modify */ ++ 0, /* post_modify */ ++ 0, /* register_offset */ ++ 0, /* register_sextend */ ++ 0, /* register_zextend */ ++ 0, /* imm_offset */ ++}; ++ + static const struct cpu_addrcost_table qdf24xx_addrcost_table = + { + { +@@ -432,6 +448,16 @@ static const struct cpu_regmove_cost hip09_regmove_cost = + 2 /* FP2FP */ + }; + ++static const struct cpu_regmove_cost hip12_regmove_cost = ++{ ++ 1, /* GP2GP */ ++ /* Avoid the use of slow int<->fp moves for spilling by setting ++ their cost higher than memmov_cost. */ ++ 6, /* GP2FP */ ++ 2, /* FP2GP */ ++ 2 /* FP2FP */ ++}; ++ + /* Generic costs for vector insn classes. */ + static const struct cpu_vector_cost generic_vector_cost = + { +@@ -511,6 +537,25 @@ static const struct cpu_vector_cost hip09_vector_cost = + 1 /* cond_not_taken_branch_cost */ + }; + ++static const struct cpu_vector_cost hip12_vector_cost = ++{ ++ 1, /* scalar_int_stmt_cost */ ++ 2, /* scalar_fp_stmt_cost */ ++ 4, /* scalar_load_cost */ ++ 1, /* scalar_store_cost */ ++ 2, /* vec_int_stmt_cost */ ++ 2, /* vec_fp_stmt_cost */ ++ 2, /* vec_permute_cost */ ++ 2, /* vec_to_scalar_cost */ ++ 5, /* scalar_to_vec_cost */ ++ 8, /* vec_align_load_cost */ ++ 8, /* vec_unalign_load_cost */ ++ 1, /* vec_unalign_store_cost */ ++ 1, /* vec_store_cost */ ++ 1, /* cond_taken_branch_cost */ ++ 1, /* cond_not_taken_branch_cost */ ++}; ++ + /* Generic costs for vector insn classes. */ + static const struct cpu_vector_cost cortexa57_vector_cost = + { +@@ -685,6 +730,15 @@ static const cpu_prefetch_tune hip09_prefetch_tune = + -1 /* default_opt_level */ + }; + ++static const cpu_prefetch_tune hip12_prefetch_tune = ++{ ++ 0, /* num_slots */ ++ 128, /* l1_cache_size */ ++ 64, /* l1_cache_line_size */ ++ 1024, /* l2_cache_size */ ++ -1 /* default_opt_level */ ++}; ++ + static const struct tune_params generic_tunings = + { + &cortexa57_extra_costs, +@@ -1101,6 +1155,33 @@ static const struct tune_params hip09_tunings = + &hip09_prefetch_tune + }; + ++static const struct tune_params hip12_tunings = ++{ ++ &hip12_extra_costs, ++ &hip12_addrcost_table, ++ &hip12_regmove_cost, ++ &hip12_vector_cost, ++ &generic_branch_cost, ++ &generic_approx_modes, ++ 4, /* memmov_cost */ ++ 16, /* issue_rate */ ++ (AARCH64_FUSE_AES_AESMC | AARCH64_FUSE_ALU_BRANCH ++ | AARCH64_FUSE_ALU_CBZ), /* fusible_ops */ ++ 16, /* function_align. */ ++ 4, /* jump_align. */ ++ 8, /* loop_align. */ ++ 4, /* int_reassoc_width. */ ++ 4, /* fp_reassoc_width. */ ++ 4, /* vec_reassoc_width. */ ++ 2, /* min_div_recip_mul_sf. */ ++ 2, /* min_div_recip_mul_df. */ ++ 0, /* max_case_values. */ ++ tune_params::AUTOPREFETCHER_WEAK, /* autoprefetcher_model. */ ++ (AARCH64_EXTRA_TUNE_NONE), /* tune_flags. */ ++ &hip12_prefetch_tune ++}; ++ ++ + /* Support for fine-grained override of the tuning structures. */ + struct aarch64_tuning_override_function + { +@@ -1127,7 +1208,7 @@ struct processor + enum aarch64_processor sched_core; + enum aarch64_arch arch; + unsigned architecture_version; +- const unsigned long flags; ++ const uint64_t flags; + const struct tune_params *const tune; + }; + +@@ -7651,25 +7732,32 @@ static void + reset_machine_option (struct gcc_options *opts) + { + if (!(opts->x_optimize_maximum) +- || opts->x_aarch64_cpu_string == NULL +- || strstr (opts->x_aarch64_cpu_string, "hip09") == NULL) ++ || opts->x_aarch64_cpu_string == NULL ++ || (strstr (opts->x_aarch64_cpu_string, "hip09") == NULL ++ && strstr (opts->x_aarch64_cpu_string, "hip12") == NULL)) + { + return; + } +- + const char *ai_infer_level = getenv ("AI_INFER_LEVEL"); + if (ai_infer_level) + { ++ char *collect_gcc = getenv("COLLECT_GCC"); ++ const char* gcc_exec = basename(ASTRDUP(collect_gcc)); ++ ++ if (gcc_exec == NULL) ++ { ++ return; ++ } + override_optimize_options_1 (opts); +- if (lang_c_p ()) ++ if (strstr(gcc_exec, "gcc") != NULL) + { + override_C_optimize_options (opts); + } +- else if (lang_cpp_p ()) ++ else if (strstr(gcc_exec, "g++") != NULL) + { + override_CPP_optimize_options (opts); + } +- else if (lang_GNU_Fortran ()) ++ else if (strstr(gcc_exec, "gfortran") != NULL) + { + override_Fortran_optimize_options (opts); + } +@@ -10809,7 +10897,7 @@ static void initialize_aarch64_code_model (struct gcc_options *); + + static enum aarch64_parse_opt_result + aarch64_parse_arch (const char *to_parse, const struct processor **res, +- unsigned long *isa_flags) ++ uint64_t *isa_flags) + { + char *ext; + const struct processor *arch; +@@ -10834,7 +10922,7 @@ aarch64_parse_arch (const char *to_parse, const struct processor **res, + { + if (strlen (arch->name) == len && strncmp (arch->name, str, len) == 0) + { +- unsigned long isa_temp = arch->flags; ++ uint64_t isa_temp = arch->flags; + + if (ext != NULL) + { +@@ -10864,7 +10952,7 @@ aarch64_parse_arch (const char *to_parse, const struct processor **res, + + static enum aarch64_parse_opt_result + aarch64_parse_cpu (const char *to_parse, const struct processor **res, +- unsigned long *isa_flags) ++ uint64_t *isa_flags) + { + char *ext; + const struct processor *cpu; +@@ -10889,7 +10977,7 @@ aarch64_parse_cpu (const char *to_parse, const struct processor **res, + { + if (strlen (cpu->name) == len && strncmp (cpu->name, str, len) == 0) + { +- unsigned long isa_temp = cpu->flags; ++ uint64_t isa_temp = cpu->flags; + + + if (ext != NULL) +@@ -11348,7 +11436,7 @@ aarch64_print_hint_for_arch (const char *str) + + static bool + aarch64_validate_mcpu (const char *str, const struct processor **res, +- unsigned long *isa_flags) ++ uint64_t *isa_flags) + { + enum aarch64_parse_opt_result parse_res + = aarch64_parse_cpu (str, res, isa_flags); +@@ -11382,7 +11470,7 @@ aarch64_validate_mcpu (const char *str, const struct processor **res, + + static bool + aarch64_validate_march (const char *str, const struct processor **res, +- unsigned long *isa_flags) ++ uint64_t *isa_flags) + { + enum aarch64_parse_opt_result parse_res + = aarch64_parse_arch (str, res, isa_flags); +@@ -11494,8 +11582,8 @@ aarch64_convert_sve_vector_bits (aarch64_sve_vector_bits_enum value) + static void + aarch64_override_options (void) + { +- unsigned long cpu_isa = 0; +- unsigned long arch_isa = 0; ++ uint64_t cpu_isa = 0; ++ uint64_t arch_isa = 0; + aarch64_isa_flags = 0; + + bool valid_cpu = true; +@@ -11714,7 +11802,7 @@ aarch64_option_print (FILE *file, int indent, struct cl_target_option *ptr) + { + const struct processor *cpu + = aarch64_get_tune_cpu (ptr->x_explicit_tune_core); +- unsigned long isa_flags = ptr->x_aarch64_isa_flags; ++ uint64_t isa_flags = ptr->x_aarch64_isa_flags; + const struct processor *arch = aarch64_get_arch (ptr->x_explicit_arch); + std::string extension + = aarch64_get_extension_string_for_isa_flags (isa_flags, arch->flags); +@@ -11930,7 +12018,7 @@ static bool + aarch64_handle_attr_isa_flags (char *str) + { + enum aarch64_parse_opt_result parse_res; +- unsigned long isa_flags = aarch64_isa_flags; ++ uint64_t isa_flags = aarch64_isa_flags; + + /* We allow "+nothing" in the beginning to clear out all architectural + features if the user wants to handpick specific features. */ +@@ -14732,7 +14820,7 @@ aarch64_declare_function_name (FILE *stream, const char* name, + const struct processor *this_arch + = aarch64_get_arch (targ_options->x_explicit_arch); + +- unsigned long isa_flags = targ_options->x_aarch64_isa_flags; ++ uint64_t isa_flags = targ_options->x_aarch64_isa_flags; + std::string extension + = aarch64_get_extension_string_for_isa_flags (isa_flags, + this_arch->flags); +@@ -14773,7 +14861,7 @@ aarch64_start_file (void) + + const struct processor *default_arch + = aarch64_get_arch (default_options->x_explicit_arch); +- unsigned long default_isa_flags = default_options->x_aarch64_isa_flags; ++ uint64_t default_isa_flags = default_options->x_aarch64_isa_flags; + std::string extension + = aarch64_get_extension_string_for_isa_flags (default_isa_flags, + default_arch->flags); +diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h +index 4e15c1398..17fe8e5c5 100644 +--- a/gcc/config/aarch64/aarch64.h ++++ b/gcc/config/aarch64/aarch64.h +@@ -185,6 +185,12 @@ extern unsigned aarch64_architecture_version; + #define AARCH64_FL_SVE2_SHA3 (1ULL << 31) + #define AARCH64_FL_SVE2_BITPERM (1ULL << 32) + ++/* Transactional Memory Extension. */ ++#define AARCH64_FL_TME (1ULL << 33) /* Has TME instructions. */ ++ ++/* Armv8.6-A architecture extensions. */ ++#define AARCH64_FL_V8_6 (1ULL << 34) ++ + /* 8-bit Integer Matrix Multiply (I8MM) extensions. */ + #define AARCH64_FL_I8MM (1ULL << 35) + +@@ -197,6 +203,34 @@ extern unsigned aarch64_architecture_version; + /* 64-bit Floating-point Matrix Multiply (F64MM) extensions. */ + #define AARCH64_FL_F64MM (1ULL << 38) + ++/* Flag Manipulation Instructions (FLAGM) extension. */ ++#define AARCH64_FL_FLAGM (1ULL << 39) ++ ++/* Pointer Authentication (PAUTH) extension. */ ++#define AARCH64_FL_PAUTH (1ULL << 40) ++ ++/* Armv9.0-A. */ ++#define AARCH64_FL_V9 (1ULL << 41) /* Armv9.0-A Architecture. */ ++ ++/* 64-byte atomic load/store extensions. */ ++#define AARCH64_FL_LS64 (1ULL << 42) ++ ++/* Armv8.7-a architecture extensions. */ ++#define AARCH64_FL_V8_7 (1ULL << 43) ++ ++/* Hardware memory operation instructions. */ ++#define AARCH64_FL_MOPS (1ULL << 44) ++ ++/* Armv8.8-a architecture extensions. */ ++#define AARCH64_FL_V8_8 (1ULL << 45) ++ ++/* SVE2 instruction supported. */ ++#define AARCH64_FL_SVE2 (1 << 28) ++#define AARCH64_FL_SVE2_AES (1 << 29) ++#define AARCH64_FL_SVE2_SM4 (1 << 30) ++#define AARCH64_FL_SVE2_SHA3 (1ULL << 31) ++#define AARCH64_FL_SVE2_BITPERM (1ULL << 32) ++ + /* Has FP and SIMD. */ + #define AARCH64_FL_FPSIMD (AARCH64_FL_FP | AARCH64_FL_SIMD) + +@@ -218,6 +252,18 @@ extern unsigned aarch64_architecture_version; + #define AARCH64_FL_FOR_ARCH8_5 \ + (AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_V8_5 \ + | AARCH64_FL_SB | AARCH64_FL_SSBS | AARCH64_FL_PREDRES) ++#define AARCH64_FL_FOR_ARCH8_6 \ ++ (AARCH64_FL_FOR_ARCH8_5 | AARCH64_FL_V8_6 | AARCH64_FL_FPSIMD \ ++ | AARCH64_FL_I8MM | AARCH64_FL_BF16) ++#define AARCH64_FL_FOR_ARCH8_7 \ ++ (AARCH64_FL_FOR_ARCH8_6 | AARCH64_FL_V8_7 | AARCH64_FL_LS64) ++#define AARCH64_FL_FOR_ARCH9 \ ++ (AARCH64_FL_FOR_ARCH8_5 | AARCH64_FL_SVE | AARCH64_FL_SVE2 | AARCH64_FL_V9 \ ++ | AARCH64_FL_F16) ++#define AARCH64_FL_FOR_ARCH9_1 \ ++ (AARCH64_FL_FOR_ARCH8_6 | AARCH64_FL_FOR_ARCH9) ++#define AARCH64_FL_FOR_ARCH9_2 \ ++ (AARCH64_FL_FOR_ARCH8_7 | AARCH64_FL_FOR_ARCH9_1) + + /* Macros to test ISA flags. */ + +diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md +index e93dabf4d..ff2fc5c5d 100644 +--- a/gcc/config/aarch64/aarch64.md ++++ b/gcc/config/aarch64/aarch64.md +@@ -306,6 +306,7 @@ + (include "../arm/xgene1.md") + (include "thunderx2t99.md") + (include "hip09.md") ++(include "hip12.md") + + ;; ------------------------------------------------------------------- + ;; Jumps and other miscellaneous insns +diff --git a/gcc/config/aarch64/aarch64.opt b/gcc/config/aarch64/aarch64.opt +index a2c830066..d5a7af581 100644 +--- a/gcc/config/aarch64/aarch64.opt ++++ b/gcc/config/aarch64/aarch64.opt +@@ -31,7 +31,7 @@ TargetSave + const char *x_aarch64_override_tune_string + + TargetVariable +-unsigned long aarch64_isa_flags = 0 ++uint64_t aarch64_isa_flags = 0 + + TargetVariable + unsigned aarch64_enable_bti = 2 +diff --git a/gcc/config/aarch64/driver-aarch64.c b/gcc/config/aarch64/driver-aarch64.c +index 4c1e42edf..317802d6e 100644 +--- a/gcc/config/aarch64/driver-aarch64.c ++++ b/gcc/config/aarch64/driver-aarch64.c +@@ -33,7 +33,7 @@ std::string aarch64_get_extension_string_for_isa_flags (unsigned long, + struct aarch64_arch_extension + { + const char *ext; +- unsigned int flag; ++ uint64_t flag; + const char *feat_string; + }; + +@@ -53,7 +53,7 @@ struct aarch64_core_data + unsigned char implementer_id; /* Exactly 8 bits */ + unsigned int part_no; /* 12 bits + 12 bits */ + unsigned variant; +- const unsigned long flags; ++ const uint64_t flags; + }; + + #define AARCH64_BIG_LITTLE(BIG, LITTLE) \ +@@ -76,7 +76,7 @@ struct aarch64_arch_driver_info + { + const char* id; + const char* name; +- const unsigned long flags; ++ const uint64_t flags; + }; + + #define AARCH64_ARCH(NAME, CORE, ARCH_IDENT, ARCH_REV, FLAGS) \ +@@ -261,8 +261,8 @@ host_detect_local_cpu (int argc, const char **argv) + unsigned int variants[2] = { ALL_VARIANTS, ALL_VARIANTS }; + unsigned int n_variants = 0; + bool processed_exts = false; +- unsigned long extension_flags = 0; +- unsigned long default_flags = 0; ++ uint64_t extension_flags = 0; ++ uint64_t default_flags = 0; + std::string buf; + size_t sep_pos = -1; + char *fcpu_info; +diff --git a/gcc/config/aarch64/hip12.md b/gcc/config/aarch64/hip12.md +new file mode 100644 +index 000000000..859a87b97 +--- /dev/null ++++ b/gcc/config/aarch64/hip12.md +@@ -0,0 +1,891 @@ ++;; hip12 pipeline description ++;; Copyright (C) 2023 Free Software Foundation, Inc. ++;; ++;;Contributed by liyunfei ++;; ++;; This file is part of GCC. ++;; ++;; GCC is free software; you can redistribute it and/or modify it ++;; under the terms of the GNU General Public License as published by ++;; the Free Software Foundation; either version 3, or (at your option) ++;; any later version. ++;; ++;; GCC is distributed in the hope that it will be useful, but ++;; WITHOUT ANY WARRANTY; without even the implied warranty of ++;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++;; General Public License for more details. ++;; ++;; You should have received a copy of the GNU General Public License ++;; along with GCC; see the file COPYING3. If not see ++;; . ++ ++(define_automaton "hip12") ++(define_automaton "hip12_ldst") ++(define_automaton "hip12_v") ++ ++; The hip12 core is modelled as issues pipeline that has ++; the following functional units. ++; 1. 4 pipelines for single cycle integer micro operations: ALU0, ALU1, ALU3, ALU4 ++ ++(define_cpu_unit "hip12_alu0" "hip12") ++(define_cpu_unit "hip12_alu1" "hip12") ++(define_cpu_unit "hip12_alu3" "hip12") ++(define_cpu_unit "hip12_alu4" "hip12") ++ ++ (define_reservation "hip12_alu0134" "hip12_alu0|hip12_alu1|hip12_alu3|hip12_alu4") ++(define_reservation "hip12_alu14" "hip12_alu1|hip12_alu4") ++ ++; 2. 2 pipelines for multi cycles integer micro operations: ALU2, ALU5 ++ ++(define_cpu_unit "hip12_alu2" "hip12") ++(define_cpu_unit "hip12_alu5" "hip12") ++ ++(define_reservation "hip12_alu25" "hip12_alu2|hip12_alu5") ++(define_reservation "hip12_alu1425" "hip12_alu1|hip12_alu4|hip12_alu2|hip12_alu5") ++ ++; 3. All ALU pipelines ++ ++(define_reservation "hip12_alu" "hip12_alu0|hip12_alu1|hip12_alu2|hip12_alu3|hip12_alu4|hip12_alu5") ++ ++; 4. 3 pipelines for load micro opetations: Load0, Load1, Load2 ++ ++(define_cpu_unit "hip12_load0" "hip12_ldst") ++(define_cpu_unit "hip12_load1" "hip12_ldst") ++(define_cpu_unit "hip12_load2" "hip12_ldst") ++ ++(define_reservation "hip12_ld" "hip12_load0|hip12_load1|hip12_load2") ++ ++; 5. 2 pipelines for store micro operations: Store1, Store2 ++ ++(define_cpu_unit "hip12_store0" "hip12_ldst") ++(define_cpu_unit "hip12_store1" "hip12_ldst") ++ ++(define_reservation "hip12_st" "hip12_store0|hip12_store1") ++ ++; 6. 2 pipelines for store data micro operations: STD0, STD1 ++ ++(define_cpu_unit "hip12_store_data0" "hip12_ldst") ++(define_cpu_unit "hip12_store_data1" "hip12_ldst") ++ ++(define_reservation "hip12_std" "hip12_store_data0|hip12_store_data1") ++ ++; 7. 4 asymmetric pipelines for Asimd/FP/SVE micro operations: V0, V1, V2, V3 ++ ++(define_cpu_unit "hip12_v0" "hip12_v") ++(define_cpu_unit "hip12_v1" "hip12_v") ++(define_cpu_unit "hip12_v2" "hip12_v") ++(define_cpu_unit "hip12_v3" "hip12_v") ++ ++(define_reservation "hip12_v0123" "hip12_v0|hip12_v1|hip12_v2|hip12_v3") ++(define_reservation "hip12_v02" "hip12_v0|hip12_v2") ++ ++; 8. 2 pipelines for branch operations: Branch0, Branch1 ++ ++(define_cpu_unit "hip12_b0" "hip12") ++(define_cpu_unit "hip12_b1" "hip12") ++ ++(define_reservation "hip12_b" "hip12_b0|hip12_b1") ++ ++;; Block all issue queues. ++ ++(define_reservation "hip12_block" " ++ hip12_alu0+hip12_alu1+hip12_alu2+hip12_alu3 ++ +hip12_alu4+hip12_alu5+hip12_load0+hip12_load1+hip12_load2+hip12_store0+hip12_store1+hip12_store_data0+hip12_store_data1+hip12_v0+hip12_v1+hip12_v2+hip12_v3") ++ ++;; Branch execution Unit ++ ++(define_insn_reservation "hip12_branch" 1 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "branch")) ++ "hip12_b") ++ ++(define_insn_reservation "hip12_branch_and_link" 1 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "call")) ++ "hip12_b+hip12_alu14") ++ ++;; Integer arithmetic/logic instructions. ++ ++(define_insn_reservation "hip12_alu_basic" 1 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "alu_imm,alu_sreg,\ ++ adc_reg,adc_imm")) ++ "hip12_alu") ++ ++(define_insn_reservation "hip12_alu_basic_flagset" 1 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "alus_imm,alus_sreg,\ ++ adcs_reg,adcs_imm")) ++ "hip12_alu1425") ++ ++(define_insn_reservation "hip12_alu_basic_extend" 2 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "alu_ext,alus_ext,\ ++ alu_shift_imm,\ ++ alu_shift_reg,alus_shift_imm,alus_shift_reg")) ++ "hip12_alu25") ++ ++(define_insn_reservation "hip12_alu_logical" 1 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "logic_reg,logic_imm")) ++ "hip12_alu") ++ ++(define_insn_reservation "hip12_alu_logical_imm" 1 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "logic_imm")) ++ "hip12_alu14") ++ ++(define_insn_reservation "hip12_alu_logical_flagset" 1 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "logics_reg")) ++ "hip12_alu1425") ++ ++(define_insn_reservation "hip12_alu_logical_flagset_imm" 2 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "logics_imm")) ++ "hip12_alu25") ++ ++(define_insn_reservation "hip12_alu_conditional" 1 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "csel")) ++ "hip12_alu14") ++ ++;; Divide and Multiply instructions. ++ ++(define_insn_reservation "hip12_divide" 8 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "sdiv,udiv")) ++ "hip12_alu25") ++ ++(define_insn_reservation "hip12_multiply" 3 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "mul,muls")) ++ "hip12_alu25") ++ ++(define_insn_reservation "hip12_multiply_long" 2 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "smull,umull,smulls,umulls")) ++ "hip12_alu25") ++ ++(define_insn_reservation "hip12_multiply_accumulate" 4 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "mla,mlas")) ++ "hip12_alu25+hip12_alu0134") ++ ++(define_insn_reservation "hip12_multiply_accumulate_long" 3 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "smlal,umlal")) ++ "hip12_alu25+hip12_alu0134") ++ ++;; no Pointer Authentication instructions in backend types. ++ ++;; Miscellaneous Data-Processing instructions. ++ ++(define_insn_reservation "hip12_address" 1 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "adr")) ++ "hip12_alu14") ++ ++(define_insn_reservation "hip12_bitfield" 1 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "bfm,bfx")) ++ "hip12_alu14") ++ ++;; Todo: Does hip12 have reg move or mvn instructions? ++(define_insn_reservation "hip12_move" 1 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "mov_imm,mov_shift_reg")) ++ "hip12_alu") ++ ++(define_insn_reservation "hip12_count_leading" 1 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "clz")) ++ "hip12_alu14") ++ ++(define_insn_reservation "hip12_reverse_bits_bytes" 1 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "rbit,rev")) ++ "hip12_alu14") ++ ++; Todo: Does hip12 have imm shift instructions? ++(define_insn_reservation "hip12_variable_shift" 1 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "shift_reg")) ++ "hip12_alu14") ++ ++; Block all issue pipes for a cycle ++(define_insn_reservation "hip12_block" 1 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "block")) ++ "hip12_block") ++ ++;; Load and Store instructions. ++ ++(define_insn_reservation "hip12_load_register" 4 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "load_4,load_8")) ++ "hip12_ld") ++ ++(define_insn_reservation "hip12_load_pair" 4 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "load_16")) ++ "hip12_ld") ++ ++(define_insn_reservation "hip12_store" 1 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "store_4,store_8")) ++ "hip12_st+hip12_std") ++ ++(define_insn_reservation "hip12_store_pair" 1 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "store_16")) ++ "hip12_st+hip12_std") ++ ++;; FP Data Processing instructions. ++; abs/neg/cpy ++(define_insn_reservation "hip12_fp_arith" 1 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "ffariths,ffarithd")) ++ "hip12_v0123") ++ ++(define_insn_reservation "hip12_fp_compare" 2 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "fcmpd,fcmps")) ++ "hip12_v02+hip12_alu0134") ++ ++(define_insn_reservation "hip12_fp_conditional_compare" 4 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "fccmpd,fccmps")) ++ "hip12_alu14,hip12_v0123") ++ ++(define_insn_reservation "hip12_fp_conditional_select" 6 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "fcsel")) ++ "hip12_alu14,hip12_v0123") ++ ++(define_insn_reservation "hip12_fp_divide_single" 6 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "fdivs")) ++ "hip12_v0123") ++ ++(define_insn_reservation "hip12_fp_divide_double" 8 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "fdivd")) ++ "hip12_v0123") ++ ++(define_insn_reservation "hip12_fp_square_single" 6 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "fsqrts")) ++ "hip12_v0123") ++ ++(define_insn_reservation "hip12_fp_square_double" 8 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "fsqrtd")) ++ "hip12_v0123") ++ ++(define_insn_reservation "hip12_fp_fused_multiply_add" 4 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "ffmad,ffmas")) ++ "hip12_v0123") ++ ++(define_insn_reservation "hip12_fp_max_min" 2 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "f_minmaxd,f_minmaxs")) ++ "hip12_v0123") ++ ++(define_insn_reservation "hip12_fp_add" 2 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "fadds,faddd")) ++ "hip12_v0123") ++ ++(define_insn_reservation "hip12_fp_multiply" 3 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "fmuld,fmuls")) ++ "hip12_v0123") ++ ++(define_insn_reservation "hip12_fp_round_int" 3 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "f_rintd,f_rints")) ++ "hip12_v0123") ++ ++;; FP Miscellaneous instructions. ++ ++(define_insn_reservation "hip12_fp_covert_i2f" 7 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "f_cvti2f")) ++ "hip12_alu14,hip12_v0123") ++ ++(define_insn_reservation "hip12_fp_covert_f2i" 5 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "f_cvtf2i")) ++ "hip12_v0123") ++ ++(define_insn_reservation "hip12_fp_covert_f2f" 3 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "f_cvt")) ++ "hip12_v0123") ++ ++(define_insn_reservation "hip12_fp_move" 2 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "fmov")) ++ "hip12_v0123") ++ ++(define_insn_reservation "hip12_fp_transfer_arm2vfp" 4 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "f_mcr")) ++ "hip12_alu14") ++ ++; transfer low half + high half ++(define_insn_reservation "hip12_fp_transfer_2arm2vfp" 10 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "f_mcrr")) ++ "hip12_alu14,nothing*3,hip12_alu14,hip12_v0123") ++ ++(define_insn_reservation "hip12_fp_transfer_vfp2arm" 2 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "f_mrc,f_mrrc")) ++ "hip12_v0123") ++ ++;; FP Load instructions. ++; only basic double/single load ++(define_insn_reservation "hip12_fp_load" 6 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "f_loadd,f_loads")) ++ "hip12_ld") ++ ++(define_insn_reservation "hip12_fp_load_vector_pair" 6 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_ldr,neon_ldp,neon_ldp_q")) ++ "hip12_alu+hip12_ld") ++ ++;; FP Store instructions. ++; only basic double/single store ++(define_insn_reservation "hip12_fp_store" 1 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "f_stored,f_stores")) ++ "hip12_st+hip12_std") ++ ++(define_insn_reservation "hip12_fp_store_vector" 3 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_ldr")) ++ "hip12_alu+hip12_st+hip12_std") ++ ++(define_insn_reservation "hip12_fp_store_pair" 1 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_ldp,neon_ldp_q")) ++ "hip12_st+hip12_std+hip12_alu") ++ ++;; ASIMD Int instructions. ++ ++(define_insn_reservation "hip12_neon_absolute_diff" 2 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_abd,neon_abd_q,neon_abd_long")) ++ "hip12_v0123") ++ ++(define_insn_reservation "hip12_neon_arith_basic" 1 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_abs,neon_abs_q,\ ++ neon_add,neon_add_q,\ ++ neon_sub,neon_sub_q,\ ++ neon_neg,neon_neg_q")) ++ "hip12_v0123") ++ ++(define_insn_reservation "hip12_neon_arith_long" 2 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_add_long,neon_sub_long")) ++ "hip12_v0123") ++ ++(define_insn_reservation "hip12_neon_arith_wide" 1 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_add_widen,neon_sub_widen")) ++ "hip12_v0123") ++ ++(define_insn_reservation "hip12_neon_arith_complex" 2 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_qadd,neon_qadd_q,\ ++ neon_qsub,neon_qsub_q,\ ++ neon_qneg,neon_qneg_q,\ ++ neon_qabs,neon_qabs_q")) ++ "hip12_v0123") ++; arith pair not specified ++ ++; neon_reduc_add is used for both addp and [su]adalp ++(define_insn_reservation "hip12_neon_arith_reduce" 3 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_reduc_add,neon_reduc_add_q")) ++ "hip12_v0123") ++ ++(define_insn_reservation "hip12_neon_arith_cmp" 2 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_compare,neon_compare_q,neon_compare_zero,\ ++ neon_tst,neon_tst_q")) ++ "hip12_v0123") ++ ++(define_insn_reservation "hip12_neon_arith_dot" 3 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_dot,neon_dot_q")) ++ "hip12_v0123") ++ ++(define_insn_reservation "hip12_neon_logical" 1 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_logic,neon_logic_q")) ++ "hip12_v0123") ++ ++(define_insn_reservation "hip12_neon_multiply_accumulate" 3 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_mla_b,neon_mla_b_q,\ ++ neon_mla_h,neon_mla_h_q,\ ++ neon_mla_s,neon_mla_s_q,\ ++ neon_mla_b_long,neon_mla_h_long,\ ++ neon_mla_s_long,neon_mla_h_scalar,\ ++ neon_mla_h_scalar_q,neon_mla_s_scalar,\ ++ neon_mla_s_scalar_q,neon_mla_h_scalar_long,\ ++ neon_mla_s_scalar_long,neon_sat_mla_b_long,\ ++ neon_sat_mla_h_long,neon_sat_mla_s_long,\ ++ neon_sat_mla_h_scalar_long,neon_sat_mla_s_scalar_long")) ++ "hip12_v0123") ++ ++(define_insn_reservation "hip12_neon_minmax" 2 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_minmax,neon_minmax_q")) ++ "hip12_v0123") ++ ++(define_insn_reservation "hip12_neon_minmax_reduce" 2 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_reduc_minmax,neon_reduc_minmax_q")) ++ "hip12_v0123") ++ ++(define_insn_reservation "hip12_neon_multiply" 3 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_mul_b,neon_mul_b_q,\ ++ neon_mul_h,neon_mul_h_q,\ ++ neon_mul_s,neon_mul_s_q,\ ++ neon_mul_b_long,neon_mul_h_long,\ ++ neon_mul_s_long,neon_mul_d_long,\ ++ neon_mul_h_scalar,neon_mul_h_scalar_q,\ ++ neon_mul_s_scalar,neon_mul_s_scalar_q,\ ++ neon_mul_h_scalar_long,neon_mul_s_scalar_long,\ ++ neon_sat_mul_b,neon_sat_mul_b_q,\ ++ neon_sat_mul_h,neon_sat_mul_h_q,\ ++ neon_sat_mul_s,neon_sat_mul_s_q,\ ++ neon_sat_mul_b_long,neon_sat_mul_h_long,\ ++ neon_sat_mul_s_long,neon_sat_mul_h_scalar,\ ++ neon_sat_mul_h_scalar_q,neon_sat_mul_s_scalar,\ ++ neon_sat_mul_s_scalar_q,neon_sat_mul_h_scalar_long,\ ++ neon_sat_mul_s_scalar_long")) ++ "hip12_v0123") ++ ++(define_insn_reservation "hip12_neon_shift" 2 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_shift_imm,neon_shift_imm_q,\ ++ neon_shift_imm_narrow_q,neon_shift_imm_long,\ ++ neon_shift_reg,neon_shift_reg_q,\ ++ neon_sat_shift_imm,neon_sat_shift_imm_q,\ ++ neon_sat_shift_imm_narrow_q,neon_sat_shift_reg,\ ++ neon_sat_shift_reg_q")) ++ "hip12_v0123") ++ ++(define_insn_reservation "hip12_neon_shift_accumulate" 3 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_shift_acc,neon_shift_acc_q")) ++ "hip12_v0123") ++ ++;; ASIMD FP instructions. ++ ++(define_insn_reservation "hip12_neon_fp_abs" 1 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_fp_abs_s,neon_fp_abs_s_q,\ ++ neon_fp_abs_d,neon_fp_abs_d_q")) ++ "hip12_v0123") ++ ++(define_insn_reservation "hip12_neon_fp_neg" 1 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_fp_neg_s,neon_fp_neg_s_q,\ ++ neon_fp_neg_d,neon_fp_neg_d_q")) ++ "hip12_v0123") ++ ++(define_insn_reservation "hip12_neon_fp_abd" 2 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_fp_abd_s,neon_fp_abd_s_q,\ ++ neon_fp_abd_d,neon_fp_abd_d_q")) ++ "hip12_v0123") ++ ++(define_insn_reservation "hip12_neon_fp_arith" 2 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_fp_addsub_s,neon_fp_addsub_s_q,\ ++ neon_fp_addsub_d,neon_fp_addsub_d_q")) ++ "hip12_v0123") ++ ++(define_insn_reservation "hip12_neon_fp_compare" 2 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_fp_compare_s,neon_fp_compare_s_q,\ ++ neon_fp_compare_d,neon_fp_compare_d_q")) ++ "hip12_v0123") ++ ++(define_insn_reservation "hip12_neon_fp_convert_narrow" 4 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_fp_cvt_narrow_s_q,neon_fp_cvt_narrow_d_q")) ++ "hip12_v0123") ++ ++(define_insn_reservation "hip12_neon_fp_convert_2int" 3 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_fp_to_int_s,neon_fp_to_int_d")) ++ "hip12_v0123") ++ ++(define_insn_reservation "hip12_neon_fp_convert_2int_q" 4 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_fp_to_int_s_q,neon_fp_to_int_d_q")) ++ "hip12_v0123") ++ ++(define_insn_reservation "hip12_neon_fp_convert_from_int" 3 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_int_to_fp_s,neon_int_to_fp_d")) ++ "hip12_v0123") ++ ++(define_insn_reservation "hip12_neon_fp_convert_from_int_q" 4 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_int_to_fp_s_q,neon_int_to_fp_d_q")) ++ "hip12_v0123") ++ ++; D/F32 ++(define_insn_reservation "hip12_neon_fp_divide_s" 6 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_fp_div_s")) ++ "hip12_v0123") ++ ++; Q/F32 ++(define_insn_reservation "hip12_neon_fp_divide_s_q" 7 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_fp_div_s_q")) ++ "hip12_v0123") ++ ++; Q/F64 ++(define_insn_reservation "hip12_neon_fp_divide_d" 9 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_fp_div_d,neon_fp_div_d_q")) ++ "hip12_v0123") ++ ++; D/F32 ++(define_insn_reservation "hip12_neon_fp_sqrt_s" 6 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_fp_sqrt_s")) ++ "hip12_v0123") ++ ++; Q/F32 ++(define_insn_reservation "hip12_neon_fp_sqrt_s_q" 7 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_fp_sqrt_s_q")) ++ "hip12_v0123") ++ ++; Q/F64 ++(define_insn_reservation "hip12_neon_fp_sqrt_d" 9 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_fp_sqrt_d,neon_fp_sqrt_d_q")) ++ "hip12_v0123") ++ ++(define_insn_reservation "hip12_neon_fp_minmax" 2 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_fp_minmax_s,neon_fp_minmax_s_q,\ ++ neon_fp_minmax_d,neon_fp_minmax_d_q")) ++ "hip12_v0123") ++ ++(define_insn_reservation "hip12_neon_fp_minmax_reduce" 3 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_fp_reduc_minmax_s,neon_fp_reduc_minmax_s_q,\ ++ neon_fp_reduc_minmax_d,neon_fp_reduc_minmax_d_q")) ++ "hip12_v0123") ++ ++(define_insn_reservation "hip12_neon_fp_multiply" 3 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_fp_mul_s,neon_fp_mul_s_q,\ ++ neon_fp_mul_s_scalar,neon_fp_mul_s_scalar_q,\ ++ neon_fp_mul_d,neon_fp_mul_d_q,\ ++ neon_fp_mul_d_scalar_q")) ++ "hip12_v0123") ++ ++(define_insn_reservation "hip12_neon_fp_multiply_add" 4 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_fp_mla_s,neon_fp_mla_s_q,\ ++ neon_fp_mla_s_scalar,neon_fp_mla_s_scalar_q,\ ++ neon_fp_mla_d,neon_fp_mla_d_q,\ ++ neon_fp_mla_d_scalar_q")) ++ "hip12_v0123") ++ ++(define_insn_reservation "hip12_neon_fp_round" 3 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_fp_round_s,neon_fp_round_d")) ++ "hip12_v0123") ++ ++(define_insn_reservation "hip12_neon_fp_round_q" 4 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_fp_round_s_q,neon_fp_round_d_q")) ++ "hip12_v0123") ++ ++;; ASIMD Miscellaneous instructions ++ ++(define_insn_reservation "hip12_neon_bit_reverse" 1 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_rbit,neon_rbit_q")) ++ "hip12_v0123") ++ ++(define_insn_reservation "hip12_neon_bitwise_insert" 1 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_bsl,neon_bsl_q")) ++ "hip12_v0123") ++ ++(define_insn_reservation "hip12_neon_count" 1 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_cls,neon_cls_q")) ++ "hip12_v0123") ++ ++(define_insn_reservation "hip12_neon_count_ds" 2 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_cnt_q")) ++ "hip12_v0123") ++ ++(define_insn_reservation "hip12_neon_count_bh" 1 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_cnt")) ++ "hip12_v0123") ++ ++(define_insn_reservation "hip12_neon_duplicate" 6 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_dup,neon_dup_q")) ++ "(hip12_v0123)+hip12_alu0134") ++ ++(define_insn_reservation "hip12_neon_extract" 2 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_dup,neon_dup_q")) ++ "hip12_v0123") ++ ++(define_insn_reservation "hip12_neon_insert" 2 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_ins,neon_ins_q")) ++ "hip12_v0123") ++ ++(define_insn_reservation "hip12_neon_move" 2 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_move,neon_move_q,neon_move_narrow_q")) ++ "hip12_v0123") ++ ++; gcc only gen neon fp recp ++(define_insn_reservation "hip12_neon_fp_recp" 3 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_fp_recpe_s,neon_fp_recpe_d,\ ++ neon_fp_rsqrte_s,neon_fp_rsqrte_d")) ++ "hip12_v0123") ++ ++(define_insn_reservation "hip12_neon_fp_recp_q" 4 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_fp_recpe_s_q,neon_fp_recpe_d_q,\ ++ neon_fp_rsqrte_s_q,neon_fp_rsqrte_d_q")) ++ "hip12_v0123") ++ ++(define_insn_reservation "hip12_neon_fp_recpx" 3 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_fp_recpx_s,neon_fp_recpx_s_q,\ ++ neon_fp_recpx_d,neon_fp_recpx_d_q")) ++ "hip12_v0123") ++ ++(define_insn_reservation "hip12_neon_fp_recps" 4 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_fp_recps_s,neon_fp_recps_s_q,\ ++ neon_fp_recps_d,neon_fp_recps_d_q,\ ++ neon_fp_rsqrts_s,neon_fp_rsqrts_s_q,\ ++ neon_fp_rsqrts_d,neon_fp_rsqrts_d_q")) ++ "hip12_v0123") ++ ++(define_insn_reservation "hip12_neon_rev" 2 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_rev,neon_rev_q")) ++ "hip12_v0123") ++ ++(define_insn_reservation "hip12_neon_tbl_12" 2 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_tbl1,neon_tbl1_q,\ ++ neon_tbl2,neon_tbl2_q")) ++ "hip12_v0123") ++ ++(define_insn_reservation "hip12_neon_tbl_3" 4 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_tbl3,neon_tbl3_q,\ ++ neon_tbl2,neon_tbl2_q")) ++ "hip12_v0123") ++ ++(define_insn_reservation "hip12_neon_tbl_4" 4 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_tbl4,neon_tbl4_q,\ ++ neon_tbl2,neon_tbl2_q")) ++ "hip12_v0123") ++; gcc only gen neon tbl, no tbx ++ ++; no neon transfer specified ++ ++(define_insn_reservation "hip12_neon_zip" 2 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_zip,neon_zip_q")) ++ "hip12_v0123") ++ ++;; ASIMD Load instructions. ++ ++(define_insn_reservation "hip12_neon_ld1_12reg" 6 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_load1_1reg,neon_load1_1reg_q,\ ++ neon_load1_2reg,neon_load1_2reg_q")) ++ "hip12_ld") ++ ++(define_insn_reservation "hip12_neon_ld1_34reg" 7 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_load1_3reg,neon_load1_3reg_q,\ ++ neon_load1_4reg,neon_load1_4reg_q")) ++ "hip12_ld") ++ ++(define_insn_reservation "hip12_neon_ld1_lane" 8 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_load1_all_lanes,neon_load1_all_lanes_q,\ ++ neon_load1_one_lane,neon_load1_one_lane_q")) ++ "hip12_ld+(hip12_v0123)") ++ ++(define_insn_reservation "hip12_neon_ld2" 8 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_load2_2reg,neon_load2_2reg_q,\ ++ neon_load2_4reg,neon_load2_4reg_q,\ ++ neon_load2_all_lanes,neon_load2_all_lanes_q,\ ++ neon_load2_one_lane,neon_load2_one_lane_q")) ++ "(hip12_ld)+(hip12_v0123)") ++ ++(define_insn_reservation "hip12_neon_ld3" 8 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_load3_3reg,neon_load3_3reg_q,\ ++ neon_load3_all_lanes,neon_load3_all_lanes_q,\ ++ neon_load3_one_lane,neon_load3_one_lane_q")) ++ "hip12_ld+hip12_v0123") ++ ++(define_insn_reservation "hip12_neon_ld4_reg" 10 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_load4_4reg,neon_load4_4reg_q")) ++ "hip12_ld+hip12_v0123") ++ ++(define_insn_reservation "hip12_neon_ld4_lane" 8 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_load4_all_lanes,neon_load4_all_lanes_q,\ ++ neon_load4_one_lane,neon_load4_one_lane_q")) ++ "hip12_ld+hip12_v0123") ++ ++;; ASIMD Load instructions. ++ ++(define_insn_reservation "hip12_neon_st1_12reg_4reg" 1 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_store1_1reg,neon_store1_1reg_q,\ ++ neon_store1_2reg,neon_store1_2reg_q,\ ++ neon_store1_4reg")) ++ "hip12_st+hip12_std+hip12_v0123") ++ ++(define_insn_reservation "hip12_neon_st1_3reg" 1 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_store1_3reg,neon_store1_3reg_q")) ++ "hip12_st+hip12_std+hip12_v0123") ++ ++(define_insn_reservation "hip12_neon_st1_4reg_q" 4 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_store1_4reg_q")) ++ "hip12_st+hip12_std") ++ ++(define_insn_reservation "hip12_neon_st1_lane_st2" 1 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_store1_one_lane,neon_store1_one_lane_q,\ ++ neon_store2_2reg,neon_store2_2reg_q,\ ++ neon_store2_4reg,neon_store2_4reg_q,\ ++ neon_store2_one_lane,neon_store2_one_lane_q")) ++ "hip12_st+hip12_std") ++ ++(define_insn_reservation "hip12_neon_st3_st4_q" 4 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_store3_3reg,neon_store3_3reg_q,\ ++ neon_store3_one_lane,neon_store3_one_lane_q,\ ++ neon_store4_4reg_q")) ++ "hip12_v0123+hip12_st+hip12_std") ++ ++(define_insn_reservation "hip12_neon_st4" 4 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "neon_store4_4reg,\ ++ neon_store4_one_lane,neon_store4_one_lane_q")) ++ "hip12_v0123+hip12_st+hip12_std") ++ ++;; Cryptography Extensions ++ ++(define_insn_reservation "hip12_crypto_aes" 2 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "crypto_aese,crypto_aesmc")) ++ "hip12_v0123") ++ ++(define_insn_reservation "hip12_crypto_pmull" 2 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "crypto_pmull")) ++ "hip12_v0123") ++ ++(define_insn_reservation "hip12_crypto_sha1_fast" 2 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "crypto_sha1_fast,crypto_sha1_xor")) ++ "hip12_v0123") ++ ++(define_insn_reservation "hip12_crypto_sha256_fast" 2 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "crypto_sha256_fast")) ++ "hip12_v02") ++ ++(define_insn_reservation "hip12_crypto_complex_1" 4 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "crypto_sha1_slow")) ++ "hip12_v0123") ++ ++(define_insn_reservation "hip12_crypto_complex_256" 4 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "crypto_sha256_slow")) ++ "hip12_v02") ++ ++(define_insn_reservation "hip12_crypto_sha512" 2 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "crypto_sha512")) ++ "hip12_v02") ++ ++(define_insn_reservation "hip12_crypto_sha3" 2 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "crypto_sha3")) ++ "hip12_v0123") ++ ++(define_insn_reservation "hip12_crypto_sm3" 2 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "crypto_sm3")) ++ "hip12_v02") ++ ++(define_insn_reservation "hip12_crypto_sm4" 4 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "crypto_sm4")) ++ "hip12_v0123") ++ ++;; CRC instructions ++ ++(define_insn_reservation "hip12_crc" 2 ++ (and (eq_attr "tune" "hip12") ++ (eq_attr "type" "crc")) ++ "hip12_alu25") ++ ++;; Simple execution unit bypasses ++(define_bypass 2 "hip12_fp_fused_multiply_add" ++ "hip12_fp_fused_multiply_add") ++ ++(define_bypass 2 "hip12_neon_arith_dot" ++ "hip12_neon_arith_dot") ++ ++(define_bypass 2 "hip12_neon_multiply_accumulate" ++ "hip12_neon_multiply_accumulate") ++ ++(define_bypass 1 "hip12_neon_shift_accumulate" ++ "hip12_neon_shift_accumulate") ++ ++(define_bypass 2 "hip12_neon_fp_multiply_add" ++ "hip12_neon_fp_multiply_add") ++ ++(define_bypass 2 "hip12_neon_fp_recps" ++ "hip12_neon_fp_recps") +\ No newline at end of file +diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi +index 4e7b657a9..5be6e0399 100644 +--- a/gcc/doc/invoke.texi ++++ b/gcc/doc/invoke.texi +@@ -15090,6 +15090,17 @@ generation. This option is enabled by default for @option{-march=armv8.5-a}. + Enable the Armv8-a Execution and Data Prediction Restriction instructions. + This option is only to enable the extension at the assembler level and does + not affect code generation. This option is enabled by default for ++@item sve2 ++Enable the Armv8-a Scalable Vector Extension 2. This also enables SVE ++instructions. ++@item bitperm ++Enable SVE2 bitperm instructions. This also enables SVE2 instructions. ++@item sve2-sm4 ++Enable SVE2 sm4 instructions. This also enables SVE2 instructions. ++@item sve2-aes ++Enable SVE2 aes instructions. This also enables SVE2 instructions. ++@item sve2-sha3 ++Enable SVE2 sha3 instructions. This also enables SVE2 instructions. + @option{-march=armv8.5-a}. + + @end table +diff --git a/gcc/ipa-hardware-detection.c b/gcc/ipa-hardware-detection.c +index 79a4ce9c4..a477580fc 100644 +--- a/gcc/ipa-hardware-detection.c ++++ b/gcc/ipa-hardware-detection.c +@@ -73,7 +73,7 @@ create_part_bb (basic_block last_bb, tree part_base) + &gsi, PLUS_EXPR, unsigned_type_node, part_base, + build_int_cst (unsigned_type_node, 4294963967)); + gcond *cond = gimple_build_cond (LE_EXPR, part_cond, +- build_int_cst (unsigned_type_node, 2), ++ build_int_cst (unsigned_type_node, 128), + NULL_TREE, NULL_TREE); + gimple_set_location (cond, input_location); + gsi_insert_before (&gsi, cond, GSI_SAME_STMT); +diff --git a/gcc/optimizer.fdata b/gcc/optimizer.fdata +new file mode 100644 +index 000000000..09e709df7 +--- /dev/null ++++ b/gcc/optimizer.fdata +@@ -0,0 +1 @@ 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3e5014f03ea804d53b5c58c3be1d3bc1be4e79e13e866fbcbe4152be3b450e0bbffb8ec1bebcd0ee3eae0bed3e96b02b3cde2ac1beaef3bebea772de3e053ebabef83a1a3c90110abf7b991440cfbf1ec005981dc0a8a82dc1e87c144080861240bdfd13c077610f401aef1bc1f11c54409c2f44bd9608803fdb1a7e3f2703813f10a857bdeca936bdaa7a6e3fa5b764bd8d2a743f650913be167021c0 +\ No newline at end of file +diff --git a/gcc/opts-common.c b/gcc/opts-common.c +index a55499ab2..f4ab65477 100644 +--- a/gcc/opts-common.c ++++ b/gcc/opts-common.c +@@ -842,19 +842,6 @@ opts_concat (const char *first, ...) + return newstr; + } + +-static int64_t +-ai_infer_optimization (int argc, const char **argv, +- const char *mcpu_option, +- int argc_hw, int64_t *argv_hw) +-{ +- /* Load dependent AI-framework libraries. */ +- int model_pred = graph_infer (argc, argv, mcpu_option, argc_hw, argv_hw); +- +- if (model_pred == 1) +- putenv ("AI_INFER_LEVEL=1"); +- return model_pred; +-} +- + static int + handle_lto_option (unsigned int lang_mask, + unsigned int num_decoded_options, +@@ -906,14 +893,27 @@ handle_machine_option (unsigned int lang_mask, + int ret = 0; + bool flag_Om = false; + bool flag_hip09 = false; ++ bool flag_hip12 = false; ++ char mcpu_name[64]; + for (unsigned i = 1; i < argc; i ++) + { + if (strcmp (argv[i], "-Om") == 0) +- flag_Om = true; ++ { ++ flag_Om = true; ++ } + if (strstr (argv[i], "mcpu=hip09") != NULL) +- flag_hip09 = true; ++ { ++ flag_hip09 = true; ++ strcpy(mcpu_name, "hip09"); ++ } ++ if (strstr (argv[i], "mcpu=hip12") != NULL) ++ { ++ flag_hip12 = true; ++ strcpy(mcpu_name, "hip12"); ++ } + } +- if (!flag_hip09 || !flag_Om) ++ ++ if (!(flag_hip09 || flag_hip12) || !flag_Om) + { + return ret; + } +@@ -931,8 +931,8 @@ handle_machine_option (unsigned int lang_mask, + PARAM_VALUE_L2_CACHE_SIZE, + PARAM_VALUE_PREFETCH_LATENCY, + PARAM_VALUE_PREFETCH_MIN_INSN_TO_MEM_RATIO}; +- int64_t output_pred = ai_infer_optimization ( +- argc, argv, "hip09", argc_hw, argv_hw); ++ int64_t output_pred = get_optimize_decision_from_optimizer ( ++ argc, argv, mcpu_name, argc_hw, argv_hw); + if (output_pred != 1) + { + return ret; diff --git a/SPECS/gcc.spec b/SPECS/gcc.spec index aef0c04..134d21b 100644 --- a/SPECS/gcc.spec +++ b/SPECS/gcc.spec @@ -5,7 +5,7 @@ %global gcc_major 8 # Note, gcc_release must be integer, if you want to add suffixes to # %%{release}, append them after %%{gcc_release} on Release: line. -%global gcc_release 26 +%global gcc_release 27 %global nvptx_tools_gitrev c28050f60193b3b95a18866a96f03334e874e78f %global nvptx_newlib_gitrev aadc8eb0ec43b7cd0dd2dfb484bae63c8b05ef24 %global _unpackaged_files_terminate_build 0 @@ -105,7 +105,7 @@ Summary: Various compilers (C, C++, Objective-C, ...) Name: gcc Version: %{gcc_version} -Release: %{gcc_release}%{?dist}.ap.2 +Release: %{gcc_release}%{?dist}.ap.3 # libgcc, libgfortran, libgomp, libstdc++ and crtstuff have # GCC Runtime Exception. License: GPLv3+ and GPLv3+ with exceptions and GPLv2+ with exceptions and LGPLv2+ and BSD @@ -329,6 +329,7 @@ Patch5004: gcc8-Instruction-generation-optimization.patch Patch5005: gcc8-Vect-Enable-skipping-vectorization-on-reduction-chai.patch Patch5006: gcc8-static-field-compression-optimization.patch Patch5007: gcc8-aarch64-tune-rebuild.patch +Patch5008: gcc8-hip12-support.patch # On ARM EABI systems, we do want -gnueabi to be part of the # target triple. @@ -964,6 +965,7 @@ so that there cannot be any synchronization problems. %patch5005 -p1 -b .Vect-Enable-skipping~ %patch5006 -p1 -b .static-field-compression~ %patch5007 -p1 -b .aarch64-tune-rebuild~ +%patch5008 -p1 -b .hip12-support~ cd nvptx-tools-%{nvptx_tools_gitrev} %patch2000 -p1 -b .nvptx-tools-no-ptxas~ @@ -3377,6 +3379,9 @@ fi %{ANNOBIN_GCC_PLUGIN_DIR}/gcc-annobin.so.0.0.0 %changelog +* Mon May 26 2025 caojiaju - 8.5.0-27.ap.3 +- support hip12 instructions pipeline,core definition and cost model + * Fri Apr 18 2025 TencentOS Team - 8.5.0-26.ap.2 - Add static field compression optimization - rebuild aarch64-tune.md and delete unused variable -- Gitee