diff --git a/binutils-2.42.spec b/binutils-2.42.spec index 6f6f574d39122c9b7ce7e9c13490fcadb60fe905..bbe73be81f3d47b45c923a6240fe3c8bfb8411c6 100644 --- a/binutils-2.42.spec +++ b/binutils-2.42.spec @@ -15,7 +15,7 @@ Summary: A GNU collection of binary utilities Name: %{?_scl_prefix}binutils%{binutils_ver} Version: 2.42 -Release: 2 +Release: 3 License: GPLv3+ URL: https://sourceware.org/binutils ExcludeArch: loongarch64 @@ -176,6 +176,16 @@ Source2: binutils-2.19.50.0.1-output-format.sed # https://gitee.com/openeuler/TC/blob/master/oEEP/oEEP-0012%20openEuler%E8%BD%AF%E4%BB%B6%E5%8C%85%E9%9D%9Eupstream%E6%94%AF%E6%8C%81%E5%A4%9A%E6%9E%B6%E6%9E%84%E4%BB%A3%E7%A0%81%E6%8F%90%E4%BA%A4%E8%A7%84%E5%88%99.md # Part 1000 - 1999 +# Part 3000 - 4999 +# Purpose: Add support for RVA23U64 mandatory extensions. +# Lifetime: Backport from upstreams: +# 25f05199bb7e35820c23e802424484accb7936b1 +# 3ba06284d2cada7a4798f7849da113661aff07dd +# 8a3ffa71945816b941d3dea9ebc7013d5be7a1a4 +Patch3001: binutils-2.44-backport-RISC-V-Add-platform-property-capability-extensions.patch +Patch3002: binutils-2.44-backport-RISC-V-Add-support-for-Zimop-extension.patch +Patch3003: binutils-2.44-backport-RISC-V-Add-support-for-Zcmop-extension.patch + # Part 5000 - # Purpose: Use /lib64 and /usr/lib64 instead of /lib and /usr/lib in the # default library search path of 64-bit targets. @@ -1267,6 +1277,9 @@ exit 0 #---------------------------------------------------------------------------- %changelog +* Wed Jul 02 2025 zhangenpei - 2.42-3 +- Backport RVA23U64 mandatory extensions. + * Wed Feb 12 2025 yinchuang - 2.42-2 - Temporarily disable install *.la file diff --git a/binutils-2.44-backport-RISC-V-Add-platform-property-capability-extensions.patch b/binutils-2.44-backport-RISC-V-Add-platform-property-capability-extensions.patch new file mode 100644 index 0000000000000000000000000000000000000000..4976c6e8562a5db15305c9489d4f27690c3e2799 --- /dev/null +++ b/binutils-2.44-backport-RISC-V-Add-platform-property-capability-extensions.patch @@ -0,0 +1,83 @@ +diff -rup binutils.orig/bfd/elfxx-riscv.c binutils-2.42/bfd/elfxx-riscv.c +--- binutils.orig/bfd/elfxx-riscv.c 2025-07-01 10:16:05.889931463 +0800 ++++ binutils-2.42/bfd/elfxx-riscv.c 2025-07-01 10:16:55.803095052 +0800 +@@ -1113,6 +1113,12 @@ static struct riscv_implicit_subset risc + {"g", "zicsr", check_implicit_always}, + {"g", "zifencei", check_implicit_always}, + {"m", "zmmul", check_implicit_always}, ++ {"shcounterenw", "h", check_implicit_always}, ++ {"shgatpa", "h", check_implicit_always}, ++ {"shtvala", "h", check_implicit_always}, ++ {"shvsatpa", "h", check_implicit_always}, ++ {"shvstvala", "h", check_implicit_always}, ++ {"shvstvecd", "h", check_implicit_always}, + {"h", "zicsr", check_implicit_always}, + {"q", "d", check_implicit_always}, + {"v", "d", check_implicit_always}, +@@ -1199,9 +1205,16 @@ static struct riscv_implicit_subset risc + {"smepmp", "zicsr", check_implicit_always}, + {"ssaia", "zicsr", check_implicit_always}, + {"sscofpmf", "zicsr", check_implicit_always}, ++ {"sscounterenw", "zicsr", check_implicit_always}, + {"ssstateen", "zicsr", check_implicit_always}, + {"sstc", "zicsr", check_implicit_always}, ++ {"sstvala", "zicsr", check_implicit_always}, ++ {"sstvecd", "zicsr", check_implicit_always}, ++ {"ssu64xl", "zicsr", check_implicit_always}, ++ ++ {"svade", "zicsr", check_implicit_always}, + {"svadu", "zicsr", check_implicit_always}, ++ {"svbare", "zicsr", check_implicit_always}, + + {"xsfvcp", "zve32x", check_implicit_always}, + {NULL, NULL, NULL} +@@ -1261,6 +1274,11 @@ static struct riscv_supported_ext riscv_ + + static struct riscv_supported_ext riscv_supported_std_z_ext[] = + { ++ {"zic64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"ziccamoa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"ziccif", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"zicclsm", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"ziccrse", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zicbom", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zicbop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zicboz", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, +@@ -1274,6 +1292,8 @@ static struct riscv_supported_ext riscv_ + {"zihintpause", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 }, + {"zihpm", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 }, + {"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"za64rs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"za128rs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zfa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zfh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, +@@ -1345,15 +1365,28 @@ static struct riscv_supported_ext riscv_ + + static struct riscv_supported_ext riscv_supported_std_s_ext[] = + { ++ {"shcounterenw", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"shgatpa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"shtvala", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"shvsatpa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"shvstvala", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"shvstvecd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"smaia", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"smcntrpmf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"smepmp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"smstateen", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"ssaia", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"ssccptr", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"sscofpmf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"sscounterenw", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"ssstateen", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"sstc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"sstvala", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"sstvecd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"ssu64xl", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"svade", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"svadu", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"svbare", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"svinval", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"svnapot", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"svpbmt", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, diff --git a/binutils-2.44-backport-RISC-V-Add-support-for-Zcmop-extension.patch b/binutils-2.44-backport-RISC-V-Add-support-for-Zcmop-extension.patch new file mode 100644 index 0000000000000000000000000000000000000000..5a405d2af8c23b5846711b837e1979ecc55591ea --- /dev/null +++ b/binutils-2.44-backport-RISC-V-Add-support-for-Zcmop-extension.patch @@ -0,0 +1,112 @@ +diff -rup binutils.orig/bfd/elfxx-riscv.c binutils-2.42/bfd/elfxx-riscv.c +--- binutils.orig/bfd/elfxx-riscv.c 2025-07-01 10:28:57.536983487 +0800 ++++ binutils-2.42/bfd/elfxx-riscv.c 2025-07-01 10:29:16.665474728 +0800 +@@ -1113,6 +1113,8 @@ static struct riscv_implicit_subset risc + {"g", "zicsr", check_implicit_always}, + {"g", "zifencei", check_implicit_always}, + {"m", "zmmul", check_implicit_always}, ++ {"zcmop", "zca", check_implicit_always}, ++ + {"shcounterenw", "h", check_implicit_always}, + {"shgatpa", "h", check_implicit_always}, + {"shtvala", "h", check_implicit_always}, +@@ -1361,6 +1363,7 @@ static struct riscv_supported_ext riscv_ + {"zcb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zcf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zcd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"zcmop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {NULL, 0, 0, 0, 0} + }; + +@@ -2604,6 +2607,8 @@ riscv_multi_subset_supports (riscv_parse + case INSN_CLASS_ZCB_AND_ZMMUL: + return (riscv_subset_supports (rps, "zcb") + && riscv_subset_supports (rps, "zmmul")); ++ case INSN_CLASS_ZCMOP: ++ return riscv_subset_supports (rps, "zcmop"); + case INSN_CLASS_SVINVAL: + return riscv_subset_supports (rps, "svinval"); + case INSN_CLASS_H: +@@ -2858,6 +2863,8 @@ riscv_multi_subset_supports_ext (riscv_p + return _("zcb' and `zbb"); + case INSN_CLASS_ZCB_AND_ZMMUL: + return _("zcb' and `zmmul', or `zcb' and `m"); ++ case INSN_CLASS_ZCMOP: ++ return "zcmop"; + case INSN_CLASS_SVINVAL: + return "svinval"; + case INSN_CLASS_H: +diff -rup binutils.orig/include/opcode/riscv.h binutils-2.42/include/opcode/riscv.h +--- binutils.orig/include/opcode/riscv.h 2025-07-01 10:29:00.552376203 +0800 ++++ binutils-2.42/include/opcode/riscv.h 2025-07-01 10:29:16.669475249 +0800 +@@ -465,6 +465,7 @@ enum riscv_insn_class + INSN_CLASS_ZCB_AND_ZBA, + INSN_CLASS_ZCB_AND_ZBB, + INSN_CLASS_ZCB_AND_ZMMUL, ++ INSN_CLASS_ZCMOP, + INSN_CLASS_SVINVAL, + INSN_CLASS_ZICBOM, + INSN_CLASS_ZICBOP, +diff -rup binutils.orig/include/opcode/riscv-opc.h binutils-2.42/include/opcode/riscv-opc.h +--- binutils.orig/include/opcode/riscv-opc.h 2025-07-01 10:29:00.551376073 +0800 ++++ binutils-2.42/include/opcode/riscv-opc.h 2025-07-01 10:29:16.668475119 +0800 +@@ -2235,6 +2235,23 @@ + #define MASK_C_NOT 0xfc7f + #define MATCH_C_MUL 0x9c41 + #define MASK_C_MUL 0xfc63 ++/* Zcmop instructions. */ ++#define MATCH_C_MOP_1 0x6081 ++#define MASK_C_MOP_1 0xffff ++#define MATCH_C_MOP_3 0x6181 ++#define MASK_C_MOP_3 0xffff ++#define MATCH_C_MOP_5 0x6281 ++#define MASK_C_MOP_5 0xffff ++#define MATCH_C_MOP_7 0x6381 ++#define MASK_C_MOP_7 0xffff ++#define MATCH_C_MOP_9 0x6481 ++#define MASK_C_MOP_9 0xffff ++#define MATCH_C_MOP_11 0x6581 ++#define MASK_C_MOP_11 0xffff ++#define MATCH_C_MOP_13 0x6681 ++#define MASK_C_MOP_13 0xffff ++#define MATCH_C_MOP_15 0x6781 ++#define MASK_C_MOP_15 0xffff + /* Svinval instruction. */ + #define MATCH_SINVAL_VMA 0x16000073 + #define MASK_SINVAL_VMA 0xfe007fff +@@ -4038,6 +4055,15 @@ DECLARE_INSN(c_lhu, MATCH_C_LHU, MASK_C_ + DECLARE_INSN(c_lh, MATCH_C_LH, MASK_C_LH) + DECLARE_INSN(c_sb, MATCH_C_SB, MASK_C_SB) + DECLARE_INSN(c_sh, MATCH_C_SH, MASK_C_SH) ++/* Zcmop instructions. */ ++DECLARE_INSN(c_mop_1, MATCH_C_MOP_1, MASK_C_MOP_1) ++DECLARE_INSN(c_mop_3, MATCH_C_MOP_3, MASK_C_MOP_3) ++DECLARE_INSN(c_mop_5, MATCH_C_MOP_5, MASK_C_MOP_5) ++DECLARE_INSN(c_mop_7, MATCH_C_MOP_7, MASK_C_MOP_7) ++DECLARE_INSN(c_mop_9, MATCH_C_MOP_9, MASK_C_MOP_9) ++DECLARE_INSN(c_mop_11, MATCH_C_MOP_11, MASK_C_MOP_11) ++DECLARE_INSN(c_mop_13, MATCH_C_MOP_13, MASK_C_MOP_13) ++DECLARE_INSN(c_mop_15, MATCH_C_MOP_15, MASK_C_MOP_15) + /* Vendor-specific (T-Head) XTheadBa instructions. */ + DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL) + /* Vendor-specific (T-Head) XTheadBb instructions. */ +diff -rup binutils.orig/opcodes/riscv-opc.c binutils-2.42/opcodes/riscv-opc.c +--- binutils.orig/opcodes/riscv-opc.c 2025-07-01 10:29:02.563638145 +0800 ++++ binutils-2.42/opcodes/riscv-opc.c 2025-07-01 10:29:16.669475249 +0800 +@@ -2035,6 +2035,16 @@ const struct riscv_opcode riscv_opcodes[ + {"c.zext.b", 0, INSN_CLASS_ZCB, "Cs", MATCH_C_ZEXT_B, MASK_C_ZEXT_B, match_opcode, 0 }, + {"c.sext.w", 64, INSN_CLASS_ZCB, "d", MATCH_C_ADDIW, MASK_C_ADDIW|MASK_RVC_IMM, match_rd_nonzero, INSN_ALIAS }, + ++/* Zcmop instructions. */ ++{"c.mop.1", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_1, MASK_C_MOP_1, match_opcode, 0 }, ++{"c.mop.3", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_3, MASK_C_MOP_3, match_opcode, 0 }, ++{"c.mop.5", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_5, MASK_C_MOP_5, match_opcode, 0 }, ++{"c.mop.7", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_7, MASK_C_MOP_7, match_opcode, 0 }, ++{"c.mop.9", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_9, MASK_C_MOP_9, match_opcode, 0 }, ++{"c.mop.11", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_11, MASK_C_MOP_11, match_opcode, 0 }, ++{"c.mop.13", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_13, MASK_C_MOP_13, match_opcode, 0 }, ++{"c.mop.15", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_15, MASK_C_MOP_15, match_opcode, 0 }, ++ + /* Supervisor instructions. */ + {"csrr", 0, INSN_CLASS_ZICSR, "d,E", MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS }, + {"csrwi", 0, INSN_CLASS_ZICSR, "E,Z", MATCH_CSRRWI, MASK_CSRRWI|MASK_RD, match_opcode, INSN_ALIAS }, diff --git a/binutils-2.44-backport-RISC-V-Add-support-for-Zimop-extension.patch b/binutils-2.44-backport-RISC-V-Add-support-for-Zimop-extension.patch new file mode 100644 index 0000000000000000000000000000000000000000..83d49b0c52293f098cc80affd6f10bc81497e6e9 --- /dev/null +++ b/binutils-2.44-backport-RISC-V-Add-support-for-Zimop-extension.patch @@ -0,0 +1,231 @@ +diff -rup binutils.orig/bfd/elfxx-riscv.c binutils-2.42/bfd/elfxx-riscv.c +--- binutils.orig/bfd/elfxx-riscv.c 2025-07-01 10:21:19.489412455 +0800 ++++ binutils-2.42/bfd/elfxx-riscv.c 2025-07-01 10:21:39.880067385 +0800 +@@ -1291,6 +1291,7 @@ static struct riscv_supported_ext riscv_ + {"zihintntl", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zihintpause", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 }, + {"zihpm", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 }, ++ {"zimop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"za64rs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"za128rs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, +@@ -2464,6 +2465,8 @@ riscv_multi_subset_supports (riscv_parse + || riscv_subset_supports (rps, "zca"))); + case INSN_CLASS_ZIHINTPAUSE: + return riscv_subset_supports (rps, "zihintpause"); ++ case INSN_CLASS_ZIMOP: ++ return riscv_subset_supports (rps, "zimop"); + case INSN_CLASS_M: + return riscv_subset_supports (rps, "m"); + case INSN_CLASS_ZMMUL: +@@ -2686,6 +2689,8 @@ riscv_multi_subset_supports_ext (riscv_p + return _("c' or `zca"); + case INSN_CLASS_ZIHINTPAUSE: + return "zihintpause"; ++ case INSN_CLASS_ZIMOP: ++ return "zimop"; + case INSN_CLASS_M: + return "m"; + case INSN_CLASS_ZMMUL: +diff -rup binutils.orig/include/opcode/riscv.h binutils-2.42/include/opcode/riscv.h +--- binutils.orig/include/opcode/riscv.h 2025-07-01 10:21:21.698591754 +0800 ++++ binutils-2.42/include/opcode/riscv.h 2025-07-01 10:21:39.882067547 +0800 +@@ -420,6 +420,7 @@ enum riscv_insn_class + INSN_CLASS_ZIHINTNTL, + INSN_CLASS_ZIHINTNTL_AND_C, + INSN_CLASS_ZIHINTPAUSE, ++ INSN_CLASS_ZIMOP, + INSN_CLASS_ZMMUL, + INSN_CLASS_ZAWRS, + INSN_CLASS_F_INX, +diff -rup binutils.orig/include/opcode/riscv-opc.h binutils-2.42/include/opcode/riscv-opc.h +--- binutils.orig/include/opcode/riscv-opc.h 2025-07-01 10:21:21.698591754 +0800 ++++ binutils-2.42/include/opcode/riscv-opc.h 2025-07-01 10:21:39.882067547 +0800 +@@ -2315,6 +2315,87 @@ + #define MASK_C_NTL_S1 0xffff + #define MATCH_C_NTL_ALL 0x9016 + #define MASK_C_NTL_ALL 0xffff ++/* Zimop instructions. */ ++#define MATCH_MOP_R_0 0x81c04073 ++#define MASK_MOP_R_0 0xfff0707f ++#define MATCH_MOP_R_1 0x81d04073 ++#define MASK_MOP_R_1 0xfff0707f ++#define MATCH_MOP_R_2 0x81e04073 ++#define MASK_MOP_R_2 0xfff0707f ++#define MATCH_MOP_R_3 0x81f04073 ++#define MASK_MOP_R_3 0xfff0707f ++#define MATCH_MOP_R_4 0x85c04073 ++#define MASK_MOP_R_4 0xfff0707f ++#define MATCH_MOP_R_5 0x85d04073 ++#define MASK_MOP_R_5 0xfff0707f ++#define MATCH_MOP_R_6 0x85e04073 ++#define MASK_MOP_R_6 0xfff0707f ++#define MATCH_MOP_R_7 0x85f04073 ++#define MASK_MOP_R_7 0xfff0707f ++#define MATCH_MOP_R_8 0x89c04073 ++#define MASK_MOP_R_8 0xfff0707f ++#define MATCH_MOP_R_9 0x89d04073 ++#define MASK_MOP_R_9 0xfff0707f ++#define MATCH_MOP_R_10 0x89e04073 ++#define MASK_MOP_R_10 0xfff0707f ++#define MATCH_MOP_R_11 0x89f04073 ++#define MASK_MOP_R_11 0xfff0707f ++#define MATCH_MOP_R_12 0x8dc04073 ++#define MASK_MOP_R_12 0xfff0707f ++#define MATCH_MOP_R_13 0x8dd04073 ++#define MASK_MOP_R_13 0xfff0707f ++#define MATCH_MOP_R_14 0x8de04073 ++#define MASK_MOP_R_14 0xfff0707f ++#define MATCH_MOP_R_15 0x8df04073 ++#define MASK_MOP_R_15 0xfff0707f ++#define MATCH_MOP_R_16 0xc1c04073 ++#define MASK_MOP_R_16 0xfff0707f ++#define MATCH_MOP_R_17 0xc1d04073 ++#define MASK_MOP_R_17 0xfff0707f ++#define MATCH_MOP_R_18 0xc1e04073 ++#define MASK_MOP_R_18 0xfff0707f ++#define MATCH_MOP_R_19 0xc1f04073 ++#define MASK_MOP_R_19 0xfff0707f ++#define MATCH_MOP_R_20 0xc5c04073 ++#define MASK_MOP_R_20 0xfff0707f ++#define MATCH_MOP_R_21 0xc5d04073 ++#define MASK_MOP_R_21 0xfff0707f ++#define MATCH_MOP_R_22 0xc5e04073 ++#define MASK_MOP_R_22 0xfff0707f ++#define MATCH_MOP_R_23 0xc5f04073 ++#define MASK_MOP_R_23 0xfff0707f ++#define MATCH_MOP_R_24 0xc9c04073 ++#define MASK_MOP_R_24 0xfff0707f ++#define MATCH_MOP_R_25 0xc9d04073 ++#define MASK_MOP_R_25 0xfff0707f ++#define MATCH_MOP_R_26 0xc9e04073 ++#define MASK_MOP_R_26 0xfff0707f ++#define MATCH_MOP_R_27 0xc9f04073 ++#define MASK_MOP_R_27 0xfff0707f ++#define MATCH_MOP_R_28 0xcdc04073 ++#define MASK_MOP_R_28 0xfff0707f ++#define MATCH_MOP_R_29 0xcdd04073 ++#define MASK_MOP_R_29 0xfff0707f ++#define MATCH_MOP_R_30 0xcde04073 ++#define MASK_MOP_R_30 0xfff0707f ++#define MATCH_MOP_R_31 0xcdf04073 ++#define MASK_MOP_R_31 0xfff0707f ++#define MATCH_MOP_RR_0 0x82004073 ++#define MASK_MOP_RR_0 0xfe00707f ++#define MATCH_MOP_RR_1 0x86004073 ++#define MASK_MOP_RR_1 0xfe00707f ++#define MATCH_MOP_RR_2 0x8a004073 ++#define MASK_MOP_RR_2 0xfe00707f ++#define MATCH_MOP_RR_3 0x8e004073 ++#define MASK_MOP_RR_3 0xfe00707f ++#define MATCH_MOP_RR_4 0xc2004073 ++#define MASK_MOP_RR_4 0xfe00707f ++#define MATCH_MOP_RR_5 0xc6004073 ++#define MASK_MOP_RR_5 0xfe00707f ++#define MATCH_MOP_RR_6 0xca004073 ++#define MASK_MOP_RR_6 0xfe00707f ++#define MATCH_MOP_RR_7 0xce004073 ++#define MASK_MOP_RR_7 0xfe00707f + /* Zawrs instructions. */ + #define MATCH_WRS_NTO 0x00d00073 + #define MASK_WRS_NTO 0xffffffff +@@ -3852,6 +3933,47 @@ DECLARE_INSN(c_ntl_p1, MATCH_C_NTL_P1, M + DECLARE_INSN(c_ntl_pall, MATCH_C_NTL_PALL, MASK_C_NTL_PALL) + DECLARE_INSN(c_ntl_s1, MATCH_C_NTL_S1, MASK_C_NTL_S1) + DECLARE_INSN(c_ntl_all, MATCH_C_NTL_ALL, MASK_C_NTL_ALL) ++/* Zimop instructions. */ ++DECLARE_INSN(MOP_R_0, MATCH_MOP_R_0, MASK_MOP_R_0) ++DECLARE_INSN(MOP_R_1, MATCH_MOP_R_1, MASK_MOP_R_1) ++DECLARE_INSN(MOP_R_2, MATCH_MOP_R_2, MASK_MOP_R_2) ++DECLARE_INSN(MOP_R_3, MATCH_MOP_R_3, MASK_MOP_R_3) ++DECLARE_INSN(MOP_R_4, MATCH_MOP_R_4, MASK_MOP_R_4) ++DECLARE_INSN(MOP_R_5, MATCH_MOP_R_5, MASK_MOP_R_5) ++DECLARE_INSN(MOP_R_6, MATCH_MOP_R_6, MASK_MOP_R_6) ++DECLARE_INSN(MOP_R_7, MATCH_MOP_R_7, MASK_MOP_R_7) ++DECLARE_INSN(MOP_R_8, MATCH_MOP_R_8, MASK_MOP_R_8) ++DECLARE_INSN(MOP_R_9, MATCH_MOP_R_9, MASK_MOP_R_9) ++DECLARE_INSN(MOP_R_10, MATCH_MOP_R_10, MASK_MOP_R_10) ++DECLARE_INSN(MOP_R_11, MATCH_MOP_R_11, MASK_MOP_R_11) ++DECLARE_INSN(MOP_R_12, MATCH_MOP_R_12, MASK_MOP_R_12) ++DECLARE_INSN(MOP_R_13, MATCH_MOP_R_13, MASK_MOP_R_13) ++DECLARE_INSN(MOP_R_14, MATCH_MOP_R_14, MASK_MOP_R_14) ++DECLARE_INSN(MOP_R_15, MATCH_MOP_R_15, MASK_MOP_R_15) ++DECLARE_INSN(MOP_R_16, MATCH_MOP_R_16, MASK_MOP_R_16) ++DECLARE_INSN(MOP_R_17, MATCH_MOP_R_17, MASK_MOP_R_17) ++DECLARE_INSN(MOP_R_18, MATCH_MOP_R_18, MASK_MOP_R_18) ++DECLARE_INSN(MOP_R_19, MATCH_MOP_R_19, MASK_MOP_R_19) ++DECLARE_INSN(MOP_R_20, MATCH_MOP_R_20, MASK_MOP_R_20) ++DECLARE_INSN(MOP_R_21, MATCH_MOP_R_21, MASK_MOP_R_21) ++DECLARE_INSN(MOP_R_22, MATCH_MOP_R_22, MASK_MOP_R_22) ++DECLARE_INSN(MOP_R_23, MATCH_MOP_R_23, MASK_MOP_R_23) ++DECLARE_INSN(MOP_R_24, MATCH_MOP_R_24, MASK_MOP_R_24) ++DECLARE_INSN(MOP_R_25, MATCH_MOP_R_25, MASK_MOP_R_25) ++DECLARE_INSN(MOP_R_26, MATCH_MOP_R_26, MASK_MOP_R_26) ++DECLARE_INSN(MOP_R_27, MATCH_MOP_R_27, MASK_MOP_R_27) ++DECLARE_INSN(MOP_R_28, MATCH_MOP_R_28, MASK_MOP_R_28) ++DECLARE_INSN(MOP_R_29, MATCH_MOP_R_29, MASK_MOP_R_29) ++DECLARE_INSN(MOP_R_30, MATCH_MOP_R_30, MASK_MOP_R_30) ++DECLARE_INSN(MOP_R_31, MATCH_MOP_R_31, MASK_MOP_R_31) ++DECLARE_INSN(MOP_RR_0, MATCH_MOP_RR_0, MASK_MOP_RR_0) ++DECLARE_INSN(MOP_RR_1, MATCH_MOP_RR_1, MASK_MOP_RR_1) ++DECLARE_INSN(MOP_RR_2, MATCH_MOP_RR_2, MASK_MOP_RR_2) ++DECLARE_INSN(MOP_RR_3, MATCH_MOP_RR_3, MASK_MOP_RR_3) ++DECLARE_INSN(MOP_RR_4, MATCH_MOP_RR_4, MASK_MOP_RR_4) ++DECLARE_INSN(MOP_RR_5, MATCH_MOP_RR_5, MASK_MOP_RR_5) ++DECLARE_INSN(MOP_RR_6, MATCH_MOP_RR_6, MASK_MOP_RR_6) ++DECLARE_INSN(MOP_RR_7, MATCH_MOP_RR_7, MASK_MOP_RR_7) + /* Zawrs instructions. */ + DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO) + DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO) +diff -rup binutils.orig/opcodes/riscv-opc.c binutils-2.42/opcodes/riscv-opc.c +--- binutils.orig/opcodes/riscv-opc.c 2025-07-01 10:21:23.053701737 +0800 ++++ binutils-2.42/opcodes/riscv-opc.c 2025-07-01 10:21:39.884067709 +0800 +@@ -996,6 +996,48 @@ const struct riscv_opcode riscv_opcodes[ + {"czero.eqz", 0, INSN_CLASS_ZICOND, "d,s,t", MATCH_CZERO_EQZ, MASK_CZERO_EQZ, match_opcode, 0 }, + {"czero.nez", 0, INSN_CLASS_ZICOND, "d,s,t", MATCH_CZERO_NEZ, MASK_CZERO_NEZ, match_opcode, 0 }, + ++/* Zimop instructions. */ ++{"mop.r.0", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_0, MASK_MOP_R_0, match_opcode, 0 }, ++{"mop.r.1", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_1, MASK_MOP_R_1, match_opcode, 0 }, ++{"mop.r.2", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_2, MASK_MOP_R_2, match_opcode, 0 }, ++{"mop.r.3", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_3, MASK_MOP_R_3, match_opcode, 0 }, ++{"mop.r.4", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_4, MASK_MOP_R_4, match_opcode, 0 }, ++{"mop.r.5", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_5, MASK_MOP_R_5, match_opcode, 0 }, ++{"mop.r.6", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_6, MASK_MOP_R_6, match_opcode, 0 }, ++{"mop.r.7", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_7, MASK_MOP_R_7, match_opcode, 0 }, ++{"mop.r.8", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_8, MASK_MOP_R_8, match_opcode, 0 }, ++{"mop.r.9", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_9, MASK_MOP_R_9, match_opcode, 0 }, ++{"mop.r.10", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_10, MASK_MOP_R_10, match_opcode, 0 }, ++{"mop.r.11", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_11, MASK_MOP_R_11, match_opcode, 0 }, ++{"mop.r.12", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_12, MASK_MOP_R_12, match_opcode, 0 }, ++{"mop.r.13", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_13, MASK_MOP_R_13, match_opcode, 0 }, ++{"mop.r.14", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_14, MASK_MOP_R_14, match_opcode, 0 }, ++{"mop.r.15", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_15, MASK_MOP_R_15, match_opcode, 0 }, ++{"mop.r.16", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_16, MASK_MOP_R_16, match_opcode, 0 }, ++{"mop.r.17", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_17, MASK_MOP_R_17, match_opcode, 0 }, ++{"mop.r.18", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_18, MASK_MOP_R_18, match_opcode, 0 }, ++{"mop.r.19", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_19, MASK_MOP_R_19, match_opcode, 0 }, ++{"mop.r.20", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_20, MASK_MOP_R_20, match_opcode, 0 }, ++{"mop.r.21", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_21, MASK_MOP_R_21, match_opcode, 0 }, ++{"mop.r.22", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_22, MASK_MOP_R_22, match_opcode, 0 }, ++{"mop.r.23", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_23, MASK_MOP_R_23, match_opcode, 0 }, ++{"mop.r.24", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_24, MASK_MOP_R_24, match_opcode, 0 }, ++{"mop.r.25", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_25, MASK_MOP_R_25, match_opcode, 0 }, ++{"mop.r.26", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_26, MASK_MOP_R_26, match_opcode, 0 }, ++{"mop.r.27", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_27, MASK_MOP_R_27, match_opcode, 0 }, ++{"mop.r.28", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_28, MASK_MOP_R_28, match_opcode, 0 }, ++{"mop.r.29", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_29, MASK_MOP_R_29, match_opcode, 0 }, ++{"mop.r.30", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_30, MASK_MOP_R_30, match_opcode, 0 }, ++{"mop.r.31", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_31, MASK_MOP_R_31, match_opcode, 0 }, ++{"mop.rr.0", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_0, MASK_MOP_RR_0, match_opcode, 0 }, ++{"mop.rr.1", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_1, MASK_MOP_RR_1, match_opcode, 0 }, ++{"mop.rr.2", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_2, MASK_MOP_RR_2, match_opcode, 0 }, ++{"mop.rr.3", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_3, MASK_MOP_RR_3, match_opcode, 0 }, ++{"mop.rr.4", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_4, MASK_MOP_RR_4, match_opcode, 0 }, ++{"mop.rr.5", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_5, MASK_MOP_RR_5, match_opcode, 0 }, ++{"mop.rr.6", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_6, MASK_MOP_RR_6, match_opcode, 0 }, ++{"mop.rr.7", 0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_7, MASK_MOP_RR_7, match_opcode, 0 }, ++ + /* Zawrs instructions. */ + {"wrs.nto", 0, INSN_CLASS_ZAWRS, "", MATCH_WRS_NTO, MASK_WRS_NTO, match_opcode, 0 }, + {"wrs.sto", 0, INSN_CLASS_ZAWRS, "", MATCH_WRS_STO, MASK_WRS_STO, match_opcode, 0 },