binutils 2.37 (openEuler 22.03 LTS) 变更 binutils 2.41 (openEuler 24.03 LTS) 说明

### binutils变更

**新增功能**

| 组件 | 新增功能 | 影响 |
| ---- | -------- | ---- |
| elfedit | Add --output-abiversion option to update ABIVERSION. | |
| Tools which display symbols or strings (readelf, strings, nm, objdump) | Add a new command line option --unicode= which controls how unicode characters are handled. | |
| readelf | -r dumps RELR relative relocations now. | |
| readelf | Add an option to prevent attempts to access debuginfod servers when following links. | |
| readelf | Add a new option --sframe which dumps the SFrame section. | |
| objcopy | Add support for efi-app-aarch64, efi-rtdrv-aarch64 and efi-bsdrv-aarch64 to enable UEFI development using binutils. | |
| objcopy | --decompress-debug-sections now supports zstd compressed debug sections. | The new option --compress-debug-sections=zstd compresses debug sections with zstd. |
| objcopy | Add command-line option, --strip-section-headers, to remove ELF section header from ELF file. | |
| ar | Add --thin for creating thin archives. | |
| nm | Add --no-weak/-W option to make it ignore weak symbols. | |
| objdump | Add an option to prevent attempts to access debuginfod servers when following links. | |
| objdump | supports syntax highlighting of disassembler output for some architectures. | |
| objdump | Add a new command line option --show-all-symbols which will make it display all symbols that match a given address when disassembling. | |
| objdump | --dwarf now support zstd compressed debug sections. | |
| objdump | Add a new option --sframe which dumps the SFrame section. | |
| objdump | --private option can now be used on PE format files to display the fields in the file header and section headers. | |
| addr2line | --dwarf now support zstd compressed debug sections. | |
| dlltool | Add --deterministic-libraries and --non-deterministic-libraries options to control whether or not it generates deterministic output libraries. | |
| strip | Add command-line option, --strip-section-headers, to remove ELF section header from ELF file. | |
| configure | Add --enable-colored-disassembly configure time option to enable colored disassembly output by default. | disabled by default |

**变更功能**

| 组件 | 变更功能 | 影响 |
| ---- | -------- | ---- |
| objcopy | --weaken, --weaken-symbol, and --weaken-symbols now make ELF STB_GNU_UNIQUE symbols weak. | 使用这三个选项时现在会将STB_GNU_UNIQUE符号变为弱符号 |
| libsframe | New versioned release of libsframe: libsframe.so.1.  This release introduces versioned symbols with version node name LIBSFRAME_1.0.  This release also updates the ABI in an incompatible way: this includes removal of sframe_get_funcdesc_with_addr API, change in the behavior of sframe_fre_get_ra_offset and sframe_fre_get_fp_offset APIs. </br> </br> SFrame Version 2 is now the default (and only) format version supported by gas, ld, readelf and objdump. | 正常使用gas, ld, readelf, objdump工具无影响。并且binutils包没有暴露该动态库用以二次开发。 |

**删除功能**

| 组件 | 删除功能 | 影响 |
| ---- | -------- | ---- |
| ar | -T is a deprecated alias without diagnostics. | use --thin instead |

**架构相关**

* The MIPS port now supports the Sony Interactive Entertainment Allegrex processor.

* The RISC-V port now supports the following new standard extensions:
  - Zicond (conditional zero instructions)
  - Zfa (additional floating-point instructions)
  - Zvbb, Zvbc, Zvkg, Zvkned, Zvknh[ab], Zvksed, Zvksh, Zvkn, Zvknc, Zvkng,
    Zvks, Zvksc, Zvkg, Zvkt (vector crypto instructions)

* The RISC-V port now supports the following vendor-defined extensions:
  - XVentanaCondOps

* The LoongArch port now supports the following extensions:
  - LSX (Loongson SIMD eXtension; 128-bit vectors)
  - LASX (Loongson Advanced SIMD eXtension; 256-bit vectors)
  - LVZ (Loongson Virtualization extension)
  - LBT (Loongson Binary Translation extension)

* The LoongArch disassembly output received the following tweaks:
  - Colored output is now supported.
  - Some pseudo-instructions are now shown in place of the canonical forms,
    where semantics are equivalent. A disassembler option '-M no-aliases' is
    added to disable the new behavior.
  - Signed immediates are no longer printed with their hex representation.
  - Unrecognized instruction words are now shown with '.word'.

### gas变更

**新增功能**

| 组件 | 新增功能 | 影响 |
| ---- | -------- | ---- |
| gas | Add a command-line option, -muse-unaligned-vector-move, for x86 target to encode aligned vector move as unaligned vector move. | |
| gas | The --multibyte-handling=[allow\|warn\|warn-sym-only] option tells the assembler what to when it encoutners multibyte characters in the input. | |
| gas | now supports --compress-debug-sections=zstd to compress debug sections with zstd. | |
| gas | Add --enable-default-compressed-debug-sections-algorithm={zlib,zstd} that selects the default compression algorithm for --enable-compressed-debug-sections. | |
| gas | New command line option --gsframe to generate SFrame unwind information on x86_64 and aarch64 targets. | |
| gas | A new .insn directive is recognized by x86 gas. | |

**变更功能**
| 组件 | 变更功能 | 影响 |
| ---- | -------- | ---- |
| gas | Outputs of .ds.x directive and .tfloat directive with hex input from x86 assembler have been reduced from 12 bytes to 10 bytes to match the output of .tfloat directive. | .ds.x和.tfloat导语的字节数发生变化 |

**删除功能**

| 组件 | 删除功能 | 影响 |
| ---- | -------- | ---- |
| gas | Remove (rudimentary) support for the x86-64 sub-architectures Intel L1OM and Intel K1OM. | 不再支持Intel L1OM和Intel K1OM |
| gas | Deprecate the LoongArch register aliases $v0, $v1, $x, $fv0 and $fv1. | 龙芯架构下不再支持以上寄存器别名使用 |

**架构指令支持**

* Add support for AArch64 system registers that were missing in previous
  releases.

* Add support for the LoongArch instruction set.

* Add support for Cortex-R52+ for Arm.

* Add support for Cortex-A510, Cortex-A710, Cortex-X2 for AArch64.

* Add support for Cortex-A710 for Arm.

* Add support for Scalable Matrix Extension (SME) for AArch64.

* Add support for 'armv8.8-a', 'armv9-a', 'armv9.1-a', 'armv9.2-a' and
  'armv9.3-a' for -march in AArch64 GAS.

* Add support for 'armv8.7-a', 'armv8.8-a', 'armv9-a', 'armv9.1-a',
  'armv9.2-a' and 'armv9.3-a' for -march in Arm GAS.

* Add support for Intel AVX512_FP16 instructions.

* Add support for the RISC-V scalar crypto extension, version 1.0.0.

* Add support for the RISC-V vector extension, version 1.0.

* Add support for the Z{f,d,q}inx extensions, version 1.0.0-rc.

* Add support for the RISC-V svinval extension, version 1.0.

* Add support for the RISC-V hypervisor extension, as defined by Privileged
  Specification 1.12.

* Add support for the RISC-V Zicbop, Zicbom, and Zicboz extensions, version
  1.0-fd39d01.

* Add support for the RISC-V Zfh extension, version 1.0.

* Add support for the Zhinx extension, version 1.0.0-rc.

* Add support for the RISC-V H extension.

* Add support for the RISC-V Zfhmin extension, version 1.0, and Zhinxmin
  extension, version 1.0.0-rc.

* Add support for Intel RAO-INT instructions.

* Add support for Intel AVX-NE-CONVERT instructions.

* Add support for Intel MSRLIST instructions.

* Add support for Intel WRMSRNS instructions.

* Add support for Intel CMPccXADD instructions.

* Add support for Intel AVX-VNNI-INT8 instructions.

* Add support for Intel AVX-IFMA instructions.

* Add support for Intel PREFETCHI instructions.

* Add support for Intel AMX-FP16 instructions.

* Add support for various T-Head extensions (XTheadBa, XTheadBb, XTheadBs,
  XTheadCmo, XTheadCondMov, XTheadFMemIdx, XTheadFmv, XTheadInt, XTheadMemIdx,
  XTheadMemPair, XTheadMac, and XTheadSync) from version 2.0 of the T-Head
  ISA manual, which are implemented in the Allwinner D1.

* Add support for the RISC-V Zawrs extension, version 1.0-rc4.

* Add support for Cortex-X1C for Arm.

* Add support for the KVX instruction set.

* Add support for Intel FRED instructions.

* Add support for Intel LKGS instructions.

* Add support for Intel AMX-COMPLEX instructions.

* Add SME2 support to the AArch64 port.

* Add support for LoongArch LSX instructions.

* Add support for LoongArch LASX instructions.

* Add support for LoongArch LVZ instructions.

* Add support for LoongArch LBT instructions.

* Initial LoongArch support for linker relaxation has been added.

### ld变更

**新增功能**

| 组件 | 新增功能 | 影响 |
| ---- | -------- | ---- |
| ld | Add -z pack-relative-relocs/-z no pack-relative-relocs to x86 ELF linker to pack relative relocations in the DT_RELR section. | |
| ld | Add -z indirect-extern-access/-z noindirect-extern-access to x86 ELF linker to control canonical function pointers and copy relocation. | |
| ld | Add --max-cache-size=SIZE to set the the maximum cache size to SIZE bytes. | |
| ld | now generate a warning message if the stack is made executable. </br> </br> also warn if it creates a memory resident segment with all three of the Read, Write and eXecute permissions set, or if it creates a thread local data segment with the eXecute permission set. | 将会产生额外的warning |
| ld | TYPE=\<type\> is now supported in an output section description to set the section type value. | |
| ld | supports a new --package-metadata option that allows embedding a JSON payload in accordance to the Package Metadata specification. | |
| ld | a new command line option to suppress the generation of any warning or error messages. | |
| ld | supports zstd compressed debug sections. | |
| ld | Add --enable-default-compressed-debug-sections-algorithm={zlib,zstd} that selects the default compression algorithm for --enable-compressed-debug-sections. | |
| ld | accepts a command line option of --remap-inputs \<PATTERN\>=\<FILE\> to relace any input file that matches \<PATTERN\> with \<FILE\>.  In addition the option --remap-inputs-file=\<FILE\> can be used to specify a file containing any number of these remapping directives. | |
| ld | option --print-map-locals can be used to include local symbols in a linker map.  (ELF targets only). | |
| ld | For most ELF based targets, if the --enable-linker-version option is used then the version of the linker will be inserted as a string into the .comment section. | |
| ld | The linker script syntax has a new command for output sections: ASCIZ "string" This will insert a zero-terminated string at the current location. | |
| ld | Add command-line option, -z nosectionheader, to omit ELF section header. | |

**删除功能**

| 组件 | 删除功能 | 影响 |
| ---- | -------- | ---- |
| ld | Remove (rudimentary) support for the x86-64 sub-architectures Intel L1OM and Intel K1OM. | 不再支持Intel L1OM和Intel K1OM  |
| ld | Remove support for -z bndplt (MPX prefix instructions). | 不再支持-z bndplt选项 |

**架构相关**

* Add support for the LoongArch architecture.

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