diff --git a/LoongArch-Add-more-relaxation-testcases.patch b/LoongArch-Add-more-relaxation-testcases.patch new file mode 100644 index 0000000000000000000000000000000000000000..573b09f9805e85b5ddb4f33b89e38e838461351c --- /dev/null +++ b/LoongArch-Add-more-relaxation-testcases.patch @@ -0,0 +1,182 @@ +From 580a53dab47c9e4f97c8559440d2bc43fb7331b6 Mon Sep 17 00:00:00 2001 +From: mengqinggang +Date: Thu, 16 Nov 2023 19:19:16 +0800 +Subject: [PATCH] LoongArch: Add more relaxation testcases + +1. .so relaxation testcase +2. ld --no-relax testcase +3. segment alignment testcase + +Signed-off-by: Peng Fan +--- + .../ld-loongarch-elf/relax-segment-max.s | 12 +++ + .../ld-loongarch-elf/relax-segment-min.s | 12 +++ + ld/testsuite/ld-loongarch-elf/relax-so.s | 4 + + ld/testsuite/ld-loongarch-elf/relax.exp | 80 +++++++++++++++++-- + 4 files changed, 103 insertions(+), 5 deletions(-) + create mode 100644 ld/testsuite/ld-loongarch-elf/relax-segment-max.s + create mode 100644 ld/testsuite/ld-loongarch-elf/relax-segment-min.s + create mode 100644 ld/testsuite/ld-loongarch-elf/relax-so.s + +diff --git a/ld/testsuite/ld-loongarch-elf/relax-segment-max.s b/ld/testsuite/ld-loongarch-elf/relax-segment-max.s +new file mode 100644 +index 00000000000..df15d4cab09 +--- /dev/null ++++ b/ld/testsuite/ld-loongarch-elf/relax-segment-max.s +@@ -0,0 +1,12 @@ ++# The .align may cause overflow because deleting nops. ++ .text # 0x120004000 ++ .align 3 ++ la.local $r12, .L1 ++ ++# .fill 0x1f7ffc # max fill without overflow, .data address is 0x120200000 ++# .fill 0x1f8000 # min fill with overflow, .data address is 0x120204000 ++ .fill 0x1fbff4 # max fill with overflow, .data address is 0x120204000 ++ ++ .data ++.L1: ++ .byte 2 +diff --git a/ld/testsuite/ld-loongarch-elf/relax-segment-min.s b/ld/testsuite/ld-loongarch-elf/relax-segment-min.s +new file mode 100644 +index 00000000000..476b9fba78c +--- /dev/null ++++ b/ld/testsuite/ld-loongarch-elf/relax-segment-min.s +@@ -0,0 +1,12 @@ ++# The .align may cause overflow because deleting nops. ++ .text # 0x120004000 ++ .align 3 ++ la.local $r12, .L1 ++ ++# .fill 0x1f7ffc # max fill without overflow, .data address is 0x120200000 ++ .fill 0x1f8000 # min fill with overflow, .data address is 0x120204000 ++# .fill 0x1fbff4 # max fill with overflow, .data address is 0x120204000 ++ ++ .data ++.L1: ++ .byte 2 +diff --git a/ld/testsuite/ld-loongarch-elf/relax-so.s b/ld/testsuite/ld-loongarch-elf/relax-so.s +new file mode 100644 +index 00000000000..01a404a8b47 +--- /dev/null ++++ b/ld/testsuite/ld-loongarch-elf/relax-so.s +@@ -0,0 +1,4 @@ ++.text ++.align 2 ++.L1: ++ la.local $r12, .L1 +diff --git a/ld/testsuite/ld-loongarch-elf/relax.exp b/ld/testsuite/ld-loongarch-elf/relax.exp +index 7ff876d7914..24d79ed5c20 100644 +--- a/ld/testsuite/ld-loongarch-elf/relax.exp ++++ b/ld/testsuite/ld-loongarch-elf/relax.exp +@@ -22,7 +22,7 @@ + if [istarget loongarch64-*-*] { + + if [isbuild loongarch64-*-*] { +- set testname "loongarch relax build" ++ set testname "loongarch relax .exe build" + set pre_builds [list \ + [list \ + "$testname" \ +@@ -39,17 +39,87 @@ if [istarget loongarch64-*-*] { + if [file exist "tmpdir/relax"] { + set objdump_output [run_host_cmd "objdump" "-d tmpdir/relax"] + if { [ regexp ".*pcaddi.*pcaddi.*" $objdump_output] } { +- pass "loongarch relax" ++ pass "loongarch relax .exe" + } { +- fail "loongarch relax" ++ fail "loongarch relax .exe" + } + } ++ ++ set testname "loongarch ld --no-relax build" ++ set pre_builds [list \ ++ [list \ ++ "$testname" \ ++ "-Wl,--no-relax" \ ++ "" \ ++ {relax.s} \ ++ {} \ ++ "norelax" \ ++ ] \ ++ ] ++ ++ run_cc_link_tests $pre_builds ++ ++ if [file exist "tmpdir/norelax"] { ++ set objdump_output [run_host_cmd "objdump" "-d tmpdir/norelax"] ++ if { [ regexp ".*pcaddi.*" $objdump_output] } { ++ fail "loongarch ld --no-relax" ++ } { ++ pass "loongarch ld --no-relax" ++ } ++ } ++ ++ run_ld_link_tests \ ++ [list \ ++ [list \ ++ "loongarch relax .so build" \ ++ "-shared -e 0x0" "" \ ++ "" \ ++ {relax-so.s} \ ++ {} \ ++ "relax-so" \ ++ ] \ ++ ] ++ ++ if [file exist "tmpdir/relax-so"] { ++ set objdump_output [run_host_cmd "objdump" "-d tmpdir/relax-so"] ++ if { [ regexp ".*pcaddi.*" $objdump_output] } { ++ pass "loongarch relax .so" ++ } { ++ fail "loongarch relax .so" ++ } ++ } ++ ++ # If symbol in data segment, offset need to sub segment align to prevent ++ # overflow. ++ run_ld_link_tests \ ++ [list \ ++ [list \ ++ "loongarch relax segment alignment min" \ ++ "-e0 -Ttext 0x120004000 -pie -z relro" "" \ ++ "" \ ++ {relax-segment-min.s} \ ++ {} \ ++ "relax-segment-min" \ ++ ] \ ++ ] ++ ++ run_ld_link_tests \ ++ [list \ ++ [list \ ++ "loongarch relax segment alignment max" \ ++ "-e0 -Ttext 0x120004000 -pie -z relro" "" \ ++ "" \ ++ {relax-segment-max.s} \ ++ {} \ ++ "relax-segment-max" \ ++ ] \ ++ ] + } + + run_ld_link_tests \ + [list \ + [list \ +- "relax-align" \ ++ "loongarch relax-align" \ + "-e 0x0 -z relro" "" \ + "" \ + {relax-align.s} \ +@@ -64,7 +134,7 @@ if [istarget loongarch64-*-*] { + run_ld_link_tests \ + [list \ + [list \ +- "uleb128" \ ++ "loongarch uleb128" \ + "-e 0x0" "" \ + "" \ + {uleb128.s} \ +-- +2.33.0 + diff --git a/LoongArch-Directly-delete-relaxed-instuctions-in-fir.patch b/LoongArch-Directly-delete-relaxed-instuctions-in-fir.patch new file mode 100644 index 0000000000000000000000000000000000000000..fd9e585ecfc39646c6ad05a1b3ca4e22cf204aac --- /dev/null +++ b/LoongArch-Directly-delete-relaxed-instuctions-in-fir.patch @@ -0,0 +1,60 @@ +From 4e94082d95e046f357409cd689ffeedd60f6c673 Mon Sep 17 00:00:00 2001 +From: mengqinggang +Date: Thu, 16 Nov 2023 19:19:12 +0800 +Subject: [PATCH] LoongArch: Directly delete relaxed instuctions in first + relaxation pass + +Directly delete relaxed instuctions in first relaxation pass, not use +R_LARCH_DELETE relocation. If not, the PC-relative offset may increase. + +Signed-off-by: Peng Fan +--- + bfd/elfnn-loongarch.c | 12 +++++++----- + 1 file changed, 7 insertions(+), 5 deletions(-) + +diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c +index 1162cb35cd6..9d4ea7e4ae7 100644 +--- a/bfd/elfnn-loongarch.c ++++ b/bfd/elfnn-loongarch.c +@@ -3739,7 +3739,8 @@ loongarch_relax_delete_bytes (bfd *abfd, + /* Relax pcalau12i,addi.d => pcaddi. */ + static bool + loongarch_relax_pcala_addi (bfd *abfd, asection *sec, +- Elf_Internal_Rela *rel_hi, bfd_vma symval) ++ Elf_Internal_Rela *rel_hi, bfd_vma symval, ++ struct bfd_link_info *info) + { + bfd_byte *contents = elf_section_data (sec)->this_hdr.contents; + Elf_Internal_Rela *rel_lo = rel_hi + 2; +@@ -3771,8 +3772,9 @@ loongarch_relax_pcala_addi (bfd *abfd, asection *sec, + /* Adjust relocations. */ + rel_hi->r_info = ELFNN_R_INFO (ELFNN_R_SYM (rel_hi->r_info), + R_LARCH_PCREL20_S2); +- rel_lo->r_info = ELFNN_R_INFO (ELFNN_R_SYM (rel_hi->r_info), +- R_LARCH_DELETE); ++ rel_lo->r_info = ELFNN_R_INFO (0, R_LARCH_NONE); ++ ++ loongarch_relax_delete_bytes (abfd, sec, rel_lo->r_offset, 4, info); + + return true; + } +@@ -4004,14 +4006,14 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, + break; + case R_LARCH_PCALA_HI20: + if (0 == info->relax_pass && (i + 4) <= sec->reloc_count) +- loongarch_relax_pcala_addi (abfd, sec, rel, symval); ++ loongarch_relax_pcala_addi (abfd, sec, rel, symval, info); + break; + case R_LARCH_GOT_PC_HI20: + if (local_got && 0 == info->relax_pass + && (i + 4) <= sec->reloc_count) + { + if (loongarch_relax_pcala_ld (abfd, sec, rel)) +- loongarch_relax_pcala_addi (abfd, sec, rel, symval); ++ loongarch_relax_pcala_addi (abfd, sec, rel, symval, info); + } + break; + default: +-- +2.33.0 + diff --git a/LoongArch-Fix-ld-no-relax-bug.patch b/LoongArch-Fix-ld-no-relax-bug.patch new file mode 100644 index 0000000000000000000000000000000000000000..756fda74128b3d42e759a3b5c23079e7495d5fe2 --- /dev/null +++ b/LoongArch-Fix-ld-no-relax-bug.patch @@ -0,0 +1,56 @@ +From 363174776d13db9f35f2e54d8f7f5e34b64acbee Mon Sep 17 00:00:00 2001 +From: mengqinggang +Date: Thu, 16 Nov 2023 19:19:11 +0800 +Subject: [PATCH] LoongArch: Fix ld --no-relax bug + +When calling ld with --no-relax, pcalau12i + ld.d still can be relaxed. +This patch fix this bug and pcalau12i + ld.d can be relaxed with --relax. + +Signed-off-by: Peng Fan +--- + bfd/elfnn-loongarch.c | 19 ++++++------------- + 1 file changed, 6 insertions(+), 13 deletions(-) + +diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c +index 18ad3cc91ca..1162cb35cd6 100644 +--- a/bfd/elfnn-loongarch.c ++++ b/bfd/elfnn-loongarch.c +@@ -3996,29 +3996,22 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, + loongarch_relax_align (abfd, sec, sym_sec, info, rel, symval); + break; + case R_LARCH_DELETE: +- if (info->relax_pass == 1) ++ if (1 == info->relax_pass) + { + loongarch_relax_delete_bytes (abfd, sec, rel->r_offset, 4, info); + rel->r_info = ELFNN_R_INFO (0, R_LARCH_NONE); + } + break; + case R_LARCH_PCALA_HI20: +- if (info->relax_pass == 0) +- { +- if (i + 4 > sec->reloc_count) +- break; +- loongarch_relax_pcala_addi (abfd, sec, rel, symval); +- } ++ if (0 == info->relax_pass && (i + 4) <= sec->reloc_count) ++ loongarch_relax_pcala_addi (abfd, sec, rel, symval); + break; + case R_LARCH_GOT_PC_HI20: +- if (local_got) ++ if (local_got && 0 == info->relax_pass ++ && (i + 4) <= sec->reloc_count) + { +- if (i + 4 > sec->reloc_count) +- break; + if (loongarch_relax_pcala_ld (abfd, sec, rel)) +- { +- loongarch_relax_pcala_addi (abfd, sec, rel, symval); +- } ++ loongarch_relax_pcala_addi (abfd, sec, rel, symval); + } + break; + default: +-- +2.33.0 + diff --git a/LoongArch-Modify-link_info.relax_pass-from-3-to-2.patch b/LoongArch-Modify-link_info.relax_pass-from-3-to-2.patch new file mode 100644 index 0000000000000000000000000000000000000000..a576bb90ba727069dfd84aeffc8e7e1c0512d631 --- /dev/null +++ b/LoongArch-Modify-link_info.relax_pass-from-3-to-2.patch @@ -0,0 +1,43 @@ +From 8338aecd231af48483e36c93c103db1da715ac74 Mon Sep 17 00:00:00 2001 +From: mengqinggang +Date: Thu, 16 Nov 2023 19:19:15 +0800 +Subject: [PATCH] LoongArch: Modify link_info.relax_pass from 3 to 2 + +The first pass handles R_LARCH_RELAX relocations, the second pass +handles R_LARCH_ALIGN relocations. + +Signed-off-by: Peng Fan +--- + bfd/elfnn-loongarch.c | 2 +- + ld/emultempl/loongarchelf.em | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c +index 987e5b98bc0..024c5d4cd96 100644 +--- a/bfd/elfnn-loongarch.c ++++ b/bfd/elfnn-loongarch.c +@@ -4013,7 +4013,7 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, + switch (ELFNN_R_TYPE (rel->r_info)) + { + case R_LARCH_ALIGN: +- if (2 == info->relax_pass) ++ if (1 == info->relax_pass) + loongarch_relax_align (abfd, sec, sym_sec, info, rel, symval); + break; + case R_LARCH_DELETE: +diff --git a/ld/emultempl/loongarchelf.em b/ld/emultempl/loongarchelf.em +index d81c99da48b..9974989489c 100644 +--- a/ld/emultempl/loongarchelf.em ++++ b/ld/emultempl/loongarchelf.em +@@ -42,7 +42,7 @@ larch_elf_before_allocation (void) + ENABLE_RELAXATION; + } + +- link_info.relax_pass = 3; ++ link_info.relax_pass = 2; + } + + static void +-- +2.33.0 + diff --git a/LoongArch-Multiple-relax_trip-in-one-relax_pass.patch b/LoongArch-Multiple-relax_trip-in-one-relax_pass.patch new file mode 100644 index 0000000000000000000000000000000000000000..20f0a39ed3654618e406e5ce60ad49551cf04474 --- /dev/null +++ b/LoongArch-Multiple-relax_trip-in-one-relax_pass.patch @@ -0,0 +1,57 @@ +From b130a0849a1b3e174210903cf5370092decc62d6 Mon Sep 17 00:00:00 2001 +From: mengqinggang +Date: Thu, 16 Nov 2023 19:19:13 +0800 +Subject: [PATCH] LoongArch: Multiple relax_trip in one relax_pass + +If deleting instructions in one relax_trip, set again to true to start the +next relax_trip. + +Signed-off-by: Peng Fan +--- + bfd/elfnn-loongarch.c | 10 +++++++--- + 1 file changed, 7 insertions(+), 3 deletions(-) + +diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c +index 9d4ea7e4ae7..7436a14441f 100644 +--- a/bfd/elfnn-loongarch.c ++++ b/bfd/elfnn-loongarch.c +@@ -3740,7 +3740,7 @@ loongarch_relax_delete_bytes (bfd *abfd, + static bool + loongarch_relax_pcala_addi (bfd *abfd, asection *sec, + Elf_Internal_Rela *rel_hi, bfd_vma symval, +- struct bfd_link_info *info) ++ struct bfd_link_info *info, bool *again) + { + bfd_byte *contents = elf_section_data (sec)->this_hdr.contents; + Elf_Internal_Rela *rel_lo = rel_hi + 2; +@@ -3766,6 +3766,9 @@ loongarch_relax_pcala_addi (bfd *abfd, asection *sec, + || ((bfd_signed_vma)(symval - pc) > (bfd_signed_vma)(int32_t)0x1ffffc)) + return false; + ++ /* Continue next relax trip. */ ++ *again = true; ++ + pca = pcaddi | rd; + bfd_put (32, abfd, pca, contents + rel_hi->r_offset); + +@@ -4006,14 +4009,15 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, + break; + case R_LARCH_PCALA_HI20: + if (0 == info->relax_pass && (i + 4) <= sec->reloc_count) +- loongarch_relax_pcala_addi (abfd, sec, rel, symval, info); ++ loongarch_relax_pcala_addi (abfd, sec, rel, symval, info, again); + break; + case R_LARCH_GOT_PC_HI20: + if (local_got && 0 == info->relax_pass + && (i + 4) <= sec->reloc_count) + { + if (loongarch_relax_pcala_ld (abfd, sec, rel)) +- loongarch_relax_pcala_addi (abfd, sec, rel, symval, info); ++ loongarch_relax_pcala_addi (abfd, sec, rel, symval, ++ info, again); + } + break; + default: +-- +2.33.0 + diff --git a/LoongArch-Remove-elf_seg_map-info-output_bfd-NULL-re.patch b/LoongArch-Remove-elf_seg_map-info-output_bfd-NULL-re.patch new file mode 100644 index 0000000000000000000000000000000000000000..bceee08335e14fc8a2d1e395378ae39075e79120 --- /dev/null +++ b/LoongArch-Remove-elf_seg_map-info-output_bfd-NULL-re.patch @@ -0,0 +1,112 @@ +From 4f2469d0cdd0f3bd1d9040521e002e8df0a63a98 Mon Sep 17 00:00:00 2001 +From: mengqinggang +Date: Thu, 16 Nov 2023 19:19:14 +0800 +Subject: [PATCH] LoongArch: Remove "elf_seg_map (info->output_bfd) == NULL" + relaxation condition + +Previously the condition prevented shared objects from being relaxed. +To remove the limitation, we need to update program header size and +.eh_frame_hdr size before relaxation. + +Signed-off-by: Peng Fan +--- + bfd/elfnn-loongarch.c | 25 +++++++++++++++++++++---- + ld/emultempl/loongarchelf.em | 18 ++++++++++++++++++ + 2 files changed, 39 insertions(+), 4 deletions(-) + +diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c +index 7436a14441f..987e5b98bc0 100644 +--- a/bfd/elfnn-loongarch.c ++++ b/bfd/elfnn-loongarch.c +@@ -3738,7 +3738,7 @@ loongarch_relax_delete_bytes (bfd *abfd, + + /* Relax pcalau12i,addi.d => pcaddi. */ + static bool +-loongarch_relax_pcala_addi (bfd *abfd, asection *sec, ++loongarch_relax_pcala_addi (bfd *abfd, asection *sec, asection *sym_sec, + Elf_Internal_Rela *rel_hi, bfd_vma symval, + struct bfd_link_info *info, bool *again) + { +@@ -3747,7 +3747,24 @@ loongarch_relax_pcala_addi (bfd *abfd, asection *sec, + uint32_t pca = bfd_get (32, abfd, contents + rel_hi->r_offset); + uint32_t add = bfd_get (32, abfd, contents + rel_lo->r_offset); + uint32_t rd = pca & 0x1f; ++ ++ /* This section's output_offset need to subtract the bytes of instructions ++ relaxed by the previous sections, so it needs to be updated beforehand. ++ size_input_section already took care of updating it after relaxation, ++ so we additionally update once here. */ ++ sec->output_offset = sec->output_section->size; + bfd_vma pc = sec_addr (sec) + rel_hi->r_offset; ++ ++ /* If pc and symbol not in the same segment, add/sub segment alignment. ++ FIXME: if there are multiple readonly segments? */ ++ if (!(sym_sec->flags & SEC_READONLY)) ++ { ++ if (symval > pc) ++ pc -= info->maxpagesize; ++ else if (symval < pc) ++ pc += info->maxpagesize; ++ } ++ + const uint32_t addi_d = 0x02c00000; + const uint32_t pcaddi = 0x18000000; + +@@ -3889,7 +3906,6 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, + || sec->sec_flg0 + || (sec->flags & SEC_RELOC) == 0 + || sec->reloc_count == 0 +- || elf_seg_map (info->output_bfd) == NULL + || (info->disable_target_specific_optimizations + && info->relax_pass == 0) + /* The exp_seg_relro_adjust is enum phase_enum (0x4), +@@ -4009,14 +4025,15 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, + break; + case R_LARCH_PCALA_HI20: + if (0 == info->relax_pass && (i + 4) <= sec->reloc_count) +- loongarch_relax_pcala_addi (abfd, sec, rel, symval, info, again); ++ loongarch_relax_pcala_addi (abfd, sec, sym_sec, rel, symval, ++ info, again); + break; + case R_LARCH_GOT_PC_HI20: + if (local_got && 0 == info->relax_pass + && (i + 4) <= sec->reloc_count) + { + if (loongarch_relax_pcala_ld (abfd, sec, rel)) +- loongarch_relax_pcala_addi (abfd, sec, rel, symval, ++ loongarch_relax_pcala_addi (abfd, sec, sym_sec, rel, symval, + info, again); + } + break; +diff --git a/ld/emultempl/loongarchelf.em b/ld/emultempl/loongarchelf.em +index 4850feb8767..d81c99da48b 100644 +--- a/ld/emultempl/loongarchelf.em ++++ b/ld/emultempl/loongarchelf.em +@@ -62,6 +62,24 @@ gld${EMULATION_NAME}_after_allocation (void) + } + } + ++ /* The program header size of executable file may increase. */ ++ if (bfd_get_flavour (link_info.output_bfd) == bfd_target_elf_flavour ++ && !bfd_link_relocatable (&link_info)) ++ { ++ if (lang_phdr_list == NULL) ++ elf_seg_map (link_info.output_bfd) = NULL; ++ if (!_bfd_elf_map_sections_to_segments (link_info.output_bfd, ++ &link_info, ++ NULL)) ++ einfo (_("%F%P: map sections to segments failed: %E\n")); ++ } ++ ++ /* Adjust program header size and .eh_frame_hdr size before ++ lang_relax_sections. Without it, the vma of data segment may increase. */ ++ lang_do_assignments (lang_allocating_phase_enum); ++ lang_reset_memory_regions (); ++ lang_size_sections (NULL, true); ++ + enum phase_enum *phase = &(expld.dataseg.phase); + bfd_elf${ELFSIZE}_loongarch_set_data_segment_info (&link_info, (int *) phase); + /* gld${EMULATION_NAME}_map_segments (need_layout); */ +-- +2.33.0 + diff --git a/LoongArch-fix-internal-error-when-as-handling-unsupp.patch b/LoongArch-fix-internal-error-when-as-handling-unsupp.patch new file mode 100644 index 0000000000000000000000000000000000000000..dda03c58792a98d62b950615e118d071ff2b301f --- /dev/null +++ b/LoongArch-fix-internal-error-when-as-handling-unsupp.patch @@ -0,0 +1,78 @@ +From df4ffdd8c87b32357f929fb4a861760038f3bbb8 Mon Sep 17 00:00:00 2001 +From: Lulu Cai +Date: Wed, 15 Nov 2023 19:20:53 +0800 +Subject: [PATCH] LoongArch: fix internal error when as handling unsupported + modifier. + +Signed-off-by: Peng Fan +--- + bfd/elfxx-loongarch.c | 3 --- + gas/config/loongarch-parse.y | 6 +++++- + gas/testsuite/gas/loongarch/reloc_type.d | 3 +++ + gas/testsuite/gas/loongarch/reloc_type.l | 2 ++ + gas/testsuite/gas/loongarch/reloc_type.s | 3 +++ + 5 files changed, 13 insertions(+), 4 deletions(-) + create mode 100644 gas/testsuite/gas/loongarch/reloc_type.d + create mode 100644 gas/testsuite/gas/loongarch/reloc_type.l + create mode 100644 gas/testsuite/gas/loongarch/reloc_type.s + +diff --git a/bfd/elfxx-loongarch.c b/bfd/elfxx-loongarch.c +index a970a257aa9..7f298c08fd3 100644 +--- a/bfd/elfxx-loongarch.c ++++ b/bfd/elfxx-loongarch.c +@@ -1629,9 +1629,6 @@ loongarch_larch_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED, + return lht->bfd_type; + } + +- (*_bfd_error_handler) (_("%pB: unsupported relocation type name %s"), +- abfd, l_r_name); +- bfd_set_error (bfd_error_bad_value); + return BFD_RELOC_NONE; + } + +diff --git a/gas/config/loongarch-parse.y b/gas/config/loongarch-parse.y +index f4e1a63b972..f786fdaee5f 100644 +--- a/gas/config/loongarch-parse.y ++++ b/gas/config/loongarch-parse.y +@@ -132,7 +132,11 @@ reloc (const char *op_c_str, const char *id_c_str, offsetT addend) + if (0 == strcmp (op_c_str, "plt")) + btype = BFD_RELOC_LARCH_B26; + else +- btype = loongarch_larch_reloc_name_lookup (NULL, op_c_str); ++ { ++ btype = loongarch_larch_reloc_name_lookup (NULL, op_c_str); ++ if (btype == BFD_RELOC_NONE) ++ as_fatal (_("unsupported modifier %s"), op_c_str); ++ } + + if (id_c_str) + { +diff --git a/gas/testsuite/gas/loongarch/reloc_type.d b/gas/testsuite/gas/loongarch/reloc_type.d +new file mode 100644 +index 00000000000..0a8f77825a0 +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/reloc_type.d +@@ -0,0 +1,3 @@ ++#as: ++#source: reloc_type.s ++#error_output: reloc_type.l +diff --git a/gas/testsuite/gas/loongarch/reloc_type.l b/gas/testsuite/gas/loongarch/reloc_type.l +new file mode 100644 +index 00000000000..e981f6f2aa5 +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/reloc_type.l +@@ -0,0 +1,2 @@ ++.*Assembler messages: ++.*Fatal error: unsupported modifier (.*)$ +diff --git a/gas/testsuite/gas/loongarch/reloc_type.s b/gas/testsuite/gas/loongarch/reloc_type.s +new file mode 100644 +index 00000000000..2ce277779db +--- /dev/null ++++ b/gas/testsuite/gas/loongarch/reloc_type.s +@@ -0,0 +1,3 @@ ++.L1: ++ nop ++ addi.d $a0,$a1,%reloc(x) +-- +2.33.0 + diff --git a/as-Add-new-atomic-instructions-in-LoongArch-v1.1.patch b/as-Add-new-atomic-instructions-in-LoongArch-v1.1.patch new file mode 100644 index 0000000000000000000000000000000000000000..46038e6c91731f08b37c2a7797e740f757285354 --- /dev/null +++ b/as-Add-new-atomic-instructions-in-LoongArch-v1.1.patch @@ -0,0 +1,199 @@ +From 9ff4752d0f6d46ca0f7d275ea07e05790ac8dd1d Mon Sep 17 00:00:00 2001 +From: Jiajie Chen +Date: Thu, 26 Oct 2023 17:35:13 +0800 +Subject: [PATCH] as: Add new atomic instructions in LoongArch v1.1 + +LoongArch V1.1 release is out at +https://github.com/loongson/LoongArch-Documentation. + +New atomic instructions in LoongArch v1.1: + +- sc.q +- llacq.w/d +- screl.w/d +- amcas{_db}.b/h/w/d +- amswap{_db}.b/h +- amadd{_db}.b/h + +Signed-off-by: Jiajie Chen +Signed-off-by: Peng Fan +--- + gas/config/tc-loongarch.c | 6 ++- + gas/testsuite/gas/loongarch/load_store_op.d | 42 +++++++++++++++++++++ + gas/testsuite/gas/loongarch/load_store_op.s | 42 +++++++++++++++++++++ + opcodes/loongarch-opc.c | 42 +++++++++++++++++++++ + 4 files changed, 130 insertions(+), 2 deletions(-) + +diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c +index d1ce111c186..59232832cf7 100644 +--- a/gas/config/tc-loongarch.c ++++ b/gas/config/tc-loongarch.c +@@ -893,8 +893,10 @@ check_this_insn_before_appending (struct loongarch_cl_insn *ip) + ip->reloc_num++; + } + else if (ip->insn->mask == 0xffff8000 +- /* amswap.w rd, rk, rj */ +- && ((ip->insn_bin & 0xfff00000) == 0x38600000 ++ /* amcas.b rd, rk, rj */ ++ && ((ip->insn_bin & 0xfff80000) == 0x38580000 ++ /* amswap.w rd, rk, rj */ ++ || (ip->insn_bin & 0xfff00000) == 0x38600000 + /* ammax_db.wu rd, rk, rj */ + || (ip->insn_bin & 0xffff0000) == 0x38700000 + /* ammin_db.wu rd, rk, rj */ +diff --git a/gas/testsuite/gas/loongarch/load_store_op.d b/gas/testsuite/gas/loongarch/load_store_op.d +index e1b4dea1851..0ad83167bbc 100644 +--- a/gas/testsuite/gas/loongarch/load_store_op.d ++++ b/gas/testsuite/gas/loongarch/load_store_op.d +@@ -176,3 +176,45 @@ Disassembly of section .text: + 298:[ ]+387e98a4 [ ]+stle.h[ ]+[ ]+\$a0, \$a1, \$a2 + 29c:[ ]+387f18a4 [ ]+stle.w[ ]+[ ]+\$a0, \$a1, \$a2 + 2a0:[ ]+387f98a4 [ ]+stle.d[ ]+[ ]+\$a0, \$a1, \$a2 ++ 2a4:[ ]+385714c4 [ ]+sc.q[ ]+[ ]+\$a0, \$a1, \$a2 ++ 2a8:[ ]+385714c4 [ ]+sc.q[ ]+[ ]+\$a0, \$a1, \$a2 ++ 2ac:[ ]+385780a4 [ ]+llacq.w[ ]+[ ]+\$a0, \$a1 ++ 2b0:[ ]+385780a4 [ ]+llacq.w[ ]+[ ]+\$a0, \$a1 ++ 2b4:[ ]+385784a4 [ ]+screl.w[ ]+[ ]+\$a0, \$a1 ++ 2b8:[ ]+385784a4 [ ]+screl.w[ ]+[ ]+\$a0, \$a1 ++ 2bc:[ ]+385788a4 [ ]+llacq.d[ ]+[ ]+\$a0, \$a1 ++ 2c0:[ ]+385788a4 [ ]+llacq.d[ ]+[ ]+\$a0, \$a1 ++ 2c4:[ ]+38578ca4 [ ]+screl.d[ ]+[ ]+\$a0, \$a1 ++ 2c8:[ ]+38578ca4 [ ]+screl.d[ ]+[ ]+\$a0, \$a1 ++ 2cc:[ ]+385814c4 [ ]+amcas.b[ ]+[ ]+\$a0, \$a1, \$a2 ++ 2d0:[ ]+385818a4 [ ]+amcas.b[ ]+[ ]+\$a0, \$a2, \$a1 ++ 2d4:[ ]+385894c4 [ ]+amcas.h[ ]+[ ]+\$a0, \$a1, \$a2 ++ 2d8:[ ]+385898a4 [ ]+amcas.h[ ]+[ ]+\$a0, \$a2, \$a1 ++ 2dc:[ ]+385914c4 [ ]+amcas.w[ ]+[ ]+\$a0, \$a1, \$a2 ++ 2e0:[ ]+385918a4 [ ]+amcas.w[ ]+[ ]+\$a0, \$a2, \$a1 ++ 2e4:[ ]+385994c4 [ ]+amcas.d[ ]+[ ]+\$a0, \$a1, \$a2 ++ 2e8:[ ]+385998a4 [ ]+amcas.d[ ]+[ ]+\$a0, \$a2, \$a1 ++ 2ec:[ ]+385a14c4 [ ]+amcas_db.b[ ]+[ ]+\$a0, \$a1, \$a2 ++ 2f0:[ ]+385a18a4 [ ]+amcas_db.b[ ]+[ ]+\$a0, \$a2, \$a1 ++ 2f4:[ ]+385a94c4 [ ]+amcas_db.h[ ]+[ ]+\$a0, \$a1, \$a2 ++ 2f8:[ ]+385a98a4 [ ]+amcas_db.h[ ]+[ ]+\$a0, \$a2, \$a1 ++ 2fc:[ ]+385b14c4 [ ]+amcas_db.w[ ]+[ ]+\$a0, \$a1, \$a2 ++ 300:[ ]+385b18a4 [ ]+amcas_db.w[ ]+[ ]+\$a0, \$a2, \$a1 ++ 304:[ ]+385b94c4 [ ]+amcas_db.d[ ]+[ ]+\$a0, \$a1, \$a2 ++ 308:[ ]+385b98a4 [ ]+amcas_db.d[ ]+[ ]+\$a0, \$a2, \$a1 ++ 30c:[ ]+385c14c4 [ ]+amswap.b[ ]+[ ]+\$a0, \$a1, \$a2 ++ 310:[ ]+385c18a4 [ ]+amswap.b[ ]+[ ]+\$a0, \$a2, \$a1 ++ 314:[ ]+385c94c4 [ ]+amswap.h[ ]+[ ]+\$a0, \$a1, \$a2 ++ 318:[ ]+385c98a4 [ ]+amswap.h[ ]+[ ]+\$a0, \$a2, \$a1 ++ 31c:[ ]+385d14c4 [ ]+amadd.b[ ]+[ ]+\$a0, \$a1, \$a2 ++ 320:[ ]+385d18a4 [ ]+amadd.b[ ]+[ ]+\$a0, \$a2, \$a1 ++ 324:[ ]+385d94c4 [ ]+amadd.h[ ]+[ ]+\$a0, \$a1, \$a2 ++ 328:[ ]+385d98a4 [ ]+amadd.h[ ]+[ ]+\$a0, \$a2, \$a1 ++ 32c:[ ]+385e14c4 [ ]+amswap_db.b[ ]+[ ]+\$a0, \$a1, \$a2 ++ 330:[ ]+385e18a4 [ ]+amswap_db.b[ ]+[ ]+\$a0, \$a2, \$a1 ++ 334:[ ]+385e94c4 [ ]+amswap_db.h[ ]+[ ]+\$a0, \$a1, \$a2 ++ 338:[ ]+385e98a4 [ ]+amswap_db.h[ ]+[ ]+\$a0, \$a2, \$a1 ++ 33c:[ ]+385f14c4 [ ]+amadd_db.b[ ]+[ ]+\$a0, \$a1, \$a2 ++ 340:[ ]+385f18a4 [ ]+amadd_db.b[ ]+[ ]+\$a0, \$a2, \$a1 ++ 344:[ ]+385f94c4 [ ]+amadd_db.h[ ]+[ ]+\$a0, \$a1, \$a2 ++ 348:[ ]+385f98a4 [ ]+amadd_db.h[ ]+[ ]+\$a0, \$a2, \$a1 +diff --git a/gas/testsuite/gas/loongarch/load_store_op.s b/gas/testsuite/gas/loongarch/load_store_op.s +index efbd124a29c..7912adb1090 100644 +--- a/gas/testsuite/gas/loongarch/load_store_op.s ++++ b/gas/testsuite/gas/loongarch/load_store_op.s +@@ -167,3 +167,45 @@ stle.b $r4,$r5,$r6 + stle.h $r4,$r5,$r6 + stle.w $r4,$r5,$r6 + stle.d $r4,$r5,$r6 ++sc.q $r4,$r5,$r6,0 ++sc.q $r4,$r5,$r6 ++llacq.w $r4,$r5,0 ++llacq.w $r4,$r5 ++screl.w $r4,$r5,0 ++screl.w $r4,$r5 ++llacq.d $r4,$r5,0 ++llacq.d $r4,$r5 ++screl.d $r4,$r5,0 ++screl.d $r4,$r5 ++amcas.b $r4,$r5,$r6,0 ++amcas.b $r4,$r6,$r5 ++amcas.h $r4,$r5,$r6,0 ++amcas.h $r4,$r6,$r5 ++amcas.w $r4,$r5,$r6,0 ++amcas.w $r4,$r6,$r5 ++amcas.d $r4,$r5,$r6,0 ++amcas.d $r4,$r6,$r5 ++amcas_db.b $r4,$r5,$r6,0 ++amcas_db.b $r4,$r6,$r5 ++amcas_db.h $r4,$r5,$r6,0 ++amcas_db.h $r4,$r6,$r5 ++amcas_db.w $r4,$r5,$r6,0 ++amcas_db.w $r4,$r6,$r5 ++amcas_db.d $r4,$r5,$r6,0 ++amcas_db.d $r4,$r6,$r5 ++amswap.b $r4,$r5,$r6,0 ++amswap.b $r4,$r6,$r5 ++amswap.h $r4,$r5,$r6,0 ++amswap.h $r4,$r6,$r5 ++amadd.b $r4,$r5,$r6,0 ++amadd.b $r4,$r6,$r5 ++amadd.h $r4,$r5,$r6,0 ++amadd.h $r4,$r6,$r5 ++amswap_db.b $r4,$r5,$r6,0 ++amswap_db.b $r4,$r6,$r5 ++amswap_db.h $r4,$r5,$r6,0 ++amswap_db.h $r4,$r6,$r5 ++amadd_db.b $r4,$r5,$r6,0 ++amadd_db.b $r4,$r6,$r5 ++amadd_db.h $r4,$r5,$r6,0 ++amadd_db.h $r4,$r6,$r5 +diff --git a/opcodes/loongarch-opc.c b/opcodes/loongarch-opc.c +index 82b88bdad2a..e110735e857 100644 +--- a/opcodes/loongarch-opc.c ++++ b/opcodes/loongarch-opc.c +@@ -816,6 +816,48 @@ static struct loongarch_opcode loongarch_load_store_opcodes[] = + { 0x38240000, 0xffff8000, "ldx.hu", "r0:5,r5:5,r10:5", 0, 0, 0, 0 }, + { 0x38280000, 0xffff8000, "ldx.wu", "r0:5,r5:5,r10:5", 0, 0, 0, 0 }, + { 0x382c0000, 0xffff8000, "preldx", "u0:5,r5:5,r10:5", 0, 0, 0, 0 }, ++ { 0x0, 0x0, "sc.q", "r,r,r,u0:0", "sc.q %1,%2,%3", 0, 0, 0 }, ++ { 0x38570000, 0xffff8000, "sc.q", "r0:5,r10:5,r5:5", 0, 0, 0, 0 }, ++ { 0x0, 0x0, "llacq.w", "r,r,u0:0", "llacq.w %1,%2", 0, 0, 0 }, ++ { 0x38578000, 0xfffffc00, "llacq.w", "r0:5,r5:5", 0, 0, 0, 0 }, ++ { 0x0, 0x0, "screl.w", "r,r,u0:0", "screl.w %1,%2", 0, 0, 0 }, ++ { 0x38578400, 0xfffffc00, "screl.w", "r0:5,r5:5", 0, 0, 0, 0 }, ++ { 0x0, 0x0, "llacq.d", "r,r,u0:0", "llacq.d %1,%2", 0, 0, 0 }, ++ { 0x38578800, 0xfffffc00, "llacq.d", "r0:5,r5:5", 0, 0, 0, 0 }, ++ { 0x0, 0x0, "screl.d", "r,r,u0:0", "screl.d %1,%2", 0, 0, 0 }, ++ { 0x38578c00, 0xfffffc00, "screl.d", "r0:5,r5:5", 0, 0, 0, 0 }, ++ { 0x0, 0x0, "amcas.b", "r,r,r,u0:0", "amcas.b %1,%2,%3", 0, 0, 0 }, ++ { 0x38580000, 0xffff8000, "amcas.b", "r0:5,r10:5,r5:5", 0, 0, 0, 0 }, ++ { 0x0, 0x0, "amcas.h", "r,r,r,u0:0", "amcas.h %1,%2,%3", 0, 0, 0 }, ++ { 0x38588000, 0xffff8000, "amcas.h", "r0:5,r10:5,r5:5", 0, 0, 0, 0 }, ++ { 0x0, 0x0, "amcas.w", "r,r,r,u0:0", "amcas.w %1,%2,%3", 0, 0, 0 }, ++ { 0x38590000, 0xffff8000, "amcas.w", "r0:5,r10:5,r5:5", 0, 0, 0, 0 }, ++ { 0x0, 0x0, "amcas.d", "r,r,r,u0:0", "amcas.d %1,%2,%3", 0, 0, 0 }, ++ { 0x38598000, 0xffff8000, "amcas.d", "r0:5,r10:5,r5:5", 0, 0, 0, 0 }, ++ { 0x0, 0x0, "amcas_db.b", "r,r,r,u0:0", "amcas_db.b %1,%2,%3", 0, 0, 0 }, ++ { 0x385a0000, 0xffff8000, "amcas_db.b", "r0:5,r10:5,r5:5", 0, 0, 0, 0 }, ++ { 0x0, 0x0, "amcas_db.h", "r,r,r,u0:0", "amcas_db.h %1,%2,%3", 0, 0, 0 }, ++ { 0x385a8000, 0xffff8000, "amcas_db.h", "r0:5,r10:5,r5:5", 0, 0, 0, 0 }, ++ { 0x0, 0x0, "amcas_db.w", "r,r,r,u0:0", "amcas_db.w %1,%2,%3", 0, 0, 0 }, ++ { 0x385b0000, 0xffff8000, "amcas_db.w", "r0:5,r10:5,r5:5", 0, 0, 0, 0 }, ++ { 0x0, 0x0, "amcas_db.d", "r,r,r,u0:0", "amcas_db.d %1,%2,%3", 0, 0, 0 }, ++ { 0x385b8000, 0xffff8000, "amcas_db.d", "r0:5,r10:5,r5:5", 0, 0, 0, 0 }, ++ { 0x0, 0x0, "amswap.b", "r,r,r,u0:0", "amswap.b %1,%2,%3", 0, 0, 0 }, ++ { 0x385c0000, 0xffff8000, "amswap.b", "r0:5,r10:5,r5:5", 0, 0, 0, 0 }, ++ { 0x0, 0x0, "amswap.h", "r,r,r,u0:0", "amswap.h %1,%2,%3", 0, 0, 0 }, ++ { 0x385c8000, 0xffff8000, "amswap.h", "r0:5,r10:5,r5:5", 0, 0, 0, 0 }, ++ { 0x0, 0x0, "amadd.b", "r,r,r,u0:0", "amadd.b %1,%2,%3", 0, 0, 0 }, ++ { 0x385d0000, 0xffff8000, "amadd.b", "r0:5,r10:5,r5:5", 0, 0, 0, 0 }, ++ { 0x0, 0x0, "amadd.h", "r,r,r,u0:0", "amadd.h %1,%2,%3", 0, 0, 0 }, ++ { 0x385d8000, 0xffff8000, "amadd.h", "r0:5,r10:5,r5:5", 0, 0, 0, 0 }, ++ { 0x0, 0x0, "amswap_db.b", "r,r,r,u0:0", "amswap_db.b %1,%2,%3", 0, 0, 0 }, ++ { 0x385e0000, 0xffff8000, "amswap_db.b", "r0:5,r10:5,r5:5", 0, 0, 0, 0 }, ++ { 0x0, 0x0, "amswap_db.h", "r,r,r,u0:0", "amswap_db.h %1,%2,%3", 0, 0, 0 }, ++ { 0x385e8000, 0xffff8000, "amswap_db.h", "r0:5,r10:5,r5:5", 0, 0, 0, 0 }, ++ { 0x0, 0x0, "amadd_db.b", "r,r,r,u0:0", "amadd_db.b %1,%2,%3", 0, 0, 0 }, ++ { 0x385f0000, 0xffff8000, "amadd_db.b", "r0:5,r10:5,r5:5", 0, 0, 0, 0 }, ++ { 0x0, 0x0, "amadd_db.h", "r,r,r,u0:0", "amadd_db.h %1,%2,%3", 0, 0, 0 }, ++ { 0x385f8000, 0xffff8000, "amadd_db.h", "r0:5,r10:5,r5:5", 0, 0, 0, 0 }, + { 0x0, 0x0, "amswap.w", "r,r,r,u0:0", "amswap.w %1,%2,%3", 0, 0, 0 }, + { 0x38600000, 0xffff8000, "amswap.w", "r0:5,r10:5,r5:5", 0, 0, 0, 0 }, + { 0x0, 0x0, "amswap.d", "r,r,r,u0:0", "amswap.d %1,%2,%3", 0, 0, 0 }, +-- +2.33.0 + diff --git a/as-Add-new-estimated-reciprocal-instructions-in-Loon.patch b/as-Add-new-estimated-reciprocal-instructions-in-Loon.patch new file mode 100644 index 0000000000000000000000000000000000000000..54beba752a8a0d0ba240b81dfabe461033840088 --- /dev/null +++ b/as-Add-new-estimated-reciprocal-instructions-in-Loon.patch @@ -0,0 +1,128 @@ +From cd51849c90e8fd13779bec69f5d4c7aadf03a532 Mon Sep 17 00:00:00 2001 +From: Jiajie Chen +Date: Thu, 26 Oct 2023 17:35:14 +0800 +Subject: [PATCH] as: Add new estimated reciprocal instructions in LoongArch + v1.1 + +New estimated reciprocal instructions in LoongArch v1.1: + +- frecipe.s/d +- frsqrte.s/d +- vfrecipe.s/d +- vfrsqrte.s/d +- xvfrecipe.s/d +- xvfrsqrte.s/d + +Signed-off-by: Jiajie Chen +Signed-off-by: Peng Fan +--- + gas/testsuite/gas/loongarch/float_op.d | 4 ++++ + gas/testsuite/gas/loongarch/float_op.s | 4 ++++ + gas/testsuite/gas/loongarch/vector.d | 8 ++++++++ + gas/testsuite/gas/loongarch/vector.s | 8 ++++++++ + opcodes/loongarch-opc.c | 12 ++++++++++++ + 5 files changed, 36 insertions(+) + +diff --git a/gas/testsuite/gas/loongarch/float_op.d b/gas/testsuite/gas/loongarch/float_op.d +index f9d3b89e4a0..b09e7ba0f21 100644 +--- a/gas/testsuite/gas/loongarch/float_op.d ++++ b/gas/testsuite/gas/loongarch/float_op.d +@@ -83,3 +83,7 @@ Disassembly of section .text: + [ ]+124:[ ]+011d2820 [ ]+ffint.d.l[ ]+[ ]+\$fa0, \$fa1 + [ ]+128:[ ]+011e4420 [ ]+frint.s[ ]+[ ]+\$fa0, \$fa1 + [ ]+12c:[ ]+011e4820 [ ]+frint.d[ ]+[ ]+\$fa0, \$fa1 ++[ ]+130:[ ]+01147420 [ ]+frecipe.s[ ]+[ ]+\$fa0, \$fa1 ++[ ]+134:[ ]+01147820 [ ]+frecipe.d[ ]+[ ]+\$fa0, \$fa1 ++[ ]+138:[ ]+01148420 [ ]+frsqrte.s[ ]+[ ]+\$fa0, \$fa1 ++[ ]+13c:[ ]+01148820 [ ]+frsqrte.d[ ]+[ ]+\$fa0, \$fa1 +diff --git a/gas/testsuite/gas/loongarch/float_op.s b/gas/testsuite/gas/loongarch/float_op.s +index 2e3ec5b8519..a83be3e3e48 100644 +--- a/gas/testsuite/gas/loongarch/float_op.s ++++ b/gas/testsuite/gas/loongarch/float_op.s +@@ -74,3 +74,7 @@ ffint.d.w $f0,$f1 + ffint.d.l $f0,$f1 + frint.s $f0,$f1 + frint.d $f0,$f1 ++frecipe.s $f0,$f1 ++frecipe.d $f0,$f1 ++frsqrte.s $f0,$f1 ++frsqrte.d $f0,$f1 +diff --git a/gas/testsuite/gas/loongarch/vector.d b/gas/testsuite/gas/loongarch/vector.d +index 1a092bca3b8..4526b3d3640 100644 +--- a/gas/testsuite/gas/loongarch/vector.d ++++ b/gas/testsuite/gas/loongarch/vector.d +@@ -1459,3 +1459,11 @@ Disassembly of section .text: + [ ]+16a0:[ ]+77e40420[ ]+xvpermi.w[ ]+\$xr0,[ ]+\$xr1,[ ]+0x1 + [ ]+16a4:[ ]+77e80420[ ]+xvpermi.d[ ]+\$xr0,[ ]+\$xr1,[ ]+0x1 + [ ]+16a8:[ ]+77ec0420[ ]+xvpermi.q[ ]+\$xr0,[ ]+\$xr1,[ ]+0x1 ++[ ]+16ac:[ ]+729d1420[ ]+vfrecipe.s[ ]+\$vr0,[ ]+\$vr1 ++[ ]+16b0:[ ]+729d1820[ ]+vfrecipe.d[ ]+\$vr0,[ ]+\$vr1 ++[ ]+16b4:[ ]+729d2420[ ]+vfrsqrte.s[ ]+\$vr0,[ ]+\$vr1 ++[ ]+16b8:[ ]+729d2820[ ]+vfrsqrte.d[ ]+\$vr0,[ ]+\$vr1 ++[ ]+16bc:[ ]+769d1420[ ]+xvfrecipe.s[ ]+\$xr0,[ ]+\$xr1 ++[ ]+16c0:[ ]+769d1820[ ]+xvfrecipe.d[ ]+\$xr0,[ ]+\$xr1 ++[ ]+16c4:[ ]+769d2420[ ]+xvfrsqrte.s[ ]+\$xr0,[ ]+\$xr1 ++[ ]+16c8:[ ]+769d2820[ ]+xvfrsqrte.d[ ]+\$xr0,[ ]+\$xr1 +diff --git a/gas/testsuite/gas/loongarch/vector.s b/gas/testsuite/gas/loongarch/vector.s +index fe0369e763e..0283a4b4d53 100644 +--- a/gas/testsuite/gas/loongarch/vector.s ++++ b/gas/testsuite/gas/loongarch/vector.s +@@ -1449,3 +1449,11 @@ xvldi $xr0, 1 + xvpermi.w $xr0, $xr1, 1 + xvpermi.d $xr0, $xr1, 1 + xvpermi.q $xr0, $xr1, 1 ++vfrecipe.s $vr0, $vr1 ++vfrecipe.d $vr0, $vr1 ++vfrsqrte.s $vr0, $vr1 ++vfrsqrte.d $vr0, $vr1 ++xvfrecipe.s $xr0, $xr1 ++xvfrecipe.d $xr0, $xr1 ++xvfrsqrte.s $xr0, $xr1 ++xvfrsqrte.d $xr0, $xr1 +diff --git a/opcodes/loongarch-opc.c b/opcodes/loongarch-opc.c +index e110735e857..15c7da6340c 100644 +--- a/opcodes/loongarch-opc.c ++++ b/opcodes/loongarch-opc.c +@@ -482,6 +482,8 @@ static struct loongarch_opcode loongarch_single_float_opcodes[] = + { 0x01144400, 0xfffffc00, "fsqrt.s", "f0:5,f5:5", 0, 0, 0, 0 }, + { 0x01145400, 0xfffffc00, "frecip.s", "f0:5,f5:5", 0, 0, 0, 0 }, + { 0x01146400, 0xfffffc00, "frsqrt.s", "f0:5,f5:5", 0, 0, 0, 0 }, ++ { 0x01147400, 0xfffffc00, "frecipe.s", "f0:5,f5:5", 0, 0, 0, 0 }, ++ { 0x01148400, 0xfffffc00, "frsqrte.s", "f0:5,f5:5", 0, 0, 0, 0 }, + { 0x01149400, 0xfffffc00, "fmov.s", "f0:5,f5:5", 0, 0, 0, 0 }, + { 0x0114a400, 0xfffffc00, "movgr2fr.w", "f0:5,r5:5", 0, 0, 0, 0 }, + { 0x0114ac00, 0xfffffc00, "movgr2frh.w", "f0:5,r5:5", 0, 0, 0, 0 }, +@@ -528,6 +530,8 @@ static struct loongarch_opcode loongarch_double_float_opcodes[] = + { 0x01144800, 0xfffffc00, "fsqrt.d", "f0:5,f5:5", 0, 0, 0, 0 }, + { 0x01145800, 0xfffffc00, "frecip.d", "f0:5,f5:5", 0, 0, 0, 0 }, + { 0x01146800, 0xfffffc00, "frsqrt.d", "f0:5,f5:5", 0, 0, 0, 0 }, ++ { 0x01147800, 0xfffffc00, "frecipe.d", "f0:5,f5:5", 0, 0, 0, 0 }, ++ { 0x01148800, 0xfffffc00, "frsqrte.d", "f0:5,f5:5", 0, 0, 0, 0 }, + { 0x01149800, 0xfffffc00, "fmov.d", "f0:5,f5:5", 0, 0, 0, 0 }, + { 0x0114a800, 0xfffffc00, "movgr2fr.d", "f0:5,r5:5", 0, 0, 0, 0 }, + { 0x0114b800, 0xfffffc00, "movfr2gr.d", "r0:5,f5:5", 0, 0, 0, 0 }, +@@ -1424,6 +1428,10 @@ static struct loongarch_opcode loongarch_lsx_opcodes[] = + { 0x729cf800, 0xfffffc00, "vfrecip.d", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729d0400, 0xfffffc00, "vfrsqrt.s", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729d0800, 0xfffffc00, "vfrsqrt.d", "v0:5,v5:5", 0, 0, 0, 0}, ++ { 0x729d1400, 0xfffffc00, "vfrecipe.s", "v0:5,v5:5", 0, 0, 0, 0}, ++ { 0x729d1800, 0xfffffc00, "vfrecipe.d", "v0:5,v5:5", 0, 0, 0, 0}, ++ { 0x729d2400, 0xfffffc00, "vfrsqrte.s", "v0:5,v5:5", 0, 0, 0, 0}, ++ { 0x729d2800, 0xfffffc00, "vfrsqrte.d", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729d3400, 0xfffffc00, "vfrint.s", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729d3800, 0xfffffc00, "vfrint.d", "v0:5,v5:5", 0, 0, 0, 0}, + { 0x729d4400, 0xfffffc00, "vfrintrm.s", "v0:5,v5:5", 0, 0, 0, 0}, +@@ -2169,6 +2177,10 @@ static struct loongarch_opcode loongarch_lasx_opcodes[] = + { 0x769cf800, 0xfffffc00, "xvfrecip.d", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769d0400, 0xfffffc00, "xvfrsqrt.s", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769d0800, 0xfffffc00, "xvfrsqrt.d", "x0:5,x5:5", 0, 0, 0, 0}, ++ { 0x769d1400, 0xfffffc00, "xvfrecipe.s", "x0:5,x5:5", 0, 0, 0, 0}, ++ { 0x769d1800, 0xfffffc00, "xvfrecipe.d", "x0:5,x5:5", 0, 0, 0, 0}, ++ { 0x769d2400, 0xfffffc00, "xvfrsqrte.s", "x0:5,x5:5", 0, 0, 0, 0}, ++ { 0x769d2800, 0xfffffc00, "xvfrsqrte.d", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769d3400, 0xfffffc00, "xvfrint.s", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769d3800, 0xfffffc00, "xvfrint.d", "x0:5,x5:5", 0, 0, 0, 0}, + { 0x769d4400, 0xfffffc00, "xvfrintrm.s", "x0:5,x5:5", 0, 0, 0, 0}, +-- +2.33.0 + diff --git a/binutils.spec b/binutils.spec index 65281c749bfea05096e482ac3e268bc3eff76aa5..2573d75ac0128b484e1584b4629019826d94c27c 100644 --- a/binutils.spec +++ b/binutils.spec @@ -2,7 +2,7 @@ Summary: A GNU collection of binary utilities Name: binutils%{?_with_debug:-debug} Version: 2.41 -Release: 1 +Release: 2 License: GPL-3.0-or-later AND (GPL-3.0-or-later WITH Bison-exception-2.2) AND (LGPL-2.0-or-later WITH GCC-exception-2.0) AND BSD-3-Clause AND GFDL-1.3-or-later AND GPL-2.0-or-later AND LGPL-2.1-or-later AND LGPL-2.0-or-later URL: https://sourceware.org/binutils @@ -78,7 +78,7 @@ URL: https://sourceware.org/binutils #----End of Configure Options------------------------------------------------ # Note - in the future the gold linker may become deprecated. -%ifnarch riscv64 +%ifnarch riscv64 loongarch64 %bcond_without gold %else # RISC-V does not have ld.gold thus disable by default. @@ -164,6 +164,16 @@ Source2: binutils-2.19.50.0.1-output-format.sed Patch1001: X86-Change-fpic-to-fPIC-in-PICFLAG.patch Patch1002: PPC-gas-supported-c2000.patch +# Part 3000 - 4999 +Patch3001: LoongArch-Fix-ld-no-relax-bug.patch +Patch3002: LoongArch-Directly-delete-relaxed-instuctions-in-fir.patch +Patch3003: LoongArch-Multiple-relax_trip-in-one-relax_pass.patch +Patch3004: LoongArch-Remove-elf_seg_map-info-output_bfd-NULL-re.patch +Patch3005: LoongArch-Modify-link_info.relax_pass-from-3-to-2.patch +Patch3006: LoongArch-Add-more-relaxation-testcases.patch +Patch3007: LoongArch-fix-internal-error-when-as-handling-unsupp.patch +Patch3008: as-Add-new-atomic-instructions-in-LoongArch-v1.1.patch +Patch3009: as-Add-new-estimated-reciprocal-instructions-in-Loon.patch # Part 5000 - @@ -217,7 +227,6 @@ Patch5007: binutils-update-linker-manual.patch # Lifetime: Fixed in 2.42 (maybe) Patch5008: binutils-gold-empty-dwp.patch - #---------------------------------------------------------------------------- Provides: bundled(libiberty) @@ -1256,6 +1265,9 @@ exit 0 #---------------------------------------------------------------------------- %changelog +* Wed Feb 28 2024 Peng Fan - 2.41-2 +- LoongArch: sync patch from binutils upstream + * Mon Feb 26 2024 eastb233 - 2.41-1 - Update binutils 2.41 - Reference: https://gitlab.com/redhat/centos-stream/rpms/binutils/-/tree/c10s