diff --git a/0001-x86-Add-int1-as-one-byte-opcode-0xf1.patch b/AVX512-0001-x86-Add-int1-as-one-byte-opcode-0xf1.patch similarity index 100% rename from 0001-x86-Add-int1-as-one-byte-opcode-0xf1.patch rename to AVX512-0001-x86-Add-int1-as-one-byte-opcode-0xf1.patch diff --git a/0002-x86-drop-OP_Mask.patch b/AVX512-0002-x86-drop-OP_Mask.patch similarity index 100% rename from 0002-x86-drop-OP_Mask.patch rename to AVX512-0002-x86-drop-OP_Mask.patch diff --git a/0003-x86-correct-VCVT-U-SI2SD-rounding-mode-handling.patch b/AVX512-0003-x86-correct-VCVT-U-SI2SD-rounding-mode-handling.patch similarity index 100% rename from 0003-x86-correct-VCVT-U-SI2SD-rounding-mode-handling.patch rename to AVX512-0003-x86-correct-VCVT-U-SI2SD-rounding-mode-handling.patch diff --git a/0004-x86-64-generalize-OP_G-s-EVEX.R-handling.patch b/AVX512-0004-x86-64-generalize-OP_G-s-EVEX.R-handling.patch similarity index 100% rename from 0004-x86-64-generalize-OP_G-s-EVEX.R-handling.patch rename to AVX512-0004-x86-64-generalize-OP_G-s-EVEX.R-handling.patch diff --git a/0005-x86-64-properly-bounds-check-bnd-N-in-OP_G.patch b/AVX512-0005-x86-64-properly-bounds-check-bnd-N-in-OP_G.patch similarity index 100% rename from 0005-x86-64-properly-bounds-check-bnd-N-in-OP_G.patch rename to AVX512-0005-x86-64-properly-bounds-check-bnd-N-in-OP_G.patch diff --git a/0006-x86-fold-duplicate-register-printing-code.patch b/AVX512-0006-x86-fold-duplicate-register-printing-code.patch similarity index 100% rename from 0006-x86-fold-duplicate-register-printing-code.patch rename to AVX512-0006-x86-fold-duplicate-register-printing-code.patch diff --git a/0007-x86-fold-duplicate-code-in-MOVSXD_Fixup.patch b/AVX512-0007-x86-fold-duplicate-code-in-MOVSXD_Fixup.patch similarity index 100% rename from 0007-x86-fold-duplicate-code-in-MOVSXD_Fixup.patch rename to AVX512-0007-x86-fold-duplicate-code-in-MOVSXD_Fixup.patch diff --git a/0008-x86-correct-EVEX.V-handling-outside-of-64-bit-mode.patch b/AVX512-0008-x86-correct-EVEX.V-handling-outside-of-64-bit-mode.patch similarity index 100% rename from 0008-x86-correct-EVEX.V-handling-outside-of-64-bit-mode.patch rename to AVX512-0008-x86-correct-EVEX.V-handling-outside-of-64-bit-mode.patch diff --git a/0009-x86-drop-vex_mode-and-vex_scalar_mode.patch b/AVX512-0009-x86-drop-vex_mode-and-vex_scalar_mode.patch similarity index 100% rename from 0009-x86-drop-vex_mode-and-vex_scalar_mode.patch rename to AVX512-0009-x86-drop-vex_mode-and-vex_scalar_mode.patch diff --git a/0010-x86-fold-duplicate-vector-register-printing-code.patch b/AVX512-0010-x86-fold-duplicate-vector-register-printing-code.patch similarity index 100% rename from 0010-x86-fold-duplicate-vector-register-printing-code.patch rename to AVX512-0010-x86-fold-duplicate-vector-register-printing-code.patch diff --git a/0011-x86-drop-xmm_m-b-w-d-q-_mode.patch b/AVX512-0011-x86-drop-xmm_m-b-w-d-q-_mode.patch similarity index 100% rename from 0011-x86-drop-xmm_m-b-w-d-q-_mode.patch rename to AVX512-0011-x86-drop-xmm_m-b-w-d-q-_mode.patch diff --git a/0012-x86-drop-vex_scalar_w_dq_mode.patch b/AVX512-0012-x86-drop-vex_scalar_w_dq_mode.patch similarity index 100% rename from 0012-x86-drop-vex_scalar_w_dq_mode.patch rename to AVX512-0012-x86-drop-vex_scalar_w_dq_mode.patch diff --git a/0013-x86-drop-dq-b-d-_mode.patch b/AVX512-0013-x86-drop-dq-b-d-_mode.patch similarity index 100% rename from 0013-x86-drop-dq-b-d-_mode.patch rename to AVX512-0013-x86-drop-dq-b-d-_mode.patch diff --git a/0014-x86-express-unduly-set-rounding-control-bits-in-disa.patch b/AVX512-0014-x86-express-unduly-set-rounding-control-bits-in-disa.patch similarity index 100% rename from 0014-x86-express-unduly-set-rounding-control-bits-in-disa.patch rename to AVX512-0014-x86-express-unduly-set-rounding-control-bits-in-disa.patch diff --git a/0015-x86-Simplify-check-for-distinct-TMM-register-operand.patch b/AVX512-0015-x86-Simplify-check-for-distinct-TMM-register-operand.patch similarity index 100% rename from 0015-x86-Simplify-check-for-distinct-TMM-register-operand.patch rename to AVX512-0015-x86-Simplify-check-for-distinct-TMM-register-operand.patch diff --git a/0016-PATCH-1-2-Enable-Intel-AVX512_FP16-instructions.patch b/AVX512-0016-PATCH-1-2-Enable-Intel-AVX512_FP16-instructions.patch similarity index 100% rename from 0016-PATCH-1-2-Enable-Intel-AVX512_FP16-instructions.patch rename to AVX512-0016-PATCH-1-2-Enable-Intel-AVX512_FP16-instructions.patch diff --git a/0017-PATCH-2-2-Add-tests-for-Intel-AVX512_FP16-instructio.patch b/AVX512-0017-PATCH-2-2-Add-tests-for-Intel-AVX512_FP16-instructio.patch similarity index 100% rename from 0017-PATCH-2-2-Add-tests-for-Intel-AVX512_FP16-instructio.patch rename to AVX512-0017-PATCH-2-2-Add-tests-for-Intel-AVX512_FP16-instructio.patch diff --git a/0018-x86-ELF-fix-.tfloat-output.patch b/AVX512-0018-x86-ELF-fix-.tfloat-output.patch similarity index 100% rename from 0018-x86-ELF-fix-.tfloat-output.patch rename to AVX512-0018-x86-ELF-fix-.tfloat-output.patch diff --git a/0019-x86-ELF-fix-.ds.x-output.patch b/AVX512-0019-x86-ELF-fix-.ds.x-output.patch similarity index 100% rename from 0019-x86-ELF-fix-.ds.x-output.patch rename to AVX512-0019-x86-ELF-fix-.ds.x-output.patch diff --git a/0020-x86-ELF-fix-.tfloat-output-with-hex-input.patch b/AVX512-0020-x86-ELF-fix-.tfloat-output-with-hex-input.patch similarity index 100% rename from 0020-x86-ELF-fix-.tfloat-output-with-hex-input.patch rename to AVX512-0020-x86-ELF-fix-.tfloat-output-with-hex-input.patch diff --git a/0021-x86-introduce-.hfloat-directive.patch b/AVX512-0021-x86-introduce-.hfloat-directive.patch similarity index 100% rename from 0021-x86-introduce-.hfloat-directive.patch rename to AVX512-0021-x86-introduce-.hfloat-directive.patch diff --git a/0022-x86-Avoid-abort-on-invalid-broadcast.patch b/AVX512-0022-x86-Avoid-abort-on-invalid-broadcast.patch similarity index 100% rename from 0022-x86-Avoid-abort-on-invalid-broadcast.patch rename to AVX512-0022-x86-Avoid-abort-on-invalid-broadcast.patch diff --git a/0023-x86-Put-back-3-aborts-in-OP_E_memory.patch b/AVX512-0023-x86-Put-back-3-aborts-in-OP_E_memory.patch similarity index 100% rename from 0023-x86-Put-back-3-aborts-in-OP_E_memory.patch rename to AVX512-0023-x86-Put-back-3-aborts-in-OP_E_memory.patch diff --git a/0024-x86-Print-bad-on-invalid-broadcast-in-OP_E_memory.patch b/AVX512-0024-x86-Print-bad-on-invalid-broadcast-in-OP_E_memory.patch similarity index 100% rename from 0024-x86-Print-bad-on-invalid-broadcast-in-OP_E_memory.patch rename to AVX512-0024-x86-Print-bad-on-invalid-broadcast-in-OP_E_memory.patch diff --git a/0025-x86-Terminate-mnemonicendp-in-swap_operand.patch b/AVX512-0025-x86-Terminate-mnemonicendp-in-swap_operand.patch similarity index 100% rename from 0025-x86-Terminate-mnemonicendp-in-swap_operand.patch rename to AVX512-0025-x86-Terminate-mnemonicendp-in-swap_operand.patch diff --git a/0026-opcodes-Make-i386-dis.c-thread-safe.patch b/AVX512-0026-opcodes-Make-i386-dis.c-thread-safe.patch similarity index 100% rename from 0026-opcodes-Make-i386-dis.c-thread-safe.patch rename to AVX512-0026-opcodes-Make-i386-dis.c-thread-safe.patch diff --git a/0027-x86-reduce-AVX512-FP16-set-of-insns-decoded-through-.patch b/AVX512-0027-x86-reduce-AVX512-FP16-set-of-insns-decoded-through-.patch similarity index 100% rename from 0027-x86-reduce-AVX512-FP16-set-of-insns-decoded-through-.patch rename to AVX512-0027-x86-reduce-AVX512-FP16-set-of-insns-decoded-through-.patch diff --git a/0028-x86-reduce-AVX512-FP-set-of-insns-decoded-through-ve.patch b/AVX512-0028-x86-reduce-AVX512-FP-set-of-insns-decoded-through-ve.patch similarity index 100% rename from 0028-x86-reduce-AVX512-FP-set-of-insns-decoded-through-ve.patch rename to AVX512-0028-x86-reduce-AVX512-FP-set-of-insns-decoded-through-ve.patch diff --git a/0029-x86-consistently-use-scalar_mode-for-AVX512-FP16-sca.patch b/AVX512-0029-x86-consistently-use-scalar_mode-for-AVX512-FP16-sca.patch similarity index 100% rename from 0029-x86-consistently-use-scalar_mode-for-AVX512-FP16-sca.patch rename to AVX512-0029-x86-consistently-use-scalar_mode-for-AVX512-FP16-sca.patch diff --git a/SME-0001-aarch64-SME-Add-sme-option-to-march.patch b/SME-0001-aarch64-SME-Add-sme-option-to-march.patch new file mode 100644 index 0000000000000000000000000000000000000000..e7e739bc707438c85f60589d2895be1ebc16b599 --- /dev/null +++ b/SME-0001-aarch64-SME-Add-sme-option-to-march.patch @@ -0,0 +1,139 @@ +From 90774538ff7755dcc12d997d52b76a484b8c68d2 Mon Sep 17 00:00:00 2001 +From: Przemyslaw Wirkus +Date: Wed, 17 Nov 2021 19:02:54 +0000 +Subject: [PATCH 01/10] aarch64: [SME] Add +sme option to -march + +Reference: https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=57f02370a1e55bf09d3ede5ba6b2fcc78b40200a + +This series of patches (tagged [SME]) add support for the Scalable +Matrix Extension. Patch introduces new command line options: +sme, +sme-f64 and ++sme-i64 to -march command line options. + +gas/ChangeLog: + + * NEWS: Updated docs. + * config/tc-aarch64.c: New SME command line options. + * doc/c-aarch64.texi: Update docs. + +include/ChangeLog: + + * opcode/aarch64.h (AARCH64_FEATURE_SME): New flag. + (AARCH64_FEATURE_SME_F64): New flag. + (AARCH64_FEATURE_SME_I64): New flag. + +opcodes/ChangeLog: + + * aarch64-tbl.h (SME): New feature object. +--- + gas/NEWS | 2 ++ + gas/config/tc-aarch64.c | 11 +++++++++++ + gas/doc/c-aarch64.texi | 6 ++++++ + include/opcode/aarch64.h | 3 +++ + opcodes/aarch64-tbl.h | 11 +++++++++++ + 5 files changed, 33 insertions(+) + +diff --git a/gas/NEWS b/gas/NEWS +index 9e24e4dd..0c5db3bf 100644 +--- a/gas/NEWS ++++ b/gas/NEWS +@@ -2,6 +2,8 @@ + + * Add support for Intel AVX512_FP16 instructions. + ++* Add support for Scalable Matrix Extension (SME) for AArch64. ++ + Changes in 2.37: + + * arm-symbianelf support removed. +diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c +index 2eaad63a..f750fad4 100644 +--- a/gas/config/tc-aarch64.c ++++ b/gas/config/tc-aarch64.c +@@ -9273,6 +9273,17 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = { + | AARCH64_FEATURE_SHA3, 0)}, + {"sve2-bitperm", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_BITPERM, 0), + AARCH64_FEATURE (AARCH64_FEATURE_SVE2, 0)}, ++ {"sme", AARCH64_FEATURE (AARCH64_FEATURE_SME, 0), ++ AARCH64_FEATURE (AARCH64_FEATURE_SVE2 ++ | AARCH64_FEATURE_BFLOAT16, 0)}, ++ {"sme-f64", AARCH64_FEATURE (AARCH64_FEATURE_SME_F64, 0), ++ AARCH64_FEATURE (AARCH64_FEATURE_SME ++ | AARCH64_FEATURE_SVE2 ++ | AARCH64_FEATURE_BFLOAT16, 0)}, ++ {"sme-i64", AARCH64_FEATURE (AARCH64_FEATURE_SME_I64, 0), ++ AARCH64_FEATURE (AARCH64_FEATURE_SME ++ | AARCH64_FEATURE_SVE2 ++ | AARCH64_FEATURE_BFLOAT16, 0)}, + {"bf16", AARCH64_FEATURE (AARCH64_FEATURE_BFLOAT16, 0), + AARCH64_ARCH_NONE}, + {"i8mm", AARCH64_FEATURE (AARCH64_FEATURE_I8MM, 0), +diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi +index 79dce2f7..1bd93821 100644 +--- a/gas/doc/c-aarch64.texi ++++ b/gas/doc/c-aarch64.texi +@@ -210,6 +210,12 @@ automatically cause those extensions to be disabled. + @tab Enable the Execution and Data and Prediction instructions. + @item @code{rng} @tab ARMv8.5-A @tab No + @tab Enable ARMv8.5-A random number instructions. ++@item @code{sme} @tab Armv9-A @tab No ++ @tab Enable SME Extension. ++@item @code{sme-f64} @tab Armv9-A @tab No ++ @tab Enable SME F64 Extension. ++@item @code{sme-i64} @tab Armv9-A @tab No ++ @tab Enable SME I64 Extension. + @item @code{ssbs} @tab ARMv8-A @tab ARMv8.5-A or later + @tab Enable Speculative Store Bypassing Safe state read and write. + @item @code{memtag} @tab ARMv8.5-A @tab No +diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h +index 2bbd593c..7256028d 100644 +--- a/include/opcode/aarch64.h ++++ b/include/opcode/aarch64.h +@@ -51,6 +51,7 @@ typedef uint32_t aarch64_insn; + #define AARCH64_FEATURE_V8_4 (1ULL << 11) /* ARMv8.4 processors. */ + #define AARCH64_FEATURE_V8_R (1ULL << 12) /* Armv8-R processors. */ + #define AARCH64_FEATURE_V8_7 (1ULL << 13) /* Armv8.7 processors. */ ++#define AARCH64_FEATURE_SME (1ULL << 14) /* Scalable Matrix Extension. */ + #define AARCH64_FEATURE_LS64 (1ULL << 15) /* Atomic 64-byte load/store. */ + #define AARCH64_FEATURE_PAC (1ULL << 16) /* v8.3 Pointer Authentication. */ + #define AARCH64_FEATURE_FP (1ULL << 17) /* FP instructions. */ +@@ -90,6 +91,8 @@ typedef uint32_t aarch64_insn; + #define AARCH64_FEATURE_F32MM (1ULL << 53) + #define AARCH64_FEATURE_F64MM (1ULL << 54) + #define AARCH64_FEATURE_FLAGM (1ULL << 55) /* v8.4 Flag Manipulation. */ ++#define AARCH64_FEATURE_SME_F64 (1ULL << 57) /* SME F64. */ ++#define AARCH64_FEATURE_SME_I64 (1ULL << 58) /* SME I64. */ + + /* Crypto instructions are the combination of AES and SHA2. */ + #define AARCH64_FEATURE_CRYPTO (AARCH64_FEATURE_SHA2 | AARCH64_FEATURE_AES) +diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h +index 17ea851c..d63b0810 100644 +--- a/opcodes/aarch64-tbl.h ++++ b/opcodes/aarch64-tbl.h +@@ -2401,6 +2401,14 @@ static const aarch64_feature_set aarch64_feature_sve2sm4 = + AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SVE2_SM4, 0); + static const aarch64_feature_set aarch64_feature_sve2bitperm = + AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SVE2_BITPERM, 0); ++static const aarch64_feature_set aarch64_feature_sme = ++ AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SME, 0); ++static const aarch64_feature_set aarch64_feature_sme_f64 = ++ AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SME ++ | AARCH64_FEATURE_SME_F64, 0); ++static const aarch64_feature_set aarch64_feature_sme_i64 = ++ AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SME ++ | AARCH64_FEATURE_SME_I64, 0); + static const aarch64_feature_set aarch64_feature_v8_6 = + AARCH64_FEATURE (AARCH64_FEATURE_V8_6, 0); + static const aarch64_feature_set aarch64_feature_v8_7 = +@@ -2458,6 +2466,9 @@ static const aarch64_feature_set aarch64_feature_flagm = + #define SVE2_SHA3 &aarch64_feature_sve2sha3 + #define SVE2_SM4 &aarch64_feature_sve2sm4 + #define SVE2_BITPERM &aarch64_feature_sve2bitperm ++#define SME &aarch64_feature_sme ++#define SME_F64 &aarch64_feature_sme_f64 ++#define SME_I64 &aarch64_feature_sme_i64 + #define ARMV8_6 &aarch64_feature_v8_6 + #define ARMV8_6_SVE &aarch64_feature_v8_6 + #define BFLOAT16_SVE &aarch64_feature_bfloat16_sve +-- +2.19.1 + diff --git a/SME-0002-aarch64-SME-Add-SME-instructions.patch b/SME-0002-aarch64-SME-Add-SME-instructions.patch new file mode 100644 index 0000000000000000000000000000000000000000..aa7f0c5ee16b048a8a7019fced04f3fcd5666c09 --- /dev/null +++ b/SME-0002-aarch64-SME-Add-SME-instructions.patch @@ -0,0 +1,2621 @@ +From 5ef91b9979d101657b69305e7b758c6f2d2029c4 Mon Sep 17 00:00:00 2001 +From: Przemyslaw Wirkus +Date: Wed, 17 Nov 2021 19:21:33 +0000 +Subject: [PATCH 02/10] aarch64: [SME] Add SME instructions + +Reference: https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=971eda734150ea9cdea47be259486c3a8d087037 + +Patch is adding new SME matrix instructions. Please note additional +instructions will be added in following patches. + +gas/ChangeLog: + + * config/tc-aarch64.c (parse_sme_zada_operand): + New parser. + * config/tc-aarch64.c (parse_reg_with_qual): + New reg parser. + * config/tc-aarch64.c (R_ZA): New egister type. + (parse_operands): New parser. + * testsuite/gas/aarch64/sme-illegal.d: New test. + * testsuite/gas/aarch64/sme-illegal.l: New test. + * testsuite/gas/aarch64/sme-illegal.s: New test. + * testsuite/gas/aarch64/sme.d: New test. + * testsuite/gas/aarch64/sme.s: New test. + * testsuite/gas/aarch64/sme-f64.d: New test. + * testsuite/gas/aarch64/sme-f64.s: New test. + * testsuite/gas/aarch64/sme-i64.d: New test. + * testsuite/gas/aarch64/sme-i64.s: New test. + +include/ChangeLog: + + * opcode/aarch64.h (enum aarch64_opnd): New operands + AARCH64_OPND_SME_ZAda_2b, AARCH64_OPND_SME_ZAda_3b and + AARCH64_OPND_SME_Pm. + (enum aarch64_insn_class): New instruction class sme_misc. + +opcodes/ChangeLog: + + * aarch64-opc.c (aarch64_print_operand): + Print OPND_SME_ZAda_2b and OPND_SME_ZAda_3b operands. + (verify_constraints): Handle OPND_SME_Pm. + * aarch64-opc.h (enum aarch64_field_kind): + New bit fields FLD_SME_ZAda_2b, FLD_SME_ZAda_3b and FLD_SME_Pm. + * aarch64-tbl.h (OP_SME_ZADA_PN_PM_ZN_S): New qualifier set. + (OP_SME_ZADA_PN_PM_ZN_D): New qualifier. + (OP_SME_ZADA_PN_PM_ZN_ZM): New qualifier. + (OP_SME_ZADA_S_PM_PM_S_S): New qualifier. + (OP_SME_ZADA_D_PM_PM_D_D): New qualifier. + (OP_SME_ZADA_S_PM_PM_H_H): New qualifier. + (OP_SME_ZADA_S_PM_PM_B_B): New qualifier. + (OP_SME_ZADA_D_PM_PM_H_H): New qualifier. + (SME_INSN): New instruction macro. + (SME_F64_INSN): New instruction macro. + (SME_I64_INSN): New instruction macro. + (SME_INSNC): New instruction macro. + (struct aarch64_opcode): New SME instructions. + aarch64-asm-2.c: Regenerate. + aarch64-dis-2.c: Regenerate. + aarch64-opc-2.c: Regenerate. +--- + gas/config/tc-aarch64.c | 127 +++++- + gas/testsuite/gas/aarch64/sme-f64.d | 31 ++ + gas/testsuite/gas/aarch64/sme-f64.s | 32 ++ + gas/testsuite/gas/aarch64/sme-i64.d | 117 +++++ + gas/testsuite/gas/aarch64/sme-i64.s | 135 ++++++ + gas/testsuite/gas/aarch64/sme-illegal.d | 3 + + gas/testsuite/gas/aarch64/sme-illegal.l | 95 ++++ + gas/testsuite/gas/aarch64/sme-illegal.s | 117 +++++ + gas/testsuite/gas/aarch64/sme.d | 93 ++++ + gas/testsuite/gas/aarch64/sme.s | 123 +++++ + include/opcode/aarch64.h | 4 + + opcodes/aarch64-asm-2.c | 7 +- + opcodes/aarch64-dis-2.c | 573 ++++++++++++++++++------ + opcodes/aarch64-opc-2.c | 3 + + opcodes/aarch64-opc.c | 11 + + opcodes/aarch64-opc.h | 3 + + opcodes/aarch64-tbl.h | 83 ++++ + 17 files changed, 1423 insertions(+), 134 deletions(-) + create mode 100644 gas/testsuite/gas/aarch64/sme-f64.d + create mode 100644 gas/testsuite/gas/aarch64/sme-f64.s + create mode 100644 gas/testsuite/gas/aarch64/sme-i64.d + create mode 100644 gas/testsuite/gas/aarch64/sme-i64.s + create mode 100644 gas/testsuite/gas/aarch64/sme-illegal.d + create mode 100644 gas/testsuite/gas/aarch64/sme-illegal.l + create mode 100644 gas/testsuite/gas/aarch64/sme-illegal.s + create mode 100644 gas/testsuite/gas/aarch64/sme.d + create mode 100644 gas/testsuite/gas/aarch64/sme.s + +diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c +index f750fad4..912dac67 100644 +--- a/gas/config/tc-aarch64.c ++++ b/gas/config/tc-aarch64.c +@@ -278,6 +278,7 @@ struct reloc_entry + BASIC_REG_TYPE(VN) /* v[0-31] */ \ + BASIC_REG_TYPE(ZN) /* z[0-31] */ \ + BASIC_REG_TYPE(PN) /* p[0-15] */ \ ++ BASIC_REG_TYPE(ZA) /* za[0-15] */ \ + /* Typecheck: any 64-bit int reg (inc SP exc XZR). */ \ + MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \ + /* Typecheck: same, plus SVE registers. */ \ +@@ -4212,6 +4213,117 @@ parse_bti_operand (char **str, + return 0; + } + ++/* Parse STR for reg of REG_TYPE and following '.' and QUALIFIER. ++ Function returns REG_ENTRY struct and QUALIFIER [bhsdq] or NULL ++ on failure. Format: ++ ++ REG_TYPE.QUALIFIER ++ ++ Side effect: Update STR with current parse position of success. ++*/ ++ ++static const reg_entry * ++parse_reg_with_qual (char **str, aarch64_reg_type reg_type, ++ aarch64_opnd_qualifier_t *qualifier) ++{ ++ char *q; ++ ++ reg_entry *reg = parse_reg (str); ++ if (reg != NULL && reg->type == reg_type) ++ { ++ if (!skip_past_char (str, '.')) ++ { ++ set_syntax_error (_("missing ZA tile element size separator")); ++ return NULL; ++ } ++ ++ q = *str; ++ switch (TOLOWER (*q)) ++ { ++ case 'b': ++ *qualifier = AARCH64_OPND_QLF_S_B; ++ break; ++ case 'h': ++ *qualifier = AARCH64_OPND_QLF_S_H; ++ break; ++ case 's': ++ *qualifier = AARCH64_OPND_QLF_S_S; ++ break; ++ case 'd': ++ *qualifier = AARCH64_OPND_QLF_S_D; ++ break; ++ case 'q': ++ *qualifier = AARCH64_OPND_QLF_S_Q; ++ break; ++ default: ++ return NULL; ++ } ++ q++; ++ ++ *str = q; ++ return reg; ++ } ++ ++ return NULL; ++} ++ ++/* Parse SME ZA tile encoded in assembler symbol. ++ Function return tile QUALIFIER on success. ++ ++ Tiles are in example format: za[0-9]\.[bhsd] ++ ++ Function returns register number or PARSE_FAIL. ++*/ ++static int ++parse_sme_zada_operand (char **str, aarch64_opnd_qualifier_t *qualifier) ++{ ++ int regno; ++ const reg_entry *reg = parse_reg_with_qual (str, REG_TYPE_ZA, qualifier); ++ ++ if (reg == NULL) ++ return PARSE_FAIL; ++ regno = reg->number; ++ ++ switch (*qualifier) ++ { ++ case AARCH64_OPND_QLF_S_B: ++ if (regno != 0x00) ++ { ++ set_syntax_error (_("invalid ZA tile register number, expected za0")); ++ return PARSE_FAIL; ++ } ++ break; ++ case AARCH64_OPND_QLF_S_H: ++ if (regno > 0x01) ++ { ++ set_syntax_error (_("invalid ZA tile register number, expected za0-za1")); ++ return PARSE_FAIL; ++ } ++ break; ++ case AARCH64_OPND_QLF_S_S: ++ if (regno > 0x03) ++ { ++ /* For the 32-bit variant: is the name of the ZA tile ZA0-ZA3. */ ++ set_syntax_error (_("invalid ZA tile register number, expected za0-za3")); ++ return PARSE_FAIL; ++ } ++ break; ++ case AARCH64_OPND_QLF_S_D: ++ if (regno > 0x07) ++ { ++ /* For the 64-bit variant: is the name of the ZA tile ZA0-ZA7 */ ++ set_syntax_error (_("invalid ZA tile register number, expected za0-za7")); ++ return PARSE_FAIL; ++ } ++ break; ++ default: ++ set_syntax_error (_("invalid ZA tile element size, allowed b, h, s and d")); ++ return PARSE_FAIL; ++ } ++ ++ return regno; ++} ++ + /* Parse a system register or a PSTATE field name for an MSR/MRS instruction. + Returns the encoding for the option, or PARSE_FAIL. + +@@ -5849,6 +5961,7 @@ parse_operands (char *str, const aarch64_opcode *opcode) + case AARCH64_OPND_SVE_Pm: + case AARCH64_OPND_SVE_Pn: + case AARCH64_OPND_SVE_Pt: ++ case AARCH64_OPND_SME_Pm: + reg_type = REG_TYPE_PN; + goto vector_reg; + +@@ -6915,6 +7028,15 @@ parse_operands (char *str, const aarch64_opcode *opcode) + goto failure; + break; + ++ case AARCH64_OPND_SME_ZAda_2b: ++ case AARCH64_OPND_SME_ZAda_3b: ++ val = parse_sme_zada_operand (&str, &qualifier); ++ if (val == PARSE_FAIL) ++ goto failure; ++ info->reg.regno = val; ++ info->qualifier = qualifier; ++ break; ++ + default: + as_fatal (_("unhandled operand code %d"), operands[i]); + } +@@ -7511,7 +7633,10 @@ static const reg_entry reg_names[] = { + REGSET (z, ZN), REGSET (Z, ZN), + + /* SVE predicate registers. */ +- REGSET16 (p, PN), REGSET16 (P, PN) ++ REGSET16 (p, PN), REGSET16 (P, PN), ++ ++ /* SME ZA tile registers. */ ++ REGSET16 (za, ZA), REGSET16 (ZA, ZA) + }; + + #undef REGDEF +diff --git a/gas/testsuite/gas/aarch64/sme-f64.d b/gas/testsuite/gas/aarch64/sme-f64.d +new file mode 100644 +index 00000000..7fdd19fd +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/sme-f64.d +@@ -0,0 +1,31 @@ ++#name: SME F64 extension ++#as: -march=armv8-a+sme-f64 ++#objdump: -dr ++ ++.*: file format .* ++ ++Disassembly of section \.text: ++ ++0+ <.*>: ++ 0: 80c82020 fmopa za0.d, p0/m, p1/m, z1.d, z8.d ++ 4: 80c76841 fmopa za1.d, p2/m, p3/m, z2.d, z7.d ++ 8: 80c6b062 fmopa za2.d, p4/m, p5/m, z3.d, z6.d ++ c: 80c5f883 fmopa za3.d, p6/m, p7/m, z4.d, z5.d ++ 10: 80c404a4 fmopa za4.d, p1/m, p0/m, z5.d, z4.d ++ 14: 80c34cc5 fmopa za5.d, p3/m, p2/m, z6.d, z3.d ++ 18: 80c294e6 fmopa za6.d, p5/m, p4/m, z7.d, z2.d ++ 1c: 80c1dd07 fmopa za7.d, p7/m, p6/m, z8.d, z1.d ++ 20: 80c41ca4 fmopa za4.d, p7/m, p0/m, z5.d, z4.d ++ 24: 80c338c5 fmopa za5.d, p6/m, p1/m, z6.d, z3.d ++ 28: 80c254e6 fmopa za6.d, p5/m, p2/m, z7.d, z2.d ++ 2c: 80c17107 fmopa za7.d, p4/m, p3/m, z8.d, z1.d ++ 30: 80c82030 fmops za0.d, p0/m, p1/m, z1.d, z8.d ++ 34: 80c76851 fmops za1.d, p2/m, p3/m, z2.d, z7.d ++ 38: 80c6b072 fmops za2.d, p4/m, p5/m, z3.d, z6.d ++ 3c: 80c5f893 fmops za3.d, p6/m, p7/m, z4.d, z5.d ++ 40: 80c404b4 fmops za4.d, p1/m, p0/m, z5.d, z4.d ++ 44: 80c34cd5 fmops za5.d, p3/m, p2/m, z6.d, z3.d ++ 48: 80c294f6 fmops za6.d, p5/m, p4/m, z7.d, z2.d ++ 4c: 80c1dd17 fmops za7.d, p7/m, p6/m, z8.d, z1.d ++ 50: 81a1f803 fmopa za3.s, p6/m, p7/m, z0.h, z1.h ++ 54: 8081f813 fmops za3.s, p6/m, p7/m, z0.s, z1.s +diff --git a/gas/testsuite/gas/aarch64/sme-f64.s b/gas/testsuite/gas/aarch64/sme-f64.s +new file mode 100644 +index 00000000..03a136b1 +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/sme-f64.s +@@ -0,0 +1,32 @@ ++/* Scalable Matrix Extension (SME F64). */ ++ ++/* FMOPA (non-widening), double-precision. */ ++fmopa za0.d, p0/m, p1/m, z1.d, z8.d ++fmopa za1.d, p2/m, p3/m, z2.d, z7.d ++fmopa za2.d, p4/m, p5/m, z3.d, z6.d ++fmopa za3.d, p6/m, p7/m, z4.d, z5.d ++fmopa za4.d, p1/m, p0/m, z5.d, z4.d ++fmopa za5.d, p3/m, p2/m, z6.d, z3.d ++fmopa za6.d, p5/m, p4/m, z7.d, z2.d ++fmopa za7.d, p7/m, p6/m, z8.d, z1.d ++fmopa za4.d, p7/m, p0/m, z5.d, z4.d ++fmopa za5.d, p6/m, p1/m, z6.d, z3.d ++fmopa za6.d, p5/m, p2/m, z7.d, z2.d ++fmopa za7.d, p4/m, p3/m, z8.d, z1.d ++ ++/* FMOPS (non-widening), double-precision. */ ++fmops za0.d, p0/m, p1/m, z1.d, z8.d ++fmops za1.d, p2/m, p3/m, z2.d, z7.d ++fmops za2.d, p4/m, p5/m, z3.d, z6.d ++fmops za3.d, p6/m, p7/m, z4.d, z5.d ++fmops za4.d, p1/m, p0/m, z5.d, z4.d ++fmops za5.d, p3/m, p2/m, z6.d, z3.d ++fmops za6.d, p5/m, p4/m, z7.d, z2.d ++fmops za7.d, p7/m, p6/m, z8.d, z1.d ++ ++/* Register aliases. */ ++foo .req za3 ++bar .req z0 ++ ++fmopa foo.s, p6/m, p7/m, bar.h, z1.h ++fmops foo.s, p6/m, p7/m, bar.s, z1.s +diff --git a/gas/testsuite/gas/aarch64/sme-i64.d b/gas/testsuite/gas/aarch64/sme-i64.d +new file mode 100644 +index 00000000..ee5880e5 +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/sme-i64.d +@@ -0,0 +1,117 @@ ++#name: SME I64 extension ++#as: -march=armv8-a+sme-i64 ++#objdump: -dr ++ ++.*: file format .* ++ ++Disassembly of section \.text: ++ ++0+ <.*>: ++ 0: c0d02020 addha za0.d, p0/m, p1/m, z1.d ++ 4: c0d06841 addha za1.d, p2/m, p3/m, z2.d ++ 8: c0d0b062 addha za2.d, p4/m, p5/m, z3.d ++ c: c0d0f883 addha za3.d, p6/m, p7/m, z4.d ++ 10: c0d004a4 addha za4.d, p1/m, p0/m, z5.d ++ 14: c0d04cc5 addha za5.d, p3/m, p2/m, z6.d ++ 18: c0d094e6 addha za6.d, p5/m, p4/m, z7.d ++ 1c: c0d0dd07 addha za7.d, p7/m, p6/m, z8.d ++ 20: c0d01ca4 addha za4.d, p7/m, p0/m, z5.d ++ 24: c0d038c5 addha za5.d, p6/m, p1/m, z6.d ++ 28: c0d054e6 addha za6.d, p5/m, p2/m, z7.d ++ 2c: c0d07107 addha za7.d, p4/m, p3/m, z8.d ++ 30: c0d12020 addva za0.d, p0/m, p1/m, z1.d ++ 34: c0d16841 addva za1.d, p2/m, p3/m, z2.d ++ 38: c0d1b062 addva za2.d, p4/m, p5/m, z3.d ++ 3c: c0d1f883 addva za3.d, p6/m, p7/m, z4.d ++ 40: c0d104a4 addva za4.d, p1/m, p0/m, z5.d ++ 44: c0d14cc5 addva za5.d, p3/m, p2/m, z6.d ++ 48: c0d194e6 addva za6.d, p5/m, p4/m, z7.d ++ 4c: c0d1dd07 addva za7.d, p7/m, p6/m, z8.d ++ 50: c0d11ca4 addva za4.d, p7/m, p0/m, z5.d ++ 54: c0d138c5 addva za5.d, p6/m, p1/m, z6.d ++ 58: c0d154e6 addva za6.d, p5/m, p2/m, z7.d ++ 5c: c0d17107 addva za7.d, p4/m, p3/m, z8.d ++ 60: a0c82020 smopa za0.d, p0/m, p1/m, z1.h, z8.h ++ 64: a0c76841 smopa za1.d, p2/m, p3/m, z2.h, z7.h ++ 68: a0c6b062 smopa za2.d, p4/m, p5/m, z3.h, z6.h ++ 6c: a0c5f883 smopa za3.d, p6/m, p7/m, z4.h, z5.h ++ 70: a0c404a4 smopa za4.d, p1/m, p0/m, z5.h, z4.h ++ 74: a0c34cc5 smopa za5.d, p3/m, p2/m, z6.h, z3.h ++ 78: a0c294e6 smopa za6.d, p5/m, p4/m, z7.h, z2.h ++ 7c: a0c1dd07 smopa za7.d, p7/m, p6/m, z8.h, z1.h ++ 80: a0c82030 smops za0.d, p0/m, p1/m, z1.h, z8.h ++ 84: a0c76851 smops za1.d, p2/m, p3/m, z2.h, z7.h ++ 88: a0c6b072 smops za2.d, p4/m, p5/m, z3.h, z6.h ++ 8c: a0c5f893 smops za3.d, p6/m, p7/m, z4.h, z5.h ++ 90: a0c404b4 smops za4.d, p1/m, p0/m, z5.h, z4.h ++ 94: a0c34cd5 smops za5.d, p3/m, p2/m, z6.h, z3.h ++ 98: a0c294f6 smops za6.d, p5/m, p4/m, z7.h, z2.h ++ 9c: a0c1dd17 smops za7.d, p7/m, p6/m, z8.h, z1.h ++ a0: a0c41cb4 smops za4.d, p7/m, p0/m, z5.h, z4.h ++ a4: a0c338d5 smops za5.d, p6/m, p1/m, z6.h, z3.h ++ a8: a0c254f6 smops za6.d, p5/m, p2/m, z7.h, z2.h ++ ac: a0c17117 smops za7.d, p4/m, p3/m, z8.h, z1.h ++ b0: a0e82020 sumopa za0.d, p0/m, p1/m, z1.h, z8.h ++ b4: a0e76841 sumopa za1.d, p2/m, p3/m, z2.h, z7.h ++ b8: a0e6b062 sumopa za2.d, p4/m, p5/m, z3.h, z6.h ++ bc: a0e5f883 sumopa za3.d, p6/m, p7/m, z4.h, z5.h ++ c0: a0e404a4 sumopa za4.d, p1/m, p0/m, z5.h, z4.h ++ c4: a0e34cc5 sumopa za5.d, p3/m, p2/m, z6.h, z3.h ++ c8: a0e294e6 sumopa za6.d, p5/m, p4/m, z7.h, z2.h ++ cc: a0e1dd07 sumopa za7.d, p7/m, p6/m, z8.h, z1.h ++ d0: a0e82030 sumops za0.d, p0/m, p1/m, z1.h, z8.h ++ d4: a0e76851 sumops za1.d, p2/m, p3/m, z2.h, z7.h ++ d8: a0e6b072 sumops za2.d, p4/m, p5/m, z3.h, z6.h ++ dc: a0e5f893 sumops za3.d, p6/m, p7/m, z4.h, z5.h ++ e0: a0e404b4 sumops za4.d, p1/m, p0/m, z5.h, z4.h ++ e4: a0e34cd5 sumops za5.d, p3/m, p2/m, z6.h, z3.h ++ e8: a0e294f6 sumops za6.d, p5/m, p4/m, z7.h, z2.h ++ ec: a0e1dd17 sumops za7.d, p7/m, p6/m, z8.h, z1.h ++ f0: a1e82020 umopa za0.d, p0/m, p1/m, z1.h, z8.h ++ f4: a1e76841 umopa za1.d, p2/m, p3/m, z2.h, z7.h ++ f8: a1e6b062 umopa za2.d, p4/m, p5/m, z3.h, z6.h ++ fc: a1e5f883 umopa za3.d, p6/m, p7/m, z4.h, z5.h ++ 100: a1e404a4 umopa za4.d, p1/m, p0/m, z5.h, z4.h ++ 104: a1e34cc5 umopa za5.d, p3/m, p2/m, z6.h, z3.h ++ 108: a1e294e6 umopa za6.d, p5/m, p4/m, z7.h, z2.h ++ 10c: a1e1dd07 umopa za7.d, p7/m, p6/m, z8.h, z1.h ++ 110: a1e82030 umops za0.d, p0/m, p1/m, z1.h, z8.h ++ 114: a1e76851 umops za1.d, p2/m, p3/m, z2.h, z7.h ++ 118: a1e6b072 umops za2.d, p4/m, p5/m, z3.h, z6.h ++ 11c: a1e5f893 umops za3.d, p6/m, p7/m, z4.h, z5.h ++ 120: a1e404b4 umops za4.d, p1/m, p0/m, z5.h, z4.h ++ 124: a1e34cd5 umops za5.d, p3/m, p2/m, z6.h, z3.h ++ 128: a1e294f6 umops za6.d, p5/m, p4/m, z7.h, z2.h ++ 12c: a1e1dd17 umops za7.d, p7/m, p6/m, z8.h, z1.h ++ 130: a1c82020 usmopa za0.d, p0/m, p1/m, z1.h, z8.h ++ 134: a1c76841 usmopa za1.d, p2/m, p3/m, z2.h, z7.h ++ 138: a1c6b062 usmopa za2.d, p4/m, p5/m, z3.h, z6.h ++ 13c: a1c5f883 usmopa za3.d, p6/m, p7/m, z4.h, z5.h ++ 140: a1c404a4 usmopa za4.d, p1/m, p0/m, z5.h, z4.h ++ 144: a1c34cc5 usmopa za5.d, p3/m, p2/m, z6.h, z3.h ++ 148: a1c294e6 usmopa za6.d, p5/m, p4/m, z7.h, z2.h ++ 14c: a1c1dd07 usmopa za7.d, p7/m, p6/m, z8.h, z1.h ++ 150: a1c82030 usmops za0.d, p0/m, p1/m, z1.h, z8.h ++ 154: a1c76851 usmops za1.d, p2/m, p3/m, z2.h, z7.h ++ 158: a1c6b072 usmops za2.d, p4/m, p5/m, z3.h, z6.h ++ 15c: a1c5f893 usmops za3.d, p6/m, p7/m, z4.h, z5.h ++ 160: a1c404b4 usmops za4.d, p1/m, p0/m, z5.h, z4.h ++ 164: a1c34cd5 usmops za5.d, p3/m, p2/m, z6.h, z3.h ++ 168: a1c294f6 usmops za6.d, p5/m, p4/m, z7.h, z2.h ++ 16c: a1c1dd17 usmops za7.d, p7/m, p6/m, z8.h, z1.h ++ 170: a1c41cb4 usmops za4.d, p7/m, p0/m, z5.h, z4.h ++ 174: a1c338d5 usmops za5.d, p6/m, p1/m, z6.h, z3.h ++ 178: a1c254f6 usmops za6.d, p5/m, p2/m, z7.h, z2.h ++ 17c: a1c17117 usmops za7.d, p4/m, p3/m, z8.h, z1.h ++ 180: c0d02020 addha za0.d, p0/m, p1/m, z1.d ++ 184: c0d17107 addva za7.d, p4/m, p3/m, z8.d ++ 188: 8181f883 bfmopa za3.s, p6/m, p7/m, z4.h, z1.h ++ 18c: 8181f893 bfmops za3.s, p6/m, p7/m, z4.h, z1.h ++ 190: a0c1dd07 smopa za7.d, p7/m, p6/m, z8.h, z1.h ++ 194: a0c17117 smops za7.d, p4/m, p3/m, z8.h, z1.h ++ 198: a0e1dd07 sumopa za7.d, p7/m, p6/m, z8.h, z1.h ++ 19c: a0e1dd17 sumops za7.d, p7/m, p6/m, z8.h, z1.h ++ 1a0: a1a1f883 umopa za3.s, p6/m, p7/m, z4.b, z1.b ++ 1a4: a1a1f893 umops za3.s, p6/m, p7/m, z4.b, z1.b ++ 1a8: a1817083 usmopa za3.s, p4/m, p3/m, z4.b, z1.b ++ 1ac: a181f893 usmops za3.s, p6/m, p7/m, z4.b, z1.b +diff --git a/gas/testsuite/gas/aarch64/sme-i64.s b/gas/testsuite/gas/aarch64/sme-i64.s +new file mode 100644 +index 00000000..1f8ba84e +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/sme-i64.s +@@ -0,0 +1,135 @@ ++/* Scalable Matrix Extension (SME I64). */ ++ ++/* ADDHA 64-bit variant. */ ++addha za0.d, p0/m, p1/m, z1.d ++addha za1.d, p2/m, p3/m, z2.d ++addha za2.d, p4/m, p5/m, z3.d ++addha za3.d, p6/m, p7/m, z4.d ++addha za4.d, p1/m, p0/m, z5.d ++addha za5.d, p3/m, p2/m, z6.d ++addha za6.d, p5/m, p4/m, z7.d ++addha za7.d, p7/m, p6/m, z8.d ++addha za4.d, p7/m, p0/m, z5.d ++addha za5.d, p6/m, p1/m, z6.d ++addha za6.d, p5/m, p2/m, z7.d ++addha za7.d, p4/m, p3/m, z8.d ++ ++/* ADDVA 64-bit variant. */ ++addva za0.d, p0/m, p1/m, z1.d ++addva za1.d, p2/m, p3/m, z2.d ++addva za2.d, p4/m, p5/m, z3.d ++addva za3.d, p6/m, p7/m, z4.d ++addva za4.d, p1/m, p0/m, z5.d ++addva za5.d, p3/m, p2/m, z6.d ++addva za6.d, p5/m, p4/m, z7.d ++addva za7.d, p7/m, p6/m, z8.d ++addva za4.d, p7/m, p0/m, z5.d ++addva za5.d, p6/m, p1/m, z6.d ++addva za6.d, p5/m, p2/m, z7.d ++addva za7.d, p4/m, p3/m, z8.d ++ ++/* SMOPA 64-bit variant. */ ++smopa za0.d, p0/m, p1/m, z1.h, z8.h ++smopa za1.d, p2/m, p3/m, z2.h, z7.h ++smopa za2.d, p4/m, p5/m, z3.h, z6.h ++smopa za3.d, p6/m, p7/m, z4.h, z5.h ++smopa za4.d, p1/m, p0/m, z5.h, z4.h ++smopa za5.d, p3/m, p2/m, z6.h, z3.h ++smopa za6.d, p5/m, p4/m, z7.h, z2.h ++smopa za7.d, p7/m, p6/m, z8.h, z1.h ++ ++/* SMOPS 64-bit variant. */ ++smops za0.d, p0/m, p1/m, z1.h, z8.h ++smops za1.d, p2/m, p3/m, z2.h, z7.h ++smops za2.d, p4/m, p5/m, z3.h, z6.h ++smops za3.d, p6/m, p7/m, z4.h, z5.h ++smops za4.d, p1/m, p0/m, z5.h, z4.h ++smops za5.d, p3/m, p2/m, z6.h, z3.h ++smops za6.d, p5/m, p4/m, z7.h, z2.h ++smops za7.d, p7/m, p6/m, z8.h, z1.h ++smops za4.d, p7/m, p0/m, z5.h, z4.h ++smops za5.d, p6/m, p1/m, z6.h, z3.h ++smops za6.d, p5/m, p2/m, z7.h, z2.h ++smops za7.d, p4/m, p3/m, z8.h, z1.h ++ ++/* SUMOPA 64-bit variant. */ ++sumopa za0.d, p0/m, p1/m, z1.h, z8.h ++sumopa za1.d, p2/m, p3/m, z2.h, z7.h ++sumopa za2.d, p4/m, p5/m, z3.h, z6.h ++sumopa za3.d, p6/m, p7/m, z4.h, z5.h ++sumopa za4.d, p1/m, p0/m, z5.h, z4.h ++sumopa za5.d, p3/m, p2/m, z6.h, z3.h ++sumopa za6.d, p5/m, p4/m, z7.h, z2.h ++sumopa za7.d, p7/m, p6/m, z8.h, z1.h ++ ++/* SUMOPS 64-bit variant. */ ++sumops za0.d, p0/m, p1/m, z1.h, z8.h ++sumops za1.d, p2/m, p3/m, z2.h, z7.h ++sumops za2.d, p4/m, p5/m, z3.h, z6.h ++sumops za3.d, p6/m, p7/m, z4.h, z5.h ++sumops za4.d, p1/m, p0/m, z5.h, z4.h ++sumops za5.d, p3/m, p2/m, z6.h, z3.h ++sumops za6.d, p5/m, p4/m, z7.h, z2.h ++sumops za7.d, p7/m, p6/m, z8.h, z1.h ++ ++/* UMOPA 64-bit variant. */ ++umopa za0.d, p0/m, p1/m, z1.h, z8.h ++umopa za1.d, p2/m, p3/m, z2.h, z7.h ++umopa za2.d, p4/m, p5/m, z3.h, z6.h ++umopa za3.d, p6/m, p7/m, z4.h, z5.h ++umopa za4.d, p1/m, p0/m, z5.h, z4.h ++umopa za5.d, p3/m, p2/m, z6.h, z3.h ++umopa za6.d, p5/m, p4/m, z7.h, z2.h ++umopa za7.d, p7/m, p6/m, z8.h, z1.h ++ ++/* UMOPS 64-bit variant. */ ++umops za0.d, p0/m, p1/m, z1.h, z8.h ++umops za1.d, p2/m, p3/m, z2.h, z7.h ++umops za2.d, p4/m, p5/m, z3.h, z6.h ++umops za3.d, p6/m, p7/m, z4.h, z5.h ++umops za4.d, p1/m, p0/m, z5.h, z4.h ++umops za5.d, p3/m, p2/m, z6.h, z3.h ++umops za6.d, p5/m, p4/m, z7.h, z2.h ++umops za7.d, p7/m, p6/m, z8.h, z1.h ++ ++/* USMOPA 64-bit variant. */ ++usmopa za0.d, p0/m, p1/m, z1.h, z8.h ++usmopa za1.d, p2/m, p3/m, z2.h, z7.h ++usmopa za2.d, p4/m, p5/m, z3.h, z6.h ++usmopa za3.d, p6/m, p7/m, z4.h, z5.h ++usmopa za4.d, p1/m, p0/m, z5.h, z4.h ++usmopa za5.d, p3/m, p2/m, z6.h, z3.h ++usmopa za6.d, p5/m, p4/m, z7.h, z2.h ++usmopa za7.d, p7/m, p6/m, z8.h, z1.h ++ ++/* USMOPS 64-bit variant. */ ++usmops za0.d, p0/m, p1/m, z1.h, z8.h ++usmops za1.d, p2/m, p3/m, z2.h, z7.h ++usmops za2.d, p4/m, p5/m, z3.h, z6.h ++usmops za3.d, p6/m, p7/m, z4.h, z5.h ++usmops za4.d, p1/m, p0/m, z5.h, z4.h ++usmops za5.d, p3/m, p2/m, z6.h, z3.h ++usmops za6.d, p5/m, p4/m, z7.h, z2.h ++usmops za7.d, p7/m, p6/m, z8.h, z1.h ++usmops za4.d, p7/m, p0/m, z5.h, z4.h ++usmops za5.d, p6/m, p1/m, z6.h, z3.h ++usmops za6.d, p5/m, p2/m, z7.h, z2.h ++usmops za7.d, p4/m, p3/m, z8.h, z1.h ++ ++/* Register aliases. */ ++foo .req za3 ++bar .req za7 ++baz .req za0 ++ ++addha baz.d, p0/m, p1/m, z1.d ++addva bar.d, p4/m, p3/m, z8.d ++bfmopa foo.s, p6/m, p7/m, z4.h, z1.h ++bfmops foo.s, p6/m, p7/m, z4.h, z1.h ++smopa bar.d, p7/m, p6/m, z8.h, z1.h ++smops bar.d, p4/m, p3/m, z8.h, z1.h ++sumopa bar.d, p7/m, p6/m, z8.h, z1.h ++sumops bar.d, p7/m, p6/m, z8.h, z1.h ++umopa foo.s, p6/m, p7/m, z4.b, z1.b ++umops foo.s, p6/m, p7/m, z4.b, z1.b ++usmopa foo.s, p4/m, p3/m, z4.b, z1.b ++usmops foo.s, p6/m, p7/m, z4.b, z1.b +diff --git a/gas/testsuite/gas/aarch64/sme-illegal.d b/gas/testsuite/gas/aarch64/sme-illegal.d +new file mode 100644 +index 00000000..8fb819ba +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/sme-illegal.d +@@ -0,0 +1,3 @@ ++#as: -march=armv8-a+sme+sme-i64+sme-f64 ++#source: sme-illegal.s ++#error_output: sme-illegal.l +diff --git a/gas/testsuite/gas/aarch64/sme-illegal.l b/gas/testsuite/gas/aarch64/sme-illegal.l +new file mode 100644 +index 00000000..19d22daa +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/sme-illegal.l +@@ -0,0 +1,95 @@ ++[^:]*: Assembler messages: ++[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za3 at operand 1 -- `addha za4.s,p0/m,p1/m,z1.s' ++[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za3 at operand 1 -- `addha za15.s,p2/m,p3/m,z2.s' ++[^:]*:[0-9]+: Error: operand mismatch -- `addha za0.s,p2/m,p3/m,z2.d' ++[^:]*:[0-9]+: Info: did you mean this\? ++[^:]*:[0-9]+: Info: addha za0.d, p2/m, p3/m, z2.d ++[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za7 at operand 1 -- `addha za8.d,p0/m,p1/m,z1.d' ++[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za7 at operand 1 -- `addha za15.d,p2/m,p3/m,z2.d' ++[^:]*:[0-9]+: Error: operand mismatch -- `addha za0.d,p2/m,p3/m,z2.s' ++[^:]*:[0-9]+: Info: did you mean this\? ++[^:]*:[0-9]+: Info: addha za0.d, p2/m, p3/m, z2.d ++[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za3 at operand 1 -- `addva za4.s,p0/m,p1/m,z1.s' ++[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za3 at operand 1 -- `addva za15.s,p2/m,p3/m,z2.s' ++[^:]*:[0-9]+: Error: operand mismatch -- `addva za0.s,p2/m,p3/m,z2.d' ++[^:]*:[0-9]+: Info: did you mean this\? ++[^:]*:[0-9]+: Info: addva za0.d, p2/m, p3/m, z2.d ++[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za7 at operand 1 -- `addva za8.d,p0/m,p1/m,z1.d' ++[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za7 at operand 1 -- `addva za15.d,p2/m,p3/m,z2.d' ++[^:]*:[0-9]+: Error: operand mismatch -- `addva za0.d,p2/m,p3/m,z2.s' ++[^:]*:[0-9]+: Info: did you mean this\? ++[^:]*:[0-9]+: Info: addva za0.d, p2/m, p3/m, z2.d ++[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za3 at operand 1 -- `bfmopa za4.s,p0/m,p1/m,z1.h,z4.h' ++[^:]*:[0-9]+: Error: operand mismatch -- `bfmopa za0.s,p2/m,p3/m,z2.s,z3.s' ++[^:]*:[0-9]+: Info: did you mean this\? ++[^:]*:[0-9]+: Info: bfmopa za0.s, p2/m, p3/m, z2.h, z3.h ++[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za3 at operand 1 -- `bfmops za4.s,p0/m,p1/m,z1.h,z4.h' ++[^:]*:[0-9]+: Error: operand mismatch -- `bfmops za0.s,p2/m,p3/m,z2.s,z3.s' ++[^:]*:[0-9]+: Info: did you mean this\? ++[^:]*:[0-9]+: Info: bfmops za0.s, p2/m, p3/m, z2.h, z3.h ++[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za3 at operand 1 -- `fmopa za4.s,p0/m,p1/m,z1.s,z4.s' ++[^:]*:[0-9]+: Error: operand mismatch -- `fmopa za0.s,p6/m,p7/m,z4.d,z1.d' ++[^:]*:[0-9]+: Info: did you mean this\? ++[^:]*:[0-9]+: Info: fmopa za0.d, p6/m, p7/m, z4.d, z1.d ++[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za7 at operand 1 -- `fmopa za8.d,p0/m,p1/m,z1.d,z8.d' ++[^:]*:[0-9]+: Error: operand mismatch -- `fmopa za0.d,p2/m,p3/m,z2.s,z7.s' ++[^:]*:[0-9]+: Info: did you mean this\? ++[^:]*:[0-9]+: Info: fmopa za0.d, p2/m, p3/m, z2.d, z7.d ++[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za3 at operand 1 -- `fmopa za4.s,p0/m,p1/m,z1.h,z4.h' ++[^:]*:[0-9]+: Error: operand mismatch -- `fmopa za1.s,p2/m,p3/m,z2.q,z3.q' ++[^:]*:[0-9]+: Info: did you mean this\? ++[^:]*:[0-9]+: Info: fmopa za1.d, p2/m, p3/m, z2.d, z3.d ++[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za3 at operand 1 -- `fmops za4.s,p0/m,p1/m,z1.s,z4.s' ++[^:]*:[0-9]+: Error: operand mismatch -- `fmops za1.s,p2/m,p3/m,z2.q,z3.q' ++[^:]*:[0-9]+: Info: did you mean this\? ++[^:]*:[0-9]+: Info: fmops za1.d, p2/m, p3/m, z2.d, z3.d ++[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za7 at operand 1 -- `fmops za8.d,p0/m,p1/m,z1.d,z8.d' ++[^:]*:[0-9]+: Error: operand mismatch -- `fmops za0.d,p2/m,p3/m,z2.s,z7.s' ++[^:]*:[0-9]+: Info: did you mean this\? ++[^:]*:[0-9]+: Info: fmops za0.d, p2/m, p3/m, z2.d, z7.d ++[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za3 at operand 1 -- `fmops za8.s,p0/m,p1/m,z1.h,z4.h' ++[^:]*:[0-9]+: Error: invalid ZA tile element size, allowed b, h, s and d at operand 1 -- `fmops za1.q,p2/m,p3/m,z2.h,z3.h' ++[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za3 at operand 1 -- `smopa za4.s,p0/m,p1/m,z1.b,z4.b' ++[^:]*:[0-9]+: Error: invalid ZA tile element size, allowed b, h, s and d at operand 1 -- `smopa za1.q,p2/m,p3/m,z2.b,z3.b' ++[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za7 at operand 1 -- `smopa za8.d,p0/m,p1/m,z1.h,z8.h' ++[^:]*:[0-9]+: Error: operand mismatch -- `smopa za1.d,p2/m,p3/m,z2.h,z7.q' ++[^:]*:[0-9]+: Info: did you mean this\? ++[^:]*:[0-9]+: Info: smopa za1.d, p2/m, p3/m, z2.h, z7.h ++[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za3 at operand 1 -- `smops za4.s,p0/m,p1/m,z1.b,z4.b' ++[^:]*:[0-9]+: Error: invalid ZA tile element size, allowed b, h, s and d at operand 1 -- `smops za1.q,p2/m,p3/m,z2.b,z3.b' ++[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za7 at operand 1 -- `smops za8.d,p0/m,p1/m,z1.h,z8.h' ++[^:]*:[0-9]+: Error: operand mismatch -- `smops za1.d,p2/m,p3/m,z2.h,z7.q' ++[^:]*:[0-9]+: Info: did you mean this\? ++[^:]*:[0-9]+: Info: smops za1.d, p2/m, p3/m, z2.h, z7.h ++[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za3 at operand 1 -- `sumopa za4.s,p0/m,p1/m,z1.b,z4.b' ++[^:]*:[0-9]+: Error: invalid ZA tile element size, allowed b, h, s and d at operand 1 -- `sumopa za1.q,p2/m,p3/m,z2.s,z3.s' ++[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za7 at operand 1 -- `sumopa za8.d,p0/m,p1/m,z1.h,z8.h' ++[^:]*:[0-9]+: Error: operand mismatch -- `sumopa za1.d,p2/m,p3/m,z2.h,z7.q' ++[^:]*:[0-9]+: Info: did you mean this\? ++[^:]*:[0-9]+: Info: sumopa za1.d, p2/m, p3/m, z2.h, z7.h ++[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za3 at operand 1 -- `sumops za4.s,p0/m,p1/m,z1.b,z4.b' ++[^:]*:[0-9]+: Error: invalid ZA tile element size, allowed b, h, s and d at operand 1 -- `sumops za1.q,p2/m,p3/m,z2.b,z3.b' ++[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za7 at operand 1 -- `sumops za8.d,p0/m,p1/m,z1.h,z8.h' ++[^:]*:[0-9]+: Error: invalid ZA tile element size, allowed b, h, s and d at operand 1 -- `sumops za1.q,p2/m,p3/m,z2.h,z7.h' ++[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za3 at operand 1 -- `umopa za4.s,p0/m,p1/m,z1.b,z4.b' ++[^:]*:[0-9]+: Error: invalid ZA tile element size, allowed b, h, s and d at operand 1 -- `umopa za1.q,p2/m,p3/m,z2.b,z3.b' ++[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za7 at operand 1 -- `umopa za8.d,p0/m,p1/m,z1.h,z8.h' ++[^:]*:[0-9]+: Error: invalid ZA tile element size, allowed b, h, s and d at operand 1 -- `umopa za1.q,p2/m,p3/m,z2.h,z7.h' ++[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za3 at operand 1 -- `umops za4.s,p0/m,p1/m,z1.b,z4.b' ++[^:]*:[0-9]+: Error: invalid ZA tile element size, allowed b, h, s and d at operand 1 -- `umops za1.q,p2/m,p3/m,z2.b,z3.b' ++[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za7 at operand 1 -- `umops za8.d,p0/m,p1/m,z1.h,z8.h' ++[^:]*:[0-9]+: Error: operand mismatch -- `umops za1.d,p2/m,p3/m,z2.d,z7.d' ++[^:]*:[0-9]+: Info: did you mean this\? ++[^:]*:[0-9]+: Info: umops za1.d, p2/m, p3/m, z2.h, z7.h ++[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za3 at operand 1 -- `usmopa za4.s,p0/m,p1/m,z1.b,z4.b' ++[^:]*:[0-9]+: Error: invalid ZA tile element size, allowed b, h, s and d at operand 1 -- `usmopa za1.q,p2/m,p3/m,z2.b,z3.b' ++[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za7 at operand 1 -- `usmopa za8.d,p0/m,p1/m,z1.h,z8.h' ++[^:]*:[0-9]+: Error: invalid ZA tile element size, allowed b, h, s and d at operand 1 -- `usmopa za1.q,p2/m,p3/m,z2.h,z7.h' ++[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za3 at operand 1 -- `usmops za4.s,p0/m,p1/m,z1.b,z4.b' ++[^:]*:[0-9]+: Error: operand mismatch -- `usmops za1.s,p2/m,p3/m,z2.s,z3.b' ++[^:]*:[0-9]+: Info: did you mean this\? ++[^:]*:[0-9]+: Info: usmops za1.d, p2/m, p3/m, z2.h, z3.h ++[^:]*:[0-9]+: Error: invalid ZA tile register number, expected za0-za7 at operand 1 -- `usmops za8.d,p0/m,p1/m,z1.h,z8.h' ++[^:]*:[0-9]+: Error: operand mismatch -- `usmops za1.d,p2/m,p3/m,z2.d,z7.d' ++[^:]*:[0-9]+: Info: did you mean this\? ++[^:]*:[0-9]+: Info: usmops za1.d, p2/m, p3/m, z2.h, z7.h +diff --git a/gas/testsuite/gas/aarch64/sme-illegal.s b/gas/testsuite/gas/aarch64/sme-illegal.s +new file mode 100644 +index 00000000..d543a642 +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/sme-illegal.s +@@ -0,0 +1,117 @@ ++/* Scalable Matrix Extension (SME). */ ++ ++/* ADDHA 32-bit variant. */ ++addha za4.s, p0/m, p1/m, z1.s ++addha za15.s, p2/m, p3/m, z2.s ++addha za0.s, p2/m, p3/m, z2.d ++ ++/* ADDHA 64-bit variant. */ ++addha za8.d, p0/m, p1/m, z1.d ++addha za15.d, p2/m, p3/m, z2.d ++addha za0.d, p2/m, p3/m, z2.s ++ ++/* ADDVA 32-bit variant. */ ++addva za4.s, p0/m, p1/m, z1.s ++addva za15.s, p2/m, p3/m, z2.s ++addva za0.s, p2/m, p3/m, z2.d ++ ++/* ADDVA 64-bit variant. */ ++addva za8.d, p0/m, p1/m, z1.d ++addva za15.d, p2/m, p3/m, z2.d ++addva za0.d, p2/m, p3/m, z2.s ++ ++/* BFMOPA. */ ++bfmopa za4.s, p0/m, p1/m, z1.h, z4.h ++bfmopa za0.s, p2/m, p3/m, z2.s, z3.s ++ ++/* BFMOPS. */ ++bfmops za4.s, p0/m, p1/m, z1.h, z4.h ++bfmops za0.s, p2/m, p3/m, z2.s, z3.s ++ ++/* FMOPA (non-widening), single-precision. */ ++fmopa za4.s, p0/m, p1/m, z1.s, z4.s ++fmopa za0.s, p6/m, p7/m, z4.d, z1.d ++ ++/* FMOPA (non-widening), double-precision. */ ++fmopa za8.d, p0/m, p1/m, z1.d, z8.d ++fmopa za0.d, p2/m, p3/m, z2.s, z7.s ++ ++/* FMOPA (widening) */ ++fmopa za4.s, p0/m, p1/m, z1.h, z4.h ++fmopa za1.s, p2/m, p3/m, z2.q, z3.q ++ ++/* FMOPS (non-widening), single-precision. */ ++fmops za4.s, p0/m, p1/m, z1.s, z4.s ++fmops za1.s, p2/m, p3/m, z2.q, z3.q ++ ++/* FMOPS (non-widening), double-precision. */ ++fmops za8.d, p0/m, p1/m, z1.d, z8.d ++fmops za0.d, p2/m, p3/m, z2.s, z7.s ++ ++/* FMOPS (widening) */ ++fmops za8.s, p0/m, p1/m, z1.h, z4.h ++fmops za1.q, p2/m, p3/m, z2.h, z3.h ++ ++/* SMOPA 32-bit variant. */ ++smopa za4.s, p0/m, p1/m, z1.b, z4.b ++smopa za1.q, p2/m, p3/m, z2.b, z3.b ++ ++/* SMOPA 64-bit variant. */ ++smopa za8.d, p0/m, p1/m, z1.h, z8.h ++smopa za1.d, p2/m, p3/m, z2.h, z7.q ++ ++/* SMOPS 32-bit variant. */ ++smops za4.s, p0/m, p1/m, z1.b, z4.b ++smops za1.q, p2/m, p3/m, z2.b, z3.b ++ ++/* SMOPS 64-bit variant. */ ++smops za8.d, p0/m, p1/m, z1.h, z8.h ++smops za1.d, p2/m, p3/m, z2.h, z7.q ++ ++/* SUMOPA 32-bit variant. */ ++sumopa za4.s, p0/m, p1/m, z1.b, z4.b ++sumopa za1.q, p2/m, p3/m, z2.s, z3.s ++ ++/* SUMOPA 64-bit variant. */ ++sumopa za8.d, p0/m, p1/m, z1.h, z8.h ++sumopa za1.d, p2/m, p3/m, z2.h, z7.q ++ ++/* SUMOPS 32-bit variant. */ ++sumops za4.s, p0/m, p1/m, z1.b, z4.b ++sumops za1.q, p2/m, p3/m, z2.b, z3.b ++ ++/* SUMOPS 64-bit variant. */ ++sumops za8.d, p0/m, p1/m, z1.h, z8.h ++sumops za1.q, p2/m, p3/m, z2.h, z7.h ++ ++/* UMOPA 32-bit variant. */ ++umopa za4.s, p0/m, p1/m, z1.b, z4.b ++umopa za1.q, p2/m, p3/m, z2.b, z3.b ++ ++/* UMOPA 64-bit variant. */ ++umopa za8.d, p0/m, p1/m, z1.h, z8.h ++umopa za1.q, p2/m, p3/m, z2.h, z7.h ++ ++/* UMOPS 32-bit variant. */ ++umops za4.s, p0/m, p1/m, z1.b, z4.b ++umops za1.q, p2/m, p3/m, z2.b, z3.b ++ ++/* UMOPS 64-bit variant. */ ++umops za8.d, p0/m, p1/m, z1.h, z8.h ++umops za1.d, p2/m, p3/m, z2.d, z7.d ++ ++/* USMOPA 32-bit variant. */ ++usmopa za4.s, p0/m, p1/m, z1.b, z4.b ++usmopa za1.q, p2/m, p3/m, z2.b, z3.b ++ ++/* USMOPA 64-bit variant. */ ++usmopa za8.d, p0/m, p1/m, z1.h, z8.h ++usmopa za1.q, p2/m, p3/m, z2.h, z7.h ++ ++/* USMOPS 32-bit variant. */ ++usmops za4.s, p0/m, p1/m, z1.b, z4.b ++usmops za1.s, p2/m, p3/m, z2.s, z3.b ++ ++/* USMOPS 64-bit variant. */ ++usmops za8.d, p0/m, p1/m, z1.h, z8.h ++usmops za1.d, p2/m, p3/m, z2.d, z7.d +diff --git a/gas/testsuite/gas/aarch64/sme.d b/gas/testsuite/gas/aarch64/sme.d +new file mode 100644 +index 00000000..673ac79c +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/sme.d +@@ -0,0 +1,93 @@ ++#name: SME extension ++#as: -march=armv8-a+sme ++#objdump: -dr ++ ++.*: file format .* ++ ++Disassembly of section \.text: ++ ++0+ <.*>: ++ 0: c0902020 addha za0.s, p0/m, p1/m, z1.s ++ 4: c0906841 addha za1.s, p2/m, p3/m, z2.s ++ 8: c090b062 addha za2.s, p4/m, p5/m, z3.s ++ c: c090f883 addha za3.s, p6/m, p7/m, z4.s ++ 10: c0912020 addva za0.s, p0/m, p1/m, z1.s ++ 14: c0916841 addva za1.s, p2/m, p3/m, z2.s ++ 18: c091b062 addva za2.s, p4/m, p5/m, z3.s ++ 1c: c091f883 addva za3.s, p6/m, p7/m, z4.s ++ 20: 81842020 bfmopa za0.s, p0/m, p1/m, z1.h, z4.h ++ 24: 81836841 bfmopa za1.s, p2/m, p3/m, z2.h, z3.h ++ 28: 8182b062 bfmopa za2.s, p4/m, p5/m, z3.h, z2.h ++ 2c: 8181f883 bfmopa za3.s, p6/m, p7/m, z4.h, z1.h ++ 30: 81842030 bfmops za0.s, p0/m, p1/m, z1.h, z4.h ++ 34: 81836851 bfmops za1.s, p2/m, p3/m, z2.h, z3.h ++ 38: 8182b072 bfmops za2.s, p4/m, p5/m, z3.h, z2.h ++ 3c: 8181f893 bfmops za3.s, p6/m, p7/m, z4.h, z1.h ++ 40: 80842020 fmopa za0.s, p0/m, p1/m, z1.s, z4.s ++ 44: 80836841 fmopa za1.s, p2/m, p3/m, z2.s, z3.s ++ 48: 8082b062 fmopa za2.s, p4/m, p5/m, z3.s, z2.s ++ 4c: 8081f883 fmopa za3.s, p6/m, p7/m, z4.s, z1.s ++ 50: 81a42020 fmopa za0.s, p0/m, p1/m, z1.h, z4.h ++ 54: 81a36841 fmopa za1.s, p2/m, p3/m, z2.h, z3.h ++ 58: 81a2b062 fmopa za2.s, p4/m, p5/m, z3.h, z2.h ++ 5c: 81a1f883 fmopa za3.s, p6/m, p7/m, z4.h, z1.h ++ 60: 80842030 fmops za0.s, p0/m, p1/m, z1.s, z4.s ++ 64: 80836851 fmops za1.s, p2/m, p3/m, z2.s, z3.s ++ 68: 8082b072 fmops za2.s, p4/m, p5/m, z3.s, z2.s ++ 6c: 8081f893 fmops za3.s, p6/m, p7/m, z4.s, z1.s ++ 70: 80841c30 fmops za0.s, p7/m, p0/m, z1.s, z4.s ++ 74: 80833851 fmops za1.s, p6/m, p1/m, z2.s, z3.s ++ 78: 80825472 fmops za2.s, p5/m, p2/m, z3.s, z2.s ++ 7c: 80817093 fmops za3.s, p4/m, p3/m, z4.s, z1.s ++ 80: 80842030 fmops za0.s, p0/m, p1/m, z1.s, z4.s ++ 84: 80836851 fmops za1.s, p2/m, p3/m, z2.s, z3.s ++ 88: 8082b072 fmops za2.s, p4/m, p5/m, z3.s, z2.s ++ 8c: 8081f893 fmops za3.s, p6/m, p7/m, z4.s, z1.s ++ 90: a0842020 smopa za0.s, p0/m, p1/m, z1.b, z4.b ++ 94: a0836841 smopa za1.s, p2/m, p3/m, z2.b, z3.b ++ 98: a082b062 smopa za2.s, p4/m, p5/m, z3.b, z2.b ++ 9c: a081f883 smopa za3.s, p6/m, p7/m, z4.b, z1.b ++ a0: a0842030 smops za0.s, p0/m, p1/m, z1.b, z4.b ++ a4: a0836851 smops za1.s, p2/m, p3/m, z2.b, z3.b ++ a8: a082b072 smops za2.s, p4/m, p5/m, z3.b, z2.b ++ ac: a081f893 smops za3.s, p6/m, p7/m, z4.b, z1.b ++ b0: a0a42020 sumopa za0.s, p0/m, p1/m, z1.b, z4.b ++ b4: a0a36841 sumopa za1.s, p2/m, p3/m, z2.b, z3.b ++ b8: a0a2b062 sumopa za2.s, p4/m, p5/m, z3.b, z2.b ++ bc: a0a1f883 sumopa za3.s, p6/m, p7/m, z4.b, z1.b ++ c0: a0a42030 sumops za0.s, p0/m, p1/m, z1.b, z4.b ++ c4: a0a36851 sumops za1.s, p2/m, p3/m, z2.b, z3.b ++ c8: a0a2b072 sumops za2.s, p4/m, p5/m, z3.b, z2.b ++ cc: a0a1f893 sumops za3.s, p6/m, p7/m, z4.b, z1.b ++ d0: a0a41c30 sumops za0.s, p7/m, p0/m, z1.b, z4.b ++ d4: a0a33851 sumops za1.s, p6/m, p1/m, z2.b, z3.b ++ d8: a0a25472 sumops za2.s, p5/m, p2/m, z3.b, z2.b ++ dc: a0a17093 sumops za3.s, p4/m, p3/m, z4.b, z1.b ++ e0: a1a42020 umopa za0.s, p0/m, p1/m, z1.b, z4.b ++ e4: a1a36841 umopa za1.s, p2/m, p3/m, z2.b, z3.b ++ e8: a1a2b062 umopa za2.s, p4/m, p5/m, z3.b, z2.b ++ ec: a1a1f883 umopa za3.s, p6/m, p7/m, z4.b, z1.b ++ f0: a1a42030 umops za0.s, p0/m, p1/m, z1.b, z4.b ++ f4: a1a36851 umops za1.s, p2/m, p3/m, z2.b, z3.b ++ f8: a1a2b072 umops za2.s, p4/m, p5/m, z3.b, z2.b ++ fc: a1a1f893 umops za3.s, p6/m, p7/m, z4.b, z1.b ++ 100: a1842020 usmopa za0.s, p0/m, p1/m, z1.b, z4.b ++ 104: a1836841 usmopa za1.s, p2/m, p3/m, z2.b, z3.b ++ 108: a182b062 usmopa za2.s, p4/m, p5/m, z3.b, z2.b ++ 10c: a181f883 usmopa za3.s, p6/m, p7/m, z4.b, z1.b ++ 110: a1841c20 usmopa za0.s, p7/m, p0/m, z1.b, z4.b ++ 114: a1833841 usmopa za1.s, p6/m, p1/m, z2.b, z3.b ++ 118: a1825462 usmopa za2.s, p5/m, p2/m, z3.b, z2.b ++ 11c: a1817083 usmopa za3.s, p4/m, p3/m, z4.b, z1.b ++ 120: a1842030 usmops za0.s, p0/m, p1/m, z1.b, z4.b ++ 124: a1836851 usmops za1.s, p2/m, p3/m, z2.b, z3.b ++ 128: a182b072 usmops za2.s, p4/m, p5/m, z3.b, z2.b ++ 12c: a181f893 usmops za3.s, p6/m, p7/m, z4.b, z1.b ++ 130: 8181f883 bfmopa za3.s, p6/m, p7/m, z4.h, z1.h ++ 134: 8181f893 bfmops za3.s, p6/m, p7/m, z4.h, z1.h ++ 138: 81a1f883 fmopa za3.s, p6/m, p7/m, z4.h, z1.h ++ 13c: 8081f893 fmops za3.s, p6/m, p7/m, z4.s, z1.s ++ 140: a1a1f883 umopa za3.s, p6/m, p7/m, z4.b, z1.b ++ 144: a1a1f893 umops za3.s, p6/m, p7/m, z4.b, z1.b ++ 148: a1817083 usmopa za3.s, p4/m, p3/m, z4.b, z1.b ++ 14c: a181f893 usmops za3.s, p6/m, p7/m, z4.b, z1.b +diff --git a/gas/testsuite/gas/aarch64/sme.s b/gas/testsuite/gas/aarch64/sme.s +new file mode 100644 +index 00000000..ad48fa0e +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/sme.s +@@ -0,0 +1,123 @@ ++/* Scalable Matrix Extension (SME). */ ++ ++/* ADDHA 32-bit variant. */ ++addha za0.s, p0/m, p1/m, z1.s ++addha za1.s, p2/m, p3/m, z2.s ++addha za2.s, p4/m, p5/m, z3.s ++addha za3.s, p6/m, p7/m, z4.s ++ ++/* ADDVA 32-bit variant. */ ++addva za0.s, p0/m, p1/m, z1.s ++addva za1.s, p2/m, p3/m, z2.s ++addva za2.s, p4/m, p5/m, z3.s ++addva za3.s, p6/m, p7/m, z4.s ++ ++/* BFMOPA. */ ++bfmopa za0.s, p0/m, p1/m, z1.h, z4.h ++bfmopa za1.s, p2/m, p3/m, z2.h, z3.h ++bfmopa za2.s, p4/m, p5/m, z3.h, z2.h ++bfmopa za3.s, p6/m, p7/m, z4.h, z1.h ++ ++/* BFMOPS. */ ++bfmops za0.s, p0/m, p1/m, z1.h, z4.h ++bfmops za1.s, p2/m, p3/m, z2.h, z3.h ++bfmops za2.s, p4/m, p5/m, z3.h, z2.h ++bfmops za3.s, p6/m, p7/m, z4.h, z1.h ++ ++/* FMOPA (non-widening), single-precision. */ ++fmopa za0.s, p0/m, p1/m, z1.s, z4.s ++fmopa za1.s, p2/m, p3/m, z2.s, z3.s ++fmopa za2.s, p4/m, p5/m, z3.s, z2.s ++fmopa za3.s, p6/m, p7/m, z4.s, z1.s ++ ++/* FMOPA (widening) */ ++fmopa za0.s, p0/m, p1/m, z1.h, z4.h ++fmopa za1.s, p2/m, p3/m, z2.h, z3.h ++fmopa za2.s, p4/m, p5/m, z3.h, z2.h ++fmopa za3.s, p6/m, p7/m, z4.h, z1.h ++ ++/* FMOPS (non-widening), single-precision. */ ++fmops za0.s, p0/m, p1/m, z1.s, z4.s ++fmops za1.s, p2/m, p3/m, z2.s, z3.s ++fmops za2.s, p4/m, p5/m, z3.s, z2.s ++fmops za3.s, p6/m, p7/m, z4.s, z1.s ++fmops za0.s, p7/m, p0/m, z1.s, z4.s ++fmops za1.s, p6/m, p1/m, z2.s, z3.s ++fmops za2.s, p5/m, p2/m, z3.s, z2.s ++fmops za3.s, p4/m, p3/m, z4.s, z1.s ++ ++/* FMOPS (widening) */ ++fmops za0.s, p0/m, p1/m, z1.s, z4.s ++fmops za1.s, p2/m, p3/m, z2.s, z3.s ++fmops za2.s, p4/m, p5/m, z3.s, z2.s ++fmops za3.s, p6/m, p7/m, z4.s, z1.s ++ ++/* SMOPA 32-bit variant. */ ++smopa za0.s, p0/m, p1/m, z1.b, z4.b ++smopa za1.s, p2/m, p3/m, z2.b, z3.b ++smopa za2.s, p4/m, p5/m, z3.b, z2.b ++smopa za3.s, p6/m, p7/m, z4.b, z1.b ++ ++/* SMOPS 32-bit variant. */ ++smops za0.s, p0/m, p1/m, z1.b, z4.b ++smops za1.s, p2/m, p3/m, z2.b, z3.b ++smops za2.s, p4/m, p5/m, z3.b, z2.b ++smops za3.s, p6/m, p7/m, z4.b, z1.b ++ ++/* SUMOPA 32-bit variant. */ ++sumopa za0.s, p0/m, p1/m, z1.b, z4.b ++sumopa za1.s, p2/m, p3/m, z2.b, z3.b ++sumopa za2.s, p4/m, p5/m, z3.b, z2.b ++sumopa za3.s, p6/m, p7/m, z4.b, z1.b ++ ++/* SUMOPS 32-bit variant. */ ++sumops za0.s, p0/m, p1/m, z1.b, z4.b ++sumops za1.s, p2/m, p3/m, z2.b, z3.b ++sumops za2.s, p4/m, p5/m, z3.b, z2.b ++sumops za3.s, p6/m, p7/m, z4.b, z1.b ++sumops za0.s, p7/m, p0/m, z1.b, z4.b ++sumops za1.s, p6/m, p1/m, z2.b, z3.b ++sumops za2.s, p5/m, p2/m, z3.b, z2.b ++sumops za3.s, p4/m, p3/m, z4.b, z1.b ++ ++/* UMOPA 32-bit variant. */ ++umopa za0.s, p0/m, p1/m, z1.b, z4.b ++umopa za1.s, p2/m, p3/m, z2.b, z3.b ++umopa za2.s, p4/m, p5/m, z3.b, z2.b ++umopa za3.s, p6/m, p7/m, z4.b, z1.b ++ ++/* UMOPS 32-bit variant. */ ++umops za0.s, p0/m, p1/m, z1.b, z4.b ++umops za1.s, p2/m, p3/m, z2.b, z3.b ++umops za2.s, p4/m, p5/m, z3.b, z2.b ++umops za3.s, p6/m, p7/m, z4.b, z1.b ++ ++/* USMOPA 32-bit variant. */ ++usmopa za0.s, p0/m, p1/m, z1.b, z4.b ++usmopa za1.s, p2/m, p3/m, z2.b, z3.b ++usmopa za2.s, p4/m, p5/m, z3.b, z2.b ++usmopa za3.s, p6/m, p7/m, z4.b, z1.b ++usmopa za0.s, p7/m, p0/m, z1.b, z4.b ++usmopa za1.s, p6/m, p1/m, z2.b, z3.b ++usmopa za2.s, p5/m, p2/m, z3.b, z2.b ++usmopa za3.s, p4/m, p3/m, z4.b, z1.b ++ ++/* USMOPS 32-bit variant. */ ++usmops za0.s, p0/m, p1/m, z1.b, z4.b ++usmops za1.s, p2/m, p3/m, z2.b, z3.b ++usmops za2.s, p4/m, p5/m, z3.b, z2.b ++usmops za3.s, p6/m, p7/m, z4.b, z1.b ++ ++/* Register aliases. */ ++foo .req za3 ++bar .req za7 ++baz .req za0 ++ ++bfmopa foo.s, p6/m, p7/m, z4.h, z1.h ++bfmops foo.s, p6/m, p7/m, z4.h, z1.h ++fmopa foo.s, p6/m, p7/m, z4.h, z1.h ++fmops foo.s, p6/m, p7/m, z4.s, z1.s ++umopa foo.s, p6/m, p7/m, z4.b, z1.b ++umops foo.s, p6/m, p7/m, z4.b, z1.b ++usmopa foo.s, p4/m, p3/m, z4.b, z1.b ++usmops foo.s, p6/m, p7/m, z4.b, z1.b +diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h +index 7256028d..4b971ea2 100644 +--- a/include/opcode/aarch64.h ++++ b/include/opcode/aarch64.h +@@ -440,6 +440,9 @@ enum aarch64_opnd + AARCH64_OPND_SVE_ZnxN, /* SVE vector register list in Zn. */ + AARCH64_OPND_SVE_Zt, /* SVE vector register in Zt. */ + AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */ ++ AARCH64_OPND_SME_ZAda_2b, /* SME .S, 2-bits. */ ++ AARCH64_OPND_SME_ZAda_3b, /* SME .D, 3-bits. */ ++ AARCH64_OPND_SME_Pm, /* SME scalable predicate register, bits [15:13]. */ + AARCH64_OPND_TME_UIMM16, /* TME unsigned 16-bit immediate. */ + AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */ + }; +@@ -604,6 +607,7 @@ enum aarch64_insn_class + movewide, + pcreladdr, + ic_system, ++ sme_misc, + sve_cpy, + sve_index, + sve_limm, +diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c +index 26d61da4..4839fef8 100644 +--- a/opcodes/aarch64-asm-2.c ++++ b/opcodes/aarch64-asm-2.c +@@ -661,6 +661,9 @@ aarch64_insert_operand (const aarch64_operand *self, + case 198: + case 204: + case 207: ++ case 209: ++ case 210: ++ case 211: + return aarch64_ins_regno (self, info, code, inst, errors); + case 15: + return aarch64_ins_reg_extended (self, info, code, inst, errors); +@@ -672,7 +675,7 @@ aarch64_insert_operand (const aarch64_operand *self, + case 33: + case 34: + case 35: +- case 210: ++ case 213: + return aarch64_ins_reglane (self, info, code, inst, errors); + case 36: + return aarch64_ins_reglist (self, info, code, inst, errors); +@@ -717,7 +720,7 @@ aarch64_insert_operand (const aarch64_operand *self, + case 187: + case 188: + case 189: +- case 209: ++ case 212: + return aarch64_ins_imm (self, info, code, inst, errors); + case 44: + case 45: +diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c +index 1b98ee64..4376e3bc 100644 +--- a/opcodes/aarch64-dis-2.c ++++ b/opcodes/aarch64-dis-2.c +@@ -36,11 +36,187 @@ aarch64_opcode_lookup_1 (uint32_t word) + { + if (((word >> 28) & 0x1) == 0) + { +- /* 33222222222211111111110000000000 +- 10987654321098765432109876543210 +- xxx00000xxxxxxxxxxxxxxxxxxxxxxxx +- udf. */ +- return 754; ++ if (((word >> 21) & 0x1) == 0) ++ { ++ if (((word >> 22) & 0x1) == 0) ++ { ++ if (((word >> 23) & 0x1) == 0) ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ xxx00000000xxxxxxxxxxxxxxxxxxxxx ++ udf. */ ++ return 754; ++ } ++ else ++ { ++ if (((word >> 4) & 0x1) == 0) ++ { ++ if (((word >> 29) & 0x1) == 0) ++ { ++ if (((word >> 30) & 0x1) == 0) ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ x0000000100xxxxxxxxxxxxxxxx0xxxx ++ fmopa. */ ++ return 2354; ++ } ++ else ++ { ++ if (((word >> 16) & 0x1) == 0) ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ x1000000100xxxx0xxxxxxxxxxx0xxxx ++ addha. */ ++ return 2348; ++ } ++ else ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ x1000000100xxxx1xxxxxxxxxxx0xxxx ++ addva. */ ++ return 2350; ++ } ++ } ++ } ++ else ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ xx100000100xxxxxxxxxxxxxxxx0xxxx ++ smopa. */ ++ return 2360; ++ } ++ } ++ else ++ { ++ if (((word >> 29) & 0x1) == 0) ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ xx000000100xxxxxxxxxxxxxxxx1xxxx ++ fmops. */ ++ return 2357; ++ } ++ else ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ xx100000100xxxxxxxxxxxxxxxx1xxxx ++ smops. */ ++ return 2362; ++ } ++ } ++ } ++ } ++ else ++ { ++ if (((word >> 4) & 0x1) == 0) ++ { ++ if (((word >> 29) & 0x1) == 0) ++ { ++ if (((word >> 30) & 0x1) == 0) ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ x0000000x10xxxxxxxxxxxxxxxx0xxxx ++ fmopa. */ ++ return 2355; ++ } ++ else ++ { ++ if (((word >> 16) & 0x1) == 0) ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ x1000000x10xxxx0xxxxxxxxxxx0xxxx ++ addha. */ ++ return 2349; ++ } ++ else ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ x1000000x10xxxx1xxxxxxxxxxx0xxxx ++ addva. */ ++ return 2351; ++ } ++ } ++ } ++ else ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ xx100000x10xxxxxxxxxxxxxxxx0xxxx ++ smopa. */ ++ return 2361; ++ } ++ } ++ else ++ { ++ if (((word >> 29) & 0x1) == 0) ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ xx000000x10xxxxxxxxxxxxxxxx1xxxx ++ fmops. */ ++ return 2358; ++ } ++ else ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ xx100000x10xxxxxxxxxxxxxxxx1xxxx ++ smops. */ ++ return 2363; ++ } ++ } ++ } ++ } ++ else ++ { ++ if (((word >> 4) & 0x1) == 0) ++ { ++ if (((word >> 22) & 0x1) == 0) ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ xxx00000x01xxxxxxxxxxxxxxxx0xxxx ++ sumopa. */ ++ return 2364; ++ } ++ else ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ xxx00000x11xxxxxxxxxxxxxxxx0xxxx ++ sumopa. */ ++ return 2365; ++ } ++ } ++ else ++ { ++ if (((word >> 22) & 0x1) == 0) ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ xxx00000x01xxxxxxxxxxxxxxxx1xxxx ++ sumops. */ ++ return 2366; ++ } ++ else ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ xxx00000x11xxxxxxxxxxxxxxxx1xxxx ++ sumops. */ ++ return 2367; ++ } ++ } ++ } + } + else + { +@@ -64,42 +240,174 @@ aarch64_opcode_lookup_1 (uint32_t word) + } + else + { +- if (((word >> 29) & 0x1) == 0) ++ if (((word >> 28) & 0x1) == 0) + { +- if (((word >> 30) & 0x1) == 0) ++ if (((word >> 4) & 0x1) == 0) + { +- /* 33222222222211111111110000000000 +- 10987654321098765432109876543210 +- x00x0001xxxxxxxxxxxxxxxxxxxxxxxx +- add. */ +- return 12; ++ if (((word >> 21) & 0x1) == 0) ++ { ++ if (((word >> 22) & 0x1) == 0) ++ { ++ if (((word >> 29) & 0x1) == 0) ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ xx000001x00xxxxxxxxxxxxxxxx0xxxx ++ bfmopa. */ ++ return 2352; ++ } ++ else ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ xx100001x00xxxxxxxxxxxxxxxx0xxxx ++ usmopa. */ ++ return 2372; ++ } ++ } ++ else ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ xxx00001x10xxxxxxxxxxxxxxxx0xxxx ++ usmopa. */ ++ return 2373; ++ } ++ } ++ else ++ { ++ if (((word >> 22) & 0x1) == 0) ++ { ++ if (((word >> 29) & 0x1) == 0) ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ xx000001x01xxxxxxxxxxxxxxxx0xxxx ++ fmopa. */ ++ return 2356; ++ } ++ else ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ xx100001x01xxxxxxxxxxxxxxxx0xxxx ++ umopa. */ ++ return 2368; ++ } ++ } ++ else ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ xxx00001x11xxxxxxxxxxxxxxxx0xxxx ++ umopa. */ ++ return 2369; ++ } ++ } + } + else + { +- /* 33222222222211111111110000000000 +- 10987654321098765432109876543210 +- x10x0001xxxxxxxxxxxxxxxxxxxxxxxx +- sub. */ +- return 16; ++ if (((word >> 21) & 0x1) == 0) ++ { ++ if (((word >> 22) & 0x1) == 0) ++ { ++ if (((word >> 29) & 0x1) == 0) ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ xx000001x00xxxxxxxxxxxxxxxx1xxxx ++ bfmops. */ ++ return 2353; ++ } ++ else ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ xx100001x00xxxxxxxxxxxxxxxx1xxxx ++ usmops. */ ++ return 2374; ++ } ++ } ++ else ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ xxx00001x10xxxxxxxxxxxxxxxx1xxxx ++ usmops. */ ++ return 2375; ++ } ++ } ++ else ++ { ++ if (((word >> 22) & 0x1) == 0) ++ { ++ if (((word >> 29) & 0x1) == 0) ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ xx000001x01xxxxxxxxxxxxxxxx1xxxx ++ fmops. */ ++ return 2359; ++ } ++ else ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ xx100001x01xxxxxxxxxxxxxxxx1xxxx ++ umops. */ ++ return 2370; ++ } ++ } ++ else ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ xxx00001x11xxxxxxxxxxxxxxxx1xxxx ++ umops. */ ++ return 2371; ++ } ++ } + } + } + else + { +- if (((word >> 30) & 0x1) == 0) ++ if (((word >> 29) & 0x1) == 0) + { +- /* 33222222222211111111110000000000 +- 10987654321098765432109876543210 +- x01x0001xxxxxxxxxxxxxxxxxxxxxxxx +- adds. */ +- return 14; ++ if (((word >> 30) & 0x1) == 0) ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ x0010001xxxxxxxxxxxxxxxxxxxxxxxx ++ add. */ ++ return 12; ++ } ++ else ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ x1010001xxxxxxxxxxxxxxxxxxxxxxxx ++ sub. */ ++ return 16; ++ } + } + else + { +- /* 33222222222211111111110000000000 +- 10987654321098765432109876543210 +- x11x0001xxxxxxxxxxxxxxxxxxxxxxxx +- subs. */ +- return 17; ++ if (((word >> 30) & 0x1) == 0) ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ x0110001xxxxxxxxxxxxxxxxxxxxxxxx ++ adds. */ ++ return 14; ++ } ++ else ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ x1110001xxxxxxxxxxxxxxxxxxxxxxxx ++ subs. */ ++ return 17; ++ } + } + } + } +@@ -2423,7 +2731,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 00011001000xxxxxxxxx00xxxxxxxxxx + stlurb. */ +- return 2388; ++ return 2416; + } + else + { +@@ -2431,7 +2739,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 10011001000xxxxxxxxx00xxxxxxxxxx + stlur. */ +- return 2396; ++ return 2424; + } + } + else +@@ -2442,7 +2750,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 01011001000xxxxxxxxx00xxxxxxxxxx + stlurh. */ +- return 2392; ++ return 2420; + } + else + { +@@ -2450,7 +2758,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 11011001000xxxxxxxxx00xxxxxxxxxx + stlur. */ +- return 2399; ++ return 2427; + } + } + } +@@ -2530,7 +2838,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 00011001010xxxxxxxxx00xxxxxxxxxx + ldapurb. */ +- return 2389; ++ return 2417; + } + else + { +@@ -2538,7 +2846,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 10011001010xxxxxxxxx00xxxxxxxxxx + ldapur. */ +- return 2397; ++ return 2425; + } + } + else +@@ -2549,7 +2857,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 01011001010xxxxxxxxx00xxxxxxxxxx + ldapurh. */ +- return 2393; ++ return 2421; + } + else + { +@@ -2557,7 +2865,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 11011001010xxxxxxxxx00xxxxxxxxxx + ldapur. */ +- return 2400; ++ return 2428; + } + } + } +@@ -2640,7 +2948,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 00011001100xxxxxxxxx00xxxxxxxxxx + ldapursb. */ +- return 2391; ++ return 2419; + } + else + { +@@ -2648,7 +2956,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 10011001100xxxxxxxxx00xxxxxxxxxx + ldapursw. */ +- return 2398; ++ return 2426; + } + } + else +@@ -2657,7 +2965,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1011001100xxxxxxxxx00xxxxxxxxxx + ldapursh. */ +- return 2395; ++ return 2423; + } + } + else +@@ -2668,7 +2976,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x0011001110xxxxxxxxx00xxxxxxxxxx + ldapursb. */ +- return 2390; ++ return 2418; + } + else + { +@@ -2676,7 +2984,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1011001110xxxxxxxxx00xxxxxxxxxx + ldapursh. */ +- return 2394; ++ return 2422; + } + } + } +@@ -3162,7 +3470,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xxx11010x00xxxxxx0xx10xxxxxxxxxx + setf8. */ +- return 2386; ++ return 2414; + } + else + { +@@ -3170,7 +3478,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xxx11010x00xxxxxx1xx10xxxxxxxxxx + setf16. */ +- return 2387; ++ return 2415; + } + } + else +@@ -3316,7 +3624,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xxx11010000xxxxxxxxx01xxxxxxxxxx + rmif. */ +- return 2385; ++ return 2413; + } + else + { +@@ -4365,7 +4673,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x01x1xxxxx000110xxxxxxxxxx + usdot. */ +- return 2405; ++ return 2433; + } + } + } +@@ -4439,7 +4747,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x01x1xxxxx000111xxxxxxxxxx + sudot. */ +- return 2406; ++ return 2434; + } + } + } +@@ -7058,7 +7366,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0xx0xxxxx011110xxxxxxxxxx + usdot. */ +- return 2404; ++ return 2432; + } + } + } +@@ -8762,7 +9070,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0100xxx10101xxxxxxxxxxxxx + bfcvtnt. */ +- return 2433; ++ return 2461; + } + } + else +@@ -9005,7 +9313,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x00x1xxxxxx00xxxxxxxxxxxxx + ld1rob. */ +- return 2409; ++ return 2437; + } + else + { +@@ -9013,7 +9321,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x01x1xxxxxx00xxxxxxxxxxxxx + ld1roh. */ +- return 2410; ++ return 2438; + } + } + else +@@ -9245,7 +9553,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0011xxxxx010xxxxxxxxxxxxx + bfdot. */ +- return 2430; ++ return 2458; + } + else + { +@@ -9266,7 +9574,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0111xxxxx010xx0xxxxxxxxxx + bfmlalb. */ +- return 2437; ++ return 2465; + } + else + { +@@ -9274,7 +9582,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0111xxxxx010xx1xxxxxxxxxx + bfmlalt. */ +- return 2436; ++ return 2464; + } + } + else +@@ -9329,7 +9637,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x11001x0011xxxxx1x0xxxxxxxxxxxxx + bfdot. */ +- return 2429; ++ return 2457; + } + else + { +@@ -9341,7 +9649,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0111xxxxx1x0xx0xxxxxxxxxx + bfmlalb. */ +- return 2435; ++ return 2463; + } + else + { +@@ -9349,7 +9657,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0111xxxxx1x0xx1xxxxxxxxxx + bfmlalt. */ +- return 2434; ++ return 2462; + } + } + else +@@ -9400,7 +9708,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x00x1xxxxx001xxxxxxxxxxxxx + ld1rob. */ +- return 2413; ++ return 2441; + } + else + { +@@ -9408,7 +9716,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x01x1xxxxx001xxxxxxxxxxxxx + ld1roh. */ +- return 2414; ++ return 2442; + } + } + else +@@ -9767,7 +10075,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0101xxxxx111xxxxxxxxxxxxx + fmmla. */ +- return 2407; ++ return 2435; + } + else + { +@@ -9800,7 +10108,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0011xxxxx111xxxxxxxxxxxxx + bfmmla. */ +- return 2431; ++ return 2459; + } + else + { +@@ -9830,7 +10138,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0111xxxxx111xxxxxxxxxxxxx + fmmla. */ +- return 2408; ++ return 2436; + } + else + { +@@ -9959,7 +10267,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1101xxxxx000x00xxxxxxxxxx + zip1. */ +- return 2417; ++ return 2445; + } + else + { +@@ -9969,7 +10277,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1101xxxxx000010xxxxxxxxxx + uzp1. */ +- return 2419; ++ return 2447; + } + else + { +@@ -9977,7 +10285,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1101xxxxx000110xxxxxxxxxx + trn1. */ +- return 2421; ++ return 2449; + } + } + } +@@ -9989,7 +10297,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1101xxxxx000x01xxxxxxxxxx + zip2. */ +- return 2418; ++ return 2446; + } + else + { +@@ -9999,7 +10307,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1101xxxxx000011xxxxxxxxxx + uzp2. */ +- return 2420; ++ return 2448; + } + else + { +@@ -10007,7 +10315,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1101xxxxx000111xxxxxxxxxx + trn2. */ +- return 2422; ++ return 2450; + } + } + } +@@ -11055,7 +11363,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1000xxxxx100110xxxxxxxxxx + smmla. */ +- return 2401; ++ return 2429; + } + else + { +@@ -11063,7 +11371,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1100xxxxx100110xxxxxxxxxx + usmmla. */ +- return 2403; ++ return 2431; + } + } + else +@@ -11072,7 +11380,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1x10xxxxx100110xxxxxxxxxx + ummla. */ +- return 2402; ++ return 2430; + } + } + } +@@ -12568,7 +12876,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x10x1xxxxx000xxxxxxxxxxxxx + ld1row. */ +- return 2411; ++ return 2439; + } + else + { +@@ -12576,7 +12884,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x11x1xxxxx000xxxxxxxxxxxxx + ld1rod. */ +- return 2412; ++ return 2440; + } + } + } +@@ -12950,7 +13258,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x10x1xxxxx001xxxxxxxxxxxxx + ld1row. */ +- return 2415; ++ return 2443; + } + else + { +@@ -12958,7 +13266,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x11x1xxxxx001xxxxxxxxxxxxx + ld1rod. */ +- return 2416; ++ return 2444; + } + } + } +@@ -14392,7 +14700,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x110001x10101xxxxxxxxxxxxx + bfcvt. */ +- return 2432; ++ return 2460; + } + } + else +@@ -16461,7 +16769,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 0x001110xx0xxxxx1x1001xxxxxxxxxx + smmla. */ +- return 2423; ++ return 2451; + } + } + } +@@ -16494,7 +16802,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 0x001110xx0xxxxx1x0101xxxxxxxxxx + sdot. */ +- return 2349; ++ return 2377; + } + } + else +@@ -16568,7 +16876,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 0x001110xx0xxxxx1x1011xxxxxxxxxx + usmmla. */ +- return 2425; ++ return 2453; + } + } + } +@@ -16601,7 +16909,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 0x001110xx0xxxxx1x0111xxxxxxxxxx + usdot. */ +- return 2426; ++ return 2454; + } + } + else +@@ -16648,7 +16956,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110000xxxxxxxxxxxxxxxxxxxxx + eor3. */ +- return 2356; ++ return 2384; + } + else + { +@@ -16656,7 +16964,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110100xxxxxxxxxxxxxxxxxxxxx + xar. */ +- return 2358; ++ return 2386; + } + } + else +@@ -16667,7 +16975,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110x10xxxxx0xxxxxxxxxxxxxxx + sm3ss1. */ +- return 2360; ++ return 2388; + } + else + { +@@ -16681,7 +16989,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110010xxxxx1xxx00xxxxxxxxxx + sm3tt1a. */ +- return 2361; ++ return 2389; + } + else + { +@@ -16689,7 +16997,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110110xxxxx1xxx00xxxxxxxxxx + sha512su0. */ +- return 2354; ++ return 2382; + } + } + else +@@ -16698,7 +17006,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110x10xxxxx1xxx10xxxxxxxxxx + sm3tt2a. */ +- return 2363; ++ return 2391; + } + } + else +@@ -16711,7 +17019,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110010xxxxx1xxx01xxxxxxxxxx + sm3tt1b. */ +- return 2362; ++ return 2390; + } + else + { +@@ -16719,7 +17027,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110110xxxxx1xxx01xxxxxxxxxx + sm4e. */ +- return 2367; ++ return 2395; + } + } + else +@@ -16728,7 +17036,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110x10xxxxx1xxx11xxxxxxxxxx + sm3tt2b. */ +- return 2364; ++ return 2392; + } + } + } +@@ -16909,7 +17217,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx101110xx0xxxxx100101xxxxxxxxxx + udot. */ +- return 2348; ++ return 2376; + } + } + else +@@ -16940,7 +17248,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx101110xx0xxxxx101x01xxxxxxxxxx + ummla. */ +- return 2424; ++ return 2452; + } + else + { +@@ -16959,7 +17267,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx101110xx0xxxxx1x1011xxxxxxxxxx + bfmmla. */ +- return 2440; ++ return 2468; + } + else + { +@@ -16969,7 +17277,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx1011100x0xxxxx1x1111xxxxxxxxxx + bfdot. */ +- return 2438; ++ return 2466; + } + else + { +@@ -16979,7 +17287,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x01011101x0xxxxx1x1111xxxxxxxxxx + bfmlalb. */ +- return 2445; ++ return 2473; + } + else + { +@@ -16987,7 +17295,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x11011101x0xxxxx1x1111xxxxxxxxxx + bfmlalt. */ +- return 2444; ++ return 2472; + } + } + } +@@ -17571,7 +17879,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000011101x1xxxx1011010xxxxxxxxxx + bfcvtn. */ +- return 2441; ++ return 2469; + } + else + { +@@ -17579,7 +17887,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010011101x1xxxx1011010xxxxxxxxxx + bfcvtn2. */ +- return 2442; ++ return 2470; + } + } + } +@@ -17897,7 +18205,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110xx1xxxxx0xxxxxxxxxxxxxxx + bcax. */ +- return 2359; ++ return 2387; + } + } + else +@@ -18508,7 +18816,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 11001110xx1xxxxx100000xxxxxxxxxx + sha512h. */ +- return 2352; ++ return 2380; + } + } + } +@@ -18560,7 +18868,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 11001110xx1xxxxx110000xxxxxxxxxx + sm3partw1. */ +- return 2365; ++ return 2393; + } + } + } +@@ -18803,7 +19111,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110xx1xxxxx100010xxxxxxxxxx + sha512su1. */ +- return 2355; ++ return 2383; + } + } + else +@@ -18879,7 +19187,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x0011100x1xxxxx110010xxxxxxxxxx + sm4ekey. */ +- return 2368; ++ return 2396; + } + } + else +@@ -19705,7 +20013,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110xx1xxxxx100001xxxxxxxxxx + sha512h2. */ +- return 2353; ++ return 2381; + } + } + else +@@ -19737,7 +20045,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x0011100x1xxxxx110001xxxxxxxxxx + sm3partw2. */ +- return 2366; ++ return 2394; + } + } + else +@@ -19977,7 +20285,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110xx1xxxxx100011xxxxxxxxxx + rax1. */ +- return 2357; ++ return 2385; + } + } + else +@@ -20009,7 +20317,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x01011100x1xxxxx110011xxxxxxxxxx + fmlal2. */ +- return 2371; ++ return 2399; + } + else + { +@@ -20017,7 +20325,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x11011100x1xxxxx110011xxxxxxxxxx + fmlal2. */ +- return 2375; ++ return 2403; + } + } + } +@@ -20039,7 +20347,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x01011101x1xxxxx110011xxxxxxxxxx + fmlsl2. */ +- return 2372; ++ return 2400; + } + else + { +@@ -20047,7 +20355,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x11011101x1xxxxx110011xxxxxxxxxx + fmlsl2. */ +- return 2376; ++ return 2404; + } + } + } +@@ -20086,7 +20394,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x00011100x1xxxxx111011xxxxxxxxxx + fmlal. */ +- return 2369; ++ return 2397; + } + else + { +@@ -20094,7 +20402,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x10011100x1xxxxx111011xxxxxxxxxx + fmlal. */ +- return 2373; ++ return 2401; + } + } + else +@@ -20116,7 +20424,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x00011101x1xxxxx111011xxxxxxxxxx + fmlsl. */ +- return 2370; ++ return 2398; + } + else + { +@@ -20124,7 +20432,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x10011101x1xxxxx111011xxxxxxxxxx + fmlsl. */ +- return 2374; ++ return 2402; + } + } + else +@@ -21932,7 +22240,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x0001111xxxxxxxx0000x0xxxxxxxxxx + fmlal. */ +- return 2377; ++ return 2405; + } + else + { +@@ -21940,7 +22248,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1001111xxxxxxxx0000x0xxxxxxxxxx + fmlal. */ +- return 2381; ++ return 2409; + } + } + else +@@ -21962,7 +22270,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x0001111xxxxxxxx0100x0xxxxxxxxxx + fmlsl. */ +- return 2378; ++ return 2406; + } + else + { +@@ -21970,7 +22278,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1001111xxxxxxxx0100x0xxxxxxxxxx + fmlsl. */ +- return 2382; ++ return 2410; + } + } + else +@@ -22476,7 +22784,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x0101111xxxxxxxx1000x0xxxxxxxxxx + fmlal2. */ +- return 2379; ++ return 2407; + } + else + { +@@ -22484,7 +22792,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1101111xxxxxxxx1000x0xxxxxxxxxx + fmlal2. */ +- return 2383; ++ return 2411; + } + } + } +@@ -22506,7 +22814,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x0101111xxxxxxxx1100x0xxxxxxxxxx + fmlsl2. */ +- return 2380; ++ return 2408; + } + else + { +@@ -22514,7 +22822,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1101111xxxxxxxx1100x0xxxxxxxxxx + fmlsl2. */ +- return 2384; ++ return 2412; + } + } + } +@@ -22570,7 +22878,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx001111xxxxxxxx1110x0xxxxxxxxxx + sdot. */ +- return 2351; ++ return 2379; + } + else + { +@@ -22578,7 +22886,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx101111xxxxxxxx1110x0xxxxxxxxxx + udot. */ +- return 2350; ++ return 2378; + } + } + } +@@ -22681,7 +22989,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx00111100xxxxxx1111x0xxxxxxxxxx + sudot. */ +- return 2428; ++ return 2456; + } + else + { +@@ -22689,7 +22997,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx00111110xxxxxx1111x0xxxxxxxxxx + usdot. */ +- return 2427; ++ return 2455; + } + } + else +@@ -22700,7 +23008,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx00111101xxxxxx1111x0xxxxxxxxxx + bfdot. */ +- return 2439; ++ return 2467; + } + else + { +@@ -22710,7 +23018,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x000111111xxxxxx1111x0xxxxxxxxxx + bfmlalb. */ +- return 2447; ++ return 2475; + } + else + { +@@ -22718,7 +23026,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x100111111xxxxxx1111x0xxxxxxxxxx + bfmlalt. */ +- return 2446; ++ return 2474; + } + } + } +@@ -23352,8 +23660,8 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode) + case 824: return NULL; /* fsqrt --> NULL. */ + case 832: value = 833; break; /* frintz --> frintz. */ + case 833: return NULL; /* frintz --> NULL. */ +- case 825: value = 2443; break; /* fcvt --> bfcvt. */ +- case 2443: return NULL; /* bfcvt --> NULL. */ ++ case 825: value = 2471; break; /* fcvt --> bfcvt. */ ++ case 2471: return NULL; /* bfcvt --> NULL. */ + case 834: value = 835; break; /* frinta --> frinta. */ + case 835: return NULL; /* frinta --> NULL. */ + case 836: value = 837; break; /* frintx --> frintx. */ +@@ -23854,6 +24162,9 @@ aarch64_extract_operand (const aarch64_operand *self, + case 198: + case 204: + case 207: ++ case 209: ++ case 210: ++ case 211: + return aarch64_ext_regno (self, info, code, inst, errors); + case 10: + return aarch64_ext_regrt_sysins (self, info, code, inst, errors); +@@ -23869,7 +24180,7 @@ aarch64_extract_operand (const aarch64_operand *self, + case 33: + case 34: + case 35: +- case 210: ++ case 213: + return aarch64_ext_reglane (self, info, code, inst, errors); + case 36: + return aarch64_ext_reglist (self, info, code, inst, errors); +@@ -23915,7 +24226,7 @@ aarch64_extract_operand (const aarch64_operand *self, + case 187: + case 188: + case 189: +- case 209: ++ case 212: + return aarch64_ext_imm (self, info, code, inst, errors); + case 44: + case 45: +diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c +index 820f6f11..cf1ce0b0 100644 +--- a/opcodes/aarch64-opc-2.c ++++ b/opcodes/aarch64-opc-2.c +@@ -233,6 +233,9 @@ const struct aarch64_operand aarch64_operands[] = + {AARCH64_OPND_CLASS_SVE_REG, "SVE_ZnxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "a list of SVE vector registers"}, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "an SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_ZtxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "a list of SVE vector registers"}, ++ {AARCH64_OPND_CLASS_SVE_REG, "SME_ZAda_2b", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZAda_2b}, "an SME ZA tile ZA0-ZA3"}, ++ {AARCH64_OPND_CLASS_SVE_REG, "SME_ZAda_3b", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZAda_3b}, "an SME ZA tile ZA0-ZA7"}, ++ {AARCH64_OPND_CLASS_PRED_REG, "SME_Pm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Pm}, "an SVE predicate register"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "TME_UIMM16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16}, "a 16-bit unsigned immediate for TME tcancel"}, + {AARCH64_OPND_CLASS_SIMD_ELEMENT, "SM3_IMM2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SM3_imm2}, "an indexed SM3 vector immediate"}, + {AARCH64_OPND_CLASS_NIL, "", 0, {0}, "DUMMY"}, +diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c +index dea4b8e6..8ced8e0d 100644 +--- a/opcodes/aarch64-opc.c ++++ b/opcodes/aarch64-opc.c +@@ -321,6 +321,9 @@ const aarch64_field fields[] = + { 19, 2 }, /* SVE_tszl_19: triangular size select low, bits [20,19]. */ + { 14, 1 }, /* SVE_xs_14: UXTW/SXTW select (bit 14). */ + { 22, 1 }, /* SVE_xs_22: UXTW/SXTW select (bit 22). */ ++ { 0, 2 }, /* SME ZAda tile ZA0-ZA3. */ ++ { 0, 3 }, /* SME ZAda tile ZA0-ZA7. */ ++ { 13, 3 }, /* SME Pm second source scalable predicate register P0-P7. */ + { 11, 2 }, /* rotate1: FCMLA immediate rotate. */ + { 13, 2 }, /* rotate2: Indexed element FCMLA immediate rotate. */ + { 12, 1 }, /* rotate3: FCADD immediate rotate. */ +@@ -3304,6 +3307,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, + case AARCH64_OPND_SVE_Pm: + case AARCH64_OPND_SVE_Pn: + case AARCH64_OPND_SVE_Pt: ++ case AARCH64_OPND_SME_Pm: + if (opnd->qualifier == AARCH64_OPND_QLF_NIL) + snprintf (buf, size, "p%d", opnd->reg.regno); + else if (opnd->qualifier == AARCH64_OPND_QLF_P_Z +@@ -3345,6 +3349,12 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, + opnd->reglane.index); + break; + ++ case AARCH64_OPND_SME_ZAda_2b: ++ case AARCH64_OPND_SME_ZAda_3b: ++ snprintf (buf, size, "za%d.%s", opnd->reg.regno, ++ aarch64_get_qualifier_name (opnd->qualifier)); ++ break; ++ + case AARCH64_OPND_CRn: + case AARCH64_OPND_CRm: + snprintf (buf, size, "C%" PRIi64, opnd->imm.value); +@@ -5277,6 +5287,7 @@ verify_constraints (const struct aarch64_inst *inst, + case AARCH64_OPND_SVE_Pm: + case AARCH64_OPND_SVE_Pn: + case AARCH64_OPND_SVE_Pt: ++ case AARCH64_OPND_SME_Pm: + inst_pred = inst_op; + inst_pred_idx = i; + break; +diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h +index a4a2b6f2..ba19c12c 100644 +--- a/opcodes/aarch64-opc.h ++++ b/opcodes/aarch64-opc.h +@@ -150,6 +150,9 @@ enum aarch64_field_kind + FLD_SVE_tszl_19, + FLD_SVE_xs_14, + FLD_SVE_xs_22, ++ FLD_SME_ZAda_2b, ++ FLD_SME_ZAda_3b, ++ FLD_SME_Pm, + FLD_rotate1, + FLD_rotate2, + FLD_rotate3, +diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h +index d63b0810..f725f2f0 100644 +--- a/opcodes/aarch64-tbl.h ++++ b/opcodes/aarch64-tbl.h +@@ -2168,6 +2168,42 @@ + { \ + QLF3(X,X,NIL), \ + } ++/* e.g. ADDVA .S, /M, /M, .S */ ++#define OP_SME_ZADA_PN_PM_ZN_S \ ++{ \ ++ QLF4(S_S,P_M,P_M,S_S), \ ++} ++/* e.g. ADDVA .D, /M, /M, .D */ ++#define OP_SME_ZADA_PN_PM_ZN_D \ ++{ \ ++ QLF4(S_D,P_M,P_M,S_D), \ ++} ++/* e.g. BFMOPA .S, /M, /M, .H, .H */ ++#define OP_SME_ZADA_PN_PM_ZN_ZM \ ++{ \ ++ QLF5(S_S,P_M,P_M,S_H,S_H), \ ++} ++#define OP_SME_ZADA_S_PM_PM_S_S \ ++{ \ ++ QLF5(S_S,P_M,P_M,S_S,S_S) \ ++} ++#define OP_SME_ZADA_D_PM_PM_D_D \ ++{ \ ++ QLF5(S_D,P_M,P_M,S_D,S_D) \ ++} ++#define OP_SME_ZADA_S_PM_PM_H_H \ ++{ \ ++ QLF5(S_S,P_M,P_M,S_H,S_H) \ ++} ++#define OP_SME_ZADA_S_PM_PM_B_B \ ++{ \ ++ QLF5(S_S,P_M,P_M,S_B,S_B) \ ++} ++#define OP_SME_ZADA_D_PM_PM_H_H \ ++{ \ ++ QLF5(S_D,P_M,P_M,S_H,S_H) \ ++} ++ + /* e.g. UDOT .2S, .8B, .8B. */ + #define QL_V3DOT \ + { \ +@@ -2564,6 +2600,18 @@ static const aarch64_feature_set aarch64_feature_flagm = + #define SVE2SM4_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ + { NAME, OPCODE, MASK, CLASS, OP, SVE2_SM4, OPS, QUALS, \ + FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL } ++#define SME_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ ++ { NAME, OPCODE, MASK, CLASS, OP, SME, OPS, QUALS, \ ++ FLAGS, 0, TIED, NULL } ++#define SME_F64_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ ++ { NAME, OPCODE, MASK, CLASS, OP, SME_F64, OPS, QUALS, \ ++ FLAGS, 0, TIED, NULL } ++#define SME_I64_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ ++ { NAME, OPCODE, MASK, CLASS, OP, SME_I64, OPS, QUALS, \ ++ FLAGS, 0, TIED, NULL } ++#define SME_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ ++ { NAME, OPCODE, MASK, CLASS, OP, SME, OPS, QUALS, \ ++ FLAGS, CONSTRAINTS, TIED, NULL } + #define SVE2BITPERM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ + { NAME, OPCODE, MASK, CLASS, OP, SVE2_BITPERM, OPS, QUALS, \ + FLAGS | F_STRICT, 0, TIED, NULL } +@@ -5045,6 +5093,35 @@ const struct aarch64_opcode aarch64_opcode_table[] = + SVE2BITPERM_INSN ("bdep", 0x4500b400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), + SVE2BITPERM_INSN ("bext", 0x4500b000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), + SVE2BITPERM_INSN ("bgrp", 0x4500b800, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), ++ /* SME instructions. */ ++ SME_INSN ("addha", 0xc0900000, 0xffff001c, sme_misc, 0, OP4 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn), OP_SME_ZADA_PN_PM_ZN_S, 0, 0), ++ SME_I64_INSN ("addha", 0xc0d00000, 0xffff0018, sme_misc, 0, OP4 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn), OP_SME_ZADA_PN_PM_ZN_D, 0, 0), ++ SME_INSN ("addva", 0xc0910000, 0xffff001c, sme_misc, 0, OP4 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn), OP_SME_ZADA_PN_PM_ZN_S, 0, 0), ++ SME_I64_INSN ("addva", 0xc0d10000, 0xffff0018, sme_misc, 0, OP4 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn), OP_SME_ZADA_PN_PM_ZN_D, 0, 0), ++ SME_INSN ("bfmopa", 0x81800000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_PN_PM_ZN_ZM, 0, 0), ++ SME_INSN ("bfmops", 0x81800010, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_PN_PM_ZN_ZM, 0, 0), ++ SME_INSN ("fmopa", 0x80800000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_S_S, 0, 0), ++ SME_F64_INSN ("fmopa", 0x80c00000, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_D_D, 0, 0), ++ SME_INSN ("fmopa", 0x81a00000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_H_H, 0, 0), ++ SME_INSN ("fmops", 0x80800010, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_S_S, 0, 0), ++ SME_F64_INSN ("fmops", 0x80c00010, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_D_D, 0, 0), ++ SME_INSN ("fmops", 0x81a00010, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_H_H, 0, 0), ++ SME_INSN ("smopa", 0xa0800000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_B_B, 0, 0), ++ SME_I64_INSN ("smopa", 0xa0c00000, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_H_H, 0, 0), ++ SME_INSN ("smops", 0xa0800010, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_B_B, 0, 0), ++ SME_I64_INSN ("smops", 0xa0c00010, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_H_H, 0, 0), ++ SME_INSN ("sumopa", 0xa0a00000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_B_B, 0, 0), ++ SME_I64_INSN ("sumopa", 0xa0e00000, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_H_H, 0, 0), ++ SME_INSN ("sumops", 0xa0a00010 ,0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_B_B, 0, 0), ++ SME_I64_INSN ("sumops", 0xa0e00010 ,0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_H_H, 0, 0), ++ SME_INSN ("umopa", 0xa1a00000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_B_B, 0, 0), ++ SME_I64_INSN ("umopa", 0xa1e00000, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_H_H, 0, 0), ++ SME_INSN ("umops", 0xa1a00010 ,0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_B_B, 0, 0), ++ SME_I64_INSN ("umops", 0xa1e00010 ,0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_H_H, 0, 0), ++ SME_INSN ("usmopa", 0xa1800000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_B_B, 0, 0), ++ SME_I64_INSN ("usmopa", 0xa1c00000, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_H_H, 0, 0), ++ SME_INSN ("usmops", 0xa1800010, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_B_B, 0, 0), ++ SME_I64_INSN ("usmops", 0xa1c00010, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_H_H, 0, 0), + + /* SIMD Dot Product (optional in v8.2-A). */ + DOT_INSN ("udot", 0x2e009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ), +@@ -5613,6 +5690,12 @@ const struct aarch64_opcode aarch64_opcode_table[] = + "an SVE vector register") \ + Y(SVE_REG, sve_reglist, "SVE_ZtxN", 0, F(FLD_SVE_Zt), \ + "a list of SVE vector registers") \ ++ Y(SVE_REG, regno, "SME_ZAda_2b", 0, F(FLD_SME_ZAda_2b), \ ++ "an SME ZA tile ZA0-ZA3") \ ++ Y(SVE_REG, regno, "SME_ZAda_3b", 0, F(FLD_SME_ZAda_3b), \ ++ "an SME ZA tile ZA0-ZA7") \ ++ Y(PRED_REG, regno, "SME_Pm", 0, F(FLD_SME_Pm), \ ++ "an SVE predicate register") \ + Y(IMMEDIATE, imm, "TME_UIMM16", 0, F(FLD_imm16), \ + "a 16-bit unsigned immediate for TME tcancel") \ + Y(SIMD_ELEMENT, reglane, "SM3_IMM2", 0, F(FLD_SM3_imm2), \ +-- +2.19.1 + diff --git a/SME-0003-aarch64-SME-Add-MOV-and-MOVA-instructions.patch b/SME-0003-aarch64-SME-Add-MOV-and-MOVA-instructions.patch new file mode 100644 index 0000000000000000000000000000000000000000..7943d2d605fab7e5d546c44f3d9212ed2bef0094 --- /dev/null +++ b/SME-0003-aarch64-SME-Add-MOV-and-MOVA-instructions.patch @@ -0,0 +1,2348 @@ +From 26b45a4793c0e6b7262dd539bd209b8294ff998c Mon Sep 17 00:00:00 2001 +From: Przemyslaw Wirkus +Date: Wed, 17 Nov 2021 19:31:25 +0000 +Subject: [PATCH 03/10] aarch64: [SME] Add MOV and MOVA instructions + +Reference: https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=7bb5f07c8aa5168009f1e7b6857a30f0ee5ad16a + +This patch is adding new MOV (alias) and MOVA SME instruction. + +gas/ChangeLog: + + * config/tc-aarch64.c (enum sme_hv_slice): new enum. + (struct reloc_entry): Added ZAH and ZAV registers. + (parse_sme_immediate): Immediate parser. + (parse_sme_za_hv_tiles_operand): ZA tile parser. + (parse_sme_za_hv_tiles_operand_index): Index parser. + (parse_operands): Added ZA tile parser calls. + (REGNUMS): New macro. Regs with suffix. + (REGSET16S): New macro. 16 regs with suffix. + * testsuite/gas/aarch64/sme-2-illegal.d: New test. + * testsuite/gas/aarch64/sme-2-illegal.l: New test. + * testsuite/gas/aarch64/sme-2-illegal.s: New test. + * testsuite/gas/aarch64/sme-2.d: New test. + * testsuite/gas/aarch64/sme-2.s: New test. + * testsuite/gas/aarch64/sme-2a.d: New test. + * testsuite/gas/aarch64/sme-2a.s: New test. + * testsuite/gas/aarch64/sme-3-illegal.d: New test. + * testsuite/gas/aarch64/sme-3-illegal.l: New test. + * testsuite/gas/aarch64/sme-3-illegal.s: New test. + * testsuite/gas/aarch64/sme-3.d: New test. + * testsuite/gas/aarch64/sme-3.s: New test. + * testsuite/gas/aarch64/sme-3a.d: New test. + * testsuite/gas/aarch64/sme-3a.s: New test. + +include/ChangeLog: + + * opcode/aarch64.h (enum aarch64_opnd): New enums + AARCH64_OPND_SME_ZA_HV_idx_src and + AARCH64_OPND_SME_ZA_HV_idx_dest. + (struct aarch64_opnd_info): New ZA tile vector struct. + +opcodes/ChangeLog: + + * aarch64-asm.c (aarch64_ins_sme_za_hv_tiles): + New inserter. + * aarch64-asm.h (AARCH64_DECL_OPD_INSERTER): + New inserter ins_sme_za_hv_tiles. + * aarch64-dis.c (aarch64_ext_sme_za_hv_tiles): + New extractor. + * aarch64-dis.h (AARCH64_DECL_OPD_EXTRACTOR): + New extractor ext_sme_za_hv_tiles. + * aarch64-opc.c (aarch64_print_operand): + Handle SME_ZA_HV_idx_src and SME_ZA_HV_idx_dest. + * aarch64-opc.h (enum aarch64_field_kind): New enums + FLD_SME_size_10, FLD_SME_Q, FLD_SME_V and FLD_SME_Rv. + (struct aarch64_operand): Increase fields size to 5. + * aarch64-tbl.h (OP_SME_BHSDQ_PM_BHSDQ): New qualifiers + aarch64-asm-2.c: Regenerate. + aarch64-dis-2.c: Regenerate. + aarch64-opc-2.c: Regenerate. +--- + gas/config/tc-aarch64.c | 219 ++++++++++++- + gas/testsuite/gas/aarch64/sme-2-illegal.d | 3 + + gas/testsuite/gas/aarch64/sme-2-illegal.l | 27 ++ + gas/testsuite/gas/aarch64/sme-2-illegal.s | 32 ++ + gas/testsuite/gas/aarch64/sme-2.d | 43 +++ + gas/testsuite/gas/aarch64/sme-2.s | 52 +++ + gas/testsuite/gas/aarch64/sme-2a.d | 29 ++ + gas/testsuite/gas/aarch64/sme-2a.s | 26 ++ + gas/testsuite/gas/aarch64/sme-3-illegal.d | 3 + + gas/testsuite/gas/aarch64/sme-3-illegal.l | 11 + + gas/testsuite/gas/aarch64/sme-3-illegal.s | 14 + + gas/testsuite/gas/aarch64/sme-3.d | 31 ++ + gas/testsuite/gas/aarch64/sme-3.s | 31 ++ + gas/testsuite/gas/aarch64/sme-3a.d | 29 ++ + gas/testsuite/gas/aarch64/sme-3a.s | 26 ++ + include/opcode/aarch64.h | 14 + + opcodes/aarch64-asm-2.c | 9 +- + opcodes/aarch64-asm.c | 55 ++++ + opcodes/aarch64-asm.h | 1 + + opcodes/aarch64-dis-2.c | 371 ++++++++++++---------- + opcodes/aarch64-dis.c | 58 ++++ + opcodes/aarch64-dis.h | 1 + + opcodes/aarch64-opc-2.c | 2 + + opcodes/aarch64-opc.c | 15 + + opcodes/aarch64-opc.h | 7 +- + opcodes/aarch64-tbl.h | 19 ++ + 26 files changed, 952 insertions(+), 176 deletions(-) + create mode 100644 gas/testsuite/gas/aarch64/sme-2-illegal.d + create mode 100644 gas/testsuite/gas/aarch64/sme-2-illegal.l + create mode 100644 gas/testsuite/gas/aarch64/sme-2-illegal.s + create mode 100644 gas/testsuite/gas/aarch64/sme-2.d + create mode 100644 gas/testsuite/gas/aarch64/sme-2.s + create mode 100644 gas/testsuite/gas/aarch64/sme-2a.d + create mode 100644 gas/testsuite/gas/aarch64/sme-2a.s + create mode 100644 gas/testsuite/gas/aarch64/sme-3-illegal.d + create mode 100644 gas/testsuite/gas/aarch64/sme-3-illegal.l + create mode 100644 gas/testsuite/gas/aarch64/sme-3-illegal.s + create mode 100644 gas/testsuite/gas/aarch64/sme-3.d + create mode 100644 gas/testsuite/gas/aarch64/sme-3.s + create mode 100644 gas/testsuite/gas/aarch64/sme-3a.d + create mode 100644 gas/testsuite/gas/aarch64/sme-3a.s + +diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c +index 912dac67..bb618b8d 100644 +--- a/gas/config/tc-aarch64.c ++++ b/gas/config/tc-aarch64.c +@@ -99,6 +99,17 @@ enum vector_el_type + NT_merge + }; + ++/* SME horizontal or vertical slice indicator, encoded in "V". ++ Values: ++ 0 - Horizontal ++ 1 - vertical ++*/ ++enum sme_hv_slice ++{ ++ HV_horizontal = 0, ++ HV_vertical = 1 ++}; ++ + /* Bits for DEFINED field in vector_type_el. */ + #define NTA_HASTYPE 1 + #define NTA_HASINDEX 2 +@@ -279,6 +290,8 @@ struct reloc_entry + BASIC_REG_TYPE(ZN) /* z[0-31] */ \ + BASIC_REG_TYPE(PN) /* p[0-15] */ \ + BASIC_REG_TYPE(ZA) /* za[0-15] */ \ ++ BASIC_REG_TYPE(ZAH) /* za[0-15]h */ \ ++ BASIC_REG_TYPE(ZAV) /* za[0-15]v */ \ + /* Typecheck: any 64-bit int reg (inc SP exc XZR). */ \ + MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \ + /* Typecheck: same, plus SVE registers. */ \ +@@ -4324,6 +4337,178 @@ parse_sme_zada_operand (char **str, aarch64_opnd_qualifier_t *qualifier) + return regno; + } + ++/* Parse STR for unsigned, immediate (1-2 digits) in format: ++ ++ # ++ ++ ++ Function return TRUE if immediate was found, or FALSE. ++*/ ++static bool ++parse_sme_immediate (char **str, int64_t *imm) ++{ ++ int64_t val; ++ if (! parse_constant_immediate (str, &val, REG_TYPE_R_N)) ++ return false; ++ ++ *imm = val; ++ return true; ++} ++ ++/* Parse index with vector select register and immediate: ++ ++ [, ] ++ [, #] ++ where is in W12-W15 range and # is optional for immediate. ++ ++ Function performs extra check for mandatory immediate value if REQUIRE_IMM ++ is set to true. ++ ++ On success function returns TRUE and populated VECTOR_SELECT_REGISTER and ++ IMM output. ++*/ ++static bool ++parse_sme_za_hv_tiles_operand_index (char **str, ++ int *vector_select_register, ++ int64_t *imm) ++{ ++ const reg_entry *reg; ++ ++ if (!skip_past_char (str, '[')) ++ { ++ set_syntax_error (_("expected '['")); ++ return false; ++ } ++ ++ /* Vector select register W12-W15 encoded in the 2-bit Rv field. */ ++ reg = parse_reg (str); ++ if (reg == NULL || reg->type != REG_TYPE_R_32 ++ || reg->number < 12 || reg->number > 15) ++ { ++ set_syntax_error (_("expected vector select register W12-W15")); ++ return false; ++ } ++ *vector_select_register = reg->number; ++ ++ if (!skip_past_char (str, ',')) /* Optional index offset immediate. */ ++ { ++ set_syntax_error (_("expected ','")); ++ return false; ++ } ++ ++ if (!parse_sme_immediate (str, imm)) ++ { ++ set_syntax_error (_("index offset immediate expected")); ++ return false; ++ } ++ ++ if (!skip_past_char (str, ']')) ++ { ++ set_syntax_error (_("expected ']'")); ++ return false; ++ } ++ ++ return true; ++} ++ ++/* Parse SME ZA horizontal or vertical vector access to tiles. ++ Function extracts from STR to SLICE_INDICATOR horizontal (0) or ++ vertical (1) ZA tile vector orientation. VECTOR_SELECT_REGISTER ++ contains select register and corresponding optional IMMEDIATE. ++ In addition QUALIFIER is extracted. ++ ++ Field format examples: ++ ++ ZA0.B[, #] ++ .H[, #] ++ .S[, #] ++ .D[, #] ++ .Q[, #] ++ ++ Function returns register number or PARSE_FAIL. ++*/ ++static int ++parse_sme_za_hv_tiles_operand (char **str, ++ enum sme_hv_slice *slice_indicator, ++ int *vector_select_register, ++ int *imm, ++ aarch64_opnd_qualifier_t *qualifier) ++{ ++ char *qh, *qv; ++ int regno; ++ int regno_limit; ++ int64_t imm_limit; ++ int64_t imm_value; ++ const reg_entry *reg; ++ ++ qh = qv = *str; ++ if ((reg = parse_reg_with_qual (&qh, REG_TYPE_ZAH, qualifier)) != NULL) ++ { ++ *slice_indicator = HV_horizontal; ++ *str = qh; ++ } ++ else if ((reg = parse_reg_with_qual (&qv, REG_TYPE_ZAV, qualifier)) != NULL) ++ { ++ *slice_indicator = HV_vertical; ++ *str = qv; ++ } ++ else ++ return PARSE_FAIL; ++ regno = reg->number; ++ ++ switch (*qualifier) ++ { ++ case AARCH64_OPND_QLF_S_B: ++ regno_limit = 0; ++ imm_limit = 15; ++ break; ++ case AARCH64_OPND_QLF_S_H: ++ regno_limit = 1; ++ imm_limit = 7; ++ break; ++ case AARCH64_OPND_QLF_S_S: ++ regno_limit = 3; ++ imm_limit = 3; ++ break; ++ case AARCH64_OPND_QLF_S_D: ++ regno_limit = 7; ++ imm_limit = 1; ++ break; ++ case AARCH64_OPND_QLF_S_Q: ++ regno_limit = 15; ++ imm_limit = 0; ++ break; ++ default: ++ set_syntax_error (_("invalid ZA tile element size, allowed b, h, s, d and q")); ++ return PARSE_FAIL; ++ } ++ ++ /* Check if destination register ZA tile vector is in range for given ++ instruction variant. */ ++ if (regno < 0 || regno > regno_limit) ++ { ++ set_syntax_error (_("ZA tile vector out of range")); ++ return PARSE_FAIL; ++ } ++ ++ if (!parse_sme_za_hv_tiles_operand_index (str, vector_select_register, ++ &imm_value)) ++ return PARSE_FAIL; ++ ++ /* Check if optional index offset is in the range for instruction ++ variant. */ ++ if (imm_value < 0 || imm_value > imm_limit) ++ { ++ set_syntax_error (_("index offset out of range")); ++ return PARSE_FAIL; ++ } ++ ++ *imm = imm_value; ++ ++ return regno; ++} ++ ++ + /* Parse a system register or a PSTATE field name for an MSR/MRS instruction. + Returns the encoding for the option, or PARSE_FAIL. + +@@ -7037,6 +7222,26 @@ parse_operands (char *str, const aarch64_opcode *opcode) + info->qualifier = qualifier; + break; + ++ case AARCH64_OPND_SME_ZA_HV_idx_src: ++ case AARCH64_OPND_SME_ZA_HV_idx_dest: ++ { ++ enum sme_hv_slice vector_indicator; ++ int vector_select_register; ++ int imm; ++ val = parse_sme_za_hv_tiles_operand (&str, &vector_indicator, ++ &vector_select_register, ++ &imm, ++ &qualifier); ++ if (val == PARSE_FAIL) ++ goto failure; ++ info->za_tile_vector.regno = val; ++ info->za_tile_vector.index.regno = vector_select_register; ++ info->za_tile_vector.index.imm = imm; ++ info->za_tile_vector.v = vector_indicator; ++ info->qualifier = qualifier; ++ break; ++ } ++ + default: + as_fatal (_("unhandled operand code %d"), operands[i]); + } +@@ -7581,11 +7786,17 @@ aarch64_canonicalize_symbol_name (char *name) + #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, true } + #define REGDEF_ALIAS(s, n, t) { #s, n, REG_TYPE_##t, false} + #define REGNUM(p,n,t) REGDEF(p##n, n, t) ++#define REGNUMS(p,n,s,t) REGDEF(p##n##s, n, t) + #define REGSET16(p,t) \ + REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \ + REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \ + REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \ + REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t) ++#define REGSET16S(p,s,t) \ ++ REGNUMS(p, 0,s,t), REGNUMS(p, 1,s,t), REGNUMS(p, 2,s,t), REGNUMS(p, 3,s,t), \ ++ REGNUMS(p, 4,s,t), REGNUMS(p, 5,s,t), REGNUMS(p, 6,s,t), REGNUMS(p, 7,s,t), \ ++ REGNUMS(p, 8,s,t), REGNUMS(p, 9,s,t), REGNUMS(p,10,s,t), REGNUMS(p,11,s,t), \ ++ REGNUMS(p,12,s,t), REGNUMS(p,13,s,t), REGNUMS(p,14,s,t), REGNUMS(p,15,s,t) + #define REGSET31(p,t) \ + REGSET16(p, t), \ + REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \ +@@ -7636,7 +7847,13 @@ static const reg_entry reg_names[] = { + REGSET16 (p, PN), REGSET16 (P, PN), + + /* SME ZA tile registers. */ +- REGSET16 (za, ZA), REGSET16 (ZA, ZA) ++ REGSET16 (za, ZA), REGSET16 (ZA, ZA), ++ ++ /* SME ZA tile registers (horizontal slice). */ ++ REGSET16S (za, h, ZAH), REGSET16S (ZA, H, ZAH), ++ ++ /* SME ZA tile registers (vertical slice). */ ++ REGSET16S (za, v, ZAV), REGSET16S (ZA, V, ZAV) + }; + + #undef REGDEF +diff --git a/gas/testsuite/gas/aarch64/sme-2-illegal.d b/gas/testsuite/gas/aarch64/sme-2-illegal.d +new file mode 100644 +index 00000000..0ff10535 +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/sme-2-illegal.d +@@ -0,0 +1,3 @@ ++#as: -march=armv8-a+sme ++#source: sme-2-illegal.s ++#error_output: sme-2-illegal.l +diff --git a/gas/testsuite/gas/aarch64/sme-2-illegal.l b/gas/testsuite/gas/aarch64/sme-2-illegal.l +new file mode 100644 +index 00000000..d3645617 +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/sme-2-illegal.l +@@ -0,0 +1,27 @@ ++[^:]*: Assembler messages: ++[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 3 -- `mova z0\.b,p0/m,za1h\.b\[w12,#0\]' ++[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 3 -- `mova z0\.h,p0/m,za2h\.h\[w12,#0\]' ++[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 3 -- `mova z0\.s,p0/m,za4h\.s\[w12,#0\]' ++[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 3 -- `mova z0\.d,p0/m,za8h\.d\[w12,#0\]' ++[^:]*:[0-9]+: Error: operand 3 must be an SME horizontal or vertical vector access register -- `mova z0\.q,p0/m,za16h.q\[w12\]' ++[^:]*:[0-9]+: Error: index offset out of range at operand 3 -- `mova z31\.b,p7/m,za0v\.b\[w15,#16\]' ++[^:]*:[0-9]+: Error: index offset out of range at operand 3 -- `mova z31\.h,p7/m,za1v\.h\[w15,#8\]' ++[^:]*:[0-9]+: Error: index offset out of range at operand 3 -- `mova z31\.s,p7/m,za3v\.s\[w15,#4\]' ++[^:]*:[0-9]+: Error: index offset out of range at operand 3 -- `mova z31\.d,p7/m,za7v\.d\[w15,#2\]' ++[^:]*:[0-9]+: Error: index offset out of range at operand 3 -- `mova z31\.q,p7/m,za15v\.q\[w15,#1\]' ++[^:]*:[0-9]+: Error: expected ',' at operand 3 -- `mova z31\.q,p7/m,za15v\.q\[w15\]' ++[^:]*:[0-9]+: Error: expected '\[' at operand 3 -- `mova z0\.b,p0/m,za0v.b' ++[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `mova z31\.b,p7/m,za0v\.b\[15,w15\]' ++[^:]*:[0-9]+: Error: expected ',' at operand 3 -- `mova z0\.h,p0/m,za0v\.h\[w12\. 0\]' ++[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `mova z0\.s,p0/m,za0v\.s\[x12,0]' ++[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `mova z0\.d,p0/m,za0v\.d\[w21,0\]' ++[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `mova z0\.q,p0/m,za0v\.q\[s12\]' ++[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `mova z0\.q,p0/m,za0v\.q\[d12\]' ++[^:]*:[0-9]+: Error: index offset immediate expected at operand 3 -- `mova z0.q,p0/m,za0v\.q\[w12,\]' ++[^:]*:[0-9]+: Error: expected ',' at operand 3 -- `mova z0\.q,p0/m,za0v\.q\[w12\.\]' ++[^:]*:[0-9]+: Error: index offset immediate expected at operand 3 -- `mova z0\.q,p0/m,za0v\.q\[w12,abc\]' ++[^:]*:[0-9]+: Error: index offset immediate expected at operand 3 -- `mova z0\.q,p0/m,za0v\.q\[w12,#abc\]' ++[^:]*:[0-9]+: Error: expected '\]' at operand 3 -- `mova z0\.q,p0/m,za0v\.q\[w12,1a\]' ++[^:]*:[0-9]+: Error: expected '\]' at operand 3 -- `mova z0\.q,p0/m,za0v\.q\[w12,#1a\]' ++[^:]*:[0-9]+: Error: expected '\]' at operand 3 -- `mova z0\.q,p0/m,za0v\.q\[w12,1a2\]' ++[^:]*:[0-9]+: Error: expected '\]' at operand 3 -- `mova z0\.q,p0/m,za0v\.q\[w12,#1a2\]' +diff --git a/gas/testsuite/gas/aarch64/sme-2-illegal.s b/gas/testsuite/gas/aarch64/sme-2-illegal.s +new file mode 100644 +index 00000000..28eb6719 +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/sme-2-illegal.s +@@ -0,0 +1,32 @@ ++/* Scalable Matrix Extension (SME). */ ++ ++/* MOVA (tile to vector) variant. */ ++mova z0.b, p0/m, za1h.b[w12, #0] ++mova z0.h, p0/m, za2h.h[w12, #0] ++mova z0.s, p0/m, za4h.s[w12, #0] ++mova z0.d, p0/m, za8h.d[w12, #0] ++mova z0.q, p0/m, za16h.q[w12] ++ ++mova z31.b, p7/m, za0v.b[w15, #16] ++mova z31.h, p7/m, za1v.h[w15, #8] ++mova z31.s, p7/m, za3v.s[w15, #4] ++mova z31.d, p7/m, za7v.d[w15, #2] ++mova z31.q, p7/m, za15v.q[w15, #1] ++mova z31.q, p7/m, za15v.q[w15] ++ ++/* Syntax issues. */ ++mova z0.b, p0/m, za0v.b ++mova z31.b, p7/m, za0v.b[15, w15] ++mova z0.h, p0/m, za0v.h[w12. 0] ++mova z0.s, p0/m, za0v.s[x12, 0] ++mova z0.d, p0/m, za0v.d[w21, 0] ++mova z0.q, p0/m, za0v.q[s12] ++mova z0.q, p0/m, za0v.q[d12] ++mova z0.q, p0/m, za0v.q[w12,] ++mova z0.q, p0/m, za0v.q[w12.] ++mova z0.q, p0/m, za0v.q[w12, abc] ++mova z0.q, p0/m, za0v.q[w12, #abc] ++mova z0.q, p0/m, za0v.q[w12, 1a] ++mova z0.q, p0/m, za0v.q[w12, #1a] ++mova z0.q, p0/m, za0v.q[w12, 1a2] ++mova z0.q, p0/m, za0v.q[w12, #1a2] +diff --git a/gas/testsuite/gas/aarch64/sme-2.d b/gas/testsuite/gas/aarch64/sme-2.d +new file mode 100644 +index 00000000..2764aac8 +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/sme-2.d +@@ -0,0 +1,43 @@ ++#name: SME extension, MOVA (tile to vector) ++#as: -march=armv8-a+sme ++#objdump: -dr ++ ++.*: file format .* ++ ++Disassembly of section \.text: ++ ++0+ <.*>: ++ 0: c0028000 mov z0.b, p0/m, za0v.b\[w12, 0\] ++ 4: c0428000 mov z0.h, p0/m, za0v.h\[w12, 0\] ++ 8: c0828000 mov z0.s, p0/m, za0v.s\[w12, 0\] ++ c: c0c28000 mov z0.d, p0/m, za0v.d\[w12, 0\] ++ 10: c0c38000 mov z0.q, p0/m, za0v.q\[w12, 0\] ++ 14: c002fdff mov z31.b, p7/m, za0v.b\[w15, 15\] ++ 18: c042fdff mov z31.h, p7/m, za1v.h\[w15, 7\] ++ 1c: c082fdff mov z31.s, p7/m, za3v.s\[w15, 3\] ++ 20: c0c2fdff mov z31.d, p7/m, za7v.d\[w15, 1\] ++ 24: c0c3fdff mov z31.q, p7/m, za15v.q\[w15, 0\] ++ 28: c0020000 mov z0.b, p0/m, za0h.b\[w12, 0\] ++ 2c: c0420000 mov z0.h, p0/m, za0h.h\[w12, 0\] ++ 30: c0820000 mov z0.s, p0/m, za0h.s\[w12, 0\] ++ 34: c0c20000 mov z0.d, p0/m, za0h.d\[w12, 0\] ++ 38: c0c30000 mov z0.q, p0/m, za0h.q\[w12, 0\] ++ 3c: c0027dff mov z31.b, p7/m, za0h.b\[w15, 15\] ++ 40: c0427dff mov z31.h, p7/m, za1h.h\[w15, 7\] ++ 44: c0827dff mov z31.s, p7/m, za3h.s\[w15, 3\] ++ 48: c0c27dff mov z31.d, p7/m, za7h.d\[w15, 1\] ++ 4c: c0c37dff mov z31.q, p7/m, za15h.q\[w15, 0\] ++ 50: c0027dff mov z31.b, p7/m, za0h.b\[w15, 15\] ++ 54: c0427dff mov z31.h, p7/m, za1h.h\[w15, 7\] ++ 58: c0827dff mov z31.s, p7/m, za3h.s\[w15, 3\] ++ 5c: c0c27dff mov z31.d, p7/m, za7h.d\[w15, 1\] ++ 60: c0c37dff mov z31.q, p7/m, za15h.q\[w15, 0\] ++ 64: c0027dff mov z31.b, p7/m, za0h.b\[w15, 15\] ++ 68: c0427dff mov z31.h, p7/m, za1h.h\[w15, 7\] ++ 6c: c0827dff mov z31.s, p7/m, za3h.s\[w15, 3\] ++ 70: c0c27dff mov z31.d, p7/m, za7h.d\[w15, 1\] ++ 74: c0c37dff mov z31.q, p7/m, za15h.q\[w15, 0\] ++ 78: c0c27dff mov z31.d, p7/m, za7h.d\[w15, 1\] ++ 7c: c0c37dff mov z31.q, p7/m, za15h.q\[w15, 0\] ++ 80: c002a400 mov z0.b, p1/m, za0v.b\[w13, 0\] ++ 84: c002a4e0 mov z0.b, p1/m, za0v.b\[w13, 7\] +diff --git a/gas/testsuite/gas/aarch64/sme-2.s b/gas/testsuite/gas/aarch64/sme-2.s +new file mode 100644 +index 00000000..a2d0f0a6 +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/sme-2.s +@@ -0,0 +1,52 @@ ++/* Scalable Matrix Extension (SME). */ ++ ++/* MOVA (tile to vector) variant. */ ++mova z0.b, p0/m, za0v.b[w12, 0] ++mova z0.h, p0/m, za0v.h[w12, 0] ++mova z0.s, p0/m, za0v.s[w12, 0] ++mova z0.d, p0/m, za0v.d[w12, 0] ++mova z0.q, p0/m, za0v.q[w12, 0] ++ ++mova z31.b, p7/m, za0v.b[w15, 15] ++mova z31.h, p7/m, za1v.h[w15, 7] ++mova z31.s, p7/m, za3v.s[w15, 3] ++mova z31.d, p7/m, za7v.d[w15, 1] ++mova z31.q, p7/m, za15v.q[w15, 0] ++ ++mova z0.b, p0/m, za0h.b[w12, 0] ++mova z0.h, p0/m, za0h.h[w12, 0] ++mova z0.s, p0/m, za0h.s[w12, 0] ++mova z0.d, p0/m, za0h.d[w12, 0] ++mova z0.q, p0/m, za0h.q[w12, 0] ++ ++mova z31.b, p7/m, za0h.b[w15, 15] ++mova z31.h, p7/m, za1h.h[w15, 7] ++mova z31.s, p7/m, za3h.s[w15, 3] ++mova z31.d, p7/m, za7h.d[w15, 1] ++mova z31.q, p7/m, za15h.q[w15, 0] ++ ++/* Parser checks. */ ++mova z31.b , p7/m , za0h.b [ w15 , 15 ] ++mova z31.h , p7/m , za1h.h [ w15 , 7 ] ++mova z31.s , p7/m , za3h.s [ w15 , 3 ] ++mova z31.d , p7/m , za7h.d [ w15 , 1 ] ++mova z31.q , p7/m , za15h.q [ w15 , #0 ] ++mova z31.b , p7/m , za0h.b [ w15 , #15 ] ++mova z31.h , p7/m , za1h.h [ w15 , #7 ] ++mova z31.s , p7/m , za3h.s [ w15 , #3 ] ++mova z31.d , p7/m , za7h.d [ w15 , #1 ] ++mova z31.q , p7/m , za15h.q [ w15, #0 ] ++ ++/* Register aliases. */ ++foo .req w15 ++bar .req za7h ++baz .req z31 ++ ++mova z31.d , p7/m , bar.d [ foo , #1 ] ++mova baz.q , p7/m , za15h.q [ foo , #0 ] ++ ++/* Named immediate. */ ++val_zero = 0 ++val_seven = 7 ++mova z0.b, p1/m, za0v.b[w13, #val_zero] ++mova z0.b, p1/m, za0v.b[w13, #val_seven] +diff --git a/gas/testsuite/gas/aarch64/sme-2a.d b/gas/testsuite/gas/aarch64/sme-2a.d +new file mode 100644 +index 00000000..9515e3fc +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/sme-2a.d +@@ -0,0 +1,29 @@ ++#name: SME extension, MOV (tile to vector) ++#as: -march=armv8-a+sme ++#objdump: -dr ++ ++.*: file format .* ++ ++Disassembly of section \.text: ++ ++0+ <.*>: ++ 0: c0028000 mov z0\.b, p0/m, za0v\.b\[w12, 0\] ++ 4: c0428000 mov z0\.h, p0/m, za0v\.h\[w12, 0\] ++ 8: c0828000 mov z0\.s, p0/m, za0v\.s\[w12, 0\] ++ c: c0c28000 mov z0\.d, p0/m, za0v\.d\[w12, 0\] ++ 10: c0c38000 mov z0\.q, p0/m, za0v\.q\[w12, 0\] ++ 14: c002fdff mov z31\.b, p7/m, za0v\.b\[w15, 15\] ++ 18: c042fdff mov z31\.h, p7/m, za1v\.h\[w15, 7\] ++ 1c: c082fdff mov z31\.s, p7/m, za3v\.s\[w15, 3\] ++ 20: c0c2fdff mov z31\.d, p7/m, za7v\.d\[w15, 1\] ++ 24: c0c3fdff mov z31\.q, p7/m, za15v\.q\[w15, 0\] ++ 28: c0020000 mov z0\.b, p0/m, za0h\.b\[w12, 0\] ++ 2c: c0420000 mov z0\.h, p0/m, za0h\.h\[w12, 0\] ++ 30: c0820000 mov z0\.s, p0/m, za0h\.s\[w12, 0\] ++ 34: c0c20000 mov z0\.d, p0/m, za0h\.d\[w12, 0\] ++ 38: c0c30000 mov z0\.q, p0/m, za0h\.q\[w12, 0\] ++ 3c: c0027dff mov z31\.b, p7/m, za0h\.b\[w15, 15\] ++ 40: c0427dff mov z31\.h, p7/m, za1h\.h\[w15, 7\] ++ 44: c0827dff mov z31\.s, p7/m, za3h\.s\[w15, 3\] ++ 48: c0c27dff mov z31\.d, p7/m, za7h\.d\[w15, 1\] ++ 4c: c0c37dff mov z31\.q, p7/m, za15h\.q\[w15, 0\] +diff --git a/gas/testsuite/gas/aarch64/sme-2a.s b/gas/testsuite/gas/aarch64/sme-2a.s +new file mode 100644 +index 00000000..47549818 +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/sme-2a.s +@@ -0,0 +1,26 @@ ++/* Scalable Matrix Extension (SME). */ ++ ++/* MOV alias (tile to vector) variant. */ ++mov z0.b, p0/m, za0v.b[w12, 0] ++mov z0.h, p0/m, za0v.h[w12, 0] ++mov z0.s, p0/m, za0v.s[w12, 0] ++mov z0.d, p0/m, za0v.d[w12, 0] ++mov z0.q, p0/m, za0v.q[w12, 0] ++ ++mov z31.b, p7/m, za0v.b[w15, 15] ++mov z31.h, p7/m, za1v.h[w15, 7] ++mov z31.s, p7/m, za3v.s[w15, 3] ++mov z31.d, p7/m, za7v.d[w15, 1] ++mov z31.q, p7/m, za15v.q[w15, 0] ++ ++mov z0.b, p0/m, za0h.b[w12, 0] ++mov z0.h, p0/m, za0h.h[w12, 0] ++mov z0.s, p0/m, za0h.s[w12, 0] ++mov z0.d, p0/m, za0h.d[w12, 0] ++mov z0.q, p0/m, za0h.q[w12, 0] ++ ++mov z31.b, p7/m, za0h.b[w15, 15] ++mov z31.h, p7/m, za1h.h[w15, 7] ++mov z31.s, p7/m, za3h.s[w15, 3] ++mov z31.d, p7/m, za7h.d[w15, 1] ++mov z31.q, p7/m, za15h.q[w15, 0] +diff --git a/gas/testsuite/gas/aarch64/sme-3-illegal.d b/gas/testsuite/gas/aarch64/sme-3-illegal.d +new file mode 100644 +index 00000000..5ee89d32 +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/sme-3-illegal.d +@@ -0,0 +1,3 @@ ++#as: -march=armv8-a+sme ++#source: sme-3-illegal.s ++#error_output: sme-3-illegal.l +diff --git a/gas/testsuite/gas/aarch64/sme-3-illegal.l b/gas/testsuite/gas/aarch64/sme-3-illegal.l +new file mode 100644 +index 00000000..8babf4c7 +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/sme-3-illegal.l +@@ -0,0 +1,11 @@ ++[^:]*: Assembler messages: ++[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `mova za1v\.b\[w12,#0\],p0/m,z0.b' ++[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `mova za2v\.h\[w12,#0\],p0/m,z0.h' ++[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `mova za4v\.s\[w12,#0\],p0/m,z0.s' ++[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `mova za8v\.d\[w12,#0\],p0/m,z0.d' ++[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `mova za16v\.q\[w12\],p0/m,z0.q' ++[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `mova za0v\.b\[w15,#16\],p7/m,z31.b' ++[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `mova za1v\.h\[w15,#8\],p7/m,z31.h' ++[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `mova za3v\.s\[w15,#4\],p7/m,z31.s' ++[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `mova za7v\.d\[w15,#2\],p7/m,z31.d' ++[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `mova za15v\.q\[w15,#1\],p7/m,z31.q' +diff --git a/gas/testsuite/gas/aarch64/sme-3-illegal.s b/gas/testsuite/gas/aarch64/sme-3-illegal.s +new file mode 100644 +index 00000000..6ed58ec6 +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/sme-3-illegal.s +@@ -0,0 +1,14 @@ ++/* Scalable Matrix Extension (SME). */ ++ ++/* MOVA (vector to tile) variant. */ ++mova za1v.b[w12, #0], p0/m, z0.b ++mova za2v.h[w12, #0], p0/m, z0.h ++mova za4v.s[w12, #0], p0/m, z0.s ++mova za8v.d[w12, #0], p0/m, z0.d ++mova za16v.q[w12], p0/m, z0.q ++ ++mova za0v.b[w15, #16], p7/m, z31.b ++mova za1v.h[w15, #8], p7/m, z31.h ++mova za3v.s[w15, #4], p7/m, z31.s ++mova za7v.d[w15, #2], p7/m, z31.d ++mova za15v.q[w15, #1], p7/m, z31.q +diff --git a/gas/testsuite/gas/aarch64/sme-3.d b/gas/testsuite/gas/aarch64/sme-3.d +new file mode 100644 +index 00000000..82f72ac9 +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/sme-3.d +@@ -0,0 +1,31 @@ ++#name: SME extension, MOVA (vector to tile) ++#as: -march=armv8-a+sme ++#objdump: -dr ++ ++.*: file format .* ++ ++Disassembly of section \.text: ++ ++0+ <.*>: ++ 0: c0008000 mov za0v\.b\[w12, 0\], p0/m, z0\.b ++ 4: c0408000 mov za0v\.h\[w12, 0\], p0/m, z0\.h ++ 8: c0808000 mov za0v\.s\[w12, 0\], p0/m, z0\.s ++ c: c0c08000 mov za0v\.d\[w12, 0\], p0/m, z0\.d ++ 10: c0c18000 mov za0v\.q\[w12, 0\], p0/m, z0\.q ++ 14: c000ffef mov za0v\.b\[w15, 15\], p7/m, z31\.b ++ 18: c040ffef mov za1v\.h\[w15, 7\], p7/m, z31\.h ++ 1c: c080ffef mov za3v\.s\[w15, 3\], p7/m, z31\.s ++ 20: c0c0ffef mov za7v\.d\[w15, 1\], p7/m, z31\.d ++ 24: c0c1ffef mov za15v\.q\[w15, 0\], p7/m, z31\.q ++ 28: c0000000 mov za0h\.b\[w12, 0\], p0/m, z0\.b ++ 2c: c0400000 mov za0h\.h\[w12, 0\], p0/m, z0\.h ++ 30: c0800000 mov za0h\.s\[w12, 0\], p0/m, z0\.s ++ 34: c0c00000 mov za0h\.d\[w12, 0\], p0/m, z0\.d ++ 38: c0c10000 mov za0h\.q\[w12, 0\], p0/m, z0\.q ++ 3c: c0007fef mov za0h\.b\[w15, 15\], p7/m, z31\.b ++ 40: c0407fef mov za1h\.h\[w15, 7\], p7/m, z31\.h ++ 44: c0807fef mov za3h\.s\[w15, 3\], p7/m, z31\.s ++ 48: c0c07fef mov za7h\.d\[w15, 1\], p7/m, z31\.d ++ 4c: c0c17fef mov za15h\.q\[w15, 0\], p7/m, z31\.q ++ 50: c0008000 mov za0v\.b\[w12, 0\], p0/m, z0\.b ++ 54: c0c17fef mov za15h\.q\[w15, 0\], p7/m, z31\.q +diff --git a/gas/testsuite/gas/aarch64/sme-3.s b/gas/testsuite/gas/aarch64/sme-3.s +new file mode 100644 +index 00000000..8efc896f +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/sme-3.s +@@ -0,0 +1,31 @@ ++/* Scalable Matrix Extension (SME). */ ++ ++/* MOVA (vector to tile) variant. */ ++mova za0v.b[w12, 0], p0/m, z0.b ++mova za0v.h[w12, 0], p0/m, z0.h ++mova za0v.s[w12, 0], p0/m, z0.s ++mova za0v.d[w12, 0], p0/m, z0.d ++mova za0v.q[w12, 0], p0/m, z0.q ++ ++mova za0v.b[w15, 15], p7/m, z31.b ++mova za1v.h[w15, 7], p7/m, z31.h ++mova za3v.s[w15, 3], p7/m, z31.s ++mova za7v.d[w15, 1], p7/m, z31.d ++mova za15v.q[w15, 0], p7/m, z31.q ++ ++mova za0h.b[w12, 0], p0/m, z0.b ++mova za0h.h[w12, 0], p0/m, z0.h ++mova za0h.s[w12, 0], p0/m, z0.s ++mova za0h.d[w12, 0], p0/m, z0.d ++mova za0h.q[w12, 0], p0/m, z0.q ++ ++mova za0h.b[w15, 15], p7/m, z31.b ++mova za1h.h[w15, 7], p7/m, z31.h ++mova za3h.s[w15, 3], p7/m, z31.s ++mova za7h.d[w15, 1], p7/m, z31.d ++mova za15h.q[w15, 0], p7/m, z31.q ++ ++foo .req w12 ++bar .req w15 ++mova za0v.b[foo, 0], p0/m, z0.b ++mova za15h.q[bar, 0], p7/m, z31.q +diff --git a/gas/testsuite/gas/aarch64/sme-3a.d b/gas/testsuite/gas/aarch64/sme-3a.d +new file mode 100644 +index 00000000..82835ae0 +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/sme-3a.d +@@ -0,0 +1,29 @@ ++#name: SME extension, MOV (vector to tile) ++#as: -march=armv8-a+sme ++#objdump: -dr ++ ++.*: file format .* ++ ++Disassembly of section \.text: ++ ++0+ <.*>: ++ 0: c0008000 mov za0v\.b\[w12, 0\], p0/m, z0\.b ++ 4: c0408000 mov za0v\.h\[w12, 0\], p0/m, z0\.h ++ 8: c0808000 mov za0v\.s\[w12, 0\], p0/m, z0\.s ++ c: c0c08000 mov za0v\.d\[w12, 0\], p0/m, z0\.d ++ 10: c0c18000 mov za0v\.q\[w12, 0\], p0/m, z0\.q ++ 14: c000ffef mov za0v\.b\[w15, 15\], p7/m, z31\.b ++ 18: c040ffef mov za1v\.h\[w15, 7\], p7/m, z31\.h ++ 1c: c080ffef mov za3v\.s\[w15, 3\], p7/m, z31\.s ++ 20: c0c0ffef mov za7v\.d\[w15, 1\], p7/m, z31\.d ++ 24: c0c1ffef mov za15v\.q\[w15, 0\], p7/m, z31\.q ++ 28: c0000000 mov za0h\.b\[w12, 0\], p0/m, z0\.b ++ 2c: c0400000 mov za0h\.h\[w12, 0\], p0/m, z0\.h ++ 30: c0800000 mov za0h\.s\[w12, 0\], p0/m, z0\.s ++ 34: c0c00000 mov za0h\.d\[w12, 0\], p0/m, z0\.d ++ 38: c0c10000 mov za0h\.q\[w12, 0\], p0/m, z0\.q ++ 3c: c0007fef mov za0h\.b\[w15, 15\], p7/m, z31\.b ++ 40: c0407fef mov za1h\.h\[w15, 7\], p7/m, z31\.h ++ 44: c0807fef mov za3h\.s\[w15, 3\], p7/m, z31\.s ++ 48: c0c07fef mov za7h\.d\[w15, 1\], p7/m, z31\.d ++ 4c: c0c17fef mov za15h\.q\[w15, 0\], p7/m, z31\.q +diff --git a/gas/testsuite/gas/aarch64/sme-3a.s b/gas/testsuite/gas/aarch64/sme-3a.s +new file mode 100644 +index 00000000..892a30e2 +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/sme-3a.s +@@ -0,0 +1,26 @@ ++/* Scalable Matrix Extension (SME). */ ++ ++/* MOV alias (vector to tile) variant. */ ++mov za0v.b[w12, 0], p0/m, z0.b ++mov za0v.h[w12, 0], p0/m, z0.h ++mov za0v.s[w12, 0], p0/m, z0.s ++mov za0v.d[w12, 0], p0/m, z0.d ++mov za0v.q[w12, 0], p0/m, z0.q ++ ++mov za0v.b[w15, 15], p7/m, z31.b ++mov za1v.h[w15, 7], p7/m, z31.h ++mov za3v.s[w15, 3], p7/m, z31.s ++mov za7v.d[w15, 1], p7/m, z31.d ++mov za15v.q[w15, 0], p7/m, z31.q ++ ++mov za0h.b[w12, 0], p0/m, z0.b ++mov za0h.h[w12, 0], p0/m, z0.h ++mov za0h.s[w12, 0], p0/m, z0.s ++mov za0h.d[w12, 0], p0/m, z0.d ++mov za0h.q[w12, 0], p0/m, z0.q ++ ++mov za0h.b[w15, 15], p7/m, z31.b ++mov za1h.h[w15, 7], p7/m, z31.h ++mov za3h.s[w15, 3], p7/m, z31.s ++mov za7h.d[w15, 1], p7/m, z31.d ++mov za15h.q[w15, 0], p7/m, z31.q +diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h +index 4b971ea2..23e3ce0a 100644 +--- a/include/opcode/aarch64.h ++++ b/include/opcode/aarch64.h +@@ -442,6 +442,8 @@ enum aarch64_opnd + AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */ + AARCH64_OPND_SME_ZAda_2b, /* SME .S, 2-bits. */ + AARCH64_OPND_SME_ZAda_3b, /* SME .D, 3-bits. */ ++ AARCH64_OPND_SME_ZA_HV_idx_src, /* SME source ZA tile vector. */ ++ AARCH64_OPND_SME_ZA_HV_idx_dest, /* SME destination ZA tile vector. */ + AARCH64_OPND_SME_Pm, /* SME scalable predicate register, bits [15:13]. */ + AARCH64_OPND_TME_UIMM16, /* TME unsigned 16-bit immediate. */ + AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */ +@@ -1109,6 +1111,18 @@ struct aarch64_opnd_info + uint32_t flags; + } sysreg; + ++ /* ZA tile vector, e.g. .D[{, }] */ ++ struct ++ { ++ int regno; /* */ ++ struct ++ { ++ int regno; /* */ ++ int imm; /* */ ++ } index; ++ unsigned v : 1; /* horizontal or vertical vector indicator. */ ++ } za_tile_vector; ++ + const aarch64_cond *cond; + /* The encoding of the PSTATE field. */ + aarch64_insn pstatefield; +diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c +index 4839fef8..eda943eb 100644 +--- a/opcodes/aarch64-asm-2.c ++++ b/opcodes/aarch64-asm-2.c +@@ -663,7 +663,7 @@ aarch64_insert_operand (const aarch64_operand *self, + case 207: + case 209: + case 210: +- case 211: ++ case 213: + return aarch64_ins_regno (self, info, code, inst, errors); + case 15: + return aarch64_ins_reg_extended (self, info, code, inst, errors); +@@ -675,7 +675,7 @@ aarch64_insert_operand (const aarch64_operand *self, + case 33: + case 34: + case 35: +- case 213: ++ case 215: + return aarch64_ins_reglane (self, info, code, inst, errors); + case 36: + return aarch64_ins_reglist (self, info, code, inst, errors); +@@ -720,7 +720,7 @@ aarch64_insert_operand (const aarch64_operand *self, + case 187: + case 188: + case 189: +- case 212: ++ case 214: + return aarch64_ins_imm (self, info, code, inst, errors); + case 44: + case 45: +@@ -879,6 +879,9 @@ aarch64_insert_operand (const aarch64_operand *self, + case 206: + case 208: + return aarch64_ins_sve_reglist (self, info, code, inst, errors); ++ case 211: ++ case 212: ++ return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors); + default: assert (0); abort (); + } + } +diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c +index 7cc81465..9a77d0f7 100644 +--- a/opcodes/aarch64-asm.c ++++ b/opcodes/aarch64-asm.c +@@ -1325,6 +1325,61 @@ aarch64_ins_sve_float_zero_one (const aarch64_operand *self, + return true; + } + ++/* Encode in SME instruction such as MOVA ZA tile vector register number, ++ vector indicator, vector selector and immediate. */ ++bool ++aarch64_ins_sme_za_hv_tiles (const aarch64_operand *self, ++ const aarch64_opnd_info *info, ++ aarch64_insn *code, ++ const aarch64_inst *inst ATTRIBUTE_UNUSED, ++ aarch64_operand_error *errors ATTRIBUTE_UNUSED) ++{ ++ int fld_size; ++ int fld_q; ++ int fld_v = info->za_tile_vector.v; ++ int fld_rv = info->za_tile_vector.index.regno - 12; ++ int fld_zan_imm = info->za_tile_vector.index.imm; ++ int regno = info->za_tile_vector.regno; ++ ++ switch (info->qualifier) ++ { ++ case AARCH64_OPND_QLF_S_B: ++ fld_size = 0; ++ fld_q = 0; ++ break; ++ case AARCH64_OPND_QLF_S_H: ++ fld_size = 1; ++ fld_q = 0; ++ fld_zan_imm |= regno << 3; ++ break; ++ case AARCH64_OPND_QLF_S_S: ++ fld_size = 2; ++ fld_q = 0; ++ fld_zan_imm |= regno << 2; ++ break; ++ case AARCH64_OPND_QLF_S_D: ++ fld_size = 3; ++ fld_q = 0; ++ fld_zan_imm |= regno << 1; ++ break; ++ case AARCH64_OPND_QLF_S_Q: ++ fld_size = 3; ++ fld_q = 1; ++ fld_zan_imm = regno; ++ break; ++ default: ++ assert (0); ++ } ++ ++ insert_field (self->fields[0], code, fld_size, 0); ++ insert_field (self->fields[1], code, fld_q, 0); ++ insert_field (self->fields[2], code, fld_v, 0); ++ insert_field (self->fields[3], code, fld_rv, 0); ++ insert_field (self->fields[4], code, fld_zan_imm, 0); ++ ++ return true; ++} ++ + /* Miscellaneous encoding functions. */ + + /* Encode size[0], i.e. bit 22, for +diff --git a/opcodes/aarch64-asm.h b/opcodes/aarch64-asm.h +index 5ea24bad..9cbcd7a8 100644 +--- a/opcodes/aarch64-asm.h ++++ b/opcodes/aarch64-asm.h +@@ -98,6 +98,7 @@ AARCH64_DECL_OPD_INSERTER (ins_sve_reglist); + AARCH64_DECL_OPD_INSERTER (ins_sve_scale); + AARCH64_DECL_OPD_INSERTER (ins_sve_shlimm); + AARCH64_DECL_OPD_INSERTER (ins_sve_shrimm); ++AARCH64_DECL_OPD_INSERTER (ins_sme_za_hv_tiles); + AARCH64_DECL_OPD_INSERTER (ins_imm_rotate1); + AARCH64_DECL_OPD_INSERTER (ins_imm_rotate2); + +diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c +index 4376e3bc..6bde0f35 100644 +--- a/opcodes/aarch64-dis-2.c ++++ b/opcodes/aarch64-dis-2.c +@@ -38,23 +38,23 @@ aarch64_opcode_lookup_1 (uint32_t word) + { + if (((word >> 21) & 0x1) == 0) + { +- if (((word >> 22) & 0x1) == 0) ++ if (((word >> 29) & 0x1) == 0) + { +- if (((word >> 23) & 0x1) == 0) +- { +- /* 33222222222211111111110000000000 +- 10987654321098765432109876543210 +- xxx00000000xxxxxxxxxxxxxxxxxxxxx +- udf. */ +- return 754; +- } +- else ++ if (((word >> 30) & 0x1) == 0) + { +- if (((word >> 4) & 0x1) == 0) ++ if (((word >> 22) & 0x1) == 0) + { +- if (((word >> 29) & 0x1) == 0) ++ if (((word >> 23) & 0x1) == 0) + { +- if (((word >> 30) & 0x1) == 0) ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ x0000000000xxxxxxxxxxxxxxxxxxxxx ++ udf. */ ++ return 754; ++ } ++ else ++ { ++ if (((word >> 4) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 +@@ -64,88 +64,110 @@ aarch64_opcode_lookup_1 (uint32_t word) + } + else + { +- if (((word >> 16) & 0x1) == 0) +- { +- /* 33222222222211111111110000000000 +- 10987654321098765432109876543210 +- x1000000100xxxx0xxxxxxxxxxx0xxxx +- addha. */ +- return 2348; +- } +- else +- { +- /* 33222222222211111111110000000000 +- 10987654321098765432109876543210 +- x1000000100xxxx1xxxxxxxxxxx0xxxx +- addva. */ +- return 2350; +- } ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ x0000000100xxxxxxxxxxxxxxxx1xxxx ++ fmops. */ ++ return 2357; + } + } +- else +- { +- /* 33222222222211111111110000000000 +- 10987654321098765432109876543210 +- xx100000100xxxxxxxxxxxxxxxx0xxxx +- smopa. */ +- return 2360; +- } + } + else + { +- if (((word >> 29) & 0x1) == 0) ++ if (((word >> 4) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 +- xx000000100xxxxxxxxxxxxxxxx1xxxx +- fmops. */ +- return 2357; ++ x0000000x10xxxxxxxxxxxxxxxx0xxxx ++ fmopa. */ ++ return 2355; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 +- xx100000100xxxxxxxxxxxxxxxx1xxxx +- smops. */ +- return 2362; ++ x0000000x10xxxxxxxxxxxxxxxx1xxxx ++ fmops. */ ++ return 2358; + } + } + } +- } +- else +- { +- if (((word >> 4) & 0x1) == 0) ++ else + { +- if (((word >> 29) & 0x1) == 0) ++ if (((word >> 17) & 0x1) == 0) + { +- if (((word >> 30) & 0x1) == 0) ++ if (((word >> 20) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 +- x0000000x10xxxxxxxxxxxxxxxx0xxxx +- fmopa. */ +- return 2355; ++ x1000000xx00xx0xxxxxxxxxxxxxxxxx ++ mov. */ ++ return 2377; + } + else + { + if (((word >> 16) & 0x1) == 0) + { +- /* 33222222222211111111110000000000 +- 10987654321098765432109876543210 +- x1000000x10xxxx0xxxxxxxxxxx0xxxx +- addha. */ +- return 2349; ++ if (((word >> 22) & 0x1) == 0) ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ x1000000x001xx00xxxxxxxxxxxxxxxx ++ addha. */ ++ return 2348; ++ } ++ else ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ x1000000x101xx00xxxxxxxxxxxxxxxx ++ addha. */ ++ return 2349; ++ } + } + else + { +- /* 33222222222211111111110000000000 +- 10987654321098765432109876543210 +- x1000000x10xxxx1xxxxxxxxxxx0xxxx +- addva. */ +- return 2351; ++ if (((word >> 22) & 0x1) == 0) ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ x1000000x001xx01xxxxxxxxxxxxxxxx ++ addva. */ ++ return 2350; ++ } ++ else ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ x1000000x101xx01xxxxxxxxxxxxxxxx ++ addva. */ ++ return 2351; ++ } + } + } + } ++ else ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ x1000000xx0xxx1xxxxxxxxxxxxxxxxx ++ mov. */ ++ return 2376; ++ } ++ } ++ } ++ else ++ { ++ if (((word >> 4) & 0x1) == 0) ++ { ++ if (((word >> 22) & 0x1) == 0) ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ xx100000x00xxxxxxxxxxxxxxxx0xxxx ++ smopa. */ ++ return 2360; ++ } + else + { + /* 33222222222211111111110000000000 +@@ -157,13 +179,13 @@ aarch64_opcode_lookup_1 (uint32_t word) + } + else + { +- if (((word >> 29) & 0x1) == 0) ++ if (((word >> 22) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 +- xx000000x10xxxxxxxxxxxxxxxx1xxxx +- fmops. */ +- return 2358; ++ xx100000x00xxxxxxxxxxxxxxxx1xxxx ++ smops. */ ++ return 2362; + } + else + { +@@ -2731,7 +2753,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 00011001000xxxxxxxxx00xxxxxxxxxx + stlurb. */ +- return 2416; ++ return 2420; + } + else + { +@@ -2739,7 +2761,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 10011001000xxxxxxxxx00xxxxxxxxxx + stlur. */ +- return 2424; ++ return 2428; + } + } + else +@@ -2750,7 +2772,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 01011001000xxxxxxxxx00xxxxxxxxxx + stlurh. */ +- return 2420; ++ return 2424; + } + else + { +@@ -2758,7 +2780,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 11011001000xxxxxxxxx00xxxxxxxxxx + stlur. */ +- return 2427; ++ return 2431; + } + } + } +@@ -2838,7 +2860,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 00011001010xxxxxxxxx00xxxxxxxxxx + ldapurb. */ +- return 2417; ++ return 2421; + } + else + { +@@ -2846,7 +2868,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 10011001010xxxxxxxxx00xxxxxxxxxx + ldapur. */ +- return 2425; ++ return 2429; + } + } + else +@@ -2857,7 +2879,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 01011001010xxxxxxxxx00xxxxxxxxxx + ldapurh. */ +- return 2421; ++ return 2425; + } + else + { +@@ -2865,7 +2887,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 11011001010xxxxxxxxx00xxxxxxxxxx + ldapur. */ +- return 2428; ++ return 2432; + } + } + } +@@ -2948,7 +2970,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 00011001100xxxxxxxxx00xxxxxxxxxx + ldapursb. */ +- return 2419; ++ return 2423; + } + else + { +@@ -2956,7 +2978,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 10011001100xxxxxxxxx00xxxxxxxxxx + ldapursw. */ +- return 2426; ++ return 2430; + } + } + else +@@ -2965,7 +2987,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1011001100xxxxxxxxx00xxxxxxxxxx + ldapursh. */ +- return 2423; ++ return 2427; + } + } + else +@@ -2976,7 +2998,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x0011001110xxxxxxxxx00xxxxxxxxxx + ldapursb. */ +- return 2418; ++ return 2422; + } + else + { +@@ -2984,7 +3006,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1011001110xxxxxxxxx00xxxxxxxxxx + ldapursh. */ +- return 2422; ++ return 2426; + } + } + } +@@ -3470,7 +3492,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xxx11010x00xxxxxx0xx10xxxxxxxxxx + setf8. */ +- return 2414; ++ return 2418; + } + else + { +@@ -3478,7 +3500,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xxx11010x00xxxxxx1xx10xxxxxxxxxx + setf16. */ +- return 2415; ++ return 2419; + } + } + else +@@ -3624,7 +3646,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xxx11010000xxxxxxxxx01xxxxxxxxxx + rmif. */ +- return 2413; ++ return 2417; + } + else + { +@@ -4673,7 +4695,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x01x1xxxxx000110xxxxxxxxxx + usdot. */ +- return 2433; ++ return 2437; + } + } + } +@@ -4747,7 +4769,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x01x1xxxxx000111xxxxxxxxxx + sudot. */ +- return 2434; ++ return 2438; + } + } + } +@@ -7366,7 +7388,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0xx0xxxxx011110xxxxxxxxxx + usdot. */ +- return 2432; ++ return 2436; + } + } + } +@@ -9070,7 +9092,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0100xxx10101xxxxxxxxxxxxx + bfcvtnt. */ +- return 2461; ++ return 2465; + } + } + else +@@ -9313,7 +9335,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x00x1xxxxxx00xxxxxxxxxxxxx + ld1rob. */ +- return 2437; ++ return 2441; + } + else + { +@@ -9321,7 +9343,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x01x1xxxxxx00xxxxxxxxxxxxx + ld1roh. */ +- return 2438; ++ return 2442; + } + } + else +@@ -9553,7 +9575,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0011xxxxx010xxxxxxxxxxxxx + bfdot. */ +- return 2458; ++ return 2462; + } + else + { +@@ -9574,7 +9596,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0111xxxxx010xx0xxxxxxxxxx + bfmlalb. */ +- return 2465; ++ return 2469; + } + else + { +@@ -9582,7 +9604,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0111xxxxx010xx1xxxxxxxxxx + bfmlalt. */ +- return 2464; ++ return 2468; + } + } + else +@@ -9637,7 +9659,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x11001x0011xxxxx1x0xxxxxxxxxxxxx + bfdot. */ +- return 2457; ++ return 2461; + } + else + { +@@ -9649,7 +9671,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0111xxxxx1x0xx0xxxxxxxxxx + bfmlalb. */ +- return 2463; ++ return 2467; + } + else + { +@@ -9657,7 +9679,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0111xxxxx1x0xx1xxxxxxxxxx + bfmlalt. */ +- return 2462; ++ return 2466; + } + } + else +@@ -9708,7 +9730,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x00x1xxxxx001xxxxxxxxxxxxx + ld1rob. */ +- return 2441; ++ return 2445; + } + else + { +@@ -9716,7 +9738,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x01x1xxxxx001xxxxxxxxxxxxx + ld1roh. */ +- return 2442; ++ return 2446; + } + } + else +@@ -10075,7 +10097,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0101xxxxx111xxxxxxxxxxxxx + fmmla. */ +- return 2435; ++ return 2439; + } + else + { +@@ -10108,7 +10130,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0011xxxxx111xxxxxxxxxxxxx + bfmmla. */ +- return 2459; ++ return 2463; + } + else + { +@@ -10138,7 +10160,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0111xxxxx111xxxxxxxxxxxxx + fmmla. */ +- return 2436; ++ return 2440; + } + else + { +@@ -10267,7 +10289,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1101xxxxx000x00xxxxxxxxxx + zip1. */ +- return 2445; ++ return 2449; + } + else + { +@@ -10277,7 +10299,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1101xxxxx000010xxxxxxxxxx + uzp1. */ +- return 2447; ++ return 2451; + } + else + { +@@ -10285,7 +10307,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1101xxxxx000110xxxxxxxxxx + trn1. */ +- return 2449; ++ return 2453; + } + } + } +@@ -10297,7 +10319,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1101xxxxx000x01xxxxxxxxxx + zip2. */ +- return 2446; ++ return 2450; + } + else + { +@@ -10307,7 +10329,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1101xxxxx000011xxxxxxxxxx + uzp2. */ +- return 2448; ++ return 2452; + } + else + { +@@ -10315,7 +10337,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1101xxxxx000111xxxxxxxxxx + trn2. */ +- return 2450; ++ return 2454; + } + } + } +@@ -11363,7 +11385,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1000xxxxx100110xxxxxxxxxx + smmla. */ +- return 2429; ++ return 2433; + } + else + { +@@ -11371,7 +11393,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1100xxxxx100110xxxxxxxxxx + usmmla. */ +- return 2431; ++ return 2435; + } + } + else +@@ -11380,7 +11402,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1x10xxxxx100110xxxxxxxxxx + ummla. */ +- return 2430; ++ return 2434; + } + } + } +@@ -12876,7 +12898,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x10x1xxxxx000xxxxxxxxxxxxx + ld1row. */ +- return 2439; ++ return 2443; + } + else + { +@@ -12884,7 +12906,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x11x1xxxxx000xxxxxxxxxxxxx + ld1rod. */ +- return 2440; ++ return 2444; + } + } + } +@@ -13258,7 +13280,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x10x1xxxxx001xxxxxxxxxxxxx + ld1row. */ +- return 2443; ++ return 2447; + } + else + { +@@ -13266,7 +13288,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x11x1xxxxx001xxxxxxxxxxxxx + ld1rod. */ +- return 2444; ++ return 2448; + } + } + } +@@ -14700,7 +14722,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x110001x10101xxxxxxxxxxxxx + bfcvt. */ +- return 2460; ++ return 2464; + } + } + else +@@ -16769,7 +16791,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 0x001110xx0xxxxx1x1001xxxxxxxxxx + smmla. */ +- return 2451; ++ return 2455; + } + } + } +@@ -16802,7 +16824,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 0x001110xx0xxxxx1x0101xxxxxxxxxx + sdot. */ +- return 2377; ++ return 2381; + } + } + else +@@ -16876,7 +16898,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 0x001110xx0xxxxx1x1011xxxxxxxxxx + usmmla. */ +- return 2453; ++ return 2457; + } + } + } +@@ -16909,7 +16931,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 0x001110xx0xxxxx1x0111xxxxxxxxxx + usdot. */ +- return 2454; ++ return 2458; + } + } + else +@@ -16956,7 +16978,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110000xxxxxxxxxxxxxxxxxxxxx + eor3. */ +- return 2384; ++ return 2388; + } + else + { +@@ -16964,7 +16986,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110100xxxxxxxxxxxxxxxxxxxxx + xar. */ +- return 2386; ++ return 2390; + } + } + else +@@ -16975,7 +16997,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110x10xxxxx0xxxxxxxxxxxxxxx + sm3ss1. */ +- return 2388; ++ return 2392; + } + else + { +@@ -16989,7 +17011,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110010xxxxx1xxx00xxxxxxxxxx + sm3tt1a. */ +- return 2389; ++ return 2393; + } + else + { +@@ -16997,7 +17019,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110110xxxxx1xxx00xxxxxxxxxx + sha512su0. */ +- return 2382; ++ return 2386; + } + } + else +@@ -17006,7 +17028,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110x10xxxxx1xxx10xxxxxxxxxx + sm3tt2a. */ +- return 2391; ++ return 2395; + } + } + else +@@ -17019,7 +17041,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110010xxxxx1xxx01xxxxxxxxxx + sm3tt1b. */ +- return 2390; ++ return 2394; + } + else + { +@@ -17027,7 +17049,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110110xxxxx1xxx01xxxxxxxxxx + sm4e. */ +- return 2395; ++ return 2399; + } + } + else +@@ -17036,7 +17058,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110x10xxxxx1xxx11xxxxxxxxxx + sm3tt2b. */ +- return 2392; ++ return 2396; + } + } + } +@@ -17217,7 +17239,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx101110xx0xxxxx100101xxxxxxxxxx + udot. */ +- return 2376; ++ return 2380; + } + } + else +@@ -17248,7 +17270,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx101110xx0xxxxx101x01xxxxxxxxxx + ummla. */ +- return 2452; ++ return 2456; + } + else + { +@@ -17267,7 +17289,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx101110xx0xxxxx1x1011xxxxxxxxxx + bfmmla. */ +- return 2468; ++ return 2472; + } + else + { +@@ -17277,7 +17299,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx1011100x0xxxxx1x1111xxxxxxxxxx + bfdot. */ +- return 2466; ++ return 2470; + } + else + { +@@ -17287,7 +17309,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x01011101x0xxxxx1x1111xxxxxxxxxx + bfmlalb. */ +- return 2473; ++ return 2477; + } + else + { +@@ -17295,7 +17317,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x11011101x0xxxxx1x1111xxxxxxxxxx + bfmlalt. */ +- return 2472; ++ return 2476; + } + } + } +@@ -17879,7 +17901,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000011101x1xxxx1011010xxxxxxxxxx + bfcvtn. */ +- return 2469; ++ return 2473; + } + else + { +@@ -17887,7 +17909,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010011101x1xxxx1011010xxxxxxxxxx + bfcvtn2. */ +- return 2470; ++ return 2474; + } + } + } +@@ -18205,7 +18227,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110xx1xxxxx0xxxxxxxxxxxxxxx + bcax. */ +- return 2387; ++ return 2391; + } + } + else +@@ -18816,7 +18838,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 11001110xx1xxxxx100000xxxxxxxxxx + sha512h. */ +- return 2380; ++ return 2384; + } + } + } +@@ -18868,7 +18890,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 11001110xx1xxxxx110000xxxxxxxxxx + sm3partw1. */ +- return 2393; ++ return 2397; + } + } + } +@@ -19111,7 +19133,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110xx1xxxxx100010xxxxxxxxxx + sha512su1. */ +- return 2383; ++ return 2387; + } + } + else +@@ -19187,7 +19209,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x0011100x1xxxxx110010xxxxxxxxxx + sm4ekey. */ +- return 2396; ++ return 2400; + } + } + else +@@ -20013,7 +20035,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110xx1xxxxx100001xxxxxxxxxx + sha512h2. */ +- return 2381; ++ return 2385; + } + } + else +@@ -20045,7 +20067,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x0011100x1xxxxx110001xxxxxxxxxx + sm3partw2. */ +- return 2394; ++ return 2398; + } + } + else +@@ -20285,7 +20307,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110xx1xxxxx100011xxxxxxxxxx + rax1. */ +- return 2385; ++ return 2389; + } + } + else +@@ -20317,7 +20339,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x01011100x1xxxxx110011xxxxxxxxxx + fmlal2. */ +- return 2399; ++ return 2403; + } + else + { +@@ -20325,7 +20347,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x11011100x1xxxxx110011xxxxxxxxxx + fmlal2. */ +- return 2403; ++ return 2407; + } + } + } +@@ -20347,7 +20369,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x01011101x1xxxxx110011xxxxxxxxxx + fmlsl2. */ +- return 2400; ++ return 2404; + } + else + { +@@ -20355,7 +20377,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x11011101x1xxxxx110011xxxxxxxxxx + fmlsl2. */ +- return 2404; ++ return 2408; + } + } + } +@@ -20394,7 +20416,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x00011100x1xxxxx111011xxxxxxxxxx + fmlal. */ +- return 2397; ++ return 2401; + } + else + { +@@ -20402,7 +20424,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x10011100x1xxxxx111011xxxxxxxxxx + fmlal. */ +- return 2401; ++ return 2405; + } + } + else +@@ -20424,7 +20446,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x00011101x1xxxxx111011xxxxxxxxxx + fmlsl. */ +- return 2398; ++ return 2402; + } + else + { +@@ -20432,7 +20454,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x10011101x1xxxxx111011xxxxxxxxxx + fmlsl. */ +- return 2402; ++ return 2406; + } + } + else +@@ -22240,7 +22262,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x0001111xxxxxxxx0000x0xxxxxxxxxx + fmlal. */ +- return 2405; ++ return 2409; + } + else + { +@@ -22248,7 +22270,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1001111xxxxxxxx0000x0xxxxxxxxxx + fmlal. */ +- return 2409; ++ return 2413; + } + } + else +@@ -22270,7 +22292,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x0001111xxxxxxxx0100x0xxxxxxxxxx + fmlsl. */ +- return 2406; ++ return 2410; + } + else + { +@@ -22278,7 +22300,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1001111xxxxxxxx0100x0xxxxxxxxxx + fmlsl. */ +- return 2410; ++ return 2414; + } + } + else +@@ -22784,7 +22806,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x0101111xxxxxxxx1000x0xxxxxxxxxx + fmlal2. */ +- return 2407; ++ return 2411; + } + else + { +@@ -22792,7 +22814,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1101111xxxxxxxx1000x0xxxxxxxxxx + fmlal2. */ +- return 2411; ++ return 2415; + } + } + } +@@ -22814,7 +22836,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x0101111xxxxxxxx1100x0xxxxxxxxxx + fmlsl2. */ +- return 2408; ++ return 2412; + } + else + { +@@ -22822,7 +22844,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1101111xxxxxxxx1100x0xxxxxxxxxx + fmlsl2. */ +- return 2412; ++ return 2416; + } + } + } +@@ -22878,7 +22900,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx001111xxxxxxxx1110x0xxxxxxxxxx + sdot. */ +- return 2379; ++ return 2383; + } + else + { +@@ -22886,7 +22908,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx101111xxxxxxxx1110x0xxxxxxxxxx + udot. */ +- return 2378; ++ return 2382; + } + } + } +@@ -22989,7 +23011,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx00111100xxxxxx1111x0xxxxxxxxxx + sudot. */ +- return 2456; ++ return 2460; + } + else + { +@@ -22997,7 +23019,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx00111110xxxxxx1111x0xxxxxxxxxx + usdot. */ +- return 2455; ++ return 2459; + } + } + else +@@ -23008,7 +23030,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx00111101xxxxxx1111x0xxxxxxxxxx + bfdot. */ +- return 2467; ++ return 2471; + } + else + { +@@ -23018,7 +23040,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x000111111xxxxxx1111x0xxxxxxxxxx + bfmlalb. */ +- return 2475; ++ return 2479; + } + else + { +@@ -23026,7 +23048,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x100111111xxxxxx1111x0xxxxxxxxxx + bfmlalt. */ +- return 2474; ++ return 2478; + } + } + } +@@ -23513,6 +23535,10 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode) + int value; + switch (key) + { ++ case 2377: value = 2379; break; /* mov --> mova. */ ++ case 2379: return NULL; /* mova --> NULL. */ ++ case 2376: value = 2378; break; /* mov --> mova. */ ++ case 2378: return NULL; /* mova --> NULL. */ + case 12: value = 19; break; /* add --> addg. */ + case 19: return NULL; /* addg --> NULL. */ + case 16: value = 20; break; /* sub --> subg. */ +@@ -23660,8 +23686,8 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode) + case 824: return NULL; /* fsqrt --> NULL. */ + case 832: value = 833; break; /* frintz --> frintz. */ + case 833: return NULL; /* frintz --> NULL. */ +- case 825: value = 2471; break; /* fcvt --> bfcvt. */ +- case 2471: return NULL; /* bfcvt --> NULL. */ ++ case 825: value = 2475; break; /* fcvt --> bfcvt. */ ++ case 2475: return NULL; /* bfcvt --> NULL. */ + case 834: value = 835; break; /* frinta --> frinta. */ + case 835: return NULL; /* frinta --> NULL. */ + case 836: value = 837; break; /* frintx --> frintx. */ +@@ -24164,7 +24190,7 @@ aarch64_extract_operand (const aarch64_operand *self, + case 207: + case 209: + case 210: +- case 211: ++ case 213: + return aarch64_ext_regno (self, info, code, inst, errors); + case 10: + return aarch64_ext_regrt_sysins (self, info, code, inst, errors); +@@ -24180,7 +24206,7 @@ aarch64_extract_operand (const aarch64_operand *self, + case 33: + case 34: + case 35: +- case 213: ++ case 215: + return aarch64_ext_reglane (self, info, code, inst, errors); + case 36: + return aarch64_ext_reglist (self, info, code, inst, errors); +@@ -24226,7 +24252,7 @@ aarch64_extract_operand (const aarch64_operand *self, + case 187: + case 188: + case 189: +- case 212: ++ case 214: + return aarch64_ext_imm (self, info, code, inst, errors); + case 44: + case 45: +@@ -24387,6 +24413,9 @@ aarch64_extract_operand (const aarch64_operand *self, + case 206: + case 208: + return aarch64_ext_sve_reglist (self, info, code, inst, errors); ++ case 211: ++ case 212: ++ return aarch64_ext_sme_za_hv_tiles (self, info, code, inst, errors); + default: assert (0); abort (); + } + } +diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c +index 2549e6c3..f4e7fe90 100644 +--- a/opcodes/aarch64-dis.c ++++ b/opcodes/aarch64-dis.c +@@ -1747,6 +1747,64 @@ aarch64_ext_sve_float_zero_one (const aarch64_operand *self, + return true; + } + ++/* Decode ZA tile vector, vector indicator, vector selector, qualifier and ++ immediate on numerous SME instruction fields such as MOVA. */ ++bool ++aarch64_ext_sme_za_hv_tiles (const aarch64_operand *self, ++ aarch64_opnd_info *info, aarch64_insn code, ++ const aarch64_inst *inst ATTRIBUTE_UNUSED, ++ aarch64_operand_error *errors ATTRIBUTE_UNUSED) ++{ ++ int fld_size = extract_field (self->fields[0], code, 0); ++ int fld_q = extract_field (self->fields[1], code, 0); ++ int fld_v = extract_field (self->fields[2], code, 0); ++ int fld_rv = extract_field (self->fields[3], code, 0); ++ int fld_zan_imm = extract_field (self->fields[4], code, 0); ++ ++ /* Deduce qualifier encoded in size and Q fields. */ ++ if (fld_size == 0) ++ info->qualifier = AARCH64_OPND_QLF_S_B; ++ else if (fld_size == 1) ++ info->qualifier = AARCH64_OPND_QLF_S_H; ++ else if (fld_size == 2) ++ info->qualifier = AARCH64_OPND_QLF_S_S; ++ else if (fld_size == 3 && fld_q == 0) ++ info->qualifier = AARCH64_OPND_QLF_S_D; ++ else if (fld_size == 3 && fld_q == 1) ++ info->qualifier = AARCH64_OPND_QLF_S_Q; ++ ++ info->za_tile_vector.index.regno = fld_rv + 12; ++ info->za_tile_vector.v = fld_v; ++ ++ switch (info->qualifier) ++ { ++ case AARCH64_OPND_QLF_S_B: ++ info->za_tile_vector.regno = 0; ++ info->za_tile_vector.index.imm = fld_zan_imm; ++ break; ++ case AARCH64_OPND_QLF_S_H: ++ info->za_tile_vector.regno = fld_zan_imm >> 3; ++ info->za_tile_vector.index.imm = fld_zan_imm & 0x07; ++ break; ++ case AARCH64_OPND_QLF_S_S: ++ info->za_tile_vector.regno = fld_zan_imm >> 2; ++ info->za_tile_vector.index.imm = fld_zan_imm & 0x03; ++ break; ++ case AARCH64_OPND_QLF_S_D: ++ info->za_tile_vector.regno = fld_zan_imm >> 1; ++ info->za_tile_vector.index.imm = fld_zan_imm & 0x01; ++ break; ++ case AARCH64_OPND_QLF_S_Q: ++ info->za_tile_vector.regno = fld_zan_imm; ++ info->za_tile_vector.index.imm = 0; ++ break; ++ default: ++ assert (0); ++ } ++ ++ return true; ++} ++ + /* Decode Zn[MM], where MM has a 7-bit triangular encoding. The fields + array specifies which field to use for Zn. MM is encoded in the + concatenation of imm5 and SVE_tszh, with imm5 being the less +diff --git a/opcodes/aarch64-dis.h b/opcodes/aarch64-dis.h +index 09305b9c..842ec554 100644 +--- a/opcodes/aarch64-dis.h ++++ b/opcodes/aarch64-dis.h +@@ -122,6 +122,7 @@ AARCH64_DECL_OPD_EXTRACTOR (ext_sve_reglist); + AARCH64_DECL_OPD_EXTRACTOR (ext_sve_scale); + AARCH64_DECL_OPD_EXTRACTOR (ext_sve_shlimm); + AARCH64_DECL_OPD_EXTRACTOR (ext_sve_shrimm); ++AARCH64_DECL_OPD_EXTRACTOR (ext_sme_za_hv_tiles); + AARCH64_DECL_OPD_EXTRACTOR (ext_imm_rotate1); + AARCH64_DECL_OPD_EXTRACTOR (ext_imm_rotate2); + +diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c +index cf1ce0b0..e80cbf20 100644 +--- a/opcodes/aarch64-opc-2.c ++++ b/opcodes/aarch64-opc-2.c +@@ -235,6 +235,8 @@ const struct aarch64_operand aarch64_operands[] = + {AARCH64_OPND_CLASS_SVE_REG, "SVE_ZtxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "a list of SVE vector registers"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_ZAda_2b", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZAda_2b}, "an SME ZA tile ZA0-ZA3"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_ZAda_3b", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZAda_3b}, "an SME ZA tile ZA0-ZA7"}, ++ {AARCH64_OPND_CLASS_SVE_REG, "SME_ZA_HV_idx_src", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_10,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_5}, "an SME horizontal or vertical vector access register"}, ++ {AARCH64_OPND_CLASS_SVE_REG, "SME_ZA_HV_idx_dest", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_10,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_2}, "an SME horizontal or vertical vector access register"}, + {AARCH64_OPND_CLASS_PRED_REG, "SME_Pm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Pm}, "an SVE predicate register"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "TME_UIMM16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16}, "a 16-bit unsigned immediate for TME tcancel"}, + {AARCH64_OPND_CLASS_SIMD_ELEMENT, "SM3_IMM2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SM3_imm2}, "an indexed SM3 vector immediate"}, +diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c +index 8ced8e0d..b12bf3e0 100644 +--- a/opcodes/aarch64-opc.c ++++ b/opcodes/aarch64-opc.c +@@ -242,6 +242,7 @@ const aarch64_field fields[] = + { 11, 4 }, /* imm4: in advsimd ext and advsimd ins instructions. */ + { 0, 4 }, /* imm4_2: in rmif instructions. */ + { 10, 4 }, /* imm4_3: in adddg/subg instructions. */ ++ { 5, 4 }, /* imm4_5: in SME instructions. */ + { 16, 5 }, /* imm5: in conditional compare (immediate) instructions. */ + { 15, 7 }, /* imm7: in load/store pair pre/post index instructions. */ + { 13, 8 }, /* imm8: in floating-point scalar move immediate inst. */ +@@ -323,6 +324,10 @@ const aarch64_field fields[] = + { 22, 1 }, /* SVE_xs_22: UXTW/SXTW select (bit 22). */ + { 0, 2 }, /* SME ZAda tile ZA0-ZA3. */ + { 0, 3 }, /* SME ZAda tile ZA0-ZA7. */ ++ { 22, 2 }, /* SME_size_10: size<1>, size<0> class field, [23:22]. */ ++ { 16, 1 }, /* SME_Q: Q class bit, bit 16. */ ++ { 15, 1 }, /* SME_V: (horizontal / vertical tiles), bit 15. */ ++ { 13, 2 }, /* SME_Rv: vector select register W12-W15, bits [14:13]. */ + { 13, 3 }, /* SME Pm second source scalable predicate register P0-P7. */ + { 11, 2 }, /* rotate1: FCMLA immediate rotate. */ + { 13, 2 }, /* rotate2: Indexed element FCMLA immediate rotate. */ +@@ -3355,6 +3360,16 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, + aarch64_get_qualifier_name (opnd->qualifier)); + break; + ++ case AARCH64_OPND_SME_ZA_HV_idx_src: ++ case AARCH64_OPND_SME_ZA_HV_idx_dest: ++ snprintf (buf, size, "za%d%c.%s[w%d, %d]", ++ opnd->za_tile_vector.regno, ++ opnd->za_tile_vector.v == 1 ? 'v' : 'h', ++ aarch64_get_qualifier_name (opnd->qualifier), ++ opnd->za_tile_vector.index.regno, ++ opnd->za_tile_vector.index.imm); ++ break; ++ + case AARCH64_OPND_CRn: + case AARCH64_OPND_CRm: + snprintf (buf, size, "C%" PRIi64, opnd->imm.value); +diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h +index ba19c12c..9c657dfb 100644 +--- a/opcodes/aarch64-opc.h ++++ b/opcodes/aarch64-opc.h +@@ -71,6 +71,7 @@ enum aarch64_field_kind + FLD_imm4, + FLD_imm4_2, + FLD_imm4_3, ++ FLD_imm4_5, + FLD_imm5, + FLD_imm7, + FLD_imm8, +@@ -152,6 +153,10 @@ enum aarch64_field_kind + FLD_SVE_xs_22, + FLD_SME_ZAda_2b, + FLD_SME_ZAda_3b, ++ FLD_SME_size_10, ++ FLD_SME_Q, ++ FLD_SME_V, ++ FLD_SME_Rv, + FLD_SME_Pm, + FLD_rotate1, + FLD_rotate2, +@@ -186,7 +191,7 @@ struct aarch64_operand + + /* The associated instruction bit-fields; no operand has more than 4 + bit-fields */ +- enum aarch64_field_kind fields[4]; ++ enum aarch64_field_kind fields[5]; + + /* Brief description */ + const char *desc; +diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h +index f725f2f0..5307cda4 100644 +--- a/opcodes/aarch64-tbl.h ++++ b/opcodes/aarch64-tbl.h +@@ -2203,6 +2203,14 @@ + { \ + QLF5(S_D,P_M,P_M,S_H,S_H) \ + } ++#define OP_SME_BHSDQ_PM_BHSDQ \ ++{ \ ++ QLF3(S_B,P_M,S_B), \ ++ QLF3(S_H,P_M,S_H), \ ++ QLF3(S_S,P_M,S_S), \ ++ QLF3(S_D,P_M,S_D), \ ++ QLF3(S_Q,P_M,S_Q) \ ++} + + /* e.g. UDOT .2S, .8B, .8B. */ + #define QL_V3DOT \ +@@ -5123,6 +5131,11 @@ const struct aarch64_opcode aarch64_opcode_table[] = + SME_INSN ("usmops", 0xa1800010, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_B_B, 0, 0), + SME_I64_INSN ("usmops", 0xa1c00010, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_H_H, 0, 0), + ++ SME_INSN ("mov", 0xc0020000, 0xff3e0200, sme_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SME_ZA_HV_idx_src), OP_SME_BHSDQ_PM_BHSDQ, 0, 0), ++ SME_INSN ("mov", 0xc0000000, 0xff3e0010, sme_misc, 0, OP3 (SME_ZA_HV_idx_dest, SVE_Pg3, SVE_Zn), OP_SME_BHSDQ_PM_BHSDQ, 0, 0), ++ SME_INSN ("mova", 0xc0020000, 0xff3e0200, sme_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SME_ZA_HV_idx_src), OP_SME_BHSDQ_PM_BHSDQ, 0, 0), ++ SME_INSN ("mova", 0xc0000000, 0xff3e0010, sme_misc, 0, OP3 (SME_ZA_HV_idx_dest, SVE_Pg3, SVE_Zn), OP_SME_BHSDQ_PM_BHSDQ, 0, 0), ++ + /* SIMD Dot Product (optional in v8.2-A). */ + DOT_INSN ("udot", 0x2e009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ), + DOT_INSN ("sdot", 0xe009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ), +@@ -5694,6 +5707,12 @@ const struct aarch64_opcode aarch64_opcode_table[] = + "an SME ZA tile ZA0-ZA3") \ + Y(SVE_REG, regno, "SME_ZAda_3b", 0, F(FLD_SME_ZAda_3b), \ + "an SME ZA tile ZA0-ZA7") \ ++ Y(SVE_REG, sme_za_hv_tiles, "SME_ZA_HV_idx_src", 0, \ ++ F(FLD_SME_size_10,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_5),\ ++ "an SME horizontal or vertical vector access register") \ ++ Y(SVE_REG, sme_za_hv_tiles, "SME_ZA_HV_idx_dest", 0, \ ++ F(FLD_SME_size_10,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_2),\ ++ "an SME horizontal or vertical vector access register") \ + Y(PRED_REG, regno, "SME_Pm", 0, F(FLD_SME_Pm), \ + "an SVE predicate register") \ + Y(IMMEDIATE, imm, "TME_UIMM16", 0, F(FLD_imm16), \ +-- +2.19.1 + diff --git a/SME-0004-aarch64-SME-Add-ZERO-instruction.patch b/SME-0004-aarch64-SME-Add-ZERO-instruction.patch new file mode 100644 index 0000000000000000000000000000000000000000..3c6ad2ccfdad8af98683ab85ea5c30e7f16897d1 --- /dev/null +++ b/SME-0004-aarch64-SME-Add-ZERO-instruction.patch @@ -0,0 +1,1618 @@ +From b0b2a9514e1d79387f744fbd765037959312cb14 Mon Sep 17 00:00:00 2001 +From: Przemyslaw Wirkus +Date: Wed, 17 Nov 2021 19:56:09 +0000 +Subject: [PATCH 04/10] aarch64: [SME] Add ZERO instruction + +Reference: https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=1cad938de57a1577e5fe4b4afcabe889a8b9b9d7 + +This patch is adding ZERO (a list of 64-bit element ZA tiles) +instruction. + +gas/ChangeLog: + + * config/tc-aarch64.c (parse_sme_list_of_64bit_tiles): + New parser. + (parse_operands): Handle OPND_SME_list_of_64bit_tiles. + * testsuite/gas/aarch64/sme-4-illegal.d: New test. + * testsuite/gas/aarch64/sme-4-illegal.l: New test. + * testsuite/gas/aarch64/sme-4-illegal.s: New test. + * testsuite/gas/aarch64/sme-4.d: New test. + * testsuite/gas/aarch64/sme-4.s: New test. + +include/ChangeLog: + + * opcode/aarch64.h (enum aarch64_opnd): New operand + AARCH64_OPND_SME_list_of_64bit_tiles. + +opcodes/ChangeLog: + + * aarch64-opc.c (print_sme_za_list): New printing function. + (aarch64_print_operand): Handle OPND_SME_list_of_64bit_tiles. + * aarch64-opc.h (enum aarch64_field_kind): New bitfield + FLD_SME_zero_mask. + * aarch64-tbl.h (struct aarch64_opcode): New ZERO instruction. + aarch64-asm-2.c: Regenerate. + aarch64-dis-2.c: Regenerate. + aarch64-opc-2.c: Regenerate. +--- + gas/config/tc-aarch64.c | 104 ++++++++ + gas/testsuite/gas/aarch64/sme-4-illegal.d | 3 + + gas/testsuite/gas/aarch64/sme-4-illegal.l | 29 +++ + gas/testsuite/gas/aarch64/sme-4-illegal.s | 32 +++ + gas/testsuite/gas/aarch64/sme-4.d | 71 ++++++ + gas/testsuite/gas/aarch64/sme-4.s | 95 +++++++ + include/opcode/aarch64.h | 1 + + opcodes/aarch64-asm-2.c | 3 +- + opcodes/aarch64-dis-2.c | 290 +++++++++++----------- + opcodes/aarch64-opc-2.c | 1 + + opcodes/aarch64-opc.c | 45 ++++ + opcodes/aarch64-opc.h | 1 + + opcodes/aarch64-tbl.h | 4 + + 13 files changed, 539 insertions(+), 140 deletions(-) + create mode 100644 gas/testsuite/gas/aarch64/sme-4-illegal.d + create mode 100644 gas/testsuite/gas/aarch64/sme-4-illegal.l + create mode 100644 gas/testsuite/gas/aarch64/sme-4-illegal.s + create mode 100644 gas/testsuite/gas/aarch64/sme-4.d + create mode 100644 gas/testsuite/gas/aarch64/sme-4.s + +diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c +index bb618b8d..33073bc9 100644 +--- a/gas/config/tc-aarch64.c ++++ b/gas/config/tc-aarch64.c +@@ -4508,6 +4508,103 @@ parse_sme_za_hv_tiles_operand (char **str, + return regno; + } + ++/* Parse list of up to eight 64-bit element tile names separated by commas in ++ SME's ZERO instruction: ++ ++ ZERO { } ++ ++ Function returns : ++ ++ an 8-bit list of 64-bit element tiles named ZA0.D to ZA7.D. ++*/ ++static int ++parse_sme_zero_mask(char **str) ++{ ++ char *q; ++ int mask; ++ aarch64_opnd_qualifier_t qualifier; ++ ++ mask = 0x00; ++ q = *str; ++ do ++ { ++ const reg_entry *reg = parse_reg_with_qual (&q, REG_TYPE_ZA, &qualifier); ++ if (reg) ++ { ++ int regno = reg->number; ++ if (qualifier == AARCH64_OPND_QLF_S_B && regno == 0) ++ { ++ /* { ZA0.B } is assembled as all-ones immediate. */ ++ mask = 0xff; ++ } ++ else if (qualifier == AARCH64_OPND_QLF_S_H && regno < 2) ++ mask |= 0x55 << regno; ++ else if (qualifier == AARCH64_OPND_QLF_S_S && regno < 4) ++ mask |= 0x11 << regno; ++ else if (qualifier == AARCH64_OPND_QLF_S_D && regno < 8) ++ mask |= 0x01 << regno; ++ else ++ { ++ set_syntax_error (_("wrong ZA tile element format")); ++ return PARSE_FAIL; ++ } ++ continue; ++ } ++ else if (strncasecmp (q, "za", 2) == 0 ++ && !ISALNUM (q[2])) ++ { ++ /* { ZA } is assembled as all-ones immediate. */ ++ mask = 0xff; ++ q += 2; ++ continue; ++ } ++ else ++ { ++ set_syntax_error (_("wrong ZA tile element format")); ++ return PARSE_FAIL; ++ } ++ } ++ while (skip_past_char (&q, ',')); ++ ++ *str = q; ++ return mask; ++} ++ ++/* Wraps in curly braces operand ZERO instruction: ++ ++ ZERO { } ++ ++ Function returns value of bit-field. ++*/ ++static int ++parse_sme_list_of_64bit_tiles (char **str) ++{ ++ int regno; ++ ++ if (!skip_past_char (str, '{')) ++ { ++ set_syntax_error (_("expected '{'")); ++ return PARSE_FAIL; ++ } ++ ++ /* Empty list is an all-zeros immediate. */ ++ if (!skip_past_char (str, '}')) ++ { ++ regno = parse_sme_zero_mask (str); ++ if (regno == PARSE_FAIL) ++ return PARSE_FAIL; ++ ++ if (!skip_past_char (str, '}')) ++ { ++ set_syntax_error (_("expected '}'")); ++ return PARSE_FAIL; ++ } ++ } ++ else ++ regno = 0x00; ++ ++ return regno; ++} + + /* Parse a system register or a PSTATE field name for an MSR/MRS instruction. + Returns the encoding for the option, or PARSE_FAIL. +@@ -7242,6 +7339,13 @@ parse_operands (char *str, const aarch64_opcode *opcode) + break; + } + ++ case AARCH64_OPND_SME_list_of_64bit_tiles: ++ val = parse_sme_list_of_64bit_tiles (&str); ++ if (val == PARSE_FAIL) ++ goto failure; ++ info->imm.value = val; ++ break; ++ + default: + as_fatal (_("unhandled operand code %d"), operands[i]); + } +diff --git a/gas/testsuite/gas/aarch64/sme-4-illegal.d b/gas/testsuite/gas/aarch64/sme-4-illegal.d +new file mode 100644 +index 00000000..b5d0543b +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/sme-4-illegal.d +@@ -0,0 +1,3 @@ ++#as: -march=armv8-a+sme ++#source: sme-4-illegal.s ++#error_output: sme-4-illegal.l +diff --git a/gas/testsuite/gas/aarch64/sme-4-illegal.l b/gas/testsuite/gas/aarch64/sme-4-illegal.l +new file mode 100644 +index 00000000..ae7d6543 +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/sme-4-illegal.l +@@ -0,0 +1,29 @@ ++[^:]*: Assembler messages: ++[^:]*:[0-9]+: Error: expected '{' at operand 1 -- `zero za' ++[^:]*:[0-9]+: Error: wrong ZA tile element format at operand 1 -- `zero {za8\.d}' ++[^:]*:[0-9]+: Error: wrong ZA tile element format at operand 1 -- `zero {za0\.d,za8.d}' ++[^:]*:[0-9]+: Error: wrong ZA tile element format at operand 1 -- `zero {za2\.h}' ++[^:]*:[0-9]+: Error: wrong ZA tile element format at operand 1 -- `zero {za4\.s}' ++[^:]*:[0-9]+: Error: wrong ZA tile element format at operand 1 -- `zero {za1\.s,za4.s}' ++[^:]*:[0-9]+: Error: wrong ZA tile element format at operand 1 -- `zero {za0\.d,za3.s,za2.h}' ++[^:]*:[0-9]+: Error: wrong ZA tile element format at operand 1 -- `zero {za1.b}' ++[^:]*:[0-9]+: Error: unexpected comma after the mnemonic name `zero' -- `zero ,' ++[^:]*:[0-9]+: Error: wrong ZA tile element format at operand 1 -- `zero {' ++[^:]*:[0-9]+: Error: wrong ZA tile element format at operand 1 -- `zero {,' ++[^:]*:[0-9]+: Error: expected '{' at operand 1 -- `zero }' ++[^:]*:[0-9]+: Error: wrong ZA tile element format at operand 1 -- `zero {,}' ++[^:]*:[0-9]+: Error: wrong ZA tile element format at operand 1 -- `zero {,,}' ++[^:]*:[0-9]+: Error: wrong ZA tile element format at operand 1 -- `zero {za0}' ++[^:]*:[0-9]+: Error: wrong ZA tile element format at operand 1 -- `zero {,za0.d}' ++[^:]*:[0-9]+: Error: wrong ZA tile element format at operand 1 -- `zero {za0.d,}' ++[^:]*:[0-9]+: Error: wrong ZA tile element format at operand 1 -- `zero {za0.d,za1.d,}' ++[^:]*:[0-9]+: Error: wrong ZA tile element format at operand 1 -- `zero {za,}' ++[^:]*:[0-9]+: Error: expected '}' at operand 1 -- `zero {za.}' ++[^:]*:[0-9]+: Error: expected '}' at operand 1 -- `zero {za-}' ++[^:]*:[0-9]+: Error: expected '}' at operand 1 -- `zero {za_}' ++[^:]*:[0-9]+: Error: expected '}' at operand 1 -- `zero {za#}' ++[^:]*:[0-9]+: Error: wrong ZA tile element format at operand 1 -- `zero {zaX}' ++[^:]*:[0-9]+: Error: wrong ZA tile element format at operand 1 -- `zero {za0}' ++[^:]*:[0-9]+: Error: wrong ZA tile element format at operand 1 -- `zero {zax}' ++[^:]*:[0-9]+: Error: expected '}' at operand 1 -- `zero {za{}' ++[^:]*:[0-9]+: Error: unexpected characters following instruction at operand 1 -- `zero {za}}' +diff --git a/gas/testsuite/gas/aarch64/sme-4-illegal.s b/gas/testsuite/gas/aarch64/sme-4-illegal.s +new file mode 100644 +index 00000000..db0fbf6c +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/sme-4-illegal.s +@@ -0,0 +1,32 @@ ++/* Scalable Matrix Extension (SME). */ ++ ++zero za ++zero { za8.d } ++zero { za0.d, za8.d } ++zero { za2.h } ++zero { za4.s } ++zero { za1.s, za4.s } ++zero { za0.d, za3.s, za2.h } ++zero { za1.b } ++ ++/* Parser checks. */ ++zero , ++zero { ++zero { , ++zero } ++zero { , } ++zero { , , } ++zero { za0 } ++zero { , za0.d } ++zero { za0.d , } ++zero { za0.d , za1.d , } ++zero { za, } ++zero { za. } ++zero { za- } ++zero { za_ } ++zero { za# } ++zero { zaX } ++zero { za0 } ++zero { zax } ++zero { za{ } ++zero { za} } +diff --git a/gas/testsuite/gas/aarch64/sme-4.d b/gas/testsuite/gas/aarch64/sme-4.d +new file mode 100644 +index 00000000..7e498e76 +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/sme-4.d +@@ -0,0 +1,71 @@ ++#name: SME extension (ZERO) ++#as: -march=armv8-a+sme ++#objdump: -dr ++ ++.*: file format .* ++ ++Disassembly of section \.text: ++ ++0+ <.*>: ++ 0: c0080000 zero {} ++ 4: c00800ff zero {za} ++ 8: c00800ff zero {za} ++ c: c00800ff zero {za} ++ 10: c00800ff zero {za} ++ 14: c00800ff zero {za} ++ 18: c0080001 zero {za0\.d} ++ 1c: c0080002 zero {za1\.d} ++ 20: c0080004 zero {za2\.d} ++ 24: c0080008 zero {za3\.d} ++ 28: c0080010 zero {za4\.d} ++ 2c: c0080020 zero {za5\.d} ++ 30: c0080040 zero {za6\.d} ++ 34: c0080080 zero {za7\.d} ++ 38: c0080001 zero {za0\.d} ++ 3c: c0080003 zero {za0\.d, za1\.d} ++ 40: c0080007 zero {za0\.d, za1\.d, za2\.d} ++ 44: c008000f zero {za0\.d, za1\.d, za2\.d, za3\.d} ++ 48: c008001f zero {za0\.s, za1\.d, za2\.d, za3\.d} ++ 4c: c008003f zero {za0\.s, za1\.s, za2\.d, za3\.d} ++ 50: c008007f zero {za0\.h, za1\.s, za3\.d} ++ 54: c00800ff zero {za} ++ 58: c0080080 zero {za7\.d} ++ 5c: c00800c0 zero {za6\.d, za7\.d} ++ 60: c00800e0 zero {za5\.d, za6\.d, za7\.d} ++ 64: c00800f0 zero {za4\.d, za5\.d, za6\.d, za7\.d} ++ 68: c00800f8 zero {za3\.s, za4\.d, za5\.d, za6\.d} ++ 6c: c00800fc zero {za2\.s, za3\.s, za4\.d, za5\.d} ++ 70: c00800fe zero {za1\.h, za2\.s, za4\.d} ++ 74: c00800ff zero {za} ++ 78: c00800fe zero {za1\.h, za2\.s, za4\.d} ++ 7c: c00800fd zero {za0\.h, za3\.s, za5\.d} ++ 80: c00800fb zero {za1\.h, za0\.s, za6\.d} ++ 84: c00800f7 zero {za0\.h, za1\.s, za7\.d} ++ 88: c00800ef zero {za1\.h, za2\.s, za0\.d} ++ 8c: c00800df zero {za0\.h, za3\.s, za1\.d} ++ 90: c00800bf zero {za1\.h, za0\.s, za2\.d} ++ 94: c008007f zero {za0\.h, za1\.s, za3\.d} ++ 98: c0080055 zero {za0\.h} ++ 9c: c00800aa zero {za1\.h} ++ a0: c0080011 zero {za0\.s} ++ a4: c0080022 zero {za1\.s} ++ a8: c0080044 zero {za2\.s} ++ ac: c0080088 zero {za3\.s} ++ b0: c0080055 zero {za0\.h} ++ b4: c0080055 zero {za0\.h} ++ b8: c0080055 zero {za0\.h} ++ bc: c00800aa zero {za1\.h} ++ c0: c00800aa zero {za1\.h} ++ c4: c00800aa zero {za1\.h} ++ c8: c0080011 zero {za0\.s} ++ cc: c0080022 zero {za1\.s} ++ d0: c0080044 zero {za2\.s} ++ d4: c0080088 zero {za3\.s} ++ d8: c00800d5 zero {za0.h, za7.d} ++ dc: c00800ab zero {za1.h, za0.d} ++ e0: c0080015 zero {za0.s, za2.d} ++ e4: c008002a zero {za1.s, za3.d} ++ e8: c0080054 zero {za2.s, za4.d} ++ ec: c00800a8 zero {za3.s, za5.d} ++ f0: c00800d5 zero {za0.h, za7.d} ++ f4: c0080015 zero {za0.s, za2.d} +diff --git a/gas/testsuite/gas/aarch64/sme-4.s b/gas/testsuite/gas/aarch64/sme-4.s +new file mode 100644 +index 00000000..1fcd3787 +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/sme-4.s +@@ -0,0 +1,95 @@ ++/* SME Extension (ZERO). */ ++ ++/* An all-zeros immediate is disassembled as an empty list { }. */ ++zero { } ++ ++/* An all-ones immediate is disassembled as {ZA}. */ ++zero { za } ++zero { za0.b } ++zero { za0.h, za1.h } ++zero { za0.d, za1.d, za2.d, za3.d, za4.d, za5.d, za6.d, za7.d } ++zero { za7.d, za6.d, za5.d, za4.d, za3.d, za2.d, za1.d, za0.d } ++ ++/* Set each bit individually. */ ++zero { za0.d } ++zero { za1.d } ++zero { za2.d } ++zero { za3.d } ++zero { za4.d } ++zero { za5.d } ++zero { za6.d } ++zero { za7.d } ++ ++/* Random bits. */ ++zero { za0.d } ++zero { za0.d, za1.d } ++zero { za0.d, za1.d, za2.d } ++zero { za0.d, za1.d, za2.d, za3.d } ++zero { za0.d, za1.d, za2.d, za3.d, za4.d } ++zero { za0.d, za1.d, za2.d, za3.d, za4.d, za5.d } ++zero { za0.d, za1.d, za2.d, za3.d, za4.d, za5.d, za6.d } ++zero { za0.d, za1.d, za2.d, za3.d, za4.d, za5.d, za6.d, za7.d } ++ ++zero { za7.d } ++zero { za7.d, za6.d } ++zero { za7.d, za6.d, za5.d } ++zero { za7.d, za6.d, za5.d, za4.d } ++zero { za7.d, za6.d, za5.d, za4.d, za3.d } ++zero { za7.d, za6.d, za5.d, za4.d, za3.d, za2.d } ++zero { za7.d, za6.d, za5.d, za4.d, za3.d, za2.d, za1.d } ++zero { za7.d, za6.d, za5.d, za4.d, za3.d, za2.d, za1.d, za0.d } ++ ++zero { za1.d, za2.d, za3.d, za4.d, za5.d, za6.d, za7.d } ++zero { za0.d, za2.d, za3.d, za4.d, za5.d, za6.d, za7.d } ++zero { za0.d, za1.d, za3.d, za4.d, za5.d, za6.d, za7.d } ++zero { za0.d, za1.d, za2.d, za4.d, za5.d, za6.d, za7.d } ++zero { za0.d, za1.d, za2.d, za3.d, za5.d, za6.d, za7.d } ++zero { za0.d, za1.d, za2.d, za3.d, za4.d, za6.d, za7.d } ++zero { za0.d, za1.d, za2.d, za3.d, za4.d, za5.d, za7.d } ++zero { za0.d, za1.d, za2.d, za3.d, za4.d, za5.d, za6.d } ++ ++/* For programmer convenience an assembler must also accept the names of ++ 32-bit, 16-bit and 8-bit element tiles. ++*/ ++zero { za0.h } ++zero { za1.h } ++zero { za0.s } ++zero { za1.s } ++zero { za2.s } ++zero { za3.s } ++ ++/* The preferred disassembly of this instruction uses the shortest list of tile ++ names that represent the encoded immediate mask. ++*/ ++ ++/* To za0.h */ ++zero { za0.d, za2.d, za4.d, za6.d } ++zero { za0.s, za2.s } ++zero { za0.h } ++ ++/* To za1.h */ ++zero { za1.d, za3.d, za5.d, za7.d } ++zero { za1.s, za3.s } ++zero { za1.h } ++ ++/* To za[0-3].s */ ++zero { za0.d, za4.d } ++zero { za1.d, za5.d } ++zero { za2.d, za6.d } ++zero { za3.d, za7.d } ++ ++/* Mix of suffixed. */ ++zero { za0.h, za7.d } ++zero { za1.h, za0.d } ++zero { za0.s, za2.d } ++zero { za1.s, za3.d } ++zero { za2.s, za4.d } ++zero { za3.s, za5.d } ++ ++/* Register aliases. */ ++foo .req za0 ++bar .req za2 ++baz .req za7 ++ ++zero { foo.h, baz.d } ++zero { za0.s, bar.d } +diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h +index 23e3ce0a..f5ce036e 100644 +--- a/include/opcode/aarch64.h ++++ b/include/opcode/aarch64.h +@@ -445,6 +445,7 @@ enum aarch64_opnd + AARCH64_OPND_SME_ZA_HV_idx_src, /* SME source ZA tile vector. */ + AARCH64_OPND_SME_ZA_HV_idx_dest, /* SME destination ZA tile vector. */ + AARCH64_OPND_SME_Pm, /* SME scalable predicate register, bits [15:13]. */ ++ AARCH64_OPND_SME_list_of_64bit_tiles, /* SME list of ZA tiles. */ + AARCH64_OPND_TME_UIMM16, /* TME unsigned 16-bit immediate. */ + AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */ + }; +diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c +index eda943eb..0e048424 100644 +--- a/opcodes/aarch64-asm-2.c ++++ b/opcodes/aarch64-asm-2.c +@@ -675,7 +675,7 @@ aarch64_insert_operand (const aarch64_operand *self, + case 33: + case 34: + case 35: +- case 215: ++ case 216: + return aarch64_ins_reglane (self, info, code, inst, errors); + case 36: + return aarch64_ins_reglist (self, info, code, inst, errors); +@@ -721,6 +721,7 @@ aarch64_insert_operand (const aarch64_operand *self, + case 188: + case 189: + case 214: ++ case 215: + return aarch64_ins_imm (self, info, code, inst, errors); + case 44: + case 45: +diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c +index 6bde0f35..9dd9402a 100644 +--- a/opcodes/aarch64-dis-2.c ++++ b/opcodes/aarch64-dis-2.c +@@ -96,55 +96,66 @@ aarch64_opcode_lookup_1 (uint32_t word) + { + if (((word >> 17) & 0x1) == 0) + { +- if (((word >> 20) & 0x1) == 0) +- { +- /* 33222222222211111111110000000000 +- 10987654321098765432109876543210 +- x1000000xx00xx0xxxxxxxxxxxxxxxxx +- mov. */ +- return 2377; +- } +- else ++ if (((word >> 19) & 0x1) == 0) + { +- if (((word >> 16) & 0x1) == 0) ++ if (((word >> 20) & 0x1) == 0) + { +- if (((word >> 22) & 0x1) == 0) +- { +- /* 33222222222211111111110000000000 +- 10987654321098765432109876543210 +- x1000000x001xx00xxxxxxxxxxxxxxxx +- addha. */ +- return 2348; +- } +- else +- { +- /* 33222222222211111111110000000000 +- 10987654321098765432109876543210 +- x1000000x101xx00xxxxxxxxxxxxxxxx +- addha. */ +- return 2349; +- } ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ x1000000xx000x0xxxxxxxxxxxxxxxxx ++ mov. */ ++ return 2377; + } + else + { +- if (((word >> 22) & 0x1) == 0) ++ if (((word >> 16) & 0x1) == 0) + { +- /* 33222222222211111111110000000000 +- 10987654321098765432109876543210 +- x1000000x001xx01xxxxxxxxxxxxxxxx +- addva. */ +- return 2350; ++ if (((word >> 22) & 0x1) == 0) ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ x1000000x0010x00xxxxxxxxxxxxxxxx ++ addha. */ ++ return 2348; ++ } ++ else ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ x1000000x1010x00xxxxxxxxxxxxxxxx ++ addha. */ ++ return 2349; ++ } + } + else + { +- /* 33222222222211111111110000000000 +- 10987654321098765432109876543210 +- x1000000x101xx01xxxxxxxxxxxxxxxx +- addva. */ +- return 2351; ++ if (((word >> 22) & 0x1) == 0) ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ x1000000x0010x01xxxxxxxxxxxxxxxx ++ addva. */ ++ return 2350; ++ } ++ else ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ x1000000x1010x01xxxxxxxxxxxxxxxx ++ addva. */ ++ return 2351; ++ } + } + } + } ++ else ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ x1000000xx0x1x0xxxxxxxxxxxxxxxxx ++ zero. */ ++ return 2380; ++ } + } + else + { +@@ -2753,7 +2764,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 00011001000xxxxxxxxx00xxxxxxxxxx + stlurb. */ +- return 2420; ++ return 2421; + } + else + { +@@ -2761,7 +2772,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 10011001000xxxxxxxxx00xxxxxxxxxx + stlur. */ +- return 2428; ++ return 2429; + } + } + else +@@ -2772,7 +2783,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 01011001000xxxxxxxxx00xxxxxxxxxx + stlurh. */ +- return 2424; ++ return 2425; + } + else + { +@@ -2780,7 +2791,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 11011001000xxxxxxxxx00xxxxxxxxxx + stlur. */ +- return 2431; ++ return 2432; + } + } + } +@@ -2860,7 +2871,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 00011001010xxxxxxxxx00xxxxxxxxxx + ldapurb. */ +- return 2421; ++ return 2422; + } + else + { +@@ -2868,7 +2879,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 10011001010xxxxxxxxx00xxxxxxxxxx + ldapur. */ +- return 2429; ++ return 2430; + } + } + else +@@ -2879,7 +2890,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 01011001010xxxxxxxxx00xxxxxxxxxx + ldapurh. */ +- return 2425; ++ return 2426; + } + else + { +@@ -2887,7 +2898,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 11011001010xxxxxxxxx00xxxxxxxxxx + ldapur. */ +- return 2432; ++ return 2433; + } + } + } +@@ -2970,7 +2981,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 00011001100xxxxxxxxx00xxxxxxxxxx + ldapursb. */ +- return 2423; ++ return 2424; + } + else + { +@@ -2978,7 +2989,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 10011001100xxxxxxxxx00xxxxxxxxxx + ldapursw. */ +- return 2430; ++ return 2431; + } + } + else +@@ -2987,7 +2998,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1011001100xxxxxxxxx00xxxxxxxxxx + ldapursh. */ +- return 2427; ++ return 2428; + } + } + else +@@ -2998,7 +3009,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x0011001110xxxxxxxxx00xxxxxxxxxx + ldapursb. */ +- return 2422; ++ return 2423; + } + else + { +@@ -3006,7 +3017,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1011001110xxxxxxxxx00xxxxxxxxxx + ldapursh. */ +- return 2426; ++ return 2427; + } + } + } +@@ -3492,7 +3503,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xxx11010x00xxxxxx0xx10xxxxxxxxxx + setf8. */ +- return 2418; ++ return 2419; + } + else + { +@@ -3500,7 +3511,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xxx11010x00xxxxxx1xx10xxxxxxxxxx + setf16. */ +- return 2419; ++ return 2420; + } + } + else +@@ -3646,7 +3657,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xxx11010000xxxxxxxxx01xxxxxxxxxx + rmif. */ +- return 2417; ++ return 2418; + } + else + { +@@ -4695,7 +4706,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x01x1xxxxx000110xxxxxxxxxx + usdot. */ +- return 2437; ++ return 2438; + } + } + } +@@ -4769,7 +4780,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x01x1xxxxx000111xxxxxxxxxx + sudot. */ +- return 2438; ++ return 2439; + } + } + } +@@ -7388,7 +7399,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0xx0xxxxx011110xxxxxxxxxx + usdot. */ +- return 2436; ++ return 2437; + } + } + } +@@ -9092,7 +9103,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0100xxx10101xxxxxxxxxxxxx + bfcvtnt. */ +- return 2465; ++ return 2466; + } + } + else +@@ -9335,7 +9346,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x00x1xxxxxx00xxxxxxxxxxxxx + ld1rob. */ +- return 2441; ++ return 2442; + } + else + { +@@ -9343,7 +9354,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x01x1xxxxxx00xxxxxxxxxxxxx + ld1roh. */ +- return 2442; ++ return 2443; + } + } + else +@@ -9575,7 +9586,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0011xxxxx010xxxxxxxxxxxxx + bfdot. */ +- return 2462; ++ return 2463; + } + else + { +@@ -9596,7 +9607,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0111xxxxx010xx0xxxxxxxxxx + bfmlalb. */ +- return 2469; ++ return 2470; + } + else + { +@@ -9604,7 +9615,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0111xxxxx010xx1xxxxxxxxxx + bfmlalt. */ +- return 2468; ++ return 2469; + } + } + else +@@ -9659,7 +9670,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x11001x0011xxxxx1x0xxxxxxxxxxxxx + bfdot. */ +- return 2461; ++ return 2462; + } + else + { +@@ -9671,7 +9682,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0111xxxxx1x0xx0xxxxxxxxxx + bfmlalb. */ +- return 2467; ++ return 2468; + } + else + { +@@ -9679,7 +9690,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0111xxxxx1x0xx1xxxxxxxxxx + bfmlalt. */ +- return 2466; ++ return 2467; + } + } + else +@@ -9730,7 +9741,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x00x1xxxxx001xxxxxxxxxxxxx + ld1rob. */ +- return 2445; ++ return 2446; + } + else + { +@@ -9738,7 +9749,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x01x1xxxxx001xxxxxxxxxxxxx + ld1roh. */ +- return 2446; ++ return 2447; + } + } + else +@@ -10097,7 +10108,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0101xxxxx111xxxxxxxxxxxxx + fmmla. */ +- return 2439; ++ return 2440; + } + else + { +@@ -10130,7 +10141,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0011xxxxx111xxxxxxxxxxxxx + bfmmla. */ +- return 2463; ++ return 2464; + } + else + { +@@ -10160,7 +10171,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0111xxxxx111xxxxxxxxxxxxx + fmmla. */ +- return 2440; ++ return 2441; + } + else + { +@@ -10289,7 +10300,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1101xxxxx000x00xxxxxxxxxx + zip1. */ +- return 2449; ++ return 2450; + } + else + { +@@ -10299,7 +10310,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1101xxxxx000010xxxxxxxxxx + uzp1. */ +- return 2451; ++ return 2452; + } + else + { +@@ -10307,7 +10318,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1101xxxxx000110xxxxxxxxxx + trn1. */ +- return 2453; ++ return 2454; + } + } + } +@@ -10319,7 +10330,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1101xxxxx000x01xxxxxxxxxx + zip2. */ +- return 2450; ++ return 2451; + } + else + { +@@ -10329,7 +10340,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1101xxxxx000011xxxxxxxxxx + uzp2. */ +- return 2452; ++ return 2453; + } + else + { +@@ -10337,7 +10348,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1101xxxxx000111xxxxxxxxxx + trn2. */ +- return 2454; ++ return 2455; + } + } + } +@@ -11385,7 +11396,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1000xxxxx100110xxxxxxxxxx + smmla. */ +- return 2433; ++ return 2434; + } + else + { +@@ -11393,7 +11404,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1100xxxxx100110xxxxxxxxxx + usmmla. */ +- return 2435; ++ return 2436; + } + } + else +@@ -11402,7 +11413,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1x10xxxxx100110xxxxxxxxxx + ummla. */ +- return 2434; ++ return 2435; + } + } + } +@@ -12898,7 +12909,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x10x1xxxxx000xxxxxxxxxxxxx + ld1row. */ +- return 2443; ++ return 2444; + } + else + { +@@ -12906,7 +12917,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x11x1xxxxx000xxxxxxxxxxxxx + ld1rod. */ +- return 2444; ++ return 2445; + } + } + } +@@ -13280,7 +13291,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x10x1xxxxx001xxxxxxxxxxxxx + ld1row. */ +- return 2447; ++ return 2448; + } + else + { +@@ -13288,7 +13299,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x11x1xxxxx001xxxxxxxxxxxxx + ld1rod. */ +- return 2448; ++ return 2449; + } + } + } +@@ -14722,7 +14733,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x110001x10101xxxxxxxxxxxxx + bfcvt. */ +- return 2464; ++ return 2465; + } + } + else +@@ -16791,7 +16802,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 0x001110xx0xxxxx1x1001xxxxxxxxxx + smmla. */ +- return 2455; ++ return 2456; + } + } + } +@@ -16824,7 +16835,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 0x001110xx0xxxxx1x0101xxxxxxxxxx + sdot. */ +- return 2381; ++ return 2382; + } + } + else +@@ -16898,7 +16909,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 0x001110xx0xxxxx1x1011xxxxxxxxxx + usmmla. */ +- return 2457; ++ return 2458; + } + } + } +@@ -16931,7 +16942,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 0x001110xx0xxxxx1x0111xxxxxxxxxx + usdot. */ +- return 2458; ++ return 2459; + } + } + else +@@ -16978,7 +16989,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110000xxxxxxxxxxxxxxxxxxxxx + eor3. */ +- return 2388; ++ return 2389; + } + else + { +@@ -16986,7 +16997,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110100xxxxxxxxxxxxxxxxxxxxx + xar. */ +- return 2390; ++ return 2391; + } + } + else +@@ -16997,7 +17008,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110x10xxxxx0xxxxxxxxxxxxxxx + sm3ss1. */ +- return 2392; ++ return 2393; + } + else + { +@@ -17011,7 +17022,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110010xxxxx1xxx00xxxxxxxxxx + sm3tt1a. */ +- return 2393; ++ return 2394; + } + else + { +@@ -17019,7 +17030,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110110xxxxx1xxx00xxxxxxxxxx + sha512su0. */ +- return 2386; ++ return 2387; + } + } + else +@@ -17028,7 +17039,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110x10xxxxx1xxx10xxxxxxxxxx + sm3tt2a. */ +- return 2395; ++ return 2396; + } + } + else +@@ -17041,7 +17052,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110010xxxxx1xxx01xxxxxxxxxx + sm3tt1b. */ +- return 2394; ++ return 2395; + } + else + { +@@ -17049,7 +17060,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110110xxxxx1xxx01xxxxxxxxxx + sm4e. */ +- return 2399; ++ return 2400; + } + } + else +@@ -17058,7 +17069,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110x10xxxxx1xxx11xxxxxxxxxx + sm3tt2b. */ +- return 2396; ++ return 2397; + } + } + } +@@ -17239,7 +17250,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx101110xx0xxxxx100101xxxxxxxxxx + udot. */ +- return 2380; ++ return 2381; + } + } + else +@@ -17270,7 +17281,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx101110xx0xxxxx101x01xxxxxxxxxx + ummla. */ +- return 2456; ++ return 2457; + } + else + { +@@ -17289,7 +17300,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx101110xx0xxxxx1x1011xxxxxxxxxx + bfmmla. */ +- return 2472; ++ return 2473; + } + else + { +@@ -17299,7 +17310,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx1011100x0xxxxx1x1111xxxxxxxxxx + bfdot. */ +- return 2470; ++ return 2471; + } + else + { +@@ -17309,7 +17320,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x01011101x0xxxxx1x1111xxxxxxxxxx + bfmlalb. */ +- return 2477; ++ return 2478; + } + else + { +@@ -17317,7 +17328,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x11011101x0xxxxx1x1111xxxxxxxxxx + bfmlalt. */ +- return 2476; ++ return 2477; + } + } + } +@@ -17901,7 +17912,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000011101x1xxxx1011010xxxxxxxxxx + bfcvtn. */ +- return 2473; ++ return 2474; + } + else + { +@@ -17909,7 +17920,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010011101x1xxxx1011010xxxxxxxxxx + bfcvtn2. */ +- return 2474; ++ return 2475; + } + } + } +@@ -18227,7 +18238,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110xx1xxxxx0xxxxxxxxxxxxxxx + bcax. */ +- return 2391; ++ return 2392; + } + } + else +@@ -18838,7 +18849,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 11001110xx1xxxxx100000xxxxxxxxxx + sha512h. */ +- return 2384; ++ return 2385; + } + } + } +@@ -18890,7 +18901,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 11001110xx1xxxxx110000xxxxxxxxxx + sm3partw1. */ +- return 2397; ++ return 2398; + } + } + } +@@ -19133,7 +19144,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110xx1xxxxx100010xxxxxxxxxx + sha512su1. */ +- return 2387; ++ return 2388; + } + } + else +@@ -19209,7 +19220,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x0011100x1xxxxx110010xxxxxxxxxx + sm4ekey. */ +- return 2400; ++ return 2401; + } + } + else +@@ -20035,7 +20046,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110xx1xxxxx100001xxxxxxxxxx + sha512h2. */ +- return 2385; ++ return 2386; + } + } + else +@@ -20067,7 +20078,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x0011100x1xxxxx110001xxxxxxxxxx + sm3partw2. */ +- return 2398; ++ return 2399; + } + } + else +@@ -20307,7 +20318,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110xx1xxxxx100011xxxxxxxxxx + rax1. */ +- return 2389; ++ return 2390; + } + } + else +@@ -20339,7 +20350,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x01011100x1xxxxx110011xxxxxxxxxx + fmlal2. */ +- return 2403; ++ return 2404; + } + else + { +@@ -20347,7 +20358,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x11011100x1xxxxx110011xxxxxxxxxx + fmlal2. */ +- return 2407; ++ return 2408; + } + } + } +@@ -20369,7 +20380,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x01011101x1xxxxx110011xxxxxxxxxx + fmlsl2. */ +- return 2404; ++ return 2405; + } + else + { +@@ -20377,7 +20388,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x11011101x1xxxxx110011xxxxxxxxxx + fmlsl2. */ +- return 2408; ++ return 2409; + } + } + } +@@ -20416,7 +20427,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x00011100x1xxxxx111011xxxxxxxxxx + fmlal. */ +- return 2401; ++ return 2402; + } + else + { +@@ -20424,7 +20435,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x10011100x1xxxxx111011xxxxxxxxxx + fmlal. */ +- return 2405; ++ return 2406; + } + } + else +@@ -20446,7 +20457,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x00011101x1xxxxx111011xxxxxxxxxx + fmlsl. */ +- return 2402; ++ return 2403; + } + else + { +@@ -20454,7 +20465,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x10011101x1xxxxx111011xxxxxxxxxx + fmlsl. */ +- return 2406; ++ return 2407; + } + } + else +@@ -22262,7 +22273,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x0001111xxxxxxxx0000x0xxxxxxxxxx + fmlal. */ +- return 2409; ++ return 2410; + } + else + { +@@ -22270,7 +22281,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1001111xxxxxxxx0000x0xxxxxxxxxx + fmlal. */ +- return 2413; ++ return 2414; + } + } + else +@@ -22292,7 +22303,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x0001111xxxxxxxx0100x0xxxxxxxxxx + fmlsl. */ +- return 2410; ++ return 2411; + } + else + { +@@ -22300,7 +22311,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1001111xxxxxxxx0100x0xxxxxxxxxx + fmlsl. */ +- return 2414; ++ return 2415; + } + } + else +@@ -22806,7 +22817,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x0101111xxxxxxxx1000x0xxxxxxxxxx + fmlal2. */ +- return 2411; ++ return 2412; + } + else + { +@@ -22814,7 +22825,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1101111xxxxxxxx1000x0xxxxxxxxxx + fmlal2. */ +- return 2415; ++ return 2416; + } + } + } +@@ -22836,7 +22847,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x0101111xxxxxxxx1100x0xxxxxxxxxx + fmlsl2. */ +- return 2412; ++ return 2413; + } + else + { +@@ -22844,7 +22855,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1101111xxxxxxxx1100x0xxxxxxxxxx + fmlsl2. */ +- return 2416; ++ return 2417; + } + } + } +@@ -22900,7 +22911,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx001111xxxxxxxx1110x0xxxxxxxxxx + sdot. */ +- return 2383; ++ return 2384; + } + else + { +@@ -22908,7 +22919,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx101111xxxxxxxx1110x0xxxxxxxxxx + udot. */ +- return 2382; ++ return 2383; + } + } + } +@@ -23011,7 +23022,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx00111100xxxxxx1111x0xxxxxxxxxx + sudot. */ +- return 2460; ++ return 2461; + } + else + { +@@ -23019,7 +23030,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx00111110xxxxxx1111x0xxxxxxxxxx + usdot. */ +- return 2459; ++ return 2460; + } + } + else +@@ -23030,7 +23041,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx00111101xxxxxx1111x0xxxxxxxxxx + bfdot. */ +- return 2471; ++ return 2472; + } + else + { +@@ -23040,7 +23051,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x000111111xxxxxx1111x0xxxxxxxxxx + bfmlalb. */ +- return 2479; ++ return 2480; + } + else + { +@@ -23048,7 +23059,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x100111111xxxxxx1111x0xxxxxxxxxx + bfmlalt. */ +- return 2478; ++ return 2479; + } + } + } +@@ -23686,8 +23697,8 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode) + case 824: return NULL; /* fsqrt --> NULL. */ + case 832: value = 833; break; /* frintz --> frintz. */ + case 833: return NULL; /* frintz --> NULL. */ +- case 825: value = 2475; break; /* fcvt --> bfcvt. */ +- case 2475: return NULL; /* bfcvt --> NULL. */ ++ case 825: value = 2476; break; /* fcvt --> bfcvt. */ ++ case 2476: return NULL; /* bfcvt --> NULL. */ + case 834: value = 835; break; /* frinta --> frinta. */ + case 835: return NULL; /* frinta --> NULL. */ + case 836: value = 837; break; /* frintx --> frintx. */ +@@ -24206,7 +24217,7 @@ aarch64_extract_operand (const aarch64_operand *self, + case 33: + case 34: + case 35: +- case 215: ++ case 216: + return aarch64_ext_reglane (self, info, code, inst, errors); + case 36: + return aarch64_ext_reglist (self, info, code, inst, errors); +@@ -24253,6 +24264,7 @@ aarch64_extract_operand (const aarch64_operand *self, + case 188: + case 189: + case 214: ++ case 215: + return aarch64_ext_imm (self, info, code, inst, errors); + case 44: + case 45: +diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c +index e80cbf20..10880a0b 100644 +--- a/opcodes/aarch64-opc-2.c ++++ b/opcodes/aarch64-opc-2.c +@@ -238,6 +238,7 @@ const struct aarch64_operand aarch64_operands[] = + {AARCH64_OPND_CLASS_SVE_REG, "SME_ZA_HV_idx_src", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_10,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_5}, "an SME horizontal or vertical vector access register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_ZA_HV_idx_dest", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_10,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_2}, "an SME horizontal or vertical vector access register"}, + {AARCH64_OPND_CLASS_PRED_REG, "SME_Pm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Pm}, "an SVE predicate register"}, ++ {AARCH64_OPND_CLASS_SVE_REG, "SME_list_of_64bit_tiles", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_zero_mask}, "list of 64-bit ZA element tiles"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "TME_UIMM16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16}, "a 16-bit unsigned immediate for TME tcancel"}, + {AARCH64_OPND_CLASS_SIMD_ELEMENT, "SM3_IMM2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SM3_imm2}, "an indexed SM3 vector immediate"}, + {AARCH64_OPND_CLASS_NIL, "", 0, {0}, "DUMMY"}, +diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c +index b12bf3e0..9f32eb55 100644 +--- a/opcodes/aarch64-opc.c ++++ b/opcodes/aarch64-opc.c +@@ -329,6 +329,7 @@ const aarch64_field fields[] = + { 15, 1 }, /* SME_V: (horizontal / vertical tiles), bit 15. */ + { 13, 2 }, /* SME_Rv: vector select register W12-W15, bits [14:13]. */ + { 13, 3 }, /* SME Pm second source scalable predicate register P0-P7. */ ++ { 0, 8 }, /* SME_zero_mask: list of up to 8 tile names separated by commas [7:0]. */ + { 11, 2 }, /* rotate1: FCMLA immediate rotate. */ + { 13, 2 }, /* rotate2: Indexed element FCMLA immediate rotate. */ + { 12, 1 }, /* rotate3: FCADD immediate rotate. */ +@@ -3139,6 +3140,46 @@ print_register_offset_address (char *buf, size_t size, + snprintf (buf, size, "[%s, %s%s]", base, offset, tb); + } + ++/* Print ZA tiles from imm8 in ZERO instruction. ++ ++ The preferred disassembly of this instruction uses the shortest list of tile ++ names that represent the encoded immediate mask. ++ ++ For example: ++ * An all-ones immediate is disassembled as {ZA}. ++ * An all-zeros immediate is disassembled as an empty list { }. ++*/ ++static void ++print_sme_za_list(char *buf, size_t size, int mask) ++{ ++ const char* zan[] = { "za", "za0.h", "za1.h", "za0.s", ++ "za1.s", "za2.s", "za3.s", "za0.d", ++ "za1.d", "za2.d", "za3.d", "za4.d", ++ "za5.d", "za6.d", "za7.d", " " }; ++ const int zan_v[] = { 0xff, 0x55, 0xaa, 0x11, ++ 0x22, 0x44, 0x88, 0x01, ++ 0x02, 0x04, 0x08, 0x10, ++ 0x20, 0x40, 0x80, 0x00 }; ++ int i, k; ++ const int ZAN_SIZE = sizeof(zan) / sizeof(zan[0]); ++ ++ k = snprintf (buf, size, "{"); ++ for (i = 0; i < ZAN_SIZE; i++) ++ { ++ if ((mask & zan_v[i]) == zan_v[i]) ++ { ++ mask &= ~zan_v[i]; ++ if (k > 1) ++ k += snprintf (buf + k, size - k, ", %s", zan[i]); ++ else ++ k += snprintf (buf + k, size - k, "%s", zan[i]); ++ } ++ if (mask == 0) ++ break; ++ } ++ snprintf (buf + k, size - k, "}"); ++} ++ + /* Generate the string representation of the operand OPNDS[IDX] for OPCODE + in *BUF. The caller should pass in the maximum size of *BUF in SIZE. + PC, PCREL_P and ADDRESS are used to pass in and return information about +@@ -3370,6 +3411,10 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, + opnd->za_tile_vector.index.imm); + break; + ++ case AARCH64_OPND_SME_list_of_64bit_tiles: ++ print_sme_za_list (buf, size, opnd->reg.regno); ++ break; ++ + case AARCH64_OPND_CRn: + case AARCH64_OPND_CRm: + snprintf (buf, size, "C%" PRIi64, opnd->imm.value); +diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h +index 9c657dfb..62aad8bf 100644 +--- a/opcodes/aarch64-opc.h ++++ b/opcodes/aarch64-opc.h +@@ -158,6 +158,7 @@ enum aarch64_field_kind + FLD_SME_V, + FLD_SME_Rv, + FLD_SME_Pm, ++ FLD_SME_zero_mask, + FLD_rotate1, + FLD_rotate2, + FLD_rotate3, +diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h +index 5307cda4..93132206 100644 +--- a/opcodes/aarch64-tbl.h ++++ b/opcodes/aarch64-tbl.h +@@ -5136,6 +5136,8 @@ const struct aarch64_opcode aarch64_opcode_table[] = + SME_INSN ("mova", 0xc0020000, 0xff3e0200, sme_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SME_ZA_HV_idx_src), OP_SME_BHSDQ_PM_BHSDQ, 0, 0), + SME_INSN ("mova", 0xc0000000, 0xff3e0010, sme_misc, 0, OP3 (SME_ZA_HV_idx_dest, SVE_Pg3, SVE_Zn), OP_SME_BHSDQ_PM_BHSDQ, 0, 0), + ++ SME_INSN ("zero", 0xc0080000, 0xffffff00, sme_misc, 0, OP1 (SME_list_of_64bit_tiles), {}, 0, 0), ++ + /* SIMD Dot Product (optional in v8.2-A). */ + DOT_INSN ("udot", 0x2e009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ), + DOT_INSN ("sdot", 0xe009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ), +@@ -5715,6 +5717,8 @@ const struct aarch64_opcode aarch64_opcode_table[] = + "an SME horizontal or vertical vector access register") \ + Y(PRED_REG, regno, "SME_Pm", 0, F(FLD_SME_Pm), \ + "an SVE predicate register") \ ++ Y(SVE_REG, imm, "SME_list_of_64bit_tiles", 0, \ ++ F(FLD_SME_zero_mask), "list of 64-bit ZA element tiles") \ + Y(IMMEDIATE, imm, "TME_UIMM16", 0, F(FLD_imm16), \ + "a 16-bit unsigned immediate for TME tcancel") \ + Y(SIMD_ELEMENT, reglane, "SM3_IMM2", 0, F(FLD_SM3_imm2), \ +-- +2.19.1 + diff --git a/SME-0005-aarch64-SME-Add-LD1x-ST1x-LDR-and-STR-instructions.patch b/SME-0005-aarch64-SME-Add-LD1x-ST1x-LDR-and-STR-instructions.patch new file mode 100644 index 0000000000000000000000000000000000000000..a76da798cbf25320574339927b278a725fda78f9 --- /dev/null +++ b/SME-0005-aarch64-SME-Add-LD1x-ST1x-LDR-and-STR-instructions.patch @@ -0,0 +1,3124 @@ +From 5b03b1112bb59adf41488cf680afe4c7134cc560 Mon Sep 17 00:00:00 2001 +From: Przemyslaw Wirkus +Date: Wed, 17 Nov 2021 20:02:06 +0000 +Subject: [PATCH 05/10] aarch64: [SME] Add LD1x, ST1x, LDR and STR instructions + +Reference: https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=01a4d0822025084609380fb989d43bda0667db72 + +This patch is adding new loads and stores defined by SME instructions. + +gas/ChangeLog: + + * config/tc-aarch64.c (parse_sme_address): New parser. + (parse_sme_za_hv_tiles_operand_with_braces): New parser. + (parse_sme_za_array): New parser. + (output_operand_error_record): Print error details if + present. + (parse_operands): Support new operands. + * testsuite/gas/aarch64/sme-5-illegal.d: New test. + * testsuite/gas/aarch64/sme-5-illegal.l: New test. + * testsuite/gas/aarch64/sme-5-illegal.s: New test. + * testsuite/gas/aarch64/sme-5.d: New test. + * testsuite/gas/aarch64/sme-5.s: New test. + * testsuite/gas/aarch64/sme-6-illegal.d: New test. + * testsuite/gas/aarch64/sme-6-illegal.l: New test. + * testsuite/gas/aarch64/sme-6-illegal.s: New test. + * testsuite/gas/aarch64/sme-6.d: New test. + * testsuite/gas/aarch64/sme-6.s: New test. + * testsuite/gas/aarch64/sme-7-illegal.d: New test. + * testsuite/gas/aarch64/sme-7-illegal.l: New test. + * testsuite/gas/aarch64/sme-7-illegal.s: New test. + * testsuite/gas/aarch64/sme-7.d: New test. + * testsuite/gas/aarch64/sme-7.s: New test. + +include/ChangeLog: + + * opcode/aarch64.h (enum aarch64_opnd): New operands. + (enum aarch64_insn_class): Added sme_ldr and sme_str. + (AARCH64_OPDE_UNTIED_IMMS): New operand error kind. + +opcodes/ChangeLog: + + * aarch64-asm.c (aarch64_ins_sme_za_hv_tiles): New inserter. + (aarch64_ins_sme_za_list): New inserter. + (aarch64_ins_sme_za_array): New inserter. + (aarch64_ins_sme_addr_ri_u4xvl): New inserter. + * aarch64-asm.h (AARCH64_DECL_OPD_INSERTER): Added + ins_sme_za_list, ins_sme_za_array and ins_sme_addr_ri_u4xvl. + * aarch64-dis.c (aarch64_ext_sme_za_hv_tiles): New extractor. + (aarch64_ext_sme_za_list): New extractor. + (aarch64_ext_sme_za_array): New extractor. + (aarch64_ext_sme_addr_ri_u4xvl): New extractor. + * aarch64-dis.h (AARCH64_DECL_OPD_EXTRACTOR): Added + ext_sme_za_list, ext_sme_za_array and ext_sme_addr_ri_u4xvl. + * aarch64-opc.c (operand_general_constraint_met_p): + (aarch64_match_operands_constraint): Handle sme_ldr, sme_str + and sme_misc. + (aarch64_print_operand): New operands supported. + * aarch64-tbl.h (OP_SVE_QUU): New qualifier. + (OP_SVE_QZU): New qualifier. + aarch64-asm-2.c: Regenerate. + aarch64-dis-2.c: Regenerate. + aarch64-opc-2.c: Regenerate. +--- + gas/config/tc-aarch64.c | 115 ++++- + gas/testsuite/gas/aarch64/sme-5-illegal.d | 3 + + gas/testsuite/gas/aarch64/sme-5-illegal.l | 51 +++ + gas/testsuite/gas/aarch64/sme-5-illegal.s | 52 +++ + gas/testsuite/gas/aarch64/sme-5.d | 93 ++++ + gas/testsuite/gas/aarch64/sme-5.s | 101 +++++ + gas/testsuite/gas/aarch64/sme-6-illegal.d | 3 + + gas/testsuite/gas/aarch64/sme-6-illegal.l | 45 ++ + gas/testsuite/gas/aarch64/sme-6-illegal.s | 46 ++ + gas/testsuite/gas/aarch64/sme-6.d | 85 ++++ + gas/testsuite/gas/aarch64/sme-6.s | 86 ++++ + gas/testsuite/gas/aarch64/sme-7-illegal.d | 3 + + gas/testsuite/gas/aarch64/sme-7-illegal.l | 33 ++ + gas/testsuite/gas/aarch64/sme-7-illegal.s | 39 ++ + gas/testsuite/gas/aarch64/sme-7.d | 27 ++ + gas/testsuite/gas/aarch64/sme-7.s | 27 ++ + include/opcode/aarch64.h | 12 +- + opcodes/aarch64-asm-2.c | 78 ++-- + opcodes/aarch64-asm.c | 47 ++ + opcodes/aarch64-asm.h | 3 + + opcodes/aarch64-dis-2.c | 528 ++++++++++++++-------- + opcodes/aarch64-dis.c | 50 ++ + opcodes/aarch64-dis.h | 3 + + opcodes/aarch64-opc-2.c | 4 + + opcodes/aarch64-opc.c | 82 +++- + opcodes/aarch64-tbl.h | 46 ++ + 26 files changed, 1417 insertions(+), 245 deletions(-) + create mode 100644 gas/testsuite/gas/aarch64/sme-5-illegal.d + create mode 100644 gas/testsuite/gas/aarch64/sme-5-illegal.l + create mode 100644 gas/testsuite/gas/aarch64/sme-5-illegal.s + create mode 100644 gas/testsuite/gas/aarch64/sme-5.d + create mode 100644 gas/testsuite/gas/aarch64/sme-5.s + create mode 100644 gas/testsuite/gas/aarch64/sme-6-illegal.d + create mode 100644 gas/testsuite/gas/aarch64/sme-6-illegal.l + create mode 100644 gas/testsuite/gas/aarch64/sme-6-illegal.s + create mode 100644 gas/testsuite/gas/aarch64/sme-6.d + create mode 100644 gas/testsuite/gas/aarch64/sme-6.s + create mode 100644 gas/testsuite/gas/aarch64/sme-7-illegal.d + create mode 100644 gas/testsuite/gas/aarch64/sme-7-illegal.l + create mode 100644 gas/testsuite/gas/aarch64/sme-7-illegal.s + create mode 100644 gas/testsuite/gas/aarch64/sme-7.d + create mode 100644 gas/testsuite/gas/aarch64/sme-7.s + +diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c +index 33073bc9..3f6a181b 100644 +--- a/gas/config/tc-aarch64.c ++++ b/gas/config/tc-aarch64.c +@@ -4508,6 +4508,38 @@ parse_sme_za_hv_tiles_operand (char **str, + return regno; + } + ++ ++static int ++parse_sme_za_hv_tiles_operand_with_braces (char **str, ++ enum sme_hv_slice *slice_indicator, ++ int *vector_select_register, ++ int *imm, ++ aarch64_opnd_qualifier_t *qualifier) ++{ ++ int regno; ++ ++ if (!skip_past_char (str, '{')) ++ { ++ set_syntax_error (_("expected '{'")); ++ return PARSE_FAIL; ++ } ++ ++ regno = parse_sme_za_hv_tiles_operand (str, slice_indicator, ++ vector_select_register, imm, ++ qualifier); ++ ++ if (regno == PARSE_FAIL) ++ return PARSE_FAIL; ++ ++ if (!skip_past_char (str, '}')) ++ { ++ set_syntax_error (_("expected '}'")); ++ return PARSE_FAIL; ++ } ++ ++ return regno; ++} ++ + /* Parse list of up to eight 64-bit element tile names separated by commas in + SME's ZERO instruction: + +@@ -4606,6 +4638,45 @@ parse_sme_list_of_64bit_tiles (char **str) + return regno; + } + ++/* Parse ZA array operand used in e.g. STR and LDR instruction. ++ Operand format: ++ ++ ZA[, ] ++ ZA[, #] ++ ++ Function returns or PARSE_FAIL. ++*/ ++static int ++parse_sme_za_array (char **str, int *imm) ++{ ++ char *p, *q; ++ int regno; ++ int64_t imm_value; ++ ++ p = q = *str; ++ while (ISALPHA (*q)) ++ q++; ++ ++ if ((q - p != 2) || strncasecmp ("za", p, q - p) != 0) ++ { ++ set_syntax_error (_("expected ZA array")); ++ return PARSE_FAIL; ++ } ++ ++ if (! parse_sme_za_hv_tiles_operand_index (&q, ®no, &imm_value)) ++ return PARSE_FAIL; ++ ++ if (imm_value < 0 || imm_value > 15) ++ { ++ set_syntax_error (_("offset out of range")); ++ return PARSE_FAIL; ++ } ++ ++ *imm = imm_value; ++ *str = q; ++ return regno; ++} ++ + /* Parse a system register or a PSTATE field name for an MSR/MRS instruction. + Returns the encoding for the option, or PARSE_FAIL. + +@@ -5412,9 +5483,15 @@ output_operand_error_record (const operand_error_record *record, char *str) + } + break; + ++ case AARCH64_OPDE_UNTIED_IMMS: ++ handler (_("operand %d must have the same immediate value " ++ "as operand 1 -- `%s'"), ++ detail->index + 1, str); ++ break; ++ + case AARCH64_OPDE_UNTIED_OPERAND: + handler (_("operand %d must be the same register as operand 1 -- `%s'"), +- detail->index + 1, str); ++ detail->index + 1, str); + break; + + case AARCH64_OPDE_OUT_OF_RANGE: +@@ -7006,6 +7083,7 @@ parse_operands (char *str, const aarch64_opcode *opcode) + case AARCH64_OPND_SVE_ADDR_RI_S4x16: + case AARCH64_OPND_SVE_ADDR_RI_S4x32: + case AARCH64_OPND_SVE_ADDR_RI_S4xVL: ++ case AARCH64_OPND_SME_ADDR_RI_U4xVL: + case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL: + case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL: + case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL: +@@ -7061,11 +7139,12 @@ parse_operands (char *str, const aarch64_opcode *opcode) + goto failure; + } + goto regoff_addr; +- ++ + case AARCH64_OPND_SVE_ADDR_RR: + case AARCH64_OPND_SVE_ADDR_RR_LSL1: + case AARCH64_OPND_SVE_ADDR_RR_LSL2: + case AARCH64_OPND_SVE_ADDR_RR_LSL3: ++ case AARCH64_OPND_SVE_ADDR_RR_LSL4: + case AARCH64_OPND_SVE_ADDR_RX: + case AARCH64_OPND_SVE_ADDR_RX_LSL1: + case AARCH64_OPND_SVE_ADDR_RX_LSL2: +@@ -7321,20 +7400,29 @@ parse_operands (char *str, const aarch64_opcode *opcode) + + case AARCH64_OPND_SME_ZA_HV_idx_src: + case AARCH64_OPND_SME_ZA_HV_idx_dest: ++ case AARCH64_OPND_SME_ZA_HV_idx_ldstr: + { +- enum sme_hv_slice vector_indicator; ++ enum sme_hv_slice slice_indicator; + int vector_select_register; + int imm; +- val = parse_sme_za_hv_tiles_operand (&str, &vector_indicator, +- &vector_select_register, +- &imm, +- &qualifier); ++ ++ if (operands[i] == AARCH64_OPND_SME_ZA_HV_idx_ldstr) ++ val = parse_sme_za_hv_tiles_operand_with_braces (&str, ++ &slice_indicator, ++ &vector_select_register, ++ &imm, ++ &qualifier); ++ else ++ val = parse_sme_za_hv_tiles_operand (&str, &slice_indicator, ++ &vector_select_register, ++ &imm, ++ &qualifier); + if (val == PARSE_FAIL) + goto failure; + info->za_tile_vector.regno = val; + info->za_tile_vector.index.regno = vector_select_register; + info->za_tile_vector.index.imm = imm; +- info->za_tile_vector.v = vector_indicator; ++ info->za_tile_vector.v = slice_indicator; + info->qualifier = qualifier; + break; + } +@@ -7346,6 +7434,17 @@ parse_operands (char *str, const aarch64_opcode *opcode) + info->imm.value = val; + break; + ++ case AARCH64_OPND_SME_ZA_array: ++ { ++ int imm; ++ val = parse_sme_za_array (&str, &imm); ++ if (val == PARSE_FAIL) ++ goto failure; ++ info->za_tile_vector.index.regno = val; ++ info->za_tile_vector.index.imm = imm; ++ break; ++ } ++ + default: + as_fatal (_("unhandled operand code %d"), operands[i]); + } +diff --git a/gas/testsuite/gas/aarch64/sme-5-illegal.d b/gas/testsuite/gas/aarch64/sme-5-illegal.d +new file mode 100644 +index 00000000..0513dc0a +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/sme-5-illegal.d +@@ -0,0 +1,3 @@ ++#as: -march=armv8-a+sme ++#source: sme-5-illegal.s ++#error_output: sme-5-illegal.l +diff --git a/gas/testsuite/gas/aarch64/sme-5-illegal.l b/gas/testsuite/gas/aarch64/sme-5-illegal.l +new file mode 100644 +index 00000000..c2f8bc92 +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/sme-5-illegal.l +@@ -0,0 +1,51 @@ ++[^:]*: Assembler messages: ++[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 1 -- `ld1b {za0h.b\[w11,0\]},p0/z,\[x0\]' ++[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 1 -- `ld1h {za0h.h\[w16,0\]},p0/z,\[x0\]' ++[^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1h {za0v.h\[w12,0\]},p0/z,\[x0,x0,lsl#3\]' ++[^:]*:[0-9]+: Error: '\]' expected at operand 3 -- `ld1w {za3v.s\[w15,3\]},p7/z,\[sp,lsl#2\]' ++[^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1d {za0h.d\[w12,0\]},p0/z,\[sp,x0,lsl#12\]' ++[^:]*:[0-9]+: Error: expected ',' at operand 1 -- `ld1q {za0v.q\[w12\]},p0/z,\[x0,x0,lsl#2\]' ++[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1b {za1h.b\[w12,0\]},p0/z,\[x0\]' ++[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1b {za1v.b\[w12,0\]},p0/z,\[sp\]' ++[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1b {za1h.b\[w12,0\]},p0/z,\[sp,x0\]' ++[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1b {za0v.b\[w15,16\]},p7/z,\[x17\]' ++[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1b {za0h.b\[w15,16\]},p7/z,\[sp\]' ++[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1b {za0v.b\[w15,16\]},p7/z,\[sp,x17\]' ++[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1h {za2v.h\[w12,0\]},p0/z,\[x0\]' ++[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1h {za2h.h\[w12,0\]},p0/z,\[sp\]' ++[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1h {za2v.h\[w12,0\]},p0/z,\[x0,x0,lsl#1\]' ++[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1h {za2h.h\[w12,0\]},p0/z,\[sp,x0,lsl#1\]' ++[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1h {za1v.h\[w15,8\]},p7/z,\[x17\]' ++[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1h {za1h.h\[w15,8\]},p7/z,\[sp\]' ++[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1h {za1v.h\[w15,8\]},p7/z,\[x0,x17,lsl#1\]' ++[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1h {za1h.h\[w15,8\]},p7/z,\[sp,x17,lsl#1\]' ++[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1w {za4h.s\[w12,0\]},p0/z,\[x0\]' ++[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1w {za4v.s\[w12,0\]},p0/z,\[sp\]' ++[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1w {za4h.s\[w12,0\]},p0/z,\[x0,x0,lsl#2\]' ++[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1w {za4v.s\[w12,0\]},p0/z,\[sp,x0,lsl#2\]' ++[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1w {za3h.s\[w15,4\]},p7/z,\[x17\]' ++[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1w {za3v.s\[w15,4\]},p7/z,\[sp\]' ++[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1w {za3h.s\[w15,4\]},p7/z,\[x0,x17,lsl#2\]' ++[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1w {za3v.s\[w15,4\]},p7/z,\[sp,x17,lsl#2\]' ++[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1d {za8v.d\[w12,0\]},p0/z,\[x0\]' ++[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1d {za8h.d\[w12,0\]},p0/z,\[sp\]' ++[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1d {za8v.d\[w12,0\]},p0/z,\[x0,x0,lsl#3\]' ++[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `ld1d {za8h.d\[w12,0\]},p0/z,\[sp,x0,lsl#3\]' ++[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1d {za7v.d\[w15,2\]},p7/z,\[x17\]' ++[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1d {za7h.d\[w15,2\]},p7/z,\[sp\]' ++[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1d {za7v.d\[w15,2\]},p7/z,\[x0,x17,lsl#3\]' ++[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1d {za7h.d\[w15,2\]},p7/z,\[sp,x17,lsl#3\]' ++[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `ld1q {za16v.q\[w12\]},p0/z,\[x0\]' ++[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `ld1q {za16h.q\[w12\]},p0/z,\[sp\]' ++[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `ld1q {za16v.q\[w12\]},p0/z,\[x0,x0,lsl#4\]' ++[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `ld1q {za16h.q\[w12\]},p0/z,\[sp,x0,lsl#4\]' ++[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1q {za15v.q\[w15,1\]},p7/z,\[x17\]' ++[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1q {za15h.q\[w15,1\]},p7/z,\[sp\]' ++[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1q {za15v.q\[w15,1\]},p7/z,\[x0,x17,lsl#4\]' ++[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1q {za15h.q\[w15,1\]},p7/z,\[sp,x17,lsl#4\]' ++[^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1b {za0h.b\[w12,0\]},p0/z,\[x0,x1,lsl#1\]' ++[^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1h {za0h.h\[w12,0\]},p0/z,\[x0,x1,lsl#2\]' ++[^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1w {za3v.s\[w12,3\]},p7/z,\[x0,x1,lsl#3\]' ++[^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1d {za0h.d\[w12,0\]},p0/z,\[x0,x1,lsl#4\]' ++[^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1q {za0v.q\[w12,0\]},p0/z,\[x0,x1,lsl#1\]' ++[^:]*:[0-9]+: Error: expected ',' at operand 1 -- `ld1q {za0v.q\[w12\]},p0/z,\[x0,x1,lsl#1\]' +diff --git a/gas/testsuite/gas/aarch64/sme-5-illegal.s b/gas/testsuite/gas/aarch64/sme-5-illegal.s +new file mode 100644 +index 00000000..bf65f6af +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/sme-5-illegal.s +@@ -0,0 +1,52 @@ ++/* Scalable Matrix Extension (SME). */ ++ld1b {za0h.b[w11, 0]}, p0/z, [x0] ++ld1h {za0h.h[w16, 0]}, p0/z, [x0] ++ld1h {za0v.h[w12, 0]}, p0/z, [x0, x0, lsl #3] ++ld1w {za3v.s[w15, 3]}, p7/z, [sp, lsl #2] ++ld1d {za0h.d[w12, 0]}, p0/z, [sp, x0, lsl #12] ++ld1q {za0v.q[w12]}, p0/z, [x0, x0, lsl #2] ++ld1b {za1h.b[w12, 0]}, p0/z, [x0] ++ld1b {za1v.b[w12, 0]}, p0/z, [sp] ++ld1b {za1h.b[w12, 0]}, p0/z, [sp, x0] ++ld1b {za0v.b[w15, 16]}, p7/z, [x17] ++ld1b {za0h.b[w15, 16]}, p7/z, [sp] ++ld1b {za0v.b[w15, 16]}, p7/z, [sp, x17] ++ld1h {za2v.h[w12, 0]}, p0/z, [x0] ++ld1h {za2h.h[w12, 0]}, p0/z, [sp] ++ld1h {za2v.h[w12, 0]}, p0/z, [x0, x0, lsl #1] ++ld1h {za2h.h[w12, 0]}, p0/z, [sp, x0, lsl #1] ++ld1h {za1v.h[w15, 8]}, p7/z, [x17] ++ld1h {za1h.h[w15, 8]}, p7/z, [sp] ++ld1h {za1v.h[w15, 8]}, p7/z, [x0, x17, lsl #1] ++ld1h {za1h.h[w15, 8]}, p7/z, [sp, x17, lsl #1] ++ld1w {za4h.s[w12, 0]}, p0/z, [x0] ++ld1w {za4v.s[w12, 0]}, p0/z, [sp] ++ld1w {za4h.s[w12, 0]}, p0/z, [x0, x0, lsl #2] ++ld1w {za4v.s[w12, 0]}, p0/z, [sp, x0, lsl #2] ++ld1w {za3h.s[w15, 4]}, p7/z, [x17] ++ld1w {za3v.s[w15, 4]}, p7/z, [sp] ++ld1w {za3h.s[w15, 4]}, p7/z, [x0, x17, lsl #2] ++ld1w {za3v.s[w15, 4]}, p7/z, [sp, x17, lsl #2] ++ld1d {za8v.d[w12, 0]}, p0/z, [x0] ++ld1d {za8h.d[w12, 0]}, p0/z, [sp] ++ld1d {za8v.d[w12, 0]}, p0/z, [x0, x0, lsl #3] ++ld1d {za8h.d[w12, 0]}, p0/z, [sp, x0, lsl #3] ++ld1d {za7v.d[w15, 2]}, p7/z, [x17] ++ld1d {za7h.d[w15, 2]}, p7/z, [sp] ++ld1d {za7v.d[w15, 2]}, p7/z, [x0, x17, lsl #3] ++ld1d {za7h.d[w15, 2]}, p7/z, [sp, x17, lsl #3] ++ld1q {za16v.q[w12]}, p0/z, [x0] ++ld1q {za16h.q[w12]}, p0/z, [sp] ++ld1q {za16v.q[w12]}, p0/z, [x0, x0, lsl #4] ++ld1q {za16h.q[w12]}, p0/z, [sp, x0, lsl #4] ++ld1q {za15v.q[w15, 1]}, p7/z, [x17] ++ld1q {za15h.q[w15, 1]}, p7/z, [sp] ++ld1q {za15v.q[w15, 1]}, p7/z, [x0, x17, lsl #4] ++ld1q {za15h.q[w15, 1]}, p7/z, [sp, x17, lsl #4] ++/* Illegal operand 3 addressing modes. */ ++ld1b {za0h.b[w12, 0]}, p0/z, [x0, x1, lsl #1] ++ld1h {za0h.h[w12, 0]}, p0/z, [x0, x1, lsl #2] ++ld1w {za3v.s[w12, 3]}, p7/z, [x0, x1, lsl #3] ++ld1d {za0h.d[w12, 0]}, p0/z, [x0, x1, lsl #4] ++ld1q {za0v.q[w12, 0]}, p0/z, [x0, x1, lsl #1] ++ld1q {za0v.q[w12]}, p0/z, [x0, x1, lsl #1] +diff --git a/gas/testsuite/gas/aarch64/sme-5.d b/gas/testsuite/gas/aarch64/sme-5.d +new file mode 100644 +index 00000000..66675349 +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/sme-5.d +@@ -0,0 +1,93 @@ ++#name: SME extension (LD1x instructions) ++#as: -march=armv8-a+sme ++#objdump: -dr ++ ++.*: file format .* ++ ++Disassembly of section \.text: ++ ++0+ <.*>: ++ 0: e01f0000 ld1b {za0h.b\[w12, 0\]}, p0/z, \[x0, xzr\] ++ 4: e01f03e0 ld1b {za0h.b\[w12, 0\]}, p0/z, \[sp, xzr\] ++ 8: e00003e0 ld1b {za0h.b\[w12, 0\]}, p0/z, \[sp, x0\] ++ c: e01f7e2f ld1b {za0h.b\[w15, 15\]}, p7/z, \[x17, xzr\] ++ 10: e01f7fef ld1b {za0h.b\[w15, 15\]}, p7/z, \[sp, xzr\] ++ 14: e0117fef ld1b {za0h.b\[w15, 15\]}, p7/z, \[sp, x17\] ++ 18: e05f0000 ld1h {za0h.h\[w12, 0\]}, p0/z, \[x0, xzr, lsl #1\] ++ 1c: e05f03e0 ld1h {za0h.h\[w12, 0\]}, p0/z, \[sp, xzr, lsl #1\] ++ 20: e0400000 ld1h {za0h.h\[w12, 0\]}, p0/z, \[x0, x0, lsl #1\] ++ 24: e04003e0 ld1h {za0h.h\[w12, 0\]}, p0/z, \[sp, x0, lsl #1\] ++ 28: e05f7e2f ld1h {za1h.h\[w15, 7\]}, p7/z, \[x17, xzr, lsl #1\] ++ 2c: e05f7fef ld1h {za1h.h\[w15, 7\]}, p7/z, \[sp, xzr, lsl #1\] ++ 30: e0517c0f ld1h {za1h.h\[w15, 7\]}, p7/z, \[x0, x17, lsl #1\] ++ 34: e0517fef ld1h {za1h.h\[w15, 7\]}, p7/z, \[sp, x17, lsl #1\] ++ 38: e09f0000 ld1w {za0h.s\[w12, 0\]}, p0/z, \[x0, xzr, lsl #2\] ++ 3c: e09f03e0 ld1w {za0h.s\[w12, 0\]}, p0/z, \[sp, xzr, lsl #2\] ++ 40: e0800000 ld1w {za0h.s\[w12, 0\]}, p0/z, \[x0, x0, lsl #2\] ++ 44: e08003e0 ld1w {za0h.s\[w12, 0\]}, p0/z, \[sp, x0, lsl #2\] ++ 48: e09f7e2f ld1w {za3h.s\[w15, 3\]}, p7/z, \[x17, xzr, lsl #2\] ++ 4c: e09f7fef ld1w {za3h.s\[w15, 3\]}, p7/z, \[sp, xzr, lsl #2\] ++ 50: e0917c0f ld1w {za3h.s\[w15, 3\]}, p7/z, \[x0, x17, lsl #2\] ++ 54: e0917fef ld1w {za3h.s\[w15, 3\]}, p7/z, \[sp, x17, lsl #2\] ++ 58: e0df0000 ld1d {za0h.d\[w12, 0\]}, p0/z, \[x0, xzr, lsl #3\] ++ 5c: e0df03e0 ld1d {za0h.d\[w12, 0\]}, p0/z, \[sp, xzr, lsl #3\] ++ 60: e0c00000 ld1d {za0h.d\[w12, 0\]}, p0/z, \[x0, x0, lsl #3\] ++ 64: e0c003e0 ld1d {za0h.d\[w12, 0\]}, p0/z, \[sp, x0, lsl #3\] ++ 68: e0df7e2f ld1d {za7h.d\[w15, 1\]}, p7/z, \[x17, xzr, lsl #3\] ++ 6c: e0df7fef ld1d {za7h.d\[w15, 1\]}, p7/z, \[sp, xzr, lsl #3\] ++ 70: e0d17c0f ld1d {za7h.d\[w15, 1\]}, p7/z, \[x0, x17, lsl #3\] ++ 74: e0d17fef ld1d {za7h.d\[w15, 1\]}, p7/z, \[sp, x17, lsl #3\] ++ 78: e1df0000 ld1q {za0h.q\[w12, 0\]}, p0/z, \[x0, xzr, lsl #4\] ++ 7c: e1df03e0 ld1q {za0h.q\[w12, 0\]}, p0/z, \[sp, xzr, lsl #4\] ++ 80: e1c00000 ld1q {za0h.q\[w12, 0\]}, p0/z, \[x0, x0, lsl #4\] ++ 84: e1c003e0 ld1q {za0h.q\[w12, 0\]}, p0/z, \[sp, x0, lsl #4\] ++ 88: e1df7e2f ld1q {za15h.q\[w15, 0\]}, p7/z, \[x17, xzr, lsl #4\] ++ 8c: e1df7fef ld1q {za15h.q\[w15, 0\]}, p7/z, \[sp, xzr, lsl #4\] ++ 90: e1d17c0f ld1q {za15h.q\[w15, 0\]}, p7/z, \[x0, x17, lsl #4\] ++ 94: e1d17fef ld1q {za15h.q\[w15, 0\]}, p7/z, \[sp, x17, lsl #4\] ++ 98: e01f8000 ld1b {za0v.b\[w12, 0\]}, p0/z, \[x0, xzr\] ++ 9c: e01f83e0 ld1b {za0v.b\[w12, 0\]}, p0/z, \[sp, xzr\] ++ a0: e00083e0 ld1b {za0v.b\[w12, 0\]}, p0/z, \[sp, x0\] ++ a4: e01ffe2f ld1b {za0v.b\[w15, 15\]}, p7/z, \[x17, xzr\] ++ a8: e01fffef ld1b {za0v.b\[w15, 15\]}, p7/z, \[sp, xzr\] ++ ac: e011ffef ld1b {za0v.b\[w15, 15\]}, p7/z, \[sp, x17\] ++ b0: e05f8000 ld1h {za0v.h\[w12, 0\]}, p0/z, \[x0, xzr, lsl #1\] ++ b4: e05f83e0 ld1h {za0v.h\[w12, 0\]}, p0/z, \[sp, xzr, lsl #1\] ++ b8: e0408000 ld1h {za0v.h\[w12, 0\]}, p0/z, \[x0, x0, lsl #1\] ++ bc: e04083e0 ld1h {za0v.h\[w12, 0\]}, p0/z, \[sp, x0, lsl #1\] ++ c0: e05ffe2f ld1h {za1v.h\[w15, 7\]}, p7/z, \[x17, xzr, lsl #1\] ++ c4: e05fffef ld1h {za1v.h\[w15, 7\]}, p7/z, \[sp, xzr, lsl #1\] ++ c8: e051fc0f ld1h {za1v.h\[w15, 7\]}, p7/z, \[x0, x17, lsl #1\] ++ cc: e051ffef ld1h {za1v.h\[w15, 7\]}, p7/z, \[sp, x17, lsl #1\] ++ d0: e09f8000 ld1w {za0v.s\[w12, 0\]}, p0/z, \[x0, xzr, lsl #2\] ++ d4: e09f83e0 ld1w {za0v.s\[w12, 0\]}, p0/z, \[sp, xzr, lsl #2\] ++ d8: e0808000 ld1w {za0v.s\[w12, 0\]}, p0/z, \[x0, x0, lsl #2\] ++ dc: e08083e0 ld1w {za0v.s\[w12, 0\]}, p0/z, \[sp, x0, lsl #2\] ++ e0: e09ffe2f ld1w {za3v.s\[w15, 3\]}, p7/z, \[x17, xzr, lsl #2\] ++ e4: e09fffef ld1w {za3v.s\[w15, 3\]}, p7/z, \[sp, xzr, lsl #2\] ++ e8: e091fc0f ld1w {za3v.s\[w15, 3\]}, p7/z, \[x0, x17, lsl #2\] ++ ec: e091ffef ld1w {za3v.s\[w15, 3\]}, p7/z, \[sp, x17, lsl #2\] ++ f0: e0df8000 ld1d {za0v.d\[w12, 0\]}, p0/z, \[x0, xzr, lsl #3\] ++ f4: e0df83e0 ld1d {za0v.d\[w12, 0\]}, p0/z, \[sp, xzr, lsl #3\] ++ f8: e0c08000 ld1d {za0v.d\[w12, 0\]}, p0/z, \[x0, x0, lsl #3\] ++ fc: e0c083e0 ld1d {za0v.d\[w12, 0\]}, p0/z, \[sp, x0, lsl #3\] ++ 100: e0dffe2f ld1d {za7v.d\[w15, 1\]}, p7/z, \[x17, xzr, lsl #3\] ++ 104: e0dfffef ld1d {za7v.d\[w15, 1\]}, p7/z, \[sp, xzr, lsl #3\] ++ 108: e0d1fc0f ld1d {za7v.d\[w15, 1\]}, p7/z, \[x0, x17, lsl #3\] ++ 10c: e0d1ffef ld1d {za7v.d\[w15, 1\]}, p7/z, \[sp, x17, lsl #3\] ++ 110: e1df8000 ld1q {za0v.q\[w12, 0\]}, p0/z, \[x0, xzr, lsl #4\] ++ 114: e1df83e0 ld1q {za0v.q\[w12, 0\]}, p0/z, \[sp, xzr, lsl #4\] ++ 118: e1c08000 ld1q {za0v.q\[w12, 0\]}, p0/z, \[x0, x0, lsl #4\] ++ 11c: e1c083e0 ld1q {za0v.q\[w12, 0\]}, p0/z, \[sp, x0, lsl #4\] ++ 120: e1dffe2f ld1q {za15v.q\[w15, 0\]}, p7/z, \[x17, xzr, lsl #4\] ++ 124: e1dfffef ld1q {za15v.q\[w15, 0\]}, p7/z, \[sp, xzr, lsl #4\] ++ 128: e1d1fc0f ld1q {za15v.q\[w15, 0\]}, p7/z, \[x0, x17, lsl #4\] ++ 12c: e1d1ffef ld1q {za15v.q\[w15, 0\]}, p7/z, \[sp, x17, lsl #4\] ++ 130: e1c083e0 ld1q {za0v.q\[w12, 0\]}, p0/z, \[sp, x0, lsl #4\] ++ 134: e1dffe2f ld1q {za15v.q\[w15, 0\]}, p7/z, \[x17, xzr, lsl #4\] ++ 138: e000ffef ld1b {za0v.b\[w15, 15\]}, p7/z, \[sp, x0\] ++ 13c: e0010000 ld1b {za0h.b\[w12, 0\]}, p0/z, \[x0, x1\] ++ 140: e0410000 ld1h {za0h.h\[w12, 0\]}, p0/z, \[x0, x1, lsl #1\] ++ 144: e0819c0f ld1w {za3v.s\[w12, 3\]}, p7/z, \[x0, x1, lsl #2\] ++ 148: e0c10000 ld1d {za0h.d\[w12, 0\]}, p0/z, \[x0, x1, lsl #3\] ++ 14c: e1c18000 ld1q {za0v.q\[w12, 0\]}, p0/z, \[x0, x1, lsl #4\] +diff --git a/gas/testsuite/gas/aarch64/sme-5.s b/gas/testsuite/gas/aarch64/sme-5.s +new file mode 100644 +index 00000000..e0d79f6d +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/sme-5.s +@@ -0,0 +1,101 @@ ++/* SME Extension (LD1x instructions). */ ++ld1b {za0h.b[w12, 0]}, p0/z, [x0] ++ld1b {za0h.b[w12, 0]}, p0/z, [sp] ++ld1b {za0h.b[w12, 0]}, p0/z, [sp, x0] ++ld1b {za0h.b[w15, 15]}, p7/z, [x17] ++ld1b {za0h.b[w15, 15]}, p7/z, [sp] ++ld1b {za0h.b[w15, 15]}, p7/z, [sp, x17] ++ ++ld1h {za0h.h[w12, 0]}, p0/z, [x0] ++ld1h {za0h.h[w12, 0]}, p0/z, [sp] ++ld1h {za0h.h[w12, 0]}, p0/z, [x0, x0, lsl #1] ++ld1h {za0h.h[w12, 0]}, p0/z, [sp, x0, lsl #1] ++ld1h {za1h.h[w15, 7]}, p7/z, [x17] ++ld1h {za1h.h[w15, 7]}, p7/z, [sp] ++ld1h {za1h.h[w15, 7]}, p7/z, [x0, x17, lsl #1] ++ld1h {za1h.h[w15, 7]}, p7/z, [sp, x17, lsl #1] ++ ++ld1w {za0h.s[w12, 0]}, p0/z, [x0] ++ld1w {za0h.s[w12, 0]}, p0/z, [sp] ++ld1w {za0h.s[w12, 0]}, p0/z, [x0, x0, lsl #2] ++ld1w {za0h.s[w12, 0]}, p0/z, [sp, x0, lsl #2] ++ld1w {za3h.s[w15, 3]}, p7/z, [x17] ++ld1w {za3h.s[w15, 3]}, p7/z, [sp] ++ld1w {za3h.s[w15, 3]}, p7/z, [x0, x17, lsl #2] ++ld1w {za3h.s[w15, 3]}, p7/z, [sp, x17, lsl #2] ++ ++ld1d {za0h.d[w12, 0]}, p0/z, [x0] ++ld1d {za0h.d[w12, 0]}, p0/z, [sp] ++ld1d {za0h.d[w12, 0]}, p0/z, [x0, x0, lsl #3] ++ld1d {za0h.d[w12, 0]}, p0/z, [sp, x0, lsl #3] ++ld1d {za7h.d[w15, 1]}, p7/z, [x17] ++ld1d {za7h.d[w15, 1]}, p7/z, [sp] ++ld1d {za7h.d[w15, 1]}, p7/z, [x0, x17, lsl #3] ++ld1d {za7h.d[w15, 1]}, p7/z, [sp, x17, lsl #3] ++ ++ld1q {za0h.q[w12, 0]}, p0/z, [x0] ++ld1q {za0h.q[w12, 0]}, p0/z, [sp] ++ld1q {za0h.q[w12, 0]}, p0/z, [x0, x0, lsl #4] ++ld1q {za0h.q[w12, 0]}, p0/z, [sp, x0, lsl #4] ++ld1q {za15h.q[w15, 0]}, p7/z, [x17] ++ld1q {za15h.q[w15, 0]}, p7/z, [sp] ++ld1q {za15h.q[w15, 0]}, p7/z, [x0, x17, lsl #4] ++ld1q {za15h.q[w15, 0]}, p7/z, [sp, x17, lsl #4] ++ ++ld1b {za0v.b[w12, 0]}, p0/z, [x0] ++ld1b {za0v.b[w12, 0]}, p0/z, [sp] ++ld1b {za0v.b[w12, 0]}, p0/z, [sp, x0] ++ld1b {za0v.b[w15, 15]}, p7/z, [x17] ++ld1b {za0v.b[w15, 15]}, p7/z, [sp] ++ld1b {za0v.b[w15, 15]}, p7/z, [sp, x17] ++ ++ld1h {za0v.h[w12, 0]}, p0/z, [x0] ++ld1h {za0v.h[w12, 0]}, p0/z, [sp] ++ld1h {za0v.h[w12, 0]}, p0/z, [x0, x0, lsl #1] ++ld1h {za0v.h[w12, 0]}, p0/z, [sp, x0, lsl #1] ++ld1h {za1v.h[w15, 7]}, p7/z, [x17] ++ld1h {za1v.h[w15, 7]}, p7/z, [sp] ++ld1h {za1v.h[w15, 7]}, p7/z, [x0, x17, lsl #1] ++ld1h {za1v.h[w15, 7]}, p7/z, [sp, x17, lsl #1] ++ ++ld1w {za0v.s[w12, 0]}, p0/z, [x0] ++ld1w {za0v.s[w12, 0]}, p0/z, [sp] ++ld1w {za0v.s[w12, 0]}, p0/z, [x0, x0, lsl #2] ++ld1w {za0v.s[w12, 0]}, p0/z, [sp, x0, lsl #2] ++ld1w {za3v.s[w15, 3]}, p7/z, [x17] ++ld1w {za3v.s[w15, 3]}, p7/z, [sp] ++ld1w {za3v.s[w15, 3]}, p7/z, [x0, x17, lsl #2] ++ld1w {za3v.s[w15, 3]}, p7/z, [sp, x17, lsl #2] ++ ++ld1d {za0v.d[w12, 0]}, p0/z, [x0] ++ld1d {za0v.d[w12, 0]}, p0/z, [sp] ++ld1d {za0v.d[w12, 0]}, p0/z, [x0, x0, lsl #3] ++ld1d {za0v.d[w12, 0]}, p0/z, [sp, x0, lsl #3] ++ld1d {za7v.d[w15, 1]}, p7/z, [x17] ++ld1d {za7v.d[w15, 1]}, p7/z, [sp] ++ld1d {za7v.d[w15, 1]}, p7/z, [x0, x17, lsl #3] ++ld1d {za7v.d[w15, 1]}, p7/z, [sp, x17, lsl #3] ++ ++ld1q {za0v.q[w12, 0]}, p0/z, [x0] ++ld1q {za0v.q[w12, 0]}, p0/z, [sp] ++ld1q {za0v.q[w12, 0]}, p0/z, [x0, x0, lsl #4] ++ld1q {za0v.q[w12, 0]}, p0/z, [sp, x0, lsl #4] ++ld1q {za15v.q[w15, 0]}, p7/z, [x17] ++ld1q {za15v.q[w15, 0]}, p7/z, [sp] ++ld1q {za15v.q[w15, 0]}, p7/z, [x0, x17, lsl #4] ++ld1q {za15v.q[w15, 0]}, p7/z, [sp, x17, lsl #4] ++ ++/* Register aliases. */ ++foo .req za0v ++bar .req w15 ++ ++ld1q {foo.q[w12, #0]}, p0/z, [sp, x0, lsl #4] ++ld1q {za15v.q[bar, #0]}, p7/z, [x17] ++ ++/* Optional LSL operator. */ ++ld1b {za0v.b[w15, 15]}, p7/z, [sp, x0, lsl #0] ++ld1b {za0h.b[w12, 0]}, p0/z, [x0, x1] ++ld1h {za0h.h[w12, 0]}, p0/z, [x0, x1] ++ld1w {za3v.s[w12, 3]}, p7/z, [x0, x1] ++ld1d {za0h.d[w12, 0]}, p0/z, [x0, x1] ++ld1q {za0v.q[w12, 0]}, p0/z, [x0, x1] +diff --git a/gas/testsuite/gas/aarch64/sme-6-illegal.d b/gas/testsuite/gas/aarch64/sme-6-illegal.d +new file mode 100644 +index 00000000..fd3f7f3e +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/sme-6-illegal.d +@@ -0,0 +1,3 @@ ++#as: -march=armv8-a+sme ++#source: sme-6-illegal.s ++#error_output: sme-6-illegal.l +diff --git a/gas/testsuite/gas/aarch64/sme-6-illegal.l b/gas/testsuite/gas/aarch64/sme-6-illegal.l +new file mode 100644 +index 00000000..233c12af +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/sme-6-illegal.l +@@ -0,0 +1,45 @@ ++[^:]*: Assembler messages: ++[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 1 -- `st1b {za0h.b\[w11,0\]},p0,\[x0\]' ++[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 1 -- `st1h {za0h.h\[w16,0\]},p0,\[x0\]' ++[^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `st1h {za0v.h\[w12,0\]},p0,\[x0,x0,lsl#3\]' ++[^:]*:[0-9]+: Error: '\]' expected at operand 3 -- `st1w {za3v.s\[w15,3\]},p7,\[sp,lsl#2\]' ++[^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `st1d {za0h.d\[w12,0\]},p0,\[sp,x0,lsl#12\]' ++[^:]*:[0-9]+: Error: expected ',' at operand 1 -- `st1q {za0v.q\[w12\]},p0,\[x0,x0,lsl#2\]' ++[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1b {za1h.b\[w12,0\]},p0,\[x0\]' ++[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1b {za1v.b\[w12,0\]},p0,\[sp\]' ++[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1b {za1h.b\[w12,0\]},p0,\[sp,x0\]' ++[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1b {za0v.b\[w15,16\]},p7,\[x17\]' ++[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1b {za0h.b\[w15,16\]},p7,\[sp\]' ++[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1b {za0v.b\[w15,16\]},p7,\[sp,x17\]' ++[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1h {za2v.h\[w12,0\]},p0,\[x0\]' ++[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1h {za2h.h\[w12,0\]},p0,\[sp\]' ++[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1h {za2v.h\[w12,0\]},p0,\[x0,x0,lsl#1\]' ++[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1h {za2h.h\[w12,0\]},p0,\[sp,x0,lsl#1\]' ++[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1h {za1v.h\[w15,8\]},p7,\[x17\]' ++[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1h {za1h.h\[w15,8\]},p7,\[sp\]' ++[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1h {za1v.h\[w15,8\]},p7,\[x0,x17,lsl#1\]' ++[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1h {za1h.h\[w15,8\]},p7,\[sp,x17,lsl#1\]' ++[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1w {za4h.s\[w12,0\]},p0,\[x0\]' ++[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1w {za4v.s\[w12,0\]},p0,\[sp\]' ++[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1w {za4h.s\[w12,0\]},p0,\[x0,x0,lsl#2\]' ++[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1w {za4v.s\[w12,0\]},p0,\[sp,x0,lsl#2\]' ++[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1w {za3h.s\[w15,4\]},p7,\[x17\]' ++[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1w {za3v.s\[w15,4\]},p7,\[sp\]' ++[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1w {za3h.s\[w15,4\]},p7,\[x0,x17,lsl#2\]' ++[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1w {za3v.s\[w15,4\]},p7,\[sp,x17,lsl#2\]' ++[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1d {za8v.d\[w12,0\]},p0,\[x0\]' ++[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1d {za8h.d\[w12,0\]},p0,\[sp\]' ++[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1d {za8v.d\[w12,0\]},p0,\[x0,x0,lsl#3\]' ++[^:]*:[0-9]+: Error: ZA tile vector out of range at operand 1 -- `st1d {za8h.d\[w12,0\]},p0,\[sp,x0,lsl#3\]' ++[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1d {za7v.d\[w15,2\]},p7,\[x17\]' ++[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1d {za7h.d\[w15,2\]},p7,\[sp\]' ++[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1d {za7v.d\[w15,2\]},p7,\[x0,x17,lsl#3\]' ++[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1d {za7h.d\[w15,2\]},p7,\[sp,x17,lsl#3\]' ++[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `st1q {za16v.q\[w12\]},p0,\[x0\]' ++[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `st1q {za16h.q\[w12\]},p0,\[sp\]' ++[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `st1q {za16v.q\[w12\]},p0,\[x0,x0,lsl#4\]' ++[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `st1q {za16h.q\[w12\]},p0,\[sp,x0,lsl#4\]' ++[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1q {za15v.q\[w15,1\]},p7,\[x17\]' ++[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1q {za15h.q\[w15,1\]},p7,\[sp\]' ++[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1q {za15v.q\[w15,1\]},p7,\[x0,x17,lsl#4\]' ++[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1q {za15h.q\[w15,1\]},p7,\[sp,x17,lsl#4\]' +diff --git a/gas/testsuite/gas/aarch64/sme-6-illegal.s b/gas/testsuite/gas/aarch64/sme-6-illegal.s +new file mode 100644 +index 00000000..d0de01d5 +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/sme-6-illegal.s +@@ -0,0 +1,46 @@ ++/* Scalable Matrix Extension (SME). */ ++ ++st1b {za0h.b[w11, 0]}, p0, [x0] ++st1h {za0h.h[w16, 0]}, p0, [x0] ++st1h {za0v.h[w12, 0]}, p0, [x0, x0, lsl #3] ++st1w {za3v.s[w15, 3]}, p7, [sp, lsl #2] ++st1d {za0h.d[w12, 0]}, p0, [sp, x0, lsl #12] ++st1q {za0v.q[w12]}, p0, [x0, x0, lsl #2] ++st1b {za1h.b[w12, 0]}, p0, [x0] ++st1b {za1v.b[w12, 0]}, p0, [sp] ++st1b {za1h.b[w12, 0]}, p0, [sp, x0] ++st1b {za0v.b[w15, 16]}, p7, [x17] ++st1b {za0h.b[w15, 16]}, p7, [sp] ++st1b {za0v.b[w15, 16]}, p7, [sp, x17] ++st1h {za2v.h[w12, 0]}, p0, [x0] ++st1h {za2h.h[w12, 0]}, p0, [sp] ++st1h {za2v.h[w12, 0]}, p0, [x0, x0, lsl #1] ++st1h {za2h.h[w12, 0]}, p0, [sp, x0, lsl #1] ++st1h {za1v.h[w15, 8]}, p7, [x17] ++st1h {za1h.h[w15, 8]}, p7, [sp] ++st1h {za1v.h[w15, 8]}, p7, [x0, x17, lsl #1] ++st1h {za1h.h[w15, 8]}, p7, [sp, x17, lsl #1] ++st1w {za4h.s[w12, 0]}, p0, [x0] ++st1w {za4v.s[w12, 0]}, p0, [sp] ++st1w {za4h.s[w12, 0]}, p0, [x0, x0, lsl #2] ++st1w {za4v.s[w12, 0]}, p0, [sp, x0, lsl #2] ++st1w {za3h.s[w15, 4]}, p7, [x17] ++st1w {za3v.s[w15, 4]}, p7, [sp] ++st1w {za3h.s[w15, 4]}, p7, [x0, x17, lsl #2] ++st1w {za3v.s[w15, 4]}, p7, [sp, x17, lsl #2] ++st1d {za8v.d[w12, 0]}, p0, [x0] ++st1d {za8h.d[w12, 0]}, p0, [sp] ++st1d {za8v.d[w12, 0]}, p0, [x0, x0, lsl #3] ++st1d {za8h.d[w12, 0]}, p0, [sp, x0, lsl #3] ++st1d {za7v.d[w15, 2]}, p7, [x17] ++st1d {za7h.d[w15, 2]}, p7, [sp] ++st1d {za7v.d[w15, 2]}, p7, [x0, x17, lsl #3] ++st1d {za7h.d[w15, 2]}, p7, [sp, x17, lsl #3] ++st1q {za16v.q[w12]}, p0, [x0] ++st1q {za16h.q[w12]}, p0, [sp] ++st1q {za16v.q[w12]}, p0, [x0, x0, lsl #4] ++st1q {za16h.q[w12]}, p0, [sp, x0, lsl #4] ++st1q {za15v.q[w15, 1]}, p7, [x17] ++st1q {za15h.q[w15, 1]}, p7, [sp] ++st1q {za15v.q[w15, 1]}, p7, [x0, x17, lsl #4] ++st1q {za15h.q[w15, 1]}, p7, [sp, x17, lsl #4] +diff --git a/gas/testsuite/gas/aarch64/sme-6.d b/gas/testsuite/gas/aarch64/sme-6.d +new file mode 100644 +index 00000000..1b1d32a1 +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/sme-6.d +@@ -0,0 +1,85 @@ ++#name: SME extension (ST1x instructions) ++#as: -march=armv8-a+sme ++#objdump: -dr ++ ++.*: file format .* ++ ++Disassembly of section \.text: ++ ++0+ <.*>: ++ 0: e03f0000 st1b {za0h.b\[w12, 0\]}, p0, \[x0, xzr\] ++ 4: e03f03e0 st1b {za0h.b\[w12, 0\]}, p0, \[sp, xzr\] ++ 8: e02003e0 st1b {za0h.b\[w12, 0\]}, p0, \[sp, x0\] ++ c: e03f7e2f st1b {za0h.b\[w15, 15\]}, p7, \[x17, xzr\] ++ 10: e03f7fef st1b {za0h.b\[w15, 15\]}, p7, \[sp, xzr\] ++ 14: e0317fef st1b {za0h.b\[w15, 15\]}, p7, \[sp, x17\] ++ 18: e07f0000 st1h {za0h.h\[w12, 0\]}, p0, \[x0, xzr, lsl #1\] ++ 1c: e07f03e0 st1h {za0h.h\[w12, 0\]}, p0, \[sp, xzr, lsl #1\] ++ 20: e0600000 st1h {za0h.h\[w12, 0\]}, p0, \[x0, x0, lsl #1\] ++ 24: e06003e0 st1h {za0h.h\[w12, 0\]}, p0, \[sp, x0, lsl #1\] ++ 28: e07f7e2f st1h {za1h.h\[w15, 7\]}, p7, \[x17, xzr, lsl #1\] ++ 2c: e07f7fef st1h {za1h.h\[w15, 7\]}, p7, \[sp, xzr, lsl #1\] ++ 30: e0717c0f st1h {za1h.h\[w15, 7\]}, p7, \[x0, x17, lsl #1\] ++ 34: e0717fef st1h {za1h.h\[w15, 7\]}, p7, \[sp, x17, lsl #1\] ++ 38: e0bf0000 st1w {za0h.s\[w12, 0\]}, p0, \[x0, xzr, lsl #2\] ++ 3c: e0bf03e0 st1w {za0h.s\[w12, 0\]}, p0, \[sp, xzr, lsl #2\] ++ 40: e0a00000 st1w {za0h.s\[w12, 0\]}, p0, \[x0, x0, lsl #2\] ++ 44: e0a003e0 st1w {za0h.s\[w12, 0\]}, p0, \[sp, x0, lsl #2\] ++ 48: e0bf7e2f st1w {za3h.s\[w15, 3\]}, p7, \[x17, xzr, lsl #2\] ++ 4c: e0bf7fef st1w {za3h.s\[w15, 3\]}, p7, \[sp, xzr, lsl #2\] ++ 50: e0b17c0f st1w {za3h.s\[w15, 3\]}, p7, \[x0, x17, lsl #2\] ++ 54: e0b17fef st1w {za3h.s\[w15, 3\]}, p7, \[sp, x17, lsl #2\] ++ 58: e0ff0000 st1d {za0h.d\[w12, 0\]}, p0, \[x0, xzr, lsl #3\] ++ 5c: e0ff03e0 st1d {za0h.d\[w12, 0\]}, p0, \[sp, xzr, lsl #3\] ++ 60: e0e00000 st1d {za0h.d\[w12, 0\]}, p0, \[x0, x0, lsl #3\] ++ 64: e0e003e0 st1d {za0h.d\[w12, 0\]}, p0, \[sp, x0, lsl #3\] ++ 68: e0ff7e2f st1d {za7h.d\[w15, 1\]}, p7, \[x17, xzr, lsl #3\] ++ 6c: e0ff7fef st1d {za7h.d\[w15, 1\]}, p7, \[sp, xzr, lsl #3\] ++ 70: e0f17c0f st1d {za7h.d\[w15, 1\]}, p7, \[x0, x17, lsl #3\] ++ 74: e0f17fef st1d {za7h.d\[w15, 1\]}, p7, \[sp, x17, lsl #3\] ++ 78: e1ff0000 st1q {za0h.q\[w12, 0\]}, p0, \[x0, xzr, lsl #4\] ++ 7c: e1ff03e0 st1q {za0h.q\[w12, 0\]}, p0, \[sp, xzr, lsl #4\] ++ 80: e1e00000 st1q {za0h.q\[w12, 0\]}, p0, \[x0, x0, lsl #4\] ++ 84: e1e003e0 st1q {za0h.q\[w12, 0\]}, p0, \[sp, x0, lsl #4\] ++ 88: e1ff7e2f st1q {za15h.q\[w15, 0\]}, p7, \[x17, xzr, lsl #4\] ++ 8c: e1ff7fef st1q {za15h.q\[w15, 0\]}, p7, \[sp, xzr, lsl #4\] ++ 90: e1f17c0f st1q {za15h.q\[w15, 0\]}, p7, \[x0, x17, lsl #4\] ++ 94: e1f17fef st1q {za15h.q\[w15, 0\]}, p7, \[sp, x17, lsl #4\] ++ 98: e03f8000 st1b {za0v.b\[w12, 0\]}, p0, \[x0, xzr\] ++ 9c: e03f83e0 st1b {za0v.b\[w12, 0\]}, p0, \[sp, xzr\] ++ a0: e02083e0 st1b {za0v.b\[w12, 0\]}, p0, \[sp, x0\] ++ a4: e03ffe2f st1b {za0v.b\[w15, 15\]}, p7, \[x17, xzr\] ++ a8: e03fffef st1b {za0v.b\[w15, 15\]}, p7, \[sp, xzr\] ++ ac: e031ffef st1b {za0v.b\[w15, 15\]}, p7, \[sp, x17\] ++ b0: e07f8000 st1h {za0v.h\[w12, 0\]}, p0, \[x0, xzr, lsl #1\] ++ b4: e07f83e0 st1h {za0v.h\[w12, 0\]}, p0, \[sp, xzr, lsl #1\] ++ b8: e0608000 st1h {za0v.h\[w12, 0\]}, p0, \[x0, x0, lsl #1\] ++ bc: e06083e0 st1h {za0v.h\[w12, 0\]}, p0, \[sp, x0, lsl #1\] ++ c0: e07ffe2f st1h {za1v.h\[w15, 7\]}, p7, \[x17, xzr, lsl #1\] ++ c4: e07fffef st1h {za1v.h\[w15, 7\]}, p7, \[sp, xzr, lsl #1\] ++ c8: e071fc0f st1h {za1v.h\[w15, 7\]}, p7, \[x0, x17, lsl #1\] ++ cc: e071ffef st1h {za1v.h\[w15, 7\]}, p7, \[sp, x17, lsl #1\] ++ d0: e0bf8000 st1w {za0v.s\[w12, 0\]}, p0, \[x0, xzr, lsl #2\] ++ d4: e0bf83e0 st1w {za0v.s\[w12, 0\]}, p0, \[sp, xzr, lsl #2\] ++ d8: e0a08000 st1w {za0v.s\[w12, 0\]}, p0, \[x0, x0, lsl #2\] ++ dc: e0a083e0 st1w {za0v.s\[w12, 0\]}, p0, \[sp, x0, lsl #2\] ++ e0: e0bffe2f st1w {za3v.s\[w15, 3\]}, p7, \[x17, xzr, lsl #2\] ++ e4: e0bfffef st1w {za3v.s\[w15, 3\]}, p7, \[sp, xzr, lsl #2\] ++ e8: e0b1fc0f st1w {za3v.s\[w15, 3\]}, p7, \[x0, x17, lsl #2\] ++ ec: e0b1ffef st1w {za3v.s\[w15, 3\]}, p7, \[sp, x17, lsl #2\] ++ f0: e0ff8000 st1d {za0v.d\[w12, 0\]}, p0, \[x0, xzr, lsl #3\] ++ f4: e0ff83e0 st1d {za0v.d\[w12, 0\]}, p0, \[sp, xzr, lsl #3\] ++ f8: e0e08000 st1d {za0v.d\[w12, 0\]}, p0, \[x0, x0, lsl #3\] ++ fc: e0e083e0 st1d {za0v.d\[w12, 0\]}, p0, \[sp, x0, lsl #3\] ++ 100: e0fffe2f st1d {za7v.d\[w15, 1\]}, p7, \[x17, xzr, lsl #3\] ++ 104: e0ffffef st1d {za7v.d\[w15, 1\]}, p7, \[sp, xzr, lsl #3\] ++ 108: e0f1fc0f st1d {za7v.d\[w15, 1\]}, p7, \[x0, x17, lsl #3\] ++ 10c: e0f1ffef st1d {za7v.d\[w15, 1\]}, p7, \[sp, x17, lsl #3\] ++ 110: e1ff8000 st1q {za0v.q\[w12, 0\]}, p0, \[x0, xzr, lsl #4\] ++ 114: e1ff83e0 st1q {za0v.q\[w12, 0\]}, p0, \[sp, xzr, lsl #4\] ++ 118: e1e08000 st1q {za0v.q\[w12, 0\]}, p0, \[x0, x0, lsl #4\] ++ 11c: e1e083e0 st1q {za0v.q\[w12, 0\]}, p0, \[sp, x0, lsl #4\] ++ 120: e1fffe2f st1q {za15v.q\[w15, 0\]}, p7, \[x17, xzr, lsl #4\] ++ 124: e1ffffef st1q {za15v.q\[w15, 0\]}, p7, \[sp, xzr, lsl #4\] ++ 128: e1f1fc0f st1q {za15v.q\[w15, 0\]}, p7, \[x0, x17, lsl #4\] ++ 12c: e1f1ffef st1q {za15v.q\[w15, 0\]}, p7, \[sp, x17, lsl #4\] +diff --git a/gas/testsuite/gas/aarch64/sme-6.s b/gas/testsuite/gas/aarch64/sme-6.s +new file mode 100644 +index 00000000..143f02a2 +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/sme-6.s +@@ -0,0 +1,86 @@ ++/* SME Extension (ST1x instructions). */ ++st1b {za0h.b[w12, 0]}, p0, [x0] ++st1b {za0h.b[w12, 0]}, p0, [sp] ++st1b {za0h.b[w12, 0]}, p0, [sp, x0] ++st1b {za0h.b[w15, 15]}, p7, [x17] ++st1b {za0h.b[w15, 15]}, p7, [sp] ++st1b {za0h.b[w15, 15]}, p7, [sp, x17] ++ ++st1h {za0h.h[w12, 0]}, p0, [x0] ++st1h {za0h.h[w12, 0]}, p0, [sp] ++st1h {za0h.h[w12, 0]}, p0, [x0, x0, lsl #1] ++st1h {za0h.h[w12, 0]}, p0, [sp, x0, lsl #1] ++st1h {za1h.h[w15, 7]}, p7, [x17] ++st1h {za1h.h[w15, 7]}, p7, [sp] ++st1h {za1h.h[w15, 7]}, p7, [x0, x17, lsl #1] ++st1h {za1h.h[w15, 7]}, p7, [sp, x17, lsl #1] ++ ++st1w {za0h.s[w12, 0]}, p0, [x0] ++st1w {za0h.s[w12, 0]}, p0, [sp] ++st1w {za0h.s[w12, 0]}, p0, [x0, x0, lsl #2] ++st1w {za0h.s[w12, 0]}, p0, [sp, x0, lsl #2] ++st1w {za3h.s[w15, 3]}, p7, [x17] ++st1w {za3h.s[w15, 3]}, p7, [sp] ++st1w {za3h.s[w15, 3]}, p7, [x0, x17, lsl #2] ++st1w {za3h.s[w15, 3]}, p7, [sp, x17, lsl #2] ++ ++st1d {za0h.d[w12, 0]}, p0, [x0] ++st1d {za0h.d[w12, 0]}, p0, [sp] ++st1d {za0h.d[w12, 0]}, p0, [x0, x0, lsl #3] ++st1d {za0h.d[w12, 0]}, p0, [sp, x0, lsl #3] ++st1d {za7h.d[w15, 1]}, p7, [x17] ++st1d {za7h.d[w15, 1]}, p7, [sp] ++st1d {za7h.d[w15, 1]}, p7, [x0, x17, lsl #3] ++st1d {za7h.d[w15, 1]}, p7, [sp, x17, lsl #3] ++ ++st1q {za0h.q[w12, 0]}, p0, [x0] ++st1q {za0h.q[w12, 0]}, p0, [sp] ++st1q {za0h.q[w12, 0]}, p0, [x0, x0, lsl #4] ++st1q {za0h.q[w12, 0]}, p0, [sp, x0, lsl #4] ++st1q {za15h.q[w15, 0]}, p7, [x17] ++st1q {za15h.q[w15, 0]}, p7, [sp] ++st1q {za15h.q[w15, 0]}, p7, [x0, x17, lsl #4] ++st1q {za15h.q[w15, 0]}, p7, [sp, x17, lsl #4] ++ ++st1b {za0v.b[w12, 0]}, p0, [x0] ++st1b {za0v.b[w12, 0]}, p0, [sp] ++st1b {za0v.b[w12, 0]}, p0, [sp, x0] ++st1b {za0v.b[w15, 15]}, p7, [x17] ++st1b {za0v.b[w15, 15]}, p7, [sp] ++st1b {za0v.b[w15, 15]}, p7, [sp, x17] ++ ++st1h {za0v.h[w12, 0]}, p0, [x0] ++st1h {za0v.h[w12, 0]}, p0, [sp] ++st1h {za0v.h[w12, 0]}, p0, [x0, x0, lsl #1] ++st1h {za0v.h[w12, 0]}, p0, [sp, x0, lsl #1] ++st1h {za1v.h[w15, 7]}, p7, [x17] ++st1h {za1v.h[w15, 7]}, p7, [sp] ++st1h {za1v.h[w15, 7]}, p7, [x0, x17, lsl #1] ++st1h {za1v.h[w15, 7]}, p7, [sp, x17, lsl #1] ++ ++st1w {za0v.s[w12, 0]}, p0, [x0] ++st1w {za0v.s[w12, 0]}, p0, [sp] ++st1w {za0v.s[w12, 0]}, p0, [x0, x0, lsl #2] ++st1w {za0v.s[w12, 0]}, p0, [sp, x0, lsl #2] ++st1w {za3v.s[w15, 3]}, p7, [x17] ++st1w {za3v.s[w15, 3]}, p7, [sp] ++st1w {za3v.s[w15, 3]}, p7, [x0, x17, lsl #2] ++st1w {za3v.s[w15, 3]}, p7, [sp, x17, lsl #2] ++ ++st1d {za0v.d[w12, 0]}, p0, [x0] ++st1d {za0v.d[w12, 0]}, p0, [sp] ++st1d {za0v.d[w12, 0]}, p0, [x0, x0, lsl #3] ++st1d {za0v.d[w12, 0]}, p0, [sp, x0, lsl #3] ++st1d {za7v.d[w15, 1]}, p7, [x17] ++st1d {za7v.d[w15, 1]}, p7, [sp] ++st1d {za7v.d[w15, 1]}, p7, [x0, x17, lsl #3] ++st1d {za7v.d[w15, 1]}, p7, [sp, x17, lsl #3] ++ ++st1q {za0v.q[w12, 0]}, p0, [x0] ++st1q {za0v.q[w12, 0]}, p0, [sp] ++st1q {za0v.q[w12, 0]}, p0, [x0, x0, lsl #4] ++st1q {za0v.q[w12, 0]}, p0, [sp, x0, lsl #4] ++st1q {za15v.q[w15, 0]}, p7, [x17] ++st1q {za15v.q[w15, 0]}, p7, [sp] ++st1q {za15v.q[w15, 0]}, p7, [x0, x17, lsl #4] ++st1q {za15v.q[w15, 0]}, p7, [sp, x17, lsl #4] +diff --git a/gas/testsuite/gas/aarch64/sme-7-illegal.d b/gas/testsuite/gas/aarch64/sme-7-illegal.d +new file mode 100644 +index 00000000..d9ca5867 +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/sme-7-illegal.d +@@ -0,0 +1,3 @@ ++#as: -march=armv8-a+sme ++#source: sme-7-illegal.s ++#error_output: sme-7-illegal.l +diff --git a/gas/testsuite/gas/aarch64/sme-7-illegal.l b/gas/testsuite/gas/aarch64/sme-7-illegal.l +new file mode 100644 +index 00000000..913bd0ee +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/sme-7-illegal.l +@@ -0,0 +1,33 @@ ++[^:]*: Assembler messages: ++[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 1 -- `ldr za\[w11,0\],\[x0\]' ++[^:]*:[0-9]+: Error: invalid addressing mode at operand 2 -- `ldr za\[w12,1\],\[sp,x0\]' ++[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `ldr za\[w12,0\],\[sp,#1,mul vl\]' ++[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `ldr za\[w13,9\],\[x17,#19,mul vl\]' ++[^:]*:[0-9]+: Error: offset out of range at operand 1 -- `ldr za\[w13,21\],\[x17,#21,mul vl\]' ++[^:]*:[0-9]+: Error: offset out of range at operand 1 -- `ldr za\[w15,32\],\[x17,#15,mul vl\]' ++[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 1 -- `ldr za\[w16,15\],\[sp,#15,mul vl\]' ++[^:]*:[0-9]+: Error: only 'MUL VL' is permitted at operand 2 -- `ldr za\[w12,0\],\[x0,#0,mul#1\]' ++[^:]*:[0-9]+: Error: only 'MUL VL' is permitted at operand 2 -- `ldr za\[w13,0\],\[sp,#0,mul#2\]' ++[^:]*:[0-9]+: Error: only 'MUL VL' is permitted at operand 2 -- `ldr za\[w14,9\],\[x17,#9,mul#3\]' ++[^:]*:[0-9]+: Error: only 'MUL VL' is permitted at operand 2 -- `ldr za\[w15,15\],\[sp,#15,mul#4\]' ++[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 1 -- `str za\[w11,0\],\[x0\]' ++[^:]*:[0-9]+: Error: invalid addressing mode at operand 2 -- `str za\[w12,1\],\[sp,x0\]' ++[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `str za\[w12,0\],\[sp,#1,mul vl\]' ++[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `str za\[w13,9\],\[x17,#19,mul vl\]' ++[^:]*:[0-9]+: Error: offset out of range at operand 1 -- `str za\[w13,21\],\[x17,#21,mul vl\]' ++[^:]*:[0-9]+: Error: offset out of range at operand 1 -- `str za\[w15,32\],\[x17,#15,mul vl\]' ++[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 1 -- `str za\[w16,15\],\[sp,#15,mul vl\]' ++[^:]*:[0-9]+: Error: only 'MUL VL' is permitted at operand 2 -- `str za\[w12,0\],\[x0,#0,mul#1\]' ++[^:]*:[0-9]+: Error: only 'MUL VL' is permitted at operand 2 -- `str za\[w13,0\],\[sp,#0,mul#2\]' ++[^:]*:[0-9]+: Error: only 'MUL VL' is permitted at operand 2 -- `str za\[w14,9\],\[x17,#9,mul#3\]' ++[^:]*:[0-9]+: Error: only 'MUL VL' is permitted at operand 2 -- `str za\[w15,15\],\[sp,#15,mul#4\]' ++[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `ldr za\[w13,13\],\[x17,#23,mul vl\]' ++[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `str za\[w13,13\],\[x17,#23,mul vl\]' ++[^:]*:[0-9]+: Error: offset out of range at operand 1 -- `ldr za\[w13,23\],\[x17,#13,mul vl\]' ++[^:]*:[0-9]+: Error: offset out of range at operand 1 -- `str za\[w13,23\],\[x17,#13,mul vl\]' ++[^:]*:[0-9]+: Error: offset out of range at operand 1 -- `ldr za\[w13,16\],\[x17,#16,mul vl\]' ++[^:]*:[0-9]+: Error: offset out of range at operand 1 -- `str za\[w13,16\],\[x17,#16,mul vl\]' ++[^:]*:[0-9]+: Error: offset out of range at operand 1 -- `ldr za\[w13,-1\],\[x17,#1,mul vl\]' ++[^:]*:[0-9]+: Error: offset out of range at operand 1 -- `str za\[w13,-1\],\[x17,#1,mul vl\]' ++[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `ldr za\[w13,1\],\[x17,#-1,mul vl\]' ++[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `str za\[w13,1\],\[x17,#-1,mul vl\]' +diff --git a/gas/testsuite/gas/aarch64/sme-7-illegal.s b/gas/testsuite/gas/aarch64/sme-7-illegal.s +new file mode 100644 +index 00000000..0d92d843 +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/sme-7-illegal.s +@@ -0,0 +1,39 @@ ++/* Scalable Matrix Extension (SME). */ ++ ++/* Load vector to ZA array. */ ++ldr za[w11, 0], [x0] ++ldr za[w12, 1], [sp, x0] ++ldr za[w12, 0], [sp, #1, mul vl] ++ldr za[w13, 9], [x17, #19, mul vl] ++ldr za[w13, 21], [x17, #21, mul vl] ++ldr za[w15, 32], [x17, #15, mul vl] ++ldr za[w16, 15], [sp, #15, mul vl] ++ldr za[w12, 0], [x0, #0, mul #1] ++ldr za[w13, 0], [sp, #0, mul #2] ++ldr za[w14, 9], [x17, #9, mul #3] ++ldr za[w15, 15], [sp, #15, mul #4] ++ ++/* Store vector from ZA array. */ ++str za[w11, 0], [x0] ++str za[w12, 1], [sp, x0] ++str za[w12, 0], [sp, #1, mul vl] ++str za[w13, 9], [x17, #19, mul vl] ++str za[w13, 21], [x17, #21, mul vl] ++str za[w15, 32], [x17, #15, mul vl] ++str za[w16, 15], [sp, #15, mul vl] ++str za[w12, 0], [x0, #0, mul #1] ++str za[w13, 0], [sp, #0, mul #2] ++str za[w14, 9], [x17, #9, mul #3] ++str za[w15, 15], [sp, #15, mul #4] ++ ++/* Operands indexes are tied. */ ++ldr za[w13, 13], [x17, #23, mul vl] ++str za[w13, 13], [x17, #23, mul vl] ++ldr za[w13, 23], [x17, #13, mul vl] ++str za[w13, 23], [x17, #13, mul vl] ++ldr za[w13, 16], [x17, #16, mul vl] ++str za[w13, 16], [x17, #16, mul vl] ++ldr za[w13, -1], [x17, #1, mul vl] ++str za[w13, -1], [x17, #1, mul vl] ++ldr za[w13, 1], [x17, #-1, mul vl] ++str za[w13, 1], [x17, #-1, mul vl] +diff --git a/gas/testsuite/gas/aarch64/sme-7.d b/gas/testsuite/gas/aarch64/sme-7.d +new file mode 100644 +index 00000000..19a3e617 +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/sme-7.d +@@ -0,0 +1,27 @@ ++#name: SME extension (LDR and STR instructions) ++#as: -march=armv8-a+sme ++#objdump: -dr ++ ++.*: file format .* ++ ++Disassembly of section \.text: ++ ++0+ <.*>: ++ 0: e1000000 ldr za\[w12, 0\], \[x0\] ++ 4: e10003e0 ldr za\[w12, 0\], \[sp\] ++ 8: e1000000 ldr za\[w12, 0\], \[x0\] ++ c: e10003e0 ldr za\[w12, 0\], \[sp\] ++ 10: e1006220 ldr za\[w15, 0\], \[x17\] ++ 14: e1002229 ldr za\[w13, 9\], \[x17, #9, mul vl\] ++ 18: e100622f ldr za\[w15, 15\], \[x17, #15, mul vl\] ++ 1c: e10063ef ldr za\[w15, 15\], \[sp, #15, mul vl\] ++ 20: e1200000 str za\[w12, 0\], \[x0\] ++ 24: e12003e0 str za\[w12, 0\], \[sp\] ++ 28: e1200000 str za\[w12, 0\], \[x0\] ++ 2c: e12003e0 str za\[w12, 0\], \[sp\] ++ 30: e1206220 str za\[w15, 0\], \[x17\] ++ 34: e1202229 str za\[w13, 9\], \[x17, #9, mul vl\] ++ 38: e120622f str za\[w15, 15\], \[x17, #15, mul vl\] ++ 3c: e12063ef str za\[w15, 15\], \[sp, #15, mul vl\] ++ 40: e10003e0 ldr za\[w12, 0\], \[sp\] ++ 44: e1206220 str za\[w15, 0\], \[x17\] +diff --git a/gas/testsuite/gas/aarch64/sme-7.s b/gas/testsuite/gas/aarch64/sme-7.s +new file mode 100644 +index 00000000..7582d6cc +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/sme-7.s +@@ -0,0 +1,27 @@ ++/* SME Extension (LDR and STR instructions). */ ++/* Load vector to ZA array. */ ++ldr za[w12, 0], [x0] ++ldr za[w12, 0], [sp] ++ldr za[w12, 0], [x0, #0, mul vl] ++ldr za[w12, 0], [sp, #0, mul vl] ++ldr za[w15, 0], [x17] ++ldr za[w13, 9], [x17, #9, mul vl] ++ldr za[w15, 15], [x17, #15, mul vl] ++ldr za[w15, 15], [sp, #15, mul vl] ++ ++/* Store vector from ZA array. */ ++str za[w12, 0], [x0] ++str za[w12, 0], [sp] ++str za[w12, 0], [x0, #0, mul vl] ++str za[w12, 0], [sp, #0, mul vl] ++str za[w15, 0], [x17] ++str za[w13, 9], [x17, #9, mul vl] ++str za[w15, 15], [x17, #15, mul vl] ++str za[w15, 15], [sp, #15, mul vl] ++ ++/* Register aliases. */ ++foo .req w12 ++bar .req w15 ++ ++ldr za[foo, 0], [sp, #0, mul vl] ++str za[bar, 0], [x17] +diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h +index f5ce036e..3a4d5e0a 100644 +--- a/include/opcode/aarch64.h ++++ b/include/opcode/aarch64.h +@@ -332,7 +332,6 @@ enum aarch64_opnd + AARCH64_OPND_PRFOP, /* Prefetch operation. */ + AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */ + AARCH64_OPND_BTI_TARGET, /* BTI {}. */ +- + AARCH64_OPND_SVE_ADDR_RI_S4x16, /* SVE [, #*16]. */ + AARCH64_OPND_SVE_ADDR_RI_S4x32, /* SVE [, #*32]. */ + AARCH64_OPND_SVE_ADDR_RI_S4xVL, /* SVE [, #, MUL VL]. */ +@@ -350,6 +349,7 @@ enum aarch64_opnd + AARCH64_OPND_SVE_ADDR_RR_LSL1, /* SVE [, , LSL #1]. */ + AARCH64_OPND_SVE_ADDR_RR_LSL2, /* SVE [, , LSL #2]. */ + AARCH64_OPND_SVE_ADDR_RR_LSL3, /* SVE [, , LSL #3]. */ ++ AARCH64_OPND_SVE_ADDR_RR_LSL4, /* SVE [, , LSL #4]. */ + AARCH64_OPND_SVE_ADDR_RX, /* SVE [, ]. */ + AARCH64_OPND_SVE_ADDR_RX_LSL1, /* SVE [, , LSL #1]. */ + AARCH64_OPND_SVE_ADDR_RX_LSL2, /* SVE [, , LSL #2]. */ +@@ -446,6 +446,9 @@ enum aarch64_opnd + AARCH64_OPND_SME_ZA_HV_idx_dest, /* SME destination ZA tile vector. */ + AARCH64_OPND_SME_Pm, /* SME scalable predicate register, bits [15:13]. */ + AARCH64_OPND_SME_list_of_64bit_tiles, /* SME list of ZA tiles. */ ++ AARCH64_OPND_SME_ZA_HV_idx_ldstr, /* SME destination ZA tile vector. */ ++ AARCH64_OPND_SME_ZA_array, /* SME ZA[{, #}]. */ ++ AARCH64_OPND_SME_ADDR_RI_U4xVL, /* SME [{, #, MUL VL}]. */ + AARCH64_OPND_TME_UIMM16, /* TME unsigned 16-bit immediate. */ + AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */ + }; +@@ -611,6 +614,8 @@ enum aarch64_insn_class + pcreladdr, + ic_system, + sme_misc, ++ sme_ldr, ++ sme_str, + sve_cpy, + sve_index, + sve_limm, +@@ -1210,6 +1215,10 @@ struct aarch64_inst + No syntax error, but the operands are not a valid combination, e.g. + FMOV D0,S0 + ++ AARCH64_OPDE_UNTIED_IMMS ++ The asm failed to use the same immediate for a destination operand ++ and a tied source operand. ++ + AARCH64_OPDE_UNTIED_OPERAND + The asm failed to use the same register for a destination operand + and a tied source operand. +@@ -1250,6 +1259,7 @@ enum aarch64_operand_error_kind + AARCH64_OPDE_SYNTAX_ERROR, + AARCH64_OPDE_FATAL_SYNTAX_ERROR, + AARCH64_OPDE_INVALID_VARIANT, ++ AARCH64_OPDE_UNTIED_IMMS, + AARCH64_OPDE_UNTIED_OPERAND, + AARCH64_OPDE_OUT_OF_RANGE, + AARCH64_OPDE_UNALIGNED, +diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c +index 0e048424..54ec35aa 100644 +--- a/opcodes/aarch64-asm-2.c ++++ b/opcodes/aarch64-asm-2.c +@@ -640,7 +640,6 @@ aarch64_insert_operand (const aarch64_operand *self, + case 29: + case 30: + case 31: +- case 166: + case 167: + case 168: + case 169: +@@ -650,7 +649,7 @@ aarch64_insert_operand (const aarch64_operand *self, + case 173: + case 174: + case 175: +- case 190: ++ case 176: + case 191: + case 192: + case 193: +@@ -659,11 +658,12 @@ aarch64_insert_operand (const aarch64_operand *self, + case 196: + case 197: + case 198: +- case 204: +- case 207: +- case 209: ++ case 199: ++ case 205: ++ case 208: + case 210: +- case 213: ++ case 211: ++ case 214: + return aarch64_ins_regno (self, info, code, inst, errors); + case 15: + return aarch64_ins_reg_extended (self, info, code, inst, errors); +@@ -675,7 +675,7 @@ aarch64_insert_operand (const aarch64_operand *self, + case 33: + case 34: + case 35: +- case 216: ++ case 220: + return aarch64_ins_reglane (self, info, code, inst, errors); + case 36: + return aarch64_ins_reglist (self, info, code, inst, errors); +@@ -710,9 +710,8 @@ aarch64_insert_operand (const aarch64_operand *self, + case 82: + case 83: + case 84: +- case 163: +- case 165: +- case 182: ++ case 164: ++ case 166: + case 183: + case 184: + case 185: +@@ -720,8 +719,9 @@ aarch64_insert_operand (const aarch64_operand *self, + case 187: + case 188: + case 189: +- case 214: ++ case 190: + case 215: ++ case 219: + return aarch64_ins_imm (self, info, code, inst, errors); + case 44: + case 45: +@@ -731,10 +731,10 @@ aarch64_insert_operand (const aarch64_operand *self, + case 48: + return aarch64_ins_advsimd_imm_modified (self, info, code, inst, errors); + case 52: +- case 153: ++ case 154: + return aarch64_ins_fpimm (self, info, code, inst, errors); + case 70: +- case 161: ++ case 162: + return aarch64_ins_limm (self, info, code, inst, errors); + case 71: + return aarch64_ins_aimm (self, info, code, inst, errors); +@@ -744,11 +744,11 @@ aarch64_insert_operand (const aarch64_operand *self, + return aarch64_ins_fbits (self, info, code, inst, errors); + case 75: + case 76: +- case 158: ++ case 159: + return aarch64_ins_imm_rotate2 (self, info, code, inst, errors); + case 77: +- case 157: +- case 159: ++ case 158: ++ case 160: + return aarch64_ins_imm_rotate1 (self, info, code, inst, errors); + case 78: + case 79: +@@ -824,8 +824,8 @@ aarch64_insert_operand (const aarch64_operand *self, + case 133: + case 134: + case 135: +- return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors); + case 136: ++ return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors); + case 137: + case 138: + case 139: +@@ -833,56 +833,62 @@ aarch64_insert_operand (const aarch64_operand *self, + case 141: + case 142: + case 143: +- return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors); + case 144: ++ return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors); + case 145: + case 146: + case 147: +- return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors); + case 148: +- return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors); ++ return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors); + case 149: +- return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors); ++ return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors); + case 150: +- return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors); ++ return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors); + case 151: +- return aarch64_ins_sve_aimm (self, info, code, inst, errors); ++ return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors); + case 152: ++ return aarch64_ins_sve_aimm (self, info, code, inst, errors); ++ case 153: + return aarch64_ins_sve_asimm (self, info, code, inst, errors); +- case 154: +- return aarch64_ins_sve_float_half_one (self, info, code, inst, errors); + case 155: +- return aarch64_ins_sve_float_half_two (self, info, code, inst, errors); ++ return aarch64_ins_sve_float_half_one (self, info, code, inst, errors); + case 156: ++ return aarch64_ins_sve_float_half_two (self, info, code, inst, errors); ++ case 157: + return aarch64_ins_sve_float_zero_one (self, info, code, inst, errors); +- case 160: ++ case 161: + return aarch64_ins_inv_limm (self, info, code, inst, errors); +- case 162: ++ case 163: + return aarch64_ins_sve_limm_mov (self, info, code, inst, errors); +- case 164: ++ case 165: + return aarch64_ins_sve_scale (self, info, code, inst, errors); +- case 176: + case 177: + case 178: +- return aarch64_ins_sve_shlimm (self, info, code, inst, errors); + case 179: ++ return aarch64_ins_sve_shlimm (self, info, code, inst, errors); + case 180: + case 181: ++ case 182: + return aarch64_ins_sve_shrimm (self, info, code, inst, errors); +- case 199: + case 200: + case 201: + case 202: + case 203: ++ case 204: + return aarch64_ins_sve_quad_index (self, info, code, inst, errors); +- case 205: +- return aarch64_ins_sve_index (self, info, code, inst, errors); + case 206: +- case 208: ++ return aarch64_ins_sve_index (self, info, code, inst, errors); ++ case 207: ++ case 209: + return aarch64_ins_sve_reglist (self, info, code, inst, errors); +- case 211: + case 212: ++ case 213: ++ case 216: + return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors); ++ case 217: ++ return aarch64_ins_sme_za_array (self, info, code, inst, errors); ++ case 218: ++ return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors); + default: assert (0); abort (); + } + } +diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c +index 9a77d0f7..a2b0e864 100644 +--- a/opcodes/aarch64-asm.c ++++ b/opcodes/aarch64-asm.c +@@ -1380,6 +1380,53 @@ aarch64_ins_sme_za_hv_tiles (const aarch64_operand *self, + return true; + } + ++/* Encode in SME instruction ZERO list of up to eight 64-bit element tile names ++ separated by commas, encoded in the "imm8" field. ++ ++ For programmer convenience an assembler must also accept the names of ++ 32-bit, 16-bit and 8-bit element tiles which are converted into the ++ corresponding set of 64-bit element tiles. ++*/ ++bool ++aarch64_ins_sme_za_list (const aarch64_operand *self, ++ const aarch64_opnd_info *info, ++ aarch64_insn *code, ++ const aarch64_inst *inst ATTRIBUTE_UNUSED, ++ aarch64_operand_error *errors ATTRIBUTE_UNUSED) ++{ ++ int fld_mask = info->imm.value; ++ insert_field (self->fields[0], code, fld_mask, 0); ++ return true; ++} ++ ++bool ++aarch64_ins_sme_za_array (const aarch64_operand *self, ++ const aarch64_opnd_info *info, ++ aarch64_insn *code, ++ const aarch64_inst *inst ATTRIBUTE_UNUSED, ++ aarch64_operand_error *errors ATTRIBUTE_UNUSED) ++{ ++ int regno = info->za_tile_vector.index.regno - 12; ++ int imm = info->za_tile_vector.index.imm; ++ insert_field (self->fields[0], code, regno, 0); ++ insert_field (self->fields[1], code, imm, 0); ++ return true; ++} ++ ++bool ++aarch64_ins_sme_addr_ri_u4xvl (const aarch64_operand *self, ++ const aarch64_opnd_info *info, ++ aarch64_insn *code, ++ const aarch64_inst *inst ATTRIBUTE_UNUSED, ++ aarch64_operand_error *errors ATTRIBUTE_UNUSED) ++{ ++ int regno = info->addr.base_regno; ++ int imm = info->addr.offset.imm; ++ insert_field (self->fields[0], code, regno, 0); ++ insert_field (self->fields[1], code, imm, 0); ++ return true; ++} ++ + /* Miscellaneous encoding functions. */ + + /* Encode size[0], i.e. bit 22, for +diff --git a/opcodes/aarch64-asm.h b/opcodes/aarch64-asm.h +index 9cbcd7a8..1f9e85c2 100644 +--- a/opcodes/aarch64-asm.h ++++ b/opcodes/aarch64-asm.h +@@ -99,6 +99,9 @@ AARCH64_DECL_OPD_INSERTER (ins_sve_scale); + AARCH64_DECL_OPD_INSERTER (ins_sve_shlimm); + AARCH64_DECL_OPD_INSERTER (ins_sve_shrimm); + AARCH64_DECL_OPD_INSERTER (ins_sme_za_hv_tiles); ++AARCH64_DECL_OPD_INSERTER (ins_sme_za_list); ++AARCH64_DECL_OPD_INSERTER (ins_sme_za_array); ++AARCH64_DECL_OPD_INSERTER (ins_sme_addr_ri_u4xvl); + AARCH64_DECL_OPD_INSERTER (ins_imm_rotate1); + AARCH64_DECL_OPD_INSERTER (ins_imm_rotate2); + +diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c +index 9dd9402a..5ce26ddc 100644 +--- a/opcodes/aarch64-dis-2.c ++++ b/opcodes/aarch64-dis-2.c +@@ -173,19 +173,63 @@ aarch64_opcode_lookup_1 (uint32_t word) + { + if (((word >> 22) & 0x1) == 0) + { +- /* 33222222222211111111110000000000 +- 10987654321098765432109876543210 +- xx100000x00xxxxxxxxxxxxxxxx0xxxx +- smopa. */ +- return 2360; ++ if (((word >> 23) & 0x1) == 0) ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ xx100000000xxxxxxxxxxxxxxxx0xxxx ++ ld1b. */ ++ return 2381; ++ } ++ else ++ { ++ if (((word >> 30) & 0x1) == 0) ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ x0100000100xxxxxxxxxxxxxxxx0xxxx ++ smopa. */ ++ return 2360; ++ } ++ else ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ x1100000100xxxxxxxxxxxxxxxx0xxxx ++ ld1w. */ ++ return 2383; ++ } ++ } + } + else + { +- /* 33222222222211111111110000000000 +- 10987654321098765432109876543210 +- xx100000x10xxxxxxxxxxxxxxxx0xxxx +- smopa. */ +- return 2361; ++ if (((word >> 23) & 0x1) == 0) ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ xx100000010xxxxxxxxxxxxxxxx0xxxx ++ ld1h. */ ++ return 2382; ++ } ++ else ++ { ++ if (((word >> 30) & 0x1) == 0) ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ x0100000110xxxxxxxxxxxxxxxx0xxxx ++ smopa. */ ++ return 2361; ++ } ++ else ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ x1100000110xxxxxxxxxxxxxxxx0xxxx ++ ld1d. */ ++ return 2384; ++ } ++ } + } + } + else +@@ -215,19 +259,63 @@ aarch64_opcode_lookup_1 (uint32_t word) + { + if (((word >> 22) & 0x1) == 0) + { +- /* 33222222222211111111110000000000 +- 10987654321098765432109876543210 +- xxx00000x01xxxxxxxxxxxxxxxx0xxxx +- sumopa. */ +- return 2364; ++ if (((word >> 23) & 0x1) == 0) ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ xxx00000001xxxxxxxxxxxxxxxx0xxxx ++ st1b. */ ++ return 2391; ++ } ++ else ++ { ++ if (((word >> 30) & 0x1) == 0) ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ x0x00000101xxxxxxxxxxxxxxxx0xxxx ++ sumopa. */ ++ return 2364; ++ } ++ else ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ x1x00000101xxxxxxxxxxxxxxxx0xxxx ++ st1w. */ ++ return 2393; ++ } ++ } + } + else + { +- /* 33222222222211111111110000000000 +- 10987654321098765432109876543210 +- xxx00000x11xxxxxxxxxxxxxxxx0xxxx +- sumopa. */ +- return 2365; ++ if (((word >> 23) & 0x1) == 0) ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ xxx00000011xxxxxxxxxxxxxxxx0xxxx ++ st1h. */ ++ return 2392; ++ } ++ else ++ { ++ if (((word >> 30) & 0x1) == 0) ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ x0x00000111xxxxxxxxxxxxxxxx0xxxx ++ sumopa. */ ++ return 2365; ++ } ++ else ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ x1x00000111xxxxxxxxxxxxxxxx0xxxx ++ st1d. */ ++ return 2394; ++ } ++ } + } + } + else +@@ -281,60 +369,104 @@ aarch64_opcode_lookup_1 (uint32_t word) + { + if (((word >> 22) & 0x1) == 0) + { +- if (((word >> 29) & 0x1) == 0) ++ if (((word >> 23) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 +- xx000001x00xxxxxxxxxxxxxxxx0xxxx +- bfmopa. */ +- return 2352; ++ xxx00001000xxxxxxxxxxxxxxxx0xxxx ++ ldr. */ ++ return 2401; + } + else + { +- /* 33222222222211111111110000000000 +- 10987654321098765432109876543210 +- xx100001x00xxxxxxxxxxxxxxxx0xxxx +- usmopa. */ +- return 2372; ++ if (((word >> 29) & 0x1) == 0) ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ xx000001100xxxxxxxxxxxxxxxx0xxxx ++ bfmopa. */ ++ return 2352; ++ } ++ else ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ xx100001100xxxxxxxxxxxxxxxx0xxxx ++ usmopa. */ ++ return 2372; ++ } + } + } + else + { +- /* 33222222222211111111110000000000 +- 10987654321098765432109876543210 +- xxx00001x10xxxxxxxxxxxxxxxx0xxxx +- usmopa. */ +- return 2373; ++ if (((word >> 30) & 0x1) == 0) ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ x0x00001x10xxxxxxxxxxxxxxxx0xxxx ++ usmopa. */ ++ return 2373; ++ } ++ else ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ x1x00001x10xxxxxxxxxxxxxxxx0xxxx ++ ld1q. */ ++ return 2385; ++ } + } + } + else + { + if (((word >> 22) & 0x1) == 0) + { +- if (((word >> 29) & 0x1) == 0) ++ if (((word >> 23) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 +- xx000001x01xxxxxxxxxxxxxxxx0xxxx +- fmopa. */ +- return 2356; ++ xxx00001001xxxxxxxxxxxxxxxx0xxxx ++ str. */ ++ return 2402; + } + else + { +- /* 33222222222211111111110000000000 +- 10987654321098765432109876543210 +- xx100001x01xxxxxxxxxxxxxxxx0xxxx +- umopa. */ +- return 2368; ++ if (((word >> 29) & 0x1) == 0) ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ xx000001101xxxxxxxxxxxxxxxx0xxxx ++ fmopa. */ ++ return 2356; ++ } ++ else ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ xx100001101xxxxxxxxxxxxxxxx0xxxx ++ umopa. */ ++ return 2368; ++ } + } + } + else + { +- /* 33222222222211111111110000000000 +- 10987654321098765432109876543210 +- xxx00001x11xxxxxxxxxxxxxxxx0xxxx +- umopa. */ +- return 2369; ++ if (((word >> 30) & 0x1) == 0) ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ x0x00001x11xxxxxxxxxxxxxxxx0xxxx ++ umopa. */ ++ return 2369; ++ } ++ else ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ x1x00001x11xxxxxxxxxxxxxxxx0xxxx ++ st1q. */ ++ return 2395; ++ } + } + } + } +@@ -2764,7 +2896,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 00011001000xxxxxxxxx00xxxxxxxxxx + stlurb. */ +- return 2421; ++ return 2443; + } + else + { +@@ -2772,7 +2904,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 10011001000xxxxxxxxx00xxxxxxxxxx + stlur. */ +- return 2429; ++ return 2451; + } + } + else +@@ -2783,7 +2915,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 01011001000xxxxxxxxx00xxxxxxxxxx + stlurh. */ +- return 2425; ++ return 2447; + } + else + { +@@ -2791,7 +2923,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 11011001000xxxxxxxxx00xxxxxxxxxx + stlur. */ +- return 2432; ++ return 2454; + } + } + } +@@ -2871,7 +3003,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 00011001010xxxxxxxxx00xxxxxxxxxx + ldapurb. */ +- return 2422; ++ return 2444; + } + else + { +@@ -2879,7 +3011,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 10011001010xxxxxxxxx00xxxxxxxxxx + ldapur. */ +- return 2430; ++ return 2452; + } + } + else +@@ -2890,7 +3022,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 01011001010xxxxxxxxx00xxxxxxxxxx + ldapurh. */ +- return 2426; ++ return 2448; + } + else + { +@@ -2898,7 +3030,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 11011001010xxxxxxxxx00xxxxxxxxxx + ldapur. */ +- return 2433; ++ return 2455; + } + } + } +@@ -2981,7 +3113,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 00011001100xxxxxxxxx00xxxxxxxxxx + ldapursb. */ +- return 2424; ++ return 2446; + } + else + { +@@ -2989,7 +3121,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 10011001100xxxxxxxxx00xxxxxxxxxx + ldapursw. */ +- return 2431; ++ return 2453; + } + } + else +@@ -2998,7 +3130,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1011001100xxxxxxxxx00xxxxxxxxxx + ldapursh. */ +- return 2428; ++ return 2450; + } + } + else +@@ -3009,7 +3141,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x0011001110xxxxxxxxx00xxxxxxxxxx + ldapursb. */ +- return 2423; ++ return 2445; + } + else + { +@@ -3017,7 +3149,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1011001110xxxxxxxxx00xxxxxxxxxx + ldapursh. */ +- return 2427; ++ return 2449; + } + } + } +@@ -3503,7 +3635,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xxx11010x00xxxxxx0xx10xxxxxxxxxx + setf8. */ +- return 2419; ++ return 2441; + } + else + { +@@ -3511,7 +3643,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xxx11010x00xxxxxx1xx10xxxxxxxxxx + setf16. */ +- return 2420; ++ return 2442; + } + } + else +@@ -3657,7 +3789,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xxx11010000xxxxxxxxx01xxxxxxxxxx + rmif. */ +- return 2418; ++ return 2440; + } + else + { +@@ -4706,7 +4838,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x01x1xxxxx000110xxxxxxxxxx + usdot. */ +- return 2438; ++ return 2460; + } + } + } +@@ -4780,7 +4912,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x01x1xxxxx000111xxxxxxxxxx + sudot. */ +- return 2439; ++ return 2461; + } + } + } +@@ -7399,7 +7531,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0xx0xxxxx011110xxxxxxxxxx + usdot. */ +- return 2437; ++ return 2459; + } + } + } +@@ -9103,7 +9235,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0100xxx10101xxxxxxxxxxxxx + bfcvtnt. */ +- return 2466; ++ return 2488; + } + } + else +@@ -9346,7 +9478,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x00x1xxxxxx00xxxxxxxxxxxxx + ld1rob. */ +- return 2442; ++ return 2464; + } + else + { +@@ -9354,7 +9486,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x01x1xxxxxx00xxxxxxxxxxxxx + ld1roh. */ +- return 2443; ++ return 2465; + } + } + else +@@ -9586,7 +9718,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0011xxxxx010xxxxxxxxxxxxx + bfdot. */ +- return 2463; ++ return 2485; + } + else + { +@@ -9607,7 +9739,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0111xxxxx010xx0xxxxxxxxxx + bfmlalb. */ +- return 2470; ++ return 2492; + } + else + { +@@ -9615,7 +9747,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0111xxxxx010xx1xxxxxxxxxx + bfmlalt. */ +- return 2469; ++ return 2491; + } + } + else +@@ -9670,7 +9802,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x11001x0011xxxxx1x0xxxxxxxxxxxxx + bfdot. */ +- return 2462; ++ return 2484; + } + else + { +@@ -9682,7 +9814,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0111xxxxx1x0xx0xxxxxxxxxx + bfmlalb. */ +- return 2468; ++ return 2490; + } + else + { +@@ -9690,7 +9822,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0111xxxxx1x0xx1xxxxxxxxxx + bfmlalt. */ +- return 2467; ++ return 2489; + } + } + else +@@ -9741,7 +9873,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x00x1xxxxx001xxxxxxxxxxxxx + ld1rob. */ +- return 2446; ++ return 2468; + } + else + { +@@ -9749,7 +9881,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x01x1xxxxx001xxxxxxxxxxxxx + ld1roh. */ +- return 2447; ++ return 2469; + } + } + else +@@ -10108,7 +10240,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0101xxxxx111xxxxxxxxxxxxx + fmmla. */ +- return 2440; ++ return 2462; + } + else + { +@@ -10141,7 +10273,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0011xxxxx111xxxxxxxxxxxxx + bfmmla. */ +- return 2464; ++ return 2486; + } + else + { +@@ -10171,7 +10303,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0111xxxxx111xxxxxxxxxxxxx + fmmla. */ +- return 2441; ++ return 2463; + } + else + { +@@ -10300,7 +10432,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1101xxxxx000x00xxxxxxxxxx + zip1. */ +- return 2450; ++ return 2472; + } + else + { +@@ -10310,7 +10442,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1101xxxxx000010xxxxxxxxxx + uzp1. */ +- return 2452; ++ return 2474; + } + else + { +@@ -10318,7 +10450,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1101xxxxx000110xxxxxxxxxx + trn1. */ +- return 2454; ++ return 2476; + } + } + } +@@ -10330,7 +10462,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1101xxxxx000x01xxxxxxxxxx + zip2. */ +- return 2451; ++ return 2473; + } + else + { +@@ -10340,7 +10472,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1101xxxxx000011xxxxxxxxxx + uzp2. */ +- return 2453; ++ return 2475; + } + else + { +@@ -10348,7 +10480,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1101xxxxx000111xxxxxxxxxx + trn2. */ +- return 2455; ++ return 2477; + } + } + } +@@ -11396,7 +11528,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1000xxxxx100110xxxxxxxxxx + smmla. */ +- return 2434; ++ return 2456; + } + else + { +@@ -11404,7 +11536,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1100xxxxx100110xxxxxxxxxx + usmmla. */ +- return 2436; ++ return 2458; + } + } + else +@@ -11413,7 +11545,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1x10xxxxx100110xxxxxxxxxx + ummla. */ +- return 2435; ++ return 2457; + } + } + } +@@ -12909,7 +13041,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x10x1xxxxx000xxxxxxxxxxxxx + ld1row. */ +- return 2444; ++ return 2466; + } + else + { +@@ -12917,7 +13049,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x11x1xxxxx000xxxxxxxxxxxxx + ld1rod. */ +- return 2445; ++ return 2467; + } + } + } +@@ -13291,7 +13423,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x10x1xxxxx001xxxxxxxxxxxxx + ld1row. */ +- return 2448; ++ return 2470; + } + else + { +@@ -13299,7 +13431,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x11x1xxxxx001xxxxxxxxxxxxx + ld1rod. */ +- return 2449; ++ return 2471; + } + } + } +@@ -14733,7 +14865,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x110001x10101xxxxxxxxxxxxx + bfcvt. */ +- return 2465; ++ return 2487; + } + } + else +@@ -16802,7 +16934,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 0x001110xx0xxxxx1x1001xxxxxxxxxx + smmla. */ +- return 2456; ++ return 2478; + } + } + } +@@ -16835,7 +16967,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 0x001110xx0xxxxx1x0101xxxxxxxxxx + sdot. */ +- return 2382; ++ return 2404; + } + } + else +@@ -16909,7 +17041,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 0x001110xx0xxxxx1x1011xxxxxxxxxx + usmmla. */ +- return 2458; ++ return 2480; + } + } + } +@@ -16942,7 +17074,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 0x001110xx0xxxxx1x0111xxxxxxxxxx + usdot. */ +- return 2459; ++ return 2481; + } + } + else +@@ -16989,7 +17121,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110000xxxxxxxxxxxxxxxxxxxxx + eor3. */ +- return 2389; ++ return 2411; + } + else + { +@@ -16997,7 +17129,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110100xxxxxxxxxxxxxxxxxxxxx + xar. */ +- return 2391; ++ return 2413; + } + } + else +@@ -17008,7 +17140,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110x10xxxxx0xxxxxxxxxxxxxxx + sm3ss1. */ +- return 2393; ++ return 2415; + } + else + { +@@ -17022,7 +17154,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110010xxxxx1xxx00xxxxxxxxxx + sm3tt1a. */ +- return 2394; ++ return 2416; + } + else + { +@@ -17030,7 +17162,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110110xxxxx1xxx00xxxxxxxxxx + sha512su0. */ +- return 2387; ++ return 2409; + } + } + else +@@ -17039,7 +17171,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110x10xxxxx1xxx10xxxxxxxxxx + sm3tt2a. */ +- return 2396; ++ return 2418; + } + } + else +@@ -17052,7 +17184,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110010xxxxx1xxx01xxxxxxxxxx + sm3tt1b. */ +- return 2395; ++ return 2417; + } + else + { +@@ -17060,7 +17192,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110110xxxxx1xxx01xxxxxxxxxx + sm4e. */ +- return 2400; ++ return 2422; + } + } + else +@@ -17069,7 +17201,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110x10xxxxx1xxx11xxxxxxxxxx + sm3tt2b. */ +- return 2397; ++ return 2419; + } + } + } +@@ -17250,7 +17382,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx101110xx0xxxxx100101xxxxxxxxxx + udot. */ +- return 2381; ++ return 2403; + } + } + else +@@ -17281,7 +17413,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx101110xx0xxxxx101x01xxxxxxxxxx + ummla. */ +- return 2457; ++ return 2479; + } + else + { +@@ -17300,7 +17432,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx101110xx0xxxxx1x1011xxxxxxxxxx + bfmmla. */ +- return 2473; ++ return 2495; + } + else + { +@@ -17310,7 +17442,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx1011100x0xxxxx1x1111xxxxxxxxxx + bfdot. */ +- return 2471; ++ return 2493; + } + else + { +@@ -17320,7 +17452,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x01011101x0xxxxx1x1111xxxxxxxxxx + bfmlalb. */ +- return 2478; ++ return 2500; + } + else + { +@@ -17328,7 +17460,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x11011101x0xxxxx1x1111xxxxxxxxxx + bfmlalt. */ +- return 2477; ++ return 2499; + } + } + } +@@ -17912,7 +18044,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000011101x1xxxx1011010xxxxxxxxxx + bfcvtn. */ +- return 2474; ++ return 2496; + } + else + { +@@ -17920,7 +18052,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010011101x1xxxx1011010xxxxxxxxxx + bfcvtn2. */ +- return 2475; ++ return 2497; + } + } + } +@@ -18238,7 +18370,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110xx1xxxxx0xxxxxxxxxxxxxxx + bcax. */ +- return 2392; ++ return 2414; + } + } + else +@@ -18849,7 +18981,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 11001110xx1xxxxx100000xxxxxxxxxx + sha512h. */ +- return 2385; ++ return 2407; + } + } + } +@@ -18901,7 +19033,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 11001110xx1xxxxx110000xxxxxxxxxx + sm3partw1. */ +- return 2398; ++ return 2420; + } + } + } +@@ -19144,7 +19276,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110xx1xxxxx100010xxxxxxxxxx + sha512su1. */ +- return 2388; ++ return 2410; + } + } + else +@@ -19220,7 +19352,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x0011100x1xxxxx110010xxxxxxxxxx + sm4ekey. */ +- return 2401; ++ return 2423; + } + } + else +@@ -20046,7 +20178,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110xx1xxxxx100001xxxxxxxxxx + sha512h2. */ +- return 2386; ++ return 2408; + } + } + else +@@ -20078,7 +20210,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x0011100x1xxxxx110001xxxxxxxxxx + sm3partw2. */ +- return 2399; ++ return 2421; + } + } + else +@@ -20318,7 +20450,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110xx1xxxxx100011xxxxxxxxxx + rax1. */ +- return 2390; ++ return 2412; + } + } + else +@@ -20350,7 +20482,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x01011100x1xxxxx110011xxxxxxxxxx + fmlal2. */ +- return 2404; ++ return 2426; + } + else + { +@@ -20358,7 +20490,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x11011100x1xxxxx110011xxxxxxxxxx + fmlal2. */ +- return 2408; ++ return 2430; + } + } + } +@@ -20380,7 +20512,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x01011101x1xxxxx110011xxxxxxxxxx + fmlsl2. */ +- return 2405; ++ return 2427; + } + else + { +@@ -20388,7 +20520,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x11011101x1xxxxx110011xxxxxxxxxx + fmlsl2. */ +- return 2409; ++ return 2431; + } + } + } +@@ -20427,7 +20559,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x00011100x1xxxxx111011xxxxxxxxxx + fmlal. */ +- return 2402; ++ return 2424; + } + else + { +@@ -20435,7 +20567,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x10011100x1xxxxx111011xxxxxxxxxx + fmlal. */ +- return 2406; ++ return 2428; + } + } + else +@@ -20457,7 +20589,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x00011101x1xxxxx111011xxxxxxxxxx + fmlsl. */ +- return 2403; ++ return 2425; + } + else + { +@@ -20465,7 +20597,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x10011101x1xxxxx111011xxxxxxxxxx + fmlsl. */ +- return 2407; ++ return 2429; + } + } + else +@@ -22273,7 +22405,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x0001111xxxxxxxx0000x0xxxxxxxxxx + fmlal. */ +- return 2410; ++ return 2432; + } + else + { +@@ -22281,7 +22413,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1001111xxxxxxxx0000x0xxxxxxxxxx + fmlal. */ +- return 2414; ++ return 2436; + } + } + else +@@ -22303,7 +22435,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x0001111xxxxxxxx0100x0xxxxxxxxxx + fmlsl. */ +- return 2411; ++ return 2433; + } + else + { +@@ -22311,7 +22443,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1001111xxxxxxxx0100x0xxxxxxxxxx + fmlsl. */ +- return 2415; ++ return 2437; + } + } + else +@@ -22817,7 +22949,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x0101111xxxxxxxx1000x0xxxxxxxxxx + fmlal2. */ +- return 2412; ++ return 2434; + } + else + { +@@ -22825,7 +22957,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1101111xxxxxxxx1000x0xxxxxxxxxx + fmlal2. */ +- return 2416; ++ return 2438; + } + } + } +@@ -22847,7 +22979,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x0101111xxxxxxxx1100x0xxxxxxxxxx + fmlsl2. */ +- return 2413; ++ return 2435; + } + else + { +@@ -22855,7 +22987,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1101111xxxxxxxx1100x0xxxxxxxxxx + fmlsl2. */ +- return 2417; ++ return 2439; + } + } + } +@@ -22911,7 +23043,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx001111xxxxxxxx1110x0xxxxxxxxxx + sdot. */ +- return 2384; ++ return 2406; + } + else + { +@@ -22919,7 +23051,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx101111xxxxxxxx1110x0xxxxxxxxxx + udot. */ +- return 2383; ++ return 2405; + } + } + } +@@ -23022,7 +23154,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx00111100xxxxxx1111x0xxxxxxxxxx + sudot. */ +- return 2461; ++ return 2483; + } + else + { +@@ -23030,7 +23162,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx00111110xxxxxx1111x0xxxxxxxxxx + usdot. */ +- return 2460; ++ return 2482; + } + } + else +@@ -23041,7 +23173,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx00111101xxxxxx1111x0xxxxxxxxxx + bfdot. */ +- return 2472; ++ return 2494; + } + else + { +@@ -23051,7 +23183,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x000111111xxxxxx1111x0xxxxxxxxxx + bfmlalb. */ +- return 2480; ++ return 2502; + } + else + { +@@ -23059,7 +23191,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x100111111xxxxxx1111x0xxxxxxxxxx + bfmlalt. */ +- return 2479; ++ return 2501; + } + } + } +@@ -23550,6 +23682,26 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode) + case 2379: return NULL; /* mova --> NULL. */ + case 2376: value = 2378; break; /* mov --> mova. */ + case 2378: return NULL; /* mova --> NULL. */ ++ case 2381: value = 2386; break; /* ld1b --> ld1b. */ ++ case 2386: return NULL; /* ld1b --> NULL. */ ++ case 2383: value = 2388; break; /* ld1w --> ld1w. */ ++ case 2388: return NULL; /* ld1w --> NULL. */ ++ case 2382: value = 2387; break; /* ld1h --> ld1h. */ ++ case 2387: return NULL; /* ld1h --> NULL. */ ++ case 2384: value = 2389; break; /* ld1d --> ld1d. */ ++ case 2389: return NULL; /* ld1d --> NULL. */ ++ case 2391: value = 2396; break; /* st1b --> st1b. */ ++ case 2396: return NULL; /* st1b --> NULL. */ ++ case 2393: value = 2398; break; /* st1w --> st1w. */ ++ case 2398: return NULL; /* st1w --> NULL. */ ++ case 2392: value = 2397; break; /* st1h --> st1h. */ ++ case 2397: return NULL; /* st1h --> NULL. */ ++ case 2394: value = 2399; break; /* st1d --> st1d. */ ++ case 2399: return NULL; /* st1d --> NULL. */ ++ case 2385: value = 2390; break; /* ld1q --> ld1q. */ ++ case 2390: return NULL; /* ld1q --> NULL. */ ++ case 2395: value = 2400; break; /* st1q --> st1q. */ ++ case 2400: return NULL; /* st1q --> NULL. */ + case 12: value = 19; break; /* add --> addg. */ + case 19: return NULL; /* addg --> NULL. */ + case 16: value = 20; break; /* sub --> subg. */ +@@ -23697,8 +23849,8 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode) + case 824: return NULL; /* fsqrt --> NULL. */ + case 832: value = 833; break; /* frintz --> frintz. */ + case 833: return NULL; /* frintz --> NULL. */ +- case 825: value = 2476; break; /* fcvt --> bfcvt. */ +- case 2476: return NULL; /* bfcvt --> NULL. */ ++ case 825: value = 2498; break; /* fcvt --> bfcvt. */ ++ case 2498: return NULL; /* bfcvt --> NULL. */ + case 834: value = 835; break; /* frinta --> frinta. */ + case 835: return NULL; /* frinta --> NULL. */ + case 836: value = 837; break; /* frintx --> frintx. */ +@@ -24178,7 +24330,6 @@ aarch64_extract_operand (const aarch64_operand *self, + case 29: + case 30: + case 31: +- case 166: + case 167: + case 168: + case 169: +@@ -24188,7 +24339,7 @@ aarch64_extract_operand (const aarch64_operand *self, + case 173: + case 174: + case 175: +- case 190: ++ case 176: + case 191: + case 192: + case 193: +@@ -24197,11 +24348,12 @@ aarch64_extract_operand (const aarch64_operand *self, + case 196: + case 197: + case 198: +- case 204: +- case 207: +- case 209: ++ case 199: ++ case 205: ++ case 208: + case 210: +- case 213: ++ case 211: ++ case 214: + return aarch64_ext_regno (self, info, code, inst, errors); + case 10: + return aarch64_ext_regrt_sysins (self, info, code, inst, errors); +@@ -24217,7 +24369,7 @@ aarch64_extract_operand (const aarch64_operand *self, + case 33: + case 34: + case 35: +- case 216: ++ case 220: + return aarch64_ext_reglane (self, info, code, inst, errors); + case 36: + return aarch64_ext_reglist (self, info, code, inst, errors); +@@ -24253,9 +24405,8 @@ aarch64_extract_operand (const aarch64_operand *self, + case 82: + case 83: + case 84: +- case 163: +- case 165: +- case 182: ++ case 164: ++ case 166: + case 183: + case 184: + case 185: +@@ -24263,8 +24414,9 @@ aarch64_extract_operand (const aarch64_operand *self, + case 187: + case 188: + case 189: +- case 214: ++ case 190: + case 215: ++ case 219: + return aarch64_ext_imm (self, info, code, inst, errors); + case 44: + case 45: +@@ -24276,10 +24428,10 @@ aarch64_extract_operand (const aarch64_operand *self, + case 49: + return aarch64_ext_shll_imm (self, info, code, inst, errors); + case 52: +- case 153: ++ case 154: + return aarch64_ext_fpimm (self, info, code, inst, errors); + case 70: +- case 161: ++ case 162: + return aarch64_ext_limm (self, info, code, inst, errors); + case 71: + return aarch64_ext_aimm (self, info, code, inst, errors); +@@ -24289,11 +24441,11 @@ aarch64_extract_operand (const aarch64_operand *self, + return aarch64_ext_fbits (self, info, code, inst, errors); + case 75: + case 76: +- case 158: ++ case 159: + return aarch64_ext_imm_rotate2 (self, info, code, inst, errors); + case 77: +- case 157: +- case 159: ++ case 158: ++ case 160: + return aarch64_ext_imm_rotate1 (self, info, code, inst, errors); + case 78: + case 79: +@@ -24369,8 +24521,8 @@ aarch64_extract_operand (const aarch64_operand *self, + case 133: + case 134: + case 135: +- return aarch64_ext_sve_addr_rr_lsl (self, info, code, inst, errors); + case 136: ++ return aarch64_ext_sve_addr_rr_lsl (self, info, code, inst, errors); + case 137: + case 138: + case 139: +@@ -24378,56 +24530,62 @@ aarch64_extract_operand (const aarch64_operand *self, + case 141: + case 142: + case 143: +- return aarch64_ext_sve_addr_rz_xtw (self, info, code, inst, errors); + case 144: ++ return aarch64_ext_sve_addr_rz_xtw (self, info, code, inst, errors); + case 145: + case 146: + case 147: +- return aarch64_ext_sve_addr_zi_u5 (self, info, code, inst, errors); + case 148: +- return aarch64_ext_sve_addr_zz_lsl (self, info, code, inst, errors); ++ return aarch64_ext_sve_addr_zi_u5 (self, info, code, inst, errors); + case 149: +- return aarch64_ext_sve_addr_zz_sxtw (self, info, code, inst, errors); ++ return aarch64_ext_sve_addr_zz_lsl (self, info, code, inst, errors); + case 150: +- return aarch64_ext_sve_addr_zz_uxtw (self, info, code, inst, errors); ++ return aarch64_ext_sve_addr_zz_sxtw (self, info, code, inst, errors); + case 151: +- return aarch64_ext_sve_aimm (self, info, code, inst, errors); ++ return aarch64_ext_sve_addr_zz_uxtw (self, info, code, inst, errors); + case 152: ++ return aarch64_ext_sve_aimm (self, info, code, inst, errors); ++ case 153: + return aarch64_ext_sve_asimm (self, info, code, inst, errors); +- case 154: +- return aarch64_ext_sve_float_half_one (self, info, code, inst, errors); + case 155: +- return aarch64_ext_sve_float_half_two (self, info, code, inst, errors); ++ return aarch64_ext_sve_float_half_one (self, info, code, inst, errors); + case 156: ++ return aarch64_ext_sve_float_half_two (self, info, code, inst, errors); ++ case 157: + return aarch64_ext_sve_float_zero_one (self, info, code, inst, errors); +- case 160: ++ case 161: + return aarch64_ext_inv_limm (self, info, code, inst, errors); +- case 162: ++ case 163: + return aarch64_ext_sve_limm_mov (self, info, code, inst, errors); +- case 164: ++ case 165: + return aarch64_ext_sve_scale (self, info, code, inst, errors); +- case 176: + case 177: + case 178: +- return aarch64_ext_sve_shlimm (self, info, code, inst, errors); + case 179: ++ return aarch64_ext_sve_shlimm (self, info, code, inst, errors); + case 180: + case 181: ++ case 182: + return aarch64_ext_sve_shrimm (self, info, code, inst, errors); +- case 199: + case 200: + case 201: + case 202: + case 203: ++ case 204: + return aarch64_ext_sve_quad_index (self, info, code, inst, errors); +- case 205: +- return aarch64_ext_sve_index (self, info, code, inst, errors); + case 206: +- case 208: ++ return aarch64_ext_sve_index (self, info, code, inst, errors); ++ case 207: ++ case 209: + return aarch64_ext_sve_reglist (self, info, code, inst, errors); +- case 211: + case 212: ++ case 213: ++ case 216: + return aarch64_ext_sme_za_hv_tiles (self, info, code, inst, errors); ++ case 217: ++ return aarch64_ext_sme_za_array (self, info, code, inst, errors); ++ case 218: ++ return aarch64_ext_sme_addr_ri_u4xvl (self, info, code, inst, errors); + default: assert (0); abort (); + } + } +diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c +index f4e7fe90..e8a0bd98 100644 +--- a/opcodes/aarch64-dis.c ++++ b/opcodes/aarch64-dis.c +@@ -1805,6 +1805,56 @@ aarch64_ext_sme_za_hv_tiles (const aarch64_operand *self, + return true; + } + ++/* Decode in SME instruction ZERO list of up to eight 64-bit element tile names ++ separated by commas, encoded in the "imm8" field. ++ ++ For programmer convenience an assembler must also accept the names of ++ 32-bit, 16-bit and 8-bit element tiles which are converted into the ++ corresponding set of 64-bit element tiles. ++*/ ++bool ++aarch64_ext_sme_za_list (const aarch64_operand *self, ++ aarch64_opnd_info *info, aarch64_insn code, ++ const aarch64_inst *inst ATTRIBUTE_UNUSED, ++ aarch64_operand_error *errors ATTRIBUTE_UNUSED) ++{ ++ int mask = extract_field (self->fields[0], code, 0); ++ info->imm.value = mask; ++ return true; ++} ++ ++/* Decode ZA array vector select register (Rv field), optional vector and ++ memory offset (imm4 field). ++*/ ++bool ++aarch64_ext_sme_za_array (const aarch64_operand *self, ++ aarch64_opnd_info *info, aarch64_insn code, ++ const aarch64_inst *inst ATTRIBUTE_UNUSED, ++ aarch64_operand_error *errors ATTRIBUTE_UNUSED) ++{ ++ int regno = extract_field (self->fields[0], code, 0) + 12; ++ int imm = extract_field (self->fields[1], code, 0); ++ info->za_tile_vector.index.regno = regno; ++ info->za_tile_vector.index.imm = imm; ++ return true; ++} ++ ++bool ++aarch64_ext_sme_addr_ri_u4xvl (const aarch64_operand *self, ++ aarch64_opnd_info *info, aarch64_insn code, ++ const aarch64_inst *inst ATTRIBUTE_UNUSED, ++ aarch64_operand_error *errors ATTRIBUTE_UNUSED) ++{ ++ int regno = extract_field (self->fields[0], code, 0); ++ int imm = extract_field (self->fields[1], code, 0); ++ info->addr.base_regno = regno; ++ info->addr.offset.imm = imm; ++ /* MUL VL operator is always present for this operand. */ ++ info->shifter.kind = AARCH64_MOD_MUL_VL; ++ info->shifter.operator_present = (imm != 0); ++ return true; ++} ++ + /* Decode Zn[MM], where MM has a 7-bit triangular encoding. The fields + array specifies which field to use for Zn. MM is encoded in the + concatenation of imm5 and SVE_tszh, with imm5 being the less +diff --git a/opcodes/aarch64-dis.h b/opcodes/aarch64-dis.h +index 842ec554..893800b2 100644 +--- a/opcodes/aarch64-dis.h ++++ b/opcodes/aarch64-dis.h +@@ -123,6 +123,9 @@ AARCH64_DECL_OPD_EXTRACTOR (ext_sve_scale); + AARCH64_DECL_OPD_EXTRACTOR (ext_sve_shlimm); + AARCH64_DECL_OPD_EXTRACTOR (ext_sve_shrimm); + AARCH64_DECL_OPD_EXTRACTOR (ext_sme_za_hv_tiles); ++AARCH64_DECL_OPD_EXTRACTOR (ext_sme_za_list); ++AARCH64_DECL_OPD_EXTRACTOR (ext_sme_za_array); ++AARCH64_DECL_OPD_EXTRACTOR (ext_sme_addr_ri_u4xvl); + AARCH64_DECL_OPD_EXTRACTOR (ext_imm_rotate1); + AARCH64_DECL_OPD_EXTRACTOR (ext_imm_rotate2); + +diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c +index 10880a0b..5dedf211 100644 +--- a/opcodes/aarch64-opc-2.c ++++ b/opcodes/aarch64-opc-2.c +@@ -151,6 +151,7 @@ const struct aarch64_operand aarch64_operands[] = + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR_LSL1", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"}, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR_LSL2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"}, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR_LSL3", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"}, ++ {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR_LSL4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"}, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX", (0 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"}, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX_LSL1", (1 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"}, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX_LSL2", (2 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"}, +@@ -239,6 +240,9 @@ const struct aarch64_operand aarch64_operands[] = + {AARCH64_OPND_CLASS_SVE_REG, "SME_ZA_HV_idx_dest", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_10,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_2}, "an SME horizontal or vertical vector access register"}, + {AARCH64_OPND_CLASS_PRED_REG, "SME_Pm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Pm}, "an SVE predicate register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_list_of_64bit_tiles", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_zero_mask}, "list of 64-bit ZA element tiles"}, ++ {AARCH64_OPND_CLASS_SVE_REG, "SME_ZA_HV_idx_ldstr", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_10,FLD_index2,FLD_SME_V,FLD_SME_Rv,FLD_imm4_2}, "an SME horizontal or vertical vector access register"}, ++ {AARCH64_OPND_CLASS_SVE_REG, "SME_ZA_array", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rv,FLD_imm4_2}, "ZA array"}, ++ {AARCH64_OPND_CLASS_ADDRESS, "SME_ADDR_RI_U4xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm4_2}, "memory offset"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "TME_UIMM16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16}, "a 16-bit unsigned immediate for TME tcancel"}, + {AARCH64_OPND_CLASS_SIMD_ELEMENT, "SM3_IMM2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SM3_imm2}, "an indexed SM3 vector immediate"}, + {AARCH64_OPND_CLASS_NIL, "", 0, {0}, "DUMMY"}, +diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c +index 9f32eb55..e46763d7 100644 +--- a/opcodes/aarch64-opc.c ++++ b/opcodes/aarch64-opc.c +@@ -197,6 +197,8 @@ aarch64_select_operand_for_sizeq_field_coding (const aarch64_opcode *opcode) + significant_operand_index [get_data_pattern (opcode->qualifiers_list[0])]; + } + ++/* Instruction bit-fields. +++ Keep synced with 'enum aarch64_field_kind'. */ + const aarch64_field fields[] = + { + { 0, 0 }, /* NIL. */ +@@ -1835,6 +1837,14 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, + } + break; + ++ case AARCH64_OPND_SME_ADDR_RI_U4xVL: ++ if (!value_in_range_p (opnd->addr.offset.imm, 0, 15)) ++ { ++ set_offset_out_of_range_error (mismatch_detail, idx, 0, 15); ++ return 0; ++ } ++ break; ++ + case AARCH64_OPND_SVE_ADDR_RI_S4xVL: + case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL: + case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL: +@@ -1932,6 +1942,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, + case AARCH64_OPND_SVE_ADDR_RR_LSL1: + case AARCH64_OPND_SVE_ADDR_RR_LSL2: + case AARCH64_OPND_SVE_ADDR_RR_LSL3: ++ case AARCH64_OPND_SVE_ADDR_RR_LSL4: + case AARCH64_OPND_SVE_ADDR_RX: + case AARCH64_OPND_SVE_ADDR_RX_LSL1: + case AARCH64_OPND_SVE_ADDR_RX_LSL2: +@@ -2750,21 +2761,51 @@ aarch64_match_operands_constraint (aarch64_inst *inst, + + DEBUG_TRACE ("enter"); + +- /* Check for cases where a source register needs to be the same as the +- destination register. Do this before matching qualifiers since if +- an instruction has both invalid tying and invalid qualifiers, +- the error about qualifiers would suggest several alternative +- instructions that also have invalid tying. */ + i = inst->opcode->tied_operand; +- if (i > 0 && (inst->operands[0].reg.regno != inst->operands[i].reg.regno)) ++ ++ if (i > 0) + { +- if (mismatch_detail) +- { +- mismatch_detail->kind = AARCH64_OPDE_UNTIED_OPERAND; +- mismatch_detail->index = i; +- mismatch_detail->error = NULL; +- } +- return 0; ++ /* Check for tied_operands with specific opcode iclass. */ ++ switch (inst->opcode->iclass) ++ { ++ /* For SME LDR and STR instructions #imm must have the same numerical ++ value for both operands. ++ */ ++ case sme_ldr: ++ case sme_str: ++ assert (inst->operands[0].type == AARCH64_OPND_SME_ZA_array); ++ assert (inst->operands[1].type == AARCH64_OPND_SME_ADDR_RI_U4xVL); ++ if (inst->operands[0].za_tile_vector.index.imm ++ != inst->operands[1].addr.offset.imm) ++ { ++ if (mismatch_detail) ++ { ++ mismatch_detail->kind = AARCH64_OPDE_UNTIED_IMMS; ++ mismatch_detail->index = i; ++ } ++ return 0; ++ } ++ break; ++ ++ default: ++ /* Check for cases where a source register needs to be the same as the ++ destination register. Do this before matching qualifiers since if ++ an instruction has both invalid tying and invalid qualifiers, ++ the error about qualifiers would suggest several alternative ++ instructions that also have invalid tying. */ ++ if (inst->operands[0].reg.regno ++ != inst->operands[i].reg.regno) ++ { ++ if (mismatch_detail) ++ { ++ mismatch_detail->kind = AARCH64_OPDE_UNTIED_OPERAND; ++ mismatch_detail->index = i; ++ mismatch_detail->error = NULL; ++ } ++ return 0; ++ } ++ break; ++ } + } + + /* Match operands' qualifier. +@@ -3403,18 +3444,27 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, + + case AARCH64_OPND_SME_ZA_HV_idx_src: + case AARCH64_OPND_SME_ZA_HV_idx_dest: +- snprintf (buf, size, "za%d%c.%s[w%d, %d]", ++ case AARCH64_OPND_SME_ZA_HV_idx_ldstr: ++ snprintf (buf, size, "%sza%d%c.%s[w%d, %d]%s", ++ opnd->type == AARCH64_OPND_SME_ZA_HV_idx_ldstr ? "{" : "", + opnd->za_tile_vector.regno, + opnd->za_tile_vector.v == 1 ? 'v' : 'h', + aarch64_get_qualifier_name (opnd->qualifier), + opnd->za_tile_vector.index.regno, +- opnd->za_tile_vector.index.imm); ++ opnd->za_tile_vector.index.imm, ++ opnd->type == AARCH64_OPND_SME_ZA_HV_idx_ldstr ? "}" : ""); + break; + + case AARCH64_OPND_SME_list_of_64bit_tiles: + print_sme_za_list (buf, size, opnd->reg.regno); + break; + ++ case AARCH64_OPND_SME_ZA_array: ++ snprintf (buf, size, "za[w%d, %d]", ++ opnd->za_tile_vector.index.regno, ++ opnd->za_tile_vector.index.imm); ++ break; ++ + case AARCH64_OPND_CRn: + case AARCH64_OPND_CRm: + snprintf (buf, size, "C%" PRIi64, opnd->imm.value); +@@ -3678,6 +3728,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, + case AARCH64_OPND_SVE_ADDR_RR_LSL1: + case AARCH64_OPND_SVE_ADDR_RR_LSL2: + case AARCH64_OPND_SVE_ADDR_RR_LSL3: ++ case AARCH64_OPND_SVE_ADDR_RR_LSL4: + case AARCH64_OPND_SVE_ADDR_RX: + case AARCH64_OPND_SVE_ADDR_RX_LSL1: + case AARCH64_OPND_SVE_ADDR_RX_LSL2: +@@ -3718,6 +3769,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, + case AARCH64_OPND_ADDR_SIMM11: + case AARCH64_OPND_ADDR_SIMM13: + case AARCH64_OPND_ADDR_OFFSET: ++ case AARCH64_OPND_SME_ADDR_RI_U4xVL: + case AARCH64_OPND_SVE_ADDR_RI_S4x16: + case AARCH64_OPND_SVE_ADDR_RI_S4x32: + case AARCH64_OPND_SVE_ADDR_RI_S4xVL: +diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h +index 93132206..d74009be 100644 +--- a/opcodes/aarch64-tbl.h ++++ b/opcodes/aarch64-tbl.h +@@ -1557,6 +1557,10 @@ + { \ + QLF3(S_D,NIL,NIL), \ + } ++#define OP_SVE_QUU \ ++{ \ ++ QLF3(S_Q,NIL,NIL), \ ++} + #define OP_SVE_DUV_BHS \ + { \ + QLF3(S_D,NIL,S_B), \ +@@ -1578,6 +1582,10 @@ + { \ + QLF3(S_D,P_Z,NIL), \ + } ++#define OP_SVE_QZU \ ++{ \ ++ QLF3(S_Q,P_Z,NIL), \ ++} + #define OP_SVE_HB \ + { \ + QLF2(S_H,S_B), \ +@@ -5138,6 +5146,33 @@ const struct aarch64_opcode aarch64_opcode_table[] = + + SME_INSN ("zero", 0xc0080000, 0xffffff00, sme_misc, 0, OP1 (SME_list_of_64bit_tiles), {}, 0, 0), + ++ SME_INSN ("ld1b", 0xe0000000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_RR), OP_SVE_BZU, 0, 0), ++ SME_INSN ("ld1h", 0xe0400000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_RR_LSL1), OP_SVE_HZU, 0, 0), ++ SME_INSN ("ld1w", 0xe0800000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_RR_LSL2), OP_SVE_SZU, 0, 0), ++ SME_INSN ("ld1d", 0xe0c00000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_RR_LSL3), OP_SVE_DZU, 0, 0), ++ SME_INSN ("ld1q", 0xe1c00000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QZU, 0, 0), ++ ++ SME_INSN ("ld1b", 0xe0000000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_R), OP_SVE_BZU, 0, 0), ++ SME_INSN ("ld1h", 0xe0400000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_R), OP_SVE_HZU, 0, 0), ++ SME_INSN ("ld1w", 0xe0800000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_R), OP_SVE_SZU, 0, 0), ++ SME_INSN ("ld1d", 0xe0c00000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_R), OP_SVE_DZU, 0, 0), ++ SME_INSN ("ld1q", 0xe1c00000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_R), OP_SVE_QZU, 0, 0), ++ ++ SME_INSN ("st1b", 0xe0200000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_RR), OP_SVE_BUU, 0, 0), ++ SME_INSN ("st1h", 0xe0600000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_RR_LSL1), OP_SVE_HUU, 0, 0), ++ SME_INSN ("st1w", 0xe0a00000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0), ++ SME_INSN ("st1d", 0xe0e00000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_RR_LSL3), OP_SVE_DUU, 0, 0), ++ SME_INSN ("st1q", 0xe1e00000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QUU, 0, 0), ++ ++ SME_INSN ("st1b", 0xe0200000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_R), OP_SVE_BUU, 0, 0), ++ SME_INSN ("st1h", 0xe0600000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_R), OP_SVE_HUU, 0, 0), ++ SME_INSN ("st1w", 0xe0a00000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_R), OP_SVE_SUU, 0, 0), ++ SME_INSN ("st1d", 0xe0e00000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_R), OP_SVE_DUU, 0, 0), ++ SME_INSN ("st1q", 0xe1e00000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_R), OP_SVE_QUU, 0, 0), ++ ++ SME_INSN ("ldr", 0xe1000000, 0xffff9c10, sme_ldr, 0, OP2 (SME_ZA_array, SME_ADDR_RI_U4xVL), {}, 0, 1), ++ SME_INSN ("str", 0xe1200000, 0xffff9c10, sme_str, 0, OP2 (SME_ZA_array, SME_ADDR_RI_U4xVL), {}, 0, 1), ++ + /* SIMD Dot Product (optional in v8.2-A). */ + DOT_INSN ("udot", 0x2e009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ), + DOT_INSN ("sdot", 0xe009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ), +@@ -5512,6 +5547,8 @@ const struct aarch64_opcode aarch64_opcode_table[] = + F(FLD_Rn,FLD_Rm), "an address with a scalar register offset") \ + Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RR_LSL3", 3 << OPD_F_OD_LSB, \ + F(FLD_Rn,FLD_Rm), "an address with a scalar register offset") \ ++ Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RR_LSL4", 4 << OPD_F_OD_LSB, \ ++ F(FLD_Rn,FLD_Rm), "an address with a scalar register offset") \ + Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RX", \ + (0 << OPD_F_OD_LSB) | OPD_F_NO_ZR, F(FLD_Rn,FLD_Rm), \ + "an address with a scalar register offset") \ +@@ -5719,6 +5756,15 @@ const struct aarch64_opcode aarch64_opcode_table[] = + "an SVE predicate register") \ + Y(SVE_REG, imm, "SME_list_of_64bit_tiles", 0, \ + F(FLD_SME_zero_mask), "list of 64-bit ZA element tiles") \ ++ Y(SVE_REG, sme_za_hv_tiles, "SME_ZA_HV_idx_ldstr", 0, \ ++ F(FLD_SME_size_10,FLD_index2,FLD_SME_V,FLD_SME_Rv,FLD_imm4_2), \ ++ "an SME horizontal or vertical vector access register") \ ++ Y(SVE_REG, sme_za_array, "SME_ZA_array", 0, \ ++ F(FLD_SME_Rv,FLD_imm4_2), \ ++ "ZA array") \ ++ Y(ADDRESS, sme_addr_ri_u4xvl, "SME_ADDR_RI_U4xVL", 0 << OPD_F_OD_LSB, \ ++ F(FLD_Rn,FLD_imm4_2), \ ++ "memory offset") \ + Y(IMMEDIATE, imm, "TME_UIMM16", 0, F(FLD_imm16), \ + "a 16-bit unsigned immediate for TME tcancel") \ + Y(SIMD_ELEMENT, reglane, "SM3_IMM2", 0, F(FLD_SM3_imm2), \ +-- +2.19.1 + diff --git a/SME-0006-aarch64-SME-Add-SME-mode-selection-and-state-access-.patch b/SME-0006-aarch64-SME-Add-SME-mode-selection-and-state-access-.patch new file mode 100644 index 0000000000000000000000000000000000000000..ab30f45afd963ab8c2f87fa738885612d121d614 --- /dev/null +++ b/SME-0006-aarch64-SME-Add-SME-mode-selection-and-state-access-.patch @@ -0,0 +1,12003 @@ +From 0c6c053b3f2a4ac2f938c41a314a1a44a1a88893 Mon Sep 17 00:00:00 2001 +From: Przemyslaw Wirkus +Date: Wed, 17 Nov 2021 20:15:13 +0000 +Subject: [PATCH 06/10] aarch64: [SME] Add SME mode selection and state access + instructions + +Reference: https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=3dd032c5fb4eb7fc6bc0341d348da5c75e2d8e38 + +This patch is adding new SME mode selection and state access instructions: +* Add SMSTART and SMSTOP instructions. +* Add SVCR system register. + +gas/ChangeLog: + + * config/tc-aarch64.c (parse_sme_sm_za): New parser. + (parse_operands): New parser. + * testsuite/gas/aarch64/sme-8-illegal.d: New test. + * testsuite/gas/aarch64/sme-8-illegal.l: New test. + * testsuite/gas/aarch64/sme-8-illegal.s: New test. + * testsuite/gas/aarch64/sme-8.d: New test. + * testsuite/gas/aarch64/sme-8.s: New test. + +include/ChangeLog: + + * opcode/aarch64.h (enum aarch64_opnd): New operand + AARCH64_OPND_SME_SM_ZA. + (enum aarch64_insn_class): New instruction classes + sme_start and sme_stop. + +opcodes/ChangeLog: + + * aarch64-asm.c (aarch64_ins_pstatefield): New inserter. + (aarch64_ins_sme_sm_za): New inserter. + * aarch64-dis.c (aarch64_ext_imm): New extractor. + (aarch64_ext_pstatefield): New extractor. + (aarch64_ext_sme_sm_za): New extractor. + * aarch64-opc.c (operand_general_constraint_met_p): + New pstatefield value for SME instructions. + (aarch64_print_operand): Printout for OPND_SME_SM_ZA. + (SR_SME): New register SVCR. + * aarch64-opc.h (F_REG_IN_CRM): New register endcoding. + * aarch64-opc.h (F_IMM_IN_CRM): New immediate endcoding. + (PSTATE_ENCODE_CRM): Encode CRm field. + (PSTATE_DECODE_CRM): Decode CRm field. + (PSTATE_ENCODE_CRM_IMM): Encode CRm immediate field. + (PSTATE_DECODE_CRM_IMM): Decode CRm immediate field. + (PSTATE_ENCODE_CRM_AND_IMM): Encode CRm and immediate + field. + * aarch64-tbl.h (struct aarch64_opcode): New SMSTART + and SMSTOP instructions. + aarch64-asm-2.c: Regenerate. + aarch64-dis-2.c: Regenerate. + aarch64-opc-2.c: Regenerate. +--- + gas/config/tc-aarch64.c | 56 +- + gas/testsuite/gas/aarch64/sme-8-illegal.d | 3 + + gas/testsuite/gas/aarch64/sme-8-illegal.l | 7 + + gas/testsuite/gas/aarch64/sme-8-illegal.s | 9 + + gas/testsuite/gas/aarch64/sme-8.d | 27 + + gas/testsuite/gas/aarch64/sme-8.s | 28 + + include/opcode/aarch64.h | 3 + + opcodes/aarch64-asm-2.c | 300 +-- + opcodes/aarch64-asm.c | 25 + + opcodes/aarch64-asm.h | 1 + + opcodes/aarch64-dis-2.c | 2706 +++++++++++---------- + opcodes/aarch64-dis.c | 38 +- + opcodes/aarch64-dis.h | 1 + + opcodes/aarch64-opc-2.c | 19 +- + opcodes/aarch64-opc.c | 31 +- + opcodes/aarch64-opc.h | 26 + + opcodes/aarch64-tbl.h | 8 + + 17 files changed, 1766 insertions(+), 1522 deletions(-) + create mode 100644 gas/testsuite/gas/aarch64/sme-8-illegal.d + create mode 100644 gas/testsuite/gas/aarch64/sme-8-illegal.l + create mode 100644 gas/testsuite/gas/aarch64/sme-8-illegal.s + create mode 100644 gas/testsuite/gas/aarch64/sme-8.d + create mode 100644 gas/testsuite/gas/aarch64/sme-8.s + +diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c +index 3f6a181b..069fe14e 100644 +--- a/gas/config/tc-aarch64.c ++++ b/gas/config/tc-aarch64.c +@@ -4677,6 +4677,32 @@ parse_sme_za_array (char **str, int *imm) + return regno; + } + ++/* Parse streaming mode operand for SMSTART and SMSTOP. ++ ++ {SM | ZA} ++ ++ Function returns 's' if SM or 'z' if ZM is parsed. Otherwise PARSE_FAIL. ++*/ ++static int ++parse_sme_sm_za (char **str) ++{ ++ char *p, *q; ++ ++ p = q = *str; ++ while (ISALPHA (*q)) ++ q++; ++ ++ if ((q - p != 2) ++ || (strncasecmp ("sm", p, 2) != 0 && strncasecmp ("za", p, 2) != 0)) ++ { ++ set_syntax_error (_("expected SM or ZA operand")); ++ return PARSE_FAIL; ++ } ++ ++ *str = q; ++ return TOLOWER (p[0]); ++} ++ + /* Parse a system register or a PSTATE field name for an MSR/MRS instruction. + Returns the encoding for the option, or PARSE_FAIL. + +@@ -7080,6 +7106,16 @@ parse_operands (char *str, const aarch64_opcode *opcode) + /* No qualifier. */ + break; + ++ case AARCH64_OPND_SME_SM_ZA: ++ /* { SM | ZA } */ ++ if ((val = parse_sme_sm_za (&str)) == PARSE_FAIL) ++ { ++ set_syntax_error (_("unknown or missing PSTATE field name")); ++ goto failure; ++ } ++ info->reg.regno = val; ++ break; ++ + case AARCH64_OPND_SVE_ADDR_RI_S4x16: + case AARCH64_OPND_SVE_ADDR_RI_S4x32: + case AARCH64_OPND_SVE_ADDR_RI_S4xVL: +@@ -7269,14 +7305,18 @@ parse_operands (char *str, const aarch64_opcode *opcode) + } + + case AARCH64_OPND_PSTATEFIELD: +- if ((val = parse_sys_reg (&str, aarch64_pstatefield_hsh, 0, 1, NULL)) +- == PARSE_FAIL) +- { +- set_syntax_error (_("unknown or missing PSTATE field name")); +- goto failure; +- } +- inst.base.operands[i].pstatefield = val; +- break; ++ { ++ uint32_t sysreg_flags; ++ if ((val = parse_sys_reg (&str, aarch64_pstatefield_hsh, 0, 1, ++ &sysreg_flags)) == PARSE_FAIL) ++ { ++ set_syntax_error (_("unknown or missing PSTATE field name")); ++ goto failure; ++ } ++ inst.base.operands[i].pstatefield = val; ++ inst.base.operands[i].sysreg.flags = sysreg_flags; ++ break; ++ } + + case AARCH64_OPND_SYSREG_IC: + inst.base.operands[i].sysins_op = +diff --git a/gas/testsuite/gas/aarch64/sme-8-illegal.d b/gas/testsuite/gas/aarch64/sme-8-illegal.d +new file mode 100644 +index 00000000..1b3c3bc4 +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/sme-8-illegal.d +@@ -0,0 +1,3 @@ ++#as: -march=armv8-a+sme ++#source: sme-8-illegal.s ++#error_output: sme-8-illegal.l +diff --git a/gas/testsuite/gas/aarch64/sme-8-illegal.l b/gas/testsuite/gas/aarch64/sme-8-illegal.l +new file mode 100644 +index 00000000..ee9f76f3 +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/sme-8-illegal.l +@@ -0,0 +1,7 @@ ++[^:]*: Assembler messages: ++[^:]*:[0-9]+: Error: unexpected characters following instruction -- `smstart x0' ++[^:]*:[0-9]+: Error: unexpected characters following instruction -- `smstart sa' ++[^:]*:[0-9]+: Error: unexpected characters following instruction -- `smstart zm' ++[^:]*:[0-9]+: Error: unexpected characters following instruction -- `smstop x0' ++[^:]*:[0-9]+: Error: unexpected characters following instruction -- `smstop sa' ++[^:]*:[0-9]+: Error: unexpected characters following instruction -- `smstop zm' +diff --git a/gas/testsuite/gas/aarch64/sme-8-illegal.s b/gas/testsuite/gas/aarch64/sme-8-illegal.s +new file mode 100644 +index 00000000..a0e20223 +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/sme-8-illegal.s +@@ -0,0 +1,9 @@ ++/* Scalable Matrix Extension (SME). */ ++ ++smstart x0 ++smstart sa ++smstart zm ++ ++smstop x0 ++smstop sa ++smstop zm +diff --git a/gas/testsuite/gas/aarch64/sme-8.d b/gas/testsuite/gas/aarch64/sme-8.d +new file mode 100644 +index 00000000..c956baa6 +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/sme-8.d +@@ -0,0 +1,27 @@ ++#name: SME mode selection and state access instructions ++#as: -march=armv8-a+sme ++#objdump: -dr ++ ++.*: file format .* ++ ++Disassembly of section \.text: ++ ++0+ <.*>: ++ 0: d53b4240 mrs x0, svcr ++ 4: d51b4240 msr svcr, x0 ++ 8: d503427f smstop sm ++ c: d503447f smstop za ++ 10: d503467f smstop ++ 14: d503437f smstart sm ++ 18: d503457f smstart za ++ 1c: d503477f smstart ++ 20: d503477f smstart ++ 24: d503437f smstart sm ++ 28: d503457f smstart za ++ 2c: d503437f smstart sm ++ 30: d503457f smstart za ++ 34: d503467f smstop ++ 38: d503427f smstop sm ++ 3c: d503447f smstop za ++ 40: d503427f smstop sm ++ 44: d503447f smstop za +diff --git a/gas/testsuite/gas/aarch64/sme-8.s b/gas/testsuite/gas/aarch64/sme-8.s +new file mode 100644 +index 00000000..d4a07530 +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/sme-8.s +@@ -0,0 +1,28 @@ ++/* SME mode selection and state access instructions. */ ++ ++/* SVCR system register access. */ ++mrs x0, svcr ++msr svcr, x0 ++ ++/* MSR SVCR Immediate access. */ ++msr svcrsm, #0 ++msr svcrza, #0 ++msr svcrsmza, #0 ++ ++msr svcrsm, #1 ++msr svcrza, #1 ++msr svcrsmza, #1 ++ ++/* SMSTART. */ ++smstart ++smstart sm ++smstart za ++smstart SM ++smstart ZA ++ ++/* SMSTOP. */ ++smstop ++smstop sm ++smstop za ++smstop SM ++smstop ZA +diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h +index 3a4d5e0a..9a3ec903 100644 +--- a/include/opcode/aarch64.h ++++ b/include/opcode/aarch64.h +@@ -449,6 +449,7 @@ enum aarch64_opnd + AARCH64_OPND_SME_ZA_HV_idx_ldstr, /* SME destination ZA tile vector. */ + AARCH64_OPND_SME_ZA_array, /* SME ZA[{, #}]. */ + AARCH64_OPND_SME_ADDR_RI_U4xVL, /* SME [{, #, MUL VL}]. */ ++ AARCH64_OPND_SME_SM_ZA, /* SME {SM | ZA}. */ + AARCH64_OPND_TME_UIMM16, /* TME unsigned 16-bit immediate. */ + AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */ + }; +@@ -616,6 +617,8 @@ enum aarch64_insn_class + sme_misc, + sme_ldr, + sme_str, ++ sme_start, ++ sme_stop, + sve_cpy, + sve_index, + sve_limm, +diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c +index 54ec35aa..8b226b10 100644 +--- a/opcodes/aarch64-asm-2.c ++++ b/opcodes/aarch64-asm-2.c +@@ -426,176 +426,176 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode) + case 1188: /* movz */ + value = 1188; /* --> movz. */ + break; +- case 1246: /* autibsp */ +- case 1245: /* autibz */ +- case 1244: /* autiasp */ +- case 1243: /* autiaz */ +- case 1242: /* pacibsp */ +- case 1241: /* pacibz */ +- case 1240: /* paciasp */ +- case 1239: /* paciaz */ +- case 1215: /* tsb */ +- case 1214: /* psb */ +- case 1213: /* esb */ +- case 1212: /* autib1716 */ +- case 1211: /* autia1716 */ +- case 1210: /* pacib1716 */ +- case 1209: /* pacia1716 */ +- case 1208: /* xpaclri */ +- case 1206: /* sevl */ +- case 1205: /* sev */ +- case 1204: /* wfi */ +- case 1203: /* wfe */ +- case 1202: /* yield */ +- case 1201: /* bti */ +- case 1200: /* csdb */ +- case 1199: /* nop */ +- case 1198: /* hint */ +- value = 1198; /* --> hint. */ +- break; +- case 1221: /* pssbb */ +- case 1220: /* ssbb */ +- case 1219: /* dfb */ +- case 1217: /* dsb */ +- value = 1217; /* --> dsb. */ +- break; +- case 1218: /* dsb */ +- value = 1218; /* --> dsb. */ +- break; +- case 1234: /* cpp */ +- case 1233: /* dvp */ +- case 1232: /* cfp */ +- case 1229: /* tlbi */ +- case 1228: /* ic */ +- case 1227: /* dc */ +- case 1226: /* at */ +- case 1225: /* sys */ +- value = 1225; /* --> sys. */ +- break; +- case 1230: /* wfet */ +- value = 1230; /* --> wfet. */ +- break; +- case 1231: /* wfit */ +- value = 1231; /* --> wfit. */ +- break; +- case 2044: /* bic */ +- case 1294: /* and */ +- value = 1294; /* --> and. */ ++ case 1250: /* autibsp */ ++ case 1249: /* autibz */ ++ case 1248: /* autiasp */ ++ case 1247: /* autiaz */ ++ case 1246: /* pacibsp */ ++ case 1245: /* pacibz */ ++ case 1244: /* paciasp */ ++ case 1243: /* paciaz */ ++ case 1219: /* tsb */ ++ case 1218: /* psb */ ++ case 1217: /* esb */ ++ case 1216: /* autib1716 */ ++ case 1215: /* autia1716 */ ++ case 1214: /* pacib1716 */ ++ case 1213: /* pacia1716 */ ++ case 1212: /* xpaclri */ ++ case 1210: /* sevl */ ++ case 1209: /* sev */ ++ case 1208: /* wfi */ ++ case 1207: /* wfe */ ++ case 1206: /* yield */ ++ case 1205: /* bti */ ++ case 1204: /* csdb */ ++ case 1203: /* nop */ ++ case 1202: /* hint */ ++ value = 1202; /* --> hint. */ ++ break; ++ case 1225: /* pssbb */ ++ case 1224: /* ssbb */ ++ case 1223: /* dfb */ ++ case 1221: /* dsb */ ++ value = 1221; /* --> dsb. */ ++ break; ++ case 1222: /* dsb */ ++ value = 1222; /* --> dsb. */ ++ break; ++ case 1238: /* cpp */ ++ case 1237: /* dvp */ ++ case 1236: /* cfp */ ++ case 1233: /* tlbi */ ++ case 1232: /* ic */ ++ case 1231: /* dc */ ++ case 1230: /* at */ ++ case 1229: /* sys */ ++ value = 1229; /* --> sys. */ ++ break; ++ case 1234: /* wfet */ ++ value = 1234; /* --> wfet. */ ++ break; ++ case 1235: /* wfit */ ++ value = 1235; /* --> wfit. */ ++ break; ++ case 2048: /* bic */ ++ case 1298: /* and */ ++ value = 1298; /* --> and. */ ++ break; ++ case 1281: /* mov */ ++ case 1300: /* and */ ++ value = 1300; /* --> and. */ ++ break; ++ case 1285: /* movs */ ++ case 1301: /* ands */ ++ value = 1301; /* --> ands. */ ++ break; ++ case 2049: /* cmple */ ++ case 1336: /* cmpge */ ++ value = 1336; /* --> cmpge. */ ++ break; ++ case 2052: /* cmplt */ ++ case 1339: /* cmpgt */ ++ value = 1339; /* --> cmpgt. */ ++ break; ++ case 2050: /* cmplo */ ++ case 1341: /* cmphi */ ++ value = 1341; /* --> cmphi. */ ++ break; ++ case 2051: /* cmpls */ ++ case 1344: /* cmphs */ ++ value = 1344; /* --> cmphs. */ + break; +- case 1277: /* mov */ +- case 1296: /* and */ +- value = 1296; /* --> and. */ +- break; +- case 1281: /* movs */ +- case 1297: /* ands */ +- value = 1297; /* --> ands. */ ++ case 1278: /* mov */ ++ case 1366: /* cpy */ ++ value = 1366; /* --> cpy. */ + break; +- case 2045: /* cmple */ +- case 1332: /* cmpge */ +- value = 1332; /* --> cmpge. */ ++ case 1280: /* mov */ ++ case 1367: /* cpy */ ++ value = 1367; /* --> cpy. */ + break; +- case 2048: /* cmplt */ +- case 1335: /* cmpgt */ +- value = 1335; /* --> cmpgt. */ ++ case 2059: /* fmov */ ++ case 1283: /* mov */ ++ case 1368: /* cpy */ ++ value = 1368; /* --> cpy. */ + break; +- case 2046: /* cmplo */ +- case 1337: /* cmphi */ +- value = 1337; /* --> cmphi. */ ++ case 1273: /* mov */ ++ case 1380: /* dup */ ++ value = 1380; /* --> dup. */ + break; +- case 2047: /* cmpls */ +- case 1340: /* cmphs */ +- value = 1340; /* --> cmphs. */ ++ case 1275: /* mov */ ++ case 1272: /* mov */ ++ case 1381: /* dup */ ++ value = 1381; /* --> dup. */ + break; +- case 1274: /* mov */ +- case 1362: /* cpy */ +- value = 1362; /* --> cpy. */ ++ case 2058: /* fmov */ ++ case 1277: /* mov */ ++ case 1382: /* dup */ ++ value = 1382; /* --> dup. */ + break; + case 1276: /* mov */ +- case 1363: /* cpy */ +- value = 1363; /* --> cpy. */ +- break; +- case 2055: /* fmov */ +- case 1279: /* mov */ +- case 1364: /* cpy */ +- value = 1364; /* --> cpy. */ +- break; +- case 1269: /* mov */ +- case 1376: /* dup */ +- value = 1376; /* --> dup. */ +- break; +- case 1271: /* mov */ +- case 1268: /* mov */ +- case 1377: /* dup */ +- value = 1377; /* --> dup. */ ++ case 1383: /* dupm */ ++ value = 1383; /* --> dupm. */ + break; +- case 2054: /* fmov */ +- case 1273: /* mov */ +- case 1378: /* dup */ +- value = 1378; /* --> dup. */ +- break; +- case 1272: /* mov */ +- case 1379: /* dupm */ +- value = 1379; /* --> dupm. */ +- break; +- case 2049: /* eon */ +- case 1381: /* eor */ +- value = 1381; /* --> eor. */ ++ case 2053: /* eon */ ++ case 1385: /* eor */ ++ value = 1385; /* --> eor. */ + break; +- case 1282: /* not */ +- case 1383: /* eor */ +- value = 1383; /* --> eor. */ ++ case 1286: /* not */ ++ case 1387: /* eor */ ++ value = 1387; /* --> eor. */ + break; +- case 1283: /* nots */ +- case 1384: /* eors */ +- value = 1384; /* --> eors. */ ++ case 1287: /* nots */ ++ case 1388: /* eors */ ++ value = 1388; /* --> eors. */ + break; +- case 2050: /* facle */ +- case 1389: /* facge */ +- value = 1389; /* --> facge. */ ++ case 2054: /* facle */ ++ case 1393: /* facge */ ++ value = 1393; /* --> facge. */ + break; +- case 2051: /* faclt */ +- case 1390: /* facgt */ +- value = 1390; /* --> facgt. */ ++ case 2055: /* faclt */ ++ case 1394: /* facgt */ ++ value = 1394; /* --> facgt. */ + break; +- case 2052: /* fcmle */ +- case 1403: /* fcmge */ +- value = 1403; /* --> fcmge. */ ++ case 2056: /* fcmle */ ++ case 1407: /* fcmge */ ++ value = 1407; /* --> fcmge. */ + break; +- case 2053: /* fcmlt */ +- case 1405: /* fcmgt */ +- value = 1405; /* --> fcmgt. */ ++ case 2057: /* fcmlt */ ++ case 1409: /* fcmgt */ ++ value = 1409; /* --> fcmgt. */ + break; +- case 1266: /* fmov */ +- case 1411: /* fcpy */ +- value = 1411; /* --> fcpy. */ ++ case 1270: /* fmov */ ++ case 1415: /* fcpy */ ++ value = 1415; /* --> fcpy. */ + break; +- case 1265: /* fmov */ +- case 1434: /* fdup */ +- value = 1434; /* --> fdup. */ ++ case 1269: /* fmov */ ++ case 1438: /* fdup */ ++ value = 1438; /* --> fdup. */ + break; +- case 1267: /* mov */ +- case 1765: /* orr */ +- value = 1765; /* --> orr. */ ++ case 1271: /* mov */ ++ case 1769: /* orr */ ++ value = 1769; /* --> orr. */ + break; +- case 2056: /* orn */ +- case 1766: /* orr */ +- value = 1766; /* --> orr. */ ++ case 2060: /* orn */ ++ case 1770: /* orr */ ++ value = 1770; /* --> orr. */ + break; +- case 1270: /* mov */ +- case 1768: /* orr */ +- value = 1768; /* --> orr. */ ++ case 1274: /* mov */ ++ case 1772: /* orr */ ++ value = 1772; /* --> orr. */ + break; +- case 1280: /* movs */ +- case 1769: /* orrs */ +- value = 1769; /* --> orrs. */ ++ case 1284: /* movs */ ++ case 1773: /* orrs */ ++ value = 1773; /* --> orrs. */ + break; +- case 1275: /* mov */ +- case 1831: /* sel */ +- value = 1831; /* --> sel. */ ++ case 1279: /* mov */ ++ case 1835: /* sel */ ++ value = 1835; /* --> sel. */ + break; +- case 1278: /* mov */ +- case 1832: /* sel */ +- value = 1832; /* --> sel. */ ++ case 1282: /* mov */ ++ case 1836: /* sel */ ++ value = 1836; /* --> sel. */ + break; + default: return NULL; + } +@@ -675,7 +675,7 @@ aarch64_insert_operand (const aarch64_operand *self, + case 33: + case 34: + case 35: +- case 220: ++ case 221: + return aarch64_ins_reglane (self, info, code, inst, errors); + case 36: + return aarch64_ins_reglist (self, info, code, inst, errors); +@@ -721,7 +721,7 @@ aarch64_insert_operand (const aarch64_operand *self, + case 189: + case 190: + case 215: +- case 219: ++ case 220: + return aarch64_ins_imm (self, info, code, inst, errors); + case 44: + case 45: +@@ -889,6 +889,8 @@ aarch64_insert_operand (const aarch64_operand *self, + return aarch64_ins_sme_za_array (self, info, code, inst, errors); + case 218: + return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors); ++ case 219: ++ return aarch64_ins_sme_sm_za (self, info, code, inst, errors); + default: assert (0); abort (); + } + } +diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c +index a2b0e864..b9aff950 100644 +--- a/opcodes/aarch64-asm.c ++++ b/opcodes/aarch64-asm.c +@@ -848,6 +848,10 @@ aarch64_ins_pstatefield (const aarch64_operand *self ATTRIBUTE_UNUSED, + /* op1:op2 */ + insert_fields (code, info->pstatefield, inst->opcode->mask, 2, + FLD_op2, FLD_op1); ++ ++ /* Extra CRm mask. */ ++ if (info->sysreg.flags | F_REG_IN_CRM) ++ insert_field (FLD_CRm, code, PSTATE_DECODE_CRM (info->sysreg.flags), 0); + return true; + } + +@@ -1427,6 +1431,27 @@ aarch64_ins_sme_addr_ri_u4xvl (const aarch64_operand *self, + return true; + } + ++/* Encode in SMSTART and SMSTOP {SM | ZA } mode. */ ++bool ++aarch64_ins_sme_sm_za (const aarch64_operand *self, ++ const aarch64_opnd_info *info, ++ aarch64_insn *code, ++ const aarch64_inst *inst ATTRIBUTE_UNUSED, ++ aarch64_operand_error *errors ATTRIBUTE_UNUSED) ++{ ++ aarch64_insn fld_crm; ++ /* Set CRm[3:1] bits. */ ++ if (info->reg.regno == 's') ++ fld_crm = 0x02 ; /* SVCRSM. */ ++ else if (info->reg.regno == 'z') ++ fld_crm = 0x04; /* SVCRZA. */ ++ else ++ assert (0); ++ ++ insert_field (self->fields[0], code, fld_crm, 0); ++ return true; ++} ++ + /* Miscellaneous encoding functions. */ + + /* Encode size[0], i.e. bit 22, for +diff --git a/opcodes/aarch64-asm.h b/opcodes/aarch64-asm.h +index 1f9e85c2..cb224f68 100644 +--- a/opcodes/aarch64-asm.h ++++ b/opcodes/aarch64-asm.h +@@ -102,6 +102,7 @@ AARCH64_DECL_OPD_INSERTER (ins_sme_za_hv_tiles); + AARCH64_DECL_OPD_INSERTER (ins_sme_za_list); + AARCH64_DECL_OPD_INSERTER (ins_sme_za_array); + AARCH64_DECL_OPD_INSERTER (ins_sme_addr_ri_u4xvl); ++AARCH64_DECL_OPD_INSERTER (ins_sme_sm_za); + AARCH64_DECL_OPD_INSERTER (ins_imm_rotate1); + AARCH64_DECL_OPD_INSERTER (ins_imm_rotate2); + +diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c +index 5ce26ddc..8d759bc3 100644 +--- a/opcodes/aarch64-dis-2.c ++++ b/opcodes/aarch64-dis-2.c +@@ -60,7 +60,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x0000000100xxxxxxxxxxxxxxxx0xxxx + fmopa. */ +- return 2354; ++ return 2358; + } + else + { +@@ -68,7 +68,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x0000000100xxxxxxxxxxxxxxxx1xxxx + fmops. */ +- return 2357; ++ return 2361; + } + } + } +@@ -80,7 +80,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x0000000x10xxxxxxxxxxxxxxxx0xxxx + fmopa. */ +- return 2355; ++ return 2359; + } + else + { +@@ -88,7 +88,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x0000000x10xxxxxxxxxxxxxxxx1xxxx + fmops. */ +- return 2358; ++ return 2362; + } + } + } +@@ -104,7 +104,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1000000xx000x0xxxxxxxxxxxxxxxxx + mov. */ +- return 2377; ++ return 2381; + } + else + { +@@ -116,7 +116,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1000000x0010x00xxxxxxxxxxxxxxxx + addha. */ +- return 2348; ++ return 2352; + } + else + { +@@ -124,7 +124,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1000000x1010x00xxxxxxxxxxxxxxxx + addha. */ +- return 2349; ++ return 2353; + } + } + else +@@ -135,7 +135,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1000000x0010x01xxxxxxxxxxxxxxxx + addva. */ +- return 2350; ++ return 2354; + } + else + { +@@ -143,7 +143,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1000000x1010x01xxxxxxxxxxxxxxxx + addva. */ +- return 2351; ++ return 2355; + } + } + } +@@ -154,7 +154,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1000000xx0x1x0xxxxxxxxxxxxxxxxx + zero. */ +- return 2380; ++ return 2384; + } + } + else +@@ -163,7 +163,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1000000xx0xxx1xxxxxxxxxxxxxxxxx + mov. */ +- return 2376; ++ return 2380; + } + } + } +@@ -179,7 +179,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx100000000xxxxxxxxxxxxxxxx0xxxx + ld1b. */ +- return 2381; ++ return 2385; + } + else + { +@@ -189,7 +189,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x0100000100xxxxxxxxxxxxxxxx0xxxx + smopa. */ +- return 2360; ++ return 2364; + } + else + { +@@ -197,7 +197,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1100000100xxxxxxxxxxxxxxxx0xxxx + ld1w. */ +- return 2383; ++ return 2387; + } + } + } +@@ -209,7 +209,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx100000010xxxxxxxxxxxxxxxx0xxxx + ld1h. */ +- return 2382; ++ return 2386; + } + else + { +@@ -219,7 +219,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x0100000110xxxxxxxxxxxxxxxx0xxxx + smopa. */ +- return 2361; ++ return 2365; + } + else + { +@@ -227,7 +227,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1100000110xxxxxxxxxxxxxxxx0xxxx + ld1d. */ +- return 2384; ++ return 2388; + } + } + } +@@ -240,7 +240,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx100000x00xxxxxxxxxxxxxxxx1xxxx + smops. */ +- return 2362; ++ return 2366; + } + else + { +@@ -248,7 +248,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx100000x10xxxxxxxxxxxxxxxx1xxxx + smops. */ +- return 2363; ++ return 2367; + } + } + } +@@ -265,7 +265,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xxx00000001xxxxxxxxxxxxxxxx0xxxx + st1b. */ +- return 2391; ++ return 2395; + } + else + { +@@ -275,7 +275,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x0x00000101xxxxxxxxxxxxxxxx0xxxx + sumopa. */ +- return 2364; ++ return 2368; + } + else + { +@@ -283,7 +283,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1x00000101xxxxxxxxxxxxxxxx0xxxx + st1w. */ +- return 2393; ++ return 2397; + } + } + } +@@ -295,7 +295,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xxx00000011xxxxxxxxxxxxxxxx0xxxx + st1h. */ +- return 2392; ++ return 2396; + } + else + { +@@ -305,7 +305,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x0x00000111xxxxxxxxxxxxxxxx0xxxx + sumopa. */ +- return 2365; ++ return 2369; + } + else + { +@@ -313,7 +313,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1x00000111xxxxxxxxxxxxxxxx0xxxx + st1d. */ +- return 2394; ++ return 2398; + } + } + } +@@ -326,7 +326,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xxx00000x01xxxxxxxxxxxxxxxx1xxxx + sumops. */ +- return 2366; ++ return 2370; + } + else + { +@@ -334,7 +334,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xxx00000x11xxxxxxxxxxxxxxxx1xxxx + sumops. */ +- return 2367; ++ return 2371; + } + } + } +@@ -375,7 +375,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xxx00001000xxxxxxxxxxxxxxxx0xxxx + ldr. */ +- return 2401; ++ return 2405; + } + else + { +@@ -385,7 +385,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx000001100xxxxxxxxxxxxxxxx0xxxx + bfmopa. */ +- return 2352; ++ return 2356; + } + else + { +@@ -393,7 +393,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx100001100xxxxxxxxxxxxxxxx0xxxx + usmopa. */ +- return 2372; ++ return 2376; + } + } + } +@@ -405,7 +405,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x0x00001x10xxxxxxxxxxxxxxxx0xxxx + usmopa. */ +- return 2373; ++ return 2377; + } + else + { +@@ -413,7 +413,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1x00001x10xxxxxxxxxxxxxxxx0xxxx + ld1q. */ +- return 2385; ++ return 2389; + } + } + } +@@ -427,7 +427,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xxx00001001xxxxxxxxxxxxxxxx0xxxx + str. */ +- return 2402; ++ return 2406; + } + else + { +@@ -437,7 +437,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx000001101xxxxxxxxxxxxxxxx0xxxx + fmopa. */ +- return 2356; ++ return 2360; + } + else + { +@@ -445,7 +445,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx100001101xxxxxxxxxxxxxxxx0xxxx + umopa. */ +- return 2368; ++ return 2372; + } + } + } +@@ -457,7 +457,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x0x00001x11xxxxxxxxxxxxxxxx0xxxx + umopa. */ +- return 2369; ++ return 2373; + } + else + { +@@ -465,7 +465,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1x00001x11xxxxxxxxxxxxxxxx0xxxx + st1q. */ +- return 2395; ++ return 2399; + } + } + } +@@ -482,7 +482,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx000001x00xxxxxxxxxxxxxxxx1xxxx + bfmops. */ +- return 2353; ++ return 2357; + } + else + { +@@ -490,7 +490,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx100001x00xxxxxxxxxxxxxxxx1xxxx + usmops. */ +- return 2374; ++ return 2378; + } + } + else +@@ -499,7 +499,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xxx00001x10xxxxxxxxxxxxxxxx1xxxx + usmops. */ +- return 2375; ++ return 2379; + } + } + else +@@ -512,7 +512,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx000001x01xxxxxxxxxxxxxxxx1xxxx + fmops. */ +- return 2359; ++ return 2363; + } + else + { +@@ -520,7 +520,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx100001x01xxxxxxxxxxxxxxxx1xxxx + umops. */ +- return 2370; ++ return 2374; + } + } + else +@@ -529,7 +529,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xxx00001x11xxxxxxxxxxxxxxxx1xxxx + umops. */ +- return 2371; ++ return 2375; + } + } + } +@@ -2896,7 +2896,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 00011001000xxxxxxxxx00xxxxxxxxxx + stlurb. */ +- return 2443; ++ return 2447; + } + else + { +@@ -2904,7 +2904,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 10011001000xxxxxxxxx00xxxxxxxxxx + stlur. */ +- return 2451; ++ return 2455; + } + } + else +@@ -2915,7 +2915,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 01011001000xxxxxxxxx00xxxxxxxxxx + stlurh. */ +- return 2447; ++ return 2451; + } + else + { +@@ -2923,7 +2923,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 11011001000xxxxxxxxx00xxxxxxxxxx + stlur. */ +- return 2454; ++ return 2458; + } + } + } +@@ -3003,7 +3003,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 00011001010xxxxxxxxx00xxxxxxxxxx + ldapurb. */ +- return 2444; ++ return 2448; + } + else + { +@@ -3011,7 +3011,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 10011001010xxxxxxxxx00xxxxxxxxxx + ldapur. */ +- return 2452; ++ return 2456; + } + } + else +@@ -3022,7 +3022,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 01011001010xxxxxxxxx00xxxxxxxxxx + ldapurh. */ +- return 2448; ++ return 2452; + } + else + { +@@ -3030,7 +3030,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 11011001010xxxxxxxxx00xxxxxxxxxx + ldapur. */ +- return 2455; ++ return 2459; + } + } + } +@@ -3113,7 +3113,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 00011001100xxxxxxxxx00xxxxxxxxxx + ldapursb. */ +- return 2446; ++ return 2450; + } + else + { +@@ -3121,7 +3121,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 10011001100xxxxxxxxx00xxxxxxxxxx + ldapursw. */ +- return 2453; ++ return 2457; + } + } + else +@@ -3130,7 +3130,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1011001100xxxxxxxxx00xxxxxxxxxx + ldapursh. */ +- return 2450; ++ return 2454; + } + } + else +@@ -3141,7 +3141,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x0011001110xxxxxxxxx00xxxxxxxxxx + ldapursb. */ +- return 2445; ++ return 2449; + } + else + { +@@ -3149,7 +3149,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1011001110xxxxxxxxx00xxxxxxxxxx + ldapursh. */ +- return 2449; ++ return 2453; + } + } + } +@@ -3635,7 +3635,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xxx11010x00xxxxxx0xx10xxxxxxxxxx + setf8. */ +- return 2441; ++ return 2445; + } + else + { +@@ -3643,7 +3643,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xxx11010x00xxxxxx1xx10xxxxxxxxxx + setf16. */ +- return 2442; ++ return 2446; + } + } + else +@@ -3789,7 +3789,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xxx11010000xxxxxxxxx01xxxxxxxxxx + rmif. */ +- return 2440; ++ return 2444; + } + else + { +@@ -4327,7 +4327,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx000000000xxxxxxxxxxxxx + add. */ +- return 1287; ++ return 1291; + } + else + { +@@ -4335,7 +4335,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx010000000xxxxxxxxxxxxx + mul. */ +- return 1756; ++ return 1760; + } + } + else +@@ -4346,7 +4346,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx001000000xxxxxxxxxxxxx + smax. */ +- return 1835; ++ return 1839; + } + else + { +@@ -4354,7 +4354,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx011000000xxxxxxxxxxxxx + orr. */ +- return 1767; ++ return 1771; + } + } + } +@@ -4366,7 +4366,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx0x0100000xxxxxxxxxxxxx + sdiv. */ +- return 1826; ++ return 1830; + } + else + { +@@ -4374,7 +4374,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx0x1100000xxxxxxxxxxxxx + sabd. */ +- return 1817; ++ return 1821; + } + } + } +@@ -4388,7 +4388,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx0x0010000xxxxxxxxxxxxx + smulh. */ +- return 1840; ++ return 1844; + } + else + { +@@ -4398,7 +4398,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx001010000xxxxxxxxxxxxx + smin. */ +- return 1838; ++ return 1842; + } + else + { +@@ -4406,7 +4406,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx011010000xxxxxxxxxxxxx + and. */ +- return 1295; ++ return 1299; + } + } + } +@@ -4416,7 +4416,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx0xx110000xxxxxxxxxxxxx + sdivr. */ +- return 1827; ++ return 1831; + } + } + } +@@ -4432,7 +4432,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx0x0001000xxxxxxxxxxxxx + sub. */ +- return 1956; ++ return 1960; + } + else + { +@@ -4442,7 +4442,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx001001000xxxxxxxxxxxxx + umax. */ +- return 1984; ++ return 1988; + } + else + { +@@ -4450,7 +4450,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx011001000xxxxxxxxxxxxx + eor. */ +- return 1382; ++ return 1386; + } + } + } +@@ -4462,7 +4462,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx0x0101000xxxxxxxxxxxxx + udiv. */ +- return 1978; ++ return 1982; + } + else + { +@@ -4470,7 +4470,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx0x1101000xxxxxxxxxxxxx + uabd. */ +- return 1969; ++ return 1973; + } + } + } +@@ -4486,7 +4486,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx000011000xxxxxxxxxxxxx + subr. */ +- return 1958; ++ return 1962; + } + else + { +@@ -4494,7 +4494,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx010011000xxxxxxxxxxxxx + umulh. */ +- return 1989; ++ return 1993; + } + } + else +@@ -4505,7 +4505,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx001011000xxxxxxxxxxxxx + umin. */ +- return 1987; ++ return 1991; + } + else + { +@@ -4513,7 +4513,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx011011000xxxxxxxxxxxxx + bic. */ +- return 1307; ++ return 1311; + } + } + } +@@ -4523,7 +4523,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx0xx111000xxxxxxxxxxxxx + udivr. */ +- return 1979; ++ return 1983; + } + } + } +@@ -4536,7 +4536,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x00x0xxxxx000xxxxxxxxxxxxx + ld1sb. */ +- return 1569; ++ return 1573; + } + else + { +@@ -4544,7 +4544,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x01x0xxxxx000xxxxxxxxxxxxx + ld1sh. */ +- return 1580; ++ return 1584; + } + } + } +@@ -4562,7 +4562,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0xx0xxxxx000000xxxxxxxxxx + sdot. */ +- return 1828; ++ return 1832; + } + else + { +@@ -4570,7 +4570,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0xx0xxxxx000010xxxxxxxxxx + sqdmlalbt. */ +- return 2178; ++ return 2182; + } + } + else +@@ -4581,7 +4581,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0xx0xxxxx000001xxxxxxxxxx + udot. */ +- return 1980; ++ return 1984; + } + else + { +@@ -4589,7 +4589,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0xx0xxxxx000011xxxxxxxxxx + sqdmlslbt. */ +- return 2185; ++ return 2189; + } + } + } +@@ -4599,7 +4599,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0xx0xxxxx0001xxxxxxxxxxxx + cdot. */ +- return 2067; ++ return 2071; + } + } + else +@@ -4610,7 +4610,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 110001x00x0xxxxx000xxxxxxxxxxxxx + ld1sb. */ +- return 1573; ++ return 1577; + } + else + { +@@ -4618,7 +4618,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 110001x01x0xxxxx000xxxxxxxxxxxxx + ld1sh. */ +- return 1584; ++ return 1588; + } + } + } +@@ -4639,7 +4639,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx1xxxxx000000xxxxxxxxxx + add. */ +- return 1285; ++ return 1289; + } + else + { +@@ -4647,7 +4647,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx1xxxxx000100xxxxxxxxxx + sqadd. */ +- return 1842; ++ return 1846; + } + } + else +@@ -4656,7 +4656,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx1xxxxx000x10xxxxxxxxxx + sqsub. */ +- return 1872; ++ return 1876; + } + } + else +@@ -4669,7 +4669,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx1xxxxx000001xxxxxxxxxx + sub. */ +- return 1954; ++ return 1958; + } + else + { +@@ -4677,7 +4677,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx1xxxxx000101xxxxxxxxxx + uqadd. */ +- return 1990; ++ return 1994; + } + } + else +@@ -4686,7 +4686,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx1xxxxx000x11xxxxxxxxxx + uqsub. */ +- return 2020; ++ return 2024; + } + } + } +@@ -4698,7 +4698,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x00x1xxxxx000xxxxxxxxxxxxx + prfb. */ +- return 1775; ++ return 1779; + } + else + { +@@ -4706,7 +4706,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x01x1xxxxx000xxxxxxxxxxxxx + ld1sh. */ +- return 1581; ++ return 1585; + } + } + } +@@ -4724,7 +4724,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x00x1xxxxx000x00xxxxxxxxxx + sqrdmlah. */ +- return 2203; ++ return 2207; + } + else + { +@@ -4732,7 +4732,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x00x1xxxxx000x10xxxxxxxxxx + mla. */ +- return 2110; ++ return 2114; + } + } + else +@@ -4743,7 +4743,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x00x1xxxxx000x01xxxxxxxxxx + sqrdmlsh. */ +- return 2207; ++ return 2211; + } + else + { +@@ -4751,7 +4751,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x00x1xxxxx000x11xxxxxxxxxx + mls. */ +- return 2113; ++ return 2117; + } + } + } +@@ -4761,7 +4761,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 110001x00x1xxxxx000xxxxxxxxxxxxx + prfb. */ +- return 1776; ++ return 1780; + } + } + else +@@ -4780,7 +4780,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0101xxxxx000000xxxxxxxxxx + sdot. */ +- return 1829; ++ return 1833; + } + else + { +@@ -4788,7 +4788,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0111xxxxx000000xxxxxxxxxx + sdot. */ +- return 1830; ++ return 1834; + } + } + else +@@ -4799,7 +4799,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0101xxxxx000100xxxxxxxxxx + sqrdmlah. */ +- return 2204; ++ return 2208; + } + else + { +@@ -4807,7 +4807,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0111xxxxx000100xxxxxxxxxx + sqrdmlah. */ +- return 2205; ++ return 2209; + } + } + } +@@ -4821,7 +4821,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0101xxxxx000010xxxxxxxxxx + mla. */ +- return 2111; ++ return 2115; + } + else + { +@@ -4829,7 +4829,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0111xxxxx000010xxxxxxxxxx + mla. */ +- return 2112; ++ return 2116; + } + } + else +@@ -4838,7 +4838,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x01x1xxxxx000110xxxxxxxxxx + usdot. */ +- return 2460; ++ return 2464; + } + } + } +@@ -4854,7 +4854,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0101xxxxx000001xxxxxxxxxx + udot. */ +- return 1981; ++ return 1985; + } + else + { +@@ -4862,7 +4862,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0111xxxxx000001xxxxxxxxxx + udot. */ +- return 1982; ++ return 1986; + } + } + else +@@ -4873,7 +4873,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0101xxxxx000101xxxxxxxxxx + sqrdmlsh. */ +- return 2208; ++ return 2212; + } + else + { +@@ -4881,7 +4881,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0111xxxxx000101xxxxxxxxxx + sqrdmlsh. */ +- return 2209; ++ return 2213; + } + } + } +@@ -4895,7 +4895,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0101xxxxx000011xxxxxxxxxx + mls. */ +- return 2114; ++ return 2118; + } + else + { +@@ -4903,7 +4903,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0111xxxxx000011xxxxxxxxxx + mls. */ +- return 2115; ++ return 2119; + } + } + else +@@ -4912,7 +4912,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x01x1xxxxx000111xxxxxxxxxx + sudot. */ +- return 2461; ++ return 2465; + } + } + } +@@ -4923,7 +4923,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 110001x01x1xxxxx000xxxxxxxxxxxxx + ld1sh. */ +- return 1585; ++ return 1589; + } + } + } +@@ -4949,7 +4949,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 0x0001x0xx000000100xxxxxxxxxxxxx + asr. */ +- return 1303; ++ return 1307; + } + else + { +@@ -4959,7 +4959,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx010000100xxxxxxxxxxxxx + asr. */ +- return 1301; ++ return 1305; + } + else + { +@@ -4967,7 +4967,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0xx010000100xxxxxxxxxxxxx + shadd. */ +- return 2144; ++ return 2148; + } + } + } +@@ -4979,7 +4979,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 0x0001x0xx001000100xxxxxxxxxxxxx + sqshl. */ +- return 2222; ++ return 2226; + } + else + { +@@ -4989,7 +4989,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx011000100xxxxxxxxxxxxx + asr. */ +- return 1302; ++ return 1306; + } + else + { +@@ -4997,7 +4997,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0xx011000100xxxxxxxxxxxxx + sqadd. */ +- return 2173; ++ return 2177; + } + } + } +@@ -5012,7 +5012,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 0x0001x0xx000100100xxxxxxxxxxxxx + asrd. */ +- return 1304; ++ return 1308; + } + else + { +@@ -5022,7 +5022,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx010100100xxxxxxxxxxxxx + asrr. */ +- return 1305; ++ return 1309; + } + else + { +@@ -5030,7 +5030,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0xx010100100xxxxxxxxxxxxx + srhadd. */ +- return 2235; ++ return 2239; + } + } + } +@@ -5044,7 +5044,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx001100100xxxxxxxxxxxxx + srshr. */ +- return 2239; ++ return 2243; + } + else + { +@@ -5052,7 +5052,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0xx001100100xxxxxxxxxxxxx + sqshlr. */ +- return 2223; ++ return 2227; + } + } + else +@@ -5061,7 +5061,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 0x0001x0xx011100100xxxxxxxxxxxxx + suqadd. */ +- return 2259; ++ return 2263; + } + } + } +@@ -5078,7 +5078,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 0x0001x0xx000010100xxxxxxxxxxxxx + srshl. */ +- return 2237; ++ return 2241; + } + else + { +@@ -5086,7 +5086,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 0x0001x0xx010010100xxxxxxxxxxxxx + shsub. */ +- return 2147; ++ return 2151; + } + } + else +@@ -5097,7 +5097,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 0x0001x0xx001010100xxxxxxxxxxxxx + sqrshl. */ +- return 2215; ++ return 2219; + } + else + { +@@ -5105,7 +5105,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 0x0001x0xx011010100xxxxxxxxxxxxx + sqsub. */ +- return 2229; ++ return 2233; + } + } + } +@@ -5121,7 +5121,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx000110100xxxxxxxxxxxxx + sqshl. */ +- return 2221; ++ return 2225; + } + else + { +@@ -5129,7 +5129,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0xx000110100xxxxxxxxxxxxx + srshlr. */ +- return 2238; ++ return 2242; + } + } + else +@@ -5138,7 +5138,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 0x0001x0xx010110100xxxxxxxxxxxxx + shsubr. */ +- return 2148; ++ return 2152; + } + } + else +@@ -5149,7 +5149,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 0x0001x0xx001110100xxxxxxxxxxxxx + sqrshlr. */ +- return 2216; ++ return 2220; + } + else + { +@@ -5157,7 +5157,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 0x0001x0xx011110100xxxxxxxxxxxxx + sqsubr. */ +- return 2230; ++ return 2234; + } + } + } +@@ -5177,7 +5177,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 0x0001x0xx000001100xxxxxxxxxxxxx + lsr. */ +- return 1747; ++ return 1751; + } + else + { +@@ -5187,7 +5187,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx010001100xxxxxxxxxxxxx + lsr. */ +- return 1745; ++ return 1749; + } + else + { +@@ -5195,7 +5195,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0xx010001100xxxxxxxxxxxxx + uhadd. */ +- return 2272; ++ return 2276; + } + } + } +@@ -5207,7 +5207,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 0x0001x0xx001001100xxxxxxxxxxxxx + uqshl. */ +- return 2302; ++ return 2306; + } + else + { +@@ -5217,7 +5217,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx011001100xxxxxxxxxxxxx + lsr. */ +- return 1746; ++ return 1750; + } + else + { +@@ -5225,7 +5225,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0xx011001100xxxxxxxxxxxxx + uqadd. */ +- return 2296; ++ return 2300; + } + } + } +@@ -5240,7 +5240,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx0x0101100xxxxxxxxxxxxx + lsrr. */ +- return 1748; ++ return 1752; + } + else + { +@@ -5248,7 +5248,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0xx0x0101100xxxxxxxxxxxxx + urhadd. */ +- return 2311; ++ return 2315; + } + } + else +@@ -5261,7 +5261,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx001101100xxxxxxxxxxxxx + urshr. */ +- return 2314; ++ return 2318; + } + else + { +@@ -5269,7 +5269,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0xx001101100xxxxxxxxxxxxx + uqshlr. */ +- return 2303; ++ return 2307; + } + } + else +@@ -5278,7 +5278,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 0x0001x0xx011101100xxxxxxxxxxxxx + usqadd. */ +- return 2319; ++ return 2323; + } + } + } +@@ -5297,7 +5297,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx000011100xxxxxxxxxxxxx + lsl. */ +- return 1741; ++ return 1745; + } + else + { +@@ -5305,7 +5305,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0xx000011100xxxxxxxxxxxxx + urshl. */ +- return 2312; ++ return 2316; + } + } + else +@@ -5316,7 +5316,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx010011100xxxxxxxxxxxxx + lsl. */ +- return 1739; ++ return 1743; + } + else + { +@@ -5324,7 +5324,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0xx010011100xxxxxxxxxxxxx + uhsub. */ +- return 2273; ++ return 2277; + } + } + } +@@ -5336,7 +5336,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 0x0001x0xx001011100xxxxxxxxxxxxx + uqrshl. */ +- return 2297; ++ return 2301; + } + else + { +@@ -5346,7 +5346,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx011011100xxxxxxxxxxxxx + lsl. */ +- return 1740; ++ return 1744; + } + else + { +@@ -5354,7 +5354,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0xx011011100xxxxxxxxxxxxx + uqsub. */ +- return 2306; ++ return 2310; + } + } + } +@@ -5371,7 +5371,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx000111100xxxxxxxxxxxxx + uqshl. */ +- return 2301; ++ return 2305; + } + else + { +@@ -5379,7 +5379,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0xx000111100xxxxxxxxxxxxx + urshlr. */ +- return 2313; ++ return 2317; + } + } + else +@@ -5390,7 +5390,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx010111100xxxxxxxxxxxxx + lslr. */ +- return 1742; ++ return 1746; + } + else + { +@@ -5398,7 +5398,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0xx010111100xxxxxxxxxxxxx + uhsubr. */ +- return 2274; ++ return 2278; + } + } + } +@@ -5412,7 +5412,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx001111100xxxxxxxxxxxxx + sqshlu. */ +- return 2224; ++ return 2228; + } + else + { +@@ -5420,7 +5420,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0xx001111100xxxxxxxxxxxxx + uqrshlr. */ +- return 2298; ++ return 2302; + } + } + else +@@ -5429,7 +5429,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 0x0001x0xx011111100xxxxxxxxxxxxx + uqsubr. */ +- return 2307; ++ return 2311; + } + } + } +@@ -5448,7 +5448,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx1xxxxx1000x0xxxxxxxxxx + asr. */ +- return 1299; ++ return 1303; + } + else + { +@@ -5458,7 +5458,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0x01xxxxx1000x0xxxxxxxxxx + smlalb. */ +- return 2152; ++ return 2156; + } + else + { +@@ -5466,7 +5466,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0x11xxxxx1000x0xxxxxxxxxx + smlalb. */ +- return 2153; ++ return 2157; + } + } + } +@@ -5478,7 +5478,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx1xxxxx1001x0xxxxxxxxxx + asr. */ +- return 1300; ++ return 1304; + } + else + { +@@ -5488,7 +5488,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0x01xxxxx1001x0xxxxxxxxxx + umlalb. */ +- return 2277; ++ return 2281; + } + else + { +@@ -5496,7 +5496,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0x11xxxxx1001x0xxxxxxxxxx + umlalb. */ +- return 2278; ++ return 2282; + } + } + } +@@ -5513,7 +5513,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx1xxxxx100001xxxxxxxxxx + lsr. */ +- return 1743; ++ return 1747; + } + else + { +@@ -5521,7 +5521,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx1xxxxx100011xxxxxxxxxx + lsl. */ +- return 1737; ++ return 1741; + } + } + else +@@ -5532,7 +5532,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0x01xxxxx1000x1xxxxxxxxxx + smlalt. */ +- return 2155; ++ return 2159; + } + else + { +@@ -5540,7 +5540,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0x11xxxxx1000x1xxxxxxxxxx + smlalt. */ +- return 2156; ++ return 2160; + } + } + } +@@ -5554,7 +5554,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx1xxxxx100101xxxxxxxxxx + lsr. */ +- return 1744; ++ return 1748; + } + else + { +@@ -5562,7 +5562,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx1xxxxx100111xxxxxxxxxx + lsl. */ +- return 1738; ++ return 1742; + } + } + else +@@ -5573,7 +5573,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0x01xxxxx1001x1xxxxxxxxxx + umlalt. */ +- return 2280; ++ return 2284; + } + else + { +@@ -5581,7 +5581,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0x11xxxxx1001x1xxxxxxxxxx + umlalt. */ +- return 2281; ++ return 2285; + } + } + } +@@ -5600,7 +5600,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x0001x0000xxxxx100xxxxxxxxxxxxx + ldnt1sb. */ +- return 2104; ++ return 2108; + } + else + { +@@ -5608,7 +5608,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x0001x0100xxxxx100xxxxxxxxxxxxx + ldnt1sh. */ +- return 2105; ++ return 2109; + } + } + else +@@ -5621,7 +5621,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x0001xxxxx100xxxxxxxxxxxxx + ld1sb. */ +- return 1575; ++ return 1579; + } + else + { +@@ -5629,7 +5629,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 110001x0001xxxxx100xxxxxxxxxxxxx + ld1sb. */ +- return 1579; ++ return 1583; + } + } + else +@@ -5640,7 +5640,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x0101xxxxx100xxxxxxxxxxxxx + ld1sh. */ +- return 1588; ++ return 1592; + } + else + { +@@ -5648,7 +5648,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 110001x0101xxxxx100xxxxxxxxxxxxx + ld1sh. */ +- return 1591; ++ return 1595; + } + } + } +@@ -5663,7 +5663,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x001xxxxxx100xxxxxxxxxxxxx + ld1rb. */ +- return 1545; ++ return 1549; + } + else + { +@@ -5673,7 +5673,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 110001x0010xxxxx100xxxxxxxxxxxxx + ld1sb. */ +- return 1574; ++ return 1578; + } + else + { +@@ -5681,7 +5681,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 110001x0011xxxxx100xxxxxxxxxxxxx + prfb. */ +- return 1777; ++ return 1781; + } + } + } +@@ -5693,7 +5693,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x011xxxxxx100xxxxxxxxxxxxx + ld1rsw. */ +- return 1566; ++ return 1570; + } + else + { +@@ -5703,7 +5703,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 110001x0110xxxxx100xxxxxxxxxxxxx + ld1sh. */ +- return 1586; ++ return 1590; + } + else + { +@@ -5711,7 +5711,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 110001x0111xxxxx100xxxxxxxxxxxxx + ld1sh. */ +- return 1587; ++ return 1591; + } + } + } +@@ -5733,7 +5733,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx0xxxxx010xxxxxxxxxxxxx + mla. */ +- return 1750; ++ return 1754; + } + else + { +@@ -5743,7 +5743,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x00x0xxxxx010xxxxxxxxxxxxx + ld1b. */ +- return 1511; ++ return 1515; + } + else + { +@@ -5751,7 +5751,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x01x0xxxxx010xxxxxxxxxxxxx + ld1h. */ +- return 1531; ++ return 1535; + } + } + } +@@ -5769,7 +5769,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0xx0xxxxx010000xxxxxxxxxx + smlalb. */ +- return 2154; ++ return 2158; + } + else + { +@@ -5777,7 +5777,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0xx0xxxxx010100xxxxxxxxxx + smlslb. */ +- return 2160; ++ return 2164; + } + } + else +@@ -5788,7 +5788,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0xx0xxxxx010010xxxxxxxxxx + umlalb. */ +- return 2279; ++ return 2283; + } + else + { +@@ -5796,7 +5796,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0xx0xxxxx010110xxxxxxxxxx + umlslb. */ +- return 2285; ++ return 2289; + } + } + } +@@ -5810,7 +5810,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0xx0xxxxx010001xxxxxxxxxx + smlalt. */ +- return 2157; ++ return 2161; + } + else + { +@@ -5818,7 +5818,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0xx0xxxxx010101xxxxxxxxxx + smlslt. */ +- return 2163; ++ return 2167; + } + } + else +@@ -5829,7 +5829,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0xx0xxxxx010011xxxxxxxxxx + umlalt. */ +- return 2282; ++ return 2286; + } + else + { +@@ -5837,7 +5837,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0xx0xxxxx010111xxxxxxxxxx + umlslt. */ +- return 2288; ++ return 2292; + } + } + } +@@ -5850,7 +5850,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 110001x00x0xxxxx010xxxxxxxxxxxxx + ld1b. */ +- return 1516; ++ return 1520; + } + else + { +@@ -5858,7 +5858,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 110001x01x0xxxxx010xxxxxxxxxxxxx + ld1h. */ +- return 1536; ++ return 1540; + } + } + } +@@ -5879,7 +5879,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx1xxxxx010000xxxxxxxxxx + index. */ +- return 1502; ++ return 1506; + } + else + { +@@ -5887,7 +5887,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx1xxxxx010001xxxxxxxxxx + index. */ +- return 1503; ++ return 1507; + } + } + else +@@ -5900,7 +5900,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0001xxxxx01010xxxxxxxxxxx + addvl. */ +- return 1289; ++ return 1293; + } + else + { +@@ -5908,7 +5908,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0101xxxxx01010xxxxxxxxxxx + rdvl. */ +- return 1811; ++ return 1815; + } + } + else +@@ -5917,7 +5917,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0x11xxxxx01010xxxxxxxxxxx + addpl. */ +- return 1288; ++ return 1292; + } + } + } +@@ -5929,7 +5929,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx1xxxxx010x10xxxxxxxxxx + index. */ +- return 1504; ++ return 1508; + } + else + { +@@ -5937,7 +5937,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx1xxxxx010x11xxxxxxxxxx + index. */ +- return 1501; ++ return 1505; + } + } + } +@@ -5949,7 +5949,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x00x1xxxxx010xxxxxxxxxxxxx + prfw. */ +- return 1795; ++ return 1799; + } + else + { +@@ -5957,7 +5957,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x01x1xxxxx010xxxxxxxxxxxxx + ld1h. */ +- return 1532; ++ return 1536; + } + } + } +@@ -5969,7 +5969,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x10001x00x1xxxxx010xxxxxxxxxxxxx + prfw. */ +- return 1797; ++ return 1801; + } + else + { +@@ -5981,7 +5981,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0101xxxxx010xxxxxxxxxxxxx + cdot. */ +- return 2069; ++ return 2073; + } + else + { +@@ -5989,7 +5989,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0111xxxxx010xxxxxxxxxxxxx + cdot. */ +- return 2068; ++ return 2072; + } + } + else +@@ -5998,7 +5998,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 110001x01x1xxxxx010xxxxxxxxxxxxx + ld1h. */ +- return 1537; ++ return 1541; + } + } + } +@@ -6016,7 +6016,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx0xxxxx110xxxxxxxxxxxxx + mad. */ +- return 1749; ++ return 1753; + } + else + { +@@ -6032,7 +6032,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0x010xxxx110x00xxxxxxxxxx + sqincw. */ +- return 1869; ++ return 1873; + } + else + { +@@ -6042,7 +6042,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x00110xxxx110x00xxxxxxxxxx + sqinch. */ +- return 1863; ++ return 1867; + } + else + { +@@ -6050,7 +6050,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x01110xxxx110x00xxxxxxxxxx + sqincd. */ +- return 1860; ++ return 1864; + } + } + } +@@ -6062,7 +6062,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0x011xxxx110x00xxxxxxxxxx + incw. */ +- return 1499; ++ return 1503; + } + else + { +@@ -6072,7 +6072,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x00111xxxx110x00xxxxxxxxxx + inch. */ +- return 1495; ++ return 1499; + } + else + { +@@ -6080,7 +6080,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x01111xxxx110x00xxxxxxxxxx + incd. */ +- return 1493; ++ return 1497; + } + } + } +@@ -6093,7 +6093,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0x01xxxxx110x10xxxxxxxxxx + sqdecw. */ +- return 1855; ++ return 1859; + } + else + { +@@ -6103,7 +6103,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0011xxxxx110x10xxxxxxxxxx + sqdech. */ +- return 1849; ++ return 1853; + } + else + { +@@ -6111,7 +6111,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0111xxxxx110x10xxxxxxxxxx + sqdecd. */ +- return 1846; ++ return 1850; + } + } + } +@@ -6128,7 +6128,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0x010xxxx110x01xxxxxxxxxx + uqincw. */ +- return 2017; ++ return 2021; + } + else + { +@@ -6138,7 +6138,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x00110xxxx110x01xxxxxxxxxx + uqinch. */ +- return 2011; ++ return 2015; + } + else + { +@@ -6146,7 +6146,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x01110xxxx110x01xxxxxxxxxx + uqincd. */ +- return 2008; ++ return 2012; + } + } + } +@@ -6158,7 +6158,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0x011xxxx110x01xxxxxxxxxx + decw. */ +- return 1374; ++ return 1378; + } + else + { +@@ -6168,7 +6168,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x00111xxxx110x01xxxxxxxxxx + dech. */ +- return 1370; ++ return 1374; + } + else + { +@@ -6176,7 +6176,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x01111xxxx110x01xxxxxxxxxx + decd. */ +- return 1368; ++ return 1372; + } + } + } +@@ -6189,7 +6189,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0x01xxxxx110x11xxxxxxxxxx + uqdecw. */ +- return 2003; ++ return 2007; + } + else + { +@@ -6199,7 +6199,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0011xxxxx110x11xxxxxxxxxx + uqdech. */ +- return 1997; ++ return 2001; + } + else + { +@@ -6207,7 +6207,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0111xxxxx110x11xxxxxxxxxx + uqdecd. */ +- return 1994; ++ return 1998; + } + } + } +@@ -6226,7 +6226,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x0000xxxxx110xxxxxxxxxxxxx + prfb. */ +- return 1774; ++ return 1778; + } + else + { +@@ -6234,7 +6234,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x0100xxxxx110xxxxxxxxxxxxx + prfh. */ +- return 1789; ++ return 1793; + } + } + else +@@ -6245,7 +6245,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x0001xxxxx110xxxxxxxxxxxxx + ld1b. */ +- return 1518; ++ return 1522; + } + else + { +@@ -6253,7 +6253,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x0101xxxxx110xxxxxxxxxxxxx + ld1h. */ +- return 1540; ++ return 1544; + } + } + } +@@ -6265,7 +6265,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x001xxxxxx110xxxxxxxxxxxxx + ld1rb. */ +- return 1547; ++ return 1551; + } + else + { +@@ -6273,7 +6273,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x011xxxxxx110xxxxxxxxxxxxx + ld1rh. */ +- return 1551; ++ return 1555; + } + } + } +@@ -6290,7 +6290,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x10001x0000xxxxx110xxxxxxxxxxxxx + ldnt1b. */ +- return 2100; ++ return 2104; + } + else + { +@@ -6298,7 +6298,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x10001x0100xxxxx110xxxxxxxxxxxxx + ldnt1h. */ +- return 2103; ++ return 2107; + } + } + else +@@ -6309,7 +6309,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x10001x0010xxxxx110xxxxxxxxxxxxx + ld1b. */ +- return 1517; ++ return 1521; + } + else + { +@@ -6317,7 +6317,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x10001x0110xxxxx110xxxxxxxxxxxxx + ld1h. */ +- return 1538; ++ return 1542; + } + } + } +@@ -6331,7 +6331,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x10001x0001xxxxx110xxxxxxxxxxxxx + ld1b. */ +- return 1523; ++ return 1527; + } + else + { +@@ -6345,7 +6345,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0101xxxxx1100x0xxxxxxxxxx + smullb. */ +- return 2165; ++ return 2169; + } + else + { +@@ -6353,7 +6353,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0101xxxxx1101x0xxxxxxxxxx + umullb. */ +- return 2290; ++ return 2294; + } + } + else +@@ -6364,7 +6364,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0101xxxxx1100x1xxxxxxxxxx + smullt. */ +- return 2168; ++ return 2172; + } + else + { +@@ -6372,7 +6372,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0101xxxxx1101x1xxxxxxxxxx + umullt. */ +- return 2293; ++ return 2297; + } + } + } +@@ -6382,7 +6382,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 110001x0101xxxxx110xxxxxxxxxxxxx + ld1h. */ +- return 1544; ++ return 1548; + } + } + } +@@ -6394,7 +6394,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x10001x0011xxxxx110xxxxxxxxxxxxx + prfw. */ +- return 1798; ++ return 1802; + } + else + { +@@ -6408,7 +6408,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0111xxxxx1100x0xxxxxxxxxx + smullb. */ +- return 2166; ++ return 2170; + } + else + { +@@ -6416,7 +6416,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0111xxxxx1101x0xxxxxxxxxx + umullb. */ +- return 2291; ++ return 2295; + } + } + else +@@ -6427,7 +6427,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0111xxxxx1100x1xxxxxxxxxx + smullt. */ +- return 2169; ++ return 2173; + } + else + { +@@ -6435,7 +6435,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0111xxxxx1101x1xxxxxxxxxx + umullt. */ +- return 2294; ++ return 2298; + } + } + } +@@ -6445,7 +6445,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 110001x0111xxxxx110xxxxxxxxxxxxx + ld1h. */ +- return 1539; ++ return 1543; + } + } + } +@@ -6478,7 +6478,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx000x00001xxxxxxxxxxxxx + saddv. */ +- return 1818; ++ return 1822; + } + else + { +@@ -6486,7 +6486,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx000x01001xxxxxxxxxxxxx + uaddv. */ +- return 1970; ++ return 1974; + } + } + else +@@ -6495,7 +6495,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx010x0x001xxxxxxxxxxxxx + movprfx. */ +- return 1753; ++ return 1757; + } + } + else +@@ -6508,7 +6508,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx001x00001xxxxxxxxxxxxx + smaxv. */ +- return 1836; ++ return 1840; + } + else + { +@@ -6516,7 +6516,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx011x00001xxxxxxxxxxxxx + orv. */ +- return 1770; ++ return 1774; + } + } + else +@@ -6527,7 +6527,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx001x01001xxxxxxxxxxxxx + umaxv. */ +- return 1985; ++ return 1989; + } + else + { +@@ -6535,7 +6535,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx011x01001xxxxxxxxxxxxx + eorv. */ +- return 1385; ++ return 1389; + } + } + } +@@ -6550,7 +6550,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx00xx10001xxxxxxxxxxxxx + sminv. */ +- return 1839; ++ return 1843; + } + else + { +@@ -6558,7 +6558,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx01xx10001xxxxxxxxxxxxx + andv. */ +- return 1298; ++ return 1302; + } + } + else +@@ -6567,7 +6567,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx0xxx11001xxxxxxxxxxxxx + uminv. */ +- return 1988; ++ return 1992; + } + } + } +@@ -6579,7 +6579,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x00x0xxxxx001xxxxxxxxxxxxx + ldff1sb. */ +- return 1669; ++ return 1673; + } + else + { +@@ -6587,7 +6587,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x01x0xxxxx001xxxxxxxxxxxxx + ldff1sh. */ +- return 1680; ++ return 1684; + } + } + } +@@ -6601,7 +6601,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0xx0xxxxx0010xxxxxxxxxxxx + cmla. */ +- return 2070; ++ return 2074; + } + else + { +@@ -6609,7 +6609,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0xx0xxxxx0011xxxxxxxxxxxx + sqrdcmlah. */ +- return 2202; ++ return 2206; + } + } + else +@@ -6620,7 +6620,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 110001x00x0xxxxx001xxxxxxxxxxxxx + ldff1sb. */ +- return 1676; ++ return 1680; + } + else + { +@@ -6628,7 +6628,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 110001x01x0xxxxx001xxxxxxxxxxxxx + ldff1sh. */ +- return 1686; ++ return 1690; + } + } + } +@@ -6651,7 +6651,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0001xxxxx001x00xxxxxxxxxx + and. */ +- return 1293; ++ return 1297; + } + else + { +@@ -6659,7 +6659,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0101xxxxx001x00xxxxxxxxxx + eor. */ +- return 1380; ++ return 1384; + } + } + else +@@ -6670,7 +6670,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0011xxxxx001x00xxxxxxxxxx + orr. */ +- return 1765; ++ return 1769; + } + else + { +@@ -6678,7 +6678,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0111xxxxx001x00xxxxxxxxxx + bic. */ +- return 1306; ++ return 1310; + } + } + } +@@ -6690,7 +6690,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0x01xxxxx001x10xxxxxxxxxx + eor3. */ +- return 2073; ++ return 2077; + } + else + { +@@ -6698,7 +6698,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0x11xxxxx001x10xxxxxxxxxx + bcax. */ +- return 2062; ++ return 2066; + } + } + } +@@ -6710,7 +6710,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx1xxxxx001x01xxxxxxxxxx + xar. */ +- return 2335; ++ return 2339; + } + else + { +@@ -6722,7 +6722,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0001xxxxx001x11xxxxxxxxxx + bsl. */ +- return 2063; ++ return 2067; + } + else + { +@@ -6730,7 +6730,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0101xxxxx001x11xxxxxxxxxx + bsl2n. */ +- return 2065; ++ return 2069; + } + } + else +@@ -6741,7 +6741,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0011xxxxx001x11xxxxxxxxxx + bsl1n. */ +- return 2064; ++ return 2068; + } + else + { +@@ -6749,7 +6749,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0111xxxxx001x11xxxxxxxxxx + nbsl. */ +- return 2120; ++ return 2124; + } + } + } +@@ -6763,7 +6763,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x00x1xxxxx001xxxxxxxxxxxxx + prfh. */ +- return 1788; ++ return 1792; + } + else + { +@@ -6771,7 +6771,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x01x1xxxxx001xxxxxxxxxxxxx + ldff1sh. */ +- return 1681; ++ return 1685; + } + } + } +@@ -6783,7 +6783,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x10001x00x1xxxxx001xxxxxxxxxxxxx + prfh. */ +- return 1790; ++ return 1794; + } + else + { +@@ -6799,7 +6799,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0101xxxxx0010x0xxxxxxxxxx + sqdmlalb. */ +- return 2175; ++ return 2179; + } + else + { +@@ -6807,7 +6807,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0111xxxxx0010x0xxxxxxxxxx + sqdmlalb. */ +- return 2176; ++ return 2180; + } + } + else +@@ -6818,7 +6818,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0101xxxxx0011x0xxxxxxxxxx + sqdmlslb. */ +- return 2182; ++ return 2186; + } + else + { +@@ -6826,7 +6826,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0111xxxxx0011x0xxxxxxxxxx + sqdmlslb. */ +- return 2183; ++ return 2187; + } + } + } +@@ -6840,7 +6840,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0101xxxxx0010x1xxxxxxxxxx + sqdmlalt. */ +- return 2179; ++ return 2183; + } + else + { +@@ -6848,7 +6848,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0111xxxxx0010x1xxxxxxxxxx + sqdmlalt. */ +- return 2180; ++ return 2184; + } + } + else +@@ -6859,7 +6859,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0101xxxxx0011x1xxxxxxxxxx + sqdmlslt. */ +- return 2186; ++ return 2190; + } + else + { +@@ -6867,7 +6867,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0111xxxxx0011x1xxxxxxxxxx + sqdmlslt. */ +- return 2187; ++ return 2191; + } + } + } +@@ -6878,7 +6878,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 110001x01x1xxxxx001xxxxxxxxxxxxx + ldff1sh. */ +- return 1687; ++ return 1691; + } + } + } +@@ -6904,7 +6904,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx0x0000101xxxxxxxxxxxxx + sxtb. */ +- return 1961; ++ return 1965; + } + else + { +@@ -6912,7 +6912,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx0x1000101xxxxxxxxxxxxx + cls. */ +- return 1326; ++ return 1330; + } + } + else +@@ -6923,7 +6923,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx0x0100101xxxxxxxxxxxxx + sxtw. */ +- return 1963; ++ return 1967; + } + else + { +@@ -6931,7 +6931,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx0x1100101xxxxxxxxxxxxx + fabs. */ +- return 1388; ++ return 1392; + } + } + } +@@ -6945,7 +6945,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx0x0010101xxxxxxxxxxxxx + sxth. */ +- return 1962; ++ return 1966; + } + else + { +@@ -6953,7 +6953,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx0x1010101xxxxxxxxxxxxx + cnt. */ +- return 1355; ++ return 1359; + } + } + else +@@ -6964,7 +6964,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx0x0110101xxxxxxxxxxxxx + abs. */ +- return 1284; ++ return 1288; + } + else + { +@@ -6972,7 +6972,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx0x1110101xxxxxxxxxxxxx + not. */ +- return 1762; ++ return 1766; + } + } + } +@@ -6989,7 +6989,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx0x0001101xxxxxxxxxxxxx + uxtb. */ +- return 2024; ++ return 2028; + } + else + { +@@ -6997,7 +6997,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx0x1001101xxxxxxxxxxxxx + clz. */ +- return 1327; ++ return 1331; + } + } + else +@@ -7008,7 +7008,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx0x0101101xxxxxxxxxxxxx + uxtw. */ +- return 2026; ++ return 2030; + } + else + { +@@ -7016,7 +7016,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx0x1101101xxxxxxxxxxxxx + fneg. */ +- return 1465; ++ return 1469; + } + } + } +@@ -7030,7 +7030,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx0x0011101xxxxxxxxxxxxx + uxth. */ +- return 2025; ++ return 2029; + } + else + { +@@ -7038,7 +7038,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx0x1011101xxxxxxxxxxxxx + cnot. */ +- return 1354; ++ return 1358; + } + } + else +@@ -7047,7 +7047,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx0xx111101xxxxxxxxxxxxx + neg. */ +- return 1759; ++ return 1763; + } + } + } +@@ -7064,7 +7064,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0001xxxxx1010xxxxxxxxxxxx + adr. */ +- return 1290; ++ return 1294; + } + else + { +@@ -7072,7 +7072,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0011xxxxx1010xxxxxxxxxxxx + adr. */ +- return 1291; ++ return 1295; + } + } + else +@@ -7081,7 +7081,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x01x1xxxxx1010xxxxxxxxxxxx + adr. */ +- return 1292; ++ return 1296; + } + } + else +@@ -7094,7 +7094,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx1xxxxx101100xxxxxxxxxx + ftssel. */ +- return 1491; ++ return 1495; + } + else + { +@@ -7102,7 +7102,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx1xxxxx101110xxxxxxxxxx + fexpa. */ +- return 1435; ++ return 1439; + } + } + else +@@ -7111,7 +7111,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx1xxxxx1011x1xxxxxxxxxx + movprfx. */ +- return 1752; ++ return 1756; + } + } + } +@@ -7128,7 +7128,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x0000xxxxx101xxxxxxxxxxxxx + ldnt1b. */ +- return 2099; ++ return 2103; + } + else + { +@@ -7136,7 +7136,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x0100xxxxx101xxxxxxxxxxxxx + ldnt1h. */ +- return 2102; ++ return 2106; + } + } + else +@@ -7147,7 +7147,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x0001xxxxx101xxxxxxxxxxxxx + ldff1sb. */ +- return 1678; ++ return 1682; + } + else + { +@@ -7155,7 +7155,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x0101xxxxx101xxxxxxxxxxxxx + ldff1sh. */ +- return 1690; ++ return 1694; + } + } + } +@@ -7167,7 +7167,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x001xxxxxx101xxxxxxxxxxxxx + ld1rb. */ +- return 1546; ++ return 1550; + } + else + { +@@ -7175,7 +7175,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x011xxxxxx101xxxxxxxxxxxxx + ld1rh. */ +- return 1550; ++ return 1554; + } + } + } +@@ -7198,7 +7198,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0xx0x0000101xxxxxxxxxxxxx + urecpe. */ +- return 2310; ++ return 2314; + } + else + { +@@ -7206,7 +7206,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0xx0x1000101xxxxxxxxxxxxx + sqabs. */ +- return 2172; ++ return 2176; + } + } + else +@@ -7217,7 +7217,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0xx00x100101xxxxxxxxxxxxx + sadalp. */ +- return 2136; ++ return 2140; + } + else + { +@@ -7225,7 +7225,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0xx01x100101xxxxxxxxxxxxx + smaxp. */ +- return 2150; ++ return 2154; + } + } + } +@@ -7235,7 +7235,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0xx0xxx10101xxxxxxxxxxxxx + sminp. */ +- return 2151; ++ return 2155; + } + } + else +@@ -7252,7 +7252,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0xx000001101xxxxxxxxxxxxx + ursqrte. */ +- return 2315; ++ return 2319; + } + else + { +@@ -7260,7 +7260,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0xx010001101xxxxxxxxxxxxx + addp. */ +- return 2061; ++ return 2065; + } + } + else +@@ -7269,7 +7269,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0xx0x1001101xxxxxxxxxxxxx + sqneg. */ +- return 2199; ++ return 2203; + } + } + else +@@ -7280,7 +7280,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0xx00x101101xxxxxxxxxxxxx + uadalp. */ +- return 2267; ++ return 2271; + } + else + { +@@ -7288,7 +7288,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0xx01x101101xxxxxxxxxxxxx + umaxp. */ +- return 2275; ++ return 2279; + } + } + } +@@ -7298,7 +7298,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0xx0xxx11101xxxxxxxxxxxxx + uminp. */ +- return 2276; ++ return 2280; + } + } + } +@@ -7310,7 +7310,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 110001x00x0xxxxx101xxxxxxxxxxxxx + ldff1sb. */ +- return 1677; ++ return 1681; + } + else + { +@@ -7318,7 +7318,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 110001x01x0xxxxx101xxxxxxxxxxxxx + ldff1sh. */ +- return 1688; ++ return 1692; + } + } + } +@@ -7332,7 +7332,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x10001x0001xxxxx101xxxxxxxxxxxxx + ldff1sb. */ +- return 1679; ++ return 1683; + } + else + { +@@ -7346,7 +7346,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0101xxxxx1010x0xxxxxxxxxx + smlslb. */ +- return 2158; ++ return 2162; + } + else + { +@@ -7354,7 +7354,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0101xxxxx1011x0xxxxxxxxxx + umlslb. */ +- return 2283; ++ return 2287; + } + } + else +@@ -7365,7 +7365,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0101xxxxx1010x1xxxxxxxxxx + smlslt. */ +- return 2161; ++ return 2165; + } + else + { +@@ -7373,7 +7373,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0101xxxxx1011x1xxxxxxxxxx + umlslt. */ +- return 2286; ++ return 2290; + } + } + } +@@ -7383,7 +7383,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 110001x0101xxxxx101xxxxxxxxxxxxx + ldff1sh. */ +- return 1691; ++ return 1695; + } + } + } +@@ -7395,7 +7395,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x10001x0011xxxxx101xxxxxxxxxxxxx + prfh. */ +- return 1791; ++ return 1795; + } + else + { +@@ -7409,7 +7409,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0111xxxxx1010x0xxxxxxxxxx + smlslb. */ +- return 2159; ++ return 2163; + } + else + { +@@ -7417,7 +7417,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0111xxxxx1011x0xxxxxxxxxx + umlslb. */ +- return 2284; ++ return 2288; + } + } + else +@@ -7428,7 +7428,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0111xxxxx1010x1xxxxxxxxxx + smlslt. */ +- return 2162; ++ return 2166; + } + else + { +@@ -7436,7 +7436,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0111xxxxx1011x1xxxxxxxxxx + umlslt. */ +- return 2287; ++ return 2291; + } + } + } +@@ -7446,7 +7446,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 110001x0111xxxxx101xxxxxxxxxxxxx + ldff1sh. */ +- return 1689; ++ return 1693; + } + } + } +@@ -7468,7 +7468,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx0xxxxx011xxxxxxxxxxxxx + mls. */ +- return 1751; ++ return 1755; + } + else + { +@@ -7478,7 +7478,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x00x0xxxxx011xxxxxxxxxxxxx + ldff1b. */ +- return 1635; ++ return 1639; + } + else + { +@@ -7486,7 +7486,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x01x0xxxxx011xxxxxxxxxxxxx + ldff1h. */ +- return 1655; ++ return 1659; + } + } + } +@@ -7504,7 +7504,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0xx0xxxxx011000xxxxxxxxxx + sqdmlalb. */ +- return 2177; ++ return 2181; + } + else + { +@@ -7512,7 +7512,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0xx0xxxxx011100xxxxxxxxxx + sqrdmlah. */ +- return 2206; ++ return 2210; + } + } + else +@@ -7523,7 +7523,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0xx0xxxxx011010xxxxxxxxxx + sqdmlslb. */ +- return 2184; ++ return 2188; + } + else + { +@@ -7531,7 +7531,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0xx0xxxxx011110xxxxxxxxxx + usdot. */ +- return 2459; ++ return 2463; + } + } + } +@@ -7545,7 +7545,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0xx0xxxxx011001xxxxxxxxxx + sqdmlalt. */ +- return 2181; ++ return 2185; + } + else + { +@@ -7553,7 +7553,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0xx0xxxxx011101xxxxxxxxxx + sqrdmlsh. */ +- return 2210; ++ return 2214; + } + } + else +@@ -7562,7 +7562,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0xx0xxxxx011x11xxxxxxxxxx + sqdmlslt. */ +- return 2188; ++ return 2192; + } + } + } +@@ -7574,7 +7574,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 110001x00x0xxxxx011xxxxxxxxxxxxx + ldff1b. */ +- return 1644; ++ return 1648; + } + else + { +@@ -7582,7 +7582,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 110001x01x0xxxxx011xxxxxxxxxxxxx + ldff1h. */ +- return 1663; ++ return 1667; + } + } + } +@@ -7603,7 +7603,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx1xxxxx011000xxxxxxxxxx + mul. */ +- return 2119; ++ return 2123; + } + else + { +@@ -7611,7 +7611,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx1xxxxx011100xxxxxxxxxx + sqdmulh. */ +- return 2192; ++ return 2196; + } + } + else +@@ -7620,7 +7620,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx1xxxxx011x10xxxxxxxxxx + smulh. */ +- return 2164; ++ return 2168; + } + } + else +@@ -7633,7 +7633,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx1xxxxx011001xxxxxxxxxx + pmul. */ +- return 2122; ++ return 2126; + } + else + { +@@ -7641,7 +7641,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx1xxxxx011101xxxxxxxxxx + sqrdmulh. */ +- return 2214; ++ return 2218; + } + } + else +@@ -7650,7 +7650,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx1xxxxx011x11xxxxxxxxxx + umulh. */ +- return 2289; ++ return 2293; + } + } + } +@@ -7662,7 +7662,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x00x1xxxxx011xxxxxxxxxxxxx + prfd. */ +- return 1781; ++ return 1785; + } + else + { +@@ -7670,7 +7670,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x01x1xxxxx011xxxxxxxxxxxxx + ldff1h. */ +- return 1656; ++ return 1660; + } + } + } +@@ -7682,7 +7682,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x10001x00x1xxxxx011xxxxxxxxxxxxx + prfd. */ +- return 1783; ++ return 1787; + } + else + { +@@ -7696,7 +7696,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0101xxxxx0110xxxxxxxxxxxx + cmla. */ +- return 2071; ++ return 2075; + } + else + { +@@ -7704,7 +7704,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0111xxxxx0110xxxxxxxxxxxx + cmla. */ +- return 2072; ++ return 2076; + } + } + else +@@ -7715,7 +7715,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0101xxxxx0111xxxxxxxxxxxx + sqrdcmlah. */ +- return 2200; ++ return 2204; + } + else + { +@@ -7723,7 +7723,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0111xxxxx0111xxxxxxxxxxxx + sqrdcmlah. */ +- return 2201; ++ return 2205; + } + } + } +@@ -7733,7 +7733,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 110001x01x1xxxxx011xxxxxxxxxxxxx + ldff1h. */ +- return 1664; ++ return 1668; + } + } + } +@@ -7751,7 +7751,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0xx0xxxxx111xxxxxxxxxxxxx + msb. */ +- return 1754; ++ return 1758; + } + else + { +@@ -7771,7 +7771,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x00010xxxx111000xxxxxxxxxx + cntb. */ +- return 1356; ++ return 1360; + } + else + { +@@ -7779,7 +7779,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x01010xxxx111000xxxxxxxxxx + cntw. */ +- return 1360; ++ return 1364; + } + } + else +@@ -7790,7 +7790,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x00110xxxx111000xxxxxxxxxx + cnth. */ +- return 1358; ++ return 1362; + } + else + { +@@ -7798,7 +7798,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x01110xxxx111000xxxxxxxxxx + cntd. */ +- return 1357; ++ return 1361; + } + } + } +@@ -7812,7 +7812,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x00011xxxx111000xxxxxxxxxx + incb. */ +- return 1492; ++ return 1496; + } + else + { +@@ -7820,7 +7820,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x01011xxxx111000xxxxxxxxxx + incw. */ +- return 1500; ++ return 1504; + } + } + else +@@ -7831,7 +7831,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x00111xxxx111000xxxxxxxxxx + inch. */ +- return 1496; ++ return 1500; + } + else + { +@@ -7839,7 +7839,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x01111xxxx111000xxxxxxxxxx + incd. */ +- return 1494; ++ return 1498; + } + } + } +@@ -7856,7 +7856,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x00010xxxx111100xxxxxxxxxx + sqincb. */ +- return 1859; ++ return 1863; + } + else + { +@@ -7864,7 +7864,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x01010xxxx111100xxxxxxxxxx + sqincw. */ +- return 1871; ++ return 1875; + } + } + else +@@ -7875,7 +7875,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x00110xxxx111100xxxxxxxxxx + sqinch. */ +- return 1865; ++ return 1869; + } + else + { +@@ -7883,7 +7883,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x01110xxxx111100xxxxxxxxxx + sqincd. */ +- return 1862; ++ return 1866; + } + } + } +@@ -7897,7 +7897,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x00011xxxx111100xxxxxxxxxx + sqincb. */ +- return 1858; ++ return 1862; + } + else + { +@@ -7905,7 +7905,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x01011xxxx111100xxxxxxxxxx + sqincw. */ +- return 1870; ++ return 1874; + } + } + else +@@ -7916,7 +7916,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x00111xxxx111100xxxxxxxxxx + sqinch. */ +- return 1864; ++ return 1868; + } + else + { +@@ -7924,7 +7924,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x01111xxxx111100xxxxxxxxxx + sqincd. */ +- return 1861; ++ return 1865; + } + } + } +@@ -7942,7 +7942,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x00010xxxx111x10xxxxxxxxxx + sqdecb. */ +- return 1845; ++ return 1849; + } + else + { +@@ -7950,7 +7950,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x01010xxxx111x10xxxxxxxxxx + sqdecw. */ +- return 1857; ++ return 1861; + } + } + else +@@ -7961,7 +7961,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x00110xxxx111x10xxxxxxxxxx + sqdech. */ +- return 1851; ++ return 1855; + } + else + { +@@ -7969,7 +7969,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x01110xxxx111x10xxxxxxxxxx + sqdecd. */ +- return 1848; ++ return 1852; + } + } + } +@@ -7983,7 +7983,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x00011xxxx111x10xxxxxxxxxx + sqdecb. */ +- return 1844; ++ return 1848; + } + else + { +@@ -7991,7 +7991,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x01011xxxx111x10xxxxxxxxxx + sqdecw. */ +- return 1856; ++ return 1860; + } + } + else +@@ -8002,7 +8002,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x00111xxxx111x10xxxxxxxxxx + sqdech. */ +- return 1850; ++ return 1854; + } + else + { +@@ -8010,7 +8010,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x01111xxxx111x10xxxxxxxxxx + sqdecd. */ +- return 1847; ++ return 1851; + } + } + } +@@ -8030,7 +8030,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0001xxxxx111001xxxxxxxxxx + decb. */ +- return 1367; ++ return 1371; + } + else + { +@@ -8038,7 +8038,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0101xxxxx111001xxxxxxxxxx + decw. */ +- return 1375; ++ return 1379; + } + } + else +@@ -8049,7 +8049,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0011xxxxx111001xxxxxxxxxx + dech. */ +- return 1371; ++ return 1375; + } + else + { +@@ -8057,7 +8057,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x0111xxxxx111001xxxxxxxxxx + decd. */ +- return 1369; ++ return 1373; + } + } + } +@@ -8073,7 +8073,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x00010xxxx111101xxxxxxxxxx + uqincb. */ +- return 2006; ++ return 2010; + } + else + { +@@ -8081,7 +8081,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x01010xxxx111101xxxxxxxxxx + uqincw. */ +- return 2018; ++ return 2022; + } + } + else +@@ -8092,7 +8092,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x00110xxxx111101xxxxxxxxxx + uqinch. */ +- return 2012; ++ return 2016; + } + else + { +@@ -8100,7 +8100,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x01110xxxx111101xxxxxxxxxx + uqincd. */ +- return 2009; ++ return 2013; + } + } + } +@@ -8114,7 +8114,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x00011xxxx111101xxxxxxxxxx + uqincb. */ +- return 2007; ++ return 2011; + } + else + { +@@ -8122,7 +8122,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x01011xxxx111101xxxxxxxxxx + uqincw. */ +- return 2019; ++ return 2023; + } + } + else +@@ -8133,7 +8133,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x00111xxxx111101xxxxxxxxxx + uqinch. */ +- return 2013; ++ return 2017; + } + else + { +@@ -8141,7 +8141,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x01111xxxx111101xxxxxxxxxx + uqincd. */ +- return 2010; ++ return 2014; + } + } + } +@@ -8159,7 +8159,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x00010xxxx111x11xxxxxxxxxx + uqdecb. */ +- return 1992; ++ return 1996; + } + else + { +@@ -8167,7 +8167,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x01010xxxx111x11xxxxxxxxxx + uqdecw. */ +- return 2004; ++ return 2008; + } + } + else +@@ -8178,7 +8178,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x00110xxxx111x11xxxxxxxxxx + uqdech. */ +- return 1998; ++ return 2002; + } + else + { +@@ -8186,7 +8186,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x01110xxxx111x11xxxxxxxxxx + uqdecd. */ +- return 1995; ++ return 1999; + } + } + } +@@ -8200,7 +8200,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x00011xxxx111x11xxxxxxxxxx + uqdecb. */ +- return 1993; ++ return 1997; + } + else + { +@@ -8208,7 +8208,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x01011xxxx111x11xxxxxxxxxx + uqdecw. */ +- return 2005; ++ return 2009; + } + } + else +@@ -8219,7 +8219,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x00111xxxx111x11xxxxxxxxxx + uqdech. */ +- return 1999; ++ return 2003; + } + else + { +@@ -8227,7 +8227,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x01111xxxx111x11xxxxxxxxxx + uqdecd. */ +- return 1996; ++ return 2000; + } + } + } +@@ -8247,7 +8247,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x0000xxxxx111xxxxxxxxxxxxx + prfb. */ +- return 1778; ++ return 1782; + } + else + { +@@ -8255,7 +8255,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x0100xxxxx111xxxxxxxxxxxxx + prfh. */ +- return 1792; ++ return 1796; + } + } + else +@@ -8266,7 +8266,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x0001xxxxx111xxxxxxxxxxxxx + ldff1b. */ +- return 1646; ++ return 1650; + } + else + { +@@ -8274,7 +8274,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x0101xxxxx111xxxxxxxxxxxxx + ldff1h. */ +- return 1667; ++ return 1671; + } + } + } +@@ -8286,7 +8286,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x001xxxxxx111xxxxxxxxxxxxx + ld1rb. */ +- return 1548; ++ return 1552; + } + else + { +@@ -8294,7 +8294,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x011xxxxxx111xxxxxxxxxxxxx + ld1rh. */ +- return 1552; ++ return 1556; + } + } + } +@@ -8311,7 +8311,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x10001x0000xxxxx111xxxxxxxxxxxxx + prfb. */ +- return 1780; ++ return 1784; + } + else + { +@@ -8319,7 +8319,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x10001x0100xxxxx111xxxxxxxxxxxxx + prfh. */ +- return 1794; ++ return 1798; + } + } + else +@@ -8330,7 +8330,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x10001x0010xxxxx111xxxxxxxxxxxxx + ldff1b. */ +- return 1645; ++ return 1649; + } + else + { +@@ -8338,7 +8338,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x10001x0110xxxxx111xxxxxxxxxxxxx + ldff1h. */ +- return 1665; ++ return 1669; + } + } + } +@@ -8356,7 +8356,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x00x1xxxxx111x00xxxxxxxxxx + sqdmulh. */ +- return 2189; ++ return 2193; + } + else + { +@@ -8364,7 +8364,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x00x1xxxxx111x10xxxxxxxxxx + mul. */ +- return 2116; ++ return 2120; + } + } + else +@@ -8373,7 +8373,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x00x1xxxxx111xx1xxxxxxxxxx + sqrdmulh. */ +- return 2211; ++ return 2215; + } + } + else +@@ -8384,7 +8384,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 110001x0001xxxxx111xxxxxxxxxxxxx + ldff1b. */ +- return 1647; ++ return 1651; + } + else + { +@@ -8392,7 +8392,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 110001x0011xxxxx111xxxxxxxxxxxxx + prfd. */ +- return 1784; ++ return 1788; + } + } + } +@@ -8410,7 +8410,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0101xxxxx1110x0xxxxxxxxxx + sqdmullb. */ +- return 2193; ++ return 2197; + } + else + { +@@ -8420,7 +8420,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0101xxxxx111100xxxxxxxxxx + sqdmulh. */ +- return 2190; ++ return 2194; + } + else + { +@@ -8428,7 +8428,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0101xxxxx111110xxxxxxxxxx + mul. */ +- return 2117; ++ return 2121; + } + } + } +@@ -8440,7 +8440,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0101xxxxx1110x1xxxxxxxxxx + sqdmullt. */ +- return 2196; ++ return 2200; + } + else + { +@@ -8448,7 +8448,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0101xxxxx1111x1xxxxxxxxxx + sqrdmulh. */ +- return 2212; ++ return 2216; + } + } + } +@@ -8458,7 +8458,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 110001x0101xxxxx111xxxxxxxxxxxxx + ldff1h. */ +- return 1668; ++ return 1672; + } + } + else +@@ -8473,7 +8473,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0111xxxxx1110x0xxxxxxxxxx + sqdmullb. */ +- return 2194; ++ return 2198; + } + else + { +@@ -8483,7 +8483,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0111xxxxx111100xxxxxxxxxx + sqdmulh. */ +- return 2191; ++ return 2195; + } + else + { +@@ -8491,7 +8491,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0111xxxxx111110xxxxxxxxxx + mul. */ +- return 2118; ++ return 2122; + } + } + } +@@ -8503,7 +8503,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0111xxxxx1110x1xxxxxxxxxx + sqdmullt. */ +- return 2197; ++ return 2201; + } + else + { +@@ -8511,7 +8511,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0111xxxxx1111x1xxxxxxxxxx + sqrdmulh. */ +- return 2213; ++ return 2217; + } + } + } +@@ -8521,7 +8521,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 110001x0111xxxxx111xxxxxxxxxxxxx + ldff1h. */ +- return 1666; ++ return 1670; + } + } + } +@@ -8551,7 +8551,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x0xx0xxxxx000xxxxxxxx0xxxx + cmphs. */ +- return 1340; ++ return 1344; + } + else + { +@@ -8559,7 +8559,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x0xx0xxxxx000xxxxxxxx1xxxx + cmphi. */ +- return 1337; ++ return 1341; + } + } + else +@@ -8570,7 +8570,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x00x0xxxxx000xxxxxxxxxxxxx + ld1rqb. */ +- return 1554; ++ return 1558; + } + else + { +@@ -8578,7 +8578,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x01x0xxxxx000xxxxxxxxxxxxx + ld1rqh. */ +- return 1558; ++ return 1562; + } + } + } +@@ -8592,7 +8592,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x0xx0xxxxx010xxxxxxxx0xxxx + cmpge. */ +- return 1331; ++ return 1335; + } + else + { +@@ -8600,7 +8600,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x0xx0xxxxx010xxxxxxxx1xxxx + cmpgt. */ +- return 1334; ++ return 1338; + } + } + else +@@ -8613,7 +8613,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x0000xxxxx010xxxxxxxxxxxxx + ld1b. */ +- return 1512; ++ return 1516; + } + else + { +@@ -8621,7 +8621,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x0100xxxxx010xxxxxxxxxxxxx + ld1sw. */ +- return 1592; ++ return 1596; + } + } + else +@@ -8632,7 +8632,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x0010xxxxx010xxxxxxxxxxxxx + ld1b. */ +- return 1514; ++ return 1518; + } + else + { +@@ -8640,7 +8640,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x0110xxxxx010xxxxxxxxxxxxx + ld1h. */ +- return 1534; ++ return 1538; + } + } + } +@@ -8658,7 +8658,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x0xx0xxxxx001xxxxxxxx0xxxx + cmpeq. */ +- return 1328; ++ return 1332; + } + else + { +@@ -8666,7 +8666,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x0xx0xxxxx001xxxxxxxx1xxxx + cmpne. */ +- return 1351; ++ return 1355; + } + } + else +@@ -8677,7 +8677,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x00x0xxxxx001xxxxxxxxxxxxx + ld1rqb. */ +- return 1553; ++ return 1557; + } + else + { +@@ -8685,7 +8685,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x01x0xxxxx001xxxxxxxxxxxxx + ld1rqh. */ +- return 1557; ++ return 1561; + } + } + } +@@ -8699,7 +8699,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x0xx0xxxxx011xxxxxxxx0xxxx + cmplt. */ +- return 1349; ++ return 1353; + } + else + { +@@ -8707,7 +8707,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x0xx0xxxxx011xxxxxxxx1xxxx + cmple. */ +- return 1343; ++ return 1347; + } + } + else +@@ -8720,7 +8720,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x0000xxxxx011xxxxxxxxxxxxx + ldff1b. */ +- return 1636; ++ return 1640; + } + else + { +@@ -8728,7 +8728,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x0100xxxxx011xxxxxxxxxxxxx + ldff1sw. */ +- return 1692; ++ return 1696; + } + } + else +@@ -8739,7 +8739,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x0010xxxxx011xxxxxxxxxxxxx + ldff1b. */ +- return 1640; ++ return 1644; + } + else + { +@@ -8747,7 +8747,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x0110xxxxx011xxxxxxxxxxxxx + ldff1h. */ +- return 1659; ++ return 1663; + } + } + } +@@ -8762,7 +8762,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0xx0xxxxx0xxxxxxxxxxxxxxx + fcmla. */ +- return 1397; ++ return 1401; + } + else + { +@@ -8774,7 +8774,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x0x00xxxxx0x0xxxxxxxxxxxxx + st1b. */ +- return 1874; ++ return 1878; + } + else + { +@@ -8784,7 +8784,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x0010xxxxx0x0xxxxxxxxxxxxx + st1b. */ +- return 1878; ++ return 1882; + } + else + { +@@ -8792,7 +8792,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x0110xxxxx0x0xxxxxxxxxxxxx + st1h. */ +- return 1899; ++ return 1903; + } + } + } +@@ -8808,7 +8808,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x0000xxxxx001xxxxxxxxxxxxx + stnt1b. */ +- return 2251; ++ return 2255; + } + else + { +@@ -8816,7 +8816,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x0100xxxxx001xxxxxxxxxxxxx + stnt1h. */ +- return 2254; ++ return 2258; + } + } + else +@@ -8827,7 +8827,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x0010xxxxx001xxxxxxxxxxxxx + stnt1b. */ +- return 2250; ++ return 2254; + } + else + { +@@ -8835,7 +8835,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x0110xxxxx001xxxxxxxxxxxxx + stnt1h. */ +- return 2253; ++ return 2257; + } + } + } +@@ -8849,7 +8849,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x0000xxxxx011xxxxxxxxxxxxx + stnt1b. */ +- return 1944; ++ return 1948; + } + else + { +@@ -8857,7 +8857,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x0100xxxxx011xxxxxxxxxxxxx + stnt1h. */ +- return 1948; ++ return 1952; + } + } + else +@@ -8868,7 +8868,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x0010xxxxx011xxxxxxxxxxxxx + st3b. */ +- return 1928; ++ return 1932; + } + else + { +@@ -8876,7 +8876,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x0110xxxxx011xxxxxxxxxxxxx + st3h. */ +- return 1932; ++ return 1936; + } + } + } +@@ -8898,7 +8898,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x01001x0xx0xxxxx100xxxxxxxx0xxxx + cmpge. */ +- return 1332; ++ return 1336; + } + else + { +@@ -8906,7 +8906,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x01001x0xx0xxxxx100xxxxxxxx1xxxx + cmpgt. */ +- return 1335; ++ return 1339; + } + } + else +@@ -8919,7 +8919,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x0xx0xxxxx110xxxxxxxx0xxxx + cmphs. */ +- return 1341; ++ return 1345; + } + else + { +@@ -8927,7 +8927,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x0xx0xxxxx110xxxxxxxx1xxxx + cmphi. */ +- return 1338; ++ return 1342; + } + } + else +@@ -8940,7 +8940,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x0000xxxxx110xxxxxxxxxxxxx + ldnt1b. */ +- return 1727; ++ return 1731; + } + else + { +@@ -8948,7 +8948,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x0100xxxxx110xxxxxxxxxxxxx + ldnt1h. */ +- return 1731; ++ return 1735; + } + } + else +@@ -8959,7 +8959,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x0010xxxxx110xxxxxxxxxxxxx + ld3b. */ +- return 1619; ++ return 1623; + } + else + { +@@ -8967,7 +8967,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x0110xxxxx110xxxxxxxxxxxxx + ld3h. */ +- return 1623; ++ return 1627; + } + } + } +@@ -8987,7 +8987,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0xx00x00x1x0xxxxxxxxxxxxx + fcadd. */ +- return 1396; ++ return 1400; + } + else + { +@@ -8995,7 +8995,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0xx01x00x1x0xxxxxxxxxxxxx + faddp. */ +- return 2077; ++ return 2081; + } + } + else +@@ -9006,7 +9006,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0xx0xx1001x0xxxxxxxxxxxxx + fmaxnmp. */ +- return 2085; ++ return 2089; + } + else + { +@@ -9014,7 +9014,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0xx0xx1011x0xxxxxxxxxxxxx + fminnmp. */ +- return 2087; ++ return 2091; + } + } + } +@@ -9026,7 +9026,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0xx0xxx101x0xxxxxxxxxxxxx + fmaxp. */ +- return 2086; ++ return 2090; + } + else + { +@@ -9034,7 +9034,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0xx0xxx111x0xxxxxxxxxxxxx + fminp. */ +- return 2088; ++ return 2092; + } + } + } +@@ -9048,7 +9048,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x0000xxxxx1x0xxxxxxxxxxxxx + st1b. */ +- return 1875; ++ return 1879; + } + else + { +@@ -9056,7 +9056,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x0100xxxxx1x0xxxxxxxxxxxxx + st1h. */ +- return 1894; ++ return 1898; + } + } + else +@@ -9067,7 +9067,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x0010xxxxx1x0xxxxxxxxxxxxx + st1b. */ +- return 1879; ++ return 1883; + } + else + { +@@ -9075,7 +9075,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x0110xxxxx1x0xxxxxxxxxxxxx + st1h. */ +- return 1900; ++ return 1904; + } + } + } +@@ -9095,7 +9095,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x0xx0xxxxx101xxxxxxxx0xxxx + cmpeq. */ +- return 1329; ++ return 1333; + } + else + { +@@ -9103,7 +9103,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x0xx0xxxxx101xxxxxxxx1xxxx + cmpne. */ +- return 1352; ++ return 1356; + } + } + else +@@ -9118,7 +9118,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x00000xxxx101xxxxxxxxxxxxx + ld1b. */ +- return 1519; ++ return 1523; + } + else + { +@@ -9126,7 +9126,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x01000xxxx101xxxxxxxxxxxxx + ld1sw. */ +- return 1597; ++ return 1601; + } + } + else +@@ -9137,7 +9137,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x00100xxxx101xxxxxxxxxxxxx + ld1b. */ +- return 1521; ++ return 1525; + } + else + { +@@ -9145,7 +9145,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x01100xxxx101xxxxxxxxxxxxx + ld1h. */ +- return 1542; ++ return 1546; + } + } + } +@@ -9159,7 +9159,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x00001xxxx101xxxxxxxxxxxxx + ldnf1b. */ +- return 1711; ++ return 1715; + } + else + { +@@ -9167,7 +9167,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x01001xxxx101xxxxxxxxxxxxx + ldnf1sw. */ +- return 1724; ++ return 1728; + } + } + else +@@ -9178,7 +9178,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x00101xxxx101xxxxxxxxxxxxx + ldnf1b. */ +- return 1713; ++ return 1717; + } + else + { +@@ -9186,7 +9186,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x01101xxxx101xxxxxxxxxxxxx + ldnf1h. */ +- return 1717; ++ return 1721; + } + } + } +@@ -9204,7 +9204,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0000xxxxx101xxxxxxxxxxxxx + fcvtxnt. */ +- return 2083; ++ return 2087; + } + else + { +@@ -9212,7 +9212,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x0000xxxxx101xxxxxxxxxxxxx + st1b. */ +- return 1876; ++ return 1880; + } + } + else +@@ -9227,7 +9227,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0100xxx00101xxxxxxxxxxxxx + fcvtnt. */ +- return 2080; ++ return 2084; + } + else + { +@@ -9235,7 +9235,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0100xxx10101xxxxxxxxxxxxx + bfcvtnt. */ +- return 2488; ++ return 2492; + } + } + else +@@ -9244,7 +9244,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0100xxxx1101xxxxxxxxxxxxx + fcvtlt. */ +- return 2078; ++ return 2082; + } + } + else +@@ -9253,7 +9253,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x0100xxxxx101xxxxxxxxxxxxx + st1h. */ +- return 1895; ++ return 1899; + } + } + } +@@ -9265,7 +9265,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x11001x0010xxxxx101xxxxxxxxxxxxx + st1b. */ +- return 1883; ++ return 1887; + } + else + { +@@ -9277,7 +9277,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0110xxxx0101xxxxxxxxxxxxx + fcvtnt. */ +- return 2081; ++ return 2085; + } + else + { +@@ -9285,7 +9285,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0110xxxx1101xxxxxxxxxxxxx + fcvtlt. */ +- return 2079; ++ return 2083; + } + } + else +@@ -9294,7 +9294,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x0110xxxxx101xxxxxxxxxxxxx + st1h. */ +- return 1904; ++ return 1908; + } + } + } +@@ -9312,7 +9312,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x0xx0xxxxx111xxxxxxxx0xxxx + cmplo. */ +- return 1345; ++ return 1349; + } + else + { +@@ -9320,7 +9320,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x0xx0xxxxx111xxxxxxxx1xxxx + cmpls. */ +- return 1347; ++ return 1351; + } + } + else +@@ -9333,7 +9333,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x0000xxxxx111xxxxxxxxxxxxx + ldnt1b. */ +- return 1728; ++ return 1732; + } + else + { +@@ -9341,7 +9341,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x0100xxxxx111xxxxxxxxxxxxx + ldnt1h. */ +- return 1732; ++ return 1736; + } + } + else +@@ -9352,7 +9352,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x0010xxxxx111xxxxxxxxxxxxx + ld3b. */ +- return 1620; ++ return 1624; + } + else + { +@@ -9360,7 +9360,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x0110xxxxx111xxxxxxxxxxxxx + ld3h. */ +- return 1624; ++ return 1628; + } + } + } +@@ -9375,7 +9375,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x11001x0x000xxxx111xxxxxxxxxxxxx + st1b. */ +- return 1881; ++ return 1885; + } + else + { +@@ -9385,7 +9385,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x11001x00100xxxx111xxxxxxxxxxxxx + st1b. */ +- return 1884; ++ return 1888; + } + else + { +@@ -9393,7 +9393,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x11001x01100xxxx111xxxxxxxxxxxxx + st1h. */ +- return 1905; ++ return 1909; + } + } + } +@@ -9407,7 +9407,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x11001x00001xxxx111xxxxxxxxxxxxx + stnt1b. */ +- return 1945; ++ return 1949; + } + else + { +@@ -9415,7 +9415,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x11001x01001xxxx111xxxxxxxxxxxxx + stnt1h. */ +- return 1949; ++ return 1953; + } + } + else +@@ -9426,7 +9426,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x11001x00101xxxx111xxxxxxxxxxxxx + st3b. */ +- return 1929; ++ return 1933; + } + else + { +@@ -9434,7 +9434,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x11001x01101xxxx111xxxxxxxxxxxxx + st3h. */ +- return 1933; ++ return 1937; + } + } + } +@@ -9457,7 +9457,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x0xx1xxxxxxx0xxxxxxxx0xxxx + cmphs. */ +- return 1342; ++ return 1346; + } + else + { +@@ -9465,7 +9465,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x0xx1xxxxxxx0xxxxxxxx1xxxx + cmphi. */ +- return 1339; ++ return 1343; + } + } + else +@@ -9478,7 +9478,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x00x1xxxxxx00xxxxxxxxxxxxx + ld1rob. */ +- return 2464; ++ return 2468; + } + else + { +@@ -9486,7 +9486,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x01x1xxxxxx00xxxxxxxxxxxxx + ld1roh. */ +- return 2465; ++ return 2469; + } + } + else +@@ -9501,7 +9501,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x0001xxxxx010xxxxxxxxxxxxx + ld1b. */ +- return 1513; ++ return 1517; + } + else + { +@@ -9509,7 +9509,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x0101xxxxx010xxxxxxxxxxxxx + ld1h. */ +- return 1533; ++ return 1537; + } + } + else +@@ -9520,7 +9520,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x0011xxxxx010xxxxxxxxxxxxx + ld1b. */ +- return 1515; ++ return 1519; + } + else + { +@@ -9528,7 +9528,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x0111xxxxx010xxxxxxxxxxxxx + ld1h. */ +- return 1535; ++ return 1539; + } + } + } +@@ -9542,7 +9542,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x0001xxxxx110xxxxxxxxxxxxx + ld2b. */ +- return 1611; ++ return 1615; + } + else + { +@@ -9550,7 +9550,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x0101xxxxx110xxxxxxxxxxxxx + ld2h. */ +- return 1615; ++ return 1619; + } + } + else +@@ -9561,7 +9561,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x0011xxxxx110xxxxxxxxxxxxx + ld4b. */ +- return 1627; ++ return 1631; + } + else + { +@@ -9569,7 +9569,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x0111xxxxx110xxxxxxxxxxxxx + ld4h. */ +- return 1631; ++ return 1635; + } + } + } +@@ -9592,7 +9592,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x11001x00x1xxxxx0000x0xxxxxxxxxx + fmla. */ +- return 1450; ++ return 1454; + } + else + { +@@ -9602,7 +9602,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x11001x0101xxxxx0000x0xxxxxxxxxx + fmla. */ +- return 1451; ++ return 1455; + } + else + { +@@ -9610,7 +9610,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x11001x0111xxxxx0000x0xxxxxxxxxx + fmla. */ +- return 1452; ++ return 1456; + } + } + } +@@ -9622,7 +9622,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x11001x00x1xxxxx0000x1xxxxxxxxxx + fmls. */ +- return 1454; ++ return 1458; + } + else + { +@@ -9632,7 +9632,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x11001x0101xxxxx0000x1xxxxxxxxxx + fmls. */ +- return 1455; ++ return 1459; + } + else + { +@@ -9640,7 +9640,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x11001x0111xxxxx0000x1xxxxxxxxxx + fmls. */ +- return 1456; ++ return 1460; + } + } + } +@@ -9653,7 +9653,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x11001x0x01xxxxx0001xxxxxxxxxxxx + fcmla. */ +- return 1398; ++ return 1402; + } + else + { +@@ -9661,7 +9661,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x11001x0x11xxxxx0001xxxxxxxxxxxx + fcmla. */ +- return 1399; ++ return 1403; + } + } + } +@@ -9675,7 +9675,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x11001x0001xxxxx010xxxxxxxxxxxxx + st1b. */ +- return 1877; ++ return 1881; + } + else + { +@@ -9687,7 +9687,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0101xxxxx010xx0xxxxxxxxxx + fmlalb. */ +- return 2089; ++ return 2093; + } + else + { +@@ -9695,7 +9695,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0101xxxxx010xx1xxxxxxxxxx + fmlalt. */ +- return 2091; ++ return 2095; + } + } + else +@@ -9704,7 +9704,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x0101xxxxx010xxxxxxxxxxxxx + st1h. */ +- return 1896; ++ return 1900; + } + } + } +@@ -9718,7 +9718,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0011xxxxx010xxxxxxxxxxxxx + bfdot. */ +- return 2485; ++ return 2489; + } + else + { +@@ -9726,7 +9726,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x0011xxxxx010xxxxxxxxxxxxx + st1b. */ +- return 1880; ++ return 1884; + } + } + else +@@ -9739,7 +9739,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0111xxxxx010xx0xxxxxxxxxx + bfmlalb. */ +- return 2492; ++ return 2496; + } + else + { +@@ -9747,7 +9747,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0111xxxxx010xx1xxxxxxxxxx + bfmlalt. */ +- return 2491; ++ return 2495; + } + } + else +@@ -9756,7 +9756,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x0111xxxxx010xxxxxxxxxxxxx + st1h. */ +- return 1901; ++ return 1905; + } + } + } +@@ -9774,7 +9774,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0x01xxxxx1x0xx0xxxxxxxxxx + fmlalb. */ +- return 2090; ++ return 2094; + } + else + { +@@ -9782,7 +9782,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0x01xxxxx1x0xx1xxxxxxxxxx + fmlalt. */ +- return 2092; ++ return 2096; + } + } + else +@@ -9791,7 +9791,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x0x01xxxxx1x0xxxxxxxxxxxxx + st1h. */ +- return 1897; ++ return 1901; + } + } + else +@@ -9802,7 +9802,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x11001x0011xxxxx1x0xxxxxxxxxxxxx + bfdot. */ +- return 2484; ++ return 2488; + } + else + { +@@ -9814,7 +9814,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0111xxxxx1x0xx0xxxxxxxxxx + bfmlalb. */ +- return 2490; ++ return 2494; + } + else + { +@@ -9822,7 +9822,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0111xxxxx1x0xx1xxxxxxxxxx + bfmlalt. */ +- return 2489; ++ return 2493; + } + } + else +@@ -9831,7 +9831,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x0111xxxxx1x0xxxxxxxxxxxxx + st1h. */ +- return 1902; ++ return 1906; + } + } + } +@@ -9850,7 +9850,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x0xx1xxxxxxx1xxxxxxxx0xxxx + cmplo. */ +- return 1346; ++ return 1350; + } + else + { +@@ -9858,7 +9858,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x0xx1xxxxxxx1xxxxxxxx1xxxx + cmpls. */ +- return 1348; ++ return 1352; + } + } + else +@@ -9873,7 +9873,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x00x1xxxxx001xxxxxxxxxxxxx + ld1rob. */ +- return 2468; ++ return 2472; + } + else + { +@@ -9881,7 +9881,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x01x1xxxxx001xxxxxxxxxxxxx + ld1roh. */ +- return 2469; ++ return 2473; + } + } + else +@@ -9896,7 +9896,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x00010xxxx101xxxxxxxxxxxxx + ld1b. */ +- return 1520; ++ return 1524; + } + else + { +@@ -9904,7 +9904,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x01010xxxx101xxxxxxxxxxxxx + ld1h. */ +- return 1541; ++ return 1545; + } + } + else +@@ -9915,7 +9915,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x00110xxxx101xxxxxxxxxxxxx + ld1b. */ +- return 1522; ++ return 1526; + } + else + { +@@ -9923,7 +9923,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x01110xxxx101xxxxxxxxxxxxx + ld1h. */ +- return 1543; ++ return 1547; + } + } + } +@@ -9937,7 +9937,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x00011xxxx101xxxxxxxxxxxxx + ldnf1b. */ +- return 1712; ++ return 1716; + } + else + { +@@ -9945,7 +9945,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x01011xxxx101xxxxxxxxxxxxx + ldnf1h. */ +- return 1716; ++ return 1720; + } + } + else +@@ -9956,7 +9956,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x00111xxxx101xxxxxxxxxxxxx + ldnf1b. */ +- return 1714; ++ return 1718; + } + else + { +@@ -9964,7 +9964,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x01111xxxx101xxxxxxxxxxxxx + ldnf1h. */ +- return 1718; ++ return 1722; + } + } + } +@@ -9982,7 +9982,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x0001xxxxx011xxxxxxxxxxxxx + ldff1b. */ +- return 1638; ++ return 1642; + } + else + { +@@ -9990,7 +9990,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x0101xxxxx011xxxxxxxxxxxxx + ldff1h. */ +- return 1657; ++ return 1661; + } + } + else +@@ -10001,7 +10001,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x0011xxxxx011xxxxxxxxxxxxx + ldff1b. */ +- return 1642; ++ return 1646; + } + else + { +@@ -10009,7 +10009,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x0111xxxxx011xxxxxxxxxxxxx + ldff1h. */ +- return 1661; ++ return 1665; + } + } + } +@@ -10023,7 +10023,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x0001xxxxx111xxxxxxxxxxxxx + ld2b. */ +- return 1612; ++ return 1616; + } + else + { +@@ -10031,7 +10031,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x0101xxxxx111xxxxxxxxxxxxx + ld2h. */ +- return 1616; ++ return 1620; + } + } + else +@@ -10042,7 +10042,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x0011xxxxx111xxxxxxxxxxxxx + ld4b. */ +- return 1628; ++ return 1632; + } + else + { +@@ -10050,7 +10050,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x0111xxxxx111xxxxxxxxxxxxx + ld4h. */ +- return 1632; ++ return 1636; + } + } + } +@@ -10069,7 +10069,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x11001x00x1xxxxx001xxxxxxxxxxxxx + fmul. */ +- return 1461; ++ return 1465; + } + else + { +@@ -10079,7 +10079,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x11001x0101xxxxx001xxxxxxxxxxxxx + fmul. */ +- return 1462; ++ return 1466; + } + else + { +@@ -10087,7 +10087,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x11001x0111xxxxx001xxxxxxxxxxxxx + fmul. */ +- return 1463; ++ return 1467; + } + } + } +@@ -10103,7 +10103,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0x01xxxxx101xx0xxxxxxxxxx + fmlslb. */ +- return 2094; ++ return 2098; + } + else + { +@@ -10111,7 +10111,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0x01xxxxx101xx1xxxxxxxxxx + fmlslt. */ +- return 2096; ++ return 2100; + } + } + else +@@ -10120,7 +10120,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x0x01xxxxx101xxxxxxxxxxxxx + st1h. */ +- return 1898; ++ return 1902; + } + } + else +@@ -10131,7 +10131,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x11001x0011xxxxx101xxxxxxxxxxxxx + st1b. */ +- return 1885; ++ return 1889; + } + else + { +@@ -10139,7 +10139,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x11001x0111xxxxx101xxxxxxxxxxxxx + st1h. */ +- return 1906; ++ return 1910; + } + } + } +@@ -10156,7 +10156,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x11001x0001xxxxx011xxxxxxxxxxxxx + st2b. */ +- return 1920; ++ return 1924; + } + else + { +@@ -10168,7 +10168,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0101xxxxx011xx0xxxxxxxxxx + fmlslb. */ +- return 2093; ++ return 2097; + } + else + { +@@ -10176,7 +10176,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0101xxxxx011xx1xxxxxxxxxx + fmlslt. */ +- return 2095; ++ return 2099; + } + } + else +@@ -10185,7 +10185,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x0101xxxxx011xxxxxxxxxxxxx + st2h. */ +- return 1924; ++ return 1928; + } + } + } +@@ -10197,7 +10197,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x11001x0011xxxxx011xxxxxxxxxxxxx + st4b. */ +- return 1936; ++ return 1940; + } + else + { +@@ -10205,7 +10205,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x11001x0111xxxxx011xxxxxxxxxxxxx + st4h. */ +- return 1940; ++ return 1944; + } + } + } +@@ -10221,7 +10221,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x11001x00010xxxx111xxxxxxxxxxxxx + st1b. */ +- return 1882; ++ return 1886; + } + else + { +@@ -10229,7 +10229,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x11001x00011xxxx111xxxxxxxxxxxxx + st2b. */ +- return 1921; ++ return 1925; + } + } + else +@@ -10240,7 +10240,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0101xxxxx111xxxxxxxxxxxxx + fmmla. */ +- return 2462; ++ return 2466; + } + else + { +@@ -10250,7 +10250,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x01010xxxx111xxxxxxxxxxxxx + st1h. */ +- return 1903; ++ return 1907; + } + else + { +@@ -10258,7 +10258,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x01011xxxx111xxxxxxxxxxxxx + st2h. */ +- return 1925; ++ return 1929; + } + } + } +@@ -10273,7 +10273,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0011xxxxx111xxxxxxxxxxxxx + bfmmla. */ +- return 2486; ++ return 2490; + } + else + { +@@ -10283,7 +10283,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x00110xxxx111xxxxxxxxxxxxx + st1b. */ +- return 1886; ++ return 1890; + } + else + { +@@ -10291,7 +10291,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x00111xxxx111xxxxxxxxxxxxx + st4b. */ +- return 1937; ++ return 1941; + } + } + } +@@ -10303,7 +10303,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0111xxxxx111xxxxxxxxxxxxx + fmmla. */ +- return 2463; ++ return 2467; + } + else + { +@@ -10313,7 +10313,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x01110xxxx111xxxxxxxxxxxxx + st1h. */ +- return 1907; ++ return 1911; + } + else + { +@@ -10321,7 +10321,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x01111xxxx111xxxxxxxxxxxxx + st4h. */ +- return 1941; ++ return 1945; + } + } + } +@@ -10353,7 +10353,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x10000xxxxxxxxxxxxxxxxxxxx + orr. */ +- return 1766; ++ return 1770; + } + else + { +@@ -10361,7 +10361,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x11000xxxxxxxxxxxxxxxxxxxx + and. */ +- return 1294; ++ return 1298; + } + } + else +@@ -10372,7 +10372,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x10100xxxxxxxxxxxxxxxxxxxx + eor. */ +- return 1381; ++ return 1385; + } + else + { +@@ -10380,7 +10380,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x11100xxxxxxxxxxxxxxxxxxxx + dupm. */ +- return 1379; ++ return 1383; + } + } + } +@@ -10392,7 +10392,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1xx01xxxx0xxxxxxxxxxxxxxx + cpy. */ +- return 1364; ++ return 1368; + } + else + { +@@ -10400,7 +10400,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1xx01xxxx1xxxxxxxxxxxxxxx + fcpy. */ +- return 1411; ++ return 1415; + } + } + } +@@ -10420,7 +10420,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1001xxxxx000xxxxxxxxxxxxx + ext. */ +- return 1386; ++ return 1390; + } + else + { +@@ -10432,7 +10432,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1101xxxxx000x00xxxxxxxxxx + zip1. */ +- return 2472; ++ return 2476; + } + else + { +@@ -10442,7 +10442,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1101xxxxx000010xxxxxxxxxx + uzp1. */ +- return 2474; ++ return 2478; + } + else + { +@@ -10450,7 +10450,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1101xxxxx000110xxxxxxxxxx + trn1. */ +- return 2476; ++ return 2480; + } + } + } +@@ -10462,7 +10462,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1101xxxxx000x01xxxxxxxxxx + zip2. */ +- return 2473; ++ return 2477; + } + else + { +@@ -10472,7 +10472,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1101xxxxx000011xxxxxxxxxx + uzp2. */ +- return 2475; ++ return 2479; + } + else + { +@@ -10480,7 +10480,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1101xxxxx000111xxxxxxxxxx + trn2. */ +- return 2477; ++ return 2481; + } + } + } +@@ -10492,7 +10492,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1x11xxxxx000xxxxxxxxxxxxx + ext. */ +- return 2076; ++ return 2080; + } + } + else +@@ -10509,7 +10509,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1xx1x0000100xxxxxxxxxxxxx + cpy. */ +- return 1362; ++ return 1366; + } + else + { +@@ -10517,7 +10517,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1xx1x1000100xxxxxxxxxxxxx + clasta. */ +- return 1320; ++ return 1324; + } + } + else +@@ -10528,7 +10528,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1xx1x0100100xxxxxxxxxxxxx + revb. */ +- return 1814; ++ return 1818; + } + else + { +@@ -10536,7 +10536,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1xx1x1100100xxxxxxxxxxxxx + splice. */ +- return 1841; ++ return 1845; + } + } + } +@@ -10550,7 +10550,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1xx1x0010100xxxxxxxxxxxxx + lasta. */ +- return 1508; ++ return 1512; + } + else + { +@@ -10558,7 +10558,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1xx1x1010100xxxxxxxxxxxxx + clasta. */ +- return 1321; ++ return 1325; + } + } + else +@@ -10567,7 +10567,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1xx1xx110100xxxxxxxxxxxxx + revw. */ +- return 1816; ++ return 1820; + } + } + } +@@ -10583,7 +10583,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1xx1x0001100xxxxxxxxxxxxx + compact. */ +- return 1361; ++ return 1365; + } + else + { +@@ -10591,7 +10591,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1xx1x1001100xxxxxxxxxxxxx + clastb. */ +- return 1323; ++ return 1327; + } + } + else +@@ -10602,7 +10602,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1xx1x0101100xxxxxxxxxxxxx + revh. */ +- return 1815; ++ return 1819; + } + else + { +@@ -10610,7 +10610,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1xx1x1101100xxxxxxxxxxxxx + splice. */ +- return 2171; ++ return 2175; + } + } + } +@@ -10624,7 +10624,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1xx1x0011100xxxxxxxxxxxxx + lastb. */ +- return 1510; ++ return 1514; + } + else + { +@@ -10632,7 +10632,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1xx1x1011100xxxxxxxxxxxxx + clastb. */ +- return 1324; ++ return 1328; + } + } + else +@@ -10641,7 +10641,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1xx1xx111100xxxxxxxxxxxxx + rbit. */ +- return 1807; ++ return 1811; + } + } + } +@@ -10661,7 +10661,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1xx1xxxxx001000xxxxxxxxxx + dup. */ +- return 1377; ++ return 1381; + } + else + { +@@ -10669,7 +10669,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1xx1xxxxx001100xxxxxxxxxx + tbl. */ +- return 1964; ++ return 1968; + } + } + else +@@ -10680,7 +10680,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1xx1xxxxx001010xxxxxxxxxx + tbl. */ +- return 2260; ++ return 2264; + } + else + { +@@ -10698,7 +10698,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1xx100000001110xxxxxxxxxx + dup. */ +- return 1376; ++ return 1380; + } + else + { +@@ -10706,7 +10706,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1xx110000001110xxxxxxxxxx + sunpklo. */ +- return 1960; ++ return 1964; + } + } + else +@@ -10715,7 +10715,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1xx1x1000001110xxxxxxxxxx + rev. */ +- return 1813; ++ return 1817; + } + } + else +@@ -10726,7 +10726,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1xx10x100001110xxxxxxxxxx + insr. */ +- return 1505; ++ return 1509; + } + else + { +@@ -10734,7 +10734,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1xx11x100001110xxxxxxxxxx + insr. */ +- return 1506; ++ return 1510; + } + } + } +@@ -10744,7 +10744,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1xx1xxx10001110xxxxxxxxxx + uunpklo. */ +- return 2023; ++ return 2027; + } + } + else +@@ -10755,7 +10755,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1xx1xxx01001110xxxxxxxxxx + sunpkhi. */ +- return 1959; ++ return 1963; + } + else + { +@@ -10763,7 +10763,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1xx1xxx11001110xxxxxxxxxx + uunpkhi. */ +- return 2022; ++ return 2026; + } + } + } +@@ -10775,7 +10775,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1xx1xxxxx001xx1xxxxxxxxxx + tbx. */ +- return 2261; ++ return 2265; + } + } + else +@@ -10790,7 +10790,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1xx100xx0101xxxxxxxxxxxxx + lasta. */ +- return 1507; ++ return 1511; + } + else + { +@@ -10798,7 +10798,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1xx110xx0101xxxxxxxxxxxxx + clasta. */ +- return 1322; ++ return 1326; + } + } + else +@@ -10807,7 +10807,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1xx1x1xx0101xxxxxxxxxxxxx + cpy. */ +- return 1363; ++ return 1367; + } + } + else +@@ -10818,7 +10818,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1xx10xxx1101xxxxxxxxxxxxx + lastb. */ +- return 1509; ++ return 1513; + } + else + { +@@ -10826,7 +10826,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1xx11xxx1101xxxxxxxxxxxxx + clastb. */ +- return 1325; ++ return 1329; + } + } + } +@@ -10850,7 +10850,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1xx10xxxx010000xxxxxxxxxx + zip1. */ +- return 2040; ++ return 2044; + } + else + { +@@ -10862,7 +10862,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1xx11x0x0010000xxxxxxxxxx + punpklo. */ +- return 1806; ++ return 1810; + } + else + { +@@ -10870,7 +10870,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1xx11x1x0010000xxxxxxxxxx + rev. */ +- return 1812; ++ return 1816; + } + } + else +@@ -10879,7 +10879,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1xx11xxx1010000xxxxxxxxxx + punpkhi. */ +- return 1805; ++ return 1809; + } + } + } +@@ -10889,7 +10889,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1xx1xxxxx011000xxxxxxxxxx + zip1. */ +- return 2041; ++ return 2045; + } + } + else +@@ -10900,7 +10900,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1xx1xxxxx010100xxxxxxxxxx + trn1. */ +- return 1965; ++ return 1969; + } + else + { +@@ -10908,7 +10908,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1xx1xxxxx011100xxxxxxxxxx + trn1. */ +- return 1966; ++ return 1970; + } + } + } +@@ -10920,7 +10920,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1xx1xxxxx010x10xxxxxxxxxx + uzp1. */ +- return 2027; ++ return 2031; + } + else + { +@@ -10928,7 +10928,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1xx1xxxxx011x10xxxxxxxxxx + uzp1. */ +- return 2028; ++ return 2032; + } + } + } +@@ -10944,7 +10944,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1xx1xxxxx010001xxxxxxxxxx + zip2. */ +- return 2042; ++ return 2046; + } + else + { +@@ -10952,7 +10952,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1xx1xxxxx011001xxxxxxxxxx + zip2. */ +- return 2043; ++ return 2047; + } + } + else +@@ -10963,7 +10963,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1xx1xxxxx010101xxxxxxxxxx + trn2. */ +- return 1967; ++ return 1971; + } + else + { +@@ -10971,7 +10971,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1xx1xxxxx011101xxxxxxxxxx + trn2. */ +- return 1968; ++ return 1972; + } + } + } +@@ -10983,7 +10983,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1xx1xxxxx010x11xxxxxxxxxx + uzp2. */ +- return 2029; ++ return 2033; + } + else + { +@@ -10991,7 +10991,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1xx1xxxxx011x11xxxxxxxxxx + uzp2. */ +- return 2030; ++ return 2034; + } + } + } +@@ -11002,7 +11002,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1xx1xxxxx11xxxxxxxxxxxxxx + sel. */ +- return 1831; ++ return 1835; + } + } + } +@@ -11021,7 +11021,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x1x0xxxxxx000xxxxxxxxxxxxx + ldr. */ +- return 1735; ++ return 1739; + } + else + { +@@ -11029,7 +11029,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x1x1xxxxxx000xxxxxxxxxxxxx + prfb. */ +- return 1779; ++ return 1783; + } + } + else +@@ -11040,7 +11040,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x10xxxxxxx100xxxxxxxxxxxxx + ld1rsh. */ +- return 1564; ++ return 1568; + } + else + { +@@ -11048,7 +11048,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x11xxxxxxx100xxxxxxxxxxxxx + ld1rsb. */ +- return 1561; ++ return 1565; + } + } + } +@@ -11064,7 +11064,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x10x0xxxxx010xxxxxxxxxxxxx + ld1w. */ +- return 1599; ++ return 1603; + } + else + { +@@ -11072,7 +11072,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x10x1xxxxx010xxxxxxxxxxxxx + ld1w. */ +- return 1600; ++ return 1604; + } + } + else +@@ -11083,7 +11083,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x110xxxxxx010xxxxxxxxxxxxx + ldr. */ +- return 1736; ++ return 1740; + } + else + { +@@ -11091,7 +11091,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x111xxxxxx010xxxxxxxxxxxxx + prfw. */ +- return 1800; ++ return 1804; + } + } + } +@@ -11107,7 +11107,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x1000xxxxx110xxxxxxxxxxxxx + prfw. */ +- return 1796; ++ return 1800; + } + else + { +@@ -11115,7 +11115,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x1100xxxxx110xxxxxxxxxxxxx + prfd. */ +- return 1782; ++ return 1786; + } + } + else +@@ -11124,7 +11124,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x1x01xxxxx110xxxxxxxxxxxxx + ld1w. */ +- return 1607; ++ return 1611; + } + } + else +@@ -11135,7 +11135,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x101xxxxxx110xxxxxxxxxxxxx + ld1rw. */ +- return 1567; ++ return 1571; + } + else + { +@@ -11143,7 +11143,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x111xxxxxx110xxxxxxxxxxxxx + ld1rsb. */ +- return 1563; ++ return 1567; + } + } + } +@@ -11159,7 +11159,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x1xxxxxxxx001xxxxxxxxxxxxx + prfh. */ +- return 1793; ++ return 1797; + } + else + { +@@ -11169,7 +11169,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x1x0xxxxxx101xxxxxxxxxxxxx + ldnt1w. */ +- return 2107; ++ return 2111; + } + else + { +@@ -11179,7 +11179,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x101xxxxxx101xxxxxxxxxxxxx + ld1rsh. */ +- return 1565; ++ return 1569; + } + else + { +@@ -11187,7 +11187,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x111xxxxxx101xxxxxxxxxxxxx + ld1rsb. */ +- return 1562; ++ return 1566; + } + } + } +@@ -11204,7 +11204,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x10x0xxxxx011xxxxxxxxxxxxx + ldff1w. */ +- return 1699; ++ return 1703; + } + else + { +@@ -11212,7 +11212,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x10x1xxxxx011xxxxxxxxxxxxx + ldff1w. */ +- return 1700; ++ return 1704; + } + } + else +@@ -11221,7 +11221,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x11xxxxxxx011xxxxxxxxxxxxx + prfd. */ +- return 1786; ++ return 1790; + } + } + else +@@ -11236,7 +11236,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x1000xxxxx111xxxxxxxxxxxxx + prfw. */ +- return 1799; ++ return 1803; + } + else + { +@@ -11244,7 +11244,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x1100xxxxx111xxxxxxxxxxxxx + prfd. */ +- return 1785; ++ return 1789; + } + } + else +@@ -11253,7 +11253,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x1x01xxxxx111xxxxxxxxxxxxx + ldff1w. */ +- return 1709; ++ return 1713; + } + } + else +@@ -11264,7 +11264,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x101xxxxxx111xxxxxxxxxxxxx + ld1rw. */ +- return 1568; ++ return 1572; + } + else + { +@@ -11272,7 +11272,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 100001x111xxxxxx111xxxxxxxxxxxxx + ld1rd. */ +- return 1549; ++ return 1553; + } + } + } +@@ -11302,7 +11302,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx0xxxxx000000xxxxxxxxxx + saddlb. */ +- return 2137; ++ return 2141; + } + else + { +@@ -11310,7 +11310,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx0xxxxx000100xxxxxxxxxx + ssublb. */ +- return 2244; ++ return 2248; + } + } + else +@@ -11321,7 +11321,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx0xxxxx000010xxxxxxxxxx + uaddlb. */ +- return 2268; ++ return 2272; + } + else + { +@@ -11329,7 +11329,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx0xxxxx000110xxxxxxxxxx + usublb. */ +- return 2321; ++ return 2325; + } + } + } +@@ -11343,7 +11343,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx0xxxxx000001xxxxxxxxxx + saddlt. */ +- return 2139; ++ return 2143; + } + else + { +@@ -11351,7 +11351,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx0xxxxx000101xxxxxxxxxx + ssublt. */ +- return 2246; ++ return 2250; + } + } + else +@@ -11362,7 +11362,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx0xxxxx000011xxxxxxxxxx + uaddlt. */ +- return 2269; ++ return 2273; + } + else + { +@@ -11370,7 +11370,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx0xxxxx000111xxxxxxxxxx + usublt. */ +- return 2322; ++ return 2326; + } + } + } +@@ -11381,7 +11381,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 110001x1xx0xxxxx000xxxxxxxxxxxxx + ld1sw. */ +- return 1593; ++ return 1597; + } + } + else +@@ -11398,7 +11398,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx1xxxxx000000xxxxxxxxxx + sqshrunb. */ +- return 2227; ++ return 2231; + } + else + { +@@ -11406,7 +11406,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx1xxxxx000100xxxxxxxxxx + shrnb. */ +- return 2145; ++ return 2149; + } + } + else +@@ -11417,7 +11417,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx1xxxxx000010xxxxxxxxxx + sqrshrunb. */ +- return 2219; ++ return 2223; + } + else + { +@@ -11425,7 +11425,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx1xxxxx000110xxxxxxxxxx + rshrnb. */ +- return 2127; ++ return 2131; + } + } + } +@@ -11439,7 +11439,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx1xxxxx000001xxxxxxxxxx + sqshrunt. */ +- return 2228; ++ return 2232; + } + else + { +@@ -11447,7 +11447,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx1xxxxx000101xxxxxxxxxx + shrnt. */ +- return 2146; ++ return 2150; + } + } + else +@@ -11458,7 +11458,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx1xxxxx000011xxxxxxxxxx + sqrshrunt. */ +- return 2220; ++ return 2224; + } + else + { +@@ -11466,7 +11466,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx1xxxxx000111xxxxxxxxxx + rshrnt. */ +- return 2128; ++ return 2132; + } + } + } +@@ -11477,7 +11477,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 110001x1xx1xxxxx000xxxxxxxxxxxxx + ld1sw. */ +- return 1594; ++ return 1598; + } + } + } +@@ -11497,7 +11497,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx0xxxxx100000xxxxxxxxxx + saddlbt. */ +- return 2138; ++ return 2142; + } + else + { +@@ -11505,7 +11505,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx0xxxxx100100xxxxxxxxxx + eorbt. */ +- return 2074; ++ return 2078; + } + } + else +@@ -11516,7 +11516,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx0xxxxx100010xxxxxxxxxx + ssublbt. */ +- return 2245; ++ return 2249; + } + else + { +@@ -11528,7 +11528,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1000xxxxx100110xxxxxxxxxx + smmla. */ +- return 2456; ++ return 2460; + } + else + { +@@ -11536,7 +11536,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1100xxxxx100110xxxxxxxxxx + usmmla. */ +- return 2458; ++ return 2462; + } + } + else +@@ -11545,7 +11545,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1x10xxxxx100110xxxxxxxxxx + ummla. */ +- return 2457; ++ return 2461; + } + } + } +@@ -11558,7 +11558,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx0xxxxx100x01xxxxxxxxxx + eortb. */ +- return 2075; ++ return 2079; + } + else + { +@@ -11566,7 +11566,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx0xxxxx100x11xxxxxxxxxx + ssubltb. */ +- return 2247; ++ return 2251; + } + } + } +@@ -11578,7 +11578,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 110001x1x00xxxxx100xxxxxxxxxxxxx + ldnt1sw. */ +- return 2106; ++ return 2110; + } + else + { +@@ -11586,7 +11586,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 110001x1x10xxxxx100xxxxxxxxxxxxx + ld1sw. */ +- return 1595; ++ return 1599; + } + } + } +@@ -11600,7 +11600,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx1xxxxx100xxxxxxxx0xxxx + match. */ +- return 2109; ++ return 2113; + } + else + { +@@ -11608,7 +11608,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx1xxxxx100xxxxxxxx1xxxx + nmatch. */ +- return 2121; ++ return 2125; + } + } + else +@@ -11619,7 +11619,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 110001x1x01xxxxx100xxxxxxxxxxxxx + ld1sw. */ +- return 1598; ++ return 1602; + } + else + { +@@ -11627,7 +11627,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 110001x1x11xxxxx100xxxxxxxxxxxxx + ld1sw. */ +- return 1596; ++ return 1600; + } + } + } +@@ -11651,7 +11651,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx0xxxxx010000xxxxxxxxxx + saddwb. */ +- return 2140; ++ return 2144; + } + else + { +@@ -11659,7 +11659,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx0xxxxx010100xxxxxxxxxx + ssubwb. */ +- return 2248; ++ return 2252; + } + } + else +@@ -11670,7 +11670,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx0xxxxx010010xxxxxxxxxx + uaddwb. */ +- return 2270; ++ return 2274; + } + else + { +@@ -11678,7 +11678,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx0xxxxx010110xxxxxxxxxx + usubwb. */ +- return 2323; ++ return 2327; + } + } + } +@@ -11692,7 +11692,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx0xxxxx010001xxxxxxxxxx + saddwt. */ +- return 2141; ++ return 2145; + } + else + { +@@ -11700,7 +11700,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx0xxxxx010101xxxxxxxxxx + ssubwt. */ +- return 2249; ++ return 2253; + } + } + else +@@ -11711,7 +11711,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx0xxxxx010011xxxxxxxxxx + uaddwt. */ +- return 2271; ++ return 2275; + } + else + { +@@ -11719,7 +11719,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx0xxxxx010111xxxxxxxxxx + usubwt. */ +- return 2324; ++ return 2328; + } + } + } +@@ -11732,7 +11732,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 110001x10x0xxxxx010xxxxxxxxxxxxx + ld1w. */ +- return 1603; ++ return 1607; + } + else + { +@@ -11740,7 +11740,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 110001x11x0xxxxx010xxxxxxxxxxxxx + ld1d. */ +- return 1525; ++ return 1529; + } + } + } +@@ -11760,7 +11760,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x10x1xxxxx010000xxxxxxxxxx + sqxtnb. */ +- return 2231; ++ return 2235; + } + else + { +@@ -11768,7 +11768,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x10x1xxxxx010100xxxxxxxxxx + sqxtunb. */ +- return 2233; ++ return 2237; + } + } + else +@@ -11777,7 +11777,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x10x1xxxxx010x10xxxxxxxxxx + uqxtnb. */ +- return 2308; ++ return 2312; + } + } + else +@@ -11790,7 +11790,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x10x1xxxxx010001xxxxxxxxxx + sqxtnt. */ +- return 2232; ++ return 2236; + } + else + { +@@ -11798,7 +11798,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x10x1xxxxx010101xxxxxxxxxx + sqxtunt. */ +- return 2234; ++ return 2238; + } + } + else +@@ -11807,7 +11807,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x10x1xxxxx010x11xxxxxxxxxx + uqxtnt. */ +- return 2309; ++ return 2313; + } + } + } +@@ -11817,7 +11817,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 110001x10x1xxxxx010xxxxxxxxxxxxx + ld1w. */ +- return 1604; ++ return 1608; + } + } + else +@@ -11826,7 +11826,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x10001x11x1xxxxx010xxxxxxxxxxxxx + ld1d. */ +- return 1526; ++ return 1530; + } + } + } +@@ -11846,7 +11846,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx0xxxxx110000xxxxxxxxxx + sabalb. */ +- return 2132; ++ return 2136; + } + else + { +@@ -11856,7 +11856,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x10x0xxxxx110100xxxxxxxxxx + adclb. */ +- return 2057; ++ return 2061; + } + else + { +@@ -11864,7 +11864,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x11x0xxxxx110100xxxxxxxxxx + sbclb. */ +- return 2142; ++ return 2146; + } + } + } +@@ -11876,7 +11876,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx0xxxxx110001xxxxxxxxxx + sabalt. */ +- return 2133; ++ return 2137; + } + else + { +@@ -11886,7 +11886,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x10x0xxxxx110101xxxxxxxxxx + adclt. */ +- return 2058; ++ return 2062; + } + else + { +@@ -11894,7 +11894,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x11x0xxxxx110101xxxxxxxxxx + sbclt. */ +- return 2143; ++ return 2147; + } + } + } +@@ -11909,7 +11909,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx0xxxxx110010xxxxxxxxxx + uabalb. */ +- return 2263; ++ return 2267; + } + else + { +@@ -11917,7 +11917,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx0xxxxx110011xxxxxxxxxx + uabalt. */ +- return 2264; ++ return 2268; + } + } + else +@@ -11928,7 +11928,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx0xxxx011011xxxxxxxxxxx + cadd. */ +- return 2066; ++ return 2070; + } + else + { +@@ -11936,7 +11936,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx0xxxx111011xxxxxxxxxxx + sqcadd. */ +- return 2174; ++ return 2178; + } + } + } +@@ -11951,7 +11951,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 110001x1000xxxxx110xxxxxxxxxxxxx + ldnt1w. */ +- return 2108; ++ return 2112; + } + else + { +@@ -11959,7 +11959,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 110001x1100xxxxx110xxxxxxxxxxxxx + ldnt1d. */ +- return 2101; ++ return 2105; + } + } + else +@@ -11970,7 +11970,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 110001x1010xxxxx110xxxxxxxxxxxxx + ld1w. */ +- return 1605; ++ return 1609; + } + else + { +@@ -11978,7 +11978,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 110001x1110xxxxx110xxxxxxxxxxxxx + ld1d. */ +- return 1527; ++ return 1531; + } + } + } +@@ -11993,7 +11993,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x10001x1001xxxxx110xxxxxxxxxxxxx + ld1w. */ +- return 1610; ++ return 1614; + } + else + { +@@ -12001,7 +12001,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x10001x1011xxxxx110xxxxxxxxxxxxx + ld1w. */ +- return 1606; ++ return 1610; + } + } + else +@@ -12012,7 +12012,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x11x1xxxxx110xxxxxxxxxxxxx + histcnt. */ +- return 2097; ++ return 2101; + } + else + { +@@ -12022,7 +12022,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 110001x1101xxxxx110xxxxxxxxxxxxx + ld1d. */ +- return 1530; ++ return 1534; + } + else + { +@@ -12030,7 +12030,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 110001x1111xxxxx110xxxxxxxxxxxxx + ld1d. */ +- return 1528; ++ return 1532; + } + } + } +@@ -12056,7 +12056,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx0xxxxx001x00xxxxxxxxxx + sabdlb. */ +- return 2134; ++ return 2138; + } + else + { +@@ -12064,7 +12064,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx0xxxxx001x10xxxxxxxxxx + uabdlb. */ +- return 2265; ++ return 2269; + } + } + else +@@ -12075,7 +12075,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx0xxxxx001x01xxxxxxxxxx + sabdlt. */ +- return 2135; ++ return 2139; + } + else + { +@@ -12083,7 +12083,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx0xxxxx001x11xxxxxxxxxx + uabdlt. */ +- return 2266; ++ return 2270; + } + } + } +@@ -12093,7 +12093,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 110001x1xx0xxxxx001xxxxxxxxxxxxx + ldff1sw. */ +- return 1694; ++ return 1698; + } + } + else +@@ -12110,7 +12110,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx1xxxxx001000xxxxxxxxxx + sqshrnb. */ +- return 2225; ++ return 2229; + } + else + { +@@ -12118,7 +12118,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx1xxxxx001100xxxxxxxxxx + uqshrnb. */ +- return 2304; ++ return 2308; + } + } + else +@@ -12129,7 +12129,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx1xxxxx001010xxxxxxxxxx + sqrshrnb. */ +- return 2217; ++ return 2221; + } + else + { +@@ -12137,7 +12137,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx1xxxxx001110xxxxxxxxxx + uqrshrnb. */ +- return 2299; ++ return 2303; + } + } + } +@@ -12151,7 +12151,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx1xxxxx001001xxxxxxxxxx + sqshrnt. */ +- return 2226; ++ return 2230; + } + else + { +@@ -12159,7 +12159,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx1xxxxx001101xxxxxxxxxx + uqshrnt. */ +- return 2305; ++ return 2309; + } + } + else +@@ -12170,7 +12170,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx1xxxxx001011xxxxxxxxxx + sqrshrnt. */ +- return 2218; ++ return 2222; + } + else + { +@@ -12178,7 +12178,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx1xxxxx001111xxxxxxxxxx + uqrshrnt. */ +- return 2300; ++ return 2304; + } + } + } +@@ -12189,7 +12189,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 110001x1xx1xxxxx001xxxxxxxxxxxxx + ldff1sw. */ +- return 1695; ++ return 1699; + } + } + } +@@ -12209,7 +12209,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx0xxxxx101000xxxxxxxxxx + sshllb. */ +- return 2241; ++ return 2245; + } + else + { +@@ -12217,7 +12217,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx0xxxxx101100xxxxxxxxxx + bext. */ +- return 2346; ++ return 2350; + } + } + else +@@ -12228,7 +12228,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx0xxxxx101010xxxxxxxxxx + ushllb. */ +- return 2317; ++ return 2321; + } + else + { +@@ -12236,7 +12236,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx0xxxxx101110xxxxxxxxxx + bgrp. */ +- return 2347; ++ return 2351; + } + } + } +@@ -12250,7 +12250,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx0xxxxx101001xxxxxxxxxx + sshllt. */ +- return 2242; ++ return 2246; + } + else + { +@@ -12258,7 +12258,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx0xxxxx101101xxxxxxxxxx + bdep. */ +- return 2345; ++ return 2349; + } + } + else +@@ -12267,7 +12267,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx0xxxxx101x11xxxxxxxxxx + ushllt. */ +- return 2318; ++ return 2322; + } + } + } +@@ -12277,7 +12277,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 110001x1xx0xxxxx101xxxxxxxxxxxxx + ldff1sw. */ +- return 1696; ++ return 1700; + } + } + else +@@ -12290,7 +12290,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1x01xxxxx101xxxxxxxxxxxxx + histseg. */ +- return 2098; ++ return 2102; + } + else + { +@@ -12298,7 +12298,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 110001x1x01xxxxx101xxxxxxxxxxxxx + ldff1sw. */ +- return 1698; ++ return 1702; + } + } + else +@@ -12307,7 +12307,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x10001x1x11xxxxx101xxxxxxxxxxxxx + ldff1sw. */ +- return 1697; ++ return 1701; + } + } + } +@@ -12330,7 +12330,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx0xxxxx011000xxxxxxxxxx + sqdmullb. */ +- return 2195; ++ return 2199; + } + else + { +@@ -12338,7 +12338,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx0xxxxx011100xxxxxxxxxx + smullb. */ +- return 2167; ++ return 2171; + } + } + else +@@ -12351,7 +12351,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1x00xxxxx011010xxxxxxxxxx + pmullb. */ +- return 2342; ++ return 2346; + } + else + { +@@ -12359,7 +12359,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1x10xxxxx011010xxxxxxxxxx + pmullb. */ +- return 2123; ++ return 2127; + } + } + else +@@ -12368,7 +12368,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx0xxxxx011110xxxxxxxxxx + umullb. */ +- return 2292; ++ return 2296; + } + } + } +@@ -12382,7 +12382,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx0xxxxx011001xxxxxxxxxx + sqdmullt. */ +- return 2198; ++ return 2202; + } + else + { +@@ -12390,7 +12390,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx0xxxxx011101xxxxxxxxxx + smullt. */ +- return 2170; ++ return 2174; + } + } + else +@@ -12403,7 +12403,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1x00xxxxx011011xxxxxxxxxx + pmullt. */ +- return 2343; ++ return 2347; + } + else + { +@@ -12411,7 +12411,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1x10xxxxx011011xxxxxxxxxx + pmullt. */ +- return 2124; ++ return 2128; + } + } + else +@@ -12420,7 +12420,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx0xxxxx011111xxxxxxxxxx + umullt. */ +- return 2295; ++ return 2299; + } + } + } +@@ -12433,7 +12433,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 110001x10x0xxxxx011xxxxxxxxxxxxx + ldff1w. */ +- return 1705; ++ return 1709; + } + else + { +@@ -12441,7 +12441,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 110001x11x0xxxxx011xxxxxxxxxxxxx + ldff1d. */ +- return 1650; ++ return 1654; + } + } + } +@@ -12459,7 +12459,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx1xxxxx011000xxxxxxxxxx + addhnb. */ +- return 2059; ++ return 2063; + } + else + { +@@ -12467,7 +12467,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx1xxxxx011100xxxxxxxxxx + subhnb. */ +- return 2257; ++ return 2261; + } + } + else +@@ -12478,7 +12478,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx1xxxxx011010xxxxxxxxxx + raddhnb. */ +- return 2125; ++ return 2129; + } + else + { +@@ -12486,7 +12486,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx1xxxxx011110xxxxxxxxxx + rsubhnb. */ +- return 2129; ++ return 2133; + } + } + } +@@ -12500,7 +12500,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx1xxxxx011001xxxxxxxxxx + addhnt. */ +- return 2060; ++ return 2064; + } + else + { +@@ -12508,7 +12508,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx1xxxxx011101xxxxxxxxxx + subhnt. */ +- return 2258; ++ return 2262; + } + } + else +@@ -12519,7 +12519,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx1xxxxx011011xxxxxxxxxx + raddhnt. */ +- return 2126; ++ return 2130; + } + else + { +@@ -12527,7 +12527,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx1xxxxx011111xxxxxxxxxx + rsubhnt. */ +- return 2130; ++ return 2134; + } + } + } +@@ -12540,7 +12540,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 110001x10x1xxxxx011xxxxxxxxxxxxx + ldff1w. */ +- return 1706; ++ return 1710; + } + else + { +@@ -12548,7 +12548,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 110001x11x1xxxxx011xxxxxxxxxxxxx + ldff1d. */ +- return 1651; ++ return 1655; + } + } + } +@@ -12569,7 +12569,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx0xxxxx111000xxxxxxxxxx + ssra. */ +- return 2243; ++ return 2247; + } + else + { +@@ -12577,7 +12577,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx0xxxxx111100xxxxxxxxxx + sri. */ +- return 2236; ++ return 2240; + } + } + else +@@ -12588,7 +12588,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx0xxxxx111010xxxxxxxxxx + srsra. */ +- return 2240; ++ return 2244; + } + else + { +@@ -12596,7 +12596,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx0xxxxx111110xxxxxxxxxx + saba. */ +- return 2131; ++ return 2135; + } + } + } +@@ -12610,7 +12610,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx0xxxxx111001xxxxxxxxxx + usra. */ +- return 2320; ++ return 2324; + } + else + { +@@ -12618,7 +12618,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx0xxxxx111101xxxxxxxxxx + sli. */ +- return 2149; ++ return 2153; + } + } + else +@@ -12629,7 +12629,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx0xxxxx111011xxxxxxxxxx + ursra. */ +- return 2316; ++ return 2320; + } + else + { +@@ -12637,7 +12637,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1xx0xxxxx111111xxxxxxxxxx + uaba. */ +- return 2262; ++ return 2266; + } + } + } +@@ -12652,7 +12652,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 110001x1000xxxxx111xxxxxxxxxxxxx + prfw. */ +- return 1801; ++ return 1805; + } + else + { +@@ -12660,7 +12660,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 110001x1100xxxxx111xxxxxxxxxxxxx + prfd. */ +- return 1787; ++ return 1791; + } + } + else +@@ -12671,7 +12671,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 110001x1010xxxxx111xxxxxxxxxxxxx + ldff1w. */ +- return 1707; ++ return 1711; + } + else + { +@@ -12679,7 +12679,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 110001x1110xxxxx111xxxxxxxxxxxxx + ldff1d. */ +- return 1652; ++ return 1656; + } + } + } +@@ -12704,7 +12704,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1001xxx001110x0xxxxxxxxxx + aesmc. */ +- return 2341; ++ return 2345; + } + else + { +@@ -12712,7 +12712,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1001xxx101110x0xxxxxxxxxx + aese. */ +- return 2339; ++ return 2343; + } + } + else +@@ -12721,7 +12721,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1001xxxx11110x0xxxxxxxxxx + sm4e. */ +- return 2336; ++ return 2340; + } + } + else +@@ -12730,7 +12730,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1001xxxxx1111x0xxxxxxxxxx + sm4ekey. */ +- return 2337; ++ return 2341; + } + } + else +@@ -12743,7 +12743,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1001xxx0x1110x1xxxxxxxxxx + aesimc. */ +- return 2340; ++ return 2344; + } + else + { +@@ -12751,7 +12751,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1001xxx1x1110x1xxxxxxxxxx + aesd. */ +- return 2338; ++ return 2342; + } + } + else +@@ -12760,7 +12760,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1001xxxxx1111x1xxxxxxxxxx + rax1. */ +- return 2344; ++ return 2348; + } + } + } +@@ -12770,7 +12770,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 110001x1001xxxxx111xxxxxxxxxxxxx + ldff1w. */ +- return 1710; ++ return 1714; + } + } + else +@@ -12779,7 +12779,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x10001x1101xxxxx111xxxxxxxxxxxxx + ldff1d. */ +- return 1654; ++ return 1658; + } + } + else +@@ -12790,7 +12790,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x10001x1011xxxxx111xxxxxxxxxxxxx + ldff1w. */ +- return 1708; ++ return 1712; + } + else + { +@@ -12798,7 +12798,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x10001x1111xxxxx111xxxxxxxxxxxxx + ldff1d. */ +- return 1653; ++ return 1657; + } + } + } +@@ -12827,7 +12827,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx0xxxxx000xxxxxxxx0xxxx + cmpge. */ +- return 1333; ++ return 1337; + } + else + { +@@ -12835,7 +12835,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx0xxxxx000xxxxxxxx1xxxx + cmpgt. */ +- return 1336; ++ return 1340; + } + } + else +@@ -12846,7 +12846,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x10x0xxxxx000xxxxxxxxxxxxx + ld1rqw. */ +- return 1560; ++ return 1564; + } + else + { +@@ -12854,7 +12854,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x11x0xxxxx000xxxxxxxxxxxxx + ld1rqd. */ +- return 1556; ++ return 1560; + } + } + } +@@ -12874,7 +12874,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx1xxxxx000000xxxxx0xxxx + whilege. */ +- return 2325; ++ return 2329; + } + else + { +@@ -12882,7 +12882,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx1xxxxx000100xxxxx0xxxx + whilege. */ +- return 2326; ++ return 2330; + } + } + else +@@ -12893,7 +12893,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx1xxxxx000010xxxxx0xxxx + whilehs. */ +- return 2331; ++ return 2335; + } + else + { +@@ -12901,7 +12901,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx1xxxxx000110xxxxx0xxxx + whilehs. */ +- return 2332; ++ return 2336; + } + } + } +@@ -12915,7 +12915,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx1xxxxx000001xxxxx0xxxx + whilelt. */ +- return 2037; ++ return 2041; + } + else + { +@@ -12923,7 +12923,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx1xxxxx000101xxxxx0xxxx + whilelt. */ +- return 2038; ++ return 2042; + } + } + else +@@ -12934,7 +12934,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx1xxxxx000011xxxxx0xxxx + whilelo. */ +- return 2033; ++ return 2037; + } + else + { +@@ -12942,7 +12942,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx1xxxxx000111xxxxx0xxxx + whilelo. */ +- return 2034; ++ return 2038; + } + } + } +@@ -12959,7 +12959,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx1xxxxx000000xxxxx1xxxx + whilegt. */ +- return 2327; ++ return 2331; + } + else + { +@@ -12967,7 +12967,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx1xxxxx000100xxxxx1xxxx + whilegt. */ +- return 2328; ++ return 2332; + } + } + else +@@ -12978,7 +12978,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx1xxxxx000010xxxxx1xxxx + whilehi. */ +- return 2329; ++ return 2333; + } + else + { +@@ -12986,7 +12986,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx1xxxxx000110xxxxx1xxxx + whilehi. */ +- return 2330; ++ return 2334; + } + } + } +@@ -13000,7 +13000,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx1xxxxx000001xxxxx1xxxx + whilele. */ +- return 2031; ++ return 2035; + } + else + { +@@ -13008,7 +13008,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx1xxxxx000101xxxxx1xxxx + whilele. */ +- return 2032; ++ return 2036; + } + } + else +@@ -13019,7 +13019,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx1xxxxx000011xxxxx1xxxx + whilels. */ +- return 2035; ++ return 2039; + } + else + { +@@ -13027,7 +13027,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx1xxxxx000111xxxxx1xxxx + whilels. */ +- return 2036; ++ return 2040; + } + } + } +@@ -13041,7 +13041,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x10x1xxxxx000xxxxxxxxxxxxx + ld1row. */ +- return 2466; ++ return 2470; + } + else + { +@@ -13049,7 +13049,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x11x1xxxxx000xxxxxxxxxxxxx + ld1rod. */ +- return 2467; ++ return 2471; + } + } + } +@@ -13068,7 +13068,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx0xxxxx000x00xxxxxxxxxx + fadd. */ +- return 1391; ++ return 1395; + } + else + { +@@ -13078,7 +13078,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx0xxxxx000010xxxxxxxxxx + fmul. */ +- return 1458; ++ return 1462; + } + else + { +@@ -13086,7 +13086,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx0xxxxx000110xxxxxxxxxx + frecps. */ +- return 1471; ++ return 1475; + } + } + } +@@ -13098,7 +13098,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx0xxxxx000x01xxxxxxxxxx + fsub. */ +- return 1484; ++ return 1488; + } + else + { +@@ -13108,7 +13108,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx0xxxxx000011xxxxxxxxxx + ftsmul. */ +- return 1490; ++ return 1494; + } + else + { +@@ -13116,7 +13116,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx0xxxxx000111xxxxxxxxxx + frsqrts. */ +- return 1481; ++ return 1485; + } + } + } +@@ -13127,7 +13127,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx1xxxxx000xxxxxxxxxxxxx + fmla. */ +- return 1449; ++ return 1453; + } + } + else +@@ -13136,7 +13136,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x1xxxxxxxx000xxxxxxxxxxxxx + str. */ +- return 1952; ++ return 1956; + } + } + } +@@ -13154,7 +13154,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx0xxxxx001xxxxxxxx0xxxx + cmplt. */ +- return 1350; ++ return 1354; + } + else + { +@@ -13162,7 +13162,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx0xxxxx001xxxxxxxx1xxxx + cmple. */ +- return 1344; ++ return 1348; + } + } + else +@@ -13173,7 +13173,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x10x0xxxxx001xxxxxxxxxxxxx + ld1rqw. */ +- return 1559; ++ return 1563; + } + else + { +@@ -13181,7 +13181,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x11x0xxxxx001xxxxxxxxxxxxx + ld1rqd. */ +- return 1555; ++ return 1559; + } + } + } +@@ -13203,7 +13203,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx000000001xxxxxxxxxxxxx + faddv. */ +- return 1395; ++ return 1399; + } + else + { +@@ -13213,7 +13213,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx010000001xxxxxxxx0xxxx + fcmge. */ +- return 1402; ++ return 1406; + } + else + { +@@ -13221,7 +13221,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx010000001xxxxxxxx1xxxx + fcmgt. */ +- return 1404; ++ return 1408; + } + } + } +@@ -13231,7 +13231,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx0x1000001xxxxxxxxxxxxx + fadda. */ +- return 1394; ++ return 1398; + } + } + else +@@ -13240,7 +13240,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx0xx100001xxxxxxxxxxxxx + fmaxnmv. */ +- return 1441; ++ return 1445; + } + } + else +@@ -13251,7 +13251,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx0xx010001xxxxxxxxxxxxx + fcmeq. */ +- return 1400; ++ return 1404; + } + else + { +@@ -13261,7 +13261,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx0x0110001xxxxxxxxxxxxx + fmaxv. */ +- return 1442; ++ return 1446; + } + else + { +@@ -13269,7 +13269,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx0x1110001xxxxxxxxxxxxx + frecpe. */ +- return 1470; ++ return 1474; + } + } + } +@@ -13286,7 +13286,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx0xx001001xxxxxxxx0xxxx + fcmlt. */ +- return 1407; ++ return 1411; + } + else + { +@@ -13294,7 +13294,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx0xx001001xxxxxxxx1xxxx + fcmle. */ +- return 1406; ++ return 1410; + } + } + else +@@ -13303,7 +13303,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx0xx101001xxxxxxxxxxxxx + fminnmv. */ +- return 1447; ++ return 1451; + } + } + else +@@ -13314,7 +13314,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx0xx011001xxxxxxxxxxxxx + fcmne. */ +- return 1408; ++ return 1412; + } + else + { +@@ -13324,7 +13324,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx0x0111001xxxxxxxxxxxxx + fminv. */ +- return 1448; ++ return 1452; + } + else + { +@@ -13332,7 +13332,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx0x1111001xxxxxxxxxxxxx + frsqrte. */ +- return 1480; ++ return 1484; + } + } + } +@@ -13348,7 +13348,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x1000xxxxx001xxxxxxxxxxxxx + stnt1w. */ +- return 2256; ++ return 2260; + } + else + { +@@ -13356,7 +13356,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x1100xxxxx001xxxxxxxxxxxxx + stnt1d. */ +- return 2252; ++ return 2256; + } + } + else +@@ -13365,7 +13365,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x1x10xxxxx001xxxxxxxxxxxxx + stnt1w. */ +- return 2255; ++ return 2259; + } + } + } +@@ -13384,7 +13384,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx1xxxxx0010xxxxxxx0xxxx + ctermeq. */ +- return 1365; ++ return 1369; + } + else + { +@@ -13392,7 +13392,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx1xxxxx0011xxxxxxx0xxxx + whilewr. */ +- return 2334; ++ return 2338; + } + } + else +@@ -13403,7 +13403,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx1xxxxx0010xxxxxxx1xxxx + ctermne. */ +- return 1366; ++ return 1370; + } + else + { +@@ -13411,7 +13411,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx1xxxxx0011xxxxxxx1xxxx + whilerw. */ +- return 2333; ++ return 2337; + } + } + } +@@ -13423,7 +13423,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x10x1xxxxx001xxxxxxxxxxxxx + ld1row. */ +- return 2470; ++ return 2474; + } + else + { +@@ -13431,7 +13431,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x11x1xxxxx001xxxxxxxxxxxxx + ld1rod. */ +- return 2471; ++ return 2475; + } + } + } +@@ -13441,7 +13441,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x11001x1xx1xxxxx001xxxxxxxxxxxxx + fmls. */ +- return 1453; ++ return 1457; + } + } + } +@@ -13468,7 +13468,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x10000xxxx01xxxx0xxxx0xxxx + and. */ +- return 1296; ++ return 1300; + } + else + { +@@ -13476,7 +13476,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x10000xxxx01xxxx0xxxx1xxxx + bic. */ +- return 1308; ++ return 1312; + } + } + else +@@ -13487,7 +13487,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x100010xxx01xxxx0xxxxxxxxx + brka. */ +- return 1310; ++ return 1314; + } + else + { +@@ -13495,7 +13495,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x100011xxx01xxxx0xxxxxxxxx + brkn. */ +- return 1314; ++ return 1318; + } + } + } +@@ -13507,7 +13507,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1000xxxxx01xxxx1xxxx0xxxx + eor. */ +- return 1383; ++ return 1387; + } + else + { +@@ -13515,7 +13515,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1000xxxxx01xxxx1xxxx1xxxx + sel. */ +- return 1832; ++ return 1836; + } + } + } +@@ -13527,7 +13527,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x1000xxxxx010xxxxxxxxxxxxx + ld1sh. */ +- return 1582; ++ return 1586; + } + else + { +@@ -13535,7 +13535,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x1000xxxxx011xxxxxxxxxxxxx + ldff1sh. */ +- return 1682; ++ return 1686; + } + } + } +@@ -13553,7 +13553,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x11000xxxx01xxxx0xxxx0xxxx + orr. */ +- return 1768; ++ return 1772; + } + else + { +@@ -13561,7 +13561,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x11000xxxx01xxxx0xxxx1xxxx + orn. */ +- return 1763; ++ return 1767; + } + } + else +@@ -13570,7 +13570,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x11001xxxx01xxxx0xxxxxxxxx + brkb. */ +- return 1312; ++ return 1316; + } + } + else +@@ -13581,7 +13581,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1100xxxxx01xxxx1xxxx0xxxx + nor. */ +- return 1760; ++ return 1764; + } + else + { +@@ -13589,7 +13589,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1100xxxxx01xxxx1xxxx1xxxx + nand. */ +- return 1757; ++ return 1761; + } + } + } +@@ -13601,7 +13601,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x1100xxxxx010xxxxxxxxxxxxx + ld1sb. */ +- return 1570; ++ return 1574; + } + else + { +@@ -13609,7 +13609,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x1100xxxxx011xxxxxxxxxxxxx + ldff1sb. */ +- return 1670; ++ return 1674; + } + } + } +@@ -13630,7 +13630,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x10100xxxx01xxxx0xxxx0xxxx + ands. */ +- return 1297; ++ return 1301; + } + else + { +@@ -13640,7 +13640,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x101010xxx01xxxx0xxxx0xxxx + brkas. */ +- return 1311; ++ return 1315; + } + else + { +@@ -13648,7 +13648,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x101011xxx01xxxx0xxxx0xxxx + brkns. */ +- return 1315; ++ return 1319; + } + } + } +@@ -13658,7 +13658,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1010xxxxx01xxxx1xxxx0xxxx + eors. */ +- return 1384; ++ return 1388; + } + } + else +@@ -13667,7 +13667,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1010xxxxx01xxxxxxxxx1xxxx + bics. */ +- return 1309; ++ return 1313; + } + } + else +@@ -13678,7 +13678,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x1010xxxxx010xxxxxxxxxxxxx + ld1w. */ +- return 1601; ++ return 1605; + } + else + { +@@ -13686,7 +13686,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x1010xxxxx011xxxxxxxxxxxxx + ldff1w. */ +- return 1701; ++ return 1705; + } + } + } +@@ -13704,7 +13704,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x11100xxxx01xxxx0xxxx0xxxx + orrs. */ +- return 1769; ++ return 1773; + } + else + { +@@ -13712,7 +13712,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x11101xxxx01xxxx0xxxx0xxxx + brkbs. */ +- return 1313; ++ return 1317; + } + } + else +@@ -13721,7 +13721,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1110xxxxx01xxxx1xxxx0xxxx + nors. */ +- return 1761; ++ return 1765; + } + } + else +@@ -13732,7 +13732,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1110xxxxx01xxxx0xxxx1xxxx + orns. */ +- return 1764; ++ return 1768; + } + else + { +@@ -13740,7 +13740,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1110xxxxx01xxxx1xxxx1xxxx + nands. */ +- return 1758; ++ return 1762; + } + } + } +@@ -13752,7 +13752,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x1110xxxxx010xxxxxxxxxxxxx + ld1sb. */ +- return 1572; ++ return 1576; + } + else + { +@@ -13760,7 +13760,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x1110xxxxx011xxxxxxxxxxxxx + ldff1sb. */ +- return 1674; ++ return 1678; + } + } + } +@@ -13778,7 +13778,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x01001x1001xxxxx010xxxxxxxxxxxxx + ld1sh. */ +- return 1583; ++ return 1587; + } + else + { +@@ -13786,7 +13786,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x01001x1101xxxxx010xxxxxxxxxxxxx + ld1sb. */ +- return 1571; ++ return 1575; + } + } + else +@@ -13797,7 +13797,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x01001x1011xxxxx010xxxxxxxxxxxxx + ld1w. */ +- return 1602; ++ return 1606; + } + else + { +@@ -13805,7 +13805,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x01001x1111xxxxx010xxxxxxxxxxxxx + ld1d. */ +- return 1524; ++ return 1528; + } + } + } +@@ -13819,7 +13819,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x01001x1001xxxxx011xxxxxxxxxxxxx + ldff1sh. */ +- return 1684; ++ return 1688; + } + else + { +@@ -13827,7 +13827,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x01001x1101xxxxx011xxxxxxxxxxxxx + ldff1sb. */ +- return 1672; ++ return 1676; + } + } + else +@@ -13838,7 +13838,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x01001x1011xxxxx011xxxxxxxxxxxxx + ldff1w. */ +- return 1703; ++ return 1707; + } + else + { +@@ -13846,7 +13846,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x01001x1111xxxxx011xxxxxxxxxxxxx + ldff1d. */ +- return 1648; ++ return 1652; + } + } + } +@@ -13866,7 +13866,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx0xxxxx010xxxxxxxx0xxxx + fcmge. */ +- return 1403; ++ return 1407; + } + else + { +@@ -13874,7 +13874,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx0xxxxx010xxxxxxxx1xxxx + fcmgt. */ +- return 1405; ++ return 1409; + } + } + else +@@ -13883,7 +13883,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx1xxxxx010xxxxxxxxxxxxx + fnmla. */ +- return 1467; ++ return 1471; + } + } + else +@@ -13894,7 +13894,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x1x0xxxxxx010xxxxxxxxxxxxx + str. */ +- return 1953; ++ return 1957; + } + else + { +@@ -13904,7 +13904,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x1x10xxxxx010xxxxxxxxxxxxx + st1w. */ +- return 1912; ++ return 1916; + } + else + { +@@ -13914,7 +13914,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x1011xxxxx010xxxxxxxxxxxxx + st1w. */ +- return 1914; ++ return 1918; + } + else + { +@@ -13922,7 +13922,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x1111xxxxx010xxxxxxxxxxxxx + st1d. */ +- return 1891; ++ return 1895; + } + } + } +@@ -13940,7 +13940,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx0xxxxx011xxxxxxxx0xxxx + fcmeq. */ +- return 1401; ++ return 1405; + } + else + { +@@ -13948,7 +13948,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx0xxxxx011xxxxxxxx1xxxx + fcmne. */ +- return 1409; ++ return 1413; + } + } + else +@@ -13961,7 +13961,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x1000xxxxx011xxxxxxxxxxxxx + stnt1w. */ +- return 1950; ++ return 1954; + } + else + { +@@ -13969,7 +13969,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x1100xxxxx011xxxxxxxxxxxxx + stnt1d. */ +- return 1946; ++ return 1950; + } + } + else +@@ -13980,7 +13980,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x1010xxxxx011xxxxxxxxxxxxx + st3w. */ +- return 1934; ++ return 1938; + } + else + { +@@ -13988,7 +13988,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x1110xxxxx011xxxxxxxxxxxxx + st3d. */ +- return 1930; ++ return 1934; + } + } + } +@@ -14001,7 +14001,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx1xxxxx011xxxxxxxxxxxxx + fnmls. */ +- return 1468; ++ return 1472; + } + else + { +@@ -14013,7 +14013,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x1001xxxxx011xxxxxxxxxxxxx + st2w. */ +- return 1926; ++ return 1930; + } + else + { +@@ -14021,7 +14021,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x1101xxxxx011xxxxxxxxxxxxx + st2d. */ +- return 1922; ++ return 1926; + } + } + else +@@ -14032,7 +14032,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x1011xxxxx011xxxxxxxxxxxxx + st4w. */ +- return 1942; ++ return 1946; + } + else + { +@@ -14040,7 +14040,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x1111xxxxx011xxxxxxxxxxxxx + st4d. */ +- return 1938; ++ return 1942; + } + } + } +@@ -14065,7 +14065,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x01001x1xx0xxxxx100xxxxxxxx0xxxx + cmpeq. */ +- return 1330; ++ return 1334; + } + else + { +@@ -14073,7 +14073,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x01001x1xx0xxxxx100xxxxxxxx1xxxx + cmpne. */ +- return 1353; ++ return 1357; + } + } + else +@@ -14088,7 +14088,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x01001x10000xxxx101xxxxxxxxxxxxx + ld1sh. */ +- return 1589; ++ return 1593; + } + else + { +@@ -14096,7 +14096,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x01001x11000xxxx101xxxxxxxxxxxxx + ld1sb. */ +- return 1576; ++ return 1580; + } + } + else +@@ -14107,7 +14107,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x01001x10100xxxx101xxxxxxxxxxxxx + ld1w. */ +- return 1608; ++ return 1612; + } + else + { +@@ -14115,7 +14115,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x01001x11100xxxx101xxxxxxxxxxxxx + ld1sb. */ +- return 1578; ++ return 1582; + } + } + } +@@ -14129,7 +14129,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x01001x10001xxxx101xxxxxxxxxxxxx + ldnf1sh. */ +- return 1722; ++ return 1726; + } + else + { +@@ -14137,7 +14137,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x01001x11001xxxx101xxxxxxxxxxxxx + ldnf1sb. */ +- return 1719; ++ return 1723; + } + } + else +@@ -14148,7 +14148,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x01001x10101xxxx101xxxxxxxxxxxxx + ldnf1w. */ +- return 1725; ++ return 1729; + } + else + { +@@ -14156,7 +14156,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x01001x11101xxxx101xxxxxxxxxxxxx + ldnf1sb. */ +- return 1721; ++ return 1725; + } + } + } +@@ -14176,7 +14176,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1x000xxxx11xxxxxxxxx0xxxx + brkpa. */ +- return 1316; ++ return 1320; + } + else + { +@@ -14184,7 +14184,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1x100xxxx11xxxxxxxxx0xxxx + brkpas. */ +- return 1317; ++ return 1321; + } + } + else +@@ -14197,7 +14197,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx010xx011xxxxxxxxx0xxxx + ptest. */ +- return 1802; ++ return 1806; + } + else + { +@@ -14211,7 +14211,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx011xx01100x0xxxxx0xxxx + pfirst. */ +- return 1772; ++ return 1776; + } + else + { +@@ -14219,7 +14219,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx011xx01110x0xxxxx0xxxx + ptrue. */ +- return 1803; ++ return 1807; + } + } + else +@@ -14230,7 +14230,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1x0011xx011x1x0xxxxx0xxxx + rdffr. */ +- return 1809; ++ return 1813; + } + else + { +@@ -14238,7 +14238,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1x1011xx011x1x0xxxxx0xxxx + rdffrs. */ +- return 1810; ++ return 1814; + } + } + } +@@ -14248,7 +14248,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx011xx011xxx1xxxxx0xxxx + pfalse. */ +- return 1771; ++ return 1775; + } + } + } +@@ -14262,7 +14262,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx01xxx111x0x0xxxxx0xxxx + ptrues. */ +- return 1804; ++ return 1808; + } + else + { +@@ -14270,7 +14270,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx01xxx111x1x0xxxxx0xxxx + rdffr. */ +- return 1808; ++ return 1812; + } + } + else +@@ -14279,7 +14279,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx01xxx111xxx1xxxxx0xxxx + pnext. */ +- return 1773; ++ return 1777; + } + } + } +@@ -14292,7 +14292,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1x00xxxxx11xxxxxxxxx1xxxx + brkpb. */ +- return 1318; ++ return 1322; + } + else + { +@@ -14300,7 +14300,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1x10xxxxx11xxxxxxxxx1xxxx + brkpbs. */ +- return 1319; ++ return 1323; + } + } + } +@@ -14316,7 +14316,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x1000xxxxx110xxxxxxxxxxxxx + ldnt1w. */ +- return 1733; ++ return 1737; + } + else + { +@@ -14324,7 +14324,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x1100xxxxx110xxxxxxxxxxxxx + ldnt1d. */ +- return 1729; ++ return 1733; + } + } + else +@@ -14335,7 +14335,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x1010xxxxx110xxxxxxxxxxxxx + ld3w. */ +- return 1625; ++ return 1629; + } + else + { +@@ -14343,7 +14343,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x1110xxxxx110xxxxxxxxxxxxx + ld3d. */ +- return 1621; ++ return 1625; + } + } + } +@@ -14357,7 +14357,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x1000xxxxx111xxxxxxxxxxxxx + ldnt1w. */ +- return 1734; ++ return 1738; + } + else + { +@@ -14365,7 +14365,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x1100xxxxx111xxxxxxxxxxxxx + ldnt1d. */ +- return 1730; ++ return 1734; + } + } + else +@@ -14376,7 +14376,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x1010xxxxx111xxxxxxxxxxxxx + ld3w. */ +- return 1626; ++ return 1630; + } + else + { +@@ -14384,7 +14384,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x1110xxxxx111xxxxxxxxxxxxx + ld3d. */ +- return 1622; ++ return 1626; + } + } + } +@@ -14413,7 +14413,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx000000100xxxxxxxxxxxxx + fadd. */ +- return 1392; ++ return 1396; + } + else + { +@@ -14421,7 +14421,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx000100100xxxxxxxxxxxxx + fmaxnm. */ +- return 1439; ++ return 1443; + } + } + else +@@ -14432,7 +14432,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx000010100xxxxxxxxxxxxx + fmul. */ +- return 1459; ++ return 1463; + } + else + { +@@ -14440,7 +14440,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx000110100xxxxxxxxxxxxx + fmax. */ +- return 1437; ++ return 1441; + } + } + } +@@ -14454,7 +14454,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx000001100xxxxxxxxxxxxx + fsub. */ +- return 1485; ++ return 1489; + } + else + { +@@ -14462,7 +14462,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx000101100xxxxxxxxxxxxx + fminnm. */ +- return 1445; ++ return 1449; + } + } + else +@@ -14473,7 +14473,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx000011100xxxxxxxxxxxxx + fsubr. */ +- return 1487; ++ return 1491; + } + else + { +@@ -14481,7 +14481,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx000111100xxxxxxxxxxxxx + fmin. */ +- return 1443; ++ return 1447; + } + } + } +@@ -14492,7 +14492,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx010xxx100xxxxxxxxxxxxx + ftmad. */ +- return 1489; ++ return 1493; + } + } + else +@@ -14509,7 +14509,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx001000100xxxxxxxxxxxxx + fabd. */ +- return 1387; ++ return 1391; + } + else + { +@@ -14517,7 +14517,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx011000100xxxxxxxxxxxxx + fadd. */ +- return 1393; ++ return 1397; + } + } + else +@@ -14528,7 +14528,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx001100100xxxxxxxxxxxxx + fdivr. */ +- return 1433; ++ return 1437; + } + else + { +@@ -14536,7 +14536,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx011100100xxxxxxxxxxxxx + fmaxnm. */ +- return 1440; ++ return 1444; + } + } + } +@@ -14550,7 +14550,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx001010100xxxxxxxxxxxxx + fmulx. */ +- return 1464; ++ return 1468; + } + else + { +@@ -14558,7 +14558,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx011010100xxxxxxxxxxxxx + fmul. */ +- return 1460; ++ return 1464; + } + } + else +@@ -14567,7 +14567,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx0x1110100xxxxxxxxxxxxx + fmax. */ +- return 1438; ++ return 1442; + } + } + } +@@ -14583,7 +14583,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx001001100xxxxxxxxxxxxx + fscale. */ +- return 1482; ++ return 1486; + } + else + { +@@ -14591,7 +14591,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx011001100xxxxxxxxxxxxx + fsub. */ +- return 1486; ++ return 1490; + } + } + else +@@ -14602,7 +14602,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx001101100xxxxxxxxxxxxx + fdiv. */ +- return 1432; ++ return 1436; + } + else + { +@@ -14610,7 +14610,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx011101100xxxxxxxxxxxxx + fminnm. */ +- return 1446; ++ return 1450; + } + } + } +@@ -14622,7 +14622,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx0x1011100xxxxxxxxxxxxx + fsubr. */ +- return 1488; ++ return 1492; + } + else + { +@@ -14630,7 +14630,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx0x1111100xxxxxxxxxxxxx + fmin. */ +- return 1444; ++ return 1448; + } + } + } +@@ -14644,7 +14644,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx0xxxxx110xxxxxxxx0xxxx + fcmuo. */ +- return 1410; ++ return 1414; + } + else + { +@@ -14652,7 +14652,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx0xxxxx110xxxxxxxx1xxxx + facge. */ +- return 1389; ++ return 1393; + } + } + } +@@ -14666,7 +14666,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x1000xxxxx1x0xxxxxxxxxxxxx + st1w. */ +- return 1908; ++ return 1912; + } + else + { +@@ -14674,7 +14674,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x1100xxxxx1x0xxxxxxxxxxxxx + st1d. */ +- return 1887; ++ return 1891; + } + } + else +@@ -14683,7 +14683,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x1x10xxxxx1x0xxxxxxxxxxxxx + st1w. */ +- return 1913; ++ return 1917; + } + } + } +@@ -14707,7 +14707,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx000000101xxxxxxxxxxxxx + frintn. */ +- return 1476; ++ return 1480; + } + else + { +@@ -14715,7 +14715,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx010000101xxxxxxxxxxxxx + scvtf. */ +- return 1822; ++ return 1826; + } + } + else +@@ -14726,7 +14726,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx000100101xxxxxxxxxxxxx + frinta. */ +- return 1473; ++ return 1477; + } + else + { +@@ -14736,7 +14736,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1x0010100101xxxxxxxxxxxxx + scvtf. */ +- return 1821; ++ return 1825; + } + else + { +@@ -14746,7 +14746,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x101010100101xxxxxxxxxxxxx + scvtf. */ +- return 1820; ++ return 1824; + } + else + { +@@ -14754,7 +14754,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x111010100101xxxxxxxxxxxxx + scvtf. */ +- return 1824; ++ return 1828; + } + } + } +@@ -14770,7 +14770,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx000010101xxxxxxxxxxxxx + frintm. */ +- return 1475; ++ return 1479; + } + else + { +@@ -14778,7 +14778,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx010010101xxxxxxxxxxxxx + scvtf. */ +- return 1819; ++ return 1823; + } + } + else +@@ -14789,7 +14789,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx000110101xxxxxxxxxxxxx + frintx. */ +- return 1478; ++ return 1482; + } + else + { +@@ -14799,7 +14799,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x10x010110101xxxxxxxxxxxxx + scvtf. */ +- return 1823; ++ return 1827; + } + else + { +@@ -14807,7 +14807,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x11x010110101xxxxxxxxxxxxx + scvtf. */ +- return 1825; ++ return 1829; + } + } + } +@@ -14827,7 +14827,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1x0001000101xxxxxxxxxxxxx + fcvt. */ +- return 1412; ++ return 1416; + } + else + { +@@ -14835,7 +14835,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1x1001000101xxxxxxxxxxxxx + fcvt. */ +- return 1414; ++ return 1418; + } + } + else +@@ -14844,7 +14844,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx001100101xxxxxxxxxxxxx + frecpx. */ +- return 1472; ++ return 1476; + } + } + else +@@ -14857,7 +14857,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x100001x10101xxxxxxxxxxxxx + fcvtx. */ +- return 2082; ++ return 2086; + } + else + { +@@ -14865,7 +14865,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x110001x10101xxxxxxxxxxxxx + bfcvt. */ +- return 2487; ++ return 2491; + } + } + else +@@ -14874,7 +14874,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1x1001x10101xxxxxxxxxxxxx + fcvt. */ +- return 1416; ++ return 1420; + } + } + } +@@ -14888,7 +14888,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x100011xx0101xxxxxxxxxxxxx + flogb. */ +- return 2084; ++ return 2088; + } + else + { +@@ -14896,7 +14896,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x110011xx0101xxxxxxxxxxxxx + fcvtzs. */ +- return 1421; ++ return 1425; + } + } + else +@@ -14909,7 +14909,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1x1011000101xxxxxxxxxxxxx + fcvtzs. */ +- return 1422; ++ return 1426; + } + else + { +@@ -14919,7 +14919,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x101011100101xxxxxxxxxxxxx + fcvtzs. */ +- return 1419; ++ return 1423; + } + else + { +@@ -14927,7 +14927,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x111011100101xxxxxxxxxxxxx + fcvtzs. */ +- return 1423; ++ return 1427; + } + } + } +@@ -14939,7 +14939,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1x1011010101xxxxxxxxxxxxx + fcvtzs. */ +- return 1418; ++ return 1422; + } + else + { +@@ -14949,7 +14949,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x101011110101xxxxxxxxxxxxx + fcvtzs. */ +- return 1420; ++ return 1424; + } + else + { +@@ -14957,7 +14957,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x111011110101xxxxxxxxxxxxx + fcvtzs. */ +- return 1424; ++ return 1428; + } + } + } +@@ -14979,7 +14979,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx000001101xxxxxxxxxxxxx + frintp. */ +- return 1477; ++ return 1481; + } + else + { +@@ -14987,7 +14987,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx010001101xxxxxxxxxxxxx + ucvtf. */ +- return 1974; ++ return 1978; + } + } + else +@@ -15000,7 +15000,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1x0001001101xxxxxxxxxxxxx + fcvt. */ +- return 1413; ++ return 1417; + } + else + { +@@ -15008,7 +15008,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1x1001001101xxxxxxxxxxxxx + fcvt. */ +- return 1415; ++ return 1419; + } + } + else +@@ -15017,7 +15017,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx011001101xxxxxxxxxxxxx + fcvtzu. */ +- return 1429; ++ return 1433; + } + } + } +@@ -15031,7 +15031,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1x00x0101101xxxxxxxxxxxxx + ucvtf. */ +- return 1973; ++ return 1977; + } + else + { +@@ -15041,7 +15041,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1010x0101101xxxxxxxxxxxxx + ucvtf. */ +- return 1972; ++ return 1976; + } + else + { +@@ -15049,7 +15049,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1110x0101101xxxxxxxxxxxxx + ucvtf. */ +- return 1976; ++ return 1980; + } + } + } +@@ -15061,7 +15061,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx001101101xxxxxxxxxxxxx + fsqrt. */ +- return 1483; ++ return 1487; + } + else + { +@@ -15071,7 +15071,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1x0011101101xxxxxxxxxxxxx + fcvtzu. */ +- return 1428; ++ return 1432; + } + else + { +@@ -15081,7 +15081,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x101011101101xxxxxxxxxxxxx + fcvtzu. */ +- return 1426; ++ return 1430; + } + else + { +@@ -15089,7 +15089,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x111011101101xxxxxxxxxxxxx + fcvtzu. */ +- return 1430; ++ return 1434; + } + } + } +@@ -15108,7 +15108,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx000011101xxxxxxxxxxxxx + frintz. */ +- return 1479; ++ return 1483; + } + else + { +@@ -15116,7 +15116,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx010011101xxxxxxxxxxxxx + ucvtf. */ +- return 1971; ++ return 1975; + } + } + else +@@ -15127,7 +15127,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx001011101xxxxxxxxxxxxx + fcvt. */ +- return 1417; ++ return 1421; + } + else + { +@@ -15135,7 +15135,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx011011101xxxxxxxxxxxxx + fcvtzu. */ +- return 1425; ++ return 1429; + } + } + } +@@ -15149,7 +15149,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx000111101xxxxxxxxxxxxx + frinti. */ +- return 1474; ++ return 1478; + } + else + { +@@ -15159,7 +15159,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x10x010111101xxxxxxxxxxxxx + ucvtf. */ +- return 1975; ++ return 1979; + } + else + { +@@ -15167,7 +15167,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x11x010111101xxxxxxxxxxxxx + ucvtf. */ +- return 1977; ++ return 1981; + } + } + } +@@ -15179,7 +15179,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x10x0x1111101xxxxxxxxxxxxx + fcvtzu. */ +- return 1427; ++ return 1431; + } + else + { +@@ -15187,7 +15187,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x11x0x1111101xxxxxxxxxxxxx + fcvtzu. */ +- return 1431; ++ return 1435; + } + } + } +@@ -15204,7 +15204,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x1000xxxxx101xxxxxxxxxxxxx + st1w. */ +- return 1909; ++ return 1913; + } + else + { +@@ -15212,7 +15212,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x1100xxxxx101xxxxxxxxxxxxx + st1d. */ +- return 1888; ++ return 1892; + } + } + else +@@ -15223,7 +15223,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x1010xxxxx101xxxxxxxxxxxxx + st1w. */ +- return 1916; ++ return 1920; + } + else + { +@@ -15231,7 +15231,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x1110xxxxx101xxxxxxxxxxxxx + st1d. */ +- return 1892; ++ return 1896; + } + } + } +@@ -15244,7 +15244,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx0xxxxx111xxxxxxxxxxxxx + facgt. */ +- return 1390; ++ return 1394; + } + else + { +@@ -15254,7 +15254,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x1xx00xxxx111xxxxxxxxxxxxx + st1w. */ +- return 1917; ++ return 1921; + } + else + { +@@ -15266,7 +15266,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x10001xxxx111xxxxxxxxxxxxx + stnt1w. */ +- return 1951; ++ return 1955; + } + else + { +@@ -15274,7 +15274,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x11001xxxx111xxxxxxxxxxxxx + stnt1d. */ +- return 1947; ++ return 1951; + } + } + else +@@ -15285,7 +15285,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x10101xxxx111xxxxxxxxxxxxx + st3w. */ +- return 1935; ++ return 1939; + } + else + { +@@ -15293,7 +15293,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x11101xxxx111xxxxxxxxxxxxx + st3d. */ +- return 1931; ++ return 1935; + } + } + } +@@ -15324,7 +15324,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx10000010xxxxxxxxxxxxxx + cntp. */ +- return 1359; ++ return 1363; + } + else + { +@@ -15338,7 +15338,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx10100010x000xxxxxxxxxx + sqincp. */ +- return 1866; ++ return 1870; + } + else + { +@@ -15346,7 +15346,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx10100010x100xxxxxxxxxx + wrffr. */ +- return 2039; ++ return 2043; + } + } + else +@@ -15355,7 +15355,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx10100010xx10xxxxxxxxxx + sqincp. */ +- return 1868; ++ return 1872; + } + } + else +@@ -15364,7 +15364,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx10100010xxx1xxxxxxxxxx + sqincp. */ +- return 1867; ++ return 1871; + } + } + } +@@ -15378,7 +15378,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx10x10010x00xxxxxxxxxxx + incp. */ +- return 1497; ++ return 1501; + } + else + { +@@ -15386,7 +15386,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx10x10010x10xxxxxxxxxxx + setffr. */ +- return 1833; ++ return 1837; + } + } + else +@@ -15395,7 +15395,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx10x10010xx1xxxxxxxxxxx + incp. */ +- return 1498; ++ return 1502; + } + } + } +@@ -15409,7 +15409,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx10xx1010xx00xxxxxxxxxx + sqdecp. */ +- return 1852; ++ return 1856; + } + else + { +@@ -15417,7 +15417,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx10xx1010xx10xxxxxxxxxx + sqdecp. */ +- return 1854; ++ return 1858; + } + } + else +@@ -15426,7 +15426,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx10xx1010xxx1xxxxxxxxxx + sqdecp. */ +- return 1853; ++ return 1857; + } + } + } +@@ -15444,7 +15444,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx10x00110xx00xxxxxxxxxx + uqincp. */ +- return 2014; ++ return 2018; + } + else + { +@@ -15452,7 +15452,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx10x10110xx00xxxxxxxxxx + decp. */ +- return 1372; ++ return 1376; + } + } + else +@@ -15461,7 +15461,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx10xx1110xx00xxxxxxxxxx + uqdecp. */ +- return 2000; ++ return 2004; + } + } + else +@@ -15474,7 +15474,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx10x00110xx10xxxxxxxxxx + uqincp. */ +- return 2015; ++ return 2019; + } + else + { +@@ -15482,7 +15482,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx10x10110xx10xxxxxxxxxx + decp. */ +- return 1373; ++ return 1377; + } + } + else +@@ -15491,7 +15491,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx10xx1110xx10xxxxxxxxxx + uqdecp. */ +- return 2001; ++ return 2005; + } + } + } +@@ -15503,7 +15503,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx10xx0110xxx1xxxxxxxxxx + uqincp. */ +- return 2016; ++ return 2020; + } + else + { +@@ -15511,7 +15511,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx10xx1110xxx1xxxxxxxxxx + uqdecp. */ +- return 2002; ++ return 2006; + } + } + } +@@ -15526,7 +15526,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x10010xxxx10xxxxxxxxxxxxxx + ld1sh. */ +- return 1590; ++ return 1594; + } + else + { +@@ -15534,7 +15534,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x11010xxxx10xxxxxxxxxxxxxx + ld1sb. */ +- return 1577; ++ return 1581; + } + } + else +@@ -15545,7 +15545,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x10110xxxx10xxxxxxxxxxxxxx + ld1w. */ +- return 1609; ++ return 1613; + } + else + { +@@ -15553,7 +15553,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x11110xxxx10xxxxxxxxxxxxxx + ld1d. */ +- return 1529; ++ return 1533; + } + } + } +@@ -15568,7 +15568,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x01001x10011xxxx10xxxxxxxxxxxxxx + ldnf1sh. */ +- return 1723; ++ return 1727; + } + else + { +@@ -15576,7 +15576,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x01001x11011xxxx10xxxxxxxxxxxxxx + ldnf1sb. */ +- return 1720; ++ return 1724; + } + } + else +@@ -15587,7 +15587,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x01001x10111xxxx10xxxxxxxxxxxxxx + ldnf1w. */ +- return 1726; ++ return 1730; + } + else + { +@@ -15595,7 +15595,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x01001x11111xxxx10xxxxxxxxxxxxxx + ldnf1d. */ +- return 1715; ++ return 1719; + } + } + } +@@ -15618,7 +15618,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx10000011xxxxxxxxxxxxxx + add. */ +- return 1286; ++ return 1290; + } + else + { +@@ -15626,7 +15626,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx11000011xxxxxxxxxxxxxx + mul. */ +- return 1755; ++ return 1759; + } + } + else +@@ -15637,7 +15637,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx10100011xxxxxxxxxxxxxx + smax. */ +- return 1834; ++ return 1838; + } + else + { +@@ -15645,7 +15645,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx11100011xxxxxxxxxxxxxx + dup. */ +- return 1378; ++ return 1382; + } + } + } +@@ -15655,7 +15655,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx1xx10011xxxxxxxxxxxxxx + sqadd. */ +- return 1843; ++ return 1847; + } + } + else +@@ -15666,7 +15666,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx1xx01011xxxxxxxxxxxxxx + smin. */ +- return 1837; ++ return 1841; + } + else + { +@@ -15674,7 +15674,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx1xx11011xxxxxxxxxxxxxx + sqsub. */ +- return 1873; ++ return 1877; + } + } + } +@@ -15690,7 +15690,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx1x000111xxxxxxxxxxxxxx + sub. */ +- return 1955; ++ return 1959; + } + else + { +@@ -15700,7 +15700,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx10100111xxxxxxxxxxxxxx + umax. */ +- return 1983; ++ return 1987; + } + else + { +@@ -15708,7 +15708,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx11100111xxxxxxxxxxxxxx + fdup. */ +- return 1434; ++ return 1438; + } + } + } +@@ -15718,7 +15718,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx1xx10111xxxxxxxxxxxxxx + uqadd. */ +- return 1991; ++ return 1995; + } + } + else +@@ -15731,7 +15731,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx1x001111xxxxxxxxxxxxxx + subr. */ +- return 1957; ++ return 1961; + } + else + { +@@ -15739,7 +15739,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx1x101111xxxxxxxxxxxxxx + umin. */ +- return 1986; ++ return 1990; + } + } + else +@@ -15748,7 +15748,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx1xx11111xxxxxxxxxxxxxx + uqsub. */ +- return 2021; ++ return 2025; + } + } + } +@@ -15765,7 +15765,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x1001xxxxx110xxxxxxxxxxxxx + ld2w. */ +- return 1617; ++ return 1621; + } + else + { +@@ -15773,7 +15773,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x1101xxxxx110xxxxxxxxxxxxx + ld2d. */ +- return 1613; ++ return 1617; + } + } + else +@@ -15784,7 +15784,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x1011xxxxx110xxxxxxxxxxxxx + ld4w. */ +- return 1633; ++ return 1637; + } + else + { +@@ -15792,7 +15792,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x1111xxxxx110xxxxxxxxxxxxx + ld4d. */ +- return 1629; ++ return 1633; + } + } + } +@@ -15806,7 +15806,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x1001xxxxx111xxxxxxxxxxxxx + ld2w. */ +- return 1618; ++ return 1622; + } + else + { +@@ -15814,7 +15814,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x1101xxxxx111xxxxxxxxxxxxx + ld2d. */ +- return 1614; ++ return 1618; + } + } + else +@@ -15825,7 +15825,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x1011xxxxx111xxxxxxxxxxxxx + ld4w. */ +- return 1634; ++ return 1638; + } + else + { +@@ -15833,7 +15833,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x1111xxxxx111xxxxxxxxxxxxx + ld4d. */ +- return 1630; ++ return 1634; + } + } + } +@@ -15852,7 +15852,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx1xxxxx100xxxxxxxxxxxxx + fmad. */ +- return 1436; ++ return 1440; + } + else + { +@@ -15860,7 +15860,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx1xxxxx110xxxxxxxxxxxxx + fnmad. */ +- return 1466; ++ return 1470; + } + } + else +@@ -15873,7 +15873,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x1001xxxxx1x0xxxxxxxxxxxxx + st1w. */ +- return 1910; ++ return 1914; + } + else + { +@@ -15881,7 +15881,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x1101xxxxx1x0xxxxxxxxxxxxx + st1d. */ +- return 1889; ++ return 1893; + } + } + else +@@ -15890,7 +15890,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x1x11xxxxx1x0xxxxxxxxxxxxx + st1w. */ +- return 1915; ++ return 1919; + } + } + } +@@ -15904,7 +15904,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx1xxxxx101xxxxxxxxxxxxx + fmsb. */ +- return 1457; ++ return 1461; + } + else + { +@@ -15916,7 +15916,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x1001xxxxx101xxxxxxxxxxxxx + st1w. */ +- return 1911; ++ return 1915; + } + else + { +@@ -15924,7 +15924,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x1101xxxxx101xxxxxxxxxxxxx + st1d. */ +- return 1890; ++ return 1894; + } + } + else +@@ -15933,7 +15933,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x1x11xxxxx101xxxxxxxxxxxxx + st1w. */ +- return 1918; ++ return 1922; + } + } + } +@@ -15945,7 +15945,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x1xx1xxxxx111xxxxxxxxxxxxx + fnmsb. */ +- return 1469; ++ return 1473; + } + else + { +@@ -15957,7 +15957,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x10x10xxxx111xxxxxxxxxxxxx + st1w. */ +- return 1919; ++ return 1923; + } + else + { +@@ -15965,7 +15965,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x11x10xxxx111xxxxxxxxxxxxx + st1d. */ +- return 1893; ++ return 1897; + } + } + else +@@ -15978,7 +15978,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x10011xxxx111xxxxxxxxxxxxx + st2w. */ +- return 1927; ++ return 1931; + } + else + { +@@ -15986,7 +15986,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x11011xxxx111xxxxxxxxxxxxx + st2d. */ +- return 1923; ++ return 1927; + } + } + else +@@ -15997,7 +15997,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x10111xxxx111xxxxxxxxxxxxx + st4w. */ +- return 1943; ++ return 1947; + } + else + { +@@ -16005,7 +16005,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 111001x11111xxxx111xxxxxxxxxxxxx + st4d. */ +- return 1939; ++ return 1943; + } + } + } +@@ -16376,7 +16376,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx110110xxxxxxxxxxxxxxxxxxxxxxxx + tbz. */ +- return 1247; ++ return 1251; + } + } + else +@@ -16395,7 +16395,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx110111xxxxxxxxxxxxxxxxxxxxxxxx + tbnz. */ +- return 1248; ++ return 1252; + } + } + } +@@ -16934,7 +16934,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 0x001110xx0xxxxx1x1001xxxxxxxxxx + smmla. */ +- return 2478; ++ return 2482; + } + } + } +@@ -16967,7 +16967,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 0x001110xx0xxxxx1x0101xxxxxxxxxx + sdot. */ +- return 2404; ++ return 2408; + } + } + else +@@ -17041,7 +17041,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 0x001110xx0xxxxx1x1011xxxxxxxxxx + usmmla. */ +- return 2480; ++ return 2484; + } + } + } +@@ -17074,7 +17074,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 0x001110xx0xxxxx1x0111xxxxxxxxxx + usdot. */ +- return 2481; ++ return 2485; + } + } + else +@@ -17121,7 +17121,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110000xxxxxxxxxxxxxxxxxxxxx + eor3. */ +- return 2411; ++ return 2415; + } + else + { +@@ -17129,7 +17129,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110100xxxxxxxxxxxxxxxxxxxxx + xar. */ +- return 2413; ++ return 2417; + } + } + else +@@ -17140,7 +17140,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110x10xxxxx0xxxxxxxxxxxxxxx + sm3ss1. */ +- return 2415; ++ return 2419; + } + else + { +@@ -17154,7 +17154,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110010xxxxx1xxx00xxxxxxxxxx + sm3tt1a. */ +- return 2416; ++ return 2420; + } + else + { +@@ -17162,7 +17162,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110110xxxxx1xxx00xxxxxxxxxx + sha512su0. */ +- return 2409; ++ return 2413; + } + } + else +@@ -17171,7 +17171,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110x10xxxxx1xxx10xxxxxxxxxx + sm3tt2a. */ +- return 2418; ++ return 2422; + } + } + else +@@ -17184,7 +17184,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110010xxxxx1xxx01xxxxxxxxxx + sm3tt1b. */ +- return 2417; ++ return 2421; + } + else + { +@@ -17192,7 +17192,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110110xxxxx1xxx01xxxxxxxxxx + sm4e. */ +- return 2422; ++ return 2426; + } + } + else +@@ -17201,7 +17201,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110x10xxxxx1xxx11xxxxxxxxxx + sm3tt2b. */ +- return 2419; ++ return 2423; + } + } + } +@@ -17382,7 +17382,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx101110xx0xxxxx100101xxxxxxxxxx + udot. */ +- return 2403; ++ return 2407; + } + } + else +@@ -17413,7 +17413,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx101110xx0xxxxx101x01xxxxxxxxxx + ummla. */ +- return 2479; ++ return 2483; + } + else + { +@@ -17432,7 +17432,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx101110xx0xxxxx1x1011xxxxxxxxxx + bfmmla. */ +- return 2495; ++ return 2499; + } + else + { +@@ -17442,7 +17442,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx1011100x0xxxxx1x1111xxxxxxxxxx + bfdot. */ +- return 2493; ++ return 2497; + } + else + { +@@ -17452,7 +17452,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x01011101x0xxxxx1x1111xxxxxxxxxx + bfmlalb. */ +- return 2500; ++ return 2504; + } + else + { +@@ -17460,7 +17460,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x11011101x0xxxxx1x1111xxxxxxxxxx + bfmlalt. */ +- return 2499; ++ return 2503; + } + } + } +@@ -18044,7 +18044,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000011101x1xxxx1011010xxxxxxxxxx + bfcvtn. */ +- return 2496; ++ return 2500; + } + else + { +@@ -18052,7 +18052,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010011101x1xxxx1011010xxxxxxxxxx + bfcvtn2. */ +- return 2497; ++ return 2501; + } + } + } +@@ -18370,7 +18370,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110xx1xxxxx0xxxxxxxxxxxxxxx + bcax. */ +- return 2414; ++ return 2418; + } + } + else +@@ -18981,7 +18981,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 11001110xx1xxxxx100000xxxxxxxxxx + sha512h. */ +- return 2407; ++ return 2411; + } + } + } +@@ -19033,7 +19033,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 11001110xx1xxxxx110000xxxxxxxxxx + sm3partw1. */ +- return 2420; ++ return 2424; + } + } + } +@@ -19276,7 +19276,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110xx1xxxxx100010xxxxxxxxxx + sha512su1. */ +- return 2410; ++ return 2414; + } + } + else +@@ -19352,7 +19352,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x0011100x1xxxxx110010xxxxxxxxxx + sm4ekey. */ +- return 2423; ++ return 2427; + } + } + else +@@ -20178,7 +20178,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110xx1xxxxx100001xxxxxxxxxx + sha512h2. */ +- return 2408; ++ return 2412; + } + } + else +@@ -20210,7 +20210,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x0011100x1xxxxx110001xxxxxxxxxx + sm3partw2. */ +- return 2421; ++ return 2425; + } + } + else +@@ -20450,7 +20450,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110xx1xxxxx100011xxxxxxxxxx + rax1. */ +- return 2412; ++ return 2416; + } + } + else +@@ -20482,7 +20482,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x01011100x1xxxxx110011xxxxxxxxxx + fmlal2. */ +- return 2426; ++ return 2430; + } + else + { +@@ -20490,7 +20490,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x11011100x1xxxxx110011xxxxxxxxxx + fmlal2. */ +- return 2430; ++ return 2434; + } + } + } +@@ -20512,7 +20512,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x01011101x1xxxxx110011xxxxxxxxxx + fmlsl2. */ +- return 2427; ++ return 2431; + } + else + { +@@ -20520,7 +20520,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x11011101x1xxxxx110011xxxxxxxxxx + fmlsl2. */ +- return 2431; ++ return 2435; + } + } + } +@@ -20559,7 +20559,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x00011100x1xxxxx111011xxxxxxxxxx + fmlal. */ +- return 2424; ++ return 2428; + } + else + { +@@ -20567,7 +20567,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x10011100x1xxxxx111011xxxxxxxxxx + fmlal. */ +- return 2428; ++ return 2432; + } + } + else +@@ -20589,7 +20589,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x00011101x1xxxxx111011xxxxxxxxxx + fmlsl. */ +- return 2425; ++ return 2429; + } + else + { +@@ -20597,7 +20597,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x10011101x1xxxxx111011xxxxxxxxxx + fmlsl. */ +- return 2429; ++ return 2433; + } + } + else +@@ -22405,7 +22405,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x0001111xxxxxxxx0000x0xxxxxxxxxx + fmlal. */ +- return 2432; ++ return 2436; + } + else + { +@@ -22413,7 +22413,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1001111xxxxxxxx0000x0xxxxxxxxxx + fmlal. */ +- return 2436; ++ return 2440; + } + } + else +@@ -22435,7 +22435,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x0001111xxxxxxxx0100x0xxxxxxxxxx + fmlsl. */ +- return 2433; ++ return 2437; + } + else + { +@@ -22443,7 +22443,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1001111xxxxxxxx0100x0xxxxxxxxxx + fmlsl. */ +- return 2437; ++ return 2441; + } + } + else +@@ -22949,7 +22949,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x0101111xxxxxxxx1000x0xxxxxxxxxx + fmlal2. */ +- return 2434; ++ return 2438; + } + else + { +@@ -22957,7 +22957,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1101111xxxxxxxx1000x0xxxxxxxxxx + fmlal2. */ +- return 2438; ++ return 2442; + } + } + } +@@ -22979,7 +22979,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x0101111xxxxxxxx1100x0xxxxxxxxxx + fmlsl2. */ +- return 2435; ++ return 2439; + } + else + { +@@ -22987,7 +22987,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1101111xxxxxxxx1100x0xxxxxxxxxx + fmlsl2. */ +- return 2439; ++ return 2443; + } + } + } +@@ -23043,7 +23043,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx001111xxxxxxxx1110x0xxxxxxxxxx + sdot. */ +- return 2406; ++ return 2410; + } + else + { +@@ -23051,7 +23051,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx101111xxxxxxxx1110x0xxxxxxxxxx + udot. */ +- return 2405; ++ return 2409; + } + } + } +@@ -23154,7 +23154,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx00111100xxxxxx1111x0xxxxxxxxxx + sudot. */ +- return 2483; ++ return 2487; + } + else + { +@@ -23162,7 +23162,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx00111110xxxxxx1111x0xxxxxxxxxx + usdot. */ +- return 2482; ++ return 2486; + } + } + else +@@ -23173,7 +23173,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx00111101xxxxxx1111x0xxxxxxxxxx + bfdot. */ +- return 2494; ++ return 2498; + } + else + { +@@ -23183,7 +23183,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x000111111xxxxxx1111x0xxxxxxxxxx + bfmlalb. */ +- return 2502; ++ return 2506; + } + else + { +@@ -23191,7 +23191,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x100111111xxxxxx1111x0xxxxxxxxxx + bfmlalt. */ +- return 2501; ++ return 2505; + } + } + } +@@ -23678,30 +23678,30 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode) + int value; + switch (key) + { +- case 2377: value = 2379; break; /* mov --> mova. */ +- case 2379: return NULL; /* mova --> NULL. */ +- case 2376: value = 2378; break; /* mov --> mova. */ +- case 2378: return NULL; /* mova --> NULL. */ +- case 2381: value = 2386; break; /* ld1b --> ld1b. */ +- case 2386: return NULL; /* ld1b --> NULL. */ +- case 2383: value = 2388; break; /* ld1w --> ld1w. */ +- case 2388: return NULL; /* ld1w --> NULL. */ +- case 2382: value = 2387; break; /* ld1h --> ld1h. */ +- case 2387: return NULL; /* ld1h --> NULL. */ +- case 2384: value = 2389; break; /* ld1d --> ld1d. */ +- case 2389: return NULL; /* ld1d --> NULL. */ +- case 2391: value = 2396; break; /* st1b --> st1b. */ +- case 2396: return NULL; /* st1b --> NULL. */ +- case 2393: value = 2398; break; /* st1w --> st1w. */ +- case 2398: return NULL; /* st1w --> NULL. */ +- case 2392: value = 2397; break; /* st1h --> st1h. */ +- case 2397: return NULL; /* st1h --> NULL. */ +- case 2394: value = 2399; break; /* st1d --> st1d. */ +- case 2399: return NULL; /* st1d --> NULL. */ +- case 2385: value = 2390; break; /* ld1q --> ld1q. */ +- case 2390: return NULL; /* ld1q --> NULL. */ +- case 2395: value = 2400; break; /* st1q --> st1q. */ +- case 2400: return NULL; /* st1q --> NULL. */ ++ case 2381: value = 2383; break; /* mov --> mova. */ ++ case 2383: return NULL; /* mova --> NULL. */ ++ case 2380: value = 2382; break; /* mov --> mova. */ ++ case 2382: return NULL; /* mova --> NULL. */ ++ case 2385: value = 2390; break; /* ld1b --> ld1b. */ ++ case 2390: return NULL; /* ld1b --> NULL. */ ++ case 2387: value = 2392; break; /* ld1w --> ld1w. */ ++ case 2392: return NULL; /* ld1w --> NULL. */ ++ case 2386: value = 2391; break; /* ld1h --> ld1h. */ ++ case 2391: return NULL; /* ld1h --> NULL. */ ++ case 2388: value = 2393; break; /* ld1d --> ld1d. */ ++ case 2393: return NULL; /* ld1d --> NULL. */ ++ case 2395: value = 2400; break; /* st1b --> st1b. */ ++ case 2400: return NULL; /* st1b --> NULL. */ ++ case 2397: value = 2402; break; /* st1w --> st1w. */ ++ case 2402: return NULL; /* st1w --> NULL. */ ++ case 2396: value = 2401; break; /* st1h --> st1h. */ ++ case 2401: return NULL; /* st1h --> NULL. */ ++ case 2398: value = 2403; break; /* st1d --> st1d. */ ++ case 2403: return NULL; /* st1d --> NULL. */ ++ case 2389: value = 2394; break; /* ld1q --> ld1q. */ ++ case 2394: return NULL; /* ld1q --> NULL. */ ++ case 2399: value = 2404; break; /* st1q --> st1q. */ ++ case 2404: return NULL; /* st1q --> NULL. */ + case 12: value = 19; break; /* add --> addg. */ + case 19: return NULL; /* addg --> NULL. */ + case 16: value = 20; break; /* sub --> subg. */ +@@ -23712,59 +23712,63 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode) + case 970: return NULL; /* stllrh --> NULL. */ + case 972: value = 976; break; /* ldnp --> ldp. */ + case 976: return NULL; /* ldp --> NULL. */ +- case 1636: value = 1637; break; /* ldff1b --> ldff1b. */ +- case 1637: return NULL; /* ldff1b --> NULL. */ +- case 1692: value = 1693; break; /* ldff1sw --> ldff1sw. */ +- case 1693: return NULL; /* ldff1sw --> NULL. */ + case 1640: value = 1641; break; /* ldff1b --> ldff1b. */ + case 1641: return NULL; /* ldff1b --> NULL. */ +- case 1659: value = 1660; break; /* ldff1h --> ldff1h. */ +- case 1660: return NULL; /* ldff1h --> NULL. */ +- case 1638: value = 1639; break; /* ldff1b --> ldff1b. */ +- case 1639: return NULL; /* ldff1b --> NULL. */ +- case 1657: value = 1658; break; /* ldff1h --> ldff1h. */ +- case 1658: return NULL; /* ldff1h --> NULL. */ ++ case 1696: value = 1697; break; /* ldff1sw --> ldff1sw. */ ++ case 1697: return NULL; /* ldff1sw --> NULL. */ ++ case 1644: value = 1645; break; /* ldff1b --> ldff1b. */ ++ case 1645: return NULL; /* ldff1b --> NULL. */ ++ case 1663: value = 1664; break; /* ldff1h --> ldff1h. */ ++ case 1664: return NULL; /* ldff1h --> NULL. */ + case 1642: value = 1643; break; /* ldff1b --> ldff1b. */ + case 1643: return NULL; /* ldff1b --> NULL. */ + case 1661: value = 1662; break; /* ldff1h --> ldff1h. */ + case 1662: return NULL; /* ldff1h --> NULL. */ +- case 1682: value = 1683; break; /* ldff1sh --> ldff1sh. */ +- case 1683: return NULL; /* ldff1sh --> NULL. */ +- case 1670: value = 1671; break; /* ldff1sb --> ldff1sb. */ +- case 1671: return NULL; /* ldff1sb --> NULL. */ +- case 1701: value = 1702; break; /* ldff1w --> ldff1w. */ +- case 1702: return NULL; /* ldff1w --> NULL. */ ++ case 1646: value = 1647; break; /* ldff1b --> ldff1b. */ ++ case 1647: return NULL; /* ldff1b --> NULL. */ ++ case 1665: value = 1666; break; /* ldff1h --> ldff1h. */ ++ case 1666: return NULL; /* ldff1h --> NULL. */ ++ case 1686: value = 1687; break; /* ldff1sh --> ldff1sh. */ ++ case 1687: return NULL; /* ldff1sh --> NULL. */ + case 1674: value = 1675; break; /* ldff1sb --> ldff1sb. */ + case 1675: return NULL; /* ldff1sb --> NULL. */ +- case 1684: value = 1685; break; /* ldff1sh --> ldff1sh. */ +- case 1685: return NULL; /* ldff1sh --> NULL. */ +- case 1672: value = 1673; break; /* ldff1sb --> ldff1sb. */ +- case 1673: return NULL; /* ldff1sb --> NULL. */ +- case 1703: value = 1704; break; /* ldff1w --> ldff1w. */ +- case 1704: return NULL; /* ldff1w --> NULL. */ +- case 1648: value = 1649; break; /* ldff1d --> ldff1d. */ +- case 1649: return NULL; /* ldff1d --> NULL. */ ++ case 1705: value = 1706; break; /* ldff1w --> ldff1w. */ ++ case 1706: return NULL; /* ldff1w --> NULL. */ ++ case 1678: value = 1679; break; /* ldff1sb --> ldff1sb. */ ++ case 1679: return NULL; /* ldff1sb --> NULL. */ ++ case 1688: value = 1689; break; /* ldff1sh --> ldff1sh. */ ++ case 1689: return NULL; /* ldff1sh --> NULL. */ ++ case 1676: value = 1677; break; /* ldff1sb --> ldff1sb. */ ++ case 1677: return NULL; /* ldff1sb --> NULL. */ ++ case 1707: value = 1708; break; /* ldff1w --> ldff1w. */ ++ case 1708: return NULL; /* ldff1w --> NULL. */ ++ case 1652: value = 1653; break; /* ldff1d --> ldff1d. */ ++ case 1653: return NULL; /* ldff1d --> NULL. */ + case 811: value = 812; break; /* xaflag --> axflag. */ + case 812: value = 1194; break; /* axflag --> tcommit. */ +- case 1194: value = 1197; break; /* tcommit --> msr. */ +- case 1197: value = 1198; break; /* msr --> hint. */ +- case 1198: value = 1207; break; /* hint --> dgh. */ +- case 1207: value = 1216; break; /* dgh --> clrex. */ +- case 1216: value = 1217; break; /* clrex --> dsb. */ +- case 1217: value = 1218; break; /* dsb --> dsb. */ +- case 1218: value = 1222; break; /* dsb --> dmb. */ +- case 1222: value = 1223; break; /* dmb --> isb. */ +- case 1223: value = 1224; break; /* isb --> sb. */ +- case 1224: value = 1225; break; /* sb --> sys. */ +- case 1225: value = 1230; break; /* sys --> wfet. */ +- case 1230: value = 1231; break; /* wfet --> wfit. */ +- case 1231: value = 1235; break; /* wfit --> cfinv. */ +- case 1235: value = 1236; break; /* cfinv --> msr. */ +- case 1236: return NULL; /* msr --> NULL. */ ++ case 1194: value = 1197; break; /* tcommit --> smstart. */ ++ case 1197: value = 1198; break; /* smstart --> smstop. */ ++ case 1198: value = 1199; break; /* smstop --> smstart. */ ++ case 1199: value = 1200; break; /* smstart --> smstop. */ ++ case 1200: value = 1201; break; /* smstop --> msr. */ ++ case 1201: value = 1202; break; /* msr --> hint. */ ++ case 1202: value = 1211; break; /* hint --> dgh. */ ++ case 1211: value = 1220; break; /* dgh --> clrex. */ ++ case 1220: value = 1221; break; /* clrex --> dsb. */ ++ case 1221: value = 1222; break; /* dsb --> dsb. */ ++ case 1222: value = 1226; break; /* dsb --> dmb. */ ++ case 1226: value = 1227; break; /* dmb --> isb. */ ++ case 1227: value = 1228; break; /* isb --> sb. */ ++ case 1228: value = 1229; break; /* sb --> sys. */ ++ case 1229: value = 1234; break; /* sys --> wfet. */ ++ case 1234: value = 1235; break; /* wfet --> wfit. */ ++ case 1235: value = 1239; break; /* wfit --> cfinv. */ ++ case 1239: value = 1240; break; /* cfinv --> msr. */ ++ case 1240: return NULL; /* msr --> NULL. */ + case 1193: value = 1195; break; /* tstart --> ttest. */ +- case 1195: value = 1237; break; /* ttest --> sysl. */ +- case 1237: value = 1238; break; /* sysl --> mrs. */ +- case 1238: return NULL; /* mrs --> NULL. */ ++ case 1195: value = 1241; break; /* ttest --> sysl. */ ++ case 1241: value = 1242; break; /* sysl --> mrs. */ ++ case 1242: return NULL; /* mrs --> NULL. */ + case 440: value = 441; break; /* st4 --> st1. */ + case 441: value = 442; break; /* st1 --> st2. */ + case 442: value = 443; break; /* st2 --> st3. */ +@@ -23849,8 +23853,8 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode) + case 824: return NULL; /* fsqrt --> NULL. */ + case 832: value = 833; break; /* frintz --> frintz. */ + case 833: return NULL; /* frintz --> NULL. */ +- case 825: value = 2498; break; /* fcvt --> bfcvt. */ +- case 2498: return NULL; /* bfcvt --> NULL. */ ++ case 825: value = 2502; break; /* fcvt --> bfcvt. */ ++ case 2502: return NULL; /* bfcvt --> NULL. */ + case 834: value = 835; break; /* frinta --> frinta. */ + case 835: return NULL; /* frinta --> NULL. */ + case 836: value = 837; break; /* frintx --> frintx. */ +@@ -24062,41 +24066,41 @@ aarch64_find_alias_opcode (const aarch64_opcode *opcode) + case 1136: value = 1185; break; /* lduminl --> stuminl. */ + case 1186: value = 1187; break; /* movn --> mov. */ + case 1188: value = 1189; break; /* movz --> mov. */ +- case 1198: value = 1246; break; /* hint --> autibsp. */ +- case 1217: value = 1221; break; /* dsb --> pssbb. */ +- case 1218: value = 1218; break; /* dsb --> dsb. */ +- case 1225: value = 1234; break; /* sys --> cpp. */ +- case 1230: value = 1230; break; /* wfet --> wfet. */ +- case 1231: value = 1231; break; /* wfit --> wfit. */ +- case 1294: value = 2044; break; /* and --> bic. */ +- case 1296: value = 1277; break; /* and --> mov. */ +- case 1297: value = 1281; break; /* ands --> movs. */ +- case 1332: value = 2045; break; /* cmpge --> cmple. */ +- case 1335: value = 2048; break; /* cmpgt --> cmplt. */ +- case 1337: value = 2046; break; /* cmphi --> cmplo. */ +- case 1340: value = 2047; break; /* cmphs --> cmpls. */ +- case 1362: value = 1274; break; /* cpy --> mov. */ +- case 1363: value = 1276; break; /* cpy --> mov. */ +- case 1364: value = 2055; break; /* cpy --> fmov. */ +- case 1376: value = 1269; break; /* dup --> mov. */ +- case 1377: value = 1271; break; /* dup --> mov. */ +- case 1378: value = 2054; break; /* dup --> fmov. */ +- case 1379: value = 1272; break; /* dupm --> mov. */ +- case 1381: value = 2049; break; /* eor --> eon. */ +- case 1383: value = 1282; break; /* eor --> not. */ +- case 1384: value = 1283; break; /* eors --> nots. */ +- case 1389: value = 2050; break; /* facge --> facle. */ +- case 1390: value = 2051; break; /* facgt --> faclt. */ +- case 1403: value = 2052; break; /* fcmge --> fcmle. */ +- case 1405: value = 2053; break; /* fcmgt --> fcmlt. */ +- case 1411: value = 1266; break; /* fcpy --> fmov. */ +- case 1434: value = 1265; break; /* fdup --> fmov. */ +- case 1765: value = 1267; break; /* orr --> mov. */ +- case 1766: value = 2056; break; /* orr --> orn. */ +- case 1768: value = 1270; break; /* orr --> mov. */ +- case 1769: value = 1280; break; /* orrs --> movs. */ +- case 1831: value = 1275; break; /* sel --> mov. */ +- case 1832: value = 1278; break; /* sel --> mov. */ ++ case 1202: value = 1250; break; /* hint --> autibsp. */ ++ case 1221: value = 1225; break; /* dsb --> pssbb. */ ++ case 1222: value = 1222; break; /* dsb --> dsb. */ ++ case 1229: value = 1238; break; /* sys --> cpp. */ ++ case 1234: value = 1234; break; /* wfet --> wfet. */ ++ case 1235: value = 1235; break; /* wfit --> wfit. */ ++ case 1298: value = 2048; break; /* and --> bic. */ ++ case 1300: value = 1281; break; /* and --> mov. */ ++ case 1301: value = 1285; break; /* ands --> movs. */ ++ case 1336: value = 2049; break; /* cmpge --> cmple. */ ++ case 1339: value = 2052; break; /* cmpgt --> cmplt. */ ++ case 1341: value = 2050; break; /* cmphi --> cmplo. */ ++ case 1344: value = 2051; break; /* cmphs --> cmpls. */ ++ case 1366: value = 1278; break; /* cpy --> mov. */ ++ case 1367: value = 1280; break; /* cpy --> mov. */ ++ case 1368: value = 2059; break; /* cpy --> fmov. */ ++ case 1380: value = 1273; break; /* dup --> mov. */ ++ case 1381: value = 1275; break; /* dup --> mov. */ ++ case 1382: value = 2058; break; /* dup --> fmov. */ ++ case 1383: value = 1276; break; /* dupm --> mov. */ ++ case 1385: value = 2053; break; /* eor --> eon. */ ++ case 1387: value = 1286; break; /* eor --> not. */ ++ case 1388: value = 1287; break; /* eors --> nots. */ ++ case 1393: value = 2054; break; /* facge --> facle. */ ++ case 1394: value = 2055; break; /* facgt --> faclt. */ ++ case 1407: value = 2056; break; /* fcmge --> fcmle. */ ++ case 1409: value = 2057; break; /* fcmgt --> fcmlt. */ ++ case 1415: value = 1270; break; /* fcpy --> fmov. */ ++ case 1438: value = 1269; break; /* fdup --> fmov. */ ++ case 1769: value = 1271; break; /* orr --> mov. */ ++ case 1770: value = 2060; break; /* orr --> orn. */ ++ case 1772: value = 1274; break; /* orr --> mov. */ ++ case 1773: value = 1284; break; /* orrs --> movs. */ ++ case 1835: value = 1279; break; /* sel --> mov. */ ++ case 1836: value = 1282; break; /* sel --> mov. */ + default: return NULL; + } + +@@ -24222,72 +24226,72 @@ aarch64_find_next_alias_opcode (const aarch64_opcode *opcode) + case 1185: value = 1136; break; /* stuminl --> lduminl. */ + case 1187: value = 1186; break; /* mov --> movn. */ + case 1189: value = 1188; break; /* mov --> movz. */ +- case 1246: value = 1245; break; /* autibsp --> autibz. */ +- case 1245: value = 1244; break; /* autibz --> autiasp. */ +- case 1244: value = 1243; break; /* autiasp --> autiaz. */ +- case 1243: value = 1242; break; /* autiaz --> pacibsp. */ +- case 1242: value = 1241; break; /* pacibsp --> pacibz. */ +- case 1241: value = 1240; break; /* pacibz --> paciasp. */ +- case 1240: value = 1239; break; /* paciasp --> paciaz. */ +- case 1239: value = 1215; break; /* paciaz --> tsb. */ +- case 1215: value = 1214; break; /* tsb --> psb. */ +- case 1214: value = 1213; break; /* psb --> esb. */ +- case 1213: value = 1212; break; /* esb --> autib1716. */ +- case 1212: value = 1211; break; /* autib1716 --> autia1716. */ +- case 1211: value = 1210; break; /* autia1716 --> pacib1716. */ +- case 1210: value = 1209; break; /* pacib1716 --> pacia1716. */ +- case 1209: value = 1208; break; /* pacia1716 --> xpaclri. */ +- case 1208: value = 1206; break; /* xpaclri --> sevl. */ +- case 1206: value = 1205; break; /* sevl --> sev. */ +- case 1205: value = 1204; break; /* sev --> wfi. */ +- case 1204: value = 1203; break; /* wfi --> wfe. */ +- case 1203: value = 1202; break; /* wfe --> yield. */ +- case 1202: value = 1201; break; /* yield --> bti. */ +- case 1201: value = 1200; break; /* bti --> csdb. */ +- case 1200: value = 1199; break; /* csdb --> nop. */ +- case 1199: value = 1198; break; /* nop --> hint. */ +- case 1221: value = 1220; break; /* pssbb --> ssbb. */ +- case 1220: value = 1219; break; /* ssbb --> dfb. */ +- case 1219: value = 1217; break; /* dfb --> dsb. */ +- case 1234: value = 1233; break; /* cpp --> dvp. */ +- case 1233: value = 1232; break; /* dvp --> cfp. */ +- case 1232: value = 1229; break; /* cfp --> tlbi. */ +- case 1229: value = 1228; break; /* tlbi --> ic. */ +- case 1228: value = 1227; break; /* ic --> dc. */ +- case 1227: value = 1226; break; /* dc --> at. */ +- case 1226: value = 1225; break; /* at --> sys. */ +- case 2044: value = 1294; break; /* bic --> and. */ +- case 1277: value = 1296; break; /* mov --> and. */ +- case 1281: value = 1297; break; /* movs --> ands. */ +- case 2045: value = 1332; break; /* cmple --> cmpge. */ +- case 2048: value = 1335; break; /* cmplt --> cmpgt. */ +- case 2046: value = 1337; break; /* cmplo --> cmphi. */ +- case 2047: value = 1340; break; /* cmpls --> cmphs. */ +- case 1274: value = 1362; break; /* mov --> cpy. */ +- case 1276: value = 1363; break; /* mov --> cpy. */ +- case 2055: value = 1279; break; /* fmov --> mov. */ +- case 1279: value = 1364; break; /* mov --> cpy. */ +- case 1269: value = 1376; break; /* mov --> dup. */ +- case 1271: value = 1268; break; /* mov --> mov. */ +- case 1268: value = 1377; break; /* mov --> dup. */ +- case 2054: value = 1273; break; /* fmov --> mov. */ +- case 1273: value = 1378; break; /* mov --> dup. */ +- case 1272: value = 1379; break; /* mov --> dupm. */ +- case 2049: value = 1381; break; /* eon --> eor. */ +- case 1282: value = 1383; break; /* not --> eor. */ +- case 1283: value = 1384; break; /* nots --> eors. */ +- case 2050: value = 1389; break; /* facle --> facge. */ +- case 2051: value = 1390; break; /* faclt --> facgt. */ +- case 2052: value = 1403; break; /* fcmle --> fcmge. */ +- case 2053: value = 1405; break; /* fcmlt --> fcmgt. */ +- case 1266: value = 1411; break; /* fmov --> fcpy. */ +- case 1265: value = 1434; break; /* fmov --> fdup. */ +- case 1267: value = 1765; break; /* mov --> orr. */ +- case 2056: value = 1766; break; /* orn --> orr. */ +- case 1270: value = 1768; break; /* mov --> orr. */ +- case 1280: value = 1769; break; /* movs --> orrs. */ +- case 1275: value = 1831; break; /* mov --> sel. */ +- case 1278: value = 1832; break; /* mov --> sel. */ ++ case 1250: value = 1249; break; /* autibsp --> autibz. */ ++ case 1249: value = 1248; break; /* autibz --> autiasp. */ ++ case 1248: value = 1247; break; /* autiasp --> autiaz. */ ++ case 1247: value = 1246; break; /* autiaz --> pacibsp. */ ++ case 1246: value = 1245; break; /* pacibsp --> pacibz. */ ++ case 1245: value = 1244; break; /* pacibz --> paciasp. */ ++ case 1244: value = 1243; break; /* paciasp --> paciaz. */ ++ case 1243: value = 1219; break; /* paciaz --> tsb. */ ++ case 1219: value = 1218; break; /* tsb --> psb. */ ++ case 1218: value = 1217; break; /* psb --> esb. */ ++ case 1217: value = 1216; break; /* esb --> autib1716. */ ++ case 1216: value = 1215; break; /* autib1716 --> autia1716. */ ++ case 1215: value = 1214; break; /* autia1716 --> pacib1716. */ ++ case 1214: value = 1213; break; /* pacib1716 --> pacia1716. */ ++ case 1213: value = 1212; break; /* pacia1716 --> xpaclri. */ ++ case 1212: value = 1210; break; /* xpaclri --> sevl. */ ++ case 1210: value = 1209; break; /* sevl --> sev. */ ++ case 1209: value = 1208; break; /* sev --> wfi. */ ++ case 1208: value = 1207; break; /* wfi --> wfe. */ ++ case 1207: value = 1206; break; /* wfe --> yield. */ ++ case 1206: value = 1205; break; /* yield --> bti. */ ++ case 1205: value = 1204; break; /* bti --> csdb. */ ++ case 1204: value = 1203; break; /* csdb --> nop. */ ++ case 1203: value = 1202; break; /* nop --> hint. */ ++ case 1225: value = 1224; break; /* pssbb --> ssbb. */ ++ case 1224: value = 1223; break; /* ssbb --> dfb. */ ++ case 1223: value = 1221; break; /* dfb --> dsb. */ ++ case 1238: value = 1237; break; /* cpp --> dvp. */ ++ case 1237: value = 1236; break; /* dvp --> cfp. */ ++ case 1236: value = 1233; break; /* cfp --> tlbi. */ ++ case 1233: value = 1232; break; /* tlbi --> ic. */ ++ case 1232: value = 1231; break; /* ic --> dc. */ ++ case 1231: value = 1230; break; /* dc --> at. */ ++ case 1230: value = 1229; break; /* at --> sys. */ ++ case 2048: value = 1298; break; /* bic --> and. */ ++ case 1281: value = 1300; break; /* mov --> and. */ ++ case 1285: value = 1301; break; /* movs --> ands. */ ++ case 2049: value = 1336; break; /* cmple --> cmpge. */ ++ case 2052: value = 1339; break; /* cmplt --> cmpgt. */ ++ case 2050: value = 1341; break; /* cmplo --> cmphi. */ ++ case 2051: value = 1344; break; /* cmpls --> cmphs. */ ++ case 1278: value = 1366; break; /* mov --> cpy. */ ++ case 1280: value = 1367; break; /* mov --> cpy. */ ++ case 2059: value = 1283; break; /* fmov --> mov. */ ++ case 1283: value = 1368; break; /* mov --> cpy. */ ++ case 1273: value = 1380; break; /* mov --> dup. */ ++ case 1275: value = 1272; break; /* mov --> mov. */ ++ case 1272: value = 1381; break; /* mov --> dup. */ ++ case 2058: value = 1277; break; /* fmov --> mov. */ ++ case 1277: value = 1382; break; /* mov --> dup. */ ++ case 1276: value = 1383; break; /* mov --> dupm. */ ++ case 2053: value = 1385; break; /* eon --> eor. */ ++ case 1286: value = 1387; break; /* not --> eor. */ ++ case 1287: value = 1388; break; /* nots --> eors. */ ++ case 2054: value = 1393; break; /* facle --> facge. */ ++ case 2055: value = 1394; break; /* faclt --> facgt. */ ++ case 2056: value = 1407; break; /* fcmle --> fcmge. */ ++ case 2057: value = 1409; break; /* fcmlt --> fcmgt. */ ++ case 1270: value = 1415; break; /* fmov --> fcpy. */ ++ case 1269: value = 1438; break; /* fmov --> fdup. */ ++ case 1271: value = 1769; break; /* mov --> orr. */ ++ case 2060: value = 1770; break; /* orn --> orr. */ ++ case 1274: value = 1772; break; /* mov --> orr. */ ++ case 1284: value = 1773; break; /* movs --> orrs. */ ++ case 1279: value = 1835; break; /* mov --> sel. */ ++ case 1282: value = 1836; break; /* mov --> sel. */ + default: return NULL; + } + +@@ -24369,7 +24373,7 @@ aarch64_extract_operand (const aarch64_operand *self, + case 33: + case 34: + case 35: +- case 220: ++ case 221: + return aarch64_ext_reglane (self, info, code, inst, errors); + case 36: + return aarch64_ext_reglist (self, info, code, inst, errors); +@@ -24416,7 +24420,7 @@ aarch64_extract_operand (const aarch64_operand *self, + case 189: + case 190: + case 215: +- case 219: ++ case 220: + return aarch64_ext_imm (self, info, code, inst, errors); + case 44: + case 45: +@@ -24586,6 +24590,8 @@ aarch64_extract_operand (const aarch64_operand *self, + return aarch64_ext_sme_za_array (self, info, code, inst, errors); + case 218: + return aarch64_ext_sme_addr_ri_u4xvl (self, info, code, inst, errors); ++ case 219: ++ return aarch64_ext_sme_sm_za (self, info, code, inst, errors); + default: assert (0); abort (); + } + } +diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c +index e8a0bd98..0121383a 100644 +--- a/opcodes/aarch64-dis.c ++++ b/opcodes/aarch64-dis.c +@@ -663,7 +663,7 @@ aarch64_ext_shll_imm (const aarch64_operand *self ATTRIBUTE_UNUSED, + bool + aarch64_ext_imm (const aarch64_operand *self, aarch64_opnd_info *info, + const aarch64_insn code, +- const aarch64_inst *inst ATTRIBUTE_UNUSED, ++ const aarch64_inst *inst, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) + { + uint64_t imm; +@@ -681,6 +681,10 @@ aarch64_ext_imm (const aarch64_operand *self, aarch64_opnd_info *info, + if (info->type == AARCH64_OPND_ADDR_ADRP) + imm <<= 12; + ++ if (inst->operands[0].type == AARCH64_OPND_PSTATEFIELD ++ && inst->operands[0].sysreg.flags & F_IMM_IN_CRM) ++ imm &= PSTATE_DECODE_CRM_IMM (inst->operands[0].sysreg.flags); ++ + info->imm.value = imm; + return true; + } +@@ -1225,11 +1229,20 @@ aarch64_ext_pstatefield (const aarch64_operand *self ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) + { + int i; ++ aarch64_insn fld_crm = extract_field (FLD_CRm, code, 0); + /* op1:op2 */ + info->pstatefield = extract_fields (code, 0, 2, FLD_op1, FLD_op2); + for (i = 0; aarch64_pstatefields[i].name != NULL; ++i) + if (aarch64_pstatefields[i].value == (aarch64_insn)info->pstatefield) +- return true; ++ { ++ /* PSTATEFIELD name can be encoded partially in CRm[3:1]. */ ++ uint32_t flags = aarch64_pstatefields[i].flags; ++ if ((flags & F_REG_IN_CRM) ++ && ((fld_crm & 0xe) != PSTATE_DECODE_CRM (flags))) ++ continue; ++ info->sysreg.flags = flags; ++ return true; ++ } + /* Reserved value in . */ + return false; + } +@@ -1855,6 +1868,27 @@ aarch64_ext_sme_addr_ri_u4xvl (const aarch64_operand *self, + return true; + } + ++/* Decode {SM|ZA} filed for SMSTART and SMSTOP instructions. */ ++bool ++aarch64_ext_sme_sm_za (const aarch64_operand *self, ++ aarch64_opnd_info *info, aarch64_insn code, ++ const aarch64_inst *inst ATTRIBUTE_UNUSED, ++ aarch64_operand_error *errors ATTRIBUTE_UNUSED) ++{ ++ info->pstatefield = 0x1b; ++ aarch64_insn fld_crm = extract_field (self->fields[0], code, 0); ++ fld_crm >>= 1; /* CRm[3:1]. */ ++ ++ if (fld_crm == 0x1) ++ info->reg.regno = 's'; ++ else if (fld_crm == 0x2) ++ info->reg.regno = 'z'; ++ else ++ assert (0); ++ ++ return true; ++} ++ + /* Decode Zn[MM], where MM has a 7-bit triangular encoding. The fields + array specifies which field to use for Zn. MM is encoded in the + concatenation of imm5 and SVE_tszh, with imm5 being the less +diff --git a/opcodes/aarch64-dis.h b/opcodes/aarch64-dis.h +index 893800b2..3366dfbc 100644 +--- a/opcodes/aarch64-dis.h ++++ b/opcodes/aarch64-dis.h +@@ -126,6 +126,7 @@ AARCH64_DECL_OPD_EXTRACTOR (ext_sme_za_hv_tiles); + AARCH64_DECL_OPD_EXTRACTOR (ext_sme_za_list); + AARCH64_DECL_OPD_EXTRACTOR (ext_sme_za_array); + AARCH64_DECL_OPD_EXTRACTOR (ext_sme_addr_ri_u4xvl); ++AARCH64_DECL_OPD_EXTRACTOR (ext_sme_sm_za); + AARCH64_DECL_OPD_EXTRACTOR (ext_imm_rotate1); + AARCH64_DECL_OPD_EXTRACTOR (ext_imm_rotate2); + +diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c +index 5dedf211..75b7f86d 100644 +--- a/opcodes/aarch64-opc-2.c ++++ b/opcodes/aarch64-opc-2.c +@@ -243,6 +243,7 @@ const struct aarch64_operand aarch64_operands[] = + {AARCH64_OPND_CLASS_SVE_REG, "SME_ZA_HV_idx_ldstr", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_10,FLD_index2,FLD_SME_V,FLD_SME_Rv,FLD_imm4_2}, "an SME horizontal or vertical vector access register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_ZA_array", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rv,FLD_imm4_2}, "ZA array"}, + {AARCH64_OPND_CLASS_ADDRESS, "SME_ADDR_RI_U4xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm4_2}, "memory offset"}, ++ {AARCH64_OPND_CLASS_ADDRESS, "SME_SM_ZA", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "streaming mode"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "TME_UIMM16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16}, "a 16-bit unsigned immediate for TME tcancel"}, + {AARCH64_OPND_CLASS_SIMD_ELEMENT, "SM3_IMM2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SM3_imm2}, "an indexed SM3 vector immediate"}, + {AARCH64_OPND_CLASS_NIL, "", 0, {0}, "DUMMY"}, +@@ -322,17 +323,17 @@ static const unsigned op_enum_table [] = + 391, + 413, + 415, +- 1270, +- 1275, +- 1268, +- 1267, ++ 1274, ++ 1279, ++ 1272, + 1271, +- 1278, +- 1280, +- 1281, +- 1277, +- 1283, ++ 1275, + 1282, ++ 1284, ++ 1285, ++ 1281, ++ 1287, ++ 1286, + 131, + }; + +diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c +index e46763d7..dba8bcba 100644 +--- a/opcodes/aarch64-opc.c ++++ b/opcodes/aarch64-opc.c +@@ -1520,7 +1520,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, + if (!aarch64_stack_pointer_p (opnd)) + { + set_other_error (mismatch_detail, idx, +- _("stack pointer register expected")); ++ _("stack pointer register expected")); + return 0; + } + break; +@@ -2592,11 +2592,15 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, + /* MSR UAO, #uimm4 + MSR PAN, #uimm4 + MSR SSBS,#uimm4 ++ MSR SVCRSM, #uimm4 ++ MSR SVCRZA, #uimm4 ++ MSR SVCRSMZA, #uimm4 + The immediate must be #0 or #1. */ + if ((opnd->pstatefield == 0x03 /* UAO. */ + || opnd->pstatefield == 0x04 /* PAN. */ + || opnd->pstatefield == 0x19 /* SSBS. */ +- || opnd->pstatefield == 0x1a) /* DIT. */ ++ || opnd->pstatefield == 0x1a /* DIT. */ ++ || opnd->pstatefield == 0x1b) /* SVCRSM, SVCRZA or SVCRSMZA. */ + && opnds[1].imm.value > 1) + { + set_imm_out_of_range_error (mismatch_detail, idx, 0, 1); +@@ -3465,6 +3469,10 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, + opnd->za_tile_vector.index.imm); + break; + ++ case AARCH64_OPND_SME_SM_ZA: ++ snprintf (buf, size, "%s", opnd->reg.regno == 's' ? "sm" : "za"); ++ break; ++ + case AARCH64_OPND_CRn: + case AARCH64_OPND_CRm: + snprintf (buf, size, "C%" PRIi64, opnd->imm.value); +@@ -3861,8 +3869,17 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, + + case AARCH64_OPND_PSTATEFIELD: + for (i = 0; aarch64_pstatefields[i].name; ++i) +- if (aarch64_pstatefields[i].value == opnd->pstatefield) +- break; ++ if (aarch64_pstatefields[i].value == opnd->pstatefield) ++ { ++ /* PSTATEFIELD name is encoded partially in CRm[3:1] for SVCRSM, ++ SVCRZA and SVCRSMZA. */ ++ uint32_t flags = aarch64_pstatefields[i].flags; ++ if (flags & F_REG_IN_CRM ++ && (PSTATE_DECODE_CRM (opnd->sysreg.flags) ++ != PSTATE_DECODE_CRM (flags))) ++ continue; ++ break; ++ } + assert (aarch64_pstatefields[i].name); + snprintf (buf, size, "%s", aarch64_pstatefields[i].name); + break; +@@ -3958,6 +3975,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, + #define SR_V8_4(n,e,f) SR_FEAT (n,e,f,V8_4) + #define SR_PAN(n,e,f) SR_FEAT (n,e,f,PAN) + #define SR_RAS(n,e,f) SR_FEAT (n,e,f,RAS) ++#define SR_SME(n,e,f) SR_FEAT (n,e,f,SME) + #define SR_SSBS(n,e,f) SR_FEAT (n,e,f,SSBS) + #define SR_SVE(n,e,f) SR_FEAT (n,e,f,SVE) + #define SR_ID_PFR2(n,e,f) SR_FEAT (n,e,f,ID_PFR2) +@@ -4808,6 +4826,8 @@ const aarch64_sys_reg aarch64_sys_regs [] = + SR_CORE ("gpccr_el3", CPENC (3,6,C2,C1,6), 0), + SR_CORE ("gptbr_el3", CPENC (3,6,C2,C1,4), 0), + ++ SR_SME ("svcr", CPENC (3,3,C4,C2,2), 0), ++ + { 0, CPENC (0,0,0,0,0), 0, 0 } + }; + +@@ -4834,6 +4854,9 @@ const aarch64_sys_reg aarch64_pstatefields [] = + SR_SSBS ("ssbs", 0x19, 0), + SR_V8_4 ("dit", 0x1a, 0), + SR_MEMTAG ("tco", 0x1c, 0), ++ SR_SME ("svcrsm", 0x1b, PSTATE_ENCODE_CRM_AND_IMM(0x2,0x1)), ++ SR_SME ("svcrza", 0x1b, PSTATE_ENCODE_CRM_AND_IMM(0x4,0x1)), ++ SR_SME ("svcrsmza", 0x1b, PSTATE_ENCODE_CRM_AND_IMM(0x6,0x1)), + { 0, CPENC (0,0,0,0,0), 0, 0 }, + }; + +diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h +index 62aad8bf..f3000fca 100644 +--- a/opcodes/aarch64-opc.h ++++ b/opcodes/aarch64-opc.h +@@ -243,6 +243,32 @@ verify_constraints (const struct aarch64_inst *, const aarch64_insn, bfd_vma, + #define F_REG_WRITE (1 << 4) /* Register can only be written to but not + read from. */ + ++#undef F_REG_IN_CRM ++#define F_REG_IN_CRM (1 << 5) /* Register extra encoding in CRm. */ ++ ++/* PSTATE field name for the MSR instruction this is encoded in "op1:op2:CRm". ++ Part of CRm can be used to encode . E.g. CRm[3:1] for SME. ++ In order to set/get full PSTATE field name use flag F_REG_IN_CRM and below ++ macros to encode and decode CRm encoding. ++*/ ++#define PSTATE_ENCODE_CRM(val) (val << 6) ++#define PSTATE_DECODE_CRM(flags) ((flags >> 6) & 0x0f) ++ ++#undef F_IMM_IN_CRM ++#define F_IMM_IN_CRM (1 << 10) /* Immediate extra encoding in CRm. */ ++ ++/* Also CRm may contain, in addition to immediate. ++ E.g. CRm[0] at bit 0 for SME. Use below macros to encode and decode ++ immediate mask. ++*/ ++#define PSTATE_ENCODE_CRM_IMM(mask) (mask << 11) ++#define PSTATE_DECODE_CRM_IMM(mask) ((mask >> 11) & 0x0f) ++ ++/* Helper macro to ENCODE CRm and its immediate. */ ++#define PSTATE_ENCODE_CRM_AND_IMM(CVAL,IMASK) \ ++ (F_REG_IN_CRM | PSTATE_ENCODE_CRM(CVAL) \ ++ | F_IMM_IN_CRM | PSTATE_ENCODE_CRM_IMM(IMASK)) ++ + /* HINT operand flags. */ + #define HINT_OPD_F_NOPRINT (1 << 0) /* Should not be printed. */ + +diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h +index d74009be..820b0820 100644 +--- a/opcodes/aarch64-tbl.h ++++ b/opcodes/aarch64-tbl.h +@@ -3933,6 +3933,11 @@ const struct aarch64_opcode aarch64_opcode_table[] = + _TME_INSN ("tcommit", 0xd503307f, 0xffffffff, 0, 0, OP0 (), {}, 0), + _TME_INSN ("ttest", 0xd5233160, 0xffffffe0, 0, 0, OP1 (Rd), QL_I1X, 0), + _TME_INSN ("tcancel", 0xd4600000, 0xffe0001f, 0, 0, OP1 (TME_UIMM16), QL_IMM_NIL, 0), ++ /* SME instructions (aliases for MSR operations. */ ++ SME_INSN ("smstart", 0xd503477f, 0xffffffff, sme_start, 0, OP0 (), {}, F_SYS_WRITE, 0), ++ SME_INSN ("smstop", 0xd503467f, 0xffffffff, sme_stop, 0, OP0 (), {}, F_SYS_WRITE, 0), ++ SME_INSN ("smstart", 0xd503417f, 0xfffff1ff, sme_start, 0, OP1 (SME_SM_ZA), {}, F_SYS_WRITE, 0), ++ SME_INSN ("smstop", 0xd503407f, 0xfffff1ff, sme_stop, 0, OP1 (SME_SM_ZA), {}, F_SYS_WRITE, 0), + /* System. */ + CORE_INSN ("msr", 0xd500401f, 0xfff8f01f, ic_system, 0, OP2 (PSTATEFIELD, UIMM4), {}, F_SYS_WRITE), + CORE_INSN ("hint",0xd503201f, 0xfffff01f, ic_system, 0, OP1 (UIMM7), {}, F_HAS_ALIAS), +@@ -5765,6 +5770,9 @@ const struct aarch64_opcode aarch64_opcode_table[] = + Y(ADDRESS, sme_addr_ri_u4xvl, "SME_ADDR_RI_U4xVL", 0 << OPD_F_OD_LSB, \ + F(FLD_Rn,FLD_imm4_2), \ + "memory offset") \ ++ Y(ADDRESS, sme_sm_za, "SME_SM_ZA", 0, \ ++ F(FLD_CRm), \ ++ "streaming mode") \ + Y(IMMEDIATE, imm, "TME_UIMM16", 0, F(FLD_imm16), \ + "a 16-bit unsigned immediate for TME tcancel") \ + Y(SIMD_ELEMENT, reglane, "SM3_IMM2", 0, F(FLD_SM3_imm2), \ +-- +2.19.1 + diff --git a/SME-0007-aarch64-SME-Add-new-SME-system-registers.patch b/SME-0007-aarch64-SME-Add-new-SME-system-registers.patch new file mode 100644 index 0000000000000000000000000000000000000000..24d17902509a7a620660327319032b7372b538be --- /dev/null +++ b/SME-0007-aarch64-SME-Add-new-SME-system-registers.patch @@ -0,0 +1,153 @@ +From dd79dd44a7e7ebc7533cfdb60f94fe2a4657ce27 Mon Sep 17 00:00:00 2001 +From: Przemyslaw Wirkus +Date: Wed, 17 Nov 2021 20:20:50 +0000 +Subject: [PATCH 07/10] aarch64: [SME] Add new SME system registers + +Reference: https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=8f1bfdb44894423680a6d56a0994dafb4b82efca + +This patch is adding miscellaneous SME related system registers. + +gas/ChangeLog: + + * testsuite/gas/aarch64/sme-sysreg.d: New test. + * testsuite/gas/aarch64/sme-sysreg.s: New test. + * testsuite/gas/aarch64/sme-sysreg-illegal.d: New test. + * testsuite/gas/aarch64/sme-sysreg-illegal.l: New test. + * testsuite/gas/aarch64/sme-sysreg-illegal.s: New test. + +opcodes/ChangeLog: + + * aarch64-opc.c: New system registers id_aa64smfr0_el1, + smcr_el1, smcr_el12, smcr_el2, smcr_el3, smpri_el1, + smprimap_el2, smidr_el1, tpidr2_el0 and mpamsm_el1. +--- + .../gas/aarch64/sme-sysreg-illegal.d | 3 ++ + .../gas/aarch64/sme-sysreg-illegal.l | 3 ++ + .../gas/aarch64/sme-sysreg-illegal.s | 3 ++ + gas/testsuite/gas/aarch64/sme-sysreg.d | 29 +++++++++++++++++++ + gas/testsuite/gas/aarch64/sme-sysreg.s | 23 +++++++++++++++ + opcodes/aarch64-opc.c | 12 +++++++- + 6 files changed, 72 insertions(+), 1 deletion(-) + create mode 100644 gas/testsuite/gas/aarch64/sme-sysreg-illegal.d + create mode 100644 gas/testsuite/gas/aarch64/sme-sysreg-illegal.l + create mode 100644 gas/testsuite/gas/aarch64/sme-sysreg-illegal.s + create mode 100644 gas/testsuite/gas/aarch64/sme-sysreg.d + create mode 100644 gas/testsuite/gas/aarch64/sme-sysreg.s + +diff --git a/gas/testsuite/gas/aarch64/sme-sysreg-illegal.d b/gas/testsuite/gas/aarch64/sme-sysreg-illegal.d +new file mode 100644 +index 00000000..ff0e855f +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/sme-sysreg-illegal.d +@@ -0,0 +1,3 @@ ++#as: -march=armv8-a+sme ++#source: sme-sysreg-illegal.s ++#warning_output: sme-sysreg-illegal.l +diff --git a/gas/testsuite/gas/aarch64/sme-sysreg-illegal.l b/gas/testsuite/gas/aarch64/sme-sysreg-illegal.l +new file mode 100644 +index 00000000..6baad135 +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/sme-sysreg-illegal.l +@@ -0,0 +1,3 @@ ++[^:]*: Assembler messages: ++[^:]*:[0-9]+: Warning: specified register cannot be written to at operand 1 -- `msr id_aa64smfr0_el1,x0' ++[^:]*:[0-9]+: Warning: specified register cannot be written to at operand 1 -- `msr smidr_el1,x0' +diff --git a/gas/testsuite/gas/aarch64/sme-sysreg-illegal.s b/gas/testsuite/gas/aarch64/sme-sysreg-illegal.s +new file mode 100644 +index 00000000..057a6bf0 +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/sme-sysreg-illegal.s +@@ -0,0 +1,3 @@ ++/* Write to r/o SME system registers. */ ++msr id_aa64smfr0_el1, x0 ++msr smidr_el1, x0 +diff --git a/gas/testsuite/gas/aarch64/sme-sysreg.d b/gas/testsuite/gas/aarch64/sme-sysreg.d +new file mode 100644 +index 00000000..8eaf73ca +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/sme-sysreg.d +@@ -0,0 +1,29 @@ ++#name: SME extension (system registers) ++#as: -march=armv8-a+sme ++#objdump: -dr ++ ++.*: file format .* ++ ++Disassembly of section \.text: ++ ++0+ <.*>: ++ 0: d53b4240 mrs x0, svcr ++ 4: d53804a0 mrs x0, id_aa64smfr0_el1 ++ 8: d53812c0 mrs x0, smcr_el1 ++ c: d53d12c0 mrs x0, smcr_el12 ++ 10: d53c12c0 mrs x0, smcr_el2 ++ 14: d53e12c0 mrs x0, smcr_el3 ++ 18: d5381280 mrs x0, smpri_el1 ++ 1c: d53c12a0 mrs x0, smprimap_el2 ++ 20: d53900c0 mrs x0, smidr_el1 ++ 24: d53bd0a0 mrs x0, tpidr2_el0 ++ 28: d538a560 mrs x0, mpamsm_el1 ++ 2c: d51b4240 msr svcr, x0 ++ 30: d51812c0 msr smcr_el1, x0 ++ 34: d51d12c0 msr smcr_el12, x0 ++ 38: d51c12c0 msr smcr_el2, x0 ++ 3c: d51e12c0 msr smcr_el3, x0 ++ 40: d5181280 msr smpri_el1, x0 ++ 44: d51c12a0 msr smprimap_el2, x0 ++ 48: d51bd0a0 msr tpidr2_el0, x0 ++ 4c: d518a560 msr mpamsm_el1, x0 +diff --git a/gas/testsuite/gas/aarch64/sme-sysreg.s b/gas/testsuite/gas/aarch64/sme-sysreg.s +new file mode 100644 +index 00000000..ce8a2942 +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/sme-sysreg.s +@@ -0,0 +1,23 @@ ++/* Read SME system registers. */ ++mrs x0, svcr ++mrs x0, id_aa64smfr0_el1 ++mrs x0, smcr_el1 ++mrs x0, smcr_el12 ++mrs x0, smcr_el2 ++mrs x0, smcr_el3 ++mrs x0, smpri_el1 ++mrs x0, smprimap_el2 ++mrs x0, smidr_el1 ++mrs x0, tpidr2_el0 ++mrs x0, mpamsm_el1 ++ ++/* Write to SME system registers. */ ++msr svcr, x0 ++msr smcr_el1, x0 ++msr smcr_el12, x0 ++msr smcr_el2, x0 ++msr smcr_el3, x0 ++msr smpri_el1, x0 ++msr smprimap_el2, x0 ++msr tpidr2_el0, x0 ++msr mpamsm_el1, x0 +diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c +index dba8bcba..923ddefe 100644 +--- a/opcodes/aarch64-opc.c ++++ b/opcodes/aarch64-opc.c +@@ -4826,7 +4826,17 @@ const aarch64_sys_reg aarch64_sys_regs [] = + SR_CORE ("gpccr_el3", CPENC (3,6,C2,C1,6), 0), + SR_CORE ("gptbr_el3", CPENC (3,6,C2,C1,4), 0), + +- SR_SME ("svcr", CPENC (3,3,C4,C2,2), 0), ++ SR_SME ("svcr", CPENC (3,3,C4,C2,2), 0), ++ SR_SME ("id_aa64smfr0_el1", CPENC (3,0,C0,C4,5), F_REG_READ), ++ SR_SME ("smcr_el1", CPENC (3,0,C1,C2,6), 0), ++ SR_SME ("smcr_el12", CPENC (3,5,C1,C2,6), 0), ++ SR_SME ("smcr_el2", CPENC (3,4,C1,C2,6), 0), ++ SR_SME ("smcr_el3", CPENC (3,6,C1,C2,6), 0), ++ SR_SME ("smpri_el1", CPENC (3,0,C1,C2,4), 0), ++ SR_SME ("smprimap_el2", CPENC (3,4,C1,C2,5), 0), ++ SR_SME ("smidr_el1", CPENC (3,1,C0,C0,6), F_REG_READ), ++ SR_SME ("tpidr2_el0", CPENC (3,3,C13,C0,5), 0), ++ SR_SME ("mpamsm_el1", CPENC (3,0,C10,C5,3), 0), + + { 0, CPENC (0,0,0,0,0), 0, 0 } + }; +-- +2.19.1 + diff --git a/SME-0008-aarch64-SME-SVE2-instructions-added-to-support-SME.patch b/SME-0008-aarch64-SME-SVE2-instructions-added-to-support-SME.patch new file mode 100644 index 0000000000000000000000000000000000000000..15b148964d31c5f7e48368f8c6dbc6cb01805aeb --- /dev/null +++ b/SME-0008-aarch64-SME-SVE2-instructions-added-to-support-SME.patch @@ -0,0 +1,1980 @@ +From 88bdc72512cf5e86b1f31b1f7732477177224f1c Mon Sep 17 00:00:00 2001 +From: Przemyslaw Wirkus +Date: Wed, 17 Nov 2021 20:26:53 +0000 +Subject: [PATCH 08/10] aarch64: [SME] SVE2 instructions added to support SME + +Reference: https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=d3de0860104b8bb8d496527fbb042c3b4c5c82dc + +This patch is adding new SVE2 instructions added to support SME extension. +The following SVE2 instructions are added by the SME architecture: +* PSEL, +* REVD, SCLAMP and UCLAMP. + +gas/ChangeLog: + + * config/tc-aarch64.c (parse_sme_pred_reg_with_index): + New parser. + (parse_operands): New parser. + * testsuite/gas/aarch64/sme-9-illegal.d: New test. + * testsuite/gas/aarch64/sme-9-illegal.l: New test. + * testsuite/gas/aarch64/sme-9-illegal.s: New test. + * testsuite/gas/aarch64/sme-9.d: New test. + * testsuite/gas/aarch64/sme-9.s: New test. + +include/ChangeLog: + + * opcode/aarch64.h (enum aarch64_opnd): New operand + AARCH64_OPND_SME_PnT_Wm_imm. + +opcodes/ChangeLog: + + * aarch64-asm.c (aarch64_ins_sme_pred_reg_with_index): + New inserter. + * aarch64-dis.c (aarch64_ext_sme_pred_reg_with_index): + New extractor. + * aarch64-opc.c (aarch64_print_operand): Printout of + OPND_SME_PnT_Wm_imm. + * aarch64-opc.h (enum aarch64_field_kind): New bitfields + FLD_SME_Rm, FLD_SME_i1, FLD_SME_tszh, FLD_SME_tszl. + * aarch64-tbl.h (OP_SVE_NN_BHSD): New qualifier. + (OP_SVE_QMQ): New qualifier. + (struct aarch64_opcode): New instructions PSEL, REVD, + SCLAMP and UCLAMP. + aarch64-asm-2.c: Regenerate. + aarch64-dis-2.c: Regenerate. + aarch64-opc-2.c: Regenerate. +--- + gas/config/tc-aarch64.c | 78 ++++ + gas/testsuite/gas/aarch64/sme-9-illegal.d | 3 + + gas/testsuite/gas/aarch64/sme-9-illegal.l | 83 +++++ + gas/testsuite/gas/aarch64/sme-9-illegal.s | 25 ++ + gas/testsuite/gas/aarch64/sme-9.d | 73 ++++ + gas/testsuite/gas/aarch64/sme-9.s | 86 +++++ + include/opcode/aarch64.h | 1 + + opcodes/aarch64-asm-2.c | 6 +- + opcodes/aarch64-asm.c | 67 ++++ + opcodes/aarch64-asm.h | 1 + + opcodes/aarch64-dis-2.c | 424 ++++++++++++---------- + opcodes/aarch64-dis.c | 43 +++ + opcodes/aarch64-dis.h | 1 + + opcodes/aarch64-opc-2.c | 1 + + opcodes/aarch64-opc.c | 12 + + opcodes/aarch64-opc.h | 4 + + opcodes/aarch64-tbl.h | 19 + + 17 files changed, 736 insertions(+), 191 deletions(-) + create mode 100644 gas/testsuite/gas/aarch64/sme-9-illegal.d + create mode 100644 gas/testsuite/gas/aarch64/sme-9-illegal.l + create mode 100644 gas/testsuite/gas/aarch64/sme-9-illegal.s + create mode 100644 gas/testsuite/gas/aarch64/sme-9.d + create mode 100644 gas/testsuite/gas/aarch64/sme-9.s + +diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c +index 069fe14e..ea58d9b0 100644 +--- a/gas/config/tc-aarch64.c ++++ b/gas/config/tc-aarch64.c +@@ -4703,6 +4703,65 @@ parse_sme_sm_za (char **str) + return TOLOWER (p[0]); + } + ++/* Parse the name of the source scalable predicate register, the index base ++ register W12-W15 and the element index. Function performs element index ++ limit checks as well as qualifier type checks. ++ ++ .[, ] ++ .[, #] ++ ++ On success function sets to INDEX_BASE_REG, to QUALIFIER and ++ to IMM. ++ Function returns , or PARSE_FAIL. ++*/ ++static int ++parse_sme_pred_reg_with_index(char **str, ++ int *index_base_reg, ++ int *imm, ++ aarch64_opnd_qualifier_t *qualifier) ++{ ++ int regno; ++ int64_t imm_limit; ++ int64_t imm_value; ++ const reg_entry *reg = parse_reg_with_qual (str, REG_TYPE_PN, qualifier); ++ ++ if (reg == NULL) ++ return PARSE_FAIL; ++ regno = reg->number; ++ ++ switch (*qualifier) ++ { ++ case AARCH64_OPND_QLF_S_B: ++ imm_limit = 15; ++ break; ++ case AARCH64_OPND_QLF_S_H: ++ imm_limit = 7; ++ break; ++ case AARCH64_OPND_QLF_S_S: ++ imm_limit = 3; ++ break; ++ case AARCH64_OPND_QLF_S_D: ++ imm_limit = 1; ++ break; ++ default: ++ set_syntax_error (_("wrong predicate register element size, allowed b, h, s and d")); ++ return PARSE_FAIL; ++ } ++ ++ if (! parse_sme_za_hv_tiles_operand_index (str, index_base_reg, &imm_value)) ++ return PARSE_FAIL; ++ ++ if (imm_value < 0 || imm_value > imm_limit) ++ { ++ set_syntax_error (_("element index out of range for given variant")); ++ return PARSE_FAIL; ++ } ++ ++ *imm = imm_value; ++ ++ return regno; ++} ++ + /* Parse a system register or a PSTATE field name for an MSR/MRS instruction. + Returns the encoding for the option, or PARSE_FAIL. + +@@ -7116,6 +7175,25 @@ parse_operands (char *str, const aarch64_opcode *opcode) + info->reg.regno = val; + break; + ++ case AARCH64_OPND_SME_PnT_Wm_imm: ++ /* .[, #] */ ++ { ++ int index_base_reg; ++ int imm; ++ val = parse_sme_pred_reg_with_index (&str, ++ &index_base_reg, ++ &imm, ++ &qualifier); ++ if (val == PARSE_FAIL) ++ goto failure; ++ ++ info->za_tile_vector.regno = val; ++ info->za_tile_vector.index.regno = index_base_reg; ++ info->za_tile_vector.index.imm = imm; ++ info->qualifier = qualifier; ++ break; ++ } ++ + case AARCH64_OPND_SVE_ADDR_RI_S4x16: + case AARCH64_OPND_SVE_ADDR_RI_S4x32: + case AARCH64_OPND_SVE_ADDR_RI_S4xVL: +diff --git a/gas/testsuite/gas/aarch64/sme-9-illegal.d b/gas/testsuite/gas/aarch64/sme-9-illegal.d +new file mode 100644 +index 00000000..65ed0d3d +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/sme-9-illegal.d +@@ -0,0 +1,3 @@ ++#as: -march=armv8-a+sme ++#source: sme-9-illegal.s ++#error_output: sme-9-illegal.l +diff --git a/gas/testsuite/gas/aarch64/sme-9-illegal.l b/gas/testsuite/gas/aarch64/sme-9-illegal.l +new file mode 100644 +index 00000000..6bab29fd +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/sme-9-illegal.l +@@ -0,0 +1,83 @@ ++[^:]*: Assembler messages: ++[^:]*:[0-9]+: Error: wrong predicate register element size, allowed b, h, s and d at operand 3 -- `psel p1,p15,p3.q\[w15\]' ++[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `psel p1,p15,p3.b\[w11\]' ++[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `psel p8,p11,p15.h\[w16\]' ++[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `psel p2,p7,p15.s\[w3\]' ++[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `psel p13,p3,p1.d\[w17\]' ++[^:]*:[0-9]+: Error: element index out of range for given variant at operand 3 -- `psel p5,p12,p9.b\[w15,#16\]' ++[^:]*:[0-9]+: Error: element index out of range for given variant at operand 3 -- `psel p1,p8,p6.h\[w14,#8\]' ++[^:]*:[0-9]+: Error: element index out of range for given variant at operand 3 -- `psel p8,p4,p15.s\[w13,#4\]' ++[^:]*:[0-9]+: Error: element index out of range for given variant at operand 3 -- `psel p1,p1,p1.d\[w12,#2\]' ++[^:]*:[0-9]+: Error: operand mismatch -- `revd z0.q,p0/m,z0.b' ++[^:]*:[0-9]+: Info: did you mean this\? ++[^:]*:[0-9]+: Info: revd z0.q, p0/m, z0.q ++[^:]*:[0-9]+: Error: operand mismatch -- `sclamp z8.b,z1.b,z31.q' ++[^:]*:[0-9]+: Info: did you mean this\? ++[^:]*:[0-9]+: Info: sclamp z8.b, z1.b, z31.b ++[^:]*:[0-9]+: Info: other valid variant\(s\): ++[^:]*:[0-9]+: Info: sclamp z8.h, z1.h, z31.h ++[^:]*:[0-9]+: Info: sclamp z8.s, z1.s, z31.s ++[^:]*:[0-9]+: Info: sclamp z8.d, z1.d, z31.d ++[^:]*:[0-9]+: Error: operand mismatch -- `sclamp z31.h,z0.h,z17.q' ++[^:]*:[0-9]+: Info: did you mean this\? ++[^:]*:[0-9]+: Info: sclamp z31.h, z0.h, z17.h ++[^:]*:[0-9]+: Info: other valid variant\(s\): ++[^:]*:[0-9]+: Info: sclamp z31.b, z0.b, z17.b ++[^:]*:[0-9]+: Info: sclamp z31.s, z0.s, z17.s ++[^:]*:[0-9]+: Info: sclamp z31.d, z0.d, z17.d ++[^:]*:[0-9]+: Error: operand mismatch -- `sclamp z0.s,z31.s,z17.q' ++[^:]*:[0-9]+: Info: did you mean this\? ++[^:]*:[0-9]+: Info: sclamp z0.s, z31.s, z17.s ++[^:]*:[0-9]+: Info: other valid variant\(s\): ++[^:]*:[0-9]+: Info: sclamp z0.b, z31.b, z17.b ++[^:]*:[0-9]+: Info: sclamp z0.h, z31.h, z17.h ++[^:]*:[0-9]+: Info: sclamp z0.d, z31.d, z17.d ++[^:]*:[0-9]+: Error: operand mismatch -- `sclamp z31.d,z0.d,z17.q' ++[^:]*:[0-9]+: Info: did you mean this\? ++[^:]*:[0-9]+: Info: sclamp z31.d, z0.d, z17.d ++[^:]*:[0-9]+: Info: other valid variant\(s\): ++[^:]*:[0-9]+: Info: sclamp z31.b, z0.b, z17.b ++[^:]*:[0-9]+: Info: sclamp z31.h, z0.h, z17.h ++[^:]*:[0-9]+: Info: sclamp z31.s, z0.s, z17.s ++[^:]*:[0-9]+: Error: operand mismatch -- `sclamp z31.q,z0.d,z17.q' ++[^:]*:[0-9]+: Info: did you mean this\? ++[^:]*:[0-9]+: Info: sclamp z31.d, z0.d, z17.d ++[^:]*:[0-9]+: Info: other valid variant\(s\): ++[^:]*:[0-9]+: Info: sclamp z31.b, z0.b, z17.b ++[^:]*:[0-9]+: Info: sclamp z31.h, z0.h, z17.h ++[^:]*:[0-9]+: Info: sclamp z31.s, z0.s, z17.s ++[^:]*:[0-9]+: Error: operand mismatch -- `uclamp z8.b,z1.b,z31.q' ++[^:]*:[0-9]+: Info: did you mean this\? ++[^:]*:[0-9]+: Info: uclamp z8.b, z1.b, z31.b ++[^:]*:[0-9]+: Info: other valid variant\(s\): ++[^:]*:[0-9]+: Info: uclamp z8.h, z1.h, z31.h ++[^:]*:[0-9]+: Info: uclamp z8.s, z1.s, z31.s ++[^:]*:[0-9]+: Info: uclamp z8.d, z1.d, z31.d ++[^:]*:[0-9]+: Error: operand mismatch -- `uclamp z31.h,z0.h,z17.q' ++[^:]*:[0-9]+: Info: did you mean this\? ++[^:]*:[0-9]+: Info: uclamp z31.h, z0.h, z17.h ++[^:]*:[0-9]+: Info: other valid variant\(s\): ++[^:]*:[0-9]+: Info: uclamp z31.b, z0.b, z17.b ++[^:]*:[0-9]+: Info: uclamp z31.s, z0.s, z17.s ++[^:]*:[0-9]+: Info: uclamp z31.d, z0.d, z17.d ++[^:]*:[0-9]+: Error: operand mismatch -- `uclamp z0.s,z31.s,z17.q' ++[^:]*:[0-9]+: Info: did you mean this\? ++[^:]*:[0-9]+: Info: uclamp z0.s, z31.s, z17.s ++[^:]*:[0-9]+: Info: other valid variant\(s\): ++[^:]*:[0-9]+: Info: uclamp z0.b, z31.b, z17.b ++[^:]*:[0-9]+: Info: uclamp z0.h, z31.h, z17.h ++[^:]*:[0-9]+: Info: uclamp z0.d, z31.d, z17.d ++[^:]*:[0-9]+: Error: operand mismatch -- `uclamp z31.d,z0.d,z17.q' ++[^:]*:[0-9]+: Info: did you mean this\? ++[^:]*:[0-9]+: Info: uclamp z31.d, z0.d, z17.d ++[^:]*:[0-9]+: Info: other valid variant\(s\): ++[^:]*:[0-9]+: Info: uclamp z31.b, z0.b, z17.b ++[^:]*:[0-9]+: Info: uclamp z31.h, z0.h, z17.h ++[^:]*:[0-9]+: Info: uclamp z31.s, z0.s, z17.s ++[^:]*:[0-9]+: Error: operand mismatch -- `uclamp z31.q,z0.d,z17.q' ++[^:]*:[0-9]+: Info: did you mean this\? ++[^:]*:[0-9]+: Info: uclamp z31.d, z0.d, z17.d ++[^:]*:[0-9]+: Info: other valid variant\(s\): ++[^:]*:[0-9]+: Info: uclamp z31.b, z0.b, z17.b ++[^:]*:[0-9]+: Info: uclamp z31.h, z0.h, z17.h ++[^:]*:[0-9]+: Info: uclamp z31.s, z0.s, z17.s +diff --git a/gas/testsuite/gas/aarch64/sme-9-illegal.s b/gas/testsuite/gas/aarch64/sme-9-illegal.s +new file mode 100644 +index 00000000..308d52ce +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/sme-9-illegal.s +@@ -0,0 +1,25 @@ ++/* Scalable Matrix Extension (SME). */ ++ ++psel p1, p15, p3.q[w15] ++psel p1, p15, p3.b[w11] ++psel p8, p11, p15.h[w16] ++psel p2, p7, p15.s[w3] ++psel p13, p3, p1.d[w17] ++psel p5, p12, p9.b[w15, #16] ++psel p1, p8, p6.h[w14, #8] ++psel p8, p4, p15.s[w13, #4] ++psel p1, p1, p1.d[w12, #2] ++ ++revd z0.q, p0/m, z0.b ++ ++sclamp z8.b, z1.b, z31.q ++sclamp z31.h, z0.h, z17.q ++sclamp z0.s, z31.s, z17.q ++sclamp z31.d, z0.d, z17.q ++sclamp z31.q, z0.d, z17.q ++ ++uclamp z8.b, z1.b, z31.q ++uclamp z31.h, z0.h, z17.q ++uclamp z0.s, z31.s, z17.q ++uclamp z31.d, z0.d, z17.q ++uclamp z31.q, z0.d, z17.q +diff --git a/gas/testsuite/gas/aarch64/sme-9.d b/gas/testsuite/gas/aarch64/sme-9.d +new file mode 100644 +index 00000000..ef314c61 +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/sme-9.d +@@ -0,0 +1,73 @@ ++#name: SVE2 instructions added to support SME ++#as: -march=armv8-a+sme ++#objdump: -dr ++ ++.*: file format .* ++ ++Disassembly of section \.text: ++ ++0+ <.*>: ++ 0: 25277c61 psel p1, p15, p3.b\[w15, 0\] ++ 4: 252778a2 psel p2, p14, p5.b\[w15, 0\] ++ 8: 257f74e3 psel p3, p13, p7.b\[w15, 7\] ++ c: 25ff7125 psel p5, p12, p9.b\[w15, 15\] ++ 10: 252a6de8 psel p8, p11, p15.h\[w14, 0\] ++ 14: 252a682d psel p13, p10, p1.h\[w14, 0\] ++ 18: 257a640f psel p15, p9, p0.h\[w14, 3\] ++ 1c: 25fa60c1 psel p1, p8, p6.h\[w14, 7\] ++ 20: 25315de2 psel p2, p7, p15.s\[w13, 0\] ++ 24: 253159e3 psel p3, p6, p15.s\[w13, 0\] ++ 28: 257155e5 psel p5, p5, p15.s\[w13, 1\] ++ 2c: 25f151e8 psel p8, p4, p15.s\[w13, 3\] ++ 30: 25604c2d psel p13, p3, p1.d\[w12, 0\] ++ 34: 2560482f psel p15, p2, p1.d\[w12, 0\] ++ 38: 25e04421 psel p1, p1, p1.d\[w12, 1\] ++ 3c: 052e8000 revd z0.q, p0/m, z0.q ++ 40: 052e9c00 revd z0.q, p7/m, z0.q ++ 44: 052e83e0 revd z0.q, p0/m, z31.q ++ 48: 052e9c1f revd z31.q, p7/m, z0.q ++ 4c: 4411c3e0 sclamp z0.b, z31.b, z17.b ++ 50: 4411c01f sclamp z31.b, z0.b, z17.b ++ 54: 441fc028 sclamp z8.b, z1.b, z31.b ++ 58: 4451c01f sclamp z31.h, z0.h, z17.h ++ 5c: 445fc028 sclamp z8.h, z1.h, z31.h ++ 60: 4491c3e0 sclamp z0.s, z31.s, z17.s ++ 64: 4491c01f sclamp z31.s, z0.s, z17.s ++ 68: 449fc028 sclamp z8.s, z1.s, z31.s ++ 6c: 44d1c3e0 sclamp z0.d, z31.d, z17.d ++ 70: 44d1c01f sclamp z31.d, z0.d, z17.d ++ 74: 44dfc028 sclamp z8.d, z1.d, z31.d ++ 78: 4411c7e0 uclamp z0.b, z31.b, z17.b ++ 7c: 4411c41f uclamp z31.b, z0.b, z17.b ++ 80: 441fc428 uclamp z8.b, z1.b, z31.b ++ 84: 4451c7e0 uclamp z0.h, z31.h, z17.h ++ 88: 4451c41f uclamp z31.h, z0.h, z17.h ++ 8c: 445fc428 uclamp z8.h, z1.h, z31.h ++ 90: 4491c7e0 uclamp z0.s, z31.s, z17.s ++ 94: 4491c41f uclamp z31.s, z0.s, z17.s ++ 98: 449fc428 uclamp z8.s, z1.s, z31.s ++ 9c: 44d1c7e0 uclamp z0.d, z31.d, z17.d ++ a0: 44d1c41f uclamp z31.d, z0.d, z17.d ++ a4: 44dfc428 uclamp z8.d, z1.d, z31.d ++ a8: 0420bca3 movprfx z3, z5 ++ ac: 052e84a3 revd z3.q, p1/m, z5.q ++ b0: 0420bc81 movprfx z1, z4 ++ b4: 052e84a1 revd z1.q, p1/m, z5.q ++ b8: 0420bc81 movprfx z1, z4 ++ bc: 440bc141 sclamp z1.b, z10.b, z11.b ++ c0: 0420bc82 movprfx z2, z4 ++ c4: 444bc142 sclamp z2.h, z10.h, z11.h ++ c8: 0420bc83 movprfx z3, z4 ++ cc: 448bc143 sclamp z3.s, z10.s, z11.s ++ d0: 0420bca4 movprfx z4, z5 ++ d4: 44cbc144 sclamp z4.d, z10.d, z11.d ++ d8: 0420bc81 movprfx z1, z4 ++ dc: 440bc541 uclamp z1.b, z10.b, z11.b ++ e0: 0420bc82 movprfx z2, z4 ++ e4: 444bc542 uclamp z2.h, z10.h, z11.h ++ e8: 0420bc83 movprfx z3, z4 ++ ec: 448bc543 uclamp z3.s, z10.s, z11.s ++ f0: 0420bca4 movprfx z4, z5 ++ f4: 44cbc544 uclamp z4.d, z10.d, z11.d ++ f8: 25277c61 psel p1, p15, p3.b\[w15, 0\] ++ fc: 252778a2 psel p2, p14, p5.b\[w15, 0\] +diff --git a/gas/testsuite/gas/aarch64/sme-9.s b/gas/testsuite/gas/aarch64/sme-9.s +new file mode 100644 +index 00000000..be8511fe +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/sme-9.s +@@ -0,0 +1,86 @@ ++/* SVE2 instructions added to support SME. */ ++ ++psel p1, p15, p3.b[w15, 0] ++psel p2, p14, p5.b[w15, 0] ++psel p3, p13, p7.b[w15, 7] ++psel p5, p12, p9.b[w15, 15] ++ ++psel p8, p11, p15.h[w14, 0] ++psel p13, p10, p1.h[w14, 0] ++psel p15, p9, p0.h[w14, 3] ++psel p1, p8, p6.h[w14, 7] ++ ++psel p2, p7, p15.s[w13, 0] ++psel p3, p6, p15.s[w13, 0] ++psel p5, p5, p15.s[w13, 1] ++psel p8, p4, p15.s[w13, 3] ++ ++psel p13, p3, p1.d[w12, 0] ++psel p15, p2, p1.d[w12, 0] ++psel p1, p1, p1.d[w12, 1] ++ ++revd z0.q, p0/m, z0.q ++revd z0.q, p7/m, z0.q ++revd z0.q, p0/m, z31.q ++revd z31.q, p7/m, z0.q ++ ++sclamp z0.b, z31.b, z17.b ++sclamp z31.b, z0.b, z17.b ++sclamp z8.b, z1.b, z31.b ++sclamp z31.h, z0.h, z17.h ++sclamp z8.h, z1.h, z31.h ++sclamp z0.s, z31.s, z17.s ++sclamp z31.s, z0.s, z17.s ++sclamp z8.s, z1.s, z31.s ++sclamp z0.d, z31.d, z17.d ++sclamp z31.d, z0.d, z17.d ++sclamp z8.d, z1.d, z31.d ++ ++uclamp z0.b, z31.b, z17.b ++uclamp z31.b, z0.b, z17.b ++uclamp z8.b, z1.b, z31.b ++uclamp z0.h, z31.h, z17.h ++uclamp z31.h, z0.h, z17.h ++uclamp z8.h, z1.h, z31.h ++uclamp z0.s, z31.s, z17.s ++uclamp z31.s, z0.s, z17.s ++uclamp z8.s, z1.s, z31.s ++uclamp z0.d, z31.d, z17.d ++uclamp z31.d, z0.d, z17.d ++uclamp z8.d, z1.d, z31.d ++ ++/* The unpredicated MOVPRFX instruction. */ ++movprfx z3, z5 ++revd z3.q, p1/m, z5.q ++ ++movprfx z1, z4 ++revd z1.q, p1/m, z5.q ++ ++movprfx z1, z4 ++sclamp z1.b, z10.b, z11.b ++ ++movprfx z2, z4 ++sclamp z2.h, z10.h, z11.h ++ ++movprfx z3, z4 ++sclamp z3.s, z10.s, z11.s ++ ++movprfx z4, z5 ++sclamp z4.d, z10.d, z11.d ++ ++movprfx z1, z4 ++uclamp z1.b, z10.b, z11.b ++ ++movprfx z2, z4 ++uclamp z2.h, z10.h, z11.h ++ ++movprfx z3, z4 ++uclamp z3.s, z10.s, z11.s ++ ++movprfx z4, z5 ++uclamp z4.d, z10.d, z11.d ++ ++foo .req p1 ++bar .req w15 ++psel foo, p15, p3.b[w15, 0] ++psel p2, p14, p5.b[bar, 0] +diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h +index 9a3ec903..2cfd8b27 100644 +--- a/include/opcode/aarch64.h ++++ b/include/opcode/aarch64.h +@@ -450,6 +450,7 @@ enum aarch64_opnd + AARCH64_OPND_SME_ZA_array, /* SME ZA[{, #}]. */ + AARCH64_OPND_SME_ADDR_RI_U4xVL, /* SME [{, #, MUL VL}]. */ + AARCH64_OPND_SME_SM_ZA, /* SME {SM | ZA}. */ ++ AARCH64_OPND_SME_PnT_Wm_imm, /* SME .[, #]. */ + AARCH64_OPND_TME_UIMM16, /* TME unsigned 16-bit immediate. */ + AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */ + }; +diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c +index 8b226b10..bbe4b683 100644 +--- a/opcodes/aarch64-asm-2.c ++++ b/opcodes/aarch64-asm-2.c +@@ -675,7 +675,7 @@ aarch64_insert_operand (const aarch64_operand *self, + case 33: + case 34: + case 35: +- case 221: ++ case 222: + return aarch64_ins_reglane (self, info, code, inst, errors); + case 36: + return aarch64_ins_reglist (self, info, code, inst, errors); +@@ -721,7 +721,7 @@ aarch64_insert_operand (const aarch64_operand *self, + case 189: + case 190: + case 215: +- case 220: ++ case 221: + return aarch64_ins_imm (self, info, code, inst, errors); + case 44: + case 45: +@@ -891,6 +891,8 @@ aarch64_insert_operand (const aarch64_operand *self, + return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors); + case 219: + return aarch64_ins_sme_sm_za (self, info, code, inst, errors); ++ case 220: ++ return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors); + default: assert (0); abort (); + } + } +diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c +index b9aff950..fd5412aa 100644 +--- a/opcodes/aarch64-asm.c ++++ b/opcodes/aarch64-asm.c +@@ -1452,6 +1452,73 @@ aarch64_ins_sme_sm_za (const aarch64_operand *self, + return true; + } + ++/* Encode source scalable predicate register (Pn), name of the index base ++ register W12-W15 (Rm), and optional element index, defaulting to 0, in the ++ range 0 to one less than the number of vector elements in a 128-bit vector ++ register, encoded in "i1:tszh:tszl". ++*/ ++bool ++aarch64_ins_sme_pred_reg_with_index (const aarch64_operand *self, ++ const aarch64_opnd_info *info, ++ aarch64_insn *code, ++ const aarch64_inst *inst ATTRIBUTE_UNUSED, ++ aarch64_operand_error *errors ATTRIBUTE_UNUSED) ++{ ++ int fld_pn = info->za_tile_vector.regno; ++ int fld_rm = info->za_tile_vector.index.regno - 12; ++ int imm = info->za_tile_vector.index.imm; ++ int fld_i1, fld_tszh, fld_tshl; ++ ++ insert_field (self->fields[0], code, fld_rm, 0); ++ insert_field (self->fields[1], code, fld_pn, 0); ++ ++ /* Optional element index, defaulting to 0, in the range 0 to one less than ++ the number of vector elements in a 128-bit vector register, encoded in ++ "i1:tszh:tszl". ++ ++ i1 tszh tszl ++ 0 0 000 RESERVED ++ x x xx1 B ++ x x x10 H ++ x x 100 S ++ x 1 000 D ++ */ ++ switch (info->qualifier) ++ { ++ case AARCH64_OPND_QLF_S_B: ++ /* is 4 bit value. */ ++ fld_i1 = (imm >> 3) & 0x1; ++ fld_tszh = (imm >> 2) & 0x1; ++ fld_tshl = ((imm << 1) | 0x1) & 0x7; ++ break; ++ case AARCH64_OPND_QLF_S_H: ++ /* is 3 bit value. */ ++ fld_i1 = (imm >> 2) & 0x1; ++ fld_tszh = (imm >> 1) & 0x1; ++ fld_tshl = ((imm << 2) | 0x2) & 0x7; ++ break; ++ case AARCH64_OPND_QLF_S_S: ++ /* is 2 bit value. */ ++ fld_i1 = (imm >> 1) & 0x1; ++ fld_tszh = imm & 0x1; ++ fld_tshl = 0x4; ++ break; ++ case AARCH64_OPND_QLF_S_D: ++ /* is 1 bit value. */ ++ fld_i1 = imm & 0x1; ++ fld_tszh = 0x1; ++ fld_tshl = 0x0; ++ break; ++ default: ++ assert (0); ++ } ++ ++ insert_field (self->fields[2], code, fld_i1, 0); ++ insert_field (self->fields[3], code, fld_tszh, 0); ++ insert_field (self->fields[4], code, fld_tshl, 0); ++ return true; ++} ++ + /* Miscellaneous encoding functions. */ + + /* Encode size[0], i.e. bit 22, for +diff --git a/opcodes/aarch64-asm.h b/opcodes/aarch64-asm.h +index cb224f68..47f775da 100644 +--- a/opcodes/aarch64-asm.h ++++ b/opcodes/aarch64-asm.h +@@ -103,6 +103,7 @@ AARCH64_DECL_OPD_INSERTER (ins_sme_za_list); + AARCH64_DECL_OPD_INSERTER (ins_sme_za_array); + AARCH64_DECL_OPD_INSERTER (ins_sme_addr_ri_u4xvl); + AARCH64_DECL_OPD_INSERTER (ins_sme_sm_za); ++AARCH64_DECL_OPD_INSERTER (ins_sme_pred_reg_with_index); + AARCH64_DECL_OPD_INSERTER (ins_imm_rotate1); + AARCH64_DECL_OPD_INSERTER (ins_imm_rotate2); + +diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c +index 8d759bc3..f9999adc 100644 +--- a/opcodes/aarch64-dis-2.c ++++ b/opcodes/aarch64-dis-2.c +@@ -2896,7 +2896,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 00011001000xxxxxxxxx00xxxxxxxxxx + stlurb. */ +- return 2447; ++ return 2451; + } + else + { +@@ -2904,7 +2904,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 10011001000xxxxxxxxx00xxxxxxxxxx + stlur. */ +- return 2455; ++ return 2459; + } + } + else +@@ -2915,7 +2915,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 01011001000xxxxxxxxx00xxxxxxxxxx + stlurh. */ +- return 2451; ++ return 2455; + } + else + { +@@ -2923,7 +2923,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 11011001000xxxxxxxxx00xxxxxxxxxx + stlur. */ +- return 2458; ++ return 2462; + } + } + } +@@ -3003,7 +3003,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 00011001010xxxxxxxxx00xxxxxxxxxx + ldapurb. */ +- return 2448; ++ return 2452; + } + else + { +@@ -3011,7 +3011,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 10011001010xxxxxxxxx00xxxxxxxxxx + ldapur. */ +- return 2456; ++ return 2460; + } + } + else +@@ -3022,7 +3022,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 01011001010xxxxxxxxx00xxxxxxxxxx + ldapurh. */ +- return 2452; ++ return 2456; + } + else + { +@@ -3030,7 +3030,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 11011001010xxxxxxxxx00xxxxxxxxxx + ldapur. */ +- return 2459; ++ return 2463; + } + } + } +@@ -3113,7 +3113,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 00011001100xxxxxxxxx00xxxxxxxxxx + ldapursb. */ +- return 2450; ++ return 2454; + } + else + { +@@ -3121,7 +3121,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 10011001100xxxxxxxxx00xxxxxxxxxx + ldapursw. */ +- return 2457; ++ return 2461; + } + } + else +@@ -3130,7 +3130,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1011001100xxxxxxxxx00xxxxxxxxxx + ldapursh. */ +- return 2454; ++ return 2458; + } + } + else +@@ -3141,7 +3141,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x0011001110xxxxxxxxx00xxxxxxxxxx + ldapursb. */ +- return 2449; ++ return 2453; + } + else + { +@@ -3149,7 +3149,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1011001110xxxxxxxxx00xxxxxxxxxx + ldapursh. */ +- return 2453; ++ return 2457; + } + } + } +@@ -3635,7 +3635,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xxx11010x00xxxxxx0xx10xxxxxxxxxx + setf8. */ +- return 2445; ++ return 2449; + } + else + { +@@ -3643,7 +3643,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xxx11010x00xxxxxx1xx10xxxxxxxxxx + setf16. */ +- return 2446; ++ return 2450; + } + } + else +@@ -3789,7 +3789,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xxx11010000xxxxxxxxx01xxxxxxxxxx + rmif. */ +- return 2444; ++ return 2448; + } + else + { +@@ -4838,7 +4838,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x01x1xxxxx000110xxxxxxxxxx + usdot. */ +- return 2464; ++ return 2468; + } + } + } +@@ -4912,7 +4912,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x01x1xxxxx000111xxxxxxxxxx + sudot. */ +- return 2465; ++ return 2469; + } + } + } +@@ -6282,42 +6282,64 @@ aarch64_opcode_lookup_1 (uint32_t word) + { + if (((word >> 21) & 0x1) == 0) + { +- if (((word >> 22) & 0x1) == 0) ++ if (((word >> 31) & 0x1) == 0) + { +- if (((word >> 23) & 0x1) == 0) ++ if (((word >> 10) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 +- x10001x0000xxxxx110xxxxxxxxxxxxx +- ldnt1b. */ +- return 2104; ++ 010001x0xx0xxxxx110xx0xxxxxxxxxx ++ sclamp. */ ++ return 2408; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 +- x10001x0100xxxxx110xxxxxxxxxxxxx +- ldnt1h. */ +- return 2107; ++ 010001x0xx0xxxxx110xx1xxxxxxxxxx ++ uclamp. */ ++ return 2409; + } + } + else + { +- if (((word >> 23) & 0x1) == 0) ++ if (((word >> 22) & 0x1) == 0) + { +- /* 33222222222211111111110000000000 +- 10987654321098765432109876543210 +- x10001x0010xxxxx110xxxxxxxxxxxxx +- ld1b. */ +- return 1521; ++ if (((word >> 23) & 0x1) == 0) ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ 110001x0000xxxxx110xxxxxxxxxxxxx ++ ldnt1b. */ ++ return 2104; ++ } ++ else ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ 110001x0100xxxxx110xxxxxxxxxxxxx ++ ldnt1h. */ ++ return 2107; ++ } + } + else + { +- /* 33222222222211111111110000000000 +- 10987654321098765432109876543210 +- x10001x0110xxxxx110xxxxxxxxxxxxx +- ld1h. */ +- return 1542; ++ if (((word >> 23) & 0x1) == 0) ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ 110001x0010xxxxx110xxxxxxxxxxxxx ++ ld1b. */ ++ return 1521; ++ } ++ else ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ 110001x0110xxxxx110xxxxxxxxxxxxx ++ ld1h. */ ++ return 1542; ++ } + } + } + } +@@ -7531,7 +7553,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0xx0xxxxx011110xxxxxxxxxx + usdot. */ +- return 2463; ++ return 2467; + } + } + } +@@ -9235,7 +9257,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0100xxx10101xxxxxxxxxxxxx + bfcvtnt. */ +- return 2492; ++ return 2496; + } + } + else +@@ -9478,7 +9500,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x00x1xxxxxx00xxxxxxxxxxxxx + ld1rob. */ +- return 2468; ++ return 2472; + } + else + { +@@ -9486,7 +9508,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x01x1xxxxxx00xxxxxxxxxxxxx + ld1roh. */ +- return 2469; ++ return 2473; + } + } + else +@@ -9718,7 +9740,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0011xxxxx010xxxxxxxxxxxxx + bfdot. */ +- return 2489; ++ return 2493; + } + else + { +@@ -9739,7 +9761,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0111xxxxx010xx0xxxxxxxxxx + bfmlalb. */ +- return 2496; ++ return 2500; + } + else + { +@@ -9747,7 +9769,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0111xxxxx010xx1xxxxxxxxxx + bfmlalt. */ +- return 2495; ++ return 2499; + } + } + else +@@ -9802,7 +9824,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x11001x0011xxxxx1x0xxxxxxxxxxxxx + bfdot. */ +- return 2488; ++ return 2492; + } + else + { +@@ -9814,7 +9836,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0111xxxxx1x0xx0xxxxxxxxxx + bfmlalb. */ +- return 2494; ++ return 2498; + } + else + { +@@ -9822,7 +9844,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0111xxxxx1x0xx1xxxxxxxxxx + bfmlalt. */ +- return 2493; ++ return 2497; + } + } + else +@@ -9873,7 +9895,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x00x1xxxxx001xxxxxxxxxxxxx + ld1rob. */ +- return 2472; ++ return 2476; + } + else + { +@@ -9881,7 +9903,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x01x1xxxxx001xxxxxxxxxxxxx + ld1roh. */ +- return 2473; ++ return 2477; + } + } + else +@@ -10240,7 +10262,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0101xxxxx111xxxxxxxxxxxxx + fmmla. */ +- return 2466; ++ return 2470; + } + else + { +@@ -10273,7 +10295,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0011xxxxx111xxxxxxxxxxxxx + bfmmla. */ +- return 2490; ++ return 2494; + } + else + { +@@ -10303,7 +10325,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0111xxxxx111xxxxxxxxxxxxx + fmmla. */ +- return 2467; ++ return 2471; + } + else + { +@@ -10432,7 +10454,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1101xxxxx000x00xxxxxxxxxx + zip1. */ +- return 2476; ++ return 2480; + } + else + { +@@ -10442,7 +10464,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1101xxxxx000010xxxxxxxxxx + uzp1. */ +- return 2478; ++ return 2482; + } + else + { +@@ -10450,7 +10472,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1101xxxxx000110xxxxxxxxxx + trn1. */ +- return 2480; ++ return 2484; + } + } + } +@@ -10462,7 +10484,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1101xxxxx000x01xxxxxxxxxx + zip2. */ +- return 2477; ++ return 2481; + } + else + { +@@ -10472,7 +10494,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1101xxxxx000011xxxxxxxxxx + uzp2. */ +- return 2479; ++ return 2483; + } + else + { +@@ -10480,7 +10502,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1101xxxxx000111xxxxxxxxxx + trn2. */ +- return 2481; ++ return 2485; + } + } + } +@@ -10563,11 +10585,22 @@ aarch64_opcode_lookup_1 (uint32_t word) + } + else + { +- /* 33222222222211111111110000000000 +- 10987654321098765432109876543210 +- 000001x1xx1xx110100xxxxxxxxxxxxx +- revw. */ +- return 1820; ++ if (((word >> 19) & 0x1) == 0) ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ 000001x1xx1x0110100xxxxxxxxxxxxx ++ revw. */ ++ return 1820; ++ } ++ else ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ 000001x1xx1x1110100xxxxxxxxxxxxx ++ revd. */ ++ return 2407; ++ } + } + } + } +@@ -11528,7 +11561,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1000xxxxx100110xxxxxxxxxx + smmla. */ +- return 2460; ++ return 2464; + } + else + { +@@ -11536,7 +11569,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1100xxxxx100110xxxxxxxxxx + usmmla. */ +- return 2462; ++ return 2466; + } + } + else +@@ -11545,7 +11578,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1x10xxxxx100110xxxxxxxxxx + ummla. */ +- return 2461; ++ return 2465; + } + } + } +@@ -13041,7 +13074,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x10x1xxxxx000xxxxxxxxxxxxx + ld1row. */ +- return 2470; ++ return 2474; + } + else + { +@@ -13049,7 +13082,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x11x1xxxxx000xxxxxxxxxxxxx + ld1rod. */ +- return 2471; ++ return 2475; + } + } + } +@@ -13423,7 +13456,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x10x1xxxxx001xxxxxxxxxxxxx + ld1row. */ +- return 2474; ++ return 2478; + } + else + { +@@ -13431,7 +13464,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x11x1xxxxx001xxxxxxxxxxxxx + ld1rod. */ +- return 2475; ++ return 2479; + } + } + } +@@ -13768,85 +13801,96 @@ aarch64_opcode_lookup_1 (uint32_t word) + } + else + { +- if (((word >> 13) & 0x1) == 0) ++ if (((word >> 31) & 0x1) == 0) + { +- if (((word >> 22) & 0x1) == 0) +- { +- if (((word >> 23) & 0x1) == 0) +- { +- /* 33222222222211111111110000000000 +- 10987654321098765432109876543210 +- x01001x1001xxxxx010xxxxxxxxxxxxx +- ld1sh. */ +- return 1587; +- } +- else +- { +- /* 33222222222211111111110000000000 +- 10987654321098765432109876543210 +- x01001x1101xxxxx010xxxxxxxxxxxxx +- ld1sb. */ +- return 1575; +- } +- } +- else +- { +- if (((word >> 23) & 0x1) == 0) +- { +- /* 33222222222211111111110000000000 +- 10987654321098765432109876543210 +- x01001x1011xxxxx010xxxxxxxxxxxxx +- ld1w. */ +- return 1606; +- } +- else +- { +- /* 33222222222211111111110000000000 +- 10987654321098765432109876543210 +- x01001x1111xxxxx010xxxxxxxxxxxxx +- ld1d. */ +- return 1528; +- } +- } ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ 001001x1xx1xxxxx01xxxxxxxxxxxxxx ++ psel. */ ++ return 2410; + } + else + { +- if (((word >> 22) & 0x1) == 0) ++ if (((word >> 13) & 0x1) == 0) + { +- if (((word >> 23) & 0x1) == 0) ++ if (((word >> 22) & 0x1) == 0) + { +- /* 33222222222211111111110000000000 +- 10987654321098765432109876543210 +- x01001x1001xxxxx011xxxxxxxxxxxxx +- ldff1sh. */ +- return 1688; ++ if (((word >> 23) & 0x1) == 0) ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ 101001x1001xxxxx010xxxxxxxxxxxxx ++ ld1sh. */ ++ return 1587; ++ } ++ else ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ 101001x1101xxxxx010xxxxxxxxxxxxx ++ ld1sb. */ ++ return 1575; ++ } + } + else + { +- /* 33222222222211111111110000000000 +- 10987654321098765432109876543210 +- x01001x1101xxxxx011xxxxxxxxxxxxx +- ldff1sb. */ +- return 1676; ++ if (((word >> 23) & 0x1) == 0) ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ 101001x1011xxxxx010xxxxxxxxxxxxx ++ ld1w. */ ++ return 1606; ++ } ++ else ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ 101001x1111xxxxx010xxxxxxxxxxxxx ++ ld1d. */ ++ return 1528; ++ } + } + } + else + { +- if (((word >> 23) & 0x1) == 0) ++ if (((word >> 22) & 0x1) == 0) + { +- /* 33222222222211111111110000000000 +- 10987654321098765432109876543210 +- x01001x1011xxxxx011xxxxxxxxxxxxx +- ldff1w. */ +- return 1707; ++ if (((word >> 23) & 0x1) == 0) ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ 101001x1001xxxxx011xxxxxxxxxxxxx ++ ldff1sh. */ ++ return 1688; ++ } ++ else ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ 101001x1101xxxxx011xxxxxxxxxxxxx ++ ldff1sb. */ ++ return 1676; ++ } + } + else + { +- /* 33222222222211111111110000000000 +- 10987654321098765432109876543210 +- x01001x1111xxxxx011xxxxxxxxxxxxx +- ldff1d. */ +- return 1652; ++ if (((word >> 23) & 0x1) == 0) ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ 101001x1011xxxxx011xxxxxxxxxxxxx ++ ldff1w. */ ++ return 1707; ++ } ++ else ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ 101001x1111xxxxx011xxxxxxxxxxxxx ++ ldff1d. */ ++ return 1652; ++ } + } + } + } +@@ -14865,7 +14909,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x110001x10101xxxxxxxxxxxxx + bfcvt. */ +- return 2491; ++ return 2495; + } + } + else +@@ -16934,7 +16978,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 0x001110xx0xxxxx1x1001xxxxxxxxxx + smmla. */ +- return 2482; ++ return 2486; + } + } + } +@@ -16967,7 +17011,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 0x001110xx0xxxxx1x0101xxxxxxxxxx + sdot. */ +- return 2408; ++ return 2412; + } + } + else +@@ -17041,7 +17085,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 0x001110xx0xxxxx1x1011xxxxxxxxxx + usmmla. */ +- return 2484; ++ return 2488; + } + } + } +@@ -17074,7 +17118,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 0x001110xx0xxxxx1x0111xxxxxxxxxx + usdot. */ +- return 2485; ++ return 2489; + } + } + else +@@ -17121,7 +17165,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110000xxxxxxxxxxxxxxxxxxxxx + eor3. */ +- return 2415; ++ return 2419; + } + else + { +@@ -17129,7 +17173,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110100xxxxxxxxxxxxxxxxxxxxx + xar. */ +- return 2417; ++ return 2421; + } + } + else +@@ -17140,7 +17184,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110x10xxxxx0xxxxxxxxxxxxxxx + sm3ss1. */ +- return 2419; ++ return 2423; + } + else + { +@@ -17154,7 +17198,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110010xxxxx1xxx00xxxxxxxxxx + sm3tt1a. */ +- return 2420; ++ return 2424; + } + else + { +@@ -17162,7 +17206,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110110xxxxx1xxx00xxxxxxxxxx + sha512su0. */ +- return 2413; ++ return 2417; + } + } + else +@@ -17171,7 +17215,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110x10xxxxx1xxx10xxxxxxxxxx + sm3tt2a. */ +- return 2422; ++ return 2426; + } + } + else +@@ -17184,7 +17228,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110010xxxxx1xxx01xxxxxxxxxx + sm3tt1b. */ +- return 2421; ++ return 2425; + } + else + { +@@ -17192,7 +17236,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110110xxxxx1xxx01xxxxxxxxxx + sm4e. */ +- return 2426; ++ return 2430; + } + } + else +@@ -17201,7 +17245,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110x10xxxxx1xxx11xxxxxxxxxx + sm3tt2b. */ +- return 2423; ++ return 2427; + } + } + } +@@ -17382,7 +17426,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx101110xx0xxxxx100101xxxxxxxxxx + udot. */ +- return 2407; ++ return 2411; + } + } + else +@@ -17413,7 +17457,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx101110xx0xxxxx101x01xxxxxxxxxx + ummla. */ +- return 2483; ++ return 2487; + } + else + { +@@ -17432,7 +17476,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx101110xx0xxxxx1x1011xxxxxxxxxx + bfmmla. */ +- return 2499; ++ return 2503; + } + else + { +@@ -17442,7 +17486,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx1011100x0xxxxx1x1111xxxxxxxxxx + bfdot. */ +- return 2497; ++ return 2501; + } + else + { +@@ -17452,7 +17496,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x01011101x0xxxxx1x1111xxxxxxxxxx + bfmlalb. */ +- return 2504; ++ return 2508; + } + else + { +@@ -17460,7 +17504,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x11011101x0xxxxx1x1111xxxxxxxxxx + bfmlalt. */ +- return 2503; ++ return 2507; + } + } + } +@@ -18044,7 +18088,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000011101x1xxxx1011010xxxxxxxxxx + bfcvtn. */ +- return 2500; ++ return 2504; + } + else + { +@@ -18052,7 +18096,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010011101x1xxxx1011010xxxxxxxxxx + bfcvtn2. */ +- return 2501; ++ return 2505; + } + } + } +@@ -18370,7 +18414,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110xx1xxxxx0xxxxxxxxxxxxxxx + bcax. */ +- return 2418; ++ return 2422; + } + } + else +@@ -18981,7 +19025,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 11001110xx1xxxxx100000xxxxxxxxxx + sha512h. */ +- return 2411; ++ return 2415; + } + } + } +@@ -19033,7 +19077,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 11001110xx1xxxxx110000xxxxxxxxxx + sm3partw1. */ +- return 2424; ++ return 2428; + } + } + } +@@ -19276,7 +19320,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110xx1xxxxx100010xxxxxxxxxx + sha512su1. */ +- return 2414; ++ return 2418; + } + } + else +@@ -19352,7 +19396,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x0011100x1xxxxx110010xxxxxxxxxx + sm4ekey. */ +- return 2427; ++ return 2431; + } + } + else +@@ -20178,7 +20222,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110xx1xxxxx100001xxxxxxxxxx + sha512h2. */ +- return 2412; ++ return 2416; + } + } + else +@@ -20210,7 +20254,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x0011100x1xxxxx110001xxxxxxxxxx + sm3partw2. */ +- return 2425; ++ return 2429; + } + } + else +@@ -20450,7 +20494,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110xx1xxxxx100011xxxxxxxxxx + rax1. */ +- return 2416; ++ return 2420; + } + } + else +@@ -20482,7 +20526,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x01011100x1xxxxx110011xxxxxxxxxx + fmlal2. */ +- return 2430; ++ return 2434; + } + else + { +@@ -20490,7 +20534,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x11011100x1xxxxx110011xxxxxxxxxx + fmlal2. */ +- return 2434; ++ return 2438; + } + } + } +@@ -20512,7 +20556,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x01011101x1xxxxx110011xxxxxxxxxx + fmlsl2. */ +- return 2431; ++ return 2435; + } + else + { +@@ -20520,7 +20564,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x11011101x1xxxxx110011xxxxxxxxxx + fmlsl2. */ +- return 2435; ++ return 2439; + } + } + } +@@ -20559,7 +20603,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x00011100x1xxxxx111011xxxxxxxxxx + fmlal. */ +- return 2428; ++ return 2432; + } + else + { +@@ -20567,7 +20611,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x10011100x1xxxxx111011xxxxxxxxxx + fmlal. */ +- return 2432; ++ return 2436; + } + } + else +@@ -20589,7 +20633,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x00011101x1xxxxx111011xxxxxxxxxx + fmlsl. */ +- return 2429; ++ return 2433; + } + else + { +@@ -20597,7 +20641,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x10011101x1xxxxx111011xxxxxxxxxx + fmlsl. */ +- return 2433; ++ return 2437; + } + } + else +@@ -22405,7 +22449,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x0001111xxxxxxxx0000x0xxxxxxxxxx + fmlal. */ +- return 2436; ++ return 2440; + } + else + { +@@ -22413,7 +22457,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1001111xxxxxxxx0000x0xxxxxxxxxx + fmlal. */ +- return 2440; ++ return 2444; + } + } + else +@@ -22435,7 +22479,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x0001111xxxxxxxx0100x0xxxxxxxxxx + fmlsl. */ +- return 2437; ++ return 2441; + } + else + { +@@ -22443,7 +22487,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1001111xxxxxxxx0100x0xxxxxxxxxx + fmlsl. */ +- return 2441; ++ return 2445; + } + } + else +@@ -22949,7 +22993,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x0101111xxxxxxxx1000x0xxxxxxxxxx + fmlal2. */ +- return 2438; ++ return 2442; + } + else + { +@@ -22957,7 +23001,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1101111xxxxxxxx1000x0xxxxxxxxxx + fmlal2. */ +- return 2442; ++ return 2446; + } + } + } +@@ -22979,7 +23023,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x0101111xxxxxxxx1100x0xxxxxxxxxx + fmlsl2. */ +- return 2439; ++ return 2443; + } + else + { +@@ -22987,7 +23031,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1101111xxxxxxxx1100x0xxxxxxxxxx + fmlsl2. */ +- return 2443; ++ return 2447; + } + } + } +@@ -23043,7 +23087,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx001111xxxxxxxx1110x0xxxxxxxxxx + sdot. */ +- return 2410; ++ return 2414; + } + else + { +@@ -23051,7 +23095,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx101111xxxxxxxx1110x0xxxxxxxxxx + udot. */ +- return 2409; ++ return 2413; + } + } + } +@@ -23154,7 +23198,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx00111100xxxxxx1111x0xxxxxxxxxx + sudot. */ +- return 2487; ++ return 2491; + } + else + { +@@ -23162,7 +23206,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx00111110xxxxxx1111x0xxxxxxxxxx + usdot. */ +- return 2486; ++ return 2490; + } + } + else +@@ -23173,7 +23217,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx00111101xxxxxx1111x0xxxxxxxxxx + bfdot. */ +- return 2498; ++ return 2502; + } + else + { +@@ -23183,7 +23227,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x000111111xxxxxx1111x0xxxxxxxxxx + bfmlalb. */ +- return 2506; ++ return 2510; + } + else + { +@@ -23191,7 +23235,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x100111111xxxxxx1111x0xxxxxxxxxx + bfmlalt. */ +- return 2505; ++ return 2509; + } + } + } +@@ -23853,8 +23897,8 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode) + case 824: return NULL; /* fsqrt --> NULL. */ + case 832: value = 833; break; /* frintz --> frintz. */ + case 833: return NULL; /* frintz --> NULL. */ +- case 825: value = 2502; break; /* fcvt --> bfcvt. */ +- case 2502: return NULL; /* bfcvt --> NULL. */ ++ case 825: value = 2506; break; /* fcvt --> bfcvt. */ ++ case 2506: return NULL; /* bfcvt --> NULL. */ + case 834: value = 835; break; /* frinta --> frinta. */ + case 835: return NULL; /* frinta --> NULL. */ + case 836: value = 837; break; /* frintx --> frintx. */ +@@ -24373,7 +24417,7 @@ aarch64_extract_operand (const aarch64_operand *self, + case 33: + case 34: + case 35: +- case 221: ++ case 222: + return aarch64_ext_reglane (self, info, code, inst, errors); + case 36: + return aarch64_ext_reglist (self, info, code, inst, errors); +@@ -24420,7 +24464,7 @@ aarch64_extract_operand (const aarch64_operand *self, + case 189: + case 190: + case 215: +- case 220: ++ case 221: + return aarch64_ext_imm (self, info, code, inst, errors); + case 44: + case 45: +@@ -24592,6 +24636,8 @@ aarch64_extract_operand (const aarch64_operand *self, + return aarch64_ext_sme_addr_ri_u4xvl (self, info, code, inst, errors); + case 219: + return aarch64_ext_sme_sm_za (self, info, code, inst, errors); ++ case 220: ++ return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors); + default: assert (0); abort (); + } + } +diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c +index 0121383a..59582c46 100644 +--- a/opcodes/aarch64-dis.c ++++ b/opcodes/aarch64-dis.c +@@ -1889,6 +1889,49 @@ aarch64_ext_sme_sm_za (const aarch64_operand *self, + return true; + } + ++bool ++aarch64_ext_sme_pred_reg_with_index (const aarch64_operand *self, ++ aarch64_opnd_info *info, aarch64_insn code, ++ const aarch64_inst *inst ATTRIBUTE_UNUSED, ++ aarch64_operand_error *errors ATTRIBUTE_UNUSED) ++{ ++ aarch64_insn fld_rm = extract_field (self->fields[0], code, 0); ++ aarch64_insn fld_pn = extract_field (self->fields[1], code, 0); ++ aarch64_insn fld_i1 = extract_field (self->fields[2], code, 0); ++ aarch64_insn fld_tszh = extract_field (self->fields[3], code, 0); ++ aarch64_insn fld_tszl = extract_field (self->fields[4], code, 0); ++ int imm; ++ ++ info->za_tile_vector.regno = fld_pn; ++ info->za_tile_vector.index.regno = fld_rm + 12; ++ ++ if (fld_tszh == 0x1 && fld_tszl == 0x0) ++ { ++ info->qualifier = AARCH64_OPND_QLF_S_D; ++ imm = fld_i1; ++ } ++ else if (fld_tszl == 0x4) ++ { ++ info->qualifier = AARCH64_OPND_QLF_S_S; ++ imm = (fld_i1 << 1) | fld_tszh; ++ } ++ else if ((fld_tszl & 0x3) == 0x2) ++ { ++ info->qualifier = AARCH64_OPND_QLF_S_H; ++ imm = (fld_i1 << 2) | (fld_tszh << 1) | (fld_tszl >> 2); ++ } ++ else if (fld_tszl & 0x1) ++ { ++ info->qualifier = AARCH64_OPND_QLF_S_B; ++ imm = (fld_i1 << 3) | (fld_tszh << 2) | (fld_tszl >> 1); ++ } ++ else ++ return false; ++ ++ info->za_tile_vector.index.imm = imm; ++ return true; ++} ++ + /* Decode Zn[MM], where MM has a 7-bit triangular encoding. The fields + array specifies which field to use for Zn. MM is encoded in the + concatenation of imm5 and SVE_tszh, with imm5 being the less +diff --git a/opcodes/aarch64-dis.h b/opcodes/aarch64-dis.h +index 3366dfbc..df59d22e 100644 +--- a/opcodes/aarch64-dis.h ++++ b/opcodes/aarch64-dis.h +@@ -127,6 +127,7 @@ AARCH64_DECL_OPD_EXTRACTOR (ext_sme_za_list); + AARCH64_DECL_OPD_EXTRACTOR (ext_sme_za_array); + AARCH64_DECL_OPD_EXTRACTOR (ext_sme_addr_ri_u4xvl); + AARCH64_DECL_OPD_EXTRACTOR (ext_sme_sm_za); ++AARCH64_DECL_OPD_EXTRACTOR (ext_sme_pred_reg_with_index); + AARCH64_DECL_OPD_EXTRACTOR (ext_imm_rotate1); + AARCH64_DECL_OPD_EXTRACTOR (ext_imm_rotate2); + +diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c +index 75b7f86d..c583bd0c 100644 +--- a/opcodes/aarch64-opc-2.c ++++ b/opcodes/aarch64-opc-2.c +@@ -244,6 +244,7 @@ const struct aarch64_operand aarch64_operands[] = + {AARCH64_OPND_CLASS_SVE_REG, "SME_ZA_array", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rv,FLD_imm4_2}, "ZA array"}, + {AARCH64_OPND_CLASS_ADDRESS, "SME_ADDR_RI_U4xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm4_2}, "memory offset"}, + {AARCH64_OPND_CLASS_ADDRESS, "SME_SM_ZA", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "streaming mode"}, ++ {AARCH64_OPND_CLASS_SVE_REG, "SME_PnT_Wm_imm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rm,FLD_SVE_Pn,FLD_SME_i1,FLD_SME_tszh,FLD_SME_tszl}, "Source scalable predicate register with index "}, + {AARCH64_OPND_CLASS_IMMEDIATE, "TME_UIMM16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16}, "a 16-bit unsigned immediate for TME tcancel"}, + {AARCH64_OPND_CLASS_SIMD_ELEMENT, "SM3_IMM2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SM3_imm2}, "an indexed SM3 vector immediate"}, + {AARCH64_OPND_CLASS_NIL, "", 0, {0}, "DUMMY"}, +diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c +index 923ddefe..a37b3ffd 100644 +--- a/opcodes/aarch64-opc.c ++++ b/opcodes/aarch64-opc.c +@@ -332,6 +332,10 @@ const aarch64_field fields[] = + { 13, 2 }, /* SME_Rv: vector select register W12-W15, bits [14:13]. */ + { 13, 3 }, /* SME Pm second source scalable predicate register P0-P7. */ + { 0, 8 }, /* SME_zero_mask: list of up to 8 tile names separated by commas [7:0]. */ ++ { 16, 2 }, /* SME_Rm: index base register W12-W15 [17:16]. */ ++ { 23, 1 }, /* SME_i1: immediate field, bit 23. */ ++ { 22, 1 }, /* SME_tszh: immediate and qualifier field, bit 22. */ ++ { 18, 3 }, /* SME_tshl: immediate and qualifier field, bits [20:18]. */ + { 11, 2 }, /* rotate1: FCMLA immediate rotate. */ + { 13, 2 }, /* rotate2: Indexed element FCMLA immediate rotate. */ + { 12, 1 }, /* rotate3: FCADD immediate rotate. */ +@@ -3473,6 +3477,14 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, + snprintf (buf, size, "%s", opnd->reg.regno == 's' ? "sm" : "za"); + break; + ++ case AARCH64_OPND_SME_PnT_Wm_imm: ++ snprintf (buf, size, "p%d.%s[w%d, %d]", ++ opnd->za_tile_vector.regno, ++ aarch64_get_qualifier_name (opnd->qualifier), ++ opnd->za_tile_vector.index.regno, ++ opnd->za_tile_vector.index.imm); ++ break; ++ + case AARCH64_OPND_CRn: + case AARCH64_OPND_CRm: + snprintf (buf, size, "C%" PRIi64, opnd->imm.value); +diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h +index f3000fca..49f3013c 100644 +--- a/opcodes/aarch64-opc.h ++++ b/opcodes/aarch64-opc.h +@@ -159,6 +159,10 @@ enum aarch64_field_kind + FLD_SME_Rv, + FLD_SME_Pm, + FLD_SME_zero_mask, ++ FLD_SME_Rm, ++ FLD_SME_i1, ++ FLD_SME_tszh, ++ FLD_SME_tszl, + FLD_rotate1, + FLD_rotate2, + FLD_rotate3, +diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h +index 820b0820..3c0e990f 100644 +--- a/opcodes/aarch64-tbl.h ++++ b/opcodes/aarch64-tbl.h +@@ -1509,6 +1509,13 @@ + { \ + QLF3(S_B,P_Z,S_B), \ + } ++#define OP_SVE_NN_BHSD \ ++{ \ ++ QLF3(NIL,NIL,S_B), \ ++ QLF3(NIL,NIL,S_H), \ ++ QLF3(NIL,NIL,S_S), \ ++ QLF3(NIL,NIL,S_D) \ ++} + #define OP_SVE_BZBB \ + { \ + QLF4(S_B,P_Z,S_B,S_B), \ +@@ -1537,6 +1544,10 @@ + { \ + QLF3(S_D,P_M,S_D), \ + } ++#define OP_SVE_QMQ \ ++{ \ ++ QLF3(S_Q,P_M,S_Q), \ ++} + #define OP_SVE_DMH \ + { \ + QLF3(S_D,P_M,S_H), \ +@@ -5178,6 +5189,11 @@ const struct aarch64_opcode aarch64_opcode_table[] = + SME_INSN ("ldr", 0xe1000000, 0xffff9c10, sme_ldr, 0, OP2 (SME_ZA_array, SME_ADDR_RI_U4xVL), {}, 0, 1), + SME_INSN ("str", 0xe1200000, 0xffff9c10, sme_str, 0, OP2 (SME_ZA_array, SME_ADDR_RI_U4xVL), {}, 0, 1), + ++ SME_INSNC ("revd", 0x52e8000, 0xffffe000, sme_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_QMQ, 0, C_SCAN_MOVPRFX, 0), ++ SME_INSNC ("sclamp", 0x4400c000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, C_SCAN_MOVPRFX, 0), ++ SME_INSNC ("uclamp", 0x4400c400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, C_SCAN_MOVPRFX, 0), ++ SME_INSN ("psel", 0x25204000, 0xff20c000, sme_misc, 0, OP3 (SVE_Pd, SVE_Pg4_10, SME_PnT_Wm_imm), OP_SVE_NN_BHSD, 0, 0), ++ + /* SIMD Dot Product (optional in v8.2-A). */ + DOT_INSN ("udot", 0x2e009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ), + DOT_INSN ("sdot", 0xe009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ), +@@ -5773,6 +5789,9 @@ const struct aarch64_opcode aarch64_opcode_table[] = + Y(ADDRESS, sme_sm_za, "SME_SM_ZA", 0, \ + F(FLD_CRm), \ + "streaming mode") \ ++ Y(SVE_REG, sme_pred_reg_with_index, "SME_PnT_Wm_imm", 0, \ ++ F(FLD_SME_Rm,FLD_SVE_Pn,FLD_SME_i1,FLD_SME_tszh,FLD_SME_tszl), \ ++ "Source scalable predicate register with index ") \ + Y(IMMEDIATE, imm, "TME_UIMM16", 0, F(FLD_imm16), \ + "a 16-bit unsigned immediate for TME tcancel") \ + Y(SIMD_ELEMENT, reglane, "SM3_IMM2", 0, F(FLD_SM3_imm2), \ +-- +2.19.1 + diff --git a/SME-0009-aarch64-Check-for-register-aliases-before-mnemonics.patch b/SME-0009-aarch64-Check-for-register-aliases-before-mnemonics.patch new file mode 100644 index 0000000000000000000000000000000000000000..ea96d361f0b312677db42193be64da1dc5c95c77 --- /dev/null +++ b/SME-0009-aarch64-Check-for-register-aliases-before-mnemonics.patch @@ -0,0 +1,221 @@ +From e4afe464b120e181747b1108a23e0da2d16abd99 Mon Sep 17 00:00:00 2001 +From: Richard Sandiford +Date: Tue, 30 Nov 2021 17:50:24 +0000 +Subject: [PATCH 09/10] aarch64: Check for register aliases before mnemonics + +Reference: https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=2dd3146b4ffcb8528a6e093741ba31636afdf8ae + +Previously we would not accept: + + A .req B + +if A happened to be the name of an instruction. Adding new +instructions could therefore invalidate existing register aliases. + +I noticed this with a test that used "zero" as a register alias +for "xzr", where "zero" is now also the name of an SME instruction. +I don't have any evidence that "real" code is doing this, but it +seems at least plausible. + +This patch switches things so that we check for register aliases +first. It might slow down parsing slightly, but the difference +is unlikely to be noticeable. + +Things like: + + b .req + 0 + +still work, since create_register_alias checks for " .req ", +and with the input scrubber, we'll only keep whitespace after +.req if it's followed by another name. If there's some valid +expression that I haven't thought about that is scrubbed to +" .req ", users could avoid the ambiguity by wrapping .req +in parentheses. + +The new test for invalid aliases already passed. I just wanted +something to exercise the !dot condition. + +I can't find a way of exercising the (existing) p == base condition, +but I'm not brave enough to say that it can never happen. If it does +happen, get_mnemonic_name would return an empty string. + +gas/ + * config/tc-aarch64.c (opcode_lookup): Move mnemonic extraction + code to... + (md_assemble): ...here. Check for register aliases first. + * testsuite/gas/aarch64/register_aliases.d, + testsuite/gas/aarch64/register_aliases.s: Test for a register + alias called "zero". + * testsuite/gas/aarch64/register_aliases_invalid.d, + testsuite/gas/aarch64/register_aliases_invalid.l, + testsuite/gas/aarch64/register_aliases_invalid.s: New test. +--- + gas/config/tc-aarch64.c | 62 +++++++++---------- + gas/testsuite/gas/aarch64/register_aliases.d | 1 + + gas/testsuite/gas/aarch64/register_aliases.s | 3 +- + .../gas/aarch64/register_aliases_invalid.d | 1 + + .../gas/aarch64/register_aliases_invalid.l | 3 + + .../gas/aarch64/register_aliases_invalid.s | 2 + + 6 files changed, 38 insertions(+), 34 deletions(-) + create mode 100644 gas/testsuite/gas/aarch64/register_aliases_invalid.d + create mode 100644 gas/testsuite/gas/aarch64/register_aliases_invalid.l + create mode 100644 gas/testsuite/gas/aarch64/register_aliases_invalid.s + +diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c +index ea58d9b0..c9677edc 100644 +--- a/gas/config/tc-aarch64.c ++++ b/gas/config/tc-aarch64.c +@@ -5786,25 +5786,18 @@ lookup_mnemonic (const char *start, int len) + } + + /* Subroutine of md_assemble, responsible for looking up the primary +- opcode from the mnemonic the user wrote. STR points to the +- beginning of the mnemonic. */ ++ opcode from the mnemonic the user wrote. BASE points to the beginning ++ of the mnemonic, DOT points to the first '.' within the mnemonic ++ (if any) and END points to the end of the mnemonic. */ + + static templates * +-opcode_lookup (char **str) ++opcode_lookup (char *base, char *dot, char *end) + { +- char *end, *base, *dot; + const aarch64_cond *cond; + char condname[16]; + int len; + +- /* Scan up to the end of the mnemonic, which must end in white space, +- '.', or end of string. */ +- dot = 0; +- for (base = end = *str; is_part_of_name(*end); end++) +- if (*end == '.' && !dot) +- dot = end; +- +- if (end == base || dot == base) ++ if (dot == end) + return 0; + + inst.cond = COND_ALWAYS; +@@ -5813,23 +5806,13 @@ opcode_lookup (char **str) + if (dot) + { + cond = str_hash_find_n (aarch64_cond_hsh, dot + 1, end - dot - 1); +- if (cond) +- { +- inst.cond = cond->value; +- *str = end; +- } +- else +- { +- *str = dot; +- return 0; +- } ++ if (!cond) ++ return 0; ++ inst.cond = cond->value; + len = dot - base; + } + else +- { +- *str = end; +- len = end - base; +- } ++ len = end - base; + + if (inst.cond == COND_ALWAYS) + { +@@ -7918,7 +7901,6 @@ dump_opcode_operands (const aarch64_opcode *opcode) + void + md_assemble (char *str) + { +- char *p = str; + templates *template; + const aarch64_opcode *opcode; + aarch64_inst *inst_base; +@@ -7941,14 +7923,28 @@ md_assemble (char *str) + DEBUG_TRACE ("=============================="); + DEBUG_TRACE ("Enter md_assemble with %s", str); + +- template = opcode_lookup (&p); ++ /* Scan up to the end of the mnemonic, which must end in whitespace, ++ '.', or end of string. */ ++ char *p = str; ++ char *dot = 0; ++ for (; is_part_of_name (*p); p++) ++ if (*p == '.' && !dot) ++ dot = p; ++ ++ if (p == str) ++ { ++ as_bad (_("unknown mnemonic -- `%s'"), str); ++ return; ++ } ++ ++ if (!dot && create_register_alias (str, p)) ++ return; ++ ++ template = opcode_lookup (str, dot, p); + if (!template) + { +- /* It wasn't an instruction, but it might be a register alias of +- the form alias .req reg directive. */ +- if (!create_register_alias (str, p)) +- as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str), +- str); ++ as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str), ++ str); + return; + } + +diff --git a/gas/testsuite/gas/aarch64/register_aliases.d b/gas/testsuite/gas/aarch64/register_aliases.d +index eab63870..8d614b47 100644 +--- a/gas/testsuite/gas/aarch64/register_aliases.d ++++ b/gas/testsuite/gas/aarch64/register_aliases.d +@@ -10,3 +10,4 @@ Disassembly of section \.text: + 8: f94003b1 ldr x17, \[x29\] + c: f90003b0 str x16, \[x29\] + 10: f94003b1 ldr x17, \[x29\] ++ 14: f900001f str xzr, \[x0\] +diff --git a/gas/testsuite/gas/aarch64/register_aliases.s b/gas/testsuite/gas/aarch64/register_aliases.s +index fcd06507..856be569 100644 +--- a/gas/testsuite/gas/aarch64/register_aliases.s ++++ b/gas/testsuite/gas/aarch64/register_aliases.s +@@ -3,9 +3,10 @@ + fp .req x29 + ip0 .req x16 + ip1 .req x17 ++ zero .req xzr + add ip0, ip0, lr + str ip0, [fp] + ldr ip1, [fp] + str IP0, [fp] + ldr IP1, [fp] +- ++ str zero, [x0] +diff --git a/gas/testsuite/gas/aarch64/register_aliases_invalid.d b/gas/testsuite/gas/aarch64/register_aliases_invalid.d +new file mode 100644 +index 00000000..7c453ce0 +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/register_aliases_invalid.d +@@ -0,0 +1 @@ ++#error_output: register_aliases_invalid.l +diff --git a/gas/testsuite/gas/aarch64/register_aliases_invalid.l b/gas/testsuite/gas/aarch64/register_aliases_invalid.l +new file mode 100644 +index 00000000..6350049d +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/register_aliases_invalid.l +@@ -0,0 +1,3 @@ ++.*: ++.*: Error: unknown mnemonic `lr\.req' -- `lr\.req x30' ++.*: Error: unknown mnemonic `lr\.a' -- `lr\.a .req x30' +diff --git a/gas/testsuite/gas/aarch64/register_aliases_invalid.s b/gas/testsuite/gas/aarch64/register_aliases_invalid.s +new file mode 100644 +index 00000000..2df2eaab +--- /dev/null ++++ b/gas/testsuite/gas/aarch64/register_aliases_invalid.s +@@ -0,0 +1,2 @@ ++lr.req x30 ++lr.a .req x30 +-- +2.19.1 + diff --git a/SME-0010-aarch64-Add-support-for-new-SME-instructions.patch b/SME-0010-aarch64-Add-support-for-new-SME-instructions.patch new file mode 100644 index 0000000000000000000000000000000000000000..1f7980a6c4c44dd959b291654ba309957e6cca0a --- /dev/null +++ b/SME-0010-aarch64-Add-support-for-new-SME-instructions.patch @@ -0,0 +1,1553 @@ +From bd5218efac195b1095c5d939f487e89345d72a93 Mon Sep 17 00:00:00 2001 +From: Richard Sandiford +Date: Thu, 6 Jan 2022 16:22:54 +0000 +Subject: [PATCH 10/10] aarch64: Add support for new SME instructions + +Reference: https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=27297937e0c648cdf115ecbceb4ba25dfefe7492 + +This patch adds support for three new SME instructions: ADDSPL, +ADDSVL and RDSVL. They behave like ADDPL, ADDVL and RDVL, but read +the streaming vector length instead of the current vector length. + +opcodes/ + * aarch64-tbl.h (aarch64_opcode_table): Add ADDSPL, ADDSVL and RDSVL. + * aarch64-dis-2.c: Regenerate. + +gas/ + * testsuite/gas/aarch64/sme.s, testsuite/gas/aarch64/sme.d: Add tests + for ADDSPL, ADDSVL and RDSVL. +--- + gas/testsuite/gas/aarch64/sme.d | 25 ++ + gas/testsuite/gas/aarch64/sme.s | 31 +++ + opcodes/aarch64-dis-2.c | 395 +++++++++++++++++--------------- + opcodes/aarch64-tbl.h | 3 + + 4 files changed, 273 insertions(+), 181 deletions(-) + +diff --git a/gas/testsuite/gas/aarch64/sme.d b/gas/testsuite/gas/aarch64/sme.d +index 673ac79c..f5cf1f0b 100644 +--- a/gas/testsuite/gas/aarch64/sme.d ++++ b/gas/testsuite/gas/aarch64/sme.d +@@ -91,3 +91,28 @@ Disassembly of section \.text: + 144: a1a1f893 umops za3.s, p6/m, p7/m, z4.b, z1.b + 148: a1817083 usmopa za3.s, p4/m, p3/m, z4.b, z1.b + 14c: a181f893 usmops za3.s, p6/m, p7/m, z4.b, z1.b ++[^:]+: 04605800 addspl x0, x0, #0 ++[^:]+: 04605801 addspl x1, x0, #0 ++[^:]+: 0460581f addspl sp, x0, #0 ++[^:]+: 04625800 addspl x0, x2, #0 ++[^:]+: 047f5800 addspl x0, sp, #0 ++[^:]+: 04605be0 addspl x0, x0, #31 ++[^:]+: 04605c00 addspl x0, x0, #-32 ++[^:]+: 04605c20 addspl x0, x0, #-31 ++[^:]+: 04605fe0 addspl x0, x0, #-1 ++[^:]+: 04205800 addsvl x0, x0, #0 ++[^:]+: 04205801 addsvl x1, x0, #0 ++[^:]+: 0420581f addsvl sp, x0, #0 ++[^:]+: 04225800 addsvl x0, x2, #0 ++[^:]+: 043f5800 addsvl x0, sp, #0 ++[^:]+: 04205be0 addsvl x0, x0, #31 ++[^:]+: 04205c00 addsvl x0, x0, #-32 ++[^:]+: 04205c20 addsvl x0, x0, #-31 ++[^:]+: 04205fe0 addsvl x0, x0, #-1 ++[^:]+: 04bf5800 rdsvl x0, #0 ++[^:]+: 04bf5801 rdsvl x1, #0 ++[^:]+: 04bf581f rdsvl xzr, #0 ++[^:]+: 04bf5be0 rdsvl x0, #31 ++[^:]+: 04bf5c00 rdsvl x0, #-32 ++[^:]+: 04bf5c20 rdsvl x0, #-31 ++[^:]+: 04bf5fe0 rdsvl x0, #-1 +diff --git a/gas/testsuite/gas/aarch64/sme.s b/gas/testsuite/gas/aarch64/sme.s +index ad48fa0e..659f1417 100644 +--- a/gas/testsuite/gas/aarch64/sme.s ++++ b/gas/testsuite/gas/aarch64/sme.s +@@ -121,3 +121,34 @@ umopa foo.s, p6/m, p7/m, z4.b, z1.b + umops foo.s, p6/m, p7/m, z4.b, z1.b + usmopa foo.s, p4/m, p3/m, z4.b, z1.b + usmops foo.s, p6/m, p7/m, z4.b, z1.b ++ ++/* ADDSPL. */ ++addspl x0, x0, #0 ++addspl x1, x0, #0 ++addspl sp, x0, #0 ++addspl x0, x2, #0 ++addspl x0, sp, #0 ++addspl x0, x0, #31 ++addspl x0, x0, #-32 ++addspl x0, x0, #-31 ++addspl x0, x0, #-1 ++ ++/* ADDSVL. */ ++addsvl x0, x0, #0 ++addsvl x1, x0, #0 ++addsvl sp, x0, #0 ++addsvl x0, x2, #0 ++addsvl x0, sp, #0 ++addsvl x0, x0, #31 ++addsvl x0, x0, #-32 ++addsvl x0, x0, #-31 ++addsvl x0, x0, #-1 ++ ++/* RDSVL. */ ++rdsvl x0, #0 ++rdsvl x1, #0 ++rdsvl xzr, #0 ++rdsvl x0, #31 ++rdsvl x0, #-32 ++rdsvl x0, #-31 ++rdsvl x0, #-1 +diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c +index f9999adc..0065c2a2 100644 +--- a/opcodes/aarch64-dis-2.c ++++ b/opcodes/aarch64-dis-2.c +@@ -60,7 +60,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x0000000100xxxxxxxxxxxxxxxx0xxxx + fmopa. */ +- return 2358; ++ return 2360; + } + else + { +@@ -68,7 +68,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x0000000100xxxxxxxxxxxxxxxx1xxxx + fmops. */ +- return 2361; ++ return 2363; + } + } + } +@@ -80,7 +80,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x0000000x10xxxxxxxxxxxxxxxx0xxxx + fmopa. */ +- return 2359; ++ return 2361; + } + else + { +@@ -88,7 +88,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x0000000x10xxxxxxxxxxxxxxxx1xxxx + fmops. */ +- return 2362; ++ return 2364; + } + } + } +@@ -104,7 +104,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1000000xx000x0xxxxxxxxxxxxxxxxx + mov. */ +- return 2381; ++ return 2384; + } + else + { +@@ -135,7 +135,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1000000x0010x01xxxxxxxxxxxxxxxx + addva. */ +- return 2354; ++ return 2356; + } + else + { +@@ -143,7 +143,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1000000x1010x01xxxxxxxxxxxxxxxx + addva. */ +- return 2355; ++ return 2357; + } + } + } +@@ -154,7 +154,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1000000xx0x1x0xxxxxxxxxxxxxxxxx + zero. */ +- return 2384; ++ return 2387; + } + } + else +@@ -163,7 +163,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1000000xx0xxx1xxxxxxxxxxxxxxxxx + mov. */ +- return 2380; ++ return 2383; + } + } + } +@@ -179,7 +179,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx100000000xxxxxxxxxxxxxxxx0xxxx + ld1b. */ +- return 2385; ++ return 2388; + } + else + { +@@ -189,7 +189,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x0100000100xxxxxxxxxxxxxxxx0xxxx + smopa. */ +- return 2364; ++ return 2367; + } + else + { +@@ -197,7 +197,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1100000100xxxxxxxxxxxxxxxx0xxxx + ld1w. */ +- return 2387; ++ return 2390; + } + } + } +@@ -209,7 +209,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx100000010xxxxxxxxxxxxxxxx0xxxx + ld1h. */ +- return 2386; ++ return 2389; + } + else + { +@@ -219,7 +219,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x0100000110xxxxxxxxxxxxxxxx0xxxx + smopa. */ +- return 2365; ++ return 2368; + } + else + { +@@ -227,7 +227,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1100000110xxxxxxxxxxxxxxxx0xxxx + ld1d. */ +- return 2388; ++ return 2391; + } + } + } +@@ -240,7 +240,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx100000x00xxxxxxxxxxxxxxxx1xxxx + smops. */ +- return 2366; ++ return 2369; + } + else + { +@@ -248,7 +248,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx100000x10xxxxxxxxxxxxxxxx1xxxx + smops. */ +- return 2367; ++ return 2370; + } + } + } +@@ -265,7 +265,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xxx00000001xxxxxxxxxxxxxxxx0xxxx + st1b. */ +- return 2395; ++ return 2398; + } + else + { +@@ -275,7 +275,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x0x00000101xxxxxxxxxxxxxxxx0xxxx + sumopa. */ +- return 2368; ++ return 2371; + } + else + { +@@ -283,7 +283,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1x00000101xxxxxxxxxxxxxxxx0xxxx + st1w. */ +- return 2397; ++ return 2400; + } + } + } +@@ -295,7 +295,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xxx00000011xxxxxxxxxxxxxxxx0xxxx + st1h. */ +- return 2396; ++ return 2399; + } + else + { +@@ -305,7 +305,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x0x00000111xxxxxxxxxxxxxxxx0xxxx + sumopa. */ +- return 2369; ++ return 2372; + } + else + { +@@ -313,7 +313,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1x00000111xxxxxxxxxxxxxxxx0xxxx + st1d. */ +- return 2398; ++ return 2401; + } + } + } +@@ -326,7 +326,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xxx00000x01xxxxxxxxxxxxxxxx1xxxx + sumops. */ +- return 2370; ++ return 2373; + } + else + { +@@ -334,7 +334,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xxx00000x11xxxxxxxxxxxxxxxx1xxxx + sumops. */ +- return 2371; ++ return 2374; + } + } + } +@@ -375,7 +375,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xxx00001000xxxxxxxxxxxxxxxx0xxxx + ldr. */ +- return 2405; ++ return 2408; + } + else + { +@@ -385,7 +385,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx000001100xxxxxxxxxxxxxxxx0xxxx + bfmopa. */ +- return 2356; ++ return 2358; + } + else + { +@@ -393,7 +393,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx100001100xxxxxxxxxxxxxxxx0xxxx + usmopa. */ +- return 2376; ++ return 2379; + } + } + } +@@ -405,7 +405,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x0x00001x10xxxxxxxxxxxxxxxx0xxxx + usmopa. */ +- return 2377; ++ return 2380; + } + else + { +@@ -413,7 +413,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1x00001x10xxxxxxxxxxxxxxxx0xxxx + ld1q. */ +- return 2389; ++ return 2392; + } + } + } +@@ -427,7 +427,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xxx00001001xxxxxxxxxxxxxxxx0xxxx + str. */ +- return 2406; ++ return 2409; + } + else + { +@@ -437,7 +437,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx000001101xxxxxxxxxxxxxxxx0xxxx + fmopa. */ +- return 2360; ++ return 2362; + } + else + { +@@ -445,7 +445,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx100001101xxxxxxxxxxxxxxxx0xxxx + umopa. */ +- return 2372; ++ return 2375; + } + } + } +@@ -457,7 +457,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x0x00001x11xxxxxxxxxxxxxxxx0xxxx + umopa. */ +- return 2373; ++ return 2376; + } + else + { +@@ -465,7 +465,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1x00001x11xxxxxxxxxxxxxxxx0xxxx + st1q. */ +- return 2399; ++ return 2402; + } + } + } +@@ -482,7 +482,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx000001x00xxxxxxxxxxxxxxxx1xxxx + bfmops. */ +- return 2357; ++ return 2359; + } + else + { +@@ -490,7 +490,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx100001x00xxxxxxxxxxxxxxxx1xxxx + usmops. */ +- return 2378; ++ return 2381; + } + } + else +@@ -499,7 +499,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xxx00001x10xxxxxxxxxxxxxxxx1xxxx + usmops. */ +- return 2379; ++ return 2382; + } + } + else +@@ -512,7 +512,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx000001x01xxxxxxxxxxxxxxxx1xxxx + fmops. */ +- return 2363; ++ return 2365; + } + else + { +@@ -520,7 +520,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx100001x01xxxxxxxxxxxxxxxx1xxxx + umops. */ +- return 2374; ++ return 2377; + } + } + else +@@ -529,7 +529,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xxx00001x11xxxxxxxxxxxxxxxx1xxxx + umops. */ +- return 2375; ++ return 2378; + } + } + } +@@ -2896,7 +2896,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 00011001000xxxxxxxxx00xxxxxxxxxx + stlurb. */ +- return 2451; ++ return 2454; + } + else + { +@@ -2904,7 +2904,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 10011001000xxxxxxxxx00xxxxxxxxxx + stlur. */ +- return 2459; ++ return 2462; + } + } + else +@@ -2915,7 +2915,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 01011001000xxxxxxxxx00xxxxxxxxxx + stlurh. */ +- return 2455; ++ return 2458; + } + else + { +@@ -2923,7 +2923,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 11011001000xxxxxxxxx00xxxxxxxxxx + stlur. */ +- return 2462; ++ return 2465; + } + } + } +@@ -3003,7 +3003,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 00011001010xxxxxxxxx00xxxxxxxxxx + ldapurb. */ +- return 2452; ++ return 2455; + } + else + { +@@ -3011,7 +3011,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 10011001010xxxxxxxxx00xxxxxxxxxx + ldapur. */ +- return 2460; ++ return 2463; + } + } + else +@@ -3022,7 +3022,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 01011001010xxxxxxxxx00xxxxxxxxxx + ldapurh. */ +- return 2456; ++ return 2459; + } + else + { +@@ -3030,7 +3030,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 11011001010xxxxxxxxx00xxxxxxxxxx + ldapur. */ +- return 2463; ++ return 2466; + } + } + } +@@ -3113,7 +3113,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 00011001100xxxxxxxxx00xxxxxxxxxx + ldapursb. */ +- return 2454; ++ return 2457; + } + else + { +@@ -3121,7 +3121,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 10011001100xxxxxxxxx00xxxxxxxxxx + ldapursw. */ +- return 2461; ++ return 2464; + } + } + else +@@ -3130,7 +3130,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1011001100xxxxxxxxx00xxxxxxxxxx + ldapursh. */ +- return 2458; ++ return 2461; + } + } + else +@@ -3141,7 +3141,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x0011001110xxxxxxxxx00xxxxxxxxxx + ldapursb. */ +- return 2453; ++ return 2456; + } + else + { +@@ -3149,7 +3149,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1011001110xxxxxxxxx00xxxxxxxxxx + ldapursh. */ +- return 2457; ++ return 2460; + } + } + } +@@ -3635,7 +3635,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xxx11010x00xxxxxx0xx10xxxxxxxxxx + setf8. */ +- return 2449; ++ return 2452; + } + else + { +@@ -3643,7 +3643,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xxx11010x00xxxxxx1xx10xxxxxxxxxx + setf16. */ +- return 2450; ++ return 2453; + } + } + else +@@ -3789,7 +3789,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xxx11010000xxxxxxxxx01xxxxxxxxxx + rmif. */ +- return 2448; ++ return 2451; + } + else + { +@@ -4838,7 +4838,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x01x1xxxxx000110xxxxxxxxxx + usdot. */ +- return 2468; ++ return 2471; + } + } + } +@@ -4912,7 +4912,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x01x1xxxxx000111xxxxxxxxxx + sudot. */ +- return 2469; ++ return 2472; + } + } + } +@@ -5923,21 +5923,54 @@ aarch64_opcode_lookup_1 (uint32_t word) + } + else + { +- if (((word >> 10) & 0x1) == 0) ++ if (((word >> 12) & 0x1) == 0) + { +- /* 33222222222211111111110000000000 +- 10987654321098765432109876543210 +- 000001x0xx1xxxxx010x10xxxxxxxxxx +- index. */ +- return 1508; ++ if (((word >> 10) & 0x1) == 0) ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ 000001x0xx1xxxxx010010xxxxxxxxxx ++ index. */ ++ return 1508; ++ } ++ else ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ 000001x0xx1xxxxx010011xxxxxxxxxx ++ index. */ ++ return 1505; ++ } + } + else + { +- /* 33222222222211111111110000000000 +- 10987654321098765432109876543210 +- 000001x0xx1xxxxx010x11xxxxxxxxxx +- index. */ +- return 1505; ++ if (((word >> 22) & 0x1) == 0) ++ { ++ if (((word >> 23) & 0x1) == 0) ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ 000001x0001xxxxx01011xxxxxxxxxxx ++ addsvl. */ ++ return 2355; ++ } ++ else ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ 000001x0101xxxxx01011xxxxxxxxxxx ++ rdsvl. */ ++ return 2366; ++ } ++ } ++ else ++ { ++ /* 33222222222211111111110000000000 ++ 10987654321098765432109876543210 ++ 000001x0x11xxxxx01011xxxxxxxxxxx ++ addspl. */ ++ return 2354; ++ } + } + } + } +@@ -6290,7 +6323,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0xx0xxxxx110xx0xxxxxxxxxx + sclamp. */ +- return 2408; ++ return 2411; + } + else + { +@@ -6298,7 +6331,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0xx0xxxxx110xx1xxxxxxxxxx + uclamp. */ +- return 2409; ++ return 2412; + } + } + else +@@ -7553,7 +7586,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x0xx0xxxxx011110xxxxxxxxxx + usdot. */ +- return 2467; ++ return 2470; + } + } + } +@@ -9257,7 +9290,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0100xxx10101xxxxxxxxxxxxx + bfcvtnt. */ +- return 2496; ++ return 2499; + } + } + else +@@ -9500,7 +9533,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x00x1xxxxxx00xxxxxxxxxxxxx + ld1rob. */ +- return 2472; ++ return 2475; + } + else + { +@@ -9508,7 +9541,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x01x1xxxxxx00xxxxxxxxxxxxx + ld1roh. */ +- return 2473; ++ return 2476; + } + } + else +@@ -9740,7 +9773,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0011xxxxx010xxxxxxxxxxxxx + bfdot. */ +- return 2493; ++ return 2496; + } + else + { +@@ -9761,7 +9794,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0111xxxxx010xx0xxxxxxxxxx + bfmlalb. */ +- return 2500; ++ return 2503; + } + else + { +@@ -9769,7 +9802,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0111xxxxx010xx1xxxxxxxxxx + bfmlalt. */ +- return 2499; ++ return 2502; + } + } + else +@@ -9824,7 +9857,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x11001x0011xxxxx1x0xxxxxxxxxxxxx + bfdot. */ +- return 2492; ++ return 2495; + } + else + { +@@ -9836,7 +9869,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0111xxxxx1x0xx0xxxxxxxxxx + bfmlalb. */ +- return 2498; ++ return 2501; + } + else + { +@@ -9844,7 +9877,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0111xxxxx1x0xx1xxxxxxxxxx + bfmlalt. */ +- return 2497; ++ return 2500; + } + } + else +@@ -9895,7 +9928,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x00x1xxxxx001xxxxxxxxxxxxx + ld1rob. */ +- return 2476; ++ return 2479; + } + else + { +@@ -9903,7 +9936,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x01x1xxxxx001xxxxxxxxxxxxx + ld1roh. */ +- return 2477; ++ return 2480; + } + } + else +@@ -10262,7 +10295,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0101xxxxx111xxxxxxxxxxxxx + fmmla. */ +- return 2470; ++ return 2473; + } + else + { +@@ -10295,7 +10328,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0011xxxxx111xxxxxxxxxxxxx + bfmmla. */ +- return 2494; ++ return 2497; + } + else + { +@@ -10325,7 +10358,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x0111xxxxx111xxxxxxxxxxxxx + fmmla. */ +- return 2471; ++ return 2474; + } + else + { +@@ -10454,7 +10487,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1101xxxxx000x00xxxxxxxxxx + zip1. */ +- return 2480; ++ return 2483; + } + else + { +@@ -10464,7 +10497,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1101xxxxx000010xxxxxxxxxx + uzp1. */ +- return 2482; ++ return 2485; + } + else + { +@@ -10472,7 +10505,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1101xxxxx000110xxxxxxxxxx + trn1. */ +- return 2484; ++ return 2487; + } + } + } +@@ -10484,7 +10517,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1101xxxxx000x01xxxxxxxxxx + zip2. */ +- return 2481; ++ return 2484; + } + else + { +@@ -10494,7 +10527,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1101xxxxx000011xxxxxxxxxx + uzp2. */ +- return 2483; ++ return 2486; + } + else + { +@@ -10502,7 +10535,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1101xxxxx000111xxxxxxxxxx + trn2. */ +- return 2485; ++ return 2488; + } + } + } +@@ -10599,7 +10632,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000001x1xx1x1110100xxxxxxxxxxxxx + revd. */ +- return 2407; ++ return 2410; + } + } + } +@@ -11561,7 +11594,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1000xxxxx100110xxxxxxxxxx + smmla. */ +- return 2464; ++ return 2467; + } + else + { +@@ -11569,7 +11602,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1100xxxxx100110xxxxxxxxxx + usmmla. */ +- return 2466; ++ return 2469; + } + } + else +@@ -11578,7 +11611,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010001x1x10xxxxx100110xxxxxxxxxx + ummla. */ +- return 2465; ++ return 2468; + } + } + } +@@ -13074,7 +13107,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x10x1xxxxx000xxxxxxxxxxxxx + ld1row. */ +- return 2474; ++ return 2477; + } + else + { +@@ -13082,7 +13115,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x11x1xxxxx000xxxxxxxxxxxxx + ld1rod. */ +- return 2475; ++ return 2478; + } + } + } +@@ -13456,7 +13489,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x10x1xxxxx001xxxxxxxxxxxxx + ld1row. */ +- return 2478; ++ return 2481; + } + else + { +@@ -13464,7 +13497,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 101001x11x1xxxxx001xxxxxxxxxxxxx + ld1rod. */ +- return 2479; ++ return 2482; + } + } + } +@@ -13807,7 +13840,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 001001x1xx1xxxxx01xxxxxxxxxxxxxx + psel. */ +- return 2410; ++ return 2413; + } + else + { +@@ -14909,7 +14942,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 011001x110001x10101xxxxxxxxxxxxx + bfcvt. */ +- return 2495; ++ return 2498; + } + } + else +@@ -16978,7 +17011,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 0x001110xx0xxxxx1x1001xxxxxxxxxx + smmla. */ +- return 2486; ++ return 2489; + } + } + } +@@ -17011,7 +17044,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 0x001110xx0xxxxx1x0101xxxxxxxxxx + sdot. */ +- return 2412; ++ return 2415; + } + } + else +@@ -17085,7 +17118,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 0x001110xx0xxxxx1x1011xxxxxxxxxx + usmmla. */ +- return 2488; ++ return 2491; + } + } + } +@@ -17118,7 +17151,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 0x001110xx0xxxxx1x0111xxxxxxxxxx + usdot. */ +- return 2489; ++ return 2492; + } + } + else +@@ -17165,7 +17198,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110000xxxxxxxxxxxxxxxxxxxxx + eor3. */ +- return 2419; ++ return 2422; + } + else + { +@@ -17173,7 +17206,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110100xxxxxxxxxxxxxxxxxxxxx + xar. */ +- return 2421; ++ return 2424; + } + } + else +@@ -17184,7 +17217,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110x10xxxxx0xxxxxxxxxxxxxxx + sm3ss1. */ +- return 2423; ++ return 2426; + } + else + { +@@ -17198,7 +17231,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110010xxxxx1xxx00xxxxxxxxxx + sm3tt1a. */ +- return 2424; ++ return 2427; + } + else + { +@@ -17206,7 +17239,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110110xxxxx1xxx00xxxxxxxxxx + sha512su0. */ +- return 2417; ++ return 2420; + } + } + else +@@ -17215,7 +17248,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110x10xxxxx1xxx10xxxxxxxxxx + sm3tt2a. */ +- return 2426; ++ return 2429; + } + } + else +@@ -17228,7 +17261,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110010xxxxx1xxx01xxxxxxxxxx + sm3tt1b. */ +- return 2425; ++ return 2428; + } + else + { +@@ -17236,7 +17269,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110110xxxxx1xxx01xxxxxxxxxx + sm4e. */ +- return 2430; ++ return 2433; + } + } + else +@@ -17245,7 +17278,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110x10xxxxx1xxx11xxxxxxxxxx + sm3tt2b. */ +- return 2427; ++ return 2430; + } + } + } +@@ -17426,7 +17459,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx101110xx0xxxxx100101xxxxxxxxxx + udot. */ +- return 2411; ++ return 2414; + } + } + else +@@ -17457,7 +17490,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx101110xx0xxxxx101x01xxxxxxxxxx + ummla. */ +- return 2487; ++ return 2490; + } + else + { +@@ -17476,7 +17509,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx101110xx0xxxxx1x1011xxxxxxxxxx + bfmmla. */ +- return 2503; ++ return 2506; + } + else + { +@@ -17486,7 +17519,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx1011100x0xxxxx1x1111xxxxxxxxxx + bfdot. */ +- return 2501; ++ return 2504; + } + else + { +@@ -17496,7 +17529,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x01011101x0xxxxx1x1111xxxxxxxxxx + bfmlalb. */ +- return 2508; ++ return 2511; + } + else + { +@@ -17504,7 +17537,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x11011101x0xxxxx1x1111xxxxxxxxxx + bfmlalt. */ +- return 2507; ++ return 2510; + } + } + } +@@ -18088,7 +18121,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 000011101x1xxxx1011010xxxxxxxxxx + bfcvtn. */ +- return 2504; ++ return 2507; + } + else + { +@@ -18096,7 +18129,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 010011101x1xxxx1011010xxxxxxxxxx + bfcvtn2. */ +- return 2505; ++ return 2508; + } + } + } +@@ -18414,7 +18447,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110xx1xxxxx0xxxxxxxxxxxxxxx + bcax. */ +- return 2422; ++ return 2425; + } + } + else +@@ -19025,7 +19058,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 11001110xx1xxxxx100000xxxxxxxxxx + sha512h. */ +- return 2415; ++ return 2418; + } + } + } +@@ -19077,7 +19110,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 11001110xx1xxxxx110000xxxxxxxxxx + sm3partw1. */ +- return 2428; ++ return 2431; + } + } + } +@@ -19320,7 +19353,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110xx1xxxxx100010xxxxxxxxxx + sha512su1. */ +- return 2418; ++ return 2421; + } + } + else +@@ -19396,7 +19429,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x0011100x1xxxxx110010xxxxxxxxxx + sm4ekey. */ +- return 2431; ++ return 2434; + } + } + else +@@ -20222,7 +20255,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110xx1xxxxx100001xxxxxxxxxx + sha512h2. */ +- return 2416; ++ return 2419; + } + } + else +@@ -20254,7 +20287,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x0011100x1xxxxx110001xxxxxxxxxx + sm3partw2. */ +- return 2429; ++ return 2432; + } + } + else +@@ -20494,7 +20527,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + 1x001110xx1xxxxx100011xxxxxxxxxx + rax1. */ +- return 2420; ++ return 2423; + } + } + else +@@ -20526,7 +20559,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x01011100x1xxxxx110011xxxxxxxxxx + fmlal2. */ +- return 2434; ++ return 2437; + } + else + { +@@ -20534,7 +20567,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x11011100x1xxxxx110011xxxxxxxxxx + fmlal2. */ +- return 2438; ++ return 2441; + } + } + } +@@ -20556,7 +20589,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x01011101x1xxxxx110011xxxxxxxxxx + fmlsl2. */ +- return 2435; ++ return 2438; + } + else + { +@@ -20564,7 +20597,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x11011101x1xxxxx110011xxxxxxxxxx + fmlsl2. */ +- return 2439; ++ return 2442; + } + } + } +@@ -20603,7 +20636,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x00011100x1xxxxx111011xxxxxxxxxx + fmlal. */ +- return 2432; ++ return 2435; + } + else + { +@@ -20611,7 +20644,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x10011100x1xxxxx111011xxxxxxxxxx + fmlal. */ +- return 2436; ++ return 2439; + } + } + else +@@ -20633,7 +20666,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x00011101x1xxxxx111011xxxxxxxxxx + fmlsl. */ +- return 2433; ++ return 2436; + } + else + { +@@ -20641,7 +20674,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x10011101x1xxxxx111011xxxxxxxxxx + fmlsl. */ +- return 2437; ++ return 2440; + } + } + else +@@ -22449,7 +22482,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x0001111xxxxxxxx0000x0xxxxxxxxxx + fmlal. */ +- return 2440; ++ return 2443; + } + else + { +@@ -22457,7 +22490,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1001111xxxxxxxx0000x0xxxxxxxxxx + fmlal. */ +- return 2444; ++ return 2447; + } + } + else +@@ -22479,7 +22512,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x0001111xxxxxxxx0100x0xxxxxxxxxx + fmlsl. */ +- return 2441; ++ return 2444; + } + else + { +@@ -22487,7 +22520,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1001111xxxxxxxx0100x0xxxxxxxxxx + fmlsl. */ +- return 2445; ++ return 2448; + } + } + else +@@ -22993,7 +23026,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x0101111xxxxxxxx1000x0xxxxxxxxxx + fmlal2. */ +- return 2442; ++ return 2445; + } + else + { +@@ -23001,7 +23034,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1101111xxxxxxxx1000x0xxxxxxxxxx + fmlal2. */ +- return 2446; ++ return 2449; + } + } + } +@@ -23023,7 +23056,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x0101111xxxxxxxx1100x0xxxxxxxxxx + fmlsl2. */ +- return 2443; ++ return 2446; + } + else + { +@@ -23031,7 +23064,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x1101111xxxxxxxx1100x0xxxxxxxxxx + fmlsl2. */ +- return 2447; ++ return 2450; + } + } + } +@@ -23087,7 +23120,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx001111xxxxxxxx1110x0xxxxxxxxxx + sdot. */ +- return 2414; ++ return 2417; + } + else + { +@@ -23095,7 +23128,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx101111xxxxxxxx1110x0xxxxxxxxxx + udot. */ +- return 2413; ++ return 2416; + } + } + } +@@ -23198,7 +23231,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx00111100xxxxxx1111x0xxxxxxxxxx + sudot. */ +- return 2491; ++ return 2494; + } + else + { +@@ -23206,7 +23239,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx00111110xxxxxx1111x0xxxxxxxxxx + usdot. */ +- return 2490; ++ return 2493; + } + } + else +@@ -23217,7 +23250,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + xx00111101xxxxxx1111x0xxxxxxxxxx + bfdot. */ +- return 2502; ++ return 2505; + } + else + { +@@ -23227,7 +23260,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x000111111xxxxxx1111x0xxxxxxxxxx + bfmlalb. */ +- return 2510; ++ return 2513; + } + else + { +@@ -23235,7 +23268,7 @@ aarch64_opcode_lookup_1 (uint32_t word) + 10987654321098765432109876543210 + x100111111xxxxxx1111x0xxxxxxxxxx + bfmlalt. */ +- return 2509; ++ return 2512; + } + } + } +@@ -23722,30 +23755,30 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode) + int value; + switch (key) + { +- case 2381: value = 2383; break; /* mov --> mova. */ +- case 2383: return NULL; /* mova --> NULL. */ +- case 2380: value = 2382; break; /* mov --> mova. */ +- case 2382: return NULL; /* mova --> NULL. */ +- case 2385: value = 2390; break; /* ld1b --> ld1b. */ +- case 2390: return NULL; /* ld1b --> NULL. */ +- case 2387: value = 2392; break; /* ld1w --> ld1w. */ +- case 2392: return NULL; /* ld1w --> NULL. */ +- case 2386: value = 2391; break; /* ld1h --> ld1h. */ +- case 2391: return NULL; /* ld1h --> NULL. */ +- case 2388: value = 2393; break; /* ld1d --> ld1d. */ +- case 2393: return NULL; /* ld1d --> NULL. */ +- case 2395: value = 2400; break; /* st1b --> st1b. */ +- case 2400: return NULL; /* st1b --> NULL. */ +- case 2397: value = 2402; break; /* st1w --> st1w. */ +- case 2402: return NULL; /* st1w --> NULL. */ +- case 2396: value = 2401; break; /* st1h --> st1h. */ +- case 2401: return NULL; /* st1h --> NULL. */ +- case 2398: value = 2403; break; /* st1d --> st1d. */ +- case 2403: return NULL; /* st1d --> NULL. */ +- case 2389: value = 2394; break; /* ld1q --> ld1q. */ +- case 2394: return NULL; /* ld1q --> NULL. */ +- case 2399: value = 2404; break; /* st1q --> st1q. */ +- case 2404: return NULL; /* st1q --> NULL. */ ++ case 2384: value = 2386; break; /* mov --> mova. */ ++ case 2386: return NULL; /* mova --> NULL. */ ++ case 2383: value = 2385; break; /* mov --> mova. */ ++ case 2385: return NULL; /* mova --> NULL. */ ++ case 2388: value = 2393; break; /* ld1b --> ld1b. */ ++ case 2393: return NULL; /* ld1b --> NULL. */ ++ case 2390: value = 2395; break; /* ld1w --> ld1w. */ ++ case 2395: return NULL; /* ld1w --> NULL. */ ++ case 2389: value = 2394; break; /* ld1h --> ld1h. */ ++ case 2394: return NULL; /* ld1h --> NULL. */ ++ case 2391: value = 2396; break; /* ld1d --> ld1d. */ ++ case 2396: return NULL; /* ld1d --> NULL. */ ++ case 2398: value = 2403; break; /* st1b --> st1b. */ ++ case 2403: return NULL; /* st1b --> NULL. */ ++ case 2400: value = 2405; break; /* st1w --> st1w. */ ++ case 2405: return NULL; /* st1w --> NULL. */ ++ case 2399: value = 2404; break; /* st1h --> st1h. */ ++ case 2404: return NULL; /* st1h --> NULL. */ ++ case 2401: value = 2406; break; /* st1d --> st1d. */ ++ case 2406: return NULL; /* st1d --> NULL. */ ++ case 2392: value = 2397; break; /* ld1q --> ld1q. */ ++ case 2397: return NULL; /* ld1q --> NULL. */ ++ case 2402: value = 2407; break; /* st1q --> st1q. */ ++ case 2407: return NULL; /* st1q --> NULL. */ + case 12: value = 19; break; /* add --> addg. */ + case 19: return NULL; /* addg --> NULL. */ + case 16: value = 20; break; /* sub --> subg. */ +@@ -23897,8 +23930,8 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode) + case 824: return NULL; /* fsqrt --> NULL. */ + case 832: value = 833; break; /* frintz --> frintz. */ + case 833: return NULL; /* frintz --> NULL. */ +- case 825: value = 2506; break; /* fcvt --> bfcvt. */ +- case 2506: return NULL; /* bfcvt --> NULL. */ ++ case 825: value = 2509; break; /* fcvt --> bfcvt. */ ++ case 2509: return NULL; /* bfcvt --> NULL. */ + case 834: value = 835; break; /* frinta --> frinta. */ + case 835: return NULL; /* frinta --> NULL. */ + case 836: value = 837; break; /* frintx --> frintx. */ +diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h +index 3c0e990f..07179c69 100644 +--- a/opcodes/aarch64-tbl.h ++++ b/opcodes/aarch64-tbl.h +@@ -5128,6 +5128,8 @@ const struct aarch64_opcode aarch64_opcode_table[] = + /* SME instructions. */ + SME_INSN ("addha", 0xc0900000, 0xffff001c, sme_misc, 0, OP4 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn), OP_SME_ZADA_PN_PM_ZN_S, 0, 0), + SME_I64_INSN ("addha", 0xc0d00000, 0xffff0018, sme_misc, 0, OP4 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn), OP_SME_ZADA_PN_PM_ZN_D, 0, 0), ++ SME_INSN ("addspl", 0x04605800, 0xffe0f800, sme_misc, 0, OP3 (Rd_SP, SVE_Rn_SP, SVE_SIMM6), OP_SVE_XXU, 0, 0), ++ SME_INSN ("addsvl", 0x04205800, 0xffe0f800, sme_misc, 0, OP3 (Rd_SP, SVE_Rn_SP, SVE_SIMM6), OP_SVE_XXU, 0, 0), + SME_INSN ("addva", 0xc0910000, 0xffff001c, sme_misc, 0, OP4 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn), OP_SME_ZADA_PN_PM_ZN_S, 0, 0), + SME_I64_INSN ("addva", 0xc0d10000, 0xffff0018, sme_misc, 0, OP4 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn), OP_SME_ZADA_PN_PM_ZN_D, 0, 0), + SME_INSN ("bfmopa", 0x81800000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_PN_PM_ZN_ZM, 0, 0), +@@ -5138,6 +5140,7 @@ const struct aarch64_opcode aarch64_opcode_table[] = + SME_INSN ("fmops", 0x80800010, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_S_S, 0, 0), + SME_F64_INSN ("fmops", 0x80c00010, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_D_D, 0, 0), + SME_INSN ("fmops", 0x81a00010, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_H_H, 0, 0), ++ SME_INSN ("rdsvl", 0x04bf5800, 0xfffff800, sme_misc, 0, OP2 (Rd, SVE_SIMM6), OP_SVE_XU, 0, 0), + SME_INSN ("smopa", 0xa0800000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_B_B, 0, 0), + SME_I64_INSN ("smopa", 0xa0c00000, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_H_H, 0, 0), + SME_INSN ("smops", 0xa0800010, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_B_B, 0, 0), +-- +2.19.1 + diff --git a/CVE-2019-1010204.patch b/backport-CVE-2019-1010204.patch similarity index 100% rename from CVE-2019-1010204.patch rename to backport-CVE-2019-1010204.patch diff --git a/CVE-2022-47008.patch b/backport-CVE-2022-47008.patch similarity index 100% rename from CVE-2022-47008.patch rename to backport-CVE-2022-47008.patch diff --git a/Fix-a-potential-use-of-an-uninitialised-value-in-the.patch b/backport-Fix-a-potential-use-of-an-uninitialised-value-in-the.patch similarity index 100% rename from Fix-a-potential-use-of-an-uninitialised-value-in-the.patch rename to backport-Fix-a-potential-use-of-an-uninitialised-value-in-the.patch diff --git a/backport-0001-PR28391-strip-objcopy-preserve-dates-.a-cannot-set-t.patch b/backport-PR28391-strip-objcopy-preserve-dates-.a-cannot-set-t.patch similarity index 100% rename from backport-0001-PR28391-strip-objcopy-preserve-dates-.a-cannot-set-t.patch rename to backport-PR28391-strip-objcopy-preserve-dates-.a-cannot-set-t.patch diff --git a/bfd-Close-the-file-descriptor-if-there-is-no-archive.patch b/backport-bfd-Close-the-file-descriptor-if-there-is-no-archive.patch similarity index 100% rename from bfd-Close-the-file-descriptor-if-there-is-no-archive.patch rename to backport-bfd-Close-the-file-descriptor-if-there-is-no-archive.patch diff --git a/binutils-AArch64-EFI.patch b/backport-binutils-AArch64-EFI.patch similarity index 100% rename from binutils-AArch64-EFI.patch rename to backport-binutils-AArch64-EFI.patch diff --git a/backport-0001-texi2pod.pl-add-no-op-no-split-option-support-PR2814.patch b/backport-texi2pod.pl-add-no-op-no-split-option-support-PR2814.patch similarity index 100% rename from backport-0001-texi2pod.pl-add-no-op-no-split-option-support-PR2814.patch rename to backport-texi2pod.pl-add-no-op-no-split-option-support-PR2814.patch diff --git a/binutils.spec b/binutils.spec index 3f60d523407f7441d91ffa0e48fa822c632fd275..e8204c1aaa57ddbae2480d6bf09196bfa76b0c1e 100644 --- a/binutils.spec +++ b/binutils.spec @@ -1,7 +1,7 @@ Summary: Binary utilities Name: binutils Version: 2.37 -Release: 25 +Release: 26 License: GPLv3+ URL: https://sourceware.org/binutils @@ -14,96 +14,116 @@ Source: https://ftp.gnu.org/gnu/binutils/binutils-%{version}.tar.xz %bcond_with gold %endif -Patch0: binutils-2.20.51.0.2-libtool-lib64.patch -Patch1: export-demangle.h-in-devel-package.patch -#BUZ:845084 -Patch2: binutils-2.22.52.0.4-no-config-h-check.patch -#BUG:1452111 -Patch3: binutils-2.27-aarch64-ifunc.patch - -#PATCH-CVE-UPSTREAM -Patch4: CVE-2019-1010204.patch - -Patch5: Fix-a-potential-use-of-an-uninitialised-value-in-the.patch -Patch6: backport-CVE-2021-45078.patch -Patch7: backport-0001-CVE-2021-42574.patch -Patch8: backport-0002-CVE-2021-42574.patch -Patch9: backport-0003-CVE-2021-42574.patch -Patch10: bfd-Close-the-file-descriptor-if-there-is-no-archive.patch -Patch11: binutils-AArch64-EFI.patch -Patch12: backport-0001-PR28391-strip-objcopy-preserve-dates-.a-cannot-set-t.patch - -Patch13: 0001-x86-Add-int1-as-one-byte-opcode-0xf1.patch -Patch14: 0002-x86-drop-OP_Mask.patch -Patch15: 0003-x86-correct-VCVT-U-SI2SD-rounding-mode-handling.patch -Patch16: 0004-x86-64-generalize-OP_G-s-EVEX.R-handling.patch -Patch17: 0005-x86-64-properly-bounds-check-bnd-N-in-OP_G.patch -Patch18: 0006-x86-fold-duplicate-register-printing-code.patch -Patch19: 0007-x86-fold-duplicate-code-in-MOVSXD_Fixup.patch -Patch20: 0008-x86-correct-EVEX.V-handling-outside-of-64-bit-mode.patch -Patch21: 0009-x86-drop-vex_mode-and-vex_scalar_mode.patch -Patch22: 0010-x86-fold-duplicate-vector-register-printing-code.patch -Patch23: 0011-x86-drop-xmm_m-b-w-d-q-_mode.patch -Patch24: 0012-x86-drop-vex_scalar_w_dq_mode.patch -Patch25: 0013-x86-drop-dq-b-d-_mode.patch -Patch26: 0014-x86-express-unduly-set-rounding-control-bits-in-disa.patch -Patch27: 0015-x86-Simplify-check-for-distinct-TMM-register-operand.patch -Patch28: 0016-PATCH-1-2-Enable-Intel-AVX512_FP16-instructions.patch -Patch29: 0017-PATCH-2-2-Add-tests-for-Intel-AVX512_FP16-instructio.patch -Patch30: 0018-x86-ELF-fix-.tfloat-output.patch -Patch31: 0019-x86-ELF-fix-.ds.x-output.patch -Patch32: 0020-x86-ELF-fix-.tfloat-output-with-hex-input.patch -Patch33: 0021-x86-introduce-.hfloat-directive.patch -Patch34: 0022-x86-Avoid-abort-on-invalid-broadcast.patch -Patch35: 0023-x86-Put-back-3-aborts-in-OP_E_memory.patch -Patch36: 0024-x86-Print-bad-on-invalid-broadcast-in-OP_E_memory.patch -Patch37: 0025-x86-Terminate-mnemonicendp-in-swap_operand.patch -Patch38: 0026-opcodes-Make-i386-dis.c-thread-safe.patch -Patch39: 0027-x86-reduce-AVX512-FP16-set-of-insns-decoded-through-.patch -Patch40: 0028-x86-reduce-AVX512-FP-set-of-insns-decoded-through-ve.patch -Patch41: 0029-x86-consistently-use-scalar_mode-for-AVX512-FP16-sca.patch -Patch42: backport-CVE-2022-38126.patch - -Patch43: backport-0001-texi2pod.pl-add-no-op-no-split-option-support-PR2814.patch - -Patch44: backport-AArch64-Add-support-for-AArch64-EFI-efi-aarch64.patch -Patch45: backport-Add-support-for-AArch64-EFI-efi-aarch64.patch -Patch46: backport-don-t-over-align-file-positions-of-PE-executable-sec.patch -Patch47: backport-PR28186-SEGV-elf.c-7991-30-in-_bfd_elf_fixup_group_sections.patch -Patch48: backport-PR28422-build_id-use-after-free.patch -Patch49: backport-PR28540-segmentation-fault-on-NULL-byte_get.patch -Patch50: Fix-gold-relocation-offset-and-adrp-signed-shife.patch -Patch51: CVE-2022-47008.patch -Patch52: backport-CVE-2022-47011.patch -Patch53: backport-CVE-2022-47696.patch -Patch54: backport-CVE-2021-46174.patch -Patch55: backport-CVE-2023-1972.patch -Patch56: backport-CVE-2022-48064.patch -Patch57: backport-CVE-2022-4285.patch -Patch58: backport-CVE-2022-38533.patch +# OpenEuler Patch Naming Rules +# https://gitee.com/openeuler/TC/blob/master/oEEP/oEEP-0012%20openEuler%E8%BD%AF%E4%BB%B6%E5%8C%85%E9%9D%9Eupstream%E6%94%AF%E6%8C%81%E5%A4%9A%E6%9E%B6%E6%9E%84%E4%BB%A3%E7%A0%81%E6%8F%90%E4%BA%A4%E8%A7%84%E5%88%99.md + +# Patch 3000 - 4999 + +Patch3001: backport-CVE-2019-1010204.patch +Patch3002: backport-Fix-a-potential-use-of-an-uninitialised-value-in-the.patch +Patch3003: backport-CVE-2021-45078.patch +Patch3004: backport-0001-CVE-2021-42574.patch +Patch3005: backport-0002-CVE-2021-42574.patch +Patch3006: backport-0003-CVE-2021-42574.patch +Patch3007: backport-bfd-Close-the-file-descriptor-if-there-is-no-archive.patch +Patch3008: backport-binutils-AArch64-EFI.patch +Patch3009: backport-PR28391-strip-objcopy-preserve-dates-.a-cannot-set-t.patch + +# AVX512 +Patch3010: AVX512-0001-x86-Add-int1-as-one-byte-opcode-0xf1.patch +Patch3011: AVX512-0002-x86-drop-OP_Mask.patch +Patch3012: AVX512-0003-x86-correct-VCVT-U-SI2SD-rounding-mode-handling.patch +Patch3013: AVX512-0004-x86-64-generalize-OP_G-s-EVEX.R-handling.patch +Patch3014: AVX512-0005-x86-64-properly-bounds-check-bnd-N-in-OP_G.patch +Patch3015: AVX512-0006-x86-fold-duplicate-register-printing-code.patch +Patch3016: AVX512-0007-x86-fold-duplicate-code-in-MOVSXD_Fixup.patch +Patch3017: AVX512-0008-x86-correct-EVEX.V-handling-outside-of-64-bit-mode.patch +Patch3018: AVX512-0009-x86-drop-vex_mode-and-vex_scalar_mode.patch +Patch3019: AVX512-0010-x86-fold-duplicate-vector-register-printing-code.patch +Patch3020: AVX512-0011-x86-drop-xmm_m-b-w-d-q-_mode.patch +Patch3021: AVX512-0012-x86-drop-vex_scalar_w_dq_mode.patch +Patch3022: AVX512-0013-x86-drop-dq-b-d-_mode.patch +Patch3023: AVX512-0014-x86-express-unduly-set-rounding-control-bits-in-disa.patch +Patch3024: AVX512-0015-x86-Simplify-check-for-distinct-TMM-register-operand.patch +Patch3025: AVX512-0016-PATCH-1-2-Enable-Intel-AVX512_FP16-instructions.patch +Patch3026: AVX512-0017-PATCH-2-2-Add-tests-for-Intel-AVX512_FP16-instructio.patch +Patch3027: AVX512-0018-x86-ELF-fix-.tfloat-output.patch +Patch3028: AVX512-0019-x86-ELF-fix-.ds.x-output.patch +Patch3029: AVX512-0020-x86-ELF-fix-.tfloat-output-with-hex-input.patch +Patch3030: AVX512-0021-x86-introduce-.hfloat-directive.patch +Patch3031: AVX512-0022-x86-Avoid-abort-on-invalid-broadcast.patch +Patch3032: AVX512-0023-x86-Put-back-3-aborts-in-OP_E_memory.patch +Patch3033: AVX512-0024-x86-Print-bad-on-invalid-broadcast-in-OP_E_memory.patch +Patch3034: AVX512-0025-x86-Terminate-mnemonicendp-in-swap_operand.patch +Patch3035: AVX512-0026-opcodes-Make-i386-dis.c-thread-safe.patch +Patch3036: AVX512-0027-x86-reduce-AVX512-FP16-set-of-insns-decoded-through-.patch +Patch3037: AVX512-0028-x86-reduce-AVX512-FP-set-of-insns-decoded-through-ve.patch +Patch3038: AVX512-0029-x86-consistently-use-scalar_mode-for-AVX512-FP16-sca.patch + +Patch3039: backport-CVE-2022-38126.patch +Patch3040: backport-texi2pod.pl-add-no-op-no-split-option-support-PR2814.patch +Patch3041: backport-AArch64-Add-support-for-AArch64-EFI-efi-aarch64.patch +Patch3042: backport-Add-support-for-AArch64-EFI-efi-aarch64.patch +Patch3043: backport-don-t-over-align-file-positions-of-PE-executable-sec.patch +Patch3044: backport-PR28186-SEGV-elf.c-7991-30-in-_bfd_elf_fixup_group_sections.patch +Patch3045: backport-PR28422-build_id-use-after-free.patch +Patch3046: backport-PR28540-segmentation-fault-on-NULL-byte_get.patch +Patch3047: backport-CVE-2022-47008.patch +Patch3048: backport-CVE-2022-47011.patch +Patch3049: backport-CVE-2022-47696.patch +Patch3050: backport-CVE-2021-46174.patch +Patch3051: backport-CVE-2023-1972.patch +Patch3052: backport-CVE-2022-48064.patch +Patch3053: backport-CVE-2022-4285.patch +Patch3054: backport-CVE-2022-38533.patch + +# SME +Patch3055: SME-0001-aarch64-SME-Add-sme-option-to-march.patch +Patch3056: SME-0002-aarch64-SME-Add-SME-instructions.patch +Patch3057: SME-0003-aarch64-SME-Add-MOV-and-MOVA-instructions.patch +Patch3058: SME-0004-aarch64-SME-Add-ZERO-instruction.patch +Patch3059: SME-0005-aarch64-SME-Add-LD1x-ST1x-LDR-and-STR-instructions.patch +Patch3060: SME-0006-aarch64-SME-Add-SME-mode-selection-and-state-access-.patch +Patch3061: SME-0007-aarch64-SME-Add-new-SME-system-registers.patch +Patch3062: SME-0008-aarch64-SME-SVE2-instructions-added-to-support-SME.patch +Patch3063: SME-0009-aarch64-Check-for-register-aliases-before-mnemonics.patch +Patch3064: SME-0010-aarch64-Add-support-for-new-SME-instructions.patch %ifarch loongarch64 -# LoongArch-related patches start with Patch101 -Patch1000: LoongArch-binutils-Add-LoongArch-support.patch -Patch1001: LoongArch-Fixup-unresolve-symbols-problem.patch -Patch1002: LoongArch-Fix-PLT-entry-generate-bug.patch -Patch1003: LoongArch-gas-add-support-using-constant-variable-in.patch -Patch1004: LoongArch-Fixup-gas-check-illegal-for-b-label.patch -Patch1005: LoongArch-Fixup-check-file-for-ifunc-reloc.patch +# LoongArch +Patch4001: LoongArch-binutils-Add-LoongArch-support.patch +Patch4002: LoongArch-Fixup-unresolve-symbols-problem.patch +Patch4003: LoongArch-Fix-PLT-entry-generate-bug.patch +Patch4004: LoongArch-gas-add-support-using-constant-variable-in.patch +Patch4005: LoongArch-Fixup-gas-check-illegal-for-b-label.patch +Patch4006: LoongArch-Fixup-check-file-for-ifunc-reloc.patch %endif + +# Patch 5000 - + +Patch5001: binutils-2.20.51.0.2-libtool-lib64.patch +Patch5002: export-demangle.h-in-devel-package.patch +# BUZ:845084 +Patch5003: binutils-2.22.52.0.4-no-config-h-check.patch +# BUG:1452111 +Patch5004: binutils-2.27-aarch64-ifunc.patch +Patch5005: Fix-gold-relocation-offset-and-adrp-signed-shife.patch + %ifarch sw_64 -Patch1006: 1006-add-sw_64-support-not-upstream-new-files.patch -Patch1007: 1007-add-sw_64-support-not-upstream-modified-files.patch +# sw_64 +Patch6001: sw_64-support-not-upstream-new-files.patch +Patch6002: sw_64-support-not-upstream-modified-files.patch %endif + Provides: bundled(libiberty) Buildroot: %(mktemp -ud %{_tmppath}/%{name}-%{version}-%{release}-XXXXXX) BuildRequires: gcc, perl, sed, coreutils, dejagnu, zlib-devel, glibc-static, sharutils, bc, libstdc++-static -BuildRequires: bison, m4, gcc-c++, gettext, flex, zlib-devel, texinfo >= 4.0, perl-podlators chrpath -Requires(post): info coreutils chkconfig -Requires(preun):info chkconfig +BuildRequires: bison, m4, gcc-c++, gettext, flex, zlib-devel, texinfo >= 4.0, perl-podlators, chrpath +Requires(post): info coreutils chkconfig +Requires(preun): info chkconfig %define _gnu %{nil} # The higher of these two numbers determines the default ld. @@ -427,7 +447,10 @@ fi %{_infodir}/bfd*info* %changelog -* Mon Dec 25 2023 luguangyang -2.37-25 +* Fri Mar 08 2024 eastb233 - 2.37-26 +- Support AArch64 SME + +* Mon Dec 25 2023 luguangyang - 2.37-25 - fix CVE-2022-38533 * Thu Sep 07 2023 yeqinglong - 2.37-24 @@ -475,16 +498,16 @@ fi * Sat Oct 08 2022 Chenxi Mao - 2.37-12 - Fix Aarch64 EFI PE section address overlap issue. -* Fri Sep 02 2022 Wei, Qiang - 2.37-11 +* Thu Sep 08 2022 Wei, Qiang - 2.37-11 - Fix man page empty issue -* Thu Sep 8 2022 yinyongkang - 2.37-10 +* Thu Sep 08 2022 yinyongkang - 2.37-10 - Type:CVE - ID:CVE-2022-38126 - SUG:NA - DESC:Fix CVE-2022-38126 -* Tue Aug 11 2022 dingguangya - 2.37-9 +* Thu Aug 11 2022 dingguangya - 2.37-9 - Type:requirements - ID:NA - SUG:NA diff --git a/1007-add-sw_64-support-not-upstream-modified-files.patch b/sw_64-support-not-upstream-modified-files.patch similarity index 100% rename from 1007-add-sw_64-support-not-upstream-modified-files.patch rename to sw_64-support-not-upstream-modified-files.patch diff --git a/1006-add-sw_64-support-not-upstream-new-files.patch b/sw_64-support-not-upstream-new-files.patch similarity index 100% rename from 1006-add-sw_64-support-not-upstream-new-files.patch rename to sw_64-support-not-upstream-new-files.patch