From 83ca02f29e3f3e36b633bfff175aba609dba3bcb Mon Sep 17 00:00:00 2001 From: Funda Wang Date: Mon, 12 May 2025 13:02:23 +0800 Subject: [PATCH] 2.44 --- ...t-opcode-of-instructions-approriatel.patch | 599 - Add-support-for-ilp32-register-alias.patch | 156 - Add-support-for-pcaddi-rd-symbol.patch | 446 - ...stcase-for-generation-of-32-64_PCREL.patch | 247 - ...r-new-assembler-option-of-mthin-add-.patch | 307 - ...ce-in-.rela.dyn-if-sec-was-discarded.patch | 102 - ...of-R_LARCH_AGLIN-caused-by-discard-s.patch | 226 - ...Loongarch-BFD-with-a-32-bit-compiler.patch | 25 - Fix-gold-linker-relocation-offset.patch | 52 - Fix-slowdown-about-partial-linking.patch | 138 - ...lex.h-when-compile-eelfxxloongarch.c.patch | 26 - Libvtv-Add-loongarch-support.patch | 36 - ...R_LARCH_-PCALA-GOT-TLS_IE-TLS_DESC-6.patch | 155 - LoongArch-Add-DT_RELR-support.patch | 641 - LoongArch-Add-DT_RELR-tests.patch | 663 - ...d-static-relocation-check-and-output.patch | 185 - ...ll36-and-tail36-pseudo-instructions-.patch | 101 - ...Arch-Add-dtpoff-calculation-function.patch | 44 - ...fNN_loongarch_mkobject-to-initialize.patch | 42 - ...s-testsuit-for-LA32-int-float-instru.patch | 654 - ...dd-gas-testsuit-for-LA32-relocations.patch | 164 - ...s-testsuit-for-LA64-int-float-instru.patch | 1237 - ...dd-gas-testsuit-for-LA64-relocations.patch | 281 - ...-gas-testsuit-for-alias-instructions.patch | 104 - ...as-testsuit-for-lbt-lvz-instructions.patch | 427 - ...s-testsuit-for-lsx-lasx-instructions.patch | 2983 --- ...gArch-Add-mignore-start-align-option.patch | 316 - ...d-more-relaxation-support-for-call36.patch | 266 - LoongArch-Add-more-relaxation-testcases.patch | 182 - ...ch-Add-new-relocation-R_LARCH_CALL36.patch | 278 - ...Add-new-relocs-and-macro-for-TLSDESC.patch | 510 - ...ch-Add-relaxation-for-R_LARCH_CALL36.patch | 684 - ...Add-support-for-OUTPUT_FORMAT-binary.patch | 124 - ...upport-for-TLS-LD-GD-DESC-relaxation.patch | 1611 -- LoongArch-Add-support-for-TLSDESC-in-ld.patch | 331 - ...-support-for-b-.L1-and-beq-t0-t1-.L1.patch | 63 - ...pport-for-the-third-expression-of-.a.patch | 445 - ...stsuit-for-DESC-and-tls-transition-a.patch | 669 - LoongArch-Add-tls-transition-support.patch | 325 - ...la.got-la.pcrel-relaxation-for-share.patch | 68 - LoongArch-Commas-inside-double-quotes.patch | 43 - LoongArch-Correct-comments.patch | 25 - ...-extra-instructions-when-TLS-type-tr.patch | 652 - ...ly-delete-relaxed-instuctions-in-fir.patch | 60 - ...e-linker-relaxation-if-set-the-addre.patch | 87 - ...scard-extra-spaces-in-objdump-output.patch | 131 - ...-Do-not-add-DF_STATIC_TLS-for-TLS-LE.patch | 27 - ...-check-R_LARCH_SOP_PUSH_ABSOLUTE-to-.patch | 55 - ...-emit-R_LARCH_RELAX-for-two-register.patch | 754 - LoongArch-Enable-gas-sort-relocs.patch | 29 - ...x-DT_RELR-and-relaxation-interaction.patch | 74 - ...Fix-a-bug-of-getting-relocation-type.patch | 27 - ...h-Fix-assertion-failure-with-DT_RELR.patch | 87 - ...d-reloc-with-mixed-visibility-ifunc-.patch | 269 - ...dwarf3-test-cases-from-XPASS-to-PASS.patch | 38 - LoongArch-Fix-gas-and-ld-test-cases.patch | 149 - ...rch-Fix-immediate-overflow-check-bug.patch | 42 - LoongArch-Fix-ld-FAIL-test-cases.patch | 91 - LoongArch-Fix-ld-no-relax-bug.patch | 56 - ...-test-failures-caused-by-using-instr.patch | 29 - ...nker-generate-PLT-entry-for-data-sym.patch | 121 - ...ongarch-elf-target-ld-testsuite-fail.patch | 206 - ...laxation-overflow-caused-by-ld-z-sep.patch | 413 - ...laxation-overflow-caused-by-section-.patch | 273 - ...me-macro-that-cannot-be-expanded-pro.patch | 390 - ...me-test-cases-for-TLS-transition-and.patch | 997 - ...me-test-failures-about-TLS-desc-and-.patch | 146 - ...e-issue-of-excessive-relocation-gene.patch | 437 - ...ong-relocation-handling-of-symbols-d.patch | 126 - ...ABI-v1.00-TLS-dynamic-relocation-gen.patch | 152 - ...R_LARCH_-32-64-_PCREL-generation-bug.patch | 81 - ...precedence-of-expression-operators-i.patch | 86 - ...relocation-for-every-reference-to-th.patch | 207 - ...AS-Add-support-for-branch-relaxation.patch | 529 - ...rch64-allows-relocations-to-use-64-b.patch | 65 - ...lign-symbol-be-in-same-section-with-.patch | 303 - ...rotected-function-symbols-local-for-.patch | 311 - ...-inconsistent-behavior-of-ld-with-un.patch | 60 - ...ify-link_info.relax_pass-from-3-to-2.patch | 43 - ...ultiple-relax_trip-in-one-relax_pass.patch | 57 - ...loc-dynamic-relocs-if-symbol-is-abso.patch | 128 - ...Arch-Optimize-the-relaxation-process.patch | 482 - ...-R_LARCH_32-from-becoming-a-runtime-.patch | 132 - ...-elf_seg_map-info-output_bfd-NULL-re.patch | 112 - ...-Remove-unused-code-in-ld-test-suite.patch | 45 - ...erflow-testcases-only-on-LoongArch-t.patch | 50 - ...ll-illegal-operand-instructions-with.patch | 381 - ...-TLS-IE-needs-only-one-dynamic-reloc.patch | 201 - ...mbol-got-type-can-only-be-obtained-a.patch | 37 - ...b-to-indent-assembly-in-TLSDESC-test.patch | 43 - LoongArch-add-.option-directive.patch | 207 - ...rch-bfd-Add-support-for-tls-le-relax.patch | 345 - ...rrect-the-name-of-R_LARCH_SOP_POP_32.patch | 26 - ...rch-bfd-Fix-some-bugs-of-howto-table.patch | 52 - ...h-binutils-compatible-with-older-gcc.patch | 26 - ...ternal-error-when-as-handling-unsupp.patch | 78 - ...Arch-gas-Add-support-for-s9-register.patch | 98 - ...rch-gas-Add-support-for-tls-le-relax.patch | 166 - ...s-Adjust-DWARF-CIE-alignment-factors.patch | 49 - ...ch-gas-Don-t-define-LoongArch-.align.patch | 82 - LoongArch-gas-Fix-make-check-gas-crash.patch | 26 - ...x-the-types-of-symbols-referred-with.patch | 84 - ...nore-.align-if-it-is-at-the-start-of.patch | 308 - ...mplify-relocations-in-sections-witho.patch | 68 - ...art-a-new-frag-after-instructions-th.patch | 143 - ...y-to-avoid-R_LARCH_ALIGN-associate-w.patch | 166 - ...ement-count_-leading-trailing-_zeros.patch | 46 - ...include-Add-support-for-tls-le-relax.patch | 43 - ...-support-for-TLS-LE-symbol-with-adde.patch | 105 - ...Arch-ld-Add-support-for-tls-le-relax.patch | 410 - ...djusted-some-code-order-in-relax.exp.patch | 340 - ...-other-pop-relocs-overflow-check-and.patch | 787 - ...e-.got-.got.plt-before-.data-and-pro.patch | 96 - ...ort-an-error-when-seeing-an-unrecogn.patch | 40 - ...plify-inserting-IRELATIVE-relocation.patch | 184 - ...opcodes-Add-support-for-tls-le-relax.patch | 29 - ...elf-d-RELASZ-excludes-.rela.plt-size.patch | 25 - ...rch-loongson2f-to-loongson-2f-3-test.patch | 25 - ...CFA_advance_loc4-is-in-the-same-frag.patch | 37 - ...y-test-because-of-readelf-not-update.patch | 201 - Not-append-rela-for-absolute-symbol.patch | 133 - ...S-ld-NEWS-Announce-LoongArch-changes.patch | 167 - PPC-gas-supported-c2000.patch | 921 - ...-support-for-b-.L1-and-beq-t0-t1-.L1.patch | 62 - ...s-Adjust-DWARF-CIE-alignment-factors.patch | 94 - Sw64-binutils-Add-Sw64-support.patch | 20973 ---------------- ...to-replace-a-pair-of-ADD32-64-and-SU.patch | 85 - X86-Change-fpic-to-fPIC-in-PICFLAG.patch | 20 +- ...tomic-instructions-in-LoongArch-v1.1.patch | 199 - ...ated-reciprocal-instructions-in-Loon.patch | 128 - ...ion-for-generate-R_LARCH_32-64_PCREL.patch | 132 - ...l-error-when-immediate-value-of-relo.patch | 140 - ...flow-in-loongarch_elf_rtype_to_howto.patch | 110 - backport-CVE-2025-0840.patch | 54 - ...verflow-printing-core_file_failing_c.patch | 118 - ...r-overflow-printing-core_file_failin.patch | 220 - ...ANSSON_LIBS-from-ld_new_DEPENDENCIES.patch | 47 - binutils-BPF-reloc-4.patch | 38 - binutils-special-sections-in-groups.patch | 27 - ...1.tar.xz => binutils-with-gold-2.44.tar.xz | 4 +- binutils.spec | 189 +- ...S-Announce-LoongArch-changes-in-2.43.patch | 126 - loongarch-index-shadows-global.patch | 31 - loongarch-ld-testsuite-xpasses.patch | 112 - ...l-segmentation-fault-when-displaying.patch | 71 - remove-file-produced-by-bison.patch | 1920 -- replace-space-with-tab.patch | 500 - 147 files changed, 23 insertions(+), 56142 deletions(-) delete mode 100644 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delete mode 100644 LoongArch-fix-internal-error-when-as-handling-unsupp.patch delete mode 100644 LoongArch-gas-Add-support-for-s9-register.patch delete mode 100644 LoongArch-gas-Add-support-for-tls-le-relax.patch delete mode 100644 LoongArch-gas-Adjust-DWARF-CIE-alignment-factors.patch delete mode 100644 LoongArch-gas-Don-t-define-LoongArch-.align.patch delete mode 100644 LoongArch-gas-Fix-make-check-gas-crash.patch delete mode 100644 LoongArch-gas-Fix-the-types-of-symbols-referred-with.patch delete mode 100644 LoongArch-gas-Ignore-.align-if-it-is-at-the-start-of.patch delete mode 100644 LoongArch-gas-Simplify-relocations-in-sections-witho.patch delete mode 100644 LoongArch-gas-Start-a-new-frag-after-instructions-th.patch delete mode 100644 LoongArch-gas-Try-to-avoid-R_LARCH_ALIGN-associate-w.patch delete mode 100644 LoongArch-implement-count_-leading-trailing-_zeros.patch delete mode 100644 LoongArch-include-Add-support-for-tls-le-relax.patch delete mode 100644 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delete mode 100644 backport-ld-Remove-JANSSON_LIBS-from-ld_new_DEPENDENCIES.patch delete mode 100644 binutils-BPF-reloc-4.patch delete mode 100644 binutils-special-sections-in-groups.patch rename binutils-2.41.tar.xz => binutils-with-gold-2.44.tar.xz (32%) delete mode 100644 gas-NEWS-ld-NEWS-Announce-LoongArch-changes-in-2.43.patch delete mode 100644 loongarch-index-shadows-global.patch delete mode 100644 loongarch-ld-testsuite-xpasses.patch delete mode 100644 nm-Avoid-potential-segmentation-fault-when-displaying.patch delete mode 100644 remove-file-produced-by-bison.patch delete mode 100644 replace-space-with-tab.patch diff --git a/Add-macros-to-get-opcode-of-instructions-approriatel.patch b/Add-macros-to-get-opcode-of-instructions-approriatel.patch deleted file mode 100644 index 3c05405..0000000 --- a/Add-macros-to-get-opcode-of-instructions-approriatel.patch +++ /dev/null @@ -1,599 +0,0 @@ -From 52fc0adff846e7fb01fd2995b5520e4194287489 Mon Sep 17 00:00:00 2001 -From: Xin Wang -Date: Fri, 6 Sep 2024 08:54:07 +0800 -Subject: [PATCH 112/123] Add macros to get opcode of instructions approriately - -LoongArch: Add macros to get opcode and register of instructions appropriately - -Currently, we get opcode of an instruction by manipulate the binary with -it's mask, it's a bit of a pain. Now a macro is defined to do this and a -macro to get the RD and RJ registers which is applicable to most instructions -of LoongArch are added. ---- - bfd/elfnn-loongarch.c | 62 +++--- - gas/config/tc-loongarch.c | 36 +-- - gas/testsuite/gas/loongarch/illegal-operand.l | 208 +++++++++--------- - include/opcode/loongarch.h | 70 +++++- - 4 files changed, 216 insertions(+), 160 deletions(-) - -diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c -index 30ac5555..770483cd 100644 ---- a/bfd/elfnn-loongarch.c -+++ b/bfd/elfnn-loongarch.c -@@ -4064,7 +4064,7 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, - /* For 2G jump, generate pcalau12i, jirl. */ - /* If use jirl, turns to R_LARCH_B16. */ - uint32_t insn = bfd_get (32, input_bfd, contents + rel->r_offset); -- if ((insn & 0x4c000000) == 0x4c000000) -+ if (LARCH_INSN_JIRL(insn)) - { - relocation &= 0xfff; - /* Signed extend. */ -@@ -4704,7 +4704,7 @@ loongarch_tls_perform_trans (bfd *abfd, asection *sec, - pcalalau12i $a0,%desc_pc_hi20(var) => - lu12i.w $a0,%le_hi20(var) - */ -- bfd_put (32, abfd, LARCH_LU12I_W | LARCH_RD_A0, -+ bfd_put (32, abfd, LARCH_OP_LU12I_W | LARCH_RD_A0, - contents + rel->r_offset); - rel->r_info = ELFNN_R_INFO (r_symndx, R_LARCH_TLS_LE_HI20); - } -@@ -4725,8 +4725,8 @@ loongarch_tls_perform_trans (bfd *abfd, asection *sec, - addi.d $a0,$a0,%desc_pc_lo12(var) => - ori $a0,$a0,le_lo12(var) - */ -- insn = LARCH_ORI | LARCH_RD_RJ_A0; -- bfd_put (32, abfd, LARCH_ORI | LARCH_RD_RJ_A0, -+ insn = LARCH_OP_ORI | LARCH_RD_RJ_A0; -+ bfd_put (32, abfd, LARCH_OP_ORI | LARCH_RD_RJ_A0, - contents + rel->r_offset); - rel->r_info = ELFNN_R_INFO (r_symndx, R_LARCH_TLS_LE_LO12); - } -@@ -4736,7 +4736,7 @@ loongarch_tls_perform_trans (bfd *abfd, asection *sec, - addi.d $a0,$a0,%desc_pc_lo12(var) => - ld.d $a0,$a0,%ie_pc_lo12(var) - */ -- bfd_put (32, abfd, LARCH_LD_D | LARCH_RD_RJ_A0, -+ bfd_put (32, abfd, LARCH_OP_LD_D | LARCH_RD_RJ_A0, - contents + rel->r_offset); - rel->r_info = ELFNN_R_INFO (r_symndx, R_LARCH_TLS_IE_PC_LO12); - } -@@ -4763,7 +4763,7 @@ loongarch_tls_perform_trans (bfd *abfd, asection *sec, - lu12i.w $rd,%le_hi20(var) - */ - insn = bfd_getl32 (contents + rel->r_offset); -- bfd_put (32, abfd, LARCH_LU12I_W | (insn & 0x1f), -+ bfd_put (32, abfd, LARCH_OP_LU12I_W | LARCH_GET_RD(insn), - contents + rel->r_offset); - rel->r_info = ELFNN_R_INFO (r_symndx, R_LARCH_TLS_LE_HI20); - } -@@ -4777,7 +4777,7 @@ loongarch_tls_perform_trans (bfd *abfd, asection *sec, - ori $rd,$rj,le_lo12(var) - */ - insn = bfd_getl32 (contents + rel->r_offset); -- bfd_put (32, abfd, LARCH_ORI | (insn & 0x3ff), -+ bfd_put (32, abfd, LARCH_OP_ORI | (insn & 0x3ff), - contents + rel->r_offset); - rel->r_info = ELFNN_R_INFO (r_symndx, R_LARCH_TLS_LE_LO12); - } -@@ -4875,11 +4875,11 @@ loongarch_relax_tls_le (bfd *abfd, asection *sec, - /* Change rj to $tp. */ - insn_rj = 0x2 << 5; - /* Get rd register. */ -- insn_rd = insn & 0x1f; -+ insn_rd = LARCH_GET_RD(insn); - /* Write symbol offset. */ - symval <<= 10; - /* Writes the modified instruction. */ -- insn = insn & 0xffc00000; -+ insn = insn & LARCH_MK_ADDI_D; - insn = insn | symval | insn_rj | insn_rd; - bfd_put (32, abfd, insn, contents + rel->r_offset); - } -@@ -4894,7 +4894,7 @@ loongarch_relax_tls_le (bfd *abfd, asection *sec, - break; - - case R_LARCH_TLS_LE_LO12: -- bfd_put (32, abfd, LARCH_ORI | (insn & 0x1f), -+ bfd_put (32, abfd, LARCH_OP_ORI | LARCH_GET_RD(insn), - contents + rel->r_offset); - break; - -@@ -4940,7 +4940,7 @@ loongarch_relax_pcala_addi (bfd *abfd, asection *sec, asection *sym_sec, - Elf_Internal_Rela *rel_lo = rel_hi + 2; - uint32_t pca = bfd_get (32, abfd, contents + rel_hi->r_offset); - uint32_t add = bfd_get (32, abfd, contents + rel_lo->r_offset); -- uint32_t rd = pca & 0x1f; -+ uint32_t rd = LARCH_GET_RD(pca); - - /* This section's output_offset need to subtract the bytes of instructions - relaxed by the previous sections, so it needs to be updated beforehand. -@@ -4961,18 +4961,17 @@ loongarch_relax_pcala_addi (bfd *abfd, asection *sec, asection *sym_sec, - else if (symval < pc) - pc += (max_alignment > 4 ? max_alignment : 0); - -- const uint32_t addi_d = 0x02c00000; -- const uint32_t pcaddi = 0x18000000; -+ const uint32_t pcaddi = LARCH_OP_PCADDI; - - /* Is pcalau12i + addi.d insns? */ - if ((ELFNN_R_TYPE (rel_lo->r_info) != R_LARCH_PCALA_LO12) - || (ELFNN_R_TYPE ((rel_lo + 1)->r_info) != R_LARCH_RELAX) - || (ELFNN_R_TYPE ((rel_hi + 1)->r_info) != R_LARCH_RELAX) - || (rel_hi->r_offset + 4 != rel_lo->r_offset) -- || ((add & addi_d) != addi_d) -+ || !LARCH_INSN_ADDI_D(add) - /* Is pcalau12i $rd + addi.d $rd,$rd? */ -- || ((add & 0x1f) != rd) -- || (((add >> 5) & 0x1f) != rd) -+ || (LARCH_GET_RD(add) != rd) -+ || (LARCH_GET_RJ(add) != rd) - /* Can be relaxed to pcaddi? */ - || (symval & 0x3) /* 4 bytes align. */ - || ((bfd_signed_vma)(symval - pc) < (bfd_signed_vma)(int32_t)0xffe00000) -@@ -5005,7 +5004,7 @@ loongarch_relax_call36 (bfd *abfd, asection *sec, asection *sym_sec, - { - bfd_byte *contents = elf_section_data (sec)->this_hdr.contents; - uint32_t jirl = bfd_get (32, abfd, contents + rel->r_offset + 4); -- uint32_t rd = jirl & 0x1f; -+ uint32_t rd = LARCH_GET_RD(jirl); - - /* This section's output_offset need to subtract the bytes of instructions - relaxed by the previous sections, so it needs to be updated beforehand. -@@ -5026,11 +5025,10 @@ loongarch_relax_call36 (bfd *abfd, asection *sec, asection *sym_sec, - else if (symval < pc) - pc += (max_alignment > 4 ? max_alignment : 0); - -- const uint32_t jirl_opcode = 0x4c000000; - - /* Is pcalau12i + addi.d insns? */ - if ((ELFNN_R_TYPE ((rel + 1)->r_info) != R_LARCH_RELAX) -- || ((jirl & jirl_opcode) != jirl_opcode) -+ || !LARCH_INSN_JIRL(jirl) - || ((bfd_signed_vma)(symval - pc) < (bfd_signed_vma)(int32_t)0xf8000000) - || ((bfd_signed_vma)(symval - pc) > (bfd_signed_vma)(int32_t)0x7fffffc)) - return false; -@@ -5038,8 +5036,8 @@ loongarch_relax_call36 (bfd *abfd, asection *sec, asection *sym_sec, - /* Continue next relax trip. */ - *again = true; - -- const uint32_t bl = 0x54000000; -- const uint32_t b = 0x50000000; -+ const uint32_t bl = LARCH_OP_BL; -+ const uint32_t b = LARCH_OP_B; - - if (rd) - bfd_put (32, abfd, bl, contents + rel->r_offset); -@@ -5062,17 +5060,16 @@ loongarch_relax_pcala_ld (bfd *abfd, asection *sec, - Elf_Internal_Rela *rel_lo = rel_hi + 2; - uint32_t pca = bfd_get (32, abfd, contents + rel_hi->r_offset); - uint32_t ld = bfd_get (32, abfd, contents + rel_lo->r_offset); -- uint32_t rd = pca & 0x1f; -- const uint32_t ld_d = 0x28c00000; -- uint32_t addi_d = 0x02c00000; -+ uint32_t rd = LARCH_GET_RD(pca); -+ uint32_t addi_d = LARCH_OP_ADDI_D; - - if ((ELFNN_R_TYPE (rel_lo->r_info) != R_LARCH_GOT_PC_LO12) - || (ELFNN_R_TYPE ((rel_lo + 1)->r_info) != R_LARCH_RELAX) - || (ELFNN_R_TYPE ((rel_hi + 1)->r_info) != R_LARCH_RELAX) - || (rel_hi->r_offset + 4 != rel_lo->r_offset) -- || ((ld & 0x1f) != rd) -- || (((ld >> 5) & 0x1f) != rd) -- || ((ld & ld_d) != ld_d)) -+ || (LARCH_GET_RD(ld) != rd) -+ || (LARCH_GET_RJ(ld) != rd) -+ || !LARCH_INSN_LD_D(ld)) - return false; - - addi_d = addi_d | (rd << 5) | rd; -@@ -5165,7 +5162,7 @@ loongarch_relax_tls_ld_gd_desc (bfd *abfd, asection *sec, asection *sym_sec, - Elf_Internal_Rela *rel_lo = rel_hi + 2; - uint32_t pca = bfd_get (32, abfd, contents + rel_hi->r_offset); - uint32_t add = bfd_get (32, abfd, contents + rel_lo->r_offset); -- uint32_t rd = pca & 0x1f; -+ uint32_t rd = LARCH_GET_RD(pca); - - /* This section's output_offset need to subtract the bytes of instructions - relaxed by the previous sections, so it needs to be updated beforehand. -@@ -5186,8 +5183,7 @@ loongarch_relax_tls_ld_gd_desc (bfd *abfd, asection *sec, asection *sym_sec, - else if (symval < pc) - pc += (max_alignment > 4 ? max_alignment : 0); - -- const uint32_t addi_d = 0x02c00000; -- const uint32_t pcaddi = 0x18000000; -+ const uint32_t pcaddi = LARCH_OP_PCADDI; - - /* Is pcalau12i + addi.d insns? */ - if ((ELFNN_R_TYPE (rel_lo->r_info) != R_LARCH_GOT_PC_LO12 -@@ -5195,10 +5191,10 @@ loongarch_relax_tls_ld_gd_desc (bfd *abfd, asection *sec, asection *sym_sec, - || (ELFNN_R_TYPE ((rel_lo + 1)->r_info) != R_LARCH_RELAX) - || (ELFNN_R_TYPE ((rel_hi + 1)->r_info) != R_LARCH_RELAX) - || (rel_hi->r_offset + 4 != rel_lo->r_offset) -- || ((add & addi_d) != addi_d) -+ || !LARCH_INSN_ADDI_D(add) - /* Is pcalau12i $rd + addi.d $rd,$rd? */ -- || ((add & 0x1f) != rd) -- || (((add >> 5) & 0x1f) != rd) -+ || (LARCH_GET_RD(add) != rd) -+ || (LARCH_GET_RJ(add) != rd) - /* Can be relaxed to pcaddi? */ - || (symval & 0x3) /* 4 bytes align. */ - || ((bfd_signed_vma)(symval - pc) < (bfd_signed_vma)(int32_t)0xffe00000) -diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c -index 16355cac..046e198f 100644 ---- a/gas/config/tc-loongarch.c -+++ b/gas/config/tc-loongarch.c -@@ -1078,34 +1078,34 @@ check_this_insn_before_appending (struct loongarch_cl_insn *ip) - ip->reloc_info[ip->reloc_num].value = const_0; - ip->reloc_num++; - } -- else if (ip->insn->mask == 0xffff8000 -- /* amcas.b rd, rk, rj */ -- && ((ip->insn_bin & 0xfff80000) == 0x38580000 -- /* amswap.w rd, rk, rj */ -- || (ip->insn_bin & 0xfff00000) == 0x38600000 -- /* ammax_db.wu rd, rk, rj */ -- || (ip->insn_bin & 0xffff0000) == 0x38700000 -- /* ammin_db.wu rd, rk, rj */ -- || (ip->insn_bin & 0xffff0000) == 0x38710000)) -+ /* check all atomic memory insns */ -+ else if (ip->insn->mask == LARCH_MK_ATOMIC_MEM -+ && LARCH_INSN_ATOMIC_MEM(ip->insn_bin)) - { - /* For AMO insn amswap.[wd], amadd.[wd], etc. */ - if (ip->args[0] != 0 - && (ip->args[0] == ip->args[1] || ip->args[0] == ip->args[2])) -- as_bad (_("automic memory operations insns require rd != rj" -+ as_bad (_("atomic memory operations insns require rd != rj" - " && rd != rk when rd isn't r0")); - } -- else if ((ip->insn->mask == 0xffe08000 -- /* bstrins.w rd, rj, msbw, lsbw */ -- && (ip->insn_bin & 0xffe00000) == 0x00600000) -- || (ip->insn->mask == 0xffc00000 -- /* bstrins.d rd, rj, msbd, lsbd */ -- && (ip->insn_bin & 0xff800000) == 0x00800000)) -+ else if ((ip->insn->mask == LARCH_MK_BSTRINS_W -+ /* bstr(ins|pick).w rd, rj, msbw, lsbw */ -+ && (LARCH_INSN_BSTRINS_W(ip->insn_bin) -+ || LARCH_INSN_BSTRPICK_W(ip->insn_bin))) -+ || (ip->insn->mask == LARCH_MK_BSTRINS_D -+ /* bstr(ins|pick).d rd, rj, msbd, lsbd */ -+ && (LARCH_INSN_BSTRINS_D(ip->insn_bin) -+ || LARCH_INSN_BSTRPICK_D(ip->insn_bin)))) - { - /* For bstr(ins|pick).[wd]. */ - if (ip->args[2] < ip->args[3]) - as_bad (_("bstr(ins|pick).[wd] require msbd >= lsbd")); - } -- else if (ip->insn->mask != 0 && (ip->insn_bin & 0xfe0003c0) == 0x04000000 -+ else if (ip->insn->mask != 0 -+ && (LARCH_INSN_CSRXCHG(ip->insn_bin) -+ || LARCH_INSN_GCSRXCHG(ip->insn_bin)) -+ && (LARCH_GET_RJ(ip->insn_bin) == 0 -+ || LARCH_GET_RJ(ip->insn_bin) == 1) - /* csrxchg rd, rj, csr_num */ - && (strcmp ("csrxchg", ip->name) == 0 - || strcmp ("gcsrxchg", ip->name) == 0)) -@@ -2207,7 +2207,7 @@ loongarch_convert_frag_branch (fragS *fragp) - case RELAX_BRANCH_26: - insn = bfd_getl32 (buf); - /* Invert the branch condition. */ -- if (LARCH_FLOAT_BRANCH == (insn & LARCH_BRANCH_OPCODE_MASK)) -+ if (LARCH_INSN_FLOAT_BRANCH(insn)) - insn ^= LARCH_FLOAT_BRANCH_INVERT_BIT; - else - insn ^= LARCH_BRANCH_INVERT_BIT; -diff --git a/gas/testsuite/gas/loongarch/illegal-operand.l b/gas/testsuite/gas/loongarch/illegal-operand.l -index dddc6d6f..33e859c7 100644 ---- a/gas/testsuite/gas/loongarch/illegal-operand.l -+++ b/gas/testsuite/gas/loongarch/illegal-operand.l -@@ -1,108 +1,108 @@ - .*: Assembler messages: --.*:2: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:3: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:4: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:5: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:6: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:7: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:8: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:9: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:10: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:11: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:12: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:13: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:14: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:15: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:16: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:17: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:18: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:19: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:20: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:21: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:22: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:23: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:24: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:25: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:26: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:27: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:28: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:29: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:30: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:31: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:32: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:33: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:34: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:35: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:36: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:37: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:38: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:39: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:40: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:41: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:42: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:43: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:44: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:45: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:46: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:47: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:48: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:49: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:50: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:51: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:52: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:53: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:54: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:55: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:56: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:57: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:58: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:59: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:60: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:61: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:62: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:63: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:64: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:65: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:66: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:67: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:68: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:69: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:70: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:71: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:72: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:73: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:74: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:75: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:76: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:77: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:78: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:79: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:80: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:81: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:82: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:83: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:84: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:85: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:86: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:87: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:88: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:89: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:90: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:91: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:92: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:93: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:94: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:95: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:96: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:97: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:98: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:99: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:100: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:101: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:102: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:103: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:104: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 --.*:105: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:2: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:3: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:4: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:5: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:6: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:7: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:8: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:9: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:10: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:11: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:12: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:13: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:14: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:15: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:16: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:17: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:18: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:19: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:20: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:21: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:22: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:23: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:24: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:25: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:26: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:27: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:28: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:29: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:30: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:31: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:32: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:33: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:34: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:35: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:36: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:37: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:38: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:39: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:40: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:41: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:42: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:43: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:44: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:45: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:46: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:47: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:48: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:49: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:50: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:51: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:52: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:53: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:54: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:55: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:56: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:57: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:58: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:59: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:60: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:61: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:62: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:63: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:64: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:65: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:66: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:67: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:68: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:69: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:70: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:71: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:72: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:73: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:74: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:75: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:76: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:77: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:78: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:79: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:80: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:81: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:82: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:83: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:84: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:85: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:86: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:87: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:88: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:89: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:90: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:91: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:92: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:93: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:94: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:95: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:96: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:97: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:98: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:99: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:100: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:101: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:102: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:103: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:104: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:105: Error: atomic memory operations insns require rd != rj && rd != rk when rd isn't r0 - .*:108: Error: bstr\(ins\|pick\)\.\[wd\] require msbd >= lsbd - .*:109: Error: bstr\(ins\|pick\)\.\[wd\] require msbd >= lsbd - .*:110: Error: bstr\(ins\|pick\)\.\[wd\] require msbd >= lsbd -diff --git a/include/opcode/loongarch.h b/include/opcode/loongarch.h -index 024ba99c..1dbc16fc 100644 ---- a/include/opcode/loongarch.h -+++ b/include/opcode/loongarch.h -@@ -31,22 +31,82 @@ extern "C" - #define LARCH_NOP 0x03400000 - #define LARCH_B 0x50000000 - /* BCEQZ/BCNEZ. */ -- #define LARCH_FLOAT_BRANCH 0x48000000 -- #define LARCH_BRANCH_OPCODE_MASK 0xfc000000 - #define LARCH_BRANCH_INVERT_BIT 0x04000000 - #define LARCH_FLOAT_BRANCH_INVERT_BIT 0x00000100 - -+ #define LARCH_MK_ADDI_D 0xffc00000 -+ #define LARCH_OP_ADDI_D 0x02c00000 -+ #define LARCH_MK_PCADDI 0xfe000000 -+ #define LARCH_OP_PCADDI 0x18000000 -+ #define LARCH_MK_B 0xfc000000 -+ #define LARCH_OP_B 0x50000000 -+ #define LARCH_MK_BL 0xfc000000 -+ #define LARCH_OP_BL 0x54000000 -+ #define LARCH_MK_ORI 0xffc00000 -+ #define LARCH_OP_ORI 0x03800000 -+ #define LARCH_MK_LU12I_W 0xfe000000 -+ #define LARCH_OP_LU12I_W 0x14000000 -+ #define LARCH_MK_LD_D 0xffc00000 -+ #define LARCH_OP_LD_D 0x28c00000 -+ #define LARCH_MK_JIRL 0xfc000000 -+ #define LARCH_OP_JIRL 0x4c000000 -+ #define LARCH_MK_BCEQZ 0xfc000300 -+ #define LARCH_OP_BCEQZ 0x48000000 -+ #define LARCH_MK_BCNEZ 0xfc000300 -+ #define LARCH_OP_BCNEZ 0x48000100 -+ #define LARCH_MK_ATOMIC_MEM 0xffff8000 -+ #define LARCH_MK_BSTRINS_W 0xffe08000 -+ #define LARCH_OP_BSTRINS_W 0x00600000 -+ #define LARCH_MK_BSTRPICK_W 0xffe08000 -+ #define LARCH_OP_BSTRPICK_W 0x00608000 -+ #define LARCH_MK_BSTRINS_D 0xffc00000 -+ #define LARCH_OP_BSTRINS_D 0x00800000 -+ #define LARCH_MK_BSTRPICK_D 0xffc00000 -+ #define LARCH_OP_BSTRPICK_D 0x00c00000 -+ #define LARCH_MK_CSRRD 0xff0003e0 -+ #define LARCH_OP_CSRRD 0x04000000 -+ #define LARCH_MK_CSRWR 0xff0003e0 -+ #define LARCH_OP_CSRWR 0x04000020 -+ #define LARCH_MK_CSRXCHG 0xff000000 -+ #define LARCH_OP_CSRXCHG 0x04000000 -+ #define LARCH_MK_GCSRXCHG 0xff000000 -+ #define LARCH_OP_GCSRXCHG 0x05000000 -+ -+ #define LARCH_INSN_OPS(insn, op) ((insn & LARCH_MK_##op) == LARCH_OP_##op) -+ #define LARCH_INSN_ADDI_D(insn) LARCH_INSN_OPS((insn), ADDI_D) -+ #define LARCH_INSN_PCADDI(insn) LARCH_INSN_OPS((insn), PCADDI) -+ #define LARCH_INSN_B(insn) LARCH_INSN_OPS((insn), B) -+ #define LARCH_INSN_BL(insn) LARCH_INSN_OPS((insn), BL) -+ #define LARCH_INSN_ORI(insn) LARCH_INSN_OPS((insn), ORI) -+ #define LARCH_INSN_LU12I_W(insn) LARCH_INSN_OPS((insn), LU12I_W) -+ #define LARCH_INSN_LD_D(insn) LARCH_INSN_OPS((insn), LD_D) -+ #define LARCH_INSN_JIRL(insn) LARCH_INSN_OPS((insn), JIRL) -+ #define LARCH_INSN_BCEQZ(insn) LARCH_INSN_OPS((insn), BCEQZ) -+ #define LARCH_INSN_BCNEZ(insn) LARCH_INSN_OPS((insn), BCNEZ) -+ #define LARCH_INSN_FLOAT_BRANCH(insn) (LARCH_INSN_BCEQZ(insn) || LARCH_INSN_BCNEZ(insn)) -+ #define LARCH_INSN_BSTRINS_W(insn) LARCH_INSN_OPS((insn), BSTRINS_W) -+ #define LARCH_INSN_BSTRPICK_W(insn) LARCH_INSN_OPS((insn), BSTRPICK_W) -+ #define LARCH_INSN_BSTRINS_D(insn) LARCH_INSN_OPS((insn), BSTRINS_D) -+ #define LARCH_INSN_BSTRPICK_D(insn) LARCH_INSN_OPS((insn), BSTRPICK_D) -+ #define LARCH_INSN_CSRXCHG(insn) LARCH_INSN_OPS((insn), CSRXCHG) -+ #define LARCH_INSN_GCSRXCHG(insn) LARCH_INSN_OPS((insn), GCSRXCHG) -+ -+ #define LARCH_INSN_ATOMIC_MEM(insn) \ -+ ((insn & 0xfff80000) == 0x38580000 \ -+ || (insn & 0xfff00000) == 0x38600000 \ -+ || (insn & 0xffff0000) == 0x38700000 \ -+ || (insn & 0xffff0000) == 0x38710000) -+ - #define ENCODE_BRANCH16_IMM(x) (((x) >> 2) << 10) - - #define OUT_OF_RANGE(value, bits, align) \ - ((value) < (-(1 << ((bits) - 1) << align)) \ - || (value) > ((((1 << ((bits) - 1)) - 1) << align))) - -- #define LARCH_LU12I_W 0x14000000 -- #define LARCH_ORI 0x03800000 -- #define LARCH_LD_D 0x28c00000 - #define LARCH_RD_A0 0x04 - #define LARCH_RD_RJ_A0 0x084 -+ #define LARCH_GET_RD(insn) (insn & 0x1f) -+ #define LARCH_GET_RJ(insn) ((insn >> 5) & 0x1f) - - typedef uint32_t insn_t; - --- -2.33.0 - diff --git a/Add-support-for-ilp32-register-alias.patch b/Add-support-for-ilp32-register-alias.patch deleted file mode 100644 index 6b3c9fe..0000000 --- a/Add-support-for-ilp32-register-alias.patch +++ /dev/null @@ -1,156 +0,0 @@ -From 6a9c6951245b9b344ebb7ababd1e9f8192d8eccd Mon Sep 17 00:00:00 2001 -From: Lulu Cai -Date: Mon, 30 Oct 2023 17:07:08 +0800 -Subject: [PATCH 017/123] Add support for ilp32 register alias. - ---- - gas/config/tc-loongarch.c | 41 +++++++++++++++++--------------------- - include/opcode/loongarch.h | 8 ++++---- - opcodes/loongarch-dis.c | 4 ++-- - opcodes/loongarch-opc.c | 8 ++++---- - 4 files changed, 28 insertions(+), 33 deletions(-) - -diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c -index 49c70bf1..59232832 100644 ---- a/gas/config/tc-loongarch.c -+++ b/gas/config/tc-loongarch.c -@@ -303,6 +303,15 @@ loongarch_after_parse_args () - for (i = 0; i < ARRAY_SIZE (loongarch_r_normal_name); i++) - str_hash_insert (r_htab, loongarch_r_normal_name[i], (void *) (i + 1), 0); - -+ /* Init ilp32/lp64 registers alias. */ -+ r_abi_names = loongarch_r_alias; -+ for (i = 0; i < ARRAY_SIZE (loongarch_r_alias); i++) -+ str_hash_insert (r_htab, loongarch_r_alias[i], (void *) (i + 1), -+ 0); -+ for (i = 0; i < ARRAY_SIZE (loongarch_r_alias_deprecated); i++) -+ str_hash_insert (r_deprecated_htab, loongarch_r_alias_deprecated[i], -+ (void *) (i + 1), 0); -+ - if (!cr_htab) - cr_htab = str_htab_create (), str_hash_insert (cr_htab, "", 0, 0); - -@@ -323,6 +332,15 @@ loongarch_after_parse_args () - str_hash_insert (f_htab, loongarch_f_normal_name[i], (void *) (i + 1), - 0); - -+ /* Init float-ilp32/lp64 registers alias. */ -+ f_abi_names = loongarch_f_alias; -+ for (i = 0; i < ARRAY_SIZE (loongarch_f_alias); i++) -+ str_hash_insert (f_htab, loongarch_f_alias[i], -+ (void *) (i + 1), 0); -+ for (i = 0; i < ARRAY_SIZE (loongarch_f_alias_deprecated); i++) -+ str_hash_insert (f_deprecated_htab, loongarch_f_alias_deprecated[i], -+ (void *) (i + 1), 0); -+ - if (!fc_htab) - fc_htab = str_htab_create (), str_hash_insert (fc_htab, "", 0, 0); - -@@ -366,29 +384,6 @@ loongarch_after_parse_args () - 0); - } - -- /* Init lp64 registers alias. */ -- if (LARCH_opts.ase_lp64) -- { -- r_abi_names = loongarch_r_lp64_name; -- for (i = 0; i < ARRAY_SIZE (loongarch_r_lp64_name); i++) -- str_hash_insert (r_htab, loongarch_r_lp64_name[i], (void *) (i + 1), -- 0); -- for (i = 0; i < ARRAY_SIZE (loongarch_r_lp64_name_deprecated); i++) -- str_hash_insert (r_deprecated_htab, loongarch_r_lp64_name_deprecated[i], -- (void *) (i + 1), 0); -- } -- -- /* Init float-lp64 registers alias */ -- if ((LARCH_opts.ase_sf || LARCH_opts.ase_df) && LARCH_opts.ase_lp64) -- { -- f_abi_names = loongarch_f_lp64_name; -- for (i = 0; i < ARRAY_SIZE (loongarch_f_lp64_name); i++) -- str_hash_insert (f_htab, loongarch_f_lp64_name[i], -- (void *) (i + 1), 0); -- for (i = 0; i < ARRAY_SIZE (loongarch_f_lp64_name_deprecated); i++) -- str_hash_insert (f_deprecated_htab, loongarch_f_lp64_name_deprecated[i], -- (void *) (i + 1), 0); -- } - } - - const char * -diff --git a/include/opcode/loongarch.h b/include/opcode/loongarch.h -index f358ff42..da936f79 100644 ---- a/include/opcode/loongarch.h -+++ b/include/opcode/loongarch.h -@@ -189,11 +189,11 @@ dec2 : [1-9][0-9]? - extern void loongarch_eliminate_adjacent_repeat_char (char *dest, char c); - - extern const char *const loongarch_r_normal_name[32]; -- extern const char *const loongarch_r_lp64_name[32]; -- extern const char *const loongarch_r_lp64_name_deprecated[32]; -+ extern const char *const loongarch_r_alias[32]; -+ extern const char *const loongarch_r_alias_deprecated[32]; - extern const char *const loongarch_f_normal_name[32]; -- extern const char *const loongarch_f_lp64_name[32]; -- extern const char *const loongarch_f_lp64_name_deprecated[32]; -+ extern const char *const loongarch_f_alias[32]; -+ extern const char *const loongarch_f_alias_deprecated[32]; - extern const char *const loongarch_fc_normal_name[4]; - extern const char *const loongarch_fc_numeric_name[4]; - extern const char *const loongarch_c_normal_name[8]; -diff --git a/opcodes/loongarch-dis.c b/opcodes/loongarch-dis.c -index 1e711f27..969ea28f 100644 ---- a/opcodes/loongarch-dis.c -+++ b/opcodes/loongarch-dis.c -@@ -82,8 +82,8 @@ set_default_loongarch_dis_options (void) - LARCH_opts.ase_lvz = 1; - LARCH_opts.ase_lbt = 1; - -- loongarch_r_disname = loongarch_r_lp64_name; -- loongarch_f_disname = loongarch_f_lp64_name; -+ loongarch_r_disname = loongarch_r_alias; -+ loongarch_f_disname = loongarch_f_alias; - loongarch_fc_disname = loongarch_fc_normal_name; - loongarch_c_disname = loongarch_c_normal_name; - loongarch_cr_disname = loongarch_cr_normal_name; -diff --git a/opcodes/loongarch-opc.c b/opcodes/loongarch-opc.c -index 5cd1411a..15c7da63 100644 ---- a/opcodes/loongarch-opc.c -+++ b/opcodes/loongarch-opc.c -@@ -41,7 +41,7 @@ const char *const loongarch_r_normal_name[32] = - "$r24", "$r25", "$r26", "$r27", "$r28", "$r29", "$r30", "$r31", - }; - --const char *const loongarch_r_lp64_name[32] = -+const char *const loongarch_r_alias[32] = - { - "$zero", "$ra", "$tp", "$sp", "$a0", "$a1", "$a2", "$a3", - "$a4", "$a5", "$a6", "$a7", "$t0", "$t1", "$t2", "$t3", -@@ -49,7 +49,7 @@ const char *const loongarch_r_lp64_name[32] = - "$s1", "$s2", "$s3", "$s4", "$s5", "$s6", "$s7", "$s8", - }; - --const char *const loongarch_r_lp64_name_deprecated[32] = -+const char *const loongarch_r_alias_deprecated[32] = - { - "", "", "", "", "$v0", "$v1", "", "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "$x", "", "", "", "", "", "", "", "", "", "", -@@ -63,7 +63,7 @@ const char *const loongarch_f_normal_name[32] = - "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", - }; - --const char *const loongarch_f_lp64_name[32] = -+const char *const loongarch_f_alias[32] = - { - "$fa0", "$fa1", "$fa2", "$fa3", "$fa4", "$fa5", "$fa6", "$fa7", - "$ft0", "$ft1", "$ft2", "$ft3", "$ft4", "$ft5", "$ft6", "$ft7", -@@ -71,7 +71,7 @@ const char *const loongarch_f_lp64_name[32] = - "$fs0", "$fs1", "$fs2", "$fs3", "$fs4", "$fs5", "$fs6", "$fs7", - }; - --const char *const loongarch_f_lp64_name_deprecated[32] = -+const char *const loongarch_f_alias_deprecated[32] = - { - "$fv0", "$fv1", "", "", "", "", "", "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", --- -2.33.0 - diff --git a/Add-support-for-pcaddi-rd-symbol.patch b/Add-support-for-pcaddi-rd-symbol.patch deleted file mode 100644 index ce4ee80..0000000 --- a/Add-support-for-pcaddi-rd-symbol.patch +++ /dev/null @@ -1,446 +0,0 @@ -From 91fcca79e66c426791c9055156644e96024e6599 Mon Sep 17 00:00:00 2001 -From: mengqinggang -Date: Mon, 18 Sep 2023 18:00:21 +0800 -Subject: [PATCH 010/123] Add support for "pcaddi rd, symbol" - -Add a macro pcaddi instruction to support "pcaddi rd, symbol". - -pcaddi has a 20-bit signed immediate, it can address a +/- 2MB pc relative -address, and the address should be 4-byte aligned. ---- - bfd/elfxx-loongarch.c | 4 +- - gas/testsuite/gas/loongarch/imm_ins.d | 137 ++++++++++++----------- - gas/testsuite/gas/loongarch/imm_ins_32.d | 91 +++++++-------- - gas/testsuite/gas/loongarch/imm_op.d | 82 +++++++------- - gas/testsuite/gas/loongarch/imm_op.s | 2 +- - gas/testsuite/gas/loongarch/pcaddi.d | 13 +++ - gas/testsuite/gas/loongarch/pcaddi.s | 4 + - opcodes/loongarch-opc.c | 2 +- - 8 files changed, 177 insertions(+), 158 deletions(-) - create mode 100644 gas/testsuite/gas/loongarch/pcaddi.d - create mode 100644 gas/testsuite/gas/loongarch/pcaddi.s - -diff --git a/bfd/elfxx-loongarch.c b/bfd/elfxx-loongarch.c -index 16a2b2fc..fd9507ce 100644 ---- a/bfd/elfxx-loongarch.c -+++ b/bfd/elfxx-loongarch.c -@@ -1415,7 +1415,7 @@ static loongarch_reloc_howto_type loongarch_howto_table[] = - NULL, /* adjust_reloc_bits. */ - NULL), /* larch_reloc_type_name. */ - -- /* pcala_hi20 + pcala_lo12 relaxed to pcrel20_s2. */ -+ /* For pcaddi and pcala_hi20 + pcala_lo12 can relax to pcrel_20. */ - LOONGARCH_HOWTO (R_LARCH_PCREL20_S2, /* type (103). */ - 2, /* rightshift. */ - 4, /* size. */ -@@ -1431,7 +1431,7 @@ static loongarch_reloc_howto_type loongarch_howto_table[] = - false, /* pcrel_offset. */ - BFD_RELOC_LARCH_PCREL20_S2, /* bfd_reloc_code_real_type. */ - reloc_sign_bits, /* adjust_reloc_bits. */ -- NULL), /* larch_reloc_type_name. */ -+ "pcrel_20"), /* larch_reloc_type_name. */ - - /* Canonical Frame Address. */ - LOONGARCH_HOWTO (R_LARCH_CFA, /* type (104). */ -diff --git a/gas/testsuite/gas/loongarch/imm_ins.d b/gas/testsuite/gas/loongarch/imm_ins.d -index f00110cd..b54df873 100644 ---- a/gas/testsuite/gas/loongarch/imm_ins.d -+++ b/gas/testsuite/gas/loongarch/imm_ins.d -@@ -7,74 +7,75 @@ - - Disassembly of section .text: - --00000000.* <.text>: --[ ]+0:[ ]+03848c0c[ ]+li.w[ ]+\$t0,[ ]+0x123 --[ ]+4:[ ]+15ffe00d[ ]+lu12i.w[ ]+\$t1,[ ]+-256 --[ ]+8:[ ]+16001fed[ ]+lu32i.d[ ]+\$t1,[ ]+255 --[ ]+c:[ ]+02bffc0e[ ]+li.w[ ]+\$t2,[ ]+-1 --[ ]+10:[ ]+1601ffee[ ]+lu32i.d[ ]+\$t2,[ ]+4095 --[ ]+14:[ ]+0004b58b[ ]+alsl.w[ ]+\$a7,[ ]+\$t0,[ ]+\$t1,[ ]+0x2 --[ ]+18:[ ]+0006b58b[ ]+alsl.wu[ ]+\$a7,[ ]+\$t0,[ ]+\$t1,[ ]+0x2 --[ ]+1c:[ ]+0009358b[ ]+bytepick.w[ ]+\$a7,[ ]+\$t0,[ ]+\$t1,[ ]+0x2 --[ ]+20:[ ]+000d358b[ ]+bytepick.d[ ]+\$a7,[ ]+\$t0,[ ]+\$t1,[ ]+0x2 -+[ ]*0000000000000000 <.text>: -+[ ]+0:[ ]+03848c0c[ ]+li.w[ ]+\$t0, 0x123 -+[ ]+4:[ ]+15ffe00d[ ]+lu12i.w[ ]+\$t1, -256 -+[ ]+8:[ ]+16001fed[ ]+lu32i.d[ ]+\$t1, 255 -+[ ]+c:[ ]+02bffc0e[ ]+li.w[ ]+\$t2, -1 -+[ ]+10:[ ]+1601ffee[ ]+lu32i.d[ ]+\$t2, 4095 -+[ ]+14:[ ]+0004b58b[ ]+alsl.w[ ]+\$a7, \$t0, \$t1, 0x2 -+[ ]+18:[ ]+0006b58b[ ]+alsl.wu[ ]+\$a7, \$t0, \$t1, 0x2 -+[ ]+1c:[ ]+0009358b[ ]+bytepick.w[ ]+\$a7, \$t0, \$t1, 0x2 -+[ ]+20:[ ]+000d358b[ ]+bytepick.d[ ]+\$a7, \$t0, \$t1, 0x2 - [ ]+24:[ ]+002a0002[ ]+break[ ]+0x2 - [ ]+28:[ ]+002a8002[ ]+dbcl[ ]+0x2 - [ ]+2c:[ ]+002b0002[ ]+syscall[ ]+0x2 --[ ]+30:[ ]+002cb58b[ ]+alsl.d[ ]+\$a7,[ ]+\$t0,[ ]+\$t1,[ ]+0x2 --[ ]+34:[ ]+0040898b[ ]+slli.w[ ]+\$a7,[ ]+\$t0,[ ]+0x2 --[ ]+38:[ ]+0041098b[ ]+slli.d[ ]+\$a7,[ ]+\$t0,[ ]+0x2 --[ ]+3c:[ ]+0044898b[ ]+srli.w[ ]+\$a7,[ ]+\$t0,[ ]+0x2 --[ ]+40:[ ]+004509ac[ ]+srli.d[ ]+\$t0,[ ]+\$t1,[ ]+0x2 --[ ]+44:[ ]+004889ac[ ]+srai.w[ ]+\$t0,[ ]+\$t1,[ ]+0x2 --[ ]+48:[ ]+004909ac[ ]+srai.d[ ]+\$t0,[ ]+\$t1,[ ]+0x2 --[ ]+4c:[ ]+006209ac[ ]+bstrins.w[ ]+\$t0,[ ]+\$t1,[ ]+0x2,[ ]+0x2 --[ ]+50:[ ]+008209ac[ ]+bstrins.d[ ]+\$t0,[ ]+\$t1,[ ]+0x2,[ ]+0x2 --[ ]+54:[ ]+00c209ac[ ]+bstrpick.d[ ]+\$t0,[ ]+\$t1,[ ]+0x2,[ ]+0x2 --[ ]+58:[ ]+00c209ac[ ]+bstrpick.d[ ]+\$t0,[ ]+\$t1,[ ]+0x2,[ ]+0x2 --[ ]+5c:[ ]+02048dac[ ]+slti[ ]+\$t0,[ ]+\$t1,[ ]+291 --[ ]+60:[ ]+02448dac[ ]+sltui[ ]+\$t0,[ ]+\$t1,[ ]+291 --[ ]+64:[ ]+02848dac[ ]+addi.w[ ]+\$t0,[ ]+\$t1,[ ]+291 --[ ]+68:[ ]+02c48dac[ ]+addi.d[ ]+\$t0,[ ]+\$t1,[ ]+291 --[ ]+6c:[ ]+03048dac[ ]+lu52i.d[ ]+\$t0,[ ]+\$t1,[ ]+291 --[ ]+70:[ ]+034009ac[ ]+andi[ ]+\$t0,[ ]+\$t1,[ ]+0x2 --[ ]+74:[ ]+038009ac[ ]+ori[ ]+\$t0,[ ]+\$t1,[ ]+0x2 --[ ]+78:[ ]+03c009ac[ ]+xori[ ]+\$t0,[ ]+\$t1,[ ]+0x2 --[ ]+7c:[ ]+100009ac[ ]+addu16i.d[ ]+\$t0,[ ]+\$t1,[ ]+2 --[ ]+80:[ ]+1400246c[ ]+lu12i.w[ ]+\$t0,[ ]+291 --[ ]+84:[ ]+1600246c[ ]+lu32i.d[ ]+\$t0,[ ]+291 --[ ]+88:[ ]+1800246c[ ]+pcaddi[ ]+\$t0,[ ]+291 --[ ]+8c:[ ]+1a00246c[ ]+pcalau12i[ ]+\$t0,[ ]+291 --[ ]+90:[ ]+1c00246c[ ]+pcaddu12i[ ]+\$t0,[ ]+291 --[ ]+94:[ ]+1e00246c[ ]+pcaddu18i[ ]+\$t0,[ ]+291 --[ ]+98:[ ]+04048c0c[ ]+csrrd[ ]+\$t0,[ ]+0x123 --[ ]+9c:[ ]+04048c2c[ ]+csrwr[ ]+\$t0,[ ]+0x123 --[ ]+a0:[ ]+040009ac[ ]+csrxchg[ ]+\$t0,[ ]+\$t1,[ ]+0x2 --[ ]+a4:[ ]+060009a2[ ]+cacop[ ]+0x2,[ ]+\$t1,[ ]+2 --[ ]+a8:[ ]+064009ac[ ]+lddir[ ]+\$t0,[ ]+\$t1,[ ]+0x2 --[ ]+ac:[ ]+06440980[ ]+ldpte[ ]+\$t0,[ ]+0x2 --[ ]+b0:[ ]+0649b9a2[ ]+invtlb[ ]+0x2,[ ]+\$t1,[ ]+\$t2 --[ ]+b4:[ ]+200101ac[ ]+ll.w[ ]+\$t0,[ ]+\$t1,[ ]+256 --[ ]+b8:[ ]+210101ac[ ]+sc.w[ ]+\$t0,[ ]+\$t1,[ ]+256 --[ ]+bc:[ ]+220101ac[ ]+ll.d[ ]+\$t0,[ ]+\$t1,[ ]+256 --[ ]+c0:[ ]+230101ac[ ]+sc.d[ ]+\$t0,[ ]+\$t1,[ ]+256 --[ ]+c4:[ ]+240101ac[ ]+ldptr.w[ ]+\$t0,[ ]+\$t1,[ ]+256 --[ ]+c8:[ ]+250101ac[ ]+stptr.w[ ]+\$t0,[ ]+\$t1,[ ]+256 --[ ]+cc:[ ]+260101ac[ ]+ldptr.d[ ]+\$t0,[ ]+\$t1,[ ]+256 --[ ]+d0:[ ]+270101ac[ ]+stptr.d[ ]+\$t0,[ ]+\$t1,[ ]+256 --[ ]+d4:[ ]+280401ac[ ]+ld.b[ ]+\$t0,[ ]+\$t1,[ ]+256 --[ ]+d8:[ ]+284401ac[ ]+ld.h[ ]+\$t0,[ ]+\$t1,[ ]+256 --[ ]+dc:[ ]+288401ac[ ]+ld.w[ ]+\$t0,[ ]+\$t1,[ ]+256 --[ ]+e0:[ ]+28c401ac[ ]+ld.d[ ]+\$t0,[ ]+\$t1,[ ]+256 --[ ]+e4:[ ]+290401ac[ ]+st.b[ ]+\$t0,[ ]+\$t1,[ ]+256 --[ ]+e8:[ ]+294401ac[ ]+st.h[ ]+\$t0,[ ]+\$t1,[ ]+256 --[ ]+ec:[ ]+298401ac[ ]+st.w[ ]+\$t0,[ ]+\$t1,[ ]+256 --[ ]+f0:[ ]+29c401ac[ ]+st.d[ ]+\$t0,[ ]+\$t1,[ ]+256 --[ ]+f4:[ ]+2a0401ac[ ]+ld.bu[ ]+\$t0,[ ]+\$t1,[ ]+256 --[ ]+f8:[ ]+2a4401ac[ ]+ld.hu[ ]+\$t0,[ ]+\$t1,[ ]+256 --[ ]+fc:[ ]+2a8401ac[ ]+ld.wu[ ]+\$t0,[ ]+\$t1,[ ]+256 --[ ]+100:[ ]+2ac401a2[ ]+preld[ ]+0x2,[ ]+\$t1,[ ]+256 --[ ]+104:[ ]+382c39a2[ ]+preldx[ ]+0x2,[ ]+\$t1,[ ]+\$t2 --[ ]+108:[ ]+2b048d8a[ ]+fld.s[ ]+\$ft2,[ ]+\$t0,[ ]+291 --[ ]+10c:[ ]+2b448d8a[ ]+fst.s[ ]+\$ft2,[ ]+\$t0,[ ]+291 --[ ]+110:[ ]+2b848d8a[ ]+fld.d[ ]+\$ft2,[ ]+\$t0,[ ]+291 --[ ]+114:[ ]+2bc48d8a[ ]+fst.d[ ]+\$ft2,[ ]+\$t0,[ ]+291 -+[ ]+30:[ ]+002cb58b[ ]+alsl.d[ ]+\$a7, \$t0, \$t1, 0x2 -+[ ]+34:[ ]+0040898b[ ]+slli.w[ ]+\$a7, \$t0, 0x2 -+[ ]+38:[ ]+0041098b[ ]+slli.d[ ]+\$a7, \$t0, 0x2 -+[ ]+3c:[ ]+0044898b[ ]+srli.w[ ]+\$a7, \$t0, 0x2 -+[ ]+40:[ ]+004509ac[ ]+srli.d[ ]+\$t0, \$t1, 0x2 -+[ ]+44:[ ]+004889ac[ ]+srai.w[ ]+\$t0, \$t1, 0x2 -+[ ]+48:[ ]+004909ac[ ]+srai.d[ ]+\$t0, \$t1, 0x2 -+[ ]+4c:[ ]+006209ac[ ]+bstrins.w[ ]+\$t0, \$t1, 0x2, 0x2 -+[ ]+50:[ ]+008209ac[ ]+bstrins.d[ ]+\$t0, \$t1, 0x2, 0x2 -+[ ]+54:[ ]+00c209ac[ ]+bstrpick.d[ ]+\$t0, \$t1, 0x2, 0x2 -+[ ]+58:[ ]+00c209ac[ ]+bstrpick.d[ ]+\$t0, \$t1, 0x2, 0x2 -+[ ]+5c:[ ]+02048dac[ ]+slti[ ]+\$t0, \$t1, 291 -+[ ]+60:[ ]+02448dac[ ]+sltui[ ]+\$t0, \$t1, 291 -+[ ]+64:[ ]+02848dac[ ]+addi.w[ ]+\$t0, \$t1, 291 -+[ ]+68:[ ]+02c48dac[ ]+addi.d[ ]+\$t0, \$t1, 291 -+[ ]+6c:[ ]+03048dac[ ]+lu52i.d[ ]+\$t0, \$t1, 291 -+[ ]+70:[ ]+034009ac[ ]+andi[ ]+\$t0, \$t1, 0x2 -+[ ]+74:[ ]+038009ac[ ]+ori[ ]+\$t0, \$t1, 0x2 -+[ ]+78:[ ]+03c009ac[ ]+xori[ ]+\$t0, \$t1, 0x2 -+[ ]+7c:[ ]+100009ac[ ]+addu16i.d[ ]+\$t0, \$t1, 2 -+[ ]+80:[ ]+1400246c[ ]+lu12i.w[ ]+\$t0, 291 -+[ ]+84:[ ]+1600246c[ ]+lu32i.d[ ]+\$t0, 291 -+[ ]+88:[ ]+1800000c[ ]+pcaddi[ ]+\$t0, 0 -+[ ]+88: R_LARCH_PCREL20_S2[ ]+\*ABS\*\+0x123 -+[ ]+8c:[ ]+1a00246c[ ]+pcalau12i[ ]+\$t0, 291 -+[ ]+90:[ ]+1c00246c[ ]+pcaddu12i[ ]+\$t0, 291 -+[ ]+94:[ ]+1e00246c[ ]+pcaddu18i[ ]+\$t0, 291 -+[ ]+98:[ ]+04048c0c[ ]+csrrd[ ]+\$t0, 0x123 -+[ ]+9c:[ ]+04048c2c[ ]+csrwr[ ]+\$t0, 0x123 -+[ ]+a0:[ ]+040009ac[ ]+csrxchg[ ]+\$t0, \$t1, 0x2 -+[ ]+a4:[ ]+060009a2[ ]+cacop[ ]+0x2, \$t1, 2 -+[ ]+a8:[ ]+064009ac[ ]+lddir[ ]+\$t0, \$t1, 0x2 -+[ ]+ac:[ ]+06440980[ ]+ldpte[ ]+\$t0, 0x2 -+[ ]+b0:[ ]+0649b9a2[ ]+invtlb[ ]+0x2, \$t1, \$t2 -+[ ]+b4:[ ]+200101ac[ ]+ll.w[ ]+\$t0, \$t1, 256 -+[ ]+b8:[ ]+210101ac[ ]+sc.w[ ]+\$t0, \$t1, 256 -+[ ]+bc:[ ]+220101ac[ ]+ll.d[ ]+\$t0, \$t1, 256 -+[ ]+c0:[ ]+230101ac[ ]+sc.d[ ]+\$t0, \$t1, 256 -+[ ]+c4:[ ]+240101ac[ ]+ldptr.w[ ]+\$t0, \$t1, 256 -+[ ]+c8:[ ]+250101ac[ ]+stptr.w[ ]+\$t0, \$t1, 256 -+[ ]+cc:[ ]+260101ac[ ]+ldptr.d[ ]+\$t0, \$t1, 256 -+[ ]+d0:[ ]+270101ac[ ]+stptr.d[ ]+\$t0, \$t1, 256 -+[ ]+d4:[ ]+280401ac[ ]+ld.b[ ]+\$t0, \$t1, 256 -+[ ]+d8:[ ]+284401ac[ ]+ld.h[ ]+\$t0, \$t1, 256 -+[ ]+dc:[ ]+288401ac[ ]+ld.w[ ]+\$t0, \$t1, 256 -+[ ]+e0:[ ]+28c401ac[ ]+ld.d[ ]+\$t0, \$t1, 256 -+[ ]+e4:[ ]+290401ac[ ]+st.b[ ]+\$t0, \$t1, 256 -+[ ]+e8:[ ]+294401ac[ ]+st.h[ ]+\$t0, \$t1, 256 -+[ ]+ec:[ ]+298401ac[ ]+st.w[ ]+\$t0, \$t1, 256 -+[ ]+f0:[ ]+29c401ac[ ]+st.d[ ]+\$t0, \$t1, 256 -+[ ]+f4:[ ]+2a0401ac[ ]+ld.bu[ ]+\$t0, \$t1, 256 -+[ ]+f8:[ ]+2a4401ac[ ]+ld.hu[ ]+\$t0, \$t1, 256 -+[ ]+fc:[ ]+2a8401ac[ ]+ld.wu[ ]+\$t0, \$t1, 256 -+[ ]+100:[ ]+2ac401a2[ ]+preld[ ]+0x2, \$t1, 256 -+[ ]+104:[ ]+382c39a2[ ]+preldx[ ]+0x2, \$t1, \$t2 -+[ ]+108:[ ]+2b048d8a[ ]+fld.s[ ]+\$ft2, \$t0, 291 -+[ ]+10c:[ ]+2b448d8a[ ]+fst.s[ ]+\$ft2, \$t0, 291 -+[ ]+110:[ ]+2b848d8a[ ]+fld.d[ ]+\$ft2, \$t0, 291 -+[ ]+114:[ ]+2bc48d8a[ ]+fst.d[ ]+\$ft2, \$t0, 291 -diff --git a/gas/testsuite/gas/loongarch/imm_ins_32.d b/gas/testsuite/gas/loongarch/imm_ins_32.d -index dc2eeb9e..3662fdda 100644 ---- a/gas/testsuite/gas/loongarch/imm_ins_32.d -+++ b/gas/testsuite/gas/loongarch/imm_ins_32.d -@@ -7,51 +7,52 @@ - - Disassembly of section .text: - --00000000.* <.text>: --[ ]+0:[ ]+03848c0c[ ]+li.w[ ]+\$t0,[ ]+0x123 --[ ]+4:[ ]+0004b58b[ ]+alsl.w[ ]+\$a7,[ ]+\$t0,[ ]+\$t1,[ ]+0x2 --[ ]+8:[ ]+0006b58b[ ]+alsl.wu[ ]+\$a7,[ ]+\$t0,[ ]+\$t1,[ ]+0x2 --[ ]+c:[ ]+0009358b[ ]+bytepick.w[ ]+\$a7,[ ]+\$t0,[ ]+\$t1,[ ]+0x2 -+.* <.text>: -+[ ]+0:[ ]+03848c0c[ ]+li.w[ ]+\$t0, 0x123 -+[ ]+4:[ ]+0004b58b[ ]+alsl.w[ ]+\$a7, \$t0, \$t1, 0x2 -+[ ]+8:[ ]+0006b58b[ ]+alsl.wu[ ]+\$a7, \$t0, \$t1, 0x2 -+[ ]+c:[ ]+0009358b[ ]+bytepick.w[ ]+\$a7, \$t0, \$t1, 0x2 - [ ]+10:[ ]+002a0002[ ]+break[ ]+0x2 - [ ]+14:[ ]+002a8002[ ]+dbcl[ ]+0x2 - [ ]+18:[ ]+002b0002[ ]+syscall[ ]+0x2 --[ ]+1c:[ ]+0040898b[ ]+slli.w[ ]+\$a7,[ ]+\$t0,[ ]+0x2 --[ ]+20:[ ]+0044898b[ ]+srli.w[ ]+\$a7,[ ]+\$t0,[ ]+0x2 --[ ]+24:[ ]+004889ac[ ]+srai.w[ ]+\$t0,[ ]+\$t1,[ ]+0x2 --[ ]+28:[ ]+006209ac[ ]+bstrins.w[ ]+\$t0,[ ]+\$t1,[ ]+0x2,[ ]+0x2 --[ ]+2c:[ ]+02048dac[ ]+slti[ ]+\$t0,[ ]+\$t1,[ ]+291 --[ ]+30:[ ]+02448dac[ ]+sltui[ ]+\$t0,[ ]+\$t1,[ ]+291 --[ ]+34:[ ]+02848dac[ ]+addi.w[ ]+\$t0,[ ]+\$t1,[ ]+291 --[ ]+38:[ ]+034009ac[ ]+andi[ ]+\$t0,[ ]+\$t1,[ ]+0x2 --[ ]+3c:[ ]+038009ac[ ]+ori[ ]+\$t0,[ ]+\$t1,[ ]+0x2 --[ ]+40:[ ]+03c009ac[ ]+xori[ ]+\$t0,[ ]+\$t1,[ ]+0x2 --[ ]+44:[ ]+1400246c[ ]+lu12i.w[ ]+\$t0,[ ]+291 --[ ]+48:[ ]+1800246c[ ]+pcaddi[ ]+\$t0,[ ]+291 --[ ]+4c:[ ]+1a00246c[ ]+pcalau12i[ ]+\$t0,[ ]+291 --[ ]+50:[ ]+1c00246c[ ]+pcaddu12i[ ]+\$t0,[ ]+291 --[ ]+54:[ ]+1e00246c[ ]+pcaddu18i[ ]+\$t0,[ ]+291 --[ ]+58:[ ]+04048c0c[ ]+csrrd[ ]+\$t0,[ ]+0x123 --[ ]+5c:[ ]+04048c2c[ ]+csrwr[ ]+\$t0,[ ]+0x123 --[ ]+60:[ ]+040009ac[ ]+csrxchg[ ]+\$t0,[ ]+\$t1,[ ]+0x2 --[ ]+64:[ ]+060009a2[ ]+cacop[ ]+0x2,[ ]+\$t1,[ ]+2 --[ ]+68:[ ]+064009ac[ ]+lddir[ ]+\$t0,[ ]+\$t1,[ ]+0x2 --[ ]+6c:[ ]+06440980[ ]+ldpte[ ]+\$t0,[ ]+0x2 --[ ]+70:[ ]+0649b9a2[ ]+invtlb[ ]+0x2,[ ]+\$t1,[ ]+\$t2 --[ ]+74:[ ]+200101ac[ ]+ll.w[ ]+\$t0,[ ]+\$t1,[ ]+256 --[ ]+78:[ ]+210101ac[ ]+sc.w[ ]+\$t0,[ ]+\$t1,[ ]+256 --[ ]+7c:[ ]+220101ac[ ]+ll.d[ ]+\$t0,[ ]+\$t1,[ ]+256 --[ ]+80:[ ]+230101ac[ ]+sc.d[ ]+\$t0,[ ]+\$t1,[ ]+256 --[ ]+84:[ ]+240101ac[ ]+ldptr.w[ ]+\$t0,[ ]+\$t1,[ ]+256 --[ ]+88:[ ]+250101ac[ ]+stptr.w[ ]+\$t0,[ ]+\$t1,[ ]+256 --[ ]+8c:[ ]+284401ac[ ]+ld.h[ ]+\$t0,[ ]+\$t1,[ ]+256 --[ ]+90:[ ]+288401ac[ ]+ld.w[ ]+\$t0,[ ]+\$t1,[ ]+256 --[ ]+94:[ ]+290401ac[ ]+st.b[ ]+\$t0,[ ]+\$t1,[ ]+256 --[ ]+98:[ ]+294401ac[ ]+st.h[ ]+\$t0,[ ]+\$t1,[ ]+256 --[ ]+9c:[ ]+298401ac[ ]+st.w[ ]+\$t0,[ ]+\$t1,[ ]+256 --[ ]+a0:[ ]+2a0401ac[ ]+ld.bu[ ]+\$t0,[ ]+\$t1,[ ]+256 --[ ]+a4:[ ]+2a4401ac[ ]+ld.hu[ ]+\$t0,[ ]+\$t1,[ ]+256 --[ ]+a8:[ ]+2a8401ac[ ]+ld.wu[ ]+\$t0,[ ]+\$t1,[ ]+256 --[ ]+ac:[ ]+2ac401a2[ ]+preld[ ]+0x2,[ ]+\$t1,[ ]+256 --[ ]+b0:[ ]+382c39a2[ ]+preldx[ ]+0x2,[ ]+\$t1,[ ]+\$t2 --[ ]+b4:[ ]+2b048d8a[ ]+fld.s[ ]+\$ft2,[ ]+\$t0,[ ]+291 --[ ]+b8:[ ]+2b448d8a[ ]+fst.s[ ]+\$ft2,[ ]+\$t0,[ ]+291 -+[ ]+1c:[ ]+0040898b[ ]+slli.w[ ]+\$a7, \$t0, 0x2 -+[ ]+20:[ ]+0044898b[ ]+srli.w[ ]+\$a7, \$t0, 0x2 -+[ ]+24:[ ]+004889ac[ ]+srai.w[ ]+\$t0, \$t1, 0x2 -+[ ]+28:[ ]+006209ac[ ]+bstrins.w[ ]+\$t0, \$t1, 0x2, 0x2 -+[ ]+2c:[ ]+02048dac[ ]+slti[ ]+\$t0, \$t1, 291 -+[ ]+30:[ ]+02448dac[ ]+sltui[ ]+\$t0, \$t1, 291 -+[ ]+34:[ ]+02848dac[ ]+addi.w[ ]+\$t0, \$t1, 291 -+[ ]+38:[ ]+034009ac[ ]+andi[ ]+\$t0, \$t1, 0x2 -+[ ]+3c:[ ]+038009ac[ ]+ori[ ]+\$t0, \$t1, 0x2 -+[ ]+40:[ ]+03c009ac[ ]+xori[ ]+\$t0, \$t1, 0x2 -+[ ]+44:[ ]+1400246c[ ]+lu12i.w[ ]+\$t0, 291 -+[ ]+48:[ ]+1800000c[ ]+pcaddi[ ]+\$t0, 0 -+[ ]+48: R_LARCH_PCREL20_S2[ ]+\*ABS\*\+0x123 -+[ ]+4c:[ ]+1a00246c[ ]+pcalau12i[ ]+\$t0, 291 -+[ ]+50:[ ]+1c00246c[ ]+pcaddu12i[ ]+\$t0, 291 -+[ ]+54:[ ]+1e00246c[ ]+pcaddu18i[ ]+\$t0, 291 -+[ ]+58:[ ]+04048c0c[ ]+csrrd[ ]+\$t0, 0x123 -+[ ]+5c:[ ]+04048c2c[ ]+csrwr[ ]+\$t0, 0x123 -+[ ]+60:[ ]+040009ac[ ]+csrxchg[ ]+\$t0, \$t1, 0x2 -+[ ]+64:[ ]+060009a2[ ]+cacop[ ]+0x2, \$t1, 2 -+[ ]+68:[ ]+064009ac[ ]+lddir[ ]+\$t0, \$t1, 0x2 -+[ ]+6c:[ ]+06440980[ ]+ldpte[ ]+\$t0, 0x2 -+[ ]+70:[ ]+0649b9a2[ ]+invtlb[ ]+0x2, \$t1, \$t2 -+[ ]+74:[ ]+200101ac[ ]+ll.w[ ]+\$t0, \$t1, 256 -+[ ]+78:[ ]+210101ac[ ]+sc.w[ ]+\$t0, \$t1, 256 -+[ ]+7c:[ ]+220101ac[ ]+ll.d[ ]+\$t0, \$t1, 256 -+[ ]+80:[ ]+230101ac[ ]+sc.d[ ]+\$t0, \$t1, 256 -+[ ]+84:[ ]+240101ac[ ]+ldptr.w[ ]+\$t0, \$t1, 256 -+[ ]+88:[ ]+250101ac[ ]+stptr.w[ ]+\$t0, \$t1, 256 -+[ ]+8c:[ ]+284401ac[ ]+ld.h[ ]+\$t0, \$t1, 256 -+[ ]+90:[ ]+288401ac[ ]+ld.w[ ]+\$t0, \$t1, 256 -+[ ]+94:[ ]+290401ac[ ]+st.b[ ]+\$t0, \$t1, 256 -+[ ]+98:[ ]+294401ac[ ]+st.h[ ]+\$t0, \$t1, 256 -+[ ]+9c:[ ]+298401ac[ ]+st.w[ ]+\$t0, \$t1, 256 -+[ ]+a0:[ ]+2a0401ac[ ]+ld.bu[ ]+\$t0, \$t1, 256 -+[ ]+a4:[ ]+2a4401ac[ ]+ld.hu[ ]+\$t0, \$t1, 256 -+[ ]+a8:[ ]+2a8401ac[ ]+ld.wu[ ]+\$t0, \$t1, 256 -+[ ]+ac:[ ]+2ac401a2[ ]+preld[ ]+0x2, \$t1, 256 -+[ ]+b0:[ ]+382c39a2[ ]+preldx[ ]+0x2, \$t1, \$t2 -+[ ]+b4:[ ]+2b048d8a[ ]+fld.s[ ]+\$ft2, \$t0, 291 -+[ ]+b8:[ ]+2b448d8a[ ]+fst.s[ ]+\$ft2, \$t0, 291 -diff --git a/gas/testsuite/gas/loongarch/imm_op.d b/gas/testsuite/gas/loongarch/imm_op.d -index 3d4cba45..2885fc96 100644 ---- a/gas/testsuite/gas/loongarch/imm_op.d -+++ b/gas/testsuite/gas/loongarch/imm_op.d -@@ -1,48 +1,48 @@ - #as: - #objdump: -dr - --.*:[ ]+file format .* -+.*:[ ]+file format .* - - - Disassembly of section .text: - --00000000.* <.text>: --[ ]+0:[ ]+020000a4 [ ]+slti[ ]+[ ]+\$a0, \$a1, 0 --[ ]+4:[ ]+021ffca4 [ ]+slti[ ]+[ ]+\$a0, \$a1, 2047 --[ ]+8:[ ]+022004a4 [ ]+slti[ ]+[ ]+\$a0, \$a1, -2047 --[ ]+c:[ ]+024000a4 [ ]+sltui[ ]+[ ]+\$a0, \$a1, 0 --[ ]+10:[ ]+025ffca4 [ ]+sltui[ ]+[ ]+\$a0, \$a1, 2047 --[ ]+14:[ ]+026004a4 [ ]+sltui[ ]+[ ]+\$a0, \$a1, -2047 --[ ]+18:[ ]+028000a4 [ ]+addi.w[ ]+[ ]+\$a0, \$a1, 0 --[ ]+1c:[ ]+029ffca4 [ ]+addi.w[ ]+[ ]+\$a0, \$a1, 2047 --[ ]+20:[ ]+02a004a4 [ ]+addi.w[ ]+[ ]+\$a0, \$a1, -2047 --[ ]+24:[ ]+02c000a4 [ ]+addi.d[ ]+[ ]+\$a0, \$a1, 0 --[ ]+28:[ ]+02dffca4 [ ]+addi.d[ ]+[ ]+\$a0, \$a1, 2047 --[ ]+2c:[ ]+02e004a4 [ ]+addi.d[ ]+[ ]+\$a0, \$a1, -2047 --[ ]+30:[ ]+030000a4 [ ]+lu52i.d[ ]+[ ]+\$a0, \$a1, 0 --[ ]+34:[ ]+031ffca4 [ ]+lu52i.d[ ]+[ ]+\$a0, \$a1, 2047 --[ ]+38:[ ]+032004a4 [ ]+lu52i.d[ ]+[ ]+\$a0, \$a1, -2047 --[ ]+3c:[ ]+034000a4 [ ]+andi[ ]+[ ]+\$a0, \$a1, 0x0 --[ ]+40:[ ]+035ffca4 [ ]+andi[ ]+[ ]+\$a0, \$a1, 0x7ff --[ ]+44:[ ]+038000a4 [ ]+ori[ ]+[ ]+\$a0, \$a1, 0x0 --[ ]+48:[ ]+039ffca4 [ ]+ori[ ]+[ ]+\$a0, \$a1, 0x7ff --[ ]+4c:[ ]+03c000a4 [ ]+xori[ ]+[ ]+\$a0, \$a1, 0x0 --[ ]+50:[ ]+03dffca4 [ ]+xori[ ]+[ ]+\$a0, \$a1, 0x7ff --[ ]+54:[ ]+100000a4 [ ]+addu16i.d[ ]+[ ]+\$a0, \$a1, 0 --[ ]+58:[ ]+11fffca4 [ ]+addu16i.d[ ]+[ ]+\$a0, \$a1, 32767 --[ ]+5c:[ ]+120004a4 [ ]+addu16i.d[ ]+[ ]+\$a0, \$a1, -32767 --[ ]+60:[ ]+14000004 [ ]+lu12i.w[ ]+[ ]+\$a0, 0 --[ ]+64:[ ]+14ffffe4 [ ]+lu12i.w[ ]+[ ]+\$a0, 524287 --[ ]+68:[ ]+17000024 [ ]+lu32i.d[ ]+[ ]+\$a0, -524287 --[ ]+6c:[ ]+18000004 [ ]+pcaddi[ ]+[ ]+\$a0, 0 --[ ]+70:[ ]+18ffffe4 [ ]+pcaddi[ ]+[ ]+\$a0, 524287 --[ ]+74:[ ]+19000024 [ ]+pcaddi[ ]+[ ]+\$a0, -524287 --[ ]+78:[ ]+1a000004 [ ]+pcalau12i[ ]+[ ]+\$a0, 0 --[ ]+7c:[ ]+1affffe4 [ ]+pcalau12i[ ]+[ ]+\$a0, 524287 --[ ]+80:[ ]+1b000024 [ ]+pcalau12i[ ]+[ ]+\$a0, -524287 --[ ]+84:[ ]+1c000004 [ ]+pcaddu12i[ ]+[ ]+\$a0, 0 --[ ]+88:[ ]+1cffffe4 [ ]+pcaddu12i[ ]+[ ]+\$a0, 524287 --[ ]+8c:[ ]+1d000024 [ ]+pcaddu12i[ ]+[ ]+\$a0, -524287 --[ ]+90:[ ]+1e000004 [ ]+pcaddu18i[ ]+[ ]+\$a0, 0 --[ ]+94:[ ]+1effffe4 [ ]+pcaddu18i[ ]+[ ]+\$a0, 524287 --[ ]+98:[ ]+1f000024 [ ]+pcaddu18i[ ]+[ ]+\$a0, -524287 -+.* <.text>: -+[ ]+0:[ ]+020000a4[ ]+slti[ ]+\$a0, \$a1, 0 -+[ ]+4:[ ]+021ffca4[ ]+slti[ ]+\$a0, \$a1, 2047 -+[ ]+8:[ ]+022004a4[ ]+slti[ ]+\$a0, \$a1, -2047 -+[ ]+c:[ ]+024000a4[ ]+sltui[ ]+\$a0, \$a1, 0 -+[ ]+10:[ ]+025ffca4[ ]+sltui[ ]+\$a0, \$a1, 2047 -+[ ]+14:[ ]+026004a4[ ]+sltui[ ]+\$a0, \$a1, -2047 -+[ ]+18:[ ]+028000a4[ ]+addi.w[ ]+\$a0, \$a1, 0 -+[ ]+1c:[ ]+029ffca4[ ]+addi.w[ ]+\$a0, \$a1, 2047 -+[ ]+20:[ ]+02a004a4[ ]+addi.w[ ]+\$a0, \$a1, -2047 -+[ ]+24:[ ]+02c000a4[ ]+addi.d[ ]+\$a0, \$a1, 0 -+[ ]+28:[ ]+02dffca4[ ]+addi.d[ ]+\$a0, \$a1, 2047 -+[ ]+2c:[ ]+02e004a4[ ]+addi.d[ ]+\$a0, \$a1, -2047 -+[ ]+30:[ ]+030000a4[ ]+lu52i.d[ ]+\$a0, \$a1, 0 -+[ ]+34:[ ]+031ffca4[ ]+lu52i.d[ ]+\$a0, \$a1, 2047 -+[ ]+38:[ ]+032004a4[ ]+lu52i.d[ ]+\$a0, \$a1, -2047 -+[ ]+3c:[ ]+034000a4[ ]+andi[ ]+\$a0, \$a1, 0x0 -+[ ]+40:[ ]+035ffca4[ ]+andi[ ]+\$a0, \$a1, 0x7ff -+[ ]+44:[ ]+038000a4[ ]+ori[ ]+\$a0, \$a1, 0x0 -+[ ]+48:[ ]+039ffca4[ ]+ori[ ]+\$a0, \$a1, 0x7ff -+[ ]+4c:[ ]+03c000a4[ ]+xori[ ]+\$a0, \$a1, 0x0 -+[ ]+50:[ ]+03dffca4[ ]+xori[ ]+\$a0, \$a1, 0x7ff -+[ ]+54:[ ]+100000a4[ ]+addu16i.d[ ]+\$a0, \$a1, 0 -+[ ]+58:[ ]+11fffca4[ ]+addu16i.d[ ]+\$a0, \$a1, 32767 -+[ ]+5c:[ ]+120004a4[ ]+addu16i.d[ ]+\$a0, \$a1, -32767 -+[ ]+60:[ ]+14000004[ ]+lu12i.w[ ]+\$a0, 0 -+[ ]+64:[ ]+14ffffe4[ ]+lu12i.w[ ]+\$a0, 524287 -+[ ]+68:[ ]+17000024[ ]+lu32i.d[ ]+\$a0, -524287 -+[ ]+6c:[ ]+18000004[ ]+pcaddi[ ]+\$a0, 0 -+[ ]+70:[ ]+18ffffe4[ ]+pcaddi[ ]+\$a0, 524287 -+[ ]+74:[ ]+19000004[ ]+pcaddi[ ]+\$a0, -524288 -+[ ]+78:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0 -+[ ]+7c:[ ]+1affffe4[ ]+pcalau12i[ ]+\$a0, 524287 -+[ ]+80:[ ]+1b000024[ ]+pcalau12i[ ]+\$a0, -524287 -+[ ]+84:[ ]+1c000004[ ]+pcaddu12i[ ]+\$a0, 0 -+[ ]+88:[ ]+1cffffe4[ ]+pcaddu12i[ ]+\$a0, 524287 -+[ ]+8c:[ ]+1d000024[ ]+pcaddu12i[ ]+\$a0, -524287 -+[ ]+90:[ ]+1e000004[ ]+pcaddu18i[ ]+\$a0, 0 -+[ ]+94:[ ]+1effffe4[ ]+pcaddu18i[ ]+\$a0, 524287 -+[ ]+98:[ ]+1f000024[ ]+pcaddu18i[ ]+\$a0, -524287 -diff --git a/gas/testsuite/gas/loongarch/imm_op.s b/gas/testsuite/gas/loongarch/imm_op.s -index 7e1c5518..eae18260 100644 ---- a/gas/testsuite/gas/loongarch/imm_op.s -+++ b/gas/testsuite/gas/loongarch/imm_op.s -@@ -27,7 +27,7 @@ lu12i.w $r4,0x7ffff - lu32i.d $r4,-0x7ffff - pcaddi $r4,0 - pcaddi $r4,0x7ffff --pcaddi $r4,-0x7ffff -+pcaddi $r4,-0x80000 - pcalau12i $r4,0 - pcalau12i $r4,0x7ffff - pcalau12i $r4,-0x7ffff -diff --git a/gas/testsuite/gas/loongarch/pcaddi.d b/gas/testsuite/gas/loongarch/pcaddi.d -new file mode 100644 -index 00000000..3ddbbba5 ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/pcaddi.d -@@ -0,0 +1,13 @@ -+#as: -+#objdump: -dr -+ -+.*:[ ]+file format .* -+ -+ -+Disassembly of section .text: -+ -+.* <.L1>: -+[ ]+0:[ ]+1800000c[ ]+pcaddi[ ]+\$t0, 0 -+[ ]+0: R_LARCH_PCREL20_S2[ ]+.L1 -+[ ]+4:[ ]+1800000c[ ]+pcaddi[ ]+\$t0, 0 -+[ ]+4: R_LARCH_PCREL20_S2[ ]+.L2 -diff --git a/gas/testsuite/gas/loongarch/pcaddi.s b/gas/testsuite/gas/loongarch/pcaddi.s -new file mode 100644 -index 00000000..10d23e84 ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/pcaddi.s -@@ -0,0 +1,4 @@ -+.L1: -+ pcaddi $r12, .L1 -+ pcaddi $r12, .L2 -+.L2: -diff --git a/opcodes/loongarch-opc.c b/opcodes/loongarch-opc.c -index 4a88c4d7..5cd1411a 100644 ---- a/opcodes/loongarch-opc.c -+++ b/opcodes/loongarch-opc.c -@@ -340,7 +340,7 @@ static struct loongarch_opcode loongarch_macro_opcodes[] = - { 0, 0, "la.tls.gd", "r,l", INSN_LA_TLS_GD64, 0 }, - { 0, 0, "la.tls.gd", "r,l", INSN_LA_TLS_GD64_LARGE_ABS, 0 }, - { 0, 0, "la.tls.gd", "r,r,l", INSN_LA_TLS_GD64_LARGE_PCREL, 0 }, -- -+ { 0, 0, "pcaddi", "r,la", "pcaddi %1, %%pcrel_20(%2)", &LARCH_opts.ase_ilp32, 0, 0 }, - { 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list. */ - }; - --- -2.33.0 - diff --git a/Add-testcase-for-generation-of-32-64_PCREL.patch b/Add-testcase-for-generation-of-32-64_PCREL.patch deleted file mode 100644 index 6bbc03a..0000000 --- a/Add-testcase-for-generation-of-32-64_PCREL.patch +++ /dev/null @@ -1,247 +0,0 @@ -From aa0064d1240e10856f352516f6097f3e75c5e463 Mon Sep 17 00:00:00 2001 -From: cailulu -Date: Fri, 1 Sep 2023 11:09:01 +0800 -Subject: [PATCH 007/123] Add testcase for generation of 32/64_PCREL. - ---- - gas/testsuite/gas/loongarch/pcrel_norelax.d | 56 +++++++++++++++++++ - gas/testsuite/gas/loongarch/pcrel_norelax.s | 42 +++++++++++++++ - gas/testsuite/gas/loongarch/pcrel_relax.d | 60 +++++++++++++++++++++ - gas/testsuite/gas/loongarch/pcrel_relax.s | 46 ++++++++++++++++ - 4 files changed, 204 insertions(+) - create mode 100644 gas/testsuite/gas/loongarch/pcrel_norelax.d - create mode 100644 gas/testsuite/gas/loongarch/pcrel_norelax.s - create mode 100644 gas/testsuite/gas/loongarch/pcrel_relax.d - create mode 100644 gas/testsuite/gas/loongarch/pcrel_relax.s - -diff --git a/gas/testsuite/gas/loongarch/pcrel_norelax.d b/gas/testsuite/gas/loongarch/pcrel_norelax.d -new file mode 100644 -index 00000000..842c8d48 ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/pcrel_norelax.d -@@ -0,0 +1,56 @@ -+#as: -mno-relax -+#objdump: -Dr -+ -+.*:[ ]+file format .* -+ -+ -+Disassembly of section .text: -+ -+00000000.* <.L1>: -+[ ]+... -+[ ]+0:[ ]+R_LARCH_32_PCREL[ ]+.L3 -+[ ]+4:[ ]+R_LARCH_32_PCREL[ ]+.L3\+0x4 -+ -+0*00000008[ ]+<.L2>: -+[ ]+... -+[ ]+8:[ ]+R_LARCH_64_PCREL[ ]+.L3 -+[ ]+10:[ ]+R_LARCH_64_PCREL[ ]+.L3\+0x8 -+ -+Disassembly[ ]+of[ ]+section[ ]+sx: -+ -+0*00000000[ ]+<.L3>: -+[ ]+0:[ ]+fffffff4[ ]+.word[ ]+0xfffffff4 -+[ ]+4:[ ]+fffffff4[ ]+.word[ ]+0xfffffff4 -+[ ]+8:[ ]+ffffffff[ ]+.word[ ]+0xffffffff -+ -+0*0000000c[ ]+<.L4>: -+[ ]+... -+[ ]+c:[ ]+R_LARCH_ADD32[ ]+.L4 -+[ ]+c:[ ]+R_LARCH_SUB32[ ]+.L5 -+[ ]+10:[ ]+R_LARCH_ADD64[ ]+.L4 -+[ ]+10:[ ]+R_LARCH_SUB64[ ]+.L5 -+ -+Disassembly[ ]+of[ ]+section[ ]+sy: -+ -+0*00000000[ ]+<.L5>: -+[ ]+... -+[ ]+0:[ ]+R_LARCH_32_PCREL[ ]+.L1 -+[ ]+4:[ ]+R_LARCH_32_PCREL[ ]+.L2\+0x4 -+[ ]+8:[ ]+R_LARCH_64_PCREL[ ]+.L1\+0x8 -+[ ]+10:[ ]+R_LARCH_64_PCREL[ ]+.L2\+0x10 -+ -+Disassembly[ ]+of[ ]+section[ ]+sz: -+ -+0*00000000[ ]+: -+[ ]+0:[ ]+fffffff8[ ]+.word[ ]+0xfffffff8 -+[ ]+4:[ ]+fffffff4[ ]+.word[ ]+0xfffffff4 -+[ ]+8:[ ]+00000000[ ]+.word[ ]+0x00000000 -+[ ]+8:[ ]+R_LARCH_ADD32[ ]+.L2 -+[ ]+8:[ ]+R_LARCH_SUB32[ ]+.L3 -+[ ]+c:[ ]+fffffff8[ ]+.word[ ]+0xfffffff8 -+[ ]+10:[ ]+ffffffff[ ]+.word[ ]+0xffffffff -+[ ]+14:[ ]+fffffff4[ ]+.word[ ]+0xfffffff4 -+[ ]+18:[ ]+ffffffff[ ]+.word[ ]+0xffffffff -+[ ]+... -+[ ]+1c:[ ]+R_LARCH_ADD64[ ]+.L2 -+[ ]+1c:[ ]+R_LARCH_SUB64[ ]+.L3 -diff --git a/gas/testsuite/gas/loongarch/pcrel_norelax.s b/gas/testsuite/gas/loongarch/pcrel_norelax.s -new file mode 100644 -index 00000000..09527f14 ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/pcrel_norelax.s -@@ -0,0 +1,42 @@ -+ .section .text -+.L1: -+ # 32_pcrel -+ .4byte .L3-.L1 -+ .4byte .L3-.L1 -+.L2: -+ # 64_pcrel -+ .8byte .L3-.L2 -+ .8byte .L3-.L2 -+ -+ .section sx -+.L3: -+ # no relocation -+ .4byte .L3-.L4 -+ .8byte .L3-.L4 -+.L4: -+ # add32+sub32 -+ .4byte .L4-.L5 -+ # add64+sub64 -+ .8byte .L4-.L5 -+ -+ .section sy -+.L5: -+ # 32_pcrel -+ .4byte .L1-.L5 -+ .4byte .L2-.L5 -+ # 64_pcrel -+ .8byte .L1-.L5 -+ .8byte .L2-.L5 -+ -+ .section sz -+ # no relocation -+ .4byte .L1-.L2 -+ .4byte .L3-.L4 -+ # add32+sub32 -+ .4byte .L2-.L3 -+ -+ # no relocation -+ .8byte .L1-.L2 -+ .8byte .L3-.L4 -+ # add64+sub64 -+ .8byte .L2-.L3 -diff --git a/gas/testsuite/gas/loongarch/pcrel_relax.d b/gas/testsuite/gas/loongarch/pcrel_relax.d -new file mode 100644 -index 00000000..d6f87525 ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/pcrel_relax.d -@@ -0,0 +1,60 @@ -+#as: -+#objdump: -Dr -+ -+.*:[ ]+file format .* -+ -+ -+Disassembly of section .text: -+ -+00000000.* <.L1>: -+[ ]+... -+[ ]+0:[ ]+R_LARCH_32_PCREL[ ]+.L3 -+[ ]+4:[ ]+R_LARCH_ADD32[ ]+.L3 -+[ ]+4:[ ]+R_LARCH_SUB32[ ]+.L1 -+ -+0*00000008[ ]+<.L2>: -+[ ]+... -+[ ]+8:[ ]+R_LARCH_64_PCREL[ ]+.L3 -+[ ]+10:[ ]+R_LARCH_ADD64[ ]+.L3 -+[ ]+10:[ ]+R_LARCH_SUB64[ ]+.L2 -+ -+Disassembly[ ]+of[ ]+section[ ]+sx: -+ -+0*00000000[ ]+<.L3>: -+[ ]+0:[ ]+fffffff4[ ]+.word[ ]+0xfffffff4 -+[ ]+4:[ ]+fffffff4[ ]+.word[ ]+0xfffffff4 -+[ ]+8:[ ]+ffffffff[ ]+.word[ ]+0xffffffff -+ -+0*0000000c[ ]+<.L4>: -+[ ]+... -+[ ]+c:[ ]+R_LARCH_ADD32[ ]+.L4 -+[ ]+c:[ ]+R_LARCH_SUB32[ ]+.L5 -+[ ]+10:[ ]+R_LARCH_ADD64[ ]+.L4 -+[ ]+10:[ ]+R_LARCH_SUB64[ ]+.L5 -+ -+Disassembly[ ]+of[ ]+section[ ]+sy: -+ -+0*00000000[ ]+<.L5>: -+[ ]+... -+[ ]+0:[ ]+R_LARCH_32_PCREL[ ]+.L1 -+[ ]+4:[ ]+R_LARCH_32_PCREL[ ]+.L3\+0x4 -+[ ]+8:[ ]+R_LARCH_64_PCREL[ ]+.L1\+0x8 -+[ ]+10:[ ]+R_LARCH_64_PCREL[ ]+.L3\+0x10 -+ -+Disassembly[ ]+of[ ]+section[ ]+sz: -+ -+0*00000000[ ]+: -+[ ]+0:[ ]+00000000[ ]+.word[ ]+0x00000000 -+[ ]+0:[ ]+R_LARCH_ADD32[ ]+.L1 -+[ ]+0:[ ]+R_LARCH_SUB32[ ]+.L2 -+[ ]+4:[ ]+fffffff4[ ]+.word[ ]+0xfffffff4 -+[ ]+... -+[ ]+8:[ ]+R_LARCH_ADD32[ ]+.L3 -+[ ]+8:[ ]+R_LARCH_SUB32[ ]+.L5 -+[ ]+c:[ ]+R_LARCH_ADD64[ ]+.L1 -+[ ]+c:[ ]+R_LARCH_SUB64[ ]+.L2 -+[ ]+14:[ ]+fffffff4[ ]+.word[ ]+0xfffffff4 -+[ ]+18:[ ]+ffffffff[ ]+.word[ ]+0xffffffff -+[ ]+... -+[ ]+1c:[ ]+R_LARCH_ADD64[ ]+.L3 -+[ ]+1c:[ ]+R_LARCH_SUB64[ ]+.L5 -diff --git a/gas/testsuite/gas/loongarch/pcrel_relax.s b/gas/testsuite/gas/loongarch/pcrel_relax.s -new file mode 100644 -index 00000000..ded275fa ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/pcrel_relax.s -@@ -0,0 +1,46 @@ -+ .section .text -+.L1: -+ # 32_pcrel -+ .4byte .L3-.L1 -+ # add32+sub32 -+ .4byte .L3-.L1 -+.L2: -+ # 64_pcrel -+ .8byte .L3-.L2 -+ # add64+sub64 -+ .8byte .L3-.L2 -+ -+ .section sx -+.L3: -+ # no relocation -+ .4byte .L3-.L4 -+ .8byte .L3-.L4 -+.L4: -+ # add32+sub32 -+ .4byte .L4-.L5 -+ # add64+sub64 -+ .8byte .L4-.L5 -+ -+ .section sy -+.L5: -+ # 32_pcrel -+ .4byte .L1-.L5 -+ .4byte .L3-.L5 -+ # 64_pcrel -+ .8byte .L1-.L5 -+ .8byte .L3-.L5 -+ -+ .section sz -+ # add32+sub32 -+ .4byte .L1-.L2 -+ # no relocation -+ .4byte .L3-.L4 -+ # add32+sub32 -+ .4byte .L3-.L5 -+ -+ #add64+sub64 -+ .8byte .L1-.L2 -+ # no relocation -+ .8byte .L3-.L4 -+ #add64+sub64 -+ .8byte .L3-.L5 --- -2.33.0 - diff --git a/Add-testsuits-for-new-assembler-option-of-mthin-add-.patch b/Add-testsuits-for-new-assembler-option-of-mthin-add-.patch deleted file mode 100644 index cbb0ca7..0000000 --- a/Add-testsuits-for-new-assembler-option-of-mthin-add-.patch +++ /dev/null @@ -1,307 +0,0 @@ -From 7904eb84e70187141d105971ff38de06215102cb Mon Sep 17 00:00:00 2001 -From: cailulu -Date: Thu, 28 Sep 2023 16:01:53 +0800 -Subject: [PATCH 012/123] Add testsuits for new assembler option of - mthin-add-sub. - ---- - gas/testsuite/gas/loongarch/no_thin_add_sub.d | 66 +++++++++++++++++++ - gas/testsuite/gas/loongarch/no_thin_add_sub.s | 44 +++++++++++++ - ...pcrel_norelax.d => thin_add_sub_norelax.d} | 25 ++++--- - ...pcrel_norelax.s => thin_add_sub_norelax.s} | 8 +-- - .../{pcrel_relax.d => thin_add_sub_relax.d} | 12 ++-- - .../{pcrel_relax.s => thin_add_sub_relax.s} | 0 - 6 files changed, 131 insertions(+), 24 deletions(-) - create mode 100644 gas/testsuite/gas/loongarch/no_thin_add_sub.d - create mode 100644 gas/testsuite/gas/loongarch/no_thin_add_sub.s - rename gas/testsuite/gas/loongarch/{pcrel_norelax.d => thin_add_sub_norelax.d} (75%) - rename gas/testsuite/gas/loongarch/{pcrel_norelax.s => thin_add_sub_norelax.s} (87%) - rename gas/testsuite/gas/loongarch/{pcrel_relax.d => thin_add_sub_relax.d} (91%) - rename gas/testsuite/gas/loongarch/{pcrel_relax.s => thin_add_sub_relax.s} (100%) - -diff --git a/gas/testsuite/gas/loongarch/no_thin_add_sub.d b/gas/testsuite/gas/loongarch/no_thin_add_sub.d -new file mode 100644 -index 00000000..614aca71 ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/no_thin_add_sub.d -@@ -0,0 +1,66 @@ -+#as: -+#objdump: -Dr -+ -+.*:[ ]+file format .* -+ -+ -+Disassembly of section .text: -+ -+00000000.* <.L1>: -+[ ]+... -+[ ]+0:[ ]+R_LARCH_ADD32[ ]+.L3 -+[ ]+0:[ ]+R_LARCH_SUB32[ ]+.L1 -+[ ]+4:[ ]+R_LARCH_ADD32[ ]+.L3 -+[ ]+4:[ ]+R_LARCH_SUB32[ ]+.L1 -+ -+0*00000008[ ]+<.L2>: -+[ ]+... -+[ ]+8:[ ]+R_LARCH_ADD64[ ]+.L3 -+[ ]+8:[ ]+R_LARCH_SUB64[ ]+.L2 -+[ ]+10:[ ]+R_LARCH_ADD64[ ]+.L3 -+[ ]+10:[ ]+R_LARCH_SUB64[ ]+.L2 -+ -+Disassembly[ ]+of[ ]+section[ ]+sx: -+ -+0*00000000[ ]+<.L3>: -+[ ]+0:[ ]+fffffff4[ ]+.word[ ]+0xfffffff4 -+[ ]+4:[ ]+fffffff4[ ]+.word[ ]+0xfffffff4 -+[ ]+8:[ ]+ffffffff[ ]+.word[ ]+0xffffffff -+ -+0*0000000c[ ]+<.L4>: -+[ ]+... -+[ ]+c:[ ]+R_LARCH_ADD32[ ]+.L4 -+[ ]+c:[ ]+R_LARCH_SUB32[ ]+.L5 -+[ ]+10:[ ]+R_LARCH_ADD64[ ]+.L4 -+[ ]+10:[ ]+R_LARCH_SUB64[ ]+.L5 -+ -+Disassembly[ ]+of[ ]+section[ ]+sy: -+ -+0*00000000[ ]+<.L5>: -+[ ]+... -+[ ]+0:[ ]+R_LARCH_ADD32[ ]+.L1 -+[ ]+0:[ ]+R_LARCH_SUB32[ ]+.L5 -+[ ]+4:[ ]+R_LARCH_ADD32[ ]+.L3 -+[ ]+4:[ ]+R_LARCH_SUB32[ ]+.L5 -+[ ]+8:[ ]+R_LARCH_ADD64[ ]+.L1 -+[ ]+8:[ ]+R_LARCH_SUB64[ ]+.L5 -+[ ]+10:[ ]+R_LARCH_ADD64[ ]+.L3 -+[ ]+10:[ ]+R_LARCH_SUB64[ ]+.L5 -+ -+Disassembly[ ]+of[ ]+section[ ]+sz: -+ -+0*00000000[ ]+: -+[ ]+0:[ ]+00000000[ ]+.word[ ]+0x00000000 -+[ ]+0:[ ]+R_LARCH_ADD32[ ]+.L1 -+[ ]+0:[ ]+R_LARCH_SUB32[ ]+.L2 -+[ ]+4:[ ]+fffffff4[ ]+.word[ ]+0xfffffff4 -+[ ]+... -+[ ]+8:[ ]+R_LARCH_ADD32[ ]+.L3 -+[ ]+8:[ ]+R_LARCH_SUB32[ ]+.L5 -+[ ]+c:[ ]+R_LARCH_ADD64[ ]+.L1 -+[ ]+c:[ ]+R_LARCH_SUB64[ ]+.L2 -+[ ]+14:[ ]+fffffff4[ ]+.word[ ]+0xfffffff4 -+[ ]+18:[ ]+ffffffff[ ]+.word[ ]+0xffffffff -+[ ]+... -+[ ]+1c:[ ]+R_LARCH_ADD64[ ]+.L3 -+[ ]+1c:[ ]+R_LARCH_SUB64[ ]+.L5 -diff --git a/gas/testsuite/gas/loongarch/no_thin_add_sub.s b/gas/testsuite/gas/loongarch/no_thin_add_sub.s -new file mode 100644 -index 00000000..c6801689 ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/no_thin_add_sub.s -@@ -0,0 +1,44 @@ -+ .section .text -+.L1: -+ # add32+sub32 -+ .4byte .L3-.L1 -+ .4byte .L3-.L1 -+.L2: -+ # add64+sub64 -+ .8byte .L3-.L2 -+ .8byte .L3-.L2 -+ -+ .section sx -+.L3: -+ # no relocation -+ .4byte .L3-.L4 -+ .8byte .L3-.L4 -+.L4: -+ # add32+sub32 -+ .4byte .L4-.L5 -+ # add64+sub64 -+ .8byte .L4-.L5 -+ -+ .section sy -+.L5: -+ # add32+sub32 -+ .4byte .L1-.L5 -+ .4byte .L3-.L5 -+ # add64+sub64 -+ .8byte .L1-.L5 -+ .8byte .L3-.L5 -+ -+ .section sz -+ # add32+sub32 -+ .4byte .L1-.L2 -+ # no relocation -+ .4byte .L3-.L4 -+ # add32+sub32 -+ .4byte .L3-.L5 -+ -+ # add64+sub64 -+ .8byte .L1-.L2 -+ # no relocation -+ .8byte .L3-.L4 -+ # add64+sub64 -+ .8byte .L3-.L5 -diff --git a/gas/testsuite/gas/loongarch/pcrel_norelax.d b/gas/testsuite/gas/loongarch/thin_add_sub_norelax.d -similarity index 75% -rename from gas/testsuite/gas/loongarch/pcrel_norelax.d -rename to gas/testsuite/gas/loongarch/thin_add_sub_norelax.d -index 842c8d48..702093b6 100644 ---- a/gas/testsuite/gas/loongarch/pcrel_norelax.d -+++ b/gas/testsuite/gas/loongarch/thin_add_sub_norelax.d -@@ -1,4 +1,4 @@ --#as: -mno-relax -+#as: -mthin-add-sub -mno-relax - #objdump: -Dr - - .*:[ ]+file format .* -@@ -10,20 +10,17 @@ Disassembly of section .text: - [ ]+... - [ ]+0:[ ]+R_LARCH_32_PCREL[ ]+.L3 - [ ]+4:[ ]+R_LARCH_32_PCREL[ ]+.L3\+0x4 -- --0*00000008[ ]+<.L2>: --[ ]+... - [ ]+8:[ ]+R_LARCH_64_PCREL[ ]+.L3 - [ ]+10:[ ]+R_LARCH_64_PCREL[ ]+.L3\+0x8 - - Disassembly[ ]+of[ ]+section[ ]+sx: - --0*00000000[ ]+<.L3>: -+0*00000000[ ]+<.L3>: - [ ]+0:[ ]+fffffff4[ ]+.word[ ]+0xfffffff4 - [ ]+4:[ ]+fffffff4[ ]+.word[ ]+0xfffffff4 - [ ]+8:[ ]+ffffffff[ ]+.word[ ]+0xffffffff - --0*0000000c[ ]+<.L4>: -+0*0000000c[ ]+<.L4>: - [ ]+... - [ ]+c:[ ]+R_LARCH_ADD32[ ]+.L4 - [ ]+c:[ ]+R_LARCH_SUB32[ ]+.L5 -@@ -32,25 +29,25 @@ Disassembly[ ]+of[ ]+section[ ]+sx: - - Disassembly[ ]+of[ ]+section[ ]+sy: - --0*00000000[ ]+<.L5>: -+0*00000000[ ]+<.L5>: - [ ]+... - [ ]+0:[ ]+R_LARCH_32_PCREL[ ]+.L1 --[ ]+4:[ ]+R_LARCH_32_PCREL[ ]+.L2\+0x4 -+[ ]+4:[ ]+R_LARCH_32_PCREL[ ]+.L3\+0x4 - [ ]+8:[ ]+R_LARCH_64_PCREL[ ]+.L1\+0x8 --[ ]+10:[ ]+R_LARCH_64_PCREL[ ]+.L2\+0x10 -+[ ]+10:[ ]+R_LARCH_64_PCREL[ ]+.L3\+0x10 - - Disassembly[ ]+of[ ]+section[ ]+sz: - --0*00000000[ ]+: -+0*00000000[ ]+: - [ ]+0:[ ]+fffffff8[ ]+.word[ ]+0xfffffff8 - [ ]+4:[ ]+fffffff4[ ]+.word[ ]+0xfffffff4 - [ ]+8:[ ]+00000000[ ]+.word[ ]+0x00000000 --[ ]+8:[ ]+R_LARCH_ADD32[ ]+.L2 --[ ]+8:[ ]+R_LARCH_SUB32[ ]+.L3 -+[ ]+8:[ ]+R_LARCH_ADD32[ ]+.L3 -+[ ]+8:[ ]+R_LARCH_SUB32[ ]+.L5 - [ ]+c:[ ]+fffffff8[ ]+.word[ ]+0xfffffff8 - [ ]+10:[ ]+ffffffff[ ]+.word[ ]+0xffffffff - [ ]+14:[ ]+fffffff4[ ]+.word[ ]+0xfffffff4 - [ ]+18:[ ]+ffffffff[ ]+.word[ ]+0xffffffff - [ ]+... --[ ]+1c:[ ]+R_LARCH_ADD64[ ]+.L2 --[ ]+1c:[ ]+R_LARCH_SUB64[ ]+.L3 -+[ ]+1c:[ ]+R_LARCH_ADD64[ ]+.L3 -+[ ]+1c:[ ]+R_LARCH_SUB64[ ]+.L5 -diff --git a/gas/testsuite/gas/loongarch/pcrel_norelax.s b/gas/testsuite/gas/loongarch/thin_add_sub_norelax.s -similarity index 87% -rename from gas/testsuite/gas/loongarch/pcrel_norelax.s -rename to gas/testsuite/gas/loongarch/thin_add_sub_norelax.s -index 09527f14..94cfd908 100644 ---- a/gas/testsuite/gas/loongarch/pcrel_norelax.s -+++ b/gas/testsuite/gas/loongarch/thin_add_sub_norelax.s -@@ -23,20 +23,20 @@ - .L5: - # 32_pcrel - .4byte .L1-.L5 -- .4byte .L2-.L5 -+ .4byte .L3-.L5 - # 64_pcrel - .8byte .L1-.L5 -- .8byte .L2-.L5 -+ .8byte .L3-.L5 - - .section sz - # no relocation - .4byte .L1-.L2 - .4byte .L3-.L4 - # add32+sub32 -- .4byte .L2-.L3 -+ .4byte .L3-.L5 - - # no relocation - .8byte .L1-.L2 - .8byte .L3-.L4 - # add64+sub64 -- .8byte .L2-.L3 -+ .8byte .L3-.L5 -diff --git a/gas/testsuite/gas/loongarch/pcrel_relax.d b/gas/testsuite/gas/loongarch/thin_add_sub_relax.d -similarity index 91% -rename from gas/testsuite/gas/loongarch/pcrel_relax.d -rename to gas/testsuite/gas/loongarch/thin_add_sub_relax.d -index d6f87525..9455c3e6 100644 ---- a/gas/testsuite/gas/loongarch/pcrel_relax.d -+++ b/gas/testsuite/gas/loongarch/thin_add_sub_relax.d -@@ -1,4 +1,4 @@ --#as: -+#as: -mthin-add-sub - #objdump: -Dr - - .*:[ ]+file format .* -@@ -12,7 +12,7 @@ Disassembly of section .text: - [ ]+4:[ ]+R_LARCH_ADD32[ ]+.L3 - [ ]+4:[ ]+R_LARCH_SUB32[ ]+.L1 - --0*00000008[ ]+<.L2>: -+0*00000008[ ]+<.L2>: - [ ]+... - [ ]+8:[ ]+R_LARCH_64_PCREL[ ]+.L3 - [ ]+10:[ ]+R_LARCH_ADD64[ ]+.L3 -@@ -20,12 +20,12 @@ Disassembly of section .text: - - Disassembly[ ]+of[ ]+section[ ]+sx: - --0*00000000[ ]+<.L3>: -+0*00000000[ ]+<.L3>: - [ ]+0:[ ]+fffffff4[ ]+.word[ ]+0xfffffff4 - [ ]+4:[ ]+fffffff4[ ]+.word[ ]+0xfffffff4 - [ ]+8:[ ]+ffffffff[ ]+.word[ ]+0xffffffff - --0*0000000c[ ]+<.L4>: -+0*0000000c[ ]+<.L4>: - [ ]+... - [ ]+c:[ ]+R_LARCH_ADD32[ ]+.L4 - [ ]+c:[ ]+R_LARCH_SUB32[ ]+.L5 -@@ -34,7 +34,7 @@ Disassembly[ ]+of[ ]+section[ ]+sx: - - Disassembly[ ]+of[ ]+section[ ]+sy: - --0*00000000[ ]+<.L5>: -+0*00000000[ ]+<.L5>: - [ ]+... - [ ]+0:[ ]+R_LARCH_32_PCREL[ ]+.L1 - [ ]+4:[ ]+R_LARCH_32_PCREL[ ]+.L3\+0x4 -@@ -43,7 +43,7 @@ Disassembly[ ]+of[ ]+section[ ]+sy: - - Disassembly[ ]+of[ ]+section[ ]+sz: - --0*00000000[ ]+: -+0*00000000[ ]+: - [ ]+0:[ ]+00000000[ ]+.word[ ]+0x00000000 - [ ]+0:[ ]+R_LARCH_ADD32[ ]+.L1 - [ ]+0:[ ]+R_LARCH_SUB32[ ]+.L2 -diff --git a/gas/testsuite/gas/loongarch/pcrel_relax.s b/gas/testsuite/gas/loongarch/thin_add_sub_relax.s -similarity index 100% -rename from gas/testsuite/gas/loongarch/pcrel_relax.s -rename to gas/testsuite/gas/loongarch/thin_add_sub_relax.s --- -2.33.0 - diff --git a/Avoid-unused-space-in-.rela.dyn-if-sec-was-discarded.patch b/Avoid-unused-space-in-.rela.dyn-if-sec-was-discarded.patch deleted file mode 100644 index c1d1fda..0000000 --- a/Avoid-unused-space-in-.rela.dyn-if-sec-was-discarded.patch +++ /dev/null @@ -1,102 +0,0 @@ -From 79505ef8b8ccd844aee06cab4aec2404fb5e4475 Mon Sep 17 00:00:00 2001 -From: Jinyang He -Date: Fri, 15 Sep 2023 11:52:14 +0800 -Subject: [PATCH 060/123] Avoid unused space in .rela.dyn if sec was discarded - -The relsec size is still increased although sec is discarded, which -cause a lot of unused space allocated. Avoid size increased if sec -was discarded. - -bfd/ChangeLog: - - * bfd/elfnn-loongarch.c: (allocate_dynrelocs): Do not increase - sreloc size when discarded_section. - -ld/ChangeLog: - - * ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp: Add test. - * ld/testsuite/ld-loongarch-elf/pie_discard.d: New test. - * ld/testsuite/ld-loongarch-elf/pie_discard.s: New test. - * ld/testsuite/ld-loongarch-elf/pie_discard.t: New test. ---- - bfd/elfnn-loongarch.c | 2 ++ - ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp | 1 + - ld/testsuite/ld-loongarch-elf/pie_discard.d | 10 ++++++++++ - ld/testsuite/ld-loongarch-elf/pie_discard.s | 9 +++++++++ - ld/testsuite/ld-loongarch-elf/pie_discard.t | 9 +++++++++ - 5 files changed, 31 insertions(+) - create mode 100644 ld/testsuite/ld-loongarch-elf/pie_discard.d - create mode 100644 ld/testsuite/ld-loongarch-elf/pie_discard.s - create mode 100644 ld/testsuite/ld-loongarch-elf/pie_discard.t - -diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c -index 2e72fe5c..1693ad7e 100644 ---- a/bfd/elfnn-loongarch.c -+++ b/bfd/elfnn-loongarch.c -@@ -1368,6 +1368,8 @@ allocate_dynrelocs (struct elf_link_hash_entry *h, void *inf) - - for (p = h->dyn_relocs; p != NULL; p = p->next) - { -+ if (discarded_section (p->sec)) -+ continue; - asection *sreloc = elf_section_data (p->sec)->sreloc; - sreloc->size += p->count * sizeof (ElfNN_External_Rela); - } -diff --git a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -index 7fc43d41..b3029e53 100644 ---- a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -+++ b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -@@ -147,3 +147,4 @@ run_dump_test "underflow_b16" - run_dump_test "underflow_b21" - run_dump_test "underflow_b26" - run_dump_test "underflow_pcrel20" -+run_dump_test "pie_discard" -diff --git a/ld/testsuite/ld-loongarch-elf/pie_discard.d b/ld/testsuite/ld-loongarch-elf/pie_discard.d -new file mode 100644 -index 00000000..7b863091 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/pie_discard.d -@@ -0,0 +1,10 @@ -+#source: pie_discard.s -+#ld: -pie -e 0 -T pie_discard.t -+#readelf: -rW -+ -+#... -+Relocation section '\.rela\.dyn' .* 1 .* -+#... -+.*R_LARCH_RELATIVE.* -+#pass -+ -diff --git a/ld/testsuite/ld-loongarch-elf/pie_discard.s b/ld/testsuite/ld-loongarch-elf/pie_discard.s -new file mode 100644 -index 00000000..82b88fc1 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/pie_discard.s -@@ -0,0 +1,9 @@ -+ .text -+ .global sym -+sym: nop -+ -+ .section .data,"aw" -+ .dword sym -+ -+ .section .discard,"aw" -+ .dword sym -diff --git a/ld/testsuite/ld-loongarch-elf/pie_discard.t b/ld/testsuite/ld-loongarch-elf/pie_discard.t -new file mode 100644 -index 00000000..49e52cdb ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/pie_discard.t -@@ -0,0 +1,9 @@ -+SECTIONS -+{ -+ . = SEGMENT_START("text-segment", 0) + SIZEOF_HEADERS; -+ .rela.dyn : { *(.rela.*) } -+ .text : { *(.text) } -+ . = DATA_SEGMENT_ALIGN (CONSTANT (MAXPAGESIZE), CONSTANT (COMMONPAGESIZE)); -+ .data : { *(.data) } -+ /DISCARD/ : { *(.discard) } -+} --- -2.33.0 - diff --git a/BFD-Fix-the-bug-of-R_LARCH_AGLIN-caused-by-discard-s.patch b/BFD-Fix-the-bug-of-R_LARCH_AGLIN-caused-by-discard-s.patch deleted file mode 100644 index c3527ac..0000000 --- a/BFD-Fix-the-bug-of-R_LARCH_AGLIN-caused-by-discard-s.patch +++ /dev/null @@ -1,226 +0,0 @@ -From aef05e9e774983b4d4a5a08ab7e172e1e678eff5 Mon Sep 17 00:00:00 2001 -From: mengqinggang -Date: Wed, 24 Jan 2024 14:34:26 +0800 -Subject: [PATCH 075/123] BFD: Fix the bug of R_LARCH_AGLIN caused by discard - section - -To represent the first and third expression of .align, R_LARCH_ALIGN need to -associate with a symbol. We define a local symbol for R_LARCH_AGLIN. -But if the section of the local symbol is discarded, it may result in -a undefined symbol error. - -Instead, we use the section name symbols, and this does not need to -add extra symbols. - -During partial linking (ld -r), if the symbol associated with a relocation is -STT_SECTION type, the addend of relocation needs to add the section output -offset. We prevent it for R_LARCH_ALIGN. - -The elf_backend_data.rela_normal only can set all relocations of a target to -rela_normal. Add a new function is_rela_normal to elf_backend_data, it can -set part of relocations to rela_normal. ---- - bfd/elf-bfd.h | 4 ++++ - bfd/elflink.c | 5 ++++- - bfd/elfnn-loongarch.c | 16 ++++++++++++++++ - bfd/elfxx-target.h | 5 +++++ - gas/config/tc-loongarch.c | 5 +---- - gas/testsuite/gas/loongarch/relax_align.d | 6 +++--- - .../ld-loongarch-elf/relax-align-discard.lds | 4 ++++ - .../ld-loongarch-elf/relax-align-discard.s | 17 +++++++++++++++++ - ld/testsuite/ld-loongarch-elf/relax.exp | 12 ++++++++++++ - 9 files changed, 66 insertions(+), 8 deletions(-) - create mode 100644 ld/testsuite/ld-loongarch-elf/relax-align-discard.lds - create mode 100644 ld/testsuite/ld-loongarch-elf/relax-align-discard.s - -diff --git a/bfd/elf-bfd.h b/bfd/elf-bfd.h -index ec856764..074120a5 100644 ---- a/bfd/elf-bfd.h -+++ b/bfd/elf-bfd.h -@@ -1703,6 +1703,10 @@ struct elf_backend_data - backend relocate_section routine for relocatable linking. */ - unsigned rela_normal : 1; - -+ /* Whether a relocation is rela_normal. Compared with rela_normal, -+ is_rela_normal can set part of relocations to rela_normal. */ -+ bool (*is_rela_normal) (Elf_Internal_Rela *); -+ - /* Set if DT_REL/DT_RELA/DT_RELSZ/DT_RELASZ should not include PLT - relocations. */ - unsigned dtrel_excludes_plt : 1; -diff --git a/bfd/elflink.c b/bfd/elflink.c -index 7217c2f0..cbf87d70 100644 ---- a/bfd/elflink.c -+++ b/bfd/elflink.c -@@ -11647,7 +11647,10 @@ elf_link_input_bfd (struct elf_final_link_info *flinfo, bfd *input_bfd) - { - rel_hash = PTR_ADD (esdo->rela.hashes, esdo->rela.count); - rela_hash_list = rel_hash; -- rela_normal = bed->rela_normal; -+ if (bed->is_rela_normal != NULL) -+ rela_normal = bed->is_rela_normal (irela); -+ else -+ rela_normal = bed->rela_normal; - } - - irela->r_offset = _bfd_elf_section_offset (output_bfd, -diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c -index 1c3295f4..f6975957 100644 ---- a/bfd/elfnn-loongarch.c -+++ b/bfd/elfnn-loongarch.c -@@ -5454,6 +5454,21 @@ elf_loongarch64_hash_symbol (struct elf_link_hash_entry *h) - return _bfd_elf_hash_symbol (h); - } - -+/* If a relocation is rela_normal and the symbol associated with the -+ relocation is STT_SECTION type, the addend of the relocation would add -+ sec->output_offset when partial linking (ld -r). -+ See elf_backend_data.rela_normal and elf_link_input_bfd(). -+ The addend of R_LARCH_ALIGN is used to represent the first and third -+ expression of .align, it should be a constant when linking. */ -+ -+static bool -+loongarch_elf_is_rela_normal (Elf_Internal_Rela *rel) -+{ -+ if (R_LARCH_ALIGN == ELFNN_R_TYPE (rel->r_info)) -+ return false; -+ return true; -+} -+ - #define TARGET_LITTLE_SYM loongarch_elfNN_vec - #define TARGET_LITTLE_NAME "elfNN-loongarch" - #define ELF_ARCH bfd_arch_loongarch -@@ -5489,6 +5504,7 @@ elf_loongarch64_hash_symbol (struct elf_link_hash_entry *h) - #define elf_backend_grok_psinfo loongarch_elf_grok_psinfo - #define elf_backend_hash_symbol elf_loongarch64_hash_symbol - #define bfd_elfNN_bfd_relax_section loongarch_elf_relax_section -+#define elf_backend_is_rela_normal loongarch_elf_is_rela_normal - - #define elf_backend_dtrel_excludes_plt 1 - -diff --git a/bfd/elfxx-target.h b/bfd/elfxx-target.h -index f8553006..385e40b7 100644 ---- a/bfd/elfxx-target.h -+++ b/bfd/elfxx-target.h -@@ -703,6 +703,10 @@ - #define elf_backend_rela_normal 0 - #endif - -+#ifndef elf_backend_is_rela_normal -+#define elf_backend_is_rela_normal NULL -+#endif -+ - #ifndef elf_backend_dtrel_excludes_plt - #define elf_backend_dtrel_excludes_plt 0 - #endif -@@ -948,6 +952,7 @@ static const struct elf_backend_data elfNN_bed = - elf_backend_default_use_rela_p, - elf_backend_rela_plts_and_copies_p, - elf_backend_rela_normal, -+ elf_backend_is_rela_normal, - elf_backend_dtrel_excludes_plt, - elf_backend_sign_extend_vma, - elf_backend_want_got_plt, -diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c -index 51575757..1e835f51 100644 ---- a/gas/config/tc-loongarch.c -+++ b/gas/config/tc-loongarch.c -@@ -1791,10 +1791,7 @@ loongarch_frag_align_code (int n, int max) - if (fragP->fr_subtype != 0 && offset > fragP->fr_subtype). */ - if (max > 0 && (bfd_vma) max < worst_case_bytes) - { -- s = symbol_find (".Lla-relax-align"); -- if (s == NULL) -- s = (symbolS *)local_symbol_make (".Lla-relax-align", now_seg, -- &zero_address_frag, 0); -+ s = symbol_find (now_seg->name); - ex.X_add_symbol = s; - ex.X_op = O_symbol; - ex.X_add_number = (max << 8) | n; -diff --git a/gas/testsuite/gas/loongarch/relax_align.d b/gas/testsuite/gas/loongarch/relax_align.d -index fc1fd032..acd215a4 100644 ---- a/gas/testsuite/gas/loongarch/relax_align.d -+++ b/gas/testsuite/gas/loongarch/relax_align.d -@@ -7,7 +7,7 @@ - - Disassembly of section .text: - --[ ]*0000000000000000 <.Lla-relax-align>: -+[ ]*0000000000000000 <.text>: - [ ]+0:[ ]+4c000020[ ]+ret - [ ]+4:[ ]+03400000[ ]+nop - [ ]+4: R_LARCH_ALIGN[ ]+\*ABS\*\+0xc -@@ -20,12 +20,12 @@ Disassembly of section .text: - [ ]+1c:[ ]+03400000[ ]+nop - [ ]+20:[ ]+4c000020[ ]+ret - [ ]+24:[ ]+03400000[ ]+nop --[ ]+24: R_LARCH_ALIGN[ ]+.Lla-relax-align\+0x104 -+[ ]+24: R_LARCH_ALIGN[ ]+.text\+0x104 - [ ]+28:[ ]+03400000[ ]+nop - [ ]+2c:[ ]+03400000[ ]+nop - [ ]+30:[ ]+4c000020[ ]+ret - [ ]+34:[ ]+03400000[ ]+nop --[ ]+34: R_LARCH_ALIGN[ ]+.Lla-relax-align\+0xb04 -+[ ]+34: R_LARCH_ALIGN[ ]+.text\+0xb04 - [ ]+38:[ ]+03400000[ ]+nop - [ ]+3c:[ ]+03400000[ ]+nop - [ ]+40:[ ]+4c000020[ ]+ret -diff --git a/ld/testsuite/ld-loongarch-elf/relax-align-discard.lds b/ld/testsuite/ld-loongarch-elf/relax-align-discard.lds -new file mode 100644 -index 00000000..4a81323d ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/relax-align-discard.lds -@@ -0,0 +1,4 @@ -+SECTIONS -+{ -+ /DISCARD/ : { *(.another.*) } -+} -diff --git a/ld/testsuite/ld-loongarch-elf/relax-align-discard.s b/ld/testsuite/ld-loongarch-elf/relax-align-discard.s -new file mode 100644 -index 00000000..b65d63f3 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/relax-align-discard.s -@@ -0,0 +1,17 @@ -+# Use the section name symbol for R_LARCH_ALIGN to avoid discard section problem -+.section ".another.text", "ax" -+.cfi_startproc -+break 0 -+.cfi_def_cfa_offset 16 -+.p2align 5 -+break 1 -+.cfi_endproc -+ -+.text -+.cfi_startproc -+break 0 -+.cfi_def_cfa_offset 16 -+.p2align 5 -+break 1 -+.cfi_endproc -+ -diff --git a/ld/testsuite/ld-loongarch-elf/relax.exp b/ld/testsuite/ld-loongarch-elf/relax.exp -index bca3e1bd..f378b93b 100644 ---- a/ld/testsuite/ld-loongarch-elf/relax.exp -+++ b/ld/testsuite/ld-loongarch-elf/relax.exp -@@ -295,6 +295,18 @@ if [istarget loongarch64-*-*] { - "relax-align" \ - ] \ - ] -+ -+ run_ld_link_tests \ -+ [list \ -+ [list \ -+ "loongarch relax align discard" \ -+ "-e 0x0 -T relax-align-discard.lds -r" "" \ -+ "" \ -+ {relax-align-discard.s} \ -+ {} \ -+ "relax-align-discard" \ -+ ] \ -+ ] - } - - set objdump_flags "-s -j .data" --- -2.33.0 - diff --git a/Fix-building-Loongarch-BFD-with-a-32-bit-compiler.patch b/Fix-building-Loongarch-BFD-with-a-32-bit-compiler.patch deleted file mode 100644 index 5857241..0000000 --- a/Fix-building-Loongarch-BFD-with-a-32-bit-compiler.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 6a455ac82af2d8f5989f71df38f6e779ae202a48 Mon Sep 17 00:00:00 2001 -From: Nick Clifton -Date: Mon, 29 Apr 2024 09:02:43 +0100 -Subject: [PATCH 084/123] Fix building Loongarch BFD with a 32-bit compiler - ---- - bfd/elfnn-loongarch.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c -index ee708c7f..47fd08cd 100644 ---- a/bfd/elfnn-loongarch.c -+++ b/bfd/elfnn-loongarch.c -@@ -782,7 +782,7 @@ bad_static_reloc (bfd *abfd, const Elf_Internal_Rela *rel, asection *sec, - (*_bfd_error_handler) - (_("%pB:(%pA+%#lx): relocation %s against `%s` can not be used when making " - "a shared object; recompile with -fPIC"), -- abfd, sec, rel->r_offset, r ? r->name : _(""), name); -+ abfd, sec, (long) rel->r_offset, r ? r->name : _(""), name); - bfd_set_error (bfd_error_bad_value); - return false; - } --- -2.33.0 - diff --git a/Fix-gold-linker-relocation-offset.patch b/Fix-gold-linker-relocation-offset.patch deleted file mode 100644 index 4ff9ee9..0000000 --- a/Fix-gold-linker-relocation-offset.patch +++ /dev/null @@ -1,52 +0,0 @@ -From 3d84bd3df6cd5741b575cb454933a3c414c4a5d5 Mon Sep 17 00:00:00 2001 -From: wangding16 -Date: Sun, 25 Aug 2024 16:51:53 +0800 -Subject: [PATCH] Fix gold linker relocation offset - -Reference: https://sourceware.org/git/?p=binutils-gdb.git;a=commitdiff;h=c441a361287ca98aa7a4ac1ff02d12d138b289dc - ---- - gold/aarch64.cc | 20 ++++++++++++++++++++ - 1 file changed, 20 insertions(+) - -diff --git a/gold/aarch64.cc b/gold/aarch64.cc -index 7f95c0cf..6004118a 100644 ---- a/gold/aarch64.cc -+++ b/gold/aarch64.cc -@@ -2916,6 +2916,7 @@ class Target_aarch64 : public Sized_target - Section_id_hash> AArch64_input_section_map; - typedef AArch64_insn_utilities Insn_utilities; - const static int TCB_SIZE = size / 8 * 2; -+ static const Address invalid_address = static_cast
(-1); - - Target_aarch64(const Target::Target_info* info = &aarch64_info) - : Sized_target(info), -@@ -8286,6 +8287,25 @@ Target_aarch64::relocate_relocs( - - gold_assert(sh_type == elfcpp::SHT_RELA); - -+ if (offset_in_output_section == this->invalid_address) { -+ const Output_relaxed_input_section* poris = -+ output_section->find_relaxed_input_section(relinfo->object, -+ relinfo->data_shndx); -+ if (poris != NULL) { -+ Address section_address = poris->address(); -+ section_size_type section_size = poris->data_size(); -+ -+ gold_assert(section_address >= view_address -+ && (section_address + section_size -+ <= view_address + view_size)); -+ -+ off_t offset = section_address - view_address; -+ view += offset; -+ view_address += offset; -+ view_size = section_size; -+ } -+ } -+ - gold::relocate_relocs( - relinfo, - prelocs, --- -2.23.0 - diff --git a/Fix-slowdown-about-partial-linking.patch b/Fix-slowdown-about-partial-linking.patch deleted file mode 100644 index 45aac57..0000000 --- a/Fix-slowdown-about-partial-linking.patch +++ /dev/null @@ -1,138 +0,0 @@ -From 97eea7a09e8c7c72a763e21608a52cc0e07e3fc6 Mon Sep 17 00:00:00 2001 -From: Xin Wang -Date: Mon, 20 Jan 2025 14:46:44 +0800 -Subject: [PATCH] Fix slowdown about partial linking - ---- - ld/ldlang.c | 66 ++++++++++++++++++++++++++++++++++++----------------- - 1 file changed, 45 insertions(+), 21 deletions(-) - -diff --git a/ld/ldlang.c b/ld/ldlang.c -index a357f802..3b6b8563 100644 ---- a/ld/ldlang.c -+++ b/ld/ldlang.c -@@ -1246,6 +1246,7 @@ struct out_section_hash_entry - { - struct bfd_hash_entry root; - lang_statement_union_type s; -+ struct out_section_hash_entry *tail; - }; - - /* The hash table. */ -@@ -1255,10 +1256,10 @@ static struct bfd_hash_table output_section_statement_table; - /* Support routines for the hash table used by lang_output_section_find, - initialize the table, fill in an entry and remove the table. */ - --static struct bfd_hash_entry * --output_section_statement_newfunc (struct bfd_hash_entry *entry, -- struct bfd_hash_table *table, -- const char *string) -+static struct out_section_hash_entry * -+output_section_statement_newfunc_1 (struct bfd_hash_entry *entry, -+ struct bfd_hash_table *table, -+ const char *string) - { - lang_output_section_statement_type **nextp; - struct out_section_hash_entry *ret; -@@ -1268,12 +1269,12 @@ output_section_statement_newfunc (struct bfd_hash_entry *entry, - entry = (struct bfd_hash_entry *) bfd_hash_allocate (table, - sizeof (*ret)); - if (entry == NULL) -- return entry; -+ return NULL; - } - - entry = bfd_hash_newfunc (entry, table, string); - if (entry == NULL) -- return entry; -+ return NULL; - - ret = (struct out_section_hash_entry *) entry; - memset (&ret->s, 0, sizeof (ret->s)); -@@ -1298,6 +1299,20 @@ output_section_statement_newfunc (struct bfd_hash_entry *entry, - instead. */ - nextp = &ret->s.output_section_statement.next; - lang_statement_append (&lang_os_list, &ret->s, nextp); -+ return ret; -+} -+ -+static struct bfd_hash_entry * -+output_section_statement_newfunc (struct bfd_hash_entry *entry, -+ struct bfd_hash_table *table, -+ const char *string) -+{ -+ struct out_section_hash_entry *ret; -+ -+ ret = output_section_statement_newfunc_1 (entry, table, string); -+ if (ret == NULL) -+ return NULL; -+ ret->tail = ret; - return &ret->root; - } - -@@ -1523,31 +1538,39 @@ lang_output_section_statement_lookup (const char *name, - { - /* We have a section of this name, but it might not have the correct - constraint. */ -+ struct out_section_hash_entry *first_ent = entry; - struct out_section_hash_entry *last_ent; - - name = entry->s.output_section_statement.name; -- do -+ if (create != 2 -+ && !(create && constraint == SPECIAL)) - { -- if (create != 2 -- && !(create && constraint == SPECIAL) -- && (constraint == entry->s.output_section_statement.constraint -+ do -+ { -+ if (constraint == entry->s.output_section_statement.constraint - || (constraint == 0 -- && entry->s.output_section_statement.constraint >= 0))) -- return &entry->s.output_section_statement; -- last_ent = entry; -- entry = (struct out_section_hash_entry *) entry->root.next; -+ && entry->s.output_section_statement.constraint >= 0)) -+ return &entry->s.output_section_statement; -+ last_ent = entry; -+ entry = (struct out_section_hash_entry *) entry->root.next; -+ } -+ while (entry != NULL -+ && name == entry->s.output_section_statement.name); - } -- while (entry != NULL -- && name == entry->s.output_section_statement.name); -+ else -+ last_ent = first_ent->tail; - - if (!create) - return NULL; - -- entry -- = ((struct out_section_hash_entry *) -- output_section_statement_newfunc (NULL, -- &output_section_statement_table, -- name)); -+ /* Only the first entry needs the tail pointer. */ -+ entry = bfd_hash_allocate (&output_section_statement_table, -+ offsetof (struct out_section_hash_entry, tail)); -+ if (entry != NULL) -+ entry -+ = output_section_statement_newfunc_1 (&entry->root, -+ &output_section_statement_table, -+ name); - if (entry == NULL) - { - einfo (_("%F%P: failed creating section `%s': %E\n"), name); -@@ -1555,6 +1578,7 @@ lang_output_section_statement_lookup (const char *name, - } - entry->root = last_ent->root; - last_ent->root.next = &entry->root; -+ first_ent->tail = entry; - } - - entry->s.output_section_statement.name = name; --- -2.33.0 - diff --git a/Include-ldlex.h-when-compile-eelfxxloongarch.c.patch b/Include-ldlex.h-when-compile-eelfxxloongarch.c.patch deleted file mode 100644 index 0264688..0000000 --- a/Include-ldlex.h-when-compile-eelfxxloongarch.c.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 00f4bdc23c28986e4bdff1385ab7c6456fe74a6a Mon Sep 17 00:00:00 2001 -From: Xin Wang -Date: Thu, 24 Oct 2024 16:45:16 +0800 -Subject: [PATCH 120/123] Include ldlex.h when compile eelfxxloongarch.c We did - not cherry-pick 8d10083c23b9415a6d645b44d136104fcf8ed176 of upstream:master - because that modified files which are not related to LoongArch - ---- - ld/emultempl/loongarchelf.em | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/ld/emultempl/loongarchelf.em b/ld/emultempl/loongarchelf.em -index 2e6b8080..e50d85d0 100644 ---- a/ld/emultempl/loongarchelf.em -+++ b/ld/emultempl/loongarchelf.em -@@ -24,6 +24,7 @@ fragment < -Date: Mon, 7 Aug 2023 13:07:05 +0200 -Subject: [PATCH 003/123] Libvtv: Add loongarch support. - -The loongarch64 specification permits page sizes of 4KiB, 16KiB and 64KiB, -but only 16KiB pages are supported for now. - -Co-Authored-By: qijingwen - -include/ - * vtv-change-permission.h (defined): Determines whether the macro - __loongarch_lp64 is defined - (VTV_PAGE_SIZE): Set VTV_PAGE_SIZE to 16KiB for loongarch64. ---- - include/vtv-change-permission.h | 4 ++++ - 1 file changed, 4 insertions(+) - -diff --git a/include/vtv-change-permission.h b/include/vtv-change-permission.h -index 5906e7d7..ffb53125 100644 ---- a/include/vtv-change-permission.h -+++ b/include/vtv-change-permission.h -@@ -48,6 +48,10 @@ extern void __VLTChangePermission (int); - #else - #if defined(__sun__) && defined(__svr4__) && defined(__sparc__) - #define VTV_PAGE_SIZE 8192 -+#elif defined(__loongarch_lp64) -+/* The page size is configurable by the kernel to be 4, 16 or 64 KiB. -+ For now, only the default page size of 16KiB is supported. */ -+#define VTV_PAGE_SIZE 16384 - #else - #define VTV_PAGE_SIZE 4096 - #endif --- -2.33.0 - diff --git a/LoongArch-Adapt-R_LARCH_-PCALA-GOT-TLS_IE-TLS_DESC-6.patch b/LoongArch-Adapt-R_LARCH_-PCALA-GOT-TLS_IE-TLS_DESC-6.patch deleted file mode 100644 index f16db1a..0000000 --- a/LoongArch-Adapt-R_LARCH_-PCALA-GOT-TLS_IE-TLS_DESC-6.patch +++ /dev/null @@ -1,155 +0,0 @@ -From 2a9dd993a723726ccc6f5cfb4119ab6c8637c0d0 Mon Sep 17 00:00:00 2001 -From: Xi Ruoyao -Date: Tue, 16 Jan 2024 15:00:16 +0800 -Subject: [PATCH 044/123] LoongArch: Adapt - R_LARCH_{PCALA,GOT,TLS_IE,TLS_DESC}64_* handling per psABI v2.30 - -In LoongArch psABI v2.30, an offset (-8 for LO20 and -12 for HI12) -should be applied on PC for these reloc types to avoid wrong relocation -when the instruction sequence crosses a page boundary. - -The lld linker has already adapted the change. Make it for the bfd -linker too. - -Link: https://github.com/loongson/la-abi-specs/releases/v2.30 -Link: https://github.com/loongson-community/discussions/issues/17 -Link: https://github.com/llvm/llvm-project/pull/73387 -Signed-off-by: Xi Ruoyao ---- - bfd/elfnn-loongarch.c | 31 +++++++++++-------- - .../ld-loongarch-elf/ld-loongarch-elf.exp | 1 + - ld/testsuite/ld-loongarch-elf/pcala64.d | 15 +++++++++ - ld/testsuite/ld-loongarch-elf/pcala64.s | 8 +++++ - 4 files changed, 42 insertions(+), 13 deletions(-) - create mode 100644 ld/testsuite/ld-loongarch-elf/pcala64.d - create mode 100644 ld/testsuite/ld-loongarch-elf/pcala64.s - -diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c -index 8b71e836..b0ebe89e 100644 ---- a/bfd/elfnn-loongarch.c -+++ b/bfd/elfnn-loongarch.c -@@ -2529,7 +2529,7 @@ loongarch_reloc_is_fatal (struct bfd_link_info *info, - ({ \ - bfd_vma __lo = (relocation & (bfd_vma)0xfff); \ - relocation = (relocation & ~(bfd_vma)0xfff) \ -- - (pc & ~(bfd_vma)0xfff); \ -+ - ((pc) & ~(bfd_vma)0xfff); \ - if (__lo > 0x7ff) \ - relocation += (0x1000 - 0x100000000); \ - if (relocation & 0x80000000) \ -@@ -3527,14 +3527,16 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, - } - break; - -- case R_LARCH_PCALA64_LO20: - case R_LARCH_PCALA64_HI12: -+ pc -= 4; -+ /* Fall through. */ -+ case R_LARCH_PCALA64_LO20: - if (h && h->plt.offset != MINUS_ONE) - relocation = sec_addr (plt) + h->plt.offset; - else - relocation += rel->r_addend; - -- RELOCATE_CALC_PC64_HI32 (relocation, pc); -+ RELOCATE_CALC_PC64_HI32 (relocation, pc - 8); - - break; - -@@ -3661,9 +3663,10 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, - relocation = got_off + sec_addr (got); - } - -- if (r_type == R_LARCH_GOT64_PC_HI12 -- || r_type == R_LARCH_GOT64_PC_LO20) -- RELOCATE_CALC_PC64_HI32 (relocation, pc); -+ if (r_type == R_LARCH_GOT64_PC_HI12) -+ RELOCATE_CALC_PC64_HI32 (relocation, pc - 12); -+ else if (r_type == R_LARCH_GOT64_PC_LO20) -+ RELOCATE_CALC_PC64_HI32 (relocation, pc - 8); - - break; - -@@ -3864,13 +3867,14 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, - /* Use both TLS_GD and TLS_DESC. */ - if ((tls_type & GOT_TLS_GD) && (tls_type & GOT_TLS_GDESC)) - relocation += 2 * GOT_ENTRY_SIZE; -- } - -- if (r_type == R_LARCH_TLS_DESC64_PC_LO20 -- || r_type == R_LARCH_TLS_DESC64_PC_HI12) -- RELOCATE_CALC_PC64_HI32 (relocation, pc); -+ if (r_type == R_LARCH_TLS_DESC64_PC_LO20) -+ RELOCATE_CALC_PC64_HI32 (relocation, pc - 8); -+ else if (r_type == R_LARCH_TLS_DESC64_PC_HI12) -+ RELOCATE_CALC_PC64_HI32 (relocation, pc - 12); - - break; -+ } - - case R_LARCH_TLS_DESC_LD: - case R_LARCH_TLS_DESC_CALL: -@@ -3899,9 +3903,10 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, - else if (GOT_TLS_GD_ANY_P (tls_type) && (tls_type & GOT_TLS_IE)) - relocation += 2 * GOT_ENTRY_SIZE; - -- if (r_type == R_LARCH_TLS_IE64_PC_LO20 -- || r_type == R_LARCH_TLS_IE64_PC_HI12) -- RELOCATE_CALC_PC64_HI32 (relocation, pc); -+ if (r_type == R_LARCH_TLS_IE64_PC_LO20) -+ RELOCATE_CALC_PC64_HI32 (relocation, pc - 8); -+ else if (r_type == R_LARCH_TLS_IE64_PC_HI12) -+ RELOCATE_CALC_PC64_HI32 (relocation, pc - 12); - - break; - -diff --git a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -index 64e644d3..c81f20af 100644 ---- a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -+++ b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -@@ -33,6 +33,7 @@ if [istarget "loongarch64-*-*"] { - run_dump_test "disas-jirl" - run_dump_test "local-ifunc-reloc" - run_dump_test "anno-sym" -+ run_dump_test "pcala64" - } - - if [istarget "loongarch32-*-*"] { -diff --git a/ld/testsuite/ld-loongarch-elf/pcala64.d b/ld/testsuite/ld-loongarch-elf/pcala64.d -new file mode 100644 -index 00000000..e0e9819d ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/pcala64.d -@@ -0,0 +1,15 @@ -+#ld: -Ttext=0x180000ff8 -Tdata=0x1000000000 -+#objdump: -d -+ -+.*:[ ]+file format .* -+ -+ -+Disassembly of section .text: -+ -+0000000180000ff8 <_start>: -+[ ]+180000ff8:[ ]+1b000004[ ]+pcalau12i[ ]+\$a0,[ ]+-524288 -+[ ]+180000ffc:[ ]+02c0000c[ ]+li.d[ ]+\$t0,[ ]+0 -+[ ]+180001000:[ ]+160001ec[ ]+lu32i.d[ ]+\$t0,[ ]+15 -+[ ]+180001004:[ ]+0300018c[ ]+lu52i.d[ ]+\$t0,[ ]+\$t0,[ ]+0 -+[ ]+180001008:[ ]+0010b084[ ]+add.d[ ]+\$a0,[ ]+\$a0,[ ]+\$t0 -+[ ]+18000100c:[ ]+4c000020[ ]+ret -diff --git a/ld/testsuite/ld-loongarch-elf/pcala64.s b/ld/testsuite/ld-loongarch-elf/pcala64.s -new file mode 100644 -index 00000000..dfef0e2b ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/pcala64.s -@@ -0,0 +1,8 @@ -+.text -+.globl _start -+_start: -+ la.pcrel $a0, $t0, sym -+ jr $ra -+.data -+sym: -+ .dword 0 --- -2.33.0 - diff --git a/LoongArch-Add-DT_RELR-support.patch b/LoongArch-Add-DT_RELR-support.patch deleted file mode 100644 index 541aff0..0000000 --- a/LoongArch-Add-DT_RELR-support.patch +++ /dev/null @@ -1,641 +0,0 @@ -From f0c66bc13d177150c3055cf7c321e48d0eb58b12 Mon Sep 17 00:00:00 2001 -From: Xi Ruoyao -Date: Wed, 30 Oct 2024 18:32:50 +0800 -Subject: [PATCH 098/123] LoongArch: Add DT_RELR support - -The logic is same as a71d87680110 ("aarch64: Add DT_RELR support"). - -As LoongArch does not have -z dynamic-undefined-weak, we don't need to -consider UNDEFWEAK_NO_DYNAMIC_RELOC. - -The linker relaxation adds another layer of complexity. When we delete -bytes in a section during relaxation, we need to fix up the offset in -the to-be-packed relative relocations against this section. - -Signed-off-by: Xi Ruoyao ---- - bfd/elfnn-loongarch.c | 488 ++++++++++++++++++++- - binutils/testsuite/lib/binutils-common.exp | 3 +- - ld/emulparams/elf64loongarch.sh | 1 + - 3 files changed, 487 insertions(+), 5 deletions(-) - -diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c -index 2bdd7be2..d11189b4 100644 ---- a/bfd/elfnn-loongarch.c -+++ b/bfd/elfnn-loongarch.c -@@ -84,6 +84,12 @@ struct _bfd_loongarch_elf_obj_tdata - && elf_tdata (bfd) != NULL \ - && elf_object_id (bfd) == LARCH_ELF_DATA) - -+struct relr_entry -+{ -+ asection *sec; -+ bfd_vma off; -+}; -+ - struct loongarch_elf_link_hash_table - { - struct elf_link_hash_table elf; -@@ -104,8 +110,51 @@ struct loongarch_elf_link_hash_table - /* The data segment phase, don't relax the section - when it is exp_seg_relro_adjust. */ - int *data_segment_phase; -+ -+ /* Array of relative relocs to be emitted in DT_RELR format. */ -+ bfd_size_type relr_alloc; -+ bfd_size_type relr_count; -+ struct relr_entry *relr; -+ -+ /* Sorted output addresses of above relative relocs. */ -+ bfd_vma *relr_sorted; -+ -+ /* Layout recomputation count. */ -+ bfd_size_type relr_layout_iter; -+}; -+ -+struct loongarch_elf_section_data -+{ -+ struct bfd_elf_section_data elf; -+ -+ /* &htab->relr[i] where i is the smallest number s.t. -+ elf_section_data (htab->relr[i].sec) == &elf. -+ NULL if there exists no such i. */ -+ struct relr_entry *relr; - }; - -+/* We need an additional field in elf_section_data to handle complex -+ interactions between DT_RELR and relaxation. */ -+static bool -+loongarch_elf_new_section_hook (bfd *abfd, asection *sec) -+{ -+ if (!sec->used_by_bfd) -+ { -+ struct loongarch_elf_section_data *sdata; -+ size_t amt = sizeof (*sdata); -+ -+ sdata = bfd_zalloc (abfd, amt); -+ if (!sdata) -+ return false; -+ sec->used_by_bfd = sdata; -+ } -+ -+ return _bfd_elf_new_section_hook (abfd, sec); -+} -+ -+#define loongarch_elf_section_data(x) \ -+ ((struct loongarch_elf_section_data *) elf_section_data (x)) -+ - /* Get the LoongArch ELF linker hash table from a link_info structure. */ - #define loongarch_elf_hash_table(p) \ - (elf_hash_table_id (elf_hash_table (p)) == LARCH_ELF_DATA \ -@@ -927,6 +976,20 @@ loongarch_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, - if (rel + 1 != relocs + sec->reloc_count - && ELFNN_R_TYPE (rel[1].r_info) == R_LARCH_RELAX) - r_type = loongarch_tls_transition (abfd, info, h, r_symndx, r_type); -+ -+ /* I don't want to spend time supporting DT_RELR with old object -+ files doing stack-based relocs. */ -+ if (info->enable_dt_relr -+ && r_type >= R_LARCH_SOP_PUSH_PCREL -+ && r_type <= R_LARCH_SOP_POP_32_U) -+ { -+ /* xgettext:c-format */ -+ _bfd_error_handler (_("%pB: stack based reloc type (%u) is not " -+ "supported with -z pack-relative-relocs"), -+ abfd, r_type); -+ return false; -+ } -+ - switch (r_type) - { - case R_LARCH_GOT_PC_HI20: -@@ -1143,6 +1206,20 @@ loongarch_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, - return false; - break; - -+ case R_LARCH_ALIGN: -+ /* Check against irrational R_LARCH_ALIGN relocs which may cause -+ removing an odd number of bytes and disrupt DT_RELR. */ -+ if (rel->r_offset % 4 != 0) -+ { -+ /* xgettext:c-format */ -+ _bfd_error_handler ( -+ _("%pB: R_LARCH_ALIGN with offset %" PRId64 " not aligned " -+ "to instruction boundary"), -+ abfd, (uint64_t) rel->r_offset); -+ return false; -+ } -+ break; -+ - default: - break; - } -@@ -1857,6 +1934,343 @@ maybe_set_textrel (struct elf_link_hash_entry *h, void *info_p) - return true; - } - -+static bool -+record_relr (struct loongarch_elf_link_hash_table *htab, asection *sec, -+ bfd_vma off, asection *sreloc) -+{ -+ struct relr_entry **sec_relr = &loongarch_elf_section_data (sec)->relr; -+ -+ /* Undo the relocation section size accounting. */ -+ BFD_ASSERT (sreloc->size >= sizeof (ElfNN_External_Rela)); -+ sreloc->size -= sizeof (ElfNN_External_Rela); -+ -+ BFD_ASSERT (off % 2 == 0 && sec->alignment_power > 0); -+ if (htab->relr_count >= htab->relr_alloc) -+ { -+ if (htab->relr_alloc == 0) -+ htab->relr_alloc = 4096; -+ else -+ htab->relr_alloc *= 2; -+ -+ htab->relr = bfd_realloc (htab->relr, -+ htab->relr_alloc * sizeof (*htab->relr)); -+ if (!htab->relr) -+ return false; -+ } -+ htab->relr[htab->relr_count].sec = sec; -+ htab->relr[htab->relr_count].off = off; -+ if (*sec_relr == NULL) -+ *sec_relr = &htab->relr[htab->relr_count]; -+ htab->relr_count++; -+ return true; -+} -+ -+static bool -+record_relr_local_got_relocs (bfd *input_bfd, struct bfd_link_info *info) -+{ -+ bfd_vma *local_got_offsets = elf_local_got_offsets (input_bfd); -+ char *local_tls_type = _bfd_loongarch_elf_local_got_tls_type (input_bfd); -+ Elf_Internal_Shdr *symtab_hdr = &elf_symtab_hdr (input_bfd); -+ struct loongarch_elf_link_hash_table *htab = -+ loongarch_elf_hash_table (info); -+ -+ if (!local_got_offsets || !local_tls_type || !bfd_link_pic (info)) -+ return true; -+ -+ for (unsigned i = 0; i < symtab_hdr->sh_info; i++) -+ { -+ bfd_vma off = local_got_offsets[i]; -+ -+ /* FIXME: If the local symbol is in SHN_ABS then emitting -+ a relative relocation is not correct, but it seems to be wrong -+ in loongarch_elf_relocate_section too. */ -+ if (local_tls_type[i] == GOT_NORMAL -+ && !record_relr (htab, htab->elf.sgot, off, htab->elf.srelgot)) -+ return false; -+ } -+ -+ return true; -+} -+ -+static bool -+record_relr_dyn_got_relocs (struct elf_link_hash_entry *h, void *inf) -+{ -+ struct bfd_link_info *info = (struct bfd_link_info *) inf; -+ struct loongarch_elf_link_hash_table *htab = -+ loongarch_elf_hash_table (info); -+ -+ if (h->root.type == bfd_link_hash_indirect) -+ return true; -+ if (h->type == STT_GNU_IFUNC && h->def_regular) -+ return true; -+ if (h->got.refcount <= 0) -+ return true; -+ if (loongarch_elf_hash_entry (h)->tls_type -+ & (GOT_TLS_GD | GOT_TLS_IE | GOT_TLS_GDESC)) -+ return true; -+ if (!bfd_link_pic (info)) -+ return true; -+ -+ /* On LoongArch a GOT entry for undefined weak symbol is never relocated -+ with R_LARCH_RELATIVE: we don't have -z dynamic-undefined-weak, thus -+ the GOT entry is either const 0 (if the symbol is LARCH_REF_LOCAL) or -+ relocated with R_LARCH_NN (otherwise). */ -+ if (h->root.type == bfd_link_hash_undefweak) -+ return true; -+ -+ if (!LARCH_REF_LOCAL (info, h)) -+ return true; -+ if (bfd_is_abs_symbol (&h->root)) -+ return true; -+ -+ if (!record_relr (htab, htab->elf.sgot, h->got.offset, -+ htab->elf.srelgot)) -+ return false; -+ -+ return true; -+} -+ -+static bool -+record_relr_non_got_relocs (bfd *input_bfd, struct bfd_link_info *info, -+ asection *sec) -+{ -+ asection *sreloc; -+ struct loongarch_elf_link_hash_table *htab; -+ Elf_Internal_Rela *relocs, *rel, *rel_end; -+ Elf_Internal_Shdr *symtab_hdr; -+ struct elf_link_hash_entry **sym_hashes; -+ -+ if (!bfd_link_pic (info)) -+ return true; -+ if (sec->reloc_count == 0) -+ return true; -+ if ((sec->flags & (SEC_RELOC | SEC_ALLOC | SEC_DEBUGGING)) -+ != (SEC_RELOC | SEC_ALLOC)) -+ return true; -+ if (sec->alignment_power == 0) -+ return true; -+ if (discarded_section (sec)) -+ return true; -+ -+ sreloc = elf_section_data (sec)->sreloc; -+ if (sreloc == NULL) -+ return true; -+ -+ htab = loongarch_elf_hash_table (info); -+ symtab_hdr = &elf_symtab_hdr (input_bfd); -+ sym_hashes = elf_sym_hashes (input_bfd); -+ relocs = _bfd_elf_link_info_read_relocs (input_bfd, info, sec, NULL, -+ NULL, info->keep_memory); -+ BFD_ASSERT (relocs != NULL); -+ rel_end = relocs + sec->reloc_count; -+ for (rel = relocs; rel < rel_end; rel++) -+ { -+ unsigned r_symndx = ELFNN_R_SYM (rel->r_info); -+ unsigned int r_type = ELFNN_R_TYPE (rel->r_info); -+ struct elf_link_hash_entry *h = NULL; -+ asection *def_sec = NULL; -+ -+ if ((r_type != R_LARCH_64 && r_type != R_LARCH_32) -+ || rel->r_offset % 2 != 0) -+ continue; -+ -+ /* The logical below must match loongarch_elf_relocate_section. */ -+ if (r_symndx < symtab_hdr->sh_info) -+ { -+ /* A local symbol. */ -+ Elf_Internal_Sym *isym; -+ isym = bfd_sym_from_r_symndx (&htab->elf.sym_cache, input_bfd, -+ r_symndx); -+ BFD_ASSERT(isym != NULL); -+ -+ /* Local STT_GNU_IFUNC symbol uses R_LARCH_IRELATIVE for -+ R_LARCH_NN, not R_LARCH_RELATIVE. */ -+ if (ELF_ST_TYPE (isym->st_info) == STT_GNU_IFUNC) -+ continue; -+ def_sec = bfd_section_from_elf_index (input_bfd, isym->st_shndx); -+ } -+ else -+ { -+ h = sym_hashes[r_symndx - symtab_hdr->sh_info]; -+ while (h->root.type == bfd_link_hash_indirect -+ || h->root.type == bfd_link_hash_warning) -+ h = (struct elf_link_hash_entry *) h->root.u.i.link; -+ -+ /* Filter out symbols that cannot have a relative reloc. */ -+ if (h->dyn_relocs == NULL) -+ continue; -+ if (bfd_is_abs_symbol (&h->root)) -+ continue; -+ if (h->type == STT_GNU_IFUNC) -+ continue; -+ -+ if (h->root.type == bfd_link_hash_defined -+ || h->root.type == bfd_link_hash_defweak) -+ def_sec = h->root.u.def.section; -+ -+ /* On LoongArch an R_LARCH_NN against undefined weak symbol -+ is never converted to R_LARCH_RELATIVE: we don't have -+ -z dynamic-undefined-weak, thus the reloc is either removed -+ (if the symbol is LARCH_REF_LOCAL) or kept (otherwise). */ -+ if (h->root.type == bfd_link_hash_undefweak) -+ continue; -+ -+ if (!LARCH_REF_LOCAL (info, h)) -+ continue; -+ } -+ -+ if (!def_sec || discarded_section (def_sec)) -+ continue; -+ -+ if (!record_relr (htab, sec, rel->r_offset, sreloc)) -+ return false; -+ } -+ -+ return true; -+} -+ -+static int -+cmp_relr_addr (const void *p, const void *q) -+{ -+ const bfd_vma *a = p, *b = q; -+ return (*a > *b) - (*a < *b); -+} -+ -+static bool -+sort_relr (struct bfd_link_info *info, -+ struct loongarch_elf_link_hash_table *htab) -+{ -+ if (htab->relr_count == 0) -+ return true; -+ -+ bfd_vma *addr = htab->relr_sorted; -+ if (!addr) -+ { -+ addr = bfd_malloc (htab->relr_count * sizeof (*addr)); -+ if (!addr) -+ return false; -+ htab->relr_sorted = addr; -+ } -+ -+ for (bfd_size_type i = 0; i < htab->relr_count; i++) -+ { -+ bfd_vma off = _bfd_elf_section_offset (info->output_bfd, info, -+ htab->relr[i].sec, -+ htab->relr[i].off); -+ addr[i] = htab->relr[i].sec->output_section->vma -+ + htab->relr[i].sec->output_offset + off; -+ } -+ qsort(addr, htab->relr_count, sizeof (*addr), cmp_relr_addr); -+ return true; -+} -+ -+static bool -+loongarch_elf_size_relative_relocs (struct bfd_link_info *info, -+ bool *need_layout) -+{ -+ struct loongarch_elf_link_hash_table *htab = -+ loongarch_elf_hash_table (info); -+ asection *srelrdyn = htab->elf.srelrdyn; -+ -+ *need_layout = false; -+ -+ if (!sort_relr (info, htab)) -+ return false; -+ bfd_vma *addr = htab->relr_sorted; -+ -+ BFD_ASSERT (srelrdyn != NULL); -+ bfd_size_type oldsize = srelrdyn->size; -+ srelrdyn->size = 0; -+ for (bfd_size_type i = 0; i < htab->relr_count; ) -+ { -+ bfd_vma base = addr[i]; -+ i++; -+ srelrdyn->size += NN / 8; -+ base += NN / 8; -+ while (1) -+ { -+ bfd_size_type start_i = i; -+ while (i < htab->relr_count -+ && addr[i] - base < (NN - 1) * (NN / 8) -+ && (addr[i] - base) % (NN / 8) == 0) -+ i++; -+ if (i == start_i) -+ break; -+ srelrdyn->size += NN / 8; -+ base += (NN - 1) * (NN / 8); -+ } -+ } -+ if (srelrdyn->size != oldsize) -+ { -+ *need_layout = true; -+ /* Stop after a few iterations in case the layout does not converge, -+ but we can only stop when the size would shrink (and pad the -+ spare space with 1. */ -+ if (htab->relr_layout_iter++ > 5 && srelrdyn->size < oldsize) -+ { -+ srelrdyn->size = oldsize; -+ *need_layout = false; -+ } -+ } -+ return true; -+} -+ -+static bool -+loongarch_elf_finish_relative_relocs (struct bfd_link_info *info) -+{ -+ struct loongarch_elf_link_hash_table *htab = -+ loongarch_elf_hash_table (info); -+ asection *srelrdyn = htab->elf.srelrdyn; -+ bfd *dynobj = htab->elf.dynobj; -+ -+ if (!srelrdyn || srelrdyn->size == 0) -+ return true; -+ -+ srelrdyn->contents = bfd_alloc (dynobj, srelrdyn->size); -+ if (!srelrdyn->contents) -+ return false; -+ -+ bfd_vma *addr = htab->relr_sorted; -+ bfd_byte *loc = srelrdyn->contents; -+ for (bfd_size_type i = 0; i < htab->relr_count; ) -+ { -+ bfd_vma base = addr[i]; -+ i++; -+ bfd_put_NN (dynobj, base, loc); -+ loc += NN / 8; -+ base += NN / 8; -+ while (1) -+ { -+ uintNN_t bits = 0; -+ while (i < htab->relr_count) -+ { -+ bfd_vma delta = addr[i] - base; -+ if (delta >= (NN - 1) * (NN / 8) || delta % (NN / 8) != 0) -+ break; -+ bits |= (uintNN_t) 1 << (delta / (NN / 8)); -+ i++; -+ } -+ if (bits == 0) -+ break; -+ bfd_put_NN (dynobj, (bits << 1) | 1, loc); -+ loc += NN / 8; -+ base += (NN - 1) * (NN / 8); -+ } -+ } -+ -+ free (addr); -+ htab->relr_sorted = NULL; -+ -+ /* Pad any excess with 1's, a do-nothing encoding. */ -+ while (loc < srelrdyn->contents + srelrdyn->size) -+ { -+ bfd_put_NN (dynobj, 1, loc); -+ loc += NN / 8; -+ } -+ -+ return true; -+} -+ - static bool - loongarch_elf_size_dynamic_sections (bfd *output_bfd, - struct bfd_link_info *info) -@@ -2036,6 +2450,24 @@ loongarch_elf_size_dynamic_sections (bfd *output_bfd, - && (htab->elf.splt == NULL || htab->elf.splt->size == 0)) - htab->elf.sgotplt->size = 0; - -+ if (info->enable_dt_relr && !bfd_link_relocatable (info)) -+ { -+ elf_link_hash_traverse (&htab->elf, record_relr_dyn_got_relocs, info); -+ -+ for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next) -+ { -+ if (!is_loongarch_elf (ibfd)) -+ continue; -+ -+ for (s = ibfd->sections; s != NULL; s = s->next) -+ if (!record_relr_non_got_relocs (ibfd, info, s)) -+ return false; -+ -+ if (!record_relr_local_got_relocs (ibfd, info)) -+ return false; -+ } -+ } -+ - /* The check_relocs and adjust_dynamic_symbol entry points have - determined the sizes of the various dynamic sections. Allocate - memory for them. */ -@@ -2060,6 +2492,14 @@ loongarch_elf_size_dynamic_sections (bfd *output_bfd, - s->reloc_count = 0; - } - } -+ else if (s == htab->elf.srelrdyn && htab->relr_count == 0) -+ { -+ /* Remove .relr.dyn based on relr_count, not size, since -+ it is not sized yet. */ -+ s->flags |= SEC_EXCLUDE; -+ /* Allocate contents later. */ -+ continue; -+ } - else - { - /* It's not one of our sections. */ -@@ -2976,7 +3416,21 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, - if (unresolved_reloc - && (ARCH_SIZE == 32 || r_type != R_LARCH_32) - && !(h && (h->is_weakalias || !h->dyn_relocs))) -- loongarch_elf_append_rela (output_bfd, sreloc, &outrel); -+ { -+ if (info->enable_dt_relr -+ && (ELFNN_R_TYPE (outrel.r_info) == R_LARCH_RELATIVE) -+ && input_section->alignment_power != 0 -+ && rel->r_offset % 2 == 0) -+ /* Don't emit a relative relocation that is packed, -+ only apply the addend (as if we are applying the -+ original R_LARCH_NN reloc in a PDE). */ -+ r = perform_relocation (rel, input_section, howto, -+ relocation, input_bfd, -+ contents); -+ else -+ loongarch_elf_append_rela (output_bfd, sreloc, -+ &outrel); -+ } - } - - relocation += rel->r_addend; -@@ -3700,7 +4154,7 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, - got_off = local_got_offsets[r_symndx] & (~(bfd_vma)1); - if ((local_got_offsets[r_symndx] & 1) == 0) - { -- if (bfd_link_pic (info)) -+ if (bfd_link_pic (info) && !info->enable_dt_relr) - { - Elf_Internal_Rela rela; - rela.r_offset = sec_addr (got) + got_off; -@@ -4112,6 +4566,13 @@ loongarch_relax_delete_bytes (bfd *abfd, - unsigned int sec_shndx = _bfd_elf_section_from_bfd_section (abfd, sec); - struct bfd_elf_section_data *data = elf_section_data (sec); - bfd_byte *contents = data->this_hdr.contents; -+ struct relr_entry *relr = loongarch_elf_section_data (sec)->relr; -+ struct loongarch_elf_link_hash_table *htab = -+ loongarch_elf_hash_table (link_info); -+ struct relr_entry *relr_end = NULL; -+ -+ if (htab->relr_count) -+ relr_end = htab->relr + htab->relr_count; - - /* Actually delete the bytes. */ - sec->size -= count; -@@ -4124,6 +4585,11 @@ loongarch_relax_delete_bytes (bfd *abfd, - if (data->relocs[i].r_offset > addr && data->relocs[i].r_offset < toaddr) - data->relocs[i].r_offset -= count; - -+ /* Likewise for relative relocs to be packed into .relr. */ -+ for (; relr && relr < relr_end && relr->sec == sec; relr++) -+ if (relr->off > addr && relr->off < toaddr) -+ relr->off -= count; -+ - /* Adjust the local symbols defined in this section. */ - for (i = 0; i < symtab_hdr->sh_info; i++) - { -@@ -5212,9 +5678,18 @@ loongarch_elf_finish_dynamic_symbol (bfd *output_bfd, - else if (bfd_link_pic (info) && LARCH_REF_LOCAL (info, h)) - { - asection *sec = h->root.u.def.section; -+ bfd_vma linkaddr = h->root.u.def.value + sec->output_section->vma -+ + sec->output_offset; -+ -+ /* Don't emit relative relocs if they are packed, but we need -+ to write the addend (link-time addr) into the GOT then. */ -+ if (info->enable_dt_relr) -+ { -+ bfd_put_NN (output_bfd, linkaddr, sgot->contents + off); -+ goto skip_got_reloc; -+ } - rela.r_info = ELFNN_R_INFO (0, R_LARCH_RELATIVE); -- rela.r_addend = (h->root.u.def.value + sec->output_section->vma -- + sec->output_offset); -+ rela.r_addend = linkaddr; - } - else - { -@@ -5225,6 +5700,7 @@ loongarch_elf_finish_dynamic_symbol (bfd *output_bfd, - - loongarch_elf_append_rela (output_bfd, srela, &rela); - } -+skip_got_reloc: - - /* Mark some specially defined symbols as absolute. */ - if (h == htab->elf.hdynamic || h == htab->elf.hgot || h == htab->elf.hplt) -@@ -5678,6 +6154,10 @@ elf_loongarch64_hash_symbol (struct elf_link_hash_entry *h) - #define elf_backend_grok_psinfo loongarch_elf_grok_psinfo - #define elf_backend_hash_symbol elf_loongarch64_hash_symbol - #define bfd_elfNN_bfd_relax_section loongarch_elf_relax_section -+#define elf_backend_size_relative_relocs loongarch_elf_size_relative_relocs -+#define elf_backend_finish_relative_relocs \ -+ loongarch_elf_finish_relative_relocs -+#define bfd_elfNN_new_section_hook loongarch_elf_new_section_hook - - #define elf_backend_dtrel_excludes_plt 1 - -diff --git a/binutils/testsuite/lib/binutils-common.exp b/binutils/testsuite/lib/binutils-common.exp -index 7e6bf16e..d006d30d 100644 ---- a/binutils/testsuite/lib/binutils-common.exp -+++ b/binutils/testsuite/lib/binutils-common.exp -@@ -444,7 +444,8 @@ proc supports_persistent_section {} { - proc supports_dt_relr {} { - if { ([istarget x86_64-*-*] - || [istarget i?86-*-*] -- || [istarget powerpc64*-*-*]) -+ || [istarget powerpc64*-*-*] -+ || [istarget loongarch64*-*-*]) - && ([istarget *-*-linux*] - || [istarget *-*-gnu*]) } { - return 1 -diff --git a/ld/emulparams/elf64loongarch.sh b/ld/emulparams/elf64loongarch.sh -index d7b2229e..8c805da9 100644 ---- a/ld/emulparams/elf64loongarch.sh -+++ b/ld/emulparams/elf64loongarch.sh -@@ -1,4 +1,5 @@ - source_sh ${srcdir}/emulparams/elf64loongarch-defs.sh -+source_sh ${srcdir}/emulparams/dt-relr.sh - OUTPUT_FORMAT="elf64-loongarch" - - case "$target" in --- -2.33.0 - diff --git a/LoongArch-Add-DT_RELR-tests.patch b/LoongArch-Add-DT_RELR-tests.patch deleted file mode 100644 index 6ab3164..0000000 --- a/LoongArch-Add-DT_RELR-tests.patch +++ /dev/null @@ -1,663 +0,0 @@ -From c3d71bd5b8f0f949729025ad3338e3f93e5e0d77 Mon Sep 17 00:00:00 2001 -From: Xi Ruoyao -Date: Sun, 30 Jun 2024 15:18:25 +0800 -Subject: [PATCH 099/123] LoongArch: Add DT_RELR tests - -Most tests are ported from AArch64. - -The relr-addend test is added to make sure the addend (link-time address) -is correctly written into the relocated section. Doing so is not -strictly needed for RELA, but strictly needed for RELR). - -Signed-off-by: Xi Ruoyao ---- - .../ld-loongarch-elf/ld-loongarch-elf.exp | 10 ++ - ld/testsuite/ld-loongarch-elf/relr-addend.d | 11 ++ - ld/testsuite/ld-loongarch-elf/relr-addend.s | 17 +++ - ld/testsuite/ld-loongarch-elf/relr-align.d | 22 ++++ - ld/testsuite/ld-loongarch-elf/relr-align.s | 106 ++++++++++++++++++ - ld/testsuite/ld-loongarch-elf/relr-data-pie.d | 18 +++ - .../ld-loongarch-elf/relr-data-shared.d | 18 +++ - ld/testsuite/ld-loongarch-elf/relr-data.s | 71 ++++++++++++ - .../ld-loongarch-elf/relr-discard-pie.d | 8 ++ - .../ld-loongarch-elf/relr-discard-shared.d | 11 ++ - ld/testsuite/ld-loongarch-elf/relr-discard.ld | 13 +++ - ld/testsuite/ld-loongarch-elf/relr-discard.s | 61 ++++++++++ - ld/testsuite/ld-loongarch-elf/relr-got-pie.d | 15 +++ - .../ld-loongarch-elf/relr-got-shared.d | 15 +++ - ld/testsuite/ld-loongarch-elf/relr-got.s | 27 +++++ - ld/testsuite/ld-loongarch-elf/relr-relocs.ld | 24 ++++ - ld/testsuite/ld-loongarch-elf/relr-text-pie.d | 14 +++ - .../ld-loongarch-elf/relr-text-shared.d | 14 +++ - ld/testsuite/ld-loongarch-elf/relr-text.s | 10 ++ - 19 files changed, 485 insertions(+) - create mode 100644 ld/testsuite/ld-loongarch-elf/relr-addend.d - create mode 100644 ld/testsuite/ld-loongarch-elf/relr-addend.s - create mode 100644 ld/testsuite/ld-loongarch-elf/relr-align.d - create mode 100644 ld/testsuite/ld-loongarch-elf/relr-align.s - create mode 100644 ld/testsuite/ld-loongarch-elf/relr-data-pie.d - create mode 100644 ld/testsuite/ld-loongarch-elf/relr-data-shared.d - create mode 100644 ld/testsuite/ld-loongarch-elf/relr-data.s - create mode 100644 ld/testsuite/ld-loongarch-elf/relr-discard-pie.d - create mode 100644 ld/testsuite/ld-loongarch-elf/relr-discard-shared.d - create mode 100644 ld/testsuite/ld-loongarch-elf/relr-discard.ld - create mode 100644 ld/testsuite/ld-loongarch-elf/relr-discard.s - create mode 100644 ld/testsuite/ld-loongarch-elf/relr-got-pie.d - create mode 100644 ld/testsuite/ld-loongarch-elf/relr-got-shared.d - create mode 100644 ld/testsuite/ld-loongarch-elf/relr-got.s - create mode 100644 ld/testsuite/ld-loongarch-elf/relr-relocs.ld - create mode 100644 ld/testsuite/ld-loongarch-elf/relr-text-pie.d - create mode 100644 ld/testsuite/ld-loongarch-elf/relr-text-shared.d - create mode 100644 ld/testsuite/ld-loongarch-elf/relr-text.s - -diff --git a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -index 30d7bc03..2be67651 100644 ---- a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -+++ b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -@@ -135,10 +135,20 @@ if [istarget "loongarch64-*-*"] { - run_dump_test "r_larch_32_elf64" - run_dump_test "ifunc-reloc" - run_dump_test "protected-func" -+ run_dump_test "relr-addend" -+ run_dump_test "relr-align" -+ run_dump_test "relr-data-shared" -+ run_dump_test "relr-discard-shared" -+ run_dump_test "relr-got-shared" -+ run_dump_test "relr-text-shared" - } - - if [check_pie_support] { - run_dump_test "pie_discard" -+ run_dump_test "relr-data-pie" -+ run_dump_test "relr-discard-pie" -+ run_dump_test "relr-got-pie" -+ run_dump_test "relr-text-pie" - } - - run_dump_test "max_imm_b16" -diff --git a/ld/testsuite/ld-loongarch-elf/relr-addend.d b/ld/testsuite/ld-loongarch-elf/relr-addend.d -new file mode 100644 -index 00000000..da13c2cf ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/relr-addend.d -@@ -0,0 +1,11 @@ -+#ld: -shared -z pack-relative-relocs -T relr-relocs.ld -+#objdump: -s -j.got -j.data -+ -+.*: file format elf64-loongarch -+ -+Contents of section \.got: -+ 20000 [0-9a-f]+ [0-9a-f]+ 00003412 00000000 .* -+ 20010 08003412 00000000 .* -+Contents of section \.data: -+ 12340000 14451100 00000000 10989101 00000000 .* -+ 12340010 00003412 00000000 08003412 00000000 .* -diff --git a/ld/testsuite/ld-loongarch-elf/relr-addend.s b/ld/testsuite/ld-loongarch-elf/relr-addend.s -new file mode 100644 -index 00000000..3d08f6ca ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/relr-addend.s -@@ -0,0 +1,17 @@ -+.data -+.align 8 -+x: -+ .quad 0x114514 -+y: -+ .quad 0x1919810 -+px: -+ .quad x -+py: -+ .quad y -+ -+.text -+.align 2 -+_start: -+ la.got $a0, x -+ la.got $a1, y -+ ret -diff --git a/ld/testsuite/ld-loongarch-elf/relr-align.d b/ld/testsuite/ld-loongarch-elf/relr-align.d -new file mode 100644 -index 00000000..d534243b ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/relr-align.d -@@ -0,0 +1,22 @@ -+#source: relr-align.s -+#ld: -shared -z pack-relative-relocs -T relr-relocs.ld -+#readelf: -rW -+ -+Relocation section '\.rela.dyn' at offset 0x[0-9a-f]+ contains 3 entries: -+ Offset Info Type Symbol's Value Symbol's Name \+ Addend -+0000000012340011 0000000000000003 R_LARCH_RELATIVE 10000 -+0000000012340019 0000000000000003 R_LARCH_RELATIVE 10000 -+0000000012340041 0000000000000003 R_LARCH_RELATIVE 10000 -+ -+Relocation section '\.relr.dyn' at offset 0x[0-9a-f]+ contains 9 entries which relocate 10 locations: -+Index: Entry Address Symbolic Address -+0000: 0000000012340000 0000000012340000 double_0 -+0001: 0000000000000003 0000000012340008 double_0 \+ 0x8 -+0002: 0000000012340022 0000000012340022 double_2 -+0003: 0000000000000003 000000001234002a double_2 \+ 0x8 -+0004: 0000000012340038 0000000012340038 single_0 -+0005: 000000001234004a 000000001234004a single_2 -+0006: 0000000012340058 0000000012340058 big -+0007: 8000000100000001 0000000012340158 big \+ 0x100 -+ 0000000012340250 big \+ 0x1f8 -+0008: 0000000000000003 0000000012340258 big \+ 0x200 -diff --git a/ld/testsuite/ld-loongarch-elf/relr-align.s b/ld/testsuite/ld-loongarch-elf/relr-align.s -new file mode 100644 -index 00000000..ddd055ab ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/relr-align.s -@@ -0,0 +1,106 @@ -+# Test DT_RELR with differently aligned relative relocs. -+ -+.text -+.global _start -+_start: -+foo: -+ -+.data -+.p2align 3 -+double_0: -+.quad foo -+.quad foo -+.byte 0 -+double_1: -+.quad foo -+.quad foo -+.byte 0 -+double_2: -+.quad foo -+.quad foo -+.byte 0 -+.byte 0 -+.byte 0 -+.byte 0 -+.byte 0 -+.byte 0 -+single_0: -+.quad foo -+.byte 0 -+single_1: -+.quad foo -+.byte 0 -+single_2: -+.quad foo -+.byte 0 -+.byte 0 -+.byte 0 -+.byte 0 -+.byte 0 -+.byte 0 -+big: -+.quad foo -+.quad 1 -+.quad 2 -+.quad 3 -+.quad 4 -+.quad 5 -+.quad 6 -+.quad 7 -+.quad 8 -+.quad 9 -+.quad 10 -+.quad 11 -+.quad 12 -+.quad 13 -+.quad 14 -+.quad 15 -+.quad 16 -+.quad 17 -+.quad 18 -+.quad 19 -+.quad 20 -+.quad 21 -+.quad 22 -+.quad 23 -+.quad 24 -+.quad 25 -+.quad 26 -+.quad 27 -+.quad 28 -+.quad 29 -+.quad 30 -+.quad 31 -+.quad foo + 32 -+.quad 33 -+.quad 34 -+.quad 35 -+.quad 36 -+.quad 37 -+.quad 38 -+.quad 39 -+.quad 40 -+.quad 41 -+.quad 42 -+.quad 43 -+.quad 44 -+.quad 45 -+.quad 46 -+.quad 47 -+.quad 48 -+.quad 49 -+.quad 50 -+.quad 51 -+.quad 52 -+.quad 53 -+.quad 54 -+.quad 55 -+.quad 56 -+.quad 57 -+.quad 58 -+.quad 59 -+.quad 60 -+.quad 61 -+.quad 62 -+.quad foo + 63 -+.quad foo + 64 -diff --git a/ld/testsuite/ld-loongarch-elf/relr-data-pie.d b/ld/testsuite/ld-loongarch-elf/relr-data-pie.d -new file mode 100644 -index 00000000..20ef9ac1 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/relr-data-pie.d -@@ -0,0 +1,18 @@ -+#source: relr-data.s -+#ld: -pie -z pack-relative-relocs -T relr-relocs.ld -+#readelf: -rW -+ -+Relocation section '\.rela\.dyn' at offset 0x[0-9a-f]+ contains 5 entries: -+ Offset Info Type Symbol's Value Symbol's Name \+ Addend -+0000000012340000 0000000000000003 R_LARCH_RELATIVE 10004 -+0000000012340008 0000000000000003 R_LARCH_RELATIVE 10008 -+0000000012340010 0000000000000003 R_LARCH_RELATIVE 1000c -+0000000012340018 0000000000000003 R_LARCH_RELATIVE 12340050 -+0000000012340040 0000000c00000002 R_LARCH_64 0000000000000000 sym_weak_undef \+ 0 -+ -+Relocation section '\.relr\.dyn' at offset 0x[0-9a-f]+ contains 2 entries which relocate 4 locations: -+Index: Entry Address Symbolic Address -+0000: 0000000012340020 0000000012340020 aligned_local -+0001: 0000000000000027 0000000012340028 aligned_hidden -+ 0000000012340030 aligned_global -+ 0000000012340048 aligned_DYNAMIC -diff --git a/ld/testsuite/ld-loongarch-elf/relr-data-shared.d b/ld/testsuite/ld-loongarch-elf/relr-data-shared.d -new file mode 100644 -index 00000000..37e4c0da ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/relr-data-shared.d -@@ -0,0 +1,18 @@ -+#source: relr-data.s -+#ld: -shared -z pack-relative-relocs -T relr-relocs.ld -+#readelf: -rW -+ -+Relocation section '\.rela\.dyn' at offset 0x[0-9a-f]+ contains 6 entries: -+ Offset Info Type Symbol's Value Symbol's Name \+ Addend -+0000000012340000 0000000000000003 R_LARCH_RELATIVE 10004 -+0000000012340008 0000000000000003 R_LARCH_RELATIVE 10008 -+0000000012340018 0000000000000003 R_LARCH_RELATIVE 12340050 -+0000000012340010 0000000d00000002 R_LARCH_64 000000000001000c sym_global \+ 0 -+0000000012340030 0000000d00000002 R_LARCH_64 000000000001000c sym_global \+ 0 -+0000000012340040 0000000c00000002 R_LARCH_64 0000000000000000 sym_weak_undef \+ 0 -+ -+Relocation section '\.relr\.dyn' at offset 0x[0-9a-f]+ contains 2 entries which relocate 3 locations: -+Index: Entry Address Symbolic Address -+0000: 0000000012340020 0000000012340020 aligned_local -+0001: 0000000000000023 0000000012340028 aligned_hidden -+ 0000000012340048 aligned_DYNAMIC -diff --git a/ld/testsuite/ld-loongarch-elf/relr-data.s b/ld/testsuite/ld-loongarch-elf/relr-data.s -new file mode 100644 -index 00000000..03673e0f ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/relr-data.s -@@ -0,0 +1,71 @@ -+# Test symbol references in .data when used with DT_RELR. -+# Relocations for unaligned sections are currently not packed. -+ -+.text -+.global _start -+_start: -+ nop -+ -+sym_local: -+ nop -+ -+.global sym_hidden -+.hidden sym_hidden -+sym_hidden: -+ nop -+ -+.global sym_global -+sym_global: -+ nop -+ -+.global sym_global_abs -+.set sym_global_abs, 42 -+ -+.global sym_weak_undef -+.weak sym_weak_undef -+ -+.section .data.unaligned_local -+unaligned_local: -+.quad sym_local -+ -+.section .data.unaligned_hidden -+unaligned_hidden: -+.quad sym_hidden -+ -+.section .data.unaligned_global -+unaligned_global: -+.quad sym_global -+ -+.section .data.unaligned_DYNAMIC -+unaligned_DYNAMIC: -+.quad _DYNAMIC -+ -+.section .data.aligned_local -+.p2align 1 -+aligned_local: -+.quad sym_local -+ -+.section .data.aligned_hidden -+.p2align 1 -+aligned_hidden: -+.quad sym_hidden -+ -+.section .data.aligned_global -+.p2align 1 -+aligned_global: -+.quad sym_global -+ -+.section .data.aligned_global_abs -+.p2align 1 -+aligned_global_abs: -+.quad sym_global_abs -+ -+.section .data.aligned_weak_undef -+.p2align 1 -+aligned_weak_undef: -+.quad sym_weak_undef -+ -+.section .data.aligned_DYNAMIC -+.p2align 1 -+aligned_DYNAMIC: -+.quad _DYNAMIC -diff --git a/ld/testsuite/ld-loongarch-elf/relr-discard-pie.d b/ld/testsuite/ld-loongarch-elf/relr-discard-pie.d -new file mode 100644 -index 00000000..4ea8ae5e ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/relr-discard-pie.d -@@ -0,0 +1,8 @@ -+#source: relr-discard.s -+#ld: -pie -z pack-relative-relocs -T relr-discard.ld -+#readelf: -rW -+ -+Relocation section '\.relr\.dyn' at offset 0x[0-9a-f]+ contains 2 entries which relocate 2 locations: -+Index: Entry Address Symbolic Address -+0000: 0000000000020008 0000000000020008 _GLOBAL_OFFSET_TABLE_ \+ 0x8 -+0001: 0000000000000003 0000000000020010 _GLOBAL_OFFSET_TABLE_ \+ 0x10 -diff --git a/ld/testsuite/ld-loongarch-elf/relr-discard-shared.d b/ld/testsuite/ld-loongarch-elf/relr-discard-shared.d -new file mode 100644 -index 00000000..8bfd8ba5 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/relr-discard-shared.d -@@ -0,0 +1,11 @@ -+#source: relr-discard.s -+#ld: -shared -z pack-relative-relocs -T relr-discard.ld -+#readelf: -rW -+ -+Relocation section '\.rela\.dyn' at offset 0x[0-9a-f]+ contains 1 entry: -+ Offset Info Type Symbol's Value Symbol's Name \+ Addend -+0000000000020010 0000000300000002 R_LARCH_64 000000000001000c sym_global \+ 0 -+ -+Relocation section '\.relr\.dyn' at offset 0x[0-9a-f]+ contains 1 entry which relocates 1 location: -+Index: Entry Address Symbolic Address -+0000: 0000000000020008 0000000000020008 _GLOBAL_OFFSET_TABLE_ \+ 0x8 -diff --git a/ld/testsuite/ld-loongarch-elf/relr-discard.ld b/ld/testsuite/ld-loongarch-elf/relr-discard.ld -new file mode 100644 -index 00000000..165f1ed2 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/relr-discard.ld -@@ -0,0 +1,13 @@ -+OUTPUT_ARCH(loongarch64) -+ENTRY(_start) -+SECTIONS -+{ -+ /DISCARD/ : { *(.discard.*) } -+ -+ . = 0x10000; -+ .text : { *(.text) } -+ . = 0x20000; -+ .got : { *(.got) *(.got.plt)} -+ . = 0x30000; -+ .data : { *(.data) *(.data.*) } -+} -diff --git a/ld/testsuite/ld-loongarch-elf/relr-discard.s b/ld/testsuite/ld-loongarch-elf/relr-discard.s -new file mode 100644 -index 00000000..b52374a5 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/relr-discard.s -@@ -0,0 +1,61 @@ -+# Test DT_RELR with references in discarded sections. -+ -+.text -+.p2align 3 -+.global _start -+_start: -+ nop -+ -+sym_local: -+ nop -+ -+.global sym_hidden -+.hidden sym_hidden -+sym_hidden: -+ nop -+ -+.global sym_global -+sym_global: -+ nop -+ -+.global sym_global_abs -+.set sym_global_abs, 42 -+ -+.global sym_weak_undef -+.weak sym_weak_undef -+ -+.section .discard.got_local,"ax" -+ la.got $a0, sym_local -+ -+.section .discard.got_global,"ax" -+ la.got $a0, sym_global -+ -+.section .discard.local,"a" -+.p2align 1 -+discard_local: -+.quad sym_local -+ -+.section .discard.hidden,"a" -+.p2align 1 -+discard_hidden: -+.quad sym_hidden -+ -+.section .discard.global,"a" -+.p2align 1 -+discard_global: -+.quad sym_global -+ -+.section .discard.global_abs,"a" -+.p2align 1 -+discard_global_abs: -+.quad sym_global_abs -+ -+.section .discard.weak_undef,"a" -+.p2align 1 -+discard_weak_undef: -+.quad sym_weak_undef -+ -+.section .discard._DYNAMIC,"a" -+.p2align 1 -+discard_DYNAMIC: -+.quad _DYNAMIC -diff --git a/ld/testsuite/ld-loongarch-elf/relr-got-pie.d b/ld/testsuite/ld-loongarch-elf/relr-got-pie.d -new file mode 100644 -index 00000000..e994f2bf ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/relr-got-pie.d -@@ -0,0 +1,15 @@ -+#source: relr-got.s -+#ld: -pie -z pack-relative-relocs -T relr-relocs.ld -+#readelf: -rW -+ -+Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 2 entries: -+ Offset Info Type Symbol's Value Symbol's Name \+ Addend -+0000000000000000 0000000000000000 R_LARCH_NONE 0 -+0000000000020030 0000000200000002 R_LARCH_64 0000000000000000 sym_weak_undef \+ 0 -+ -+Relocation section '.relr.dyn' at offset 0x[0-9a-f]+ contains 2 entries which relocate 4 locations: -+Index: Entry Address Symbolic Address -+0000: 0000000000020008 0000000000020008 _GLOBAL_OFFSET_TABLE_ \+ 0x8 -+0001: 000000000000000f 0000000000020010 _GLOBAL_OFFSET_TABLE_ \+ 0x10 -+ 0000000000020018 _GLOBAL_OFFSET_TABLE_ \+ 0x18 -+ 0000000000020020 _GLOBAL_OFFSET_TABLE_ \+ 0x20 -diff --git a/ld/testsuite/ld-loongarch-elf/relr-got-shared.d b/ld/testsuite/ld-loongarch-elf/relr-got-shared.d -new file mode 100644 -index 00000000..169e0e5d ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/relr-got-shared.d -@@ -0,0 +1,15 @@ -+#source: relr-got.s -+#ld: -shared -z pack-relative-relocs -T relr-relocs.ld -+#readelf: -rW -+ -+Relocation section '\.rela\.dyn' at offset 0x[0-9a-f]+ contains 3 entries: -+ Offset Info Type Symbol's Value Symbol's Name \+ Addend -+0000000000020020 0000000300000002 R_LARCH_64 0000000000010034 sym_global \+ 0 -+0000000000020028 0000000500000002 R_LARCH_64 000000000000002a sym_global_abs \+ 0 -+0000000000020030 0000000200000002 R_LARCH_64 0000000000000000 sym_weak_undef \+ 0 -+ -+Relocation section '\.relr\.dyn' at offset 0x[0-9a-f]+ contains 2 entries which relocate 3 locations: -+Index: Entry Address Symbolic Address -+0000: 0000000000020008 0000000000020008 _GLOBAL_OFFSET_TABLE_ \+ 0x8 -+0001: 0000000000000007 0000000000020010 _GLOBAL_OFFSET_TABLE_ \+ 0x10 -+ 0000000000020018 _GLOBAL_OFFSET_TABLE_ \+ 0x18 -diff --git a/ld/testsuite/ld-loongarch-elf/relr-got.s b/ld/testsuite/ld-loongarch-elf/relr-got.s -new file mode 100644 -index 00000000..162528bc ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/relr-got.s -@@ -0,0 +1,27 @@ -+.text -+.global _start -+_start: -+ la.got $a0, sym_local -+ la.got $a1, sym_hidden -+ la.got $a2, sym_global -+ la.got $a3, sym_global_abs -+ la.got $a4, sym_weak_undef -+ la.got $a5, _DYNAMIC -+ -+sym_local: -+ nop -+ -+.global sym_hidden -+.hidden sym_hidden -+sym_hidden: -+ nop -+ -+.global sym_global -+sym_global: -+ nop -+ -+.global sym_global_abs -+.set sym_global_abs, 42 -+ -+.global sym_weak_undef -+.weak sym_weak_undef -diff --git a/ld/testsuite/ld-loongarch-elf/relr-relocs.ld b/ld/testsuite/ld-loongarch-elf/relr-relocs.ld -new file mode 100644 -index 00000000..ed83275b ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/relr-relocs.ld -@@ -0,0 +1,24 @@ -+/* Script for DT_RELR tests */ -+OUTPUT_ARCH(loongarch64) -+ENTRY(_start) -+SECTIONS -+{ -+ PROVIDE (__executable_start = 0x8000); . = 0x10000; -+ .text : -+ { -+ *(.before) -+ *(.text) -+ *(.after) -+ } =0 -+ . = 0x20000; -+ .got : -+ { -+ *(.got) -+ *(.got.plt) -+ } -+ . = 0x12340000; -+ .data : -+ { -+ *(.data) -+ } -+} -diff --git a/ld/testsuite/ld-loongarch-elf/relr-text-pie.d b/ld/testsuite/ld-loongarch-elf/relr-text-pie.d -new file mode 100644 -index 00000000..5121313e ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/relr-text-pie.d -@@ -0,0 +1,14 @@ -+#source: relr-text.s -+#ld: -pie -z pack-relative-relocs -T relr-relocs.ld -+#readelf: -drW -+ -+#... -+ 0x0000000000000016 \(TEXTREL\) 0x0 -+#... -+ 0x0000000000000024 \(RELR\) .* -+ 0x0000000000000023 \(RELRSZ\) 8 \(bytes\) -+ 0x0000000000000025 \(RELRENT\) 8 \(bytes\) -+#... -+Relocation section '\.relr\.dyn' .* contains 1 entry which relocates 1 location: -+Index: Entry Address Symbolic Address -+0000: 0000000000010000 0000000000010000 _start -diff --git a/ld/testsuite/ld-loongarch-elf/relr-text-shared.d b/ld/testsuite/ld-loongarch-elf/relr-text-shared.d -new file mode 100644 -index 00000000..8e34500f ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/relr-text-shared.d -@@ -0,0 +1,14 @@ -+#source: relr-text.s -+#ld: -shared -z pack-relative-relocs -T relr-relocs.ld -+#readelf: -drW -+ -+#... -+ 0x0000000000000016 \(TEXTREL\) 0x0 -+#... -+ 0x0000000000000024 \(RELR\) .* -+ 0x0000000000000023 \(RELRSZ\) 8 \(bytes\) -+ 0x0000000000000025 \(RELRENT\) 8 \(bytes\) -+#... -+Relocation section '\.relr\.dyn' .* contains 1 entry which relocates 1 location: -+Index: Entry Address Symbolic Address -+0000: 0000000000010000 0000000000010000 _start -diff --git a/ld/testsuite/ld-loongarch-elf/relr-text.s b/ld/testsuite/ld-loongarch-elf/relr-text.s -new file mode 100644 -index 00000000..47465f2d ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/relr-text.s -@@ -0,0 +1,10 @@ -+# Test DT_RELR with DT_TEXTREL and R_LARCH_ALIGN. -+ -+.text -+.p2align 5 -+.global _start -+_start: -+.global foo -+.hidden foo -+foo: -+.quad foo --- -2.33.0 - diff --git a/LoongArch-Add-bad-static-relocation-check-and-output.patch b/LoongArch-Add-bad-static-relocation-check-and-output.patch deleted file mode 100644 index dd1333e..0000000 --- a/LoongArch-Add-bad-static-relocation-check-and-output.patch +++ /dev/null @@ -1,185 +0,0 @@ -From 3aeea61a3efc9a5535a2dcb9e938782ba3a60aa6 Mon Sep 17 00:00:00 2001 -From: Lulu Cai -Date: Tue, 19 Mar 2024 17:51:19 +0800 -Subject: [PATCH 082/123] LoongArch: Add bad static relocation check and output - more information to user - -Absolute address symbols cannot be used with -shared. -We output more information to the user than just BFD_ASSETR. ---- - bfd/elfnn-loongarch.c | 33 +++++++++++++++++-- - .../ld-loongarch-elf/ld-loongarch-elf.exp | 3 ++ - .../ld-loongarch-elf/reloc_abs_with_shared.d | 6 ++++ - .../ld-loongarch-elf/reloc_abs_with_shared.s | 9 +++++ - .../ld-loongarch-elf/reloc_le_with_shared.d | 6 ++++ - .../ld-loongarch-elf/reloc_le_with_shared.s | 8 +++++ - .../ld-loongarch-elf/reloc_ler_with_shared.d | 4 +++ - .../ld-loongarch-elf/reloc_ler_with_shared.s | 9 +++++ - 8 files changed, 76 insertions(+), 2 deletions(-) - create mode 100644 ld/testsuite/ld-loongarch-elf/reloc_abs_with_shared.d - create mode 100644 ld/testsuite/ld-loongarch-elf/reloc_abs_with_shared.s - create mode 100644 ld/testsuite/ld-loongarch-elf/reloc_le_with_shared.d - create mode 100644 ld/testsuite/ld-loongarch-elf/reloc_le_with_shared.s - create mode 100644 ld/testsuite/ld-loongarch-elf/reloc_ler_with_shared.d - create mode 100644 ld/testsuite/ld-loongarch-elf/reloc_ler_with_shared.s - -diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c -index 0a7caa2a..ee708c7f 100644 ---- a/bfd/elfnn-loongarch.c -+++ b/bfd/elfnn-loongarch.c -@@ -760,6 +760,33 @@ loongarch_tls_transition (bfd *input_bfd, - allocate space in the global offset table or procedure linkage - table. */ - -+static bool -+bad_static_reloc (bfd *abfd, const Elf_Internal_Rela *rel, asection *sec, -+ unsigned r_type, struct elf_link_hash_entry *h, -+ Elf_Internal_Sym *isym) -+{ -+ /* We propably can improve the information to tell users that they should -+ be recompile the code with -fPIC or -fPIE, just like what x86 does. */ -+ reloc_howto_type * r = loongarch_elf_rtype_to_howto (abfd, r_type); -+ const char *name = NULL; -+ -+ if (h) -+ name = h->root.root.string; -+ else if (isym) -+ name = bfd_elf_string_from_elf_section (abfd, -+ elf_symtab_hdr (abfd).sh_link, -+ isym->st_name); -+ if (name == NULL || *name == '\0') -+ name =""; -+ -+ (*_bfd_error_handler) -+ (_("%pB:(%pA+%#lx): relocation %s against `%s` can not be used when making " -+ "a shared object; recompile with -fPIC"), -+ abfd, sec, rel->r_offset, r ? r->name : _(""), name); -+ bfd_set_error (bfd_error_bad_value); -+ return false; -+} -+ - static bool - loongarch_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, - asection *sec, const Elf_Internal_Rela *relocs) -@@ -904,7 +931,7 @@ loongarch_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, - case R_LARCH_TLS_LE_HI20_R: - case R_LARCH_SOP_PUSH_TLS_TPREL: - if (!bfd_link_executable (info)) -- return false; -+ return bad_static_reloc (abfd, rel, sec, r_type, h, isym); - - if (!loongarch_elf_record_tls_and_got_reference (abfd, info, h, - r_symndx, -@@ -922,6 +949,9 @@ loongarch_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, - - case R_LARCH_ABS_HI20: - case R_LARCH_SOP_PUSH_ABSOLUTE: -+ if (bfd_link_pic (info)) -+ return bad_static_reloc (abfd, rel, sec, r_type, h, isym); -+ - if (h != NULL) - /* If this reloc is in a read-only section, we might - need a copy reloc. We can't check reliably at this -@@ -3397,7 +3427,6 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, - case R_LARCH_ABS_LO12: - case R_LARCH_ABS64_LO20: - case R_LARCH_ABS64_HI12: -- BFD_ASSERT (!is_pic); - - if (is_undefweak) - { -diff --git a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -index fc7b5bfe..3c8e9195 100644 ---- a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -+++ b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -@@ -134,6 +134,9 @@ if [istarget "loongarch64-*-*"] { - run_dump_test "desc-norelax" - run_dump_test "desc-relax" - run_dump_test "data-got" -+ run_dump_test "reloc_le_with_shared" -+ run_dump_test "reloc_ler_with_shared" -+ run_dump_test "reloc_abs_with_shared" - } - - if [check_pie_support] { -diff --git a/ld/testsuite/ld-loongarch-elf/reloc_abs_with_shared.d b/ld/testsuite/ld-loongarch-elf/reloc_abs_with_shared.d -new file mode 100644 -index 00000000..532e84fb ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/reloc_abs_with_shared.d -@@ -0,0 +1,6 @@ -+#source: reloc_abs_with_shared.s -+#as: -+#ld: -shared -+#error: .*relocation R_LARCH_ABS_HI20 against `s` can not be used when making a shared object; recompile with -fPIC -+#... -+#pass -diff --git a/ld/testsuite/ld-loongarch-elf/reloc_abs_with_shared.s b/ld/testsuite/ld-loongarch-elf/reloc_abs_with_shared.s -new file mode 100644 -index 00000000..13341af2 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/reloc_abs_with_shared.s -@@ -0,0 +1,9 @@ -+ .text -+ .globl s -+ .data -+ .type s, @object -+ s: -+ .word 123 -+ .text -+ lu12i.w $r4,%abs_hi20(s) -+ addi.d $r4,$r4,%abs_lo12(s) -diff --git a/ld/testsuite/ld-loongarch-elf/reloc_le_with_shared.d b/ld/testsuite/ld-loongarch-elf/reloc_le_with_shared.d -new file mode 100644 -index 00000000..562b079a ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/reloc_le_with_shared.d -@@ -0,0 +1,6 @@ -+#source: reloc_le_with_shared.s -+#as: -+#ld: -shared -+#error: .*relocation R_LARCH_TLS_LE_HI20 against `s` can not be used when making a shared object; recompile with -fPIC -+#... -+#pass -diff --git a/ld/testsuite/ld-loongarch-elf/reloc_le_with_shared.s b/ld/testsuite/ld-loongarch-elf/reloc_le_with_shared.s -new file mode 100644 -index 00000000..c7206650 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/reloc_le_with_shared.s -@@ -0,0 +1,8 @@ -+ .text -+ .globl s -+ .section .tdata,"awT",@progbits -+ .type s, @object -+ s: -+ .word 123 -+ .text -+ la.tls.le $r4, s -diff --git a/ld/testsuite/ld-loongarch-elf/reloc_ler_with_shared.d b/ld/testsuite/ld-loongarch-elf/reloc_ler_with_shared.d -new file mode 100644 -index 00000000..7382d5b8 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/reloc_ler_with_shared.d -@@ -0,0 +1,4 @@ -+#source: reloc_ler_with_shared.s -+#as: -+#ld: -shared -+#error: .*relocation R_LARCH_TLS_LE_HI20_R against `s` can not be used when making a shared object; recompile with -fPIC -diff --git a/ld/testsuite/ld-loongarch-elf/reloc_ler_with_shared.s b/ld/testsuite/ld-loongarch-elf/reloc_ler_with_shared.s -new file mode 100644 -index 00000000..a9e56967 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/reloc_ler_with_shared.s -@@ -0,0 +1,9 @@ -+ .text -+ .globl s -+ .section .tdata,"awT",@progbits -+ .type s, @object -+ s: -+ .word 123 -+ .text -+ lu12i.w $r4,%le_hi20_r(s) -+ add.d $r4,$r4,$r2,%le_add_r(s) --- -2.33.0 - diff --git a/LoongArch-Add-call36-and-tail36-pseudo-instructions-.patch b/LoongArch-Add-call36-and-tail36-pseudo-instructions-.patch deleted file mode 100644 index 0ac64cb..0000000 --- a/LoongArch-Add-call36-and-tail36-pseudo-instructions-.patch +++ /dev/null @@ -1,101 +0,0 @@ -From 205e07d68684bc331c16b7bcea44b8d5ca84f7e8 Mon Sep 17 00:00:00 2001 -From: mengqinggang -Date: Thu, 23 Nov 2023 15:42:49 +0800 -Subject: [PATCH 021/123] LoongArch: Add call36 and tail36 pseudo instructions - for medium code model - - For tail36, it is necessary to explicitly indicate the temporary register. - Therefore, the compiler and users will know that the tail will use a register. - - call36 func - pcalau18i $ra, %call36(func) - jirl $ra, $ra, 0; - - tail36 $t0, func - pcalau18i $t0, %call36(func) - jirl $zero, $t0, 0; ---- - gas/testsuite/gas/loongarch/medium-call.d | 10 ++++++++-- - gas/testsuite/gas/loongarch/medium-call.s | 2 ++ - ld/testsuite/ld-loongarch-elf/medium-call.s | 2 ++ - opcodes/loongarch-opc.c | 11 +++++++++++ - 4 files changed, 23 insertions(+), 2 deletions(-) - -diff --git a/gas/testsuite/gas/loongarch/medium-call.d b/gas/testsuite/gas/loongarch/medium-call.d -index 4183818c..3491760b 100644 ---- a/gas/testsuite/gas/loongarch/medium-call.d -+++ b/gas/testsuite/gas/loongarch/medium-call.d -@@ -10,6 +10,12 @@ Disassembly of section .text: - [ ]+0:[ ]+1e000001[ ]+pcaddu18i[ ]+\$ra, 0 - [ ]+0: R_LARCH_CALL36[ ]+a - [ ]+4:[ ]+4c000021[ ]+jirl[ ]+\$ra, \$ra, 0 --[ ]+8:[ ]+1e00000c[ ]+pcaddu18i[ ]+\$t0, 0 -+[ ]+8:[ ]+1e000001[ ]+pcaddu18i[ ]+\$ra, 0 - [ ]+8: R_LARCH_CALL36[ ]+a --[ ]+c:[ ]+4c000180[ ]+jr[ ]+\$t0 -+[ ]+c:[ ]+4c000021[ ]+jirl[ ]+\$ra, \$ra, 0 -+[ ]+10:[ ]+1e00000c[ ]+pcaddu18i[ ]+\$t0, 0 -+[ ]+10: R_LARCH_CALL36[ ]+a -+[ ]+14:[ ]+4c000180[ ]+jr[ ]+\$t0 -+[ ]+18:[ ]+1e00000c[ ]+pcaddu18i[ ]+\$t0, 0 -+[ ]+18: R_LARCH_CALL36[ ]+a -+[ ]+1c:[ ]+4c000180[ ]+jr[ ]+\$t0 -diff --git a/gas/testsuite/gas/loongarch/medium-call.s b/gas/testsuite/gas/loongarch/medium-call.s -index f2977d1c..74d15076 100644 ---- a/gas/testsuite/gas/loongarch/medium-call.s -+++ b/gas/testsuite/gas/loongarch/medium-call.s -@@ -1,6 +1,8 @@ - # call .L1, r1(ra) temp register, r1(ra) return register. -+ call36 a - pcaddu18i $r1, %call36(a) - jirl $r1, $r1, 0 - # tail .L1, r12(t0) temp register, r0(zero) return register. -+ tail36 $r12, a - pcaddu18i $r12, %call36(a) - jirl $r0, $r12, 0 -diff --git a/ld/testsuite/ld-loongarch-elf/medium-call.s b/ld/testsuite/ld-loongarch-elf/medium-call.s -index 4d1888b7..50a6b8e7 100644 ---- a/ld/testsuite/ld-loongarch-elf/medium-call.s -+++ b/ld/testsuite/ld-loongarch-elf/medium-call.s -@@ -1,7 +1,9 @@ - .L1: - # call .L1, r1(ra) temp register, r1(ra) return register. -+ call36 .L1 - pcaddu18i $r1, %call36(.L1) - jirl $r1, $r1, 0 - # tail .L1, r12(t0) temp register, r0(zero) return register. -+ tail36 $r12, .L1 - pcaddu18i $r12, %call36(.L1) - jirl $r0, $r12, 0 -diff --git a/opcodes/loongarch-opc.c b/opcodes/loongarch-opc.c -index 15c7da63..b47817f8 100644 ---- a/opcodes/loongarch-opc.c -+++ b/opcodes/loongarch-opc.c -@@ -293,6 +293,15 @@ const char *const loongarch_x_normal_name[32] = - &LARCH_opts.ase_lp64, \ - &LARCH_opts.ase_gpcr - -+#define INSN_LA_CALL \ -+ "pcaddu18i $ra,%%call36(%1);" \ -+ "jirl $ra,$ra,0;", \ -+ 0, 0 -+ -+#define INSN_LA_TAIL \ -+ "pcaddu18i %1,%%call36(%2);" \ -+ "jirl $zero,%1,0;", \ -+ 0, 0 - - static struct loongarch_opcode loongarch_macro_opcodes[] = - { -@@ -340,6 +349,8 @@ static struct loongarch_opcode loongarch_macro_opcodes[] = - { 0, 0, "la.tls.gd", "r,l", INSN_LA_TLS_GD64, 0 }, - { 0, 0, "la.tls.gd", "r,l", INSN_LA_TLS_GD64_LARGE_ABS, 0 }, - { 0, 0, "la.tls.gd", "r,r,l", INSN_LA_TLS_GD64_LARGE_PCREL, 0 }, -+ { 0, 0, "call36", "la", INSN_LA_CALL, 0 }, -+ { 0, 0, "tail36", "r,la", INSN_LA_TAIL, 0 }, - { 0, 0, "pcaddi", "r,la", "pcaddi %1, %%pcrel_20(%2)", &LARCH_opts.ase_ilp32, 0, 0 }, - { 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list. */ - }; --- -2.33.0 - diff --git a/LoongArch-Add-dtpoff-calculation-function.patch b/LoongArch-Add-dtpoff-calculation-function.patch deleted file mode 100644 index 059b31e..0000000 --- a/LoongArch-Add-dtpoff-calculation-function.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 43fdb57b36afb8fd1d76f3dc7a9833d60ef90422 Mon Sep 17 00:00:00 2001 -From: Lulu Cai -Date: Fri, 23 Feb 2024 16:28:22 +0800 -Subject: [PATCH 070/123] LoongArch: Add dtpoff calculation function - -When tls_sec is NULL, we should not access the virtual address -of tls_sec. ---- - bfd/elfnn-loongarch.c | 12 +++++++++++- - 1 file changed, 11 insertions(+), 1 deletion(-) - -diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c -index eea1839f..489ccbe0 100644 ---- a/bfd/elfnn-loongarch.c -+++ b/bfd/elfnn-loongarch.c -@@ -2550,6 +2550,16 @@ loongarch_reloc_is_fatal (struct bfd_link_info *info, - }) - - -+static bfd_vma -+tls_dtpoff_base (struct bfd_link_info *info) -+{ -+ /* If tls_sec is NULL, we should have signalled an error already. */ -+ if (elf_hash_table (info)->tls_sec == NULL) -+ return 0; -+ return elf_hash_table (info)->tls_sec->vma; -+} -+ -+ - static int - loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, - bfd *input_bfd, asection *input_section, -@@ -3708,7 +3718,7 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, - rela.r_offset = sec_addr (got) + got_off + desc_off; - rela.r_addend = 0; - if (indx == 0) -- rela.r_addend = relocation - elf_hash_table (info)->tls_sec->vma; -+ rela.r_addend = relocation - tls_dtpoff_base (info); - - rela.r_info = ELFNN_R_INFO (indx, R_LARCH_TLS_DESCNN); - loongarch_elf_append_rela (output_bfd, relgot, &rela); --- -2.33.0 - diff --git a/LoongArch-Add-elfNN_loongarch_mkobject-to-initialize.patch b/LoongArch-Add-elfNN_loongarch_mkobject-to-initialize.patch deleted file mode 100644 index 74779fd..0000000 --- a/LoongArch-Add-elfNN_loongarch_mkobject-to-initialize.patch +++ /dev/null @@ -1,42 +0,0 @@ -From 5ba625b50145a8234129ab6b4a58a18e530ae9d7 Mon Sep 17 00:00:00 2001 -From: Xin Wang -Date: Fri, 6 Sep 2024 09:00:12 +0800 -Subject: [PATCH 114/123] LoongArch: Add elfNN_loongarch_mkobject to initialize - LoongArch tdata - -LoongArch: Add elfNN_loongarch_mkobject to initialize LoongArch tdata. ---- - bfd/elfnn-loongarch.c | 10 ++++++++++ - 1 file changed, 10 insertions(+) - -diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c -index 09a9513b..b6d7d1e8 100644 ---- a/bfd/elfnn-loongarch.c -+++ b/bfd/elfnn-loongarch.c -@@ -84,6 +84,14 @@ struct _bfd_loongarch_elf_obj_tdata - && elf_tdata (bfd) != NULL \ - && elf_object_id (bfd) == LARCH_ELF_DATA) - -+static bool -+elfNN_loongarch_object (bfd *abfd) -+{ -+ return bfd_elf_allocate_object (abfd, -+ sizeof (struct _bfd_loongarch_elf_obj_tdata), -+ LARCH_ELF_DATA); -+} -+ - struct relr_entry - { - asection *sec; -@@ -6158,6 +6166,8 @@ elf_loongarch64_hash_symbol (struct elf_link_hash_entry *h) - #define bfd_elfNN_bfd_reloc_name_lookup loongarch_reloc_name_lookup - #define elf_info_to_howto_rel NULL /* Fall through to elf_info_to_howto. */ - #define elf_info_to_howto loongarch_info_to_howto_rela -+#define bfd_elfNN_mkobject \ -+ elfNN_loongarch_object - #define bfd_elfNN_bfd_merge_private_bfd_data \ - elfNN_loongarch_merge_private_bfd_data - --- -2.33.0 - diff --git a/LoongArch-Add-gas-testsuit-for-LA32-int-float-instru.patch b/LoongArch-Add-gas-testsuit-for-LA32-int-float-instru.patch deleted file mode 100644 index e181e9b..0000000 --- a/LoongArch-Add-gas-testsuit-for-LA32-int-float-instru.patch +++ /dev/null @@ -1,654 +0,0 @@ -From 1ced47506592c7724be57101d70254e826e833d1 Mon Sep 17 00:00:00 2001 -From: Lulu Cai -Date: Wed, 10 Jan 2024 16:17:50 +0800 -Subject: [PATCH 066/123] LoongArch: Add gas testsuit for LA32 int/float - instructions - -Test the int/float instructions of LA32. ---- - gas/testsuite/gas/loongarch/insn_float32.d | 157 +++++++++++++++++++++ - gas/testsuite/gas/loongarch/insn_float32.s | 149 +++++++++++++++++++ - gas/testsuite/gas/loongarch/insn_int32.d | 147 +++++++++++++++++++ - gas/testsuite/gas/loongarch/insn_int32.s | 156 ++++++++++++++++++++ - 4 files changed, 609 insertions(+) - create mode 100644 gas/testsuite/gas/loongarch/insn_float32.d - create mode 100644 gas/testsuite/gas/loongarch/insn_float32.s - create mode 100644 gas/testsuite/gas/loongarch/insn_int32.d - create mode 100644 gas/testsuite/gas/loongarch/insn_int32.s - -diff --git a/gas/testsuite/gas/loongarch/insn_float32.d b/gas/testsuite/gas/loongarch/insn_float32.d -new file mode 100644 -index 00000000..ee2408af ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/insn_float32.d -@@ -0,0 +1,157 @@ -+#as-new: -+#objdump: -d -+#skip: loongarch64-*-* -+ -+.*: file format .* -+ -+ -+Disassembly of section .text: -+ -+0+ <.*>: -+ 0: 01008820 fadd.s \$fa0, \$fa1, \$fa2 -+ 4: 01010820 fadd.d \$fa0, \$fa1, \$fa2 -+ 8: 01028820 fsub.s \$fa0, \$fa1, \$fa2 -+ c: 01030820 fsub.d \$fa0, \$fa1, \$fa2 -+ 10: 01048820 fmul.s \$fa0, \$fa1, \$fa2 -+ 14: 01050820 fmul.d \$fa0, \$fa1, \$fa2 -+ 18: 01068820 fdiv.s \$fa0, \$fa1, \$fa2 -+ 1c: 01070820 fdiv.d \$fa0, \$fa1, \$fa2 -+ 20: 01088820 fmax.s \$fa0, \$fa1, \$fa2 -+ 24: 01090820 fmax.d \$fa0, \$fa1, \$fa2 -+ 28: 010a8820 fmin.s \$fa0, \$fa1, \$fa2 -+ 2c: 010b0820 fmin.d \$fa0, \$fa1, \$fa2 -+ 30: 010c8820 fmaxa.s \$fa0, \$fa1, \$fa2 -+ 34: 010d0820 fmaxa.d \$fa0, \$fa1, \$fa2 -+ 38: 010e8820 fmina.s \$fa0, \$fa1, \$fa2 -+ 3c: 010f0820 fmina.d \$fa0, \$fa1, \$fa2 -+ 40: 01108820 fscaleb.s \$fa0, \$fa1, \$fa2 -+ 44: 01110820 fscaleb.d \$fa0, \$fa1, \$fa2 -+ 48: 01128820 fcopysign.s \$fa0, \$fa1, \$fa2 -+ 4c: 01130820 fcopysign.d \$fa0, \$fa1, \$fa2 -+ 50: 01140420 fabs.s \$fa0, \$fa1 -+ 54: 01140820 fabs.d \$fa0, \$fa1 -+ 58: 01141420 fneg.s \$fa0, \$fa1 -+ 5c: 01141820 fneg.d \$fa0, \$fa1 -+ 60: 01142420 flogb.s \$fa0, \$fa1 -+ 64: 01142820 flogb.d \$fa0, \$fa1 -+ 68: 01143420 fclass.s \$fa0, \$fa1 -+ 6c: 01143820 fclass.d \$fa0, \$fa1 -+ 70: 01144420 fsqrt.s \$fa0, \$fa1 -+ 74: 01144820 fsqrt.d \$fa0, \$fa1 -+ 78: 01145420 frecip.s \$fa0, \$fa1 -+ 7c: 01145820 frecip.d \$fa0, \$fa1 -+ 80: 01146420 frsqrt.s \$fa0, \$fa1 -+ 84: 01146820 frsqrt.d \$fa0, \$fa1 -+ 88: 01149420 fmov.s \$fa0, \$fa1 -+ 8c: 01149820 fmov.d \$fa0, \$fa1 -+ 90: 0114a4a0 movgr2fr.w \$fa0, \$a1 -+ 94: 0114a8a0 movgr2fr.d \$fa0, \$a1 -+ 98: 0114aca0 movgr2frh.w \$fa0, \$a1 -+ 9c: 0114b424 movfr2gr.s \$a0, \$fa1 -+ a0: 0114b824 movfr2gr.d \$a0, \$fa1 -+ a4: 0114bc24 movfrh2gr.s \$a0, \$fa1 -+ a8: 0114c0a0 movgr2fcsr \$fcsr0, \$a1 -+ ac: 0114c804 movfcsr2gr \$a0, \$fcsr0 -+ b0: 0114d020 movfr2cf \$fcc0, \$fa1 -+ b4: 0114d4a0 movcf2fr \$fa0, \$fcc5 -+ b8: 0114d8a0 movgr2cf \$fcc0, \$a1 -+ bc: 0114dca4 movcf2gr \$a0, \$fcc5 -+ c0: 01191820 fcvt.s.d \$fa0, \$fa1 -+ c4: 01192420 fcvt.d.s \$fa0, \$fa1 -+ c8: 011a0420 ftintrm.w.s \$fa0, \$fa1 -+ cc: 011a0820 ftintrm.w.d \$fa0, \$fa1 -+ d0: 011a2420 ftintrm.l.s \$fa0, \$fa1 -+ d4: 011a2820 ftintrm.l.d \$fa0, \$fa1 -+ d8: 011a4420 ftintrp.w.s \$fa0, \$fa1 -+ dc: 011a4820 ftintrp.w.d \$fa0, \$fa1 -+ e0: 011a6420 ftintrp.l.s \$fa0, \$fa1 -+ e4: 011a6820 ftintrp.l.d \$fa0, \$fa1 -+ e8: 011a8420 ftintrz.w.s \$fa0, \$fa1 -+ ec: 011a8820 ftintrz.w.d \$fa0, \$fa1 -+ f0: 011aa420 ftintrz.l.s \$fa0, \$fa1 -+ f4: 011aa820 ftintrz.l.d \$fa0, \$fa1 -+ f8: 011ac420 ftintrne.w.s \$fa0, \$fa1 -+ fc: 011ac820 ftintrne.w.d \$fa0, \$fa1 -+ 100: 011ae420 ftintrne.l.s \$fa0, \$fa1 -+ 104: 011ae820 ftintrne.l.d \$fa0, \$fa1 -+ 108: 011b0420 ftint.w.s \$fa0, \$fa1 -+ 10c: 011b0820 ftint.w.d \$fa0, \$fa1 -+ 110: 011b2420 ftint.l.s \$fa0, \$fa1 -+ 114: 011b2820 ftint.l.d \$fa0, \$fa1 -+ 118: 011d1020 ffint.s.w \$fa0, \$fa1 -+ 11c: 011d1820 ffint.s.l \$fa0, \$fa1 -+ 120: 011d2020 ffint.d.w \$fa0, \$fa1 -+ 124: 011d2820 ffint.d.l \$fa0, \$fa1 -+ 128: 011e4420 frint.s \$fa0, \$fa1 -+ 12c: 011e4820 frint.d \$fa0, \$fa1 -+ 130: 01147420 frecipe.s \$fa0, \$fa1 -+ 134: 01147820 frecipe.d \$fa0, \$fa1 -+ 138: 01148420 frsqrte.s \$fa0, \$fa1 -+ 13c: 01148820 frsqrte.d \$fa0, \$fa1 -+ 140: 08118820 fmadd.s \$fa0, \$fa1, \$fa2, \$fa3 -+ 144: 08218820 fmadd.d \$fa0, \$fa1, \$fa2, \$fa3 -+ 148: 08518820 fmsub.s \$fa0, \$fa1, \$fa2, \$fa3 -+ 14c: 08618820 fmsub.d \$fa0, \$fa1, \$fa2, \$fa3 -+ 150: 08918820 fnmadd.s \$fa0, \$fa1, \$fa2, \$fa3 -+ 154: 08a18820 fnmadd.d \$fa0, \$fa1, \$fa2, \$fa3 -+ 158: 08d18820 fnmsub.s \$fa0, \$fa1, \$fa2, \$fa3 -+ 15c: 08e18820 fnmsub.d \$fa0, \$fa1, \$fa2, \$fa3 -+ 160: 0c100820 fcmp.caf.s \$fcc0, \$fa1, \$fa2 -+ 164: 0c108820 fcmp.saf.s \$fcc0, \$fa1, \$fa2 -+ 168: 0c110820 fcmp.clt.s \$fcc0, \$fa1, \$fa2 -+ 16c: 0c118820 fcmp.slt.s \$fcc0, \$fa1, \$fa2 -+ 170: 0c118820 fcmp.slt.s \$fcc0, \$fa1, \$fa2 -+ 174: 0c120820 fcmp.ceq.s \$fcc0, \$fa1, \$fa2 -+ 178: 0c128820 fcmp.seq.s \$fcc0, \$fa1, \$fa2 -+ 17c: 0c130820 fcmp.cle.s \$fcc0, \$fa1, \$fa2 -+ 180: 0c138820 fcmp.sle.s \$fcc0, \$fa1, \$fa2 -+ 184: 0c138820 fcmp.sle.s \$fcc0, \$fa1, \$fa2 -+ 188: 0c140820 fcmp.cun.s \$fcc0, \$fa1, \$fa2 -+ 18c: 0c148820 fcmp.sun.s \$fcc0, \$fa1, \$fa2 -+ 190: 0c150820 fcmp.cult.s \$fcc0, \$fa1, \$fa2 -+ 194: 0c150820 fcmp.cult.s \$fcc0, \$fa1, \$fa2 -+ 198: 0c158820 fcmp.sult.s \$fcc0, \$fa1, \$fa2 -+ 19c: 0c160820 fcmp.cueq.s \$fcc0, \$fa1, \$fa2 -+ 1a0: 0c168820 fcmp.sueq.s \$fcc0, \$fa1, \$fa2 -+ 1a4: 0c170820 fcmp.cule.s \$fcc0, \$fa1, \$fa2 -+ 1a8: 0c170820 fcmp.cule.s \$fcc0, \$fa1, \$fa2 -+ 1ac: 0c178820 fcmp.sule.s \$fcc0, \$fa1, \$fa2 -+ 1b0: 0c180820 fcmp.cne.s \$fcc0, \$fa1, \$fa2 -+ 1b4: 0c188820 fcmp.sne.s \$fcc0, \$fa1, \$fa2 -+ 1b8: 0c1a0820 fcmp.cor.s \$fcc0, \$fa1, \$fa2 -+ 1bc: 0c1a8820 fcmp.sor.s \$fcc0, \$fa1, \$fa2 -+ 1c0: 0c1c0820 fcmp.cune.s \$fcc0, \$fa1, \$fa2 -+ 1c4: 0c1c8820 fcmp.sune.s \$fcc0, \$fa1, \$fa2 -+ 1c8: 0c200820 fcmp.caf.d \$fcc0, \$fa1, \$fa2 -+ 1cc: 0c208820 fcmp.saf.d \$fcc0, \$fa1, \$fa2 -+ 1d0: 0c210820 fcmp.clt.d \$fcc0, \$fa1, \$fa2 -+ 1d4: 0c218820 fcmp.slt.d \$fcc0, \$fa1, \$fa2 -+ 1d8: 0c218820 fcmp.slt.d \$fcc0, \$fa1, \$fa2 -+ 1dc: 0c220820 fcmp.ceq.d \$fcc0, \$fa1, \$fa2 -+ 1e0: 0c228820 fcmp.seq.d \$fcc0, \$fa1, \$fa2 -+ 1e4: 0c230820 fcmp.cle.d \$fcc0, \$fa1, \$fa2 -+ 1e8: 0c238820 fcmp.sle.d \$fcc0, \$fa1, \$fa2 -+ 1ec: 0c238820 fcmp.sle.d \$fcc0, \$fa1, \$fa2 -+ 1f0: 0c240820 fcmp.cun.d \$fcc0, \$fa1, \$fa2 -+ 1f4: 0c248820 fcmp.sun.d \$fcc0, \$fa1, \$fa2 -+ 1f8: 0c250820 fcmp.cult.d \$fcc0, \$fa1, \$fa2 -+ 1fc: 0c250820 fcmp.cult.d \$fcc0, \$fa1, \$fa2 -+ 200: 0c258820 fcmp.sult.d \$fcc0, \$fa1, \$fa2 -+ 204: 0c260820 fcmp.cueq.d \$fcc0, \$fa1, \$fa2 -+ 208: 0c268820 fcmp.sueq.d \$fcc0, \$fa1, \$fa2 -+ 20c: 0c270820 fcmp.cule.d \$fcc0, \$fa1, \$fa2 -+ 210: 0c270820 fcmp.cule.d \$fcc0, \$fa1, \$fa2 -+ 214: 0c278820 fcmp.sule.d \$fcc0, \$fa1, \$fa2 -+ 218: 0c280820 fcmp.cne.d \$fcc0, \$fa1, \$fa2 -+ 21c: 0c288820 fcmp.sne.d \$fcc0, \$fa1, \$fa2 -+ 220: 0c2a0820 fcmp.cor.d \$fcc0, \$fa1, \$fa2 -+ 224: 0c2a8820 fcmp.sor.d \$fcc0, \$fa1, \$fa2 -+ 228: 0c2c0820 fcmp.cune.d \$fcc0, \$fa1, \$fa2 -+ 22c: 0c2c8820 fcmp.sune.d \$fcc0, \$fa1, \$fa2 -+ 230: 0d000820 fsel \$fa0, \$fa1, \$fa2, \$fcc0 -+ 234: 2b00058a fld.s \$ft2, \$t0, 1 -+ 238: 2b40058a fst.s \$ft2, \$t0, 1 -+ 23c: 2b80058a fld.d \$ft2, \$t0, 1 -+ 240: 2bc0058a fst.d \$ft2, \$t0, 1 -+ 244: 48000000 bceqz \$fcc0, 0 # 0x244 -+ 248: 48000100 bcnez \$fcc0, 0 # 0x248 -diff --git a/gas/testsuite/gas/loongarch/insn_float32.s b/gas/testsuite/gas/loongarch/insn_float32.s -new file mode 100644 -index 00000000..8465633b ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/insn_float32.s -@@ -0,0 +1,149 @@ -+fadd.s $f0,$f1,$f2 -+fadd.d $f0,$f1,$f2 -+fsub.s $f0,$f1,$f2 -+fsub.d $f0,$f1,$f2 -+fmul.s $f0,$f1,$f2 -+fmul.d $f0,$f1,$f2 -+fdiv.s $f0,$f1,$f2 -+fdiv.d $f0,$f1,$f2 -+fmax.s $f0,$f1,$f2 -+fmax.d $f0,$f1,$f2 -+fmin.s $f0,$f1,$f2 -+fmin.d $f0,$f1,$f2 -+fmaxa.s $f0,$f1,$f2 -+fmaxa.d $f0,$f1,$f2 -+fmina.s $f0,$f1,$f2 -+fmina.d $f0,$f1,$f2 -+fscaleb.s $f0,$f1,$f2 -+fscaleb.d $f0,$f1,$f2 -+fcopysign.s $f0,$f1,$f2 -+fcopysign.d $f0,$f1,$f2 -+fabs.s $f0,$f1 -+fabs.d $f0,$f1 -+fneg.s $f0,$f1 -+fneg.d $f0,$f1 -+flogb.s $f0,$f1 -+flogb.d $f0,$f1 -+fclass.s $f0,$f1 -+fclass.d $f0,$f1 -+fsqrt.s $f0,$f1 -+fsqrt.d $f0,$f1 -+frecip.s $f0,$f1 -+frecip.d $f0,$f1 -+frsqrt.s $f0,$f1 -+frsqrt.d $f0,$f1 -+fmov.s $f0,$f1 -+fmov.d $f0,$f1 -+movgr2fr.w $f0,$r5 -+movgr2fr.d $f0,$r5 -+movgr2frh.w $f0,$r5 -+movfr2gr.s $r4,$f1 -+movfr2gr.d $r4,$f1 -+movfrh2gr.s $r4,$f1 -+movgr2fcsr $fcsr0,$r5 -+movfcsr2gr $r4,$fcsr0 -+movfr2cf $fcc0,$f1 -+movcf2fr $f0,$fcc5 -+movgr2cf $fcc0,$r5 -+movcf2gr $r4,$fcc5 -+fcvt.s.d $f0,$f1 -+fcvt.d.s $f0,$f1 -+ftintrm.w.s $f0,$f1 -+ftintrm.w.d $f0,$f1 -+ftintrm.l.s $f0,$f1 -+ftintrm.l.d $f0,$f1 -+ftintrp.w.s $f0,$f1 -+ftintrp.w.d $f0,$f1 -+ftintrp.l.s $f0,$f1 -+ftintrp.l.d $f0,$f1 -+ftintrz.w.s $f0,$f1 -+ftintrz.w.d $f0,$f1 -+ftintrz.l.s $f0,$f1 -+ftintrz.l.d $f0,$f1 -+ftintrne.w.s $f0,$f1 -+ftintrne.w.d $f0,$f1 -+ftintrne.l.s $f0,$f1 -+ftintrne.l.d $f0,$f1 -+ftint.w.s $f0,$f1 -+ftint.w.d $f0,$f1 -+ftint.l.s $f0,$f1 -+ftint.l.d $f0,$f1 -+ffint.s.w $f0,$f1 -+ffint.s.l $f0,$f1 -+ffint.d.w $f0,$f1 -+ffint.d.l $f0,$f1 -+frint.s $f0,$f1 -+frint.d $f0,$f1 -+frecipe.s $f0,$f1 -+frecipe.d $f0,$f1 -+frsqrte.s $f0,$f1 -+frsqrte.d $f0,$f1 -+ -+# 4_opt_op -+fmadd.s $f0,$f1,$f2,$f3 -+fmadd.d $f0,$f1,$f2,$f3 -+fmsub.s $f0,$f1,$f2,$f3 -+fmsub.d $f0,$f1,$f2,$f3 -+fnmadd.s $f0,$f1,$f2,$f3 -+fnmadd.d $f0,$f1,$f2,$f3 -+fnmsub.s $f0,$f1,$f2,$f3 -+fnmsub.d $f0,$f1,$f2,$f3 -+fcmp.caf.s $fcc0,$f1,$f2 -+fcmp.saf.s $fcc0,$f1,$f2 -+fcmp.clt.s $fcc0,$f1,$f2 -+fcmp.slt.s $fcc0,$f1,$f2 -+fcmp.sgt.s $fcc0,$f2,$f1 -+fcmp.ceq.s $fcc0,$f1,$f2 -+fcmp.seq.s $fcc0,$f1,$f2 -+fcmp.cle.s $fcc0,$f1,$f2 -+fcmp.sle.s $fcc0,$f1,$f2 -+fcmp.sge.s $fcc0,$f2,$f1 -+fcmp.cun.s $fcc0,$f1,$f2 -+fcmp.sun.s $fcc0,$f1,$f2 -+fcmp.cult.s $fcc0,$f1,$f2 -+fcmp.cugt.s $fcc0,$f2,$f1 -+fcmp.sult.s $fcc0,$f1,$f2 -+fcmp.cueq.s $fcc0,$f1,$f2 -+fcmp.sueq.s $fcc0,$f1,$f2 -+fcmp.cule.s $fcc0,$f1,$f2 -+fcmp.cuge.s $fcc0,$f2,$f1 -+fcmp.sule.s $fcc0,$f1,$f2 -+fcmp.cne.s $fcc0,$f1,$f2 -+fcmp.sne.s $fcc0,$f1,$f2 -+fcmp.cor.s $fcc0,$f1,$f2 -+fcmp.sor.s $fcc0,$f1,$f2 -+fcmp.cune.s $fcc0,$f1,$f2 -+fcmp.sune.s $fcc0,$f1,$f2 -+fcmp.caf.d $fcc0,$f1,$f2 -+fcmp.saf.d $fcc0,$f1,$f2 -+fcmp.clt.d $fcc0,$f1,$f2 -+fcmp.slt.d $fcc0,$f1,$f2 -+fcmp.sgt.d $fcc0,$f2,$f1 -+fcmp.ceq.d $fcc0,$f1,$f2 -+fcmp.seq.d $fcc0,$f1,$f2 -+fcmp.cle.d $fcc0,$f1,$f2 -+fcmp.sle.d $fcc0,$f1,$f2 -+fcmp.sge.d $fcc0,$f2,$f1 -+fcmp.cun.d $fcc0,$f1,$f2 -+fcmp.sun.d $fcc0,$f1,$f2 -+fcmp.cult.d $fcc0,$f1,$f2 -+fcmp.cugt.d $fcc0,$f2,$f1 -+fcmp.sult.d $fcc0,$f1,$f2 -+fcmp.cueq.d $fcc0,$f1,$f2 -+fcmp.sueq.d $fcc0,$f1,$f2 -+fcmp.cule.d $fcc0,$f1,$f2 -+fcmp.cuge.d $fcc0,$f2,$f1 -+fcmp.sule.d $fcc0,$f1,$f2 -+fcmp.cne.d $fcc0,$f1,$f2 -+fcmp.sne.d $fcc0,$f1,$f2 -+fcmp.cor.d $fcc0,$f1,$f2 -+fcmp.sor.d $fcc0,$f1,$f2 -+fcmp.cune.d $fcc0,$f1,$f2 -+fcmp.sune.d $fcc0,$f1,$f2 -+fsel $f0,$f1,$f2,$fcc0 -+fld.s $f10,$r12,1 -+fst.s $f10,$r12,1 -+fld.d $f10,$r12,1 -+fst.d $f10,$r12,1 -+bceqz $fcc0,.L1 -+bcnez $fcc0,.L1 -diff --git a/gas/testsuite/gas/loongarch/insn_int32.d b/gas/testsuite/gas/loongarch/insn_int32.d -new file mode 100644 -index 00000000..d90dbe40 ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/insn_int32.d -@@ -0,0 +1,147 @@ -+#as-new: -+#objdump: -d -M no-aliases -+#skip: loongarch64-*-* -+ -+.*: file format .* -+ -+ -+Disassembly of section .text: -+ -+0+ <.*>: -+ 0: 020000a4 slti \$a0, \$a1, 0 -+ 4: 021ffca4 slti \$a0, \$a1, 2047 -+ 8: 022004a4 slti \$a0, \$a1, -2047 -+ c: 024000a4 sltui \$a0, \$a1, 0 -+ 10: 025ffca4 sltui \$a0, \$a1, 2047 -+ 14: 026004a4 sltui \$a0, \$a1, -2047 -+ 18: 028000a4 addi.w \$a0, \$a1, 0 -+ 1c: 029ffca4 addi.w \$a0, \$a1, 2047 -+ 20: 02a004a4 addi.w \$a0, \$a1, -2047 -+ 24: 034000a4 andi \$a0, \$a1, 0x0 -+ 28: 035ffca4 andi \$a0, \$a1, 0x7ff -+ 2c: 038000a4 ori \$a0, \$a1, 0x0 -+ 30: 039ffca4 ori \$a0, \$a1, 0x7ff -+ 34: 03c000a4 xori \$a0, \$a1, 0x0 -+ 38: 03dffca4 xori \$a0, \$a1, 0x7ff -+ 3c: 14000004 lu12i.w \$a0, 0 -+ 40: 14ffffe4 lu12i.w \$a0, 524287 -+ 44: 1c000004 pcaddu12i \$a0, 0 -+ 48: 1cffffe4 pcaddu12i \$a0, 524287 -+ 4c: 1d000024 pcaddu12i \$a0, -524287 -+ 50: 0004b58b alsl.w \$a7, \$t0, \$t1, 0x2 -+ 54: 0006b58b alsl.wu \$a7, \$t0, \$t1, 0x2 -+ 58: 002a0002 break 0x2 -+ 5c: 002a8002 dbcl 0x2 -+ 60: 002b0002 syscall 0x2 -+ 64: 0040898b slli.w \$a7, \$t0, 0x2 -+ 68: 0044898b srli.w \$a7, \$t0, 0x2 -+ 6c: 004889ac srai.w \$t0, \$t1, 0x2 -+ 70: 02048dac slti \$t0, \$t1, 291 -+ 74: 02448dac sltui \$t0, \$t1, 291 -+ 78: 02848dac addi.w \$t0, \$t1, 291 -+ 7c: 034009ac andi \$t0, \$t1, 0x2 -+ 80: 038009ac ori \$t0, \$t1, 0x2 -+ 84: 03c009ac xori \$t0, \$t1, 0x2 -+ 88: 1400246c lu12i.w \$t0, 291 -+ 8c: 1c00246c pcaddu12i \$t0, 291 -+ 90: 04048c0c csrrd \$t0, 0x123 -+ 94: 04048c2c csrwr \$t0, 0x123 -+ 98: 040009ac csrxchg \$t0, \$t1, 0x2 -+ 9c: 060009a2 cacop 0x2, \$t1, 2 -+ a0: 064009ac lddir \$t0, \$t1, 0x2 -+ a4: 06440980 ldpte \$t0, 0x2 -+ a8: 0649b9a2 invtlb 0x2, \$t1, \$t2 -+ ac: 000060a4 rdtimel.w \$a0, \$a1 -+ b0: 000064a4 rdtimeh.w \$a0, \$a1 -+ b4: 000418a4 alsl.w \$a0, \$a1, \$a2, 0x1 -+ b8: 000598a4 alsl.w \$a0, \$a1, \$a2, 0x4 -+ bc: 000618a4 alsl.wu \$a0, \$a1, \$a2, 0x1 -+ c0: 000798a4 alsl.wu \$a0, \$a1, \$a2, 0x4 -+ c4: 001018a4 add.w \$a0, \$a1, \$a2 -+ c8: 001118a4 sub.w \$a0, \$a1, \$a2 -+ cc: 001218a4 slt \$a0, \$a1, \$a2 -+ d0: 001298a4 sltu \$a0, \$a1, \$a2 -+ d4: 001418a4 nor \$a0, \$a1, \$a2 -+ d8: 001498a4 and \$a0, \$a1, \$a2 -+ dc: 001518a4 or \$a0, \$a1, \$a2 -+ e0: 001598a4 xor \$a0, \$a1, \$a2 -+ e4: 001718a4 sll.w \$a0, \$a1, \$a2 -+ e8: 001798a4 srl.w \$a0, \$a1, \$a2 -+ ec: 001818a4 sra.w \$a0, \$a1, \$a2 -+ f0: 001c18a4 mul.w \$a0, \$a1, \$a2 -+ f4: 001c98a4 mulh.w \$a0, \$a1, \$a2 -+ f8: 001d18a4 mulh.wu \$a0, \$a1, \$a2 -+ fc: 002018a4 div.w \$a0, \$a1, \$a2 -+ 100: 002098a4 mod.w \$a0, \$a1, \$a2 -+ 104: 002118a4 div.wu \$a0, \$a1, \$a2 -+ 108: 002198a4 mod.wu \$a0, \$a1, \$a2 -+ 10c: 002a0000 break 0x0 -+ 110: 002a7fff break 0x7fff -+ 114: 002a8000 dbcl 0x0 -+ 118: 002affff dbcl 0x7fff -+ 11c: 004080a4 slli.w \$a0, \$a1, 0x0 -+ 120: 004084a4 slli.w \$a0, \$a1, 0x1 -+ 124: 0040fca4 slli.w \$a0, \$a1, 0x1f -+ 128: 004480a4 srli.w \$a0, \$a1, 0x0 -+ 12c: 004484a4 srli.w \$a0, \$a1, 0x1 -+ 130: 0044fca4 srli.w \$a0, \$a1, 0x1f -+ 134: 004880a4 srai.w \$a0, \$a1, 0x0 -+ 138: 004884a4 srai.w \$a0, \$a1, 0x1 -+ 13c: 0048fca4 srai.w \$a0, \$a1, 0x1f -+ 140: 200000a4 ll.w \$a0, \$a1, 0 -+ 144: 203ffca4 ll.w \$a0, \$a1, 16380 -+ 148: 210000a4 sc.w \$a0, \$a1, 0 -+ 14c: 213ffca4 sc.w \$a0, \$a1, 16380 -+ 150: 280000a4 ld.b \$a0, \$a1, 0 -+ 154: 281ffca4 ld.b \$a0, \$a1, 2047 -+ 158: 282004a4 ld.b \$a0, \$a1, -2047 -+ 15c: 284000a4 ld.h \$a0, \$a1, 0 -+ 160: 285ffca4 ld.h \$a0, \$a1, 2047 -+ 164: 286004a4 ld.h \$a0, \$a1, -2047 -+ 168: 288000a4 ld.w \$a0, \$a1, 0 -+ 16c: 289ffca4 ld.w \$a0, \$a1, 2047 -+ 170: 28a004a4 ld.w \$a0, \$a1, -2047 -+ 174: 290000a4 st.b \$a0, \$a1, 0 -+ 178: 291ffca4 st.b \$a0, \$a1, 2047 -+ 17c: 292004a4 st.b \$a0, \$a1, -2047 -+ 180: 294000a4 st.h \$a0, \$a1, 0 -+ 184: 295ffca4 st.h \$a0, \$a1, 2047 -+ 188: 296004a4 st.h \$a0, \$a1, -2047 -+ 18c: 298000a4 st.w \$a0, \$a1, 0 -+ 190: 299ffca4 st.w \$a0, \$a1, 2047 -+ 194: 29a004a4 st.w \$a0, \$a1, -2047 -+ 198: 2a0000a4 ld.bu \$a0, \$a1, 0 -+ 19c: 2a1ffca4 ld.bu \$a0, \$a1, 2047 -+ 1a0: 2a2004a4 ld.bu \$a0, \$a1, -2047 -+ 1a4: 2a4000a4 ld.hu \$a0, \$a1, 0 -+ 1a8: 2a5ffca4 ld.hu \$a0, \$a1, 2047 -+ 1ac: 2a6004a4 ld.hu \$a0, \$a1, -2047 -+ 1b0: 2ac000a0 preld 0x0, \$a1, 0 -+ 1b4: 2adffcbf preld 0x1f, \$a1, 2047 -+ 1b8: 2ae004bf preld 0x1f, \$a1, -2047 -+ 1bc: 385714c4 sc.q \$a0, \$a1, \$a2 -+ 1c0: 385714c4 sc.q \$a0, \$a1, \$a2 -+ 1c4: 385780a4 llacq.w \$a0, \$a1 -+ 1c8: 385780a4 llacq.w \$a0, \$a1 -+ 1cc: 385784a4 screl.w \$a0, \$a1 -+ 1d0: 385784a4 screl.w \$a0, \$a1 -+ 1d4: 38720000 dbar 0x0 -+ 1d8: 38727fff dbar 0x7fff -+ 1dc: 38728000 ibar 0x0 -+ 1e0: 3872ffff ibar 0x7fff -+ -+0+1e4 <.L1>: -+ 1e4: 03400000 andi \$zero, \$zero, 0x0 -+ 1e8: 53ffffff b -4 # 1e4 <.L1> -+ 1ec: 57fffbff bl -8 # 1e4 <.L1> -+ 1f0: 5bfff485 beq \$a0, \$a1, -12 # 1e4 <.L1> -+ 1f4: 5ffff085 bne \$a0, \$a1, -16 # 1e4 <.L1> -+ 1f8: 63ffec85 blt \$a0, \$a1, -20 # 1e4 <.L1> -+ 1fc: 63ffe8a4 blt \$a1, \$a0, -24 # 1e4 <.L1> -+ 200: 67ffe485 bge \$a0, \$a1, -28 # 1e4 <.L1> -+ 204: 67ffe0a4 bge \$a1, \$a0, -32 # 1e4 <.L1> -+ 208: 6bffdc85 bltu \$a0, \$a1, -36 # 1e4 <.L1> -+ 20c: 6bffd8a4 bltu \$a1, \$a0, -40 # 1e4 <.L1> -+ 210: 6fffd485 bgeu \$a0, \$a1, -44 # 1e4 <.L1> -+ 214: 6fffd0a4 bgeu \$a1, \$a0, -48 # 1e4 <.L1> -+ 218: 4c000080 jirl \$zero, \$a0, 0 -diff --git a/gas/testsuite/gas/loongarch/insn_int32.s b/gas/testsuite/gas/loongarch/insn_int32.s -new file mode 100644 -index 00000000..4889df1f ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/insn_int32.s -@@ -0,0 +1,156 @@ -+# imm_op -+slti $r4,$r5,0 -+slti $r4,$r5,0x7ff -+slti $r4,$r5,-0x7ff -+sltui $r4,$r5,0 -+sltui $r4,$r5,0x7ff -+sltui $r4,$r5,-0x7ff -+addi.w $r4,$r5,0 -+addi.w $r4,$r5,0x7ff -+addi.w $r4,$r5,-0x7ff -+andi $r4,$r5,0 -+andi $r4,$r5,0x7ff -+ori $r4,$r5,0 -+ori $r4,$r5,0x7ff -+xori $r4,$r5,0 -+xori $r4,$r5,0x7ff -+lu12i.w $r4,0 -+lu12i.w $r4,0x7ffff -+pcaddu12i $r4,0 -+pcaddu12i $r4,0x7ffff -+pcaddu12i $r4,-0x7ffff -+ -+# imm_ins -+.equ a, 0x123 -+.equ b, 0xfffff00000 -+.equ c, 0xfffffffffff -+.equ d, 2 -+.equ e,0x100 -+ -+alsl.w $r11,$r12,$r13,d -+alsl.wu $r11,$r12,$r13,d -+ -+break d -+dbcl d -+syscall d -+ -+slli.w $r11,$r12,d -+srli.w $r11,$r12,d -+srai.w $r12,$r13,d -+ -+slti $r12,$r13,a -+sltui $r12,$r13,a -+addi.w $r12,$r13,a -+andi $r12,$r13,d -+ori $r12,$r13,d -+xori $r12,$r13,d -+lu12i.w $r12,a -+pcaddu12i $r12,a -+ -+csrrd $r12,a -+csrwr $r12,a -+csrxchg $r12,$r13,d -+cacop d,$r13,d -+lddir $r12,$r13,d -+ldpte $r12,d -+ -+invtlb d,$r13,$r14 -+ -+# fix_op -+rdtimel.w $r4,$r5 -+rdtimeh.w $r4,$r5 -+alsl.w $r4,$r5,$r6,1 -+alsl.w $r4,$r5,$r6,4 -+alsl.wu $r4,$r5,$r6,1 -+alsl.wu $r4,$r5,$r6,4 -+add.w $r4,$r5,$r6 -+sub.w $r4,$r5,$r6 -+slt $r4,$r5,$r6 -+sltu $r4,$r5,$r6 -+nor $r4,$r5,$r6 -+and $r4,$r5,$r6 -+or $r4,$r5,$r6 -+xor $r4,$r5,$r6 -+ -+# load_store -+sll.w $r4,$r5,$r6 -+srl.w $r4,$r5,$r6 -+sra.w $r4,$r5,$r6 -+mul.w $r4,$r5,$r6 -+mulh.w $r4,$r5,$r6 -+mulh.wu $r4,$r5,$r6 -+div.w $r4,$r5,$r6 -+mod.w $r4,$r5,$r6 -+div.wu $r4,$r5,$r6 -+mod.wu $r4,$r5,$r6 -+break 0 -+break 0x7fff -+dbcl 0 -+dbcl 0x7fff -+slli.w $r4,$r5,0 -+slli.w $r4,$r5,1 -+slli.w $r4,$r5,0x1f -+srli.w $r4,$r5,0 -+srli.w $r4,$r5,1 -+srli.w $r4,$r5,0x1f -+srai.w $r4,$r5,0 -+srai.w $r4,$r5,1 -+srai.w $r4,$r5,0x1f -+ll.w $r4,$r5,0 -+ll.w $r4,$r5,0x3ffc -+sc.w $r4,$r5,0 -+sc.w $r4,$r5,0x3ffc -+ld.b $r4,$r5,0 -+ld.b $r4,$r5,0x7ff -+ld.b $r4,$r5,-0x7ff -+ld.h $r4,$r5,0 -+ld.h $r4,$r5,0x7ff -+ld.h $r4,$r5,-0x7ff -+ld.w $r4,$r5,0 -+ld.w $r4,$r5,0x7ff -+ld.w $r4,$r5,-0x7ff -+st.b $r4,$r5,0 -+st.b $r4,$r5,0x7ff -+st.b $r4,$r5,-0x7ff -+st.h $r4,$r5,0 -+st.h $r4,$r5,0x7ff -+st.h $r4,$r5,-0x7ff -+st.w $r4,$r5,0 -+st.w $r4,$r5,0x7ff -+st.w $r4,$r5,-0x7ff -+ld.bu $r4,$r5,0 -+ld.bu $r4,$r5,0x7ff -+ld.bu $r4,$r5,-0x7ff -+ld.hu $r4,$r5,0 -+ld.hu $r4,$r5,0x7ff -+ld.hu $r4,$r5,-0x7ff -+preld 0,$r5,0 -+preld 31,$r5,0x7ff -+preld 31,$r5,-0x7ff -+sc.q $r4,$r5,$r6,0 -+sc.q $r4,$r5,$r6 -+llacq.w $r4,$r5,0 -+llacq.w $r4,$r5 -+screl.w $r4,$r5,0 -+screl.w $r4,$r5 -+dbar 0 -+dbar 0x7fff -+ibar 0 -+ibar 0x7fff -+ -+# jmp_op -+.L1: -+nop -+b .L1 -+bl .L1 -+beq $r4,$r5,.L1 -+bne $r4,$r5,.L1 -+blt $r4,$r5,.L1 -+bgt $r4,$r5,.L1 -+bge $r4,$r5,.L1 -+ble $r4,$r5,.L1 -+bltu $r4,$r5,.L1 -+bgtu $r4,$r5,.L1 -+bgeu $r4,$r5,.L1 -+bleu $r4,$r5,.L1 -+jirl $zero,$r4,0 --- -2.33.0 - diff --git a/LoongArch-Add-gas-testsuit-for-LA32-relocations.patch b/LoongArch-Add-gas-testsuit-for-LA32-relocations.patch deleted file mode 100644 index 2d29d27..0000000 --- a/LoongArch-Add-gas-testsuit-for-LA32-relocations.patch +++ /dev/null @@ -1,164 +0,0 @@ -From bed92cdad966e2a7b9cfea8a5113187304255968 Mon Sep 17 00:00:00 2001 -From: Lulu Cai -Date: Fri, 12 Jan 2024 11:15:10 +0800 -Subject: [PATCH 068/123] LoongArch: Add gas testsuit for LA32 relocations - -Test the relocation of the LA32 instruction set. ---- - gas/testsuite/gas/loongarch/relocs_32.d | 75 +++++++++++++++++++++++++ - gas/testsuite/gas/loongarch/relocs_32.s | 61 ++++++++++++++++++++ - 2 files changed, 136 insertions(+) - create mode 100644 gas/testsuite/gas/loongarch/relocs_32.d - create mode 100644 gas/testsuite/gas/loongarch/relocs_32.s - -diff --git a/gas/testsuite/gas/loongarch/relocs_32.d b/gas/testsuite/gas/loongarch/relocs_32.d -new file mode 100644 -index 00000000..3e1bb62e ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/relocs_32.d -@@ -0,0 +1,75 @@ -+#as: -mthin-add-sub -+#objdump: -dr -+#skip: loongarch64-*-* -+ -+.*:[ ]+file format .* -+ -+ -+Disassembly of section .text: -+ -+0+ <.*>: -+ 0: 4c0050a4 jirl \$a0, \$a1, 80 -+ 0: R_LARCH_B16 .L1 -+ 4: 50004c00 b 76 # 50 <.L1> -+ 4: R_LARCH_B26 .L1 -+ 8: 14000004 lu12i.w \$a0, 0 -+ 8: R_LARCH_ABS_HI20 .L1 -+ c: 038000a4 ori \$a0, \$a1, 0x0 -+ c: R_LARCH_ABS_LO12 .L1 -+ 10: 1a000004 pcalau12i \$a0, 0 -+ 10: R_LARCH_PCALA_HI20 .L1 -+ 14: 02800085 addi.w \$a1, \$a0, 0 -+ 14: R_LARCH_PCALA_LO12 .L1 -+ 18: 1a000004 pcalau12i \$a0, 0 -+ 18: R_LARCH_GOT_PC_HI20 .L1 -+ 1c: 28800085 ld.w \$a1, \$a0, 0 -+ 1c: R_LARCH_GOT_PC_LO12 .L1 -+ 20: 14000004 lu12i.w \$a0, 0 -+ 20: R_LARCH_GOT_HI20 .L1 -+ 24: 03800084 ori \$a0, \$a0, 0x0 -+ 24: R_LARCH_GOT_LO12 .L1 -+ 28: 14000004 lu12i.w \$a0, 0 -+ 28: R_LARCH_TLS_LE_HI20 TLSL1 -+ 2c: 03800085 ori \$a1, \$a0, 0x0 -+ 2c: R_LARCH_TLS_LE_LO12 TLSL1 -+ 30: 1a000004 pcalau12i \$a0, 0 -+ 30: R_LARCH_TLS_IE_PC_HI20 TLSL1 -+ 34: 02c00005 li.d \$a1, 0 -+ 34: R_LARCH_TLS_IE_PC_LO12 TLSL1 -+ 38: 14000004 lu12i.w \$a0, 0 -+ 38: R_LARCH_TLS_IE_HI20 TLSL1 -+ 3c: 03800084 ori \$a0, \$a0, 0x0 -+ 3c: R_LARCH_TLS_IE_LO12 TLSL1 -+ 40: 1a000004 pcalau12i \$a0, 0 -+ 40: R_LARCH_TLS_LD_PC_HI20 TLSL1 -+ 44: 14000004 lu12i.w \$a0, 0 -+ 44: R_LARCH_TLS_LD_HI20 TLSL1 -+ 48: 1a000004 pcalau12i \$a0, 0 -+ 48: R_LARCH_TLS_GD_PC_HI20 TLSL1 -+ 4c: 14000004 lu12i.w \$a0, 0 -+ 4c: R_LARCH_TLS_GD_HI20 TLSL1 -+ -+0+50 <.L1>: -+ 50: 00000000 .word 0x00000000 -+ 50: R_LARCH_32_PCREL .L2 -+ -+0+54 <.L2>: -+ 54: 03400000 nop -+ 58: 03400000 nop -+ 58: R_LARCH_ALIGN .* -+ 5c: 03400000 nop -+ 60: 03400000 nop -+ 64: 1800000c pcaddi \$t0, 0 -+ 64: R_LARCH_PCREL20_S2 .L1 -+ 68: 1a000004 pcalau12i \$a0, 0 -+ 68: R_LARCH_TLS_DESC_PC_HI20 TLSL1 -+ 6c: 028000a5 addi.w \$a1, \$a1, 0 -+ 6c: R_LARCH_TLS_DESC_PC_LO12 TLSL1 -+ 70: 14000004 lu12i.w \$a0, 0 -+ 70: R_LARCH_TLS_DESC_HI20 TLSL1 -+ 74: 03800084 ori \$a0, \$a0, 0x0 -+ 74: R_LARCH_TLS_DESC_LO12 TLSL1 -+ 78: 28800081 ld.w \$ra, \$a0, 0 -+ 78: R_LARCH_TLS_DESC_LD TLSL1 -+ 7c: 4c000021 jirl \$ra, \$ra, 0 -+ 7c: R_LARCH_TLS_DESC_CALL TLSL1 -diff --git a/gas/testsuite/gas/loongarch/relocs_32.s b/gas/testsuite/gas/loongarch/relocs_32.s -new file mode 100644 -index 00000000..c5139a75 ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/relocs_32.s -@@ -0,0 +1,61 @@ -+/* b16. */ -+jirl $r4,$r5,%b16(.L1) -+ -+/* b26. */ -+b %b26(.L1) -+ -+/* lu12i.w. */ -+lu12i.w $r4,%abs_hi20(.L1) -+ -+/* ori */ -+ori $r4,$r5,%abs_lo12(.L1) -+ -+pcalau12i $r4,%pc_hi20(.L1) -+addi.w $r5,$r4,%pc_lo12(.L1) -+ -+pcalau12i $r4,%got_pc_hi20(.L1) -+ld.w $r5,$r4,%got_pc_lo12(.L1) -+ -+lu12i.w $r4,%got_hi20(.L1) -+ori $r4,$r4,%got_lo12(.L1) -+ -+/* TLS LE. */ -+lu12i.w $r4,%le_hi20(TLSL1) -+ori $r5,$r4,%le_lo12(TLSL1) -+ -+/* Part of IE relocs. */ -+pcalau12i $r4,%ie_pc_hi20(TLSL1) -+addi.d $r5,$r0,%ie_pc_lo12(TLSL1) -+ -+lu12i.w $r4,%ie_hi20(TLSL1) -+ori $r4,$r4,%ie_lo12(TLSL1) -+ -+/* Part of LD relocs. */ -+pcalau12i $r4,%ld_pc_hi20(TLSL1) -+lu12i.w $r4,%ld_hi20(TLSL1) -+ -+/* Part of GD relocs. */ -+pcalau12i $r4,%gd_pc_hi20(TLSL1) -+lu12i.w $r4,%gd_hi20(TLSL1) -+ -+/* Test insn relocs. */ -+.L1: -+/* 32-bit PC relative. */ -+.4byte .L2-.L1 -+.L2: -+nop -+ -+/* R_LARCH_ALIGN. */ -+.align 4 -+ -+/* R_LARCH_PCREL20_S2. */ -+pcaddi $r12,.L1 -+ -+/* Part of DESC relocs. */ -+pcalau12i $r4,%desc_pc_hi20(TLSL1) -+addi.w $r5,$r5,%desc_pc_lo12(TLSL1) -+ -+lu12i.w $r4,%desc_hi20(TLSL1) -+ori $r4,$r4,%desc_lo12(TLSL1) -+ld.w $r1,$r4,%desc_ld(TLSL1) -+jirl $r1,$r1,%desc_call(TLSL1) --- -2.33.0 - diff --git a/LoongArch-Add-gas-testsuit-for-LA64-int-float-instru.patch b/LoongArch-Add-gas-testsuit-for-LA64-int-float-instru.patch deleted file mode 100644 index 94644d5..0000000 --- a/LoongArch-Add-gas-testsuit-for-LA64-int-float-instru.patch +++ /dev/null @@ -1,1237 +0,0 @@ -From 1d52dc328f178949b32251507572afb688e929d5 Mon Sep 17 00:00:00 2001 -From: Lulu Cai -Date: Wed, 10 Jan 2024 14:44:48 +0800 -Subject: [PATCH 065/123] LoongArch: Add gas testsuit for LA64 int/float - instructions - -Test the int/float instructions of LA64. ---- - gas/testsuite/gas/loongarch/insn_float64.d | 165 ++++++++ - gas/testsuite/gas/loongarch/insn_float64.s | 157 ++++++++ - gas/testsuite/gas/loongarch/insn_int64.d | 430 ++++++++++++++++++++ - gas/testsuite/gas/loongarch/insn_int64.s | 440 +++++++++++++++++++++ - 4 files changed, 1192 insertions(+) - create mode 100644 gas/testsuite/gas/loongarch/insn_float64.d - create mode 100644 gas/testsuite/gas/loongarch/insn_float64.s - create mode 100644 gas/testsuite/gas/loongarch/insn_int64.d - create mode 100644 gas/testsuite/gas/loongarch/insn_int64.s - -diff --git a/gas/testsuite/gas/loongarch/insn_float64.d b/gas/testsuite/gas/loongarch/insn_float64.d -new file mode 100644 -index 00000000..4ffbfa78 ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/insn_float64.d -@@ -0,0 +1,165 @@ -+#as-new: -+#objdump: -d -+#skip: loongarch32-*-* -+ -+.*: file format .* -+ -+ -+Disassembly of section .text: -+ -+0+ <.*>: -+ 0: 01008820 fadd.s \$fa0, \$fa1, \$fa2 -+ 4: 01010820 fadd.d \$fa0, \$fa1, \$fa2 -+ 8: 01028820 fsub.s \$fa0, \$fa1, \$fa2 -+ c: 01030820 fsub.d \$fa0, \$fa1, \$fa2 -+ 10: 01048820 fmul.s \$fa0, \$fa1, \$fa2 -+ 14: 01050820 fmul.d \$fa0, \$fa1, \$fa2 -+ 18: 01068820 fdiv.s \$fa0, \$fa1, \$fa2 -+ 1c: 01070820 fdiv.d \$fa0, \$fa1, \$fa2 -+ 20: 01088820 fmax.s \$fa0, \$fa1, \$fa2 -+ 24: 01090820 fmax.d \$fa0, \$fa1, \$fa2 -+ 28: 010a8820 fmin.s \$fa0, \$fa1, \$fa2 -+ 2c: 010b0820 fmin.d \$fa0, \$fa1, \$fa2 -+ 30: 010c8820 fmaxa.s \$fa0, \$fa1, \$fa2 -+ 34: 010d0820 fmaxa.d \$fa0, \$fa1, \$fa2 -+ 38: 010e8820 fmina.s \$fa0, \$fa1, \$fa2 -+ 3c: 010f0820 fmina.d \$fa0, \$fa1, \$fa2 -+ 40: 01108820 fscaleb.s \$fa0, \$fa1, \$fa2 -+ 44: 01110820 fscaleb.d \$fa0, \$fa1, \$fa2 -+ 48: 01128820 fcopysign.s \$fa0, \$fa1, \$fa2 -+ 4c: 01130820 fcopysign.d \$fa0, \$fa1, \$fa2 -+ 50: 01140420 fabs.s \$fa0, \$fa1 -+ 54: 01140820 fabs.d \$fa0, \$fa1 -+ 58: 01141420 fneg.s \$fa0, \$fa1 -+ 5c: 01141820 fneg.d \$fa0, \$fa1 -+ 60: 01142420 flogb.s \$fa0, \$fa1 -+ 64: 01142820 flogb.d \$fa0, \$fa1 -+ 68: 01143420 fclass.s \$fa0, \$fa1 -+ 6c: 01143820 fclass.d \$fa0, \$fa1 -+ 70: 01144420 fsqrt.s \$fa0, \$fa1 -+ 74: 01144820 fsqrt.d \$fa0, \$fa1 -+ 78: 01145420 frecip.s \$fa0, \$fa1 -+ 7c: 01145820 frecip.d \$fa0, \$fa1 -+ 80: 01146420 frsqrt.s \$fa0, \$fa1 -+ 84: 01146820 frsqrt.d \$fa0, \$fa1 -+ 88: 01149420 fmov.s \$fa0, \$fa1 -+ 8c: 01149820 fmov.d \$fa0, \$fa1 -+ 90: 0114a4a0 movgr2fr.w \$fa0, \$a1 -+ 94: 0114a8a0 movgr2fr.d \$fa0, \$a1 -+ 98: 0114aca0 movgr2frh.w \$fa0, \$a1 -+ 9c: 0114b424 movfr2gr.s \$a0, \$fa1 -+ a0: 0114b824 movfr2gr.d \$a0, \$fa1 -+ a4: 0114bc24 movfrh2gr.s \$a0, \$fa1 -+ a8: 0114c0a0 movgr2fcsr \$fcsr0, \$a1 -+ ac: 0114c804 movfcsr2gr \$a0, \$fcsr0 -+ b0: 0114d020 movfr2cf \$fcc0, \$fa1 -+ b4: 0114d4a0 movcf2fr \$fa0, \$fcc5 -+ b8: 0114d8a0 movgr2cf \$fcc0, \$a1 -+ bc: 0114dca4 movcf2gr \$a0, \$fcc5 -+ c0: 01191820 fcvt.s.d \$fa0, \$fa1 -+ c4: 01192420 fcvt.d.s \$fa0, \$fa1 -+ c8: 011a0420 ftintrm.w.s \$fa0, \$fa1 -+ cc: 011a0820 ftintrm.w.d \$fa0, \$fa1 -+ d0: 011a2420 ftintrm.l.s \$fa0, \$fa1 -+ d4: 011a2820 ftintrm.l.d \$fa0, \$fa1 -+ d8: 011a4420 ftintrp.w.s \$fa0, \$fa1 -+ dc: 011a4820 ftintrp.w.d \$fa0, \$fa1 -+ e0: 011a6420 ftintrp.l.s \$fa0, \$fa1 -+ e4: 011a6820 ftintrp.l.d \$fa0, \$fa1 -+ e8: 011a8420 ftintrz.w.s \$fa0, \$fa1 -+ ec: 011a8820 ftintrz.w.d \$fa0, \$fa1 -+ f0: 011aa420 ftintrz.l.s \$fa0, \$fa1 -+ f4: 011aa820 ftintrz.l.d \$fa0, \$fa1 -+ f8: 011ac420 ftintrne.w.s \$fa0, \$fa1 -+ fc: 011ac820 ftintrne.w.d \$fa0, \$fa1 -+ 100: 011ae420 ftintrne.l.s \$fa0, \$fa1 -+ 104: 011ae820 ftintrne.l.d \$fa0, \$fa1 -+ 108: 011b0420 ftint.w.s \$fa0, \$fa1 -+ 10c: 011b0820 ftint.w.d \$fa0, \$fa1 -+ 110: 011b2420 ftint.l.s \$fa0, \$fa1 -+ 114: 011b2820 ftint.l.d \$fa0, \$fa1 -+ 118: 011d1020 ffint.s.w \$fa0, \$fa1 -+ 11c: 011d1820 ffint.s.l \$fa0, \$fa1 -+ 120: 011d2020 ffint.d.w \$fa0, \$fa1 -+ 124: 011d2820 ffint.d.l \$fa0, \$fa1 -+ 128: 011e4420 frint.s \$fa0, \$fa1 -+ 12c: 011e4820 frint.d \$fa0, \$fa1 -+ 130: 01147420 frecipe.s \$fa0, \$fa1 -+ 134: 01147820 frecipe.d \$fa0, \$fa1 -+ 138: 01148420 frsqrte.s \$fa0, \$fa1 -+ 13c: 01148820 frsqrte.d \$fa0, \$fa1 -+ 140: 08118820 fmadd.s \$fa0, \$fa1, \$fa2, \$fa3 -+ 144: 08218820 fmadd.d \$fa0, \$fa1, \$fa2, \$fa3 -+ 148: 08518820 fmsub.s \$fa0, \$fa1, \$fa2, \$fa3 -+ 14c: 08618820 fmsub.d \$fa0, \$fa1, \$fa2, \$fa3 -+ 150: 08918820 fnmadd.s \$fa0, \$fa1, \$fa2, \$fa3 -+ 154: 08a18820 fnmadd.d \$fa0, \$fa1, \$fa2, \$fa3 -+ 158: 08d18820 fnmsub.s \$fa0, \$fa1, \$fa2, \$fa3 -+ 15c: 08e18820 fnmsub.d \$fa0, \$fa1, \$fa2, \$fa3 -+ 160: 0c100820 fcmp.caf.s \$fcc0, \$fa1, \$fa2 -+ 164: 0c108820 fcmp.saf.s \$fcc0, \$fa1, \$fa2 -+ 168: 0c110820 fcmp.clt.s \$fcc0, \$fa1, \$fa2 -+ 16c: 0c118820 fcmp.slt.s \$fcc0, \$fa1, \$fa2 -+ 170: 0c118820 fcmp.slt.s \$fcc0, \$fa1, \$fa2 -+ 174: 0c120820 fcmp.ceq.s \$fcc0, \$fa1, \$fa2 -+ 178: 0c128820 fcmp.seq.s \$fcc0, \$fa1, \$fa2 -+ 17c: 0c130820 fcmp.cle.s \$fcc0, \$fa1, \$fa2 -+ 180: 0c138820 fcmp.sle.s \$fcc0, \$fa1, \$fa2 -+ 184: 0c138820 fcmp.sle.s \$fcc0, \$fa1, \$fa2 -+ 188: 0c140820 fcmp.cun.s \$fcc0, \$fa1, \$fa2 -+ 18c: 0c148820 fcmp.sun.s \$fcc0, \$fa1, \$fa2 -+ 190: 0c150820 fcmp.cult.s \$fcc0, \$fa1, \$fa2 -+ 194: 0c150820 fcmp.cult.s \$fcc0, \$fa1, \$fa2 -+ 198: 0c158820 fcmp.sult.s \$fcc0, \$fa1, \$fa2 -+ 19c: 0c160820 fcmp.cueq.s \$fcc0, \$fa1, \$fa2 -+ 1a0: 0c168820 fcmp.sueq.s \$fcc0, \$fa1, \$fa2 -+ 1a4: 0c170820 fcmp.cule.s \$fcc0, \$fa1, \$fa2 -+ 1a8: 0c170820 fcmp.cule.s \$fcc0, \$fa1, \$fa2 -+ 1ac: 0c178820 fcmp.sule.s \$fcc0, \$fa1, \$fa2 -+ 1b0: 0c180820 fcmp.cne.s \$fcc0, \$fa1, \$fa2 -+ 1b4: 0c188820 fcmp.sne.s \$fcc0, \$fa1, \$fa2 -+ 1b8: 0c1a0820 fcmp.cor.s \$fcc0, \$fa1, \$fa2 -+ 1bc: 0c1a8820 fcmp.sor.s \$fcc0, \$fa1, \$fa2 -+ 1c0: 0c1c0820 fcmp.cune.s \$fcc0, \$fa1, \$fa2 -+ 1c4: 0c1c8820 fcmp.sune.s \$fcc0, \$fa1, \$fa2 -+ 1c8: 0c200820 fcmp.caf.d \$fcc0, \$fa1, \$fa2 -+ 1cc: 0c208820 fcmp.saf.d \$fcc0, \$fa1, \$fa2 -+ 1d0: 0c210820 fcmp.clt.d \$fcc0, \$fa1, \$fa2 -+ 1d4: 0c218820 fcmp.slt.d \$fcc0, \$fa1, \$fa2 -+ 1d8: 0c218820 fcmp.slt.d \$fcc0, \$fa1, \$fa2 -+ 1dc: 0c220820 fcmp.ceq.d \$fcc0, \$fa1, \$fa2 -+ 1e0: 0c228820 fcmp.seq.d \$fcc0, \$fa1, \$fa2 -+ 1e4: 0c230820 fcmp.cle.d \$fcc0, \$fa1, \$fa2 -+ 1e8: 0c238820 fcmp.sle.d \$fcc0, \$fa1, \$fa2 -+ 1ec: 0c238820 fcmp.sle.d \$fcc0, \$fa1, \$fa2 -+ 1f0: 0c240820 fcmp.cun.d \$fcc0, \$fa1, \$fa2 -+ 1f4: 0c248820 fcmp.sun.d \$fcc0, \$fa1, \$fa2 -+ 1f8: 0c250820 fcmp.cult.d \$fcc0, \$fa1, \$fa2 -+ 1fc: 0c250820 fcmp.cult.d \$fcc0, \$fa1, \$fa2 -+ 200: 0c258820 fcmp.sult.d \$fcc0, \$fa1, \$fa2 -+ 204: 0c260820 fcmp.cueq.d \$fcc0, \$fa1, \$fa2 -+ 208: 0c268820 fcmp.sueq.d \$fcc0, \$fa1, \$fa2 -+ 20c: 0c270820 fcmp.cule.d \$fcc0, \$fa1, \$fa2 -+ 210: 0c270820 fcmp.cule.d \$fcc0, \$fa1, \$fa2 -+ 214: 0c278820 fcmp.sule.d \$fcc0, \$fa1, \$fa2 -+ 218: 0c280820 fcmp.cne.d \$fcc0, \$fa1, \$fa2 -+ 21c: 0c288820 fcmp.sne.d \$fcc0, \$fa1, \$fa2 -+ 220: 0c2a0820 fcmp.cor.d \$fcc0, \$fa1, \$fa2 -+ 224: 0c2a8820 fcmp.sor.d \$fcc0, \$fa1, \$fa2 -+ 228: 0c2c0820 fcmp.cune.d \$fcc0, \$fa1, \$fa2 -+ 22c: 0c2c8820 fcmp.sune.d \$fcc0, \$fa1, \$fa2 -+ 230: 0d000820 fsel \$fa0, \$fa1, \$fa2, \$fcc0 -+ 234: 2b00058a fld.s \$ft2, \$t0, 1 -+ 238: 2b40058a fst.s \$ft2, \$t0, 1 -+ 23c: 2b80058a fld.d \$ft2, \$t0, 1 -+ 240: 2bc0058a fst.d \$ft2, \$t0, 1 -+ 244: 38741480 fldgt.s \$fa0, \$a0, \$a1 -+ 248: 38749480 fldgt.d \$fa0, \$a0, \$a1 -+ 24c: 38751480 fldle.s \$fa0, \$a0, \$a1 -+ 250: 38759480 fldle.d \$fa0, \$a0, \$a1 -+ 254: 38761480 fstgt.s \$fa0, \$a0, \$a1 -+ 258: 38769480 fstgt.d \$fa0, \$a0, \$a1 -+ 25c: 38771480 fstle.s \$fa0, \$a0, \$a1 -+ 260: 38779480 fstle.d \$fa0, \$a0, \$a1 -+ 264: 48000000 bceqz \$fcc0, 0 # 0x264 -+ 268: 48000100 bcnez \$fcc0, 0 # 0x268 -diff --git a/gas/testsuite/gas/loongarch/insn_float64.s b/gas/testsuite/gas/loongarch/insn_float64.s -new file mode 100644 -index 00000000..a7ce56ef ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/insn_float64.s -@@ -0,0 +1,157 @@ -+fadd.s $f0,$f1,$f2 -+fadd.d $f0,$f1,$f2 -+fsub.s $f0,$f1,$f2 -+fsub.d $f0,$f1,$f2 -+fmul.s $f0,$f1,$f2 -+fmul.d $f0,$f1,$f2 -+fdiv.s $f0,$f1,$f2 -+fdiv.d $f0,$f1,$f2 -+fmax.s $f0,$f1,$f2 -+fmax.d $f0,$f1,$f2 -+fmin.s $f0,$f1,$f2 -+fmin.d $f0,$f1,$f2 -+fmaxa.s $f0,$f1,$f2 -+fmaxa.d $f0,$f1,$f2 -+fmina.s $f0,$f1,$f2 -+fmina.d $f0,$f1,$f2 -+fscaleb.s $f0,$f1,$f2 -+fscaleb.d $f0,$f1,$f2 -+fcopysign.s $f0,$f1,$f2 -+fcopysign.d $f0,$f1,$f2 -+fabs.s $f0,$f1 -+fabs.d $f0,$f1 -+fneg.s $f0,$f1 -+fneg.d $f0,$f1 -+flogb.s $f0,$f1 -+flogb.d $f0,$f1 -+fclass.s $f0,$f1 -+fclass.d $f0,$f1 -+fsqrt.s $f0,$f1 -+fsqrt.d $f0,$f1 -+frecip.s $f0,$f1 -+frecip.d $f0,$f1 -+frsqrt.s $f0,$f1 -+frsqrt.d $f0,$f1 -+fmov.s $f0,$f1 -+fmov.d $f0,$f1 -+movgr2fr.w $f0,$r5 -+movgr2fr.d $f0,$r5 -+movgr2frh.w $f0,$r5 -+movfr2gr.s $r4,$f1 -+movfr2gr.d $r4,$f1 -+movfrh2gr.s $r4,$f1 -+movgr2fcsr $fcsr0,$r5 -+movfcsr2gr $r4,$fcsr0 -+movfr2cf $fcc0,$f1 -+movcf2fr $f0,$fcc5 -+movgr2cf $fcc0,$r5 -+movcf2gr $r4,$fcc5 -+fcvt.s.d $f0,$f1 -+fcvt.d.s $f0,$f1 -+ftintrm.w.s $f0,$f1 -+ftintrm.w.d $f0,$f1 -+ftintrm.l.s $f0,$f1 -+ftintrm.l.d $f0,$f1 -+ftintrp.w.s $f0,$f1 -+ftintrp.w.d $f0,$f1 -+ftintrp.l.s $f0,$f1 -+ftintrp.l.d $f0,$f1 -+ftintrz.w.s $f0,$f1 -+ftintrz.w.d $f0,$f1 -+ftintrz.l.s $f0,$f1 -+ftintrz.l.d $f0,$f1 -+ftintrne.w.s $f0,$f1 -+ftintrne.w.d $f0,$f1 -+ftintrne.l.s $f0,$f1 -+ftintrne.l.d $f0,$f1 -+ftint.w.s $f0,$f1 -+ftint.w.d $f0,$f1 -+ftint.l.s $f0,$f1 -+ftint.l.d $f0,$f1 -+ffint.s.w $f0,$f1 -+ffint.s.l $f0,$f1 -+ffint.d.w $f0,$f1 -+ffint.d.l $f0,$f1 -+frint.s $f0,$f1 -+frint.d $f0,$f1 -+frecipe.s $f0,$f1 -+frecipe.d $f0,$f1 -+frsqrte.s $f0,$f1 -+frsqrte.d $f0,$f1 -+ -+# 4_opt_op -+fmadd.s $f0,$f1,$f2,$f3 -+fmadd.d $f0,$f1,$f2,$f3 -+fmsub.s $f0,$f1,$f2,$f3 -+fmsub.d $f0,$f1,$f2,$f3 -+fnmadd.s $f0,$f1,$f2,$f3 -+fnmadd.d $f0,$f1,$f2,$f3 -+fnmsub.s $f0,$f1,$f2,$f3 -+fnmsub.d $f0,$f1,$f2,$f3 -+fcmp.caf.s $fcc0,$f1,$f2 -+fcmp.saf.s $fcc0,$f1,$f2 -+fcmp.clt.s $fcc0,$f1,$f2 -+fcmp.slt.s $fcc0,$f1,$f2 -+fcmp.sgt.s $fcc0,$f2,$f1 -+fcmp.ceq.s $fcc0,$f1,$f2 -+fcmp.seq.s $fcc0,$f1,$f2 -+fcmp.cle.s $fcc0,$f1,$f2 -+fcmp.sle.s $fcc0,$f1,$f2 -+fcmp.sge.s $fcc0,$f2,$f1 -+fcmp.cun.s $fcc0,$f1,$f2 -+fcmp.sun.s $fcc0,$f1,$f2 -+fcmp.cult.s $fcc0,$f1,$f2 -+fcmp.cugt.s $fcc0,$f2,$f1 -+fcmp.sult.s $fcc0,$f1,$f2 -+fcmp.cueq.s $fcc0,$f1,$f2 -+fcmp.sueq.s $fcc0,$f1,$f2 -+fcmp.cule.s $fcc0,$f1,$f2 -+fcmp.cuge.s $fcc0,$f2,$f1 -+fcmp.sule.s $fcc0,$f1,$f2 -+fcmp.cne.s $fcc0,$f1,$f2 -+fcmp.sne.s $fcc0,$f1,$f2 -+fcmp.cor.s $fcc0,$f1,$f2 -+fcmp.sor.s $fcc0,$f1,$f2 -+fcmp.cune.s $fcc0,$f1,$f2 -+fcmp.sune.s $fcc0,$f1,$f2 -+fcmp.caf.d $fcc0,$f1,$f2 -+fcmp.saf.d $fcc0,$f1,$f2 -+fcmp.clt.d $fcc0,$f1,$f2 -+fcmp.slt.d $fcc0,$f1,$f2 -+fcmp.sgt.d $fcc0,$f2,$f1 -+fcmp.ceq.d $fcc0,$f1,$f2 -+fcmp.seq.d $fcc0,$f1,$f2 -+fcmp.cle.d $fcc0,$f1,$f2 -+fcmp.sle.d $fcc0,$f1,$f2 -+fcmp.sge.d $fcc0,$f2,$f1 -+fcmp.cun.d $fcc0,$f1,$f2 -+fcmp.sun.d $fcc0,$f1,$f2 -+fcmp.cult.d $fcc0,$f1,$f2 -+fcmp.cugt.d $fcc0,$f2,$f1 -+fcmp.sult.d $fcc0,$f1,$f2 -+fcmp.cueq.d $fcc0,$f1,$f2 -+fcmp.sueq.d $fcc0,$f1,$f2 -+fcmp.cule.d $fcc0,$f1,$f2 -+fcmp.cuge.d $fcc0,$f2,$f1 -+fcmp.sule.d $fcc0,$f1,$f2 -+fcmp.cne.d $fcc0,$f1,$f2 -+fcmp.sne.d $fcc0,$f1,$f2 -+fcmp.cor.d $fcc0,$f1,$f2 -+fcmp.sor.d $fcc0,$f1,$f2 -+fcmp.cune.d $fcc0,$f1,$f2 -+fcmp.sune.d $fcc0,$f1,$f2 -+fsel $f0,$f1,$f2,$fcc0 -+fld.s $f10,$r12,1 -+fst.s $f10,$r12,1 -+fld.d $f10,$r12,1 -+fst.d $f10,$r12,1 -+fldgt.s $f0,$a0,$a1 -+fldgt.d $f0,$a0,$a1 -+fldle.s $f0,$a0,$a1 -+fldle.d $f0,$a0,$a1 -+fstgt.s $f0,$a0,$a1 -+fstgt.d $f0,$a0,$a1 -+fstle.s $f0,$a0,$a1 -+fstle.d $f0,$a0,$a1 -+bceqz $fcc0,.L1 -+bcnez $fcc0,.L1 -diff --git a/gas/testsuite/gas/loongarch/insn_int64.d b/gas/testsuite/gas/loongarch/insn_int64.d -new file mode 100644 -index 00000000..360b840d ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/insn_int64.d -@@ -0,0 +1,430 @@ -+#as-new: -+#objdump: -d -M no-aliases -+#skip: loongarch32-*-* -+ -+.*: file format .* -+ -+ -+Disassembly of section .text: -+ -+0+ <.*>: -+ 0: 020000a4 slti \$a0, \$a1, 0 -+ 4: 021ffca4 slti \$a0, \$a1, 2047 -+ 8: 022004a4 slti \$a0, \$a1, -2047 -+ c: 024000a4 sltui \$a0, \$a1, 0 -+ 10: 025ffca4 sltui \$a0, \$a1, 2047 -+ 14: 026004a4 sltui \$a0, \$a1, -2047 -+ 18: 028000a4 addi.w \$a0, \$a1, 0 -+ 1c: 029ffca4 addi.w \$a0, \$a1, 2047 -+ 20: 02a004a4 addi.w \$a0, \$a1, -2047 -+ 24: 02c000a4 addi.d \$a0, \$a1, 0 -+ 28: 02dffca4 addi.d \$a0, \$a1, 2047 -+ 2c: 02e004a4 addi.d \$a0, \$a1, -2047 -+ 30: 030000a4 lu52i.d \$a0, \$a1, 0 -+ 34: 031ffca4 lu52i.d \$a0, \$a1, 2047 -+ 38: 032004a4 lu52i.d \$a0, \$a1, -2047 -+ 3c: 034000a4 andi \$a0, \$a1, 0x0 -+ 40: 035ffca4 andi \$a0, \$a1, 0x7ff -+ 44: 038000a4 ori \$a0, \$a1, 0x0 -+ 48: 039ffca4 ori \$a0, \$a1, 0x7ff -+ 4c: 03c000a4 xori \$a0, \$a1, 0x0 -+ 50: 03dffca4 xori \$a0, \$a1, 0x7ff -+ 54: 100000a4 addu16i.d \$a0, \$a1, 0 -+ 58: 11fffca4 addu16i.d \$a0, \$a1, 32767 -+ 5c: 120004a4 addu16i.d \$a0, \$a1, -32767 -+ 60: 14000004 lu12i.w \$a0, 0 -+ 64: 14ffffe4 lu12i.w \$a0, 524287 -+ 68: 17000024 lu32i.d \$a0, -524287 -+ 6c: 18000004 pcaddi \$a0, 0 -+ 70: 18ffffe4 pcaddi \$a0, 524287 -+ 74: 19000004 pcaddi \$a0, -524288 -+ 78: 1a000004 pcalau12i \$a0, 0 -+ 7c: 1affffe4 pcalau12i \$a0, 524287 -+ 80: 1b000024 pcalau12i \$a0, -524287 -+ 84: 1c000004 pcaddu12i \$a0, 0 -+ 88: 1cffffe4 pcaddu12i \$a0, 524287 -+ 8c: 1d000024 pcaddu12i \$a0, -524287 -+ 90: 1e000004 pcaddu18i \$a0, 0 -+ 94: 1effffe4 pcaddu18i \$a0, 524287 -+ 98: 1f000024 pcaddu18i \$a0, -524287 -+ 9c: 0004b58b alsl.w \$a7, \$t0, \$t1, 0x2 -+ a0: 0006b58b alsl.wu \$a7, \$t0, \$t1, 0x2 -+ a4: 0009358b bytepick.w \$a7, \$t0, \$t1, 0x2 -+ a8: 000d358b bytepick.d \$a7, \$t0, \$t1, 0x2 -+ ac: 002a0002 break 0x2 -+ b0: 002a8002 dbcl 0x2 -+ b4: 002b0002 syscall 0x2 -+ b8: 002cb58b alsl.d \$a7, \$t0, \$t1, 0x2 -+ bc: 0040898b slli.w \$a7, \$t0, 0x2 -+ c0: 0041098b slli.d \$a7, \$t0, 0x2 -+ c4: 0044898b srli.w \$a7, \$t0, 0x2 -+ c8: 004509ac srli.d \$t0, \$t1, 0x2 -+ cc: 004889ac srai.w \$t0, \$t1, 0x2 -+ d0: 004909ac srai.d \$t0, \$t1, 0x2 -+ d4: 006209ac bstrins.w \$t0, \$t1, 0x2, 0x2 -+ d8: 008209ac bstrins.d \$t0, \$t1, 0x2, 0x2 -+ dc: 00c209ac bstrpick.d \$t0, \$t1, 0x2, 0x2 -+ e0: 00c209ac bstrpick.d \$t0, \$t1, 0x2, 0x2 -+ e4: 02048dac slti \$t0, \$t1, 291 -+ e8: 02448dac sltui \$t0, \$t1, 291 -+ ec: 02848dac addi.w \$t0, \$t1, 291 -+ f0: 02c48dac addi.d \$t0, \$t1, 291 -+ f4: 03048dac lu52i.d \$t0, \$t1, 291 -+ f8: 034009ac andi \$t0, \$t1, 0x2 -+ fc: 038009ac ori \$t0, \$t1, 0x2 -+ 100: 03c009ac xori \$t0, \$t1, 0x2 -+ 104: 100009ac addu16i.d \$t0, \$t1, 2 -+ 108: 1400246c lu12i.w \$t0, 291 -+ 10c: 1600246c lu32i.d \$t0, 291 -+ 110: 1800000c pcaddi \$t0, 0 -+ 114: 1a00246c pcalau12i \$t0, 291 -+ 118: 1c00246c pcaddu12i \$t0, 291 -+ 11c: 1e00246c pcaddu18i \$t0, 291 -+ 120: 04048c0c csrrd \$t0, 0x123 -+ 124: 04048c2c csrwr \$t0, 0x123 -+ 128: 040009ac csrxchg \$t0, \$t1, 0x2 -+ 12c: 060009a2 cacop 0x2, \$t1, 2 -+ 130: 064009ac lddir \$t0, \$t1, 0x2 -+ 134: 06440980 ldpte \$t0, 0x2 -+ 138: 0649b9a2 invtlb 0x2, \$t1, \$t2 -+ 13c: 000010a4 clo.w \$a0, \$a1 -+ 140: 000014a4 clz.w \$a0, \$a1 -+ 144: 000018a4 cto.w \$a0, \$a1 -+ 148: 00001ca4 ctz.w \$a0, \$a1 -+ 14c: 000020a4 clo.d \$a0, \$a1 -+ 150: 000024a4 clz.d \$a0, \$a1 -+ 154: 000028a4 cto.d \$a0, \$a1 -+ 158: 00002ca4 ctz.d \$a0, \$a1 -+ 15c: 000030a4 revb.2h \$a0, \$a1 -+ 160: 000034a4 revb.4h \$a0, \$a1 -+ 164: 000038a4 revb.2w \$a0, \$a1 -+ 168: 00003ca4 revb.d \$a0, \$a1 -+ 16c: 000040a4 revh.2w \$a0, \$a1 -+ 170: 000044a4 revh.d \$a0, \$a1 -+ 174: 000048a4 bitrev.4b \$a0, \$a1 -+ 178: 00004ca4 bitrev.8b \$a0, \$a1 -+ 17c: 000050a4 bitrev.w \$a0, \$a1 -+ 180: 000054a4 bitrev.d \$a0, \$a1 -+ 184: 000058a4 ext.w.h \$a0, \$a1 -+ 188: 00005ca4 ext.w.b \$a0, \$a1 -+ 18c: 000060a4 rdtimel.w \$a0, \$a1 -+ 190: 000064a4 rdtimeh.w \$a0, \$a1 -+ 194: 000068a4 rdtime.d \$a0, \$a1 -+ 198: 00006ca4 cpucfg \$a0, \$a1 -+ 19c: 000118a0 asrtle.d \$a1, \$a2 -+ 1a0: 000198a0 asrtgt.d \$a1, \$a2 -+ 1a4: 000418a4 alsl.w \$a0, \$a1, \$a2, 0x1 -+ 1a8: 000598a4 alsl.w \$a0, \$a1, \$a2, 0x4 -+ 1ac: 000618a4 alsl.wu \$a0, \$a1, \$a2, 0x1 -+ 1b0: 000798a4 alsl.wu \$a0, \$a1, \$a2, 0x4 -+ 1b4: 000818a4 bytepick.w \$a0, \$a1, \$a2, 0x0 -+ 1b8: 000998a4 bytepick.w \$a0, \$a1, \$a2, 0x3 -+ 1bc: 000c18a4 bytepick.d \$a0, \$a1, \$a2, 0x0 -+ 1c0: 000f98a4 bytepick.d \$a0, \$a1, \$a2, 0x7 -+ 1c4: 001018a4 add.w \$a0, \$a1, \$a2 -+ 1c8: 001098a4 add.d \$a0, \$a1, \$a2 -+ 1cc: 001118a4 sub.w \$a0, \$a1, \$a2 -+ 1d0: 001198a4 sub.d \$a0, \$a1, \$a2 -+ 1d4: 001218a4 slt \$a0, \$a1, \$a2 -+ 1d8: 001298a4 sltu \$a0, \$a1, \$a2 -+ 1dc: 001318a4 maskeqz \$a0, \$a1, \$a2 -+ 1e0: 001398a4 masknez \$a0, \$a1, \$a2 -+ 1e4: 001418a4 nor \$a0, \$a1, \$a2 -+ 1e8: 001498a4 and \$a0, \$a1, \$a2 -+ 1ec: 001518a4 or \$a0, \$a1, \$a2 -+ 1f0: 001598a4 xor \$a0, \$a1, \$a2 -+ 1f4: 001618a4 orn \$a0, \$a1, \$a2 -+ 1f8: 001698a4 andn \$a0, \$a1, \$a2 -+ 1fc: 001718a4 sll.w \$a0, \$a1, \$a2 -+ 200: 001798a4 srl.w \$a0, \$a1, \$a2 -+ 204: 001818a4 sra.w \$a0, \$a1, \$a2 -+ 208: 001898a4 sll.d \$a0, \$a1, \$a2 -+ 20c: 001918a4 srl.d \$a0, \$a1, \$a2 -+ 210: 001998a4 sra.d \$a0, \$a1, \$a2 -+ 214: 001b18a4 rotr.w \$a0, \$a1, \$a2 -+ 218: 001b98a4 rotr.d \$a0, \$a1, \$a2 -+ 21c: 001c18a4 mul.w \$a0, \$a1, \$a2 -+ 220: 001c98a4 mulh.w \$a0, \$a1, \$a2 -+ 224: 001d18a4 mulh.wu \$a0, \$a1, \$a2 -+ 228: 001d98a4 mul.d \$a0, \$a1, \$a2 -+ 22c: 001e18a4 mulh.d \$a0, \$a1, \$a2 -+ 230: 001e98a4 mulh.du \$a0, \$a1, \$a2 -+ 234: 001f18a4 mulw.d.w \$a0, \$a1, \$a2 -+ 238: 001f98a4 mulw.d.wu \$a0, \$a1, \$a2 -+ 23c: 002018a4 div.w \$a0, \$a1, \$a2 -+ 240: 002098a4 mod.w \$a0, \$a1, \$a2 -+ 244: 002118a4 div.wu \$a0, \$a1, \$a2 -+ 248: 002198a4 mod.wu \$a0, \$a1, \$a2 -+ 24c: 002218a4 div.d \$a0, \$a1, \$a2 -+ 250: 002298a4 mod.d \$a0, \$a1, \$a2 -+ 254: 002318a4 div.du \$a0, \$a1, \$a2 -+ 258: 002398a4 mod.du \$a0, \$a1, \$a2 -+ 25c: 002418a4 crc.w.b.w \$a0, \$a1, \$a2 -+ 260: 002498a4 crc.w.h.w \$a0, \$a1, \$a2 -+ 264: 002518a4 crc.w.w.w \$a0, \$a1, \$a2 -+ 268: 002598a4 crc.w.d.w \$a0, \$a1, \$a2 -+ 26c: 002618a4 crcc.w.b.w \$a0, \$a1, \$a2 -+ 270: 002698a4 crcc.w.h.w \$a0, \$a1, \$a2 -+ 274: 002718a4 crcc.w.w.w \$a0, \$a1, \$a2 -+ 278: 002798a4 crcc.w.d.w \$a0, \$a1, \$a2 -+ 27c: 002a0000 break 0x0 -+ 280: 002a7fff break 0x7fff -+ 284: 002a8000 dbcl 0x0 -+ 288: 002affff dbcl 0x7fff -+ 28c: 002c18a4 alsl.d \$a0, \$a1, \$a2, 0x1 -+ 290: 002d98a4 alsl.d \$a0, \$a1, \$a2, 0x4 -+ 294: 004080a4 slli.w \$a0, \$a1, 0x0 -+ 298: 004084a4 slli.w \$a0, \$a1, 0x1 -+ 29c: 0040fca4 slli.w \$a0, \$a1, 0x1f -+ 2a0: 004100a4 slli.d \$a0, \$a1, 0x0 -+ 2a4: 004104a4 slli.d \$a0, \$a1, 0x1 -+ 2a8: 0041fca4 slli.d \$a0, \$a1, 0x3f -+ 2ac: 004480a4 srli.w \$a0, \$a1, 0x0 -+ 2b0: 004484a4 srli.w \$a0, \$a1, 0x1 -+ 2b4: 0044fca4 srli.w \$a0, \$a1, 0x1f -+ 2b8: 004500a4 srli.d \$a0, \$a1, 0x0 -+ 2bc: 004504a4 srli.d \$a0, \$a1, 0x1 -+ 2c0: 0045fca4 srli.d \$a0, \$a1, 0x3f -+ 2c4: 004880a4 srai.w \$a0, \$a1, 0x0 -+ 2c8: 004884a4 srai.w \$a0, \$a1, 0x1 -+ 2cc: 0048fca4 srai.w \$a0, \$a1, 0x1f -+ 2d0: 004900a4 srai.d \$a0, \$a1, 0x0 -+ 2d4: 004904a4 srai.d \$a0, \$a1, 0x1 -+ 2d8: 0049fca4 srai.d \$a0, \$a1, 0x3f -+ 2dc: 004c80a4 rotri.w \$a0, \$a1, 0x0 -+ 2e0: 004c84a4 rotri.w \$a0, \$a1, 0x1 -+ 2e4: 004cfca4 rotri.w \$a0, \$a1, 0x1f -+ 2e8: 004d00a4 rotri.d \$a0, \$a1, 0x0 -+ 2ec: 004d04a4 rotri.d \$a0, \$a1, 0x1 -+ 2f0: 004dfca4 rotri.d \$a0, \$a1, 0x3f -+ 2f4: 006000a4 bstrins.w \$a0, \$a1, 0x0, 0x0 -+ 2f8: 006204a4 bstrins.w \$a0, \$a1, 0x2, 0x1 -+ 2fc: 007f00a4 bstrins.w \$a0, \$a1, 0x1f, 0x0 -+ 300: 006080a4 bstrpick.w \$a0, \$a1, 0x0, 0x0 -+ 304: 006284a4 bstrpick.w \$a0, \$a1, 0x2, 0x1 -+ 308: 007f80a4 bstrpick.w \$a0, \$a1, 0x1f, 0x0 -+ 30c: 008000a4 bstrins.d \$a0, \$a1, 0x0, 0x0 -+ 310: 009f04a4 bstrins.d \$a0, \$a1, 0x1f, 0x1 -+ 314: 00a000a4 bstrins.d \$a0, \$a1, 0x20, 0x0 -+ 318: 00bf00a4 bstrins.d \$a0, \$a1, 0x3f, 0x0 -+ 31c: 00c000a4 bstrpick.d \$a0, \$a1, 0x0, 0x0 -+ 320: 00df04a4 bstrpick.d \$a0, \$a1, 0x1f, 0x1 -+ 324: 00e000a4 bstrpick.d \$a0, \$a1, 0x20, 0x0 -+ 328: 00ff00a4 bstrpick.d \$a0, \$a1, 0x3f, 0x0 -+ 32c: 200000a4 ll.w \$a0, \$a1, 0 -+ 330: 203ffca4 ll.w \$a0, \$a1, 16380 -+ 334: 210000a4 sc.w \$a0, \$a1, 0 -+ 338: 213ffca4 sc.w \$a0, \$a1, 16380 -+ 33c: 220000a4 ll.d \$a0, \$a1, 0 -+ 340: 223ffca4 ll.d \$a0, \$a1, 16380 -+ 344: 230000a4 sc.d \$a0, \$a1, 0 -+ 348: 233ffca4 sc.d \$a0, \$a1, 16380 -+ 34c: 240000a4 ldptr.w \$a0, \$a1, 0 -+ 350: 243ffca4 ldptr.w \$a0, \$a1, 16380 -+ 354: 250000a4 stptr.w \$a0, \$a1, 0 -+ 358: 253ffca4 stptr.w \$a0, \$a1, 16380 -+ 35c: 260000a4 ldptr.d \$a0, \$a1, 0 -+ 360: 263ffca4 ldptr.d \$a0, \$a1, 16380 -+ 364: 270000a4 stptr.d \$a0, \$a1, 0 -+ 368: 273ffca4 stptr.d \$a0, \$a1, 16380 -+ 36c: 280000a4 ld.b \$a0, \$a1, 0 -+ 370: 281ffca4 ld.b \$a0, \$a1, 2047 -+ 374: 282004a4 ld.b \$a0, \$a1, -2047 -+ 378: 284000a4 ld.h \$a0, \$a1, 0 -+ 37c: 285ffca4 ld.h \$a0, \$a1, 2047 -+ 380: 286004a4 ld.h \$a0, \$a1, -2047 -+ 384: 288000a4 ld.w \$a0, \$a1, 0 -+ 388: 289ffca4 ld.w \$a0, \$a1, 2047 -+ 38c: 28a004a4 ld.w \$a0, \$a1, -2047 -+ 390: 28c000a4 ld.d \$a0, \$a1, 0 -+ 394: 28dffca4 ld.d \$a0, \$a1, 2047 -+ 398: 28e004a4 ld.d \$a0, \$a1, -2047 -+ 39c: 290000a4 st.b \$a0, \$a1, 0 -+ 3a0: 291ffca4 st.b \$a0, \$a1, 2047 -+ 3a4: 292004a4 st.b \$a0, \$a1, -2047 -+ 3a8: 294000a4 st.h \$a0, \$a1, 0 -+ 3ac: 295ffca4 st.h \$a0, \$a1, 2047 -+ 3b0: 296004a4 st.h \$a0, \$a1, -2047 -+ 3b4: 298000a4 st.w \$a0, \$a1, 0 -+ 3b8: 299ffca4 st.w \$a0, \$a1, 2047 -+ 3bc: 29a004a4 st.w \$a0, \$a1, -2047 -+ 3c0: 29c000a4 st.d \$a0, \$a1, 0 -+ 3c4: 29dffca4 st.d \$a0, \$a1, 2047 -+ 3c8: 29e004a4 st.d \$a0, \$a1, -2047 -+ 3cc: 2a0000a4 ld.bu \$a0, \$a1, 0 -+ 3d0: 2a1ffca4 ld.bu \$a0, \$a1, 2047 -+ 3d4: 2a2004a4 ld.bu \$a0, \$a1, -2047 -+ 3d8: 2a4000a4 ld.hu \$a0, \$a1, 0 -+ 3dc: 2a5ffca4 ld.hu \$a0, \$a1, 2047 -+ 3e0: 2a6004a4 ld.hu \$a0, \$a1, -2047 -+ 3e4: 2a8000a4 ld.wu \$a0, \$a1, 0 -+ 3e8: 2a9ffca4 ld.wu \$a0, \$a1, 2047 -+ 3ec: 2aa004a4 ld.wu \$a0, \$a1, -2047 -+ 3f0: 2ac000a0 preld 0x0, \$a1, 0 -+ 3f4: 2adffcbf preld 0x1f, \$a1, 2047 -+ 3f8: 2ae004bf preld 0x1f, \$a1, -2047 -+ 3fc: 380018a4 ldx.b \$a0, \$a1, \$a2 -+ 400: 380418a4 ldx.h \$a0, \$a1, \$a2 -+ 404: 380818a4 ldx.w \$a0, \$a1, \$a2 -+ 408: 380c18a4 ldx.d \$a0, \$a1, \$a2 -+ 40c: 381018a4 stx.b \$a0, \$a1, \$a2 -+ 410: 381418a4 stx.h \$a0, \$a1, \$a2 -+ 414: 381818a4 stx.w \$a0, \$a1, \$a2 -+ 418: 381c18a4 stx.d \$a0, \$a1, \$a2 -+ 41c: 382018a4 ldx.bu \$a0, \$a1, \$a2 -+ 420: 382418a4 ldx.hu \$a0, \$a1, \$a2 -+ 424: 382818a4 ldx.wu \$a0, \$a1, \$a2 -+ 428: 382c18a0 preldx 0x0, \$a1, \$a2 -+ 42c: 382c18bf preldx 0x1f, \$a1, \$a2 -+ 430: 38720000 dbar 0x0 -+ 434: 38727fff dbar 0x7fff -+ 438: 38728000 ibar 0x0 -+ 43c: 3872ffff ibar 0x7fff -+ 440: 386014c4 amswap.w \$a0, \$a1, \$a2 -+ 444: 386018a4 amswap.w \$a0, \$a2, \$a1 -+ 448: 386094c4 amswap.d \$a0, \$a1, \$a2 -+ 44c: 386098a4 amswap.d \$a0, \$a2, \$a1 -+ 450: 386114c4 amadd.w \$a0, \$a1, \$a2 -+ 454: 386118a4 amadd.w \$a0, \$a2, \$a1 -+ 458: 386194c4 amadd.d \$a0, \$a1, \$a2 -+ 45c: 386198a4 amadd.d \$a0, \$a2, \$a1 -+ 460: 386214c4 amand.w \$a0, \$a1, \$a2 -+ 464: 386218a4 amand.w \$a0, \$a2, \$a1 -+ 468: 386294c4 amand.d \$a0, \$a1, \$a2 -+ 46c: 386298a4 amand.d \$a0, \$a2, \$a1 -+ 470: 386314c4 amor.w \$a0, \$a1, \$a2 -+ 474: 386318a4 amor.w \$a0, \$a2, \$a1 -+ 478: 386394c4 amor.d \$a0, \$a1, \$a2 -+ 47c: 386398a4 amor.d \$a0, \$a2, \$a1 -+ 480: 386414c4 amxor.w \$a0, \$a1, \$a2 -+ 484: 386418a4 amxor.w \$a0, \$a2, \$a1 -+ 488: 386494c4 amxor.d \$a0, \$a1, \$a2 -+ 48c: 386498a4 amxor.d \$a0, \$a2, \$a1 -+ 490: 386514c4 ammax.w \$a0, \$a1, \$a2 -+ 494: 386518a4 ammax.w \$a0, \$a2, \$a1 -+ 498: 386594c4 ammax.d \$a0, \$a1, \$a2 -+ 49c: 386598a4 ammax.d \$a0, \$a2, \$a1 -+ 4a0: 386614c4 ammin.w \$a0, \$a1, \$a2 -+ 4a4: 386618a4 ammin.w \$a0, \$a2, \$a1 -+ 4a8: 386694c4 ammin.d \$a0, \$a1, \$a2 -+ 4ac: 386698a4 ammin.d \$a0, \$a2, \$a1 -+ 4b0: 386714c4 ammax.wu \$a0, \$a1, \$a2 -+ 4b4: 386718a4 ammax.wu \$a0, \$a2, \$a1 -+ 4b8: 386794c4 ammax.du \$a0, \$a1, \$a2 -+ 4bc: 386798a4 ammax.du \$a0, \$a2, \$a1 -+ 4c0: 386814c4 ammin.wu \$a0, \$a1, \$a2 -+ 4c4: 386818a4 ammin.wu \$a0, \$a2, \$a1 -+ 4c8: 386894c4 ammin.du \$a0, \$a1, \$a2 -+ 4cc: 386898a4 ammin.du \$a0, \$a2, \$a1 -+ 4d0: 386914c4 amswap_db.w \$a0, \$a1, \$a2 -+ 4d4: 386918a4 amswap_db.w \$a0, \$a2, \$a1 -+ 4d8: 386994c4 amswap_db.d \$a0, \$a1, \$a2 -+ 4dc: 386998a4 amswap_db.d \$a0, \$a2, \$a1 -+ 4e0: 386a14c4 amadd_db.w \$a0, \$a1, \$a2 -+ 4e4: 386a18a4 amadd_db.w \$a0, \$a2, \$a1 -+ 4e8: 386a94c4 amadd_db.d \$a0, \$a1, \$a2 -+ 4ec: 386a98a4 amadd_db.d \$a0, \$a2, \$a1 -+ 4f0: 386b14c4 amand_db.w \$a0, \$a1, \$a2 -+ 4f4: 386b18a4 amand_db.w \$a0, \$a2, \$a1 -+ 4f8: 386b94c4 amand_db.d \$a0, \$a1, \$a2 -+ 4fc: 386b98a4 amand_db.d \$a0, \$a2, \$a1 -+ 500: 386c14c4 amor_db.w \$a0, \$a1, \$a2 -+ 504: 386c18a4 amor_db.w \$a0, \$a2, \$a1 -+ 508: 386c94c4 amor_db.d \$a0, \$a1, \$a2 -+ 50c: 386c98a4 amor_db.d \$a0, \$a2, \$a1 -+ 510: 386d14c4 amxor_db.w \$a0, \$a1, \$a2 -+ 514: 386d18a4 amxor_db.w \$a0, \$a2, \$a1 -+ 518: 386d94c4 amxor_db.d \$a0, \$a1, \$a2 -+ 51c: 386d98a4 amxor_db.d \$a0, \$a2, \$a1 -+ 520: 386e14c4 ammax_db.w \$a0, \$a1, \$a2 -+ 524: 386e18a4 ammax_db.w \$a0, \$a2, \$a1 -+ 528: 386e94c4 ammax_db.d \$a0, \$a1, \$a2 -+ 52c: 386e98a4 ammax_db.d \$a0, \$a2, \$a1 -+ 530: 386f14c4 ammin_db.w \$a0, \$a1, \$a2 -+ 534: 386f18a4 ammin_db.w \$a0, \$a2, \$a1 -+ 538: 386f94c4 ammin_db.d \$a0, \$a1, \$a2 -+ 53c: 386f98a4 ammin_db.d \$a0, \$a2, \$a1 -+ 540: 387014c4 ammax_db.wu \$a0, \$a1, \$a2 -+ 544: 387018a4 ammax_db.wu \$a0, \$a2, \$a1 -+ 548: 387094c4 ammax_db.du \$a0, \$a1, \$a2 -+ 54c: 387098a4 ammax_db.du \$a0, \$a2, \$a1 -+ 550: 387114c4 ammin_db.wu \$a0, \$a1, \$a2 -+ 554: 387118a4 ammin_db.wu \$a0, \$a2, \$a1 -+ 558: 387194c4 ammin_db.du \$a0, \$a1, \$a2 -+ 55c: 387198a4 ammin_db.du \$a0, \$a2, \$a1 -+ 560: 387818a4 ldgt.b \$a0, \$a1, \$a2 -+ 564: 387898a4 ldgt.h \$a0, \$a1, \$a2 -+ 568: 387918a4 ldgt.w \$a0, \$a1, \$a2 -+ 56c: 387998a4 ldgt.d \$a0, \$a1, \$a2 -+ 570: 387a18a4 ldle.b \$a0, \$a1, \$a2 -+ 574: 387a98a4 ldle.h \$a0, \$a1, \$a2 -+ 578: 387b18a4 ldle.w \$a0, \$a1, \$a2 -+ 57c: 387b98a4 ldle.d \$a0, \$a1, \$a2 -+ 580: 387c18a4 stgt.b \$a0, \$a1, \$a2 -+ 584: 387c98a4 stgt.h \$a0, \$a1, \$a2 -+ 588: 387d18a4 stgt.w \$a0, \$a1, \$a2 -+ 58c: 387d98a4 stgt.d \$a0, \$a1, \$a2 -+ 590: 387e18a4 stle.b \$a0, \$a1, \$a2 -+ 594: 387e98a4 stle.h \$a0, \$a1, \$a2 -+ 598: 387f18a4 stle.w \$a0, \$a1, \$a2 -+ 59c: 387f98a4 stle.d \$a0, \$a1, \$a2 -+ 5a0: 385714c4 sc.q \$a0, \$a1, \$a2 -+ 5a4: 385714c4 sc.q \$a0, \$a1, \$a2 -+ 5a8: 385780a4 llacq.w \$a0, \$a1 -+ 5ac: 385780a4 llacq.w \$a0, \$a1 -+ 5b0: 385784a4 screl.w \$a0, \$a1 -+ 5b4: 385784a4 screl.w \$a0, \$a1 -+ 5b8: 385788a4 llacq.d \$a0, \$a1 -+ 5bc: 385788a4 llacq.d \$a0, \$a1 -+ 5c0: 38578ca4 screl.d \$a0, \$a1 -+ 5c4: 38578ca4 screl.d \$a0, \$a1 -+ 5c8: 385814c4 amcas.b \$a0, \$a1, \$a2 -+ 5cc: 385818a4 amcas.b \$a0, \$a2, \$a1 -+ 5d0: 385894c4 amcas.h \$a0, \$a1, \$a2 -+ 5d4: 385898a4 amcas.h \$a0, \$a2, \$a1 -+ 5d8: 385914c4 amcas.w \$a0, \$a1, \$a2 -+ 5dc: 385918a4 amcas.w \$a0, \$a2, \$a1 -+ 5e0: 385994c4 amcas.d \$a0, \$a1, \$a2 -+ 5e4: 385998a4 amcas.d \$a0, \$a2, \$a1 -+ 5e8: 385a14c4 amcas_db.b \$a0, \$a1, \$a2 -+ 5ec: 385a18a4 amcas_db.b \$a0, \$a2, \$a1 -+ 5f0: 385a94c4 amcas_db.h \$a0, \$a1, \$a2 -+ 5f4: 385a98a4 amcas_db.h \$a0, \$a2, \$a1 -+ 5f8: 385b14c4 amcas_db.w \$a0, \$a1, \$a2 -+ 5fc: 385b18a4 amcas_db.w \$a0, \$a2, \$a1 -+ 600: 385b94c4 amcas_db.d \$a0, \$a1, \$a2 -+ 604: 385b98a4 amcas_db.d \$a0, \$a2, \$a1 -+ 608: 385c14c4 amswap.b \$a0, \$a1, \$a2 -+ 60c: 385c18a4 amswap.b \$a0, \$a2, \$a1 -+ 610: 385c94c4 amswap.h \$a0, \$a1, \$a2 -+ 614: 385c98a4 amswap.h \$a0, \$a2, \$a1 -+ 618: 385d14c4 amadd.b \$a0, \$a1, \$a2 -+ 61c: 385d18a4 amadd.b \$a0, \$a2, \$a1 -+ 620: 385d94c4 amadd.h \$a0, \$a1, \$a2 -+ 624: 385d98a4 amadd.h \$a0, \$a2, \$a1 -+ 628: 385e14c4 amswap_db.b \$a0, \$a1, \$a2 -+ 62c: 385e18a4 amswap_db.b \$a0, \$a2, \$a1 -+ 630: 385e94c4 amswap_db.h \$a0, \$a1, \$a2 -+ 634: 385e98a4 amswap_db.h \$a0, \$a2, \$a1 -+ 638: 385f14c4 amadd_db.b \$a0, \$a1, \$a2 -+ 63c: 385f18a4 amadd_db.b \$a0, \$a2, \$a1 -+ 640: 385f94c4 amadd_db.h \$a0, \$a1, \$a2 -+ 644: 385f98a4 amadd_db.h \$a0, \$a2, \$a1 -+ -+0+648 <.L1>: -+ 648: 03400000 andi \$zero, \$zero, 0x0 -+ 64c: 43fffc9f beqz \$a0, -4 # 648 <.L1> -+ 650: 47fff89f bnez \$a0, -8 # 648 <.L1> -+ 654: 53fff7ff b -12 # 648 <.L1> -+ 658: 57fff3ff bl -16 # 648 <.L1> -+ 65c: 5bffec85 beq \$a0, \$a1, -20 # 648 <.L1> -+ 660: 5fffe885 bne \$a0, \$a1, -24 # 648 <.L1> -+ 664: 63ffe485 blt \$a0, \$a1, -28 # 648 <.L1> -+ 668: 63ffe0a4 blt \$a1, \$a0, -32 # 648 <.L1> -+ 66c: 67ffdc85 bge \$a0, \$a1, -36 # 648 <.L1> -+ 670: 67ffd8a4 bge \$a1, \$a0, -40 # 648 <.L1> -+ 674: 6bffd485 bltu \$a0, \$a1, -44 # 648 <.L1> -+ 678: 6bffd0a4 bltu \$a1, \$a0, -48 # 648 <.L1> -+ 67c: 6fffcc85 bgeu \$a0, \$a1, -52 # 648 <.L1> -+ 680: 6fffc8a4 bgeu \$a1, \$a0, -56 # 648 <.L1> -+ 684: 4c000080 jirl \$zero, \$a0, 0 -diff --git a/gas/testsuite/gas/loongarch/insn_int64.s b/gas/testsuite/gas/loongarch/insn_int64.s -new file mode 100644 -index 00000000..f8089517 ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/insn_int64.s -@@ -0,0 +1,440 @@ -+# imm_op -+slti $r4,$r5,0 -+slti $r4,$r5,0x7ff -+slti $r4,$r5,-0x7ff -+sltui $r4,$r5,0 -+sltui $r4,$r5,0x7ff -+sltui $r4,$r5,-0x7ff -+addi.w $r4,$r5,0 -+addi.w $r4,$r5,0x7ff -+addi.w $r4,$r5,-0x7ff -+addi.d $r4,$r5,0 -+addi.d $r4,$r5,0x7ff -+addi.d $r4,$r5,-0x7ff -+lu52i.d $r4,$r5,0 -+lu52i.d $r4,$r5,0x7ff -+lu52i.d $r4,$r5,-0x7ff -+andi $r4,$r5,0 -+andi $r4,$r5,0x7ff -+ori $r4,$r5,0 -+ori $r4,$r5,0x7ff -+xori $r4,$r5,0 -+xori $r4,$r5,0x7ff -+addu16i.d $r4,$r5,0 -+addu16i.d $r4,$r5,0x7fff -+addu16i.d $r4,$r5,-0x7fff -+lu12i.w $r4,0 -+lu12i.w $r4,0x7ffff -+lu32i.d $r4,-0x7ffff -+pcaddi $r4,0 -+pcaddi $r4,0x7ffff -+pcaddi $r4,-0x80000 -+pcalau12i $r4,0 -+pcalau12i $r4,0x7ffff -+pcalau12i $r4,-0x7ffff -+pcaddu12i $r4,0 -+pcaddu12i $r4,0x7ffff -+pcaddu12i $r4,-0x7ffff -+pcaddu18i $r4,0 -+pcaddu18i $r4,0x7ffff -+pcaddu18i $r4,-0x7ffff -+ -+# imm_ins -+.equ a, 0x123 -+.equ b, 0xfffff00000 -+.equ c, 0xfffffffffff -+.equ d, 2 -+.equ e,0x100 -+ -+alsl.w $r11,$r12,$r13,d -+alsl.wu $r11,$r12,$r13,d -+bytepick.w $r11,$r12,$r13,d -+bytepick.d $r11,$r12,$r13,d -+ -+break d -+dbcl d -+syscall d -+ -+alsl.d $r11,$r12, $r13,d -+slli.w $r11,$r12,d -+slli.d $r11,$r12,d -+srli.w $r11,$r12,d -+srli.d $r12,$r13,d -+srai.w $r12,$r13,d -+srai.d $r12,$r13,d -+ -+bstrins.w $r12,$r13,d,d -+bstrins.d $r12,$r13,d,d -+bstrpick.d $r12,$r13,d,d -+bstrpick.d $r12,$r13,d,d -+ -+slti $r12,$r13,a -+sltui $r12,$r13,a -+addi.w $r12,$r13,a -+addi.d $r12,$r13,a -+lu52i.d $r12,$r13,a -+andi $r12,$r13,d -+ori $r12,$r13,d -+xori $r12,$r13,d -+addu16i.d $r12,$r13,d -+lu12i.w $r12,a -+lu32i.d $r12,a -+pcaddi $r12,a -+pcalau12i $r12,a -+pcaddu12i $r12,a -+pcaddu18i $r12,a -+ -+csrrd $r12,a -+csrwr $r12,a -+csrxchg $r12,$r13,d -+cacop d,$r13,d -+lddir $r12,$r13,d -+ldpte $r12,d -+ -+invtlb d,$r13,$r14 -+ -+# fix_op -+clo.w $r4,$r5 -+clz.w $r4,$r5 -+cto.w $r4,$r5 -+ctz.w $r4,$r5 -+clo.d $r4,$r5 -+clz.d $r4,$r5 -+cto.d $r4,$r5 -+ctz.d $r4,$r5 -+revb.2h $r4,$r5 -+revb.4h $r4,$r5 -+revb.2w $r4,$r5 -+revb.d $r4,$r5 -+revh.2w $r4,$r5 -+revh.d $r4,$r5 -+bitrev.4b $r4,$r5 -+bitrev.8b $r4,$r5 -+bitrev.w $r4,$r5 -+bitrev.d $r4,$r5 -+ext.w.h $r4,$r5 -+ext.w.b $r4,$r5 -+rdtimel.w $r4,$r5 -+rdtimeh.w $r4,$r5 -+rdtime.d $r4,$r5 -+cpucfg $r4,$r5 -+asrtle.d $r5,$r6 -+asrtgt.d $r5,$r6 -+alsl.w $r4,$r5,$r6,1 -+alsl.w $r4,$r5,$r6,4 -+alsl.wu $r4,$r5,$r6,1 -+alsl.wu $r4,$r5,$r6,4 -+bytepick.w $r4,$r5,$r6,0 -+bytepick.w $r4,$r5,$r6,3 -+bytepick.d $r4,$r5,$r6,0 -+bytepick.d $r4,$r5,$r6,7 -+add.w $r4,$r5,$r6 -+add.d $r4,$r5,$r6 -+sub.w $r4,$r5,$r6 -+sub.d $r4,$r5,$r6 -+slt $r4,$r5,$r6 -+sltu $r4,$r5,$r6 -+maskeqz $r4,$r5,$r6 -+masknez $r4,$r5,$r6 -+nor $r4,$r5,$r6 -+and $r4,$r5,$r6 -+or $r4,$r5,$r6 -+xor $r4,$r5,$r6 -+orn $r4,$r5,$r6 -+andn $r4,$r5,$r6 -+ -+# load_store -+sll.w $r4,$r5,$r6 -+srl.w $r4,$r5,$r6 -+sra.w $r4,$r5,$r6 -+sll.d $r4,$r5,$r6 -+srl.d $r4,$r5,$r6 -+sra.d $r4,$r5,$r6 -+rotr.w $r4,$r5,$r6 -+rotr.d $r4,$r5,$r6 -+mul.w $r4,$r5,$r6 -+mulh.w $r4,$r5,$r6 -+mulh.wu $r4,$r5,$r6 -+mul.d $r4,$r5,$r6 -+mulh.d $r4,$r5,$r6 -+mulh.du $r4,$r5,$r6 -+mulw.d.w $r4,$r5,$r6 -+mulw.d.wu $r4,$r5,$r6 -+div.w $r4,$r5,$r6 -+mod.w $r4,$r5,$r6 -+div.wu $r4,$r5,$r6 -+mod.wu $r4,$r5,$r6 -+div.d $r4,$r5,$r6 -+mod.d $r4,$r5,$r6 -+div.du $r4,$r5,$r6 -+mod.du $r4,$r5,$r6 -+crc.w.b.w $r4,$r5,$r6 -+crc.w.h.w $r4,$r5,$r6 -+crc.w.w.w $r4,$r5,$r6 -+crc.w.d.w $r4,$r5,$r6 -+crcc.w.b.w $r4,$r5,$r6 -+crcc.w.h.w $r4,$r5,$r6 -+crcc.w.w.w $r4,$r5,$r6 -+crcc.w.d.w $r4,$r5,$r6 -+break 0 -+break 0x7fff -+dbcl 0 -+dbcl 0x7fff -+alsl.d $r4,$r5,$r6,1 -+alsl.d $r4,$r5,$r6,4 -+slli.w $r4,$r5,0 -+slli.w $r4,$r5,1 -+slli.w $r4,$r5,0x1f -+slli.d $r4,$r5,0 -+slli.d $r4,$r5,1 -+slli.d $r4,$r5,0x3f -+srli.w $r4,$r5,0 -+srli.w $r4,$r5,1 -+srli.w $r4,$r5,0x1f -+srli.d $r4,$r5,0 -+srli.d $r4,$r5,1 -+srli.d $r4,$r5,0x3f -+srai.w $r4,$r5,0 -+srai.w $r4,$r5,1 -+srai.w $r4,$r5,0x1f -+srai.d $r4,$r5,0 -+srai.d $r4,$r5,1 -+srai.d $r4,$r5,0x3f -+rotri.w $r4,$r5,0 -+rotri.w $r4,$r5,1 -+rotri.w $r4,$r5,0x1f -+rotri.d $r4,$r5,0 -+rotri.d $r4,$r5,1 -+rotri.d $r4,$r5,0x3f -+bstrins.w $r4,$r5,0,0 -+bstrins.w $r4,$r5,2,1 -+bstrins.w $r4,$r5,31,0 -+bstrpick.w $r4,$r5,0,0 -+bstrpick.w $r4,$r5,2,1 -+bstrpick.w $r4,$r5,31,0 -+bstrins.d $r4,$r5,0,0 -+bstrins.d $r4,$r5,31,1 -+bstrins.d $r4,$r5,32,0 -+bstrins.d $r4,$r5,63,0 -+bstrpick.d $r4,$r5,0,0 -+bstrpick.d $r4,$r5,31,1 -+bstrpick.d $r4,$r5,32,0 -+bstrpick.d $r4,$r5,63,0 -+ll.w $r4,$r5,0 -+ll.w $r4,$r5,0x3ffc -+sc.w $r4,$r5,0 -+sc.w $r4,$r5,0x3ffc -+ll.d $r4,$r5,0 -+ll.d $r4,$r5,0x3ffc -+sc.d $r4,$r5,0 -+sc.d $r4,$r5,0x3ffc -+ldptr.w $r4,$r5,0 -+ldptr.w $r4,$r5,0x3ffc -+stptr.w $r4,$r5,0 -+stptr.w $r4,$r5,0x3ffc -+ldptr.d $r4,$r5,0 -+ldptr.d $r4,$r5,0x3ffc -+stptr.d $r4,$r5,0 -+stptr.d $r4,$r5,0x3ffc -+ld.b $r4,$r5,0 -+ld.b $r4,$r5,0x7ff -+ld.b $r4,$r5,-0x7ff -+ld.h $r4,$r5,0 -+ld.h $r4,$r5,0x7ff -+ld.h $r4,$r5,-0x7ff -+ld.w $r4,$r5,0 -+ld.w $r4,$r5,0x7ff -+ld.w $r4,$r5,-0x7ff -+ld.d $r4,$r5,0 -+ld.d $r4,$r5,0x7ff -+ld.d $r4,$r5,-0x7ff -+st.b $r4,$r5,0 -+st.b $r4,$r5,0x7ff -+st.b $r4,$r5,-0x7ff -+st.h $r4,$r5,0 -+st.h $r4,$r5,0x7ff -+st.h $r4,$r5,-0x7ff -+st.w $r4,$r5,0 -+st.w $r4,$r5,0x7ff -+st.w $r4,$r5,-0x7ff -+st.d $r4,$r5,0 -+st.d $r4,$r5,0x7ff -+st.d $r4,$r5,-0x7ff -+ld.bu $r4,$r5,0 -+ld.bu $r4,$r5,0x7ff -+ld.bu $r4,$r5,-0x7ff -+ld.hu $r4,$r5,0 -+ld.hu $r4,$r5,0x7ff -+ld.hu $r4,$r5,-0x7ff -+ld.wu $r4,$r5,0 -+ld.wu $r4,$r5,0x7ff -+ld.wu $r4,$r5,-0x7ff -+preld 0,$r5,0 -+preld 31,$r5,0x7ff -+preld 31,$r5,-0x7ff -+ldx.b $r4,$r5,$r6 -+ldx.h $r4,$r5,$r6 -+ldx.w $r4,$r5,$r6 -+ldx.d $r4,$r5,$r6 -+stx.b $r4,$r5,$r6 -+stx.h $r4,$r5,$r6 -+stx.w $r4,$r5,$r6 -+stx.d $r4,$r5,$r6 -+ldx.bu $r4,$r5,$r6 -+ldx.hu $r4,$r5,$r6 -+ldx.wu $r4,$r5,$r6 -+preldx 0,$r5,$r6 -+preldx 31,$r5,$r6 -+dbar 0 -+dbar 0x7fff -+ibar 0 -+ibar 0x7fff -+amswap.w $r4,$r5,$r6,0 -+amswap.w $r4,$r6,$r5 -+amswap.d $r4,$r5,$r6,0 -+amswap.d $r4,$r6,$r5 -+amadd.w $r4,$r5,$r6,0 -+amadd.w $r4,$r6,$r5 -+amadd.d $r4,$r5,$r6,0 -+amadd.d $r4,$r6,$r5 -+amand.w $r4,$r5,$r6,0 -+amand.w $r4,$r6,$r5 -+amand.d $r4,$r5,$r6,0 -+amand.d $r4,$r6,$r5 -+amor.w $r4,$r5,$r6,0 -+amor.w $r4,$r6,$r5 -+amor.d $r4,$r5,$r6,0 -+amor.d $r4,$r6,$r5 -+amxor.w $r4,$r5,$r6,0 -+amxor.w $r4,$r6,$r5 -+amxor.d $r4,$r5,$r6,0 -+amxor.d $r4,$r6,$r5 -+ammax.w $r4,$r5,$r6,0 -+ammax.w $r4,$r6,$r5 -+ammax.d $r4,$r5,$r6,0 -+ammax.d $r4,$r6,$r5 -+ammin.w $r4,$r5,$r6,0 -+ammin.w $r4,$r6,$r5 -+ammin.d $r4,$r5,$r6,0 -+ammin.d $r4,$r6,$r5 -+ammax.wu $r4,$r5,$r6,0 -+ammax.wu $r4,$r6,$r5 -+ammax.du $r4,$r5,$r6,0 -+ammax.du $r4,$r6,$r5 -+ammin.wu $r4,$r5,$r6,0 -+ammin.wu $r4,$r6,$r5 -+ammin.du $r4,$r5,$r6,0 -+ammin.du $r4,$r6,$r5 -+amswap_db.w $r4,$r5,$r6,0 -+amswap_db.w $r4,$r6,$r5 -+amswap_db.d $r4,$r5,$r6,0 -+amswap_db.d $r4,$r6,$r5 -+amadd_db.w $r4,$r5,$r6,0 -+amadd_db.w $r4,$r6,$r5 -+amadd_db.d $r4,$r5,$r6,0 -+amadd_db.d $r4,$r6,$r5 -+amand_db.w $r4,$r5,$r6,0 -+amand_db.w $r4,$r6,$r5 -+amand_db.d $r4,$r5,$r6,0 -+amand_db.d $r4,$r6,$r5 -+amor_db.w $r4,$r5,$r6,0 -+amor_db.w $r4,$r6,$r5 -+amor_db.d $r4,$r5,$r6,0 -+amor_db.d $r4,$r6,$r5 -+amxor_db.w $r4,$r5,$r6,0 -+amxor_db.w $r4,$r6,$r5 -+amxor_db.d $r4,$r5,$r6,0 -+amxor_db.d $r4,$r6,$r5 -+ammax_db.w $r4,$r5,$r6,0 -+ammax_db.w $r4,$r6,$r5 -+ammax_db.d $r4,$r5,$r6,0 -+ammax_db.d $r4,$r6,$r5 -+ammin_db.w $r4,$r5,$r6,0 -+ammin_db.w $r4,$r6,$r5 -+ammin_db.d $r4,$r5,$r6,0 -+ammin_db.d $r4,$r6,$r5 -+ammax_db.wu $r4,$r5,$r6,0 -+ammax_db.wu $r4,$r6,$r5 -+ammax_db.du $r4,$r5,$r6,0 -+ammax_db.du $r4,$r6,$r5 -+ammin_db.wu $r4,$r5,$r6,0 -+ammin_db.wu $r4,$r6,$r5 -+ammin_db.du $r4,$r5,$r6,0 -+ammin_db.du $r4,$r6,$r5 -+ldgt.b $r4,$r5,$r6 -+ldgt.h $r4,$r5,$r6 -+ldgt.w $r4,$r5,$r6 -+ldgt.d $r4,$r5,$r6 -+ldle.b $r4,$r5,$r6 -+ldle.h $r4,$r5,$r6 -+ldle.w $r4,$r5,$r6 -+ldle.d $r4,$r5,$r6 -+stgt.b $r4,$r5,$r6 -+stgt.h $r4,$r5,$r6 -+stgt.w $r4,$r5,$r6 -+stgt.d $r4,$r5,$r6 -+stle.b $r4,$r5,$r6 -+stle.h $r4,$r5,$r6 -+stle.w $r4,$r5,$r6 -+stle.d $r4,$r5,$r6 -+sc.q $r4,$r5,$r6,0 -+sc.q $r4,$r5,$r6 -+llacq.w $r4,$r5,0 -+llacq.w $r4,$r5 -+screl.w $r4,$r5,0 -+screl.w $r4,$r5 -+llacq.d $r4,$r5,0 -+llacq.d $r4,$r5 -+screl.d $r4,$r5,0 -+screl.d $r4,$r5 -+amcas.b $r4,$r5,$r6,0 -+amcas.b $r4,$r6,$r5 -+amcas.h $r4,$r5,$r6,0 -+amcas.h $r4,$r6,$r5 -+amcas.w $r4,$r5,$r6,0 -+amcas.w $r4,$r6,$r5 -+amcas.d $r4,$r5,$r6,0 -+amcas.d $r4,$r6,$r5 -+amcas_db.b $r4,$r5,$r6,0 -+amcas_db.b $r4,$r6,$r5 -+amcas_db.h $r4,$r5,$r6,0 -+amcas_db.h $r4,$r6,$r5 -+amcas_db.w $r4,$r5,$r6,0 -+amcas_db.w $r4,$r6,$r5 -+amcas_db.d $r4,$r5,$r6,0 -+amcas_db.d $r4,$r6,$r5 -+amswap.b $r4,$r5,$r6,0 -+amswap.b $r4,$r6,$r5 -+amswap.h $r4,$r5,$r6,0 -+amswap.h $r4,$r6,$r5 -+amadd.b $r4,$r5,$r6,0 -+amadd.b $r4,$r6,$r5 -+amadd.h $r4,$r5,$r6,0 -+amadd.h $r4,$r6,$r5 -+amswap_db.b $r4,$r5,$r6,0 -+amswap_db.b $r4,$r6,$r5 -+amswap_db.h $r4,$r5,$r6,0 -+amswap_db.h $r4,$r6,$r5 -+amadd_db.b $r4,$r5,$r6,0 -+amadd_db.b $r4,$r6,$r5 -+amadd_db.h $r4,$r5,$r6,0 -+amadd_db.h $r4,$r6,$r5 -+ -+# jmp_op -+.L1: -+nop -+beqz $r4,.L1 -+bnez $r4,.L1 -+b .L1 -+bl .L1 -+beq $r4,$r5,.L1 -+bne $r4,$r5,.L1 -+blt $r4,$r5,.L1 -+bgt $r4,$r5,.L1 -+bge $r4,$r5,.L1 -+ble $r4,$r5,.L1 -+bltu $r4,$r5,.L1 -+bgtu $r4,$r5,.L1 -+bgeu $r4,$r5,.L1 -+bleu $r4,$r5,.L1 -+jirl $zero,$r4,0 --- -2.33.0 - diff --git a/LoongArch-Add-gas-testsuit-for-LA64-relocations.patch b/LoongArch-Add-gas-testsuit-for-LA64-relocations.patch deleted file mode 100644 index 724786a..0000000 --- a/LoongArch-Add-gas-testsuit-for-LA64-relocations.patch +++ /dev/null @@ -1,281 +0,0 @@ -From 6dbcb5e8afae6d282e0955fdbbc7732b10338902 Mon Sep 17 00:00:00 2001 -From: Lulu Cai -Date: Thu, 11 Jan 2024 09:45:57 +0800 -Subject: [PATCH 067/123] LoongArch: Add gas testsuit for LA64 relocations - -Test the relocation of the LA64 instruction set. ---- - gas/testsuite/gas/loongarch/relocs_64.d | 144 ++++++++++++++++++++++++ - gas/testsuite/gas/loongarch/relocs_64.s | 109 ++++++++++++++++++ - 2 files changed, 253 insertions(+) - create mode 100644 gas/testsuite/gas/loongarch/relocs_64.d - create mode 100644 gas/testsuite/gas/loongarch/relocs_64.s - -diff --git a/gas/testsuite/gas/loongarch/relocs_64.d b/gas/testsuite/gas/loongarch/relocs_64.d -new file mode 100644 -index 00000000..631137eb ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/relocs_64.d -@@ -0,0 +1,144 @@ -+#as: -mthin-add-sub -+#objdump: -dr -+#skip: loongarch32-*-* -+ -+.*: file format .* -+ -+ -+Disassembly of section .text: -+ -+0+ <.*>: -+ 0: 4c008ca4 jirl \$a0, \$a1, 140 -+ 0: R_LARCH_B16 .L1 -+ 4: 40008880 beqz \$a0, 136 # 8c <.L1> -+ 4: R_LARCH_B21 .L1 -+ 8: 50008400 b 132 # 8c <.L1> -+ 8: R_LARCH_B26 .L1 -+ c: 14000004 lu12i.w \$a0, 0 -+ c: R_LARCH_ABS_HI20 .L1 -+ 10: 038000a4 ori \$a0, \$a1, 0x0 -+ 10: R_LARCH_ABS_LO12 .L1 -+ 14: 16000004 lu32i.d \$a0, 0 -+ 14: R_LARCH_ABS64_LO20 .L1 -+ 18: 03000085 lu52i.d \$a1, \$a0, 0 -+ 18: R_LARCH_ABS64_HI12 .L1 -+ 1c: 1a000004 pcalau12i \$a0, 0 -+ 1c: R_LARCH_PCALA_HI20 .L1 -+ 20: 02c00085 addi.d \$a1, \$a0, 0 -+ 20: R_LARCH_PCALA_LO12 .L1 -+ 24: 16000004 lu32i.d \$a0, 0 -+ 24: R_LARCH_PCALA64_LO20 .L1 -+ 28: 03000085 lu52i.d \$a1, \$a0, 0 -+ 28: R_LARCH_PCALA64_HI12 .L1 -+ 2c: 1a000004 pcalau12i \$a0, 0 -+ 2c: R_LARCH_GOT_PC_HI20 .L1 -+ 30: 28c00085 ld.d \$a1, \$a0, 0 -+ 30: R_LARCH_GOT_PC_LO12 .L1 -+ 34: 16000004 lu32i.d \$a0, 0 -+ 34: R_LARCH_GOT64_PC_LO20 .L1 -+ 38: 03000085 lu52i.d \$a1, \$a0, 0 -+ 38: R_LARCH_GOT64_PC_HI12 .L1 -+ 3c: 14000004 lu12i.w \$a0, 0 -+ 3c: R_LARCH_GOT_HI20 .L1 -+ 40: 03800084 ori \$a0, \$a0, 0x0 -+ 40: R_LARCH_GOT_LO12 .L1 -+ 44: 16000004 lu32i.d \$a0, 0 -+ 44: R_LARCH_GOT64_LO20 .L1 -+ 48: 03000085 lu52i.d \$a1, \$a0, 0 -+ 48: R_LARCH_GOT64_HI12 .L1 -+ 4c: 14000004 lu12i.w \$a0, 0 -+ 4c: R_LARCH_TLS_LE_HI20 TLSL1 -+ 50: 03800085 ori \$a1, \$a0, 0x0 -+ 50: R_LARCH_TLS_LE_LO12 TLSL1 -+ 54: 16000004 lu32i.d \$a0, 0 -+ 54: R_LARCH_TLS_LE64_LO20 TLSL1 -+ 58: 03000085 lu52i.d \$a1, \$a0, 0 -+ 58: R_LARCH_TLS_LE64_HI12 TLSL1 -+ 5c: 1a000004 pcalau12i \$a0, 0 -+ 5c: R_LARCH_TLS_IE_PC_HI20 TLSL1 -+ 60: 02c00005 li.d \$a1, 0 -+ 60: R_LARCH_TLS_IE_PC_LO12 TLSL1 -+ 64: 16000005 lu32i.d \$a1, 0 -+ 64: R_LARCH_TLS_IE64_PC_LO20 TLSL1 -+ 68: 030000a5 lu52i.d \$a1, \$a1, 0 -+ 68: R_LARCH_TLS_IE64_PC_HI12 TLSL1 -+ 6c: 14000004 lu12i.w \$a0, 0 -+ 6c: R_LARCH_TLS_IE_HI20 TLSL1 -+ 70: 03800084 ori \$a0, \$a0, 0x0 -+ 70: R_LARCH_TLS_IE_LO12 TLSL1 -+ 74: 16000004 lu32i.d \$a0, 0 -+ 74: R_LARCH_TLS_IE64_LO20 TLSL1 -+ 78: 03000084 lu52i.d \$a0, \$a0, 0 -+ 78: R_LARCH_TLS_IE64_HI12 TLSL1 -+ 7c: 1a000004 pcalau12i \$a0, 0 -+ 7c: R_LARCH_TLS_LD_PC_HI20 TLSL1 -+ 80: 14000004 lu12i.w \$a0, 0 -+ 80: R_LARCH_TLS_LD_HI20 TLSL1 -+ 84: 1a000004 pcalau12i \$a0, 0 -+ 84: R_LARCH_TLS_GD_PC_HI20 TLSL1 -+ 88: 14000004 lu12i.w \$a0, 0 -+ 88: R_LARCH_TLS_GD_HI20 TLSL1 -+ -+0+8c <.L1>: -+ 8c: 00000000 .word 0x00000000 -+ 8c: R_LARCH_32_PCREL .L2 -+ -+0+90 <.L2>: -+ ... -+ 90: R_LARCH_64_PCREL .L3 -+ -+0+98 <.L3>: -+ 98: 03400000 nop -+ 9c: 03400000 nop -+ 9c: R_LARCH_ALIGN .* -+ a0: 03400000 nop -+ a4: 03400000 nop -+ a8: 1800000c pcaddi \$t0, 0 -+ a8: R_LARCH_PCREL20_S2 .L1 -+ ac: 1e000001 pcaddu18i \$ra, 0 -+ ac: R_LARCH_CALL36 a -+ b0: 4c000021 jirl \$ra, \$ra, 0 -+ b4: 1a000004 pcalau12i \$a0, 0 -+ b4: R_LARCH_TLS_DESC_PC_HI20 TLSL1 -+ b8: 02c000a5 addi.d \$a1, \$a1, 0 -+ b8: R_LARCH_TLS_DESC_PC_LO12 TLSL1 -+ bc: 16000005 lu32i.d \$a1, 0 -+ bc: R_LARCH_TLS_DESC64_PC_LO20 TLSL1 -+ c0: 030000a5 lu52i.d \$a1, \$a1, 0 -+ c0: R_LARCH_TLS_DESC64_PC_HI12 TLSL1 -+ c4: 14000004 lu12i.w \$a0, 0 -+ c4: R_LARCH_TLS_DESC_HI20 TLSL1 -+ c8: 03800084 ori \$a0, \$a0, 0x0 -+ c8: R_LARCH_TLS_DESC_LO12 TLSL1 -+ cc: 16000004 lu32i.d \$a0, 0 -+ cc: R_LARCH_TLS_DESC64_LO20 TLSL1 -+ d0: 03000084 lu52i.d \$a0, \$a0, 0 -+ d0: R_LARCH_TLS_DESC64_HI12 TLSL1 -+ d4: 28c00081 ld.d \$ra, \$a0, 0 -+ d4: R_LARCH_TLS_DESC_LD TLSL1 -+ d8: 4c000021 jirl \$ra, \$ra, 0 -+ d8: R_LARCH_TLS_DESC_CALL TLSL1 -+ dc: 14000004 lu12i.w \$a0, 0 -+ dc: R_LARCH_TLS_LE_HI20_R TLSL1 -+ dc: R_LARCH_RELAX \*ABS\* -+ e0: 001090a5 add.d \$a1, \$a1, \$a0 -+ e0: R_LARCH_TLS_LE_ADD_R TLSL1 -+ e0: R_LARCH_RELAX \*ABS\* -+ e4: 29800085 st.w \$a1, \$a0, 0 -+ e4: R_LARCH_TLS_LE_LO12_R TLSL1 -+ e4: R_LARCH_RELAX \*ABS\* -+ e8: 14000004 lu12i.w \$a0, 0 -+ e8: R_LARCH_TLS_LE_HI20_R TLSL1 -+ e8: R_LARCH_RELAX \*ABS\* -+ ec: 001090a5 add.d \$a1, \$a1, \$a0 -+ ec: R_LARCH_TLS_LE_ADD_R TLSL1 -+ ec: R_LARCH_RELAX \*ABS\* -+ f0: 29800085 st.w \$a1, \$a0, 0 -+ f0: R_LARCH_TLS_LE_LO12_R TLSL1 -+ f0: R_LARCH_RELAX \*ABS\* -+ f4: 18000004 pcaddi \$a0, 0 -+ f4: R_LARCH_TLS_LD_PCREL20_S2 TLSL1 -+ f8: 18000004 pcaddi \$a0, 0 -+ f8: R_LARCH_TLS_GD_PCREL20_S2 TLSL1 -+ fc: 18000004 pcaddi \$a0, 0 -+ fc: R_LARCH_TLS_DESC_PCREL20_S2 TLSL1 -diff --git a/gas/testsuite/gas/loongarch/relocs_64.s b/gas/testsuite/gas/loongarch/relocs_64.s -new file mode 100644 -index 00000000..1d1548f5 ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/relocs_64.s -@@ -0,0 +1,109 @@ -+/* b16. */ -+jirl $r4,$r5,%b16(.L1) -+ -+/* b21. */ -+beqz $r4,%b21(.L1) -+ -+/* b26. */ -+b %b26(.L1) -+ -+/* lu12i.w. */ -+lu12i.w $r4,%abs_hi20(.L1) -+ -+/* ori */ -+ori $r4,$r5,%abs_lo12(.L1) -+ -+/* lu32i.d. */ -+lu32i.d $r4,%abs64_lo20(.L1) -+ -+/* lu52i.d. */ -+lu52i.d $r5,$r4,%abs64_hi12(.L1) -+ -+pcalau12i $r4,%pc_hi20(.L1) -+addi.d $r5,$r4,%pc_lo12(.L1) -+lu32i.d $r4,%pc64_lo20(.L1) -+lu52i.d $r5,$r4,%pc64_hi12(.L1) -+ -+pcalau12i $r4,%got_pc_hi20(.L1) -+ld.d $r5,$r4,%got_pc_lo12(.L1) -+lu32i.d $r4,%got64_pc_lo20(.L1) -+lu52i.d $r5,$r4,%got64_pc_hi12(.L1) -+ -+lu12i.w $r4,%got_hi20(.L1) -+ori $r4,$r4,%got_lo12(.L1) -+lu32i.d $r4,%got64_lo20(.L1) -+lu52i.d $r5,$r4,%got64_hi12(.L1) -+ -+/* TLS LE. */ -+lu12i.w $r4,%le_hi20(TLSL1) -+ori $r5,$r4,%le_lo12(TLSL1) -+lu32i.d $r4,%le64_lo20(TLSL1) -+lu52i.d $r5,$r4,%le64_hi12(TLSL1) -+ -+/* Part of IE relocs. */ -+pcalau12i $r4,%ie_pc_hi20(TLSL1) -+addi.d $r5,$r0,%ie_pc_lo12(TLSL1) -+lu32i.d $r5,%ie64_pc_lo20(TLSL1) -+lu52i.d $r5,$r5,%ie64_pc_hi12(TLSL1) -+ -+lu12i.w $r4,%ie_hi20(TLSL1) -+ori $r4,$r4,%ie_lo12(TLSL1) -+lu32i.d $r4,%ie64_lo20(TLSL1) -+lu52i.d $r4,$r4,%ie64_hi12(TLSL1) -+ -+/* Part of LD relocs. */ -+pcalau12i $r4,%ld_pc_hi20(TLSL1) -+lu12i.w $r4,%ld_hi20(TLSL1) -+ -+/* Part of GD relocs. */ -+pcalau12i $r4,%gd_pc_hi20(TLSL1) -+lu12i.w $r4,%gd_hi20(TLSL1) -+ -+/* Test insn relocs. */ -+.L1: -+/* 32-bit PC relative. */ -+.4byte .L2-.L1 -+.L2: -+/* 64-bit PC relative. */ -+.8byte .L3-.L2 -+ -+.L3: -+nop -+ -+/* R_LARCH_ALIGN. */ -+.align 4 -+ -+/* R_LARCH_PCREL20_S2. */ -+pcaddi $r12,.L1 -+ -+/* R_LARCH_ADD_CALL36 */ -+pcaddu18i $r1, %call36(a) -+jirl $r1, $r1, 0 -+ -+/* Part of DESC relocs. */ -+pcalau12i $r4,%desc_pc_hi20(TLSL1) -+addi.d $r5,$r5,%desc_pc_lo12(TLSL1) -+lu32i.d $r5,%desc64_pc_lo20(TLSL1) -+lu52i.d $r5,$r5,%desc64_pc_hi12(TLSL1) -+ -+lu12i.w $r4,%desc_hi20(TLSL1) -+ori $r4,$r4,%desc_lo12(TLSL1) -+lu32i.d $r4,%desc64_lo20(TLSL1) -+lu52i.d $r4,$r4,%desc64_hi12(TLSL1) -+ld.d $r1,$r4,%desc_ld(TLSL1) -+jirl $r1,$r1,%desc_call(TLSL1) -+ -+/* New TLS Insn. */ -+lu12i.w $r4,%le_hi20_r(TLSL1) -+add.d $r5,$r5,$r4,%le_add_r(TLSL1) -+st.w $r5,$r4,%le_lo12_r(TLSL1) -+ -+/* New TLS Insn with addend. */ -+lu12i.w $r4,%le_hi20_r(TLSL1) -+add.d $r5,$r5,$r4,%le_add_r(TLSL1) -+st.w $r5,$r4,%le_lo12_r(TLSL1) -+ -+/* Part of relaxed LD/GD/DESC insn sequence. */ -+pcaddi $a0,%ld_pcrel_20(TLSL1) -+pcaddi $a0,%gd_pcrel_20(TLSL1) -+pcaddi $a0,%desc_pcrel_20(TLSL1) --- -2.33.0 - diff --git a/LoongArch-Add-gas-testsuit-for-alias-instructions.patch b/LoongArch-Add-gas-testsuit-for-alias-instructions.patch deleted file mode 100644 index 54c3322..0000000 --- a/LoongArch-Add-gas-testsuit-for-alias-instructions.patch +++ /dev/null @@ -1,104 +0,0 @@ -From f2183b3edb1cee6d9fe0c3dbd26956501bcd6904 Mon Sep 17 00:00:00 2001 -From: Lulu Cai -Date: Fri, 5 Jan 2024 11:41:27 +0800 -Subject: [PATCH 062/123] LoongArch: Add gas testsuit for alias instructions - -Test the alias instructions. ---- - gas/testsuite/gas/loongarch/insn_alias_32.d | 19 +++++++++++++++++++ - gas/testsuite/gas/loongarch/insn_alias_32.s | 10 ++++++++++ - gas/testsuite/gas/loongarch/insn_alias_64.d | 20 ++++++++++++++++++++ - gas/testsuite/gas/loongarch/insn_alias_64.s | 11 +++++++++++ - 4 files changed, 60 insertions(+) - create mode 100644 gas/testsuite/gas/loongarch/insn_alias_32.d - create mode 100644 gas/testsuite/gas/loongarch/insn_alias_32.s - create mode 100644 gas/testsuite/gas/loongarch/insn_alias_64.d - create mode 100644 gas/testsuite/gas/loongarch/insn_alias_64.s - -diff --git a/gas/testsuite/gas/loongarch/insn_alias_32.d b/gas/testsuite/gas/loongarch/insn_alias_32.d -new file mode 100644 -index 00000000..753eae7a ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/insn_alias_32.d -@@ -0,0 +1,19 @@ -+#as: -+#objdump: -d -M no-aliases -+#skip: loongarch64-*-* -+ -+.* file format .* -+ -+ -+Disassembly of section .text: -+ -+0+ : -+ 0: 001500a4 or \$a0, \$a1, \$zero -+ 4: 02bffc04 addi.w \$a0, \$zero, -1 -+ 8: 03400000 andi \$zero, \$zero, 0x0 -+ c: 03800404 ori \$a0, \$zero, 0x1 -+ 10: 4c000020 jirl \$zero, \$ra, 0 -+ 14: 4c000020 jirl \$zero, \$ra, 0 -+ 18: 60000080 blt \$a0, \$zero, 0 # 18 -+ 1c: 64000080 bge \$a0, \$zero, 0 # 1c -+ 20: 64000004 bge \$zero, \$a0, 0 # 20 -diff --git a/gas/testsuite/gas/loongarch/insn_alias_32.s b/gas/testsuite/gas/loongarch/insn_alias_32.s -new file mode 100644 -index 00000000..8027e32a ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/insn_alias_32.s -@@ -0,0 +1,10 @@ -+L1: -+ move $a0,$a1 -+ li.w $a0,-1 -+ nop -+ li.w $a0,1 -+ ret -+ jr $ra -+ bltz $a0,.L1 -+ bgez $a0,.L1 -+ blez $a0,.L1 -diff --git a/gas/testsuite/gas/loongarch/insn_alias_64.d b/gas/testsuite/gas/loongarch/insn_alias_64.d -new file mode 100644 -index 00000000..8d3ed7bc ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/insn_alias_64.d -@@ -0,0 +1,20 @@ -+#as-new: -+#objdump: -d -M no-aliases -+#skip: loongarch32-*-* -+ -+.*: file format .* -+ -+ -+Disassembly of section .text: -+ -+0+ : -+ 0: 001500a4 or \$a0, \$a1, \$zero -+ 4: 02bffc04 addi.w \$a0, \$zero, -1 -+ 8: 02bffc04 addi.w \$a0, \$zero, -1 -+ c: 03400000 andi \$zero, \$zero, 0x0 -+ 10: 03800404 ori \$a0, \$zero, 0x1 -+ 14: 4c000020 jirl \$zero, \$ra, 0 -+ 18: 4c000020 jirl \$zero, \$ra, 0 -+ 1c: 60000080 blt \$a0, \$zero, 0 # 1c -+ 20: 64000080 bge \$a0, \$zero, 0 # 20 -+ 24: 64000004 bge \$zero, \$a0, 0 # 24 -diff --git a/gas/testsuite/gas/loongarch/insn_alias_64.s b/gas/testsuite/gas/loongarch/insn_alias_64.s -new file mode 100644 -index 00000000..e7e42638 ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/insn_alias_64.s -@@ -0,0 +1,11 @@ -+L1: -+ move $a0,$a1 -+ li.w $a0,-1 -+ li.d $a0,-1 -+ nop -+ li.w $a0,1 -+ ret -+ jr $ra -+ bltz $a0,.L1 -+ bgez $a0,.L1 -+ blez $a0,.L1 --- -2.33.0 - diff --git a/LoongArch-Add-gas-testsuit-for-lbt-lvz-instructions.patch b/LoongArch-Add-gas-testsuit-for-lbt-lvz-instructions.patch deleted file mode 100644 index 16cae02..0000000 --- a/LoongArch-Add-gas-testsuit-for-lbt-lvz-instructions.patch +++ /dev/null @@ -1,427 +0,0 @@ -From 8b2478a4eab5b880516b32b5d478a1eab5be1f4c Mon Sep 17 00:00:00 2001 -From: Lulu Cai -Date: Fri, 5 Jan 2024 11:58:34 +0800 -Subject: [PATCH 063/123] LoongArch: Add gas testsuit for lbt/lvz instructions - -Test the LBT/LVZ instructions. Only LA64 supports -these instructions. ---- - gas/testsuite/gas/loongarch/insn_lbt.d | 186 +++++++++++++++++++++++++ - gas/testsuite/gas/loongarch/insn_lbt.s | 176 +++++++++++++++++++++++ - gas/testsuite/gas/loongarch/insn_lvz.d | 15 ++ - gas/testsuite/gas/loongarch/insn_lvz.s | 5 + - 4 files changed, 382 insertions(+) - create mode 100644 gas/testsuite/gas/loongarch/insn_lbt.d - create mode 100644 gas/testsuite/gas/loongarch/insn_lbt.s - create mode 100644 gas/testsuite/gas/loongarch/insn_lvz.d - create mode 100644 gas/testsuite/gas/loongarch/insn_lvz.s - -diff --git a/gas/testsuite/gas/loongarch/insn_lbt.d b/gas/testsuite/gas/loongarch/insn_lbt.d -new file mode 100644 -index 00000000..7d80fb89 ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/insn_lbt.d -@@ -0,0 +1,186 @@ -+#as: -+#objdump: -d -+#skip: loongarch32-*-* -+ -+.*: file format .* -+ -+ -+Disassembly of section .text: -+ -+0+ <.*>: -+ 0: 00000820 movgr2scr \$scr0, \$ra -+ 4: 00000c20 movscr2gr \$zero, \$scr1 -+ 8: 48006600 jiscr0 100 -+ c: 48006700 jiscr1 100 -+ 10: 00290420 addu12i.w \$zero, \$ra, 1 -+ 14: 00298420 addu12i.d \$zero, \$ra, 1 -+ 18: 00300820 adc.b \$zero, \$ra, \$tp -+ 1c: 00308820 adc.h \$zero, \$ra, \$tp -+ 20: 00310820 adc.w \$zero, \$ra, \$tp -+ 24: 00318820 adc.d \$zero, \$ra, \$tp -+ 28: 00320820 sbc.b \$zero, \$ra, \$tp -+ 2c: 00328820 sbc.h \$zero, \$ra, \$tp -+ 30: 00330820 sbc.w \$zero, \$ra, \$tp -+ 34: 00338820 sbc.d \$zero, \$ra, \$tp -+ 38: 001a0820 rotr.b \$zero, \$ra, \$tp -+ 3c: 001a8820 rotr.h \$zero, \$ra, \$tp -+ 40: 004c2420 rotri.b \$zero, \$ra, 0x1 -+ 44: 004c4420 rotri.h \$zero, \$ra, 0x1 -+ 48: 00340820 rcr.b \$zero, \$ra, \$tp -+ 4c: 00348820 rcr.h \$zero, \$ra, \$tp -+ 50: 00350820 rcr.w \$zero, \$ra, \$tp -+ 54: 00358820 rcr.d \$zero, \$ra, \$tp -+ 58: 00502420 rcri.b \$zero, \$ra, 0x1 -+ 5c: 00504420 rcri.h \$zero, \$ra, 0x1 -+ 60: 00508420 rcri.w \$zero, \$ra, 0x1 -+ 64: 00510420 rcri.d \$zero, \$ra, 0x1 -+ 68: 0114e420 fcvt.ud.d \$fa0, \$fa1 -+ 6c: 0114e020 fcvt.ld.d \$fa0, \$fa1 -+ 70: 01150820 fcvt.d.ld \$fa0, \$fa1, \$fa2 -+ 74: 2e800420 ldl.d \$zero, \$ra, 1 -+ 78: 2e000420 ldl.w \$zero, \$ra, 1 -+ 7c: 2e400420 ldr.w \$zero, \$ra, 1 -+ 80: 2ec00420 ldr.d \$zero, \$ra, 1 -+ 84: 2f000420 stl.w \$zero, \$ra, 1 -+ 88: 2f800420 stl.d \$zero, \$ra, 1 -+ 8c: 2f400420 str.w \$zero, \$ra, 1 -+ 90: 2fc00420 str.d \$zero, \$ra, 1 -+ 94: 003f040c x86adc.b \$zero, \$ra -+ 98: 003f040d x86adc.h \$zero, \$ra -+ 9c: 003f040e x86adc.w \$zero, \$ra -+ a0: 003f040f x86adc.d \$zero, \$ra -+ a4: 003f0404 x86add.b \$zero, \$ra -+ a8: 003f0405 x86add.h \$zero, \$ra -+ ac: 003f0406 x86add.w \$zero, \$ra -+ b0: 003f0407 x86add.d \$zero, \$ra -+ b4: 003f0400 x86add.wu \$zero, \$ra -+ b8: 003f0401 x86add.du \$zero, \$ra -+ bc: 00008000 x86inc.b \$zero -+ c0: 00008001 x86inc.h \$zero -+ c4: 00008002 x86inc.w \$zero -+ c8: 00008003 x86inc.d \$zero -+ cc: 003f0410 x86sbc.b \$zero, \$ra -+ d0: 003f0411 x86sbc.h \$zero, \$ra -+ d4: 003f0412 x86sbc.w \$zero, \$ra -+ d8: 003f0413 x86sbc.d \$zero, \$ra -+ dc: 003f0408 x86sub.b \$zero, \$ra -+ e0: 003f0409 x86sub.h \$zero, \$ra -+ e4: 003f040a x86sub.w \$zero, \$ra -+ e8: 003f040b x86sub.d \$zero, \$ra -+ ec: 003f0402 x86sub.wu \$zero, \$ra -+ f0: 003f0403 x86sub.du \$zero, \$ra -+ f4: 00008004 x86dec.b \$zero -+ f8: 00008005 x86dec.h \$zero -+ fc: 00008006 x86dec.w \$zero -+ 100: 00008007 x86dec.d \$zero -+ 104: 003f8410 x86and.b \$zero, \$ra -+ 108: 003f8411 x86and.h \$zero, \$ra -+ 10c: 003f8412 x86and.w \$zero, \$ra -+ 110: 003f8413 x86and.d \$zero, \$ra -+ 114: 003f8414 x86or.b \$zero, \$ra -+ 118: 003f8415 x86or.h \$zero, \$ra -+ 11c: 003f8416 x86or.w \$zero, \$ra -+ 120: 003f8417 x86or.d \$zero, \$ra -+ 124: 003f8418 x86xor.b \$zero, \$ra -+ 128: 003f8419 x86xor.h \$zero, \$ra -+ 12c: 003f841a x86xor.w \$zero, \$ra -+ 130: 003f841b x86xor.d \$zero, \$ra -+ 134: 003e8400 x86mul.b \$zero, \$ra -+ 138: 003e8401 x86mul.h \$zero, \$ra -+ 13c: 003e8402 x86mul.w \$zero, \$ra -+ 140: 003e8403 x86mul.d \$zero, \$ra -+ 144: 003e8404 x86mul.bu \$zero, \$ra -+ 148: 003e8405 x86mul.hu \$zero, \$ra -+ 14c: 003e8406 x86mul.wu \$zero, \$ra -+ 150: 003e8407 x86mul.du \$zero, \$ra -+ 154: 003f840c x86rcl.b \$zero, \$ra -+ 158: 003f840d x86rcl.h \$zero, \$ra -+ 15c: 003f840e x86rcl.w \$zero, \$ra -+ 160: 003f840f x86rcl.d \$zero, \$ra -+ 164: 00542418 x86rcli.b \$zero, 0x1 -+ 168: 00544419 x86rcli.h \$zero, 0x1 -+ 16c: 0054841a x86rcli.w \$zero, 0x1 -+ 170: 0055041b x86rcli.d \$zero, 0x1 -+ 174: 003f8408 x86rcr.b \$zero, \$ra -+ 178: 003f8409 x86rcr.h \$zero, \$ra -+ 17c: 003f840a x86rcr.w \$zero, \$ra -+ 180: 003f840b x86rcr.d \$zero, \$ra -+ 184: 00542410 x86rcri.b \$zero, 0x1 -+ 188: 00544411 x86rcri.h \$zero, 0x1 -+ 18c: 00548412 x86rcri.w \$zero, 0x1 -+ 190: 00550413 x86rcri.d \$zero, 0x1 -+ 194: 003f8404 x86rotl.b \$zero, \$ra -+ 198: 003f8405 x86rotl.h \$zero, \$ra -+ 19c: 003f8406 x86rotl.w \$zero, \$ra -+ 1a0: 003f8407 x86rotl.d \$zero, \$ra -+ 1a4: 00542414 x86rotli.b \$zero, 0x1 -+ 1a8: 00544415 x86rotli.h \$zero, 0x1 -+ 1ac: 00548416 x86rotli.w \$zero, 0x1 -+ 1b0: 00550417 x86rotli.d \$zero, 0x1 -+ 1b4: 003f8400 x86rotr.b \$zero, \$ra -+ 1b8: 003f8401 x86rotr.h \$zero, \$ra -+ 1bc: 003f8402 x86rotr.d \$zero, \$ra -+ 1c0: 003f8403 x86rotr.w \$zero, \$ra -+ 1c4: 0054240c x86rotri.b \$zero, 0x1 -+ 1c8: 0054440d x86rotri.h \$zero, 0x1 -+ 1cc: 0054840e x86rotri.w \$zero, 0x1 -+ 1d0: 0055040f x86rotri.d \$zero, 0x1 -+ 1d4: 003f0414 x86sll.b \$zero, \$ra -+ 1d8: 003f0415 x86sll.h \$zero, \$ra -+ 1dc: 003f0416 x86sll.w \$zero, \$ra -+ 1e0: 003f0417 x86sll.d \$zero, \$ra -+ 1e4: 00542400 x86slli.b \$zero, 0x1 -+ 1e8: 00544401 x86slli.h \$zero, 0x1 -+ 1ec: 00548402 x86slli.w \$zero, 0x1 -+ 1f0: 00550403 x86slli.d \$zero, 0x1 -+ 1f4: 003f0418 x86srl.b \$zero, \$ra -+ 1f8: 003f0419 x86srl.h \$zero, \$ra -+ 1fc: 003f041a x86srl.w \$zero, \$ra -+ 200: 003f041b x86srl.d \$zero, \$ra -+ 204: 00542404 x86srli.b \$zero, 0x1 -+ 208: 00544405 x86srli.h \$zero, 0x1 -+ 20c: 00548406 x86srli.w \$zero, 0x1 -+ 210: 00550407 x86srli.d \$zero, 0x1 -+ 214: 003f041c x86sra.b \$zero, \$ra -+ 218: 003f041d x86sra.h \$zero, \$ra -+ 21c: 003f041e x86sra.w \$zero, \$ra -+ 220: 003f041f x86sra.d \$zero, \$ra -+ 224: 00542408 x86srai.b \$zero, 0x1 -+ 228: 00544409 x86srai.h \$zero, 0x1 -+ 22c: 0054840a x86srai.w \$zero, 0x1 -+ 230: 0055040b x86srai.d \$zero, 0x1 -+ 234: 00368400 setx86j \$zero, 0x1 -+ 238: 00007820 setx86loope \$zero, \$ra -+ 23c: 00007c20 setx86loopne \$zero, \$ra -+ 240: 005c0400 x86mfflag \$zero, 0x1 -+ 244: 005c0420 x86mtflag \$zero, 0x1 -+ 248: 00007400 x86mftop \$zero -+ 24c: 00007020 x86mttop 0x1 -+ 250: 00008009 x86inctop -+ 254: 00008029 x86dectop -+ 258: 00008008 x86settm -+ 25c: 00008028 x86clrtm -+ 260: 00580420 x86settag \$zero, 0x1, 0x1 -+ 264: 00370411 armadd.w \$zero, \$ra, 0x1 -+ 268: 00378411 armsub.w \$zero, \$ra, 0x1 -+ 26c: 00380411 armadc.w \$zero, \$ra, 0x1 -+ 270: 00388411 armsbc.w \$zero, \$ra, 0x1 -+ 274: 00390411 armand.w \$zero, \$ra, 0x1 -+ 278: 00398411 armor.w \$zero, \$ra, 0x1 -+ 27c: 003a0411 armxor.w \$zero, \$ra, 0x1 -+ 280: 003fc41c armnot.w \$zero, 0x1 -+ 284: 003a8411 armsll.w \$zero, \$ra, 0x1 -+ 288: 003b0411 armsrl.w \$zero, \$ra, 0x1 -+ 28c: 003b8411 armsra.w \$zero, \$ra, 0x1 -+ 290: 003c0411 armrotr.w \$zero, \$ra, 0x1 -+ 294: 003c8411 armslli.w \$zero, 0x1, 0x1 -+ 298: 003d0411 armsrli.w \$zero, 0x1, 0x1 -+ 29c: 003d8411 armsrai.w \$zero, 0x1, 0x1 -+ 2a0: 003e0411 armrotri.w \$zero, 0x1, 0x1 -+ 2a4: 003fc41f armrrx.w \$zero, 0x1 -+ 2a8: 00364420 armmove \$zero, \$ra, 0x1 -+ 2ac: 003fc41d armmov.w \$zero, 0x1 -+ 2b0: 003fc41e armmov.d \$zero, 0x1 -+ 2b4: 005c0440 armmfflag \$zero, 0x1 -+ 2b8: 005c0460 armmtflag \$zero, 0x1 -+ 2bc: 0036c400 setarmj \$zero, 0x1 -diff --git a/gas/testsuite/gas/loongarch/insn_lbt.s b/gas/testsuite/gas/loongarch/insn_lbt.s -new file mode 100644 -index 00000000..e49453c0 ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/insn_lbt.s -@@ -0,0 +1,176 @@ -+movgr2scr $scr0, $r1 -+movscr2gr $r0, $scr1 -+jiscr0 100 -+jiscr1 100 -+addu12i.w $r0, $r1, 1 -+addu12i.d $r0, $r1, 1 -+adc.b $r0, $r1, $r2 -+adc.h $r0, $r1, $r2 -+adc.w $r0, $r1, $r2 -+adc.d $r0, $r1, $r2 -+sbc.b $r0, $r1, $r2 -+sbc.h $r0, $r1, $r2 -+sbc.w $r0, $r1, $r2 -+sbc.d $r0, $r1, $r2 -+rotr.b $r0, $r1, $r2 -+rotr.h $r0, $r1, $r2 -+rotri.b $r0, $r1, 1 -+rotri.h $r0, $r1, 1 -+rcr.b $r0, $r1, $r2 -+rcr.h $r0, $r1, $r2 -+rcr.w $r0, $r1, $r2 -+rcr.d $r0, $r1, $r2 -+rcri.b $r0, $r1, 1 -+rcri.h $r0, $r1, 1 -+rcri.w $r0, $r1, 1 -+rcri.d $r0, $r1, 1 -+fcvt.ud.d $f0, $f1 -+fcvt.ld.d $f0, $f1 -+fcvt.d.ld $f0, $f1, $f2 -+ldl.d $r0, $r1, 1 -+ldl.w $r0, $r1, 1 -+ldr.w $r0, $r1, 1 -+ldr.d $r0, $r1, 1 -+stl.w $r0, $r1, 1 -+stl.d $r0, $r1, 1 -+str.w $r0, $r1, 1 -+str.d $r0, $r1, 1 -+x86adc.b $r0, $r1 -+x86adc.h $r0, $r1 -+x86adc.w $r0, $r1 -+x86adc.d $r0, $r1 -+x86add.b $r0, $r1 -+x86add.h $r0, $r1 -+x86add.w $r0, $r1 -+x86add.d $r0, $r1 -+x86add.wu $r0, $r1 -+x86add.du $r0, $r1 -+x86inc.b $r0 -+x86inc.h $r0 -+x86inc.w $r0 -+x86inc.d $r0 -+x86sbc.b $r0, $r1 -+x86sbc.h $r0, $r1 -+x86sbc.w $r0, $r1 -+x86sbc.d $r0, $r1 -+x86sub.b $r0, $r1 -+x86sub.h $r0, $r1 -+x86sub.w $r0, $r1 -+x86sub.d $r0, $r1 -+x86sub.wu $r0, $r1 -+x86sub.du $r0, $r1 -+x86dec.b $r0 -+x86dec.h $r0 -+x86dec.w $r0 -+x86dec.d $r0 -+x86and.b $r0, $r1 -+x86and.h $r0, $r1 -+x86and.w $r0, $r1 -+x86and.d $r0, $r1 -+x86or.b $r0, $r1 -+x86or.h $r0, $r1 -+x86or.w $r0, $r1 -+x86or.d $r0, $r1 -+x86xor.b $r0, $r1 -+x86xor.h $r0, $r1 -+x86xor.w $r0, $r1 -+x86xor.d $r0, $r1 -+x86mul.b $r0, $r1 -+x86mul.h $r0, $r1 -+x86mul.w $r0, $r1 -+x86mul.d $r0, $r1 -+x86mul.bu $r0, $r1 -+x86mul.hu $r0, $r1 -+x86mul.wu $r0, $r1 -+x86mul.du $r0, $r1 -+x86rcl.b $r0, $r1 -+x86rcl.h $r0, $r1 -+x86rcl.w $r0, $r1 -+x86rcl.d $r0, $r1 -+x86rcli.b $r0, 1 -+x86rcli.h $r0, 1 -+x86rcli.w $r0, 1 -+x86rcli.d $r0, 1 -+x86rcr.b $r0, $r1 -+x86rcr.h $r0, $r1 -+x86rcr.w $r0, $r1 -+x86rcr.d $r0, $r1 -+x86rcri.b $r0, 1 -+x86rcri.h $r0, 1 -+x86rcri.w $r0, 1 -+x86rcri.d $r0, 1 -+x86rotl.b $r0, $r1 -+x86rotl.h $r0, $r1 -+x86rotl.w $r0, $r1 -+x86rotl.d $r0, $r1 -+x86rotli.b $r0, 1 -+x86rotli.h $r0, 1 -+x86rotli.w $r0, 1 -+x86rotli.d $r0, 1 -+x86rotr.b $r0, $r1 -+x86rotr.h $r0, $r1 -+x86rotr.d $r0, $r1 -+x86rotr.w $r0, $r1 -+x86rotri.b $r0, 1 -+x86rotri.h $r0, 1 -+x86rotri.w $r0, 1 -+x86rotri.d $r0, 1 -+x86sll.b $r0, $r1 -+x86sll.h $r0, $r1 -+x86sll.w $r0, $r1 -+x86sll.d $r0, $r1 -+x86slli.b $r0, 1 -+x86slli.h $r0, 1 -+x86slli.w $r0, 1 -+x86slli.d $r0, 1 -+x86srl.b $r0, $r1 -+x86srl.h $r0, $r1 -+x86srl.w $r0, $r1 -+x86srl.d $r0, $r1 -+x86srli.b $r0, 1 -+x86srli.h $r0, 1 -+x86srli.w $r0, 1 -+x86srli.d $r0, 1 -+x86sra.b $r0, $r1 -+x86sra.h $r0, $r1 -+x86sra.w $r0, $r1 -+x86sra.d $r0, $r1 -+x86srai.b $r0, 1 -+x86srai.h $r0, 1 -+x86srai.w $r0, 1 -+x86srai.d $r0, 1 -+setx86j $r0, 1 -+setx86loope $r0, $r1 -+setx86loopne $r0, $r1 -+x86mfflag $r0, 1 -+x86mtflag $r0, 1 -+x86mftop $r0 -+x86mttop 1 -+x86inctop -+x86dectop -+x86settm -+x86clrtm -+x86settag $r0, 1, 1 -+armadd.w $r0, $r1, 1 -+armsub.w $r0, $r1, 1 -+armadc.w $r0, $r1, 1 -+armsbc.w $r0, $r1, 1 -+armand.w $r0, $r1, 1 -+armor.w $r0, $r1, 1 -+armxor.w $r0, $r1, 1 -+armnot.w $r0, 1 -+armsll.w $r0, $r1, 1 -+armsrl.w $r0, $r1, 1 -+armsra.w $r0, $r1, 1 -+armrotr.w $r0, $r1, 1 -+armslli.w $r0, 1, 1 -+armsrli.w $r0, 1, 1 -+armsrai.w $r0, 1, 1 -+armrotri.w $r0, 1, 1 -+armrrx.w $r0, 1 -+armmove $r0, $r1, 1 -+armmov.w $r0, 1 -+armmov.d $r0, 1 -+armmfflag $r0, 1 -+armmtflag $r0, 1 -+setarmj $r0, 1 -diff --git a/gas/testsuite/gas/loongarch/insn_lvz.d b/gas/testsuite/gas/loongarch/insn_lvz.d -new file mode 100644 -index 00000000..547091ed ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/insn_lvz.d -@@ -0,0 +1,15 @@ -+#as: -+#objdump: -d -+#skip: loongarch32-*-* -+ -+.*: file format .* -+ -+ -+Disassembly of section .text: -+ -+0+ <.*>: -+ 0: 05000400 gcsrrd \$zero, 0x1 -+ 4: 05000420 gcsrwr \$zero, 0x1 -+ 8: 05000483 gcsrxchg \$sp, \$a0, 0x1 -+ c: 06482401 gtlbflush -+ 10: 002b8001 hvcl 0x1 -diff --git a/gas/testsuite/gas/loongarch/insn_lvz.s b/gas/testsuite/gas/loongarch/insn_lvz.s -new file mode 100644 -index 00000000..1b1a5940 ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/insn_lvz.s -@@ -0,0 +1,5 @@ -+gcsrrd $r0, 1 -+gcsrwr $r0, 1 -+gcsrxchg $r3, $r4, 1 -+gtlbflush -+hvcl 1 --- -2.33.0 - diff --git a/LoongArch-Add-gas-testsuit-for-lsx-lasx-instructions.patch b/LoongArch-Add-gas-testsuit-for-lsx-lasx-instructions.patch deleted file mode 100644 index 34b3adc..0000000 --- a/LoongArch-Add-gas-testsuit-for-lsx-lasx-instructions.patch +++ /dev/null @@ -1,2983 +0,0 @@ -From a603a7896467eb497797ff323f3ad61105a1b416 Mon Sep 17 00:00:00 2001 -From: Lulu Cai -Date: Fri, 5 Jan 2024 15:05:13 +0800 -Subject: [PATCH 064/123] LoongArch: Add gas testsuit for lsx/lasx instructions - -Test the LSX/LASX instructions. Only LA64 supports -these instructions. ---- - gas/testsuite/gas/loongarch/insn_lasx.d | 737 +++++++++++++++++++++++ - gas/testsuite/gas/loongarch/insn_lasx.s | 727 +++++++++++++++++++++++ - gas/testsuite/gas/loongarch/insn_lsx.d | 742 ++++++++++++++++++++++++ - gas/testsuite/gas/loongarch/insn_lsx.s | 732 +++++++++++++++++++++++ - 4 files changed, 2938 insertions(+) - create mode 100644 gas/testsuite/gas/loongarch/insn_lasx.d - create mode 100644 gas/testsuite/gas/loongarch/insn_lasx.s - create mode 100644 gas/testsuite/gas/loongarch/insn_lsx.d - create mode 100644 gas/testsuite/gas/loongarch/insn_lsx.s - -diff --git a/gas/testsuite/gas/loongarch/insn_lasx.d b/gas/testsuite/gas/loongarch/insn_lasx.d -new file mode 100644 -index 00000000..74742b5f ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/insn_lasx.d -@@ -0,0 +1,737 @@ -+#as: -+#objdump: -d -+#skip: loongarch32-*-* -+ -+.*: file format .* -+ -+ -+Disassembly of section .text: -+ -+0+ <.*>: -+ 0: 0a118820 xvfmadd.s \$xr0, \$xr1, \$xr2, \$xr3 -+ 4: 0a518820 xvfmsub.s \$xr0, \$xr1, \$xr2, \$xr3 -+ 8: 0a918820 xvfnmadd.s \$xr0, \$xr1, \$xr2, \$xr3 -+ c: 0ad18820 xvfnmsub.s \$xr0, \$xr1, \$xr2, \$xr3 -+ 10: 0c900820 xvfcmp.caf.s \$xr0, \$xr1, \$xr2 -+ 14: 0c908820 xvfcmp.saf.s \$xr0, \$xr1, \$xr2 -+ 18: 0c910820 xvfcmp.clt.s \$xr0, \$xr1, \$xr2 -+ 1c: 0c918820 xvfcmp.slt.s \$xr0, \$xr1, \$xr2 -+ 20: 0c920820 xvfcmp.ceq.s \$xr0, \$xr1, \$xr2 -+ 24: 0c928820 xvfcmp.seq.s \$xr0, \$xr1, \$xr2 -+ 28: 0c930820 xvfcmp.cle.s \$xr0, \$xr1, \$xr2 -+ 2c: 0c938820 xvfcmp.sle.s \$xr0, \$xr1, \$xr2 -+ 30: 0c940820 xvfcmp.cun.s \$xr0, \$xr1, \$xr2 -+ 34: 0c948820 xvfcmp.sun.s \$xr0, \$xr1, \$xr2 -+ 38: 0c950820 xvfcmp.cult.s \$xr0, \$xr1, \$xr2 -+ 3c: 0c958820 xvfcmp.sult.s \$xr0, \$xr1, \$xr2 -+ 40: 0c960820 xvfcmp.cueq.s \$xr0, \$xr1, \$xr2 -+ 44: 0c968820 xvfcmp.sueq.s \$xr0, \$xr1, \$xr2 -+ 48: 0c970820 xvfcmp.cule.s \$xr0, \$xr1, \$xr2 -+ 4c: 0c978820 xvfcmp.sule.s \$xr0, \$xr1, \$xr2 -+ 50: 0c980820 xvfcmp.cne.s \$xr0, \$xr1, \$xr2 -+ 54: 0c988820 xvfcmp.sne.s \$xr0, \$xr1, \$xr2 -+ 58: 0c9a0820 xvfcmp.cor.s \$xr0, \$xr1, \$xr2 -+ 5c: 0c9a8820 xvfcmp.sor.s \$xr0, \$xr1, \$xr2 -+ 60: 0c9c0820 xvfcmp.cune.s \$xr0, \$xr1, \$xr2 -+ 64: 0c9c8820 xvfcmp.sune.s \$xr0, \$xr1, \$xr2 -+ 68: 0d218820 xvbitsel.v \$xr0, \$xr1, \$xr2, \$xr3 -+ 6c: 0d618820 xvshuf.b \$xr0, \$xr1, \$xr2, \$xr3 -+ 70: 0a218820 xvfmadd.d \$xr0, \$xr1, \$xr2, \$xr3 -+ 74: 0a618820 xvfmsub.d \$xr0, \$xr1, \$xr2, \$xr3 -+ 78: 0aa18820 xvfnmadd.d \$xr0, \$xr1, \$xr2, \$xr3 -+ 7c: 0ae18820 xvfnmsub.d \$xr0, \$xr1, \$xr2, \$xr3 -+ 80: 0ca00820 xvfcmp.caf.d \$xr0, \$xr1, \$xr2 -+ 84: 0ca08820 xvfcmp.saf.d \$xr0, \$xr1, \$xr2 -+ 88: 0ca10820 xvfcmp.clt.d \$xr0, \$xr1, \$xr2 -+ 8c: 0ca18820 xvfcmp.slt.d \$xr0, \$xr1, \$xr2 -+ 90: 0ca20820 xvfcmp.ceq.d \$xr0, \$xr1, \$xr2 -+ 94: 0ca28820 xvfcmp.seq.d \$xr0, \$xr1, \$xr2 -+ 98: 0ca30820 xvfcmp.cle.d \$xr0, \$xr1, \$xr2 -+ 9c: 0ca38820 xvfcmp.sle.d \$xr0, \$xr1, \$xr2 -+ a0: 0ca40820 xvfcmp.cun.d \$xr0, \$xr1, \$xr2 -+ a4: 0ca48820 xvfcmp.sun.d \$xr0, \$xr1, \$xr2 -+ a8: 0ca50820 xvfcmp.cult.d \$xr0, \$xr1, \$xr2 -+ ac: 0ca58820 xvfcmp.sult.d \$xr0, \$xr1, \$xr2 -+ b0: 0ca60820 xvfcmp.cueq.d \$xr0, \$xr1, \$xr2 -+ b4: 0ca68820 xvfcmp.sueq.d \$xr0, \$xr1, \$xr2 -+ b8: 0ca70820 xvfcmp.cule.d \$xr0, \$xr1, \$xr2 -+ bc: 0ca78820 xvfcmp.sule.d \$xr0, \$xr1, \$xr2 -+ c0: 0ca80820 xvfcmp.cne.d \$xr0, \$xr1, \$xr2 -+ c4: 0ca88820 xvfcmp.sne.d \$xr0, \$xr1, \$xr2 -+ c8: 0caa0820 xvfcmp.cor.d \$xr0, \$xr1, \$xr2 -+ cc: 0caa8820 xvfcmp.sor.d \$xr0, \$xr1, \$xr2 -+ d0: 0cac0820 xvfcmp.cune.d \$xr0, \$xr1, \$xr2 -+ d4: 0cac8820 xvfcmp.sune.d \$xr0, \$xr1, \$xr2 -+ d8: 2c800420 xvld \$xr0, \$ra, 1 -+ dc: 2cc00420 xvst \$xr0, \$ra, 1 -+ e0: 38480820 xvldx \$xr0, \$ra, \$tp -+ e4: 384c0820 xvstx \$xr0, \$ra, \$tp -+ e8: 3211f420 xvldrepl.d \$xr0, \$ra, 1000 -+ ec: 32206420 xvldrepl.w \$xr0, \$ra, 100 -+ f0: 32401420 xvldrepl.h \$xr0, \$ra, 10 -+ f4: 32800420 xvldrepl.b \$xr0, \$ra, 1 -+ f8: 3315f420 xvstelm.d \$xr0, \$ra, 1000, 0x1 -+ fc: 33246420 xvstelm.w \$xr0, \$ra, 100, 0x1 -+ 100: 33441420 xvstelm.h \$xr0, \$ra, 10, 0x1 -+ 104: 33840420 xvstelm.b \$xr0, \$ra, 1, 0x1 -+ 108: 74000820 xvseq.b \$xr0, \$xr1, \$xr2 -+ 10c: 74008820 xvseq.h \$xr0, \$xr1, \$xr2 -+ 110: 74010820 xvseq.w \$xr0, \$xr1, \$xr2 -+ 114: 74018820 xvseq.d \$xr0, \$xr1, \$xr2 -+ 118: 74020820 xvsle.b \$xr0, \$xr1, \$xr2 -+ 11c: 74028820 xvsle.h \$xr0, \$xr1, \$xr2 -+ 120: 74030820 xvsle.w \$xr0, \$xr1, \$xr2 -+ 124: 74038820 xvsle.d \$xr0, \$xr1, \$xr2 -+ 128: 74040820 xvsle.bu \$xr0, \$xr1, \$xr2 -+ 12c: 74048820 xvsle.hu \$xr0, \$xr1, \$xr2 -+ 130: 74050820 xvsle.wu \$xr0, \$xr1, \$xr2 -+ 134: 74058820 xvsle.du \$xr0, \$xr1, \$xr2 -+ 138: 74060820 xvslt.b \$xr0, \$xr1, \$xr2 -+ 13c: 74068820 xvslt.h \$xr0, \$xr1, \$xr2 -+ 140: 74070820 xvslt.w \$xr0, \$xr1, \$xr2 -+ 144: 74078820 xvslt.d \$xr0, \$xr1, \$xr2 -+ 148: 74080820 xvslt.bu \$xr0, \$xr1, \$xr2 -+ 14c: 74088820 xvslt.hu \$xr0, \$xr1, \$xr2 -+ 150: 74090820 xvslt.wu \$xr0, \$xr1, \$xr2 -+ 154: 74098820 xvslt.du \$xr0, \$xr1, \$xr2 -+ 158: 740a0820 xvadd.b \$xr0, \$xr1, \$xr2 -+ 15c: 740a8820 xvadd.h \$xr0, \$xr1, \$xr2 -+ 160: 740b0820 xvadd.w \$xr0, \$xr1, \$xr2 -+ 164: 740b8820 xvadd.d \$xr0, \$xr1, \$xr2 -+ 168: 740c0820 xvsub.b \$xr0, \$xr1, \$xr2 -+ 16c: 740c8820 xvsub.h \$xr0, \$xr1, \$xr2 -+ 170: 740d0820 xvsub.w \$xr0, \$xr1, \$xr2 -+ 174: 740d8820 xvsub.d \$xr0, \$xr1, \$xr2 -+ 178: 74460820 xvsadd.b \$xr0, \$xr1, \$xr2 -+ 17c: 74468820 xvsadd.h \$xr0, \$xr1, \$xr2 -+ 180: 74470820 xvsadd.w \$xr0, \$xr1, \$xr2 -+ 184: 74478820 xvsadd.d \$xr0, \$xr1, \$xr2 -+ 188: 74480820 xvssub.b \$xr0, \$xr1, \$xr2 -+ 18c: 74488820 xvssub.h \$xr0, \$xr1, \$xr2 -+ 190: 74490820 xvssub.w \$xr0, \$xr1, \$xr2 -+ 194: 74498820 xvssub.d \$xr0, \$xr1, \$xr2 -+ 198: 744a0820 xvsadd.bu \$xr0, \$xr1, \$xr2 -+ 19c: 744a8820 xvsadd.hu \$xr0, \$xr1, \$xr2 -+ 1a0: 744b0820 xvsadd.wu \$xr0, \$xr1, \$xr2 -+ 1a4: 744b8820 xvsadd.du \$xr0, \$xr1, \$xr2 -+ 1a8: 744c0820 xvssub.bu \$xr0, \$xr1, \$xr2 -+ 1ac: 744c8820 xvssub.hu \$xr0, \$xr1, \$xr2 -+ 1b0: 744d0820 xvssub.wu \$xr0, \$xr1, \$xr2 -+ 1b4: 744d8820 xvssub.du \$xr0, \$xr1, \$xr2 -+ 1b8: 74540820 xvhaddw.h.b \$xr0, \$xr1, \$xr2 -+ 1bc: 74548820 xvhaddw.w.h \$xr0, \$xr1, \$xr2 -+ 1c0: 74550820 xvhaddw.d.w \$xr0, \$xr1, \$xr2 -+ 1c4: 74558820 xvhaddw.q.d \$xr0, \$xr1, \$xr2 -+ 1c8: 74560820 xvhsubw.h.b \$xr0, \$xr1, \$xr2 -+ 1cc: 74568820 xvhsubw.w.h \$xr0, \$xr1, \$xr2 -+ 1d0: 74570820 xvhsubw.d.w \$xr0, \$xr1, \$xr2 -+ 1d4: 74578820 xvhsubw.q.d \$xr0, \$xr1, \$xr2 -+ 1d8: 74580820 xvhaddw.hu.bu \$xr0, \$xr1, \$xr2 -+ 1dc: 74588820 xvhaddw.wu.hu \$xr0, \$xr1, \$xr2 -+ 1e0: 74590820 xvhaddw.du.wu \$xr0, \$xr1, \$xr2 -+ 1e4: 74598820 xvhaddw.qu.du \$xr0, \$xr1, \$xr2 -+ 1e8: 745a0820 xvhsubw.hu.bu \$xr0, \$xr1, \$xr2 -+ 1ec: 745a8820 xvhsubw.wu.hu \$xr0, \$xr1, \$xr2 -+ 1f0: 745b0820 xvhsubw.du.wu \$xr0, \$xr1, \$xr2 -+ 1f4: 745b8820 xvhsubw.qu.du \$xr0, \$xr1, \$xr2 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-+xvfrecipe.d $xr0, $xr1 -+xvfrsqrte.s $xr0, $xr1 -+xvfrsqrte.d $xr0, $xr1 -diff --git a/gas/testsuite/gas/loongarch/insn_lsx.d b/gas/testsuite/gas/loongarch/insn_lsx.d -new file mode 100644 -index 00000000..8bf5bb54 ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/insn_lsx.d -@@ -0,0 +1,742 @@ -+#as: -+#objdump: -d -+#skip: loongarch32-*-* -+ -+.*: file format .* -+ -+ -+Disassembly of section .text: -+ -+0+ <.*>: -+ 0: 09118820 vfmadd.s \$vr0, \$vr1, \$vr2, \$vr3 -+ 4: 09518820 vfmsub.s \$vr0, \$vr1, \$vr2, \$vr3 -+ 8: 09918820 vfnmadd.s \$vr0, \$vr1, \$vr2, \$vr3 -+ c: 09d18820 vfnmsub.s \$vr0, \$vr1, \$vr2, \$vr3 -+ 10: 0c500820 vfcmp.caf.s \$vr0, \$vr1, \$vr2 -+ 14: 0c508820 vfcmp.saf.s \$vr0, \$vr1, \$vr2 -+ 18: 0c510820 vfcmp.clt.s \$vr0, \$vr1, \$vr2 -+ 1c: 0c518820 vfcmp.slt.s \$vr0, \$vr1, \$vr2 -+ 20: 0c520820 vfcmp.ceq.s \$vr0, \$vr1, \$vr2 -+ 24: 0c528820 vfcmp.seq.s \$vr0, \$vr1, \$vr2 -+ 28: 0c530820 vfcmp.cle.s \$vr0, \$vr1, \$vr2 -+ 2c: 0c538820 vfcmp.sle.s \$vr0, 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/dev/null -+++ b/gas/testsuite/gas/loongarch/insn_lsx.s -@@ -0,0 +1,732 @@ -+vfmadd.s $vr0, $vr1, $vr2, $vr3 -+vfmsub.s $vr0, $vr1, $vr2, $vr3 -+vfnmadd.s $vr0, $vr1, $vr2, $vr3 -+vfnmsub.s $vr0, $vr1, $vr2, $vr3 -+vfcmp.caf.s $vr0, $vr1, $vr2 -+vfcmp.saf.s $vr0, $vr1, $vr2 -+vfcmp.clt.s $vr0, $vr1, $vr2 -+vfcmp.slt.s $vr0, $vr1, $vr2 -+vfcmp.ceq.s $vr0, $vr1, $vr2 -+vfcmp.seq.s $vr0, $vr1, $vr2 -+vfcmp.cle.s $vr0, $vr1, $vr2 -+vfcmp.sle.s $vr0, $vr1, $vr2 -+vfcmp.cun.s $vr0, $vr1, $vr2 -+vfcmp.sun.s $vr0, $vr1, $vr2 -+vfcmp.cult.s $vr0, $vr1, $vr2 -+vfcmp.sult.s $vr0, $vr1, $vr2 -+vfcmp.cueq.s $vr0, $vr1, $vr2 -+vfcmp.sueq.s $vr0, $vr1, $vr2 -+vfcmp.cule.s $vr0, $vr1, $vr2 -+vfcmp.sule.s $vr0, $vr1, $vr2 -+vfcmp.cne.s $vr0, $vr1, $vr2 -+vfcmp.sne.s $vr0, $vr1, $vr2 -+vfcmp.cor.s $vr0, $vr1, $vr2 -+vfcmp.sor.s $vr0, $vr1, $vr2 -+vfcmp.cune.s $vr0, $vr1, $vr2 -+vfcmp.sune.s $vr0, $vr1, $vr2 -+vbitsel.v $vr0, $vr1, $vr2, $vr3 -+vshuf.b $vr0, $vr1, $vr2, $vr3 -+vfmadd.d $vr0, $vr1, $vr2, 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$vr0, $r1, 1000, 1 -+vstelm.w $vr0, $r1, 100, 1 -+vstelm.h $vr0, $r1, 10, 1 -+vstelm.b $vr0, $r1, 1, 1 -+vseq.b $vr0, $vr1, $vr2 -+vseq.h $vr0, $vr1, $vr2 -+vseq.w $vr0, $vr1, $vr2 -+vseq.d $vr0, $vr1, $vr2 -+vsle.b $vr0, $vr1, $vr2 -+vsle.h $vr0, $vr1, $vr2 -+vsle.w $vr0, $vr1, $vr2 -+vsle.d $vr0, $vr1, $vr2 -+vsle.bu $vr0, $vr1, $vr2 -+vsle.hu $vr0, $vr1, $vr2 -+vsle.wu $vr0, $vr1, $vr2 -+vsle.du $vr0, $vr1, $vr2 -+vslt.b $vr0, $vr1, $vr2 -+vslt.h $vr0, $vr1, $vr2 -+vslt.w $vr0, $vr1, $vr2 -+vslt.d $vr0, $vr1, $vr2 -+vslt.bu $vr0, $vr1, $vr2 -+vslt.hu $vr0, $vr1, $vr2 -+vslt.wu $vr0, $vr1, $vr2 -+vslt.du $vr0, $vr1, $vr2 -+vadd.b $vr0, $vr1, $vr2 -+vadd.h $vr0, $vr1, $vr2 -+vadd.w $vr0, $vr1, $vr2 -+vadd.d $vr0, $vr1, $vr2 -+vsub.b $vr0, $vr1, $vr2 -+vsub.h $vr0, $vr1, $vr2 -+vsub.w $vr0, $vr1, $vr2 -+vsub.d $vr0, $vr1, $vr2 -+vsadd.b $vr0, $vr1, $vr2 -+vsadd.h $vr0, $vr1, $vr2 -+vsadd.w $vr0, $vr1, $vr2 -+vsadd.d $vr0, $vr1, $vr2 -+vssub.b $vr0, $vr1, $vr2 -+vssub.h $vr0, $vr1, $vr2 -+vssub.w $vr0, $vr1, $vr2 -+vssub.d $vr0, $vr1, $vr2 -+vsadd.bu $vr0, $vr1, $vr2 -+vsadd.hu $vr0, $vr1, $vr2 -+vsadd.wu $vr0, $vr1, $vr2 -+vsadd.du $vr0, $vr1, $vr2 -+vssub.bu $vr0, $vr1, $vr2 -+vssub.hu $vr0, $vr1, $vr2 -+vssub.wu $vr0, $vr1, $vr2 -+vssub.du $vr0, $vr1, $vr2 -+vhaddw.h.b $vr0, $vr1, $vr2 -+vhaddw.w.h $vr0, $vr1, $vr2 -+vhaddw.d.w $vr0, $vr1, $vr2 -+vhaddw.q.d $vr0, $vr1, $vr2 -+vhsubw.h.b $vr0, $vr1, $vr2 -+vhsubw.w.h $vr0, $vr1, $vr2 -+vhsubw.d.w $vr0, $vr1, $vr2 -+vhsubw.q.d $vr0, $vr1, $vr2 -+vhaddw.hu.bu $vr0, $vr1, $vr2 -+vhaddw.wu.hu $vr0, $vr1, $vr2 -+vhaddw.du.wu $vr0, $vr1, $vr2 -+vhaddw.qu.du $vr0, $vr1, $vr2 -+vhsubw.hu.bu $vr0, $vr1, $vr2 -+vhsubw.wu.hu $vr0, $vr1, $vr2 -+vhsubw.du.wu $vr0, $vr1, $vr2 -+vhsubw.qu.du $vr0, $vr1, $vr2 -+vadda.b $vr0, $vr1, $vr2 -+vadda.h $vr0, $vr1, $vr2 -+vadda.w $vr0, $vr1, $vr2 -+vadda.d $vr0, $vr1, $vr2 -+vabsd.b $vr0, $vr1, $vr2 -+vabsd.h $vr0, $vr1, $vr2 -+vabsd.w $vr0, $vr1, $vr2 -+vabsd.d $vr0, $vr1, $vr2 -+vabsd.bu $vr0, $vr1, $vr2 -+vabsd.hu $vr0, $vr1, $vr2 -+vabsd.wu $vr0, $vr1, $vr2 -+vabsd.du $vr0, $vr1, $vr2 -+vavg.b $vr0, $vr1, $vr2 -+vavg.h $vr0, $vr1, $vr2 -+vavg.w $vr0, $vr1, $vr2 -+vavg.d $vr0, $vr1, $vr2 -+vavg.bu $vr0, $vr1, $vr2 -+vavg.hu $vr0, $vr1, $vr2 -+vavg.wu $vr0, $vr1, $vr2 -+vavg.du $vr0, $vr1, $vr2 -+vavgr.b $vr0, $vr1, $vr2 -+vavgr.h $vr0, $vr1, $vr2 -+vavgr.w $vr0, $vr1, $vr2 -+vavgr.d $vr0, $vr1, $vr2 -+vavgr.bu $vr0, $vr1, $vr2 -+vavgr.hu $vr0, $vr1, $vr2 -+vavgr.wu $vr0, $vr1, $vr2 -+vavgr.du $vr0, $vr1, $vr2 -+vmax.b $vr0, $vr1, $vr2 -+vmax.h $vr0, $vr1, $vr2 -+vmax.w $vr0, $vr1, $vr2 -+vmax.d $vr0, $vr1, $vr2 -+vmin.b $vr0, $vr1, $vr2 -+vmin.h $vr0, $vr1, $vr2 -+vmin.w $vr0, $vr1, $vr2 -+vmin.d $vr0, $vr1, $vr2 -+vmax.bu $vr0, $vr1, $vr2 -+vmax.hu $vr0, $vr1, $vr2 -+vmax.wu $vr0, $vr1, $vr2 -+vmax.du $vr0, $vr1, $vr2 -+vmin.bu $vr0, $vr1, $vr2 -+vmin.hu $vr0, $vr1, $vr2 -+vmin.wu $vr0, $vr1, $vr2 -+vmin.du $vr0, $vr1, $vr2 -+vmul.b $vr0, $vr1, $vr2 -+vmul.h $vr0, $vr1, $vr2 -+vmul.w $vr0, $vr1, $vr2 -+vmul.d $vr0, $vr1, $vr2 -+vmuh.b $vr0, $vr1, $vr2 -+vmuh.h $vr0, $vr1, $vr2 -+vmuh.w $vr0, $vr1, $vr2 -+vmuh.d $vr0, $vr1, $vr2 -+vmuh.bu $vr0, $vr1, $vr2 -+vmuh.hu $vr0, $vr1, $vr2 -+vmuh.wu $vr0, $vr1, $vr2 -+vmuh.du $vr0, $vr1, $vr2 -+vmadd.b $vr0, $vr1, $vr2 -+vmadd.h $vr0, $vr1, $vr2 -+vmadd.w $vr0, $vr1, $vr2 -+vmadd.d $vr0, $vr1, $vr2 -+vmsub.b $vr0, $vr1, $vr2 -+vmsub.h $vr0, $vr1, $vr2 -+vmsub.w $vr0, $vr1, $vr2 -+vmsub.d $vr0, $vr1, $vr2 -+vdiv.b $vr0, $vr1, $vr2 -+vdiv.h $vr0, $vr1, $vr2 -+vdiv.w $vr0, $vr1, $vr2 -+vdiv.d $vr0, $vr1, $vr2 -+vmod.b $vr0, $vr1, $vr2 -+vmod.h $vr0, $vr1, $vr2 -+vmod.w $vr0, $vr1, $vr2 -+vmod.d $vr0, $vr1, $vr2 -+vdiv.bu $vr0, $vr1, $vr2 -+vdiv.hu $vr0, $vr1, $vr2 -+vdiv.wu $vr0, $vr1, $vr2 -+vdiv.du $vr0, $vr1, $vr2 -+vmod.bu $vr0, $vr1, $vr2 -+vmod.hu $vr0, $vr1, $vr2 -+vmod.wu $vr0, $vr1, $vr2 -+vmod.du $vr0, $vr1, $vr2 -+vsll.b $vr0, $vr1, $vr2 -+vsll.h $vr0, $vr1, $vr2 -+vsll.w $vr0, $vr1, $vr2 -+vsll.d $vr0, $vr1, $vr2 -+vsrl.b $vr0, $vr1, $vr2 -+vsrl.h $vr0, $vr1, $vr2 -+vsrl.w $vr0, $vr1, $vr2 -+vsrl.d $vr0, $vr1, $vr2 -+vsra.b $vr0, $vr1, $vr2 -+vsra.h $vr0, $vr1, $vr2 -+vsra.w $vr0, $vr1, $vr2 -+vsra.d $vr0, $vr1, $vr2 -+vrotr.b $vr0, $vr1, $vr2 -+vrotr.h $vr0, $vr1, $vr2 -+vrotr.w $vr0, $vr1, $vr2 -+vrotr.d $vr0, $vr1, $vr2 -+vsrlr.b $vr0, $vr1, $vr2 -+vsrlr.h $vr0, $vr1, $vr2 -+vsrlr.w $vr0, $vr1, $vr2 -+vsrlr.d $vr0, $vr1, $vr2 -+vsrar.b $vr0, $vr1, $vr2 -+vsrar.h $vr0, $vr1, $vr2 -+vsrar.w $vr0, $vr1, $vr2 -+vsrar.d $vr0, $vr1, $vr2 -+vsrln.b.h $vr0, $vr1, $vr2 -+vsrln.h.w $vr0, $vr1, $vr2 -+vsrln.w.d $vr0, $vr1, $vr2 -+vsran.b.h $vr0, $vr1, $vr2 -+vsran.h.w $vr0, $vr1, $vr2 -+vsran.w.d $vr0, $vr1, $vr2 -+vsrlrn.b.h $vr0, $vr1, $vr2 -+vsrlrn.h.w $vr0, $vr1, $vr2 -+vsrlrn.w.d $vr0, $vr1, $vr2 -+vsrarn.b.h $vr0, $vr1, $vr2 -+vsrarn.h.w $vr0, $vr1, $vr2 -+vsrarn.w.d $vr0, $vr1, $vr2 -+vssrln.b.h $vr0, $vr1, $vr2 -+vssrln.h.w $vr0, $vr1, $vr2 -+vssrln.w.d $vr0, $vr1, $vr2 -+vssran.b.h $vr0, $vr1, $vr2 -+vssran.h.w $vr0, $vr1, $vr2 -+vssran.w.d $vr0, $vr1, $vr2 -+vssrlrn.b.h $vr0, $vr1, $vr2 -+vssrlrn.h.w $vr0, $vr1, $vr2 -+vssrlrn.w.d $vr0, $vr1, $vr2 -+vssrarn.b.h $vr0, $vr1, $vr2 -+vssrarn.h.w $vr0, $vr1, $vr2 -+vssrarn.w.d $vr0, $vr1, $vr2 -+vssrln.bu.h $vr0, $vr1, $vr2 -+vssrln.hu.w $vr0, $vr1, $vr2 -+vssrln.wu.d $vr0, $vr1, $vr2 -+vssran.bu.h $vr0, $vr1, $vr2 -+vssran.hu.w $vr0, $vr1, $vr2 -+vssran.wu.d $vr0, $vr1, $vr2 -+vssrlrn.bu.h $vr0, $vr1, $vr2 -+vssrlrn.hu.w $vr0, $vr1, $vr2 -+vssrlrn.wu.d $vr0, $vr1, $vr2 -+vssrarn.bu.h $vr0, $vr1, $vr2 -+vssrarn.hu.w $vr0, $vr1, $vr2 -+vssrarn.wu.d $vr0, $vr1, $vr2 -+vbitclr.b $vr0, $vr1, $vr2 -+vbitclr.h $vr0, $vr1, $vr2 -+vbitclr.w $vr0, $vr1, $vr2 -+vbitclr.d $vr0, $vr1, $vr2 -+vbitset.b $vr0, $vr1, $vr2 -+vbitset.h $vr0, $vr1, $vr2 -+vbitset.w $vr0, $vr1, $vr2 -+vbitset.d $vr0, $vr1, $vr2 -+vbitrev.b $vr0, $vr1, $vr2 -+vbitrev.h $vr0, $vr1, $vr2 -+vbitrev.w $vr0, $vr1, $vr2 -+vbitrev.d $vr0, $vr1, $vr2 -+vpackev.b $vr0, $vr1, $vr2 -+vpackev.h $vr0, $vr1, $vr2 -+vpackev.w $vr0, $vr1, $vr2 -+vpackev.d $vr0, $vr1, $vr2 -+vpackod.b $vr0, $vr1, $vr2 -+vpackod.h $vr0, $vr1, $vr2 -+vpackod.w $vr0, $vr1, $vr2 -+vpackod.d $vr0, $vr1, $vr2 -+vilvl.b $vr0, $vr1, $vr2 -+vilvl.h $vr0, $vr1, $vr2 -+vilvl.w $vr0, $vr1, $vr2 -+vilvl.d $vr0, $vr1, $vr2 -+vilvh.b $vr0, $vr1, $vr2 -+vilvh.h $vr0, $vr1, $vr2 -+vilvh.w $vr0, $vr1, $vr2 -+vilvh.d $vr0, $vr1, $vr2 -+vpickev.b $vr0, $vr1, $vr2 -+vpickev.h $vr0, $vr1, $vr2 -+vpickev.w $vr0, $vr1, $vr2 -+vpickev.d $vr0, $vr1, $vr2 -+vpickod.b $vr0, $vr1, $vr2 -+vpickod.h $vr0, $vr1, $vr2 -+vpickod.w $vr0, $vr1, $vr2 -+vpickod.d $vr0, $vr1, $vr2 -+vreplve.b $vr0, $vr1, $r2 -+vreplve.h $vr0, $vr1, $r2 -+vreplve.w $vr0, $vr1, $r2 -+vreplve.d $vr0, $vr1, $r2 -+vand.v $vr0, $vr1, $vr2 -+vor.v $vr0, $vr1, $vr2 -+vxor.v $vr0, $vr1, $vr2 -+vnor.v $vr0, $vr1, $vr2 -+vandn.v $vr0, $vr1, $vr2 -+vorn.v $vr0, $vr1, $vr2 -+vfrstp.b $vr0, $vr1, $vr2 -+vfrstp.h $vr0, $vr1, $vr2 -+vadd.q $vr0, $vr1, $vr2 -+vsub.q $vr0, $vr1, $vr2 -+vsigncov.b $vr0, $vr1, $vr2 -+vsigncov.h $vr0, $vr1, $vr2 -+vsigncov.w $vr0, $vr1, $vr2 -+vsigncov.d $vr0, $vr1, $vr2 -+vfadd.s $vr0, $vr1, $vr2 -+vfadd.d $vr0, $vr1, $vr2 -+vfsub.s $vr0, $vr1, $vr2 -+vfsub.d $vr0, $vr1, $vr2 -+vfmul.s $vr0, $vr1, $vr2 -+vfmul.d $vr0, $vr1, $vr2 -+vfdiv.s $vr0, $vr1, $vr2 -+vfdiv.d $vr0, $vr1, $vr2 -+vfmax.s $vr0, $vr1, $vr2 -+vfmax.d $vr0, $vr1, $vr2 -+vfmin.s $vr0, $vr1, $vr2 -+vfmin.d $vr0, $vr1, $vr2 -+vfmaxa.s $vr0, $vr1, $vr2 -+vfmaxa.d $vr0, $vr1, $vr2 -+vfmina.s $vr0, $vr1, $vr2 -+vfmina.d $vr0, $vr1, $vr2 -+vfcvt.h.s $vr0, $vr1, $vr2 -+vfcvt.s.d $vr0, $vr1, $vr2 -+vffint.s.l $vr0, $vr1, $vr2 -+vftint.w.d $vr0, $vr1, $vr2 -+vftintrm.w.d $vr0, $vr1, $vr2 -+vftintrp.w.d $vr0, $vr1, $vr2 -+vftintrz.w.d $vr0, $vr1, $vr2 -+vftintrne.w.d $vr0, $vr1, $vr2 -+vshuf.h $vr0, $vr1, $vr2 -+vshuf.w $vr0, $vr1, $vr2 -+vshuf.d $vr0, $vr1, $vr2 -+vseqi.b $vr0, $vr1, 1 -+vseqi.h $vr0, $vr1, 1 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$vr1, 1 -+vmini.hu $vr0, $vr1, 1 -+vmini.wu $vr0, $vr1, 1 -+vmini.du $vr0, $vr1, 1 -+vfrstpi.b $vr0, $vr1, 1 -+vfrstpi.h $vr0, $vr1, 1 -+vclo.b $vr0, $vr1 -+vclo.h $vr0, $vr1 -+vclo.w $vr0, $vr1 -+vclo.d $vr0, $vr1 -+vclz.b $vr0, $vr1 -+vclz.h $vr0, $vr1 -+vclz.w $vr0, $vr1 -+vclz.d $vr0, $vr1 -+vpcnt.b $vr0, $vr1 -+vpcnt.h $vr0, $vr1 -+vpcnt.w $vr0, $vr1 -+vpcnt.d $vr0, $vr1 -+vneg.b $vr0, $vr1 -+vneg.h $vr0, $vr1 -+vneg.w $vr0, $vr1 -+vneg.d $vr0, $vr1 -+vmskltz.b $vr0, $vr1 -+vmskltz.h $vr0, $vr1 -+vmskltz.w $vr0, $vr1 -+vmskltz.d $vr0, $vr1 -+vmskgez.b $vr0, $vr1 -+vmsknz.b $vr0, $vr1 -+vseteqz.v $fcc0, $vr1 -+vsetnez.v $fcc0, $vr1 -+vsetanyeqz.b $fcc0, $vr1 -+vsetanyeqz.h $fcc0, $vr1 -+vsetanyeqz.w $fcc0, $vr1 -+vsetanyeqz.d $fcc0, $vr1 -+vsetallnez.b $fcc0, $vr1 -+vsetallnez.h $fcc0, $vr1 -+vsetallnez.w $fcc0, $vr1 -+vsetallnez.d $fcc0, $vr1 -+vflogb.s $vr0, $vr1 -+vflogb.d $vr0, $vr1 -+vfclass.s $vr0, $vr1 -+vfclass.d $vr0, $vr1 -+vfsqrt.s $vr0, $vr1 -+vfsqrt.d $vr0, $vr1 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$vr0, $vr1, 1 -+vslli.h $vr0, $vr1, 1 -+vslli.w $vr0, $vr1, 1 -+vslli.d $vr0, $vr1, 1 -+vsrli.b $vr0, $vr1, 1 -+vsrli.h $vr0, $vr1, 1 -+vsrli.w $vr0, $vr1, 1 -+vsrli.d $vr0, $vr1, 1 -+vsrai.b $vr0, $vr1, 1 -+vsrai.h $vr0, $vr1, 1 -+vsrai.w $vr0, $vr1, 1 -+vsrai.d $vr0, $vr1, 1 -+vsrlni.b.h $vr0, $vr1, 1 -+vsrlni.h.w $vr0, $vr1, 1 -+vsrlni.w.d $vr0, $vr1, 1 -+vsrlni.d.q $vr0, $vr1, 1 -+vssrlni.b.h $vr0, $vr1, 1 -+vssrlni.h.w $vr0, $vr1, 1 -+vssrlni.w.d $vr0, $vr1, 1 -+vssrlni.d.q $vr0, $vr1, 1 -+vsrlrni.b.h $vr0, $vr1, 1 -+vsrlrni.h.w $vr0, $vr1, 1 -+vsrlrni.w.d $vr0, $vr1, 1 -+vsrlrni.d.q $vr0, $vr1, 1 -+vssrlni.bu.h $vr0, $vr1, 1 -+vssrlni.hu.w $vr0, $vr1, 1 -+vssrlni.wu.d $vr0, $vr1, 1 -+vssrlni.du.q $vr0, $vr1, 1 -+vssrlrni.b.h $vr0, $vr1, 1 -+vssrlrni.h.w $vr0, $vr1, 1 -+vssrlrni.w.d $vr0, $vr1, 1 -+vssrlrni.d.q $vr0, $vr1, 1 -+vssrlrni.bu.h $vr0, $vr1, 1 -+vssrlrni.hu.w $vr0, $vr1, 1 -+vssrlrni.wu.d $vr0, $vr1, 1 -+vssrlrni.du.q $vr0, $vr1, 1 -+vsrani.b.h $vr0, $vr1, 1 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-+vrepli.b $vr0, 1 -+vaddwev.h.b $vr0, $vr1, $vr2 -+vaddwev.w.h $vr0, $vr1, $vr2 -+vaddwev.d.w $vr0, $vr1, $vr2 -+vaddwev.q.d $vr0, $vr1, $vr2 -+vaddwev.h.bu $vr0, $vr1, $vr2 -+vaddwev.w.hu $vr0, $vr1, $vr2 -+vaddwev.d.wu $vr0, $vr1, $vr2 -+vaddwev.q.du $vr0, $vr1, $vr2 -+vaddwev.h.bu.b $vr0, $vr1, $vr2 -+vaddwev.w.hu.h $vr0, $vr1, $vr2 -+vaddwev.d.wu.w $vr0, $vr1, $vr2 -+vaddwev.q.du.d $vr0, $vr1, $vr2 -+vaddwod.h.b $vr0, $vr1, $vr2 -+vaddwod.w.h $vr0, $vr1, $vr2 -+vaddwod.d.w $vr0, $vr1, $vr2 -+vaddwod.q.d $vr0, $vr1, $vr2 -+vaddwod.h.bu $vr0, $vr1, $vr2 -+vaddwod.w.hu $vr0, $vr1, $vr2 -+vaddwod.d.wu $vr0, $vr1, $vr2 -+vaddwod.q.du $vr0, $vr1, $vr2 -+vaddwod.h.bu.b $vr0, $vr1, $vr2 -+vaddwod.w.hu.h $vr0, $vr1, $vr2 -+vaddwod.d.wu.w $vr0, $vr1, $vr2 -+vaddwod.q.du.d $vr0, $vr1, $vr2 -+vmaddwev.h.b $vr0, $vr1, $vr2 -+vmaddwev.w.h $vr0, $vr1, $vr2 -+vmaddwev.d.w $vr0, $vr1, $vr2 -+vmaddwev.q.d $vr0, $vr1, $vr2 -+vmaddwev.h.bu $vr0, $vr1, $vr2 -+vmaddwev.w.hu $vr0, $vr1, $vr2 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-+vmulwod.h.b $vr0, $vr1, $vr2 -+vmulwod.w.h $vr0, $vr1, $vr2 -+vmulwod.d.w $vr0, $vr1, $vr2 -+vmulwod.q.d $vr0, $vr1, $vr2 -+vmulwod.h.bu $vr0, $vr1, $vr2 -+vmulwod.w.hu $vr0, $vr1, $vr2 -+vmulwod.d.wu $vr0, $vr1, $vr2 -+vmulwod.q.du $vr0, $vr1, $vr2 -+vmulwod.h.bu.b $vr0, $vr1, $vr2 -+vmulwod.w.hu.h $vr0, $vr1, $vr2 -+vmulwod.d.wu.w $vr0, $vr1, $vr2 -+vmulwod.q.du.d $vr0, $vr1, $vr2 -+vsubwev.h.b $vr0, $vr1, $vr2 -+vsubwev.w.h $vr0, $vr1, $vr2 -+vsubwev.d.w $vr0, $vr1, $vr2 -+vsubwev.q.d $vr0, $vr1, $vr2 -+vsubwev.h.bu $vr0, $vr1, $vr2 -+vsubwev.w.hu $vr0, $vr1, $vr2 -+vsubwev.d.wu $vr0, $vr1, $vr2 -+vsubwev.q.du $vr0, $vr1, $vr2 -+vsubwod.h.b $vr0, $vr1, $vr2 -+vsubwod.w.h $vr0, $vr1, $vr2 -+vsubwod.d.w $vr0, $vr1, $vr2 -+vsubwod.q.d $vr0, $vr1, $vr2 -+vsubwod.h.bu $vr0, $vr1, $vr2 -+vsubwod.w.hu $vr0, $vr1, $vr2 -+vsubwod.d.wu $vr0, $vr1, $vr2 -+vsubwod.q.du $vr0, $vr1, $vr2 -+vrepli.d $vr0, 1 -+vrepli.h $vr0, 1 -+vrepli.w $vr0, 1 -+vldi $vr0, 1 -+vpermi.w $vr0, $vr1, 1 -+vext2xv.h.b $xr0, $xr1 -+vext2xv.w.b $xr0, $xr1 -+vext2xv.d.b $xr0, $xr1 -+vext2xv.w.h $xr0, $xr1 -+vext2xv.d.h $xr0, $xr1 -+vext2xv.d.w $xr0, $xr1 -+vext2xv.hu.bu $xr0, $xr1 -+vext2xv.wu.bu $xr0, $xr1 -+vext2xv.du.bu $xr0, $xr1 -+vext2xv.wu.hu $xr0, $xr1 -+vext2xv.du.hu $xr0, $xr1 -+vext2xv.du.wu $xr0, $xr1 -+vfrecipe.s $vr0, $vr1 -+vfrecipe.d $vr0, $vr1 -+vfrsqrte.s $vr0, $vr1 -+vfrsqrte.d $vr0, $vr1 --- -2.33.0 - diff --git a/LoongArch-Add-mignore-start-align-option.patch b/LoongArch-Add-mignore-start-align-option.patch deleted file mode 100644 index fbd615c..0000000 --- a/LoongArch-Add-mignore-start-align-option.patch +++ /dev/null @@ -1,316 +0,0 @@ -From 5b5553b3a8d81b48b5b6829165173fe158c3fe8f Mon Sep 17 00:00:00 2001 -From: mengqinggang -Date: Sun, 7 Apr 2024 16:34:42 +0800 -Subject: [PATCH 080/123] LoongArch: Add -mignore-start-align option - -Ignore .align at the start of a section may result in misalignment when -partial linking. Manually add -mignore-start-align option without partial -linking. - -Gcc -falign-functions add .align 5 to the start of a section, it causes some -error message mismatch. Set these testcases to xfail on LoongArch target. ---- - gas/config/tc-loongarch.c | 70 +++++++++++++------ - ...ign-first.d => relax-align-ignore-start.d} | 2 +- - ...ign-first.s => relax-align-ignore-start.s} | 0 - include/opcode/loongarch.h | 1 + - ld/testsuite/ld-elf/dwarf.exp | 5 ++ - .../ld-loongarch-elf/partial-link-align-a.s | 2 + - .../ld-loongarch-elf/partial-link-align-b.s | 3 + - ...ign-first.d => relax-align-ignore-start.d} | 1 + - ...ign-first.s => relax-align-ignore-start.s} | 0 - ld/testsuite/ld-loongarch-elf/relax.exp | 32 ++++++++- - ld/testsuite/ld-undefined/undefined.exp | 2 + - 11 files changed, 95 insertions(+), 23 deletions(-) - rename gas/testsuite/gas/loongarch/{relax-align-first.d => relax-align-ignore-start.d} (87%) - rename gas/testsuite/gas/loongarch/{relax-align-first.s => relax-align-ignore-start.s} (100%) - create mode 100644 ld/testsuite/ld-loongarch-elf/partial-link-align-a.s - create mode 100644 ld/testsuite/ld-loongarch-elf/partial-link-align-b.s - rename ld/testsuite/ld-loongarch-elf/{relax-align-first.d => relax-align-ignore-start.d} (92%) - rename ld/testsuite/ld-loongarch-elf/{relax-align-first.s => relax-align-ignore-start.s} (100%) - -diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c -index 110b92e4..f030fd07 100644 ---- a/gas/config/tc-loongarch.c -+++ b/gas/config/tc-loongarch.c -@@ -139,15 +139,17 @@ enum options - - OPTION_ABI, - OPTION_FLOAT_ABI, -- - OPTION_FLOAT_ISA, - - OPTION_LA_LOCAL_WITH_ABS, - OPTION_LA_GLOBAL_WITH_PCREL, - OPTION_LA_GLOBAL_WITH_ABS, -+ - OPTION_RELAX, - OPTION_NO_RELAX, -+ - OPTION_THIN_ADD_SUB, -+ OPTION_IGNORE_START_ALIGN, - - OPTION_END_OF_ENUM, - }; -@@ -165,6 +167,7 @@ struct option md_longopts[] = - { "mrelax", no_argument, NULL, OPTION_RELAX }, - { "mno-relax", no_argument, NULL, OPTION_NO_RELAX }, - { "mthin-add-sub", no_argument, NULL, OPTION_THIN_ADD_SUB}, -+ { "mignore-start-align", no_argument, NULL, OPTION_IGNORE_START_ALIGN}, - - { NULL, no_argument, NULL, 0 } - }; -@@ -247,6 +250,10 @@ md_parse_option (int c, const char *arg) - LARCH_opts.thin_add_sub = 1; - break; - -+ case OPTION_IGNORE_START_ALIGN: -+ LARCH_opts.ignore_start_align = 1; -+ break; -+ - case OPTION_IGNORE: - break; - -@@ -1772,7 +1779,9 @@ md_show_usage (FILE *stream) - -mthin-add-sub Convert a pair of R_LARCH_ADD32/64 and R_LARCH_SUB32/64 to\n\ - R_LARCH_32/64_PCREL as much as possible\n\ - The option does not affect the generation of R_LARCH_32_PCREL\n\ -- relocations in .eh_frame\n")); -+ relocations in .eh_frame\n\ -+ -mignore-start-align Ignore .align if it is at the start of a section. This option\n\ -+ can't be used when partial linking (ld -r).\n")); - } - - static void -@@ -1794,39 +1803,60 @@ bool - loongarch_frag_align_code (int n, int max) - { - char *nops; -+ expressionS ex; - symbolS *s = NULL; - -- bfd_vma insn_alignment = 4; -- bfd_vma bytes = (bfd_vma) 1 << n; -- bfd_vma worst_case_bytes = bytes - insn_alignment; -+ /* When not relaxing, loongarch_handle_align handles code alignment. */ -+ if (!LARCH_opts.relax) -+ return false; -+ -+ bfd_vma align_bytes = (bfd_vma) 1 << n; -+ bfd_vma worst_case_bytes = align_bytes - 4; -+ bfd_vma addend = worst_case_bytes; -+ bool align_max = max > 0 && (bfd_vma) max < worst_case_bytes; - - /* If we are moving to a smaller alignment than the instruction size, then no - alignment is required. */ -- if (bytes <= insn_alignment) -+ if (align_bytes <= 4) - return true; - -- /* When not relaxing, loongarch_handle_align handles code alignment. */ -- if (!LARCH_opts.relax) -- return false; -- - /* If max <= 0, ignore max. - If max >= worst_case_bytes, max has no effect. - Similar to gas/write.c relax_segment function rs_align_code case: - if (fragP->fr_subtype != 0 && offset > fragP->fr_subtype). */ -- if (max > 0 && (bfd_vma) max < worst_case_bytes) -+ if (align_max) - { - s = symbol_find (now_seg->name); -- worst_case_bytes = ALIGN_MAX_ADDEND (n, max); -+ addend = ALIGN_MAX_ADDEND (n, max); -+ } -+ -+ if (LARCH_opts.ignore_start_align) -+ { -+ frag_grow (worst_case_bytes); -+ /* Use relaxable frag for .align. -+ If .align at the start of section, do nothing. Section alignment can -+ ensure correct alignment. -+ If .align is not at the start of a section, reserve NOP instructions -+ and R_LARCH_ALIGN relocation. */ -+ nops = frag_var (rs_machine_dependent, worst_case_bytes, worst_case_bytes, -+ rs_align_code, s, addend, NULL); - } -+ else -+ { -+ nops = frag_more (worst_case_bytes); -+ if (align_max) -+ { -+ ex.X_add_symbol = s; -+ ex.X_op = O_symbol; -+ } -+ else -+ ex.X_op = O_constant; -+ -+ ex.X_add_number = addend; - -- frag_grow (worst_case_bytes); -- /* Use relaxable frag for .align. -- If .align at the start of section, do nothing. Section alignment can -- ensure correct alignment. -- If .align is not at the start of a section, reserve NOP instructions -- and R_LARCH_ALIGN relocation. */ -- nops = frag_var (rs_machine_dependent, worst_case_bytes, worst_case_bytes, -- rs_align_code, s, worst_case_bytes, NULL); -+ fix_new_exp (frag_now, nops - frag_now->fr_literal, 0, -+ &ex, false, BFD_RELOC_LARCH_ALIGN); -+ } - - /* Default write NOP for aligned bytes. */ - loongarch_make_nops (nops, worst_case_bytes); -diff --git a/gas/testsuite/gas/loongarch/relax-align-first.d b/gas/testsuite/gas/loongarch/relax-align-ignore-start.d -similarity index 87% -rename from gas/testsuite/gas/loongarch/relax-align-first.d -rename to gas/testsuite/gas/loongarch/relax-align-ignore-start.d -index ec0698b6..0a67392d 100644 ---- a/gas/testsuite/gas/loongarch/relax-align-first.d -+++ b/gas/testsuite/gas/loongarch/relax-align-ignore-start.d -@@ -1,4 +1,4 @@ --#as: -+#as: -mignore-start-align - #objdump: -dr - - .*:[ ]+file format .* -diff --git a/gas/testsuite/gas/loongarch/relax-align-first.s b/gas/testsuite/gas/loongarch/relax-align-ignore-start.s -similarity index 100% -rename from gas/testsuite/gas/loongarch/relax-align-first.s -rename to gas/testsuite/gas/loongarch/relax-align-ignore-start.s -diff --git a/include/opcode/loongarch.h b/include/opcode/loongarch.h -index 5fc6e190..024ba99c 100644 ---- a/include/opcode/loongarch.h -+++ b/include/opcode/loongarch.h -@@ -256,6 +256,7 @@ dec2 : [1-9][0-9]? - - int relax; - int thin_add_sub; -+ int ignore_start_align; - } LARCH_opts; - - extern size_t loongarch_insn_length (insn_t insn); -diff --git a/ld/testsuite/ld-elf/dwarf.exp b/ld/testsuite/ld-elf/dwarf.exp -index 3d1b99ac..5cb2aab9 100644 ---- a/ld/testsuite/ld-elf/dwarf.exp -+++ b/ld/testsuite/ld-elf/dwarf.exp -@@ -52,6 +52,9 @@ set build_tests { - {"DWARF parse during linker error" - "" "-fno-toplevel-reorder" - {dwarf2a.c dwarf2b.c} {{error_output "dwarf2.err"}} "dwarf2.x"} -+} -+ -+set build_tests_dwarf3 { - {"Handle no DWARF information" - "" "-g0" - {dwarf3.c} {{error_output "dwarf3.err"}} "dwarf3.x"} -@@ -72,6 +75,8 @@ set run_tests { - set old_CFLAGS "$CFLAGS_FOR_TARGET" - append CFLAGS_FOR_TARGET " $NOSANITIZE_CFLAGS" - run_cc_link_tests $build_tests -+setup_xfail loongarch*-*-* -+run_cc_link_tests $build_tests_dwarf3 - run_ld_link_exec_tests $run_tests - set CFLAGS_FOR_TARGET "$old_CFLAGS" - -diff --git a/ld/testsuite/ld-loongarch-elf/partial-link-align-a.s b/ld/testsuite/ld-loongarch-elf/partial-link-align-a.s -new file mode 100644 -index 00000000..a8b4f295 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/partial-link-align-a.s -@@ -0,0 +1,2 @@ -+.text -+la.local $t0, .text -diff --git a/ld/testsuite/ld-loongarch-elf/partial-link-align-b.s b/ld/testsuite/ld-loongarch-elf/partial-link-align-b.s -new file mode 100644 -index 00000000..46fa058b ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/partial-link-align-b.s -@@ -0,0 +1,3 @@ -+.text -+.align 4 -+ret -diff --git a/ld/testsuite/ld-loongarch-elf/relax-align-first.d b/ld/testsuite/ld-loongarch-elf/relax-align-ignore-start.d -similarity index 92% -rename from ld/testsuite/ld-loongarch-elf/relax-align-first.d -rename to ld/testsuite/ld-loongarch-elf/relax-align-ignore-start.d -index 9a4fad8e..939cf427 100644 ---- a/ld/testsuite/ld-loongarch-elf/relax-align-first.d -+++ b/ld/testsuite/ld-loongarch-elf/relax-align-ignore-start.d -@@ -1,3 +1,4 @@ -+#as: -mignore-start-align - #ld: -e0 - #objdump: -d - -diff --git a/ld/testsuite/ld-loongarch-elf/relax-align-first.s b/ld/testsuite/ld-loongarch-elf/relax-align-ignore-start.s -similarity index 100% -rename from ld/testsuite/ld-loongarch-elf/relax-align-first.s -rename to ld/testsuite/ld-loongarch-elf/relax-align-ignore-start.s -diff --git a/ld/testsuite/ld-loongarch-elf/relax.exp b/ld/testsuite/ld-loongarch-elf/relax.exp -index 7274218f..bfd6d1c0 100644 ---- a/ld/testsuite/ld-loongarch-elf/relax.exp -+++ b/ld/testsuite/ld-loongarch-elf/relax.exp -@@ -19,10 +19,38 @@ - # MA 02110-1301, USA. - # - --if [istarget loongarch64-*-*] { -- run_dump_test "relax-align-first" -+proc run_partial_linking_align_test {} { -+ global as -+ global ld -+ global srcdir -+ global subdir -+ global runtests -+ -+ set testname "partial-link-align" -+ if ![runtest_file_p $runtests $testname] then { -+ return -+ } - -+ if { ![ld_assemble $as "$srcdir/$subdir/$testname-a.s" tmpdir/a.o] -+ || ![ld_assemble $as "$srcdir/$subdir/$testname-b.s" tmpdir/b.o] -+ || ![ld_link $ld tmpdir/$testname.os "tmpdir/a.o tmpdir/b.o -r"] -+ || ![ld_link $ld tmpdir/$testname "tmpdir/$testname.os -e0 -Ttext 0x1000"] } { -+ fail $testname -+ } else { -+ set objdump_output [run_host_cmd "objdump" "-d tmpdir/$testname"] -+ if { [ regexp ".*1010:\\s*4c000020\\s*jirl.*" $objdump_output ] } { -+ pass $testname -+ } else { -+ fail $testname -+ } -+ } -+} -+ -+if [istarget loongarch64-*-*] { - if [isbuild loongarch64-*-*] { -+ run_dump_test "relax-align-ignore-start" -+ run_partial_linking_align_test -+ - set testname "loongarch relax .exe build" - set pre_builds [list \ - [list \ -diff --git a/ld/testsuite/ld-undefined/undefined.exp b/ld/testsuite/ld-undefined/undefined.exp -index c0479a22..97bdd92d 100644 ---- a/ld/testsuite/ld-undefined/undefined.exp -+++ b/ld/testsuite/ld-undefined/undefined.exp -@@ -74,6 +74,7 @@ if { ![check_compiler_available] } { - # in a literal pool outside the function, so that both the - # "undefined function" and "undefined line" tests fail. - setup_xfail xtensa*-*-linux* -+ setup_xfail loongarch*-*-* - - set mf "tmpdir/undefined.o* in function `function':" - checkund $mf $testfn -@@ -154,6 +155,7 @@ if { ![check_compiler_available] } { - - # eBPF doesn't support dwarf yet. - setup_xfail bpf-*-* -+ setup_xfail loongarch*-*-* - - checkund $ml $testline - } --- -2.33.0 - diff --git a/LoongArch-Add-more-relaxation-support-for-call36.patch b/LoongArch-Add-more-relaxation-support-for-call36.patch deleted file mode 100644 index 7e03187..0000000 --- a/LoongArch-Add-more-relaxation-support-for-call36.patch +++ /dev/null @@ -1,266 +0,0 @@ -From 0638980f66ece88b89b96746aba82c1f5cd6d6eb Mon Sep 17 00:00:00 2001 -From: mengqinggang -Date: Thu, 10 Oct 2024 16:23:30 +0800 -Subject: [PATCH 117/123] LoongArch: Add more relaxation support for call36 - -Add relaxation support for call36 that jump to PLT entry. - -Add relaxation support for call36 with IFUNC symbol. - -Add relaxation support for call36 that jump to undefweak symbol. -For undefweak symbol, it can always be relaxed if it have no PLT entry. -Because we set the address of undefweak symbol without PLT entry to PC -like relocate_section. ---- - bfd/elfnn-loongarch.c | 21 +++- - .../ld-loongarch-elf/relax-call36-exe.s | 32 ++++++ - .../ld-loongarch-elf/relax-call36-so.s | 35 ++++++ - ld/testsuite/ld-loongarch-elf/relax.exp | 105 ++++++++++++++++++ - 4 files changed, 190 insertions(+), 3 deletions(-) - create mode 100644 ld/testsuite/ld-loongarch-elf/relax-call36-exe.s - create mode 100644 ld/testsuite/ld-loongarch-elf/relax-call36-so.s - -diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c -index 70522fae..890233d1 100644 ---- a/bfd/elfnn-loongarch.c -+++ b/bfd/elfnn-loongarch.c -@@ -5434,7 +5434,8 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, - Elf_Internal_Sym *sym = (Elf_Internal_Sym *)symtab_hdr->contents - + r_symndx; - -- if (ELF_ST_TYPE (sym->st_info) == STT_GNU_IFUNC) -+ if (ELF_ST_TYPE (sym->st_info) == STT_GNU_IFUNC -+ && r_type != R_LARCH_CALL36) - continue; - - /* Only TLS instruction sequences that are accompanied by -@@ -5467,8 +5468,8 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, - } - else - { -- /* Disable the relaxation for ifunc. */ -- if (h != NULL && h->type == STT_GNU_IFUNC) -+ if (h != NULL && h->type == STT_GNU_IFUNC -+ && r_type != R_LARCH_CALL36) - continue; - - /* The GOT entry of tls symbols must in current execute file or -@@ -5485,6 +5486,20 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, - && GOT_TLS_GD_BOTH_P (tls_type)) - symval += 2 * GOT_ENTRY_SIZE; - } -+ else if (h->plt.offset != MINUS_ONE) -+ { -+ sym_sec = htab->elf.splt ? htab->elf.splt : htab->elf.iplt; -+ symval = h->plt.offset; -+ } -+ /* Like loongarch_elf_relocate_section, set relocation(offset) to 0. -+ Undefweak for other relocations handing in the future. */ -+ else if (h->root.type == bfd_link_hash_undefweak -+ && !h->root.linker_def -+ && r_type == R_LARCH_CALL36) -+ { -+ sym_sec = sec; -+ symval = rel->r_offset; -+ } - else if ((h->root.type == bfd_link_hash_defined - || h->root.type == bfd_link_hash_defweak) - && h->root.u.def.section != NULL -diff --git a/ld/testsuite/ld-loongarch-elf/relax-call36-exe.s b/ld/testsuite/ld-loongarch-elf/relax-call36-exe.s -new file mode 100644 -index 00000000..26cff4df ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/relax-call36-exe.s -@@ -0,0 +1,32 @@ -+ldd: # local define default -+call36 ldd # ldd -+ -+ldh: # local define hidden -+.hidden ldh -+call36 ldh # ldh -+ -+gdd: -+.global gdd # global define default -+call36 gdd # gdd@plt -+ -+gdh: -+.global gdh # global define hidden -+.hidden gdh -+call36 gdh # gdh -+ -+wdd: -+.weak wdd # weak define default -+call36 wdd # wdd@plt -+ -+.weak wud # weak undefine default -+call36 wud # wud@plt -+ -+wdh: -+.weak wdh # weak define hidden -+.hidden wdh -+call36 wdh # wdh -+ -+.weak wuh # weak undefine hidden -+.hidden wuh -+call36 wuh # wuh -+ -diff --git a/ld/testsuite/ld-loongarch-elf/relax-call36-so.s b/ld/testsuite/ld-loongarch-elf/relax-call36-so.s -new file mode 100644 -index 00000000..050273b0 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/relax-call36-so.s -@@ -0,0 +1,35 @@ -+ldd: # local define default -+call36 ldd # ldd -+ -+ldh: # local define hidden -+.hidden ldh -+call36 ldh # ldh -+ -+gdd: -+.global gdd # global define default -+call36 gdd # gdd@plt -+ -+.global gud # global undefine default -+call36 gud # gud@plt -+ -+gdh: -+.global gdh # global define hidden -+.hidden gdh -+call36 gdh # gdh -+ -+wdd: -+.weak wdd # weak define default -+call36 wdd # wdd@plt -+ -+.weak wud # weak undefine default -+call36 wud # wud@plt -+ -+wdh: -+.weak wdh # weak define hidden -+.hidden wdh -+call36 wdh # wdh -+ -+.weak wuh # weak undefine hidden -+.hidden wuh -+call36 wuh # wuh -+ -diff --git a/ld/testsuite/ld-loongarch-elf/relax.exp b/ld/testsuite/ld-loongarch-elf/relax.exp -index 05b268f4..57ea3877 100644 ---- a/ld/testsuite/ld-loongarch-elf/relax.exp -+++ b/ld/testsuite/ld-loongarch-elf/relax.exp -@@ -51,6 +51,111 @@ if [istarget loongarch64-*-*] { - run_dump_test "relax-align-ignore-start" - run_partial_linking_align_test - -+ run_ld_link_tests \ -+ [list \ -+ [list \ -+ "loongarch relax call36 .so build" \ -+ "-shared" "" \ -+ "" \ -+ {relax-call36-so.s} \ -+ {} \ -+ "relax-call36.so" \ -+ ] \ -+ ] -+ -+ if [file exist "tmpdir/relax-call36.so"] { -+ set objdump_output [run_host_cmd "objdump" "-d tmpdir/relax-call36.so"] -+ if { [ regexp "pcaddu18i" $objdump_output] } { -+ fail "loongarch relax call36 so" -+ } { -+ pass "loongarch relax call36 so" -+ } -+ } -+ -+ run_ld_link_tests \ -+ [list \ -+ [list \ -+ "loongarch relax call36 dyn exe build" \ -+ "-pie -e 0" "" \ -+ "" \ -+ {relax-call36-exe.s} \ -+ {} \ -+ "relax-call36-d.exe" \ -+ ] \ -+ ] -+ -+ if [file exist "tmpdir/relax-call36-d.exe"] { -+ set objdump_output [run_host_cmd "objdump" "-d tmpdir/relax-call36-d.exe"] -+ if { [ regexp "pcaddu18i" $objdump_output] } { -+ fail "loongarch relax call36 dyn exe" -+ } { -+ pass "loongarch relax call36 dyn exe" -+ } -+ } -+ -+ run_ld_link_tests \ -+ [list \ -+ [list \ -+ "loongarch relax call36 dyn-pie exe build" \ -+ "-pie -e 0" "" \ -+ "" \ -+ {relax-call36-exe.s} \ -+ {} \ -+ "relax-call36-dp.exe" \ -+ ] \ -+ ] -+ -+ if [file exist "tmpdir/relax-call36-dp.exe"] { -+ set objdump_output [run_host_cmd "objdump" "-d tmpdir/relax-call36-dp.exe"] -+ if { [ regexp "pcaddu18i" $objdump_output] } { -+ fail "loongarch relax call36 dyn-pie exe" -+ } { -+ pass "loongarch relax call36 dyn-pie exe" -+ } -+ } -+ -+ run_ld_link_tests \ -+ [list \ -+ [list \ -+ "loongarch relax call36 static exe build" \ -+ "-static -e 0" "" \ -+ "" \ -+ {relax-call36-exe.s} \ -+ {} \ -+ "relax-call36-s.exe" \ -+ ] \ -+ ] -+ -+ if [file exist "tmpdir/relax-call36-s.exe"] { -+ set objdump_output [run_host_cmd "objdump" "-d tmpdir/relax-call36-s.exe"] -+ if { [ regexp "pcaddu18i" $objdump_output] } { -+ fail "loongarch relax call36 static exe" -+ } { -+ pass "loongarch relax call36 static exe" -+ } -+ } -+ -+ run_ld_link_tests \ -+ [list \ -+ [list \ -+ "loongarch relax call36 static-pie exe build" \ -+ "-static -pie --no-dynamic-linker -e 0" "" \ -+ "" \ -+ {relax-call36-exe.s} \ -+ {} \ -+ "relax-call36-sp.exe" \ -+ ] \ -+ ] -+ -+ if [file exist "tmpdir/relax-call36-sp.exe"] { -+ set objdump_output [run_host_cmd "objdump" "-d tmpdir/relax-call36-sp.exe"] -+ if { [ regexp "pcaddu18i" $objdump_output] } { -+ fail "loongarch relax call36 static-pie exe" -+ } { -+ pass "loongarch relax call36 static-pie exe" -+ } -+ } -+ - run_ld_link_tests \ - [list \ - [list \ --- -2.33.0 - diff --git a/LoongArch-Add-more-relaxation-testcases.patch b/LoongArch-Add-more-relaxation-testcases.patch deleted file mode 100644 index 573b09f..0000000 --- a/LoongArch-Add-more-relaxation-testcases.patch +++ /dev/null @@ -1,182 +0,0 @@ -From 580a53dab47c9e4f97c8559440d2bc43fb7331b6 Mon Sep 17 00:00:00 2001 -From: mengqinggang -Date: Thu, 16 Nov 2023 19:19:16 +0800 -Subject: [PATCH] LoongArch: Add more relaxation testcases - -1. .so relaxation testcase -2. ld --no-relax testcase -3. segment alignment testcase - -Signed-off-by: Peng Fan ---- - .../ld-loongarch-elf/relax-segment-max.s | 12 +++ - .../ld-loongarch-elf/relax-segment-min.s | 12 +++ - ld/testsuite/ld-loongarch-elf/relax-so.s | 4 + - ld/testsuite/ld-loongarch-elf/relax.exp | 80 +++++++++++++++++-- - 4 files changed, 103 insertions(+), 5 deletions(-) - create mode 100644 ld/testsuite/ld-loongarch-elf/relax-segment-max.s - create mode 100644 ld/testsuite/ld-loongarch-elf/relax-segment-min.s - create mode 100644 ld/testsuite/ld-loongarch-elf/relax-so.s - -diff --git a/ld/testsuite/ld-loongarch-elf/relax-segment-max.s b/ld/testsuite/ld-loongarch-elf/relax-segment-max.s -new file mode 100644 -index 00000000000..df15d4cab09 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/relax-segment-max.s -@@ -0,0 +1,12 @@ -+# The .align may cause overflow because deleting nops. -+ .text # 0x120004000 -+ .align 3 -+ la.local $r12, .L1 -+ -+# .fill 0x1f7ffc # max fill without overflow, .data address is 0x120200000 -+# .fill 0x1f8000 # min fill with overflow, .data address is 0x120204000 -+ .fill 0x1fbff4 # max fill with overflow, .data address is 0x120204000 -+ -+ .data -+.L1: -+ .byte 2 -diff --git a/ld/testsuite/ld-loongarch-elf/relax-segment-min.s b/ld/testsuite/ld-loongarch-elf/relax-segment-min.s -new file mode 100644 -index 00000000000..476b9fba78c ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/relax-segment-min.s -@@ -0,0 +1,12 @@ -+# The .align may cause overflow because deleting nops. -+ .text # 0x120004000 -+ .align 3 -+ la.local $r12, .L1 -+ -+# .fill 0x1f7ffc # max fill without overflow, .data address is 0x120200000 -+ .fill 0x1f8000 # min fill with overflow, .data address is 0x120204000 -+# .fill 0x1fbff4 # max fill with overflow, .data address is 0x120204000 -+ -+ .data -+.L1: -+ .byte 2 -diff --git a/ld/testsuite/ld-loongarch-elf/relax-so.s b/ld/testsuite/ld-loongarch-elf/relax-so.s -new file mode 100644 -index 00000000000..01a404a8b47 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/relax-so.s -@@ -0,0 +1,4 @@ -+.text -+.align 2 -+.L1: -+ la.local $r12, .L1 -diff --git a/ld/testsuite/ld-loongarch-elf/relax.exp b/ld/testsuite/ld-loongarch-elf/relax.exp -index 7ff876d7914..24d79ed5c20 100644 ---- a/ld/testsuite/ld-loongarch-elf/relax.exp -+++ b/ld/testsuite/ld-loongarch-elf/relax.exp -@@ -22,7 +22,7 @@ - if [istarget loongarch64-*-*] { - - if [isbuild loongarch64-*-*] { -- set testname "loongarch relax build" -+ set testname "loongarch relax .exe build" - set pre_builds [list \ - [list \ - "$testname" \ -@@ -39,17 +39,87 @@ if [istarget loongarch64-*-*] { - if [file exist "tmpdir/relax"] { - set objdump_output [run_host_cmd "objdump" "-d tmpdir/relax"] - if { [ regexp ".*pcaddi.*pcaddi.*" $objdump_output] } { -- pass "loongarch relax" -+ pass "loongarch relax .exe" - } { -- fail "loongarch relax" -+ fail "loongarch relax .exe" - } - } -+ -+ set testname "loongarch ld --no-relax build" -+ set pre_builds [list \ -+ [list \ -+ "$testname" \ -+ "-Wl,--no-relax" \ -+ "" \ -+ {relax.s} \ -+ {} \ -+ "norelax" \ -+ ] \ -+ ] -+ -+ run_cc_link_tests $pre_builds -+ -+ if [file exist "tmpdir/norelax"] { -+ set objdump_output [run_host_cmd "objdump" "-d tmpdir/norelax"] -+ if { [ regexp ".*pcaddi.*" $objdump_output] } { -+ fail "loongarch ld --no-relax" -+ } { -+ pass "loongarch ld --no-relax" -+ } -+ } -+ -+ run_ld_link_tests \ -+ [list \ -+ [list \ -+ "loongarch relax .so build" \ -+ "-shared -e 0x0" "" \ -+ "" \ -+ {relax-so.s} \ -+ {} \ -+ "relax-so" \ -+ ] \ -+ ] -+ -+ if [file exist "tmpdir/relax-so"] { -+ set objdump_output [run_host_cmd "objdump" "-d tmpdir/relax-so"] -+ if { [ regexp ".*pcaddi.*" $objdump_output] } { -+ pass "loongarch relax .so" -+ } { -+ fail "loongarch relax .so" -+ } -+ } -+ -+ # If symbol in data segment, offset need to sub segment align to prevent -+ # overflow. -+ run_ld_link_tests \ -+ [list \ -+ [list \ -+ "loongarch relax segment alignment min" \ -+ "-e0 -Ttext 0x120004000 -pie -z relro" "" \ -+ "" \ -+ {relax-segment-min.s} \ -+ {} \ -+ "relax-segment-min" \ -+ ] \ -+ ] -+ -+ run_ld_link_tests \ -+ [list \ -+ [list \ -+ "loongarch relax segment alignment max" \ -+ "-e0 -Ttext 0x120004000 -pie -z relro" "" \ -+ "" \ -+ {relax-segment-max.s} \ -+ {} \ -+ "relax-segment-max" \ -+ ] \ -+ ] - } - - run_ld_link_tests \ - [list \ - [list \ -- "relax-align" \ -+ "loongarch relax-align" \ - "-e 0x0 -z relro" "" \ - "" \ - {relax-align.s} \ -@@ -64,7 +134,7 @@ if [istarget loongarch64-*-*] { - run_ld_link_tests \ - [list \ - [list \ -- "uleb128" \ -+ "loongarch uleb128" \ - "-e 0x0" "" \ - "" \ - {uleb128.s} \ --- -2.33.0 - diff --git a/LoongArch-Add-new-relocation-R_LARCH_CALL36.patch b/LoongArch-Add-new-relocation-R_LARCH_CALL36.patch deleted file mode 100644 index 1731ae2..0000000 --- a/LoongArch-Add-new-relocation-R_LARCH_CALL36.patch +++ /dev/null @@ -1,278 +0,0 @@ -From 27daffe58e9d1494a1e3c66813526ec4e8e8480b Mon Sep 17 00:00:00 2001 -From: mengqinggang -Date: Thu, 28 Sep 2023 16:41:15 +0800 -Subject: [PATCH 020/123] LoongArch: Add new relocation R_LARCH_CALL36 - -R_LARCH_CALL36 is used for medium code model function call pcaddu18i+jirl, and -these two instructions must adjacent. - -The LoongArch ABI v2.20 at here: https://github.com/loongson/la-abi-specs. ---- - bfd/bfd-in2.h | 4 +++- - bfd/elfnn-loongarch.c | 19 ++++++++++----- - bfd/elfxx-loongarch.c | 24 +++++++++++++++++++ - bfd/libbfd.h | 1 + - bfd/reloc.c | 3 +++ - gas/config/tc-loongarch.c | 6 ++++- - gas/testsuite/gas/loongarch/medium-call.d | 15 ++++++++++++ - gas/testsuite/gas/loongarch/medium-call.s | 6 +++++ - include/elf/loongarch.h | 2 ++ - .../ld-loongarch-elf/ld-loongarch-elf.exp | 12 ++++++++++ - ld/testsuite/ld-loongarch-elf/medium-call.s | 7 ++++++ - 11 files changed, 91 insertions(+), 8 deletions(-) - create mode 100644 gas/testsuite/gas/loongarch/medium-call.d - create mode 100644 gas/testsuite/gas/loongarch/medium-call.s - create mode 100644 ld/testsuite/ld-loongarch-elf/medium-call.s - -diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h -index 933b8ec2..86e7139f 100644 ---- a/bfd/bfd-in2.h -+++ b/bfd/bfd-in2.h -@@ -7343,7 +7343,9 @@ assembler and not (currently) written to any object files. */ - BFD_RELOC_LARCH_ADD_ULEB128, - BFD_RELOC_LARCH_SUB_ULEB128, - BFD_RELOC_LARCH_64_PCREL, -- BFD_RELOC_UNUSED }; -+ BFD_RELOC_LARCH_CALL36, -+ BFD_RELOC_UNUSED -+}; - typedef enum bfd_reloc_code_real bfd_reloc_code_real_type; - - reloc_howto_type *bfd_reloc_type_lookup -diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c -index 09c98713..20dd0640 100644 ---- a/bfd/elfnn-loongarch.c -+++ b/bfd/elfnn-loongarch.c -@@ -780,6 +780,7 @@ loongarch_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, - case R_LARCH_B16: - case R_LARCH_B21: - case R_LARCH_B26: -+ case R_LARCH_CALL36: - if (h != NULL) - { - h->needs_plt = 1; -@@ -1884,20 +1885,24 @@ loongarch_check_offset (const Elf_Internal_Rela *rel, - ret; \ - }) - -+/* Write immediate to instructions. */ -+ - static bfd_reloc_status_type - loongarch_reloc_rewrite_imm_insn (const Elf_Internal_Rela *rel, - const asection *input_section ATTRIBUTE_UNUSED, - reloc_howto_type *howto, bfd *input_bfd, - bfd_byte *contents, bfd_vma reloc_val) - { -- int bits = bfd_get_reloc_size (howto) * 8; -- uint32_t insn = bfd_get (bits, input_bfd, contents + rel->r_offset); -- -+ /* Adjust the immediate based on alignment and -+ its position in the instruction. */ - if (!loongarch_adjust_reloc_bitsfield (input_bfd, howto, &reloc_val)) - return bfd_reloc_overflow; - -- insn = (insn & (uint32_t)howto->src_mask) -- | ((insn & (~(uint32_t)howto->dst_mask)) | reloc_val); -+ int bits = bfd_get_reloc_size (howto) * 8; -+ uint64_t insn = bfd_get (bits, input_bfd, contents + rel->r_offset); -+ -+ /* Write immediate to instruction. */ -+ insn = (insn & ~howto->dst_mask) | (reloc_val & howto->dst_mask); - - bfd_put (bits, input_bfd, insn, contents + rel->r_offset); - -@@ -2120,6 +2125,7 @@ perform_relocation (const Elf_Internal_Rela *rel, asection *input_section, - case R_LARCH_TLS_GD_PC_HI20: - case R_LARCH_TLS_GD_HI20: - case R_LARCH_PCREL20_S2: -+ case R_LARCH_CALL36: - r = loongarch_check_offset (rel, input_section); - if (r != bfd_reloc_ok) - break; -@@ -3120,9 +3126,10 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, - break; - - /* New reloc types. */ -+ case R_LARCH_B16: - case R_LARCH_B21: - case R_LARCH_B26: -- case R_LARCH_B16: -+ case R_LARCH_CALL36: - unresolved_reloc = false; - if (is_undefweak) - { -diff --git a/bfd/elfxx-loongarch.c b/bfd/elfxx-loongarch.c -index 7f298c08..d93b7904 100644 ---- a/bfd/elfxx-loongarch.c -+++ b/bfd/elfxx-loongarch.c -@@ -1547,6 +1547,24 @@ static loongarch_reloc_howto_type loongarch_howto_table[] = - NULL, /* adjust_reloc_bits */ - NULL), /* larch_reloc_type_name */ - -+ /* Used for medium code model function call pcaddu18i+jirl, -+ these two instructions must adjacent. */ -+ LOONGARCH_HOWTO (R_LARCH_CALL36, /* type (110). */ -+ 2, /* rightshift. */ -+ 8, /* size. */ -+ 36, /* bitsize. */ -+ true, /* pc_relative. */ -+ 0, /* bitpos. */ -+ complain_overflow_signed, /* complain_on_overflow. */ -+ bfd_elf_generic_reloc, /* special_function. */ -+ "R_LARCH_CALL36", /* name. */ -+ false, /* partial_inplace. */ -+ 0, /* src_mask. */ -+ 0x03fffc0001ffffe0, /* dst_mask. */ -+ false, /* pcrel_offset. */ -+ BFD_RELOC_LARCH_CALL36, /* bfd_reloc_code_real_type. */ -+ reloc_sign_bits, /* adjust_reloc_bits. */ -+ "call36"), /* larch_reloc_type_name. */ - }; - - reloc_howto_type * -@@ -1726,6 +1744,12 @@ reloc_sign_bits (bfd *abfd, reloc_howto_type *howto, bfd_vma *fix_val) - /* Perform insn bits field. 15:0<<10, 20:16>>16. */ - val = ((val & 0xffff) << 10) | ((val >> 16) & 0x1f); - break; -+ case R_LARCH_CALL36: -+ /* 0x8000: If low 16-bit immediate greater than 0x7fff, -+ it become to a negative number due to sign-extended, -+ so the high part need to add 0x8000. */ -+ val = (((val + 0x8000) >> 16) << 5) | (((val & 0xffff) << 10) << 32); -+ break; - default: - val <<= howto->bitpos; - break; -diff --git a/bfd/libbfd.h b/bfd/libbfd.h -index d4fb3107..297f3048 100644 ---- a/bfd/libbfd.h -+++ b/bfd/libbfd.h -@@ -3525,6 +3525,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@", - "BFD_RELOC_LARCH_ADD_ULEB128", - "BFD_RELOC_LARCH_SUB_ULEB128", - "BFD_RELOC_LARCH_64_PCREL", -+ "BFD_RELOC_LARCH_CALL36", - "@@overflow: BFD_RELOC_UNUSED@@", - }; - #endif -diff --git a/bfd/reloc.c b/bfd/reloc.c -index fbc67ac7..70004f04 100644 ---- a/bfd/reloc.c -+++ b/bfd/reloc.c -@@ -8156,6 +8156,9 @@ ENUMX - ENUMX - BFD_RELOC_LARCH_64_PCREL - -+ENUMX -+ BFD_RELOC_LARCH_CALL36 -+ - ENUMDOC - LARCH relocations. - -diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c -index 59232832..367a0b6c 100644 ---- a/gas/config/tc-loongarch.c -+++ b/gas/config/tc-loongarch.c -@@ -682,7 +682,7 @@ loongarch_args_parser_can_match_arg_helper (char esc_ch1, char esc_ch2, - esc_ch1, esc_ch2, bit_field, arg); - - if (ip->reloc_info[0].type >= BFD_RELOC_LARCH_B16 -- && ip->reloc_info[0].type < BFD_RELOC_LARCH_64_PCREL) -+ && ip->reloc_info[0].type < BFD_RELOC_UNUSED) - { - /* As we compact stack-relocs, it is no need for pop operation. - But break out until here in order to check the imm field. -@@ -956,6 +956,10 @@ move_insn (struct loongarch_cl_insn *insn, fragS *frag, long where) - static void - append_fixed_insn (struct loongarch_cl_insn *insn) - { -+ /* Ensure the jirl is emitted to the same frag as the pcaddu18i. */ -+ if (BFD_RELOC_LARCH_CALL36 == insn->reloc_info[0].type) -+ frag_grow (8); -+ - char *f = frag_more (insn->insn_length); - move_insn (insn, frag_now, f - frag_now->fr_literal); - } -diff --git a/gas/testsuite/gas/loongarch/medium-call.d b/gas/testsuite/gas/loongarch/medium-call.d -new file mode 100644 -index 00000000..4183818c ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/medium-call.d -@@ -0,0 +1,15 @@ -+#as: -+#objdump: -dr -+ -+.*:[ ]+file format .* -+ -+ -+Disassembly of section .text: -+ -+.* <.text>: -+[ ]+0:[ ]+1e000001[ ]+pcaddu18i[ ]+\$ra, 0 -+[ ]+0: R_LARCH_CALL36[ ]+a -+[ ]+4:[ ]+4c000021[ ]+jirl[ ]+\$ra, \$ra, 0 -+[ ]+8:[ ]+1e00000c[ ]+pcaddu18i[ ]+\$t0, 0 -+[ ]+8: R_LARCH_CALL36[ ]+a -+[ ]+c:[ ]+4c000180[ ]+jr[ ]+\$t0 -diff --git a/gas/testsuite/gas/loongarch/medium-call.s b/gas/testsuite/gas/loongarch/medium-call.s -new file mode 100644 -index 00000000..f2977d1c ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/medium-call.s -@@ -0,0 +1,6 @@ -+ # call .L1, r1(ra) temp register, r1(ra) return register. -+ pcaddu18i $r1, %call36(a) -+ jirl $r1, $r1, 0 -+ # tail .L1, r12(t0) temp register, r0(zero) return register. -+ pcaddu18i $r12, %call36(a) -+ jirl $r0, $r12, 0 -diff --git a/include/elf/loongarch.h b/include/elf/loongarch.h -index e31395e1..34719ee8 100644 ---- a/include/elf/loongarch.h -+++ b/include/elf/loongarch.h -@@ -251,6 +251,8 @@ RELOC_NUMBER (R_LARCH_SUB_ULEB128, 108) - - RELOC_NUMBER (R_LARCH_64_PCREL, 109) - -+RELOC_NUMBER (R_LARCH_CALL36, 110) -+ - END_RELOC_NUMBERS (R_LARCH_count) - - /* Processor specific flags for the ELF header e_flags field. */ -diff --git a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -index b95cc53e..1fc70d0a 100644 ---- a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -+++ b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -@@ -55,4 +55,16 @@ if [istarget "loongarch64-*-*"] { - "64_pcrel" \ - ] \ - ] -+ -+ run_ld_link_tests \ -+ [list \ -+ [list \ -+ "medium code model call" \ -+ "-e 0x0" "" \ -+ "" \ -+ {medium-call.s} \ -+ {} \ -+ "medium-call" \ -+ ] \ -+ ] - } -diff --git a/ld/testsuite/ld-loongarch-elf/medium-call.s b/ld/testsuite/ld-loongarch-elf/medium-call.s -new file mode 100644 -index 00000000..4d1888b7 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/medium-call.s -@@ -0,0 +1,7 @@ -+.L1: -+ # call .L1, r1(ra) temp register, r1(ra) return register. -+ pcaddu18i $r1, %call36(.L1) -+ jirl $r1, $r1, 0 -+ # tail .L1, r12(t0) temp register, r0(zero) return register. -+ pcaddu18i $r12, %call36(.L1) -+ jirl $r0, $r12, 0 --- -2.33.0 - diff --git a/LoongArch-Add-new-relocs-and-macro-for-TLSDESC.patch b/LoongArch-Add-new-relocs-and-macro-for-TLSDESC.patch deleted file mode 100644 index 8a7754a..0000000 --- a/LoongArch-Add-new-relocs-and-macro-for-TLSDESC.patch +++ /dev/null @@ -1,510 +0,0 @@ -From a7cc512b2871a9ba63967eaa9f7b91f41baed858 Mon Sep 17 00:00:00 2001 -From: Lulu Cai -Date: Tue, 31 Oct 2023 16:11:29 +0800 -Subject: [PATCH 025/123] LoongArch: Add new relocs and macro for TLSDESC. - -The normal DESC instruction sequence is: - pcalau12i $a0,%desc_pc_hi20(var) #R_LARCH_TLS_DESC_PC_HI20 - addi.d $a0,$a0,%desc_pc_lo12(var) #R_LARCH_TLS_DESC_PC_LO12 - ld.d $ra,$a0,%desc_ld(var) #R_LARCH_TLS_DESC_LD - jirl $ra,$ra,%desc_call(var) #R_LARCH_TLS_DESC_CALL - add.d $a0,$a0,$tp ---- - bfd/bfd-in2.h | 12 +++ - bfd/elfxx-loongarch.c | 210 +++++++++++++++++++++++++++++++++++++- - bfd/libbfd.h | 12 +++ - bfd/reloc.c | 29 ++++++ - gas/config/tc-loongarch.c | 14 ++- - include/elf/loongarch.h | 22 +++- - opcodes/loongarch-opc.c | 54 ++++++++++ - 7 files changed, 349 insertions(+), 4 deletions(-) - -diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h -index 86e7139f..d210e71b 100644 ---- a/bfd/bfd-in2.h -+++ b/bfd/bfd-in2.h -@@ -7260,6 +7260,8 @@ assembler and not (currently) written to any object files. */ - BFD_RELOC_LARCH_TLS_DTPREL64, - BFD_RELOC_LARCH_TLS_TPREL32, - BFD_RELOC_LARCH_TLS_TPREL64, -+ BFD_RELOC_LARCH_TLS_DESC32, -+ BFD_RELOC_LARCH_TLS_DESC64, - BFD_RELOC_LARCH_MARK_LA, - BFD_RELOC_LARCH_MARK_PCREL, - BFD_RELOC_LARCH_SOP_PUSH_PCREL, -@@ -7344,6 +7346,16 @@ assembler and not (currently) written to any object files. */ - BFD_RELOC_LARCH_SUB_ULEB128, - BFD_RELOC_LARCH_64_PCREL, - BFD_RELOC_LARCH_CALL36, -+ BFD_RELOC_LARCH_TLS_DESC_PC_HI20, -+ BFD_RELOC_LARCH_TLS_DESC_PC_LO12, -+ BFD_RELOC_LARCH_TLS_DESC64_PC_LO20, -+ BFD_RELOC_LARCH_TLS_DESC64_PC_HI12, -+ BFD_RELOC_LARCH_TLS_DESC_HI20, -+ BFD_RELOC_LARCH_TLS_DESC_LO12, -+ BFD_RELOC_LARCH_TLS_DESC64_LO20, -+ BFD_RELOC_LARCH_TLS_DESC64_HI12, -+ BFD_RELOC_LARCH_TLS_DESC_LD, -+ BFD_RELOC_LARCH_TLS_DESC_CALL, - BFD_RELOC_UNUSED - }; - typedef enum bfd_reloc_code_real bfd_reloc_code_real_type; -diff --git a/bfd/elfxx-loongarch.c b/bfd/elfxx-loongarch.c -index 679b79f3..30a941a8 100644 ---- a/bfd/elfxx-loongarch.c -+++ b/bfd/elfxx-loongarch.c -@@ -293,8 +293,40 @@ static loongarch_reloc_howto_type loongarch_howto_table[] = - NULL, /* adjust_reloc_bits */ - NULL), /* larch_reloc_type_name */ - -- LOONGARCH_EMPTY_HOWTO (13), -- LOONGARCH_EMPTY_HOWTO (14), -+ LOONGARCH_HOWTO (R_LARCH_TLS_DESC32, /* type (13). */ -+ 0, /* rightshift. */ -+ 4, /* size. */ -+ 32, /* bitsize. */ -+ false, /* pc_relative. */ -+ 0, /* bitpos. */ -+ complain_overflow_dont, /* complain_on_overflow. */ -+ bfd_elf_generic_reloc, /* special_function. */ -+ "R_LARCH_TLS_DESC32", /* name. */ -+ false, /* partial_inplace. */ -+ 0, /* src_mask. */ -+ ALL_ONES, /* dst_mask. */ -+ false, /* pcrel_offset. */ -+ BFD_RELOC_LARCH_TLS_DESC32, /* bfd_reloc_code_real_type. */ -+ NULL, /* adjust_reloc_bits. */ -+ NULL), /* larch_reloc_type_name. */ -+ -+ LOONGARCH_HOWTO (R_LARCH_TLS_DESC64, /* type (14). */ -+ 0, /* rightshift. */ -+ 4, /* size. */ -+ 64, /* bitsize. */ -+ false, /* pc_relative. */ -+ 0, /* bitpos. */ -+ complain_overflow_dont, /* complain_on_overflow. */ -+ bfd_elf_generic_reloc, /* special_function. */ -+ "R_LARCH_TLS_DESC64", /* name. */ -+ false, /* partial_inplace. */ -+ 0, /* src_mask. */ -+ ALL_ONES, /* dst_mask. */ -+ false, /* pcrel_offset. */ -+ BFD_RELOC_LARCH_TLS_DESC64, /* bfd_reloc_code_real_type. */ -+ NULL, /* adjust_reloc_bits. */ -+ NULL), /* larch_reloc_type_name. */ -+ - LOONGARCH_EMPTY_HOWTO (15), - LOONGARCH_EMPTY_HOWTO (16), - LOONGARCH_EMPTY_HOWTO (17), -@@ -1569,6 +1601,180 @@ static loongarch_reloc_howto_type loongarch_howto_table[] = - BFD_RELOC_LARCH_CALL36, /* bfd_reloc_code_real_type. */ - reloc_sign_bits, /* adjust_reloc_bits. */ - "call36"), /* larch_reloc_type_name. */ -+ -+ /* TLS_DESC PCREL. */ -+ LOONGARCH_HOWTO (R_LARCH_TLS_DESC_PC_HI20, /* type (111). */ -+ 12, /* rightshift. */ -+ 4, /* size. */ -+ 20, /* bitsize. */ -+ true, /* pc_relative. */ -+ 5, /* bitpos. */ -+ complain_overflow_signed, /* complain_on_overflow. */ -+ bfd_elf_generic_reloc, /* special_function. */ -+ "R_LARCH_TLS_DESC_PC_HI20", /* name. */ -+ false, /* partial_inplace. */ -+ 0, /* src_mask. */ -+ 0x1ffffe0, /* dst_mask. */ -+ false, /* pcrel_offset. */ -+ BFD_RELOC_LARCH_TLS_DESC_PC_HI20, /* bfd_reloc_code_real_type. */ -+ reloc_bits, /* adjust_reloc_bits. */ -+ "desc_pc_hi20"), /* larch_reloc_type_name. */ -+ -+ LOONGARCH_HOWTO (R_LARCH_TLS_DESC_PC_LO12, /* type (112). */ -+ 0, /* rightshift. */ -+ 4, /* size. */ -+ 12, /* bitsize. */ -+ true, /* pc_relative. */ -+ 10, /* bitpos. */ -+ complain_overflow_signed, /* complain_on_overflow. */ -+ bfd_elf_generic_reloc, /* special_function. */ -+ "R_LARCH_TLS_DESC_PC_LO12", /* name. */ -+ false, /* partial_inplace. */ -+ 0, /* src_mask. */ -+ 0x3ffc00, /* dst_mask. */ -+ false, /* pcrel_offset. */ -+ BFD_RELOC_LARCH_TLS_DESC_PC_LO12, /* bfd_reloc_code_real_type. */ -+ reloc_bits, /* adjust_reloc_bits. */ -+ "desc_pc_lo12"), /* larch_reloc_type_name. */ -+ -+ /* TLS_DESC64 LARGE PCREL. */ -+ LOONGARCH_HOWTO (R_LARCH_TLS_DESC64_PC_LO20, /* type (113). */ -+ 32, /* rightshift. */ -+ 8, /* size. */ -+ 20, /* bitsize. */ -+ true, /* pc_relative. */ -+ 5, /* bitpos. */ -+ complain_overflow_signed, /* complain_on_overflow. */ -+ bfd_elf_generic_reloc, /* special_function. */ -+ "R_LARCH_TLS_DESC64_PC_LO20", /* name. */ -+ false, /* partial_inplace. */ -+ 0, /* src_mask. */ -+ 0x1ffffe0, /* dst_mask. */ -+ false, /* pcrel_offset. */ -+ BFD_RELOC_LARCH_TLS_DESC64_PC_LO20, /* bfd_reloc_code_real_type. */ -+ reloc_bits, /* adjust_reloc_bits. */ -+ "desc64_pc_lo20"), /* larch_reloc_type_name. */ -+ -+ LOONGARCH_HOWTO (R_LARCH_TLS_DESC64_PC_HI12, /* type (114). */ -+ 52, /* rightshift. */ -+ 8, /* size. */ -+ 12, /* bitsize. */ -+ true, /* pc_relative. */ -+ 10, /* bitpos. */ -+ complain_overflow_signed, /* complain_on_overflow. */ -+ bfd_elf_generic_reloc, /* special_function. */ -+ "R_LARCH_TLS_DESC64_PC_HI12", /* name. */ -+ false, /* partial_inplace. */ -+ 0, /* src_mask. */ -+ 0x3ffc00, /* dst_mask. */ -+ false, /* pcrel_offset. */ -+ BFD_RELOC_LARCH_TLS_DESC64_PC_HI12, /* bfd_reloc_code_real_type. */ -+ reloc_bits, /* adjust_reloc_bits. */ -+ "desc64_pc_hi12"), /* larch_reloc_type_name. */ -+ -+ /* TLS_DESC ABS. */ -+ LOONGARCH_HOWTO (R_LARCH_TLS_DESC_HI20, /* type (115). */ -+ 12, /* rightshift. */ -+ 4, /* size. */ -+ 20, /* bitsize. */ -+ false, /* pc_relative. */ -+ 5, /* bitpos. */ -+ complain_overflow_signed, /* complain_on_overflow. */ -+ bfd_elf_generic_reloc, /* special_function. */ -+ "R_LARCH_TLS_DESC_HI20", /* name. */ -+ false, /* partial_inplace. */ -+ 0, /* src_mask. */ -+ 0x1ffffe0, /* dst_mask. */ -+ false, /* pcrel_offset. */ -+ BFD_RELOC_LARCH_TLS_DESC_HI20, /* bfd_reloc_code_real_type. */ -+ reloc_bits, /* adjust_reloc_bits. */ -+ "desc_hi20"), /* larch_reloc_type_name. */ -+ -+ LOONGARCH_HOWTO (R_LARCH_TLS_DESC_LO12, /* type (116). */ -+ 0, /* rightshift. */ -+ 4, /* size. */ -+ 12, /* bitsize. */ -+ false, /* pc_relative. */ -+ 10, /* bitpos. */ -+ complain_overflow_signed, /* complain_on_overflow. */ -+ bfd_elf_generic_reloc, /* special_function. */ -+ "R_LARCH_TLS_DESC_LO12", /* name. */ -+ false, /* partial_inplace. */ -+ 0, /* src_mask. */ -+ 0x3ffc00, /* dst_mask. */ -+ false, /* pcrel_offset. */ -+ BFD_RELOC_LARCH_TLS_DESC_LO12, /* bfd_reloc_code_real_type. */ -+ reloc_bits, /* adjust_reloc_bits. */ -+ "desc_lo12"), /* larch_reloc_type_name. */ -+ -+ /* TLS_DESC64 LARGE ABS. */ -+ LOONGARCH_HOWTO (R_LARCH_TLS_DESC64_LO20, /* type (117). */ -+ 32, /* rightshift. */ -+ 8, /* size. */ -+ 20, /* bitsize. */ -+ false, /* pc_relative. */ -+ 5, /* bitpos. */ -+ complain_overflow_signed, /* complain_on_overflow. */ -+ bfd_elf_generic_reloc, /* special_function. */ -+ "R_LARCH_TLS_DESC64_LO20", /* name. */ -+ false, /* partial_inplace. */ -+ 0, /* src_mask. */ -+ 0x1ffffe0, /* dst_mask. */ -+ false, /* pcrel_offset. */ -+ BFD_RELOC_LARCH_TLS_DESC64_LO20, /* bfd_reloc_code_real_type. */ -+ reloc_bits, /* adjust_reloc_bits. */ -+ "desc64_lo20"), /* larch_reloc_type_name. */ -+ -+ LOONGARCH_HOWTO (R_LARCH_TLS_DESC64_HI12, /* type (118). */ -+ 52, /* rightshift. */ -+ 8, /* size. */ -+ 12, /* bitsize. */ -+ false, /* pc_relative. */ -+ 10, /* bitpos. */ -+ complain_overflow_signed, /* complain_on_overflow. */ -+ bfd_elf_generic_reloc, /* special_function. */ -+ "R_LARCH_TLS_DESC64_HI12", /* name. */ -+ false, /* partial_inplace. */ -+ 0, /* src_mask. */ -+ 0x3ffc00, /* dst_mask. */ -+ false, /* pcrel_offset. */ -+ BFD_RELOC_LARCH_TLS_DESC64_HI12, /* bfd_reloc_code_real_type. */ -+ reloc_bits, /* adjust_reloc_bits. */ -+ "desc64_hi12"), /* larch_reloc_type_name. */ -+ -+ LOONGARCH_HOWTO (R_LARCH_TLS_DESC_LD, /* type (119). */ -+ 0, /* rightshift. */ -+ 4, /* size. */ -+ 0, /* bitsize. */ -+ true, /* pc_relative. */ -+ 0, /* bitpos. */ -+ complain_overflow_signed, /* complain_on_overflow. */ -+ bfd_elf_generic_reloc, /* special_function. */ -+ "R_LARCH_TLS_DESC_LD", /* name. */ -+ false, /* partial_inplace. */ -+ 0, /* src_mask. */ -+ 0, /* dst_mask. */ -+ false, /* pcrel_offset. */ -+ BFD_RELOC_LARCH_TLS_DESC_LD, /* bfd_reloc_code_real_type. */ -+ NULL, /* adjust_reloc_bits. */ -+ "desc_ld"), /* larch_reloc_type_name. */ -+ -+ LOONGARCH_HOWTO (R_LARCH_TLS_DESC_CALL, /* type (120). */ -+ 0, /* rightshift. */ -+ 4, /* size. */ -+ 0, /* bitsize. */ -+ false, /* pc_relative. */ -+ 0, /* bitpos. */ -+ complain_overflow_dont, /* complain_on_overflow. */ -+ bfd_elf_generic_reloc, /* special_function. */ -+ "R_LARCH_TLS_DESC_CALL", /* name. */ -+ false, /* partial_inplace. */ -+ 0, /* src_mask. */ -+ 0, /* dst_mask. */ -+ false, /* pcrel_offset. */ -+ BFD_RELOC_LARCH_TLS_DESC_CALL, /* bfd_reloc_code_real_type. */ -+ NULL, /* adjust_reloc_bits. */ -+ "desc_call"), /* larch_reloc_type_name. */ - }; - - reloc_howto_type * -diff --git a/bfd/libbfd.h b/bfd/libbfd.h -index 297f3048..a474b971 100644 ---- a/bfd/libbfd.h -+++ b/bfd/libbfd.h -@@ -3442,6 +3442,8 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@", - "BFD_RELOC_LARCH_TLS_DTPREL64", - "BFD_RELOC_LARCH_TLS_TPREL32", - "BFD_RELOC_LARCH_TLS_TPREL64", -+ "BFD_RELOC_LARCH_TLS_DESC32", -+ "BFD_RELOC_LARCH_TLS_DESC64", - "BFD_RELOC_LARCH_MARK_LA", - "BFD_RELOC_LARCH_MARK_PCREL", - "BFD_RELOC_LARCH_SOP_PUSH_PCREL", -@@ -3526,6 +3528,16 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@", - "BFD_RELOC_LARCH_SUB_ULEB128", - "BFD_RELOC_LARCH_64_PCREL", - "BFD_RELOC_LARCH_CALL36", -+ "BFD_RELOC_LARCH_TLS_DESC_PC_HI20", -+ "BFD_RELOC_LARCH_TLS_DESC_PC_LO12", -+ "BFD_RELOC_LARCH_TLS_DESC64_PC_LO20", -+ "BFD_RELOC_LARCH_TLS_DESC64_PC_HI12", -+ "BFD_RELOC_LARCH_TLS_DESC_HI20", -+ "BFD_RELOC_LARCH_TLS_DESC_LO12", -+ "BFD_RELOC_LARCH_TLS_DESC64_LO20", -+ "BFD_RELOC_LARCH_TLS_DESC64_HI12", -+ "BFD_RELOC_LARCH_TLS_DESC_LD", -+ "BFD_RELOC_LARCH_TLS_DESC_CALL", - "@@overflow: BFD_RELOC_UNUSED@@", - }; - #endif -diff --git a/bfd/reloc.c b/bfd/reloc.c -index 70004f04..5af98afb 100644 ---- a/bfd/reloc.c -+++ b/bfd/reloc.c -@@ -7975,6 +7975,10 @@ ENUMX - BFD_RELOC_LARCH_TLS_TPREL32 - ENUMX - BFD_RELOC_LARCH_TLS_TPREL64 -+ENUMX -+ BFD_RELOC_LARCH_TLS_DESC32 -+ENUMX -+ BFD_RELOC_LARCH_TLS_DESC64 - ENUMX - BFD_RELOC_LARCH_MARK_LA - ENUMX -@@ -8159,6 +8163,31 @@ ENUMX - ENUMX - BFD_RELOC_LARCH_CALL36 - -+ENUMX -+ BFD_RELOC_LARCH_TLS_DESC_PC_HI20 -+ENUMX -+ BFD_RELOC_LARCH_TLS_DESC_PC_LO12 -+ -+ENUMX -+ BFD_RELOC_LARCH_TLS_DESC64_PC_LO20 -+ENUMX -+ BFD_RELOC_LARCH_TLS_DESC64_PC_HI12 -+ -+ENUMX -+ BFD_RELOC_LARCH_TLS_DESC_HI20 -+ENUMX -+ BFD_RELOC_LARCH_TLS_DESC_LO12 -+ -+ENUMX -+ BFD_RELOC_LARCH_TLS_DESC64_LO20 -+ENUMX -+ BFD_RELOC_LARCH_TLS_DESC64_HI12 -+ -+ENUMX -+ BFD_RELOC_LARCH_TLS_DESC_LD -+ENUMX -+ BFD_RELOC_LARCH_TLS_DESC_CALL -+ - ENUMDOC - LARCH relocations. - -diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c -index 9b912daf..1658025f 100644 ---- a/gas/config/tc-loongarch.c -+++ b/gas/config/tc-loongarch.c -@@ -682,7 +682,7 @@ loongarch_args_parser_can_match_arg_helper (char esc_ch1, char esc_ch2, - esc_ch1, esc_ch2, bit_field, arg); - - if (ip->reloc_info[0].type >= BFD_RELOC_LARCH_B16 -- && ip->reloc_info[0].type < BFD_RELOC_UNUSED) -+ && ip->reloc_info[0].type <= BFD_RELOC_LARCH_TLS_DESC_CALL) - { - /* As we compact stack-relocs, it is no need for pop operation. - But break out until here in order to check the imm field. -@@ -1274,6 +1274,14 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) - case BFD_RELOC_LARCH_TLS_LD_HI20: - case BFD_RELOC_LARCH_TLS_GD_PC_HI20: - case BFD_RELOC_LARCH_TLS_GD_HI20: -+ case BFD_RELOC_LARCH_TLS_DESC_PC_HI20: -+ case BFD_RELOC_LARCH_TLS_DESC_PC_LO12: -+ case BFD_RELOC_LARCH_TLS_DESC64_PC_LO20: -+ case BFD_RELOC_LARCH_TLS_DESC64_PC_HI12: -+ case BFD_RELOC_LARCH_TLS_DESC_HI20: -+ case BFD_RELOC_LARCH_TLS_DESC_LO12: -+ case BFD_RELOC_LARCH_TLS_DESC64_LO20: -+ case BFD_RELOC_LARCH_TLS_DESC64_HI12: - /* Add tls lo (got_lo reloc type). */ - if (fixP->fx_addsy == NULL) - as_bad_where (fixP->fx_file, fixP->fx_line, -@@ -1294,6 +1302,10 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) - stack_top = 0; - break; - -+ case BFD_RELOC_LARCH_TLS_DESC_LD: -+ case BFD_RELOC_LARCH_TLS_DESC_CALL: -+ break; -+ - case BFD_RELOC_LARCH_SOP_POP_32_S_10_5: - case BFD_RELOC_LARCH_SOP_POP_32_S_10_12: - case BFD_RELOC_LARCH_SOP_POP_32_U_10_12: -diff --git a/include/elf/loongarch.h b/include/elf/loongarch.h -index 34719ee8..41e9fe4d 100644 ---- a/include/elf/loongarch.h -+++ b/include/elf/loongarch.h -@@ -38,7 +38,8 @@ RELOC_NUMBER (R_LARCH_TLS_DTPREL64, 9) - RELOC_NUMBER (R_LARCH_TLS_TPREL32, 10) - RELOC_NUMBER (R_LARCH_TLS_TPREL64, 11) - RELOC_NUMBER (R_LARCH_IRELATIVE, 12) -- -+RELOC_NUMBER (R_LARCH_TLS_DESC32, 13) -+RELOC_NUMBER (R_LARCH_TLS_DESC64, 14) - /* Reserved for future relocs that the dynamic linker must understand. */ - - /* Used by the static linker for relocating .text. */ -@@ -253,6 +254,25 @@ RELOC_NUMBER (R_LARCH_64_PCREL, 109) - - RELOC_NUMBER (R_LARCH_CALL36, 110) - -+/* TLS_DESC PCREL. */ -+RELOC_NUMBER (R_LARCH_TLS_DESC_PC_HI20, 111) -+RELOC_NUMBER (R_LARCH_TLS_DESC_PC_LO12, 112) -+ -+/* TLS_DESC LARGE PCREL. */ -+RELOC_NUMBER (R_LARCH_TLS_DESC64_PC_LO20, 113) -+RELOC_NUMBER (R_LARCH_TLS_DESC64_PC_HI12, 114) -+ -+/* TLS_DESC ABS. */ -+RELOC_NUMBER (R_LARCH_TLS_DESC_HI20, 115) -+RELOC_NUMBER (R_LARCH_TLS_DESC_LO12, 116) -+ -+/* TLSDESC LARGE ABS. */ -+RELOC_NUMBER (R_LARCH_TLS_DESC64_LO20, 117) -+RELOC_NUMBER (R_LARCH_TLS_DESC64_HI12, 118) -+ -+RELOC_NUMBER (R_LARCH_TLS_DESC_LD, 119) -+RELOC_NUMBER (R_LARCH_TLS_DESC_CALL, 120) -+ - END_RELOC_NUMBERS (R_LARCH_count) - - /* Processor specific flags for the ELF header e_flags field. */ -diff --git a/opcodes/loongarch-opc.c b/opcodes/loongarch-opc.c -index b47817f8..a632373f 100644 ---- a/opcodes/loongarch-opc.c -+++ b/opcodes/loongarch-opc.c -@@ -303,6 +303,55 @@ const char *const loongarch_x_normal_name[32] = - "jirl $zero,%1,0;", \ - 0, 0 - -+/* For TLS_DESC32 pcrel. */ -+#define INSN_LA_TLS_DESC32 \ -+ "pcalau12i $r4,%%desc_pc_hi20(%2);" \ -+ "addi.w $r4,$r4,%%desc_pc_lo12(%2);" \ -+ "ld.w $r1,$r4,%%desc_ld(%2);" \ -+ "jirl $r1,$r1,%%desc_call(%2);", \ -+ &LARCH_opts.ase_ilp32, \ -+ &LARCH_opts.ase_lp64 -+ -+/* For TLS_DESC32 abs. */ -+#define INSN_LA_TLS_DESC32_ABS \ -+ "lu12i.w $r4,%%desc_hi20(%2);" \ -+ "ori $r4,$r4,%%desc_lo12(%2);" \ -+ "ld.w $r1,$r4,%%desc_ld(%2);" \ -+ "jirl $r1,$r1,%%desc_call(%2);", \ -+ &LARCH_opts.ase_gabs, \ -+ &LARCH_opts.ase_lp64 -+ -+/* For TLS_DESC64 pcrel. */ -+#define INSN_LA_TLS_DESC64 \ -+ "pcalau12i $r4,%%desc_pc_hi20(%2);" \ -+ "addi.d $r4,$r4,%%desc_pc_lo12(%2);" \ -+ "ld.d $r1,$r4,%%desc_ld(%2);" \ -+ "jirl $r1,$r1,%%desc_call(%2);", \ -+ &LARCH_opts.ase_lp64, 0 -+ -+/* For TLS_DESC64 large pcrel. */ -+#define INSN_LA_TLS_DESC64_LARGE_PCREL \ -+ "pcalau12i $r4,%%desc_pc_hi20(%3);" \ -+ "addi.d %2,$r0,%%desc_pc_lo12(%3);" \ -+ "lu32i.d %2,%%desc64_pc_lo20(%3);" \ -+ "lu52i.d %2,%2,%%desc64_pc_hi12(%3);" \ -+ "add.d $r4,$r4,%2;" \ -+ "ld.d $r1,$r4,%%desc_ld(%3);" \ -+ "jirl $r1,$r1,%%desc_call(%3);", \ -+ &LARCH_opts.ase_lp64, \ -+ &LARCH_opts.ase_gabs -+ -+/* For TLS_DESC64 large abs. */ -+#define INSN_LA_TLS_DESC64_LARGE_ABS \ -+ "lu12i.w $r4,%%desc_hi20(%2);" \ -+ "ori $r4,$r4,%%desc_lo12(%2);" \ -+ "lu32i.d $r4,%%desc64_lo20(%2);" \ -+ "lu52i.d $r4,$r4,%%desc64_hi12(%2);" \ -+ "ld.d $r1,$r4,%%desc_ld(%2);" \ -+ "jirl $r1,$r1,%%desc_call(%2);", \ -+ &LARCH_opts.ase_gabs, \ -+ &LARCH_opts.ase_gpcr -+ - static struct loongarch_opcode loongarch_macro_opcodes[] = - { - /* match, mask, name, format, macro, include, exclude, pinfo. */ -@@ -352,6 +401,11 @@ static struct loongarch_opcode loongarch_macro_opcodes[] = - { 0, 0, "call36", "la", INSN_LA_CALL, 0 }, - { 0, 0, "tail36", "r,la", INSN_LA_TAIL, 0 }, - { 0, 0, "pcaddi", "r,la", "pcaddi %1, %%pcrel_20(%2)", &LARCH_opts.ase_ilp32, 0, 0 }, -+ { 0, 0, "la.tls.desc", "r,l", INSN_LA_TLS_DESC32_ABS, 0 }, -+ { 0, 0, "la.tls.desc", "r,l", INSN_LA_TLS_DESC32, 0 }, -+ { 0, 0, "la.tls.desc", "r,l", INSN_LA_TLS_DESC64_LARGE_ABS, 0 }, -+ { 0, 0, "la.tls.desc", "r,l", INSN_LA_TLS_DESC64, 0 }, -+ { 0, 0, "la.tls.desc", "r,r,l", INSN_LA_TLS_DESC64_LARGE_PCREL,0 }, - { 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list. */ - }; - --- -2.33.0 - diff --git a/LoongArch-Add-relaxation-for-R_LARCH_CALL36.patch b/LoongArch-Add-relaxation-for-R_LARCH_CALL36.patch deleted file mode 100644 index 9ce9579..0000000 --- a/LoongArch-Add-relaxation-for-R_LARCH_CALL36.patch +++ /dev/null @@ -1,684 +0,0 @@ -From 1ac9f2fb1378c35c8d75b54b82a34a5e560b6ad3 Mon Sep 17 00:00:00 2001 -From: mengqinggang -Date: Wed, 28 Feb 2024 17:42:36 +0800 -Subject: [PATCH 074/123] LoongArch: Add relaxation for R_LARCH_CALL36 - -This relaxation is effective for both macro instructions (call36, tail36) -and explicit relocation instructions (pcaddu18i + jirl). - -call36 f -> bl f - R_LARCH_CALL36 -> R_LARCH_B26 - -tail36 $t0, f -> b f - R_LARCH_CALL36 -> R_LARCH_B26 ---- - bfd/elfnn-loongarch.c | 59 ++++ - gas/config/tc-loongarch.c | 19 +- - gas/testsuite/gas/loongarch/medium-call.d | 7 +- - .../relax-cfi-fde-DW_CFA_advance_loc.d | 10 +- - .../relax-cfi-fde-DW_CFA_advance_loc.s | 4 + - gas/testsuite/gas/loongarch/relocs_64.d | 282 +++++++++--------- - .../ld-loongarch-elf/ld-loongarch-elf.exp | 2 + - .../ld-loongarch-elf/relax-medium-call-1.d | 21 ++ - .../ld-loongarch-elf/relax-medium-call-1.s | 43 +++ - .../ld-loongarch-elf/relax-medium-call.d | 21 ++ - .../ld-loongarch-elf/relax-medium-call.s | 35 +++ - 11 files changed, 356 insertions(+), 147 deletions(-) - create mode 100644 ld/testsuite/ld-loongarch-elf/relax-medium-call-1.d - create mode 100644 ld/testsuite/ld-loongarch-elf/relax-medium-call-1.s - create mode 100644 ld/testsuite/ld-loongarch-elf/relax-medium-call.d - create mode 100644 ld/testsuite/ld-loongarch-elf/relax-medium-call.s - -diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c -index 489ccbe0..1c3295f4 100644 ---- a/bfd/elfnn-loongarch.c -+++ b/bfd/elfnn-loongarch.c -@@ -4334,6 +4334,60 @@ loongarch_relax_pcala_addi (bfd *abfd, asection *sec, asection *sym_sec, - return true; - } - -+/* call36 f -> bl f -+ tail36 $t0, f -> b f. */ -+static bool -+loongarch_relax_call36 (bfd *abfd, asection *sec, -+ Elf_Internal_Rela *rel, bfd_vma symval, -+ struct bfd_link_info *info, bool *again, -+ bfd_vma max_alignment) -+{ -+ bfd_byte *contents = elf_section_data (sec)->this_hdr.contents; -+ uint32_t jirl = bfd_get (32, abfd, contents + rel->r_offset + 4); -+ uint32_t rd = jirl & 0x1f; -+ -+ /* This section's output_offset need to subtract the bytes of instructions -+ relaxed by the previous sections, so it needs to be updated beforehand. -+ size_input_section already took care of updating it after relaxation, -+ so we additionally update once here. */ -+ sec->output_offset = sec->output_section->size; -+ bfd_vma pc = sec_addr (sec) + rel->r_offset; -+ -+ /* If pc and symbol not in the same segment, add/sub segment alignment. -+ FIXME: if there are multiple readonly segments? How to determine if -+ two sections are in the same segment. */ -+ if (symval > pc) -+ pc -= (max_alignment > 4 ? max_alignment : 0); -+ else if (symval < pc) -+ pc += (max_alignment > 4 ? max_alignment : 0); -+ -+ const uint32_t jirl_opcode = 0x4c000000; -+ -+ /* Is pcalau12i + addi.d insns? */ -+ if ((ELFNN_R_TYPE ((rel + 1)->r_info) != R_LARCH_RELAX) -+ || ((jirl & jirl_opcode) != jirl_opcode) -+ || ((bfd_signed_vma)(symval - pc) < (bfd_signed_vma)(int32_t)0xf8000000) -+ || ((bfd_signed_vma)(symval - pc) > (bfd_signed_vma)(int32_t)0x7fffffc)) -+ return false; -+ -+ /* Continue next relax trip. */ -+ *again = true; -+ -+ const uint32_t bl = 0x54000000; -+ const uint32_t b = 0x50000000; -+ -+ if (rd) -+ bfd_put (32, abfd, bl, contents + rel->r_offset); -+ else -+ bfd_put (32, abfd, b, contents + rel->r_offset); -+ -+ /* Adjust relocations. */ -+ rel->r_info = ELFNN_R_INFO (ELFNN_R_SYM (rel->r_info), R_LARCH_B26); -+ /* Delete jirl instruction. */ -+ loongarch_relax_delete_bytes (abfd, sec, rel->r_offset + 4, 4, info); -+ return true; -+} -+ - /* Relax pcalau12i,ld.d => pcalau12i,addi.d. */ - static bool - loongarch_relax_pcala_ld (bfd *abfd, asection *sec, -@@ -4752,6 +4806,11 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, - rel->r_info = ELFNN_R_INFO (0, R_LARCH_NONE); - } - break; -+ case R_LARCH_CALL36: -+ if (0 == info->relax_pass && (i + 2) <= sec->reloc_count) -+ loongarch_relax_call36 (abfd, sec, rel, symval, info, again, -+ max_alignment); -+ break; - - case R_LARCH_TLS_LE_HI20_R: - case R_LARCH_TLS_LE_LO12_R: -diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c -index ff126d56..51575757 100644 ---- a/gas/config/tc-loongarch.c -+++ b/gas/config/tc-loongarch.c -@@ -116,6 +116,8 @@ const char *md_shortopts = "O::g::G:"; - - static const char default_arch[] = DEFAULT_ARCH; - -+static bool call36 = 0; -+ - /* The lowest 4-bit is the bytes of instructions. */ - #define RELAX_BRANCH_16 0xc0000014 - #define RELAX_BRANCH_21 0xc0000024 -@@ -720,7 +722,8 @@ loongarch_args_parser_can_match_arg_helper (char esc_ch1, char esc_ch2, - || BFD_RELOC_LARCH_TLS_LE_HI20 == reloc_type - || BFD_RELOC_LARCH_TLS_LE_LO12 == reloc_type - || BFD_RELOC_LARCH_TLS_LE64_LO20 == reloc_type -- || BFD_RELOC_LARCH_TLS_LE64_HI12 == reloc_type)) -+ || BFD_RELOC_LARCH_TLS_LE64_HI12 == reloc_type -+ || BFD_RELOC_LARCH_CALL36 == reloc_type)) - { - ip->reloc_info[ip->reloc_num].type = BFD_RELOC_LARCH_RELAX; - ip->reloc_info[ip->reloc_num].value = const_0; -@@ -1016,6 +1019,20 @@ append_fixed_insn (struct loongarch_cl_insn *insn) - - char *f = frag_more (insn->insn_length); - move_insn (insn, frag_now, f - frag_now->fr_literal); -+ -+ if (call36) -+ { -+ if (strcmp (insn->name, "jirl") == 0) -+ { -+ /* See comment at end of append_fixp_and_insn. */ -+ frag_wane (frag_now); -+ frag_new (0); -+ } -+ call36 = 0; -+ } -+ -+ if (BFD_RELOC_LARCH_CALL36 == insn->reloc_info[0].type) -+ call36 = 1; - } - - /* Add instructions based on the worst-case scenario firstly. */ -diff --git a/gas/testsuite/gas/loongarch/medium-call.d b/gas/testsuite/gas/loongarch/medium-call.d -index 3491760b..79d74ba3 100644 ---- a/gas/testsuite/gas/loongarch/medium-call.d -+++ b/gas/testsuite/gas/loongarch/medium-call.d -@@ -1,21 +1,26 @@ - #as: - #objdump: -dr -+#skip: loongarch32-*-* - - .*:[ ]+file format .* - - - Disassembly of section .text: - --.* <.text>: -+[ ]*0000000000000000 <.text>: - [ ]+0:[ ]+1e000001[ ]+pcaddu18i[ ]+\$ra, 0 - [ ]+0: R_LARCH_CALL36[ ]+a -+[ ]+0: R_LARCH_RELAX[ ]+\*ABS\* - [ ]+4:[ ]+4c000021[ ]+jirl[ ]+\$ra, \$ra, 0 - [ ]+8:[ ]+1e000001[ ]+pcaddu18i[ ]+\$ra, 0 - [ ]+8: R_LARCH_CALL36[ ]+a -+[ ]+8: R_LARCH_RELAX[ ]+\*ABS\* - [ ]+c:[ ]+4c000021[ ]+jirl[ ]+\$ra, \$ra, 0 - [ ]+10:[ ]+1e00000c[ ]+pcaddu18i[ ]+\$t0, 0 - [ ]+10: R_LARCH_CALL36[ ]+a -+[ ]+10: R_LARCH_RELAX[ ]+\*ABS\* - [ ]+14:[ ]+4c000180[ ]+jr[ ]+\$t0 - [ ]+18:[ ]+1e00000c[ ]+pcaddu18i[ ]+\$t0, 0 - [ ]+18: R_LARCH_CALL36[ ]+a -+[ ]+18: R_LARCH_RELAX[ ]+\*ABS\* - [ ]+1c:[ ]+4c000180[ ]+jr[ ]+\$t0 -diff --git a/gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.d b/gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.d -index 6b164cfb..d685bd86 100644 ---- a/gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.d -+++ b/gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.d -@@ -26,7 +26,7 @@ Disassembly of section .eh_frame: - [ ]+2c:[ ]+d6400016[ ]+.word[ ]+[ ]+0xd6400016 - [ ]+2e: R_LARCH_ADD6[ ]+L0\^A - [ ]+2e: R_LARCH_SUB6[ ]+L0\^A --[ ]+30:[ ]+4000160c[ ]+beqz[ ]+\$t4, 3145748[ ]+# 300044 -+[ ]+30:[ ]+4000160c[ ]+beqz[ ]+\$t4, 3145748[ ]+# 300044 - [ ]+33: R_LARCH_ADD6[ ]+L0\^A - [ ]+33: R_LARCH_SUB6[ ]+L0\^A - [ ]+34:[ ]+00160cd6[ ]+orn[ ]+\$fp, \$a2, \$sp -@@ -39,14 +39,16 @@ Disassembly of section .eh_frame: - [ ]+40:[ ]+d6400016[ ]+.word[ ]+[ ]+0xd6400016 - [ ]+42: R_LARCH_ADD6[ ]+L0\^A - [ ]+42: R_LARCH_SUB6[ ]+L0\^A --[ ]+44:[ ]+4000160c[ ]+beqz[ ]+\$t4, 3145748[ ]+# 300058 -+[ ]+44:[ ]+4000160c[ ]+beqz[ ]+\$t4, 3145748[ ]+# 300058 - [ ]+47: R_LARCH_ADD6[ ]+L0\^A - [ ]+47: R_LARCH_SUB6[ ]+L0\^A - [ ]+48:[ ]+00160cd6[ ]+orn[ ]+\$fp, \$a2, \$sp - [ ]+4c:[ ]+160cd640[ ]+lu32i.d[ ]+\$zero, 26290 - [ ]+4c: R_LARCH_ADD6[ ]+L0\^A - [ ]+4c: R_LARCH_SUB6[ ]+L0\^A --[ ]+50:[ ]+00d64000[ ]+bstrpick.d[ ]+\$zero, \$zero, 0x16, 0x10 -+[ ]+50:[ ]+0cd64000[ ]+.word[ ]+[ ]+0x0cd64000 - [ ]+51: R_LARCH_ADD6[ ]+L0\^A - [ ]+51: R_LARCH_SUB6[ ]+L0\^A --[ ]+54:[ ]+00000000[ ]+.word[ ]+[ ]+0x00000000 -+[ ]+54:[ ]+d6400016[ ]+.word[ ]+[ ]+0xd6400016 -+[ ]+56: R_LARCH_ADD6[ ]+L0\^A -+[ ]+56: R_LARCH_SUB6[ ]+L0\^A -diff --git a/gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.s b/gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.s -index 2c67587b..021d296a 100644 ---- a/gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.s -+++ b/gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.s -@@ -38,4 +38,8 @@ la.tls.ie $t0, a - la.tls.le $t0, a - .cfi_restore 22 - -+.cfi_def_cfa 22, 0 -+call36 f -+.cfi_restore 22 -+ - .cfi_endproc -diff --git a/gas/testsuite/gas/loongarch/relocs_64.d b/gas/testsuite/gas/loongarch/relocs_64.d -index 35dde02f..ce5216a2 100644 ---- a/gas/testsuite/gas/loongarch/relocs_64.d -+++ b/gas/testsuite/gas/loongarch/relocs_64.d -@@ -1,148 +1,148 @@ --#as: -mthin-add-sub -+#as: - #objdump: -dr - #skip: loongarch32-*-* - --.*: file format .* -+.*:[ ]+file format .* - - - Disassembly of section .text: - --0+ <.*>: -- 0: 4c008ca4 jirl \$a0, \$a1, 140 -- 0: R_LARCH_B16 .L1 -- 4: 40008880 beqz \$a0, 136 # 8c <.L1> -- 4: R_LARCH_B21 .L1 -- 8: 50008400 b 132 # 8c <.L1> -- 8: R_LARCH_B26 .L1 -- c: 14000004 lu12i.w \$a0, 0 -- c: R_LARCH_ABS_HI20 .L1 -- 10: 038000a4 ori \$a0, \$a1, 0x0 -- 10: R_LARCH_ABS_LO12 .L1 -- 14: 16000004 lu32i.d \$a0, 0 -- 14: R_LARCH_ABS64_LO20 .L1 -- 18: 03000085 lu52i.d \$a1, \$a0, 0 -- 18: R_LARCH_ABS64_HI12 .L1 -- 1c: 1a000004 pcalau12i \$a0, 0 -- 1c: R_LARCH_PCALA_HI20 .L1 -- 20: 02c00085 addi.d \$a1, \$a0, 0 -- 20: R_LARCH_PCALA_LO12 .L1 -- 24: 16000004 lu32i.d \$a0, 0 -- 24: R_LARCH_PCALA64_LO20 .L1 -- 28: 03000085 lu52i.d \$a1, \$a0, 0 -- 28: R_LARCH_PCALA64_HI12 .L1 -- 2c: 1a000004 pcalau12i \$a0, 0 -- 2c: R_LARCH_GOT_PC_HI20 .L1 -- 30: 28c00085 ld.d \$a1, \$a0, 0 -- 30: R_LARCH_GOT_PC_LO12 .L1 -- 34: 16000004 lu32i.d \$a0, 0 -- 34: R_LARCH_GOT64_PC_LO20 .L1 -- 38: 03000085 lu52i.d \$a1, \$a0, 0 -- 38: R_LARCH_GOT64_PC_HI12 .L1 -- 3c: 14000004 lu12i.w \$a0, 0 -- 3c: R_LARCH_GOT_HI20 .L1 -- 40: 03800084 ori \$a0, \$a0, 0x0 -- 40: R_LARCH_GOT_LO12 .L1 -- 44: 16000004 lu32i.d \$a0, 0 -- 44: R_LARCH_GOT64_LO20 .L1 -- 48: 03000085 lu52i.d \$a1, \$a0, 0 -- 48: R_LARCH_GOT64_HI12 .L1 -- 4c: 14000004 lu12i.w \$a0, 0 -- 4c: R_LARCH_TLS_LE_HI20 TLSL1 -- 4c: R_LARCH_RELAX \*ABS\* -- 50: 03800085 ori \$a1, \$a0, 0x0 -- 50: R_LARCH_TLS_LE_LO12 TLSL1 -- 50: R_LARCH_RELAX \*ABS\* -- 54: 16000004 lu32i.d \$a0, 0 -- 54: R_LARCH_TLS_LE64_LO20 TLSL1 -- 54: R_LARCH_RELAX \*ABS\* -- 58: 03000085 lu52i.d \$a1, \$a0, 0 -- 58: R_LARCH_TLS_LE64_HI12 TLSL1 -- 58: R_LARCH_RELAX \*ABS\* -- 5c: 1a000004 pcalau12i \$a0, 0 -- 5c: R_LARCH_TLS_IE_PC_HI20 TLSL1 -- 60: 02c00005 li.d \$a1, 0 -- 60: R_LARCH_TLS_IE_PC_LO12 TLSL1 -- 64: 16000005 lu32i.d \$a1, 0 -- 64: R_LARCH_TLS_IE64_PC_LO20 TLSL1 -- 68: 030000a5 lu52i.d \$a1, \$a1, 0 -- 68: R_LARCH_TLS_IE64_PC_HI12 TLSL1 -- 6c: 14000004 lu12i.w \$a0, 0 -- 6c: R_LARCH_TLS_IE_HI20 TLSL1 -- 70: 03800084 ori \$a0, \$a0, 0x0 -- 70: R_LARCH_TLS_IE_LO12 TLSL1 -- 74: 16000004 lu32i.d \$a0, 0 -- 74: R_LARCH_TLS_IE64_LO20 TLSL1 -- 78: 03000084 lu52i.d \$a0, \$a0, 0 -- 78: R_LARCH_TLS_IE64_HI12 TLSL1 -- 7c: 1a000004 pcalau12i \$a0, 0 -- 7c: R_LARCH_TLS_LD_PC_HI20 TLSL1 -- 80: 14000004 lu12i.w \$a0, 0 -- 80: R_LARCH_TLS_LD_HI20 TLSL1 -- 84: 1a000004 pcalau12i \$a0, 0 -- 84: R_LARCH_TLS_GD_PC_HI20 TLSL1 -- 88: 14000004 lu12i.w \$a0, 0 -- 88: R_LARCH_TLS_GD_HI20 TLSL1 -- --0+8c <.L1>: -- 8c: 00000000 .word 0x00000000 -- 8c: R_LARCH_32_PCREL .L2 -- --0+90 <.L2>: -- ... -- 90: R_LARCH_64_PCREL .L3 -- --0+98 <.L3>: -- 98: 03400000 nop -- 9c: 03400000 nop -- 9c: R_LARCH_ALIGN .* -- a0: 03400000 nop -- a4: 03400000 nop -- a8: 1800000c pcaddi \$t0, 0 -- a8: R_LARCH_PCREL20_S2 .L1 -- ac: 1e000001 pcaddu18i \$ra, 0 -- ac: R_LARCH_CALL36 a -- b0: 4c000021 jirl \$ra, \$ra, 0 -- b4: 1a000004 pcalau12i \$a0, 0 -- b4: R_LARCH_TLS_DESC_PC_HI20 TLSL1 -- b8: 02c000a5 addi.d \$a1, \$a1, 0 -- b8: R_LARCH_TLS_DESC_PC_LO12 TLSL1 -- bc: 16000005 lu32i.d \$a1, 0 -- bc: R_LARCH_TLS_DESC64_PC_LO20 TLSL1 -- c0: 030000a5 lu52i.d \$a1, \$a1, 0 -- c0: R_LARCH_TLS_DESC64_PC_HI12 TLSL1 -- c4: 14000004 lu12i.w \$a0, 0 -- c4: R_LARCH_TLS_DESC_HI20 TLSL1 -- c8: 03800084 ori \$a0, \$a0, 0x0 -- c8: R_LARCH_TLS_DESC_LO12 TLSL1 -- cc: 16000004 lu32i.d \$a0, 0 -- cc: R_LARCH_TLS_DESC64_LO20 TLSL1 -- d0: 03000084 lu52i.d \$a0, \$a0, 0 -- d0: R_LARCH_TLS_DESC64_HI12 TLSL1 -- d4: 28c00081 ld.d \$ra, \$a0, 0 -- d4: R_LARCH_TLS_DESC_LD TLSL1 -- d8: 4c000021 jirl \$ra, \$ra, 0 -- d8: R_LARCH_TLS_DESC_CALL TLSL1 -- dc: 14000004 lu12i.w \$a0, 0 -- dc: R_LARCH_TLS_LE_HI20_R TLSL1 -- dc: R_LARCH_RELAX \*ABS\* -- e0: 001090a5 add.d \$a1, \$a1, \$a0 -- e0: R_LARCH_TLS_LE_ADD_R TLSL1 -- e0: R_LARCH_RELAX \*ABS\* -- e4: 29800085 st.w \$a1, \$a0, 0 -- e4: R_LARCH_TLS_LE_LO12_R TLSL1 -- e4: R_LARCH_RELAX \*ABS\* -- e8: 14000004 lu12i.w \$a0, 0 -- e8: R_LARCH_TLS_LE_HI20_R TLSL1 -- e8: R_LARCH_RELAX \*ABS\* -- ec: 001090a5 add.d \$a1, \$a1, \$a0 -- ec: R_LARCH_TLS_LE_ADD_R TLSL1 -- ec: R_LARCH_RELAX \*ABS\* -- f0: 29800085 st.w \$a1, \$a0, 0 -- f0: R_LARCH_TLS_LE_LO12_R TLSL1 -- f0: R_LARCH_RELAX \*ABS\* -- f4: 18000004 pcaddi \$a0, 0 -- f4: R_LARCH_TLS_LD_PCREL20_S2 TLSL1 -- f8: 18000004 pcaddi \$a0, 0 -- f8: R_LARCH_TLS_GD_PCREL20_S2 TLSL1 -- fc: 18000004 pcaddi \$a0, 0 -- fc: R_LARCH_TLS_DESC_PCREL20_S2 TLSL1 -+[ ]*0000000000000000 <.L1-0x8c>: -+[ ]+0:[ ]+4c008ca4[ ]+jirl[ ]+\$a0, \$a1, 140 -+[ ]+0: R_LARCH_B16[ ]+.L1 -+[ ]+4:[ ]+40008880[ ]+beqz[ ]+\$a0, 136[ ]+# 8c <.L1> -+[ ]+4: R_LARCH_B21[ ]+.L1 -+[ ]+8:[ ]+50008400[ ]+b[ ]+132[ ]+# 8c <.L1> -+[ ]+8: R_LARCH_B26[ ]+.L1 -+[ ]+c:[ ]+14000004[ ]+lu12i.w[ ]+\$a0, 0 -+[ ]+c: R_LARCH_ABS_HI20[ ]+.L1 -+[ ]+10:[ ]+038000a4[ ]+ori[ ]+\$a0, \$a1, 0x0 -+[ ]+10: R_LARCH_ABS_LO12[ ]+.L1 -+[ ]+14:[ ]+16000004[ ]+lu32i.d[ ]+\$a0, 0 -+[ ]+14: R_LARCH_ABS64_LO20[ ]+.L1 -+[ ]+18:[ ]+03000085[ ]+lu52i.d[ ]+\$a1, \$a0, 0 -+[ ]+18: R_LARCH_ABS64_HI12[ ]+.L1 -+[ ]+1c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0 -+[ ]+1c: R_LARCH_PCALA_HI20[ ]+.L1 -+[ ]+20:[ ]+02c00085[ ]+addi.d[ ]+\$a1, \$a0, 0 -+[ ]+20: R_LARCH_PCALA_LO12[ ]+.L1 -+[ ]+24:[ ]+16000004[ ]+lu32i.d[ ]+\$a0, 0 -+[ ]+24: R_LARCH_PCALA64_LO20[ ]+.L1 -+[ ]+28:[ ]+03000085[ ]+lu52i.d[ ]+\$a1, \$a0, 0 -+[ ]+28: R_LARCH_PCALA64_HI12[ ]+.L1 -+[ ]+2c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0 -+[ ]+2c: R_LARCH_GOT_PC_HI20[ ]+.L1 -+[ ]+30:[ ]+28c00085[ ]+ld.d[ ]+\$a1, \$a0, 0 -+[ ]+30: R_LARCH_GOT_PC_LO12[ ]+.L1 -+[ ]+34:[ ]+16000004[ ]+lu32i.d[ ]+\$a0, 0 -+[ ]+34: R_LARCH_GOT64_PC_LO20[ ]+.L1 -+[ ]+38:[ ]+03000085[ ]+lu52i.d[ ]+\$a1, \$a0, 0 -+[ ]+38: R_LARCH_GOT64_PC_HI12[ ]+.L1 -+[ ]+3c:[ ]+14000004[ ]+lu12i.w[ ]+\$a0, 0 -+[ ]+3c: R_LARCH_GOT_HI20[ ]+.L1 -+[ ]+40:[ ]+03800084[ ]+ori[ ]+\$a0, \$a0, 0x0 -+[ ]+40: R_LARCH_GOT_LO12[ ]+.L1 -+[ ]+44:[ ]+16000004[ ]+lu32i.d[ ]+\$a0, 0 -+[ ]+44: R_LARCH_GOT64_LO20[ ]+.L1 -+[ ]+48:[ ]+03000085[ ]+lu52i.d[ ]+\$a1, \$a0, 0 -+[ ]+48: R_LARCH_GOT64_HI12[ ]+.L1 -+[ ]+4c:[ ]+14000004[ ]+lu12i.w[ ]+\$a0, 0 -+[ ]+4c: R_LARCH_TLS_LE_HI20[ ]+TLSL1 -+[ ]+4c: R_LARCH_RELAX[ ]+\*ABS\* -+[ ]+50:[ ]+03800085[ ]+ori[ ]+\$a1, \$a0, 0x0 -+[ ]+50: R_LARCH_TLS_LE_LO12[ ]+TLSL1 -+[ ]+50: R_LARCH_RELAX[ ]+\*ABS\* -+[ ]+54:[ ]+16000004[ ]+lu32i.d[ ]+\$a0, 0 -+[ ]+54: R_LARCH_TLS_LE64_LO20[ ]+TLSL1 -+[ ]+54: R_LARCH_RELAX[ ]+\*ABS\* -+[ ]+58:[ ]+03000085[ ]+lu52i.d[ ]+\$a1, \$a0, 0 -+[ ]+58: R_LARCH_TLS_LE64_HI12[ ]+TLSL1 -+[ ]+58: R_LARCH_RELAX[ ]+\*ABS\* -+[ ]+5c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0 -+[ ]+5c: R_LARCH_TLS_IE_PC_HI20[ ]+TLSL1 -+[ ]+60:[ ]+02c00005[ ]+li.d[ ]+\$a1, 0 -+[ ]+60: R_LARCH_TLS_IE_PC_LO12[ ]+TLSL1 -+[ ]+64:[ ]+16000005[ ]+lu32i.d[ ]+\$a1, 0 -+[ ]+64: R_LARCH_TLS_IE64_PC_LO20[ ]+TLSL1 -+[ ]+68:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1, \$a1, 0 -+[ ]+68: R_LARCH_TLS_IE64_PC_HI12[ ]+TLSL1 -+[ ]+6c:[ ]+14000004[ ]+lu12i.w[ ]+\$a0, 0 -+[ ]+6c: R_LARCH_TLS_IE_HI20[ ]+TLSL1 -+[ ]+70:[ ]+03800084[ ]+ori[ ]+\$a0, \$a0, 0x0 -+[ ]+70: R_LARCH_TLS_IE_LO12[ ]+TLSL1 -+[ ]+74:[ ]+16000004[ ]+lu32i.d[ ]+\$a0, 0 -+[ ]+74: R_LARCH_TLS_IE64_LO20[ ]+TLSL1 -+[ ]+78:[ ]+03000084[ ]+lu52i.d[ ]+\$a0, \$a0, 0 -+[ ]+78: R_LARCH_TLS_IE64_HI12[ ]+TLSL1 -+[ ]+7c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0 -+[ ]+7c: R_LARCH_TLS_LD_PC_HI20[ ]+TLSL1 -+[ ]+80:[ ]+14000004[ ]+lu12i.w[ ]+\$a0, 0 -+[ ]+80: R_LARCH_TLS_LD_HI20[ ]+TLSL1 -+[ ]+84:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0 -+[ ]+84: R_LARCH_TLS_GD_PC_HI20[ ]+TLSL1 -+[ ]+88:[ ]+14000004[ ]+lu12i.w[ ]+\$a0, 0 -+[ ]+88: R_LARCH_TLS_GD_HI20[ ]+TLSL1 -+000000000000008c <.L1>: -+[ ]+8c:[ ]+00000000[ ]+.word[ ]+[ ]+0x00000000 -+[ ]+8c: R_LARCH_ADD32[ ]+.L2 -+[ ]+8c: R_LARCH_SUB32[ ]+.L1 -+0000000000000090 <.L2>: -+[ ]+... -+[ ]+90: R_LARCH_ADD64[ ]+.L3 -+[ ]+90: R_LARCH_SUB64[ ]+.L2 -+0000000000000098 <.L3>: -+[ ]+98:[ ]+03400000[ ]+nop -+[ ]+9c:[ ]+03400000[ ]+nop -+[ ]+9c: R_LARCH_ALIGN[ ]+\*ABS\*\+0xc -+[ ]+a0:[ ]+03400000[ ]+nop -+[ ]+a4:[ ]+03400000[ ]+nop -+[ ]+a8:[ ]+1800000c[ ]+pcaddi[ ]+\$t0, 0 -+[ ]+a8: R_LARCH_PCREL20_S2[ ]+.L1 -+[ ]+ac:[ ]+1e000001[ ]+pcaddu18i[ ]+\$ra, 0 -+[ ]+ac: R_LARCH_CALL36[ ]+a -+[ ]+ac: R_LARCH_RELAX[ ]+\*ABS\* -+[ ]+b0:[ ]+4c000021[ ]+jirl[ ]+\$ra, \$ra, 0 -+[ ]+b4:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0 -+[ ]+b4: R_LARCH_TLS_DESC_PC_HI20[ ]+TLSL1 -+[ ]+b8:[ ]+02c000a5[ ]+addi.d[ ]+\$a1, \$a1, 0 -+[ ]+b8: R_LARCH_TLS_DESC_PC_LO12[ ]+TLSL1 -+[ ]+bc:[ ]+16000005[ ]+lu32i.d[ ]+\$a1, 0 -+[ ]+bc: R_LARCH_TLS_DESC64_PC_LO20[ ]+TLSL1 -+[ ]+c0:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1, \$a1, 0 -+[ ]+c0: R_LARCH_TLS_DESC64_PC_HI12[ ]+TLSL1 -+[ ]+c4:[ ]+14000004[ ]+lu12i.w[ ]+\$a0, 0 -+[ ]+c4: R_LARCH_TLS_DESC_HI20[ ]+TLSL1 -+[ ]+c8:[ ]+03800084[ ]+ori[ ]+\$a0, \$a0, 0x0 -+[ ]+c8: R_LARCH_TLS_DESC_LO12[ ]+TLSL1 -+[ ]+cc:[ ]+16000004[ ]+lu32i.d[ ]+\$a0, 0 -+[ ]+cc: R_LARCH_TLS_DESC64_LO20[ ]+TLSL1 -+[ ]+d0:[ ]+03000084[ ]+lu52i.d[ ]+\$a0, \$a0, 0 -+[ ]+d0: R_LARCH_TLS_DESC64_HI12[ ]+TLSL1 -+[ ]+d4:[ ]+28c00081[ ]+ld.d[ ]+\$ra, \$a0, 0 -+[ ]+d4: R_LARCH_TLS_DESC_LD[ ]+TLSL1 -+[ ]+d8:[ ]+4c000021[ ]+jirl[ ]+\$ra, \$ra, 0 -+[ ]+d8: R_LARCH_TLS_DESC_CALL[ ]+TLSL1 -+[ ]+dc:[ ]+14000004[ ]+lu12i.w[ ]+\$a0, 0 -+[ ]+dc: R_LARCH_TLS_LE_HI20_R[ ]+TLSL1 -+[ ]+dc: R_LARCH_RELAX[ ]+\*ABS\* -+[ ]+e0:[ ]+001090a5[ ]+add.d[ ]+\$a1, \$a1, \$a0 -+[ ]+e0: R_LARCH_TLS_LE_ADD_R[ ]+TLSL1 -+[ ]+e0: R_LARCH_RELAX[ ]+\*ABS\* -+[ ]+e4:[ ]+29800085[ ]+st.w[ ]+\$a1, \$a0, 0 -+[ ]+e4: R_LARCH_TLS_LE_LO12_R[ ]+TLSL1 -+[ ]+e4: R_LARCH_RELAX[ ]+\*ABS\* -+[ ]+e8:[ ]+14000004[ ]+lu12i.w[ ]+\$a0, 0 -+[ ]+e8: R_LARCH_TLS_LE_HI20_R[ ]+TLSL1 -+[ ]+e8: R_LARCH_RELAX[ ]+\*ABS\* -+[ ]+ec:[ ]+001090a5[ ]+add.d[ ]+\$a1, \$a1, \$a0 -+[ ]+ec: R_LARCH_TLS_LE_ADD_R[ ]+TLSL1 -+[ ]+ec: R_LARCH_RELAX[ ]+\*ABS\* -+[ ]+f0:[ ]+29800085[ ]+st.w[ ]+\$a1, \$a0, 0 -+[ ]+f0: R_LARCH_TLS_LE_LO12_R[ ]+TLSL1 -+[ ]+f0: R_LARCH_RELAX[ ]+\*ABS\* -+[ ]+f4:[ ]+18000004[ ]+pcaddi[ ]+\$a0, 0 -+[ ]+f4: R_LARCH_TLS_LD_PCREL20_S2[ ]+TLSL1 -+[ ]+f8:[ ]+18000004[ ]+pcaddi[ ]+\$a0, 0 -+[ ]+f8: R_LARCH_TLS_GD_PCREL20_S2[ ]+TLSL1 -+[ ]+fc:[ ]+18000004[ ]+pcaddi[ ]+\$a0, 0 -+[ ]+fc: R_LARCH_TLS_DESC_PCREL20_S2[ ]+TLSL1 -diff --git a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -index c839f525..0121cad9 100644 ---- a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -+++ b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -@@ -52,6 +52,8 @@ if [istarget "loongarch64-*-*"] { - run_dump_test "underflow_s_5_20" - run_dump_test "tls-le-norelax" - run_dump_test "tls-le-relax" -+ run_dump_test "relax-medium-call" -+ run_dump_test "relax-medium-call-1" - } - - if [istarget "loongarch32-*-*"] { -diff --git a/ld/testsuite/ld-loongarch-elf/relax-medium-call-1.d b/ld/testsuite/ld-loongarch-elf/relax-medium-call-1.d -new file mode 100644 -index 00000000..c8ee9333 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/relax-medium-call-1.d -@@ -0,0 +1,21 @@ -+#ld: -e0 -Ttext=0x120000000 --section-start=ta=0x118000000 --section-start=tb=0x127fffffc -+#objdump: -d -j .text -+ -+.*:[ ]+file format .* -+ -+ -+Disassembly of section .text: -+ -+[ ]*0000000120000000 <__bss_start-0x4030>: -+[ ]+120000000:[ ]+54000200[ ]+bl[ ]+-134217728[ ]+# 118000000 -+[ ]+120000004:[ ]+1fffc001[ ]+pcaddu18i[ ]+\$ra, -512 -+[ ]+120000008:[ ]+4ffffc21[ ]+jirl[ ]+\$ra, \$ra, -4 -+[ ]+12000000c:[ ]+50000200[ ]+b[ ]+-134217728[ ]+# 11800000c -+[ ]+120000010:[ ]+1fffc00c[ ]+pcaddu18i[ ]+\$t0, -512 -+[ ]+120000014:[ ]+4ffffd80[ ]+jirl[ ]+\$zero, \$t0, -4 -+[ ]+120000018:[ ]+1e004001[ ]+pcaddu18i[ ]+\$ra, 512 -+[ ]+12000001c:[ ]+4c000421[ ]+jirl[ ]+\$ra, \$ra, 4 -+[ ]+120000020:[ ]+57fffdff[ ]+bl[ ]+134217724[ ]+# 12800001c -+[ ]+120000024:[ ]+1e00400c[ ]+pcaddu18i[ ]+\$t0, 512 -+[ ]+120000028:[ ]+4c000580[ ]+jirl[ ]+\$zero, \$t0, 4 -+[ ]+12000002c:[ ]+53fffdff[ ]+b[ ]+134217724[ ]+# 128000028 -diff --git a/ld/testsuite/ld-loongarch-elf/relax-medium-call-1.s b/ld/testsuite/ld-loongarch-elf/relax-medium-call-1.s -new file mode 100644 -index 00000000..5266fdab ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/relax-medium-call-1.s -@@ -0,0 +1,43 @@ -+.section "ta", "ax" -+a: -+ ret -+ ret -+ ret -+b: -+ ret -+ -+.text -+ pcaddu18i $ra, %call36(a) # min offset, can relax -+ jirl $ra, $ra, 0 -+ pcaddu18i $ra, %call36(a) # overflow, not relax -+ jirl $ra, $ra, 0 -+ pcaddu18i $t0, %call36(b) # min offset, can relax -+ jirl $zero, $t0, 0 -+ pcaddu18i $t0, %call36(b) # overflow, not relax -+ jirl $zero, $t0, 0 -+ -+ pcaddu18i $ra, %call36(c) # overflow, not relax -+ jirl $ra, $ra, 0 -+ pcaddu18i $ra, %call36(c) # max offset, can relax -+ jirl $ra, $ra, 0 -+ pcaddu18i $t0, %call36(d) # overflow, no relax -+ jirl $zero, $t0, 0 -+ pcaddu18i $t0, %call36(d) # max offset, can relax -+ jirl $zero, $t0, 0 -+ -+.section "tb", "ax" -+ ret -+ ret -+ ret -+ ret -+ ret -+ ret -+ ret -+ ret -+c: -+ ret -+ ret -+ ret -+d: -+ ret -+ -diff --git a/ld/testsuite/ld-loongarch-elf/relax-medium-call.d b/ld/testsuite/ld-loongarch-elf/relax-medium-call.d -new file mode 100644 -index 00000000..c8ee9333 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/relax-medium-call.d -@@ -0,0 +1,21 @@ -+#ld: -e0 -Ttext=0x120000000 --section-start=ta=0x118000000 --section-start=tb=0x127fffffc -+#objdump: -d -j .text -+ -+.*:[ ]+file format .* -+ -+ -+Disassembly of section .text: -+ -+[ ]*0000000120000000 <__bss_start-0x4030>: -+[ ]+120000000:[ ]+54000200[ ]+bl[ ]+-134217728[ ]+# 118000000 -+[ ]+120000004:[ ]+1fffc001[ ]+pcaddu18i[ ]+\$ra, -512 -+[ ]+120000008:[ ]+4ffffc21[ ]+jirl[ ]+\$ra, \$ra, -4 -+[ ]+12000000c:[ ]+50000200[ ]+b[ ]+-134217728[ ]+# 11800000c -+[ ]+120000010:[ ]+1fffc00c[ ]+pcaddu18i[ ]+\$t0, -512 -+[ ]+120000014:[ ]+4ffffd80[ ]+jirl[ ]+\$zero, \$t0, -4 -+[ ]+120000018:[ ]+1e004001[ ]+pcaddu18i[ ]+\$ra, 512 -+[ ]+12000001c:[ ]+4c000421[ ]+jirl[ ]+\$ra, \$ra, 4 -+[ ]+120000020:[ ]+57fffdff[ ]+bl[ ]+134217724[ ]+# 12800001c -+[ ]+120000024:[ ]+1e00400c[ ]+pcaddu18i[ ]+\$t0, 512 -+[ ]+120000028:[ ]+4c000580[ ]+jirl[ ]+\$zero, \$t0, 4 -+[ ]+12000002c:[ ]+53fffdff[ ]+b[ ]+134217724[ ]+# 128000028 -diff --git a/ld/testsuite/ld-loongarch-elf/relax-medium-call.s b/ld/testsuite/ld-loongarch-elf/relax-medium-call.s -new file mode 100644 -index 00000000..c0521b65 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/relax-medium-call.s -@@ -0,0 +1,35 @@ -+.section "ta", "ax" -+a: -+ ret -+ ret -+ ret -+b: -+ ret -+ -+.text -+ call36 a # min offset, can relax -+ call36 a # overflow, not relax -+ tail36 $t0, b # min offset, can relax -+ tail36 $t0, b # overflow, not relax -+ -+ call36 c # overflow, not relax -+ call36 c # max offset, can relax -+ tail36 $t0, d # overflow, no relax -+ tail36 $t0, d # max offset, can relax -+ -+.section "tb", "ax" -+ ret -+ ret -+ ret -+ ret -+ ret -+ ret -+ ret -+ ret -+c: -+ ret -+ ret -+ ret -+d: -+ ret -+ --- -2.33.0 - diff --git a/LoongArch-Add-support-for-OUTPUT_FORMAT-binary.patch b/LoongArch-Add-support-for-OUTPUT_FORMAT-binary.patch deleted file mode 100644 index 35c5857..0000000 --- a/LoongArch-Add-support-for-OUTPUT_FORMAT-binary.patch +++ /dev/null @@ -1,124 +0,0 @@ -From 2d1db1c7427598dbabc93b7d47b01a1aa5e2cec0 Mon Sep 17 00:00:00 2001 -From: mengqinggang -Date: Fri, 28 Jun 2024 14:24:19 +0800 -Subject: [PATCH 105/123] LoongArch: Add support for OUTPUT_FORMAT("binary") - -In binary output format, loongarch_elf_hash_table return NULL and result -in segment fault. - -When ld output binary file, it seems that elf related functions should -not be called. But loongarch_elf_relax_section be called and -loongarch_elf_hash_table cause segment fault. - -Just redefined loongarch_elf_hash_table and always return -link_info->hash. - -The tests of binutils, glibc and gcc is ok. - -0 loongarch_elf_relax_section () -1 0x000055555557ab28 in lang_size_sections_1 () -2 0x000055555557a16c in lang_size_sections_1 () -3 0x000055555557b0a8 in one_lang_size_sections_pass () -4 0x000055555557b478 in lang_size_sections () -5 0x000055555557e65c in lang_relax_sections () -6 0x000055555559f9c8 in ldelf_map_segments () -7 0x000055555559783c in gldelf64loongarch_after_allocation () -8 0x000055555558dac0 in ldemul_after_allocation () -9 0x000055555557f6c0 in lang_process () -10 0x0000555555585314 in main () ---- - bfd/elfnn-loongarch.c | 4 +--- - ld/emultempl/loongarchelf.em | 16 ---------------- - ld/testsuite/ld-loongarch-elf/binary.ld | 1 + - ld/testsuite/ld-loongarch-elf/binary.s | 4 ++++ - .../ld-loongarch-elf/ld-loongarch-elf.exp | 12 ++++++++++++ - 5 files changed, 18 insertions(+), 19 deletions(-) - create mode 100644 ld/testsuite/ld-loongarch-elf/binary.ld - create mode 100644 ld/testsuite/ld-loongarch-elf/binary.s - -diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c -index af4d8baa..c2468443 100644 ---- a/bfd/elfnn-loongarch.c -+++ b/bfd/elfnn-loongarch.c -@@ -157,9 +157,7 @@ loongarch_elf_new_section_hook (bfd *abfd, asection *sec) - - /* Get the LoongArch ELF linker hash table from a link_info structure. */ - #define loongarch_elf_hash_table(p) \ -- (elf_hash_table_id (elf_hash_table (p)) == LARCH_ELF_DATA \ -- ? ((struct loongarch_elf_link_hash_table *) ((p)->hash)) \ -- : NULL) -+ ((struct loongarch_elf_link_hash_table *) ((p)->hash)) \ - - #define MINUS_ONE ((bfd_vma) 0 - 1) - -diff --git a/ld/emultempl/loongarchelf.em b/ld/emultempl/loongarchelf.em -index 13f8dacb..2e6b8080 100644 ---- a/ld/emultempl/loongarchelf.em -+++ b/ld/emultempl/loongarchelf.em -@@ -102,23 +102,7 @@ gld${EMULATION_NAME}_after_allocation (void) - ldelf_map_segments (need_layout); - } - --/* This is a convenient point to tell BFD about target specific flags. -- After the output has been created, but before inputs are read. */ -- --static void --larch_create_output_section_statements (void) --{ -- /* See PR 22920 for an example of why this is necessary. */ -- if (strstr (bfd_get_target (link_info.output_bfd), "loong") == NULL) -- { -- einfo (_("%F%P: error: cannot change output format" -- " whilst linking %s binaries\n"), "LoongArch"); -- return; -- } --} -- - EOF - - LDEMUL_BEFORE_ALLOCATION=larch_elf_before_allocation - LDEMUL_AFTER_ALLOCATION=gld${EMULATION_NAME}_after_allocation --LDEMUL_CREATE_OUTPUT_SECTION_STATEMENTS=larch_create_output_section_statements -diff --git a/ld/testsuite/ld-loongarch-elf/binary.ld b/ld/testsuite/ld-loongarch-elf/binary.ld -new file mode 100644 -index 00000000..73cd4f2c ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/binary.ld -@@ -0,0 +1 @@ -+OUTPUT_FORMAT(binary); -diff --git a/ld/testsuite/ld-loongarch-elf/binary.s b/ld/testsuite/ld-loongarch-elf/binary.s -new file mode 100644 -index 00000000..b0aeb62a ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/binary.s -@@ -0,0 +1,4 @@ -+.text -+ ret -+.data -+ .4byte 0x12345678 -diff --git a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -index 032b9bad..232e7c20 100644 ---- a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -+++ b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -@@ -118,6 +118,18 @@ if [istarget "loongarch64-*-*"] { - "abi1_max_imm" \ - ] \ - ] -+ -+ run_ld_link_tests \ -+ [list \ -+ [list \ -+ "binary output format" \ -+ "-T binary.ld" "" \ -+ "" \ -+ {binary.s} \ -+ {} \ -+ "a.binary" \ -+ ] \ -+ ] - } - - if [istarget "loongarch64-*-*"] { --- -2.33.0 - diff --git a/LoongArch-Add-support-for-TLS-LD-GD-DESC-relaxation.patch b/LoongArch-Add-support-for-TLS-LD-GD-DESC-relaxation.patch deleted file mode 100644 index 631df74..0000000 --- a/LoongArch-Add-support-for-TLS-LD-GD-DESC-relaxation.patch +++ /dev/null @@ -1,1611 +0,0 @@ -From b71b59b2ff4e169cbed791a1738ba7ac40e1ed49 Mon Sep 17 00:00:00 2001 -From: mengqinggang -Date: Mon, 11 Dec 2023 16:08:20 +0800 -Subject: [PATCH 028/123] LoongArch: Add support for TLS LD/GD/DESC relaxation - -The pcalau12i + addi.d of TLS LD/GD/DESC relax to pcaddi. -Relaxation is only performed when the TLS model transition is not possible. ---- - bfd/bfd-in2.h | 3 + - bfd/elfnn-loongarch.c | 174 +++++++- - bfd/elfxx-loongarch.c | 60 +++ - bfd/libbfd.h | 3 + - bfd/reloc.c | 7 + - gas/config/tc-loongarch.c | 8 +- - gas/testsuite/gas/loongarch/macro_op.d | 128 +++--- - gas/testsuite/gas/loongarch/macro_op_32.d | 120 +++--- - .../gas/loongarch/macro_op_large_abs.d | 160 +++---- - .../gas/loongarch/macro_op_large_pc.d | 160 +++---- - include/elf/loongarch.h | 4 + - ld/testsuite/ld-loongarch-elf/macro_op.d | 391 +++++++++--------- - ld/testsuite/ld-loongarch-elf/macro_op_32.d | 120 +++--- - 13 files changed, 795 insertions(+), 543 deletions(-) - -diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h -index d210e71b..d7b762d4 100644 ---- a/bfd/bfd-in2.h -+++ b/bfd/bfd-in2.h -@@ -7356,6 +7356,9 @@ assembler and not (currently) written to any object files. */ - BFD_RELOC_LARCH_TLS_DESC64_HI12, - BFD_RELOC_LARCH_TLS_DESC_LD, - BFD_RELOC_LARCH_TLS_DESC_CALL, -+ BFD_RELOC_LARCH_TLS_LD_PCREL20_S2, -+ BFD_RELOC_LARCH_TLS_GD_PCREL20_S2, -+ BFD_RELOC_LARCH_TLS_DESC_PCREL20_S2, - BFD_RELOC_UNUSED - }; - typedef enum bfd_reloc_code_real bfd_reloc_code_real_type; -diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c -index 13fddd63..d46bcd77 100644 ---- a/bfd/elfnn-loongarch.c -+++ b/bfd/elfnn-loongarch.c -@@ -2285,7 +2285,9 @@ perform_relocation (const Elf_Internal_Rela *rel, asection *input_section, - case R_LARCH_TLS_DESC_LO12: - case R_LARCH_TLS_DESC64_LO20: - case R_LARCH_TLS_DESC64_HI12: -- -+ case R_LARCH_TLS_LD_PCREL20_S2: -+ case R_LARCH_TLS_GD_PCREL20_S2: -+ case R_LARCH_TLS_DESC_PCREL20_S2: - r = loongarch_check_offset (rel, input_section); - if (r != bfd_reloc_ok) - break; -@@ -3667,6 +3669,9 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, - case R_LARCH_TLS_GD_HI20: - case R_LARCH_TLS_DESC_PC_HI20: - case R_LARCH_TLS_DESC_HI20: -+ case R_LARCH_TLS_LD_PCREL20_S2: -+ case R_LARCH_TLS_GD_PCREL20_S2: -+ case R_LARCH_TLS_DESC_PCREL20_S2: - BFD_ASSERT (rel->r_addend == 0); - unresolved_reloc = false; - -@@ -3675,7 +3680,8 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, - is_ie = true; - - if (r_type == R_LARCH_TLS_DESC_PC_HI20 -- || r_type == R_LARCH_TLS_DESC_HI20) -+ || r_type == R_LARCH_TLS_DESC_HI20 -+ || r_type == R_LARCH_TLS_DESC_PCREL20_S2) - is_desc = true; - - bfd_vma got_off = 0; -@@ -3806,7 +3812,11 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, - || r_type == R_LARCH_TLS_IE_PC_HI20 - || r_type == R_LARCH_TLS_DESC_PC_HI20) - RELOCATE_CALC_PC32_HI20 (relocation, pc); -- -+ else if (r_type == R_LARCH_TLS_LD_PCREL20_S2 -+ || r_type == R_LARCH_TLS_GD_PCREL20_S2 -+ || r_type == R_LARCH_TLS_DESC_PCREL20_S2) -+ relocation -= pc; -+ /* else {} ABS relocations. */ - break; - - case R_LARCH_TLS_DESC_PC_LO12: -@@ -4237,6 +4247,85 @@ loongarch_relax_align (bfd *abfd, asection *sec, - addend - need_nop_bytes, link_info); - } - -+/* Relax pcalau12i + addi.d of TLS LD/GD/DESC to pcaddi. */ -+static bool -+loongarch_relax_tls_ld_gd_desc (bfd *abfd, asection *sec, asection *sym_sec, -+ Elf_Internal_Rela *rel_hi, bfd_vma symval, -+ struct bfd_link_info *info, bool *again) -+{ -+ bfd_byte *contents = elf_section_data (sec)->this_hdr.contents; -+ Elf_Internal_Rela *rel_lo = rel_hi + 2; -+ uint32_t pca = bfd_get (32, abfd, contents + rel_hi->r_offset); -+ uint32_t add = bfd_get (32, abfd, contents + rel_lo->r_offset); -+ uint32_t rd = pca & 0x1f; -+ -+ /* This section's output_offset need to subtract the bytes of instructions -+ relaxed by the previous sections, so it needs to be updated beforehand. -+ size_input_section already took care of updating it after relaxation, -+ so we additionally update once here. */ -+ sec->output_offset = sec->output_section->size; -+ bfd_vma pc = sec_addr (sec) + rel_hi->r_offset; -+ -+ /* If pc and symbol not in the same segment, add/sub segment alignment. -+ FIXME: if there are multiple readonly segments? */ -+ if (!(sym_sec->flags & SEC_READONLY)) -+ { -+ if (symval > pc) -+ pc -= info->maxpagesize; -+ else if (symval < pc) -+ pc += info->maxpagesize; -+ } -+ -+ const uint32_t addi_d = 0x02c00000; -+ const uint32_t pcaddi = 0x18000000; -+ -+ /* Is pcalau12i + addi.d insns? */ -+ if ((ELFNN_R_TYPE (rel_lo->r_info) != R_LARCH_GOT_PC_LO12 -+ && ELFNN_R_TYPE (rel_lo->r_info) != R_LARCH_TLS_DESC_PC_LO12) -+ || (ELFNN_R_TYPE ((rel_lo + 1)->r_info) != R_LARCH_RELAX) -+ || (ELFNN_R_TYPE ((rel_hi + 1)->r_info) != R_LARCH_RELAX) -+ || (rel_hi->r_offset + 4 != rel_lo->r_offset) -+ || ((add & addi_d) != addi_d) -+ /* Is pcalau12i $rd + addi.d $rd,$rd? */ -+ || ((add & 0x1f) != rd) -+ || (((add >> 5) & 0x1f) != rd) -+ /* Can be relaxed to pcaddi? */ -+ || (symval & 0x3) /* 4 bytes align. */ -+ || ((bfd_signed_vma)(symval - pc) < (bfd_signed_vma)(int32_t)0xffe00000) -+ || ((bfd_signed_vma)(symval - pc) > (bfd_signed_vma)(int32_t)0x1ffffc)) -+ return false; -+ -+ /* Continue next relax trip. */ -+ *again = true; -+ -+ pca = pcaddi | rd; -+ bfd_put (32, abfd, pca, contents + rel_hi->r_offset); -+ -+ /* Adjust relocations. */ -+ switch (ELFNN_R_TYPE (rel_hi->r_info)) -+ { -+ case R_LARCH_TLS_LD_PC_HI20: -+ rel_hi->r_info = ELFNN_R_INFO (ELFNN_R_SYM (rel_hi->r_info), -+ R_LARCH_TLS_LD_PCREL20_S2); -+ break; -+ case R_LARCH_TLS_GD_PC_HI20: -+ rel_hi->r_info = ELFNN_R_INFO (ELFNN_R_SYM (rel_hi->r_info), -+ R_LARCH_TLS_GD_PCREL20_S2); -+ break; -+ case R_LARCH_TLS_DESC_PC_HI20: -+ rel_hi->r_info = ELFNN_R_INFO (ELFNN_R_SYM (rel_hi->r_info), -+ R_LARCH_TLS_DESC_PCREL20_S2); -+ break; -+ default: -+ break; -+ } -+ rel_lo->r_info = ELFNN_R_INFO (0, R_LARCH_NONE); -+ -+ loongarch_relax_delete_bytes (abfd, sec, rel_lo->r_offset, 4, info); -+ -+ return true; -+} -+ - static bool - loongarch_elf_relax_section (bfd *abfd, asection *sec, - struct bfd_link_info *info, -@@ -4281,15 +4370,23 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, - - for (unsigned int i = 0; i < sec->reloc_count; i++) - { -- Elf_Internal_Rela *rel = relocs + i; -- asection *sym_sec; -+ char symtype; - bfd_vma symval; -- unsigned long r_symndx = ELFNN_R_SYM (rel->r_info); -- unsigned long r_type = ELFNN_R_TYPE (rel->r_info); -+ asection *sym_sec; - bool local_got = false; -- char symtype; -+ Elf_Internal_Rela *rel = relocs + i; - struct elf_link_hash_entry *h = NULL; -+ unsigned long r_type = ELFNN_R_TYPE (rel->r_info); -+ unsigned long r_symndx = ELFNN_R_SYM (rel->r_info); - -+ /* Four kind of relocations: -+ Normal: symval is the symbol address. -+ R_LARCH_ALIGN: symval is the address of the last NOP instruction -+ added by this relocation, and then adds 4 more. -+ R_LARCH_CALL36: symval is the symbol address for local symbols, -+ or the PLT entry address of the symbol. (Todo) -+ R_LARCHL_TLS_LD/GD/DESC_PC_HI20: symval is the GOT entry address -+ of the symbol. */ - if (r_symndx < symtab_hdr->sh_info) - { - Elf_Internal_Sym *sym = (Elf_Internal_Sym *)symtab_hdr->contents -@@ -4297,7 +4394,24 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, - if (ELF_ST_TYPE (sym->st_info) == STT_GNU_IFUNC) - continue; - -- if (sym->st_shndx == SHN_UNDEF || R_LARCH_ALIGN == r_type) -+ if (R_LARCH_TLS_LD_PC_HI20 == r_type -+ || R_LARCH_TLS_GD_PC_HI20 == r_type -+ || R_LARCH_TLS_DESC_PC_HI20 == r_type) -+ { -+ if (loongarch_can_relax_tls (info, r_type, h, abfd, r_symndx)) -+ continue; -+ else -+ { -+ sym_sec = htab->elf.sgot; -+ symval = elf_local_got_offsets (abfd)[r_symndx]; -+ char tls_type = _bfd_loongarch_elf_tls_type (abfd, h, -+ r_symndx); -+ if (R_LARCH_TLS_DESC_PC_HI20 == r_type -+ && GOT_TLS_GD_BOTH_P (tls_type)) -+ symval += 2 * GOT_ENTRY_SIZE; -+ } -+ } -+ else if (sym->st_shndx == SHN_UNDEF || R_LARCH_ALIGN == r_type) - { - sym_sec = sec; - symval = rel->r_offset; -@@ -4322,7 +4436,26 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, - if (h != NULL && h->type == STT_GNU_IFUNC) - continue; - -- if ((h->root.type == bfd_link_hash_defined -+ /* The GOT entry of tls symbols must in current execute file or -+ shared object. */ -+ if (R_LARCH_TLS_LD_PC_HI20 == r_type -+ || R_LARCH_TLS_GD_PC_HI20 == r_type -+ || R_LARCH_TLS_DESC_PC_HI20 == r_type) -+ { -+ if (loongarch_can_relax_tls (info, r_type, h, abfd, r_symndx)) -+ continue; -+ else -+ { -+ sym_sec = htab->elf.sgot; -+ symval = h->got.offset; -+ char tls_type = _bfd_loongarch_elf_tls_type (abfd, h, -+ r_symndx); -+ if (R_LARCH_TLS_DESC_PC_HI20 == r_type -+ && GOT_TLS_GD_BOTH_P (tls_type)) -+ symval += 2 * GOT_ENTRY_SIZE; -+ } -+ } -+ else if ((h->root.type == bfd_link_hash_defined - || h->root.type == bfd_link_hash_defweak) - && h->root.u.def.section != NULL - && h->root.u.def.section->output_section != NULL) -@@ -4351,7 +4484,7 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, - if (symtype != STT_SECTION) - symval += rel->r_addend; - } -- /* For R_LARCH_ALIGN, symval is sec_addr (sym_sec) + rel->r_offset -+ /* For R_LARCH_ALIGN, symval is sec_addr (sec) + rel->r_offset - + (alingmeng - 4). - If r_symndx is 0, alignmeng-4 is r_addend. - If r_symndx > 0, alignment-4 is 2^(r_addend & 0xff)-4. */ -@@ -4392,6 +4525,25 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, - info, again); - } - break; -+ -+ case R_LARCH_TLS_LD_PC_HI20: -+ if (0 == info->relax_pass && (i + 4) <= sec->reloc_count) -+ loongarch_relax_tls_ld_gd_desc (abfd, sec, sym_sec, rel, symval, -+ info, again); -+ break; -+ -+ case R_LARCH_TLS_GD_PC_HI20: -+ if (0 == info->relax_pass && (i + 4) <= sec->reloc_count) -+ loongarch_relax_tls_ld_gd_desc (abfd, sec, sym_sec, rel, symval, -+ info, again); -+ break; -+ -+ case R_LARCH_TLS_DESC_PC_HI20: -+ if (0 == info->relax_pass && (i + 4) <= sec->reloc_count) -+ loongarch_relax_tls_ld_gd_desc (abfd, sec, sym_sec, rel, symval, -+ info, again); -+ break; -+ - default: - break; - } -diff --git a/bfd/elfxx-loongarch.c b/bfd/elfxx-loongarch.c -index 30a941a8..310e6d62 100644 ---- a/bfd/elfxx-loongarch.c -+++ b/bfd/elfxx-loongarch.c -@@ -1775,6 +1775,60 @@ static loongarch_reloc_howto_type loongarch_howto_table[] = - BFD_RELOC_LARCH_TLS_DESC_CALL, /* bfd_reloc_code_real_type. */ - NULL, /* adjust_reloc_bits. */ - "desc_call"), /* larch_reloc_type_name. */ -+ -+ /* For pcaddi, ld_pc_hi20 + ld_pc_lo12 can relax to ld_pcrel20_s2. */ -+ LOONGARCH_HOWTO (R_LARCH_TLS_LD_PCREL20_S2, /* type (124). */ -+ 2, /* rightshift. */ -+ 4, /* size. */ -+ 20, /* bitsize. */ -+ false, /* pc_relative. */ -+ 5, /* bitpos. */ -+ complain_overflow_signed, /* complain_on_overflow. */ -+ bfd_elf_generic_reloc, /* special_function. */ -+ "R_LARCH_TLS_LD_PCREL20_S2", /* name. */ -+ false, /* partial_inplace. */ -+ 0, /* src_mask. */ -+ 0x1ffffe0, /* dst_mask. */ -+ true, /* pcrel_offset. */ -+ BFD_RELOC_LARCH_TLS_LD_PCREL20_S2, /* bfd_reloc_code_real_type. */ -+ reloc_sign_bits, /* adjust_reloc_bits. */ -+ "ld_pcrel_20"), /* larch_reloc_type_name. */ -+ -+ /* For pcaddi, gd_pc_hi20 + gd_pc_lo12 can relax to gd_pcrel20_s2. */ -+ LOONGARCH_HOWTO (R_LARCH_TLS_GD_PCREL20_S2, /* type (125). */ -+ 2, /* rightshift. */ -+ 4, /* size. */ -+ 20, /* bitsize. */ -+ false, /* pc_relative. */ -+ 5, /* bitpos. */ -+ complain_overflow_signed, /* complain_on_overflow. */ -+ bfd_elf_generic_reloc, /* special_function. */ -+ "R_LARCH_TLS_GD_PCREL20_S2", /* name. */ -+ false, /* partial_inplace. */ -+ 0, /* src_mask. */ -+ 0x1ffffe0, /* dst_mask. */ -+ true, /* pcrel_offset. */ -+ BFD_RELOC_LARCH_TLS_GD_PCREL20_S2, /* bfd_reloc_code_real_type. */ -+ reloc_sign_bits, /* adjust_reloc_bits. */ -+ "gd_pcrel_20"), /* larch_reloc_type_name. */ -+ -+ /* For pcaddi, desc_pc_hi20 + desc_pc_lo12 can relax to desc_pcrel20_s2. */ -+ LOONGARCH_HOWTO (R_LARCH_TLS_DESC_PCREL20_S2, /* type (126). */ -+ 2, /* rightshift. */ -+ 4, /* size. */ -+ 20, /* bitsize. */ -+ false, /* pc_relative. */ -+ 5, /* bitpos. */ -+ complain_overflow_signed, /* complain_on_overflow. */ -+ bfd_elf_generic_reloc, /* special_function. */ -+ "R_LARCH_TLS_DESC_PCREL20_S2", /* name. */ -+ false, /* partial_inplace. */ -+ 0, /* src_mask. */ -+ 0x1ffffe0, /* dst_mask. */ -+ true, /* pcrel_offset. */ -+ BFD_RELOC_LARCH_TLS_DESC_PCREL20_S2, /* bfd_reloc_code_real_type. */ -+ reloc_sign_bits, /* adjust_reloc_bits. */ -+ "desc_pcrel_20"), /* larch_reloc_type_name. */ - }; - - reloc_howto_type * -@@ -1783,7 +1837,9 @@ loongarch_elf_rtype_to_howto (bfd *abfd, unsigned int r_type) - if(r_type < R_LARCH_count) - { - /* For search table fast. */ -+ /* - BFD_ASSERT (ARRAY_SIZE (loongarch_howto_table) == R_LARCH_count); -+ */ - - if (loongarch_howto_table[r_type].howto.type == r_type) - return (reloc_howto_type *)&loongarch_howto_table[r_type]; -@@ -1802,7 +1858,9 @@ loongarch_elf_rtype_to_howto (bfd *abfd, unsigned int r_type) - reloc_howto_type * - loongarch_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED, const char *r_name) - { -+ /* - BFD_ASSERT (ARRAY_SIZE (loongarch_howto_table) == R_LARCH_count); -+ */ - - for (size_t i = 0; i < ARRAY_SIZE (loongarch_howto_table); i++) - if (loongarch_howto_table[i].howto.name -@@ -1821,7 +1879,9 @@ reloc_howto_type * - loongarch_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED, - bfd_reloc_code_real_type code) - { -+ /* - BFD_ASSERT (ARRAY_SIZE (loongarch_howto_table) == R_LARCH_count); -+ */ - - /* Fast search for new reloc types. */ - if (BFD_RELOC_LARCH_B16 <= code && code < BFD_RELOC_LARCH_RELAX) -diff --git a/bfd/libbfd.h b/bfd/libbfd.h -index a474b971..b5af327f 100644 ---- a/bfd/libbfd.h -+++ b/bfd/libbfd.h -@@ -3538,6 +3538,9 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@", - "BFD_RELOC_LARCH_TLS_DESC64_HI12", - "BFD_RELOC_LARCH_TLS_DESC_LD", - "BFD_RELOC_LARCH_TLS_DESC_CALL", -+ "BFD_RELOC_LARCH_TLS_LD_PCREL20_S2", -+ "BFD_RELOC_LARCH_TLS_GD_PCREL20_S2", -+ "BFD_RELOC_LARCH_TLS_DESC_PCREL20_S2", - "@@overflow: BFD_RELOC_UNUSED@@", - }; - #endif -diff --git a/bfd/reloc.c b/bfd/reloc.c -index 5af98afb..4782f0f6 100644 ---- a/bfd/reloc.c -+++ b/bfd/reloc.c -@@ -8188,6 +8188,13 @@ ENUMX - ENUMX - BFD_RELOC_LARCH_TLS_DESC_CALL - -+ENUMX -+ BFD_RELOC_LARCH_TLS_LD_PCREL20_S2 -+ENUMX -+ BFD_RELOC_LARCH_TLS_GD_PCREL20_S2 -+ENUMX -+ BFD_RELOC_LARCH_TLS_DESC_PCREL20_S2 -+ - ENUMDOC - LARCH relocations. - -diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c -index 1658025f..def26daf 100644 ---- a/gas/config/tc-loongarch.c -+++ b/gas/config/tc-loongarch.c -@@ -682,7 +682,7 @@ loongarch_args_parser_can_match_arg_helper (char esc_ch1, char esc_ch2, - esc_ch1, esc_ch2, bit_field, arg); - - if (ip->reloc_info[0].type >= BFD_RELOC_LARCH_B16 -- && ip->reloc_info[0].type <= BFD_RELOC_LARCH_TLS_DESC_CALL) -+ && ip->reloc_info[0].type <= BFD_RELOC_LARCH_TLS_DESC_PCREL20_S2) - { - /* As we compact stack-relocs, it is no need for pop operation. - But break out until here in order to check the imm field. -@@ -694,7 +694,11 @@ loongarch_args_parser_can_match_arg_helper (char esc_ch1, char esc_ch2, - && (BFD_RELOC_LARCH_PCALA_HI20 == reloc_type - || BFD_RELOC_LARCH_PCALA_LO12 == reloc_type - || BFD_RELOC_LARCH_GOT_PC_HI20 == reloc_type -- || BFD_RELOC_LARCH_GOT_PC_LO12 == reloc_type)) -+ || BFD_RELOC_LARCH_GOT_PC_LO12 == reloc_type -+ || BFD_RELOC_LARCH_TLS_LD_PC_HI20 == reloc_type -+ || BFD_RELOC_LARCH_TLS_GD_PC_HI20 == reloc_type -+ || BFD_RELOC_LARCH_TLS_DESC_PC_HI20 == reloc_type -+ || BFD_RELOC_LARCH_TLS_DESC_PC_LO12 == reloc_type)) - { - ip->reloc_info[ip->reloc_num].type = BFD_RELOC_LARCH_RELAX; - ip->reloc_info[ip->reloc_num].value = const_0; -diff --git a/gas/testsuite/gas/loongarch/macro_op.d b/gas/testsuite/gas/loongarch/macro_op.d -index 32860864..47f8f45c 100644 ---- a/gas/testsuite/gas/loongarch/macro_op.d -+++ b/gas/testsuite/gas/loongarch/macro_op.d -@@ -2,70 +2,72 @@ - #objdump: -dr - #skip: loongarch32-*-* - --.*:[ ]+file format .* -+.*: file format .* - - - Disassembly of section .text: - --00000000.* <.text>: --[ ]+0:[ ]+00150004[ ]+move[ ]+\$a0,[ ]+\$zero --[ ]+4:[ ]+02bffc04[ ]+li\.w[ ]+\$a0,[ ]+-1 --[ ]+8:[ ]+00150004[ ]+move[ ]+\$a0,[ ]+\$zero --[ ]+c:[ ]+02bffc04[ ]+li\.w[ ]+\$a0,[ ]+-1 --[ ]+10:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+10:[ ]+R_LARCH_GOT_PC_HI20[ ]+\.L1 --[ ]+10:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+14:[ ]+28c00084[ ]+ld\.d[ ]+\$a0,[ ]+\$a0,[ ]+0 --[ ]+14:[ ]+R_LARCH_GOT_PC_LO12[ ]+\.L1 --[ ]+14:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+18:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+18:[ ]+R_LARCH_GOT_PC_HI20[ ]+\.L1 --[ ]+18:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+1c:[ ]+28c00084[ ]+ld\.d[ ]+\$a0,[ ]+\$a0,[ ]+0 --[ ]+1c:[ ]+R_LARCH_GOT_PC_LO12[ ]+\.L1 --[ ]+1c:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+20:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+20:[ ]+R_LARCH_PCALA_HI20[ ]+\.L1 --[ ]+20:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+24:[ ]+02c00084[ ]+addi\.d[ ]+\$a0,[ ]+\$a0,[ ]+0 --[ ]+24:[ ]+R_LARCH_PCALA_LO12[ ]+\.L1 --[ ]+24:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+28:[ ]+14000004[ ]+lu12i\.w[ ]+\$a0,[ ]+0 --[ ]+28:[ ]+R_LARCH_MARK_LA[ ]+\*ABS\* --[ ]+28:[ ]+R_LARCH_ABS_HI20[ ]+\.L1 --[ ]+2c:[ ]+03800084[ ]+ori[ ]+\$a0,[ ]+\$a0,[ ]+0x0 --[ ]+2c:[ ]+R_LARCH_ABS_LO12[ ]+\.L1 --[ ]+30:[ ]+16000004[ ]+lu32i\.d[ ]+\$a0,[ ]+0 --[ ]+30:[ ]+R_LARCH_ABS64_LO20[ ]+\.L1 --[ ]+34:[ ]+03000084[ ]+lu52i\.d[ ]+\$a0,[ ]+\$a0,[ ]+0 --[ ]+34:[ ]+R_LARCH_ABS64_HI12[ ]+\.L1 --[ ]+38:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+38:[ ]+R_LARCH_PCALA_HI20[ ]+\.L1 --[ ]+38:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+3c:[ ]+02c00084[ ]+addi\.d[ ]+\$a0,[ ]+\$a0,[ ]+0 --[ ]+3c:[ ]+R_LARCH_PCALA_LO12[ ]+\.L1 --[ ]+3c:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+40:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+40:[ ]+R_LARCH_GOT_PC_HI20[ ]+\.L1 --[ ]+40:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+44:[ ]+28c00084[ ]+ld\.d[ ]+\$a0,[ ]+\$a0,[ ]+0 --[ ]+44:[ ]+R_LARCH_GOT_PC_LO12[ ]+\.L1 --[ ]+44:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+48:[ ]+14000004[ ]+lu12i\.w[ ]+\$a0,[ ]+0 --[ ]+48:[ ]+R_LARCH_TLS_LE_HI20[ ]+TLS1 --[ ]+4c:[ ]+03800084[ ]+ori[ ]+\$a0,[ ]+\$a0,[ ]+0x0 --[ ]+4c:[ ]+R_LARCH_TLS_LE_LO12[ ]+TLS1 --[ ]+50:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+50:[ ]+R_LARCH_TLS_IE_PC_HI20[ ]+TLS1 --[ ]+54:[ ]+28c00084[ ]+ld\.d[ ]+\$a0,[ ]+\$a0,[ ]+0 --[ ]+54:[ ]+R_LARCH_TLS_IE_PC_LO12[ ]+TLS1 --[ ]+58:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+58:[ ]+R_LARCH_TLS_LD_PC_HI20[ ]+TLS1 --[ ]+5c:[ ]+02c00084[ ]+addi\.d[ ]+\$a0,[ ]+\$a0,[ ]+0 --[ ]+5c:[ ]+R_LARCH_GOT_PC_LO12[ ]+TLS1 --[ ]+5c:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+60:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+60:[ ]+R_LARCH_TLS_GD_PC_HI20[ ]+TLS1 --[ ]+64:[ ]+02c00084[ ]+addi\.d[ ]+\$a0,[ ]+\$a0,[ ]+0 --[ ]+64:[ ]+R_LARCH_GOT_PC_LO12[ ]+TLS1 --[ ]+64:[ ]+R_LARCH_RELAX[ ]+\*ABS\* -+0+ <.*>: -+ 0: 00150004 move \$a0, \$zero -+ 4: 02bffc04 li.w \$a0, -1 -+ 8: 00150004 move \$a0, \$zero -+ c: 02bffc04 li.w \$a0, -1 -+ 10: 1a000004 pcalau12i \$a0, 0 -+ 10: R_LARCH_GOT_PC_HI20 .L1 -+ 10: R_LARCH_RELAX \*ABS\* -+ 14: 28c00084 ld.d \$a0, \$a0, 0 -+ 14: R_LARCH_GOT_PC_LO12 .L1 -+ 14: R_LARCH_RELAX \*ABS\* -+ 18: 1a000004 pcalau12i \$a0, 0 -+ 18: R_LARCH_GOT_PC_HI20 .L1 -+ 18: R_LARCH_RELAX \*ABS\* -+ 1c: 28c00084 ld.d \$a0, \$a0, 0 -+ 1c: R_LARCH_GOT_PC_LO12 .L1 -+ 1c: R_LARCH_RELAX \*ABS\* -+ 20: 1a000004 pcalau12i \$a0, 0 -+ 20: R_LARCH_PCALA_HI20 .L1 -+ 20: R_LARCH_RELAX \*ABS\* -+ 24: 02c00084 addi.d \$a0, \$a0, 0 -+ 24: R_LARCH_PCALA_LO12 .L1 -+ 24: R_LARCH_RELAX \*ABS\* -+ 28: 14000004 lu12i.w \$a0, 0 -+ 28: R_LARCH_MARK_LA \*ABS\* -+ 28: R_LARCH_ABS_HI20 .L1 -+ 2c: 03800084 ori \$a0, \$a0, 0x0 -+ 2c: R_LARCH_ABS_LO12 .L1 -+ 30: 16000004 lu32i.d \$a0, 0 -+ 30: R_LARCH_ABS64_LO20 .L1 -+ 34: 03000084 lu52i.d \$a0, \$a0, 0 -+ 34: R_LARCH_ABS64_HI12 .L1 -+ 38: 1a000004 pcalau12i \$a0, 0 -+ 38: R_LARCH_PCALA_HI20 .L1 -+ 38: R_LARCH_RELAX \*ABS\* -+ 3c: 02c00084 addi.d \$a0, \$a0, 0 -+ 3c: R_LARCH_PCALA_LO12 .L1 -+ 3c: R_LARCH_RELAX \*ABS\* -+ 40: 1a000004 pcalau12i \$a0, 0 -+ 40: R_LARCH_GOT_PC_HI20 .L1 -+ 40: R_LARCH_RELAX \*ABS\* -+ 44: 28c00084 ld.d \$a0, \$a0, 0 -+ 44: R_LARCH_GOT_PC_LO12 .L1 -+ 44: R_LARCH_RELAX \*ABS\* -+ 48: 14000004 lu12i.w \$a0, 0 -+ 48: R_LARCH_TLS_LE_HI20 TLS1 -+ 4c: 03800084 ori \$a0, \$a0, 0x0 -+ 4c: R_LARCH_TLS_LE_LO12 TLS1 -+ 50: 1a000004 pcalau12i \$a0, 0 -+ 50: R_LARCH_TLS_IE_PC_HI20 TLS1 -+ 54: 28c00084 ld.d \$a0, \$a0, 0 -+ 54: R_LARCH_TLS_IE_PC_LO12 TLS1 -+ 58: 1a000004 pcalau12i \$a0, 0 -+ 58: R_LARCH_TLS_LD_PC_HI20 TLS1 -+ 58: R_LARCH_RELAX \*ABS\* -+ 5c: 02c00084 addi.d \$a0, \$a0, 0 -+ 5c: R_LARCH_GOT_PC_LO12 TLS1 -+ 5c: R_LARCH_RELAX \*ABS\* -+ 60: 1a000004 pcalau12i \$a0, 0 -+ 60: R_LARCH_TLS_GD_PC_HI20 TLS1 -+ 60: R_LARCH_RELAX \*ABS\* -+ 64: 02c00084 addi.d \$a0, \$a0, 0 -+ 64: R_LARCH_GOT_PC_LO12 TLS1 -+ 64: R_LARCH_RELAX \*ABS\* -diff --git a/gas/testsuite/gas/loongarch/macro_op_32.d b/gas/testsuite/gas/loongarch/macro_op_32.d -index 188026a5..a7349aa8 100644 ---- a/gas/testsuite/gas/loongarch/macro_op_32.d -+++ b/gas/testsuite/gas/loongarch/macro_op_32.d -@@ -2,66 +2,68 @@ - #objdump: -dr - #skip: loongarch64-*-* - --.*:[ ]+file format .* -+.*: file format .* - - - Disassembly of section .text: - --00000000.* <.L1>: --[ ]+0:[ ]+00150004[ ]+move[ ]+\$a0,[ ]+\$zero --[ ]+4:[ ]+02bffc04[ ]+li\.w[ ]+\$a0,[ ]+-1 --[ ]+8:[ ]+00150004[ ]+move[ ]+\$a0,[ ]+\$zero --[ ]+c:[ ]+02bffc04[ ]+li\.w[ ]+\$a0,[ ]+-1 --[ ]+10:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+10:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1 --[ ]+10:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+14:[ ]+28800084[ ]+ld.w[ ]+\$a0,[ ]+\$a0,[ ]+0 --[ ]+14:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1 --[ ]+14:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+18:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+18:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1 --[ ]+18:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+1c:[ ]+28800084[ ]+ld.w[ ]+\$a0,[ ]+\$a0,[ ]+0 --[ ]+1c:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1 --[ ]+1c:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+20:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+20:[ ]+R_LARCH_PCALA_HI20[ ]+.L1 --[ ]+20:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+24:[ ]+02800084[ ]+addi.w[ ]+\$a0,[ ]+\$a0,[ ]+0 --[ ]+24:[ ]+R_LARCH_PCALA_LO12[ ]+.L1 --[ ]+24:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+28:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0 --[ ]+28:[ ]+R_LARCH_MARK_LA[ ]+\*ABS\* --[ ]+28:[ ]+R_LARCH_ABS_HI20[ ]+.L1 --[ ]+2c:[ ]+03800084[ ]+ori[ ]+\$a0,[ ]+\$a0,[ ]+0x0 --[ ]+2c:[ ]+R_LARCH_ABS_LO12[ ]+.L1 --[ ]+30:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+30:[ ]+R_LARCH_PCALA_HI20[ ]+.L1 --[ ]+30:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+34:[ ]+02800084[ ]+addi.w[ ]+\$a0,[ ]+\$a0,[ ]+0 --[ ]+34:[ ]+R_LARCH_PCALA_LO12[ ]+.L1 --[ ]+34:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+38:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+38:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1 --[ ]+38:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+3c:[ ]+28800084[ ]+ld.w[ ]+\$a0,[ ]+\$a0,[ ]+0 --[ ]+3c:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1 --[ ]+3c:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+40:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0 --[ ]+40:[ ]+R_LARCH_TLS_LE_HI20[ ]+TLS1 --[ ]+44:[ ]+03800084[ ]+ori[ ]+\$a0,[ ]+\$a0,[ ]+0x0 --[ ]+44:[ ]+R_LARCH_TLS_LE_LO12[ ]+TLS1 --[ ]+48:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+48:[ ]+R_LARCH_TLS_IE_PC_HI20[ ]+TLS1 --[ ]+4c:[ ]+28800084[ ]+ld.w[ ]+\$a0,[ ]+\$a0,[ ]+0 --[ ]+4c:[ ]+R_LARCH_TLS_IE_PC_LO12[ ]+TLS1 --[ ]+50:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+50:[ ]+R_LARCH_TLS_LD_PC_HI20[ ]+TLS1 --[ ]+54:[ ]+02800084[ ]+addi.w[ ]+\$a0,[ ]+\$a0,[ ]+0 --[ ]+54:[ ]+R_LARCH_GOT_PC_LO12[ ]+TLS1 --[ ]+54:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+58:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+58:[ ]+R_LARCH_TLS_GD_PC_HI20[ ]+TLS1 --[ ]+5c:[ ]+02800084[ ]+addi.w[ ]+\$a0,[ ]+\$a0,[ ]+0 --[ ]+5c:[ ]+R_LARCH_GOT_PC_LO12[ ]+TLS1 --[ ]+5c:[ ]+R_LARCH_RELAX[ ]+\*ABS\* -+0+ <.L1>: -+ 0: 00150004 move \$a0, \$zero -+ 4: 02bffc04 li.w \$a0, -1 -+ 8: 00150004 move \$a0, \$zero -+ c: 02bffc04 li.w \$a0, -1 -+ 10: 1a000004 pcalau12i \$a0, 0 -+ 10: R_LARCH_GOT_PC_HI20 .L1 -+ 10: R_LARCH_RELAX \*ABS\* -+ 14: 28800084 ld.w \$a0, \$a0, 0 -+ 14: R_LARCH_GOT_PC_LO12 .L1 -+ 14: R_LARCH_RELAX \*ABS\* -+ 18: 1a000004 pcalau12i \$a0, 0 -+ 18: R_LARCH_GOT_PC_HI20 .L1 -+ 18: R_LARCH_RELAX \*ABS\* -+ 1c: 28800084 ld.w \$a0, \$a0, 0 -+ 1c: R_LARCH_GOT_PC_LO12 .L1 -+ 1c: R_LARCH_RELAX \*ABS\* -+ 20: 1a000004 pcalau12i \$a0, 0 -+ 20: R_LARCH_PCALA_HI20 .L1 -+ 20: R_LARCH_RELAX \*ABS\* -+ 24: 02800084 addi.w \$a0, \$a0, 0 -+ 24: R_LARCH_PCALA_LO12 .L1 -+ 24: R_LARCH_RELAX \*ABS\* -+ 28: 14000004 lu12i.w \$a0, 0 -+ 28: R_LARCH_MARK_LA \*ABS\* -+ 28: R_LARCH_ABS_HI20 .L1 -+ 2c: 03800084 ori \$a0, \$a0, 0x0 -+ 2c: R_LARCH_ABS_LO12 .L1 -+ 30: 1a000004 pcalau12i \$a0, 0 -+ 30: R_LARCH_PCALA_HI20 .L1 -+ 30: R_LARCH_RELAX \*ABS\* -+ 34: 02800084 addi.w \$a0, \$a0, 0 -+ 34: R_LARCH_PCALA_LO12 .L1 -+ 34: R_LARCH_RELAX \*ABS\* -+ 38: 1a000004 pcalau12i \$a0, 0 -+ 38: R_LARCH_GOT_PC_HI20 .L1 -+ 38: R_LARCH_RELAX \*ABS\* -+ 3c: 28800084 ld.w \$a0, \$a0, 0 -+ 3c: R_LARCH_GOT_PC_LO12 .L1 -+ 3c: R_LARCH_RELAX \*ABS\* -+ 40: 14000004 lu12i.w \$a0, 0 -+ 40: R_LARCH_TLS_LE_HI20 TLS1 -+ 44: 03800084 ori \$a0, \$a0, 0x0 -+ 44: R_LARCH_TLS_LE_LO12 TLS1 -+ 48: 1a000004 pcalau12i \$a0, 0 -+ 48: R_LARCH_TLS_IE_PC_HI20 TLS1 -+ 4c: 28800084 ld.w \$a0, \$a0, 0 -+ 4c: R_LARCH_TLS_IE_PC_LO12 TLS1 -+ 50: 1a000004 pcalau12i \$a0, 0 -+ 50: R_LARCH_TLS_LD_PC_HI20 TLS1 -+ 50: R_LARCH_RELAX \*ABS\* -+ 54: 02800084 addi.w \$a0, \$a0, 0 -+ 54: R_LARCH_GOT_PC_LO12 TLS1 -+ 54: R_LARCH_RELAX \*ABS\* -+ 58: 1a000004 pcalau12i \$a0, 0 -+ 58: R_LARCH_TLS_GD_PC_HI20 TLS1 -+ 58: R_LARCH_RELAX \*ABS\* -+ 5c: 02800084 addi.w \$a0, \$a0, 0 -+ 5c: R_LARCH_GOT_PC_LO12 TLS1 -+ 5c: R_LARCH_RELAX \*ABS\* -diff --git a/gas/testsuite/gas/loongarch/macro_op_large_abs.d b/gas/testsuite/gas/loongarch/macro_op_large_abs.d -index 0c49f68e..729e878f 100644 ---- a/gas/testsuite/gas/loongarch/macro_op_large_abs.d -+++ b/gas/testsuite/gas/loongarch/macro_op_large_abs.d -@@ -1,85 +1,89 @@ --#as: -mla-global-with-abs -+#as: - #objdump: -dr - #skip: loongarch32-*-* - --.*:[ ]+file format .* -+.*: file format .* - - - Disassembly of section .text: - --00000000.* <.L1>: --[ ]+0:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+0:[ ]+R_LARCH_PCALA_HI20[ ]+.L1 --[ ]+0:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+4:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0 --[ ]+4:[ ]+R_LARCH_PCALA_LO12[ ]+.L1 --[ ]+4:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+8:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0 --[ ]+8:[ ]+R_LARCH_PCALA64_LO20[ ]+.L1 --[ ]+c:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0 --[ ]+c:[ ]+R_LARCH_PCALA64_HI12[ ]+.L1 --[ ]+10:[ ]+00109484[ ]+add.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1 --[ ]+14:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0 --[ ]+14:[ ]+R_LARCH_MARK_LA[ ]+\*ABS\* --[ ]+14:[ ]+R_LARCH_ABS_HI20[ ]+.L1 --[ ]+18:[ ]+03800084[ ]+ori[ ]+\$a0,[ ]+\$a0,[ ]+0x0 --[ ]+18:[ ]+R_LARCH_ABS_LO12[ ]+.L1 --[ ]+1c:[ ]+16000004[ ]+lu32i.d[ ]+\$a0,[ ]+0 --[ ]+1c:[ ]+R_LARCH_ABS64_LO20[ ]+.L1 --[ ]+20:[ ]+03000084[ ]+lu52i.d[ ]+\$a0,[ ]+\$a0,[ ]+0 --[ ]+20:[ ]+R_LARCH_ABS64_HI12[ ]+.L1 --[ ]+24:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+24:[ ]+R_LARCH_PCALA_HI20[ ]+.L1 --[ ]+24:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+28:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0 --[ ]+28:[ ]+R_LARCH_PCALA_LO12[ ]+.L1 --[ ]+28:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+2c:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0 --[ ]+2c:[ ]+R_LARCH_PCALA64_LO20[ ]+.L1 --[ ]+30:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0 --[ ]+30:[ ]+R_LARCH_PCALA64_HI12[ ]+.L1 --[ ]+34:[ ]+00109484[ ]+add.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1 --[ ]+38:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+38:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1 --[ ]+38:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+3c:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0 --[ ]+3c:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1 --[ ]+3c:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+40:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0 --[ ]+40:[ ]+R_LARCH_GOT64_PC_LO20[ ]+.L1 --[ ]+44:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0 --[ ]+44:[ ]+R_LARCH_GOT64_PC_HI12[ ]+.L1 --[ ]+48:[ ]+380c1484[ ]+ldx.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1 --[ ]+4c:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0 --[ ]+4c:[ ]+R_LARCH_TLS_LE_HI20[ ]+TLS1 --[ ]+50:[ ]+03800084[ ]+ori[ ]+\$a0,[ ]+\$a0,[ ]+0x0 --[ ]+50:[ ]+R_LARCH_TLS_LE_LO12[ ]+TLS1 --[ ]+54:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+54:[ ]+R_LARCH_TLS_IE_PC_HI20[ ]+TLS1 --[ ]+58:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0 --[ ]+58:[ ]+R_LARCH_TLS_IE_PC_LO12[ ]+TLS1 --[ ]+5c:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0 --[ ]+5c:[ ]+R_LARCH_TLS_IE64_PC_LO20[ ]+TLS1 --[ ]+60:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0 --[ ]+60:[ ]+R_LARCH_TLS_IE64_PC_HI12[ ]+TLS1 --[ ]+64:[ ]+380c1484[ ]+ldx.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1 --[ ]+68:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+68:[ ]+R_LARCH_TLS_LD_PC_HI20[ ]+TLS1 --[ ]+6c:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0 --[ ]+6c:[ ]+R_LARCH_GOT_PC_LO12[ ]+TLS1 --[ ]+6c:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+70:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0 --[ ]+70:[ ]+R_LARCH_GOT64_PC_LO20[ ]+TLS1 --[ ]+74:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0 --[ ]+74:[ ]+R_LARCH_GOT64_PC_HI12[ ]+TLS1 --[ ]+78:[ ]+00109484[ ]+add.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1 --[ ]+7c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+7c:[ ]+R_LARCH_TLS_GD_PC_HI20[ ]+TLS1 --[ ]+80:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0 --[ ]+80:[ ]+R_LARCH_GOT_PC_LO12[ ]+TLS1 --[ ]+80:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+84:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0 --[ ]+84:[ ]+R_LARCH_GOT64_PC_LO20[ ]+TLS1 --[ ]+88:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0 --[ ]+88:[ ]+R_LARCH_GOT64_PC_HI12[ ]+TLS1 --[ ]+8c:[ ]+00109484[ ]+add.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1 -+0+ <.L1>: -+ 0: 1a000004 pcalau12i \$a0, 0 -+ 0: R_LARCH_PCALA_HI20 .L1 -+ 0: R_LARCH_RELAX \*ABS\* -+ 4: 02c00005 li.d \$a1, 0 -+ 4: R_LARCH_PCALA_LO12 .L1 -+ 4: R_LARCH_RELAX \*ABS\* -+ 8: 16000005 lu32i.d \$a1, 0 -+ 8: R_LARCH_PCALA64_LO20 .L1 -+ c: 030000a5 lu52i.d \$a1, \$a1, 0 -+ c: R_LARCH_PCALA64_HI12 .L1 -+ 10: 00109484 add.d \$a0, \$a0, \$a1 -+ 14: 1a000004 pcalau12i \$a0, 0 -+ 14: R_LARCH_GOT_PC_HI20 .L1 -+ 14: R_LARCH_RELAX \*ABS\* -+ 18: 02c00005 li.d \$a1, 0 -+ 18: R_LARCH_GOT_PC_LO12 .L1 -+ 18: R_LARCH_RELAX \*ABS\* -+ 1c: 16000005 lu32i.d \$a1, 0 -+ 1c: R_LARCH_GOT64_PC_LO20 .L1 -+ 20: 030000a5 lu52i.d \$a1, \$a1, 0 -+ 20: R_LARCH_GOT64_PC_HI12 .L1 -+ 24: 380c1484 ldx.d \$a0, \$a0, \$a1 -+ 28: 1a000004 pcalau12i \$a0, 0 -+ 28: R_LARCH_PCALA_HI20 .L1 -+ 28: R_LARCH_RELAX \*ABS\* -+ 2c: 02c00005 li.d \$a1, 0 -+ 2c: R_LARCH_PCALA_LO12 .L1 -+ 2c: R_LARCH_RELAX \*ABS\* -+ 30: 16000005 lu32i.d \$a1, 0 -+ 30: R_LARCH_PCALA64_LO20 .L1 -+ 34: 030000a5 lu52i.d \$a1, \$a1, 0 -+ 34: R_LARCH_PCALA64_HI12 .L1 -+ 38: 00109484 add.d \$a0, \$a0, \$a1 -+ 3c: 1a000004 pcalau12i \$a0, 0 -+ 3c: R_LARCH_GOT_PC_HI20 .L1 -+ 3c: R_LARCH_RELAX \*ABS\* -+ 40: 02c00005 li.d \$a1, 0 -+ 40: R_LARCH_GOT_PC_LO12 .L1 -+ 40: R_LARCH_RELAX \*ABS\* -+ 44: 16000005 lu32i.d \$a1, 0 -+ 44: R_LARCH_GOT64_PC_LO20 .L1 -+ 48: 030000a5 lu52i.d \$a1, \$a1, 0 -+ 48: R_LARCH_GOT64_PC_HI12 .L1 -+ 4c: 380c1484 ldx.d \$a0, \$a0, \$a1 -+ 50: 14000004 lu12i.w \$a0, 0 -+ 50: R_LARCH_TLS_LE_HI20 TLS1 -+ 54: 03800084 ori \$a0, \$a0, 0x0 -+ 54: R_LARCH_TLS_LE_LO12 TLS1 -+ 58: 1a000004 pcalau12i \$a0, 0 -+ 58: R_LARCH_TLS_IE_PC_HI20 TLS1 -+ 5c: 02c00005 li.d \$a1, 0 -+ 5c: R_LARCH_TLS_IE_PC_LO12 TLS1 -+ 60: 16000005 lu32i.d \$a1, 0 -+ 60: R_LARCH_TLS_IE64_PC_LO20 TLS1 -+ 64: 030000a5 lu52i.d \$a1, \$a1, 0 -+ 64: R_LARCH_TLS_IE64_PC_HI12 TLS1 -+ 68: 380c1484 ldx.d \$a0, \$a0, \$a1 -+ 6c: 1a000004 pcalau12i \$a0, 0 -+ 6c: R_LARCH_TLS_LD_PC_HI20 TLS1 -+ 6c: R_LARCH_RELAX \*ABS\* -+ 70: 02c00005 li.d \$a1, 0 -+ 70: R_LARCH_GOT_PC_LO12 TLS1 -+ 70: R_LARCH_RELAX \*ABS\* -+ 74: 16000005 lu32i.d \$a1, 0 -+ 74: R_LARCH_GOT64_PC_LO20 TLS1 -+ 78: 030000a5 lu52i.d \$a1, \$a1, 0 -+ 78: R_LARCH_GOT64_PC_HI12 TLS1 -+ 7c: 00109484 add.d \$a0, \$a0, \$a1 -+ 80: 1a000004 pcalau12i \$a0, 0 -+ 80: R_LARCH_TLS_GD_PC_HI20 TLS1 -+ 80: R_LARCH_RELAX \*ABS\* -+ 84: 02c00005 li.d \$a1, 0 -+ 84: R_LARCH_GOT_PC_LO12 TLS1 -+ 84: R_LARCH_RELAX \*ABS\* -+ 88: 16000005 lu32i.d \$a1, 0 -+ 88: R_LARCH_GOT64_PC_LO20 TLS1 -+ 8c: 030000a5 lu52i.d \$a1, \$a1, 0 -+ 8c: R_LARCH_GOT64_PC_HI12 TLS1 -+ 90: 00109484 add.d \$a0, \$a0, \$a1 -diff --git a/gas/testsuite/gas/loongarch/macro_op_large_pc.d b/gas/testsuite/gas/loongarch/macro_op_large_pc.d -index 0c49f68e..729e878f 100644 ---- a/gas/testsuite/gas/loongarch/macro_op_large_pc.d -+++ b/gas/testsuite/gas/loongarch/macro_op_large_pc.d -@@ -1,85 +1,89 @@ --#as: -mla-global-with-abs -+#as: - #objdump: -dr - #skip: loongarch32-*-* - --.*:[ ]+file format .* -+.*: file format .* - - - Disassembly of section .text: - --00000000.* <.L1>: --[ ]+0:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+0:[ ]+R_LARCH_PCALA_HI20[ ]+.L1 --[ ]+0:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+4:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0 --[ ]+4:[ ]+R_LARCH_PCALA_LO12[ ]+.L1 --[ ]+4:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+8:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0 --[ ]+8:[ ]+R_LARCH_PCALA64_LO20[ ]+.L1 --[ ]+c:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0 --[ ]+c:[ ]+R_LARCH_PCALA64_HI12[ ]+.L1 --[ ]+10:[ ]+00109484[ ]+add.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1 --[ ]+14:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0 --[ ]+14:[ ]+R_LARCH_MARK_LA[ ]+\*ABS\* --[ ]+14:[ ]+R_LARCH_ABS_HI20[ ]+.L1 --[ ]+18:[ ]+03800084[ ]+ori[ ]+\$a0,[ ]+\$a0,[ ]+0x0 --[ ]+18:[ ]+R_LARCH_ABS_LO12[ ]+.L1 --[ ]+1c:[ ]+16000004[ ]+lu32i.d[ ]+\$a0,[ ]+0 --[ ]+1c:[ ]+R_LARCH_ABS64_LO20[ ]+.L1 --[ ]+20:[ ]+03000084[ ]+lu52i.d[ ]+\$a0,[ ]+\$a0,[ ]+0 --[ ]+20:[ ]+R_LARCH_ABS64_HI12[ ]+.L1 --[ ]+24:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+24:[ ]+R_LARCH_PCALA_HI20[ ]+.L1 --[ ]+24:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+28:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0 --[ ]+28:[ ]+R_LARCH_PCALA_LO12[ ]+.L1 --[ ]+28:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+2c:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0 --[ ]+2c:[ ]+R_LARCH_PCALA64_LO20[ ]+.L1 --[ ]+30:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0 --[ ]+30:[ ]+R_LARCH_PCALA64_HI12[ ]+.L1 --[ ]+34:[ ]+00109484[ ]+add.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1 --[ ]+38:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+38:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1 --[ ]+38:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+3c:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0 --[ ]+3c:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1 --[ ]+3c:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+40:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0 --[ ]+40:[ ]+R_LARCH_GOT64_PC_LO20[ ]+.L1 --[ ]+44:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0 --[ ]+44:[ ]+R_LARCH_GOT64_PC_HI12[ ]+.L1 --[ ]+48:[ ]+380c1484[ ]+ldx.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1 --[ ]+4c:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0 --[ ]+4c:[ ]+R_LARCH_TLS_LE_HI20[ ]+TLS1 --[ ]+50:[ ]+03800084[ ]+ori[ ]+\$a0,[ ]+\$a0,[ ]+0x0 --[ ]+50:[ ]+R_LARCH_TLS_LE_LO12[ ]+TLS1 --[ ]+54:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+54:[ ]+R_LARCH_TLS_IE_PC_HI20[ ]+TLS1 --[ ]+58:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0 --[ ]+58:[ ]+R_LARCH_TLS_IE_PC_LO12[ ]+TLS1 --[ ]+5c:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0 --[ ]+5c:[ ]+R_LARCH_TLS_IE64_PC_LO20[ ]+TLS1 --[ ]+60:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0 --[ ]+60:[ ]+R_LARCH_TLS_IE64_PC_HI12[ ]+TLS1 --[ ]+64:[ ]+380c1484[ ]+ldx.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1 --[ ]+68:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+68:[ ]+R_LARCH_TLS_LD_PC_HI20[ ]+TLS1 --[ ]+6c:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0 --[ ]+6c:[ ]+R_LARCH_GOT_PC_LO12[ ]+TLS1 --[ ]+6c:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+70:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0 --[ ]+70:[ ]+R_LARCH_GOT64_PC_LO20[ ]+TLS1 --[ ]+74:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0 --[ ]+74:[ ]+R_LARCH_GOT64_PC_HI12[ ]+TLS1 --[ ]+78:[ ]+00109484[ ]+add.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1 --[ ]+7c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+7c:[ ]+R_LARCH_TLS_GD_PC_HI20[ ]+TLS1 --[ ]+80:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0 --[ ]+80:[ ]+R_LARCH_GOT_PC_LO12[ ]+TLS1 --[ ]+80:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+84:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0 --[ ]+84:[ ]+R_LARCH_GOT64_PC_LO20[ ]+TLS1 --[ ]+88:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0 --[ ]+88:[ ]+R_LARCH_GOT64_PC_HI12[ ]+TLS1 --[ ]+8c:[ ]+00109484[ ]+add.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1 -+0+ <.L1>: -+ 0: 1a000004 pcalau12i \$a0, 0 -+ 0: R_LARCH_PCALA_HI20 .L1 -+ 0: R_LARCH_RELAX \*ABS\* -+ 4: 02c00005 li.d \$a1, 0 -+ 4: R_LARCH_PCALA_LO12 .L1 -+ 4: R_LARCH_RELAX \*ABS\* -+ 8: 16000005 lu32i.d \$a1, 0 -+ 8: R_LARCH_PCALA64_LO20 .L1 -+ c: 030000a5 lu52i.d \$a1, \$a1, 0 -+ c: R_LARCH_PCALA64_HI12 .L1 -+ 10: 00109484 add.d \$a0, \$a0, \$a1 -+ 14: 1a000004 pcalau12i \$a0, 0 -+ 14: R_LARCH_GOT_PC_HI20 .L1 -+ 14: R_LARCH_RELAX \*ABS\* -+ 18: 02c00005 li.d \$a1, 0 -+ 18: R_LARCH_GOT_PC_LO12 .L1 -+ 18: R_LARCH_RELAX \*ABS\* -+ 1c: 16000005 lu32i.d \$a1, 0 -+ 1c: R_LARCH_GOT64_PC_LO20 .L1 -+ 20: 030000a5 lu52i.d \$a1, \$a1, 0 -+ 20: R_LARCH_GOT64_PC_HI12 .L1 -+ 24: 380c1484 ldx.d \$a0, \$a0, \$a1 -+ 28: 1a000004 pcalau12i \$a0, 0 -+ 28: R_LARCH_PCALA_HI20 .L1 -+ 28: R_LARCH_RELAX \*ABS\* -+ 2c: 02c00005 li.d \$a1, 0 -+ 2c: R_LARCH_PCALA_LO12 .L1 -+ 2c: R_LARCH_RELAX \*ABS\* -+ 30: 16000005 lu32i.d \$a1, 0 -+ 30: R_LARCH_PCALA64_LO20 .L1 -+ 34: 030000a5 lu52i.d \$a1, \$a1, 0 -+ 34: R_LARCH_PCALA64_HI12 .L1 -+ 38: 00109484 add.d \$a0, \$a0, \$a1 -+ 3c: 1a000004 pcalau12i \$a0, 0 -+ 3c: R_LARCH_GOT_PC_HI20 .L1 -+ 3c: R_LARCH_RELAX \*ABS\* -+ 40: 02c00005 li.d \$a1, 0 -+ 40: R_LARCH_GOT_PC_LO12 .L1 -+ 40: R_LARCH_RELAX \*ABS\* -+ 44: 16000005 lu32i.d \$a1, 0 -+ 44: R_LARCH_GOT64_PC_LO20 .L1 -+ 48: 030000a5 lu52i.d \$a1, \$a1, 0 -+ 48: R_LARCH_GOT64_PC_HI12 .L1 -+ 4c: 380c1484 ldx.d \$a0, \$a0, \$a1 -+ 50: 14000004 lu12i.w \$a0, 0 -+ 50: R_LARCH_TLS_LE_HI20 TLS1 -+ 54: 03800084 ori \$a0, \$a0, 0x0 -+ 54: R_LARCH_TLS_LE_LO12 TLS1 -+ 58: 1a000004 pcalau12i \$a0, 0 -+ 58: R_LARCH_TLS_IE_PC_HI20 TLS1 -+ 5c: 02c00005 li.d \$a1, 0 -+ 5c: R_LARCH_TLS_IE_PC_LO12 TLS1 -+ 60: 16000005 lu32i.d \$a1, 0 -+ 60: R_LARCH_TLS_IE64_PC_LO20 TLS1 -+ 64: 030000a5 lu52i.d \$a1, \$a1, 0 -+ 64: R_LARCH_TLS_IE64_PC_HI12 TLS1 -+ 68: 380c1484 ldx.d \$a0, \$a0, \$a1 -+ 6c: 1a000004 pcalau12i \$a0, 0 -+ 6c: R_LARCH_TLS_LD_PC_HI20 TLS1 -+ 6c: R_LARCH_RELAX \*ABS\* -+ 70: 02c00005 li.d \$a1, 0 -+ 70: R_LARCH_GOT_PC_LO12 TLS1 -+ 70: R_LARCH_RELAX \*ABS\* -+ 74: 16000005 lu32i.d \$a1, 0 -+ 74: R_LARCH_GOT64_PC_LO20 TLS1 -+ 78: 030000a5 lu52i.d \$a1, \$a1, 0 -+ 78: R_LARCH_GOT64_PC_HI12 TLS1 -+ 7c: 00109484 add.d \$a0, \$a0, \$a1 -+ 80: 1a000004 pcalau12i \$a0, 0 -+ 80: R_LARCH_TLS_GD_PC_HI20 TLS1 -+ 80: R_LARCH_RELAX \*ABS\* -+ 84: 02c00005 li.d \$a1, 0 -+ 84: R_LARCH_GOT_PC_LO12 TLS1 -+ 84: R_LARCH_RELAX \*ABS\* -+ 88: 16000005 lu32i.d \$a1, 0 -+ 88: R_LARCH_GOT64_PC_LO20 TLS1 -+ 8c: 030000a5 lu52i.d \$a1, \$a1, 0 -+ 8c: R_LARCH_GOT64_PC_HI12 TLS1 -+ 90: 00109484 add.d \$a0, \$a0, \$a1 -diff --git a/include/elf/loongarch.h b/include/elf/loongarch.h -index 41e9fe4d..6cfee164 100644 ---- a/include/elf/loongarch.h -+++ b/include/elf/loongarch.h -@@ -273,6 +273,10 @@ RELOC_NUMBER (R_LARCH_TLS_DESC64_HI12, 118) - RELOC_NUMBER (R_LARCH_TLS_DESC_LD, 119) - RELOC_NUMBER (R_LARCH_TLS_DESC_CALL, 120) - -+RELOC_NUMBER (R_LARCH_TLS_LD_PCREL20_S2, 124) -+RELOC_NUMBER (R_LARCH_TLS_GD_PCREL20_S2, 125) -+RELOC_NUMBER (R_LARCH_TLS_DESC_PCREL20_S2, 126) -+ - END_RELOC_NUMBERS (R_LARCH_count) - - /* Processor specific flags for the ELF header e_flags field. */ -diff --git a/ld/testsuite/ld-loongarch-elf/macro_op.d b/ld/testsuite/ld-loongarch-elf/macro_op.d -index edc71bc0..f0d87c03 100644 ---- a/ld/testsuite/ld-loongarch-elf/macro_op.d -+++ b/ld/testsuite/ld-loongarch-elf/macro_op.d -@@ -1,200 +1,205 @@ - #as: - #objdump: -dr -+#skip: loongarch32-*-* - --.*:[ ]+file format .* -+.*: file format .* - - - Disassembly of section .text: - --00000000.* <.L1>: --[ ]+0:[ ]+00150004[ ]+move[ ]+\$a0,[ ]+\$zero --[ ]+4:[ ]+02bffc04[ ]+li\.w[ ]+\$a0,[ ]+-1 --[ ]+8:[ ]+00150004[ ]+move[ ]+\$a0,[ ]+\$zero --[ ]+c:[ ]+02bffc04[ ]+li\.w[ ]+\$a0,[ ]+-1 --[ ]+10:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+10:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1 --[ ]+10:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+14:[ ]+28c00084[ ]+ld.d[ ]+\$a0,[ ]+\$a0,[ ]+0 --[ ]+14:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1 --[ ]+14:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+18:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+18:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1 --[ ]+18:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+1c:[ ]+28c00084[ ]+ld.d[ ]+\$a0,[ ]+\$a0,[ ]+0 --[ ]+1c:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1 --[ ]+1c:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+20:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+20:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1 --[ ]+20:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+24:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0 --[ ]+24:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1 --[ ]+24:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+28:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0 --[ ]+28:[ ]+R_LARCH_GOT64_PC_LO20[ ]+.L1 --[ ]+2c:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0 --[ ]+2c:[ ]+R_LARCH_GOT64_PC_HI12[ ]+.L1 --[ ]+30:[ ]+380c1484[ ]+ldx.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1 --[ ]+34:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+34:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1 --[ ]+34:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+38:[ ]+28c00084[ ]+ld.d[ ]+\$a0,[ ]+\$a0,[ ]+0 --[ ]+38:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1 --[ ]+38:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+3c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+3c:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1 --[ ]+3c:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+40:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0 --[ ]+40:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1 --[ ]+40:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+44:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0 --[ ]+44:[ ]+R_LARCH_GOT64_PC_LO20[ ]+.L1 --[ ]+48:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0 --[ ]+48:[ ]+R_LARCH_GOT64_PC_HI12[ ]+.L1 --[ ]+4c:[ ]+380c1484[ ]+ldx.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1 --[ ]+50:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+50:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1 --[ ]+50:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+54:[ ]+28c00084[ ]+ld.d[ ]+\$a0,[ ]+\$a0,[ ]+0 --[ ]+54:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1 --[ ]+54:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+58:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+58:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1 --[ ]+58:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+5c:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0 --[ ]+5c:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1 --[ ]+5c:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+60:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0 --[ ]+60:[ ]+R_LARCH_GOT64_PC_LO20[ ]+.L1 --[ ]+64:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0 --[ ]+64:[ ]+R_LARCH_GOT64_PC_HI12[ ]+.L1 --[ ]+68:[ ]+380c1484[ ]+ldx.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1 --[ ]+6c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+6c:[ ]+R_LARCH_PCALA_HI20[ ]+.L1 --[ ]+6c:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+70:[ ]+02c00084[ ]+addi.d[ ]+\$a0,[ ]+\$a0,[ ]+0 --[ ]+70:[ ]+R_LARCH_PCALA_LO12[ ]+.L1 --[ ]+70:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+74:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+74:[ ]+R_LARCH_PCALA_HI20[ ]+.L1 --[ ]+74:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+78:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0 --[ ]+78:[ ]+R_LARCH_PCALA_LO12[ ]+.L1 --[ ]+78:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+7c:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0 --[ ]+7c:[ ]+R_LARCH_PCALA64_LO20[ ]+.L1 --[ ]+80:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0 --[ ]+80:[ ]+R_LARCH_PCALA64_HI12[ ]+.L1 --[ ]+84:[ ]+00109484[ ]+add.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1 --[ ]+88:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+88:[ ]+R_LARCH_PCALA_HI20[ ]+.L1 --[ ]+88:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+8c:[ ]+02c00084[ ]+addi.d[ ]+\$a0,[ ]+\$a0,[ ]+0 --[ ]+8c:[ ]+R_LARCH_PCALA_LO12[ ]+.L1 --[ ]+8c:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+90:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+90:[ ]+R_LARCH_PCALA_HI20[ ]+.L1 --[ ]+90:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+94:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0 --[ ]+94:[ ]+R_LARCH_PCALA_LO12[ ]+.L1 --[ ]+94:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+98:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0 --[ ]+98:[ ]+R_LARCH_PCALA64_LO20[ ]+.L1 --[ ]+9c:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0 --[ ]+9c:[ ]+R_LARCH_PCALA64_HI12[ ]+.L1 --[ ]+a0:[ ]+00109484[ ]+add.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1 --[ ]+a4:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0 --[ ]+a4:[ ]+R_LARCH_MARK_LA[ ]+\*ABS\* --[ ]+a4:[ ]+R_LARCH_ABS_HI20[ ]+.L1 --[ ]+a8:[ ]+03800084[ ]+ori[ ]+\$a0,[ ]+\$a0,[ ]+0x0 --[ ]+a8:[ ]+R_LARCH_ABS_LO12[ ]+.L1 --[ ]+ac:[ ]+16000004[ ]+lu32i.d[ ]+\$a0,[ ]+0 --[ ]+ac:[ ]+R_LARCH_ABS64_LO20[ ]+.L1 --[ ]+b0:[ ]+03000084[ ]+lu52i.d[ ]+\$a0,[ ]+\$a0,[ ]+0 --[ ]+b0:[ ]+R_LARCH_ABS64_HI12[ ]+.L1 --[ ]+b4:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+b4:[ ]+R_LARCH_PCALA_HI20[ ]+.L1 --[ ]+b4:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+b8:[ ]+02c00084[ ]+addi.d[ ]+\$a0,[ ]+\$a0,[ ]+0 --[ ]+b8:[ ]+R_LARCH_PCALA_LO12[ ]+.L1 --[ ]+b8:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+bc:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+bc:[ ]+R_LARCH_PCALA_HI20[ ]+.L1 --[ ]+bc:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+c0:[ ]+02c00084[ ]+addi.d[ ]+\$a0,[ ]+\$a0,[ ]+0 --[ ]+c0:[ ]+R_LARCH_PCALA_LO12[ ]+.L1 --[ ]+c0:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+c4:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+c4:[ ]+R_LARCH_PCALA_HI20[ ]+.L1 --[ ]+c4:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+c8:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0 --[ ]+c8:[ ]+R_LARCH_PCALA_LO12[ ]+.L1 --[ ]+c8:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+cc:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0 --[ ]+cc:[ ]+R_LARCH_PCALA64_LO20[ ]+.L1 --[ ]+d0:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0 --[ ]+d0:[ ]+R_LARCH_PCALA64_HI12[ ]+.L1 --[ ]+d4:[ ]+00109484[ ]+add.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1 --[ ]+d8:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+d8:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1 --[ ]+d8:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+dc:[ ]+28c00084[ ]+ld.d[ ]+\$a0,[ ]+\$a0,[ ]+0 --[ ]+dc:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1 --[ ]+dc:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+e0:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+e0:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1 --[ ]+e0:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+e4:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0 --[ ]+e4:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1 --[ ]+e4:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+e8:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0 --[ ]+e8:[ ]+R_LARCH_GOT64_PC_LO20[ ]+.L1 --[ ]+ec:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0 --[ ]+ec:[ ]+R_LARCH_GOT64_PC_HI12[ ]+.L1 --[ ]+f0:[ ]+380c1484[ ]+ldx.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1 --[ ]+f4:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0 --[ ]+f4:[ ]+R_LARCH_TLS_LE_HI20[ ]+TLS1 --[ ]+f8:[ ]+03800084[ ]+ori[ ]+\$a0,[ ]+\$a0,[ ]+0x0 --[ ]+f8:[ ]+R_LARCH_TLS_LE_LO12[ ]+TLS1 --[ ]+fc:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+fc:[ ]+R_LARCH_TLS_IE_PC_HI20[ ]+TLS1 --[ ]+100:[ ]+28c00084[ ]+ld.d[ ]+\$a0,[ ]+\$a0,[ ]+0 --[ ]+100:[ ]+R_LARCH_TLS_IE_PC_LO12[ ]+TLS1 --[ ]+104:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+104:[ ]+R_LARCH_TLS_IE_PC_HI20[ ]+TLS1 --[ ]+108:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0 --[ ]+108:[ ]+R_LARCH_TLS_IE_PC_LO12[ ]+TLS1 --[ ]+10c:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0 --[ ]+10c:[ ]+R_LARCH_TLS_IE64_PC_LO20[ ]+TLS1 --[ ]+110:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0 --[ ]+110:[ ]+R_LARCH_TLS_IE64_PC_HI12[ ]+TLS1 --[ ]+114:[ ]+380c1484[ ]+ldx.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1 --[ ]+118:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+118:[ ]+R_LARCH_TLS_LD_PC_HI20[ ]+TLS1 --[ ]+11c:[ ]+02c00084[ ]+addi.d[ ]+\$a0,[ ]+\$a0,[ ]+0 --[ ]+11c:[ ]+R_LARCH_GOT_PC_LO12[ ]+TLS1 --[ ]+11c:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+120:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+120:[ ]+R_LARCH_TLS_LD_PC_HI20[ ]+TLS1 --[ ]+124:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0 --[ ]+124:[ ]+R_LARCH_GOT_PC_LO12[ ]+TLS1 --[ ]+124:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+128:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0 --[ ]+128:[ ]+R_LARCH_GOT64_PC_LO20[ ]+TLS1 --[ ]+12c:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0 --[ ]+12c:[ ]+R_LARCH_GOT64_PC_HI12[ ]+TLS1 --[ ]+130:[ ]+00109484[ ]+add.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1 --[ ]+134:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+134:[ ]+R_LARCH_TLS_GD_PC_HI20[ ]+TLS1 --[ ]+138:[ ]+02c00084[ ]+addi.d[ ]+\$a0,[ ]+\$a0,[ ]+0 --[ ]+138:[ ]+R_LARCH_GOT_PC_LO12[ ]+TLS1 --[ ]+138:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+13c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+13c:[ ]+R_LARCH_TLS_GD_PC_HI20[ ]+TLS1 --[ ]+140:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0 --[ ]+140:[ ]+R_LARCH_GOT_PC_LO12[ ]+TLS1 --[ ]+140:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+144:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0 --[ ]+144:[ ]+R_LARCH_GOT64_PC_LO20[ ]+TLS1 --[ ]+148:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0 --[ ]+148:[ ]+R_LARCH_GOT64_PC_HI12[ ]+TLS1 --[ ]+14c:[ ]+00109484[ ]+add.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1 -+0+ <.L1>: -+ 0: 00150004 move \$a0, \$zero -+ 4: 02bffc04 li.w \$a0, -1 -+ 8: 00150004 move \$a0, \$zero -+ c: 02bffc04 li.w \$a0, -1 -+ 10: 1a000004 pcalau12i \$a0, 0 -+ 10: R_LARCH_GOT_PC_HI20 .L1 -+ 10: R_LARCH_RELAX \*ABS\* -+ 14: 28c00084 ld.d \$a0, \$a0, 0 -+ 14: R_LARCH_GOT_PC_LO12 .L1 -+ 14: R_LARCH_RELAX \*ABS\* -+ 18: 1a000004 pcalau12i \$a0, 0 -+ 18: R_LARCH_GOT_PC_HI20 .L1 -+ 18: R_LARCH_RELAX \*ABS\* -+ 1c: 28c00084 ld.d \$a0, \$a0, 0 -+ 1c: R_LARCH_GOT_PC_LO12 .L1 -+ 1c: R_LARCH_RELAX \*ABS\* -+ 20: 1a000004 pcalau12i \$a0, 0 -+ 20: R_LARCH_GOT_PC_HI20 .L1 -+ 20: R_LARCH_RELAX \*ABS\* -+ 24: 02c00005 li.d \$a1, 0 -+ 24: R_LARCH_GOT_PC_LO12 .L1 -+ 24: R_LARCH_RELAX \*ABS\* -+ 28: 16000005 lu32i.d \$a1, 0 -+ 28: R_LARCH_GOT64_PC_LO20 .L1 -+ 2c: 030000a5 lu52i.d \$a1, \$a1, 0 -+ 2c: R_LARCH_GOT64_PC_HI12 .L1 -+ 30: 380c1484 ldx.d \$a0, \$a0, \$a1 -+ 34: 1a000004 pcalau12i \$a0, 0 -+ 34: R_LARCH_GOT_PC_HI20 .L1 -+ 34: R_LARCH_RELAX \*ABS\* -+ 38: 28c00084 ld.d \$a0, \$a0, 0 -+ 38: R_LARCH_GOT_PC_LO12 .L1 -+ 38: R_LARCH_RELAX \*ABS\* -+ 3c: 1a000004 pcalau12i \$a0, 0 -+ 3c: R_LARCH_GOT_PC_HI20 .L1 -+ 3c: R_LARCH_RELAX \*ABS\* -+ 40: 02c00005 li.d \$a1, 0 -+ 40: R_LARCH_GOT_PC_LO12 .L1 -+ 40: R_LARCH_RELAX \*ABS\* -+ 44: 16000005 lu32i.d \$a1, 0 -+ 44: R_LARCH_GOT64_PC_LO20 .L1 -+ 48: 030000a5 lu52i.d \$a1, \$a1, 0 -+ 48: R_LARCH_GOT64_PC_HI12 .L1 -+ 4c: 380c1484 ldx.d \$a0, \$a0, \$a1 -+ 50: 1a000004 pcalau12i \$a0, 0 -+ 50: R_LARCH_GOT_PC_HI20 .L1 -+ 50: R_LARCH_RELAX \*ABS\* -+ 54: 28c00084 ld.d \$a0, \$a0, 0 -+ 54: R_LARCH_GOT_PC_LO12 .L1 -+ 54: R_LARCH_RELAX \*ABS\* -+ 58: 1a000004 pcalau12i \$a0, 0 -+ 58: R_LARCH_GOT_PC_HI20 .L1 -+ 58: R_LARCH_RELAX \*ABS\* -+ 5c: 02c00005 li.d \$a1, 0 -+ 5c: R_LARCH_GOT_PC_LO12 .L1 -+ 5c: R_LARCH_RELAX \*ABS\* -+ 60: 16000005 lu32i.d \$a1, 0 -+ 60: R_LARCH_GOT64_PC_LO20 .L1 -+ 64: 030000a5 lu52i.d \$a1, \$a1, 0 -+ 64: R_LARCH_GOT64_PC_HI12 .L1 -+ 68: 380c1484 ldx.d \$a0, \$a0, \$a1 -+ 6c: 1a000004 pcalau12i \$a0, 0 -+ 6c: R_LARCH_PCALA_HI20 .L1 -+ 6c: R_LARCH_RELAX \*ABS\* -+ 70: 02c00084 addi.d \$a0, \$a0, 0 -+ 70: R_LARCH_PCALA_LO12 .L1 -+ 70: R_LARCH_RELAX \*ABS\* -+ 74: 1a000004 pcalau12i \$a0, 0 -+ 74: R_LARCH_PCALA_HI20 .L1 -+ 74: R_LARCH_RELAX \*ABS\* -+ 78: 02c00005 li.d \$a1, 0 -+ 78: R_LARCH_PCALA_LO12 .L1 -+ 78: R_LARCH_RELAX \*ABS\* -+ 7c: 16000005 lu32i.d \$a1, 0 -+ 7c: R_LARCH_PCALA64_LO20 .L1 -+ 80: 030000a5 lu52i.d \$a1, \$a1, 0 -+ 80: R_LARCH_PCALA64_HI12 .L1 -+ 84: 00109484 add.d \$a0, \$a0, \$a1 -+ 88: 1a000004 pcalau12i \$a0, 0 -+ 88: R_LARCH_PCALA_HI20 .L1 -+ 88: R_LARCH_RELAX \*ABS\* -+ 8c: 02c00084 addi.d \$a0, \$a0, 0 -+ 8c: R_LARCH_PCALA_LO12 .L1 -+ 8c: R_LARCH_RELAX \*ABS\* -+ 90: 1a000004 pcalau12i \$a0, 0 -+ 90: R_LARCH_PCALA_HI20 .L1 -+ 90: R_LARCH_RELAX \*ABS\* -+ 94: 02c00005 li.d \$a1, 0 -+ 94: R_LARCH_PCALA_LO12 .L1 -+ 94: R_LARCH_RELAX \*ABS\* -+ 98: 16000005 lu32i.d \$a1, 0 -+ 98: R_LARCH_PCALA64_LO20 .L1 -+ 9c: 030000a5 lu52i.d \$a1, \$a1, 0 -+ 9c: R_LARCH_PCALA64_HI12 .L1 -+ a0: 00109484 add.d \$a0, \$a0, \$a1 -+ a4: 14000004 lu12i.w \$a0, 0 -+ a4: R_LARCH_MARK_LA \*ABS\* -+ a4: R_LARCH_ABS_HI20 .L1 -+ a8: 03800084 ori \$a0, \$a0, 0x0 -+ a8: R_LARCH_ABS_LO12 .L1 -+ ac: 16000004 lu32i.d \$a0, 0 -+ ac: R_LARCH_ABS64_LO20 .L1 -+ b0: 03000084 lu52i.d \$a0, \$a0, 0 -+ b0: R_LARCH_ABS64_HI12 .L1 -+ b4: 1a000004 pcalau12i \$a0, 0 -+ b4: R_LARCH_PCALA_HI20 .L1 -+ b4: R_LARCH_RELAX \*ABS\* -+ b8: 02c00084 addi.d \$a0, \$a0, 0 -+ b8: R_LARCH_PCALA_LO12 .L1 -+ b8: R_LARCH_RELAX \*ABS\* -+ bc: 1a000004 pcalau12i \$a0, 0 -+ bc: R_LARCH_PCALA_HI20 .L1 -+ bc: R_LARCH_RELAX \*ABS\* -+ c0: 02c00084 addi.d \$a0, \$a0, 0 -+ c0: R_LARCH_PCALA_LO12 .L1 -+ c0: R_LARCH_RELAX \*ABS\* -+ c4: 1a000004 pcalau12i \$a0, 0 -+ c4: R_LARCH_PCALA_HI20 .L1 -+ c4: R_LARCH_RELAX \*ABS\* -+ c8: 02c00005 li.d \$a1, 0 -+ c8: R_LARCH_PCALA_LO12 .L1 -+ c8: R_LARCH_RELAX \*ABS\* -+ cc: 16000005 lu32i.d \$a1, 0 -+ cc: R_LARCH_PCALA64_LO20 .L1 -+ d0: 030000a5 lu52i.d \$a1, \$a1, 0 -+ d0: R_LARCH_PCALA64_HI12 .L1 -+ d4: 00109484 add.d \$a0, \$a0, \$a1 -+ d8: 1a000004 pcalau12i \$a0, 0 -+ d8: R_LARCH_GOT_PC_HI20 .L1 -+ d8: R_LARCH_RELAX \*ABS\* -+ dc: 28c00084 ld.d \$a0, \$a0, 0 -+ dc: R_LARCH_GOT_PC_LO12 .L1 -+ dc: R_LARCH_RELAX \*ABS\* -+ e0: 1a000004 pcalau12i \$a0, 0 -+ e0: R_LARCH_GOT_PC_HI20 .L1 -+ e0: R_LARCH_RELAX \*ABS\* -+ e4: 02c00005 li.d \$a1, 0 -+ e4: R_LARCH_GOT_PC_LO12 .L1 -+ e4: R_LARCH_RELAX \*ABS\* -+ e8: 16000005 lu32i.d \$a1, 0 -+ e8: R_LARCH_GOT64_PC_LO20 .L1 -+ ec: 030000a5 lu52i.d \$a1, \$a1, 0 -+ ec: R_LARCH_GOT64_PC_HI12 .L1 -+ f0: 380c1484 ldx.d \$a0, \$a0, \$a1 -+ f4: 14000004 lu12i.w \$a0, 0 -+ f4: R_LARCH_TLS_LE_HI20 TLS1 -+ f8: 03800084 ori \$a0, \$a0, 0x0 -+ f8: R_LARCH_TLS_LE_LO12 TLS1 -+ fc: 1a000004 pcalau12i \$a0, 0 -+ fc: R_LARCH_TLS_IE_PC_HI20 TLS1 -+ 100: 28c00084 ld.d \$a0, \$a0, 0 -+ 100: R_LARCH_TLS_IE_PC_LO12 TLS1 -+ 104: 1a000004 pcalau12i \$a0, 0 -+ 104: R_LARCH_TLS_IE_PC_HI20 TLS1 -+ 108: 02c00005 li.d \$a1, 0 -+ 108: R_LARCH_TLS_IE_PC_LO12 TLS1 -+ 10c: 16000005 lu32i.d \$a1, 0 -+ 10c: R_LARCH_TLS_IE64_PC_LO20 TLS1 -+ 110: 030000a5 lu52i.d \$a1, \$a1, 0 -+ 110: R_LARCH_TLS_IE64_PC_HI12 TLS1 -+ 114: 380c1484 ldx.d \$a0, \$a0, \$a1 -+ 118: 1a000004 pcalau12i \$a0, 0 -+ 118: R_LARCH_TLS_LD_PC_HI20 TLS1 -+ 118: R_LARCH_RELAX \*ABS\* -+ 11c: 02c00084 addi.d \$a0, \$a0, 0 -+ 11c: R_LARCH_GOT_PC_LO12 TLS1 -+ 11c: R_LARCH_RELAX \*ABS\* -+ 120: 1a000004 pcalau12i \$a0, 0 -+ 120: R_LARCH_TLS_LD_PC_HI20 TLS1 -+ 120: R_LARCH_RELAX \*ABS\* -+ 124: 02c00005 li.d \$a1, 0 -+ 124: R_LARCH_GOT_PC_LO12 TLS1 -+ 124: R_LARCH_RELAX \*ABS\* -+ 128: 16000005 lu32i.d \$a1, 0 -+ 128: R_LARCH_GOT64_PC_LO20 TLS1 -+ 12c: 030000a5 lu52i.d \$a1, \$a1, 0 -+ 12c: R_LARCH_GOT64_PC_HI12 TLS1 -+ 130: 00109484 add.d \$a0, \$a0, \$a1 -+ 134: 1a000004 pcalau12i \$a0, 0 -+ 134: R_LARCH_TLS_GD_PC_HI20 TLS1 -+ 134: R_LARCH_RELAX \*ABS\* -+ 138: 02c00084 addi.d \$a0, \$a0, 0 -+ 138: R_LARCH_GOT_PC_LO12 TLS1 -+ 138: R_LARCH_RELAX \*ABS\* -+ 13c: 1a000004 pcalau12i \$a0, 0 -+ 13c: R_LARCH_TLS_GD_PC_HI20 TLS1 -+ 13c: R_LARCH_RELAX \*ABS\* -+ 140: 02c00005 li.d \$a1, 0 -+ 140: R_LARCH_GOT_PC_LO12 TLS1 -+ 140: R_LARCH_RELAX \*ABS\* -+ 144: 16000005 lu32i.d \$a1, 0 -+ 144: R_LARCH_GOT64_PC_LO20 TLS1 -+ 148: 030000a5 lu52i.d \$a1, \$a1, 0 -+ 148: R_LARCH_GOT64_PC_HI12 TLS1 -+ 14c: 00109484 add.d \$a0, \$a0, \$a1 -diff --git a/ld/testsuite/ld-loongarch-elf/macro_op_32.d b/ld/testsuite/ld-loongarch-elf/macro_op_32.d -index 188026a5..a7349aa8 100644 ---- a/ld/testsuite/ld-loongarch-elf/macro_op_32.d -+++ b/ld/testsuite/ld-loongarch-elf/macro_op_32.d -@@ -2,66 +2,68 @@ - #objdump: -dr - #skip: loongarch64-*-* - --.*:[ ]+file format .* -+.*: file format .* - - - Disassembly of section .text: - --00000000.* <.L1>: --[ ]+0:[ ]+00150004[ ]+move[ ]+\$a0,[ ]+\$zero --[ ]+4:[ ]+02bffc04[ ]+li\.w[ ]+\$a0,[ ]+-1 --[ ]+8:[ ]+00150004[ ]+move[ ]+\$a0,[ ]+\$zero --[ ]+c:[ ]+02bffc04[ ]+li\.w[ ]+\$a0,[ ]+-1 --[ ]+10:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+10:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1 --[ ]+10:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+14:[ ]+28800084[ ]+ld.w[ ]+\$a0,[ ]+\$a0,[ ]+0 --[ ]+14:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1 --[ ]+14:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+18:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+18:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1 --[ ]+18:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+1c:[ ]+28800084[ ]+ld.w[ ]+\$a0,[ ]+\$a0,[ ]+0 --[ ]+1c:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1 --[ ]+1c:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+20:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+20:[ ]+R_LARCH_PCALA_HI20[ ]+.L1 --[ ]+20:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+24:[ ]+02800084[ ]+addi.w[ ]+\$a0,[ ]+\$a0,[ ]+0 --[ ]+24:[ ]+R_LARCH_PCALA_LO12[ ]+.L1 --[ ]+24:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+28:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0 --[ ]+28:[ ]+R_LARCH_MARK_LA[ ]+\*ABS\* --[ ]+28:[ ]+R_LARCH_ABS_HI20[ ]+.L1 --[ ]+2c:[ ]+03800084[ ]+ori[ ]+\$a0,[ ]+\$a0,[ ]+0x0 --[ ]+2c:[ ]+R_LARCH_ABS_LO12[ ]+.L1 --[ ]+30:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+30:[ ]+R_LARCH_PCALA_HI20[ ]+.L1 --[ ]+30:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+34:[ ]+02800084[ ]+addi.w[ ]+\$a0,[ ]+\$a0,[ ]+0 --[ ]+34:[ ]+R_LARCH_PCALA_LO12[ ]+.L1 --[ ]+34:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+38:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+38:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1 --[ ]+38:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+3c:[ ]+28800084[ ]+ld.w[ ]+\$a0,[ ]+\$a0,[ ]+0 --[ ]+3c:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1 --[ ]+3c:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+40:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0 --[ ]+40:[ ]+R_LARCH_TLS_LE_HI20[ ]+TLS1 --[ ]+44:[ ]+03800084[ ]+ori[ ]+\$a0,[ ]+\$a0,[ ]+0x0 --[ ]+44:[ ]+R_LARCH_TLS_LE_LO12[ ]+TLS1 --[ ]+48:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+48:[ ]+R_LARCH_TLS_IE_PC_HI20[ ]+TLS1 --[ ]+4c:[ ]+28800084[ ]+ld.w[ ]+\$a0,[ ]+\$a0,[ ]+0 --[ ]+4c:[ ]+R_LARCH_TLS_IE_PC_LO12[ ]+TLS1 --[ ]+50:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+50:[ ]+R_LARCH_TLS_LD_PC_HI20[ ]+TLS1 --[ ]+54:[ ]+02800084[ ]+addi.w[ ]+\$a0,[ ]+\$a0,[ ]+0 --[ ]+54:[ ]+R_LARCH_GOT_PC_LO12[ ]+TLS1 --[ ]+54:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+58:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+58:[ ]+R_LARCH_TLS_GD_PC_HI20[ ]+TLS1 --[ ]+5c:[ ]+02800084[ ]+addi.w[ ]+\$a0,[ ]+\$a0,[ ]+0 --[ ]+5c:[ ]+R_LARCH_GOT_PC_LO12[ ]+TLS1 --[ ]+5c:[ ]+R_LARCH_RELAX[ ]+\*ABS\* -+0+ <.L1>: -+ 0: 00150004 move \$a0, \$zero -+ 4: 02bffc04 li.w \$a0, -1 -+ 8: 00150004 move \$a0, \$zero -+ c: 02bffc04 li.w \$a0, -1 -+ 10: 1a000004 pcalau12i \$a0, 0 -+ 10: R_LARCH_GOT_PC_HI20 .L1 -+ 10: R_LARCH_RELAX \*ABS\* -+ 14: 28800084 ld.w \$a0, \$a0, 0 -+ 14: R_LARCH_GOT_PC_LO12 .L1 -+ 14: R_LARCH_RELAX \*ABS\* -+ 18: 1a000004 pcalau12i \$a0, 0 -+ 18: R_LARCH_GOT_PC_HI20 .L1 -+ 18: R_LARCH_RELAX \*ABS\* -+ 1c: 28800084 ld.w \$a0, \$a0, 0 -+ 1c: R_LARCH_GOT_PC_LO12 .L1 -+ 1c: R_LARCH_RELAX \*ABS\* -+ 20: 1a000004 pcalau12i \$a0, 0 -+ 20: R_LARCH_PCALA_HI20 .L1 -+ 20: R_LARCH_RELAX \*ABS\* -+ 24: 02800084 addi.w \$a0, \$a0, 0 -+ 24: R_LARCH_PCALA_LO12 .L1 -+ 24: R_LARCH_RELAX \*ABS\* -+ 28: 14000004 lu12i.w \$a0, 0 -+ 28: R_LARCH_MARK_LA \*ABS\* -+ 28: R_LARCH_ABS_HI20 .L1 -+ 2c: 03800084 ori \$a0, \$a0, 0x0 -+ 2c: R_LARCH_ABS_LO12 .L1 -+ 30: 1a000004 pcalau12i \$a0, 0 -+ 30: R_LARCH_PCALA_HI20 .L1 -+ 30: R_LARCH_RELAX \*ABS\* -+ 34: 02800084 addi.w \$a0, \$a0, 0 -+ 34: R_LARCH_PCALA_LO12 .L1 -+ 34: R_LARCH_RELAX \*ABS\* -+ 38: 1a000004 pcalau12i \$a0, 0 -+ 38: R_LARCH_GOT_PC_HI20 .L1 -+ 38: R_LARCH_RELAX \*ABS\* -+ 3c: 28800084 ld.w \$a0, \$a0, 0 -+ 3c: R_LARCH_GOT_PC_LO12 .L1 -+ 3c: R_LARCH_RELAX \*ABS\* -+ 40: 14000004 lu12i.w \$a0, 0 -+ 40: R_LARCH_TLS_LE_HI20 TLS1 -+ 44: 03800084 ori \$a0, \$a0, 0x0 -+ 44: R_LARCH_TLS_LE_LO12 TLS1 -+ 48: 1a000004 pcalau12i \$a0, 0 -+ 48: R_LARCH_TLS_IE_PC_HI20 TLS1 -+ 4c: 28800084 ld.w \$a0, \$a0, 0 -+ 4c: R_LARCH_TLS_IE_PC_LO12 TLS1 -+ 50: 1a000004 pcalau12i \$a0, 0 -+ 50: R_LARCH_TLS_LD_PC_HI20 TLS1 -+ 50: R_LARCH_RELAX \*ABS\* -+ 54: 02800084 addi.w \$a0, \$a0, 0 -+ 54: R_LARCH_GOT_PC_LO12 TLS1 -+ 54: R_LARCH_RELAX \*ABS\* -+ 58: 1a000004 pcalau12i \$a0, 0 -+ 58: R_LARCH_TLS_GD_PC_HI20 TLS1 -+ 58: R_LARCH_RELAX \*ABS\* -+ 5c: 02800084 addi.w \$a0, \$a0, 0 -+ 5c: R_LARCH_GOT_PC_LO12 TLS1 -+ 5c: R_LARCH_RELAX \*ABS\* --- -2.33.0 - diff --git a/LoongArch-Add-support-for-TLSDESC-in-ld.patch b/LoongArch-Add-support-for-TLSDESC-in-ld.patch deleted file mode 100644 index 11540fa..0000000 --- a/LoongArch-Add-support-for-TLSDESC-in-ld.patch +++ /dev/null @@ -1,331 +0,0 @@ -From b6d513ce677d288d470740a2a150a68a961e07cd Mon Sep 17 00:00:00 2001 -From: Lulu Cai -Date: Tue, 31 Oct 2023 16:11:56 +0800 -Subject: [PATCH 026/123] LoongArch: Add support for TLSDESC in ld. - -1.The linker for each DESC generates a R_LARCH_TLS_DESC64 dynamic - relocation, which relocation is placed at .rela.dyn. - TLSDESC always allocates two GOT slots and one dynamic relocation - space to TLSDESC. -2. When using multiple ways to access the same TLS variable, a - maximum of 5 GOT slots are used. For example, using GD, TLSDESC, - and IE to access the same TLS variable, GD always uses the first - two of the five GOT, TLSDESC uses the third and fourth, and IE - uses the last. ---- - bfd/elfnn-loongarch.c | 168 ++++++++++++++++++++++++++++++++++++------ - 1 file changed, 146 insertions(+), 22 deletions(-) - -diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c -index 8e61d8d2..31dde892 100644 ---- a/bfd/elfnn-loongarch.c -+++ b/bfd/elfnn-loongarch.c -@@ -48,6 +48,12 @@ struct loongarch_elf_link_hash_entry - #define GOT_TLS_GD 2 - #define GOT_TLS_IE 4 - #define GOT_TLS_LE 8 -+#define GOT_TLS_GDESC 16 -+ -+#define GOT_TLS_GD_BOTH_P(tls_type) \ -+ ((tls_type & GOT_TLS_GD) && (tls_type & GOT_TLS_GDESC)) -+#define GOT_TLS_GD_ANY_P(tls_type) \ -+ ((tls_type & GOT_TLS_GD) || (tls_type & GOT_TLS_GDESC)) - char tls_type; - }; - -@@ -563,6 +569,7 @@ loongarch_elf_record_tls_and_got_reference (bfd *abfd, - case GOT_NORMAL: - case GOT_TLS_GD: - case GOT_TLS_IE: -+ case GOT_TLS_GDESC: - /* Need GOT. */ - if (htab->elf.sgot == NULL - && !loongarch_elf_create_got_section (htab->elf.dynobj, info)) -@@ -750,6 +757,14 @@ loongarch_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, - return false; - break; - -+ case R_LARCH_TLS_DESC_PC_HI20: -+ case R_LARCH_TLS_DESC_HI20: -+ if (!loongarch_elf_record_tls_and_got_reference (abfd, info, h, -+ r_symndx, -+ GOT_TLS_GDESC)) -+ return false; -+ break; -+ - case R_LARCH_ABS_HI20: - case R_LARCH_SOP_PUSH_ABSOLUTE: - if (h != NULL) -@@ -1130,7 +1145,7 @@ allocate_dynrelocs (struct elf_link_hash_entry *h, void *inf) - - s = htab->elf.sgot; - h->got.offset = s->size; -- if (tls_type & (GOT_TLS_GD | GOT_TLS_IE)) -+ if (tls_type & (GOT_TLS_GD | GOT_TLS_IE | GOT_TLS_GDESC)) - { - /* TLS_GD needs two dynamic relocs and two GOT slots. */ - if (tls_type & GOT_TLS_GD) -@@ -1167,7 +1182,15 @@ allocate_dynrelocs (struct elf_link_hash_entry *h, void *inf) - htab->elf.srelgot->size += sizeof (ElfNN_External_Rela); - } - } -+ -+ /* TLS_DESC needs one dynamic reloc and two GOT slot. */ -+ if (tls_type & GOT_TLS_GDESC) -+ { -+ s->size += GOT_ENTRY_SIZE * 2; -+ htab->elf.srelgot->size += sizeof (ElfNN_External_Rela); -+ } - } -+ - else - { - s->size += GOT_ENTRY_SIZE; -@@ -1670,19 +1693,34 @@ loongarch_elf_size_dynamic_sections (bfd *output_bfd, - if (0 < *local_got) - { - *local_got = s->size; -+ if (*local_tls_type & (GOT_TLS_GD | GOT_TLS_IE | GOT_TLS_GDESC)) -+ { -+ /* TLS gd use two got. */ -+ if (*local_tls_type & GOT_TLS_GD) -+ { -+ s->size += 2 * GOT_ENTRY_SIZE; -+ if (!bfd_link_executable (info)) -+ srel->size += sizeof (ElfNN_External_Rela); -+ } - -- /* TLS gd use two got. */ -- if (*local_tls_type & GOT_TLS_GD) -- s->size += GOT_ENTRY_SIZE * 2; -- else -- /* Normal got, tls ie/ld use one got. */ -- s->size += GOT_ENTRY_SIZE; -+ /* TLS_DESC use two got. */ -+ if (*local_tls_type & GOT_TLS_GDESC) -+ { -+ s->size += 2 * GOT_ENTRY_SIZE; -+ srel->size += sizeof (ElfNN_External_Rela); -+ } - -- if (bfd_link_executable (info) -- && (*local_tls_type & (GOT_TLS_GD| GOT_TLS_IE))) -- ;/* Do nothing. */ -+ /* TLS ie and use one got. */ -+ if (*local_tls_type & GOT_TLS_IE) -+ { -+ s->size += GOT_ENTRY_SIZE; -+ if (!bfd_link_executable (info)) -+ srel->size += sizeof (ElfNN_External_Rela); -+ } -+ } - else - { -+ s->size += GOT_ENTRY_SIZE; - srel->size += sizeof (ElfNN_External_Rela); - } - } -@@ -2126,6 +2164,15 @@ perform_relocation (const Elf_Internal_Rela *rel, asection *input_section, - case R_LARCH_TLS_GD_HI20: - case R_LARCH_PCREL20_S2: - case R_LARCH_CALL36: -+ case R_LARCH_TLS_DESC_PC_HI20: -+ case R_LARCH_TLS_DESC_PC_LO12: -+ case R_LARCH_TLS_DESC64_PC_LO20: -+ case R_LARCH_TLS_DESC64_PC_HI12: -+ case R_LARCH_TLS_DESC_HI20: -+ case R_LARCH_TLS_DESC_LO12: -+ case R_LARCH_TLS_DESC64_LO20: -+ case R_LARCH_TLS_DESC64_HI12: -+ - r = loongarch_check_offset (rel, input_section); - if (r != bfd_reloc_ok) - break; -@@ -2135,6 +2182,11 @@ perform_relocation (const Elf_Internal_Rela *rel, asection *input_section, - contents, value); - break; - -+ case R_LARCH_TLS_DESC_LD: -+ case R_LARCH_TLS_DESC_CALL: -+ r = bfd_reloc_ok; -+ break; -+ - case R_LARCH_RELAX: - break; - -@@ -2383,10 +2435,10 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, - struct elf_link_hash_entry *h = NULL; - const char *name; - bfd_reloc_status_type r = bfd_reloc_ok; -- bool is_ie, is_undefweak, unresolved_reloc, defined_local; -+ bool is_ie, is_desc, is_undefweak, unresolved_reloc, defined_local; - bool resolved_local, resolved_dynly, resolved_to_const; - char tls_type; -- bfd_vma relocation, off, ie_off; -+ bfd_vma relocation, off, ie_off, desc_off; - int i, j; - - howto = loongarch_elf_rtype_to_howto (input_bfd, r_type); -@@ -2515,6 +2567,7 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, - - BFD_ASSERT (!resolved_local || defined_local); - -+ is_desc = false; - is_ie = false; - switch (r_type) - { -@@ -3398,6 +3451,8 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, - case R_LARCH_TLS_LD_HI20: - case R_LARCH_TLS_GD_PC_HI20: - case R_LARCH_TLS_GD_HI20: -+ case R_LARCH_TLS_DESC_PC_HI20: -+ case R_LARCH_TLS_DESC_HI20: - BFD_ASSERT (rel->r_addend == 0); - unresolved_reloc = false; - -@@ -3405,6 +3460,10 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, - || r_type == R_LARCH_TLS_IE_HI20) - is_ie = true; - -+ if (r_type == R_LARCH_TLS_DESC_PC_HI20 -+ || r_type == R_LARCH_TLS_DESC_HI20) -+ is_desc = true; -+ - bfd_vma got_off = 0; - if (h != NULL) - { -@@ -3419,9 +3478,19 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, - - BFD_ASSERT (got_off != MINUS_ONE); - -- ie_off = 0; - tls_type = _bfd_loongarch_elf_tls_type (input_bfd, h, r_symndx); -- if ((tls_type & GOT_TLS_GD) && (tls_type & GOT_TLS_IE)) -+ -+ /* If a tls variable is accessed in multiple ways, GD uses -+ the first two slots of GOT, desc follows with two slots, -+ and IE uses one slot at the end. */ -+ desc_off = 0; -+ if (GOT_TLS_GD_BOTH_P (tls_type)) -+ desc_off = 2 * GOT_ENTRY_SIZE; -+ -+ ie_off = 0; -+ if (GOT_TLS_GD_BOTH_P (tls_type) && (tls_type & GOT_TLS_IE)) -+ ie_off = 4 * GOT_ENTRY_SIZE; -+ else if (GOT_TLS_GD_ANY_P (tls_type) && (tls_type & GOT_TLS_IE)) - ie_off = 2 * GOT_ENTRY_SIZE; - - if ((got_off & 1) == 0) -@@ -3470,6 +3539,21 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, - loongarch_elf_append_rela (output_bfd, relgot, &rela); - } - } -+ if (tls_type & GOT_TLS_GDESC) -+ { -+ /* Unless it is a static link, DESC always emits a -+ dynamic relocation. */ -+ int indx = h && h->dynindx != -1 ? h->dynindx : 0; -+ rela.r_offset = sec_addr (got) + got_off + desc_off; -+ rela.r_addend = 0; -+ if (indx == 0) -+ rela.r_addend = relocation - elf_hash_table (info)->tls_sec->vma; -+ -+ rela.r_info = ELFNN_R_INFO (indx, R_LARCH_TLS_DESCNN); -+ loongarch_elf_append_rela (output_bfd, relgot, &rela); -+ bfd_put_NN (output_bfd, 0, -+ got->contents + got_off + desc_off); -+ } - if (tls_type & GOT_TLS_IE) - { - rela.r_offset = sec_addr (got) + got_off + ie_off; -@@ -3497,16 +3581,52 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, - } - } - } -- relocation = (got_off & (~(bfd_vma)1)) + sec_addr (got) -- + (is_ie ? ie_off : 0); -+ relocation = (got_off & (~(bfd_vma)1)) + sec_addr (got); -+ if (is_desc) -+ relocation += desc_off; -+ else if (is_ie) -+ relocation += ie_off; - - if (r_type == R_LARCH_TLS_LD_PC_HI20 - || r_type == R_LARCH_TLS_GD_PC_HI20 -- || r_type == R_LARCH_TLS_IE_PC_HI20) -+ || r_type == R_LARCH_TLS_IE_PC_HI20 -+ || r_type == R_LARCH_TLS_DESC_PC_HI20) - RELOCATE_CALC_PC32_HI20 (relocation, pc); - - break; - -+ case R_LARCH_TLS_DESC_PC_LO12: -+ case R_LARCH_TLS_DESC64_PC_LO20: -+ case R_LARCH_TLS_DESC64_PC_HI12: -+ case R_LARCH_TLS_DESC_LO12: -+ case R_LARCH_TLS_DESC64_LO20: -+ case R_LARCH_TLS_DESC64_HI12: -+ { -+ unresolved_reloc = false; -+ -+ if (h) -+ relocation = sec_addr (got) + (h->got.offset & (~(bfd_vma)1)); -+ else -+ relocation = sec_addr (got) -+ + (local_got_offsets[r_symndx] & (~(bfd_vma)1)); -+ -+ tls_type = _bfd_loongarch_elf_tls_type (input_bfd, h, r_symndx); -+ /* Use both TLS_GD and TLS_DESC. */ -+ if ((tls_type & GOT_TLS_GD) && (tls_type & GOT_TLS_GDESC)) -+ relocation += 2 * GOT_ENTRY_SIZE; -+ } -+ -+ if (r_type == R_LARCH_TLS_DESC64_PC_LO20 -+ || r_type == R_LARCH_TLS_DESC64_PC_HI12) -+ RELOCATE_CALC_PC64_HI32 (relocation, pc); -+ -+ break; -+ -+ case R_LARCH_TLS_DESC_LD: -+ case R_LARCH_TLS_DESC_CALL: -+ unresolved_reloc = false; -+ break; -+ - case R_LARCH_TLS_IE_PC_LO12: - case R_LARCH_TLS_IE64_PC_LO20: - case R_LARCH_TLS_IE64_PC_HI12: -@@ -3516,14 +3636,17 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, - unresolved_reloc = false; - - if (h) -- relocation = sec_addr (got) + (h->got.offset & (~(bfd_vma)3)); -+ relocation = sec_addr (got) + (h->got.offset & (~(bfd_vma)1)); - else - relocation = sec_addr (got) -- + (local_got_offsets[r_symndx] & (~(bfd_vma)3)); -+ + (local_got_offsets[r_symndx] & (~(bfd_vma)1)); - - tls_type = _bfd_loongarch_elf_tls_type (input_bfd, h, r_symndx); -- /* Use both TLS_GD and TLS_IE. */ -- if ((tls_type & GOT_TLS_GD) && (tls_type & GOT_TLS_IE)) -+ /* Use TLS_GD TLS_DESC and TLS_IE. */ -+ if (GOT_TLS_GD_BOTH_P (tls_type) && (tls_type & GOT_TLS_IE)) -+ relocation += 4 * GOT_ENTRY_SIZE; -+ /* Use GOT_TLS_GD_ANY_P (tls_type) and TLS_IE. */ -+ else if (GOT_TLS_GD_ANY_P (tls_type) && (tls_type & GOT_TLS_IE)) - relocation += 2 * GOT_ENTRY_SIZE; - - if (r_type == R_LARCH_TLS_IE64_PC_LO20 -@@ -4167,7 +4290,8 @@ loongarch_elf_finish_dynamic_symbol (bfd *output_bfd, - - if (h->got.offset != MINUS_ONE - /* TLS got entry have been handled in elf_relocate_section. */ -- && !(loongarch_elf_hash_entry (h)->tls_type & (GOT_TLS_GD | GOT_TLS_IE)) -+ && !(loongarch_elf_hash_entry (h)->tls_type -+ & (GOT_TLS_GD | GOT_TLS_IE | GOT_TLS_GDESC)) - /* Have allocated got entry but not allocated rela before. */ - && !UNDEFWEAK_NO_DYNAMIC_RELOC (info, h)) - { --- -2.33.0 - diff --git a/LoongArch-Add-support-for-b-.L1-and-beq-t0-t1-.L1.patch b/LoongArch-Add-support-for-b-.L1-and-beq-t0-t1-.L1.patch deleted file mode 100644 index d77330c..0000000 --- a/LoongArch-Add-support-for-b-.L1-and-beq-t0-t1-.L1.patch +++ /dev/null @@ -1,63 +0,0 @@ -From 114ab354c7fd16678578031340437b60e7b36e53 Mon Sep 17 00:00:00 2001 -From: mengqinggang -Date: Sun, 10 Dec 2023 17:41:32 +0800 -Subject: [PATCH 019/123] LoongArch: Add support for and - -Support symbol names enclosed in double quotation marks. ---- - .../gas/loongarch/double_quotation_marks.d | 13 +++++++++++++ - .../gas/loongarch/double_quotation_marks.s | 2 ++ - opcodes/loongarch-coder.c | 7 +++++++ - 3 files changed, 22 insertions(+) - create mode 100644 gas/testsuite/gas/loongarch/double_quotation_marks.d - create mode 100644 gas/testsuite/gas/loongarch/double_quotation_marks.s - -diff --git a/gas/testsuite/gas/loongarch/double_quotation_marks.d b/gas/testsuite/gas/loongarch/double_quotation_marks.d -new file mode 100644 -index 00000000..a42534b9 ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/double_quotation_marks.d -@@ -0,0 +1,13 @@ -+#as: -+#objdump: -dr -+ -+.*:[ ]+file format .* -+ -+ -+Disassembly of section .text: -+ -+.* <.text>: -+[ ]+0:[ ]+50000000[ ]+b[ ]+0[ ]+# 0x0 -+[ ]+0: R_LARCH_B26[ ]+.L1 -+[ ]+4:[ ]+5800018d[ ]+beq[ ]+\$t0, \$t1, 0[ ]+# 0x4 -+[ ]+4: R_LARCH_B16[ ]+.L1 -diff --git a/gas/testsuite/gas/loongarch/double_quotation_marks.s b/gas/testsuite/gas/loongarch/double_quotation_marks.s -new file mode 100644 -index 00000000..f8b63074 ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/double_quotation_marks.s -@@ -0,0 +1,2 @@ -+b ".L1" -+beq $r12, $r13, ".L1" -diff --git a/opcodes/loongarch-coder.c b/opcodes/loongarch-coder.c -index a68ae1c3..672a468b 100644 ---- a/opcodes/loongarch-coder.c -+++ b/opcodes/loongarch-coder.c -@@ -264,6 +264,13 @@ loongarch_split_args_by_comma (char *args, const char *arg_strs[]) - else - *args = '\0', arg_strs[num++] = args + 1; - } -+ -+ if (*(args-1) == '"') -+ { -+ *(args-1) = '\0'; -+ arg_strs[num-1] = arg_strs[num-1] + 1; -+ } -+ - arg_strs[num] = NULL; - return num; - } --- -2.33.0 - diff --git a/LoongArch-Add-support-for-the-third-expression-of-.a.patch b/LoongArch-Add-support-for-the-third-expression-of-.a.patch deleted file mode 100644 index aa608ee..0000000 --- a/LoongArch-Add-support-for-the-third-expression-of-.a.patch +++ /dev/null @@ -1,445 +0,0 @@ -From 3df3fec5862a2d6adec7dc469e7c53596e0ca464 Mon Sep 17 00:00:00 2001 -From: mengqinggang -Date: Fri, 8 Dec 2023 15:15:50 +0800 -Subject: [PATCH 023/123] LoongArch: Add support for the third expression of - .align for R_LARCH_ALIGN - -If the symbol index is not zero, the addend is used to represent -the first and the third expressions of the .align. - -The lowest 8 bits are used to represent the first expression. -Other bits are used to represent the third expression. - -The addend of R_LARCH_ALIGN for ".align 5, ,4" is 0x405. -The addend of R_LARCH_ALIGN for ".balign 32, ,4" is 0x405. ---- - bfd/elfnn-loongarch.c | 71 ++++++++++++------- - bfd/elfxx-loongarch.c | 10 ++- - gas/config/tc-loongarch.c | 20 ++++-- - gas/config/tc-loongarch.h | 4 +- - gas/testsuite/gas/loongarch/relax_align.d | 46 +++++++----- - gas/testsuite/gas/loongarch/relax_align.s | 4 +- - ld/testsuite/ld-elf/anno-sym.d | 2 + - ld/testsuite/ld-loongarch-elf/anno-sym.d | 7 ++ - ld/testsuite/ld-loongarch-elf/anno-sym.l | 4 ++ - ld/testsuite/ld-loongarch-elf/anno-sym.s | 13 ++++ - .../ld-loongarch-elf/ld-loongarch-elf.exp | 1 + - ld/testsuite/ld-loongarch-elf/relax-align.dd | 5 +- - ld/testsuite/ld-loongarch-elf/relax-align.s | 5 +- - ld/testsuite/ld-loongarch-elf/relax.exp | 2 +- - 14 files changed, 134 insertions(+), 60 deletions(-) - create mode 100644 ld/testsuite/ld-loongarch-elf/anno-sym.d - create mode 100644 ld/testsuite/ld-loongarch-elf/anno-sym.l - create mode 100644 ld/testsuite/ld-loongarch-elf/anno-sym.s - -diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c -index 6fd6a04d..8e61d8d2 100644 ---- a/bfd/elfnn-loongarch.c -+++ b/bfd/elfnn-loongarch.c -@@ -3851,44 +3851,53 @@ loongarch_relax_align (bfd *abfd, asection *sec, - Elf_Internal_Rela *rel, - bfd_vma symval) - { -- bfd_byte *contents = elf_section_data (sec)->this_hdr.contents; -- bfd_vma alignment = 1, pos; -- while (alignment <= rel->r_addend) -- alignment *= 2; -+ bfd_vma addend, max = 0, alignment = 1; - -- symval -= rel->r_addend; -- bfd_vma aligned_addr = ((symval - 1) & ~(alignment - 1)) + alignment; -- bfd_vma nop_bytes = aligned_addr - symval; -+ int index = ELFNN_R_SYM (rel->r_info); -+ if (index > 0) -+ { -+ alignment = 1 << (rel->r_addend & 0xff); -+ max = rel->r_addend >> 8; -+ } -+ else -+ alignment = rel->r_addend + 4; - -- /* Once we've handled an R_LARCH_ALIGN, we can't relax anything else. */ -- sec->sec_flg0 = true; -+ addend = alignment - 4; /* The bytes of NOPs added by R_LARCH_ALIGN. */ -+ symval -= addend; /* The address of first NOP added by R_LARCH_ALIGN. */ -+ bfd_vma aligned_addr = ((symval - 1) & ~(alignment - 1)) + alignment; -+ bfd_vma need_nop_bytes = aligned_addr - symval; /* */ - - /* Make sure there are enough NOPs to actually achieve the alignment. */ -- if (rel->r_addend < nop_bytes) -+ if (addend < need_nop_bytes) - { - _bfd_error_handler - (_("%pB(%pA+%#" PRIx64 "): %" PRId64 " bytes required for alignment " - "to %" PRId64 "-byte boundary, but only %" PRId64 " present"), - abfd, sym_sec, (uint64_t) rel->r_offset, -- (int64_t) nop_bytes, (int64_t) alignment, (int64_t) rel->r_addend); -+ (int64_t) need_nop_bytes, (int64_t) alignment, (int64_t) addend); - bfd_set_error (bfd_error_bad_value); - return false; - } - -- /* Delete the reloc. */ -+ /* Once we've handled an R_LARCH_ALIGN in a section, -+ we can't relax anything else in this section. */ -+ sec->sec_flg0 = true; - rel->r_info = ELFNN_R_INFO (0, R_LARCH_NONE); - -+ /* If skipping more bytes than the specified maximum, -+ then the alignment is not done at all and delete all NOPs. */ -+ if (max > 0 && need_nop_bytes > max) -+ return loongarch_relax_delete_bytes (abfd, sec, rel->r_offset, -+ addend, link_info); -+ - /* If the number of NOPs is already correct, there's nothing to do. */ -- if (nop_bytes == rel->r_addend) -+ if (need_nop_bytes == addend) - return true; - -- /* Write as many LOONGARCH NOPs as we need. */ -- for (pos = 0; pos < (nop_bytes & -4); pos += 4) -- bfd_putl32 (LARCH_NOP, contents + rel->r_offset + pos); -- - /* Delete the excess NOPs. */ -- return loongarch_relax_delete_bytes (abfd, sec, rel->r_offset + nop_bytes, -- rel->r_addend - nop_bytes, link_info); -+ return loongarch_relax_delete_bytes (abfd, sec, -+ rel->r_offset + need_nop_bytes, -+ addend - need_nop_bytes, link_info); - } - - static bool -@@ -3897,8 +3906,8 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, - bool *again) - { - struct loongarch_elf_link_hash_table *htab = loongarch_elf_hash_table (info); -- Elf_Internal_Shdr *symtab_hdr = &elf_symtab_hdr (abfd); - struct bfd_elf_section_data *data = elf_section_data (sec); -+ Elf_Internal_Shdr *symtab_hdr = &elf_symtab_hdr (abfd); - Elf_Internal_Rela *relocs; - *again = false; - -@@ -3931,7 +3940,7 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, - 0, NULL, NULL, NULL))) - return true; - -- data->relocs = relocs; -+ data->relocs = relocs; - - for (unsigned int i = 0; i < sec->reloc_count; i++) - { -@@ -3939,6 +3948,7 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, - asection *sym_sec; - bfd_vma symval; - unsigned long r_symndx = ELFNN_R_SYM (rel->r_info); -+ unsigned long r_type = ELFNN_R_TYPE (rel->r_info); - bool local_got = false; - char symtype; - struct elf_link_hash_entry *h = NULL; -@@ -3950,7 +3960,7 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, - if (ELF_ST_TYPE (sym->st_info) == STT_GNU_IFUNC) - continue; - -- if (sym->st_shndx == SHN_UNDEF) -+ if (sym->st_shndx == SHN_UNDEF || R_LARCH_ALIGN == r_type) - { - sym_sec = sec; - symval = rel->r_offset; -@@ -3976,9 +3986,9 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, - continue; - - if ((h->root.type == bfd_link_hash_defined -- || h->root.type == bfd_link_hash_defweak) -- && h->root.u.def.section != NULL -- && h->root.u.def.section->output_section != NULL) -+ || h->root.type == bfd_link_hash_defweak) -+ && h->root.u.def.section != NULL -+ && h->root.u.def.section->output_section != NULL) - { - symval = h->root.u.def.value; - sym_sec = h->root.u.def.section; -@@ -4004,12 +4014,21 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, - if (symtype != STT_SECTION) - symval += rel->r_addend; - } -+ /* For R_LARCH_ALIGN, symval is sec_addr (sym_sec) + rel->r_offset -+ + (alingmeng - 4). -+ If r_symndx is 0, alignmeng-4 is r_addend. -+ If r_symndx > 0, alignment-4 is 2^(r_addend & 0xff)-4. */ -+ else if (R_LARCH_ALIGN == r_type) -+ if (r_symndx > 0) -+ symval += ((1 << (rel->r_addend & 0xff)) - 4); -+ else -+ symval += rel->r_addend; - else - symval += rel->r_addend; - - symval += sec_addr (sym_sec); - -- switch (ELFNN_R_TYPE (rel->r_info)) -+ switch (r_type) - { - case R_LARCH_ALIGN: - if (1 == info->relax_pass) -diff --git a/bfd/elfxx-loongarch.c b/bfd/elfxx-loongarch.c -index d93b7904..679b79f3 100644 ---- a/bfd/elfxx-loongarch.c -+++ b/bfd/elfxx-loongarch.c -@@ -1395,9 +1395,13 @@ static loongarch_reloc_howto_type loongarch_howto_table[] = - NULL, /* adjust_reloc_bits. */ - NULL), /* larch_reloc_type_name. */ - -- /* Indicates an alignment statement. The addend field encodes how many -- bytes of NOPs follow the statement. The desired alignment is the -- addend rounded up to the next power of two. */ -+ /* Indicates an alignment statement. f the symbol index is 0, -+ the addend indicates the number of bytes occupied by nop instructions -+ at the relocation offset. The alignment boundary is specified by the -+ addend rounded up to the next power of two. -+ If the symbol index is not 0, the addend indicates the first and third -+ expressions of .align. The lowest 8 bits are used to represent the first -+ expression, other bits are used to represent the third expression. */ - LOONGARCH_HOWTO (R_LARCH_ALIGN, /* type (102). */ - 0, /* rightshift. */ - 0, /* size. */ -diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c -index 367a0b6c..9b912daf 100644 ---- a/gas/config/tc-loongarch.c -+++ b/gas/config/tc-loongarch.c -@@ -1652,14 +1652,16 @@ loongarch_make_nops (char *buf, bfd_vma bytes) - the correct alignment now because of other linker relaxations. */ - - bool --loongarch_frag_align_code (int n) -+loongarch_frag_align_code (int n, int max) - { -- bfd_vma bytes = (bfd_vma) 1 << n; -- bfd_vma insn_alignment = 4; -- bfd_vma worst_case_bytes = bytes - insn_alignment; - char *nops; -+ symbolS *s; - expressionS ex; - -+ bfd_vma insn_alignment = 4; -+ bfd_vma bytes = (bfd_vma) 1 << n; -+ bfd_vma worst_case_bytes = bytes - insn_alignment; -+ - /* If we are moving to a smaller alignment than the instruction size, then no - alignment is required. */ - if (bytes <= insn_alignment) -@@ -1671,8 +1673,14 @@ loongarch_frag_align_code (int n) - - nops = frag_more (worst_case_bytes); - -- ex.X_op = O_constant; -- ex.X_add_number = worst_case_bytes; -+ s = symbol_find (".Lla-relax-align"); -+ if (s == NULL) -+ s = (symbolS *)local_symbol_make (".Lla-relax-align", now_seg, -+ &zero_address_frag, 0); -+ -+ ex.X_add_symbol = s; -+ ex.X_op = O_symbol; -+ ex.X_add_number = (max << 8) | n; - - loongarch_make_nops (nops, worst_case_bytes); - -diff --git a/gas/config/tc-loongarch.h b/gas/config/tc-loongarch.h -index 4afa3842..194ee107 100644 ---- a/gas/config/tc-loongarch.h -+++ b/gas/config/tc-loongarch.h -@@ -49,11 +49,11 @@ extern int loongarch_relax_frag (asection *, struct frag *, long); - #define md_undefined_symbol(name) (0) - #define md_operand(x) - --extern bool loongarch_frag_align_code (int); -+extern bool loongarch_frag_align_code (int, int); - #define md_do_align(N, FILL, LEN, MAX, LABEL) \ - if ((N) != 0 && !(FILL) && !need_pass_2 && subseg_text_p (now_seg)) \ - { \ -- if (loongarch_frag_align_code (N)) \ -+ if (loongarch_frag_align_code (N, MAX)) \ - goto LABEL; \ - } - -diff --git a/gas/testsuite/gas/loongarch/relax_align.d b/gas/testsuite/gas/loongarch/relax_align.d -index 1810eb4c..2cc6c86d 100644 ---- a/gas/testsuite/gas/loongarch/relax_align.d -+++ b/gas/testsuite/gas/loongarch/relax_align.d -@@ -1,4 +1,4 @@ --#as: -+#as: --no-warn - #objdump: -dr - #skip: loongarch32-*-* - -@@ -7,20 +7,30 @@ - - Disassembly of section .text: - --00000000.* : --[ ]+0:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+0:[ ]+R_LARCH_PCALA_HI20[ ]+L1 --[ ]+0:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+4:[ ]+02c00084[ ]+addi\.d[ ]+\$a0,[ ]+\$a0,[ ]+0 --[ ]+4:[ ]+R_LARCH_PCALA_LO12[ ]+L1 --[ ]+4:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+8:[ ]+03400000[ ]+nop[ ]+ --[ ]+8:[ ]+R_LARCH_ALIGN[ ]+\*ABS\*\+0xc --[ ]+c:[ ]+03400000[ ]+nop[ ]+ --[ ]+10:[ ]+03400000[ ]+nop[ ]+ --[ ]+14:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 --[ ]+14:[ ]+R_LARCH_PCALA_HI20[ ]+L1 --[ ]+14:[ ]+R_LARCH_RELAX[ ]+\*ABS\* --[ ]+18:[ ]+02c00084[ ]+addi\.d[ ]+\$a0,[ ]+\$a0,[ ]+0 --[ ]+18:[ ]+R_LARCH_PCALA_LO12[ ]+L1 --[ ]+18:[ ]+R_LARCH_RELAX[ ]+\*ABS\* -+[ ]*0000000000000000 <.Lla-relax-align>: -+[ ]+0:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0 -+[ ]+0: R_LARCH_PCALA_HI20[ ]+L1 -+[ ]+0: R_LARCH_RELAX[ ]+\*ABS\* -+[ ]+4:[ ]+02c00084[ ]+addi.d[ ]+\$a0, \$a0, 0 -+[ ]+4: R_LARCH_PCALA_LO12[ ]+L1 -+[ ]+4: R_LARCH_RELAX[ ]+\*ABS\* -+[ ]+8:[ ]+03400000[ ]+nop.* -+[ ]+8: R_LARCH_ALIGN[ ]+.Lla-relax-align\+0x4 -+[ ]+c:[ ]+03400000[ ]+nop.* -+[ ]+10:[ ]+03400000[ ]+nop.* -+[ ]+14:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0 -+[ ]+14: R_LARCH_PCALA_HI20[ ]+L1 -+[ ]+14: R_LARCH_RELAX[ ]+\*ABS\* -+[ ]+18:[ ]+02c00084[ ]+addi.d[ ]+\$a0, \$a0, 0 -+[ ]+18: R_LARCH_PCALA_LO12[ ]+L1 -+[ ]+18: R_LARCH_RELAX[ ]+\*ABS\* -+[ ]+1c:[ ]+03400000[ ]+nop.* -+[ ]+1c: R_LARCH_ALIGN[ ]+.Lla-relax-align\+0x404 -+[ ]+20:[ ]+03400000[ ]+nop.* -+[ ]+24:[ ]+03400000[ ]+nop.* -+[ ]+28:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0 -+[ ]+28: R_LARCH_PCALA_HI20[ ]+L1 -+[ ]+28: R_LARCH_RELAX[ ]+\*ABS\* -+[ ]+2c:[ ]+02c00084[ ]+addi.d[ ]+\$a0, \$a0, 0 -+[ ]+2c: R_LARCH_PCALA_LO12[ ]+L1 -+[ ]+2c: R_LARCH_RELAX[ ]+\*ABS\* -diff --git a/gas/testsuite/gas/loongarch/relax_align.s b/gas/testsuite/gas/loongarch/relax_align.s -index 3880d783..c0177c88 100644 ---- a/gas/testsuite/gas/loongarch/relax_align.s -+++ b/gas/testsuite/gas/loongarch/relax_align.s -@@ -1,5 +1,7 @@ - .text --L1: -+.L1: - la.local $a0, L1 - .align 4 - la.local $a0, L1 -+ .align 4, , 4 -+ la.local $a0, L1 -diff --git a/ld/testsuite/ld-elf/anno-sym.d b/ld/testsuite/ld-elf/anno-sym.d -index 9e53c4a9..f1ce21f9 100644 ---- a/ld/testsuite/ld-elf/anno-sym.d -+++ b/ld/testsuite/ld-elf/anno-sym.d -@@ -3,3 +3,5 @@ - #error_output: anno-sym.l - # The mips-irix6 target fails this test because it does not find any function symbols. Not sure why. - #skip: *-*-irix* -+# The .align generate a local symbol .Lla-relax-align. -+#skip: loongarch*-*-* -diff --git a/ld/testsuite/ld-loongarch-elf/anno-sym.d b/ld/testsuite/ld-loongarch-elf/anno-sym.d -new file mode 100644 -index 00000000..a58f4a6c ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/anno-sym.d -@@ -0,0 +1,7 @@ -+# Copied from ld-elf, add -mno-relax to prevent generate .Lla-relax-align symbol -+# Check that linking anno-sym.o produces an undefined reference message referring to '_start' and not 'annobin_hello.c' -+#as: -mno-relax -+#ld: -e _start -+#error_output: anno-sym.l -+# The mips-irix6 target fails this test because it does not find any function symbols. Not sure why. -+#skip: *-*-irix* -diff --git a/ld/testsuite/ld-loongarch-elf/anno-sym.l b/ld/testsuite/ld-loongarch-elf/anno-sym.l -new file mode 100644 -index 00000000..ee9611ae ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/anno-sym.l -@@ -0,0 +1,4 @@ -+#... -+.*: in function `(|_)start': -+.*: undefined reference to `foo' -+#pass -diff --git a/ld/testsuite/ld-loongarch-elf/anno-sym.s b/ld/testsuite/ld-loongarch-elf/anno-sym.s -new file mode 100644 -index 00000000..92016a80 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/anno-sym.s -@@ -0,0 +1,13 @@ -+ .text -+ -+ .hidden .annobin_hello.c -+ .type .annobin_hello.c, STT_NOTYPE -+ .equiv .annobin_hello.c, . -+ .size .annobin_hello.c, 0 -+ -+ .global _start -+_start: -+ .nop -+ .align 4 -+ .dc.a foo -+ -diff --git a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -index 1fc70d0a..b43a518a 100644 ---- a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -+++ b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -@@ -32,6 +32,7 @@ if [istarget "loongarch64-*-*"] { - run_dump_test "syscall" - run_dump_test "disas-jirl" - run_dump_test "local-ifunc-reloc" -+ run_dump_test "anno-sym" - } - - if [istarget "loongarch32-*-*"] { -diff --git a/ld/testsuite/ld-loongarch-elf/relax-align.dd b/ld/testsuite/ld-loongarch-elf/relax-align.dd -index 5fce2255..37fdab18 100644 ---- a/ld/testsuite/ld-loongarch-elf/relax-align.dd -+++ b/ld/testsuite/ld-loongarch-elf/relax-align.dd -@@ -1,7 +1,8 @@ - #... - .*pcaddi.* --.*pcaddi.* - .*nop.* -+.*pcaddi.* - .*nop.* --.*0:.*pcaddi.* -+.*pcaddi.* -+.*pcaddi.* - #pass -diff --git a/ld/testsuite/ld-loongarch-elf/relax-align.s b/ld/testsuite/ld-loongarch-elf/relax-align.s -index 9617c02d..66dfea8f 100644 ---- a/ld/testsuite/ld-loongarch-elf/relax-align.s -+++ b/ld/testsuite/ld-loongarch-elf/relax-align.s -@@ -4,6 +4,9 @@ - .text - L1: - la.local $a0, L1 -+ .align 3 - la.local $a0, L1 -- .align 4 -+ .align 3, ,4 -+ la.local $a0, L1 -+ .align 3, ,2 - la.local $a0, L1 -diff --git a/ld/testsuite/ld-loongarch-elf/relax.exp b/ld/testsuite/ld-loongarch-elf/relax.exp -index 24d79ed5..77323d8d 100644 ---- a/ld/testsuite/ld-loongarch-elf/relax.exp -+++ b/ld/testsuite/ld-loongarch-elf/relax.exp -@@ -121,7 +121,7 @@ if [istarget loongarch64-*-*] { - [list \ - "loongarch relax-align" \ - "-e 0x0 -z relro" "" \ -- "" \ -+ "--no-warn" \ - {relax-align.s} \ - [list \ - [list objdump -d relax-align.dd] \ --- -2.33.0 - diff --git a/LoongArch-Add-testsuit-for-DESC-and-tls-transition-a.patch b/LoongArch-Add-testsuit-for-DESC-and-tls-transition-a.patch deleted file mode 100644 index bf4e209..0000000 --- a/LoongArch-Add-testsuit-for-DESC-and-tls-transition-a.patch +++ /dev/null @@ -1,669 +0,0 @@ -From aaab3bca7ff42e982134fd638ad1ae8324260a8f Mon Sep 17 00:00:00 2001 -From: Lulu Cai -Date: Wed, 13 Dec 2023 11:34:56 +0800 -Subject: [PATCH 029/123] LoongArch: Add testsuit for DESC and tls transition - and tls relaxation. - ---- - gas/testsuite/gas/loongarch/tlsdesc_32.d | 27 ++++++++ - gas/testsuite/gas/loongarch/tlsdesc_32.s | 12 ++++ - gas/testsuite/gas/loongarch/tlsdesc_32_abs.d | 26 ++++++++ - gas/testsuite/gas/loongarch/tlsdesc_32_abs.s | 8 +++ - gas/testsuite/gas/loongarch/tlsdesc_64.d | 28 ++++++++ - gas/testsuite/gas/loongarch/tlsdesc_64.s | 12 ++++ - .../gas/loongarch/tlsdesc_large_abs.d | 34 ++++++++++ - .../gas/loongarch/tlsdesc_large_abs.s | 12 ++++ - .../gas/loongarch/tlsdesc_large_pc.d | 38 +++++++++++ - .../gas/loongarch/tlsdesc_large_pc.s | 17 +++++ - ld/testsuite/ld-loongarch-elf/desc-ie.d | 16 +++++ - ld/testsuite/ld-loongarch-elf/desc-ie.s | 18 +++++ - ld/testsuite/ld-loongarch-elf/desc-le.d | 15 +++++ - ld/testsuite/ld-loongarch-elf/desc-le.s | 14 ++++ - ld/testsuite/ld-loongarch-elf/desc-norelax.d | 16 +++++ - ld/testsuite/ld-loongarch-elf/desc-norelax.s | 5 ++ - ld/testsuite/ld-loongarch-elf/desc-relax.d | 15 +++++ - ld/testsuite/ld-loongarch-elf/desc-relax.s | 5 ++ - ld/testsuite/ld-loongarch-elf/ie-le.d | 13 ++++ - ld/testsuite/ld-loongarch-elf/ie-le.s | 11 ++++ - .../ld-loongarch-elf/ld-loongarch-elf.exp | 9 +++ - ld/testsuite/ld-loongarch-elf/tlsdesc-dso.d | 56 ++++++++++++++++ - ld/testsuite/ld-loongarch-elf/tlsdesc-dso.s | 65 +++++++++++++++++++ - 23 files changed, 472 insertions(+) - create mode 100644 gas/testsuite/gas/loongarch/tlsdesc_32.d - create mode 100644 gas/testsuite/gas/loongarch/tlsdesc_32.s - create mode 100644 gas/testsuite/gas/loongarch/tlsdesc_32_abs.d - create mode 100644 gas/testsuite/gas/loongarch/tlsdesc_32_abs.s - create mode 100644 gas/testsuite/gas/loongarch/tlsdesc_64.d - create mode 100644 gas/testsuite/gas/loongarch/tlsdesc_64.s - create mode 100644 gas/testsuite/gas/loongarch/tlsdesc_large_abs.d - create mode 100644 gas/testsuite/gas/loongarch/tlsdesc_large_abs.s - create mode 100644 gas/testsuite/gas/loongarch/tlsdesc_large_pc.d - create mode 100644 gas/testsuite/gas/loongarch/tlsdesc_large_pc.s - create mode 100644 ld/testsuite/ld-loongarch-elf/desc-ie.d - create mode 100644 ld/testsuite/ld-loongarch-elf/desc-ie.s - create mode 100644 ld/testsuite/ld-loongarch-elf/desc-le.d - create mode 100644 ld/testsuite/ld-loongarch-elf/desc-le.s - create mode 100644 ld/testsuite/ld-loongarch-elf/desc-norelax.d - create mode 100644 ld/testsuite/ld-loongarch-elf/desc-norelax.s - create mode 100644 ld/testsuite/ld-loongarch-elf/desc-relax.d - create mode 100644 ld/testsuite/ld-loongarch-elf/desc-relax.s - create mode 100644 ld/testsuite/ld-loongarch-elf/ie-le.d - create mode 100644 ld/testsuite/ld-loongarch-elf/ie-le.s - create mode 100644 ld/testsuite/ld-loongarch-elf/tlsdesc-dso.d - create mode 100644 ld/testsuite/ld-loongarch-elf/tlsdesc-dso.s - -diff --git a/gas/testsuite/gas/loongarch/tlsdesc_32.d b/gas/testsuite/gas/loongarch/tlsdesc_32.d -new file mode 100644 -index 00000000..eddcc5ed ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/tlsdesc_32.d -@@ -0,0 +1,27 @@ -+#as: -+#objdump: -dr -+#skip: loongarch64-*-* -+ -+.*:[ ]+file format .* -+ -+Disassembly of section .text: -+ -+0+ <.*>: -+ 0: 1a000004 pcalau12i \$a0, 0 -+ 0: R_LARCH_TLS_DESC_PC_HI20 var -+ 4: 02800084 addi.w \$a0, \$a0, 0 -+ 4: R_LARCH_TLS_DESC_PC_LO12 var -+ 8: 28800081 ld.w \$ra, \$a0, 0 -+ 8: R_LARCH_TLS_DESC_LD var -+ c: 4c000021 jirl \$ra, \$ra, 0 -+ c: R_LARCH_TLS_DESC_CALL var -+ 10: 1a000004 pcalau12i \$a0, 0 -+ 10: R_LARCH_TLS_DESC_PC_HI20 var -+ 10: R_LARCH_RELAX \*ABS\* -+ 14: 02800084 addi.w \$a0, \$a0, 0 -+ 14: R_LARCH_TLS_DESC_PC_LO12 var -+ 14: R_LARCH_RELAX \*ABS\* -+ 18: 28800081 ld.w \$ra, \$a0, 0 -+ 18: R_LARCH_TLS_DESC_LD var -+ 1c: 4c000021 jirl \$ra, \$ra, 0 -+ 1c: R_LARCH_TLS_DESC_CALL var -diff --git a/gas/testsuite/gas/loongarch/tlsdesc_32.s b/gas/testsuite/gas/loongarch/tlsdesc_32.s -new file mode 100644 -index 00000000..ef6aee94 ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/tlsdesc_32.s -@@ -0,0 +1,12 @@ -+.L1: -+ # R_LARCH_TLS_DESC_PC_HI20 var -+ pcalau12i $a0,%desc_pc_hi20(var) -+ # R_LARCH_TLS_DESC_PC_LO12 var -+ addi.w $a0,$a0,%desc_pc_lo12(var) -+ # R_LARCH_TLS_DESC_LD var -+ ld.w $ra,$a0,%desc_ld(var) -+ # R_LARCH_TLS_DESC_CALL var -+ jirl $ra,$ra,%desc_call(var) -+ -+ # test macro, pcalau12i + addi.w => pcaddi -+ la.tls.desc $a0,var -diff --git a/gas/testsuite/gas/loongarch/tlsdesc_32_abs.d b/gas/testsuite/gas/loongarch/tlsdesc_32_abs.d -new file mode 100644 -index 00000000..e787e409 ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/tlsdesc_32_abs.d -@@ -0,0 +1,26 @@ -+#as: -mla-global-with-abs -+#objdump: -dr -+#skip: loongarch64-*-* -+ -+.*: file format .* -+ -+ -+Disassembly of section .text: -+ -+0+ <.*>: -+ 0: 14000004 lu12i.w \$a0, 0 -+ 0: R_LARCH_TLS_DESC_HI20 var -+ 4: 03800084 ori \$a0, \$a0, 0x0 -+ 4: R_LARCH_TLS_DESC_LO12 var -+ 8: 28800081 ld.w \$ra, \$a0, 0 -+ 8: R_LARCH_TLS_DESC_LD var -+ c: 4c000021 jirl \$ra, \$ra, 0 -+ c: R_LARCH_TLS_DESC_CALL var -+ 10: 14000004 lu12i.w \$a0, 0 -+ 10: R_LARCH_TLS_DESC_HI20 var -+ 14: 03800084 ori \$a0, \$a0, 0x0 -+ 14: R_LARCH_TLS_DESC_LO12 var -+ 18: 28800081 ld.w \$ra, \$a0, 0 -+ 18: R_LARCH_TLS_DESC_LD var -+ 1c: 4c000021 jirl \$ra, \$ra, 0 -+ 1c: R_LARCH_TLS_DESC_CALL var -diff --git a/gas/testsuite/gas/loongarch/tlsdesc_32_abs.s b/gas/testsuite/gas/loongarch/tlsdesc_32_abs.s -new file mode 100644 -index 00000000..65d096ea ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/tlsdesc_32_abs.s -@@ -0,0 +1,8 @@ -+.L1: -+ lu12i.w $a0,%desc_hi20(var) -+ ori $a0,$a0,%desc_lo12(var) -+ ld.w $ra,$a0,%desc_ld(var) -+ jirl $ra,$ra,%desc_call(var) -+ -+ # Test macro expansion -+ la.tls.desc $a0,var -diff --git a/gas/testsuite/gas/loongarch/tlsdesc_64.d b/gas/testsuite/gas/loongarch/tlsdesc_64.d -new file mode 100644 -index 00000000..2a2829c9 ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/tlsdesc_64.d -@@ -0,0 +1,28 @@ -+#as: -+#objdump: -dr -+#skip: loongarch32-*-* -+ -+.*: file format .* -+ -+ -+Disassembly of section .text: -+ -+0+ <.*>: -+ 0: 1a000004 pcalau12i \$a0, 0 -+ 0: R_LARCH_TLS_DESC_PC_HI20 var -+ 4: 02c00084 addi.d \$a0, \$a0, 0 -+ 4: R_LARCH_TLS_DESC_PC_LO12 var -+ 8: 28c00081 ld.d \$ra, \$a0, 0 -+ 8: R_LARCH_TLS_DESC_LD var -+ c: 4c000021 jirl \$ra, \$ra, 0 -+ c: R_LARCH_TLS_DESC_CALL var -+ 10: 1a000004 pcalau12i \$a0, 0 -+ 10: R_LARCH_TLS_DESC_PC_HI20 var -+ 10: R_LARCH_RELAX \*ABS\* -+ 14: 02c00084 addi.d \$a0, \$a0, 0 -+ 14: R_LARCH_TLS_DESC_PC_LO12 var -+ 14: R_LARCH_RELAX \*ABS\* -+ 18: 28c00081 ld.d \$ra, \$a0, 0 -+ 18: R_LARCH_TLS_DESC_LD var -+ 1c: 4c000021 jirl \$ra, \$ra, 0 -+ 1c: R_LARCH_TLS_DESC_CALL var -diff --git a/gas/testsuite/gas/loongarch/tlsdesc_64.s b/gas/testsuite/gas/loongarch/tlsdesc_64.s -new file mode 100644 -index 00000000..9d0ccb17 ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/tlsdesc_64.s -@@ -0,0 +1,12 @@ -+.L1: -+ # R_LARCH_TLS_DESC_PC_HI20 var -+ pcalau12i $a0,%desc_pc_hi20(var) -+ # R_LARCH_TLS_DESC_PC_LO12 var -+ addi.d $a0,$a0,%desc_pc_lo12(var) -+ # R_LARCH_TLS_DESC_LD var -+ ld.d $ra,$a0,%desc_ld(var) -+ # R_LARCH_TLS_DESC_CALL var -+ jirl $ra,$ra,%desc_call(var) -+ -+ # test macro, pcalau12i + addi.d => pcaddi -+ la.tls.desc $a0,var -diff --git a/gas/testsuite/gas/loongarch/tlsdesc_large_abs.d b/gas/testsuite/gas/loongarch/tlsdesc_large_abs.d -new file mode 100644 -index 00000000..5411a3ac ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/tlsdesc_large_abs.d -@@ -0,0 +1,34 @@ -+#as: -mla-global-with-abs -+#objdump: -dr -+#skip: loongarch32-*-* -+ -+.*: file format .* -+ -+ -+Disassembly of section .text: -+ -+0+ <.*>: -+ 0: 14000004 lu12i.w \$a0, 0 -+ 0: R_LARCH_TLS_DESC_HI20 var -+ 4: 03800084 ori \$a0, \$a0, 0x0 -+ 4: R_LARCH_TLS_DESC_LO12 var -+ 8: 16000004 lu32i.d \$a0, 0 -+ 8: R_LARCH_TLS_DESC64_LO20 var -+ c: 03000084 lu52i.d \$a0, \$a0, 0 -+ c: R_LARCH_TLS_DESC64_HI12 var -+ 10: 28c00081 ld.d \$ra, \$a0, 0 -+ 10: R_LARCH_TLS_DESC_LD var -+ 14: 4c000021 jirl \$ra, \$ra, 0 -+ 14: R_LARCH_TLS_DESC_CALL var -+ 18: 14000004 lu12i.w \$a0, 0 -+ 18: R_LARCH_TLS_DESC_HI20 var -+ 1c: 03800084 ori \$a0, \$a0, 0x0 -+ 1c: R_LARCH_TLS_DESC_LO12 var -+ 20: 16000004 lu32i.d \$a0, 0 -+ 20: R_LARCH_TLS_DESC64_LO20 var -+ 24: 03000084 lu52i.d \$a0, \$a0, 0 -+ 24: R_LARCH_TLS_DESC64_HI12 var -+ 28: 28c00081 ld.d \$ra, \$a0, 0 -+ 28: R_LARCH_TLS_DESC_LD var -+ 2c: 4c000021 jirl \$ra, \$ra, 0 -+ 2c: R_LARCH_TLS_DESC_CALL var -diff --git a/gas/testsuite/gas/loongarch/tlsdesc_large_abs.s b/gas/testsuite/gas/loongarch/tlsdesc_large_abs.s -new file mode 100644 -index 00000000..27a52620 ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/tlsdesc_large_abs.s -@@ -0,0 +1,12 @@ -+.L1: -+ .global var -+ #TLSDESC large abs -+ lu12i.w $a0,%desc_hi20(var) -+ ori $a0,$a0,%desc_lo12(var) -+ lu32i.d $a0,%desc64_lo20(var) -+ lu52i.d $a0,$a0,%desc64_hi12(var) -+ ld.d $ra,$a0,%desc_ld(var) -+ jirl $ra,$ra,%desc_call(var) -+ -+ # Test macro expansion -+ la.tls.desc $a0,var -diff --git a/gas/testsuite/gas/loongarch/tlsdesc_large_pc.d b/gas/testsuite/gas/loongarch/tlsdesc_large_pc.d -new file mode 100644 -index 00000000..2b7a4660 ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/tlsdesc_large_pc.d -@@ -0,0 +1,38 @@ -+#as: -+#objdump: -dr -+#skip: loongarch32-*-* -+ -+.*: file format .* -+ -+ -+Disassembly of section .text: -+ -+0+ <.*>: -+ 0: 1a000004 pcalau12i \$a0, 0 -+ 0: R_LARCH_TLS_DESC_PC_HI20 var -+ 4: 02c00005 li.d \$a1, 0 -+ 4: R_LARCH_TLS_DESC_PC_LO12 var -+ 8: 16000005 lu32i.d \$a1, 0 -+ 8: R_LARCH_TLS_DESC64_PC_LO20 var -+ c: 030000a5 lu52i.d \$a1, \$a1, 0 -+ c: R_LARCH_TLS_DESC64_PC_HI12 var -+ 10: 00109484 add.d \$a0, \$a0, \$a1 -+ 14: 28c00081 ld.d \$ra, \$a0, 0 -+ 14: R_LARCH_TLS_DESC_LD var -+ 18: 4c000021 jirl \$ra, \$ra, 0 -+ 18: R_LARCH_TLS_DESC_CALL var -+ 1c: 1a000004 pcalau12i \$a0, 0 -+ 1c: R_LARCH_TLS_DESC_PC_HI20 var -+ 1c: R_LARCH_RELAX \*ABS\* -+ 20: 02c00001 li.d \$ra, 0 -+ 20: R_LARCH_TLS_DESC_PC_LO12 var -+ 20: R_LARCH_RELAX \*ABS\* -+ 24: 16000001 lu32i.d \$ra, 0 -+ 24: R_LARCH_TLS_DESC64_PC_LO20 var -+ 28: 03000021 lu52i.d \$ra, \$ra, 0 -+ 28: R_LARCH_TLS_DESC64_PC_HI12 var -+ 2c: 00108484 add.d \$a0, \$a0, \$ra -+ 30: 28c00081 ld.d \$ra, \$a0, 0 -+ 30: R_LARCH_TLS_DESC_LD var -+ 34: 4c000021 jirl \$ra, \$ra, 0 -+ 34: R_LARCH_TLS_DESC_CALL var -diff --git a/gas/testsuite/gas/loongarch/tlsdesc_large_pc.s b/gas/testsuite/gas/loongarch/tlsdesc_large_pc.s -new file mode 100644 -index 00000000..0d0839a7 ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/tlsdesc_large_pc.s -@@ -0,0 +1,17 @@ -+.L1: -+ # R_LARCH_TLS_DESC_PC_HI20 var -+ pcalau12i $a0,%desc_pc_hi20(var) -+ # R_LARCH_TLS_DESC_PC_LO12 -+ addi.d $a1,$zero,%desc_pc_lo12(var) -+ # R_LARCH_TLS_DESC64_PC_LO20 -+ lu32i.d $a1,%desc64_pc_lo20(var) -+ # R_LARCH_TLS_DESC64_PC_HI12 -+ lu52i.d $a1,$a1,%desc64_pc_hi12(var) -+ add.d $a0,$a0,$a1 -+ # R_LARCH_TLS_DESC_LD -+ ld.d $ra,$a0,%desc_ld(var) -+ # R_LARCH_TLS_DESC -+ jirl $ra,$ra,%desc_call(var) -+ -+ # Test macro expansion -+ la.tls.desc $a0,$ra,var -diff --git a/ld/testsuite/ld-loongarch-elf/desc-ie.d b/ld/testsuite/ld-loongarch-elf/desc-ie.d -new file mode 100644 -index 00000000..d1acbfc6 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/desc-ie.d -@@ -0,0 +1,16 @@ -+#as: -+#ld: -shared -z norelro -e 0x0 -+#objdump: -dr -+#skip: loongarch32-*-* -+ -+.*: file format .* -+ -+Disassembly of section .text: -+ -+0+230 : -+ 230: 1a000084 pcalau12i \$a0, 4 -+ 234: 28cd6084 ld.d \$a0, \$a0, 856 -+ 238: 03400000 nop.* -+ 23c: 03400000 nop.* -+ 240: 1a000084 pcalau12i \$a0, 4 -+ 244: 28cd6081 ld.d \$ra, \$a0, 856 -diff --git a/ld/testsuite/ld-loongarch-elf/desc-ie.s b/ld/testsuite/ld-loongarch-elf/desc-ie.s -new file mode 100644 -index 00000000..7f5772bc ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/desc-ie.s -@@ -0,0 +1,18 @@ -+ .global v1 -+ .section .tdata,"awT",@progbits -+v1: -+ .word 1 -+ .text -+ .global fn1 -+ .type fn1,@function -+fn1: -+ -+ # Use DESC and IE to access the same symbol, -+ # DESC will relax to IE. -+ pcalau12i $a0,%desc_pc_hi20(var) -+ addi.d $a0,$a0,%desc_pc_lo12(var) -+ ld.d $ra,$a0,%desc_ld(var) -+ jirl $ra,$ra,%desc_call(var) -+ -+ pcalau12i $a0,%ie_pc_hi20(var) -+ ld.d $ra,$a0,%ie_pc_lo12(var) -diff --git a/ld/testsuite/ld-loongarch-elf/desc-le.d b/ld/testsuite/ld-loongarch-elf/desc-le.d -new file mode 100644 -index 00000000..b4ca9f82 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/desc-le.d -@@ -0,0 +1,15 @@ -+#as: -+#ld: -z norelro -e 0x0 -+#objdump: -dr -+#skip: loongarch32-*-* -+ -+.*: file format .* -+ -+ -+Disassembly of section .text: -+ -+0+1200000e8 : -+ 1200000e8: 14000004 lu12i.w \$a0, 0 -+ 1200000ec: 03800084 ori \$a0, \$a0, 0x0 -+ 1200000f0: 03400000 nop.* -+ 1200000f4: 03400000 nop.* -diff --git a/ld/testsuite/ld-loongarch-elf/desc-le.s b/ld/testsuite/ld-loongarch-elf/desc-le.s -new file mode 100644 -index 00000000..9ffaa2d6 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/desc-le.s -@@ -0,0 +1,14 @@ -+ .global var -+ .section .tdata,"awT",@progbits -+var: -+ .word 1 -+ .text -+ .global fn1 -+ .type fn1,@function -+fn1: -+ -+ # DESC will relax to LE. -+ pcalau12i $a0,%desc_pc_hi20(var) -+ addi.d $a0,$a0,%desc_pc_lo12(var) -+ ld.d $ra,$a0,%desc_ld(var) -+ jirl $ra,$ra,%desc_call(var) -diff --git a/ld/testsuite/ld-loongarch-elf/desc-norelax.d b/ld/testsuite/ld-loongarch-elf/desc-norelax.d -new file mode 100644 -index 00000000..32ce3e5e ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/desc-norelax.d -@@ -0,0 +1,16 @@ -+#as: -+#ld: -z norelro -shared --section-start=.got=0x1ff000 -+#objdump: -dr -+#skip: loongarch32-*-* -+ -+.*: file format .* -+ -+ -+Disassembly of section .text: -+ -+0+1c0 <.*>: -+ 1c0: 1a003fe4 pcalau12i \$a0, 511 -+ 1c4: 02c02084 addi.d \$a0, \$a0, 8 -+ 1c8: 28c00081 ld.d \$ra, \$a0, 0 -+ 1cc: 4c000021 jirl \$ra, \$ra, 0 -+ 1d0: 0010888c add.d \$t0, \$a0, \$tp -diff --git a/ld/testsuite/ld-loongarch-elf/desc-norelax.s b/ld/testsuite/ld-loongarch-elf/desc-norelax.s -new file mode 100644 -index 00000000..9aa7f552 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/desc-norelax.s -@@ -0,0 +1,5 @@ -+.L1: -+# The got address of the symbol exceeds the -+# range of pcaddi, do not relax. -+la.tls.desc $a0,var -+add.d $t0,$a0,$tp -diff --git a/ld/testsuite/ld-loongarch-elf/desc-relax.d b/ld/testsuite/ld-loongarch-elf/desc-relax.d -new file mode 100644 -index 00000000..ce53d317 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/desc-relax.d -@@ -0,0 +1,15 @@ -+#as: -+#ld: -z norelro -shared -+#objdump: -dr -+#skip: loongarch32-*-* -+ -+.*: file format .* -+ -+ -+Disassembly of section .text: -+ -+0+188 <.*>: -+ 188: 18020844 pcaddi \$a0, 4162 -+ 18c: 28c00081 ld.d \$ra, \$a0, 0 -+ 190: 4c000021 jirl \$ra, \$ra, 0 -+ 194: 0010888c add.d \$t0, \$a0, \$tp -diff --git a/ld/testsuite/ld-loongarch-elf/desc-relax.s b/ld/testsuite/ld-loongarch-elf/desc-relax.s -new file mode 100644 -index 00000000..4a993a5c ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/desc-relax.s -@@ -0,0 +1,5 @@ -+.L1: -+# A UND symbol but no more than the range of pcaddi, -+# do pcalau12i + addi => pcaddi -+la.tls.desc $a0,var -+add.d $t0,$a0,$tp -diff --git a/ld/testsuite/ld-loongarch-elf/ie-le.d b/ld/testsuite/ld-loongarch-elf/ie-le.d -new file mode 100644 -index 00000000..42694d7f ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/ie-le.d -@@ -0,0 +1,13 @@ -+#as: -+#ld: -z norelro -e 0x0 -+#objdump: -dr -+#skip: loongarch32-*-* -+ -+.*: file format .* -+ -+ -+Disassembly of section .text: -+ -+0+1200000e8 : -+ 1200000e8: 14000004 lu12i.w \$a0, 0 -+ 1200000ec: 03800084 ori \$a0, \$a0, 0x0 -diff --git a/ld/testsuite/ld-loongarch-elf/ie-le.s b/ld/testsuite/ld-loongarch-elf/ie-le.s -new file mode 100644 -index 00000000..795c7ce4 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/ie-le.s -@@ -0,0 +1,11 @@ -+ .data -+ .section .tdata,"awT",@progbits -+var: -+ .word 1 -+ .text -+ .global fn1 -+ .type gn1,@function -+fn1: -+ # expect IE to relax LE. -+ pcalau12i $a0,%ie_pc_hi20(var) -+ ld.d $a0,$a0,%ie_pc_lo12(var) -diff --git a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -index b43a518a..2a5709a5 100644 ---- a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -+++ b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -@@ -69,3 +69,12 @@ if [istarget "loongarch64-*-*"] { - ] \ - ] - } -+ -+if [istarget "loongarch64-*-*"] { -+ run_dump_test "desc-ie" -+ run_dump_test "desc-le" -+ run_dump_test "ie-le" -+ run_dump_test "tlsdesc-dso" -+ run_dump_test "desc-norelax" -+ run_dump_test "desc-relax" -+} -diff --git a/ld/testsuite/ld-loongarch-elf/tlsdesc-dso.d b/ld/testsuite/ld-loongarch-elf/tlsdesc-dso.d -new file mode 100644 -index 00000000..667ad746 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/tlsdesc-dso.d -@@ -0,0 +1,56 @@ -+#as: -+#ld: -shared -z norelro -+#objdump: -dr -+#skip: loongarch32-*-* -+ -+.*: file format .* -+ -+ -+Disassembly of section .text: -+ -+0+418 : -+ 418: 180214c4 pcaddi \$a0, 4262 -+ 41c: 1a000084 pcalau12i \$a0, 4 -+ 420: 28db0084 ld.d \$a0, \$a0, 1728 -+ 424: 180212a4 pcaddi \$a0, 4245 -+ 428: 18021304 pcaddi \$a0, 4248 -+ 42c: 28c00081 ld.d \$ra, \$a0, 0 -+ 430: 4c000021 jirl \$ra, \$ra, 0 -+ 434: 1a000084 pcalau12i \$a0, 4 -+ 438: 28d9c084 ld.d \$a0, \$a0, 1648 -+ 43c: 03400000 nop.* -+ 440: 03400000 nop.* -+ 444: 1a000084 pcalau12i \$a0, 4 -+ 448: 28d9c084 ld.d \$a0, \$a0, 1648 -+ 44c: 18021264 pcaddi \$a0, 4243 -+ 450: 18021244 pcaddi \$a0, 4242 -+ 454: 28c00081 ld.d \$ra, \$a0, 0 -+ 458: 4c000021 jirl \$ra, \$ra, 0 -+ 45c: 1a000084 pcalau12i \$a0, 4 -+ 460: 28daa084 ld.d \$a0, \$a0, 1704 -+ -+0+464 : -+ 464: 1a000084 pcalau12i \$a0, 4 -+ 468: 28d86084 ld.d \$a0, \$a0, 1560 -+ 46c: 18020ce4 pcaddi \$a0, 4199 -+ 470: 18020e04 pcaddi \$a0, 4208 -+ 474: 28c00081 ld.d \$ra, \$a0, 0 -+ 478: 4c000021 jirl \$ra, \$ra, 0 -+ 47c: 18020d24 pcaddi \$a0, 4201 -+ 480: 1a000084 pcalau12i \$a0, 4 -+ 484: 28d90084 ld.d \$a0, \$a0, 1600 -+ 488: 03400000 nop.* -+ 48c: 03400000 nop.* -+ 490: 1a000084 pcalau12i \$a0, 4 -+ 494: 28d90084 ld.d \$a0, \$a0, 1600 -+ 498: 18020d84 pcaddi \$a0, 4204 -+ 49c: 28c00081 ld.d \$ra, \$a0, 0 -+ 4a0: 4c000021 jirl \$ra, \$ra, 0 -+ 4a4: 18020d24 pcaddi \$a0, 4201 -+ 4a8: 1a000084 pcalau12i \$a0, 4 -+ 4ac: 28d96084 ld.d \$a0, \$a0, 1624 -+ -+0+4b0 : -+ 4b0: 18020d84 pcaddi \$a0, 4204 -+ 4b4: 28c00081 ld.d \$ra, \$a0, 0 -+ 4b8: 4c000021 jirl \$ra, \$ra, 0 -diff --git a/ld/testsuite/ld-loongarch-elf/tlsdesc-dso.s b/ld/testsuite/ld-loongarch-elf/tlsdesc-dso.s -new file mode 100644 -index 00000000..936bbcea ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/tlsdesc-dso.s -@@ -0,0 +1,65 @@ -+ .data -+ .section .tdata,"awT",@progbits -+ .global gl1, gl2, gl3, gl4 -+gl1: .dword 1 -+gl2: .dword 2 -+gl3: .dword 3 -+gl4: .dword 4 -+lo1: .dword 10 -+lo2: .dword 20 -+lo3: .dword 30 -+lo4: .dword 40 -+ .text -+# Access global symbol -+fun_gl1: -+ # GD + IE -+ # GD: pcaddi + addi.d => pcaddi -+ la.tls.gd $a0, gl1 -+ la.tls.ie $a0, gl1 -+ -+ # GD + DESC -+ # GD: pcaddi + addi.d => pcaddi -+ la.tls.gd $a0, gl2 -+ # DESC: pcaddi + addi.d => pcaddi -+ la.tls.desc $a0, gl2 -+ -+ # DESC + IE -+ # DESC -> IE -+ la.tls.desc $a0, gl3 -+ la.tls.ie $a0, gl3 -+ -+ # GD + DESC + IE -+ # GD: pcaddi + addi.d => pcaddi -+ la.tls.gd $a0, gl4 -+ # DESC: pcaddi + addi.d => pcaddi -+ la.tls.desc $a0, gl4 -+ la.tls.ie $a0, gl4 -+ -+# Access local symbol -+fun_lo: -+ # IE + GD -+ la.tls.ie $a0, lo1 -+ # GD: pcaddi + addi.d => pcaddi -+ la.tls.gd $a0, lo1 -+ -+ # DESC + GD -+ # DESC: pcaddi + addi.d => pcaddi -+ la.tls.desc $a0, lo2 -+ # GD: pcaddi + addi.d => pcaddi -+ la.tls.gd $a0, lo2 -+ -+ # DESC + IE -+ # DESC: DESC -> IE -+ la.tls.desc $a0, lo3 -+ la.tls.ie $a0, lo3 -+ -+ # DESC + GD + IE -+ # DESC: pcaddi + addi.d => pcaddi -+ la.tls.desc $a0, lo4 -+ # GD: pcaddi + addi.d => pcaddi -+ la.tls.gd $a0, lo4 -+ la.tls.ie $a0, lo4 -+ -+# Access external undef symbol -+fun_external: -+ la.tls.desc $a0, sH1 --- -2.33.0 - diff --git a/LoongArch-Add-tls-transition-support.patch b/LoongArch-Add-tls-transition-support.patch deleted file mode 100644 index fb6e68d..0000000 --- a/LoongArch-Add-tls-transition-support.patch +++ /dev/null @@ -1,325 +0,0 @@ -From c5c96dc807dbb67b601ff90fb9976dc123d5b7af Mon Sep 17 00:00:00 2001 -From: Lulu Cai -Date: Sun, 26 Nov 2023 14:25:26 +0800 -Subject: [PATCH 027/123] LoongArch: Add tls transition support. - -Transitions between DESC->IE/LE and IE->LE are supported now. -1. For DESC -> LE: - pcalau12i $a0,%desc_pc_hi20(var) => lu12i.w $a0,%le_hi20(var) - addi.d $a0,$a0,%desc_pc_lo12(var) => ori $a0,$a0,%le_lo12(var) - ld.d $a1,$a0,%desc_ld(var) => NOP - jirl $ra,$a1,%desc_call(var) => NOP - add.d $a0,$a0,$tp -2. For DESC -> IE: - pcalau12i $a0,%desc_pc_hi20(var) => pcalau12i $a0,%ie_pc_hi20(var) - addi.d $a0,$a0,%desc_pc_lo12(var) => ld.d $a0,$a0,%ie_pc_lo12(var) - ld.d $a1,$a0,%desc_ld(var) => NOP - jirl $ra,$a1,%desc_call(var) => NOP - add.d $a0,$a0,$tp -3. For IE -> LE: - pcalau12i $a0,%ie_pc_hi20(var) => lu12i.w $a0,%le_hi20(var) - ld.d $a0,$a0,%ie_pc_lo12(var) => ori $a0,$a0,%le_lo12(var) - add.d $a0,$a0,$tp -4. When a tls variable is accessed using both DESC and IE, DESC transitions - to IE and uses the same GOT entry as IE. ---- - bfd/elfnn-loongarch.c | 216 ++++++++++++++++++++++++++++++++++++- - include/opcode/loongarch.h | 6 ++ - 2 files changed, 221 insertions(+), 1 deletion(-) - -diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c -index 31dde892..13fddd63 100644 ---- a/bfd/elfnn-loongarch.c -+++ b/bfd/elfnn-loongarch.c -@@ -145,6 +145,16 @@ struct loongarch_elf_link_hash_table - #define elf_backend_rela_normal 1 - #define elf_backend_default_execstack 0 - -+#define IS_LOONGARCH_TLS_DESC_RELOC(R_TYPE) \ -+ ((R_TYPE) == R_LARCH_TLS_DESC_PC_HI20 \ -+ || (R_TYPE) == R_LARCH_TLS_DESC_PC_LO12 \ -+ || (R_TYPE) == R_LARCH_TLS_DESC_LD \ -+ || (R_TYPE) == R_LARCH_TLS_DESC_CALL) -+ -+#define IS_LOONGARCH_TLS_IE_RELOC(R_TYPE) \ -+ ((R_TYPE) == R_LARCH_TLS_IE_PC_HI20 \ -+ || (R_TYPE) == R_LARCH_TLS_IE_PC_LO12) -+ - /* Generate a PLT header. */ - - static bool -@@ -593,6 +603,10 @@ loongarch_elf_record_tls_and_got_reference (bfd *abfd, - - char *new_tls_type = &_bfd_loongarch_elf_tls_type (abfd, h, symndx); - *new_tls_type |= tls_type; -+ -+ /* If a symbol is accessed by both IE and DESC, relax DESC to IE. */ -+ if ((*new_tls_type & GOT_TLS_IE) && (*new_tls_type & GOT_TLS_GDESC)) -+ *new_tls_type &= ~ (GOT_TLS_GDESC); - if ((*new_tls_type & GOT_NORMAL) && (*new_tls_type & ~GOT_NORMAL)) - { - _bfd_error_handler (_("%pB: `%s' accessed both as normal and " -@@ -605,6 +619,104 @@ loongarch_elf_record_tls_and_got_reference (bfd *abfd, - return true; - } - -+static unsigned int -+loongarch_reloc_got_type (unsigned int r_type) -+{ -+ switch (r_type) -+ { -+ case R_LARCH_TLS_DESC_PC_HI20: -+ case R_LARCH_TLS_DESC_PC_LO12: -+ case R_LARCH_TLS_DESC_LD: -+ case R_LARCH_TLS_DESC_CALL: -+ return GOT_TLS_GDESC; -+ -+ case R_LARCH_TLS_IE_PC_HI20: -+ case R_LARCH_TLS_IE_PC_LO12: -+ return GOT_TLS_IE; -+ -+ default: -+ break; -+ } -+ return GOT_UNKNOWN; -+} -+ -+/* Return true if tls type transition can be performed. */ -+static bool -+loongarch_can_relax_tls (struct bfd_link_info *info, unsigned int r_type, -+ struct elf_link_hash_entry *h, bfd *input_bfd, -+ unsigned long r_symndx) -+{ -+ char symbol_tls_type; -+ unsigned int reloc_got_type; -+ -+ if (! (IS_LOONGARCH_TLS_DESC_RELOC (r_type) -+ || IS_LOONGARCH_TLS_IE_RELOC (r_type))) -+ return false; -+ -+ symbol_tls_type = _bfd_loongarch_elf_tls_type (input_bfd, h, r_symndx); -+ reloc_got_type = loongarch_reloc_got_type (r_type); -+ -+ if (symbol_tls_type == GOT_TLS_IE && GOT_TLS_GD_ANY_P (reloc_got_type)) -+ return true; -+ -+ if (! bfd_link_executable (info)) -+ return false; -+ -+ if (h && h->root.type == bfd_link_hash_undefweak) -+ return false; -+ -+ return true; -+} -+ -+/* The type of relocation that can be transitioned. */ -+static unsigned int -+loongarch_tls_transition_without_check (struct bfd_link_info *info, -+ unsigned int r_type, -+ struct elf_link_hash_entry *h) -+{ -+ bool local_exec = bfd_link_executable (info) -+ && SYMBOL_REFERENCES_LOCAL (info, h); -+ -+ switch (r_type) -+ { -+ case R_LARCH_TLS_DESC_PC_HI20: -+ return (local_exec -+ ? R_LARCH_TLS_LE_HI20 -+ : R_LARCH_TLS_IE_PC_HI20); -+ -+ case R_LARCH_TLS_DESC_PC_LO12: -+ return (local_exec -+ ? R_LARCH_TLS_LE_LO12 -+ : R_LARCH_TLS_IE_PC_LO12); -+ -+ case R_LARCH_TLS_DESC_LD: -+ case R_LARCH_TLS_DESC_CALL: -+ return R_LARCH_NONE; -+ -+ case R_LARCH_TLS_IE_PC_HI20: -+ return local_exec ? R_LARCH_TLS_LE_HI20 : r_type; -+ -+ case R_LARCH_TLS_IE_PC_LO12: -+ return local_exec ? R_LARCH_TLS_LE_LO12 : r_type; -+ -+ default: -+ break; -+ } -+ -+ return r_type; -+} -+ -+static unsigned int -+loongarch_tls_transition (struct bfd_link_info *info, unsigned int r_type, -+ struct elf_link_hash_entry *h, bfd *input_bfd, -+ unsigned long r_symndx) -+{ -+ if (! loongarch_can_relax_tls (info, r_type, h, input_bfd,r_symndx)) -+ return r_type; -+ -+ return loongarch_tls_transition_without_check (info, r_type, h); -+} -+ - /* Look through the relocs for a section during the first phase, and - allocate space in the global offset table or procedure linkage - table. */ -@@ -706,6 +818,7 @@ loongarch_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, - int need_dynreloc = 0; - int only_need_pcrel = 0; - -+ r_type = loongarch_tls_transition (info, r_type, h, abfd, r_symndx); - switch (r_type) - { - case R_LARCH_GOT_PC_HI20: -@@ -2403,6 +2516,96 @@ loongarch_reloc_is_fatal (struct bfd_link_info *info, - relocation += 0x100000000; \ - }) - -+/* Transition instruction sequence to relax instruction sequence. */ -+static bool -+loongarch_tls_relax (bfd *abfd, asection *sec, Elf_Internal_Rela *rel, -+ int r_type, struct elf_link_hash_entry *h, -+ struct bfd_link_info *info) -+{ -+ bool local_exec = bfd_link_executable (info) -+ && SYMBOL_REFERENCES_LOCAL (info, h); -+ bfd_byte *contents = elf_section_data (sec)->this_hdr.contents; -+ unsigned long insn; -+ -+ switch (r_type) -+ { -+ case R_LARCH_TLS_DESC_PC_HI20: -+ if (local_exec) -+ /* DESC -> LE relaxation: -+ pcalalau12i $a0,%desc_pc_hi20(var) => -+ lu12i.w $a0,%le_hi20(var) -+ */ -+ bfd_put (32, abfd, LARCH_LU12I_W | LARCH_RD_A0, -+ contents + rel->r_offset); -+ -+ /* DESC -> IE relaxation: -+ pcalalau12i $a0,%desc_pc_hi20(var) => -+ pcalalau12i $a0,%ie_pc_hi20(var) -+ */ -+ return true; -+ -+ case R_LARCH_TLS_DESC_PC_LO12: -+ if (local_exec) -+ { -+ /* DESC -> LE relaxation: -+ addi.d $a0,$a0,%desc_pc_lo12(var) => -+ ori $a0,$a0,le_lo12(var) -+ */ -+ insn = LARCH_ORI | LARCH_RD_RJ_A0; -+ bfd_put (32, abfd, LARCH_ORI | LARCH_RD_RJ_A0, -+ contents + rel->r_offset); -+ } -+ else -+ { -+ /* DESC -> IE relaxation: -+ addi.d $a0,$a0,%desc_pc_lo12(var) => -+ ld.d $a0,$a0,%%ie_pc_lo12 -+ */ -+ bfd_put (32, abfd, LARCH_LD_D | LARCH_RD_RJ_A0, -+ contents + rel->r_offset); -+ } -+ return true; -+ -+ case R_LARCH_TLS_DESC_LD: -+ case R_LARCH_TLS_DESC_CALL: -+ /* DESC -> LE/IE relaxation: -+ ld.d $ra,$a0,%desc_ld(var) => NOP -+ jirl $ra,$ra,%desc_call(var) => NOP -+ */ -+ bfd_put (32, abfd, LARCH_NOP, contents + rel->r_offset); -+ return true; -+ -+ case R_LARCH_TLS_IE_PC_HI20: -+ if (local_exec) -+ { -+ /* IE -> LE relaxation: -+ pcalalau12i $rd,%ie_pc_hi20(var) => -+ lu12i.w $rd,%le_hi20(var) -+ */ -+ insn = bfd_getl32 (contents + rel->r_offset); -+ bfd_put (32, abfd, LARCH_LU12I_W | (insn & 0x1f), -+ contents + rel->r_offset); -+ } -+ return true; -+ -+ case R_LARCH_TLS_IE_PC_LO12: -+ if (local_exec) -+ { -+ /* IE -> LE relaxation: -+ ld.d $rd,$rj,%%ie_pc_lo12 => -+ ori $rd,$rj,le_lo12(var) -+ */ -+ insn = bfd_getl32 (contents + rel->r_offset); -+ bfd_put (32, abfd, LARCH_ORI | (insn & 0x3ff), -+ contents + rel->r_offset); -+ } -+ return true; -+ } -+ -+ return false; -+} -+ -+ - static int - loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, - bfd *input_bfd, asection *input_section, -@@ -2426,7 +2629,7 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, - relend = relocs + input_section->reloc_count; - for (rel = relocs; rel < relend; rel++) - { -- int r_type = ELFNN_R_TYPE (rel->r_info); -+ unsigned int r_type = ELFNN_R_TYPE (rel->r_info); - unsigned long r_symndx = ELFNN_R_SYM (rel->r_info); - bfd_vma pc = sec_addr (input_section) + rel->r_offset; - reloc_howto_type *howto = NULL; -@@ -2436,6 +2639,7 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, - const char *name; - bfd_reloc_status_type r = bfd_reloc_ok; - bool is_ie, is_desc, is_undefweak, unresolved_reloc, defined_local; -+ unsigned int relaxed_r_type; - bool resolved_local, resolved_dynly, resolved_to_const; - char tls_type; - bfd_vma relocation, off, ie_off, desc_off; -@@ -2567,6 +2771,16 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, - - BFD_ASSERT (!resolved_local || defined_local); - -+ relaxed_r_type = loongarch_tls_transition (info, r_type, h, input_bfd, r_symndx); -+ if (relaxed_r_type != r_type) -+ { -+ howto = loongarch_elf_rtype_to_howto (input_bfd, relaxed_r_type); -+ BFD_ASSERT (howto != NULL); -+ -+ if (loongarch_tls_relax (input_bfd, input_section, rel, r_type, h, info)) -+ r_type = relaxed_r_type; -+ } -+ - is_desc = false; - is_ie = false; - switch (r_type) -diff --git a/include/opcode/loongarch.h b/include/opcode/loongarch.h -index da936f79..32ff4d8a 100644 ---- a/include/opcode/loongarch.h -+++ b/include/opcode/loongarch.h -@@ -42,6 +42,12 @@ extern "C" - ((value) < (-(1 << ((bits) - 1) << align)) \ - || (value) > ((((1 << ((bits) - 1)) - 1) << align))) - -+ #define LARCH_LU12I_W 0x14000000 -+ #define LARCH_ORI 0x03800000 -+ #define LARCH_LD_D 0x28c00000 -+ #define LARCH_RD_A0 0x04 -+ #define LARCH_RD_RJ_A0 0x084 -+ - typedef uint32_t insn_t; - - struct loongarch_opcode --- -2.33.0 - diff --git a/LoongArch-Allow-la.got-la.pcrel-relaxation-for-share.patch b/LoongArch-Allow-la.got-la.pcrel-relaxation-for-share.patch deleted file mode 100644 index dfa45de..0000000 --- a/LoongArch-Allow-la.got-la.pcrel-relaxation-for-share.patch +++ /dev/null @@ -1,68 +0,0 @@ -From f1cef8611e241100dc6da362d27382b7fd543143 Mon Sep 17 00:00:00 2001 -From: Xi Ruoyao -Date: Wed, 6 Dec 2023 03:05:47 +0800 -Subject: [PATCH 022/123] LoongArch: Allow la.got -> la.pcrel relaxation for - shared object - -Even in shared objects, la.got -> la.pcrel relaxation can still be -performed for symbols with hidden visibility. For example, if a.c is: - - extern int x; - int f() { return x++; } - -and b.c is: - - int x = 114514; - -If compiling and linking with: - - gcc -shared -fPIC -O2 -fvisibility=hidden a.c b.c - -Then the la.got in a.o should be relaxed to la.pcrel, and the resulted f -should be like: - - pcaddi $t0, x - ldptr.w $a0, $t0, 0 - addi.w $t1, $a0, 1 - stptr.w $t1, $t0, 0 - ret - -Remove bfd_link_executable from the condition of la.got -> la.pcrel -relaxation so this will really happen. The SYMBOL_REFERENCES_LOCAL -check is enough not to wrongly relax preemptable symbols (for e.g. -when -fvisibility=hidden is not used). - -Note that on x86_64 this is also relaxed and the produced code is like: - - lea x(%rip), %rdx - mov (%rdx), %rax - lea 1(%rax), %ecx - mov %ecx, (%rdx) - ret - -Tested by running ld test suite, bootstrapping and regtesting GCC with -the patched ld, and building and testing Glibc with the patched ld. No -regression is observed. - -Signed-off-by: Xi Ruoyao ---- - bfd/elfnn-loongarch.c | 3 +-- - 1 file changed, 1 insertion(+), 2 deletions(-) - -diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c -index 20dd0640..6fd6a04d 100644 ---- a/bfd/elfnn-loongarch.c -+++ b/bfd/elfnn-loongarch.c -@@ -3986,8 +3986,7 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, - else - continue; - -- if (h && bfd_link_executable (info) -- && SYMBOL_REFERENCES_LOCAL (info, h)) -+ if (h && SYMBOL_REFERENCES_LOCAL (info, h)) - local_got = true; - symtype = h->type; - } --- -2.33.0 - diff --git a/LoongArch-Commas-inside-double-quotes.patch b/LoongArch-Commas-inside-double-quotes.patch deleted file mode 100644 index bf5ceaa..0000000 --- a/LoongArch-Commas-inside-double-quotes.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 0f5ce25e8a67bb55de5de18e02c8c9afe2a31ec7 Mon Sep 17 00:00:00 2001 -From: Alan Modra -Date: Thu, 28 Dec 2023 22:12:17 +1030 -Subject: [PATCH 036/123] LoongArch: Commas inside double quotes - -This adds an extra feature: Commas inside double quotes are not an -arg delimiter, and thus can be part of the arg. - - * loongarch-coder.c (loongarch_split_args_by_comma): Commas - inside quotes are not arg delimiters. ---- - opcodes/loongarch-coder.c | 6 +++++- - 1 file changed, 5 insertions(+), 1 deletion(-) - -diff --git a/opcodes/loongarch-coder.c b/opcodes/loongarch-coder.c -index b6835276..c5b09509 100644 ---- a/opcodes/loongarch-coder.c -+++ b/opcodes/loongarch-coder.c -@@ -18,6 +18,7 @@ - along with this program; see the file COPYING3. If not, - see . */ - #include "sysdep.h" -+#include - #include "opcode/loongarch.h" - - int -@@ -256,9 +257,12 @@ loongarch_split_args_by_comma (char *args, const char *arg_strs[]) - - if (*args) - { -+ bool inquote = false; - arg_strs[num++] = args; - for (; *args; args++) -- if (*args == ',') -+ if (*args == '"') -+ inquote = !inquote; -+ else if (*args == ',' && !inquote) - { - if (MAX_ARG_NUM_PLUS_2 - 1 == num) - goto out; --- -2.33.0 - diff --git a/LoongArch-Correct-comments.patch b/LoongArch-Correct-comments.patch deleted file mode 100644 index 6744c65..0000000 --- a/LoongArch-Correct-comments.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 4744da32d9f3c4fb37f4ddf4019a514bbbbd5220 Mon Sep 17 00:00:00 2001 -From: caiyinyu -Date: Tue, 17 Oct 2023 20:58:40 +0800 -Subject: [PATCH 015/123] LoongArch: Correct comments. - ---- - bfd/elfnn-loongarch.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c -index 7dbe31eb..09c98713 100644 ---- a/bfd/elfnn-loongarch.c -+++ b/bfd/elfnn-loongarch.c -@@ -2325,7 +2325,7 @@ loongarch_reloc_is_fatal (struct bfd_link_info *info, - addi.d $t0, $zero, lo12 (0x812) - $t0 = 0xfffffffffffff812 (if lo12 > 0x7ff, because sign-extend, - lo20 need to sub 0x1) -- lu32i.d $t0, lo12 (0x71234) -+ lu32i.d $t0, lo20 (0x71234) - $t0 = {0x71234, 0xfffff812} - = 0x71234fffff812 - lu52i.d $t0, hi12 (0x0) --- -2.33.0 - diff --git a/LoongArch-Delete-extra-instructions-when-TLS-type-tr.patch b/LoongArch-Delete-extra-instructions-when-TLS-type-tr.patch deleted file mode 100644 index 7a0242e..0000000 --- a/LoongArch-Delete-extra-instructions-when-TLS-type-tr.patch +++ /dev/null @@ -1,652 +0,0 @@ -From 2bd49b44dfe938623456d4abfef7f0c5f5b3b81f Mon Sep 17 00:00:00 2001 -From: Lulu Cai -Date: Wed, 24 Jan 2024 17:43:20 +0800 -Subject: [PATCH 069/123] LoongArch: Delete extra instructions when TLS type - transition - -This modification mainly changes the timing of type transition, -adds relaxation to the old LE instruction sequence, and fixes -bugs in extreme code models. - -We strictly distinguish between type transition and relaxation. -Type transition is from one type to another, while relaxation -is the removal of instructions under the same TLS type. Detailed -instructions are as follows: - -1. For type transition, only the normal code model of DESC/IE -does type transition, and each relocation is accompanied by a -RELAX relocation. Neither abs nor extreme will do type transition, -and no RELAX relocation will be generated. -The extra instructions when DESC transitions to other TLS types -will be deleted during the type transition. - -2. Implemented relaxation for the old LE instruction sequence. -The first two instructions of LE's 32-bit and 64-bit models -use the same relocations and cannot be distinguished based on -relocations. Therefore, for LE's instruction sequence, any code -model will try to relax. - -3. Some function names have been adjusted to facilitate understanding, -parameters have been adjusted, and unused macros have been deleted. ---- - bfd/elfnn-loongarch.c | 420 +++++++++++++++++++++++--------------- - gas/config/tc-loongarch.c | 31 ++- - 2 files changed, 279 insertions(+), 172 deletions(-) - -diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c -index 1693ad7e..eea1839f 100644 ---- a/bfd/elfnn-loongarch.c -+++ b/bfd/elfnn-loongarch.c -@@ -145,16 +145,20 @@ struct loongarch_elf_link_hash_table - #define elf_backend_rela_normal 1 - #define elf_backend_default_execstack 0 - --#define IS_LOONGARCH_TLS_DESC_RELOC(R_TYPE) \ -- ((R_TYPE) == R_LARCH_TLS_DESC_PC_HI20 \ -- || (R_TYPE) == R_LARCH_TLS_DESC_PC_LO12 \ -- || (R_TYPE) == R_LARCH_TLS_DESC_LD \ -- || (R_TYPE) == R_LARCH_TLS_DESC_CALL) -- --#define IS_LOONGARCH_TLS_IE_RELOC(R_TYPE) \ -- ((R_TYPE) == R_LARCH_TLS_IE_PC_HI20 \ -+#define IS_LOONGARCH_TLS_TRANS_RELOC(R_TYPE) \ -+ ((R_TYPE) == R_LARCH_TLS_DESC_PC_HI20 \ -+ || (R_TYPE) == R_LARCH_TLS_DESC_PC_LO12 \ -+ || (R_TYPE) == R_LARCH_TLS_DESC_LD \ -+ || (R_TYPE) == R_LARCH_TLS_DESC_CALL \ -+ || (R_TYPE) == R_LARCH_TLS_IE_PC_HI20 \ - || (R_TYPE) == R_LARCH_TLS_IE_PC_LO12) - -+#define IS_OUTDATED_TLS_LE_RELOC(R_TYPE) \ -+ ((R_TYPE) == R_LARCH_TLS_LE_HI20 \ -+ || (R_TYPE) == R_LARCH_TLS_LE_LO12 \ -+ || (R_TYPE) == R_LARCH_TLS_LE64_LO20 \ -+ || (R_TYPE) == R_LARCH_TLS_LE64_HI12) -+ - /* Generate a PLT header. */ - - static bool -@@ -642,15 +646,18 @@ loongarch_reloc_got_type (unsigned int r_type) - - /* Return true if tls type transition can be performed. */ - static bool --loongarch_can_relax_tls (struct bfd_link_info *info, unsigned int r_type, -- struct elf_link_hash_entry *h, bfd *input_bfd, -- unsigned long r_symndx) -+loongarch_can_trans_tls (bfd *input_bfd, -+ struct bfd_link_info *info, -+ struct elf_link_hash_entry *h, -+ unsigned int r_symndx, -+ unsigned int r_type) - { - char symbol_tls_type; - unsigned int reloc_got_type; - -- if (! (IS_LOONGARCH_TLS_DESC_RELOC (r_type) -- || IS_LOONGARCH_TLS_IE_RELOC (r_type))) -+ /* Only TLS DESC/IE in normal code mode will perform type -+ transition. */ -+ if (! IS_LOONGARCH_TLS_TRANS_RELOC (r_type)) - return false; - - symbol_tls_type = _bfd_loongarch_elf_tls_type (input_bfd, h, r_symndx); -@@ -707,11 +714,13 @@ loongarch_tls_transition_without_check (struct bfd_link_info *info, - } - - static unsigned int --loongarch_tls_transition (struct bfd_link_info *info, unsigned int r_type, -- struct elf_link_hash_entry *h, bfd *input_bfd, -- unsigned long r_symndx) -+loongarch_tls_transition (bfd *input_bfd, -+ struct bfd_link_info *info, -+ struct elf_link_hash_entry *h, -+ unsigned int r_symndx, -+ unsigned int r_type) - { -- if (! loongarch_can_relax_tls (info, r_type, h, input_bfd,r_symndx)) -+ if (! loongarch_can_trans_tls (input_bfd, info, h, r_symndx, r_type)) - return r_type; - - return loongarch_tls_transition_without_check (info, r_type, h); -@@ -818,7 +827,11 @@ loongarch_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, - int need_dynreloc = 0; - int only_need_pcrel = 0; - -- r_type = loongarch_tls_transition (info, r_type, h, abfd, r_symndx); -+ /* Type transitions are only possible with relocations accompanied -+ by R_LARCH_RELAX. */ -+ if (rel + 1 != relocs + sec->reloc_count -+ && ELFNN_R_TYPE (rel[1].r_info) == R_LARCH_RELAX) -+ r_type = loongarch_tls_transition (abfd, info, h, r_symndx, r_type); - switch (r_type) - { - case R_LARCH_GOT_PC_HI20: -@@ -2536,95 +2549,6 @@ loongarch_reloc_is_fatal (struct bfd_link_info *info, - relocation += 0x100000000; \ - }) - --/* Transition instruction sequence to relax instruction sequence. */ --static bool --loongarch_tls_relax (bfd *abfd, asection *sec, Elf_Internal_Rela *rel, -- int r_type, struct elf_link_hash_entry *h, -- struct bfd_link_info *info) --{ -- bool local_exec = bfd_link_executable (info) -- && SYMBOL_REFERENCES_LOCAL (info, h); -- bfd_byte *contents = elf_section_data (sec)->this_hdr.contents; -- unsigned long insn; -- -- switch (r_type) -- { -- case R_LARCH_TLS_DESC_PC_HI20: -- if (local_exec) -- /* DESC -> LE relaxation: -- pcalalau12i $a0,%desc_pc_hi20(var) => -- lu12i.w $a0,%le_hi20(var) -- */ -- bfd_put (32, abfd, LARCH_LU12I_W | LARCH_RD_A0, -- contents + rel->r_offset); -- -- /* DESC -> IE relaxation: -- pcalalau12i $a0,%desc_pc_hi20(var) => -- pcalalau12i $a0,%ie_pc_hi20(var) -- */ -- return true; -- -- case R_LARCH_TLS_DESC_PC_LO12: -- if (local_exec) -- { -- /* DESC -> LE relaxation: -- addi.d $a0,$a0,%desc_pc_lo12(var) => -- ori $a0,$a0,le_lo12(var) -- */ -- insn = LARCH_ORI | LARCH_RD_RJ_A0; -- bfd_put (32, abfd, LARCH_ORI | LARCH_RD_RJ_A0, -- contents + rel->r_offset); -- } -- else -- { -- /* DESC -> IE relaxation: -- addi.d $a0,$a0,%desc_pc_lo12(var) => -- ld.d $a0,$a0,%%ie_pc_lo12 -- */ -- bfd_put (32, abfd, LARCH_LD_D | LARCH_RD_RJ_A0, -- contents + rel->r_offset); -- } -- return true; -- -- case R_LARCH_TLS_DESC_LD: -- case R_LARCH_TLS_DESC_CALL: -- /* DESC -> LE/IE relaxation: -- ld.d $ra,$a0,%desc_ld(var) => NOP -- jirl $ra,$ra,%desc_call(var) => NOP -- */ -- bfd_put (32, abfd, LARCH_NOP, contents + rel->r_offset); -- return true; -- -- case R_LARCH_TLS_IE_PC_HI20: -- if (local_exec) -- { -- /* IE -> LE relaxation: -- pcalalau12i $rd,%ie_pc_hi20(var) => -- lu12i.w $rd,%le_hi20(var) -- */ -- insn = bfd_getl32 (contents + rel->r_offset); -- bfd_put (32, abfd, LARCH_LU12I_W | (insn & 0x1f), -- contents + rel->r_offset); -- } -- return true; -- -- case R_LARCH_TLS_IE_PC_LO12: -- if (local_exec) -- { -- /* IE -> LE relaxation: -- ld.d $rd,$rj,%%ie_pc_lo12 => -- ori $rd,$rj,le_lo12(var) -- */ -- insn = bfd_getl32 (contents + rel->r_offset); -- bfd_put (32, abfd, LARCH_ORI | (insn & 0x3ff), -- contents + rel->r_offset); -- } -- return true; -- } -- -- return false; --} -- - - static int - loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, -@@ -2659,7 +2583,6 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, - const char *name; - bfd_reloc_status_type r = bfd_reloc_ok; - bool is_ie, is_desc, is_undefweak, unresolved_reloc, defined_local; -- unsigned int relaxed_r_type; - bool resolved_local, resolved_dynly, resolved_to_const; - char tls_type; - bfd_vma relocation, off, ie_off, desc_off; -@@ -2791,16 +2714,6 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, - - BFD_ASSERT (!resolved_local || defined_local); - -- relaxed_r_type = loongarch_tls_transition (info, r_type, h, input_bfd, r_symndx); -- if (relaxed_r_type != r_type) -- { -- howto = loongarch_elf_rtype_to_howto (input_bfd, relaxed_r_type); -- BFD_ASSERT (howto != NULL); -- -- if (loongarch_tls_relax (input_bfd, input_section, rel, r_type, h, info)) -- r_type = relaxed_r_type; -- } -- - is_desc = false; - is_ie = false; - switch (r_type) -@@ -4112,6 +4025,116 @@ loongarch_relax_delete_bytes (bfd *abfd, - - return true; - } -+ -+/* Start perform TLS type transition. -+ Currently there are three cases of relocation handled here: -+ DESC -> IE, DEC -> LE and IE -> LE. */ -+static bool -+loongarch_tls_perform_trans (bfd *abfd, asection *sec, -+ Elf_Internal_Rela *rel, -+ struct elf_link_hash_entry *h, -+ struct bfd_link_info *info) -+{ -+ unsigned long insn; -+ bool local_exec = bfd_link_executable (info) -+ && SYMBOL_REFERENCES_LOCAL (info, h); -+ bfd_byte *contents = elf_section_data (sec)->this_hdr.contents; -+ unsigned long r_type = ELFNN_R_TYPE (rel->r_info); -+ unsigned long r_symndx = ELFNN_R_SYM (rel->r_info); -+ -+ switch (r_type) -+ { -+ case R_LARCH_TLS_DESC_PC_HI20: -+ if (local_exec) -+ { -+ /* DESC -> LE relaxation: -+ pcalalau12i $a0,%desc_pc_hi20(var) => -+ lu12i.w $a0,%le_hi20(var) -+ */ -+ bfd_put (32, abfd, LARCH_LU12I_W | LARCH_RD_A0, -+ contents + rel->r_offset); -+ rel->r_info = ELFNN_R_INFO (r_symndx, R_LARCH_TLS_LE_HI20); -+ } -+ else -+ { -+ /* DESC -> IE relaxation: -+ pcalalau12i $a0,%desc_pc_hi20(var) => -+ pcalalau12i $a0,%ie_pc_hi20(var) -+ */ -+ rel->r_info = ELFNN_R_INFO (r_symndx, R_LARCH_TLS_IE_PC_HI20); -+ } -+ return true; -+ -+ case R_LARCH_TLS_DESC_PC_LO12: -+ if (local_exec) -+ { -+ /* DESC -> LE relaxation: -+ addi.d $a0,$a0,%desc_pc_lo12(var) => -+ ori $a0,$a0,le_lo12(var) -+ */ -+ insn = LARCH_ORI | LARCH_RD_RJ_A0; -+ bfd_put (32, abfd, LARCH_ORI | LARCH_RD_RJ_A0, -+ contents + rel->r_offset); -+ rel->r_info = ELFNN_R_INFO (r_symndx, R_LARCH_TLS_LE_LO12); -+ } -+ else -+ { -+ /* DESC -> IE relaxation: -+ addi.d $a0,$a0,%desc_pc_lo12(var) => -+ ld.d $a0,$a0,%ie_pc_lo12(var) -+ */ -+ bfd_put (32, abfd, LARCH_LD_D | LARCH_RD_RJ_A0, -+ contents + rel->r_offset); -+ rel->r_info = ELFNN_R_INFO (r_symndx, R_LARCH_TLS_IE_PC_LO12); -+ } -+ return true; -+ -+ case R_LARCH_TLS_DESC_LD: -+ case R_LARCH_TLS_DESC_CALL: -+ /* DESC -> LE/IE relaxation: -+ ld.d $ra,$a0,%desc_ld(var) => NOP -+ jirl $ra,$ra,%desc_call(var) => NOP -+ */ -+ rel->r_info = ELFNN_R_INFO (0, R_LARCH_NONE); -+ bfd_put (32, abfd, LARCH_NOP, contents + rel->r_offset); -+ /* link with -relax option will delete NOP. */ -+ if (!info->disable_target_specific_optimizations) -+ loongarch_relax_delete_bytes (abfd, sec, rel->r_offset, 4, info); -+ return true; -+ -+ case R_LARCH_TLS_IE_PC_HI20: -+ if (local_exec) -+ { -+ /* IE -> LE relaxation: -+ pcalalau12i $rd,%ie_pc_hi20(var) => -+ lu12i.w $rd,%le_hi20(var) -+ */ -+ insn = bfd_getl32 (contents + rel->r_offset); -+ bfd_put (32, abfd, LARCH_LU12I_W | (insn & 0x1f), -+ contents + rel->r_offset); -+ rel->r_info = ELFNN_R_INFO (r_symndx, R_LARCH_TLS_LE_HI20); -+ } -+ return true; -+ -+ case R_LARCH_TLS_IE_PC_LO12: -+ if (local_exec) -+ { -+ /* IE -> LE relaxation: -+ ld.d $rd,$rj,%%ie_pc_lo12(var) => -+ ori $rd,$rj,le_lo12(var) -+ */ -+ insn = bfd_getl32 (contents + rel->r_offset); -+ bfd_put (32, abfd, LARCH_ORI | (insn & 0x3ff), -+ contents + rel->r_offset); -+ rel->r_info = ELFNN_R_INFO (r_symndx, R_LARCH_TLS_LE_LO12); -+ } -+ return true; -+ } -+ -+ return false; -+} -+ -+ - /* Relax tls le, mainly relax the process of getting TLS le symbolic addresses. - there are three situations in which an assembly instruction sequence needs to - be relaxed: -@@ -4148,6 +4171,21 @@ loongarch_relax_delete_bytes (bfd *abfd, - lu12i.w $rd,%le_hi20_r (sym) ==> (instruction deleted) - add.{w/d} $rd,$rd,$tp,%le_add_r (sym) ==> (instruction deleted) - addi.{w/d} $rs,$rd,%le_lo12_r (sym) ==> addi.{w/d} $rs,$tp,%le_lo12_r (sym) -+ -+ -+ For relocation of all old LE instruction sequences, whether it is -+ a normal code model or an extreme code model, relaxation will be -+ performed when the relaxation conditions are met. -+ -+ nomal code model: -+ lu12i.w $rd,%le_hi20(sym) => (deleted) -+ ori $rd,$rd,le_lo12(sym) => ori $rd,$zero,le_lo12(sym) -+ -+ extreme code model: -+ lu12i.w $rd,%le_hi20(sym) => (deleted) -+ ori $rd,$rd,%le_lo12(sym) => ori $rd,$zero,le_lo12(sym) -+ lu32i.d $rd,%le64_lo20(sym) => (deleted) -+ lu52i.d $rd,$rd,%le64_hi12(sym) => (deleted) - */ - static bool - loongarch_relax_tls_le (bfd *abfd, asection *sec, -@@ -4159,31 +4197,56 @@ loongarch_relax_tls_le (bfd *abfd, asection *sec, - uint32_t insn = bfd_get (32, abfd, contents + rel->r_offset); - static uint32_t insn_rj,insn_rd; - symval = symval - elf_hash_table (link_info)->tls_sec->vma; -- /* Whether the symbol offset is in the interval (offset < 0x800). */ -- if (ELFNN_R_TYPE ((rel + 1)->r_info) == R_LARCH_RELAX && (symval < 0x800)) -+ /* The old LE instruction sequence can be relaxed when the symbol offset -+ is smaller than the 12-bit range. */ -+ if (ELFNN_R_TYPE ((rel + 1)->r_info) == R_LARCH_RELAX && (symval <= 0xfff)) - { - switch (ELFNN_R_TYPE (rel->r_info)) - { -- case R_LARCH_TLS_LE_HI20_R: -- case R_LARCH_TLS_LE_ADD_R: -- /* delete insn. */ -- rel->r_info = ELFNN_R_INFO (0, R_LARCH_NONE); -- loongarch_relax_delete_bytes (abfd, sec, rel->r_offset, 4, link_info); -- break; -- case R_LARCH_TLS_LE_LO12_R: -- /* Change rj to $tp. */ -- insn_rj = 0x2 << 5; -- /* Get rd register. */ -- insn_rd = insn & 0x1f; -- /* Write symbol offset. */ -- symval <<= 10; -- /* Writes the modified instruction. */ -- insn = insn & 0xffc00000; -- insn = insn | symval | insn_rj | insn_rd; -- bfd_put (32, abfd, insn, contents + rel->r_offset); -- break; -- default: -- break; -+ /*if offset < 0x800, then perform the new le instruction -+ sequence relax. */ -+ case R_LARCH_TLS_LE_HI20_R: -+ case R_LARCH_TLS_LE_ADD_R: -+ /* delete insn. */ -+ if (symval < 0x800) -+ { -+ rel->r_info = ELFNN_R_INFO (0, R_LARCH_NONE); -+ loongarch_relax_delete_bytes (abfd, sec, rel->r_offset, -+ 4, link_info); -+ } -+ break; -+ -+ case R_LARCH_TLS_LE_LO12_R: -+ if (symval < 0x800) -+ { -+ /* Change rj to $tp. */ -+ insn_rj = 0x2 << 5; -+ /* Get rd register. */ -+ insn_rd = insn & 0x1f; -+ /* Write symbol offset. */ -+ symval <<= 10; -+ /* Writes the modified instruction. */ -+ insn = insn & 0xffc00000; -+ insn = insn | symval | insn_rj | insn_rd; -+ bfd_put (32, abfd, insn, contents + rel->r_offset); -+ } -+ break; -+ -+ case R_LARCH_TLS_LE_HI20: -+ case R_LARCH_TLS_LE64_LO20: -+ case R_LARCH_TLS_LE64_HI12: -+ rel->r_info = ELFNN_R_INFO (0, R_LARCH_NONE); -+ loongarch_relax_delete_bytes (abfd, sec, rel->r_offset, -+ 4, link_info); -+ break; -+ -+ case R_LARCH_TLS_LE_LO12: -+ bfd_put (32, abfd, LARCH_ORI | (insn & 0x1f), -+ contents + rel->r_offset); -+ break; -+ -+ default: -+ break; - } - } - return true; -@@ -4534,7 +4597,7 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, - R_LARCH_CALL36: symval is the symbol address for local symbols, - or the PLT entry address of the symbol. (Todo) - R_LARCHL_TLS_LD/GD/DESC_PC_HI20: symval is the GOT entry address -- of the symbol. */ -+ of the symbol if transition is not possible. */ - if (r_symndx < symtab_hdr->sh_info) - { - Elf_Internal_Sym *sym = (Elf_Internal_Sym *)symtab_hdr->contents -@@ -4542,22 +4605,24 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, - if (ELF_ST_TYPE (sym->st_info) == STT_GNU_IFUNC) - continue; - -+ /* Only TLS instruction sequences that are accompanied by -+ R_LARCH_RELAX and cannot perform type transition can be -+ relaxed. */ - if (R_LARCH_TLS_LD_PC_HI20 == r_type - || R_LARCH_TLS_GD_PC_HI20 == r_type -- || R_LARCH_TLS_DESC_PC_HI20 == r_type) -+ || (R_LARCH_TLS_DESC_PC_HI20 == r_type -+ && (i + 1 != sec->reloc_count) -+ && ELFNN_R_TYPE (rel[1].r_info) == R_LARCH_RELAX -+ && ! loongarch_can_trans_tls (abfd, info, h, -+ r_symndx, r_type))) - { -- if (loongarch_can_relax_tls (info, r_type, h, abfd, r_symndx)) -- continue; -- else -- { -- sym_sec = htab->elf.sgot; -- symval = elf_local_got_offsets (abfd)[r_symndx]; -- char tls_type = _bfd_loongarch_elf_tls_type (abfd, h, -- r_symndx); -- if (R_LARCH_TLS_DESC_PC_HI20 == r_type -- && GOT_TLS_GD_BOTH_P (tls_type)) -- symval += 2 * GOT_ENTRY_SIZE; -- } -+ sym_sec = htab->elf.sgot; -+ symval = elf_local_got_offsets (abfd)[r_symndx]; -+ char tls_type = _bfd_loongarch_elf_tls_type (abfd, h, -+ r_symndx); -+ if (R_LARCH_TLS_DESC_PC_HI20 == r_type -+ && GOT_TLS_GD_BOTH_P (tls_type)) -+ symval += 2 * GOT_ENTRY_SIZE; - } - else if (sym->st_shndx == SHN_UNDEF || R_LARCH_ALIGN == r_type) - { -@@ -4588,20 +4653,19 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, - shared object. */ - if (R_LARCH_TLS_LD_PC_HI20 == r_type - || R_LARCH_TLS_GD_PC_HI20 == r_type -- || R_LARCH_TLS_DESC_PC_HI20 == r_type) -+ || (R_LARCH_TLS_DESC_PC_HI20 == r_type -+ && (i + 1 != sec->reloc_count) -+ && ELFNN_R_TYPE (rel[1].r_info) == R_LARCH_RELAX -+ && !loongarch_can_trans_tls (abfd, info, h, -+ r_symndx, r_type))) - { -- if (loongarch_can_relax_tls (info, r_type, h, abfd, r_symndx)) -- continue; -- else -- { -- sym_sec = htab->elf.sgot; -- symval = h->got.offset; -- char tls_type = _bfd_loongarch_elf_tls_type (abfd, h, -- r_symndx); -- if (R_LARCH_TLS_DESC_PC_HI20 == r_type -- && GOT_TLS_GD_BOTH_P (tls_type)) -- symval += 2 * GOT_ENTRY_SIZE; -- } -+ sym_sec = htab->elf.sgot; -+ symval = h->got.offset; -+ char tls_type = _bfd_loongarch_elf_tls_type (abfd, h, -+ r_symndx); -+ if (R_LARCH_TLS_DESC_PC_HI20 == r_type -+ && GOT_TLS_GD_BOTH_P (tls_type)) -+ symval += 2 * GOT_ENTRY_SIZE; - } - else if ((h->root.type == bfd_link_hash_defined - || h->root.type == bfd_link_hash_defweak) -@@ -4646,6 +4710,24 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, - - symval += sec_addr (sym_sec); - -+ /* If the conditions for tls type transition are met, type -+ transition is performed instead of relax. -+ During the transition from DESC->IE/LE, there are 2 situations -+ depending on the different configurations of the relax/norelax -+ option. -+ If the -relax option is used, the extra nops will be removed, -+ and this transition is performed in pass 0. -+ If the --no-relax option is used, nop will be retained, and -+ this transition is performed in pass 1. */ -+ if (IS_LOONGARCH_TLS_TRANS_RELOC (r_type) -+ && (i + 1 != sec->reloc_count) -+ && ELFNN_R_TYPE (rel[1].r_info) == R_LARCH_RELAX -+ && loongarch_can_trans_tls (abfd, info, h, r_symndx, r_type)) -+ { -+ loongarch_tls_perform_trans (abfd, sec, rel, h, info); -+ r_type = ELFNN_R_TYPE (rel->r_info); -+ } -+ - switch (r_type) - { - case R_LARCH_ALIGN: -@@ -4664,6 +4746,10 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, - case R_LARCH_TLS_LE_HI20_R: - case R_LARCH_TLS_LE_LO12_R: - case R_LARCH_TLS_LE_ADD_R: -+ case R_LARCH_TLS_LE_HI20: -+ case R_LARCH_TLS_LE_LO12: -+ case R_LARCH_TLS_LE64_LO20: -+ case R_LARCH_TLS_LE64_HI12: - if (0 == info->relax_pass && (i + 2) <= sec->reloc_count) - loongarch_relax_tls_le (abfd, sec, rel, info, symval); - break; -diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c -index e6da4e1e..b510d228 100644 ---- a/gas/config/tc-loongarch.c -+++ b/gas/config/tc-loongarch.c -@@ -716,7 +716,11 @@ loongarch_args_parser_can_match_arg_helper (char esc_ch1, char esc_ch2, - - if (LARCH_opts.relax - && (BFD_RELOC_LARCH_TLS_LE_HI20_R == reloc_type -- || BFD_RELOC_LARCH_TLS_LE_LO12_R == reloc_type)) -+ || BFD_RELOC_LARCH_TLS_LE_LO12_R == reloc_type -+ || BFD_RELOC_LARCH_TLS_LE_HI20 == reloc_type -+ || BFD_RELOC_LARCH_TLS_LE_LO12 == reloc_type -+ || BFD_RELOC_LARCH_TLS_LE64_LO20 == reloc_type -+ || BFD_RELOC_LARCH_TLS_LE64_HI12 == reloc_type)) - { - ip->reloc_info[ip->reloc_num].type = BFD_RELOC_LARCH_RELAX; - ip->reloc_info[ip->reloc_num].value = const_0; -@@ -724,8 +728,12 @@ loongarch_args_parser_can_match_arg_helper (char esc_ch1, char esc_ch2, - } - - /* Only one register macros (used in normal code model) -- emit R_LARCH_RELAX. */ -+ emit R_LARCH_RELAX. -+ LARCH_opts.ase_labs and LARCH_opts.ase_gabs are used -+ to generate the code model of absolute addresses, and -+ we do not relax this code model. */ - if (LARCH_opts.relax && (ip->expand_from_macro & 1) -+ && !(LARCH_opts.ase_labs | LARCH_opts.ase_gabs) - && (BFD_RELOC_LARCH_PCALA_HI20 == reloc_type - || BFD_RELOC_LARCH_PCALA_LO12 == reloc_type - || BFD_RELOC_LARCH_GOT_PC_HI20 == reloc_type -@@ -733,7 +741,11 @@ loongarch_args_parser_can_match_arg_helper (char esc_ch1, char esc_ch2, - || BFD_RELOC_LARCH_TLS_LD_PC_HI20 == reloc_type - || BFD_RELOC_LARCH_TLS_GD_PC_HI20 == reloc_type - || BFD_RELOC_LARCH_TLS_DESC_PC_HI20 == reloc_type -- || BFD_RELOC_LARCH_TLS_DESC_PC_LO12 == reloc_type)) -+ || BFD_RELOC_LARCH_TLS_DESC_PC_LO12 == reloc_type -+ || BFD_RELOC_LARCH_TLS_DESC_LD == reloc_type -+ || BFD_RELOC_LARCH_TLS_DESC_CALL == reloc_type -+ || BFD_RELOC_LARCH_TLS_IE_PC_HI20 == reloc_type -+ || BFD_RELOC_LARCH_TLS_IE_PC_LO12 == reloc_type)) - { - ip->reloc_info[ip->reloc_num].type = BFD_RELOC_LARCH_RELAX; - ip->reloc_info[ip->reloc_num].value = const_0; -@@ -1080,7 +1092,11 @@ append_fixp_and_insn (struct loongarch_cl_insn *ip) - if (symbol_get_frag (to) == symbol_get_frag (from))) - - For macro instructions, only the first instruction expanded from macro -- need to start a new frag. */ -+ need to start a new frag. -+ Since the relocations of the normal code model and the extreme code model -+ of the old LE instruction sequence are the same, it is impossible to -+ distinguish which code model it is based on relocation alone, so the -+ extreme code model has to be relaxed. */ - if (LARCH_opts.relax - && (BFD_RELOC_LARCH_PCALA_HI20 == reloc_info[0].type - || BFD_RELOC_LARCH_GOT_PC_HI20 == reloc_info[0].type -@@ -1088,7 +1104,12 @@ append_fixp_and_insn (struct loongarch_cl_insn *ip) - || BFD_RELOC_LARCH_TLS_LE_ADD_R == reloc_info[0].type - || BFD_RELOC_LARCH_TLS_LD_PC_HI20 == reloc_info[0].type - || BFD_RELOC_LARCH_TLS_GD_PC_HI20 == reloc_info[0].type -- || BFD_RELOC_LARCH_TLS_DESC_PC_HI20 == reloc_info[0].type)) -+ || BFD_RELOC_LARCH_TLS_DESC_PC_HI20 == reloc_info[0].type -+ || BFD_RELOC_LARCH_TLS_IE_PC_HI20 == reloc_info[0].type -+ || BFD_RELOC_LARCH_TLS_LE_HI20 == reloc_info[0].type -+ || BFD_RELOC_LARCH_TLS_LE_LO12 == reloc_info[0].type -+ || BFD_RELOC_LARCH_TLS_LE64_LO20 == reloc_info[0].type -+ || BFD_RELOC_LARCH_TLS_LE64_HI12 == reloc_info[0].type)) - { - frag_wane (frag_now); - frag_new (0); --- -2.33.0 - diff --git a/LoongArch-Directly-delete-relaxed-instuctions-in-fir.patch b/LoongArch-Directly-delete-relaxed-instuctions-in-fir.patch deleted file mode 100644 index fd9e585..0000000 --- a/LoongArch-Directly-delete-relaxed-instuctions-in-fir.patch +++ /dev/null @@ -1,60 +0,0 @@ -From 4e94082d95e046f357409cd689ffeedd60f6c673 Mon Sep 17 00:00:00 2001 -From: mengqinggang -Date: Thu, 16 Nov 2023 19:19:12 +0800 -Subject: [PATCH] LoongArch: Directly delete relaxed instuctions in first - relaxation pass - -Directly delete relaxed instuctions in first relaxation pass, not use -R_LARCH_DELETE relocation. If not, the PC-relative offset may increase. - -Signed-off-by: Peng Fan ---- - bfd/elfnn-loongarch.c | 12 +++++++----- - 1 file changed, 7 insertions(+), 5 deletions(-) - -diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c -index 1162cb35cd6..9d4ea7e4ae7 100644 ---- a/bfd/elfnn-loongarch.c -+++ b/bfd/elfnn-loongarch.c -@@ -3739,7 +3739,8 @@ loongarch_relax_delete_bytes (bfd *abfd, - /* Relax pcalau12i,addi.d => pcaddi. */ - static bool - loongarch_relax_pcala_addi (bfd *abfd, asection *sec, -- Elf_Internal_Rela *rel_hi, bfd_vma symval) -+ Elf_Internal_Rela *rel_hi, bfd_vma symval, -+ struct bfd_link_info *info) - { - bfd_byte *contents = elf_section_data (sec)->this_hdr.contents; - Elf_Internal_Rela *rel_lo = rel_hi + 2; -@@ -3771,8 +3772,9 @@ loongarch_relax_pcala_addi (bfd *abfd, asection *sec, - /* Adjust relocations. */ - rel_hi->r_info = ELFNN_R_INFO (ELFNN_R_SYM (rel_hi->r_info), - R_LARCH_PCREL20_S2); -- rel_lo->r_info = ELFNN_R_INFO (ELFNN_R_SYM (rel_hi->r_info), -- R_LARCH_DELETE); -+ rel_lo->r_info = ELFNN_R_INFO (0, R_LARCH_NONE); -+ -+ loongarch_relax_delete_bytes (abfd, sec, rel_lo->r_offset, 4, info); - - return true; - } -@@ -4004,14 +4006,14 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, - break; - case R_LARCH_PCALA_HI20: - if (0 == info->relax_pass && (i + 4) <= sec->reloc_count) -- loongarch_relax_pcala_addi (abfd, sec, rel, symval); -+ loongarch_relax_pcala_addi (abfd, sec, rel, symval, info); - break; - case R_LARCH_GOT_PC_HI20: - if (local_got && 0 == info->relax_pass - && (i + 4) <= sec->reloc_count) - { - if (loongarch_relax_pcala_ld (abfd, sec, rel)) -- loongarch_relax_pcala_addi (abfd, sec, rel, symval); -+ loongarch_relax_pcala_addi (abfd, sec, rel, symval, info); - } - break; - default: --- -2.33.0 - diff --git a/LoongArch-Disable-linker-relaxation-if-set-the-addre.patch b/LoongArch-Disable-linker-relaxation-if-set-the-addre.patch deleted file mode 100644 index cf188c7..0000000 --- a/LoongArch-Disable-linker-relaxation-if-set-the-addre.patch +++ /dev/null @@ -1,87 +0,0 @@ -From 9bdf2be420d4477838bfb11d9cd4c2d6ad257119 Mon Sep 17 00:00:00 2001 -From: mengqinggang -Date: Thu, 30 May 2024 19:52:34 +0800 -Subject: [PATCH 090/123] LoongArch: Disable linker relaxation if set the - address of section or segment - -If set the address of section or segment, the offset from pc to symbol -may become bigger and cause overflow. ---- - ld/emultempl/loongarchelf.em | 16 ++++++++++++++++ - ld/testsuite/ld-loongarch-elf/relax-ttext.s | 13 +++++++++++++ - ld/testsuite/ld-loongarch-elf/relax.exp | 12 ++++++++++++ - 3 files changed, 41 insertions(+) - create mode 100644 ld/testsuite/ld-loongarch-elf/relax-ttext.s - -diff --git a/ld/emultempl/loongarchelf.em b/ld/emultempl/loongarchelf.em -index 99749894..13f8dacb 100644 ---- a/ld/emultempl/loongarchelf.em -+++ b/ld/emultempl/loongarchelf.em -@@ -25,6 +25,22 @@ fragment <= 0x200000, overflow -+.text -+.align 14 # delete at relax pass 1 -+.fill 0x4000 -+.align 14 # delete at relax pass 1 -+la.local $t2, a # relax to pcaddi at relax pass 0 -+ -+.section ".text1", "ax" -+ .fill 0x4000 -+a: # 0x120204000 -+ ret -diff --git a/ld/testsuite/ld-loongarch-elf/relax.exp b/ld/testsuite/ld-loongarch-elf/relax.exp -index 05c4ed0a..05b268f4 100644 ---- a/ld/testsuite/ld-loongarch-elf/relax.exp -+++ b/ld/testsuite/ld-loongarch-elf/relax.exp -@@ -51,6 +51,18 @@ if [istarget loongarch64-*-*] { - run_dump_test "relax-align-ignore-start" - run_partial_linking_align_test - -+ run_ld_link_tests \ -+ [list \ -+ [list \ -+ "loongarch relax ttext" \ -+ "" "" \ -+ "" \ -+ {relax-ttext.s} \ -+ {} \ -+ "relax-ttext" \ -+ ] \ -+ ] -+ - set testname "loongarch relax .exe build" - set pre_builds [list \ - [list \ --- -2.33.0 - diff --git a/LoongArch-Discard-extra-spaces-in-objdump-output.patch b/LoongArch-Discard-extra-spaces-in-objdump-output.patch deleted file mode 100644 index 5f82cf8..0000000 --- a/LoongArch-Discard-extra-spaces-in-objdump-output.patch +++ /dev/null @@ -1,131 +0,0 @@ -From c65840dfbeb0e2b292439b3627a0a29436649845 Mon Sep 17 00:00:00 2001 -From: Lulu Cai -Date: Wed, 3 Jan 2024 19:57:10 +0800 -Subject: [PATCH 041/123] LoongArch: Discard extra spaces in objdump output - -Due to the formatted output of objdump, some instructions -that do not require output operands (such as nop/ret) will -have extra spaces added after them. - -Determine whether to output operands through the format -of opcodes. When opc->format is an empty string, no extra -spaces are output. ---- - gas/testsuite/gas/loongarch/64_pcrel.d | 2 +- - .../gas/loongarch/deprecated_reg_aliases.d | 2 +- - gas/testsuite/gas/loongarch/jmp_op.d | 4 ++-- - gas/testsuite/gas/loongarch/nop.d | 2 +- - gas/testsuite/gas/loongarch/privilege_op.d | 14 +++++++------- - gas/testsuite/gas/loongarch/reloc.d | 2 +- - opcodes/loongarch-dis.c | 7 ++++++- - 7 files changed, 19 insertions(+), 14 deletions(-) - -diff --git a/gas/testsuite/gas/loongarch/64_pcrel.d b/gas/testsuite/gas/loongarch/64_pcrel.d -index 66b80a39..642e3079 100644 ---- a/gas/testsuite/gas/loongarch/64_pcrel.d -+++ b/gas/testsuite/gas/loongarch/64_pcrel.d -@@ -7,5 +7,5 @@ - Disassembly of section .text: - - 00000000.* <.text>: --[ ]+0:[ ]+03400000[ ]+nop[ ]+ -+[ ]+0:[ ]+03400000[ ]+nop - [ ]+0:[ ]+R_LARCH_64_PCREL[ ]+\*ABS\* -diff --git a/gas/testsuite/gas/loongarch/deprecated_reg_aliases.d b/gas/testsuite/gas/loongarch/deprecated_reg_aliases.d -index 3ea08067..01e593fb 100644 ---- a/gas/testsuite/gas/loongarch/deprecated_reg_aliases.d -+++ b/gas/testsuite/gas/loongarch/deprecated_reg_aliases.d -@@ -15,4 +15,4 @@ Disassembly of section .text: - [ ]+8:[ ]+16024685[ ]+lu32i\.d[ ]+\$a1, 4660 - [ ]+c:[ ]+08200420[ ]+fmadd\.d[ ]+\$fa0, \$fa1, \$fa1, \$fa0 - [ ]+10:[ ]+380c16a4[ ]+ldx\.d[ ]+\$a0, \$r21, \$a1 --[ ]+14:[ ]+4c000020[ ]+ret[ ]+ -+[ ]+14:[ ]+4c000020[ ]+ret -diff --git a/gas/testsuite/gas/loongarch/jmp_op.d b/gas/testsuite/gas/loongarch/jmp_op.d -index cc544f11..21576072 100644 ---- a/gas/testsuite/gas/loongarch/jmp_op.d -+++ b/gas/testsuite/gas/loongarch/jmp_op.d -@@ -7,7 +7,7 @@ - Disassembly of section .text: - - 00000000.* <.L1>: --[ ]+0:[ ]+03400000[ ]+nop[ ]+ -+[ ]+0:[ ]+03400000[ ]+nop - [ ]+4:[ ]+63fffc04[ ]+bgtz[ ]+\$a0,[ ]+-4[ ]+#[ ]+0[ ]+<\.L1> - [ ]+4:[ ]+R_LARCH_B16[ ]+\.L1 - [ ]+8:[ ]+67fff880[ ]+bgez[ ]+\$a0,[ ]+-8[ ]+#[ ]+0[ ]+<\.L1> -@@ -47,4 +47,4 @@ Disassembly of section .text: - [ ]+4c:[ ]+R_LARCH_B16[ ]+\.L1 - [ ]+50:[ ]+6fffb0a4[ ]+bgeu[ ]+\$a1,[ ]+\$a0,[ ]+-80[ ]+#[ ]+0[ ]+<\.L1> - [ ]+50:[ ]+R_LARCH_B16[ ]+\.L1 --[ ]+54:[ ]+4c000020[ ]+ret[ ]+ -+[ ]+54:[ ]+4c000020[ ]+ret -diff --git a/gas/testsuite/gas/loongarch/nop.d b/gas/testsuite/gas/loongarch/nop.d -index 222456e8..ca8c5630 100644 ---- a/gas/testsuite/gas/loongarch/nop.d -+++ b/gas/testsuite/gas/loongarch/nop.d -@@ -7,4 +7,4 @@ - Disassembly of section .text: - - 0+000 : --[ ]+0:[ ]+03400000[ ]+nop[ ]+ -+[ ]+0:[ ]+03400000[ ]+nop -diff --git a/gas/testsuite/gas/loongarch/privilege_op.d b/gas/testsuite/gas/loongarch/privilege_op.d -index 73925f21..e9ca60b2 100644 ---- a/gas/testsuite/gas/loongarch/privilege_op.d -+++ b/gas/testsuite/gas/loongarch/privilege_op.d -@@ -31,13 +31,13 @@ Disassembly of section .text: - [ ]+54:[ ]+064814a4 [ ]+iocsrwr.h[ ]+[ ]+\$a0, \$a1 - [ ]+58:[ ]+064818a4 [ ]+iocsrwr.w[ ]+[ ]+\$a0, \$a1 - [ ]+5c:[ ]+06481ca4 [ ]+iocsrwr.d[ ]+[ ]+\$a0, \$a1 --[ ]+60:[ ]+06482000 [ ]+tlbclr[ ]+ --[ ]+64:[ ]+06482400 [ ]+tlbflush[ ]+ --[ ]+68:[ ]+06482800 [ ]+tlbsrch[ ]+ --[ ]+6c:[ ]+06482c00 [ ]+tlbrd[ ]+ --[ ]+70:[ ]+06483000 [ ]+tlbwr[ ]+ --[ ]+74:[ ]+06483400 [ ]+tlbfill[ ]+ --[ ]+78:[ ]+06483800 [ ]+ertn[ ]+ -+[ ]+60:[ ]+06482000 [ ]+tlbclr -+[ ]+64:[ ]+06482400 [ ]+tlbflush -+[ ]+68:[ ]+06482800 [ ]+tlbsrch -+[ ]+6c:[ ]+06482c00 [ ]+tlbrd -+[ ]+70:[ ]+06483000 [ ]+tlbwr -+[ ]+74:[ ]+06483400 [ ]+tlbfill -+[ ]+78:[ ]+06483800 [ ]+ertn - [ ]+7c:[ ]+06488000 [ ]+idle[ ]+[ ]+0x0 - [ ]+80:[ ]+0648ffff [ ]+idle[ ]+[ ]+0x7fff - [ ]+84:[ ]+064998a0 [ ]+invtlb[ ]+[ ]+0x0, \$a1, \$a2 -diff --git a/gas/testsuite/gas/loongarch/reloc.d b/gas/testsuite/gas/loongarch/reloc.d -index 0458830f..fa249c58 100644 ---- a/gas/testsuite/gas/loongarch/reloc.d -+++ b/gas/testsuite/gas/loongarch/reloc.d -@@ -8,7 +8,7 @@ - Disassembly of section .text: - - 00000000.* <.text>: --[ ]+0:[ ]+03400000[ ]+nop[ ]+ -+[ ]+0:[ ]+03400000[ ]+nop - [ ]+4:[ ]+58000085[ ]+beq[ ]+\$a0,[ ]+\$a1,[ ]+0[ ]+#[ ]+0x4 - [ ]+4:[ ]+R_LARCH_B16[ ]+.L1 - [ ]+8:[ ]+5c000085[ ]+bne[ ]+\$a0,[ ]+\$a1,[ ]+0[ ]+#[ ]+0x8 -diff --git a/opcodes/loongarch-dis.c b/opcodes/loongarch-dis.c -index 969ea28f..941bf363 100644 ---- a/opcodes/loongarch-dis.c -+++ b/opcodes/loongarch-dis.c -@@ -267,7 +267,12 @@ disassemble_one (insn_t insn, struct disassemble_info *info) - } - - info->insn_type = dis_nonbranch; -- info->fprintf_styled_func (info->stream, dis_style_mnemonic, "%-12s", opc->name); -+ if (opc->format == NULL || opc->format[0] == '\0') -+ info->fprintf_styled_func (info->stream, dis_style_mnemonic, -+ "%s", opc->name); -+ else -+ info->fprintf_styled_func (info->stream, dis_style_mnemonic, -+ "%-12s", opc->name); - - { - char *fake_args = xmalloc (strlen (opc->format) + 1); --- -2.33.0 - diff --git a/LoongArch-Do-not-add-DF_STATIC_TLS-for-TLS-LE.patch b/LoongArch-Do-not-add-DF_STATIC_TLS-for-TLS-LE.patch deleted file mode 100644 index eda5f2c..0000000 --- a/LoongArch-Do-not-add-DF_STATIC_TLS-for-TLS-LE.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 85e65d5f829b23397ad39ad610589421e29c0e32 Mon Sep 17 00:00:00 2001 -From: Tatsuyuki Ishi -Date: Thu, 28 Dec 2023 23:58:00 +0900 -Subject: [PATCH 047/123] LoongArch: Do not add DF_STATIC_TLS for TLS LE - -TLS LE is exclusively for executables, while DF_STATIC_TLS is for DLLs. -DF_STATIC_TLS should only be set for TLS IE (and when it's DLL), not LE. ---- - bfd/elfnn-loongarch.c | 2 -- - 1 file changed, 2 deletions(-) - -diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c -index b0ebe89e..f57b6152 100644 ---- a/bfd/elfnn-loongarch.c -+++ b/bfd/elfnn-loongarch.c -@@ -863,8 +863,6 @@ loongarch_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, - if (!bfd_link_executable (info)) - return false; - -- info->flags |= DF_STATIC_TLS; -- - if (!loongarch_elf_record_tls_and_got_reference (abfd, info, h, - r_symndx, - GOT_TLS_LE)) --- -2.33.0 - diff --git a/LoongArch-Do-not-check-R_LARCH_SOP_PUSH_ABSOLUTE-to-.patch b/LoongArch-Do-not-check-R_LARCH_SOP_PUSH_ABSOLUTE-to-.patch deleted file mode 100644 index ae6d969..0000000 --- a/LoongArch-Do-not-check-R_LARCH_SOP_PUSH_ABSOLUTE-to-.patch +++ /dev/null @@ -1,55 +0,0 @@ -From 1f00570084528ffcc4764a7f31307e2b5d233301 Mon Sep 17 00:00:00 2001 -From: Lulu Cai -Date: Wed, 19 Jun 2024 11:00:36 +0800 -Subject: [PATCH 093/123] LoongArch: Do not check R_LARCH_SOP_PUSH_ABSOLUTE to - avoid broken links to old object files - -R_LARCH_SOP_PUSH_ABSOLUTE with -fPIC was heavily used in the era of gas-2.38. -We do not check this relocation to prevent broken links with old object -files. ---- - bfd/elfnn-loongarch.c | 11 ++++++----- - 1 file changed, 6 insertions(+), 5 deletions(-) - -diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c -index 51e3d311..840cdd35 100644 ---- a/bfd/elfnn-loongarch.c -+++ b/bfd/elfnn-loongarch.c -@@ -756,10 +756,6 @@ loongarch_tls_transition (bfd *input_bfd, - return loongarch_tls_transition_without_check (info, r_type, h); - } - --/* Look through the relocs for a section during the first phase, and -- allocate space in the global offset table or procedure linkage -- table. */ -- - static bool - bad_static_reloc (bfd *abfd, const Elf_Internal_Rela *rel, asection *sec, - unsigned r_type, struct elf_link_hash_entry *h, -@@ -787,6 +783,10 @@ bad_static_reloc (bfd *abfd, const Elf_Internal_Rela *rel, asection *sec, - return false; - } - -+/* Look through the relocs for a section during the first phase, and -+ allocate space in the global offset table or procedure linkage -+ table. */ -+ - static bool - loongarch_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, - asection *sec, const Elf_Internal_Rela *relocs) -@@ -948,10 +948,11 @@ loongarch_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, - break; - - case R_LARCH_ABS_HI20: -- case R_LARCH_SOP_PUSH_ABSOLUTE: - if (bfd_link_pic (info)) - return bad_static_reloc (abfd, rel, sec, r_type, h, isym); - -+ /* Fall through. */ -+ case R_LARCH_SOP_PUSH_ABSOLUTE: - if (h != NULL) - /* If this reloc is in a read-only section, we might - need a copy reloc. We can't check reliably at this --- -2.33.0 - diff --git a/LoongArch-Do-not-emit-R_LARCH_RELAX-for-two-register.patch b/LoongArch-Do-not-emit-R_LARCH_RELAX-for-two-register.patch deleted file mode 100644 index 09093b9..0000000 --- a/LoongArch-Do-not-emit-R_LARCH_RELAX-for-two-register.patch +++ /dev/null @@ -1,754 +0,0 @@ -From ef4712b21aa2ab233282bc3aa38f21e6957a9db9 Mon Sep 17 00:00:00 2001 -From: mengqinggang -Date: Wed, 10 Jan 2024 09:55:13 +0800 -Subject: [PATCH 045/123] LoongArch: Do not emit R_LARCH_RELAX for two register - macros - -For two register macros (e.g. la.local $t0, $t1, symbol) used in extreme code -model, do not emit R_LARCH_RELAX relocations. ---- - gas/config/tc-loongarch.c | 45 ++- - .../gas/loongarch/macro_op_extreme_pc.d | 151 ++++--- - .../gas/loongarch/tlsdesc_large_pc.d | 58 ++- - ld/testsuite/ld-loongarch-elf/macro_op.d | 376 +++++++++--------- - 4 files changed, 311 insertions(+), 319 deletions(-) - -diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c -index fad18fcd..1ae57b45 100644 ---- a/gas/config/tc-loongarch.c -+++ b/gas/config/tc-loongarch.c -@@ -71,7 +71,17 @@ struct loongarch_cl_insn - long where; - /* The relocs associated with the instruction, if any. */ - fixS *fixp[MAX_RELOC_NUMBER_A_INSN]; -- long macro_id; -+ /* Represents macros or instructions expanded from macro. -+ For la.local -> la.pcrel or la.pcrel -> pcalau12i + addi.d, la.pcrel, -+ pcalau12i and addi.d are expanded from macro. -+ The first bit represents expanded from one register macro (e.g. -+ la.local $t0, symbol) and emit R_LARCH_RELAX relocations. -+ The second bit represents expanded from two registers macro (e.g. -+ la.local $t0, $t1, symbol) and not emit R_LARCH_RELAX relocations. -+ -+ The macros or instructions expanded from macros do not output register -+ deprecated warning. */ -+ unsigned int expand_from_macro; - }; - - #ifndef DEFAULT_ARCH -@@ -722,7 +732,10 @@ loongarch_args_parser_can_match_arg_helper (char esc_ch1, char esc_ch2, - ip->reloc_info[ip->reloc_num].value = const_0; - ip->reloc_num++; - } -- if (LARCH_opts.relax && ip->macro_id -+ -+ /* Only one register macros (used in normal code model) -+ emit R_LARCH_RELAX. */ -+ if (LARCH_opts.relax && (ip->expand_from_macro & 1) - && (BFD_RELOC_LARCH_PCALA_HI20 == reloc_type - || BFD_RELOC_LARCH_PCALA_LO12 == reloc_type - || BFD_RELOC_LARCH_GOT_PC_HI20 == reloc_type -@@ -754,7 +767,9 @@ loongarch_args_parser_can_match_arg_helper (char esc_ch1, char esc_ch2, - imm = (intptr_t) str_hash_find (r_deprecated_htab, arg); - ip->match_now = 0 < imm; - ret = imm - 1; -- if (ip->match_now && !ip->macro_id) -+ /* !ip->expand_from_macro: avoiding duplicate output warnings, -+ only the first macro output warning. */ -+ if (ip->match_now && !ip->expand_from_macro) - as_warn (_("register alias %s is deprecated, use %s instead"), - arg, r_abi_names[ret]); - break; -@@ -773,7 +788,7 @@ loongarch_args_parser_can_match_arg_helper (char esc_ch1, char esc_ch2, - } - ip->match_now = 0 < imm; - ret = imm - 1; -- if (ip->match_now && !ip->macro_id) -+ if (ip->match_now && !ip->expand_from_macro) - break; - /* Handle potential usage of deprecated register aliases. */ - imm = (intptr_t) str_hash_find (f_deprecated_htab, arg); -@@ -1172,7 +1187,7 @@ assember_macro_helper (const char *const args[], void *context_ptr) - * assuming 'not starting with space and not ending with space' or pass in - * empty c_str. */ - static void --loongarch_assemble_INSNs (char *str, struct loongarch_cl_insn *ctx) -+loongarch_assemble_INSNs (char *str, unsigned int expand_from_macro) - { - char *rest; - size_t len_str = strlen(str); -@@ -1195,7 +1210,7 @@ loongarch_assemble_INSNs (char *str, struct loongarch_cl_insn *ctx) - - struct loongarch_cl_insn the_one = { 0 }; - the_one.name = str; -- the_one.macro_id = ctx->macro_id; -+ the_one.expand_from_macro = expand_from_macro; - - for (; *str && *str != ' '; str++) - ; -@@ -1217,29 +1232,37 @@ loongarch_assemble_INSNs (char *str, struct loongarch_cl_insn *ctx) - break; - - append_fixp_and_insn (&the_one); -+ -+ /* Expanding macro instructions. */ - if (the_one.insn_length == 0 && the_one.insn->macro) - { -- the_one.macro_id = 1; -+ unsigned int new_expand_from_macro = 0; -+ if (2 == the_one.arg_num) -+ new_expand_from_macro |= 1; -+ else if (3 == the_one.arg_num) -+ new_expand_from_macro |= 2; - - char *c_str = loongarch_expand_macro (the_one.insn->macro, - the_one.arg_strs, - assember_macro_helper, - &the_one, len_str); -- loongarch_assemble_INSNs (c_str, &the_one); -+ /* The first instruction expanded from macro. */ -+ loongarch_assemble_INSNs (c_str, new_expand_from_macro); - free (c_str); - } - } - while (0); - -+ /* The rest instructions expanded from macro, split by semicolon(;), -+ assembly one by one. */ - if (*rest != '\0') -- loongarch_assemble_INSNs (rest, ctx); -+ loongarch_assemble_INSNs (rest, expand_from_macro); - } - - void - md_assemble (char *str) - { -- struct loongarch_cl_insn the_one = { 0 }; -- loongarch_assemble_INSNs (str, &the_one); -+ loongarch_assemble_INSNs (str, 0); - } - - const char * -diff --git a/gas/testsuite/gas/loongarch/macro_op_extreme_pc.d b/gas/testsuite/gas/loongarch/macro_op_extreme_pc.d -index 8e4b6e6c..68fbb338 100644 ---- a/gas/testsuite/gas/loongarch/macro_op_extreme_pc.d -+++ b/gas/testsuite/gas/loongarch/macro_op_extreme_pc.d -@@ -2,87 +2,76 @@ - #objdump: -dr - #skip: loongarch32-*-* - --.*: file format .* -+.*:[ ]+file format .* -+ - - Disassembly of section .text: - --0+ <.L1>: -- 0: 1a000004 pcalau12i \$a0, 0 -- 0: R_LARCH_PCALA_HI20 .L1 -- 0: R_LARCH_RELAX \*ABS\* -- 4: 02c00005 li.d \$a1, 0 -- 4: R_LARCH_PCALA_LO12 .L1 -- 4: R_LARCH_RELAX \*ABS\* -- 8: 16000005 lu32i.d \$a1, 0 -- 8: R_LARCH_PCALA64_LO20 .L1 -- c: 030000a5 lu52i.d \$a1, \$a1, 0 -- c: R_LARCH_PCALA64_HI12 .L1 -- 10: 00109484 add.d \$a0, \$a0, \$a1 -- 14: 1a000004 pcalau12i \$a0, 0 -- 14: R_LARCH_PCALA_HI20 .L1 -- 14: R_LARCH_RELAX \*ABS\* -- 18: 02c00005 li.d \$a1, 0 -- 18: R_LARCH_PCALA_LO12 .L1 -- 18: R_LARCH_RELAX \*ABS\* -- 1c: 16000005 lu32i.d \$a1, 0 -- 1c: R_LARCH_PCALA64_LO20 .L1 -- 20: 030000a5 lu52i.d \$a1, \$a1, 0 -- 20: R_LARCH_PCALA64_HI12 .L1 -- 24: 00109484 add.d \$a0, \$a0, \$a1 -- 28: 1a000004 pcalau12i \$a0, 0 -- 28: R_LARCH_PCALA_HI20 .L1 -- 28: R_LARCH_RELAX \*ABS\* -- 2c: 02c00005 li.d \$a1, 0 -- 2c: R_LARCH_PCALA_LO12 .L1 -- 2c: R_LARCH_RELAX \*ABS\* -- 30: 16000005 lu32i.d \$a1, 0 -- 30: R_LARCH_PCALA64_LO20 .L1 -- 34: 030000a5 lu52i.d \$a1, \$a1, 0 -- 34: R_LARCH_PCALA64_HI12 .L1 -- 38: 00109484 add.d \$a0, \$a0, \$a1 -- 3c: 1a000004 pcalau12i \$a0, 0 -- 3c: R_LARCH_GOT_PC_HI20 .L1 -- 3c: R_LARCH_RELAX \*ABS\* -- 40: 02c00005 li.d \$a1, 0 -- 40: R_LARCH_GOT_PC_LO12 .L1 -- 40: R_LARCH_RELAX \*ABS\* -- 44: 16000005 lu32i.d \$a1, 0 -- 44: R_LARCH_GOT64_PC_LO20 .L1 -- 48: 030000a5 lu52i.d \$a1, \$a1, 0 -- 48: R_LARCH_GOT64_PC_HI12 .L1 -- 4c: 380c1484 ldx.d \$a0, \$a0, \$a1 -- 50: 14000004 lu12i.w \$a0, 0 -- 50: R_LARCH_TLS_LE_HI20 TLS1 -- 54: 03800084 ori \$a0, \$a0, 0x0 -- 54: R_LARCH_TLS_LE_LO12 TLS1 -- 58: 1a000004 pcalau12i \$a0, 0 -- 58: R_LARCH_TLS_IE_PC_HI20 TLS1 -- 5c: 02c00005 li.d \$a1, 0 -- 5c: R_LARCH_TLS_IE_PC_LO12 TLS1 -- 60: 16000005 lu32i.d \$a1, 0 -- 60: R_LARCH_TLS_IE64_PC_LO20 TLS1 -- 64: 030000a5 lu52i.d \$a1, \$a1, 0 -- 64: R_LARCH_TLS_IE64_PC_HI12 TLS1 -- 68: 380c1484 ldx.d \$a0, \$a0, \$a1 -- 6c: 1a000004 pcalau12i \$a0, 0 -- 6c: R_LARCH_TLS_LD_PC_HI20 TLS1 -- 6c: R_LARCH_RELAX \*ABS\* -- 70: 02c00005 li.d \$a1, 0 -- 70: R_LARCH_GOT_PC_LO12 TLS1 -- 70: R_LARCH_RELAX \*ABS\* -- 74: 16000005 lu32i.d \$a1, 0 -- 74: R_LARCH_GOT64_PC_LO20 TLS1 -- 78: 030000a5 lu52i.d \$a1, \$a1, 0 -- 78: R_LARCH_GOT64_PC_HI12 TLS1 -- 7c: 00109484 add.d \$a0, \$a0, \$a1 -- 80: 1a000004 pcalau12i \$a0, 0 -- 80: R_LARCH_TLS_GD_PC_HI20 TLS1 -- 80: R_LARCH_RELAX \*ABS\* -- 84: 02c00005 li.d \$a1, 0 -- 84: R_LARCH_GOT_PC_LO12 TLS1 -- 84: R_LARCH_RELAX \*ABS\* -- 88: 16000005 lu32i.d \$a1, 0 -- 88: R_LARCH_GOT64_PC_LO20 TLS1 -- 8c: 030000a5 lu52i.d \$a1, \$a1, 0 -- 8c: R_LARCH_GOT64_PC_HI12 TLS1 -- 90: 00109484 add.d \$a0, \$a0, \$a1 -+[ ]*0000000000000000 <.L1>: -+[ ]+0:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0 -+[ ]+0: R_LARCH_PCALA_HI20[ ]+.L1 -+[ ]+4:[ ]+02c00005[ ]+li.d[ ]+\$a1, 0 -+[ ]+4: R_LARCH_PCALA_LO12[ ]+.L1 -+[ ]+8:[ ]+16000005[ ]+lu32i.d[ ]+\$a1, 0 -+[ ]+8: R_LARCH_PCALA64_LO20[ ]+.L1 -+[ ]+c:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1, \$a1, 0 -+[ ]+c: R_LARCH_PCALA64_HI12[ ]+.L1 -+[ ]+10:[ ]+00109484[ ]+add.d[ ]+\$a0, \$a0, \$a1 -+[ ]+14:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0 -+[ ]+14: R_LARCH_PCALA_HI20[ ]+.L1 -+[ ]+18:[ ]+02c00005[ ]+li.d[ ]+\$a1, 0 -+[ ]+18: R_LARCH_PCALA_LO12[ ]+.L1 -+[ ]+1c:[ ]+16000005[ ]+lu32i.d[ ]+\$a1, 0 -+[ ]+1c: R_LARCH_PCALA64_LO20[ ]+.L1 -+[ ]+20:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1, \$a1, 0 -+[ ]+20: R_LARCH_PCALA64_HI12[ ]+.L1 -+[ ]+24:[ ]+00109484[ ]+add.d[ ]+\$a0, \$a0, \$a1 -+[ ]+28:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0 -+[ ]+28: R_LARCH_PCALA_HI20[ ]+.L1 -+[ ]+2c:[ ]+02c00005[ ]+li.d[ ]+\$a1, 0 -+[ ]+2c: R_LARCH_PCALA_LO12[ ]+.L1 -+[ ]+30:[ ]+16000005[ ]+lu32i.d[ ]+\$a1, 0 -+[ ]+30: R_LARCH_PCALA64_LO20[ ]+.L1 -+[ ]+34:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1, \$a1, 0 -+[ ]+34: R_LARCH_PCALA64_HI12[ ]+.L1 -+[ ]+38:[ ]+00109484[ ]+add.d[ ]+\$a0, \$a0, \$a1 -+[ ]+3c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0 -+[ ]+3c: R_LARCH_GOT_PC_HI20[ ]+.L1 -+[ ]+40:[ ]+02c00005[ ]+li.d[ ]+\$a1, 0 -+[ ]+40: R_LARCH_GOT_PC_LO12[ ]+.L1 -+[ ]+44:[ ]+16000005[ ]+lu32i.d[ ]+\$a1, 0 -+[ ]+44: R_LARCH_GOT64_PC_LO20[ ]+.L1 -+[ ]+48:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1, \$a1, 0 -+[ ]+48: R_LARCH_GOT64_PC_HI12[ ]+.L1 -+[ ]+4c:[ ]+380c1484[ ]+ldx.d[ ]+\$a0, \$a0, \$a1 -+[ ]+50:[ ]+14000004[ ]+lu12i.w[ ]+\$a0, 0 -+[ ]+50: R_LARCH_TLS_LE_HI20[ ]+TLS1 -+[ ]+54:[ ]+03800084[ ]+ori[ ]+\$a0, \$a0, 0x0 -+[ ]+54: R_LARCH_TLS_LE_LO12[ ]+TLS1 -+[ ]+58:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0 -+[ ]+58: R_LARCH_TLS_IE_PC_HI20[ ]+TLS1 -+[ ]+5c:[ ]+02c00005[ ]+li.d[ ]+\$a1, 0 -+[ ]+5c: R_LARCH_TLS_IE_PC_LO12[ ]+TLS1 -+[ ]+60:[ ]+16000005[ ]+lu32i.d[ ]+\$a1, 0 -+[ ]+60: R_LARCH_TLS_IE64_PC_LO20[ ]+TLS1 -+[ ]+64:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1, \$a1, 0 -+[ ]+64: R_LARCH_TLS_IE64_PC_HI12[ ]+TLS1 -+[ ]+68:[ ]+380c1484[ ]+ldx.d[ ]+\$a0, \$a0, \$a1 -+[ ]+6c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0 -+[ ]+6c: R_LARCH_TLS_LD_PC_HI20[ ]+TLS1 -+[ ]+70:[ ]+02c00005[ ]+li.d[ ]+\$a1, 0 -+[ ]+70: R_LARCH_GOT_PC_LO12[ ]+TLS1 -+[ ]+74:[ ]+16000005[ ]+lu32i.d[ ]+\$a1, 0 -+[ ]+74: R_LARCH_GOT64_PC_LO20[ ]+TLS1 -+[ ]+78:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1, \$a1, 0 -+[ ]+78: R_LARCH_GOT64_PC_HI12[ ]+TLS1 -+[ ]+7c:[ ]+00109484[ ]+add.d[ ]+\$a0, \$a0, \$a1 -+[ ]+80:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0 -+[ ]+80: R_LARCH_TLS_GD_PC_HI20[ ]+TLS1 -+[ ]+84:[ ]+02c00005[ ]+li.d[ ]+\$a1, 0 -+[ ]+84: R_LARCH_GOT_PC_LO12[ ]+TLS1 -+[ ]+88:[ ]+16000005[ ]+lu32i.d[ ]+\$a1, 0 -+[ ]+88: R_LARCH_GOT64_PC_LO20[ ]+TLS1 -+[ ]+8c:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1, \$a1, 0 -+[ ]+8c: R_LARCH_GOT64_PC_HI12[ ]+TLS1 -+[ ]+90:[ ]+00109484[ ]+add.d[ ]+\$a0, \$a0, \$a1 -diff --git a/gas/testsuite/gas/loongarch/tlsdesc_large_pc.d b/gas/testsuite/gas/loongarch/tlsdesc_large_pc.d -index 2b7a4660..a7fcce31 100644 ---- a/gas/testsuite/gas/loongarch/tlsdesc_large_pc.d -+++ b/gas/testsuite/gas/loongarch/tlsdesc_large_pc.d -@@ -2,37 +2,35 @@ - #objdump: -dr - #skip: loongarch32-*-* - --.*: file format .* -+.*:[ ]+file format .* - - - Disassembly of section .text: - --0+ <.*>: -- 0: 1a000004 pcalau12i \$a0, 0 -- 0: R_LARCH_TLS_DESC_PC_HI20 var -- 4: 02c00005 li.d \$a1, 0 -- 4: R_LARCH_TLS_DESC_PC_LO12 var -- 8: 16000005 lu32i.d \$a1, 0 -- 8: R_LARCH_TLS_DESC64_PC_LO20 var -- c: 030000a5 lu52i.d \$a1, \$a1, 0 -- c: R_LARCH_TLS_DESC64_PC_HI12 var -- 10: 00109484 add.d \$a0, \$a0, \$a1 -- 14: 28c00081 ld.d \$ra, \$a0, 0 -- 14: R_LARCH_TLS_DESC_LD var -- 18: 4c000021 jirl \$ra, \$ra, 0 -- 18: R_LARCH_TLS_DESC_CALL var -- 1c: 1a000004 pcalau12i \$a0, 0 -- 1c: R_LARCH_TLS_DESC_PC_HI20 var -- 1c: R_LARCH_RELAX \*ABS\* -- 20: 02c00001 li.d \$ra, 0 -- 20: R_LARCH_TLS_DESC_PC_LO12 var -- 20: R_LARCH_RELAX \*ABS\* -- 24: 16000001 lu32i.d \$ra, 0 -- 24: R_LARCH_TLS_DESC64_PC_LO20 var -- 28: 03000021 lu52i.d \$ra, \$ra, 0 -- 28: R_LARCH_TLS_DESC64_PC_HI12 var -- 2c: 00108484 add.d \$a0, \$a0, \$ra -- 30: 28c00081 ld.d \$ra, \$a0, 0 -- 30: R_LARCH_TLS_DESC_LD var -- 34: 4c000021 jirl \$ra, \$ra, 0 -- 34: R_LARCH_TLS_DESC_CALL var -+[ ]*0000000000000000 <.text>: -+[ ]+0:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0 -+[ ]+0: R_LARCH_TLS_DESC_PC_HI20[ ]+var -+[ ]+4:[ ]+02c00005[ ]+li.d[ ]+\$a1, 0 -+[ ]+4: R_LARCH_TLS_DESC_PC_LO12[ ]+var -+[ ]+8:[ ]+16000005[ ]+lu32i.d[ ]+\$a1, 0 -+[ ]+8: R_LARCH_TLS_DESC64_PC_LO20[ ]+var -+[ ]+c:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1, \$a1, 0 -+[ ]+c: R_LARCH_TLS_DESC64_PC_HI12[ ]+var -+[ ]+10:[ ]+00109484[ ]+add.d[ ]+\$a0, \$a0, \$a1 -+[ ]+14:[ ]+28c00081[ ]+ld.d[ ]+\$ra, \$a0, 0 -+[ ]+14: R_LARCH_TLS_DESC_LD[ ]+var -+[ ]+18:[ ]+4c000021[ ]+jirl[ ]+\$ra, \$ra, 0 -+[ ]+18: R_LARCH_TLS_DESC_CALL[ ]+var -+[ ]+1c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0 -+[ ]+1c: R_LARCH_TLS_DESC_PC_HI20[ ]+var -+[ ]+20:[ ]+02c00001[ ]+li.d[ ]+\$ra, 0 -+[ ]+20: R_LARCH_TLS_DESC_PC_LO12[ ]+var -+[ ]+24:[ ]+16000001[ ]+lu32i.d[ ]+\$ra, 0 -+[ ]+24: R_LARCH_TLS_DESC64_PC_LO20[ ]+var -+[ ]+28:[ ]+03000021[ ]+lu52i.d[ ]+\$ra, \$ra, 0 -+[ ]+28: R_LARCH_TLS_DESC64_PC_HI12[ ]+var -+[ ]+2c:[ ]+00108484[ ]+add.d[ ]+\$a0, \$a0, \$ra -+[ ]+30:[ ]+28c00081[ ]+ld.d[ ]+\$ra, \$a0, 0 -+[ ]+30: R_LARCH_TLS_DESC_LD[ ]+var -+[ ]+34:[ ]+4c000021[ ]+jirl[ ]+\$ra, \$ra, 0 -+[ ]+34: R_LARCH_TLS_DESC_CALL[ ]+var -diff --git a/ld/testsuite/ld-loongarch-elf/macro_op.d b/ld/testsuite/ld-loongarch-elf/macro_op.d -index f0d87c03..c9493918 100644 ---- a/ld/testsuite/ld-loongarch-elf/macro_op.d -+++ b/ld/testsuite/ld-loongarch-elf/macro_op.d -@@ -2,204 +2,186 @@ - #objdump: -dr - #skip: loongarch32-*-* - --.*: file format .* -+.*:[ ]+file format .* - - - Disassembly of section .text: - --0+ <.L1>: -- 0: 00150004 move \$a0, \$zero -- 4: 02bffc04 li.w \$a0, -1 -- 8: 00150004 move \$a0, \$zero -- c: 02bffc04 li.w \$a0, -1 -- 10: 1a000004 pcalau12i \$a0, 0 -- 10: R_LARCH_GOT_PC_HI20 .L1 -- 10: R_LARCH_RELAX \*ABS\* -- 14: 28c00084 ld.d \$a0, \$a0, 0 -- 14: R_LARCH_GOT_PC_LO12 .L1 -- 14: R_LARCH_RELAX \*ABS\* -- 18: 1a000004 pcalau12i \$a0, 0 -- 18: R_LARCH_GOT_PC_HI20 .L1 -- 18: R_LARCH_RELAX \*ABS\* -- 1c: 28c00084 ld.d \$a0, \$a0, 0 -- 1c: R_LARCH_GOT_PC_LO12 .L1 -- 1c: R_LARCH_RELAX \*ABS\* -- 20: 1a000004 pcalau12i \$a0, 0 -- 20: R_LARCH_GOT_PC_HI20 .L1 -- 20: R_LARCH_RELAX \*ABS\* -- 24: 02c00005 li.d \$a1, 0 -- 24: R_LARCH_GOT_PC_LO12 .L1 -- 24: R_LARCH_RELAX \*ABS\* -- 28: 16000005 lu32i.d \$a1, 0 -- 28: R_LARCH_GOT64_PC_LO20 .L1 -- 2c: 030000a5 lu52i.d \$a1, \$a1, 0 -- 2c: R_LARCH_GOT64_PC_HI12 .L1 -- 30: 380c1484 ldx.d \$a0, \$a0, \$a1 -- 34: 1a000004 pcalau12i \$a0, 0 -- 34: R_LARCH_GOT_PC_HI20 .L1 -- 34: R_LARCH_RELAX \*ABS\* -- 38: 28c00084 ld.d \$a0, \$a0, 0 -- 38: R_LARCH_GOT_PC_LO12 .L1 -- 38: R_LARCH_RELAX \*ABS\* -- 3c: 1a000004 pcalau12i \$a0, 0 -- 3c: R_LARCH_GOT_PC_HI20 .L1 -- 3c: R_LARCH_RELAX \*ABS\* -- 40: 02c00005 li.d \$a1, 0 -- 40: R_LARCH_GOT_PC_LO12 .L1 -- 40: R_LARCH_RELAX \*ABS\* -- 44: 16000005 lu32i.d \$a1, 0 -- 44: R_LARCH_GOT64_PC_LO20 .L1 -- 48: 030000a5 lu52i.d \$a1, \$a1, 0 -- 48: R_LARCH_GOT64_PC_HI12 .L1 -- 4c: 380c1484 ldx.d \$a0, \$a0, \$a1 -- 50: 1a000004 pcalau12i \$a0, 0 -- 50: R_LARCH_GOT_PC_HI20 .L1 -- 50: R_LARCH_RELAX \*ABS\* -- 54: 28c00084 ld.d \$a0, \$a0, 0 -- 54: R_LARCH_GOT_PC_LO12 .L1 -- 54: R_LARCH_RELAX \*ABS\* -- 58: 1a000004 pcalau12i \$a0, 0 -- 58: R_LARCH_GOT_PC_HI20 .L1 -- 58: R_LARCH_RELAX \*ABS\* -- 5c: 02c00005 li.d \$a1, 0 -- 5c: R_LARCH_GOT_PC_LO12 .L1 -- 5c: R_LARCH_RELAX \*ABS\* -- 60: 16000005 lu32i.d \$a1, 0 -- 60: R_LARCH_GOT64_PC_LO20 .L1 -- 64: 030000a5 lu52i.d \$a1, \$a1, 0 -- 64: R_LARCH_GOT64_PC_HI12 .L1 -- 68: 380c1484 ldx.d \$a0, \$a0, \$a1 -- 6c: 1a000004 pcalau12i \$a0, 0 -- 6c: R_LARCH_PCALA_HI20 .L1 -- 6c: R_LARCH_RELAX \*ABS\* -- 70: 02c00084 addi.d \$a0, \$a0, 0 -- 70: R_LARCH_PCALA_LO12 .L1 -- 70: R_LARCH_RELAX \*ABS\* -- 74: 1a000004 pcalau12i \$a0, 0 -- 74: R_LARCH_PCALA_HI20 .L1 -- 74: R_LARCH_RELAX \*ABS\* -- 78: 02c00005 li.d \$a1, 0 -- 78: R_LARCH_PCALA_LO12 .L1 -- 78: R_LARCH_RELAX \*ABS\* -- 7c: 16000005 lu32i.d \$a1, 0 -- 7c: R_LARCH_PCALA64_LO20 .L1 -- 80: 030000a5 lu52i.d \$a1, \$a1, 0 -- 80: R_LARCH_PCALA64_HI12 .L1 -- 84: 00109484 add.d \$a0, \$a0, \$a1 -- 88: 1a000004 pcalau12i \$a0, 0 -- 88: R_LARCH_PCALA_HI20 .L1 -- 88: R_LARCH_RELAX \*ABS\* -- 8c: 02c00084 addi.d \$a0, \$a0, 0 -- 8c: R_LARCH_PCALA_LO12 .L1 -- 8c: R_LARCH_RELAX \*ABS\* -- 90: 1a000004 pcalau12i \$a0, 0 -- 90: R_LARCH_PCALA_HI20 .L1 -- 90: R_LARCH_RELAX \*ABS\* -- 94: 02c00005 li.d \$a1, 0 -- 94: R_LARCH_PCALA_LO12 .L1 -- 94: R_LARCH_RELAX \*ABS\* -- 98: 16000005 lu32i.d \$a1, 0 -- 98: R_LARCH_PCALA64_LO20 .L1 -- 9c: 030000a5 lu52i.d \$a1, \$a1, 0 -- 9c: R_LARCH_PCALA64_HI12 .L1 -- a0: 00109484 add.d \$a0, \$a0, \$a1 -- a4: 14000004 lu12i.w \$a0, 0 -- a4: R_LARCH_MARK_LA \*ABS\* -- a4: R_LARCH_ABS_HI20 .L1 -- a8: 03800084 ori \$a0, \$a0, 0x0 -- a8: R_LARCH_ABS_LO12 .L1 -- ac: 16000004 lu32i.d \$a0, 0 -- ac: R_LARCH_ABS64_LO20 .L1 -- b0: 03000084 lu52i.d \$a0, \$a0, 0 -- b0: R_LARCH_ABS64_HI12 .L1 -- b4: 1a000004 pcalau12i \$a0, 0 -- b4: R_LARCH_PCALA_HI20 .L1 -- b4: R_LARCH_RELAX \*ABS\* -- b8: 02c00084 addi.d \$a0, \$a0, 0 -- b8: R_LARCH_PCALA_LO12 .L1 -- b8: R_LARCH_RELAX \*ABS\* -- bc: 1a000004 pcalau12i \$a0, 0 -- bc: R_LARCH_PCALA_HI20 .L1 -- bc: R_LARCH_RELAX \*ABS\* -- c0: 02c00084 addi.d \$a0, \$a0, 0 -- c0: R_LARCH_PCALA_LO12 .L1 -- c0: R_LARCH_RELAX \*ABS\* -- c4: 1a000004 pcalau12i \$a0, 0 -- c4: R_LARCH_PCALA_HI20 .L1 -- c4: R_LARCH_RELAX \*ABS\* -- c8: 02c00005 li.d \$a1, 0 -- c8: R_LARCH_PCALA_LO12 .L1 -- c8: R_LARCH_RELAX \*ABS\* -- cc: 16000005 lu32i.d \$a1, 0 -- cc: R_LARCH_PCALA64_LO20 .L1 -- d0: 030000a5 lu52i.d \$a1, \$a1, 0 -- d0: R_LARCH_PCALA64_HI12 .L1 -- d4: 00109484 add.d \$a0, \$a0, \$a1 -- d8: 1a000004 pcalau12i \$a0, 0 -- d8: R_LARCH_GOT_PC_HI20 .L1 -- d8: R_LARCH_RELAX \*ABS\* -- dc: 28c00084 ld.d \$a0, \$a0, 0 -- dc: R_LARCH_GOT_PC_LO12 .L1 -- dc: R_LARCH_RELAX \*ABS\* -- e0: 1a000004 pcalau12i \$a0, 0 -- e0: R_LARCH_GOT_PC_HI20 .L1 -- e0: R_LARCH_RELAX \*ABS\* -- e4: 02c00005 li.d \$a1, 0 -- e4: R_LARCH_GOT_PC_LO12 .L1 -- e4: R_LARCH_RELAX \*ABS\* -- e8: 16000005 lu32i.d \$a1, 0 -- e8: R_LARCH_GOT64_PC_LO20 .L1 -- ec: 030000a5 lu52i.d \$a1, \$a1, 0 -- ec: R_LARCH_GOT64_PC_HI12 .L1 -- f0: 380c1484 ldx.d \$a0, \$a0, \$a1 -- f4: 14000004 lu12i.w \$a0, 0 -- f4: R_LARCH_TLS_LE_HI20 TLS1 -- f8: 03800084 ori \$a0, \$a0, 0x0 -- f8: R_LARCH_TLS_LE_LO12 TLS1 -- fc: 1a000004 pcalau12i \$a0, 0 -- fc: R_LARCH_TLS_IE_PC_HI20 TLS1 -- 100: 28c00084 ld.d \$a0, \$a0, 0 -- 100: R_LARCH_TLS_IE_PC_LO12 TLS1 -- 104: 1a000004 pcalau12i \$a0, 0 -- 104: R_LARCH_TLS_IE_PC_HI20 TLS1 -- 108: 02c00005 li.d \$a1, 0 -- 108: R_LARCH_TLS_IE_PC_LO12 TLS1 -- 10c: 16000005 lu32i.d \$a1, 0 -- 10c: R_LARCH_TLS_IE64_PC_LO20 TLS1 -- 110: 030000a5 lu52i.d \$a1, \$a1, 0 -- 110: R_LARCH_TLS_IE64_PC_HI12 TLS1 -- 114: 380c1484 ldx.d \$a0, \$a0, \$a1 -- 118: 1a000004 pcalau12i \$a0, 0 -- 118: R_LARCH_TLS_LD_PC_HI20 TLS1 -- 118: R_LARCH_RELAX \*ABS\* -- 11c: 02c00084 addi.d \$a0, \$a0, 0 -- 11c: R_LARCH_GOT_PC_LO12 TLS1 -- 11c: R_LARCH_RELAX \*ABS\* -- 120: 1a000004 pcalau12i \$a0, 0 -- 120: R_LARCH_TLS_LD_PC_HI20 TLS1 -- 120: R_LARCH_RELAX \*ABS\* -- 124: 02c00005 li.d \$a1, 0 -- 124: R_LARCH_GOT_PC_LO12 TLS1 -- 124: R_LARCH_RELAX \*ABS\* -- 128: 16000005 lu32i.d \$a1, 0 -- 128: R_LARCH_GOT64_PC_LO20 TLS1 -- 12c: 030000a5 lu52i.d \$a1, \$a1, 0 -- 12c: R_LARCH_GOT64_PC_HI12 TLS1 -- 130: 00109484 add.d \$a0, \$a0, \$a1 -- 134: 1a000004 pcalau12i \$a0, 0 -- 134: R_LARCH_TLS_GD_PC_HI20 TLS1 -- 134: R_LARCH_RELAX \*ABS\* -- 138: 02c00084 addi.d \$a0, \$a0, 0 -- 138: R_LARCH_GOT_PC_LO12 TLS1 -- 138: R_LARCH_RELAX \*ABS\* -- 13c: 1a000004 pcalau12i \$a0, 0 -- 13c: R_LARCH_TLS_GD_PC_HI20 TLS1 -- 13c: R_LARCH_RELAX \*ABS\* -- 140: 02c00005 li.d \$a1, 0 -- 140: R_LARCH_GOT_PC_LO12 TLS1 -- 140: R_LARCH_RELAX \*ABS\* -- 144: 16000005 lu32i.d \$a1, 0 -- 144: R_LARCH_GOT64_PC_LO20 TLS1 -- 148: 030000a5 lu52i.d \$a1, \$a1, 0 -- 148: R_LARCH_GOT64_PC_HI12 TLS1 -- 14c: 00109484 add.d \$a0, \$a0, \$a1 -+[ ]*0000000000000000 <.L1>: -+[ ]+0:[ ]+00150004[ ]+move[ ]+\$a0, \$zero -+[ ]+4:[ ]+02bffc04[ ]+li.w[ ]+\$a0, -1 -+[ ]+8:[ ]+00150004[ ]+move[ ]+\$a0, \$zero -+[ ]+c:[ ]+02bffc04[ ]+li.w[ ]+\$a0, -1 -+[ ]+10:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0 -+[ ]+10: R_LARCH_GOT_PC_HI20[ ]+.L1 -+[ ]+10: R_LARCH_RELAX[ ]+\*ABS\* -+[ ]+14:[ ]+28c00084[ ]+ld.d[ ]+\$a0, \$a0, 0 -+[ ]+14: R_LARCH_GOT_PC_LO12[ ]+.L1 -+[ ]+14: R_LARCH_RELAX[ ]+\*ABS\* -+[ ]+18:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0 -+[ ]+18: R_LARCH_GOT_PC_HI20[ ]+.L1 -+[ ]+18: R_LARCH_RELAX[ ]+\*ABS\* -+[ ]+1c:[ ]+28c00084[ ]+ld.d[ ]+\$a0, \$a0, 0 -+[ ]+1c: R_LARCH_GOT_PC_LO12[ ]+.L1 -+[ ]+1c: R_LARCH_RELAX[ ]+\*ABS\* -+[ ]+20:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0 -+[ ]+20: R_LARCH_GOT_PC_HI20[ ]+.L1 -+[ ]+24:[ ]+02c00005[ ]+li.d[ ]+\$a1, 0 -+[ ]+24: R_LARCH_GOT_PC_LO12[ ]+.L1 -+[ ]+28:[ ]+16000005[ ]+lu32i.d[ ]+\$a1, 0 -+[ ]+28: R_LARCH_GOT64_PC_LO20[ ]+.L1 -+[ ]+2c:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1, \$a1, 0 -+[ ]+2c: R_LARCH_GOT64_PC_HI12[ ]+.L1 -+[ ]+30:[ ]+380c1484[ ]+ldx.d[ ]+\$a0, \$a0, \$a1 -+[ ]+34:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0 -+[ ]+34: R_LARCH_GOT_PC_HI20[ ]+.L1 -+[ ]+34: R_LARCH_RELAX[ ]+\*ABS\* -+[ ]+38:[ ]+28c00084[ ]+ld.d[ ]+\$a0, \$a0, 0 -+[ ]+38: R_LARCH_GOT_PC_LO12[ ]+.L1 -+[ ]+38: R_LARCH_RELAX[ ]+\*ABS\* -+[ ]+3c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0 -+[ ]+3c: R_LARCH_GOT_PC_HI20[ ]+.L1 -+[ ]+40:[ ]+02c00005[ ]+li.d[ ]+\$a1, 0 -+[ ]+40: R_LARCH_GOT_PC_LO12[ ]+.L1 -+[ ]+44:[ ]+16000005[ ]+lu32i.d[ ]+\$a1, 0 -+[ ]+44: R_LARCH_GOT64_PC_LO20[ ]+.L1 -+[ ]+48:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1, \$a1, 0 -+[ ]+48: R_LARCH_GOT64_PC_HI12[ ]+.L1 -+[ ]+4c:[ ]+380c1484[ ]+ldx.d[ ]+\$a0, \$a0, \$a1 -+[ ]+50:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0 -+[ ]+50: R_LARCH_GOT_PC_HI20[ ]+.L1 -+[ ]+50: R_LARCH_RELAX[ ]+\*ABS\* -+[ ]+54:[ ]+28c00084[ ]+ld.d[ ]+\$a0, \$a0, 0 -+[ ]+54: R_LARCH_GOT_PC_LO12[ ]+.L1 -+[ ]+54: R_LARCH_RELAX[ ]+\*ABS\* -+[ ]+58:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0 -+[ ]+58: R_LARCH_GOT_PC_HI20[ ]+.L1 -+[ ]+5c:[ ]+02c00005[ ]+li.d[ ]+\$a1, 0 -+[ ]+5c: R_LARCH_GOT_PC_LO12[ ]+.L1 -+[ ]+60:[ ]+16000005[ ]+lu32i.d[ ]+\$a1, 0 -+[ ]+60: R_LARCH_GOT64_PC_LO20[ ]+.L1 -+[ ]+64:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1, \$a1, 0 -+[ ]+64: R_LARCH_GOT64_PC_HI12[ ]+.L1 -+[ ]+68:[ ]+380c1484[ ]+ldx.d[ ]+\$a0, \$a0, \$a1 -+[ ]+6c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0 -+[ ]+6c: R_LARCH_PCALA_HI20[ ]+.L1 -+[ ]+6c: R_LARCH_RELAX[ ]+\*ABS\* -+[ ]+70:[ ]+02c00084[ ]+addi.d[ ]+\$a0, \$a0, 0 -+[ ]+70: R_LARCH_PCALA_LO12[ ]+.L1 -+[ ]+70: R_LARCH_RELAX[ ]+\*ABS\* -+[ ]+74:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0 -+[ ]+74: R_LARCH_PCALA_HI20[ ]+.L1 -+[ ]+78:[ ]+02c00005[ ]+li.d[ ]+\$a1, 0 -+[ ]+78: R_LARCH_PCALA_LO12[ ]+.L1 -+[ ]+7c:[ ]+16000005[ ]+lu32i.d[ ]+\$a1, 0 -+[ ]+7c: R_LARCH_PCALA64_LO20[ ]+.L1 -+[ ]+80:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1, \$a1, 0 -+[ ]+80: R_LARCH_PCALA64_HI12[ ]+.L1 -+[ ]+84:[ ]+00109484[ ]+add.d[ ]+\$a0, \$a0, \$a1 -+[ ]+88:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0 -+[ ]+88: R_LARCH_PCALA_HI20[ ]+.L1 -+[ ]+88: R_LARCH_RELAX[ ]+\*ABS\* -+[ ]+8c:[ ]+02c00084[ ]+addi.d[ ]+\$a0, \$a0, 0 -+[ ]+8c: R_LARCH_PCALA_LO12[ ]+.L1 -+[ ]+8c: R_LARCH_RELAX[ ]+\*ABS\* -+[ ]+90:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0 -+[ ]+90: R_LARCH_PCALA_HI20[ ]+.L1 -+[ ]+94:[ ]+02c00005[ ]+li.d[ ]+\$a1, 0 -+[ ]+94: R_LARCH_PCALA_LO12[ ]+.L1 -+[ ]+98:[ ]+16000005[ ]+lu32i.d[ ]+\$a1, 0 -+[ ]+98: R_LARCH_PCALA64_LO20[ ]+.L1 -+[ ]+9c:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1, \$a1, 0 -+[ ]+9c: R_LARCH_PCALA64_HI12[ ]+.L1 -+[ ]+a0:[ ]+00109484[ ]+add.d[ ]+\$a0, \$a0, \$a1 -+[ ]+a4:[ ]+14000004[ ]+lu12i.w[ ]+\$a0, 0 -+[ ]+a4: R_LARCH_MARK_LA[ ]+\*ABS\* -+[ ]+a4: R_LARCH_ABS_HI20[ ]+.L1 -+[ ]+a8:[ ]+03800084[ ]+ori[ ]+\$a0, \$a0, 0x0 -+[ ]+a8: R_LARCH_ABS_LO12[ ]+.L1 -+[ ]+ac:[ ]+16000004[ ]+lu32i.d[ ]+\$a0, 0 -+[ ]+ac: R_LARCH_ABS64_LO20[ ]+.L1 -+[ ]+b0:[ ]+03000084[ ]+lu52i.d[ ]+\$a0, \$a0, 0 -+[ ]+b0: R_LARCH_ABS64_HI12[ ]+.L1 -+[ ]+b4:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0 -+[ ]+b4: R_LARCH_PCALA_HI20[ ]+.L1 -+[ ]+b4: R_LARCH_RELAX[ ]+\*ABS\* -+[ ]+b8:[ ]+02c00084[ ]+addi.d[ ]+\$a0, \$a0, 0 -+[ ]+b8: R_LARCH_PCALA_LO12[ ]+.L1 -+[ ]+b8: R_LARCH_RELAX[ ]+\*ABS\* -+[ ]+bc:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0 -+[ ]+bc: R_LARCH_PCALA_HI20[ ]+.L1 -+[ ]+bc: R_LARCH_RELAX[ ]+\*ABS\* -+[ ]+c0:[ ]+02c00084[ ]+addi.d[ ]+\$a0, \$a0, 0 -+[ ]+c0: R_LARCH_PCALA_LO12[ ]+.L1 -+[ ]+c0: R_LARCH_RELAX[ ]+\*ABS\* -+[ ]+c4:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0 -+[ ]+c4: R_LARCH_PCALA_HI20[ ]+.L1 -+[ ]+c8:[ ]+02c00005[ ]+li.d[ ]+\$a1, 0 -+[ ]+c8: R_LARCH_PCALA_LO12[ ]+.L1 -+[ ]+cc:[ ]+16000005[ ]+lu32i.d[ ]+\$a1, 0 -+[ ]+cc: R_LARCH_PCALA64_LO20[ ]+.L1 -+[ ]+d0:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1, \$a1, 0 -+[ ]+d0: R_LARCH_PCALA64_HI12[ ]+.L1 -+[ ]+d4:[ ]+00109484[ ]+add.d[ ]+\$a0, \$a0, \$a1 -+[ ]+d8:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0 -+[ ]+d8: R_LARCH_GOT_PC_HI20[ ]+.L1 -+[ ]+d8: R_LARCH_RELAX[ ]+\*ABS\* -+[ ]+dc:[ ]+28c00084[ ]+ld.d[ ]+\$a0, \$a0, 0 -+[ ]+dc: R_LARCH_GOT_PC_LO12[ ]+.L1 -+[ ]+dc: R_LARCH_RELAX[ ]+\*ABS\* -+[ ]+e0:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0 -+[ ]+e0: R_LARCH_GOT_PC_HI20[ ]+.L1 -+[ ]+e4:[ ]+02c00005[ ]+li.d[ ]+\$a1, 0 -+[ ]+e4: R_LARCH_GOT_PC_LO12[ ]+.L1 -+[ ]+e8:[ ]+16000005[ ]+lu32i.d[ ]+\$a1, 0 -+[ ]+e8: R_LARCH_GOT64_PC_LO20[ ]+.L1 -+[ ]+ec:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1, \$a1, 0 -+[ ]+ec: R_LARCH_GOT64_PC_HI12[ ]+.L1 -+[ ]+f0:[ ]+380c1484[ ]+ldx.d[ ]+\$a0, \$a0, \$a1 -+[ ]+f4:[ ]+14000004[ ]+lu12i.w[ ]+\$a0, 0 -+[ ]+f4: R_LARCH_TLS_LE_HI20[ ]+TLS1 -+[ ]+f8:[ ]+03800084[ ]+ori[ ]+\$a0, \$a0, 0x0 -+[ ]+f8: R_LARCH_TLS_LE_LO12[ ]+TLS1 -+[ ]+fc:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0 -+[ ]+fc: R_LARCH_TLS_IE_PC_HI20[ ]+TLS1 -+[ ]+100:[ ]+28c00084[ ]+ld.d[ ]+\$a0, \$a0, 0 -+[ ]+100: R_LARCH_TLS_IE_PC_LO12[ ]+TLS1 -+[ ]+104:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0 -+[ ]+104: R_LARCH_TLS_IE_PC_HI20[ ]+TLS1 -+[ ]+108:[ ]+02c00005[ ]+li.d[ ]+\$a1, 0 -+[ ]+108: R_LARCH_TLS_IE_PC_LO12[ ]+TLS1 -+[ ]+10c:[ ]+16000005[ ]+lu32i.d[ ]+\$a1, 0 -+[ ]+10c: R_LARCH_TLS_IE64_PC_LO20[ ]+TLS1 -+[ ]+110:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1, \$a1, 0 -+[ ]+110: R_LARCH_TLS_IE64_PC_HI12[ ]+TLS1 -+[ ]+114:[ ]+380c1484[ ]+ldx.d[ ]+\$a0, \$a0, \$a1 -+[ ]+118:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0 -+[ ]+118: R_LARCH_TLS_LD_PC_HI20[ ]+TLS1 -+[ ]+118: R_LARCH_RELAX[ ]+\*ABS\* -+[ ]+11c:[ ]+02c00084[ ]+addi.d[ ]+\$a0, \$a0, 0 -+[ ]+11c: R_LARCH_GOT_PC_LO12[ ]+TLS1 -+[ ]+11c: R_LARCH_RELAX[ ]+\*ABS\* -+[ ]+120:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0 -+[ ]+120: R_LARCH_TLS_LD_PC_HI20[ ]+TLS1 -+[ ]+124:[ ]+02c00005[ ]+li.d[ ]+\$a1, 0 -+[ ]+124: R_LARCH_GOT_PC_LO12[ ]+TLS1 -+[ ]+128:[ ]+16000005[ ]+lu32i.d[ ]+\$a1, 0 -+[ ]+128: R_LARCH_GOT64_PC_LO20[ ]+TLS1 -+[ ]+12c:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1, \$a1, 0 -+[ ]+12c: R_LARCH_GOT64_PC_HI12[ ]+TLS1 -+[ ]+130:[ ]+00109484[ ]+add.d[ ]+\$a0, \$a0, \$a1 -+[ ]+134:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0 -+[ ]+134: R_LARCH_TLS_GD_PC_HI20[ ]+TLS1 -+[ ]+134: R_LARCH_RELAX[ ]+\*ABS\* -+[ ]+138:[ ]+02c00084[ ]+addi.d[ ]+\$a0, \$a0, 0 -+[ ]+138: R_LARCH_GOT_PC_LO12[ ]+TLS1 -+[ ]+138: R_LARCH_RELAX[ ]+\*ABS\* -+[ ]+13c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0 -+[ ]+13c: R_LARCH_TLS_GD_PC_HI20[ ]+TLS1 -+[ ]+140:[ ]+02c00005[ ]+li.d[ ]+\$a1, 0 -+[ ]+140: R_LARCH_GOT_PC_LO12[ ]+TLS1 -+[ ]+144:[ ]+16000005[ ]+lu32i.d[ ]+\$a1, 0 -+[ ]+144: R_LARCH_GOT64_PC_LO20[ ]+TLS1 -+[ ]+148:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1, \$a1, 0 -+[ ]+148: R_LARCH_GOT64_PC_HI12[ ]+TLS1 -+[ ]+14c:[ ]+00109484[ ]+add.d[ ]+\$a0, \$a0, \$a1 --- -2.33.0 - diff --git a/LoongArch-Enable-gas-sort-relocs.patch b/LoongArch-Enable-gas-sort-relocs.patch deleted file mode 100644 index 4179425..0000000 --- a/LoongArch-Enable-gas-sort-relocs.patch +++ /dev/null @@ -1,29 +0,0 @@ -From c4da692895d01cf281c22efc2c30a6d4fdfb3d21 Mon Sep 17 00:00:00 2001 -From: Jinyang He -Date: Fri, 11 Aug 2023 16:10:40 +0800 -Subject: [PATCH 009/123] LoongArch: Enable gas sort relocs - -The md_pre_output_hook creating fixup is asynchronous, causing relocs -may be out of order in .eh_frame. Define GAS_SORT_RELOCS so that reorder -relocs when write_relocs. - -Reported-by: Rui Ueyama ---- - gas/config/tc-loongarch.h | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/gas/config/tc-loongarch.h b/gas/config/tc-loongarch.h -index d353f18d..fd094356 100644 ---- a/gas/config/tc-loongarch.h -+++ b/gas/config/tc-loongarch.h -@@ -123,6 +123,7 @@ extern void tc_loongarch_parse_to_dw2regnum (expressionS *); - - extern void loongarch_pre_output_hook (void); - #define md_pre_output_hook loongarch_pre_output_hook () -+#define GAS_SORT_RELOCS 1 - - #define SUB_SEGMENT_ALIGN(SEG, FRCHAIN) 0 - --- -2.33.0 - diff --git a/LoongArch-Fix-DT_RELR-and-relaxation-interaction.patch b/LoongArch-Fix-DT_RELR-and-relaxation-interaction.patch deleted file mode 100644 index 88b0b0a..0000000 --- a/LoongArch-Fix-DT_RELR-and-relaxation-interaction.patch +++ /dev/null @@ -1,74 +0,0 @@ -From 9a78ebba126036f6ebdd15ffbe50ffbd8ccd84dd Mon Sep 17 00:00:00 2001 -From: Xi Ruoyao -Date: Mon, 12 Aug 2024 18:23:47 +0800 -Subject: [PATCH 108/123] LoongArch: Fix DT_RELR and relaxation interaction - -Due to the way BFD implements DT_RELR as a part of relaxation, if in a -relax trip size_relative_relocs has changed the layout, when -relax_section runs only the vma of the section being relaxed is -guaranteed to be updated. Then bad thing can happen. For example, when -linking an auxilary program _freeze_module in the Python 3.12.4 building -system (with PGO + LTO), before sizing the .relr.dyn section, the vma of -.text is 30560 and the vma of .rodata is 2350944; in the final -executable the vma of .text is 36704 and the vma of .rodata is 2357024. -The vma increase is expected because .relr.dyn is squashed somewhere -before .text. But size_relative_relocs may see the state in which .text -is at 36704 but .rodata "is" still at 2350944. Thus the distance -between .text and .rodata can be under-estimated and overflowing -R_LARCH_PCREL20_S2 reloc can be created. - -To avoid this issue, if size_relative_relocs is updating the size of -.relr.dyn, just supress the normal relaxation in this relax trip. In -this situation size_relative_relocs should have been demending the next -relax trip, so the normal relaxation can happen in the next trip. - -I tried to make a reduced test case but failed. - -Signed-off-by: Xi Ruoyao ---- - bfd/elfnn-loongarch.c | 15 +++++++++++++++ - 1 file changed, 15 insertions(+) - -diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c -index 73eea0f9..0c499c47 100644 ---- a/bfd/elfnn-loongarch.c -+++ b/bfd/elfnn-loongarch.c -@@ -121,6 +121,12 @@ struct loongarch_elf_link_hash_table - - /* Layout recomputation count. */ - bfd_size_type relr_layout_iter; -+ -+ /* In BFD DT_RELR is implemented as a "relaxation." If in a relax trip -+ size_relative_relocs is updating the layout, relax_section may see -+ a partially updated state (some sections have vma updated but the -+ others do not), and it's unsafe to do the normal relaxation. */ -+ bool layout_mutating_for_relr; - }; - - struct loongarch_elf_section_data -@@ -2210,6 +2216,8 @@ loongarch_elf_size_relative_relocs (struct bfd_link_info *info, - *need_layout = false; - } - } -+ -+ htab->layout_mutating_for_relr = *need_layout; - return true; - } - -@@ -5256,6 +5264,13 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, - return true; - - struct loongarch_elf_link_hash_table *htab = loongarch_elf_hash_table (info); -+ -+ /* It may happen that some sections have updated vma but the others do -+ not. Go to the next relax trip (size_relative_relocs should have -+ been demending another relax trip anyway). */ -+ if (htab->layout_mutating_for_relr) -+ return true; -+ - if (bfd_link_relocatable (info) - || sec->sec_flg0 - || (sec->flags & SEC_RELOC) == 0 --- -2.33.0 - diff --git a/LoongArch-Fix-a-bug-of-getting-relocation-type.patch b/LoongArch-Fix-a-bug-of-getting-relocation-type.patch deleted file mode 100644 index 7c92162..0000000 --- a/LoongArch-Fix-a-bug-of-getting-relocation-type.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 8b0f08599a65c649ce88b53b8042a13d1b307371 Mon Sep 17 00:00:00 2001 -From: mengqinggang -Date: Fri, 26 Jan 2024 11:16:49 +0800 -Subject: [PATCH 054/123] LoongArch: Fix a bug of getting relocation type - -The old code works because R_LARCH_RELAX has no symbol index. It causes -'(rel + 1)->r_info == R_LARCH_RELAX' is 1 and ELFNN_R_TYPE (1) is 1. ---- - bfd/elfnn-loongarch.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c -index 858b95e1..2e72fe5c 100644 ---- a/bfd/elfnn-loongarch.c -+++ b/bfd/elfnn-loongarch.c -@@ -4158,7 +4158,7 @@ loongarch_relax_tls_le (bfd *abfd, asection *sec, - static uint32_t insn_rj,insn_rd; - symval = symval - elf_hash_table (link_info)->tls_sec->vma; - /* Whether the symbol offset is in the interval (offset < 0x800). */ -- if (ELFNN_R_TYPE ((rel + 1)->r_info == R_LARCH_RELAX) && (symval < 0x800)) -+ if (ELFNN_R_TYPE ((rel + 1)->r_info) == R_LARCH_RELAX && (symval < 0x800)) - { - switch (ELFNN_R_TYPE (rel->r_info)) - { --- -2.33.0 - diff --git a/LoongArch-Fix-assertion-failure-with-DT_RELR.patch b/LoongArch-Fix-assertion-failure-with-DT_RELR.patch deleted file mode 100644 index 55c54b9..0000000 --- a/LoongArch-Fix-assertion-failure-with-DT_RELR.patch +++ /dev/null @@ -1,87 +0,0 @@ -From c49ea2f71e219ee85f2dd18ad18a928b135d45f9 Mon Sep 17 00:00:00 2001 -From: Xi Ruoyao -Date: Mon, 12 Aug 2024 18:23:46 +0800 -Subject: [PATCH 107/123] LoongArch: Fix assertion failure with DT_RELR - -In the DT_RELR implementation I missed a code path emiting relative -reloc entries. Then the already packed relative reloc entries will be -(unnecessarily) pushed into .rela.dyn but we've not allocated the space -for them, triggering an assertion failure. - -Unfortunately I failed to notice the issue until profiled bootstrapping -GCC with LTO and -Wl,-z,pack-relative-relocs. The failure can be easily -triggered by linking a "hello world" program with -fprofile-generate and -LTO: - - $ PATH=$HOME/ld-test:$PATH gcc hw.c -fprofile-generate -Wl,-z,pack-relative-relocs -flto - /home/xry111/git-repos/binutils-build/TEST/ld: BFD (GNU Binutils) 2.43.50.20240802 assertion fail ../../binutils-gdb/bfd/elfnn-loongarch.c:2628 - /home/xry111/git-repos/binutils-build/TEST/ld: BFD (GNU Binutils) 2.43.50.20240802 assertion fail ../../binutils-gdb/bfd/elfnn-loongarch.c:2628 - collect2: error: ld returned 1 exit status - -And the reduced test case is just incredibly simple (included in the -patch) so it seems I'm just stupid enough to fail to detect it before. -Let's fix it now anyway. - -Signed-off-by: Xi Ruoyao ---- - bfd/elfnn-loongarch.c | 3 ++- - ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp | 1 + - ld/testsuite/ld-loongarch-elf/relr-got-start.d | 7 +++++++ - ld/testsuite/ld-loongarch-elf/relr-got-start.s | 5 +++++ - 4 files changed, 15 insertions(+), 1 deletion(-) - create mode 100644 ld/testsuite/ld-loongarch-elf/relr-got-start.d - create mode 100644 ld/testsuite/ld-loongarch-elf/relr-got-start.s - -diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c -index adf16ddc..73eea0f9 100644 ---- a/bfd/elfnn-loongarch.c -+++ b/bfd/elfnn-loongarch.c -@@ -4130,7 +4130,8 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, - bfd_link_pic (info), - h) - && bfd_link_pic (info) -- && LARCH_REF_LOCAL (info, h)) -+ && LARCH_REF_LOCAL (info, h) -+ && !info->enable_dt_relr) - { - Elf_Internal_Rela rela; - rela.r_offset = sec_addr (got) + got_off; -diff --git a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -index 232e7c20..78726900 100644 ---- a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -+++ b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -@@ -161,6 +161,7 @@ if [istarget "loongarch64-*-*"] { - run_dump_test "relr-data-pie" - run_dump_test "relr-discard-pie" - run_dump_test "relr-got-pie" -+ run_dump_test "relr-got-start" - run_dump_test "relr-text-pie" - run_dump_test "abssym_pie" - } -diff --git a/ld/testsuite/ld-loongarch-elf/relr-got-start.d b/ld/testsuite/ld-loongarch-elf/relr-got-start.d -new file mode 100644 -index 00000000..0b1a5b98 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/relr-got-start.d -@@ -0,0 +1,7 @@ -+#source: relr-got-start.s -+#ld: -pie -z pack-relative-relocs -T relr-relocs.ld -+#readelf: -rW -+ -+Relocation section '\.relr\.dyn' at offset 0x[a-z0-f]+ contains 1 entry which relocates 1 location: -+Index: Entry Address Symbolic Address -+0000: 0000000000020008 0000000000020008 _GLOBAL_OFFSET_TABLE_ \+ 0x8 -diff --git a/ld/testsuite/ld-loongarch-elf/relr-got-start.s b/ld/testsuite/ld-loongarch-elf/relr-got-start.s -new file mode 100644 -index 00000000..c89fb425 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/relr-got-start.s -@@ -0,0 +1,5 @@ -+.globl _start -+_start: -+ pcalau12i $r5,%got_pc_hi20(_start) -+ ld.d $r5,$r5,%got_pc_lo12(_start) -+ ret --- -2.33.0 - diff --git a/LoongArch-Fix-bad-reloc-with-mixed-visibility-ifunc-.patch b/LoongArch-Fix-bad-reloc-with-mixed-visibility-ifunc-.patch deleted file mode 100644 index 73ee425..0000000 --- a/LoongArch-Fix-bad-reloc-with-mixed-visibility-ifunc-.patch +++ /dev/null @@ -1,269 +0,0 @@ -From 601d68c3a9866761ca19d1c27186f30de68a7af5 Mon Sep 17 00:00:00 2001 -From: Xi Ruoyao -Date: Sun, 30 Jun 2024 15:18:22 +0800 -Subject: [PATCH 096/123] LoongArch: Fix bad reloc with mixed visibility ifunc - symbols in shared libraries - -With a simple test case: - - .globl ifunc - .globl ifunc_hidden - .hidden ifunc_hidden - .type ifunc, %gnu_indirect_function - .type ifunc_hidden, %gnu_indirect_function - - .text - .align 2 - ifunc: ret - ifunc_hidden: ret - - test: - bl ifunc - bl ifunc_hidden - -"ld -shared" produces a shared object with one R_LARCH_NONE (instead of -R_LARCH_JUMP_SLOT as we expect) to relocate the GOT entry of "ifunc". -It's because the indices in .plt and .rela.plt mismatches for -STV_DEFAULT STT_IFUNC symbols when another PLT entry exists for a -STV_HIDDEN STT_IFUNC symbol, and such a mismatch breaks the logic of -loongarch_elf_finish_dynamic_symbol. Fix the issue by reordering .plt -so the indices no longer mismatch. - -Signed-off-by: Xi Ruoyao ---- - bfd/elfnn-loongarch.c | 77 ++++++++++++++++--- - ld/testsuite/ld-loongarch-elf/ifunc-reloc.d | 19 +++++ - ld/testsuite/ld-loongarch-elf/ifunc-reloc.s | 55 +++++++++++++ - .../ld-loongarch-elf/ld-loongarch-elf.exp | 1 + - 4 files changed, 140 insertions(+), 12 deletions(-) - create mode 100644 ld/testsuite/ld-loongarch-elf/ifunc-reloc.d - create mode 100644 ld/testsuite/ld-loongarch-elf/ifunc-reloc.s - -diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c -index fa0a5e38..6b1a4ecc 100644 ---- a/bfd/elfnn-loongarch.c -+++ b/bfd/elfnn-loongarch.c -@@ -1716,9 +1716,10 @@ local_allocate_ifunc_dyn_relocs (struct bfd_link_info *info, - ifunc dynamic relocs. */ - - static bool --elfNN_allocate_ifunc_dynrelocs (struct elf_link_hash_entry *h, void *inf) -+elfNN_allocate_ifunc_dynrelocs (struct elf_link_hash_entry *h, -+ struct bfd_link_info *info, -+ bool ref_local) - { -- struct bfd_link_info *info; - /* An example of a bfd_link_hash_indirect symbol is versioned - symbol. For example: __gxx_personality_v0(bfd_link_hash_indirect) - -> __gxx_personality_v0(bfd_link_hash_defined) -@@ -1734,20 +1735,18 @@ elfNN_allocate_ifunc_dynrelocs (struct elf_link_hash_entry *h, void *inf) - if (h->root.type == bfd_link_hash_warning) - h = (struct elf_link_hash_entry *) h->root.u.i.link; - -- info = (struct bfd_link_info *) inf; -- - /* Since STT_GNU_IFUNC symbol must go through PLT, we handle it - here if it is defined and referenced in a non-shared object. */ - if (h->type == STT_GNU_IFUNC && h->def_regular) - { -- if (SYMBOL_REFERENCES_LOCAL (info, h)) -+ if (ref_local && SYMBOL_REFERENCES_LOCAL (info, h)) - return local_allocate_ifunc_dyn_relocs (info, h, - &h->dyn_relocs, - PLT_ENTRY_SIZE, - PLT_HEADER_SIZE, - GOT_ENTRY_SIZE, - false); -- else -+ else if (!ref_local && !SYMBOL_REFERENCES_LOCAL (info, h)) - return _bfd_elf_allocate_ifunc_dyn_relocs (info, h, - &h->dyn_relocs, - PLT_ENTRY_SIZE, -@@ -1759,6 +1758,23 @@ elfNN_allocate_ifunc_dynrelocs (struct elf_link_hash_entry *h, void *inf) - return true; - } - -+static bool -+elfNN_allocate_ifunc_dynrelocs_ref_local (struct elf_link_hash_entry *h, -+ void *info) -+{ -+ return elfNN_allocate_ifunc_dynrelocs (h, (struct bfd_link_info *) info, -+ true); -+} -+ -+static bool -+elfNN_allocate_ifunc_dynrelocs_ref_global (struct elf_link_hash_entry *h, -+ void *info) -+{ -+ return elfNN_allocate_ifunc_dynrelocs (h, (struct bfd_link_info *) info, -+ false); -+} -+ -+ - /* Allocate space in .plt, .got and associated reloc sections for - ifunc dynamic relocs. */ - -@@ -1774,7 +1790,7 @@ elfNN_allocate_local_ifunc_dynrelocs (void **slot, void *inf) - || h->root.type != bfd_link_hash_defined) - abort (); - -- return elfNN_allocate_ifunc_dynrelocs (h, inf); -+ return elfNN_allocate_ifunc_dynrelocs_ref_local (h, inf); - } - - /* Set DF_TEXTREL if we find any dynamic relocs that apply to -@@ -1933,11 +1949,48 @@ loongarch_elf_size_dynamic_sections (bfd *output_bfd, - sym dynamic relocs. */ - elf_link_hash_traverse (&htab->elf, allocate_dynrelocs, info); - -- /* Allocate global ifunc sym .plt and .got entries, and space for global -- ifunc sym dynamic relocs. */ -- elf_link_hash_traverse (&htab->elf, elfNN_allocate_ifunc_dynrelocs, info); -- -- /* Allocate .plt and .got entries, and space for local ifunc symbols. */ -+ /* Allocate global ifunc sym .plt and .got entries, and space for -+ *preemptible* ifunc sym dynamic relocs. Note that we must do it -+ for *all* preemptible ifunc (including local ifuncs and STV_HIDDEN -+ ifuncs) before doing it for any non-preemptible ifunc symbol: -+ assuming we are not so careful, when we link a shared library the -+ correlation of .plt and .rela.plt might look like: -+ -+ idx in .plt idx in .rela.plt -+ ext_func1@plt 0 0 -+ ext_func2@plt 1 1 -+ ext_func3@plt 2 2 -+ hidden_ifunc1@plt 3 None: it's in .rela.got -+ hidden_ifunc2@plt 4 None: it's in .rela.got -+ normal_ifunc1@plt 5 != 3 -+ normal_ifunc2@plt 6 != 4 -+ local_ifunc@plt 7 None: it's in .rela.got -+ -+ Now oops the indices for normal_ifunc{1,2} in .rela.plt were different -+ from the indices in .plt :(. This would break finish_dynamic_symbol -+ which assumes the index in .rela.plt matches the index in .plt. -+ -+ So let's be careful and make it correct: -+ -+ idx in .plt idx in .rela.plt -+ ext_func1@plt 0 0 -+ ext_func2@plt 1 1 -+ ext_func3@plt 2 2 -+ normal_ifunc1@plt 3 3 -+ normal_ifunc2@plt 4 4 -+ hidden_ifunc1@plt 5 None: it's in .rela.got -+ hidden_ifunc2@plt 6 None: it's in .rela.got -+ local_ifunc@plt 7 None: it's in .rela.got -+ -+ Now normal_ifuncs first. */ -+ elf_link_hash_traverse (&htab->elf, -+ elfNN_allocate_ifunc_dynrelocs_ref_global, info); -+ -+ /* Next hidden_ifuncs follows. */ -+ elf_link_hash_traverse (&htab->elf, -+ elfNN_allocate_ifunc_dynrelocs_ref_local, info); -+ -+ /* Finally local_ifuncs. */ - htab_traverse (htab->loc_hash_table, - elfNN_allocate_local_ifunc_dynrelocs, info); - -diff --git a/ld/testsuite/ld-loongarch-elf/ifunc-reloc.d b/ld/testsuite/ld-loongarch-elf/ifunc-reloc.d -new file mode 100644 -index 00000000..cb592874 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/ifunc-reloc.d -@@ -0,0 +1,19 @@ -+#ld: -shared -+#readelf: -Wr -+ -+#... -+.*'\.rela\.dyn'.* -+#... -+.* R_LARCH_RELATIVE .* -+.* R_LARCH_IRELATIVE .* -+.* R_LARCH_IRELATIVE .* -+.* R_LARCH_IRELATIVE .* -+#... -+.*'\.rela\.plt'.* -+#... -+.* R_LARCH_JUMP_SLOT .* -+.* R_LARCH_JUMP_SLOT .* -+.* R_LARCH_JUMP_SLOT .* -+.* R_LARCH_JUMP_SLOT .* -+.* R_LARCH_JUMP_SLOT .* -+.* R_LARCH_JUMP_SLOT .* -diff --git a/ld/testsuite/ld-loongarch-elf/ifunc-reloc.s b/ld/testsuite/ld-loongarch-elf/ifunc-reloc.s -new file mode 100644 -index 00000000..e59f2b20 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/ifunc-reloc.s -@@ -0,0 +1,55 @@ -+.globl foo -+.globl foo_hidden1 -+.globl foo_hidden2 -+.globl foo_protected -+ -+.type foo, %gnu_indirect_function -+.type foo_hidden1, %gnu_indirect_function -+.type foo_hidden2, %gnu_indirect_function -+.type foo_protected, %gnu_indirect_function -+.type foo_internal, %gnu_indirect_function -+ -+.hidden foo_hidden1 -+.hidden foo_hidden2 -+ -+.protected foo_protected -+ -+.globl ext_ifunc1 -+.globl ext_ifunc2 -+.type ext_ifunc1, %gnu_indirect_function -+.type ext_ifunc2, %gnu_indirect_function -+ -+.text -+.align 2 -+foo: -+ ret -+ -+foo_hidden1: -+ ret -+ -+foo_hidden2: -+ ret -+ -+foo_protected: -+ ret -+ -+foo_internal: -+ ret -+ -+test: -+ la.got $a0, num -+ # The order is deliberately shuffled. -+ bl ext_ifunc1 -+ bl foo -+ bl foo_hidden1 -+ bl ext_func1 -+ bl foo_protected -+ bl foo_internal -+ bl foo_hidden2 -+ bl ext_func2 -+ bl ext_ifunc2 -+ -+.data -+.align 3 -+num: -+ .quad 114514 -diff --git a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -index 7ffabe2c..506dac3e 100644 ---- a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -+++ b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -@@ -133,6 +133,7 @@ if [istarget "loongarch64-*-*"] { - run_dump_test "reloc_ler_with_shared" - run_dump_test "reloc_abs_with_shared" - run_dump_test "r_larch_32_elf64" -+ run_dump_test "ifunc-reloc" - } - - if [check_pie_support] { --- -2.33.0 - diff --git a/LoongArch-Fix-dwarf3-test-cases-from-XPASS-to-PASS.patch b/LoongArch-Fix-dwarf3-test-cases-from-XPASS-to-PASS.patch deleted file mode 100644 index 5d265c0..0000000 --- a/LoongArch-Fix-dwarf3-test-cases-from-XPASS-to-PASS.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 30f91452b13e20976c0d470f1e097c083571459b Mon Sep 17 00:00:00 2001 -From: Lulu Cai -Date: Thu, 11 Jul 2024 19:00:43 +0800 -Subject: [PATCH 102/123] LoongArch: Fix dwarf3 test cases from XPASS to PASS - -In the past, the .align directive generated a label that did not match -the regular expression, and we set it to XFAIL. -But now it matches fine so it becomes XPASS. We fix it with PASS. ---- - ld/testsuite/ld-elf/dwarf.exp | 5 ----- - 1 file changed, 5 deletions(-) - -diff --git a/ld/testsuite/ld-elf/dwarf.exp b/ld/testsuite/ld-elf/dwarf.exp -index 5cb2aab9..3d1b99ac 100644 ---- a/ld/testsuite/ld-elf/dwarf.exp -+++ b/ld/testsuite/ld-elf/dwarf.exp -@@ -52,9 +52,6 @@ set build_tests { - {"DWARF parse during linker error" - "" "-fno-toplevel-reorder" - {dwarf2a.c dwarf2b.c} {{error_output "dwarf2.err"}} "dwarf2.x"} --} -- --set build_tests_dwarf3 { - {"Handle no DWARF information" - "" "-g0" - {dwarf3.c} {{error_output "dwarf3.err"}} "dwarf3.x"} -@@ -75,8 +72,6 @@ set run_tests { - set old_CFLAGS "$CFLAGS_FOR_TARGET" - append CFLAGS_FOR_TARGET " $NOSANITIZE_CFLAGS" - run_cc_link_tests $build_tests --setup_xfail loongarch*-*-* --run_cc_link_tests $build_tests_dwarf3 - run_ld_link_exec_tests $run_tests - set CFLAGS_FOR_TARGET "$old_CFLAGS" - --- -2.33.0 - diff --git a/LoongArch-Fix-gas-and-ld-test-cases.patch b/LoongArch-Fix-gas-and-ld-test-cases.patch deleted file mode 100644 index 05106f1..0000000 --- a/LoongArch-Fix-gas-and-ld-test-cases.patch +++ /dev/null @@ -1,149 +0,0 @@ -From e361b5c22683557c2214f8bb9032d80bb7c3d4e0 Mon Sep 17 00:00:00 2001 -From: Lulu Cai -Date: Thu, 7 Mar 2024 11:09:14 +0800 -Subject: [PATCH 072/123] LoongArch: Fix gas and ld test cases - -* After adding the old LE relax, all old LE relocations will have - an R_LARCH_RELAX relocation. Fix the gas test case failure caused - by the implementation of the old LE relax. - -* loongarch64-elf does not support pie and -z norelro options, - removed in test files. ---- - gas/testsuite/gas/loongarch/relocs_32.d | 2 ++ - gas/testsuite/gas/loongarch/relocs_64.d | 4 ++++ - ld/testsuite/ld-loongarch-elf/desc-le-norelax.d | 2 +- - ld/testsuite/ld-loongarch-elf/desc-le-relax.d | 2 +- - ld/testsuite/ld-loongarch-elf/ie-le-norelax.d | 2 +- - ld/testsuite/ld-loongarch-elf/ie-le-relax.d | 2 +- - ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp | 5 ++++- - ld/testsuite/ld-loongarch-elf/macro_op_32.d | 4 ++++ - 8 files changed, 18 insertions(+), 5 deletions(-) - -diff --git a/gas/testsuite/gas/loongarch/relocs_32.d b/gas/testsuite/gas/loongarch/relocs_32.d -index 3e1bb62e..96ef2800 100644 ---- a/gas/testsuite/gas/loongarch/relocs_32.d -+++ b/gas/testsuite/gas/loongarch/relocs_32.d -@@ -30,8 +30,10 @@ Disassembly of section .text: - 24: R_LARCH_GOT_LO12 .L1 - 28: 14000004 lu12i.w \$a0, 0 - 28: R_LARCH_TLS_LE_HI20 TLSL1 -+ 28: R_LARCH_RELAX \*ABS\* - 2c: 03800085 ori \$a1, \$a0, 0x0 - 2c: R_LARCH_TLS_LE_LO12 TLSL1 -+ 2c: R_LARCH_RELAX \*ABS\* - 30: 1a000004 pcalau12i \$a0, 0 - 30: R_LARCH_TLS_IE_PC_HI20 TLSL1 - 34: 02c00005 li.d \$a1, 0 -diff --git a/gas/testsuite/gas/loongarch/relocs_64.d b/gas/testsuite/gas/loongarch/relocs_64.d -index 631137eb..35dde02f 100644 ---- a/gas/testsuite/gas/loongarch/relocs_64.d -+++ b/gas/testsuite/gas/loongarch/relocs_64.d -@@ -48,12 +48,16 @@ Disassembly of section .text: - 48: R_LARCH_GOT64_HI12 .L1 - 4c: 14000004 lu12i.w \$a0, 0 - 4c: R_LARCH_TLS_LE_HI20 TLSL1 -+ 4c: R_LARCH_RELAX \*ABS\* - 50: 03800085 ori \$a1, \$a0, 0x0 - 50: R_LARCH_TLS_LE_LO12 TLSL1 -+ 50: R_LARCH_RELAX \*ABS\* - 54: 16000004 lu32i.d \$a0, 0 - 54: R_LARCH_TLS_LE64_LO20 TLSL1 -+ 54: R_LARCH_RELAX \*ABS\* - 58: 03000085 lu52i.d \$a1, \$a0, 0 - 58: R_LARCH_TLS_LE64_HI12 TLSL1 -+ 58: R_LARCH_RELAX \*ABS\* - 5c: 1a000004 pcalau12i \$a0, 0 - 5c: R_LARCH_TLS_IE_PC_HI20 TLSL1 - 60: 02c00005 li.d \$a1, 0 -diff --git a/ld/testsuite/ld-loongarch-elf/desc-le-norelax.d b/ld/testsuite/ld-loongarch-elf/desc-le-norelax.d -index 5a53245a..43749f1b 100644 ---- a/ld/testsuite/ld-loongarch-elf/desc-le-norelax.d -+++ b/ld/testsuite/ld-loongarch-elf/desc-le-norelax.d -@@ -1,5 +1,5 @@ - #as: --#ld: -z norelro -e0 --no-relax -+#ld: -e0 --no-relax - #objdump: -dr - #skip: loongarch32-*-* - -diff --git a/ld/testsuite/ld-loongarch-elf/desc-le-relax.d b/ld/testsuite/ld-loongarch-elf/desc-le-relax.d -index 03b5535e..71a540fd 100644 ---- a/ld/testsuite/ld-loongarch-elf/desc-le-relax.d -+++ b/ld/testsuite/ld-loongarch-elf/desc-le-relax.d -@@ -1,5 +1,5 @@ - #as: --#ld: -z norelro -e0 -+#ld: -e0 - #objdump: -dr -M no-aliases - #skip: loongarch32-*-* - -diff --git a/ld/testsuite/ld-loongarch-elf/ie-le-norelax.d b/ld/testsuite/ld-loongarch-elf/ie-le-norelax.d -index 81d78ca3..0221b495 100644 ---- a/ld/testsuite/ld-loongarch-elf/ie-le-norelax.d -+++ b/ld/testsuite/ld-loongarch-elf/ie-le-norelax.d -@@ -1,5 +1,5 @@ - #as: --#ld: -z norelro -e0 --no-relax -+#ld: -e0 --no-relax - #objdump: -dr - #skip: loongarch32-*-* - -diff --git a/ld/testsuite/ld-loongarch-elf/ie-le-relax.d b/ld/testsuite/ld-loongarch-elf/ie-le-relax.d -index 03b5535e..71a540fd 100644 ---- a/ld/testsuite/ld-loongarch-elf/ie-le-relax.d -+++ b/ld/testsuite/ld-loongarch-elf/ie-le-relax.d -@@ -1,5 +1,5 @@ - #as: --#ld: -z norelro -e0 -+#ld: -e0 - #objdump: -dr -M no-aliases - #skip: loongarch32-*-* - -diff --git a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -index ca428f5b..c839f525 100644 ---- a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -+++ b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -@@ -133,6 +133,10 @@ if [istarget "loongarch64-*-*"] { - run_dump_test "desc-relax" - } - -+ if [check_pie_support] { -+ run_dump_test "pie_discard" -+ } -+ - run_dump_test "max_imm_b16" - run_dump_test "max_imm_b21" - run_dump_test "max_imm_b26" -@@ -145,7 +149,6 @@ if [istarget "loongarch64-*-*"] { - run_dump_test "underflow_b21" - run_dump_test "underflow_b26" - run_dump_test "underflow_pcrel20" -- run_dump_test "pie_discard" - run_dump_test "desc-le-norelax" - run_dump_test "desc-le-relax" - run_dump_test "ie-le-norelax" -diff --git a/ld/testsuite/ld-loongarch-elf/macro_op_32.d b/ld/testsuite/ld-loongarch-elf/macro_op_32.d -index a7349aa8..8fd69922 100644 ---- a/ld/testsuite/ld-loongarch-elf/macro_op_32.d -+++ b/ld/testsuite/ld-loongarch-elf/macro_op_32.d -@@ -49,12 +49,16 @@ Disassembly of section .text: - 3c: R_LARCH_RELAX \*ABS\* - 40: 14000004 lu12i.w \$a0, 0 - 40: R_LARCH_TLS_LE_HI20 TLS1 -+ 40: R_LARCH_RELAX \*ABS\* - 44: 03800084 ori \$a0, \$a0, 0x0 - 44: R_LARCH_TLS_LE_LO12 TLS1 -+ 44: R_LARCH_RELAX \*ABS\* - 48: 1a000004 pcalau12i \$a0, 0 - 48: R_LARCH_TLS_IE_PC_HI20 TLS1 -+ 48: R_LARCH_RELAX \*ABS\* - 4c: 28800084 ld.w \$a0, \$a0, 0 - 4c: R_LARCH_TLS_IE_PC_LO12 TLS1 -+ 4c: R_LARCH_RELAX \*ABS\* - 50: 1a000004 pcalau12i \$a0, 0 - 50: R_LARCH_TLS_LD_PC_HI20 TLS1 - 50: R_LARCH_RELAX \*ABS\* --- -2.33.0 - diff --git a/LoongArch-Fix-immediate-overflow-check-bug.patch b/LoongArch-Fix-immediate-overflow-check-bug.patch deleted file mode 100644 index 739dec0..0000000 --- a/LoongArch-Fix-immediate-overflow-check-bug.patch +++ /dev/null @@ -1,42 +0,0 @@ -From 1dfd5f57202ef519e7ae21219be9c16e7a163072 Mon Sep 17 00:00:00 2001 -From: mengqinggang -Date: Sat, 15 Jul 2023 17:56:07 +0800 -Subject: [PATCH 001/123] LoongArch: Fix immediate overflow check bug - -For B16/B21/B26/PCREL20_S2 relocations, if immediate overflow check after -rightshift, and the mask need to include sign bit. - -Now, the immediate overflow check before rightshift for easier understand. - -bfd/ChangeLog: - - * elfxx-loongarch.c (reloc_bits_pcrel20_s2): Delete. - (reloc_bits_b16): Delete. - (reloc_bits_b21): Delete. - (reloc_bits_b26): Delete. - (reloc_sign_bits): New. ---- - bfd/elfxx-loongarch.c | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - -diff --git a/bfd/elfxx-loongarch.c b/bfd/elfxx-loongarch.c -index 35676ead..16a2b2fc 100644 ---- a/bfd/elfxx-loongarch.c -+++ b/bfd/elfxx-loongarch.c -@@ -1708,10 +1708,12 @@ reloc_sign_bits (bfd *abfd, reloc_howto_type *howto, bfd_vma *fix_val) - { - case R_LARCH_SOP_POP_32_S_0_10_10_16_S2: - case R_LARCH_B26: -- /* Perform insn bits field. 25:16>>16, 15:0<<10. */ -+ /* Perform insn bits field. 15:0<<10, 25:16>>16. */ - val = ((val & 0xffff) << 10) | ((val >> 16) & 0x3ff); - break; -+ case R_LARCH_SOP_POP_32_S_0_5_10_16_S2: - case R_LARCH_B21: -+ /* Perform insn bits field. 15:0<<10, 20:16>>16. */ - val = ((val & 0xffff) << 10) | ((val >> 16) & 0x1f); - break; - default: --- -2.33.0 - diff --git a/LoongArch-Fix-ld-FAIL-test-cases.patch b/LoongArch-Fix-ld-FAIL-test-cases.patch deleted file mode 100644 index efd8e1b..0000000 --- a/LoongArch-Fix-ld-FAIL-test-cases.patch +++ /dev/null @@ -1,91 +0,0 @@ -From 32434338ecb0d5547e2cb7986f98040bc726f43f Mon Sep 17 00:00:00 2001 -From: Lulu Cai -Date: Wed, 17 Jul 2024 10:54:46 +0800 -Subject: [PATCH 104/123] LoongArch: Fix ld FAIL test cases - -To avoid differences in C library paths on different systems -use gcc instead of ld to perform the test. - -Problems caused by adding options to different distributions -will not be fixed. ---- - ld/testsuite/ld-loongarch-elf/pic.exp | 41 ++++++++++++++++----------- - 1 file changed, 24 insertions(+), 17 deletions(-) - -diff --git a/ld/testsuite/ld-loongarch-elf/pic.exp b/ld/testsuite/ld-loongarch-elf/pic.exp -index 2ca5b3a0..241d198d 100644 ---- a/ld/testsuite/ld-loongarch-elf/pic.exp -+++ b/ld/testsuite/ld-loongarch-elf/pic.exp -@@ -92,17 +92,6 @@ set link_tests [list \ - ] \ - "nopic-global" \ - ] \ -- [list \ -- "$testname readelf -s/-r nopic-global-so" \ -- "-L./tmpdir -lnopic-global -L/usr/lib -lc" "" \ -- "" \ -- {nopic-global.s} \ -- [list \ -- [list readelf -s nopic-global-so.sd] \ -- [list readelf -r nopic-global-so.rd] \ -- ] \ -- "nopic-global-so" \ -- ] \ - [list \ - "$testname readelf -s/-x nopic-weak-global" \ - "-T pic.ld" "" \ -@@ -114,19 +103,35 @@ set link_tests [list \ - ] \ - "nopic-weak-global" \ - ] \ -+] -+ -+# Since the c library path may be different in different -+# Distributions, the test program can link to the c library -+# using the gcc instead of ld to avoid system impact. -+run_ld_link_tests $link_tests -+ -+ -+ -+set link_tests_libc [list \ -+ [list \ -+ "$testname readelf -s/-r nopic-global-so" \ -+ "-L./tmpdir -lnopic-global -L/usr/lib -lc" "" \ -+ {nopic-global.s} \ -+ {{readelf {-s} nopic-global-so.sd} \ -+ {readelf {-r} nopic-global-so.rd}} \ -+ "nopic-global-so" \ -+ ] \ - [list \ - "$testname readelf -s/-x nopic-weak-global-so" \ - "-L./tmpdir -lnopic-global -L/usr/lib -lc" "" \ -- "" \ - {nopic-weak-global.s} \ -- [list \ -- [list readelf -s nopic-weak-global-so.sd] \ -- [list readelf -r nopic-weak-global-so.rd] \ -- ] \ -+ {{readelf {-s} nopic-weak-global-so.sd} \ -+ {readelf {-r} nopic-weak-global-so.rd}} \ - "nopic-weak-global-so" \ - ] \ - ] - -+ - # 0:name - # 1:ld/ar leading options, placed before object files - # 2:ld/ar trailing options, placed after object files -@@ -135,7 +140,9 @@ set link_tests [list \ - # 5:list of actions, options and expected outputs. - # 6:name of output file - # 7:compiler flags (optional) --run_ld_link_tests $link_tests -+run_cc_link_tests $link_tests_libc -+ -+ - - set testname "nopic link exec test" - --- -2.33.0 - diff --git a/LoongArch-Fix-ld-no-relax-bug.patch b/LoongArch-Fix-ld-no-relax-bug.patch deleted file mode 100644 index 756fda7..0000000 --- a/LoongArch-Fix-ld-no-relax-bug.patch +++ /dev/null @@ -1,56 +0,0 @@ -From 363174776d13db9f35f2e54d8f7f5e34b64acbee Mon Sep 17 00:00:00 2001 -From: mengqinggang -Date: Thu, 16 Nov 2023 19:19:11 +0800 -Subject: [PATCH] LoongArch: Fix ld --no-relax bug - -When calling ld with --no-relax, pcalau12i + ld.d still can be relaxed. -This patch fix this bug and pcalau12i + ld.d can be relaxed with --relax. - -Signed-off-by: Peng Fan ---- - bfd/elfnn-loongarch.c | 19 ++++++------------- - 1 file changed, 6 insertions(+), 13 deletions(-) - -diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c -index 18ad3cc91ca..1162cb35cd6 100644 ---- a/bfd/elfnn-loongarch.c -+++ b/bfd/elfnn-loongarch.c -@@ -3996,29 +3996,22 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, - loongarch_relax_align (abfd, sec, sym_sec, info, rel, symval); - break; - case R_LARCH_DELETE: -- if (info->relax_pass == 1) -+ if (1 == info->relax_pass) - { - loongarch_relax_delete_bytes (abfd, sec, rel->r_offset, 4, info); - rel->r_info = ELFNN_R_INFO (0, R_LARCH_NONE); - } - break; - case R_LARCH_PCALA_HI20: -- if (info->relax_pass == 0) -- { -- if (i + 4 > sec->reloc_count) -- break; -- loongarch_relax_pcala_addi (abfd, sec, rel, symval); -- } -+ if (0 == info->relax_pass && (i + 4) <= sec->reloc_count) -+ loongarch_relax_pcala_addi (abfd, sec, rel, symval); - break; - case R_LARCH_GOT_PC_HI20: -- if (local_got) -+ if (local_got && 0 == info->relax_pass -+ && (i + 4) <= sec->reloc_count) - { -- if (i + 4 > sec->reloc_count) -- break; - if (loongarch_relax_pcala_ld (abfd, sec, rel)) -- { -- loongarch_relax_pcala_addi (abfd, sec, rel, symval); -- } -+ loongarch_relax_pcala_addi (abfd, sec, rel, symval); - } - break; - default: --- -2.33.0 - diff --git a/LoongArch-Fix-ld-test-failures-caused-by-using-instr.patch b/LoongArch-Fix-ld-test-failures-caused-by-using-instr.patch deleted file mode 100644 index bb9ae1a..0000000 --- a/LoongArch-Fix-ld-test-failures-caused-by-using-instr.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 765057030817ea3083dd7a7ca607c89d21d4eed3 Mon Sep 17 00:00:00 2001 -From: Lulu Cai -Date: Tue, 23 Apr 2024 15:49:09 +0800 -Subject: [PATCH 085/123] LoongArch: Fix ld test failures caused by using - instruction aliases - -Different versions of objdump may take different forms of output -for instructions. Use -M no-aliases to avoid the failure of ld -test cases caused by objdump using aliases. ---- - ld/testsuite/ld-loongarch-elf/relax.exp | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/ld/testsuite/ld-loongarch-elf/relax.exp b/ld/testsuite/ld-loongarch-elf/relax.exp -index bfd6d1c0..c1da9c10 100644 ---- a/ld/testsuite/ld-loongarch-elf/relax.exp -+++ b/ld/testsuite/ld-loongarch-elf/relax.exp -@@ -37,7 +37,7 @@ proc run_partial_linking_align_test {} { - || ![ld_link $ld tmpdir/$testname "tmpdir/$testname.os -e0 -Ttext 0x1000"] } { - fail $testname - } else { -- set objdump_output [run_host_cmd "objdump" "-d tmpdir/$testname"] -+ set objdump_output [run_host_cmd "objdump" "-d -M no-aliases tmpdir/$testname"] - if { [ regexp ".*1010:\\s*4c000020\\s*jirl.*" $objdump_output ] } { - pass $testname - } else { --- -2.33.0 - diff --git a/LoongArch-Fix-linker-generate-PLT-entry-for-data-sym.patch b/LoongArch-Fix-linker-generate-PLT-entry-for-data-sym.patch deleted file mode 100644 index 19284f1..0000000 --- a/LoongArch-Fix-linker-generate-PLT-entry-for-data-sym.patch +++ /dev/null @@ -1,121 +0,0 @@ -From 9836fa5ff54d6543ab05e552579810ef150d8a77 Mon Sep 17 00:00:00 2001 -From: mengqinggang -Date: Thu, 1 Dec 2022 17:23:14 +0800 -Subject: [PATCH 039/123] LoongArch: Fix linker generate PLT entry for data - symbol - -With old "medium" code model, we call a function with a pair of PCALAU12I -and JIRL instructions. The assembler produces something like: - - 8: 1a00000c pcalau12i $t0, 0 - 8: R_LARCH_PCALA_HI20 g - c: 4c000181 jirl $ra, $t0, 0 - c: R_LARCH_PCALA_LO12 g - -The linker generates a "PLT entry" for data without any diagnostic. -If "g" is a data symbol and ld with -shared option, it may load two -instructions in the PLT. - -Without -shared option, loongarch_elf_adjust_dynamic_symbol can delete PLT -entry. - -For R_LARCH_PCALA_HI20 relocation, linker only generate PLT entry for STT_FUNC -and STT_GNU_IFUNC symbols. ---- - bfd/elfnn-loongarch.c | 6 ++++- - ld/testsuite/ld-loongarch-elf/data-plt.s | 20 ++++++++++++++++ - .../ld-loongarch-elf/ld-loongarch-elf.exp | 24 +++++++++++++++++++ - ld/testsuite/ld-loongarch-elf/libjirl.s | 1 + - 4 files changed, 50 insertions(+), 1 deletion(-) - create mode 100644 ld/testsuite/ld-loongarch-elf/data-plt.s - -diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c -index f7eb66da..73e4b819 100644 ---- a/bfd/elfnn-loongarch.c -+++ b/bfd/elfnn-loongarch.c -@@ -891,8 +891,12 @@ loongarch_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, - h->non_got_ref = 1; - break; - -+ /* For normal cmodel, pcalau12i + addi.d/w used to data. -+ For first version medium cmodel, pcalau12i + jirl are used to -+ function call, it need to creat PLT entry for STT_FUNC and -+ STT_GNU_IFUNC type symbol. */ - case R_LARCH_PCALA_HI20: -- if (h != NULL) -+ if (h != NULL && (STT_FUNC == h->type || STT_GNU_IFUNC == h->type)) - { - /* For pcalau12i + jirl. */ - h->needs_plt = 1; -diff --git a/ld/testsuite/ld-loongarch-elf/data-plt.s b/ld/testsuite/ld-loongarch-elf/data-plt.s -new file mode 100644 -index 00000000..faff052c ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/data-plt.s -@@ -0,0 +1,20 @@ -+# The first version medium codel model function call is: pcalau12i + jirl. -+# R_LARCH_PCALA_HI20 only need to generate PLT entry for function symbols. -+ .text -+ .globl a -+ -+ .data -+ .align 2 -+ .type a, @object -+ .size a, 4 -+a: -+ .word 1 -+ -+ .text -+ .align 2 -+ .globl test -+ .type test, @function -+test: -+ pcalau12i $r12,%pc_hi20(a) -+ ld.w $r12,$r12,%pc_lo12(a) -+ .size test, .-test -diff --git a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -index 8dc04fea..64e644d3 100644 ---- a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -+++ b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -@@ -59,6 +59,30 @@ if [istarget "loongarch64-*-*"] { - ] - } - -+ # loongarch*-elf target do not support -shared option -+ if [check_shared_lib_support] { -+ run_ld_link_tests \ -+ [list \ -+ [list \ -+ "data plt" \ -+ "-shared" "" \ -+ "" \ -+ {data-plt.s} \ -+ {} \ -+ "data-plt.so" \ -+ ] \ -+ ] -+ -+ if [file exist "tmpdir/data-plt.so"] { -+ set objdump_output [run_host_cmd "objdump" "-d tmpdir/data-plt.so"] -+ if { [ regexp "" $objdump_output] } { -+ fail "data plt" -+ } { -+ pass "data plt" -+ } -+ } -+ } -+ - run_ld_link_tests \ - [list \ - [list \ -diff --git a/ld/testsuite/ld-loongarch-elf/libjirl.s b/ld/testsuite/ld-loongarch-elf/libjirl.s -index 4d963870..de028c5a 100644 ---- a/ld/testsuite/ld-loongarch-elf/libjirl.s -+++ b/ld/testsuite/ld-loongarch-elf/libjirl.s -@@ -1,2 +1,3 @@ -+.type func @function - pcalau12i $r12, %pc_hi20(func) - jirl $r1,$r12, %pc_lo12(func) --- -2.33.0 - diff --git a/LoongArch-Fix-loongarch-elf-target-ld-testsuite-fail.patch b/LoongArch-Fix-loongarch-elf-target-ld-testsuite-fail.patch deleted file mode 100644 index 008aa52..0000000 --- a/LoongArch-Fix-loongarch-elf-target-ld-testsuite-fail.patch +++ /dev/null @@ -1,206 +0,0 @@ -From e86a0c83da7c0d80f02428d400538113f8294757 Mon Sep 17 00:00:00 2001 -From: Lulu Cai -Date: Wed, 27 Dec 2023 17:10:41 +0800 -Subject: [PATCH 038/123] LoongArch: Fix loongarch*-elf target ld testsuite - failure - -The loongarch*-elf target does not support SHARED and PIE, so this -target is skipped for some tests that require these options. ---- - .../ld-loongarch-elf/ld-loongarch-elf.exp | 30 +++--- - .../ld-loongarch-elf/local-ifunc-reloc.d | 1 + - ld/testsuite/ld-loongarch-elf/relax.exp | 99 ++++++++++--------- - 3 files changed, 71 insertions(+), 59 deletions(-) - -diff --git a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -index 2a5709a5..8dc04fea 100644 ---- a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -+++ b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -@@ -43,19 +43,21 @@ if [istarget "loongarch32-*-*"] { - } - - if [istarget "loongarch64-*-*"] { -- run_ld_link_tests \ -- [list \ -- [list \ -- "64_pcrel" \ -- "-e 0x0 -z relro" "" \ -- "" \ -- {64_pcrel.s} \ -- [list \ -- [list objdump -D 64_pcrel.d] \ -- ] \ -- "64_pcrel" \ -- ] \ -- ] -+ if [check_shared_lib_support] { -+ run_ld_link_tests \ -+ [list \ -+ [list \ -+ "64_pcrel" \ -+ "-e 0x0 -z relro" "" \ -+ "" \ -+ {64_pcrel.s} \ -+ [list \ -+ [list objdump -D 64_pcrel.d] \ -+ ] \ -+ "64_pcrel" \ -+ ] \ -+ ] -+ } - - run_ld_link_tests \ - [list \ -@@ -71,10 +73,12 @@ if [istarget "loongarch64-*-*"] { - } - - if [istarget "loongarch64-*-*"] { -+ if [check_shared_lib_support] { - run_dump_test "desc-ie" - run_dump_test "desc-le" - run_dump_test "ie-le" - run_dump_test "tlsdesc-dso" - run_dump_test "desc-norelax" - run_dump_test "desc-relax" -+ } - } -diff --git a/ld/testsuite/ld-loongarch-elf/local-ifunc-reloc.d b/ld/testsuite/ld-loongarch-elf/local-ifunc-reloc.d -index bf73d9f2..8e1d3f0d 100644 ---- a/ld/testsuite/ld-loongarch-elf/local-ifunc-reloc.d -+++ b/ld/testsuite/ld-loongarch-elf/local-ifunc-reloc.d -@@ -1,6 +1,7 @@ - #as: - #ld: -shared -z combreloc - #objdump: -R -+#skip: loongarch*-elf - - .*: +file format .* - -diff --git a/ld/testsuite/ld-loongarch-elf/relax.exp b/ld/testsuite/ld-loongarch-elf/relax.exp -index b697d015..6c65318a 100644 ---- a/ld/testsuite/ld-loongarch-elf/relax.exp -+++ b/ld/testsuite/ld-loongarch-elf/relax.exp -@@ -150,17 +150,19 @@ if [istarget loongarch64-*-*] { - } - } - -- run_ld_link_tests \ -- [list \ -- [list \ -- "loongarch relax .so build" \ -- "-shared -e 0x0" "" \ -- "" \ -- {relax-so.s} \ -- {} \ -- "relax-so" \ -- ] \ -- ] -+ if [check_shared_lib_support] { -+ run_ld_link_tests \ -+ [list \ -+ [list \ -+ "loongarch relax .so build" \ -+ "-shared -e 0x0" "" \ -+ "" \ -+ {relax-so.s} \ -+ {} \ -+ "relax-so" \ -+ ] \ -+ ] -+ } - - if [file exist "tmpdir/relax-so"] { - set objdump_output [run_host_cmd "objdump" "-d tmpdir/relax-so"] -@@ -173,29 +175,31 @@ if [istarget loongarch64-*-*] { - - # If symbol in data segment, offset need to sub segment align to prevent - # overflow. -- run_ld_link_tests \ -- [list \ -- [list \ -- "loongarch relax segment alignment min" \ -- "-e0 -Ttext 0x120004000 -pie -z relro" "" \ -- "" \ -- {relax-segment-min.s} \ -- {} \ -- "relax-segment-min" \ -- ] \ -- ] -+ if [check_pie_support] { -+ run_ld_link_tests \ -+ [list \ -+ [list \ -+ "loongarch relax segment alignment min" \ -+ "-e0 -Ttext 0x120004000 -pie -z relro" "" \ -+ "" \ -+ {relax-segment-min.s} \ -+ {} \ -+ "relax-segment-min" \ -+ ] \ -+ ] - -- run_ld_link_tests \ -- [list \ -- [list \ -- "loongarch relax segment alignment max" \ -- "-e0 -Ttext 0x120004000 -pie -z relro" "" \ -- "" \ -- {relax-segment-max.s} \ -- {} \ -- "relax-segment-max" \ -- ] \ -- ] -+ run_ld_link_tests \ -+ [list \ -+ [list \ -+ "loongarch relax segment alignment max" \ -+ "-e0 -Ttext 0x120004000 -pie -z relro" "" \ -+ "" \ -+ {relax-segment-max.s} \ -+ {} \ -+ "relax-segment-max" \ -+ ] \ -+ ] -+ } - - if [file exist "tmpdir/relax-tls-le"] { - set objdump_output1 [run_host_cmd "objdump" "-d tmpdir/relax-tls-le"] -@@ -265,19 +269,22 @@ if [istarget loongarch64-*-*] { - } - - } -- run_ld_link_tests \ -- [list \ -- [list \ -- "loongarch relax-align" \ -- "-e 0x0 -z relro" "" \ -- "--no-warn" \ -- {relax-align.s} \ -- [list \ -- [list objdump -d relax-align.dd] \ -- ] \ -- "relax-align" \ -- ] \ -- ] -+ -+ if [check_shared_lib_support] { -+ run_ld_link_tests \ -+ [list \ -+ [list \ -+ "loongarch relax-align" \ -+ "-e 0x0 -z relro" "" \ -+ "--no-warn" \ -+ {relax-align.s} \ -+ [list \ -+ [list objdump -d relax-align.dd] \ -+ ] \ -+ "relax-align" \ -+ ] \ -+ ] -+ } - - set objdump_flags "-s -j .data" - run_ld_link_tests \ --- -2.33.0 - diff --git a/LoongArch-Fix-relaxation-overflow-caused-by-ld-z-sep.patch b/LoongArch-Fix-relaxation-overflow-caused-by-ld-z-sep.patch deleted file mode 100644 index a48ea36..0000000 --- a/LoongArch-Fix-relaxation-overflow-caused-by-ld-z-sep.patch +++ /dev/null @@ -1,413 +0,0 @@ -From a86ce43d41f2b4453d1137939f25c7b2c68215ee Mon Sep 17 00:00:00 2001 -From: mengqinggang -Date: Wed, 22 May 2024 14:27:08 +0800 -Subject: [PATCH 088/123] LoongArch: Fix relaxation overflow caused by ld -z - separate-code - -ld -z separate-code let .text and .rodata in two different but read only -segment. If the symbol and pc in two segment, the offset from pc to -symbol need to consider segment alignment. - -Add a function 'loongarch_two_sections_in_same_segment' to determine -whether two sections are in the same segment. ---- - bfd/elfnn-loongarch.c | 101 +++++++++++------- - .../ld-loongarch-elf/relax-medium-call-1.d | 51 ++++++--- - .../ld-loongarch-elf/relax-medium-call-1.s | 6 +- - .../ld-loongarch-elf/relax-medium-call.d | 51 ++++++--- - .../ld-loongarch-elf/relax-medium-call.s | 6 +- - .../relax-separate-code-overflow.s | 21 ++++ - ld/testsuite/ld-loongarch-elf/relax.exp | 15 +++ - 7 files changed, 176 insertions(+), 75 deletions(-) - create mode 100644 ld/testsuite/ld-loongarch-elf/relax-separate-code-overflow.s - -diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c -index 47fd08cd..eb572a77 100644 ---- a/bfd/elfnn-loongarch.c -+++ b/bfd/elfnn-loongarch.c -@@ -3948,6 +3948,12 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, - info->callbacks->reloc_overflow - (info, h ? &h->root : NULL, name, howto->name, rel->r_addend, - input_bfd, input_section, rel->r_offset); -+ if (r_type == R_LARCH_PCREL20_S2 -+ || r_type == R_LARCH_TLS_LD_PCREL20_S2 -+ || r_type == R_LARCH_TLS_GD_PCREL20_S2 -+ || r_type == R_LARCH_TLS_DESC_PCREL20_S2) -+ _bfd_error_handler (_("recompile with 'gcc -mno-relax' or" -+ " 'as -mno-relax' or 'ld --no-relax'")); - break; - - case bfd_reloc_outofrange: -@@ -4312,6 +4318,30 @@ loongarch_relax_tls_le (bfd *abfd, asection *sec, - return true; - } - -+/* Whether two sections in the same segment. */ -+static bool -+loongarch_two_sections_in_same_segment (bfd *abfd, asection *a, asection *b) -+{ -+ struct elf_segment_map *m; -+ for (m = elf_seg_map (abfd); m != NULL; m = m->next) -+ { -+ int i; -+ int j = 0; -+ for (i = m->count - 1; i >= 0; i--) -+ { -+ if (m->sections[i] == a) -+ j++; -+ if (m->sections[i] == b) -+ j++; -+ } -+ if (1 == j) -+ return false; -+ if (2 == j) -+ return true; -+ } -+ return false; -+} -+ - /* Relax pcalau12i,addi.d => pcaddi. */ - static bool - loongarch_relax_pcala_addi (bfd *abfd, asection *sec, asection *sym_sec, -@@ -4332,23 +4362,17 @@ loongarch_relax_pcala_addi (bfd *abfd, asection *sec, asection *sym_sec, - sec->output_offset = sec->output_section->size; - bfd_vma pc = sec_addr (sec) + rel_hi->r_offset; - -- /* If pc and symbol not in the same segment, add/sub segment alignment. -- FIXME: if there are multiple readonly segments? How to determine if -- two sections are in the same segment. */ -- if (!(sym_sec->flags & SEC_READONLY)) -- { -- max_alignment = info->maxpagesize > max_alignment ? info->maxpagesize -- : max_alignment; -- if (symval > pc) -- pc -= max_alignment; -- else if (symval < pc) -- pc += max_alignment; -- } -- else -- if (symval > pc) -- pc -= max_alignment; -- else if (symval < pc) -- pc += max_alignment; -+ /* If pc and symbol not in the same segment, add/sub segment alignment. */ -+ if (!loongarch_two_sections_in_same_segment (info->output_bfd, -+ sec->output_section, -+ sym_sec->output_section)) -+ max_alignment = info->maxpagesize > max_alignment ? info->maxpagesize -+ : max_alignment; -+ -+ if (symval > pc) -+ pc -= (max_alignment > 4 ? max_alignment : 0); -+ else if (symval < pc) -+ pc += (max_alignment > 4 ? max_alignment : 0); - - const uint32_t addi_d = 0x02c00000; - const uint32_t pcaddi = 0x18000000; -@@ -4387,7 +4411,7 @@ loongarch_relax_pcala_addi (bfd *abfd, asection *sec, asection *sym_sec, - /* call36 f -> bl f - tail36 $t0, f -> b f. */ - static bool --loongarch_relax_call36 (bfd *abfd, asection *sec, -+loongarch_relax_call36 (bfd *abfd, asection *sec, asection *sym_sec, - Elf_Internal_Rela *rel, bfd_vma symval, - struct bfd_link_info *info, bool *again, - bfd_vma max_alignment) -@@ -4403,9 +4427,13 @@ loongarch_relax_call36 (bfd *abfd, asection *sec, - sec->output_offset = sec->output_section->size; - bfd_vma pc = sec_addr (sec) + rel->r_offset; - -- /* If pc and symbol not in the same segment, add/sub segment alignment. -- FIXME: if there are multiple readonly segments? How to determine if -- two sections are in the same segment. */ -+ /* If pc and symbol not in the same segment, add/sub segment alignment. */ -+ if (!loongarch_two_sections_in_same_segment (info->output_bfd, -+ sec->output_section, -+ sym_sec->output_section)) -+ max_alignment = info->maxpagesize > max_alignment ? info->maxpagesize -+ : max_alignment; -+ - if (symval > pc) - pc -= (max_alignment > 4 ? max_alignment : 0); - else if (symval < pc) -@@ -4559,22 +4587,17 @@ loongarch_relax_tls_ld_gd_desc (bfd *abfd, asection *sec, asection *sym_sec, - sec->output_offset = sec->output_section->size; - bfd_vma pc = sec_addr (sec) + rel_hi->r_offset; - -- /* If pc and symbol not in the same segment, add/sub segment alignment. -- FIXME: if there are multiple readonly segments? */ -- if (!(sym_sec->flags & SEC_READONLY)) -- { -- max_alignment = info->maxpagesize > max_alignment ? info->maxpagesize -- : max_alignment; -- if (symval > pc) -- pc -= max_alignment; -- else if (symval < pc) -- pc += max_alignment; -- } -- else -- if (symval > pc) -- pc -= max_alignment; -- else if (symval < pc) -- pc += max_alignment; -+ /* If pc and symbol not in the same segment, add/sub segment alignment. */ -+ if (!loongarch_two_sections_in_same_segment (info->output_bfd, -+ sec->output_section, -+ sym_sec->output_section)) -+ max_alignment = info->maxpagesize > max_alignment ? info->maxpagesize -+ : max_alignment; -+ -+ if (symval > pc) -+ pc -= (max_alignment > 4 ? max_alignment : 0); -+ else if (symval < pc) -+ pc += (max_alignment > 4 ? max_alignment : 0); - - const uint32_t addi_d = 0x02c00000; - const uint32_t pcaddi = 0x18000000; -@@ -4858,8 +4881,8 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, - break; - case R_LARCH_CALL36: - if (0 == info->relax_pass && (i + 2) <= sec->reloc_count) -- loongarch_relax_call36 (abfd, sec, rel, symval, info, again, -- max_alignment); -+ loongarch_relax_call36 (abfd, sec, sym_sec, rel, symval, -+ info, again, max_alignment); - break; - - case R_LARCH_TLS_LE_HI20_R: -diff --git a/ld/testsuite/ld-loongarch-elf/relax-medium-call-1.d b/ld/testsuite/ld-loongarch-elf/relax-medium-call-1.d -index c8ee9333..96e7bb09 100644 ---- a/ld/testsuite/ld-loongarch-elf/relax-medium-call-1.d -+++ b/ld/testsuite/ld-loongarch-elf/relax-medium-call-1.d -@@ -1,21 +1,42 @@ --#ld: -e0 -Ttext=0x120000000 --section-start=ta=0x118000000 --section-start=tb=0x127fffffc --#objdump: -d -j .text -+#ld: -e0 -+#objdump: -d - - .*:[ ]+file format .* - - - Disassembly of section .text: - --[ ]*0000000120000000 <__bss_start-0x4030>: --[ ]+120000000:[ ]+54000200[ ]+bl[ ]+-134217728[ ]+# 118000000 --[ ]+120000004:[ ]+1fffc001[ ]+pcaddu18i[ ]+\$ra, -512 --[ ]+120000008:[ ]+4ffffc21[ ]+jirl[ ]+\$ra, \$ra, -4 --[ ]+12000000c:[ ]+50000200[ ]+b[ ]+-134217728[ ]+# 11800000c --[ ]+120000010:[ ]+1fffc00c[ ]+pcaddu18i[ ]+\$t0, -512 --[ ]+120000014:[ ]+4ffffd80[ ]+jirl[ ]+\$zero, \$t0, -4 --[ ]+120000018:[ ]+1e004001[ ]+pcaddu18i[ ]+\$ra, 512 --[ ]+12000001c:[ ]+4c000421[ ]+jirl[ ]+\$ra, \$ra, 4 --[ ]+120000020:[ ]+57fffdff[ ]+bl[ ]+134217724[ ]+# 12800001c --[ ]+120000024:[ ]+1e00400c[ ]+pcaddu18i[ ]+\$t0, 512 --[ ]+120000028:[ ]+4c000580[ ]+jirl[ ]+\$zero, \$t0, 4 --[ ]+12000002c:[ ]+53fffdff[ ]+b[ ]+134217724[ ]+# 128000028 -+[ ]*0000000120000078 : -+[ ]+120000078:[ ]+4c000020[ ]+ret -+[ ]+12000007c:[ ]+4c000020[ ]+ret -+[ ]+120000080:[ ]+4c000020[ ]+ret -+[ ]*0000000120000084 : -+[ ]+120000084:[ ]+4c000020[ ]+ret -+[ ]+... -+[ ]+128000078:[ ]+54000200[ ]+bl[ ]+-134217728[ ]+# 120000078 -+[ ]+12800007c:[ ]+1fffc001[ ]+pcaddu18i[ ]+\$ra, -512 -+[ ]+128000080:[ ]+4ffffc21[ ]+jirl[ ]+\$ra, \$ra, -4 -+[ ]+128000084:[ ]+50000200[ ]+b[ ]+-134217728[ ]+# 120000084 -+[ ]+128000088:[ ]+1fffc00c[ ]+pcaddu18i[ ]+\$t0, -512 -+[ ]+12800008c:[ ]+4ffffd80[ ]+jirl[ ]+\$zero, \$t0, -4 -+[ ]+128000090:[ ]+1e004001[ ]+pcaddu18i[ ]+\$ra, 512 -+[ ]+128000094:[ ]+4c000021[ ]+jirl[ ]+\$ra, \$ra, 0 -+[ ]+128000098:[ ]+57fff9ff[ ]+bl[ ]+134217720[ ]+# 130000090 -+[ ]+12800009c:[ ]+1e00400c[ ]+pcaddu18i[ ]+\$t0, 512 -+[ ]+1280000a0:[ ]+4c000180[ ]+jr[ ]+\$t0 -+[ ]+1280000a4:[ ]+53fff9ff[ ]+b[ ]+134217720[ ]+# 13000009c -+[ ]+... -+[ ]+130000070:[ ]+4c000020[ ]+ret -+[ ]+130000074:[ ]+4c000020[ ]+ret -+[ ]+130000078:[ ]+4c000020[ ]+ret -+[ ]+13000007c:[ ]+4c000020[ ]+ret -+[ ]+130000080:[ ]+4c000020[ ]+ret -+[ ]+130000084:[ ]+4c000020[ ]+ret -+[ ]+130000088:[ ]+4c000020[ ]+ret -+[ ]+13000008c:[ ]+4c000020[ ]+ret -+[ ]*0000000130000090 : -+[ ]+130000090:[ ]+4c000020[ ]+ret -+[ ]+130000094:[ ]+4c000020[ ]+ret -+[ ]+130000098:[ ]+4c000020[ ]+ret -+[ ]*000000013000009c : -+[ ]+13000009c:[ ]+4c000020[ ]+ret -diff --git a/ld/testsuite/ld-loongarch-elf/relax-medium-call-1.s b/ld/testsuite/ld-loongarch-elf/relax-medium-call-1.s -index 5266fdab..1770ec9f 100644 ---- a/ld/testsuite/ld-loongarch-elf/relax-medium-call-1.s -+++ b/ld/testsuite/ld-loongarch-elf/relax-medium-call-1.s -@@ -1,12 +1,12 @@ --.section "ta", "ax" -+.text - a: - ret - ret - ret - b: - ret -+ .fill 0x7fffff0 - --.text - pcaddu18i $ra, %call36(a) # min offset, can relax - jirl $ra, $ra, 0 - pcaddu18i $ra, %call36(a) # overflow, not relax -@@ -25,7 +25,7 @@ b: - pcaddu18i $t0, %call36(d) # max offset, can relax - jirl $zero, $t0, 0 - --.section "tb", "ax" -+ .fill 0x7ffffc8 - ret - ret - ret -diff --git a/ld/testsuite/ld-loongarch-elf/relax-medium-call.d b/ld/testsuite/ld-loongarch-elf/relax-medium-call.d -index c8ee9333..96e7bb09 100644 ---- a/ld/testsuite/ld-loongarch-elf/relax-medium-call.d -+++ b/ld/testsuite/ld-loongarch-elf/relax-medium-call.d -@@ -1,21 +1,42 @@ --#ld: -e0 -Ttext=0x120000000 --section-start=ta=0x118000000 --section-start=tb=0x127fffffc --#objdump: -d -j .text -+#ld: -e0 -+#objdump: -d - - .*:[ ]+file format .* - - - Disassembly of section .text: - --[ ]*0000000120000000 <__bss_start-0x4030>: --[ ]+120000000:[ ]+54000200[ ]+bl[ ]+-134217728[ ]+# 118000000 --[ ]+120000004:[ ]+1fffc001[ ]+pcaddu18i[ ]+\$ra, -512 --[ ]+120000008:[ ]+4ffffc21[ ]+jirl[ ]+\$ra, \$ra, -4 --[ ]+12000000c:[ ]+50000200[ ]+b[ ]+-134217728[ ]+# 11800000c --[ ]+120000010:[ ]+1fffc00c[ ]+pcaddu18i[ ]+\$t0, -512 --[ ]+120000014:[ ]+4ffffd80[ ]+jirl[ ]+\$zero, \$t0, -4 --[ ]+120000018:[ ]+1e004001[ ]+pcaddu18i[ ]+\$ra, 512 --[ ]+12000001c:[ ]+4c000421[ ]+jirl[ ]+\$ra, \$ra, 4 --[ ]+120000020:[ ]+57fffdff[ ]+bl[ ]+134217724[ ]+# 12800001c --[ ]+120000024:[ ]+1e00400c[ ]+pcaddu18i[ ]+\$t0, 512 --[ ]+120000028:[ ]+4c000580[ ]+jirl[ ]+\$zero, \$t0, 4 --[ ]+12000002c:[ ]+53fffdff[ ]+b[ ]+134217724[ ]+# 128000028 -+[ ]*0000000120000078 : -+[ ]+120000078:[ ]+4c000020[ ]+ret -+[ ]+12000007c:[ ]+4c000020[ ]+ret -+[ ]+120000080:[ ]+4c000020[ ]+ret -+[ ]*0000000120000084 : -+[ ]+120000084:[ ]+4c000020[ ]+ret -+[ ]+... -+[ ]+128000078:[ ]+54000200[ ]+bl[ ]+-134217728[ ]+# 120000078 -+[ ]+12800007c:[ ]+1fffc001[ ]+pcaddu18i[ ]+\$ra, -512 -+[ ]+128000080:[ ]+4ffffc21[ ]+jirl[ ]+\$ra, \$ra, -4 -+[ ]+128000084:[ ]+50000200[ ]+b[ ]+-134217728[ ]+# 120000084 -+[ ]+128000088:[ ]+1fffc00c[ ]+pcaddu18i[ ]+\$t0, -512 -+[ ]+12800008c:[ ]+4ffffd80[ ]+jirl[ ]+\$zero, \$t0, -4 -+[ ]+128000090:[ ]+1e004001[ ]+pcaddu18i[ ]+\$ra, 512 -+[ ]+128000094:[ ]+4c000021[ ]+jirl[ ]+\$ra, \$ra, 0 -+[ ]+128000098:[ ]+57fff9ff[ ]+bl[ ]+134217720[ ]+# 130000090 -+[ ]+12800009c:[ ]+1e00400c[ ]+pcaddu18i[ ]+\$t0, 512 -+[ ]+1280000a0:[ ]+4c000180[ ]+jr[ ]+\$t0 -+[ ]+1280000a4:[ ]+53fff9ff[ ]+b[ ]+134217720[ ]+# 13000009c -+[ ]+... -+[ ]+130000070:[ ]+4c000020[ ]+ret -+[ ]+130000074:[ ]+4c000020[ ]+ret -+[ ]+130000078:[ ]+4c000020[ ]+ret -+[ ]+13000007c:[ ]+4c000020[ ]+ret -+[ ]+130000080:[ ]+4c000020[ ]+ret -+[ ]+130000084:[ ]+4c000020[ ]+ret -+[ ]+130000088:[ ]+4c000020[ ]+ret -+[ ]+13000008c:[ ]+4c000020[ ]+ret -+[ ]*0000000130000090 : -+[ ]+130000090:[ ]+4c000020[ ]+ret -+[ ]+130000094:[ ]+4c000020[ ]+ret -+[ ]+130000098:[ ]+4c000020[ ]+ret -+[ ]*000000013000009c : -+[ ]+13000009c:[ ]+4c000020[ ]+ret -diff --git a/ld/testsuite/ld-loongarch-elf/relax-medium-call.s b/ld/testsuite/ld-loongarch-elf/relax-medium-call.s -index c0521b65..7b149620 100644 ---- a/ld/testsuite/ld-loongarch-elf/relax-medium-call.s -+++ b/ld/testsuite/ld-loongarch-elf/relax-medium-call.s -@@ -1,12 +1,12 @@ --.section "ta", "ax" -+.text - a: - ret - ret - ret - b: - ret -+ .fill 0x7fffff0 - --.text - call36 a # min offset, can relax - call36 a # overflow, not relax - tail36 $t0, b # min offset, can relax -@@ -17,7 +17,7 @@ b: - tail36 $t0, d # overflow, no relax - tail36 $t0, d # max offset, can relax - --.section "tb", "ax" -+ .fill 0x7ffffc8 - ret - ret - ret -diff --git a/ld/testsuite/ld-loongarch-elf/relax-separate-code-overflow.s b/ld/testsuite/ld-loongarch-elf/relax-separate-code-overflow.s -new file mode 100644 -index 00000000..df5dd5fe ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/relax-separate-code-overflow.s -@@ -0,0 +1,21 @@ -+# ld -z separate-code let .text and .rodata in two segment, -+# need to consider segment alignment -+.text -+ # first two la.local relax in the second trip, and result in the third -+ # la.local (relax to pcaddi) overflow -+ la.local $r12, a -+ la.local $r12, b -+ .fill 0x3ff8 -+ # relax in the first trip -+ la.local $r12, c -+ .fill 0x1fbfec -+a: -+ .fill 8 -+b: -+ .fill 0x1000 -+d: -+ .fill 0x1 -+ -+.section .rodata -+c: -+ .8byte 0x1 -diff --git a/ld/testsuite/ld-loongarch-elf/relax.exp b/ld/testsuite/ld-loongarch-elf/relax.exp -index c1da9c10..05c4ed0a 100644 ---- a/ld/testsuite/ld-loongarch-elf/relax.exp -+++ b/ld/testsuite/ld-loongarch-elf/relax.exp -@@ -308,6 +308,21 @@ if [istarget loongarch64-*-*] { - "relax-section-align-overflow" \ - ] \ - ] -+ -+ # # loongarch*-elf target do not support -z separate-code -+ if [check_shared_lib_support] { -+ run_ld_link_tests \ -+ [list \ -+ [list \ -+ "loongarch relax separate code overflow" \ -+ "-e0 -z separate-code" "" \ -+ "" \ -+ {relax-separate-code-overflow.s} \ -+ {} \ -+ "relax-separate-code-overflow" \ -+ ] \ -+ ] -+ } - } - - if [check_shared_lib_support] { --- -2.33.0 - diff --git a/LoongArch-Fix-relaxation-overflow-caused-by-section-.patch b/LoongArch-Fix-relaxation-overflow-caused-by-section-.patch deleted file mode 100644 index 477dd5b..0000000 --- a/LoongArch-Fix-relaxation-overflow-caused-by-section-.patch +++ /dev/null @@ -1,273 +0,0 @@ -From 9c12754717e9564ba5caa8220a87fa759f6e3f33 Mon Sep 17 00:00:00 2001 -From: mengqinggang -Date: Wed, 27 Dec 2023 11:12:30 +0800 -Subject: [PATCH 043/123] LoongArch: Fix relaxation overflow caused by section - alignment - -When deleting NOP instructions addend by .align at second pass, this may cause -the PC decrease but the symbol address to remain unchanged due to section -alignment. - -To solve this question, we subtract a maximux alignment of all sections like -RISC-V. ---- - bfd/elfnn-loongarch.c | 79 +++++++++++++------ - .../relax-section-align-overflow.s | 25 ++++++ - ld/testsuite/ld-loongarch-elf/relax.exp | 25 ++++-- - 3 files changed, 100 insertions(+), 29 deletions(-) - create mode 100644 ld/testsuite/ld-loongarch-elf/relax-section-align-overflow.s - -diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c -index 3d858169..8b71e836 100644 ---- a/bfd/elfnn-loongarch.c -+++ b/bfd/elfnn-loongarch.c -@@ -4188,8 +4188,9 @@ loongarch_relax_tls_le (bfd *abfd, asection *sec, - /* Relax pcalau12i,addi.d => pcaddi. */ - static bool - loongarch_relax_pcala_addi (bfd *abfd, asection *sec, asection *sym_sec, -- Elf_Internal_Rela *rel_hi, bfd_vma symval, -- struct bfd_link_info *info, bool *again) -+ Elf_Internal_Rela *rel_hi, bfd_vma symval, -+ struct bfd_link_info *info, bool *again, -+ bfd_vma max_alignment) - { - bfd_byte *contents = elf_section_data (sec)->this_hdr.contents; - Elf_Internal_Rela *rel_lo = rel_hi + 2; -@@ -4205,14 +4206,22 @@ loongarch_relax_pcala_addi (bfd *abfd, asection *sec, asection *sym_sec, - bfd_vma pc = sec_addr (sec) + rel_hi->r_offset; - - /* If pc and symbol not in the same segment, add/sub segment alignment. -- FIXME: if there are multiple readonly segments? */ -+ FIXME: if there are multiple readonly segments? How to determine if -+ two sections are in the same segment. */ - if (!(sym_sec->flags & SEC_READONLY)) - { -+ max_alignment = info->maxpagesize > max_alignment ? info->maxpagesize -+ : max_alignment; - if (symval > pc) -- pc -= info->maxpagesize; -+ pc -= max_alignment; - else if (symval < pc) -- pc += info->maxpagesize; -+ pc += max_alignment; - } -+ else -+ if (symval > pc) -+ pc -= max_alignment; -+ else if (symval < pc) -+ pc += max_alignment; - - const uint32_t addi_d = 0x02c00000; - const uint32_t pcaddi = 0x18000000; -@@ -4352,8 +4361,9 @@ loongarch_relax_align (bfd *abfd, asection *sec, - /* Relax pcalau12i + addi.d of TLS LD/GD/DESC to pcaddi. */ - static bool - loongarch_relax_tls_ld_gd_desc (bfd *abfd, asection *sec, asection *sym_sec, -- Elf_Internal_Rela *rel_hi, bfd_vma symval, -- struct bfd_link_info *info, bool *again) -+ Elf_Internal_Rela *rel_hi, bfd_vma symval, -+ struct bfd_link_info *info, bool *again, -+ bfd_vma max_alignment) - { - bfd_byte *contents = elf_section_data (sec)->this_hdr.contents; - Elf_Internal_Rela *rel_lo = rel_hi + 2; -@@ -4372,11 +4382,18 @@ loongarch_relax_tls_ld_gd_desc (bfd *abfd, asection *sec, asection *sym_sec, - FIXME: if there are multiple readonly segments? */ - if (!(sym_sec->flags & SEC_READONLY)) - { -+ max_alignment = info->maxpagesize > max_alignment ? info->maxpagesize -+ : max_alignment; - if (symval > pc) -- pc -= info->maxpagesize; -+ pc -= max_alignment; - else if (symval < pc) -- pc += info->maxpagesize; -+ pc += max_alignment; - } -+ else -+ if (symval > pc) -+ pc -= max_alignment; -+ else if (symval < pc) -+ pc += max_alignment; - - const uint32_t addi_d = 0x02c00000; - const uint32_t pcaddi = 0x18000000; -@@ -4428,6 +4445,21 @@ loongarch_relax_tls_ld_gd_desc (bfd *abfd, asection *sec, asection *sym_sec, - return true; - } - -+/* Traverse all output sections and return the max alignment. */ -+ -+static bfd_vma -+loongarch_get_max_alignment (asection *sec) -+{ -+ asection *o; -+ unsigned int max_alignment_power = 0; -+ -+ for (o = sec->output_section->owner->sections; o != NULL; o = o->next) -+ if (o->alignment_power > max_alignment_power) -+ max_alignment_power = o->alignment_power; -+ -+ return (bfd_vma) 1 << max_alignment_power; -+} -+ - static bool - loongarch_elf_relax_section (bfd *abfd, asection *sec, - struct bfd_link_info *info, -@@ -4438,6 +4470,7 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, - Elf_Internal_Shdr *symtab_hdr = &elf_symtab_hdr (abfd); - Elf_Internal_Rela *relocs; - *again = false; -+ bfd_vma max_alignment = 0; - - if (bfd_link_relocatable (info) - || sec->sec_flg0 -@@ -4470,6 +4503,15 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, - - data->relocs = relocs; - -+ /* Estimate the maximum alignment for all output sections once time -+ should be enough. */ -+ max_alignment = htab->max_alignment; -+ if (max_alignment == (bfd_vma) -1) -+ { -+ max_alignment = loongarch_get_max_alignment (sec); -+ htab->max_alignment = max_alignment; -+ } -+ - for (unsigned int i = 0; i < sec->reloc_count; i++) - { - char symtype; -@@ -4606,6 +4648,7 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, - if (1 == info->relax_pass) - loongarch_relax_align (abfd, sec, sym_sec, info, rel, symval); - break; -+ - case R_LARCH_DELETE: - if (1 == info->relax_pass) - { -@@ -4613,6 +4656,7 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, - rel->r_info = ELFNN_R_INFO (0, R_LARCH_NONE); - } - break; -+ - case R_LARCH_TLS_LE_HI20_R: - case R_LARCH_TLS_LE_LO12_R: - case R_LARCH_TLS_LE_ADD_R: -@@ -4623,34 +4667,25 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, - case R_LARCH_PCALA_HI20: - if (0 == info->relax_pass && (i + 4) <= sec->reloc_count) - loongarch_relax_pcala_addi (abfd, sec, sym_sec, rel, symval, -- info, again); -+ info, again, max_alignment); - break; -+ - case R_LARCH_GOT_PC_HI20: - if (local_got && 0 == info->relax_pass - && (i + 4) <= sec->reloc_count) - { - if (loongarch_relax_pcala_ld (abfd, sec, rel)) - loongarch_relax_pcala_addi (abfd, sec, sym_sec, rel, symval, -- info, again); -+ info, again, max_alignment); - } - break; - - case R_LARCH_TLS_LD_PC_HI20: -- if (0 == info->relax_pass && (i + 4) <= sec->reloc_count) -- loongarch_relax_tls_ld_gd_desc (abfd, sec, sym_sec, rel, symval, -- info, again); -- break; -- - case R_LARCH_TLS_GD_PC_HI20: -- if (0 == info->relax_pass && (i + 4) <= sec->reloc_count) -- loongarch_relax_tls_ld_gd_desc (abfd, sec, sym_sec, rel, symval, -- info, again); -- break; -- - case R_LARCH_TLS_DESC_PC_HI20: - if (0 == info->relax_pass && (i + 4) <= sec->reloc_count) - loongarch_relax_tls_ld_gd_desc (abfd, sec, sym_sec, rel, symval, -- info, again); -+ info, again, max_alignment); - break; - - default: -diff --git a/ld/testsuite/ld-loongarch-elf/relax-section-align-overflow.s b/ld/testsuite/ld-loongarch-elf/relax-section-align-overflow.s -new file mode 100644 -index 00000000..c341a8bb ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/relax-section-align-overflow.s -@@ -0,0 +1,25 @@ -+# relocation overflow because .align -+.text -+ addi.d $t0, $t1, 0 -+ addi.d $t0, $t1, 0 -+ # Add one NOP instruction -+ .align 3 -+ addi.d $t0, $t1, 0 -+ -+.section ".t.a", "ax" -+ addi.d $t0, $t1, 0 -+ # In one try: -+ # first pass, la.local can be relaxed (0x120200010 - 0x120000014 = 0x1ffffc) -+ # second pass, the NOP addend by .align be deleted and pc decrease 4, -+ # but .L1 not decrease because section alignment. -+ # (0x120200010 - 0x120000010 = 0x200000) -+ la.local $t0, .L1 -+ .fill 0x1ffff0 -+ -+.section ".t.b", "ax" -+.L1: -+ addi.d $t0, $t1, 0 -+ # To make section address not change when first .align 3 delete NOP -+ .align 4 -+ addi.d $t0, $t1, 0 -+ -diff --git a/ld/testsuite/ld-loongarch-elf/relax.exp b/ld/testsuite/ld-loongarch-elf/relax.exp -index aed8457d..107e5a56 100644 ---- a/ld/testsuite/ld-loongarch-elf/relax.exp -+++ b/ld/testsuite/ld-loongarch-elf/relax.exp -@@ -82,14 +82,14 @@ if [istarget loongarch64-*-*] { - ] - } - -- if [file exist "tmpdir/relax-so"] { -- set objdump_output [run_host_cmd "objdump" "-d tmpdir/relax-so"] -- if { [ regexp ".*pcaddi.*" $objdump_output] } { -- pass "loongarch relax .so" -- } { -- fail "loongarch relax .so" -- } -+ if [file exist "tmpdir/relax-so"] { -+ set objdump_output [run_host_cmd "objdump" "-d tmpdir/relax-so"] -+ if { [ regexp ".*pcaddi.*" $objdump_output] } { -+ pass "loongarch relax .so" -+ } { -+ fail "loongarch relax .so" - } -+ } - - run_ld_link_tests \ - [list \ -@@ -268,6 +268,17 @@ if [istarget loongarch64-*-*] { - ] - } - -+ run_ld_link_tests \ -+ [list \ -+ [list \ -+ "loongarch relax section align overflow" \ -+ "-e0 -Ttext 0x120000000" "" \ -+ "" \ -+ {relax-section-align-overflow.s} \ -+ {} \ -+ "relax-section-align-overflow" \ -+ ] \ -+ ] - } - - if [check_shared_lib_support] { --- -2.33.0 - diff --git a/LoongArch-Fix-some-macro-that-cannot-be-expanded-pro.patch b/LoongArch-Fix-some-macro-that-cannot-be-expanded-pro.patch deleted file mode 100644 index ace5190..0000000 --- a/LoongArch-Fix-some-macro-that-cannot-be-expanded-pro.patch +++ /dev/null @@ -1,390 +0,0 @@ -From 6ddd9c5a47335388ce3031313325b259a9f28773 Mon Sep 17 00:00:00 2001 -From: Lulu Cai -Date: Wed, 27 Dec 2023 19:42:01 +0800 -Subject: [PATCH 037/123] LoongArch: Fix some macro that cannot be expanded - properly - -Suppose we want to use la.got to generate 32 pcrel and -32 abs instruction sequences respectively. According to -the existing conditions, to generate 32 pcrel sequences -use -mabi=ilp32*, and to generate 32 abs use -mabi=ilp32* -and -mla-global-with-abs. - -Due to the fact that the conditions for generating 32 abs -also satisfy 32 pcrel, using -mabi=ilp32* and -mla-global-with-abs -will result in only generating instruction sequences of 32 pcrel. - -By modifying the conditions for macro expansion and adjusting -the matching order of macro instructions, it is ensured that -the correct sequence of instructions can be generated. ---- - .../gas/loongarch/macro_op_extreme_abs.d | 72 +++++++++++++++ - .../gas/loongarch/macro_op_extreme_abs.s | 9 ++ - ...o_op_large_abs.d => macro_op_extreme_pc.d} | 13 ++- - .../gas/loongarch/macro_op_extreme_pc.s | 9 ++ - .../gas/loongarch/macro_op_large_abs.s | 9 -- - .../gas/loongarch/macro_op_large_pc.d | 89 ------------------- - .../gas/loongarch/macro_op_large_pc.s | 9 -- - opcodes/loongarch-opc.c | 24 ++--- - 8 files changed, 108 insertions(+), 126 deletions(-) - create mode 100644 gas/testsuite/gas/loongarch/macro_op_extreme_abs.d - create mode 100644 gas/testsuite/gas/loongarch/macro_op_extreme_abs.s - rename gas/testsuite/gas/loongarch/{macro_op_large_abs.d => macro_op_extreme_pc.d} (93%) - create mode 100644 gas/testsuite/gas/loongarch/macro_op_extreme_pc.s - delete mode 100644 gas/testsuite/gas/loongarch/macro_op_large_abs.s - delete mode 100644 gas/testsuite/gas/loongarch/macro_op_large_pc.d - delete mode 100644 gas/testsuite/gas/loongarch/macro_op_large_pc.s - -diff --git a/gas/testsuite/gas/loongarch/macro_op_extreme_abs.d b/gas/testsuite/gas/loongarch/macro_op_extreme_abs.d -new file mode 100644 -index 00000000..5c823ba0 ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/macro_op_extreme_abs.d -@@ -0,0 +1,72 @@ -+#as: -mla-global-with-abs -mla-local-with-abs -+#objdump: -dr -+#skip: loongarch32-*-* -+ -+.*: file format .* -+ -+ -+Disassembly of section .text: -+ -+0+ <.L1>: -+ 0: 14000004 lu12i.w \$a0, 0 -+ 0: R_LARCH_MARK_LA \*ABS\* -+ 0: R_LARCH_ABS_HI20 .L1 -+ 4: 03800084 ori \$a0, \$a0, 0x0 -+ 4: R_LARCH_ABS_LO12 .L1 -+ 8: 16000004 lu32i.d \$a0, 0 -+ 8: R_LARCH_ABS64_LO20 .L1 -+ c: 03000084 lu52i.d \$a0, \$a0, 0 -+ c: R_LARCH_ABS64_HI12 .L1 -+ 10: 14000004 lu12i.w \$a0, 0 -+ 10: R_LARCH_MARK_LA \*ABS\* -+ 10: R_LARCH_ABS_HI20 .L1 -+ 14: 03800084 ori \$a0, \$a0, 0x0 -+ 14: R_LARCH_ABS_LO12 .L1 -+ 18: 16000004 lu32i.d \$a0, 0 -+ 18: R_LARCH_ABS64_LO20 .L1 -+ 1c: 03000084 lu52i.d \$a0, \$a0, 0 -+ 1c: R_LARCH_ABS64_HI12 .L1 -+ 20: 1a000004 pcalau12i \$a0, 0 -+ 20: R_LARCH_PCALA_HI20 .L1 -+ 20: R_LARCH_RELAX \*ABS\* -+ 24: 02c00084 addi.d \$a0, \$a0, 0 -+ 24: R_LARCH_PCALA_LO12 .L1 -+ 24: R_LARCH_RELAX \*ABS\* -+ 28: 14000004 lu12i.w \$a0, 0 -+ 28: R_LARCH_GOT_HI20 .L1 -+ 2c: 03800084 ori \$a0, \$a0, 0x0 -+ 2c: R_LARCH_GOT_LO12 .L1 -+ 30: 16000004 lu32i.d \$a0, 0 -+ 30: R_LARCH_GOT64_LO20 .L1 -+ 34: 03000084 lu52i.d \$a0, \$a0, 0 -+ 34: R_LARCH_GOT64_HI12 .L1 -+ 38: 28c00084 ld.d \$a0, \$a0, 0 -+ 3c: 14000004 lu12i.w \$a0, 0 -+ 3c: R_LARCH_TLS_LE_HI20 TLS1 -+ 40: 03800084 ori \$a0, \$a0, 0x0 -+ 40: R_LARCH_TLS_LE_LO12 TLS1 -+ 44: 14000004 lu12i.w \$a0, 0 -+ 44: R_LARCH_TLS_IE_HI20 TLS1 -+ 48: 03800084 ori \$a0, \$a0, 0x0 -+ 48: R_LARCH_TLS_IE_LO12 TLS1 -+ 4c: 16000004 lu32i.d \$a0, 0 -+ 4c: R_LARCH_TLS_IE64_LO20 TLS1 -+ 50: 03000084 lu52i.d \$a0, \$a0, 0 -+ 50: R_LARCH_TLS_IE64_HI12 TLS1 -+ 54: 28c00084 ld.d \$a0, \$a0, 0 -+ 58: 14000004 lu12i.w \$a0, 0 -+ 58: R_LARCH_TLS_LD_HI20 TLS1 -+ 5c: 03800084 ori \$a0, \$a0, 0x0 -+ 5c: R_LARCH_GOT_LO12 TLS1 -+ 60: 16000004 lu32i.d \$a0, 0 -+ 60: R_LARCH_GOT64_LO20 TLS1 -+ 64: 03000084 lu52i.d \$a0, \$a0, 0 -+ 64: R_LARCH_GOT64_HI12 TLS1 -+ 68: 14000004 lu12i.w \$a0, 0 -+ 68: R_LARCH_TLS_GD_HI20 TLS1 -+ 6c: 03800084 ori \$a0, \$a0, 0x0 -+ 6c: R_LARCH_GOT_LO12 TLS1 -+ 70: 16000004 lu32i.d \$a0, 0 -+ 70: R_LARCH_GOT64_LO20 TLS1 -+ 74: 03000084 lu52i.d \$a0, \$a0, 0 -+ 74: R_LARCH_GOT64_HI12 TLS1 -diff --git a/gas/testsuite/gas/loongarch/macro_op_extreme_abs.s b/gas/testsuite/gas/loongarch/macro_op_extreme_abs.s -new file mode 100644 -index 00000000..eca07006 ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/macro_op_extreme_abs.s -@@ -0,0 +1,9 @@ -+.L1: -+la.local $r4, $r5, .L1 -+la.global $r4, $r5, .L1 -+la.pcrel $r4, .L1 -+la.got $r4,.L1 -+la.tls.le $r4, TLS1 -+la.tls.ie $r4, TLS1 -+la.tls.ld $r4, TLS1 -+la.tls.gd $r4, TLS1 -diff --git a/gas/testsuite/gas/loongarch/macro_op_large_abs.d b/gas/testsuite/gas/loongarch/macro_op_extreme_pc.d -similarity index 93% -rename from gas/testsuite/gas/loongarch/macro_op_large_abs.d -rename to gas/testsuite/gas/loongarch/macro_op_extreme_pc.d -index 729e878f..8e4b6e6c 100644 ---- a/gas/testsuite/gas/loongarch/macro_op_large_abs.d -+++ b/gas/testsuite/gas/loongarch/macro_op_extreme_pc.d -@@ -1,10 +1,9 @@ --#as: -+#as: -mla-global-with-pcrel - #objdump: -dr - #skip: loongarch32-*-* - - .*: file format .* - -- - Disassembly of section .text: - - 0+ <.L1>: -@@ -20,16 +19,16 @@ Disassembly of section .text: - c: R_LARCH_PCALA64_HI12 .L1 - 10: 00109484 add.d \$a0, \$a0, \$a1 - 14: 1a000004 pcalau12i \$a0, 0 -- 14: R_LARCH_GOT_PC_HI20 .L1 -+ 14: R_LARCH_PCALA_HI20 .L1 - 14: R_LARCH_RELAX \*ABS\* - 18: 02c00005 li.d \$a1, 0 -- 18: R_LARCH_GOT_PC_LO12 .L1 -+ 18: R_LARCH_PCALA_LO12 .L1 - 18: R_LARCH_RELAX \*ABS\* - 1c: 16000005 lu32i.d \$a1, 0 -- 1c: R_LARCH_GOT64_PC_LO20 .L1 -+ 1c: R_LARCH_PCALA64_LO20 .L1 - 20: 030000a5 lu52i.d \$a1, \$a1, 0 -- 20: R_LARCH_GOT64_PC_HI12 .L1 -- 24: 380c1484 ldx.d \$a0, \$a0, \$a1 -+ 20: R_LARCH_PCALA64_HI12 .L1 -+ 24: 00109484 add.d \$a0, \$a0, \$a1 - 28: 1a000004 pcalau12i \$a0, 0 - 28: R_LARCH_PCALA_HI20 .L1 - 28: R_LARCH_RELAX \*ABS\* -diff --git a/gas/testsuite/gas/loongarch/macro_op_extreme_pc.s b/gas/testsuite/gas/loongarch/macro_op_extreme_pc.s -new file mode 100644 -index 00000000..4c685b5b ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/macro_op_extreme_pc.s -@@ -0,0 +1,9 @@ -+.L1: -+la.local $r4, $r5, .L1 -+la.global $r4, $r5, .L1 -+la.pcrel $r4, $r5, .L1 -+la.got $r4, $r5, .L1 -+la.tls.le $r4, TLS1 -+la.tls.ie $r4, $r5, TLS1 -+la.tls.ld $r4, $r5, TLS1 -+la.tls.gd $r4, $r5, TLS1 -diff --git a/gas/testsuite/gas/loongarch/macro_op_large_abs.s b/gas/testsuite/gas/loongarch/macro_op_large_abs.s -deleted file mode 100644 -index fd76391d..00000000 ---- a/gas/testsuite/gas/loongarch/macro_op_large_abs.s -+++ /dev/null -@@ -1,9 +0,0 @@ --.L1: --la.local $r4, $r5, .L1 --la.global $r4, $r5, .L1 --la.pcrel $r4, $r5, .L1 --la.got $r4, $r5, .L1 --la.tls.le $r4, TLS1 --la.tls.ie $r4, $r5, TLS1 --la.tls.ld $r4, $r5, TLS1 --la.tls.gd $r4, $r5, TLS1 -diff --git a/gas/testsuite/gas/loongarch/macro_op_large_pc.d b/gas/testsuite/gas/loongarch/macro_op_large_pc.d -deleted file mode 100644 -index 729e878f..00000000 ---- a/gas/testsuite/gas/loongarch/macro_op_large_pc.d -+++ /dev/null -@@ -1,89 +0,0 @@ --#as: --#objdump: -dr --#skip: loongarch32-*-* -- --.*: file format .* -- -- --Disassembly of section .text: -- --0+ <.L1>: -- 0: 1a000004 pcalau12i \$a0, 0 -- 0: R_LARCH_PCALA_HI20 .L1 -- 0: R_LARCH_RELAX \*ABS\* -- 4: 02c00005 li.d \$a1, 0 -- 4: R_LARCH_PCALA_LO12 .L1 -- 4: R_LARCH_RELAX \*ABS\* -- 8: 16000005 lu32i.d \$a1, 0 -- 8: R_LARCH_PCALA64_LO20 .L1 -- c: 030000a5 lu52i.d \$a1, \$a1, 0 -- c: R_LARCH_PCALA64_HI12 .L1 -- 10: 00109484 add.d \$a0, \$a0, \$a1 -- 14: 1a000004 pcalau12i \$a0, 0 -- 14: R_LARCH_GOT_PC_HI20 .L1 -- 14: R_LARCH_RELAX \*ABS\* -- 18: 02c00005 li.d \$a1, 0 -- 18: R_LARCH_GOT_PC_LO12 .L1 -- 18: R_LARCH_RELAX \*ABS\* -- 1c: 16000005 lu32i.d \$a1, 0 -- 1c: R_LARCH_GOT64_PC_LO20 .L1 -- 20: 030000a5 lu52i.d \$a1, \$a1, 0 -- 20: R_LARCH_GOT64_PC_HI12 .L1 -- 24: 380c1484 ldx.d \$a0, \$a0, \$a1 -- 28: 1a000004 pcalau12i \$a0, 0 -- 28: R_LARCH_PCALA_HI20 .L1 -- 28: R_LARCH_RELAX \*ABS\* -- 2c: 02c00005 li.d \$a1, 0 -- 2c: R_LARCH_PCALA_LO12 .L1 -- 2c: R_LARCH_RELAX \*ABS\* -- 30: 16000005 lu32i.d \$a1, 0 -- 30: R_LARCH_PCALA64_LO20 .L1 -- 34: 030000a5 lu52i.d \$a1, \$a1, 0 -- 34: R_LARCH_PCALA64_HI12 .L1 -- 38: 00109484 add.d \$a0, \$a0, \$a1 -- 3c: 1a000004 pcalau12i \$a0, 0 -- 3c: R_LARCH_GOT_PC_HI20 .L1 -- 3c: R_LARCH_RELAX \*ABS\* -- 40: 02c00005 li.d \$a1, 0 -- 40: R_LARCH_GOT_PC_LO12 .L1 -- 40: R_LARCH_RELAX \*ABS\* -- 44: 16000005 lu32i.d \$a1, 0 -- 44: R_LARCH_GOT64_PC_LO20 .L1 -- 48: 030000a5 lu52i.d \$a1, \$a1, 0 -- 48: R_LARCH_GOT64_PC_HI12 .L1 -- 4c: 380c1484 ldx.d \$a0, \$a0, \$a1 -- 50: 14000004 lu12i.w \$a0, 0 -- 50: R_LARCH_TLS_LE_HI20 TLS1 -- 54: 03800084 ori \$a0, \$a0, 0x0 -- 54: R_LARCH_TLS_LE_LO12 TLS1 -- 58: 1a000004 pcalau12i \$a0, 0 -- 58: R_LARCH_TLS_IE_PC_HI20 TLS1 -- 5c: 02c00005 li.d \$a1, 0 -- 5c: R_LARCH_TLS_IE_PC_LO12 TLS1 -- 60: 16000005 lu32i.d \$a1, 0 -- 60: R_LARCH_TLS_IE64_PC_LO20 TLS1 -- 64: 030000a5 lu52i.d \$a1, \$a1, 0 -- 64: R_LARCH_TLS_IE64_PC_HI12 TLS1 -- 68: 380c1484 ldx.d \$a0, \$a0, \$a1 -- 6c: 1a000004 pcalau12i \$a0, 0 -- 6c: R_LARCH_TLS_LD_PC_HI20 TLS1 -- 6c: R_LARCH_RELAX \*ABS\* -- 70: 02c00005 li.d \$a1, 0 -- 70: R_LARCH_GOT_PC_LO12 TLS1 -- 70: R_LARCH_RELAX \*ABS\* -- 74: 16000005 lu32i.d \$a1, 0 -- 74: R_LARCH_GOT64_PC_LO20 TLS1 -- 78: 030000a5 lu52i.d \$a1, \$a1, 0 -- 78: R_LARCH_GOT64_PC_HI12 TLS1 -- 7c: 00109484 add.d \$a0, \$a0, \$a1 -- 80: 1a000004 pcalau12i \$a0, 0 -- 80: R_LARCH_TLS_GD_PC_HI20 TLS1 -- 80: R_LARCH_RELAX \*ABS\* -- 84: 02c00005 li.d \$a1, 0 -- 84: R_LARCH_GOT_PC_LO12 TLS1 -- 84: R_LARCH_RELAX \*ABS\* -- 88: 16000005 lu32i.d \$a1, 0 -- 88: R_LARCH_GOT64_PC_LO20 TLS1 -- 8c: 030000a5 lu52i.d \$a1, \$a1, 0 -- 8c: R_LARCH_GOT64_PC_HI12 TLS1 -- 90: 00109484 add.d \$a0, \$a0, \$a1 -diff --git a/gas/testsuite/gas/loongarch/macro_op_large_pc.s b/gas/testsuite/gas/loongarch/macro_op_large_pc.s -deleted file mode 100644 -index fd76391d..00000000 ---- a/gas/testsuite/gas/loongarch/macro_op_large_pc.s -+++ /dev/null -@@ -1,9 +0,0 @@ --.L1: --la.local $r4, $r5, .L1 --la.global $r4, $r5, .L1 --la.pcrel $r4, $r5, .L1 --la.got $r4, $r5, .L1 --la.tls.le $r4, TLS1 --la.tls.ie $r4, $r5, TLS1 --la.tls.ld $r4, $r5, TLS1 --la.tls.gd $r4, $r5, TLS1 -diff --git a/opcodes/loongarch-opc.c b/opcodes/loongarch-opc.c -index 44b5f612..cc3d1986 100644 ---- a/opcodes/loongarch-opc.c -+++ b/opcodes/loongarch-opc.c -@@ -171,7 +171,7 @@ const char *const loongarch_x_normal_name[32] = - "lu32i.d %1,%%got64_lo20(%2);" \ - "lu52i.d %1,%1,%%got64_hi12(%2);" \ - "ld.d %1,%1,0", \ -- &LARCH_opts.ase_lp64, \ -+ &LARCH_opts.ase_gabs, \ - &LARCH_opts.ase_gpcr - /* got64 pic. */ - #define INSN_LA_GOT64_LARGE_PCREL \ -@@ -229,7 +229,7 @@ const char *const loongarch_x_normal_name[32] = - "lu32i.d %1,%%ie64_lo20(%2);" \ - "lu52i.d %1,%1,%%ie64_hi12(%2);" \ - "ld.d %1,%1,0", \ -- &LARCH_opts.ase_lp64, \ -+ &LARCH_opts.ase_gabs, \ - &LARCH_opts.ase_gpcr - - /* For LoongArch32/64 cmode=normal. */ -@@ -260,7 +260,7 @@ const char *const loongarch_x_normal_name[32] = - "ori %1,%1,%%got_lo12(%2);" \ - "lu32i.d %1,%%got64_lo20(%2);" \ - "lu52i.d %1,%1,%%got64_hi12(%2);", \ -- &LARCH_opts.ase_lp64, \ -+ &LARCH_opts.ase_gabs, \ - &LARCH_opts.ase_gpcr - - #define INSN_LA_TLS_GD32 \ -@@ -290,7 +290,7 @@ const char *const loongarch_x_normal_name[32] = - "ori %1,%1,%%got_lo12(%2);" \ - "lu32i.d %1,%%got64_lo20(%2);" \ - "lu52i.d %1,%1,%%got64_hi12(%2);", \ -- &LARCH_opts.ase_lp64, \ -+ &LARCH_opts.ase_gabs, \ - &LARCH_opts.ase_gpcr - - #define INSN_LA_CALL \ -@@ -376,27 +376,27 @@ static struct loongarch_opcode loongarch_macro_opcodes[] = - { 0, 0, "la.pcrel", "r,la", INSN_LA_PCREL32, 0 }, - { 0, 0, "la.pcrel", "r,la", INSN_LA_PCREL64, 0 }, - { 0, 0, "la.pcrel", "r,r,la", INSN_LA_PCREL64_LARGE, 0 }, -- { 0, 0, "la.got", "r,la", INSN_LA_GOT32, 0 }, - { 0, 0, "la.got", "r,la", INSN_LA_GOT32_ABS, 0 }, -- { 0, 0, "la.got", "r,la", INSN_LA_GOT64, 0 }, -+ { 0, 0, "la.got", "r,la", INSN_LA_GOT32, 0 }, - { 0, 0, "la.got", "r,la", INSN_LA_GOT64_LARGE_ABS, 0 }, -+ { 0, 0, "la.got", "r,la", INSN_LA_GOT64, 0 }, - { 0, 0, "la.got", "r,r,la", INSN_LA_GOT64_LARGE_PCREL, 0 }, - { 0, 0, "la.tls.le", "r,l", INSN_LA_TLS_LE, 0 }, - { 0, 0, "la.tls.le", "r,l", INSN_LA_TLS_LE64_LARGE, 0 }, -- { 0, 0, "la.tls.ie", "r,l", INSN_LA_TLS_IE32, 0 }, - { 0, 0, "la.tls.ie", "r,l", INSN_LA_TLS_IE32_ABS, 0 }, -- { 0, 0, "la.tls.ie", "r,l", INSN_LA_TLS_IE64, 0 }, -+ { 0, 0, "la.tls.ie", "r,l", INSN_LA_TLS_IE32, 0 }, - { 0, 0, "la.tls.ie", "r,l", INSN_LA_TLS_IE64_LARGE_ABS, 0 }, -+ { 0, 0, "la.tls.ie", "r,l", INSN_LA_TLS_IE64, 0 }, - { 0, 0, "la.tls.ie", "r,r,l", INSN_LA_TLS_IE64_LARGE_PCREL, 0 }, -- { 0, 0, "la.tls.ld", "r,l", INSN_LA_TLS_LD32, 0 }, - { 0, 0, "la.tls.ld", "r,l", INSN_LA_TLS_LD32_ABS, 0 }, -- { 0, 0, "la.tls.ld", "r,l", INSN_LA_TLS_LD64, 0 }, -+ { 0, 0, "la.tls.ld", "r,l", INSN_LA_TLS_LD32, 0 }, - { 0, 0, "la.tls.ld", "r,l", INSN_LA_TLS_LD64_LARGE_ABS, 0 }, -+ { 0, 0, "la.tls.ld", "r,l", INSN_LA_TLS_LD64, 0 }, - { 0, 0, "la.tls.ld", "r,r,l", INSN_LA_TLS_LD64_LARGE_PCREL, 0 }, -- { 0, 0, "la.tls.gd", "r,l", INSN_LA_TLS_GD32, 0 }, - { 0, 0, "la.tls.gd", "r,l", INSN_LA_TLS_GD32_ABS, 0 }, -- { 0, 0, "la.tls.gd", "r,l", INSN_LA_TLS_GD64, 0 }, -+ { 0, 0, "la.tls.gd", "r,l", INSN_LA_TLS_GD32, 0 }, - { 0, 0, "la.tls.gd", "r,l", INSN_LA_TLS_GD64_LARGE_ABS, 0 }, -+ { 0, 0, "la.tls.gd", "r,l", INSN_LA_TLS_GD64, 0 }, - { 0, 0, "la.tls.gd", "r,r,l", INSN_LA_TLS_GD64_LARGE_PCREL, 0 }, - { 0, 0, "call36", "la", INSN_LA_CALL, 0 }, - { 0, 0, "tail36", "r,la", INSN_LA_TAIL, 0 }, --- -2.33.0 - diff --git a/LoongArch-Fix-some-test-cases-for-TLS-transition-and.patch b/LoongArch-Fix-some-test-cases-for-TLS-transition-and.patch deleted file mode 100644 index f8aa7a9..0000000 --- a/LoongArch-Fix-some-test-cases-for-TLS-transition-and.patch +++ /dev/null @@ -1,997 +0,0 @@ -From 67ca2a7a3bd324aaef2d033de24384e64778d0d9 Mon Sep 17 00:00:00 2001 -From: Lulu Cai -Date: Thu, 25 Jan 2024 19:20:00 +0800 -Subject: [PATCH 071/123] LoongArch: Fix some test cases for TLS transition and - relax - ---- - gas/testsuite/gas/loongarch/macro_op.d | 4 + - gas/testsuite/gas/loongarch/macro_op_32.d | 4 + - .../gas/loongarch/macro_op_extreme_abs.d | 4 +- - .../gas/loongarch/macro_op_extreme_pc.d | 2 + - .../relax-cfi-fde-DW_CFA_advance_loc.d | 16 ++-- - .../relax-cfi-fde-DW_CFA_advance_loc.s | 8 ++ - gas/testsuite/gas/loongarch/reloc.d | 8 ++ - gas/testsuite/gas/loongarch/tlsdesc_32.d | 27 ------ - gas/testsuite/gas/loongarch/tlsdesc_32.s | 12 --- - gas/testsuite/gas/loongarch/tlsdesc_64.d | 2 + - ld/testsuite/ld-loongarch-elf/desc-ie.d | 14 ++- - ld/testsuite/ld-loongarch-elf/desc-ie.s | 13 +-- - .../ld-loongarch-elf/desc-le-norelax.d | 15 ++++ - .../ld-loongarch-elf/desc-le-norelax.s | 11 +++ - ld/testsuite/ld-loongarch-elf/desc-le-relax.d | 13 +++ - ld/testsuite/ld-loongarch-elf/desc-le-relax.s | 14 +++ - ld/testsuite/ld-loongarch-elf/desc-le.d | 15 ---- - ld/testsuite/ld-loongarch-elf/desc-le.s | 14 --- - ld/testsuite/ld-loongarch-elf/ie-le-norelax.d | 13 +++ - .../{ie-le.s => ie-le-norelax.s} | 4 +- - ld/testsuite/ld-loongarch-elf/ie-le-relax.d | 13 +++ - ld/testsuite/ld-loongarch-elf/ie-le-relax.s | 13 +++ - ld/testsuite/ld-loongarch-elf/ie-le.d | 13 --- - .../ld-loongarch-elf/ld-loongarch-elf.exp | 11 ++- - ld/testsuite/ld-loongarch-elf/macro_op.d | 4 + - ld/testsuite/ld-loongarch-elf/relax.exp | 6 +- - .../ld-loongarch-elf/tls-le-norelax.d | 18 ++++ - .../{tls-le.s => tls-le-norelax.s} | 4 + - ld/testsuite/ld-loongarch-elf/tls-le-relax.d | 13 +++ - ld/testsuite/ld-loongarch-elf/tls-le-relax.s | 22 +++++ - ld/testsuite/ld-loongarch-elf/tls-le.d | 14 --- - ld/testsuite/ld-loongarch-elf/tlsdesc-dso.d | 86 ++++++++++--------- - ld/testsuite/ld-loongarch-elf/tlsdesc-dso.s | 9 ++ - ld/testsuite/ld-loongarch-elf/tlsdesc_abs.d | 23 +++++ - ld/testsuite/ld-loongarch-elf/tlsdesc_abs.s | 7 ++ - .../ld-loongarch-elf/tlsdesc_extreme.d | 25 ++++++ - .../ld-loongarch-elf/tlsdesc_extreme.s | 7 ++ - 37 files changed, 333 insertions(+), 168 deletions(-) - delete mode 100644 gas/testsuite/gas/loongarch/tlsdesc_32.d - delete mode 100644 gas/testsuite/gas/loongarch/tlsdesc_32.s - create mode 100644 ld/testsuite/ld-loongarch-elf/desc-le-norelax.d - create mode 100644 ld/testsuite/ld-loongarch-elf/desc-le-norelax.s - create mode 100644 ld/testsuite/ld-loongarch-elf/desc-le-relax.d - create mode 100644 ld/testsuite/ld-loongarch-elf/desc-le-relax.s - delete mode 100644 ld/testsuite/ld-loongarch-elf/desc-le.d - delete mode 100644 ld/testsuite/ld-loongarch-elf/desc-le.s - create mode 100644 ld/testsuite/ld-loongarch-elf/ie-le-norelax.d - rename ld/testsuite/ld-loongarch-elf/{ie-le.s => ie-le-norelax.s} (63%) - create mode 100644 ld/testsuite/ld-loongarch-elf/ie-le-relax.d - create mode 100644 ld/testsuite/ld-loongarch-elf/ie-le-relax.s - delete mode 100644 ld/testsuite/ld-loongarch-elf/ie-le.d - create mode 100644 ld/testsuite/ld-loongarch-elf/tls-le-norelax.d - rename ld/testsuite/ld-loongarch-elf/{tls-le.s => tls-le-norelax.s} (70%) - create mode 100644 ld/testsuite/ld-loongarch-elf/tls-le-relax.d - create mode 100644 ld/testsuite/ld-loongarch-elf/tls-le-relax.s - delete mode 100644 ld/testsuite/ld-loongarch-elf/tls-le.d - create mode 100644 ld/testsuite/ld-loongarch-elf/tlsdesc_abs.d - create mode 100644 ld/testsuite/ld-loongarch-elf/tlsdesc_abs.s - create mode 100644 ld/testsuite/ld-loongarch-elf/tlsdesc_extreme.d - create mode 100644 ld/testsuite/ld-loongarch-elf/tlsdesc_extreme.s - -diff --git a/gas/testsuite/gas/loongarch/macro_op.d b/gas/testsuite/gas/loongarch/macro_op.d -index 47f8f45c..106f619e 100644 ---- a/gas/testsuite/gas/loongarch/macro_op.d -+++ b/gas/testsuite/gas/loongarch/macro_op.d -@@ -53,12 +53,16 @@ Disassembly of section .text: - 44: R_LARCH_RELAX \*ABS\* - 48: 14000004 lu12i.w \$a0, 0 - 48: R_LARCH_TLS_LE_HI20 TLS1 -+ 48: R_LARCH_RELAX \*ABS\* - 4c: 03800084 ori \$a0, \$a0, 0x0 - 4c: R_LARCH_TLS_LE_LO12 TLS1 -+ 4c: R_LARCH_RELAX \*ABS\* - 50: 1a000004 pcalau12i \$a0, 0 - 50: R_LARCH_TLS_IE_PC_HI20 TLS1 -+ 50: R_LARCH_RELAX \*ABS\* - 54: 28c00084 ld.d \$a0, \$a0, 0 - 54: R_LARCH_TLS_IE_PC_LO12 TLS1 -+ 54: R_LARCH_RELAX \*ABS\* - 58: 1a000004 pcalau12i \$a0, 0 - 58: R_LARCH_TLS_LD_PC_HI20 TLS1 - 58: R_LARCH_RELAX \*ABS\* -diff --git a/gas/testsuite/gas/loongarch/macro_op_32.d b/gas/testsuite/gas/loongarch/macro_op_32.d -index a7349aa8..8fd69922 100644 ---- a/gas/testsuite/gas/loongarch/macro_op_32.d -+++ b/gas/testsuite/gas/loongarch/macro_op_32.d -@@ -49,12 +49,16 @@ Disassembly of section .text: - 3c: R_LARCH_RELAX \*ABS\* - 40: 14000004 lu12i.w \$a0, 0 - 40: R_LARCH_TLS_LE_HI20 TLS1 -+ 40: R_LARCH_RELAX \*ABS\* - 44: 03800084 ori \$a0, \$a0, 0x0 - 44: R_LARCH_TLS_LE_LO12 TLS1 -+ 44: R_LARCH_RELAX \*ABS\* - 48: 1a000004 pcalau12i \$a0, 0 - 48: R_LARCH_TLS_IE_PC_HI20 TLS1 -+ 48: R_LARCH_RELAX \*ABS\* - 4c: 28800084 ld.w \$a0, \$a0, 0 - 4c: R_LARCH_TLS_IE_PC_LO12 TLS1 -+ 4c: R_LARCH_RELAX \*ABS\* - 50: 1a000004 pcalau12i \$a0, 0 - 50: R_LARCH_TLS_LD_PC_HI20 TLS1 - 50: R_LARCH_RELAX \*ABS\* -diff --git a/gas/testsuite/gas/loongarch/macro_op_extreme_abs.d b/gas/testsuite/gas/loongarch/macro_op_extreme_abs.d -index 5c823ba0..8e3a2aa9 100644 ---- a/gas/testsuite/gas/loongarch/macro_op_extreme_abs.d -+++ b/gas/testsuite/gas/loongarch/macro_op_extreme_abs.d -@@ -28,10 +28,8 @@ Disassembly of section .text: - 1c: R_LARCH_ABS64_HI12 .L1 - 20: 1a000004 pcalau12i \$a0, 0 - 20: R_LARCH_PCALA_HI20 .L1 -- 20: R_LARCH_RELAX \*ABS\* - 24: 02c00084 addi.d \$a0, \$a0, 0 - 24: R_LARCH_PCALA_LO12 .L1 -- 24: R_LARCH_RELAX \*ABS\* - 28: 14000004 lu12i.w \$a0, 0 - 28: R_LARCH_GOT_HI20 .L1 - 2c: 03800084 ori \$a0, \$a0, 0x0 -@@ -43,8 +41,10 @@ Disassembly of section .text: - 38: 28c00084 ld.d \$a0, \$a0, 0 - 3c: 14000004 lu12i.w \$a0, 0 - 3c: R_LARCH_TLS_LE_HI20 TLS1 -+ 3c: R_LARCH_RELAX \*ABS\* - 40: 03800084 ori \$a0, \$a0, 0x0 - 40: R_LARCH_TLS_LE_LO12 TLS1 -+ 40: R_LARCH_RELAX \*ABS\* - 44: 14000004 lu12i.w \$a0, 0 - 44: R_LARCH_TLS_IE_HI20 TLS1 - 48: 03800084 ori \$a0, \$a0, 0x0 -diff --git a/gas/testsuite/gas/loongarch/macro_op_extreme_pc.d b/gas/testsuite/gas/loongarch/macro_op_extreme_pc.d -index 68fbb338..21c5e5a0 100644 ---- a/gas/testsuite/gas/loongarch/macro_op_extreme_pc.d -+++ b/gas/testsuite/gas/loongarch/macro_op_extreme_pc.d -@@ -46,8 +46,10 @@ Disassembly of section .text: - [ ]+4c:[ ]+380c1484[ ]+ldx.d[ ]+\$a0, \$a0, \$a1 - [ ]+50:[ ]+14000004[ ]+lu12i.w[ ]+\$a0, 0 - [ ]+50: R_LARCH_TLS_LE_HI20[ ]+TLS1 -+[ ]+50: R_LARCH_RELAX[ ]+\*ABS\* - [ ]+54:[ ]+03800084[ ]+ori[ ]+\$a0, \$a0, 0x0 - [ ]+54: R_LARCH_TLS_LE_LO12[ ]+TLS1 -+[ ]+54: R_LARCH_RELAX[ ]+\*ABS\* - [ ]+58:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0 - [ ]+58: R_LARCH_TLS_IE_PC_HI20[ ]+TLS1 - [ ]+5c:[ ]+02c00005[ ]+li.d[ ]+\$a1, 0 -diff --git a/gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.d b/gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.d -index 367039e1..6b164cfb 100644 ---- a/gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.d -+++ b/gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.d -@@ -14,7 +14,7 @@ Disassembly of section .eh_frame: - [ ]+c:[ ]+01017c01[ ]+fadd.d[ ]+\$fa1, \$fa0, \$fs7 - [ ]+10:[ ]+0c030d1b[ ]+.word[ ]+[ ]+0x0c030d1b - [ ]+14:[ ]+00000016[ ]+.word[ ]+[ ]+0x00000016 --[ ]+18:[ ]+00000034[ ]+.word[ ]+[ ]+0x00000034 -+[ ]+18:[ ]+0000003c[ ]+.word[ ]+[ ]+0x0000003c - [ ]+1c:[ ]+0000001c[ ]+.word[ ]+[ ]+0x0000001c - [ ]+... - [ ]+20: R_LARCH_32_PCREL[ ]+L0\^A -@@ -26,7 +26,7 @@ Disassembly of section .eh_frame: - [ ]+2c:[ ]+d6400016[ ]+.word[ ]+[ ]+0xd6400016 - [ ]+2e: R_LARCH_ADD6[ ]+L0\^A - [ ]+2e: R_LARCH_SUB6[ ]+L0\^A --[ ]+30:[ ]+4000160c[ ]+beqz[ ]+\$t4, 3145748[ ]+# 300044 -+[ ]+30:[ ]+4000160c[ ]+beqz[ ]+\$t4, 3145748[ ]+# 300044 - [ ]+33: R_LARCH_ADD6[ ]+L0\^A - [ ]+33: R_LARCH_SUB6[ ]+L0\^A - [ ]+34:[ ]+00160cd6[ ]+orn[ ]+\$fp, \$a2, \$sp -@@ -39,8 +39,14 @@ Disassembly of section .eh_frame: - [ ]+40:[ ]+d6400016[ ]+.word[ ]+[ ]+0xd6400016 - [ ]+42: R_LARCH_ADD6[ ]+L0\^A - [ ]+42: R_LARCH_SUB6[ ]+L0\^A --[ ]+44:[ ]+4000160c[ ]+beqz[ ]+\$t4, 3145748[ ]+# 300058 -+[ ]+44:[ ]+4000160c[ ]+beqz[ ]+\$t4, 3145748[ ]+# 300058 - [ ]+47: R_LARCH_ADD6[ ]+L0\^A - [ ]+47: R_LARCH_SUB6[ ]+L0\^A --[ ]+48:[ ]+000000d6[ ]+.word[ ]+[ ]+0x000000d6 --[ ]+4c:[ ]+00000000[ ]+.word[ ]+[ ]+0x00000000 -+[ ]+48:[ ]+00160cd6[ ]+orn[ ]+\$fp, \$a2, \$sp -+[ ]+4c:[ ]+160cd640[ ]+lu32i.d[ ]+\$zero, 26290 -+[ ]+4c: R_LARCH_ADD6[ ]+L0\^A -+[ ]+4c: R_LARCH_SUB6[ ]+L0\^A -+[ ]+50:[ ]+00d64000[ ]+bstrpick.d[ ]+\$zero, \$zero, 0x16, 0x10 -+[ ]+51: R_LARCH_ADD6[ ]+L0\^A -+[ ]+51: R_LARCH_SUB6[ ]+L0\^A -+[ ]+54:[ ]+00000000[ ]+.word[ ]+[ ]+0x00000000 -diff --git a/gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.s b/gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.s -index 6e4c9b8b..2c67587b 100644 ---- a/gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.s -+++ b/gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.s -@@ -30,4 +30,12 @@ pcalau12i $t0, %le_hi20_r(a) - add.d $t0, $tp, $t0, %le_add_r(a) - .cfi_restore 22 - -+.cfi_def_cfa 22, 0 -+la.tls.ie $t0, a -+.cfi_restore 22 -+ -+.cfi_def_cfa 22, 0 -+la.tls.le $t0, a -+.cfi_restore 22 -+ - .cfi_endproc -diff --git a/gas/testsuite/gas/loongarch/reloc.d b/gas/testsuite/gas/loongarch/reloc.d -index fa249c58..6a8f0e1f 100644 ---- a/gas/testsuite/gas/loongarch/reloc.d -+++ b/gas/testsuite/gas/loongarch/reloc.d -@@ -81,12 +81,16 @@ Disassembly of section .text: - [ ]+8c:[ ]+R_LARCH_GOT64_HI12[ ]+.L1 - [ ]+90:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0 - [ ]+90:[ ]+R_LARCH_TLS_LE_HI20[ ]+TLSL1 -+[ ]+90:[ ]+R_LARCH_RELAX[ ]+\*ABS\* - [ ]+94:[ ]+03800085[ ]+ori[ ]+\$a1,[ ]+\$a0,[ ]+0x0 - [ ]+94:[ ]+R_LARCH_TLS_LE_LO12[ ]+TLSL1 -+[ ]+94:[ ]+R_LARCH_RELAX[ ]+\*ABS\* - [ ]+98:[ ]+16000004[ ]+lu32i.d[ ]+\$a0,[ ]+0 - [ ]+98:[ ]+R_LARCH_TLS_LE64_LO20[ ]+TLSL1 -+[ ]+98:[ ]+R_LARCH_RELAX[ ]+\*ABS\* - [ ]+9c:[ ]+03000085[ ]+lu52i.d[ ]+\$a1,[ ]+\$a0,[ ]+0 - [ ]+9c:[ ]+R_LARCH_TLS_LE64_HI12[ ]+TLSL1 -+[ ]+9c:[ ]+R_LARCH_RELAX[ ]+\*ABS\* - [ ]+a0:[ ]+58000085[ ]+beq[ ]+\$a0,[ ]+\$a1,[ ]+0[ ]+#[ ]+0xa0 - [ ]+a0:[ ]+R_LARCH_B16[ ]+.L1\+0x8 - [ ]+a4:[ ]+5c000085[ ]+bne[ ]+\$a0,[ ]+\$a1,[ ]+0[ ]+#[ ]+0xa4 -@@ -159,12 +163,16 @@ Disassembly of section .text: - [ ]+128:[ ]+R_LARCH_GOT64_HI12[ ]+.L1\+0x8 - [ ]+12c:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0 - [ ]+12c:[ ]+R_LARCH_TLS_LE_HI20[ ]+TLSL1\+0x8 -+[ ]+12c:[ ]+R_LARCH_RELAX[ ]+\*ABS\* - [ ]+130:[ ]+03800085[ ]+ori[ ]+\$a1,[ ]+\$a0,[ ]+0x0 - [ ]+130:[ ]+R_LARCH_TLS_LE_LO12[ ]+TLSL1\+0x8 -+[ ]+130:[ ]+R_LARCH_RELAX[ ]+\*ABS\* - [ ]+134:[ ]+16000004[ ]+lu32i.d[ ]+\$a0,[ ]+0 - [ ]+134:[ ]+R_LARCH_TLS_LE64_LO20[ ]+TLSL1\+0x8 -+[ ]+134:[ ]+R_LARCH_RELAX[ ]+\*ABS\* - [ ]+138:[ ]+03000085[ ]+lu52i.d[ ]+\$a1,[ ]+\$a0,[ ]+0 - [ ]+138:[ ]+R_LARCH_TLS_LE64_HI12[ ]+TLSL1\+0x8 -+[ ]+138:[ ]+R_LARCH_RELAX[ ]+\*ABS\* - [ ]+13c:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0 - [ ]+13c:[ ]+R_LARCH_TLS_LE_HI20_R[ ]+TLSL1 - [ ]+13c:[ ]+R_LARCH_RELAX[ ]+\*ABS\* -diff --git a/gas/testsuite/gas/loongarch/tlsdesc_32.d b/gas/testsuite/gas/loongarch/tlsdesc_32.d -deleted file mode 100644 -index eddcc5ed..00000000 ---- a/gas/testsuite/gas/loongarch/tlsdesc_32.d -+++ /dev/null -@@ -1,27 +0,0 @@ --#as: --#objdump: -dr --#skip: loongarch64-*-* -- --.*:[ ]+file format .* -- --Disassembly of section .text: -- --0+ <.*>: -- 0: 1a000004 pcalau12i \$a0, 0 -- 0: R_LARCH_TLS_DESC_PC_HI20 var -- 4: 02800084 addi.w \$a0, \$a0, 0 -- 4: R_LARCH_TLS_DESC_PC_LO12 var -- 8: 28800081 ld.w \$ra, \$a0, 0 -- 8: R_LARCH_TLS_DESC_LD var -- c: 4c000021 jirl \$ra, \$ra, 0 -- c: R_LARCH_TLS_DESC_CALL var -- 10: 1a000004 pcalau12i \$a0, 0 -- 10: R_LARCH_TLS_DESC_PC_HI20 var -- 10: R_LARCH_RELAX \*ABS\* -- 14: 02800084 addi.w \$a0, \$a0, 0 -- 14: R_LARCH_TLS_DESC_PC_LO12 var -- 14: R_LARCH_RELAX \*ABS\* -- 18: 28800081 ld.w \$ra, \$a0, 0 -- 18: R_LARCH_TLS_DESC_LD var -- 1c: 4c000021 jirl \$ra, \$ra, 0 -- 1c: R_LARCH_TLS_DESC_CALL var -diff --git a/gas/testsuite/gas/loongarch/tlsdesc_32.s b/gas/testsuite/gas/loongarch/tlsdesc_32.s -deleted file mode 100644 -index 2a139c04..00000000 ---- a/gas/testsuite/gas/loongarch/tlsdesc_32.s -+++ /dev/null -@@ -1,12 +0,0 @@ --.L1: -- # R_LARCH_TLS_DESC_PC_HI20 var -- pcalau12i $a0,%desc_pc_hi20(var) -- # R_LARCH_TLS_DESC_PC_LO12 var -- addi.w $a0,$a0,%desc_pc_lo12(var) -- # R_LARCH_TLS_DESC_LD var -- ld.w $ra,$a0,%desc_ld(var) -- # R_LARCH_TLS_DESC_CALL var -- jirl $ra,$ra,%desc_call(var) -- -- # test macro, pcalau12i + addi.w => pcaddi -- la.tls.desc $a0,var -diff --git a/gas/testsuite/gas/loongarch/tlsdesc_64.d b/gas/testsuite/gas/loongarch/tlsdesc_64.d -index 2a2829c9..8fc9e883 100644 ---- a/gas/testsuite/gas/loongarch/tlsdesc_64.d -+++ b/gas/testsuite/gas/loongarch/tlsdesc_64.d -@@ -24,5 +24,7 @@ Disassembly of section .text: - 14: R_LARCH_RELAX \*ABS\* - 18: 28c00081 ld.d \$ra, \$a0, 0 - 18: R_LARCH_TLS_DESC_LD var -+ 18: R_LARCH_RELAX \*ABS\* - 1c: 4c000021 jirl \$ra, \$ra, 0 - 1c: R_LARCH_TLS_DESC_CALL var -+ 1c: R_LARCH_RELAX \*ABS\* -diff --git a/ld/testsuite/ld-loongarch-elf/desc-ie.d b/ld/testsuite/ld-loongarch-elf/desc-ie.d -index 32e35050..e1f49e2d 100644 ---- a/ld/testsuite/ld-loongarch-elf/desc-ie.d -+++ b/ld/testsuite/ld-loongarch-elf/desc-ie.d -@@ -1,5 +1,5 @@ - #as: --#ld: -shared -z norelro -e 0x0 --hash-style=both -+#ld: -shared -z norelro --hash-style=both - #objdump: -dr - #skip: loongarch32-*-* - -@@ -7,10 +7,8 @@ - - Disassembly of section .text: - --0+230 : -- 230: 1a000084 pcalau12i \$a0, 4 -- 234: 28cd6084 ld.d \$a0, \$a0, 856 -- 238: 03400000 nop.* -- 23c: 03400000 nop.* -- 240: 1a000084 pcalau12i \$a0, 4 -- 244: 28cd6081 ld.d \$ra, \$a0, 856 -+[0-9a-f]+ : -+ +[0-9a-f]+: 1a000084 pcalau12i \$a0, .* -+ +[0-9a-f]+: 28cca084 ld.d \$a0, \$a0, .* -+ +[0-9a-f]+: 1a000084 pcalau12i \$a0, .* -+ +[0-9a-f]+: 28cca084 ld.d \$a0, \$a0, .* -diff --git a/ld/testsuite/ld-loongarch-elf/desc-ie.s b/ld/testsuite/ld-loongarch-elf/desc-ie.s -index 7f5772bc..441080b6 100644 ---- a/ld/testsuite/ld-loongarch-elf/desc-ie.s -+++ b/ld/testsuite/ld-loongarch-elf/desc-ie.s -@@ -1,6 +1,6 @@ -- .global v1 -+ .global var - .section .tdata,"awT",@progbits --v1: -+var: - .word 1 - .text - .global fn1 -@@ -9,10 +9,5 @@ fn1: - - # Use DESC and IE to access the same symbol, - # DESC will relax to IE. -- pcalau12i $a0,%desc_pc_hi20(var) -- addi.d $a0,$a0,%desc_pc_lo12(var) -- ld.d $ra,$a0,%desc_ld(var) -- jirl $ra,$ra,%desc_call(var) -- -- pcalau12i $a0,%ie_pc_hi20(var) -- ld.d $ra,$a0,%ie_pc_lo12(var) -+ la.tls.ie $a0,var -+ la.tls.desc $a0,var -diff --git a/ld/testsuite/ld-loongarch-elf/desc-le-norelax.d b/ld/testsuite/ld-loongarch-elf/desc-le-norelax.d -new file mode 100644 -index 00000000..5a53245a ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/desc-le-norelax.d -@@ -0,0 +1,15 @@ -+#as: -+#ld: -z norelro -e0 --no-relax -+#objdump: -dr -+#skip: loongarch32-*-* -+ -+.*: file format .* -+ -+ -+Disassembly of section .text: -+ -+[0-9a-f]+ : -+ +[0-9a-f]+: 14000004 lu12i.w \$a0, .* -+ +[0-9a-f]+: 03800084 ori \$a0, \$a0, .* -+ +[0-9a-f]+: 03400000 nop -+ +[0-9a-f]+: 03400000 nop -diff --git a/ld/testsuite/ld-loongarch-elf/desc-le-norelax.s b/ld/testsuite/ld-loongarch-elf/desc-le-norelax.s -new file mode 100644 -index 00000000..c91f15de ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/desc-le-norelax.s -@@ -0,0 +1,11 @@ -+ .global var -+ .section .tdata,"awT",@progbits -+var: -+ .word 1 -+ .text -+ .global fn1 -+ .type fn1,@function -+fn1: -+ -+ # DESC will relax to LE. -+ la.tls.desc $a0,var -diff --git a/ld/testsuite/ld-loongarch-elf/desc-le-relax.d b/ld/testsuite/ld-loongarch-elf/desc-le-relax.d -new file mode 100644 -index 00000000..03b5535e ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/desc-le-relax.d -@@ -0,0 +1,13 @@ -+#as: -+#ld: -z norelro -e0 -+#objdump: -dr -M no-aliases -+#skip: loongarch32-*-* -+ -+.*: file format .* -+ -+ -+Disassembly of section .text: -+ -+[0-9a-f]+ : -+ +[0-9a-f]+: 03800004 ori \$a0, \$zero, 0x0 -+ +[0-9a-f]+: 03801004 ori \$a0, \$zero, 0x4 -diff --git a/ld/testsuite/ld-loongarch-elf/desc-le-relax.s b/ld/testsuite/ld-loongarch-elf/desc-le-relax.s -new file mode 100644 -index 00000000..d590299d ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/desc-le-relax.s -@@ -0,0 +1,14 @@ -+ .global var -+ .section .tdata,"awT",@progbits -+var1: -+ .word 1 -+var2: -+ .word 1 -+ .text -+ .global fn1 -+ .type fn1,@function -+fn1: -+ -+ # DESC will relax to LE. -+ la.tls.desc $a0,var1 -+ la.tls.desc $a0,var2 -diff --git a/ld/testsuite/ld-loongarch-elf/desc-le.d b/ld/testsuite/ld-loongarch-elf/desc-le.d -deleted file mode 100644 -index b4ca9f82..00000000 ---- a/ld/testsuite/ld-loongarch-elf/desc-le.d -+++ /dev/null -@@ -1,15 +0,0 @@ --#as: --#ld: -z norelro -e 0x0 --#objdump: -dr --#skip: loongarch32-*-* -- --.*: file format .* -- -- --Disassembly of section .text: -- --0+1200000e8 : -- 1200000e8: 14000004 lu12i.w \$a0, 0 -- 1200000ec: 03800084 ori \$a0, \$a0, 0x0 -- 1200000f0: 03400000 nop.* -- 1200000f4: 03400000 nop.* -diff --git a/ld/testsuite/ld-loongarch-elf/desc-le.s b/ld/testsuite/ld-loongarch-elf/desc-le.s -deleted file mode 100644 -index 9ffaa2d6..00000000 ---- a/ld/testsuite/ld-loongarch-elf/desc-le.s -+++ /dev/null -@@ -1,14 +0,0 @@ -- .global var -- .section .tdata,"awT",@progbits --var: -- .word 1 -- .text -- .global fn1 -- .type fn1,@function --fn1: -- -- # DESC will relax to LE. -- pcalau12i $a0,%desc_pc_hi20(var) -- addi.d $a0,$a0,%desc_pc_lo12(var) -- ld.d $ra,$a0,%desc_ld(var) -- jirl $ra,$ra,%desc_call(var) -diff --git a/ld/testsuite/ld-loongarch-elf/ie-le-norelax.d b/ld/testsuite/ld-loongarch-elf/ie-le-norelax.d -new file mode 100644 -index 00000000..81d78ca3 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/ie-le-norelax.d -@@ -0,0 +1,13 @@ -+#as: -+#ld: -z norelro -e0 --no-relax -+#objdump: -dr -+#skip: loongarch32-*-* -+ -+.*: file format .* -+ -+ -+Disassembly of section .text: -+ -+[0-9a-f]+ <.*>: -+ +[0-9a-f]+: 14000024 lu12i.w \$a0, .* -+ +[0-9a-f]+: 03800084 ori \$a0, \$a0, .* -diff --git a/ld/testsuite/ld-loongarch-elf/ie-le.s b/ld/testsuite/ld-loongarch-elf/ie-le-norelax.s -similarity index 63% -rename from ld/testsuite/ld-loongarch-elf/ie-le.s -rename to ld/testsuite/ld-loongarch-elf/ie-le-norelax.s -index 795c7ce4..db87a2d3 100644 ---- a/ld/testsuite/ld-loongarch-elf/ie-le.s -+++ b/ld/testsuite/ld-loongarch-elf/ie-le-norelax.s -@@ -1,5 +1,6 @@ - .data - .section .tdata,"awT",@progbits -+ .fill 0x1000,1,0 - var: - .word 1 - .text -@@ -7,5 +8,4 @@ var: - .type gn1,@function - fn1: - # expect IE to relax LE. -- pcalau12i $a0,%ie_pc_hi20(var) -- ld.d $a0,$a0,%ie_pc_lo12(var) -+ la.tls.ie $a0,var -diff --git a/ld/testsuite/ld-loongarch-elf/ie-le-relax.d b/ld/testsuite/ld-loongarch-elf/ie-le-relax.d -new file mode 100644 -index 00000000..03b5535e ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/ie-le-relax.d -@@ -0,0 +1,13 @@ -+#as: -+#ld: -z norelro -e0 -+#objdump: -dr -M no-aliases -+#skip: loongarch32-*-* -+ -+.*: file format .* -+ -+ -+Disassembly of section .text: -+ -+[0-9a-f]+ : -+ +[0-9a-f]+: 03800004 ori \$a0, \$zero, 0x0 -+ +[0-9a-f]+: 03801004 ori \$a0, \$zero, 0x4 -diff --git a/ld/testsuite/ld-loongarch-elf/ie-le-relax.s b/ld/testsuite/ld-loongarch-elf/ie-le-relax.s -new file mode 100644 -index 00000000..08bc3987 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/ie-le-relax.s -@@ -0,0 +1,13 @@ -+ .data -+ .section .tdata,"awT",@progbits -+var1: -+ .word 1 -+var2: -+ .word 2 -+ .text -+ .global fn1 -+ .type gn1,@function -+fn1: -+ # expect IE to relax LE -+ la.tls.ie $a0,var1 -+ la.tls.ie $a0,var2 -diff --git a/ld/testsuite/ld-loongarch-elf/ie-le.d b/ld/testsuite/ld-loongarch-elf/ie-le.d -deleted file mode 100644 -index 42694d7f..00000000 ---- a/ld/testsuite/ld-loongarch-elf/ie-le.d -+++ /dev/null -@@ -1,13 +0,0 @@ --#as: --#ld: -z norelro -e 0x0 --#objdump: -dr --#skip: loongarch32-*-* -- --.*: file format .* -- -- --Disassembly of section .text: -- --0+1200000e8 : -- 1200000e8: 14000004 lu12i.w \$a0, 0 -- 1200000ec: 03800084 ori \$a0, \$a0, 0x0 -diff --git a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -index 7dca8218..ca428f5b 100644 ---- a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -+++ b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -@@ -34,7 +34,6 @@ if [istarget "loongarch64-*-*"] { - run_dump_test "local-ifunc-reloc" - run_dump_test "anno-sym" - run_dump_test "pcala64" -- run_dump_test "tls-le" - run_dump_test "overflow_s_10_5" - run_dump_test "overflow_s_10_12" - run_dump_test "overflow_s_10_16" -@@ -51,6 +50,8 @@ if [istarget "loongarch64-*-*"] { - run_dump_test "underflow_s_0_5_10_16_s2" - run_dump_test "underflow_s_0_10_10_16_s2" - run_dump_test "underflow_s_5_20" -+ run_dump_test "tls-le-norelax" -+ run_dump_test "tls-le-relax" - } - - if [istarget "loongarch32-*-*"] { -@@ -127,8 +128,6 @@ if [istarget "loongarch64-*-*"] { - if [istarget "loongarch64-*-*"] { - if [check_shared_lib_support] { - run_dump_test "desc-ie" -- run_dump_test "desc-le" -- run_dump_test "ie-le" - run_dump_test "tlsdesc-dso" - run_dump_test "desc-norelax" - run_dump_test "desc-relax" -@@ -147,5 +146,11 @@ if [istarget "loongarch64-*-*"] { - run_dump_test "underflow_b26" - run_dump_test "underflow_pcrel20" - run_dump_test "pie_discard" -+ run_dump_test "desc-le-norelax" -+ run_dump_test "desc-le-relax" -+ run_dump_test "ie-le-norelax" -+ run_dump_test "ie-le-relax" -+ run_dump_test "tlsdesc_abs" -+ run_dump_test "tlsdesc_extreme" - } - -diff --git a/ld/testsuite/ld-loongarch-elf/macro_op.d b/ld/testsuite/ld-loongarch-elf/macro_op.d -index c9493918..6a886224 100644 ---- a/ld/testsuite/ld-loongarch-elf/macro_op.d -+++ b/ld/testsuite/ld-loongarch-elf/macro_op.d -@@ -140,12 +140,16 @@ Disassembly of section .text: - [ ]+f0:[ ]+380c1484[ ]+ldx.d[ ]+\$a0, \$a0, \$a1 - [ ]+f4:[ ]+14000004[ ]+lu12i.w[ ]+\$a0, 0 - [ ]+f4: R_LARCH_TLS_LE_HI20[ ]+TLS1 -+[ ]+f4: R_LARCH_RELAX[ ]+\*ABS\* - [ ]+f8:[ ]+03800084[ ]+ori[ ]+\$a0, \$a0, 0x0 - [ ]+f8: R_LARCH_TLS_LE_LO12[ ]+TLS1 -+[ ]+f8: R_LARCH_RELAX[ ]+\*ABS\* - [ ]+fc:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0 - [ ]+fc: R_LARCH_TLS_IE_PC_HI20[ ]+TLS1 -+[ ]+fc: R_LARCH_RELAX[ ]+\*ABS\* - [ ]+100:[ ]+28c00084[ ]+ld.d[ ]+\$a0, \$a0, 0 - [ ]+100: R_LARCH_TLS_IE_PC_LO12[ ]+TLS1 -+[ ]+100: R_LARCH_RELAX[ ]+\*ABS\* - [ ]+104:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0 - [ ]+104: R_LARCH_TLS_IE_PC_HI20[ ]+TLS1 - [ ]+108:[ ]+02c00005[ ]+li.d[ ]+\$a1, 0 -diff --git a/ld/testsuite/ld-loongarch-elf/relax.exp b/ld/testsuite/ld-loongarch-elf/relax.exp -index c537976a..bca3e1bd 100644 ---- a/ld/testsuite/ld-loongarch-elf/relax.exp -+++ b/ld/testsuite/ld-loongarch-elf/relax.exp -@@ -137,7 +137,7 @@ if [istarget loongarch64-*-*] { - [list \ - [list \ - "loongarch old tls le .exe build" \ -- "" "" \ -+ "--no-relax" "" \ - "" \ - {old-tls-le.s} \ - {} \ -@@ -158,7 +158,7 @@ if [istarget loongarch64-*-*] { - [list \ - [list \ - "loongarch tls le realx compatible .exe build" \ -- "" "" \ -+ "--no-relax" "" \ - "" \ - {tls-relax-compatible-check-new.s tls-relax-compatible-check-old.s} \ - {} \ -@@ -201,7 +201,7 @@ if [istarget loongarch64-*-*] { - [list \ - [list \ - "loongarch tls le realx bound-check .exe build" \ -- "" "" \ -+ "--no-relax" "" \ - "" \ - {relax-bound-check-tls-le.s} \ - {} \ -diff --git a/ld/testsuite/ld-loongarch-elf/tls-le-norelax.d b/ld/testsuite/ld-loongarch-elf/tls-le-norelax.d -new file mode 100644 -index 00000000..a53d8123 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/tls-le-norelax.d -@@ -0,0 +1,18 @@ -+#ld: --no-relax -+#objdump: -d -M no-aliases -+ -+.*:[ ]+file format .* -+ -+ -+Disassembly of section .text: -+ -+[0-9a-f]+ <_start>: -+ +[0-9a-f]+: 14000004 lu12i.w \$a0, 0 -+ +[0-9a-f]+: 03802085 ori \$a1, \$a0, 0x8 -+ +[0-9a-f]+: 14000004 lu12i.w \$a0, 0 -+ +[0-9a-f]+: 02c02085 addi.d \$a1, \$a0, 8 -+ +[0-9a-f]+: 14000004 lu12i.w \$a0, 0 -+ +[0-9a-f]+: 03802084 ori \$a0, \$a0, 0x8 -+ +[0-9a-f]+: 16000004 lu32i.d \$a0, 0 -+ +[0-9a-f]+: 03000084 lu52i.d \$a0, \$a0, 0 -+ +[0-9a-f]+: 4c000020 jirl \$zero, \$ra, 0 -diff --git a/ld/testsuite/ld-loongarch-elf/tls-le.s b/ld/testsuite/ld-loongarch-elf/tls-le-norelax.s -similarity index 70% -rename from ld/testsuite/ld-loongarch-elf/tls-le.s -rename to ld/testsuite/ld-loongarch-elf/tls-le-norelax.s -index 2e6a9de4..80f87920 100644 ---- a/ld/testsuite/ld-loongarch-elf/tls-le.s -+++ b/ld/testsuite/ld-loongarch-elf/tls-le-norelax.s -@@ -15,4 +15,8 @@ _start: - ori $r5,$r4,%le_lo12(a + 0x8) - lu12i.w $r4,%le_hi20_r(a + 0x8) - addi.d $r5,$r4,%le_lo12_r(a + 0x8) -+ lu12i.w $r4,%le_hi20(a + 0x8) -+ ori $r4,$r4,%le_lo12(a + 0x8) -+ lu32i.d $r4,%le64_lo20(a + 0x8) -+ lu52i.d $r4,$r4,%le64_hi12(a + 0x8) - jr $ra -diff --git a/ld/testsuite/ld-loongarch-elf/tls-le-relax.d b/ld/testsuite/ld-loongarch-elf/tls-le-relax.d -new file mode 100644 -index 00000000..19e101c8 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/tls-le-relax.d -@@ -0,0 +1,13 @@ -+#ld: -+#objdump: -d -M no-aliases -+ -+.*:[ ]+file format .* -+ -+ -+Disassembly of section .text: -+ -+[0-9a-f]+ <_start>: -+ +[0-9a-f]+: 03802005 ori \$a1, \$zero, 0x8 -+ +[0-9a-f]+: 02c02045 addi.d \$a1, \$tp, 8 -+ +[0-9a-f]+: 03802004 ori \$a0, \$zero, 0x8 -+ +[0-9a-f]+: 4c000020 jirl \$zero, \$ra, 0 -diff --git a/ld/testsuite/ld-loongarch-elf/tls-le-relax.s b/ld/testsuite/ld-loongarch-elf/tls-le-relax.s -new file mode 100644 -index 00000000..80f87920 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/tls-le-relax.s -@@ -0,0 +1,22 @@ -+# Support for TLS LE symbols with addend -+ .text -+ .globl a -+ .section .tdata,"awT",@progbits -+ .align 2 -+ .type a, @object -+ .size a, 4 -+a: -+ .word 123 -+ -+ .text -+ .global _start -+_start: -+ lu12i.w $r4,%le_hi20(a + 0x8) -+ ori $r5,$r4,%le_lo12(a + 0x8) -+ lu12i.w $r4,%le_hi20_r(a + 0x8) -+ addi.d $r5,$r4,%le_lo12_r(a + 0x8) -+ lu12i.w $r4,%le_hi20(a + 0x8) -+ ori $r4,$r4,%le_lo12(a + 0x8) -+ lu32i.d $r4,%le64_lo20(a + 0x8) -+ lu52i.d $r4,$r4,%le64_hi12(a + 0x8) -+ jr $ra -diff --git a/ld/testsuite/ld-loongarch-elf/tls-le.d b/ld/testsuite/ld-loongarch-elf/tls-le.d -deleted file mode 100644 -index cbd6adb8..00000000 ---- a/ld/testsuite/ld-loongarch-elf/tls-le.d -+++ /dev/null -@@ -1,14 +0,0 @@ --#ld: --no-relax --#objdump: -d -- --.*:[ ]+file format .* -- -- --Disassembly of section .text: -- --[ ]*00000001200000e8 <_start>: --[ ]+1200000e8:[ ]+14000004[ ]+lu12i.w[ ]+\$a0, 0 --[ ]+1200000ec:[ ]+03802085[ ]+ori[ ]+\$a1, \$a0, 0x8 --[ ]+1200000f0:[ ]+14000004[ ]+lu12i.w[ ]+\$a0, 0 --[ ]+1200000f4:[ ]+02c02085[ ]+addi.d[ ]+\$a1, \$a0, 8 --[ ]+1200000f8:[ ]+4c000020[ ]+ret -diff --git a/ld/testsuite/ld-loongarch-elf/tlsdesc-dso.d b/ld/testsuite/ld-loongarch-elf/tlsdesc-dso.d -index 453902d1..84ea97e0 100644 ---- a/ld/testsuite/ld-loongarch-elf/tlsdesc-dso.d -+++ b/ld/testsuite/ld-loongarch-elf/tlsdesc-dso.d -@@ -8,49 +8,53 @@ - - Disassembly of section .text: - --0+418 : -- 418: 180214c4 pcaddi \$a0, 4262 -- 41c: 1a000084 pcalau12i \$a0, 4 -- 420: 28db0084 ld.d \$a0, \$a0, 1728 -- 424: 180212a4 pcaddi \$a0, 4245 -- 428: 18021304 pcaddi \$a0, 4248 -- 42c: 28c00081 ld.d \$ra, \$a0, 0 -- 430: 4c000021 jirl \$ra, \$ra, 0 -- 434: 1a000084 pcalau12i \$a0, 4 -- 438: 28d9c084 ld.d \$a0, \$a0, 1648 -- 43c: 03400000 nop.* -- 440: 03400000 nop.* -- 444: 1a000084 pcalau12i \$a0, 4 -- 448: 28d9c084 ld.d \$a0, \$a0, 1648 -- 44c: 18021264 pcaddi \$a0, 4243 -- 450: 18021244 pcaddi \$a0, 4242 -- 454: 28c00081 ld.d \$ra, \$a0, 0 -- 458: 4c000021 jirl \$ra, \$ra, 0 -- 45c: 1a000084 pcalau12i \$a0, 4 -- 460: 28daa084 ld.d \$a0, \$a0, 1704 -- --0+464 : -+0+448 : -+ 448: 18021584 pcaddi \$a0, 4268 -+ 44c: 1a000084 pcalau12i \$a0, 4 -+ 450: 28dc2084 ld.d \$a0, \$a0, 1800 -+ 454: 18021364 pcaddi \$a0, 4251 -+ 458: 180213c4 pcaddi \$a0, 4254 -+ 45c: 28c00081 ld.d \$ra, \$a0, 0 -+ 460: 4c000021 jirl \$ra, \$ra, 0 - 464: 1a000084 pcalau12i \$a0, 4 -- 468: 28d86084 ld.d \$a0, \$a0, 1560 -- 46c: 18020ce4 pcaddi \$a0, 4199 -- 470: 18020e04 pcaddi \$a0, 4208 -- 474: 28c00081 ld.d \$ra, \$a0, 0 -- 478: 4c000021 jirl \$ra, \$ra, 0 -- 47c: 18020d24 pcaddi \$a0, 4201 -- 480: 1a000084 pcalau12i \$a0, 4 -- 484: 28d90084 ld.d \$a0, \$a0, 1600 -- 488: 03400000 nop.* -- 48c: 03400000 nop.* -- 490: 1a000084 pcalau12i \$a0, 4 -- 494: 28d90084 ld.d \$a0, \$a0, 1600 -- 498: 18020d84 pcaddi \$a0, 4204 -+ 468: 28dae084 ld.d \$a0, \$a0, 1720 -+ 46c: 1a000084 pcalau12i \$a0, 4 -+ 470: 28dae084 ld.d \$a0, \$a0, 1720 -+ 474: 18021364 pcaddi \$a0, 4251 -+ 478: 18021344 pcaddi \$a0, 4250 -+ 47c: 28c00081 ld.d \$ra, \$a0, 0 -+ 480: 4c000021 jirl \$ra, \$ra, 0 -+ 484: 1a000084 pcalau12i \$a0, 4 -+ 488: 28dbc084 ld.d \$a0, \$a0, 1776 -+ -+0+48c : -+ 48c: 1a000084 pcalau12i \$a0, 4 -+ 490: 28d98084 ld.d \$a0, \$a0, 1632 -+ 494: 18020de4 pcaddi \$a0, 4207 -+ 498: 18020f04 pcaddi \$a0, 4216 - 49c: 28c00081 ld.d \$ra, \$a0, 0 - 4a0: 4c000021 jirl \$ra, \$ra, 0 -- 4a4: 18020d24 pcaddi \$a0, 4201 -+ 4a4: 18020e24 pcaddi \$a0, 4209 - 4a8: 1a000084 pcalau12i \$a0, 4 -- 4ac: 28d96084 ld.d \$a0, \$a0, 1624 -+ 4ac: 28da2084 ld.d \$a0, \$a0, 1672 -+ 4b0: 1a000084 pcalau12i \$a0, 4 -+ 4b4: 28da2084 ld.d \$a0, \$a0, 1672 -+ 4b8: 18020ec4 pcaddi \$a0, 4214 -+ 4bc: 28c00081 ld.d \$ra, \$a0, 0 -+ 4c0: 4c000021 jirl \$ra, \$ra, 0 -+ 4c4: 18020e64 pcaddi \$a0, 4211 -+ 4c8: 1a000084 pcalau12i \$a0, 4 -+ 4cc: 28da8084 ld.d \$a0, \$a0, 1696 -+ -+0+4d0 : -+ 4d0: 18020ec4 pcaddi \$a0, 4214 -+ 4d4: 28c00081 ld.d \$ra, \$a0, 0 -+ 4d8: 4c000021 jirl \$ra, \$ra, 0 - --0+4b0 : -- 4b0: 18020d84 pcaddi \$a0, 4204 -- 4b4: 28c00081 ld.d \$ra, \$a0, 0 -- 4b8: 4c000021 jirl \$ra, \$ra, 0 -+0+4dc : -+ 4dc: 18021224 pcaddi \$a0, 4241 -+ 4e0: 28c00081 ld.d \$ra, \$a0, 0 -+ 4e4: 4c000021 jirl \$ra, \$ra, 0 -+ 4e8: 18021144 pcaddi \$a0, 4234 -+ 4ec: 28c00081 ld.d \$ra, \$a0, 0 -+ 4f0: 4c000021 jirl \$ra, \$ra, 0 -diff --git a/ld/testsuite/ld-loongarch-elf/tlsdesc-dso.s b/ld/testsuite/ld-loongarch-elf/tlsdesc-dso.s -index 936bbcea..faadca61 100644 ---- a/ld/testsuite/ld-loongarch-elf/tlsdesc-dso.s -+++ b/ld/testsuite/ld-loongarch-elf/tlsdesc-dso.s -@@ -1,6 +1,8 @@ - .data - .section .tdata,"awT",@progbits - .global gl1, gl2, gl3, gl4 -+ .global hd1, hd2 -+ .hidden hd1, hd2 - gl1: .dword 1 - gl2: .dword 2 - gl3: .dword 3 -@@ -9,6 +11,8 @@ lo1: .dword 10 - lo2: .dword 20 - lo3: .dword 30 - lo4: .dword 40 -+hd1: .dword 100 -+hd2: .dword 200 - .text - # Access global symbol - fun_gl1: -@@ -63,3 +67,8 @@ fun_lo: - # Access external undef symbol - fun_external: - la.tls.desc $a0, sH1 -+ -+# Access hidden symbol -+fun_hidden: -+ la.tls.desc $a0, hd1 -+ la.tls.desc $a0, hd2 -diff --git a/ld/testsuite/ld-loongarch-elf/tlsdesc_abs.d b/ld/testsuite/ld-loongarch-elf/tlsdesc_abs.d -new file mode 100644 -index 00000000..62f5a2a0 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/tlsdesc_abs.d -@@ -0,0 +1,23 @@ -+#as: -mla-global-with-abs -+#ld: --no-relax -e0 -+#objdump: -dr -+#skip: loongarch32-*-* -+ -+.*: file format .* -+ -+ -+Disassembly of section .text: -+ -+0+120000100 <.*>: -+ 120000100: 14400084 lu12i.w \$a0, .* -+ 120000104: 03850084 ori \$a0, \$a0, .* -+ 120000108: 16000024 lu32i.d \$a0, .* -+ 12000010c: 03000084 lu52i.d \$a0, \$a0, 0 -+ 120000110: 28c00081 ld.d \$ra, \$a0, 0 -+ 120000114: 4c000021 jirl \$ra, \$ra, 0 -+ 120000118: 14400084 lu12i.w \$a0, .* -+ 12000011c: 03850084 ori \$a0, \$a0, .* -+ 120000120: 16000024 lu32i.d \$a0, .* -+ 120000124: 03000084 lu52i.d \$a0, \$a0, 0 -+ 120000128: 28c00081 ld.d \$ra, \$a0, 0 -+ 12000012c: 4c000021 jirl \$ra, \$ra, 0 -diff --git a/ld/testsuite/ld-loongarch-elf/tlsdesc_abs.s b/ld/testsuite/ld-loongarch-elf/tlsdesc_abs.s -new file mode 100644 -index 00000000..61ac9a80 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/tlsdesc_abs.s -@@ -0,0 +1,7 @@ -+ .section ".tdata", "awT", @progbits -+ .global var -+var: .dword 1 -+ .text -+ # No matter which register the user uses, the abs macro expansion uses $a0 -+ la.tls.desc $a0,var -+ la.tls.desc $t0,var -diff --git a/ld/testsuite/ld-loongarch-elf/tlsdesc_extreme.d b/ld/testsuite/ld-loongarch-elf/tlsdesc_extreme.d -new file mode 100644 -index 00000000..55179997 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/tlsdesc_extreme.d -@@ -0,0 +1,25 @@ -+#as: -mla-global-with-pcrel -+#ld: --no-relax -e0 -+#objdump: -dr -+#skip: loongarch32-*-* -+ -+.*: file format .* -+ -+ -+Disassembly of section .text: -+ -+0+120000100 <.*>: -+ 120000100: 1a000084 pcalau12i \$a0, .* -+ 120000104: 02c52001 li.d \$ra, .* -+ 120000108: 16000001 lu32i.d \$ra, 0 -+ 12000010c: 03000021 lu52i.d \$ra, \$ra, 0 -+ 120000110: 00108484 add.d \$a0, \$a0, \$ra -+ 120000114: 28c00081 ld.d \$ra, \$a0, 0 -+ 120000118: 4c000021 jirl \$ra, \$ra, 0 -+ 12000011c: 1a000084 pcalau12i \$a0, .* -+ 120000120: 02c5200d li.d \$t1, .* -+ 120000124: 1600000d lu32i.d \$t1, 0 -+ 120000128: 030001ad lu52i.d \$t1, \$t1, 0 -+ 12000012c: 0010b484 add.d \$a0, \$a0, \$t1 -+ 120000130: 28c00081 ld.d \$ra, \$a0, 0 -+ 120000134: 4c000021 jirl \$ra, \$ra, 0 -diff --git a/ld/testsuite/ld-loongarch-elf/tlsdesc_extreme.s b/ld/testsuite/ld-loongarch-elf/tlsdesc_extreme.s -new file mode 100644 -index 00000000..3582692d ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/tlsdesc_extreme.s -@@ -0,0 +1,7 @@ -+ .section ".tdata", "awT", @progbits -+ .global var -+var: .dword 1 -+ .text -+ # No matter which two registers are passed in, $a0 and $ra are always used -+ la.tls.desc $a0,$ra,var -+ la.tls.desc $t0,$t1,var --- -2.33.0 - diff --git a/LoongArch-Fix-some-test-failures-about-TLS-desc-and-.patch b/LoongArch-Fix-some-test-failures-about-TLS-desc-and-.patch deleted file mode 100644 index 77b4973..0000000 --- a/LoongArch-Fix-some-test-failures-about-TLS-desc-and-.patch +++ /dev/null @@ -1,146 +0,0 @@ -From ced17161d4aac5b19c9aca8e6183607a83fc1774 Mon Sep 17 00:00:00 2001 -From: Xi Ruoyao -Date: Sat, 20 Jan 2024 00:38:24 +0800 -Subject: [PATCH 048/123] LoongArch: Fix some test failures about TLS desc and - TLS relaxation - -There are two issues causing 11 test failures: - -1. The TLS desc tests are matching the entire disassemble of a linked - executable. But if ld is configured --enable-default-hash-style=gnu - (note that most modern distros use this option), the layout of the - linked executables will be different and the immediate operands in - the linked executables will also be different. So we add - "--hash-style=both" for these tests to cancel the effect of - --enable-default-hash-style=gnu, like [x86_64 mark-plt tests]. -2. By default objdump disassemble uses [pseudo-instructions] so "addi.w" - is outputed as "li.w", causing mismatches in TLS relaxation tests. - We can turn off the pseudo-instruction usage in objdump using "-M - no-aliases" to fix them. - -[x86_64 mark-plt tests]: 16666ccc91295d1568c5c2cb0e7600694840dfd9 -[pseudo-instructions]: 17f9439038257b1de0c130a416a9a7645c653cb0 - -Signed-off-by: Xi Ruoyao ---- - ld/testsuite/ld-loongarch-elf/desc-ie.d | 2 +- - ld/testsuite/ld-loongarch-elf/desc-norelax.d | 2 +- - ld/testsuite/ld-loongarch-elf/desc-relax.d | 2 +- - ld/testsuite/ld-loongarch-elf/relax.exp | 14 +++++++------- - ld/testsuite/ld-loongarch-elf/tlsdesc-dso.d | 2 +- - 5 files changed, 11 insertions(+), 11 deletions(-) - -diff --git a/ld/testsuite/ld-loongarch-elf/desc-ie.d b/ld/testsuite/ld-loongarch-elf/desc-ie.d -index d1acbfc6..32e35050 100644 ---- a/ld/testsuite/ld-loongarch-elf/desc-ie.d -+++ b/ld/testsuite/ld-loongarch-elf/desc-ie.d -@@ -1,5 +1,5 @@ - #as: --#ld: -shared -z norelro -e 0x0 -+#ld: -shared -z norelro -e 0x0 --hash-style=both - #objdump: -dr - #skip: loongarch32-*-* - -diff --git a/ld/testsuite/ld-loongarch-elf/desc-norelax.d b/ld/testsuite/ld-loongarch-elf/desc-norelax.d -index 32ce3e5e..e4863dda 100644 ---- a/ld/testsuite/ld-loongarch-elf/desc-norelax.d -+++ b/ld/testsuite/ld-loongarch-elf/desc-norelax.d -@@ -1,5 +1,5 @@ - #as: --#ld: -z norelro -shared --section-start=.got=0x1ff000 -+#ld: -z norelro -shared --section-start=.got=0x1ff000 --hash-style=both - #objdump: -dr - #skip: loongarch32-*-* - -diff --git a/ld/testsuite/ld-loongarch-elf/desc-relax.d b/ld/testsuite/ld-loongarch-elf/desc-relax.d -index ce53d317..c885953c 100644 ---- a/ld/testsuite/ld-loongarch-elf/desc-relax.d -+++ b/ld/testsuite/ld-loongarch-elf/desc-relax.d -@@ -1,5 +1,5 @@ - #as: --#ld: -z norelro -shared -+#ld: -z norelro -shared --hash-style=both - #objdump: -dr - #skip: loongarch32-*-* - -diff --git a/ld/testsuite/ld-loongarch-elf/relax.exp b/ld/testsuite/ld-loongarch-elf/relax.exp -index 107e5a56..c537976a 100644 ---- a/ld/testsuite/ld-loongarch-elf/relax.exp -+++ b/ld/testsuite/ld-loongarch-elf/relax.exp -@@ -104,7 +104,7 @@ if [istarget loongarch64-*-*] { - ] - - if [file exist "tmpdir/relax-tls-le"] { -- set objdump_output1 [run_host_cmd "objdump" "-d tmpdir/relax-tls-le"] -+ set objdump_output1 [run_host_cmd "objdump" "-d tmpdir/relax-tls-le -M no-aliases"] - if { [ regexp ".addi.*st.*" $objdump_output1] } { - pass "loongarch relax success" - } { -@@ -125,7 +125,7 @@ if [istarget loongarch64-*-*] { - ] - - if [file exist "tmpdir/no-relax-tls-le"] { -- set objdump_output2 [run_host_cmd "objdump" "-d tmpdir/no-relax-tls-le"] -+ set objdump_output2 [run_host_cmd "objdump" "-d tmpdir/no-relax-tls-le -M no-aliases"] - if { [ regexp ".*lu12i.*add.*addi.*st.*" $objdump_output2] } { - pass "loongarch no-relax success" - } { -@@ -146,7 +146,7 @@ if [istarget loongarch64-*-*] { - ] - - if [file exist "tmpdir/old-tls-le"] { -- set objdump_output3 [run_host_cmd "objdump" "-d tmpdir/old-tls-le"] -+ set objdump_output3 [run_host_cmd "objdump" "-d tmpdir/old-tls-le -M no-aliases"] - if { [ regexp ".*lu12i.*ori.*add.*addi.*stptr.*" $objdump_output3] } { - pass "loongarch old tls le success" - } { -@@ -167,7 +167,7 @@ if [istarget loongarch64-*-*] { - ] - - if [file exist "tmpdir/realx-compatible"] { -- set objdump_output4 [run_host_cmd "objdump" "-d tmpdir/realx-compatible"] -+ set objdump_output4 [run_host_cmd "objdump" "-d tmpdir/realx-compatible -M no-aliases"] - if { [ regexp ".addi.*st.*" $objdump_output4] && \ - [ regexp ".*lu12i.*ori.*add.*addi.*stptr.*" $objdump_output4] } { - pass "loongarch tls le relax compatible check success" -@@ -188,7 +188,7 @@ if [istarget loongarch64-*-*] { - ] \ - ] - if [file exist "tmpdir/no-realx-compatible"] { -- set objdump_output4 [run_host_cmd "objdump" "-d tmpdir/no-realx-compatible"] -+ set objdump_output4 [run_host_cmd "objdump" "-d tmpdir/no-realx-compatible -M no-aliases"] - if { [ regexp ".*lu12i.*add.*addi.*st.*" $objdump_output4] && \ - [ regexp ".*lu12i.*ori.*add.*addi.*stptr.*" $objdump_output4] } { - pass "loongarch tls le no-relax compatible check success" -@@ -210,7 +210,7 @@ if [istarget loongarch64-*-*] { - ] - - if [file exist "tmpdir/relax-bound-check-tls-le"] { -- set objdump_output5 [run_host_cmd "objdump" "-d tmpdir/relax-bound-check-tls-le"] -+ set objdump_output5 [run_host_cmd "objdump" "-d tmpdir/relax-bound-check-tls-le -M no-aliases"] - if { [ regexp ".*lu12i.*add.*addi.*st.*" $objdump_output5] && \ - [ regexp ".addi.*st.*" $objdump_output5] } { - pass "loongarch no-relax success" -@@ -232,7 +232,7 @@ if [istarget loongarch64-*-*] { - ] - - if [file exist "tmpdir/no-relax-bound-check-tls-le"] { -- set objdump_output5 [run_host_cmd "objdump" "-d tmpdir/no-relax-bound-check-tls-le"] -+ set objdump_output5 [run_host_cmd "objdump" "-d tmpdir/no-relax-bound-check-tls-le -M no-aliases"] - if { [ regexp ".*addi.*st.*" $objdump_output5] } { - pass "loongarch no-relax success" - } { -diff --git a/ld/testsuite/ld-loongarch-elf/tlsdesc-dso.d b/ld/testsuite/ld-loongarch-elf/tlsdesc-dso.d -index 667ad746..453902d1 100644 ---- a/ld/testsuite/ld-loongarch-elf/tlsdesc-dso.d -+++ b/ld/testsuite/ld-loongarch-elf/tlsdesc-dso.d -@@ -1,5 +1,5 @@ - #as: --#ld: -shared -z norelro -+#ld: -shared -z norelro --hash-style=both - #objdump: -dr - #skip: loongarch32-*-* - --- -2.33.0 - diff --git a/LoongArch-Fix-the-issue-of-excessive-relocation-gene.patch b/LoongArch-Fix-the-issue-of-excessive-relocation-gene.patch deleted file mode 100644 index a955a13..0000000 --- a/LoongArch-Fix-the-issue-of-excessive-relocation-gene.patch +++ /dev/null @@ -1,437 +0,0 @@ -From e43c6e4abc81d9bbf66fb210d86682d9f647031d Mon Sep 17 00:00:00 2001 -From: Lulu Cai -Date: Thu, 21 Mar 2024 16:33:21 +0800 -Subject: [PATCH 077/123] LoongArch: Fix the issue of excessive relocation - generated by GD and IE - -Currently, whether GD and IE generate dynamic relocation is -determined by SYMBOL_REFERENCES_LOCAL and bfd_link_executable. -This results in dynamic relocations still being generated in some -situations where dynamic relocations are not necessary (such as -the undefined weak symbol in static links). - -We use RLARCH_TLS_GD_IE_NEED_DYN_RELOC macros to determine whether -GD/IE needs dynamic relocation. If GD/IE requires dynamic relocation, -set need_reloc to true and indx to be a dynamic index. - -At the same time, some test cases were modified to use regular -expression matching instead of complete disassembly matching. ---- - bfd/elfnn-loongarch.c | 179 ++++++++++---------- - ld/testsuite/ld-loongarch-elf/desc-ie.d | 4 +- - ld/testsuite/ld-loongarch-elf/tlsdesc-dso.d | 94 +++++----- - 3 files changed, 142 insertions(+), 135 deletions(-) - -diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c -index f6975957..7f98dce1 100644 ---- a/bfd/elfnn-loongarch.c -+++ b/bfd/elfnn-loongarch.c -@@ -159,6 +159,27 @@ struct loongarch_elf_link_hash_table - || (R_TYPE) == R_LARCH_TLS_LE64_LO20 \ - || (R_TYPE) == R_LARCH_TLS_LE64_HI12) - -+/* If TLS GD/IE need dynamic relocations, INDX will be the dynamic indx, -+ and set NEED_RELOC to true used in allocate_dynrelocs and -+ loongarch_elf_relocate_section for TLS GD/IE. */ -+#define LARCH_TLS_GD_IE_NEED_DYN_RELOC(INFO, DYN, H, INDX, NEED_RELOC) \ -+ do \ -+ { \ -+ if ((H) != NULL \ -+ && (H)->dynindx != -1 \ -+ && WILL_CALL_FINISH_DYNAMIC_SYMBOL ((DYN), \ -+ bfd_link_pic (INFO), (H))) \ -+ (INDX) = (H)->dynindx; \ -+ if (((H) == NULL \ -+ || ELF_ST_VISIBILITY ((H)->other) == STV_DEFAULT \ -+ || (H)->root.type != bfd_link_hash_undefweak) \ -+ && (!bfd_link_executable (INFO) \ -+ || (INDX) != 0)) \ -+ (NEED_RELOC) = true; \ -+ } \ -+ while (0) -+ -+ - /* Generate a PLT header. */ - - static bool -@@ -1276,40 +1297,24 @@ allocate_dynrelocs (struct elf_link_hash_entry *h, void *inf) - h->got.offset = s->size; - if (tls_type & (GOT_TLS_GD | GOT_TLS_IE | GOT_TLS_GDESC)) - { -+ int indx = 0; -+ bool need_reloc = false; -+ LARCH_TLS_GD_IE_NEED_DYN_RELOC (info, dyn, h, indx, -+ need_reloc); - /* TLS_GD needs two dynamic relocs and two GOT slots. */ - if (tls_type & GOT_TLS_GD) - { - s->size += 2 * GOT_ENTRY_SIZE; -- if (bfd_link_executable (info)) -- { -- /* Link exe and not defined local. */ -- if (!SYMBOL_REFERENCES_LOCAL (info, h)) -- htab->elf.srelgot->size += 2 * sizeof (ElfNN_External_Rela); -- } -- else -- { -- if (SYMBOL_REFERENCES_LOCAL (info, h)) -- htab->elf.srelgot->size += sizeof (ElfNN_External_Rela); -- else -- htab->elf.srelgot->size += 2 * sizeof (ElfNN_External_Rela); -- } -+ if (need_reloc) -+ htab->elf.srelgot->size += 2 * sizeof (ElfNN_External_Rela); - } - - /* TLS_IE needs one dynamic reloc and one GOT slot. */ - if (tls_type & GOT_TLS_IE) - { - s->size += GOT_ENTRY_SIZE; -- -- if (bfd_link_executable (info)) -- { -- /* Link exe and not defined local. */ -- if (!SYMBOL_REFERENCES_LOCAL (info, h)) -- htab->elf.srelgot->size += sizeof (ElfNN_External_Rela); -- } -- else -- { -- htab->elf.srelgot->size += sizeof (ElfNN_External_Rela); -- } -+ if (need_reloc) -+ htab->elf.srelgot->size += 2 * sizeof (ElfNN_External_Rela); - } - - /* TLS_DESC needs one dynamic reloc and two GOT slot. */ -@@ -2550,13 +2555,18 @@ loongarch_reloc_is_fatal (struct bfd_link_info *info, - }) - - -+/* Compute the tp/dtp offset of a tls symbol. -+ It is dtp offset in dynamic tls model (gd/ld) and tp -+ offset in static tls model (ie/le). Both offsets are -+ calculated the same way on LoongArch, so the same -+ function is used. */ - static bfd_vma --tls_dtpoff_base (struct bfd_link_info *info) -+tlsoff (struct bfd_link_info *info, bfd_vma addr) - { - /* If tls_sec is NULL, we should have signalled an error already. */ - if (elf_hash_table (info)->tls_sec == NULL) - return 0; -- return elf_hash_table (info)->tls_sec->vma; -+ return addr - elf_hash_table (info)->tls_sec->vma; - } - - -@@ -2890,7 +2900,7 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, - is_undefweak, name, "TLS section not be created"); - } - else -- relocation -= elf_hash_table (info)->tls_sec->vma; -+ relocation = tlsoff (info, relocation); - } - else - { -@@ -3416,7 +3426,7 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, - - case R_LARCH_TLS_LE_HI20_R: - relocation += rel->r_addend; -- relocation -= elf_hash_table (info)->tls_sec->vma; -+ relocation = tlsoff (info, relocation); - RELOCATE_TLS_TP32_HI20 (relocation); - break; - -@@ -3599,7 +3609,7 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, - BFD_ASSERT (resolved_local && elf_hash_table (info)->tls_sec); - - relocation += rel->r_addend; -- relocation -= elf_hash_table (info)->tls_sec->vma; -+ relocation = tlsoff (info, relocation); - break; - - /* TLS IE LD/GD process separately is troublesome. -@@ -3654,71 +3664,72 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, - /* If a tls variable is accessed in multiple ways, GD uses - the first two slots of GOT, desc follows with two slots, - and IE uses one slot at the end. */ -- desc_off = 0; -- if (GOT_TLS_GD_BOTH_P (tls_type)) -- desc_off = 2 * GOT_ENTRY_SIZE; -- -- ie_off = 0; -- if (GOT_TLS_GD_BOTH_P (tls_type) && (tls_type & GOT_TLS_IE)) -- ie_off = 4 * GOT_ENTRY_SIZE; -- else if (GOT_TLS_GD_ANY_P (tls_type) && (tls_type & GOT_TLS_IE)) -- ie_off = 2 * GOT_ENTRY_SIZE; -+ off = 0; -+ if (tls_type & GOT_TLS_GD) -+ off += 2 * GOT_ENTRY_SIZE; -+ desc_off = off; -+ if (tls_type & GOT_TLS_GDESC) -+ off += 2 * GOT_ENTRY_SIZE; -+ ie_off = off; - - if ((got_off & 1) == 0) - { - Elf_Internal_Rela rela; - asection *relgot = htab->elf.srelgot; -- bfd_vma tls_block_off = 0; - -- if (SYMBOL_REFERENCES_LOCAL (info, h)) -- { -- BFD_ASSERT (elf_hash_table (info)->tls_sec); -- tls_block_off = relocation -- - elf_hash_table (info)->tls_sec->vma; -- } -+ int indx = 0; -+ bool need_reloc = false; -+ LARCH_TLS_GD_IE_NEED_DYN_RELOC (info, is_dyn, h, indx, -+ need_reloc); - - if (tls_type & GOT_TLS_GD) - { -- rela.r_offset = sec_addr (got) + got_off; -- rela.r_addend = 0; -- if (SYMBOL_REFERENCES_LOCAL (info, h)) -+ if (need_reloc) - { -- /* Local sym, used in exec, set module id 1. */ -- if (bfd_link_executable (info)) -- bfd_put_NN (output_bfd, 1, got->contents + got_off); -+ /* Dynamic resolved Module ID. */ -+ rela.r_offset = sec_addr (got) + got_off; -+ rela.r_addend = 0; -+ rela.r_info = ELFNN_R_INFO (indx,R_LARCH_TLS_DTPMODNN); -+ bfd_put_NN (output_bfd, 0, got->contents + got_off); -+ loongarch_elf_append_rela (output_bfd, relgot, &rela); -+ -+ if (indx == 0) -+ { -+ /* Local symbol, tp offset has been known. */ -+ BFD_ASSERT (! unresolved_reloc); -+ bfd_put_NN (output_bfd, -+ tlsoff (info, relocation), -+ (got->contents + got_off + GOT_ENTRY_SIZE)); -+ } - else - { -- rela.r_info = ELFNN_R_INFO (0, R_LARCH_TLS_DTPMODNN); -+ /* Dynamic resolved block offset. */ -+ bfd_put_NN (output_bfd, 0, -+ got->contents + got_off + GOT_ENTRY_SIZE); -+ rela.r_info = ELFNN_R_INFO (indx, -+ R_LARCH_TLS_DTPRELNN); -+ rela.r_offset += GOT_ENTRY_SIZE; - loongarch_elf_append_rela (output_bfd, relgot, &rela); - } -- -- bfd_put_NN (output_bfd, tls_block_off, -- got->contents + got_off + GOT_ENTRY_SIZE); - } -- /* Dynamic resolved. */ - else - { -- /* Dynamic relocate module id. */ -- rela.r_info = ELFNN_R_INFO (h->dynindx, -- R_LARCH_TLS_DTPMODNN); -- loongarch_elf_append_rela (output_bfd, relgot, &rela); -- -- /* Dynamic relocate offset of block. */ -- rela.r_offset += GOT_ENTRY_SIZE; -- rela.r_info = ELFNN_R_INFO (h->dynindx, -- R_LARCH_TLS_DTPRELNN); -- loongarch_elf_append_rela (output_bfd, relgot, &rela); -+ /* In a static link or an executable link with the symbol -+ binding locally. Mark it as belonging to module 1. */ -+ bfd_put_NN (output_bfd, 1, got->contents + got_off); -+ bfd_put_NN (output_bfd, tlsoff (info, relocation), -+ got->contents + got_off + GOT_ENTRY_SIZE); - } - } - if (tls_type & GOT_TLS_GDESC) - { - /* Unless it is a static link, DESC always emits a - dynamic relocation. */ -- int indx = h && h->dynindx != -1 ? h->dynindx : 0; -+ indx = h && h->dynindx != -1 ? h->dynindx : 0; - rela.r_offset = sec_addr (got) + got_off + desc_off; - rela.r_addend = 0; - if (indx == 0) -- rela.r_addend = relocation - tls_dtpoff_base (info); -+ rela.r_addend = tlsoff (info, relocation); - - rela.r_info = ELFNN_R_INFO (indx, R_LARCH_TLS_DESCNN); - loongarch_elf_append_rela (output_bfd, relgot, &rela); -@@ -3727,28 +3738,24 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, - } - if (tls_type & GOT_TLS_IE) - { -- rela.r_offset = sec_addr (got) + got_off + ie_off; -- if (SYMBOL_REFERENCES_LOCAL (info, h)) -+ if (need_reloc) - { -- /* Local sym, used in exec, set module id 1. */ -- if (!bfd_link_executable (info)) -- { -- rela.r_info = ELFNN_R_INFO (0, R_LARCH_TLS_TPRELNN); -- rela.r_addend = tls_block_off; -- loongarch_elf_append_rela (output_bfd, relgot, &rela); -- } -+ bfd_put_NN (output_bfd, 0, -+ got->contents + got_off + ie_off); -+ rela.r_offset = sec_addr (got) + got_off + ie_off; -+ rela.r_addend = 0; - -- bfd_put_NN (output_bfd, tls_block_off, -- got->contents + got_off + ie_off); -+ if (indx == 0) -+ rela.r_addend = tlsoff (info, relocation); -+ rela.r_info = ELFNN_R_INFO (indx, R_LARCH_TLS_TPRELNN); -+ loongarch_elf_append_rela (output_bfd, relgot, &rela); - } -- /* Dynamic resolved. */ - else - { -- /* Dynamic relocate offset of block. */ -- rela.r_info = ELFNN_R_INFO (h->dynindx, -- R_LARCH_TLS_TPRELNN); -- rela.r_addend = 0; -- loongarch_elf_append_rela (output_bfd, relgot, &rela); -+ /* In a static link or an executable link with the symbol -+ bindinglocally, compute offset directly. */ -+ bfd_put_NN (output_bfd, tlsoff (info, relocation), -+ got->contents + got_off + ie_off); - } - } - } -@@ -3787,7 +3794,7 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, - - tls_type = _bfd_loongarch_elf_tls_type (input_bfd, h, r_symndx); - /* Use both TLS_GD and TLS_DESC. */ -- if ((tls_type & GOT_TLS_GD) && (tls_type & GOT_TLS_GDESC)) -+ if (GOT_TLS_GD_BOTH_P (tls_type)) - relocation += 2 * GOT_ENTRY_SIZE; - - if (r_type == R_LARCH_TLS_DESC64_PC_LO20) -diff --git a/ld/testsuite/ld-loongarch-elf/desc-ie.d b/ld/testsuite/ld-loongarch-elf/desc-ie.d -index e1f49e2d..c833b233 100644 ---- a/ld/testsuite/ld-loongarch-elf/desc-ie.d -+++ b/ld/testsuite/ld-loongarch-elf/desc-ie.d -@@ -9,6 +9,6 @@ Disassembly of section .text: - - [0-9a-f]+ : - +[0-9a-f]+: 1a000084 pcalau12i \$a0, .* -- +[0-9a-f]+: 28cca084 ld.d \$a0, \$a0, .* -+ +[0-9a-f]+: 28cd0084 ld.d \$a0, \$a0, .* - +[0-9a-f]+: 1a000084 pcalau12i \$a0, .* -- +[0-9a-f]+: 28cca084 ld.d \$a0, \$a0, .* -+ +[0-9a-f]+: 28cd0084 ld.d \$a0, \$a0, .* -diff --git a/ld/testsuite/ld-loongarch-elf/tlsdesc-dso.d b/ld/testsuite/ld-loongarch-elf/tlsdesc-dso.d -index 84ea97e0..8f66302f 100644 ---- a/ld/testsuite/ld-loongarch-elf/tlsdesc-dso.d -+++ b/ld/testsuite/ld-loongarch-elf/tlsdesc-dso.d -@@ -8,53 +8,53 @@ - - Disassembly of section .text: - --0+448 : -- 448: 18021584 pcaddi \$a0, 4268 -- 44c: 1a000084 pcalau12i \$a0, 4 -- 450: 28dc2084 ld.d \$a0, \$a0, 1800 -- 454: 18021364 pcaddi \$a0, 4251 -- 458: 180213c4 pcaddi \$a0, 4254 -- 45c: 28c00081 ld.d \$ra, \$a0, 0 -- 460: 4c000021 jirl \$ra, \$ra, 0 -- 464: 1a000084 pcalau12i \$a0, 4 -- 468: 28dae084 ld.d \$a0, \$a0, 1720 -- 46c: 1a000084 pcalau12i \$a0, 4 -- 470: 28dae084 ld.d \$a0, \$a0, 1720 -- 474: 18021364 pcaddi \$a0, 4251 -- 478: 18021344 pcaddi \$a0, 4250 -- 47c: 28c00081 ld.d \$ra, \$a0, 0 -- 480: 4c000021 jirl \$ra, \$ra, 0 -- 484: 1a000084 pcalau12i \$a0, 4 -- 488: 28dbc084 ld.d \$a0, \$a0, 1776 -+[0-9a-f]+ : -+ +[0-9a-f]+: 18021584 pcaddi \$a0, 4268 -+ +[0-9a-f]+: 1a000084 pcalau12i \$a0, 4 -+ +[0-9a-f]+: 28dd4084 ld.d \$a0, \$a0, 1872 -+ +[0-9a-f]+: 18021364 pcaddi \$a0, 4251 -+ +[0-9a-f]+: 180213c4 pcaddi \$a0, 4254 -+ +[0-9a-f]+: 28c00081 ld.d \$ra, \$a0, 0 -+ +[0-9a-f]+: 4c000021 jirl \$ra, \$ra, 0 -+ +[0-9a-f]+: 1a000084 pcalau12i \$a0, 4 -+ +[0-9a-f]+: 28dc0084 ld.d \$a0, \$a0, 1792 -+ +[0-9a-f]+: 1a000084 pcalau12i \$a0, 4 -+ +[0-9a-f]+: 28dc0084 ld.d \$a0, \$a0, 1792 -+ +[0-9a-f]+: 18021364 pcaddi \$a0, 4251 -+ +[0-9a-f]+: 180213c4 pcaddi \$a0, 4254 -+ +[0-9a-f]+: 28c00081 ld.d \$ra, \$a0, 0 -+ +[0-9a-f]+: 4c000021 jirl \$ra, \$ra, 0 -+ +[0-9a-f]+: 1a000084 pcalau12i \$a0, 4 -+ +[0-9a-f]+: 28dce084 ld.d \$a0, \$a0, 1848 - --0+48c : -- 48c: 1a000084 pcalau12i \$a0, 4 -- 490: 28d98084 ld.d \$a0, \$a0, 1632 -- 494: 18020de4 pcaddi \$a0, 4207 -- 498: 18020f04 pcaddi \$a0, 4216 -- 49c: 28c00081 ld.d \$ra, \$a0, 0 -- 4a0: 4c000021 jirl \$ra, \$ra, 0 -- 4a4: 18020e24 pcaddi \$a0, 4209 -- 4a8: 1a000084 pcalau12i \$a0, 4 -- 4ac: 28da2084 ld.d \$a0, \$a0, 1672 -- 4b0: 1a000084 pcalau12i \$a0, 4 -- 4b4: 28da2084 ld.d \$a0, \$a0, 1672 -- 4b8: 18020ec4 pcaddi \$a0, 4214 -- 4bc: 28c00081 ld.d \$ra, \$a0, 0 -- 4c0: 4c000021 jirl \$ra, \$ra, 0 -- 4c4: 18020e64 pcaddi \$a0, 4211 -- 4c8: 1a000084 pcalau12i \$a0, 4 -- 4cc: 28da8084 ld.d \$a0, \$a0, 1696 -+[0-9a-f]+ : -+ +[0-9a-f]+: 1a000084 pcalau12i \$a0, 4 -+ +[0-9a-f]+: 28daa084 ld.d \$a0, \$a0, 1704 -+ +[0-9a-f]+: 18020de4 pcaddi \$a0, 4207 -+ +[0-9a-f]+: 18020f04 pcaddi \$a0, 4216 -+ +[0-9a-f]+: 28c00081 ld.d \$ra, \$a0, 0 -+ +[0-9a-f]+: 4c000021 jirl \$ra, \$ra, 0 -+ +[0-9a-f]+: 18020e24 pcaddi \$a0, 4209 -+ +[0-9a-f]+: 1a000084 pcalau12i \$a0, 4 -+ +[0-9a-f]+: 28db4084 ld.d \$a0, \$a0, 1744 -+ +[0-9a-f]+: 1a000084 pcalau12i \$a0, 4 -+ +[0-9a-f]+: 28db4084 ld.d \$a0, \$a0, 1744 -+ +[0-9a-f]+: 18020f44 pcaddi \$a0, 4218 -+ +[0-9a-f]+: 28c00081 ld.d \$ra, \$a0, 0 -+ +[0-9a-f]+: 4c000021 jirl \$ra, \$ra, 0 -+ +[0-9a-f]+: 18020e64 pcaddi \$a0, 4211 -+ +[0-9a-f]+: 1a000084 pcalau12i \$a0, 4 -+ +[0-9a-f]+: 28dba084 ld.d \$a0, \$a0, 1768 - --0+4d0 : -- 4d0: 18020ec4 pcaddi \$a0, 4214 -- 4d4: 28c00081 ld.d \$ra, \$a0, 0 -- 4d8: 4c000021 jirl \$ra, \$ra, 0 -+[0-9a-f]+ : -+ +[0-9a-f]+: 18020ec4 pcaddi \$a0, 4214 -+ +[0-9a-f]+: 28c00081 ld.d \$ra, \$a0, 0 -+ +[0-9a-f]+: 4c000021 jirl \$ra, \$ra, 0 - --0+4dc : -- 4dc: 18021224 pcaddi \$a0, 4241 -- 4e0: 28c00081 ld.d \$ra, \$a0, 0 -- 4e4: 4c000021 jirl \$ra, \$ra, 0 -- 4e8: 18021144 pcaddi \$a0, 4234 -- 4ec: 28c00081 ld.d \$ra, \$a0, 0 -- 4f0: 4c000021 jirl \$ra, \$ra, 0 -+[0-9a-f]+ : -+ +[0-9a-f]+: 18021224 pcaddi \$a0, 4241 -+ +[0-9a-f]+: 28c00081 ld.d \$ra, \$a0, 0 -+ +[0-9a-f]+: 4c000021 jirl \$ra, \$ra, 0 -+ +[0-9a-f]+: 18021144 pcaddi \$a0, 4234 -+ +[0-9a-f]+: 28c00081 ld.d \$ra, \$a0, 0 -+ +[0-9a-f]+: 4c000021 jirl \$ra, \$ra, 0 --- -2.33.0 - diff --git a/LoongArch-Fix-wrong-relocation-handling-of-symbols-d.patch b/LoongArch-Fix-wrong-relocation-handling-of-symbols-d.patch deleted file mode 100644 index b41195d..0000000 --- a/LoongArch-Fix-wrong-relocation-handling-of-symbols-d.patch +++ /dev/null @@ -1,126 +0,0 @@ -From a5d5353514c361b3fbc5be1e5d1b51c7b3de591b Mon Sep 17 00:00:00 2001 -From: Lulu Cai -Date: Fri, 9 Aug 2024 17:40:59 +0800 -Subject: [PATCH 109/123] LoongArch: Fix wrong relocation handling of symbols - defined by PROVIDE - -If the symbol defined by PROVIDE in the link script is not in SECTION, -the symbol is placed in the ABS section. The linker considers that -symbols in the ABS section do not need to calculate PC relative offsets. - -Symbols in ABS sections should calculate PC relative offsets normally -based on relocations. ---- - bfd/elfnn-loongarch.c | 2 +- - ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp | 3 +++ - ld/testsuite/ld-loongarch-elf/provide_abs.d | 12 ++++++++++++ - ld/testsuite/ld-loongarch-elf/provide_abs.ld | 1 + - ld/testsuite/ld-loongarch-elf/provide_noabs.d | 13 +++++++++++++ - ld/testsuite/ld-loongarch-elf/provide_noabs.ld | 7 +++++++ - ld/testsuite/ld-loongarch-elf/provide_sym.s | 7 +++++++ - 7 files changed, 44 insertions(+), 1 deletion(-) - create mode 100644 ld/testsuite/ld-loongarch-elf/provide_abs.d - create mode 100644 ld/testsuite/ld-loongarch-elf/provide_abs.ld - create mode 100644 ld/testsuite/ld-loongarch-elf/provide_noabs.d - create mode 100644 ld/testsuite/ld-loongarch-elf/provide_noabs.ld - create mode 100644 ld/testsuite/ld-loongarch-elf/provide_sym.s - -diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c -index 0c499c47..14ecd944 100644 ---- a/bfd/elfnn-loongarch.c -+++ b/bfd/elfnn-loongarch.c -@@ -3312,7 +3312,7 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, - /* The r_symndx will be STN_UNDEF (zero) only for relocs against symbols - from removed linkonce sections, or sections discarded by a linker - script. Also for R_*_SOP_PUSH_ABSOLUTE and PCREL to specify const. */ -- if (r_symndx == STN_UNDEF || bfd_is_abs_section (sec)) -+ if (r_symndx == STN_UNDEF) - { - defined_local = false; - resolved_local = false; -diff --git a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -index 78726900..cb6d2296 100644 ---- a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -+++ b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -@@ -184,5 +184,8 @@ if [istarget "loongarch64-*-*"] { - run_dump_test "ie-le-relax" - run_dump_test "tlsdesc_abs" - run_dump_test "tlsdesc_extreme" -+ run_dump_test "provide_abs" -+ run_dump_test "provide_noabs" -+ - } - -diff --git a/ld/testsuite/ld-loongarch-elf/provide_abs.d b/ld/testsuite/ld-loongarch-elf/provide_abs.d -new file mode 100644 -index 00000000..1514fb18 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/provide_abs.d -@@ -0,0 +1,12 @@ -+#source: provide_sym.s -+#as: -+#ld: -T provide_abs.ld -+#objdump: -d -+ -+.*: +file format .* -+ -+#... -+ 0: 58001085 beq \$a0, \$a1, 16 # 10 -+ 4: 40000c80 beqz \$a0, 12 # 10 -+ 8: 54000800 bl 8 # 10 -+#pass -diff --git a/ld/testsuite/ld-loongarch-elf/provide_abs.ld b/ld/testsuite/ld-loongarch-elf/provide_abs.ld -new file mode 100644 -index 00000000..473476cd ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/provide_abs.ld -@@ -0,0 +1 @@ -+PROVIDE(fun1 = 0x10); -diff --git a/ld/testsuite/ld-loongarch-elf/provide_noabs.d b/ld/testsuite/ld-loongarch-elf/provide_noabs.d -new file mode 100644 -index 00000000..7d6bc4d1 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/provide_noabs.d -@@ -0,0 +1,13 @@ -+#source: provide_sym.s -+#as: -+#ld: -T provide_noabs.ld -+#objdump: -d -+ -+.*: +file format .* -+ -+ -+#... -+ 0: 58001085 beq \$a0, \$a1, 16 # 10 -+ 4: 40000c80 beqz \$a0, 12 # 10 -+ 8: 54000800 bl 8 # 10 -+#pass -diff --git a/ld/testsuite/ld-loongarch-elf/provide_noabs.ld b/ld/testsuite/ld-loongarch-elf/provide_noabs.ld -new file mode 100644 -index 00000000..0154c6f3 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/provide_noabs.ld -@@ -0,0 +1,7 @@ -+SECTIONS -+{ -+ .text : -+ { -+ PROVIDE(fun1 = 0x10); -+ } -+} -diff --git a/ld/testsuite/ld-loongarch-elf/provide_sym.s b/ld/testsuite/ld-loongarch-elf/provide_sym.s -new file mode 100644 -index 00000000..6610894e ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/provide_sym.s -@@ -0,0 +1,7 @@ -+ .text -+ .globl main -+ .type main, @function -+main: -+ beq $a0,$a1,%b16(fun1) -+ beqz $a0,%b21(fun1) -+ bl %b26(fun1) --- -2.33.0 - diff --git a/LoongArch-Fixed-ABI-v1.00-TLS-dynamic-relocation-gen.patch b/LoongArch-Fixed-ABI-v1.00-TLS-dynamic-relocation-gen.patch deleted file mode 100644 index 38105a7..0000000 --- a/LoongArch-Fixed-ABI-v1.00-TLS-dynamic-relocation-gen.patch +++ /dev/null @@ -1,152 +0,0 @@ -From aa37c01e929ddd41416ecdd6d8b57799cff4b001 Mon Sep 17 00:00:00 2001 -From: Lulu Cai -Date: Thu, 5 Sep 2024 10:20:49 +0800 -Subject: [PATCH 111/123] LoongArch: Fixed ABI v1.00 TLS dynamic relocation - generation bug - -Commit "b67a17aa7c0c478a" modified the logic of allocating dynamic -relocation space for TLS GD/IE, but only modified the logic of -generation dynamic relocations for TLS GD/IE in ABI v2.00. When -linking an object file of ABI v1.00 with bfd ld of ABI v2.00, it -will cause an assertion failure. - -Modified the dynamic relocation generation logic of TLS GD/IE -in ABI v1.00 to be consistent with ABI v2.00. ---- - bfd/elfnn-loongarch.c | 92 +++++++++++++++++++++---------------------- - 1 file changed, 45 insertions(+), 47 deletions(-) - -diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c -index 14ecd944..30ac5555 100644 ---- a/bfd/elfnn-loongarch.c -+++ b/bfd/elfnn-loongarch.c -@@ -3541,7 +3541,7 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, - bfd_reloc_notsupported, is_undefweak, name, - "TLS section not be created")); - else -- relocation -= elf_hash_table (info)->tls_sec->vma; -+ relocation = tlsoff (info, relocation); - } - else - fatal = (loongarch_reloc_is_fatal -@@ -3890,73 +3890,71 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, - { - Elf_Internal_Rela rela; - asection *srel = htab->elf.srelgot; -- bfd_vma tls_block_off = 0; - -- if (LARCH_REF_LOCAL (info, h)) -- { -- BFD_ASSERT (elf_hash_table (info)->tls_sec); -- tls_block_off = relocation -- - elf_hash_table (info)->tls_sec->vma; -- } -+ int indx = 0; -+ bool need_reloc = false; -+ LARCH_TLS_GD_IE_NEED_DYN_RELOC (info, is_dyn, h, indx, -+ need_reloc); - - if (tls_type & GOT_TLS_GD) - { -- rela.r_offset = sec_addr (got) + got_off; -- rela.r_addend = 0; -- if (LARCH_REF_LOCAL (info, h)) -+ if (need_reloc) - { -- /* Local sym, used in exec, set module id 1. */ -- if (bfd_link_executable (info)) -- bfd_put_NN (output_bfd, 1, got->contents + got_off); -+ /* Dynamic resolved Module ID. */ -+ rela.r_offset = sec_addr (got) + got_off; -+ rela.r_addend = 0; -+ rela.r_info = ELFNN_R_INFO (indx, R_LARCH_TLS_DTPMODNN); -+ bfd_put_NN (output_bfd, 0, got->contents + got_off); -+ loongarch_elf_append_rela (output_bfd, srel, &rela); -+ -+ if (indx == 0) -+ { -+ /* Local symbol, tp offset has been known. */ -+ BFD_ASSERT (! unresolved_reloc); -+ bfd_put_NN (output_bfd, -+ tlsoff (info, relocation), -+ (got->contents + got_off + GOT_ENTRY_SIZE)); -+ } - else - { -- rela.r_info = ELFNN_R_INFO (0, -- R_LARCH_TLS_DTPMODNN); -+ /* Dynamic resolved block offset. */ -+ bfd_put_NN (output_bfd, 0, -+ got->contents + got_off + GOT_ENTRY_SIZE); -+ rela.r_info = ELFNN_R_INFO (indx, -+ R_LARCH_TLS_DTPRELNN); -+ rela.r_offset += GOT_ENTRY_SIZE; - loongarch_elf_append_rela (output_bfd, srel, &rela); - } -- -- bfd_put_NN (output_bfd, tls_block_off, -- got->contents + got_off + GOT_ENTRY_SIZE); - } -- /* Dynamic resolved. */ - else - { -- /* Dynamic relocate module id. */ -- rela.r_info = ELFNN_R_INFO (h->dynindx, -- R_LARCH_TLS_DTPMODNN); -- loongarch_elf_append_rela (output_bfd, srel, &rela); -- -- /* Dynamic relocate offset of block. */ -- rela.r_offset += GOT_ENTRY_SIZE; -- rela.r_info = ELFNN_R_INFO (h->dynindx, -- R_LARCH_TLS_DTPRELNN); -- loongarch_elf_append_rela (output_bfd, srel, &rela); -+ /* In a static link or an executable link with the symbol -+ binding locally. Mark it as belonging to module 1. */ -+ bfd_put_NN (output_bfd, 1, got->contents + got_off); -+ bfd_put_NN (output_bfd, tlsoff (info, relocation), -+ got->contents + got_off + GOT_ENTRY_SIZE); - } - } - if (tls_type & GOT_TLS_IE) - { -- rela.r_offset = sec_addr (got) + got_off + ie_off; -- if (LARCH_REF_LOCAL (info, h)) -+ if (need_reloc) - { -- /* Local sym, used in exec, set module id 1. */ -- if (!bfd_link_executable (info)) -- { -- rela.r_info = ELFNN_R_INFO (0, R_LARCH_TLS_TPRELNN); -- rela.r_addend = tls_block_off; -- loongarch_elf_append_rela (output_bfd, srel, &rela); -- } -+ bfd_put_NN (output_bfd, 0, -+ got->contents + got_off + ie_off); -+ rela.r_offset = sec_addr (got) + got_off + ie_off; -+ rela.r_addend = 0; - -- bfd_put_NN (output_bfd, tls_block_off, -- got->contents + got_off + ie_off); -+ if (indx == 0) -+ rela.r_addend = tlsoff (info, relocation); -+ rela.r_info = ELFNN_R_INFO (indx, R_LARCH_TLS_TPRELNN); -+ loongarch_elf_append_rela (output_bfd, srel, &rela); - } -- /* Dynamic resolved. */ - else - { -- /* Dynamic relocate offset of block. */ -- rela.r_info = ELFNN_R_INFO (h->dynindx, -- R_LARCH_TLS_TPRELNN); -- rela.r_addend = 0; -- loongarch_elf_append_rela (output_bfd, srel, &rela); -+ /* In a static link or an executable link with the symbol -+ binding locally, compute offset directly. */ -+ bfd_put_NN (output_bfd, tlsoff (info, relocation), -+ got->contents + got_off + ie_off); - } - } - } --- -2.33.0 - diff --git a/LoongArch-Fixed-R_LARCH_-32-64-_PCREL-generation-bug.patch b/LoongArch-Fixed-R_LARCH_-32-64-_PCREL-generation-bug.patch deleted file mode 100644 index a5fe072..0000000 --- a/LoongArch-Fixed-R_LARCH_-32-64-_PCREL-generation-bug.patch +++ /dev/null @@ -1,81 +0,0 @@ -From 75fa7292c935fc1306985b6959712d633edc9e36 Mon Sep 17 00:00:00 2001 -From: Lulu Cai -Date: Sat, 21 Sep 2024 11:29:39 +0800 -Subject: [PATCH 115/123] LoongArch: Fixed R_LARCH_[32/64]_PCREL generation bug - -The enum BFD_RELOC_[32/64] was mistakenly used in the macro instead -of the relocation in fixp. This can cause the second relocation -of a pair to be deleted when -mthin-add-sub is enabled. Apply the -correct macro to fix this. - -Also sets the initial value of -mthin-add-sub. ---- - gas/config/tc-loongarch.h | 3 ++- - gas/testsuite/gas/loongarch/no_thin_add_sub_8_16.d | 12 ++++++++++++ - gas/testsuite/gas/loongarch/no_thin_add_sub_8_16.s | 6 ++++++ - opcodes/loongarch-opc.c | 3 ++- - 4 files changed, 22 insertions(+), 2 deletions(-) - create mode 100644 gas/testsuite/gas/loongarch/no_thin_add_sub_8_16.d - create mode 100644 gas/testsuite/gas/loongarch/no_thin_add_sub_8_16.s - -diff --git a/gas/config/tc-loongarch.h b/gas/config/tc-loongarch.h -index 05c0af45..2f081edf 100644 ---- a/gas/config/tc-loongarch.h -+++ b/gas/config/tc-loongarch.h -@@ -79,7 +79,8 @@ extern bool loongarch_frag_align_code (int, int); - SEC_CODE, we generate 32/64_PCREL. */ - #define TC_FORCE_RELOCATION_SUB_LOCAL(FIX, SEG) \ - (!(LARCH_opts.thin_add_sub \ -- && (BFD_RELOC_32 || BFD_RELOC_64) \ -+ && ((FIX)->fx_r_type == BFD_RELOC_32 \ -+ ||(FIX)->fx_r_type == BFD_RELOC_64) \ - && (!LARCH_opts.relax \ - || S_GET_VALUE (FIX->fx_subsy) \ - == FIX->fx_frag->fr_address + FIX->fx_where \ -diff --git a/gas/testsuite/gas/loongarch/no_thin_add_sub_8_16.d b/gas/testsuite/gas/loongarch/no_thin_add_sub_8_16.d -new file mode 100644 -index 00000000..334d1742 ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/no_thin_add_sub_8_16.d -@@ -0,0 +1,12 @@ -+#as: -mthin-add-sub -+#readelf: -rW -+#skip: loongarch32-*-* -+ -+Relocation section '.rela.text' at offset 0x108 contains 6 entries: -+.* -+0+0 000000060000002f R_LARCH_ADD8 0+0 global_a \+ 0 -+0+0 0000000400000034 R_LARCH_SUB8 0+0 L0\^A \+ 0 -+0+1 0000000600000030 R_LARCH_ADD16 0+0 global_a \+ 0 -+0+1 0000000500000035 R_LARCH_SUB16 0+1 L0\^A \+ 0 -+0+3 0000000600000063 R_LARCH_32_PCREL 0+0 global_a \+ 0 -+0+7 000000060000006d R_LARCH_64_PCREL 0+0 global_a \+ 0 -diff --git a/gas/testsuite/gas/loongarch/no_thin_add_sub_8_16.s b/gas/testsuite/gas/loongarch/no_thin_add_sub_8_16.s -new file mode 100644 -index 00000000..68f3655c ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/no_thin_add_sub_8_16.s -@@ -0,0 +1,6 @@ -+ .text -+.L1: -+ .byte global_a - . -+ .2byte global_a - . -+ .4byte global_a - . -+ .8byte global_a - . -diff --git a/opcodes/loongarch-opc.c b/opcodes/loongarch-opc.c -index 6afc0e8a..f3794b6a 100644 ---- a/opcodes/loongarch-opc.c -+++ b/opcodes/loongarch-opc.c -@@ -24,7 +24,8 @@ - - struct loongarch_ASEs_option LARCH_opts = - { -- .relax = 1 -+ .relax = 1, -+ .thin_add_sub = 0 - }; - - size_t --- -2.33.0 - diff --git a/LoongArch-Fixed-precedence-of-expression-operators-i.patch b/LoongArch-Fixed-precedence-of-expression-operators-i.patch deleted file mode 100644 index b0a538d..0000000 --- a/LoongArch-Fixed-precedence-of-expression-operators-i.patch +++ /dev/null @@ -1,86 +0,0 @@ -From 75fd1d4832ec228aa66be49e24ba686bfeb5507b Mon Sep 17 00:00:00 2001 -From: Lulu Cai -Date: Mon, 2 Sep 2024 12:05:54 +0800 -Subject: [PATCH 119/123] LoongArch: Fixed precedence of expression operators - in instructions - -The precedence of the operators "+" and "-" in the current loongarch -instruction expression is higher than "<<" and ">>", which is different -from the explanation in the user guide. - -We modified the precedence of "<<" and ">>" to be higher than "+" and "-". ---- - gas/config/loongarch-parse.y | 24 ++++++++++++------------ - gas/testsuite/gas/loongarch/insn_expr.d | 10 ++++++++++ - gas/testsuite/gas/loongarch/insn_expr.s | 1 + - 3 files changed, 23 insertions(+), 12 deletions(-) - create mode 100644 gas/testsuite/gas/loongarch/insn_expr.d - create mode 100644 gas/testsuite/gas/loongarch/insn_expr.s - -diff --git a/gas/config/loongarch-parse.y b/gas/config/loongarch-parse.y -index f786fdae..ec5a4166 100644 ---- a/gas/config/loongarch-parse.y -+++ b/gas/config/loongarch-parse.y -@@ -368,24 +368,24 @@ multiplicative_expression - | multiplicative_expression '%' unary_expression {emit_bin ('%');} - ; - --additive_expression -+shift_expression - : multiplicative_expression -- | additive_expression '+' multiplicative_expression {emit_bin ('+');} -- | additive_expression '-' multiplicative_expression {emit_bin ('-');} -+ | shift_expression LEFT_OP multiplicative_expression {emit_bin (LEFT_OP);} -+ | shift_expression RIGHT_OP multiplicative_expression {emit_bin (RIGHT_OP);} - ; - --shift_expression -- : additive_expression -- | shift_expression LEFT_OP additive_expression {emit_bin (LEFT_OP);} -- | shift_expression RIGHT_OP additive_expression {emit_bin (RIGHT_OP);} -+additive_expression -+ : shift_expression -+ | additive_expression '+' shift_expression {emit_bin ('+');} -+ | additive_expression '-' shift_expression {emit_bin ('-');} - ; - - relational_expression -- : shift_expression -- | relational_expression '<' shift_expression {emit_bin ('<');} -- | relational_expression '>' shift_expression {emit_bin ('>');} -- | relational_expression LE_OP shift_expression {emit_bin (LE_OP);} -- | relational_expression GE_OP shift_expression {emit_bin (GE_OP);} -+ : additive_expression -+ | relational_expression '<' additive_expression {emit_bin ('<');} -+ | relational_expression '>' additive_expression {emit_bin ('>');} -+ | relational_expression LE_OP additive_expression {emit_bin (LE_OP);} -+ | relational_expression GE_OP additive_expression {emit_bin (GE_OP);} - ; - - equality_expression -diff --git a/gas/testsuite/gas/loongarch/insn_expr.d b/gas/testsuite/gas/loongarch/insn_expr.d -new file mode 100644 -index 00000000..9abc711a ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/insn_expr.d -@@ -0,0 +1,10 @@ -+#as: -+#objdump: -d -+ -+.*: file format .* -+ -+ -+Disassembly of section \.text: -+ -+0+ <\.text>: -+ 0: 02c00ca4 addi.d \$a0, \$a1, 3 -diff --git a/gas/testsuite/gas/loongarch/insn_expr.s b/gas/testsuite/gas/loongarch/insn_expr.s -new file mode 100644 -index 00000000..3b9ef08a ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/insn_expr.s -@@ -0,0 +1 @@ -+addi.d $a0,$a1,(8 >> 2 + 1) --- -2.33.0 - diff --git a/LoongArch-Force-relocation-for-every-reference-to-th.patch b/LoongArch-Force-relocation-for-every-reference-to-th.patch deleted file mode 100644 index fa036b2..0000000 --- a/LoongArch-Force-relocation-for-every-reference-to-th.patch +++ /dev/null @@ -1,207 +0,0 @@ -From 6be26e106b7a240afce3fa1d8f214ef90ee53bd1 Mon Sep 17 00:00:00 2001 -From: Lulu Cai -Date: Thu, 17 Oct 2024 15:08:47 +0800 -Subject: [PATCH 118/123] LoongArch: Force relocation for every reference to - the global offset table - -Local absolute symbols are resolved at assembly stage and the symbol -value is placed in the relocation addend. But non-zero addend will -cause an assertion failure during linking. - -Forces emission of relocations to defer resolution of local abs symbols -until link time. - -bfd/ - - * elfnn-loongarch.c (loongarch_elf_relax_section): Determine - absolute symbols in advance to avoid ld crash. - -gas/ - - * config/tc-loongarch.c (loongarch_force_relocation): New - function to force relocation. - * config/tc-loongarch.h (TC_FORCE_RELOCATION): New macros - to force relocation. - (loongarch_force_relocation): Function declaration. - * testsuite/gas/loongarch/localpic.d: New test. - * testsuite/gas/loongarch/localpic.s: New test. ---- - bfd/elfnn-loongarch.c | 16 ++++++++-------- - gas/config/tc-loongarch.c | 24 ++++++++++++++++++++++++ - gas/config/tc-loongarch.h | 3 +++ - gas/testsuite/gas/loongarch/localpic.d | 22 ++++++++++++++++++++++ - gas/testsuite/gas/loongarch/localpic.s | 26 ++++++++++++++++++++++++++ - 5 files changed, 83 insertions(+), 8 deletions(-) - create mode 100644 gas/testsuite/gas/loongarch/localpic.d - create mode 100644 gas/testsuite/gas/loongarch/localpic.s - -diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c -index 890233d1..8b9628f7 100644 ---- a/bfd/elfnn-loongarch.c -+++ b/bfd/elfnn-loongarch.c -@@ -5328,7 +5328,6 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, - bfd_vma symval; - asection *sym_sec; - bool local_got = false; -- bool is_abs_symbol = false; - Elf_Internal_Rela *rel = relocs + i; - struct elf_link_hash_entry *h = NULL; - unsigned long r_type = ELFNN_R_TYPE (rel->r_info); -@@ -5434,8 +5433,9 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, - Elf_Internal_Sym *sym = (Elf_Internal_Sym *)symtab_hdr->contents - + r_symndx; - -- if (ELF_ST_TYPE (sym->st_info) == STT_GNU_IFUNC -- && r_type != R_LARCH_CALL36) -+ if ((ELF_ST_TYPE (sym->st_info) == STT_GNU_IFUNC -+ && r_type != R_LARCH_CALL36) -+ || sym->st_shndx == SHN_ABS) - continue; - - /* Only TLS instruction sequences that are accompanied by -@@ -5464,12 +5464,13 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, - symval = sym->st_value; - } - symtype = ELF_ST_TYPE (sym->st_info); -- is_abs_symbol = sym->st_shndx == SHN_ABS; - } - else - { -- if (h != NULL && h->type == STT_GNU_IFUNC -- && r_type != R_LARCH_CALL36) -+ if (h != NULL -+ && ((h->type == STT_GNU_IFUNC -+ && r_type != R_LARCH_CALL36) -+ || bfd_is_abs_section (h->root.u.def.section))) - continue; - - /* The GOT entry of tls symbols must in current execute file or -@@ -5511,7 +5512,6 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, - else - continue; - -- is_abs_symbol = bfd_is_abs_section (h->root.u.def.section); - if (h && LARCH_REF_LOCAL (info, h)) - local_got = true; - symtype = h->type; -@@ -5544,7 +5544,7 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, - - symval += sec_addr (sym_sec); - -- if (r_type == R_LARCH_GOT_PC_HI20 && (!local_got || is_abs_symbol)) -+ if (r_type == R_LARCH_GOT_PC_HI20 && !local_got) - continue; - - if (relax_func (abfd, sec, sym_sec, rel, symval, -diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c -index 046e198f..7fa7fa0f 100644 ---- a/gas/config/tc-loongarch.c -+++ b/gas/config/tc-loongarch.c -@@ -1456,6 +1456,30 @@ md_pcrel_from (fixS *fixP ATTRIBUTE_UNUSED) - return 0; - } - -+/* Return 1 if the relocation must be forced, and 0 if the relocation -+ should never be forced. */ -+int -+loongarch_force_relocation (struct fix *fixp) -+{ -+ /* Ensure we emit a relocation for every reference to the global -+ offset table. */ -+ switch (fixp->fx_r_type) -+ { -+ case BFD_RELOC_LARCH_GOT_PC_HI20: -+ case BFD_RELOC_LARCH_GOT_PC_LO12: -+ case BFD_RELOC_LARCH_GOT64_PC_LO20: -+ case BFD_RELOC_LARCH_GOT64_PC_HI12: -+ case BFD_RELOC_LARCH_GOT_HI20: -+ case BFD_RELOC_LARCH_GOT_LO12: -+ case BFD_RELOC_LARCH_GOT64_LO20: -+ case BFD_RELOC_LARCH_GOT64_HI12: -+ return 1; -+ default: -+ break; -+ } -+ return generic_force_reloc (fixp); -+} -+ - static void fix_reloc_insn (fixS *fixP, bfd_vma reloc_val, char *buf) - { - reloc_howto_type *howto; -diff --git a/gas/config/tc-loongarch.h b/gas/config/tc-loongarch.h -index 2f081edf..da8b0547 100644 ---- a/gas/config/tc-loongarch.h -+++ b/gas/config/tc-loongarch.h -@@ -74,6 +74,9 @@ extern bool loongarch_frag_align_code (int, int); - relaxation, so do not resolve such expressions in the assembler. */ - #define md_allow_local_subtract(l,r,s) 0 - -+#define TC_FORCE_RELOCATION(FIX) loongarch_force_relocation (FIX) -+extern int loongarch_force_relocation (struct fix *); -+ - /* If subsy of BFD_RELOC32/64 and PC in same segment, and without relax - or PC at start of subsy or with relax but sub_symbol_segment not in - SEC_CODE, we generate 32/64_PCREL. */ -diff --git a/gas/testsuite/gas/loongarch/localpic.d b/gas/testsuite/gas/loongarch/localpic.d -new file mode 100644 -index 00000000..bea19578 ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/localpic.d -@@ -0,0 +1,22 @@ -+#as: -+#readelf: -rWs -+#name: loongarch64 local PIC -+ -+Relocation section '.rela.text' at offset 0x[0-9a-f]+ contains 12 entries: -+ Offset Info Type Symbol's Value Symbol's Name \+ Addend -+[0-9a-f]+ [0-9a-f]+ R_LARCH_GOT_PC_HI20 [0-9a-f]+ sym \+ 0 -+[0-9a-f]+ [0-9a-f]+ R_LARCH_GOT_PC_LO12 [0-9a-f]+ sym \+ 0 -+[0-9a-f]+ [0-9a-f]+ R_LARCH_GOT_PC_HI20 [0-9a-f]+ foo \+ 0 -+[0-9a-f]+ [0-9a-f]+ R_LARCH_GOT_PC_LO12 [0-9a-f]+ foo \+ 0 -+[0-9a-f]+ [0-9a-f]+ R_LARCH_GOT64_PC_LO20 [0-9a-f]+ foo \+ 0 -+[0-9a-f]+ [0-9a-f]+ R_LARCH_GOT64_PC_HI12 [0-9a-f]+ foo \+ 0 -+[0-9a-f]+ [0-9a-f]+ R_LARCH_GOT_HI20 [0-9a-f]+ foo \+ 0 -+[0-9a-f]+ [0-9a-f]+ R_LARCH_GOT_LO12 [0-9a-f]+ foo \+ 0 -+[0-9a-f]+ [0-9a-f]+ R_LARCH_GOT_HI20 [0-9a-f]+ sym \+ 0 -+[0-9a-f]+ [0-9a-f]+ R_LARCH_GOT_LO12 [0-9a-f]+ sym \+ 0 -+[0-9a-f]+ [0-9a-f]+ R_LARCH_GOT64_LO20 [0-9a-f]+ sym \+ 0 -+[0-9a-f]+ [0-9a-f]+ R_LARCH_GOT64_HI12 [0-9a-f]+ sym \+ 0 -+#... -+ +[0-9a-f]+: +[0-9a-f]+ 0 NOTYPE LOCAL DEFAULT +[0-9a-f]+ foo -+ +[0-9a-f]+: 0+abba 0 NOTYPE LOCAL DEFAULT ABS sym -+#pass -diff --git a/gas/testsuite/gas/loongarch/localpic.s b/gas/testsuite/gas/loongarch/localpic.s -new file mode 100644 -index 00000000..55548e4b ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/localpic.s -@@ -0,0 +1,26 @@ -+.text -+foo: -+ .quad 0 -+ # 32-bit PC-relative -+ pcalau12i $a0,%got_pc_hi20(sym) -+ ld.d $a0,$a0,%got_pc_lo12(sym) -+ # 64-bit PC-relative -+ pcalau12i $a0,%got_pc_hi20(foo) -+ addi.d $a1,$zero,%got_pc_lo12(foo) -+ lu32i.d $a1,%got64_pc_lo20(foo) -+ lu52i.d $a1,$a1,%got64_pc_hi12(foo) -+ ldx.d $a0,$a0,$a1 -+ -+ # 32-bit absolute -+ lu12i.w $a0,%got_hi20(foo) -+ ori $a0,$a0,%got_lo12(foo) -+ ld.w $a0,$a0,0 -+ -+ #64-bit absolute -+ lu12i.w $a0,%got_hi20(sym) -+ ori $a0,$a0,%got_lo12(sym) -+ lu32i.d $a0,%got64_lo20(sym) -+ lu52i.d $a0,$a0,%got64_hi12(sym) -+ ld.d $a0,$a0,0 -+ -+.set sym,0xabba --- -2.33.0 - diff --git a/LoongArch-GAS-Add-support-for-branch-relaxation.patch b/LoongArch-GAS-Add-support-for-branch-relaxation.patch deleted file mode 100644 index 39c3c48..0000000 --- a/LoongArch-GAS-Add-support-for-branch-relaxation.patch +++ /dev/null @@ -1,529 +0,0 @@ -From f9249a44e8e12e90cf5a49729107f69661ed07ec Mon Sep 17 00:00:00 2001 -From: mengqinggang -Date: Sun, 24 Sep 2023 14:53:28 +0800 -Subject: [PATCH 013/123] LoongArch/GAS: Add support for branch relaxation - -For the instructions of R_LARCH_B16/B21, if the immediate overflow, -add a B instruction and R_LARCH_B26 relocation. - -For example: - -.L1 - ... - blt $t0, $t1, .L1 - R_LARCH_B16 - -change to: - -.L1 - ... - bge $t0, $t1, .L2 - b .L1 - R_LARCH_B26 -.L2 ---- - gas/config/tc-loongarch.c | 236 +++++++++++++++--- - .../gas/loongarch/la_branch_relax_1.d | 64 +++++ - .../gas/loongarch/la_branch_relax_1.s | 33 +++ - .../gas/loongarch/la_branch_relax_2.d | 40 +++ - .../gas/loongarch/la_branch_relax_2.s | 23 ++ - include/opcode/loongarch.h | 12 + - 6 files changed, 367 insertions(+), 41 deletions(-) - create mode 100644 gas/testsuite/gas/loongarch/la_branch_relax_1.d - create mode 100644 gas/testsuite/gas/loongarch/la_branch_relax_1.s - create mode 100644 gas/testsuite/gas/loongarch/la_branch_relax_2.d - create mode 100644 gas/testsuite/gas/loongarch/la_branch_relax_2.s - -diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c -index 4c48382c..059a1711 100644 ---- a/gas/config/tc-loongarch.c -+++ b/gas/config/tc-loongarch.c -@@ -106,6 +106,16 @@ const char *md_shortopts = "O::g::G:"; - - static const char default_arch[] = DEFAULT_ARCH; - -+/* The lowest 4-bit is the bytes of instructions. */ -+#define RELAX_BRANCH_16 0xc0000014 -+#define RELAX_BRANCH_21 0xc0000024 -+#define RELAX_BRANCH_26 0xc0000048 -+ -+#define RELAX_BRANCH(x) \ -+ (((x) & 0xf0000000) == 0xc0000000) -+#define RELAX_BRANCH_ENCODE(x) \ -+ (BFD_RELOC_LARCH_B16 == (x) ? RELAX_BRANCH_16 : RELAX_BRANCH_21) -+ - enum options - { - OPTION_IGNORE = OPTION_MD_BASE, -@@ -955,11 +965,22 @@ append_fixed_insn (struct loongarch_cl_insn *insn) - move_insn (insn, frag_now, f - frag_now->fr_literal); - } - -+/* Add instructions based on the worst-case scenario firstly. */ -+static void -+append_relaxed_branch_insn (struct loongarch_cl_insn *insn, int max_chars, -+ int var, relax_substateT subtype, symbolS *symbol, offsetT offset) -+{ -+ frag_grow (max_chars); -+ move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); -+ frag_var (rs_machine_dependent, max_chars, var, -+ subtype, symbol, offset, NULL); -+} -+ - static void - append_fixp_and_insn (struct loongarch_cl_insn *ip) - { - reloc_howto_type *howto; -- bfd_reloc_code_real_type reloc_type; -+ bfd_reloc_code_real_type r_type; - struct reloc_info *reloc_info = ip->reloc_info; - size_t i; - -@@ -967,14 +988,40 @@ append_fixp_and_insn (struct loongarch_cl_insn *ip) - - for (i = 0; i < ip->reloc_num; i++) - { -- reloc_type = reloc_info[i].type; -- howto = bfd_reloc_type_lookup (stdoutput, reloc_type); -- if (howto == NULL) -- as_fatal (_("no HOWTO loong relocation number %d"), reloc_type); -- -- ip->fixp[i] = -- fix_new_exp (ip->frag, ip->where, bfd_get_reloc_size (howto), -- &reloc_info[i].value, FALSE, reloc_type); -+ r_type = reloc_info[i].type; -+ -+ if (r_type != BFD_RELOC_UNUSED) -+ { -+ -+ gas_assert (&(reloc_info[i].value)); -+ if (BFD_RELOC_LARCH_B16 == r_type || BFD_RELOC_LARCH_B21 == r_type) -+ { -+ int min_bytes = 4; /* One branch instruction. */ -+ unsigned max_bytes = 8; /* Branch and jump instructions. */ -+ -+ if (now_seg == absolute_section) -+ { -+ as_bad (_("relaxable branches not supported in absolute section")); -+ return; -+ } -+ -+ append_relaxed_branch_insn (ip, max_bytes, min_bytes, -+ RELAX_BRANCH_ENCODE (r_type), -+ reloc_info[i].value.X_add_symbol, -+ reloc_info[i].value.X_add_number); -+ return; -+ } -+ else -+ { -+ howto = bfd_reloc_type_lookup (stdoutput, r_type); -+ if (howto == NULL) -+ as_fatal (_("no HOWTO loong relocation number %d"), r_type); -+ -+ ip->fixp[i] = fix_new_exp (ip->frag, ip->where, -+ bfd_get_reloc_size (howto), -+ &reloc_info[i].value, FALSE, r_type); -+ } -+ } - } - - if (ip->insn_length < ip->relax_max_length) -@@ -1489,14 +1536,6 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) - } - } - --int --loongarch_relax_frag (asection *sec ATTRIBUTE_UNUSED, -- fragS *fragp ATTRIBUTE_UNUSED, -- long stretch ATTRIBUTE_UNUSED) --{ -- return 0; --} -- - int - md_estimate_size_before_relax (fragS *fragp ATTRIBUTE_UNUSED, - asection *segtype ATTRIBUTE_UNUSED) -@@ -1528,30 +1567,6 @@ tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) - return reloc; - } - --/* Convert a machine dependent frag. */ --void --md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec ATTRIBUTE_UNUSED, -- fragS *fragp) --{ -- expressionS exp; -- exp.X_op = O_symbol; -- exp.X_add_symbol = fragp->fr_symbol; -- exp.X_add_number = fragp->fr_offset; -- bfd_byte *buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; -- -- fixS *fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, -- 4, &exp, false, fragp->fr_subtype); -- buf += 4; -- -- fixp->fx_file = fragp->fr_file; -- fixp->fx_line = fragp->fr_line; -- fragp->fr_fix += fragp->fr_var; -- -- gas_assert (fragp->fr_next == NULL -- || (fragp->fr_next->fr_address - fragp->fr_address -- == fragp->fr_fix)); --} -- - /* Standard calling conventions leave the CFA at SP on entry. */ - void - loongarch_cfi_frame_initial_instructions (void) -@@ -1777,3 +1792,142 @@ loongarch_elf_final_processing (void) - { - elf_elfheader (stdoutput)->e_flags = LARCH_opts.ase_abi; - } -+ -+/* Compute the length of a branch sequence, and adjust the stored length -+ accordingly. If FRAGP is NULL, the worst-case length is returned. */ -+static unsigned -+loongarch_relaxed_branch_length (fragS *fragp, asection *sec, int update) -+{ -+ int length = 4; -+ -+ if (!fragp) -+ return 8; -+ -+ if (fragp->fr_symbol != NULL -+ && S_IS_DEFINED (fragp->fr_symbol) -+ && !S_IS_WEAK (fragp->fr_symbol) -+ && sec == S_GET_SEGMENT (fragp->fr_symbol)) -+ { -+ offsetT val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; -+ -+ val -= fragp->fr_address + fragp->fr_fix; -+ -+ if (RELAX_BRANCH_16 == fragp->fr_subtype -+ && OUT_OF_RANGE (val, 16, 2)) -+ { -+ length = 8; -+ if (update) -+ fragp->fr_subtype = RELAX_BRANCH_26; -+ } -+ -+ if (RELAX_BRANCH_21 == fragp->fr_subtype -+ && OUT_OF_RANGE (val, 21, 2)) -+ { -+ length = 8; -+ if (update) -+ fragp->fr_subtype = RELAX_BRANCH_26; -+ } -+ -+ if (RELAX_BRANCH_26 == fragp->fr_subtype) -+ length = 8; -+ } -+ -+ return length; -+} -+ -+int -+loongarch_relax_frag (asection *sec ATTRIBUTE_UNUSED, -+ fragS *fragp ATTRIBUTE_UNUSED, -+ long stretch ATTRIBUTE_UNUSED) -+{ -+ if (RELAX_BRANCH (fragp->fr_subtype)) -+ { -+ offsetT old_var = fragp->fr_var; -+ fragp->fr_var = loongarch_relaxed_branch_length (fragp, sec, true); -+ return fragp->fr_var - old_var; -+ } -+ return 0; -+} -+ -+/* Expand far branches to multi-instruction sequences. -+ Branch instructions: -+ beq, bne, blt, bgt, bltz, bgtz, ble, bge, blez, bgez -+ bltu, bgtu, bleu, bgeu -+ beqz, bnez, bceqz, bcnez. */ -+ -+static void -+loongarch_convert_frag_branch (fragS *fragp) -+{ -+ bfd_byte *buf; -+ expressionS exp; -+ fixS *fixp; -+ insn_t insn; -+ -+ buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; -+ -+ exp.X_op = O_symbol; -+ exp.X_add_symbol = fragp->fr_symbol; -+ exp.X_add_number = fragp->fr_offset; -+ -+ gas_assert ((fragp->fr_subtype & 0xf) == fragp->fr_var); -+ -+ /* blt $t0, $t1, .L1 -+ nop -+ change to: -+ bge $t0, $t1, .L2 -+ b .L1 -+ .L2: -+ nop */ -+ switch (fragp->fr_subtype) -+ { -+ case RELAX_BRANCH_26: -+ insn = bfd_getl32 (buf); -+ /* Invert the branch condition. */ -+ if (LARCH_FLOAT_BRANCH == (insn & LARCH_BRANCH_OPCODE_MASK)) -+ insn ^= LARCH_FLOAT_BRANCH_INVERT_BIT; -+ else -+ insn ^= LARCH_BRANCH_INVERT_BIT; -+ insn |= ENCODE_BRANCH16_IMM (8); /* Set target to PC + 8. */ -+ bfd_putl32 (insn, buf); -+ buf += 4; -+ -+ /* Add the B instruction and jump to the original target. */ -+ bfd_putl32 (LARCH_B, buf); -+ fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, -+ 4, &exp, false, BFD_RELOC_LARCH_B26); -+ buf += 4; -+ break; -+ case RELAX_BRANCH_21: -+ fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, -+ 4, &exp, false, BFD_RELOC_LARCH_B21); -+ buf += 4; -+ break; -+ case RELAX_BRANCH_16: -+ fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, -+ 4, &exp, false, BFD_RELOC_LARCH_B16); -+ buf += 4; -+ break; -+ -+ default: -+ abort(); -+ } -+ -+ fixp->fx_file = fragp->fr_file; -+ fixp->fx_line = fragp->fr_line; -+ -+ gas_assert (buf == (bfd_byte *)fragp->fr_literal -+ + fragp->fr_fix + fragp->fr_var); -+ -+ fragp->fr_fix += fragp->fr_var; -+} -+ -+/* Relax a machine dependent frag. This returns the amount by which -+ the current size of the frag should change. */ -+ -+void -+md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec ATTRIBUTE_UNUSED, -+ fragS *fragp) -+{ -+ gas_assert (RELAX_BRANCH (fragp->fr_subtype)); -+ loongarch_convert_frag_branch (fragp); -+} -diff --git a/gas/testsuite/gas/loongarch/la_branch_relax_1.d b/gas/testsuite/gas/loongarch/la_branch_relax_1.d -new file mode 100644 -index 00000000..7984b6df ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/la_branch_relax_1.d -@@ -0,0 +1,64 @@ -+#as: -+#objdump: -dr -+ -+.*:[ ]+file format .* -+ -+ -+Disassembly of section .text: -+ -+0* <.L1>: -+[ ]+... -+[ ]+48d158:[ ]+5c00098d[ ]+bne[ ]+\$t0, \$t1, 8[ ]+# 48d160 <.L1\+0x48d160> -+[ ]+48d15c:[ ]+532ea7ed[ ]+b[ ]+-4772188[ ]+# 0 <.L1> -+[ ]+48d15c: R_LARCH_B26[ ]+.L1 -+[ ]+48d160:[ ]+5800098d[ ]+beq[ ]+\$t0, \$t1, 8[ ]+# 48d168 <.L1\+0x48d168> -+[ ]+48d164:[ ]+532e9fed[ ]+b[ ]+-4772196[ ]+# 0 <.L1> -+[ ]+48d164: R_LARCH_B26[ ]+.L1 -+[ ]+48d168:[ ]+6400098d[ ]+bge[ ]+\$t0, \$t1, 8[ ]+# 48d170 <.L1\+0x48d170> -+[ ]+48d16c:[ ]+532e97ed[ ]+b[ ]+-4772204[ ]+# 0 <.L1> -+[ ]+48d16c: R_LARCH_B26[ ]+.L1 -+[ ]+48d170:[ ]+640009ac[ ]+bge[ ]+\$t1, \$t0, 8[ ]+# 48d178 <.L1\+0x48d178> -+[ ]+48d174:[ ]+532e8fed[ ]+b[ ]+-4772212[ ]+# 0 <.L1> -+[ ]+48d174: R_LARCH_B26[ ]+.L1 -+[ ]+48d178:[ ]+64000980[ ]+bgez[ ]+\$t0, 8[ ]+# 48d180 <.L1\+0x48d180> -+[ ]+48d17c:[ ]+532e87ed[ ]+b[ ]+-4772220[ ]+# 0 <.L1> -+[ ]+48d17c: R_LARCH_B26[ ]+.L1 -+[ ]+48d180:[ ]+6400080c[ ]+blez[ ]+\$t0, 8[ ]+# 48d188 <.L1\+0x48d188> -+[ ]+48d184:[ ]+532e7fed[ ]+b[ ]+-4772228[ ]+# 0 <.L1> -+[ ]+48d184: R_LARCH_B26[ ]+.L1 -+[ ]+48d188:[ ]+600009ac[ ]+blt[ ]+\$t1, \$t0, 8[ ]+# 48d190 <.L1\+0x48d190> -+[ ]+48d18c:[ ]+532e77ed[ ]+b[ ]+-4772236[ ]+# 0 <.L1> -+[ ]+48d18c: R_LARCH_B26[ ]+.L1 -+[ ]+48d190:[ ]+6000098d[ ]+blt[ ]+\$t0, \$t1, 8[ ]+# 48d198 <.L1\+0x48d198> -+[ ]+48d194:[ ]+532e6fed[ ]+b[ ]+-4772244[ ]+# 0 <.L1> -+[ ]+48d194: R_LARCH_B26[ ]+.L1 -+[ ]+48d198:[ ]+6000080c[ ]+bgtz[ ]+\$t0, 8[ ]+# 48d1a0 <.L1\+0x48d1a0> -+[ ]+48d19c:[ ]+532e67ed[ ]+b[ ]+-4772252[ ]+# 0 <.L1> -+[ ]+48d19c: R_LARCH_B26[ ]+.L1 -+[ ]+48d1a0:[ ]+60000980[ ]+bltz[ ]+\$t0, 8[ ]+# 48d1a8 <.L1\+0x48d1a8> -+[ ]+48d1a4:[ ]+532e5fed[ ]+b[ ]+-4772260[ ]+# 0 <.L1> -+[ ]+48d1a4: R_LARCH_B26[ ]+.L1 -+[ ]+48d1a8:[ ]+6c00098d[ ]+bgeu[ ]+\$t0, \$t1, 8[ ]+# 48d1b0 <.L1\+0x48d1b0> -+[ ]+48d1ac:[ ]+532e57ed[ ]+b[ ]+-4772268[ ]+# 0 <.L1> -+[ ]+48d1ac: R_LARCH_B26[ ]+.L1 -+[ ]+48d1b0:[ ]+6c0009ac[ ]+bgeu[ ]+\$t1, \$t0, 8[ ]+# 48d1b8 <.L1\+0x48d1b8> -+[ ]+48d1b4:[ ]+532e4fed[ ]+b[ ]+-4772276[ ]+# 0 <.L1> -+[ ]+48d1b4: R_LARCH_B26[ ]+.L1 -+[ ]+48d1b8:[ ]+680009ac[ ]+bltu[ ]+\$t1, \$t0, 8[ ]+# 48d1c0 <.L1\+0x48d1c0> -+[ ]+48d1bc:[ ]+532e47ed[ ]+b[ ]+-4772284[ ]+# 0 <.L1> -+[ ]+48d1bc: R_LARCH_B26[ ]+.L1 -+[ ]+48d1c0:[ ]+6800098d[ ]+bltu[ ]+\$t0, \$t1, 8[ ]+# 48d1c8 <.L1\+0x48d1c8> -+[ ]+48d1c4:[ ]+532e3fed[ ]+b[ ]+-4772292[ ]+# 0 <.L1> -+[ ]+48d1c4: R_LARCH_B26[ ]+.L1 -+[ ]+48d1c8:[ ]+44000980[ ]+bnez[ ]+\$t0, 8[ ]+# 48d1d0 <.L1\+0x48d1d0> -+[ ]+48d1cc:[ ]+532e37ed[ ]+b[ ]+-4772300[ ]+# 0 <.L1> -+[ ]+48d1cc: R_LARCH_B26[ ]+.L1 -+[ ]+48d1d0:[ ]+40000980[ ]+beqz[ ]+\$t0, 8[ ]+# 48d1d8 <.L1\+0x48d1d8> -+[ ]+48d1d4:[ ]+532e2fed[ ]+b[ ]+-4772308[ ]+# 0 <.L1> -+[ ]+48d1d4: R_LARCH_B26[ ]+.L1 -+[ ]+48d1d8:[ ]+48000900[ ]+bcnez[ ]+\$fcc0, 8[ ]+# 48d1e0 <.L1\+0x48d1e0> -+[ ]+48d1dc:[ ]+532e27ed[ ]+b[ ]+-4772316[ ]+# 0 <.L1> -+[ ]+48d1dc: R_LARCH_B26[ ]+.L1 -+[ ]+48d1e0:[ ]+48000800[ ]+bceqz[ ]+\$fcc0, 8[ ]+# 48d1e8 <.L1\+0x48d1e8> -+[ ]+48d1e4:[ ]+532e1fed[ ]+b[ ]+-4772324[ ]+# 0 <.L1> -+[ ]+48d1e4: R_LARCH_B26[ ]+.L1 -diff --git a/gas/testsuite/gas/loongarch/la_branch_relax_1.s b/gas/testsuite/gas/loongarch/la_branch_relax_1.s -new file mode 100644 -index 00000000..53288f25 ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/la_branch_relax_1.s -@@ -0,0 +1,33 @@ -+# Instruction and Relocation generating tests -+ -+.L1: -+ .fill 0x123456, 4, 0x0 -+ -+# R_LARCH_B16 -+ beq $r12, $r13, .L1 -+ bne $r12, $r13, .L1 -+ -+ blt $r12, $r13, .L1 -+ bgt $r12, $r13, .L1 -+ -+ bltz $r12, .L1 -+ bgtz $r12, .L1 -+ -+ ble $r12, $r13, .L1 -+ bge $r12, $r13, .L1 -+ -+ blez $r12, .L1 -+ bgez $r12, .L1 -+ -+ bltu $r12, $r13, .L1 -+ bgtu $r12, $r13, .L1 -+ -+ bleu $r12, $r13, .L1 -+ bgeu $r12, $r13, .L1 -+ -+# R_LARCH_B21 -+ beqz $r12, .L1 -+ bnez $r12, .L1 -+ -+ bceqz $fcc0, .L1 -+ bcnez $fcc0, .L1 -diff --git a/gas/testsuite/gas/loongarch/la_branch_relax_2.d b/gas/testsuite/gas/loongarch/la_branch_relax_2.d -new file mode 100644 -index 00000000..4a3c6384 ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/la_branch_relax_2.d -@@ -0,0 +1,40 @@ -+#as: -+#objdump: -dr -+ -+.*:[ ]+file format .* -+ -+ -+Disassembly of section .text: -+ -+0* <.L1>: -+[ ]+... -+[ ]+20000:[ ]+5a00018d[ ]+beq[ ]+\$t0, \$t1, -131072[ ]+# 0 <.L1> -+[ ]+20000: R_LARCH_B16[ ]+.L1 -+[ ]+20004:[ ]+5c00098d[ ]+bne[ ]+\$t0, \$t1, 8[ ]+# 2000c <.L1\+0x2000c> -+[ ]+20008:[ ]+51fffbff[ ]+b[ ]+-131080[ ]+# 0 <.L1> -+[ ]+20008: R_LARCH_B26[ ]+.L1 -+[ ]+2000c:[ ]+5c00098d[ ]+bne[ ]+\$t0, \$t1, 8[ ]+# 20014 <.L1\+0x20014> -+[ ]+20010:[ ]+52000000[ ]+b[ ]+131072[ ]+# 40010 <.L2> -+[ ]+20010: R_LARCH_B26[ ]+.L2 -+[ ]+20014:[ ]+59fffd8d[ ]+beq[ ]+\$t0, \$t1, 131068[ ]+# 40010 <.L2> -+[ ]+20014: R_LARCH_B16[ ]+.L2 -+[ ]+... -+0*40010 <.L2>: -+[ ]+... -+[ ]+440010:[ ]+40000190[ ]+beqz[ ]+\$t0, -4194304[ ]+# 40010 <.L2> -+[ ]+440010: R_LARCH_B21[ ]+.L2 -+[ ]+440014:[ ]+44000980[ ]+bnez[ ]+\$t0, 8[ ]+# 44001c <.L2\+0x40000c> -+[ ]+440018:[ ]+53fffbef[ ]+b[ ]+-4194312[ ]+# 40010 <.L2> -+[ ]+440018: R_LARCH_B26[ ]+.L2 -+[ ]+44001c:[ ]+44000980[ ]+bnez[ ]+\$t0, 8[ ]+# 440024 <.L2\+0x400014> -+[ ]+440020:[ ]+50000010[ ]+b[ ]+4194304[ ]+# 840020 <.L3> -+[ ]+440020: R_LARCH_B26[ ]+.L3 -+[ ]+440024:[ ]+43fffd8f[ ]+beqz[ ]+\$t0, 4194300[ ]+# 840020 <.L3> -+[ ]+440024: R_LARCH_B21[ ]+.L3 -+[ ]+... -+0*840020 <.L3>: -+[ ]+840020:[ ]+5800018d[ ]+beq[ ]+\$t0, \$t1, 0[ ]+# 840020 <.L3> -+[ ]+840020: R_LARCH_B16[ ]+.L4 -+0*840024 <.L5>: -+[ ]+840024:[ ]+40000180[ ]+beqz[ ]+\$t0, 0[ ]+# 840024 <.L5> -+[ ]+840024: R_LARCH_B21[ ]+.L5 -diff --git a/gas/testsuite/gas/loongarch/la_branch_relax_2.s b/gas/testsuite/gas/loongarch/la_branch_relax_2.s -new file mode 100644 -index 00000000..3e6c5534 ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/la_branch_relax_2.s -@@ -0,0 +1,23 @@ -+# Immediate boundary value tests -+ -+.L1: -+ .fill 0x8000, 4, 0 -+ beq $r12, $r13, .L1 # min imm -0x20000 -+ beq $r12, $r13, .L1 # out of range -+ beq $r12, $r13, .L2 # out of range -+ beq $r12, $r13, .L2 # max imm 0x1fffc -+ .fill 0x7ffe, 4, 0 -+.L2: -+ .fill 0x100000, 4, 0 -+ beqz $r12, .L2 # min imm -0x400000 -+ beqz $r12, .L2 # out of range -+ beqz $r12, .L3 # out of range -+ beqz $r12, .L3 # max imm 0x3ffffc -+ .fill 0xffffe, 4, 0 -+.L3: -+ -+# 0 imm -+.L4: -+ beq $r12, $r13, .L4 -+.L5: -+ beqz $r12, .L5 -diff --git a/include/opcode/loongarch.h b/include/opcode/loongarch.h -index 2ed4082c..f358ff42 100644 ---- a/include/opcode/loongarch.h -+++ b/include/opcode/loongarch.h -@@ -29,6 +29,18 @@ extern "C" - #endif - - #define LARCH_NOP 0x03400000 -+ #define LARCH_B 0x50000000 -+ /* BCEQZ/BCNEZ. */ -+ #define LARCH_FLOAT_BRANCH 0x48000000 -+ #define LARCH_BRANCH_OPCODE_MASK 0xfc000000 -+ #define LARCH_BRANCH_INVERT_BIT 0x04000000 -+ #define LARCH_FLOAT_BRANCH_INVERT_BIT 0x00000100 -+ -+ #define ENCODE_BRANCH16_IMM(x) (((x) >> 2) << 10) -+ -+ #define OUT_OF_RANGE(value, bits, align) \ -+ ((value) < (-(1 << ((bits) - 1) << align)) \ -+ || (value) > ((((1 << ((bits) - 1)) - 1) << align))) - - typedef uint32_t insn_t; - --- -2.33.0 - diff --git a/LoongArch-LoongArch64-allows-relocations-to-use-64-b.patch b/LoongArch-LoongArch64-allows-relocations-to-use-64-b.patch deleted file mode 100644 index ddb0c0a..0000000 --- a/LoongArch-LoongArch64-allows-relocations-to-use-64-b.patch +++ /dev/null @@ -1,65 +0,0 @@ -From 87c63c08d6171b556f86c14fded00ab8b4aaa73b Mon Sep 17 00:00:00 2001 -From: Lulu Cai -Date: Wed, 7 Aug 2024 18:04:26 +0800 -Subject: [PATCH 110/123] LoongArch: LoongArch64 allows relocations to use - 64-bit addends - -Relocations using 64-bit addends allow larger constant offset address -calculations to be fused. ---- - gas/config/tc-loongarch.c | 3 +++ - gas/testsuite/gas/loongarch/large_addend.d | 12 ++++++++++++ - gas/testsuite/gas/loongarch/large_addend.s | 8 ++++++++ - 3 files changed, 23 insertions(+) - create mode 100644 gas/testsuite/gas/loongarch/large_addend.d - create mode 100644 gas/testsuite/gas/loongarch/large_addend.s - -diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c -index 72815233..16355cac 100644 ---- a/gas/config/tc-loongarch.c -+++ b/gas/config/tc-loongarch.c -@@ -1221,6 +1221,9 @@ append_fixp_and_insn (struct loongarch_cl_insn *ip) - bfd_get_reloc_size (howto), - &reloc_info[i].value, FALSE, r_type); - } -+ /* Allow LoongArch 64 to use 64-bit addends. */ -+ if (LARCH_opts.ase_lp64) -+ ip->fixp[i]->fx_no_overflow = 1; - } - } - -diff --git a/gas/testsuite/gas/loongarch/large_addend.d b/gas/testsuite/gas/loongarch/large_addend.d -new file mode 100644 -index 00000000..18eb33a3 ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/large_addend.d -@@ -0,0 +1,12 @@ -+#as: -+#objdump: -r -+#skip: loongarch32-*-* -+ -+.*: file format elf64-loongarch -+ -+RELOCATION RECORDS FOR \[\.text\]: -+OFFSET TYPE VALUE -+0000000000000000 R_LARCH_PCALA_HI20 _start\+0x7fffabcd12345678 -+0000000000000004 R_LARCH_PCALA_LO12 _start\+0x7fffabcd12345678 -+0000000000000008 R_LARCH_PCALA64_LO20 _start\+0x7fffabcd12345678 -+000000000000000c R_LARCH_PCALA64_HI12 _start\+0x7fffabcd12345678 -diff --git a/gas/testsuite/gas/loongarch/large_addend.s b/gas/testsuite/gas/loongarch/large_addend.s -new file mode 100644 -index 00000000..7db90525 ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/large_addend.s -@@ -0,0 +1,8 @@ -+ .text -+ .global _start -+_start: -+ pcalau12i $a0, %pc_hi20(_start+0x7fffabcd12345678) -+ addi.d $a1, $zero, %pc_lo12(_start+0x7fffabcd12345678) -+ lu32i.d $a1, %pc64_lo20(_start+0x7fffabcd12345678) -+ lu52i.d $a1, $a1, %pc64_hi12(_start+0x7fffabcd12345678) -+ add.d $a0, $a1, $a0 --- -2.33.0 - diff --git a/LoongArch-Make-align-symbol-be-in-same-section-with-.patch b/LoongArch-Make-align-symbol-be-in-same-section-with-.patch deleted file mode 100644 index 1f10592..0000000 --- a/LoongArch-Make-align-symbol-be-in-same-section-with-.patch +++ /dev/null @@ -1,303 +0,0 @@ -From ea14dbe723a67501b377bf6d4f390ca4b6a58938 Mon Sep 17 00:00:00 2001 -From: mengqinggang -Date: Wed, 29 May 2024 14:50:39 +0800 -Subject: [PATCH 089/123] LoongArch: Make align symbol be in same section with - alignment directive - -R_LARCH_ALIGN (psABI v2.30) requires a symbol index. The symbol is only -created at the first time to handle alignment directive. This means that -all other sections may use this symbol. If the section of this symbol is -discarded, there may be problems. Search it in its own section. - -Remove elf_backend_data.is_rela_normal() function added at commit daeda14191c. - -Co-authored-by: Jinyang He -Reported-by: WANG Xuerui -Link: https://lore.kernel.org/loongarch/2abbb633-a10e-71cc-a5e1-4d9e39074066@loongson.cn/T/#t ---- - bfd/elf-bfd.h | 4 -- - bfd/elflink.c | 5 +- - bfd/elfnn-loongarch.c | 16 ------ - bfd/elfxx-target.h | 5 -- - gas/config/tc-loongarch.c | 63 +++++++++++++++++++++- - gas/config/tc-loongarch.h | 3 ++ - gas/testsuite/gas/loongarch/relax-align2.d | 24 +++++++++ - gas/testsuite/gas/loongarch/relax-align2.s | 11 ++++ - gas/testsuite/gas/loongarch/relax_align.d | 6 +-- - 9 files changed, 104 insertions(+), 33 deletions(-) - create mode 100644 gas/testsuite/gas/loongarch/relax-align2.d - create mode 100644 gas/testsuite/gas/loongarch/relax-align2.s - -diff --git a/bfd/elf-bfd.h b/bfd/elf-bfd.h -index 074120a5..ec856764 100644 ---- a/bfd/elf-bfd.h -+++ b/bfd/elf-bfd.h -@@ -1703,10 +1703,6 @@ struct elf_backend_data - backend relocate_section routine for relocatable linking. */ - unsigned rela_normal : 1; - -- /* Whether a relocation is rela_normal. Compared with rela_normal, -- is_rela_normal can set part of relocations to rela_normal. */ -- bool (*is_rela_normal) (Elf_Internal_Rela *); -- - /* Set if DT_REL/DT_RELA/DT_RELSZ/DT_RELASZ should not include PLT - relocations. */ - unsigned dtrel_excludes_plt : 1; -diff --git a/bfd/elflink.c b/bfd/elflink.c -index cbf87d70..7217c2f0 100644 ---- a/bfd/elflink.c -+++ b/bfd/elflink.c -@@ -11647,10 +11647,7 @@ elf_link_input_bfd (struct elf_final_link_info *flinfo, bfd *input_bfd) - { - rel_hash = PTR_ADD (esdo->rela.hashes, esdo->rela.count); - rela_hash_list = rel_hash; -- if (bed->is_rela_normal != NULL) -- rela_normal = bed->is_rela_normal (irela); -- else -- rela_normal = bed->rela_normal; -+ rela_normal = bed->rela_normal; - } - - irela->r_offset = _bfd_elf_section_offset (output_bfd, -diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c -index eb572a77..9eaad7f4 100644 ---- a/bfd/elfnn-loongarch.c -+++ b/bfd/elfnn-loongarch.c -@@ -5527,21 +5527,6 @@ elf_loongarch64_hash_symbol (struct elf_link_hash_entry *h) - return _bfd_elf_hash_symbol (h); - } - --/* If a relocation is rela_normal and the symbol associated with the -- relocation is STT_SECTION type, the addend of the relocation would add -- sec->output_offset when partial linking (ld -r). -- See elf_backend_data.rela_normal and elf_link_input_bfd(). -- The addend of R_LARCH_ALIGN is used to represent the first and third -- expression of .align, it should be a constant when linking. */ -- --static bool --loongarch_elf_is_rela_normal (Elf_Internal_Rela *rel) --{ -- if (R_LARCH_ALIGN == ELFNN_R_TYPE (rel->r_info)) -- return false; -- return true; --} -- - #define TARGET_LITTLE_SYM loongarch_elfNN_vec - #define TARGET_LITTLE_NAME "elfNN-loongarch" - #define ELF_ARCH bfd_arch_loongarch -@@ -5577,7 +5562,6 @@ loongarch_elf_is_rela_normal (Elf_Internal_Rela *rel) - #define elf_backend_grok_psinfo loongarch_elf_grok_psinfo - #define elf_backend_hash_symbol elf_loongarch64_hash_symbol - #define bfd_elfNN_bfd_relax_section loongarch_elf_relax_section --#define elf_backend_is_rela_normal loongarch_elf_is_rela_normal - - #define elf_backend_dtrel_excludes_plt 1 - -diff --git a/bfd/elfxx-target.h b/bfd/elfxx-target.h -index 385e40b7..f8553006 100644 ---- a/bfd/elfxx-target.h -+++ b/bfd/elfxx-target.h -@@ -703,10 +703,6 @@ - #define elf_backend_rela_normal 0 - #endif - --#ifndef elf_backend_is_rela_normal --#define elf_backend_is_rela_normal NULL --#endif -- - #ifndef elf_backend_dtrel_excludes_plt - #define elf_backend_dtrel_excludes_plt 0 - #endif -@@ -952,7 +948,6 @@ static const struct elf_backend_data elfNN_bed = - elf_backend_default_use_rela_p, - elf_backend_rela_plts_and_copies_p, - elf_backend_rela_normal, -- elf_backend_is_rela_normal, - elf_backend_dtrel_excludes_plt, - elf_backend_sign_extend_vma, - elf_backend_want_got_plt, -diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c -index f030fd07..f039d027 100644 ---- a/gas/config/tc-loongarch.c -+++ b/gas/config/tc-loongarch.c -@@ -419,6 +419,55 @@ loongarch_target_format () - return LARCH_opts.ase_lp64 ? "elf64-loongarch" : "elf32-loongarch"; - } - -+typedef struct -+{ -+ unsigned int sec_id; -+ symbolS *s; -+} align_sec_sym; -+ -+static htab_t align_hash; -+ -+static hashval_t -+align_sec_sym_hash (const void *entry) -+{ -+ const align_sec_sym *e = entry; -+ return (hashval_t) (e->sec_id); -+} -+ -+static int -+align_sec_sym_eq (const void *entry1, const void *entry2) -+{ -+ const align_sec_sym *e1 = entry1, *e2 = entry2; -+ return e1->sec_id == e2->sec_id; -+} -+ -+/* Make align symbol be in same section with alignment directive. -+ If the symbol is only created at the first time to handle alignment -+ directive. This means that all other sections may use this symbol. -+ If the section of this symbol is discarded, there may be problems. */ -+ -+static symbolS *get_align_symbol (segT sec) -+{ -+ align_sec_sym search = { sec->id, NULL }; -+ align_sec_sym *pentry = htab_find (align_hash, &search); -+ if (pentry) -+ return pentry->s; -+ -+ /* If we not find the symbol in this section. Create and insert it. */ -+ symbolS *s = (symbolS *)local_symbol_make (".Lla-relax-align", sec, -+ &zero_address_frag, 0); -+ align_sec_sym entry = { sec->id, s }; -+ align_sec_sym **slot = (align_sec_sym **) htab_find_slot (align_hash, -+ &entry, INSERT); -+ if (slot == NULL) -+ return NULL; -+ *slot = (align_sec_sym *) xmalloc (sizeof (align_sec_sym)); -+ if (*slot == NULL) -+ return NULL; -+ **slot = entry; -+ return entry.s; -+} -+ - void - md_begin () - { -@@ -440,11 +489,21 @@ md_begin () - it->name, it->format, it->macro); - } - -+ align_hash = htab_create (10, align_sec_sym_hash, align_sec_sym_eq, free); -+ - /* FIXME: expressionS use 'offsetT' as constant, - * we want this is 64-bit type. */ - assert (8 <= sizeof (offsetT)); - } - -+/* Called just before the assembler exits. */ -+ -+void -+loongarch_md_end (void) -+{ -+ htab_delete (align_hash); -+} -+ - unsigned long - loongarch_mach (void) - { -@@ -1826,7 +1885,9 @@ loongarch_frag_align_code (int n, int max) - if (fragP->fr_subtype != 0 && offset > fragP->fr_subtype). */ - if (align_max) - { -- s = symbol_find (now_seg->name); -+ s = get_align_symbol (now_seg); -+ if (!s) -+ as_fatal (_("internal error: cannot get align symbol")); - addend = ALIGN_MAX_ADDEND (n, max); - } - -diff --git a/gas/config/tc-loongarch.h b/gas/config/tc-loongarch.h -index 6963867e..05c0af45 100644 ---- a/gas/config/tc-loongarch.h -+++ b/gas/config/tc-loongarch.h -@@ -32,6 +32,9 @@ extern unsigned long loongarch_mach (void); - #define WORKING_DOT_WORD 1 - #define REPEAT_CONS_EXPRESSIONS - -+#define md_end loongarch_md_end -+extern void loongarch_md_end (void); -+ - /* Early than md_begin. */ - #define md_after_parse_args loongarch_after_parse_args - extern void loongarch_after_parse_args (void); -diff --git a/gas/testsuite/gas/loongarch/relax-align2.d b/gas/testsuite/gas/loongarch/relax-align2.d -new file mode 100644 -index 00000000..cbef84f8 ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/relax-align2.d -@@ -0,0 +1,24 @@ -+#as: --no-warn -+#readelf: -rsW -+#skip: loongarch32-*-* -+ -+Relocation section '\.rela\.text' at offset .* contains 2 entries: -+.* -+0+04[ ]+0000000000000066[ ]+R_LARCH_ALIGN[ ]+c -+0+14[ ]+0000000500000066[ ]+R_LARCH_ALIGN[ ]+0+[ ]+\.Lla-relax-align \+ 404 -+ -+Relocation section '\.rela\.text2' at offset .* contains 2 entries: -+.* -+0+04[ ]+0000000000000066[ ]+R_LARCH_ALIGN[ ]+c -+0+14[ ]+0000000600000066[ ]+R_LARCH_ALIGN[ ]+0+[ ]+\.Lla-relax-align \+ 404 -+ -+Symbol table '\.symtab' contains .* entries: -+#... -+[ ]+.*:[ ]+0+[ ]+0[ ]+SECTION[ ]+LOCAL[ ]+DEFAULT[ ]+1[ ]+\.text -+#... -+[ ]+.*:[ ]+0+[ ]+0[ ]+SECTION[ ]+LOCAL[ ]+DEFAULT[ ]+5[ ]+\.text2 -+#... -+[ ]+.*:[ ]+0+[ ]+0[ ]+NOTYPE[ ]+LOCAL[ ]+DEFAULT[ ]+1[ ]+\.Lla-relax-align -+#... -+[ ]+.*:[ ]+0+[ ]+0[ ]+NOTYPE[ ]+LOCAL[ ]+DEFAULT[ ]+5[ ]+\.Lla-relax-align -+#pass -diff --git a/gas/testsuite/gas/loongarch/relax-align2.s b/gas/testsuite/gas/loongarch/relax-align2.s -new file mode 100644 -index 00000000..6cd6bd87 ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/relax-align2.s -@@ -0,0 +1,11 @@ -+.section ".text", "ax" -+nop -+.align 4 -+nop -+.align 4, , 4 -+ -+.section ".text2", "ax" -+nop -+.align 4 -+nop -+.align 4, , 4 -diff --git a/gas/testsuite/gas/loongarch/relax_align.d b/gas/testsuite/gas/loongarch/relax_align.d -index acd215a4..fc1fd032 100644 ---- a/gas/testsuite/gas/loongarch/relax_align.d -+++ b/gas/testsuite/gas/loongarch/relax_align.d -@@ -7,7 +7,7 @@ - - Disassembly of section .text: - --[ ]*0000000000000000 <.text>: -+[ ]*0000000000000000 <.Lla-relax-align>: - [ ]+0:[ ]+4c000020[ ]+ret - [ ]+4:[ ]+03400000[ ]+nop - [ ]+4: R_LARCH_ALIGN[ ]+\*ABS\*\+0xc -@@ -20,12 +20,12 @@ Disassembly of section .text: - [ ]+1c:[ ]+03400000[ ]+nop - [ ]+20:[ ]+4c000020[ ]+ret - [ ]+24:[ ]+03400000[ ]+nop --[ ]+24: R_LARCH_ALIGN[ ]+.text\+0x104 -+[ ]+24: R_LARCH_ALIGN[ ]+.Lla-relax-align\+0x104 - [ ]+28:[ ]+03400000[ ]+nop - [ ]+2c:[ ]+03400000[ ]+nop - [ ]+30:[ ]+4c000020[ ]+ret - [ ]+34:[ ]+03400000[ ]+nop --[ ]+34: R_LARCH_ALIGN[ ]+.text\+0xb04 -+[ ]+34: R_LARCH_ALIGN[ ]+.Lla-relax-align\+0xb04 - [ ]+38:[ ]+03400000[ ]+nop - [ ]+3c:[ ]+03400000[ ]+nop - [ ]+40:[ ]+4c000020[ ]+ret --- -2.33.0 - diff --git a/LoongArch-Make-protected-function-symbols-local-for-.patch b/LoongArch-Make-protected-function-symbols-local-for-.patch deleted file mode 100644 index 7e024e2..0000000 --- a/LoongArch-Make-protected-function-symbols-local-for-.patch +++ /dev/null @@ -1,311 +0,0 @@ -From a95555b83c866216189dde969ab7b76ebd57c60c Mon Sep 17 00:00:00 2001 -From: Xi Ruoyao -Date: Sun, 30 Jun 2024 15:18:23 +0800 -Subject: [PATCH 097/123] LoongArch: Make protected function symbols local for - -shared - -On LoongArch there is no reason to treat STV_PROTECTED STT_FUNC symbols -as preemptible. See the comment above LARCH_REF_LOCAL for detailed -explanation. - -Signed-off-by: Xi Ruoyao ---- - bfd/elfnn-loongarch.c | 76 ++++++++++++++----- - ld/testsuite/ld-loongarch-elf/ifunc-reloc.d | 2 +- - .../ld-loongarch-elf/ld-loongarch-elf.exp | 1 + - .../ld-loongarch-elf/protected-func.d | 6 ++ - .../ld-loongarch-elf/protected-func.s | 17 +++++ - 5 files changed, 81 insertions(+), 21 deletions(-) - create mode 100644 ld/testsuite/ld-loongarch-elf/protected-func.d - create mode 100644 ld/testsuite/ld-loongarch-elf/protected-func.s - -diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c -index 6b1a4ecc..2bdd7be2 100644 ---- a/bfd/elfnn-loongarch.c -+++ b/bfd/elfnn-loongarch.c -@@ -181,6 +181,44 @@ struct loongarch_elf_link_hash_table - } \ - while (0) - -+/* TL;DR always use it in this file instead when you want to type -+ SYMBOL_REFERENCES_LOCAL. -+ -+ It's like SYMBOL_REFERENCES_LOCAL, but it returns true for local -+ protected functions. It happens to be same as SYMBOL_CALLS_LOCAL but -+ let's not reuse SYMBOL_CALLS_LOCAL or "CALLS" may puzzle people. -+ -+ We do generate a PLT entry when someone attempts to la.pcrel an external -+ function. But we never really implemented "R_LARCH_COPY", thus we've -+ never supported la.pcrel an external symbol unless the loaded address is -+ only used for locating a function to be called. Thus the PLT entry is -+ a normal PLT entry, not intended to be a so-called "canonical PLT entry" -+ on the ports supporting copy relocation. So attempting to la.pcrel an -+ external function will just break pointer equality, even it's a -+ STV_DEFAULT function: -+ -+ $ cat t.c -+ #include -+ void check(void *p) {assert(p == check);} -+ $ cat main.c -+ extern void check(void *); -+ int main(void) { check(check); } -+ $ cc t.c -fPIC -shared -o t.so -+ $ cc main.c -mdirect-extern-access t.so -Wl,-rpath=. -fpie -pie -+ $ ./a.out -+ a.out: t.c:2: check: Assertion `p == check' failed. -+ Aborted -+ -+ Thus handling STV_PROTECTED function specially just fixes nothing: -+ adding -fvisibility=protected compiling t.c will not magically fix -+ the inequality. The only possible and correct fix is not to use -+ -mdirect-extern-access. -+ -+ So we should remove this special handling, because it's only an -+ unsuccessful workaround for invalid code and it's penalizing valid -+ code. */ -+#define LARCH_REF_LOCAL(info, h) \ -+ (_bfd_elf_symbol_refs_local_p ((h), (info), true)) - - /* Generate a PLT header. */ - -@@ -712,7 +750,7 @@ loongarch_tls_transition_without_check (struct bfd_link_info *info, - struct elf_link_hash_entry *h) - { - bool local_exec = bfd_link_executable (info) -- && SYMBOL_REFERENCES_LOCAL (info, h); -+ && LARCH_REF_LOCAL (info, h); - - switch (r_type) - { -@@ -1221,7 +1259,7 @@ loongarch_elf_adjust_dynamic_symbol (struct bfd_link_info *info, - { - if (h->plt.refcount <= 0 - || (h->type != STT_GNU_IFUNC -- && (SYMBOL_REFERENCES_LOCAL (info, h) -+ && (LARCH_REF_LOCAL (info, h) - || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT - && h->root.type == bfd_link_hash_undefweak)))) - { -@@ -1739,14 +1777,14 @@ elfNN_allocate_ifunc_dynrelocs (struct elf_link_hash_entry *h, - here if it is defined and referenced in a non-shared object. */ - if (h->type == STT_GNU_IFUNC && h->def_regular) - { -- if (ref_local && SYMBOL_REFERENCES_LOCAL (info, h)) -+ if (ref_local && LARCH_REF_LOCAL (info, h)) - return local_allocate_ifunc_dyn_relocs (info, h, - &h->dyn_relocs, - PLT_ENTRY_SIZE, - PLT_HEADER_SIZE, - GOT_ENTRY_SIZE, - false); -- else if (!ref_local && !SYMBOL_REFERENCES_LOCAL (info, h)) -+ else if (!ref_local && !LARCH_REF_LOCAL (info, h)) - return _bfd_elf_allocate_ifunc_dyn_relocs (info, h, - &h->dyn_relocs, - PLT_ENTRY_SIZE, -@@ -1774,7 +1812,6 @@ elfNN_allocate_ifunc_dynrelocs_ref_global (struct elf_link_hash_entry *h, - false); - } - -- - /* Allocate space in .plt, .got and associated reloc sections for - ifunc dynamic relocs. */ - -@@ -2686,7 +2723,6 @@ tlsoff (struct bfd_link_info *info, bfd_vma addr) - return addr - elf_hash_table (info)->tls_sec->vma; - } - -- - static int - loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, - bfd *input_bfd, asection *input_section, -@@ -2812,7 +2848,7 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, - { - defined_local = !unresolved_reloc && !ignored; - resolved_local = -- defined_local && SYMBOL_REFERENCES_LOCAL (info, h); -+ defined_local && LARCH_REF_LOCAL (info, h); - resolved_dynly = !resolved_local; - resolved_to_const = !resolved_local && !resolved_dynly; - } -@@ -2901,7 +2937,7 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, - outrel.r_addend = 0; - } - -- if (SYMBOL_REFERENCES_LOCAL (info, h)) -+ if (LARCH_REF_LOCAL (info, h)) - { - - if (htab->elf.splt != NULL) -@@ -3251,7 +3287,7 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, - if (!WILL_CALL_FINISH_DYNAMIC_SYMBOL (is_dyn, - bfd_link_pic (info), h) - && ((bfd_link_pic (info) -- && SYMBOL_REFERENCES_LOCAL (info, h)))) -+ && LARCH_REF_LOCAL (info, h)))) - { - /* This is actually a static link, or it is a - -Bsymbolic link and the symbol is defined -@@ -3396,7 +3432,7 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, - asection *srel = htab->elf.srelgot; - bfd_vma tls_block_off = 0; - -- if (SYMBOL_REFERENCES_LOCAL (info, h)) -+ if (LARCH_REF_LOCAL (info, h)) - { - BFD_ASSERT (elf_hash_table (info)->tls_sec); - tls_block_off = relocation -@@ -3407,7 +3443,7 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, - { - rela.r_offset = sec_addr (got) + got_off; - rela.r_addend = 0; -- if (SYMBOL_REFERENCES_LOCAL (info, h)) -+ if (LARCH_REF_LOCAL (info, h)) - { - /* Local sym, used in exec, set module id 1. */ - if (bfd_link_executable (info)) -@@ -3440,7 +3476,7 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, - if (tls_type & GOT_TLS_IE) - { - rela.r_offset = sec_addr (got) + got_off + ie_off; -- if (SYMBOL_REFERENCES_LOCAL (info, h)) -+ if (LARCH_REF_LOCAL (info, h)) - { - /* Local sym, used in exec, set module id 1. */ - if (!bfd_link_executable (info)) -@@ -3642,7 +3678,7 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, - bfd_link_pic (info), - h) - && bfd_link_pic (info) -- && SYMBOL_REFERENCES_LOCAL (info, h)) -+ && LARCH_REF_LOCAL (info, h)) - { - Elf_Internal_Rela rela; - rela.r_offset = sec_addr (got) + got_off; -@@ -4183,7 +4219,7 @@ loongarch_tls_perform_trans (bfd *abfd, asection *sec, - { - unsigned long insn; - bool local_exec = bfd_link_executable (info) -- && SYMBOL_REFERENCES_LOCAL (info, h); -+ && LARCH_REF_LOCAL (info, h); - bfd_byte *contents = elf_section_data (sec)->this_hdr.contents; - unsigned long r_type = ELFNN_R_TYPE (rel->r_info); - unsigned long r_symndx = ELFNN_R_SYM (rel->r_info); -@@ -4895,7 +4931,7 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, - else - continue; - -- if (h && SYMBOL_REFERENCES_LOCAL (info, h)) -+ if (h && LARCH_REF_LOCAL (info, h)) - local_got = true; - symtype = h->type; - } -@@ -5032,12 +5068,12 @@ loongarch_elf_finish_dynamic_symbol (bfd *output_bfd, - if (htab->elf.splt) - { - BFD_ASSERT ((h->type == STT_GNU_IFUNC -- && SYMBOL_REFERENCES_LOCAL (info, h)) -+ && LARCH_REF_LOCAL (info, h)) - || h->dynindx != -1); - - plt = htab->elf.splt; - gotplt = htab->elf.sgotplt; -- if (h->type == STT_GNU_IFUNC && SYMBOL_REFERENCES_LOCAL (info, h)) -+ if (h->type == STT_GNU_IFUNC && LARCH_REF_LOCAL (info, h)) - relplt = htab->elf.srelgot; - else - relplt = htab->elf.srelplt; -@@ -5048,7 +5084,7 @@ loongarch_elf_finish_dynamic_symbol (bfd *output_bfd, - else /* if (htab->elf.iplt) */ - { - BFD_ASSERT (h->type == STT_GNU_IFUNC -- && SYMBOL_REFERENCES_LOCAL (info, h)); -+ && LARCH_REF_LOCAL (info, h)); - - plt = htab->elf.iplt; - gotplt = htab->elf.igotplt; -@@ -5136,7 +5172,7 @@ loongarch_elf_finish_dynamic_symbol (bfd *output_bfd, - if (htab->elf.splt == NULL) - srela = htab->elf.irelplt; - -- if (SYMBOL_REFERENCES_LOCAL (info, h)) -+ if (LARCH_REF_LOCAL (info, h)) - { - asection *sec = h->root.u.def.section; - rela.r_info = ELFNN_R_INFO (0, R_LARCH_IRELATIVE); -@@ -5173,7 +5209,7 @@ loongarch_elf_finish_dynamic_symbol (bfd *output_bfd, - return true; - } - } -- else if (bfd_link_pic (info) && SYMBOL_REFERENCES_LOCAL (info, h)) -+ else if (bfd_link_pic (info) && LARCH_REF_LOCAL (info, h)) - { - asection *sec = h->root.u.def.section; - rela.r_info = ELFNN_R_INFO (0, R_LARCH_RELATIVE); -diff --git a/ld/testsuite/ld-loongarch-elf/ifunc-reloc.d b/ld/testsuite/ld-loongarch-elf/ifunc-reloc.d -index cb592874..968e7564 100644 ---- a/ld/testsuite/ld-loongarch-elf/ifunc-reloc.d -+++ b/ld/testsuite/ld-loongarch-elf/ifunc-reloc.d -@@ -8,6 +8,7 @@ - .* R_LARCH_IRELATIVE .* - .* R_LARCH_IRELATIVE .* - .* R_LARCH_IRELATIVE .* -+.* R_LARCH_IRELATIVE .* - #... - .*'\.rela\.plt'.* - #... -@@ -16,4 +17,3 @@ - .* R_LARCH_JUMP_SLOT .* - .* R_LARCH_JUMP_SLOT .* - .* R_LARCH_JUMP_SLOT .* --.* R_LARCH_JUMP_SLOT .* -diff --git a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -index 506dac3e..30d7bc03 100644 ---- a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -+++ b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -@@ -134,6 +134,7 @@ if [istarget "loongarch64-*-*"] { - run_dump_test "reloc_abs_with_shared" - run_dump_test "r_larch_32_elf64" - run_dump_test "ifunc-reloc" -+ run_dump_test "protected-func" - } - - if [check_pie_support] { -diff --git a/ld/testsuite/ld-loongarch-elf/protected-func.d b/ld/testsuite/ld-loongarch-elf/protected-func.d -new file mode 100644 -index 00000000..501c7cb5 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/protected-func.d -@@ -0,0 +1,6 @@ -+#ld: -shared -+#readelf: -Wr -+ -+#... -+.* R_LARCH_RELATIVE .* -+.* R_LARCH_RELATIVE .* -diff --git a/ld/testsuite/ld-loongarch-elf/protected-func.s b/ld/testsuite/ld-loongarch-elf/protected-func.s -new file mode 100644 -index 00000000..8f28f925 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/protected-func.s -@@ -0,0 +1,17 @@ -+# protected function should be non-preemptible and relocated with -+# R_LARCH_RELATIVE in shared library, for both GOT and pointer data -+ -+.globl x -+.protected x -+.type x, @function -+x: -+ ret -+ -+.globl _start -+_start: -+ la.got $a0, x -+ ret -+ -+.data -+p: -+ .quad x --- -2.33.0 - diff --git a/LoongArch-Modify-inconsistent-behavior-of-ld-with-un.patch b/LoongArch-Modify-inconsistent-behavior-of-ld-with-un.patch deleted file mode 100644 index 2b2d75e..0000000 --- a/LoongArch-Modify-inconsistent-behavior-of-ld-with-un.patch +++ /dev/null @@ -1,60 +0,0 @@ -From 268391acb9fa956bad24533e2cc0d1459dea1b3d Mon Sep 17 00:00:00 2001 -From: ticat_fp -Date: Mon, 26 Feb 2024 11:11:35 +0800 -Subject: [PATCH] LoongArch: Modify inconsistent behavior of ld with - --unresolved-symbols=ignore-all - -Remove duplicated check when producing executable files that reference external symbols -defined in other files. RELOC_FOR_GLOBAL_SYMBOL will check it. - -Testcase is: -resolv.c: -int main(int argc, char *argv[]) { - return argc; -} - -t.c: - -extern const struct my_struct ms1; -static const struct my_struct *ms = &ms1; - -t.h: -typedef struct my_struct { - char *str; - int i; -} my_struct; - -Compiling and linking command with: -gcc t.c -c ; gcc resolv.c -c -gcc resolv.o t.o -o resolv -Wl,--unresolved-symbols=ignore-all - -Got error as: -~/install/usr/bin/ld: t.o:(.data.rel+0x0): undefined reference to `ms1' -collect2: error: ld returned 1 exit status ---- - bfd/elfnn-loongarch.c | 9 +-------- - 1 file changed, 1 insertion(+), 8 deletions(-) - -diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c -index 1b5009e13b2..e96e0f53608 100644 ---- a/bfd/elfnn-loongarch.c -+++ b/bfd/elfnn-loongarch.c -@@ -2868,14 +2868,7 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, - else if (resolved_dynly) - { - if (h->dynindx == -1) -- { -- if (h->root.type == bfd_link_hash_undefined) -- (*info->callbacks->undefined_symbol) -- (info, name, input_bfd, input_section, -- rel->r_offset, true); -- -- outrel.r_info = ELFNN_R_INFO (0, r_type); -- } -+ outrel.r_info = ELFNN_R_INFO (0, r_type); - else - outrel.r_info = ELFNN_R_INFO (h->dynindx, r_type); - --- -2.27.0 - diff --git a/LoongArch-Modify-link_info.relax_pass-from-3-to-2.patch b/LoongArch-Modify-link_info.relax_pass-from-3-to-2.patch deleted file mode 100644 index a576bb9..0000000 --- a/LoongArch-Modify-link_info.relax_pass-from-3-to-2.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 8338aecd231af48483e36c93c103db1da715ac74 Mon Sep 17 00:00:00 2001 -From: mengqinggang -Date: Thu, 16 Nov 2023 19:19:15 +0800 -Subject: [PATCH] LoongArch: Modify link_info.relax_pass from 3 to 2 - -The first pass handles R_LARCH_RELAX relocations, the second pass -handles R_LARCH_ALIGN relocations. - -Signed-off-by: Peng Fan ---- - bfd/elfnn-loongarch.c | 2 +- - ld/emultempl/loongarchelf.em | 2 +- - 2 files changed, 2 insertions(+), 2 deletions(-) - -diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c -index 987e5b98bc0..024c5d4cd96 100644 ---- a/bfd/elfnn-loongarch.c -+++ b/bfd/elfnn-loongarch.c -@@ -4013,7 +4013,7 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, - switch (ELFNN_R_TYPE (rel->r_info)) - { - case R_LARCH_ALIGN: -- if (2 == info->relax_pass) -+ if (1 == info->relax_pass) - loongarch_relax_align (abfd, sec, sym_sec, info, rel, symval); - break; - case R_LARCH_DELETE: -diff --git a/ld/emultempl/loongarchelf.em b/ld/emultempl/loongarchelf.em -index d81c99da48b..9974989489c 100644 ---- a/ld/emultempl/loongarchelf.em -+++ b/ld/emultempl/loongarchelf.em -@@ -42,7 +42,7 @@ larch_elf_before_allocation (void) - ENABLE_RELAXATION; - } - -- link_info.relax_pass = 3; -+ link_info.relax_pass = 2; - } - - static void --- -2.33.0 - diff --git a/LoongArch-Multiple-relax_trip-in-one-relax_pass.patch b/LoongArch-Multiple-relax_trip-in-one-relax_pass.patch deleted file mode 100644 index 20f0a39..0000000 --- a/LoongArch-Multiple-relax_trip-in-one-relax_pass.patch +++ /dev/null @@ -1,57 +0,0 @@ -From b130a0849a1b3e174210903cf5370092decc62d6 Mon Sep 17 00:00:00 2001 -From: mengqinggang -Date: Thu, 16 Nov 2023 19:19:13 +0800 -Subject: [PATCH] LoongArch: Multiple relax_trip in one relax_pass - -If deleting instructions in one relax_trip, set again to true to start the -next relax_trip. - -Signed-off-by: Peng Fan ---- - bfd/elfnn-loongarch.c | 10 +++++++--- - 1 file changed, 7 insertions(+), 3 deletions(-) - -diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c -index 9d4ea7e4ae7..7436a14441f 100644 ---- a/bfd/elfnn-loongarch.c -+++ b/bfd/elfnn-loongarch.c -@@ -3740,7 +3740,7 @@ loongarch_relax_delete_bytes (bfd *abfd, - static bool - loongarch_relax_pcala_addi (bfd *abfd, asection *sec, - Elf_Internal_Rela *rel_hi, bfd_vma symval, -- struct bfd_link_info *info) -+ struct bfd_link_info *info, bool *again) - { - bfd_byte *contents = elf_section_data (sec)->this_hdr.contents; - Elf_Internal_Rela *rel_lo = rel_hi + 2; -@@ -3766,6 +3766,9 @@ loongarch_relax_pcala_addi (bfd *abfd, asection *sec, - || ((bfd_signed_vma)(symval - pc) > (bfd_signed_vma)(int32_t)0x1ffffc)) - return false; - -+ /* Continue next relax trip. */ -+ *again = true; -+ - pca = pcaddi | rd; - bfd_put (32, abfd, pca, contents + rel_hi->r_offset); - -@@ -4006,14 +4009,15 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, - break; - case R_LARCH_PCALA_HI20: - if (0 == info->relax_pass && (i + 4) <= sec->reloc_count) -- loongarch_relax_pcala_addi (abfd, sec, rel, symval, info); -+ loongarch_relax_pcala_addi (abfd, sec, rel, symval, info, again); - break; - case R_LARCH_GOT_PC_HI20: - if (local_got && 0 == info->relax_pass - && (i + 4) <= sec->reloc_count) - { - if (loongarch_relax_pcala_ld (abfd, sec, rel)) -- loongarch_relax_pcala_addi (abfd, sec, rel, symval, info); -+ loongarch_relax_pcala_addi (abfd, sec, rel, symval, -+ info, again); - } - break; - default: --- -2.33.0 - diff --git a/LoongArch-Not-alloc-dynamic-relocs-if-symbol-is-abso.patch b/LoongArch-Not-alloc-dynamic-relocs-if-symbol-is-abso.patch deleted file mode 100644 index 77c522d..0000000 --- a/LoongArch-Not-alloc-dynamic-relocs-if-symbol-is-abso.patch +++ /dev/null @@ -1,128 +0,0 @@ -From d7c082ef88547077b24d3b27144daf4ce4e442f4 Mon Sep 17 00:00:00 2001 -From: Jinyang He -Date: Mon, 8 Jul 2024 11:27:52 +0800 -Subject: [PATCH 101/123] LoongArch: Not alloc dynamic relocs if symbol is - absolute - -The absolute symbol should be resolved to const when link to dso or exe. -Alloc dynamic relocs will cause extra space and R_LARCH_NONE finally. ---- - bfd/elfnn-loongarch.c | 14 +++++++------- - ld/testsuite/ld-loongarch-elf/abssym.s | 3 +++ - ld/testsuite/ld-loongarch-elf/abssym_pie.d | 6 ++++++ - ld/testsuite/ld-loongarch-elf/abssym_shared.d | 6 ++++++ - ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp | 2 ++ - 5 files changed, 24 insertions(+), 7 deletions(-) - create mode 100644 ld/testsuite/ld-loongarch-elf/abssym.s - create mode 100644 ld/testsuite/ld-loongarch-elf/abssym_pie.d - create mode 100644 ld/testsuite/ld-loongarch-elf/abssym_shared.d - -diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c -index d11189b4..af4d8baa 100644 ---- a/bfd/elfnn-loongarch.c -+++ b/bfd/elfnn-loongarch.c -@@ -899,6 +899,7 @@ loongarch_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, - unsigned int r_type; - unsigned int r_symndx; - struct elf_link_hash_entry *h; -+ bool is_abs_symbol = false; - Elf_Internal_Sym *isym = NULL; - - r_symndx = ELFNN_R_SYM (rel->r_info); -@@ -917,6 +918,7 @@ loongarch_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, - if (isym == NULL) - return false; - -+ is_abs_symbol = isym->st_shndx == SHN_ABS; - if (ELF_ST_TYPE (isym->st_info) == STT_GNU_IFUNC) - { - h = elfNN_loongarch_get_local_sym_hash (htab, abfd, rel, true); -@@ -935,6 +937,7 @@ loongarch_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, - while (h->root.type == bfd_link_hash_indirect - || h->root.type == bfd_link_hash_warning) - h = (struct elf_link_hash_entry *) h->root.u.i.link; -+ is_abs_symbol = bfd_is_abs_symbol (&h->root); - } - - /* It is referenced by a non-shared object. */ -@@ -1142,13 +1145,6 @@ loongarch_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, - && bfd_link_pic (info) - && (sec->flags & SEC_ALLOC) != 0) - { -- bool is_abs_symbol = false; -- -- if (r_symndx < symtab_hdr->sh_info) -- is_abs_symbol = isym->st_shndx == SHN_ABS; -- else -- is_abs_symbol = bfd_is_abs_symbol (&h->root); -- - if (!is_abs_symbol) - { - _bfd_error_handler -@@ -1165,6 +1161,10 @@ loongarch_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, - case R_LARCH_JUMP_SLOT: - case R_LARCH_64: - -+ /* Resolved to const. */ -+ if (is_abs_symbol) -+ break; -+ - need_dynreloc = 1; - - /* If resolved symbol is defined in this object, -diff --git a/ld/testsuite/ld-loongarch-elf/abssym.s b/ld/testsuite/ld-loongarch-elf/abssym.s -new file mode 100644 -index 00000000..3eacc766 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/abssym.s -@@ -0,0 +1,3 @@ -+.section .data,"aw" -+.quad _size8 -+.word _size4 -diff --git a/ld/testsuite/ld-loongarch-elf/abssym_pie.d b/ld/testsuite/ld-loongarch-elf/abssym_pie.d -new file mode 100644 -index 00000000..dfc3e35b ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/abssym_pie.d -@@ -0,0 +1,6 @@ -+#source: abssym.s -+#ld: -pie -e 0 --defsym _size8=0 --defsym _size4=0 -+#readelf: -r -+#... -+There are no relocations in this file. -+#... -diff --git a/ld/testsuite/ld-loongarch-elf/abssym_shared.d b/ld/testsuite/ld-loongarch-elf/abssym_shared.d -new file mode 100644 -index 00000000..2db7e890 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/abssym_shared.d -@@ -0,0 +1,6 @@ -+#source: abssym.s -+#ld: -shared --defsym _size8=0 --defsym _size4=0 -+#readelf: -r -+#... -+There are no relocations in this file. -+#... -diff --git a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -index 2be67651..032b9bad 100644 ---- a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -+++ b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -@@ -141,6 +141,7 @@ if [istarget "loongarch64-*-*"] { - run_dump_test "relr-discard-shared" - run_dump_test "relr-got-shared" - run_dump_test "relr-text-shared" -+ run_dump_test "abssym_shared" - } - - if [check_pie_support] { -@@ -149,6 +150,7 @@ if [istarget "loongarch64-*-*"] { - run_dump_test "relr-discard-pie" - run_dump_test "relr-got-pie" - run_dump_test "relr-text-pie" -+ run_dump_test "abssym_pie" - } - - run_dump_test "max_imm_b16" --- -2.33.0 - diff --git a/LoongArch-Optimize-the-relaxation-process.patch b/LoongArch-Optimize-the-relaxation-process.patch deleted file mode 100644 index 7ff76e0..0000000 --- a/LoongArch-Optimize-the-relaxation-process.patch +++ /dev/null @@ -1,482 +0,0 @@ -From 4c19c0fd7815a9acabdca9954028f772da1d985e Mon Sep 17 00:00:00 2001 -From: mengqinggang -Date: Thu, 10 Oct 2024 16:20:52 +0800 -Subject: [PATCH 116/123] LoongArch: Optimize the relaxation process - -The symbol value is only calculated when the relocation can be relaxed. ---- - bfd/elfnn-loongarch.c | 281 +++++++++++++++++++++--------------------- - 1 file changed, 139 insertions(+), 142 deletions(-) - -diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c -index b6d7d1e8..70522fae 100644 ---- a/bfd/elfnn-loongarch.c -+++ b/bfd/elfnn-loongarch.c -@@ -4072,7 +4072,7 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, - /* For 2G jump, generate pcalau12i, jirl. */ - /* If use jirl, turns to R_LARCH_B16. */ - uint32_t insn = bfd_get (32, input_bfd, contents + rel->r_offset); -- if (LARCH_INSN_JIRL(insn)) -+ if (LARCH_INSN_JIRL (insn)) - { - relocation &= 0xfff; - /* Signed extend. */ -@@ -4852,9 +4852,11 @@ loongarch_tls_perform_trans (bfd *abfd, asection *sec, - */ - static bool - loongarch_relax_tls_le (bfd *abfd, asection *sec, -- Elf_Internal_Rela *rel, -+ asection *sym_sec ATTRIBUTE_UNUSED, -+ Elf_Internal_Rela *rel, bfd_vma symval, - struct bfd_link_info *link_info, -- bfd_vma symval) -+ bool *agin ATTRIBUTE_UNUSED, -+ bfd_vma max_alignment ATTRIBUTE_UNUSED) - { - bfd_byte *contents = elf_section_data (sec)->this_hdr.contents; - uint32_t insn = bfd_get (32, abfd, contents + rel->r_offset); -@@ -4862,7 +4864,7 @@ loongarch_relax_tls_le (bfd *abfd, asection *sec, - symval = symval - elf_hash_table (link_info)->tls_sec->vma; - /* The old LE instruction sequence can be relaxed when the symbol offset - is smaller than the 12-bit range. */ -- if (ELFNN_R_TYPE ((rel + 1)->r_info) == R_LARCH_RELAX && (symval <= 0xfff)) -+ if (symval <= 0xfff) - { - switch (ELFNN_R_TYPE (rel->r_info)) - { -@@ -4975,9 +4977,6 @@ loongarch_relax_pcala_addi (bfd *abfd, asection *sec, asection *sym_sec, - - /* Is pcalau12i + addi.d insns? */ - if ((ELFNN_R_TYPE (rel_lo->r_info) != R_LARCH_PCALA_LO12) -- || (ELFNN_R_TYPE ((rel_lo + 1)->r_info) != R_LARCH_RELAX) -- || (ELFNN_R_TYPE ((rel_hi + 1)->r_info) != R_LARCH_RELAX) -- || (rel_hi->r_offset + 4 != rel_lo->r_offset) - || !LARCH_INSN_ADDI_D(add) - /* Is pcalau12i $rd + addi.d $rd,$rd? */ - || (LARCH_GET_RD(add) != rd) -@@ -5035,10 +5034,8 @@ loongarch_relax_call36 (bfd *abfd, asection *sec, asection *sym_sec, - else if (symval < pc) - pc += (max_alignment > 4 ? max_alignment : 0); - -- - /* Is pcalau12i + addi.d insns? */ -- if ((ELFNN_R_TYPE ((rel + 1)->r_info) != R_LARCH_RELAX) -- || !LARCH_INSN_JIRL(jirl) -+ if (!LARCH_INSN_JIRL (jirl) - || ((bfd_signed_vma)(symval - pc) < (bfd_signed_vma)(int32_t)0xf8000000) - || ((bfd_signed_vma)(symval - pc) > (bfd_signed_vma)(int32_t)0x7fffffc)) - return false; -@@ -5064,7 +5061,12 @@ loongarch_relax_call36 (bfd *abfd, asection *sec, asection *sym_sec, - /* Relax pcalau12i,ld.d => pcalau12i,addi.d. */ - static bool - loongarch_relax_pcala_ld (bfd *abfd, asection *sec, -- Elf_Internal_Rela *rel_hi) -+ asection *sym_sec ATTRIBUTE_UNUSED, -+ Elf_Internal_Rela *rel_hi, -+ bfd_vma symval ATTRIBUTE_UNUSED, -+ struct bfd_link_info *info ATTRIBUTE_UNUSED, -+ bool *again ATTRIBUTE_UNUSED, -+ bfd_vma max_alignment ATTRIBUTE_UNUSED) - { - bfd_byte *contents = elf_section_data (sec)->this_hdr.contents; - Elf_Internal_Rela *rel_lo = rel_hi + 2; -@@ -5074,9 +5076,6 @@ loongarch_relax_pcala_ld (bfd *abfd, asection *sec, - uint32_t addi_d = LARCH_OP_ADDI_D; - - if ((ELFNN_R_TYPE (rel_lo->r_info) != R_LARCH_GOT_PC_LO12) -- || (ELFNN_R_TYPE ((rel_lo + 1)->r_info) != R_LARCH_RELAX) -- || (ELFNN_R_TYPE ((rel_hi + 1)->r_info) != R_LARCH_RELAX) -- || (rel_hi->r_offset + 4 != rel_lo->r_offset) - || (LARCH_GET_RD(ld) != rd) - || (LARCH_GET_RJ(ld) != rd) - || !LARCH_INSN_LD_D(ld)) -@@ -5106,11 +5105,12 @@ bfd_elfNN_loongarch_set_data_segment_info (struct bfd_link_info *info, - /* Implement R_LARCH_ALIGN by deleting excess alignment NOPs. - Once we've handled an R_LARCH_ALIGN, we can't relax anything else. */ - static bool --loongarch_relax_align (bfd *abfd, asection *sec, -- asection *sym_sec, -- struct bfd_link_info *link_info, -+loongarch_relax_align (bfd *abfd, asection *sec, asection *sym_sec, - Elf_Internal_Rela *rel, -- bfd_vma symval) -+ bfd_vma symval ATTRIBUTE_UNUSED, -+ struct bfd_link_info *link_info, -+ bool *again ATTRIBUTE_UNUSED, -+ bfd_vma max_alignment ATTRIBUTE_UNUSED) - { - bfd_vma addend, max = 0, alignment = 1; - -@@ -5198,9 +5198,6 @@ loongarch_relax_tls_ld_gd_desc (bfd *abfd, asection *sec, asection *sym_sec, - /* Is pcalau12i + addi.d insns? */ - if ((ELFNN_R_TYPE (rel_lo->r_info) != R_LARCH_GOT_PC_LO12 - && ELFNN_R_TYPE (rel_lo->r_info) != R_LARCH_TLS_DESC_PC_LO12) -- || (ELFNN_R_TYPE ((rel_lo + 1)->r_info) != R_LARCH_RELAX) -- || (ELFNN_R_TYPE ((rel_hi + 1)->r_info) != R_LARCH_RELAX) -- || (rel_hi->r_offset + 4 != rel_lo->r_offset) - || !LARCH_INSN_ADDI_D(add) - /* Is pcalau12i $rd + addi.d $rd,$rd? */ - || (LARCH_GET_RD(add) != rd) -@@ -5257,12 +5254,18 @@ loongarch_get_max_alignment (asection *sec) - return (bfd_vma) 1 << max_alignment_power; - } - -+typedef bool (*relax_func_t) (bfd *, asection *, asection *, -+ Elf_Internal_Rela *, bfd_vma, -+ struct bfd_link_info *, bool *, -+ bfd_vma); -+ - static bool - loongarch_elf_relax_section (bfd *abfd, asection *sec, - struct bfd_link_info *info, - bool *again) - { - *again = false; -+ - if (!is_elf_hash_table (info->hash) - || elf_hash_table_id (elf_hash_table (info)) != LARCH_ELF_DATA) - return true; -@@ -5277,13 +5280,13 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, - - if (bfd_link_relocatable (info) - || sec->sec_flg0 -- || (sec->flags & SEC_RELOC) == 0 - || sec->reloc_count == 0 -+ || (sec->flags & SEC_RELOC) == 0 -+ || (sec->flags & SEC_HAS_CONTENTS) == 0 -+ /* The exp_seg_relro_adjust is enum phase_enum (0x4). */ -+ || *(htab->data_segment_phase) == 4 - || (info->disable_target_specific_optimizations -- && info->relax_pass == 0) -- /* The exp_seg_relro_adjust is enum phase_enum (0x4), -- and defined in ld/ldexp.h. */ -- || *(htab->data_segment_phase) == 4) -+ && info->relax_pass == 0)) - return true; - - struct bfd_elf_section_data *data = elf_section_data (sec); -@@ -5293,11 +5296,14 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, - else if (!(relocs = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, - info->keep_memory))) - return true; -+ data->relocs = relocs; - -+ /* Read this BFD's contents if we haven't done so already. */ - if (!data->this_hdr.contents - && !bfd_malloc_and_get_section (abfd, sec, &data->this_hdr.contents)) - return true; - -+ /* Read this BFD's symbols if we haven't done so already. */ - Elf_Internal_Shdr *symtab_hdr = &elf_symtab_hdr (abfd); - if (symtab_hdr->sh_info != 0 - && !symtab_hdr->contents -@@ -5307,8 +5313,6 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, - 0, NULL, NULL, NULL))) - return true; - -- data->relocs = relocs; -- - /* Estimate the maximum alignment for all output sections once time - should be enough. */ - bfd_vma max_alignment = htab->max_alignment; -@@ -5330,6 +5334,93 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, - unsigned long r_type = ELFNN_R_TYPE (rel->r_info); - unsigned long r_symndx = ELFNN_R_SYM (rel->r_info); - -+ if (r_symndx >= symtab_hdr->sh_info) -+ { -+ h = elf_sym_hashes (abfd)[r_symndx - symtab_hdr->sh_info]; -+ while (h->root.type == bfd_link_hash_indirect -+ || h->root.type == bfd_link_hash_warning) -+ h = (struct elf_link_hash_entry *) h->root.u.i.link; -+ } -+ -+ /* If the conditions for tls type transition are met, type -+ transition is performed instead of relax. -+ During the transition from DESC->IE/LE, there are 2 situations -+ depending on the different configurations of the relax/norelax -+ option. -+ If the -relax option is used, the extra nops will be removed, -+ and this transition is performed in pass 0. -+ If the --no-relax option is used, nop will be retained, and -+ this transition is performed in pass 1. */ -+ if (IS_LOONGARCH_TLS_TRANS_RELOC (r_type) -+ && (i + 1 != sec->reloc_count) -+ && ELFNN_R_TYPE (rel[1].r_info) == R_LARCH_RELAX -+ && rel->r_offset == rel[1].r_offset -+ && loongarch_can_trans_tls (abfd, info, h, r_symndx, r_type)) -+ { -+ loongarch_tls_perform_trans (abfd, sec, rel, h, info); -+ r_type = ELFNN_R_TYPE (rel->r_info); -+ } -+ -+ relax_func_t relax_func = NULL; -+ if (info->relax_pass == 0) -+ { -+ switch (r_type) -+ { -+ case R_LARCH_PCALA_HI20: -+ relax_func = loongarch_relax_pcala_addi; -+ break; -+ case R_LARCH_GOT_PC_HI20: -+ relax_func = loongarch_relax_pcala_ld; -+ break; -+ case R_LARCH_CALL36: -+ relax_func = loongarch_relax_call36; -+ break; -+ case R_LARCH_TLS_LE_HI20_R: -+ case R_LARCH_TLS_LE_LO12_R: -+ case R_LARCH_TLS_LE_ADD_R: -+ case R_LARCH_TLS_LE_HI20: -+ case R_LARCH_TLS_LE_LO12: -+ case R_LARCH_TLS_LE64_LO20: -+ case R_LARCH_TLS_LE64_HI12: -+ relax_func = loongarch_relax_tls_le; -+ break; -+ case R_LARCH_TLS_LD_PC_HI20: -+ case R_LARCH_TLS_GD_PC_HI20: -+ case R_LARCH_TLS_DESC_PC_HI20: -+ relax_func = loongarch_relax_tls_ld_gd_desc; -+ break; -+ default: -+ continue; -+ } -+ -+ /* Only relax this reloc if it is paired with R_RISCV_RELAX. */ -+ if (r_type == R_LARCH_TLS_LD_PC_HI20 -+ || r_type == R_LARCH_TLS_GD_PC_HI20 -+ || r_type == R_LARCH_TLS_DESC_PC_HI20 -+ || r_type == R_LARCH_PCALA_HI20 -+ || r_type == R_LARCH_GOT_PC_HI20) -+ { -+ if ((i + 2) == sec->reloc_count - 1 -+ || ELFNN_R_TYPE ((rel + 1)->r_info) != R_LARCH_RELAX -+ || ELFNN_R_TYPE ((rel + 3)->r_info) != R_LARCH_RELAX -+ || rel->r_offset != (rel + 1)->r_offset -+ || (rel + 2)->r_offset != (rel + 3)->r_offset -+ || rel->r_offset + 4 != (rel + 2)->r_offset) -+ continue; -+ } -+ else -+ { -+ if (i == sec->reloc_count - 1 -+ || ELFNN_R_TYPE ((rel + 1)->r_info) != R_LARCH_RELAX -+ || rel->r_offset != (rel + 1)->r_offset) -+ continue; -+ } -+ } -+ else if (info->relax_pass == 1 && r_type == R_LARCH_ALIGN) -+ relax_func = loongarch_relax_align; -+ else -+ continue; -+ - /* Four kind of relocations: - Normal: symval is the symbol address. - R_LARCH_ALIGN: symval is the address of the last NOP instruction -@@ -5342,29 +5433,26 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, - { - Elf_Internal_Sym *sym = (Elf_Internal_Sym *)symtab_hdr->contents - + r_symndx; -+ - if (ELF_ST_TYPE (sym->st_info) == STT_GNU_IFUNC) - continue; - - /* Only TLS instruction sequences that are accompanied by - R_LARCH_RELAX and cannot perform type transition can be - relaxed. */ -- if (R_LARCH_TLS_LD_PC_HI20 == r_type -- || R_LARCH_TLS_GD_PC_HI20 == r_type -- || (R_LARCH_TLS_DESC_PC_HI20 == r_type -- && (i + 1 != sec->reloc_count) -- && ELFNN_R_TYPE (rel[1].r_info) == R_LARCH_RELAX -- && ! loongarch_can_trans_tls (abfd, info, h, -- r_symndx, r_type))) -+ if (r_type == R_LARCH_TLS_LD_PC_HI20 -+ || r_type == R_LARCH_TLS_GD_PC_HI20 -+ || r_type == R_LARCH_TLS_DESC_PC_HI20) - { - sym_sec = htab->elf.sgot; - symval = elf_local_got_offsets (abfd)[r_symndx]; - char tls_type = _bfd_loongarch_elf_tls_type (abfd, h, - r_symndx); -- if (R_LARCH_TLS_DESC_PC_HI20 == r_type -+ if (r_type == R_LARCH_TLS_DESC_PC_HI20 - && GOT_TLS_GD_BOTH_P (tls_type)) - symval += 2 * GOT_ENTRY_SIZE; - } -- else if (sym->st_shndx == SHN_UNDEF || R_LARCH_ALIGN == r_type) -+ else if (sym->st_shndx == SHN_UNDEF || r_type == R_LARCH_ALIGN) - { - sym_sec = sec; - symval = rel->r_offset; -@@ -5375,35 +5463,25 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, - symval = sym->st_value; - } - symtype = ELF_ST_TYPE (sym->st_info); -+ is_abs_symbol = sym->st_shndx == SHN_ABS; - } - else - { -- r_symndx = ELFNN_R_SYM (rel->r_info) - symtab_hdr->sh_info; -- h = elf_sym_hashes (abfd)[r_symndx]; -- -- while (h->root.type == bfd_link_hash_indirect -- || h->root.type == bfd_link_hash_warning) -- h = (struct elf_link_hash_entry *) h->root.u.i.link; -- - /* Disable the relaxation for ifunc. */ - if (h != NULL && h->type == STT_GNU_IFUNC) - continue; - - /* The GOT entry of tls symbols must in current execute file or - shared object. */ -- if (R_LARCH_TLS_LD_PC_HI20 == r_type -- || R_LARCH_TLS_GD_PC_HI20 == r_type -- || (R_LARCH_TLS_DESC_PC_HI20 == r_type -- && (i + 1 != sec->reloc_count) -- && ELFNN_R_TYPE (rel[1].r_info) == R_LARCH_RELAX -- && !loongarch_can_trans_tls (abfd, info, h, -- r_symndx, r_type))) -+ if (r_type == R_LARCH_TLS_LD_PC_HI20 -+ || r_type == R_LARCH_TLS_GD_PC_HI20 -+ || r_type == R_LARCH_TLS_DESC_PC_HI20) - { - sym_sec = htab->elf.sgot; - symval = h->got.offset; - char tls_type = _bfd_loongarch_elf_tls_type (abfd, h, - r_symndx); -- if (R_LARCH_TLS_DESC_PC_HI20 == r_type -+ if (r_type == R_LARCH_TLS_DESC_PC_HI20 - && GOT_TLS_GD_BOTH_P (tls_type)) - symval += 2 * GOT_ENTRY_SIZE; - } -@@ -5412,12 +5490,13 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, - && h->root.u.def.section != NULL - && h->root.u.def.section->output_section != NULL) - { -- symval = h->root.u.def.value; - sym_sec = h->root.u.def.section; -+ symval = h->root.u.def.value; - } - else - continue; - -+ is_abs_symbol = bfd_is_abs_section (h->root.u.def.section); - if (h && LARCH_REF_LOCAL (info, h)) - local_got = true; - symtype = h->type; -@@ -5440,7 +5519,7 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, - + (alingmeng - 4). - If r_symndx is 0, alignmeng-4 is r_addend. - If r_symndx > 0, alignment-4 is 2^(r_addend & 0xff)-4. */ -- else if (R_LARCH_ALIGN == r_type) -+ else if (r_type == R_LARCH_ALIGN) - if (r_symndx > 0) - symval += ((1 << (rel->r_addend & 0xff)) - 4); - else -@@ -5450,96 +5529,14 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, - - symval += sec_addr (sym_sec); - -- /* If the conditions for tls type transition are met, type -- transition is performed instead of relax. -- During the transition from DESC->IE/LE, there are 2 situations -- depending on the different configurations of the relax/norelax -- option. -- If the -relax option is used, the extra nops will be removed, -- and this transition is performed in pass 0. -- If the --no-relax option is used, nop will be retained, and -- this transition is performed in pass 1. */ -- if (IS_LOONGARCH_TLS_TRANS_RELOC (r_type) -- && (i + 1 != sec->reloc_count) -- && ELFNN_R_TYPE (rel[1].r_info) == R_LARCH_RELAX -- && loongarch_can_trans_tls (abfd, info, h, r_symndx, r_type)) -- { -- loongarch_tls_perform_trans (abfd, sec, rel, h, info); -- r_type = ELFNN_R_TYPE (rel->r_info); -- } -- -- switch (r_type) -- { -- case R_LARCH_ALIGN: -- if (1 == info->relax_pass) -- loongarch_relax_align (abfd, sec, sym_sec, info, rel, symval); -- break; -+ if (r_type == R_LARCH_GOT_PC_HI20 && (!local_got || is_abs_symbol)) -+ continue; - -- case R_LARCH_DELETE: -- if (1 == info->relax_pass) -- { -- loongarch_relax_delete_bytes (abfd, sec, rel->r_offset, 4, info); -- rel->r_info = ELFNN_R_INFO (0, R_LARCH_NONE); -- } -- break; -- case R_LARCH_CALL36: -- if (0 == info->relax_pass && (i + 2) <= sec->reloc_count) -- loongarch_relax_call36 (abfd, sec, sym_sec, rel, symval, -+ if (relax_func (abfd, sec, sym_sec, rel, symval, -+ info, again, max_alignment) -+ && relax_func == loongarch_relax_pcala_ld) -+ loongarch_relax_pcala_addi (abfd, sec, sym_sec, rel, symval, - info, again, max_alignment); -- break; -- -- case R_LARCH_TLS_LE_HI20_R: -- case R_LARCH_TLS_LE_LO12_R: -- case R_LARCH_TLS_LE_ADD_R: -- case R_LARCH_TLS_LE_HI20: -- case R_LARCH_TLS_LE_LO12: -- case R_LARCH_TLS_LE64_LO20: -- case R_LARCH_TLS_LE64_HI12: -- if (0 == info->relax_pass && (i + 2) <= sec->reloc_count) -- loongarch_relax_tls_le (abfd, sec, rel, info, symval); -- break; -- -- case R_LARCH_PCALA_HI20: -- if (0 == info->relax_pass && (i + 4) <= sec->reloc_count) -- loongarch_relax_pcala_addi (abfd, sec, sym_sec, rel, symval, -- info, again, max_alignment); -- break; -- -- case R_LARCH_GOT_PC_HI20: -- if (h) -- is_abs_symbol = bfd_is_abs_section(h->root.u.def.section); -- else -- { -- Elf_Internal_Sym *sym = (Elf_Internal_Sym *)symtab_hdr->contents -- + ELFNN_R_SYM (rel->r_info); -- is_abs_symbol = sym->st_shndx == SHN_ABS; -- } -- /* If symval is in the range [-2^31, 2^31), we can relax the -- pair of instructions from pcalau12i/ld.d to lu12i.w/ori for -- abosulte symbol. This is not implemented yet, so we just -- remain the r_type which will be needed when relocate for -- absolute symbol. */ -- if (local_got && 0 == info->relax_pass -- && !is_abs_symbol -- && (i + 4) <= sec->reloc_count) -- { -- if (loongarch_relax_pcala_ld (abfd, sec, rel)) -- loongarch_relax_pcala_addi (abfd, sec, sym_sec, rel, symval, -- info, again, max_alignment); -- } -- break; -- -- case R_LARCH_TLS_LD_PC_HI20: -- case R_LARCH_TLS_GD_PC_HI20: -- case R_LARCH_TLS_DESC_PC_HI20: -- if (0 == info->relax_pass && (i + 4) <= sec->reloc_count) -- loongarch_relax_tls_ld_gd_desc (abfd, sec, sym_sec, rel, symval, -- info, again, max_alignment); -- break; -- -- default: -- break; -- } - } - - return true; --- -2.33.0 - diff --git a/LoongArch-Reject-R_LARCH_32-from-becoming-a-runtime-.patch b/LoongArch-Reject-R_LARCH_32-from-becoming-a-runtime-.patch deleted file mode 100644 index 109c1b2..0000000 --- a/LoongArch-Reject-R_LARCH_32-from-becoming-a-runtime-.patch +++ /dev/null @@ -1,132 +0,0 @@ -From b1375201b1643fee97a240ba17523a529b286e12 Mon Sep 17 00:00:00 2001 -From: Xi Ruoyao -Date: Sun, 30 Jun 2024 15:18:21 +0800 -Subject: [PATCH 095/123] LoongArch: Reject R_LARCH_32 from becoming a runtime - reloc in ELFCLASS64 - -We were converting R_LARCH_32 to R_LARCH_RELATIVE for ELFCLASS64: - - $ cat t.s - .data - x: - .4byte x - .4byte 0xdeadbeef - $ as/as-new t.s -o t.o - $ ld/ld-new -shared t.o - $ objdump -R - a.out: file format elf64-loongarch - - DYNAMIC RELOCATION RECORDS - OFFSET TYPE VALUE - 00000000000001a8 R_LARCH_RELATIVE *ABS*+0x00000000000001a8 - -But this is just wrong: at runtime the dynamic linker will run -*(uintptr *)&x += load_address, clobbering the next 4 bytes of data -("0xdeadbeef" in the example). - -If we keep the R_LARCH_32 reloc as-is in ELFCLASS64, it'll be rejected -by the Glibc dynamic linker anyway. And it does not make too much sense -to modify Glibc to support it. So we can just reject it like x86_64: - - relocation R_X86_64_32 against `.data' can not be used when making a - shared object; recompile with -fPIC - -or RISC-V: - - relocation R_RISCV_32 against non-absolute symbol `a local symbol' - can not be used in RV64 when making a shared object - -Signed-off-by: Xi Ruoyao ---- - bfd/elfnn-loongarch.c | 30 +++++++++++++++++-- - .../ld-loongarch-elf/ld-loongarch-elf.exp | 1 + - .../ld-loongarch-elf/r_larch_32_elf64.d | 4 +++ - .../ld-loongarch-elf/r_larch_32_elf64.s | 3 ++ - 4 files changed, 36 insertions(+), 2 deletions(-) - create mode 100644 ld/testsuite/ld-loongarch-elf/r_larch_32_elf64.d - create mode 100644 ld/testsuite/ld-loongarch-elf/r_larch_32_elf64.s - -diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c -index 840cdd35..fa0a5e38 100644 ---- a/bfd/elfnn-loongarch.c -+++ b/bfd/elfnn-loongarch.c -@@ -1036,8 +1036,32 @@ loongarch_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, - only_need_pcrel = 1; - break; - -- case R_LARCH_JUMP_SLOT: - case R_LARCH_32: -+ if (ARCH_SIZE > 32 -+ && bfd_link_pic (info) -+ && (sec->flags & SEC_ALLOC) != 0) -+ { -+ bool is_abs_symbol = false; -+ -+ if (r_symndx < symtab_hdr->sh_info) -+ is_abs_symbol = isym->st_shndx == SHN_ABS; -+ else -+ is_abs_symbol = bfd_is_abs_symbol (&h->root); -+ -+ if (!is_abs_symbol) -+ { -+ _bfd_error_handler -+ (_("%pB: relocation R_LARCH_32 against non-absolute " -+ "symbol `%s' cannot be used in ELFCLASS64 when " -+ "making a shared object or PIE"), -+ abfd, h ? h->root.root.string : "a local symbol"); -+ bfd_set_error (bfd_error_bad_value); -+ return false; -+ } -+ } -+ -+ /* Fall through. */ -+ case R_LARCH_JUMP_SLOT: - case R_LARCH_64: - - need_dynreloc = 1; -@@ -2858,8 +2882,10 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, - outrel.r_addend = relocation + rel->r_addend; - } - -- /* No alloc space of func allocate_dynrelocs. */ -+ /* No alloc space of func allocate_dynrelocs. -+ No alloc space of invalid R_LARCH_32 in ELFCLASS64. */ - if (unresolved_reloc -+ && (ARCH_SIZE == 32 || r_type != R_LARCH_32) - && !(h && (h->is_weakalias || !h->dyn_relocs))) - loongarch_elf_append_rela (output_bfd, sreloc, &outrel); - } -diff --git a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -index 89552a11..7ffabe2c 100644 ---- a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -+++ b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -@@ -132,6 +132,7 @@ if [istarget "loongarch64-*-*"] { - run_dump_test "reloc_le_with_shared" - run_dump_test "reloc_ler_with_shared" - run_dump_test "reloc_abs_with_shared" -+ run_dump_test "r_larch_32_elf64" - } - - if [check_pie_support] { -diff --git a/ld/testsuite/ld-loongarch-elf/r_larch_32_elf64.d b/ld/testsuite/ld-loongarch-elf/r_larch_32_elf64.d -new file mode 100644 -index 00000000..34313295 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/r_larch_32_elf64.d -@@ -0,0 +1,4 @@ -+#name: R_LARCH_32 in ELFCLASS64 -+#source: r_larch_32_elf64.s -+#ld: -shared -melf64loongarch -+#error: R_LARCH_32 .* cannot be used in ELFCLASS64 -diff --git a/ld/testsuite/ld-loongarch-elf/r_larch_32_elf64.s b/ld/testsuite/ld-loongarch-elf/r_larch_32_elf64.s -new file mode 100644 -index 00000000..6649f2bc ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/r_larch_32_elf64.s -@@ -0,0 +1,3 @@ -+.data -+x: -+ .4byte x --- -2.33.0 - diff --git a/LoongArch-Remove-elf_seg_map-info-output_bfd-NULL-re.patch b/LoongArch-Remove-elf_seg_map-info-output_bfd-NULL-re.patch deleted file mode 100644 index bceee08..0000000 --- a/LoongArch-Remove-elf_seg_map-info-output_bfd-NULL-re.patch +++ /dev/null @@ -1,112 +0,0 @@ -From 4f2469d0cdd0f3bd1d9040521e002e8df0a63a98 Mon Sep 17 00:00:00 2001 -From: mengqinggang -Date: Thu, 16 Nov 2023 19:19:14 +0800 -Subject: [PATCH] LoongArch: Remove "elf_seg_map (info->output_bfd) == NULL" - relaxation condition - -Previously the condition prevented shared objects from being relaxed. -To remove the limitation, we need to update program header size and -.eh_frame_hdr size before relaxation. - -Signed-off-by: Peng Fan ---- - bfd/elfnn-loongarch.c | 25 +++++++++++++++++++++---- - ld/emultempl/loongarchelf.em | 18 ++++++++++++++++++ - 2 files changed, 39 insertions(+), 4 deletions(-) - -diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c -index 7436a14441f..987e5b98bc0 100644 ---- a/bfd/elfnn-loongarch.c -+++ b/bfd/elfnn-loongarch.c -@@ -3738,7 +3738,7 @@ loongarch_relax_delete_bytes (bfd *abfd, - - /* Relax pcalau12i,addi.d => pcaddi. */ - static bool --loongarch_relax_pcala_addi (bfd *abfd, asection *sec, -+loongarch_relax_pcala_addi (bfd *abfd, asection *sec, asection *sym_sec, - Elf_Internal_Rela *rel_hi, bfd_vma symval, - struct bfd_link_info *info, bool *again) - { -@@ -3747,7 +3747,24 @@ loongarch_relax_pcala_addi (bfd *abfd, asection *sec, - uint32_t pca = bfd_get (32, abfd, contents + rel_hi->r_offset); - uint32_t add = bfd_get (32, abfd, contents + rel_lo->r_offset); - uint32_t rd = pca & 0x1f; -+ -+ /* This section's output_offset need to subtract the bytes of instructions -+ relaxed by the previous sections, so it needs to be updated beforehand. -+ size_input_section already took care of updating it after relaxation, -+ so we additionally update once here. */ -+ sec->output_offset = sec->output_section->size; - bfd_vma pc = sec_addr (sec) + rel_hi->r_offset; -+ -+ /* If pc and symbol not in the same segment, add/sub segment alignment. -+ FIXME: if there are multiple readonly segments? */ -+ if (!(sym_sec->flags & SEC_READONLY)) -+ { -+ if (symval > pc) -+ pc -= info->maxpagesize; -+ else if (symval < pc) -+ pc += info->maxpagesize; -+ } -+ - const uint32_t addi_d = 0x02c00000; - const uint32_t pcaddi = 0x18000000; - -@@ -3889,7 +3906,6 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, - || sec->sec_flg0 - || (sec->flags & SEC_RELOC) == 0 - || sec->reloc_count == 0 -- || elf_seg_map (info->output_bfd) == NULL - || (info->disable_target_specific_optimizations - && info->relax_pass == 0) - /* The exp_seg_relro_adjust is enum phase_enum (0x4), -@@ -4009,14 +4025,15 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, - break; - case R_LARCH_PCALA_HI20: - if (0 == info->relax_pass && (i + 4) <= sec->reloc_count) -- loongarch_relax_pcala_addi (abfd, sec, rel, symval, info, again); -+ loongarch_relax_pcala_addi (abfd, sec, sym_sec, rel, symval, -+ info, again); - break; - case R_LARCH_GOT_PC_HI20: - if (local_got && 0 == info->relax_pass - && (i + 4) <= sec->reloc_count) - { - if (loongarch_relax_pcala_ld (abfd, sec, rel)) -- loongarch_relax_pcala_addi (abfd, sec, rel, symval, -+ loongarch_relax_pcala_addi (abfd, sec, sym_sec, rel, symval, - info, again); - } - break; -diff --git a/ld/emultempl/loongarchelf.em b/ld/emultempl/loongarchelf.em -index 4850feb8767..d81c99da48b 100644 ---- a/ld/emultempl/loongarchelf.em -+++ b/ld/emultempl/loongarchelf.em -@@ -62,6 +62,24 @@ gld${EMULATION_NAME}_after_allocation (void) - } - } - -+ /* The program header size of executable file may increase. */ -+ if (bfd_get_flavour (link_info.output_bfd) == bfd_target_elf_flavour -+ && !bfd_link_relocatable (&link_info)) -+ { -+ if (lang_phdr_list == NULL) -+ elf_seg_map (link_info.output_bfd) = NULL; -+ if (!_bfd_elf_map_sections_to_segments (link_info.output_bfd, -+ &link_info, -+ NULL)) -+ einfo (_("%F%P: map sections to segments failed: %E\n")); -+ } -+ -+ /* Adjust program header size and .eh_frame_hdr size before -+ lang_relax_sections. Without it, the vma of data segment may increase. */ -+ lang_do_assignments (lang_allocating_phase_enum); -+ lang_reset_memory_regions (); -+ lang_size_sections (NULL, true); -+ - enum phase_enum *phase = &(expld.dataseg.phase); - bfd_elf${ELFSIZE}_loongarch_set_data_segment_info (&link_info, (int *) phase); - /* gld${EMULATION_NAME}_map_segments (need_layout); */ --- -2.33.0 - diff --git a/LoongArch-Remove-unused-code-in-ld-test-suite.patch b/LoongArch-Remove-unused-code-in-ld-test-suite.patch deleted file mode 100644 index f1c7772..0000000 --- a/LoongArch-Remove-unused-code-in-ld-test-suite.patch +++ /dev/null @@ -1,45 +0,0 @@ -From a88594951ad3b0657d8e6139c3fde63e7a771b12 Mon Sep 17 00:00:00 2001 -From: Xi Ruoyao -Date: Sat, 22 Jun 2024 18:06:47 +0800 -Subject: [PATCH 094/123] LoongArch: Remove unused code in ld test suite - -These seems some left over from MIPS code and they do not make any -sense for LoongArch. - -Signed-off-by: Xi Ruoyao ---- - ld/testsuite/ld-loongarch-elf/anno-sym.d | 2 -- - ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp | 7 ------- - 2 files changed, 9 deletions(-) - -diff --git a/ld/testsuite/ld-loongarch-elf/anno-sym.d b/ld/testsuite/ld-loongarch-elf/anno-sym.d -index a58f4a6c..6d2149f0 100644 ---- a/ld/testsuite/ld-loongarch-elf/anno-sym.d -+++ b/ld/testsuite/ld-loongarch-elf/anno-sym.d -@@ -3,5 +3,3 @@ - #as: -mno-relax - #ld: -e _start - #error_output: anno-sym.l --# The mips-irix6 target fails this test because it does not find any function symbols. Not sure why. --#skip: *-*-irix* -diff --git a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -index 5d109a4d..89552a11 100644 ---- a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -+++ b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -@@ -19,13 +19,6 @@ - # MA 02110-1301, USA. - # - --proc loongarch_choose_lp64_emul {} { -- if { [istarget "loongarch64be-*"] } { -- return "elf64bloongarch" -- } -- return "elf64lloongarch" --} -- - if [istarget "loongarch64-*-*"] { - run_dump_test "jmp_op" - run_dump_test "macro_op" --- -2.33.0 - diff --git a/LoongArch-Run-overflow-testcases-only-on-LoongArch-t.patch b/LoongArch-Run-overflow-testcases-only-on-LoongArch-t.patch deleted file mode 100644 index d7e80a1..0000000 --- a/LoongArch-Run-overflow-testcases-only-on-LoongArch-t.patch +++ /dev/null @@ -1,50 +0,0 @@ -From 070b9a5e5d1a0864a8e9971cefd4b0e73637e783 Mon Sep 17 00:00:00 2001 -From: mengqinggang -Date: Tue, 27 Feb 2024 15:12:14 +0800 -Subject: [PATCH 061/123] LoongArch: Run overflow testcases only on LoongArch - target - ---- - .../ld-loongarch-elf/ld-loongarch-elf.exp | 27 ++++++++++--------- - 1 file changed, 14 insertions(+), 13 deletions(-) - -diff --git a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -index b3029e53..7dca8218 100644 ---- a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -+++ b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -@@ -133,18 +133,19 @@ if [istarget "loongarch64-*-*"] { - run_dump_test "desc-norelax" - run_dump_test "desc-relax" - } -+ -+ run_dump_test "max_imm_b16" -+ run_dump_test "max_imm_b21" -+ run_dump_test "max_imm_b26" -+ run_dump_test "max_imm_pcrel20" -+ run_dump_test "overflow_b16" -+ run_dump_test "overflow_b21" -+ run_dump_test "overflow_b26" -+ run_dump_test "overflow_pcrel20" -+ run_dump_test "underflow_b16" -+ run_dump_test "underflow_b21" -+ run_dump_test "underflow_b26" -+ run_dump_test "underflow_pcrel20" -+ run_dump_test "pie_discard" - } - --run_dump_test "max_imm_b16" --run_dump_test "max_imm_b21" --run_dump_test "max_imm_b26" --run_dump_test "max_imm_pcrel20" --run_dump_test "overflow_b16" --run_dump_test "overflow_b21" --run_dump_test "overflow_b26" --run_dump_test "overflow_pcrel20" --run_dump_test "underflow_b16" --run_dump_test "underflow_b21" --run_dump_test "underflow_b26" --run_dump_test "underflow_pcrel20" --run_dump_test "pie_discard" --- -2.33.0 - diff --git a/LoongArch-Scan-all-illegal-operand-instructions-with.patch b/LoongArch-Scan-all-illegal-operand-instructions-with.patch deleted file mode 100644 index 04e3367..0000000 --- a/LoongArch-Scan-all-illegal-operand-instructions-with.patch +++ /dev/null @@ -1,381 +0,0 @@ -From e3cee667f81d7f7982f4a9f75370415b00e9cff6 Mon Sep 17 00:00:00 2001 -From: Lulu Cai -Date: Sat, 2 Mar 2024 10:47:42 +0800 -Subject: [PATCH 073/123] LoongArch: Scan all illegal operand instructions - without interruption - -Currently, gas will exit immediately and report an error when -it sees illegal operands, and will not process the remaining -instructions. Replace as_fatal with as_bad to check for all -illegal operands. - -Add test cases for illegal operands of some instructions. ---- - gas/config/tc-loongarch.c | 11 +- - .../gas/loongarch/check_bstrins-pick.d | 18 +++ - .../gas/loongarch/check_bstrins-pick.s | 9 ++ - gas/testsuite/gas/loongarch/illegal-operand.l | 113 +++++++++++++++++ - gas/testsuite/gas/loongarch/illegal-operand.s | 117 ++++++++++++++++++ - gas/testsuite/gas/loongarch/loongarch.exp | 4 + - gas/testsuite/gas/loongarch/lvz-lbt.d | 2 +- - gas/testsuite/gas/loongarch/lvz-lbt.s | 2 +- - 8 files changed, 269 insertions(+), 7 deletions(-) - create mode 100644 gas/testsuite/gas/loongarch/check_bstrins-pick.d - create mode 100644 gas/testsuite/gas/loongarch/check_bstrins-pick.s - create mode 100644 gas/testsuite/gas/loongarch/illegal-operand.l - create mode 100644 gas/testsuite/gas/loongarch/illegal-operand.s - -diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c -index b510d228..ff126d56 100644 ---- a/gas/config/tc-loongarch.c -+++ b/gas/config/tc-loongarch.c -@@ -958,8 +958,8 @@ check_this_insn_before_appending (struct loongarch_cl_insn *ip) - /* For AMO insn amswap.[wd], amadd.[wd], etc. */ - if (ip->args[0] != 0 - && (ip->args[0] == ip->args[1] || ip->args[0] == ip->args[2])) -- as_fatal (_("AMO insns require rd != base && rd != rt" -- " when rd isn't $r0")); -+ as_bad (_("automic memory operations insns require rd != rj" -+ " && rd != rk when rd isn't r0")); - } - else if ((ip->insn->mask == 0xffe08000 - /* bstrins.w rd, rj, msbw, lsbw */ -@@ -970,12 +970,13 @@ check_this_insn_before_appending (struct loongarch_cl_insn *ip) - { - /* For bstr(ins|pick).[wd]. */ - if (ip->args[2] < ip->args[3]) -- as_fatal (_("bstr(ins|pick).[wd] require msbd >= lsbd")); -+ as_bad (_("bstr(ins|pick).[wd] require msbd >= lsbd")); - } - else if (ip->insn->mask != 0 && (ip->insn_bin & 0xfe0003c0) == 0x04000000 - /* csrxchg rd, rj, csr_num */ -- && (strcmp ("csrxchg", ip->name) == 0)) -- as_fatal (_("csrxchg require rj != $r0 && rj != $r1")); -+ && (strcmp ("csrxchg", ip->name) == 0 -+ || strcmp ("gcsrxchg", ip->name) == 0)) -+ as_bad (_("g?csrxchg require rj != r0 && rj != r1")); - - return ret; - } -diff --git a/gas/testsuite/gas/loongarch/check_bstrins-pick.d b/gas/testsuite/gas/loongarch/check_bstrins-pick.d -new file mode 100644 -index 00000000..7575be19 ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/check_bstrins-pick.d -@@ -0,0 +1,18 @@ -+#as: -+#objdump: -d -+#skip: loongarch32-*-* -+ -+.*:[ ]+file format .* -+ -+ -+Disassembly of section .text: -+ -+0+ <.*>: -+ 0: 00682041 bstrins\.w \$ra, \$tp, 0x8, 0x8 -+ 4: 00882041 bstrins\.d \$ra, \$tp, 0x8, 0x8 -+ 8: 0068a041 bstrpick\.w \$ra, \$tp, 0x8, 0x8 -+ c: 00c82041 bstrpick\.d \$ra, \$tp, 0x8, 0x8 -+ 10: 00680041 bstrins\.w \$ra, \$tp, 0x8, 0x0 -+ 14: 00880041 bstrins\.d \$ra, \$tp, 0x8, 0x0 -+ 18: 00688041 bstrpick\.w \$ra, \$tp, 0x8, 0x0 -+ 1c: 00c80041 bstrpick\.d \$ra, \$tp, 0x8, 0x0 -diff --git a/gas/testsuite/gas/loongarch/check_bstrins-pick.s b/gas/testsuite/gas/loongarch/check_bstrins-pick.s -new file mode 100644 -index 00000000..0decaf98 ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/check_bstrins-pick.s -@@ -0,0 +1,9 @@ -+bstrins.w $r1,$r2,8,8 -+bstrins.d $r1,$r2,8,8 -+bstrpick.w $r1,$r2,8,8 -+bstrpick.d $r1,$r2,8,8 -+ -+bstrins.w $r1,$r2,8,0 -+bstrins.d $r1,$r2,8,0 -+bstrpick.w $r1,$r2,8,0 -+bstrpick.d $r1,$r2,8,0 -diff --git a/gas/testsuite/gas/loongarch/illegal-operand.l b/gas/testsuite/gas/loongarch/illegal-operand.l -new file mode 100644 -index 00000000..dddc6d6f ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/illegal-operand.l -@@ -0,0 +1,113 @@ -+.*: Assembler messages: -+.*:2: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:3: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:4: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:5: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:6: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:7: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:8: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:9: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:10: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:11: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:12: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:13: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:14: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:15: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:16: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:17: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:18: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:19: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:20: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:21: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:22: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:23: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:24: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:25: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:26: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:27: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:28: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:29: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:30: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:31: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:32: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:33: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:34: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:35: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:36: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:37: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:38: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:39: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:40: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:41: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:42: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:43: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:44: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:45: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:46: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:47: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:48: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:49: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:50: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:51: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:52: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:53: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:54: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:55: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:56: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:57: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:58: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:59: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:60: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:61: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:62: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:63: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:64: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:65: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:66: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:67: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:68: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:69: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:70: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:71: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:72: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:73: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:74: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:75: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:76: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:77: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:78: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:79: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:80: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:81: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:82: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:83: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:84: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:85: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:86: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:87: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:88: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:89: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:90: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:91: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:92: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:93: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:94: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:95: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:96: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:97: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:98: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:99: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:100: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:101: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:102: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:103: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:104: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:105: Error: automic memory operations insns require rd != rj && rd != rk when rd isn't r0 -+.*:108: Error: bstr\(ins\|pick\)\.\[wd\] require msbd >= lsbd -+.*:109: Error: bstr\(ins\|pick\)\.\[wd\] require msbd >= lsbd -+.*:110: Error: bstr\(ins\|pick\)\.\[wd\] require msbd >= lsbd -+.*:111: Error: bstr\(ins\|pick\)\.\[wd\] require msbd >= lsbd -+.*:114: Error: g\?csrxchg require rj != r0 && rj != r1 -+.*:115: Error: g\?csrxchg require rj != r0 && rj != r1 -+.*:116: Error: g\?csrxchg require rj != r0 && rj != r1 -+.*:117: Error: g\?csrxchg require rj != r0 && rj != r1 -diff --git a/gas/testsuite/gas/loongarch/illegal-operand.s b/gas/testsuite/gas/loongarch/illegal-operand.s -new file mode 100644 -index 00000000..3860539d ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/illegal-operand.s -@@ -0,0 +1,117 @@ -+# Illegal operand of atomic memory access instruction. -+amcas.b $r1,$r1,$r2 -+amcas.b $r1,$r2,$r1 -+amcas.h $r1,$r1,$r2 -+amcas.h $r1,$r2,$r1 -+amcas.w $r1,$r1,$r2 -+amcas.w $r1,$r2,$r1 -+amcas.d $r1,$r1,$r2 -+amcas.d $r1,$r2,$r1 -+amcas_db.b $r1,$r1,$r2 -+amcas_db.b $r1,$r2,$r1 -+amcas_db.h $r1,$r1,$r2 -+amcas_db.h $r1,$r2,$r1 -+amcas_db.w $r1,$r1,$r2 -+amcas_db.w $r1,$r2,$r1 -+amcas_db.d $r1,$r1,$r2 -+amcas_db.d $r1,$r2,$r1 -+amswap.b $r1,$r1,$r2 -+amswap.b $r1,$r2,$r1 -+amswap.h $r1,$r1,$r2 -+amswap.h $r1,$r2,$r1 -+amadd.b $r1,$r1,$r2 -+amadd.b $r1,$r2,$r1 -+amadd.h $r1,$r1,$r2 -+amadd.h $r1,$r2,$r1 -+amswap_db.b $r1,$r1,$r2 -+amswap_db.b $r1,$r2,$r1 -+amswap_db.h $r1,$r1,$r2 -+amswap_db.h $r1,$r2,$r1 -+amadd_db.b $r1,$r1,$r2 -+amadd_db.b $r1,$r2,$r1 -+amadd_db.h $r1,$r1,$r2 -+amadd_db.h $r1,$r2,$r1 -+amswap.w $r1,$r1,$r2 -+amswap.w $r1,$r2,$r1 -+amswap.d $r1,$r1,$r2 -+amswap.d $r1,$r2,$r1 -+amadd.w $r1,$r1,$r2 -+amadd.w $r1,$r2,$r1 -+amadd.d $r1,$r1,$r2 -+amadd.d $r1,$r2,$r1 -+amand.w $r1,$r1,$r2 -+amand.w $r1,$r2,$r1 -+amand.d $r1,$r1,$r2 -+amand.d $r1,$r2,$r1 -+amor.w $r1,$r1,$r2 -+amor.w $r1,$r2,$r1 -+amor.d $r1,$r1,$r2 -+amor.d $r1,$r2,$r1 -+amxor.w $r1,$r1,$r2 -+amxor.w $r1,$r2,$r1 -+amxor.d $r1,$r1,$r2 -+amxor.d $r1,$r2,$r1 -+ammax.w $r1,$r1,$r2 -+ammax.w $r1,$r2,$r1 -+ammax.d $r1,$r1,$r2 -+ammax.d $r1,$r2,$r1 -+ammin.w $r1,$r1,$r2 -+ammin.w $r1,$r2,$r1 -+ammin.d $r1,$r1,$r2 -+ammin.d $r1,$r2,$r1 -+ammax.wu $r1,$r1,$r2 -+ammax.wu $r1,$r2,$r1 -+ammax.du $r1,$r1,$r2 -+ammax.du $r1,$r2,$r1 -+ammin.wu $r1,$r1,$r2 -+ammin.wu $r1,$r2,$r1 -+ammin.du $r1,$r1,$r2 -+ammin.du $r1,$r2,$r1 -+amswap_db.w $r1,$r1,$r2 -+amswap_db.w $r1,$r2,$r1 -+amswap_db.d $r1,$r1,$r2 -+amswap_db.d $r1,$r2,$r1 -+amadd_db.w $r1,$r1,$r2 -+amadd_db.w $r1,$r2,$r1 -+amadd_db.d $r1,$r1,$r2 -+amadd_db.d $r1,$r2,$r1 -+amand_db.w $r1,$r1,$r2 -+amand_db.w $r1,$r2,$r1 -+amand_db.d $r1,$r1,$r2 -+amand_db.d $r1,$r2,$r1 -+amor_db.w $r1,$r1,$r2 -+amor_db.w $r1,$r2,$r1 -+amor_db.d $r1,$r1,$r2 -+amor_db.d $r1,$r2,$r1 -+amxor_db.w $r1,$r1,$r2 -+amxor_db.w $r1,$r2,$r1 -+amxor_db.d $r1,$r1,$r2 -+amxor_db.d $r1,$r2,$r1 -+ammax_db.w $r1,$r1,$r2 -+ammax_db.w $r1,$r2,$r1 -+ammax_db.d $r1,$r1,$r2 -+ammax_db.d $r1,$r2,$r1 -+ammin_db.w $r1,$r1,$r2 -+ammin_db.w $r1,$r2,$r1 -+ammin_db.d $r1,$r1,$r2 -+ammin_db.d $r1,$r2,$r1 -+ammax_db.wu $r1,$r1,$r2 -+ammax_db.wu $r1,$r2,$r1 -+ammax_db.du $r1,$r1,$r2 -+ammax_db.du $r1,$r2,$r1 -+ammin_db.wu $r1,$r1,$r2 -+ammin_db.wu $r1,$r2,$r1 -+ammin_db.du $r1,$r1,$r2 -+ammin_db.du $r1,$r2,$r1 -+ -+# Illegal operand of bstr(ins|pick).[wd] -+bstrins.w $r1,$r2,0,8 -+bstrins.d $r1,$r2,0,8 -+bstrpick.w $r1,$r2,0,8 -+bstrpick.d $r1,$r2,0,8 -+ -+# Illegal operand of csrxchg/gcsrxchg -+csrxchg $r0,$r0,1 -+csrxchg $r0,$r1,1 -+gcsrxchg $r0,$r0,1 -+gcsrxchg $r0,$r1,1 -diff --git a/gas/testsuite/gas/loongarch/loongarch.exp b/gas/testsuite/gas/loongarch/loongarch.exp -index 1051a541..a2ccfb13 100644 ---- a/gas/testsuite/gas/loongarch/loongarch.exp -+++ b/gas/testsuite/gas/loongarch/loongarch.exp -@@ -32,4 +32,8 @@ if [istarget loongarch*-*-*] { - - run_list_test "align" - run_list_test "reg-s9" -+ -+ if [istarget loongarch64-*-*] { -+ run_list_test "illegal-operand" -+ } - } -diff --git a/gas/testsuite/gas/loongarch/lvz-lbt.d b/gas/testsuite/gas/loongarch/lvz-lbt.d -index f8970776..760066a0 100644 ---- a/gas/testsuite/gas/loongarch/lvz-lbt.d -+++ b/gas/testsuite/gas/loongarch/lvz-lbt.d -@@ -10,7 +10,7 @@ Disassembly of section .text: - 00000000.* <.text>: - [ ]*0:[ ]*05000400[ ]*gcsrrd[ ]*\$zero,[ ]*0x1[ ]* - [ ]*4:[ ]*05000420[ ]*gcsrwr[ ]*\$zero,[ ]*0x1[ ]* --[ ]*8:[ ]*05000420[ ]*gcsrwr[ ]*\$zero,[ ]*0x1[ ]* -+[ ]*8:[ ]*05000440[ ]*gcsrxchg[ ]*\$zero,[ ]*\$tp,[ ]*0x1[ ]* - [ ]*c:[ ]*06482401[ ]*gtlbflush[ ]* - [ ]*10:[ ]*002b8001[ ]*hvcl[ ]*0x1[ ]* - [ ]*14:[ ]*00000820[ ]*movgr2scr[ ]*\$scr0,[ ]*\$ra[ ]* -diff --git a/gas/testsuite/gas/loongarch/lvz-lbt.s b/gas/testsuite/gas/loongarch/lvz-lbt.s -index 64469a43..2e5089e4 100644 ---- a/gas/testsuite/gas/loongarch/lvz-lbt.s -+++ b/gas/testsuite/gas/loongarch/lvz-lbt.s -@@ -1,6 +1,6 @@ - gcsrrd $r0, 1 - gcsrwr $r0, 1 --gcsrxchg $r0, $r1, 1 -+gcsrxchg $r0, $r2, 1 - gtlbflush - hvcl 1 - movgr2scr $scr0, $r1 --- -2.33.0 - diff --git a/LoongArch-TLS-IE-needs-only-one-dynamic-reloc.patch b/LoongArch-TLS-IE-needs-only-one-dynamic-reloc.patch deleted file mode 100644 index 072510f..0000000 --- a/LoongArch-TLS-IE-needs-only-one-dynamic-reloc.patch +++ /dev/null @@ -1,201 +0,0 @@ -From 35938863d51f469f5bc715b3a7aa6f2a0eb150a6 Mon Sep 17 00:00:00 2001 -From: Xi Ruoyao -Date: Wed, 19 Jun 2024 14:04:18 +0800 -Subject: [PATCH 092/123] LoongArch: TLS IE needs only one dynamic reloc - -As the comment in the code says, TLS_IE needs only one dynamic reloc. -But commit b67a17aa7c0c ("LoongArch: Fix the issue of excessive -relocation generated by GD and IE") has incorrectly allocated the space -for two dynamic relocs, causing libc.so to contain 8 R_LARCH_NONE. - -Adjust tlsdesc-dso.d for the offset changes and add two tests to ensure -there are no R_LARCH_NONE with TLS. - -Signed-off-by: Xi Ruoyao ---- - bfd/elfnn-loongarch.c | 2 +- - ld/testsuite/ld-loongarch-elf/desc-ie-reloc.d | 9 ++ - ld/testsuite/ld-loongarch-elf/desc-ie.d | 8 +- - .../ld-loongarch-elf/ld-loongarch-elf.exp | 2 + - .../ld-loongarch-elf/tlsdesc-dso-reloc.d | 9 ++ - ld/testsuite/ld-loongarch-elf/tlsdesc-dso.d | 86 +++++++++---------- - 6 files changed, 68 insertions(+), 48 deletions(-) - create mode 100644 ld/testsuite/ld-loongarch-elf/desc-ie-reloc.d - create mode 100644 ld/testsuite/ld-loongarch-elf/tlsdesc-dso-reloc.d - -diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c -index 9eaad7f4..51e3d311 100644 ---- a/bfd/elfnn-loongarch.c -+++ b/bfd/elfnn-loongarch.c -@@ -1353,7 +1353,7 @@ allocate_dynrelocs (struct elf_link_hash_entry *h, void *inf) - { - s->size += GOT_ENTRY_SIZE; - if (need_reloc) -- htab->elf.srelgot->size += 2 * sizeof (ElfNN_External_Rela); -+ htab->elf.srelgot->size += sizeof (ElfNN_External_Rela); - } - - /* TLS_DESC needs one dynamic reloc and two GOT slot. */ -diff --git a/ld/testsuite/ld-loongarch-elf/desc-ie-reloc.d b/ld/testsuite/ld-loongarch-elf/desc-ie-reloc.d -new file mode 100644 -index 00000000..c7a2f8ed ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/desc-ie-reloc.d -@@ -0,0 +1,9 @@ -+#source: desc-ie.s -+#as: -+#ld: -shared -z norelro --hash-style=both -+#readelf: -Wr -+ -+#failif -+#... -+.* +R_LARCH_NONE +.* -+#... -diff --git a/ld/testsuite/ld-loongarch-elf/desc-ie.d b/ld/testsuite/ld-loongarch-elf/desc-ie.d -index c833b233..0759404b 100644 ---- a/ld/testsuite/ld-loongarch-elf/desc-ie.d -+++ b/ld/testsuite/ld-loongarch-elf/desc-ie.d -@@ -8,7 +8,7 @@ - Disassembly of section .text: - - [0-9a-f]+ : -- +[0-9a-f]+: 1a000084 pcalau12i \$a0, .* -- +[0-9a-f]+: 28cd0084 ld.d \$a0, \$a0, .* -- +[0-9a-f]+: 1a000084 pcalau12i \$a0, .* -- +[0-9a-f]+: 28cd0084 ld.d \$a0, \$a0, .* -+ +[0-9a-f]+: [0-9a-f]+ pcalau12i \$a0, .* -+ +[0-9a-f]+: [0-9a-f]+ ld.d \$a0, \$a0, .* -+ +[0-9a-f]+: [0-9a-f]+ pcalau12i \$a0, .* -+ +[0-9a-f]+: [0-9a-f]+ ld.d \$a0, \$a0, .* -diff --git a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -index 3c8e9195..5d109a4d 100644 ---- a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -+++ b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -@@ -130,7 +130,9 @@ if [istarget "loongarch64-*-*"] { - if [istarget "loongarch64-*-*"] { - if [check_shared_lib_support] { - run_dump_test "desc-ie" -+ run_dump_test "desc-ie-reloc" - run_dump_test "tlsdesc-dso" -+ run_dump_test "tlsdesc-dso-reloc" - run_dump_test "desc-norelax" - run_dump_test "desc-relax" - run_dump_test "data-got" -diff --git a/ld/testsuite/ld-loongarch-elf/tlsdesc-dso-reloc.d b/ld/testsuite/ld-loongarch-elf/tlsdesc-dso-reloc.d -new file mode 100644 -index 00000000..d5afa7c3 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/tlsdesc-dso-reloc.d -@@ -0,0 +1,9 @@ -+#source: tlsdesc-dso.s -+#as: -+#ld: -shared -z norelro --hash-style=both -+#readelf: -Wr -+ -+#failif -+#... -+.* +R_LARCH_NONE +.* -+#... -diff --git a/ld/testsuite/ld-loongarch-elf/tlsdesc-dso.d b/ld/testsuite/ld-loongarch-elf/tlsdesc-dso.d -index 8f66302f..d6997ec9 100644 ---- a/ld/testsuite/ld-loongarch-elf/tlsdesc-dso.d -+++ b/ld/testsuite/ld-loongarch-elf/tlsdesc-dso.d -@@ -9,52 +9,52 @@ - Disassembly of section .text: - - [0-9a-f]+ : -- +[0-9a-f]+: 18021584 pcaddi \$a0, 4268 -- +[0-9a-f]+: 1a000084 pcalau12i \$a0, 4 -- +[0-9a-f]+: 28dd4084 ld.d \$a0, \$a0, 1872 -- +[0-9a-f]+: 18021364 pcaddi \$a0, 4251 -- +[0-9a-f]+: 180213c4 pcaddi \$a0, 4254 -- +[0-9a-f]+: 28c00081 ld.d \$ra, \$a0, 0 -- +[0-9a-f]+: 4c000021 jirl \$ra, \$ra, 0 -- +[0-9a-f]+: 1a000084 pcalau12i \$a0, 4 -- +[0-9a-f]+: 28dc0084 ld.d \$a0, \$a0, 1792 -- +[0-9a-f]+: 1a000084 pcalau12i \$a0, 4 -- +[0-9a-f]+: 28dc0084 ld.d \$a0, \$a0, 1792 -- +[0-9a-f]+: 18021364 pcaddi \$a0, 4251 -- +[0-9a-f]+: 180213c4 pcaddi \$a0, 4254 -- +[0-9a-f]+: 28c00081 ld.d \$ra, \$a0, 0 -- +[0-9a-f]+: 4c000021 jirl \$ra, \$ra, 0 -- +[0-9a-f]+: 1a000084 pcalau12i \$a0, 4 -- +[0-9a-f]+: 28dce084 ld.d \$a0, \$a0, 1848 -+ +[0-9a-f]+: [0-9a-f]+ pcaddi \$a0, .* -+ +[0-9a-f]+: [0-9a-f]+ pcalau12i \$a0, .* -+ +[0-9a-f]+: [0-9a-f]+ ld.d \$a0, \$a0, .* -+ +[0-9a-f]+: [0-9a-f]+ pcaddi \$a0, .* -+ +[0-9a-f]+: [0-9a-f]+ pcaddi \$a0, .* -+ +[0-9a-f]+: [0-9a-f]+ ld.d \$ra, \$a0, .* -+ +[0-9a-f]+: [0-9a-f]+ jirl \$ra, \$ra, .* -+ +[0-9a-f]+: [0-9a-f]+ pcalau12i \$a0, .* -+ +[0-9a-f]+: [0-9a-f]+ ld.d \$a0, \$a0, .* -+ +[0-9a-f]+: [0-9a-f]+ pcalau12i \$a0, .* -+ +[0-9a-f]+: [0-9a-f]+ ld.d \$a0, \$a0, .* -+ +[0-9a-f]+: [0-9a-f]+ pcaddi \$a0, .* -+ +[0-9a-f]+: [0-9a-f]+ pcaddi \$a0, .* -+ +[0-9a-f]+: [0-9a-f]+ ld.d \$ra, \$a0, .* -+ +[0-9a-f]+: [0-9a-f]+ jirl \$ra, \$ra, .* -+ +[0-9a-f]+: [0-9a-f]+ pcalau12i \$a0, .* -+ +[0-9a-f]+: [0-9a-f]+ ld.d \$a0, \$a0, .* - - [0-9a-f]+ : -- +[0-9a-f]+: 1a000084 pcalau12i \$a0, 4 -- +[0-9a-f]+: 28daa084 ld.d \$a0, \$a0, 1704 -- +[0-9a-f]+: 18020de4 pcaddi \$a0, 4207 -- +[0-9a-f]+: 18020f04 pcaddi \$a0, 4216 -- +[0-9a-f]+: 28c00081 ld.d \$ra, \$a0, 0 -- +[0-9a-f]+: 4c000021 jirl \$ra, \$ra, 0 -- +[0-9a-f]+: 18020e24 pcaddi \$a0, 4209 -- +[0-9a-f]+: 1a000084 pcalau12i \$a0, 4 -- +[0-9a-f]+: 28db4084 ld.d \$a0, \$a0, 1744 -- +[0-9a-f]+: 1a000084 pcalau12i \$a0, 4 -- +[0-9a-f]+: 28db4084 ld.d \$a0, \$a0, 1744 -- +[0-9a-f]+: 18020f44 pcaddi \$a0, 4218 -- +[0-9a-f]+: 28c00081 ld.d \$ra, \$a0, 0 -- +[0-9a-f]+: 4c000021 jirl \$ra, \$ra, 0 -- +[0-9a-f]+: 18020e64 pcaddi \$a0, 4211 -- +[0-9a-f]+: 1a000084 pcalau12i \$a0, 4 -- +[0-9a-f]+: 28dba084 ld.d \$a0, \$a0, 1768 -+ +[0-9a-f]+: [0-9a-f]+ pcalau12i \$a0, .* -+ +[0-9a-f]+: [0-9a-f]+ ld.d \$a0, \$a0, .* -+ +[0-9a-f]+: [0-9a-f]+ pcaddi \$a0, .* -+ +[0-9a-f]+: [0-9a-f]+ pcaddi \$a0, .* -+ +[0-9a-f]+: [0-9a-f]+ ld.d \$ra, \$a0, .* -+ +[0-9a-f]+: [0-9a-f]+ jirl \$ra, \$ra, .* -+ +[0-9a-f]+: [0-9a-f]+ pcaddi \$a0, .* -+ +[0-9a-f]+: [0-9a-f]+ pcalau12i \$a0, .* -+ +[0-9a-f]+: [0-9a-f]+ ld.d \$a0, \$a0, .* -+ +[0-9a-f]+: [0-9a-f]+ pcalau12i \$a0, .* -+ +[0-9a-f]+: [0-9a-f]+ ld.d \$a0, \$a0, .* -+ +[0-9a-f]+: [0-9a-f]+ pcaddi \$a0, .* -+ +[0-9a-f]+: [0-9a-f]+ ld.d \$ra, \$a0, .* -+ +[0-9a-f]+: [0-9a-f]+ jirl \$ra, \$ra, .* -+ +[0-9a-f]+: [0-9a-f]+ pcaddi \$a0, .* -+ +[0-9a-f]+: [0-9a-f]+ pcalau12i \$a0, .* -+ +[0-9a-f]+: [0-9a-f]+ ld.d \$a0, \$a0, .* - - [0-9a-f]+ : -- +[0-9a-f]+: 18020ec4 pcaddi \$a0, 4214 -- +[0-9a-f]+: 28c00081 ld.d \$ra, \$a0, 0 -- +[0-9a-f]+: 4c000021 jirl \$ra, \$ra, 0 -+ +[0-9a-f]+: [0-9a-f]+ pcaddi \$a0, .* -+ +[0-9a-f]+: [0-9a-f]+ ld.d \$ra, \$a0, .* -+ +[0-9a-f]+: [0-9a-f]+ jirl \$ra, \$ra, .* - - [0-9a-f]+ : -- +[0-9a-f]+: 18021224 pcaddi \$a0, 4241 -- +[0-9a-f]+: 28c00081 ld.d \$ra, \$a0, 0 -- +[0-9a-f]+: 4c000021 jirl \$ra, \$ra, 0 -- +[0-9a-f]+: 18021144 pcaddi \$a0, 4234 -- +[0-9a-f]+: 28c00081 ld.d \$ra, \$a0, 0 -- +[0-9a-f]+: 4c000021 jirl \$ra, \$ra, 0 -+ +[0-9a-f]+: [0-9a-f]+ pcaddi \$a0, .* -+ +[0-9a-f]+: [0-9a-f]+ ld.d \$ra, \$a0, .* -+ +[0-9a-f]+: [0-9a-f]+ jirl \$ra, \$ra, .* -+ +[0-9a-f]+: [0-9a-f]+ pcaddi \$a0, .* -+ +[0-9a-f]+: [0-9a-f]+ ld.d \$ra, \$a0, .* -+ +[0-9a-f]+: [0-9a-f]+ jirl \$ra, \$ra, .* --- -2.33.0 - diff --git a/LoongArch-The-symbol-got-type-can-only-be-obtained-a.patch b/LoongArch-The-symbol-got-type-can-only-be-obtained-a.patch deleted file mode 100644 index 4988d81..0000000 --- a/LoongArch-The-symbol-got-type-can-only-be-obtained-a.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 6f250e80b7445f58291c273adf8fa03c65939b43 Mon Sep 17 00:00:00 2001 -From: Lulu Cai -Date: Fri, 19 Apr 2024 10:24:52 +0800 -Subject: [PATCH 081/123] LoongArch: The symbol got type can only be obtained - after initialization - -When scanning relocations and determining whether TLS type transition is -possible, it will try to obtain the symbol got type. If the symbol got -type record has not yet been allocated space and initialized, it will -cause ld to crash. So when uninitialized, the symbol is set to GOT_UNKNOWN. ---- - bfd/elfnn-loongarch.c | 9 ++++++++- - 1 file changed, 8 insertions(+), 1 deletion(-) - -diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c -index 70ef28f3..0a7caa2a 100644 ---- a/bfd/elfnn-loongarch.c -+++ b/bfd/elfnn-loongarch.c -@@ -683,7 +683,14 @@ loongarch_can_trans_tls (bfd *input_bfd, - if (! IS_LOONGARCH_TLS_TRANS_RELOC (r_type)) - return false; - -- symbol_tls_type = _bfd_loongarch_elf_tls_type (input_bfd, h, r_symndx); -+ /* Obtaining tls got type here may occur before -+ loongarch_elf_record_tls_and_got_reference, so it is necessary -+ to ensure that tls got type has been initialized, otherwise it -+ is set to GOT_UNKNOWN. */ -+ symbol_tls_type = GOT_UNKNOWN; -+ if (_bfd_loongarch_elf_local_got_tls_type (input_bfd) || h) -+ symbol_tls_type = _bfd_loongarch_elf_tls_type (input_bfd, h, r_symndx); -+ - reloc_got_type = loongarch_reloc_got_type (r_type); - - if (symbol_tls_type == GOT_TLS_IE && GOT_TLS_GD_ANY_P (reloc_got_type)) --- -2.33.0 - diff --git a/LoongArch-Use-tab-to-indent-assembly-in-TLSDESC-test.patch b/LoongArch-Use-tab-to-indent-assembly-in-TLSDESC-test.patch deleted file mode 100644 index fc23333..0000000 --- a/LoongArch-Use-tab-to-indent-assembly-in-TLSDESC-test.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 6f1158c052786ad574d6fdb34db4e1e5ddf90309 Mon Sep 17 00:00:00 2001 -From: Tatsuyuki Ishi -Date: Thu, 28 Dec 2023 23:58:01 +0900 -Subject: [PATCH 046/123] LoongArch: Use tab to indent assembly in TLSDESC test - suite - -The usual convention is to use tabs. Not all test are following this, -but at least when using tabs, let's use it consistently throughout the -file. ---- - gas/testsuite/gas/loongarch/tlsdesc_32.s | 2 +- - gas/testsuite/gas/loongarch/tlsdesc_64.s | 2 +- - 2 files changed, 2 insertions(+), 2 deletions(-) - -diff --git a/gas/testsuite/gas/loongarch/tlsdesc_32.s b/gas/testsuite/gas/loongarch/tlsdesc_32.s -index ef6aee94..2a139c04 100644 ---- a/gas/testsuite/gas/loongarch/tlsdesc_32.s -+++ b/gas/testsuite/gas/loongarch/tlsdesc_32.s -@@ -4,7 +4,7 @@ - # R_LARCH_TLS_DESC_PC_LO12 var - addi.w $a0,$a0,%desc_pc_lo12(var) - # R_LARCH_TLS_DESC_LD var -- ld.w $ra,$a0,%desc_ld(var) -+ ld.w $ra,$a0,%desc_ld(var) - # R_LARCH_TLS_DESC_CALL var - jirl $ra,$ra,%desc_call(var) - -diff --git a/gas/testsuite/gas/loongarch/tlsdesc_64.s b/gas/testsuite/gas/loongarch/tlsdesc_64.s -index 9d0ccb17..9850940e 100644 ---- a/gas/testsuite/gas/loongarch/tlsdesc_64.s -+++ b/gas/testsuite/gas/loongarch/tlsdesc_64.s -@@ -4,7 +4,7 @@ - # R_LARCH_TLS_DESC_PC_LO12 var - addi.d $a0,$a0,%desc_pc_lo12(var) - # R_LARCH_TLS_DESC_LD var -- ld.d $ra,$a0,%desc_ld(var) -+ ld.d $ra,$a0,%desc_ld(var) - # R_LARCH_TLS_DESC_CALL var - jirl $ra,$ra,%desc_call(var) - --- -2.33.0 - diff --git a/LoongArch-add-.option-directive.patch b/LoongArch-add-.option-directive.patch deleted file mode 100644 index b27392e..0000000 --- a/LoongArch-add-.option-directive.patch +++ /dev/null @@ -1,207 +0,0 @@ -From fdb688f870f5d9078de4fe77a7d3fbed57df5b07 Mon Sep 17 00:00:00 2001 -From: Lulu Cai -Date: Tue, 21 May 2024 10:14:27 +0800 -Subject: [PATCH 091/123] LoongArch: add .option directive - -In some cases we may want to use different options only for certain -assembly, so the .option directive is added to control the assembler -options. - -.option can accept 4 parameters: - -push -pop - Pushes or pops the current option stack. They limit the scope of - option changes so that they do not affect other parts of the assembly - file. - -relax -norelax - Enables or disables relaxation. ---- - gas/config/tc-loongarch.c | 59 +++++++++++++++++++ - gas/testsuite/gas/loongarch/loongarch.exp | 1 + - .../gas/loongarch/pseudo_op_option.d | 36 +++++++++++ - .../gas/loongarch/pseudo_op_option.s | 19 ++++++ - .../gas/loongarch/pseudo_op_option_fail.l | 2 + - .../gas/loongarch/pseudo_op_option_fail.s | 2 + - 6 files changed, 119 insertions(+) - create mode 100644 gas/testsuite/gas/loongarch/pseudo_op_option.d - create mode 100644 gas/testsuite/gas/loongarch/pseudo_op_option.s - create mode 100644 gas/testsuite/gas/loongarch/pseudo_op_option_fail.l - create mode 100644 gas/testsuite/gas/loongarch/pseudo_op_option_fail.s - -diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c -index f039d027..72815233 100644 ---- a/gas/config/tc-loongarch.c -+++ b/gas/config/tc-loongarch.c -@@ -541,6 +541,64 @@ s_dtprel (int bytes) - demand_empty_rest_of_line (); - } - -+struct LARCH_option_stack -+{ -+ struct LARCH_option_stack *next; -+ struct loongarch_ASEs_option options; -+}; -+ -+static struct LARCH_option_stack *LARCH_opts_stack = NULL; -+ -+/* Handle the .option pseudo-op. -+ The alignment of .align is done by R_LARCH_ALIGN at link time. -+ If the .align directive is within the range controlled by -+ .option norelax, that is, relax is turned off, R_LARCH_ALIGN -+ cannot be generated, which may cause ld to be unable to handle -+ the alignment. */ -+static void -+s_loongarch_option (int x ATTRIBUTE_UNUSED) -+{ -+ char *name = input_line_pointer, ch; -+ while (!is_end_of_line[(unsigned char) *input_line_pointer]) -+ ++input_line_pointer; -+ ch = *input_line_pointer; -+ *input_line_pointer = '\0'; -+ -+ if (strcmp (name, "relax") == 0) -+ LARCH_opts.relax = 1; -+ else if (strcmp (name, "norelax") == 0) -+ LARCH_opts.relax = 0; -+ else if (strcmp (name, "push") == 0) -+ { -+ struct LARCH_option_stack *s; -+ -+ s = XNEW (struct LARCH_option_stack); -+ s->next = LARCH_opts_stack; -+ s->options = LARCH_opts; -+ LARCH_opts_stack = s; -+ } -+ else if (strcmp (name, "pop") == 0) -+ { -+ struct LARCH_option_stack *s; -+ -+ s = LARCH_opts_stack; -+ if (s == NULL) -+ as_bad (_(".option pop with no .option push")); -+ else -+ { -+ LARCH_opts_stack = s->next; -+ LARCH_opts = s->options; -+ free (s); -+ } -+ } -+ else -+ { -+ as_warn (_("unrecognized .option directive: %s"), name); -+ } -+ *input_line_pointer = ch; -+ demand_empty_rest_of_line (); -+} -+ - static const pseudo_typeS loongarch_pseudo_table[] = - { - { "dword", cons, 8 }, -@@ -548,6 +606,7 @@ static const pseudo_typeS loongarch_pseudo_table[] = - { "half", cons, 2 }, - { "dtprelword", s_dtprel, 4 }, - { "dtpreldword", s_dtprel, 8 }, -+ { "option", s_loongarch_option, 0}, - { NULL, NULL, 0 }, - }; - -diff --git a/gas/testsuite/gas/loongarch/loongarch.exp b/gas/testsuite/gas/loongarch/loongarch.exp -index a2ccfb13..157797c5 100644 ---- a/gas/testsuite/gas/loongarch/loongarch.exp -+++ b/gas/testsuite/gas/loongarch/loongarch.exp -@@ -35,5 +35,6 @@ if [istarget loongarch*-*-*] { - - if [istarget loongarch64-*-*] { - run_list_test "illegal-operand" -+ run_list_test "pseudo_op_option_fail" - } - } -diff --git a/gas/testsuite/gas/loongarch/pseudo_op_option.d b/gas/testsuite/gas/loongarch/pseudo_op_option.d -new file mode 100644 -index 00000000..53921a1e ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/pseudo_op_option.d -@@ -0,0 +1,36 @@ -+#as: -mrelax -+#objdump: -dr -+#skip: loongarch32-*-* -+ -+.*: file format .* -+ -+ -+Disassembly of section .text: -+ -+0.* <.text>: -+ 0: 1a000004 pcalau12i \$a0, 0 -+ 0: R_LARCH_PCALA_HI20 x -+ 0: R_LARCH_RELAX \*ABS\* -+ 4: 02c00084 addi.d \$a0, \$a0, 0 -+ 4: R_LARCH_PCALA_LO12 x -+ 4: R_LARCH_RELAX \*ABS\* -+ 8: 1a000004 pcalau12i \$a0, 0 -+ 8: R_LARCH_PCALA_HI20 x -+ c: 02c00084 addi.d \$a0, \$a0, 0 -+ c: R_LARCH_PCALA_LO12 x -+ 10: 1a000004 pcalau12i \$a0, 0 -+ 10: R_LARCH_PCALA_HI20 x -+ 10: R_LARCH_RELAX \*ABS\* -+ 14: 02c00084 addi.d \$a0, \$a0, 0 -+ 14: R_LARCH_PCALA_LO12 x -+ 14: R_LARCH_RELAX \*ABS\* -+ 18: 1a000004 pcalau12i \$a0, 0 -+ 18: R_LARCH_PCALA_HI20 x -+ 1c: 02c00084 addi.d \$a0, \$a0, 0 -+ 1c: R_LARCH_PCALA_LO12 x -+ 20: 1a000004 pcalau12i \$a0, 0 -+ 20: R_LARCH_PCALA_HI20 x -+ 20: R_LARCH_RELAX \*ABS\* -+ 24: 02c00084 addi.d \$a0, \$a0, 0 -+ 24: R_LARCH_PCALA_LO12 x -+ 24: R_LARCH_RELAX \*ABS\* -diff --git a/gas/testsuite/gas/loongarch/pseudo_op_option.s b/gas/testsuite/gas/loongarch/pseudo_op_option.s -new file mode 100644 -index 00000000..f21b7263 ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/pseudo_op_option.s -@@ -0,0 +1,19 @@ -+# Gas enables relax by default. -+# Push and pop can be nested, and each pop restores the options before -+# the most recent push. -+ .text -+.L1: -+ la.pcrel $a0,x -+ -+ .option push -+ .option norelax -+ la.pcrel $a0,x -+ -+ .option push -+ .option relax -+ la.pcrel $a0,x -+ .option pop -+ -+ la.pcrel $a0,x -+ .option pop -+ la.pcrel $a0,x -diff --git a/gas/testsuite/gas/loongarch/pseudo_op_option_fail.l b/gas/testsuite/gas/loongarch/pseudo_op_option_fail.l -new file mode 100644 -index 00000000..ffb9a72e ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/pseudo_op_option_fail.l -@@ -0,0 +1,2 @@ -+.*: Assembler messages: -+.*: Error: \.option pop with no \.option push -diff --git a/gas/testsuite/gas/loongarch/pseudo_op_option_fail.s b/gas/testsuite/gas/loongarch/pseudo_op_option_fail.s -new file mode 100644 -index 00000000..e368cdba ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/pseudo_op_option_fail.s -@@ -0,0 +1,2 @@ -+ .text -+ .option pop --- -2.33.0 - diff --git a/LoongArch-bfd-Add-support-for-tls-le-relax.patch b/LoongArch-bfd-Add-support-for-tls-le-relax.patch deleted file mode 100644 index b9ad9eb..0000000 --- a/LoongArch-bfd-Add-support-for-tls-le-relax.patch +++ /dev/null @@ -1,345 +0,0 @@ -From 7bba42c3fe6dd98cf8f08fc13fcc246f4c7aee90 Mon Sep 17 00:00:00 2001 -From: changjiachen -Date: Thu, 28 Dec 2023 20:07:54 +0800 -Subject: [PATCH 031/123] LoongArch: bfd: Add support for tls le relax. - -Add tls le relax support and related relocs in bfd. - -New relocation related explanation can refer to the following url: -https://github.com/loongson/la-abi-specs/blob/release/laelf.adoc - -This support does two main things: - -1. Implement support for three new relocation items in bfd. - -The three new relocation items are shown below: - -R_LARCH_TLS_LE_ADD_R -R_LARCH_TLS_LE_HI20_R -R_LARCH_TLS_LE_LO12_R - -2. ADD a new macro RELOCATE_TLS_TP32_HI20 - -Handle problems caused by symbol extensions in TLS LE, The processing -is similar to the macro RELOCATE_CALC_PC32_HI20 method. - -3. Implement the tls le relax function. - -bfd/ChangeLog: - - * bfd-in2.h: Add relocs related to tls le relax. - * elfnn-loongarch.c: - (loongarch_relax_tls_le): New function. - (RELOCATE_TLS_TP32_HI20): New macro. - (loongarch_elf_check_relocs): Add new reloc support. - (perform_relocation): Likewise. - (loongarch_elf_relocate_section): Handle new relocs related to relax. - (loongarch_elf_relax_section): Likewise. - * elfxx-loongarch.c: - (LOONGARCH_HOWTO (R_LARCH_TLS_LE_ADD_R)): New reloc how to type. - (LOONGARCH_HOWTO (R_LARCH_TLS_LE_HI20_R)): Likewise. - (LOONGARCH_HOWTO (R_LARCH_TLS_LE_LO12_R)): Likewise. - * libbfd.h: Add relocs related to tls le relax. - * reloc.c: Likewise. ---- - bfd/bfd-in2.h | 4 ++ - bfd/elfnn-loongarch.c | 105 ++++++++++++++++++++++++++++++++++++++++++ - bfd/elfxx-loongarch.c | 55 ++++++++++++++++++++-- - bfd/libbfd.h | 3 ++ - bfd/reloc.c | 7 +++ - 5 files changed, 169 insertions(+), 5 deletions(-) - -diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h -index d7b762d4..4e7ad048 100644 ---- a/bfd/bfd-in2.h -+++ b/bfd/bfd-in2.h -@@ -7356,11 +7356,15 @@ assembler and not (currently) written to any object files. */ - BFD_RELOC_LARCH_TLS_DESC64_HI12, - BFD_RELOC_LARCH_TLS_DESC_LD, - BFD_RELOC_LARCH_TLS_DESC_CALL, -+ BFD_RELOC_LARCH_TLS_LE_HI20_R, -+ BFD_RELOC_LARCH_TLS_LE_ADD_R, -+ BFD_RELOC_LARCH_TLS_LE_LO12_R, - BFD_RELOC_LARCH_TLS_LD_PCREL20_S2, - BFD_RELOC_LARCH_TLS_GD_PCREL20_S2, - BFD_RELOC_LARCH_TLS_DESC_PCREL20_S2, - BFD_RELOC_UNUSED - }; -+ - typedef enum bfd_reloc_code_real bfd_reloc_code_real_type; - - reloc_howto_type *bfd_reloc_type_lookup -diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c -index d46bcd77..f7eb66da 100644 ---- a/bfd/elfnn-loongarch.c -+++ b/bfd/elfnn-loongarch.c -@@ -858,6 +858,7 @@ loongarch_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, - break; - - case R_LARCH_TLS_LE_HI20: -+ case R_LARCH_TLS_LE_HI20_R: - case R_LARCH_SOP_PUSH_TLS_TPREL: - if (!bfd_link_executable (info)) - return false; -@@ -2261,6 +2262,8 @@ perform_relocation (const Elf_Internal_Rela *rel, asection *input_section, - case R_LARCH_GOT64_HI12: - case R_LARCH_TLS_LE_HI20: - case R_LARCH_TLS_LE_LO12: -+ case R_LARCH_TLS_LE_HI20_R: -+ case R_LARCH_TLS_LE_LO12_R: - case R_LARCH_TLS_LE64_LO20: - case R_LARCH_TLS_LE64_HI12: - case R_LARCH_TLS_IE_PC_HI20: -@@ -2303,6 +2306,7 @@ perform_relocation (const Elf_Internal_Rela *rel, asection *input_section, - break; - - case R_LARCH_RELAX: -+ case R_LARCH_TLS_LE_ADD_R: - break; - - default: -@@ -2483,6 +2487,16 @@ loongarch_reloc_is_fatal (struct bfd_link_info *info, - relocation += 0x1000; \ - }) - -+/* Handle problems caused by symbol extensions in TLS LE, The processing -+ is similar to the macro RELOCATE_CALC_PC32_HI20 method. */ -+#define RELOCATE_TLS_TP32_HI20(relocation) \ -+ ({ \ -+ bfd_vma __lo = (relocation) & ((bfd_vma)0xfff); \ -+ if (__lo > 0x7ff) \ -+ relocation += 0x800; \ -+ relocation = relocation & ~(bfd_vma)0xfff; \ -+ }) -+ - /* For example: pc is 0x11000010000100, symbol is 0x1812348ffff812 - offset = (0x1812348ffff812 & ~0xfff) - (0x11000010000100 & ~0xfff) - = 0x712347ffff000 -@@ -3474,6 +3488,13 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, - - break; - -+ case R_LARCH_TLS_LE_HI20_R: -+ relocation -= elf_hash_table (info)->tls_sec->vma; -+ -+ RELOCATE_TLS_TP32_HI20 (relocation); -+ -+ break; -+ - case R_LARCH_PCALA_LO12: - /* Not support if sym_addr in 2k page edge. - pcalau12i pc_hi20 (sym_addr) -@@ -3644,6 +3665,7 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, - - case R_LARCH_TLS_LE_HI20: - case R_LARCH_TLS_LE_LO12: -+ case R_LARCH_TLS_LE_LO12_R: - case R_LARCH_TLS_LE64_LO20: - case R_LARCH_TLS_LE64_HI12: - BFD_ASSERT (resolved_local && elf_hash_table (info)->tls_sec); -@@ -4082,6 +4104,82 @@ loongarch_relax_delete_bytes (bfd *abfd, - - return true; - } -+/* Relax tls le, mainly relax the process of getting TLS le symbolic addresses. -+ there are three situations in which an assembly instruction sequence needs to -+ be relaxed: -+ symbol address = tp + offset (symbol),offset (symbol) = le_hi20_r + le_lo12_r -+ -+ Case 1: -+ in this case, the rd register in the st.{w/d} instruction does not store the -+ full tls symbolic address, but tp + le_hi20_r, which is a part of the tls -+ symbolic address, and then obtains the rd + le_lo12_r address through the -+ st.w instruction feature. -+ this is the full tls symbolic address (tp + le_hi20_r + le_lo12_r). -+ -+ before relax: after relax: -+ -+ lu12i.w $rd,%le_hi20_r (sym) ==> (instruction deleted) -+ add.{w/d} $rd,$rd,$tp,%le_add_r (sym) ==> (instruction deleted) -+ st.{w/d} $rs,$rd,%le_lo12_r (sym) ==> st.{w/d} $rs,$tp,%le_lo12_r (sym) -+ -+ Case 2: -+ in this case, ld.{w/d} is similar to st.{w/d} in case1. -+ -+ before relax: after relax: -+ -+ lu12i.w $rd,%le_hi20_r (sym) ==> (instruction deleted) -+ add.{w/d} $rd,$rd,$tp,%le_add_r (sym) ==> (instruction deleted) -+ ld.{w/d} $rs,$rd,%le_lo12_r (sym) ==> ld.{w/d} $rs,$tp,%le_lo12_r (sym) -+ -+ Case 3: -+ in this case,the rs register in addi.{w/d} stores the full address of the tls -+ symbol (tp + le_hi20_r + le_lo12_r). -+ -+ before relax: after relax: -+ -+ lu12i.w $rd,%le_hi20_r (sym) ==> (instruction deleted) -+ add.{w/d} $rd,$rd,$tp,%le_add_r (sym) ==> (instruction deleted) -+ addi.{w/d} $rs,$rd,%le_lo12_r (sym) ==> addi.{w/d} $rs,$tp,%le_lo12_r (sym) -+*/ -+static bool -+loongarch_relax_tls_le (bfd *abfd, asection *sec, -+ Elf_Internal_Rela *rel, -+ struct bfd_link_info *link_info, -+ bfd_vma symval) -+{ -+ bfd_byte *contents = elf_section_data (sec)->this_hdr.contents; -+ uint32_t insn = bfd_get (32, abfd, contents + rel->r_offset); -+ static uint32_t insn_rj,insn_rd; -+ symval = symval - elf_hash_table (link_info)->tls_sec->vma; -+ /* Whether the symbol offset is in the interval (offset < 0x800). */ -+ if (ELFNN_R_TYPE ((rel + 1)->r_info == R_LARCH_RELAX) && (symval < 0x800)) -+ { -+ switch (ELFNN_R_TYPE (rel->r_info)) -+ { -+ case R_LARCH_TLS_LE_HI20_R: -+ case R_LARCH_TLS_LE_ADD_R: -+ /* delete insn. */ -+ rel->r_info = ELFNN_R_INFO (0, R_LARCH_NONE); -+ loongarch_relax_delete_bytes (abfd, sec, rel->r_offset, 4, link_info); -+ break; -+ case R_LARCH_TLS_LE_LO12_R: -+ /* Change rj to $tp. */ -+ insn_rj = 0x2 << 5; -+ /* Get rd register. */ -+ insn_rd = insn & 0x1f; -+ /* Write symbol offset. */ -+ symval <<= 10; -+ /* Writes the modified instruction. */ -+ insn = insn & 0xffc00000; -+ insn = insn | symval | insn_rj | insn_rd; -+ bfd_put (32, abfd, insn, contents + rel->r_offset); -+ break; -+ default: -+ break; -+ } -+ } -+ return true; -+} - - /* Relax pcalau12i,addi.d => pcaddi. */ - static bool -@@ -4511,6 +4609,13 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, - rel->r_info = ELFNN_R_INFO (0, R_LARCH_NONE); - } - break; -+ case R_LARCH_TLS_LE_HI20_R: -+ case R_LARCH_TLS_LE_LO12_R: -+ case R_LARCH_TLS_LE_ADD_R: -+ if (0 == info->relax_pass && (i + 2) <= sec->reloc_count) -+ loongarch_relax_tls_le (abfd, sec, rel, info, symval); -+ break; -+ - case R_LARCH_PCALA_HI20: - if (0 == info->relax_pass && (i + 4) <= sec->reloc_count) - loongarch_relax_pcala_addi (abfd, sec, sym_sec, rel, symval, -diff --git a/bfd/elfxx-loongarch.c b/bfd/elfxx-loongarch.c -index 4fe8cbff..2c40fb02 100644 ---- a/bfd/elfxx-loongarch.c -+++ b/bfd/elfxx-loongarch.c -@@ -1776,9 +1776,56 @@ static loongarch_reloc_howto_type loongarch_howto_table[] = - NULL, /* adjust_reloc_bits. */ - "desc_call"), /* larch_reloc_type_name. */ - -- LOONGARCH_EMPTY_HOWTO (121), -- LOONGARCH_EMPTY_HOWTO (122), -- LOONGARCH_EMPTY_HOWTO (123), -+ LOONGARCH_HOWTO (R_LARCH_TLS_LE_HI20_R, /* type (121). */ -+ 12, /* rightshift. */ -+ 4, /* size. */ -+ 20, /* bitsize. */ -+ false, /* pc_relative. */ -+ 5, /* bitpos. */ -+ complain_overflow_signed, /* complain_on_overflow. */ -+ bfd_elf_generic_reloc, /* special_function. */ -+ "R_LARCH_TLS_LE_HI20_R", /* name. */ -+ false, /* partial_inplace. */ -+ 0, /* src_mask. */ -+ 0x1ffffe0, /* dst_mask. */ -+ false, /* pcrel_offset. */ -+ BFD_RELOC_LARCH_TLS_LE_HI20_R, /* bfd_reloc_code_real_type. */ -+ reloc_bits, /* adjust_reloc_bits. */ -+ "le_hi20_r"), /* larch_reloc_type_name. */ -+ -+ LOONGARCH_HOWTO (R_LARCH_TLS_LE_ADD_R, /* type (122). */ -+ 0, /* rightshift. */ -+ 0, /* size. */ -+ 0, /* bitsize. */ -+ false, /* pc_relative. */ -+ 0, /* bitpos. */ -+ complain_overflow_dont, /* complain_on_overflow. */ -+ bfd_elf_generic_reloc, /* special_function. */ -+ "R_LARCH_TLS_LE_ADD_R", /* name. */ -+ false, /* partial_inplace. */ -+ 0, /* src_mask. */ -+ 0, /* dst_mask. */ -+ false, /* pcrel_offset. */ -+ BFD_RELOC_LARCH_TLS_LE_ADD_R, /* bfd_reloc_code_real_type. */ -+ NULL, /* adjust_reloc_bits. */ -+ "le_add_r"), /* larch_reloc_type_name. */ -+ -+ LOONGARCH_HOWTO (R_LARCH_TLS_LE_LO12_R, /* type (123). */ -+ 0, /* rightshift. */ -+ 4, /* size. */ -+ 12, /* bitsize. */ -+ false, /* pc_relative. */ -+ 10, /* bitpos. */ -+ complain_overflow_signed, /* complain_on_overflow. */ -+ bfd_elf_generic_reloc, /* special_function. */ -+ "R_LARCH_TLS_LE_LO12_R", /* name. */ -+ false, /* partial_inplace. */ -+ 0, /* src_mask. */ -+ 0x3ffc00, /* dst_mask. */ -+ false, /* pcrel_offset. */ -+ BFD_RELOC_LARCH_TLS_LE_LO12_R, /* bfd_reloc_code_real_type. */ -+ reloc_bits, /* adjust_reloc_bits. */ -+ "le_lo12_r"), /* larch_reloc_type_name. */ - - /* For pcaddi, ld_pc_hi20 + ld_pc_lo12 can relax to ld_pcrel20_s2. */ - LOONGARCH_HOWTO (R_LARCH_TLS_LD_PCREL20_S2, /* type (124). */ -@@ -1870,9 +1917,7 @@ reloc_howto_type * - loongarch_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED, - bfd_reloc_code_real_type code) - { -- /* - BFD_ASSERT (ARRAY_SIZE (loongarch_howto_table) == R_LARCH_count); -- */ - - /* Fast search for new reloc types. */ - if (BFD_RELOC_LARCH_B16 <= code && code < BFD_RELOC_LARCH_RELAX) -diff --git a/bfd/libbfd.h b/bfd/libbfd.h -index b5af327f..617d5239 100644 ---- a/bfd/libbfd.h -+++ b/bfd/libbfd.h -@@ -3538,6 +3538,9 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@", - "BFD_RELOC_LARCH_TLS_DESC64_HI12", - "BFD_RELOC_LARCH_TLS_DESC_LD", - "BFD_RELOC_LARCH_TLS_DESC_CALL", -+ "BFD_RELOC_LARCH_TLS_LE_HI20_R", -+ "BFD_RELOC_LARCH_TLS_LE_ADD_R", -+ "BFD_RELOC_LARCH_TLS_LE_LO12_R", - "BFD_RELOC_LARCH_TLS_LD_PCREL20_S2", - "BFD_RELOC_LARCH_TLS_GD_PCREL20_S2", - "BFD_RELOC_LARCH_TLS_DESC_PCREL20_S2", -diff --git a/bfd/reloc.c b/bfd/reloc.c -index 4782f0f6..bb45027c 100644 ---- a/bfd/reloc.c -+++ b/bfd/reloc.c -@@ -8188,6 +8188,13 @@ ENUMX - ENUMX - BFD_RELOC_LARCH_TLS_DESC_CALL - -+ENUMX -+ BFD_RELOC_LARCH_TLS_LE_HI20_R -+ENUMX -+ BFD_RELOC_LARCH_TLS_LE_ADD_R -+ENUMX -+ BFD_RELOC_LARCH_TLS_LE_LO12_R -+ - ENUMX - BFD_RELOC_LARCH_TLS_LD_PCREL20_S2 - ENUMX --- -2.33.0 - diff --git a/LoongArch-bfd-Correct-the-name-of-R_LARCH_SOP_POP_32.patch b/LoongArch-bfd-Correct-the-name-of-R_LARCH_SOP_POP_32.patch deleted file mode 100644 index 30cc313..0000000 --- a/LoongArch-bfd-Correct-the-name-of-R_LARCH_SOP_POP_32.patch +++ /dev/null @@ -1,26 +0,0 @@ -From af43295f92b7f2c85f9613481eb92efcd348f5be Mon Sep 17 00:00:00 2001 -From: Jinyang He -Date: Tue, 5 Sep 2023 10:31:27 +0800 -Subject: [PATCH 057/123] LoongArch: bfd: Correct the name of - R_LARCH_SOP_POP_32_U in howto_table - ---- - bfd/elfxx-loongarch.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/bfd/elfxx-loongarch.c b/bfd/elfxx-loongarch.c -index 2c40fb02..fe38f369 100644 ---- a/bfd/elfxx-loongarch.c -+++ b/bfd/elfxx-loongarch.c -@@ -548,7 +548,7 @@ static loongarch_reloc_howto_type loongarch_howto_table[] = - 0, /* bitpos. */ - complain_overflow_unsigned, /* complain_on_overflow. */ - bfd_elf_generic_reloc, /* special_function. */ -- "R_LARCH_SOP_POP_32_S_U", /* name. */ -+ "R_LARCH_SOP_POP_32_U", /* name. */ - false, /* partial_inplace. */ - 0xffffffff00000000, /* src_mask */ - 0x00000000ffffffff, /* dst_mask */ --- -2.33.0 - diff --git a/LoongArch-bfd-Fix-some-bugs-of-howto-table.patch b/LoongArch-bfd-Fix-some-bugs-of-howto-table.patch deleted file mode 100644 index a20ea41..0000000 --- a/LoongArch-bfd-Fix-some-bugs-of-howto-table.patch +++ /dev/null @@ -1,52 +0,0 @@ -From 4945a32e162be2a7001ed8e8066e983d0ae41bf4 Mon Sep 17 00:00:00 2001 -From: mengqinggang -Date: Thu, 22 Feb 2024 20:18:25 +0800 -Subject: [PATCH 058/123] LoongArch: bfd: Fix some bugs of howto table - -R_LARCH_IRELATIVE: For dynamic relocation that does not distinguish between -32/64 bits, size and bitsize set to 8 and 64. -R_LARCH_TLS_DESC64: Change size to 8. -R_LARCH_SOP_POP_32_S_0_5_10_16_S2: Change src_mask to 0, dst_mask to -0x03fffc1f. ---- - bfd/elfxx-loongarch.c | 10 +++++----- - 1 file changed, 5 insertions(+), 5 deletions(-) - -diff --git a/bfd/elfxx-loongarch.c b/bfd/elfxx-loongarch.c -index fe38f369..127f3548 100644 ---- a/bfd/elfxx-loongarch.c -+++ b/bfd/elfxx-loongarch.c -@@ -278,8 +278,8 @@ static loongarch_reloc_howto_type loongarch_howto_table[] = - - LOONGARCH_HOWTO (R_LARCH_IRELATIVE, /* type (12). */ - 0, /* rightshift */ -- 4, /* size */ -- 32, /* bitsize */ -+ 8, /* size */ -+ 64, /* bitsize */ - false, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ -@@ -312,7 +312,7 @@ static loongarch_reloc_howto_type loongarch_howto_table[] = - - LOONGARCH_HOWTO (R_LARCH_TLS_DESC64, /* type (14). */ - 0, /* rightshift. */ -- 4, /* size. */ -+ 8, /* size. */ - 64, /* bitsize. */ - false, /* pc_relative. */ - 0, /* bitpos. */ -@@ -514,8 +514,8 @@ static loongarch_reloc_howto_type loongarch_howto_table[] = - bfd_elf_generic_reloc, /* special_function. */ - "R_LARCH_SOP_POP_32_S_0_5_10_16_S2", /* name. */ - false, /* partial_inplace. */ -- 0xfc0003e0, /* src_mask */ -- 0xfc0003e0, /* dst_mask */ -+ 0x0, /* src_mask */ -+ 0x03fffc1f, /* dst_mask */ - false, /* pcrel_offset */ - BFD_RELOC_LARCH_SOP_POP_32_S_0_5_10_16_S2, - /* bfd_reloc_code_real_type */ --- -2.33.0 - diff --git a/LoongArch-binutils-compatible-with-older-gcc.patch b/LoongArch-binutils-compatible-with-older-gcc.patch deleted file mode 100644 index bfca9eb..0000000 --- a/LoongArch-binutils-compatible-with-older-gcc.patch +++ /dev/null @@ -1,26 +0,0 @@ -diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c -index 7fa7fa0f..16f688d6 100644 ---- a/gas/config/tc-loongarch.c -+++ b/gas/config/tc-loongarch.c -@@ -599,8 +599,21 @@ s_loongarch_option (int x ATTRIBUTE_UNUSED) - demand_empty_rest_of_line (); - } - -+static void -+s_loongarch_align (int arg) -+{ -+ const char *t = input_line_pointer; -+ while (!is_end_of_line[(unsigned char) *t] && *t != ',') -+ ++t; -+ if (*t == ',') -+ s_align_ptwo (arg); -+ else -+ s_align_ptwo (0); -+} -+ - static const pseudo_typeS loongarch_pseudo_table[] = - { -+ { "align", s_loongarch_align, -4 }, - { "dword", cons, 8 }, - { "word", cons, 4 }, - { "half", cons, 2 }, diff --git a/LoongArch-fix-internal-error-when-as-handling-unsupp.patch b/LoongArch-fix-internal-error-when-as-handling-unsupp.patch deleted file mode 100644 index dda03c5..0000000 --- a/LoongArch-fix-internal-error-when-as-handling-unsupp.patch +++ /dev/null @@ -1,78 +0,0 @@ -From df4ffdd8c87b32357f929fb4a861760038f3bbb8 Mon Sep 17 00:00:00 2001 -From: Lulu Cai -Date: Wed, 15 Nov 2023 19:20:53 +0800 -Subject: [PATCH] LoongArch: fix internal error when as handling unsupported - modifier. - -Signed-off-by: Peng Fan ---- - bfd/elfxx-loongarch.c | 3 --- - gas/config/loongarch-parse.y | 6 +++++- - gas/testsuite/gas/loongarch/reloc_type.d | 3 +++ - gas/testsuite/gas/loongarch/reloc_type.l | 2 ++ - gas/testsuite/gas/loongarch/reloc_type.s | 3 +++ - 5 files changed, 13 insertions(+), 4 deletions(-) - create mode 100644 gas/testsuite/gas/loongarch/reloc_type.d - create mode 100644 gas/testsuite/gas/loongarch/reloc_type.l - create mode 100644 gas/testsuite/gas/loongarch/reloc_type.s - -diff --git a/bfd/elfxx-loongarch.c b/bfd/elfxx-loongarch.c -index a970a257aa9..7f298c08fd3 100644 ---- a/bfd/elfxx-loongarch.c -+++ b/bfd/elfxx-loongarch.c -@@ -1629,9 +1629,6 @@ loongarch_larch_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED, - return lht->bfd_type; - } - -- (*_bfd_error_handler) (_("%pB: unsupported relocation type name %s"), -- abfd, l_r_name); -- bfd_set_error (bfd_error_bad_value); - return BFD_RELOC_NONE; - } - -diff --git a/gas/config/loongarch-parse.y b/gas/config/loongarch-parse.y -index f4e1a63b972..f786fdaee5f 100644 ---- a/gas/config/loongarch-parse.y -+++ b/gas/config/loongarch-parse.y -@@ -132,7 +132,11 @@ reloc (const char *op_c_str, const char *id_c_str, offsetT addend) - if (0 == strcmp (op_c_str, "plt")) - btype = BFD_RELOC_LARCH_B26; - else -- btype = loongarch_larch_reloc_name_lookup (NULL, op_c_str); -+ { -+ btype = loongarch_larch_reloc_name_lookup (NULL, op_c_str); -+ if (btype == BFD_RELOC_NONE) -+ as_fatal (_("unsupported modifier %s"), op_c_str); -+ } - - if (id_c_str) - { -diff --git a/gas/testsuite/gas/loongarch/reloc_type.d b/gas/testsuite/gas/loongarch/reloc_type.d -new file mode 100644 -index 00000000000..0a8f77825a0 ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/reloc_type.d -@@ -0,0 +1,3 @@ -+#as: -+#source: reloc_type.s -+#error_output: reloc_type.l -diff --git a/gas/testsuite/gas/loongarch/reloc_type.l b/gas/testsuite/gas/loongarch/reloc_type.l -new file mode 100644 -index 00000000000..e981f6f2aa5 ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/reloc_type.l -@@ -0,0 +1,2 @@ -+.*Assembler messages: -+.*Fatal error: unsupported modifier (.*)$ -diff --git a/gas/testsuite/gas/loongarch/reloc_type.s b/gas/testsuite/gas/loongarch/reloc_type.s -new file mode 100644 -index 00000000000..2ce277779db ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/reloc_type.s -@@ -0,0 +1,3 @@ -+.L1: -+ nop -+ addi.d $a0,$a1,%reloc(x) --- -2.33.0 - diff --git a/LoongArch-gas-Add-support-for-s9-register.patch b/LoongArch-gas-Add-support-for-s9-register.patch deleted file mode 100644 index f5c834a..0000000 --- a/LoongArch-gas-Add-support-for-s9-register.patch +++ /dev/null @@ -1,98 +0,0 @@ -From 0f44b5db22c6059f8b8742e08eca9ae282973c7a Mon Sep 17 00:00:00 2001 -From: mengqinggang -Date: Thu, 25 Jan 2024 14:44:12 +0800 -Subject: [PATCH 053/123] LoongArch: gas: Add support for s9 register - -In LoongArch ABI, r22 register can be used as frame pointer or -static register(s9). - -Link: https://github.com/loongson/la-abi-specs/blob/release/lapcs.adoc#general-purpose-registers ---- - gas/config/tc-loongarch.c | 7 +++++-- - gas/testsuite/gas/loongarch/loongarch.exp | 1 + - gas/testsuite/gas/loongarch/reg-s9.l | 1 + - gas/testsuite/gas/loongarch/reg-s9.s | 2 ++ - include/opcode/loongarch.h | 1 + - opcodes/loongarch-opc.c | 9 +++++++++ - 6 files changed, 19 insertions(+), 2 deletions(-) - create mode 100644 gas/testsuite/gas/loongarch/reg-s9.l - create mode 100644 gas/testsuite/gas/loongarch/reg-s9.s - -diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c -index 5b7f5137..0495f63a 100644 ---- a/gas/config/tc-loongarch.c -+++ b/gas/config/tc-loongarch.c -@@ -316,8 +316,11 @@ loongarch_after_parse_args () - /* Init ilp32/lp64 registers alias. */ - r_abi_names = loongarch_r_alias; - for (i = 0; i < ARRAY_SIZE (loongarch_r_alias); i++) -- str_hash_insert (r_htab, loongarch_r_alias[i], (void *) (i + 1), -- 0); -+ str_hash_insert (r_htab, loongarch_r_alias[i], (void *) (i + 1), 0); -+ -+ for (i = 0; i < ARRAY_SIZE (loongarch_r_alias_1); i++) -+ str_hash_insert (r_htab, loongarch_r_alias_1[i], (void *) (i + 1), 0); -+ - for (i = 0; i < ARRAY_SIZE (loongarch_r_alias_deprecated); i++) - str_hash_insert (r_deprecated_htab, loongarch_r_alias_deprecated[i], - (void *) (i + 1), 0); -diff --git a/gas/testsuite/gas/loongarch/loongarch.exp b/gas/testsuite/gas/loongarch/loongarch.exp -index fedeeecb..1051a541 100644 ---- a/gas/testsuite/gas/loongarch/loongarch.exp -+++ b/gas/testsuite/gas/loongarch/loongarch.exp -@@ -31,4 +31,5 @@ if [istarget loongarch*-*-*] { - } - - run_list_test "align" -+ run_list_test "reg-s9" - } -diff --git a/gas/testsuite/gas/loongarch/reg-s9.l b/gas/testsuite/gas/loongarch/reg-s9.l -new file mode 100644 -index 00000000..8ea739b7 ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/reg-s9.l -@@ -0,0 +1 @@ -+# No warning or error expected. -diff --git a/gas/testsuite/gas/loongarch/reg-s9.s b/gas/testsuite/gas/loongarch/reg-s9.s -new file mode 100644 -index 00000000..74f40481 ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/reg-s9.s -@@ -0,0 +1,2 @@ -+# Add support for $s9 register -+addi.d $t0, $s9, 0 -diff --git a/include/opcode/loongarch.h b/include/opcode/loongarch.h -index 32ff4d8a..5fc6e190 100644 ---- a/include/opcode/loongarch.h -+++ b/include/opcode/loongarch.h -@@ -196,6 +196,7 @@ dec2 : [1-9][0-9]? - - extern const char *const loongarch_r_normal_name[32]; - extern const char *const loongarch_r_alias[32]; -+ extern const char *const loongarch_r_alias_1[32]; - extern const char *const loongarch_r_alias_deprecated[32]; - extern const char *const loongarch_f_normal_name[32]; - extern const char *const loongarch_f_alias[32]; -diff --git a/opcodes/loongarch-opc.c b/opcodes/loongarch-opc.c -index cc3d1986..6afc0e8a 100644 ---- a/opcodes/loongarch-opc.c -+++ b/opcodes/loongarch-opc.c -@@ -49,6 +49,15 @@ const char *const loongarch_r_alias[32] = - "$s1", "$s2", "$s3", "$s4", "$s5", "$s6", "$s7", "$s8", - }; - -+/* Add support for $s9. */ -+const char *const loongarch_r_alias_1[32] = -+{ -+ "", "", "", "", "", "", "", "", -+ "", "", "", "", "", "", "", "", -+ "", "", "", "", "", "", "$s9", "", -+ "", "", "", "", "", "", "", "", -+}; -+ - const char *const loongarch_r_alias_deprecated[32] = - { - "", "", "", "", "$v0", "$v1", "", "", "", "", "", "", "", "", "", "", --- -2.33.0 - diff --git a/LoongArch-gas-Add-support-for-tls-le-relax.patch b/LoongArch-gas-Add-support-for-tls-le-relax.patch deleted file mode 100644 index ca7acbc..0000000 --- a/LoongArch-gas-Add-support-for-tls-le-relax.patch +++ /dev/null @@ -1,166 +0,0 @@ -From d839b6eeb36c9d033038854e08cc8e10b34968ba Mon Sep 17 00:00:00 2001 -From: changjiachen -Date: Thu, 28 Dec 2023 19:59:39 +0800 -Subject: [PATCH 034/123] LoongArch: gas: Add support for tls le relax. - -Add tls le relax related relocs support and testsuites in gas. - -The main test is three new relocation items, -R_LARCH_TLS_LE_ADD_R, R_LARCH_TLS_LE_HI20_R, -R_LARCH_TLS_LE_LO12_R can be generated properly -and tls le insn format check. - -gas/ChangeLog: - - * config/tc-loongarch.c: - (loongarch_args_parser_can_match_arg_helper): Add support for relax. - * gas/testsuite/gas/loongarch/reloc.d: Likewise. - * gas/testsuite/gas/loongarch/reloc.s: Likewise. - * gas/testsuite/gas/loongarch/loongarch.exp: Likewise. - * gas/testsuite/gas/loongarch/tls_le_insn_format_check.s: New test. ---- - gas/config/tc-loongarch.c | 32 +++++++++++++++++++ - gas/testsuite/gas/loongarch/loongarch.exp | 9 ++++++ - gas/testsuite/gas/loongarch/reloc.d | 18 +++++++++++ - gas/testsuite/gas/loongarch/reloc.s | 11 +++++++ - .../gas/loongarch/tls_le_insn_format_check.s | 15 +++++++++ - 5 files changed, 85 insertions(+) - create mode 100644 gas/testsuite/gas/loongarch/tls_le_insn_format_check.s - -diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c -index def26daf..fad18fcd 100644 ---- a/gas/config/tc-loongarch.c -+++ b/gas/config/tc-loongarch.c -@@ -636,6 +636,30 @@ loongarch_args_parser_can_match_arg_helper (char esc_ch1, char esc_ch2, - break; - } - break; -+ /* This is used for TLS, where the fourth operand is %le_add_r, -+ to get a relocation applied to an add instruction, for relaxation to use. -+ Two conditions, ip->match_now and reloc_num, are used to check tls insn -+ to prevent cases like add.d $a0,$a0,$a0,8. */ -+ case 't': -+ ip->match_now = loongarch_parse_expr (arg, ip->reloc_info + ip->reloc_num, -+ reloc_num_we_have, &reloc_num, &imm) == 0; -+ -+ if (!ip->match_now) -+ break; -+ -+ bfd_reloc_code_real_type tls_reloc_type = BFD_RELOC_LARCH_TLS_LE_ADD_R; -+ -+ if (reloc_num -+ && (ip->reloc_info[ip->reloc_num].type == tls_reloc_type)) -+ { -+ ip->reloc_num += reloc_num; -+ ip->reloc_info[ip->reloc_num].type = BFD_RELOC_LARCH_RELAX; -+ ip->reloc_info[ip->reloc_num].value = const_0; -+ ip->reloc_num++; -+ } -+ else -+ ip->match_now = 0; -+ break; - case 's': - case 'u': - ip->match_now = -@@ -690,6 +714,14 @@ loongarch_args_parser_can_match_arg_helper (char esc_ch1, char esc_ch2, - ip->reloc_num += reloc_num; - reloc_type = ip->reloc_info[0].type; - -+ if (LARCH_opts.relax -+ && (BFD_RELOC_LARCH_TLS_LE_HI20_R == reloc_type -+ || BFD_RELOC_LARCH_TLS_LE_LO12_R == reloc_type)) -+ { -+ ip->reloc_info[ip->reloc_num].type = BFD_RELOC_LARCH_RELAX; -+ ip->reloc_info[ip->reloc_num].value = const_0; -+ ip->reloc_num++; -+ } - if (LARCH_opts.relax && ip->macro_id - && (BFD_RELOC_LARCH_PCALA_HI20 == reloc_type - || BFD_RELOC_LARCH_PCALA_LO12 == reloc_type -diff --git a/gas/testsuite/gas/loongarch/loongarch.exp b/gas/testsuite/gas/loongarch/loongarch.exp -index 6d126fd4..c0aa593d 100644 ---- a/gas/testsuite/gas/loongarch/loongarch.exp -+++ b/gas/testsuite/gas/loongarch/loongarch.exp -@@ -21,4 +21,13 @@ - if [istarget loongarch*-*-*] { - run_dump_tests [lsort [glob -nocomplain $srcdir/$subdir/*.d]] - gas_test_old bfd_reloc_8.s "" "bfd_reloc_8" -+ if [file exist "tls_le_insn_format_check.s "] { -+ set format [run_host_cmd "as" "tls_le_insn_format_check.s"] -+ if { [ regexp ".*no match insn.*" $format] } { -+ pass "loongarch tls le insn format pass" -+ } { -+ pass "loongarch tls le insn format fail" -+ } -+ } -+ - } -diff --git a/gas/testsuite/gas/loongarch/reloc.d b/gas/testsuite/gas/loongarch/reloc.d -index c3820c55..0458830f 100644 ---- a/gas/testsuite/gas/loongarch/reloc.d -+++ b/gas/testsuite/gas/loongarch/reloc.d -@@ -165,3 +165,21 @@ Disassembly of section .text: - [ ]+134:[ ]+R_LARCH_TLS_LE64_LO20[ ]+TLSL1\+0x8 - [ ]+138:[ ]+03000085[ ]+lu52i.d[ ]+\$a1,[ ]+\$a0,[ ]+0 - [ ]+138:[ ]+R_LARCH_TLS_LE64_HI12[ ]+TLSL1\+0x8 -+[ ]+13c:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0 -+[ ]+13c:[ ]+R_LARCH_TLS_LE_HI20_R[ ]+TLSL1 -+[ ]+13c:[ ]+R_LARCH_RELAX[ ]+\*ABS\* -+[ ]+140:[ ]+001090a5[ ]+add.d[ ]+\$a1,[ ]+\$a1,[ ]+\$a0 -+[ ]+140:[ ]+R_LARCH_TLS_LE_ADD_R[ ]+TLSL1 -+[ ]+140:[ ]+R_LARCH_RELAX[ ]+\*ABS\* -+[ ]+144:[ ]+29800085[ ]+st.w[ ]+\$a1,[ ]+\$a0,[ ]+0 -+[ ]+144:[ ]+R_LARCH_TLS_LE_LO12_R[ ]+TLSL1 -+[ ]+144:[ ]+R_LARCH_RELAX[ ]+\*ABS\* -+[ ]+148:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0 -+[ ]+148:[ ]+R_LARCH_TLS_LE_HI20_R[ ]+TLSL1\+0x8 -+[ ]+148:[ ]+R_LARCH_RELAX[ ]+\*ABS\* -+[ ]+14c:[ ]+001090a5[ ]+add.d[ ]+\$a1,[ ]+\$a1,[ ]+\$a0 -+[ ]+14c:[ ]+R_LARCH_TLS_LE_ADD_R[ ]+TLSL1\+0x8 -+[ ]+14c:[ ]+R_LARCH_RELAX[ ]+\*ABS\* -+[ ]+150:[ ]+29800085[ ]+st.w[ ]+\$a1,[ ]+\$a0,[ ]+0 -+[ ]+150:[ ]+R_LARCH_TLS_LE_LO12_R[ ]+TLSL1\+0x8 -+[ ]+150:[ ]+R_LARCH_RELAX[ ]+\*ABS\* -diff --git a/gas/testsuite/gas/loongarch/reloc.s b/gas/testsuite/gas/loongarch/reloc.s -index a67fecd9..0a343c11 100644 ---- a/gas/testsuite/gas/loongarch/reloc.s -+++ b/gas/testsuite/gas/loongarch/reloc.s -@@ -142,3 +142,14 @@ lu12i.w $r4,%le_hi20(TLSL1 + 0x8) - ori $r5,$r4,%le_lo12(TLSL1 + 0x8) - lu32i.d $r4,%le64_lo20(TLSL1 + 0x8) - lu52i.d $r5,$r4,%le64_hi12(TLSL1 + 0x8) -+ -+ -+/* New TLS Insn. */ -+lu12i.w $r4,%le_hi20_r(TLSL1) -+add.d $r5,$r5,$r4,%le_add_r(TLSL1) -+st.w $r5,$r4,%le_lo12_r(TLSL1) -+ -+/* New TLS Insn with addend. */ -+lu12i.w $r4,%le_hi20_r(TLSL1 + 0x8) -+add.d $r5,$r5,$r4,%le_add_r(TLSL1 + 0x8) -+st.w $r5,$r4,%le_lo12_r(TLSL1 + 0x8) -diff --git a/gas/testsuite/gas/loongarch/tls_le_insn_format_check.s b/gas/testsuite/gas/loongarch/tls_le_insn_format_check.s -new file mode 100644 -index 00000000..1b3c9d18 ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/tls_le_insn_format_check.s -@@ -0,0 +1,15 @@ -+/* Assemble the following assembly statements using as. -+ -+ The test case is mainly to check the format of tls le type -+ symbolic address fetch instruction.Because in tls le symbolic -+ address acquisition, there will be a special add.d instruction, -+ which has four operands (add.d op1,op2,op3,op4),the first three -+ operands are registers, and the last operand is a relocation, -+ we need to format check the fourth operand.If it is not a correct -+ relocation type operand, we need to throw the relevant exception -+ message. -+ -+ if a "no match insn" exception is thrown, the test passes; -+ otherwise, the test fails. */ -+ -+add.d $a0,$a0,$a0,8 --- -2.33.0 - diff --git a/LoongArch-gas-Adjust-DWARF-CIE-alignment-factors.patch b/LoongArch-gas-Adjust-DWARF-CIE-alignment-factors.patch deleted file mode 100644 index bb056a0..0000000 --- a/LoongArch-gas-Adjust-DWARF-CIE-alignment-factors.patch +++ /dev/null @@ -1,49 +0,0 @@ -From 3b3e724f35e119acdbac2c8c6682a11e9cae64e2 Mon Sep 17 00:00:00 2001 -From: mengqinggang -Date: Mon, 29 Apr 2024 15:11:31 +0800 -Subject: [PATCH 086/123] LoongArch: gas: Adjust DWARF CIE alignment factors - -Set DWARF2_CIE_DATA_ALIGNMENT (data alignment factors) to -8. -It helps to save space. - -Data Alignment Factor -A signed LEB128 encoded value that is factored out of all offset -instructions that are associated with this CIE or its FDEs. This value -shall be multiplied by the register offset argument of an offset -instruction to obtain the new offset value. ---- - gas/config/tc-loongarch.h | 14 +++++++++----- - 1 file changed, 9 insertions(+), 5 deletions(-) - -diff --git a/gas/config/tc-loongarch.h b/gas/config/tc-loongarch.h -index 0b5cdfe6..6963867e 100644 ---- a/gas/config/tc-loongarch.h -+++ b/gas/config/tc-loongarch.h -@@ -99,15 +99,19 @@ extern bool loongarch_frag_align_code (int, int); - - #define TC_FORCE_RELOCATION_LOCAL(FIX) 1 - --/* Adjust debug_line after relaxation. */ --#define DWARF2_USE_FIXED_ADVANCE_PC 1 -- - /* Values passed to md_apply_fix don't include symbol values. */ - #define MD_APPLY_SYM_VALUE(FIX) 0 - - #define TARGET_USE_CFIPOP 1 --#define DWARF2_DEFAULT_RETURN_COLUMN 1 /* $ra. */ --#define DWARF2_CIE_DATA_ALIGNMENT -4 -+/* Adjust debug_line after relaxation. */ -+#define DWARF2_USE_FIXED_ADVANCE_PC 1 -+ -+/* FDE Data Alignment Factor. -+ FDE Code Alignment Factor (DWARF2_LINE_MIN_INSN_LENGTH) should be 1 -+ because DW_CFA_advance_loc need to be relocated in bytes -+ when linker relaxation. */ -+#define DWARF2_CIE_DATA_ALIGNMENT (-8) -+#define DWARF2_DEFAULT_RETURN_COLUMN 1 /* FDE Return Address Register. */ - - #define tc_cfi_frame_initial_instructions \ - loongarch_cfi_frame_initial_instructions --- -2.33.0 - diff --git a/LoongArch-gas-Don-t-define-LoongArch-.align.patch b/LoongArch-gas-Don-t-define-LoongArch-.align.patch deleted file mode 100644 index ca6e908..0000000 --- a/LoongArch-gas-Don-t-define-LoongArch-.align.patch +++ /dev/null @@ -1,82 +0,0 @@ -From f30bb80d462445ac5557bc65abd4672ce915b9e9 Mon Sep 17 00:00:00 2001 -From: mengqinggang -Date: Sun, 1 Oct 2023 15:29:44 +0800 -Subject: [PATCH 050/123] LoongArch: gas: Don't define LoongArch .align - -Gcc may generate "\t.align\t%d,54525952,4\n" before commit -b20c7ee066cb7d952fa193972e8bc6362c6e4063. To write 54525952 (NOP) to object -file, we call s_align_ptwo (-4). It result in alignment padding must be a -multiple of 4 if .align has second parameter. - -Use default s_align_ptwo for .align. ---- - gas/config/tc-loongarch.c | 13 ------------- - gas/testsuite/gas/loongarch/align.l | 1 + - gas/testsuite/gas/loongarch/align.s | 5 +++++ - gas/testsuite/gas/loongarch/loongarch.exp | 1 + - 4 files changed, 7 insertions(+), 13 deletions(-) - create mode 100644 gas/testsuite/gas/loongarch/align.l - create mode 100644 gas/testsuite/gas/loongarch/align.s - -diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c -index 1ae57b45..49470073 100644 ---- a/gas/config/tc-loongarch.c -+++ b/gas/config/tc-loongarch.c -@@ -436,18 +436,6 @@ loongarch_mach (void) - - static const expressionS const_0 = { .X_op = O_constant, .X_add_number = 0 }; - --static void --s_loongarch_align (int arg) --{ -- const char *t = input_line_pointer; -- while (!is_end_of_line[(unsigned char) *t] && *t != ',') -- ++t; -- if (*t == ',') -- s_align_ptwo (arg); -- else -- s_align_ptwo (0); --} -- - /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate - a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for - use in DWARF debug information. */ -@@ -479,7 +467,6 @@ s_dtprel (int bytes) - - static const pseudo_typeS loongarch_pseudo_table[] = - { -- { "align", s_loongarch_align, -4 }, - { "dword", cons, 8 }, - { "word", cons, 4 }, - { "half", cons, 2 }, -diff --git a/gas/testsuite/gas/loongarch/align.l b/gas/testsuite/gas/loongarch/align.l -new file mode 100644 -index 00000000..8ea739b7 ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/align.l -@@ -0,0 +1 @@ -+# No warning or error expected. -diff --git a/gas/testsuite/gas/loongarch/align.s b/gas/testsuite/gas/loongarch/align.s -new file mode 100644 -index 00000000..93f25289 ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/align.s -@@ -0,0 +1,5 @@ -+# Fix bug: alignment padding must a multiple of 4 if .align has second parameter -+.data -+ .byte 1 -+ .align 3, 2 -+ .4byte 3 -diff --git a/gas/testsuite/gas/loongarch/loongarch.exp b/gas/testsuite/gas/loongarch/loongarch.exp -index c0aa593d..fedeeecb 100644 ---- a/gas/testsuite/gas/loongarch/loongarch.exp -+++ b/gas/testsuite/gas/loongarch/loongarch.exp -@@ -30,4 +30,5 @@ if [istarget loongarch*-*-*] { - } - } - -+ run_list_test "align" - } --- -2.33.0 - diff --git a/LoongArch-gas-Fix-make-check-gas-crash.patch b/LoongArch-gas-Fix-make-check-gas-crash.patch deleted file mode 100644 index 97a9adb..0000000 --- a/LoongArch-gas-Fix-make-check-gas-crash.patch +++ /dev/null @@ -1,26 +0,0 @@ -From e80e6624e3b5aafd683706f6567e4b748c4c441f Mon Sep 17 00:00:00 2001 -From: mengqinggang -Date: Fri, 18 Aug 2023 17:02:20 +0800 -Subject: [PATCH 005/123] LoongArch: gas: Fix make check-gas crash - ---- - gas/testsuite/lib/gas-defs.exp | 3 --- - 1 file changed, 3 deletions(-) - -diff --git a/gas/testsuite/lib/gas-defs.exp b/gas/testsuite/lib/gas-defs.exp -index 3e134ca8..da0c24ea 100644 ---- a/gas/testsuite/lib/gas-defs.exp -+++ b/gas/testsuite/lib/gas-defs.exp -@@ -361,9 +361,6 @@ proc verbose_eval { expr { level 1 } } { - # that version gets released, and has been out in the world for a few - # months at least, it may be safe to delete this copy. - --if { [istarget loongarch*-*-*] } { -- rename prune_warnings prune_warnings_other --} - if ![string length [info proc prune_warnings]] { - # - # prune_warnings -- delete various system verbosities from TEXT. --- -2.33.0 - diff --git a/LoongArch-gas-Fix-the-types-of-symbols-referred-with.patch b/LoongArch-gas-Fix-the-types-of-symbols-referred-with.patch deleted file mode 100644 index 9196dce..0000000 --- a/LoongArch-gas-Fix-the-types-of-symbols-referred-with.patch +++ /dev/null @@ -1,84 +0,0 @@ -From f0efc301a550708ea07b8dad127d5cb149661d24 Mon Sep 17 00:00:00 2001 -From: Xi Ruoyao -Date: Fri, 2 Feb 2024 21:00:58 +0800 -Subject: [PATCH 055/123] LoongArch: gas: Fix the types of symbols referred - with %le_*_r in the symtab - -When a symbol is referred with %le_{hi20,lo12,add}_r, it's definitely a -TLS symbol and we should set its type to TLS in the symtab. Otherwise -when building Perl with gcc-14 -flto, we get: - -/usr/bin/ld: PL_current_context: TLS definition in -./miniperl.ltrans0.ltrans.o section .tbss mismatches non-TLS reference -in ./miniperl.ltrans1.ltrans.o - -A minimal reproducer: - - $ cat t1.s - .section .tbss - .globl x - x: .word 0 - $ cat t2.s - f: - lu12i.w $a0, %le_hi20_r(x) - add.d $a0, $a0, $tp, %le_add_r(x) - li.w $a1, 1 - st.w $a1, $a0, %le_lo12_r(x) - $ gas/as-new t1.s -o t1.o - $ gas/as-new t2.s -o t2.o - $ ld/ld-new t1.o t2.o - ld/ld-new: x: TLS definition in t1.o section .tbss mismatches - non-TLS reference in t2.o - -Unfortunately this was undetected before Binutils-2.42 release because -GCC < 14 does not use %le_*_r, and without LTO it's very rare to have a -TLS LE definition and its reference in two different translation units. -So this fix should be backported to Binutils-2.42 branch too. - -Signed-off-by: Xi Ruoyao ---- - gas/config/tc-loongarch.c | 3 +++ - gas/testsuite/gas/loongarch/tls_le_r_sym_type.d | 3 +++ - gas/testsuite/gas/loongarch/tls_le_r_sym_type.s | 6 ++++++ - 3 files changed, 12 insertions(+) - create mode 100644 gas/testsuite/gas/loongarch/tls_le_r_sym_type.d - create mode 100644 gas/testsuite/gas/loongarch/tls_le_r_sym_type.s - -diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c -index 0495f63a..5e96f624 100644 ---- a/gas/config/tc-loongarch.c -+++ b/gas/config/tc-loongarch.c -@@ -1340,6 +1340,9 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) - case BFD_RELOC_LARCH_TLS_DESC_LO12: - case BFD_RELOC_LARCH_TLS_DESC64_LO20: - case BFD_RELOC_LARCH_TLS_DESC64_HI12: -+ case BFD_RELOC_LARCH_TLS_LE_ADD_R: -+ case BFD_RELOC_LARCH_TLS_LE_HI20_R: -+ case BFD_RELOC_LARCH_TLS_LE_LO12_R: - /* Add tls lo (got_lo reloc type). */ - if (fixP->fx_addsy == NULL) - as_bad_where (fixP->fx_file, fixP->fx_line, -diff --git a/gas/testsuite/gas/loongarch/tls_le_r_sym_type.d b/gas/testsuite/gas/loongarch/tls_le_r_sym_type.d -new file mode 100644 -index 00000000..43bcd789 ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/tls_le_r_sym_type.d -@@ -0,0 +1,3 @@ -+#readelf: -s -+#... -+.*TLS[ \t]+GLOBAL[ \t]+DEFAULT[ \t]+UND[ \t]+x -diff --git a/gas/testsuite/gas/loongarch/tls_le_r_sym_type.s b/gas/testsuite/gas/loongarch/tls_le_r_sym_type.s -new file mode 100644 -index 00000000..3ccedae9 ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/tls_le_r_sym_type.s -@@ -0,0 +1,6 @@ -+f: -+ lu12i.w $a0, %le_hi20_r(x) -+ add.d $a0, $a0, $tp, %le_add_r(x) -+ li.w $a1, 1 -+ st.w $a1, $a0, %le_lo12_r(x) -+ ret --- -2.33.0 - diff --git a/LoongArch-gas-Ignore-.align-if-it-is-at-the-start-of.patch b/LoongArch-gas-Ignore-.align-if-it-is-at-the-start-of.patch deleted file mode 100644 index 04fa7c9..0000000 --- a/LoongArch-gas-Ignore-.align-if-it-is-at-the-start-of.patch +++ /dev/null @@ -1,308 +0,0 @@ -From adb3d28328bbf2d17c3a44778497827d7d35124a Mon Sep 17 00:00:00 2001 -From: mengqinggang -Date: Tue, 19 Mar 2024 21:09:12 +0800 -Subject: [PATCH 076/123] LoongArch: gas: Ignore .align if it is at the start - of a section - -Ignore .align if it is at the start of a section and the alignment -can be divided by the section alignment, the section alignment -can ensure this .align has a correct alignment. ---- - gas/config/tc-loongarch.c | 134 ++++++++++++++---- - .../gas/loongarch/relax-align-first.d | 12 ++ - .../gas/loongarch/relax-align-first.s | 7 + - .../ld-loongarch-elf/relax-align-first.d | 15 ++ - .../ld-loongarch-elf/relax-align-first.s | 13 ++ - ld/testsuite/ld-loongarch-elf/relax.exp | 1 + - 6 files changed, 157 insertions(+), 25 deletions(-) - create mode 100644 gas/testsuite/gas/loongarch/relax-align-first.d - create mode 100644 gas/testsuite/gas/loongarch/relax-align-first.s - create mode 100644 ld/testsuite/ld-loongarch-elf/relax-align-first.d - create mode 100644 ld/testsuite/ld-loongarch-elf/relax-align-first.s - -diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c -index 1e835f51..110b92e4 100644 ---- a/gas/config/tc-loongarch.c -+++ b/gas/config/tc-loongarch.c -@@ -128,6 +128,11 @@ static bool call36 = 0; - #define RELAX_BRANCH_ENCODE(x) \ - (BFD_RELOC_LARCH_B16 == (x) ? RELAX_BRANCH_16 : RELAX_BRANCH_21) - -+#define ALIGN_MAX_ADDEND(n, max) ((max << 8) | n) -+#define ALIGN_MAX_NOP_BYTES(addend) ((1 << (addend & 0xff)) - 4) -+#define FRAG_AT_START_OF_SECTION(frag) \ -+ (0 == frag->fr_address && 0 == frag->fr_fix) -+ - enum options - { - OPTION_IGNORE = OPTION_MD_BASE, -@@ -1647,10 +1652,32 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) - } - } - -+/* Estimate the size of a frag before relaxing. */ -+ - int --md_estimate_size_before_relax (fragS *fragp ATTRIBUTE_UNUSED, -- asection *segtype ATTRIBUTE_UNUSED) -+md_estimate_size_before_relax (fragS *fragp, asection *sec) - { -+ /* align pseudo instunctions. */ -+ if (rs_align_code == fragp->fr_subtype) -+ { -+ offsetT nop_bytes; -+ if (NULL == fragp->fr_symbol) -+ nop_bytes = fragp->fr_offset; -+ else -+ nop_bytes = ALIGN_MAX_NOP_BYTES (fragp->fr_offset); -+ -+ /* Normally, nop_bytes should be >= 4. */ -+ gas_assert (nop_bytes > 0); -+ -+ if (FRAG_AT_START_OF_SECTION (fragp) -+ && 0 == ((1 << sec->alignment_power) % (nop_bytes + 4))) -+ return (fragp->fr_var = 0); -+ else -+ return (fragp->fr_var = nop_bytes); -+ } -+ -+ /* branch instructions and other instructions. -+ branch instructions may become 8 bytes after relaxing. */ - return (fragp->fr_var = 4); - } - -@@ -1767,8 +1794,7 @@ bool - loongarch_frag_align_code (int n, int max) - { - char *nops; -- symbolS *s; -- expressionS ex; -+ symbolS *s = NULL; - - bfd_vma insn_alignment = 4; - bfd_vma bytes = (bfd_vma) 1 << n; -@@ -1783,8 +1809,6 @@ loongarch_frag_align_code (int n, int max) - if (!LARCH_opts.relax) - return false; - -- nops = frag_more (worst_case_bytes); -- - /* If max <= 0, ignore max. - If max >= worst_case_bytes, max has no effect. - Similar to gas/write.c relax_segment function rs_align_code case: -@@ -1792,20 +1816,20 @@ loongarch_frag_align_code (int n, int max) - if (max > 0 && (bfd_vma) max < worst_case_bytes) - { - s = symbol_find (now_seg->name); -- ex.X_add_symbol = s; -- ex.X_op = O_symbol; -- ex.X_add_number = (max << 8) | n; -- } -- else -- { -- ex.X_op = O_constant; -- ex.X_add_number = worst_case_bytes; -+ worst_case_bytes = ALIGN_MAX_ADDEND (n, max); - } - -- loongarch_make_nops (nops, worst_case_bytes); -+ frag_grow (worst_case_bytes); -+ /* Use relaxable frag for .align. -+ If .align at the start of section, do nothing. Section alignment can -+ ensure correct alignment. -+ If .align is not at the start of a section, reserve NOP instructions -+ and R_LARCH_ALIGN relocation. */ -+ nops = frag_var (rs_machine_dependent, worst_case_bytes, worst_case_bytes, -+ rs_align_code, s, worst_case_bytes, NULL); - -- fix_new_exp (frag_now, nops - frag_now->fr_literal, 0, -- &ex, false, BFD_RELOC_LARCH_ALIGN); -+ /* Default write NOP for aligned bytes. */ -+ loongarch_make_nops (nops, worst_case_bytes); - - /* We need to start a new frag after the alignment which may be removed by - the linker, to prevent the assembler from computing static offsets. -@@ -1963,8 +1987,7 @@ loongarch_relaxed_branch_length (fragS *fragp, asection *sec, int update) - } - - int --loongarch_relax_frag (asection *sec ATTRIBUTE_UNUSED, -- fragS *fragp ATTRIBUTE_UNUSED, -+loongarch_relax_frag (asection *sec, fragS *fragp, - long stretch ATTRIBUTE_UNUSED) - { - if (RELAX_BRANCH (fragp->fr_subtype)) -@@ -1973,6 +1996,27 @@ loongarch_relax_frag (asection *sec ATTRIBUTE_UNUSED, - fragp->fr_var = loongarch_relaxed_branch_length (fragp, sec, true); - return fragp->fr_var - old_var; - } -+ else if (rs_align_code == fragp->fr_subtype) -+ { -+ offsetT nop_bytes; -+ if (NULL == fragp->fr_symbol) -+ nop_bytes = fragp->fr_offset; -+ else -+ nop_bytes = ALIGN_MAX_NOP_BYTES (fragp->fr_offset); -+ -+ /* Normally, nop_bytes should be >= 4. */ -+ gas_assert (nop_bytes > 0); -+ -+ offsetT old_var = fragp->fr_var; -+ /* If .align at the start of a section, do nothing. Section alignment -+ * can ensure correct alignment. */ -+ if (FRAG_AT_START_OF_SECTION (fragp) -+ && 0 == ((1 << sec->alignment_power) % (nop_bytes + 4))) -+ fragp->fr_var = 0; -+ else -+ fragp->fr_var = nop_bytes; -+ return fragp->fr_var - old_var; -+ } - return 0; - } - -@@ -2048,13 +2092,53 @@ loongarch_convert_frag_branch (fragS *fragp) - fragp->fr_fix += fragp->fr_var; - } - --/* Relax a machine dependent frag. This returns the amount by which -- the current size of the frag should change. */ -+/* Relax .align frag. */ -+ -+static void -+loongarch_convert_frag_align (fragS *fragp, asection *sec) -+{ -+ bfd_byte *buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; -+ -+ offsetT nop_bytes; -+ if (NULL == fragp->fr_symbol) -+ nop_bytes = fragp->fr_offset; -+ else -+ nop_bytes = ALIGN_MAX_NOP_BYTES (fragp->fr_offset); -+ -+ /* Normally, nop_bytes should be >= 4. */ -+ gas_assert (nop_bytes > 0); -+ -+ if (!(FRAG_AT_START_OF_SECTION (fragp) -+ && 0 == ((1 << sec->alignment_power) % (nop_bytes + 4)))) -+ { -+ expressionS exp; -+ exp.X_op = O_symbol; -+ exp.X_add_symbol = fragp->fr_symbol; -+ exp.X_add_number = fragp->fr_offset; -+ -+ fixS *fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, -+ nop_bytes, &exp, false, BFD_RELOC_LARCH_ALIGN); -+ fixp->fx_file = fragp->fr_file; -+ fixp->fx_line = fragp->fr_line; -+ -+ buf += nop_bytes; -+ } -+ -+ gas_assert (buf == (bfd_byte *)fragp->fr_literal -+ + fragp->fr_fix + fragp->fr_var); -+ -+ fragp->fr_fix += fragp->fr_var; -+} -+ -+/* Relax a machine dependent frag. */ - - void --md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec ATTRIBUTE_UNUSED, -- fragS *fragp) -+md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) - { -- gas_assert (RELAX_BRANCH (fragp->fr_subtype)); -- loongarch_convert_frag_branch (fragp); -+ gas_assert (RELAX_BRANCH (fragp->fr_subtype) -+ || rs_align_code == fragp->fr_subtype); -+ if (RELAX_BRANCH (fragp->fr_subtype)) -+ loongarch_convert_frag_branch (fragp); -+ else if (rs_align_code == fragp->fr_subtype) -+ loongarch_convert_frag_align (fragp, asec); - } -diff --git a/gas/testsuite/gas/loongarch/relax-align-first.d b/gas/testsuite/gas/loongarch/relax-align-first.d -new file mode 100644 -index 00000000..ec0698b6 ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/relax-align-first.d -@@ -0,0 +1,12 @@ -+#as: -+#objdump: -dr -+ -+.*:[ ]+file format .* -+ -+ -+Disassembly of section .text: -+0* <.text>: -+[ ]+0:[ ]+4c000020[ ]+ret -+Disassembly of section abc: -+0* : -+[ ]+0:[ ]+4c000020[ ]+ret -diff --git a/gas/testsuite/gas/loongarch/relax-align-first.s b/gas/testsuite/gas/loongarch/relax-align-first.s -new file mode 100644 -index 00000000..a4c3d68f ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/relax-align-first.s -@@ -0,0 +1,7 @@ -+.text -+.align 3 -+ret -+ -+.section "abc", "ax" -+.align 4, ,4 -+ret -diff --git a/ld/testsuite/ld-loongarch-elf/relax-align-first.d b/ld/testsuite/ld-loongarch-elf/relax-align-first.d -new file mode 100644 -index 00000000..9a4fad8e ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/relax-align-first.d -@@ -0,0 +1,15 @@ -+#ld: -e0 -+#objdump: -d -+ -+.*:[ ]+file format .* -+ -+ -+Disassembly of section aaa: -+0000000120000078 : -+[ ]+120000078:[ ]+4c000020[ ]+ret -+Disassembly of section bbb: -+0000000120000080 : -+[ ]+120000080:[ ]+4c000020[ ]+ret -+Disassembly of section ccc: -+0000000120000090 <__bss_start-0x4004>: -+[ ]+120000090:[ ]+4c000020[ ]+ret -diff --git a/ld/testsuite/ld-loongarch-elf/relax-align-first.s b/ld/testsuite/ld-loongarch-elf/relax-align-first.s -new file mode 100644 -index 00000000..0a9115b5 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/relax-align-first.s -@@ -0,0 +1,13 @@ -+# If .align at the start of a section, do not add NOP instructions -+# and do not emit R_LARCH_ALIGN relocations. -+# Section alignment can ensure correct alignment. -+.section "aaa", "ax" -+ret -+ -+.section "bbb", "ax" -+.align 3 -+ret -+ -+.section "ccc", "ax" -+.align 4, ,4 -+ret -diff --git a/ld/testsuite/ld-loongarch-elf/relax.exp b/ld/testsuite/ld-loongarch-elf/relax.exp -index f378b93b..7274218f 100644 ---- a/ld/testsuite/ld-loongarch-elf/relax.exp -+++ b/ld/testsuite/ld-loongarch-elf/relax.exp -@@ -20,6 +20,7 @@ - # - - if [istarget loongarch64-*-*] { -+ run_dump_test "relax-align-first" - - if [isbuild loongarch64-*-*] { - set testname "loongarch relax .exe build" --- -2.33.0 - diff --git a/LoongArch-gas-Simplify-relocations-in-sections-witho.patch b/LoongArch-gas-Simplify-relocations-in-sections-witho.patch deleted file mode 100644 index aae49f7..0000000 --- a/LoongArch-gas-Simplify-relocations-in-sections-witho.patch +++ /dev/null @@ -1,68 +0,0 @@ -From 47494a014c00dfa3832441171255018be62ac756 Mon Sep 17 00:00:00 2001 -From: Jinyang He -Date: Mon, 22 Apr 2024 17:49:50 +0800 -Subject: [PATCH 083/123] LoongArch: gas: Simplify relocations in sections - without code flag - -Gas should not emit ADD/SUB relocation pairs for label differences -if they are in the same section without code flag even relax enabled. -Because the real value is not be affected by relaxation and it can be -compute out in assembly stage. Thus, correct the `TC_FORCE_RELOCATION -_SUB_SAME` and the label differences in same section without code -flag can be resolved in fixup_segment(). ---- - gas/config/tc-loongarch.h | 4 +--- - gas/testsuite/gas/loongarch/relax_debug_line.d | 12 ++++++++++++ - gas/testsuite/gas/loongarch/relax_debug_line.s | 6 ++++++ - 3 files changed, 19 insertions(+), 3 deletions(-) - create mode 100644 gas/testsuite/gas/loongarch/relax_debug_line.d - create mode 100644 gas/testsuite/gas/loongarch/relax_debug_line.s - -diff --git a/gas/config/tc-loongarch.h b/gas/config/tc-loongarch.h -index 194ee107..0b5cdfe6 100644 ---- a/gas/config/tc-loongarch.h -+++ b/gas/config/tc-loongarch.h -@@ -91,9 +91,7 @@ extern bool loongarch_frag_align_code (int, int); - #define TC_FORCE_RELOCATION_SUB_SAME(FIX, SEC) \ - (LARCH_opts.relax ? \ - (GENERIC_FORCE_RELOCATION_SUB_SAME (FIX, SEC) \ -- || ((SEC)->flags & SEC_CODE) != 0 \ -- || ((SEC)->flags & SEC_DEBUGGING) != 0 \ -- || TC_FORCE_RELOCATION (FIX)) \ -+ || ((SEC)->flags & SEC_CODE) != 0) \ - : (GENERIC_FORCE_RELOCATION_SUB_SAME (FIX, SEC))) \ - - #define TC_LINKRELAX_FIXUP(seg) ((seg->flags & SEC_CODE) \ -diff --git a/gas/testsuite/gas/loongarch/relax_debug_line.d b/gas/testsuite/gas/loongarch/relax_debug_line.d -new file mode 100644 -index 00000000..c17813c2 ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/relax_debug_line.d -@@ -0,0 +1,12 @@ -+#as: --gdwarf-5 -+#readelf: -r --wide -+#skip: loongarch32-*-* -+ -+Relocation section '\.rela\.debug_line' at offset .* contains 5 entries: -+#... -+0+22.*R_LARCH_32[ \t]+[0-9]+.* -+0+2c.*R_LARCH_32[ \t]+[0-9]+.* -+0+36.*R_LARCH_64[ \t]+[0-9]+.* -+0+42.*R_LARCH_ADD16[ \t]+[0-9]+.* -+0+42.*R_LARCH_SUB16[ \t]+[0-9]+.* -+#pass -diff --git a/gas/testsuite/gas/loongarch/relax_debug_line.s b/gas/testsuite/gas/loongarch/relax_debug_line.s -new file mode 100644 -index 00000000..d2852bb9 ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/relax_debug_line.s -@@ -0,0 +1,6 @@ -+ .file 0 "test" -+ .text -+ .loc 0 10 0 -+ nop -+ -+.section .debug_line, "", @progbits --- -2.33.0 - diff --git a/LoongArch-gas-Start-a-new-frag-after-instructions-th.patch b/LoongArch-gas-Start-a-new-frag-after-instructions-th.patch deleted file mode 100644 index 6297e76..0000000 --- a/LoongArch-gas-Start-a-new-frag-after-instructions-th.patch +++ /dev/null @@ -1,143 +0,0 @@ -From 04b665b402affb89a5b077516bc306da11af1e84 Mon Sep 17 00:00:00 2001 -From: mengqinggang -Date: Thu, 18 Jan 2024 19:03:11 +0800 -Subject: [PATCH 051/123] LoongArch: gas: Start a new frag after instructions - that can be relaxed - -For R_LARCH_TLS_{LE_HI20_R,LE_ADD_R,LD_PC_HI20,GD_PC_HI20, DESC_PC_HI20} -relocations, start a new frag to get correct eh_frame Call Frame Information -FDE DW_CFA_advance_loc info. ---- - gas/config/tc-loongarch.c | 19 ++++++-- - .../relax-cfi-fde-DW_CFA_advance_loc.d | 46 +++++++++++++++++++ - .../relax-cfi-fde-DW_CFA_advance_loc.s | 33 +++++++++++++ - 3 files changed, 93 insertions(+), 5 deletions(-) - create mode 100644 gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.d - create mode 100644 gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.s - -diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c -index 49470073..5b7f5137 100644 ---- a/gas/config/tc-loongarch.c -+++ b/gas/config/tc-loongarch.c -@@ -1070,13 +1070,22 @@ append_fixp_and_insn (struct loongarch_cl_insn *ip) - optimized away or compressed by the linker during relaxation, to prevent - the assembler from computing static offsets across such an instruction. - -- This is necessary to get correct .eh_frame cfa info. If one cfa's two -- symbol is not in the same frag, it will generate relocs to calculate -- symbol subtraction. (gas/dw2gencfi.c:output_cfi_insn: -- if (symbol_get_frag (to) == symbol_get_frag (from))) */ -+ This is necessary to get correct .eh_frame FDE DW_CFA_advance_loc info. -+ If one cfi_insn_data's two symbols are not in the same frag, it will -+ generate ADD and SUB relocations pairs to calculate DW_CFA_advance_loc. -+ (gas/dw2gencfi.c: output_cfi_insn: -+ if (symbol_get_frag (to) == symbol_get_frag (from))) -+ -+ For macro instructions, only the first instruction expanded from macro -+ need to start a new frag. */ - if (LARCH_opts.relax - && (BFD_RELOC_LARCH_PCALA_HI20 == reloc_info[0].type -- || BFD_RELOC_LARCH_GOT_PC_HI20 == reloc_info[0].type)) -+ || BFD_RELOC_LARCH_GOT_PC_HI20 == reloc_info[0].type -+ || BFD_RELOC_LARCH_TLS_LE_HI20_R == reloc_info[0].type -+ || BFD_RELOC_LARCH_TLS_LE_ADD_R == reloc_info[0].type -+ || BFD_RELOC_LARCH_TLS_LD_PC_HI20 == reloc_info[0].type -+ || BFD_RELOC_LARCH_TLS_GD_PC_HI20 == reloc_info[0].type -+ || BFD_RELOC_LARCH_TLS_DESC_PC_HI20 == reloc_info[0].type)) - { - frag_wane (frag_now); - frag_new (0); -diff --git a/gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.d b/gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.d -new file mode 100644 -index 00000000..367039e1 ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.d -@@ -0,0 +1,46 @@ -+#as: -mrelax -+#objdump: -Dr -j .eh_frame -+#skip: loongarch32-*-* -+ -+.*:[ ]+file format .* -+ -+ -+Disassembly of section .eh_frame: -+ -+[ ]*0000000000000000 <.eh_frame>: -+[ ]+0:[ ]+00000014[ ]+.word[ ]+[ ]+0x00000014 -+[ ]+4:[ ]+00000000[ ]+.word[ ]+[ ]+0x00000000 -+[ ]+8:[ ]+00527a01[ ]+.word[ ]+[ ]+0x00527a01 -+[ ]+c:[ ]+01017c01[ ]+fadd.d[ ]+\$fa1, \$fa0, \$fs7 -+[ ]+10:[ ]+0c030d1b[ ]+.word[ ]+[ ]+0x0c030d1b -+[ ]+14:[ ]+00000016[ ]+.word[ ]+[ ]+0x00000016 -+[ ]+18:[ ]+00000034[ ]+.word[ ]+[ ]+0x00000034 -+[ ]+1c:[ ]+0000001c[ ]+.word[ ]+[ ]+0x0000001c -+[ ]+... -+[ ]+20: R_LARCH_32_PCREL[ ]+L0\^A -+[ ]+24: R_LARCH_ADD32[ ]+L0\^A -+[ ]+24: R_LARCH_SUB32[ ]+L0\^A -+[ ]+28:[ ]+0cd64000[ ]+.word[ ]+[ ]+0x0cd64000 -+[ ]+29: R_LARCH_ADD6[ ]+L0\^A -+[ ]+29: R_LARCH_SUB6[ ]+L0\^A -+[ ]+2c:[ ]+d6400016[ ]+.word[ ]+[ ]+0xd6400016 -+[ ]+2e: R_LARCH_ADD6[ ]+L0\^A -+[ ]+2e: R_LARCH_SUB6[ ]+L0\^A -+[ ]+30:[ ]+4000160c[ ]+beqz[ ]+\$t4, 3145748[ ]+# 300044 -+[ ]+33: R_LARCH_ADD6[ ]+L0\^A -+[ ]+33: R_LARCH_SUB6[ ]+L0\^A -+[ ]+34:[ ]+00160cd6[ ]+orn[ ]+\$fp, \$a2, \$sp -+[ ]+38:[ ]+160cd640[ ]+lu32i.d[ ]+\$zero, 26290 -+[ ]+38: R_LARCH_ADD6[ ]+L0\^A -+[ ]+38: R_LARCH_SUB6[ ]+L0\^A -+[ ]+3c:[ ]+0cd64000[ ]+.word[ ]+[ ]+0x0cd64000 -+[ ]+3d: R_LARCH_ADD6[ ]+L0\^A -+[ ]+3d: R_LARCH_SUB6[ ]+L0\^A -+[ ]+40:[ ]+d6400016[ ]+.word[ ]+[ ]+0xd6400016 -+[ ]+42: R_LARCH_ADD6[ ]+L0\^A -+[ ]+42: R_LARCH_SUB6[ ]+L0\^A -+[ ]+44:[ ]+4000160c[ ]+beqz[ ]+\$t4, 3145748[ ]+# 300058 -+[ ]+47: R_LARCH_ADD6[ ]+L0\^A -+[ ]+47: R_LARCH_SUB6[ ]+L0\^A -+[ ]+48:[ ]+000000d6[ ]+.word[ ]+[ ]+0x000000d6 -+[ ]+4c:[ ]+00000000[ ]+.word[ ]+[ ]+0x00000000 -diff --git a/gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.s b/gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.s -new file mode 100644 -index 00000000..6e4c9b8b ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.s -@@ -0,0 +1,33 @@ -+# Emits ADD/SUB relocations for CFA FDE DW_CFA_advance_loc with -mrelax option. -+.text -+.cfi_startproc -+ -+.cfi_def_cfa 22, 0 -+la.local $t0, a -+.cfi_restore 22 -+ -+.cfi_def_cfa 22, 0 -+la.got $t0, a -+.cfi_restore 22 -+ -+.cfi_def_cfa 22, 0 -+la.tls.ld $t0, a -+.cfi_restore 22 -+ -+.cfi_def_cfa 22, 0 -+la.tls.gd $t0, a -+.cfi_restore 22 -+ -+.cfi_def_cfa 22, 0 -+la.tls.desc $t0, a -+.cfi_restore 22 -+ -+.cfi_def_cfa 22, 0 -+pcalau12i $t0, %le_hi20_r(a) -+.cfi_restore 22 -+ -+.cfi_def_cfa 22, 0 -+add.d $t0, $tp, $t0, %le_add_r(a) -+.cfi_restore 22 -+ -+.cfi_endproc --- -2.33.0 - diff --git a/LoongArch-gas-Try-to-avoid-R_LARCH_ALIGN-associate-w.patch b/LoongArch-gas-Try-to-avoid-R_LARCH_ALIGN-associate-w.patch deleted file mode 100644 index bfa314f..0000000 --- a/LoongArch-gas-Try-to-avoid-R_LARCH_ALIGN-associate-w.patch +++ /dev/null @@ -1,166 +0,0 @@ -From 7b212e5db865a826dc15aaf5e0562133c88eb769 Mon Sep 17 00:00:00 2001 -From: mengqinggang -Date: Mon, 5 Feb 2024 16:16:52 +0800 -Subject: [PATCH 056/123] LoongArch: gas: Try to avoid R_LARCH_ALIGN associate - with a symbol - -The R_LARCH_ALIGN need to associated with a symbol if .align has the first -and third expressions. If R_LARCH_ALIGN associate with a symbol, the addend can -represent the first and third expression of .align. - -For '.align 3', the addend of R_LARCH_ALIGN only need to represent the alignment -and R_LARCH_ALIGN not need to associate with a symbol. - -For '.align x, , y', R_LARCH_ALIGN need to associate with a symbol if 0 < y < -2^x - 4. ---- - gas/config/tc-loongarch.c | 27 +++++++--- - gas/testsuite/gas/loongarch/relax_align.d | 64 +++++++++++++---------- - gas/testsuite/gas/loongarch/relax_align.s | 20 +++++-- - 3 files changed, 72 insertions(+), 39 deletions(-) - -diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c -index 5e96f624..e6da4e1e 100644 ---- a/gas/config/tc-loongarch.c -+++ b/gas/config/tc-loongarch.c -@@ -1746,14 +1746,25 @@ loongarch_frag_align_code (int n, int max) - - nops = frag_more (worst_case_bytes); - -- s = symbol_find (".Lla-relax-align"); -- if (s == NULL) -- s = (symbolS *)local_symbol_make (".Lla-relax-align", now_seg, -- &zero_address_frag, 0); -- -- ex.X_add_symbol = s; -- ex.X_op = O_symbol; -- ex.X_add_number = (max << 8) | n; -+ /* If max <= 0, ignore max. -+ If max >= worst_case_bytes, max has no effect. -+ Similar to gas/write.c relax_segment function rs_align_code case: -+ if (fragP->fr_subtype != 0 && offset > fragP->fr_subtype). */ -+ if (max > 0 && (bfd_vma) max < worst_case_bytes) -+ { -+ s = symbol_find (".Lla-relax-align"); -+ if (s == NULL) -+ s = (symbolS *)local_symbol_make (".Lla-relax-align", now_seg, -+ &zero_address_frag, 0); -+ ex.X_add_symbol = s; -+ ex.X_op = O_symbol; -+ ex.X_add_number = (max << 8) | n; -+ } -+ else -+ { -+ ex.X_op = O_constant; -+ ex.X_add_number = worst_case_bytes; -+ } - - loongarch_make_nops (nops, worst_case_bytes); - -diff --git a/gas/testsuite/gas/loongarch/relax_align.d b/gas/testsuite/gas/loongarch/relax_align.d -index 2cc6c86d..fc1fd032 100644 ---- a/gas/testsuite/gas/loongarch/relax_align.d -+++ b/gas/testsuite/gas/loongarch/relax_align.d -@@ -1,4 +1,4 @@ --#as: --no-warn -+#as: - #objdump: -dr - #skip: loongarch32-*-* - -@@ -8,29 +8,39 @@ - Disassembly of section .text: - - [ ]*0000000000000000 <.Lla-relax-align>: --[ ]+0:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0 --[ ]+0: R_LARCH_PCALA_HI20[ ]+L1 --[ ]+0: R_LARCH_RELAX[ ]+\*ABS\* --[ ]+4:[ ]+02c00084[ ]+addi.d[ ]+\$a0, \$a0, 0 --[ ]+4: R_LARCH_PCALA_LO12[ ]+L1 --[ ]+4: R_LARCH_RELAX[ ]+\*ABS\* --[ ]+8:[ ]+03400000[ ]+nop.* --[ ]+8: R_LARCH_ALIGN[ ]+.Lla-relax-align\+0x4 --[ ]+c:[ ]+03400000[ ]+nop.* --[ ]+10:[ ]+03400000[ ]+nop.* --[ ]+14:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0 --[ ]+14: R_LARCH_PCALA_HI20[ ]+L1 --[ ]+14: R_LARCH_RELAX[ ]+\*ABS\* --[ ]+18:[ ]+02c00084[ ]+addi.d[ ]+\$a0, \$a0, 0 --[ ]+18: R_LARCH_PCALA_LO12[ ]+L1 --[ ]+18: R_LARCH_RELAX[ ]+\*ABS\* --[ ]+1c:[ ]+03400000[ ]+nop.* --[ ]+1c: R_LARCH_ALIGN[ ]+.Lla-relax-align\+0x404 --[ ]+20:[ ]+03400000[ ]+nop.* --[ ]+24:[ ]+03400000[ ]+nop.* --[ ]+28:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0 --[ ]+28: R_LARCH_PCALA_HI20[ ]+L1 --[ ]+28: R_LARCH_RELAX[ ]+\*ABS\* --[ ]+2c:[ ]+02c00084[ ]+addi.d[ ]+\$a0, \$a0, 0 --[ ]+2c: R_LARCH_PCALA_LO12[ ]+L1 --[ ]+2c: R_LARCH_RELAX[ ]+\*ABS\* -+[ ]+0:[ ]+4c000020[ ]+ret -+[ ]+4:[ ]+03400000[ ]+nop -+[ ]+4: R_LARCH_ALIGN[ ]+\*ABS\*\+0xc -+[ ]+8:[ ]+03400000[ ]+nop -+[ ]+c:[ ]+03400000[ ]+nop -+[ ]+10:[ ]+4c000020[ ]+ret -+[ ]+14:[ ]+03400000[ ]+nop -+[ ]+14: R_LARCH_ALIGN[ ]+\*ABS\*\+0xc -+[ ]+18:[ ]+03400000[ ]+nop -+[ ]+1c:[ ]+03400000[ ]+nop -+[ ]+20:[ ]+4c000020[ ]+ret -+[ ]+24:[ ]+03400000[ ]+nop -+[ ]+24: R_LARCH_ALIGN[ ]+.Lla-relax-align\+0x104 -+[ ]+28:[ ]+03400000[ ]+nop -+[ ]+2c:[ ]+03400000[ ]+nop -+[ ]+30:[ ]+4c000020[ ]+ret -+[ ]+34:[ ]+03400000[ ]+nop -+[ ]+34: R_LARCH_ALIGN[ ]+.Lla-relax-align\+0xb04 -+[ ]+38:[ ]+03400000[ ]+nop -+[ ]+3c:[ ]+03400000[ ]+nop -+[ ]+40:[ ]+4c000020[ ]+ret -+[ ]+44:[ ]+03400000[ ]+nop -+[ ]+44: R_LARCH_ALIGN[ ]+\*ABS\*\+0xc -+[ ]+48:[ ]+03400000[ ]+nop -+[ ]+4c:[ ]+03400000[ ]+nop -+[ ]+50:[ ]+4c000020[ ]+ret -+[ ]+54:[ ]+03400000[ ]+nop -+[ ]+54: R_LARCH_ALIGN[ ]+\*ABS\*\+0xc -+[ ]+58:[ ]+03400000[ ]+nop -+[ ]+5c:[ ]+03400000[ ]+nop -+[ ]+60:[ ]+4c000020[ ]+ret -+[ ]+64:[ ]+03400000[ ]+nop -+[ ]+64: R_LARCH_ALIGN[ ]+\*ABS\*\+0xc -+[ ]+68:[ ]+03400000[ ]+nop -+[ ]+6c:[ ]+03400000[ ]+nop -+[ ]+70:[ ]+4c000020[ ]+ret -diff --git a/gas/testsuite/gas/loongarch/relax_align.s b/gas/testsuite/gas/loongarch/relax_align.s -index c0177c88..4f4867fb 100644 ---- a/gas/testsuite/gas/loongarch/relax_align.s -+++ b/gas/testsuite/gas/loongarch/relax_align.s -@@ -1,7 +1,19 @@ -+# If max < -0x80000000, max becomes a positive number because type conversion -+# (bfd_signed_vma -> unsigned int). - .text - .L1: -- la.local $a0, L1 -+ ret - .align 4 -- la.local $a0, L1 -- .align 4, , 4 -- la.local $a0, L1 -+ ret -+ .align 4, , 0 -+ ret -+ .align 4, , 1 -+ ret -+ .align 4, , 11 -+ ret -+ .align 4, , 12 -+ ret -+ .align 4, , -1 -+ ret -+ .align 4, , -0x80000000 -+ ret --- -2.33.0 - diff --git a/LoongArch-implement-count_-leading-trailing-_zeros.patch b/LoongArch-implement-count_-leading-trailing-_zeros.patch deleted file mode 100644 index fd7737f..0000000 --- a/LoongArch-implement-count_-leading-trailing-_zeros.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 92fd8ea969cddf3434830ea3f3cfa48cd3e23f30 Mon Sep 17 00:00:00 2001 -From: Xi Ruoyao -Date: Mon, 7 Aug 2023 13:07:08 +0200 -Subject: [PATCH 004/123] LoongArch: implement count_{leading,trailing}_zeros - -LoongArch always support clz and ctz instructions, so we can always use -__builtin_{clz,ctz} for count_{leading,trailing}_zeros. This improves -the code of libgcc, and also benefits Glibc once we merge longlong.h -there. - -Bootstrapped and regtested on loongarch64-linux-gnu. - -include/ - * longlong.h [__loongarch__] (count_leading_zeros): Define. - [__loongarch__] (count_trailing_zeros): Likewise. - [__loongarch__] (COUNT_LEADING_ZEROS_0): Likewise. ---- - include/longlong.h | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - -diff --git a/include/longlong.h b/include/longlong.h -index 9948a587..32d2048d 100644 ---- a/include/longlong.h -+++ b/include/longlong.h -@@ -593,6 +593,18 @@ extern UDItype __umulsidi3 (USItype, USItype); - #define UMUL_TIME 14 - #endif - -+#ifdef __loongarch__ -+# if W_TYPE_SIZE == 32 -+# define count_leading_zeros(count, x) ((count) = __builtin_clz (x)) -+# define count_trailing_zeros(count, x) ((count) = __builtin_ctz (x)) -+# define COUNT_LEADING_ZEROS_0 32 -+# elif W_TYPE_SIZE == 64 -+# define count_leading_zeros(count, x) ((count) = __builtin_clzll (x)) -+# define count_trailing_zeros(count, x) ((count) = __builtin_ctzll (x)) -+# define COUNT_LEADING_ZEROS_0 64 -+# endif -+#endif -+ - #if defined (__M32R__) && W_TYPE_SIZE == 32 - #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ - /* The cmp clears the condition bit. */ \ --- -2.33.0 - diff --git a/LoongArch-include-Add-support-for-tls-le-relax.patch b/LoongArch-include-Add-support-for-tls-le-relax.patch deleted file mode 100644 index b182e42..0000000 --- a/LoongArch-include-Add-support-for-tls-le-relax.patch +++ /dev/null @@ -1,43 +0,0 @@ -From fd100b34ac667ad62f57800762c76ac5272ceb16 Mon Sep 17 00:00:00 2001 -From: changjiachen -Date: Thu, 28 Dec 2023 19:57:30 +0800 -Subject: [PATCH 032/123] LoongArch: include: Add support for tls le relax. - -Add new relocs number for tls le relax. - -include/ChangeLog: - - * elf/loongarch.h: - (RELOC_NUMBER (R_LARCH_TLS_LE_HI20_R, 121)): New relocs number. - (RELOC_NUMBER (R_LARCH_TLS_LE_ADD_R, 122)): Likewise. - (RELOC_NUMBER (R_LARCH_TLS_LE_LO12_R, 123)): Likewise. ---- - include/elf/loongarch.h | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - -diff --git a/include/elf/loongarch.h b/include/elf/loongarch.h -index 6cfee164..1deb6ba1 100644 ---- a/include/elf/loongarch.h -+++ b/include/elf/loongarch.h -@@ -273,6 +273,18 @@ RELOC_NUMBER (R_LARCH_TLS_DESC64_HI12, 118) - RELOC_NUMBER (R_LARCH_TLS_DESC_LD, 119) - RELOC_NUMBER (R_LARCH_TLS_DESC_CALL, 120) - -+/* TLS-LE-LUI -+ lu12i.w rd,%le_hi20_r (sym). */ -+RELOC_NUMBER (R_LARCH_TLS_LE_HI20_R, 121) -+ -+/* TLS-LE-ADD -+ add.d rd,rj,rk,%le_add_r (sym). */ -+RELOC_NUMBER (R_LARCH_TLS_LE_ADD_R, 122) -+ -+/* TLS-LE-ST -+ st.w/addi.w/ld.w rd,rj,%le_lo12_r (sym). */ -+RELOC_NUMBER (R_LARCH_TLS_LE_LO12_R, 123) -+ - RELOC_NUMBER (R_LARCH_TLS_LD_PCREL20_S2, 124) - RELOC_NUMBER (R_LARCH_TLS_GD_PCREL20_S2, 125) - RELOC_NUMBER (R_LARCH_TLS_DESC_PCREL20_S2, 126) --- -2.33.0 - diff --git a/LoongArch-ld-Add-support-for-TLS-LE-symbol-with-adde.patch b/LoongArch-ld-Add-support-for-TLS-LE-symbol-with-adde.patch deleted file mode 100644 index 8a66394..0000000 --- a/LoongArch-ld-Add-support-for-TLS-LE-symbol-with-adde.patch +++ /dev/null @@ -1,105 +0,0 @@ -From 7460efab086ff238d2b4de990a6d4f89efaafc23 Mon Sep 17 00:00:00 2001 -From: mengqinggang -Date: Thu, 25 Jan 2024 09:32:14 +0800 -Subject: [PATCH 052/123] LoongArch: ld: Add support for TLS LE symbol with - addend - -Add support for TLS LE symbol with addend, such as: - lu12i.w $t0, %le_hi20(a + 0x8) - ori $t0, $t0, %le_lo12(a + 0x8) ---- - bfd/elfnn-loongarch.c | 5 ++--- - .../ld-loongarch-elf/ld-loongarch-elf.exp | 1 + - ld/testsuite/ld-loongarch-elf/tls-le.d | 14 ++++++++++++++ - ld/testsuite/ld-loongarch-elf/tls-le.s | 18 ++++++++++++++++++ - 4 files changed, 35 insertions(+), 3 deletions(-) - create mode 100644 ld/testsuite/ld-loongarch-elf/tls-le.d - create mode 100644 ld/testsuite/ld-loongarch-elf/tls-le.s - -diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c -index f57b6152..858b95e1 100644 ---- a/bfd/elfnn-loongarch.c -+++ b/bfd/elfnn-loongarch.c -@@ -3487,14 +3487,12 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, - relocation += rel->r_addend; - - RELOCATE_CALC_PC32_HI20 (relocation, pc); -- - break; - - case R_LARCH_TLS_LE_HI20_R: -+ relocation += rel->r_addend; - relocation -= elf_hash_table (info)->tls_sec->vma; -- - RELOCATE_TLS_TP32_HI20 (relocation); -- - break; - - case R_LARCH_PCALA_LO12: -@@ -3675,6 +3673,7 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, - case R_LARCH_TLS_LE64_HI12: - BFD_ASSERT (resolved_local && elf_hash_table (info)->tls_sec); - -+ relocation += rel->r_addend; - relocation -= elf_hash_table (info)->tls_sec->vma; - break; - -diff --git a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -index c81f20af..46b53536 100644 ---- a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -+++ b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -@@ -34,6 +34,7 @@ if [istarget "loongarch64-*-*"] { - run_dump_test "local-ifunc-reloc" - run_dump_test "anno-sym" - run_dump_test "pcala64" -+ run_dump_test "tls-le" - } - - if [istarget "loongarch32-*-*"] { -diff --git a/ld/testsuite/ld-loongarch-elf/tls-le.d b/ld/testsuite/ld-loongarch-elf/tls-le.d -new file mode 100644 -index 00000000..cbd6adb8 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/tls-le.d -@@ -0,0 +1,14 @@ -+#ld: --no-relax -+#objdump: -d -+ -+.*:[ ]+file format .* -+ -+ -+Disassembly of section .text: -+ -+[ ]*00000001200000e8 <_start>: -+[ ]+1200000e8:[ ]+14000004[ ]+lu12i.w[ ]+\$a0, 0 -+[ ]+1200000ec:[ ]+03802085[ ]+ori[ ]+\$a1, \$a0, 0x8 -+[ ]+1200000f0:[ ]+14000004[ ]+lu12i.w[ ]+\$a0, 0 -+[ ]+1200000f4:[ ]+02c02085[ ]+addi.d[ ]+\$a1, \$a0, 8 -+[ ]+1200000f8:[ ]+4c000020[ ]+ret -diff --git a/ld/testsuite/ld-loongarch-elf/tls-le.s b/ld/testsuite/ld-loongarch-elf/tls-le.s -new file mode 100644 -index 00000000..2e6a9de4 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/tls-le.s -@@ -0,0 +1,18 @@ -+# Support for TLS LE symbols with addend -+ .text -+ .globl a -+ .section .tdata,"awT",@progbits -+ .align 2 -+ .type a, @object -+ .size a, 4 -+a: -+ .word 123 -+ -+ .text -+ .global _start -+_start: -+ lu12i.w $r4,%le_hi20(a + 0x8) -+ ori $r5,$r4,%le_lo12(a + 0x8) -+ lu12i.w $r4,%le_hi20_r(a + 0x8) -+ addi.d $r5,$r4,%le_lo12_r(a + 0x8) -+ jr $ra --- -2.33.0 - diff --git a/LoongArch-ld-Add-support-for-tls-le-relax.patch b/LoongArch-ld-Add-support-for-tls-le-relax.patch deleted file mode 100644 index bcfe742..0000000 --- a/LoongArch-ld-Add-support-for-tls-le-relax.patch +++ /dev/null @@ -1,410 +0,0 @@ -From 752d56ec3ba19235fd3d75fd30adaa4bec10dded Mon Sep 17 00:00:00 2001 -From: changjiachen -Date: Thu, 28 Dec 2023 20:01:15 +0800 -Subject: [PATCH 035/123] LoongArch: ld: Add support for tls le relax. - -Add tls le relax related testsuites in ld. - -The new test cases are mainly tested in three aspects: - -1. tls le relax function correctness test. -2. tls le relax boundary check test. -3. tls le relax function compatibility test. - -ld/testsuite/ChangeLog: - - * ld/testsuite/ld-loongarch-elf/relax.exp: Modify test. - * ld/testsuite/ld-loongarch-elf/old-tls-le.s: New test. - * ld/testsuite/ld-loongarch-elf/relax-bound-check-tls-le.s: Likewise. - * ld/testsuite/ld-loongarch-elf/tls-relax-compatible-check-new.s: Likewise. - * ld/testsuite/ld-loongarch-elf/relax-tls-le.s: Likewise. - * ld/testsuite/ld-loongarch-elf/tls-relax-compatible-check-old.s: Likewise. ---- - ld/testsuite/ld-loongarch-elf/old-tls-le.s | 23 +++ - .../relax-bound-check-tls-le.s | 53 ++++++ - ld/testsuite/ld-loongarch-elf/relax-tls-le.s | 26 +++ - ld/testsuite/ld-loongarch-elf/relax.exp | 151 +++++++++++++++++- - .../tls-relax-compatible-check-new.s | 35 ++++ - .../tls-relax-compatible-check-old.s | 33 ++++ - 6 files changed, 320 insertions(+), 1 deletion(-) - create mode 100644 ld/testsuite/ld-loongarch-elf/old-tls-le.s - create mode 100644 ld/testsuite/ld-loongarch-elf/relax-bound-check-tls-le.s - create mode 100644 ld/testsuite/ld-loongarch-elf/relax-tls-le.s - create mode 100644 ld/testsuite/ld-loongarch-elf/tls-relax-compatible-check-new.s - create mode 100644 ld/testsuite/ld-loongarch-elf/tls-relax-compatible-check-old.s - -diff --git a/ld/testsuite/ld-loongarch-elf/old-tls-le.s b/ld/testsuite/ld-loongarch-elf/old-tls-le.s -new file mode 100644 -index 00000000..be3d2b9c ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/old-tls-le.s -@@ -0,0 +1,23 @@ -+/* This test case mainly tests whether the original -+ tls le assembly instruction can be linked normally -+ after tls le relax is added to the current ld. */ -+ -+ .text -+ .globl aa -+ .section .tbss,"awT",@nobits -+ .align 2 -+ .type aa, @object -+ .size aa, 4 -+aa: -+ .space 4 -+ .text -+ .align 2 -+ .globl main -+ .type main, @function -+main: -+ lu12i.w $r12,%le_hi20(aa) -+ ori $r12,$r12,%le_lo12(aa) -+ add.d $r12,$r12,$r2 -+ addi.w $r13,$r0,2 # 0x2 -+ stptr.w $r13,$r12,0 -+ -diff --git a/ld/testsuite/ld-loongarch-elf/relax-bound-check-tls-le.s b/ld/testsuite/ld-loongarch-elf/relax-bound-check-tls-le.s -new file mode 100644 -index 00000000..b2a64b5d ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/relax-bound-check-tls-le.s -@@ -0,0 +1,53 @@ -+/* This test case mainly tests whether the address of the -+ tls le symbol can be resolved normally when the offset -+ of the symbol is greater than 0x800. (When the symbol -+ offset is greater than 0x800, relax is not performed). */ -+ -+ .text -+ .globl count1 -+ .section .tbss,"awT",@nobits -+ .align 2 -+ .type count1, @object -+ .size count1, 4 -+count1: -+ .space 0x400 -+ .globl count2 -+ .align 2 -+ .type count2, @object -+ .size count2, 4 -+count2: -+ .space 0x400 -+ .globl count3 -+ .align 2 -+ .type count3, @object -+ .size count3, 4 -+count3: -+ .space 0x400 -+ .globl count4 -+ .align 2 -+ .type count4, @object -+ .size count4, 4 -+count4: -+ .space 4 -+ .text -+ .align 2 -+ .globl main -+ .type main, @function -+main: -+ lu12i.w $r12,%le_hi20_r(count1) -+ add.d $r12,$r12,$r2,%le_add_r(count1) -+ addi.w $r13,$r0,1 -+ st.w $r13,$r12,%le_lo12_r(count1) -+ lu12i.w $r12,%le_hi20_r(count2) -+ add.d $r12,$r12,$r2,%le_add_r(count2) -+ addi.w $r13,$r0,2 -+ st.w $r13,$r12,%le_lo12_r(count2) -+ lu12i.w $r12,%le_hi20(count3) -+ add.d $r12,$r12,$r2,%le_add_r(count3) -+ addi.w $r13,$r0,3 -+ st.w $r13,$r12,%le_lo12_r(count3) -+ lu12i.w $r12,%le_hi20(count4) -+ add.d $r12,$r12,$r2,%le_add_r(count4) -+ addi.w $r13,$r0,4 -+ st.w $r13,$r12,%le_lo12_r(count4) -+ -diff --git a/ld/testsuite/ld-loongarch-elf/relax-tls-le.s b/ld/testsuite/ld-loongarch-elf/relax-tls-le.s -new file mode 100644 -index 00000000..1ea53baf ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/relax-tls-le.s -@@ -0,0 +1,26 @@ -+/* This test case mainly tests whether the tls le variable -+ address acquisition can be relax normally. -+ -+ before relax: after relax: -+ -+ lu12i.w $r12,%le_hi20_r(sym) ====> (instruction deleted). -+ add.d $r12,$r12,$r2,%le_add_r(sym) ====> (instruction deleted). -+ st.w $r13,$r12,%le_lo12_r(sym) ====> st.w $r13,$r2,%le_lo12_r(sym). */ -+ -+ .text -+ .globl a -+ .section .tbss,"awT",@nobits -+ .align 2 -+ .type a, @object -+ .size a, 4 -+a: -+ .space 4 -+ .text -+ .align 2 -+ .globl main -+ .type main, @function -+main: -+ lu12i.w $r12,%le_hi20_r(a) -+ add.d $r12,$r12,$r2,%le_add_r(a) -+ addi.w $r13,$r0,1 # 0x1 -+ st.w $r13,$r12,%le_lo12_r(a) -diff --git a/ld/testsuite/ld-loongarch-elf/relax.exp b/ld/testsuite/ld-loongarch-elf/relax.exp -index 77323d8d..b697d015 100644 ---- a/ld/testsuite/ld-loongarch-elf/relax.exp -+++ b/ld/testsuite/ld-loongarch-elf/relax.exp -@@ -33,8 +33,90 @@ if [istarget loongarch64-*-*] { - "relax" \ - ] \ - ] -+ set tls_relax_builds [list \ -+ [list \ -+ "tls_relax_builds" \ -+ "" \ -+ "" \ -+ {relax-tls-le.s} \ -+ {} \ -+ "relax-tls-le" \ -+ ] \ -+ ] -+ set tls_no_relax_builds [list \ -+ [list \ -+ "tls_no_relax_builds" \ -+ "-Wl,--no-relax" \ -+ "" \ -+ {relax-tls-le.s} \ -+ {} \ -+ "no-relax-tls-le" \ -+ ] \ -+ ] -+ -+ set relax_bound_check [list \ -+ [list \ -+ "relax_bound_check" \ -+ "" \ -+ "" \ -+ {relax-bound-check-tls-le.s} \ -+ {} \ -+ "relax-bound-check-tls-le" \ -+ ] \ -+ ] -+ set no_relax_bound_check [list \ -+ [list \ -+ "no_relax_bound_check" \ -+ "-Wl,--no-relax" \ -+ "" \ -+ {relax-bound-check-tls-le.s} \ -+ {} \ -+ "no-relax-bound-check-tls-le" \ -+ ] \ -+ ] -+ -+ set old_tls_le [list \ -+ [list \ -+ "old_tls_le" \ -+ "" \ -+ "" \ -+ {old-tls-le.s} \ -+ {} \ -+ "old-tls-le" \ -+ ] \ -+ ] -+ -+ set relax_compatible [list \ -+ [list \ -+ "relax_compatible" \ -+ "" \ -+ "" \ -+ {tls-relax-compatible-check-new.s tls-relax-compatible-check-old.s} \ -+ {} \ -+ "realx-compatible" \ -+ ] \ -+ ] -+ -+ set no_relax_compatible [list \ -+ [list \ -+ "no_relax_compatible" \ -+ "-Wl,--no-relax" \ -+ "" \ -+ {tls-relax-compatible-check-new.s tls-relax-compatible-check-old.s} \ -+ {} \ -+ "no-realx-compatible" \ -+ ] \ -+ ] -+ - - run_cc_link_tests $pre_builds -+ run_cc_link_tests $tls_relax_builds -+ run_cc_link_tests $tls_no_relax_builds -+ run_cc_link_tests $relax_bound_check -+ run_cc_link_tests $no_relax_bound_check -+ run_cc_link_tests $old_tls_le -+ run_cc_link_tests $relax_compatible -+ run_cc_link_tests $no_relax_compatible - - if [file exist "tmpdir/relax"] { - set objdump_output [run_host_cmd "objdump" "-d tmpdir/relax"] -@@ -114,8 +196,75 @@ if [istarget loongarch64-*-*] { - "relax-segment-max" \ - ] \ - ] -- } - -+ if [file exist "tmpdir/relax-tls-le"] { -+ set objdump_output1 [run_host_cmd "objdump" "-d tmpdir/relax-tls-le"] -+ if { [ regexp ".addi.*st.*" $objdump_output1] } { -+ pass "loongarch relax success" -+ } { -+ fail "loongarch relax fail" -+ } -+ } -+ if [file exist "tmpdir/no-relax-tls-le"] { -+ set objdump_output2 [run_host_cmd "objdump" "-d tmpdir/no-relax-tls-le"] -+ if { [ regexp ".*lu12i.*add.*addi.*st.*" $objdump_output2] } { -+ pass "loongarch no-relax success" -+ } { -+ fail "loongarch no-relax fail" -+ } -+ -+ } -+ if [file exist "tmpdir/old-tls-le"] { -+ set objdump_output3 [run_host_cmd "objdump" "-d tmpdir/old-tls-le"] -+ if { [ regexp ".*lu12i.*ori.*add.*addi.*stptr.*" $objdump_output3] } { -+ pass "loongarch old tls le success" -+ } { -+ fail "loongarch old tls le fail" -+ } -+ -+ } -+ -+ if [file exist "tmpdir/realx-compatible"] { -+ set objdump_output4 [run_host_cmd "objdump" "-d tmpdir/realx-compatible"] -+ if { [ regexp ".addi.*st.*" $objdump_output4] && \ -+ [ regexp ".*lu12i.*ori.*add.*addi.*stptr.*" $objdump_output4] } { -+ pass "loongarch tls le relax compatible check success" -+ } { -+ fail "loongarch tls le relax compatible check fail" -+ } -+ } -+ -+ if [file exist "tmpdir/no-realx-compatible"] { -+ set objdump_output4 [run_host_cmd "objdump" "-d tmpdir/realx-compatible"] -+ if { [ regexp ".*lu12i.*add.*addi.*st.*" $objdump_output4] && \ -+ [ regexp ".*lu12i.*ori.*add.*addi.*stptr.*" $objdump_output4] } { -+ pass "loongarch tls le no-relax compatible check success" -+ } { -+ fail "loongarch tls le no-relax compatible check fail" -+ } -+ } -+ -+ -+ if [file exist "tmpdir/relax-bound-check-tls-le"] { -+ set objdump_output5 [run_host_cmd "objdump" "-d tmpdir/relax-bound-check-tls-le"] -+ if { [ regexp ".*lu12i.*add.*addi.*st.*" $objdump_output5] && \ -+ [ regexp ".addi.*st.*" $objdump_output5] } { -+ pass "loongarch no-relax success" -+ } { -+ fail "loongarch no-relax fail" -+ } -+ -+ } -+ if [file exist "tmpdir/no-relax-bound-check-tls-le"] { -+ set objdump_output5 [run_host_cmd "objdump" "-d tmpdir/no-relax-bound-check-tls-le"] -+ if { [ regexp ".*addi.*st.*" $objdump_output5] } { -+ pass "loongarch no-relax success" -+ } { -+ fail "loongarch no-relax fail" -+ } -+ } -+ -+ } - run_ld_link_tests \ - [list \ - [list \ -diff --git a/ld/testsuite/ld-loongarch-elf/tls-relax-compatible-check-new.s b/ld/testsuite/ld-loongarch-elf/tls-relax-compatible-check-new.s -new file mode 100644 -index 00000000..059ca0b9 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/tls-relax-compatible-check-new.s -@@ -0,0 +1,35 @@ -+/* This test case mainly carries out ld compatibility test. -+ This test case is the new tls le instruction sequence, -+ which will be linked with tls-relax-compatible-check-old.s. -+ If the link is normal, it indicates that there is no -+ compatibility problem. */ -+ -+ .text -+ .globl new -+ .section .tbss,"awT",@nobits -+ .align 2 -+ .type new, @object -+ .size new, 4 -+new: -+ .space 4 -+ .text -+ .align 2 -+ .globl main -+ .type main, @function -+main: -+.LFB0 = . -+ addi.d $r3,$r3,-16 -+ st.d $r1,$r3,8 -+ stptr.d $r22,$r3,0 -+ addi.d $r22,$r3,16 -+ bl %plt(old) -+ lu12i.w $r12,%le_hi20_r(new) -+ add.d $r12,$r12,$r2,%le_add_r(new) -+ addi.w $r13,$r0,2 # 0x2 -+ st.w $r13,$r12,%le_lo12_r(new) -+ or $r12,$r0,$r0 -+ or $r4,$r12,$r0 -+ ld.d $r1,$r3,8 -+ ldptr.d $r22,$r3,0 -+ addi.d $r3,$r3,16 -+ jr $r1 -diff --git a/ld/testsuite/ld-loongarch-elf/tls-relax-compatible-check-old.s b/ld/testsuite/ld-loongarch-elf/tls-relax-compatible-check-old.s -new file mode 100644 -index 00000000..083a2688 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/tls-relax-compatible-check-old.s -@@ -0,0 +1,33 @@ -+/* This test case mainly carries out ld compatibility test. -+ This test case is the old tls le instruction sequence, -+ which will be linked with tls-relax-compatible-check-new.s. -+ If the link is normal, it indicates that there is no -+ compatibility problem. */ -+ -+ .text -+ .globl older -+ .section .tbss,"awT",@nobits -+ .align 2 -+ .type older, @object -+ .size older, 4 -+older: -+ .space 4 -+ .text -+ .align 2 -+ .globl old -+ .type old, @function -+old: -+.LFB0 = . -+ addi.d $r3,$r3,-16 -+ st.d $r22,$r3,8 -+ addi.d $r22,$r3,16 -+ lu12i.w $r12,%le_hi20(older) -+ ori $r12,$r12,%le_lo12(older) -+ add.d $r12,$r12,$r2 -+ addi.w $r13,$r0,1 # 0x1 -+ stptr.w $r13,$r12,0 -+ nop -+ or $r4,$r12,$r0 -+ ld.d $r22,$r3,8 -+ addi.d $r3,$r3,16 -+ jr $r1 --- -2.33.0 - diff --git a/LoongArch-ld-Adjusted-some-code-order-in-relax.exp.patch b/LoongArch-ld-Adjusted-some-code-order-in-relax.exp.patch deleted file mode 100644 index 1601347..0000000 --- a/LoongArch-ld-Adjusted-some-code-order-in-relax.exp.patch +++ /dev/null @@ -1,340 +0,0 @@ -From 075962ddaa562d7d9b9bd9de8a5204e3913ea36a Mon Sep 17 00:00:00 2001 -From: changjiachen -Date: Thu, 4 Jan 2024 14:06:09 +0800 -Subject: [PATCH 042/123] LoongArch: ld: Adjusted some code order in relax.exp. - - ld/testsuite/ChangeLog: - - * ld/testsuite/ld-loongarch-elf/relax.exp: Modify test. ---- - ld/testsuite/ld-loongarch-elf/relax.exp | 298 ++++++++++++------------ - 1 file changed, 149 insertions(+), 149 deletions(-) - -diff --git a/ld/testsuite/ld-loongarch-elf/relax.exp b/ld/testsuite/ld-loongarch-elf/relax.exp -index 6c65318a..aed8457d 100644 ---- a/ld/testsuite/ld-loongarch-elf/relax.exp -+++ b/ld/testsuite/ld-loongarch-elf/relax.exp -@@ -33,90 +33,8 @@ if [istarget loongarch64-*-*] { - "relax" \ - ] \ - ] -- set tls_relax_builds [list \ -- [list \ -- "tls_relax_builds" \ -- "" \ -- "" \ -- {relax-tls-le.s} \ -- {} \ -- "relax-tls-le" \ -- ] \ -- ] -- set tls_no_relax_builds [list \ -- [list \ -- "tls_no_relax_builds" \ -- "-Wl,--no-relax" \ -- "" \ -- {relax-tls-le.s} \ -- {} \ -- "no-relax-tls-le" \ -- ] \ -- ] -- -- set relax_bound_check [list \ -- [list \ -- "relax_bound_check" \ -- "" \ -- "" \ -- {relax-bound-check-tls-le.s} \ -- {} \ -- "relax-bound-check-tls-le" \ -- ] \ -- ] -- set no_relax_bound_check [list \ -- [list \ -- "no_relax_bound_check" \ -- "-Wl,--no-relax" \ -- "" \ -- {relax-bound-check-tls-le.s} \ -- {} \ -- "no-relax-bound-check-tls-le" \ -- ] \ -- ] -- -- set old_tls_le [list \ -- [list \ -- "old_tls_le" \ -- "" \ -- "" \ -- {old-tls-le.s} \ -- {} \ -- "old-tls-le" \ -- ] \ -- ] -- -- set relax_compatible [list \ -- [list \ -- "relax_compatible" \ -- "" \ -- "" \ -- {tls-relax-compatible-check-new.s tls-relax-compatible-check-old.s} \ -- {} \ -- "realx-compatible" \ -- ] \ -- ] -- -- set no_relax_compatible [list \ -- [list \ -- "no_relax_compatible" \ -- "-Wl,--no-relax" \ -- "" \ -- {tls-relax-compatible-check-new.s tls-relax-compatible-check-old.s} \ -- {} \ -- "no-realx-compatible" \ -- ] \ -- ] -- - - run_cc_link_tests $pre_builds -- run_cc_link_tests $tls_relax_builds -- run_cc_link_tests $tls_no_relax_builds -- run_cc_link_tests $relax_bound_check -- run_cc_link_tests $no_relax_bound_check -- run_cc_link_tests $old_tls_le -- run_cc_link_tests $relax_compatible -- run_cc_link_tests $no_relax_compatible - - if [file exist "tmpdir/relax"] { - set objdump_output [run_host_cmd "objdump" "-d tmpdir/relax"] -@@ -173,6 +91,155 @@ if [istarget loongarch64-*-*] { - } - } - -+ run_ld_link_tests \ -+ [list \ -+ [list \ -+ "loongarch tls le relax .exe build" \ -+ "" "" \ -+ "" \ -+ {relax-tls-le.s} \ -+ {} \ -+ "relax-tls-le" \ -+ ] \ -+ ] -+ -+ if [file exist "tmpdir/relax-tls-le"] { -+ set objdump_output1 [run_host_cmd "objdump" "-d tmpdir/relax-tls-le"] -+ if { [ regexp ".addi.*st.*" $objdump_output1] } { -+ pass "loongarch relax success" -+ } { -+ fail "loongarch relax fail" -+ } -+ } -+ -+ run_ld_link_tests \ -+ [list \ -+ [list \ -+ "loongarch tls le no relax .exe build" \ -+ "--no-relax" "" \ -+ "" \ -+ {relax-tls-le.s} \ -+ {} \ -+ "no-relax-tls-le" \ -+ ] \ -+ ] -+ -+ if [file exist "tmpdir/no-relax-tls-le"] { -+ set objdump_output2 [run_host_cmd "objdump" "-d tmpdir/no-relax-tls-le"] -+ if { [ regexp ".*lu12i.*add.*addi.*st.*" $objdump_output2] } { -+ pass "loongarch no-relax success" -+ } { -+ fail "loongarch no-relax fail" -+ } -+ } -+ -+ run_ld_link_tests \ -+ [list \ -+ [list \ -+ "loongarch old tls le .exe build" \ -+ "" "" \ -+ "" \ -+ {old-tls-le.s} \ -+ {} \ -+ "old-tls-le" \ -+ ] \ -+ ] -+ -+ if [file exist "tmpdir/old-tls-le"] { -+ set objdump_output3 [run_host_cmd "objdump" "-d tmpdir/old-tls-le"] -+ if { [ regexp ".*lu12i.*ori.*add.*addi.*stptr.*" $objdump_output3] } { -+ pass "loongarch old tls le success" -+ } { -+ fail "loongarch old tls le fail" -+ } -+ } -+ -+ run_ld_link_tests \ -+ [list \ -+ [list \ -+ "loongarch tls le realx compatible .exe build" \ -+ "" "" \ -+ "" \ -+ {tls-relax-compatible-check-new.s tls-relax-compatible-check-old.s} \ -+ {} \ -+ "realx-compatible" \ -+ ] \ -+ ] -+ -+ if [file exist "tmpdir/realx-compatible"] { -+ set objdump_output4 [run_host_cmd "objdump" "-d tmpdir/realx-compatible"] -+ if { [ regexp ".addi.*st.*" $objdump_output4] && \ -+ [ regexp ".*lu12i.*ori.*add.*addi.*stptr.*" $objdump_output4] } { -+ pass "loongarch tls le relax compatible check success" -+ } { -+ fail "loongarch tls le relax compatible check fail" -+ } -+ } -+ -+ run_ld_link_tests \ -+ [list \ -+ [list \ -+ "loongarch tls le no realx compatible .exe build" \ -+ "--no-relax" "" \ -+ "" \ -+ {tls-relax-compatible-check-new.s tls-relax-compatible-check-old.s} \ -+ {} \ -+ "no-realx-compatible" \ -+ ] \ -+ ] -+ if [file exist "tmpdir/no-realx-compatible"] { -+ set objdump_output4 [run_host_cmd "objdump" "-d tmpdir/no-realx-compatible"] -+ if { [ regexp ".*lu12i.*add.*addi.*st.*" $objdump_output4] && \ -+ [ regexp ".*lu12i.*ori.*add.*addi.*stptr.*" $objdump_output4] } { -+ pass "loongarch tls le no-relax compatible check success" -+ } { -+ fail "loongarch tls le no-relax compatible check fail" -+ } -+ } -+ -+ run_ld_link_tests \ -+ [list \ -+ [list \ -+ "loongarch tls le realx bound-check .exe build" \ -+ "" "" \ -+ "" \ -+ {relax-bound-check-tls-le.s} \ -+ {} \ -+ "relax-bound-check-tls-le" \ -+ ] \ -+ ] -+ -+ if [file exist "tmpdir/relax-bound-check-tls-le"] { -+ set objdump_output5 [run_host_cmd "objdump" "-d tmpdir/relax-bound-check-tls-le"] -+ if { [ regexp ".*lu12i.*add.*addi.*st.*" $objdump_output5] && \ -+ [ regexp ".addi.*st.*" $objdump_output5] } { -+ pass "loongarch no-relax success" -+ } { -+ fail "loongarch no-relax fail" -+ } -+ } -+ -+ run_ld_link_tests \ -+ [list \ -+ [list \ -+ "loongarch tls le no realx bound-check .exe build" \ -+ "--no-relax" "" \ -+ "" \ -+ {relax-bound-check-tls-le.s} \ -+ {} \ -+ "no-relax-bound-check-tls-le" \ -+ ] \ -+ ] -+ -+ if [file exist "tmpdir/no-relax-bound-check-tls-le"] { -+ set objdump_output5 [run_host_cmd "objdump" "-d tmpdir/no-relax-bound-check-tls-le"] -+ if { [ regexp ".*addi.*st.*" $objdump_output5] } { -+ pass "loongarch no-relax success" -+ } { -+ fail "loongarch no-relax fail" -+ } -+ } -+ - # If symbol in data segment, offset need to sub segment align to prevent - # overflow. - if [check_pie_support] { -@@ -201,73 +268,6 @@ if [istarget loongarch64-*-*] { - ] - } - -- if [file exist "tmpdir/relax-tls-le"] { -- set objdump_output1 [run_host_cmd "objdump" "-d tmpdir/relax-tls-le"] -- if { [ regexp ".addi.*st.*" $objdump_output1] } { -- pass "loongarch relax success" -- } { -- fail "loongarch relax fail" -- } -- } -- if [file exist "tmpdir/no-relax-tls-le"] { -- set objdump_output2 [run_host_cmd "objdump" "-d tmpdir/no-relax-tls-le"] -- if { [ regexp ".*lu12i.*add.*addi.*st.*" $objdump_output2] } { -- pass "loongarch no-relax success" -- } { -- fail "loongarch no-relax fail" -- } -- -- } -- if [file exist "tmpdir/old-tls-le"] { -- set objdump_output3 [run_host_cmd "objdump" "-d tmpdir/old-tls-le"] -- if { [ regexp ".*lu12i.*ori.*add.*addi.*stptr.*" $objdump_output3] } { -- pass "loongarch old tls le success" -- } { -- fail "loongarch old tls le fail" -- } -- -- } -- -- if [file exist "tmpdir/realx-compatible"] { -- set objdump_output4 [run_host_cmd "objdump" "-d tmpdir/realx-compatible"] -- if { [ regexp ".addi.*st.*" $objdump_output4] && \ -- [ regexp ".*lu12i.*ori.*add.*addi.*stptr.*" $objdump_output4] } { -- pass "loongarch tls le relax compatible check success" -- } { -- fail "loongarch tls le relax compatible check fail" -- } -- } -- -- if [file exist "tmpdir/no-realx-compatible"] { -- set objdump_output4 [run_host_cmd "objdump" "-d tmpdir/realx-compatible"] -- if { [ regexp ".*lu12i.*add.*addi.*st.*" $objdump_output4] && \ -- [ regexp ".*lu12i.*ori.*add.*addi.*stptr.*" $objdump_output4] } { -- pass "loongarch tls le no-relax compatible check success" -- } { -- fail "loongarch tls le no-relax compatible check fail" -- } -- } -- -- -- if [file exist "tmpdir/relax-bound-check-tls-le"] { -- set objdump_output5 [run_host_cmd "objdump" "-d tmpdir/relax-bound-check-tls-le"] -- if { [ regexp ".*lu12i.*add.*addi.*st.*" $objdump_output5] && \ -- [ regexp ".addi.*st.*" $objdump_output5] } { -- pass "loongarch no-relax success" -- } { -- fail "loongarch no-relax fail" -- } -- -- } -- if [file exist "tmpdir/no-relax-bound-check-tls-le"] { -- set objdump_output5 [run_host_cmd "objdump" "-d tmpdir/no-relax-bound-check-tls-le"] -- if { [ regexp ".*addi.*st.*" $objdump_output5] } { -- pass "loongarch no-relax success" -- } { -- fail "loongarch no-relax fail" -- } -- } -- - } - - if [check_shared_lib_support] { --- -2.33.0 - diff --git a/LoongArch-ld-Fix-other-pop-relocs-overflow-check-and.patch b/LoongArch-ld-Fix-other-pop-relocs-overflow-check-and.patch deleted file mode 100644 index 01ba915..0000000 --- a/LoongArch-ld-Fix-other-pop-relocs-overflow-check-and.patch +++ /dev/null @@ -1,787 +0,0 @@ -From 4fcc588a781a65c6a939dc74644c98a0f039f879 Mon Sep 17 00:00:00 2001 -From: Jinyang He -Date: Tue, 5 Sep 2023 10:31:28 +0800 -Subject: [PATCH 059/123] LoongArch: ld: Fix other pop relocs overflow check - and add tests - -Add reloc_unsign_bits() to fix others sop_pop relocs overflow check. -Then add over/underflow tests for relocs B*, SOP_POP* and PCREL20_S2. - -bfd/ChangeLog: - - * bfd/elfxx-loongarch.c: Add reloc_unsign_bits(). - -ld/ChangeLog: - - * ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp: Add tests. - * ld/testsuite/ld-loongarch-elf/abi1_max_imm.dd: New test. - * ld/testsuite/ld-loongarch-elf/abi1_max_imm.s: New test. - * ld/testsuite/ld-loongarch-elf/abi1_sops.s: New test. - * ld/testsuite/ld-loongarch-elf/abi2_max_imm.s: New test. - * ld/testsuite/ld-loongarch-elf/abi2_overflows.s: New test. - * ld/testsuite/ld-loongarch-elf/max_imm_b16.d: New test. - * ld/testsuite/ld-loongarch-elf/max_imm_b21.d: New test. - * ld/testsuite/ld-loongarch-elf/max_imm_b26.d: New test. - * ld/testsuite/ld-loongarch-elf/max_imm_pcrel20.d: New test. - * ld/testsuite/ld-loongarch-elf/overflow_b16.d: New test. - * ld/testsuite/ld-loongarch-elf/overflow_b21.d: New test. - * ld/testsuite/ld-loongarch-elf/overflow_b26.d: New test. - * ld/testsuite/ld-loongarch-elf/overflow_pcrel20.d: New test. - * ld/testsuite/ld-loongarch-elf/overflow_s_0_10_10_16_s2.d: New test. - * ld/testsuite/ld-loongarch-elf/overflow_s_0_5_10_16_s2.d: New test. - * ld/testsuite/ld-loongarch-elf/overflow_s_10_12.d: New test. - * ld/testsuite/ld-loongarch-elf/overflow_s_10_16.d: New test. - * ld/testsuite/ld-loongarch-elf/overflow_s_10_16_s2.d: New test. - * ld/testsuite/ld-loongarch-elf/overflow_s_10_5.d: New test. - * ld/testsuite/ld-loongarch-elf/overflow_s_5_20.d: New test. - * ld/testsuite/ld-loongarch-elf/overflow_u.d: New test. - * ld/testsuite/ld-loongarch-elf/overflow_u_10_12.d: New test. - * ld/testsuite/ld-loongarch-elf/underflow_b16.d: New test. - * ld/testsuite/ld-loongarch-elf/underflow_b21.d: New test. - * ld/testsuite/ld-loongarch-elf/underflow_b26.d: New test. - * ld/testsuite/ld-loongarch-elf/underflow_pcrel20.d: New test. - * ld/testsuite/ld-loongarch-elf/underflow_s_0_10_10_16_s2.d: New test. - * ld/testsuite/ld-loongarch-elf/underflow_s_0_5_10_16_s2.d: New test. - * ld/testsuite/ld-loongarch-elf/underflow_s_10_12.d: New test. - * ld/testsuite/ld-loongarch-elf/underflow_s_10_16.d: New test. - * ld/testsuite/ld-loongarch-elf/underflow_s_10_16_s2.d: New test. - * ld/testsuite/ld-loongarch-elf/underflow_s_10_5.d: New test. - * ld/testsuite/ld-loongarch-elf/underflow_s_5_20.d: New test. ---- - bfd/elfxx-loongarch.c | 34 +++++++++++---- - ld/testsuite/ld-loongarch-elf/abi1_max_imm.dd | 18 ++++++++ - ld/testsuite/ld-loongarch-elf/abi1_max_imm.s | 39 +++++++++++++++++ - ld/testsuite/ld-loongarch-elf/abi1_sops.s | 43 +++++++++++++++++++ - ld/testsuite/ld-loongarch-elf/abi2_max_imm.s | 24 +++++++++++ - .../ld-loongarch-elf/abi2_overflows.s | 24 +++++++++++ - .../ld-loongarch-elf/ld-loongarch-elf.exp | 39 +++++++++++++++++ - ld/testsuite/ld-loongarch-elf/max_imm_b16.d | 9 ++++ - ld/testsuite/ld-loongarch-elf/max_imm_b21.d | 9 ++++ - ld/testsuite/ld-loongarch-elf/max_imm_b26.d | 9 ++++ - .../ld-loongarch-elf/max_imm_pcrel20.d | 9 ++++ - ld/testsuite/ld-loongarch-elf/overflow_b16.d | 4 ++ - ld/testsuite/ld-loongarch-elf/overflow_b21.d | 4 ++ - ld/testsuite/ld-loongarch-elf/overflow_b26.d | 4 ++ - .../ld-loongarch-elf/overflow_pcrel20.d | 4 ++ - .../overflow_s_0_10_10_16_s2.d | 4 ++ - .../overflow_s_0_5_10_16_s2.d | 4 ++ - .../ld-loongarch-elf/overflow_s_10_12.d | 4 ++ - .../ld-loongarch-elf/overflow_s_10_16.d | 4 ++ - .../ld-loongarch-elf/overflow_s_10_16_s2.d | 4 ++ - .../ld-loongarch-elf/overflow_s_10_5.d | 4 ++ - .../ld-loongarch-elf/overflow_s_5_20.d | 4 ++ - ld/testsuite/ld-loongarch-elf/overflow_u.d | 4 ++ - .../ld-loongarch-elf/overflow_u_10_12.d | 4 ++ - ld/testsuite/ld-loongarch-elf/underflow_b16.d | 4 ++ - ld/testsuite/ld-loongarch-elf/underflow_b21.d | 4 ++ - ld/testsuite/ld-loongarch-elf/underflow_b26.d | 4 ++ - .../ld-loongarch-elf/underflow_pcrel20.d | 4 ++ - .../underflow_s_0_10_10_16_s2.d | 4 ++ - .../underflow_s_0_5_10_16_s2.d | 4 ++ - .../ld-loongarch-elf/underflow_s_10_12.d | 4 ++ - .../ld-loongarch-elf/underflow_s_10_16.d | 4 ++ - .../ld-loongarch-elf/underflow_s_10_16_s2.d | 4 ++ - .../ld-loongarch-elf/underflow_s_10_5.d | 4 ++ - .../ld-loongarch-elf/underflow_s_5_20.d | 4 ++ - 35 files changed, 344 insertions(+), 9 deletions(-) - create mode 100644 ld/testsuite/ld-loongarch-elf/abi1_max_imm.dd - create mode 100644 ld/testsuite/ld-loongarch-elf/abi1_max_imm.s - create mode 100644 ld/testsuite/ld-loongarch-elf/abi1_sops.s - create mode 100644 ld/testsuite/ld-loongarch-elf/abi2_max_imm.s - create mode 100644 ld/testsuite/ld-loongarch-elf/abi2_overflows.s - create mode 100644 ld/testsuite/ld-loongarch-elf/max_imm_b16.d - create mode 100644 ld/testsuite/ld-loongarch-elf/max_imm_b21.d - create mode 100644 ld/testsuite/ld-loongarch-elf/max_imm_b26.d - create mode 100644 ld/testsuite/ld-loongarch-elf/max_imm_pcrel20.d - create mode 100644 ld/testsuite/ld-loongarch-elf/overflow_b16.d - create mode 100644 ld/testsuite/ld-loongarch-elf/overflow_b21.d - create mode 100644 ld/testsuite/ld-loongarch-elf/overflow_b26.d - create mode 100644 ld/testsuite/ld-loongarch-elf/overflow_pcrel20.d - create mode 100644 ld/testsuite/ld-loongarch-elf/overflow_s_0_10_10_16_s2.d - create mode 100644 ld/testsuite/ld-loongarch-elf/overflow_s_0_5_10_16_s2.d - create mode 100644 ld/testsuite/ld-loongarch-elf/overflow_s_10_12.d - create mode 100644 ld/testsuite/ld-loongarch-elf/overflow_s_10_16.d - create mode 100644 ld/testsuite/ld-loongarch-elf/overflow_s_10_16_s2.d - create mode 100644 ld/testsuite/ld-loongarch-elf/overflow_s_10_5.d - create mode 100644 ld/testsuite/ld-loongarch-elf/overflow_s_5_20.d - create mode 100644 ld/testsuite/ld-loongarch-elf/overflow_u.d - create mode 100644 ld/testsuite/ld-loongarch-elf/overflow_u_10_12.d - create mode 100644 ld/testsuite/ld-loongarch-elf/underflow_b16.d - create mode 100644 ld/testsuite/ld-loongarch-elf/underflow_b21.d - create mode 100644 ld/testsuite/ld-loongarch-elf/underflow_b26.d - create mode 100644 ld/testsuite/ld-loongarch-elf/underflow_pcrel20.d - create mode 100644 ld/testsuite/ld-loongarch-elf/underflow_s_0_10_10_16_s2.d - create mode 100644 ld/testsuite/ld-loongarch-elf/underflow_s_0_5_10_16_s2.d - create mode 100644 ld/testsuite/ld-loongarch-elf/underflow_s_10_12.d - create mode 100644 ld/testsuite/ld-loongarch-elf/underflow_s_10_16.d - create mode 100644 ld/testsuite/ld-loongarch-elf/underflow_s_10_16_s2.d - create mode 100644 ld/testsuite/ld-loongarch-elf/underflow_s_10_5.d - create mode 100644 ld/testsuite/ld-loongarch-elf/underflow_s_5_20.d - -diff --git a/bfd/elfxx-loongarch.c b/bfd/elfxx-loongarch.c -index 127f3548..ee1323ea 100644 ---- a/bfd/elfxx-loongarch.c -+++ b/bfd/elfxx-loongarch.c -@@ -55,6 +55,8 @@ static bool - reloc_bits (bfd *abfd, reloc_howto_type *howto, bfd_vma *val); - static bool - reloc_sign_bits (bfd *abfd, reloc_howto_type *howto, bfd_vma *fix_val); -+static bool -+reloc_unsign_bits (bfd *abfd, reloc_howto_type *howto, bfd_vma *fix_val); - - static bfd_reloc_status_type - loongarch_elf_add_sub_reloc (bfd *, arelent *, asymbol *, void *, -@@ -415,7 +417,7 @@ static loongarch_reloc_howto_type loongarch_howto_table[] = - 0x7c00, /* dst_mask */ - false, /* pcrel_offset */ - BFD_RELOC_LARCH_SOP_POP_32_S_10_5, /* bfd_reloc_code_real_type */ -- reloc_bits, /* adjust_reloc_bits */ -+ reloc_sign_bits, /* adjust_reloc_bits */ - NULL), /* larch_reloc_type_name */ - - LOONGARCH_HOWTO (R_LARCH_SOP_POP_32_U_10_12, /* type (39). */ -@@ -432,7 +434,7 @@ static loongarch_reloc_howto_type loongarch_howto_table[] = - 0x3ffc00, /* dst_mask */ - false, /* pcrel_offset */ - BFD_RELOC_LARCH_SOP_POP_32_U_10_12, /* bfd_reloc_code_real_type */ -- reloc_bits, /* adjust_reloc_bits */ -+ reloc_unsign_bits, /* adjust_reloc_bits */ - NULL), /* larch_reloc_type_name */ - - LOONGARCH_HOWTO (R_LARCH_SOP_POP_32_S_10_12, /* type (40). */ -@@ -449,7 +451,7 @@ static loongarch_reloc_howto_type loongarch_howto_table[] = - 0x3ffc00, /* dst_mask */ - false, /* pcrel_offset */ - BFD_RELOC_LARCH_SOP_POP_32_S_10_12, /* bfd_reloc_code_real_type */ -- reloc_bits, /* adjust_reloc_bits */ -+ reloc_sign_bits, /* adjust_reloc_bits */ - NULL), /* larch_reloc_type_name */ - - LOONGARCH_HOWTO (R_LARCH_SOP_POP_32_S_10_16, /* type (41). */ -@@ -466,7 +468,7 @@ static loongarch_reloc_howto_type loongarch_howto_table[] = - 0x3fffc00, /* dst_mask */ - false, /* pcrel_offset */ - BFD_RELOC_LARCH_SOP_POP_32_S_10_16, /* bfd_reloc_code_real_type */ -- reloc_bits, /* adjust_reloc_bits */ -+ reloc_sign_bits, /* adjust_reloc_bits */ - NULL), /* larch_reloc_type_name */ - - LOONGARCH_HOWTO (R_LARCH_SOP_POP_32_S_10_16_S2, /* type (42). */ -@@ -500,7 +502,7 @@ static loongarch_reloc_howto_type loongarch_howto_table[] = - 0x1ffffe0, /* dst_mask */ - false, /* pcrel_offset */ - BFD_RELOC_LARCH_SOP_POP_32_S_5_20, /* bfd_reloc_code_real_type */ -- reloc_bits, /* adjust_reloc_bits */ -+ reloc_sign_bits, /* adjust_reloc_bits */ - NULL), /* larch_reloc_type_name */ - - LOONGARCH_HOWTO (R_LARCH_SOP_POP_32_S_0_5_10_16_S2, -@@ -554,7 +556,7 @@ static loongarch_reloc_howto_type loongarch_howto_table[] = - 0x00000000ffffffff, /* dst_mask */ - false, /* pcrel_offset */ - BFD_RELOC_LARCH_SOP_POP_32_U, /* bfd_reloc_code_real_type */ -- reloc_bits, /* adjust_reloc_bits */ -+ reloc_unsign_bits, /* adjust_reloc_bits */ - NULL), /* larch_reloc_type_name */ - - /* 8-bit in-place addition, for local label subtraction. */ -@@ -1991,9 +1993,11 @@ reloc_bits (bfd *abfd ATTRIBUTE_UNUSED, - } - - static bool --reloc_sign_bits (bfd *abfd, reloc_howto_type *howto, bfd_vma *fix_val) -+reloc_bits_sanity (bfd *abfd, reloc_howto_type *howto, bfd_vma *fix_val, -+ unsigned int sign) - { -- if (howto->complain_on_overflow != complain_overflow_signed) -+ if ((sign && howto->complain_on_overflow != complain_overflow_signed) -+ || (!sign && howto->complain_on_overflow != complain_overflow_unsigned)) - return false; - - bfd_signed_vma val = (bfd_signed_vma)(*fix_val); -@@ -2014,7 +2018,7 @@ reloc_sign_bits (bfd *abfd, reloc_howto_type *howto, bfd_vma *fix_val) - } - - bfd_signed_vma mask = ((bfd_signed_vma)0x1 << (howto->bitsize -- + howto->rightshift - 1)) - 1; -+ + howto->rightshift - sign)) - 1; - - /* Positive number: high part is all 0; - Negative number: if high part is not all 0, high part must be all 1. -@@ -2064,6 +2068,18 @@ reloc_sign_bits (bfd *abfd, reloc_howto_type *howto, bfd_vma *fix_val) - return true; - } - -+static bool -+reloc_sign_bits (bfd *abfd, reloc_howto_type *howto, bfd_vma *fix_val) -+{ -+ return reloc_bits_sanity (abfd, howto, fix_val, 1); -+} -+ -+static bool -+reloc_unsign_bits (bfd *abfd, reloc_howto_type *howto, bfd_vma *fix_val) -+{ -+ return reloc_bits_sanity (abfd, howto, fix_val, 0); -+} -+ - bool - loongarch_adjust_reloc_bitsfield (bfd *abfd, reloc_howto_type *howto, - bfd_vma *fix_val) -diff --git a/ld/testsuite/ld-loongarch-elf/abi1_max_imm.dd b/ld/testsuite/ld-loongarch-elf/abi1_max_imm.dd -new file mode 100644 -index 00000000..c8527140 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/abi1_max_imm.dd -@@ -0,0 +1,18 @@ -+#... -+.*00003c00.* -+.*00004000.* -+.*001ffc00.* -+.*00200000.* -+.*01fffc00.* -+.*02000000.* -+.*01fffc00.* -+.*02000000.* -+.*03fffc0f.* -+.*00000010.* -+.*03fffdff.* -+.*00000200.* -+.*00ffffe0.* -+.*01000000.* -+.*003ffc00.* -+.*ffffffff.* -+#pass -diff --git a/ld/testsuite/ld-loongarch-elf/abi1_max_imm.s b/ld/testsuite/ld-loongarch-elf/abi1_max_imm.s -new file mode 100644 -index 00000000..02507f19 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/abi1_max_imm.s -@@ -0,0 +1,39 @@ -+.macro sign_check reloc_name reloc_bits -+ .reloc off, R_LARCH_SOP_PUSH_ABSOLUTE, (1 << (\reloc_bits - 1)) - 1 -+ .reloc off, \reloc_name -+ .word 0 -+ .set off, off + 4 -+ .reloc off, R_LARCH_SOP_PUSH_ABSOLUTE, -(1 << (\reloc_bits - 1)) -+ .reloc off, \reloc_name -+ .word 0 -+ .set off, off + 4 -+.endm -+ -+.macro sign_check_s2 reloc_name reloc_bits -+ .reloc off, R_LARCH_SOP_PUSH_ABSOLUTE, ((1 << (\reloc_bits - 1)) - 1) << 2 -+ .reloc off, \reloc_name -+ .word 0 -+ .set off, off + 4 -+ .reloc off, R_LARCH_SOP_PUSH_ABSOLUTE, (-(1 << (\reloc_bits - 1))) << 2 -+ .reloc off, \reloc_name -+ .word 0 -+ .set off, off + 4 -+.endm -+ -+.macro unsign_check reloc_name reloc_bits -+ .reloc off, R_LARCH_SOP_PUSH_ABSOLUTE, (1 << \reloc_bits) - 1 -+ .reloc off, \reloc_name -+ .word 0 -+ .set off, off + 4 -+.endm -+ -+.set off, 0 -+sign_check R_LARCH_SOP_POP_32_S_10_5 5 -+sign_check R_LARCH_SOP_POP_32_S_10_12 12 -+sign_check R_LARCH_SOP_POP_32_S_10_16 16 -+sign_check_s2 R_LARCH_SOP_POP_32_S_10_16_S2 16 -+sign_check_s2 R_LARCH_SOP_POP_32_S_0_5_10_16_S2 21 -+sign_check_s2 R_LARCH_SOP_POP_32_S_0_10_10_16_S2 26 -+sign_check R_LARCH_SOP_POP_32_S_5_20 20 -+unsign_check R_LARCH_SOP_POP_32_U_10_12 12 -+unsign_check R_LARCH_SOP_POP_32_U 32 -diff --git a/ld/testsuite/ld-loongarch-elf/abi1_sops.s b/ld/testsuite/ld-loongarch-elf/abi1_sops.s -new file mode 100644 -index 00000000..34f2d592 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/abi1_sops.s -@@ -0,0 +1,43 @@ -+.macro sign_check reloc_sym reloc_name reloc_bits -+ .ifdef \reloc_sym -+ .ifdef overflow -+ .reloc 0, R_LARCH_SOP_PUSH_ABSOLUTE, 1 << (\reloc_bits - 1) -+ .reloc 0, \reloc_name -+ .else -+ .reloc 0, R_LARCH_SOP_PUSH_ABSOLUTE, -(1 << (\reloc_bits - 1)) - 1 -+ .reloc 0, \reloc_name -+ .endif -+ .word 0 -+ .endif -+.endm -+ -+.macro sign_check_s2 reloc_sym reloc_name reloc_bits -+ .ifdef \reloc_sym -+ .ifdef overflow -+ .reloc 0, R_LARCH_SOP_PUSH_ABSOLUTE, (1 << (\reloc_bits - 1)) << 2 -+ .reloc 0, \reloc_name -+ .else -+ .reloc 0, R_LARCH_SOP_PUSH_ABSOLUTE, (-(1 << (\reloc_bits - 1)) - 1) << 2 -+ .reloc 0, \reloc_name -+ .endif -+ .word 0 -+ .endif -+.endm -+ -+.macro unsign_check reloc_sym reloc_name reloc_bits -+ .ifdef \reloc_sym -+ .reloc 0, R_LARCH_SOP_PUSH_ABSOLUTE, 1 << \reloc_bits -+ .reloc 0, \reloc_name -+ .word 0 -+ .endif -+.endm -+ -+sign_check s_10_5 R_LARCH_SOP_POP_32_S_10_5 5 -+sign_check s_10_12 R_LARCH_SOP_POP_32_S_10_12 12 -+sign_check s_10_16 R_LARCH_SOP_POP_32_S_10_16 16 -+sign_check_s2 s_10_16_s2 R_LARCH_SOP_POP_32_S_10_16_S2 16 -+sign_check_s2 s_0_5_10_16_s2 R_LARCH_SOP_POP_32_S_0_5_10_16_S2 21 -+sign_check_s2 s_0_10_10_16_s2 R_LARCH_SOP_POP_32_S_0_10_10_16_S2 26 -+sign_check s_5_20 R_LARCH_SOP_POP_32_S_5_20 20 -+unsign_check u_10_12 R_LARCH_SOP_POP_32_U_10_12 12 -+unsign_check u R_LARCH_SOP_POP_32_U 32 -diff --git a/ld/testsuite/ld-loongarch-elf/abi2_max_imm.s b/ld/testsuite/ld-loongarch-elf/abi2_max_imm.s -new file mode 100644 -index 00000000..f1bc3868 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/abi2_max_imm.s -@@ -0,0 +1,24 @@ -+ .text -+.ifdef b16 -+ beq $a0, $a1, low -+ beq $a0, $a1, high -+.endif -+.ifdef b21 -+ beqz $a0, low -+ beqz $a0, high -+.endif -+.ifdef b26 -+ b low -+ b high -+.endif -+.ifdef pcrel20 -+ .reloc 0, R_LARCH_PCREL20_S2, low -+ pcaddi $a0, 0 -+ .reloc 4, R_LARCH_PCREL20_S2, high -+ pcaddi $a0, 0 -+.endif -+ -+ .section ".low" -+low: nop -+ .section ".high" -+high: nop -diff --git a/ld/testsuite/ld-loongarch-elf/abi2_overflows.s b/ld/testsuite/ld-loongarch-elf/abi2_overflows.s -new file mode 100644 -index 00000000..1c25bd8c ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/abi2_overflows.s -@@ -0,0 +1,24 @@ -+ .text -+ -+.set idx, 0 -+.ifdef underflow -+ nop -+ .set idx, 4 -+.endif -+ -+.ifdef b16 -+ beq $a0, $a1, local_sym -+.endif -+.ifdef b21 -+ beqz $a0, local_sym -+.endif -+.ifdef b26 -+ b local_sym -+.endif -+.ifdef pcrel20 -+ .reloc idx, R_LARCH_PCREL20_S2, local_sym -+ pcaddi $a0, 0 -+.endif -+ -+ .section ".local_sym" -+local_sym: nop -diff --git a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -index 46b53536..7fc43d41 100644 ---- a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -+++ b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -@@ -35,6 +35,22 @@ if [istarget "loongarch64-*-*"] { - run_dump_test "anno-sym" - run_dump_test "pcala64" - run_dump_test "tls-le" -+ run_dump_test "overflow_s_10_5" -+ run_dump_test "overflow_s_10_12" -+ run_dump_test "overflow_s_10_16" -+ run_dump_test "overflow_s_10_16_s2" -+ run_dump_test "overflow_s_0_5_10_16_s2" -+ run_dump_test "overflow_s_0_10_10_16_s2" -+ run_dump_test "overflow_s_5_20" -+ run_dump_test "overflow_u_10_12" -+ run_dump_test "overflow_u" -+ run_dump_test "underflow_s_10_5" -+ run_dump_test "underflow_s_10_12" -+ run_dump_test "underflow_s_10_16" -+ run_dump_test "underflow_s_10_16_s2" -+ run_dump_test "underflow_s_0_5_10_16_s2" -+ run_dump_test "underflow_s_0_10_10_16_s2" -+ run_dump_test "underflow_s_5_20" - } - - if [istarget "loongarch32-*-*"] { -@@ -95,6 +111,16 @@ if [istarget "loongarch64-*-*"] { - {} \ - "medium-call" \ - ] \ -+ [list \ -+ "abi1_max_imm" \ -+ "-e 0x0" "" \ -+ "" \ -+ {abi1_max_imm.s} \ -+ [list \ -+ [list objdump -D abi1_max_imm.dd] \ -+ ] \ -+ "abi1_max_imm" \ -+ ] \ - ] - } - -@@ -108,3 +134,16 @@ if [istarget "loongarch64-*-*"] { - run_dump_test "desc-relax" - } - } -+ -+run_dump_test "max_imm_b16" -+run_dump_test "max_imm_b21" -+run_dump_test "max_imm_b26" -+run_dump_test "max_imm_pcrel20" -+run_dump_test "overflow_b16" -+run_dump_test "overflow_b21" -+run_dump_test "overflow_b26" -+run_dump_test "overflow_pcrel20" -+run_dump_test "underflow_b16" -+run_dump_test "underflow_b21" -+run_dump_test "underflow_b26" -+run_dump_test "underflow_pcrel20" -diff --git a/ld/testsuite/ld-loongarch-elf/max_imm_b16.d b/ld/testsuite/ld-loongarch-elf/max_imm_b16.d -new file mode 100644 -index 00000000..2c3f6cdb ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/max_imm_b16.d -@@ -0,0 +1,9 @@ -+#source: abi2_max_imm.s -+#as: --defsym b16=1 -+#ld: -e 0 -Ttext 0x20000000 --section-start=.low=0x1ffe0000 --section-start=.high=0x20020000 -+#objdump: -s -+ -+#... -+Contents of section .text: -+ 20000000 8500005a 85fcff59.* -+#pass -diff --git a/ld/testsuite/ld-loongarch-elf/max_imm_b21.d b/ld/testsuite/ld-loongarch-elf/max_imm_b21.d -new file mode 100644 -index 00000000..5861fb46 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/max_imm_b21.d -@@ -0,0 +1,9 @@ -+#source: abi2_max_imm.s -+#as: --defsym b21=1 -+#ld: -e 0 -Ttext 0x20000000 --section-start=.low=0x1fc00000 --section-start=.high=0x20400000 -+#objdump: -s -+ -+#... -+Contents of section .text: -+ 20000000 90000040 8ffcff43.* -+#pass -diff --git a/ld/testsuite/ld-loongarch-elf/max_imm_b26.d b/ld/testsuite/ld-loongarch-elf/max_imm_b26.d -new file mode 100644 -index 00000000..f475ccb3 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/max_imm_b26.d -@@ -0,0 +1,9 @@ -+#source: abi2_max_imm.s -+#as: --defsym b26=1 -+#ld: -e 0 -Ttext 0x20000000 --section-start=.low=0x18000000 --section-start=.high=0x28000000 -+#objdump: -s -+ -+#... -+Contents of section .text: -+ 20000000 00020050 fffdff53.* -+#pass -diff --git a/ld/testsuite/ld-loongarch-elf/max_imm_pcrel20.d b/ld/testsuite/ld-loongarch-elf/max_imm_pcrel20.d -new file mode 100644 -index 00000000..4bd9d2f1 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/max_imm_pcrel20.d -@@ -0,0 +1,9 @@ -+#source: abi2_max_imm.s -+#as: --defsym pcrel20=1 -+#ld: -e 0 -Ttext 0x20000000 --section-start=.low=0x1fe00000 --section-start=.high=0x20200000 -+#objdump: -s -+ -+#... -+Contents of section .text: -+ 20000000 04000019 e4ffff18.* -+#pass -diff --git a/ld/testsuite/ld-loongarch-elf/overflow_b16.d b/ld/testsuite/ld-loongarch-elf/overflow_b16.d -new file mode 100644 -index 00000000..26cad414 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/overflow_b16.d -@@ -0,0 +1,4 @@ -+#source: abi2_overflows.s -+#as: --defsym overflow=1 --defsym b16=1 -+#ld: -e 0 --section-start=.local_sym=0x20020000 -Ttext 0x20000000 -+#error: .*relocation truncated to fit: R_LARCH_B16 against `local_sym' -diff --git a/ld/testsuite/ld-loongarch-elf/overflow_b21.d b/ld/testsuite/ld-loongarch-elf/overflow_b21.d -new file mode 100644 -index 00000000..826856f2 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/overflow_b21.d -@@ -0,0 +1,4 @@ -+#source: abi2_overflows.s -+#as: --defsym overflow=1 --defsym b21=1 -+#ld: -e 0 --section-start=.local_sym=0x20400000 -Ttext 0x20000000 -+#error: .*relocation truncated to fit: R_LARCH_B21 against `local_sym' -diff --git a/ld/testsuite/ld-loongarch-elf/overflow_b26.d b/ld/testsuite/ld-loongarch-elf/overflow_b26.d -new file mode 100644 -index 00000000..474e5751 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/overflow_b26.d -@@ -0,0 +1,4 @@ -+#source: abi2_overflows.s -+#as: --defsym overflow=1 --defsym b26=1 -+#ld: -e 0 --section-start=.local_sym=0x28000000 -Ttext 0x20000000 -+#error: .*relocation truncated to fit: R_LARCH_B26 against `local_sym' -diff --git a/ld/testsuite/ld-loongarch-elf/overflow_pcrel20.d b/ld/testsuite/ld-loongarch-elf/overflow_pcrel20.d -new file mode 100644 -index 00000000..420be729 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/overflow_pcrel20.d -@@ -0,0 +1,4 @@ -+#source: abi2_overflows.s -+#as: --defsym overflow=1 --defsym pcrel20=1 -+#ld: -e 0 --section-start=.local_sym=0x20200000 -Ttext 0x20000000 -+#error: .*relocation truncated to fit: R_LARCH_PCREL20_S2 against `local_sym' -diff --git a/ld/testsuite/ld-loongarch-elf/overflow_s_0_10_10_16_s2.d b/ld/testsuite/ld-loongarch-elf/overflow_s_0_10_10_16_s2.d -new file mode 100644 -index 00000000..621054b1 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/overflow_s_0_10_10_16_s2.d -@@ -0,0 +1,4 @@ -+#source: abi1_sops.s -+#as: --defsym overflow=1 --defsym s_0_10_10_16_s2=1 -+#ld: -e 0 -+#error: .*relocation truncated to fit: R_LARCH_SOP_POP_32_S_0_10_10_16_S2 against `' -\ No newline at end of file -diff --git a/ld/testsuite/ld-loongarch-elf/overflow_s_0_5_10_16_s2.d b/ld/testsuite/ld-loongarch-elf/overflow_s_0_5_10_16_s2.d -new file mode 100644 -index 00000000..348f5ae9 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/overflow_s_0_5_10_16_s2.d -@@ -0,0 +1,4 @@ -+#source: abi1_sops.s -+#as: --defsym overflow=1 --defsym s_0_5_10_16_s2=1 -+#ld: -e 0 -+#error: .*relocation truncated to fit: R_LARCH_SOP_POP_32_S_0_5_10_16_S2 against `' -\ No newline at end of file -diff --git a/ld/testsuite/ld-loongarch-elf/overflow_s_10_12.d b/ld/testsuite/ld-loongarch-elf/overflow_s_10_12.d -new file mode 100644 -index 00000000..dcadff7e ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/overflow_s_10_12.d -@@ -0,0 +1,4 @@ -+#source: abi1_sops.s -+#as: --defsym overflow=1 --defsym s_10_12=1 -+#ld: -e 0 -+#error: .*relocation truncated to fit: R_LARCH_SOP_POP_32_S_10_12 against `' -\ No newline at end of file -diff --git a/ld/testsuite/ld-loongarch-elf/overflow_s_10_16.d b/ld/testsuite/ld-loongarch-elf/overflow_s_10_16.d -new file mode 100644 -index 00000000..3677415a ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/overflow_s_10_16.d -@@ -0,0 +1,4 @@ -+#source: abi1_sops.s -+#as: --defsym overflow=1 --defsym s_10_16=1 -+#ld: -e 0 -+#error: .*relocation truncated to fit: R_LARCH_SOP_POP_32_S_10_16 against `' -\ No newline at end of file -diff --git a/ld/testsuite/ld-loongarch-elf/overflow_s_10_16_s2.d b/ld/testsuite/ld-loongarch-elf/overflow_s_10_16_s2.d -new file mode 100644 -index 00000000..24ffa811 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/overflow_s_10_16_s2.d -@@ -0,0 +1,4 @@ -+#source: abi1_sops.s -+#as: --defsym overflow=1 --defsym s_10_16_s2=1 -+#ld: -e 0 -+#error: .*relocation truncated to fit: R_LARCH_SOP_POP_32_S_10_16_S2 against `' -\ No newline at end of file -diff --git a/ld/testsuite/ld-loongarch-elf/overflow_s_10_5.d b/ld/testsuite/ld-loongarch-elf/overflow_s_10_5.d -new file mode 100644 -index 00000000..7881457d ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/overflow_s_10_5.d -@@ -0,0 +1,4 @@ -+#source: abi1_sops.s -+#as: --defsym overflow=1 --defsym s_10_5=1 -+#ld: -e 0 -+#error: .*relocation truncated to fit: R_LARCH_SOP_POP_32_S_10_5 against `' -\ No newline at end of file -diff --git a/ld/testsuite/ld-loongarch-elf/overflow_s_5_20.d b/ld/testsuite/ld-loongarch-elf/overflow_s_5_20.d -new file mode 100644 -index 00000000..5f06eed8 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/overflow_s_5_20.d -@@ -0,0 +1,4 @@ -+#source: abi1_sops.s -+#as: --defsym overflow=1 --defsym s_5_20=1 -+#ld: -e 0 -+#error: .*relocation truncated to fit: R_LARCH_SOP_POP_32_S_5_20 against `' -\ No newline at end of file -diff --git a/ld/testsuite/ld-loongarch-elf/overflow_u.d b/ld/testsuite/ld-loongarch-elf/overflow_u.d -new file mode 100644 -index 00000000..96906f64 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/overflow_u.d -@@ -0,0 +1,4 @@ -+#source: abi1_sops.s -+#as: --defsym overflow=1 --defsym u=1 -+#ld: -e 0 -+#error: .*relocation truncated to fit: R_LARCH_SOP_POP_32_U against `' -\ No newline at end of file -diff --git a/ld/testsuite/ld-loongarch-elf/overflow_u_10_12.d b/ld/testsuite/ld-loongarch-elf/overflow_u_10_12.d -new file mode 100644 -index 00000000..9d8e0905 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/overflow_u_10_12.d -@@ -0,0 +1,4 @@ -+#source: abi1_sops.s -+#as: --defsym overflow=1 --defsym u_10_12=1 -+#ld: -e 0 -+#error: .*relocation truncated to fit: R_LARCH_SOP_POP_32_U_10_12 against `' -\ No newline at end of file -diff --git a/ld/testsuite/ld-loongarch-elf/underflow_b16.d b/ld/testsuite/ld-loongarch-elf/underflow_b16.d -new file mode 100644 -index 00000000..e2e21949 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/underflow_b16.d -@@ -0,0 +1,4 @@ -+#source: abi2_overflows.s -+#as: --defsym underflow=1 --defsym b16=1 -+#ld: -e 0 --section-start=.local_sym=0x1ffe0000 -Ttext 0x20000000 -+#error: .*relocation truncated to fit: R_LARCH_B16 against `local_sym' -diff --git a/ld/testsuite/ld-loongarch-elf/underflow_b21.d b/ld/testsuite/ld-loongarch-elf/underflow_b21.d -new file mode 100644 -index 00000000..6f56526b ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/underflow_b21.d -@@ -0,0 +1,4 @@ -+#source: abi2_overflows.s -+#as: --defsym underflow=1 --defsym b21=1 -+#ld: -e 0 --section-start=.local_sym=0x1fc00000 -Ttext 0x20000000 -+#error: .*relocation truncated to fit: R_LARCH_B21 against `local_sym' -diff --git a/ld/testsuite/ld-loongarch-elf/underflow_b26.d b/ld/testsuite/ld-loongarch-elf/underflow_b26.d -new file mode 100644 -index 00000000..5756cc14 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/underflow_b26.d -@@ -0,0 +1,4 @@ -+#source: abi2_overflows.s -+#as: --defsym underflow=1 --defsym b26=1 -+#ld: -e 0 --section-start=.local_sym=0x18000000 -Ttext 0x20000000 -+#error: .*relocation truncated to fit: R_LARCH_B26 against `local_sym' -diff --git a/ld/testsuite/ld-loongarch-elf/underflow_pcrel20.d b/ld/testsuite/ld-loongarch-elf/underflow_pcrel20.d -new file mode 100644 -index 00000000..e65c60ad ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/underflow_pcrel20.d -@@ -0,0 +1,4 @@ -+#source: abi2_overflows.s -+#as: --defsym underflow=1 --defsym pcrel20=1 -+#ld: -e 0 --section-start=.local_sym=0x1fe00000 -Ttext 0x20000000 -+#error: .*relocation truncated to fit: R_LARCH_PCREL20_S2 against `local_sym' -diff --git a/ld/testsuite/ld-loongarch-elf/underflow_s_0_10_10_16_s2.d b/ld/testsuite/ld-loongarch-elf/underflow_s_0_10_10_16_s2.d -new file mode 100644 -index 00000000..3e7715a2 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/underflow_s_0_10_10_16_s2.d -@@ -0,0 +1,4 @@ -+#source: abi1_sops.s -+#as: --defsym underflow=1 --defsym s_0_10_10_16_s2=1 -+#ld: -e 0 -+#error: .*relocation truncated to fit: R_LARCH_SOP_POP_32_S_0_10_10_16_S2 against `' -\ No newline at end of file -diff --git a/ld/testsuite/ld-loongarch-elf/underflow_s_0_5_10_16_s2.d b/ld/testsuite/ld-loongarch-elf/underflow_s_0_5_10_16_s2.d -new file mode 100644 -index 00000000..14be5a9c ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/underflow_s_0_5_10_16_s2.d -@@ -0,0 +1,4 @@ -+#source: abi1_sops.s -+#as: --defsym underflow=1 --defsym s_0_5_10_16_s2=1 -+#ld: -e 0 -+#error: .*relocation truncated to fit: R_LARCH_SOP_POP_32_S_0_5_10_16_S2 against `' -\ No newline at end of file -diff --git a/ld/testsuite/ld-loongarch-elf/underflow_s_10_12.d b/ld/testsuite/ld-loongarch-elf/underflow_s_10_12.d -new file mode 100644 -index 00000000..ed9fe9b7 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/underflow_s_10_12.d -@@ -0,0 +1,4 @@ -+#source: abi1_sops.s -+#as: --defsym underflow=1 --defsym s_10_12=1 -+#ld: -e 0 -+#error: .*relocation truncated to fit: R_LARCH_SOP_POP_32_S_10_12 against `' -\ No newline at end of file -diff --git a/ld/testsuite/ld-loongarch-elf/underflow_s_10_16.d b/ld/testsuite/ld-loongarch-elf/underflow_s_10_16.d -new file mode 100644 -index 00000000..03b851b5 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/underflow_s_10_16.d -@@ -0,0 +1,4 @@ -+#source: abi1_sops.s -+#as: --defsym underflow=1 --defsym s_10_16=1 -+#ld: -e 0 -+#error: .*relocation truncated to fit: R_LARCH_SOP_POP_32_S_10_16 against `' -\ No newline at end of file -diff --git a/ld/testsuite/ld-loongarch-elf/underflow_s_10_16_s2.d b/ld/testsuite/ld-loongarch-elf/underflow_s_10_16_s2.d -new file mode 100644 -index 00000000..c0e4ca03 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/underflow_s_10_16_s2.d -@@ -0,0 +1,4 @@ -+#source: abi1_sops.s -+#as: --defsym underflow=1 --defsym s_10_16_s2=1 -+#ld: -e 0 -+#error: .*relocation truncated to fit: R_LARCH_SOP_POP_32_S_10_16_S2 against `' -\ No newline at end of file -diff --git a/ld/testsuite/ld-loongarch-elf/underflow_s_10_5.d b/ld/testsuite/ld-loongarch-elf/underflow_s_10_5.d -new file mode 100644 -index 00000000..77d0eb04 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/underflow_s_10_5.d -@@ -0,0 +1,4 @@ -+#source: abi1_sops.s -+#as: --defsym underflow=1 --defsym s_10_5=1 -+#ld: -e 0 -+#error: .*relocation truncated to fit: R_LARCH_SOP_POP_32_S_10_5 against `' -\ No newline at end of file -diff --git a/ld/testsuite/ld-loongarch-elf/underflow_s_5_20.d b/ld/testsuite/ld-loongarch-elf/underflow_s_5_20.d -new file mode 100644 -index 00000000..c458bb81 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/underflow_s_5_20.d -@@ -0,0 +1,4 @@ -+#source: abi1_sops.s -+#as: --defsym underflow=1 --defsym s_5_20=1 -+#ld: -e 0 -+#error: .*relocation truncated to fit: R_LARCH_SOP_POP_32_S_5_20 against `' -\ No newline at end of file --- -2.33.0 - diff --git a/LoongArch-ld-Move-.got-.got.plt-before-.data-and-pro.patch b/LoongArch-ld-Move-.got-.got.plt-before-.data-and-pro.patch deleted file mode 100644 index 74e9111..0000000 --- a/LoongArch-ld-Move-.got-.got.plt-before-.data-and-pro.patch +++ /dev/null @@ -1,96 +0,0 @@ -From b3c4d41eedd38561194a8de8c530e318f621660c Mon Sep 17 00:00:00 2001 -From: mengqinggang -Date: Wed, 3 Apr 2024 10:20:27 +0800 -Subject: [PATCH 078/123] LoongArch: ld: Move .got .got.plt before .data and - protect .got with relro - -Move .got .got.plt before .data so .got can be protected with -zrelro. -And the first two entries of .got.plt (_dl_runtime_resolve and link map) -are placed within the relro region. ---- - bfd/elfnn-loongarch.c | 2 ++ - ld/emulparams/elf64loongarch-defs.sh | 5 ++++- - ld/testsuite/ld-loongarch-elf/data-got.d | 16 ++++++++++++++++ - ld/testsuite/ld-loongarch-elf/data-got.s | 6 ++++++ - .../ld-loongarch-elf/ld-loongarch-elf.exp | 1 + - 5 files changed, 29 insertions(+), 1 deletion(-) - create mode 100644 ld/testsuite/ld-loongarch-elf/data-got.d - create mode 100644 ld/testsuite/ld-loongarch-elf/data-got.s - -diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c -index 7f98dce1..36f1cfd5 100644 ---- a/bfd/elfnn-loongarch.c -+++ b/bfd/elfnn-loongarch.c -@@ -127,6 +127,8 @@ struct loongarch_elf_link_hash_table - - #define GOT_ENTRY_SIZE (LARCH_ELF_WORD_BYTES) - -+/* Reserve two entries of GOTPLT for ld.so, one is used for PLT -+ resolver _dl_runtime_resolve, the other is used for link map. */ - #define GOTPLT_HEADER_SIZE (GOT_ENTRY_SIZE * 2) - - #define elf_backend_want_got_plt 1 -diff --git a/ld/emulparams/elf64loongarch-defs.sh b/ld/emulparams/elf64loongarch-defs.sh -index c793f5d8..a8147bf7 100644 ---- a/ld/emulparams/elf64loongarch-defs.sh -+++ b/ld/emulparams/elf64loongarch-defs.sh -@@ -34,6 +34,9 @@ TEXT_START_ADDR=0x120000000 - MAXPAGESIZE="CONSTANT (MAXPAGESIZE)" - COMMONPAGESIZE="CONSTANT (COMMONPAGESIZE)" - --SEPARATE_GOTPLT=0 -+# Put .got before .data -+DATA_GOT=" " -+# First two entries for PLT resolver _dl_runtime_resolve and link map. -+SEPARATE_GOTPLT="SIZEOF (.got.plt) >= 16 ? 16 : 0" - INITIAL_READONLY_SECTIONS=".interp : { *(.interp) } ${CREATE_PIE-${INITIAL_READONLY_SECTIONS}}" - INITIAL_READONLY_SECTIONS="${RELOCATING+${CREATE_SHLIB-${INITIAL_READONLY_SECTIONS}}}" -diff --git a/ld/testsuite/ld-loongarch-elf/data-got.d b/ld/testsuite/ld-loongarch-elf/data-got.d -new file mode 100644 -index 00000000..a754478a ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/data-got.d -@@ -0,0 +1,16 @@ -+# line 11 test the first two entries of .got.plt in relro region -+# relro segment size is .dynamic size + .got size + 0x10 -+# line 13 test .got .got.plt before .got -+# line 15 test .got in relro segment -+#as: -+#ld: -shared -z relro --hash-style=both -+#readelf: -l --wide -+#skip: loongarch32-*-* -+ -+#... -+ GNU_RELRO 0x003c10 0x0000000000007c10 0x0000000000007c10 0x0003f0 0x0003f0 R 0x1 -+#... -+ 01 .dynamic .got .got.plt .data -+#... -+ 03 .dynamic .got -+#pass -diff --git a/ld/testsuite/ld-loongarch-elf/data-got.s b/ld/testsuite/ld-loongarch-elf/data-got.s -new file mode 100644 -index 00000000..364fcf64 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/data-got.s -@@ -0,0 +1,6 @@ -+.text -+b foo -+.section .got -+.space 0x2a8, 4 -+.data -+.zero 24 -diff --git a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -index 0121cad9..fc7b5bfe 100644 ---- a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -+++ b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -@@ -133,6 +133,7 @@ if [istarget "loongarch64-*-*"] { - run_dump_test "tlsdesc-dso" - run_dump_test "desc-norelax" - run_dump_test "desc-relax" -+ run_dump_test "data-got" - } - - if [check_pie_support] { --- -2.33.0 - diff --git a/LoongArch-ld-Report-an-error-when-seeing-an-unrecogn.patch b/LoongArch-ld-Report-an-error-when-seeing-an-unrecogn.patch deleted file mode 100644 index ac7dc81..0000000 --- a/LoongArch-ld-Report-an-error-when-seeing-an-unrecogn.patch +++ /dev/null @@ -1,40 +0,0 @@ -From ec2d7d7fe1c2bc448ff77a192fc71be1bee87593 Mon Sep 17 00:00:00 2001 -From: Lulu Cai -Date: Thu, 21 Mar 2024 15:16:05 +0800 -Subject: [PATCH 079/123] LoongArch: ld:Report an error when seeing an - unrecognized relocation - -If we generate an object file using an assembler with the new -relocations added, and then linking those files with an older -linker, the link will still complete and the linked file will -be generated. -In this case we should report an error instead of continuing -the linking process. ---- - bfd/elfnn-loongarch.c | 9 +++++++-- - 1 file changed, 7 insertions(+), 2 deletions(-) - -diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c -index 36f1cfd5..70ef28f3 100644 ---- a/bfd/elfnn-loongarch.c -+++ b/bfd/elfnn-loongarch.c -@@ -2610,9 +2610,14 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, - bfd_vma relocation, off, ie_off, desc_off; - int i, j; - -+ /* When an unrecognized relocation is encountered, which usually -+ occurs when using a newer assembler but an older linker, an error -+ should be reported instead of continuing to the next relocation. */ - howto = loongarch_elf_rtype_to_howto (input_bfd, r_type); -- if (howto == NULL || r_type == R_LARCH_GNU_VTINHERIT -- || r_type == R_LARCH_GNU_VTENTRY) -+ if (howto == NULL) -+ return _bfd_unrecognized_reloc (input_bfd, input_section, r_type); -+ -+ if (r_type == R_LARCH_GNU_VTINHERIT || r_type == R_LARCH_GNU_VTENTRY) - continue; - - /* This is a final link. */ --- -2.33.0 - diff --git a/LoongArch-ld-Simplify-inserting-IRELATIVE-relocation.patch b/LoongArch-ld-Simplify-inserting-IRELATIVE-relocation.patch deleted file mode 100644 index 43c2a73..0000000 --- a/LoongArch-ld-Simplify-inserting-IRELATIVE-relocation.patch +++ /dev/null @@ -1,184 +0,0 @@ -From 2c70ecb7fd4c90282d75ef7e30f2afdee94dc02e Mon Sep 17 00:00:00 2001 -From: mengqinggang -Date: Tue, 11 Jul 2023 11:21:18 +0800 -Subject: [PATCH 002/123] LoongArch: ld: Simplify inserting IRELATIVE - relocations to .rela.dyn - -In LoongArch, the R_LARCH_IRELATIVE relocations for local ifunc symbols are -in .rela.dyn. Before, this is done by loongarch_elf_finish_dynamic_sections. -But this function is called after elf_link_sort_relocs, it need to find a -null slot to insert IRELATIVE relocation. - -Now, it is processed by elf_loongarch_output_arch_local_syms before -elf_link_sort_relocs, just need to call loongarch_elf_append_rela to -insert IRELATIVE relocation. - -bfd/ChangeLog: - - * elfnn-loongarch.c (elfNN_allocate_local_ifunc_dynrelocs): Return - type change to int. - (loongarch_elf_size_dynamic_sections): Delete (void *). - (loongarch_elf_finish_dynamic_symbol): Use loongarch_elf_append_rela - insert IRELATIVE relocation to .rela.dyn. - (elfNN_loongarch_finish_local_dynamic_symbol): Return type change to - int. - (loongarch_elf_finish_dynamic_sections): Delete process of local - ifunc symbols. - (elf_backend_output_arch_local_syms): New. - -ld/ChangeLog: - - * testsuite/ld-loongarch-elf/local-ifunc-reloc.d: Regenerated. ---- - bfd/elfnn-loongarch.c | 67 +++++++++---------- - .../ld-loongarch-elf/local-ifunc-reloc.d | 2 +- - 2 files changed, 34 insertions(+), 35 deletions(-) - -diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c -index f7dc7279..2fe4924b 100644 ---- a/bfd/elfnn-loongarch.c -+++ b/bfd/elfnn-loongarch.c -@@ -1538,7 +1538,7 @@ elfNN_allocate_ifunc_dynrelocs (struct elf_link_hash_entry *h, void *inf) - /* Allocate space in .plt, .got and associated reloc sections for - ifunc dynamic relocs. */ - --static bool -+static int - elfNN_allocate_local_ifunc_dynrelocs (void **slot, void *inf) - { - struct elf_link_hash_entry *h = (struct elf_link_hash_entry *) *slot; -@@ -1700,7 +1700,7 @@ loongarch_elf_size_dynamic_sections (bfd *output_bfd, - - /* Allocate .plt and .got entries, and space for local ifunc symbols. */ - htab_traverse (htab->loc_hash_table, -- (void *) elfNN_allocate_local_ifunc_dynrelocs, info); -+ elfNN_allocate_local_ifunc_dynrelocs, info); - - /* Don't allocate .got.plt section if there are no PLT. */ - if (htab->elf.sgotplt && htab->elf.sgotplt->size == GOTPLT_HEADER_SIZE -@@ -4049,12 +4049,6 @@ loongarch_elf_finish_dynamic_symbol (bfd *output_bfd, - { - struct loongarch_elf_link_hash_table *htab = loongarch_elf_hash_table (info); - const struct elf_backend_data *bed = get_elf_backend_data (output_bfd); -- asection *rela_dyn = bfd_get_section_by_name (output_bfd, ".rela.dyn"); -- struct bfd_link_order *lo = NULL; -- Elf_Internal_Rela *slot = NULL, *last_slot = NULL; -- -- if (rela_dyn) -- lo = rela_dyn->map_head.link_order; - - if (h->plt.offset != MINUS_ONE) - { -@@ -4064,7 +4058,6 @@ loongarch_elf_finish_dynamic_symbol (bfd *output_bfd, - uint32_t plt_entry[PLT_ENTRY_INSNS]; - bfd_byte *loc; - Elf_Internal_Rela rela; -- asection *rela_sec = NULL; - - if (htab->elf.splt) - { -@@ -4122,26 +4115,7 @@ loongarch_elf_finish_dynamic_symbol (bfd *output_bfd, - + h->root.u.def.section->output_section->vma - + h->root.u.def.section->output_offset); - -- /* Find the space after dyn sort. */ -- while (slot == last_slot || slot->r_offset != 0) -- { -- if (slot != last_slot) -- { -- slot++; -- continue; -- } -- -- BFD_ASSERT (lo != NULL); -- rela_sec = lo->u.indirect.section; -- lo = lo->next; -- -- slot = (Elf_Internal_Rela *)rela_sec->contents; -- last_slot = (Elf_Internal_Rela *)(rela_sec->contents + -- rela_sec->size); -- } -- -- bed->s->swap_reloca_out (output_bfd, &rela, (bfd_byte *)slot); -- rela_sec->reloc_count++; -+ loongarch_elf_append_rela (output_bfd, relplt, &rela); - } - else - { -@@ -4308,7 +4282,7 @@ loongarch_finish_dyn (bfd *output_bfd, struct bfd_link_info *info, bfd *dynobj, - /* Finish up local dynamic symbol handling. We set the contents of - various dynamic sections here. */ - --static bool -+static int - elfNN_loongarch_finish_local_dynamic_symbol (void **slot, void *inf) - { - struct elf_link_hash_entry *h = (struct elf_link_hash_entry *) *slot; -@@ -4317,6 +4291,33 @@ elfNN_loongarch_finish_local_dynamic_symbol (void **slot, void *inf) - return loongarch_elf_finish_dynamic_symbol (info->output_bfd, info, h, NULL); - } - -+/* Value of struct elf_backend_data->elf_backend_output_arch_local_syms, -+ this function is called before elf_link_sort_relocs. -+ So relocation R_LARCH_IRELATIVE for local ifunc can be append to -+ .rela.dyn (.rela.got) by loongarch_elf_append_rela. */ -+ -+static bool -+elf_loongarch_output_arch_local_syms -+ (bfd *output_bfd ATTRIBUTE_UNUSED, -+ struct bfd_link_info *info, -+ void *flaginfo ATTRIBUTE_UNUSED, -+ int (*func) (void *, const char *, -+ Elf_Internal_Sym *, -+ asection *, -+ struct elf_link_hash_entry *) ATTRIBUTE_UNUSED) -+{ -+ struct loongarch_elf_link_hash_table *htab = loongarch_elf_hash_table (info); -+ if (htab == NULL) -+ return false; -+ -+ /* Fill PLT and GOT entries for local STT_GNU_IFUNC symbols. */ -+ htab_traverse (htab->loc_hash_table, -+ elfNN_loongarch_finish_local_dynamic_symbol, -+ info); -+ -+ return true; -+} -+ - static bool - loongarch_elf_finish_dynamic_sections (bfd *output_bfd, - struct bfd_link_info *info) -@@ -4395,10 +4396,6 @@ loongarch_elf_finish_dynamic_sections (bfd *output_bfd, - elf_section_data (output_section)->this_hdr.sh_entsize = GOT_ENTRY_SIZE; - } - -- /* Fill PLT and GOT entries for local STT_GNU_IFUNC symbols. */ -- htab_traverse (htab->loc_hash_table, -- (void *) elfNN_loongarch_finish_local_dynamic_symbol, info); -- - return true; - } - -@@ -4663,6 +4660,8 @@ elf_loongarch64_hash_symbol (struct elf_link_hash_entry *h) - #define elf_backend_size_dynamic_sections loongarch_elf_size_dynamic_sections - #define elf_backend_relocate_section loongarch_elf_relocate_section - #define elf_backend_finish_dynamic_symbol loongarch_elf_finish_dynamic_symbol -+#define elf_backend_output_arch_local_syms \ -+ elf_loongarch_output_arch_local_syms - #define elf_backend_finish_dynamic_sections \ - loongarch_elf_finish_dynamic_sections - #define elf_backend_object_p loongarch_elf_object_p -diff --git a/ld/testsuite/ld-loongarch-elf/local-ifunc-reloc.d b/ld/testsuite/ld-loongarch-elf/local-ifunc-reloc.d -index 29f2d3f3..bf73d9f2 100644 ---- a/ld/testsuite/ld-loongarch-elf/local-ifunc-reloc.d -+++ b/ld/testsuite/ld-loongarch-elf/local-ifunc-reloc.d -@@ -6,5 +6,5 @@ - - DYNAMIC RELOCATION RECORDS - OFFSET +TYPE +VALUE --[[:xdigit:]]+ R_LARCH_IRELATIVE +\*ABS\*\+0x[[:xdigit:]]+ - [[:xdigit:]]+ R_LARCH_64 +test -+[[:xdigit:]]+ R_LARCH_IRELATIVE +\*ABS\*\+0x[[:xdigit:]]+ --- -2.33.0 - diff --git a/LoongArch-opcodes-Add-support-for-tls-le-relax.patch b/LoongArch-opcodes-Add-support-for-tls-le-relax.patch deleted file mode 100644 index e271ed9..0000000 --- a/LoongArch-opcodes-Add-support-for-tls-le-relax.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 689b6f002360f50386eb3bd83a20aff8cf61afb1 Mon Sep 17 00:00:00 2001 -From: changjiachen -Date: Thu, 28 Dec 2023 19:58:28 +0800 -Subject: [PATCH 033/123] LoongArch: opcodes: Add support for tls le relax. - -Add new opcode for tls le relax. - - opcode/ChangeLog: - - * loongarch-opc.c: Add new loongarch opcode. ---- - opcodes/loongarch-opc.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/opcodes/loongarch-opc.c b/opcodes/loongarch-opc.c -index a632373f..44b5f612 100644 ---- a/opcodes/loongarch-opc.c -+++ b/opcodes/loongarch-opc.c -@@ -464,6 +464,7 @@ static struct loongarch_opcode loongarch_fix_opcodes[] = - { 0x000c0000, 0xfffc0000, "bytepick.d", "r0:5,r5:5,r10:5,u15:3", 0, 0, 0, 0 }, - { 0x00100000, 0xffff8000, "add.w", "r0:5,r5:5,r10:5", 0, 0, 0, 0 }, - { 0x00108000, 0xffff8000, "add.d", "r0:5,r5:5,r10:5", 0, 0, 0, 0 }, -+ { 0x00108000, 0xffff8000, "add.d", "r0:5,r5:5,r10:5,t", 0, 0, 0, 0 }, - { 0x00110000, 0xffff8000, "sub.w", "r0:5,r5:5,r10:5", 0, 0, 0, 0 }, - { 0x00118000, 0xffff8000, "sub.d", "r0:5,r5:5,r10:5", 0, 0, 0, 0 }, - { 0x00120000, 0xffff8000, "slt", "r0:5,r5:5,r10:5", 0, 0, 0, 0 }, --- -2.33.0 - diff --git a/LoongArch-readelf-d-RELASZ-excludes-.rela.plt-size.patch b/LoongArch-readelf-d-RELASZ-excludes-.rela.plt-size.patch deleted file mode 100644 index 4573489..0000000 --- a/LoongArch-readelf-d-RELASZ-excludes-.rela.plt-size.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 601f6c1fb4e3b4a0174d99ec5dd6d4d19f89013e Mon Sep 17 00:00:00 2001 -From: mengqinggang -Date: Mon, 31 Jul 2023 17:09:48 +0800 -Subject: [PATCH 014/123] LoongArch: readelf -d RELASZ excludes .rela.plt size - -Before, readelf -d RELASZ is the sum of .rela.dyn size and .rela.plt size. -To consistent with LoongArch lld, RELASZ chang to only the size of .rela.dyn. ---- - bfd/elfnn-loongarch.c | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c -index 2fe4924b..7dbe31eb 100644 ---- a/bfd/elfnn-loongarch.c -+++ b/bfd/elfnn-loongarch.c -@@ -4672,4 +4672,6 @@ elf_loongarch64_hash_symbol (struct elf_link_hash_entry *h) - #define elf_backend_hash_symbol elf_loongarch64_hash_symbol - #define bfd_elfNN_bfd_relax_section loongarch_elf_relax_section - -+#define elf_backend_dtrel_excludes_plt 1 -+ - #include "elfNN-target.h" --- -2.33.0 - diff --git a/MIPS-GAS-Add-march-loongson2f-to-loongson-2f-3-test.patch b/MIPS-GAS-Add-march-loongson2f-to-loongson-2f-3-test.patch deleted file mode 100644 index fe9d680..0000000 --- a/MIPS-GAS-Add-march-loongson2f-to-loongson-2f-3-test.patch +++ /dev/null @@ -1,25 +0,0 @@ -From a06390be2ae099645373a826da3fd0f9d6c3e48a Mon Sep 17 00:00:00 2001 -From: YunQiang Su -Date: Fri, 24 Nov 2023 14:35:12 +0800 -Subject: [PATCH 018/123] MIPS/GAS: Add -march=loongson2f to loongson-2f-3 test - -On MIPSr6, the encoding of JR instruction has been chaned. -This patch can fix these failures for r6 default triples: - ST Microelectronics Loongson-2F workarounds of Jump Instruction issue ---- - gas/testsuite/gas/mips/loongson-2f-3.d | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/gas/testsuite/gas/mips/loongson-2f-3.d b/gas/testsuite/gas/mips/loongson-2f-3.d -index f3ac2c97..c31d3abf 100644 ---- a/gas/testsuite/gas/mips/loongson-2f-3.d -+++ b/gas/testsuite/gas/mips/loongson-2f-3.d -@@ -1,4 +1,4 @@ --#as: -mfix-loongson2f-jump -+#as: -march=loongson2f -mfix-loongson2f-jump - #objdump: -M reg-names=numeric -dr - #name: ST Microelectronics Loongson-2F workarounds of Jump Instruction issue - --- -2.33.0 - diff --git a/Make-sure-DW_CFA_advance_loc4-is-in-the-same-frag.patch b/Make-sure-DW_CFA_advance_loc4-is-in-the-same-frag.patch deleted file mode 100644 index 1fe10de..0000000 --- a/Make-sure-DW_CFA_advance_loc4-is-in-the-same-frag.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 4c35fff684c03e27b0b4a421681be4e90cd293a2 Mon Sep 17 00:00:00 2001 -From: Jinyang He -Date: Thu, 10 Aug 2023 10:21:40 +0800 -Subject: [PATCH 008/123] Make sure DW_CFA_advance_loc4 is in the same frag - -Do the same as commit b9d8f5601bcf in another place generating -DW_CFA_advance_loc4. The idea behind commit b9d8f5601bcf was that -when a DW_CFA_advance_loc4 of zero is seen in eh_frame_relax_frag and -eh_frame_convert_frag we want to remove the opcode entirely, not just -convert to a nop. If the opcode was split over two frags then a size -adjustment would need to be done to the first frag, not just the -second as is correct for other cases with split frags. This would -complicate the eh relaxation. It's easier to ensure the frag is not -split. - - * ehopt.c (check_eh_frame): Don't allow DW_CFA_advance_loc4 - to be placed in a different frag to the rs_cfa. ---- - gas/ehopt.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/gas/ehopt.c b/gas/ehopt.c -index feea61b9..9d6606ad 100644 ---- a/gas/ehopt.c -+++ b/gas/ehopt.c -@@ -386,7 +386,7 @@ check_eh_frame (expressionS *exp, unsigned int *pnbytes) - { - /* This might be a DW_CFA_advance_loc4. Record the frag and the - position within the frag, so that we can change it later. */ -- frag_grow (1); -+ frag_grow (1 + 4); - d->state = state_saw_loc4; - d->loc4_frag = frag_now; - d->loc4_fix = frag_now_fix (); --- -2.33.0 - diff --git a/Modify-test-because-of-readelf-not-update.patch b/Modify-test-because-of-readelf-not-update.patch deleted file mode 100644 index 0b7c0d8..0000000 --- a/Modify-test-because-of-readelf-not-update.patch +++ /dev/null @@ -1,201 +0,0 @@ -From e0968610301d68ee7bf35f2bcba0817d08e07921 Mon Sep 17 00:00:00 2001 -From: Xin Wang -Date: Fri, 25 Oct 2024 15:07:38 +0800 -Subject: [PATCH 121/123] Modify test because of readelf not update - ---- - ld/testsuite/ld-loongarch-elf/relr-align.d | 24 +++++++++---------- - ld/testsuite/ld-loongarch-elf/relr-data-pie.d | 12 +++++----- - .../ld-loongarch-elf/relr-data-shared.d | 10 ++++---- - .../ld-loongarch-elf/relr-discard-pie.d | 8 +++---- - .../ld-loongarch-elf/relr-discard-shared.d | 6 ++--- - ld/testsuite/ld-loongarch-elf/relr-got-pie.d | 12 +++++----- - .../ld-loongarch-elf/relr-got-shared.d | 10 ++++---- - .../ld-loongarch-elf/relr-got-start.d | 6 ++--- - ld/testsuite/ld-loongarch-elf/relr-text-pie.d | 6 ++--- - .../ld-loongarch-elf/relr-text-shared.d | 6 ++--- - 10 files changed, 50 insertions(+), 50 deletions(-) - -diff --git a/ld/testsuite/ld-loongarch-elf/relr-align.d b/ld/testsuite/ld-loongarch-elf/relr-align.d -index d534243b..e95b0fb8 100644 ---- a/ld/testsuite/ld-loongarch-elf/relr-align.d -+++ b/ld/testsuite/ld-loongarch-elf/relr-align.d -@@ -8,15 +8,15 @@ Relocation section '\.rela.dyn' at offset 0x[0-9a-f]+ contains 3 entries: - 0000000012340019 0000000000000003 R_LARCH_RELATIVE 10000 - 0000000012340041 0000000000000003 R_LARCH_RELATIVE 10000 - --Relocation section '\.relr.dyn' at offset 0x[0-9a-f]+ contains 9 entries which relocate 10 locations: --Index: Entry Address Symbolic Address --0000: 0000000012340000 0000000012340000 double_0 --0001: 0000000000000003 0000000012340008 double_0 \+ 0x8 --0002: 0000000012340022 0000000012340022 double_2 --0003: 0000000000000003 000000001234002a double_2 \+ 0x8 --0004: 0000000012340038 0000000012340038 single_0 --0005: 000000001234004a 000000001234004a single_2 --0006: 0000000012340058 0000000012340058 big --0007: 8000000100000001 0000000012340158 big \+ 0x100 -- 0000000012340250 big \+ 0x1f8 --0008: 0000000000000003 0000000012340258 big \+ 0x200 -+Relocation section '\.relr.dyn' at offset 0x[0-9a-f]+ contains 9 entries: -+ 10 offsets -+0000000012340000 -+0000000012340008 -+0000000012340022 -+000000001234002a -+0000000012340038 -+000000001234004a -+0000000012340058 -+0000000012340158 -+0000000012340250 -+0000000012340258 -diff --git a/ld/testsuite/ld-loongarch-elf/relr-data-pie.d b/ld/testsuite/ld-loongarch-elf/relr-data-pie.d -index 20ef9ac1..fe32ae34 100644 ---- a/ld/testsuite/ld-loongarch-elf/relr-data-pie.d -+++ b/ld/testsuite/ld-loongarch-elf/relr-data-pie.d -@@ -10,9 +10,9 @@ Relocation section '\.rela\.dyn' at offset 0x[0-9a-f]+ contains 5 entries: - 0000000012340018 0000000000000003 R_LARCH_RELATIVE 12340050 - 0000000012340040 0000000c00000002 R_LARCH_64 0000000000000000 sym_weak_undef \+ 0 - --Relocation section '\.relr\.dyn' at offset 0x[0-9a-f]+ contains 2 entries which relocate 4 locations: --Index: Entry Address Symbolic Address --0000: 0000000012340020 0000000012340020 aligned_local --0001: 0000000000000027 0000000012340028 aligned_hidden -- 0000000012340030 aligned_global -- 0000000012340048 aligned_DYNAMIC -+Relocation section '\.relr\.dyn' at offset 0x[0-9a-f]+ contains 2 entries: -+ 4 offsets -+0000000012340020 -+0000000012340028 -+0000000012340030 -+0000000012340048 -diff --git a/ld/testsuite/ld-loongarch-elf/relr-data-shared.d b/ld/testsuite/ld-loongarch-elf/relr-data-shared.d -index 37e4c0da..0521786f 100644 ---- a/ld/testsuite/ld-loongarch-elf/relr-data-shared.d -+++ b/ld/testsuite/ld-loongarch-elf/relr-data-shared.d -@@ -11,8 +11,8 @@ Relocation section '\.rela\.dyn' at offset 0x[0-9a-f]+ contains 6 entries: - 0000000012340030 0000000d00000002 R_LARCH_64 000000000001000c sym_global \+ 0 - 0000000012340040 0000000c00000002 R_LARCH_64 0000000000000000 sym_weak_undef \+ 0 - --Relocation section '\.relr\.dyn' at offset 0x[0-9a-f]+ contains 2 entries which relocate 3 locations: --Index: Entry Address Symbolic Address --0000: 0000000012340020 0000000012340020 aligned_local --0001: 0000000000000023 0000000012340028 aligned_hidden -- 0000000012340048 aligned_DYNAMIC -+Relocation section '\.relr\.dyn' at offset 0x[0-9a-f]+ contains 2 entries: -+ 3 offsets -+0000000012340020 -+0000000012340028 -+0000000012340048 -diff --git a/ld/testsuite/ld-loongarch-elf/relr-discard-pie.d b/ld/testsuite/ld-loongarch-elf/relr-discard-pie.d -index 4ea8ae5e..11d2dba8 100644 ---- a/ld/testsuite/ld-loongarch-elf/relr-discard-pie.d -+++ b/ld/testsuite/ld-loongarch-elf/relr-discard-pie.d -@@ -2,7 +2,7 @@ - #ld: -pie -z pack-relative-relocs -T relr-discard.ld - #readelf: -rW - --Relocation section '\.relr\.dyn' at offset 0x[0-9a-f]+ contains 2 entries which relocate 2 locations: --Index: Entry Address Symbolic Address --0000: 0000000000020008 0000000000020008 _GLOBAL_OFFSET_TABLE_ \+ 0x8 --0001: 0000000000000003 0000000000020010 _GLOBAL_OFFSET_TABLE_ \+ 0x10 -+Relocation section '\.relr\.dyn' at offset 0x[0-9a-f]+ contains 2 entries: -+ 2 offsets -+0000000000020008 -+0000000000020010 -diff --git a/ld/testsuite/ld-loongarch-elf/relr-discard-shared.d b/ld/testsuite/ld-loongarch-elf/relr-discard-shared.d -index 8bfd8ba5..2a540832 100644 ---- a/ld/testsuite/ld-loongarch-elf/relr-discard-shared.d -+++ b/ld/testsuite/ld-loongarch-elf/relr-discard-shared.d -@@ -6,6 +6,6 @@ Relocation section '\.rela\.dyn' at offset 0x[0-9a-f]+ contains 1 entry: - Offset Info Type Symbol's Value Symbol's Name \+ Addend - 0000000000020010 0000000300000002 R_LARCH_64 000000000001000c sym_global \+ 0 - --Relocation section '\.relr\.dyn' at offset 0x[0-9a-f]+ contains 1 entry which relocates 1 location: --Index: Entry Address Symbolic Address --0000: 0000000000020008 0000000000020008 _GLOBAL_OFFSET_TABLE_ \+ 0x8 -+Relocation section '\.relr\.dyn' at offset 0x[0-9a-f]+ contains 1 entry: -+ 1 offset -+0000000000020008 -diff --git a/ld/testsuite/ld-loongarch-elf/relr-got-pie.d b/ld/testsuite/ld-loongarch-elf/relr-got-pie.d -index e994f2bf..849bf9b4 100644 ---- a/ld/testsuite/ld-loongarch-elf/relr-got-pie.d -+++ b/ld/testsuite/ld-loongarch-elf/relr-got-pie.d -@@ -7,9 +7,9 @@ Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 2 entries: - 0000000000000000 0000000000000000 R_LARCH_NONE 0 - 0000000000020030 0000000200000002 R_LARCH_64 0000000000000000 sym_weak_undef \+ 0 - --Relocation section '.relr.dyn' at offset 0x[0-9a-f]+ contains 2 entries which relocate 4 locations: --Index: Entry Address Symbolic Address --0000: 0000000000020008 0000000000020008 _GLOBAL_OFFSET_TABLE_ \+ 0x8 --0001: 000000000000000f 0000000000020010 _GLOBAL_OFFSET_TABLE_ \+ 0x10 -- 0000000000020018 _GLOBAL_OFFSET_TABLE_ \+ 0x18 -- 0000000000020020 _GLOBAL_OFFSET_TABLE_ \+ 0x20 -+Relocation section '.relr.dyn' at offset 0x[0-9a-f]+ contains 2 entries: -+ 4 offsets -+0000000000020008 -+0000000000020010 -+0000000000020018 -+0000000000020020 -diff --git a/ld/testsuite/ld-loongarch-elf/relr-got-shared.d b/ld/testsuite/ld-loongarch-elf/relr-got-shared.d -index 169e0e5d..030261af 100644 ---- a/ld/testsuite/ld-loongarch-elf/relr-got-shared.d -+++ b/ld/testsuite/ld-loongarch-elf/relr-got-shared.d -@@ -8,8 +8,8 @@ Relocation section '\.rela\.dyn' at offset 0x[0-9a-f]+ contains 3 entries: - 0000000000020028 0000000500000002 R_LARCH_64 000000000000002a sym_global_abs \+ 0 - 0000000000020030 0000000200000002 R_LARCH_64 0000000000000000 sym_weak_undef \+ 0 - --Relocation section '\.relr\.dyn' at offset 0x[0-9a-f]+ contains 2 entries which relocate 3 locations: --Index: Entry Address Symbolic Address --0000: 0000000000020008 0000000000020008 _GLOBAL_OFFSET_TABLE_ \+ 0x8 --0001: 0000000000000007 0000000000020010 _GLOBAL_OFFSET_TABLE_ \+ 0x10 -- 0000000000020018 _GLOBAL_OFFSET_TABLE_ \+ 0x18 -+Relocation section '\.relr\.dyn' at offset 0x[0-9a-f]+ contains 2 entries: -+ 3 offsets -+0000000000020008 -+0000000000020010 -+0000000000020018 -diff --git a/ld/testsuite/ld-loongarch-elf/relr-got-start.d b/ld/testsuite/ld-loongarch-elf/relr-got-start.d -index 0b1a5b98..b4723d6c 100644 ---- a/ld/testsuite/ld-loongarch-elf/relr-got-start.d -+++ b/ld/testsuite/ld-loongarch-elf/relr-got-start.d -@@ -2,6 +2,6 @@ - #ld: -pie -z pack-relative-relocs -T relr-relocs.ld - #readelf: -rW - --Relocation section '\.relr\.dyn' at offset 0x[a-z0-f]+ contains 1 entry which relocates 1 location: --Index: Entry Address Symbolic Address --0000: 0000000000020008 0000000000020008 _GLOBAL_OFFSET_TABLE_ \+ 0x8 -+Relocation section '\.relr\.dyn' at offset 0x[a-z0-f]+ contains 1 entry: -+ 1 offset -+0000000000020008 -diff --git a/ld/testsuite/ld-loongarch-elf/relr-text-pie.d b/ld/testsuite/ld-loongarch-elf/relr-text-pie.d -index 5121313e..c39975ba 100644 ---- a/ld/testsuite/ld-loongarch-elf/relr-text-pie.d -+++ b/ld/testsuite/ld-loongarch-elf/relr-text-pie.d -@@ -9,6 +9,6 @@ - 0x0000000000000023 \(RELRSZ\) 8 \(bytes\) - 0x0000000000000025 \(RELRENT\) 8 \(bytes\) - #... --Relocation section '\.relr\.dyn' .* contains 1 entry which relocates 1 location: --Index: Entry Address Symbolic Address --0000: 0000000000010000 0000000000010000 _start -+Relocation section '\.relr\.dyn' .* contains 1 entry: -+ 1 offset -+0000000000010000 -diff --git a/ld/testsuite/ld-loongarch-elf/relr-text-shared.d b/ld/testsuite/ld-loongarch-elf/relr-text-shared.d -index 8e34500f..5d86d398 100644 ---- a/ld/testsuite/ld-loongarch-elf/relr-text-shared.d -+++ b/ld/testsuite/ld-loongarch-elf/relr-text-shared.d -@@ -9,6 +9,6 @@ - 0x0000000000000023 \(RELRSZ\) 8 \(bytes\) - 0x0000000000000025 \(RELRENT\) 8 \(bytes\) - #... --Relocation section '\.relr\.dyn' .* contains 1 entry which relocates 1 location: --Index: Entry Address Symbolic Address --0000: 0000000000010000 0000000000010000 _start -+Relocation section '\.relr\.dyn' .* contains 1 entry: -+ 1 offset -+0000000000010000 --- -2.33.0 - diff --git a/Not-append-rela-for-absolute-symbol.patch b/Not-append-rela-for-absolute-symbol.patch deleted file mode 100644 index e457be9..0000000 --- a/Not-append-rela-for-absolute-symbol.patch +++ /dev/null @@ -1,133 +0,0 @@ -From 41abd06f7ba97c5b92a2d38c99c357772bba3ade Mon Sep 17 00:00:00 2001 -From: Xin Wang -Date: Fri, 16 Aug 2024 11:28:10 +0800 -Subject: [PATCH 113/123] Not append rela for absolute symbol - -LoongArch: Not append rela for absolute symbol - -Use la.global to get absolute symbol like la.abs. -la.global put address of a global symbol into a got -entry and append a rela for it, which will be used -to relocate by dynamic linker. Dynamic linker should -not relocate for got entry of absolute symbol as it -stores symval not symbol's address. ---- - bfd/elfnn-loongarch.c | 19 ++++++++++++++++++- - ld/testsuite/ld-loongarch-elf/abs-global.out | 1 + - ld/testsuite/ld-loongarch-elf/abs-global.s | 5 +++++ - .../ld-loongarch-elf/get_abs_global_sym.c | 7 +++++++ - .../ld-loongarch-elf/ld-loongarch-elf.exp | 12 ++++++++++++ - 5 files changed, 43 insertions(+), 1 deletion(-) - create mode 100644 ld/testsuite/ld-loongarch-elf/abs-global.out - create mode 100644 ld/testsuite/ld-loongarch-elf/abs-global.s - create mode 100644 ld/testsuite/ld-loongarch-elf/get_abs_global_sym.c - -diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c -index 770483cd..09a9513b 100644 ---- a/bfd/elfnn-loongarch.c -+++ b/bfd/elfnn-loongarch.c -@@ -4135,6 +4135,7 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, - if (!WILL_CALL_FINISH_DYNAMIC_SYMBOL (is_dyn, - bfd_link_pic (info), - h) -+ && !bfd_is_abs_section(h->root.u.def.section) - && bfd_link_pic (info) - && LARCH_REF_LOCAL (info, h) - && !info->enable_dt_relr) -@@ -4157,7 +4158,8 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, - && local_got_offsets[r_symndx] != MINUS_ONE); - - got_off = local_got_offsets[r_symndx] & (~(bfd_vma)1); -- if ((local_got_offsets[r_symndx] & 1) == 0) -+ if (sym->st_shndx != SHN_ABS -+ && (local_got_offsets[r_symndx] & 1) == 0) - { - if (bfd_link_pic (info) && !info->enable_dt_relr) - { -@@ -5314,6 +5316,7 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, - bfd_vma symval; - asection *sym_sec; - bool local_got = false; -+ bool is_abs_symbol = false; - Elf_Internal_Rela *rel = relocs + i; - struct elf_link_hash_entry *h = NULL; - unsigned long r_type = ELFNN_R_TYPE (rel->r_info); -@@ -5495,7 +5498,21 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, - break; - - case R_LARCH_GOT_PC_HI20: -+ if (h) -+ is_abs_symbol = bfd_is_abs_section(h->root.u.def.section); -+ else -+ { -+ Elf_Internal_Sym *sym = (Elf_Internal_Sym *)symtab_hdr->contents -+ + ELFNN_R_SYM (rel->r_info); -+ is_abs_symbol = sym->st_shndx == SHN_ABS; -+ } -+ /* If symval is in the range [-2^31, 2^31), we can relax the -+ pair of instructions from pcalau12i/ld.d to lu12i.w/ori for -+ abosulte symbol. This is not implemented yet, so we just -+ remain the r_type which will be needed when relocate for -+ absolute symbol. */ - if (local_got && 0 == info->relax_pass -+ && !is_abs_symbol - && (i + 4) <= sec->reloc_count) - { - if (loongarch_relax_pcala_ld (abfd, sec, rel)) -diff --git a/ld/testsuite/ld-loongarch-elf/abs-global.out b/ld/testsuite/ld-loongarch-elf/abs-global.out -new file mode 100644 -index 00000000..3656652b ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/abs-global.out -@@ -0,0 +1 @@ -+abba -diff --git a/ld/testsuite/ld-loongarch-elf/abs-global.s b/ld/testsuite/ld-loongarch-elf/abs-global.s -new file mode 100644 -index 00000000..93a5da6d ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/abs-global.s -@@ -0,0 +1,5 @@ -+.text -+.globl get_sym -+get_sym: -+ la.global $a0, sym -+ ret -diff --git a/ld/testsuite/ld-loongarch-elf/get_abs_global_sym.c b/ld/testsuite/ld-loongarch-elf/get_abs_global_sym.c -new file mode 100644 -index 00000000..29781ad7 ---- /dev/null -+++ b/ld/testsuite/ld-loongarch-elf/get_abs_global_sym.c -@@ -0,0 +1,7 @@ -+#include -+ -+extern int get_sym(); -+int main() { -+ printf("%x\n", get_sym()); -+ return 0; -+} -diff --git a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -index cb6d2296..555ebf92 100644 ---- a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -+++ b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp -@@ -130,6 +130,18 @@ if [istarget "loongarch64-*-*"] { - "a.binary" \ - ] \ - ] -+ -+ -+ run_ld_link_exec_tests [list \ -+ [list \ -+ "get global abs symbol test" \ -+ "-Wl,-z norelro -Wl,--defsym sym=0xabba" \ -+ "" \ -+ { abs-global.s get_abs_global_sym.c} \ -+ "abs-global" \ -+ "abs-global.out" \ -+ ] \ -+ ] - } - - if [istarget "loongarch64-*-*"] { --- -2.33.0 - diff --git a/PATCH-v2-gas-NEWS-ld-NEWS-Announce-LoongArch-changes.patch b/PATCH-v2-gas-NEWS-ld-NEWS-Announce-LoongArch-changes.patch deleted file mode 100644 index 1199cad..0000000 --- a/PATCH-v2-gas-NEWS-ld-NEWS-Announce-LoongArch-changes.patch +++ /dev/null @@ -1,167 +0,0 @@ -From ae6dd4b75b96f999e1480287810aef41bbdc4969 Mon Sep 17 00:00:00 2001 -From: Xi Ruoyao -Date: Tue, 23 Jan 2024 16:00:32 +0000 -Subject: [PATCH 049/123] [PATCH v2] gas/NEWS, ld/NEWS: Announce LoongArch - changes in 2.42 - ---- - gas/NEWS | 93 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - ld/NEWS | 40 ++++++++++++++++++++++++ - 2 files changed, 133 insertions(+) - -diff --git a/gas/NEWS b/gas/NEWS -index 59bdd30a..9ad24543 100644 ---- a/gas/NEWS -+++ b/gas/NEWS -@@ -1,5 +1,98 @@ - -*- text -*- - -+Changes in 2.42: -+ -+* Experimental support in GAS to synthesize CFI for ABI-conformant, -+ hand-written asm using the new command line option --scfi=experimental on -+ x86-64. Only System V AMD64 ABI is supported. -+ -+* Add support for the Arm Scalable Vector Extension version 2.1 (SVE2.1) -+ instructions. -+ -+* Add support for the AArch64 Scalable Matrix Extension version 2.1 (SME2.1) -+ instructions. -+ -+* Add support for 'armv8.9-a' and 'armv9.4-a' for -march in Arm GAS. -+ -+* Initial support for Intel APX: 32 GPRs, NDD, PUSH2/POP2 and PUSHP/POPP. -+ -+* On RISC-V macro instructions expanding to AUIPC and a load, store, or branch -+ no longer accept x0 as an intermediate and/or destination register. -+ -+* Add support for Reliability, Availability and Serviceability extension v2 -+ (RASv2) for AArch64. -+ -+* Add support for 128-bit Atomic Instructions (LSE128) for AArch64. -+ -+* Add support for Guarded Control Stack (GCS) for AArch64. -+ -+* Add support for AArch64 Check Feature Status Extension (CHK). -+ -+* Add support for 'armv8.9-a' and 'armv9.4-a' for -march in AArch64 GAS. -+ -+* Add support for Intel USER_MSR instructions. -+ -+* Add support for Intel AVX10.1. -+ -+* Add support for Intel PBNDKB instructions. -+ -+* Add support for Intel SM4 instructions. -+ -+* Add support for Intel SM3 instructions. -+ -+* Add support for Intel SHA512 instructions. -+ -+* Add support for Intel AVX-VNNI-INT16 instructions. -+ -+* Add support for Cortex-A520 for AArch64. -+ -+* Add support for Cortex-A720 for AArch64. -+ -+* Add support for Cortex-X3 for AArch64. -+ -+* Add support for Cortex-X4 for AArch64. -+ -+* Add support for RISC-V T-Head extensions (XTheadVector, XTheadZvlsseg -+ and XTheadZvamo) from version 2.3.0 of the T-Head ISA manual. -+ -+* Add support for RISC-V CORE-V extensions (XCVmac, XCValu) with version 1.0. -+ -+* Add support for RISC-V SiFive VCIX extension (XSfVcp) with version 1.0. -+ -+* The BPF assembler now uses semi-colon (;) to separate statements, and -+ therefore they cannot longer be used to begin line comments. This matches the -+ behavior of the clang/LLVM BPF assembler. -+ -+* The BPF assembler now allows using both hash (#) and double slash (//) to -+ begin line comments. -+ -+* Add support for LoongArch v1.10 new instructions: estimated reciprocal -+ instructions, sub-word atomic instructions, atomic CAS instructions, -+ 16-byte store-conditional instruction, load-linked instructions with -+ acquire semantics, and store-conditional instructions with release -+ semantics. -+ -+* The %call36 relocation operator, along with the pseudo-instructions -+ call36 and tail36, are now usable with the LoongArch "medium" code -+ model, allowing text sections up to 128 GiB. -+ -+* TLS descriptors (TLSDESC) are now supported on LoongArch. This includes -+ the following new relocation operators: %desc_pc_hi20, %desc_pc_lo12, -+ %desc_ld, and %desc_call, and the la.tls.desc pseudo-instruction. -+ -+* TLS LE relaxation is now supported on LoongArch. New relocation -+ operators %le_hi20_r, %le_lo12r, and %le_add_r are now available. -+ -+* Add support for LoongArch branch relaxation: a conditional branch with -+ destination out of its immediate operand range, but still within -+ a "b"'s range, is now assembled as an inverted branch and a "b". This -+ works around the unreliable branch offset estimation of the compiler -+ when .align directive is encoded into a long NOP sequence with an -+ R_LARCH_RELAX by the assembler. -+ -+* Symbol or label names in LoongArch assembly can now be spelled with -+ double-quotes. -+ - Changes in 2.41: - - * Add support for Intel FRED instructions. -diff --git a/ld/NEWS b/ld/NEWS -index e1ac20b8..687b5190 100644 ---- a/ld/NEWS -+++ b/ld/NEWS -@@ -1,5 +1,45 @@ - -*- text -*- - -+Changes in 2.42: -+ -+* Add -z mark-plt/-z nomark-plt options to x86-64 ELF linker to mark PLT -+ entries with DT_X86_64_PLT, DT_X86_64_PLTSZ and DT_X86_64_PLTENT dynamic -+ tags. Also added --enable-mark-plt configure option to mark PLT entries -+ by default. -+ -+* Support Intel APX relocations. -+ -+* On RISC-V, add ld target option --[no-]check-uleb128. Should rebuild the -+ objects by binutils 2.42 and up if enabling the option and get warnings, -+ since the non-zero addend of SUB_ULEB128 shouldn't be generated from .uleb128 -+ directives. -+ -+* Add support for the KVX instruction set. -+ -+* A new linker script sorting directive has been added: REVERSE. This reverses -+ the order of the sorting. It may be combined with either SORT_BY_NAME or -+ SORT_BY_INIT_PRIORITY. -+ -+* Added --warn-execstack-objects to warn about executable stacks only when an -+ input object file requests one. Also added --error-execstack and -+ --error-rxw-segments options to convert warnings about executable stacks and -+ segments into errors. -+ -+ Also added --enable-error-execstack=[yes|no] and -+ --enable-error-rwx-segments=[yes|no] configure options to set the default for -+ converting warnings into errors. -+ -+* On LoongArch, various linker relaxation bugs are fixed; the most notable -+ of which is BZ 30944 (incorrect .balign semantics). -+ -+* On LoongArch, the LoongArch ABI v2.30 (LoongArch ELF psABI v20231219) is -+ now implemented. This includes new relocation types, and changed -+ semantics for PC-relative relocations handling the higher half of 64-bit -+ offsets. -+ -+* On LoongArch, link-time TLS optimization and TLS relaxation are now -+ supported. -+ - Changes in 2.41: - - * The linker now accepts a command line option of --remap-inputs --- -2.33.0 - diff --git a/PPC-gas-supported-c2000.patch b/PPC-gas-supported-c2000.patch deleted file mode 100644 index 7d9b3eb..0000000 --- a/PPC-gas-supported-c2000.patch +++ /dev/null @@ -1,921 +0,0 @@ -From efa66fcdad9c88db3244ec12e1a64db553a9484c Mon Sep 17 00:00:00 2001 -From: chenyuanfeng -Date: Tue, 27 Feb 2024 09:53:29 +0800 -Subject: [PATCH] PPC-gas-supported-c2000 - ---- - binutils/ChangeLog-2024 | 29 +++++ - binutils/doc/binutils.info | 2 +- - binutils/doc/binutils.texi | 2 +- - gas/config/tc-ppc.c | 2 + - gas/doc/as.info | 5 +- - gas/doc/as.texi | 2 +- - gas/doc/c-ppc.texi | 3 + - gas/po/gas.pot | 233 +++++++++++++++++++------------------ - include/opcode/ppc.h | 7 ++ - opcodes/ppc-dis.c | 21 ++-- - opcodes/ppc-opc.c | 2 +- - 11 files changed, 181 insertions(+), 127 deletions(-) - create mode 100644 binutils/ChangeLog-2024 - -diff --git a/binutils/ChangeLog-2024 b/binutils/ChangeLog-2024 -new file mode 100644 -index 00000000..db429887 ---- /dev/null -+++ b/binutils/ChangeLog-2024 -@@ -0,0 +1,29 @@ -+2024-01-03 YuanFeng Chen -+ -+ * config/tc-ppc.c (md_show_usage): Add -mc2000 options. -+ * ppc.h : (PPC_OPCODE_HTM): Define. -+ (PPC_OPCODE_C2000): Likewise. -+ * ppc-dis.c (PPCHTM): Define as PPC_OPCODE_HTM. -+ (ppc_opts): Add "c2000" entry. -+ (ppc_opts): "power8","power9","power10", "libresoc", "future" entries add PPC_OPCODE_HTM flag. -+ * ppc-opc.c : PPCHTM defined as PPC_OPCODE_HTM instead of PPC_OPCODE_POWER8. -+ * doc/binutils.texi (PowerPC -M option): Mention c2000. -+ * doc/as.texi (Target PowerPC optins): Mention c2000. -+ * doc/c-ppc.texi (PowerPC-Opts): Document "-mc2000". -+ * po/gas.pot: Regenerate. -+ -+ -+For older changes see ChangeLog-2020 -+ -+Copyright (C) 2024 Free Software Foundation, Inc. -+ -+Copying and distribution of this file, with or without modification, -+are permitted in any medium without royalty provided the copyright -+notice and this notice are preserved. -+ -+Local Variables: -+mode: change-log -+left-margin: 8 -+fill-column: 74 -+version-control: never -+End: -\ No newline at end of file -diff --git a/binutils/doc/binutils.info b/binutils/doc/binutils.info -index c9446db8..0fea501d 100644 ---- a/binutils/doc/binutils.info -+++ b/binutils/doc/binutils.info -@@ -2343,7 +2343,7 @@ given. - ‘efs’, ‘power4’, ‘power5’, ‘power6’, ‘power7’, ‘power8’, ‘power9’, - ‘power10’, ‘ppc’, ‘ppc32’, ‘ppc64’, ‘ppc64bridge’, ‘ppcps’, ‘pwr’, - ‘pwr2’, ‘pwr4’, ‘pwr5’, ‘pwr5x’, ‘pwr6’, ‘pwr7’, ‘pwr8’, ‘pwr9’, -- ‘pwr10’, ‘pwrx’, ‘titan’, ‘vle’, and ‘future’. ‘32’ and ‘64’ -+ ‘pwr10’, ‘pwrx’, ‘titan’, ‘c2000’, ‘vle’, and ‘future’. ‘32’ and ‘64’ - modify the default or a prior CPU selection, disabling and enabling - 64-bit insns respectively. In addition, ‘altivec’, ‘any’, ‘lsp’, - ‘htm’, ‘vsx’, ‘spe’ and ‘spe2’ add capabilities to a previous _or -diff --git a/binutils/doc/binutils.texi b/binutils/doc/binutils.texi -index 8314cb57..e94ec504 100644 ---- a/binutils/doc/binutils.texi -+++ b/binutils/doc/binutils.texi -@@ -2655,7 +2655,7 @@ rather than @code{li}. All of the @option{-m} arguments for - @option{ppc32}, @option{ppc64}, @option{ppc64bridge}, @option{ppcps}, - @option{pwr}, @option{pwr2}, @option{pwr4}, @option{pwr5}, @option{pwr5x}, - @option{pwr6}, @option{pwr7}, @option{pwr8}, @option{pwr9}, @option{pwr10}, --@option{pwrx}, @option{titan}, @option{vle}, and @option{future}. -+@option{pwrx}, @option{titan}, @option{c2000}, @option{vle}, and @option{future}. - @option{32} and @option{64} modify the default or a prior CPU - selection, disabling and enabling 64-bit insns respectively. In - addition, @option{altivec}, @option{any}, @option{lsp}, @option{htm}, -diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c -index a8b034c8..d99a6091 100644 ---- a/gas/config/tc-ppc.c -+++ b/gas/config/tc-ppc.c -@@ -1426,6 +1426,8 @@ PowerPC options:\n")); - fprintf (stream, _("\ - -mtitan generate code for AppliedMicro Titan core complex\n")); - fprintf (stream, _("\ -+-mc2000 generate code for Hexin C2000 architecture\n")); -+ fprintf (stream, _("\ - -mregnames Allow symbolic names for registers\n")); - fprintf (stream, _("\ - -mno-regnames Do not allow symbolic names for registers\n")); -diff --git a/gas/doc/as.info b/gas/doc/as.info -index ce2dc91c..ef56d9a0 100644 ---- a/gas/doc/as.info -+++ b/gas/doc/as.info -@@ -288,7 +288,7 @@ Command-Line Options: Invoking. - -mbroadway|-mppc64|-m620|-me500|-e500x2|-me500mc|-me500mc64|-me5500| - -me6500|-mppc64bridge|-mbooke|-mpower4|-mpwr4|-mpower5|-mpwr5|-mpwr5x| - -mpower6|-mpwr6|-mpower7|-mpwr7|-mpower8|-mpwr8|-mpower9|-mpwr9-ma2| -- -mcell|-mspe|-mspe2|-mtitan|-me300|-mcom] -+ -mcell|-mspe|-mspe2|-mtitan|-mc2000|-me300|-mcom] - [-many] [-maltivec|-mvsx|-mhtm|-mvle] - [-mregnames|-mno-regnames] - [-mrelocatable|-mrelocatable-lib|-K PIC] [-memb] -@@ -18702,6 +18702,9 @@ architecture reference manual. - ‘-mfuture’ - Generate code for ’future’ architecture. - -+‘-mc2000’ -+ Generate code for Hexin C2000 architecture. -+ - ‘-mcell’ - ‘-mcell’ - Generate code for Cell Broadband Engine architecture. -diff --git a/gas/doc/as.texi b/gas/doc/as.texi -index 4959c2f6..02cd9058 100644 ---- a/gas/doc/as.texi -+++ b/gas/doc/as.texi -@@ -536,7 +536,7 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}. - @b{-mbroadway}|@b{-mppc64}|@b{-m620}|@b{-me500}|@b{-e500x2}|@b{-me500mc}|@b{-me500mc64}|@b{-me5500}| - @b{-me6500}|@b{-mppc64bridge}|@b{-mbooke}|@b{-mpower4}|@b{-mpwr4}|@b{-mpower5}|@b{-mpwr5}|@b{-mpwr5x}| - @b{-mpower6}|@b{-mpwr6}|@b{-mpower7}|@b{-mpwr7}|@b{-mpower8}|@b{-mpwr8}|@b{-mpower9}|@b{-mpwr9}@b{-ma2}| -- @b{-mcell}|@b{-mspe}|@b{-mspe2}|@b{-mtitan}|@b{-me300}|@b{-mcom}] -+ @b{-mcell}|@b{-mspe}|@b{-mspe2}|@b{-mtitan}|@b{-mc2000}|@b{-me300}|@b{-mcom}] - [@b{-many}] [@b{-maltivec}|@b{-mvsx}|@b{-mhtm}|@b{-mvle}] - [@b{-mregnames}|@b{-mno-regnames}] - [@b{-mrelocatable}|@b{-mrelocatable-lib}|@b{-K PIC}] [@b{-memb}] -diff --git a/gas/doc/c-ppc.texi b/gas/doc/c-ppc.texi -index f1dc17c6..115b730c 100644 ---- a/gas/doc/c-ppc.texi -+++ b/gas/doc/c-ppc.texi -@@ -159,6 +159,9 @@ Generate code for Power10 architecture. - @item -mfuture - Generate code for 'future' architecture. - -+@item -mc2000 -+Generate code for Hexin C2000 architecture. -+ - @item -mcell - @item -mcell - Generate code for Cell Broadband Engine architecture. -diff --git a/gas/po/gas.pot b/gas/po/gas.pot -index bf47483b..36aa5fd7 100644 ---- a/gas/po/gas.pot -+++ b/gas/po/gas.pot -@@ -8,10 +8,11 @@ msgid "" - msgstr "" - "Project-Id-Version: PACKAGE VERSION\n" - "Report-Msgid-Bugs-To: https://sourceware.org/bugzilla/\n" --"POT-Creation-Date: 2023-07-30 14:35+0100\n" -+"POT-Creation-Date: 2024-02-27 09:52+0800\n" - "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" - "Last-Translator: FULL NAME \n" - "Language-Team: LANGUAGE \n" -+"Language: \n" - "MIME-Version: 1.0\n" - "Content-Type: text/plain; charset=CHARSET\n" - "Content-Transfer-Encoding: 8bit\n" -@@ -647,7 +648,7 @@ msgstr "" - #: cgen.c:106 config/tc-alpha.c:2097 config/tc-alpha.c:2121 - #: config/tc-arc.c:4074 config/tc-arc.c:4147 config/tc-d10v.c:550 - #: config/tc-d30v.c:534 config/tc-mn10200.c:1092 config/tc-mn10300.c:1753 --#: config/tc-ppc.c:3959 config/tc-s390.c:1337 config/tc-s390.c:1460 -+#: config/tc-ppc.c:3961 config/tc-s390.c:1337 config/tc-s390.c:1460 - #: config/tc-s390.c:1594 config/tc-v850.c:2535 config/tc-v850.c:2606 - #: config/tc-v850.c:2653 config/tc-v850.c:2690 config/tc-v850.c:2727 - #: config/tc-v850.c:2991 -@@ -655,7 +656,7 @@ msgid "too many fixups" - msgstr "" - - #: cgen.c:371 cgen.c:393 config/tc-d10v.c:461 config/tc-d30v.c:450 --#: config/tc-mn10200.c:1034 config/tc-mn10300.c:1678 config/tc-ppc.c:3481 -+#: config/tc-mn10200.c:1034 config/tc-mn10300.c:1678 config/tc-ppc.c:3483 - #: config/tc-s390.c:1321 config/tc-v850.c:2644 config/tc-v850.c:2678 - #: config/tc-v850.c:2718 config/tc-v850.c:2964 config/tc-z80.c:785 - msgid "illegal operand" -@@ -664,7 +665,7 @@ msgstr "" - #: cgen.c:397 config/tc-avr.c:910 config/tc-d10v.c:463 config/tc-d30v.c:452 - #: config/tc-h8300.c:493 config/tc-mcore.c:662 config/tc-microblaze.c:613 - #: config/tc-mmix.c:495 config/tc-mn10200.c:1037 config/tc-mn10300.c:1681 --#: config/tc-msp430.c:417 config/tc-ppc.c:3483 config/tc-s390.c:1326 -+#: config/tc-msp430.c:417 config/tc-ppc.c:3485 config/tc-s390.c:1326 - #: config/tc-sh.c:988 config/tc-v850.c:2648 config/tc-v850.c:2682 - #: config/tc-v850.c:2722 config/tc-v850.c:2967 config/tc-xgate.c:895 - #: config/tc-z80.c:933 config/tc-z8k.c:349 -@@ -688,7 +689,7 @@ msgstr "" - msgid "expression too complex" - msgstr "" - --#: cgen.c:961 config/tc-ppc.c:7489 config/tc-s390.c:2376 config/tc-v850.c:3500 -+#: cgen.c:961 config/tc-ppc.c:7491 config/tc-s390.c:2376 config/tc-v850.c:3500 - #: config/tc-xstormy16.c:541 - msgid "unresolved expression that must be resolved" - msgstr "" -@@ -2689,7 +2690,7 @@ msgid "sequence number in use for !tlsgd!%ld" - msgstr "" - - #: config/tc-alpha.c:1994 config/tc-arc.c:2869 config/tc-mn10200.c:847 --#: config/tc-mn10300.c:1150 config/tc-ppc.c:2063 config/tc-s390.c:668 -+#: config/tc-mn10300.c:1150 config/tc-ppc.c:2065 config/tc-s390.c:668 - #: config/tc-tilegx.c:422 config/tc-tilegx.c:472 config/tc-tilepro.c:375 - msgid "operand" - msgstr "" -@@ -2706,7 +2707,7 @@ msgstr "" - msgid "can not resolve expression" - msgstr "" - --#: config/tc-alpha.c:3514 config/tc-microblaze.c:204 config/tc-ppc.c:2405 -+#: config/tc-alpha.c:3514 config/tc-microblaze.c:204 config/tc-ppc.c:2407 - #, c-format - msgid ".COMMon length (%ld.) <0! Ignored." - msgstr "" -@@ -2926,8 +2927,8 @@ msgstr "" - #: config/tc-ia64.c:7463 config/tc-m68k.c:4558 config/tc-m68k.c:4570 - #: config/tc-mips.c:3703 config/tc-mips.c:3736 config/tc-mips.c:3762 - #: config/tc-nds32.c:3440 config/tc-nios2.c:3624 config/tc-nios2.c:3629 --#: config/tc-nios2.c:3635 config/tc-ns32k.c:1906 config/tc-ppc.c:1743 --#: config/tc-ppc.c:1783 config/tc-pru.c:1568 config/tc-pru.c:1572 -+#: config/tc-nios2.c:3635 config/tc-ns32k.c:1906 config/tc-ppc.c:1745 -+#: config/tc-ppc.c:1785 config/tc-pru.c:1568 config/tc-pru.c:1572 - #: config/tc-s390.c:538 config/tc-s390.c:576 config/tc-sparc.c:961 - #: config/tc-sparc.c:993 config/tc-tic30.c:121 config/tc-tic30.c:131 - #: config/tc-tic30.c:141 config/tc-tic30.c:151 config/tc-tic4x.c:1220 -@@ -3279,8 +3280,8 @@ msgstr "" - #: config/tc-arc.c:4324 - #, c-format - msgid "" --"A jump instruction with long immediate detected at the end of the ZOL label @" --"%s" -+"A jump instruction with long immediate detected at the end of the ZOL label " -+"@%s" - msgstr "" - - #: config/tc-arc.c:4330 -@@ -6026,7 +6027,7 @@ msgstr "" - #. xgettext:c-format. - #: config/tc-avr.c:1865 config/tc-bfin.c:824 config/tc-d10v.c:1461 - #: config/tc-d30v.c:1768 config/tc-metag.c:7016 config/tc-mn10200.c:772 --#: config/tc-mn10300.c:2178 config/tc-msp430.c:4645 config/tc-ppc.c:7768 -+#: config/tc-mn10300.c:2178 config/tc-msp430.c:4645 config/tc-ppc.c:7770 - #: config/tc-spu.c:878 config/tc-spu.c:1091 config/tc-v850.c:3365 - #: config/tc-z80.c:3878 - #, c-format -@@ -8716,8 +8717,8 @@ msgstr "" - #: config/tc-i386.c:7529 - #, c-format - msgid "" --"no instruction mnemonic suffix given and no register operands; can't size `%" --"s'" -+"no instruction mnemonic suffix given and no register operands; can't size " -+"`%s'" - msgstr "" - - #: config/tc-i386.c:7534 -@@ -10849,8 +10850,8 @@ msgstr "" - msgid ".SCOMMon length (%ld.) <0! Ignored." - msgstr "" - --#: config/tc-m32r.c:1514 config/tc-microblaze.c:218 config/tc-ppc.c:2419 --#: config/tc-ppc.c:4358 config/tc-ppc.c:4413 -+#: config/tc-m32r.c:1514 config/tc-microblaze.c:218 config/tc-ppc.c:2421 -+#: config/tc-ppc.c:4360 config/tc-ppc.c:4415 - msgid "ignoring bad alignment" - msgstr "" - -@@ -11696,7 +11697,7 @@ msgid_plural "%s relocations do not fit in %u bytes" - msgstr[0] "" - msgstr[1] "" - --#: config/tc-m68k.c:7940 config/tc-ppc.c:2592 -+#: config/tc-m68k.c:7940 config/tc-ppc.c:2594 - msgid "unknown .gnu_attribute value" - msgstr "" - -@@ -11737,11 +11738,10 @@ msgstr "" - msgid "base register expected" - msgstr "" - --#: config/tc-mcore.c:888 config/tc-microblaze.c:948 --#: config/tc-microblaze.c:1084 config/tc-microblaze.c:1118 --#: config/tc-microblaze.c:1573 config/tc-microblaze.c:1641 --#: config/tc-microblaze.c:1716 config/tc-microblaze.c:2137 --#: config/tc-microblaze.c:2186 -+#: config/tc-mcore.c:888 config/tc-microblaze.c:948 config/tc-microblaze.c:1084 -+#: config/tc-microblaze.c:1118 config/tc-microblaze.c:1573 -+#: config/tc-microblaze.c:1641 config/tc-microblaze.c:1716 -+#: config/tc-microblaze.c:2137 config/tc-microblaze.c:2186 - #, c-format - msgid "unknown opcode \"%s\"" - msgstr "" -@@ -13767,7 +13767,7 @@ msgid "Unrecognized opcode: `%s'" - msgstr "" - - #. xgettext:c-format. --#: config/tc-mn10200.c:1133 config/tc-mn10300.c:1822 config/tc-ppc.c:4008 -+#: config/tc-mn10200.c:1133 config/tc-mn10300.c:1822 config/tc-ppc.c:4010 - #: config/tc-s390.c:1607 config/tc-v850.c:3041 - #, c-format - msgid "junk at end of line: `%s'" -@@ -15226,7 +15226,7 @@ msgstr "" - msgid "pcrel too far" - msgstr "" - --#: config/tc-ppc.c:964 config/tc-ppc.c:972 config/tc-ppc.c:3495 -+#: config/tc-ppc.c:964 config/tc-ppc.c:972 config/tc-ppc.c:3497 - msgid "invalid register expression" - msgstr "" - -@@ -15494,414 +15494,419 @@ msgstr "" - - #: config/tc-ppc.c:1428 - #, c-format --msgid "-mregnames Allow symbolic names for registers\n" -+msgid "-mc2000 generate code for Hexin C2000 architecture\n" - msgstr "" - - #: config/tc-ppc.c:1430 - #, c-format -+msgid "-mregnames Allow symbolic names for registers\n" -+msgstr "" -+ -+#: config/tc-ppc.c:1432 -+#, c-format - msgid "-mno-regnames Do not allow symbolic names for registers\n" - msgstr "" - --#: config/tc-ppc.c:1433 -+#: config/tc-ppc.c:1435 - #, c-format - msgid "-mrelocatable support for GCC's -mrelocatble option\n" - msgstr "" - --#: config/tc-ppc.c:1435 -+#: config/tc-ppc.c:1437 - #, c-format - msgid "-mrelocatable-lib support for GCC's -mrelocatble-lib option\n" - msgstr "" - --#: config/tc-ppc.c:1437 -+#: config/tc-ppc.c:1439 - #, c-format - msgid "-memb set PPC_EMB bit in ELF flags\n" - msgstr "" - --#: config/tc-ppc.c:1439 -+#: config/tc-ppc.c:1441 - #, c-format - msgid "" - "-mlittle, -mlittle-endian, -le\n" - " generate code for a little endian machine\n" - msgstr "" - --#: config/tc-ppc.c:1442 -+#: config/tc-ppc.c:1444 - #, c-format - msgid "" - "-mbig, -mbig-endian, -be\n" - " generate code for a big endian machine\n" - msgstr "" - --#: config/tc-ppc.c:1445 -+#: config/tc-ppc.c:1447 - #, c-format - msgid "-msolaris generate code for Solaris\n" - msgstr "" - --#: config/tc-ppc.c:1447 -+#: config/tc-ppc.c:1449 - #, c-format - msgid "-mno-solaris do not generate code for Solaris\n" - msgstr "" - --#: config/tc-ppc.c:1449 -+#: config/tc-ppc.c:1451 - #, c-format - msgid "-K PIC set EF_PPC_RELOCATABLE_LIB in ELF flags\n" - msgstr "" - --#: config/tc-ppc.c:1451 -+#: config/tc-ppc.c:1453 - #, c-format - msgid "-V print assembler version number\n" - msgstr "" - --#: config/tc-ppc.c:1453 -+#: config/tc-ppc.c:1455 - #, c-format - msgid "-Qy, -Qn ignored\n" - msgstr "" - --#: config/tc-ppc.c:1456 -+#: config/tc-ppc.c:1458 - #, c-format - msgid "" - "-nops=count when aligning, more than COUNT nops uses a branch\n" - msgstr "" - --#: config/tc-ppc.c:1458 -+#: config/tc-ppc.c:1460 - #, c-format - msgid "-ppc476-workaround warn if emitting data to code sections\n" - msgstr "" - --#: config/tc-ppc.c:1488 -+#: config/tc-ppc.c:1490 - #, c-format - msgid "unknown default cpu = %s, os = %s" - msgstr "" - --#: config/tc-ppc.c:1574 -+#: config/tc-ppc.c:1576 - #, c-format - msgid "mask trims opcode bits for %s" - msgstr "" - --#: config/tc-ppc.c:1584 -+#: config/tc-ppc.c:1586 - #, c-format - msgid "operand index error for %s" - msgstr "" - --#: config/tc-ppc.c:1610 -+#: config/tc-ppc.c:1612 - #, c-format - msgid "operand %d overlap in %s" - msgstr "" - --#: config/tc-ppc.c:1619 -+#: config/tc-ppc.c:1621 - #, c-format - msgid "non-optional operand %d follows optional operand in %s" - msgstr "" - --#: config/tc-ppc.c:1685 -+#: config/tc-ppc.c:1687 - #, c-format - msgid "powerpc_operands[%d].bitm invalid" - msgstr "" - --#: config/tc-ppc.c:1692 -+#: config/tc-ppc.c:1694 - #, c-format - msgid "powerpc_operands[%d] duplicates powerpc_operands[%d]" - msgstr "" - --#: config/tc-ppc.c:1720 config/tc-ppc.c:1773 config/tc-ppc.c:1815 --#: config/tc-ppc.c:1863 -+#: config/tc-ppc.c:1722 config/tc-ppc.c:1775 config/tc-ppc.c:1817 -+#: config/tc-ppc.c:1865 - #, c-format - msgid "major opcode is not sorted for %s" - msgstr "" - --#: config/tc-ppc.c:1726 -+#: config/tc-ppc.c:1728 - #, c-format - msgid "%s is enabled by vle flag" - msgstr "" - --#: config/tc-ppc.c:1733 -+#: config/tc-ppc.c:1735 - #, c-format - msgid "%s not disabled by vle flag" - msgstr "" - --#: config/tc-ppc.c:1839 -+#: config/tc-ppc.c:1841 - #, c-format - msgid "opcode is not sorted for %s" - msgstr "" - --#: config/tc-ppc.c:2257 -+#: config/tc-ppc.c:2259 - #, c-format - msgid "symbol+offset@%s means symbol@%s+offset" - msgstr "" - --#: config/tc-ppc.c:2277 -+#: config/tc-ppc.c:2279 - #, c-format - msgid "symbol+offset@%s not supported" - msgstr "" - --#: config/tc-ppc.c:2356 config/tc-ppc.c:4226 config/tc-ppc.c:7691 -+#: config/tc-ppc.c:2358 config/tc-ppc.c:4228 config/tc-ppc.c:7693 - msgid "data in executable section" - msgstr "" - --#: config/tc-ppc.c:2397 -+#: config/tc-ppc.c:2399 - msgid "expected comma after symbol-name: rest of line ignored." - msgstr "" - --#: config/tc-ppc.c:2430 -+#: config/tc-ppc.c:2432 - #, c-format - msgid "ignoring attempt to re-define symbol `%s'." - msgstr "" - --#: config/tc-ppc.c:2438 -+#: config/tc-ppc.c:2440 - #, c-format - msgid "length of .lcomm \"%s\" is already %ld. Not changed to %ld." - msgstr "" - --#: config/tc-ppc.c:2456 -+#: config/tc-ppc.c:2458 - msgid "common alignment not a power of 2" - msgstr "" - --#: config/tc-ppc.c:2498 -+#: config/tc-ppc.c:2500 - #, c-format - msgid "expected comma after name `%s' in .localentry directive" - msgstr "" - --#: config/tc-ppc.c:2508 -+#: config/tc-ppc.c:2510 - msgid "missing expression in .localentry directive" - msgstr "" - --#: config/tc-ppc.c:2529 -+#: config/tc-ppc.c:2531 - #, c-format - msgid ".localentry expression for `%s' is not a valid power of 2" - msgstr "" - --#: config/tc-ppc.c:2546 -+#: config/tc-ppc.c:2548 - #, c-format - msgid ".localentry expression for `%s' does not evaluate to a constant" - msgstr "" - --#: config/tc-ppc.c:2561 -+#: config/tc-ppc.c:2563 - msgid "missing expression in .abiversion directive" - msgstr "" - --#: config/tc-ppc.c:2570 -+#: config/tc-ppc.c:2572 - msgid ".abiversion expression does not evaluate to a constant" - msgstr "" - --#: config/tc-ppc.c:2650 -+#: config/tc-ppc.c:2652 - msgid "relocation cannot be done when using -mrelocatable" - msgstr "" - --#: config/tc-ppc.c:2696 -+#: config/tc-ppc.c:2698 - msgid "TOC section size exceeds 64k" - msgstr "" - --#: config/tc-ppc.c:3256 -+#: config/tc-ppc.c:3258 - #, c-format - msgid "%s howto doesn't match size/pcrel in gas" - msgstr "" - --#: config/tc-ppc.c:3335 -+#: config/tc-ppc.c:3337 - #, c-format - msgid "unrecognized opcode: `%s'" - msgstr "" - - #. lmw, stmw, lswi, lswx, stswi, stswx --#: config/tc-ppc.c:3346 -+#: config/tc-ppc.c:3348 - #, c-format - msgid "`%s' invalid when little-endian" - msgstr "" - --#: config/tc-ppc.c:3695 -+#: config/tc-ppc.c:3697 - #, c-format - msgid "@tls may not be used with \"%s\" operands" - msgstr "" - --#: config/tc-ppc.c:3698 -+#: config/tc-ppc.c:3700 - msgid "@tls may only be used in last operand" - msgstr "" - --#: config/tc-ppc.c:3736 config/tc-ppc.c:3746 config/tc-ppc.c:3756 --#: config/tc-ppc.c:3771 -+#: config/tc-ppc.c:3738 config/tc-ppc.c:3748 config/tc-ppc.c:3758 -+#: config/tc-ppc.c:3773 - #, c-format - msgid "%s unsupported on this instruction" - msgstr "" - --#: config/tc-ppc.c:3818 -+#: config/tc-ppc.c:3820 - #, c-format - msgid "assuming %s on symbol" - msgstr "" - --#: config/tc-ppc.c:3941 -+#: config/tc-ppc.c:3943 - msgid "unsupported relocation for DS offset field" - msgstr "" - --#: config/tc-ppc.c:3994 -+#: config/tc-ppc.c:3996 - #, c-format - msgid "syntax error; found `%c', expected `%c'" - msgstr "" - --#: config/tc-ppc.c:3999 -+#: config/tc-ppc.c:4001 - #, c-format - msgid "syntax error; end of line, expected `%c'" - msgstr "" - --#: config/tc-ppc.c:4064 config/tc-ppc.c:6865 -+#: config/tc-ppc.c:4066 config/tc-ppc.c:6867 - #, c-format - msgid "instruction address is not a multiple of %d" - msgstr "" - --#: config/tc-ppc.c:4183 -+#: config/tc-ppc.c:4185 - msgid "bad .section directive: want a,e,v,w,x,M,S,G,T in string" - msgstr "" - --#: config/tc-ppc.c:4333 -+#: config/tc-ppc.c:4335 - msgid "missing size" - msgstr "" - --#: config/tc-ppc.c:4342 -+#: config/tc-ppc.c:4344 - msgid "negative size" - msgstr "" - --#: config/tc-ppc.c:4369 -+#: config/tc-ppc.c:4371 - msgid "Unknown visibility field in .comm" - msgstr "" - --#: config/tc-ppc.c:4387 -+#: config/tc-ppc.c:4389 - msgid "missing real symbol name" - msgstr "" - --#: config/tc-ppc.c:4426 -+#: config/tc-ppc.c:4428 - msgid "attempt to redefine symbol" - msgstr "" - --#: config/tc-ppc.c:4735 -+#: config/tc-ppc.c:4737 - #, c-format - msgid "no known dwarf XCOFF section for flag 0x%08x\n" - msgstr "" - --#: config/tc-ppc.c:4748 -+#: config/tc-ppc.c:4750 - #, c-format - msgid "label %s was not defined in this dwarf section" - msgstr "" - --#: config/tc-ppc.c:4862 -+#: config/tc-ppc.c:4864 - msgid "the XCOFF file format does not support arbitrary sections" - msgstr "" - --#: config/tc-ppc.c:4900 -+#: config/tc-ppc.c:4902 - msgid "Unknown visibility field in .extern" - msgstr "" - --#: config/tc-ppc.c:4937 -+#: config/tc-ppc.c:4939 - msgid "Unknown visibility field in .globl" - msgstr "" - --#: config/tc-ppc.c:4974 -+#: config/tc-ppc.c:4976 - msgid "Unknown visibility field in .weak" - msgstr "" - --#: config/tc-ppc.c:5025 -+#: config/tc-ppc.c:5027 - msgid ".ref outside .csect" - msgstr "" - --#: config/tc-ppc.c:5046 config/tc-ppc.c:5306 -+#: config/tc-ppc.c:5048 config/tc-ppc.c:5308 - msgid "missing symbol name" - msgstr "" - --#: config/tc-ppc.c:5076 -+#: config/tc-ppc.c:5078 - msgid "missing rename string" - msgstr "" - --#: config/tc-ppc.c:5106 config/tc-ppc.c:5708 -+#: config/tc-ppc.c:5108 config/tc-ppc.c:5710 - msgid "missing value" - msgstr "" - --#: config/tc-ppc.c:5124 -+#: config/tc-ppc.c:5126 - msgid "illegal .stabx expression; zero assumed" - msgstr "" - --#: config/tc-ppc.c:5156 -+#: config/tc-ppc.c:5158 - msgid "missing class" - msgstr "" - --#: config/tc-ppc.c:5165 -+#: config/tc-ppc.c:5167 - msgid "missing type" - msgstr "" - --#: config/tc-ppc.c:5192 -+#: config/tc-ppc.c:5194 - msgid ".stabx of storage class stsym must be within .bs/.es" - msgstr "" - --#: config/tc-ppc.c:5496 -+#: config/tc-ppc.c:5498 - msgid "nested .bs blocks" - msgstr "" - --#: config/tc-ppc.c:5527 -+#: config/tc-ppc.c:5529 - msgid ".es without preceding .bs" - msgstr "" - --#: config/tc-ppc.c:5700 -+#: config/tc-ppc.c:5702 - msgid "non-constant byte count" - msgstr "" - --#: config/tc-ppc.c:5775 -+#: config/tc-ppc.c:5777 - msgid ".tc not in .toc section" - msgstr "" - --#: config/tc-ppc.c:5793 -+#: config/tc-ppc.c:5795 - msgid ".tc with no label" - msgstr "" - --#: config/tc-ppc.c:5821 -+#: config/tc-ppc.c:5823 - #, c-format - msgid ".tc with storage class %d not yet supported" - msgstr "" - --#: config/tc-ppc.c:5890 config/tc-s390.c:1967 -+#: config/tc-ppc.c:5892 config/tc-s390.c:1967 - msgid ".machine stack overflow" - msgstr "" - --#: config/tc-ppc.c:5897 config/tc-s390.c:1978 -+#: config/tc-ppc.c:5899 config/tc-s390.c:1978 - msgid ".machine stack underflow" - msgstr "" - --#: config/tc-ppc.c:5939 config/tc-s390.c:1990 -+#: config/tc-ppc.c:5941 config/tc-s390.c:1990 - #, c-format - msgid "invalid machine `%s'" - msgstr "" - --#: config/tc-ppc.c:5983 -+#: config/tc-ppc.c:5985 - msgid "bad symbol suffix" - msgstr "" - --#: config/tc-ppc.c:6082 -+#: config/tc-ppc.c:6084 - msgid "unrecognized symbol suffix" - msgstr "" - --#: config/tc-ppc.c:6170 -+#: config/tc-ppc.c:6172 - msgid ".ef with no preceding .function" - msgstr "" - --#: config/tc-ppc.c:6309 -+#: config/tc-ppc.c:6311 - #, c-format - msgid "warning: symbol %s has no csect" - msgstr "" - --#: config/tc-ppc.c:6641 -+#: config/tc-ppc.c:6643 - msgid "symbol in .toc does not match any .tc" - msgstr "" - --#: config/tc-ppc.c:7393 -+#: config/tc-ppc.c:7395 - #, c-format - msgid "%s unsupported as instruction fixup" - msgstr "" - --#: config/tc-ppc.c:7492 -+#: config/tc-ppc.c:7494 - #, c-format - msgid "unsupported relocation against %s" - msgstr "" - --#: config/tc-ppc.c:7654 -+#: config/tc-ppc.c:7656 - #, c-format - msgid "R_TLSML relocation doesn't target a TOC entry named \"_$TLSML\": %s" - msgstr "" - --#: config/tc-ppc.c:7674 -+#: config/tc-ppc.c:7676 - #, c-format - msgid "Gas failure, reloc value %d\n" - msgstr "" -diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h -index aea7d6c2..f599a8a1 100644 ---- a/include/opcode/ppc.h -+++ b/include/opcode/ppc.h -@@ -245,6 +245,13 @@ extern const unsigned int spe2_num_opcodes; - /* Opcode is only supported by 'future' architecture. */ - #define PPC_OPCODE_FUTURE 0x1000000000000ull - -+/* Opcode is supported by Hardware Transactional Memory */ -+#define PPC_OPCODE_HTM 0x2000000000000ull -+ -+/* Opcode is supported by C2000 */ -+#define PPC_OPCODE_C2000 0x4000000000000ull -+ -+ - /* A macro to extract the major opcode from an instruction. */ - #define PPC_OP(i) (((i) >> 26) & 0x3f) - -diff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c -index d97137d8..055dc8f5 100644 ---- a/opcodes/ppc-dis.c -+++ b/opcodes/ppc-dis.c -@@ -196,29 +196,34 @@ struct ppc_mopt ppc_opts[] = { - { "power8", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64 - | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 - | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 -- | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX), -+ | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX | PPC_OPCODE_HTM), - 0 }, - { "power9", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64 - | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 - | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9 -- | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX), -+ | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX | PPC_OPCODE_HTM), - 0 }, - { "power10", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64 - | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 - | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9 -- | PPC_OPCODE_POWER10 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX), -+ | PPC_OPCODE_POWER10 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX | PPC_OPCODE_HTM), - 0 }, - { "libresoc",(PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64 - | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 - | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9 -- | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX | PPC_OPCODE_SVP64), -+ | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX | PPC_OPCODE_SVP64 | PPC_OPCODE_HTM), - 0 }, - { "future", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64 - | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 - | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9 -- | PPC_OPCODE_POWER10 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX -+ | PPC_OPCODE_POWER10 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX | PPC_OPCODE_HTM - | PPC_OPCODE_FUTURE), - 0 }, -+ { "c2000", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64 -+ | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 -+ | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_C2000 -+ | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX), -+ 0 }, - { "ppc", PPC_OPCODE_PPC, - 0 }, - { "ppc32", PPC_OPCODE_PPC, -@@ -255,17 +260,17 @@ struct ppc_mopt ppc_opts[] = { - { "pwr8", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64 - | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 - | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 -- | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX), -+ | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX | PPC_OPCODE_HTM), - 0 }, - { "pwr9", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64 - | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 - | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9 -- | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX), -+ | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX | PPC_OPCODE_HTM), - 0 }, - { "pwr10", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64 - | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 - | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9 -- | PPC_OPCODE_POWER10 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX), -+ | PPC_OPCODE_POWER10 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX | PPC_OPCODE_HTM), - 0 }, - { "pwrx", PPC_OPCODE_POWER | PPC_OPCODE_POWER2, - 0 }, -diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c -index 37f1aeb7..ac92a8f1 100644 ---- a/opcodes/ppc-opc.c -+++ b/opcodes/ppc-opc.c -@@ -5007,7 +5007,7 @@ const unsigned int num_powerpc_operands = ARRAY_SIZE (powerpc_operands); - #define E500 PPC_OPCODE_E500 - #define E6500 PPC_OPCODE_E6500 - #define PPCVLE PPC_OPCODE_VLE --#define PPCHTM PPC_OPCODE_POWER8 -+#define PPCHTM PPC_OPCODE_HTM - #define E200Z4 PPC_OPCODE_E200Z4 - #define PPCLSP PPC_OPCODE_LSP - #define SVP64 PPC_OPCODE_SVP64 --- -2.33.0 - diff --git a/Re-LoongArch-Add-support-for-b-.L1-and-beq-t0-t1-.L1.patch b/Re-LoongArch-Add-support-for-b-.L1-and-beq-t0-t1-.L1.patch deleted file mode 100644 index 17c4e67..0000000 --- a/Re-LoongArch-Add-support-for-b-.L1-and-beq-t0-t1-.L1.patch +++ /dev/null @@ -1,62 +0,0 @@ -From 311282d26b81bbe082f798e7b6100e8ef6f6d6ed Mon Sep 17 00:00:00 2001 -From: Alan Modra -Date: Sun, 24 Dec 2023 14:41:06 +1030 -Subject: [PATCH 024/123] Re: LoongArch: Add support for and - -This fixes the buffer overflow added in commit 22b78fad28, and a few -other problems. - - * loongarch-coder.c (loongarch_split_args_by_comma): Don't - overflow buffer when args == "". Don't remove unbalanced - quotes. Don't trim last arg if max number of args exceeded. ---- - opcodes/loongarch-coder.c | 30 ++++++++++++++++-------------- - 1 file changed, 16 insertions(+), 14 deletions(-) - -diff --git a/opcodes/loongarch-coder.c b/opcodes/loongarch-coder.c -index 672a468b..b6835276 100644 ---- a/opcodes/loongarch-coder.c -+++ b/opcodes/loongarch-coder.c -@@ -255,22 +255,24 @@ loongarch_split_args_by_comma (char *args, const char *arg_strs[]) - size_t num = 0; - - if (*args) -- arg_strs[num++] = args; -- for (; *args; args++) -- if (*args == ',') -- { -- if (MAX_ARG_NUM_PLUS_2 - 1 == num) -- break; -- else -- *args = '\0', arg_strs[num++] = args + 1; -- } -- -- if (*(args-1) == '"') - { -- *(args-1) = '\0'; -- arg_strs[num-1] = arg_strs[num-1] + 1; -- } -+ arg_strs[num++] = args; -+ for (; *args; args++) -+ if (*args == ',') -+ { -+ if (MAX_ARG_NUM_PLUS_2 - 1 == num) -+ goto out; -+ *args = '\0'; -+ arg_strs[num++] = args + 1; -+ } - -+ if (*(args - 1) == '"' && *arg_strs[num - 1] == '"') -+ { -+ *(args - 1) = '\0'; -+ arg_strs[num - 1] += 1; -+ } -+ } -+ out: - arg_strs[num] = NULL; - return num; - } --- -2.33.0 - diff --git a/Re-LoongArch-gas-Adjust-DWARF-CIE-alignment-factors.patch b/Re-LoongArch-gas-Adjust-DWARF-CIE-alignment-factors.patch deleted file mode 100644 index 9b43e82..0000000 --- a/Re-LoongArch-gas-Adjust-DWARF-CIE-alignment-factors.patch +++ /dev/null @@ -1,94 +0,0 @@ -From 2279b12faf8e02e4c3123435008a79ad615781e5 Mon Sep 17 00:00:00 2001 -From: Alan Modra -Date: Thu, 23 May 2024 14:51:31 +0930 -Subject: [PATCH 087/123] Re: LoongArch: gas: Adjust DWARF CIE alignment - factors - -Adjust the gas testsuite to suit commit de203ed568f6. - - * testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.d: - Expect data alignment of -8. Tidy. ---- - .../relax-cfi-fde-DW_CFA_advance_loc.d | 44 +++++++++---------- - 1 file changed, 22 insertions(+), 22 deletions(-) - -diff --git a/gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.d b/gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.d -index d685bd86..6da53b43 100644 ---- a/gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.d -+++ b/gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.d -@@ -5,50 +5,50 @@ - .*:[ ]+file format .* - - --Disassembly of section .eh_frame: -+Disassembly of section \.eh_frame: - --[ ]*0000000000000000 <.eh_frame>: --[ ]+0:[ ]+00000014[ ]+.word[ ]+[ ]+0x00000014 --[ ]+4:[ ]+00000000[ ]+.word[ ]+[ ]+0x00000000 --[ ]+8:[ ]+00527a01[ ]+.word[ ]+[ ]+0x00527a01 --[ ]+c:[ ]+01017c01[ ]+fadd.d[ ]+\$fa1, \$fa0, \$fs7 --[ ]+10:[ ]+0c030d1b[ ]+.word[ ]+[ ]+0x0c030d1b --[ ]+14:[ ]+00000016[ ]+.word[ ]+[ ]+0x00000016 --[ ]+18:[ ]+0000003c[ ]+.word[ ]+[ ]+0x0000003c --[ ]+1c:[ ]+0000001c[ ]+.word[ ]+[ ]+0x0000001c -+[ ]*0000000000000000 <\.eh_frame>: -+[ ]+0:[ ]+00000014[ ].* -+[ ]+4:[ ]+00000000[ ].* -+[ ]+8:[ ]+00527a01[ ].* -+[ ]+c:[ ]+01017801[ ].* -+[ ]+10:[ ]+0c030d1b[ ].* -+[ ]+14:[ ]+00000016[ ].* -+[ ]+18:[ ]+0000003c[ ].* -+[ ]+1c:[ ]+0000001c[ ].* - [ ]+... - [ ]+20: R_LARCH_32_PCREL[ ]+L0\^A - [ ]+24: R_LARCH_ADD32[ ]+L0\^A - [ ]+24: R_LARCH_SUB32[ ]+L0\^A --[ ]+28:[ ]+0cd64000[ ]+.word[ ]+[ ]+0x0cd64000 -+[ ]+28:[ ]+0cd64000[ ].* - [ ]+29: R_LARCH_ADD6[ ]+L0\^A - [ ]+29: R_LARCH_SUB6[ ]+L0\^A --[ ]+2c:[ ]+d6400016[ ]+.word[ ]+[ ]+0xd6400016 -+[ ]+2c:[ ]+d6400016[ ].* - [ ]+2e: R_LARCH_ADD6[ ]+L0\^A - [ ]+2e: R_LARCH_SUB6[ ]+L0\^A --[ ]+30:[ ]+4000160c[ ]+beqz[ ]+\$t4, 3145748[ ]+# 300044 -+[ ]+30:[ ]+4000160c[ ].* - [ ]+33: R_LARCH_ADD6[ ]+L0\^A - [ ]+33: R_LARCH_SUB6[ ]+L0\^A --[ ]+34:[ ]+00160cd6[ ]+orn[ ]+\$fp, \$a2, \$sp --[ ]+38:[ ]+160cd640[ ]+lu32i.d[ ]+\$zero, 26290 -+[ ]+34:[ ]+00160cd6[ ].* -+[ ]+38:[ ]+160cd640[ ].* - [ ]+38: R_LARCH_ADD6[ ]+L0\^A - [ ]+38: R_LARCH_SUB6[ ]+L0\^A --[ ]+3c:[ ]+0cd64000[ ]+.word[ ]+[ ]+0x0cd64000 -+[ ]+3c:[ ]+0cd64000[ ].* - [ ]+3d: R_LARCH_ADD6[ ]+L0\^A - [ ]+3d: R_LARCH_SUB6[ ]+L0\^A --[ ]+40:[ ]+d6400016[ ]+.word[ ]+[ ]+0xd6400016 -+[ ]+40:[ ]+d6400016[ ].* - [ ]+42: R_LARCH_ADD6[ ]+L0\^A - [ ]+42: R_LARCH_SUB6[ ]+L0\^A --[ ]+44:[ ]+4000160c[ ]+beqz[ ]+\$t4, 3145748[ ]+# 300058 -+[ ]+44:[ ]+4000160c[ ].* - [ ]+47: R_LARCH_ADD6[ ]+L0\^A - [ ]+47: R_LARCH_SUB6[ ]+L0\^A --[ ]+48:[ ]+00160cd6[ ]+orn[ ]+\$fp, \$a2, \$sp --[ ]+4c:[ ]+160cd640[ ]+lu32i.d[ ]+\$zero, 26290 -+[ ]+48:[ ]+00160cd6[ ].* -+[ ]+4c:[ ]+160cd640[ ].* - [ ]+4c: R_LARCH_ADD6[ ]+L0\^A - [ ]+4c: R_LARCH_SUB6[ ]+L0\^A --[ ]+50:[ ]+0cd64000[ ]+.word[ ]+[ ]+0x0cd64000 -+[ ]+50:[ ]+0cd64000[ ].* - [ ]+51: R_LARCH_ADD6[ ]+L0\^A - [ ]+51: R_LARCH_SUB6[ ]+L0\^A --[ ]+54:[ ]+d6400016[ ]+.word[ ]+[ ]+0xd6400016 -+[ ]+54:[ ]+d6400016[ ].* - [ ]+56: R_LARCH_ADD6[ ]+L0\^A - [ ]+56: R_LARCH_SUB6[ ]+L0\^A --- -2.33.0 - diff --git a/Sw64-binutils-Add-Sw64-support.patch b/Sw64-binutils-Add-Sw64-support.patch deleted file mode 100644 index d531424..0000000 --- a/Sw64-binutils-Add-Sw64-support.patch +++ /dev/null @@ -1,20973 +0,0 @@ -diff --git a/Makefile.in b/Makefile.in -index 38f1f9ab..b0fa1958 100644 ---- a/Makefile.in -+++ b/Makefile.in -@@ -701,6 +701,7 @@ all: - #### host and target specific makefile fragments come in here. - @target_makefile_frag@ - @alphaieee_frag@ -+@sw_64ieee_frag@ - @ospace_frag@ - @host_makefile_frag@ - ### -diff --git a/Makefile.tpl b/Makefile.tpl -index 88db8f44..9cea1974 100644 ---- a/Makefile.tpl -+++ b/Makefile.tpl -@@ -624,6 +624,7 @@ all: - #### host and target specific makefile fragments come in here. - @target_makefile_frag@ - @alphaieee_frag@ -+@sw_64ieee_frag@ - @ospace_frag@ - @host_makefile_frag@ - ### -diff --git a/bfd/Makefile.am b/bfd/Makefile.am -index 5c5fdefd..4009f0a2 100644 ---- a/bfd/Makefile.am -+++ b/bfd/Makefile.am -@@ -97,6 +97,7 @@ BFD64_LIBS_CFILES = archive64.c - ALL_MACHINES = \ - cpu-aarch64.lo \ - cpu-alpha.lo \ -+ cpu-sw_64.lo \ - cpu-amdgcn.lo \ - cpu-arc.lo \ - cpu-arm.lo \ -@@ -180,6 +181,7 @@ ALL_MACHINES = \ - ALL_MACHINES_CFILES = \ - cpu-aarch64.c \ - cpu-alpha.c \ -+ cpu-sw_64.c \ - cpu-amdgcn.c \ - cpu-arc.c \ - cpu-arm.c \ -@@ -543,6 +545,7 @@ BFD64_BACKENDS = \ - aix5ppc-core.lo \ - aout64.lo \ - coff-alpha.lo \ -+ coff-sw_64.lo \ - coff-x86_64.lo \ - coff64-rs6000.lo \ - elf32-ia64.lo \ -@@ -550,6 +553,7 @@ BFD64_BACKENDS = \ - elf32-score.lo \ - elf32-score7.lo \ - elf64-alpha.lo \ -+ elf64-sw_64.lo \ - elf64-amdgcn.lo \ - elf64-gen.lo \ - elf64-hppa.lo \ -@@ -594,12 +598,14 @@ BFD64_BACKENDS_CFILES = \ - aix5ppc-core.c \ - aout64.c \ - coff-alpha.c \ -+ coff-sw_64.c \ - coff-x86_64.c \ - coff64-rs6000.c \ - elf32-mips.c \ - elf32-score.c \ - elf32-score7.c \ - elf64-alpha.c \ -+ elf64-sw_64.c \ - elf64-amdgcn.c \ - elf64-gen.c \ - elf64-hppa.c \ -diff --git a/bfd/Makefile.in b/bfd/Makefile.in -index 4edfedee..e929a9e4 100644 ---- a/bfd/Makefile.in -+++ b/bfd/Makefile.in -@@ -552,6 +552,7 @@ BFD64_LIBS_CFILES = archive64.c - ALL_MACHINES = \ - cpu-aarch64.lo \ - cpu-alpha.lo \ -+ cpu-sw_64.lo \ - cpu-amdgcn.lo \ - cpu-arc.lo \ - cpu-arm.lo \ -@@ -635,6 +636,7 @@ ALL_MACHINES = \ - ALL_MACHINES_CFILES = \ - cpu-aarch64.c \ - cpu-alpha.c \ -+ cpu-sw_64.c \ - cpu-amdgcn.c \ - cpu-arc.c \ - cpu-arm.c \ -@@ -1000,6 +1002,7 @@ BFD64_BACKENDS = \ - aix5ppc-core.lo \ - aout64.lo \ - coff-alpha.lo \ -+ coff-sw_64.lo \ - coff-x86_64.lo \ - coff64-rs6000.lo \ - elf32-ia64.lo \ -@@ -1007,6 +1010,7 @@ BFD64_BACKENDS = \ - elf32-score.lo \ - elf32-score7.lo \ - elf64-alpha.lo \ -+ elf64-sw_64.lo \ - elf64-amdgcn.lo \ - elf64-gen.lo \ - elf64-hppa.lo \ -@@ -1051,12 +1055,14 @@ BFD64_BACKENDS_CFILES = \ - aix5ppc-core.c \ - aout64.c \ - coff-alpha.c \ -+ coff-sw_64.c \ - coff-x86_64.c \ - coff64-rs6000.c \ - elf32-mips.c \ - elf32-score.c \ - elf32-score7.c \ - elf64-alpha.c \ -+ elf64-sw_64.c \ - elf64-amdgcn.c \ - elf64-gen.c \ - elf64-hppa.c \ -@@ -1439,6 +1445,7 @@ distclean-compile: - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cf-i386lynx.Plo@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cisco-core.Plo@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/coff-alpha.Plo@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/coff-sw_64.Plo@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/coff-bfd.Plo@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/coff-go32.Plo@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/coff-i386.Plo@am__quote@ -@@ -1459,6 +1466,7 @@ distclean-compile: - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/corefile.Plo@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-aarch64.Plo@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-alpha.Plo@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-sw_64.Plo@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-amdgcn.Plo@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-arc.Plo@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-arm.Plo@am__quote@ -@@ -1623,6 +1631,7 @@ distclean-compile: - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32.Plo@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-aarch64.Plo@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-alpha.Plo@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-sw_64.Plo@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-amdgcn.Plo@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-bpf.Plo@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-gen.Plo@am__quote@ -diff --git a/bfd/archures.c b/bfd/archures.c -index 5a2a76c3..a968c687 100644 ---- a/bfd/archures.c -+++ b/bfd/archures.c -@@ -24,6 +24,9 @@ - #include "libbfd.h" - #include "safe-ctype.h" - -+/* add sw_64 target -+ * add cpu sw6a-1621, sw6b-3231. */ -+ - /* - - SECTION -@@ -303,6 +306,11 @@ DESCRIPTION - .#define bfd_mach_alpha_ev4 0x10 - .#define bfd_mach_alpha_ev5 0x20 - .#define bfd_mach_alpha_ev6 0x30 -+.#ifdef TARGET_SW_64 -+. bfd_arch_sw_64, {* Sw_64 *} -+.#define bfd_mach_sw_64_sw6a 4 -+.#define bfd_mach_sw_64_sw6b 8 -+.#endif - . bfd_arch_arm, {* Advanced Risc Machines ARM. *} - .#define bfd_mach_arm_unknown 0 - .#define bfd_mach_arm_2 1 -@@ -619,6 +627,7 @@ DESCRIPTION - - extern const bfd_arch_info_type bfd_aarch64_arch; - extern const bfd_arch_info_type bfd_alpha_arch; -+extern const bfd_arch_info_type bfd_sw_64_arch; - extern const bfd_arch_info_type bfd_amdgcn_arch; - extern const bfd_arch_info_type bfd_arc_arch; - extern const bfd_arch_info_type bfd_arm_arch; -@@ -707,6 +716,9 @@ static const bfd_arch_info_type * const bfd_archures_list[] = - #else - &bfd_aarch64_arch, - &bfd_alpha_arch, -+#ifdef TARGET_SW_64 -+ &bfd_sw_64_arch, -+#endif - &bfd_amdgcn_arch, - &bfd_arc_arch, - &bfd_arm_arch, -diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h -index b34c8ef9..12dac144 100644 ---- a/bfd/bfd-in2.h -+++ b/bfd/bfd-in2.h -@@ -1556,6 +1556,12 @@ enum bfd_architecture - #define bfd_mach_alpha_ev4 0x10 - #define bfd_mach_alpha_ev5 0x20 - #define bfd_mach_alpha_ev6 0x30 -+#ifdef TARGET_SW_64 -+ bfd_arch_sw_64, /* Sw_64 */ -+#define bfd_mach_sw_64_sw6a 4 -+#define bfd_mach_sw_64_sw6b 8 -+#define bfd_mach_sw_64_sw8a 12 -+#endif - bfd_arch_arm, /* Advanced Risc Machines ARM. */ - #define bfd_mach_arm_unknown 0 - #define bfd_mach_arm_2 1 -@@ -3523,6 +3529,111 @@ between two procedure entry points is < 2^21, or else a hint. */ - BFD_RELOC_ALPHA_TPREL_LO16, - BFD_RELOC_ALPHA_TPREL16, - -+#ifdef TARGET_SW_64 -+/* Sw_64 ECOFF and ELF relocations. Some of these treat the symbol or -+"addend" in some special way. -+For GPDISP_HI16 ("gpdisp") relocations, the symbol is ignored when -+writing; when reading, it will be the absolute section symbol. The -+addend is the displacement in bytes of the "lda" instruction from -+the "ldah" instruction (which is at the address of this reloc). */ -+ BFD_RELOC_SW_64_GPDISP_HI16, -+ -+/* For GPDISP_LO16 ("ignore") relocations, the symbol is handled as -+with GPDISP_HI16 relocs. The addend is ignored when writing the -+relocations out, and is filled in with the file's GP value on -+reading, for convenience. */ -+ BFD_RELOC_SW_64_GPDISP_LO16, -+ -+/* The ELF GPDISP relocation is exactly the same as the GPDISP_HI16 -+relocation except that there is no accompanying GPDISP_LO16 -+relocation. */ -+ BFD_RELOC_SW_64_GPDISP, -+ -+/* The Sw_64 LITERAL/LITUSE relocs are produced by a symbol reference; -+the assembler turns it into a LDQ instruction to load the address of -+the symbol, and then fills in a register in the real instruction. -+ -+The LITERAL reloc, at the LDQ instruction, refers to the .lita -+section symbol. The addend is ignored when writing, but is filled -+in with the file's GP value on reading, for convenience, as with the -+GPDISP_LO16 reloc. -+ -+The ELF_LITERAL reloc is somewhere between 16_GOTOFF and GPDISP_LO16. -+It should refer to the symbol to be referenced, as with 16_GOTOFF, -+but it generates output not based on the position within the .got -+section, but relative to the GP value chosen for the file during the -+final link stage. -+ -+The LITUSE reloc, on the instruction using the loaded address, gives -+information to the linker that it might be able to use to optimize -+away some literal section references. The symbol is ignored (read -+as the absolute section symbol), and the "addend" indicates the type -+of instruction using the register: -+1 - "memory" fmt insn -+2 - byte-manipulation (byte offset reg) -+3 - jsr (target of branch) */ -+ BFD_RELOC_SW_64_LITERAL, -+ BFD_RELOC_SW_64_ELF_LITERAL, -+ BFD_RELOC_SW_64_ELF_LITERAL_GOT, -+ BFD_RELOC_SW_64_LITUSE, -+ -+/* The HINT relocation indicates a value that should be filled into the -+"hint" field of a jmp/jsr/ret instruction, for possible branch- -+prediction logic which may be provided on some processors. */ -+ BFD_RELOC_SW_64_HINT, -+ -+/* The LINKAGE relocation outputs a linkage pair in the object file, -+which is filled by the linker. */ -+ BFD_RELOC_SW_64_LINKAGE, -+ -+/* The CODEADDR relocation outputs a STO_CA in the object file, -+which is filled by the linker. */ -+ BFD_RELOC_SW_64_CODEADDR, -+ -+/* The GPREL_HI/LO relocations together form a 32-bit offset from the -+GP register. */ -+ BFD_RELOC_SW_64_GPREL_HI16, -+ BFD_RELOC_SW_64_GPREL_LO16, -+ -+/* Like BFD_RELOC_23_PCREL_S2, except that the source and target must -+share a common GP, and the target address is adjusted for -+STO_SW_64_STD_GPLOAD. */ -+ BFD_RELOC_SW_64_BRSGP, -+ -+/* The NOP relocation outputs a NOP if the longword displacement -+between two procedure entry points is < 2^21. */ -+ BFD_RELOC_SW_64_NOP, -+ -+/* The BSR relocation outputs a BSR if the longword displacement -+between two procedure entry points is < 2^21. */ -+ BFD_RELOC_SW_64_BSR, -+ -+/* The LDA relocation outputs a LDA if the longword displacement -+between two procedure entry points is < 2^16. */ -+ BFD_RELOC_SW_64_LDA, -+ -+/* The BOH relocation outputs a BSR if the longword displacement -+between two procedure entry points is < 2^21, or else a hint. */ -+ BFD_RELOC_SW_64_BOH, -+ -+/* Sw_64 thread-local storage relocations. */ -+ BFD_RELOC_SW_64_TLSGD, -+ BFD_RELOC_SW_64_TLSLDM, -+ BFD_RELOC_SW_64_DTPMOD64, -+ BFD_RELOC_SW_64_GOTDTPREL16, -+ BFD_RELOC_SW_64_DTPREL64, -+ BFD_RELOC_SW_64_DTPREL_HI16, -+ BFD_RELOC_SW_64_DTPREL_LO16, -+ BFD_RELOC_SW_64_DTPREL16, -+ BFD_RELOC_SW_64_GOTTPREL16, -+ BFD_RELOC_SW_64_TPREL64, -+ BFD_RELOC_SW_64_TPREL_HI16, -+ BFD_RELOC_SW_64_TPREL_LO16, -+ BFD_RELOC_SW_64_TPREL16, -+ BFD_RELOC_SW_64_TLSREL_GOT, -+ BFD_RELOC_SW_64_BR26, -+#endif -+ - /* The MIPS jump instruction. */ - BFD_RELOC_MIPS_JMP, - BFD_RELOC_MICROMIPS_JMP, -diff --git a/bfd/coff-sw_64.c b/bfd/coff-sw_64.c -new file mode 100644 -index 00000000..c5d515a5 ---- /dev/null -+++ b/bfd/coff-sw_64.c -@@ -0,0 +1,2459 @@ -+/* BFD back-end for SW_64 Extended-Coff files. -+ Copyright (C) 1993-2023 Free Software Foundation, Inc. -+ Modified from coff-mips.c by Steve Chamberlain and -+ Ian Lance Taylor . -+ -+ This file is part of BFD, the Binary File Descriptor library. -+ -+ This program is free software; you can redistribute it and/or modify -+ it under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 3 of the License, or -+ (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ GNU General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, -+ MA 02110-1301, USA. */ -+ -+#include "sysdep.h" -+#include "bfd.h" -+#include "bfdlink.h" -+#include "libbfd.h" -+#include "coff/internal.h" -+#include "coff/sym.h" -+#include "coff/symconst.h" -+#include "coff/ecoff.h" -+#include "coff/sw_64.h" -+#include "aout/ar.h" -+#include "libcoff.h" -+#include "libecoff.h" -+ -+/* Prototypes for static functions. */ -+ -+/* ECOFF has COFF sections, but the debugging information is stored in -+ a completely different format. ECOFF targets use some of the -+ swapping routines from coffswap.h, and some of the generic COFF -+ routines in coffgen.c, but, unlike the real COFF targets, do not -+ use coffcode.h itself. -+ -+ Get the generic COFF swapping routines, except for the reloc, -+ symbol, and lineno ones. Give them ecoff names. Define some -+ accessor macros for the large sizes used for SW_64 ECOFF. */ -+ -+#define GET_FILEHDR_SYMPTR H_GET_64 -+#define PUT_FILEHDR_SYMPTR H_PUT_64 -+#define GET_AOUTHDR_TSIZE H_GET_64 -+#define PUT_AOUTHDR_TSIZE H_PUT_64 -+#define GET_AOUTHDR_DSIZE H_GET_64 -+#define PUT_AOUTHDR_DSIZE H_PUT_64 -+#define GET_AOUTHDR_BSIZE H_GET_64 -+#define PUT_AOUTHDR_BSIZE H_PUT_64 -+#define GET_AOUTHDR_ENTRY H_GET_64 -+#define PUT_AOUTHDR_ENTRY H_PUT_64 -+#define GET_AOUTHDR_TEXT_START H_GET_64 -+#define PUT_AOUTHDR_TEXT_START H_PUT_64 -+#define GET_AOUTHDR_DATA_START H_GET_64 -+#define PUT_AOUTHDR_DATA_START H_PUT_64 -+#define GET_SCNHDR_PADDR H_GET_64 -+#define PUT_SCNHDR_PADDR H_PUT_64 -+#define GET_SCNHDR_VADDR H_GET_64 -+#define PUT_SCNHDR_VADDR H_PUT_64 -+#define GET_SCNHDR_SIZE H_GET_64 -+#define PUT_SCNHDR_SIZE H_PUT_64 -+#define GET_SCNHDR_SCNPTR H_GET_64 -+#define PUT_SCNHDR_SCNPTR H_PUT_64 -+#define GET_SCNHDR_RELPTR H_GET_64 -+#define PUT_SCNHDR_RELPTR H_PUT_64 -+#define GET_SCNHDR_LNNOPTR H_GET_64 -+#define PUT_SCNHDR_LNNOPTR H_PUT_64 -+ -+#define SW_64ECOFF -+ -+#define NO_COFF_RELOCS -+#define NO_COFF_SYMBOLS -+#define NO_COFF_LINENOS -+#define coff_swap_filehdr_in sw_64_ecoff_swap_filehdr_in -+#define coff_swap_filehdr_out sw_64_ecoff_swap_filehdr_out -+#define coff_swap_aouthdr_in sw_64_ecoff_swap_aouthdr_in -+#define coff_swap_aouthdr_out sw_64_ecoff_swap_aouthdr_out -+#define coff_swap_scnhdr_in sw_64_ecoff_swap_scnhdr_in -+#define coff_swap_scnhdr_out sw_64_ecoff_swap_scnhdr_out -+#include "coffswap.h" -+ -+/* Get the ECOFF swapping routines. */ -+#define ECOFF_64 -+#include "ecoffswap.h" -+ -+/* How to process the various reloc types. */ -+ -+static bfd_reloc_status_type -+reloc_nil (bfd *abfd ATTRIBUTE_UNUSED, arelent *reloc ATTRIBUTE_UNUSED, -+ asymbol *sym ATTRIBUTE_UNUSED, void *data ATTRIBUTE_UNUSED, -+ asection *sec ATTRIBUTE_UNUSED, bfd *output_bfd ATTRIBUTE_UNUSED, -+ char **error_message ATTRIBUTE_UNUSED) -+{ -+ return bfd_reloc_ok; -+} -+ -+/* In case we're on a 32-bit machine, construct a 64-bit "-1" value -+ from smaller values. Start with zero, widen, *then* decrement. */ -+#define MINUS_ONE (((bfd_vma) 0) - 1) -+ -+static reloc_howto_type sw_64_howto_table[] = { -+ /* Reloc type 0 is ignored by itself. However, it appears after a -+ GPDISP reloc to identify the location where the low order 16 bits -+ of the gp register are loaded. */ -+ HOWTO (SW_64_R_IGNORE, /* type */ -+ 0, /* rightshift */ -+ 0, /* size (0 = byte, 1 = short, 2 = long) */ -+ 8, /* bitsize */ -+ true, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont, /* complain_on_overflow */ -+ reloc_nil, /* special_function */ -+ "IGNORE", /* name */ -+ true, /* partial_inplace */ -+ 0, /* src_mask */ -+ 0, /* dst_mask */ -+ true), /* pcrel_offset */ -+ -+ /* A 32 bit reference to a symbol. */ -+ HOWTO (SW_64_R_REFLONG, /* type */ -+ 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ 32, /* bitsize */ -+ false, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_bitfield, /* complain_on_overflow */ -+ 0, /* special_function */ -+ "REFLONG", /* name */ -+ true, /* partial_inplace */ -+ 0xffffffff, /* src_mask */ -+ 0xffffffff, /* dst_mask */ -+ false), /* pcrel_offset */ -+ -+ /* A 64 bit reference to a symbol. */ -+ HOWTO (SW_64_R_REFQUAD, /* type */ -+ 0, /* rightshift */ -+ 4, /* size (0 = byte, 1 = short, 2 = long) */ -+ 64, /* bitsize */ -+ false, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_bitfield, /* complain_on_overflow */ -+ 0, /* special_function */ -+ "REFQUAD", /* name */ -+ true, /* partial_inplace */ -+ MINUS_ONE, /* src_mask */ -+ MINUS_ONE, /* dst_mask */ -+ false), /* pcrel_offset */ -+ -+ /* A 32 bit GP relative offset. This is just like REFLONG except -+ that when the value is used the value of the gp register will be -+ added in. */ -+ HOWTO (SW_64_R_GPREL32, /* type */ -+ 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ 32, /* bitsize */ -+ false, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_bitfield, /* complain_on_overflow */ -+ 0, /* special_function */ -+ "GPREL32", /* name */ -+ true, /* partial_inplace */ -+ 0xffffffff, /* src_mask */ -+ 0xffffffff, /* dst_mask */ -+ false), /* pcrel_offset */ -+ -+ /* Used for an instruction that refers to memory off the GP -+ register. The offset is 16 bits of the 32 bit instruction. This -+ reloc always seems to be against the .lita section. */ -+ HOWTO (SW_64_R_LITERAL, /* type */ -+ 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ 16, /* bitsize */ -+ false, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_signed, /* complain_on_overflow */ -+ 0, /* special_function */ -+ "LITERAL", /* name */ -+ true, /* partial_inplace */ -+ 0xffff, /* src_mask */ -+ 0xffff, /* dst_mask */ -+ false), /* pcrel_offset */ -+ -+ /* This reloc only appears immediately following a LITERAL reloc. -+ It identifies a use of the literal. It seems that the linker can -+ use this to eliminate a portion of the .lita section. The symbol -+ index is special: 1 means the literal address is in the base -+ register of a memory format instruction; 2 means the literal -+ address is in the byte offset register of a byte-manipulation -+ instruction; 3 means the literal address is in the target -+ register of a jsr instruction. This does not actually do any -+ relocation. */ -+ HOWTO (SW_64_R_LITUSE, /* type */ -+ 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ 32, /* bitsize */ -+ false, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont, /* complain_on_overflow */ -+ reloc_nil, /* special_function */ -+ "LITUSE", /* name */ -+ false, /* partial_inplace */ -+ 0, /* src_mask */ -+ 0, /* dst_mask */ -+ false), /* pcrel_offset */ -+ -+ /* Load the gp register. This is always used for a ldah instruction -+ which loads the upper 16 bits of the gp register. The next reloc -+ will be an IGNORE reloc which identifies the location of the lda -+ instruction which loads the lower 16 bits. The symbol index of -+ the GPDISP instruction appears to actually be the number of bytes -+ between the ldah and lda instructions. This gives two different -+ ways to determine where the lda instruction is; I don't know why -+ both are used. The value to use for the relocation is the -+ difference between the GP value and the current location; the -+ load will always be done against a register holding the current -+ address. */ -+ HOWTO (SW_64_R_GPDISP, /* type */ -+ 16, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ 16, /* bitsize */ -+ true, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont, /* complain_on_overflow */ -+ reloc_nil, /* special_function */ -+ "GPDISP", /* name */ -+ true, /* partial_inplace */ -+ 0xffff, /* src_mask */ -+ 0xffff, /* dst_mask */ -+ true), /* pcrel_offset */ -+ -+ /* A 21 bit branch. The native assembler generates these for -+ branches within the text segment, and also fills in the PC -+ relative offset in the instruction. */ -+ HOWTO (SW_64_R_BRADDR, /* type */ -+ 2, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ 21, /* bitsize */ -+ true, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_signed, /* complain_on_overflow */ -+ 0, /* special_function */ -+ "BRADDR", /* name */ -+ true, /* partial_inplace */ -+ 0x1fffff, /* src_mask */ -+ 0x1fffff, /* dst_mask */ -+ false), /* pcrel_offset */ -+ -+ /* A 26 bit branch. The native assembler generates these for -+ branches within the text segment, and also fills in the PC -+ relative offset in the instruction. */ -+ HOWTO (SW_64_R_BR26ADDR, /* type */ -+ 2, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ 26, /* bitsize */ -+ true, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_signed, /* complain_on_overflow */ -+ 0, /* special_function */ -+ "BR26ADDR", /* name */ -+ true, /* partial_inplace */ -+ 0x3ffffff, /* src_mask */ -+ 0x3ffffff, /* dst_mask */ -+ false), /* pcrel_offset */ -+ -+ /* A hint for a jump to a register. */ -+ HOWTO (SW_64_R_HINT, /* type */ -+ 2, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ 14, /* bitsize */ -+ true, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont, /* complain_on_overflow */ -+ 0, /* special_function */ -+ "HINT", /* name */ -+ true, /* partial_inplace */ -+ 0x3fff, /* src_mask */ -+ 0x3fff, /* dst_mask */ -+ false), /* pcrel_offset */ -+ -+ /* 16 bit PC relative offset. */ -+ HOWTO (SW_64_R_SREL16, /* type */ -+ 0, /* rightshift */ -+ 1, /* size (0 = byte, 1 = short, 2 = long) */ -+ 16, /* bitsize */ -+ true, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_signed, /* complain_on_overflow */ -+ 0, /* special_function */ -+ "SREL16", /* name */ -+ true, /* partial_inplace */ -+ 0xffff, /* src_mask */ -+ 0xffff, /* dst_mask */ -+ false), /* pcrel_offset */ -+ -+ /* 32 bit PC relative offset. */ -+ HOWTO (SW_64_R_SREL32, /* type */ -+ 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ 32, /* bitsize */ -+ true, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_signed, /* complain_on_overflow */ -+ 0, /* special_function */ -+ "SREL32", /* name */ -+ true, /* partial_inplace */ -+ 0xffffffff, /* src_mask */ -+ 0xffffffff, /* dst_mask */ -+ false), /* pcrel_offset */ -+ -+ /* A 64 bit PC relative offset. */ -+ HOWTO (SW_64_R_SREL64, /* type */ -+ 0, /* rightshift */ -+ 4, /* size (0 = byte, 1 = short, 2 = long) */ -+ 64, /* bitsize */ -+ true, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_signed, /* complain_on_overflow */ -+ 0, /* special_function */ -+ "SREL64", /* name */ -+ true, /* partial_inplace */ -+ MINUS_ONE, /* src_mask */ -+ MINUS_ONE, /* dst_mask */ -+ false), /* pcrel_offset */ -+ -+ /* Push a value on the reloc evaluation stack. */ -+ HOWTO (SW_64_R_OP_PUSH, /* type */ -+ 0, /* rightshift */ -+ 0, /* size (0 = byte, 1 = short, 2 = long) */ -+ 0, /* bitsize */ -+ false, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont, /* complain_on_overflow */ -+ 0, /* special_function */ -+ "OP_PUSH", /* name */ -+ false, /* partial_inplace */ -+ 0, /* src_mask */ -+ 0, /* dst_mask */ -+ false), /* pcrel_offset */ -+ -+ /* Store the value from the stack at the given address. Store it in -+ a bitfield of size r_size starting at bit position r_offset. */ -+ HOWTO (SW_64_R_OP_STORE, /* type */ -+ 0, /* rightshift */ -+ 4, /* size (0 = byte, 1 = short, 2 = long) */ -+ 64, /* bitsize */ -+ false, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont, /* complain_on_overflow */ -+ 0, /* special_function */ -+ "OP_STORE", /* name */ -+ false, /* partial_inplace */ -+ 0, /* src_mask */ -+ MINUS_ONE, /* dst_mask */ -+ false), /* pcrel_offset */ -+ -+ /* Subtract the reloc address from the value on the top of the -+ relocation stack. */ -+ HOWTO (SW_64_R_OP_PSUB, /* type */ -+ 0, /* rightshift */ -+ 0, /* size (0 = byte, 1 = short, 2 = long) */ -+ 0, /* bitsize */ -+ false, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont, /* complain_on_overflow */ -+ 0, /* special_function */ -+ "OP_PSUB", /* name */ -+ false, /* partial_inplace */ -+ 0, /* src_mask */ -+ 0, /* dst_mask */ -+ false), /* pcrel_offset */ -+ -+ /* Shift the value on the top of the relocation stack right by the -+ given value. */ -+ HOWTO (SW_64_R_OP_PRSHIFT, /* type */ -+ 0, /* rightshift */ -+ 0, /* size (0 = byte, 1 = short, 2 = long) */ -+ 0, /* bitsize */ -+ false, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont, /* complain_on_overflow */ -+ 0, /* special_function */ -+ "OP_PRSHIFT", /* name */ -+ false, /* partial_inplace */ -+ 0, /* src_mask */ -+ 0, /* dst_mask */ -+ false), /* pcrel_offset */ -+ -+ /* Adjust the GP value for a new range in the object file. */ -+ HOWTO (SW_64_R_GPVALUE, /* type */ -+ 0, /* rightshift */ -+ 0, /* size (0 = byte, 1 = short, 2 = long) */ -+ 0, /* bitsize */ -+ false, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont, /* complain_on_overflow */ -+ 0, /* special_function */ -+ "GPVALUE", /* name */ -+ false, /* partial_inplace */ -+ 0, /* src_mask */ -+ 0, /* dst_mask */ -+ false) /* pcrel_offset */ -+}; -+ -+/* Recognize an SW_64 ECOFF file. */ -+ -+static bfd_cleanup -+sw_64_ecoff_object_p (bfd *abfd) -+{ -+ bfd_cleanup ret; -+ -+ ret = coff_object_p (abfd); -+ -+ if (ret != NULL) -+ { -+ asection *sec; -+ -+ /* SW_64 ECOFF has a .pdata section. The lnnoptr field of the -+ .pdata section is the number of entries it contains. Each -+ entry takes up 8 bytes. The number of entries is required -+ since the section is aligned to a 16 byte boundary. When we -+ link .pdata sections together, we do not want to include the -+ alignment bytes. We handle this on input by faking the size -+ of the .pdata section to remove the unwanted alignment bytes. -+ On output we will set the lnnoptr field and force the -+ alignment. */ -+ sec = bfd_get_section_by_name (abfd, _PDATA); -+ if (sec != (asection *) NULL) -+ { -+ bfd_size_type size; -+ -+ size = (bfd_size_type) sec->line_filepos * 8; -+ BFD_ASSERT (size == sec->size || size + 8 == sec->size); -+ if (!bfd_set_section_size (sec, size)) -+ return NULL; -+ } -+ } -+ -+ return ret; -+} -+ -+/* See whether the magic number matches. */ -+ -+static bool -+sw_64_ecoff_bad_format_hook (bfd *abfd ATTRIBUTE_UNUSED, void *filehdr) -+{ -+ struct internal_filehdr *internal_f = (struct internal_filehdr *) filehdr; -+ -+ if (!SW_64_ECOFF_BADMAG (*internal_f)) -+ return true; -+ -+ if (SW_64_ECOFF_COMPRESSEDMAG (*internal_f)) -+ _bfd_error_handler ( -+ _ ("%pB: cannot handle compressed SW_64 binaries; " -+ "use compiler flags, or objZ, to generate uncompressed binaries"), -+ abfd); -+ -+ return false; -+} -+ -+/* This is a hook called by coff_real_object_p to create any backend -+ specific information. */ -+ -+static void * -+sw_64_ecoff_mkobject_hook (bfd *abfd, void *filehdr, void *aouthdr) -+{ -+ void *ecoff; -+ -+ ecoff = _bfd_ecoff_mkobject_hook (abfd, filehdr, aouthdr); -+ -+ if (ecoff != NULL) -+ { -+ struct internal_filehdr *internal_f = (struct internal_filehdr *) filehdr; -+ -+ /* Set additional BFD flags according to the object type from the -+ machine specific file header flags. */ -+ switch (internal_f->f_flags & F_SW_64_OBJECT_TYPE_MASK) -+ { -+ case F_SW_64_SHARABLE: -+ abfd->flags |= DYNAMIC; -+ break; -+ case F_SW_64_CALL_SHARED: -+ /* Always executable if using shared libraries as the run time -+ loader might resolve undefined references. */ -+ abfd->flags |= (DYNAMIC | EXEC_P); -+ break; -+ } -+ } -+ return ecoff; -+} -+ -+/* Reloc handling. */ -+ -+/* Swap a reloc in. */ -+ -+static void -+sw_64_ecoff_swap_reloc_in (bfd *abfd, void *ext_ptr, -+ struct internal_reloc *intern) -+{ -+ const RELOC *ext = (RELOC *) ext_ptr; -+ -+ intern->r_vaddr = H_GET_64 (abfd, ext->r_vaddr); -+ intern->r_symndx = H_GET_32 (abfd, ext->r_symndx); -+ -+ BFD_ASSERT (bfd_header_little_endian (abfd)); -+ -+ intern->r_type = ((ext->r_bits[0] & RELOC_BITS0_TYPE_LITTLE) -+ >> RELOC_BITS0_TYPE_SH_LITTLE); -+ intern->r_extern = (ext->r_bits[1] & RELOC_BITS1_EXTERN_LITTLE) != 0; -+ intern->r_offset = ((ext->r_bits[1] & RELOC_BITS1_OFFSET_LITTLE) -+ >> RELOC_BITS1_OFFSET_SH_LITTLE); -+ /* Ignored the reserved bits. */ -+ intern->r_size = ((ext->r_bits[3] & RELOC_BITS3_SIZE_LITTLE) -+ >> RELOC_BITS3_SIZE_SH_LITTLE); -+ -+ if (intern->r_type == SW_64_R_LITUSE || intern->r_type == SW_64_R_GPDISP) -+ { -+ /* Handle the LITUSE and GPDISP relocs specially. Its symndx -+ value is not actually a symbol index, but is instead a -+ special code. We put the code in the r_size field, and -+ clobber the symndx. */ -+ if (intern->r_size != 0) -+ abort (); -+ intern->r_size = intern->r_symndx; -+ intern->r_symndx = RELOC_SECTION_NONE; -+ } -+ else if (intern->r_type == SW_64_R_IGNORE) -+ { -+ /* The IGNORE reloc generally follows a GPDISP reloc, and is -+ against the .lita section. The section is irrelevant. */ -+ if (!intern->r_extern && intern->r_symndx == RELOC_SECTION_ABS) -+ abort (); -+ if (!intern->r_extern && intern->r_symndx == RELOC_SECTION_LITA) -+ intern->r_symndx = RELOC_SECTION_ABS; -+ } -+} -+ -+/* Swap a reloc out. */ -+ -+static void -+sw_64_ecoff_swap_reloc_out (bfd *abfd, const struct internal_reloc *intern, -+ void *dst) -+{ -+ RELOC *ext = (RELOC *) dst; -+ long symndx; -+ unsigned char size; -+ -+ /* Undo the hackery done in swap_reloc_in. */ -+ if (intern->r_type == SW_64_R_LITUSE || intern->r_type == SW_64_R_GPDISP) -+ { -+ symndx = intern->r_size; -+ size = 0; -+ } -+ else if (intern->r_type == SW_64_R_IGNORE && !intern->r_extern -+ && intern->r_symndx == RELOC_SECTION_ABS) -+ { -+ symndx = RELOC_SECTION_LITA; -+ size = intern->r_size; -+ } -+ else -+ { -+ symndx = intern->r_symndx; -+ size = intern->r_size; -+ } -+ -+ /* XXX FIXME: The maximum symndx value used to be 14 but this -+ fails with object files produced by DEC's C++ compiler. -+ Where does the value 14 (or 15) come from anyway ? */ -+ BFD_ASSERT (intern->r_extern -+ || (intern->r_symndx >= 0 && intern->r_symndx <= 15)); -+ -+ H_PUT_64 (abfd, intern->r_vaddr, ext->r_vaddr); -+ H_PUT_32 (abfd, symndx, ext->r_symndx); -+ -+ BFD_ASSERT (bfd_header_little_endian (abfd)); -+ -+ ext->r_bits[0] = ((intern->r_type << RELOC_BITS0_TYPE_SH_LITTLE) -+ & RELOC_BITS0_TYPE_LITTLE); -+ ext->r_bits[1] = ((intern->r_extern ? RELOC_BITS1_EXTERN_LITTLE : 0) -+ | ((intern->r_offset << RELOC_BITS1_OFFSET_SH_LITTLE) -+ & RELOC_BITS1_OFFSET_LITTLE)); -+ ext->r_bits[2] = 0; -+ ext->r_bits[3] -+ = ((size << RELOC_BITS3_SIZE_SH_LITTLE) & RELOC_BITS3_SIZE_LITTLE); -+} -+ -+/* Finish canonicalizing a reloc. Part of this is generic to all -+ ECOFF targets, and that part is in ecoff.c. The rest is done in -+ this backend routine. It must fill in the howto field. */ -+ -+static void -+sw_64_adjust_reloc_in (bfd *abfd, const struct internal_reloc *intern, -+ arelent *rptr) -+{ -+ if (intern->r_type > SW_64_R_GPVALUE) -+ { -+ /* xgettext:c-format */ -+ _bfd_error_handler (_ ("%pB: unsupported relocation type %#x"), abfd, -+ intern->r_type); -+ bfd_set_error (bfd_error_bad_value); -+ rptr->addend = 0; -+ rptr->howto = NULL; -+ return; -+ } -+ -+ switch (intern->r_type) -+ { -+ case SW_64_R_BRADDR: -+ case SW_64_R_BR26ADDR: -+ case SW_64_R_SREL16: -+ case SW_64_R_SREL32: -+ case SW_64_R_SREL64: -+ /* This relocs appear to be fully resolved when they are against -+ internal symbols. Against external symbols, BRADDR at least -+ appears to be resolved against the next instruction. */ -+ if (!intern->r_extern) -+ rptr->addend = 0; -+ else -+ rptr->addend = -(intern->r_vaddr + 4); -+ break; -+ -+ case SW_64_R_GPREL32: -+ case SW_64_R_LITERAL: -+ /* Copy the gp value for this object file into the addend, to -+ ensure that we are not confused by the linker. */ -+ if (!intern->r_extern) -+ rptr->addend += ecoff_data (abfd)->gp; -+ break; -+ -+ case SW_64_R_LITUSE: -+ case SW_64_R_GPDISP: -+ /* The LITUSE and GPDISP relocs do not use a symbol, or an -+ addend, but they do use a special code. Put this code in the -+ addend field. */ -+ rptr->addend = intern->r_size; -+ break; -+ -+ case SW_64_R_OP_STORE: -+ /* The STORE reloc needs the size and offset fields. We store -+ them in the addend. */ -+ BFD_ASSERT (intern->r_offset <= 256); -+ rptr->addend = (intern->r_offset << 8) + intern->r_size; -+ break; -+ -+ case SW_64_R_OP_PUSH: -+ case SW_64_R_OP_PSUB: -+ case SW_64_R_OP_PRSHIFT: -+ /* The PUSH, PSUB and PRSHIFT relocs do not actually use an -+ address. I believe that the address supplied is really an -+ addend. */ -+ rptr->addend = intern->r_vaddr; -+ break; -+ -+ case SW_64_R_GPVALUE: -+ /* Set the addend field to the new GP value. */ -+ rptr->addend = intern->r_symndx + ecoff_data (abfd)->gp; -+ break; -+ -+ case SW_64_R_IGNORE: -+ /* If the type is SW_64_R_IGNORE, make sure this is a reference -+ to the absolute section so that the reloc is ignored. For -+ some reason the address of this reloc type is not adjusted by -+ the section vma. We record the gp value for this object file -+ here, for convenience when doing the GPDISP relocation. */ -+ rptr->sym_ptr_ptr = bfd_abs_section_ptr->symbol_ptr_ptr; -+ rptr->address = intern->r_vaddr; -+ rptr->addend = ecoff_data (abfd)->gp; -+ break; -+ -+ default: -+ break; -+ } -+ -+ rptr->howto = &sw_64_howto_table[intern->r_type]; -+} -+ -+/* When writing out a reloc we need to pull some values back out of -+ the addend field into the reloc. This is roughly the reverse of -+ sw_64_adjust_reloc_in, except that there are several changes we do -+ not need to undo. */ -+ -+static void -+sw_64_adjust_reloc_out (bfd *abfd ATTRIBUTE_UNUSED, const arelent *rel, -+ struct internal_reloc *intern) -+{ -+ switch (intern->r_type) -+ { -+ case SW_64_R_LITUSE: -+ case SW_64_R_GPDISP: -+ intern->r_size = rel->addend; -+ break; -+ -+ case SW_64_R_OP_STORE: -+ intern->r_size = rel->addend & 0xff; -+ intern->r_offset = (rel->addend >> 8) & 0xff; -+ break; -+ -+ case SW_64_R_OP_PUSH: -+ case SW_64_R_OP_PSUB: -+ case SW_64_R_OP_PRSHIFT: -+ intern->r_vaddr = rel->addend; -+ break; -+ -+ case SW_64_R_IGNORE: -+ intern->r_vaddr = rel->address; -+ break; -+ -+ default: -+ break; -+ } -+} -+ -+/* The size of the stack for the relocation evaluator. */ -+#define RELOC_STACKSIZE (10) -+ -+/* SW_64 ECOFF relocs have a built in expression evaluator as well as -+ other interdependencies. Rather than use a bunch of special -+ functions and global variables, we use a single routine to do all -+ the relocation for a section. I haven't yet worked out how the -+ assembler is going to handle this. */ -+ -+static bfd_byte * -+sw_64_ecoff_get_relocated_section_contents (bfd *abfd, -+ struct bfd_link_info *link_info, -+ struct bfd_link_order *link_order, -+ bfd_byte *data, bool relocatable, -+ asymbol **symbols) -+{ -+ bfd *input_bfd = link_order->u.indirect.section->owner; -+ asection *input_section = link_order->u.indirect.section; -+ long reloc_size = bfd_get_reloc_upper_bound (input_bfd, input_section); -+ arelent **reloc_vector = NULL; -+ long reloc_count; -+ bfd *output_bfd = relocatable ? abfd : (bfd *) NULL; -+ bfd_vma gp; -+ bfd_size_type sz; -+ bool gp_undefined; -+ bfd_vma stack[RELOC_STACKSIZE]; -+ int tos = 0; -+ -+ if (reloc_size < 0) -+ goto error_return; -+ reloc_vector = (arelent **) bfd_malloc ((bfd_size_type) reloc_size); -+ if (reloc_vector == NULL && reloc_size != 0) -+ goto error_return; -+ -+ sz = input_section->rawsize ? input_section->rawsize : input_section->size; -+ if (!bfd_get_section_contents (input_bfd, input_section, data, 0, sz)) -+ goto error_return; -+ -+ reloc_count -+ = bfd_canonicalize_reloc (input_bfd, input_section, reloc_vector, symbols); -+ if (reloc_count < 0) -+ goto error_return; -+ if (reloc_count == 0) -+ goto successful_return; -+ -+ /* Get the GP value for the output BFD. */ -+ gp_undefined = false; -+ gp = _bfd_get_gp_value (abfd); -+ if (gp == 0) -+ { -+ if (relocatable) -+ { -+ asection *sec; -+ bfd_vma lo; -+ -+ /* Make up a value. */ -+ lo = (bfd_vma) -1; -+ for (sec = abfd->sections; sec != NULL; sec = sec->next) -+ { -+ if (sec->vma < lo -+ && (strcmp (sec->name, ".sbss") == 0 -+ || strcmp (sec->name, ".sdata") == 0 -+ || strcmp (sec->name, ".lit4") == 0 -+ || strcmp (sec->name, ".lit8") == 0 -+ || strcmp (sec->name, ".lita") == 0)) -+ lo = sec->vma; -+ } -+ gp = lo + 0x8000; -+ _bfd_set_gp_value (abfd, gp); -+ } -+ else -+ { -+ struct bfd_link_hash_entry *h; -+ -+ h = bfd_link_hash_lookup (link_info->hash, "_gp", false, false, true); -+ if (h == (struct bfd_link_hash_entry *) NULL -+ || h->type != bfd_link_hash_defined) -+ gp_undefined = true; -+ else -+ { -+ gp = (h->u.def.value + h->u.def.section->output_section->vma -+ + h->u.def.section->output_offset); -+ _bfd_set_gp_value (abfd, gp); -+ } -+ } -+ } -+ -+ for (; *reloc_vector != (arelent *) NULL; reloc_vector++) -+ { -+ arelent *rel; -+ bfd_reloc_status_type r; -+ char *err; -+ -+ rel = *reloc_vector; -+ r = bfd_reloc_ok; -+ switch (rel->howto->type) -+ { -+ case SW_64_R_IGNORE: -+ rel->address += input_section->output_offset; -+ break; -+ -+ case SW_64_R_REFLONG: -+ case SW_64_R_REFQUAD: -+ case SW_64_R_BRADDR: -+ case SW_64_R_BR26ADDR: -+ case SW_64_R_HINT: -+ case SW_64_R_SREL16: -+ case SW_64_R_SREL32: -+ case SW_64_R_SREL64: -+ if (relocatable -+ && ((*rel->sym_ptr_ptr)->flags & BSF_SECTION_SYM) == 0) -+ { -+ rel->address += input_section->output_offset; -+ break; -+ } -+ r = bfd_perform_relocation (input_bfd, rel, data, input_section, -+ output_bfd, &err); -+ break; -+ -+ case SW_64_R_GPREL32: -+ /* This relocation is used in a switch table. It is a 32 -+ bit offset from the current GP value. We must adjust it -+ by the different between the original GP value and the -+ current GP value. The original GP value is stored in the -+ addend. We adjust the addend and let -+ bfd_perform_relocation finish the job. */ -+ rel->addend -= gp; -+ r = bfd_perform_relocation (input_bfd, rel, data, input_section, -+ output_bfd, &err); -+ if (r == bfd_reloc_ok && gp_undefined) -+ { -+ r = bfd_reloc_dangerous; -+ err = (char *) _ ( -+ "GP relative relocation used when GP not defined"); -+ } -+ break; -+ -+ case SW_64_R_LITERAL: -+ /* This is a reference to a literal value, generally -+ (always?) in the .lita section. This is a 16 bit GP -+ relative relocation. Sometimes the subsequent reloc is a -+ LITUSE reloc, which indicates how this reloc is used. -+ This sometimes permits rewriting the two instructions -+ referred to by the LITERAL and the LITUSE into different -+ instructions which do not refer to .lita. This can save -+ a memory reference, and permits removing a value from -+ .lita thus saving GP relative space. -+ -+ We do not these optimizations. To do them we would need -+ to arrange to link the .lita section first, so that by -+ the time we got here we would know the final values to -+ use. This would not be particularly difficult, but it is -+ not currently implemented. */ -+ -+ { -+ unsigned long insn; -+ -+ /* I believe that the LITERAL reloc will only apply to a -+ ldq or ldl instruction, so check my assumption. */ -+ insn = bfd_get_32 (input_bfd, data + rel->address); -+ BFD_ASSERT (((insn >> 26) & 0x3f) == 0x29 -+ || ((insn >> 26) & 0x3f) == 0x28); -+ -+ rel->addend -= gp; -+ r = bfd_perform_relocation (input_bfd, rel, data, input_section, -+ output_bfd, &err); -+ if (r == bfd_reloc_ok && gp_undefined) -+ { -+ r = bfd_reloc_dangerous; -+ err = (char *) _ ( -+ "GP relative relocation used when GP not defined"); -+ } -+ } -+ break; -+ -+ case SW_64_R_LITUSE: -+ /* See SW_64_R_LITERAL above for the uses of this reloc. It -+ does not cause anything to happen, itself. */ -+ rel->address += input_section->output_offset; -+ break; -+ -+ case SW_64_R_GPDISP: -+ /* This marks the ldah of an ldah/lda pair which loads the -+ gp register with the difference of the gp value and the -+ current location. The second of the pair is r_size bytes -+ ahead; it used to be marked with an SW_64_R_IGNORE reloc, -+ but that no longer happens in OSF/1 3.2. */ -+ { -+ unsigned long insn1, insn2; -+ bfd_vma addend; -+ -+ /* Get the two instructions. */ -+ insn1 = bfd_get_32 (input_bfd, data + rel->address); -+ insn2 = bfd_get_32 (input_bfd, data + rel->address + rel->addend); -+ -+ BFD_ASSERT (((insn1 >> 26) & 0x3f) == 0x09); /* ldah */ -+ BFD_ASSERT (((insn2 >> 26) & 0x3f) == 0x08); /* lda */ -+ -+ /* Get the existing addend. We must account for the sign -+ extension done by lda and ldah. */ -+ addend = ((insn1 & 0xffff) << 16) + (insn2 & 0xffff); -+ if (insn1 & 0x8000) -+ { -+ addend -= 0x80000000; -+ addend -= 0x80000000; -+ } -+ if (insn2 & 0x8000) -+ addend -= 0x10000; -+ -+ /* The existing addend includes the different between the -+ gp of the input BFD and the address in the input BFD. -+ Subtract this out. */ -+ addend -= (ecoff_data (input_bfd)->gp -+ - (input_section->vma + rel->address)); -+ -+ /* Now add in the final gp value, and subtract out the -+ final address. */ -+ addend += (gp -+ - (input_section->output_section->vma -+ + input_section->output_offset + rel->address)); -+ -+ /* Change the instructions, accounting for the sign -+ extension, and write them out. */ -+ if (addend & 0x8000) -+ addend += 0x10000; -+ insn1 = (insn1 & 0xffff0000) | ((addend >> 16) & 0xffff); -+ insn2 = (insn2 & 0xffff0000) | (addend & 0xffff); -+ -+ bfd_put_32 (input_bfd, (bfd_vma) insn1, data + rel->address); -+ bfd_put_32 (input_bfd, (bfd_vma) insn2, -+ data + rel->address + rel->addend); -+ -+ rel->address += input_section->output_offset; -+ } -+ break; -+ -+ case SW_64_R_OP_PUSH: -+ /* Push a value on the reloc evaluation stack. */ -+ { -+ asymbol *symbol; -+ bfd_vma relocation; -+ -+ if (relocatable) -+ { -+ rel->address += input_section->output_offset; -+ break; -+ } -+ -+ /* Figure out the relocation of this symbol. */ -+ symbol = *rel->sym_ptr_ptr; -+ -+ if (bfd_is_und_section (symbol->section)) -+ r = bfd_reloc_undefined; -+ -+ if (bfd_is_com_section (symbol->section)) -+ relocation = 0; -+ else -+ relocation = symbol->value; -+ relocation += symbol->section->output_section->vma; -+ relocation += symbol->section->output_offset; -+ relocation += rel->addend; -+ -+ if (tos >= RELOC_STACKSIZE) -+ abort (); -+ -+ stack[tos++] = relocation; -+ } -+ break; -+ -+ case SW_64_R_OP_STORE: -+ /* Store a value from the reloc stack into a bitfield. */ -+ { -+ bfd_vma val; -+ int offset, size; -+ -+ if (relocatable) -+ { -+ rel->address += input_section->output_offset; -+ break; -+ } -+ -+ if (tos == 0) -+ abort (); -+ -+ /* The offset and size for this reloc are encoded into the -+ addend field by sw_64_adjust_reloc_in. */ -+ offset = (rel->addend >> 8) & 0xff; -+ size = rel->addend & 0xff; -+ -+ val = bfd_get_64 (abfd, data + rel->address); -+ val &= ~(((1 << size) - 1) << offset); -+ val |= (stack[--tos] & ((1 << size) - 1)) << offset; -+ bfd_put_64 (abfd, val, data + rel->address); -+ } -+ break; -+ -+ case SW_64_R_OP_PSUB: -+ /* Subtract a value from the top of the stack. */ -+ { -+ asymbol *symbol; -+ bfd_vma relocation; -+ -+ if (relocatable) -+ { -+ rel->address += input_section->output_offset; -+ break; -+ } -+ -+ /* Figure out the relocation of this symbol. */ -+ symbol = *rel->sym_ptr_ptr; -+ -+ if (bfd_is_und_section (symbol->section)) -+ r = bfd_reloc_undefined; -+ -+ if (bfd_is_com_section (symbol->section)) -+ relocation = 0; -+ else -+ relocation = symbol->value; -+ relocation += symbol->section->output_section->vma; -+ relocation += symbol->section->output_offset; -+ relocation += rel->addend; -+ -+ if (tos == 0) -+ abort (); -+ -+ stack[tos - 1] -= relocation; -+ } -+ break; -+ -+ case SW_64_R_OP_PRSHIFT: -+ /* Shift the value on the top of the stack. */ -+ { -+ asymbol *symbol; -+ bfd_vma relocation; -+ -+ if (relocatable) -+ { -+ rel->address += input_section->output_offset; -+ break; -+ } -+ -+ /* Figure out the relocation of this symbol. */ -+ symbol = *rel->sym_ptr_ptr; -+ -+ if (bfd_is_und_section (symbol->section)) -+ r = bfd_reloc_undefined; -+ -+ if (bfd_is_com_section (symbol->section)) -+ relocation = 0; -+ else -+ relocation = symbol->value; -+ relocation += symbol->section->output_section->vma; -+ relocation += symbol->section->output_offset; -+ relocation += rel->addend; -+ -+ if (tos == 0) -+ abort (); -+ -+ stack[tos - 1] >>= relocation; -+ } -+ break; -+ -+ case SW_64_R_GPVALUE: -+ /* I really don't know if this does the right thing. */ -+ gp = rel->addend; -+ gp_undefined = false; -+ break; -+ -+ default: -+ abort (); -+ } -+ -+ if (relocatable) -+ { -+ asection *os = input_section->output_section; -+ -+ /* A partial link, so keep the relocs. */ -+ os->orelocation[os->reloc_count] = rel; -+ os->reloc_count++; -+ } -+ -+ if (r != bfd_reloc_ok) -+ { -+ switch (r) -+ { -+ case bfd_reloc_undefined: -+ (*link_info->callbacks->undefined_symbol) ( -+ link_info, bfd_asymbol_name (*rel->sym_ptr_ptr), input_bfd, -+ input_section, rel->address, true); -+ break; -+ case bfd_reloc_dangerous: -+ (*link_info->callbacks->reloc_dangerous) (link_info, err, -+ input_bfd, -+ input_section, -+ rel->address); -+ break; -+ case bfd_reloc_overflow: -+ (*link_info->callbacks->reloc_overflow) ( -+ link_info, NULL, bfd_asymbol_name (*rel->sym_ptr_ptr), -+ rel->howto->name, rel->addend, input_bfd, input_section, -+ rel->address); -+ break; -+ case bfd_reloc_outofrange: -+ default: -+ abort (); -+ break; -+ } -+ } -+ } -+ -+ if (tos != 0) -+ abort (); -+ -+successful_return: -+ free (reloc_vector); -+ return data; -+ -+error_return: -+ free (reloc_vector); -+ return NULL; -+} -+ -+/* Get the howto structure for a generic reloc type. */ -+ -+static reloc_howto_type * -+sw_64_bfd_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED, -+ bfd_reloc_code_real_type code) -+{ -+ int sw_64_type; -+ -+ switch (code) -+ { -+ case BFD_RELOC_32: -+ sw_64_type = SW_64_R_REFLONG; -+ break; -+ case BFD_RELOC_64: -+ case BFD_RELOC_CTOR: -+ sw_64_type = SW_64_R_REFQUAD; -+ break; -+ case BFD_RELOC_GPREL32: -+ sw_64_type = SW_64_R_GPREL32; -+ break; -+ case BFD_RELOC_SW_64_LITERAL: -+ sw_64_type = SW_64_R_LITERAL; -+ break; -+ case BFD_RELOC_SW_64_LITUSE: -+ sw_64_type = SW_64_R_LITUSE; -+ break; -+ case BFD_RELOC_SW_64_GPDISP_HI16: -+ sw_64_type = SW_64_R_GPDISP; -+ break; -+ case BFD_RELOC_SW_64_GPDISP_LO16: -+ sw_64_type = SW_64_R_IGNORE; -+ break; -+ case BFD_RELOC_23_PCREL_S2: -+ sw_64_type = SW_64_R_BRADDR; -+ break; -+ case BFD_RELOC_SW_64_BR26: -+ sw_64_type = SW_64_R_BR26ADDR; -+ break; -+ case BFD_RELOC_SW_64_HINT: -+ sw_64_type = SW_64_R_HINT; -+ break; -+ case BFD_RELOC_16_PCREL: -+ sw_64_type = SW_64_R_SREL16; -+ break; -+ case BFD_RELOC_32_PCREL: -+ sw_64_type = SW_64_R_SREL32; -+ break; -+ case BFD_RELOC_64_PCREL: -+ sw_64_type = SW_64_R_SREL64; -+ break; -+ default: -+ return (reloc_howto_type *) NULL; -+ } -+ -+ return &sw_64_howto_table[sw_64_type]; -+} -+ -+static reloc_howto_type * -+sw_64_bfd_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED, const char *r_name) -+{ -+ unsigned int i; -+ -+ for (i = 0; i < sizeof (sw_64_howto_table) / sizeof (sw_64_howto_table[0]); -+ i++) -+ if (sw_64_howto_table[i].name != NULL -+ && strcasecmp (sw_64_howto_table[i].name, r_name) == 0) -+ return &sw_64_howto_table[i]; -+ -+ return NULL; -+} -+ -+/* A helper routine for sw_64_relocate_section which converts an -+ external reloc when generating relocatable output. Returns the -+ relocation amount. */ -+ -+static bfd_vma -+sw_64_convert_external_reloc (bfd *output_bfd ATTRIBUTE_UNUSED, -+ struct bfd_link_info *info, bfd *input_bfd, -+ struct external_reloc *ext_rel, -+ struct ecoff_link_hash_entry *h) -+{ -+ unsigned long r_symndx; -+ bfd_vma relocation; -+ -+ BFD_ASSERT (bfd_link_relocatable (info)); -+ -+ if (h->root.type == bfd_link_hash_defined -+ || h->root.type == bfd_link_hash_defweak) -+ { -+ asection *hsec; -+ const char *name; -+ -+ /* This symbol is defined in the output. Convert the reloc from -+ being against the symbol to being against the section. */ -+ -+ /* Clear the r_extern bit. */ -+ ext_rel->r_bits[1] &= ~RELOC_BITS1_EXTERN_LITTLE; -+ -+ /* Compute a new r_symndx value. */ -+ hsec = h->root.u.def.section; -+ name = bfd_section_name (hsec->output_section); -+ -+ r_symndx = (unsigned long) -1; -+ switch (name[1]) -+ { -+ case 'A': -+ if (strcmp (name, "*ABS*") == 0) -+ r_symndx = RELOC_SECTION_ABS; -+ break; -+ case 'b': -+ if (strcmp (name, ".bss") == 0) -+ r_symndx = RELOC_SECTION_BSS; -+ break; -+ case 'd': -+ if (strcmp (name, ".data") == 0) -+ r_symndx = RELOC_SECTION_DATA; -+ break; -+ case 'f': -+ if (strcmp (name, ".fini") == 0) -+ r_symndx = RELOC_SECTION_FINI; -+ break; -+ case 'i': -+ if (strcmp (name, ".init") == 0) -+ r_symndx = RELOC_SECTION_INIT; -+ break; -+ case 'l': -+ if (strcmp (name, ".lita") == 0) -+ r_symndx = RELOC_SECTION_LITA; -+ else if (strcmp (name, ".lit8") == 0) -+ r_symndx = RELOC_SECTION_LIT8; -+ else if (strcmp (name, ".lit4") == 0) -+ r_symndx = RELOC_SECTION_LIT4; -+ break; -+ case 'p': -+ if (strcmp (name, ".pdata") == 0) -+ r_symndx = RELOC_SECTION_PDATA; -+ break; -+ case 'r': -+ if (strcmp (name, ".rdata") == 0) -+ r_symndx = RELOC_SECTION_RDATA; -+ else if (strcmp (name, ".rconst") == 0) -+ r_symndx = RELOC_SECTION_RCONST; -+ break; -+ case 's': -+ if (strcmp (name, ".sdata") == 0) -+ r_symndx = RELOC_SECTION_SDATA; -+ else if (strcmp (name, ".sbss") == 0) -+ r_symndx = RELOC_SECTION_SBSS; -+ break; -+ case 't': -+ if (strcmp (name, ".text") == 0) -+ r_symndx = RELOC_SECTION_TEXT; -+ break; -+ case 'x': -+ if (strcmp (name, ".xdata") == 0) -+ r_symndx = RELOC_SECTION_XDATA; -+ break; -+ } -+ -+ if (r_symndx == (unsigned long) -1) -+ abort (); -+ -+ /* Add the section VMA and the symbol value. */ -+ relocation = (h->root.u.def.value + hsec->output_section->vma -+ + hsec->output_offset); -+ } -+ else -+ { -+ /* Change the symndx value to the right one for -+ the output BFD. */ -+ r_symndx = h->indx; -+ if (r_symndx == (unsigned long) -1) -+ { -+ /* Caller must give an error. */ -+ r_symndx = 0; -+ } -+ relocation = 0; -+ } -+ -+ /* Write out the new r_symndx value. */ -+ H_PUT_32 (input_bfd, r_symndx, ext_rel->r_symndx); -+ -+ return relocation; -+} -+ -+/* Relocate a section while linking an SW_64 ECOFF file. This is -+ quite similar to get_relocated_section_contents. Perhaps they -+ could be combined somehow. */ -+ -+static bool -+sw_64_relocate_section (bfd *output_bfd, struct bfd_link_info *info, -+ bfd *input_bfd, asection *input_section, -+ bfd_byte *contents, void *external_relocs) -+{ -+ asection **symndx_to_section, *lita_sec; -+ struct ecoff_link_hash_entry **sym_hashes; -+ bfd_vma gp; -+ bool gp_undefined; -+ bfd_vma stack[RELOC_STACKSIZE]; -+ int tos = 0; -+ struct external_reloc *ext_rel; -+ struct external_reloc *ext_rel_end; -+ bfd_size_type amt; -+ -+ /* We keep a table mapping the symndx found in an internal reloc to -+ the appropriate section. This is faster than looking up the -+ section by name each time. */ -+ symndx_to_section = ecoff_data (input_bfd)->symndx_to_section; -+ if (symndx_to_section == (asection **) NULL) -+ { -+ amt = NUM_RELOC_SECTIONS * sizeof (asection *); -+ symndx_to_section = (asection **) bfd_alloc (input_bfd, amt); -+ if (!symndx_to_section) -+ return false; -+ -+ symndx_to_section[RELOC_SECTION_NONE] = NULL; -+ symndx_to_section[RELOC_SECTION_TEXT] -+ = bfd_get_section_by_name (input_bfd, ".text"); -+ symndx_to_section[RELOC_SECTION_RDATA] -+ = bfd_get_section_by_name (input_bfd, ".rdata"); -+ symndx_to_section[RELOC_SECTION_DATA] -+ = bfd_get_section_by_name (input_bfd, ".data"); -+ symndx_to_section[RELOC_SECTION_SDATA] -+ = bfd_get_section_by_name (input_bfd, ".sdata"); -+ symndx_to_section[RELOC_SECTION_SBSS] -+ = bfd_get_section_by_name (input_bfd, ".sbss"); -+ symndx_to_section[RELOC_SECTION_BSS] -+ = bfd_get_section_by_name (input_bfd, ".bss"); -+ symndx_to_section[RELOC_SECTION_INIT] -+ = bfd_get_section_by_name (input_bfd, ".init"); -+ symndx_to_section[RELOC_SECTION_LIT8] -+ = bfd_get_section_by_name (input_bfd, ".lit8"); -+ symndx_to_section[RELOC_SECTION_LIT4] -+ = bfd_get_section_by_name (input_bfd, ".lit4"); -+ symndx_to_section[RELOC_SECTION_XDATA] -+ = bfd_get_section_by_name (input_bfd, ".xdata"); -+ symndx_to_section[RELOC_SECTION_PDATA] -+ = bfd_get_section_by_name (input_bfd, ".pdata"); -+ symndx_to_section[RELOC_SECTION_FINI] -+ = bfd_get_section_by_name (input_bfd, ".fini"); -+ symndx_to_section[RELOC_SECTION_LITA] -+ = bfd_get_section_by_name (input_bfd, ".lita"); -+ symndx_to_section[RELOC_SECTION_ABS] = bfd_abs_section_ptr; -+ symndx_to_section[RELOC_SECTION_RCONST] -+ = bfd_get_section_by_name (input_bfd, ".rconst"); -+ -+ ecoff_data (input_bfd)->symndx_to_section = symndx_to_section; -+ } -+ -+ sym_hashes = ecoff_data (input_bfd)->sym_hashes; -+ -+ /* On the SW_64, the .lita section must be addressable by the global -+ pointer. To support large programs, we need to allow multiple -+ global pointers. This works as long as each input .lita section -+ is <64KB big. This implies that when producing relocatable -+ output, the .lita section is limited to 64KB. . */ -+ -+ lita_sec = symndx_to_section[RELOC_SECTION_LITA]; -+ gp = _bfd_get_gp_value (output_bfd); -+ if (!bfd_link_relocatable (info) && lita_sec != NULL) -+ { -+ struct ecoff_section_tdata *lita_sec_data; -+ -+ /* Make sure we have a section data structure to which we can -+ hang on to the gp value we pick for the section. */ -+ lita_sec_data = ecoff_section_data (input_bfd, lita_sec); -+ if (lita_sec_data == NULL) -+ { -+ amt = sizeof (struct ecoff_section_tdata); -+ lita_sec_data -+ = ((struct ecoff_section_tdata *) bfd_zalloc (input_bfd, amt)); -+ lita_sec->used_by_bfd = lita_sec_data; -+ } -+ -+ if (lita_sec_data->gp != 0) -+ { -+ /* If we already assigned a gp to this section, we better -+ stick with that value. */ -+ gp = lita_sec_data->gp; -+ } -+ else -+ { -+ bfd_vma lita_vma; -+ bfd_size_type lita_size; -+ -+ lita_vma = lita_sec->output_offset + lita_sec->output_section->vma; -+ lita_size = lita_sec->size; -+ -+ if (gp == 0 || lita_vma < gp - 0x8000 -+ || lita_vma + lita_size >= gp + 0x8000) -+ { -+ /* Either gp hasn't been set at all or the current gp -+ cannot address this .lita section. In both cases we -+ reset the gp to point into the "middle" of the -+ current input .lita section. */ -+ if (gp && !ecoff_data (output_bfd)->issued_multiple_gp_warning) -+ { -+ (*info->callbacks->warning) (info, -+ _ ("using multiple gp values"), -+ (char *) NULL, output_bfd, -+ (asection *) NULL, (bfd_vma) 0); -+ ecoff_data (output_bfd)->issued_multiple_gp_warning = true; -+ } -+ if (lita_vma < gp - 0x8000) -+ gp = lita_vma + lita_size - 0x8000; -+ else -+ gp = lita_vma + 0x8000; -+ } -+ -+ lita_sec_data->gp = gp; -+ } -+ -+ _bfd_set_gp_value (output_bfd, gp); -+ } -+ -+ gp_undefined = (gp == 0); -+ -+ BFD_ASSERT (bfd_header_little_endian (output_bfd)); -+ BFD_ASSERT (bfd_header_little_endian (input_bfd)); -+ -+ ext_rel = (struct external_reloc *) external_relocs; -+ ext_rel_end = ext_rel + input_section->reloc_count; -+ for (; ext_rel < ext_rel_end; ext_rel++) -+ { -+ bfd_vma r_vaddr; -+ unsigned long r_symndx; -+ int r_type; -+ int r_extern; -+ int r_offset; -+ int r_size; -+ bool relocatep; -+ bool adjust_addrp; -+ bool gp_usedp; -+ bfd_vma addend; -+ -+ r_vaddr = H_GET_64 (input_bfd, ext_rel->r_vaddr); -+ r_symndx = H_GET_32 (input_bfd, ext_rel->r_symndx); -+ -+ r_type = ((ext_rel->r_bits[0] & RELOC_BITS0_TYPE_LITTLE) -+ >> RELOC_BITS0_TYPE_SH_LITTLE); -+ r_extern = (ext_rel->r_bits[1] & RELOC_BITS1_EXTERN_LITTLE) != 0; -+ r_offset = ((ext_rel->r_bits[1] & RELOC_BITS1_OFFSET_LITTLE) -+ >> RELOC_BITS1_OFFSET_SH_LITTLE); -+ /* Ignored the reserved bits. */ -+ r_size = ((ext_rel->r_bits[3] & RELOC_BITS3_SIZE_LITTLE) -+ >> RELOC_BITS3_SIZE_SH_LITTLE); -+ -+ relocatep = false; -+ adjust_addrp = true; -+ gp_usedp = false; -+ addend = 0; -+ -+ switch (r_type) -+ { -+ case SW_64_R_GPRELHIGH: -+ _bfd_error_handler (_ ("%pB: %s unsupported"), input_bfd, -+ "SW_64_R_GPRELHIGH"); -+ bfd_set_error (bfd_error_bad_value); -+ continue; -+ -+ case SW_64_R_GPRELLOW: -+ _bfd_error_handler (_ ("%pB: %s unsupported"), input_bfd, -+ "SW_64_R_GPRELLOW"); -+ bfd_set_error (bfd_error_bad_value); -+ continue; -+ -+ default: -+ /* xgettext:c-format */ -+ _bfd_error_handler (_ ("%pB: unsupported relocation type %#x"), -+ input_bfd, (int) r_type); -+ bfd_set_error (bfd_error_bad_value); -+ continue; -+ -+ case SW_64_R_IGNORE: -+ /* This reloc appears after a GPDISP reloc. On earlier -+ versions of OSF/1, It marked the position of the second -+ instruction to be altered by the GPDISP reloc, but it is -+ not otherwise used for anything. For some reason, the -+ address of the relocation does not appear to include the -+ section VMA, unlike the other relocation types. */ -+ if (bfd_link_relocatable (info)) -+ H_PUT_64 (input_bfd, input_section->output_offset + r_vaddr, -+ ext_rel->r_vaddr); -+ adjust_addrp = false; -+ break; -+ -+ case SW_64_R_REFLONG: -+ case SW_64_R_REFQUAD: -+ case SW_64_R_HINT: -+ relocatep = true; -+ break; -+ -+ case SW_64_R_BRADDR: -+ case SW_64_R_BR26ADDR: -+ case SW_64_R_SREL16: -+ case SW_64_R_SREL32: -+ case SW_64_R_SREL64: -+ if (r_extern) -+ addend += -(r_vaddr + 4); -+ relocatep = true; -+ break; -+ -+ case SW_64_R_GPREL32: -+ /* This relocation is used in a switch table. It is a 32 -+ bit offset from the current GP value. We must adjust it -+ by the different between the original GP value and the -+ current GP value. */ -+ relocatep = true; -+ addend = ecoff_data (input_bfd)->gp - gp; -+ gp_usedp = true; -+ break; -+ -+ case SW_64_R_LITERAL: -+ /* This is a reference to a literal value, generally -+ (always?) in the .lita section. This is a 16 bit GP -+ relative relocation. Sometimes the subsequent reloc is a -+ LITUSE reloc, which indicates how this reloc is used. -+ This sometimes permits rewriting the two instructions -+ referred to by the LITERAL and the LITUSE into different -+ instructions which do not refer to .lita. This can save -+ a memory reference, and permits removing a value from -+ .lita thus saving GP relative space. -+ -+ We do not these optimizations. To do them we would need -+ to arrange to link the .lita section first, so that by -+ the time we got here we would know the final values to -+ use. This would not be particularly difficult, but it is -+ not currently implemented. */ -+ -+ /* I believe that the LITERAL reloc will only apply to a ldq -+ or ldl instruction, so check my assumption. */ -+ { -+ unsigned long insn; -+ -+ insn -+ = bfd_get_32 (input_bfd, contents + r_vaddr - input_section->vma); -+ BFD_ASSERT (((insn >> 26) & 0x3f) == 0x29 -+ || ((insn >> 26) & 0x3f) == 0x28); -+ } -+ -+ relocatep = true; -+ addend = ecoff_data (input_bfd)->gp - gp; -+ gp_usedp = true; -+ break; -+ -+ case SW_64_R_LITUSE: -+ /* See SW_64_R_LITERAL above for the uses of this reloc. It -+ does not cause anything to happen, itself. */ -+ break; -+ -+ case SW_64_R_GPDISP: -+ /* This marks the ldah of an ldah/lda pair which loads the -+ gp register with the difference of the gp value and the -+ current location. The second of the pair is r_symndx -+ bytes ahead. It used to be marked with an SW_64_R_IGNORE -+ reloc, but OSF/1 3.2 no longer does that. */ -+ { -+ unsigned long insn1, insn2; -+ -+ /* Get the two instructions. */ -+ insn1 -+ = bfd_get_32 (input_bfd, contents + r_vaddr - input_section->vma); -+ insn2 = bfd_get_32 (input_bfd, (contents + r_vaddr -+ - input_section->vma + r_symndx)); -+ -+ BFD_ASSERT (((insn1 >> 26) & 0x3f) == 0x09); /* ldah */ -+ BFD_ASSERT (((insn2 >> 26) & 0x3f) == 0x08); /* lda */ -+ -+ /* Get the existing addend. We must account for the sign -+ extension done by lda and ldah. */ -+ addend = ((insn1 & 0xffff) << 16) + (insn2 & 0xffff); -+ if (insn1 & 0x8000) -+ { -+ /* This is addend -= 0x100000000 without causing an -+ integer overflow on a 32 bit host. */ -+ addend -= 0x80000000; -+ addend -= 0x80000000; -+ } -+ if (insn2 & 0x8000) -+ addend -= 0x10000; -+ -+ /* The existing addend includes the difference between the -+ gp of the input BFD and the address in the input BFD. -+ We want to change this to the difference between the -+ final GP and the final address. */ -+ addend += (gp - ecoff_data (input_bfd)->gp + input_section->vma -+ - (input_section->output_section->vma -+ + input_section->output_offset)); -+ -+ /* Change the instructions, accounting for the sign -+ extension, and write them out. */ -+ if (addend & 0x8000) -+ addend += 0x10000; -+ insn1 = (insn1 & 0xffff0000) | ((addend >> 16) & 0xffff); -+ insn2 = (insn2 & 0xffff0000) | (addend & 0xffff); -+ -+ bfd_put_32 (input_bfd, (bfd_vma) insn1, -+ contents + r_vaddr - input_section->vma); -+ bfd_put_32 (input_bfd, (bfd_vma) insn2, -+ contents + r_vaddr - input_section->vma + r_symndx); -+ -+ gp_usedp = true; -+ } -+ break; -+ -+ case SW_64_R_OP_PUSH: -+ case SW_64_R_OP_PSUB: -+ case SW_64_R_OP_PRSHIFT: -+ /* Manipulate values on the reloc evaluation stack. The -+ r_vaddr field is not an address in input_section, it is -+ the current value (including any addend) of the object -+ being used. */ -+ if (!r_extern) -+ { -+ asection *s; -+ -+ s = symndx_to_section[r_symndx]; -+ if (s == (asection *) NULL) -+ abort (); -+ addend = s->output_section->vma + s->output_offset - s->vma; -+ } -+ else -+ { -+ struct ecoff_link_hash_entry *h; -+ -+ h = sym_hashes[r_symndx]; -+ if (h == (struct ecoff_link_hash_entry *) NULL) -+ abort (); -+ -+ if (!bfd_link_relocatable (info)) -+ { -+ if (h->root.type == bfd_link_hash_defined -+ || h->root.type == bfd_link_hash_defweak) -+ addend = (h->root.u.def.value -+ + h->root.u.def.section->output_section->vma -+ + h->root.u.def.section->output_offset); -+ else -+ { -+ /* Note that we pass the address as 0, since we -+ do not have a meaningful number for the -+ location within the section that is being -+ relocated. */ -+ (*info->callbacks->undefined_symbol) (info, -+ h->root.root.string, -+ input_bfd, -+ input_section, -+ (bfd_vma) 0, true); -+ addend = 0; -+ } -+ } -+ else -+ { -+ if (h->root.type != bfd_link_hash_defined -+ && h->root.type != bfd_link_hash_defweak && h->indx == -1) -+ { -+ /* This symbol is not being written out. Pass -+ the address as 0, as with undefined_symbol, -+ above. */ -+ (*info->callbacks->unattached_reloc) (info, -+ h->root.root.string, -+ input_bfd, -+ input_section, -+ (bfd_vma) 0); -+ } -+ -+ addend = sw_64_convert_external_reloc (output_bfd, info, -+ input_bfd, ext_rel, h); -+ } -+ } -+ -+ addend += r_vaddr; -+ -+ if (bfd_link_relocatable (info)) -+ { -+ /* Adjust r_vaddr by the addend. */ -+ H_PUT_64 (input_bfd, addend, ext_rel->r_vaddr); -+ } -+ else -+ { -+ switch (r_type) -+ { -+ case SW_64_R_OP_PUSH: -+ if (tos >= RELOC_STACKSIZE) -+ abort (); -+ stack[tos++] = addend; -+ break; -+ -+ case SW_64_R_OP_PSUB: -+ if (tos == 0) -+ abort (); -+ stack[tos - 1] -= addend; -+ break; -+ -+ case SW_64_R_OP_PRSHIFT: -+ if (tos == 0) -+ abort (); -+ stack[tos - 1] >>= addend; -+ break; -+ } -+ } -+ -+ adjust_addrp = false; -+ break; -+ -+ case SW_64_R_OP_STORE: -+ /* Store a value from the reloc stack into a bitfield. If -+ we are generating relocatable output, all we do is -+ adjust the address of the reloc. */ -+ if (!bfd_link_relocatable (info)) -+ { -+ bfd_vma mask; -+ bfd_vma val; -+ -+ if (tos == 0) -+ abort (); -+ -+ /* Get the relocation mask. The separate steps and the -+ casts to bfd_vma are attempts to avoid a bug in the -+ SW_64 OSF 1.3 C compiler. See reloc.c for more -+ details. */ -+ mask = 1; -+ mask <<= (bfd_vma) r_size; -+ mask -= 1; -+ -+ /* FIXME: I don't know what kind of overflow checking, -+ if any, should be done here. */ -+ val = bfd_get_64 (input_bfd, -+ contents + r_vaddr - input_section->vma); -+ val &= ~mask << (bfd_vma) r_offset; -+ val |= (stack[--tos] & mask) << (bfd_vma) r_offset; -+ bfd_put_64 (input_bfd, val, -+ contents + r_vaddr - input_section->vma); -+ } -+ break; -+ -+ case SW_64_R_GPVALUE: -+ /* I really don't know if this does the right thing. */ -+ gp = ecoff_data (input_bfd)->gp + r_symndx; -+ gp_undefined = false; -+ break; -+ } -+ -+ if (relocatep) -+ { -+ reloc_howto_type *howto; -+ struct ecoff_link_hash_entry *h = NULL; -+ asection *s = NULL; -+ bfd_vma relocation; -+ bfd_reloc_status_type r; -+ -+ /* Perform a relocation. */ -+ -+ howto = &sw_64_howto_table[r_type]; -+ -+ if (r_extern) -+ { -+ h = sym_hashes[r_symndx]; -+ /* If h is NULL, that means that there is a reloc -+ against an external symbol which we thought was just -+ a debugging symbol. This should not happen. */ -+ if (h == (struct ecoff_link_hash_entry *) NULL) -+ abort (); -+ } -+ else -+ { -+ if (r_symndx >= NUM_RELOC_SECTIONS) -+ s = NULL; -+ else -+ s = symndx_to_section[r_symndx]; -+ -+ if (s == (asection *) NULL) -+ abort (); -+ } -+ -+ if (bfd_link_relocatable (info)) -+ { -+ /* We are generating relocatable output, and must -+ convert the existing reloc. */ -+ if (r_extern) -+ { -+ if (h->root.type != bfd_link_hash_defined -+ && h->root.type != bfd_link_hash_defweak && h->indx == -1) -+ { -+ /* This symbol is not being written out. */ -+ (*info->callbacks->unattached_reloc) ( -+ info, h->root.root.string, input_bfd, input_section, -+ r_vaddr - input_section->vma); -+ } -+ -+ relocation -+ = sw_64_convert_external_reloc (output_bfd, info, input_bfd, -+ ext_rel, h); -+ } -+ else -+ { -+ /* This is a relocation against a section. Adjust -+ the value by the amount the section moved. */ -+ relocation -+ = (s->output_section->vma + s->output_offset - s->vma); -+ } -+ -+ /* If this is PC relative, the existing object file -+ appears to already have the reloc worked out. We -+ must subtract out the old value and add in the new -+ one. */ -+ if (howto->pc_relative) -+ relocation -+ -= (input_section->output_section->vma -+ + input_section->output_offset - input_section->vma); -+ -+ /* Put in any addend. */ -+ relocation += addend; -+ -+ /* Adjust the contents. */ -+ r = _bfd_relocate_contents (howto, input_bfd, relocation, -+ (contents + r_vaddr -+ - input_section->vma)); -+ } -+ else -+ { -+ /* We are producing a final executable. */ -+ if (r_extern) -+ { -+ /* This is a reloc against a symbol. */ -+ if (h->root.type == bfd_link_hash_defined -+ || h->root.type == bfd_link_hash_defweak) -+ { -+ asection *hsec; -+ -+ hsec = h->root.u.def.section; -+ relocation -+ = (h->root.u.def.value + hsec->output_section->vma -+ + hsec->output_offset); -+ } -+ else -+ { -+ (*info->callbacks->undefined_symbol) ( -+ info, h->root.root.string, input_bfd, input_section, -+ r_vaddr - input_section->vma, true); -+ relocation = 0; -+ } -+ } -+ else -+ { -+ /* This is a reloc against a section. */ -+ relocation -+ = (s->output_section->vma + s->output_offset - s->vma); -+ -+ /* Adjust a PC relative relocation by removing the -+ reference to the original source section. */ -+ if (howto->pc_relative) -+ relocation += input_section->vma; -+ } -+ -+ r = _bfd_final_link_relocate (howto, input_bfd, input_section, -+ contents, -+ r_vaddr - input_section->vma, -+ relocation, addend); -+ } -+ -+ if (r != bfd_reloc_ok) -+ { -+ switch (r) -+ { -+ default: -+ case bfd_reloc_outofrange: -+ abort (); -+ case bfd_reloc_overflow: { -+ const char *name; -+ -+ if (r_extern) -+ name = sym_hashes[r_symndx]->root.root.string; -+ else -+ name = bfd_section_name (symndx_to_section[r_symndx]); -+ (*info->callbacks->reloc_overflow) ( -+ info, NULL, name, sw_64_howto_table[r_type].name, -+ (bfd_vma) 0, input_bfd, input_section, -+ r_vaddr - input_section->vma); -+ } -+ break; -+ } -+ } -+ } -+ -+ if (bfd_link_relocatable (info) && adjust_addrp) -+ { -+ /* Change the address of the relocation. */ -+ H_PUT_64 (input_bfd, -+ (input_section->output_section->vma -+ + input_section->output_offset - input_section->vma -+ + r_vaddr), -+ ext_rel->r_vaddr); -+ } -+ -+ if (gp_usedp && gp_undefined) -+ { -+ (*info->callbacks->reloc_dangerous) ( -+ info, _ ("GP relative relocation used when GP not defined"), -+ input_bfd, input_section, r_vaddr - input_section->vma); -+ /* Only give the error once per link. */ -+ gp = 4; -+ _bfd_set_gp_value (output_bfd, gp); -+ gp_undefined = false; -+ } -+ } -+ -+ if (tos != 0) -+ abort (); -+ -+ return true; -+} -+ -+/* Do final adjustments to the filehdr and the aouthdr. This routine -+ sets the dynamic bits in the file header. */ -+ -+static bool -+sw_64_adjust_headers (bfd *abfd, struct internal_filehdr *fhdr, -+ struct internal_aouthdr *ahdr ATTRIBUTE_UNUSED) -+{ -+ if ((abfd->flags & (DYNAMIC | EXEC_P)) == (DYNAMIC | EXEC_P)) -+ fhdr->f_flags |= F_SW_64_CALL_SHARED; -+ else if ((abfd->flags & DYNAMIC) != 0) -+ fhdr->f_flags |= F_SW_64_SHARABLE; -+ return true; -+} -+ -+/* Archive handling. In OSF/1 (or Digital Unix) v3.2, Digital -+ introduced archive packing, in which the elements in an archive are -+ optionally compressed using a simple dictionary scheme. We know -+ how to read such archives, but we don't write them. */ -+ -+#define sw_64_ecoff_slurp_armap _bfd_ecoff_slurp_armap -+#define sw_64_ecoff_slurp_extended_name_table \ -+ _bfd_ecoff_slurp_extended_name_table -+#define sw_64_ecoff_construct_extended_name_table \ -+ _bfd_ecoff_construct_extended_name_table -+#define sw_64_ecoff_truncate_arname _bfd_ecoff_truncate_arname -+#define sw_64_ecoff_write_armap _bfd_ecoff_write_armap -+#define sw_64_ecoff_write_ar_hdr _bfd_generic_write_ar_hdr -+#define sw_64_ecoff_generic_stat_arch_elt _bfd_ecoff_generic_stat_arch_elt -+#define sw_64_ecoff_update_armap_timestamp _bfd_ecoff_update_armap_timestamp -+ -+/* A compressed file uses this instead of ARFMAG. */ -+ -+#define ARFZMAG "Z\012" -+ -+/* Read an archive header. This is like the standard routine, but it -+ also accepts ARFZMAG. */ -+ -+static void * -+sw_64_ecoff_read_ar_hdr (bfd *abfd) -+{ -+ struct areltdata *ret; -+ struct ar_hdr *h; -+ -+ ret = (struct areltdata *) _bfd_generic_read_ar_hdr_mag (abfd, ARFZMAG); -+ if (ret == NULL) -+ return NULL; -+ -+ h = (struct ar_hdr *) ret->arch_header; -+ if (strncmp (h->ar_fmag, ARFZMAG, 2) == 0) -+ { -+ bfd_byte ab[8]; -+ -+ /* This is a compressed file. We must set the size correctly. -+ The size is the eight bytes after the dummy file header. */ -+ if (bfd_seek (abfd, (file_ptr) FILHSZ, SEEK_CUR) != 0 -+ || bfd_bread (ab, (bfd_size_type) 8, abfd) != 8 -+ || bfd_seek (abfd, (file_ptr) (-(FILHSZ + 8)), SEEK_CUR) != 0) -+ { -+ free (ret); -+ return NULL; -+ } -+ -+ ret->parsed_size = H_GET_64 (abfd, ab); -+ } -+ -+ return ret; -+} -+ -+/* Get an archive element at a specified file position. This is where -+ we uncompress the archive element if necessary. */ -+ -+static bfd * -+sw_64_ecoff_get_elt_at_filepos (bfd *archive, file_ptr filepos, -+ struct bfd_link_info *info) -+{ -+ bfd *nbfd = NULL; -+ struct areltdata *tdata; -+ struct ar_hdr *hdr; -+ bfd_byte ab[8]; -+ bfd_size_type size; -+ bfd_byte *buf, *p; -+ struct bfd_in_memory *bim; -+ ufile_ptr filesize; -+ -+ buf = NULL; -+ nbfd = _bfd_get_elt_at_filepos (archive, filepos, info); -+ if (nbfd == NULL) -+ goto error_return; -+ -+ if ((nbfd->flags & BFD_IN_MEMORY) != 0) -+ { -+ /* We have already expanded this BFD. */ -+ return nbfd; -+ } -+ -+ tdata = (struct areltdata *) nbfd->arelt_data; -+ hdr = (struct ar_hdr *) tdata->arch_header; -+ if (strncmp (hdr->ar_fmag, ARFZMAG, 2) != 0) -+ return nbfd; -+ -+ /* We must uncompress this element. We do this by copying it into a -+ memory buffer, and making bfd_bread and bfd_seek use that buffer. -+ This can use a lot of memory, but it's simpler than getting a -+ temporary file, making that work with the file descriptor caching -+ code, and making sure that it is deleted at all appropriate -+ times. It can be changed if it ever becomes important. */ -+ -+ /* The compressed file starts with a dummy ECOFF file header. */ -+ if (bfd_seek (nbfd, (file_ptr) FILHSZ, SEEK_SET) != 0) -+ goto error_return; -+ -+ /* The next eight bytes are the real file size. */ -+ if (bfd_bread (ab, (bfd_size_type) 8, nbfd) != 8) -+ goto error_return; -+ size = H_GET_64 (nbfd, ab); -+ -+ /* The decompression algorithm will at most expand by eight times. */ -+ filesize = bfd_get_file_size (archive); -+ if (filesize != 0 && size / 8 > filesize) -+ { -+ bfd_set_error (bfd_error_malformed_archive); -+ goto error_return; -+ } -+ -+ if (size != 0) -+ { -+ bfd_size_type left; -+ bfd_byte dict[4096]; -+ unsigned int h; -+ bfd_byte b; -+ -+ buf = (bfd_byte *) bfd_malloc (size); -+ if (buf == NULL) -+ goto error_return; -+ p = buf; -+ -+ left = size; -+ -+ /* I don't know what the next eight bytes are for. */ -+ if (bfd_bread (ab, (bfd_size_type) 8, nbfd) != 8) -+ goto error_return; -+ -+ /* This is the uncompression algorithm. It's a simple -+ dictionary based scheme in which each character is predicted -+ by a hash of the previous three characters. A control byte -+ indicates whether the character is predicted or whether it -+ appears in the input stream; each control byte manages the -+ next eight bytes in the output stream. */ -+ memset (dict, 0, sizeof dict); -+ h = 0; -+ while (bfd_bread (&b, (bfd_size_type) 1, nbfd) == 1) -+ { -+ unsigned int i; -+ -+ for (i = 0; i < 8; i++, b >>= 1) -+ { -+ bfd_byte n; -+ -+ if ((b & 1) == 0) -+ n = dict[h]; -+ else -+ { -+ if (bfd_bread (&n, 1, nbfd) != 1) -+ goto error_return; -+ dict[h] = n; -+ } -+ -+ *p++ = n; -+ -+ --left; -+ if (left == 0) -+ break; -+ -+ h <<= 4; -+ h ^= n; -+ h &= sizeof dict - 1; -+ } -+ -+ if (left == 0) -+ break; -+ } -+ } -+ -+ /* Now the uncompressed file contents are in buf. */ -+ bim = ((struct bfd_in_memory *) bfd_malloc ( -+ (bfd_size_type) sizeof (struct bfd_in_memory))); -+ if (bim == NULL) -+ goto error_return; -+ bim->size = size; -+ bim->buffer = buf; -+ -+ nbfd->mtime_set = true; -+ nbfd->mtime = strtol (hdr->ar_date, (char **) NULL, 10); -+ -+ nbfd->flags |= BFD_IN_MEMORY; -+ nbfd->iostream = bim; -+ nbfd->iovec = &_bfd_memory_iovec; -+ nbfd->origin = 0; -+ BFD_ASSERT (!nbfd->cacheable); -+ -+ return nbfd; -+ -+error_return: -+ free (buf); -+ if (nbfd != NULL) -+ bfd_close (nbfd); -+ return NULL; -+} -+ -+/* Open the next archived file. */ -+ -+static bfd * -+sw_64_ecoff_openr_next_archived_file (bfd *archive, bfd *last_file) -+{ -+ ufile_ptr filestart; -+ -+ if (last_file == NULL) -+ filestart = bfd_ardata (archive)->first_file_filepos; -+ else -+ { -+ struct areltdata *t; -+ struct ar_hdr *h; -+ bfd_size_type size; -+ -+ /* We can't use arelt_size here, because that uses parsed_size, -+ which is the uncompressed size. We need the compressed size. */ -+ t = (struct areltdata *) last_file->arelt_data; -+ h = (struct ar_hdr *) t->arch_header; -+ size = strtol (h->ar_size, (char **) NULL, 10); -+ -+ /* Pad to an even boundary... -+ Note that last_file->origin can be odd in the case of -+ BSD-4.4-style element with a long odd size. */ -+ filestart = last_file->proxy_origin + size; -+ filestart += filestart % 2; -+ if (filestart < last_file->proxy_origin) -+ { -+ /* Prevent looping. See PR19256. */ -+ bfd_set_error (bfd_error_malformed_archive); -+ return NULL; -+ } -+ } -+ -+ return sw_64_ecoff_get_elt_at_filepos (archive, filestart, NULL); -+} -+ -+/* Open the archive file given an index into the armap. */ -+ -+static bfd * -+sw_64_ecoff_get_elt_at_index (bfd *abfd, symindex sym_index) -+{ -+ carsym *entry; -+ -+ entry = bfd_ardata (abfd)->symdefs + sym_index; -+ return sw_64_ecoff_get_elt_at_filepos (abfd, entry->file_offset, NULL); -+} -+ -+static void -+sw_64_ecoff_swap_coff_aux_in (bfd *abfd ATTRIBUTE_UNUSED, -+ void *ext1 ATTRIBUTE_UNUSED, -+ int type ATTRIBUTE_UNUSED, -+ int in_class ATTRIBUTE_UNUSED, -+ int indx ATTRIBUTE_UNUSED, -+ int numaux ATTRIBUTE_UNUSED, -+ void *in1 ATTRIBUTE_UNUSED) -+{} -+ -+static void -+sw_64_ecoff_swap_coff_sym_in (bfd *abfd ATTRIBUTE_UNUSED, -+ void *ext1 ATTRIBUTE_UNUSED, -+ void *in1 ATTRIBUTE_UNUSED) -+{} -+ -+static void -+sw_64_ecoff_swap_coff_lineno_in (bfd *abfd ATTRIBUTE_UNUSED, -+ void *ext1 ATTRIBUTE_UNUSED, -+ void *in1 ATTRIBUTE_UNUSED) -+{} -+ -+static unsigned int -+sw_64_ecoff_swap_coff_aux_out (bfd *abfd ATTRIBUTE_UNUSED, -+ void *inp ATTRIBUTE_UNUSED, -+ int type ATTRIBUTE_UNUSED, -+ int in_class ATTRIBUTE_UNUSED, -+ int indx ATTRIBUTE_UNUSED, -+ int numaux ATTRIBUTE_UNUSED, -+ void *extp ATTRIBUTE_UNUSED) -+{ -+ return 0; -+} -+ -+static unsigned int -+sw_64_ecoff_swap_coff_sym_out (bfd *abfd ATTRIBUTE_UNUSED, -+ void *inp ATTRIBUTE_UNUSED, -+ void *extp ATTRIBUTE_UNUSED) -+{ -+ return 0; -+} -+ -+static unsigned int -+sw_64_ecoff_swap_coff_lineno_out (bfd *abfd ATTRIBUTE_UNUSED, -+ void *inp ATTRIBUTE_UNUSED, -+ void *extp ATTRIBUTE_UNUSED) -+{ -+ return 0; -+} -+ -+static unsigned int -+sw_64_ecoff_swap_coff_reloc_out (bfd *abfd ATTRIBUTE_UNUSED, -+ void *inp ATTRIBUTE_UNUSED, -+ void *extp ATTRIBUTE_UNUSED) -+{ -+ return 0; -+} -+ -+/* This is the ECOFF backend structure. The backend field of the -+ target vector points to this. */ -+ -+static const struct ecoff_backend_data sw_64_ecoff_backend_data = { -+ /* COFF backend structure. */ -+ {sw_64_ecoff_swap_coff_aux_in, -+ sw_64_ecoff_swap_coff_sym_in, -+ sw_64_ecoff_swap_coff_lineno_in, -+ sw_64_ecoff_swap_coff_aux_out, -+ sw_64_ecoff_swap_coff_sym_out, -+ sw_64_ecoff_swap_coff_lineno_out, -+ sw_64_ecoff_swap_coff_reloc_out, -+ sw_64_ecoff_swap_filehdr_out, -+ sw_64_ecoff_swap_aouthdr_out, -+ sw_64_ecoff_swap_scnhdr_out, -+ FILHSZ, -+ AOUTSZ, -+ SCNHSZ, -+ 0, -+ 0, -+ 0, -+ 0, -+ FILNMLEN, -+ true, -+ ECOFF_NO_LONG_SECTION_NAMES, -+ 4, -+ false, -+ 2, -+ 32768, -+ sw_64_ecoff_swap_filehdr_in, -+ sw_64_ecoff_swap_aouthdr_in, -+ sw_64_ecoff_swap_scnhdr_in, -+ NULL, -+ sw_64_ecoff_bad_format_hook, -+ _bfd_ecoff_set_arch_mach_hook, -+ sw_64_ecoff_mkobject_hook, -+ _bfd_ecoff_styp_to_sec_flags, -+ _bfd_ecoff_set_alignment_hook, -+ _bfd_ecoff_slurp_symbol_table, -+ NULL, -+ NULL, -+ NULL, -+ NULL, -+ NULL, -+ NULL, -+ NULL, -+ NULL, -+ NULL, -+ NULL, -+ NULL, -+ NULL, -+ NULL, -+ NULL, -+ NULL}, -+ /* Supported architecture. */ -+ bfd_arch_sw_64, -+ /* Initial portion of armap string. */ -+ "________64", -+ /* The page boundary used to align sections in a demand-paged -+ executable file. E.g., 0x1000. */ -+ 0x2000, -+ /* true if the .rdata section is part of the text segment, as on the -+ SW_64. false if .rdata is part of the data segment, as on the -+ MIPS. */ -+ true, -+ /* Bitsize of constructor entries. */ -+ 64, -+ /* Reloc to use for constructor entries. */ -+ &sw_64_howto_table[SW_64_R_REFQUAD], -+ {/* Symbol table magic number. */ -+ magicSym2, -+ /* Alignment of debugging information. E.g., 4. */ -+ 8, -+ /* Sizes of external symbolic information. */ -+ sizeof (struct hdr_ext), sizeof (struct dnr_ext), sizeof (struct pdr_ext), -+ sizeof (struct sym_ext), sizeof (struct opt_ext), sizeof (struct fdr_ext), -+ sizeof (struct rfd_ext), sizeof (struct ext_ext), -+ /* Functions to swap in external symbolic data. */ -+ ecoff_swap_hdr_in, ecoff_swap_dnr_in, ecoff_swap_pdr_in, ecoff_swap_sym_in, -+ ecoff_swap_opt_in, ecoff_swap_fdr_in, ecoff_swap_rfd_in, ecoff_swap_ext_in, -+ _bfd_ecoff_swap_tir_in, _bfd_ecoff_swap_rndx_in, -+ /* Functions to swap out external symbolic data. */ -+ ecoff_swap_hdr_out, ecoff_swap_dnr_out, ecoff_swap_pdr_out, -+ ecoff_swap_sym_out, ecoff_swap_opt_out, ecoff_swap_fdr_out, -+ ecoff_swap_rfd_out, ecoff_swap_ext_out, _bfd_ecoff_swap_tir_out, -+ _bfd_ecoff_swap_rndx_out, -+ /* Function to read in symbolic data. */ -+ _bfd_ecoff_slurp_symbolic_info}, -+ /* External reloc size. */ -+ RELSZ, -+ /* Reloc swapping functions. */ -+ sw_64_ecoff_swap_reloc_in, -+ sw_64_ecoff_swap_reloc_out, -+ /* Backend reloc tweaking. */ -+ sw_64_adjust_reloc_in, -+ sw_64_adjust_reloc_out, -+ /* Relocate section contents while linking. */ -+ sw_64_relocate_section, -+ /* Do final adjustments to filehdr and aouthdr. */ -+ sw_64_adjust_headers, -+ /* Read an element from an archive at a given file position. */ -+ sw_64_ecoff_get_elt_at_filepos}; -+ -+/* Looking up a reloc type is SW_64 specific. */ -+#define _bfd_ecoff_bfd_reloc_type_lookup sw_64_bfd_reloc_type_lookup -+#define _bfd_ecoff_bfd_reloc_name_lookup sw_64_bfd_reloc_name_lookup -+ -+/* So is getting relocated section contents. */ -+#define _bfd_ecoff_bfd_get_relocated_section_contents \ -+ sw_64_ecoff_get_relocated_section_contents -+ -+/* Handling file windows is generic. */ -+#define _bfd_ecoff_get_section_contents_in_window \ -+ _bfd_generic_get_section_contents_in_window -+ -+/* Input section flag lookup is generic. */ -+#define _bfd_ecoff_bfd_lookup_section_flags bfd_generic_lookup_section_flags -+ -+/* Relaxing sections is generic. */ -+#define _bfd_ecoff_bfd_relax_section bfd_generic_relax_section -+#define _bfd_ecoff_bfd_gc_sections bfd_generic_gc_sections -+#define _bfd_ecoff_bfd_merge_sections bfd_generic_merge_sections -+#define _bfd_ecoff_bfd_is_group_section bfd_generic_is_group_section -+#define _bfd_ecoff_bfd_group_name bfd_generic_group_name -+#define _bfd_ecoff_bfd_discard_group bfd_generic_discard_group -+#define _bfd_ecoff_section_already_linked _bfd_coff_section_already_linked -+#define _bfd_ecoff_bfd_define_common_symbol bfd_generic_define_common_symbol -+#define _bfd_ecoff_bfd_link_hide_symbol _bfd_generic_link_hide_symbol -+#define _bfd_ecoff_bfd_define_start_stop bfd_generic_define_start_stop -+#define _bfd_ecoff_bfd_link_check_relocs _bfd_generic_link_check_relocs -+ -+/* Installing internal relocations in a section is also generic. */ -+#define _bfd_ecoff_set_reloc _bfd_generic_set_reloc -+ -+const bfd_target sw_64_ecoff_le_vec -+ = {"ecoff-littlesw_64", /* name */ -+ bfd_target_ecoff_flavour, -+ BFD_ENDIAN_LITTLE, /* data byte order is little */ -+ BFD_ENDIAN_LITTLE, /* header byte order is little */ -+ -+ (HAS_RELOC | EXEC_P /* object flags */ -+ | HAS_LINENO | HAS_DEBUG | HAS_SYMS | HAS_LOCALS | DYNAMIC | WP_TEXT -+ | D_PAGED), -+ -+ (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_CODE | SEC_DATA -+ | SEC_SMALL_DATA), -+ 0, /* leading underscore */ -+ ' ', /* ar_pad_char */ -+ 15, /* ar_max_namelen */ -+ 0, /* match priority. */ -+ TARGET_KEEP_UNUSED_SECTION_SYMBOLS, /* keep unused section symbols. */ -+ bfd_getl64, -+ bfd_getl_signed_64, -+ bfd_putl64, -+ bfd_getl32, -+ bfd_getl_signed_32, -+ bfd_putl32, -+ bfd_getl16, -+ bfd_getl_signed_16, -+ bfd_putl16, /* data */ -+ bfd_getl64, -+ bfd_getl_signed_64, -+ bfd_putl64, -+ bfd_getl32, -+ bfd_getl_signed_32, -+ bfd_putl32, -+ bfd_getl16, -+ bfd_getl_signed_16, -+ bfd_putl16, /* hdrs */ -+ -+ {/* bfd_check_format */ -+ _bfd_dummy_target, sw_64_ecoff_object_p, bfd_generic_archive_p, -+ _bfd_dummy_target}, -+ {/* bfd_set_format */ -+ _bfd_bool_bfd_false_error, _bfd_ecoff_mkobject, _bfd_generic_mkarchive, -+ _bfd_bool_bfd_false_error}, -+ {/* bfd_write_contents */ -+ _bfd_bool_bfd_false_error, _bfd_ecoff_write_object_contents, -+ _bfd_write_archive_contents, _bfd_bool_bfd_false_error}, -+ -+ BFD_JUMP_TABLE_GENERIC (_bfd_ecoff), -+ BFD_JUMP_TABLE_COPY (_bfd_ecoff), -+ BFD_JUMP_TABLE_CORE (_bfd_nocore), -+ BFD_JUMP_TABLE_ARCHIVE (sw_64_ecoff), -+ BFD_JUMP_TABLE_SYMBOLS (_bfd_ecoff), -+ BFD_JUMP_TABLE_RELOCS (_bfd_ecoff), -+ BFD_JUMP_TABLE_WRITE (_bfd_ecoff), -+ BFD_JUMP_TABLE_LINK (_bfd_ecoff), -+ BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic), -+ -+ NULL, -+ -+ &sw_64_ecoff_backend_data}; -diff --git a/bfd/config.bfd b/bfd/config.bfd -index bdee5395..85434116 100644 ---- a/bfd/config.bfd -+++ b/bfd/config.bfd -@@ -179,6 +179,7 @@ targ_cpu=`echo $targ | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'` - case "${targ_cpu}" in - aarch64*) targ_archs="bfd_aarch64_arch bfd_arm_arch";; - alpha*) targ_archs=bfd_alpha_arch ;; -+sw_64*) targ_archs=bfd_sw_64_arch ;; - am33_2.0*) targ_archs=bfd_mn10300_arch ;; - arc*) targ_archs=bfd_arc_arch ;; - arm*) targ_archs=bfd_arm_arch ;; -@@ -327,6 +328,55 @@ case "${targ}" in - targ_defvec=alpha_ecoff_le_vec - want64=true - ;; -+ sw_64*-*-freebsd* | sw_64*-*-kfreebsd*-gnu) -+ targ_defvec=sw_64_elf64_fbsd_vec -+ targ_selvecs="sw_64_elf64_vec sw_64_ecoff_le_vec" -+ want64=true -+ # FreeBSD <= 4.0 supports only the old nonstandard way of ABI labelling. -+ case "${targ}" in -+ sw_64*-*-freebsd3* | sw_64*-*-freebsd4 | sw_64*-*-freebsd4.0*) -+ targ_cflags=-DOLD_FREEBSD_ABI_LABEL ;; -+ esac -+ ;; -+ sw_64*-*-netbsd* | sw_64*-*-openbsd*) -+ targ_defvec=sw_64_elf64_vec -+ targ_selvecs=sw_64_ecoff_le_vec -+ want64=true -+ ;; -+ sw_64*-*-netware*) -+ targ_defvec=sw_64_ecoff_le_vec -+ targ_selvecs=sw_64_nlm32_vec -+ want64=true -+ ;; -+ sw_64*-*-linux*ecoff*) -+ targ_defvec=sw_64_ecoff_le_vec -+ targ_selvecs=sw_64_elf64_vec -+ want64=true -+ ;; -+ sw_64-*-linux-* | sw_64-*-elf*) -+ targ_defvec=sw_64_elf64_vec -+ targ_selvecs=sw_64_ecoff_le_vec -+ want64=true -+ ;; -+ sw_64sw6a-*-linux-* | sw_64sw6a-*-elf*) -+ targ_defvec=sw_64_elf64_vec -+ targ_selvecs=sw_64_ecoff_le_vec -+ want64=true -+ ;; -+ sw_64sw6b-*-linux-* | sw_64sw6b-*-elf*) -+ targ_defvec=sw_64_elf64_vec -+ targ_selvecs=sw_64_ecoff_le_vec -+ want64=true -+ ;; -+ sw_64sw8a-*-linux-* | sw_64sw8a-*-elf*) -+ targ_defvec=sw_64_elf64_vec -+ targ_selvecs=sw_64_ecoff_le_vec -+ want64=true -+ ;; -+ sw_64*-*-*) -+ targ_defvec=sw_64_ecoff_le_vec -+ want64=true -+ ;; - amdgcn-*-*) - targ_defvec=amdgcn_elf64_le_vec - want64=true -diff --git a/bfd/config.in b/bfd/config.in -index 7ff3eeeb..6b0ac52c 100644 ---- a/bfd/config.in -+++ b/bfd/config.in -@@ -363,3 +363,5 @@ - - /* Use structured /proc on Solaris. */ - #undef _STRUCTURED_PROC -+ -+#undef TARGET_SW_64 -diff --git a/bfd/configure b/bfd/configure -index 910af3ce..493bac83 100755 ---- a/bfd/configure -+++ b/bfd/configure -@@ -12003,6 +12003,11 @@ i[3-7]86-*-linux-* | x86_64-*-linux-*) - ac_default_ld_z_separate_code=1 - fi - ;; -+sw_64-*-linux-*) -+cat >>confdefs.h <<_ACEOF -+#define TARGET_SW_64 -+_ACEOF -+ ;; - esac - if test "${ac_default_ld_z_separate_code}" = unset; then - ac_default_ld_z_separate_code=0 -@@ -13847,6 +13852,10 @@ do - alpha_elf64_fbsd_vec) tb="$tb elf64-alpha.lo elf64.lo $elf"; target_size=64 ;; - alpha_vms_vec) tb="$tb vms-alpha.lo vms-misc.lo vms-lib.lo"; target_size=64 ;; - alpha_vms_lib_txt_vec) tb="$tb vms-lib.lo vms-misc.lo" ;; -+ sw_64_ecoff_le_vec) tb="$tb coff-sw_64.lo ecoff.lo $ecoff"; target_size=64 ;; -+ sw_64_elf64_vec) tb="$tb elf64-sw_64.lo elf64.lo $elf"; target_size=64 ;; -+ sw_64_elf64_fbsd_vec) tb="$tb elf64-sw_64.lo elf64.lo $elf"; target_size=64 ;; -+ sw_64_nlm32_vec) tb="$tb nlm32-sw_64.lo nlm32.lo nlm.lo"; target_size=64 ;; - am33_elf32_linux_vec) tb="$tb elf32-am33lin.lo elf32.lo $elf" ;; - amdgcn_elf64_le_vec) tb="$tb elf64-amdgcn.lo elf64.lo $elf"; target_size=64 ;; - aout0_be_vec) tb="$tb aout0.lo aout32.lo" ;; -@@ -14253,7 +14262,20 @@ if test "${target}" = "${host}"; then - COREFILE=netbsd-core.lo - ;; - alpha*-*-*) -- COREFILE=osf-core.lo -+ COREFILE=osf-core.lo -+ ;; -+ sw_64*-*-freebsd* | sw_64*-*-kfreebsd*-gnu | sw_64*-*-*vms*) -+ COREFILE='' -+ ;; -+ sw_64*-*-linux-*) -+ COREFILE=trad-core.lo -+ TRAD_HEADER='"hosts/sw_64linux.h"' -+ ;; -+ sw_64*-*-netbsd* | sw_64*-*-openbsd*) -+ COREFILE=netbsd-core.lo -+ ;; -+ sw_64*-*-*) -+ COREFILE=osf-core.lo - ;; - arm-*-freebsd* | arm-*-kfreebsd*-gnu) - COREFILE='' ;; -diff --git a/bfd/configure.ac b/bfd/configure.ac -index f044616f..160b1351 100644 ---- a/bfd/configure.ac -+++ b/bfd/configure.ac -@@ -414,6 +414,10 @@ do - alpha_elf64_fbsd_vec) tb="$tb elf64-alpha.lo elf64.lo $elf"; target_size=64 ;; - alpha_vms_vec) tb="$tb vms-alpha.lo vms-misc.lo vms-lib.lo"; target_size=64 ;; - alpha_vms_lib_txt_vec) tb="$tb vms-lib.lo vms-misc.lo" ;; -+ sw_64_ecoff_le_vec) tb="$tb coff-sw_64.lo ecoff.lo $ecoff"; target_size=64 ;; -+ sw_64_elf64_vec) tb="$tb elf64-sw_64.lo elf64.lo $elf"; target_size=64 ;; -+ sw_64_elf64_fbsd_vec) tb="$tb elf64-sw_64.lo elf64.lo $elf"; target_size=64 ;; -+ sw_64_nlm32_vec) tb="$tb nlm32-sw_64.lo nlm32.lo nlm.lo"; target_size=64 ;; - am33_elf32_linux_vec) tb="$tb elf32-am33lin.lo elf32.lo $elf" ;; - amdgcn_elf64_le_vec) tb="$tb elf64-amdgcn.lo elf64.lo $elf"; target_size=64 ;; - aout0_be_vec) tb="$tb aout0.lo aout32.lo" ;; -diff --git a/bfd/configure.com b/bfd/configure.com -index 4fb6855e..06c42239 100644 ---- a/bfd/configure.com -+++ b/bfd/configure.com -@@ -26,9 +26,10 @@ $! - $ arch=F$GETSYI("ARCH_NAME") - $ arch=F$EDIT(arch,"LOWERCASE") - $if arch .eqs. "alpha" then target = "alpha" -+$if arch .eqs. "sw_64" then target = "sw_64" - $if arch .eqs. "ia64" then target = "ia64" - $! --$if (arch .eqs. "alpha") .or. (arch .eqs. "ia64") -+$if (arch .eqs. "alpha") .or. (arch .eqs. "ia64") .or. (arch .eqs. "sw_64") - $then - $! - $ write sys$output "Configuring BFD for ''target' target" -diff --git a/bfd/cpu-sw_64.c b/bfd/cpu-sw_64.c -new file mode 100644 -index 00000000..5dc347c2 ---- /dev/null -+++ b/bfd/cpu-sw_64.c -@@ -0,0 +1,54 @@ -+/* BFD support for the Sw_64 architecture. -+ Copyright (C) 1992-2023 Free Software Foundation, Inc. -+ -+ This file is part of BFD, the Binary File Descriptor library. -+ -+ This program is free software; you can redistribute it and/or modify -+ it under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 3 of the License, or -+ (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ GNU General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, -+ MA 02110-1301, USA. */ -+ -+#include "sysdep.h" -+#include "bfd.h" -+#include "libbfd.h" -+ -+#define N(BITS_WORD, BITS_ADDR, NUMBER, PRINT, DEFAULT, NEXT) \ -+ { \ -+ BITS_WORD, /* Bits in a word. */ \ -+ BITS_ADDR, /* Bits in an address. */ \ -+ 8, /* Bits in a byte. */ \ -+ bfd_arch_sw_64, NUMBER, "sw_64", PRINT, \ -+ 3, /* Section alignment power. */ \ -+ DEFAULT, bfd_default_compatible, bfd_default_scan, \ -+ bfd_arch_default_fill, NEXT, \ -+ 0 /* Maximum offset of a reloc from the start of an insn. */ \ -+ } -+ -+enum -+{ -+ I_sw6a, -+ I_sw6b, -+ I_sw8a -+}; -+ -+#define NN(index) (&arch_info_struct[(index) + 1]) -+static const bfd_arch_info_type arch_info_struct[] = { -+ N (64, 64, bfd_mach_sw_64_sw6a, "sw_64:4", false, NN (I_sw6a)), -+ N (64, 64, bfd_mach_sw_64_sw6a, "sw_64:4", false, NN (I_sw6b)), -+ /* The next element of the last one should be NULL. */ -+ N (64, 64, bfd_mach_sw_64_sw6b, "sw_64:8", false, NN (I_sw8a)), -+ N (64, 64, bfd_mach_sw_64_sw8a, "sw_64:12", false, NULL), -+}; -+ -+const bfd_arch_info_type bfd_sw_64_arch -+ = N (64, 64, 0, "sw_64", false, &arch_info_struct[0]); -diff --git a/bfd/ecoff.c b/bfd/ecoff.c -index 522a4425..bbd979b0 100644 ---- a/bfd/ecoff.c -+++ b/bfd/ecoff.c -@@ -222,6 +222,13 @@ _bfd_ecoff_set_arch_mach_hook (bfd *abfd, void * filehdr) - mach = 0; - break; - -+#ifdef TARGET_SW_64 -+ case SW_64_MAGIC: -+ arch = bfd_arch_sw_64; -+ mach = 0; -+ break; -+#endif -+ - default: - arch = bfd_arch_obscure; - mach = 0; -@@ -275,6 +282,11 @@ ecoff_get_magic (bfd *abfd) - case bfd_arch_alpha: - return ALPHA_MAGIC; - -+#ifdef TARGET_SW_64 -+ case bfd_arch_sw_64: -+ return SW_64_MAGIC; -+#endif -+ - default: - abort (); - return 0; -diff --git a/bfd/elf-bfd.h b/bfd/elf-bfd.h -index ec856764..7e9fb196 100644 ---- a/bfd/elf-bfd.h -+++ b/bfd/elf-bfd.h -@@ -533,6 +533,9 @@ enum elf_target_id - { - AARCH64_ELF_DATA = 1, - ALPHA_ELF_DATA, -+#ifdef TARGET_SW_64 -+ SW_64_ELF_DATA, -+#endif - AMDGCN_ELF_DATA, - ARC_ELF_DATA, - ARM_ELF_DATA, -diff --git a/bfd/elf.c b/bfd/elf.c -index d38e0aff..ef1ba0b6 100644 ---- a/bfd/elf.c -+++ b/bfd/elf.c -@@ -2116,6 +2116,9 @@ _bfd_elf_get_dynamic_symbols (bfd *abfd, Elf_Internal_Phdr *phdr, - switch (bed->elf_machine_code) - { - case EM_ALPHA: -+#ifdef TARGET_SW_64 -+ case EM_SW_64: -+#endif - case EM_S390: - case EM_S390_OLD: - if (bed->s->elfclass == ELFCLASS64) -@@ -11794,6 +11797,9 @@ elfcore_grok_netbsd_note (bfd *abfd, Elf_Internal_Note *note) - - case bfd_arch_aarch64: - case bfd_arch_alpha: -+#ifdef TARGET_SW_64 -+ case bfd_arch_sw_64: -+#endif - case bfd_arch_sparc: - switch (note->type) - { -diff --git a/bfd/elf64-sw_64.c b/bfd/elf64-sw_64.c -new file mode 100644 -index 00000000..1d24bfc3 ---- /dev/null -+++ b/bfd/elf64-sw_64.c -@@ -0,0 +1,5635 @@ -+/* Sw_64 specific support for 64-bit ELF -+ Copyright (C) 1996-2023 Free Software Foundation, Inc. -+ Contributed by Richard Henderson . -+ -+ This file is part of BFD, the Binary File Descriptor library. -+ -+ This program is free software; you can redistribute it and/or modify -+ it under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 3 of the License, or -+ (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ GNU General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, -+ MA 02110-1301, USA. */ -+ -+/* We need a published ABI spec for this. Until one comes out, don't -+ assume this'll remain unchanged forever. */ -+ -+#include "sysdep.h" -+#include "bfd.h" -+#include "libbfd.h" -+#include "elf-bfd.h" -+#include "ecoff-bfd.h" -+ -+#include "elf/sw_64.h" -+ -+#define SW_64ECOFF -+ -+#define NO_COFF_RELOCS -+#define NO_COFF_SYMBOLS -+#define NO_COFF_LINENOS -+ -+/* Get the ECOFF swapping routines. Needed for the debug information. */ -+#include "coff/internal.h" -+#include "coff/sym.h" -+#include "coff/symconst.h" -+#include "coff/ecoff.h" -+#include "coff/sw_64.h" -+#include "aout/ar.h" -+#include "libcoff.h" -+#include "libecoff.h" -+#define ECOFF_64 -+#include "ecoffswap.h" -+ -+/* Instruction data for plt generation and relaxation. */ -+ -+#define OP_LDI 0x3eU -+#define OP_LDIH 0x3fU -+#define OP_LDL 0x23U -+#define OP_BR 0x04U -+#define OP_BSR 0x05U -+ -+#define INSN_LDI (OP_LDI << 26) -+#define INSN_LDIH (OP_LDIH << 26) -+#define INSN_LDL (OP_LDL << 26) -+#define INSN_BR (OP_BR << 26) -+ -+#define OP_LDW 0x22 -+#define INSN_LDW (OP_LDW << 26) -+ -+#define INSN_ADDL 0x40000100 -+#define INSN_RDUNIQ 0x0000009e -+#define INSN_SUBL 0x40000120 -+#define INSN_S4SUBL 0x40000160 -+#define INSN_UNOP 0x43ff075f -+ -+#define INSN_ADDPI (((0x10) & 0x3F) << 26) | (((0x1e) & 0xFF) << 5) | 26 -+#define INSN_JSR 0x04000000 -+#define INSN_JMP 0x0c000000 -+#define INSN_JSR_MASK 0xfc000000 -+#define INSN_LDL_MASK 0xfc000000 -+ -+#define INSN_A(I, A) (I | ((unsigned) A << 21)) -+#define INSN_AB(I, A, B) (INSN_A (I, A) | (B << 16)) -+#define INSN_ABC(I, A, B, C) (INSN_A (I, A) | (B << 16) | C) -+#define INSN_ABO(I, A, B, O) (INSN_A (I, A) | (B << 16) | ((O) &0xffff)) -+#define INSN_AD(I, A, D) (INSN_A (I, A) | (((D) >> 2) & 0x1fffff)) -+ -+/* PLT/GOT Stuff */ -+ -+/* Set by ld emulation. Putting this into the link_info or hash structure -+ is simply working too hard. */ -+#ifdef USE_SECUREPLT -+bool elf64_sw_64_use_secureplt = true; -+#else -+bool elf64_sw_64_use_secureplt = false; -+#endif -+ -+#define OLD_PLT_HEADER_SIZE 32 -+#define OLD_PLT_ENTRY_SIZE 12 -+#define NEW_PLT_HEADER_SIZE 36 -+#define NEW_PLT_ENTRY_SIZE 4 -+ -+#define PLT_HEADER_SIZE \ -+ (elf64_sw_64_use_secureplt ? NEW_PLT_HEADER_SIZE : OLD_PLT_HEADER_SIZE) -+#define PLT_ENTRY_SIZE \ -+ (elf64_sw_64_use_secureplt ? NEW_PLT_ENTRY_SIZE : OLD_PLT_ENTRY_SIZE) -+ -+#define MAX_GOT_SIZE_NEW (1024 * 1024 * 2048 - 1) -+ -+#define MAX_GOT_SIZE (64 * 1024) -+ -+#define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so" -+ -+/* Used to implement multiple .got subsections. */ -+struct sw_64_elf_got_entry -+{ -+ struct sw_64_elf_got_entry *next; -+ -+ /* Which .got subsection? */ -+ bfd *gotobj; -+ -+ /* The addend in effect for this entry. */ -+ bfd_vma addend; -+ -+ /* The .got offset for this entry. */ -+ int got_offset; -+ -+ /* The .plt offset for this entry. */ -+ int plt_offset; -+ -+ /* How many references to this entry? */ -+ int use_count; -+ -+ /* The relocation type of this entry. */ -+ unsigned char reloc_type; -+ -+ /* How a LITERAL is used. */ -+ unsigned char flags; -+ -+ /* Have we initialized the dynamic relocation for this entry? */ -+ unsigned char reloc_done; -+ -+ /* Have we adjusted this entry for SEC_MERGE? */ -+ unsigned char reloc_xlated; -+}; -+ -+struct sw_64_elf_reloc_entry -+{ -+ struct sw_64_elf_reloc_entry *next; -+ -+ /* Which .reloc section? */ -+ asection *srel; -+ -+ /* Which section this relocation is against? */ -+ asection *sec; -+ -+ /* How many did we find? */ -+ unsigned long count; -+ -+ /* What kind of relocation? */ -+ unsigned int rtype; -+}; -+ -+struct sw_64_elf_link_hash_entry -+{ -+ struct elf_link_hash_entry root; -+ -+ /* External symbol information. */ -+ EXTR esym; -+ -+ /* Cumulative flags for all the .got entries. */ -+ int flags; -+ -+ /* Contexts in which a literal was referenced. */ -+#define SW_64_ELF_LINK_HASH_LU_ADDR 0x01 -+#define SW_64_ELF_LINK_HASH_LU_MEM 0x02 -+#define SW_64_ELF_LINK_HASH_LU_BYTE 0x04 -+#define SW_64_ELF_LINK_HASH_LU_JSR 0x08 -+#define SW_64_ELF_LINK_HASH_LU_TLSGD 0x10 -+#define SW_64_ELF_LINK_HASH_LU_TLSLDM 0x20 -+#define SW_64_ELF_LINK_HASH_LU_JSRDIRECT 0x40 -+#define SW_64_ELF_LINK_HASH_LU_PLT 0x38 -+#define SW_64_ELF_LINK_HASH_TLS_IE 0x80 -+ -+ /* Used to implement multiple .got subsections. */ -+ struct sw_64_elf_got_entry *got_entries; -+ -+ /* Used to count non-got, non-plt relocations for delayed sizing -+ of relocation sections. */ -+ struct sw_64_elf_reloc_entry *reloc_entries; -+}; -+ -+/* Sw_64 ELF linker hash table. */ -+ -+struct sw_64_elf_link_hash_table -+{ -+ struct elf_link_hash_table root; -+ -+ /* The head of a list of .got subsections linked through -+ sw_64_elf_tdata (abfd)->got_link_next. */ -+ bfd *got_list; -+ -+ /* The most recent relax pass that we've seen. The GOTs -+ should be regenerated if this doesn't match. */ -+ int relax_trip; -+}; -+ -+/* Look up an entry in a Sw_64 ELF linker hash table. */ -+ -+#define sw_64_elf_link_hash_lookup(table, string, create, copy, follow) \ -+ ((struct sw_64_elf_link_hash_entry *) elf_link_hash_lookup ( \ -+ &(table)->root, (string), (create), (copy), (follow))) -+ -+/* Traverse a Sw_64 ELF linker hash table. */ -+ -+#define sw_64_elf_link_hash_traverse(table, func, info) \ -+ (elf_link_hash_traverse ( \ -+ &(table)->root, (bool (*) (struct elf_link_hash_entry *, void *)) (func), \ -+ (info))) -+ -+/* Get the Sw_64 ELF linker hash table from a link_info structure. */ -+ -+#define sw_64_elf_hash_table(p) \ -+ ((is_elf_hash_table ((p)->hash) \ -+ && elf_hash_table_id (elf_hash_table (p)) == SW_64_ELF_DATA) \ -+ ? (struct sw_64_elf_link_hash_table *) (p)->hash \ -+ : NULL) -+ -+/* Get the object's symbols as our own entry type. */ -+ -+#define sw_64_elf_sym_hashes(abfd) \ -+ ((struct sw_64_elf_link_hash_entry **) elf_sym_hashes (abfd)) -+ -+/* Should we do dynamic things to this symbol? This differs from the -+ generic version in that we never need to consider function pointer -+ equality wrt PLT entries -- we don't create a PLT entry if a symbol's -+ address is ever taken. */ -+ -+static inline bool -+sw_64_elf_dynamic_symbol_p (struct elf_link_hash_entry *h, -+ struct bfd_link_info *info) -+{ -+ return _bfd_elf_dynamic_symbol_p (h, info, 0); -+} -+ -+/* Create an entry in a Sw_64 ELF linker hash table. */ -+ -+static struct bfd_hash_entry * -+elf64_sw_64_link_hash_newfunc (struct bfd_hash_entry *entry, -+ struct bfd_hash_table *table, const char *string) -+{ -+ struct sw_64_elf_link_hash_entry *ret -+ = (struct sw_64_elf_link_hash_entry *) entry; -+ -+ /* Allocate the structure if it has not already been allocated by a -+ subclass. */ -+ if (ret == (struct sw_64_elf_link_hash_entry *) NULL) -+ ret = ((struct sw_64_elf_link_hash_entry *) bfd_hash_allocate ( -+ table, sizeof (struct sw_64_elf_link_hash_entry))); -+ if (ret == (struct sw_64_elf_link_hash_entry *) NULL) -+ return (struct bfd_hash_entry *) ret; -+ -+ /* Call the allocation method of the superclass. */ -+ ret = ((struct sw_64_elf_link_hash_entry *) _bfd_elf_link_hash_newfunc ( -+ (struct bfd_hash_entry *) ret, table, string)); -+ if (ret != (struct sw_64_elf_link_hash_entry *) NULL) -+ { -+ /* Set local fields. */ -+ memset (&ret->esym, 0, sizeof (EXTR)); -+ /* We use -2 as a marker to indicate that the information has -+ not been set. -1 means there is no associated ifd. */ -+ ret->esym.ifd = -2; -+ ret->flags = 0; -+ ret->got_entries = NULL; -+ ret->reloc_entries = NULL; -+ } -+ -+ return (struct bfd_hash_entry *) ret; -+} -+ -+/* Create a Sw_64 ELF linker hash table. */ -+ -+static struct bfd_link_hash_table * -+elf64_sw_64_bfd_link_hash_table_create (bfd *abfd) -+{ -+ struct sw_64_elf_link_hash_table *ret; -+ size_t amt = sizeof (struct sw_64_elf_link_hash_table); -+ -+ ret = (struct sw_64_elf_link_hash_table *) bfd_zmalloc (amt); -+ if (ret == (struct sw_64_elf_link_hash_table *) NULL) -+ return NULL; -+ -+ if (!_bfd_elf_link_hash_table_init (&ret->root, abfd, -+ elf64_sw_64_link_hash_newfunc, -+ sizeof (struct sw_64_elf_link_hash_entry), -+ SW_64_ELF_DATA)) -+ { -+ free (ret); -+ return NULL; -+ } -+ -+ return &ret->root.root; -+} -+ -+/* Sw_64 ELF follows MIPS ELF in using a special find_nearest_line -+ routine in order to handle the ECOFF debugging information. */ -+ -+struct sw_64_elf_find_line -+{ -+ struct ecoff_debug_info d; -+ struct ecoff_find_line i; -+}; -+ -+/* We have some private fields hanging off of the elf_tdata structure. */ -+ -+struct sw_64_elf_obj_tdata -+{ -+ struct elf_obj_tdata root; -+ -+ /* For every input file, these are the got entries for that object's -+ local symbols. */ -+ struct sw_64_elf_got_entry **local_got_entries; -+ -+ /* For every input file, this is the object that owns the got that -+ this input file uses. */ -+ bfd *gotobj; -+ -+ /* For every got, this is a linked list through the objects using this got. */ -+ bfd *in_got_link_next; -+ -+ /* For every got, this is a link to the next got subsegment. */ -+ bfd *got_link_next; -+ -+ /* For every got, this is the section. */ -+ asection *got; -+ -+ /* For every got, this is it's total number of words. */ -+ int total_got_size; -+ -+ /* For every got, this is the sum of the number of words required -+ to hold all of the member object's local got. */ -+ int local_got_size; -+ -+ /* Used by elf64_sw_64_find_nearest_line entry point. */ -+ struct sw_64_elf_find_line *find_line_info; -+}; -+ -+#define sw_64_elf_tdata(abfd) ((struct sw_64_elf_obj_tdata *) (abfd)->tdata.any) -+ -+#define is_sw_64_elf(bfd) \ -+ (bfd_get_flavour (bfd) == bfd_target_elf_flavour && elf_tdata (bfd) != NULL \ -+ && elf_object_id (bfd) == SW_64_ELF_DATA) -+ -+static bool -+elf64_sw_64_mkobject (bfd *abfd) -+{ -+ return bfd_elf_allocate_object (abfd, sizeof (struct sw_64_elf_obj_tdata), -+ SW_64_ELF_DATA); -+} -+ -+/* Return the MACH for a sw_64 e_flags value. */ -+unsigned long -+bfd_elf_sw_64_mach (flagword flags) -+{ -+ switch (flags) -+ { -+ case E_SW_64_MACH_SW6A: -+ return bfd_mach_sw_64_sw6a; -+ case E_SW_64_MACH_SW6B: -+ return bfd_mach_sw_64_sw6b; -+ case E_SW_64_MACH_SW8A: -+ return bfd_mach_sw_64_sw8a; -+ default: -+ return 0; -+ } -+ return 0; -+} -+ -+static bool -+elf64_sw_64_object_p (bfd *abfd) -+{ -+ /* Set the right machine number for an Sw_64 ELF file. */ -+ unsigned long mach; -+ -+ mach = bfd_elf_sw_64_mach (elf_elfheader (abfd)->e_flags); -+ return bfd_default_set_arch_mach (abfd, bfd_arch_sw_64, mach); -+} -+ -+/* A relocation function which doesn't do anything. */ -+ -+static bfd_reloc_status_type -+elf64_sw_64_reloc_nil (bfd *abfd ATTRIBUTE_UNUSED, arelent *reloc, -+ asymbol *sym ATTRIBUTE_UNUSED, -+ void *data ATTRIBUTE_UNUSED, asection *sec, -+ bfd *output_bfd, char **error_message ATTRIBUTE_UNUSED) -+{ -+ if (output_bfd) -+ reloc->address += sec->output_offset; -+ return bfd_reloc_ok; -+} -+ -+/* A relocation function used for an unsupported reloc. */ -+ -+static bfd_reloc_status_type -+elf64_sw_64_reloc_bad (bfd *abfd ATTRIBUTE_UNUSED, arelent *reloc, -+ asymbol *sym ATTRIBUTE_UNUSED, -+ void *data ATTRIBUTE_UNUSED, asection *sec, -+ bfd *output_bfd, char **error_message ATTRIBUTE_UNUSED) -+{ -+ if (output_bfd) -+ reloc->address += sec->output_offset; -+ return bfd_reloc_notsupported; -+} -+ -+/* Do the work of the GPDISP relocation. */ -+ -+static bfd_reloc_status_type -+elf64_sw_64_do_reloc_gpdisp (bfd *abfd, bfd_vma gpdisp, bfd_byte *p_ldih, -+ bfd_byte *p_ldi) -+{ -+ bfd_reloc_status_type ret = bfd_reloc_ok; -+ bfd_vma addend; -+ unsigned long i_ldih, i_ldi; -+ -+ i_ldih = bfd_get_32 (abfd, p_ldih); -+ i_ldi = bfd_get_32 (abfd, p_ldi); -+ -+ /* Complain if the instructions are not correct. */ -+ if (((i_ldih >> 26) & 0x3f) != 0x3f || ((i_ldi >> 26) & 0x3f) != 0x3e) -+ ret = bfd_reloc_dangerous; -+ -+ /* Extract the user-supplied offset, mirroring the sign extensions -+ that the instructions perform. */ -+ addend = ((i_ldih & 0xffff) << 16) | (i_ldi & 0xffff); -+ addend = (addend ^ 0x80008000) - 0x80008000; -+ -+ gpdisp += addend; -+ -+ if ((bfd_signed_vma) gpdisp < -(bfd_signed_vma) 0x80000000 -+ || (bfd_signed_vma) gpdisp >= (bfd_signed_vma) 0x7fff8000) -+ ret = bfd_reloc_overflow; -+ -+ /* compensate for the sign extension again. */ -+ i_ldih = ((i_ldih & 0xffff0000) -+ | (((gpdisp >> 16) + ((gpdisp >> 15) & 1)) & 0xffff)); -+ i_ldi = (i_ldi & 0xffff0000) | (gpdisp & 0xffff); -+ -+ bfd_put_32 (abfd, (bfd_vma) i_ldih, p_ldih); -+ bfd_put_32 (abfd, (bfd_vma) i_ldi, p_ldi); -+ -+ return ret; -+} -+ -+/* The special function for the GPDISP reloc. */ -+ -+static bfd_reloc_status_type -+elf64_sw_64_reloc_gpdisp (bfd *abfd, arelent *reloc_entry, -+ asymbol *sym ATTRIBUTE_UNUSED, void *data, -+ asection *input_section, bfd *output_bfd, -+ char **err_msg) -+{ -+ bfd_reloc_status_type ret; -+ bfd_vma gp, relocation; -+ bfd_vma high_address; -+ bfd_byte *p_ldih, *p_ldi; -+ -+ /* Don't do anything if we're not doing a final link. */ -+ if (output_bfd) -+ { -+ reloc_entry->address += input_section->output_offset; -+ return bfd_reloc_ok; -+ } -+ -+ high_address = bfd_get_section_limit (abfd, input_section); -+ if (reloc_entry->address > high_address -+ || reloc_entry->address + reloc_entry->addend > high_address) -+ return bfd_reloc_outofrange; -+ -+ /* The gp used in the portion of the output object to which this -+ input object belongs is cached on the input bfd. */ -+ gp = _bfd_get_gp_value (abfd); -+ -+ relocation = (input_section->output_section->vma -+ + input_section->output_offset + reloc_entry->address); -+ -+ p_ldih = (bfd_byte *) data + reloc_entry->address; -+ p_ldi = p_ldih + reloc_entry->addend; -+ -+ ret = elf64_sw_64_do_reloc_gpdisp (abfd, gp - relocation, p_ldih, p_ldi); -+ -+ /* Complain if the instructions are not correct. */ -+ if (ret == bfd_reloc_dangerous) -+ *err_msg = _ ("GPDISP relocation did not find ldih and ldi instructions"); -+ -+ return ret; -+} -+ -+/* In case we're on a 32-bit machine, construct a 64-bit "-1" value -+ from smaller values. Start with zero, widen, *then* decrement. */ -+#define MINUS_ONE (((bfd_vma) 0) - 1) -+ -+#define SKIP_HOWTO(N) \ -+ HOWTO (N, 0, 0, 0, 0, 0, complain_overflow_dont, elf64_sw_64_reloc_bad, 0, \ -+ 0, 0, 0, 0) -+ -+static reloc_howto_type elf64_sw_64_howto_table[] = { -+ HOWTO (R_SW_64_NONE, /* type */ -+ 0, /* rightshift */ -+ 0, /* size (0 = byte, 1 = short, 2 = long) */ -+ 0, /* bitsize */ -+ true, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont, /* complain_on_overflow */ -+ elf64_sw_64_reloc_nil, /* special_function */ -+ "NONE", /* name */ -+ false, /* partial_inplace */ -+ 0, /* src_mask */ -+ 0, /* dst_mask */ -+ true), /* pcrel_offset */ -+ -+ /* A 32 bit reference to a symbol. */ -+ HOWTO (R_SW_64_REFLONG, /* type */ -+ 0, /* rightshift */ -+ 4, /* size (0 = byte, 1 = short, 2 = long) */ -+ 32, /* bitsize */ -+ false, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_bitfield, /* complain_on_overflow */ -+ bfd_elf_generic_reloc, /* special_function */ -+ "REFLONG", /* name */ -+ false, /* partial_inplace */ -+ 0xffffffff, /* src_mask */ -+ 0xffffffff, /* dst_mask */ -+ false), /* pcrel_offset */ -+ -+ /* A 64 bit reference to a symbol. */ -+ HOWTO (R_SW_64_REFQUAD, /* type */ -+ 0, /* rightshift */ -+ 8, /* size (0 = byte, 1 = short, 2 = long) */ -+ 64, /* bitsize */ -+ false, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_bitfield, /* complain_on_overflow */ -+ bfd_elf_generic_reloc, /* special_function */ -+ "REFQUAD", /* name */ -+ false, /* partial_inplace */ -+ MINUS_ONE, /* src_mask */ -+ MINUS_ONE, /* dst_mask */ -+ false), /* pcrel_offset */ -+ -+ /* A 32 bit GP relative offset. This is just like REFLONG except -+ that when the value is used the value of the gp register will be -+ added in. */ -+ HOWTO (R_SW_64_GPREL32, /* type */ -+ 0, /* rightshift */ -+ 4, /* size (0 = byte, 1 = short, 2 = long) */ -+ 32, /* bitsize */ -+ false, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_bitfield, /* complain_on_overflow */ -+ bfd_elf_generic_reloc, /* special_function */ -+ "GPREL32", /* name */ -+ false, /* partial_inplace */ -+ 0xffffffff, /* src_mask */ -+ 0xffffffff, /* dst_mask */ -+ false), /* pcrel_offset */ -+ -+ /* Used for an instruction that refers to memory off the GP register. */ -+ HOWTO (R_SW_64_LITERAL, /* type */ -+ 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ 16, /* bitsize */ -+ false, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_signed, /* complain_on_overflow */ -+ bfd_elf_generic_reloc, /* special_function */ -+ "ELF_LITERAL", /* name */ -+ false, /* partial_inplace */ -+ 0xffff, /* src_mask */ -+ 0xffff, /* dst_mask */ -+ false), /* pcrel_offset */ -+ -+ /* This reloc only appears immediately following an ELF_LITERAL reloc. -+ It identifies a use of the literal. The symbol index is special: -+ 1 means the literal address is in the base register of a memory -+ format instruction; 2 means the literal address is in the byte -+ offset register of a byte-manipulation instruction; 3 means the -+ literal address is in the target register of a jsr instruction. -+ This does not actually do any relocation. */ -+ HOWTO (R_SW_64_LITUSE, /* type */ -+ 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ 32, /* bitsize */ -+ false, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont, /* complain_on_overflow */ -+ elf64_sw_64_reloc_nil, /* special_function */ -+ "LITUSE", /* name */ -+ false, /* partial_inplace */ -+ 0, /* src_mask */ -+ 0, /* dst_mask */ -+ false), /* pcrel_offset */ -+ -+ /* Load the gp register. This is always used for a ldih instruction -+ which loads the upper 16 bits of the gp register. The symbol -+ index of the GPDISP instruction is an offset in bytes to the ldi -+ instruction that loads the lower 16 bits. The value to use for -+ the relocation is the difference between the GP value and the -+ current location; the load will always be done against a register -+ holding the current address. -+ -+ NOTE: Unlike ECOFF, partial in-place relocation is not done. If -+ any offset is present in the instructions, it is an offset from -+ the register to the ldih instruction. This lets us avoid any -+ stupid hackery like inventing a gp value to do partial relocation -+ against. Also unlike ECOFF, we do the whole relocation off of -+ the GPDISP rather than a GPDISP_HI16/GPDISP_LO16 pair. An odd, -+ space consuming bit, that, since all the information was present -+ in the GPDISP_HI16 reloc. */ -+ HOWTO (R_SW_64_GPDISP, /* type */ -+ 16, /* rightshift */ -+ 4, /* size (0 = byte, 1 = short, 2 = long) */ -+ 16, /* bitsize */ -+ false, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont, /* complain_on_overflow */ -+ elf64_sw_64_reloc_gpdisp, /* special_function */ -+ "GPDISP", /* name */ -+ false, /* partial_inplace */ -+ 0xffff, /* src_mask */ -+ 0xffff, /* dst_mask */ -+ true), /* pcrel_offset */ -+ -+ /* A 21 bit branch. */ -+ HOWTO (R_SW_64_BRADDR, /* type */ -+ 2, /* rightshift */ -+ 4, /* size (0 = byte, 1 = short, 2 = long) */ -+ 21, /* bitsize */ -+ true, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_signed, /* complain_on_overflow */ -+ bfd_elf_generic_reloc, /* special_function */ -+ "BRADDR", /* name */ -+ false, /* partial_inplace */ -+ 0x1fffff, /* src_mask */ -+ 0x1fffff, /* dst_mask */ -+ true), /* pcrel_offset */ -+ -+ /* A hint for a jump to a register. */ -+ HOWTO (R_SW_64_HINT, /* type */ -+ 2, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ 16, /* bitsize */ -+ true, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont, /* complain_on_overflow */ -+ bfd_elf_generic_reloc, /* special_function */ -+ "HINT", /* name */ -+ false, /* partial_inplace */ -+ 0xffff, /* src_mask */ -+ 0xffff, /* dst_mask */ -+ true), /* pcrel_offset */ -+ -+ /* 16 bit PC relative offset. */ -+ HOWTO (R_SW_64_SREL16, /* type */ -+ 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ 16, /* bitsize */ -+ true, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_signed, /* complain_on_overflow */ -+ bfd_elf_generic_reloc, /* special_function */ -+ "SREL16", /* name */ -+ false, /* partial_inplace */ -+ 0xffff, /* src_mask */ -+ 0xffff, /* dst_mask */ -+ true), /* pcrel_offset */ -+ -+ /* 32 bit PC relative offset. */ -+ HOWTO (R_SW_64_SREL32, /* type */ -+ 0, /* rightshift */ -+ 4, /* size (0 = byte, 1 = short, 2 = long) */ -+ 32, /* bitsize */ -+ true, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_signed, /* complain_on_overflow */ -+ bfd_elf_generic_reloc, /* special_function */ -+ "SREL32", /* name */ -+ false, /* partial_inplace */ -+ 0xffffffff, /* src_mask */ -+ 0xffffffff, /* dst_mask */ -+ true), /* pcrel_offset */ -+ -+ /* A 64 bit PC relative offset. */ -+ HOWTO (R_SW_64_SREL64, /* type */ -+ 0, /* rightshift */ -+ 8, /* size (0 = byte, 1 = short, 2 = long) */ -+ 64, /* bitsize */ -+ true, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_signed, /* complain_on_overflow */ -+ bfd_elf_generic_reloc, /* special_function */ -+ "SREL64", /* name */ -+ false, /* partial_inplace */ -+ MINUS_ONE, /* src_mask */ -+ MINUS_ONE, /* dst_mask */ -+ true), /* pcrel_offset */ -+ -+ /* Skip 12 - 16; deprecated ECOFF relocs. */ -+ SKIP_HOWTO (12), SKIP_HOWTO (13), SKIP_HOWTO (14), SKIP_HOWTO (15), -+ SKIP_HOWTO (16), -+ -+ /* The high 16 bits of the displacement from GP to the target. */ -+ HOWTO (R_SW_64_GPRELHIGH, 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ 16, /* bitsize */ -+ false, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_signed, /* complain_on_overflow */ -+ bfd_elf_generic_reloc, /* special_function */ -+ "GPRELHIGH", /* name */ -+ false, /* partial_inplace */ -+ 0xffff, /* src_mask */ -+ 0xffff, /* dst_mask */ -+ false), /* pcrel_offset */ -+ -+ /* The low 16 bits of the displacement from GP to the target. */ -+ HOWTO (R_SW_64_GPRELLOW, 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ 16, /* bitsize */ -+ false, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont, /* complain_on_overflow */ -+ bfd_elf_generic_reloc, /* special_function */ -+ "GPRELLOW", /* name */ -+ false, /* partial_inplace */ -+ 0xffff, /* src_mask */ -+ 0xffff, /* dst_mask */ -+ false), /* pcrel_offset */ -+ -+ /* A 16-bit displacement from the GP to the target. */ -+ HOWTO (R_SW_64_GPREL16, 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ 16, /* bitsize */ -+ false, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_signed, /* complain_on_overflow */ -+ bfd_elf_generic_reloc, /* special_function */ -+ "GPREL16", /* name */ -+ false, /* partial_inplace */ -+ 0xffff, /* src_mask */ -+ 0xffff, /* dst_mask */ -+ false), /* pcrel_offset */ -+ -+ /* Skip 20 - 23; deprecated ECOFF relocs. */ -+ SKIP_HOWTO (20), SKIP_HOWTO (21), SKIP_HOWTO (22), SKIP_HOWTO (23), -+ -+ /* Misc ELF relocations. */ -+ -+ /* A dynamic relocation to copy the target into our .dynbss section. */ -+ /* Not generated, as all Sw_64 objects use PIC, so it is not needed. It -+ is present because every other ELF has one, but should not be used -+ because .dynbss is an ugly thing. */ -+ HOWTO (R_SW_64_COPY, 0, 0, 0, false, 0, complain_overflow_dont, -+ bfd_elf_generic_reloc, "COPY", false, 0, 0, true), -+ -+ /* A dynamic relocation for a .got entry. */ -+ HOWTO (R_SW_64_GLOB_DAT, 0, 0, 0, false, 0, complain_overflow_dont, -+ bfd_elf_generic_reloc, "GLOB_DAT", false, 0, 0, true), -+ -+ /* A dynamic relocation for a .plt entry. */ -+ HOWTO (R_SW_64_JMP_SLOT, 0, 0, 0, false, 0, complain_overflow_dont, -+ bfd_elf_generic_reloc, "JMP_SLOT", false, 0, 0, true), -+ -+ /* A dynamic relocation to add the base of the DSO to a 64-bit field. */ -+ HOWTO (R_SW_64_RELATIVE, 0, 0, 0, false, 0, complain_overflow_dont, -+ bfd_elf_generic_reloc, "RELATIVE", false, 0, 0, true), -+ -+ /* A 21 bit branch that adjusts for gp loads. */ -+ HOWTO (R_SW_64_BRSGP, /* type */ -+ 2, /* rightshift */ -+ 4, /* size (0 = byte, 1 = short, 2 = long) */ -+ 21, /* bitsize */ -+ true, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_signed, /* complain_on_overflow */ -+ bfd_elf_generic_reloc, /* special_function */ -+ "BRSGP", /* name */ -+ false, /* partial_inplace */ -+ 0x1fffff, /* src_mask */ -+ 0x1fffff, /* dst_mask */ -+ true), /* pcrel_offset */ -+ -+ /* Creates a tls_index for the symbol in the got. */ -+ HOWTO (R_SW_64_TLSGD, /* type */ -+ 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ 16, /* bitsize */ -+ false, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_signed, /* complain_on_overflow */ -+ bfd_elf_generic_reloc, /* special_function */ -+ "TLSGD", /* name */ -+ false, /* partial_inplace */ -+ 0xffff, /* src_mask */ -+ 0xffff, /* dst_mask */ -+ false), /* pcrel_offset */ -+ -+ /* Creates a tls_index for the (current) module in the got. */ -+ HOWTO (R_SW_64_TLSLDM, /* type */ -+ 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ 16, /* bitsize */ -+ false, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_signed, /* complain_on_overflow */ -+ bfd_elf_generic_reloc, /* special_function */ -+ "TLSLDM", /* name */ -+ false, /* partial_inplace */ -+ 0xffff, /* src_mask */ -+ 0xffff, /* dst_mask */ -+ false), /* pcrel_offset */ -+ -+ /* A dynamic relocation for a DTP module entry. */ -+ HOWTO (R_SW_64_DTPMOD64, /* type */ -+ 0, /* rightshift */ -+ 8, /* size (0 = byte, 1 = short, 2 = long) */ -+ 64, /* bitsize */ -+ false, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_bitfield, /* complain_on_overflow */ -+ bfd_elf_generic_reloc, /* special_function */ -+ "DTPMOD64", /* name */ -+ false, /* partial_inplace */ -+ MINUS_ONE, /* src_mask */ -+ MINUS_ONE, /* dst_mask */ -+ false), /* pcrel_offset */ -+ -+ /* Creates a 64-bit offset in the got for the displacement -+ from DTP to the target. */ -+ HOWTO (R_SW_64_GOTDTPREL, /* type */ -+ 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ 16, /* bitsize */ -+ false, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_signed, /* complain_on_overflow */ -+ bfd_elf_generic_reloc, /* special_function */ -+ "GOTDTPREL", /* name */ -+ false, /* partial_inplace */ -+ 0xffff, /* src_mask */ -+ 0xffff, /* dst_mask */ -+ false), /* pcrel_offset */ -+ -+ /* A dynamic relocation for a displacement from DTP to the target. */ -+ HOWTO (R_SW_64_DTPREL64, /* type */ -+ 0, /* rightshift */ -+ 8, /* size (0 = byte, 1 = short, 2 = long) */ -+ 64, /* bitsize */ -+ false, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_bitfield, /* complain_on_overflow */ -+ bfd_elf_generic_reloc, /* special_function */ -+ "DTPREL64", /* name */ -+ false, /* partial_inplace */ -+ MINUS_ONE, /* src_mask */ -+ MINUS_ONE, /* dst_mask */ -+ false), /* pcrel_offset */ -+ -+ /* The high 16 bits of the displacement from DTP to the target. */ -+ HOWTO (R_SW_64_DTPRELHI, /* type */ -+ 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ 16, /* bitsize */ -+ false, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_signed, /* complain_on_overflow */ -+ bfd_elf_generic_reloc, /* special_function */ -+ "DTPRELHI", /* name */ -+ false, /* partial_inplace */ -+ 0xffff, /* src_mask */ -+ 0xffff, /* dst_mask */ -+ false), /* pcrel_offset */ -+ -+ /* The low 16 bits of the displacement from DTP to the target. */ -+ HOWTO (R_SW_64_DTPRELLO, /* type */ -+ 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ 16, /* bitsize */ -+ false, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont, /* complain_on_overflow */ -+ bfd_elf_generic_reloc, /* special_function */ -+ "DTPRELLO", /* name */ -+ false, /* partial_inplace */ -+ 0xffff, /* src_mask */ -+ 0xffff, /* dst_mask */ -+ false), /* pcrel_offset */ -+ -+ /* A 16-bit displacement from DTP to the target. */ -+ HOWTO (R_SW_64_DTPREL16, /* type */ -+ 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ 16, /* bitsize */ -+ false, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_signed, /* complain_on_overflow */ -+ bfd_elf_generic_reloc, /* special_function */ -+ "DTPREL16", /* name */ -+ false, /* partial_inplace */ -+ 0xffff, /* src_mask */ -+ 0xffff, /* dst_mask */ -+ false), /* pcrel_offset */ -+ -+ /* Creates a 64-bit offset in the got for the displacement -+ from TP to the target. */ -+ HOWTO (R_SW_64_GOTTPREL, /* type */ -+ 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ 16, /* bitsize */ -+ false, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_signed, /* complain_on_overflow */ -+ bfd_elf_generic_reloc, /* special_function */ -+ "GOTTPREL", /* name */ -+ false, /* partial_inplace */ -+ 0xffff, /* src_mask */ -+ 0xffff, /* dst_mask */ -+ false), /* pcrel_offset */ -+ -+ /* A dynamic relocation for a displacement from TP to the target. */ -+ HOWTO (R_SW_64_TPREL64, /* type */ -+ 0, /* rightshift */ -+ 8, /* size (0 = byte, 1 = short, 2 = long) */ -+ 64, /* bitsize */ -+ false, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_bitfield, /* complain_on_overflow */ -+ bfd_elf_generic_reloc, /* special_function */ -+ "TPREL64", /* name */ -+ false, /* partial_inplace */ -+ MINUS_ONE, /* src_mask */ -+ MINUS_ONE, /* dst_mask */ -+ false), /* pcrel_offset */ -+ -+ /* The high 16 bits of the displacement from TP to the target. */ -+ HOWTO (R_SW_64_TPRELHI, /* type */ -+ 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ 16, /* bitsize */ -+ false, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_signed, /* complain_on_overflow */ -+ bfd_elf_generic_reloc, /* special_function */ -+ "TPRELHI", /* name */ -+ false, /* partial_inplace */ -+ 0xffff, /* src_mask */ -+ 0xffff, /* dst_mask */ -+ false), /* pcrel_offset */ -+ -+ /* The low 16 bits of the displacement from TP to the target. */ -+ HOWTO (R_SW_64_TPRELLO, /* type */ -+ 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ 16, /* bitsize */ -+ false, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont, /* complain_on_overflow */ -+ bfd_elf_generic_reloc, /* special_function */ -+ "TPRELLO", /* name */ -+ false, /* partial_inplace */ -+ 0xffff, /* src_mask */ -+ 0xffff, /* dst_mask */ -+ false), /* pcrel_offset */ -+ -+ /* A 16-bit displacement from TP to the target. */ -+ HOWTO (R_SW_64_TPREL16, /* type */ -+ 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ 16, /* bitsize */ -+ false, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_signed, /* complain_on_overflow */ -+ bfd_elf_generic_reloc, /* special_function */ -+ "TPREL16", /* name */ -+ false, /* partial_inplace */ -+ 0xffff, /* src_mask */ -+ 0xffff, /* dst_mask */ -+ false), /* pcrel_offset */ -+ /* A 26 bit branch. */ -+ HOWTO (R_SW_64_BR26ADDR, /* type */ -+ 2, /* rightshift */ -+ 4, /* size (0 = byte, 1 = short, 2 = long) */ -+ 26, /* bitsize */ -+ true, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_signed, /* complain_on_overflow */ -+ bfd_elf_generic_reloc, /* special_function */ -+ "BR26ADDR", /* name */ -+ false, /* partial_inplace */ -+ 0x3ffffff, /* src_mask */ -+ 0x3ffffff, /* dst_mask */ -+ true), /* pcrel_offset */ -+ HOWTO (R_SW_64_LITERAL_GOT, /* type */ -+ 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ 16, /* bitsize */ -+ false, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_signed, /* complain_on_overflow */ -+ bfd_elf_generic_reloc, /* special_function */ -+ "ELF_LITERAL_GOT", /* name */ -+ false, /* partial_inplace */ -+ 0xffff, /* src_mask */ -+ 0xffff, /* dst_mask */ -+ false), /* pcrel_offset */ -+ HOWTO (R_SW_64_TLSREL_GOT, /* type */ -+ 0, /* rightshift */ -+ 1, /* size (0 = byte, 1 = short, 2 = long) */ -+ 16, /* bitsize */ -+ false, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_signed, /* complain_on_overflow */ -+ bfd_elf_generic_reloc, /* special_function */ -+ "ELF_TLSREL_GOT", /* name */ -+ false, /* partial_inplace */ -+ 0xffff, /* src_mask */ -+ 0xffff, /* dst_mask */ -+ false), /* pcrel_offset */ -+}; -+ -+/* A mapping from BFD reloc types to Sw_64 ELF reloc types. */ -+ -+struct elf_reloc_map -+{ -+ bfd_reloc_code_real_type bfd_reloc_val; -+ int elf_reloc_val; -+}; -+ -+static const struct elf_reloc_map elf64_sw_64_reloc_map[] = { -+ {BFD_RELOC_NONE, R_SW_64_NONE}, -+ {BFD_RELOC_32, R_SW_64_REFLONG}, -+ {BFD_RELOC_64, R_SW_64_REFQUAD}, -+ {BFD_RELOC_CTOR, R_SW_64_REFQUAD}, -+ {BFD_RELOC_GPREL32, R_SW_64_GPREL32}, -+ {BFD_RELOC_SW_64_ELF_LITERAL, R_SW_64_LITERAL}, -+ {BFD_RELOC_SW_64_LITUSE, R_SW_64_LITUSE}, -+ {BFD_RELOC_SW_64_GPDISP, R_SW_64_GPDISP}, -+ {BFD_RELOC_23_PCREL_S2, R_SW_64_BRADDR}, -+ {BFD_RELOC_SW_64_HINT, R_SW_64_HINT}, -+ {BFD_RELOC_16_PCREL, R_SW_64_SREL16}, -+ {BFD_RELOC_32_PCREL, R_SW_64_SREL32}, -+ {BFD_RELOC_64_PCREL, R_SW_64_SREL64}, -+ {BFD_RELOC_SW_64_GPREL_HI16, R_SW_64_GPRELHIGH}, -+ {BFD_RELOC_SW_64_GPREL_LO16, R_SW_64_GPRELLOW}, -+ {BFD_RELOC_GPREL16, R_SW_64_GPREL16}, -+ {BFD_RELOC_SW_64_BRSGP, R_SW_64_BRSGP}, -+ {BFD_RELOC_SW_64_TLSGD, R_SW_64_TLSGD}, -+ {BFD_RELOC_SW_64_TLSLDM, R_SW_64_TLSLDM}, -+ {BFD_RELOC_SW_64_DTPMOD64, R_SW_64_DTPMOD64}, -+ {BFD_RELOC_SW_64_GOTDTPREL16, R_SW_64_GOTDTPREL}, -+ {BFD_RELOC_SW_64_DTPREL64, R_SW_64_DTPREL64}, -+ {BFD_RELOC_SW_64_DTPREL_HI16, R_SW_64_DTPRELHI}, -+ {BFD_RELOC_SW_64_DTPREL_LO16, R_SW_64_DTPRELLO}, -+ {BFD_RELOC_SW_64_DTPREL16, R_SW_64_DTPREL16}, -+ {BFD_RELOC_SW_64_GOTTPREL16, R_SW_64_GOTTPREL}, -+ {BFD_RELOC_SW_64_TPREL64, R_SW_64_TPREL64}, -+ {BFD_RELOC_SW_64_TPREL_HI16, R_SW_64_TPRELHI}, -+ {BFD_RELOC_SW_64_TPREL_LO16, R_SW_64_TPRELLO}, -+ {BFD_RELOC_SW_64_TPREL16, R_SW_64_TPREL16}, -+ {BFD_RELOC_SW_64_BR26, R_SW_64_BR26ADDR}, -+ {BFD_RELOC_SW_64_ELF_LITERAL_GOT, R_SW_64_LITERAL_GOT}, -+ {BFD_RELOC_SW_64_TLSREL_GOT, R_SW_64_TLSREL_GOT}, -+}; -+ -+/* Given a BFD reloc type, return a HOWTO structure. */ -+ -+static reloc_howto_type * -+elf64_sw_64_bfd_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED, -+ bfd_reloc_code_real_type code) -+{ -+ const struct elf_reloc_map *i, *e; -+ i = e = elf64_sw_64_reloc_map; -+ e += sizeof (elf64_sw_64_reloc_map) / sizeof (struct elf_reloc_map); -+ for (; i != e; ++i) -+ { -+ if (i->bfd_reloc_val == code) -+ return &elf64_sw_64_howto_table[i->elf_reloc_val]; -+ } -+ return 0; -+} -+ -+static reloc_howto_type * -+elf64_sw_64_bfd_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED, -+ const char *r_name) -+{ -+ unsigned int i; -+ -+ for (i = 0; i < (sizeof (elf64_sw_64_howto_table) -+ / sizeof (elf64_sw_64_howto_table[0])); -+ i++) -+ if (elf64_sw_64_howto_table[i].name != NULL -+ && strcasecmp (elf64_sw_64_howto_table[i].name, r_name) == 0) -+ return &elf64_sw_64_howto_table[i]; -+ -+ return NULL; -+} -+ -+/* Given an Sw_64 ELF reloc type, fill in an arelent structure. */ -+ -+static bool -+elf64_sw_64_info_to_howto (bfd *abfd, arelent *cache_ptr, -+ Elf_Internal_Rela *dst) -+{ -+ unsigned r_type = ELF64_R_TYPE (dst->r_info); -+ -+ if (r_type >= R_SW_64_max) -+ { -+ /* xgettext:c-format */ -+ _bfd_error_handler (_ ("%pB: unsupported relocation type %#x"), abfd, -+ r_type); -+ bfd_set_error (bfd_error_bad_value); -+ return false; -+ } -+ cache_ptr->howto = &elf64_sw_64_howto_table[r_type]; -+ return true; -+} -+ -+/* These two relocations create a two-word entry in the got. */ -+#define sw_64_got_entry_size(r_type) \ -+ (r_type == R_SW_64_TLSGD || r_type == R_SW_64_TLSLDM ? 16 : 8) -+ -+/* This is PT_TLS segment p_vaddr. */ -+#define sw_64_get_dtprel_base(info) (elf_hash_table (info)->tls_sec->vma) -+ -+/* Main program TLS (whose template starts at PT_TLS p_vaddr) -+ is assigned offset round (16, PT_TLS p_align). */ -+#define sw_64_get_tprel_base(info) \ -+ (elf_hash_table (info)->tls_sec->vma \ -+ - align_power ((bfd_vma) 16, \ -+ elf_hash_table (info)->tls_sec->alignment_power)) -+ -+/* Handle an Sw_64 specific section when reading an object file. This -+ is called when bfd_section_from_shdr finds a section with an unknown -+ type. */ -+ -+static bool -+elf64_sw_64_section_from_shdr (bfd *abfd, Elf_Internal_Shdr *hdr, -+ const char *name, int shindex) -+{ -+ asection *newsect; -+ -+ /* There ought to be a place to keep ELF backend specific flags, but -+ at the moment there isn't one. We just keep track of the -+ sections by their name, instead. Fortunately, the ABI gives -+ suggested names for all the MIPS specific sections, so we will -+ probably get away with this. */ -+ switch (hdr->sh_type) -+ { -+ case SHT_SW_64_DEBUG: -+ if (strcmp (name, ".mdebug") != 0) -+ return false; -+ break; -+ default: -+ return false; -+ } -+ -+ if (!_bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex)) -+ return false; -+ newsect = hdr->bfd_section; -+ -+ if (hdr->sh_type == SHT_SW_64_DEBUG) -+ { -+ if (!bfd_set_section_flags (newsect, -+ bfd_section_flags (newsect) | SEC_DEBUGGING)) -+ return false; -+ } -+ -+ return true; -+} -+ -+/* Convert Sw_64 specific section flags to bfd internal section flags. */ -+ -+static bool -+elf64_sw_64_section_flags (const Elf_Internal_Shdr *hdr) -+{ -+ if (hdr->sh_flags & SHF_SW_64_GPREL) -+ hdr->bfd_section->flags |= SEC_SMALL_DATA; -+ -+ return true; -+} -+ -+/* Set the correct type for an Sw_64 ELF section. We do this by the -+ section name, which is a hack, but ought to work. */ -+ -+static bool -+elf64_sw_64_fake_sections (bfd *abfd, Elf_Internal_Shdr *hdr, asection *sec) -+{ -+ register const char *name; -+ -+ name = bfd_section_name (sec); -+ -+ if (strcmp (name, ".mdebug") == 0) -+ { -+ hdr->sh_type = SHT_SW_64_DEBUG; -+ /* In a shared object on Irix 5.3, the .mdebug section has an -+ entsize of 0. FIXME: Does this matter? */ -+ if ((abfd->flags & DYNAMIC) != 0) -+ hdr->sh_entsize = 0; -+ else -+ hdr->sh_entsize = 1; -+ } -+ else if ((sec->flags & SEC_SMALL_DATA) || strcmp (name, ".sdata") == 0 -+ || strcmp (name, ".sbss") == 0 || strcmp (name, ".lit4") == 0 -+ || strcmp (name, ".lit8") == 0) -+ hdr->sh_flags |= SHF_SW_64_GPREL; -+ -+ return true; -+} -+ -+/* Hook called by the linker routine which adds symbols from an object -+ file. We use it to put .comm items in .sbss, and not .bss. */ -+ -+static bool -+elf64_sw_64_add_symbol_hook (bfd *abfd, struct bfd_link_info *info, -+ Elf_Internal_Sym *sym, -+ const char **namep ATTRIBUTE_UNUSED, -+ flagword *flagsp ATTRIBUTE_UNUSED, asection **secp, -+ bfd_vma *valp) -+{ -+ if (sym->st_shndx == SHN_COMMON && !bfd_link_relocatable (info) -+ && sym->st_size <= elf_gp_size (abfd)) -+ { -+ /* Common symbols less than or equal to -G nn bytes are -+ automatically put into .sbss. */ -+ -+ asection *scomm = bfd_get_section_by_name (abfd, ".scommon"); -+ -+ if (scomm == NULL) -+ { -+ scomm = bfd_make_section_with_flags (abfd, ".scommon", -+ (SEC_ALLOC | SEC_IS_COMMON -+ | SEC_SMALL_DATA -+ | SEC_LINKER_CREATED)); -+ if (scomm == NULL) -+ return false; -+ } -+ -+ *secp = scomm; -+ *valp = sym->st_size; -+ } -+ -+ return true; -+} -+ -+/* Create the .got section. */ -+ -+static bool -+elf64_sw_64_create_got_section (bfd *abfd, -+ struct bfd_link_info *info ATTRIBUTE_UNUSED) -+{ -+ flagword flags; -+ asection *s; -+ -+ if (!is_sw_64_elf (abfd)) -+ return false; -+ -+ flags = (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY -+ | SEC_LINKER_CREATED); -+ s = bfd_make_section_anyway_with_flags (abfd, ".got", flags); -+ if (s == NULL || !bfd_set_section_alignment (s, 3)) -+ return false; -+ -+ sw_64_elf_tdata (abfd)->got = s; -+ -+ /* Make sure the object's gotobj is set to itself so that we default -+ to every object with its own .got. We'll merge .gots later once -+ we've collected each object's info. */ -+ sw_64_elf_tdata (abfd)->gotobj = abfd; -+ -+ return true; -+} -+ -+/* Create all the dynamic sections. */ -+ -+static bool -+elf64_sw_64_create_dynamic_sections (bfd *abfd, struct bfd_link_info *info) -+{ -+ asection *s; -+ flagword flags; -+ struct elf_link_hash_entry *h; -+ -+ if (!is_sw_64_elf (abfd)) -+ return false; -+ -+ /* We need to create .plt, .rela.plt, .got, and .rela.got sections. */ -+ -+ flags -+ = (SEC_ALLOC | SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS | SEC_IN_MEMORY -+ | SEC_LINKER_CREATED | (elf64_sw_64_use_secureplt ? SEC_READONLY : 0)); -+ s = bfd_make_section_anyway_with_flags (abfd, ".plt", flags); -+ elf_hash_table (info)->splt = s; -+ if (s == NULL || !bfd_set_section_alignment (s, 4)) -+ return false; -+ -+ /* Define the symbol _PROCEDURE_LINKAGE_TABLE_ at the start of the -+ .plt section. */ -+ h = _bfd_elf_define_linkage_sym (abfd, info, s, "_PROCEDURE_LINKAGE_TABLE_"); -+ elf_hash_table (info)->hplt = h; -+ if (h == NULL) -+ return false; -+ -+ flags = (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY -+ | SEC_LINKER_CREATED | SEC_READONLY); -+ s = bfd_make_section_anyway_with_flags (abfd, ".rela.plt", flags); -+ elf_hash_table (info)->srelplt = s; -+ if (s == NULL || !bfd_set_section_alignment (s, 3)) -+ return false; -+ -+ if (elf64_sw_64_use_secureplt) -+ { -+ flags = SEC_ALLOC | SEC_LINKER_CREATED; -+ s = bfd_make_section_anyway_with_flags (abfd, ".got.plt", flags); -+ elf_hash_table (info)->sgotplt = s; -+ if (s == NULL || !bfd_set_section_alignment (s, 3)) -+ return false; -+ } -+ -+ /* We may or may not have created a .got section for this object, but -+ we definitely havn't done the rest of the work. */ -+ -+ if (sw_64_elf_tdata (abfd)->gotobj == NULL) -+ { -+ if (!elf64_sw_64_create_got_section (abfd, info)) -+ return false; -+ } -+ -+ flags = (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY -+ | SEC_LINKER_CREATED | SEC_READONLY); -+ s = bfd_make_section_anyway_with_flags (abfd, ".rela.got", flags); -+ elf_hash_table (info)->srelgot = s; -+ if (s == NULL || !bfd_set_section_alignment (s, 3)) -+ return false; -+ -+ /* Define the symbol _GLOBAL_OFFSET_TABLE_ at the start of the -+ dynobj's .got section. We don't do this in the linker script -+ because we don't want to define the symbol if we are not creating -+ a global offset table. */ -+ h = _bfd_elf_define_linkage_sym (abfd, info, sw_64_elf_tdata (abfd)->got, -+ "_GLOBAL_OFFSET_TABLE_"); -+ elf_hash_table (info)->hgot = h; -+ if (h == NULL) -+ return false; -+ -+ return true; -+} -+ -+/* Read ECOFF debugging information from a .mdebug section into a -+ ecoff_debug_info structure. */ -+ -+static bool -+elf64_sw_64_read_ecoff_info (bfd *abfd, asection *section, -+ struct ecoff_debug_info *debug) -+{ -+ HDRR *symhdr; -+ const struct ecoff_debug_swap *swap; -+ char *ext_hdr = NULL; -+ -+ swap = get_elf_backend_data (abfd)->elf_backend_ecoff_debug_swap; -+ memset (debug, 0, sizeof (*debug)); -+ -+ ext_hdr = (char *) bfd_malloc (swap->external_hdr_size); -+ if (ext_hdr == NULL && swap->external_hdr_size != 0) -+ goto error_return; -+ -+ if (!bfd_get_section_contents (abfd, section, ext_hdr, (file_ptr) 0, -+ swap->external_hdr_size)) -+ goto error_return; -+ -+ symhdr = &debug->symbolic_header; -+ (*swap->swap_hdr_in) (abfd, ext_hdr, symhdr); -+ -+ /* The symbolic header contains absolute file offsets and sizes to -+ read. */ -+#define READ(ptr, offset, count, size, type) \ -+ if (symhdr->count == 0) \ -+ debug->ptr = NULL; \ -+ else \ -+ { \ -+ bfd_size_type amt = (bfd_size_type) size * symhdr->count; \ -+ debug->ptr = (type) bfd_malloc (amt); \ -+ if (debug->ptr == NULL) \ -+ goto error_return; \ -+ if (bfd_seek (abfd, (file_ptr) symhdr->offset, SEEK_SET) != 0 \ -+ || bfd_bread (debug->ptr, amt, abfd) != amt) \ -+ goto error_return; \ -+ } -+ -+ READ (line, cbLineOffset, cbLine, sizeof (unsigned char), unsigned char *); -+ READ (external_dnr, cbDnOffset, idnMax, swap->external_dnr_size, void *); -+ READ (external_pdr, cbPdOffset, ipdMax, swap->external_pdr_size, void *); -+ READ (external_sym, cbSymOffset, isymMax, swap->external_sym_size, void *); -+ READ (external_opt, cbOptOffset, ioptMax, swap->external_opt_size, void *); -+ READ (external_aux, cbAuxOffset, iauxMax, sizeof (union aux_ext), -+ union aux_ext *); -+ READ (ss, cbSsOffset, issMax, sizeof (char), char *); -+ READ (ssext, cbSsExtOffset, issExtMax, sizeof (char), char *); -+ READ (external_fdr, cbFdOffset, ifdMax, swap->external_fdr_size, void *); -+ READ (external_rfd, cbRfdOffset, crfd, swap->external_rfd_size, void *); -+ READ (external_ext, cbExtOffset, iextMax, swap->external_ext_size, void *); -+#undef READ -+ -+ debug->fdr = NULL; -+ -+ return true; -+ -+error_return: -+ free (ext_hdr); -+ _bfd_ecoff_free_ecoff_debug_info (debug); -+ return false; -+} -+ -+/* Sw_64 ELF local labels start with '$'. */ -+ -+static bool -+elf64_sw_64_is_local_label_name (bfd *abfd ATTRIBUTE_UNUSED, const char *name) -+{ -+ return name[0] == '$'; -+} -+ -+static bool -+elf64_sw_64_find_nearest_line (bfd *abfd, asymbol **symbols, asection *section, -+ bfd_vma offset, const char **filename_ptr, -+ const char **functionname_ptr, -+ unsigned int *line_ptr, -+ unsigned int *discriminator_ptr) -+{ -+ asection *msec; -+ -+ if (_bfd_dwarf2_find_nearest_line (abfd, symbols, NULL, section, offset, -+ filename_ptr, functionname_ptr, line_ptr, -+ discriminator_ptr, dwarf_debug_sections, -+ &elf_tdata (abfd)->dwarf2_find_line_info) -+ == 1) -+ return true; -+ -+ msec = bfd_get_section_by_name (abfd, ".mdebug"); -+ if (msec != NULL) -+ { -+ flagword origflags; -+ struct sw_64_elf_find_line *fi; -+ const struct ecoff_debug_swap *const swap -+ = get_elf_backend_data (abfd)->elf_backend_ecoff_debug_swap; -+ -+ /* If we are called during a link, sw_64_elf_final_link may have -+ cleared the SEC_HAS_CONTENTS field. We force it back on here -+ if appropriate (which it normally will be). */ -+ origflags = msec->flags; -+ if (elf_section_data (msec)->this_hdr.sh_type != SHT_NOBITS) -+ msec->flags |= SEC_HAS_CONTENTS; -+ -+ fi = sw_64_elf_tdata (abfd)->find_line_info; -+ if (fi == NULL) -+ { -+ bfd_size_type external_fdr_size; -+ char *fraw_src; -+ char *fraw_end; -+ struct fdr *fdr_ptr; -+ bfd_size_type amt = sizeof (struct sw_64_elf_find_line); -+ -+ fi = (struct sw_64_elf_find_line *) bfd_zalloc (abfd, amt); -+ if (fi == NULL) -+ { -+ msec->flags = origflags; -+ return false; -+ } -+ -+ if (!elf64_sw_64_read_ecoff_info (abfd, msec, &fi->d)) -+ { -+ msec->flags = origflags; -+ return false; -+ } -+ -+ /* Swap in the FDR information. */ -+ amt = fi->d.symbolic_header.ifdMax * sizeof (struct fdr); -+ fi->d.fdr = (struct fdr *) bfd_alloc (abfd, amt); -+ if (fi->d.fdr == NULL) -+ { -+ msec->flags = origflags; -+ return false; -+ } -+ external_fdr_size = swap->external_fdr_size; -+ fdr_ptr = fi->d.fdr; -+ fraw_src = (char *) fi->d.external_fdr; -+ fraw_end -+ = (fraw_src + fi->d.symbolic_header.ifdMax * external_fdr_size); -+ for (; fraw_src < fraw_end; fraw_src += external_fdr_size, fdr_ptr++) -+ (*swap->swap_fdr_in) (abfd, fraw_src, fdr_ptr); -+ -+ sw_64_elf_tdata (abfd)->find_line_info = fi; -+ -+ /* Note that we don't bother to ever free this information. -+ find_nearest_line is either called all the time, as in -+ objdump -l, so the information should be saved, or it is -+ rarely called, as in ld error messages, so the memory -+ wasted is unimportant. Still, it would probably be a -+ good idea for free_cached_info to throw it away. */ -+ } -+ -+ if (_bfd_ecoff_locate_line (abfd, section, offset, &fi->d, swap, &fi->i, -+ filename_ptr, functionname_ptr, line_ptr)) -+ { -+ msec->flags = origflags; -+ return true; -+ } -+ -+ msec->flags = origflags; -+ } -+ -+ /* Fall back on the generic ELF find_nearest_line routine. */ -+ -+ return _bfd_elf_find_nearest_line (abfd, symbols, section, offset, -+ filename_ptr, functionname_ptr, line_ptr, -+ discriminator_ptr); -+} -+ -+/* Structure used to pass information to sw_64_elf_output_extsym. */ -+ -+struct extsym_info -+{ -+ bfd *abfd; -+ struct bfd_link_info *info; -+ struct ecoff_debug_info *debug; -+ const struct ecoff_debug_swap *swap; -+ bool failed; -+}; -+ -+static bool -+elf64_sw_64_output_extsym (struct sw_64_elf_link_hash_entry *h, void *data) -+{ -+ struct extsym_info *einfo = (struct extsym_info *) data; -+ bool strip; -+ asection *sec, *output_section; -+ -+ if (h->root.indx == -2) -+ strip = false; -+ else if ((h->root.def_dynamic || h->root.ref_dynamic -+ || h->root.root.type == bfd_link_hash_new) -+ && !h->root.def_regular && !h->root.ref_regular) -+ strip = true; -+ else if (einfo->info->strip == strip_all -+ || (einfo->info->strip == strip_some -+ && bfd_hash_lookup (einfo->info->keep_hash, -+ h->root.root.root.string, false, false) -+ == NULL)) -+ strip = true; -+ else -+ strip = false; -+ -+ if (strip) -+ return true; -+ -+ if (h->esym.ifd == -2) -+ { -+ h->esym.jmptbl = 0; -+ h->esym.cobol_main = 0; -+ h->esym.weakext = 0; -+ h->esym.reserved = 0; -+ h->esym.ifd = ifdNil; -+ h->esym.asym.value = 0; -+ h->esym.asym.st = stGlobal; -+ -+ if (h->root.root.type != bfd_link_hash_defined -+ && h->root.root.type != bfd_link_hash_defweak) -+ h->esym.asym.sc = scAbs; -+ else -+ { -+ const char *name; -+ -+ sec = h->root.root.u.def.section; -+ output_section = sec->output_section; -+ -+ /* When making a shared library and symbol h is the one from -+ the another shared library, OUTPUT_SECTION may be null. */ -+ if (output_section == NULL) -+ h->esym.asym.sc = scUndefined; -+ else -+ { -+ name = bfd_section_name (output_section); -+ -+ if (strcmp (name, ".text") == 0) -+ h->esym.asym.sc = scText; -+ else if (strcmp (name, ".data") == 0) -+ h->esym.asym.sc = scData; -+ else if (strcmp (name, ".sdata") == 0) -+ h->esym.asym.sc = scSData; -+ else if (strcmp (name, ".rodata") == 0 -+ || strcmp (name, ".rdata") == 0) -+ h->esym.asym.sc = scRData; -+ else if (strcmp (name, ".bss") == 0) -+ h->esym.asym.sc = scBss; -+ else if (strcmp (name, ".sbss") == 0) -+ h->esym.asym.sc = scSBss; -+ else if (strcmp (name, ".init") == 0) -+ h->esym.asym.sc = scInit; -+ else if (strcmp (name, ".fini") == 0) -+ h->esym.asym.sc = scFini; -+ else -+ h->esym.asym.sc = scAbs; -+ } -+ } -+ -+ h->esym.asym.reserved = 0; -+ h->esym.asym.index = indexNil; -+ } -+ -+ if (h->root.root.type == bfd_link_hash_common) -+ h->esym.asym.value = h->root.root.u.c.size; -+ else if (h->root.root.type == bfd_link_hash_defined -+ || h->root.root.type == bfd_link_hash_defweak) -+ { -+ if (h->esym.asym.sc == scCommon) -+ h->esym.asym.sc = scBss; -+ else if (h->esym.asym.sc == scSCommon) -+ h->esym.asym.sc = scSBss; -+ -+ sec = h->root.root.u.def.section; -+ output_section = sec->output_section; -+ if (output_section != NULL) -+ h->esym.asym.value = (h->root.root.u.def.value + sec->output_offset -+ + output_section->vma); -+ else -+ h->esym.asym.value = 0; -+ } -+ -+ if (!bfd_ecoff_debug_one_external (einfo->abfd, einfo->debug, einfo->swap, -+ h->root.root.root.string, &h->esym)) -+ { -+ einfo->failed = true; -+ return false; -+ } -+ -+ return true; -+} -+ -+/* Search for and possibly create a got entry. */ -+ -+static struct sw_64_elf_got_entry * -+get_got_entry (bfd *abfd, struct sw_64_elf_link_hash_entry *h, -+ unsigned long r_type, unsigned long r_symndx, bfd_vma r_addend) -+{ -+ struct sw_64_elf_got_entry *gotent; -+ struct sw_64_elf_got_entry **slot; -+ -+ if (h) -+ slot = &h->got_entries; -+ else -+ { -+ /* This is a local .got entry -- record for merge. */ -+ -+ struct sw_64_elf_got_entry **local_got_entries; -+ -+ local_got_entries = sw_64_elf_tdata (abfd)->local_got_entries; -+ if (!local_got_entries) -+ { -+ bfd_size_type size; -+ Elf_Internal_Shdr *symtab_hdr; -+ -+ symtab_hdr = &elf_tdata (abfd)->symtab_hdr; -+ size = symtab_hdr->sh_info; -+ size *= sizeof (struct sw_64_elf_got_entry *); -+ -+ local_got_entries -+ = (struct sw_64_elf_got_entry **) bfd_zalloc (abfd, size); -+ if (!local_got_entries) -+ return NULL; -+ -+ sw_64_elf_tdata (abfd)->local_got_entries = local_got_entries; -+ } -+ -+ slot = &local_got_entries[r_symndx]; -+ } -+ -+ for (gotent = *slot; gotent; gotent = gotent->next) -+ if (gotent->gotobj == abfd && gotent->reloc_type == r_type -+ && gotent->addend == r_addend) -+ break; -+ -+ if (!gotent) -+ { -+ int entry_size; -+ size_t amt; -+ -+ amt = sizeof (struct sw_64_elf_got_entry); -+ gotent = (struct sw_64_elf_got_entry *) bfd_alloc (abfd, amt); -+ if (!gotent) -+ return NULL; -+ -+ gotent->gotobj = abfd; -+ gotent->addend = r_addend; -+ gotent->got_offset = -1; -+ gotent->plt_offset = -1; -+ gotent->use_count = 1; -+ gotent->reloc_type = r_type; -+ gotent->reloc_done = 0; -+ gotent->reloc_xlated = 0; -+ -+ gotent->next = *slot; -+ *slot = gotent; -+ -+ entry_size = sw_64_got_entry_size (r_type); -+ sw_64_elf_tdata (abfd)->total_got_size += entry_size; -+ if (!h) -+ sw_64_elf_tdata (abfd)->local_got_size += entry_size; -+ } -+ else -+ gotent->use_count += 1; -+ -+ return gotent; -+} -+ -+static bool -+elf64_sw_64_want_plt (struct sw_64_elf_link_hash_entry *ah) -+{ -+ return ((ah->root.type == STT_FUNC -+ || ah->root.root.type == bfd_link_hash_undefweak -+ || ah->root.root.type == bfd_link_hash_undefined) -+ && (ah->flags & SW_64_ELF_LINK_HASH_LU_PLT) != 0 -+ && (ah->flags & ~SW_64_ELF_LINK_HASH_LU_PLT) == 0); -+} -+ -+/* Whether to sort relocs output by ld -r or ld --emit-relocs, by r_offset. -+ Don't do so for code sections. We want to keep ordering of LITERAL/LITUSE -+ as is. On the other hand, elf-eh-frame.c processing requires .eh_frame -+ relocs to be sorted. */ -+ -+static bool -+elf64_sw_64_sort_relocs_p (asection *sec) -+{ -+ return (sec->flags & SEC_CODE) == 0; -+} -+ -+/* Handle dynamic relocations when doing an Sw_64 ELF link. */ -+ -+static bool -+elf64_sw_64_check_relocs (bfd *abfd, struct bfd_link_info *info, asection *sec, -+ const Elf_Internal_Rela *relocs) -+{ -+ bfd *dynobj; -+ asection *sreloc; -+ Elf_Internal_Shdr *symtab_hdr; -+ struct sw_64_elf_link_hash_entry **sym_hashes; -+ const Elf_Internal_Rela *rel, *relend; -+ -+ if (bfd_link_relocatable (info)) -+ return true; -+ -+ /* Don't do anything special with non-loaded, non-alloced sections. -+ In particular, any relocs in such sections should not affect GOT -+ and PLT reference counting (ie. we don't allow them to create GOT -+ or PLT entries), there's no possibility or desire to optimize TLS -+ relocs, and there's not much point in propagating relocs to shared -+ libs that the dynamic linker won't relocate. */ -+ if ((sec->flags & SEC_ALLOC) == 0) -+ return true; -+ -+ BFD_ASSERT (is_sw_64_elf (abfd)); -+ -+ dynobj = elf_hash_table (info)->dynobj; -+ if (dynobj == NULL) -+ elf_hash_table (info)->dynobj = dynobj = abfd; -+ -+ sreloc = NULL; -+ symtab_hdr = &elf_symtab_hdr (abfd); -+ sym_hashes = sw_64_elf_sym_hashes (abfd); -+ -+ relend = relocs + sec->reloc_count; -+ for (rel = relocs; rel < relend; ++rel) -+ { -+ enum -+ { -+ NEED_GOT = 1, -+ NEED_GOT_ENTRY = 2, -+ NEED_DYNREL = 4 -+ }; -+ -+ unsigned long r_symndx, r_type; -+ struct sw_64_elf_link_hash_entry *h; -+ unsigned int gotent_flags; -+ bool maybe_dynamic; -+ unsigned int need; -+ bfd_vma addend; -+ -+ r_symndx = ELF64_R_SYM (rel->r_info); -+ if (r_symndx < symtab_hdr->sh_info) -+ h = NULL; -+ else -+ { -+ h = sym_hashes[r_symndx - symtab_hdr->sh_info]; -+ -+ while (h->root.root.type == bfd_link_hash_indirect -+ || h->root.root.type == bfd_link_hash_warning) -+ h = (struct sw_64_elf_link_hash_entry *) h->root.root.u.i.link; -+ -+ /* PR15323, ref flags aren't set for references in the same -+ object. */ -+ h->root.ref_regular = 1; -+ } -+ -+ /* We can only get preliminary data on whether a symbol is -+ locally or externally defined, as not all of the input files -+ have yet been processed. Do something with what we know, as -+ this may help reduce memory usage and processing time later. */ -+ maybe_dynamic = false; -+ if (h -+ && ((bfd_link_pic (info) -+ && (!info->symbolic -+ || info->unresolved_syms_in_shared_libs == RM_IGNORE)) -+ || !h->root.def_regular -+ || h->root.root.type == bfd_link_hash_defweak)) -+ maybe_dynamic = true; -+ -+ need = 0; -+ gotent_flags = 0; -+ r_type = ELF64_R_TYPE (rel->r_info); -+ addend = rel->r_addend; -+ -+ switch (r_type) -+ { -+ case R_SW_64_LITERAL: -+ need = NEED_GOT | NEED_GOT_ENTRY; -+ -+ /* Remember how this literal is used from its LITUSEs. -+ This will be important when it comes to decide if we can -+ create a .plt entry for a function symbol. */ -+ while (++rel < relend && ELF64_R_TYPE (rel->r_info) == R_SW_64_LITUSE) -+ if (rel->r_addend >= 1 && rel->r_addend <= 6) -+ gotent_flags |= 1 << rel->r_addend; -+ --rel; -+ -+ /* No LITUSEs -- presumably the address is used somehow. */ -+ if (gotent_flags == 0) -+ gotent_flags = SW_64_ELF_LINK_HASH_LU_ADDR; -+ break; -+ -+ case R_SW_64_GPDISP: -+ case R_SW_64_GPREL16: -+ case R_SW_64_GPREL32: -+ case R_SW_64_GPRELHIGH: -+ case R_SW_64_GPRELLOW: -+ case R_SW_64_BRSGP: -+ need = NEED_GOT; -+ break; -+ -+ case R_SW_64_REFLONG: -+ case R_SW_64_REFQUAD: -+ if (bfd_link_pic (info) || maybe_dynamic) -+ need = NEED_DYNREL; -+ break; -+ -+ case R_SW_64_TLSLDM: -+ /* The symbol for a TLSLDM reloc is ignored. Collapse the -+ reloc to the STN_UNDEF (0) symbol so that they all match. */ -+ r_symndx = STN_UNDEF; -+ h = 0; -+ maybe_dynamic = false; -+ /* FALLTHRU */ -+ -+ case R_SW_64_TLSGD: -+ case R_SW_64_GOTDTPREL: -+ need = NEED_GOT | NEED_GOT_ENTRY; -+ break; -+ -+ case R_SW_64_GOTTPREL: -+ need = NEED_GOT | NEED_GOT_ENTRY; -+ gotent_flags = SW_64_ELF_LINK_HASH_TLS_IE; -+ if (bfd_link_pic (info)) -+ info->flags |= DF_STATIC_TLS; -+ break; -+ -+ case R_SW_64_TPREL64: -+ if (bfd_link_dll (info)) -+ { -+ info->flags |= DF_STATIC_TLS; -+ need = NEED_DYNREL; -+ } -+ else if (maybe_dynamic) -+ need = NEED_DYNREL; -+ break; -+ } -+ -+ if (need & NEED_GOT) -+ { -+ if (sw_64_elf_tdata (abfd)->gotobj == NULL) -+ { -+ if (!elf64_sw_64_create_got_section (abfd, info)) -+ return false; -+ } -+ } -+ -+ if (need & NEED_GOT_ENTRY) -+ { -+ struct sw_64_elf_got_entry *gotent; -+ -+ gotent = get_got_entry (abfd, h, r_type, r_symndx, addend); -+ if (!gotent) -+ return false; -+ -+ if (gotent_flags) -+ { -+ gotent->flags |= gotent_flags; -+ if (h) -+ { -+ gotent_flags |= h->flags; -+ h->flags = gotent_flags; -+ -+ /* Make a guess as to whether a .plt entry is needed. */ -+ /* ??? It appears that we won't make it into -+ adjust_dynamic_symbol for symbols that remain -+ totally undefined. Copying this check here means -+ we can create a plt entry for them too. */ -+ h->root.needs_plt -+ = (maybe_dynamic && elf64_sw_64_want_plt (h)); -+ } -+ } -+ } -+ -+ if (need & NEED_DYNREL) -+ { -+ /* We need to create the section here now whether we eventually -+ use it or not so that it gets mapped to an output section by -+ the linker. If not used, we'll kill it in size_dynamic_sections. -+ */ -+ if (sreloc == NULL) -+ { -+ sreloc -+ = _bfd_elf_make_dynamic_reloc_section (sec, dynobj, 3, abfd, -+ /*rela?*/ true); -+ -+ if (sreloc == NULL) -+ return false; -+ } -+ -+ if (h) -+ { -+ /* Since we havn't seen all of the input symbols yet, we -+ don't know whether we'll actually need a dynamic relocation -+ entry for this reloc. So make a record of it. Once we -+ find out if this thing needs dynamic relocation we'll -+ expand the relocation sections by the appropriate amount. */ -+ -+ struct sw_64_elf_reloc_entry *rent; -+ -+ for (rent = h->reloc_entries; rent; rent = rent->next) -+ if (rent->rtype == r_type && rent->srel == sreloc) -+ break; -+ -+ if (!rent) -+ { -+ size_t amt = sizeof (struct sw_64_elf_reloc_entry); -+ rent = (struct sw_64_elf_reloc_entry *) bfd_alloc (abfd, amt); -+ if (!rent) -+ return false; -+ -+ rent->srel = sreloc; -+ rent->sec = sec; -+ rent->rtype = r_type; -+ rent->count = 1; -+ -+ rent->next = h->reloc_entries; -+ h->reloc_entries = rent; -+ } -+ else -+ rent->count++; -+ } -+ else if (bfd_link_pic (info)) -+ { -+ /* If this is a shared library, and the section is to be -+ loaded into memory, we need a RELATIVE reloc. */ -+ sreloc->size += sizeof (Elf64_External_Rela); -+ if (sec->flags & SEC_READONLY) -+ { -+ info->flags |= DF_TEXTREL; -+ info->callbacks->minfo ( -+ _ ("%pB: dynamic relocation against `T' in " -+ "read-only section `%pA'\n"), -+ sec->owner, sec); -+ } -+ } -+ } -+ } -+ -+ return true; -+} -+ -+/* Return the section that should be marked against GC for a given -+ relocation. */ -+ -+static asection * -+elf64_sw_64_gc_mark_hook (asection *sec, struct bfd_link_info *info, -+ Elf_Internal_Rela *rel, struct elf_link_hash_entry *h, -+ Elf_Internal_Sym *sym) -+{ -+ /* These relocations don't really reference a symbol. Instead we store -+ extra data in their addend slot. Ignore the symbol. */ -+ switch (ELF64_R_TYPE (rel->r_info)) -+ { -+ case R_SW_64_LITUSE: -+ case R_SW_64_GPDISP: -+ case R_SW_64_HINT: -+ return NULL; -+ } -+ -+ return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym); -+} -+ -+/* Adjust a symbol defined by a dynamic object and referenced by a -+ regular object. The current definition is in some section of the -+ dynamic object, but we're not including those sections. We have to -+ change the definition to something the rest of the link can -+ understand. */ -+ -+static bool -+elf64_sw_64_adjust_dynamic_symbol (struct bfd_link_info *info, -+ struct elf_link_hash_entry *h) -+{ -+ bfd *dynobj; -+ asection *s; -+ struct sw_64_elf_link_hash_entry *ah; -+ -+ dynobj = elf_hash_table (info)->dynobj; -+ ah = (struct sw_64_elf_link_hash_entry *) h; -+ -+ /* Now that we've seen all of the input symbols, finalize our decision -+ about whether this symbol should get a .plt entry. Irritatingly, it -+ is common for folk to leave undefined symbols in shared libraries, -+ and they still expect lazy binding; accept undefined symbols in lieu -+ of STT_FUNC. */ -+ if (sw_64_elf_dynamic_symbol_p (h, info) && elf64_sw_64_want_plt (ah)) -+ { -+ h->needs_plt = true; -+ -+ s = elf_hash_table (info)->splt; -+ if (!s && !elf64_sw_64_create_dynamic_sections (dynobj, info)) -+ return false; -+ -+ /* We need one plt entry per got subsection. Delay allocation of -+ the actual plt entries until size_plt_section, called from -+ size_dynamic_sections or during relaxation. */ -+ -+ return true; -+ } -+ else -+ h->needs_plt = false; -+ -+ /* If this is a weak symbol, and there is a real definition, the -+ processor independent code will have arranged for us to see the -+ real definition first, and we can just use the same value. */ -+ if (h->is_weakalias) -+ { -+ struct elf_link_hash_entry *def = weakdef (h); -+ BFD_ASSERT (def->root.type == bfd_link_hash_defined); -+ h->root.u.def.section = def->root.u.def.section; -+ h->root.u.def.value = def->root.u.def.value; -+ return true; -+ } -+ -+ /* This is a reference to a symbol defined by a dynamic object which -+ is not a function. The Sw_64, since it uses .got entries for all -+ symbols even in regular objects, does not need the hackery of a -+ .dynbss section and COPY dynamic relocations. */ -+ -+ return true; -+} -+ -+/* Record STO_SW_64_NOPV and STO_SW_64_STD_GPLOAD. */ -+ -+static void -+elf64_sw_64_merge_symbol_attribute (struct elf_link_hash_entry *h, -+ unsigned int st_other, bool definition, -+ bool dynamic) -+{ -+ if (!dynamic && definition) -+ h->other = ((h->other & ELF_ST_VISIBILITY (-1)) -+ | (st_other & ~ELF_ST_VISIBILITY (-1))); -+} -+ -+/* Symbol versioning can create new symbols, and make our old symbols -+ indirect to the new ones. Consolidate the got and reloc information -+ in these situations. */ -+ -+static void -+elf64_sw_64_copy_indirect_symbol (struct bfd_link_info *info, -+ struct elf_link_hash_entry *dir, -+ struct elf_link_hash_entry *ind) -+{ -+ struct sw_64_elf_link_hash_entry *hi -+ = (struct sw_64_elf_link_hash_entry *) ind; -+ struct sw_64_elf_link_hash_entry *hs -+ = (struct sw_64_elf_link_hash_entry *) dir; -+ -+ /* Do the merging in the superclass. */ -+ _bfd_elf_link_hash_copy_indirect (info, dir, ind); -+ -+ /* Merge the flags. Whee. */ -+ hs->flags |= hi->flags; -+ -+ /* ??? It's unclear to me what's really supposed to happen when -+ "merging" defweak and defined symbols, given that we don't -+ actually throw away the defweak. This more-or-less copies -+ the logic related to got and plt entries in the superclass. */ -+ if (ind->root.type != bfd_link_hash_indirect) -+ return; -+ -+ /* Merge the .got entries. Cannibalize the old symbol's list in -+ doing so, since we don't need it anymore. */ -+ -+ if (hs->got_entries == NULL) -+ hs->got_entries = hi->got_entries; -+ else -+ { -+ struct sw_64_elf_got_entry *gi, *gs, *gin, *gsh; -+ -+ gsh = hs->got_entries; -+ for (gi = hi->got_entries; gi; gi = gin) -+ { -+ gin = gi->next; -+ for (gs = gsh; gs; gs = gs->next) -+ if (gi->gotobj == gs->gotobj && gi->reloc_type == gs->reloc_type -+ && gi->addend == gs->addend) -+ { -+ gs->use_count += gi->use_count; -+ goto got_found; -+ } -+ gi->next = hs->got_entries; -+ hs->got_entries = gi; -+ got_found:; -+ } -+ } -+ hi->got_entries = NULL; -+ -+ /* And similar for the reloc entries. */ -+ -+ if (hs->reloc_entries == NULL) -+ hs->reloc_entries = hi->reloc_entries; -+ else -+ { -+ struct sw_64_elf_reloc_entry *ri, *rs, *rin, *rsh; -+ -+ rsh = hs->reloc_entries; -+ for (ri = hi->reloc_entries; ri; ri = rin) -+ { -+ rin = ri->next; -+ for (rs = rsh; rs; rs = rs->next) -+ if (ri->rtype == rs->rtype && ri->srel == rs->srel) -+ { -+ rs->count += ri->count; -+ goto found_reloc; -+ } -+ ri->next = hs->reloc_entries; -+ hs->reloc_entries = ri; -+ found_reloc:; -+ } -+ } -+ hi->reloc_entries = NULL; -+} -+ -+/* Is it possible to merge two object file's .got tables? */ -+ -+static bool -+elf64_sw_64_can_merge_gots (bfd *a, bfd *b) -+{ -+ int total = sw_64_elf_tdata (a)->total_got_size; -+ bfd *bsub; -+ -+ /* Trivial quick fallout test. */ -+ if (total + sw_64_elf_tdata (b)->total_got_size <= MAX_GOT_SIZE) -+ return true; -+ -+ /* By their nature, local .got entries cannot be merged. */ -+ if ((total += sw_64_elf_tdata (b)->local_got_size) > MAX_GOT_SIZE) -+ return false; -+ -+ /* Failing the common trivial comparison, we must effectively -+ perform the merge. Not actually performing the merge means that -+ we don't have to store undo information in case we fail. */ -+ for (bsub = b; bsub; bsub = sw_64_elf_tdata (bsub)->in_got_link_next) -+ { -+ struct sw_64_elf_link_hash_entry **hashes = sw_64_elf_sym_hashes (bsub); -+ Elf_Internal_Shdr *symtab_hdr = &elf_tdata (bsub)->symtab_hdr; -+ int i, n; -+ -+ n = NUM_SHDR_ENTRIES (symtab_hdr) - symtab_hdr->sh_info; -+ for (i = 0; i < n; ++i) -+ { -+ struct sw_64_elf_got_entry *ae, *be; -+ struct sw_64_elf_link_hash_entry *h; -+ -+ h = hashes[i]; -+ while (h->root.root.type == bfd_link_hash_indirect -+ || h->root.root.type == bfd_link_hash_warning) -+ h = (struct sw_64_elf_link_hash_entry *) h->root.root.u.i.link; -+ -+ for (be = h->got_entries; be; be = be->next) -+ { -+ if (be->use_count == 0) -+ continue; -+ if (be->gotobj != b) -+ continue; -+ -+ for (ae = h->got_entries; ae; ae = ae->next) -+ if (ae->gotobj == a && ae->reloc_type == be->reloc_type -+ && ae->addend == be->addend) -+ goto global_found; -+ -+ total += sw_64_got_entry_size (be->reloc_type); -+ if (total > MAX_GOT_SIZE) -+ return false; -+ global_found:; -+ } -+ } -+ } -+ -+ return true; -+} -+ -+/* Actually merge two .got tables. */ -+ -+static void -+elf64_sw_64_merge_gots (bfd *a, bfd *b) -+{ -+ int total = sw_64_elf_tdata (a)->total_got_size; -+ bfd *bsub; -+ -+ /* Remember local expansion. */ -+ { -+ int e = sw_64_elf_tdata (b)->local_got_size; -+ total += e; -+ sw_64_elf_tdata (a)->local_got_size += e; -+ } -+ -+ for (bsub = b; bsub; bsub = sw_64_elf_tdata (bsub)->in_got_link_next) -+ { -+ struct sw_64_elf_got_entry **local_got_entries; -+ struct sw_64_elf_link_hash_entry **hashes; -+ Elf_Internal_Shdr *symtab_hdr; -+ int i, n; -+ -+ /* Let the local .got entries know they are part of a new subsegment. */ -+ local_got_entries = sw_64_elf_tdata (bsub)->local_got_entries; -+ if (local_got_entries) -+ { -+ n = elf_tdata (bsub)->symtab_hdr.sh_info; -+ for (i = 0; i < n; ++i) -+ { -+ struct sw_64_elf_got_entry *ent; -+ for (ent = local_got_entries[i]; ent; ent = ent->next) -+ ent->gotobj = a; -+ } -+ } -+ -+ /* Merge the global .got entries. */ -+ hashes = sw_64_elf_sym_hashes (bsub); -+ symtab_hdr = &elf_tdata (bsub)->symtab_hdr; -+ -+ n = NUM_SHDR_ENTRIES (symtab_hdr) - symtab_hdr->sh_info; -+ for (i = 0; i < n; ++i) -+ { -+ struct sw_64_elf_got_entry *ae, *be, **pbe, **start; -+ struct sw_64_elf_link_hash_entry *h; -+ -+ h = hashes[i]; -+ while (h->root.root.type == bfd_link_hash_indirect -+ || h->root.root.type == bfd_link_hash_warning) -+ h = (struct sw_64_elf_link_hash_entry *) h->root.root.u.i.link; -+ -+ pbe = start = &h->got_entries; -+ while ((be = *pbe) != NULL) -+ { -+ if (be->use_count == 0) -+ { -+ *pbe = be->next; -+ memset (be, 0xa5, sizeof (*be)); -+ goto kill; -+ } -+ if (be->gotobj != b) -+ goto next; -+ -+ for (ae = *start; ae; ae = ae->next) -+ if (ae->gotobj == a && ae->reloc_type == be->reloc_type -+ && ae->addend == be->addend) -+ { -+ ae->flags |= be->flags; -+ ae->use_count += be->use_count; -+ *pbe = be->next; -+ memset (be, 0xa5, sizeof (*be)); -+ goto kill; -+ } -+ be->gotobj = a; -+ total += sw_64_got_entry_size (be->reloc_type); -+ -+ next:; -+ pbe = &be->next; -+ kill:; -+ } -+ } -+ -+ sw_64_elf_tdata (bsub)->gotobj = a; -+ } -+ sw_64_elf_tdata (a)->total_got_size = total; -+ -+ /* Merge the two in_got chains. */ -+ { -+ bfd *next; -+ -+ bsub = a; -+ while ((next = sw_64_elf_tdata (bsub)->in_got_link_next) != NULL) -+ bsub = next; -+ -+ sw_64_elf_tdata (bsub)->in_got_link_next = b; -+ } -+} -+ -+/* Calculate the offsets for the got entries. */ -+ -+static bool -+elf64_sw_64_calc_got_offsets_for_symbol (struct sw_64_elf_link_hash_entry *h, -+ void *arg ATTRIBUTE_UNUSED) -+{ -+ struct sw_64_elf_got_entry *gotent; -+ -+ for (gotent = h->got_entries; gotent; gotent = gotent->next) -+ if (gotent->use_count > 0) -+ { -+ struct sw_64_elf_obj_tdata *td; -+ bfd_size_type *plge; -+ -+ td = sw_64_elf_tdata (gotent->gotobj); -+ plge = &td->got->size; -+ gotent->got_offset = *plge; -+ *plge += sw_64_got_entry_size (gotent->reloc_type); -+ } -+ -+ return true; -+} -+ -+static void -+elf64_sw_64_calc_got_offsets (struct bfd_link_info *info) -+{ -+ bfd *i, *got_list; -+ struct sw_64_elf_link_hash_table *htab; -+ -+ htab = sw_64_elf_hash_table (info); -+ if (htab == NULL) -+ return; -+ got_list = htab->got_list; -+ -+ /* First, zero out the .got sizes, as we may be recalculating the -+ .got after optimizing it. */ -+ for (i = got_list; i; i = sw_64_elf_tdata (i)->got_link_next) -+ sw_64_elf_tdata (i)->got->size = 0; -+ -+ /* Next, fill in the offsets for all the global entries. */ -+ sw_64_elf_link_hash_traverse (htab, elf64_sw_64_calc_got_offsets_for_symbol, -+ NULL); -+ -+ /* Finally, fill in the offsets for the local entries. */ -+ for (i = got_list; i; i = sw_64_elf_tdata (i)->got_link_next) -+ { -+ bfd_size_type got_offset = sw_64_elf_tdata (i)->got->size; -+ bfd *j; -+ -+ for (j = i; j; j = sw_64_elf_tdata (j)->in_got_link_next) -+ { -+ struct sw_64_elf_got_entry **local_got_entries, *gotent; -+ int k, n; -+ -+ local_got_entries = sw_64_elf_tdata (j)->local_got_entries; -+ if (!local_got_entries) -+ continue; -+ -+ for (k = 0, n = elf_tdata (j)->symtab_hdr.sh_info; k < n; ++k) -+ for (gotent = local_got_entries[k]; gotent; gotent = gotent->next) -+ if (gotent->use_count > 0) -+ { -+ gotent->got_offset = got_offset; -+ got_offset += sw_64_got_entry_size (gotent->reloc_type); -+ } -+ } -+ -+ sw_64_elf_tdata (i)->got->size = got_offset; -+ } -+} -+ -+/* Constructs the gots. */ -+ -+static bool -+elf64_sw_64_size_got_sections (struct bfd_link_info *info, bool may_merge) -+{ -+ bfd *i, *got_list, *cur_got_obj = NULL; -+ struct sw_64_elf_link_hash_table *htab; -+ -+ htab = sw_64_elf_hash_table (info); -+ if (htab == NULL) -+ return false; -+ got_list = htab->got_list; -+ -+ /* On the first time through, pretend we have an existing got list -+ consisting of all of the input files. */ -+ if (got_list == NULL) -+ { -+ for (i = info->input_bfds; i; i = i->link.next) -+ { -+ bfd *this_got; -+ -+ if (!is_sw_64_elf (i)) -+ continue; -+ -+ this_got = sw_64_elf_tdata (i)->gotobj; -+ if (this_got == NULL) -+ continue; -+ -+ /* We are assuming no merging has yet occurred. */ -+ BFD_ASSERT (this_got == i); -+ -+ if (sw_64_elf_tdata (this_got)->total_got_size > MAX_GOT_SIZE_NEW) -+ { -+ /* Yikes! A single object file has too many entries. */ -+ _bfd_error_handler -+ /* xgettext:c-format */ -+ (_ ("%pB: .got subsegment exceeds 2G (size %d)"), i, -+ sw_64_elf_tdata (this_got)->total_got_size); -+ return false; -+ } -+ -+ if (got_list == NULL) -+ got_list = this_got; -+ else -+ sw_64_elf_tdata (cur_got_obj)->got_link_next = this_got; -+ cur_got_obj = this_got; -+ } -+ -+ /* Strange degenerate case of no got references. */ -+ if (got_list == NULL) -+ return true; -+ -+ htab->got_list = got_list; -+ } -+ -+ cur_got_obj = got_list; -+ if (cur_got_obj == NULL) -+ return false; -+ -+ if (may_merge) -+ { -+ i = sw_64_elf_tdata (cur_got_obj)->got_link_next; -+ while (i != NULL) -+ { -+ if (elf64_sw_64_can_merge_gots (cur_got_obj, i)) -+ { -+ elf64_sw_64_merge_gots (cur_got_obj, i); -+ -+ sw_64_elf_tdata (i)->got->size = 0; -+ i = sw_64_elf_tdata (i)->got_link_next; -+ sw_64_elf_tdata (cur_got_obj)->got_link_next = i; -+ } -+ else -+ { -+ cur_got_obj = i; -+ i = sw_64_elf_tdata (i)->got_link_next; -+ } -+ } -+ } -+ -+ /* Once the gots have been merged, fill in the got offsets for -+ everything therein. */ -+ elf64_sw_64_calc_got_offsets (info); -+ -+ return true; -+} -+ -+static bool -+elf64_sw_64_size_plt_section_1 (struct sw_64_elf_link_hash_entry *h, void *data) -+{ -+ asection *splt = (asection *) data; -+ struct sw_64_elf_got_entry *gotent; -+ bool saw_one = false; -+ -+ /* If we didn't need an entry before, we still don't. */ -+ if (!h->root.needs_plt) -+ return true; -+ -+ /* For each LITERAL got entry still in use, allocate a plt entry. */ -+ for (gotent = h->got_entries; gotent; gotent = gotent->next) -+ if (gotent->reloc_type == R_SW_64_LITERAL && gotent->use_count > 0) -+ { -+ if (splt->size == 0) -+ splt->size = PLT_HEADER_SIZE; -+ gotent->plt_offset = splt->size; -+ splt->size += PLT_ENTRY_SIZE; -+ saw_one = true; -+ } -+ -+ /* If there weren't any, there's no longer a need for the PLT entry. */ -+ if (!saw_one) -+ h->root.needs_plt = false; -+ -+ return true; -+} -+ -+/* Called from relax_section to rebuild the PLT in light of potential changes -+ in the function's status. */ -+ -+static void -+elf64_sw_64_size_plt_section (struct bfd_link_info *info) -+{ -+ asection *splt, *spltrel, *sgotplt; -+ unsigned long entries; -+ struct sw_64_elf_link_hash_table *htab; -+ -+ htab = sw_64_elf_hash_table (info); -+ if (htab == NULL) -+ return; -+ -+ splt = elf_hash_table (info)->splt; -+ if (splt == NULL) -+ return; -+ -+ splt->size = 0; -+ -+ sw_64_elf_link_hash_traverse (htab, elf64_sw_64_size_plt_section_1, splt); -+ -+ /* Every plt entry requires a JMP_SLOT relocation. */ -+ spltrel = elf_hash_table (info)->srelplt; -+ entries = 0; -+ if (splt->size) -+ { -+ if (elf64_sw_64_use_secureplt) -+ entries = (splt->size - NEW_PLT_HEADER_SIZE) / NEW_PLT_ENTRY_SIZE; -+ else -+ entries = (splt->size - OLD_PLT_HEADER_SIZE) / OLD_PLT_ENTRY_SIZE; -+ } -+ spltrel->size = entries * sizeof (Elf64_External_Rela); -+ -+ /* When using the secureplt, we need two words somewhere in the data -+ segment for the dynamic linker to tell us where to go. This is the -+ entire contents of the .got.plt section. */ -+ if (elf64_sw_64_use_secureplt) -+ { -+ sgotplt = elf_hash_table (info)->sgotplt; -+ sgotplt->size = entries ? 16 : 0; -+ } -+} -+ -+static bool -+elf64_sw_64_always_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED, -+ struct bfd_link_info *info) -+{ -+ bfd *i; -+ struct sw_64_elf_link_hash_table *htab; -+ -+ if (bfd_link_relocatable (info)) -+ return true; -+ -+ htab = sw_64_elf_hash_table (info); -+ if (htab == NULL) -+ return false; -+ -+ if (!elf64_sw_64_size_got_sections (info, true)) -+ return false; -+ -+ /* Allocate space for all of the .got subsections. */ -+ i = htab->got_list; -+ for (; i; i = sw_64_elf_tdata (i)->got_link_next) -+ { -+ asection *s = sw_64_elf_tdata (i)->got; -+ if (s->size > 0) -+ { -+ s->contents = (bfd_byte *) bfd_zalloc (i, s->size); -+ if (s->contents == NULL) -+ return false; -+ } -+ } -+ -+ return true; -+} -+ -+/* The number of dynamic relocations required by a static relocation. */ -+ -+static int -+sw_64_dynamic_entries_for_reloc (int r_type, int dynamic, int shared, int pie) -+{ -+ switch (r_type) -+ { -+ /* May appear in GOT entries. */ -+ case R_SW_64_TLSGD: -+ return (dynamic ? 2 : shared ? 1 : 0); -+ case R_SW_64_TLSLDM: -+ return shared; -+ case R_SW_64_LITERAL: -+ return dynamic || shared; -+ case R_SW_64_GOTTPREL: -+ return dynamic || (shared && !pie); -+ case R_SW_64_GOTDTPREL: -+ return dynamic; -+ -+ /* May appear in data sections. */ -+ case R_SW_64_REFLONG: -+ case R_SW_64_REFQUAD: -+ return dynamic || shared; -+ case R_SW_64_TPREL64: -+ return dynamic || (shared && !pie); -+ -+ /* Everything else is illegal. We'll issue an error during -+ relocate_section. */ -+ default: -+ return 0; -+ } -+} -+ -+/* Work out the sizes of the dynamic relocation entries. */ -+ -+static bool -+elf64_sw_64_calc_dynrel_sizes (struct sw_64_elf_link_hash_entry *h, -+ struct bfd_link_info *info) -+{ -+ bool dynamic; -+ struct sw_64_elf_reloc_entry *relent; -+ unsigned long entries; -+ -+ /* If the symbol was defined as a common symbol in a regular object -+ file, and there was no definition in any dynamic object, then the -+ linker will have allocated space for the symbol in a common -+ section but the ELF_LINK_HASH_DEF_REGULAR flag will not have been -+ set. This is done for dynamic symbols in -+ elf_adjust_dynamic_symbol but this is not done for non-dynamic -+ symbols, somehow. */ -+ if (!h->root.def_regular && h->root.ref_regular && !h->root.def_dynamic -+ && (h->root.root.type == bfd_link_hash_defined -+ || h->root.root.type == bfd_link_hash_defweak) -+ && !(h->root.root.u.def.section->owner->flags & DYNAMIC)) -+ h->root.def_regular = 1; -+ -+ /* If the symbol is dynamic, we'll need all the relocations in their -+ natural form. If this is a shared object, and it has been forced -+ local, we'll need the same number of RELATIVE relocations. */ -+ dynamic = sw_64_elf_dynamic_symbol_p (&h->root, info); -+ -+ /* If the symbol is a hidden undefined weak, then we never have any -+ relocations. Avoid the loop which may want to add RELATIVE relocs -+ based on bfd_link_pic (info). */ -+ if (h->root.root.type == bfd_link_hash_undefweak && !dynamic) -+ return true; -+ -+ for (relent = h->reloc_entries; relent; relent = relent->next) -+ { -+ entries = sw_64_dynamic_entries_for_reloc (relent->rtype, dynamic, -+ bfd_link_pic (info), -+ bfd_link_pie (info)); -+ if (entries) -+ { -+ asection *sec = relent->sec; -+ relent->srel->size -+ += entries * sizeof (Elf64_External_Rela) * relent->count; -+ if ((sec->flags & SEC_READONLY) != 0) -+ { -+ info->flags |= DT_TEXTREL; -+ info->callbacks->minfo ( -+ _ ("%pB: dynamic relocation against `T' in " -+ "read-only section `%pA'\n"), -+ sec->owner, sec); -+ } -+ } -+ } -+ -+ return true; -+} -+ -+/* Subroutine of elf64_sw_64_size_rela_got_section for doing the -+ global symbols. */ -+ -+static bool -+elf64_sw_64_size_rela_got_1 (struct sw_64_elf_link_hash_entry *h, -+ struct bfd_link_info *info) -+{ -+ bool dynamic; -+ struct sw_64_elf_got_entry *gotent; -+ unsigned long entries; -+ -+ /* If we're using a plt for this symbol, then all of its relocations -+ for its got entries go into .rela.plt. */ -+ if (h->root.needs_plt) -+ return true; -+ -+ /* If the symbol is dynamic, we'll need all the relocations in their -+ natural form. If this is a shared object, and it has been forced -+ local, we'll need the same number of RELATIVE relocations. */ -+ dynamic = sw_64_elf_dynamic_symbol_p (&h->root, info); -+ -+ /* If the symbol is a hidden undefined weak, then we never have any -+ relocations. Avoid the loop which may want to add RELATIVE relocs -+ based on bfd_link_pic (info). */ -+ if (h->root.root.type == bfd_link_hash_undefweak && !dynamic) -+ return true; -+ -+ entries = 0; -+ for (gotent = h->got_entries; gotent; gotent = gotent->next) -+ if (gotent->use_count > 0) -+ entries += sw_64_dynamic_entries_for_reloc (gotent->reloc_type, dynamic, -+ bfd_link_pic (info), -+ bfd_link_pie (info)); -+ -+ if (entries > 0) -+ { -+ asection *srel = elf_hash_table (info)->srelgot; -+ BFD_ASSERT (srel != NULL); -+ srel->size += sizeof (Elf64_External_Rela) * entries; -+ } -+ -+ return true; -+} -+ -+/* Set the sizes of the dynamic relocation sections. */ -+ -+static void -+elf64_sw_64_size_rela_got_section (struct bfd_link_info *info) -+{ -+ unsigned long entries; -+ bfd *i; -+ asection *srel; -+ struct sw_64_elf_link_hash_table *htab; -+ -+ htab = sw_64_elf_hash_table (info); -+ if (htab == NULL) -+ return; -+ -+ /* Shared libraries often require RELATIVE relocs, and some relocs -+ require attention for the main application as well. */ -+ -+ entries = 0; -+ for (i = htab->got_list; i; i = sw_64_elf_tdata (i)->got_link_next) -+ { -+ bfd *j; -+ -+ for (j = i; j; j = sw_64_elf_tdata (j)->in_got_link_next) -+ { -+ struct sw_64_elf_got_entry **local_got_entries, *gotent; -+ int k, n; -+ -+ local_got_entries = sw_64_elf_tdata (j)->local_got_entries; -+ if (!local_got_entries) -+ continue; -+ -+ for (k = 0, n = elf_tdata (j)->symtab_hdr.sh_info; k < n; ++k) -+ for (gotent = local_got_entries[k]; gotent; gotent = gotent->next) -+ if (gotent->use_count > 0) -+ entries -+ += (sw_64_dynamic_entries_for_reloc (gotent->reloc_type, 0, -+ bfd_link_pic (info), -+ bfd_link_pie (info))); -+ } -+ } -+ -+ srel = elf_hash_table (info)->srelgot; -+ if (!srel) -+ { -+ BFD_ASSERT (entries == 0); -+ return; -+ } -+ srel->size = sizeof (Elf64_External_Rela) * entries; -+ -+ /* Now do the non-local symbols. */ -+ sw_64_elf_link_hash_traverse (htab, elf64_sw_64_size_rela_got_1, info); -+} -+ -+/* Set the sizes of the dynamic sections. */ -+ -+static bool -+elf64_sw_64_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED, -+ struct bfd_link_info *info) -+{ -+ bfd *dynobj; -+ asection *s; -+ bool relplt, relocs; -+ struct sw_64_elf_link_hash_table *htab; -+ -+ htab = sw_64_elf_hash_table (info); -+ if (htab == NULL) -+ return false; -+ -+ dynobj = elf_hash_table (info)->dynobj; -+ BFD_ASSERT (dynobj != NULL); -+ -+ if (elf_hash_table (info)->dynamic_sections_created) -+ { -+ /* Set the contents of the .interp section to the interpreter. */ -+ if (bfd_link_executable (info) && !info->nointerp) -+ { -+ s = bfd_get_linker_section (dynobj, ".interp"); -+ BFD_ASSERT (s != NULL); -+ s->size = sizeof ELF_DYNAMIC_INTERPRETER; -+ s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER; -+ } -+ -+ /* Now that we've seen all of the input files, we can decide which -+ symbols need dynamic relocation entries and which don't. We've -+ collected information in check_relocs that we can now apply to -+ size the dynamic relocation sections. */ -+ sw_64_elf_link_hash_traverse (htab, elf64_sw_64_calc_dynrel_sizes, info); -+ -+ elf64_sw_64_size_rela_got_section (info); -+ elf64_sw_64_size_plt_section (info); -+ } -+ /* else we're not dynamic and by definition we don't need such things. */ -+ -+ /* The check_relocs and adjust_dynamic_symbol entry points have -+ determined the sizes of the various dynamic sections. Allocate -+ memory for them. */ -+ relplt = false; -+ relocs = false; -+ for (s = dynobj->sections; s != NULL; s = s->next) -+ { -+ const char *name; -+ -+ if (!(s->flags & SEC_LINKER_CREATED)) -+ continue; -+ -+ /* It's OK to base decisions on the section name, because none -+ of the dynobj section names depend upon the input files. */ -+ name = bfd_section_name (s); -+ -+ if (startswith (name, ".rela")) -+ { -+ if (s->size != 0) -+ { -+ if (strcmp (name, ".rela.plt") == 0) -+ relplt = true; -+ else -+ relocs = true; -+ -+ /* We use the reloc_count field as a counter if we need -+ to copy relocs into the output file. */ -+ s->reloc_count = 0; -+ } -+ } -+ else if (!startswith (name, ".got") && strcmp (name, ".plt") != 0 -+ && strcmp (name, ".dynbss") != 0) -+ { -+ /* It's not one of our dynamic sections, so don't allocate space. */ -+ continue; -+ } -+ -+ if (s->size == 0) -+ { -+ /* If we don't need this section, strip it from the output file. -+ This is to handle .rela.bss and .rela.plt. We must create it -+ in create_dynamic_sections, because it must be created before -+ the linker maps input sections to output sections. The -+ linker does that before adjust_dynamic_symbol is called, and -+ it is that function which decides whether anything needs to -+ go into these sections. */ -+ if (!startswith (name, ".got")) -+ s->flags |= SEC_EXCLUDE; -+ } -+ else if ((s->flags & SEC_HAS_CONTENTS) != 0) -+ { -+ /* Allocate memory for the section contents. */ -+ s->contents = (bfd_byte *) bfd_zalloc (dynobj, s->size); -+ if (s->contents == NULL) -+ return false; -+ } -+ } -+ -+ if (elf_hash_table (info)->dynamic_sections_created) -+ { -+ /* Add some entries to the .dynamic section. We fill in the -+ values later, in elf64_sw_64_finish_dynamic_sections, but we -+ must add the entries now so that we get the correct size for -+ the .dynamic section. The DT_DEBUG entry is filled in by the -+ dynamic linker and used by the debugger. */ -+#define add_dynamic_entry(TAG, VAL) _bfd_elf_add_dynamic_entry (info, TAG, VAL) -+ -+ if (bfd_link_executable (info)) -+ { -+ if (!add_dynamic_entry (DT_DEBUG, 0)) -+ return false; -+ } -+ -+ if (relplt) -+ { -+ if (!add_dynamic_entry (DT_PLTGOT, 0) -+ || !add_dynamic_entry (DT_PLTRELSZ, 0) -+ || !add_dynamic_entry (DT_PLTREL, DT_RELA) -+ || !add_dynamic_entry (DT_JMPREL, 0)) -+ return false; -+ -+ if (elf64_sw_64_use_secureplt -+ && !add_dynamic_entry (DT_SW_64_PLTRO, 1)) -+ return false; -+ } -+ -+ if (relocs) -+ { -+ if (!add_dynamic_entry (DT_RELA, 0) -+ || !add_dynamic_entry (DT_RELASZ, 0) -+ || !add_dynamic_entry (DT_RELAENT, sizeof (Elf64_External_Rela))) -+ return false; -+ -+ if (info->flags & DF_TEXTREL) -+ { -+ if (!add_dynamic_entry (DT_TEXTREL, 0)) -+ return false; -+ } -+ } -+ } -+#undef add_dynamic_entry -+ -+ return true; -+} -+ -+/* These functions do relaxation for Sw_64 ELF. -+ -+ Currently I'm only handling what I can do with existing compiler -+ and assembler support, which means no instructions are removed, -+ though some may be nopped. At this time GCC does not emit enough -+ information to do all of the relaxing that is possible. It will -+ take some not small amount of work for that to happen. -+ -+ There are a couple of interesting papers that I once read on this -+ subject, that I cannot find references to at the moment, that -+ related to Sw_64 in particular. They are by David Wall, then of -+ DEC WRL. */ -+ -+struct sw_64_relax_info -+{ -+ bfd *abfd; -+ asection *sec; -+ bfd_byte *contents; -+ Elf_Internal_Shdr *symtab_hdr; -+ Elf_Internal_Rela *relocs, *relend; -+ struct bfd_link_info *link_info; -+ bfd_vma gp; -+ bfd *gotobj; -+ asection *tsec; -+ struct sw_64_elf_link_hash_entry *h; -+ struct sw_64_elf_got_entry **first_gotent; -+ struct sw_64_elf_got_entry *gotent; -+ bool changed_contents; -+ bool changed_relocs; -+ unsigned char other; -+}; -+ -+static Elf_Internal_Rela * -+elf64_sw_64_find_reloc_at_ofs (Elf_Internal_Rela *rel, -+ Elf_Internal_Rela *relend, bfd_vma offset, -+ int type) -+{ -+ while (rel < relend) -+ { -+ if (rel->r_offset == offset -+ && ELF64_R_TYPE (rel->r_info) == (unsigned int) type) -+ return rel; -+ ++rel; -+ } -+ return NULL; -+} -+ -+static bool -+elf64_sw_64_relax_got_load (struct sw_64_relax_info *info, bfd_vma symval, -+ Elf_Internal_Rela *irel, unsigned long r_type) -+{ -+ unsigned int insn; -+ bfd_signed_vma disp; -+ -+ /* Get the instruction. */ -+ insn = bfd_get_32 (info->abfd, info->contents + irel->r_offset); -+ -+ if (insn >> 26 != OP_LDL && insn >> 26 != OP_LDW) -+ { -+ reloc_howto_type *howto = elf64_sw_64_howto_table + r_type; -+ _bfd_error_handler -+ /* xgettext:c-format */ -+ (_ ("%pB: %pA+%#" PRIx64 ": warning: " -+ "%s relocation against unexpected insn"), -+ info->abfd, info->sec, (uint64_t) irel->r_offset, howto->name); -+ return true; -+ } -+ -+ /* Can't relax dynamic symbols. */ -+ if (info->h != NULL -+ && sw_64_elf_dynamic_symbol_p (&info->h->root, info->link_info)) -+ return true; -+ -+ /* Can't use local-exec relocations in shared libraries. */ -+ if (r_type == R_SW_64_GOTTPREL && bfd_link_dll (info->link_info)) -+ return true; -+ -+ if (r_type == R_SW_64_LITERAL) -+ { -+ /* Look for nice constant addresses. This includes the not-uncommon -+ special case of 0 for undefweak symbols. */ -+ if ((info->h && info->h->root.root.type == bfd_link_hash_undefweak) -+ || (!bfd_link_pic (info->link_info) -+ && (symval >= (bfd_vma) -0x8000 || symval < 0x8000))) -+ { -+ disp = 0; -+ insn = (OP_LDI << 26) | (insn & (31 << 21)) | (31 << 16); -+ insn |= (symval & 0xffff); -+ r_type = R_SW_64_NONE; -+ } -+ else -+ { -+ /* We may only create GPREL relocs during the second pass. */ -+ if ((info->link_info->relax_pass == 0) -+ || !(symval >= (bfd_vma) -0x8000 || symval < 0x8000)) -+ return true; -+ -+ disp = symval - info->gp; -+ insn = (OP_LDI << 26) | (insn & 0x03ff0000); -+ r_type = R_SW_64_GPREL16; -+ } -+ } -+ else -+ { -+ bfd_vma dtp_base, tp_base; -+ -+ BFD_ASSERT (elf_hash_table (info->link_info)->tls_sec != NULL); -+ dtp_base = sw_64_get_dtprel_base (info->link_info); -+ tp_base = sw_64_get_tprel_base (info->link_info); -+ disp = symval - (r_type == R_SW_64_GOTDTPREL ? dtp_base : tp_base); -+ -+ insn = (OP_LDI << 26) | (insn & (31 << 21)) | (31 << 16); -+ -+ switch (r_type) -+ { -+ case R_SW_64_GOTDTPREL: -+ r_type = R_SW_64_DTPREL16; -+ break; -+ case R_SW_64_GOTTPREL: -+ r_type = R_SW_64_TPREL16; -+ break; -+ default: -+ BFD_ASSERT (0); -+ return false; -+ } -+ } -+ -+ if (disp < -0x8000 || disp >= 0x8000) -+ return true; -+ -+ bfd_put_32 (info->abfd, (bfd_vma) insn, info->contents + irel->r_offset); -+ info->changed_contents = true; -+ -+ /* Reduce the use count on this got entry by one, possibly -+ eliminating it. */ -+ if (--info->gotent->use_count == 0) -+ { -+ int sz = sw_64_got_entry_size (r_type); -+ sw_64_elf_tdata (info->gotobj)->total_got_size -= sz; -+ if (!info->h) -+ sw_64_elf_tdata (info->gotobj)->local_got_size -= sz; -+ } -+ -+ /* Smash the existing GOT relocation for its 16-bit immediate pair. */ -+ irel->r_info = ELF64_R_INFO (ELF64_R_SYM (irel->r_info), r_type); -+ info->changed_relocs = true; -+ -+ /* ??? Search forward through this basic block looking for insns -+ that use the target register. Stop after an insn modifying the -+ register is seen, or after a branch or call. -+ -+ Any such memory load insn may be substituted by a load directly -+ off the GP. This allows the memory load insn to be issued before -+ the calculated GP register would otherwise be ready. -+ -+ Any such jsr insn can be replaced by a bsr if it is in range. -+ -+ This would mean that we'd have to _add_ relocations, the pain of -+ which gives one pause. */ -+ -+ return true; -+} -+ -+static bfd_vma -+elf64_sw_64_relax_opt_call (struct sw_64_relax_info *info, bfd_vma symval) -+{ -+ /* If the function has the same gp, and we can identify that the -+ function does not use its function pointer, we can eliminate the -+ address load. */ -+ -+ /* If the symbol is marked NOPV, we are being told the function never -+ needs its procedure value. */ -+ if ((info->other & STO_SW_64_STD_GPLOAD) == STO_SW_64_NOPV) -+ return symval; -+ -+ /* If the symbol is marked STD_GP, we are being told the function does -+ a normal ldgp in the first two words. */ -+ else if ((info->other & STO_SW_64_STD_GPLOAD) == STO_SW_64_STD_GPLOAD) -+ ; -+ -+ /* Otherwise, we may be able to identify a GP load in the first two -+ words, which we can then skip. */ -+ else -+ { -+ Elf_Internal_Rela *tsec_relocs, *tsec_relend, *tsec_free, *gpdisp; -+ bfd_vma ofs; -+ -+ /* Load the relocations from the section that the target symbol is in. */ -+ if (info->sec == info->tsec) -+ { -+ tsec_relocs = info->relocs; -+ tsec_relend = info->relend; -+ tsec_free = NULL; -+ } -+ else -+ { -+ tsec_relocs -+ = (_bfd_elf_link_read_relocs (info->abfd, info->tsec, NULL, -+ (Elf_Internal_Rela *) NULL, -+ info->link_info->keep_memory)); -+ if (tsec_relocs == NULL) -+ return 0; -+ tsec_relend = tsec_relocs + info->tsec->reloc_count; -+ tsec_free = (elf_section_data (info->tsec)->relocs == tsec_relocs -+ ? NULL -+ : tsec_relocs); -+ } -+ -+ /* Recover the symbol's offset within the section. */ -+ ofs = (symval - info->tsec->output_section->vma -+ - info->tsec->output_offset); -+ -+ /* Look for a GPDISP reloc. */ -+ gpdisp = (elf64_sw_64_find_reloc_at_ofs (tsec_relocs, tsec_relend, ofs, -+ R_SW_64_GPDISP)); -+ -+ if (!gpdisp || gpdisp->r_addend != 4) -+ { -+ free (tsec_free); -+ return 0; -+ } -+ free (tsec_free); -+ } -+ -+ /* We've now determined that we can skip an initial gp load. Verify -+ that the call and the target use the same gp. */ -+ if (info->link_info->output_bfd->xvec != info->tsec->owner->xvec -+ || info->gotobj != sw_64_elf_tdata (info->tsec->owner)->gotobj) -+ return 0; -+ -+ return symval + 8; -+} -+ -+int addpi_flag = 0; -+bfd_signed_vma addpi_odisp = 0; -+int ldr_offset = 0; -+static bool -+elf64_sw_64_relax_with_lituse (struct sw_64_relax_info *info, bfd_vma symval, -+ Elf_Internal_Rela *irel) -+{ -+ Elf_Internal_Rela *urel, *erel, *irelend = info->relend; -+ int flags; -+ bfd_signed_vma disp; -+ bool fits16; -+ bool fits32; -+ bool lit_reused = false; -+ bool all_optimized = true; -+ bool changed_contents; -+ bool changed_relocs; -+ bfd_byte *contents = info->contents; -+ bfd *abfd = info->abfd; -+ bfd_vma sec_output_vma; -+ unsigned int lit_insn; -+ int relax_pass; -+ -+ lit_insn = bfd_get_32 (abfd, contents + irel->r_offset); -+ if (lit_insn >> 26 != OP_LDL && lit_insn >> 26 != OP_LDW) -+ { -+ _bfd_error_handler -+ /* xgettext:c-format */ -+ (_ ("%pB: %pA+%#" PRIx64 ": warning: " -+ "%s relocation against unexpected insn"), -+ abfd, info->sec, (uint64_t) irel->r_offset, "LITERAL"); -+ return true; -+ } -+ -+ /* Can't relax dynamic symbols. */ -+ if (info->h != NULL -+ && sw_64_elf_dynamic_symbol_p (&info->h->root, info->link_info)) -+ return true; -+ -+ changed_contents = info->changed_contents; -+ changed_relocs = info->changed_relocs; -+ sec_output_vma = info->sec->output_section->vma + info->sec->output_offset; -+ relax_pass = info->link_info->relax_pass; -+ -+ /* Summarize how this particular LITERAL is used. */ -+ for (erel = irel + 1, flags = 0; erel < irelend; ++erel) -+ { -+ if (ELF64_R_TYPE (erel->r_info) != R_SW_64_LITUSE) -+ break; -+ if (erel->r_addend <= 6) -+ flags |= 1 << erel->r_addend; -+ } -+ -+ /* A little preparation for the loop... */ -+ disp = symval - info->gp; -+ -+ for (urel = irel + 1; urel < erel; ++urel) -+ { -+ bfd_vma urel_r_offset = urel->r_offset; -+ unsigned int insn; -+ int insn_disp; -+ bfd_signed_vma xdisp; -+ Elf_Internal_Rela nrel; -+ -+ insn = bfd_get_32 (abfd, contents + urel_r_offset); -+ -+ switch (urel->r_addend) -+ { -+ case LITUSE_SW_64_ADDR: -+ default: -+ /* This type is really just a placeholder to note that all -+ uses cannot be optimized, but to still allow some. */ -+ all_optimized = false; -+ break; -+ -+ case LITUSE_SW_64_BASE: -+ /* We may only create GPREL relocs during the second pass. */ -+ if (relax_pass == 0) -+ { -+ all_optimized = false; -+ break; -+ } -+ -+ /* We can always optimize 16-bit displacements. */ -+ -+ /* Extract the displacement from the instruction, sign-extending -+ it if necessary, then test whether it is within 16 or 32 bits -+ displacement from GP. */ -+ insn_disp = ((insn & 0xffff) ^ 0x8000) - 0x8000; -+ -+ xdisp = disp + insn_disp; -+ fits16 = (xdisp >= -(bfd_signed_vma) 0x8000 && xdisp < 0x8000); -+ fits32 -+ = (xdisp >= -(bfd_signed_vma) 0x80000000 && xdisp < 0x7fff8000); -+ -+ if (fits16) -+ { -+ /* Take the op code and dest from this insn, take the base -+ register from the literal insn. Leave the offset alone. */ -+ insn = (insn & 0xffe0ffff) | (lit_insn & 0x001f0000); -+ bfd_put_32 (abfd, (bfd_vma) insn, contents + urel_r_offset); -+ changed_contents = true; -+ -+ nrel = *urel; -+ nrel.r_info -+ = ELF64_R_INFO (ELF64_R_SYM (irel->r_info), R_SW_64_GPREL16); -+ nrel.r_addend = irel->r_addend; -+ -+ /* As we adjust, move the reloc to the end so that we don't -+ break the LITERAL+LITUSE chain. */ -+ if (urel < --erel) -+ *urel-- = *erel; -+ *erel = nrel; -+ changed_relocs = true; -+ } -+ -+ /* If all mem+byte, we can optimize 32-bit mem displacements. */ -+ else if (fits32 && !(flags & ~6)) -+ { -+ /* FIXME: sanity check that lit insn Ra is mem insn Rb. */ -+ -+ irel->r_info -+ = ELF64_R_INFO (ELF64_R_SYM (irel->r_info), R_SW_64_GPRELHIGH); -+ lit_insn = (OP_LDIH << 26) | (lit_insn & 0x03ff0000); -+ bfd_put_32 (abfd, (bfd_vma) lit_insn, contents + irel->r_offset); -+ lit_reused = true; -+ changed_contents = true; -+ -+ /* Since all relocs must be optimized, don't bother swapping -+ this relocation to the end. */ -+ urel->r_info -+ = ELF64_R_INFO (ELF64_R_SYM (irel->r_info), R_SW_64_GPRELLOW); -+ urel->r_addend = irel->r_addend; -+ changed_relocs = true; -+ } -+ else -+ all_optimized = false; -+ break; -+ -+ case LITUSE_SW_64_BYTOFF: -+ /* We can always optimize byte instructions. */ -+ -+ /* FIXME: sanity check the insn for byte op. Check that the -+ literal dest reg is indeed Rb in the byte insn. */ -+ -+ insn &= ~(unsigned) 0x001ff000; -+ insn |= ((symval & 7) << 13) | 0x1000; -+ bfd_put_32 (abfd, (bfd_vma) insn, contents + urel_r_offset); -+ changed_contents = true; -+ -+ nrel = *urel; -+ nrel.r_info = ELF64_R_INFO (0, R_SW_64_NONE); -+ nrel.r_addend = 0; -+ -+ /* As we adjust, move the reloc to the end so that we don't -+ break the LITERAL+LITUSE chain. */ -+ if (urel < --erel) -+ *urel-- = *erel; -+ *erel = nrel; -+ changed_relocs = true; -+ break; -+ -+ case LITUSE_SW_64_JSR: -+ case LITUSE_SW_64_TLSGD: -+ case LITUSE_SW_64_TLSLDM: -+ case LITUSE_SW_64_JSRDIRECT: { -+ bfd_vma optdest, org; -+ bfd_signed_vma odisp; -+ -+ /* For undefined weak symbols, we're mostly interested in getting -+ rid of the got entry whenever possible, so optimize this to a -+ use of the zero register. */ -+ if (info->h && info->h->root.root.type == bfd_link_hash_undefweak) -+ { -+ insn |= 31 << 16; -+ bfd_put_32 (abfd, (bfd_vma) insn, contents + urel_r_offset); -+ -+ changed_contents = true; -+ break; -+ } -+ -+ /* If not zero, place to jump without needing pv. */ -+ optdest = elf64_sw_64_relax_opt_call (info, symval); -+ org = sec_output_vma + urel_r_offset + 4; -+ odisp = (optdest ? optdest : symval) - org; -+ addpi_odisp = odisp; -+ if (odisp >= -0x400000 && odisp < 0x400000) -+ { -+ Elf_Internal_Rela *xrel; -+ -+ /* Preserve branch prediction call stack when possible. */ -+ if ((insn & INSN_JSR_MASK) == INSN_JSR) -+ insn = (OP_BSR << 26) | (insn & 0x03e00000); -+ else -+ insn = (OP_BR << 26) | (insn & 0x03e00000); -+ bfd_put_32 (abfd, (bfd_vma) insn, contents + urel_r_offset); -+ changed_contents = true; -+ -+ nrel = *urel; -+ nrel.r_info -+ = ELF64_R_INFO (ELF64_R_SYM (irel->r_info), R_SW_64_BRADDR); -+ nrel.r_addend = irel->r_addend; -+ -+ if (optdest) -+ nrel.r_addend += optdest - symval; -+ else -+ all_optimized = false; -+ -+ /* Kill any HINT reloc that might exist for this insn. */ -+ xrel -+ = (elf64_sw_64_find_reloc_at_ofs (info->relocs, info->relend, -+ urel_r_offset, -+ R_SW_64_HINT)); -+ if (xrel) -+ xrel->r_info = ELF64_R_INFO (0, R_SW_64_NONE); -+ -+ /* As we adjust, move the reloc to the end so that we don't -+ break the LITERAL+LITUSE chain. */ -+ if (urel < --erel) -+ *urel-- = *erel; -+ *erel = nrel; -+ -+ info->changed_relocs = true; -+ } -+ else if (odisp >= -0x2000000 && odisp < 0x2000000 -+ && (insn & INSN_JSR_MASK) == INSN_JSR -+ && info->link_info->flag_sw_lbr == 8 -+ && (urel_r_offset - irel->r_offset) < 8 && optdest -+ && ELF64_R_TYPE ((irel - 1)->r_info) == R_SW_64_LITERAL_GOT -+ && bfd_get_32 (abfd, contents + urel_r_offset + 4) -+ == 0xffba0000 -+ && bfd_get_32 (abfd, contents + urel_r_offset + 8) -+ == 0xfbbd0000) -+ { -+ Elf_Internal_Rela *xrel; -+ /* Preserve branch prediction call stack when possible. */ -+ if ((insn & INSN_JSR_MASK) == INSN_JSR) -+ insn = (0x1d << 26); -+ else -+ { -+ printf ("lbr error\n"); -+ insn = (0x1d << 26); -+ } -+ bfd_put_32 (abfd, (bfd_vma) insn, contents + urel_r_offset); -+ changed_contents = true; -+ addpi_flag = 1; -+ ldr_offset = urel_r_offset; -+ -+ nrel = *urel; -+ nrel.r_info -+ = ELF64_R_INFO (ELF64_R_SYM (irel->r_info), R_SW_64_BR26ADDR); -+ nrel.r_addend = irel->r_addend; -+ -+ if (optdest) -+ nrel.r_addend += optdest - symval; -+ else -+ all_optimized = false; -+ -+ /* Kill any HINT reloc that might exist for this insn. */ -+ xrel -+ = (elf64_sw_64_find_reloc_at_ofs (info->relocs, info->relend, -+ urel_r_offset, -+ R_SW_64_HINT)); -+ if (xrel) -+ xrel->r_info = ELF64_R_INFO (0, R_SW_64_NONE); -+ -+ /* As we adjust, move the reloc to the end so that we don't -+ break the LITERAL+LITUSE chain. */ -+ if (urel < --erel) -+ *urel-- = *erel; -+ *erel = nrel; -+ -+ info->changed_relocs = true; -+ } -+ else -+ all_optimized = false; -+ -+ /* Even if the target is not in range for a direct branch, -+ if we share a GP, we can eliminate the gp reload. */ -+ if (optdest) -+ { -+ Elf_Internal_Rela *gpdisp -+ = (elf64_sw_64_find_reloc_at_ofs (info->relocs, irelend, -+ urel_r_offset + 4, -+ R_SW_64_GPDISP)); -+ if (gpdisp) -+ { -+ bfd_byte *p_ldih = contents + gpdisp->r_offset; -+ bfd_byte *p_ldi = p_ldih + gpdisp->r_addend; -+ unsigned int ldih = bfd_get_32 (abfd, p_ldih); -+ unsigned int ldi = bfd_get_32 (abfd, p_ldi); -+ -+ /* Verify that the instruction is "ldih $29,0 ($26)". -+ Consider a function that ends in a noreturn call, -+ and that the next function begins with an ldgp, -+ and that by accident there is no padding between. -+ In that case the insn would use $27 as the base. */ -+ -+ if (ldih == 0xffba0000 && ldi == 0xfbba0000) -+ { -+ bfd_put_32 (abfd, (bfd_vma) INSN_UNOP, p_ldih); -+ bfd_put_32 (abfd, (bfd_vma) INSN_UNOP, p_ldi); -+ -+ gpdisp->r_info = ELF64_R_INFO (0, R_SW_64_NONE); -+ changed_contents = true; -+ changed_relocs = true; -+ } -+ } -+ } -+ } -+ break; -+ } -+ } -+ -+ /* If we reused the literal instruction, we must have optimized all. */ -+ BFD_ASSERT (!lit_reused || all_optimized); -+ -+ /* If all cases were optimized, we can reduce the use count on this -+ got entry by one, possibly eliminating it. */ -+ if (all_optimized) -+ { -+ if (--info->gotent->use_count == 0) -+ { -+ int sz = sw_64_got_entry_size (R_SW_64_LITERAL); -+ sw_64_elf_tdata (info->gotobj)->total_got_size -= sz; -+ if (!info->h) -+ sw_64_elf_tdata (info->gotobj)->local_got_size -= sz; -+ } -+ -+ /* If the literal instruction is no longer needed (it may have been -+ reused. We can eliminate it. */ -+ /* ??? For now, I don't want to deal with compacting the section, -+ so just nop it out. */ -+ if (!lit_reused) -+ { -+ /* this will cause sw_64/brk.S err. */ -+ if (ELF64_R_TYPE ((irel - 1)->r_info) == R_SW_64_LITERAL_GOT) -+ { -+ (irel - 1)->r_info = ELF64_R_INFO (0, R_SW_64_NONE); -+ changed_relocs = true; -+ -+ bfd_put_32 (abfd, (bfd_vma) INSN_UNOP, -+ contents + (irel - 1)->r_offset); -+ } -+ irel->r_info = ELF64_R_INFO (0, R_SW_64_NONE); -+ changed_relocs = true; -+ if (addpi_odisp >= -0x400000 && addpi_odisp < 0x400000 -+ || addpi_flag == 0) -+ bfd_put_32 (abfd, (bfd_vma) INSN_UNOP, contents + irel->r_offset); -+ else -+ { -+ addpi_flag = 0; -+ bfd_put_32 (abfd, -+ (bfd_vma) INSN_ADDPI -+ | ((ldr_offset - irel->r_offset) / 4) << 13, -+ contents + irel->r_offset); -+ } -+ changed_contents = true; -+ } -+ } -+ -+ info->changed_contents = changed_contents; -+ info->changed_relocs = changed_relocs; -+ -+ if (all_optimized || relax_pass == 0) -+ return true; -+ return elf64_sw_64_relax_got_load (info, symval, irel, R_SW_64_LITERAL); -+} -+ -+static bool -+elf64_sw_64_relax_tls_get_addr (struct sw_64_relax_info *info, bfd_vma symval, -+ Elf_Internal_Rela *irel, bool is_gd) -+{ -+ bfd_byte *pos[5]; -+ unsigned int insn, tlsgd_reg; -+ Elf_Internal_Rela *gpdisp, *hint; -+ bool dynamic, use_gottprel; -+ unsigned long new_symndx; -+ -+ dynamic = (info->h != NULL -+ && sw_64_elf_dynamic_symbol_p (&info->h->root, info->link_info)); -+ -+ /* If a TLS symbol is accessed using IE at least once, there is no point -+ to use dynamic model for it. */ -+ if (is_gd && info->h && (info->h->flags & SW_64_ELF_LINK_HASH_TLS_IE)) -+ ; -+ -+ /* If the symbol is local, and we've already committed to DF_STATIC_TLS, -+ then we might as well relax to IE. */ -+ else if (bfd_link_pic (info->link_info) && !dynamic -+ && (info->link_info->flags & DF_STATIC_TLS)) -+ ; -+ -+ /* Otherwise we must be building an executable to do anything. */ -+ else if (bfd_link_pic (info->link_info)) -+ return true; -+ -+ /* The TLSGD/TLSLDM relocation must be followed by a LITERAL and -+ the matching LITUSE_TLS relocations. */ -+ if (irel + 2 >= info->relend) -+ return true; -+ if (ELF64_R_TYPE (irel[1].r_info) != R_SW_64_LITERAL -+ || ELF64_R_TYPE (irel[2].r_info) != R_SW_64_LITUSE -+ || irel[2].r_addend != (is_gd ? LITUSE_SW_64_TLSGD : LITUSE_SW_64_TLSLDM)) -+ return true; -+ -+ /* There must be a GPDISP relocation positioned immediately after the -+ LITUSE relocation. */ -+ gpdisp = elf64_sw_64_find_reloc_at_ofs (info->relocs, info->relend, -+ irel[2].r_offset + 4, R_SW_64_GPDISP); -+ if (!gpdisp) -+ return true; -+ -+ pos[0] = info->contents + irel[0].r_offset; -+ pos[1] = info->contents + irel[1].r_offset; -+ pos[2] = info->contents + irel[2].r_offset; -+ pos[3] = info->contents + gpdisp->r_offset; -+ pos[4] = pos[3] + gpdisp->r_addend; -+ -+ /* Beware of the compiler hoisting part of the sequence out a loop -+ and adjusting the destination register for the TLSGD insn. If this -+ happens, there will be a move into $16 before the JSR insn, so only -+ transformations of the first insn pair should use this register. */ -+ tlsgd_reg = bfd_get_32 (info->abfd, pos[0]); -+ tlsgd_reg = (tlsgd_reg >> 21) & 31; -+ -+ /* Generally, the positions are not allowed to be out of order, lest the -+ modified insn sequence have different register lifetimes. We can make -+ an exception when pos 1 is adjacent to pos 0. */ -+ if (pos[1] + 4 == pos[0]) -+ { -+ bfd_byte *tmp = pos[0]; -+ pos[0] = pos[1]; -+ pos[1] = tmp; -+ } -+ if (pos[1] >= pos[2] || pos[2] >= pos[3]) -+ return true; -+ -+ /* Reduce the use count on the LITERAL relocation. Do this before we -+ smash the symndx when we adjust the relocations below. */ -+ { -+ struct sw_64_elf_got_entry *lit_gotent; -+ struct sw_64_elf_link_hash_entry *lit_h; -+ unsigned long indx; -+ -+ BFD_ASSERT (ELF64_R_SYM (irel[1].r_info) >= info->symtab_hdr->sh_info); -+ indx = ELF64_R_SYM (irel[1].r_info) - info->symtab_hdr->sh_info; -+ lit_h = sw_64_elf_sym_hashes (info->abfd)[indx]; -+ -+ while (lit_h->root.root.type == bfd_link_hash_indirect -+ || lit_h->root.root.type == bfd_link_hash_warning) -+ lit_h = (struct sw_64_elf_link_hash_entry *) lit_h->root.root.u.i.link; -+ -+ for (lit_gotent = lit_h->got_entries; lit_gotent; -+ lit_gotent = lit_gotent->next) -+ if (lit_gotent->gotobj == info->gotobj -+ && lit_gotent->reloc_type == R_SW_64_LITERAL -+ && lit_gotent->addend == irel[1].r_addend) -+ break; -+ BFD_ASSERT (lit_gotent); -+ -+ if (--lit_gotent->use_count == 0) -+ { -+ int sz = sw_64_got_entry_size (R_SW_64_LITERAL); -+ sw_64_elf_tdata (info->gotobj)->total_got_size -= sz; -+ } -+ } -+ -+ /* Change -+ -+ ldi $16,x ($gp) !tlsgd!1 -+ ldl $27,__tls_get_addr ($gp) !literal!1 -+ jsr $26, ($27),__tls_get_addr !lituse_tlsgd!1 -+ ldih $29,0 ($26) !gpdisp!2 -+ ldi $29,0 ($29) !gpdisp!2 -+ to -+ ldl $16,x ($gp) !gottprel -+ unop -+ call_pal rduniq -+ addl $16,$0,$0 -+ unop -+ or the first pair to -+ ldi $16,x ($gp) !tprel -+ unop -+ or -+ ldih $16,x ($gp) !tprelhi -+ ldi $16,x ($16) !tprello -+ -+ as appropriate. */ -+ -+ use_gottprel = false; -+ new_symndx = is_gd ? ELF64_R_SYM (irel->r_info) : STN_UNDEF; -+ -+ /* Some compilers warn about a Boolean-looking expression being -+ used in a switch. The explicit cast silences them. */ -+ switch ((int) (!dynamic && !bfd_link_pic (info->link_info))) -+ { -+ case 1: { -+ bfd_vma tp_base; -+ bfd_signed_vma disp; -+ -+ BFD_ASSERT (elf_hash_table (info->link_info)->tls_sec != NULL); -+ tp_base = sw_64_get_tprel_base (info->link_info); -+ disp = symval - tp_base; -+ -+ if (disp >= -0x8000 && disp < 0x8000) -+ { -+ insn = (OP_LDI << 26) | (tlsgd_reg << 21) | (31 << 16); -+ bfd_put_32 (info->abfd, (bfd_vma) insn, pos[0]); -+ bfd_put_32 (info->abfd, (bfd_vma) INSN_UNOP, pos[1]); -+ -+ irel[0].r_offset = pos[0] - info->contents; -+ irel[0].r_info = ELF64_R_INFO (new_symndx, R_SW_64_TPREL16); -+ irel[1].r_info = ELF64_R_INFO (0, R_SW_64_NONE); -+ break; -+ } -+ else if (disp >= -(bfd_signed_vma) 0x80000000 -+ && disp < (bfd_signed_vma) 0x7fff8000 && pos[0] + 4 == pos[1]) -+ { -+ insn = (OP_LDIH << 26) | (tlsgd_reg << 21) | (31 << 16); -+ bfd_put_32 (info->abfd, (bfd_vma) insn, pos[0]); -+ insn = (OP_LDI << 26) | (tlsgd_reg << 21) | (tlsgd_reg << 16); -+ bfd_put_32 (info->abfd, (bfd_vma) insn, pos[1]); -+ -+ irel[0].r_offset = pos[0] - info->contents; -+ irel[0].r_info = ELF64_R_INFO (new_symndx, R_SW_64_TPRELHI); -+ irel[1].r_offset = pos[1] - info->contents; -+ irel[1].r_info = ELF64_R_INFO (new_symndx, R_SW_64_TPRELLO); -+ break; -+ } -+ } -+ /* FALLTHRU */ -+ -+ default: -+ use_gottprel = true; -+ -+ insn = (OP_LDL << 26) | (tlsgd_reg << 21) | (29 << 16); -+ bfd_put_32 (info->abfd, (bfd_vma) insn, pos[0]); -+ bfd_put_32 (info->abfd, (bfd_vma) INSN_UNOP, pos[1]); -+ -+ irel[0].r_offset = pos[0] - info->contents; -+ irel[0].r_info = ELF64_R_INFO (new_symndx, R_SW_64_GOTTPREL); -+ irel[1].r_info = ELF64_R_INFO (0, R_SW_64_NONE); -+ break; -+ } -+ -+ bfd_put_32 (info->abfd, (bfd_vma) INSN_RDUNIQ, pos[2]); -+ -+ insn = INSN_ADDL | (16 << 21) | (0 << 16) | (0 << 0); -+ bfd_put_32 (info->abfd, (bfd_vma) insn, pos[3]); -+ -+ bfd_put_32 (info->abfd, (bfd_vma) INSN_UNOP, pos[4]); -+ -+ irel[2].r_info = ELF64_R_INFO (0, R_SW_64_NONE); -+ gpdisp->r_info = ELF64_R_INFO (0, R_SW_64_NONE); -+ -+ hint = elf64_sw_64_find_reloc_at_ofs (info->relocs, info->relend, -+ irel[2].r_offset, R_SW_64_HINT); -+ if (hint) -+ hint->r_info = ELF64_R_INFO (0, R_SW_64_NONE); -+ -+ info->changed_contents = true; -+ info->changed_relocs = true; -+ -+ /* Reduce the use count on the TLSGD/TLSLDM relocation. */ -+ if (--info->gotent->use_count == 0) -+ { -+ int sz = sw_64_got_entry_size (info->gotent->reloc_type); -+ sw_64_elf_tdata (info->gotobj)->total_got_size -= sz; -+ if (!info->h) -+ sw_64_elf_tdata (info->gotobj)->local_got_size -= sz; -+ } -+ -+ /* If we've switched to a GOTTPREL relocation, increment the reference -+ count on that got entry. */ -+ if (use_gottprel) -+ { -+ struct sw_64_elf_got_entry *tprel_gotent; -+ -+ for (tprel_gotent = *info->first_gotent; tprel_gotent; -+ tprel_gotent = tprel_gotent->next) -+ if (tprel_gotent->gotobj == info->gotobj -+ && tprel_gotent->reloc_type == R_SW_64_GOTTPREL -+ && tprel_gotent->addend == irel->r_addend) -+ break; -+ if (tprel_gotent) -+ tprel_gotent->use_count++; -+ else -+ { -+ if (info->gotent->use_count == 0) -+ tprel_gotent = info->gotent; -+ else -+ { -+ tprel_gotent = (struct sw_64_elf_got_entry *) -+ bfd_alloc (info->abfd, sizeof (struct sw_64_elf_got_entry)); -+ if (!tprel_gotent) -+ return false; -+ -+ tprel_gotent->next = *info->first_gotent; -+ *info->first_gotent = tprel_gotent; -+ -+ tprel_gotent->gotobj = info->gotobj; -+ tprel_gotent->addend = irel->r_addend; -+ tprel_gotent->got_offset = -1; -+ tprel_gotent->reloc_done = 0; -+ tprel_gotent->reloc_xlated = 0; -+ } -+ -+ tprel_gotent->use_count = 1; -+ tprel_gotent->reloc_type = R_SW_64_GOTTPREL; -+ } -+ } -+ -+ return true; -+} -+ -+static bool -+elf64_sw_64_relax_section (bfd *abfd, asection *sec, -+ struct bfd_link_info *link_info, bool *again) -+{ -+ Elf_Internal_Shdr *symtab_hdr; -+ Elf_Internal_Rela *internal_relocs; -+ Elf_Internal_Rela *irel, *irelend; -+ Elf_Internal_Sym *isymbuf = NULL; -+ struct sw_64_elf_got_entry **local_got_entries; -+ struct sw_64_relax_info info; -+ struct sw_64_elf_link_hash_table *htab; -+ int relax_pass; -+ -+ htab = sw_64_elf_hash_table (link_info); -+ if (htab == NULL) -+ return false; -+ -+ /* There's nothing to change, yet. */ -+ *again = false; -+ -+ if (bfd_link_relocatable (link_info) -+ || ((sec->flags & (SEC_CODE | SEC_RELOC | SEC_ALLOC | SEC_HAS_CONTENTS)) -+ != (SEC_CODE | SEC_RELOC | SEC_ALLOC | SEC_HAS_CONTENTS)) -+ || sec->reloc_count == 0) -+ return true; -+ -+ BFD_ASSERT (is_sw_64_elf (abfd)); -+ relax_pass = link_info->relax_pass; -+ -+ /* Make sure our GOT and PLT tables are up-to-date. */ -+ if (htab->relax_trip != link_info->relax_trip) -+ { -+ htab->relax_trip = link_info->relax_trip; -+ -+ /* This should never fail after the initial round, since the only error -+ is GOT overflow, and relaxation only shrinks the table. However, we -+ may only merge got sections during the first pass. If we merge -+ sections after we've created GPREL relocs, the GP for the merged -+ section backs up which may put the relocs out of range. */ -+ if (!elf64_sw_64_size_got_sections (link_info, relax_pass == 0)) -+ abort (); -+ if (elf_hash_table (link_info)->dynamic_sections_created) -+ { -+ elf64_sw_64_size_plt_section (link_info); -+ elf64_sw_64_size_rela_got_section (link_info); -+ } -+ } -+ -+ symtab_hdr = &elf_symtab_hdr (abfd); -+ local_got_entries = sw_64_elf_tdata (abfd)->local_got_entries; -+ -+ /* Load the relocations for this section. */ -+ internal_relocs -+ = (_bfd_elf_link_read_relocs (abfd, sec, NULL, (Elf_Internal_Rela *) NULL, -+ link_info->keep_memory)); -+ if (internal_relocs == NULL) -+ return false; -+ -+ memset (&info, 0, sizeof (info)); -+ info.abfd = abfd; -+ info.sec = sec; -+ info.link_info = link_info; -+ info.symtab_hdr = symtab_hdr; -+ info.relocs = internal_relocs; -+ info.relend = irelend = internal_relocs + sec->reloc_count; -+ -+ /* Find the GP for this object. Do not store the result back via -+ _bfd_set_gp_value, since this could change again before final. */ -+ info.gotobj = sw_64_elf_tdata (abfd)->gotobj; -+ if (info.gotobj) -+ { -+ asection *sgot = sw_64_elf_tdata (info.gotobj)->got; -+ info.gp = (sgot->output_section->vma + sgot->output_offset + 0x8000); -+ } -+ -+ /* Get the section contents. */ -+ if (elf_section_data (sec)->this_hdr.contents != NULL) -+ info.contents = elf_section_data (sec)->this_hdr.contents; -+ else -+ { -+ if (!bfd_malloc_and_get_section (abfd, sec, &info.contents)) -+ goto error_return; -+ } -+ -+ for (irel = internal_relocs; irel < irelend; irel++) -+ { -+ bfd_vma symval; -+ struct sw_64_elf_got_entry *gotent; -+ unsigned long r_type = ELF64_R_TYPE (irel->r_info); -+ unsigned long r_symndx = ELF64_R_SYM (irel->r_info); -+ -+ /* Early exit for unhandled or unrelaxable relocations. */ -+ if (r_type != R_SW_64_LITERAL) -+ { -+ /* We complete everything except LITERAL in the first pass. */ -+ if (relax_pass != 0) -+ continue; -+ if (r_type == R_SW_64_TLSLDM) -+ { -+ /* The symbol for a TLSLDM reloc is ignored. Collapse the -+ reloc to the STN_UNDEF (0) symbol so that they all match. */ -+ r_symndx = STN_UNDEF; -+ } -+ else if (r_type != R_SW_64_GOTDTPREL && r_type != R_SW_64_GOTTPREL -+ && r_type != R_SW_64_TLSGD) -+ continue; -+ } -+ -+ /* Get the value of the symbol referred to by the reloc. */ -+ if (r_symndx < symtab_hdr->sh_info) -+ { -+ /* A local symbol. */ -+ Elf_Internal_Sym *isym; -+ -+ /* Read this BFD's local symbols. */ -+ if (isymbuf == NULL) -+ { -+ isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents; -+ if (isymbuf == NULL) -+ isymbuf -+ = bfd_elf_get_elf_syms (abfd, symtab_hdr, symtab_hdr->sh_info, -+ 0, NULL, NULL, NULL); -+ if (isymbuf == NULL) -+ goto error_return; -+ } -+ -+ isym = isymbuf + r_symndx; -+ -+ /* Given the symbol for a TLSLDM reloc is ignored, this also -+ means forcing the symbol value to the tp base. */ -+ if (r_type == R_SW_64_TLSLDM) -+ { -+ info.tsec = bfd_abs_section_ptr; -+ symval = sw_64_get_tprel_base (info.link_info); -+ } -+ else -+ { -+ symval = isym->st_value; -+ if (isym->st_shndx == SHN_UNDEF) -+ continue; -+ else if (isym->st_shndx == SHN_ABS) -+ info.tsec = bfd_abs_section_ptr; -+ else if (isym->st_shndx == SHN_COMMON) -+ info.tsec = bfd_com_section_ptr; -+ else -+ info.tsec = bfd_section_from_elf_index (abfd, isym->st_shndx); -+ } -+ -+ info.h = NULL; -+ info.other = isym->st_other; -+ if (local_got_entries) -+ info.first_gotent = &local_got_entries[r_symndx]; -+ else -+ { -+ info.first_gotent = &info.gotent; -+ info.gotent = NULL; -+ } -+ } -+ else -+ { -+ unsigned long indx; -+ struct sw_64_elf_link_hash_entry *h; -+ -+ indx = r_symndx - symtab_hdr->sh_info; -+ h = sw_64_elf_sym_hashes (abfd)[indx]; -+ BFD_ASSERT (h != NULL); -+ -+ while (h->root.root.type == bfd_link_hash_indirect -+ || h->root.root.type == bfd_link_hash_warning) -+ h = (struct sw_64_elf_link_hash_entry *) h->root.root.u.i.link; -+ -+ /* If the symbol is undefined, we can't do anything with it. */ -+ if (h->root.root.type == bfd_link_hash_undefined) -+ continue; -+ -+ /* If the symbol isn't defined in the current module, -+ again we can't do anything. */ -+ if (h->root.root.type == bfd_link_hash_undefweak) -+ { -+ info.tsec = bfd_abs_section_ptr; -+ symval = 0; -+ } -+ else if (!h->root.def_regular) -+ { -+ /* Except for TLSGD relocs, which can sometimes be -+ relaxed to GOTTPREL relocs. */ -+ if (r_type != R_SW_64_TLSGD) -+ continue; -+ info.tsec = bfd_abs_section_ptr; -+ symval = 0; -+ } -+ else -+ { -+ info.tsec = h->root.root.u.def.section; -+ symval = h->root.root.u.def.value; -+ } -+ -+ info.h = h; -+ info.other = h->root.other; -+ info.first_gotent = &h->got_entries; -+ } -+ -+ /* Search for the got entry to be used by this relocation. */ -+ for (gotent = *info.first_gotent; gotent; gotent = gotent->next) -+ if (gotent->gotobj == info.gotobj && gotent->reloc_type == r_type -+ && gotent->addend == irel->r_addend) -+ break; -+ info.gotent = gotent; -+ -+ symval += info.tsec->output_section->vma + info.tsec->output_offset; -+ symval += irel->r_addend; -+ -+ switch (r_type) -+ { -+ case R_SW_64_LITERAL: -+ BFD_ASSERT (info.gotent != NULL); -+ -+ /* If there exist LITUSE relocations immediately following, this -+ opens up all sorts of interesting optimizations, because we -+ now know every location that this address load is used. */ -+ if (irel + 1 < irelend -+ && ELF64_R_TYPE (irel[1].r_info) == R_SW_64_LITUSE) -+ { -+ if (!elf64_sw_64_relax_with_lituse (&info, symval, irel)) -+ goto error_return; -+ } -+ else -+ { -+ if (!elf64_sw_64_relax_got_load (&info, symval, irel, r_type)) -+ goto error_return; -+ } -+ break; -+ -+ case R_SW_64_GOTDTPREL: -+ case R_SW_64_GOTTPREL: -+ BFD_ASSERT (info.gotent != NULL); -+ if (!elf64_sw_64_relax_got_load (&info, symval, irel, r_type)) -+ goto error_return; -+ break; -+ -+ case R_SW_64_TLSGD: -+ case R_SW_64_TLSLDM: -+ BFD_ASSERT (info.gotent != NULL); -+ if (!elf64_sw_64_relax_tls_get_addr (&info, symval, irel, -+ r_type == R_SW_64_TLSGD)) -+ goto error_return; -+ break; -+ } -+ } -+ -+ if (isymbuf != NULL && symtab_hdr->contents != (unsigned char *) isymbuf) -+ { -+ if (!link_info->keep_memory) -+ free (isymbuf); -+ else -+ { -+ /* Cache the symbols for elf_link_input_bfd. */ -+ symtab_hdr->contents = (unsigned char *) isymbuf; -+ } -+ } -+ -+ if (info.contents != NULL -+ && elf_section_data (sec)->this_hdr.contents != info.contents) -+ { -+ if (!info.changed_contents && !link_info->keep_memory) -+ free (info.contents); -+ else -+ { -+ /* Cache the section contents for elf_link_input_bfd. */ -+ elf_section_data (sec)->this_hdr.contents = info.contents; -+ } -+ } -+ -+ if (elf_section_data (sec)->relocs != internal_relocs) -+ { -+ if (!info.changed_relocs) -+ free (internal_relocs); -+ else -+ elf_section_data (sec)->relocs = internal_relocs; -+ } -+ -+ *again = info.changed_contents || info.changed_relocs; -+ -+ return true; -+ -+error_return: -+ if (symtab_hdr->contents != (unsigned char *) isymbuf) -+ free (isymbuf); -+ if (elf_section_data (sec)->this_hdr.contents != info.contents) -+ free (info.contents); -+ if (elf_section_data (sec)->relocs != internal_relocs) -+ free (internal_relocs); -+ return false; -+} -+ -+/* Emit a dynamic relocation for (DYNINDX, RTYPE, ADDEND) at (SEC, OFFSET) -+ into the next available slot in SREL. */ -+ -+static void -+elf64_sw_64_emit_dynrel (bfd *abfd, struct bfd_link_info *info, asection *sec, -+ asection *srel, bfd_vma offset, long dynindx, -+ long rtype, bfd_vma addend) -+{ -+ Elf_Internal_Rela outrel; -+ bfd_byte *loc; -+ -+ BFD_ASSERT (srel != NULL); -+ -+ outrel.r_info = ELF64_R_INFO (dynindx, rtype); -+ outrel.r_addend = addend; -+ -+ offset = _bfd_elf_section_offset (abfd, info, sec, offset); -+ if ((offset | 1) != (bfd_vma) -1) -+ outrel.r_offset = sec->output_section->vma + sec->output_offset + offset; -+ else -+ memset (&outrel, 0, sizeof (outrel)); -+ -+ loc = srel->contents; -+ loc += srel->reloc_count++ * sizeof (Elf64_External_Rela); -+ bfd_elf64_swap_reloca_out (abfd, &outrel, loc); -+ BFD_ASSERT (sizeof (Elf64_External_Rela) * srel->reloc_count <= srel->size); -+} -+ -+/* Relocate an Sw_64 ELF section for a relocatable link. -+ -+ We don't have to change anything unless the reloc is against a section -+ symbol, in which case we have to adjust according to where the section -+ symbol winds up in the output section. */ -+ -+static bool -+elf64_sw_64_relocate_section_r (bfd *output_bfd ATTRIBUTE_UNUSED, -+ struct bfd_link_info *info ATTRIBUTE_UNUSED, -+ bfd *input_bfd, asection *input_section, -+ bfd_byte *contents ATTRIBUTE_UNUSED, -+ Elf_Internal_Rela *relocs, -+ Elf_Internal_Sym *local_syms, -+ asection **local_sections) -+{ -+ unsigned long symtab_hdr_sh_info; -+ Elf_Internal_Rela *rel; -+ Elf_Internal_Rela *relend; -+ struct elf_link_hash_entry **sym_hashes; -+ bool ret_val = true; -+ -+ symtab_hdr_sh_info = elf_symtab_hdr (input_bfd).sh_info; -+ sym_hashes = elf_sym_hashes (input_bfd); -+ -+ relend = relocs + input_section->reloc_count; -+ for (rel = relocs; rel < relend; rel++) -+ { -+ unsigned long r_symndx; -+ Elf_Internal_Sym *sym; -+ asection *sec; -+ unsigned long r_type; -+ -+ r_type = ELF64_R_TYPE (rel->r_info); -+ if (r_type >= R_SW_64_max) -+ { -+ _bfd_error_handler -+ /* xgettext:c-format */ -+ (_ ("%pB: unsupported relocation type %#x"), input_bfd, -+ (int) r_type); -+ bfd_set_error (bfd_error_bad_value); -+ ret_val = false; -+ continue; -+ } -+ -+ /* The symbol associated with GPDISP and LITUSE is -+ immaterial. Only the addend is significant. */ -+ if (r_type == R_SW_64_GPDISP || r_type == R_SW_64_LITUSE) -+ continue; -+ -+ r_symndx = ELF64_R_SYM (rel->r_info); -+ if (r_symndx < symtab_hdr_sh_info) -+ { -+ sym = local_syms + r_symndx; -+ sec = local_sections[r_symndx]; -+ } -+ else -+ { -+ struct elf_link_hash_entry *h; -+ -+ h = sym_hashes[r_symndx - symtab_hdr_sh_info]; -+ -+ while (h->root.type == bfd_link_hash_indirect -+ || h->root.type == bfd_link_hash_warning) -+ h = (struct elf_link_hash_entry *) h->root.u.i.link; -+ -+ if (h->root.type != bfd_link_hash_defined -+ && h->root.type != bfd_link_hash_defweak) -+ continue; -+ -+ sym = NULL; -+ sec = h->root.u.def.section; -+ } -+ -+ if (sec != NULL && discarded_section (sec)) -+ RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section, rel, 1, -+ relend, -+ elf64_sw_64_howto_table + r_type, 0, -+ contents); -+ -+ if (sym != NULL && ELF_ST_TYPE (sym->st_info) == STT_SECTION) -+ rel->r_addend += sec->output_offset; -+ } -+ -+ return ret_val; -+} -+ -+/* Relocate an Sw_64 ELF section. */ -+ -+static bool -+elf64_sw_64_relocate_section (bfd *output_bfd, struct bfd_link_info *info, -+ bfd *input_bfd, asection *input_section, -+ bfd_byte *contents, Elf_Internal_Rela *relocs, -+ Elf_Internal_Sym *local_syms, -+ asection **local_sections) -+{ -+ Elf_Internal_Shdr *symtab_hdr; -+ Elf_Internal_Rela *rel; -+ Elf_Internal_Rela *relend; -+ asection *sgot, *srel, *srelgot; -+ bfd *dynobj, *gotobj; -+ bfd_vma gp, tp_base, dtp_base; -+ struct sw_64_elf_got_entry **local_got_entries; -+ bool ret_val; -+ -+ BFD_ASSERT (is_sw_64_elf (input_bfd)); -+ -+ /* Handle relocatable links with a smaller loop. */ -+ if (bfd_link_relocatable (info)) -+ return elf64_sw_64_relocate_section_r (output_bfd, info, input_bfd, -+ input_section, contents, relocs, -+ local_syms, local_sections); -+ -+ /* This is a final link. */ -+ -+ ret_val = true; -+ -+ symtab_hdr = &elf_symtab_hdr (input_bfd); -+ -+ dynobj = elf_hash_table (info)->dynobj; -+ srelgot = elf_hash_table (info)->srelgot; -+ -+ if (input_section->flags & SEC_ALLOC) -+ { -+ const char *section_name; -+ section_name = (bfd_elf_string_from_elf_section ( -+ input_bfd, elf_elfheader (input_bfd)->e_shstrndx, -+ _bfd_elf_single_rel_hdr (input_section)->sh_name)); -+ BFD_ASSERT (section_name != NULL); -+ srel = bfd_get_linker_section (dynobj, section_name); -+ } -+ else -+ srel = NULL; -+ -+ /* Find the gp value for this input bfd. */ -+ gotobj = sw_64_elf_tdata (input_bfd)->gotobj; -+ if (gotobj) -+ { -+ sgot = sw_64_elf_tdata (gotobj)->got; -+ gp = _bfd_get_gp_value (gotobj); -+ if (gp == 0) -+ { -+ gp = (sgot->output_section->vma + sgot->output_offset + 0x8000); -+ _bfd_set_gp_value (gotobj, gp); -+ } -+ } -+ else -+ { -+ sgot = NULL; -+ gp = 0; -+ } -+ -+ local_got_entries = sw_64_elf_tdata (input_bfd)->local_got_entries; -+ -+ if (elf_hash_table (info)->tls_sec != NULL) -+ { -+ dtp_base = sw_64_get_dtprel_base (info); -+ tp_base = sw_64_get_tprel_base (info); -+ } -+ else -+ dtp_base = tp_base = 0; -+ -+ relend = relocs + input_section->reloc_count; -+ for (rel = relocs; rel < relend; rel++) -+ { -+ struct sw_64_elf_link_hash_entry *h = NULL; -+ struct sw_64_elf_got_entry *gotent; -+ bfd_reloc_status_type r; -+ reloc_howto_type *howto; -+ unsigned long r_symndx; -+ Elf_Internal_Sym *sym = NULL; -+ asection *sec = NULL; -+ bfd_vma value; -+ bfd_vma addend; -+ bool dynamic_symbol_p; -+ bool unresolved_reloc = false; -+ bool undef_weak_ref = false; -+ unsigned long r_type; -+ -+ r_type = ELF64_R_TYPE (rel->r_info); -+ if (r_type >= R_SW_64_max) -+ { -+ _bfd_error_handler -+ /* xgettext:c-format */ -+ (_ ("%pB: unsupported relocation type %#x"), input_bfd, -+ (int) r_type); -+ bfd_set_error (bfd_error_bad_value); -+ ret_val = false; -+ continue; -+ } -+ -+ howto = elf64_sw_64_howto_table + r_type; -+ r_symndx = ELF64_R_SYM (rel->r_info); -+ -+ /* The symbol for a TLSLDM reloc is ignored. Collapse the -+ reloc to the STN_UNDEF (0) symbol so that they all match. */ -+ if (r_type == R_SW_64_TLSLDM) -+ r_symndx = STN_UNDEF; -+ -+ if (r_symndx < symtab_hdr->sh_info) -+ { -+ asection *msec; -+ sym = local_syms + r_symndx; -+ sec = local_sections[r_symndx]; -+ msec = sec; -+ value = _bfd_elf_rela_local_sym (output_bfd, sym, &msec, rel); -+ -+ /* If this is a tp-relative relocation against sym STN_UNDEF (0), -+ this is hackery from relax_section. Force the value to -+ be the tls module base. */ -+ if (r_symndx == STN_UNDEF -+ && (r_type == R_SW_64_TLSLDM || r_type == R_SW_64_GOTTPREL -+ || r_type == R_SW_64_TPREL64 || r_type == R_SW_64_TPRELHI -+ || r_type == R_SW_64_TPRELLO || r_type == R_SW_64_TPREL16)) -+ value = dtp_base; -+ -+ if (local_got_entries) -+ gotent = local_got_entries[r_symndx]; -+ else -+ gotent = NULL; -+ -+ /* Need to adjust local GOT entries' addends for SEC_MERGE -+ unless it has been done already. */ -+ if ((sec->flags & SEC_MERGE) -+ && ELF_ST_TYPE (sym->st_info) == STT_SECTION -+ && sec->sec_info_type == SEC_INFO_TYPE_MERGE && gotent -+ && !gotent->reloc_xlated) -+ { -+ struct sw_64_elf_got_entry *ent; -+ -+ for (ent = gotent; ent; ent = ent->next) -+ { -+ ent->reloc_xlated = 1; -+ if (ent->use_count == 0) -+ continue; -+ msec = sec; -+ ent->addend = _bfd_merged_section_offset ( -+ output_bfd, &msec, elf_section_data (sec)->sec_info, -+ sym->st_value + ent->addend); -+ ent->addend -= sym->st_value; -+ ent->addend += msec->output_section->vma + msec->output_offset -+ - sec->output_section->vma -+ - sec->output_offset; -+ } -+ } -+ -+ dynamic_symbol_p = false; -+ } -+ else -+ { -+ bool warned, ignored; -+ struct elf_link_hash_entry *hh; -+ struct elf_link_hash_entry **sym_hashes = elf_sym_hashes (input_bfd); -+ -+ RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, -+ r_symndx, symtab_hdr, sym_hashes, hh, sec, -+ value, unresolved_reloc, warned, ignored); -+ -+ if (warned) -+ continue; -+ -+ if (value == 0 && !unresolved_reloc -+ && hh->root.type == bfd_link_hash_undefweak) -+ undef_weak_ref = true; -+ -+ h = (struct sw_64_elf_link_hash_entry *) hh; -+ dynamic_symbol_p = sw_64_elf_dynamic_symbol_p (&h->root, info); -+ gotent = h->got_entries; -+ } -+ -+ if (sec != NULL && discarded_section (sec)) -+ RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section, rel, 1, -+ relend, howto, 0, contents); -+ -+ addend = rel->r_addend; -+ value += addend; -+ -+ /* Search for the proper got entry. */ -+ for (; gotent; gotent = gotent->next) -+ if (gotent->gotobj == gotobj && gotent->reloc_type == r_type -+ && gotent->addend == addend) -+ break; -+ -+ switch (r_type) -+ { -+ case R_SW_64_GPDISP: { -+ bfd_byte *p_ldih, *p_ldi; -+ -+ BFD_ASSERT (gp != 0); -+ -+ value = (input_section->output_section->vma -+ + input_section->output_offset + rel->r_offset); -+ -+ p_ldih = contents + rel->r_offset; -+ p_ldi = p_ldih + rel->r_addend; -+ -+ r = elf64_sw_64_do_reloc_gpdisp (input_bfd, gp - value, p_ldih, -+ p_ldi); -+ } -+ break; -+ -+ case R_SW_64_LITERAL: -+ BFD_ASSERT (sgot != NULL); -+ BFD_ASSERT (gp != 0); -+ BFD_ASSERT (gotent != NULL); -+ BFD_ASSERT (gotent->use_count >= 1); -+ -+ if (!gotent->reloc_done) -+ { -+ gotent->reloc_done = 1; -+ -+ bfd_put_64 (output_bfd, value, -+ sgot->contents + gotent->got_offset); -+ -+ /* If the symbol has been forced local, output a -+ RELATIVE reloc, otherwise it will be handled in -+ finish_dynamic_symbol. */ -+ if (bfd_link_pic (info) && !dynamic_symbol_p && !undef_weak_ref) -+ elf64_sw_64_emit_dynrel (output_bfd, info, sgot, srelgot, -+ gotent->got_offset, 0, -+ R_SW_64_RELATIVE, value); -+ } -+ -+ value = (sgot->output_section->vma + sgot->output_offset -+ + gotent->got_offset); -+ Elf_Internal_Rela *rel_got; -+ rel_got = rel - 1; -+ if ((ELF64_R_TYPE (rel_got->r_info) == R_SW_64_LITERAL_GOT)) -+ { -+ value -= gp; -+ -+ /* emit the ldih $29, got_disp ($29). */ -+ bfd_byte *p_ldih; -+ p_ldih = contents + rel_got->r_offset; -+ bfd_vma got_disp; -+ bfd_vma got_low; -+ bfd_vma got_tmp; -+ unsigned long i_ldih; -+ i_ldih = bfd_get_32 (input_bfd, p_ldih); -+ got_disp = ((i_ldih & 0xffff) << 16); -+ got_disp = (got_disp ^ 0x80008000) - 0x80008000; -+ -+ if ((int) value >= 0x8000 || (int) value < -0x8000) -+ { -+ got_low = (short) value; -+ got_tmp = value - got_low; -+ got_disp = got_disp + got_tmp; -+ value = (bfd_vma) got_low; -+ } -+ i_ldih -+ = ((i_ldih & 0xffff0000) -+ | (((got_disp >> 16) + ((got_disp >> 15) & 1)) & 0xffff)); -+ bfd_put_32 (input_bfd, (bfd_vma) i_ldih, p_ldih); -+ -+ // emit ldl $27,disp ($27) -+ goto default_reloc; -+ } -+ else -+ { -+ value -= gp; -+ goto default_reloc; -+ } -+ -+ case R_SW_64_GPREL32: -+ case R_SW_64_GPREL16: -+ case R_SW_64_GPRELLOW: -+ if (dynamic_symbol_p) -+ { -+ _bfd_error_handler -+ /* xgettext:c-format */ -+ (_ ("%pB: gp-relative relocation against dynamic symbol %s"), -+ input_bfd, h->root.root.root.string); -+ ret_val = false; -+ } -+ BFD_ASSERT (gp != 0); -+ value -= gp; -+ goto default_reloc; -+ -+ case R_SW_64_GPRELHIGH: -+ if (dynamic_symbol_p) -+ { -+ _bfd_error_handler -+ /* xgettext:c-format */ -+ (_ ("%pB: gp-relative relocation against dynamic symbol %s"), -+ input_bfd, h->root.root.root.string); -+ ret_val = false; -+ } -+ BFD_ASSERT (gp != 0); -+ value -= gp; -+ value = ((bfd_signed_vma) value >> 16) + ((value >> 15) & 1); -+ goto default_reloc; -+ -+ case R_SW_64_HINT: -+ /* A call to a dynamic symbol is definitely out of range of -+ the 16-bit displacement. Don't bother writing anything. */ -+ if (dynamic_symbol_p) -+ { -+ r = bfd_reloc_ok; -+ break; -+ } -+ /* The regular PC-relative stuff measures from the start of -+ the instruction rather than the end. */ -+ value -= 4; -+ goto default_reloc; -+ -+ case R_SW_64_BRADDR: -+ if (dynamic_symbol_p) -+ { -+ _bfd_error_handler -+ /* xgettext:c-format */ -+ (_ ("%pB: pc-relative relocation against dynamic symbol %s"), -+ input_bfd, h->root.root.root.string); -+ ret_val = false; -+ } -+ /* The regular PC-relative stuff measures from the start of -+ the instruction rather than the end. */ -+ value -= 4; -+ goto default_reloc; -+ -+ case R_SW_64_BR26ADDR: -+ if (dynamic_symbol_p) -+ { -+ _bfd_error_handler -+ /* xgettext:c-format */ -+ (_ ("%pB: pc-relative relocation against dynamic symbol %s"), -+ input_bfd, h->root.root.root.string); -+ ret_val = false; -+ } -+ /* The regular PC-relative stuff measures from the start of -+ the instruction rather than the end. */ -+ value -= 4; -+ goto default_reloc; -+ -+ case R_SW_64_BRSGP: { -+ int other; -+ const char *name; -+ -+ /* The regular PC-relative stuff measures from the start of -+ the instruction rather than the end. */ -+ value -= 4; -+ -+ /* The source and destination gp must be the same. Note that -+ the source will always have an assigned gp, since we forced -+ one in check_relocs, but that the destination may not, as -+ it might not have had any relocations at all. Also take -+ care not to crash if H is an undefined symbol. */ -+ if (h != NULL && sec != NULL && sw_64_elf_tdata (sec->owner)->gotobj -+ && gotobj != sw_64_elf_tdata (sec->owner)->gotobj) -+ { -+ _bfd_error_handler -+ /* xgettext:c-format */ -+ (_ ("%pB: change in gp: BRSGP %s"), input_bfd, -+ h->root.root.root.string); -+ ret_val = false; -+ } -+ -+ /* The symbol should be marked either NOPV or STD_GPLOAD. */ -+ if (h != NULL) -+ other = h->root.other; -+ else -+ other = sym->st_other; -+ switch (other & STO_SW_64_STD_GPLOAD) -+ { -+ case STO_SW_64_NOPV: -+ break; -+ case STO_SW_64_STD_GPLOAD: -+ value += 8; -+ break; -+ default: -+ if (h != NULL) -+ name = h->root.root.root.string; -+ else -+ { -+ name -+ = (bfd_elf_string_from_elf_section (input_bfd, -+ symtab_hdr->sh_link, -+ sym->st_name)); -+ if (name == NULL) -+ name = _ (""); -+ else if (name[0] == 0) -+ name = bfd_section_name (sec); -+ } -+ _bfd_error_handler -+ /* xgettext:c-format */ -+ (_ ( -+ "%pB: !samegp reloc against symbol without .prologue: %s"), -+ input_bfd, name); -+ ret_val = false; -+ break; -+ } -+ -+ goto default_reloc; -+ } -+ -+ case R_SW_64_REFLONG: -+ case R_SW_64_REFQUAD: -+ case R_SW_64_DTPREL64: -+ case R_SW_64_TPREL64: { -+ long dynindx, dyntype = r_type; -+ bfd_vma dynaddend; -+ -+ /* Careful here to remember RELATIVE relocations for global -+ variables for symbolic shared objects. */ -+ -+ if (dynamic_symbol_p) -+ { -+ BFD_ASSERT (h->root.dynindx != -1); -+ dynindx = h->root.dynindx; -+ dynaddend = addend; -+ addend = 0, value = 0; -+ } -+ else if (r_type == R_SW_64_DTPREL64) -+ { -+ BFD_ASSERT (elf_hash_table (info)->tls_sec != NULL); -+ value -= dtp_base; -+ goto default_reloc; -+ } -+ else if (r_type == R_SW_64_TPREL64) -+ { -+ BFD_ASSERT (elf_hash_table (info)->tls_sec != NULL); -+ if (!bfd_link_dll (info)) -+ { -+ value -= tp_base; -+ goto default_reloc; -+ } -+ dynindx = 0; -+ dynaddend = value - dtp_base; -+ } -+ else if (bfd_link_pic (info) && r_symndx != STN_UNDEF -+ && (input_section->flags & SEC_ALLOC) && !undef_weak_ref -+ && !(unresolved_reloc -+ && (_bfd_elf_section_offset ( -+ output_bfd, info, input_section, rel->r_offset) -+ == (bfd_vma) -1))) -+ { -+ if (r_type == R_SW_64_REFLONG) -+ { -+ _bfd_error_handler -+ /* xgettext:c-format */ -+ (_ ("%pB: unhandled dynamic relocation against %s"), -+ input_bfd, h->root.root.root.string); -+ ret_val = false; -+ } -+ dynindx = 0; -+ dyntype = R_SW_64_RELATIVE; -+ dynaddend = value; -+ } -+ else -+ goto default_reloc; -+ -+ if (input_section->flags & SEC_ALLOC) -+ elf64_sw_64_emit_dynrel (output_bfd, info, input_section, srel, -+ rel->r_offset, dynindx, dyntype, -+ dynaddend); -+ } -+ goto default_reloc; -+ -+ case R_SW_64_SREL16: -+ case R_SW_64_SREL32: -+ case R_SW_64_SREL64: -+ if (dynamic_symbol_p) -+ { -+ _bfd_error_handler -+ /* xgettext:c-format */ -+ (_ ("%pB: pc-relative relocation against dynamic symbol %s"), -+ input_bfd, h->root.root.root.string); -+ ret_val = false; -+ } -+ else if (bfd_link_pic (info) && undef_weak_ref) -+ { -+ _bfd_error_handler -+ /* xgettext:c-format */ -+ (_ ("%pB: pc-relative relocation against undefined weak symbol " -+ "%s"), -+ input_bfd, h->root.root.root.string); -+ ret_val = false; -+ } -+ -+ /* ??? .eh_frame references to discarded sections will be smashed -+ to relocations against SHN_UNDEF. The .eh_frame format allows -+ NULL to be encoded as 0 in any format, so this works here. */ -+ if (r_symndx == STN_UNDEF -+ || (unresolved_reloc -+ && _bfd_elf_section_offset (output_bfd, info, input_section, -+ rel->r_offset) -+ == (bfd_vma) -1)) -+ howto = (elf64_sw_64_howto_table -+ + (r_type - R_SW_64_SREL32 + R_SW_64_REFLONG)); -+ goto default_reloc; -+ -+ case R_SW_64_TLSLDM: -+ /* Ignore the symbol for the relocation. The result is always -+ the current module. */ -+ dynamic_symbol_p = 0; -+ /* FALLTHRU */ -+ -+ case R_SW_64_TLSGD: -+ if (!gotent->reloc_done) -+ { -+ gotent->reloc_done = 1; -+ -+ /* Note that the module index for the main program is 1. */ -+ bfd_put_64 (output_bfd, !bfd_link_pic (info) && !dynamic_symbol_p, -+ sgot->contents + gotent->got_offset); -+ -+ /* If the symbol has been forced local, output a -+ DTPMOD64 reloc, otherwise it will be handled in -+ finish_dynamic_symbol. */ -+ if (bfd_link_pic (info) && !dynamic_symbol_p) -+ elf64_sw_64_emit_dynrel (output_bfd, info, sgot, srelgot, -+ gotent->got_offset, 0, -+ R_SW_64_DTPMOD64, 0); -+ -+ if (dynamic_symbol_p || r_type == R_SW_64_TLSLDM) -+ value = 0; -+ else -+ { -+ BFD_ASSERT (elf_hash_table (info)->tls_sec != NULL); -+ value -= dtp_base; -+ } -+ bfd_put_64 (output_bfd, value, -+ sgot->contents + gotent->got_offset + 8); -+ } -+ -+ value = (sgot->output_section->vma + sgot->output_offset -+ + gotent->got_offset); -+ rel_got = rel - 1; -+ if ((ELF64_R_TYPE (rel_got->r_info) == R_SW_64_TLSREL_GOT)) -+ { -+ value -= gp; -+ /* emit the ldih $29, got_disp ($29). */ -+ bfd_byte *p_ldih; -+ p_ldih = contents + rel_got->r_offset; -+ bfd_vma got_disp; -+ bfd_vma got_low; -+ bfd_vma got_tmp; -+ unsigned long i_ldih; -+ i_ldih = bfd_get_32 (input_bfd, p_ldih); -+ got_disp = ((i_ldih & 0xffff) << 16); -+ got_disp = (got_disp ^ 0x80008000) - 0x80008000; -+ -+ if ((int) value >= 0x8000 || (int) value < -0x8000) -+ { -+ got_low = (short) value; -+ got_tmp = value - got_low; -+ got_disp = got_disp + got_tmp; -+ value = (bfd_vma) got_low; -+ } -+ i_ldih -+ = ((i_ldih & 0xffff0000) -+ | (((got_disp >> 16) + ((got_disp >> 15) & 1)) & 0xffff)); -+ bfd_put_32 (input_bfd, (bfd_vma) i_ldih, p_ldih); -+ -+ // emit ldl $27,disp ($27) -+ goto default_reloc; -+ } -+ else -+ { -+ value -= gp; -+ goto default_reloc; -+ } -+ -+ case R_SW_64_DTPRELHI: -+ case R_SW_64_DTPRELLO: -+ case R_SW_64_DTPREL16: -+ if (dynamic_symbol_p) -+ { -+ _bfd_error_handler -+ /* xgettext:c-format */ -+ (_ ("%pB: dtp-relative relocation against dynamic symbol %s"), -+ input_bfd, h->root.root.root.string); -+ ret_val = false; -+ } -+ BFD_ASSERT (elf_hash_table (info)->tls_sec != NULL); -+ value -= dtp_base; -+ if (r_type == R_SW_64_DTPRELHI) -+ value = ((bfd_signed_vma) value >> 16) + ((value >> 15) & 1); -+ goto default_reloc; -+ -+ case R_SW_64_TPRELHI: -+ case R_SW_64_TPRELLO: -+ case R_SW_64_TPREL16: -+ if (bfd_link_dll (info)) -+ { -+ _bfd_error_handler -+ /* xgettext:c-format */ -+ (_ ("%pB: TLS local exec code cannot be linked into shared " -+ "objects"), -+ input_bfd); -+ ret_val = false; -+ } -+ else if (dynamic_symbol_p) -+ { -+ _bfd_error_handler -+ /* xgettext:c-format */ -+ (_ ("%pB: tp-relative relocation against dynamic symbol %s"), -+ input_bfd, h->root.root.root.string); -+ ret_val = false; -+ } -+ BFD_ASSERT (elf_hash_table (info)->tls_sec != NULL); -+ value -= tp_base; -+ if (r_type == R_SW_64_TPRELHI) -+ value = ((bfd_signed_vma) value >> 16) + ((value >> 15) & 1); -+ goto default_reloc; -+ -+ case R_SW_64_GOTDTPREL: -+ case R_SW_64_GOTTPREL: -+ BFD_ASSERT (sgot != NULL); -+ BFD_ASSERT (gp != 0); -+ BFD_ASSERT (gotent != NULL); -+ BFD_ASSERT (gotent->use_count >= 1); -+ -+ if (!gotent->reloc_done) -+ { -+ gotent->reloc_done = 1; -+ -+ if (dynamic_symbol_p) -+ value = 0; -+ else -+ { -+ BFD_ASSERT (elf_hash_table (info)->tls_sec != NULL); -+ if (r_type == R_SW_64_GOTDTPREL) -+ value -= dtp_base; -+ else if (bfd_link_executable (info)) -+ value -= tp_base; -+ else -+ { -+ elf64_sw_64_emit_dynrel (output_bfd, info, sgot, srelgot, -+ gotent->got_offset, 0, -+ R_SW_64_TPREL64, -+ value - dtp_base); -+ value = 0; -+ } -+ } -+ bfd_put_64 (output_bfd, value, -+ sgot->contents + gotent->got_offset); -+ } -+ -+ value = (sgot->output_section->vma + sgot->output_offset -+ + gotent->got_offset); -+ rel_got = rel - 1; -+ if ((ELF64_R_TYPE (rel_got->r_info) == R_SW_64_TLSREL_GOT)) -+ { -+ value -= gp; -+ /* emit the ldih $29, got_disp ($29). */ -+ bfd_byte *p_ldih; -+ p_ldih = contents + rel_got->r_offset; -+ bfd_vma got_disp; -+ bfd_vma got_low; -+ bfd_vma got_tmp; -+ unsigned long i_ldih; -+ i_ldih = bfd_get_32 (input_bfd, p_ldih); -+ got_disp = ((i_ldih & 0xffff) << 16); -+ got_disp = (got_disp ^ 0x80008000) - 0x80008000; -+ -+ if ((int) value >= 0x8000 || (int) value < -0x8000) -+ { -+ got_low = (short) value; -+ got_tmp = value - got_low; -+ got_disp = got_disp + got_tmp; -+ value = (bfd_vma) got_low; -+ } -+ i_ldih -+ = ((i_ldih & 0xffff0000) -+ | (((got_disp >> 16) + ((got_disp >> 15) & 1)) & 0xffff)); -+ bfd_put_32 (input_bfd, (bfd_vma) i_ldih, p_ldih); -+ -+ // emit ldl $27,disp ($27) -+ goto default_reloc; -+ } -+ else -+ { -+ value -= gp; -+ goto default_reloc; -+ } -+ -+ case R_SW_64_TLSREL_GOT: -+ r = bfd_reloc_ok; -+ break; -+ -+ case R_SW_64_LITERAL_GOT: -+ r = bfd_reloc_ok; -+ break; -+ -+ default: -+ default_reloc: -+ r = _bfd_final_link_relocate (howto, input_bfd, input_section, -+ contents, rel->r_offset, value, 0); -+ break; -+ } -+ -+ switch (r) -+ { -+ case bfd_reloc_ok: -+ break; -+ -+ case bfd_reloc_overflow: { -+ const char *name; -+ -+ /* Don't warn if the overflow is due to pc relative reloc -+ against discarded section. Section optimization code should -+ handle it. */ -+ -+ if (r_symndx < symtab_hdr->sh_info && sec != NULL -+ && howto->pc_relative && discarded_section (sec)) -+ break; -+ -+ if (h != NULL) -+ name = NULL; -+ else -+ { -+ name = (bfd_elf_string_from_elf_section (input_bfd, -+ symtab_hdr->sh_link, -+ sym->st_name)); -+ if (name == NULL) -+ return false; -+ if (*name == '\0') -+ name = bfd_section_name (sec); -+ } -+ (*info->callbacks->reloc_overflow) (info, -+ (h ? &h->root.root : NULL), -+ name, howto->name, (bfd_vma) 0, -+ input_bfd, input_section, -+ rel->r_offset); -+ } -+ break; -+ -+ default: -+ case bfd_reloc_outofrange: -+ abort (); -+ } -+ } -+ -+ return ret_val; -+} -+ -+/* Finish up dynamic symbol handling. We set the contents of various -+ dynamic sections here. */ -+ -+static bool -+elf64_sw_64_finish_dynamic_symbol (bfd *output_bfd, struct bfd_link_info *info, -+ struct elf_link_hash_entry *h, -+ Elf_Internal_Sym *sym) -+{ -+ struct sw_64_elf_link_hash_entry *ah = (struct sw_64_elf_link_hash_entry *) h; -+ -+ if (h->needs_plt) -+ { -+ /* Fill in the .plt entry for this symbol. */ -+ asection *splt, *sgot, *srel; -+ Elf_Internal_Rela outrel; -+ bfd_byte *loc; -+ bfd_vma got_addr, plt_addr; -+ bfd_vma plt_index; -+ struct sw_64_elf_got_entry *gotent; -+ -+ BFD_ASSERT (h->dynindx != -1); -+ -+ splt = elf_hash_table (info)->splt; -+ BFD_ASSERT (splt != NULL); -+ srel = elf_hash_table (info)->srelplt; -+ BFD_ASSERT (srel != NULL); -+ -+ for (gotent = ah->got_entries; gotent; gotent = gotent->next) -+ if (gotent->reloc_type == R_SW_64_LITERAL && gotent->use_count > 0) -+ { -+ unsigned int insn; -+ int disp; -+ -+ sgot = sw_64_elf_tdata (gotent->gotobj)->got; -+ BFD_ASSERT (sgot != NULL); -+ -+ BFD_ASSERT (gotent->got_offset != -1); -+ BFD_ASSERT (gotent->plt_offset != -1); -+ -+ got_addr = (sgot->output_section->vma + sgot->output_offset -+ + gotent->got_offset); -+ plt_addr = (splt->output_section->vma + splt->output_offset -+ + gotent->plt_offset); -+ -+ plt_index = (gotent->plt_offset - PLT_HEADER_SIZE) / PLT_ENTRY_SIZE; -+ -+ /* Fill in the entry in the procedure linkage table. */ -+ if (elf64_sw_64_use_secureplt) -+ { -+ disp = (PLT_HEADER_SIZE - 4) - (gotent->plt_offset + 4); -+ insn = INSN_AD (INSN_BR, 31, disp); -+ bfd_put_32 (output_bfd, insn, -+ splt->contents + gotent->plt_offset); -+ -+ plt_index = ((gotent->plt_offset - NEW_PLT_HEADER_SIZE) -+ / NEW_PLT_ENTRY_SIZE); -+ } -+ else -+ { -+ disp = -(gotent->plt_offset + 4); -+ insn = INSN_AD (INSN_BR, 28, disp); -+ bfd_put_32 (output_bfd, insn, -+ splt->contents + gotent->plt_offset); -+ bfd_put_32 (output_bfd, INSN_UNOP, -+ splt->contents + gotent->plt_offset + 4); -+ bfd_put_32 (output_bfd, INSN_UNOP, -+ splt->contents + gotent->plt_offset + 8); -+ -+ plt_index = ((gotent->plt_offset - OLD_PLT_HEADER_SIZE) -+ / OLD_PLT_ENTRY_SIZE); -+ } -+ -+ /* Fill in the entry in the .rela.plt section. */ -+ outrel.r_offset = got_addr; -+ outrel.r_info = ELF64_R_INFO (h->dynindx, R_SW_64_JMP_SLOT); -+ outrel.r_addend = 0; -+ -+ loc = srel->contents + plt_index * sizeof (Elf64_External_Rela); -+ bfd_elf64_swap_reloca_out (output_bfd, &outrel, loc); -+ -+ /* Fill in the entry in the .got. */ -+ bfd_put_64 (output_bfd, plt_addr, -+ sgot->contents + gotent->got_offset); -+ } -+ } -+ else if (sw_64_elf_dynamic_symbol_p (h, info)) -+ { -+ /* Fill in the dynamic relocations for this symbol's .got entries. */ -+ asection *srel; -+ struct sw_64_elf_got_entry *gotent; -+ -+ srel = elf_hash_table (info)->srelgot; -+ BFD_ASSERT (srel != NULL); -+ -+ for (gotent = ((struct sw_64_elf_link_hash_entry *) h)->got_entries; -+ gotent != NULL; gotent = gotent->next) -+ { -+ asection *sgot; -+ long r_type; -+ -+ if (gotent->use_count == 0) -+ continue; -+ -+ sgot = sw_64_elf_tdata (gotent->gotobj)->got; -+ -+ r_type = gotent->reloc_type; -+ switch (r_type) -+ { -+ case R_SW_64_LITERAL: -+ r_type = R_SW_64_GLOB_DAT; -+ break; -+ case R_SW_64_TLSGD: -+ r_type = R_SW_64_DTPMOD64; -+ break; -+ case R_SW_64_GOTDTPREL: -+ r_type = R_SW_64_DTPREL64; -+ break; -+ case R_SW_64_GOTTPREL: -+ r_type = R_SW_64_TPREL64; -+ break; -+ case R_SW_64_TLSLDM: -+ default: -+ abort (); -+ } -+ -+ elf64_sw_64_emit_dynrel (output_bfd, info, sgot, srel, -+ gotent->got_offset, h->dynindx, r_type, -+ gotent->addend); -+ -+ if (gotent->reloc_type == R_SW_64_TLSGD) -+ elf64_sw_64_emit_dynrel (output_bfd, info, sgot, srel, -+ gotent->got_offset + 8, h->dynindx, -+ R_SW_64_DTPREL64, gotent->addend); -+ } -+ } -+ -+ /* Mark some specially defined symbols as absolute. */ -+ if (h == elf_hash_table (info)->hdynamic || h == elf_hash_table (info)->hgot -+ || h == elf_hash_table (info)->hplt) -+ sym->st_shndx = SHN_ABS; -+ -+ return true; -+} -+ -+/* Finish up the dynamic sections. */ -+ -+static bool -+elf64_sw_64_finish_dynamic_sections (bfd *output_bfd, -+ struct bfd_link_info *info) -+{ -+ bfd *dynobj; -+ asection *sdyn; -+ -+ dynobj = elf_hash_table (info)->dynobj; -+ sdyn = bfd_get_linker_section (dynobj, ".dynamic"); -+ -+ if (elf_hash_table (info)->dynamic_sections_created) -+ { -+ asection *splt, *sgotplt, *srelaplt; -+ Elf64_External_Dyn *dyncon, *dynconend; -+ bfd_vma plt_vma, gotplt_vma; -+ -+ splt = elf_hash_table (info)->splt; -+ srelaplt = elf_hash_table (info)->srelplt; -+ BFD_ASSERT (splt != NULL && sdyn != NULL); -+ -+ plt_vma = splt->output_section->vma + splt->output_offset; -+ -+ gotplt_vma = 0; -+ if (elf64_sw_64_use_secureplt) -+ { -+ sgotplt = elf_hash_table (info)->sgotplt; -+ BFD_ASSERT (sgotplt != NULL); -+ if (sgotplt->size > 0) -+ gotplt_vma = sgotplt->output_section->vma + sgotplt->output_offset; -+ } -+ -+ dyncon = (Elf64_External_Dyn *) sdyn->contents; -+ dynconend = (Elf64_External_Dyn *) (sdyn->contents + sdyn->size); -+ for (; dyncon < dynconend; dyncon++) -+ { -+ Elf_Internal_Dyn dyn; -+ -+ bfd_elf64_swap_dyn_in (dynobj, dyncon, &dyn); -+ -+ switch (dyn.d_tag) -+ { -+ case DT_PLTGOT: -+ dyn.d_un.d_ptr = elf64_sw_64_use_secureplt ? gotplt_vma : plt_vma; -+ break; -+ case DT_PLTRELSZ: -+ dyn.d_un.d_val = srelaplt ? srelaplt->size : 0; -+ break; -+ case DT_JMPREL: -+ dyn.d_un.d_ptr -+ = srelaplt -+ ? (srelaplt->output_section->vma + srelaplt->output_offset) -+ : 0; -+ break; -+ } -+ -+ bfd_elf64_swap_dyn_out (output_bfd, &dyn, dyncon); -+ } -+ -+ /* Initialize the plt header. */ -+ if (splt->size > 0) -+ { -+ unsigned int insn; -+ int ofs; -+ -+ if (elf64_sw_64_use_secureplt) -+ { -+ ofs = gotplt_vma - (plt_vma + PLT_HEADER_SIZE); -+ -+ insn = INSN_ABC (INSN_SUBL, 27, 28, 25); -+ bfd_put_32 (output_bfd, insn, splt->contents); -+ -+ insn = INSN_ABO (INSN_LDIH, 28, 28, (ofs + 0x8000) >> 16); -+ bfd_put_32 (output_bfd, insn, splt->contents + 4); -+ -+ insn = INSN_ABC (INSN_S4SUBL, 25, 25, 25); -+ bfd_put_32 (output_bfd, insn, splt->contents + 8); -+ -+ insn = INSN_ABO (INSN_LDI, 28, 28, ofs); -+ bfd_put_32 (output_bfd, insn, splt->contents + 12); -+ -+ insn = INSN_ABO (INSN_LDL, 27, 28, 0); -+ bfd_put_32 (output_bfd, insn, splt->contents + 16); -+ -+ insn = INSN_ABC (INSN_ADDL, 25, 25, 25); -+ bfd_put_32 (output_bfd, insn, splt->contents + 20); -+ -+ insn = INSN_ABO (INSN_LDL, 28, 28, 8); -+ bfd_put_32 (output_bfd, insn, splt->contents + 24); -+ -+ insn = INSN_AB (INSN_JMP, 31, 27); -+ bfd_put_32 (output_bfd, insn, splt->contents + 28); -+ -+ insn = INSN_AD (INSN_BR, 28, -PLT_HEADER_SIZE); -+ bfd_put_32 (output_bfd, insn, splt->contents + 32); -+ } -+ else -+ { -+ insn = INSN_AD (INSN_BR, 27, 0); /* br $27, .+4 */ -+ bfd_put_32 (output_bfd, insn, splt->contents); -+ -+ insn = INSN_ABO (INSN_LDL, 27, 27, 12); -+ bfd_put_32 (output_bfd, insn, splt->contents + 4); -+ -+ insn = INSN_UNOP; -+ bfd_put_32 (output_bfd, insn, splt->contents + 8); -+ -+ insn = INSN_AB (INSN_JMP, 27, 27); -+ bfd_put_32 (output_bfd, insn, splt->contents + 12); -+ -+ /* The next two words will be filled in by ld.so. */ -+ bfd_put_64 (output_bfd, 0, splt->contents + 16); -+ bfd_put_64 (output_bfd, 0, splt->contents + 24); -+ } -+ -+ elf_section_data (splt->output_section)->this_hdr.sh_entsize = 0; -+ } -+ } -+ -+ return true; -+} -+ -+/* We need to use a special link routine to handle the .mdebug section. -+ We need to merge all instances of these sections together, not write -+ them all out sequentially. */ -+ -+static bool -+elf64_sw_64_final_link (bfd *abfd, struct bfd_link_info *info) -+{ -+ asection *o; -+ struct bfd_link_order *p; -+ asection *mdebug_sec; -+ struct ecoff_debug_info debug; -+ const struct ecoff_debug_swap *swap -+ = get_elf_backend_data (abfd)->elf_backend_ecoff_debug_swap; -+ HDRR *symhdr = &debug.symbolic_header; -+ void *mdebug_handle = NULL; -+ struct sw_64_elf_link_hash_table *htab; -+ -+ htab = sw_64_elf_hash_table (info); -+ if (htab == NULL) -+ return false; -+ -+ /* Go through the sections and collect the mdebug information. */ -+ mdebug_sec = NULL; -+ for (o = abfd->sections; o != (asection *) NULL; o = o->next) -+ { -+ if (strcmp (o->name, ".mdebug") == 0) -+ { -+ struct extsym_info einfo; -+ -+ /* We have found the .mdebug section in the output file. -+ Look through all the link_orders comprising it and merge -+ the information together. */ -+ symhdr->magic = swap->sym_magic; -+ /* FIXME: What should the version stamp be? */ -+ symhdr->vstamp = 0; -+ symhdr->ilineMax = 0; -+ symhdr->cbLine = 0; -+ symhdr->idnMax = 0; -+ symhdr->ipdMax = 0; -+ symhdr->isymMax = 0; -+ symhdr->ioptMax = 0; -+ symhdr->iauxMax = 0; -+ symhdr->issMax = 0; -+ symhdr->issExtMax = 0; -+ symhdr->ifdMax = 0; -+ symhdr->crfd = 0; -+ symhdr->iextMax = 0; -+ -+ /* We accumulate the debugging information itself in the -+ debug_info structure. */ -+ debug.line = NULL; -+ debug.external_dnr = NULL; -+ debug.external_pdr = NULL; -+ debug.external_sym = NULL; -+ debug.external_opt = NULL; -+ debug.external_aux = NULL; -+ debug.ss = NULL; -+ debug.ssext = debug.ssext_end = NULL; -+ debug.external_fdr = NULL; -+ debug.external_rfd = NULL; -+ debug.external_ext = debug.external_ext_end = NULL; -+ -+ mdebug_handle = bfd_ecoff_debug_init (abfd, &debug, swap, info); -+ if (mdebug_handle == NULL) -+ return false; -+ -+ if (1) -+ { -+ asection *s; -+ EXTR esym; -+ bfd_vma last = 0; -+ unsigned int i; -+ static const char *const name[] -+ = {".text", ".init", ".fini", ".data", -+ ".rodata", ".sdata", ".sbss", ".bss"}; -+ static const int sc[] = {scText, scInit, scFini, scData, -+ scRData, scSData, scSBss, scBss}; -+ -+ esym.jmptbl = 0; -+ esym.cobol_main = 0; -+ esym.weakext = 0; -+ esym.reserved = 0; -+ esym.ifd = ifdNil; -+ esym.asym.iss = issNil; -+ esym.asym.st = stLocal; -+ esym.asym.reserved = 0; -+ esym.asym.index = indexNil; -+ for (i = 0; i < 8; i++) -+ { -+ esym.asym.sc = sc[i]; -+ s = bfd_get_section_by_name (abfd, name[i]); -+ if (s != NULL) -+ { -+ esym.asym.value = s->vma; -+ last = s->vma + s->size; -+ } -+ else -+ esym.asym.value = last; -+ -+ if (!bfd_ecoff_debug_one_external (abfd, &debug, swap, -+ name[i], &esym)) -+ return false; -+ } -+ } -+ -+ for (p = o->map_head.link_order; p != (struct bfd_link_order *) NULL; -+ p = p->next) -+ { -+ asection *input_section; -+ bfd *input_bfd; -+ const struct ecoff_debug_swap *input_swap; -+ struct ecoff_debug_info input_debug; -+ char *eraw_src; -+ char *eraw_end; -+ -+ if (p->type != bfd_indirect_link_order) -+ { -+ if (p->type == bfd_data_link_order) -+ continue; -+ abort (); -+ } -+ -+ input_section = p->u.indirect.section; -+ input_bfd = input_section->owner; -+ -+ if (!is_sw_64_elf (input_bfd)) -+ /* I don't know what a non SW_64 ELF bfd would be -+ doing with a .mdebug section, but I don't really -+ want to deal with it. */ -+ continue; -+ -+ input_swap = (get_elf_backend_data (input_bfd) -+ ->elf_backend_ecoff_debug_swap); -+ -+ BFD_ASSERT (p->size == input_section->size); -+ -+ /* The ECOFF linking code expects that we have already -+ read in the debugging information and set up an -+ ecoff_debug_info structure, so we do that now. */ -+ if (!elf64_sw_64_read_ecoff_info (input_bfd, input_section, -+ &input_debug)) -+ return false; -+ -+ if (!(bfd_ecoff_debug_accumulate (mdebug_handle, abfd, &debug, -+ swap, input_bfd, &input_debug, -+ input_swap, info))) -+ return false; -+ -+ /* Loop through the external symbols. For each one with -+ interesting information, try to find the symbol in -+ the linker global hash table and save the information -+ for the output external symbols. */ -+ eraw_src = (char *) input_debug.external_ext; -+ eraw_end = (eraw_src -+ + (input_debug.symbolic_header.iextMax -+ * input_swap->external_ext_size)); -+ for (; eraw_src < eraw_end; -+ eraw_src += input_swap->external_ext_size) -+ { -+ EXTR ext; -+ const char *name; -+ struct sw_64_elf_link_hash_entry *h; -+ -+ (*input_swap->swap_ext_in) (input_bfd, eraw_src, &ext); -+ if (ext.asym.sc == scNil || ext.asym.sc == scUndefined -+ || ext.asym.sc == scSUndefined) -+ continue; -+ -+ name = input_debug.ssext + ext.asym.iss; -+ h = sw_64_elf_link_hash_lookup (htab, name, false, false, -+ true); -+ if (h == NULL || h->esym.ifd != -2) -+ continue; -+ -+ if (ext.ifd != -1) -+ { -+ BFD_ASSERT (ext.ifd < input_debug.symbolic_header.ifdMax); -+ ext.ifd = input_debug.ifdmap[ext.ifd]; -+ } -+ -+ h->esym = ext; -+ } -+ -+ /* Free up the information we just read. */ -+ free (input_debug.line); -+ free (input_debug.external_dnr); -+ free (input_debug.external_pdr); -+ free (input_debug.external_sym); -+ free (input_debug.external_opt); -+ free (input_debug.external_aux); -+ free (input_debug.ss); -+ free (input_debug.ssext); -+ free (input_debug.external_fdr); -+ free (input_debug.external_rfd); -+ free (input_debug.external_ext); -+ -+ /* Hack: reset the SEC_HAS_CONTENTS flag so that -+ elf_link_input_bfd ignores this section. */ -+ input_section->flags &= ~SEC_HAS_CONTENTS; -+ } -+ -+ /* Build the external symbol information. */ -+ einfo.abfd = abfd; -+ einfo.info = info; -+ einfo.debug = &debug; -+ einfo.swap = swap; -+ einfo.failed = false; -+ elf_link_hash_traverse (elf_hash_table (info), -+ elf64_sw_64_output_extsym, &einfo); -+ if (einfo.failed) -+ return false; -+ -+ /* Set the size of the .mdebug section. */ -+ o->size = bfd_ecoff_debug_size (abfd, &debug, swap); -+ -+ /* Skip this section later on (I don't think this currently -+ matters, but someday it might). */ -+ o->map_head.link_order = (struct bfd_link_order *) NULL; -+ -+ mdebug_sec = o; -+ } -+ } -+ -+ /* Invoke the regular ELF backend linker to do all the work. */ -+ if (!bfd_elf_final_link (abfd, info)) -+ return false; -+ -+ /* Now write out the computed sections. */ -+ -+ /* The .got subsections... */ -+ { -+ bfd *i, *dynobj = elf_hash_table (info)->dynobj; -+ for (i = htab->got_list; i != NULL; i = sw_64_elf_tdata (i)->got_link_next) -+ { -+ asection *sgot; -+ -+ /* elf_bfd_final_link already did everything in dynobj. */ -+ if (i == dynobj) -+ continue; -+ -+ sgot = sw_64_elf_tdata (i)->got; -+ if (!bfd_set_section_contents (abfd, sgot->output_section, -+ sgot->contents, -+ (file_ptr) sgot->output_offset, -+ sgot->size)) -+ return false; -+ } -+ } -+ -+ if (mdebug_sec != (asection *) NULL) -+ { -+ BFD_ASSERT (abfd->output_has_begun); -+ if (!bfd_ecoff_write_accumulated_debug (mdebug_handle, abfd, &debug, swap, -+ info, mdebug_sec->filepos)) -+ return false; -+ -+ bfd_ecoff_debug_free (mdebug_handle, abfd, &debug, swap, info); -+ } -+ -+ return true; -+} -+ -+static enum elf_reloc_type_class -+elf64_sw_64_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED, -+ const asection *rel_sec ATTRIBUTE_UNUSED, -+ const Elf_Internal_Rela *rela) -+{ -+ switch ((int) ELF64_R_TYPE (rela->r_info)) -+ { -+ case R_SW_64_RELATIVE: -+ return reloc_class_relative; -+ case R_SW_64_JMP_SLOT: -+ return reloc_class_plt; -+ case R_SW_64_COPY: -+ return reloc_class_copy; -+ default: -+ return reloc_class_normal; -+ } -+} -+ -+static const struct bfd_elf_special_section elf64_sw_64_special_sections[] -+ = {{STRING_COMMA_LEN (".sbss"), -2, SHT_NOBITS, -+ SHF_ALLOC + SHF_WRITE + SHF_SW_64_GPREL}, -+ {STRING_COMMA_LEN (".sdata"), -2, SHT_PROGBITS, -+ SHF_ALLOC + SHF_WRITE + SHF_SW_64_GPREL}, -+ {NULL, 0, 0, 0, 0}}; -+ -+/* ECOFF swapping routines. These are used when dealing with the -+ .mdebug section, which is in the ECOFF debugging format. Copied -+ from elf32-mips.c. */ -+static const struct ecoff_debug_swap elf64_sw_64_ecoff_debug_swap = { -+ /* Symbol table magic number. */ -+ magicSym2, -+ /* Alignment of debugging information. E.g., 4. */ -+ 8, -+ /* Sizes of external symbolic information. */ -+ sizeof (struct hdr_ext), sizeof (struct dnr_ext), sizeof (struct pdr_ext), -+ sizeof (struct sym_ext), sizeof (struct opt_ext), sizeof (struct fdr_ext), -+ sizeof (struct rfd_ext), sizeof (struct ext_ext), -+ /* Functions to swap in external symbolic data. */ -+ ecoff_swap_hdr_in, ecoff_swap_dnr_in, ecoff_swap_pdr_in, ecoff_swap_sym_in, -+ ecoff_swap_opt_in, ecoff_swap_fdr_in, ecoff_swap_rfd_in, ecoff_swap_ext_in, -+ _bfd_ecoff_swap_tir_in, _bfd_ecoff_swap_rndx_in, -+ /* Functions to swap out external symbolic data. */ -+ ecoff_swap_hdr_out, ecoff_swap_dnr_out, ecoff_swap_pdr_out, -+ ecoff_swap_sym_out, ecoff_swap_opt_out, ecoff_swap_fdr_out, -+ ecoff_swap_rfd_out, ecoff_swap_ext_out, _bfd_ecoff_swap_tir_out, -+ _bfd_ecoff_swap_rndx_out, -+ /* Function to read in symbolic data. */ -+ elf64_sw_64_read_ecoff_info}; -+ -+/* Use a non-standard hash bucket size of 8. */ -+ -+static const struct elf_size_info sw_64_elf_size_info -+ = {sizeof (Elf64_External_Ehdr), -+ sizeof (Elf64_External_Phdr), -+ sizeof (Elf64_External_Shdr), -+ sizeof (Elf64_External_Rel), -+ sizeof (Elf64_External_Rela), -+ sizeof (Elf64_External_Sym), -+ sizeof (Elf64_External_Dyn), -+ sizeof (Elf_External_Note), -+ 8, -+ 1, -+ 64, -+ 3, -+ ELFCLASS64, -+ EV_CURRENT, -+ bfd_elf64_write_out_phdrs, -+ bfd_elf64_write_shdrs_and_ehdr, -+ bfd_elf64_checksum_contents, -+ bfd_elf64_write_relocs, -+ bfd_elf64_swap_symbol_in, -+ bfd_elf64_swap_symbol_out, -+ bfd_elf64_slurp_reloc_table, -+ bfd_elf64_slurp_symbol_table, -+ bfd_elf64_swap_dyn_in, -+ bfd_elf64_swap_dyn_out, -+ bfd_elf64_swap_reloc_in, -+ bfd_elf64_swap_reloc_out, -+ bfd_elf64_swap_reloca_in, -+ bfd_elf64_swap_reloca_out}; -+ -+#define TARGET_LITTLE_SYM sw_64_elf64_vec -+#define TARGET_LITTLE_NAME "elf64-sw_64" -+#define ELF_ARCH bfd_arch_sw_64 -+#define ELF_TARGET_ID SW_64_ELF_DATA -+#define ELF_MACHINE_CODE EM_SW_64 -+#define ELF_MAXPAGESIZE 0x10000 -+#define ELF_COMMONPAGESIZE 0x2000 -+ -+#define bfd_elf64_bfd_link_hash_table_create \ -+ elf64_sw_64_bfd_link_hash_table_create -+ -+#define bfd_elf64_bfd_reloc_type_lookup elf64_sw_64_bfd_reloc_type_lookup -+#define bfd_elf64_bfd_reloc_name_lookup elf64_sw_64_bfd_reloc_name_lookup -+#define elf_info_to_howto elf64_sw_64_info_to_howto -+ -+#define bfd_elf64_mkobject elf64_sw_64_mkobject -+#define elf_backend_object_p elf64_sw_64_object_p -+ -+#define elf_backend_section_from_shdr elf64_sw_64_section_from_shdr -+#define elf_backend_section_flags elf64_sw_64_section_flags -+#define elf_backend_fake_sections elf64_sw_64_fake_sections -+ -+#define bfd_elf64_bfd_is_local_label_name elf64_sw_64_is_local_label_name -+#define bfd_elf64_find_nearest_line elf64_sw_64_find_nearest_line -+#define bfd_elf64_bfd_relax_section elf64_sw_64_relax_section -+ -+#define elf_backend_add_symbol_hook elf64_sw_64_add_symbol_hook -+#define elf_backend_relocs_compatible _bfd_elf_relocs_compatible -+#define elf_backend_sort_relocs_p elf64_sw_64_sort_relocs_p -+#define elf_backend_check_relocs elf64_sw_64_check_relocs -+#define elf_backend_create_dynamic_sections elf64_sw_64_create_dynamic_sections -+#define elf_backend_adjust_dynamic_symbol elf64_sw_64_adjust_dynamic_symbol -+#define elf_backend_merge_symbol_attribute elf64_sw_64_merge_symbol_attribute -+#define elf_backend_copy_indirect_symbol elf64_sw_64_copy_indirect_symbol -+#define elf_backend_always_size_sections elf64_sw_64_always_size_sections -+#define elf_backend_size_dynamic_sections elf64_sw_64_size_dynamic_sections -+#define elf_backend_omit_section_dynsym _bfd_elf_omit_section_dynsym_all -+#define elf_backend_relocate_section elf64_sw_64_relocate_section -+#define elf_backend_finish_dynamic_symbol elf64_sw_64_finish_dynamic_symbol -+#define elf_backend_finish_dynamic_sections elf64_sw_64_finish_dynamic_sections -+#define bfd_elf64_bfd_final_link elf64_sw_64_final_link -+#define elf_backend_reloc_type_class elf64_sw_64_reloc_type_class -+ -+#define elf_backend_can_gc_sections 1 -+#define elf_backend_gc_mark_hook elf64_sw_64_gc_mark_hook -+ -+#define elf_backend_ecoff_debug_swap &elf64_sw_64_ecoff_debug_swap -+ -+#define elf_backend_size_info sw_64_elf_size_info -+ -+#define elf_backend_special_sections elf64_sw_64_special_sections -+ -+#define elf_backend_strip_zero_sized_dynamic_sections \ -+ _bfd_elf_strip_zero_sized_dynamic_sections -+ -+/* A few constants that determine how the .plt section is set up. */ -+#define elf_backend_want_got_plt 0 -+#define elf_backend_plt_readonly 0 -+#define elf_backend_want_plt_sym 1 -+#define elf_backend_got_header_size 0 -+#define elf_backend_dtrel_excludes_plt 1 -+ -+#include "elf64-target.h" -+ -+/* FreeBSD support. */ -+ -+#undef TARGET_LITTLE_SYM -+#define TARGET_LITTLE_SYM sw_64_elf64_fbsd_vec -+#undef TARGET_LITTLE_NAME -+#define TARGET_LITTLE_NAME "elf64-sw_64-freebsd" -+#undef ELF_OSABI -+#define ELF_OSABI ELFOSABI_FREEBSD -+ -+/* The kernel recognizes executables as valid only if they carry a -+ "FreeBSD" label in the ELF header. So we put this label on all -+ executables and (for simplicity) also all other object files. */ -+ -+static bool -+elf64_sw_64_fbsd_init_file_header (bfd *abfd, struct bfd_link_info *info) -+{ -+ Elf_Internal_Ehdr *i_ehdrp; /* ELF file header, internal form. */ -+ -+ if (!_bfd_elf_init_file_header (abfd, info)) -+ return false; -+ -+ i_ehdrp = elf_elfheader (abfd); -+ -+ /* Put an ABI label supported by FreeBSD >= 4.1. */ -+ i_ehdrp->e_ident[EI_OSABI] = get_elf_backend_data (abfd)->elf_osabi; -+#ifdef OLD_FREEBSD_ABI_LABEL -+ /* The ABI label supported by FreeBSD <= 4.0 is quite nonstandard. */ -+ memcpy (&i_ehdrp->e_ident[EI_ABIVERSION], "FreeBSD", 8); -+#endif -+ return true; -+} -+#undef elf_backend_init_file_header -+#define elf_backend_init_file_header elf64_sw_64_fbsd_init_file_header -+ -+#undef elf64_bed -+#define elf64_bed elf64_sw_64_fbsd_bed -+ -+#include "elf64-target.h" -diff --git a/bfd/hosts/sw_64linux.h b/bfd/hosts/sw_64linux.h -new file mode 100644 -index 00000000..e5dfe2a1 ---- /dev/null -+++ b/bfd/hosts/sw_64linux.h -@@ -0,0 +1,25 @@ -+/* Copyright (C) 2007-2023 Free Software Foundation, Inc. -+ -+ This file is part of BFD, the Binary File Descriptor library. -+ -+ This program is free software; you can redistribute it and/or modify -+ it under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 3 of the License, or -+ (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ GNU General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, -+ MA 02110-1301, USA. */ -+ -+/* Linux dumps "struct task_struct" at the end of the core-file. This -+ structure is currently 1080 bytes long, but we allow up to 4096 -+ bytes to allow for some future growth. */ -+#define TRAD_CORE_EXTRA_SIZE_ALLOWED 4096 -+#define TRAD_UNIX_CORE_FILE_FAILING_SIGNAL(abfd) \ -+ ((abfd)->tdata.trad_core_data->u.signal) -diff --git a/bfd/libbfd-in.h b/bfd/libbfd-in.h -index 03ae099c..a72fedb0 100644 ---- a/bfd/libbfd-in.h -+++ b/bfd/libbfd-in.h -@@ -413,8 +413,12 @@ extern bfd_cleanup _bfd_vms_lib_alpha_archive_p - (bfd *) ATTRIBUTE_HIDDEN; - extern bfd_cleanup _bfd_vms_lib_ia64_archive_p - (bfd *) ATTRIBUTE_HIDDEN; -+extern const bfd_target *_bfd_vms_lib_sw_64_archive_p -+ (bfd *) ATTRIBUTE_HIDDEN; - extern bool _bfd_vms_lib_alpha_mkarchive - (bfd *) ATTRIBUTE_HIDDEN; -+extern bfd_boolean _bfd_vms_lib_sw_64_mkarchive -+ (bfd *) ATTRIBUTE_HIDDEN; - extern bool _bfd_vms_lib_ia64_mkarchive - (bfd *) ATTRIBUTE_HIDDEN; - -diff --git a/bfd/libbfd.h b/bfd/libbfd.h -index d4fb3107..40ac4a78 100644 ---- a/bfd/libbfd.h -+++ b/bfd/libbfd.h -@@ -1241,6 +1241,36 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@", - "BFD_RELOC_ALPHA_TPREL_HI16", - "BFD_RELOC_ALPHA_TPREL_LO16", - "BFD_RELOC_ALPHA_TPREL16", -+#ifdef TARGET_SW_64 -+ "BFD_RELOC_SW_64_GPDISP_HI16", -+ "BFD_RELOC_SW_64_GPDISP_LO16", -+ "BFD_RELOC_SW_64_GPDISP", -+ "BFD_RELOC_SW_64_LITERAL", -+ "BFD_RELOC_SW_64_ELF_LITERAL", -+ "BFD_RELOC_SW_64_LITUSE", -+ "BFD_RELOC_SW_64_HINT", -+ "BFD_RELOC_SW_64_LINKAGE", -+ "BFD_RELOC_SW_64_CODEADDR", -+ "BFD_RELOC_SW_64_GPREL_HI16", -+ "BFD_RELOC_SW_64_GPREL_LO16", -+ "BFD_RELOC_SW_64_BRSGP" -+ "BFD_RELOC_SW_64_NOP", -+ "BFD_RELOC_SW_64_BSR", -+ "BFD_RELOC_SW_64_LDA", -+ "BFD_RELOC_SW_64_BOH", -+ "BFD_RELOC_SW_64_TLSGD", -+ "BFD_RELOC_SW_64_TLSLDM", -+ "BFD_RELOC_SW_64_DTPMOD64", -+ "BFD_RELOC_SW_64_GOTDTPREL16", -+ "BFD_RELOC_SW_64_DTPREL64", -+ "BFD_RELOC_SW_64_DTPREL_HI16", -+ "BFD_RELOC_SW_64_DTPREL_LO16", -+ "BFD_RELOC_SW_64_DTPREL16", -+ "BFD_RELOC_SW_64_GOTTPREL16", -+ "BFD_RELOC_SW_64_TPREL64", -+ "BFD_RELOC_SW_64_TLSREL_GOT", -+ "BFD_RELOC_SW_64_ELF_LITERAL_GOT", -+#endif - "BFD_RELOC_MIPS_JMP", - "BFD_RELOC_MICROMIPS_JMP", - "BFD_RELOC_MIPS16_JMP", -diff --git a/bfd/peicode.h b/bfd/peicode.h -index e2e2be65..7f5f196d 100644 ---- a/bfd/peicode.h -+++ b/bfd/peicode.h -@@ -1203,6 +1203,10 @@ pe_ILF_object_p (bfd * abfd) - case IMAGE_FILE_MACHINE_UNKNOWN: - case IMAGE_FILE_MACHINE_ALPHA: - case IMAGE_FILE_MACHINE_ALPHA64: -+#ifdef TARGET_SW_64 -+ case IMAGE_FILE_MACHINE_SW_64: -+ case IMAGE_FILE_MACHINE_SW_6464: -+#endif - case IMAGE_FILE_MACHINE_IA64: - break; - -diff --git a/bfd/reloc.c b/bfd/reloc.c -index fbc67ac7..bb961186 100644 ---- a/bfd/reloc.c -+++ b/bfd/reloc.c -@@ -1546,6 +1546,8 @@ ENUMX - BFD_RELOC_16_PCREL_S2 - ENUMX - BFD_RELOC_23_PCREL_S2 -+ENUMX -+ BFD_RELOC_SW_64_BR26 - ENUMDOC - These PC-relative relocations are stored as word displacements -- - i.e., byte displacements shifted right two bits. The 30-bit word -diff --git a/bfd/targets.c b/bfd/targets.c -index 3dbcd088..02ca240d 100644 ---- a/bfd/targets.c -+++ b/bfd/targets.c -@@ -690,6 +690,14 @@ extern const bfd_target alpha_elf64_vec; - extern const bfd_target alpha_elf64_fbsd_vec; - extern const bfd_target alpha_vms_vec; - extern const bfd_target alpha_vms_lib_txt_vec; -+#ifdef TARGET_SW_64 -+extern const bfd_target sw_64_ecoff_le_vec; -+extern const bfd_target sw_64_elf64_vec; -+extern const bfd_target sw_64_elf64_fbsd_vec; -+extern const bfd_target sw_64_nlm32_vec; -+extern const bfd_target sw_64_vms_vec; -+extern const bfd_target sw_64_vms_lib_txt_vec; -+#endif - extern const bfd_target am33_elf32_linux_vec; - extern const bfd_target amdgcn_elf64_le_vec; - extern const bfd_target aout_vec; -@@ -1011,6 +1019,15 @@ static const bfd_target * const _bfd_target_vector[] = - #endif - &alpha_vms_lib_txt_vec, - -+#ifdef BFD64 -+ &sw_64_ecoff_le_vec, -+ &sw_64_elf64_vec, -+ &sw_64_elf64_fbsd_vec, -+ &sw_64_nlm32_vec, -+ &sw_64_vms_vec, -+#endif -+ &sw_64_vms_lib_txt_vec, -+ - &am33_elf32_linux_vec, - - #if 0 -diff --git a/binutils/config.in b/binutils/config.in -index 91fe00af..2c53f57d 100644 ---- a/binutils/config.in -+++ b/binutils/config.in -@@ -262,3 +262,5 @@ - - /* Define to 1 if you need to in order for `stat' and other things to work. */ - #undef _POSIX_SOURCE -+ -+#undef TARGET_SW_64 -diff --git a/binutils/configure b/binutils/configure -index e0bf7f1e..664dbbeb 100755 ---- a/binutils/configure -+++ b/binutils/configure -@@ -14675,6 +14675,11 @@ do - mep-*) - OBJDUMP_DEFS="-DSKIP_ZEROES=256 -DSKIP_ZEROES_AT_END=0" - ;; -+ sw_64-*-*) -+cat >>confdefs.h <<_ACEOF -+#define TARGET_SW_64 -+_ACEOF -+ ;; - esac - - # Add objdump private vectors. -diff --git a/binutils/readelf.c b/binutils/readelf.c -index 97d72d0b..f8be1eba 100644 ---- a/binutils/readelf.c -+++ b/binutils/readelf.c -@@ -96,6 +96,9 @@ - - #include "elf/aarch64.h" - #include "elf/alpha.h" -+#ifdef TARGET_SW_64 -+#include "elf/sw_64.h" -+#endif - #include "elf/amdgpu.h" - #include "elf/arc.h" - #include "elf/arm.h" -@@ -1057,6 +1060,9 @@ guess_is_rela (unsigned int e_machine) - case EM_AARCH64: - case EM_ADAPTEVA_EPIPHANY: - case EM_ALPHA: -+#ifdef TARGET_SW_64 -+ case EM_SW_64: -+#endif - case EM_ALTERA_NIOS2: - case EM_ARC: - case EM_ARC_COMPACT: -@@ -1731,6 +1737,12 @@ dump_relocations (Filedata *filedata, - rtype = elf_alpha_reloc_type (type); - break; - -+#ifdef TARGET_SW_64 -+ case EM_SW_64: -+ rtype = elf_sw_64_reloc_type (type); -+ break; -+#endif -+ - case EM_ARM: - rtype = elf_arm_reloc_type (type); - break; -@@ -1950,6 +1962,47 @@ dump_relocations (Filedata *filedata, - res = false; - } - } -+#ifdef TARGET_SW_64 -+ else if (filedata->file_header.e_machine == EM_SW_64 && rtype != NULL -+ && streq (rtype, "R_SW_64_LITUSE")) -+ { -+ switch (rels[i].r_addend) -+ { -+ case LITUSE_SW_64_ADDR: -+ rtype = "ADDR"; -+ break; -+ case LITUSE_SW_64_BASE: -+ rtype = "BASE"; -+ break; -+ case LITUSE_SW_64_BYTOFF: -+ rtype = "BYTOFF"; -+ break; -+ case LITUSE_SW_64_JSR: -+ rtype = "JSR"; -+ break; -+ case LITUSE_SW_64_TLSGD: -+ rtype = "TLSGD"; -+ break; -+ case LITUSE_SW_64_TLSLDM: -+ rtype = "TLSLDM"; -+ break; -+ case LITUSE_SW_64_JSRDIRECT: -+ rtype = "JSRDIRECT"; -+ break; -+ default: -+ rtype = NULL; -+ } -+ if (rtype) -+ printf (" (%s)", rtype); -+ else -+ { -+ putchar (' '); -+ printf (_ (""), -+ (unsigned long) rels[i].r_addend); -+ res = false; -+ } -+ } -+#endif - else if (symtab_index) - { - if (symtab == NULL || symtab_index >= nsyms) -@@ -2355,6 +2408,20 @@ get_alpha_dynamic_type (unsigned long type) - } - } - -+#ifdef TARGET_SW_64 -+static const char * -+get_sw_64_dynamic_type (unsigned long type) -+{ -+ switch (type) -+ { -+ case DT_SW_64_PLTRO: -+ return "SW_64_PLTRO"; -+ default: -+ return NULL; -+ } -+} -+#endif -+ - static const char * - get_score_dynamic_type (unsigned long type) - { -@@ -2559,6 +2626,11 @@ get_dynamic_type (Filedata * filedata, unsigned long type) - case EM_ALPHA: - result = get_alpha_dynamic_type (type); - break; -+#ifdef TARGET_SW_64 -+ case EM_SW_64: -+ result = get_sw_64_dynamic_type (type); -+ break; -+#endif - case EM_SCORE: - result = get_score_dynamic_type (type); - break; -@@ -2979,6 +3051,10 @@ get_machine_name (unsigned e_machine) - /* Large numbers... */ - case EM_MT: return "Morpho Techologies MT processor"; - case EM_ALPHA: return "Alpha"; -+#ifdef TARGET_SW_64 -+ case EM_SW_64: -+ return "Sw_64"; -+#endif - case EM_WEBASSEMBLY: return "Web Assembly"; - case EM_DLX: return "OpenDLX"; - case EM_XSTORMY16: return "Sanyo XStormy16 CPU core"; -@@ -11092,6 +11168,7 @@ get_num_dynamic_syms (Filedata * filedata) - unsigned int hash_ent_size = 4; - - if ((filedata->file_header.e_machine == EM_ALPHA -+ || filedata->file_header.e_machine == EM_SW_64 - || filedata->file_header.e_machine == EM_S390 - || filedata->file_header.e_machine == EM_S390_OLD) - && filedata->file_header.e_ident[EI_CLASS] == ELFCLASS64) -@@ -12791,6 +12868,23 @@ get_alpha_symbol_other (unsigned int other) - } - } - -+#ifdef TARGET_SW_64 -+static const char * -+get_sw_64_symbol_other (unsigned int other) -+{ -+ switch (other) -+ { -+ case STO_SW_64_NOPV: -+ return "NOPV"; -+ case STO_SW_64_STD_GPLOAD: -+ return "STD GPLOAD"; -+ default: -+ error (_ ("Unrecognized sw_64 specific other value: %u"), other); -+ return _ (""); -+ } -+} -+#endif -+ - static const char * - get_solaris_symbol_visibility (unsigned int visibility) - { -@@ -12955,6 +13049,11 @@ get_symbol_other (Filedata * filedata, unsigned int other) - case EM_ALPHA: - result = get_alpha_symbol_other (other); - break; -+#ifdef TARGET_SW_64 -+ case EM_SW_64: -+ result = get_sw_64_symbol_other (other); -+ break; -+#endif - case EM_AARCH64: - result = get_aarch64_symbol_other (other); - break; -@@ -14320,6 +14419,10 @@ is_32bit_abs_reloc (Filedata * filedata, unsigned int reloc_type) - return reloc_type == 3; - case EM_ALPHA: - return reloc_type == 1; /* R_ALPHA_REFLONG. */ -+#ifdef TARGET_SW_64 -+ case EM_SW_64: -+ return reloc_type == 1; /* R_SW_64_REFLONG. */ -+#endif - case EM_ARC: - return reloc_type == 1; /* R_ARC_32. */ - case EM_ARC_COMPACT: -@@ -14516,6 +14619,10 @@ is_32bit_pcrel_reloc (Filedata * filedata, unsigned int reloc_type) - return reloc_type == 6; - case EM_ALPHA: - return reloc_type == 10; /* R_ALPHA_SREL32. */ -+#ifdef TARGET_SW_64 -+ case EM_SW_64: -+ return reloc_type == 10; /* R_SW_64_SREL32. */ -+#endif - case EM_ARC_COMPACT: - case EM_ARC_COMPACT2: - return reloc_type == 49; /* R_ARC_32_PCREL. */ -@@ -14586,6 +14693,10 @@ is_64bit_abs_reloc (Filedata * filedata, unsigned int reloc_type) - return reloc_type == 257; /* R_AARCH64_ABS64. */ - case EM_ALPHA: - return reloc_type == 2; /* R_ALPHA_REFQUAD. */ -+#ifdef TARGET_SW_64 -+ case EM_SW_64: -+ return reloc_type == 2; /* R_SW_64_REFQUAD. */ -+#endif - case EM_IA_64: - return (reloc_type == 0x26 /* R_IA64_DIR64MSB. */ - || reloc_type == 0x27 /* R_IA64_DIR64LSB. */); -@@ -14630,6 +14741,10 @@ is_64bit_pcrel_reloc (Filedata * filedata, unsigned int reloc_type) - return reloc_type == 260; /* R_AARCH64_PREL64. */ - case EM_ALPHA: - return reloc_type == 11; /* R_ALPHA_SREL64. */ -+#ifdef TARGET_SW_64 -+ case EM_SW_64: -+ return reloc_type == 11; /* R_SW_64_SREL64. */ -+#endif - case EM_IA_64: - return (reloc_type == 0x4e /* R_IA64_PCREL64MSB. */ - || reloc_type == 0x4f /* R_IA64_PCREL64LSB. */); -@@ -14965,6 +15080,9 @@ is_none_reloc (Filedata * filedata, unsigned int reloc_type) - case EM_68K: /* R_68K_NONE. */ - case EM_ADAPTEVA_EPIPHANY: - case EM_ALPHA: /* R_ALPHA_NONE. */ -+#ifdef TARGET_SW_64 -+ case EM_SW_64: /* R_SW_64_NONE. */ -+#endif - case EM_ALTERA_NIOS2: /* R_NIOS2_NONE. */ - case EM_ARC: /* R_ARC_NONE. */ - case EM_ARC_COMPACT2: /* R_ARC_NONE. */ -@@ -20755,6 +20873,9 @@ get_netbsd_elfcore_note_type (Filedata * filedata, unsigned e_type) - - case EM_OLD_ALPHA: - case EM_ALPHA: -+#ifdef TARGET_SW_64 -+ case EM_SW_64: -+#endif - case EM_SPARC: - case EM_SPARC32PLUS: - case EM_SPARCV9: -diff --git a/binutils/testsuite/binutils-all/nm.exp b/binutils/testsuite/binutils-all/nm.exp -index 91b519d9..a5bccc7b 100644 ---- a/binutils/testsuite/binutils-all/nm.exp -+++ b/binutils/testsuite/binutils-all/nm.exp -@@ -44,7 +44,7 @@ if {![binutils_assemble $srcdir/$subdir/bintest.s tmpdir/bintest.o]} then { - - # This test does not work correctly on ECOFF targets, because ECOFF - # stores most symbols twice, which messes up the nm output. -- setup_xfail "alpha*-*-*ecoff" "alpha*-*-osf*" -+ setup_xfail "alpha*-*-*ecoff" "alpha*-*-osf*" "sw_64*-*-*ecoff" "sw_64*-*-osf*" - - # This test does not work correctly on XCOFF targets, because XCOFF - # does not enter static symbols in the symbol table. -@@ -102,7 +102,7 @@ if {![binutils_assemble $srcdir/$subdir/bintest.s tmpdir/bintest.o]} then { - - # This test does not work correctly on ECOFF targets, because ECOFF - # stores most symbols twice, which messes up the nm output. -- setup_xfail "alpha*-*-*ecoff" "alpha*-*-osf*" -+ setup_xfail "alpha*-*-*ecoff" "alpha*-*-osf*" "sw_64*-*-*ecoff" "sw_64*-*-osf*" - - # This test does not work correctly on XCOFF targets, because XCOFF - # does not enter static symbols in the symbol table. -@@ -251,7 +251,7 @@ if [is_elf_format] { - setup_xfail "sh*-*-*" - # The pre-compiled dwarf info in dw4.s is not compatible with the - # ALPHA, HPPA, IA64 and MIPS targets. -- setup_xfail "alpha*-*-*" "hppa*-*-*" "ia64*-*-*" "mips*-*-*" -+ setup_xfail "alpha*-*-*" "sw_64*-*-*" "hppa*-*-*" "ia64*-*-*" "mips*-*-*" - # Assembling the source file triggers an ICE in the FT32 assembler. - # FIXME: Fix the ICE... - setup_xfail "ft32-*-*" -@@ -291,7 +291,7 @@ if [is_elf_format] { - # Test nm --ifunc-chars on a indirect symbols. - - # The following targets are known to not support ifuncs. -- setup_xfail "alpha*-*-*" -+ setup_xfail "alpha*-*-*" "sw_64*-*-*" - setup_xfail "arm*-elf" "arm*-*-nto*" "arm*-*-netbsd*" - setup_xfail "*-*-hpux*" - setup_xfail "mips*-*-*" "tx39*-*-*" -diff --git a/config.guess b/config.guess -index 354a8ccd..24e06352 100755 ---- a/config.guess -+++ b/config.guess -@@ -369,6 +369,36 @@ case $UNAME_MACHINE:$UNAME_SYSTEM:$UNAME_RELEASE:$UNAME_VERSION in - OSF_REL=`echo "$UNAME_RELEASE" | sed -e 's/^[PVTX]//' | tr ABCDEFGHIJKLMNOPQRSTUVWXYZ abcdefghijklmnopqrstuvwxyz` - GUESS=$UNAME_MACHINE-dec-osf$OSF_REL - ;; -+ sw_64:OSF1:*:*) -+ case $UNAME_RELEASE in -+ *4.0) -+ UNAME_RELEASE=`/usr/sbin/sizer -v | awk '{print $3}'` -+ ;; -+ *5.*) -+ UNAME_RELEASE=`/usr/sbin/sizer -v | awk '{print $4}'` -+ ;; -+ esac -+ # According to Compaq, /usr/sbin/psrinfo has been available on -+ # OSF/1 and Tru64 systems produced since 1995. I hope that -+ # covers most systems running today. This code pipes the CPU -+ # types through head -n 1, so we only detect the type of CPU 0. -+ SW_64_CPU_TYPE=`/usr/sbin/psrinfo -v | sed -n -e 's/^ The sw_64 \(.*\) processor.*$/\1/p' | head -n 1` -+ case "$SW_64_CPU_TYPE" in -+ "SW6A (21264)") -+ UNAME_MACHINE="sw_64sw6a" ;; -+ "SW6B (21264)") -+ UNAME_MACHINE="sw_64sw6b" ;; -+ "SW6 (21264A)") -+ UNAME_MACHINE="sw_64sw6" ;; -+ esac -+ # A Pn.n version is a patched version. -+ # A Vn.n version is a released version. -+ # A Tn.n version is a released field test version. -+ # A Xn.n version is an unreleased experimental baselevel. -+ # 1.2 uses "1.2" for uname -r. -+ OSF_REL=`echo "$UNAME_RELEASE" | sed -e 's/^[PVTX]//' | tr ABCDEFGHIJKLMNOPQRSTUVWXYZ abcdefghijklmnopqrstuvwxyz` -+ GUESS=$UNAME_MACHINE-dec-osf$OSF_REL -+ ;; - Amiga*:UNIX_System_V:4.0:*) - GUESS=m68k-unknown-sysv4 - ;; -@@ -996,6 +1026,17 @@ EOF - if test "$?" = 0 ; then LIBC=gnulibc1 ; fi - GUESS=$UNAME_MACHINE-unknown-linux-$LIBC - ;; -+ sw_64:Linux:*:*) -+ case `sed -n '/^cpu model/s/^.*: \(.*\)/\1/p' /proc/cpuinfo 2>/dev/null` in -+ SW6A) UNAME_MACHINE=sw_64sw6a ;; -+ SW6B) UNAME_MACHINE=sw_64sw6b ;; -+ SW8A) UNAME_MACHINE=sw_64sw8a ;; -+ SW6) UNAME_MACHINE=sw_64sw6 ;; -+ esac -+ objdump --private-headers /bin/sh | grep -q ld.so.1 -+ if test "$?" = 0 ; then LIBC="gnulibc1" ; fi -+ GUESS=$UNAME_MACHINE-unknown-linux-${LIBC} -+ ;; - arc:Linux:*:* | arceb:Linux:*:* | arc32:Linux:*:* | arc64:Linux:*:*) - GUESS=$UNAME_MACHINE-unknown-linux-$LIBC - ;; -diff --git a/config.sub b/config.sub -index f6ede1d0..72927971 100755 ---- a/config.sub -+++ b/config.sub -@@ -1185,6 +1185,7 @@ case $cpu-$vendor in - | alpha | alphaev[4-8] | alphaev56 | alphaev6[78] \ - | alpha64 | alpha64ev[4-8] | alpha64ev56 | alpha64ev6[78] \ - | alphapca5[67] | alpha64pca5[67] \ -+ | sw_64 | sw_64sw6a | sw_64sw6b | sw_64sw8a \ - | am33_2.0 \ - | amdgcn \ - | arc | arceb | arc32 | arc64 \ -diff --git a/config/elf.m4 b/config/elf.m4 -index 1772a443..537373c3 100644 ---- a/config/elf.m4 -+++ b/config/elf.m4 -@@ -17,7 +17,7 @@ target_elf=no - case $target in - *-darwin* | *-aix* | *-cygwin* | *-mingw* | *-aout* | *-*coff* | \ - *-msdosdjgpp* | *-vms* | *-wince* | *-*-pe* | \ -- alpha*-dec-osf* | *-interix* | hppa[[12]]*-*-hpux* | \ -+ alpha*-dec-osf* | sw_64*-dec-osf* | *-interix* | hppa[[12]]*-*-hpux* | \ - nvptx-*-none) - target_elf=no - ;; -diff --git a/config/intdiv0.m4 b/config/intdiv0.m4 -index 55dddcf1..75de6873 100644 ---- a/config/intdiv0.m4 -+++ b/config/intdiv0.m4 -@@ -56,7 +56,7 @@ int main () - [ - # Guess based on the CPU. - case "$host_cpu" in -- alpha* | i[34567]86 | m68k | s390*) -+ alpha* | sw_64* | i[34567]86 | m68k | s390*) - gt_cv_int_divbyzero_sigfpe="guessing yes";; - *) - gt_cv_int_divbyzero_sigfpe="guessing no";; -diff --git a/config/picflag.m4 b/config/picflag.m4 -index 3f3ac744..3cd3c8b3 100644 ---- a/config/picflag.m4 -+++ b/config/picflag.m4 -@@ -20,6 +20,9 @@ case "${$2}" in - alpha*-dec-osf5*) - # PIC is the default. - ;; -+ sw_64*-dec-osf5*) -+ # PIC is the default. -+ ;; - hppa*64*-*-hpux*) - # PIC is the default for 64-bit PA HP-UX. - ;; -diff --git a/config/tcl.m4 b/config/tcl.m4 -index 4542a4b2..e33d6280 100644 ---- a/config/tcl.m4 -+++ b/config/tcl.m4 -@@ -1368,6 +1368,9 @@ dnl AC_CHECK_TOOL(AR, ar) - if test "`uname -m`" = "alpha" ; then - CFLAGS="$CFLAGS -mieee" - fi -+ if test "`uname -m`" = "sw_64" ; then -+ CFLAGS="$CFLAGS -mieee" -+ fi - if test $do64bit = yes; then - AC_CACHE_CHECK([if compiler accepts -m64 flag], tcl_cv_cc_m64, [ - hold_cflags=$CFLAGS -@@ -1415,8 +1418,7 @@ dnl AC_CHECK_TOOL(AR, ar) - CC_SEARCH_FLAGS="" - LD_SEARCH_FLAGS=""]) - fi -- if test "`uname -m`" = "alpha" ; then -- CFLAGS="$CFLAGS -mieee" -+ if test "`uname -m`" = "alpha" ; then CFLAGS="$CFLAGS -mieee" - fi - ;; - Lynx*) -diff --git a/configure b/configure -index 9cb953a1..cb344197 100755 ---- a/configure -+++ b/configure -@@ -792,6 +792,7 @@ ac_subst_files='serialization_dependencies - host_makefile_frag - target_makefile_frag - alphaieee_frag -+sw_64ieee_frag - ospace_frag' - ac_user_opts=' - enable_option_checking -@@ -3736,6 +3737,9 @@ case "${target}" in - alpha*-dec-osf*) - noconfigdirs="$noconfigdirs target-newlib target-libgloss" - ;; -+ sw_64*-dec-osf*) -+ noconfigdirs="$noconfigdirs target-newlib target-libgloss" -+ ;; - i[3456789]86-*-linux*) - # This section makes it possible to build newlib natively on linux. - # If we are using a cross compiler then don't configure newlib. -@@ -3877,6 +3881,15 @@ case "${target}" in - bpf-*-*) - noconfigdirs="$noconfigdirs target-libobjc target-libbacktrace" - ;; -+ sw_64*-dec-osf*) -+ # ld works, but does not support shared libraries. -+ # gas doesn't generate exception information. -+ noconfigdirs="$noconfigdirs gas ld" -+ ;; -+ sw_64*-*-*) -+ # newlib is not 64 bit ready -+ noconfigdirs="$noconfigdirs target-newlib target-libgloss" -+ ;; - sh*-*-pe|mips*-*-pe|*arm-wince-pe) - noconfigdirs="$noconfigdirs tcl tk itcl libgui sim" - ;; -@@ -4145,6 +4158,9 @@ fi - alpha*-linux*) - host_makefile_frag="config/mh-alpha-linux" - ;; -+ sw_64*-linux*) -+ host_makefile_frag="config/mh-sw_64-linux" -+ ;; - hppa*-hp-hpux10*) - host_makefile_frag="config/mh-pa-hpux10" - ;; -@@ -8703,7 +8719,7 @@ target_elf=no - case $target in - *-darwin* | *-aix* | *-cygwin* | *-mingw* | *-aout* | *-*coff* | \ - *-msdosdjgpp* | *-vms* | *-wince* | *-*-pe* | \ -- alpha*-dec-osf* | *-interix* | hppa[12]*-*-hpux* | \ -+ alpha*-dec-osf* | sw_64*-dec-osf* | *-interix* | hppa[12]*-*-hpux* | \ - nvptx-*-none) - target_elf=no - ;; -@@ -9686,6 +9702,15 @@ case $target in - ;; - esac - -+sw_64ieee_frag=/dev/null -+case $target in -+ sw_64*-*-*) -+ # This just makes sure to use the -mieee option to build target libs. -+ # This should probably be set individually by each library. -+ sw_64ieee_frag="config/mt-sw_64ieee" -+ ;; -+esac -+ - # If --enable-target-optspace always use -Os instead of -O2 to build - # the target libraries, similarly if it is not specified, use -Os - # on selected platforms. -@@ -10418,7 +10443,7 @@ case "${target}" in - esac - - # Makefile fragments. --for frag in host_makefile_frag target_makefile_frag alphaieee_frag ospace_frag; -+for frag in host_makefile_frag target_makefile_frag alphaieee_frag sw_64ieee_frag ospace_frag; - do - eval fragval=\$$frag - if test $fragval != /dev/null; then -diff --git a/configure.ac b/configure.ac -index 2f740926..d0ebb2da 100644 ---- a/configure.ac -+++ b/configure.ac -@@ -969,6 +969,9 @@ case "${target}" in - alpha*-dec-osf*) - noconfigdirs="$noconfigdirs target-newlib target-libgloss" - ;; -+ sw_64*-dec-osf*) -+ noconfigdirs="$noconfigdirs target-newlib target-libgloss" -+ ;; - i[[3456789]]86-*-linux*) - # This section makes it possible to build newlib natively on linux. - # If we are using a cross compiler then don't configure newlib. -@@ -1110,6 +1113,15 @@ case "${target}" in - bpf-*-*) - noconfigdirs="$noconfigdirs target-libobjc target-libbacktrace" - ;; -+ sw_64*-dec-osf*) -+ # ld works, but does not support shared libraries. -+ # gas doesn't generate exception information. -+ noconfigdirs="$noconfigdirs gas ld" -+ ;; -+ sw_64*-*-*) -+ # newlib is not 64 bit ready -+ noconfigdirs="$noconfigdirs target-newlib target-libgloss" -+ ;; - sh*-*-pe|mips*-*-pe|*arm-wince-pe) - noconfigdirs="$noconfigdirs tcl tk itcl libgui sim" - ;; -@@ -1359,6 +1371,9 @@ case "${host}" in - alpha*-linux*) - host_makefile_frag="config/mh-alpha-linux" - ;; -+ sw_64*-linux*) -+ host_makefile_frag="config/mh-sw_64-linux" -+ ;; - hppa*-hp-hpux10*) - host_makefile_frag="config/mh-pa-hpux10" - ;; -@@ -2824,6 +2839,15 @@ case $target in - ;; - esac - -+sw_64ieee_frag=/dev/null -+case $target in -+ sw_64*-*-*) -+ # This just makes sure to use the -mieee option to build target libs. -+ # This should probably be set individually by each library. -+ sw_64ieee_frag="config/mt-sw_64ieee" -+ ;; -+esac -+ - # If --enable-target-optspace always use -Os instead of -O2 to build - # the target libraries, similarly if it is not specified, use -Os - # on selected platforms. -@@ -3551,7 +3575,7 @@ case "${target}" in - esac - - # Makefile fragments. --for frag in host_makefile_frag target_makefile_frag alphaieee_frag ospace_frag; -+for frag in host_makefile_frag target_makefile_frag alphaieee_frag sw_64ieee_frag ospace_frag; - do - eval fragval=\$$frag - if test $fragval != /dev/null; then -@@ -3561,6 +3585,7 @@ done - AC_SUBST_FILE(host_makefile_frag) - AC_SUBST_FILE(target_makefile_frag) - AC_SUBST_FILE(alphaieee_frag) -+AC_SUBST_FILE(sw_64ieee_frag) - AC_SUBST_FILE(ospace_frag) - - # Miscellanea: directories, flags, etc. -diff --git a/gas/Makefile.am b/gas/Makefile.am -index f8770e83..1f6a38fa 100644 ---- a/gas/Makefile.am -+++ b/gas/Makefile.am -@@ -138,6 +138,7 @@ HFILES = \ - TARGET_CPU_CFILES = \ - config/tc-aarch64.c \ - config/tc-alpha.c \ -+ config/tc-sw_64.c \ - config/tc-arc.c \ - config/tc-arm.c \ - config/tc-avr.c \ -@@ -213,6 +214,7 @@ TARGET_CPU_CFILES = \ - TARGET_CPU_HFILES = \ - config/tc-aarch64.h \ - config/tc-alpha.h \ -+ config/tc-sw_64.h \ - config/tc-arc.h \ - config/tc-arm.h \ - config/tc-avr.h \ -diff --git a/gas/Makefile.in b/gas/Makefile.in -index 427f42df..78248678 100644 ---- a/gas/Makefile.in -+++ b/gas/Makefile.in -@@ -625,6 +625,7 @@ HFILES = \ - TARGET_CPU_CFILES = \ - config/tc-aarch64.c \ - config/tc-alpha.c \ -+ config/tc-sw_64.c \ - config/tc-arc.c \ - config/tc-arm.c \ - config/tc-avr.c \ -@@ -700,6 +701,7 @@ TARGET_CPU_CFILES = \ - TARGET_CPU_HFILES = \ - config/tc-aarch64.h \ - config/tc-alpha.h \ -+ config/tc-sw_64.h \ - config/tc-arc.h \ - config/tc-arm.h \ - config/tc-avr.h \ -@@ -1084,6 +1086,8 @@ config/tc-aarch64.$(OBJEXT): config/$(am__dirstamp) \ - config/$(DEPDIR)/$(am__dirstamp) - config/tc-alpha.$(OBJEXT): config/$(am__dirstamp) \ - config/$(DEPDIR)/$(am__dirstamp) -+config/tc-sw_64.$(OBJEXT): config/$(am__dirstamp) \ -+ config/$(DEPDIR)/$(am__dirstamp) - config/tc-arc.$(OBJEXT): config/$(am__dirstamp) \ - config/$(DEPDIR)/$(am__dirstamp) - config/tc-arm.$(OBJEXT): config/$(am__dirstamp) \ -@@ -1360,6 +1364,7 @@ distclean-compile: - @AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/rx-parse.Po@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-aarch64.Po@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-alpha.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-sw_64.Po@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-arc.Po@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-arm.Po@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-avr.Po@am__quote@ -diff --git a/gas/as.c b/gas/as.c -index 6839c841..844b85fe 100644 ---- a/gas/as.c -+++ b/gas/as.c -@@ -57,6 +57,9 @@ - extern void gas_cgen_begin (void); - #endif - -+expressionS toksave[5]; -+int nop_quantity=0; -+ - /* We build a list of defsyms as we read the options, and then define - them after we have initialized everything. */ - struct defsym_list -@@ -511,6 +514,7 @@ parse_args (int * pargc, char *** pargv) - OPTION_NOCOMPRESS_DEBUG, - OPTION_NO_PAD_SECTIONS, - OPTION_MULTIBYTE_HANDLING, /* = STD_BASE + 40 */ -+ OPTION_ORG_BACKWARDS, - OPTION_SFRAME - /* When you add options here, check that they do - not collide with OPTION_MD_BASE. See as.h. */ -@@ -594,6 +598,7 @@ parse_args (int * pargc, char *** pargv) - ,{"traditional-format", no_argument, NULL, OPTION_TRADITIONAL_FORMAT} - ,{"warn", no_argument, NULL, OPTION_WARN} - ,{"multibyte-handling", required_argument, NULL, OPTION_MULTIBYTE_HANDLING} -+ ,{"pal", no_argument, NULL, OPTION_ORG_BACKWARDS} - }; - - /* Construct the option lists from the standard list and the target -@@ -696,6 +701,12 @@ parse_args (int * pargc, char *** pargv) - flag_traditional_format = 1; - break; - -+#ifdef TARGET_SW_64 -+ case OPTION_ORG_BACKWARDS: -+ pal_org_backwrards =1; -+ break; -+#endif -+ - case OPTION_MULTIBYTE_HANDLING: - if (strcmp (optarg, "allow") == 0) - multibyte_handling = multibyte_allow; -diff --git a/gas/as.h b/gas/as.h -index 99ffe77a..aa11891b 100644 ---- a/gas/as.h -+++ b/gas/as.h -@@ -361,6 +361,11 @@ COMMON int linkrelax; - - COMMON int do_not_pad_sections_to_alignment; - -+#ifdef TARGET_SW_64 -+/* Support -pal for hmcode. */ -+COMMON int pal_org_backwrards; -+#endif -+ - enum multibyte_input_handling - { - multibyte_allow = 0, -diff --git a/gas/config.in b/gas/config.in -index 232bc350..878e1b5b 100644 ---- a/gas/config.in -+++ b/gas/config.in -@@ -331,3 +331,11 @@ - - /* Define to 1 if you need to in order for `stat' and other things to work. */ - #undef _POSIX_SOURCE -+ -+/* Default CPU for SW_64 targets. */ -+#undef SW_CPU_STRING_DEFAULT -+ -+/* Define Git verion for elf flags. */ -+#undef GIT_REVISION -+ -+#undef TARGET_SW_64 -diff --git a/gas/config/obj-ecoff.c b/gas/config/obj-ecoff.c -index 26da2af0..1409727b 100644 ---- a/gas/config/obj-ecoff.c -+++ b/gas/config/obj-ecoff.c -@@ -128,6 +128,16 @@ ecoff_frob_file_before_fix (void) - fprmask = alpha_fprmask; - #endif - -+#ifdef TC_SW_64 -+ sw_64_frob_ecoff_data (); -+ -+ if (!bfd_ecoff_set_gp_value (stdoutput, sw_64_gp_value)) -+ as_fatal (_ ("Can't set GP value")); -+ -+ gprmask = sw_64_gprmask; -+ fprmask = sw_64_fprmask; -+#endif -+ - if (! bfd_ecoff_set_regmasks (stdoutput, gprmask, fprmask, cprmask)) - as_fatal (_("Can't set register masks")); - } -diff --git a/gas/config/obj-elf.c b/gas/config/obj-elf.c -index 753a929f..d59612a8 100644 ---- a/gas/config/obj-elf.c -+++ b/gas/config/obj-elf.c -@@ -40,6 +40,12 @@ - #include "elf/alpha.h" - #endif - -+#ifdef TARGET_SW_64 -+#ifdef TC_SW_64 -+#include "elf/sw_64.h" -+#endif -+#endif -+ - #ifdef TC_MIPS - #include "elf/mips.h" - #endif -diff --git a/gas/config/obj-elf.h b/gas/config/obj-elf.h -index e8fc3126..e09a6760 100644 ---- a/gas/config/obj-elf.h -+++ b/gas/config/obj-elf.h -@@ -42,6 +42,11 @@ - extern int alpha_flag_mdebug; - #endif - -+#ifdef TC_SW_64 -+#define ECOFF_DEBUGGING (sw_64_flag_mdebug > 0) -+extern int sw_64_flag_mdebug; -+#endif -+ - /* For now, always set ECOFF_DEBUGGING for a MIPS target. */ - #ifdef TC_MIPS - #define ECOFF_DEBUGGING mips_flag_mdebug -diff --git a/gas/config/tc-sw_64.c b/gas/config/tc-sw_64.c -new file mode 100644 -index 00000000..1893ec4d ---- /dev/null -+++ b/gas/config/tc-sw_64.c -@@ -0,0 +1,7142 @@ -+/* tc-sw_64.c - Processor-specific code for the Sw_64 AXP CPU. -+ Copyright (C) 1989-2023 Free Software Foundation, Inc. -+ Contributed by Carnegie Mellon University, 1993. -+ Written by Alessandro Forin, based on earlier gas-1.38 target CPU files. -+ Modified by Ken Raeburn for gas-2.x and ECOFF support. -+ Modified by Richard Henderson for ELF support. -+ Modified by Klaus K"ampf for EVAX (OpenVMS/Sw_64) support. -+ -+ This file is part of GAS, the GNU Assembler. -+ -+ GAS is free software; you can redistribute it and/or modify -+ it under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 3, or (at your option) -+ any later version. -+ -+ GAS is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ GNU General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with GAS; see the file COPYING. If not, write to the Free -+ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA -+ 02110-1301, USA. */ -+ -+/* Mach Operating System -+ Copyright (c) 1993 Carnegie Mellon University -+ All Rights Reserved. -+ -+ Permission to use, copy, modify and distribute this software and its -+ documentation is hereby granted, provided that both the copyright -+ notice and this permission notice appear in all copies of the -+ software, derivative works or modified versions, and any portions -+ thereof, and that both notices appear in supporting documentation. -+ -+ CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS -+ CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR -+ ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. -+ -+ Carnegie Mellon requests users of this software to return to -+ -+ Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU -+ School of Computer Science -+ Carnegie Mellon University -+ Pittsburgh PA 15213-3890 -+ -+ any improvements or extensions that they make and grant Carnegie the -+ rights to redistribute these changes. */ -+ -+#include "as.h" -+#include "subsegs.h" -+#include "ecoff.h" -+ -+#include "opcode/sw_64.h" -+ -+#ifdef OBJ_ELF -+#include "elf/sw_64.h" -+#endif -+ -+#ifdef OBJ_EVAX -+#include "vms.h" -+#include "vms/egps.h" -+#endif -+ -+#include "dwarf2dbg.h" -+#include "dw2gencfi.h" -+#include "safe-ctype.h" -+ -+/* Local types. */ -+ -+#define TOKENIZE_ERROR -1 -+#define TOKENIZE_ERROR_REPORT -2 -+#define MAX_INSN_FIXUPS 2 -+#define MAX_INSN_ARGS 5 -+ -+/* Used since new relocation types are introduced in this -+ file (DUMMY_RELOC_LITUSE_*) */ -+typedef int extended_bfd_reloc_code_real_type; -+ -+struct sw_64_fixup -+{ -+ expressionS exp; -+ /* bfd_reloc_code_real_type reloc; */ -+ extended_bfd_reloc_code_real_type reloc; -+#ifdef OBJ_EVAX -+ /* The symbol of the item in the linkage section. */ -+ symbolS *xtrasym; -+ -+ /* The symbol of the procedure descriptor. */ -+ symbolS *procsym; -+#endif -+}; -+ -+struct sw_64_insn -+{ -+ unsigned insn; -+ int nfixups; -+ struct sw_64_fixup fixups[MAX_INSN_FIXUPS]; -+ long sequence; -+}; -+ -+enum sw_64_macro_arg -+{ -+ MACRO_EOA = 1, -+ MACRO_IR, -+ MACRO_PIR, -+ MACRO_OPIR, -+ MACRO_CPIR, -+ MACRO_FPR, -+ MACRO_EXP -+}; -+ -+struct sw_64_macro -+{ -+ const char *name; -+ void (*emit) (const expressionS *, int, const void *); -+ const void *arg; -+ enum sw_64_macro_arg argsets[16]; -+}; -+ -+/* Extra expression types. */ -+ -+#define O_pregister O_md1 /* O_register, in parentheses. */ -+#define O_cpregister O_md2 /* + a leading comma. */ -+ -+/* The sw_64_reloc_op table below depends on the ordering of these. */ -+#define O_literal O_md3 /* !literal relocation. */ -+#define O_lituse_addr O_md4 /* !lituse_addr relocation. */ -+#define O_lituse_base O_md5 /* !lituse_base relocation. */ -+#define O_lituse_bytoff O_md6 /* !lituse_bytoff relocation. */ -+#define O_lituse_jsr O_md7 /* !lituse_jsr relocation. */ -+#define O_lituse_tlsgd O_md8 /* !lituse_tlsgd relocation. */ -+#define O_lituse_tlsldm O_md9 /* !lituse_tlsldm relocation. */ -+#define O_lituse_jsrdirect O_md10 /* !lituse_jsrdirect relocation. */ -+#define O_gpdisp O_md11 /* !gpdisp relocation. */ -+#define O_gprelhigh O_md12 /* !gprelhigh relocation. */ -+#define O_gprellow O_md13 /* !gprellow relocation. */ -+#define O_gprel O_md14 /* !gprel relocation. */ -+#define O_samegp O_md15 /* !samegp relocation. */ -+#define O_tlsgd O_md16 /* !tlsgd relocation. */ -+#define O_tlsldm O_md17 /* !tlsldm relocation. */ -+#define O_gotdtprel O_md18 /* !gotdtprel relocation. */ -+#define O_dtprelhi O_md19 /* !dtprelhi relocation. */ -+#define O_dtprello O_md20 /* !dtprello relocation. */ -+#define O_dtprel O_md21 /* !dtprel relocation. */ -+#define O_gottprel O_md22 /* !gottprel relocation. */ -+#define O_tprelhi O_md23 /* !tprelhi relocation. */ -+#define O_tprello O_md24 /* !tprello relocation. */ -+#define O_tprel O_md25 /* !tprel relocation. */ -+#define O_tlsrel_got O_md26 /* !tlsrel_got relocation. */ -+#define O_literal_got O_md27 /* !literal_got relocation. */ -+ -+#define DUMMY_RELOC_LITUSE_ADDR (BFD_RELOC_UNUSED + 1) -+#define DUMMY_RELOC_LITUSE_BASE (BFD_RELOC_UNUSED + 2) -+#define DUMMY_RELOC_LITUSE_BYTOFF (BFD_RELOC_UNUSED + 3) -+#define DUMMY_RELOC_LITUSE_JSR (BFD_RELOC_UNUSED + 4) -+#define DUMMY_RELOC_LITUSE_TLSGD (BFD_RELOC_UNUSED + 5) -+#define DUMMY_RELOC_LITUSE_TLSLDM (BFD_RELOC_UNUSED + 6) -+#define DUMMY_RELOC_LITUSE_JSRDIRECT (BFD_RELOC_UNUSED + 7) -+ -+#define USER_RELOC_P(R) ((R) >= O_literal && (R) <= O_literal_got) -+/* Macros for extracting the type and number of encoded register tokens. */ -+ -+#define is_ir_num(x) (((x) &32) == 0) -+#define is_fpr_num(x) (((x) &32) != 0) -+#define regno(x) ((x) &31) -+ -+/* Something odd inherited from the old assembler. */ -+ -+#define note_gpreg(R) (sw_64_gprmask |= (1 << (R))) -+#define note_fpreg(R) (sw_64_fprmask |= (1 << (R))) -+ -+/* Predicates for 16- and 32-bit ranges. */ -+/* XXX: The non-shift version appears to trigger a compiler bug when -+ cross-assembling from x86 w/ gcc 2.7.2. */ -+ -+#if 1 -+#define range_signed_16(x) \ -+ (((offsetT) (x) >> 15) == 0 || ((offsetT) (x) >> 15) == -1) -+#define range_signed_32(x) \ -+ (((offsetT) (x) >> 31) == 0 || ((offsetT) (x) >> 31) == -1) -+#else -+#define range_signed_16(x) \ -+ ((offsetT) (x) >= -(offsetT) 0x8000 && (offsetT) (x) <= (offsetT) 0x7FFF) -+#define range_signed_32(x) \ -+ ((offsetT) (x) >= -(offsetT) 0x80000000 \ -+ && (offsetT) (x) <= (offsetT) 0x7FFFFFFF) -+#endif -+ -+/* Macros for sign extending from 16- and 32-bits. */ -+/* XXX: The cast macros will work on all the systems that I care about, -+ but really a predicate should be found to use the non-cast forms. */ -+ -+#define sign_extend_16(x) ((short) (x)) -+#define sign_extend_32(x) ((int) (x)) -+ -+/* Macros to build tokens. */ -+ -+#define set_tok_reg(t, r) \ -+ (memset (&(t), 0, sizeof (t)), (t).X_op = O_register, (t).X_add_number = (r)) -+#define set_tok_preg(t, r) \ -+ (memset (&(t), 0, sizeof (t)), (t).X_op = O_pregister, (t).X_add_number = (r)) -+#define set_tok_cpreg(t, r) \ -+ (memset (&(t), 0, sizeof (t)), (t).X_op = O_cpregister, \ -+ (t).X_add_number = (r)) -+#define set_tok_freg(t, r) \ -+ (memset (&(t), 0, sizeof (t)), (t).X_op = O_register, \ -+ (t).X_add_number = (r) + 32) -+#define set_tok_sym(t, s, a) \ -+ (memset (&(t), 0, sizeof (t)), (t).X_op = O_symbol, (t).X_add_symbol = (s), \ -+ (t).X_add_number = (a)) -+#define set_tok_const(t, n) \ -+ (memset (&(t), 0, sizeof (t)), (t).X_op = O_constant, (t).X_add_number = (n)) -+ -+/* Generic assembler global variables which must be defined by all -+ targets. */ -+ -+/* Characters which always start a comment. */ -+const char comment_chars[] = "#"; -+ -+/* Characters which start a comment at the beginning of a line. */ -+const char line_comment_chars[] = "#"; -+ -+/* Characters which may be used to separate multiple commands on a -+ single line. */ -+const char line_separator_chars[] = ";"; -+ -+/* Characters which are used to indicate an exponent in a floating -+ point number. */ -+const char EXP_CHARS[] = "eE"; -+ -+/* Characters which mean that a number is a floating point constant, -+ as in 0d1.0. */ -+/* XXX: Do all of these really get used on the sw_64?? */ -+const char FLT_CHARS[] = "rRsSfFdDxXpP"; -+ -+extern expressionS toksave[MAX_INSN_ARGS]; -+extern int nop_quantity; -+static int sw_64_branch_separate = 0; -+ -+/* The argument of the -march= flag. The architecture we are assembling. */ -+static int file_sw_64_arch = CPU_UNKNOWN; -+static const char *sw_64_arch_string; -+ -+extern fixS *frags_pre_fixup; -+ -+struct sw_64_cpu_info -+{ -+ const char *name; /* CPU or ISA name. */ -+ int flags; /* SW_64_CPU_* flags. */ -+ int ase; /* Set of ASEs implemented by the CPU. */ -+ int isa; /* ISA level. */ -+ int cpu; /* CPU number (default CPU if ISA). */ -+}; -+ -+#define SW_64_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */ -+ -+struct sw_64_set_options -+{ -+ int isa; -+ int ase; -+ int sw_64_tmp; -+ int micromips; -+ int noreorder; -+ unsigned int at; -+ int warn_about_macros; -+ int nomove; -+ int nobopt; -+ int noautoextend; -+ bfd_boolean insn32; -+ int gp32; -+ int fp32; -+ int arch; -+ bfd_boolean sym32; -+ bfd_boolean soft_float; -+ bfd_boolean single_float; -+}; -+ -+static struct sw_64_set_options sw_64_opts = { -+ /* isa */ ISA_UNKNOWN, -+ /* ase */ 0, -+ /* sw_64_tmp */ -1, -+ /* micromips */ -1, -+ /* noreorder */ 0, -+ /* at */ FALSE, -+ /* warn_about_macros */ 0, -+ /* nomove */ 0, -+ /* nobopt */ 0, -+ /* noautoextend */ 0, -+ /* insn32 */ FALSE, -+ /* gp32 */ 0, -+ /* fp32 */ 0, -+ /* arch */ CPU_UNKNOWN, -+ /* sym32 */ FALSE, -+ /* soft_float */ FALSE, -+ /* single_float */ FALSE}; -+ -+#ifdef OBJ_EVAX -+const char *md_shortopts = "Fm:g+1h:HG:"; -+#else -+const char *md_shortopts = "Fm:gG:"; -+#endif -+ -+struct option md_longopts[] = { -+#define OPTION_GPREL16 (OPTION_MD_BASE) -+ {"gprel16", no_argument, NULL, OPTION_GPREL16}, -+#define OPTION_LITERALGOT (OPTION_GPREL16 + 1) -+ {"literalgot", no_argument, NULL, OPTION_LITERALGOT}, -+#define OPTION_TLSRELGOT_GOTTPREL (OPTION_LITERALGOT + 1) -+ {"tlsrelgot_gottprel", no_argument, NULL, OPTION_TLSRELGOT_GOTTPREL}, -+#define OPTION_TLSRELGOT_GOTDTPREL (OPTION_TLSRELGOT_GOTTPREL + 1) -+ {"tlsrelgot_gotdtprel", no_argument, NULL, OPTION_TLSRELGOT_GOTDTPREL}, -+#define OPTION_TLSRELGOT_TLSLDM (OPTION_TLSRELGOT_GOTDTPREL + 1) -+ {"tlsrelgot_tlsldm", no_argument, NULL, OPTION_TLSRELGOT_TLSLDM}, -+#define OPTION_TLSRELGOT_TLSGD (OPTION_TLSRELGOT_TLSLDM + 1) -+ {"tlsrelgot_tlsgd", no_argument, NULL, OPTION_TLSRELGOT_TLSGD}, -+#define OPTION_32ADDR (OPTION_TLSRELGOT_TLSGD + 1) -+ {"32addr", no_argument, NULL, OPTION_32ADDR}, -+#define OPTION_NOCHECK_SAMEREG (OPTION_32ADDR + 1) -+ {"nocheck-samereg", no_argument, NULL, OPTION_NOCHECK_SAMEREG}, -+#define OPTION_RELAX (OPTION_NOCHECK_SAMEREG + 1) -+ {"relax", no_argument, NULL, OPTION_RELAX}, -+#ifdef OBJ_ELF -+#define OPTION_MDEBUG (OPTION_RELAX + 1) -+#define OPTION_NO_MDEBUG (OPTION_MDEBUG + 1) -+ {"mdebug", no_argument, NULL, OPTION_MDEBUG}, -+ {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, -+#endif -+#ifdef OBJ_EVAX -+#define OPTION_REPLACE (OPTION_RELAX + 1) -+#define OPTION_NOREPLACE (OPTION_REPLACE + 1) -+ {"replace", no_argument, NULL, OPTION_REPLACE}, -+ {"noreplace", no_argument, NULL, OPTION_NOREPLACE}, -+#endif -+#define OPTION_BRANCH_SEPARATE (OPTION_RELAX + 3) -+#define OPTION_NOBRANCH_SEPARATE (OPTION_RELAX + 4) -+ {"branch-separate", no_argument, NULL, OPTION_BRANCH_SEPARATE}, -+ {"nobranch-separate", no_argument, NULL, OPTION_NOBRANCH_SEPARATE}, -+ {NULL, no_argument, NULL, 0}}; -+ -+size_t md_longopts_size = sizeof (md_longopts); -+ -+#ifdef OBJ_EVAX -+#define AXP_REG_R0 0 -+#define AXP_REG_R16 16 -+#define AXP_REG_R17 17 -+#undef AXP_REG_T9 -+#define AXP_REG_T9 22 -+#undef AXP_REG_T10 -+#define AXP_REG_T10 23 -+#undef AXP_REG_T11 -+#define AXP_REG_T11 24 -+#undef AXP_REG_T12 -+#define AXP_REG_T12 25 -+#define AXP_REG_AI 25 -+#undef AXP_REG_FP -+#define AXP_REG_FP 29 -+ -+#undef AXP_REG_GP -+#define AXP_REG_GP AXP_REG_PV -+ -+#endif /* OBJ_EVAX */ -+ -+/* The cpu for which we are generating code. */ -+static unsigned sw_64_target; -+static const char *sw_64_target_name; -+ -+/* The hash table of instruction opcodes. */ -+static htab_t sw_64_opcode_hash; -+ -+/* The hash table of macro opcodes. */ -+static htab_t sw_64_macro_hash; -+ -+#ifdef OBJ_ECOFF -+/* The $gp relocation symbol. */ -+static symbolS *sw_64_gp_symbol; -+ -+/* XXX: what is this, and why is it exported? */ -+valueT sw_64_gp_value; -+#endif -+ -+/* The current $gp register. */ -+static int sw_64_gp_register = AXP_REG_GP; -+ -+/* A table of the register symbols. */ -+static symbolS *sw_64_register_table[64]; -+ -+/* Constant sections, or sections of constants. */ -+#ifdef OBJ_ECOFF -+static segT sw_64_lita_section; -+#endif -+#ifdef OBJ_EVAX -+segT sw_64_link_section; -+#endif -+#ifndef OBJ_EVAX -+static segT sw_64_lit8_section; -+#endif -+ -+/* Symbols referring to said sections. */ -+#ifdef OBJ_ECOFF -+static symbolS *sw_64_lita_symbol; -+#endif -+#ifdef OBJ_EVAX -+static symbolS *sw_64_link_symbol; -+#endif -+#ifndef OBJ_EVAX -+static symbolS *sw_64_lit8_symbol; -+#endif -+ -+/* Literal for .litX+0x8000 within .lita. */ -+#ifdef OBJ_ECOFF -+static offsetT sw_64_lit8_literal; -+#endif -+ -+/* Is the assembler not allowed to use $at? */ -+static int sw_64_noat_on = 0; -+ -+/* Are macros enabled? */ -+static int sw_64_macros_on = 1; -+ -+/* Are floats disabled? */ -+static int sw_64_nofloats_on = 0; -+ -+/* Are addresses 32 bit? */ -+static int sw_64_addr32_on = 0; -+ -+/* Insert ldih instruction with tlsrel_got relocation before ldi instruction -+ * with tlsgd relocation. */ -+static int sw_64_tlsrelgot_tlsgd_on = 0; -+ -+/* Insert ldih instruction with tlsrel_got relocation before ldi instruction -+ * with tlsldm relocation. */ -+static int sw_64_tlsrelgot_tlsldm_on = 0; -+ -+/* Insert ldih instruction with literal_got relocation before ldl instruction -+ * with literal relocation. */ -+static int sw_64_literalgot_on = 1; -+ -+/* Change gprel16 relocation to gprelhi+gprello relocation with ldih insn and -+ * ldi/ldw/flds/fldd insn. */ -+static int sw_64_gprel16_on = 0; -+ -+/* Insert ldih instruction with tlsrel_got relocation before ldl instruction -+ * with gottprel relocation. */ -+static int sw_64_tlsrelgot_gottprel_on = 0; -+ -+/* Insert ldih instruction with tlsrel_got relocation before ldl instruction -+ * with gotdtprel relocation. */ -+static int sw_64_tlsrelgot_gotdtprel_on = 0; -+ -+/* Symbol labelling the current insn. When the Sw_64 gas sees -+ foo: -+ .quad 0 -+ and the section happens to not be on an eight byte boundary, it -+ will align both the symbol and the .quad to an eight byte boundary. */ -+static symbolS *sw_64_insn_label; -+#if defined (OBJ_ELF) || defined (OBJ_EVAX) -+static symbolS *sw_64_prologue_label; -+#endif -+ -+#ifdef OBJ_EVAX -+/* Symbol associate with the current call instruction. */ -+static symbolS *sw_64_linkage_symbol; -+#endif -+ -+/* Whether we should automatically align data generation pseudo-ops. -+ .align 0 will turn this off. */ -+static int sw_64_auto_align_on = 1; -+ -+/* The known current alignment of the current section. */ -+static int sw_64_current_align; -+ -+/* These are exported to ECOFF code. */ -+unsigned long sw_64_gprmask, sw_64_fprmask; -+ -+/* Whether the debugging option was seen. */ -+static int sw_64_debug; -+ -+#ifdef OBJ_ELF -+/* Whether we are emitting an mdebug section. */ -+int sw_64_flag_mdebug = -1; -+#endif -+ -+#ifdef OBJ_EVAX -+/* Whether to perform the VMS procedure call optimization. */ -+int sw_64_flag_replace = 1; -+#endif -+ -+/* Don't fully resolve relocations, allowing code movement in the linker. */ -+static int sw_64_flag_relax; -+ -+/* What value to give to bfd_set_gp_size. */ -+static int g_switch_value = 8; -+ -+static int sw_64_flag_nocheck_samereg = 0; -+ -+#ifdef OBJ_EVAX -+/* Collect information about current procedure here. */ -+struct sw_64_evax_procs -+{ -+ symbolS *symbol; /* Proc pdesc symbol. */ -+ int pdsckind; -+ int framereg; /* Register for frame pointer. */ -+ int framesize; /* Size of frame. */ -+ int rsa_offset; -+ int ra_save; -+ int fp_save; -+ long imask; -+ long fmask; -+ int type; -+ int prologue; -+ symbolS *handler; -+ int handler_data; -+}; -+ -+/* Linked list of .linkage fixups. */ -+struct sw_64_linkage_fixups *sw_64_linkage_fixup_root; -+static struct sw_64_linkage_fixups *sw_64_linkage_fixup_tail; -+ -+/* Current procedure descriptor. */ -+static struct sw_64_evax_procs *sw_64_evax_proc; -+static struct sw_64_evax_procs sw_64_evax_proc_data; -+ -+static int sw_64_flag_hash_long_names = 0; /* -+ */ -+static int sw_64_flag_show_after_trunc = 0; /* -H */ -+ -+/* If the -+ switch is given, then a hash is appended to any name that is -+ longer than 64 characters, else longer symbol names are truncated. */ -+ -+#endif -+ -+#ifdef RELOC_OP_P -+/* A table to map the spelling of a relocation operand into an appropriate -+ bfd_reloc_code_real_type type. The table is assumed to be ordered such -+ that op-O_literal indexes into it. */ -+ -+#define SW_64_RELOC_TABLE(op) \ -+ (&sw_64_reloc_op[((!USER_RELOC_P (op)) ? (abort (), 0) \ -+ : (int) (op) - (int) O_literal)]) -+ -+#define DEF(NAME, RELOC, REQ, ALLOW) \ -+ { \ -+#NAME, sizeof (#NAME) - 1, O_##NAME, RELOC, REQ, ALLOW \ -+ } -+ -+static const struct sw_64_reloc_op_tag -+{ -+ const char *name; /* String to lookup. */ -+ size_t length; /* Size of the string. */ -+ operatorT op; /* Which operator to use. */ -+ extended_bfd_reloc_code_real_type reloc; -+ unsigned int require_seq : 1; /* Require a sequence number. */ -+ unsigned int allow_seq : 1; /* Allow a sequence number. */ -+} sw_64_reloc_op[] = { -+ DEF (literal, BFD_RELOC_SW_64_ELF_LITERAL, 0, 1), -+ DEF (lituse_addr, DUMMY_RELOC_LITUSE_ADDR, 1, 1), -+ DEF (lituse_base, DUMMY_RELOC_LITUSE_BASE, 1, 1), -+ DEF (lituse_bytoff, DUMMY_RELOC_LITUSE_BYTOFF, 1, 1), -+ DEF (lituse_jsr, DUMMY_RELOC_LITUSE_JSR, 1, 1), -+ DEF (lituse_tlsgd, DUMMY_RELOC_LITUSE_TLSGD, 1, 1), -+ DEF (lituse_tlsldm, DUMMY_RELOC_LITUSE_TLSLDM, 1, 1), -+ DEF (lituse_jsrdirect, DUMMY_RELOC_LITUSE_JSRDIRECT, 1, 1), -+ DEF (gpdisp, BFD_RELOC_SW_64_GPDISP, 1, 1), -+ DEF (gprelhigh, BFD_RELOC_SW_64_GPREL_HI16, 0, 0), -+ DEF (gprellow, BFD_RELOC_SW_64_GPREL_LO16, 0, 0), -+ DEF (gprel, BFD_RELOC_GPREL16, 0, 0), -+ DEF (samegp, BFD_RELOC_SW_64_BRSGP, 0, 0), -+ DEF (tlsgd, BFD_RELOC_SW_64_TLSGD, 0, 1), -+ DEF (tlsldm, BFD_RELOC_SW_64_TLSLDM, 0, 1), -+ DEF (gotdtprel, BFD_RELOC_SW_64_GOTDTPREL16, 0, 1), -+ DEF (dtprelhi, BFD_RELOC_SW_64_DTPREL_HI16, 0, 0), -+ DEF (dtprello, BFD_RELOC_SW_64_DTPREL_LO16, 0, 0), -+ DEF (dtprel, BFD_RELOC_SW_64_DTPREL16, 0, 0), -+ DEF (gottprel, BFD_RELOC_SW_64_GOTTPREL16, 0, 1), -+ DEF (tprelhi, BFD_RELOC_SW_64_TPREL_HI16, 0, 0), -+ DEF (tprello, BFD_RELOC_SW_64_TPREL_LO16, 0, 0), -+ DEF (tprel, BFD_RELOC_SW_64_TPREL16, 0, 0), -+ DEF (tlsrel_got, BFD_RELOC_SW_64_TLSREL_GOT, 0, 1), -+ DEF (literal_got, BFD_RELOC_SW_64_ELF_LITERAL_GOT, 0, 1), -+}; -+ -+#undef DEF -+ -+static const int sw_64_num_reloc_op -+ = sizeof (sw_64_reloc_op) / sizeof (*sw_64_reloc_op); -+#endif /* RELOC_OP_P */ -+ -+/* Maximum # digits needed to hold the largest sequence #. */ -+#define SW_64_RELOC_DIGITS 25 -+ -+/* Structure to hold explicit sequence information. */ -+struct sw_64_reloc_tag -+{ -+ fixS *master; /* The literal reloc. */ -+ fixS *tlsrel_got; /* The tlsrel_got reloc. */ -+ fixS *tlsgd; /* The tlsgd reloc. */ -+ fixS *tlsldm; /* The tlsldm reloc. */ -+ fixS *gotdtprel; /* The gotdtprel reloc. */ -+ fixS *gottprel; /* The gottprel reloc. */ -+ fixS *literal_got; /* The literal_got reloc. */ -+ -+#ifdef OBJ_EVAX -+ struct symbol *sym; /* Linkage section item symbol. */ -+ struct symbol *psym; /* Pdesc symbol. */ -+#endif -+ fixS *slaves; /* Head of linked list of lituses. */ -+ segT segment; /* Segment relocs are in or undefined_section. */ -+ long sequence; /* Sequence #. */ -+ unsigned n_master; /* # of literals. */ -+ unsigned n_slaves; /* # of lituses. */ -+ unsigned saw_tlsgd : 1; /* True if ... */ -+ unsigned saw_tlsldm : 1; -+ unsigned saw_lu_tlsgd : 1; -+ unsigned saw_lu_tlsldm : 1; -+ unsigned multi_section_p : 1; /* True if more than one section was used. */ -+ char string[1]; /* Printable form of sequence to hash with. */ -+}; -+ -+/* Hash table to link up literals with the appropriate lituse. */ -+static htab_t sw_64_literal_hash; -+ -+/* Sequence numbers for internal use by macros. */ -+static long next_sequence_num = -1; -+ -+/* A table of CPU names and opcode sets. */ -+ -+static const struct cpu_type -+{ -+ const char *name; -+ unsigned flags; -+} cpu_types[] = {{"sw6a", AXP_OPCODE_SW6 | AXP_OPCODE_SW6A}, -+ {"sw6b", AXP_OPCODE_SW6 | AXP_OPCODE_SW6B}, -+ {"sw8a", AXP_OPCODE_SW6 | AXP_OPCODE_SW8A}, -+ {"sw4e", AXP_OPCODE_SW6 | AXP_OPCODE_SW4E}, -+ -+ {0, 0}}; -+ -+/* Some instruction sets indexed by lg (size). */ -+static const char *const sextX_op[] = {"sextb", "sexth", "sextw", NULL}; -+static const char *const insXl_op[] = {"ins0b", "ins1b", "ins2b", "ins3b"}; -+static const char *const insXh_op[] = {NULL, "ins5b", "ins6b", "ins7b"}; -+static const char *const extXl_op[] = {"ext0b", "ext1b", "ext2b", "ext3b"}; -+static const char *const extXh_op[] = {NULL, "ext5b", "ext6b", "ext7b"}; -+static const char *const mskXl_op[] = {"mask0b", "mask1b", "mask2b", "mask3b"}; -+static const char *const mskXh_op[] = {NULL, "mask5b", "mask6b", "mask7b"}; -+static const char *const stX_op[] = {"stb", "stb", "stw", "stl"}; -+static const char *const ldXu_op[] = {"ldbu", "ldhu", NULL, NULL}; -+ -+static void -+assemble_insn (const struct sw_64_opcode *, const expressionS *, int, -+ struct sw_64_insn *, extended_bfd_reloc_code_real_type); -+static void -+emit_insn (struct sw_64_insn *); -+static void -+assemble_tokens (const char *, expressionS *, int, int); -+#ifdef OBJ_EVAX -+static const char * -+s_sw_64_section_name (void); -+static symbolS * -+add_to_link_pool (symbolS *, offsetT); -+#endif -+ -+static struct sw_64_reloc_tag * -+get_sw_64_reloc_tag (long sequence) -+{ -+ char buffer[SW_64_RELOC_DIGITS]; -+ struct sw_64_reloc_tag *info; -+ -+ sprintf (buffer, "!%ld", sequence); -+ -+ info = (struct sw_64_reloc_tag *) str_hash_find (sw_64_literal_hash, buffer); -+ if (!info) -+ { -+ size_t len = strlen (buffer); -+ -+ info = notes_calloc (sizeof (struct sw_64_reloc_tag) + len, 1); -+ -+ info->segment = now_seg; -+ info->sequence = sequence; -+ strcpy (info->string, buffer); -+ str_hash_insert (sw_64_literal_hash, info->string, info, 0); -+ -+#ifdef OBJ_EVAX -+ info->sym = 0; -+ info->psym = 0; -+#endif -+ } -+ -+ return info; -+} -+ -+#ifndef OBJ_EVAX -+static void -+sw_64_adjust_relocs (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, -+ void *ptr ATTRIBUTE_UNUSED) -+{ -+ segment_info_type *seginfo = seg_info (sec); -+ fixS **prevP; -+ fixS *fixp; -+ fixS *next; -+ fixS *slave; -+ -+ /* If seginfo is NULL, we did not create this section; don't do -+ anything with it. By using a pointer to a pointer, we can update -+ the links in place. */ -+ if (seginfo == NULL) -+ return; -+ -+ /* If there are no relocations, skip the section. */ -+ if (!seginfo->fix_root) -+ return; -+ -+ /* First rebuild the fixup chain without the explicit lituse and -+ gpdisp_lo16 relocs. */ -+ prevP = &seginfo->fix_root; -+ for (fixp = seginfo->fix_root; fixp; fixp = next) -+ { -+ next = fixp->fx_next; -+ fixp->fx_next = (fixS *) 0; -+ -+ switch (fixp->fx_r_type) -+ { -+ case BFD_RELOC_SW_64_LITUSE: -+ if (fixp->tc_fix_data.info->n_master == 0) -+ as_bad_where (fixp->fx_file, fixp->fx_line, -+ _ ("No !literal!%ld was found"), -+ fixp->tc_fix_data.info->sequence); -+#ifdef RELOC_OP_P -+ if (fixp->fx_offset == LITUSE_SW_64_TLSGD) -+ { -+ if (!fixp->tc_fix_data.info->saw_tlsgd) -+ as_bad_where (fixp->fx_file, fixp->fx_line, -+ _ ("No !tlsgd!%ld was found"), -+ fixp->tc_fix_data.info->sequence); -+ } -+ else if (fixp->fx_offset == LITUSE_SW_64_TLSLDM) -+ { -+ if (!fixp->tc_fix_data.info->saw_tlsldm) -+ as_bad_where (fixp->fx_file, fixp->fx_line, -+ _ ("No !tlsldm!%ld was found"), -+ fixp->tc_fix_data.info->sequence); -+ } -+#endif -+ break; -+ -+ case BFD_RELOC_SW_64_GPDISP_LO16: -+ if (fixp->tc_fix_data.info->n_master == 0) -+ as_bad_where (fixp->fx_file, fixp->fx_line, -+ _ ("No ldih !gpdisp!%ld was found"), -+ fixp->tc_fix_data.info->sequence); -+ break; -+ -+ case BFD_RELOC_SW_64_ELF_LITERAL_GOT: -+ if (fixp->tc_fix_data.info) -+ break; -+ *prevP = fixp; -+ prevP = &fixp->fx_next; -+ break; -+ -+ case BFD_RELOC_SW_64_ELF_LITERAL: -+ if (fixp->tc_fix_data.info -+ && (fixp->tc_fix_data.info->saw_tlsgd -+ || fixp->tc_fix_data.info->saw_tlsldm)) -+ break; -+ *prevP = fixp; -+ prevP = &fixp->fx_next; -+ break; -+ -+ case BFD_RELOC_SW_64_TLSREL_GOT: -+ if (fixp->tc_fix_data.info) -+ break; -+ *prevP = fixp; -+ prevP = &fixp->fx_next; -+ break; -+ -+ /* FALLTHRU */ -+ default: -+ *prevP = fixp; -+ prevP = &fixp->fx_next; -+ break; -+ } -+ } -+ -+ /* Go back and re-chain dependent relocations. They are currently -+ linked through the next_reloc field in reverse order, so as we -+ go through the next_reloc chain, we effectively reverse the chain -+ once again. -+ -+ Except if there is more than one !literal for a given sequence -+ number. In that case, the programmer and/or compiler is not sure -+ how control flows from literal to lituse, and we can't be sure to -+ get the relaxation correct. -+ -+ ??? Well, actually we could, if there are enough lituses such that -+ we can make each literal have at least one of each lituse type -+ present. Not implemented. -+ -+ Also suppress the optimization if the !literals/!lituses are spread -+ in different segments. This can happen with "interesting" uses of -+ inline assembly; examples are present in the Linux kernel semaphores. */ -+ -+ fixS *fix_prev = NULL; -+ fixS **orig_prevp_root = &seginfo->fix_root; -+ for (fixp = seginfo->fix_root; fixp; fixp = next) -+ { -+ fixS *fix_master = NULL; -+ fixS *fix_literal_got = NULL; -+ fixS *fix_tlsrel_got = NULL; -+ fixS *fix_tlsldm = NULL; -+ fixS *fix_tlsgd = NULL; -+ fixS *fix_tprel = NULL; -+ fixS *fix_gotdtprel = NULL; -+ fixS *fix_gottprel = NULL; -+ -+ next = fixp->fx_next; -+ switch (fixp->fx_r_type) -+ { -+ case BFD_RELOC_SW_64_TLSGD: -+ case BFD_RELOC_SW_64_TLSLDM: -+ if (!fixp->tc_fix_data.info) -+ { -+ fix_prev = fixp; -+ break; -+ } -+ if (fixp->tc_fix_data.info->n_master == 0) -+ { -+ fix_prev = fixp; -+ break; -+ } -+ else if (fixp->tc_fix_data.info->n_master > 1) -+ { -+ as_bad_where (fixp->fx_file, fixp->fx_line, -+ _ ("too many !literal!%ld for %s"), -+ fixp->tc_fix_data.info->sequence, -+ (fixp->fx_r_type == BFD_RELOC_SW_64_TLSGD -+ ? "!tlsgd" -+ : "!tlsldm")); -+ break; -+ } -+ { -+ fix_tlsrel_got = fixp->tc_fix_data.info->tlsrel_got; -+ fix_tlsldm = fixp->tc_fix_data.info->tlsldm; -+ fix_tlsgd = fixp->tc_fix_data.info->tlsgd; -+ fix_tprel = NULL; -+ -+ if (fixp->tc_fix_data.info->saw_tlsgd && fix_tlsgd -+ && (fixp == fix_tlsgd)) -+ { -+ if (fix_tlsrel_got) -+ { -+ if (fix_prev != NULL) -+ fix_prev->fx_next = fix_tlsrel_got; -+ fix_tlsrel_got->fx_next = fix_tlsgd; -+ if (fixp == *orig_prevp_root) -+ *orig_prevp_root = fix_tlsrel_got; -+ } -+ else -+ { -+ if (fix_prev != NULL) -+ fix_prev->fx_next = fixp; -+ } -+ fix_tprel = fix_tlsgd; -+ } -+ -+ if (fixp->tc_fix_data.info->saw_tlsldm && fix_tlsldm -+ && (fixp == fix_tlsldm)) -+ { -+ if (fix_tlsrel_got) -+ { -+ if (fix_prev != NULL) -+ fix_prev->fx_next = fix_tlsrel_got; -+ fix_tlsrel_got->fx_next = fix_tlsldm; -+ if (fixp == *orig_prevp_root) -+ *orig_prevp_root = fix_tlsrel_got; -+ } -+ else -+ { -+ if (fix_prev != NULL) -+ fix_prev->fx_next = fixp; -+ } -+ fix_tprel = fix_tlsldm; -+ } -+ -+ fixp->tc_fix_data.info->master->fx_next = fixp->fx_next; -+ fixp->fx_next = fixp->tc_fix_data.info->master; -+ fix_prev = fixp; -+ fixp = fixp->fx_next; -+ } -+ /* Fall through. */ -+ -+ case BFD_RELOC_SW_64_ELF_LITERAL: -+ if (fixp->tc_fix_data.info && fixp->tc_fix_data.info->n_master == 1 -+ && !fixp->tc_fix_data.info->multi_section_p) -+ { -+ fix_master = fixp->tc_fix_data.info->master; -+ fix_literal_got = fixp->tc_fix_data.info->literal_got; -+ if (fix_master != fixp) -+ { -+ as_bad_where (fixp->fx_file, fixp->fx_line, -+ _ ("error !literal!%ld"), -+ fixp->tc_fix_data.info->sequence); -+ break; -+ } -+ if (fix_literal_got) -+ { -+ fix_literal_got->fx_next = fixp; -+ if (fix_prev != NULL) -+ fix_prev->fx_next = fix_literal_got; -+ if (fixp == *orig_prevp_root) -+ *orig_prevp_root = fix_literal_got; -+ } -+ else -+ { -+ if (fix_prev != NULL) -+ fix_prev->fx_next = fixp; -+ } -+ -+ fix_prev = fixp; -+ if (fixp->tc_fix_data.info->slaves != ((fixS *) 0)) -+ fix_prev = fixp->tc_fix_data.info->slaves; -+ for (slave = fixp->tc_fix_data.info->slaves; slave != (fixS *) 0; -+ slave = slave->tc_fix_data.next_reloc) -+ { -+ slave->fx_next = fixp->fx_next; -+ fixp->fx_next = slave; -+ } -+ } -+ else -+ { -+ fix_prev = fixp; -+ break; -+ } -+ break; -+ -+ case BFD_RELOC_SW_64_GPDISP_HI16: -+ if (fixp->tc_fix_data.info->n_slaves == 0) -+ as_bad_where (fixp->fx_file, fixp->fx_line, -+ _ ("No ldi !gpdisp!%ld was found"), -+ fixp->tc_fix_data.info->sequence); -+ else -+ { -+ if (fix_prev != NULL) -+ fix_prev->fx_next = fixp; -+ slave = fixp->tc_fix_data.info->slaves; -+ slave->fx_next = next; -+ fixp->fx_next = slave; -+ fix_prev = slave; -+ } -+ break; -+ -+ case BFD_RELOC_SW_64_GOTDTPREL16: -+ if (!fixp->tc_fix_data.info) -+ { -+ fix_prev = fixp; -+ break; -+ } -+ if (fixp->tc_fix_data.info->n_master == 0) -+ { -+ fix_prev = fixp; -+ break; -+ } -+ else if (fixp->tc_fix_data.info->n_master > 1) -+ { -+ as_bad_where (fixp->fx_file, fixp->fx_line, -+ _ ("too many !gotdtprel!%ld"), -+ fixp->tc_fix_data.info->sequence); -+ break; -+ } -+ -+ { -+ fix_tlsrel_got = fixp->tc_fix_data.info->tlsrel_got; -+ fix_gotdtprel = fixp->tc_fix_data.info->gotdtprel; -+ if ((fixp != fix_gotdtprel) -+ || (fixp != fixp->tc_fix_data.info->master)) -+ { -+ as_bad_where (fixp->fx_file, fixp->fx_line, -+ _ ("bad reloc_tag of !gotdtprel!%ld"), -+ fixp->tc_fix_data.info->sequence); -+ break; -+ } -+ if (fix_tlsrel_got) -+ { -+ if (fix_prev != NULL) -+ fix_prev->fx_next = fix_tlsrel_got; -+ fix_tlsrel_got->fx_next = fix_gotdtprel; -+ if (fixp == *orig_prevp_root) -+ *orig_prevp_root = fix_tlsrel_got; -+ } -+ else -+ { -+ if (fix_prev != NULL) -+ fix_prev->fx_next = fixp; -+ } -+ fix_prev = fixp; -+ } -+ break; -+ case BFD_RELOC_SW_64_GOTTPREL16: -+ if (!fixp->tc_fix_data.info) -+ { -+ fix_prev = fixp; -+ break; -+ } -+ if (fixp->tc_fix_data.info->n_master == 0) -+ { -+ fix_prev = fixp; -+ break; -+ } -+ else if (fixp->tc_fix_data.info->n_master > 1) -+ { -+ as_bad_where (fixp->fx_file, fixp->fx_line, -+ _ ("too many !gottprel!%ld"), -+ fixp->tc_fix_data.info->sequence); -+ break; -+ } -+ -+ { -+ fix_tlsrel_got = fixp->tc_fix_data.info->tlsrel_got; -+ fix_gottprel = fixp->tc_fix_data.info->gottprel; -+ if ((fixp != fix_gottprel) -+ || (fixp != fixp->tc_fix_data.info->master)) -+ { -+ as_bad_where (fixp->fx_file, fixp->fx_line, -+ _ ("bad reloc_tag of !gottprel!%ld"), -+ fixp->tc_fix_data.info->sequence); -+ break; -+ } -+ if (fix_tlsrel_got) -+ { -+ if (fix_prev != NULL) -+ fix_prev->fx_next = fix_tlsrel_got; -+ fix_tlsrel_got->fx_next = fix_gottprel; -+ if (fixp == *orig_prevp_root) -+ *orig_prevp_root = fix_tlsrel_got; -+ } -+ else -+ { -+ if (fix_prev != NULL) -+ fix_prev->fx_next = fixp; -+ } -+ fix_prev = fixp; -+ } -+ break; -+ -+ default: -+ fix_prev = fixp; -+ break; -+ } -+ } -+} -+/* Before the relocations are written, reorder them, so that user -+ supplied !lituse relocations follow the appropriate !literal -+ relocations, and similarly for !gpdisp relocations. */ -+ -+void -+sw_64_before_fix (void) -+{ -+ if (sw_64_literal_hash) -+ bfd_map_over_sections (stdoutput, sw_64_adjust_relocs, NULL); -+} -+ -+#endif -+ -+#ifdef DEBUG_SW_64 -+static void -+debug_exp (expressionS tok[], int ntok) -+{ -+ int i; -+ -+ fprintf (stderr, "debug_exp: %d tokens", ntok); -+ for (i = 0; i < ntok; i++) -+ { -+ expressionS *t = &tok[i]; -+ const char *name; -+ -+ switch (t->X_op) -+ { -+ default: -+ name = "unknown"; -+ break; -+ case O_illegal: -+ name = "O_illegal"; -+ break; -+ case O_absent: -+ name = "O_absent"; -+ break; -+ case O_constant: -+ name = "O_constant"; -+ break; -+ case O_symbol: -+ name = "O_symbol"; -+ break; -+ case O_symbol_rva: -+ name = "O_symbol_rva"; -+ break; -+ case O_register: -+ name = "O_register"; -+ break; -+ case O_big: -+ name = "O_big"; -+ break; -+ case O_uminus: -+ name = "O_uminus"; -+ break; -+ case O_bit_not: -+ name = "O_bit_not"; -+ break; -+ case O_logical_not: -+ name = "O_logical_not"; -+ break; -+ case O_multiply: -+ name = "O_multiply"; -+ break; -+ case O_divide: -+ name = "O_divide"; -+ break; -+ case O_modulus: -+ name = "O_modulus"; -+ break; -+ case O_left_shift: -+ name = "O_left_shift"; -+ break; -+ case O_right_shift: -+ name = "O_right_shift"; -+ break; -+ case O_bit_inclusive_or: -+ name = "O_bit_inclusive_or"; -+ break; -+ case O_bit_or_not: -+ name = "O_bit_or_not"; -+ break; -+ case O_bit_exclusive_or: -+ name = "O_bit_exclusive_or"; -+ break; -+ case O_bit_and: -+ name = "O_bit_and"; -+ break; -+ case O_add: -+ name = "O_add"; -+ break; -+ case O_subtract: -+ name = "O_subtract"; -+ break; -+ case O_eq: -+ name = "O_eq"; -+ break; -+ case O_ne: -+ name = "O_ne"; -+ break; -+ case O_lt: -+ name = "O_lt"; -+ break; -+ case O_le: -+ name = "O_le"; -+ break; -+ case O_ge: -+ name = "O_ge"; -+ break; -+ case O_gt: -+ name = "O_gt"; -+ break; -+ case O_logical_and: -+ name = "O_logical_and"; -+ break; -+ case O_logical_or: -+ name = "O_logical_or"; -+ break; -+ case O_index: -+ name = "O_index"; -+ break; -+ case O_pregister: -+ name = "O_pregister"; -+ break; -+ case O_cpregister: -+ name = "O_cpregister"; -+ break; -+ case O_literal: -+ name = "O_literal"; -+ break; -+ case O_lituse_addr: -+ name = "O_lituse_addr"; -+ break; -+ case O_lituse_base: -+ name = "O_lituse_base"; -+ break; -+ case O_lituse_bytoff: -+ name = "O_lituse_bytoff"; -+ break; -+ case O_lituse_jsr: -+ name = "O_lituse_jsr"; -+ break; -+ case O_lituse_tlsgd: -+ name = "O_lituse_tlsgd"; -+ break; -+ case O_lituse_tlsldm: -+ name = "O_lituse_tlsldm"; -+ break; -+ case O_lituse_jsrdirect: -+ name = "O_lituse_jsrdirect"; -+ break; -+ case O_gpdisp: -+ name = "O_gpdisp"; -+ break; -+ case O_gprelhigh: -+ name = "O_gprelhigh"; -+ break; -+ case O_gprellow: -+ name = "O_gprellow"; -+ break; -+ case O_gprel: -+ name = "O_gprel"; -+ break; -+ case O_samegp: -+ name = "O_samegp"; -+ break; -+ case O_tlsgd: -+ name = "O_tlsgd"; -+ break; -+ case O_tlsldm: -+ name = "O_tlsldm"; -+ break; -+ case O_gotdtprel: -+ name = "O_gotdtprel"; -+ break; -+ case O_dtprelhi: -+ name = "O_dtprelhi"; -+ break; -+ case O_dtprello: -+ name = "O_dtprello"; -+ break; -+ case O_dtprel: -+ name = "O_dtprel"; -+ break; -+ case O_gottprel: -+ name = "O_gottprel"; -+ break; -+ case O_tprelhi: -+ name = "O_tprelhi"; -+ break; -+ case O_tprello: -+ name = "O_tprello"; -+ break; -+ case O_tprel: -+ name = "O_tprel"; -+ break; -+ } -+ -+ fprintf (stderr, ", %s (%s, %s, %d)", name, -+ (t->X_add_symbol) ? S_GET_NAME (t->X_add_symbol) : "--", -+ (t->X_op_symbol) ? S_GET_NAME (t->X_op_symbol) : "--", -+ (int) t->X_add_number); -+ } -+ fprintf (stderr, "\n"); -+ fflush (stderr); -+} -+#endif -+ -+/* Parse the arguments to an opcode. */ -+ -+static int -+tokenize_arguments (char *str, expressionS tok[], int ntok) -+{ -+ expressionS *end_tok = tok + ntok; -+ char *old_input_line_pointer; -+ int saw_comma = 0, saw_arg = 0; -+#ifdef DEBUG_SW_64 -+ expressionS *orig_tok = tok; -+#endif -+#ifdef RELOC_OP_P -+ char *p; -+ const struct sw_64_reloc_op_tag *r; -+ int c, i; -+ size_t len; -+ int reloc_found_p = 0; -+#endif -+ -+ memset (tok, 0, sizeof (*tok) * ntok); -+ -+ /* Save and restore input_line_pointer around this function. */ -+ old_input_line_pointer = input_line_pointer; -+ input_line_pointer = str; -+ -+#ifdef RELOC_OP_P -+ /* ??? Wrest control of ! away from the regular expression parser. */ -+ is_end_of_line[(unsigned char) '!'] = 1; -+#endif -+ -+ while (tok < end_tok && *input_line_pointer) -+ { -+ SKIP_WHITESPACE (); -+ switch (*input_line_pointer) -+ { -+ case '\0': -+ goto fini; -+ -+#ifdef RELOC_OP_P -+ case '!': -+ /* A relocation operand can be placed after the normal operand on an -+ assembly language statement, and has the following form: -+ !relocation_type!sequence_number. */ -+ if (reloc_found_p) -+ { -+ /* Only support one relocation op per insn. */ -+ as_bad (_ ("More than one relocation op per insn")); -+ goto err_report; -+ } -+ -+ if (!saw_arg) -+ goto err; -+ -+ ++input_line_pointer; -+ SKIP_WHITESPACE (); -+ c = get_symbol_name (&p); -+ -+ /* Parse !relocation_type. */ -+ len = input_line_pointer - p; -+ if (len == 0) -+ { -+ as_bad (_ ("No relocation operand")); -+ goto err_report; -+ } -+ -+ r = &sw_64_reloc_op[0]; -+ for (i = sw_64_num_reloc_op - 1; i >= 0; i--, r++) -+ if (len == r->length && memcmp (p, r->name, len) == 0) -+ break; -+ if (i < 0) -+ { -+ as_bad (_ ("Unknown relocation operand: !%s"), p); -+ goto err_report; -+ } -+ -+ *input_line_pointer = c; -+ SKIP_WHITESPACE_AFTER_NAME (); -+ if (*input_line_pointer != '!') -+ { -+ if (r->require_seq) -+ { -+ as_bad (_ ("no sequence number after !%s"), p); -+ goto err_report; -+ } -+ -+ tok->X_add_number = 0; -+ } -+ else -+ { -+ if (!r->allow_seq) -+ { -+ as_bad (_ ("!%s does not use a sequence number"), p); -+ goto err_report; -+ } -+ -+ input_line_pointer++; -+ -+ /* Parse !sequence_number. */ -+ expression (tok); -+ if (tok->X_op != O_constant || tok->X_add_number <= 0) -+ { -+ as_bad (_ ("Bad sequence number: !%s!%s"), r->name, -+ input_line_pointer); -+ goto err_report; -+ } -+ } -+ -+ tok->X_op = r->op; -+ reloc_found_p = 1; -+ ++tok; -+ break; -+#endif /* RELOC_OP_P */ -+ -+ case ',': -+ ++input_line_pointer; -+ if (saw_comma || !saw_arg) -+ goto err; -+ saw_comma = 1; -+ break; -+ -+ case '(': { -+ char *hold = input_line_pointer++; -+ -+ /* First try for parenthesized register ... */ -+ expression (tok); -+ resolve_register (tok); -+ if (*input_line_pointer == ')' && tok->X_op == O_register) -+ { -+ tok->X_op = (saw_comma ? O_cpregister : O_pregister); -+ saw_comma = 0; -+ saw_arg = 1; -+ ++input_line_pointer; -+ ++tok; -+ break; -+ } -+ -+ /* ... then fall through to plain expression. */ -+ input_line_pointer = hold; -+ } -+ /* Fall through. */ -+ -+ default: -+ if (saw_arg && !saw_comma) -+ goto err; -+ -+ expression (tok); -+ if (tok->X_op == O_illegal || tok->X_op == O_absent) -+ goto err; -+ -+ resolve_register (tok); -+ -+ saw_comma = 0; -+ saw_arg = 1; -+ ++tok; -+ break; -+ } -+ } -+ -+fini: -+ if (saw_comma) -+ goto err; -+ input_line_pointer = old_input_line_pointer; -+ -+#ifdef DEBUG_SW_64 -+ debug_exp (orig_tok, ntok - (end_tok - tok)); -+#endif -+#ifdef RELOC_OP_P -+ is_end_of_line[(unsigned char) '!'] = 0; -+#endif -+ -+ return ntok - (end_tok - tok); -+ -+err: -+#ifdef RELOC_OP_P -+ is_end_of_line[(unsigned char) '!'] = 0; -+#endif -+ input_line_pointer = old_input_line_pointer; -+ return TOKENIZE_ERROR; -+ -+#ifdef RELOC_OP_P -+err_report: -+ is_end_of_line[(unsigned char) '!'] = 0; -+#endif -+ input_line_pointer = old_input_line_pointer; -+ return TOKENIZE_ERROR_REPORT; -+} -+ -+/* Search forward through all variants of an opcode looking for a -+ syntax match. */ -+ -+static const struct sw_64_opcode * -+find_opcode_match (const struct sw_64_opcode *first_opcode, -+ const expressionS *tok, int *pntok, int *pcpumatch) -+{ -+ const struct sw_64_opcode *opcode = first_opcode; -+ int ntok = *pntok; -+ int got_cpu_match = 0; -+ -+ do -+ { -+ const unsigned char *opidx; -+ int tokidx = 0; -+ -+ /* Don't match opcodes that don't exist on this architecture. */ -+ if (!(opcode->flags & sw_64_target)) -+ goto match_failed; -+ -+ got_cpu_match = 1; -+ -+ for (opidx = opcode->operands; *opidx; ++opidx) -+ { -+ const struct sw_64_operand *operand = &sw_64_operands[*opidx]; -+ -+ /* Only take input from real operands. */ -+ if (operand->flags & AXP_OPERAND_FAKE) -+ continue; -+ -+ /* When we expect input, make sure we have it. */ -+ if (tokidx >= ntok) -+ { -+ /* -pal: don't allowed to use default result register. */ -+ if (pal_org_backwrards) -+ goto match_failed; -+ else if ((operand->flags & AXP_OPERAND_OPTIONAL_MASK) == 0) -+ goto match_failed; -+ continue; -+ } -+ -+ /* Match operand type with expression type. */ -+ switch (operand->flags & AXP_OPERAND_TYPECHECK_MASK) -+ { -+ case AXP_OPERAND_IR: -+ if (tok[tokidx].X_op != O_register -+ || !is_ir_num (tok[tokidx].X_add_number)) -+ goto match_failed; -+ break; -+ case AXP_OPERAND_FPR: -+ if (tok[tokidx].X_op != O_register -+ || !is_fpr_num (tok[tokidx].X_add_number)) -+ goto match_failed; -+ break; -+ case AXP_OPERAND_IR | AXP_OPERAND_PARENS: -+ if (tok[tokidx].X_op != O_pregister -+ || !is_ir_num (tok[tokidx].X_add_number)) -+ goto match_failed; -+ break; -+ case AXP_OPERAND_IR | AXP_OPERAND_PARENS | AXP_OPERAND_COMMA: -+ if (tok[tokidx].X_op != O_cpregister -+ || !is_ir_num (tok[tokidx].X_add_number)) -+ goto match_failed; -+ break; -+ -+ case AXP_OPERAND_RELATIVE: -+ case AXP_OPERAND_SIGNED: -+ case AXP_OPERAND_UNSIGNED: -+ switch (tok[tokidx].X_op) -+ { -+ case O_illegal: -+ case O_absent: -+ case O_register: -+ case O_pregister: -+ case O_cpregister: -+ goto match_failed; -+ -+ default: -+ break; -+ } -+ break; -+ -+ default: -+ /* Everything else should have been fake. */ -+ abort (); -+ } -+ ++tokidx; -+ } -+ -+ /* Possible match -- did we use all of our input? */ -+ if (tokidx == ntok) -+ { -+ *pntok = ntok; -+ return opcode; -+ } -+ -+ match_failed:; -+ } while (++opcode - sw_64_opcodes < (int) sw_64_num_opcodes -+ && !strcmp (opcode->name, first_opcode->name)); -+ -+ if (*pcpumatch) -+ *pcpumatch = got_cpu_match; -+ -+ return NULL; -+} -+ -+/* Given an opcode name and a pre-tokenized set of arguments, assemble -+ the insn, but do not emit it. -+ -+ Note that this implies no macros allowed, since we can't store more -+ than one insn in an insn structure. */ -+ -+static void -+assemble_tokens_to_insn (const char *opname, const expressionS *tok, int ntok, -+ struct sw_64_insn *insn) -+{ -+ const struct sw_64_opcode *opcode; -+ -+ /* Search opcodes. */ -+ opcode -+ = (const struct sw_64_opcode *) str_hash_find (sw_64_opcode_hash, opname); -+ if (opcode) -+ { -+ int cpumatch; -+ opcode = find_opcode_match (opcode, tok, &ntok, &cpumatch); -+ if (opcode) -+ { -+ assemble_insn (opcode, tok, ntok, insn, BFD_RELOC_UNUSED); -+ return; -+ } -+ else if (cpumatch) -+ as_bad (_ ("inappropriate arguments for opcode `%s'"), opname); -+ else -+ as_bad (_ ("opcode `%s' not supported for target %s"), opname, -+ sw_64_target_name); -+ } -+ else -+ as_bad (_ ("unknown opcode `%s'"), opname); -+} -+ -+/* Build a BFD section with its flags set appropriately for the .lita, -+ .lit8, or .lit4 sections. */ -+ -+static void -+create_literal_section (const char *name, segT *secp, symbolS **symp) -+{ -+ segT current_section = now_seg; -+ int current_subsec = now_subseg; -+ segT new_sec; -+ -+ *secp = new_sec = subseg_new (name, 0); -+ subseg_set (current_section, current_subsec); -+ bfd_set_section_alignment (new_sec, 4); -+ bfd_set_section_flags (new_sec, (SEC_RELOC | SEC_ALLOC | SEC_LOAD -+ | SEC_READONLY | SEC_DATA)); -+ -+ S_CLEAR_EXTERNAL (*symp = section_symbol (new_sec)); -+} -+ -+/* Load a (partial) expression into a target register. -+ -+ If poffset is not null, after the call it will either contain -+ O_constant 0, or a 16-bit offset appropriate for any MEM format -+ instruction. In addition, pbasereg will be modified to point to -+ the base register to use in that MEM format instruction. -+ -+ In any case, *pbasereg should contain a base register to add to the -+ expression. This will normally be either AXP_REG_ZERO or -+ sw_64_gp_register. Symbol addresses will always be loaded via $gp, -+ so "foo ($0)" is interpreted as adding the address of foo to $0; -+ i.e. "ldl $targ, LIT ($gp); addl $targ, $0, $targ". Odd, perhaps, -+ but this is what OSF/1 does. -+ -+ If explicit relocations of the form !literal! are allowed, -+ and used, then explicit_reloc with be an expression pointer. -+ -+ Finally, the return value is nonzero if the calling macro may emit -+ a LITUSE reloc if otherwise appropriate; the return value is the -+ sequence number to use. */ -+ -+static long -+load_expression (int targreg, const expressionS *exp, int *pbasereg, -+ expressionS *poffset, const char *opname) -+{ -+ long emit_lituse = 0; -+ offsetT addend = exp->X_add_number; -+ int basereg = *pbasereg; -+ struct sw_64_insn insn; -+ expressionS newtok[3]; -+ -+ switch (exp->X_op) -+ { -+ case O_symbol: { -+#ifdef OBJ_ECOFF -+ offsetT lit; -+ -+ /* Attempt to reduce .lit load by splitting the offset from -+ its symbol when possible, but don't create a situation in -+ which we'd fail. */ -+ if (!range_signed_32 (addend) -+ && (sw_64_noat_on || targreg == AXP_REG_AT)) -+ { -+ lit = add_to_literal_pool (exp->X_add_symbol, addend, -+ sw_64_lita_section, 8); -+ addend = 0; -+ } -+ else -+ lit -+ = add_to_literal_pool (exp->X_add_symbol, 0, sw_64_lita_section, 8); -+ -+ if (lit >= 0x8000) -+ as_fatal (_ ("overflow in literal (.lita) table")); -+ -+ /* Emit "ldl r, lit (gp)". */ -+ -+ if (basereg != sw_64_gp_register && targreg == basereg) -+ { -+ if (sw_64_noat_on) -+ as_warn (_ ("macro requires $at register while noat in effect")); -+ if (targreg == AXP_REG_AT) -+ as_warn (_ ("macro requires $at while $at in use")); -+ -+ set_tok_reg (newtok[0], AXP_REG_AT); -+ } -+ else -+ set_tok_reg (newtok[0], targreg); -+ -+ set_tok_sym (newtok[1], sw_64_lita_symbol, lit); -+ set_tok_preg (newtok[2], sw_64_gp_register); -+ -+ assemble_tokens_to_insn ("ldl", newtok, 3, &insn); -+ -+ gas_assert (insn.nfixups == 1); -+ insn.fixups[0].reloc = BFD_RELOC_SW_64_LITERAL; -+ insn.sequence = emit_lituse = next_sequence_num--; -+#endif /* OBJ_ECOFF */ -+#ifdef OBJ_ELF -+ /* Emit "ldl r, gotoff (gp)". */ -+ -+ if (basereg != sw_64_gp_register && targreg == basereg) -+ { -+ if (sw_64_noat_on) -+ as_bad (_ ("macro requires $at register while noat in effect")); -+ if (targreg == AXP_REG_AT) -+ as_bad (_ ("macro requires $at while $at in use")); -+ -+ set_tok_reg (newtok[0], AXP_REG_AT); -+ } -+ else -+ set_tok_reg (newtok[0], targreg); -+ -+ /* XXX: Disable this .got minimizing optimization so that we can get -+ better instruction offset knowledge in the compiler. This happens -+ very infrequently anyway. */ -+ if (1 -+ || (!range_signed_32 (addend) -+ && (sw_64_noat_on || targreg == AXP_REG_AT))) -+ { -+ newtok[1] = *exp; -+ addend = 0; -+ } -+ else -+ set_tok_sym (newtok[1], exp->X_add_symbol, 0); -+ -+ set_tok_preg (newtok[2], sw_64_gp_register); -+ -+ assemble_tokens_to_insn ("ldl", newtok, 3, &insn); -+ -+ gas_assert (insn.nfixups == 1); -+ insn.fixups[0].reloc = BFD_RELOC_SW_64_ELF_LITERAL; -+ insn.sequence = emit_lituse = next_sequence_num--; -+#endif /* OBJ_ELF */ -+#ifdef OBJ_EVAX -+ /* Find symbol or symbol pointer in link section. */ -+ -+ if (exp->X_add_symbol == sw_64_evax_proc->symbol) -+ { -+ /* Linkage-relative expression. */ -+ set_tok_reg (newtok[0], targreg); -+ -+ if (range_signed_16 (addend)) -+ { -+ set_tok_const (newtok[1], addend); -+ addend = 0; -+ } -+ else -+ { -+ set_tok_const (newtok[1], 0); -+ } -+ set_tok_preg (newtok[2], basereg); -+ assemble_tokens_to_insn ("ldi", newtok, 3, &insn); -+ } -+ else -+ { -+ const char *symname = S_GET_NAME (exp->X_add_symbol); -+ const char *ptr1, *ptr2; -+ int symlen = strlen (symname); -+ -+ if ((symlen > 4 -+ && strcmp (ptr2 = &symname[symlen - 4], "..lk") == 0)) -+ { -+ /* Access to an item whose address is stored in the linkage -+ section. Just read the address. */ -+ set_tok_reg (newtok[0], targreg); -+ -+ newtok[1] = *exp; -+ newtok[1].X_op = O_subtract; -+ newtok[1].X_op_symbol = sw_64_evax_proc->symbol; -+ -+ set_tok_preg (newtok[2], basereg); -+ assemble_tokens_to_insn ("ldi", newtok, 3, &insn); -+ sw_64_linkage_symbol = exp->X_add_symbol; -+ -+ if (poffset) -+ set_tok_const (*poffset, 0); -+ -+ if (sw_64_flag_replace && targreg == 26) -+ { -+ /* Add a NOP fixup for 'ldX $26,YYY..NAME..lk'. */ -+ char *ensymname; -+ symbolS *ensym; -+ -+ /* Build the entry name as 'NAME..en'. */ -+ ptr1 = strstr (symname, "..") + 2; -+ if (ptr1 > ptr2) -+ ptr1 = symname; -+ ensymname = XNEWVEC (char, ptr2 - ptr1 + 5); -+ memcpy (ensymname, ptr1, ptr2 - ptr1); -+ memcpy (ensymname + (ptr2 - ptr1), "..en", 5); -+ -+ gas_assert (insn.nfixups + 1 <= MAX_INSN_FIXUPS); -+ insn.fixups[insn.nfixups].reloc = BFD_RELOC_SW_64_NOP; -+ ensym = symbol_find_or_make (ensymname); -+ free (ensymname); -+ symbol_mark_used (ensym); -+ /* The fixup must be the same as the BFD_RELOC_SW_64_BOH -+ case in emit_jsrjmp. See B.4.5.2 of the OpenVMS Linker -+ Utility Manual. */ -+ insn.fixups[insn.nfixups].exp.X_op = O_symbol; -+ insn.fixups[insn.nfixups].exp.X_add_symbol = ensym; -+ insn.fixups[insn.nfixups].exp.X_add_number = 0; -+ insn.fixups[insn.nfixups].xtrasym = sw_64_linkage_symbol; -+ insn.fixups[insn.nfixups].procsym = sw_64_evax_proc->symbol; -+ insn.nfixups++; -+ -+ /* ??? Force bsym to be instantiated now, as it will be -+ too late to do so in tc_gen_reloc. */ -+ symbol_get_bfdsym (exp->X_add_symbol); -+ } -+ else if (sw_64_flag_replace && targreg == 27) -+ { -+ /* Add a ldi fixup for 'ldX $27,YYY.NAME..lk+8'. */ -+ char *psymname; -+ symbolS *psym; -+ -+ /* Extract NAME. */ -+ ptr1 = strstr (symname, "..") + 2; -+ if (ptr1 > ptr2) -+ ptr1 = symname; -+ psymname = xmemdup0 (ptr1, ptr2 - ptr1); -+ -+ gas_assert (insn.nfixups + 1 <= MAX_INSN_FIXUPS); -+ insn.fixups[insn.nfixups].reloc = BFD_RELOC_SW_64_LDA; -+ psym = symbol_find_or_make (psymname); -+ free (psymname); -+ symbol_mark_used (psym); -+ insn.fixups[insn.nfixups].exp.X_op = O_subtract; -+ insn.fixups[insn.nfixups].exp.X_add_symbol = psym; -+ insn.fixups[insn.nfixups].exp.X_op_symbol -+ = sw_64_evax_proc->symbol; -+ insn.fixups[insn.nfixups].exp.X_add_number = 0; -+ insn.fixups[insn.nfixups].xtrasym = sw_64_linkage_symbol; -+ insn.fixups[insn.nfixups].procsym = sw_64_evax_proc->symbol; -+ insn.nfixups++; -+ } -+ -+ emit_insn (&insn); -+ return 0; -+ } -+ else -+ { -+ /* Not in the linkage section. Put the value into the linkage -+ section. */ -+ symbolS *linkexp; -+ -+ if (!range_signed_32 (addend)) -+ addend = sign_extend_32 (addend); -+ linkexp = add_to_link_pool (exp->X_add_symbol, 0); -+ set_tok_reg (newtok[0], targreg); -+ set_tok_sym (newtok[1], linkexp, 0); -+ set_tok_preg (newtok[2], basereg); -+ assemble_tokens_to_insn ("ldl", newtok, 3, &insn); -+ } -+ } -+#endif /* OBJ_EVAX */ -+ -+ emit_insn (&insn); -+ -+#ifndef OBJ_EVAX -+ if (basereg != sw_64_gp_register && basereg != AXP_REG_ZERO) -+ { -+ /* Emit "addl r, base, r". */ -+ -+ set_tok_reg (newtok[1], basereg); -+ set_tok_reg (newtok[2], targreg); -+ assemble_tokens ("addl", newtok, 3, 0); -+ } -+#endif -+ basereg = targreg; -+ } -+ break; -+ -+ case O_constant: -+ break; -+ /* .text -+ * call_hmc__tbi_addr: -+ * ldi $4, ((tbi_tbl - call_hmc__tbi_addr) & 0xFFFF)($4) -+ * tbi_tbl: -+ * the value of label tbi_tbl can't be calculated,so the op of the -+ * expression "((tbi_tbl - call_hmc__tbi_addr) & 0xFFFF)" is "O_bit_and" -+ * but not "O_constant", so we must pass it ! -+ * */ -+ case O_bit_and: -+ set_tok_reg (newtok[0], targreg); -+ newtok[1] = *exp; -+ set_tok_preg (newtok[2], basereg); -+ assemble_tokens ("ldi", newtok, 3, 0); -+ break; -+ -+ case O_subtract: -+ /* Assume that this difference expression will be resolved to an -+ absolute value and that that value will fit in 16 bits. */ -+ -+ set_tok_reg (newtok[0], targreg); -+ newtok[1] = *exp; -+ set_tok_preg (newtok[2], basereg); -+ assemble_tokens (opname, newtok, 3, 0); -+ -+ if (poffset) -+ set_tok_const (*poffset, 0); -+ return 0; -+ -+ case O_big: -+ if (exp->X_add_number > 0) -+ as_bad (_ ("bignum invalid; zero assumed")); -+ else -+ as_bad (_ ("floating point number invalid; zero assumed")); -+ addend = 0; -+ break; -+ -+ default: -+ as_bad (_ ("can't handle expression")); -+ addend = 0; -+ break; -+ } -+ -+ if (!range_signed_32 (addend)) -+ { -+#ifdef OBJ_EVAX -+ symbolS *litexp; -+#else -+ offsetT lit; -+ long seq_num = next_sequence_num--; -+#endif -+ -+ /* For 64-bit addends, just put it in the literal pool. */ -+#ifdef OBJ_EVAX -+ /* Emit "ldl targreg, lit (basereg)". */ -+ litexp = add_to_link_pool (section_symbol (absolute_section), addend); -+ set_tok_reg (newtok[0], targreg); -+ set_tok_sym (newtok[1], litexp, 0); -+ set_tok_preg (newtok[2], sw_64_gp_register); -+ assemble_tokens ("ldl", newtok, 3, 0); -+#else -+ -+ if (sw_64_lit8_section == NULL) -+ { -+ create_literal_section (".lit8", &sw_64_lit8_section, -+ &sw_64_lit8_symbol); -+ -+#ifdef OBJ_ECOFF -+ sw_64_lit8_literal = add_to_literal_pool (sw_64_lit8_symbol, 0x8000, -+ sw_64_lita_section, 8); -+ if (sw_64_lit8_literal >= 0x8000) -+ as_fatal (_ ("overflow in literal (.lita) table")); -+#endif -+ } -+ -+ lit = add_to_literal_pool (NULL, addend, sw_64_lit8_section, 8) - 0x8000; -+ if (lit >= 0x8000) -+ as_fatal (_ ("overflow in literal (.lit8) table")); -+ -+ /* Emit "ldi litreg, .lit8+0x8000". */ -+ -+ if (targreg == basereg) -+ { -+ if (sw_64_noat_on) -+ as_bad (_ ("macro requires $at register while noat in effect")); -+ if (targreg == AXP_REG_AT) -+ as_bad (_ ("macro requires $at while $at in use")); -+ -+ set_tok_reg (newtok[0], AXP_REG_AT); -+ } -+ else -+ set_tok_reg (newtok[0], targreg); -+#ifdef OBJ_ECOFF -+ set_tok_sym (newtok[1], sw_64_lita_symbol, sw_64_lit8_literal); -+#endif -+#ifdef OBJ_ELF -+ set_tok_sym (newtok[1], sw_64_lit8_symbol, 0x8000); -+#endif -+ set_tok_preg (newtok[2], sw_64_gp_register); -+ -+ assemble_tokens_to_insn ("ldl", newtok, 3, &insn); -+ -+ gas_assert (insn.nfixups == 1); -+#ifdef OBJ_ECOFF -+ insn.fixups[0].reloc = BFD_RELOC_SW_64_LITERAL; -+#endif -+#ifdef OBJ_ELF -+ insn.fixups[0].reloc = BFD_RELOC_SW_64_ELF_LITERAL; -+#endif -+ insn.sequence = seq_num; -+ -+ emit_insn (&insn); -+ -+ /* Emit "ldl litreg, lit (litreg)". */ -+ -+ set_tok_const (newtok[1], lit); -+ set_tok_preg (newtok[2], newtok[0].X_add_number); -+ -+ assemble_tokens_to_insn ("ldl", newtok, 3, &insn); -+ -+ gas_assert (insn.nfixups < MAX_INSN_FIXUPS); -+ insn.fixups[insn.nfixups].reloc = DUMMY_RELOC_LITUSE_BASE; -+ insn.fixups[insn.nfixups].exp.X_op = O_absent; -+ insn.nfixups++; -+ insn.sequence = seq_num; -+ emit_lituse = 0; -+ -+ emit_insn (&insn); -+ -+ /* Emit "addl litreg, base, target". */ -+ -+ if (basereg != AXP_REG_ZERO) -+ { -+ set_tok_reg (newtok[1], basereg); -+ set_tok_reg (newtok[2], targreg); -+ assemble_tokens ("addl", newtok, 3, 0); -+ } -+#endif /* !OBJ_EVAX */ -+ -+ if (poffset) -+ set_tok_const (*poffset, 0); -+ *pbasereg = targreg; -+ } -+ else -+ { -+ offsetT low, high, extra, tmp; -+ -+ /* For 32-bit operands, break up the addend. */ -+ -+ low = sign_extend_16 (addend); -+ tmp = addend - low; -+ high = sign_extend_16 (tmp >> 16); -+ -+ if (tmp - (high << 16)) -+ { -+ extra = 0x4000; -+ tmp -= 0x40000000; -+ high = sign_extend_16 (tmp >> 16); -+ } -+ else -+ extra = 0; -+ -+ set_tok_reg (newtok[0], targreg); -+ set_tok_preg (newtok[2], basereg); -+ -+ if (extra) -+ { -+ /* Emit "ldih r, extra (r). */ -+ set_tok_const (newtok[1], extra); -+ assemble_tokens ("ldih", newtok, 3, 0); -+ set_tok_preg (newtok[2], basereg = targreg); -+ } -+ -+ if (high) -+ { -+ /* Emit "ldih r, high (r). */ -+ set_tok_const (newtok[1], high); -+ if (newtok[0].X_add_number == 31 && newtok[0].X_op == O_register) -+ as_warn (_ (" the disp is out of range ,may be incorrect !")); -+ else -+ assemble_tokens ("ldih", newtok, 3, 0); -+ basereg = targreg; -+ set_tok_preg (newtok[2], basereg); -+ } -+ -+ if ((low && !poffset) || (!poffset && basereg != targreg)) -+ { -+ /* Emit "ldi r, low (base)". */ -+ set_tok_const (newtok[1], low); -+ assemble_tokens ("ldi", newtok, 3, 0); -+ basereg = targreg; -+ low = 0; -+ } -+ -+ if (poffset) -+ set_tok_const (*poffset, low); -+ *pbasereg = basereg; -+ } -+ -+ return emit_lituse; -+} -+ -+/* The ldi macro differs from the ldi instruction in that it handles -+ most simple expressions, particularly symbol address loads and -+ large constants. */ -+ -+static void -+emit_ldi (const expressionS *tok, int ntok, const void *unused ATTRIBUTE_UNUSED) -+{ -+ int basereg; -+ -+ if (ntok == 2) -+ basereg = (tok[1].X_op == O_constant ? AXP_REG_ZERO : sw_64_gp_register); -+ else -+ basereg = tok[2].X_add_number; -+ -+ (void) load_expression (tok[0].X_add_number, &tok[1], &basereg, NULL, "ldi"); -+} -+ -+/* The ldih macro differs from the ldih instruction in that it has $31 -+ as an implied base register. */ -+ -+static void -+emit_ldih (const expressionS *tok, int ntok ATTRIBUTE_UNUSED, -+ const void *unused ATTRIBUTE_UNUSED) -+{ -+ expressionS newtok[3]; -+ -+ newtok[0] = tok[0]; -+ newtok[1] = tok[1]; -+ set_tok_preg (newtok[2], AXP_REG_ZERO); -+ -+ assemble_tokens ("ldih", newtok, 3, 0); -+} -+ -+/* Called internally to handle all alignment needs. This takes care -+ of eliding calls to frag_align if'n the cached current alignment -+ says we've already got it, as well as taking care of the auto-align -+ feature wrt labels. */ -+ -+static void -+sw_64_align (int n, char *pfill, symbolS *label, int force ATTRIBUTE_UNUSED) -+{ -+ if (sw_64_current_align >= n) -+ return; -+ -+ if (pfill == NULL) -+ { -+ if (subseg_text_p (now_seg)) -+ frag_align_code (n, 0); -+ else -+ frag_align (n, 0, 0); -+ } -+ else -+ frag_align (n, *pfill, 0); -+ -+ sw_64_current_align = n; -+ -+ if (label != NULL && S_GET_SEGMENT (label) == now_seg) -+ { -+ symbol_set_frag (label, frag_now); -+ S_SET_VALUE (label, (valueT) frag_now_fix ()); -+ } -+ -+ record_alignment (now_seg, n); -+ -+ /* ??? If sw_64_flag_relax && force && elf, record the requested alignment -+ in a reloc for the linker to see. */ -+} -+ -+/* Actually output an instruction with its fixup. */ -+ -+static void -+emit_insn (struct sw_64_insn *insn) -+{ -+ char *f; -+ int i; -+ -+ /* Take care of alignment duties. */ -+ if (sw_64_auto_align_on && sw_64_current_align < 2) -+ sw_64_align (2, (char *) NULL, sw_64_insn_label, 0); -+ if (sw_64_current_align > 2) -+ sw_64_current_align = 2; -+ sw_64_insn_label = NULL; -+ -+ /* Write out the instruction. */ -+ f = frag_more (4); -+ md_number_to_chars (f, insn->insn, 4); -+ -+#ifdef OBJ_ELF -+ dwarf2_emit_insn (4); -+#endif -+ -+ /* Apply the fixups in order. */ -+ for (i = 0; i < insn->nfixups; ++i) -+ { -+ const struct sw_64_operand *operand = (const struct sw_64_operand *) 0; -+ struct sw_64_fixup *fixup = &insn->fixups[i]; -+ struct sw_64_reloc_tag *info = NULL; -+ int size, pcrel; -+ fixS *fixP; -+ -+ /* Some fixups are only used internally and so have no howto. */ -+ if ((int) fixup->reloc < 0) -+ { -+ operand = &sw_64_operands[-(int) fixup->reloc]; -+ size = 4; -+ pcrel = ((operand->flags & AXP_OPERAND_RELATIVE) != 0); -+ } -+ else if (fixup->reloc > BFD_RELOC_UNUSED -+ || fixup->reloc == BFD_RELOC_SW_64_GPDISP_HI16 -+ || fixup->reloc == BFD_RELOC_SW_64_GPDISP_LO16) -+ { -+ size = 2; -+ pcrel = 0; -+ } -+ else -+ { -+ reloc_howto_type *reloc_howto -+ = bfd_reloc_type_lookup (stdoutput, -+ (bfd_reloc_code_real_type) fixup->reloc); -+ gas_assert (reloc_howto); -+ -+ size = bfd_get_reloc_size (reloc_howto); -+ -+ switch (fixup->reloc) -+ { -+#ifdef OBJ_EVAX -+ case BFD_RELOC_SW_64_NOP: -+ case BFD_RELOC_SW_64_BSR: -+ case BFD_RELOC_SW_64_LDA: -+ case BFD_RELOC_SW_64_BOH: -+ break; -+#endif -+ default: -+ gas_assert (size >= 1 && size <= 4); -+ } -+ -+ pcrel = reloc_howto->pc_relative; -+ } -+ -+ fixP = fix_new_exp (frag_now, f - frag_now->fr_literal, size, &fixup->exp, -+ pcrel, (bfd_reloc_code_real_type) fixup->reloc); -+ -+ /* Turn off complaints that the addend is too large for some fixups, -+ and copy in the sequence number for the explicit relocations. */ -+ switch (fixup->reloc) -+ { -+ case BFD_RELOC_SW_64_HINT: -+ case BFD_RELOC_GPREL32: -+ case BFD_RELOC_GPREL16: -+ case BFD_RELOC_SW_64_GPREL_HI16: -+ case BFD_RELOC_SW_64_GPREL_LO16: -+ case BFD_RELOC_SW_64_DTPREL_HI16: -+ case BFD_RELOC_SW_64_DTPREL_LO16: -+ case BFD_RELOC_SW_64_DTPREL16: -+ case BFD_RELOC_SW_64_TPREL_HI16: -+ case BFD_RELOC_SW_64_TPREL_LO16: -+ case BFD_RELOC_SW_64_TPREL16: -+ fixP->fx_no_overflow = 1; -+ break; -+ -+ case BFD_RELOC_SW_64_GPDISP_HI16: -+ fixP->fx_no_overflow = 1; -+ fixP->fx_addsy = section_symbol (now_seg); -+ fixP->fx_offset = 0; -+ -+ info = get_sw_64_reloc_tag (insn->sequence); -+ if (++info->n_master > 1) -+ as_bad (_ ("too many ldih insns for !gpdisp!%ld"), insn->sequence); -+ if (info->segment != now_seg) -+ as_bad (_ ( -+ "both insns for !gpdisp!%ld must be in the same section"), -+ insn->sequence); -+ fixP->tc_fix_data.info = info; -+ break; -+ -+ case BFD_RELOC_SW_64_GPDISP_LO16: -+ fixP->fx_no_overflow = 1; -+ -+ info = get_sw_64_reloc_tag (insn->sequence); -+ if (++info->n_slaves > 1) -+ as_bad (_ ("too many ldi insns for !gpdisp!%ld"), insn->sequence); -+ if (info->segment != now_seg) -+ as_bad (_ ( -+ "both insns for !gpdisp!%ld must be in the same section"), -+ insn->sequence); -+ fixP->tc_fix_data.info = info; -+ info->slaves = fixP; -+ break; -+ -+ case BFD_RELOC_SW_64_ELF_LITERAL_GOT: -+ fixP->fx_no_overflow = 1; -+ fixP->fx_size = 4; -+ -+ if (insn->sequence == 0) -+ break; -+ info = get_sw_64_reloc_tag (insn->sequence); -+ info->literal_got = fixP; -+ fixP->tc_fix_data.info = info; -+ break; -+ -+ case BFD_RELOC_SW_64_LITERAL: -+ case BFD_RELOC_SW_64_ELF_LITERAL: -+ fixP->fx_no_overflow = 1; -+ if ((frags_pre_fixup != NULL) -+ && (frags_pre_fixup->fx_r_type -+ == BFD_RELOC_SW_64_ELF_LITERAL_GOT)) -+ fixP->fx_size = 4; -+ if (insn->sequence == 0) -+ break; -+ info = get_sw_64_reloc_tag (insn->sequence); -+ info->master = fixP; -+ info->n_master++; -+ if (info->segment != now_seg) -+ info->multi_section_p = 1; -+ fixP->tc_fix_data.info = info; -+ break; -+ -+#ifdef RELOC_OP_P -+ case DUMMY_RELOC_LITUSE_ADDR: -+ fixP->fx_offset = LITUSE_SW_64_ADDR; -+ goto do_lituse; -+ case DUMMY_RELOC_LITUSE_BASE: -+ fixP->fx_offset = LITUSE_SW_64_BASE; -+ goto do_lituse; -+ case DUMMY_RELOC_LITUSE_BYTOFF: -+ fixP->fx_offset = LITUSE_SW_64_BYTOFF; -+ goto do_lituse; -+ case DUMMY_RELOC_LITUSE_JSR: -+ fixP->fx_offset = LITUSE_SW_64_JSR; -+ goto do_lituse; -+ case DUMMY_RELOC_LITUSE_TLSGD: -+ fixP->fx_offset = LITUSE_SW_64_TLSGD; -+ goto do_lituse; -+ case DUMMY_RELOC_LITUSE_TLSLDM: -+ fixP->fx_offset = LITUSE_SW_64_TLSLDM; -+ goto do_lituse; -+ case DUMMY_RELOC_LITUSE_JSRDIRECT: -+ fixP->fx_offset = LITUSE_SW_64_JSRDIRECT; -+ goto do_lituse; -+ do_lituse: -+ fixP->fx_addsy = section_symbol (now_seg); -+ fixP->fx_r_type = BFD_RELOC_SW_64_LITUSE; -+ -+ info = get_sw_64_reloc_tag (insn->sequence); -+ if (fixup->reloc == DUMMY_RELOC_LITUSE_TLSGD) -+ info->saw_lu_tlsgd = 1; -+ else if (fixup->reloc == DUMMY_RELOC_LITUSE_TLSLDM) -+ info->saw_lu_tlsldm = 1; -+ if (++info->n_slaves > 1) -+ { -+ if (info->saw_lu_tlsgd) -+ as_bad (_ ("too many lituse insns for !lituse_tlsgd!%ld"), -+ insn->sequence); -+ else if (info->saw_lu_tlsldm) -+ as_bad (_ ("too many lituse insns for !lituse_tlsldm!%ld"), -+ insn->sequence); -+ } -+ fixP->tc_fix_data.info = info; -+ fixP->tc_fix_data.next_reloc = info->slaves; -+ info->slaves = fixP; -+ if (info->segment != now_seg) -+ info->multi_section_p = 1; -+ break; -+ -+ case BFD_RELOC_SW_64_TLSREL_GOT: -+ if (insn->sequence == 0) -+ break; -+ info = get_sw_64_reloc_tag (insn->sequence); -+ info->tlsrel_got = fixP; -+ fixP->tc_fix_data.info = info; -+ break; -+ -+ case BFD_RELOC_SW_64_TLSGD: -+ fixP->fx_no_overflow = 1; -+ -+ if (insn->sequence == 0) -+ break; -+ info = get_sw_64_reloc_tag (insn->sequence); -+ if (info->saw_tlsgd) -+ as_bad (_ ("duplicate !tlsgd!%ld"), insn->sequence); -+ else if (info->saw_tlsldm) -+ as_bad (_ ("sequence number in use for !tlsldm!%ld"), -+ insn->sequence); -+ else -+ info->saw_tlsgd = 1; -+ info->tlsgd = fixP; -+ fixP->tc_fix_data.info = info; -+ break; -+ -+ case BFD_RELOC_SW_64_TLSLDM: -+ fixP->fx_no_overflow = 1; -+ -+ if (insn->sequence == 0) -+ break; -+ info = get_sw_64_reloc_tag (insn->sequence); -+ if (info->saw_tlsldm) -+ as_bad (_ ("duplicate !tlsldm!%ld"), insn->sequence); -+ else if (info->saw_tlsgd) -+ as_bad (_ ("sequence number in use for !tlsgd!%ld"), -+ insn->sequence); -+ else -+ info->saw_tlsldm = 1; -+ info->tlsldm = fixP; -+ fixP->tc_fix_data.info = info; -+ break; -+#endif -+ case BFD_RELOC_SW_64_GOTDTPREL16: -+ fixP->fx_no_overflow = 1; -+ -+ if (insn->sequence == 0) -+ break; -+ info = get_sw_64_reloc_tag (insn->sequence); -+ info->gotdtprel = fixP; -+ info->master = fixP; -+ info->n_master++; -+ fixP->tc_fix_data.info = info; -+ break; -+ -+ case BFD_RELOC_SW_64_GOTTPREL16: -+ fixP->fx_no_overflow = 1; -+ -+ if (insn->sequence == 0) -+ break; -+ info = get_sw_64_reloc_tag (insn->sequence); -+ info->gottprel = fixP; -+ info->master = fixP; -+ info->n_master++; -+ fixP->tc_fix_data.info = info; -+ break; -+#ifdef OBJ_EVAX -+ case BFD_RELOC_SW_64_NOP: -+ case BFD_RELOC_SW_64_LDA: -+ case BFD_RELOC_SW_64_BSR: -+ case BFD_RELOC_SW_64_BOH: -+ info = get_sw_64_reloc_tag (next_sequence_num--); -+ fixP->tc_fix_data.info = info; -+ fixP->tc_fix_data.info->sym = fixup->xtrasym; -+ fixP->tc_fix_data.info->psym = fixup->procsym; -+ break; -+#endif -+ -+ default: -+ if ((int) fixup->reloc < 0) -+ { -+ if (operand->flags & AXP_OPERAND_NOOVERFLOW) -+ fixP->fx_no_overflow = 1; -+ } -+ break; -+ } -+ } -+} -+ -+/* Insert an operand value into an instruction. */ -+ -+static unsigned -+insert_operand (unsigned insn, const struct sw_64_operand *operand, offsetT val, -+ const char *file, unsigned line) -+{ -+ if (operand->bits != 32 && !(operand->flags & AXP_OPERAND_NOOVERFLOW)) -+ { -+ offsetT min, max; -+ -+ if (operand->flags & AXP_OPERAND_SIGNED) -+ { -+ max = (1 << (operand->bits - 1)) - 1; -+ min = -(1 << (operand->bits - 1)); -+ } -+ else -+ { -+ max = (1 << operand->bits) - 1; -+ min = 0; -+ } -+ -+ if (val < min || val > max) -+ as_warn_value_out_of_range (_ ("operand"), val, min, max, file, line); -+ } -+ -+ if (operand->insert) -+ { -+ const char *errmsg = NULL; -+ -+ insn = (*operand->insert) (insn, val, &errmsg); -+ if (errmsg) -+ as_warn ("%s", errmsg); -+ } -+ else -+ insn |= ((val & ((1 << operand->bits) - 1)) << operand->shift); -+ -+ return insn; -+} -+ -+static unsigned int need_rd_f = 0; -+static unsigned int next_insn = 0; -+static unsigned int register1 = 0; -+static char lstname[5]; -+/* Turn an opcode description and a set of arguments into -+ an instruction and a fixup. */ -+ -+static void -+assemble_insn (const struct sw_64_opcode *opcode, const expressionS *tok, -+ int ntok, struct sw_64_insn *insn, -+ extended_bfd_reloc_code_real_type reloc) -+{ -+ const struct sw_64_operand *reloc_operand = NULL; -+ const expressionS *reloc_exp = NULL; -+ const unsigned char *argidx; -+ unsigned image; -+ int tokidx = 0; -+ next_insn++; -+ -+ memset (insn, 0, sizeof (*insn)); -+ image = opcode->opcode; -+ -+ for (argidx = opcode->operands; *argidx; ++argidx) -+ { -+ const struct sw_64_operand *operand = &sw_64_operands[*argidx]; -+ const expressionS *t = (const expressionS *) 0; -+ -+ if (operand->flags & AXP_OPERAND_FAKE) -+ { -+ /* Fake operands take no value and generate no fixup. */ -+ image = insert_operand (image, operand, 0, NULL, 0); -+ continue; -+ } -+ -+ if (tokidx >= ntok) -+ { -+ switch (operand->flags & AXP_OPERAND_OPTIONAL_MASK) -+ { -+ case AXP_OPERAND_DEFAULT_FIRST: -+ t = &tok[0]; -+ break; -+ case AXP_OPERAND_DEFAULT_SECOND: -+ t = &tok[1]; -+ break; -+ case AXP_OPERAND_DEFAULT_THIRD: -+ t = &tok[2]; -+ break; -+ case AXP_OPERAND_DEFAULT_ZERO: { -+ static expressionS zero_exp; -+ t = &zero_exp; -+ zero_exp.X_op = O_constant; -+ zero_exp.X_unsigned = 1; -+ } -+ break; -+ default: -+ abort (); -+ } -+ } -+ else -+ t = &tok[tokidx++]; -+ -+ switch (t->X_op) -+ { -+ case O_register: -+ case O_pregister: -+ case O_cpregister: -+ image -+ = insert_operand (image, operand, regno (t->X_add_number), NULL, 0); -+ break; -+ -+ case O_constant: -+ image = insert_operand (image, operand, t->X_add_number, NULL, 0); -+ reloc_operand = operand; -+ reloc_exp = t; -+ break; -+ -+ default: -+ /* This is only 0 for fields that should contain registers, -+ which means this pattern shouldn't have matched. */ -+ if (operand->default_reloc == 0) -+ abort (); -+ -+ /* There is one special case for which an insn receives two -+ relocations, and thus the user-supplied reloc does not -+ override the operand reloc. */ -+ if (operand->default_reloc == BFD_RELOC_SW_64_HINT) -+ { -+ struct sw_64_fixup *fixup; -+ -+ if (insn->nfixups >= MAX_INSN_FIXUPS) -+ as_fatal (_ ("too many fixups")); -+ -+ fixup = &insn->fixups[insn->nfixups++]; -+ fixup->exp = *t; -+ fixup->reloc = BFD_RELOC_SW_64_HINT; -+ } -+ else -+ { -+ if (reloc == BFD_RELOC_UNUSED) -+ reloc = operand->default_reloc; -+ -+ gas_assert (reloc_operand == NULL); -+ reloc_operand = operand; -+ reloc_exp = t; -+ } -+ break; -+ } -+ } -+ -+ if (reloc != BFD_RELOC_UNUSED) -+ { -+ struct sw_64_fixup *fixup; -+ -+ if (insn->nfixups >= MAX_INSN_FIXUPS) -+ as_fatal (_ ("too many fixups")); -+ -+ /* ??? My but this is hacky. But the OSF/1 assembler uses the same -+ relocation tag for both ldih and ldi with gpdisp. Choose the -+ correct internal relocation based on the opcode. */ -+ if (reloc == BFD_RELOC_SW_64_GPDISP) -+ { -+ if (strcmp (opcode->name, "ldih") == 0) -+ reloc = BFD_RELOC_SW_64_GPDISP_HI16; -+ else if (strcmp (opcode->name, "ldi") == 0) -+ reloc = BFD_RELOC_SW_64_GPDISP_LO16; -+ else -+ as_bad (_ ("invalid relocation for instruction")); -+ } -+ -+ /* If this is a real relocation (as opposed to a lituse hint), then -+ the relocation width should match the operand width. -+ Take care of -MDISP in operand table. */ -+ else if (reloc < BFD_RELOC_UNUSED && reloc > 0) -+ { -+ if (reloc == BFD_RELOC_SW_64_BRSGP -+ && (strcmp (opcode->name, "lbr") == 0)) -+ reloc = BFD_RELOC_SW_64_BR26; -+ -+ reloc_howto_type *reloc_howto -+ = bfd_reloc_type_lookup (stdoutput, -+ (bfd_reloc_code_real_type) reloc); -+ if (reloc_operand == NULL -+ || reloc_howto->bitsize != reloc_operand->bits) -+ { -+ as_bad (_ ("invalid relocation for field")); -+ return; -+ } -+ } -+ -+ fixup = &insn->fixups[insn->nfixups++]; -+ if (reloc_exp) -+ fixup->exp = *reloc_exp; -+ else -+ fixup->exp.X_op = O_absent; -+ fixup->reloc = reloc; -+ } -+ -+ insn->insn = image; -+ -+ if (!strcmp (sw_64_target_name, "sw6a") || !strcmp (sw_64_target_name, "sw6b") -+ || !strcmp (sw_64_target_name, "sw8a")) -+ { -+ if (!strcmp (opcode->name, "lstw") || !strcmp (opcode->name, "lstl") -+ || !strcmp (opcode->name, "stl_c") || !strcmp (opcode->name, "stq_c")) -+ { -+ sw_64_align (3, (char *) NULL, sw_64_insn_label, 0); -+ need_rd_f = 1; -+ next_insn = 0; -+ register1 = tok[0].X_add_number; -+ strcpy (lstname, opcode->name); -+ } -+ if (!strcmp (sw_64_target_name, "sw6a") -+ || !strcmp (sw_64_target_name, "sw6b")) -+ { -+ if (strcmp (opcode->name, "rd_f") && need_rd_f && (next_insn == 1)) -+ as_bad (_ ("missing \"rd_f\" before \"%s\" !!"), -+ (char *) opcode->name); -+ } -+ if (!strcmp (opcode->name, "rd_f") && (register1 != tok[0].X_add_number)) -+ as_bad (_ (" %s and rd_f the first register must be the same"), -+ lstname); -+ } -+} -+ -+/* Handle all "simple" integer register loads -- ldl, ldl_l, ldl_u, -+ etc. They differ from the real instructions in that they do simple -+ expressions like the ldi macro. */ -+ -+static void -+emit_ir_load (const expressionS *tok, int ntok, const void *opname) -+{ -+ int basereg; -+ long lituse; -+ expressionS newtok[3]; -+ struct sw_64_insn insn; -+ const char *symname -+ = tok[1].X_add_symbol ? S_GET_NAME (tok[1].X_add_symbol) : ""; -+ int symlen = strlen (symname); -+ -+ if (ntok == 2) -+ basereg = (tok[1].X_op == O_constant ? AXP_REG_ZERO : sw_64_gp_register); -+ else -+ basereg = tok[2].X_add_number; -+ -+ lituse = load_expression (tok[0].X_add_number, &tok[1], &basereg, &newtok[1], -+ (const char *) opname); -+ -+ if (basereg == sw_64_gp_register -+ && (symlen > 4 && strcmp (&symname[symlen - 4], "..lk") == 0)) -+ return; -+ -+ newtok[0] = tok[0]; -+ set_tok_preg (newtok[2], basereg); -+ -+ assemble_tokens_to_insn ((const char *) opname, newtok, 3, &insn); -+ -+ if (lituse) -+ { -+ gas_assert (insn.nfixups < MAX_INSN_FIXUPS); -+ insn.fixups[insn.nfixups].reloc = DUMMY_RELOC_LITUSE_BASE; -+ insn.fixups[insn.nfixups].exp.X_op = O_absent; -+ insn.nfixups++; -+ insn.sequence = lituse; -+ } -+ -+ emit_insn (&insn); -+} -+ -+/* Handle fp register loads, and both integer and fp register stores. -+ Again, we handle simple expressions. */ -+ -+static void -+emit_loadstore (const expressionS *tok, int ntok, const void *opname) -+{ -+ int basereg; -+ long lituse; -+ expressionS newtok[3]; -+ struct sw_64_insn insn; -+ -+ if (ntok == 2) -+ basereg = (tok[1].X_op == O_constant ? AXP_REG_ZERO : sw_64_gp_register); -+ else -+ basereg = tok[2].X_add_number; -+ -+ if (tok[1].X_op != O_constant || !range_signed_16 (tok[1].X_add_number)) -+ { -+ if (sw_64_noat_on) -+ as_bad (_ ("macro requires $at register while noat in effect")); -+ else -+ as_warn (_ ("assembler requires $28 register for the marco !")); -+ -+ lituse = load_expression (AXP_REG_AT, &tok[1], &basereg, &newtok[1], -+ (const char *) opname); -+ } -+ else -+ { -+ newtok[1] = tok[1]; -+ lituse = 0; -+ } -+ -+ newtok[0] = tok[0]; -+ set_tok_preg (newtok[2], basereg); -+ -+ assemble_tokens_to_insn ((const char *) opname, newtok, 3, &insn); -+ -+ if (lituse) -+ { -+ gas_assert (insn.nfixups < MAX_INSN_FIXUPS); -+ insn.fixups[insn.nfixups].reloc = DUMMY_RELOC_LITUSE_BASE; -+ insn.fixups[insn.nfixups].exp.X_op = O_absent; -+ insn.nfixups++; -+ insn.sequence = lituse; -+ } -+ -+ emit_insn (&insn); -+} -+ -+/* Load a half-word or byte as an unsigned value. */ -+ -+static void -+emit_ldXu (const expressionS *tok, int ntok, const void *vlgsize) -+{ -+ if (sw_64_target & AXP_OPCODE_SW6) -+ emit_ir_load (tok, ntok, ldXu_op[(long) vlgsize]); -+ else -+ { -+ expressionS newtok[3]; -+ struct sw_64_insn insn; -+ int basereg; -+ long lituse; -+ -+ if (sw_64_noat_on) -+ as_bad (_ ("macro requires $at register while noat in effect")); -+ -+ if (ntok == 2) -+ basereg -+ = (tok[1].X_op == O_constant ? AXP_REG_ZERO : sw_64_gp_register); -+ else -+ basereg = tok[2].X_add_number; -+ -+ /* Emit "ldi $at, exp". */ -+ lituse = load_expression (AXP_REG_AT, &tok[1], &basereg, NULL, "ldi"); -+ -+ /* Emit "ldl_u targ, 0 ($at)". */ -+ newtok[0] = tok[0]; -+ set_tok_const (newtok[1], 0); -+ set_tok_preg (newtok[2], basereg); -+ assemble_tokens_to_insn ("ldl_u", newtok, 3, &insn); -+ -+ if (lituse) -+ { -+ gas_assert (insn.nfixups < MAX_INSN_FIXUPS); -+ insn.fixups[insn.nfixups].reloc = DUMMY_RELOC_LITUSE_BASE; -+ insn.fixups[insn.nfixups].exp.X_op = O_absent; -+ insn.nfixups++; -+ insn.sequence = lituse; -+ } -+ -+ emit_insn (&insn); -+ -+ /* Emit "extXl targ, $at, targ". */ -+ set_tok_reg (newtok[1], basereg); -+ newtok[2] = newtok[0]; -+ assemble_tokens_to_insn (extXl_op[(long) vlgsize], newtok, 3, &insn); -+ -+ if (lituse) -+ { -+ gas_assert (insn.nfixups < MAX_INSN_FIXUPS); -+ insn.fixups[insn.nfixups].reloc = DUMMY_RELOC_LITUSE_BYTOFF; -+ insn.fixups[insn.nfixups].exp.X_op = O_absent; -+ insn.nfixups++; -+ insn.sequence = lituse; -+ } -+ -+ emit_insn (&insn); -+ } -+} -+ -+/* Load a half-word or byte as a signed value. */ -+ -+static void -+emit_ldX (const expressionS *tok, int ntok, const void *vlgsize) -+{ -+ emit_ldXu (tok, ntok, vlgsize); -+ assemble_tokens (sextX_op[(long) vlgsize], tok, 1, 1); -+} -+ -+/* Load an integral value from an unaligned address as an unsigned -+ value. */ -+ -+static void -+emit_uldXu (const expressionS *tok, int ntok, const void *vlgsize) -+{ -+ long lgsize = (long) vlgsize; -+ expressionS newtok[3]; -+ -+ if (sw_64_noat_on) -+ as_bad (_ ("macro requires $at register while noat in effect")); -+ -+ /* Emit "ldi $at, exp". */ -+ memcpy (newtok, tok, sizeof (expressionS) * ntok); -+ newtok[0].X_add_number = AXP_REG_AT; -+ assemble_tokens ("ldi", newtok, ntok, 1); -+ -+ /* Emit "ldl_u $t9, 0 ($at)". */ -+ set_tok_reg (newtok[0], AXP_REG_T9); -+ set_tok_const (newtok[1], 0); -+ set_tok_preg (newtok[2], AXP_REG_AT); -+ assemble_tokens ("ldl_u", newtok, 3, 1); -+ -+ /* Emit "ldl_u $t10, size-1 ($at)". */ -+ set_tok_reg (newtok[0], AXP_REG_T10); -+ set_tok_const (newtok[1], (1 << lgsize) - 1); -+ assemble_tokens ("ldl_u", newtok, 3, 1); -+ -+ /* Emit "extXl $t9, $at, $t9". */ -+ set_tok_reg (newtok[0], AXP_REG_T9); -+ set_tok_reg (newtok[1], AXP_REG_AT); -+ set_tok_reg (newtok[2], AXP_REG_T9); -+ assemble_tokens (extXl_op[lgsize], newtok, 3, 1); -+ -+ /* Emit "extXh $t10, $at, $t10". */ -+ set_tok_reg (newtok[0], AXP_REG_T10); -+ set_tok_reg (newtok[2], AXP_REG_T10); -+ assemble_tokens (extXh_op[lgsize], newtok, 3, 1); -+ -+ /* Emit "or $t9, $t10, targ". */ -+ set_tok_reg (newtok[0], AXP_REG_T9); -+ set_tok_reg (newtok[1], AXP_REG_T10); -+ newtok[2] = tok[0]; -+ assemble_tokens ("or", newtok, 3, 1); -+} -+ -+/* Load an integral value from an unaligned address as a signed value. -+ Note that quads should get funneled to the unsigned load since we -+ don't have to do the sign extension. */ -+ -+static void -+emit_uldX (const expressionS *tok, int ntok, const void *vlgsize) -+{ -+ emit_uldXu (tok, ntok, vlgsize); -+ assemble_tokens (sextX_op[(long) vlgsize], tok, 1, 1); -+} -+ -+/* Implement the ldil macro. */ -+ -+static void -+emit_ldil (const expressionS *tok, int ntok, -+ const void *unused ATTRIBUTE_UNUSED) -+{ -+ expressionS newtok[2]; -+ -+ memcpy (newtok, tok, sizeof (newtok)); -+ newtok[1].X_add_number = sign_extend_32 (tok[1].X_add_number); -+ -+ assemble_tokens ("ldi", newtok, ntok, 1); -+} -+ -+/* Store a half-word or byte. */ -+ -+static void -+emit_stX (const expressionS *tok, int ntok, const void *vlgsize) -+{ -+ int lgsize = (int) (long) vlgsize; -+ -+ if (sw_64_target & AXP_OPCODE_SW6) -+ emit_loadstore (tok, ntok, stX_op[lgsize]); -+ else -+ { -+ expressionS newtok[3]; -+ struct sw_64_insn insn; -+ int basereg; -+ long lituse; -+ -+ if (sw_64_noat_on) -+ as_bad (_ ("macro requires $at register while noat in effect")); -+ -+ if (ntok == 2) -+ basereg -+ = (tok[1].X_op == O_constant ? AXP_REG_ZERO : sw_64_gp_register); -+ else -+ basereg = tok[2].X_add_number; -+ -+ /* Emit "ldi $at, exp". */ -+ lituse = load_expression (AXP_REG_AT, &tok[1], &basereg, NULL, "ldi"); -+ -+ /* Emit "ldl_u $t9, 0 ($at)". */ -+ set_tok_reg (newtok[0], AXP_REG_T9); -+ set_tok_const (newtok[1], 0); -+ set_tok_preg (newtok[2], basereg); -+ assemble_tokens_to_insn ("ldl_u", newtok, 3, &insn); -+ -+ if (lituse) -+ { -+ gas_assert (insn.nfixups < MAX_INSN_FIXUPS); -+ insn.fixups[insn.nfixups].reloc = DUMMY_RELOC_LITUSE_BASE; -+ insn.fixups[insn.nfixups].exp.X_op = O_absent; -+ insn.nfixups++; -+ insn.sequence = lituse; -+ } -+ -+ emit_insn (&insn); -+ -+ /* Emit "insXl src, $at, $t10". */ -+ newtok[0] = tok[0]; -+ set_tok_reg (newtok[1], basereg); -+ set_tok_reg (newtok[2], AXP_REG_T10); -+ assemble_tokens_to_insn (insXl_op[lgsize], newtok, 3, &insn); -+ -+ if (lituse) -+ { -+ gas_assert (insn.nfixups < MAX_INSN_FIXUPS); -+ insn.fixups[insn.nfixups].reloc = DUMMY_RELOC_LITUSE_BYTOFF; -+ insn.fixups[insn.nfixups].exp.X_op = O_absent; -+ insn.nfixups++; -+ insn.sequence = lituse; -+ } -+ -+ emit_insn (&insn); -+ -+ /* Emit "mskXl $t9, $at, $t9". */ -+ set_tok_reg (newtok[0], AXP_REG_T9); -+ newtok[2] = newtok[0]; -+ assemble_tokens_to_insn (mskXl_op[lgsize], newtok, 3, &insn); -+ -+ if (lituse) -+ { -+ gas_assert (insn.nfixups < MAX_INSN_FIXUPS); -+ insn.fixups[insn.nfixups].reloc = DUMMY_RELOC_LITUSE_BYTOFF; -+ insn.fixups[insn.nfixups].exp.X_op = O_absent; -+ insn.nfixups++; -+ insn.sequence = lituse; -+ } -+ -+ emit_insn (&insn); -+ -+ /* Emit "or $t9, $t10, $t9". */ -+ set_tok_reg (newtok[1], AXP_REG_T10); -+ assemble_tokens ("or", newtok, 3, 1); -+ -+ /* Emit "stq_u $t9, 0 ($at). */ -+ set_tok_const (newtok[1], 0); -+ set_tok_preg (newtok[2], AXP_REG_AT); -+ assemble_tokens_to_insn ("stl_u", newtok, 3, &insn); -+ -+ if (lituse) -+ { -+ gas_assert (insn.nfixups < MAX_INSN_FIXUPS); -+ insn.fixups[insn.nfixups].reloc = DUMMY_RELOC_LITUSE_BASE; -+ insn.fixups[insn.nfixups].exp.X_op = O_absent; -+ insn.nfixups++; -+ insn.sequence = lituse; -+ } -+ -+ emit_insn (&insn); -+ } -+} -+ -+/* Store an integer to an unaligned address. */ -+ -+static void -+emit_ustX (const expressionS *tok, int ntok, const void *vlgsize) -+{ -+ int lgsize = (int) (long) vlgsize; -+ expressionS newtok[3]; -+ -+ /* Emit "ldi $at, exp". */ -+ memcpy (newtok, tok, sizeof (expressionS) * ntok); -+ newtok[0].X_add_number = AXP_REG_AT; -+ assemble_tokens ("ldi", newtok, ntok, 1); -+ -+ /* Emit "ldl_u $9, 0 ($at)". */ -+ set_tok_reg (newtok[0], AXP_REG_T9); -+ set_tok_const (newtok[1], 0); -+ set_tok_preg (newtok[2], AXP_REG_AT); -+ assemble_tokens ("ldl_u", newtok, 3, 1); -+ -+ /* Emit "ldl_u $10, size-1 ($at)". */ -+ set_tok_reg (newtok[0], AXP_REG_T10); -+ set_tok_const (newtok[1], (1 << lgsize) - 1); -+ assemble_tokens ("ldl_u", newtok, 3, 1); -+ -+ /* Emit "insXl src, $at, $t11". */ -+ newtok[0] = tok[0]; -+ set_tok_reg (newtok[1], AXP_REG_AT); -+ set_tok_reg (newtok[2], AXP_REG_T11); -+ assemble_tokens (insXl_op[lgsize], newtok, 3, 1); -+ -+ /* Emit "insXh src, $at, $t12". */ -+ set_tok_reg (newtok[2], AXP_REG_T12); -+ assemble_tokens (insXh_op[lgsize], newtok, 3, 1); -+ -+ /* Emit "mskXl $t9, $at, $t9". */ -+ set_tok_reg (newtok[0], AXP_REG_T9); -+ newtok[2] = newtok[0]; -+ assemble_tokens (mskXl_op[lgsize], newtok, 3, 1); -+ -+ /* Emit "mskXh $t10, $at, $t10". */ -+ set_tok_reg (newtok[0], AXP_REG_T10); -+ newtok[2] = newtok[0]; -+ assemble_tokens (mskXh_op[lgsize], newtok, 3, 1); -+ -+ /* Emit "or $t9, $t11, $t9". */ -+ set_tok_reg (newtok[0], AXP_REG_T9); -+ set_tok_reg (newtok[1], AXP_REG_T11); -+ newtok[2] = newtok[0]; -+ assemble_tokens ("or", newtok, 3, 1); -+ -+ /* Emit "or $t10, $t12, $t10". */ -+ set_tok_reg (newtok[0], AXP_REG_T10); -+ set_tok_reg (newtok[1], AXP_REG_T12); -+ newtok[2] = newtok[0]; -+ assemble_tokens ("or", newtok, 3, 1); -+ -+ /* Emit "stq_u $t10, size-1 ($at)". */ -+ set_tok_reg (newtok[0], AXP_REG_T10); -+ set_tok_const (newtok[1], (1 << lgsize) - 1); -+ set_tok_preg (newtok[2], AXP_REG_AT); -+ assemble_tokens ("stl_u", newtok, 3, 1); -+ -+ /* Emit "stq_u $t9, 0 ($at)". */ -+ set_tok_reg (newtok[0], AXP_REG_T9); -+ set_tok_const (newtok[1], 0); -+ assemble_tokens ("stl_u", newtok, 3, 1); -+} -+ -+/* Sign extend a half-word or byte. The 32-bit sign extend is -+ implemented as "addl $31, $r, $t" in the opcode table. */ -+ -+static void -+emit_sextX (const expressionS *tok, int ntok, const void *vlgsize) -+{ -+ long lgsize = (long) vlgsize; -+ -+ if (sw_64_target & AXP_OPCODE_SW6) -+ assemble_tokens (sextX_op[lgsize], tok, ntok, 0); -+ else -+ { -+ int bitshift = 64 - 8 * (1 << lgsize); -+ expressionS newtok[3]; -+ -+ /* Emit "sll src,bits,dst". */ -+ newtok[0] = tok[0]; -+ set_tok_const (newtok[1], bitshift); -+ newtok[2] = tok[ntok - 1]; -+ assemble_tokens ("sll", newtok, 3, 1); -+ -+ /* Emit "sra dst,bits,dst". */ -+ newtok[0] = newtok[2]; -+ assemble_tokens ("sra", newtok, 3, 1); -+ } -+} -+ -+static void -+emit_vlogx (const expressionS *tok, int ntok, -+ const void *unused ATTRIBUTE_UNUSED) -+{ -+ unsigned int mask = 0; -+ struct sw_64_insn insn; -+ assemble_tokens_to_insn ("vlog", tok, ntok - 1, &insn); -+ mask = (tok[4].X_add_number >> 6) << 26; -+ mask += (tok[4].X_add_number & 0x3f) << 10; -+ insn.insn |= mask; -+ emit_insn (&insn); -+} -+ -+/* Implement the division and modulus macros. */ -+ -+#ifdef OBJ_EVAX -+ -+/* Make register usage like in normal procedure call. -+ Don't clobber PV and RA. */ -+ -+static void -+emit_division (const expressionS *tok, int ntok, const void *symname) -+{ -+ if (strcmp (sw_64_target_name, "sw6a") == 0 -+ || strcmp (sw_64_target_name, "sw6b") == 0) -+ { -+ /* DIVISION and MODULUS. Yech. -+ -+ Convert -+ OP x,y,result -+ to -+ mov x,R16 # if x != R16 -+ mov y,R17 # if y != R17 -+ ldi AT,__OP -+ call AT,(AT),0 -+ mov R0,result -+ -+ with appropriate optimizations if R0,R16,R17 are the registers -+ specified by the compiler. */ -+ -+ int xr, yr, rr; -+ symbolS *sym; -+ expressionS newtok[3]; -+ -+ xr = regno (tok[0].X_add_number); -+ yr = regno (tok[1].X_add_number); -+ -+ if (ntok < 3) -+ rr = xr; -+ else -+ rr = regno (tok[2].X_add_number); -+ -+ /* Move the operands into the right place. */ -+ if (yr == AXP_REG_R16 && xr == AXP_REG_R17) -+ { -+ /* They are in exactly the wrong order -- swap through AT. */ -+ if (sw_64_noat_on) -+ as_bad (_ ("macro requires $at register while noat in effect")); -+ -+ set_tok_reg (newtok[0], AXP_REG_R16); -+ set_tok_reg (newtok[1], AXP_REG_AT); -+ assemble_tokens ("mov", newtok, 2, 1); -+ -+ set_tok_reg (newtok[0], AXP_REG_R17); -+ set_tok_reg (newtok[1], AXP_REG_R16); -+ assemble_tokens ("mov", newtok, 2, 1); -+ -+ set_tok_reg (newtok[0], AXP_REG_AT); -+ set_tok_reg (newtok[1], AXP_REG_R17); -+ assemble_tokens ("mov", newtok, 2, 1); -+ } -+ else -+ { -+ if (yr == AXP_REG_R16) -+ { -+ set_tok_reg (newtok[0], AXP_REG_R16); -+ set_tok_reg (newtok[1], AXP_REG_R17); -+ assemble_tokens ("mov", newtok, 2, 1); -+ } -+ -+ if (xr != AXP_REG_R16) -+ { -+ set_tok_reg (newtok[0], xr); -+ set_tok_reg (newtok[1], AXP_REG_R16); -+ assemble_tokens ("mov", newtok, 2, 1); -+ } -+ -+ if (yr != AXP_REG_R16 && yr != AXP_REG_R17) -+ { -+ set_tok_reg (newtok[0], yr); -+ set_tok_reg (newtok[1], AXP_REG_R17); -+ assemble_tokens ("mov", newtok, 2, 1); -+ } -+ } -+ -+ sym = symbol_find_or_make ((const char *) symname); -+ -+ set_tok_reg (newtok[0], AXP_REG_AT); -+ set_tok_sym (newtok[1], sym, 0); -+ assemble_tokens ("ldi", newtok, 2, 1); -+ -+ /* Call the division routine. */ -+ set_tok_reg (newtok[0], AXP_REG_AT); -+ set_tok_cpreg (newtok[1], AXP_REG_AT); -+ set_tok_const (newtok[2], 0); -+ assemble_tokens ("call", newtok, 3, 1); -+ -+ /* Move the result to the right place. */ -+ if (rr != AXP_REG_R0) -+ { -+ set_tok_reg (newtok[0], AXP_REG_R0); -+ set_tok_reg (newtok[1], rr); -+ assemble_tokens ("mov", newtok, 2, 1); -+ } -+ } -+ else -+ { -+ if (strcmp (symname, "__divw") == 0) -+ assemble_tokens ("divw", tok, 3, 0); -+ if (strcmp (symname, "__divl") == 0) -+ assemble_tokens ("divl", tok, 3, 0); -+ if (strcmp (symname, "__remw") == 0) -+ assemble_tokens ("remw", tok, 3, 0); -+ if (strcmp (symname, "__reml") == 0) -+ assemble_tokens ("reml", tok, 3, 0); -+ } -+} -+ -+#else /* !OBJ_EVAX */ -+ -+static void -+emit_division (const expressionS *tok, int ntok, const void *symname) -+{ -+ if (strcmp (sw_64_target_name, "sw6a") == 0 -+ || strcmp (sw_64_target_name, "sw6b") == 0) -+ { -+ /* DIVISION and MODULUS. Yech. -+ Convert -+ OP x,y,result -+ to -+ ldi pv,__OP -+ mov x,t10 -+ mov y,t11 -+ call t9,(pv),__OP -+ mov t12,result -+ -+ with appropriate optimizations if t10,t11,t12 are the registers -+ specified by the compiler. */ -+ -+ int xr, yr, rr; -+ symbolS *sym; -+ expressionS newtok[3]; -+ -+ xr = regno (tok[0].X_add_number); -+ yr = regno (tok[1].X_add_number); -+ -+ if (ntok < 3) -+ rr = xr; -+ else -+ rr = regno (tok[2].X_add_number); -+ -+ sym = symbol_find_or_make ((const char *) symname); -+ -+ /* Move the operands into the right place. */ -+ if (yr == AXP_REG_T10 && xr == AXP_REG_T11) -+ { -+ /* They are in exactly the wrong order -- swap through AT. */ -+ if (sw_64_noat_on) -+ as_bad (_ ("macro requires $at register while noat in effect")); -+ -+ set_tok_reg (newtok[0], AXP_REG_T10); -+ set_tok_reg (newtok[1], AXP_REG_AT); -+ assemble_tokens ("mov", newtok, 2, 1); -+ -+ set_tok_reg (newtok[0], AXP_REG_T11); -+ set_tok_reg (newtok[1], AXP_REG_T10); -+ assemble_tokens ("mov", newtok, 2, 1); -+ -+ set_tok_reg (newtok[0], AXP_REG_AT); -+ set_tok_reg (newtok[1], AXP_REG_T11); -+ assemble_tokens ("mov", newtok, 2, 1); -+ } -+ else -+ { -+ if (yr == AXP_REG_T10) -+ { -+ set_tok_reg (newtok[0], AXP_REG_T10); -+ set_tok_reg (newtok[1], AXP_REG_T11); -+ assemble_tokens ("mov", newtok, 2, 1); -+ } -+ -+ if (xr != AXP_REG_T10) -+ { -+ set_tok_reg (newtok[0], xr); -+ set_tok_reg (newtok[1], AXP_REG_T10); -+ assemble_tokens ("mov", newtok, 2, 1); -+ } -+ -+ if (yr != AXP_REG_T10 && yr != AXP_REG_T11) -+ { -+ set_tok_reg (newtok[0], yr); -+ set_tok_reg (newtok[1], AXP_REG_T11); -+ assemble_tokens ("mov", newtok, 2, 1); -+ } -+ } -+ -+ /* Call the division routine. */ -+ set_tok_reg (newtok[0], AXP_REG_T9); -+ set_tok_sym (newtok[1], sym, 0); -+ assemble_tokens ("call", newtok, 2, 1); -+ -+ /* Reload the GP register. */ -+#ifdef OBJ_AOUT -+ FIXME -+#endif -+#if defined(OBJ_ECOFF) || defined(OBJ_ELF) -+ set_tok_reg (newtok[0], sw_64_gp_register); -+ set_tok_const (newtok[1], 0); -+ set_tok_preg (newtok[2], AXP_REG_T9); -+ assemble_tokens ("ldgp", newtok, 3, 1); -+#endif -+ -+ /* Move the result to the right place. */ -+ if (rr != AXP_REG_T12) -+ { -+ set_tok_reg (newtok[0], AXP_REG_T12); -+ set_tok_reg (newtok[1], rr); -+ assemble_tokens ("mov", newtok, 2, 1); -+ } -+ } -+ else -+ { -+ if (strcmp (symname, "__divw") == 0) -+ assemble_tokens ("divw", tok, 3, 0); -+ if (strcmp (symname, "__divl") == 0) -+ assemble_tokens ("divl", tok, 3, 0); -+ if (strcmp (symname, "__remw") == 0) -+ assemble_tokens ("remw", tok, 3, 0); -+ if (strcmp (symname, "__reml") == 0) -+ assemble_tokens ("reml", tok, 3, 0); -+ } -+} -+ -+#endif /* !OBJ_EVAX */ -+ -+/* The call and jmp macros differ from their instruction counterparts -+ in that they can load the target address and default most -+ everything. */ -+ -+static void -+emit_jsrjmp (const expressionS *tok, int ntok, const void *vopname) -+{ -+ const char *opname = (const char *) vopname; -+ struct sw_64_insn insn; -+ expressionS newtok[3]; -+ int r, tokidx = 0; -+ long lituse = 0; -+ -+ if (tokidx < ntok && tok[tokidx].X_op == O_register) -+ r = regno (tok[tokidx++].X_add_number); -+ else -+ r = strcmp (opname, "jmp") == 0 ? AXP_REG_ZERO : AXP_REG_RA; -+ -+ set_tok_reg (newtok[0], r); -+ -+ if (tokidx < ntok -+ && (tok[tokidx].X_op == O_pregister || tok[tokidx].X_op == O_cpregister)) -+ r = regno (tok[tokidx++].X_add_number); -+#ifdef OBJ_EVAX -+ /* Keep register if call $n.. */ -+#else -+ else -+ { -+ int basereg = sw_64_gp_register; -+ lituse = load_expression (r = AXP_REG_PV, &tok[tokidx], &basereg, NULL, -+ opname); -+ } -+#endif -+ -+ set_tok_cpreg (newtok[1], r); -+ -+#ifndef OBJ_EVAX -+ if (tokidx < ntok) -+ newtok[2] = tok[tokidx]; -+ else -+#endif -+ set_tok_const (newtok[2], 0); -+ -+ assemble_tokens_to_insn (opname, newtok, 3, &insn); -+ -+ if (lituse) -+ { -+ gas_assert (insn.nfixups < MAX_INSN_FIXUPS); -+ insn.fixups[insn.nfixups].reloc = DUMMY_RELOC_LITUSE_JSR; -+ insn.fixups[insn.nfixups].exp.X_op = O_absent; -+ insn.nfixups++; -+ insn.sequence = lituse; -+ } -+ -+#ifdef OBJ_EVAX -+ if (sw_64_flag_replace && r == AXP_REG_RA && tok[tokidx].X_add_symbol -+ && sw_64_linkage_symbol) -+ { -+ /* Create a BOH reloc for 'call $27,NAME'. */ -+ const char *symname = S_GET_NAME (tok[tokidx].X_add_symbol); -+ int symlen = strlen (symname); -+ char *ensymname; -+ -+ /* Build the entry name as 'NAME..en'. */ -+ ensymname = XNEWVEC (char, symlen + 5); -+ memcpy (ensymname, symname, symlen); -+ memcpy (ensymname + symlen, "..en", 5); -+ -+ gas_assert (insn.nfixups < MAX_INSN_FIXUPS); -+ if (insn.nfixups > 0) -+ { -+ memmove (&insn.fixups[1], &insn.fixups[0], -+ sizeof (struct sw_64_fixup) * insn.nfixups); -+ } -+ -+ /* The fixup must be the same as the BFD_RELOC_SW_64_NOP -+ case in load_expression. See B.4.5.2 of the OpenVMS -+ Linker Utility Manual. */ -+ insn.fixups[0].reloc = BFD_RELOC_SW_64_BOH; -+ insn.fixups[0].exp.X_op = O_symbol; -+ insn.fixups[0].exp.X_add_symbol = symbol_find_or_make (ensymname); -+ insn.fixups[0].exp.X_add_number = 0; -+ insn.fixups[0].xtrasym = sw_64_linkage_symbol; -+ insn.fixups[0].procsym = sw_64_evax_proc->symbol; -+ insn.nfixups++; -+ sw_64_linkage_symbol = 0; -+ free (ensymname); -+ } -+#endif -+ -+ emit_insn (&insn); -+} -+ -+/* The ret and jcr instructions differ from their instruction -+ counterparts in that everything can be defaulted. */ -+ -+static void -+emit_retjcr (const expressionS *tok, int ntok, const void *vopname) -+{ -+ const char *opname = (const char *) vopname; -+ expressionS newtok[3]; -+ int r, tokidx = 0; -+ -+ if (tokidx < ntok && tok[tokidx].X_op == O_register) -+ r = regno (tok[tokidx++].X_add_number); -+ else -+ r = AXP_REG_ZERO; -+ -+ set_tok_reg (newtok[0], r); -+ -+ if (tokidx < ntok -+ && (tok[tokidx].X_op == O_pregister || tok[tokidx].X_op == O_cpregister)) -+ r = regno (tok[tokidx++].X_add_number); -+ else -+ r = AXP_REG_RA; -+ -+ set_tok_cpreg (newtok[1], r); -+ -+ if (tokidx < ntok) -+ newtok[2] = tok[tokidx]; -+ else -+ set_tok_const (newtok[2], strcmp (opname, "ret") == 0); -+ -+ assemble_tokens (opname, newtok, 3, 0); -+} -+ -+/* Implement the ldgp macro. */ -+ -+static void -+emit_ldgp (const expressionS *tok ATTRIBUTE_UNUSED, int ntok ATTRIBUTE_UNUSED, -+ const void *unused ATTRIBUTE_UNUSED) -+{ -+#ifdef OBJ_AOUT -+ FIXME -+#endif -+#if defined (OBJ_ECOFF) || defined (OBJ_ELF) -+ /* from "ldgp r1,n (r2)", generate "ldih r1,X (R2); ldi r1,Y (r1)" -+ with appropriate constants and relocations. */ -+ struct sw_64_insn insn; -+ expressionS newtok[3]; -+ expressionS addend; -+ -+#ifdef OBJ_ECOFF -+ if (regno (tok[2].X_add_number) == AXP_REG_PV) -+ ecoff_set_gp_prolog_size (0); -+#endif -+ -+ newtok[0] = tok[0]; -+ set_tok_const (newtok[1], 0); -+ newtok[2] = tok[2]; -+ -+ assemble_tokens_to_insn ("ldih", newtok, 3, &insn); -+ -+ addend = tok[1]; -+ -+#ifdef OBJ_ECOFF -+ if (addend.X_op != O_constant) -+ as_bad (_ ("can not resolve expression")); -+ addend.X_op = O_symbol; -+ addend.X_add_symbol = sw_64_gp_symbol; -+#endif -+ -+ insn.nfixups = 1; -+ insn.fixups[0].exp = addend; -+ insn.fixups[0].reloc = BFD_RELOC_SW_64_GPDISP_HI16; -+ insn.sequence = next_sequence_num; -+ -+ emit_insn (&insn); -+ -+ set_tok_preg (newtok[2], tok[0].X_add_number); -+ -+ assemble_tokens_to_insn ("ldi", newtok, 3, &insn); -+ -+#ifdef OBJ_ECOFF -+ addend.X_add_number += 4; -+#endif -+ -+ insn.nfixups = 1; -+ insn.fixups[0].exp = addend; -+ insn.fixups[0].reloc = BFD_RELOC_SW_64_GPDISP_LO16; -+ insn.sequence = next_sequence_num--; -+ -+ emit_insn (&insn); -+#endif /* OBJ_ECOFF || OBJ_ELF */ -+} -+ -+/* The macro table. */ -+ -+static const struct sw_64_macro sw_64_macros[] = -+{ -+ { "vlog", emit_vlogx, NULL, -+ { MACRO_FPR, MACRO_FPR, MACRO_FPR, MACRO_FPR, MACRO_EOA } }, -+/* Load/Store macros. */ -+ { "ldi", emit_ldi, NULL, -+ { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } }, -+ { "ldih", emit_ldih, NULL, -+ { MACRO_IR, MACRO_EXP, MACRO_EOA } }, -+ -+ { "ldw", emit_ir_load, "ldw", -+ { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } }, -+ { "ldl", emit_ir_load, "ldl", -+ { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } }, -+ { "ldl_u", emit_ir_load, "ldl_u", -+ { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } }, -+ { "ldw_inc", emit_ir_load, "ldw_inc", -+ { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } }, -+ { "ldl_inc", emit_ir_load, "ldl_inc", -+ { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } }, -+ { "ldw_dec", emit_ir_load, "ldw_dec", -+ { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } }, -+ { "ldl_dec", emit_ir_load, "ldl_dec", -+ { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } }, -+ { "ldw_set", emit_ir_load, "ldw_set", -+ { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } }, -+ { "ldl_set", emit_ir_load, "ldl_set", -+ { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } }, -+ { "flds", emit_loadstore, "flds", -+ { MACRO_FPR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } }, -+ { "fldd", emit_loadstore, "fldd", -+ { MACRO_FPR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } }, -+ -+ { "ldb", emit_ldX, (void *) 0, -+ { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } }, -+ { "ldh", emit_ldX, (void *) 1, -+ { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } }, -+ -+ { "ldgp", emit_ldgp, NULL, -+ { MACRO_IR, MACRO_EXP, MACRO_PIR, MACRO_EOA } }, -+ { "stw", emit_loadstore, "stw", -+ { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } }, -+ { "stl", emit_loadstore, "stl", -+ { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } }, -+ { "fsts", emit_loadstore, "fsts", -+ { MACRO_FPR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } }, -+ { "fstd", emit_loadstore, "fstd", -+ { MACRO_FPR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } }, -+ { "stb", emit_stX, (void *) 0, -+ { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } }, -+ -+/* Arithmetic macros. */ -+ { "sextb", emit_sextX, (void *) 0, -+ { MACRO_IR, MACRO_IR, MACRO_EOA, -+ MACRO_IR, MACRO_EOA, -+ /* MACRO_EXP, MACRO_IR, MACRO_EOA */ } }, -+ { "sexth", emit_sextX, (void *) 1, -+ { MACRO_IR, MACRO_IR, MACRO_EOA, -+ MACRO_IR, MACRO_EOA, -+ /* MACRO_EXP, MACRO_IR, MACRO_EOA */ } }, -+ -+ { "divw", emit_division, "__divw", -+ { MACRO_IR, MACRO_IR, MACRO_IR, MACRO_EOA, -+ MACRO_IR, MACRO_IR, MACRO_EOA, -+ /* MACRO_IR, MACRO_EXP, MACRO_IR, MACRO_EOA, -+ MACRO_IR, MACRO_EXP, MACRO_EOA */ } }, -+ { "divwu", emit_division, "__divwu", -+ { MACRO_IR, MACRO_IR, MACRO_IR, MACRO_EOA, -+ MACRO_IR, MACRO_IR, MACRO_EOA, -+ /* MACRO_IR, MACRO_EXP, MACRO_IR, MACRO_EOA, -+ MACRO_IR, MACRO_EXP, MACRO_EOA */ } }, -+ { "divl", emit_division, "__divl", -+ { MACRO_IR, MACRO_IR, MACRO_IR, MACRO_EOA, -+ MACRO_IR, MACRO_IR, MACRO_EOA, -+ /* MACRO_IR, MACRO_EXP, MACRO_IR, MACRO_EOA, -+ MACRO_IR, MACRO_EXP, MACRO_EOA */ } }, -+ { "divlu", emit_division, "__divlu", -+ { MACRO_IR, MACRO_IR, MACRO_IR, MACRO_EOA, -+ MACRO_IR, MACRO_IR, MACRO_EOA, -+ /* MACRO_IR, MACRO_EXP, MACRO_IR, MACRO_EOA, -+ MACRO_IR, MACRO_EXP, MACRO_EOA */ } }, -+ { "remw", emit_division, "__remw", -+ { MACRO_IR, MACRO_IR, MACRO_IR, MACRO_EOA, -+ MACRO_IR, MACRO_IR, MACRO_EOA, -+ /* MACRO_IR, MACRO_EXP, MACRO_IR, MACRO_EOA, -+ MACRO_IR, MACRO_EXP, MACRO_EOA */ } }, -+ { "remwu", emit_division, "__remwu", -+ { MACRO_IR, MACRO_IR, MACRO_IR, MACRO_EOA, -+ MACRO_IR, MACRO_IR, MACRO_EOA, -+ /* MACRO_IR, MACRO_EXP, MACRO_IR, MACRO_EOA, -+ MACRO_IR, MACRO_EXP, MACRO_EOA */ } }, -+ { "reml", emit_division, "__reml", -+ { MACRO_IR, MACRO_IR, MACRO_IR, MACRO_EOA, -+ MACRO_IR, MACRO_IR, MACRO_EOA, -+ /* MACRO_IR, MACRO_EXP, MACRO_IR, MACRO_EOA, -+ MACRO_IR, MACRO_EXP, MACRO_EOA */ } }, -+ { "remlu", emit_division, "__remlu", -+ { MACRO_IR, MACRO_IR, MACRO_IR, MACRO_EOA, -+ MACRO_IR, MACRO_IR, MACRO_EOA, -+ /* MACRO_IR, MACRO_EXP, MACRO_IR, MACRO_EOA, -+ MACRO_IR, MACRO_EXP, MACRO_EOA */ } }, -+ -+ { "call", emit_jsrjmp, "call", -+ { MACRO_PIR, MACRO_EXP, MACRO_EOA, -+ MACRO_PIR, MACRO_EOA, -+ MACRO_IR, MACRO_EXP, MACRO_EOA, -+ MACRO_EXP, MACRO_EOA } }, -+ { "jmp", emit_jsrjmp, "jmp", -+ { MACRO_PIR, MACRO_EXP, MACRO_EOA, -+ MACRO_PIR, MACRO_EOA, -+ MACRO_IR, MACRO_EXP, MACRO_EOA, -+ MACRO_EXP, MACRO_EOA } }, -+ { "ret", emit_retjcr, "ret", -+ { MACRO_IR, MACRO_EXP, MACRO_EOA, -+ MACRO_IR, MACRO_EOA, -+ MACRO_PIR, MACRO_EXP, MACRO_EOA, -+ MACRO_PIR, MACRO_EOA, -+ MACRO_EXP, MACRO_EOA, -+ MACRO_EOA } }, -+}; -+ -+static const unsigned int sw_64_num_macros -+ = sizeof (sw_64_macros) / sizeof (*sw_64_macros); -+ -+/* Search forward through all variants of a macro looking for a syntax -+ match. */ -+ -+static const struct sw_64_macro * -+find_macro_match (const struct sw_64_macro *first_macro, const expressionS *tok, -+ int *pntok) -+ -+{ -+ const struct sw_64_macro *macro = first_macro; -+ int ntok = *pntok; -+ -+ do -+ { -+ const enum sw_64_macro_arg *arg = macro->argsets; -+ int tokidx = 0; -+ -+ while (*arg) -+ { -+ switch (*arg) -+ { -+ case MACRO_EOA: -+ if (tokidx == ntok) -+ return macro; -+ else -+ tokidx = 0; -+ break; -+ -+ /* Index register. */ -+ case MACRO_IR: -+ if (tokidx >= ntok || tok[tokidx].X_op != O_register -+ || !is_ir_num (tok[tokidx].X_add_number)) -+ goto match_failed; -+ ++tokidx; -+ break; -+ -+ /* Parenthesized index register. */ -+ case MACRO_PIR: -+ if (tokidx >= ntok || tok[tokidx].X_op != O_pregister -+ || !is_ir_num (tok[tokidx].X_add_number)) -+ goto match_failed; -+ ++tokidx; -+ break; -+ -+ /* Optional parenthesized index register. */ -+ case MACRO_OPIR: -+ if (tokidx < ntok && tok[tokidx].X_op == O_pregister -+ && is_ir_num (tok[tokidx].X_add_number)) -+ ++tokidx; -+ break; -+ -+ /* Leading comma with a parenthesized index register. */ -+ case MACRO_CPIR: -+ if (tokidx >= ntok || tok[tokidx].X_op != O_cpregister -+ || !is_ir_num (tok[tokidx].X_add_number)) -+ goto match_failed; -+ ++tokidx; -+ break; -+ -+ /* Floating point register. */ -+ case MACRO_FPR: -+ if (tokidx >= ntok || tok[tokidx].X_op != O_register -+ || !is_fpr_num (tok[tokidx].X_add_number)) -+ goto match_failed; -+ ++tokidx; -+ break; -+ -+ /* Normal expression. */ -+ case MACRO_EXP: -+ if (tokidx >= ntok) -+ goto match_failed; -+ switch (tok[tokidx].X_op) -+ { -+ case O_illegal: -+ case O_absent: -+ case O_register: -+ case O_pregister: -+ case O_cpregister: -+ case O_literal: -+ case O_lituse_base: -+ case O_lituse_bytoff: -+ case O_lituse_jsr: -+ case O_gpdisp: -+ case O_gprelhigh: -+ case O_gprellow: -+ case O_gprel: -+ case O_samegp: -+ goto match_failed; -+ -+ default: -+ break; -+ } -+ ++tokidx; -+ break; -+ -+ match_failed: -+ while (*arg != MACRO_EOA) -+ ++arg; -+ tokidx = 0; -+ break; -+ } -+ ++arg; -+ } -+ } while (++macro - sw_64_macros < (int) sw_64_num_macros -+ && !strcmp (macro->name, first_macro->name)); -+ -+ return NULL; -+} -+ -+/* Given an opcode name and a pre-tokenized set of arguments, take the -+ opcode all the way through emission. */ -+static void -+assemble_tokens (const char *opname, expressionS *tok, int ntok, -+ int local_macros_on) -+{ -+ int found_something = 0; -+ const struct sw_64_opcode *opcode; -+ const struct sw_64_macro *macro; -+ int cpumatch = 1; -+ extended_bfd_reloc_code_real_type reloc = BFD_RELOC_UNUSED; -+ -+#ifdef RELOC_OP_P -+ /* If a user-specified relocation is present, this is not a macro. */ -+ if (ntok && USER_RELOC_P (tok[ntok - 1].X_op)) -+ { -+ if (sw_64_literalgot_on) -+ { -+ if (tok[ntok - 1].X_op == O_literal) -+ { -+ struct sw_64_insn insn; -+ expressionS newtok[3]; -+ newtok[0] = tok[0]; -+ set_tok_const (newtok[1], 0); -+ set_tok_preg (newtok[2], sw_64_gp_register); -+ assemble_tokens_to_insn ("ldih", newtok, 3, &insn); -+ insn.nfixups = 1; -+ insn.fixups[0].reloc = BFD_RELOC_SW_64_ELF_LITERAL_GOT; -+ insn.sequence = tok[ntok - 1].X_add_number; -+ emit_insn (&insn); -+ tok[2].X_add_number = tok[0].X_add_number; -+ } -+ } -+ if (sw_64_tlsrelgot_gottprel_on) -+ { -+ if (tok[ntok - 1].X_op == O_gottprel) -+ { -+ struct sw_64_insn insn; -+ expressionS newtok[3]; -+ newtok[0] = tok[0]; -+ set_tok_const (newtok[1], 0); -+ set_tok_preg (newtok[2], sw_64_gp_register); -+ assemble_tokens_to_insn ("ldih", newtok, 3, &insn); -+ insn.nfixups = 1; -+ insn.fixups[0].reloc = BFD_RELOC_SW_64_TLSREL_GOT; -+ insn.sequence = tok[ntok - 1].X_add_number; -+ emit_insn (&insn); -+ tok[2].X_add_number = tok[0].X_add_number; -+ } -+ } -+ -+ if (sw_64_tlsrelgot_gotdtprel_on) -+ { -+ if (tok[ntok - 1].X_op == O_gotdtprel) -+ { -+ struct sw_64_insn insn; -+ expressionS newtok[3]; -+ newtok[0] = tok[0]; -+ set_tok_const (newtok[1], 0); -+ set_tok_preg (newtok[2], sw_64_gp_register); -+ assemble_tokens_to_insn ("ldih", newtok, 3, &insn); -+ insn.nfixups = 1; -+ insn.fixups[0].reloc = BFD_RELOC_SW_64_TLSREL_GOT; -+ insn.sequence = tok[ntok - 1].X_add_number; -+ emit_insn (&insn); -+ tok[2].X_add_number = tok[0].X_add_number; -+ } -+ } -+ -+ if (sw_64_tlsrelgot_tlsgd_on) -+ { -+ if (tok[ntok - 1].X_op == O_tlsgd) -+ { -+ struct sw_64_insn insn; -+ expressionS newtok[3]; -+ newtok[0] = tok[0]; -+ set_tok_const (newtok[1], 0); -+ set_tok_preg (newtok[2], sw_64_gp_register); -+ assemble_tokens_to_insn ("ldih", newtok, 3, &insn); -+ insn.nfixups = 1; -+ insn.fixups[0].reloc = BFD_RELOC_SW_64_TLSREL_GOT; -+ insn.sequence = tok[ntok - 1].X_add_number; -+ emit_insn (&insn); -+ tok[2].X_add_number = tok[0].X_add_number; -+ } -+ } -+ -+ if (sw_64_tlsrelgot_tlsldm_on) -+ { -+ if (tok[ntok - 1].X_op == O_tlsldm) -+ { -+ struct sw_64_insn insn; -+ expressionS newtok[3]; -+ newtok[0] = tok[0]; -+ set_tok_const (newtok[1], 0); -+ set_tok_preg (newtok[2], sw_64_gp_register); -+ assemble_tokens_to_insn ("ldih", newtok, 3, &insn); -+ insn.nfixups = 1; -+ insn.fixups[0].reloc = BFD_RELOC_SW_64_TLSREL_GOT; -+ insn.sequence = tok[ntok - 1].X_add_number; -+ emit_insn (&insn); -+ tok[2].X_add_number = tok[0].X_add_number; -+ } -+ } -+ -+ if (sw_64_gprel16_on) -+ { -+ if (tok[ntok - 1].X_op == O_gprel) -+ { -+ if (strncmp (opname, "ldi", strlen ("ldi")) == 0 -+ || strncmp (opname, "ldw", strlen ("ldw")) == 0 -+ || strncmp (opname, "ldl", strlen ("ldl")) == 0) -+ { -+ struct sw_64_insn insn; -+ expressionS newtok[3]; -+ -+ newtok[0] = tok[0]; -+ newtok[1] = tok[1]; -+ set_tok_preg (newtok[2], sw_64_gp_register); -+ assemble_tokens_to_insn ("ldih", newtok, 3, &insn); -+ insn.nfixups = 1; -+ insn.fixups[0].reloc = BFD_RELOC_SW_64_GPREL_HI16; -+ emit_insn (&insn); -+ -+ tok[2].X_add_number = tok[0].X_add_number; -+ tok[ntok - 1].X_op = O_gprellow; -+ } -+ else if (strncmp (opname, "stw", strlen ("stw")) == 0 -+ || strncmp (opname, "stl", strlen ("stl")) == 0 -+ || strncmp (opname, "flds", strlen ("flds")) == 0 -+ || strncmp (opname, "fldd", strlen ("fldd")) == 0 -+ || strncmp (opname, "fsts", strlen ("fsts")) == 0 -+ || strncmp (opname, "fstd", strlen ("fstd")) == 0) -+ { -+ struct sw_64_insn insn; -+ expressionS newtok[3]; -+ -+ if (sw_64_noat_on) -+ as_warn (_ ( -+ "!gprelhi requires $at register while noat in effect")); -+ else -+ as_warn ( -+ _ ("assembler requires $28 register for the !gprelhi !")); -+ -+ set_tok_reg (newtok[0], 28); -+ newtok[1] = tok[1]; -+ set_tok_preg (newtok[2], sw_64_gp_register); -+ assemble_tokens_to_insn ("ldih", newtok, 3, &insn); -+ insn.nfixups = 1; -+ insn.fixups[0].reloc = BFD_RELOC_SW_64_GPREL_HI16; -+ emit_insn (&insn); -+ -+ tok[2].X_add_number = 28; -+ tok[ntok - 1].X_op = O_gprellow; -+ } -+ else -+ { -+ as_warn (_ ("!gprel16(change into gprelhi+gprello) donot " -+ "support this memory access instruction(%s).\n"), -+ opname); -+ } -+ } -+ } -+ -+ reloc = SW_64_RELOC_TABLE (tok[ntok - 1].X_op)->reloc; -+ ntok--; -+ } -+ else -+#endif -+ if (local_macros_on) -+ { -+ macro = ((const struct sw_64_macro *) str_hash_find (sw_64_macro_hash, -+ opname)); -+ if (macro) -+ { -+ found_something = 1; -+ macro = find_macro_match (macro, tok, &ntok); -+ if (macro) -+ { -+ (*macro->emit) (tok, ntok, macro->arg); -+ return; -+ } -+ } -+ } -+ -+ if (memcmp (opname, "vlog", 4) == 0) -+ { -+ unsigned long value; -+ unsigned long length = strchr (opname, 'g') - opname + 1; -+ value = strtol (opname + length, NULL, 16); -+ if (opname[length + 2] != '\0') -+ as_bad (_ ("%s, wrong truth number!!"), opname); -+ else if (value > 0xFF) -+ as_bad (_ ("%s, wrong truth number!!"), opname); -+ else if (value == 0 -+ && (opname[length] != '0' || opname[length + 1] != '0')) -+ as_bad (_ ("%s, wrong truth number!!"), opname); -+ macro = ((const struct sw_64_macro *) str_hash_find (sw_64_macro_hash, -+ "vlog")); -+ if (macro) -+ { -+ found_something = 1; -+ macro = find_macro_match (macro, tok, &ntok); -+ if (macro) -+ { -+ expressionS newtok[5]; -+ newtok[0] = tok[0]; -+ newtok[1] = tok[1]; -+ newtok[2] = tok[2]; -+ newtok[3] = tok[3]; -+ set_tok_const (newtok[4], value); -+ (*macro->emit) (newtok, ntok + 1, macro->arg); -+ return; -+ } -+ } -+ } -+ -+ /* Search opcodes. */ -+ opcode -+ = (const struct sw_64_opcode *) str_hash_find (sw_64_opcode_hash, opname); -+ if (opcode) -+ { -+ found_something = 1; -+ opcode = find_opcode_match (opcode, tok, &ntok, &cpumatch); -+ if (opcode) -+ { -+ struct sw_64_insn insn; -+ assemble_insn (opcode, tok, ntok, &insn, reloc); -+ -+ /* Copy the sequence number for the reloc from the reloc token. */ -+ if (reloc != BFD_RELOC_UNUSED) -+ insn.sequence = tok[ntok].X_add_number; -+ -+ emit_insn (&insn); -+ return; -+ } -+ } -+ -+ if (found_something) -+ { -+ if (cpumatch) -+ as_bad (_ ("inappropriate arguments for opcode `%s'"), opname); -+ else -+ as_bad (_ ("opcode `%s' not supported for target %s"), opname, -+ sw_64_target_name); -+ } -+ else -+ as_bad (_ ("unknown opcode `%s'"), opname); -+} -+ -+#ifdef OBJ_EVAX -+ -+/* Add sym+addend to link pool. -+ Return offset from current procedure value (pv) to entry in link pool. -+ -+ Add new fixup only if offset isn't 16bit. */ -+ -+static symbolS * -+add_to_link_pool (symbolS *sym, offsetT addend) -+{ -+ symbolS *basesym; -+ segT current_section = now_seg; -+ int current_subsec = now_subseg; -+ char *p; -+ segment_info_type *seginfo = seg_info (sw_64_link_section); -+ fixS *fixp; -+ symbolS *linksym, *expsym; -+ expressionS e; -+ -+ basesym = sw_64_evax_proc->symbol; -+ -+ /* @@ This assumes all entries in a given section will be of the same -+ size... Probably correct, but unwise to rely on. */ -+ /* This must always be called with the same subsegment. */ -+ -+ if (seginfo->frchainP) -+ for (fixp = seginfo->frchainP->fix_root; fixp != (fixS *) NULL; -+ fixp = fixp->fx_next) -+ { -+ if (fixp->fx_addsy == sym && fixp->fx_offset == (valueT) addend -+ && fixp->tc_fix_data.info && fixp->tc_fix_data.info->sym -+ && symbol_symbolS (fixp->tc_fix_data.info->sym) -+ && (symbol_get_value_expression (fixp->tc_fix_data.info->sym) -+ ->X_op_symbol -+ == basesym)) -+ return fixp->tc_fix_data.info->sym; -+ } -+ -+ /* Not found, add a new entry. */ -+ subseg_set (sw_64_link_section, 0); -+ linksym = symbol_new (FAKE_LABEL_NAME, now_seg, frag_now, frag_now_fix ()); -+ p = frag_more (8); -+ memset (p, 0, 8); -+ -+ /* Create a symbol for 'basesym - linksym' (offset of the added entry). */ -+ e.X_op = O_subtract; -+ e.X_add_symbol = linksym; -+ e.X_op_symbol = basesym; -+ e.X_add_number = 0; -+ expsym = make_expr_symbol (&e); -+ -+ /* Create a fixup for the entry. */ -+ fixp = fix_new (frag_now, p - frag_now->fr_literal, 8, sym, addend, 0, -+ BFD_RELOC_64); -+ fixp->tc_fix_data.info = get_sw_64_reloc_tag (next_sequence_num--); -+ fixp->tc_fix_data.info->sym = expsym; -+ -+ subseg_set (current_section, current_subsec); -+ -+ /* Return the symbol. */ -+ return expsym; -+} -+#endif /* OBJ_EVAX */ -+ -+/* Assembler directives. */ -+ -+/* Handle the .text pseudo-op. This is like the usual one, but it -+ clears sw_64_insn_label and restores auto alignment. */ -+ -+static void -+s_sw_64_text (int i) -+{ -+#ifdef OBJ_ELF -+ obj_elf_text (i); -+#else -+ s_text (i); -+#endif -+#ifdef OBJ_EVAX -+ { -+ symbolS *symbolP; -+ -+ symbolP = symbol_find (".text"); -+ if (symbolP == NULL) -+ { -+ symbolP = symbol_make (".text"); -+ S_SET_SEGMENT (symbolP, text_section); -+ symbol_table_insert (symbolP); -+ } -+ } -+#endif -+ sw_64_insn_label = NULL; -+ sw_64_auto_align_on = 1; -+ sw_64_current_align = 0; -+} -+ -+/* Handle the .data pseudo-op. This is like the usual one, but it -+ clears sw_64_insn_label and restores auto alignment. */ -+ -+static void -+s_sw_64_data (int i) -+{ -+#ifdef OBJ_ELF -+ obj_elf_data (i); -+#else -+ s_data (i); -+#endif -+ sw_64_insn_label = NULL; -+ sw_64_auto_align_on = 1; -+ sw_64_current_align = 0; -+} -+ -+#if defined (OBJ_ECOFF) || defined (OBJ_EVAX) -+ -+/* Handle the OSF/1 and openVMS .comm pseudo quirks. */ -+ -+static void -+s_sw_64_comm (int ignore ATTRIBUTE_UNUSED) -+{ -+ char *name; -+ char c; -+ char *p; -+ offsetT size; -+ symbolS *symbolP; -+#ifdef OBJ_EVAX -+ offsetT temp; -+ int log_align = 0; -+#endif -+ -+ c = get_symbol_name (&name); -+ -+ /* Just after name is now '\0'. */ -+ p = input_line_pointer; -+ *p = c; -+ -+ SKIP_WHITESPACE_AFTER_NAME (); -+ -+ /* Sw_64 OSF/1 compiler doesn't provide the comma, gcc does. */ -+ if (*input_line_pointer == ',') -+ { -+ input_line_pointer++; -+ SKIP_WHITESPACE (); -+ } -+ if ((size = get_absolute_expression ()) < 0) -+ { -+ as_warn (_ (".COMMon length (%ld.) <0! Ignored."), (long) size); -+ ignore_rest_of_line (); -+ return; -+ } -+ -+ *p = 0; -+ symbolP = symbol_find_or_make (name); -+ *p = c; -+ -+ if (S_IS_DEFINED (symbolP) && !S_IS_COMMON (symbolP)) -+ { -+ as_bad (_ ("Ignoring attempt to re-define symbol")); -+ ignore_rest_of_line (); -+ return; -+ } -+ -+#ifdef OBJ_EVAX -+ if (*input_line_pointer != ',') -+ temp = 8; /* Default alignment. */ -+ else -+ { -+ input_line_pointer++; -+ SKIP_WHITESPACE (); -+ temp = get_absolute_expression (); -+ } -+ -+ /* ??? Unlike on OSF/1, the alignment factor is not in log units. */ -+ while ((temp >>= 1) != 0) -+ ++log_align; -+ -+ if (*input_line_pointer == ',') -+ { -+ /* Extended form of the directive -+ -+ .comm symbol, size, alignment, section -+ -+ where the "common" semantics is transferred to the section. -+ The symbol is effectively an alias for the section name. */ -+ -+ segT sec; -+ const char *sec_name; -+ symbolS *sec_symbol; -+ segT current_seg = now_seg; -+ subsegT current_subseg = now_subseg; -+ int cur_size; -+ -+ input_line_pointer++; -+ SKIP_WHITESPACE (); -+ sec_name = s_sw_64_section_name (); -+ sec_symbol = symbol_find_or_make (sec_name); -+ sec = subseg_new (sec_name, 0); -+ S_SET_SEGMENT (sec_symbol, sec); -+ symbol_get_bfdsym (sec_symbol)->flags |= BSF_SECTION_SYM; -+ bfd_vms_set_section_flags (stdoutput, sec, 0, -+ EGPS__V_OVR | EGPS__V_GBL | EGPS__V_NOMOD); -+ record_alignment (sec, log_align); -+ -+ /* Reuse stab_string_size to store the size of the section. */ -+ cur_size = seg_info (sec)->stabu.stab_string_size; -+ if ((int) size > cur_size) -+ { -+ char *pfrag = frag_var (rs_fill, 1, 1, (relax_substateT) 0, NULL, -+ (valueT) size - (valueT) cur_size, NULL); -+ *pfrag = 0; -+ seg_info (sec)->stabu.stab_string_size = (int) size; -+ } -+ -+ S_SET_SEGMENT (symbolP, sec); -+ -+ subseg_set (current_seg, current_subseg); -+ } -+ else -+ { -+ /* Regular form of the directive -+ -+ .comm symbol, size, alignment -+ -+ where the "common" semantics in on the symbol. -+ These symbols are assembled in the .bss section. */ -+ -+ char *pfrag; -+ segT current_seg = now_seg; -+ subsegT current_subseg = now_subseg; -+ -+ subseg_set (bss_section, 1); -+ frag_align (log_align, 0, 0); -+ record_alignment (bss_section, log_align); -+ -+ symbol_set_frag (symbolP, frag_now); -+ pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size, NULL); -+ *pfrag = 0; -+ -+ S_SET_SEGMENT (symbolP, bss_section); -+ -+ subseg_set (current_seg, current_subseg); -+ } -+#endif -+ -+ if (S_GET_VALUE (symbolP)) -+ { -+ if (S_GET_VALUE (symbolP) != (valueT) size) -+ as_bad (_ ( -+ "Length of .comm \"%s\" is already %ld. Not changed to %ld."), -+ S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), -+ (long) size); -+ } -+ else -+ { -+#ifndef OBJ_EVAX -+ S_SET_VALUE (symbolP, (valueT) size); -+#endif -+ S_SET_EXTERNAL (symbolP); -+ } -+ -+#ifndef OBJ_EVAX -+ know (symbol_get_frag (symbolP) == &zero_address_frag); -+#endif -+ demand_empty_rest_of_line (); -+} -+ -+#endif /* ! OBJ_ELF */ -+ -+#ifdef OBJ_ECOFF -+ -+/* Handle the .rdata pseudo-op. This is like the usual one, but it -+ clears sw_64_insn_label and restores auto alignment. */ -+ -+static void -+s_sw_64_rdata (int ignore ATTRIBUTE_UNUSED) -+{ -+ get_absolute_expression (); -+ subseg_new (".rdata", 0); -+ demand_empty_rest_of_line (); -+ sw_64_insn_label = NULL; -+ sw_64_auto_align_on = 1; -+ sw_64_current_align = 0; -+} -+ -+#endif -+ -+#ifdef OBJ_ECOFF -+ -+/* Handle the .sdata pseudo-op. This is like the usual one, but it -+ clears sw_64_insn_label and restores auto alignment. */ -+ -+static void -+s_sw_64_sdata (int ignore ATTRIBUTE_UNUSED) -+{ -+ get_absolute_expression (); -+ subseg_new (".sdata", 0); -+ demand_empty_rest_of_line (); -+ sw_64_insn_label = NULL; -+ sw_64_auto_align_on = 1; -+ sw_64_current_align = 0; -+} -+#endif -+ -+#ifdef OBJ_ELF -+struct sw_64_elf_frame_data -+{ -+ symbolS *func_sym; -+ symbolS *func_end_sym; -+ symbolS *prologue_sym; -+ unsigned int mask; -+ unsigned int fmask; -+ int fp_regno; -+ int ra_regno; -+ offsetT frame_size; -+ offsetT mask_offset; -+ offsetT fmask_offset; -+ -+ struct sw_64_elf_frame_data *next; -+}; -+ -+static struct sw_64_elf_frame_data *all_frame_data; -+static struct sw_64_elf_frame_data **plast_frame_data = &all_frame_data; -+static struct sw_64_elf_frame_data *cur_frame_data; -+ -+extern int all_cfi_sections; -+ -+/* Handle the .section pseudo-op. This is like the usual one, but it -+ clears sw_64_insn_label and restores auto alignment. */ -+ -+static void -+s_sw_64_section (int ignore ATTRIBUTE_UNUSED) -+{ -+ obj_elf_section (ignore); -+ -+ sw_64_insn_label = NULL; -+ sw_64_auto_align_on = 1; -+ sw_64_current_align = 0; -+} -+ -+static void -+s_sw_64_ent (int dummy ATTRIBUTE_UNUSED) -+{ -+ if (ECOFF_DEBUGGING) -+ ecoff_directive_ent (0); -+ else -+ { -+ char *name, name_end; -+ -+ name_end = get_symbol_name (&name); -+ /* CFI_EMIT_eh_frame is the default. */ -+ all_cfi_sections = CFI_EMIT_eh_frame; -+ -+ if (!is_name_beginner (*name)) -+ { -+ as_warn (_ (".ent directive has no name")); -+ (void) restore_line_pointer (name_end); -+ } -+ else -+ { -+ symbolS *sym; -+ -+ if (cur_frame_data) -+ as_warn (_ ("nested .ent directives")); -+ -+ sym = symbol_find_or_make (name); -+ symbol_get_bfdsym (sym)->flags |= BSF_FUNCTION; -+ -+ cur_frame_data = XCNEW (struct sw_64_elf_frame_data); -+ cur_frame_data->func_sym = sym; -+ -+ /* Provide sensible defaults. */ -+ cur_frame_data->fp_regno = 30; /* sp */ -+ cur_frame_data->ra_regno = 26; /* ra */ -+ -+ *plast_frame_data = cur_frame_data; -+ plast_frame_data = &cur_frame_data->next; -+ -+ /* The .ent directive is sometimes followed by a number. Not sure -+ what it really means, but ignore it. */ -+ *input_line_pointer = name_end; -+ SKIP_WHITESPACE_AFTER_NAME (); -+ if (*input_line_pointer == ',') -+ { -+ input_line_pointer++; -+ SKIP_WHITESPACE (); -+ } -+ if (ISDIGIT (*input_line_pointer) || *input_line_pointer == '-') -+ (void) get_absolute_expression (); -+ } -+ demand_empty_rest_of_line (); -+ } -+} -+ -+static void -+s_sw_64_end (int dummy ATTRIBUTE_UNUSED) -+{ -+ if (ECOFF_DEBUGGING) -+ ecoff_directive_end (0); -+ else -+ { -+ char *name, name_end; -+ -+ name_end = get_symbol_name (&name); -+ -+ if (!is_name_beginner (*name)) -+ { -+ as_warn (_ (".end directive has no name")); -+ } -+ else -+ { -+ symbolS *sym; -+ -+ sym = symbol_find (name); -+ if (!cur_frame_data) -+ as_warn (_ (".end directive without matching .ent")); -+ else if (sym != cur_frame_data->func_sym) -+ as_warn (_ (".end directive names different symbol than .ent")); -+ -+ /* Create an expression to calculate the size of the function. */ -+ if (sym && cur_frame_data) -+ { -+ OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (sym); -+ expressionS *exp = XNEW (expressionS); -+ -+ obj->size = exp; -+ exp->X_op = O_subtract; -+ exp->X_add_symbol = symbol_temp_new_now (); -+ exp->X_op_symbol = sym; -+ exp->X_add_number = 0; -+ -+ cur_frame_data->func_end_sym = exp->X_add_symbol; -+ } -+ -+ cur_frame_data = NULL; -+ } -+ -+ (void) restore_line_pointer (name_end); -+ demand_empty_rest_of_line (); -+ } -+} -+ -+static void -+s_sw_64_mask (int fp) -+{ -+ if (ECOFF_DEBUGGING) -+ { -+ if (fp) -+ ecoff_directive_fmask (0); -+ else -+ ecoff_directive_mask (0); -+ } -+ else -+ { -+ long val; -+ offsetT offset; -+ -+ if (!cur_frame_data) -+ { -+ if (fp) -+ as_warn (_ (".fmask outside of .ent")); -+ else -+ as_warn (_ (".mask outside of .ent")); -+ discard_rest_of_line (); -+ return; -+ } -+ -+ if (get_absolute_expression_and_terminator (&val) != ',') -+ { -+ if (fp) -+ as_warn (_ ("bad .fmask directive")); -+ else -+ as_warn (_ ("bad .mask directive")); -+ --input_line_pointer; -+ discard_rest_of_line (); -+ return; -+ } -+ -+ offset = get_absolute_expression (); -+ demand_empty_rest_of_line (); -+ -+ if (fp) -+ { -+ cur_frame_data->fmask = val; -+ cur_frame_data->fmask_offset = offset; -+ } -+ else -+ { -+ cur_frame_data->mask = val; -+ cur_frame_data->mask_offset = offset; -+ } -+ } -+} -+ -+static void -+s_sw_64_frame (int dummy ATTRIBUTE_UNUSED) -+{ -+ if (ECOFF_DEBUGGING) -+ ecoff_directive_frame (0); -+ else -+ { -+ long val; -+ -+ if (!cur_frame_data) -+ { -+ as_warn (_ (".frame outside of .ent")); -+ discard_rest_of_line (); -+ return; -+ } -+ -+ cur_frame_data->fp_regno = tc_get_register (1); -+ -+ SKIP_WHITESPACE (); -+ if (*input_line_pointer++ != ',' -+ || get_absolute_expression_and_terminator (&val) != ',') -+ { -+ as_warn (_ ("bad .frame directive")); -+ --input_line_pointer; -+ discard_rest_of_line (); -+ return; -+ } -+ cur_frame_data->frame_size = val; -+ -+ cur_frame_data->ra_regno = tc_get_register (0); -+ -+ /* Next comes the "offset of saved $a0 from $sp". In gcc terms -+ this is current_function_pretend_args_size. There's no place -+ to put this value, so ignore it. */ -+ s_ignore (42); -+ } -+} -+ -+static void -+s_sw_64_prologue (int ignore ATTRIBUTE_UNUSED) -+{ -+ symbolS *sym; -+ int arg; -+ -+ arg = get_absolute_expression (); -+ demand_empty_rest_of_line (); -+ sw_64_prologue_label -+ = symbol_new (FAKE_LABEL_NAME, now_seg, frag_now, frag_now_fix ()); -+ -+ if (ECOFF_DEBUGGING) -+ sym = ecoff_get_cur_proc_sym (); -+ else -+ sym = cur_frame_data ? cur_frame_data->func_sym : NULL; -+ -+ if (sym == NULL) -+ { -+ as_bad (_ (".prologue directive without a preceding .ent directive")); -+ return; -+ } -+ -+ switch (arg) -+ { -+ case 0: /* No PV required. */ -+ S_SET_OTHER (sym, STO_SW_64_NOPV -+ | (S_GET_OTHER (sym) & ~STO_SW_64_STD_GPLOAD)); -+ break; -+ case 1: /* Std GP load. */ -+ S_SET_OTHER (sym, STO_SW_64_STD_GPLOAD -+ | (S_GET_OTHER (sym) & ~STO_SW_64_STD_GPLOAD)); -+ break; -+ case 2: /* Non-std use of PV. */ -+ break; -+ -+ default: -+ as_bad (_ ("Invalid argument %d to .prologue."), arg); -+ break; -+ } -+ -+ if (cur_frame_data) -+ cur_frame_data->prologue_sym = symbol_temp_new_now (); -+} -+ -+static char *first_file_directive; -+ -+static void -+s_sw_64_file (int ignore ATTRIBUTE_UNUSED) -+{ -+ /* Save the first .file directive we see, so that we can change our -+ minds about whether ecoff debugging should or shouldn't be enabled. */ -+ if (sw_64_flag_mdebug < 0 && !first_file_directive) -+ { -+ char *start = input_line_pointer; -+ size_t len; -+ -+ discard_rest_of_line (); -+ -+ len = input_line_pointer - start; -+ first_file_directive = xmemdup0 (start, len); -+ -+ input_line_pointer = start; -+ } -+ -+ if (ECOFF_DEBUGGING) -+ ecoff_directive_file (0); -+ else -+ dwarf2_directive_file (0); -+} -+ -+static void -+s_sw_64_loc (int ignore ATTRIBUTE_UNUSED) -+{ -+ if (ECOFF_DEBUGGING) -+ ecoff_directive_loc (0); -+ else -+ dwarf2_directive_loc (0); -+} -+ -+static void -+s_sw_64_stab (int n) -+{ -+ /* If we've been undecided about mdebug, make up our minds in favour. */ -+ if (sw_64_flag_mdebug < 0) -+ { -+ segT sec = subseg_new (".mdebug", 0); -+ bfd_set_section_flags (sec, SEC_HAS_CONTENTS | SEC_READONLY); -+ bfd_set_section_alignment (sec, 3); -+ ecoff_read_begin_hook (); -+ -+ if (first_file_directive) -+ { -+ char *save_ilp = input_line_pointer; -+ input_line_pointer = first_file_directive; -+ ecoff_directive_file (0); -+ input_line_pointer = save_ilp; -+ free (first_file_directive); -+ } -+ -+ sw_64_flag_mdebug = 1; -+ } -+ s_stab (n); -+} -+ -+static void -+s_sw_64_coff_wrapper (int which) -+{ -+ static void (*const fns[]) (int) = { -+ ecoff_directive_begin, ecoff_directive_bend, ecoff_directive_def, -+ ecoff_directive_dim, ecoff_directive_endef, ecoff_directive_scl, -+ ecoff_directive_tag, ecoff_directive_val, -+ }; -+ -+ gas_assert (which >= 0 && which < (int) (sizeof (fns) / sizeof (*fns))); -+ -+ if (ECOFF_DEBUGGING) -+ (*fns[which]) (0); -+ else -+ { -+ as_bad (_ ("ECOFF debugging is disabled.")); -+ ignore_rest_of_line (); -+ } -+} -+ -+/* Called at the end of assembly. Here we emit unwind info for frames -+ unless the compiler has done it for us. */ -+ -+void -+sw_64_elf_md_finish (void) -+{ -+ struct sw_64_elf_frame_data *p; -+ -+ if (cur_frame_data) -+ as_warn (_ (".ent directive without matching .end")); -+ -+ /* If someone has generated the unwind info themselves, great. */ -+ if (bfd_get_section_by_name (stdoutput, ".eh_frame") != NULL) -+ return; -+ -+ /* ??? In theory we could look for functions for which we have -+ generated unwind info via CFI directives, and those we have not. -+ Those we have not could still get their unwind info from here. -+ For now, do nothing if we've seen any CFI directives. Note that -+ the above test will not trigger, as we've not emitted data yet. */ -+ if (all_fde_data != NULL) -+ return; -+ -+ /* Generate .eh_frame data for the unwind directives specified. */ -+ for (p = all_frame_data; p; p = p->next) -+ if (p->prologue_sym) -+ { -+ /* Create a temporary symbol at the same location as our -+ function symbol. This prevents problems with globals. */ -+ cfi_new_fde (symbol_temp_new (S_GET_SEGMENT (p->func_sym), -+ symbol_get_frag (p->func_sym), -+ S_GET_VALUE (p->func_sym))); -+ -+ cfi_set_sections (); -+ cfi_set_return_column (p->ra_regno); -+ cfi_add_CFA_def_cfa_register (30); -+ if (p->fp_regno != 30 || p->mask || p->fmask || p->frame_size) -+ { -+ unsigned int mask; -+ offsetT offset; -+ -+ cfi_add_advance_loc (p->prologue_sym); -+ -+ if (p->fp_regno != 30) -+ if (p->frame_size != 0) -+ cfi_add_CFA_def_cfa (p->fp_regno, p->frame_size); -+ else -+ cfi_add_CFA_def_cfa_register (p->fp_regno); -+ else if (p->frame_size != 0) -+ cfi_add_CFA_def_cfa_offset (p->frame_size); -+ -+ mask = p->mask; -+ offset = p->mask_offset; -+ -+ /* Recall that $26 is special-cased and stored first. */ -+ if ((mask >> 26) & 1) -+ { -+ cfi_add_CFA_offset (26, offset); -+ offset += 8; -+ mask &= ~(1 << 26); -+ } -+ while (mask) -+ { -+ unsigned int i; -+ i = mask & -mask; -+ mask ^= i; -+ i = ffs (i) - 1; -+ -+ cfi_add_CFA_offset (i, offset); -+ offset += 8; -+ } -+ -+ mask = p->fmask; -+ offset = p->fmask_offset; -+ while (mask) -+ { -+ unsigned int i; -+ i = mask & -mask; -+ mask ^= i; -+ i = ffs (i) - 1; -+ -+ cfi_add_CFA_offset (i + 32, offset); -+ offset += 8; -+ } -+ } -+ -+ cfi_end_fde (p->func_end_sym); -+ } -+} -+ -+static void -+s_sw_64_usepv (int unused ATTRIBUTE_UNUSED) -+{ -+ char *name, name_end; -+ char *which, which_end; -+ symbolS *sym; -+ int other; -+ -+ name_end = get_symbol_name (&name); -+ -+ if (!is_name_beginner (*name)) -+ { -+ as_bad (_ (".usepv directive has no name")); -+ (void) restore_line_pointer (name_end); -+ ignore_rest_of_line (); -+ return; -+ } -+ -+ sym = symbol_find_or_make (name); -+ name_end = restore_line_pointer (name_end); -+ if (!is_end_of_line[(unsigned char) name_end]) -+ input_line_pointer++; -+ -+ if (name_end != ',') -+ { -+ as_bad (_ (".usepv directive has no type")); -+ ignore_rest_of_line (); -+ return; -+ } -+ -+ SKIP_WHITESPACE (); -+ -+ which_end = get_symbol_name (&which); -+ -+ if (strcmp (which, "no") == 0) -+ other = STO_SW_64_NOPV; -+ else if (strcmp (which, "std") == 0) -+ other = STO_SW_64_STD_GPLOAD; -+ else -+ { -+ as_bad (_ ("unknown argument for .usepv")); -+ other = 0; -+ } -+ -+ (void) restore_line_pointer (which_end); -+ demand_empty_rest_of_line (); -+ -+ S_SET_OTHER (sym, other | (S_GET_OTHER (sym) & ~STO_SW_64_STD_GPLOAD)); -+} -+#endif /* OBJ_ELF */ -+ -+/* Standard calling conventions leaves the CFA at $30 on entry. */ -+ -+void -+sw_64_cfi_frame_initial_instructions (void) -+{ -+ cfi_add_CFA_def_cfa_register (30); -+} -+ -+#ifdef OBJ_EVAX -+ -+/* Get name of section. */ -+static const char * -+s_sw_64_section_name (void) -+{ -+ char *name; -+ -+ SKIP_WHITESPACE (); -+ if (*input_line_pointer == '"') -+ { -+ int dummy; -+ -+ name = demand_copy_C_string (&dummy); -+ if (name == NULL) -+ { -+ ignore_rest_of_line (); -+ return NULL; -+ } -+ } -+ else -+ { -+ char *end = input_line_pointer; -+ -+ while (0 == strchr ("\n\t,; ", *end)) -+ end++; -+ if (end == input_line_pointer) -+ { -+ as_warn (_ ("missing name")); -+ ignore_rest_of_line (); -+ return NULL; -+ } -+ -+ name = xmemdup0 (input_line_pointer, end - input_line_pointer); -+ input_line_pointer = end; -+ } -+ SKIP_WHITESPACE (); -+ return name; -+} -+ -+/* Put clear/set flags in one flagword. The LSBs are flags to be set, -+ the MSBs are the flags to be cleared. */ -+ -+#define EGPS__V_NO_SHIFT 16 -+#define EGPS__V_MASK 0xffff -+ -+/* Parse one VMS section flag. */ -+ -+static flagword -+s_sw_64_section_word (char *str, size_t len) -+{ -+ int no = 0; -+ flagword flag = 0; -+ -+ if (len == 5 && strncmp (str, "NO", 2) == 0) -+ { -+ no = 1; -+ str += 2; -+ len -= 2; -+ } -+ -+ if (len == 3) -+ { -+ if (strncmp (str, "PIC", 3) == 0) -+ flag = EGPS__V_PIC; -+ else if (strncmp (str, "LIB", 3) == 0) -+ flag = EGPS__V_LIB; -+ else if (strncmp (str, "OVR", 3) == 0) -+ flag = EGPS__V_OVR; -+ else if (strncmp (str, "REL", 3) == 0) -+ flag = EGPS__V_REL; -+ else if (strncmp (str, "GBL", 3) == 0) -+ flag = EGPS__V_GBL; -+ else if (strncmp (str, "SHR", 3) == 0) -+ flag = EGPS__V_SHR; -+ else if (strncmp (str, "EXE", 3) == 0) -+ flag = EGPS__V_EXE; -+ else if (strncmp (str, "WRT", 3) == 0) -+ flag = EGPS__V_WRT; -+ else if (strncmp (str, "VEC", 3) == 0) -+ flag = EGPS__V_VEC; -+ else if (strncmp (str, "MOD", 3) == 0) -+ { -+ flag = no ? EGPS__V_NOMOD : EGPS__V_NOMOD << EGPS__V_NO_SHIFT; -+ no = 0; -+ } -+ else if (strncmp (str, "COM", 3) == 0) -+ flag = EGPS__V_COM; -+ } -+ -+ if (flag == 0) -+ { -+ char c = str[len]; -+ str[len] = 0; -+ as_warn (_ ("unknown section attribute %s"), str); -+ str[len] = c; -+ return 0; -+ } -+ -+ if (no) -+ return flag << EGPS__V_NO_SHIFT; -+ else -+ return flag; -+} -+ -+/* Handle the section specific pseudo-op. */ -+ -+#define EVAX_SECTION_COUNT 5 -+ -+static const char *section_name[EVAX_SECTION_COUNT + 1] -+ = {"NULL", ".rdata", ".comm", ".link", ".ctors", ".dtors"}; -+ -+static void -+s_sw_64_section (int secid) -+{ -+ const char *name; -+ char *beg; -+ segT sec; -+ flagword vms_flags = 0; -+ symbolS *symbol; -+ -+ if (secid == 0) -+ { -+ name = s_sw_64_section_name (); -+ if (name == NULL) -+ return; -+ sec = subseg_new (name, 0); -+ if (*input_line_pointer == ',') -+ { -+ /* Skip the comma. */ -+ ++input_line_pointer; -+ SKIP_WHITESPACE (); -+ -+ do -+ { -+ char c; -+ -+ SKIP_WHITESPACE (); -+ c = get_symbol_name (&beg); -+ *input_line_pointer = c; -+ -+ vms_flags |= s_sw_64_section_word (beg, input_line_pointer - beg); -+ -+ SKIP_WHITESPACE_AFTER_NAME (); -+ } while (*input_line_pointer++ == ','); -+ -+ --input_line_pointer; -+ } -+ -+ symbol = symbol_find_or_make (name); -+ S_SET_SEGMENT (symbol, sec); -+ symbol_get_bfdsym (symbol)->flags |= BSF_SECTION_SYM; -+ bfd_vms_set_section_flags (stdoutput, sec, -+ (vms_flags >> EGPS__V_NO_SHIFT) & EGPS__V_MASK, -+ vms_flags & EGPS__V_MASK); -+ } -+ else -+ { -+ get_absolute_expression (); -+ subseg_new (section_name[secid], 0); -+ } -+ -+ demand_empty_rest_of_line (); -+ sw_64_insn_label = NULL; -+ sw_64_auto_align_on = 1; -+ sw_64_current_align = 0; -+} -+ -+static void -+s_sw_64_literals (int ignore ATTRIBUTE_UNUSED) -+{ -+ subseg_new (".literals", 0); -+ demand_empty_rest_of_line (); -+ sw_64_insn_label = NULL; -+ sw_64_auto_align_on = 1; -+ sw_64_current_align = 0; -+} -+ -+/* Parse .ent directives. */ -+ -+static void -+s_sw_64_ent (int ignore ATTRIBUTE_UNUSED) -+{ -+ symbolS *symbol; -+ expressionS symexpr; -+ -+ if (sw_64_evax_proc != NULL) -+ as_bad (_ ("previous .ent not closed by a .end")); -+ -+ sw_64_evax_proc = &sw_64_evax_proc_data; -+ -+ sw_64_evax_proc->pdsckind = 0; -+ sw_64_evax_proc->framereg = -1; -+ sw_64_evax_proc->framesize = 0; -+ sw_64_evax_proc->rsa_offset = 0; -+ sw_64_evax_proc->ra_save = AXP_REG_RA; -+ sw_64_evax_proc->fp_save = -1; -+ sw_64_evax_proc->imask = 0; -+ sw_64_evax_proc->fmask = 0; -+ sw_64_evax_proc->prologue = 0; -+ sw_64_evax_proc->type = 0; -+ sw_64_evax_proc->handler = 0; -+ sw_64_evax_proc->handler_data = 0; -+ -+ expression (&symexpr); -+ -+ if (symexpr.X_op != O_symbol) -+ { -+ as_fatal (_ (".ent directive has no symbol")); -+ demand_empty_rest_of_line (); -+ return; -+ } -+ -+ symbol = make_expr_symbol (&symexpr); -+ symbol_get_bfdsym (symbol)->flags |= BSF_FUNCTION; -+ sw_64_evax_proc->symbol = symbol; -+ -+ demand_empty_rest_of_line (); -+} -+ -+static void -+s_sw_64_handler (int is_data) -+{ -+ if (is_data) -+ sw_64_evax_proc->handler_data = get_absolute_expression (); -+ else -+ { -+ char *name, name_end; -+ -+ name_end = get_symbol_name (&name); -+ -+ if (!is_name_beginner (*name)) -+ { -+ as_warn (_ (".handler directive has no name")); -+ } -+ else -+ { -+ symbolS *sym; -+ -+ sym = symbol_find_or_make (name); -+ symbol_get_bfdsym (sym)->flags |= BSF_FUNCTION; -+ sw_64_evax_proc->handler = sym; -+ } -+ -+ (void) restore_line_pointer (name_end); -+ } -+ -+ demand_empty_rest_of_line (); -+} -+ -+/* Parse .frame ,,RA, directives. */ -+ -+static void -+s_sw_64_frame (int ignore ATTRIBUTE_UNUSED) -+{ -+ long val; -+ int ra; -+ -+ sw_64_evax_proc->framereg = tc_get_register (1); -+ -+ SKIP_WHITESPACE (); -+ if (*input_line_pointer++ != ',' -+ || get_absolute_expression_and_terminator (&val) != ',') -+ { -+ as_warn (_ ("Bad .frame directive 1./2. param")); -+ --input_line_pointer; -+ demand_empty_rest_of_line (); -+ return; -+ } -+ -+ sw_64_evax_proc->framesize = val; -+ -+ ra = tc_get_register (1); -+ if (ra != AXP_REG_RA) -+ as_warn (_ ("Bad RA (%d) register for .frame"), ra); -+ -+ SKIP_WHITESPACE (); -+ if (*input_line_pointer++ != ',') -+ { -+ as_warn (_ ("Bad .frame directive 3./4. param")); -+ --input_line_pointer; -+ demand_empty_rest_of_line (); -+ return; -+ } -+ sw_64_evax_proc->rsa_offset = get_absolute_expression (); -+} -+ -+/* Parse .prologue. */ -+ -+static void -+s_sw_64_prologue (int ignore ATTRIBUTE_UNUSED) -+{ -+ demand_empty_rest_of_line (); -+ sw_64_prologue_label -+ = symbol_new (FAKE_LABEL_NAME, now_seg, frag_now, frag_now_fix ()); -+} -+ -+/* Parse .pdesc ,{null|stack|reg} -+ Insert a procedure descriptor. */ -+ -+static void -+s_sw_64_pdesc (int ignore ATTRIBUTE_UNUSED) -+{ -+ char *name; -+ char name_end; -+ char *p; -+ expressionS exp; -+ symbolS *entry_sym; -+ const char *entry_sym_name; -+ const char *pdesc_sym_name; -+ fixS *fixp; -+ size_t len; -+ -+ if (now_seg != sw_64_link_section) -+ { -+ as_bad (_ (".pdesc directive not in link (.link) section")); -+ return; -+ } -+ -+ expression (&exp); -+ if (exp.X_op != O_symbol) -+ { -+ as_bad (_ (".pdesc directive has no entry symbol")); -+ return; -+ } -+ -+ entry_sym = make_expr_symbol (&exp); -+ entry_sym_name = S_GET_NAME (entry_sym); -+ -+ /* Strip "..en". */ -+ len = strlen (entry_sym_name); -+ if (len < 4 || strcmp (entry_sym_name + len - 4, "..en") != 0) -+ { -+ as_bad (_ (".pdesc has a bad entry symbol")); -+ return; -+ } -+ len -= 4; -+ pdesc_sym_name = S_GET_NAME (sw_64_evax_proc->symbol); -+ -+ if (!sw_64_evax_proc || !S_IS_DEFINED (sw_64_evax_proc->symbol) -+ || strlen (pdesc_sym_name) != len -+ || memcmp (entry_sym_name, pdesc_sym_name, len) != 0) -+ { -+ as_fatal (_ (".pdesc doesn't match with last .ent")); -+ return; -+ } -+ -+ /* Define pdesc symbol. */ -+ symbol_set_value_now (sw_64_evax_proc->symbol); -+ -+ /* Save bfd symbol of proc entry in function symbol. */ -+ ((struct evax_private_udata_struct *) symbol_get_bfdsym ( -+ sw_64_evax_proc->symbol) -+ ->udata.p) -+ ->enbsym -+ = symbol_get_bfdsym (entry_sym); -+ -+ SKIP_WHITESPACE (); -+ if (*input_line_pointer++ != ',') -+ { -+ as_warn (_ ("No comma after .pdesc ")); -+ demand_empty_rest_of_line (); -+ return; -+ } -+ -+ SKIP_WHITESPACE (); -+ name_end = get_symbol_name (&name); -+ -+ if (strncmp (name, "stack", 5) == 0) -+ sw_64_evax_proc->pdsckind = PDSC_S_K_KIND_FP_STACK; -+ -+ else if (strncmp (name, "reg", 3) == 0) -+ sw_64_evax_proc->pdsckind = PDSC_S_K_KIND_FP_REGISTER; -+ -+ else if (strncmp (name, "null", 4) == 0) -+ sw_64_evax_proc->pdsckind = PDSC_S_K_KIND_NULL; -+ -+ else -+ { -+ (void) restore_line_pointer (name_end); -+ as_fatal (_ ("unknown procedure kind")); -+ demand_empty_rest_of_line (); -+ return; -+ } -+ -+ (void) restore_line_pointer (name_end); -+ demand_empty_rest_of_line (); -+ -+#ifdef md_flush_pending_output -+ md_flush_pending_output (); -+#endif -+ -+ frag_align (3, 0, 0); -+ p = frag_more (16); -+ fixp = fix_new (frag_now, p - frag_now->fr_literal, 8, 0, 0, 0, 0); -+ fixp->fx_done = 1; -+ -+ *p = sw_64_evax_proc->pdsckind -+ | ((sw_64_evax_proc->framereg == 29) ? PDSC_S_M_BASE_REG_IS_FP : 0) -+ | ((sw_64_evax_proc->handler) ? PDSC_S_M_HANDLER_VALID : 0) -+ | ((sw_64_evax_proc->handler_data) ? PDSC_S_M_HANDLER_DATA_VALID : 0); -+ *(p + 1) = PDSC_S_M_NATIVE | PDSC_S_M_NO_JACKET; -+ -+ switch (sw_64_evax_proc->pdsckind) -+ { -+ case PDSC_S_K_KIND_NULL: -+ *(p + 2) = 0; -+ *(p + 3) = 0; -+ break; -+ case PDSC_S_K_KIND_FP_REGISTER: -+ *(p + 2) = sw_64_evax_proc->fp_save; -+ *(p + 3) = sw_64_evax_proc->ra_save; -+ break; -+ case PDSC_S_K_KIND_FP_STACK: -+ md_number_to_chars (p + 2, (valueT) sw_64_evax_proc->rsa_offset, 2); -+ break; -+ default: /* impossible */ -+ break; -+ } -+ -+ *(p + 4) = 0; -+ *(p + 5) = sw_64_evax_proc->type & 0x0f; -+ -+ /* Signature offset. */ -+ md_number_to_chars (p + 6, (valueT) 0, 2); -+ -+ fix_new_exp (frag_now, p - frag_now->fr_literal + 8, 8, &exp, 0, -+ BFD_RELOC_64); -+ -+ if (sw_64_evax_proc->pdsckind == PDSC_S_K_KIND_NULL) -+ return; -+ -+ /* pdesc+16: Size. */ -+ p = frag_more (6); -+ md_number_to_chars (p, (valueT) sw_64_evax_proc->framesize, 4); -+ md_number_to_chars (p + 4, (valueT) 0, 2); -+ -+ /* Entry length. */ -+ exp.X_op = O_subtract; -+ exp.X_add_symbol = sw_64_prologue_label; -+ exp.X_op_symbol = entry_sym; -+ emit_expr (&exp, 2); -+ -+ if (sw_64_evax_proc->pdsckind == PDSC_S_K_KIND_FP_REGISTER) -+ return; -+ -+ /* pdesc+24: register masks. */ -+ p = frag_more (8); -+ md_number_to_chars (p, sw_64_evax_proc->imask, 4); -+ md_number_to_chars (p + 4, sw_64_evax_proc->fmask, 4); -+ -+ if (sw_64_evax_proc->handler) -+ { -+ p = frag_more (8); -+ fixp = fix_new (frag_now, p - frag_now->fr_literal, 8, -+ sw_64_evax_proc->handler, 0, 0, BFD_RELOC_64); -+ } -+ -+ if (sw_64_evax_proc->handler_data) -+ { -+ p = frag_more (8); -+ md_number_to_chars (p, sw_64_evax_proc->handler_data, 8); -+ } -+} -+ -+/* Support for crash debug on vms. */ -+ -+static void -+s_sw_64_name (int ignore ATTRIBUTE_UNUSED) -+{ -+ char *p; -+ expressionS exp; -+ -+ if (now_seg != sw_64_link_section) -+ { -+ as_bad (_ (".name directive not in link (.link) section")); -+ demand_empty_rest_of_line (); -+ return; -+ } -+ -+ expression (&exp); -+ if (exp.X_op != O_symbol) -+ { -+ as_warn (_ (".name directive has no symbol")); -+ demand_empty_rest_of_line (); -+ return; -+ } -+ -+ demand_empty_rest_of_line (); -+ -+#ifdef md_flush_pending_output -+ md_flush_pending_output (); -+#endif -+ -+ frag_align (3, 0, 0); -+ p = frag_more (8); -+ -+ fix_new_exp (frag_now, p - frag_now->fr_literal, 8, &exp, 0, BFD_RELOC_64); -+} -+ -+/* Parse .linkage . -+ Create a linkage pair relocation. */ -+ -+static void -+s_sw_64_linkage (int ignore ATTRIBUTE_UNUSED) -+{ -+ expressionS exp; -+ char *p; -+ fixS *fixp; -+ -+#ifdef md_flush_pending_output -+ md_flush_pending_output (); -+#endif -+ -+ expression (&exp); -+ if (exp.X_op != O_symbol) -+ { -+ as_fatal (_ ("No symbol after .linkage")); -+ } -+ else -+ { -+ struct sw_64_linkage_fixups *linkage_fixup; -+ -+ p = frag_more (LKP_S_K_SIZE); -+ memset (p, 0, LKP_S_K_SIZE); -+ fixp = fix_new_exp (frag_now, p - frag_now->fr_literal, LKP_S_K_SIZE, -+ &exp, 0, BFD_RELOC_SW_64_LINKAGE); -+ -+ if (sw_64_insn_label == NULL) -+ sw_64_insn_label -+ = symbol_new (FAKE_LABEL_NAME, now_seg, frag_now, frag_now_fix ()); -+ -+ /* Create a linkage element. */ -+ linkage_fixup = XNEW (struct sw_64_linkage_fixups); -+ linkage_fixup->fixp = fixp; -+ linkage_fixup->next = NULL; -+ linkage_fixup->label = sw_64_insn_label; -+ -+ /* Append it to the list. */ -+ if (sw_64_linkage_fixup_root == NULL) -+ sw_64_linkage_fixup_root = linkage_fixup; -+ else -+ sw_64_linkage_fixup_tail->next = linkage_fixup; -+ sw_64_linkage_fixup_tail = linkage_fixup; -+ } -+ demand_empty_rest_of_line (); -+} -+ -+/* Parse .code_address . -+ Create a code address relocation. */ -+ -+static void -+s_sw_64_code_address (int ignore ATTRIBUTE_UNUSED) -+{ -+ expressionS exp; -+ char *p; -+ -+#ifdef md_flush_pending_output -+ md_flush_pending_output (); -+#endif -+ -+ expression (&exp); -+ if (exp.X_op != O_symbol) -+ as_fatal (_ ("No symbol after .code_address")); -+ else -+ { -+ p = frag_more (8); -+ memset (p, 0, 8); -+ fix_new_exp (frag_now, p - frag_now->fr_literal, 8, &exp, 0, -+ BFD_RELOC_SW_64_CODEADDR); -+ } -+ demand_empty_rest_of_line (); -+} -+ -+static void -+s_sw_64_fp_save (int ignore ATTRIBUTE_UNUSED) -+{ -+ sw_64_evax_proc->fp_save = tc_get_register (1); -+ -+ demand_empty_rest_of_line (); -+} -+ -+static void -+s_sw_64_mask (int ignore ATTRIBUTE_UNUSED) -+{ -+ long val; -+ -+ if (get_absolute_expression_and_terminator (&val) != ',') -+ { -+ as_warn (_ ("Bad .mask directive")); -+ --input_line_pointer; -+ } -+ else -+ { -+ sw_64_evax_proc->imask = val; -+ (void) get_absolute_expression (); -+ } -+ demand_empty_rest_of_line (); -+} -+ -+static void -+s_sw_64_fmask (int ignore ATTRIBUTE_UNUSED) -+{ -+ long val; -+ -+ if (get_absolute_expression_and_terminator (&val) != ',') -+ { -+ as_warn (_ ("Bad .fmask directive")); -+ --input_line_pointer; -+ } -+ else -+ { -+ sw_64_evax_proc->fmask = val; -+ (void) get_absolute_expression (); -+ } -+ demand_empty_rest_of_line (); -+} -+ -+static void -+s_sw_64_end (int ignore ATTRIBUTE_UNUSED) -+{ -+ char *name; -+ char c; -+ -+ c = get_symbol_name (&name); -+ (void) restore_line_pointer (c); -+ demand_empty_rest_of_line (); -+ sw_64_evax_proc = NULL; -+} -+ -+static void -+s_sw_64_file (int ignore ATTRIBUTE_UNUSED) -+{ -+ symbolS *s; -+ int length; -+ static char case_hack[32]; -+ -+ sprintf (case_hack, "", sw_64_flag_hash_long_names, -+ sw_64_flag_show_after_trunc); -+ -+ s = symbol_find_or_make (case_hack); -+ symbol_get_bfdsym (s)->flags |= BSF_FILE; -+ -+ get_absolute_expression (); -+ s = symbol_find_or_make (demand_copy_string (&length)); -+ symbol_get_bfdsym (s)->flags |= BSF_FILE; -+ demand_empty_rest_of_line (); -+} -+#endif /* OBJ_EVAX */ -+ -+/* Handle the .gprel32 pseudo op. */ -+ -+static void -+s_sw_64_gprel32 (int ignore ATTRIBUTE_UNUSED) -+{ -+ expressionS e; -+ char *p; -+ -+ SKIP_WHITESPACE (); -+ expression (&e); -+ -+#ifdef OBJ_ELF -+ switch (e.X_op) -+ { -+ case O_constant: -+ e.X_add_symbol = section_symbol (absolute_section); -+ e.X_op = O_symbol; -+ /* FALLTHRU */ -+ case O_symbol: -+ break; -+ default: -+ abort (); -+ } -+#else -+#ifdef OBJ_ECOFF -+ switch (e.X_op) -+ { -+ case O_constant: -+ e.X_add_symbol = section_symbol (absolute_section); -+ /* fall through */ -+ case O_symbol: -+ e.X_op = O_subtract; -+ e.X_op_symbol = sw_64_gp_symbol; -+ break; -+ default: -+ abort (); -+ } -+#endif -+#endif -+ -+ if (sw_64_auto_align_on && sw_64_current_align < 2) -+ sw_64_align (2, (char *) NULL, sw_64_insn_label, 0); -+ if (sw_64_current_align > 2) -+ sw_64_current_align = 2; -+ sw_64_insn_label = NULL; -+ -+ p = frag_more (4); -+ memset (p, 0, 4); -+ fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &e, 0, BFD_RELOC_GPREL32); -+} -+ -+/* Handle floating point allocation pseudo-ops. This is like the -+ generic version, but it makes sure the current label, if any, is -+ correctly aligned. */ -+ -+static void -+s_sw_64_float_cons (int type) -+{ -+ int log_size; -+ -+ switch (type) -+ { -+ default: -+ case 'f': -+ case 'F': -+ log_size = 2; -+ break; -+ -+ case 'd': -+ case 'D': -+ case 'G': -+ log_size = 3; -+ break; -+ -+ case 'x': -+ case 'X': -+ case 'p': -+ case 'P': -+ log_size = 4; -+ break; -+ } -+ -+ if (sw_64_auto_align_on && sw_64_current_align < log_size) -+ sw_64_align (log_size, (char *) NULL, sw_64_insn_label, 0); -+ if (sw_64_current_align > log_size) -+ sw_64_current_align = log_size; -+ sw_64_insn_label = NULL; -+ -+ float_cons (type); -+} -+ -+/* Handle the .proc pseudo op. We don't really do much with it except -+ parse it. */ -+ -+static void -+s_sw_64_proc (int is_static ATTRIBUTE_UNUSED) -+{ -+ char *name; -+ char c; -+ char *p; -+ symbolS *symbolP; -+ int temp; -+ -+ /* Takes ".proc name,nargs". */ -+ SKIP_WHITESPACE (); -+ c = get_symbol_name (&name); -+ p = input_line_pointer; -+ symbolP = symbol_find_or_make (name); -+ *p = c; -+ SKIP_WHITESPACE_AFTER_NAME (); -+ if (*input_line_pointer != ',') -+ { -+ *p = 0; -+ as_warn (_ ("Expected comma after name \"%s\""), name); -+ *p = c; -+ temp = 0; -+ ignore_rest_of_line (); -+ } -+ else -+ { -+ input_line_pointer++; -+ temp = get_absolute_expression (); -+ } -+ /* *symbol_get_obj (symbolP) = (signed char) temp; */ -+ (void) symbolP; -+ as_warn (_ ("unhandled: .proc %s,%d"), name, temp); -+ demand_empty_rest_of_line (); -+} -+ -+/* Handle the .set pseudo op. This is used to turn on and off most of -+ the assembler features. */ -+ -+static void -+s_sw_64_set (int x ATTRIBUTE_UNUSED) -+{ -+ char *name, ch, *s; -+ int yesno = 1; -+ -+ SKIP_WHITESPACE (); -+ -+ ch = get_symbol_name (&name); -+ s = name; -+ if (s[0] == 'n' && s[1] == 'o') -+ { -+ yesno = 0; -+ s += 2; -+ } -+ if (!strcmp ("reorder", s)) -+ /* ignore */; -+ else if (!strcmp ("at", s)) -+ sw_64_noat_on = !yesno; -+ else if (!strcmp ("macro", s)) -+ sw_64_macros_on = yesno; -+ else if (!strcmp ("move", s)) -+ /* ignore */; -+ else if (!strcmp ("volatile", s)) -+ /* ignore */; -+ else -+ as_warn (_ ("Tried to .set unrecognized mode `%s'"), name); -+ -+ (void) restore_line_pointer (ch); -+ demand_empty_rest_of_line (); -+} -+ -+/* Handle the .base pseudo op. This changes the assembler's notion of -+ the $gp register. */ -+ -+static void -+s_sw_64_base (int ignore ATTRIBUTE_UNUSED) -+{ -+ SKIP_WHITESPACE (); -+ -+ if (*input_line_pointer == '$') -+ { -+ /* $rNN form. */ -+ input_line_pointer++; -+ if (*input_line_pointer == 'r') -+ input_line_pointer++; -+ } -+ -+ sw_64_gp_register = get_absolute_expression (); -+ if (sw_64_gp_register < 0 || sw_64_gp_register > 31) -+ { -+ sw_64_gp_register = AXP_REG_GP; -+ as_warn (_ ("Bad base register, using $%d."), sw_64_gp_register); -+ } -+ -+ demand_empty_rest_of_line (); -+} -+ -+/* Handle the .align pseudo-op. This aligns to a power of two. It -+ also adjusts any current instruction label. We treat this the same -+ way the MIPS port does: .align 0 turns off auto alignment. */ -+ -+static void -+s_sw_64_align (int ignore ATTRIBUTE_UNUSED) -+{ -+ int align; -+ char fill, *pfill; -+ long max_alignment = 16; -+ -+ align = get_absolute_expression (); -+ if (align > max_alignment) -+ { -+ align = max_alignment; -+ as_bad (_ ("Alignment too large: %d. assumed"), align); -+ } -+ else if (align < 0) -+ { -+ as_warn (_ ("Alignment negative: 0 assumed")); -+ align = 0; -+ } -+ -+ if (*input_line_pointer == ',') -+ { -+ input_line_pointer++; -+ fill = get_absolute_expression (); -+ pfill = &fill; -+ } -+ else -+ pfill = NULL; -+ -+ if (align != 0) -+ { -+ sw_64_auto_align_on = 1; -+ sw_64_align (align, pfill, NULL, 1); -+ } -+ else -+ { -+ sw_64_auto_align_on = 0; -+ } -+ sw_64_insn_label = NULL; -+ -+ demand_empty_rest_of_line (); -+} -+ -+/* Hook the normal string processor to reset known alignment. */ -+ -+static void -+s_sw_64_stringer (int terminate) -+{ -+ sw_64_current_align = 0; -+ sw_64_insn_label = NULL; -+ stringer (8 + terminate); -+} -+ -+/* Hook the normal space processing to reset known alignment. */ -+ -+static void -+s_sw_64_space (int ignore) -+{ -+ sw_64_current_align = 0; -+ sw_64_insn_label = NULL; -+ s_space (ignore); -+} -+ -+/* Hook into cons for auto-alignment. */ -+ -+void -+sw_64_cons_align (int size) -+{ -+ int log_size; -+ -+ log_size = 0; -+ while ((size >>= 1) != 0) -+ ++log_size; -+ -+ if (sw_64_auto_align_on && sw_64_current_align < log_size) -+ sw_64_align (log_size, (char *) NULL, sw_64_insn_label, 0); -+ if (sw_64_current_align > log_size) -+ sw_64_current_align = log_size; -+ sw_64_insn_label = NULL; -+} -+ -+/* Here come the .uword, .ulong, and .uquad explicitly unaligned -+ pseudos. We just turn off auto-alignment and call down to cons. */ -+ -+static void -+s_sw_64_ucons (int bytes) -+{ -+ int hold = sw_64_auto_align_on; -+ sw_64_auto_align_on = 0; -+ cons (bytes); -+ sw_64_auto_align_on = hold; -+} -+ -+/* Switch the working cpu type. */ -+ -+static void -+s_sw_64_arch (int ignored ATTRIBUTE_UNUSED) -+{ -+ char *name, ch; -+ const struct cpu_type *p; -+ -+ SKIP_WHITESPACE (); -+ -+ ch = get_symbol_name (&name); -+ -+ for (p = cpu_types; p->name; ++p) -+ if (strcmp (name, p->name) == 0) -+ { -+ sw_64_target_name = p->name, sw_64_target = p->flags; -+ goto found; -+ } -+ as_warn (_ ("Unknown CPU identifier `%s'"), name); -+ -+found: -+ (void) restore_line_pointer (ch); -+ demand_empty_rest_of_line (); -+} -+ -+#ifdef DEBUG1 -+/* print token expression with sw_64 specific extension. */ -+ -+static void -+sw_64_print_token (FILE *f, const expressionS *exp) -+{ -+ switch (exp->X_op) -+ { -+ case O_cpregister: -+ putc (',', f); -+ /* FALLTHRU */ -+ case O_pregister: -+ putc ('(', f); -+ { -+ expressionS nexp = *exp; -+ nexp.X_op = O_register; -+ print_expr_1 (f, &nexp); -+ } -+ putc (')', f); -+ break; -+ default: -+ print_expr_1 (f, exp); -+ break; -+ } -+} -+#endif -+ -+/* The target specific pseudo-ops which we support. */ -+ -+const pseudo_typeS md_pseudo_table[] = { -+#ifdef OBJ_ECOFF -+ {"comm", s_sw_64_comm, 0}, /* OSF1 compiler does this. */ -+ {"rdata", s_sw_64_rdata, 0}, -+#endif -+ {"text", s_sw_64_text, 0}, -+ {"data", s_sw_64_data, 0}, -+#ifdef OBJ_ECOFF -+ {"sdata", s_sw_64_sdata, 0}, -+#endif -+#ifdef OBJ_ELF -+ {"section", s_sw_64_section, 0}, -+ {"section.s", s_sw_64_section, 0}, -+ {"sect", s_sw_64_section, 0}, -+ {"sect.s", s_sw_64_section, 0}, -+#endif -+#ifdef OBJ_EVAX -+ {"section", s_sw_64_section, 0}, -+ {"literals", s_sw_64_literals, 0}, -+ {"pdesc", s_sw_64_pdesc, 0}, -+ {"name", s_sw_64_name, 0}, -+ {"linkage", s_sw_64_linkage, 0}, -+ {"code_address", s_sw_64_code_address, 0}, -+ {"ent", s_sw_64_ent, 0}, -+ {"frame", s_sw_64_frame, 0}, -+ {"fp_save", s_sw_64_fp_save, 0}, -+ {"mask", s_sw_64_mask, 0}, -+ {"fmask", s_sw_64_fmask, 0}, -+ {"end", s_sw_64_end, 0}, -+ {"file", s_sw_64_file, 0}, -+ {"rdata", s_sw_64_section, 1}, -+ {"comm", s_sw_64_comm, 0}, -+ {"link", s_sw_64_section, 3}, -+ {"ctors", s_sw_64_section, 4}, -+ {"dtors", s_sw_64_section, 5}, -+ {"handler", s_sw_64_handler, 0}, -+ {"handler_data", s_sw_64_handler, 1}, -+#endif -+#ifdef OBJ_ELF -+ /* Frame related pseudos. */ -+ {"ent", s_sw_64_ent, 0}, -+ {"end", s_sw_64_end, 0}, -+ {"mask", s_sw_64_mask, 0}, -+ {"fmask", s_sw_64_mask, 1}, -+ {"frame", s_sw_64_frame, 0}, -+ {"prologue", s_sw_64_prologue, 0}, -+ {"file", s_sw_64_file, 5}, -+ {"loc", s_sw_64_loc, 9}, -+ {"stabs", s_sw_64_stab, 's'}, -+ {"stabn", s_sw_64_stab, 'n'}, -+ {"usepv", s_sw_64_usepv, 0}, -+ /* COFF debugging related pseudos. */ -+ {"begin", s_sw_64_coff_wrapper, 0}, -+ {"bend", s_sw_64_coff_wrapper, 1}, -+ {"def", s_sw_64_coff_wrapper, 2}, -+ {"dim", s_sw_64_coff_wrapper, 3}, -+ {"endef", s_sw_64_coff_wrapper, 4}, -+ {"scl", s_sw_64_coff_wrapper, 5}, -+ {"tag", s_sw_64_coff_wrapper, 6}, -+ {"val", s_sw_64_coff_wrapper, 7}, -+#else -+#ifdef OBJ_EVAX -+ {"prologue", s_sw_64_prologue, 0}, -+#else -+ {"prologue", s_ignore, 0}, -+#endif -+#endif -+ {"gprel32", s_sw_64_gprel32, 0}, -+ {"t_floating", s_sw_64_float_cons, 'd'}, -+ {"s_floating", s_sw_64_float_cons, 'f'}, -+ {"f_floating", s_sw_64_float_cons, 'F'}, -+ {"g_floating", s_sw_64_float_cons, 'G'}, -+ {"d_floating", s_sw_64_float_cons, 'D'}, -+ -+ {"proc", s_sw_64_proc, 0}, -+ {"aproc", s_sw_64_proc, 1}, -+ {"set", s_sw_64_set, 0}, -+ {"reguse", s_ignore, 0}, -+ {"livereg", s_ignore, 0}, -+ {"base", s_sw_64_base, 0}, /*??*/ -+ {"option", s_ignore, 0}, -+ {"aent", s_ignore, 0}, -+ {"ugen", s_ignore, 0}, -+ {"eflag", s_ignore, 0}, -+ -+ {"align", s_sw_64_align, 0}, -+ {"double", s_sw_64_float_cons, 'd'}, -+ {"float", s_sw_64_float_cons, 'f'}, -+ {"single", s_sw_64_float_cons, 'f'}, -+ {"ascii", s_sw_64_stringer, 0}, -+ {"asciz", s_sw_64_stringer, 1}, -+ {"string", s_sw_64_stringer, 1}, -+ {"space", s_sw_64_space, 0}, -+ {"skip", s_sw_64_space, 0}, -+ {"zero", s_sw_64_space, 0}, -+ -+ /* Unaligned data pseudos. */ -+ {"uword", s_sw_64_ucons, 2}, -+ {"ulong", s_sw_64_ucons, 4}, -+ {"uquad", s_sw_64_ucons, 8}, -+ -+#ifdef OBJ_ELF -+ /* Dwarf wants these versions of unaligned. */ -+ {"2byte", s_sw_64_ucons, 2}, -+ {"4byte", s_sw_64_ucons, 4}, -+ {"8byte", s_sw_64_ucons, 8}, -+#endif -+ -+ /* We don't do any optimizing, so we can safely ignore these. */ -+ {"noalias", s_ignore, 0}, -+ {"alias", s_ignore, 0}, -+ -+ {"arch", s_sw_64_arch, 0}, -+ -+ {NULL, 0, 0}, -+}; -+ -+#ifdef OBJ_ECOFF -+ -+/* @@@ GP selection voodoo. All of this seems overly complicated and -+ unnecessary; which is the primary reason it's for ECOFF only. */ -+ -+static inline void -+maybe_set_gp (asection *sec) -+{ -+ bfd_vma vma; -+ -+ if (!sec) -+ return; -+ vma = bfd_section_vma (sec); -+ if (vma && vma < sw_64_gp_value) -+ sw_64_gp_value = vma; -+} -+ -+static void -+select_gp_value (void) -+{ -+ gas_assert (sw_64_gp_value == 0); -+ -+ /* Get minus-one in whatever width... */ -+ sw_64_gp_value = 0; -+ sw_64_gp_value--; -+ -+ /* Select the smallest VMA of these existing sections. */ -+ maybe_set_gp (sw_64_lita_section); -+ -+/* @@ Will a simple 0x8000 work here? If not, why not? */ -+#define GP_ADJUSTMENT (0x8000 - 0x10) -+ -+ sw_64_gp_value += GP_ADJUSTMENT; -+ -+ S_SET_VALUE (sw_64_gp_symbol, sw_64_gp_value); -+ -+#ifdef DEBUG1 -+ printf (_ ("Chose GP value of %lx\n"), sw_64_gp_value); -+#endif -+} -+#endif /* OBJ_ECOFF */ -+ -+#ifdef OBJ_ELF -+/* Map 's' to SHF_SW_64_GPREL. */ -+ -+bfd_vma -+sw_64_elf_section_letter (int letter, const char **ptr_msg) -+{ -+ if (letter == 's') -+ return SHF_SW_64_GPREL; -+ -+ *ptr_msg = _ ("bad .section directive: want a,s,w,x,M,S,G,T in string"); -+ return -1; -+} -+ -+/* Map SHF_SW_64_GPREL to SEC_SMALL_DATA. */ -+ -+flagword -+sw_64_elf_section_flags (flagword flags, bfd_vma attr, -+ int type ATTRIBUTE_UNUSED) -+{ -+ if (attr & SHF_SW_64_GPREL) -+ flags |= SEC_SMALL_DATA; -+ return flags; -+} -+#endif /* OBJ_ELF */ -+ -+/* This is called from HANDLE_ALIGN in write.c. Fill in the contents -+ of an rs_align_code fragment. */ -+ -+void -+sw_64_handle_align (fragS *fragp) -+{ -+ static unsigned char const unop[4] = {0x5f, 0x07, 0xff, 0x43}; -+ static unsigned char const nopunop[8] -+ = {0x5f, 0x07, 0xff, 0x43, 0x5f, 0x07, 0xff, 0x43}; -+ -+ int bytes, fix; -+ char *p; -+ -+ if (fragp->fr_type != rs_align_code) -+ return; -+ -+ bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; -+ p = fragp->fr_literal + fragp->fr_fix; -+ fix = 0; -+ -+ if (bytes & 3) -+ { -+ fix = bytes & 3; -+ memset (p, 0, fix); -+ p += fix; -+ bytes -= fix; -+ } -+ -+ if (bytes & 4) -+ { -+ memcpy (p, unop, 4); -+ p += 4; -+ bytes -= 4; -+ fix += 4; -+ } -+ -+ memcpy (p, nopunop, 8); -+ -+ fragp->fr_fix += fix; -+ fragp->fr_var = 8; -+} -+ -+/* Public interface functions. */ -+ -+/* This function is called once, at assembler startup time. It sets -+ up all the tables, etc. that the MD part of the assembler will -+ need, that can be determined before arguments are parsed. */ -+ -+void -+md_begin (void) -+{ -+ unsigned int i; -+ -+ /* Verify that X_op field is wide enough. */ -+ { -+ expressionS e; -+ -+ e.X_op = O_max; -+ gas_assert (e.X_op == O_max); -+ } -+ -+ if (!bfd_set_arch_mach (stdoutput, bfd_arch_sw_64, file_sw_64_arch)) -+ as_warn (_ ("could not set architecture and machine")); -+ -+ /* Create the opcode hash table. */ -+ sw_64_opcode_hash = str_htab_create (); -+ -+ for (i = 0; i < sw_64_num_opcodes;) -+ { -+ const char *name, *slash; -+ -+ name = sw_64_opcodes[i].name; -+ if (str_hash_insert (sw_64_opcode_hash, name, &sw_64_opcodes[i], 0)) -+ as_fatal (_ ("internal error: can't hash opcode `%s': %s"), name); -+ -+ /* Some opcodes include modifiers of various sorts with a "/mod" -+ syntax, like the architecture manual suggests. However, for -+ use with gcc at least, we also need access to those same opcodes -+ without the "/". */ -+ -+ if ((slash = strchr (name, '/')) != NULL) -+ { -+ size_t len = strlen (name); -+ char *p = notes_alloc (len); -+ size_t len1 = slash - name; -+ -+ memcpy (p, name, len1); -+ memcpy (p + len1, slash + 1, len - len1); -+ -+ (void) str_hash_insert (sw_64_opcode_hash, p, &sw_64_opcodes[i], 0); -+ /* Ignore failures -- the opcode table does duplicate some -+ variants in different forms, like "hw_stq" and "hw_st/q". */ -+ } -+ -+ while (++i < sw_64_num_opcodes -+ && (sw_64_opcodes[i].name == name -+ || !strcmp (sw_64_opcodes[i].name, name))) -+ continue; -+ } -+ -+ /* Create the macro hash table. */ -+ sw_64_macro_hash = str_htab_create (); -+ -+ for (i = 0; i < sw_64_num_macros;) -+ { -+ const char *name, *retval; -+ -+ name = sw_64_macros[i].name; -+ if (str_hash_insert (sw_64_macro_hash, name, &sw_64_macros[i], 0)) -+ as_fatal (_ ("internal error: can't hash macro `%s': %s"), name); -+ -+ while (++i < sw_64_num_macros -+ && (sw_64_macros[i].name == name -+ || !strcmp (sw_64_macros[i].name, name))) -+ continue; -+ } -+ -+ /* Construct symbols for each of the registers. */ -+ for (i = 0; i < 32; ++i) -+ { -+ char name[4]; -+ -+ sprintf (name, "$%d", i); -+ sw_64_register_table[i] -+ = symbol_create (name, reg_section, &zero_address_frag, i); -+ } -+ -+ for (; i < 64; ++i) -+ { -+ char name[5]; -+ -+ sprintf (name, "$f%d", i - 32); -+ sw_64_register_table[i] -+ = symbol_create (name, reg_section, &zero_address_frag, i); -+ } -+ -+ /* Create the special symbols and sections we'll be using. */ -+ -+ /* So .sbss will get used for tiny objects. */ -+ bfd_set_gp_size (stdoutput, g_switch_value); -+ -+#ifdef OBJ_ECOFF -+ create_literal_section (".lita", &sw_64_lita_section, &sw_64_lita_symbol); -+ -+ /* For handling the GP, create a symbol that won't be output in the -+ symbol table. We'll edit it out of relocs later. */ -+ sw_64_gp_symbol = symbol_create ("", sw_64_lita_section, -+ &zero_address_frag, 0x8000); -+#endif -+ -+#ifdef OBJ_EVAX -+ create_literal_section (".link", &sw_64_link_section, &sw_64_link_symbol); -+#endif -+ -+#ifdef OBJ_ELF -+ if (ECOFF_DEBUGGING) -+ { -+ segT sec = subseg_new (".mdebug", (subsegT) 0); -+ bfd_set_section_flags (sec, SEC_HAS_CONTENTS | SEC_READONLY); -+ bfd_set_section_alignment (sec, 3); -+ } -+#endif -+ -+ /* Create literal lookup hash table. */ -+ sw_64_literal_hash = str_htab_create (); -+ -+ subseg_set (text_section, 0); -+} -+ -+/* The public interface to the instruction assembler. */ -+ -+void -+md_assemble (char *str) -+{ -+ /* Current maximum is 13. */ -+ char opname[32]; -+ expressionS tok[MAX_INSN_ARGS]; -+ int ntok, trunclen; -+ size_t opnamelen; -+ -+ /* Split off the opcode. */ -+ opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_/0123456789"); -+ trunclen -+ = (opnamelen < sizeof (opname) - 1 ? opnamelen : sizeof (opname) - 1); -+ memcpy (opname, str, trunclen); -+ opname[trunclen] = '\0'; -+ -+ if (!strcmp (opname, "ldw_inc") || !strcmp (opname, "ldl_inc") -+ || !strcmp (opname, "ldw_dec") || !strcmp (opname, "ldl_dec") -+ || !strcmp (opname, "ldw_set") || !strcmp (opname, "ldl_set")) -+ { -+ if (!strcmp (sw_64_target_name, "sw6a")) -+ as_warn (_ ("The %s is only 6A instruction, you better change it!"), -+ opname); -+ if (!strcmp (sw_64_target_name, "sw6b")) -+ as_bad (_ ("sw6b don't have \"%s\" !!"), (char *) opname); -+ } -+ -+ /* Tokenize the rest of the line. */ -+ if ((ntok = tokenize_arguments (str + opnamelen, tok, MAX_INSN_ARGS)) < 0) -+ { -+ if (ntok != TOKENIZE_ERROR_REPORT) -+ as_bad (_ ("syntax error")); -+ -+ return; -+ } -+ -+#define REG_NUM 64 -+ int i, j; -+ char float_insn[REG_NUM][REG_NUM] -+ = {"fadds", "faddd", "fsubs", "fsubd", "fmuls", "fmuld", -+ "fdivs", "fdivd", "fsqrts", "fsqrtd", "fcmpeq", "fcmple", -+ "fcmplt", "fcmpun", "fcvtsd", "fcvtds", "fcvtdl_g", "fcvtdl_p", -+ "fcvtdl_z", "fcvtdl_n", "fcvtdl", "fcvtlw", "fcvtls", "fcvtld", -+ "fmas", "fmad", "fmss", "fmsd", "fnmas", "fnmad", -+ "fnmss", "fnmsd", "vadds", "vaddd", "vsubs", "vsubd", -+ "vmuls", "vmuld", "vdivs", "vdivd", "vsqrts", "vsqrtd", -+ "vmas", "vmad", "vmss", "vmsd", "vnmas", "vnmad", -+ "vnmss", "vnmsd", "vfcmpeq", "vfcmple", "vfcmplt", "vfcmpun"}; -+ if (!sw_64_flag_nocheck_samereg) -+ { -+ for (i = 0; i < REG_NUM; i++) -+ { -+ if (strcmp (opname, float_insn[i]) == 0) -+ { -+ for (j = 0; j < ntok - 1; j++) -+ { -+ if (tok[j].X_add_number == tok[ntok - 1].X_add_number) -+ if (!strcmp (sw_64_target_name, "sw6b")) -+ ; -+ else if (!strcmp (sw_64_target_name, "sw8a")) -+ ; -+ else -+ as_warn ( -+ _ ("SRC and DST register of '%s' must be different!"), -+ opname); -+ } -+ } -+ } -+ } -+ /* sw8a don't have 'rd_f', 'wr_f' and atomic_op instructions. */ -+ if (!strcmp (sw_64_target_name, "sw8a") -+ && (!strcmp (opname, "rd_f") || !strcmp (opname, "wr_f") -+ || !strcmp (opname, "ldw_inc") || !strcmp (opname, "ldl_inc") -+ || !strcmp (opname, "ldw_dec") || !strcmp (opname, "ldl_dec") -+ || !strcmp (opname, "ldw_set") || !strcmp (opname, "ldw_set"))) -+ as_warn (_ ("sw8a don't have \"%s\" !!"), (char *) opname); -+ -+ if (sw_64_branch_separate == 1) -+ { -+ if ((strcmp (opname, "beq") == 0) || (strcmp (opname, "bne") == 0) -+ || (strcmp (opname, "bge") == 0) || (strcmp (opname, "bgt") == 0) -+ || (strcmp (opname, "ble") == 0) || (strcmp (opname, "blt") == 0) -+ || (strcmp (opname, "blbc") == 0) || (strcmp (opname, "blbs") == 0) -+ || (strcmp (opname, "fbeq") == 0) || (strcmp (opname, "fbge") == 0) -+ || (strcmp (opname, "fbgt") == 0) || (strcmp (opname, "fble") == 0) -+ || (strcmp (opname, "fblt") == 0) || (strcmp (opname, "fbne") == 0)) -+ { -+ if (nop_quantity > 0) -+ { -+ tokenize_arguments ("", toksave, MAX_INSN_ARGS); -+ for (; nop_quantity < 4; nop_quantity++) -+ assemble_tokens ("nop", toksave, 0, 1); -+ } -+ nop_quantity = 1; -+ } -+ else -+ { -+ if (nop_quantity > 0) -+ nop_quantity = (nop_quantity + 1) % 4; -+ } -+ } -+ -+ /* Finish it off. */ -+ assemble_tokens (opname, tok, ntok, sw_64_macros_on); -+} -+ -+/* Round up a section's size to the appropriate boundary. */ -+ -+valueT -+md_section_align (segT seg, valueT size) -+{ -+ int align = bfd_section_alignment (seg); -+ valueT mask = ((valueT) 1 << align) - 1; -+ -+ return (size + mask) & ~mask; -+} -+ -+/* Turn a string in input_line_pointer into a floating point constant -+ of type TYPE, and store the appropriate bytes in *LITP. The number -+ of LITTLENUMS emitted is stored in *SIZEP. An error message is -+ returned, or NULL on OK. */ -+ -+const char * -+md_atof (int type, char *litP, int *sizeP) -+{ -+ extern const char *vax_md_atof (int, char *, int *); -+ -+ switch (type) -+ { -+ /* VAX floats. */ -+ case 'G': -+ /* vax_md_atof () doesn't like "G" for some reason. */ -+ type = 'g'; -+ /* Fall through. */ -+ case 'F': -+ case 'D': -+ return vax_md_atof (type, litP, sizeP); -+ -+ default: -+ return ieee_md_atof (type, litP, sizeP, FALSE); -+ } -+} -+ -+/* Take care of the target-specific command-line options. */ -+ -+int -+md_parse_option (int c, const char *arg) -+{ -+ switch (c) -+ { -+ case 'F': -+ sw_64_nofloats_on = 1; -+ break; -+ -+ case OPTION_32ADDR: -+ sw_64_addr32_on = 1; -+ break; -+ -+ case 'g': -+ sw_64_debug = 1; -+ break; -+ -+ case 'G': -+ g_switch_value = atoi (arg); -+ break; -+ -+ case 'm': { -+ const struct cpu_type *p; -+ -+ for (p = cpu_types; p->name; ++p) -+ if (strcmp (arg, p->name) == 0) -+ { -+ sw_64_target_name = p->name, sw_64_target = p->flags; -+ goto found; -+ } -+ as_warn (_ ("Unknown CPU identifier `%s'"), arg); -+ found:; -+ } -+ break; -+ -+#ifdef OBJ_EVAX -+ case '+': /* For g++. Hash any name > 63 chars long. */ -+ sw_64_flag_hash_long_names = 1; -+ break; -+ -+ case 'H': /* Show new symbol after hash truncation. */ -+ sw_64_flag_show_after_trunc = 1; -+ break; -+ -+ case 'h': /* For gnu-c/vax compatibility. */ -+ break; -+ -+ case OPTION_REPLACE: -+ sw_64_flag_replace = 1; -+ break; -+ -+ case OPTION_NOREPLACE: -+ sw_64_flag_replace = 0; -+ break; -+#endif -+ -+ case OPTION_RELAX: -+ sw_64_flag_relax = 1; -+ break; -+ -+#ifdef OBJ_ELF -+ case OPTION_MDEBUG: -+ sw_64_flag_mdebug = 1; -+ break; -+ case OPTION_NO_MDEBUG: -+ sw_64_flag_mdebug = 0; -+ break; -+#endif -+ -+ case OPTION_NOCHECK_SAMEREG: -+ sw_64_flag_nocheck_samereg = 1; -+ break; -+ -+ case OPTION_LITERALGOT: -+ sw_64_literalgot_on = 1; -+ break; -+ -+ case OPTION_TLSRELGOT_GOTTPREL: -+ sw_64_tlsrelgot_gottprel_on = 1; -+ break; -+ -+ case OPTION_TLSRELGOT_GOTDTPREL: -+ sw_64_tlsrelgot_gotdtprel_on = 1; -+ break; -+ -+ case OPTION_TLSRELGOT_TLSLDM: -+ sw_64_tlsrelgot_tlsldm_on = 1; -+ break; -+ -+ case OPTION_TLSRELGOT_TLSGD: -+ sw_64_tlsrelgot_tlsgd_on = 1; -+ break; -+ -+ case OPTION_GPREL16: -+ sw_64_gprel16_on = 1; -+ break; -+ -+ case OPTION_BRANCH_SEPARATE: -+ sw_64_branch_separate = 1; -+ break; -+ case OPTION_NOBRANCH_SEPARATE: -+ sw_64_branch_separate = 0; -+ break; -+ -+ default: -+ return 0; -+ } -+ -+ return 1; -+} -+ -+/* Print a description of the command-line options that we accept. */ -+ -+void -+md_show_usage (FILE *stream) -+{ -+ fputs (_ ("\ -+Sw_64 options:\n\ -+-32addr treat addresses as 32-bit values\n\ -+-F lack floating point instructions support\n\ -+-msw6a | -msw6b\n\ -+ these variants include PALcode opcodes\n\ -+-tlsrelgot_tlsgd\n\ -+ insert ldih instruction with tlsrel_got relocation before ldi instruction with tlsgd relocation\n\ -+-tlsrelgot_tlsldm\n\ -+ insert ldih instruction with tlsrel_got relocation before ldi instruction with tlsldm relocation\n\ -+-literalgot\n\ -+ insert ldih instruction with literal_got relocation before ldl instruction with literal relocation\n\ -+-gprel16\n\ -+ change gprel16 relocation to gprelhi+gprello relocation with ldih instruction and ldi/ldw/flds/fldd instruction\n"), -+ stream); -+ -+#ifdef OBJ_EVAX -+ fputs (_ ("\ -+VMS options:\n\ -+-+ encode (don't truncate) names longer than 64 characters\n\ -+-H show new symbol after hash truncation\n\ -+-replace/-noreplace enable or disable the optimization of procedure calls\n"), -+ stream); -+#endif -+} -+ -+/* Decide from what point a pc-relative relocation is relative to, -+ relative to the pc-relative fixup. Er, relatively speaking. */ -+ -+long -+md_pcrel_from (fixS *fixP) -+{ -+ valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; -+ -+ switch (fixP->fx_r_type) -+ { -+ case BFD_RELOC_23_PCREL_S2: -+ case BFD_RELOC_SW_64_BR26: -+ case BFD_RELOC_SW_64_HINT: -+ case BFD_RELOC_SW_64_BRSGP: -+ return addr + 4; -+ default: -+ return addr; -+ } -+} -+ -+/* Attempt to simplify or even eliminate a fixup. The return value is -+ ignored; perhaps it was once meaningful, but now it is historical. -+ To indicate that a fixup has been eliminated, set fixP->fx_done. -+ -+ For ELF, here it is that we transform the GPDISP_HI16 reloc we used -+ internally into the GPDISP reloc used externally. We had to do -+ this so that we'd have the GPDISP_LO16 reloc as a tag to compute -+ the distance to the "ldi" instruction for setting the addend to -+ GPDISP. */ -+ -+void -+md_apply_fix (fixS *fixP, valueT *valP, segT seg) -+{ -+ char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where; -+ valueT value = *valP; -+ unsigned image, size; -+ -+ switch (fixP->fx_r_type) -+ { -+ /* The GPDISP relocations are processed internally with a symbol -+ referring to the current function's section; we need to drop -+ in a value which, when added to the address of the start of -+ the function, gives the desired GP. */ -+ case BFD_RELOC_SW_64_GPDISP_HI16: { -+ fixS *next = fixP->fx_next; -+ -+ /* With user-specified !gpdisp relocations, we can be missing -+ the matching LO16 reloc. We will have already issued an -+ error message. */ -+ if (next) -+ fixP->fx_offset = (next->fx_frag->fr_address + next->fx_where -+ - fixP->fx_frag->fr_address - fixP->fx_where); -+ -+ value = (value - sign_extend_16 (value)) >> 16; -+ } -+#ifdef OBJ_ELF -+ fixP->fx_r_type = BFD_RELOC_SW_64_GPDISP; -+#endif -+ goto do_reloc_gp; -+ -+ case BFD_RELOC_SW_64_GPDISP_LO16: -+ value = sign_extend_16 (value); -+ fixP->fx_offset = 0; -+#ifdef OBJ_ELF -+ fixP->fx_done = 1; -+#endif -+ -+ do_reloc_gp: -+ fixP->fx_addsy = section_symbol (seg); -+ md_number_to_chars (fixpos, value, 2); -+ break; -+ case BFD_RELOC_8: -+ if (fixP->fx_pcrel) -+ fixP->fx_r_type = BFD_RELOC_8_PCREL; -+ size = 1; -+ goto do_reloc_xx; -+ case BFD_RELOC_16: -+ if (fixP->fx_pcrel) -+ fixP->fx_r_type = BFD_RELOC_16_PCREL; -+ size = 2; -+ goto do_reloc_xx; -+ -+ case BFD_RELOC_32: -+ if (fixP->fx_pcrel) -+ fixP->fx_r_type = BFD_RELOC_32_PCREL; -+ size = 4; -+ goto do_reloc_xx; -+ -+ case BFD_RELOC_64: -+ if (fixP->fx_pcrel) -+ fixP->fx_r_type = BFD_RELOC_64_PCREL; -+ size = 8; -+ -+ do_reloc_xx: -+ if (fixP->fx_pcrel == 0 && fixP->fx_addsy == 0) -+ { -+ md_number_to_chars (fixpos, value, size); -+ goto done; -+ } -+ return; -+ -+#ifdef OBJ_ECOFF -+ case BFD_RELOC_GPREL32: -+ gas_assert (fixP->fx_subsy == sw_64_gp_symbol); -+ fixP->fx_subsy = 0; -+ /* FIXME: inherited this obliviousness of `value' -- why? */ -+ md_number_to_chars (fixpos, -sw_64_gp_value, 4); -+ break; -+#else -+ case BFD_RELOC_GPREL32: -+#endif -+ case BFD_RELOC_GPREL16: -+ case BFD_RELOC_SW_64_GPREL_HI16: -+ case BFD_RELOC_SW_64_GPREL_LO16: -+ return; -+ -+ case BFD_RELOC_23_PCREL_S2: -+ if (fixP->fx_pcrel == 0 && fixP->fx_addsy == 0) -+ { -+ image = bfd_getl32 (fixpos); -+ image = (image & ~0x1FFFFF) | ((value >> 2) & 0x1FFFFF); -+ goto write_done; -+ } -+ return; -+ -+ case BFD_RELOC_SW_64_BR26: -+ if (fixP->fx_pcrel == 0 && fixP->fx_addsy == 0) -+ { -+ image = bfd_getl32 (fixpos); -+ image = (image & ~0x3FFFFFF) | ((value >> 2) & 0x3FFFFFF); -+ goto write_done; -+ } -+ return; -+ -+ case BFD_RELOC_SW_64_HINT: -+ if (fixP->fx_pcrel == 0 && fixP->fx_addsy == 0) -+ { -+ image = bfd_getl32 (fixpos); -+ /* SW6 use 16 bit hint disp,not 14. */ -+ image = (image & ~0xFFFF) | ((value >> 2) & 0xFFFF); -+ goto write_done; -+ } -+ return; -+ -+#ifdef OBJ_ELF -+ case BFD_RELOC_SW_64_BRSGP: -+ return; -+ -+ case BFD_RELOC_SW_64_TLSGD: -+ case BFD_RELOC_SW_64_TLSLDM: -+ case BFD_RELOC_SW_64_GOTDTPREL16: -+ case BFD_RELOC_SW_64_DTPREL_HI16: -+ case BFD_RELOC_SW_64_DTPREL_LO16: -+ case BFD_RELOC_SW_64_DTPREL16: -+ case BFD_RELOC_SW_64_GOTTPREL16: -+ case BFD_RELOC_SW_64_TPREL_HI16: -+ case BFD_RELOC_SW_64_TPREL_LO16: -+ case BFD_RELOC_SW_64_TPREL16: -+ if (fixP->fx_addsy) -+ S_SET_THREAD_LOCAL (fixP->fx_addsy); -+ return; -+#endif -+ -+#ifdef OBJ_ECOFF -+ case BFD_RELOC_SW_64_LITERAL: -+ md_number_to_chars (fixpos, value, 2); -+ return; -+#endif -+ case BFD_RELOC_SW_64_ELF_LITERAL: -+ case BFD_RELOC_SW_64_ELF_LITERAL_GOT: -+ case BFD_RELOC_SW_64_LITUSE: -+ case BFD_RELOC_SW_64_LINKAGE: -+ case BFD_RELOC_SW_64_CODEADDR: -+ case BFD_RELOC_SW_64_TLSREL_GOT: -+ return; -+ -+#ifdef OBJ_EVAX -+ case BFD_RELOC_SW_64_NOP: -+ value -= (8 + 4); /* PC-relative, base is call+4. */ -+ -+ /* From B.4.5.2 of the OpenVMS Linker Utility Manual: -+ "Finally, the ETIR$C_STC_BSR command passes the same address -+ as ETIR$C_STC_NOP (so that they will fail or succeed together), -+ and the same test is done again." */ -+ if (S_GET_SEGMENT (fixP->fx_addsy) == undefined_section) -+ { -+ fixP->fx_addnumber = -value; -+ return; -+ } -+ if (value + (1u << 22) >= (1u << 23)) -+ goto done; -+ else -+ { -+ /* Change to a nop. */ -+ image = 0x47FF041F; -+ goto write_done; -+ } -+ -+ case BFD_RELOC_SW_64_LDA: -+ /* fixup_segment sets fixP->fx_addsy to NULL when it can pre-compute -+ the value for an O_subtract. */ -+ if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) == undefined_section) -+ { -+ fixP->fx_addnumber = symbol_get_bfdsym (fixP->fx_subsy)->value; -+ return; -+ } -+ if (value + (1u << 15) >= (1u << 16)) -+ goto done; -+ else -+ { -+ /* Change to an ldi. */ -+ image = 0x237B0000 | (value & 0xFFFF); -+ goto write_done; -+ } -+ -+ case BFD_RELOC_SW_64_BSR: -+ case BFD_RELOC_SW_64_BOH: -+ value -= 4; /* PC-relative, base is call+4. */ -+ -+ /* See comment in the BFD_RELOC_SW_64_NOP case above. */ -+ if (S_GET_SEGMENT (fixP->fx_addsy) == undefined_section) -+ { -+ fixP->fx_addnumber = -value; -+ return; -+ } -+ if (value + (1u << 22) >= (1u << 23)) -+ { -+ /* Out of range. */ -+ if (fixP->fx_r_type == BFD_RELOC_SW_64_BOH) -+ { -+ /* Add a hint. */ -+ image = bfd_getl32 (fixpos); -+ image = (image & ~0x3FFF) | ((value >> 2) & 0x3FFF); -+ goto write_done; -+ } -+ goto done; -+ } -+ else -+ { -+ /* Change to a branch. */ -+ image = 0xD3400000 | ((value >> 2) & 0x1FFFFF); -+ goto write_done; -+ } -+#endif -+ -+ case BFD_RELOC_VTABLE_INHERIT: -+ case BFD_RELOC_VTABLE_ENTRY: -+ return; -+ -+ default: { -+ const struct sw_64_operand *operand; -+ -+ if ((int) fixP->fx_r_type >= 0) -+ as_fatal (_ ("unhandled relocation type %s"), -+ bfd_get_reloc_code_name (fixP->fx_r_type)); -+ -+ gas_assert (-(int) fixP->fx_r_type < (int) sw_64_num_operands); -+ operand = &sw_64_operands[-(int) fixP->fx_r_type]; -+ -+ /* The rest of these fixups only exist internally during symbol -+ resolution and have no representation in the object file. -+ Therefore they must be completely resolved as constants. */ -+ -+ if (fixP->fx_addsy != 0 -+ && S_GET_SEGMENT (fixP->fx_addsy) != absolute_section) -+ as_bad_where (fixP->fx_file, fixP->fx_line, -+ _ ("non-absolute expression in constant field")); -+ -+ image = bfd_getl32 (fixpos); -+ image = insert_operand (image, operand, (offsetT) value, fixP->fx_file, -+ fixP->fx_line); -+ } -+ goto write_done; -+ } -+ -+ if (fixP->fx_addsy != 0 || fixP->fx_pcrel != 0) -+ return; -+ else -+ { -+ as_warn_where (fixP->fx_file, fixP->fx_line, _ ("type %d reloc done?\n"), -+ (int) fixP->fx_r_type); -+ goto done; -+ } -+ -+write_done: -+ md_number_to_chars (fixpos, image, 4); -+ -+done: -+ fixP->fx_done = 1; -+} -+ -+/* Look for a register name in the given symbol. */ -+ -+symbolS * -+md_undefined_symbol (char *name) -+{ -+ if (*name == '$') -+ { -+ int is_float = 0, num; -+ -+ switch (*++name) -+ { -+ case 'f': -+ if (name[1] == 'p' && name[2] == '\0') -+ return sw_64_register_table[AXP_REG_FP]; -+ is_float = 32; -+ /* Fall through. */ -+ -+ case 'r': -+ if (!ISDIGIT (*++name)) -+ break; -+ /* Fall through. */ -+ -+ case '0': -+ case '1': -+ case '2': -+ case '3': -+ case '4': -+ case '5': -+ case '6': -+ case '7': -+ case '8': -+ case '9': -+ if (name[1] == '\0') -+ num = name[0] - '0'; -+ else if (name[0] != '0' && ISDIGIT (name[1]) && name[2] == '\0') -+ { -+ num = (name[0] - '0') * 10 + name[1] - '0'; -+ if (num >= 32) -+ break; -+ } -+ else -+ break; -+ -+ if (!sw_64_noat_on && (num + is_float) == AXP_REG_AT) -+ as_warn (_ ("Used $at without \".set noat\"")); -+ return sw_64_register_table[num + is_float]; -+ -+ case 'a': -+ if (name[1] == 't' && name[2] == '\0') -+ { -+ if (!sw_64_noat_on) -+ as_warn (_ ("Used $at without \".set noat\"")); -+ return sw_64_register_table[AXP_REG_AT]; -+ } -+ break; -+ -+ case 'g': -+ if (name[1] == 'p' && name[2] == '\0') -+ return sw_64_register_table[sw_64_gp_register]; -+ break; -+ -+ case 's': -+ if (name[1] == 'p' && name[2] == '\0') -+ return sw_64_register_table[AXP_REG_SP]; -+ break; -+ } -+ } -+ return NULL; -+} -+ -+#ifdef OBJ_ECOFF -+/* @@@ Magic ECOFF bits. */ -+ -+void -+sw_64_frob_ecoff_data (void) -+{ -+ select_gp_value (); -+ /* $zero and $f31 are read-only. */ -+ sw_64_gprmask &= ~1; -+ sw_64_fprmask &= ~1; -+} -+#endif -+ -+/* Hook to remember a recently defined label so that the auto-align -+ code can adjust the symbol after we know what alignment will be -+ required. */ -+ -+void -+sw_64_define_label (symbolS *sym) -+{ -+ sw_64_insn_label = sym; -+#ifdef OBJ_ELF -+ dwarf2_emit_label (sym); -+#endif -+} -+ -+/* Return true if we must always emit a reloc for a type and false if -+ there is some hope of resolving it at assembly time. */ -+ -+int -+sw_64_force_relocation (fixS *f) -+{ -+ if (sw_64_flag_relax) -+ return 1; -+ -+ switch (f->fx_r_type) -+ { -+ case BFD_RELOC_SW_64_GPDISP_HI16: -+ case BFD_RELOC_SW_64_GPDISP_LO16: -+ case BFD_RELOC_SW_64_GPDISP: -+ case BFD_RELOC_SW_64_LITERAL: -+ case BFD_RELOC_SW_64_ELF_LITERAL: -+ case BFD_RELOC_SW_64_ELF_LITERAL_GOT: -+ case BFD_RELOC_SW_64_LITUSE: -+ case BFD_RELOC_GPREL16: -+ case BFD_RELOC_GPREL32: -+ case BFD_RELOC_SW_64_GPREL_HI16: -+ case BFD_RELOC_SW_64_GPREL_LO16: -+ case BFD_RELOC_SW_64_LINKAGE: -+ case BFD_RELOC_SW_64_CODEADDR: -+ case BFD_RELOC_SW_64_BRSGP: -+ case BFD_RELOC_SW_64_TLSGD: -+ case BFD_RELOC_SW_64_TLSLDM: -+ case BFD_RELOC_SW_64_GOTDTPREL16: -+ case BFD_RELOC_SW_64_DTPREL_HI16: -+ case BFD_RELOC_SW_64_DTPREL_LO16: -+ case BFD_RELOC_SW_64_DTPREL16: -+ case BFD_RELOC_SW_64_GOTTPREL16: -+ case BFD_RELOC_SW_64_TPREL_HI16: -+ case BFD_RELOC_SW_64_TPREL_LO16: -+ case BFD_RELOC_SW_64_TPREL16: -+#ifdef OBJ_EVAX -+ case BFD_RELOC_SW_64_NOP: -+ case BFD_RELOC_SW_64_BSR: -+ case BFD_RELOC_SW_64_LDA: -+ case BFD_RELOC_SW_64_BOH: -+#endif -+ return 1; -+ -+ default: -+ break; -+ } -+ -+ return generic_force_reloc (f); -+} -+ -+/* Return true if we can partially resolve a relocation now. */ -+ -+int -+sw_64_fix_adjustable (fixS *f) -+{ -+ /* Are there any relocation types for which we must generate a -+ reloc but we can adjust the values contained within it? */ -+ switch (f->fx_r_type) -+ { -+ case BFD_RELOC_SW_64_GPDISP_HI16: -+ case BFD_RELOC_SW_64_GPDISP_LO16: -+ case BFD_RELOC_SW_64_GPDISP: -+ return 0; -+ -+ case BFD_RELOC_SW_64_LITERAL: -+ case BFD_RELOC_SW_64_ELF_LITERAL: -+ case BFD_RELOC_SW_64_ELF_LITERAL_GOT: -+ case BFD_RELOC_SW_64_LITUSE: -+ case BFD_RELOC_SW_64_LINKAGE: -+ case BFD_RELOC_SW_64_CODEADDR: -+ case BFD_RELOC_SW_64_TLSREL_GOT: -+ return 1; -+ -+ case BFD_RELOC_VTABLE_ENTRY: -+ case BFD_RELOC_VTABLE_INHERIT: -+ return 0; -+ -+ case BFD_RELOC_GPREL16: -+ case BFD_RELOC_GPREL32: -+ case BFD_RELOC_SW_64_GPREL_HI16: -+ case BFD_RELOC_SW_64_GPREL_LO16: -+ case BFD_RELOC_23_PCREL_S2: -+ case BFD_RELOC_SW_64_BR26: -+ case BFD_RELOC_16: -+ case BFD_RELOC_32: -+ case BFD_RELOC_64: -+ case BFD_RELOC_SW_64_HINT: -+ return 1; -+ -+ case BFD_RELOC_SW_64_TLSGD: -+ case BFD_RELOC_SW_64_TLSLDM: -+ case BFD_RELOC_SW_64_GOTDTPREL16: -+ case BFD_RELOC_SW_64_DTPREL_HI16: -+ case BFD_RELOC_SW_64_DTPREL_LO16: -+ case BFD_RELOC_SW_64_DTPREL16: -+ case BFD_RELOC_SW_64_GOTTPREL16: -+ case BFD_RELOC_SW_64_TPREL_HI16: -+ case BFD_RELOC_SW_64_TPREL_LO16: -+ case BFD_RELOC_SW_64_TPREL16: -+ /* ??? No idea why we can't return a reference to .tbss+10, but -+ we're preventing this in the other assemblers. Follow for now. */ -+ return 0; -+ -+#ifdef OBJ_ELF -+ case BFD_RELOC_SW_64_BRSGP: -+ /* If we have a BRSGP reloc to a local symbol, adjust it to BRADDR and -+ let it get resolved at assembly time. */ -+ { -+ symbolS *sym = f->fx_addsy; -+ const char *name; -+ int offset = 0; -+ -+ if (generic_force_reloc (f)) -+ return 0; -+ -+ switch (S_GET_OTHER (sym) & STO_SW_64_STD_GPLOAD) -+ { -+ case STO_SW_64_NOPV: -+ break; -+ case STO_SW_64_STD_GPLOAD: -+ offset = 8; -+ break; -+ default: -+ if (S_IS_LOCAL (sym)) -+ name = ""; -+ else -+ name = S_GET_NAME (sym); -+ as_bad_where ( -+ f->fx_file, f->fx_line, -+ _ ("!samegp reloc against symbol without .prologue: %s"), name); -+ break; -+ } -+ f->fx_r_type = BFD_RELOC_23_PCREL_S2; -+ f->fx_offset += offset; -+ return 1; -+ } -+#endif -+#ifdef OBJ_EVAX -+ case BFD_RELOC_SW_64_NOP: -+ case BFD_RELOC_SW_64_BSR: -+ case BFD_RELOC_SW_64_LDA: -+ case BFD_RELOC_SW_64_BOH: -+ return 1; -+#endif -+ -+ default: -+ return 1; -+ } -+} -+ -+/* Generate the BFD reloc to be stuck in the object file from the -+ fixup used internally in the assembler. */ -+ -+arelent * -+tc_gen_reloc (asection *sec ATTRIBUTE_UNUSED, fixS *fixp) -+{ -+ arelent *reloc; -+ -+ reloc = XNEW (arelent); -+ reloc->sym_ptr_ptr = XNEW (asymbol *); -+ *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); -+ reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; -+ -+ /* Make sure none of our internal relocations make it this far. -+ They'd better have been fully resolved by this point. */ -+ gas_assert ((int) fixp->fx_r_type > 0); -+ -+ reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); -+ if (reloc->howto == NULL) -+ { -+ as_bad_where (fixp->fx_file, fixp->fx_line, -+ _ ("cannot represent `%s' relocation in object file"), -+ bfd_get_reloc_code_name (fixp->fx_r_type)); -+ return NULL; -+ } -+ -+ if (!fixp->fx_pcrel != !reloc->howto->pc_relative) -+ as_fatal (_ ("internal error? cannot generate `%s' relocation"), -+ bfd_get_reloc_code_name (fixp->fx_r_type)); -+ -+ gas_assert (!fixp->fx_pcrel == !reloc->howto->pc_relative); -+ -+ reloc->addend = fixp->fx_offset; -+ -+#ifdef OBJ_ECOFF -+ /* Fake out bfd_perform_relocation. sigh. */ -+ /* ??? Better would be to use the special_function hook. */ -+ if (fixp->fx_r_type == BFD_RELOC_SW_64_LITERAL) -+ reloc->addend = -sw_64_gp_value; -+#endif -+ -+#ifdef OBJ_EVAX -+ switch (fixp->fx_r_type) -+ { -+ struct evax_private_udata_struct *udata; -+ const char *pname; -+ int pname_len; -+ -+ case BFD_RELOC_SW_64_LINKAGE: -+ /* Copy the linkage index. */ -+ reloc->addend = fixp->fx_addnumber; -+ break; -+ -+ case BFD_RELOC_SW_64_NOP: -+ case BFD_RELOC_SW_64_BSR: -+ case BFD_RELOC_SW_64_LDA: -+ case BFD_RELOC_SW_64_BOH: -+ pname = symbol_get_bfdsym (fixp->fx_addsy)->name; -+ -+ /* We need the non-suffixed name of the procedure. Beware that -+ the main symbol might be equated so look it up and take its name. */ -+ pname_len = strlen (pname); -+ if (pname_len > 4 && strcmp (pname + pname_len - 4, "..en") == 0) -+ { -+ symbolS *sym; -+ char *my_pname = xmemdup0 (pname, pname_len - 4); -+ sym = symbol_find (my_pname); -+ free (my_pname); -+ if (sym == NULL) -+ abort (); -+ -+ while (symbol_equated_reloc_p (sym)) -+ { -+ symbolS *n = symbol_get_value_expression (sym)->X_add_symbol; -+ -+ /* We must avoid looping, as that can occur with a badly -+ written program. */ -+ if (n == sym) -+ break; -+ sym = n; -+ } -+ pname = symbol_get_bfdsym (sym)->name; -+ } -+ -+ udata = XNEW (struct evax_private_udata_struct); -+ udata->enbsym = symbol_get_bfdsym (fixp->fx_addsy); -+ udata->bsym = symbol_get_bfdsym (fixp->tc_fix_data.info->psym); -+ udata->origname = (char *) pname; -+ udata->lkindex = ((struct evax_private_udata_struct *) symbol_get_bfdsym ( -+ fixp->tc_fix_data.info->sym) -+ ->udata.p) -+ ->lkindex; -+ reloc->sym_ptr_ptr = (void *) udata; -+ reloc->addend = fixp->fx_addnumber; -+ -+ default: -+ break; -+ } -+#endif -+ -+ return reloc; -+} -+ -+/* Parse a register name off of the input_line and return a register -+ number. Gets md_undefined_symbol above to do the register name -+ matching for us. -+ -+ Only called as a part of processing the ECOFF .frame directive. */ -+ -+int -+tc_get_register (int frame ATTRIBUTE_UNUSED) -+{ -+ int framereg = AXP_REG_SP; -+ -+ SKIP_WHITESPACE (); -+ if (*input_line_pointer == '$') -+ { -+ char *s; -+ char c = get_symbol_name (&s); -+ symbolS *sym = md_undefined_symbol (s); -+ -+ *strchr (s, '\0') = c; -+ if (sym && (framereg = S_GET_VALUE (sym)) <= 31) -+ goto found; -+ } -+ as_warn (_ ("frame reg expected, using $%d."), framereg); -+ -+found: -+ note_gpreg (framereg); -+ return framereg; -+} -+ -+/* This is called before the symbol table is processed. In order to -+ work with gcc when using mips-tfile, we must keep all local labels. -+ However, in other cases, we want to discard them. If we were -+ called with -g, but we didn't see any debugging information, it may -+ mean that gcc is smuggling debugging information through to -+ mips-tfile, in which case we must generate all local labels. */ -+ -+#ifdef OBJ_ECOFF -+ -+void -+sw_64_frob_file_before_adjust (void) -+{ -+ if (sw_64_debug != 0 && !ecoff_debugging_seen) -+ flag_keep_locals = 1; -+} -+ -+#endif /* OBJ_ECOFF */ -+ -+/* Set up globals to generate code for the ISA or processor -+ * described by INFO. */ -+ -+static void -+sw_64_set_architecture (const struct sw_64_cpu_info *info) -+{ -+ if (info != 0) -+ { -+ file_sw_64_arch = info->cpu; -+ sw_64_opts.arch = info->cpu; -+ sw_64_opts.isa = info->isa; -+ } -+} -+ -+void -+sw_64_after_parse_args (void) -+{ -+ const struct sw_64_cpu_info *arch_info = 0; -+ const struct sw_64_cpu_info *tune_info = 0; -+ -+ const struct cpu_type *p; -+ if (sw_64_target_name == NULL) -+ { -+ for (p = cpu_types; p->name; ++p) -+ if (strcmp (SW_CPU_STRING_DEFAULT, p->name) == 0) -+ { -+ sw_64_target_name = p->name, sw_64_target = p->flags; -+ goto found; -+ } -+ as_bad (_ ("Unknown CPU default name `%s'"), SW_CPU_STRING_DEFAULT); -+ found: -+ gas_assert (sw_64_target); -+ } -+ sw_64_set_architecture (arch_info); -+} -+ -+static const struct sw_64_cpu_info sw_64_cpu_info_table[] = { -+ /* Entries for generic ISAs. */ -+ {NULL, 0, 0, 0, 0}}; -+ -+/* The Sw_64 has support for some VAX floating point types, as well as for -+ IEEE floating point. We consider IEEE to be the primary floating point -+ format, and sneak in the VAX floating point support here. */ -+#include "config/atof-vax.c" -diff --git a/gas/config/tc-sw_64.h b/gas/config/tc-sw_64.h -new file mode 100644 -index 00000000..c3acee56 ---- /dev/null -+++ b/gas/config/tc-sw_64.h -@@ -0,0 +1,206 @@ -+/* This file is tc-sw_64.h -+ Copyright (C) 1994-2023 Free Software Foundation, Inc. -+ Written by Ken Raeburn . -+ -+ This file is part of GAS, the GNU Assembler. -+ -+ GAS is free software; you can redistribute it and/or modify -+ it under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 3, or (at your option) -+ any later version. -+ -+ GAS is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ GNU General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with GAS; see the file COPYING. If not, write to the Free -+ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA -+ 02110-1301, USA. */ -+ -+#define TC_SW_64 -+ -+#define TARGET_BYTES_BIG_ENDIAN 0 -+ -+#define WORKING_DOT_WORD -+ -+#define TARGET_ARCH bfd_arch_sw_64 -+ -+#ifdef TE_FreeBSD -+#define ELF_TARGET_FORMAT "elf64-sw_64-freebsd" -+#endif -+#ifndef ELF_TARGET_FORMAT -+#define ELF_TARGET_FORMAT "elf64-sw_64" -+#endif -+ -+#define TARGET_FORMAT \ -+ (OUTPUT_FLAVOR == bfd_target_ecoff_flavour ? "ecoff-littlesw_64" \ -+ : OUTPUT_FLAVOR == bfd_target_elf_flavour ? ELF_TARGET_FORMAT \ -+ : OUTPUT_FLAVOR == bfd_target_evax_flavour ? "vms-sw_64" \ -+ : "unknown-format") -+ -+#define NEED_LITERAL_POOL -+#define REPEAT_CONS_EXPRESSIONS -+ -+struct fix; -+struct sw_64_reloc_tag; -+ -+extern int -+sw_64_force_relocation (struct fix *); -+extern int -+sw_64_fix_adjustable (struct fix *); -+ -+extern unsigned long sw_64_gprmask, sw_64_fprmask; -+extern valueT sw_64_gp_value; -+ -+#define TC_FORCE_RELOCATION(FIX) sw_64_force_relocation (FIX) -+#define tc_fix_adjustable(FIX) sw_64_fix_adjustable (FIX) -+#define RELOC_REQUIRES_SYMBOL -+ -+/* Values passed to md_apply_fix don't include the symbol value. */ -+#define MD_APPLY_SYM_VALUE(FIX) 0 -+ -+#define md_convert_frag(b, s, f) as_fatal ("sw_64 convert_frag\n") -+#define md_estimate_size_before_relax(f, s) \ -+ (as_fatal ("estimate_size_before_relax called"), 1) -+#define md_operand(x) -+ -+#ifdef OBJ_EVAX -+#define TC_VALIDATE_FIX_SUB(FIX, SEG) 1 -+ -+#define tc_canonicalize_symbol_name evax_shorten_name -+ -+#define TC_CONS_FIX_NEW(FRAG, OFF, LEN, EXP, RELOC) \ -+ (void) RELOC, fix_new_exp (FRAG, OFF, (int) LEN, EXP, 0, \ -+ LEN == 2 ? BFD_RELOC_16 \ -+ : LEN == 4 ? BFD_RELOC_32 \ -+ : LEN == 8 ? BFD_RELOC_64 \ -+ : BFD_RELOC_SW_64_LINKAGE); -+#endif -+ -+#ifdef OBJ_EVAX -+#define TC_IMPLICIT_LCOMM_ALIGNMENT(SIZE, P2VAR) (P2VAR) = 3 -+#else -+#define TC_IMPLICIT_LCOMM_ALIGNMENT(size, align) \ -+ do \ -+ { \ -+ align = 0; \ -+ if (size > 1) \ -+ { \ -+ addressT temp = 1; \ -+ while ((size & temp) == 0) \ -+ ++align, temp <<= 1; \ -+ } \ -+ } while (0) -+#endif -+ -+#define md_number_to_chars number_to_chars_littleendian -+ -+extern int -+tc_get_register (int); -+extern void -+sw_64_frob_ecoff_data (void); -+ -+#define tc_frob_label(sym) sw_64_define_label (sym) -+extern void -+sw_64_define_label (symbolS *); -+ -+#define md_cons_align(nbytes) sw_64_cons_align (nbytes) -+extern void -+sw_64_cons_align (int); -+ -+#define HANDLE_ALIGN(fragp) sw_64_handle_align (fragp) -+extern void -+sw_64_handle_align (struct frag *); -+ -+#define MAX_MEM_FOR_RS_ALIGN_CODE (3 + 4 + 8) -+ -+#ifdef OBJ_ECOFF -+#define tc_frob_file_before_adjust() sw_64_frob_file_before_adjust () -+extern void -+sw_64_frob_file_before_adjust (void); -+ -+#define TC_VALIDATE_FIX_SUB(FIX, SEG) \ -+ ((md_register_arithmetic || (SEG) != reg_section) \ -+ && ((FIX)->fx_r_type == BFD_RELOC_GPREL32 \ -+ || (FIX)->fx_r_type == BFD_RELOC_GPREL16)) -+#endif -+ -+#define md_after_parse_args() sw_64_after_parse_args () -+extern void -+sw_64_after_parse_args (void); -+ -+#define DIFF_EXPR_OK /* foo-. gets turned into PC relative relocs. */ -+ -+#ifdef OBJ_ELF -+#define md_elf_section_letter sw_64_elf_section_letter -+extern bfd_vma -+sw_64_elf_section_letter (int, const char **); -+#define md_elf_section_flags sw_64_elf_section_flags -+extern flagword -+sw_64_elf_section_flags (flagword, bfd_vma, int); -+#endif -+ -+/* Whether to add support for explicit !relocation_op!sequence_number. At the -+ moment, only do this for ELF, though ECOFF could use it as well. */ -+ -+#ifdef OBJ_ELF -+#define RELOC_OP_P -+#endif -+ -+#ifndef OBJ_EVAX -+/* Before the relocations are written, reorder them, so that user -+ supplied !lituse relocations follow the appropriate !literal -+ relocations. Also convert the gas-internal relocations to the -+ appropriate linker relocations. */ -+#define tc_frob_file_before_fix() sw_64_before_fix () -+extern void -+sw_64_before_fix (void); -+#endif -+ -+#ifdef OBJ_ELF -+#define md_finish sw_64_elf_md_finish -+extern void -+sw_64_elf_md_finish (void); -+#endif -+ -+/* New fields for supporting explicit relocations (such as !literal to mark -+ where a pointer is loaded from the global table, and !lituse_base to track -+ all of the normal uses of that pointer). */ -+ -+#define TC_FIX_TYPE struct sw_64_fix_tag -+ -+struct sw_64_fix_tag -+{ -+ struct fix *next_reloc; /* Next !lituse or !gpdisp. */ -+ struct sw_64_reloc_tag *info; /* Other members with same sequence. */ -+}; -+ -+/* Initialize the TC_FIX_TYPE field. */ -+#define TC_INIT_FIX_DATA(FIX) \ -+ do \ -+ { \ -+ FIX->tc_fix_data.next_reloc = NULL; \ -+ FIX->tc_fix_data.info = NULL; \ -+ } while (0) -+ -+/* Work with DEBUG5 to print fields in tc_fix_type. */ -+#define TC_FIX_DATA_PRINT(STREAM, FIX) \ -+ do \ -+ { \ -+ if (FIX->tc_fix_data.info) \ -+ fprintf (STREAM, "\tinfo = 0x%lx, next_reloc = 0x%lx\n", \ -+ (long) FIX->tc_fix_data.info, \ -+ (long) FIX->tc_fix_data.next_reloc); \ -+ } while (0) -+ -+#define TARGET_USE_CFIPOP 1 -+ -+#define tc_cfi_frame_initial_instructions sw_64_cfi_frame_initial_instructions -+extern void -+sw_64_cfi_frame_initial_instructions (void); -+ -+#define DWARF2_LINE_MIN_INSN_LENGTH 4 -+#define DWARF2_DEFAULT_RETURN_COLUMN 26 -+#define DWARF2_CIE_DATA_ALIGNMENT (-8) -diff --git a/gas/configure b/gas/configure -index 1fc3a54b..5ce68a75 100755 ---- a/gas/configure -+++ b/gas/configure -@@ -12260,6 +12260,44 @@ _ACEOF - ;; - esac - -+ case ${cpu_type} in -+ sw_64 | sw_64sw*) -+ # Set sw_cpu to the name of the default CPU. -+ sw_cpu=$with_cpu -+ cpu_types=${with_cpu:2:4} -+cat >>confdefs.h <<_ACEOF -+#define SW_CPU_STRING_DEFAULT "${with_cpu}" -+_ACEOF -+ -+# Check for git version if there was a github -+git_version=`git log -1 --format="%h"` -+git_short=${git_version:0:5}${cpu_types}"9" -+cat >> confdefs.h <<_ACEOF -+#define GIT_REVISION 0x$git_short -+#define TARGET_SW_64 -+_ACEOF -+ ;; -+ esac -+ case ${cpu_type} in -+ sw_64) -+ # Set sw_cpu to the name of the default CPU. -+ case ${target_cpu} in -+ sw_64sw6a) -+ sw_cpu=sw6a -+ ;; -+ sw_64sw6b) -+ sw_cpu=sw6b -+ ;; -+ sw_64sw8a) -+ sw_cpu=sw8a -+ ;; -+ esac -+ -+cat >>confdefs.h <<_ACEOF -+_ACEOF -+ ;; -+ esac -+ - # Do we need the opcodes library? - case ${cpu_type} in - vax | tic30 | i386 | arm) -diff --git a/gas/configure.tgt b/gas/configure.tgt -index 3429f850..562a938e 100644 ---- a/gas/configure.tgt -+++ b/gas/configure.tgt -@@ -49,6 +49,7 @@ case ${cpu} in - aarch64) cpu_type=aarch64 endian=little arch=aarch64;; - aarch64_be) cpu_type=aarch64 endian=big arch=aarch64;; - alpha*) cpu_type=alpha ;; -+ sw_64*) cpu_type=sw_64 ;; - am33_2.0) cpu_type=mn10300 endian=little ;; - arc*eb) cpu_type=arc endian=big ;; - arm*be|arm*b) cpu_type=arm endian=big ;; -@@ -143,6 +144,12 @@ case ${generic_target} in - alpha-*-linux-*) fmt=elf em=linux ;; - alpha-*-netbsd* | alpha-*-openbsd*) fmt=elf em=nbsd ;; - -+ sw_64-*-osf*) fmt=ecoff ;; -+ sw_64-*-linux*ecoff*) fmt=ecoff ;; -+ sw_64-*-linux-*) fmt=elf em=linux ;; -+ sw_64-*-netbsd*) fmt=elf em=nbsd ;; -+ sw_64-*-openbsd*) fmt=elf em=obsd ;; -+ - arc-*-elf*) fmt=elf ;; - arc*-*-linux*) fmt=elf bfd_gas=yes ;; - -@@ -448,7 +455,8 @@ esac - - case ${cpu_type} in - aarch64 | alpha | arm | csky | i386 | ia64 | microblaze | mips | ns32k | \ -- or1k | or1knd | pdp11 | ppc | riscv | sh | sparc | z80 | z8k | loongarch) -+ or1k | or1knd | pdp11 | ppc | riscv | sh | sparc | z80 | z8k | loongarch | \ -+ sw_64) - bfd_gas=yes - ;; - esac -diff --git a/gas/read.c b/gas/read.c -index 826156db..c0c0cc4c 100644 ---- a/gas/read.c -+++ b/gas/read.c -@@ -2472,7 +2472,7 @@ bss_alloc (symbolS *symbolP, addressT size, unsigned int align) - subsegT current_subseg = now_subseg; - segT bss_seg = bss_section; - --#if defined (TC_MIPS) || defined (TC_ALPHA) -+#if defined (TC_MIPS) || defined (TC_ALPHA) || defined (TC_SW_64) - if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour - || OUTPUT_FLAVOR == bfd_target_elf_flavour) - { -diff --git a/gas/testsuite/gas/all/gas.exp b/gas/testsuite/gas/all/gas.exp -index bab5a6c7..1db165f1 100644 ---- a/gas/testsuite/gas/all/gas.exp -+++ b/gas/testsuite/gas/all/gas.exp -@@ -62,6 +62,7 @@ if { ![istarget cris-*-*] && ![istarget crisv32-*-*] - # differences of two previously undefined symbols. Hence this test will - # not pass for these targets. - if { ![istarget alpha*-*-*vms*] -+ && ![istarget sw_64*-*-*vms*] - && ![istarget am3*-*-*] - && ![istarget avr-*-*] - && ![istarget ft32-*-*] -@@ -126,6 +127,8 @@ if { ![is_aout_format] } { - } - alpha-*-*linux*ecoff { } - alpha-*-osf* { } -+ sw_64-*-*linux*ecoff { } -+ sw_64-*-osf* { } - hppa*-*-hpux* { } - mep-*-* { } - mmix-*-* { } -@@ -145,6 +148,7 @@ if { ![is_aout_format] } { - # pdp11 gets unexpected reloc types. - switch -glob $target_triplet { - alpha*-*-* { } -+ sw_64*-*-* { } - am3*-*-* { } - cr16*-*-* { } - crx*-*-* { } -@@ -364,6 +368,8 @@ proc test_cond {} { - switch -glob $target_triplet { - alpha-*-linux*ecoff { } - alpha-*-osf* { } -+ sw_64-*-linux*ecoff { } -+ sw_64-*-osf* { } - hppa*-*-* { } - *c4x*-*-* { } - *c54x*-*-* { } -@@ -441,6 +447,7 @@ if { ![istarget "pdp11-*-*"] } { - # .set works differently on some targets. - switch -glob $target_triplet { - alpha*-*-* { } -+ sw_64*-*-* { } - mips*-*-* { } - *c54x*-*-* { } - z80-*-* { } -diff --git a/gas/testsuite/gas/elf/common5a.d b/gas/testsuite/gas/elf/common5a.d -index ec136b48..d5aaac4a 100644 ---- a/gas/testsuite/gas/elf/common5a.d -+++ b/gas/testsuite/gas/elf/common5a.d -@@ -1,5 +1,5 @@ - #source: common5a.s - #as: - #error_output: common5a.l --#notarget: alpha-*-* -+#notarget: alpha-*-* sw_64-*-* - # The Alpha target uses its own .set pseudo-insn. -diff --git a/gas/testsuite/gas/elf/common5b.d b/gas/testsuite/gas/elf/common5b.d -index 9369c2df..a0e3a2ff 100644 ---- a/gas/testsuite/gas/elf/common5b.d -+++ b/gas/testsuite/gas/elf/common5b.d -@@ -1,5 +1,5 @@ - #source: common5b.s - #as: - #error_output: common5b.l --#notarget: alpha-*-* -+#notarget: alpha-*-* sw_64-*-* - # The Alpha target uses its own .set pseudo-insn. -diff --git a/gas/testsuite/gas/elf/common5c.d b/gas/testsuite/gas/elf/common5c.d -index cbb3fc68..720f464f 100644 ---- a/gas/testsuite/gas/elf/common5c.d -+++ b/gas/testsuite/gas/elf/common5c.d -@@ -1,5 +1,5 @@ - #source: common5c.s - #as: - #error_output: common5a.l --#notarget: alpha-*-* -+#notarget: alpha-*-* sw_64-*-* - # The Alpha target uses its own .set pseudo-insn. -diff --git a/gas/testsuite/gas/elf/common5d.d b/gas/testsuite/gas/elf/common5d.d -index 7b11fa24..b922fa59 100644 ---- a/gas/testsuite/gas/elf/common5d.d -+++ b/gas/testsuite/gas/elf/common5d.d -@@ -1,5 +1,5 @@ - #source: common5d.s - #as: - #error_output: common5b.l --#notarget: alpha-*-* -+#notarget: alpha-*-* sw_64-*-* - # The Alpha target uses its own .set pseudo-insn. -diff --git a/gas/testsuite/gas/elf/elf.exp b/gas/testsuite/gas/elf/elf.exp -index 9e389ff1..7cd49c0e 100644 ---- a/gas/testsuite/gas/elf/elf.exp -+++ b/gas/testsuite/gas/elf/elf.exp -@@ -167,6 +167,7 @@ if { [is_elf_format] } then { - } - switch -glob $target_triplet { - alpha*-*-* { } -+ sw_64*-*-* { } - am3*-*-* { } - *c54x*-*-* { } - cr16*-*-* { } -@@ -220,7 +221,7 @@ if { [is_elf_format] } then { - run_elf_list_test "section5" "" "-al -Z" "-SW" "| grep \" \\\\.test\\\[0-9\\\]\"" - } - run_dump_test "struct" -- if { ![istarget "alpha*-*-*"] } then { -+ if { ![istarget "alpha*-*-*"] && ! [istarget "sw_64*-*-*"]} then { - # The alpha port uses .set for state, e.g. nomacro. - run_dump_test "symtab" - } -diff --git a/gas/testsuite/gas/elf/ifunc-1.d b/gas/testsuite/gas/elf/ifunc-1.d -index 5b2657b0..f920b977 100644 ---- a/gas/testsuite/gas/elf/ifunc-1.d -+++ b/gas/testsuite/gas/elf/ifunc-1.d -@@ -1,6 +1,6 @@ - #readelf: -s - #name: .set with IFUNC --#notarget: alpha* -+#notarget: alpha* sw_64* - - #... - [ ]+[0-9]+:[ ]+[0-9a-f]+[ ]+[0-9]+[ ]+IFUNC[ ]+GLOBAL[ ]+DEFAULT[ ]+[1-9] __GI_foo -diff --git a/gas/testsuite/gas/elf/size.d b/gas/testsuite/gas/elf/size.d -index 5890386a..edd76de3 100644 ---- a/gas/testsuite/gas/elf/size.d -+++ b/gas/testsuite/gas/elf/size.d -@@ -1,6 +1,6 @@ - #readelf: -sW - #name: ELF symbol size --#notarget: alpha-*-* hppa*-*-hpux* -+#notarget: alpha-*-* sw_64-*-* hppa*-*-hpux* - # The Alpha target uses its own .set pseudo-insn. - - #... -diff --git a/gas/write.c b/gas/write.c -index 573a667d..6ae9856d 100644 ---- a/gas/write.c -+++ b/gas/write.c -@@ -120,6 +120,8 @@ struct reloc_list* reloc_list; - - void print_fixup (fixS *); - -+fixS * frags_pre_fixup = NULL; -+ - /* We generally attach relocs to frag chains. However, after we have - chained these all together into a segment, any relocs we add after - that must be attached to a segment. This will include relocs added -@@ -199,14 +201,21 @@ fix_new_internal (fragS *frag, /* Which frag? */ - *seg_fix_rootP = fixP; - if (fixP->fx_next == NULL) - *seg_fix_tailP = fixP; -+ frags_pre_fixup = NULL; - } - else - { - fixP->fx_next = NULL; - if (*seg_fix_tailP) -+ { -+ frags_pre_fixup = *seg_fix_tailP; - (*seg_fix_tailP)->fx_next = fixP; -+ } - else -+ { -+ frags_pre_fixup = NULL; - *seg_fix_rootP = fixP; -+ } - *seg_fix_tailP = fixP; - } - } -@@ -550,6 +559,56 @@ relax_seg (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, void *xxx) - info->changed = 1; - } - -+#ifdef TARGET_SW_64 -+static void -+sort_frchain (frag_list) -+fragS *frag_list; -+{ -+ fragS *fragp, *fragc, *fragi; -+ long r; -+ for (fragp = frag_list;fragp;) -+ { -+ fragc=fragp; -+ if (fragp->fr_next) -+ fragp = fragp->fr_next; -+ else -+ /* the end of the frag_list. */ -+ break; -+ r = ((long)fragp->fr_address - (long)fragc->fr_address - fragc->fr_fix) ; -+ if ( r < 0) -+ { -+ /*adjust the last fill frag's address ,but don't insert back. */ -+ if (fragp->fr_type == rs_fill && fragp->fr_next == 0) -+ { -+ fragp->fr_address=fragp->last_fr_address=fragc->fr_address -+ + fragc->fr_fix+fragc->fr_offset; -+ continue; -+ } -+ -+ fragc->fr_next = fragp->fr_next; -+ for (fragi = frag_list; fragi != fragc; fragi=fragi->fr_next) -+ { -+ r = (fragi->fr_next->fr_address -+ - fragp->fr_address - fragp->fr_fix) ; -+ if (r >= 0) -+ { -+ fragp->fr_next = fragi->fr_next; -+ fragi->fr_next = fragp; -+ fragp = fragc; -+ break; -+ } -+ } -+ if (fragi == fragc) -+ { -+ as_bad_where (fragp->fr_file, -+ fragp->fr_line, -+ "ERR,can't insert the node!\n"); -+ } -+ } -+ } -+} -+#endif -+ - static void - size_seg (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, void *xxx ATTRIBUTE_UNUSED) - { -@@ -562,6 +621,10 @@ size_seg (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, void *xxx ATTRIBUTE_UNUSED) - subseg_change (sec, 0); - - seginfo = seg_info (sec); -+#ifdef TARGET_SW_64 -+ if (pal_org_backwrards) -+ sort_frchain (seginfo->frchainP->frch_root); -+#endif - if (seginfo && seginfo->frchainP) - { - for (fragp = seginfo->frchainP->frch_root; fragp; fragp = fragp->fr_next) -@@ -3018,7 +3081,13 @@ relax_segment (struct frag *segment_frag_root, segT segment, int pass) - /* Growth may be negative, but variable part of frag - cannot have fewer than 0 chars. That is, we can't - .org backwards. */ -+ -+#ifdef TARGET_SW_64 -+ if (((offsetT) (address + fragP->fr_fix) > target) && -+ !pal_org_backwrards) -+#else - if ((offsetT) (address + fragP->fr_fix) > target) -+#endif - { - growth = 0; - -diff --git a/gprof/sw_64.c b/gprof/sw_64.c -new file mode 100644 -index 00000000..5bf726ca ---- /dev/null -+++ b/gprof/sw_64.c -@@ -0,0 +1,171 @@ -+/* -+ * Copyright (c) 1983, 1993, 1998 -+ * The Regents of the University of California. All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. Neither the name of the University nor the names of its contributors -+ * may be used to endorse or promote products derived from this software -+ * without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ */ -+#include "gprof.h" -+#include "search_list.h" -+#include "source.h" -+#include "symtab.h" -+#include "cg_arcs.h" -+#include "corefile.h" -+#include "hist.h" -+ -+/* -+ * Opcodes of the call instructions: -+ */ -+#define OP_Jxx 0x1aU -+#define OP_BSR 0x34U -+ -+#define Jxx_FUNC_JMP 0U -+#define Jxx_FUNC_JSR 1U -+#define Jxx_FUNC_RET 2U -+#define Jxx_FUNC_JSR_COROUTINE 3U -+ -+/* *INDENT-OFF* */ -+/* Here to document only. We can't use this when cross compiling as -+ the bitfield layout might not be the same as native. -+ -+ typedef union -+ { -+ struct -+ { -+ unsigned other:26; -+ unsigned op_code:6; -+ } -+ a; -- any format -+ struct -+ { -+ int disp:21; -+ unsigned ra:5; -+ unsigned op_code:6; -+ } -+ b; -- branch format -+ struct -+ { -+ int hint:14; -+ unsigned func:2; -+ unsigned rb:5; -+ unsigned ra:5; -+ unsigned op_code:6; -+ } -+ j; -- jump format -+ } -+ sw_64_Instruction; -+*/ -+/* *INDENT-ON* */ -+ -+static Sym indirect_child; -+ -+void -+sw_64_find_call (Sym *, bfd_vma, bfd_vma); -+ -+/* -+ * On the SW_64 we can only detect PC relative calls, which are -+ * usually generated for calls to functions within the same -+ * object file only. This is still better than nothing, however. -+ * (In particular it should be possible to find functions that -+ * potentially call integer division routines, for example.) -+ */ -+void -+sw_64_find_call (Sym *parent, bfd_vma p_lowpc, bfd_vma p_highpc) -+{ -+ bfd_vma pc, dest_pc; -+ unsigned int insn; -+ Sym *child; -+ -+ if (indirect_child.name == NULL) -+ { -+ sym_init (&indirect_child); -+ indirect_child.name = _ (""); -+ indirect_child.cg.prop.fract = 1.0; -+ indirect_child.cg.cyc.head = &indirect_child; -+ } -+ -+ DBG (CALLDEBUG, printf (_ ("[find_call] %s: 0x%lx to 0x%lx\n"), parent->name, -+ (unsigned long) p_lowpc, (unsigned long) p_highpc)); -+ for (pc = (p_lowpc + 3) & ~(bfd_vma) 3; pc < p_highpc; pc += 4) -+ { -+ insn = bfd_get_32 (core_bfd, ((unsigned char *) core_text_space + pc -+ - core_text_sect->vma)); -+ switch (insn & (0x3fU << 26)) -+ { -+ case OP_Jxx << 26: -+ /* There is no simple and reliable way to determine the -+ * target of a jsr (the hint bits help, but there aren't -+ * enough bits to get a satisfactory hit rate). Instead, -+ * for any indirect jump we simply add an arc from PARENT -+ * to INDIRECT_CHILD---that way the user it at least able -+ * to see that there are other calls as well. */ -+ if ((insn & (3 << 14)) == Jxx_FUNC_JSR << 14 -+ || (insn & (3 << 14)) == Jxx_FUNC_JSR_COROUTINE << 14) -+ { -+ DBG (CALLDEBUG, -+ printf (_ ("[find_call] 0x%lx: jsr%s \n"), -+ (unsigned long) pc, -+ ((insn & (3 << 14)) == Jxx_FUNC_JSR << 14 -+ ? "" -+ : "_coroutine"))); -+ arc_add (parent, &indirect_child, (unsigned long) 0); -+ } -+ break; -+ -+ case OP_BSR << 26: -+ DBG (CALLDEBUG, -+ printf (_ ("[find_call] 0x%lx: bsr"), (unsigned long) pc)); -+ /* Regular PC relative addressing. Check that this is the -+ * address of a function. The linker sometimes redirects -+ * the entry point by 8 bytes to skip loading the global -+ * pointer, so we allow for either address. */ -+ dest_pc -+ = pc + 4 -+ + (((bfd_signed_vma) (insn & 0x1fffff) ^ 0x100000) - 0x100000); -+ if (hist_check_address (dest_pc)) -+ { -+ child = sym_lookup (&symtab, dest_pc); -+ if (child) -+ { -+ DBG (CALLDEBUG, printf (" 0x%lx\t; name=%s, addr=0x%lx", -+ (unsigned long) dest_pc, child->name, -+ (unsigned long) child->addr)); -+ if (child->addr == dest_pc || child->addr == dest_pc - 8) -+ { -+ DBG (CALLDEBUG, printf ("\n")); -+ /* a hit: */ -+ arc_add (parent, child, (unsigned long) 0); -+ continue; -+ } -+ } -+ } -+ /* Something funny going on. */ -+ DBG (CALLDEBUG, printf ("\tbut it's a botch\n")); -+ break; -+ -+ default: -+ break; -+ } -+ } -+} -diff --git a/include/bfdlink.h b/include/bfdlink.h -index 840790a2..b40de75a 100644 ---- a/include/bfdlink.h -+++ b/include/bfdlink.h -@@ -733,6 +733,7 @@ struct bfd_link_info - /* The maximum cache size. Backend can use cache_size and and - max_cache_size to decide if keep_memory should be honored. */ - bfd_size_type max_cache_size; -+ long flag_sw_lbr; - }; - - /* Some forward-definitions used by some callbacks. */ -diff --git a/include/coff/ecoff.h b/include/coff/ecoff.h -index 991d92f9..488db08c 100644 ---- a/include/coff/ecoff.h -+++ b/include/coff/ecoff.h -@@ -47,6 +47,14 @@ - /* A compressed version of an ALPHA_MAGIC file created by DEC's tools. */ - #define ALPHA_MAGIC_COMPRESSED 0x188 - -+#ifdef TARGET_SW_64 -+/* Sw_64 magic numbers used in filehdr. */ -+#define SW_64_MAGIC 0x184 -+#define SW_64_MAGIC_BSD 0x187 -+/* A compressed version of an SW_64_MAGIC file created by DEC's tools. */ -+#define SW_64_MAGIC_COMPRESSED 0x189 -+#endif -+ - /* Magic numbers used in a.out header. */ - #define ECOFF_AOUT_OMAGIC 0407 /* not demand paged (ld -N). */ - #define ECOFF_AOUT_ZMAGIC 0413 /* demand load format, eg normal ld output */ -diff --git a/include/coff/pe.h b/include/coff/pe.h -index 6b26d533..79e349a5 100644 ---- a/include/coff/pe.h -+++ b/include/coff/pe.h -@@ -134,6 +134,10 @@ - #define IMAGE_FILE_MACHINE_UNKNOWN 0x0000 - #define IMAGE_FILE_MACHINE_ALPHA 0x0184 - #define IMAGE_FILE_MACHINE_ALPHA64 0x0284 -+#ifdef TARGET_SW_64 -+#define IMAGE_FILE_MACHINE_SW_64 0x0184 -+#define IMAGE_FILE_MACHINE_SW_6464 0x0284 -+#endif - #define IMAGE_FILE_MACHINE_AM33 0x01d3 - #define IMAGE_FILE_MACHINE_AMD64 0x8664 - #define IMAGE_FILE_MACHINE_ARM 0x01c0 -diff --git a/include/coff/sw_64.h b/include/coff/sw_64.h -new file mode 100644 -index 00000000..3476e45b ---- /dev/null -+++ b/include/coff/sw_64.h -@@ -0,0 +1,391 @@ -+/* ECOFF support on Sw_64 machines. -+ coff/ecoff.h must be included before this file. -+ -+ Copyright (C) 2001-2023 Free Software Foundation, Inc. -+ -+ This program is free software; you can redistribute it and/or modify -+ it under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 3 of the License, or -+ (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ GNU General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, -+ MA 02110-1301, USA. */ -+ -+/********************** FILE HEADER **********************/ -+ -+struct external_filehdr -+{ -+ unsigned char f_magic[2]; /* magic number */ -+ unsigned char f_nscns[2]; /* number of sections */ -+ unsigned char f_timdat[4]; /* time & date stamp */ -+ unsigned char f_symptr[8]; /* file pointer to symtab */ -+ unsigned char f_nsyms[4]; /* number of symtab entries */ -+ unsigned char f_opthdr[2]; /* sizeof (optional hdr) */ -+ unsigned char f_flags[2]; /* flags */ -+}; -+ -+/* Magic numbers are defined in coff/ecoff.h. */ -+#define SW_64_ECOFF_BADMAG(x) \ -+ ((x).f_magic != SW_64_MAGIC && (x).f_magic != SW_64_MAGIC_BSD) -+ -+#define SW_64_ECOFF_COMPRESSEDMAG(x) ((x).f_magic == SW_64_MAGIC_COMPRESSED) -+ -+/* The object type is encoded in the f_flags. */ -+#define F_SW_64_OBJECT_TYPE_MASK 0x3000 -+#define F_SW_64_NO_SHARED 0x1000 -+#define F_SW_64_SHARABLE 0x2000 -+#define F_SW_64_CALL_SHARED 0x3000 -+ -+#define FILHDR struct external_filehdr -+#define FILHSZ 24 -+ -+/********************** AOUT "OPTIONAL HEADER" **********************/ -+ -+typedef struct external_aouthdr -+{ -+ unsigned char magic[2]; /* type of file. */ -+ unsigned char vstamp[2]; /* version stamp. */ -+ unsigned char bldrev[2]; /* ?? */ -+ unsigned char padding[2]; /* pad to quadword boundary. */ -+ unsigned char tsize[8]; /* text size in bytes. */ -+ unsigned char dsize[8]; /* initialized data " " */ -+ unsigned char bsize[8]; /* uninitialized data " "*/ -+ unsigned char entry[8]; /* entry pt. */ -+ unsigned char text_start[8]; /* base of text used for this file. */ -+ unsigned char data_start[8]; /* base of data used for this file. */ -+ unsigned char bss_start[8]; /* base of bss used for this file. */ -+ unsigned char gprmask[4]; /* bitmask of general registers used. */ -+ unsigned char fprmask[4]; /* bitmask of floating point registers used. */ -+ unsigned char gp_value[8]; /* value for gp register. */ -+} AOUTHDR; -+ -+/* compute size of a header */ -+ -+#define AOUTSZ 80 -+#define AOUTHDRSZ 80 -+ -+/********************** SECTION HEADER **********************/ -+ -+struct external_scnhdr -+{ -+ unsigned char s_name[8]; /* section name */ -+ unsigned char s_paddr[8]; /* physical address, aliased s_nlib */ -+ unsigned char s_vaddr[8]; /* virtual address */ -+ unsigned char s_size[8]; /* section size */ -+ unsigned char s_scnptr[8]; /* file ptr to raw data for section */ -+ unsigned char s_relptr[8]; /* file ptr to relocation */ -+ unsigned char s_lnnoptr[8]; /* file ptr to line numbers */ -+ unsigned char s_nreloc[2]; /* number of relocation entries */ -+ unsigned char s_nlnno[2]; /* number of line number entries*/ -+ unsigned char s_flags[4]; /* flags */ -+}; -+ -+#define SCNHDR struct external_scnhdr -+#define SCNHSZ 64 -+ -+/********************** RELOCATION DIRECTIVES **********************/ -+ -+struct external_reloc -+{ -+ unsigned char r_vaddr[8]; -+ unsigned char r_symndx[4]; -+ unsigned char r_bits[4]; -+}; -+ -+#define RELOC struct external_reloc -+#define RELSZ 16 -+ -+/* Constants to unpack the r_bits field. The Sw_64 seems to always be -+ little endian, so I haven't bothered to define big endian variants -+ of these. */ -+ -+#define RELOC_BITS0_TYPE_LITTLE 0xff -+#define RELOC_BITS0_TYPE_SH_LITTLE 0 -+ -+#define RELOC_BITS1_EXTERN_LITTLE 0x01 -+ -+#define RELOC_BITS1_OFFSET_LITTLE 0x7e -+#define RELOC_BITS1_OFFSET_SH_LITTLE 1 -+ -+#define RELOC_BITS1_RESERVED_LITTLE 0x80 -+#define RELOC_BITS1_RESERVED_SH_LITTLE 7 -+#define RELOC_BITS2_RESERVED_LITTLE 0xff -+#define RELOC_BITS2_RESERVED_SH_LEFT_LITTLE 1 -+#define RELOC_BITS3_RESERVED_LITTLE 0x03 -+#define RELOC_BITS3_RESERVED_SH_LEFT_LITTLE 9 -+ -+#define RELOC_BITS3_SIZE_LITTLE 0xfc -+#define RELOC_BITS3_SIZE_SH_LITTLE 2 -+ -+/* The r_type field in a reloc is one of the following values. */ -+#define SW_64_R_IGNORE 0 -+#define SW_64_R_REFLONG 1 -+#define SW_64_R_REFQUAD 2 -+#define SW_64_R_GPREL32 3 -+#define SW_64_R_LITERAL 4 -+#define SW_64_R_LITUSE 5 -+#define SW_64_R_GPDISP 6 -+#define SW_64_R_BRADDR 7 -+#define SW_64_R_HINT 8 -+#define SW_64_R_SREL16 9 -+#define SW_64_R_SREL32 10 -+#define SW_64_R_SREL64 11 -+#define SW_64_R_OP_PUSH 12 -+#define SW_64_R_OP_STORE 13 -+#define SW_64_R_OP_PSUB 14 -+#define SW_64_R_OP_PRSHIFT 15 -+#define SW_64_R_GPVALUE 16 -+#define SW_64_R_GPRELHIGH 17 -+#define SW_64_R_GPRELLOW 18 -+#define SW_64_R_IMMED 19 -+#define SW_64_R_BR26ADDR 20 -+ -+/* Overloaded reloc value used by Net- and OpenBSD. */ -+#define SW_64_R_LITERALSLEAZY 17 -+ -+/* With SW_64_R_LITUSE, the r_size field is one of the following values. */ -+#define SW_64_R_LU_BASE 1 -+#define SW_64_R_LU_BYTOFF 2 -+#define SW_64_R_LU_JSR 3 -+ -+/* With SW_64_R_IMMED, the r_size field is one of the following values. */ -+#define SW_64_R_IMMED_GP_16 1 -+#define SW_64_R_IMMED_GP_HI32 2 -+#define SW_64_R_IMMED_SCN_HI32 3 -+#define SW_64_R_IMMED_BR_HI32 4 -+#define SW_64_R_IMMED_LO32 5 -+ -+/********************** SYMBOLIC INFORMATION **********************/ -+ -+/* ECOFF uses COFF-like section structures, but its own symbol format. -+ This file defines the symbol format in fields whose size and alignment -+ will not vary on different host systems. */ -+ -+/* File header as a set of bytes. */ -+ -+struct hdr_ext -+{ -+ unsigned char h_magic[2]; -+ unsigned char h_vstamp[2]; -+ unsigned char h_ilineMax[4]; -+ unsigned char h_idnMax[4]; -+ unsigned char h_ipdMax[4]; -+ unsigned char h_isymMax[4]; -+ unsigned char h_ioptMax[4]; -+ unsigned char h_iauxMax[4]; -+ unsigned char h_issMax[4]; -+ unsigned char h_issExtMax[4]; -+ unsigned char h_ifdMax[4]; -+ unsigned char h_crfd[4]; -+ unsigned char h_iextMax[4]; -+ unsigned char h_cbLine[8]; -+ unsigned char h_cbLineOffset[8]; -+ unsigned char h_cbDnOffset[8]; -+ unsigned char h_cbPdOffset[8]; -+ unsigned char h_cbSymOffset[8]; -+ unsigned char h_cbOptOffset[8]; -+ unsigned char h_cbAuxOffset[8]; -+ unsigned char h_cbSsOffset[8]; -+ unsigned char h_cbSsExtOffset[8]; -+ unsigned char h_cbFdOffset[8]; -+ unsigned char h_cbRfdOffset[8]; -+ unsigned char h_cbExtOffset[8]; -+}; -+ -+/* File descriptor external record. */ -+ -+struct fdr_ext -+{ -+ unsigned char f_adr[8]; -+ unsigned char f_cbLineOffset[8]; -+ unsigned char f_cbLine[8]; -+ unsigned char f_cbSs[8]; -+ unsigned char f_rss[4]; -+ unsigned char f_issBase[4]; -+ unsigned char f_isymBase[4]; -+ unsigned char f_csym[4]; -+ unsigned char f_ilineBase[4]; -+ unsigned char f_cline[4]; -+ unsigned char f_ioptBase[4]; -+ unsigned char f_copt[4]; -+ unsigned char f_ipdFirst[4]; -+ unsigned char f_cpd[4]; -+ unsigned char f_iauxBase[4]; -+ unsigned char f_caux[4]; -+ unsigned char f_rfdBase[4]; -+ unsigned char f_crfd[4]; -+ unsigned char f_bits1[1]; -+ unsigned char f_bits2[3]; -+ unsigned char f_padding[4]; -+}; -+ -+#define FDR_BITS1_LANG_BIG 0xF8 -+#define FDR_BITS1_LANG_SH_BIG 3 -+#define FDR_BITS1_LANG_LITTLE 0x1F -+#define FDR_BITS1_LANG_SH_LITTLE 0 -+ -+#define FDR_BITS1_FMERGE_BIG 0x04 -+#define FDR_BITS1_FMERGE_LITTLE 0x20 -+ -+#define FDR_BITS1_FREADIN_BIG 0x02 -+#define FDR_BITS1_FREADIN_LITTLE 0x40 -+ -+#define FDR_BITS1_FBIGENDIAN_BIG 0x01 -+#define FDR_BITS1_FBIGENDIAN_LITTLE 0x80 -+ -+#define FDR_BITS2_GLEVEL_BIG 0xC0 -+#define FDR_BITS2_GLEVEL_SH_BIG 6 -+#define FDR_BITS2_GLEVEL_LITTLE 0x03 -+#define FDR_BITS2_GLEVEL_SH_LITTLE 0 -+ -+/* We ignore the `reserved' field in bits2. */ -+ -+/* Procedure descriptor external record. */ -+ -+struct pdr_ext -+{ -+ unsigned char p_adr[8]; -+ unsigned char p_cbLineOffset[8]; -+ unsigned char p_isym[4]; -+ unsigned char p_iline[4]; -+ unsigned char p_regmask[4]; -+ unsigned char p_regoffset[4]; -+ unsigned char p_iopt[4]; -+ unsigned char p_fregmask[4]; -+ unsigned char p_fregoffset[4]; -+ unsigned char p_frameoffset[4]; -+ unsigned char p_lnLow[4]; -+ unsigned char p_lnHigh[4]; -+ unsigned char p_gp_prologue[1]; -+ unsigned char p_bits1[1]; -+ unsigned char p_bits2[1]; -+ unsigned char p_localoff[1]; -+ unsigned char p_framereg[2]; -+ unsigned char p_pcreg[2]; -+}; -+ -+#define PDR_BITS1_GP_USED_BIG 0x80 -+#define PDR_BITS1_REG_FRAME_BIG 0x40 -+#define PDR_BITS1_PROF_BIG 0x20 -+#define PDR_BITS1_RESERVED_BIG 0x1f -+#define PDR_BITS1_RESERVED_SH_LEFT_BIG 8 -+#define PDR_BITS2_RESERVED_BIG 0xff -+#define PDR_BITS2_RESERVED_SH_BIG 0 -+ -+#define PDR_BITS1_GP_USED_LITTLE 0x01 -+#define PDR_BITS1_REG_FRAME_LITTLE 0x02 -+#define PDR_BITS1_PROF_LITTLE 0x04 -+#define PDR_BITS1_RESERVED_LITTLE 0xf8 -+#define PDR_BITS1_RESERVED_SH_LITTLE 3 -+#define PDR_BITS2_RESERVED_LITTLE 0xff -+#define PDR_BITS2_RESERVED_SH_LEFT_LITTLE 5 -+ -+/* Line numbers. */ -+ -+struct line_ext -+{ -+ unsigned char l_line[4]; -+}; -+ -+/* Symbol external record. */ -+ -+struct sym_ext -+{ -+ unsigned char s_value[8]; -+ unsigned char s_iss[4]; -+ unsigned char s_bits1[1]; -+ unsigned char s_bits2[1]; -+ unsigned char s_bits3[1]; -+ unsigned char s_bits4[1]; -+}; -+ -+#define SYM_BITS1_ST_BIG 0xFC -+#define SYM_BITS1_ST_SH_BIG 2 -+#define SYM_BITS1_ST_LITTLE 0x3F -+#define SYM_BITS1_ST_SH_LITTLE 0 -+ -+#define SYM_BITS1_SC_BIG 0x03 -+#define SYM_BITS1_SC_SH_LEFT_BIG 3 -+#define SYM_BITS1_SC_LITTLE 0xC0 -+#define SYM_BITS1_SC_SH_LITTLE 6 -+ -+#define SYM_BITS2_SC_BIG 0xE0 -+#define SYM_BITS2_SC_SH_BIG 5 -+#define SYM_BITS2_SC_LITTLE 0x07 -+#define SYM_BITS2_SC_SH_LEFT_LITTLE 2 -+ -+#define SYM_BITS2_RESERVED_BIG 0x10 -+#define SYM_BITS2_RESERVED_LITTLE 0x08 -+ -+#define SYM_BITS2_INDEX_BIG 0x0F -+#define SYM_BITS2_INDEX_SH_LEFT_BIG 16 -+#define SYM_BITS2_INDEX_LITTLE 0xF0 -+#define SYM_BITS2_INDEX_SH_LITTLE 4 -+ -+#define SYM_BITS3_INDEX_SH_LEFT_BIG 8 -+#define SYM_BITS3_INDEX_SH_LEFT_LITTLE 4 -+ -+#define SYM_BITS4_INDEX_SH_LEFT_BIG 0 -+#define SYM_BITS4_INDEX_SH_LEFT_LITTLE 12 -+ -+/* External symbol external record. */ -+ -+struct ext_ext -+{ -+ struct sym_ext es_asym; -+ unsigned char es_bits1[1]; -+ unsigned char es_bits2[3]; -+ unsigned char es_ifd[4]; -+}; -+ -+#define EXT_BITS1_JMPTBL_BIG 0x80 -+#define EXT_BITS1_JMPTBL_LITTLE 0x01 -+ -+#define EXT_BITS1_COBOL_MAIN_BIG 0x40 -+#define EXT_BITS1_COBOL_MAIN_LITTLE 0x02 -+ -+#define EXT_BITS1_WEAKEXT_BIG 0x20 -+#define EXT_BITS1_WEAKEXT_LITTLE 0x04 -+ -+/* Dense numbers external record. */ -+ -+struct dnr_ext -+{ -+ unsigned char d_rfd[4]; -+ unsigned char d_index[4]; -+}; -+ -+/* Relative file descriptor. */ -+ -+struct rfd_ext -+{ -+ unsigned char rfd[4]; -+}; -+ -+/* Optimizer symbol external record. */ -+ -+struct opt_ext -+{ -+ unsigned char o_bits1[1]; -+ unsigned char o_bits2[1]; -+ unsigned char o_bits3[1]; -+ unsigned char o_bits4[1]; -+ struct rndx_ext o_rndx; -+ unsigned char o_offset[4]; -+}; -+ -+#define OPT_BITS2_VALUE_SH_LEFT_BIG 16 -+#define OPT_BITS2_VALUE_SH_LEFT_LITTLE 0 -+ -+#define OPT_BITS3_VALUE_SH_LEFT_BIG 8 -+#define OPT_BITS3_VALUE_SH_LEFT_LITTLE 8 -+ -+#define OPT_BITS4_VALUE_SH_LEFT_BIG 0 -+#define OPT_BITS4_VALUE_SH_LEFT_LITTLE 16 -diff --git a/include/elf/common.h b/include/elf/common.h -index ffa6b60b..417bcb0a 100644 ---- a/include/elf/common.h -+++ b/include/elf/common.h -@@ -415,6 +415,9 @@ - /* Alpha backend magic number. Written in the absence of an ABI. */ - #define EM_ALPHA 0x9026 - -+/* Sw_64 backend magic number. Written in the absence of an ABI. */ -+#define EM_SW_64 0x9916 -+ - /* Cygnus M32R ELF backend. Written in the absence of an ABI. */ - #define EM_CYGNUS_M32R 0x9041 - -diff --git a/include/elf/sw_64.h b/include/elf/sw_64.h -new file mode 100644 -index 00000000..26fff944 ---- /dev/null -+++ b/include/elf/sw_64.h -@@ -0,0 +1,138 @@ -+/* SW_64 ELF support for BFD. -+ Copyright (C) 1996-2023 Free Software Foundation, Inc. -+ -+ By Eric Youngdale, . No processor supplement available -+ for this platform. -+ -+ This file is part of BFD, the Binary File Descriptor library. -+ -+ This program is free software; you can redistribute it and/or modify -+ it under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 3 of the License, or -+ (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ GNU General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, -+ MA 02110-1301, USA. */ -+ -+/* This file holds definitions specific to the SW_64 ELF ABI. Note -+ that most of this is not actually implemented by BFD. */ -+ -+#ifndef _ELF_SW_64_H -+#define _ELF_SW_64_H -+ -+/* Processor specific flags for the ELF header e_flags field. */ -+ -+/* All addresses must be below 2GB. */ -+#define EF_SW_64_32BIT 0x00000001 -+ -+/* All relocations needed for relaxation with code movement are present. */ -+#define EF_SW_64_CANRELAX 0x00000002 -+ -+/* Processor specific section flags. */ -+ -+/* This section must be in the global data area. */ -+#define SHF_SW_64_GPREL 0x10000000 -+ -+/* Section contains some sort of debugging information. The exact -+ format is unspecified. It's probably ECOFF symbols. */ -+#define SHT_SW_64_DEBUG 0x70000001 -+ -+/* Section contains register usage information. */ -+#define SHT_SW_64_REGINFO 0x70000002 -+ -+/* Special values for the st_other field in the symbol table. */ -+ -+#define STO_SW_64_NOPV 0x80 -+#define STO_SW_64_STD_GPLOAD 0x88 -+ -+/* Special values for Elf64_Dyn tag. */ -+#define DT_SW_64_PLTRO DT_LOPROC -+ -+#include "elf/reloc-macros.h" -+ -+unsigned long -+bfd_elf_sw_64_mach (flagword flags); -+ -+enum -+{ -+ E_SW_64_MACH_SW6A = 4, -+ E_SW_64_MACH_SW6B = 8, -+ E_SW_64_MACH_SW8A = 12, -+}; -+ -+#define EF_SW_64_MACH ~(0x3) -+ -+#define E_SW_64_MACH_SW6A 4 -+#define E_SW_64_MACH_SW6B 8 -+#define E_SW_64_MACH_SW8A 12 -+ -+/* Sw_64 relocs. */ -+START_RELOC_NUMBERS (elf_sw_64_reloc_type) -+RELOC_NUMBER (R_SW_64_NONE, 0) /* No reloc */ -+RELOC_NUMBER (R_SW_64_REFLONG, 1) /* Direct 32 bit */ -+RELOC_NUMBER (R_SW_64_REFQUAD, 2) /* Direct 64 bit */ -+RELOC_NUMBER (R_SW_64_GPREL32, 3) /* GP relative 32 bit */ -+RELOC_NUMBER (R_SW_64_LITERAL, 4) /* GP relative 16 bit w/optimization */ -+RELOC_NUMBER (R_SW_64_LITUSE, 5) /* Optimization hint for LITERAL */ -+RELOC_NUMBER (R_SW_64_GPDISP, 6) /* Add displacement to GP */ -+RELOC_NUMBER (R_SW_64_BRADDR, 7) /* PC+4 relative 23 bit shifted */ -+RELOC_NUMBER (R_SW_64_HINT, 8) /* PC+4 relative 16 bit shifted */ -+RELOC_NUMBER (R_SW_64_SREL16, 9) /* PC relative 16 bit */ -+RELOC_NUMBER (R_SW_64_SREL32, 10) /* PC relative 32 bit */ -+RELOC_NUMBER (R_SW_64_SREL64, 11) /* PC relative 64 bit */ -+ -+/* Skip 12 - 16; deprecated ECOFF relocs. */ -+ -+RELOC_NUMBER (R_SW_64_GPRELHIGH, 17) /* GP relative 32 bit, high 16 bits */ -+RELOC_NUMBER (R_SW_64_GPRELLOW, 18) /* GP relative 32 bit, low 16 bits */ -+RELOC_NUMBER (R_SW_64_GPREL16, 19) /* GP relative 16 bit */ -+ -+/* Skip 20 - 23; deprecated ECOFF relocs. */ -+ -+/* These relocations are specific to shared libraries. */ -+RELOC_NUMBER (R_SW_64_COPY, 24) /* Copy symbol at runtime */ -+RELOC_NUMBER (R_SW_64_GLOB_DAT, 25) /* Create GOT entry */ -+RELOC_NUMBER (R_SW_64_JMP_SLOT, 26) /* Create PLT entry */ -+RELOC_NUMBER (R_SW_64_RELATIVE, 27) /* Adjust by program base */ -+ -+/* Like BRADDR, but assert that the source and target object file -+ share the same GP value, and adjust the target address for -+ STO_SW_64_STD_GPLOAD. */ -+RELOC_NUMBER (R_SW_64_BRSGP, 28) -+ -+/* Thread-Local Storage. */ -+RELOC_NUMBER (R_SW_64_TLSGD, 29) -+RELOC_NUMBER (R_SW_64_TLSLDM, 30) -+RELOC_NUMBER (R_SW_64_DTPMOD64, 31) -+RELOC_NUMBER (R_SW_64_GOTDTPREL, 32) -+RELOC_NUMBER (R_SW_64_DTPREL64, 33) -+RELOC_NUMBER (R_SW_64_DTPRELHI, 34) -+RELOC_NUMBER (R_SW_64_DTPRELLO, 35) -+RELOC_NUMBER (R_SW_64_DTPREL16, 36) -+RELOC_NUMBER (R_SW_64_GOTTPREL, 37) -+RELOC_NUMBER (R_SW_64_TPREL64, 38) -+RELOC_NUMBER (R_SW_64_TPRELHI, 39) -+RELOC_NUMBER (R_SW_64_TPRELLO, 40) -+RELOC_NUMBER (R_SW_64_TPREL16, 41) -+RELOC_NUMBER (R_SW_64_BR26ADDR, 42) -+RELOC_NUMBER (R_SW_64_LITERAL_GOT, 43) /* GP relative 16 bit */ -+RELOC_NUMBER (R_SW_64_TLSREL_GOT, 44) /* GP relative 16 bit */ -+ -+END_RELOC_NUMBERS (R_SW_64_max) -+ -+#define LITUSE_SW_64_ADDR 0 -+#define LITUSE_SW_64_BASE 1 -+#define LITUSE_SW_64_BYTOFF 2 -+#define LITUSE_SW_64_JSR 3 -+#define LITUSE_SW_64_TLSGD 4 -+#define LITUSE_SW_64_TLSLDM 5 -+#define LITUSE_SW_64_JSRDIRECT 6 -+ -+#endif /* _ELF_SW_64_H */ -diff --git a/include/longlong.h b/include/longlong.h -index 9948a587..eaaac3f3 100644 ---- a/include/longlong.h -+++ b/include/longlong.h -@@ -191,6 +191,67 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype); - #endif /* __alpha_cix__ */ - #endif /* __alpha */ - -+//__sw_64_cix__ -+#if defined(__sw_64) && W_TYPE_SIZE == 64 -+/* There is a bug in g++ before version 5 that -+ errors on __builtin_sw_64_umulh. */ -+#if !defined(__cplusplus) || __GNUC__ >= 5 -+#define umul_ppmm(ph, pl, m0, m1) \ -+ do \ -+ { \ -+ UDItype __m0 = (m0), __m1 = (m1); \ -+ (ph) = __builtin_sw_64_umulh (__m0, __m1); \ -+ (pl) = __m0 * __m1; \ -+ } while (0) -+#define UMUL_TIME 46 -+#endif /* !c++ */ -+#ifndef LONGLONG_STANDALONE -+#define udiv_qrnnd(q, r, n1, n0, d) \ -+ do \ -+ { \ -+ UDItype __r; \ -+ (q) = __udiv_qrnnd (&__r, (n1), (n0), (d)); \ -+ (r) = __r; \ -+ } while (0) -+extern UDItype -+__udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype); -+#define UDIV_TIME 220 -+#endif /* LONGLONG_STANDALONE */ -+#ifdef __sw_64_cix__ -+#define count_leading_zeros(COUNT, X) ((COUNT) = __builtin_clzl (X)) -+#define count_trailing_zeros(COUNT, X) ((COUNT) = __builtin_ctzl (X)) -+#define COUNT_LEADING_ZEROS_0 64 -+#else -+#define count_leading_zeros(COUNT, X) \ -+ do \ -+ { \ -+ UDItype __xr = (X), __t, __a; \ -+ __t = __builtin_sw_64_cmpbge (0, __xr); \ -+ __a = __clz_tab[__t ^ 0xff] - 1; \ -+ __t = __builtin_sw_64_extbl (__xr, __a); \ -+ (COUNT) = 64 - (__clz_tab[__t] + __a * 8); \ -+ } while (0) -+#define count_trailing_zeros(COUNT, X) \ -+ do \ -+ { \ -+ UDItype __xr = (X), __t, __a; \ -+ __t = __builtin_sw_64_cmpbge (0, __xr); \ -+ __t = ~__t & -~__t; \ -+ __a = ((__t & 0xCC) != 0) * 2; \ -+ __a += ((__t & 0xF0) != 0) * 4; \ -+ __a += ((__t & 0xAA) != 0); \ -+ __t = __builtin_sw_64_extbl (__xr, __a); \ -+ __a <<= 3; \ -+ __t &= -__t; \ -+ __a += ((__t & 0xCC) != 0) * 2; \ -+ __a += ((__t & 0xF0) != 0) * 4; \ -+ __a += ((__t & 0xAA) != 0); \ -+ (COUNT) = __a; \ -+ } while (0) -+#endif /* __sw_64_cix__ */ -+#endif /* __sw_64 */ -+// sw_64 -+ - #if defined (__arc__) && W_TYPE_SIZE == 32 - #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ - __asm__ ("add.f %1, %4, %5\n\tadc %0, %2, %3" \ -diff --git a/include/opcode/sw_64.h b/include/opcode/sw_64.h -new file mode 100644 -index 00000000..14668753 ---- /dev/null -+++ b/include/opcode/sw_64.h -@@ -0,0 +1,246 @@ -+/* sw_64.h -- Header file for Sw_64 opcode table -+ Copyright (C) 1996-2023 Free Software Foundation, Inc. -+ Contributed by Richard Henderson , -+ patterned after the PPC opcode table written by Ian Lance Taylor. -+ -+ This file is part of GDB, GAS, and the GNU binutils. -+ -+ GDB, GAS, and the GNU binutils are free software; you can redistribute -+ them and/or modify them under the terms of the GNU General Public -+ License as published by the Free Software Foundation; either version 3, -+ or (at your option) any later version. -+ -+ GDB, GAS, and the GNU binutils are distributed in the hope that they -+ will be useful, but WITHOUT ANY WARRANTY; without even the implied -+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -+ the GNU General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this file; see the file COPYING3. If not, write to the Free -+ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, -+ MA 02110-1301, USA. */ -+ -+#ifndef OPCODE_SW_64_H -+#define OPCODE_SW_64_H -+ -+/* The opcode table is an array of struct sw_64_opcode. */ -+ -+struct sw_64_opcode -+{ -+ /* The opcode name. */ -+ const char *name; -+ -+ /* The opcode itself. Those bits which will be filled in with -+ operands are zeroes. */ -+ unsigned opcode; -+ -+ /* The opcode mask. This is used by the disassembler. This is a -+ mask containing ones indicating those bits which must match the -+ opcode field, and zeroes indicating those bits which need not -+ match (and are presumably filled in by operands). */ -+ unsigned mask; -+ -+ /* One bit flags for the opcode. These are primarily used to -+ indicate specific processors and environments support the -+ instructions. The defined values are listed below. */ -+ unsigned flags; -+ -+ /* An array of operand codes. Each code is an index into the -+ operand table. They appear in the order which the operands must -+ appear in assembly code, and are terminated by a zero. */ -+ -+ unsigned char operands[5]; -+}; -+ -+/* The table itself is sorted by major opcode number, and is otherwise -+ in the order in which the disassembler should consider -+ instructions. */ -+extern const struct sw_64_opcode sw_64_opcodes[]; -+extern const unsigned sw_64_num_opcodes; -+ -+/* Values defined for the flags field of a struct sw_64_opcode. */ -+ -+/* CPU Availability */ -+#define AXP_OPCODE_SW6 0x0800 /* SW6 insns. */ -+#define AXP_OPCODE_SW6A 0x1000 /* SW6A insns. */ -+#define AXP_OPCODE_SW6B 0x2000 /* SW6B insns. */ -+#define AXP_OPCODE_SW8A 0x4000 /* SW8A insns. */ -+#define AXP_OPCODE_SW4E 0x8000 /* SW4E insns. */ -+ -+#define AXP_OPCODE_NOPAL \ -+ ((AXP_OPCODE_SW6 | AXP_OPCODE_SW6A | AXP_OPCODE_SW6B | AXP_OPCODE_SW8A \ -+ | AXP_OPCODE_SW4E)) -+ -+/* A macro to extract the major opcode from an instruction. */ -+#define AXP_OP(i) (((i) >> 26) & 0x3F) -+ -+#define AXP_LITOP(i) (((i) >> 26) & 0x3D) -+ -+/* The total number of major opcodes. */ -+#define AXP_NOPS 0x40 -+ -+/* The operands table is an array of struct sw_64_operand. */ -+ -+struct sw_64_operand -+{ -+ /* The number of bits in the operand. */ -+ unsigned int bits : 5; -+ -+ /* How far the operand is left shifted in the instruction. */ -+ unsigned int shift : 5; -+ -+ /* The default relocation type for this operand. */ -+ signed int default_reloc : 16; -+ -+ /* One bit syntax flags. */ -+ unsigned int flags : 16; -+ -+ /* Insertion function. This is used by the assembler. To insert an -+ operand value into an instruction, check this field. -+ -+ If it is NULL, execute -+ i |= (op & ((1 << o->bits) - 1)) << o->shift; -+ (i is the instruction which we are filling in, o is a pointer to -+ this structure, and op is the opcode value; this assumes twos -+ complement arithmetic). -+ -+ If this field is not NULL, then simply call it with the -+ instruction and the operand value. It will return the new value -+ of the instruction. If the ERRMSG argument is not NULL, then if -+ the operand value is illegal, *ERRMSG will be set to a warning -+ string (the operand will be inserted in any case). If the -+ operand value is legal, *ERRMSG will be unchanged (most operands -+ can accept any value). */ -+ unsigned (*insert) (unsigned instruction, int op, const char **errmsg); -+ -+ /* Extraction function. This is used by the disassembler. To -+ extract this operand type from an instruction, check this field. -+ -+ If it is NULL, compute -+ op = ((i) >> o->shift) & ((1 << o->bits) - 1); -+ if ((o->flags & AXP_OPERAND_SIGNED) != 0 -+ && (op & (1 << (o->bits - 1))) != 0) -+ op -= 1 << o->bits; -+ (i is the instruction, o is a pointer to this structure, and op -+ is the result; this assumes twos complement arithmetic). -+ -+ If this field is not NULL, then simply call it with the -+ instruction value. It will return the value of the operand. If -+ the INVALID argument is not NULL, *INVALID will be set to -+ non-zero if this operand type can not actually be extracted from -+ this operand (i.e., the instruction does not match). If the -+ operand is valid, *INVALID will not be changed. */ -+ int (*extract) (unsigned instruction, int *invalid); -+}; -+ -+#define ISA_UNKNOWN 0 /* Gas internal use. */ -+ -+#define CPU_UNKNOWN 0 /* Gas internal use. */ -+ -+/* Elements in the table are retrieved by indexing with values from -+ the operands field of the sw_64_opcodes table. */ -+ -+extern const struct sw_64_operand sw_64_operands[]; -+extern const unsigned sw_64_num_operands; -+ -+/* Values defined for the flags field of a struct sw_64_operand. */ -+ -+/* Mask for selecting the type for typecheck purposes. */ -+#define AXP_OPERAND_TYPECHECK_MASK \ -+ (AXP_OPERAND_PARENS | AXP_OPERAND_COMMA | AXP_OPERAND_IR | AXP_OPERAND_FPR \ -+ | AXP_OPERAND_RELATIVE | AXP_OPERAND_SIGNED | AXP_OPERAND_UNSIGNED) -+ -+/* This operand does not actually exist in the assembler input. This -+ is used to support extended mnemonics, for which two operands fields -+ are identical. The assembler should call the insert function with -+ any op value. The disassembler should call the extract function, -+ ignore the return value, and check the value placed in the invalid -+ argument. */ -+#define AXP_OPERAND_FAKE 01 -+ -+/* The operand should be wrapped in parentheses rather than separated -+ from the previous by a comma. This is used for the load and store -+ instructions which want their operands to look like "Ra,disp (Rb)". */ -+#define AXP_OPERAND_PARENS 02 -+ -+/* Used in combination with PARENS, this supresses the supression of -+ the comma. This is used for "jmp Ra,(Rb),hint". */ -+#define AXP_OPERAND_COMMA 04 -+ -+/* This operand names an integer register. */ -+#define AXP_OPERAND_IR 010 -+ -+/* This operand names a floating point register. */ -+#define AXP_OPERAND_FPR 020 -+ -+/* This operand is a relative branch displacement. The disassembler -+ prints these symbolically if possible. */ -+#define AXP_OPERAND_RELATIVE 040 -+ -+/* This operand takes signed values. */ -+#define AXP_OPERAND_SIGNED 0100 -+ -+/* This operand takes unsigned values. This exists primarily so that -+ a flags value of 0 can be treated as end-of-arguments. */ -+#define AXP_OPERAND_UNSIGNED 0200 -+ -+/* Supress overflow detection on this field. This is used for hints. */ -+#define AXP_OPERAND_NOOVERFLOW 0400 -+ -+/* Mask for optional argument default value. */ -+#define AXP_OPERAND_OPTIONAL_MASK 07000 -+ -+/* This operand defaults to zero. This is used for jump hints. */ -+#define AXP_OPERAND_DEFAULT_ZERO 01000 -+ -+/* This operand should default to the first (real) operand and is used -+ in conjunction with AXP_OPERAND_OPTIONAL. This allows -+ "and $0,3,$0" to be written as "and $0,3", etc. I don't like -+ it, but it's what DEC does. */ -+#define AXP_OPERAND_DEFAULT_FIRST 02000 -+ -+/* Similarly, this operand should default to the second (real) operand. -+ This allows "negl $0" instead of "negl $0,$0". */ -+#define AXP_OPERAND_DEFAULT_SECOND 04000 -+ -+/* Similarly, this operand should default to the third (real) operand. -+ * This allows "selne $0,$1,$2,$2" to be written as "selne $0,$1,$2" */ -+#define AXP_OPERAND_DEFAULT_THIRD 0xa00 -+ -+/* Register common names. */ -+ -+#define AXP_REG_V0 0 -+#define AXP_REG_T0 1 -+#define AXP_REG_T1 2 -+#define AXP_REG_T2 3 -+#define AXP_REG_T3 4 -+#define AXP_REG_T4 5 -+#define AXP_REG_T5 6 -+#define AXP_REG_T6 7 -+#define AXP_REG_T7 8 -+#define AXP_REG_S0 9 -+#define AXP_REG_S1 10 -+#define AXP_REG_S2 11 -+#define AXP_REG_S3 12 -+#define AXP_REG_S4 13 -+#define AXP_REG_S5 14 -+#define AXP_REG_FP 15 -+#define AXP_REG_A0 16 -+#define AXP_REG_A1 17 -+#define AXP_REG_A2 18 -+#define AXP_REG_A3 19 -+#define AXP_REG_A4 20 -+#define AXP_REG_A5 21 -+#define AXP_REG_T8 22 -+#define AXP_REG_T9 23 -+#define AXP_REG_T10 24 -+#define AXP_REG_T11 25 -+#define AXP_REG_RA 26 -+#define AXP_REG_PV 27 -+#define AXP_REG_T12 27 -+#define AXP_REG_AT 28 -+#define AXP_REG_GP 29 -+#define AXP_REG_SP 30 -+#define AXP_REG_ZERO 31 -+ -+#endif /* OPCODE_SW_64_H */ -diff --git a/ld/Makefile.am b/ld/Makefile.am -index c3adbb0c..fbeca376 100644 ---- a/ld/Makefile.am -+++ b/ld/Makefile.am -@@ -158,6 +158,7 @@ ALL_EMULATION_SOURCES = \ - eaixrs6.c \ - ealpha.c \ - ealphavms.c \ -+ esw_64.c \ - earcelf.c \ - earclinux.c \ - earclinux_nps.c \ -@@ -432,6 +433,9 @@ ALL_64_EMULATION_SOURCES = \ - eelf64alpha.c \ - eelf64alpha_fbsd.c \ - eelf64alpha_nbsd.c \ -+ eelf64sw_64.c \ -+ eelf64sw_64_fbsd.c \ -+ eelf64sw_64_nbsd.c \ - eelf64bmip.c \ - eelf64bpf.c \ - eelf64briscv.c \ -@@ -656,6 +660,7 @@ $(ALL_EMULATION_SOURCES) $(ALL_64_EMULATION_SOURCES): $(GEN_DEPENDS) - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eaixrs6.Pc@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ealpha.Pc@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ealphavms.Pc@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/esw_64.Pc@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earcelf.Pc@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earclinux.Pc@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earclinux_nps.Pc@am__quote@ -@@ -927,6 +932,9 @@ $(ALL_EMULATION_SOURCES) $(ALL_64_EMULATION_SOURCES): $(GEN_DEPENDS) - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64alpha.Pc@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64alpha_fbsd.Pc@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64alpha_nbsd.Pc@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64sw_64.Pc@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64sw_64_fbsd.Pc@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64sw_64_nbsd.Pc@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64bmip.Pc@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64bpf.Pc@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64briscv.Pc@am__quote@ -diff --git a/ld/Makefile.in b/ld/Makefile.in -index d1a56026..32eced36 100644 ---- a/ld/Makefile.in -+++ b/ld/Makefile.in -@@ -659,6 +659,7 @@ ALL_EMULATION_SOURCES = \ - eaixrs6.c \ - ealpha.c \ - ealphavms.c \ -+ esw_64.c \ - earcelf.c \ - earclinux.c \ - earclinux_nps.c \ -@@ -932,6 +933,9 @@ ALL_64_EMULATION_SOURCES = \ - eelf64alpha.c \ - eelf64alpha_fbsd.c \ - eelf64alpha_nbsd.c \ -+ eelf64sw_64.c \ -+ eelf64sw_64_fbsd.c \ -+ eelf64sw_64_nbsd.c \ - eelf64bmip.c \ - eelf64bpf.c \ - eelf64briscv.c \ -@@ -1277,6 +1281,7 @@ distclean-compile: - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eaixrs6.Po@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ealpha.Po@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ealphavms.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/esw_64.Po@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earcelf.Po@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earclinux.Po@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earclinux_nps.Po@am__quote@ -@@ -1435,6 +1440,9 @@ distclean-compile: - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64alpha.Po@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64alpha_fbsd.Po@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64alpha_nbsd.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64sw_64.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64sw_64_fbsd.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64sw_64_nbsd.Po@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64bmip.Po@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64bpf.Po@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64briscv.Po@am__quote@ -@@ -2373,6 +2381,7 @@ $(ALL_EMULATION_SOURCES) $(ALL_64_EMULATION_SOURCES): $(GEN_DEPENDS) - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eaixrs6.Pc@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ealpha.Pc@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ealphavms.Pc@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/esw_64.Pc@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earcelf.Pc@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earclinux.Pc@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earclinux_nps.Pc@am__quote@ -@@ -2644,6 +2653,9 @@ $(ALL_EMULATION_SOURCES) $(ALL_64_EMULATION_SOURCES): $(GEN_DEPENDS) - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64alpha.Pc@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64alpha_fbsd.Pc@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64alpha_nbsd.Pc@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64sw_64.Pc@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64sw_64_fbsd.Pc@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64sw_64_nbsd.Pc@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64bmip.Pc@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64bpf.Pc@am__quote@ - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64briscv.Pc@am__quote@ -diff --git a/ld/config.in b/ld/config.in -index ad0dc6a1..769863c6 100644 ---- a/ld/config.in -+++ b/ld/config.in -@@ -255,3 +255,5 @@ - - /* Define to 1 if you need to in order for `stat' and other things to work. */ - #undef _POSIX_SOURCE -+ -+#undef TARGET_SW_64 -diff --git a/ld/configure b/ld/configure -index 7037dfdd..68c49c17 100755 ---- a/ld/configure -+++ b/ld/configure -@@ -15663,6 +15663,13 @@ else - esac - fi - -+case "${target}" in -+ sw_64-*-*) -+cat >>confdefs.h <<_ACEOF -+#define TARGET_SW_64 -+_ACEOF -+ ;; -+ esac - - case "${enable_default_hash_style}" in - sysv | both) ac_default_emit_sysv_hash=1 ;; -diff --git a/ld/configure.tgt b/ld/configure.tgt -index c62b9581..a9917f62 100644 ---- a/ld/configure.tgt -+++ b/ld/configure.tgt -@@ -151,6 +151,22 @@ alpha*-*-openbsd*) targ_emul=elf64alpha - alpha*-*-*vms*) targ_emul=alphavms - targ_extra_ofiles= - ;; -+sw_64*-*-linux-* | sw_64*-*-gnu*) -+ case "${targ}" in -+ sw_64sw6a*) -+ targ_emul=elf64sw_64 targ_extra_emuls=sw_64 -+ tdir_sw_64=`echo ${targ_alias} | sed -e 's/linux\(-gnu\)*/linux\1ecoff/'` ;; -+ sw_64sw6b*) -+ targ_emul=elf64sw_64 targ_extra_emuls=sw_64 -+ tdir_sw_64=`echo ${targ_alias} | sed -e 's/linux\(-gnu\)*/linux\1ecoff/'` ;; -+ sw_64sw8a*) -+ targ_emul=elf64sw_64 targ_extra_emuls=sw_64 -+ tdir_sw_64=`echo ${targ_alias} | sed -e 's/linux\(-gnu\)*/linux\1ecoff/'` ;; -+ *) -+ targ_emul=elf64sw_64 targ_extra_emuls=sw_64 -+ tdir_sw_64=`echo ${targ_alias} | sed -e 's/linux\(-gnu\)*/linux\1ecoff/'` ;; -+ esac -+ ;; - am33_2.0-*-linux*) targ_emul=elf32am33lin # mn10300 variant - ;; - arc*-*-elf*) targ_emul=arcelf -@@ -1147,6 +1163,9 @@ alpha*-*-*) - NATIVE_LIB_DIRS='/usr/local/lib /usr/ccs/lib /lib /usr/lib' - ;; - -+sw_64*-*-*) -+ NATIVE_LIB_DIRS='/usr/local/lib /usr/ccs/lib /lib /usr/lib' -+ ;; - esac - - case "${target}" in -diff --git a/ld/emulparams/elf64sw_64.sh b/ld/emulparams/elf64sw_64.sh -new file mode 100644 -index 00000000..fb991baa ---- /dev/null -+++ b/ld/emulparams/elf64sw_64.sh -@@ -0,0 +1,38 @@ -+ENTRY=_start -+SCRIPT_NAME=elf -+ELFSIZE=64 -+TEMPLATE_NAME=elf -+EXTRA_EM_FILE=sw_64elf -+OUTPUT_FORMAT="elf64-sw_64" -+NO_REL_RELOCS=yes -+TEXT_START_ADDR="0x120000000" -+MAXPAGESIZE="CONSTANT (MAXPAGESIZE)" -+COMMONPAGESIZE="CONSTANT (COMMONPAGESIZE)" -+ -+# for flags of elf file header -+if [ "$sw_cpu_type" = "sw_64sw6a" ]; then -+ ARCH=sw_64:4 -+elif [ "$sw_cpu_type" = "sw_64sw6b" ]; then -+ ARCH=sw_64:8 -+elif [ "$sw_cpu_type" = "sw_64sw8a" ]; then -+ ARCH=sw_64:12 -+else -+ ARCH=sw_64 -+fi -+ -+MACHINE= -+GENERATE_SHLIB_SCRIPT=yes -+GENERATE_PIE_SCRIPT=yes -+ -+# Yes, we want duplicate .plt sections. The linker chooses the -+# appropriate one magically in sw_64_after_open. -+PLT=".plt ${RELOCATING-0} : SPECIAL { *(.plt) }" -+DATA_PLT=yes -+TEXT_PLT=yes -+ -+# Note that the number is always big-endian, thus we have to -+# reverse the digit string. -+NOP=0x5f07ff435f07ff43 -+ -+OTHER_READONLY_SECTIONS=" -+ .reginfo ${RELOCATING-0} : { *(.reginfo) }" -diff --git a/ld/emulparams/elf64sw_64_fbsd.sh b/ld/emulparams/elf64sw_64_fbsd.sh -new file mode 100644 -index 00000000..deef0352 ---- /dev/null -+++ b/ld/emulparams/elf64sw_64_fbsd.sh -@@ -0,0 +1,3 @@ -+source_sh ${srcdir}/emulparams/elf64sw_64.sh -+source_sh ${srcdir}/emulparams/elf_fbsd.sh -+OUTPUT_FORMAT="elf64-sw_64-freebsd" -diff --git a/ld/emulparams/elf64sw_64_nbsd.sh b/ld/emulparams/elf64sw_64_nbsd.sh -new file mode 100644 -index 00000000..234df284 ---- /dev/null -+++ b/ld/emulparams/elf64sw_64_nbsd.sh -@@ -0,0 +1,2 @@ -+source_sh ${srcdir}/emulparams/elf64sw_64.sh -+ENTRY=__start -diff --git a/ld/emulparams/sw_64.sh b/ld/emulparams/sw_64.sh -new file mode 100644 -index 00000000..17c49bd7 ---- /dev/null -+++ b/ld/emulparams/sw_64.sh -@@ -0,0 +1,3 @@ -+SCRIPT_NAME=sw_64 -+OUTPUT_FORMAT="ecoff-littlesw_64" -+ARCH=sw_64 -diff --git a/ld/emultempl/sw_64elf.em b/ld/emultempl/sw_64elf.em -new file mode 100644 -index 00000000..b01baa80 ---- /dev/null -+++ b/ld/emultempl/sw_64elf.em -@@ -0,0 +1,152 @@ -+# This shell script emits a C file. -*- C -*- -+# Copyright (C) 2003-2023 Free Software Foundation, Inc. -+# -+# This file is part of the GNU Binutils. -+# -+# This program is free software; you can redistribute it and/or modify -+# it under the terms of the GNU General Public License as published by -+# the Free Software Foundation; either version 3 of the License, or -+# (at your option) any later version. -+# -+# This program is distributed in the hope that it will be useful, -+# but WITHOUT ANY WARRANTY; without even the implied warranty of -+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+# GNU General Public License for more details. -+# -+# You should have received a copy of the GNU General Public License -+# along with this program; if not, write to the Free Software -+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, -+# MA 02110-1301, USA. -+# -+ -+# This file is sourced from elf.em, and defines extra sw_64 -+# specific routines. -+# -+fragment <next) -+ { -+ if (os->constraint == SPECIAL && strcmp (os->name, ".plt") == 0) -+ { -+ if (num_plt < 2) -+ plt_os[num_plt] = os; -+ ++num_plt; -+ } -+ } -+ -+ if (num_plt == 2) -+ { -+ plt_os[0]->constraint = elf64_sw_64_use_secureplt ? 0 : -1; -+ plt_os[1]->constraint = elf64_sw_64_use_secureplt ? -1 : 0; -+ } -+ } -+ -+ gld${EMULATION_NAME}_after_open (); -+} -+ -+static void -+sw_64_after_parse (void) -+{ -+ link_info.relax_pass = 2; -+ if (limit_32bit -+ && !bfd_link_pic (&link_info) -+ && !bfd_link_relocatable (&link_info)) -+ lang_section_start (".interp", -+ exp_binop ('+', -+ exp_intop (SW_64_TEXT_START_32BIT), -+ exp_nameop (SIZEOF_HEADERS, NULL)), -+ NULL); -+ -+ ldelf_after_parse (); -+} -+ -+static void -+sw_64_before_allocation (void) -+{ -+ /* Call main function; we're just extending it. */ -+ gld${EMULATION_NAME}_before_allocation (); -+ -+ /* Add -relax if -O, not -r, and not explicitly disabled. */ -+ if (link_info.optimize -+ && !bfd_link_relocatable (&link_info) -+ && ! RELAXATION_DISABLED_BY_USER) -+ ENABLE_RELAXATION; -+} -+ -+static void -+sw_64_finish (void) -+{ -+ if (limit_32bit) -+ elf_elfheader (link_info.output_bfd)->e_flags |= EF_SW_64_32BIT; -+ -+ finish_default (); -+} -+EOF -+ -+# Define some shell vars to insert bits of code into the standard elf -+# parse_args and list_options functions. -+# -+PARSE_AND_LIST_PROLOGUE=' -+#define OPTION_TASO 300 -+#define OPTION_SECUREPLT (OPTION_TASO + 1) -+#define OPTION_NO_SECUREPLT (OPTION_SECUREPLT + 1) -+' -+ -+PARSE_AND_LIST_LONGOPTS=' -+ { "taso", no_argument, NULL, OPTION_TASO }, -+ { "secureplt", no_argument, NULL, OPTION_SECUREPLT }, -+ { "no-secureplt", no_argument, NULL, OPTION_NO_SECUREPLT }, -+' -+ -+PARSE_AND_LIST_OPTIONS=' -+ fprintf (file, _("\ -+ --taso Load executable in the lower 31-bit addressable\n\ -+ virtual address range.\n\ -+ --secureplt Force PLT in text segment.\n\ -+ --no-secureplt Force PLT in data segment.\n\ -+")); -+' -+ -+PARSE_AND_LIST_ARGS_CASES=' -+ case OPTION_TASO: -+ limit_32bit = 1; -+ break; -+ case OPTION_SECUREPLT: -+ elf64_sw_64_use_secureplt = true; -+ break; -+ case OPTION_NO_SECUREPLT: -+ elf64_sw_64_use_secureplt = false; -+ break; -+' -+ -+# Put these extra sw_64 routines in ld_${EMULATION_NAME}_emulation -+# -+LDEMUL_AFTER_OPEN=sw_64_after_open -+LDEMUL_AFTER_PARSE=sw_64_after_parse -+LDEMUL_BEFORE_ALLOCATION=sw_64_before_allocation -+LDEMUL_FINISH=sw_64_finish -diff --git a/ld/ldlex.h b/ld/ldlex.h -index 87cac021..65f23b54 100644 ---- a/ld/ldlex.h -+++ b/ld/ldlex.h -@@ -54,6 +54,7 @@ enum option_values - OPTION_OFORMAT, - OPTION_RELAX, - OPTION_NO_RELAX, -+ OPTION_LBR, - OPTION_NO_SYMBOLIC, - OPTION_RETAIN_SYMBOLS_FILE, - OPTION_RPATH, -diff --git a/ld/lexsup.c b/ld/lexsup.c -index fe872231..6bc26a39 100644 ---- a/ld/lexsup.c -+++ b/ld/lexsup.c -@@ -457,6 +457,8 @@ static const struct ld_option ld_options[] = - '\0', NULL, N_("Reduce code size by using target specific optimizations"), TWO_DASHES }, - { {"no-relax", no_argument, NULL, OPTION_NO_RELAX}, - '\0', NULL, N_("Do not use relaxation techniques to reduce code size"), TWO_DASHES }, -+ { {"fsw-lbr", no_argument, NULL, OPTION_LBR}, -+ '\0', NULL, N_("Reduce code size by using target specific optimizations"), ONE_DASH}, - { {"retain-symbols-file", required_argument, NULL, - OPTION_RETAIN_SYMBOLS_FILE}, - '\0', N_("FILE"), N_("Keep only symbols listed in FILE"), TWO_DASHES }, -@@ -1286,6 +1288,9 @@ parse_args (unsigned argc, char **argv) - case OPTION_RELAX: - ENABLE_RELAXATION; - break; -+ case OPTION_LBR: -+ link_info.flag_sw_lbr=8; -+ break; - case OPTION_RETAIN_SYMBOLS_FILE: - add_keepsyms_file (optarg); - break; -diff --git a/ld/scripttempl/sw_64.sc b/ld/scripttempl/sw_64.sc -new file mode 100644 -index 00000000..56020f37 ---- /dev/null -+++ b/ld/scripttempl/sw_64.sc -@@ -0,0 +1,87 @@ -+# Linker script for Sw_64 systems. -+# Ian Lance Taylor . -+# These variables may be overridden by the emulation file. The -+# defaults are appropriate for an Sw_64 running OSF/1. -+# -+# Copyright (C) 2014-2023 Free Software Foundation, Inc. -+# -+# Copying and distribution of this file, with or without modification, -+# are permitted in any medium without royalty provided the copyright -+# notice and this notice are preserved. -+ -+test -z "$ENTRY" && ENTRY=__start -+test -z "$TEXT_START_ADDR" && TEXT_START_ADDR="0x120000000 + SIZEOF_HEADERS" -+if test "x$LD_FLAG" = "xn" -o "x$LD_FLAG" = "xN"; then -+ DATA_ADDR=. -+else -+ test -z "$DATA_ADDR" && DATA_ADDR=0x140000000 -+fi -+cat <>confdefs.h <<_ACEOF -+#define TARGET_SW_64 -+_ACEOF -+# endif -+ ;; - bfd_amdgcn_arch) ;; - bfd_arc_arch) ta="$ta arc-dis.lo arc-opc.lo arc-ext.lo" ;; - bfd_arm_arch) ta="$ta arm-dis.lo" ;; -diff --git a/opcodes/configure.ac b/opcodes/configure.ac -index 1beb72e8..edf691b9 100644 ---- a/opcodes/configure.ac -+++ b/opcodes/configure.ac -@@ -263,6 +263,7 @@ if test x${all_targets} = xfalse ; then - case "$arch" in - bfd_aarch64_arch) ta="$ta aarch64-asm.lo aarch64-dis.lo aarch64-opc.lo aarch64-asm-2.lo aarch64-dis-2.lo aarch64-opc-2.lo" ;; - bfd_alpha_arch) ta="$ta alpha-dis.lo alpha-opc.lo" ;; -+ bfd_sw_64_arch) ta="$ta sw_64-dis.lo sw_64-opc.lo" ;; - bfd_amdgcn_arch) ;; - bfd_arc_arch) ta="$ta arc-dis.lo arc-opc.lo arc-ext.lo" ;; - bfd_arm_arch) ta="$ta arm-dis.lo" ;; -diff --git a/opcodes/configure.com b/opcodes/configure.com -index 1fd2741f..c6a2afda 100644 ---- a/opcodes/configure.com -+++ b/opcodes/configure.com -@@ -44,6 +44,14 @@ $ FILES="alpha-dis,alpha-opc" - $ DEFS="""ARCH_alpha""" - $EOD - $ endif -+$ if arch.eqs."sw_64" -+$ then -+$ create build.com -+$DECK -+$ FILES="sw_64-dis,sw_64-opc" -+$ DEFS="""ARCH_sw_64""" -+$EOD -+$ endif - $! - $ append sys$input build.com - $DECK -diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c -index 7a4a641c..3db14bca 100644 ---- a/opcodes/disassemble.c -+++ b/opcodes/disassemble.c -@@ -27,6 +27,9 @@ - #ifdef BFD64 - #define ARCH_aarch64 - #define ARCH_alpha -+#ifdef TARGET_SW_64 -+#define ARCH_sw_64 -+#endif - #define ARCH_bpf - #define ARCH_ia64 - #define ARCH_loongarch -@@ -147,6 +150,13 @@ disassembler (enum bfd_architecture a, - disassemble = print_insn_alpha; - break; - #endif -+#ifdef TARGET_SW_64 -+#ifdef ARCH_sw_64 -+ case bfd_arch_sw_64: -+ disassemble = print_insn_sw_64; -+ break; -+#endif -+#endif - #ifdef ARCH_arc - case bfd_arch_arc: - disassemble = arc_get_disassembler (abfd); -diff --git a/opcodes/disassemble.h b/opcodes/disassemble.h -index b7474a85..06a38a66 100644 ---- a/opcodes/disassemble.h -+++ b/opcodes/disassemble.h -@@ -23,6 +23,9 @@ - - extern int print_insn_aarch64 (bfd_vma, disassemble_info *); - extern int print_insn_alpha (bfd_vma, disassemble_info *); -+#ifdef TARGET_SW_64 -+extern int print_insn_sw_64 (bfd_vma, disassemble_info *); -+#endif - extern int print_insn_avr (bfd_vma, disassemble_info *); - extern int print_insn_bfin (bfd_vma, disassemble_info *); - extern int print_insn_big_arm (bfd_vma, disassemble_info *); -diff --git a/opcodes/sw_64-dis.c b/opcodes/sw_64-dis.c -new file mode 100644 -index 00000000..7e139239 ---- /dev/null -+++ b/opcodes/sw_64-dis.c -@@ -0,0 +1,238 @@ -+/* sw_64-dis.c -- Disassemble Sw_64 AXP instructions -+ Copyright (C) 1996-2023 Free Software Foundation, Inc. -+ Contributed by Richard Henderson , -+ patterned after the PPC opcode handling written by Ian Lance Taylor. -+ -+ This file is part of libopcodes. -+ -+ This library is free software; you can redistribute it and/or modify -+ it under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 3, or (at your option) -+ any later version. -+ -+ It is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+ License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this file; see the file COPYING. If not, write to the Free -+ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA -+ 02110-1301, USA. */ -+ -+#include "sysdep.h" -+#include -+#include "disassemble.h" -+#include "opcode/sw_64.h" -+ -+/* OSF register names. */ -+ -+static const char *const osf_regnames[64] -+ = {"$r0", "$r1", "$r2", "$r3", "$r4", "$r5", "$r6", "$r7", -+ "$r8", "$r9", "$r10", "$r11", "$r12", "$r13", "$r14", "fp", -+ "$r16", "$r17", "$r18", "$r19", "$r20", "$r21", "$r22", "$r23", -+ "$r24", "$r25", "ra", "$r27", "$r28", "$r29", "sp", "$r31", -+ "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", -+ "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", -+ "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", -+ "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"}; -+ -+/* VMS register names. */ -+ -+static const char *const vms_regnames[64] -+ = {"R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", "R8", "R9", -+ "R10", "R11", "R12", "R13", "R14", "R15", "R16", "R17", "R18", "R19", -+ "R20", "R21", "R22", "R23", "R24", "AI", "RA", "PV", "AT", "FP", -+ "SP", "RZ", "F0", "F1", "F2", "F3", "F4", "F5", "F6", "F7", -+ "F8", "F9", "F10", "F11", "F12", "F13", "F14", "F15", "F16", "F17", -+ "F18", "F19", "F20", "F21", "F22", "F23", "F24", "F25", "F26", "F27", -+ "F28", "F29", "F30", "FZ"}; -+ -+/* Disassemble Sw_64 instructions. */ -+ -+int -+print_insn_sw_64 (bfd_vma memaddr, struct disassemble_info *info) -+{ -+ static const struct sw_64_opcode *opcode_index[AXP_NOPS + 1]; -+ const char *const *regnames; -+ const struct sw_64_opcode *opcode, *opcode_end; -+ const unsigned char *opindex; -+ unsigned insn, op, isa_mask; -+ int need_comma; -+ -+ /* Initialize the majorop table the first time through. */ -+ if (!opcode_index[0]) -+ { -+ opcode = sw_64_opcodes; -+ opcode_end = opcode + sw_64_num_opcodes; -+ -+ for (op = 0; op < AXP_NOPS; ++op) -+ { -+ opcode_index[op] = opcode; -+ if ((AXP_LITOP (opcode->opcode) != 0x10) -+ && (AXP_LITOP (opcode->opcode) != 0x11)) -+ { -+ while (opcode < opcode_end && op == AXP_OP (opcode->opcode)) -+ ++opcode; -+ } -+ else -+ { -+ while (opcode < opcode_end && op == AXP_LITOP (opcode->opcode)) -+ ++opcode; -+ } -+ } -+ opcode_index[op] = opcode; -+ } -+ -+ if (info->flavour == bfd_target_evax_flavour) -+ regnames = vms_regnames; -+ else -+ regnames = osf_regnames; -+ -+ isa_mask = AXP_OPCODE_NOPAL; -+ switch (info->mach) -+ { -+ case bfd_mach_sw_64_sw6a: -+ isa_mask |= AXP_OPCODE_SW6 | AXP_OPCODE_SW6A; -+ break; -+ case bfd_mach_sw_64_sw6b: -+ isa_mask |= AXP_OPCODE_SW6 | AXP_OPCODE_SW6B; -+ break; -+ case bfd_mach_sw_64_sw8a: -+ isa_mask |= AXP_OPCODE_SW6 | AXP_OPCODE_SW8A; -+ break; -+ } -+ -+ /* Read the insn into a host word. */ -+ { -+ bfd_byte buffer[4]; -+ int status = (*info->read_memory_func) (memaddr, buffer, 4, info); -+ if (status != 0) -+ { -+ (*info->memory_error_func) (status, memaddr, info); -+ return -1; -+ } -+ insn = bfd_getl32 (buffer); -+ } -+ -+ /* Get the major opcode of the instruction. */ -+ -+ if ((AXP_LITOP (insn) == 0x10) || (AXP_LITOP (insn) == 0x11)) -+ op = AXP_LITOP (insn); -+ else if ((AXP_OP (insn) & 0x3C) == 0x14) // logx -+ op = 0x14; -+ else -+ op = AXP_OP (insn); -+ -+ /* Find the first match in the opcode table. */ -+ opcode_end = opcode_index[op + 1]; -+ for (opcode = opcode_index[op]; opcode < opcode_end; ++opcode) -+ { -+ if ((insn ^ opcode->opcode) & opcode->mask) -+ continue; -+ -+ if (!(opcode->flags & isa_mask)) -+ continue; -+ -+ /* Make two passes over the operands. First see if any of them -+ have extraction functions, and, if they do, make sure the -+ instruction is valid. */ -+ { -+ int invalid = 0; -+ for (opindex = opcode->operands; *opindex != 0; opindex++) -+ { -+ const struct sw_64_operand *operand = sw_64_operands + *opindex; -+ if (operand->extract) -+ (*operand->extract) (insn, &invalid); -+ } -+ if (invalid) -+ continue; -+ } -+ -+ /* The instruction is valid. */ -+ goto found; -+ } -+ -+ /* No instruction found. */ -+ (*info->fprintf_func) (info->stream, ".long %#08x", insn); -+ -+ return 4; -+ -+found: -+ if (!strncmp ("sys_call", opcode->name, 8)) -+ { -+ if (insn & (0x1 << 25)) -+ (*info->fprintf_func) (info->stream, "%s", "sys_call"); -+ else -+ (*info->fprintf_func) (info->stream, "%s", "sys_call/b"); -+ } -+ else -+ (*info->fprintf_func) (info->stream, "%s", opcode->name); -+ -+ /* Get zz[7:6] and zz[5:0] to form truth for vlog. */ -+ if (!strcmp (opcode->name, "vlog")) -+ { -+ unsigned int truth; -+ char tr[4]; -+ truth = (AXP_OP (insn) & 3) << 6; -+ truth = truth | ((insn & 0xFC00) >> 10); -+ sprintf (tr, "%x", truth); -+ (*info->fprintf_func) (info->stream, "%s", tr); -+ } -+ if (opcode->operands[0] != 0) -+ (*info->fprintf_func) (info->stream, "\t"); -+ -+ /* Now extract and print the operands. */ -+ need_comma = 0; -+ for (opindex = opcode->operands; *opindex != 0; opindex++) -+ { -+ const struct sw_64_operand *operand = sw_64_operands + *opindex; -+ int value; -+ -+ /* Operands that are marked FAKE are simply ignored. We -+ already made sure that the extract function considered -+ the instruction to be valid. */ -+ if ((operand->flags & AXP_OPERAND_FAKE) != 0) -+ continue; -+ -+ /* Extract the value from the instruction. */ -+ if (operand->extract) -+ value = (*operand->extract) (insn, (int *) NULL); -+ else -+ { -+ value = (insn >> operand->shift) & ((1 << operand->bits) - 1); -+ if (operand->flags & AXP_OPERAND_SIGNED) -+ { -+ int signbit = 1 << (operand->bits - 1); -+ value = (value ^ signbit) - signbit; -+ } -+ } -+ -+ if (need_comma -+ && ((operand->flags & (AXP_OPERAND_PARENS | AXP_OPERAND_COMMA)) -+ != AXP_OPERAND_PARENS)) -+ { -+ (*info->fprintf_func) (info->stream, ","); -+ } -+ if (operand->flags & AXP_OPERAND_PARENS) -+ (*info->fprintf_func) (info->stream, "("); -+ -+ /* Print the operand as directed by the flags. */ -+ if (operand->flags & AXP_OPERAND_IR) -+ (*info->fprintf_func) (info->stream, "%s", regnames[value]); -+ else if (operand->flags & AXP_OPERAND_FPR) -+ (*info->fprintf_func) (info->stream, "%s", regnames[value + 32]); -+ else if (operand->flags & AXP_OPERAND_RELATIVE) -+ (*info->print_address_func) (memaddr + 4 + value, info); -+ else if (operand->flags & AXP_OPERAND_SIGNED) -+ (*info->fprintf_func) (info->stream, "%d", value); -+ else -+ (*info->fprintf_func) (info->stream, "%#x", value); -+ -+ if (operand->flags & AXP_OPERAND_PARENS) -+ (*info->fprintf_func) (info->stream, ")"); -+ need_comma = 1; -+ } -+ -+ return 4; -+} -diff --git a/opcodes/sw_64-opc.c b/opcodes/sw_64-opc.c -new file mode 100644 -index 00000000..f770919e ---- /dev/null -+++ b/opcodes/sw_64-opc.c -@@ -0,0 +1,1398 @@ -+/* sw_64-opc.c -- Sw_64 AXP opcode list -+ Copyright (C) 1996-2023 Free Software Foundation, Inc. -+ Contributed by Richard Henderson , -+ patterned after the PPC opcode handling written by Ian Lance Taylor. -+ -+ This file is part of libopcodes. -+ -+ This library is free software; you can redistribute it and/or modify -+ it under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 3, or (at your option) -+ any later version. -+ -+ It is distributed in the hope that it will be useful, but WITHOUT -+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -+ License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this file; see the file COPYING. If not, write to the -+ Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA -+ 02110-1301, USA. */ -+ -+#include "sysdep.h" -+#include -+#include "opcode/sw_64.h" -+#include "bfd.h" -+#include "opintl.h" -+ -+/* This file holds the Sw_64 AXP opcode table. The opcode table includes -+ almost all of the extended instruction mnemonics. This permits the -+ disassembler to use them, and simplifies the assembler logic, at the -+ cost of increasing the table size. The table is strictly constant -+ data, so the compiler should be able to put it in the text segment. -+ -+ This file also holds the operand table. All knowledge about inserting -+ and extracting operands from instructions is kept in this file. -+ -+ The information for the base instruction set was compiled from the -+ _Sw_64 Architecture Handbook_, Digital Order Number EC-QD2KB-TE, -+ version 2. -+ */ -+ -+/* The RB field when it is the same as the RA field in the same insn. -+ This operand is marked fake. The insertion function just copies -+ the RA field into the RB field, and the extraction function just -+ checks that the fields are the same. */ -+ -+static unsigned -+insert_rba (unsigned insn, int value ATTRIBUTE_UNUSED, -+ const char **errmsg ATTRIBUTE_UNUSED) -+{ -+ return insn | (((insn >> 21) & 0x1f) << 16); -+} -+ -+static int -+extract_rba (unsigned insn, int *invalid) -+{ -+ if (invalid != (int *) NULL && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f)) -+ *invalid = 1; -+ return 0; -+} -+ -+/* The same for the RC field. */ -+ -+static unsigned -+insert_rca (unsigned insn, int value ATTRIBUTE_UNUSED, -+ const char **errmsg ATTRIBUTE_UNUSED) -+{ -+ return insn | ((insn >> 21) & 0x1f); -+} -+ -+static int -+extract_rca (unsigned insn, int *invalid) -+{ -+ if (invalid != (int *) NULL && ((insn >> 21) & 0x1f) != (insn & 0x1f)) -+ *invalid = 1; -+ return 0; -+} -+ -+static unsigned -+insert_rdc (unsigned insn, int value ATTRIBUTE_UNUSED, -+ const char **errmsg ATTRIBUTE_UNUSED) -+{ -+ return insn | ((insn >> 5) & 0x1f); -+} -+ -+static int -+extract_rdc (unsigned insn, int *invalid) -+{ -+ if (invalid != (int *) NULL && ((insn >> 5) & 0x1f) != (insn & 0x1f)) -+ *invalid = 1; -+ return 0; -+} -+ -+/* Fake arguments in which the registers must be set to ZERO. */ -+ -+static unsigned -+insert_za (unsigned insn, int value ATTRIBUTE_UNUSED, -+ const char **errmsg ATTRIBUTE_UNUSED) -+{ -+ return insn | (31 << 21); -+} -+ -+static int -+extract_za (unsigned insn, int *invalid) -+{ -+ if (invalid != (int *) NULL && ((insn >> 21) & 0x1f) != 31) -+ *invalid = 1; -+ return 0; -+} -+ -+static unsigned -+insert_zb (unsigned insn, int value ATTRIBUTE_UNUSED, -+ const char **errmsg ATTRIBUTE_UNUSED) -+{ -+ return insn | (31 << 16); -+} -+ -+static int -+extract_zb (unsigned insn, int *invalid) -+{ -+ if (invalid != (int *) NULL && ((insn >> 16) & 0x1f) != 31) -+ *invalid = 1; -+ return 0; -+} -+ -+static unsigned -+insert_zc (unsigned insn, int value ATTRIBUTE_UNUSED, -+ const char **errmsg ATTRIBUTE_UNUSED) -+{ -+ return insn | 31; -+} -+ -+static int -+extract_zc (unsigned insn, int *invalid) -+{ -+ if (invalid != (int *) NULL && (insn & 0x1f) != 31) -+ *invalid = 1; -+ return 0; -+} -+ -+static unsigned -+insert_zc2 (unsigned insn, int value ATTRIBUTE_UNUSED, -+ const char **errmsg ATTRIBUTE_UNUSED) -+{ -+ return insn | 31 << 5; -+} -+ -+static int -+extract_zc2 (unsigned insn, int *invalid) -+{ -+ if (invalid != (int *) NULL && ((insn >> 5) & 0x1f) != 31) -+ *invalid = 1; -+ return 0; -+} -+ -+/* The displacement field of a Branch format insn. */ -+ -+static unsigned -+insert_bdisp (unsigned insn, int value, const char **errmsg) -+{ -+ if (errmsg != (const char **) NULL && (value & 3)) -+ *errmsg = _ ("branch operand unaligned"); -+ return insn | ((value / 4) & 0x1FFFFF); -+} -+ -+static int -+extract_bdisp (unsigned insn, int *invalid ATTRIBUTE_UNUSED) -+{ -+ return 4 * (((insn & 0x1FFFFF) ^ 0x100000) - 0x100000); -+} -+ -+static unsigned -+insert_bdisp26 (unsigned insn, int value, const char **errmsg) -+{ -+ if (errmsg != (const char **) NULL && (value & 3)) -+ *errmsg = _ ("branch operand unaligned"); -+ return insn | ((value / 4) & 0x3FFFFFF); -+} -+ -+static int -+extract_bdisp26 (unsigned insn, int *invalid ATTRIBUTE_UNUSED) -+{ -+ return 4 * (((insn & 0x3FFFFFF) ^ 0x2000000) - 0x2000000); -+} -+ -+/* The hint field of a JMP/JSR insn. */ -+ -+/* sw use 16 bits hint disp. */ -+static unsigned -+insert_jhint (unsigned insn, int value, const char **errmsg) -+{ -+ if (errmsg != (const char **) NULL && (value & 3)) -+ *errmsg = _ ("jump hint unaligned"); -+ return insn | ((value / 4) & 0xFFFF); -+} -+ -+static int -+extract_jhint (unsigned insn, int *invalid ATTRIBUTE_UNUSED) -+{ -+ return 4 * (((insn & 0xFFFF) ^ 0x8000) - 0x8000); -+} -+ -+/* The hint field of an SW6 HW_JMP/JSR insn. */ -+ -+static unsigned -+insert_sw6hwjhint (unsigned insn, int value, const char **errmsg) -+{ -+ if (errmsg != (const char **) NULL && (value & 3)) -+ *errmsg = _ ("jump hint unaligned"); -+ return insn | ((value / 4) & 0x1FFF); -+} -+ -+static int -+extract_sw6hwjhint (unsigned insn, int *invalid ATTRIBUTE_UNUSED) -+{ -+ return 4 * (((insn & 0x1FFF) ^ 0x1000) - 0x1000); -+} -+ -+/* The operands table. */ -+ -+const struct sw_64_operand sw_64_operands[] = { -+/* The fields are bits, shift, insert, extract, flags. */ -+/* The zero index is used to indicate end-of-list. */ -+#define UNUSED 0 -+ {0, 0, 0, 0, 0, 0}, -+ -+/* The plain integer register fields. */ -+#define RA (UNUSED + 1) -+ {5, 21, 0, AXP_OPERAND_IR, 0, 0}, -+#define RB (RA + 1) -+ {5, 16, 0, AXP_OPERAND_IR, 0, 0}, -+#define RC (RB + 1) -+ {5, 0, 0, AXP_OPERAND_IR, 0, 0}, -+ -+/* The plain fp register fields. */ -+#define FA (RC + 1) -+ {5, 21, 0, AXP_OPERAND_FPR, 0, 0}, -+#define FB (FA + 1) -+ {5, 16, 0, AXP_OPERAND_FPR, 0, 0}, -+#define FC (FB + 1) -+ {5, 0, 0, AXP_OPERAND_FPR, 0, 0}, -+ -+/* The integer registers when they are ZERO. */ -+#define ZA (FC + 1) -+ {5, 21, 0, AXP_OPERAND_FAKE, insert_za, extract_za}, -+#define ZB (ZA + 1) -+ {5, 16, 0, AXP_OPERAND_FAKE, insert_zb, extract_zb}, -+#define ZC (ZB + 1) -+ {5, 0, 0, AXP_OPERAND_FAKE, insert_zc, extract_zc}, -+ -+/* The RB field when it needs parentheses. */ -+#define PRB (ZC + 1) -+ {5, 16, 0, AXP_OPERAND_IR | AXP_OPERAND_PARENS, 0, 0}, -+ -+/* The RB field when it needs parentheses _and_ a preceding comma. */ -+#define CPRB (PRB + 1) -+ {5, 16, 0, AXP_OPERAND_IR | AXP_OPERAND_PARENS | AXP_OPERAND_COMMA, 0, 0}, -+ -+/* The RB field when it must be the same as the RA field. */ -+#define RBA (CPRB + 1) -+ {5, 16, 0, AXP_OPERAND_FAKE, insert_rba, extract_rba}, -+ -+/* The RC field when it must be the same as the RB field. */ -+#define RCA (RBA + 1) -+ {5, 0, 0, AXP_OPERAND_FAKE, insert_rca, extract_rca}, -+ -+#define RDC (RCA + 1) -+ {5, 0, 0, AXP_OPERAND_FAKE, insert_rdc, extract_rdc}, -+ -+/* The RC field when it can *default* to RA. */ -+#define DRC1 (RDC + 1) -+ {5, 0, 0, AXP_OPERAND_IR | AXP_OPERAND_DEFAULT_FIRST, 0, 0}, -+ -+/* The RC field when it can *default* to RB. */ -+#define DRC2 (DRC1 + 1) -+ {5, 0, 0, AXP_OPERAND_IR | AXP_OPERAND_DEFAULT_SECOND, 0, 0}, -+ -+/* The RD field when it can *default* to RC. */ -+#define DRC3 (DRC2 + 1) -+ {5, 0, 0, AXP_OPERAND_IR | AXP_OPERAND_DEFAULT_THIRD, 0, 0}, -+ -+/* The FC field when it can *default* to RA. */ -+#define DFC1 (DRC3 + 1) -+ {5, 0, 0, AXP_OPERAND_FPR | AXP_OPERAND_DEFAULT_FIRST, 0, 0}, -+ -+/* The FC field when it can *default* to RB. */ -+#define DFC2 (DFC1 + 1) -+ {5, 0, 0, AXP_OPERAND_FPR | AXP_OPERAND_DEFAULT_SECOND, 0, 0}, -+ -+/* The FD field when it can *default* to FC. */ -+#define DFC3 (DFC2 + 1) -+ {5, 0, 0, AXP_OPERAND_FPR | AXP_OPERAND_DEFAULT_THIRD, 0, 0}, -+ -+/* The unsigned 8-bit literal of Operate format insns. */ -+#define LIT (DFC3 + 1) -+ {8, 13, -LIT, AXP_OPERAND_UNSIGNED, 0, 0}, -+ -+/* The signed 16-bit displacement of Memory format insns. From here -+ we can't tell what relocation should be used, so don't use a default. */ -+#define MDISP (LIT + 1) -+ {16, 0, -MDISP, AXP_OPERAND_SIGNED, 0, 0}, -+ -+/* The signed "23-bit" aligned displacement of Branch format insns. */ -+#define BDISP (MDISP + 1) -+ {21, 0, BFD_RELOC_23_PCREL_S2, AXP_OPERAND_RELATIVE, insert_bdisp, -+ extract_bdisp}, -+ -+/* The 25-bit PALcode function. */ -+#define PALFN (BDISP + 1) -+ {25, 0, -PALFN, AXP_OPERAND_UNSIGNED, 0, 0}, -+ -+/* sw jsr/ret insntructions has no function bits. */ -+/* The optional signed "16-bit" aligned displacement of the JMP/JSR hint. */ -+#define JMPHINT (PALFN + 1) -+ {16, 0, BFD_RELOC_SW_64_HINT, -+ AXP_OPERAND_RELATIVE | AXP_OPERAND_DEFAULT_ZERO | AXP_OPERAND_NOOVERFLOW, -+ insert_jhint, extract_jhint}, -+ -+/* The optional hint to RET/JSR_COROUTINE. */ -+#define RETHINT (JMPHINT + 1) -+ {16, 0, -RETHINT, AXP_OPERAND_UNSIGNED | AXP_OPERAND_DEFAULT_ZERO, 0, 0}, -+ -+#define SW6HWDISP (RETHINT + 1) -+ {12, 0, -SW6HWDISP, AXP_OPERAND_SIGNED, 0, 0}, -+ -+/* The 16-bit combined index/scoreboard mask for the sw6 -+ hw_m[ft]pr (pal19/pal1d) insns. */ -+#define SW6HWINDEX (SW6HWDISP + 1) -+ {16, 0, -SW6HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0}, -+ -+/* The 13-bit branch hint for the sw6 hw_jmp/jsr (pal1e) insn. */ -+#define SW6HWJMPHINT (SW6HWINDEX + 1) -+ {8, 0, -SW6HWJMPHINT, -+ AXP_OPERAND_RELATIVE | AXP_OPERAND_DEFAULT_ZERO | AXP_OPERAND_NOOVERFLOW, -+ insert_sw6hwjhint, extract_sw6hwjhint}, -+ -+/* for the third operand of ternary operands integer insn. */ -+#define R3 (SW6HWJMPHINT + 1) -+ {5, 5, 0, AXP_OPERAND_IR, 0, 0}, -+ -+/* The plain fp register fields. */ -+#define F3 (R3 + 1) -+ {5, 5, 0, AXP_OPERAND_FPR, 0, 0}, -+ -+/* sw simd settle instruction lit. */ -+#define FMALIT (F3 + 1) -+ {5, 5, -FMALIT, AXP_OPERAND_UNSIGNED, 0, 0}, // V1.1 -+ -+/* For pal to check disp which must be plus sign and less than 0x8000. */ -+#define LMDISP (FMALIT + 1) -+ {15, 0, -LMDISP, AXP_OPERAND_UNSIGNED, 0, 0}, -+ -+#define RPIINDEX (LMDISP + 1) -+ {8, 0, -RPIINDEX, AXP_OPERAND_UNSIGNED, 0, 0}, -+ -+#define ATMDISP (RPIINDEX + 1) -+ {12, 0, -ATMDISP, AXP_OPERAND_SIGNED, 0, 0}, -+ -+#define DISP13 (ATMDISP + 1) -+ {13, 13, -DISP13, AXP_OPERAND_SIGNED, 0, 0}, -+#define BDISP26 (DISP13 + 1) -+ {26, 0, BFD_RELOC_SW_64_BR26, AXP_OPERAND_RELATIVE, insert_bdisp26, -+ extract_bdisp26}, -+#define DPFTH (BDISP26 + 1) -+ {5, 21, -DPFTH, AXP_OPERAND_UNSIGNED, 0, 0}, -+/* Used by vshfqb. */ -+#define ZC2 (DPFTH + 1) -+ {5, 5, 0, AXP_OPERAND_FAKE, insert_zc2, extract_zc2}}; -+ -+const unsigned sw_64_num_operands -+ = sizeof (sw_64_operands) / sizeof (*sw_64_operands); -+ -+/* Macros used to form opcodes. */ -+ -+/* The main opcode. */ -+#define OP(x) (((x) &0x3Fu) << 26) -+#define OP_MASK 0xFC000000 -+ -+/* Branch format instructions. */ -+#define BRA_(oo) OP (oo) -+#define BRA_MASK OP_MASK -+#define BRA(oo) BRA_ (oo), BRA_MASK -+ -+/* Floating point format instructions. */ -+#define FP_(oo, fff) (OP (oo) | (((fff) &0xFF) << 5)) -+#define FP_MASK (OP_MASK | 0x1FE0) -+#define FP(oo, fff) FP_ (oo, fff), FP_MASK -+ -+#define FMA_(oo, fff) (OP (oo) | (((fff) &0x3F) << 10)) -+#define FMA_MASK (OP_MASK | 0xFC00) -+#define FMA(oo, fff) FMA_ (oo, fff), FMA_MASK -+ -+/* Memory format instructions. */ -+#define MEM_(oo) OP (oo) -+#define MEM_MASK OP_MASK -+#define MEM(oo) MEM_ (oo), MEM_MASK -+ -+/* Memory/Func Code format instructions. */ -+#define MFC_(oo, ffff) (OP (oo) | ((ffff) &0xFFFF)) -+#define MFC_MASK (OP_MASK | 0xFFFF) -+#define MFC(oo, ffff) MFC_ (oo, ffff), MFC_MASK -+ -+/* Memory/Branch format instructions. */ -+#define MBR_(oo, h) (OP (oo) | (((h) &3) << 14)) -+#define MBR_MASK (OP_MASK | 0xC000) -+#define MBR(oo, h) MBR_ (oo, h), MBR_MASK -+ -+/* Operate format instructions. The OPRL variant specifies a -+ literal second argument. */ -+#define OPR_(oo, ff) (OP (oo) | (((ff) &0xFF) << 5)) -+#define OPRL_(oo, ff) (OPR_ ((oo), (ff))) -+#define OPR_MASK (OP_MASK | 0x1FE0) -+#define OPR(oo, ff) OPR_ (oo, ff), OPR_MASK -+#define OPRL(oo, ff) OPRL_ (oo, ff), OPR_MASK -+ -+/* sw ternary operands Operate format instructions. */ -+#define TOPR_(oo, ff) (OP (oo) | (((ff) &0x07) << 10)) -+#define TOPRL_(oo, ff) (TOPR_ ((oo), (ff))) -+#define TOPR_MASK (OP_MASK | 0x1C00) -+#define TOPR(oo, ff) TOPR_ (oo, ff), TOPR_MASK -+#define TOPRL(oo, ff) TOPRL_ (oo, ff), TOPR_MASK -+ -+/* sw atom instructions. */ -+#define ATMEM_(oo, h) (OP (oo) | (((h) &0xF) << 12)) -+#define ATMEM_MASK (OP_MASK | 0xF000) -+#define ATMEM(oo, h) ATMEM_ (oo, h), ATMEM_MASK -+ -+/* sw privilege instructions. */ -+#define PRIRET_(oo, h) (OP (oo) | (((h) &0x1) << 20)) -+#define PRIRET_MASK (OP_MASK | 0x100000) -+#define PRIRET(oo, h) PRIRET_ (oo, h), PRIRET_MASK -+ -+/* sw rpi_rcsr,rpi_wcsr. */ -+#define CSR_(oo, ff) (OP (oo) | (((ff) &0xFF) << 8)) -+#define CSR_MASK (OP_MASK | 0xFF00) -+#define CSR(oo, ff) CSR_ (oo, ff), CSR_MASK -+ -+/* Generic PALcode format instructions. */ -+#define PCD_(oo, ff) (OP (oo) | (ff << 25)) -+#define PCD_MASK OP_MASK -+#define PCD(oo, ff) PCD_ (oo, ff), PCD_MASK -+ -+/* Specific PALcode instructions. */ -+#define SPCD_(oo, ffff) (OP (oo) | ((ffff) &0x3FFFFFF)) -+#define SPCD_MASK 0xFFFFFFFF -+#define SPCD(oo, ffff) SPCD_ (oo, ffff), SPCD_MASK -+ -+/* Hardware memory (hw_{ld,st}) instructions. */ -+#define SW6HWMEM_(oo, f) (OP (oo) | (((f) &0xF) << 12)) -+#define SW6HWMEM_MASK (OP_MASK | 0xF000) -+#define SW6HWMEM(oo, f) SW6HWMEM_ (oo, f), SW6HWMEM_MASK -+ -+#define SW6HWMBR_(oo, h) (OP (oo) | (((h) &7) << 13)) -+#define SW6HWMBR_MASK (OP_MASK | 0xE000) -+#define SW6HWMBR(oo, h) SW6HWMBR_ (oo, h), SW6HWMBR_MASK -+ -+#define LOGX_(oo, ff) (OP (oo) | (((ff) &0x3F) << 10)) -+#define LOGX_MASK (0xF0000000) -+#define LOGX(oo, ff) LOGX_ (oo, ff), LOGX_MASK -+ -+#define PSE_LOGX_(oo, ff) \ -+ (OP (oo) | (((ff) &0x3F) << 10) | (((ff) >> 0x6) << 26) | 0x3E0) -+#define PSE_LOGX(oo, ff) PSE_LOGX_ (oo, ff), LOGX_MASK -+ -+/* Abbreviations for instruction subsets. */ -+#define CORE3 AXP_OPCODE_SW6 -+#define CORE3A AXP_OPCODE_SW6A -+#define CORE3B AXP_OPCODE_SW6B -+#define CORE4A AXP_OPCODE_SW8A | AXP_OPCODE_SW4E -+/* Common combinations of arguments. */ -+#define ARG_NONE \ -+ { \ -+ 0 \ -+ } -+#define ARG_BRA \ -+ { \ -+ RA, BDISP \ -+ } -+#define ARG_FBRA \ -+ { \ -+ FA, BDISP \ -+ } -+#define ARG_FP \ -+ { \ -+ FA, FB, DFC1 \ -+ } -+#define ARG_FPZ1 \ -+ { \ -+ ZA, FB, DFC1 \ -+ } -+#define ARG_MEM \ -+ { \ -+ RA, MDISP, PRB \ -+ } -+#define ARG_FMEM \ -+ { \ -+ FA, MDISP, PRB \ -+ } -+#define ARG_OPR \ -+ { \ -+ RA, RB, DRC1 \ -+ } -+ -+#define ARG_OPRCAS \ -+ { \ -+ RA, RB, RC \ -+ } -+ -+#define ARG_OPRL \ -+ { \ -+ RA, LIT, DRC1 \ -+ } -+#define ARG_OPRZ1 \ -+ { \ -+ ZA, RB, DRC1 \ -+ } -+#define ARG_OPRLZ1 \ -+ { \ -+ ZA, LIT, RC \ -+ } -+#define ARG_PCD \ -+ { \ -+ PALFN \ -+ } -+#define ARG_SW6HWMEM \ -+ { \ -+ RA, SW6HWDISP, PRB \ -+ } -+ -+#define ARG_FPL \ -+ { \ -+ FA, LIT, DFC1 \ -+ } -+#define ARG_FMA \ -+ { \ -+ FA, FB, F3, DFC1 \ -+ } -+#define ARG_PREFETCH \ -+ { \ -+ ZA, MDISP, PRB \ -+ } -+#define ARG_FCMOV \ -+ { \ -+ FA, FB, F3, DFC3 \ -+ } -+#define ARG_TOPR \ -+ { \ -+ RA, RB, R3, DRC3 \ -+ } -+#define ARG_TOPRL \ -+ { \ -+ RA, LIT, R3, DRC3 \ -+ } -+ -+/* for cmov** instruction. */ -+#define ARG_TOPC \ -+ { \ -+ RA, RB, R3, RDC \ -+ } -+#define ARG_TOPCL \ -+ { \ -+ RA, LIT, R3, RDC \ -+ } -+#define ARG_TOPFC \ -+ { \ -+ FA, FB, F3, RDC \ -+ } -+#define ARG_TOPFCL \ -+ { \ -+ FA, LIT, F3, RDC \ -+ } -+ -+/* sw settle instruction. */ -+#define ARG_FMAL \ -+ { \ -+ FA, FB, FMALIT, DFC1 \ -+ } -+/* sw atom insitruction. */ -+#define ARG_ATMEM \ -+ { \ -+ RA, ATMDISP, PRB \ -+ } -+ -+#define ARG_VUAMEM \ -+ { \ -+ FA, ATMDISP, PRB \ -+ } -+#define ARG_OPRLZ3 \ -+ { \ -+ RA, LIT, ZC \ -+ } -+ -+#define ARG_DISP13 \ -+ { \ -+ DISP13, RC \ -+ } -+ -+/* The opcode table. -+ -+ The format of the opcode table is: -+ -+ NAME OPCODE MASK { OPERANDS } -+ -+ NAME is the name of the instruction. -+ -+ OPCODE is the instruction opcode. -+ -+ MASK is the opcode mask; this is used to tell the disassembler -+ which bits in the actual opcode must match OPCODE. -+ -+ OPERANDS is the list of operands. -+ -+ The preceding macros merge the text of the OPCODE and MASK fields. -+ -+ The disassembler reads the table in order and prints the first -+ instruction which matches, so this table is sorted to put more -+ specific instructions before more general instructions. -+ -+ Otherwise, it is sorted by major opcode and minor function code. -+ -+ There are three classes of not-really-instructions in this table: -+ -+ ALIAS is another name for another instruction. Some of -+ these come from the Architecture Handbook, some -+ come from the original gas opcode tables. In all -+ cases, the functionality of the opcode is unchanged. -+ -+ PSEUDO a stylized code form endorsed by Chapter A.4 of the -+ Architecture Handbook. -+ -+ EXTRA a stylized code form found in the original gas tables. -+ */ -+ -+const struct sw_64_opcode sw_64_opcodes[] = { -+ {"sys_call/b", PCD (0x00, 0x00), CORE3, ARG_PCD}, -+ {"sys_call", PCD (0x00, 0x01), CORE3, ARG_PCD}, -+ {"draina", SPCD (0x00, 0x0002), CORE3, ARG_NONE}, -+ {"bpt", SPCD (0x00, 0x0080), CORE3, ARG_NONE}, -+ {"bugchk", SPCD (0x00, 0x0081), CORE3, ARG_NONE}, -+ {"callsys", SPCD (0x00, 0x0083), CORE3, ARG_NONE}, -+ {"chmk", SPCD (0x00, 0x0083), CORE3, ARG_NONE}, -+ {"imb", SPCD (0x00, 0x0086), CORE3, ARG_NONE}, -+ {"rduniq", SPCD (0x00, 0x009e), CORE3, ARG_NONE}, -+ {"wruniq", SPCD (0x00, 0x009f), CORE3, ARG_NONE}, -+ {"gentrap", SPCD (0x00, 0x00aa), CORE3, ARG_NONE}, -+ {"call", MEM (0x01), CORE3, {RA, CPRB, JMPHINT}}, -+ {"ret", MEM (0x02), CORE3, {RA, CPRB, RETHINT}}, -+ {"ret", -+ MEM_ (0x02) | (31 << 21) | (26 << 16) | 1, -+ 0xFFFFFFFF, -+ CORE3, -+ {0}}, /*pseudo*/ -+ {"jmp", MEM (0x03), CORE3, {RA, CPRB, JMPHINT}}, -+ {"br", BRA (0x04), CORE3, {ZA, BDISP}}, /* pseudo */ -+ {"br", BRA (0x04), CORE3, ARG_BRA}, -+ {"bsr", BRA (0x05), CORE3, ARG_BRA}, -+ {"memb", MFC (0x06, 0x0000), CORE3, ARG_NONE}, -+ {"imemb", MFC (0x06, 0x0001), CORE3, ARG_NONE}, -+ {"wmemb", MFC (0x06, 0x0002), CORE4A, ARG_NONE}, -+ {"rtc", MFC (0x06, 0x0020), CORE3, {RA, ZB}}, -+ {"rtc", MFC (0x06, 0x0020), CORE3, {RA, RB}}, -+ {"rcid", MFC (0x06, 0x0040), CORE3, {RA, ZB}}, -+ {"halt", MFC (0x06, 0x0080), CORE3, {ZA, ZB}}, -+ {"rd_f", MFC (0x06, 0x1000), CORE3, {RA, ZB}}, -+ {"wr_f", MFC (0x06, 0x1020), CORE3, {RA, ZB}}, -+ {"rtid", MFC (0x06, 0x1040), CORE3, {RA}}, -+ {"pri_rcsr", CSR (0x06, 0xFE), CORE3, {RA, RPIINDEX, ZB}}, -+ {"pri_wcsr", CSR (0x06, 0xFF), CORE3, {RA, RPIINDEX, ZB}}, -+ {"csrws", CSR (0x06, 0xFC), CORE4A, {RA, RPIINDEX, ZB}}, -+ {"csrwc", CSR (0x06, 0xFD), CORE4A, {RA, RPIINDEX, ZB}}, -+ {"csrr", CSR (0x06, 0xFE), CORE4A, {RA, RPIINDEX, ZB}}, -+ {"csrw", CSR (0x06, 0xFF), CORE4A, {RA, RPIINDEX, ZB}}, -+ {"pri_ret", PRIRET (0x07, 0x0), CORE3, {RA}}, -+ {"pri_ret/b", PRIRET (0x07, 0x1), CORE3, {RA}}, -+ {"lldw", ATMEM (0x08, 0x0), CORE3, ARG_ATMEM}, -+ {"lldl", ATMEM (0x08, 0x1), CORE3, ARG_ATMEM}, -+ {"ldw_inc", ATMEM (0x08, 0x2), CORE3, ARG_ATMEM}, -+ {"ldl_inc", ATMEM (0x08, 0x3), CORE3, ARG_ATMEM}, -+ {"ldw_dec", ATMEM (0x08, 0x4), CORE3, ARG_ATMEM}, -+ {"ldl_dec", ATMEM (0x08, 0x5), CORE3, ARG_ATMEM}, -+ {"ldw_set", ATMEM (0x08, 0x6), CORE3, ARG_ATMEM}, -+ {"ldl_set", ATMEM (0x08, 0x7), CORE3, ARG_ATMEM}, -+ {"lstw", ATMEM (0x08, 0x8), CORE3, ARG_ATMEM}, -+ {"lstl", ATMEM (0x08, 0x9), CORE3, ARG_ATMEM}, -+ {"ldw_nc", ATMEM (0x08, 0xA), CORE3, ARG_ATMEM}, -+ {"ldl_nc", ATMEM (0x08, 0xB), CORE3, ARG_ATMEM}, -+ {"ldd_nc", ATMEM (0x08, 0xC), CORE3, ARG_VUAMEM}, -+ {"stw_nc", ATMEM (0x08, 0xD), CORE3, ARG_ATMEM}, -+ {"stl_nc", ATMEM (0x08, 0xE), CORE3, ARG_ATMEM}, -+ {"std_nc", ATMEM (0x08, 0xF), CORE3, ARG_VUAMEM}, -+ {"fillcs", MEM (0x09), CORE3, ARG_PREFETCH}, -+ {"ldwe", MEM (0x09), CORE3, ARG_FMEM}, // CORE3 v0.2a -+ {"e_fillcs", MEM (0x0A), CORE3, ARG_PREFETCH}, -+ {"ldse", MEM (0x0A), CORE3, ARG_FMEM}, -+ {"lds4e", MEM (0x0A), CORE3, ARG_FMEM}, /* pseudo CORE3 SIMD */ -+ {"fillcs_e", MEM (0x0B), CORE3, ARG_PREFETCH}, -+ {"ldde", MEM (0x0B), CORE3, ARG_FMEM}, -+ {"ldd4e", MEM (0x0B), CORE3, ARG_FMEM}, /* pseudo CORE3 SIMD */ -+ {"e_fillde", MEM (0x0C), CORE3, ARG_PREFETCH}, -+ {"vlds", MEM (0x0C), CORE3, ARG_FMEM}, -+ {"v4lds", MEM (0x0C), CORE3, ARG_FMEM}, -+ {"vldd", MEM (0x0D), CORE3, ARG_FMEM}, -+ {"v4ldd", MEM (0x0D), CORE3, ARG_FMEM}, -+ {"vsts", MEM (0x0E), CORE3, ARG_FMEM}, -+ {"v4sts", MEM (0x0E), CORE3, ARG_FMEM}, -+ {"vstd", MEM (0x0F), CORE3, ARG_FMEM}, -+ {"v4std", MEM (0x0F), CORE3, ARG_FMEM}, -+ {"addw", OPR (0x10, 0x00), CORE3, ARG_OPR}, -+ {"addw", OPRL (0x12, 0x00), CORE3, ARG_OPRL}, -+ {"sextl", OPR (0x10, 0x00), CORE3, ARG_OPRZ1}, /* pseudo */ -+ {"sextl", OPRL (0x12, 0x00), CORE3, ARG_OPRLZ1}, /* pseudo */ -+ {"subw", OPR (0x10, 0x01), CORE3, ARG_OPR}, -+ {"subw", OPRL (0x12, 0x01), CORE3, ARG_OPRL}, -+ {"negw", OPR (0x10, 0x01), CORE3, ARG_OPRZ1}, /* pseudo swgcc */ -+ {"negw", OPRL (0x12, 0x01), CORE3, ARG_OPRLZ1}, /* pseudo swgcc */ -+ {"s4addw", OPR (0x10, 0x02), CORE3, ARG_OPR}, -+ {"s4addw", OPRL (0x12, 0x02), CORE3, ARG_OPRL}, -+ {"s4subw", OPR (0x10, 0x03), CORE3, ARG_OPR}, -+ {"s4subw", OPRL (0x12, 0x03), CORE3, ARG_OPRL}, -+ {"s8addw", OPR (0x10, 0x04), CORE3, ARG_OPR}, -+ {"s8addw", OPRL (0x12, 0x04), CORE3, ARG_OPRL}, -+ {"s8subw", OPR (0x10, 0x05), CORE3, ARG_OPR}, -+ {"s8subw", OPRL (0x12, 0x05), CORE3, ARG_OPRL}, -+ {"addl", OPR (0x10, 0x08), CORE3, ARG_OPR}, -+ {"addl", OPRL (0x12, 0x08), CORE3, ARG_OPRL}, -+ {"subl", OPR (0x10, 0x09), CORE3, ARG_OPR}, -+ {"subl", OPRL (0x12, 0x09), CORE3, ARG_OPRL}, -+ {"negl", OPR (0x10, 0x09), CORE3, ARG_OPRZ1}, /* pseudo swgcc */ -+ {"negl", OPRL (0x12, 0x09), CORE3, ARG_OPRLZ1}, /* pseudo swgcc */ -+ {"neglv", OPR (0x10, 0x09), CORE3, ARG_OPRZ1}, /* pseudo swgcc */ -+ {"neglv", OPRL (0x12, 0x09), CORE3, ARG_OPRLZ1}, /* pseudo swgcc */ -+ {"s4addl", OPR (0x10, 0x0A), CORE3, ARG_OPR}, -+ {"s4addl", OPRL (0x12, 0x0A), CORE3, ARG_OPRL}, -+ {"s4subl", OPR (0x10, 0x0B), CORE3, ARG_OPR}, -+ {"s4subl", OPRL (0x12, 0x0B), CORE3, ARG_OPRL}, -+ {"s8addl", OPR (0x10, 0x0C), CORE3, ARG_OPR}, -+ {"s8addl", OPRL (0x12, 0x0C), CORE3, ARG_OPRL}, -+ {"s8subl", OPR (0x10, 0x0D), CORE3, ARG_OPR}, -+ {"s8subl", OPRL (0x12, 0x0D), CORE3, ARG_OPRL}, -+ {"mulw", OPR (0x10, 0x10), CORE3, ARG_OPR}, -+ {"mulw", OPRL (0x12, 0x10), CORE3, ARG_OPRL}, -+ {"divw", OPR (0x10, 0x11), CORE4A, ARG_OPR}, -+ {"udivw", OPR (0x10, 0x12), CORE4A, ARG_OPR}, -+ {"remw", OPR (0x10, 0x13), CORE4A, ARG_OPR}, -+ {"uremw", OPR (0x10, 0x14), CORE4A, ARG_OPR}, -+ {"mull", OPR (0x10, 0x18), CORE3, ARG_OPR}, -+ {"mull", OPRL (0x12, 0x18), CORE3, ARG_OPRL}, -+ {"umulh", OPR (0x10, 0x19), CORE3, ARG_OPR}, -+ {"umulh", OPRL (0x12, 0x19), CORE3, ARG_OPRL}, -+ {"divl", OPR (0x10, 0x1A), CORE4A, ARG_OPR}, -+ {"udivl", OPR (0x10, 0x1B), CORE4A, ARG_OPR}, -+ {"reml", OPR (0x10, 0x1C), CORE4A, ARG_OPR}, -+ {"ureml", OPR (0x10, 0x1D), CORE4A, ARG_OPR}, -+ {"addpi", OPR (0x10, 0x1E), CORE4A, ARG_DISP13}, -+ {"addpis", OPR (0x10, 0x1F), CORE4A, ARG_DISP13}, -+ {"crc32b", OPR (0x10, 0x20), CORE4A, ARG_OPR}, -+ {"crc32h", OPR (0x10, 0x21), CORE4A, ARG_OPR}, -+ {"crc32w", OPR (0x10, 0x22), CORE4A, ARG_OPR}, -+ {"crc32l", OPR (0x10, 0x23), CORE4A, ARG_OPR}, -+ {"crc32cb", OPR (0x10, 0x24), CORE4A, ARG_OPR}, -+ {"crc32ch", OPR (0x10, 0x25), CORE4A, ARG_OPR}, -+ {"crc32cw", OPR (0x10, 0x26), CORE4A, ARG_OPR}, -+ {"crc32cl", OPR (0x10, 0x27), CORE4A, ARG_OPR}, -+ {"cmpeq", OPR (0x10, 0x28), CORE3, ARG_OPR}, -+ {"cmpeq", OPRL (0x12, 0x28), CORE3, ARG_OPRL}, -+ {"cmplt", OPR (0x10, 0x29), CORE3, ARG_OPR}, -+ {"cmplt", OPRL (0x12, 0x29), CORE3, ARG_OPRL}, -+ {"cmple", OPR (0x10, 0x2A), CORE3, ARG_OPR}, -+ {"cmple", OPRL (0x12, 0x2A), CORE3, ARG_OPRL}, -+ {"cmpult", OPR (0x10, 0x2B), CORE3, ARG_OPR}, -+ {"cmpult", OPRL (0x12, 0x2B), CORE3, ARG_OPRL}, -+ {"cmpule", OPR (0x10, 0x2C), CORE3, ARG_OPR}, -+ {"cmpule", OPRL (0x12, 0x2C), CORE3, ARG_OPRL}, -+ {"sbt", OPR (0x10, 0x2D), CORE4A, ARG_OPR}, -+ {"sbt", OPRL (0x12, 0x2D), CORE4A, ARG_OPRL}, -+ {"cbt", OPR (0x10, 0x2E), CORE4A, ARG_OPR}, -+ {"cbt", OPRL (0x12, 0x2E), CORE4A, ARG_OPRL}, -+ {"and", OPR (0x10, 0x38), CORE3, ARG_OPR}, -+ {"and", OPRL (0x12, 0x38), CORE3, ARG_OPRL}, -+ {"bic", OPR (0x10, 0x39), CORE3, ARG_OPR}, -+ {"bic", OPRL (0x12, 0x39), CORE3, ARG_OPRL}, -+ {"andnot", OPR (0x10, 0x39), CORE3, ARG_OPR}, /* pseudo */ -+ {"andnot", OPRL (0x12, 0x39), CORE3, ARG_OPRL}, /* pseudo */ -+ {"nop", -+ OPR (0x10, 0x3A), -+ CORE3, -+ {ZA, ZB, ZC}}, /* Now unop has a new expression. */ -+ {"excb", OPR (0x10, 0x3A), CORE3, {ZA, ZB, ZC}}, /* pseudo */ -+ {"clr", OPR (0x10, 0x3A), CORE3, {ZA, ZB, RC}}, /* pseudo swgcc */ -+ {"mov", OPR (0x10, 0x3A), CORE3, {ZA, RB, RC}}, /* pseudo */ -+ {"mov", OPRL (0x12, 0x3A), CORE3, {ZA, LIT, RC}}, /* pseudo */ -+ {"implver", -+ OPRL_ (0x12, 0x3A) | 2 << 13, -+ 0xFFFFFFE0, -+ CORE3, -+ {ZA, RC}}, /* pseudo swgcc */ -+ {"amask", -+ OPR_ (0x10, 0x3A) | 31 << 16, -+ OPR_MASK, -+ CORE3, -+ {ZA, RB, RC}}, /* pseudo */ -+ {"amask", OPRL (0x12, 0x3A), CORE3, {ZA, LIT, RC}}, /* pseudo */ -+ {"or", OPR (0x10, 0x3A), CORE3, ARG_OPR}, -+ {"or", OPRL (0x12, 0x3A), CORE3, ARG_OPRL}, -+ {"bis", OPR (0x10, 0x3A), CORE3, ARG_OPR}, -+ {"bis", OPRL (0x12, 0x3A), CORE3, ARG_OPRL}, -+ {"not", OPR (0x10, 0x3B), CORE3, ARG_OPRZ1}, /* pseudo swgcc */ -+ {"not", OPRL (0x12, 0x3B), CORE3, ARG_OPRLZ1}, /* pseudo swgcc */ -+ {"ornot", OPR (0x10, 0x3B), CORE3, ARG_OPR}, -+ {"ornot", OPRL (0x12, 0x3B), CORE3, ARG_OPRL}, -+ {"xor", OPR (0x10, 0x3C), CORE3, ARG_OPR}, -+ {"xor", OPRL (0x12, 0x3C), CORE3, ARG_OPRL}, -+ {"eqv", OPR (0x10, 0x3D), CORE3, ARG_OPR}, -+ {"eqv", OPRL (0x12, 0x3D), CORE3, ARG_OPRL}, -+ {"xornot", OPR (0x10, 0x3D), CORE3, ARG_OPR}, /* pseudo swgcc */ -+ {"xornot", OPRL (0x12, 0x3D), CORE3, ARG_OPRL}, /* pseudo swgcc */ -+ {"inslb", OPR (0x10, 0x40), CORE3, ARG_OPR}, -+ {"inslb", OPRL (0x12, 0x40), CORE3, ARG_OPRL}, -+ {"ins0b", OPR (0x10, 0x40), CORE3, ARG_OPR}, -+ {"ins0b", OPRL (0x12, 0x40), CORE3, ARG_OPRL}, -+ {"inslh", OPR (0x10, 0x41), CORE3, ARG_OPR}, -+ {"inslh", OPRL (0x12, 0x41), CORE3, ARG_OPRL}, -+ {"ins1b", OPR (0x10, 0x41), CORE3, ARG_OPR}, -+ {"ins1b", OPRL (0x12, 0x41), CORE3, ARG_OPRL}, -+ {"inslw", OPR (0x10, 0x42), CORE3, ARG_OPR}, -+ {"inslw", OPRL (0x12, 0x42), CORE3, ARG_OPRL}, -+ {"ins2b", OPR (0x10, 0x42), CORE3, ARG_OPR}, -+ {"ins2b", OPRL (0x12, 0x42), CORE3, ARG_OPRL}, -+ {"insll", OPR (0x10, 0x43), CORE3, ARG_OPR}, -+ {"insll", OPRL (0x12, 0x43), CORE3, ARG_OPRL}, -+ {"ins3b", OPR (0x10, 0x43), CORE3, ARG_OPR}, -+ {"ins3b", OPRL (0x12, 0x43), CORE3, ARG_OPRL}, -+ {"inshb", OPR (0x10, 0x44), CORE3, ARG_OPR}, -+ {"inshb", OPRL (0x12, 0x44), CORE3, ARG_OPRL}, -+ {"ins4b", OPR (0x10, 0x44), CORE3, ARG_OPR}, -+ {"ins4b", OPRL (0x12, 0x44), CORE3, ARG_OPRL}, -+ {"inshh", OPR (0x10, 0x45), CORE3, ARG_OPR}, -+ {"inshh", OPRL (0x12, 0x45), CORE3, ARG_OPRL}, -+ {"ins5b", OPR (0x10, 0x45), CORE3, ARG_OPR}, -+ {"ins5b", OPRL (0x12, 0x45), CORE3, ARG_OPRL}, -+ {"inshw", OPR (0x10, 0x46), CORE3, ARG_OPR}, -+ {"inshw", OPRL (0x12, 0x46), CORE3, ARG_OPRL}, -+ {"ins6b", OPR (0x10, 0x46), CORE3, ARG_OPR}, -+ {"ins6b", OPRL (0x12, 0x46), CORE3, ARG_OPRL}, -+ {"inshl", OPR (0x10, 0x47), CORE3, ARG_OPR}, -+ {"inshl", OPRL (0x12, 0x47), CORE3, ARG_OPRL}, -+ {"ins7b", OPR (0x10, 0x47), CORE3, ARG_OPR}, -+ {"ins7b", OPRL (0x12, 0x47), CORE3, ARG_OPRL}, -+ {"slll", OPR (0x10, 0x48), CORE4A, ARG_OPR}, -+ {"slll", OPRL (0x12, 0x48), CORE4A, ARG_OPRL}, -+ {"srll", OPR (0x10, 0x49), CORE4A, ARG_OPR}, -+ {"srll", OPRL (0x12, 0x49), CORE4A, ARG_OPRL}, -+ {"sral", OPR (0x10, 0x4A), CORE4A, ARG_OPR}, -+ {"sral", OPRL (0x12, 0x4A), CORE4A, ARG_OPRL}, -+ {"roll", OPR (0x10, 0x4B), CORE4A, ARG_OPR}, -+ {"roll", OPRL (0x12, 0x4B), CORE4A, ARG_OPRL}, -+ {"sllw", OPR (0x10, 0x4C), CORE4A, ARG_OPR}, -+ {"sllw", OPRL (0x12, 0x4C), CORE4A, ARG_OPRL}, -+ {"srlw", OPR (0x10, 0x4D), CORE4A, ARG_OPR}, -+ {"srlw", OPRL (0x12, 0x4D), CORE4A, ARG_OPRL}, -+ {"sraw", OPR (0x10, 0x4E), CORE4A, ARG_OPR}, -+ {"sraw", OPRL (0x12, 0x4E), CORE4A, ARG_OPRL}, -+ {"rolw", OPR (0x10, 0x4F), CORE4A, ARG_OPR}, -+ {"rolw", OPRL (0x12, 0x4F), CORE4A, ARG_OPRL}, -+ {"sll", OPR (0x10, 0x48), CORE3, ARG_OPR}, -+ {"sll", OPRL (0x12, 0x48), CORE3, ARG_OPRL}, -+ {"srl", OPR (0x10, 0x49), CORE3, ARG_OPR}, -+ {"srl", OPRL (0x12, 0x49), CORE3, ARG_OPRL}, -+ {"sra", OPR (0x10, 0x4A), CORE3, ARG_OPR}, -+ {"sra", OPRL (0x12, 0x4A), CORE3, ARG_OPRL}, -+ {"sllw2", OPR (0x10, 0x4C), CORE3, ARG_OPR}, // CORE3 v0.2a -+ {"sllw2", OPRL (0x12, 0x4C), CORE3, ARG_OPRL}, // CORE3 v0.2a -+ {"srlw2", OPR (0x10, 0x4D), CORE3, ARG_OPR}, // CORE3 v0.2a -+ {"srlw2", OPRL (0x12, 0x4D), CORE3, ARG_OPRL}, // CORE3 v0.2a -+ {"sraw2", OPR (0x10, 0x4E), CORE3, ARG_OPR}, // CORE3 v0.2a -+ {"sraw2", OPRL (0x12, 0x4E), CORE3, ARG_OPRL}, // CORE3 v0.2a -+ {"extlb", OPR (0x10, 0x50), CORE3, ARG_OPR}, -+ {"extlb", OPRL (0x12, 0x50), CORE3, ARG_OPRL}, -+ {"ext0b", OPR (0x10, 0x50), CORE3, ARG_OPR}, -+ {"ext0b", OPRL (0x12, 0x50), CORE3, ARG_OPRL}, -+ {"extlh", OPR (0x10, 0x51), CORE3, ARG_OPR}, -+ {"extlh", OPRL (0x12, 0x51), CORE3, ARG_OPRL}, -+ {"ext1b", OPR (0x10, 0x51), CORE3, ARG_OPR}, -+ {"ext1b", OPRL (0x12, 0x51), CORE3, ARG_OPRL}, -+ {"extlw", OPR (0x10, 0x52), CORE3, ARG_OPR}, -+ {"extlw", OPRL (0x12, 0x52), CORE3, ARG_OPRL}, -+ {"ext2b", OPR (0x10, 0x52), CORE3, ARG_OPR}, -+ {"ext2b", OPRL (0x12, 0x52), CORE3, ARG_OPRL}, -+ {"extll", OPR (0x10, 0x53), CORE3, ARG_OPR}, -+ {"extll", OPRL (0x12, 0x53), CORE3, ARG_OPRL}, -+ {"ext3b", OPR (0x10, 0x53), CORE3, ARG_OPR}, -+ {"ext3b", OPRL (0x12, 0x53), CORE3, ARG_OPRL}, -+ {"exthb", OPR (0x10, 0x54), CORE3, ARG_OPR}, -+ {"exthb", OPRL (0x12, 0x54), CORE3, ARG_OPRL}, -+ {"ext4b", OPR (0x10, 0x54), CORE3, ARG_OPR}, -+ {"ext4b", OPRL (0x12, 0x54), CORE3, ARG_OPRL}, -+ {"exthh", OPR (0x10, 0x55), CORE3, ARG_OPR}, -+ {"exthh", OPRL (0x12, 0x55), CORE3, ARG_OPRL}, -+ {"ext5b", OPR (0x10, 0x55), CORE3, ARG_OPR}, -+ {"ext5b", OPRL (0x12, 0x55), CORE3, ARG_OPRL}, -+ {"exthw", OPR (0x10, 0x56), CORE3, ARG_OPR}, -+ {"exthw", OPRL (0x12, 0x56), CORE3, ARG_OPRL}, -+ {"ext6b", OPR (0x10, 0x56), CORE3, ARG_OPR}, -+ {"ext6b", OPRL (0x12, 0x56), CORE3, ARG_OPRL}, -+ {"exthl", OPR (0x10, 0x57), CORE3, ARG_OPR}, -+ {"exthl", OPRL (0x12, 0x57), CORE3, ARG_OPRL}, -+ {"ext7b", OPR (0x10, 0x57), CORE3, ARG_OPR}, -+ {"ext7b", OPRL (0x12, 0x57), CORE3, ARG_OPRL}, -+ {"ctpop", OPR (0x10, 0x58), CORE3, ARG_OPRZ1}, -+ {"ctlz", OPR (0x10, 0x59), CORE3, ARG_OPRZ1}, -+ {"cttz", OPR (0x10, 0x5A), CORE3, ARG_OPRZ1}, -+ {"revbh", OPR (0x10, 0x5B), CORE4A, ARG_OPRZ1}, -+ {"revbw", OPR (0x10, 0x5C), CORE4A, ARG_OPRZ1}, -+ {"revbl", OPR (0x10, 0x5D), CORE4A, ARG_OPRZ1}, -+ {"casw", OPR (0x10, 0x5E), CORE4A, ARG_OPRCAS}, -+ {"casl", OPR (0x10, 0x5F), CORE4A, ARG_OPRCAS}, -+ {"masklb", OPR (0x10, 0x60), CORE3, ARG_OPR}, -+ {"masklb", OPRL (0x12, 0x60), CORE3, ARG_OPRL}, -+ {"mask0b", OPR (0x10, 0x60), CORE3, ARG_OPR}, -+ {"mask0b", OPRL (0x12, 0x60), CORE3, ARG_OPRL}, -+ {"masklh", OPR (0x10, 0x61), CORE3, ARG_OPR}, -+ {"masklh", OPRL (0x12, 0x61), CORE3, ARG_OPRL}, -+ {"mask1b", OPR (0x10, 0x61), CORE3, ARG_OPR}, -+ {"mask1b", OPRL (0x12, 0x61), CORE3, ARG_OPRL}, -+ {"masklw", OPR (0x10, 0x62), CORE3, ARG_OPR}, -+ {"masklw", OPRL (0x12, 0x62), CORE3, ARG_OPRL}, -+ {"mask2b", OPR (0x10, 0x62), CORE3, ARG_OPR}, -+ {"mask2b", OPRL (0x12, 0x62), CORE3, ARG_OPRL}, -+ {"maskll", OPR (0x10, 0x63), CORE3, ARG_OPR}, -+ {"maskll", OPRL (0x12, 0x63), CORE3, ARG_OPRL}, -+ {"mask3b", OPR (0x10, 0x63), CORE3, ARG_OPR}, -+ {"mask3b", OPRL (0x12, 0x63), CORE3, ARG_OPRL}, -+ {"maskhb", OPR (0x10, 0x64), CORE3, ARG_OPR}, -+ {"maskhb", OPRL (0x12, 0x64), CORE3, ARG_OPRL}, -+ {"mask4b", OPR (0x10, 0x64), CORE3, ARG_OPR}, -+ {"mask4b", OPRL (0x12, 0x64), CORE3, ARG_OPRL}, -+ {"maskhh", OPR (0x10, 0x65), CORE3, ARG_OPR}, -+ {"maskhh", OPRL (0x12, 0x65), CORE3, ARG_OPRL}, -+ {"mask5b", OPR (0x10, 0x65), CORE3, ARG_OPR}, -+ {"mask5b", OPRL (0x12, 0x65), CORE3, ARG_OPRL}, -+ {"maskhw", OPR (0x10, 0x66), CORE3, ARG_OPR}, -+ {"maskhw", OPRL (0x12, 0x66), CORE3, ARG_OPRL}, -+ {"mask6b", OPR (0x10, 0x66), CORE3, ARG_OPR}, -+ {"mask6b", OPRL (0x12, 0x66), CORE3, ARG_OPRL}, -+ {"maskhl", OPR (0x10, 0x67), CORE3, ARG_OPR}, -+ {"maskhl", OPRL (0x12, 0x67), CORE3, ARG_OPRL}, -+ {"mask7b", OPR (0x10, 0x67), CORE3, ARG_OPR}, -+ {"mask7b", OPRL (0x12, 0x67), CORE3, ARG_OPRL}, -+ {"zap", OPR (0x10, 0x68), CORE3, ARG_OPR}, -+ {"zap", OPRL (0x12, 0x68), CORE3, ARG_OPRL}, -+ {"zapnot", OPR (0x10, 0x69), CORE3, ARG_OPR}, -+ {"zapnot", OPRL (0x12, 0x69), CORE3, ARG_OPRL}, -+ {"sextb", OPR (0x10, 0x6A), CORE3, ARG_OPRZ1}, -+ {"sextb", OPRL (0x12, 0x6A), CORE3, ARG_OPRLZ1}, -+ {"sexth", OPR (0x10, 0x6B), CORE3, ARG_OPRZ1}, -+ {"sexth", OPRL (0x12, 0x6B), CORE3, ARG_OPRLZ1}, -+ {"cmpgeb", OPR (0x10, 0x6C), CORE3, ARG_OPR}, -+ {"cmpgeb", OPRL (0x12, 0x6C), CORE3, ARG_OPRL}, -+ {"fimovs", OPR (0x10, 0x70), CORE3, {FA, ZB, RC}}, -+ {"cmovdl", OPR (0x10, 0x72), CORE4A, {ZA, FB, RC}}, -+ {"cmovdl_g", OPR (0x10, 0x74), CORE4A, {ZA, FB, RC}}, -+ {"fimovd", OPR (0x10, 0x78), CORE3, {FA, ZB, RC}}, -+ {"ftoid", OPR (0x10, 0x78), CORE3, {FA, ZB, RC}}, -+ {"cmovdl_p", OPR (0x10, 0x7a), CORE4A, {ZA, FB, RC}}, -+ {"cmovdl_z", OPR (0x10, 0x7c), CORE4A, {ZA, FB, RC}}, -+ {"cmovdl_n", OPR (0x10, 0x80), CORE4A, {ZA, FB, RC}}, -+ {"cmovdlu", OPR (0x10, 0x81), CORE4A, {ZA, FB, RC}}, -+ {"cmovdlu_g", OPR (0x10, 0x82), CORE4A, {ZA, FB, RC}}, -+ {"cmovdlu_p", OPR (0x10, 0x83), CORE4A, {ZA, FB, RC}}, -+ {"cmovdlu_z", OPR (0x10, 0x84), CORE4A, {ZA, FB, RC}}, -+ {"cmovdlu_n", OPR (0x10, 0x85), CORE4A, {ZA, FB, RC}}, -+ {"cmovdwu", OPR (0x10, 0x86), CORE4A, {ZA, FB, RC}}, -+ {"cmovdwu_g", OPR (0x10, 0x87), CORE4A, {ZA, FB, RC}}, -+ {"cmovdwu_p", OPR (0x10, 0x88), CORE4A, {ZA, FB, RC}}, -+ {"cmovdwu_z", OPR (0x10, 0x89), CORE4A, {ZA, FB, RC}}, -+ {"cmovdwu_n", OPR (0x10, 0x8a), CORE4A, {ZA, FB, RC}}, -+ {"cmovdw", OPR (0x10, 0x8b), CORE4A, {ZA, FB, RC}}, -+ {"cmovdw_g", OPR (0x10, 0x8c), CORE4A, {ZA, FB, RC}}, -+ {"cmovdw_p", OPR (0x10, 0x8d), CORE4A, {ZA, FB, RC}}, -+ {"cmovdw_z", OPR (0x10, 0x8e), CORE4A, {ZA, FB, RC}}, -+ {"cmovdw_n", OPR (0x10, 0x8f), CORE4A, {ZA, FB, RC}}, -+ {"seleq", TOPR (0x11, 0x0), CORE3, ARG_TOPR}, -+ {"seleq", TOPRL (0x13, 0x0), CORE3, ARG_TOPRL}, -+ {"selge", TOPR (0x11, 0x1), CORE3, ARG_TOPR}, -+ {"selge", TOPRL (0x13, 0x1), CORE3, ARG_TOPRL}, -+ {"selgt", TOPR (0x11, 0x2), CORE3, ARG_TOPR}, -+ {"selgt", TOPRL (0x13, 0x2), CORE3, ARG_TOPRL}, -+ {"selle", TOPR (0x11, 0x3), CORE3, ARG_TOPR}, -+ {"selle", TOPRL (0x13, 0x3), CORE3, ARG_TOPRL}, -+ {"sellt", TOPR (0x11, 0x4), CORE3, ARG_TOPR}, -+ {"sellt", TOPRL (0x13, 0x4), CORE3, ARG_TOPRL}, -+ {"selne", TOPR (0x11, 0x5), CORE3, ARG_TOPR}, -+ {"selne", TOPRL (0x13, 0x5), CORE3, ARG_TOPRL}, -+ {"sellbc", TOPR (0x11, 0x6), CORE3, ARG_TOPR}, -+ {"sellbc", TOPRL (0x13, 0x6), CORE3, ARG_TOPRL}, -+ {"sellbs", TOPR (0x11, 0x7), CORE3, ARG_TOPR}, -+ {"sellbs", TOPRL (0x13, 0x7), CORE3, ARG_TOPRL}, -+ {"vlog", LOGX (0x14, 0x00), CORE3, ARG_FMA}, -+ -+ {"vbicw", PSE_LOGX (0x14, 0x30), CORE3, {FA, FB, DFC1}}, -+ {"vxorw", PSE_LOGX (0x14, 0x3c), CORE3, {FA, FB, DFC1}}, -+ {"vandw", PSE_LOGX (0x14, 0xc0), CORE3, {FA, FB, DFC1}}, -+ {"veqvw", PSE_LOGX (0x14, 0xc3), CORE3, {FA, FB, DFC1}}, -+ {"vornotw", PSE_LOGX (0x14, 0xf3), CORE3, {FA, FB, DFC1}}, -+ {"vbisw", PSE_LOGX (0x14, 0xfc), CORE3, {FA, FB, DFC1}}, -+ -+ {"fadds", FP (0x18, 0x00), CORE3, ARG_FP}, -+ {"faddd", FP (0x18, 0x01), CORE3, ARG_FP}, -+ {"fsubs", FP (0x18, 0x02), CORE3, ARG_FP}, -+ {"fsubd", FP (0x18, 0x03), CORE3, ARG_FP}, -+ {"fmuls", FP (0x18, 0x04), CORE3, ARG_FP}, -+ {"fmuld", FP (0x18, 0x05), CORE3, ARG_FP}, -+ {"fdivs", FP (0x18, 0x06), CORE3, ARG_FP}, -+ {"fdivd", FP (0x18, 0x07), CORE3, ARG_FP}, -+ {"fsqrts", FP (0x18, 0x08), CORE3, ARG_FPZ1}, -+ {"fsqrtd", FP (0x18, 0x09), CORE3, ARG_FPZ1}, -+ {"fcmpeq", FP (0x18, 0x10), CORE3, ARG_FP}, -+ {"fcmple", FP (0x18, 0x11), CORE3, ARG_FP}, -+ {"fcmplt", FP (0x18, 0x12), CORE3, ARG_FP}, -+ {"fcmpun", FP (0x18, 0x13), CORE3, ARG_FP}, -+ -+ {"fcvtsd", FP (0x18, 0x20), CORE3, ARG_FPZ1}, -+ {"fcvtds", FP (0x18, 0x21), CORE3, ARG_FPZ1}, -+ {"fcvtdl_g", FP (0x18, 0x22), CORE3, ARG_FPZ1}, -+ {"fcvtdl_p", FP (0x18, 0x23), CORE3, ARG_FPZ1}, -+ {"fcvtdl_z", FP (0x18, 0x24), CORE3, ARG_FPZ1}, -+ {"fcvtdl_n", FP (0x18, 0x25), CORE3, ARG_FPZ1}, -+ {"fcvtdl", FP (0x18, 0x27), CORE3, ARG_FPZ1}, -+ {"fcvtwl", FP (0x18, 0x28), CORE3, ARG_FPZ1}, -+ {"fcvtlw", FP (0x18, 0x29), CORE3, ARG_FPZ1}, -+ {"fcvtls", FP (0x18, 0x2d), CORE3, ARG_FPZ1}, -+ {"fcvths", FP (0x18, 0x2e), CORE4A, ARG_FPZ1}, -+ {"fcvtld", FP (0x18, 0x2f), CORE3, ARG_FPZ1}, -+ -+ {"fnop", FP (0x18, 0x030), CORE3, {ZA, ZB, ZC}}, -+ {"fclr", FP (0x18, 0x030), CORE3, {ZA, ZB, FC}}, -+ {"fabs", FP (0x18, 0x030), CORE3, ARG_FPZ1}, -+ {"fcpys", FP (0x18, 0x30), CORE3, ARG_FP}, -+ {"fmov", FP (0x18, 0x30), CORE3, {FA, RBA, FC}}, -+ {"fcpyse", FP (0x18, 0x31), CORE3, ARG_FP}, -+ {"fneg", FP (0x18, 0x32), CORE3, {FA, RBA, FC}}, -+ {"fcpysn", FP (0x18, 0x32), CORE3, ARG_FP}, -+ -+ {"ifmovs", FP (0x18, 0x40), CORE3, {RA, ZB, FC}}, -+ {"ifmovd", FP (0x18, 0x41), CORE3, {RA, ZB, FC}}, -+ {"itofd", FP (0x18, 0x41), CORE3, {RA, ZB, FC}}, -+ {"cmovls", FP (0x18, 0x48), CORE4A, {ZA, RB, FC}}, -+ {"cmovws", FP (0x18, 0x49), CORE4A, {ZA, RB, FC}}, -+ {"cmovld", FP (0x18, 0x4a), CORE4A, {ZA, RB, FC}}, -+ {"cmovwd", FP (0x18, 0x4b), CORE4A, {ZA, RB, FC}}, -+ {"cmovuls", FP (0x18, 0x4c), CORE4A, {ZA, RB, FC}}, -+ {"cmovuws", FP (0x18, 0x4d), CORE4A, {ZA, RB, FC}}, -+ {"cmovuld", FP (0x18, 0x4e), CORE4A, {ZA, RB, FC}}, -+ {"cmovuwd", FP (0x18, 0x4f), CORE4A, {ZA, RB, FC}}, -+ {"rfpcr", FP (0x18, 0x50), CORE3, {FA, RBA, RCA}}, -+ {"wfpcr", FP (0x18, 0x51), CORE3, {FA, RBA, RCA}}, -+ {"setfpec0", FP (0x18, 0x54), CORE3, ARG_NONE}, -+ {"setfpec1", FP (0x18, 0x55), CORE3, ARG_NONE}, -+ {"setfpec2", FP (0x18, 0x56), CORE3, ARG_NONE}, -+ {"setfpec3", FP (0x18, 0x57), CORE3, ARG_NONE}, -+ {"frecs", FP (0x18, 0x58), CORE4A, {FA, ZB, DFC1}}, -+ {"frecd", FP (0x18, 0x59), CORE4A, {FA, ZB, DFC1}}, -+ {"fris", FP (0x18, 0x5A), CORE4A, ARG_FPZ1}, -+ {"fris_g", FP (0x18, 0x5B), CORE4A, ARG_FPZ1}, -+ {"fris_p", FP (0x18, 0x5C), CORE4A, ARG_FPZ1}, -+ {"fris_z", FP (0x18, 0x5D), CORE4A, ARG_FPZ1}, -+ {"fris_n", FP (0x18, 0x5F), CORE4A, ARG_FPZ1}, -+ {"frid", FP (0x18, 0x60), CORE4A, ARG_FPZ1}, -+ {"frid_g", FP (0x18, 0x61), CORE4A, ARG_FPZ1}, -+ {"frid_p", FP (0x18, 0x62), CORE4A, ARG_FPZ1}, -+ {"frid_z", FP (0x18, 0x63), CORE4A, ARG_FPZ1}, -+ {"frid_n", FP (0x18, 0x64), CORE4A, ARG_FPZ1}, -+ {"fmas", FMA (0x19, 0x00), CORE3, ARG_FMA}, -+ {"fmad", FMA (0x19, 0x01), CORE3, ARG_FMA}, -+ {"fmss", FMA (0x19, 0x02), CORE3, ARG_FMA}, -+ {"fmsd", FMA (0x19, 0x03), CORE3, ARG_FMA}, -+ {"fnmas", FMA (0x19, 0x04), CORE3, ARG_FMA}, -+ {"fnmad", FMA (0x19, 0x05), CORE3, ARG_FMA}, -+ {"fnmss", FMA (0x19, 0x06), CORE3, ARG_FMA}, -+ {"fnmsd", FMA (0x19, 0x07), CORE3, ARG_FMA}, -+ -+ // fcmov*(SW6) to fcmov*(SW6) for fcmov* no need in sw64, and fsel*->fcmov* -+ // has difference in operands number,so it should not repalce directly. The -+ // default FD should be the same FC but not FA -+ {"fseleq", FMA (0x19, 0x10), CORE3, ARG_FCMOV}, -+ {"fselne", FMA (0x19, 0x11), CORE3, ARG_FCMOV}, -+ {"fsellt", FMA (0x19, 0x12), CORE3, ARG_FCMOV}, -+ {"fselle", FMA (0x19, 0x13), CORE3, ARG_FCMOV}, -+ {"fselgt", FMA (0x19, 0x14), CORE3, ARG_FCMOV}, -+ {"fselge", FMA (0x19, 0x15), CORE3, ARG_FCMOV}, -+ -+ {"vaddw", FP (0x1A, 0x00), CORE3, ARG_FP}, -+ {"vaddw", FP (0x1A, 0x20), CORE3, ARG_FPL}, -+ {"vsubw", FP (0x1A, 0x01), CORE3, ARG_FP}, -+ {"vsubw", FP (0x1A, 0x21), CORE3, ARG_FPL}, -+ {"vcmpgew", FP (0x1A, 0x02), CORE3, ARG_FP}, -+ {"vcmpgew", FP (0x1A, 0x22), CORE3, ARG_FPL}, -+ {"vcmpeqw", FP (0x1A, 0x03), CORE3, ARG_FP}, -+ {"vcmpeqw", FP (0x1A, 0x23), CORE3, ARG_FPL}, -+ {"vcmplew", FP (0x1A, 0x04), CORE3, ARG_FP}, -+ {"vcmplew", FP (0x1A, 0x24), CORE3, ARG_FPL}, -+ {"vcmpltw", FP (0x1A, 0x05), CORE3, ARG_FP}, -+ {"vcmpltw", FP (0x1A, 0x25), CORE3, ARG_FPL}, -+ {"vcmpulew", FP (0x1A, 0x06), CORE3, ARG_FP}, -+ {"vcmpulew", FP (0x1A, 0x26), CORE3, ARG_FPL}, -+ {"vcmpultw", FP (0x1A, 0x07), CORE3, ARG_FP}, -+ {"vcmpultw", FP (0x1A, 0x27), CORE3, ARG_FPL}, -+ -+ {"vsllw", FP (0x1A, 0x08), CORE3, ARG_FP}, -+ {"vsllw", FP (0x1A, 0x28), CORE3, ARG_FPL}, -+ {"vsrlw", FP (0x1A, 0x09), CORE3, ARG_FP}, -+ {"vsrlw", FP (0x1A, 0x29), CORE3, ARG_FPL}, -+ {"vsraw", FP (0x1A, 0x0A), CORE3, ARG_FP}, -+ {"vsraw", FP (0x1A, 0x2A), CORE3, ARG_FPL}, -+ {"vrolw", FP (0x1A, 0x0B), CORE3, ARG_FP}, -+ {"vrolw", FP (0x1A, 0x2B), CORE3, ARG_FPL}, -+ {"sllow", FP (0x1A, 0x0C), CORE3, ARG_FP}, -+ {"sllow", FP (0x1A, 0x2C), CORE3, ARG_FPL}, -+ {"srlow", FP (0x1A, 0x0D), CORE3, ARG_FP}, -+ {"srlow", FP (0x1A, 0x2D), CORE3, ARG_FPL}, -+ {"vaddl", FP (0x1A, 0x0E), CORE3, ARG_FP}, -+ {"vaddl", FP (0x1A, 0x2E), CORE3, ARG_FPL}, -+ {"vsubl", FP (0x1A, 0x0F), CORE3, ARG_FP}, -+ {"vsubl", FP (0x1A, 0x2F), CORE3, ARG_FPL}, -+ {"vsllb", FP (0x1A, 0x10), CORE4A, ARG_FP}, -+ {"vsllb", FP (0x1A, 0x30), CORE4A, ARG_FPL}, -+ {"vsrlb", FP (0x1A, 0x11), CORE4A, ARG_FP}, -+ {"vsrlb", FP (0x1A, 0x31), CORE4A, ARG_FPL}, -+ {"vsrab", FP (0x1A, 0x12), CORE4A, ARG_FP}, -+ {"vsrab", FP (0x1A, 0x32), CORE4A, ARG_FPL}, -+ {"vrolb", FP (0x1A, 0x13), CORE4A, ARG_FP}, -+ {"vrolb", FP (0x1A, 0x33), CORE4A, ARG_FPL}, -+ {"vsllh", FP (0x1A, 0x14), CORE4A, ARG_FP}, -+ {"vsllh", FP (0x1A, 0x34), CORE4A, ARG_FPL}, -+ {"vsrlh", FP (0x1A, 0x15), CORE4A, ARG_FP}, -+ {"vsrlh", FP (0x1A, 0x35), CORE4A, ARG_FPL}, -+ {"vsrah", FP (0x1A, 0x16), CORE4A, ARG_FP}, -+ {"vsrah", FP (0x1A, 0x36), CORE4A, ARG_FPL}, -+ {"vrolh", FP (0x1A, 0x17), CORE4A, ARG_FP}, -+ {"vrolh", FP (0x1A, 0x37), CORE4A, ARG_FPL}, -+ {"ctpopow", FP (0x1A, 0x18), CORE3, {FA, ZB, DFC1}}, -+ {"ctlzow", FP (0x1A, 0x19), CORE3, {FA, ZB, DFC1}}, -+ {"vslll", FP (0x1A, 0x1A), CORE4A, ARG_FP}, -+ {"vslll", FP (0x1A, 0x3A), CORE4A, ARG_FPL}, -+ {"vsrll", FP (0x1A, 0x1B), CORE4A, ARG_FP}, -+ {"vsrll", FP (0x1A, 0x3B), CORE4A, ARG_FPL}, -+ {"vsral", FP (0x1A, 0x1C), CORE4A, ARG_FP}, -+ {"vsral", FP (0x1A, 0x3C), CORE4A, ARG_FPL}, -+ {"vroll", FP (0x1A, 0x1D), CORE4A, ARG_FP}, -+ {"vroll", FP (0x1A, 0x3D), CORE4A, ARG_FPL}, -+ {"vmaxb", FP (0x1A, 0x1E), CORE4A, ARG_FP}, -+ {"vminb", FP (0x1A, 0x1F), CORE4A, ARG_FP}, -+ {"vucaddw", FP (0x1A, 0x40), CORE3, ARG_FP}, -+ {"vucaddw", FP (0x1A, 0x60), CORE3, ARG_FPL}, -+ {"vucsubw", FP (0x1A, 0x41), CORE3, ARG_FP}, -+ {"vucsubw", FP (0x1A, 0x61), CORE3, ARG_FPL}, -+ {"vucaddh", FP (0x1A, 0x42), CORE3, ARG_FP}, -+ {"vucaddh", FP (0x1A, 0x62), CORE3, ARG_FPL}, -+ {"vucsubh", FP (0x1A, 0x43), CORE3, ARG_FP}, -+ {"vucsubh", FP (0x1A, 0x63), CORE3, ARG_FPL}, -+ {"vucaddb", FP (0x1A, 0x44), CORE3, ARG_FP}, -+ {"vucaddb", FP (0x1A, 0x64), CORE3, ARG_FPL}, -+ {"vucsubb", FP (0x1A, 0x45), CORE3, ARG_FP}, -+ {"vucsubb", FP (0x1A, 0x65), CORE3, ARG_FPL}, -+ {"sraow", FP (0x1A, 0x46), CORE4A, ARG_FP}, -+ {"sraow", FP (0x1A, 0x66), CORE4A, ARG_FPL}, -+ {"vsumw", FP (0x1A, 0x47), CORE4A, {FA, ZB, DFC1}}, -+ {"vsuml", FP (0x1A, 0x48), CORE4A, {FA, ZB, DFC1}}, -+ {"vcmpueqb", FP (0x1A, 0x4B), CORE4A, ARG_FP}, -+ {"vcmpueqb", FP (0x1A, 0x6B), CORE4A, ARG_FPL}, -+ {"vcmpugtb", FP (0x1A, 0x4C), CORE4A, ARG_FP}, -+ {"vcmpugtb", FP (0x1A, 0x6C), CORE4A, ARG_FPL}, -+ {"vmaxh", FP (0x1A, 0x50), CORE4A, ARG_FP}, -+ {"vminh", FP (0x1A, 0x51), CORE4A, ARG_FP}, -+ {"vmaxw", FP (0x1A, 0x52), CORE4A, ARG_FP}, -+ {"vminw", FP (0x1A, 0x53), CORE4A, ARG_FP}, -+ {"vmaxl", FP (0x1A, 0x54), CORE4A, ARG_FP}, -+ {"vminl", FP (0x1A, 0x55), CORE4A, ARG_FP}, -+ {"vumaxb", FP (0x1A, 0x56), CORE4A, ARG_FP}, -+ {"vuminb", FP (0x1A, 0x57), CORE4A, ARG_FP}, -+ {"vumaxh", FP (0x1A, 0x58), CORE4A, ARG_FP}, -+ {"vuminh", FP (0x1A, 0x59), CORE4A, ARG_FP}, -+ {"vumaxw", FP (0x1A, 0x5A), CORE4A, ARG_FP}, -+ {"vuminw", FP (0x1A, 0x5B), CORE4A, ARG_FP}, -+ {"vumaxl", FP (0x1A, 0x5C), CORE4A, ARG_FP}, -+ {"vuminl", FP (0x1A, 0x5D), CORE4A, ARG_FP}, -+ {"vsm3msw", FP (0x1A, 0x4D), CORE4A, ARG_FP}, -+ {"vsm4key", FP (0x1A, 0x68), CORE4A, ARG_FPL}, -+ {"vsm4r", FP (0x1A, 0x49), CORE4A, ARG_FP}, -+ {"vbinvw", FP (0x1A, 0x4A), CORE4A, ARG_FPZ1}, -+ {"vadds", FP (0x1A, 0x80), CORE3, ARG_FP}, -+ {"v4adds", FP (0x1A, 0x80), CORE3, ARG_FP}, /* pseudo CORE3 SIMD*/ -+ {"vaddd", FP (0x1A, 0x81), CORE3, ARG_FP}, -+ {"v4addd", FP (0x1A, 0x81), CORE3, ARG_FP}, /* pseudo CORE3 SIMD*/ -+ {"vsubs", FP (0x1A, 0x82), CORE3, ARG_FP}, -+ {"v4subs", FP (0x1A, 0x82), CORE3, ARG_FP}, /* pseudo CORE3 SIMD*/ -+ {"vsubd", FP (0x1A, 0x83), CORE3, ARG_FP}, -+ {"v4subd", FP (0x1A, 0x83), CORE3, ARG_FP}, /* pseudo CORE3 SIMD*/ -+ {"vmuls", FP (0x1A, 0x84), CORE3, ARG_FP}, -+ {"v4muls", FP (0x1A, 0x84), CORE3, ARG_FP}, /* pseudo CORE3 SIMD*/ -+ {"vmuld", FP (0x1A, 0x85), CORE3, ARG_FP}, -+ {"v4muld", FP (0x1A, 0x85), CORE3, ARG_FP}, /* pseudo CORE3 SIMD*/ -+ {"vdivs", FP (0x1A, 0x86), CORE3, ARG_FP}, -+ {"vdivd", FP (0x1A, 0x87), CORE3, ARG_FP}, -+ {"vsqrts", FP (0x1A, 0x88), CORE3, ARG_FPZ1}, -+ {"vsqrtd", FP (0x1A, 0x89), CORE3, ARG_FPZ1}, -+ {"vfcmpeq", FP (0x1A, 0x8C), CORE3, ARG_FP}, -+ {"vfcmple", FP (0x1A, 0x8D), CORE3, ARG_FP}, -+ {"vfcmplt", FP (0x1A, 0x8E), CORE3, ARG_FP}, -+ {"vfcmpun", FP (0x1A, 0x8F), CORE3, ARG_FP}, -+ {"vcpys", FP (0x1A, 0x90), CORE3, ARG_FP}, -+ {"vfmov", FP (0x1A, 0x90), CORE3, {FA, RBA, FC}}, // V1.1 -+ {"vcpyse", FP (0x1A, 0x91), CORE3, ARG_FP}, // CORE3 1.0 -+ {"vcpysn", FP (0x1A, 0x92), CORE3, ARG_FP}, // CORE3 1.0 -+ {"vsums", FP (0x1A, 0x93), CORE4A, {FA, ZB, DFC1}}, -+ {"vsumd", FP (0x1A, 0x94), CORE4A, {FA, ZB, DFC1}}, -+ {"vfcvtsd", FP (0x1A, 0x95), CORE4A, ARG_FPZ1}, -+ {"vfcvtds", FP (0x1A, 0x96), CORE4A, ARG_FPZ1}, -+ {"vfcvtls", FP (0x1A, 0x99), CORE4A, ARG_FPZ1}, -+ {"vfcvtld", FP (0x1A, 0x9A), CORE4A, ARG_FPZ1}, -+ {"vfcvtdl", FP (0x1A, 0x9B), CORE4A, ARG_FPZ1}, -+ {"vfcvtdl_g", FP (0x1A, 0x9C), CORE4A, ARG_FPZ1}, -+ {"vfcvtdl_p", FP (0x1A, 0x9D), CORE4A, ARG_FPZ1}, -+ {"vfcvtdl_z", FP (0x1A, 0x9E), CORE4A, ARG_FPZ1}, -+ {"vfcvtdl_n", FP (0x1A, 0x9F), CORE4A, ARG_FPZ1}, -+ {"vfris", FP (0x1A, 0xA0), CORE4A, ARG_FPZ1}, -+ {"vfris_g", FP (0x1A, 0xA1), CORE4A, ARG_FPZ1}, -+ {"vfris_p", FP (0x1A, 0xA2), CORE4A, ARG_FPZ1}, -+ {"vfris_z", FP (0x1A, 0xA3), CORE4A, ARG_FPZ1}, -+ {"vfris_n", FP (0x1A, 0xA4), CORE4A, ARG_FPZ1}, -+ {"vfrid", FP (0x1A, 0xA5), CORE4A, ARG_FPZ1}, -+ {"vfrid_g", FP (0x1A, 0xA6), CORE4A, ARG_FPZ1}, -+ {"vfrid_p", FP (0x1A, 0xA7), CORE4A, ARG_FPZ1}, -+ {"vfrid_z", FP (0x1A, 0xA8), CORE4A, ARG_FPZ1}, -+ {"vfrid_n", FP (0x1A, 0xA9), CORE4A, ARG_FPZ1}, -+ {"vfrecs", FP (0x1A, 0xAA), CORE4A, {FA, ZB, DFC1}}, -+ {"vfrecd", FP (0x1A, 0xAB), CORE4A, {FA, ZB, DFC1}}, -+ {"vmaxs", FP (0x1A, 0xAC), CORE4A, ARG_FP}, -+ {"vmins", FP (0x1A, 0xAD), CORE4A, ARG_FP}, -+ {"vmaxd", FP (0x1A, 0xAE), CORE4A, ARG_FP}, -+ {"vmind", FP (0x1A, 0xAF), CORE4A, ARG_FP}, -+ {"addow", FP (0x1A, 0xB0), CORE4A, ARG_FP}, -+ {"addow", FP (0x1A, 0xC0), CORE4A, ARG_FPL}, -+ {"subow", FP (0x1A, 0xB1), CORE4A, ARG_FP}, -+ {"subow", FP (0x1A, 0xC1), CORE4A, ARG_FPL}, -+ {"cmpeqow", FP (0x1A, 0xB2), CORE4A, ARG_FP}, -+ {"cmpuleow", FP (0x1A, 0xB3), CORE4A, ARG_FP}, -+ {"cmpultow", FP (0x1A, 0xB4), CORE4A, ARG_FP}, -+ {"umulow", FP (0x1A, 0xB5), CORE4A, ARG_FP}, -+ {"vaesenc", FP (0x1A, 0xB6), CORE4A, ARG_FP}, -+ {"vaesencl", FP (0x1A, 0xB7), CORE4A, ARG_FP}, -+ {"vaesdec", FP (0x1A, 0xB8), CORE4A, ARG_FP}, -+ {"vaesdecl", FP (0x1A, 0xB9), CORE4A, ARG_FP}, -+ {"vaessbox", FP (0x1A, 0xBA), CORE4A, {FA, ZB, DFC1}}, -+ {"sha1msw", FP (0x1A, 0xBC), CORE4A, ARG_FP}, -+ {"sha256msw", FP (0x1A, 0xBD), CORE4A, ARG_FP}, -+ {"sha512msl0", FP (0x1A, 0xBE), CORE4A, ARG_FP}, -+ {"vmas", FMA (0x1B, 0x00), CORE3, ARG_FMA}, -+ {"vmad", FMA (0x1B, 0x01), CORE3, ARG_FMA}, -+ {"vmss", FMA (0x1B, 0x02), CORE3, ARG_FMA}, -+ {"vmsd", FMA (0x1B, 0x03), CORE3, ARG_FMA}, -+ {"vnmas", FMA (0x1B, 0x04), CORE3, ARG_FMA}, -+ {"vnmad", FMA (0x1B, 0x05), CORE3, ARG_FMA}, -+ {"vnmss", FMA (0x1B, 0x06), CORE3, ARG_FMA}, -+ {"vnmsd", FMA (0x1B, 0x07), CORE3, ARG_FMA}, -+ {"vfseleq", FMA (0x1B, 0x10), CORE3, ARG_FMA}, -+ {"vfsellt", FMA (0x1B, 0x12), CORE3, ARG_FMA}, -+ {"vfselle", FMA (0x1B, 0x13), CORE3, ARG_FMA}, -+ {"vseleqw", FMA (0x1B, 0x18), CORE3, ARG_FMA}, -+ {"vseleqw", FMA (0x1B, 0x38), CORE3, ARG_FMAL}, -+ {"vsellbcw", FMA (0x1B, 0x19), CORE3, ARG_FMA}, -+ {"vsellbcw", FMA (0x1B, 0x39), CORE3, ARG_FMAL}, -+ {"vselltw", FMA (0x1B, 0x1A), CORE3, ARG_FMA}, -+ {"vselltw", FMA (0x1B, 0x3A), CORE3, ARG_FMAL}, -+ {"vsellew", FMA (0x1B, 0x1B), CORE3, ARG_FMA}, -+ {"vsellew", FMA (0x1B, 0x3B), CORE3, ARG_FMAL}, -+ {"sha1r", FMA (0x1B, 0x1E), CORE4A, ARG_FMAL}, -+ {"sha256r", FMA (0x1B, 0x1F), CORE4A, ARG_FMAL}, -+ {"vinsw", FMA (0x1B, 0x20), CORE3, ARG_FMAL}, -+ {"vinsf", FMA (0x1B, 0x21), CORE3, ARG_FMAL}, -+ {"vextw", FMA (0x1B, 0x22), CORE3, {FA, FMALIT, DFC1}}, -+ {"vextf", FMA (0x1B, 0x23), CORE3, {FA, FMALIT, DFC1}}, -+ {"vcpyw", FMA (0x1B, 0x24), CORE3, {FA, DFC1}}, -+ {"vcpyf", FMA (0x1B, 0x25), CORE3, {FA, DFC1}}, -+ {"vconw", FMA (0x1B, 0x26), CORE3, ARG_FMA}, -+ {"vshfw", FMA (0x1B, 0x27), CORE3, ARG_FMA}, -+ {"vcons", FMA (0x1B, 0x28), CORE3, ARG_FMA}, -+ {"vcond", FMA (0x1B, 0x29), CORE3, ARG_FMA}, -+ {"vinsb", FMA (0x1B, 0x2A), CORE4A, ARG_FMAL}, -+ {"vinsh", FMA (0x1B, 0x2B), CORE4A, ARG_FMAL}, -+ {"vinsectlh", FMA (0x1B, 0x2C), CORE4A, {FA, FB, ZC2, DFC1}}, -+ {"vinsectlw", FMA (0x1B, 0x2D), CORE4A, {FA, FB, ZC2, DFC1}}, -+ {"vinsectll", FMA (0x1B, 0x2E), CORE4A, {FA, FB, ZC2, DFC1}}, -+ {"vinsectlb", FMA (0x1B, 0x2F), CORE4A, {FA, FB, ZC2, DFC1}}, -+ {"vshfq", FMA (0x1B, 0x30), CORE4A, ARG_FMAL}, -+ {"vshfqb", FMA (0x1B, 0x31), CORE4A, {FA, FB, ZC2, DFC1}}, -+ {"vcpyb", FMA (0x1B, 0x32), CORE4A, {FA, DFC1}}, -+ {"vcpyh", FMA (0x1B, 0x33), CORE4A, {FA, DFC1}}, -+ {"vsm3r", FMA (0x1B, 0x34), CORE4A, ARG_FMAL}, -+ {"vfcvtsh", FMA (0x1B, 0x35), CORE4A, ARG_FMAL}, -+ {"vfcvths", FMA (0x1B, 0x36), CORE4A, {FA, FMALIT, FC}}, -+ {"fcvtsh", FMA (0x1B, 0x37), CORE4A, {FA, FB, FMALIT, DFC1}}, -+ {"sha512msl1", FMA (0x1B, 0x3C), CORE4A, ARG_FMA}, -+ {"sha512r0", FMA (0x1B, 0x3D), CORE4A, ARG_FMA}, -+ {"sha512r1", FMA (0x1B, 0x3E), CORE4A, ARG_FMA}, -+ {"vldw_u", ATMEM (0x1C, 0x0), CORE3, ARG_VUAMEM}, -+ {"vstw_u", ATMEM (0x1C, 0x1), CORE3, ARG_VUAMEM}, -+ {"vlds_u", ATMEM (0x1C, 0x2), CORE3, ARG_VUAMEM}, -+ {"vsts_u", ATMEM (0x1C, 0x3), CORE3, ARG_VUAMEM}, -+ {"vldd_u", ATMEM (0x1C, 0x4), CORE3, ARG_VUAMEM}, -+ {"vstd_u", ATMEM (0x1C, 0x5), CORE3, ARG_VUAMEM}, -+ {"vstw_ul", ATMEM (0x1C, 0x8), CORE3, ARG_VUAMEM}, -+ {"vstw_uh", ATMEM (0x1C, 0x9), CORE3, ARG_VUAMEM}, -+ {"vsts_ul", ATMEM (0x1C, 0xA), CORE3, ARG_VUAMEM}, -+ {"vsts_uh", ATMEM (0x1C, 0xB), CORE3, ARG_VUAMEM}, -+ {"vstd_ul", ATMEM (0x1C, 0xC), CORE3, ARG_VUAMEM}, -+ {"vstd_uh", ATMEM (0x1C, 0xD), CORE3, ARG_VUAMEM}, -+ {"vldd_nc", ATMEM (0x1C, 0xE), CORE3, ARG_VUAMEM}, -+ {"vstd_nc", ATMEM (0x1C, 0xF), CORE3, ARG_VUAMEM}, -+ {"lbr", BRA (0x1D), CORE4A, {BDISP26}}, -+ {"ldbu_a", ATMEM (0x1E, 0x0), CORE4A, ARG_ATMEM}, -+ {"ldhu_a", ATMEM (0x1E, 0x1), CORE4A, ARG_ATMEM}, -+ {"ldw_a", ATMEM (0x1E, 0x2), CORE4A, ARG_ATMEM}, -+ {"ldl_a", ATMEM (0x1E, 0x3), CORE4A, ARG_ATMEM}, -+ {"flds_a", ATMEM (0x1E, 0x4), CORE4A, ARG_VUAMEM}, -+ {"fldd_a", ATMEM (0x1E, 0x5), CORE4A, ARG_VUAMEM}, -+ {"stb_a", ATMEM (0x1E, 0x6), CORE4A, ARG_ATMEM}, -+ {"sth_a", ATMEM (0x1E, 0x7), CORE4A, ARG_ATMEM}, -+ {"stw_a", ATMEM (0x1E, 0x8), CORE4A, ARG_ATMEM}, -+ {"stl_a", ATMEM (0x1E, 0x9), CORE4A, ARG_ATMEM}, -+ {"fsts_a", ATMEM (0x1E, 0xA), CORE4A, ARG_VUAMEM}, -+ {"fstd_a", ATMEM (0x1E, 0xB), CORE4A, ARG_VUAMEM}, -+ {"dpfhr", ATMEM (0x1E, 0xE), CORE4A, {DPFTH, ATMDISP, PRB}}, -+ {"dpfhw", ATMEM (0x1E, 0xF), CORE4A, {DPFTH, ATMDISP, PRB}}, -+ {"flushd", MEM (0x20), CORE3, ARG_PREFETCH}, -+ {"ldbu", MEM (0x20), CORE3, ARG_MEM}, -+ {"evictdg", MEM (0x21), CORE3, ARG_PREFETCH}, -+ {"ldhu", MEM (0x21), CORE3, ARG_MEM}, -+ {"s_fillcs", MEM (0x22), CORE3, ARG_PREFETCH}, -+ {"ldw", MEM (0x22), CORE3, ARG_MEM}, -+ {"wh64", MFC (0x22, 0xF800), CORE3, {ZA, PRB}}, -+ {"s_fillde", MEM (0x23), CORE3, ARG_PREFETCH}, -+ {"ldl", MEM (0x23), CORE3, ARG_MEM}, -+ {"evictdl", MEM (0x24), CORE3, ARG_PREFETCH}, -+ {"ldl_u", MEM (0x24), CORE3, ARG_MEM}, -+ {"pri_ldw/p", SW6HWMEM (0x25, 0x0), CORE3, ARG_SW6HWMEM}, -+ {"pri_ldw_inc/p", SW6HWMEM (0x25, 0x2), CORE3, ARG_SW6HWMEM}, -+ {"pri_ldw_dec/p", SW6HWMEM (0x25, 0x4), CORE3, ARG_SW6HWMEM}, -+ {"pri_ldw_set/p", SW6HWMEM (0x25, 0x6), CORE3, ARG_SW6HWMEM}, -+ {"pri_ldw/v", SW6HWMEM (0x25, 0x8), CORE3, ARG_SW6HWMEM}, -+ {"pri_ldw/vpte", SW6HWMEM (0x25, 0xA), CORE3, ARG_SW6HWMEM}, -+ {"pri_ldl/p", SW6HWMEM (0x25, 0x1), CORE3, ARG_SW6HWMEM}, -+ {"pri_ldl_inc/p", SW6HWMEM (0x25, 0x3), CORE3, ARG_SW6HWMEM}, -+ {"pri_ldl_dec/p", SW6HWMEM (0x25, 0x5), CORE3, ARG_SW6HWMEM}, -+ {"pri_ldl_set/p", SW6HWMEM (0x25, 0x7), CORE3, ARG_SW6HWMEM}, -+ {"pri_ldl/v", SW6HWMEM (0x25, 0x9), CORE3, ARG_SW6HWMEM}, -+ {"pri_ldl/vpte", SW6HWMEM (0x25, 0xB), CORE3, ARG_SW6HWMEM}, -+ {"fillde", MEM (0x26), CORE3, ARG_PREFETCH}, -+ {"flds", MEM (0x26), CORE3, ARG_FMEM}, -+ {"fillde_e", MEM (0x27), CORE3, ARG_PREFETCH}, -+ {"fldd", MEM (0x27), CORE3, ARG_FMEM}, -+ -+ {"stb", MEM (0x28), CORE3, ARG_MEM}, -+ {"sth", MEM (0x29), CORE3, ARG_MEM}, -+ {"stw", MEM (0x2A), CORE3, ARG_MEM}, -+ {"stl", MEM (0x2B), CORE3, ARG_MEM}, -+ {"stl_u", MEM (0x2C), CORE3, ARG_MEM}, -+ {"pri_stw/p", SW6HWMEM (0x2D, 0x0), CORE3, ARG_SW6HWMEM}, -+ {"pri_stw/v", SW6HWMEM (0x2D, 0x8), CORE3, ARG_SW6HWMEM}, -+ {"pri_stl/p", SW6HWMEM (0x2D, 0x1), CORE3, ARG_SW6HWMEM}, -+ {"pri_stl/v", SW6HWMEM (0x2D, 0x9), CORE3, ARG_SW6HWMEM}, -+ {"fsts", MEM (0x2E), CORE3, ARG_FMEM}, -+ {"fstd", MEM (0x2F), CORE3, ARG_FMEM}, -+ {"beq", BRA (0x30), CORE3, ARG_BRA}, -+ {"bne", BRA (0x31), CORE3, ARG_BRA}, -+ {"blt", BRA (0x32), CORE3, ARG_BRA}, -+ {"ble", BRA (0x33), CORE3, ARG_BRA}, -+ {"bgt", BRA (0x34), CORE3, ARG_BRA}, -+ {"bge", BRA (0x35), CORE3, ARG_BRA}, -+ {"blbc", BRA (0x36), CORE3, ARG_BRA}, -+ {"blbs", BRA (0x37), CORE3, ARG_BRA}, -+ -+ {"fbeq", BRA (0x38), CORE3, ARG_FBRA}, -+ {"fbne", BRA (0x39), CORE3, ARG_FBRA}, -+ {"fblt", BRA (0x3A), CORE3, ARG_FBRA}, -+ {"fble", BRA (0x3B), CORE3, ARG_FBRA}, -+ {"fbgt", BRA (0x3C), CORE3, ARG_FBRA}, -+ {"fbge", BRA (0x3D), CORE3, ARG_FBRA}, -+ {"ldi", MEM (0x3E), CORE3, {RA, MDISP, ZB}}, -+ {"ldi", MEM (0x3E), CORE3, ARG_MEM}, -+ {"ldih", MEM (0x3F), CORE3, {RA, MDISP, ZB}}, -+ {"ldih", MEM (0x3F), CORE3, ARG_MEM}, -+ {"unop", MEM_ (0x3F) | (30 << 16), MEM_MASK, CORE3, {ZA}}, -+}; -+ -+const unsigned sw_64_num_opcodes -+ = sizeof (sw_64_opcodes) / sizeof (*sw_64_opcodes); diff --git a/Use-32-64_PCREL-to-replace-a-pair-of-ADD32-64-and-SU.patch b/Use-32-64_PCREL-to-replace-a-pair-of-ADD32-64-and-SU.patch deleted file mode 100644 index 73edbc0..0000000 --- a/Use-32-64_PCREL-to-replace-a-pair-of-ADD32-64-and-SU.patch +++ /dev/null @@ -1,85 +0,0 @@ -From 7ce995e6e17a8ec5c139f0398dd4f598fae5ca92 Mon Sep 17 00:00:00 2001 -From: cailulu -Date: Fri, 1 Sep 2023 11:09:00 +0800 -Subject: [PATCH 006/123] Use 32/64_PCREL to replace a pair of ADD32/64 and - SUB32/64. - -Subtraction for labels that require static relocation -usually generates ADD32/64 and SUB32/64. - -If subsy of BFD_RELOC_32/64 and PC in same segment, -and disable relax or PC at start of subsy or enable -relax but not in SEC_CODE, we generate 32/64_PCREL -to replace a pair of ADD32/64 and SUB32/64. ---- - gas/config/tc-loongarch.c | 22 ++++++++++++---------- - gas/config/tc-loongarch.h | 12 ++++++++++-- - 2 files changed, 22 insertions(+), 12 deletions(-) - -diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c -index 29a14e74..38a51fc2 100644 ---- a/gas/config/tc-loongarch.c -+++ b/gas/config/tc-loongarch.c -@@ -1197,7 +1197,6 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) - static int64_t stack_top; - static int last_reloc_is_sop_push_pcrel_1 = 0; - int last_reloc_is_sop_push_pcrel = last_reloc_is_sop_push_pcrel_1; -- segT sub_segment; - last_reloc_is_sop_push_pcrel_1 = 0; - - char *buf = fixP->fx_frag->fr_literal + fixP->fx_where; -@@ -1275,16 +1274,19 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) - (use md_number_to_chars (buf, 0, fixP->fx_size)). */ - case BFD_RELOC_64: - case BFD_RELOC_32: -- if (fixP->fx_r_type == BFD_RELOC_32 -- && fixP->fx_addsy && fixP->fx_subsy -- && (sub_segment = S_GET_SEGMENT (fixP->fx_subsy)) -- && strcmp (sub_segment->name, ".eh_frame") == 0 -- && S_GET_VALUE (fixP->fx_subsy) -- == fixP->fx_frag->fr_address + fixP->fx_where) -+ if (fixP->fx_pcrel) - { -- fixP->fx_r_type = BFD_RELOC_LARCH_32_PCREL; -- fixP->fx_subsy = NULL; -- break; -+ switch (fixP->fx_r_type) -+ { -+ case BFD_RELOC_64: -+ fixP->fx_r_type = BFD_RELOC_LARCH_64_PCREL; -+ break; -+ case BFD_RELOC_32: -+ fixP->fx_r_type = BFD_RELOC_LARCH_32_PCREL; -+ break; -+ default: -+ break; -+ } - } - - if (fixP->fx_addsy && fixP->fx_subsy) -diff --git a/gas/config/tc-loongarch.h b/gas/config/tc-loongarch.h -index a9f2a0a1..d353f18d 100644 ---- a/gas/config/tc-loongarch.h -+++ b/gas/config/tc-loongarch.h -@@ -71,8 +71,16 @@ extern bool loongarch_frag_align_code (int); - relaxation, so do not resolve such expressions in the assembler. */ - #define md_allow_local_subtract(l,r,s) 0 - --/* Values passed to md_apply_fix don't include symbol values. */ --#define TC_FORCE_RELOCATION_SUB_LOCAL(FIX, SEG) 1 -+/* If subsy of BFD_RELOC32/64 and PC in same segment, and without relax -+ or PC at start of subsy or with relax but sub_symbol_segment not in -+ SEC_CODE, we generate 32/64_PCREL. */ -+#define TC_FORCE_RELOCATION_SUB_LOCAL(FIX, SEG) \ -+ (!((BFD_RELOC_32 || BFD_RELOC_64) \ -+ &&(!LARCH_opts.relax \ -+ || S_GET_VALUE (FIX->fx_subsy) \ -+ == FIX->fx_frag->fr_address + FIX->fx_where \ -+ || (LARCH_opts.relax \ -+ && ((S_GET_SEGMENT (FIX->fx_subsy)->flags & SEC_CODE) == 0))))) - - #define TC_VALIDATE_FIX_SUB(FIX, SEG) 1 - #define DIFF_EXPR_OK 1 --- -2.33.0 - diff --git a/X86-Change-fpic-to-fPIC-in-PICFLAG.patch b/X86-Change-fpic-to-fPIC-in-PICFLAG.patch index 3982dcc..45ed225 100644 --- a/X86-Change-fpic-to-fPIC-in-PICFLAG.patch +++ b/X86-Change-fpic-to-fPIC-in-PICFLAG.patch @@ -4,23 +4,23 @@ Date: Tue, 8 Aug 2023 20:05:24 +0800 Subject: [PATCH] [X86] Change -fpic to -fPIC in PICFLAG --- - intl/configure | 2 +- + config/picflag.m4 | 2 +- libiberty/configure | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) -diff --git a/intl/configure b/intl/configure +diff --git a/config/picflag.m4 b/config/picflag.m4 index e75f072f..f8438526 100755 ---- a/intl/configure -+++ b/intl/configure -@@ -6867,7 +6867,7 @@ case "${host}" in +--- a/config/picflag.m4 ++++ b/config/picflag.m4 +@@ -57,7 +57,7 @@ # Some targets support both -fPIC and -fpic, but prefer the latter. # FIXME: Why? - i[34567]86-*-* | x86_64-*-*) -- PICFLAG=-fpic -+ PICFLAG=-fPIC + i[[34567]]86-*-* | x86_64-*-*) +- $1=-fpic ++ $1=-fPIC ;; - # FIXME: Override -fPIC default in libgcc only? - sh-*-linux* | sh[2346lbe]*-*-linux*) + # FIXME: Override -fPIC default in libgcc only? + sh-*-linux* | sh[[2346lbe]]*-*-linux*) diff --git a/libiberty/configure b/libiberty/configure index 1ccfac9f..0b85f351 100755 --- a/libiberty/configure diff --git a/as-Add-new-atomic-instructions-in-LoongArch-v1.1.patch b/as-Add-new-atomic-instructions-in-LoongArch-v1.1.patch deleted file mode 100644 index 46038e6..0000000 --- a/as-Add-new-atomic-instructions-in-LoongArch-v1.1.patch +++ /dev/null @@ -1,199 +0,0 @@ -From 9ff4752d0f6d46ca0f7d275ea07e05790ac8dd1d Mon Sep 17 00:00:00 2001 -From: Jiajie Chen -Date: Thu, 26 Oct 2023 17:35:13 +0800 -Subject: [PATCH] as: Add new atomic instructions in LoongArch v1.1 - -LoongArch V1.1 release is out at -https://github.com/loongson/LoongArch-Documentation. - -New atomic instructions in LoongArch v1.1: - -- sc.q -- llacq.w/d -- screl.w/d -- amcas{_db}.b/h/w/d -- amswap{_db}.b/h -- amadd{_db}.b/h - -Signed-off-by: Jiajie Chen -Signed-off-by: Peng Fan ---- - gas/config/tc-loongarch.c | 6 ++- - gas/testsuite/gas/loongarch/load_store_op.d | 42 +++++++++++++++++++++ - gas/testsuite/gas/loongarch/load_store_op.s | 42 +++++++++++++++++++++ - opcodes/loongarch-opc.c | 42 +++++++++++++++++++++ - 4 files changed, 130 insertions(+), 2 deletions(-) - -diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c -index d1ce111c186..59232832cf7 100644 ---- a/gas/config/tc-loongarch.c -+++ b/gas/config/tc-loongarch.c -@@ -893,8 +893,10 @@ check_this_insn_before_appending (struct loongarch_cl_insn *ip) - ip->reloc_num++; - } - else if (ip->insn->mask == 0xffff8000 -- /* amswap.w rd, rk, rj */ -- && ((ip->insn_bin & 0xfff00000) == 0x38600000 -+ /* amcas.b rd, rk, rj */ -+ && ((ip->insn_bin & 0xfff80000) == 0x38580000 -+ /* amswap.w rd, rk, rj */ -+ || (ip->insn_bin & 0xfff00000) == 0x38600000 - /* ammax_db.wu rd, rk, rj */ - || (ip->insn_bin & 0xffff0000) == 0x38700000 - /* ammin_db.wu rd, rk, rj */ -diff --git a/gas/testsuite/gas/loongarch/load_store_op.d b/gas/testsuite/gas/loongarch/load_store_op.d -index e1b4dea1851..0ad83167bbc 100644 ---- a/gas/testsuite/gas/loongarch/load_store_op.d -+++ b/gas/testsuite/gas/loongarch/load_store_op.d -@@ -176,3 +176,45 @@ Disassembly of section .text: - 298:[ ]+387e98a4 [ ]+stle.h[ ]+[ ]+\$a0, \$a1, \$a2 - 29c:[ ]+387f18a4 [ ]+stle.w[ ]+[ ]+\$a0, \$a1, \$a2 - 2a0:[ ]+387f98a4 [ ]+stle.d[ ]+[ ]+\$a0, \$a1, \$a2 -+ 2a4:[ ]+385714c4 [ ]+sc.q[ ]+[ ]+\$a0, \$a1, \$a2 -+ 2a8:[ ]+385714c4 [ ]+sc.q[ ]+[ ]+\$a0, \$a1, \$a2 -+ 2ac:[ ]+385780a4 [ ]+llacq.w[ ]+[ ]+\$a0, \$a1 -+ 2b0:[ ]+385780a4 [ ]+llacq.w[ ]+[ ]+\$a0, \$a1 -+ 2b4:[ ]+385784a4 [ ]+screl.w[ ]+[ ]+\$a0, \$a1 -+ 2b8:[ ]+385784a4 [ ]+screl.w[ ]+[ ]+\$a0, \$a1 -+ 2bc:[ ]+385788a4 [ ]+llacq.d[ ]+[ ]+\$a0, \$a1 -+ 2c0:[ ]+385788a4 [ ]+llacq.d[ ]+[ ]+\$a0, \$a1 -+ 2c4:[ ]+38578ca4 [ ]+screl.d[ ]+[ ]+\$a0, \$a1 -+ 2c8:[ ]+38578ca4 [ ]+screl.d[ ]+[ ]+\$a0, \$a1 -+ 2cc:[ ]+385814c4 [ ]+amcas.b[ ]+[ ]+\$a0, \$a1, \$a2 -+ 2d0:[ ]+385818a4 [ ]+amcas.b[ ]+[ ]+\$a0, \$a2, \$a1 -+ 2d4:[ ]+385894c4 [ ]+amcas.h[ ]+[ ]+\$a0, \$a1, \$a2 -+ 2d8:[ ]+385898a4 [ ]+amcas.h[ ]+[ ]+\$a0, \$a2, \$a1 -+ 2dc:[ ]+385914c4 [ ]+amcas.w[ ]+[ ]+\$a0, \$a1, \$a2 -+ 2e0:[ ]+385918a4 [ ]+amcas.w[ ]+[ ]+\$a0, \$a2, \$a1 -+ 2e4:[ ]+385994c4 [ ]+amcas.d[ ]+[ ]+\$a0, \$a1, \$a2 -+ 2e8:[ ]+385998a4 [ ]+amcas.d[ ]+[ ]+\$a0, \$a2, \$a1 -+ 2ec:[ ]+385a14c4 [ ]+amcas_db.b[ ]+[ ]+\$a0, \$a1, \$a2 -+ 2f0:[ ]+385a18a4 [ ]+amcas_db.b[ ]+[ ]+\$a0, \$a2, \$a1 -+ 2f4:[ ]+385a94c4 [ ]+amcas_db.h[ ]+[ ]+\$a0, \$a1, \$a2 -+ 2f8:[ ]+385a98a4 [ ]+amcas_db.h[ ]+[ ]+\$a0, \$a2, \$a1 -+ 2fc:[ ]+385b14c4 [ ]+amcas_db.w[ ]+[ ]+\$a0, \$a1, \$a2 -+ 300:[ ]+385b18a4 [ ]+amcas_db.w[ ]+[ ]+\$a0, \$a2, \$a1 -+ 304:[ ]+385b94c4 [ ]+amcas_db.d[ ]+[ ]+\$a0, \$a1, \$a2 -+ 308:[ ]+385b98a4 [ ]+amcas_db.d[ ]+[ ]+\$a0, \$a2, \$a1 -+ 30c:[ ]+385c14c4 [ ]+amswap.b[ ]+[ ]+\$a0, \$a1, \$a2 -+ 310:[ ]+385c18a4 [ ]+amswap.b[ ]+[ ]+\$a0, \$a2, \$a1 -+ 314:[ ]+385c94c4 [ ]+amswap.h[ ]+[ ]+\$a0, \$a1, \$a2 -+ 318:[ ]+385c98a4 [ ]+amswap.h[ ]+[ ]+\$a0, \$a2, \$a1 -+ 31c:[ ]+385d14c4 [ ]+amadd.b[ ]+[ ]+\$a0, \$a1, \$a2 -+ 320:[ ]+385d18a4 [ ]+amadd.b[ ]+[ ]+\$a0, \$a2, \$a1 -+ 324:[ ]+385d94c4 [ ]+amadd.h[ ]+[ ]+\$a0, \$a1, \$a2 -+ 328:[ ]+385d98a4 [ ]+amadd.h[ ]+[ ]+\$a0, \$a2, \$a1 -+ 32c:[ ]+385e14c4 [ ]+amswap_db.b[ ]+[ ]+\$a0, \$a1, \$a2 -+ 330:[ ]+385e18a4 [ ]+amswap_db.b[ ]+[ ]+\$a0, \$a2, \$a1 -+ 334:[ ]+385e94c4 [ ]+amswap_db.h[ ]+[ ]+\$a0, \$a1, \$a2 -+ 338:[ ]+385e98a4 [ ]+amswap_db.h[ ]+[ ]+\$a0, \$a2, \$a1 -+ 33c:[ ]+385f14c4 [ ]+amadd_db.b[ ]+[ ]+\$a0, \$a1, \$a2 -+ 340:[ ]+385f18a4 [ ]+amadd_db.b[ ]+[ ]+\$a0, \$a2, \$a1 -+ 344:[ ]+385f94c4 [ ]+amadd_db.h[ ]+[ ]+\$a0, \$a1, \$a2 -+ 348:[ ]+385f98a4 [ ]+amadd_db.h[ ]+[ ]+\$a0, \$a2, \$a1 -diff --git a/gas/testsuite/gas/loongarch/load_store_op.s b/gas/testsuite/gas/loongarch/load_store_op.s -index efbd124a29c..7912adb1090 100644 ---- a/gas/testsuite/gas/loongarch/load_store_op.s -+++ b/gas/testsuite/gas/loongarch/load_store_op.s -@@ -167,3 +167,45 @@ stle.b $r4,$r5,$r6 - stle.h $r4,$r5,$r6 - stle.w $r4,$r5,$r6 - stle.d $r4,$r5,$r6 -+sc.q $r4,$r5,$r6,0 -+sc.q $r4,$r5,$r6 -+llacq.w $r4,$r5,0 -+llacq.w $r4,$r5 -+screl.w $r4,$r5,0 -+screl.w $r4,$r5 -+llacq.d $r4,$r5,0 -+llacq.d $r4,$r5 -+screl.d $r4,$r5,0 -+screl.d $r4,$r5 -+amcas.b $r4,$r5,$r6,0 -+amcas.b $r4,$r6,$r5 -+amcas.h $r4,$r5,$r6,0 -+amcas.h $r4,$r6,$r5 -+amcas.w $r4,$r5,$r6,0 -+amcas.w $r4,$r6,$r5 -+amcas.d $r4,$r5,$r6,0 -+amcas.d $r4,$r6,$r5 -+amcas_db.b $r4,$r5,$r6,0 -+amcas_db.b $r4,$r6,$r5 -+amcas_db.h $r4,$r5,$r6,0 -+amcas_db.h $r4,$r6,$r5 -+amcas_db.w $r4,$r5,$r6,0 -+amcas_db.w $r4,$r6,$r5 -+amcas_db.d $r4,$r5,$r6,0 -+amcas_db.d $r4,$r6,$r5 -+amswap.b $r4,$r5,$r6,0 -+amswap.b $r4,$r6,$r5 -+amswap.h $r4,$r5,$r6,0 -+amswap.h $r4,$r6,$r5 -+amadd.b $r4,$r5,$r6,0 -+amadd.b $r4,$r6,$r5 -+amadd.h $r4,$r5,$r6,0 -+amadd.h $r4,$r6,$r5 -+amswap_db.b $r4,$r5,$r6,0 -+amswap_db.b $r4,$r6,$r5 -+amswap_db.h $r4,$r5,$r6,0 -+amswap_db.h $r4,$r6,$r5 -+amadd_db.b $r4,$r5,$r6,0 -+amadd_db.b $r4,$r6,$r5 -+amadd_db.h $r4,$r5,$r6,0 -+amadd_db.h $r4,$r6,$r5 -diff --git a/opcodes/loongarch-opc.c b/opcodes/loongarch-opc.c -index 82b88bdad2a..e110735e857 100644 ---- a/opcodes/loongarch-opc.c -+++ b/opcodes/loongarch-opc.c -@@ -816,6 +816,48 @@ static struct loongarch_opcode loongarch_load_store_opcodes[] = - { 0x38240000, 0xffff8000, "ldx.hu", "r0:5,r5:5,r10:5", 0, 0, 0, 0 }, - { 0x38280000, 0xffff8000, "ldx.wu", "r0:5,r5:5,r10:5", 0, 0, 0, 0 }, - { 0x382c0000, 0xffff8000, "preldx", "u0:5,r5:5,r10:5", 0, 0, 0, 0 }, -+ { 0x0, 0x0, "sc.q", "r,r,r,u0:0", "sc.q %1,%2,%3", 0, 0, 0 }, -+ { 0x38570000, 0xffff8000, "sc.q", "r0:5,r10:5,r5:5", 0, 0, 0, 0 }, -+ { 0x0, 0x0, "llacq.w", "r,r,u0:0", "llacq.w %1,%2", 0, 0, 0 }, -+ { 0x38578000, 0xfffffc00, "llacq.w", "r0:5,r5:5", 0, 0, 0, 0 }, -+ { 0x0, 0x0, "screl.w", "r,r,u0:0", "screl.w %1,%2", 0, 0, 0 }, -+ { 0x38578400, 0xfffffc00, "screl.w", "r0:5,r5:5", 0, 0, 0, 0 }, -+ { 0x0, 0x0, "llacq.d", "r,r,u0:0", "llacq.d %1,%2", 0, 0, 0 }, -+ { 0x38578800, 0xfffffc00, "llacq.d", "r0:5,r5:5", 0, 0, 0, 0 }, -+ { 0x0, 0x0, "screl.d", "r,r,u0:0", "screl.d %1,%2", 0, 0, 0 }, -+ { 0x38578c00, 0xfffffc00, "screl.d", "r0:5,r5:5", 0, 0, 0, 0 }, -+ { 0x0, 0x0, "amcas.b", "r,r,r,u0:0", "amcas.b %1,%2,%3", 0, 0, 0 }, -+ { 0x38580000, 0xffff8000, "amcas.b", "r0:5,r10:5,r5:5", 0, 0, 0, 0 }, -+ { 0x0, 0x0, "amcas.h", "r,r,r,u0:0", "amcas.h %1,%2,%3", 0, 0, 0 }, -+ { 0x38588000, 0xffff8000, "amcas.h", "r0:5,r10:5,r5:5", 0, 0, 0, 0 }, -+ { 0x0, 0x0, "amcas.w", "r,r,r,u0:0", "amcas.w %1,%2,%3", 0, 0, 0 }, -+ { 0x38590000, 0xffff8000, "amcas.w", "r0:5,r10:5,r5:5", 0, 0, 0, 0 }, -+ { 0x0, 0x0, "amcas.d", "r,r,r,u0:0", "amcas.d %1,%2,%3", 0, 0, 0 }, -+ { 0x38598000, 0xffff8000, "amcas.d", "r0:5,r10:5,r5:5", 0, 0, 0, 0 }, -+ { 0x0, 0x0, "amcas_db.b", "r,r,r,u0:0", "amcas_db.b %1,%2,%3", 0, 0, 0 }, -+ { 0x385a0000, 0xffff8000, "amcas_db.b", "r0:5,r10:5,r5:5", 0, 0, 0, 0 }, -+ { 0x0, 0x0, "amcas_db.h", "r,r,r,u0:0", "amcas_db.h %1,%2,%3", 0, 0, 0 }, -+ { 0x385a8000, 0xffff8000, "amcas_db.h", "r0:5,r10:5,r5:5", 0, 0, 0, 0 }, -+ { 0x0, 0x0, "amcas_db.w", "r,r,r,u0:0", "amcas_db.w %1,%2,%3", 0, 0, 0 }, -+ { 0x385b0000, 0xffff8000, "amcas_db.w", "r0:5,r10:5,r5:5", 0, 0, 0, 0 }, -+ { 0x0, 0x0, "amcas_db.d", "r,r,r,u0:0", "amcas_db.d %1,%2,%3", 0, 0, 0 }, -+ { 0x385b8000, 0xffff8000, "amcas_db.d", "r0:5,r10:5,r5:5", 0, 0, 0, 0 }, -+ { 0x0, 0x0, "amswap.b", "r,r,r,u0:0", "amswap.b %1,%2,%3", 0, 0, 0 }, -+ { 0x385c0000, 0xffff8000, "amswap.b", "r0:5,r10:5,r5:5", 0, 0, 0, 0 }, -+ { 0x0, 0x0, "amswap.h", "r,r,r,u0:0", "amswap.h %1,%2,%3", 0, 0, 0 }, -+ { 0x385c8000, 0xffff8000, "amswap.h", "r0:5,r10:5,r5:5", 0, 0, 0, 0 }, -+ { 0x0, 0x0, "amadd.b", "r,r,r,u0:0", "amadd.b %1,%2,%3", 0, 0, 0 }, -+ { 0x385d0000, 0xffff8000, "amadd.b", "r0:5,r10:5,r5:5", 0, 0, 0, 0 }, -+ { 0x0, 0x0, "amadd.h", "r,r,r,u0:0", "amadd.h %1,%2,%3", 0, 0, 0 }, -+ { 0x385d8000, 0xffff8000, "amadd.h", "r0:5,r10:5,r5:5", 0, 0, 0, 0 }, -+ { 0x0, 0x0, "amswap_db.b", "r,r,r,u0:0", "amswap_db.b %1,%2,%3", 0, 0, 0 }, -+ { 0x385e0000, 0xffff8000, "amswap_db.b", "r0:5,r10:5,r5:5", 0, 0, 0, 0 }, -+ { 0x0, 0x0, "amswap_db.h", "r,r,r,u0:0", "amswap_db.h %1,%2,%3", 0, 0, 0 }, -+ { 0x385e8000, 0xffff8000, "amswap_db.h", "r0:5,r10:5,r5:5", 0, 0, 0, 0 }, -+ { 0x0, 0x0, "amadd_db.b", "r,r,r,u0:0", "amadd_db.b %1,%2,%3", 0, 0, 0 }, -+ { 0x385f0000, 0xffff8000, "amadd_db.b", "r0:5,r10:5,r5:5", 0, 0, 0, 0 }, -+ { 0x0, 0x0, "amadd_db.h", "r,r,r,u0:0", "amadd_db.h %1,%2,%3", 0, 0, 0 }, -+ { 0x385f8000, 0xffff8000, "amadd_db.h", "r0:5,r10:5,r5:5", 0, 0, 0, 0 }, - { 0x0, 0x0, "amswap.w", "r,r,r,u0:0", "amswap.w %1,%2,%3", 0, 0, 0 }, - { 0x38600000, 0xffff8000, "amswap.w", "r0:5,r10:5,r5:5", 0, 0, 0, 0 }, - { 0x0, 0x0, "amswap.d", "r,r,r,u0:0", "amswap.d %1,%2,%3", 0, 0, 0 }, --- -2.33.0 - diff --git a/as-Add-new-estimated-reciprocal-instructions-in-Loon.patch b/as-Add-new-estimated-reciprocal-instructions-in-Loon.patch deleted file mode 100644 index 54beba7..0000000 --- a/as-Add-new-estimated-reciprocal-instructions-in-Loon.patch +++ /dev/null @@ -1,128 +0,0 @@ -From cd51849c90e8fd13779bec69f5d4c7aadf03a532 Mon Sep 17 00:00:00 2001 -From: Jiajie Chen -Date: Thu, 26 Oct 2023 17:35:14 +0800 -Subject: [PATCH] as: Add new estimated reciprocal instructions in LoongArch - v1.1 - -New estimated reciprocal instructions in LoongArch v1.1: - -- frecipe.s/d -- frsqrte.s/d -- vfrecipe.s/d -- vfrsqrte.s/d -- xvfrecipe.s/d -- xvfrsqrte.s/d - -Signed-off-by: Jiajie Chen -Signed-off-by: Peng Fan ---- - gas/testsuite/gas/loongarch/float_op.d | 4 ++++ - gas/testsuite/gas/loongarch/float_op.s | 4 ++++ - gas/testsuite/gas/loongarch/vector.d | 8 ++++++++ - gas/testsuite/gas/loongarch/vector.s | 8 ++++++++ - opcodes/loongarch-opc.c | 12 ++++++++++++ - 5 files changed, 36 insertions(+) - -diff --git a/gas/testsuite/gas/loongarch/float_op.d b/gas/testsuite/gas/loongarch/float_op.d -index f9d3b89e4a0..b09e7ba0f21 100644 ---- a/gas/testsuite/gas/loongarch/float_op.d -+++ b/gas/testsuite/gas/loongarch/float_op.d -@@ -83,3 +83,7 @@ Disassembly of section .text: - [ ]+124:[ ]+011d2820 [ ]+ffint.d.l[ ]+[ ]+\$fa0, \$fa1 - [ ]+128:[ ]+011e4420 [ ]+frint.s[ ]+[ ]+\$fa0, \$fa1 - [ ]+12c:[ ]+011e4820 [ ]+frint.d[ ]+[ ]+\$fa0, \$fa1 -+[ ]+130:[ ]+01147420 [ ]+frecipe.s[ ]+[ ]+\$fa0, \$fa1 -+[ ]+134:[ ]+01147820 [ ]+frecipe.d[ ]+[ ]+\$fa0, \$fa1 -+[ ]+138:[ ]+01148420 [ ]+frsqrte.s[ ]+[ ]+\$fa0, \$fa1 -+[ ]+13c:[ ]+01148820 [ ]+frsqrte.d[ ]+[ ]+\$fa0, \$fa1 -diff --git a/gas/testsuite/gas/loongarch/float_op.s b/gas/testsuite/gas/loongarch/float_op.s -index 2e3ec5b8519..a83be3e3e48 100644 ---- a/gas/testsuite/gas/loongarch/float_op.s -+++ b/gas/testsuite/gas/loongarch/float_op.s -@@ -74,3 +74,7 @@ ffint.d.w $f0,$f1 - ffint.d.l $f0,$f1 - frint.s $f0,$f1 - frint.d $f0,$f1 -+frecipe.s $f0,$f1 -+frecipe.d $f0,$f1 -+frsqrte.s $f0,$f1 -+frsqrte.d $f0,$f1 -diff --git a/gas/testsuite/gas/loongarch/vector.d b/gas/testsuite/gas/loongarch/vector.d -index 1a092bca3b8..4526b3d3640 100644 ---- a/gas/testsuite/gas/loongarch/vector.d -+++ b/gas/testsuite/gas/loongarch/vector.d -@@ -1459,3 +1459,11 @@ Disassembly of section .text: - [ ]+16a0:[ ]+77e40420[ ]+xvpermi.w[ ]+\$xr0,[ ]+\$xr1,[ ]+0x1 - [ ]+16a4:[ ]+77e80420[ ]+xvpermi.d[ ]+\$xr0,[ ]+\$xr1,[ ]+0x1 - [ ]+16a8:[ ]+77ec0420[ ]+xvpermi.q[ ]+\$xr0,[ ]+\$xr1,[ ]+0x1 -+[ ]+16ac:[ ]+729d1420[ ]+vfrecipe.s[ ]+\$vr0,[ ]+\$vr1 -+[ ]+16b0:[ ]+729d1820[ ]+vfrecipe.d[ ]+\$vr0,[ ]+\$vr1 -+[ ]+16b4:[ ]+729d2420[ ]+vfrsqrte.s[ ]+\$vr0,[ ]+\$vr1 -+[ ]+16b8:[ ]+729d2820[ ]+vfrsqrte.d[ ]+\$vr0,[ ]+\$vr1 -+[ ]+16bc:[ ]+769d1420[ ]+xvfrecipe.s[ ]+\$xr0,[ ]+\$xr1 -+[ ]+16c0:[ ]+769d1820[ ]+xvfrecipe.d[ ]+\$xr0,[ ]+\$xr1 -+[ ]+16c4:[ ]+769d2420[ ]+xvfrsqrte.s[ ]+\$xr0,[ ]+\$xr1 -+[ ]+16c8:[ ]+769d2820[ ]+xvfrsqrte.d[ ]+\$xr0,[ ]+\$xr1 -diff --git a/gas/testsuite/gas/loongarch/vector.s b/gas/testsuite/gas/loongarch/vector.s -index fe0369e763e..0283a4b4d53 100644 ---- a/gas/testsuite/gas/loongarch/vector.s -+++ b/gas/testsuite/gas/loongarch/vector.s -@@ -1449,3 +1449,11 @@ xvldi $xr0, 1 - xvpermi.w $xr0, $xr1, 1 - xvpermi.d $xr0, $xr1, 1 - xvpermi.q $xr0, $xr1, 1 -+vfrecipe.s $vr0, $vr1 -+vfrecipe.d $vr0, $vr1 -+vfrsqrte.s $vr0, $vr1 -+vfrsqrte.d $vr0, $vr1 -+xvfrecipe.s $xr0, $xr1 -+xvfrecipe.d $xr0, $xr1 -+xvfrsqrte.s $xr0, $xr1 -+xvfrsqrte.d $xr0, $xr1 -diff --git a/opcodes/loongarch-opc.c b/opcodes/loongarch-opc.c -index e110735e857..15c7da6340c 100644 ---- a/opcodes/loongarch-opc.c -+++ b/opcodes/loongarch-opc.c -@@ -482,6 +482,8 @@ static struct loongarch_opcode loongarch_single_float_opcodes[] = - { 0x01144400, 0xfffffc00, "fsqrt.s", "f0:5,f5:5", 0, 0, 0, 0 }, - { 0x01145400, 0xfffffc00, "frecip.s", "f0:5,f5:5", 0, 0, 0, 0 }, - { 0x01146400, 0xfffffc00, "frsqrt.s", "f0:5,f5:5", 0, 0, 0, 0 }, -+ { 0x01147400, 0xfffffc00, "frecipe.s", "f0:5,f5:5", 0, 0, 0, 0 }, -+ { 0x01148400, 0xfffffc00, "frsqrte.s", "f0:5,f5:5", 0, 0, 0, 0 }, - { 0x01149400, 0xfffffc00, "fmov.s", "f0:5,f5:5", 0, 0, 0, 0 }, - { 0x0114a400, 0xfffffc00, "movgr2fr.w", "f0:5,r5:5", 0, 0, 0, 0 }, - { 0x0114ac00, 0xfffffc00, "movgr2frh.w", "f0:5,r5:5", 0, 0, 0, 0 }, -@@ -528,6 +530,8 @@ static struct loongarch_opcode loongarch_double_float_opcodes[] = - { 0x01144800, 0xfffffc00, "fsqrt.d", "f0:5,f5:5", 0, 0, 0, 0 }, - { 0x01145800, 0xfffffc00, "frecip.d", "f0:5,f5:5", 0, 0, 0, 0 }, - { 0x01146800, 0xfffffc00, "frsqrt.d", "f0:5,f5:5", 0, 0, 0, 0 }, -+ { 0x01147800, 0xfffffc00, "frecipe.d", "f0:5,f5:5", 0, 0, 0, 0 }, -+ { 0x01148800, 0xfffffc00, "frsqrte.d", "f0:5,f5:5", 0, 0, 0, 0 }, - { 0x01149800, 0xfffffc00, "fmov.d", "f0:5,f5:5", 0, 0, 0, 0 }, - { 0x0114a800, 0xfffffc00, "movgr2fr.d", "f0:5,r5:5", 0, 0, 0, 0 }, - { 0x0114b800, 0xfffffc00, "movfr2gr.d", "r0:5,f5:5", 0, 0, 0, 0 }, -@@ -1424,6 +1428,10 @@ static struct loongarch_opcode loongarch_lsx_opcodes[] = - { 0x729cf800, 0xfffffc00, "vfrecip.d", "v0:5,v5:5", 0, 0, 0, 0}, - { 0x729d0400, 0xfffffc00, "vfrsqrt.s", "v0:5,v5:5", 0, 0, 0, 0}, - { 0x729d0800, 0xfffffc00, "vfrsqrt.d", "v0:5,v5:5", 0, 0, 0, 0}, -+ { 0x729d1400, 0xfffffc00, "vfrecipe.s", "v0:5,v5:5", 0, 0, 0, 0}, -+ { 0x729d1800, 0xfffffc00, "vfrecipe.d", "v0:5,v5:5", 0, 0, 0, 0}, -+ { 0x729d2400, 0xfffffc00, "vfrsqrte.s", "v0:5,v5:5", 0, 0, 0, 0}, -+ { 0x729d2800, 0xfffffc00, "vfrsqrte.d", "v0:5,v5:5", 0, 0, 0, 0}, - { 0x729d3400, 0xfffffc00, "vfrint.s", "v0:5,v5:5", 0, 0, 0, 0}, - { 0x729d3800, 0xfffffc00, "vfrint.d", "v0:5,v5:5", 0, 0, 0, 0}, - { 0x729d4400, 0xfffffc00, "vfrintrm.s", "v0:5,v5:5", 0, 0, 0, 0}, -@@ -2169,6 +2177,10 @@ static struct loongarch_opcode loongarch_lasx_opcodes[] = - { 0x769cf800, 0xfffffc00, "xvfrecip.d", "x0:5,x5:5", 0, 0, 0, 0}, - { 0x769d0400, 0xfffffc00, "xvfrsqrt.s", "x0:5,x5:5", 0, 0, 0, 0}, - { 0x769d0800, 0xfffffc00, "xvfrsqrt.d", "x0:5,x5:5", 0, 0, 0, 0}, -+ { 0x769d1400, 0xfffffc00, "xvfrecipe.s", "x0:5,x5:5", 0, 0, 0, 0}, -+ { 0x769d1800, 0xfffffc00, "xvfrecipe.d", "x0:5,x5:5", 0, 0, 0, 0}, -+ { 0x769d2400, 0xfffffc00, "xvfrsqrte.s", "x0:5,x5:5", 0, 0, 0, 0}, -+ { 0x769d2800, 0xfffffc00, "xvfrsqrte.d", "x0:5,x5:5", 0, 0, 0, 0}, - { 0x769d3400, 0xfffffc00, "xvfrint.s", "x0:5,x5:5", 0, 0, 0, 0}, - { 0x769d3800, 0xfffffc00, "xvfrint.d", "x0:5,x5:5", 0, 0, 0, 0}, - { 0x769d4400, 0xfffffc00, "xvfrintrm.s", "x0:5,x5:5", 0, 0, 0, 0}, --- -2.33.0 - diff --git a/as-add-option-for-generate-R_LARCH_32-64_PCREL.patch b/as-add-option-for-generate-R_LARCH_32-64_PCREL.patch deleted file mode 100644 index 8d3ff13..0000000 --- a/as-add-option-for-generate-R_LARCH_32-64_PCREL.patch +++ /dev/null @@ -1,132 +0,0 @@ -From fdcb71293e3a3ca4f699a34e2c1f76c42e799f9e Mon Sep 17 00:00:00 2001 -From: cailulu -Date: Thu, 28 Sep 2023 16:01:52 +0800 -Subject: [PATCH 011/123] as: add option for generate R_LARCH_32/64_PCREL. - -Some older kernels cannot handle the newly generated R_LARCH_32/64_PCREL, -so the assembler generates R_LARCH_ADD32/64+R_LARCH_SUB32/64 by default, -and use the assembler option mthin-add-sub to generate R_LARCH_32/64_PCREL -as much as possible. - -The Option of mthin-add-sub does not affect the generation of R_LARCH_32_PCREL -relocation in .eh_frame. ---- - gas/config/tc-loongarch.c | 29 +++++++++++++++++++++++++++++ - gas/config/tc-loongarch.h | 13 +++++++------ - include/opcode/loongarch.h | 1 + - 3 files changed, 37 insertions(+), 6 deletions(-) - -diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c -index 38a51fc2..4c48382c 100644 ---- a/gas/config/tc-loongarch.c -+++ b/gas/config/tc-loongarch.c -@@ -120,6 +120,7 @@ enum options - OPTION_LA_GLOBAL_WITH_ABS, - OPTION_RELAX, - OPTION_NO_RELAX, -+ OPTION_THIN_ADD_SUB, - - OPTION_END_OF_ENUM, - }; -@@ -136,6 +137,7 @@ struct option md_longopts[] = - - { "mrelax", no_argument, NULL, OPTION_RELAX }, - { "mno-relax", no_argument, NULL, OPTION_NO_RELAX }, -+ { "mthin-add-sub", no_argument, NULL, OPTION_THIN_ADD_SUB}, - - { NULL, no_argument, NULL, 0 } - }; -@@ -214,6 +216,10 @@ md_parse_option (int c, const char *arg) - LARCH_opts.relax = 0; - break; - -+ case OPTION_THIN_ADD_SUB: -+ LARCH_opts.thin_add_sub = 1; -+ break; -+ - case OPTION_IGNORE: - break; - -@@ -1197,6 +1203,7 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) - static int64_t stack_top; - static int last_reloc_is_sop_push_pcrel_1 = 0; - int last_reloc_is_sop_push_pcrel = last_reloc_is_sop_push_pcrel_1; -+ segT sub_segment; - last_reloc_is_sop_push_pcrel_1 = 0; - - char *buf = fixP->fx_frag->fr_literal + fixP->fx_where; -@@ -1289,6 +1296,23 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) - } - } - -+ /* If symbol in .eh_frame the address may be adjusted, and contents of -+ .eh_frame will be adjusted, so use pc-relative relocation for FDE -+ initial location. -+ The Option of mthin-add-sub does not affect the generation of -+ R_LARCH_32_PCREL relocation in .eh_frame. */ -+ if (fixP->fx_r_type == BFD_RELOC_32 -+ && fixP->fx_addsy && fixP->fx_subsy -+ && (sub_segment = S_GET_SEGMENT (fixP->fx_subsy)) -+ && strcmp (sub_segment->name, ".eh_frame") == 0 -+ && S_GET_VALUE (fixP->fx_subsy) -+ == fixP->fx_frag->fr_address + fixP->fx_where) -+ { -+ fixP->fx_r_type = BFD_RELOC_LARCH_32_PCREL; -+ fixP->fx_subsy = NULL; -+ break; -+ } -+ - if (fixP->fx_addsy && fixP->fx_subsy) - { - fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP)); -@@ -1591,6 +1615,11 @@ md_show_usage (FILE *stream) - { - fprintf (stream, _("LARCH options:\n")); - /* FIXME */ -+ fprintf (stream, _("\ -+ -mthin-add-sub Convert a pair of R_LARCH_ADD32/64 and R_LARCH_SUB32/64 to\n\ -+ R_LARCH_32/64_PCREL as much as possible\n\ -+ The option does not affect the generation of R_LARCH_32_PCREL\n\ -+ relocations in .eh_frame\n")); - } - - static void -diff --git a/gas/config/tc-loongarch.h b/gas/config/tc-loongarch.h -index fd094356..4afa3842 100644 ---- a/gas/config/tc-loongarch.h -+++ b/gas/config/tc-loongarch.h -@@ -75,12 +75,13 @@ extern bool loongarch_frag_align_code (int); - or PC at start of subsy or with relax but sub_symbol_segment not in - SEC_CODE, we generate 32/64_PCREL. */ - #define TC_FORCE_RELOCATION_SUB_LOCAL(FIX, SEG) \ -- (!((BFD_RELOC_32 || BFD_RELOC_64) \ -- &&(!LARCH_opts.relax \ -- || S_GET_VALUE (FIX->fx_subsy) \ -- == FIX->fx_frag->fr_address + FIX->fx_where \ -- || (LARCH_opts.relax \ -- && ((S_GET_SEGMENT (FIX->fx_subsy)->flags & SEC_CODE) == 0))))) -+ (!(LARCH_opts.thin_add_sub \ -+ && (BFD_RELOC_32 || BFD_RELOC_64) \ -+ && (!LARCH_opts.relax \ -+ || S_GET_VALUE (FIX->fx_subsy) \ -+ == FIX->fx_frag->fr_address + FIX->fx_where \ -+ || (LARCH_opts.relax \ -+ && ((S_GET_SEGMENT (FIX->fx_subsy)->flags & SEC_CODE) == 0))))) - - #define TC_VALIDATE_FIX_SUB(FIX, SEG) 1 - #define DIFF_EXPR_OK 1 -diff --git a/include/opcode/loongarch.h b/include/opcode/loongarch.h -index e145db5e..2ed4082c 100644 ---- a/include/opcode/loongarch.h -+++ b/include/opcode/loongarch.h -@@ -236,6 +236,7 @@ dec2 : [1-9][0-9]? - #define ase_gabs isa.use_la_global_with_abs - - int relax; -+ int thin_add_sub; - } LARCH_opts; - - extern size_t loongarch_insn_length (insn_t insn); --- -2.33.0 - diff --git a/as-fixed-internal-error-when-immediate-value-of-relo.patch b/as-fixed-internal-error-when-immediate-value-of-relo.patch deleted file mode 100644 index e51f726..0000000 --- a/as-fixed-internal-error-when-immediate-value-of-relo.patch +++ /dev/null @@ -1,140 +0,0 @@ -From 690ba386f3729db0f466f607eb0e53c1ed0c431f Mon Sep 17 00:00:00 2001 -From: Lulu Cai -Date: Wed, 11 Oct 2023 10:20:45 +0800 -Subject: [PATCH 016/123] as: fixed internal error when immediate value of - relocation overflow. - -The as and ld use _bfd_error_handler to output error messages when -checking relocation alignment and relocation overflow. However, the -abfd value passed by as to the function is NULL, resulting in an -internal error. The ld passes a non-null value to the function, -so it can output an error message normally. ---- - bfd/elfxx-loongarch.c | 22 ++++++++++++++++------ - gas/config/tc-loongarch.c | 2 +- - gas/testsuite/gas/loongarch/imm_overflow.d | 3 +++ - gas/testsuite/gas/loongarch/imm_overflow.l | 2 ++ - gas/testsuite/gas/loongarch/imm_overflow.s | 4 ++++ - gas/testsuite/gas/loongarch/imm_unalign.d | 3 +++ - gas/testsuite/gas/loongarch/imm_unalign.l | 2 ++ - gas/testsuite/gas/loongarch/imm_unalign.s | 6 ++++++ - 8 files changed, 37 insertions(+), 7 deletions(-) - create mode 100644 gas/testsuite/gas/loongarch/imm_overflow.d - create mode 100644 gas/testsuite/gas/loongarch/imm_overflow.l - create mode 100644 gas/testsuite/gas/loongarch/imm_overflow.s - create mode 100644 gas/testsuite/gas/loongarch/imm_unalign.d - create mode 100644 gas/testsuite/gas/loongarch/imm_unalign.l - create mode 100644 gas/testsuite/gas/loongarch/imm_unalign.s - -diff --git a/bfd/elfxx-loongarch.c b/bfd/elfxx-loongarch.c -index fd9507ce..7f298c08 100644 ---- a/bfd/elfxx-loongarch.c -+++ b/bfd/elfxx-loongarch.c -@@ -1679,9 +1679,14 @@ reloc_sign_bits (bfd *abfd, reloc_howto_type *howto, bfd_vma *fix_val) - if (howto->rightshift - && (val & ((((bfd_signed_vma) 1) << howto->rightshift) - 1))) - { -- (*_bfd_error_handler) (_("%pB: relocation %s right shift %d error 0x%lx"), -- abfd, howto->name, howto->rightshift, (long) val); -- bfd_set_error (bfd_error_bad_value); -+ /* The as passes NULL casued internal error, so it can not use _bfd_error_handler -+ output details, ld is not affected. */ -+ if (abfd != NULL) -+ { -+ (*_bfd_error_handler) (_("%pB: relocation %s right shift %d error 0x%lx"), -+ abfd, howto->name, howto->rightshift, (long) val); -+ bfd_set_error (bfd_error_bad_value); -+ } - return false; - } - -@@ -1693,9 +1698,14 @@ reloc_sign_bits (bfd *abfd, reloc_howto_type *howto, bfd_vma *fix_val) - high part: from sign bit to highest bit. */ - if ((val & ~mask) && ((val & ~mask) != ~mask)) - { -- (*_bfd_error_handler) (_("%pB: relocation %s overflow 0x%lx"), -- abfd, howto->name, (long) val); -- bfd_set_error (bfd_error_bad_value); -+ /* The as passes NULL casued internal error, so it can not use _bfd_error_handler -+ output details, ld is not affected. */ -+ if (abfd != NULL) -+ { -+ (*_bfd_error_handler) (_("%pB: relocation %s overflow 0x%lx"), -+ abfd, howto->name, (long) val); -+ bfd_set_error (bfd_error_bad_value); -+ } - return false; - } - -diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c -index 059a1711..49c70bf1 100644 ---- a/gas/config/tc-loongarch.c -+++ b/gas/config/tc-loongarch.c -@@ -1236,7 +1236,7 @@ static void fix_reloc_insn (fixS *fixP, bfd_vma reloc_val, char *buf) - insn = bfd_getl32 (buf); - - if (!loongarch_adjust_reloc_bitsfield (NULL, howto, &reloc_val)) -- as_warn_where (fixP->fx_file, fixP->fx_line, "Reloc overflow"); -+ as_bad_where (fixP->fx_file, fixP->fx_line, "Reloc overflow"); - - insn = (insn & (insn_t)howto->src_mask) - | ((insn & (~(insn_t)howto->dst_mask)) | reloc_val); -diff --git a/gas/testsuite/gas/loongarch/imm_overflow.d b/gas/testsuite/gas/loongarch/imm_overflow.d -new file mode 100644 -index 00000000..50a65b7c ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/imm_overflow.d -@@ -0,0 +1,3 @@ -+#as: -+#source: imm_overflow.s -+#error_output: imm_overflow.l -diff --git a/gas/testsuite/gas/loongarch/imm_overflow.l b/gas/testsuite/gas/loongarch/imm_overflow.l -new file mode 100644 -index 00000000..449b3c2a ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/imm_overflow.l -@@ -0,0 +1,2 @@ -+.*Assembler messages: -+.*Error: Reloc overflow -diff --git a/gas/testsuite/gas/loongarch/imm_overflow.s b/gas/testsuite/gas/loongarch/imm_overflow.s -new file mode 100644 -index 00000000..9aac396a ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/imm_overflow.s -@@ -0,0 +1,4 @@ -+.L1: -+ nop -+ .fill 0x3ffffff, 4, 0 -+ b .L1 -diff --git a/gas/testsuite/gas/loongarch/imm_unalign.d b/gas/testsuite/gas/loongarch/imm_unalign.d -new file mode 100644 -index 00000000..1deb5025 ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/imm_unalign.d -@@ -0,0 +1,3 @@ -+#as: -+#source: imm_unalign.s -+#error_output: imm_unalign.l -diff --git a/gas/testsuite/gas/loongarch/imm_unalign.l b/gas/testsuite/gas/loongarch/imm_unalign.l -new file mode 100644 -index 00000000..449b3c2a ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/imm_unalign.l -@@ -0,0 +1,2 @@ -+.*Assembler messages: -+.*Error: Reloc overflow -diff --git a/gas/testsuite/gas/loongarch/imm_unalign.s b/gas/testsuite/gas/loongarch/imm_unalign.s -new file mode 100644 -index 00000000..a853bdcb ---- /dev/null -+++ b/gas/testsuite/gas/loongarch/imm_unalign.s -@@ -0,0 +1,6 @@ -+.L1: -+ .2byte 0x12 -+ -+.L2: -+ .fill 1, 4, 0 -+ b .L1 --- -2.33.0 - diff --git a/asan-buffer-overflow-in-loongarch_elf_rtype_to_howto.patch b/asan-buffer-overflow-in-loongarch_elf_rtype_to_howto.patch deleted file mode 100644 index 8a6f425..0000000 --- a/asan-buffer-overflow-in-loongarch_elf_rtype_to_howto.patch +++ /dev/null @@ -1,110 +0,0 @@ -From 4eb7459bdbdb37611f8d993171c5d72fa347a143 Mon Sep 17 00:00:00 2001 -From: Alan Modra -Date: Tue, 26 Dec 2023 22:46:56 +1030 -Subject: [PATCH 030/123] asan: buffer overflow in loongarch_elf_rtype_to_howto - -Seen when running ld-loongarch-elf/tlsdesc-dso test. -elfxx-loongarch.c:1844:32: runtime error: index 125 out of bounds for -type 'loongarch_reloc_howto_type [124]' - -So either the loongarch_howto_table needs three more -LOONGARCH_EMPTY_HOWTO entries, or loongarch_elf_rtype_to_howto should -be testing for r_type < ARRAY_SIZE (loongarch_howto_table). I figure -it's worth wasting a little more space to get faster lookup. - - * elfxx-loongarch.c (loongarch_howto_table): Add - LOONGARCH_EMPTY_HOWTO entries for 121..123. - (loongarch_elf_rtype_to_howto): Don't support slow lookup. - Assert exact table size and r_type indexing. Omit return cast. - (loongarch_reloc_name_lookup): Omit assertion and return cast. - (loongarch_reloc_type_lookup): Likewise. ---- - bfd/elfxx-loongarch.c | 32 +++++++++++--------------------- - 1 file changed, 11 insertions(+), 21 deletions(-) - -diff --git a/bfd/elfxx-loongarch.c b/bfd/elfxx-loongarch.c -index 310e6d62..4fe8cbff 100644 ---- a/bfd/elfxx-loongarch.c -+++ b/bfd/elfxx-loongarch.c -@@ -1776,6 +1776,10 @@ static loongarch_reloc_howto_type loongarch_howto_table[] = - NULL, /* adjust_reloc_bits. */ - "desc_call"), /* larch_reloc_type_name. */ - -+ LOONGARCH_EMPTY_HOWTO (121), -+ LOONGARCH_EMPTY_HOWTO (122), -+ LOONGARCH_EMPTY_HOWTO (123), -+ - /* For pcaddi, ld_pc_hi20 + ld_pc_lo12 can relax to ld_pcrel20_s2. */ - LOONGARCH_HOWTO (R_LARCH_TLS_LD_PCREL20_S2, /* type (124). */ - 2, /* rightshift. */ -@@ -1834,19 +1838,11 @@ static loongarch_reloc_howto_type loongarch_howto_table[] = - reloc_howto_type * - loongarch_elf_rtype_to_howto (bfd *abfd, unsigned int r_type) - { -- if(r_type < R_LARCH_count) -+ if (r_type < R_LARCH_count) - { -- /* For search table fast. */ -- /* - BFD_ASSERT (ARRAY_SIZE (loongarch_howto_table) == R_LARCH_count); -- */ -- -- if (loongarch_howto_table[r_type].howto.type == r_type) -- return (reloc_howto_type *)&loongarch_howto_table[r_type]; -- -- for (size_t i = 0; i < ARRAY_SIZE (loongarch_howto_table); i++) -- if (loongarch_howto_table[i].howto.type == r_type) -- return (reloc_howto_type *)&loongarch_howto_table[i]; -+ BFD_ASSERT (loongarch_howto_table[r_type].howto.type == r_type); -+ return &loongarch_howto_table[r_type].howto; - } - - (*_bfd_error_handler) (_("%pB: unsupported relocation type %#x"), -@@ -1858,19 +1854,14 @@ loongarch_elf_rtype_to_howto (bfd *abfd, unsigned int r_type) - reloc_howto_type * - loongarch_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED, const char *r_name) - { -- /* -- BFD_ASSERT (ARRAY_SIZE (loongarch_howto_table) == R_LARCH_count); -- */ -- - for (size_t i = 0; i < ARRAY_SIZE (loongarch_howto_table); i++) - if (loongarch_howto_table[i].howto.name - && strcasecmp (loongarch_howto_table[i].howto.name, r_name) == 0) -- return (reloc_howto_type *)&loongarch_howto_table[i]; -+ return &loongarch_howto_table[i].howto; - - (*_bfd_error_handler) (_("%pB: unsupported relocation type %s"), - abfd, r_name); - bfd_set_error (bfd_error_bad_value); -- - return NULL; - } - -@@ -1888,20 +1879,19 @@ loongarch_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED, - { - BFD_ASSERT (BFD_RELOC_LARCH_RELAX - BFD_RELOC_LARCH_B16 - == R_LARCH_RELAX - R_LARCH_B16); -- loongarch_reloc_howto_type *ht = NULL; -+ loongarch_reloc_howto_type *ht; - ht = &loongarch_howto_table[code - BFD_RELOC_LARCH_B16 + R_LARCH_B16]; - BFD_ASSERT (ht->bfd_type == code); -- return (reloc_howto_type *)ht; -+ return &ht->howto; - } - - for (size_t i = 0; i < ARRAY_SIZE (loongarch_howto_table); i++) - if (loongarch_howto_table[i].bfd_type == code) -- return (reloc_howto_type *)&loongarch_howto_table[i]; -+ return &loongarch_howto_table[i].howto; - - (*_bfd_error_handler) (_("%pB: unsupported bfd relocation type %#x"), - abfd, code); - bfd_set_error (bfd_error_bad_value); -- - return NULL; - } - --- -2.33.0 - diff --git a/backport-CVE-2025-0840.patch b/backport-CVE-2025-0840.patch deleted file mode 100644 index 6cd6b0d..0000000 --- a/backport-CVE-2025-0840.patch +++ /dev/null @@ -1,54 +0,0 @@ -From baac6c221e9d69335bf41366a1c7d87d8ab2f893 Mon Sep 17 00:00:00 2001 -From: Alan Modra -Date: Wed, 15 Jan 2025 19:13:43 +1030 -Subject: [PATCH] PR32560 stack-buffer-overflow at objdump disassemble_bytes - -There's always someone pushing the boundaries. - - PR 32560 - * objdump.c (MAX_INSN_WIDTH): Define. - (insn_width): Make it an unsigned long. - (disassemble_bytes): Use MAX_INSN_WIDTH to size buffer. - (main ): Restrict size of insn_width. ---- - binutils/objdump.c | 10 ++++++---- - 1 file changed, 6 insertions(+), 4 deletions(-) - -diff --git a/binutils/objdump.c b/binutils/objdump.c -index ecbe39e942e..80044dea580 100644 ---- a/binutils/objdump.c -+++ b/binutils/objdump.c -@@ -117,7 +117,8 @@ static bool disassemble_all; /* -D */ - static int disassemble_zeroes; /* --disassemble-zeroes */ - static bool formats_info; /* -i */ - int wide_output; /* -w */ --static int insn_width; /* --insn-width */ -+#define MAX_INSN_WIDTH 49 -+static unsigned long insn_width; /* --insn-width */ - static bfd_vma start_address = (bfd_vma) -1; /* --start-address */ - static bfd_vma stop_address = (bfd_vma) -1; /* --stop-address */ - static int dump_debugging; /* --debugging */ -@@ -3391,7 +3392,7 @@ disassemble_bytes (struct disassemble_info *inf, - } - else - { -- char buf[50]; -+ char buf[MAX_INSN_WIDTH + 1]; - unsigned int bpc = 0; - unsigned int pb = 0; - -@@ -6070,8 +6071,9 @@ main (int argc, char **argv) - break; - case OPTION_INSN_WIDTH: - insn_width = strtoul (optarg, NULL, 0); -- if (insn_width <= 0) -- fatal (_("error: instruction width must be positive")); -+ if (insn_width - 1 >= MAX_INSN_WIDTH) -+ fatal (_("error: instruction width must be in the range 1 to " -+ XSTRING (MAX_INSN_WIDTH))); - break; - case OPTION_INLINES: - unwind_inlines = true; --- -2.43.5 - diff --git a/backport-PR32399-buffer-overflow-printing-core_file_failing_c.patch b/backport-PR32399-buffer-overflow-printing-core_file_failing_c.patch deleted file mode 100644 index f7a9f93..0000000 --- a/backport-PR32399-buffer-overflow-printing-core_file_failing_c.patch +++ /dev/null @@ -1,118 +0,0 @@ -From 1e3b2da08eb21042f01a9f6862b487ca77484c92 Mon Sep 17 00:00:00 2001 -From: Alan Modra -Date: Fri, 29 Nov 2024 10:18:36 +1030 -Subject: [PATCH] PR32399, buffer overflow printing core_file_failing_command - -Assorted targets do not check, as the ELF targets do, that the program -name in a core file is NUL terminated. Fix some of them. I haven't -attempted to fix all targets because editing host specific code can -easily result in build bugs, which aren't discovered until someone -build binutils for that host. (Of the files edited here, I can't -easily compile hpux-core.c and osf-core.c on a linux system.) - - PR 32399 - * hppabsd-core.c (hppabsd_core_core_file_p): Ensure core_command - string is terminated. - * hpux-core.c (hpux_core_core_file_p): Likewise. - * irix-core.c (irix_core_core_file_p): Likewise. - * lynx-core.c (lynx_core_file_p): Likewise. - * osf-core.c (osf_core_core_file_p): Likewise. - * mach-o.c (bfd_mach_o_core_file_failing_command): Likewise. ---- - bfd/hppabsd-core.c | 3 ++- - bfd/hpux-core.c | 3 ++- - bfd/irix-core.c | 3 ++- - bfd/lynx-core.c | 3 ++- - bfd/mach-o.c | 4 ++-- - bfd/osf-core.c | 3 ++- - 6 files changed, 12 insertions(+), 7 deletions(-) - -diff --git a/bfd/hppabsd-core.c b/bfd/hppabsd-core.c -index ae5d1f8f1e5..1c24e641b3a 100644 ---- a/bfd/hppabsd-core.c -+++ b/bfd/hppabsd-core.c -@@ -179,7 +179,8 @@ hppabsd_core_core_file_p (bfd *abfd) - goto fail; - core_regsec (abfd)->vma = 0; - -- strncpy (core_command (abfd), u.u_comm, MAXCOMLEN + 1); -+ strncpy (core_command (abfd), u.u_comm, MAXCOMLEN); -+ core_command (abfd)[MAXCOMLEN] = 0; - core_signal (abfd) = u.u_code; - return _bfd_no_cleanup; - -diff --git a/bfd/hpux-core.c b/bfd/hpux-core.c -index 1e2ea926f02..18516e3a897 100644 ---- a/bfd/hpux-core.c -+++ b/bfd/hpux-core.c -@@ -177,7 +177,8 @@ hpux_core_core_file_p (bfd *abfd) - if (bfd_bread ((void *) &proc_exec, (bfd_size_type) core_header.len, - abfd) != core_header.len) - break; -- strncpy (core_command (abfd), proc_exec.cmd, MAXCOMLEN + 1); -+ strncpy (core_command (abfd), proc_exec.cmd, MAXCOMLEN); -+ core_command (abfd)[MAXCOMLEN] = 0; - good_sections++; - } - break; -diff --git a/bfd/irix-core.c b/bfd/irix-core.c -index 80cb82d0fa3..7a486841d35 100644 ---- a/bfd/irix-core.c -+++ b/bfd/irix-core.c -@@ -203,7 +203,8 @@ irix_core_core_file_p (bfd *abfd) - if (!core_hdr (abfd)) - return NULL; - -- strncpy (core_command (abfd), coreout.c_name, CORE_NAMESIZE); -+ strncpy (core_command (abfd), coreout.c_name, CORE_NAMESIZE - 1); -+ core_command (abfd)[CORE_NAMESIZE - 1] = 0; - core_signal (abfd) = coreout.c_sigcause; - - if (bfd_seek (abfd, coreout.c_vmapoffset, SEEK_SET) != 0) -diff --git a/bfd/lynx-core.c b/bfd/lynx-core.c -index 44d94ad8745..7870dc62866 100644 ---- a/bfd/lynx-core.c -+++ b/bfd/lynx-core.c -@@ -120,7 +120,8 @@ lynx_core_file_p (bfd *abfd) - if (!core_hdr (abfd)) - return NULL; - -- strncpy (core_command (abfd), pss.pname, PNMLEN + 1); -+ strncpy (core_command (abfd), pss.pname, PNMLEN); -+ core_command (abfd)[PNMLEN] = 0; - - /* Compute the size of the thread contexts */ - -diff --git a/bfd/mach-o.c b/bfd/mach-o.c -index 974747caadd..037718fb22c 100644 ---- a/bfd/mach-o.c -+++ b/bfd/mach-o.c -@@ -6019,9 +6019,9 @@ bfd_mach_o_core_file_failing_command (bfd *abfd) - int ret; - - ret = bfd_mach_o_core_fetch_environment (abfd, &buf, &len); -- if (ret < 0) -+ if (ret < 0 || len == 0) - return NULL; -- -+ buf[len - 1] = 0; - return (char *) buf; - } - -diff --git a/bfd/osf-core.c b/bfd/osf-core.c -index 55b127d48b3..6869dfa23ea 100644 ---- a/bfd/osf-core.c -+++ b/bfd/osf-core.c -@@ -92,7 +92,8 @@ osf_core_core_file_p (bfd *abfd) - if (!core_hdr (abfd)) - return NULL; - -- strncpy (core_command (abfd), core_header.name, MAXCOMLEN + 1); -+ strncpy (core_command (abfd), core_header.name, MAXCOMLEN); -+ core_command (abfd)[MAXCOMLEN] = 0; - core_signal (abfd) = core_header.signo; - - for (i = 0; i < core_header.nscns; i++) --- -2.28.0.windows.1 - diff --git a/backport-Re-PR32399-buffer-overflow-printing-core_file_failin.patch b/backport-Re-PR32399-buffer-overflow-printing-core_file_failin.patch deleted file mode 100644 index c3c59f2..0000000 --- a/backport-Re-PR32399-buffer-overflow-printing-core_file_failin.patch +++ /dev/null @@ -1,220 +0,0 @@ -From 8ab91a033555c5faae1bcd615800670b91673731 Mon Sep 17 00:00:00 2001 -From: Alan Modra -Date: Sat, 30 Nov 2024 16:41:14 +1030 -Subject: [PATCH] Re: PR32399, buffer overflow printing - core_file_failing_command - -Fix more potential buffer overflows, and correct trad-code.c and -cisco-core.c where they should be using bfd_{z}alloc rather than -bfd_{z}malloc. To stop buffer overflows with fuzzed objects that -don't have a terminator on the core_file_failing_command string, this -patch allocates an extra byte at the end of the entire header buffer -rather than poking a NUL at the end of the name array (u_comm[] or -similar) because (a) it's better to not overwrite the file data, and -(b) it is possible that some core files make use of fields in struct -user beyond the end of u_comm to extend the command name. The patch -also changes some unnecessary uses of bfd_zalloc to bfd_alloc. -There's not much point in clearing memeory that will shortly be -completely overwritten. - - PR 32399 - * aix5ppc-core.c (xcoff64_core_p): Allocate an extra byte to - ensure the core_file_failing_command string is terminated. - * netbsd-core.c (netbsd_core_file_p): Likewise. - * ptrace-core.c (ptrace_unix_core_file_p): Likewise. - * rs6000-core.c (rs6000coff_core_p): Likewise. - * trad-core.c (trad_unix_core_file_p): Likewise, and bfd_alloc - tdata rather than bfd_zmalloc. - * cisco-core.c (cisco_core_file_validate): bfd_zalloc tdata. ---- - bfd/aix5ppc-core.c | 15 ++++++++------- - bfd/cisco-core.c | 2 +- - bfd/netbsd-core.c | 14 ++++++++------ - bfd/ptrace-core.c | 8 +++++--- - bfd/rs6000-core.c | 5 ++++- - bfd/trad-core.c | 8 +++++--- - 6 files changed, 31 insertions(+), 21 deletions(-) - -diff --git a/bfd/aix5ppc-core.c b/bfd/aix5ppc-core.c -index 179a7bf5b78..a6d6449fc57 100644 ---- a/bfd/aix5ppc-core.c -+++ b/bfd/aix5ppc-core.c -@@ -66,8 +66,7 @@ xcoff64_core_p (bfd *abfd) - if (bfd_seek (abfd, 0, SEEK_SET) != 0) - goto xcoff64_core_p_error; - -- if (sizeof (struct core_dumpxx) -- != bfd_bread (&core, sizeof (struct core_dumpxx), abfd)) -+ if (sizeof core != bfd_bread (&core, sizeof core, abfd)) - goto xcoff64_core_p_error; - - if (bfd_stat (abfd, &statbuf) < 0) -@@ -111,14 +110,16 @@ xcoff64_core_p (bfd *abfd) - return NULL; - } - -- new_core_hdr = bfd_zalloc (abfd, sizeof (struct core_dumpxx)); -+ new_core_hdr = bfd_alloc (abfd, sizeof (*new_core_hdr) + 1); - if (NULL == new_core_hdr) - return NULL; - -- memcpy (new_core_hdr, &core, sizeof (struct core_dumpxx)); -- /* The core_hdr() macro is no longer used here because it would -- expand to code relying on gcc's cast-as-lvalue extension, -- which was removed in gcc 4.0. */ -+ memcpy (new_core_hdr, &core, sizeof (*new_core_hdr)); -+ -+ /* Ensure core_file_failing_command string is terminated. This is -+ just to stop buffer overflows on fuzzed files. */ -+ ((char *) new_core_hdr)[sizeof (*new_core_hdr)] = 0; -+ - abfd->tdata.any = new_core_hdr; - - /* .stack section. */ -diff --git a/bfd/cisco-core.c b/bfd/cisco-core.c -index 75b11150f6d..1bbb44192ff 100644 ---- a/bfd/cisco-core.c -+++ b/bfd/cisco-core.c -@@ -154,7 +154,7 @@ cisco_core_file_validate (bfd *abfd, int crash_info_loc) - /* OK, we believe you. You're a core file. */ - - amt = sizeof (struct cisco_core_struct); -- abfd->tdata.cisco_core_data = (struct cisco_core_struct *) bfd_zmalloc (amt); -+ abfd->tdata.cisco_core_data = bfd_zalloc (abfd, amt); - if (abfd->tdata.cisco_core_data == NULL) - return NULL; - -diff --git a/bfd/netbsd-core.c b/bfd/netbsd-core.c -index 647af9d7bc2..ae56f3913e4 100644 ---- a/bfd/netbsd-core.c -+++ b/bfd/netbsd-core.c -@@ -47,7 +47,7 @@ - struct netbsd_core_struct - { - struct core core; --} *rawptr; -+}; - - /* Handle NetBSD-style core dump file. */ - -@@ -60,9 +60,9 @@ netbsd_core_file_p (bfd *abfd) - asection *asect; - struct core core; - struct coreseg coreseg; -- size_t amt = sizeof core; -+ struct netbsd_core_struct *rawptr; - -- val = bfd_bread (&core, amt, abfd); -+ val = bfd_bread (&core, sizeof core, abfd); - if (val != sizeof core) - { - /* Too small to be a core file. */ -@@ -76,13 +76,15 @@ netbsd_core_file_p (bfd *abfd) - return 0; - } - -- amt = sizeof (struct netbsd_core_struct); -- rawptr = (struct netbsd_core_struct *) bfd_zalloc (abfd, amt); -+ rawptr = bfd_alloc (abfd, sizeof (*rawptr) + 1); - if (rawptr == NULL) - return 0; - -- rawptr->core = core; - abfd->tdata.netbsd_core_data = rawptr; -+ rawptr->core = core; -+ /* Ensure core_file_failing_command string is terminated. This is -+ just to stop buffer overflows on fuzzed files. */ -+ ((char *) rawptr)[sizeof (*rawptr)] = 0; - - offset = core.c_hdrsize; - for (i = 0; i < core.c_nseg; i++) -diff --git a/bfd/ptrace-core.c b/bfd/ptrace-core.c -index 426d6070dc8..5952c06f8b6 100644 ---- a/bfd/ptrace-core.c -+++ b/bfd/ptrace-core.c -@@ -61,7 +61,6 @@ ptrace_unix_core_file_p (bfd *abfd) - int val; - struct ptrace_user u; - struct trad_core_struct *rawptr; -- size_t amt; - flagword flags; - - val = bfd_bread ((void *)&u, (bfd_size_type) sizeof u, abfd); -@@ -77,8 +76,7 @@ ptrace_unix_core_file_p (bfd *abfd) - - /* Allocate both the upage and the struct core_data at once, so - a single free() will free them both. */ -- amt = sizeof (struct trad_core_struct); -- rawptr = (struct trad_core_struct *) bfd_zalloc (abfd, amt); -+ rawptr = bfd_alloc (abfd, sizeof (*rawptr) + 1); - - if (rawptr == NULL) - return 0; -@@ -87,6 +85,10 @@ ptrace_unix_core_file_p (bfd *abfd) - - rawptr->u = u; /*Copy the uarea into the tdata part of the bfd */ - -+ /* Ensure core_file_failing_command string is terminated. This is -+ just to stop buffer overflows on fuzzed files. */ -+ ((char *) rawptr)[sizeof (*rawptr)] = 0; -+ - /* Create the sections. */ - - flags = SEC_ALLOC + SEC_LOAD + SEC_HAS_CONTENTS; -diff --git a/bfd/rs6000-core.c b/bfd/rs6000-core.c -index 19b9f46631f..ac8b29838ad 100644 ---- a/bfd/rs6000-core.c -+++ b/bfd/rs6000-core.c -@@ -476,12 +476,15 @@ rs6000coff_core_p (bfd *abfd) - #else - size = sizeof (core.new_dump); - #endif -- tmpptr = (char *) bfd_zalloc (abfd, (bfd_size_type) size); -+ tmpptr = bfd_alloc (abfd, size + 1); - if (!tmpptr) - return NULL; - - /* Copy core file header. */ - memcpy (tmpptr, &core, size); -+ /* Ensure core_file_failing_command string is terminated. This is -+ just to stop buffer overflows on fuzzed files. */ -+ tmpptr[size] = 0; - set_tdata (abfd, tmpptr); - - /* Set architecture. */ -diff --git a/bfd/trad-core.c b/bfd/trad-core.c -index 012bc4bdd01..06b6bdadd87 100644 ---- a/bfd/trad-core.c -+++ b/bfd/trad-core.c -@@ -65,7 +65,6 @@ trad_unix_core_file_p (bfd *abfd) - int val; - struct user u; - struct trad_core_struct *rawptr; -- size_t amt; - flagword flags; - - #ifdef TRAD_CORE_USER_OFFSET -@@ -132,8 +131,7 @@ trad_unix_core_file_p (bfd *abfd) - - /* Allocate both the upage and the struct core_data at once, so - a single free() will free them both. */ -- amt = sizeof (struct trad_core_struct); -- rawptr = (struct trad_core_struct *) bfd_zmalloc (amt); -+ rawptr = bfd_alloc (abfd, sizeof (*rawptr) + 1); - if (rawptr == NULL) - return 0; - -@@ -141,6 +139,10 @@ trad_unix_core_file_p (bfd *abfd) - - rawptr->u = u; /*Copy the uarea into the tdata part of the bfd */ - -+ /* Ensure core_file_failing_command string is terminated. This is -+ just to stop buffer overflows on fuzzed files. */ -+ ((char *) rawptr)[sizeof (*rawptr)] = 0; -+ - /* Create the sections. */ - - flags = SEC_ALLOC + SEC_LOAD + SEC_HAS_CONTENTS; --- -2.28.0.windows.1 - diff --git a/backport-ld-Remove-JANSSON_LIBS-from-ld_new_DEPENDENCIES.patch b/backport-ld-Remove-JANSSON_LIBS-from-ld_new_DEPENDENCIES.patch deleted file mode 100644 index d598c73..0000000 --- a/backport-ld-Remove-JANSSON_LIBS-from-ld_new_DEPENDENCIES.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 9e9a27707e9342f2002f7673421d4abbafc883ec Mon Sep 17 00:00:00 2001 -From: "H.J. Lu" -Date: Wed, 19 Jun 2024 14:24:35 -0700 -Subject: [PATCH] ld: Remove JANSSON_LIBS from ld_new_DEPENDENCIES - -Remove JANSSON_LIBS from ld_new_DEPENDENCIES since ld_new_DEPENDENCIES -should only contain binutils dependencies. - - PR ld/31909 - * Makefile.am (ld_new_DEPENDENCIES): Remove JANSSON_LIBS. - * Makefile.in: Regenerated. - -Signed-off-by: H.J. Lu ---- - ld/Makefile.am | 2 +- - ld/Makefile.in | 2 +- - 2 files changed, 2 insertions(+), 2 deletions(-) - -diff --git a/ld/Makefile.am b/ld/Makefile.am -index f9ee05b1400..6a9833e5775 100644 ---- a/ld/Makefile.am -+++ b/ld/Makefile.am -@@ -658,7 +658,7 @@ ld_new_SOURCES = ldgram.y ldlex-wrapper.c lexsup.c ldlang.c mri.c ldctor.c ldmai - ldwrite.c ldexp.c ldemul.c ldver.c ldmisc.c ldfile.c ldcref.c plugin.c \ - ldbuildid.c - ld_new_DEPENDENCIES = $(EMULATION_OFILES) $(EMUL_EXTRA_OFILES) \ -- $(BFDLIB) $(LIBCTF) $(LIBIBERTY) $(LIBINTL_DEP) $(JANSSON_LIBS) -+ $(BFDLIB) $(LIBCTF) $(LIBIBERTY) $(LIBINTL_DEP) - ld_new_LDADD = $(EMULATION_OFILES) $(EMUL_EXTRA_OFILES) $(BFDLIB) $(LIBCTF) \ - $(LIBIBERTY) $(LIBINTL) $(ZLIB) $(ZSTD_LIBS) $(JANSSON_LIBS) - -diff --git a/ld/Makefile.in b/ld/Makefile.in -index 8350f00a521..8639e782cdf 100644 ---- a/ld/Makefile.in -+++ b/ld/Makefile.in -@@ -1036,7 +1036,7 @@ ld_new_SOURCES = ldgram.y ldlex-wrapper.c lexsup.c ldlang.c mri.c ldctor.c ldmai - ldbuildid.c - - ld_new_DEPENDENCIES = $(EMULATION_OFILES) $(EMUL_EXTRA_OFILES) \ -- $(BFDLIB) $(LIBCTF) $(LIBIBERTY) $(LIBINTL_DEP) $(JANSSON_LIBS) -+ $(BFDLIB) $(LIBCTF) $(LIBIBERTY) $(LIBINTL_DEP) - - ld_new_LDADD = $(EMULATION_OFILES) $(EMUL_EXTRA_OFILES) $(BFDLIB) $(LIBCTF) \ - $(LIBIBERTY) $(LIBINTL) $(ZLIB) $(ZSTD_LIBS) $(JANSSON_LIBS) --- -2.33.0 - diff --git a/binutils-BPF-reloc-4.patch b/binutils-BPF-reloc-4.patch deleted file mode 100644 index a664518..0000000 --- a/binutils-BPF-reloc-4.patch +++ /dev/null @@ -1,38 +0,0 @@ -diff -rup binutils.orig/bfd/bpf-reloc.def binutils-2.41/bfd/bpf-reloc.def ---- binutils.orig/bfd/bpf-reloc.def 2023-10-30 10:41:59.114273359 +0000 -+++ binutils-2.41/bfd/bpf-reloc.def 2023-10-30 11:09:41.316109162 +0000 -@@ -72,3 +72,20 @@ - 0xffffffff, /* src_mask */ - 0xffffffff, /* dst_mask */ - true) /* pcrel_offset */ -+ -+ /* R_BPF_64_NODYLD32 is not used by GNU tools - but it is generated by LLVM. -+ We provide an entry here so that tools like strip can safely handle BPF -+ binaries generated by other tools. */ -+ BPF_HOWTO (R_BPF_64_NODYLD32, /* type */ -+ 0, /* rightshift */ -+ 0, /* size */ -+ 0, /* bitsize */ -+ false, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont, /* complain_on_overflow */ -+ bpf_elf_generic_reloc, /* special_function */ -+ "R_BPF_64_NODYLD32", /* name */ -+ false, /* partial_inplace */ -+ 0, /* src_mask */ -+ 0, /* dst_mask */ -+ false) /* pcrel_offset */ -diff -rup binutils.orig/include/elf/bpf.h binutils-2.41/include/elf/bpf.h ---- binutils.orig/include/elf/bpf.h 2023-10-30 10:41:59.332273599 +0000 -+++ binutils-2.41/include/elf/bpf.h 2023-10-30 10:59:44.475368448 +0000 -@@ -30,8 +30,8 @@ START_RELOC_NUMBERS (elf_bpf_reloc_type) - RELOC_NUMBER (R_BPF_64_64, 1) - RELOC_NUMBER (R_BPF_64_ABS64, 2) - RELOC_NUMBER (R_BPF_64_ABS32, 3) --/* R_BPF_64_NODYLD32 is not used by GNU tools. -- * It is kept in this file to remind that the value is already taken. */ -+/* R_BPF_64_NODYLD32 is not used by GNU tools - but it is generated by LLVM. -+ It is kept in this file to remind that the value is already taken. */ - RELOC_NUMBER (R_BPF_64_NODYLD32, 4) - RELOC_NUMBER (R_BPF_64_32, 10) - END_RELOC_NUMBERS (R_BPF_max) diff --git a/binutils-special-sections-in-groups.patch b/binutils-special-sections-in-groups.patch deleted file mode 100644 index 7de5a93..0000000 --- a/binutils-special-sections-in-groups.patch +++ /dev/null @@ -1,27 +0,0 @@ ---- binutils.orig/bfd/elf.c 2018-10-19 11:42:10.107277490 +0100 -+++ binutils-2.31.1/bfd/elf.c 2018-10-19 11:44:33.607105801 +0100 -@@ -830,7 +830,13 @@ setup_group (bfd *abfd, Elf_Internal_Shd - } - } - -- if (elf_group_name (newsect) == NULL) -+ if (elf_group_name (newsect) == NULL -+ /* OS specific sections might be in a group (eg ARM's ARM_EXIDX section) -+ but they will not have been added to the group because they do not -+ have contents that the ELF code in the BFD library knows how to -+ process. This is OK though - we rely upon the target backends to -+ handle these sections for us. */ -+ && hdr->sh_type < SHT_LOOS) - { - /* xgettext:c-format */ - _bfd_error_handler (_("%pB: no group info for section '%pA'"), -@@ -936,7 +942,8 @@ _bfd_elf_setup_sections (bfd *abfd) - else if (idx->shdr->bfd_section) - elf_sec_group (idx->shdr->bfd_section) = shdr->bfd_section; - else if (idx->shdr->sh_type != SHT_RELA -- && idx->shdr->sh_type != SHT_REL) -+ && idx->shdr->sh_type != SHT_REL -+ && idx->shdr->sh_type < SHT_LOOS) - { - /* There are some unknown sections in the group. */ - _bfd_error_handler diff --git a/binutils-2.41.tar.xz b/binutils-with-gold-2.44.tar.xz similarity index 32% rename from binutils-2.41.tar.xz rename to binutils-with-gold-2.44.tar.xz index f74d6d6..59b8744 100644 --- a/binutils-2.41.tar.xz +++ b/binutils-with-gold-2.44.tar.xz @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:ae9a5789e23459e59606e6714723f2d3ffc31c03174191ef0d015bdf06007450 -size 26765692 +oid sha256:67be9198476cc37436e2801de649f4ad80bf0d02430d86aff63c6b59b6e23987 +size 28548400 diff --git a/binutils.spec b/binutils.spec index 1434539..6c7357d 100644 --- a/binutils.spec +++ b/binutils.spec @@ -1,8 +1,8 @@ Summary: A GNU collection of binary utilities Name: binutils%{?_with_debug:-debug} -Version: 2.41 -Release: 19 +Version: 2.44 +Release: 1 License: GPL-3.0-or-later AND (GPL-3.0-or-later WITH Bison-exception-2.2) AND (LGPL-2.0-or-later WITH GCC-exception-2.0) AND BSD-3-Clause AND GFDL-1.3-or-later AND GPL-2.0-or-later AND LGPL-2.1-or-later AND LGPL-2.0-or-later URL: https://sourceware.org/binutils @@ -151,7 +151,7 @@ URL: https://sourceware.org/binutils # too many controversial patches so we stick with the official FSF version # instead. -Source: https://ftp.gnu.org/gnu/binutils/binutils-%{version}.tar.xz +Source: https://ftp.gnu.org/gnu/binutils/binutils-with-gold-%{version}.tar.xz Source2: binutils-2.19.50.0.1-output-format.sed #---------------------------------------------------------------------------- @@ -162,144 +162,8 @@ Source2: binutils-2.19.50.0.1-output-format.sed # Part 1000 - 1999 Patch1001: X86-Change-fpic-to-fPIC-in-PICFLAG.patch -Patch1002: PPC-gas-supported-c2000.patch -Patch1003: Sw64-binutils-Add-Sw64-support.patch # Part 3000 - 4999 -Patch3001: LoongArch-Fix-ld-no-relax-bug.patch -Patch3002: LoongArch-Directly-delete-relaxed-instuctions-in-fir.patch -Patch3003: LoongArch-Multiple-relax_trip-in-one-relax_pass.patch -Patch3004: LoongArch-Remove-elf_seg_map-info-output_bfd-NULL-re.patch -Patch3005: LoongArch-Modify-link_info.relax_pass-from-3-to-2.patch -Patch3006: LoongArch-Add-more-relaxation-testcases.patch -Patch3007: LoongArch-fix-internal-error-when-as-handling-unsupp.patch -Patch3008: as-Add-new-atomic-instructions-in-LoongArch-v1.1.patch -Patch3009: as-Add-new-estimated-reciprocal-instructions-in-Loon.patch -Patch3010: LoongArch-Modify-inconsistent-behavior-of-ld-with-un.patch -Patch3011: backport-ld-Remove-JANSSON_LIBS-from-ld_new_DEPENDENCIES.patch -Patch3012: LoongArch-Fix-immediate-overflow-check-bug.patch -Patch3013: LoongArch-ld-Simplify-inserting-IRELATIVE-relocation.patch -Patch3014: Libvtv-Add-loongarch-support.patch -Patch3015: LoongArch-implement-count_-leading-trailing-_zeros.patch -Patch3016: LoongArch-gas-Fix-make-check-gas-crash.patch -Patch3017: Use-32-64_PCREL-to-replace-a-pair-of-ADD32-64-and-SU.patch -Patch3018: Add-testcase-for-generation-of-32-64_PCREL.patch -Patch3019: Make-sure-DW_CFA_advance_loc4-is-in-the-same-frag.patch -Patch3020: LoongArch-Enable-gas-sort-relocs.patch -Patch3021: Add-support-for-pcaddi-rd-symbol.patch -Patch3022: as-add-option-for-generate-R_LARCH_32-64_PCREL.patch -Patch3023: Add-testsuits-for-new-assembler-option-of-mthin-add-.patch -Patch3024: LoongArch-GAS-Add-support-for-branch-relaxation.patch -Patch3025: LoongArch-readelf-d-RELASZ-excludes-.rela.plt-size.patch -Patch3026: LoongArch-Correct-comments.patch -Patch3027: as-fixed-internal-error-when-immediate-value-of-relo.patch -Patch3028: Add-support-for-ilp32-register-alias.patch -Patch3029: MIPS-GAS-Add-march-loongson2f-to-loongson-2f-3-test.patch -Patch3030: LoongArch-Add-support-for-b-.L1-and-beq-t0-t1-.L1.patch -Patch3031: LoongArch-Add-new-relocation-R_LARCH_CALL36.patch -Patch3032: LoongArch-Add-call36-and-tail36-pseudo-instructions-.patch -Patch3033: LoongArch-Allow-la.got-la.pcrel-relaxation-for-share.patch -Patch3034: LoongArch-Add-support-for-the-third-expression-of-.a.patch -Patch3035: Re-LoongArch-Add-support-for-b-.L1-and-beq-t0-t1-.L1.patch -Patch3036: LoongArch-Add-new-relocs-and-macro-for-TLSDESC.patch -Patch3037: LoongArch-Add-support-for-TLSDESC-in-ld.patch -Patch3038: LoongArch-Add-tls-transition-support.patch -Patch3039: LoongArch-Add-support-for-TLS-LD-GD-DESC-relaxation.patch -Patch3040: LoongArch-Add-testsuit-for-DESC-and-tls-transition-a.patch -Patch3041: asan-buffer-overflow-in-loongarch_elf_rtype_to_howto.patch -Patch3042: LoongArch-bfd-Add-support-for-tls-le-relax.patch -Patch3043: LoongArch-include-Add-support-for-tls-le-relax.patch -Patch3044: LoongArch-opcodes-Add-support-for-tls-le-relax.patch -Patch3045: LoongArch-gas-Add-support-for-tls-le-relax.patch -Patch3046: LoongArch-ld-Add-support-for-tls-le-relax.patch -Patch3047: LoongArch-Commas-inside-double-quotes.patch -Patch3048: LoongArch-Fix-some-macro-that-cannot-be-expanded-pro.patch -Patch3049: LoongArch-Fix-loongarch-elf-target-ld-testsuite-fail.patch -Patch3050: LoongArch-Fix-linker-generate-PLT-entry-for-data-sym.patch -Patch3051: loongarch-index-shadows-global.patch -Patch3052: LoongArch-Discard-extra-spaces-in-objdump-output.patch -Patch3053: LoongArch-ld-Adjusted-some-code-order-in-relax.exp.patch -Patch3054: LoongArch-Fix-relaxation-overflow-caused-by-section-.patch -Patch3055: LoongArch-Adapt-R_LARCH_-PCALA-GOT-TLS_IE-TLS_DESC-6.patch -Patch3056: LoongArch-Do-not-emit-R_LARCH_RELAX-for-two-register.patch -Patch3057: LoongArch-Use-tab-to-indent-assembly-in-TLSDESC-test.patch -Patch3058: LoongArch-Do-not-add-DF_STATIC_TLS-for-TLS-LE.patch -Patch3059: LoongArch-Fix-some-test-failures-about-TLS-desc-and-.patch -Patch3060: PATCH-v2-gas-NEWS-ld-NEWS-Announce-LoongArch-changes.patch -Patch3061: LoongArch-gas-Don-t-define-LoongArch-.align.patch -Patch3062: LoongArch-gas-Start-a-new-frag-after-instructions-th.patch -Patch3063: LoongArch-ld-Add-support-for-TLS-LE-symbol-with-adde.patch -Patch3064: LoongArch-gas-Add-support-for-s9-register.patch -Patch3065: LoongArch-Fix-a-bug-of-getting-relocation-type.patch -Patch3066: LoongArch-gas-Fix-the-types-of-symbols-referred-with.patch -Patch3067: LoongArch-gas-Try-to-avoid-R_LARCH_ALIGN-associate-w.patch -Patch3068: LoongArch-bfd-Correct-the-name-of-R_LARCH_SOP_POP_32.patch -Patch3069: LoongArch-bfd-Fix-some-bugs-of-howto-table.patch -Patch3070: LoongArch-ld-Fix-other-pop-relocs-overflow-check-and.patch -Patch3071: Avoid-unused-space-in-.rela.dyn-if-sec-was-discarded.patch -Patch3072: LoongArch-Run-overflow-testcases-only-on-LoongArch-t.patch -Patch3073: LoongArch-Add-gas-testsuit-for-alias-instructions.patch -Patch3074: LoongArch-Add-gas-testsuit-for-lbt-lvz-instructions.patch -Patch3075: LoongArch-Add-gas-testsuit-for-lsx-lasx-instructions.patch -Patch3076: LoongArch-Add-gas-testsuit-for-LA64-int-float-instru.patch -Patch3077: LoongArch-Add-gas-testsuit-for-LA32-int-float-instru.patch -Patch3078: LoongArch-Add-gas-testsuit-for-LA64-relocations.patch -Patch3079: LoongArch-Add-gas-testsuit-for-LA32-relocations.patch -Patch3080: LoongArch-Delete-extra-instructions-when-TLS-type-tr.patch -Patch3081: LoongArch-Add-dtpoff-calculation-function.patch -Patch3082: LoongArch-Fix-some-test-cases-for-TLS-transition-and.patch -Patch3083: LoongArch-Fix-gas-and-ld-test-cases.patch -Patch3084: LoongArch-Scan-all-illegal-operand-instructions-with.patch -Patch3085: LoongArch-Add-relaxation-for-R_LARCH_CALL36.patch -Patch3086: BFD-Fix-the-bug-of-R_LARCH_AGLIN-caused-by-discard-s.patch -Patch3087: LoongArch-gas-Ignore-.align-if-it-is-at-the-start-of.patch -Patch3088: LoongArch-Fix-the-issue-of-excessive-relocation-gene.patch -Patch3089: LoongArch-ld-Move-.got-.got.plt-before-.data-and-pro.patch -Patch3090: LoongArch-ld-Report-an-error-when-seeing-an-unrecogn.patch -Patch3091: LoongArch-Add-mignore-start-align-option.patch -Patch3092: LoongArch-The-symbol-got-type-can-only-be-obtained-a.patch -Patch3093: LoongArch-Add-bad-static-relocation-check-and-output.patch -Patch3094: LoongArch-gas-Simplify-relocations-in-sections-witho.patch -Patch3095: Fix-building-Loongarch-BFD-with-a-32-bit-compiler.patch -Patch3096: LoongArch-Fix-ld-test-failures-caused-by-using-instr.patch -Patch3097: LoongArch-gas-Adjust-DWARF-CIE-alignment-factors.patch -Patch3098: Re-LoongArch-gas-Adjust-DWARF-CIE-alignment-factors.patch -Patch3099: LoongArch-Fix-relaxation-overflow-caused-by-ld-z-sep.patch -Patch3100: LoongArch-Make-align-symbol-be-in-same-section-with-.patch -Patch3101: LoongArch-Disable-linker-relaxation-if-set-the-addre.patch -Patch3102: LoongArch-add-.option-directive.patch -Patch3103: LoongArch-TLS-IE-needs-only-one-dynamic-reloc.patch -Patch3104: LoongArch-Do-not-check-R_LARCH_SOP_PUSH_ABSOLUTE-to-.patch -Patch3105: LoongArch-Remove-unused-code-in-ld-test-suite.patch -Patch3106: LoongArch-Reject-R_LARCH_32-from-becoming-a-runtime-.patch -Patch3107: LoongArch-Fix-bad-reloc-with-mixed-visibility-ifunc-.patch -Patch3108: LoongArch-Make-protected-function-symbols-local-for-.patch -Patch3109: LoongArch-Add-DT_RELR-support.patch -Patch3110: LoongArch-Add-DT_RELR-tests.patch -Patch3111: LoongArch-Not-alloc-dynamic-relocs-if-symbol-is-abso.patch -Patch3112: LoongArch-Fix-dwarf3-test-cases-from-XPASS-to-PASS.patch -Patch3113: gas-NEWS-ld-NEWS-Announce-LoongArch-changes-in-2.43.patch -Patch3114: LoongArch-Fix-ld-FAIL-test-cases.patch -Patch3115: LoongArch-Add-support-for-OUTPUT_FORMAT-binary.patch -Patch3116: loongarch-ld-testsuite-xpasses.patch -Patch3117: LoongArch-Fix-assertion-failure-with-DT_RELR.patch -Patch3118: LoongArch-Fix-DT_RELR-and-relaxation-interaction.patch -Patch3119: LoongArch-Fix-wrong-relocation-handling-of-symbols-d.patch -Patch3120: LoongArch-LoongArch64-allows-relocations-to-use-64-b.patch -Patch3121: LoongArch-Fixed-ABI-v1.00-TLS-dynamic-relocation-gen.patch -Patch3122: Add-macros-to-get-opcode-of-instructions-approriatel.patch -Patch3123: Not-append-rela-for-absolute-symbol.patch -Patch3124: LoongArch-Add-elfNN_loongarch_mkobject-to-initialize.patch -Patch3125: LoongArch-Fixed-R_LARCH_-32-64-_PCREL-generation-bug.patch -Patch3126: LoongArch-Optimize-the-relaxation-process.patch -Patch3127: LoongArch-Add-more-relaxation-support-for-call36.patch -Patch3128: LoongArch-Force-relocation-for-every-reference-to-th.patch -Patch3129: LoongArch-Fixed-precedence-of-expression-operators-i.patch -Patch3130: Include-ldlex.h-when-compile-eelfxxloongarch.c.patch -Patch3131: Modify-test-because-of-readelf-not-update.patch -Patch3132: remove-file-produced-by-bison.patch -Patch3133: replace-space-with-tab.patch -Patch3134: LoongArch-binutils-compatible-with-older-gcc.patch # Part 5000 - @@ -334,10 +198,6 @@ Patch5003: binutils-no-config-h-check.patch # FIXME: Find related bug. Decide on permanency. Patch5004: binutils-2.27-aarch64-ifunc.patch -# Purpose: Allow OS specific sections in section groups. -# Lifetime: Fixed in 2.42 (maybe) -Patch5005: binutils-special-sections-in-groups.patch - # Purpose: Stop gold from aborting when input sections with the same name # have different flags. # Lifetime: Fixed in 2.42 (maybe) @@ -353,45 +213,19 @@ Patch5007: binutils-update-linker-manual.patch # Lifetime: Fixed in 2.42 (maybe) Patch5008: binutils-gold-empty-dwp.patch -# Purpose: Fix gold linker relocation offset. -# Lifetime: Permanent -Patch5009: Fix-gold-linker-relocation-offset.patch - -# Purpose: Accept and ignore R_BPF_64_NODYLD32 relocations -# Lifetime: Fixed in 2.42 -Patch5010: binutils-BPF-reloc-4.patch - # Purpose: Change the gold configuration script to only warn about # unsupported targets. This allows the binutils to be built with # BPF support enabled. # Lifetime: Permanent. Patch5011: binutils-gold-warn-unsupported.patch -# Purpose: Fix slowdown about partial linking. -# Lifetime: Fixed in 2.44 -Patch5012: Fix-slowdown-about-partial-linking.patch - -# Purpose: nm: Avoid potential segmentation fault when displaying -# symbols without version info. -# Lifetime: Fixed in 2.44 -Patch5013: nm-Avoid-potential-segmentation-fault-when-displaying.patch - -# Purpose: PR32560 stack-buffer-overflow at objdump disassemble_bytes -# Lifetime: Fixed in 2.44 -Patch5014: backport-CVE-2025-0840.patch - # Purpose: PR32716, objdump -i memory leak # Lifetime: fixed in master Patch5015: backport-CVE-2025-3198.patch -# Purpose: PR32399, buffer overflow printing core_file_failing_command -# Lifetime: Fixed in 2.44 -Patch5016: backport-PR32399-buffer-overflow-printing-core_file_failing_c.patch -Patch5017: backport-Re-PR32399-buffer-overflow-printing-core_file_failin.patch - #---------------------------------------------------------------------------- -Patch6001: aarch64-add-l4-instruction.patch +#Patch6001: aarch64-add-l4-instruction.patch Provides: bundled(libiberty) @@ -531,11 +365,7 @@ using libelf instead of BFD. #---------------------------------------------------------------------------- %if %{with docs} -%package help -Summary: Manual and information files - -%description help -This package contains binutils manual and information files. +%package_help %endif #---------------------------------------------------------------------------- @@ -630,7 +460,7 @@ use by developers. It is NOT INTENDED FOR PRODUCTION use. #---------------------------------------------------------------------------- %prep -%autosetup -p1 -n binutils-%{version} +%autosetup -p1 -n binutils-with-gold-%{version} # On ppc64 and aarch64, we might use 64KiB pages sed -i -e '/#define.*ELF_COMMONPAGESIZE/s/0x1000$/0x10000/' bfd/elf*ppc.c @@ -876,7 +706,7 @@ run_target_configuration() else RARGS="--disable-shared" fi - + ../configure --target=$target $CARGS $SARGS $RARGS $TARGS || cat config.log popd @@ -1353,7 +1183,7 @@ exit 0 %{_libdir}/libopcodes.so %if %{with docs} -%files help +#%files help %{_mandir}/man1/* %{_infodir}/as.info.* %{_infodir}/binutils.info.* @@ -1407,6 +1237,9 @@ exit 0 #---------------------------------------------------------------------------- %changelog +* Mon May 12 2025 Funda Wang - 2.44-1 +- update to 2.44 + * Fri Apr 18 2025 eastb233 - 2.41-19 - Fix PR32399, buffer overflow printing core_file_failing_command diff --git a/gas-NEWS-ld-NEWS-Announce-LoongArch-changes-in-2.43.patch b/gas-NEWS-ld-NEWS-Announce-LoongArch-changes-in-2.43.patch deleted file mode 100644 index 37db085..0000000 --- a/gas-NEWS-ld-NEWS-Announce-LoongArch-changes-in-2.43.patch +++ /dev/null @@ -1,126 +0,0 @@ -From 448658bbccadde4f9170174dca842f09bc5651b7 Mon Sep 17 00:00:00 2001 -From: Lulu Cai -Date: Fri, 26 Jul 2024 16:34:38 +0800 -Subject: [PATCH 103/123] gas/NEWS, ld/NEWS: Announce LoongArch changes in 2.43 - ---- - gas/NEWS | 75 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - ld/NEWS | 18 ++++++++++++++ - 2 files changed, 93 insertions(+) - -diff --git a/gas/NEWS b/gas/NEWS -index 9ad24543..3a291e53 100644 ---- a/gas/NEWS -+++ b/gas/NEWS -@@ -1,5 +1,80 @@ - -*- text -*- - -+Changes in 2.43: -+ -+* Add support for LoongArch .option for fine-grained control of assembly -+ code options. -+ -+* The MIPS '--trap' command-line option now causes GAS to dynamically -+ track the ISA setting as code is assembled and to emit either trap or -+ breakpoint instructions according to whether the currently selected ISA -+ permits the use of trap instructions or not. Previously the ISA was -+ only checked at startup and GAS bailed out if the initial ISA was -+ incompatible with the '--trap' option. -+ -+* Support CFCMOV feature in Intel APX. Now, APX_F is fully supportted. -+ -+* Support CCMP and CTEST feature in Intel APX. -+ -+* Support zero-upper feature in Intel APX. -+ -+* Add a .base64 directive to the assembler which allows base64 encoded -+ binary data to be provided as strings. -+ -+* Add support for 'armv9.5-a' for -march in AArch64 GAS. -+ -+* In x86 Intel syntax undue mnemonic suffixes are now warned about. This is -+ a first step towards rejecting their use where unjustified. -+ -+* Assembler macros as well as the bodies of .irp / .irpc / .rept can now use -+ the syntax \+ to access the number of times a given macro has been executed. -+ This is similar to the already existing \@ syntax, except that the count is -+ maintained on a per-macro basis. -+ -+* Support the NF feature in Intel APX. -+ -+* Remove KEYLOCKER and SHA promotions from EVEX MAP4. -+ -+* References to FB and dollar labels, when supported, are no longer permitted -+ in a radix other than 10. (Note that definitions of such labels were already -+ thus restricted, except that leading zeroes were permitted.) -+ -+* Remove support for RISC-V privileged spec 1.9.1, but linker can still -+ recognize it in case of linking old objects. -+ -+* Add support for RISC-V Zacas extension with version 1.0. -+ -+* Add support for RISC-V Zcmp extension with version 1.0. -+ -+* Add support for RISC-V Zfbfmin extension with version 1.0. -+ -+* Add support for RISC-V Zvfbfmin extension with version 1.0. -+ -+* Add support for RISC-V Zvfbfwma extension with version 1.0. -+ -+* Add support for RISC-V Smcsrind/Sscsrind extension with version 1.0. -+ -+* Add support for RISC-V CORE-V extensions (XCvMem, XCvBi, XCvElw) with -+ version 1.0. -+ -+* Add support for RISC-V SiFive cease extension (XSfCease) with version 1.0. -+ -+* The base register operand in D(X,B) and D(L,B) may be explicitly omitted -+ in assembly on s390. It can now be coded as D(X,) or D(L,) instead of D(X,0) -+ D(X,%r0), D(L,0), and D(L,%r0). -+ -+* Warn when a register name type does not match the operand type on s390. -+ Add support for s390-specific option "warn-regtype-mismatch=[strict|relaxed| -+ no]" to override the register name type check behavior. The default -+ is "relaxed", which allows floating-point and vector register names to be -+ used interchangeably. -+ -+* Add support for 'armv9.5-a' for -march in Arm GAS. -+ -+* Add support for the AArch64 Lookup Table Extension (LUT). -+ -+* Add support for the AArch64 Lookup Table Extension v2 (LUTv2). -+ - Changes in 2.42: - - * Experimental support in GAS to synthesize CFI for ABI-conformant, -diff --git a/ld/NEWS b/ld/NEWS -index 687b5190..14e5207c 100644 ---- a/ld/NEWS -+++ b/ld/NEWS -@@ -1,5 +1,23 @@ - -*- text -*- - -+Changes in 2.43: -+ -+* Add support for LoongArch DT_RELR (compressed R_LARCH_RELATIVE). -+ -+* Put .got .got.plt in the relro to make it read-only after relocation. -+ -+* Add -z isa-level-report=[none|all|needed|used] to the x86 ELF linker -+ to report needed and used x86-64 ISA levels. -+ -+* Add --rosegment option which changes the -z separate-code option so that -+ only one read-only segment is created (instead of two). (The option name -+ is misleading, but it matches the name used by LLD and GOLD). -+ -+* Add --section-ordering-file option to add extra mapping of input -+ sections to output sections. -+ -+* Add -plugin-save-temps to store plugin intermediate files permanently. -+ - Changes in 2.42: - - * Add -z mark-plt/-z nomark-plt options to x86-64 ELF linker to mark PLT --- -2.33.0 - diff --git a/loongarch-index-shadows-global.patch b/loongarch-index-shadows-global.patch deleted file mode 100644 index bcc0052..0000000 --- a/loongarch-index-shadows-global.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 8e018f9efeab0a04c045f6fd06d493a00a027dd9 Mon Sep 17 00:00:00 2001 -From: Alan Modra -Date: Wed, 3 Jan 2024 16:03:48 +1030 -Subject: [PATCH 040/123] loongarch: 'index' shadows global - -Avoid an error when compiling with older versions of gcc. - - * elfnn-loongarch.c (loongarch_relax_align): Rename "index" to - "sym_index". ---- - bfd/elfnn-loongarch.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c -index 73e4b819..3d858169 100644 ---- a/bfd/elfnn-loongarch.c -+++ b/bfd/elfnn-loongarch.c -@@ -4302,8 +4302,8 @@ loongarch_relax_align (bfd *abfd, asection *sec, - { - bfd_vma addend, max = 0, alignment = 1; - -- int index = ELFNN_R_SYM (rel->r_info); -- if (index > 0) -+ int sym_index = ELFNN_R_SYM (rel->r_info); -+ if (sym_index > 0) - { - alignment = 1 << (rel->r_addend & 0xff); - max = rel->r_addend >> 8; --- -2.33.0 - diff --git a/loongarch-ld-testsuite-xpasses.patch b/loongarch-ld-testsuite-xpasses.patch deleted file mode 100644 index 7c4952f..0000000 --- a/loongarch-ld-testsuite-xpasses.patch +++ /dev/null @@ -1,112 +0,0 @@ -From 33403fb9c012c0eecf216ca9e9398a4ed8de81df Mon Sep 17 00:00:00 2001 -From: Alan Modra -Date: Wed, 7 Aug 2024 07:56:33 +0930 -Subject: [PATCH 106/123] loongarch ld testsuite xpasses - -Some tests started passing with commit 3a83f0342e54. However, -supporting a changed ld output format is not so simple, and the change -to the loongarch_elf_hash_table macro needs further changes to the -rest of the code. It is true that some uses of -loongarch_elf_hash_table do not need to check the type of the hash -table, but others like loongarch_elf_relax_section do need to check. -bfd_relax_section is called in lang_size_sections using the input bfd, -not the output bfd. If the input bfd may be of different type to the -output, then the hash table type must be checked before accessing -elements of the hash table. This patch corrects -loongarch_elf_relax_section. I haven't checked all the uses of the -hash table throughout the loongarch backend. - -bfd/ - * elfnn-loongarch.c (loongarch_elf_relax_section): Don't relax - unless the hash table is loongarch_elf_link_hash_table. - Move variable declarations. Formatting. -ld/ - * testsuite/ld-elf/pr21884.d: Don't xfail loongarach. - * testsuite/ld-unique/pr21529.d: Likewise. ---- - bfd/elfnn-loongarch.c | 18 ++++++++++-------- - ld/testsuite/ld-elf/pr21884.d | 2 +- - ld/testsuite/ld-unique/pr21529.d | 2 +- - 3 files changed, 12 insertions(+), 10 deletions(-) - -diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c -index c2468443..adf16ddc 100644 ---- a/bfd/elfnn-loongarch.c -+++ b/bfd/elfnn-loongarch.c -@@ -5246,16 +5246,15 @@ loongarch_get_max_alignment (asection *sec) - - static bool - loongarch_elf_relax_section (bfd *abfd, asection *sec, -- struct bfd_link_info *info, -- bool *again) -+ struct bfd_link_info *info, -+ bool *again) - { -- struct loongarch_elf_link_hash_table *htab = loongarch_elf_hash_table (info); -- struct bfd_elf_section_data *data = elf_section_data (sec); -- Elf_Internal_Shdr *symtab_hdr = &elf_symtab_hdr (abfd); -- Elf_Internal_Rela *relocs; - *again = false; -- bfd_vma max_alignment = 0; -+ if (!is_elf_hash_table (info->hash) -+ || elf_hash_table_id (elf_hash_table (info)) != LARCH_ELF_DATA) -+ return true; - -+ struct loongarch_elf_link_hash_table *htab = loongarch_elf_hash_table (info); - if (bfd_link_relocatable (info) - || sec->sec_flg0 - || (sec->flags & SEC_RELOC) == 0 -@@ -5267,6 +5266,8 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, - || *(htab->data_segment_phase) == 4) - return true; - -+ struct bfd_elf_section_data *data = elf_section_data (sec); -+ Elf_Internal_Rela *relocs; - if (data->relocs) - relocs = data->relocs; - else if (!(relocs = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, -@@ -5277,6 +5278,7 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, - && !bfd_malloc_and_get_section (abfd, sec, &data->this_hdr.contents)) - return true; - -+ Elf_Internal_Shdr *symtab_hdr = &elf_symtab_hdr (abfd); - if (symtab_hdr->sh_info != 0 - && !symtab_hdr->contents - && !(symtab_hdr->contents = -@@ -5289,7 +5291,7 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, - - /* Estimate the maximum alignment for all output sections once time - should be enough. */ -- max_alignment = htab->max_alignment; -+ bfd_vma max_alignment = htab->max_alignment; - if (max_alignment == (bfd_vma) -1) - { - max_alignment = loongarch_get_max_alignment (sec); -diff --git a/ld/testsuite/ld-elf/pr21884.d b/ld/testsuite/ld-elf/pr21884.d -index e289b419..3d44ccfe 100644 ---- a/ld/testsuite/ld-elf/pr21884.d -+++ b/ld/testsuite/ld-elf/pr21884.d -@@ -3,7 +3,7 @@ - #ld: -T pr21884.t - #objdump: -b binary -s - #xfail: aarch64*-*-* arm*-*-* avr-*-* ia64-*-* m68hc1*-*-* nds32*-*-* --#xfail: riscv*-*-* score-*-* v850-*-* loongarch*-*-* -+#xfail: riscv*-*-* score-*-* v850-*-* - # Skip targets which can't change output format to binary. - - .*: file format binary -diff --git a/ld/testsuite/ld-unique/pr21529.d b/ld/testsuite/ld-unique/pr21529.d -index 896f8722..fb637943 100644 ---- a/ld/testsuite/ld-unique/pr21529.d -+++ b/ld/testsuite/ld-unique/pr21529.d -@@ -1,6 +1,6 @@ - #ld: --oformat binary -T pr21529.ld -e main - #objdump: -s -b binary --#xfail: aarch64*-*-* arm*-*-* avr-*-* ia64-*-* m68hc1*-*-* nds32*-*-* riscv*-*-* score-*-* v850-*-* loongarch*-*-* -+#xfail: aarch64*-*-* arm*-*-* avr-*-* ia64-*-* m68hc1*-*-* nds32*-*-* riscv*-*-* score-*-* v850-*-* - # Skip targets which can't change output format to binary. - - #pass --- -2.33.0 - diff --git a/nm-Avoid-potential-segmentation-fault-when-displaying.patch b/nm-Avoid-potential-segmentation-fault-when-displaying.patch deleted file mode 100644 index 27136a7..0000000 --- a/nm-Avoid-potential-segmentation-fault-when-displaying.patch +++ /dev/null @@ -1,71 +0,0 @@ -From 5f8987d3999edb26e757115fe87be55787d510b9 Mon Sep 17 00:00:00 2001 -From: Nick Clifton -Date: Tue, 17 Dec 2024 09:18:57 +0000 -Subject: [PATCH] nm: Avoid potential segmentation fault when displaying - symbols without version info. - -PR 32467 ---- - binutils/nm.c | 24 ++++++++++++++++-------- - 1 file changed, 16 insertions(+), 8 deletions(-) - -diff --git a/binutils/nm.c b/binutils/nm.c -index faf27c59b4d..0ba7604d34f 100644 ---- a/binutils/nm.c -+++ b/binutils/nm.c -@@ -682,7 +682,7 @@ print_symname (const char *form, struct extended_symbol_info *info, - const char *name, bfd *abfd) - { - char *alloc = NULL; -- char *atver = NULL; -+ char *atname = NULL; - - if (name == NULL) - name = info->sinfo->name; -@@ -690,9 +690,19 @@ print_symname (const char *form, struct extended_symbol_info *info, - if (!with_symbol_versions - && bfd_get_flavour (abfd) == bfd_target_elf_flavour) - { -- atver = strchr (name, '@'); -+ char *atver = strchr (name, '@'); -+ - if (atver) -- *atver = 0; -+ { -+ /* PR 32467 - Corrupt binaries might include an @ character in a -+ symbol name. Since non-versioned symbol names can be in -+ read-only memory (via memory mapping of a file's contents) we -+ cannot just replace the @ character with a NUL. Instead we -+ create a truncated copy of the name. */ -+ atname = xstrdup (name); -+ atname [atver - name] = 0; -+ name = atname; -+ } - } - - if (do_demangle && *name) -@@ -703,9 +713,7 @@ print_symname (const char *form, struct extended_symbol_info *info, - } - - if (unicode_display != unicode_default) -- { -- name = convert_utf8 (name); -- } -+ name = convert_utf8 (name); - - if (info != NULL && info->elfinfo && with_symbol_versions) - { -@@ -726,8 +734,8 @@ print_symname (const char *form, struct extended_symbol_info *info, - } - } - printf (form, name); -- if (atver) -- *atver = '@'; -+ -+ free (atname); - free (alloc); - } - --- -2.43.5 - diff --git a/remove-file-produced-by-bison.patch b/remove-file-produced-by-bison.patch deleted file mode 100644 index 1eb2d53..0000000 --- a/remove-file-produced-by-bison.patch +++ /dev/null @@ -1,1920 +0,0 @@ -From 68485a414f2edc538ca4f4f292caea86b58acce3 Mon Sep 17 00:00:00 2001 -From: Xin Wang -Date: Wed, 30 Oct 2024 19:47:55 +0800 -Subject: [PATCH 122/123] remove file produced by bison - ---- - gas/config/loongarch-parse.c | 1901 ---------------------------------- - 1 file changed, 1901 deletions(-) - delete mode 100644 gas/config/loongarch-parse.c - -diff --git a/gas/config/loongarch-parse.c b/gas/config/loongarch-parse.c -deleted file mode 100644 -index 2fad9e0b..00000000 ---- a/gas/config/loongarch-parse.c -+++ /dev/null -@@ -1,1901 +0,0 @@ --/* A Bison parser, made by GNU Bison 3.8.2. */ -- --/* Bison implementation for Yacc-like parsers in C -- -- Copyright (C) 1984, 1989-1990, 2000-2015, 2018-2021 Free Software Foundation, -- Inc. -- -- This program is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program. If not, see . */ -- --/* As a special exception, you may create a larger work that contains -- part or all of the Bison parser skeleton and distribute that work -- under terms of your choice, so long as that work isn't itself a -- parser generator using the skeleton or a modified version thereof -- as a parser skeleton. Alternatively, if you modify or redistribute -- the parser skeleton itself, you may (at your option) remove this -- special exception, which will cause the skeleton and the resulting -- Bison output files to be licensed under the GNU General Public -- License without this special exception. -- -- This special exception was added by the Free Software Foundation in -- version 2.2 of Bison. */ -- --/* C LALR(1) parser skeleton written by Richard Stallman, by -- simplifying the original so-called "semantic" parser. */ -- --/* DO NOT RELY ON FEATURES THAT ARE NOT DOCUMENTED in the manual, -- especially those whose name start with YY_ or yy_. They are -- private implementation details that can be changed or removed. */ -- --/* All symbols defined below should begin with yy or YY, to avoid -- infringing on user name space. This should be done even for local -- variables, as they might otherwise be expanded by user macros. -- There are some unavoidable exceptions within include files to -- define necessary library symbols; they are noted "INFRINGES ON -- USER NAME SPACE" below. */ -- --/* Identify Bison output, and Bison version. */ --#define YYBISON 30802 -- --/* Bison version string. */ --#define YYBISON_VERSION "3.8.2" -- --/* Skeleton name. */ --#define YYSKELETON_NAME "yacc.c" -- --/* Pure parsers. */ --#define YYPURE 0 -- --/* Push parsers. */ --#define YYPUSH 0 -- --/* Pull parsers. */ --#define YYPULL 1 -- -- -- -- --/* First part of user prologue. */ --#line 19 "./config/loongarch-parse.y" -- --#include "as.h" --#include "loongarch-lex.h" --#include "loongarch-parse.h" --static void yyerror (const char *s ATTRIBUTE_UNUSED) --{ --}; --int yylex (void); -- -- --static struct reloc_info *top, *end; -- --static expressionS const_0 = --{ -- .X_op = O_constant, -- .X_add_number = 0 --}; -- --static int --is_const (struct reloc_info *info) --{ -- return (info->type == BFD_RELOC_LARCH_SOP_PUSH_ABSOLUTE -- && info->value.X_op == O_constant); --} -- --int --loongarch_parse_expr (const char *expr, -- struct reloc_info *reloc_stack_top, -- size_t max_reloc_num, -- size_t *reloc_num, -- offsetT *imm) --{ -- int ret; -- struct yy_buffer_state *buffstate; -- top = reloc_stack_top; -- end = top + max_reloc_num; -- buffstate = yy_scan_string (expr); -- ret = yyparse (); -- -- if (ret == 0) -- { -- if (is_const (top - 1)) -- *imm = (--top)->value.X_add_number; -- else -- *imm = 0; -- *reloc_num = top - reloc_stack_top; -- } -- yy_delete_buffer (buffstate); -- -- return ret; --} -- --static void --emit_const (offsetT imm) --{ -- if (end <= top) -- as_fatal (_("expr too huge")); -- top->type = BFD_RELOC_LARCH_SOP_PUSH_ABSOLUTE; -- top->value.X_op = O_constant; -- top->value.X_add_number = imm; -- top++; --} -- --static const char * --my_getExpression (expressionS *ep, const char *str) --{ -- char *save_in, *ret; -- -- if (*str == ':') -- { -- unsigned long j; -- char *str_1 = (char *) str; -- j = strtol (str_1, &str_1, 10); -- get_internal_label (ep, j, *str_1 == 'f'); -- return NULL; -- } -- save_in = input_line_pointer; -- input_line_pointer = (char *)str; -- expression (ep); -- ret = input_line_pointer; -- input_line_pointer = save_in; -- return ret; --} -- --static void --emit_const_var (const char *op) --{ -- expressionS ep; -- -- if (end <= top) -- as_fatal (_("expr too huge")); -- -- my_getExpression (&ep, op); -- -- if (ep.X_op != O_constant) -- as_bad ("illegal operand: %s", op); -- -- top->value.X_op = O_constant; -- top->value.X_add_number = ep.X_add_number; -- top->type = BFD_RELOC_LARCH_SOP_PUSH_ABSOLUTE; -- top++; --} -- --static void --reloc (const char *op_c_str, const char *id_c_str, offsetT addend) --{ -- expressionS id_sym_expr; -- bfd_reloc_code_real_type btype; -- -- if (end <= top) -- as_fatal (_("expr too huge")); -- -- /* For compatible old asm code. */ -- if (0 == strcmp (op_c_str, "plt")) -- btype = BFD_RELOC_LARCH_B26; -- else -- btype = loongarch_larch_reloc_name_lookup (NULL, op_c_str); -- -- if (id_c_str) -- { -- my_getExpression (&id_sym_expr, id_c_str); -- id_sym_expr.X_add_number += addend; -- } -- else -- { -- id_sym_expr.X_op = O_constant; -- id_sym_expr.X_add_number = addend; -- } -- -- top->value = id_sym_expr; -- top->type = btype; -- top++; --} -- --static void --emit_unary (char op) --{ -- struct reloc_info *s_top = top - 1; -- if (is_const (s_top)) -- { -- offsetT opr = s_top->value.X_add_number; -- switch (op) -- { -- case '+': -- break; -- case '-': -- opr = -opr; -- break; -- case '~': -- opr = ~opr; -- break; -- case '!': -- opr = !opr; -- break; -- default: -- abort (); -- } -- s_top->value.X_add_number = opr; -- } -- else -- { -- if (end <= top) -- as_fatal (_("expr too huge")); -- switch (op) -- { -- case '!': -- top->type = BFD_RELOC_LARCH_SOP_NOT; -- break; -- default: -- abort (); -- } -- top->value = const_0; -- top++; -- } --} -- --static void --emit_bin (int op) --{ -- struct reloc_info *last_1st = top - 1, *last_2nd = top - 2; -- if (is_const (last_1st) && is_const (last_2nd)) -- { -- offsetT opr1 = last_2nd->value.X_add_number; -- offsetT opr2 = last_1st->value.X_add_number; -- switch (op) -- { -- case '*': -- opr1 = opr1 * opr2; -- break; -- case '/': -- opr1 = opr1 / opr2; -- break; -- case '%': -- opr1 = opr1 % opr2; -- break; -- case '+': -- opr1 = opr1 + opr2; -- break; -- case '-': -- opr1 = opr1 - opr2; -- break; -- case LEFT_OP: -- opr1 = opr1 << opr2; -- break; -- case RIGHT_OP: -- /* Algorithm right shift. */ -- opr1 = (offsetT)opr1 >> (offsetT)opr2; -- break; -- case '<': -- opr1 = opr1 < opr2; -- break; -- case '>': -- opr1 = opr1 > opr2; -- break; -- case LE_OP: -- opr1 = opr1 <= opr2; -- break; -- case GE_OP: -- opr1 = opr1 >= opr2; -- break; -- case EQ_OP: -- opr1 = opr1 == opr2; -- break; -- case NE_OP: -- opr1 = opr1 != opr2; -- break; -- case '&': -- opr1 = opr1 & opr2; -- break; -- case '^': -- opr1 = opr1 ^ opr2; -- break; -- case '|': -- opr1 = opr1 | opr2; -- break; -- case AND_OP: -- opr1 = opr1 && opr2; -- break; -- case OR_OP: -- opr1 = opr1 || opr2; -- break; -- default: -- abort (); -- } -- last_2nd->value.X_add_number = opr1; -- last_1st->type = 0; -- top--; -- } -- else -- { -- if (end <= top) -- as_fatal (_("expr too huge")); -- switch (op) -- { -- case '+': -- top->type = BFD_RELOC_LARCH_SOP_ADD; -- break; -- case '-': -- top->type = BFD_RELOC_LARCH_SOP_SUB; -- break; -- case LEFT_OP: -- top->type = BFD_RELOC_LARCH_SOP_SL; -- break; -- case RIGHT_OP: -- top->type = BFD_RELOC_LARCH_SOP_SR; -- break; -- case '&': -- top->type = BFD_RELOC_LARCH_SOP_AND; -- break; -- default: -- abort (); -- } -- top->value = const_0; -- top++; -- } --} -- --static void --emit_if_else (void) --{ -- struct reloc_info *last_1st = top - 1; -- struct reloc_info *last_2nd = top - 2; -- struct reloc_info *last_3rd = top - 3; -- if (is_const (last_1st) && is_const (last_2nd) && is_const (last_3rd)) -- { -- offsetT opr1 = last_3rd->value.X_add_number; -- offsetT opr2 = last_2nd->value.X_add_number; -- offsetT opr3 = last_1st->value.X_add_number; -- opr1 = opr1 ? opr2 : opr3; -- last_3rd->value.X_add_number = opr1; -- last_2nd->type = 0; -- last_1st->type = 0; -- top -= 2; -- } -- else -- { -- if (end <= top) -- as_fatal (_("expr too huge")); -- top->type = BFD_RELOC_LARCH_SOP_IF_ELSE; -- top->value = const_0; -- top++; -- } --} -- -- --#line 377 "config/loongarch-parse.c" -- --# ifndef YY_CAST --# ifdef __cplusplus --# define YY_CAST(Type, Val) static_cast (Val) --# define YY_REINTERPRET_CAST(Type, Val) reinterpret_cast (Val) --# else --# define YY_CAST(Type, Val) ((Type) (Val)) --# define YY_REINTERPRET_CAST(Type, Val) ((Type) (Val)) --# endif --# endif --# ifndef YY_NULLPTR --# if defined __cplusplus --# if 201103L <= __cplusplus --# define YY_NULLPTR nullptr --# else --# define YY_NULLPTR 0 --# endif --# else --# define YY_NULLPTR ((void*)0) --# endif --# endif -- --/* Use api.header.include to #include this header -- instead of duplicating it here. */ --#ifndef YY_YY_CONFIG_LOONGARCH_PARSE_H_INCLUDED --# define YY_YY_CONFIG_LOONGARCH_PARSE_H_INCLUDED --/* Debug traces. */ --#ifndef YYDEBUG --# define YYDEBUG 0 --#endif --#if YYDEBUG --extern int yydebug; --#endif -- --/* Token kinds. */ --#ifndef YYTOKENTYPE --# define YYTOKENTYPE -- enum yytokentype -- { -- YYEMPTY = -2, -- YYEOF = 0, /* "end of file" */ -- YYerror = 256, /* error */ -- YYUNDEF = 257, /* "invalid token" */ -- INTEGER = 258, /* INTEGER */ -- IDENTIFIER = 259, /* IDENTIFIER */ -- LEFT_OP = 260, /* LEFT_OP */ -- RIGHT_OP = 261, /* RIGHT_OP */ -- LE_OP = 262, /* LE_OP */ -- GE_OP = 263, /* GE_OP */ -- EQ_OP = 264, /* EQ_OP */ -- NE_OP = 265, /* NE_OP */ -- AND_OP = 266, /* AND_OP */ -- OR_OP = 267 /* OR_OP */ -- }; -- typedef enum yytokentype yytoken_kind_t; --#endif --/* Token kinds. */ --#define YYEMPTY -2 --#define YYEOF 0 --#define YYerror 256 --#define YYUNDEF 257 --#define INTEGER 258 --#define IDENTIFIER 259 --#define LEFT_OP 260 --#define RIGHT_OP 261 --#define LE_OP 262 --#define GE_OP 263 --#define EQ_OP 264 --#define NE_OP 265 --#define AND_OP 266 --#define OR_OP 267 -- --/* Value type. */ --#if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED --union YYSTYPE --{ --#line 325 "./config/loongarch-parse.y" -- --char *c_str; --offsetT imm; -- --#line 459 "config/loongarch-parse.c" -- --}; --typedef union YYSTYPE YYSTYPE; --# define YYSTYPE_IS_TRIVIAL 1 --# define YYSTYPE_IS_DECLARED 1 --#endif -- -- --extern YYSTYPE yylval; -- -- --int yyparse (void); -- -- --#endif /* !YY_YY_CONFIG_LOONGARCH_PARSE_H_INCLUDED */ --/* Symbol kind. */ --enum yysymbol_kind_t --{ -- YYSYMBOL_YYEMPTY = -2, -- YYSYMBOL_YYEOF = 0, /* "end of file" */ -- YYSYMBOL_YYerror = 1, /* error */ -- YYSYMBOL_YYUNDEF = 2, /* "invalid token" */ -- YYSYMBOL_INTEGER = 3, /* INTEGER */ -- YYSYMBOL_IDENTIFIER = 4, /* IDENTIFIER */ -- YYSYMBOL_LEFT_OP = 5, /* LEFT_OP */ -- YYSYMBOL_RIGHT_OP = 6, /* RIGHT_OP */ -- YYSYMBOL_LE_OP = 7, /* LE_OP */ -- YYSYMBOL_GE_OP = 8, /* GE_OP */ -- YYSYMBOL_EQ_OP = 9, /* EQ_OP */ -- YYSYMBOL_NE_OP = 10, /* NE_OP */ -- YYSYMBOL_AND_OP = 11, /* AND_OP */ -- YYSYMBOL_OR_OP = 12, /* OR_OP */ -- YYSYMBOL_13_ = 13, /* '(' */ -- YYSYMBOL_14_ = 14, /* ')' */ -- YYSYMBOL_15_ = 15, /* '%' */ -- YYSYMBOL_16_ = 16, /* '-' */ -- YYSYMBOL_17_ = 17, /* '+' */ -- YYSYMBOL_18_ = 18, /* '~' */ -- YYSYMBOL_19_ = 19, /* '!' */ -- YYSYMBOL_20_ = 20, /* '*' */ -- YYSYMBOL_21_ = 21, /* '/' */ -- YYSYMBOL_22_ = 22, /* '<' */ -- YYSYMBOL_23_ = 23, /* '>' */ -- YYSYMBOL_24_ = 24, /* '&' */ -- YYSYMBOL_25_ = 25, /* '^' */ -- YYSYMBOL_26_ = 26, /* '|' */ -- YYSYMBOL_27_ = 27, /* '?' */ -- YYSYMBOL_28_ = 28, /* ':' */ -- YYSYMBOL_YYACCEPT = 29, /* $accept */ -- YYSYMBOL_primary_expression = 30, /* primary_expression */ -- YYSYMBOL_addend = 31, /* addend */ -- YYSYMBOL_unary_expression = 32, /* unary_expression */ -- YYSYMBOL_multiplicative_expression = 33, /* multiplicative_expression */ -- YYSYMBOL_additive_expression = 34, /* additive_expression */ -- YYSYMBOL_shift_expression = 35, /* shift_expression */ -- YYSYMBOL_relational_expression = 36, /* relational_expression */ -- YYSYMBOL_equality_expression = 37, /* equality_expression */ -- YYSYMBOL_and_expression = 38, /* and_expression */ -- YYSYMBOL_exclusive_or_expression = 39, /* exclusive_or_expression */ -- YYSYMBOL_inclusive_or_expression = 40, /* inclusive_or_expression */ -- YYSYMBOL_logical_and_expression = 41, /* logical_and_expression */ -- YYSYMBOL_logical_or_expression = 42, /* logical_or_expression */ -- YYSYMBOL_conditional_expression = 43, /* conditional_expression */ -- YYSYMBOL_expression = 44 /* expression */ --}; --typedef enum yysymbol_kind_t yysymbol_kind_t; -- -- -- -- --#ifdef short --# undef short --#endif -- --/* On compilers that do not define __PTRDIFF_MAX__ etc., make sure -- and (if available) are included -- so that the code can choose integer types of a good width. */ -- --#ifndef __PTRDIFF_MAX__ --# include /* INFRINGES ON USER NAME SPACE */ --# if defined __STDC_VERSION__ && 199901 <= __STDC_VERSION__ --# include /* INFRINGES ON USER NAME SPACE */ --# define YY_STDINT_H --# endif --#endif -- --/* Narrow types that promote to a signed type and that can represent a -- signed or unsigned integer of at least N bits. In tables they can -- save space and decrease cache pressure. Promoting to a signed type -- helps avoid bugs in integer arithmetic. */ -- --#ifdef __INT_LEAST8_MAX__ --typedef __INT_LEAST8_TYPE__ yytype_int8; --#elif defined YY_STDINT_H --typedef int_least8_t yytype_int8; --#else --typedef signed char yytype_int8; --#endif -- --#ifdef __INT_LEAST16_MAX__ --typedef __INT_LEAST16_TYPE__ yytype_int16; --#elif defined YY_STDINT_H --typedef int_least16_t yytype_int16; --#else --typedef short yytype_int16; --#endif -- --/* Work around bug in HP-UX 11.23, which defines these macros -- incorrectly for preprocessor constants. This workaround can likely -- be removed in 2023, as HPE has promised support for HP-UX 11.23 -- (aka HP-UX 11i v2) only through the end of 2022; see Table 2 of -- . */ --#ifdef __hpux --# undef UINT_LEAST8_MAX --# undef UINT_LEAST16_MAX --# define UINT_LEAST8_MAX 255 --# define UINT_LEAST16_MAX 65535 --#endif -- --#if defined __UINT_LEAST8_MAX__ && __UINT_LEAST8_MAX__ <= __INT_MAX__ --typedef __UINT_LEAST8_TYPE__ yytype_uint8; --#elif (!defined __UINT_LEAST8_MAX__ && defined YY_STDINT_H \ -- && UINT_LEAST8_MAX <= INT_MAX) --typedef uint_least8_t yytype_uint8; --#elif !defined __UINT_LEAST8_MAX__ && UCHAR_MAX <= INT_MAX --typedef unsigned char yytype_uint8; --#else --typedef short yytype_uint8; --#endif -- --#if defined __UINT_LEAST16_MAX__ && __UINT_LEAST16_MAX__ <= __INT_MAX__ --typedef __UINT_LEAST16_TYPE__ yytype_uint16; --#elif (!defined __UINT_LEAST16_MAX__ && defined YY_STDINT_H \ -- && UINT_LEAST16_MAX <= INT_MAX) --typedef uint_least16_t yytype_uint16; --#elif !defined __UINT_LEAST16_MAX__ && USHRT_MAX <= INT_MAX --typedef unsigned short yytype_uint16; --#else --typedef int yytype_uint16; --#endif -- --#ifndef YYPTRDIFF_T --# if defined __PTRDIFF_TYPE__ && defined __PTRDIFF_MAX__ --# define YYPTRDIFF_T __PTRDIFF_TYPE__ --# define YYPTRDIFF_MAXIMUM __PTRDIFF_MAX__ --# elif defined PTRDIFF_MAX --# ifndef ptrdiff_t --# include /* INFRINGES ON USER NAME SPACE */ --# endif --# define YYPTRDIFF_T ptrdiff_t --# define YYPTRDIFF_MAXIMUM PTRDIFF_MAX --# else --# define YYPTRDIFF_T long --# define YYPTRDIFF_MAXIMUM LONG_MAX --# endif --#endif -- --#ifndef YYSIZE_T --# ifdef __SIZE_TYPE__ --# define YYSIZE_T __SIZE_TYPE__ --# elif defined size_t --# define YYSIZE_T size_t --# elif defined __STDC_VERSION__ && 199901 <= __STDC_VERSION__ --# include /* INFRINGES ON USER NAME SPACE */ --# define YYSIZE_T size_t --# else --# define YYSIZE_T unsigned --# endif --#endif -- --#define YYSIZE_MAXIMUM \ -- YY_CAST (YYPTRDIFF_T, \ -- (YYPTRDIFF_MAXIMUM < YY_CAST (YYSIZE_T, -1) \ -- ? YYPTRDIFF_MAXIMUM \ -- : YY_CAST (YYSIZE_T, -1))) -- --#define YYSIZEOF(X) YY_CAST (YYPTRDIFF_T, sizeof (X)) -- -- --/* Stored state numbers (used for stacks). */ --typedef yytype_int8 yy_state_t; -- --/* State numbers in computations. */ --typedef int yy_state_fast_t; -- --#ifndef YY_ --# if defined YYENABLE_NLS && YYENABLE_NLS --# if ENABLE_NLS --# include /* INFRINGES ON USER NAME SPACE */ --# define YY_(Msgid) dgettext ("bison-runtime", Msgid) --# endif --# endif --# ifndef YY_ --# define YY_(Msgid) Msgid --# endif --#endif -- -- --#ifndef YY_ATTRIBUTE_PURE --# if defined __GNUC__ && 2 < __GNUC__ + (96 <= __GNUC_MINOR__) --# define YY_ATTRIBUTE_PURE __attribute__ ((__pure__)) --# else --# define YY_ATTRIBUTE_PURE --# endif --#endif -- --#ifndef YY_ATTRIBUTE_UNUSED --# if defined __GNUC__ && 2 < __GNUC__ + (7 <= __GNUC_MINOR__) --# define YY_ATTRIBUTE_UNUSED __attribute__ ((__unused__)) --# else --# define YY_ATTRIBUTE_UNUSED --# endif --#endif -- --/* Suppress unused-variable warnings by "using" E. */ --#if ! defined lint || defined __GNUC__ --# define YY_USE(E) ((void) (E)) --#else --# define YY_USE(E) /* empty */ --#endif -- --/* Suppress an incorrect diagnostic about yylval being uninitialized. */ --#if defined __GNUC__ && ! defined __ICC && 406 <= __GNUC__ * 100 + __GNUC_MINOR__ --# if __GNUC__ * 100 + __GNUC_MINOR__ < 407 --# define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN \ -- _Pragma ("GCC diagnostic push") \ -- _Pragma ("GCC diagnostic ignored \"-Wuninitialized\"") --# else --# define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN \ -- _Pragma ("GCC diagnostic push") \ -- _Pragma ("GCC diagnostic ignored \"-Wuninitialized\"") \ -- _Pragma ("GCC diagnostic ignored \"-Wmaybe-uninitialized\"") --# endif --# define YY_IGNORE_MAYBE_UNINITIALIZED_END \ -- _Pragma ("GCC diagnostic pop") --#else --# define YY_INITIAL_VALUE(Value) Value --#endif --#ifndef YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN --# define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN --# define YY_IGNORE_MAYBE_UNINITIALIZED_END --#endif --#ifndef YY_INITIAL_VALUE --# define YY_INITIAL_VALUE(Value) /* Nothing. */ --#endif -- --#if defined __cplusplus && defined __GNUC__ && ! defined __ICC && 6 <= __GNUC__ --# define YY_IGNORE_USELESS_CAST_BEGIN \ -- _Pragma ("GCC diagnostic push") \ -- _Pragma ("GCC diagnostic ignored \"-Wuseless-cast\"") --# define YY_IGNORE_USELESS_CAST_END \ -- _Pragma ("GCC diagnostic pop") --#endif --#ifndef YY_IGNORE_USELESS_CAST_BEGIN --# define YY_IGNORE_USELESS_CAST_BEGIN --# define YY_IGNORE_USELESS_CAST_END --#endif -- -- --#define YY_ASSERT(E) ((void) (0 && (E))) -- --#if !defined yyoverflow -- --/* The parser invokes alloca or malloc; define the necessary symbols. */ -- --# ifdef YYSTACK_USE_ALLOCA --# if YYSTACK_USE_ALLOCA --# ifdef __GNUC__ --# define YYSTACK_ALLOC __builtin_alloca --# elif defined __BUILTIN_VA_ARG_INCR --# include /* INFRINGES ON USER NAME SPACE */ --# elif defined _AIX --# define YYSTACK_ALLOC __alloca --# elif defined _MSC_VER --# include /* INFRINGES ON USER NAME SPACE */ --# define alloca _alloca --# else --# define YYSTACK_ALLOC alloca --# if ! defined _ALLOCA_H && ! defined EXIT_SUCCESS --# include /* INFRINGES ON USER NAME SPACE */ -- /* Use EXIT_SUCCESS as a witness for stdlib.h. */ --# ifndef EXIT_SUCCESS --# define EXIT_SUCCESS 0 --# endif --# endif --# endif --# endif --# endif -- --# ifdef YYSTACK_ALLOC -- /* Pacify GCC's 'empty if-body' warning. */ --# define YYSTACK_FREE(Ptr) do { /* empty */; } while (0) --# ifndef YYSTACK_ALLOC_MAXIMUM -- /* The OS might guarantee only one guard page at the bottom of the stack, -- and a page size can be as small as 4096 bytes. So we cannot safely -- invoke alloca (N) if N exceeds 4096. Use a slightly smaller number -- to allow for a few compiler-allocated temporary stack slots. */ --# define YYSTACK_ALLOC_MAXIMUM 4032 /* reasonable circa 2006 */ --# endif --# else --# define YYSTACK_ALLOC YYMALLOC --# define YYSTACK_FREE YYFREE --# ifndef YYSTACK_ALLOC_MAXIMUM --# define YYSTACK_ALLOC_MAXIMUM YYSIZE_MAXIMUM --# endif --# if (defined __cplusplus && ! defined EXIT_SUCCESS \ -- && ! ((defined YYMALLOC || defined malloc) \ -- && (defined YYFREE || defined free))) --# include /* INFRINGES ON USER NAME SPACE */ --# ifndef EXIT_SUCCESS --# define EXIT_SUCCESS 0 --# endif --# endif --# ifndef YYMALLOC --# define YYMALLOC malloc --# if ! defined malloc && ! defined EXIT_SUCCESS --void *malloc (YYSIZE_T); /* INFRINGES ON USER NAME SPACE */ --# endif --# endif --# ifndef YYFREE --# define YYFREE free --# if ! defined free && ! defined EXIT_SUCCESS --void free (void *); /* INFRINGES ON USER NAME SPACE */ --# endif --# endif --# endif --#endif /* !defined yyoverflow */ -- --#if (! defined yyoverflow \ -- && (! defined __cplusplus \ -- || (defined YYSTYPE_IS_TRIVIAL && YYSTYPE_IS_TRIVIAL))) -- --/* A type that is properly aligned for any stack member. */ --union yyalloc --{ -- yy_state_t yyss_alloc; -- YYSTYPE yyvs_alloc; --}; -- --/* The size of the maximum gap between one aligned stack and the next. */ --# define YYSTACK_GAP_MAXIMUM (YYSIZEOF (union yyalloc) - 1) -- --/* The size of an array large to enough to hold all stacks, each with -- N elements. */ --# define YYSTACK_BYTES(N) \ -- ((N) * (YYSIZEOF (yy_state_t) + YYSIZEOF (YYSTYPE)) \ -- + YYSTACK_GAP_MAXIMUM) -- --# define YYCOPY_NEEDED 1 -- --/* Relocate STACK from its old location to the new one. The -- local variables YYSIZE and YYSTACKSIZE give the old and new number of -- elements in the stack, and YYPTR gives the new location of the -- stack. Advance YYPTR to a properly aligned location for the next -- stack. */ --# define YYSTACK_RELOCATE(Stack_alloc, Stack) \ -- do \ -- { \ -- YYPTRDIFF_T yynewbytes; \ -- YYCOPY (&yyptr->Stack_alloc, Stack, yysize); \ -- Stack = &yyptr->Stack_alloc; \ -- yynewbytes = yystacksize * YYSIZEOF (*Stack) + YYSTACK_GAP_MAXIMUM; \ -- yyptr += yynewbytes / YYSIZEOF (*yyptr); \ -- } \ -- while (0) -- --#endif -- --#if defined YYCOPY_NEEDED && YYCOPY_NEEDED --/* Copy COUNT objects from SRC to DST. The source and destination do -- not overlap. */ --# ifndef YYCOPY --# if defined __GNUC__ && 1 < __GNUC__ --# define YYCOPY(Dst, Src, Count) \ -- __builtin_memcpy (Dst, Src, YY_CAST (YYSIZE_T, (Count)) * sizeof (*(Src))) --# else --# define YYCOPY(Dst, Src, Count) \ -- do \ -- { \ -- YYPTRDIFF_T yyi; \ -- for (yyi = 0; yyi < (Count); yyi++) \ -- (Dst)[yyi] = (Src)[yyi]; \ -- } \ -- while (0) --# endif --# endif --#endif /* !YYCOPY_NEEDED */ -- --/* YYFINAL -- State number of the termination state. */ --#define YYFINAL 48 --/* YYLAST -- Last index in YYTABLE. */ --#define YYLAST 74 -- --/* YYNTOKENS -- Number of terminals. */ --#define YYNTOKENS 29 --/* YYNNTS -- Number of nonterminals. */ --#define YYNNTS 16 --/* YYNRULES -- Number of rules. */ --#define YYNRULES 45 --/* YYNSTATES -- Number of states. */ --#define YYNSTATES 82 -- --/* YYMAXUTOK -- Last valid token kind. */ --#define YYMAXUTOK 267 -- -- --/* YYTRANSLATE(TOKEN-NUM) -- Symbol number corresponding to TOKEN-NUM -- as returned by yylex, with out-of-bounds checking. */ --#define YYTRANSLATE(YYX) \ -- (0 <= (YYX) && (YYX) <= YYMAXUTOK \ -- ? YY_CAST (yysymbol_kind_t, yytranslate[YYX]) \ -- : YYSYMBOL_YYUNDEF) -- --/* YYTRANSLATE[TOKEN-NUM] -- Symbol number corresponding to TOKEN-NUM -- as returned by yylex. */ --static const yytype_int8 yytranslate[] = --{ -- 0, 2, 2, 2, 2, 2, 2, 2, 2, 2, -- 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, -- 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, -- 2, 2, 2, 19, 2, 2, 2, 15, 24, 2, -- 13, 14, 20, 17, 2, 16, 2, 21, 2, 2, -- 2, 2, 2, 2, 2, 2, 2, 2, 28, 2, -- 22, 2, 23, 27, 2, 2, 2, 2, 2, 2, -- 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, -- 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, -- 2, 2, 2, 2, 25, 2, 2, 2, 2, 2, -- 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, -- 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, -- 2, 2, 2, 2, 26, 2, 18, 2, 2, 2, -- 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, -- 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, -- 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, -- 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, -- 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, -- 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, -- 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, -- 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, -- 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, -- 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, -- 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, -- 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, -- 2, 2, 2, 2, 2, 2, 1, 2, 3, 4, -- 5, 6, 7, 8, 9, 10, 11, 12 --}; -- --#if YYDEBUG --/* YYRLINE[YYN] -- Source line where rule number YYN was defined. */ --static const yytype_int16 yyrline[] = --{ -- 0, 339, 339, 340, 341, 342, 343, 347, 348, 349, -- 353, 354, 355, 356, 357, 361, 362, 363, 364, 368, -- 369, 370, 374, 375, 376, 380, 381, 382, 383, 384, -- 388, 389, 390, 394, 395, 399, 400, 404, 405, 409, -- 410, 414, 415, 419, 420, 424 --}; --#endif -- --/** Accessing symbol of state STATE. */ --#define YY_ACCESSING_SYMBOL(State) YY_CAST (yysymbol_kind_t, yystos[State]) -- --#if YYDEBUG || 0 --/* The user-facing name of the symbol whose (internal) number is -- YYSYMBOL. No bounds checking. */ --static const char *yysymbol_name (yysymbol_kind_t yysymbol) YY_ATTRIBUTE_UNUSED; -- --/* YYTNAME[SYMBOL-NUM] -- String name of the symbol SYMBOL-NUM. -- First, the terminals, then, starting at YYNTOKENS, nonterminals. */ --static const char *const yytname[] = --{ -- "\"end of file\"", "error", "\"invalid token\"", "INTEGER", -- "IDENTIFIER", "LEFT_OP", "RIGHT_OP", "LE_OP", "GE_OP", "EQ_OP", "NE_OP", -- "AND_OP", "OR_OP", "'('", "')'", "'%'", "'-'", "'+'", "'~'", "'!'", -- "'*'", "'/'", "'<'", "'>'", "'&'", "'^'", "'|'", "'?'", "':'", "$accept", -- "primary_expression", "addend", "unary_expression", -- "multiplicative_expression", "additive_expression", "shift_expression", -- "relational_expression", "equality_expression", "and_expression", -- "exclusive_or_expression", "inclusive_or_expression", -- "logical_and_expression", "logical_or_expression", -- "conditional_expression", "expression", YY_NULLPTR --}; -- --static const char * --yysymbol_name (yysymbol_kind_t yysymbol) --{ -- return yytname[yysymbol]; --} --#endif -- --#define YYPACT_NINF (-28) -- --#define yypact_value_is_default(Yyn) \ -- ((Yyn) == YYPACT_NINF) -- --#define YYTABLE_NINF (-1) -- --#define yytable_value_is_error(Yyn) \ -- 0 -- --/* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing -- STATE-NUM. */ --static const yytype_int8 yypact[] = --{ -- 2, -28, -28, 2, 10, 2, 2, 2, 2, -28, -- -28, 9, 23, 36, 0, 37, -8, 7, 26, 25, -- 1, -28, 43, 31, 44, -28, -28, -28, -28, 2, -- 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, -- 2, 2, 2, 2, 2, 2, 2, 2, -28, -28, -- 45, -28, -28, -28, 9, 9, 23, 23, 36, 36, -- 36, 36, 0, 0, 37, -8, 7, 26, 25, 30, -- -28, -28, 2, 17, 21, -28, -28, 56, 57, -28, -- -28, -28 --}; -- --/* YYDEFACT[STATE-NUM] -- Default reduction number in state STATE-NUM. -- Performed when YYTABLE does not specify something else to do. Zero -- means the default is an error. */ --static const yytype_int8 yydefact[] = --{ -- 0, 2, 3, 0, 0, 0, 0, 0, 0, 10, -- 15, 19, 22, 25, 30, 33, 35, 37, 39, 41, -- 43, 45, 0, 0, 0, 12, 11, 13, 14, 0, -- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -- 0, 0, 0, 0, 0, 0, 0, 0, 1, 4, -- 0, 18, 16, 17, 21, 20, 23, 24, 28, 29, -- 26, 27, 31, 32, 34, 36, 38, 40, 42, 0, -- 9, 9, 0, 0, 0, 44, 6, 0, 0, 5, -- 7, 8 --}; -- --/* YYPGOTO[NTERM-NUM]. */ --static const yytype_int8 yypgoto[] = --{ -- -28, -28, -10, -4, 18, 19, -27, 15, 20, 22, -- 24, 27, 28, -28, -9, -3 --}; -- --/* YYDEFGOTO[NTERM-NUM]. */ --static const yytype_int8 yydefgoto[] = --{ -- 0, 9, 73, 10, 11, 12, 13, 14, 15, 16, -- 17, 18, 19, 20, 21, 22 --}; -- --/* YYTABLE[YYPACT[STATE-NUM]] -- What to do in state STATE-NUM. If -- positive, shift that token. If negative, reduce the rule whose -- number is the opposite. If YYTABLE_NINF, syntax error. */ --static const yytype_int8 yytable[] = --{ -- 23, 25, 26, 27, 28, 1, 2, 36, 37, 58, -- 59, 60, 61, 46, 24, 3, 42, 4, 5, 6, -- 7, 8, 38, 39, 29, 51, 52, 53, 47, 30, -- 31, 76, 43, 77, 78, 79, 45, 77, 78, 32, -- 33, 34, 35, 48, 69, 49, 40, 41, 70, 71, -- 54, 55, 44, 56, 57, 62, 63, 50, 72, 80, -- 81, 74, 64, 75, 0, 65, 0, 0, 66, 0, -- 0, 0, 67, 0, 68 --}; -- --static const yytype_int8 yycheck[] = --{ -- 3, 5, 6, 7, 8, 3, 4, 7, 8, 36, -- 37, 38, 39, 12, 4, 13, 24, 15, 16, 17, -- 18, 19, 22, 23, 15, 29, 30, 31, 27, 20, -- 21, 14, 25, 16, 17, 14, 11, 16, 17, 16, -- 17, 5, 6, 0, 47, 14, 9, 10, 3, 4, -- 32, 33, 26, 34, 35, 40, 41, 13, 28, 3, -- 3, 71, 42, 72, -1, 43, -1, -1, 44, -1, -- -1, -1, 45, -1, 46 --}; -- --/* YYSTOS[STATE-NUM] -- The symbol kind of the accessing symbol of -- state STATE-NUM. */ --static const yytype_int8 yystos[] = --{ -- 0, 3, 4, 13, 15, 16, 17, 18, 19, 30, -- 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, -- 42, 43, 44, 44, 4, 32, 32, 32, 32, 15, -- 20, 21, 16, 17, 5, 6, 7, 8, 22, 23, -- 9, 10, 24, 25, 26, 11, 12, 27, 0, 14, -- 13, 32, 32, 32, 33, 33, 34, 34, 35, 35, -- 35, 35, 36, 36, 37, 38, 39, 40, 41, 44, -- 3, 4, 28, 31, 31, 43, 14, 16, 17, 14, -- 3, 3 --}; -- --/* YYR1[RULE-NUM] -- Symbol kind of the left-hand side of rule RULE-NUM. */ --static const yytype_int8 yyr1[] = --{ -- 0, 29, 30, 30, 30, 30, 30, 31, 31, 31, -- 32, 32, 32, 32, 32, 33, 33, 33, 33, 34, -- 34, 34, 35, 35, 35, 36, 36, 36, 36, 36, -- 37, 37, 37, 38, 38, 39, 39, 40, 40, 41, -- 41, 42, 42, 43, 43, 44 --}; -- --/* YYR2[RULE-NUM] -- Number of symbols on the right-hand side of rule RULE-NUM. */ --static const yytype_int8 yyr2[] = --{ -- 0, 2, 1, 1, 3, 6, 6, 3, 3, 0, -- 1, 2, 2, 2, 2, 1, 3, 3, 3, 1, -- 3, 3, 1, 3, 3, 1, 3, 3, 3, 3, -- 1, 3, 3, 1, 3, 1, 3, 1, 3, 1, -- 3, 1, 3, 1, 5, 1 --}; -- -- --enum { YYENOMEM = -2 }; -- --#define yyerrok (yyerrstatus = 0) --#define yyclearin (yychar = YYEMPTY) -- --#define YYACCEPT goto yyacceptlab --#define YYABORT goto yyabortlab --#define YYERROR goto yyerrorlab --#define YYNOMEM goto yyexhaustedlab -- -- --#define YYRECOVERING() (!!yyerrstatus) -- --#define YYBACKUP(Token, Value) \ -- do \ -- if (yychar == YYEMPTY) \ -- { \ -- yychar = (Token); \ -- yylval = (Value); \ -- YYPOPSTACK (yylen); \ -- yystate = *yyssp; \ -- goto yybackup; \ -- } \ -- else \ -- { \ -- yyerror (YY_("syntax error: cannot back up")); \ -- YYERROR; \ -- } \ -- while (0) -- --/* Backward compatibility with an undocumented macro. -- Use YYerror or YYUNDEF. */ --#define YYERRCODE YYUNDEF -- -- --/* Enable debugging if requested. */ --#if YYDEBUG -- --# ifndef YYFPRINTF --# include /* INFRINGES ON USER NAME SPACE */ --# define YYFPRINTF fprintf --# endif -- --# define YYDPRINTF(Args) \ --do { \ -- if (yydebug) \ -- YYFPRINTF Args; \ --} while (0) -- -- -- -- --# define YY_SYMBOL_PRINT(Title, Kind, Value, Location) \ --do { \ -- if (yydebug) \ -- { \ -- YYFPRINTF (stderr, "%s ", Title); \ -- yy_symbol_print (stderr, \ -- Kind, Value); \ -- YYFPRINTF (stderr, "\n"); \ -- } \ --} while (0) -- -- --/*-----------------------------------. --| Print this symbol's value on YYO. | --`-----------------------------------*/ -- --static void --yy_symbol_value_print (FILE *yyo, -- yysymbol_kind_t yykind, YYSTYPE const * const yyvaluep) --{ -- FILE *yyoutput = yyo; -- YY_USE (yyoutput); -- if (!yyvaluep) -- return; -- YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN -- YY_USE (yykind); -- YY_IGNORE_MAYBE_UNINITIALIZED_END --} -- -- --/*---------------------------. --| Print this symbol on YYO. | --`---------------------------*/ -- --static void --yy_symbol_print (FILE *yyo, -- yysymbol_kind_t yykind, YYSTYPE const * const yyvaluep) --{ -- YYFPRINTF (yyo, "%s %s (", -- yykind < YYNTOKENS ? "token" : "nterm", yysymbol_name (yykind)); -- -- yy_symbol_value_print (yyo, yykind, yyvaluep); -- YYFPRINTF (yyo, ")"); --} -- --/*------------------------------------------------------------------. --| yy_stack_print -- Print the state stack from its BOTTOM up to its | --| TOP (included). | --`------------------------------------------------------------------*/ -- --static void --yy_stack_print (yy_state_t *yybottom, yy_state_t *yytop) --{ -- YYFPRINTF (stderr, "Stack now"); -- for (; yybottom <= yytop; yybottom++) -- { -- int yybot = *yybottom; -- YYFPRINTF (stderr, " %d", yybot); -- } -- YYFPRINTF (stderr, "\n"); --} -- --# define YY_STACK_PRINT(Bottom, Top) \ --do { \ -- if (yydebug) \ -- yy_stack_print ((Bottom), (Top)); \ --} while (0) -- -- --/*------------------------------------------------. --| Report that the YYRULE is going to be reduced. | --`------------------------------------------------*/ -- --static void --yy_reduce_print (yy_state_t *yyssp, YYSTYPE *yyvsp, -- int yyrule) --{ -- int yylno = yyrline[yyrule]; -- int yynrhs = yyr2[yyrule]; -- int yyi; -- YYFPRINTF (stderr, "Reducing stack by rule %d (line %d):\n", -- yyrule - 1, yylno); -- /* The symbols being reduced. */ -- for (yyi = 0; yyi < yynrhs; yyi++) -- { -- YYFPRINTF (stderr, " $%d = ", yyi + 1); -- yy_symbol_print (stderr, -- YY_ACCESSING_SYMBOL (+yyssp[yyi + 1 - yynrhs]), -- &yyvsp[(yyi + 1) - (yynrhs)]); -- YYFPRINTF (stderr, "\n"); -- } --} -- --# define YY_REDUCE_PRINT(Rule) \ --do { \ -- if (yydebug) \ -- yy_reduce_print (yyssp, yyvsp, Rule); \ --} while (0) -- --/* Nonzero means print parse trace. It is left uninitialized so that -- multiple parsers can coexist. */ --int yydebug; --#else /* !YYDEBUG */ --# define YYDPRINTF(Args) ((void) 0) --# define YY_SYMBOL_PRINT(Title, Kind, Value, Location) --# define YY_STACK_PRINT(Bottom, Top) --# define YY_REDUCE_PRINT(Rule) --#endif /* !YYDEBUG */ -- -- --/* YYINITDEPTH -- initial size of the parser's stacks. */ --#ifndef YYINITDEPTH --# define YYINITDEPTH 200 --#endif -- --/* YYMAXDEPTH -- maximum size the stacks can grow to (effective only -- if the built-in stack extension method is used). -- -- Do not make this value too large; the results are undefined if -- YYSTACK_ALLOC_MAXIMUM < YYSTACK_BYTES (YYMAXDEPTH) -- evaluated with infinite-precision integer arithmetic. */ -- --#ifndef YYMAXDEPTH --# define YYMAXDEPTH 10000 --#endif -- -- -- -- -- -- --/*-----------------------------------------------. --| Release the memory associated to this symbol. | --`-----------------------------------------------*/ -- --static void --yydestruct (const char *yymsg, -- yysymbol_kind_t yykind, YYSTYPE *yyvaluep) --{ -- YY_USE (yyvaluep); -- if (!yymsg) -- yymsg = "Deleting"; -- YY_SYMBOL_PRINT (yymsg, yykind, yyvaluep, yylocationp); -- -- YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN -- YY_USE (yykind); -- YY_IGNORE_MAYBE_UNINITIALIZED_END --} -- -- --/* Lookahead token kind. */ --int yychar; -- --/* The semantic value of the lookahead symbol. */ --YYSTYPE yylval; --/* Number of syntax errors so far. */ --int yynerrs; -- -- -- -- --/*----------. --| yyparse. | --`----------*/ -- --int --yyparse (void) --{ -- yy_state_fast_t yystate = 0; -- /* Number of tokens to shift before error messages enabled. */ -- int yyerrstatus = 0; -- -- /* Refer to the stacks through separate pointers, to allow yyoverflow -- to reallocate them elsewhere. */ -- -- /* Their size. */ -- YYPTRDIFF_T yystacksize = YYINITDEPTH; -- -- /* The state stack: array, bottom, top. */ -- yy_state_t yyssa[YYINITDEPTH]; -- yy_state_t *yyss = yyssa; -- yy_state_t *yyssp = yyss; -- -- /* The semantic value stack: array, bottom, top. */ -- YYSTYPE yyvsa[YYINITDEPTH]; -- YYSTYPE *yyvs = yyvsa; -- YYSTYPE *yyvsp = yyvs; -- -- int yyn; -- /* The return value of yyparse. */ -- int yyresult; -- /* Lookahead symbol kind. */ -- yysymbol_kind_t yytoken = YYSYMBOL_YYEMPTY; -- /* The variables used to return semantic value and location from the -- action routines. */ -- YYSTYPE yyval; -- -- -- --#define YYPOPSTACK(N) (yyvsp -= (N), yyssp -= (N)) -- -- /* The number of symbols on the RHS of the reduced rule. -- Keep to zero when no symbol should be popped. */ -- int yylen = 0; -- -- YYDPRINTF ((stderr, "Starting parse\n")); -- -- yychar = YYEMPTY; /* Cause a token to be read. */ -- -- goto yysetstate; -- -- --/*------------------------------------------------------------. --| yynewstate -- push a new state, which is found in yystate. | --`------------------------------------------------------------*/ --yynewstate: -- /* In all cases, when you get here, the value and location stacks -- have just been pushed. So pushing a state here evens the stacks. */ -- yyssp++; -- -- --/*--------------------------------------------------------------------. --| yysetstate -- set current state (the top of the stack) to yystate. | --`--------------------------------------------------------------------*/ --yysetstate: -- YYDPRINTF ((stderr, "Entering state %d\n", yystate)); -- YY_ASSERT (0 <= yystate && yystate < YYNSTATES); -- YY_IGNORE_USELESS_CAST_BEGIN -- *yyssp = YY_CAST (yy_state_t, yystate); -- YY_IGNORE_USELESS_CAST_END -- YY_STACK_PRINT (yyss, yyssp); -- -- if (yyss + yystacksize - 1 <= yyssp) --#if !defined yyoverflow && !defined YYSTACK_RELOCATE -- YYNOMEM; --#else -- { -- /* Get the current used size of the three stacks, in elements. */ -- YYPTRDIFF_T yysize = yyssp - yyss + 1; -- --# if defined yyoverflow -- { -- /* Give user a chance to reallocate the stack. Use copies of -- these so that the &'s don't force the real ones into -- memory. */ -- yy_state_t *yyss1 = yyss; -- YYSTYPE *yyvs1 = yyvs; -- -- /* Each stack pointer address is followed by the size of the -- data in use in that stack, in bytes. This used to be a -- conditional around just the two extra args, but that might -- be undefined if yyoverflow is a macro. */ -- yyoverflow (YY_("memory exhausted"), -- &yyss1, yysize * YYSIZEOF (*yyssp), -- &yyvs1, yysize * YYSIZEOF (*yyvsp), -- &yystacksize); -- yyss = yyss1; -- yyvs = yyvs1; -- } --# else /* defined YYSTACK_RELOCATE */ -- /* Extend the stack our own way. */ -- if (YYMAXDEPTH <= yystacksize) -- YYNOMEM; -- yystacksize *= 2; -- if (YYMAXDEPTH < yystacksize) -- yystacksize = YYMAXDEPTH; -- -- { -- yy_state_t *yyss1 = yyss; -- union yyalloc *yyptr = -- YY_CAST (union yyalloc *, -- YYSTACK_ALLOC (YY_CAST (YYSIZE_T, YYSTACK_BYTES (yystacksize)))); -- if (! yyptr) -- YYNOMEM; -- YYSTACK_RELOCATE (yyss_alloc, yyss); -- YYSTACK_RELOCATE (yyvs_alloc, yyvs); --# undef YYSTACK_RELOCATE -- if (yyss1 != yyssa) -- YYSTACK_FREE (yyss1); -- } --# endif -- -- yyssp = yyss + yysize - 1; -- yyvsp = yyvs + yysize - 1; -- -- YY_IGNORE_USELESS_CAST_BEGIN -- YYDPRINTF ((stderr, "Stack size increased to %ld\n", -- YY_CAST (long, yystacksize))); -- YY_IGNORE_USELESS_CAST_END -- -- if (yyss + yystacksize - 1 <= yyssp) -- YYABORT; -- } --#endif /* !defined yyoverflow && !defined YYSTACK_RELOCATE */ -- -- -- if (yystate == YYFINAL) -- YYACCEPT; -- -- goto yybackup; -- -- --/*-----------. --| yybackup. | --`-----------*/ --yybackup: -- /* Do appropriate processing given the current state. Read a -- lookahead token if we need one and don't already have one. */ -- -- /* First try to decide what to do without reference to lookahead token. */ -- yyn = yypact[yystate]; -- if (yypact_value_is_default (yyn)) -- goto yydefault; -- -- /* Not known => get a lookahead token if don't already have one. */ -- -- /* YYCHAR is either empty, or end-of-input, or a valid lookahead. */ -- if (yychar == YYEMPTY) -- { -- YYDPRINTF ((stderr, "Reading a token\n")); -- yychar = yylex (); -- } -- -- if (yychar <= YYEOF) -- { -- yychar = YYEOF; -- yytoken = YYSYMBOL_YYEOF; -- YYDPRINTF ((stderr, "Now at end of input.\n")); -- } -- else if (yychar == YYerror) -- { -- /* The scanner already issued an error message, process directly -- to error recovery. But do not keep the error token as -- lookahead, it is too special and may lead us to an endless -- loop in error recovery. */ -- yychar = YYUNDEF; -- yytoken = YYSYMBOL_YYerror; -- goto yyerrlab1; -- } -- else -- { -- yytoken = YYTRANSLATE (yychar); -- YY_SYMBOL_PRINT ("Next token is", yytoken, &yylval, &yylloc); -- } -- -- /* If the proper action on seeing token YYTOKEN is to reduce or to -- detect an error, take that action. */ -- yyn += yytoken; -- if (yyn < 0 || YYLAST < yyn || yycheck[yyn] != yytoken) -- goto yydefault; -- yyn = yytable[yyn]; -- if (yyn <= 0) -- { -- if (yytable_value_is_error (yyn)) -- goto yyerrlab; -- yyn = -yyn; -- goto yyreduce; -- } -- -- /* Count tokens shifted since error; after three, turn off error -- status. */ -- if (yyerrstatus) -- yyerrstatus--; -- -- /* Shift the lookahead token. */ -- YY_SYMBOL_PRINT ("Shifting", yytoken, &yylval, &yylloc); -- yystate = yyn; -- YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN -- *++yyvsp = yylval; -- YY_IGNORE_MAYBE_UNINITIALIZED_END -- -- /* Discard the shifted token. */ -- yychar = YYEMPTY; -- goto yynewstate; -- -- --/*-----------------------------------------------------------. --| yydefault -- do the default action for the current state. | --`-----------------------------------------------------------*/ --yydefault: -- yyn = yydefact[yystate]; -- if (yyn == 0) -- goto yyerrlab; -- goto yyreduce; -- -- --/*-----------------------------. --| yyreduce -- do a reduction. | --`-----------------------------*/ --yyreduce: -- /* yyn is the number of a rule to reduce with. */ -- yylen = yyr2[yyn]; -- -- /* If YYLEN is nonzero, implement the default value of the action: -- '$$ = $1'. -- -- Otherwise, the following line sets YYVAL to garbage. -- This behavior is undocumented and Bison -- users should not rely upon it. Assigning to YYVAL -- unconditionally makes the parser a bit smaller, and it avoids a -- GCC warning that YYVAL may be used uninitialized. */ -- yyval = yyvsp[1-yylen]; -- -- -- YY_REDUCE_PRINT (yyn); -- switch (yyn) -- { -- case 2: /* primary_expression: INTEGER */ --#line 339 "./config/loongarch-parse.y" -- {emit_const ((yyvsp[0].imm));} --#line 1529 "config/loongarch-parse.c" -- break; -- -- case 3: /* primary_expression: IDENTIFIER */ --#line 340 "./config/loongarch-parse.y" -- {emit_const_var ((yyvsp[0].c_str));} --#line 1535 "config/loongarch-parse.c" -- break; -- -- case 5: /* primary_expression: '%' IDENTIFIER '(' IDENTIFIER addend ')' */ --#line 342 "./config/loongarch-parse.y" -- {reloc ((yyvsp[-4].c_str), (yyvsp[-2].c_str), (yyvsp[-1].imm)); free ((yyvsp[-4].c_str)); free ((yyvsp[-2].c_str));} --#line 1541 "config/loongarch-parse.c" -- break; -- -- case 6: /* primary_expression: '%' IDENTIFIER '(' INTEGER addend ')' */ --#line 343 "./config/loongarch-parse.y" -- {reloc ((yyvsp[-4].c_str), NULL, (yyvsp[-2].imm) + (yyvsp[-1].imm)); free ((yyvsp[-4].c_str));} --#line 1547 "config/loongarch-parse.c" -- break; -- -- case 7: /* addend: addend '-' INTEGER */ --#line 347 "./config/loongarch-parse.y" -- {(yyval.imm) -= (yyvsp[0].imm);} --#line 1553 "config/loongarch-parse.c" -- break; -- -- case 8: /* addend: addend '+' INTEGER */ --#line 348 "./config/loongarch-parse.y" -- {(yyval.imm) += (yyvsp[0].imm);} --#line 1559 "config/loongarch-parse.c" -- break; -- -- case 9: /* addend: %empty */ --#line 349 "./config/loongarch-parse.y" -- {(yyval.imm) = 0;} --#line 1565 "config/loongarch-parse.c" -- break; -- -- case 11: /* unary_expression: '+' unary_expression */ --#line 354 "./config/loongarch-parse.y" -- {emit_unary ('+');} --#line 1571 "config/loongarch-parse.c" -- break; -- -- case 12: /* unary_expression: '-' unary_expression */ --#line 355 "./config/loongarch-parse.y" -- {emit_unary ('-');} --#line 1577 "config/loongarch-parse.c" -- break; -- -- case 13: /* unary_expression: '~' unary_expression */ --#line 356 "./config/loongarch-parse.y" -- {emit_unary ('~');} --#line 1583 "config/loongarch-parse.c" -- break; -- -- case 14: /* unary_expression: '!' unary_expression */ --#line 357 "./config/loongarch-parse.y" -- {emit_unary ('!');} --#line 1589 "config/loongarch-parse.c" -- break; -- -- case 16: /* multiplicative_expression: multiplicative_expression '*' unary_expression */ --#line 362 "./config/loongarch-parse.y" -- {emit_bin ('*');} --#line 1595 "config/loongarch-parse.c" -- break; -- -- case 17: /* multiplicative_expression: multiplicative_expression '/' unary_expression */ --#line 363 "./config/loongarch-parse.y" -- {emit_bin ('/');} --#line 1601 "config/loongarch-parse.c" -- break; -- -- case 18: /* multiplicative_expression: multiplicative_expression '%' unary_expression */ --#line 364 "./config/loongarch-parse.y" -- {emit_bin ('%');} --#line 1607 "config/loongarch-parse.c" -- break; -- -- case 20: /* additive_expression: additive_expression '+' multiplicative_expression */ --#line 369 "./config/loongarch-parse.y" -- {emit_bin ('+');} --#line 1613 "config/loongarch-parse.c" -- break; -- -- case 21: /* additive_expression: additive_expression '-' multiplicative_expression */ --#line 370 "./config/loongarch-parse.y" -- {emit_bin ('-');} --#line 1619 "config/loongarch-parse.c" -- break; -- -- case 23: /* shift_expression: shift_expression LEFT_OP additive_expression */ --#line 375 "./config/loongarch-parse.y" -- {emit_bin (LEFT_OP);} --#line 1625 "config/loongarch-parse.c" -- break; -- -- case 24: /* shift_expression: shift_expression RIGHT_OP additive_expression */ --#line 376 "./config/loongarch-parse.y" -- {emit_bin (RIGHT_OP);} --#line 1631 "config/loongarch-parse.c" -- break; -- -- case 26: /* relational_expression: relational_expression '<' shift_expression */ --#line 381 "./config/loongarch-parse.y" -- {emit_bin ('<');} --#line 1637 "config/loongarch-parse.c" -- break; -- -- case 27: /* relational_expression: relational_expression '>' shift_expression */ --#line 382 "./config/loongarch-parse.y" -- {emit_bin ('>');} --#line 1643 "config/loongarch-parse.c" -- break; -- -- case 28: /* relational_expression: relational_expression LE_OP shift_expression */ --#line 383 "./config/loongarch-parse.y" -- {emit_bin (LE_OP);} --#line 1649 "config/loongarch-parse.c" -- break; -- -- case 29: /* relational_expression: relational_expression GE_OP shift_expression */ --#line 384 "./config/loongarch-parse.y" -- {emit_bin (GE_OP);} --#line 1655 "config/loongarch-parse.c" -- break; -- -- case 31: /* equality_expression: equality_expression EQ_OP relational_expression */ --#line 389 "./config/loongarch-parse.y" -- {emit_bin (EQ_OP);} --#line 1661 "config/loongarch-parse.c" -- break; -- -- case 32: /* equality_expression: equality_expression NE_OP relational_expression */ --#line 390 "./config/loongarch-parse.y" -- {emit_bin (NE_OP);} --#line 1667 "config/loongarch-parse.c" -- break; -- -- case 34: /* and_expression: and_expression '&' equality_expression */ --#line 395 "./config/loongarch-parse.y" -- {emit_bin ('&');} --#line 1673 "config/loongarch-parse.c" -- break; -- -- case 36: /* exclusive_or_expression: exclusive_or_expression '^' and_expression */ --#line 400 "./config/loongarch-parse.y" -- {emit_bin ('^');} --#line 1679 "config/loongarch-parse.c" -- break; -- -- case 38: /* inclusive_or_expression: inclusive_or_expression '|' exclusive_or_expression */ --#line 405 "./config/loongarch-parse.y" -- {emit_bin ('|');} --#line 1685 "config/loongarch-parse.c" -- break; -- -- case 40: /* logical_and_expression: logical_and_expression AND_OP inclusive_or_expression */ --#line 410 "./config/loongarch-parse.y" -- {emit_bin (AND_OP);} --#line 1691 "config/loongarch-parse.c" -- break; -- -- case 42: /* logical_or_expression: logical_or_expression OR_OP logical_and_expression */ --#line 415 "./config/loongarch-parse.y" -- {emit_bin (OR_OP);} --#line 1697 "config/loongarch-parse.c" -- break; -- -- case 44: /* conditional_expression: logical_or_expression '?' expression ':' conditional_expression */ --#line 420 "./config/loongarch-parse.y" -- {emit_if_else ();} --#line 1703 "config/loongarch-parse.c" -- break; -- -- --#line 1707 "config/loongarch-parse.c" -- -- default: break; -- } -- /* User semantic actions sometimes alter yychar, and that requires -- that yytoken be updated with the new translation. We take the -- approach of translating immediately before every use of yytoken. -- One alternative is translating here after every semantic action, -- but that translation would be missed if the semantic action invokes -- YYABORT, YYACCEPT, or YYERROR immediately after altering yychar or -- if it invokes YYBACKUP. In the case of YYABORT or YYACCEPT, an -- incorrect destructor might then be invoked immediately. In the -- case of YYERROR or YYBACKUP, subsequent parser actions might lead -- to an incorrect destructor call or verbose syntax error message -- before the lookahead is translated. */ -- YY_SYMBOL_PRINT ("-> $$ =", YY_CAST (yysymbol_kind_t, yyr1[yyn]), &yyval, &yyloc); -- -- YYPOPSTACK (yylen); -- yylen = 0; -- -- *++yyvsp = yyval; -- -- /* Now 'shift' the result of the reduction. Determine what state -- that goes to, based on the state we popped back to and the rule -- number reduced by. */ -- { -- const int yylhs = yyr1[yyn] - YYNTOKENS; -- const int yyi = yypgoto[yylhs] + *yyssp; -- yystate = (0 <= yyi && yyi <= YYLAST && yycheck[yyi] == *yyssp -- ? yytable[yyi] -- : yydefgoto[yylhs]); -- } -- -- goto yynewstate; -- -- --/*--------------------------------------. --| yyerrlab -- here on detecting error. | --`--------------------------------------*/ --yyerrlab: -- /* Make sure we have latest lookahead translation. See comments at -- user semantic actions for why this is necessary. */ -- yytoken = yychar == YYEMPTY ? YYSYMBOL_YYEMPTY : YYTRANSLATE (yychar); -- /* If not already recovering from an error, report this error. */ -- if (!yyerrstatus) -- { -- ++yynerrs; -- yyerror (YY_("syntax error")); -- } -- -- if (yyerrstatus == 3) -- { -- /* If just tried and failed to reuse lookahead token after an -- error, discard it. */ -- -- if (yychar <= YYEOF) -- { -- /* Return failure if at end of input. */ -- if (yychar == YYEOF) -- YYABORT; -- } -- else -- { -- yydestruct ("Error: discarding", -- yytoken, &yylval); -- yychar = YYEMPTY; -- } -- } -- -- /* Else will try to reuse lookahead token after shifting the error -- token. */ -- goto yyerrlab1; -- -- --/*---------------------------------------------------. --| yyerrorlab -- error raised explicitly by YYERROR. | --`---------------------------------------------------*/ --yyerrorlab: -- /* Pacify compilers when the user code never invokes YYERROR and the -- label yyerrorlab therefore never appears in user code. */ -- if (0) -- YYERROR; -- ++yynerrs; -- -- /* Do not reclaim the symbols of the rule whose action triggered -- this YYERROR. */ -- YYPOPSTACK (yylen); -- yylen = 0; -- YY_STACK_PRINT (yyss, yyssp); -- yystate = *yyssp; -- goto yyerrlab1; -- -- --/*-------------------------------------------------------------. --| yyerrlab1 -- common code for both syntax error and YYERROR. | --`-------------------------------------------------------------*/ --yyerrlab1: -- yyerrstatus = 3; /* Each real token shifted decrements this. */ -- -- /* Pop stack until we find a state that shifts the error token. */ -- for (;;) -- { -- yyn = yypact[yystate]; -- if (!yypact_value_is_default (yyn)) -- { -- yyn += YYSYMBOL_YYerror; -- if (0 <= yyn && yyn <= YYLAST && yycheck[yyn] == YYSYMBOL_YYerror) -- { -- yyn = yytable[yyn]; -- if (0 < yyn) -- break; -- } -- } -- -- /* Pop the current state because it cannot handle the error token. */ -- if (yyssp == yyss) -- YYABORT; -- -- -- yydestruct ("Error: popping", -- YY_ACCESSING_SYMBOL (yystate), yyvsp); -- YYPOPSTACK (1); -- yystate = *yyssp; -- YY_STACK_PRINT (yyss, yyssp); -- } -- -- YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN -- *++yyvsp = yylval; -- YY_IGNORE_MAYBE_UNINITIALIZED_END -- -- -- /* Shift the error token. */ -- YY_SYMBOL_PRINT ("Shifting", YY_ACCESSING_SYMBOL (yyn), yyvsp, yylsp); -- -- yystate = yyn; -- goto yynewstate; -- -- --/*-------------------------------------. --| yyacceptlab -- YYACCEPT comes here. | --`-------------------------------------*/ --yyacceptlab: -- yyresult = 0; -- goto yyreturnlab; -- -- --/*-----------------------------------. --| yyabortlab -- YYABORT comes here. | --`-----------------------------------*/ --yyabortlab: -- yyresult = 1; -- goto yyreturnlab; -- -- --/*-----------------------------------------------------------. --| yyexhaustedlab -- YYNOMEM (memory exhaustion) comes here. | --`-----------------------------------------------------------*/ --yyexhaustedlab: -- yyerror (YY_("memory exhausted")); -- yyresult = 2; -- goto yyreturnlab; -- -- --/*----------------------------------------------------------. --| yyreturnlab -- parsing is finished, clean up and return. | --`----------------------------------------------------------*/ --yyreturnlab: -- if (yychar != YYEMPTY) -- { -- /* Make sure we have latest lookahead translation. See comments at -- user semantic actions for why this is necessary. */ -- yytoken = YYTRANSLATE (yychar); -- yydestruct ("Cleanup: discarding lookahead", -- yytoken, &yylval); -- } -- /* Do not reclaim the symbols of the rule whose action triggered -- this YYABORT or YYACCEPT. */ -- YYPOPSTACK (yylen); -- YY_STACK_PRINT (yyss, yyssp); -- while (yyssp != yyss) -- { -- yydestruct ("Cleanup: popping", -- YY_ACCESSING_SYMBOL (+*yyssp), yyvsp); -- YYPOPSTACK (1); -- } --#ifndef yyoverflow -- if (yyss != yyssa) -- YYSTACK_FREE (yyss); --#endif -- -- return yyresult; --} -- --#line 426 "./config/loongarch-parse.y" -- -- --- -2.33.0 - diff --git a/replace-space-with-tab.patch b/replace-space-with-tab.patch deleted file mode 100644 index fdcc092..0000000 --- a/replace-space-with-tab.patch +++ /dev/null @@ -1,500 +0,0 @@ -From c4e6b6be66500cb31f7d123377a90fed17dd992a Mon Sep 17 00:00:00 2001 -From: Xin Wang -Date: Wed, 30 Oct 2024 19:48:09 +0800 -Subject: [PATCH 123/123] replace space with tab - ---- - bfd/elfnn-loongarch.c | 322 +++++++++++++++++++++--------------------- - 1 file changed, 161 insertions(+), 161 deletions(-) - -diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c -index 8b9628f7..13216ef9 100644 ---- a/bfd/elfnn-loongarch.c -+++ b/bfd/elfnn-loongarch.c -@@ -159,7 +159,7 @@ loongarch_elf_new_section_hook (bfd *abfd, asection *sec) - - sdata = bfd_zalloc (abfd, amt); - if (!sdata) -- return false; -+ return false; - sec->used_by_bfd = sdata; - } - -@@ -993,17 +993,17 @@ loongarch_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, - r_type = loongarch_tls_transition (abfd, info, h, r_symndx, r_type); - - /* I don't want to spend time supporting DT_RELR with old object -- files doing stack-based relocs. */ -+ files doing stack-based relocs. */ - if (info->enable_dt_relr -- && r_type >= R_LARCH_SOP_PUSH_PCREL -- && r_type <= R_LARCH_SOP_POP_32_U) -- { -- /* xgettext:c-format */ -- _bfd_error_handler (_("%pB: stack based reloc type (%u) is not " -- "supported with -z pack-relative-relocs"), -- abfd, r_type); -- return false; -- } -+ && r_type >= R_LARCH_SOP_PUSH_PCREL -+ && r_type <= R_LARCH_SOP_POP_32_U) -+ { -+ /* xgettext:c-format */ -+ _bfd_error_handler (_("%pB: stack based reloc type (%u) is not " -+ "supported with -z pack-relative-relocs"), -+ abfd, r_type); -+ return false; -+ } - - switch (r_type) - { -@@ -1218,19 +1218,19 @@ loongarch_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, - return false; - break; - -- case R_LARCH_ALIGN: -- /* Check against irrational R_LARCH_ALIGN relocs which may cause -- removing an odd number of bytes and disrupt DT_RELR. */ -- if (rel->r_offset % 4 != 0) -- { -- /* xgettext:c-format */ -- _bfd_error_handler ( -- _("%pB: R_LARCH_ALIGN with offset %" PRId64 " not aligned " -- "to instruction boundary"), -- abfd, (uint64_t) rel->r_offset); -- return false; -- } -- break; -+ case R_LARCH_ALIGN: -+ /* Check against irrational R_LARCH_ALIGN relocs which may cause -+ removing an odd number of bytes and disrupt DT_RELR. */ -+ if (rel->r_offset % 4 != 0) -+ { -+ /* xgettext:c-format */ -+ _bfd_error_handler ( -+ _("%pB: R_LARCH_ALIGN with offset %" PRId64 " not aligned " -+ "to instruction boundary"), -+ abfd, (uint64_t) rel->r_offset); -+ return false; -+ } -+ break; - - default: - break; -@@ -1948,7 +1948,7 @@ maybe_set_textrel (struct elf_link_hash_entry *h, void *info_p) - - static bool - record_relr (struct loongarch_elf_link_hash_table *htab, asection *sec, -- bfd_vma off, asection *sreloc) -+ bfd_vma off, asection *sreloc) - { - struct relr_entry **sec_relr = &loongarch_elf_section_data (sec)->relr; - -@@ -1960,14 +1960,14 @@ record_relr (struct loongarch_elf_link_hash_table *htab, asection *sec, - if (htab->relr_count >= htab->relr_alloc) - { - if (htab->relr_alloc == 0) -- htab->relr_alloc = 4096; -+ htab->relr_alloc = 4096; - else -- htab->relr_alloc *= 2; -+ htab->relr_alloc *= 2; - - htab->relr = bfd_realloc (htab->relr, -- htab->relr_alloc * sizeof (*htab->relr)); -+ htab->relr_alloc * sizeof (*htab->relr)); - if (!htab->relr) -- return false; -+ return false; - } - htab->relr[htab->relr_count].sec = sec; - htab->relr[htab->relr_count].off = off; -@@ -1994,11 +1994,11 @@ record_relr_local_got_relocs (bfd *input_bfd, struct bfd_link_info *info) - bfd_vma off = local_got_offsets[i]; - - /* FIXME: If the local symbol is in SHN_ABS then emitting -- a relative relocation is not correct, but it seems to be wrong -- in loongarch_elf_relocate_section too. */ -+ a relative relocation is not correct, but it seems to be wrong -+ in loongarch_elf_relocate_section too. */ - if (local_tls_type[i] == GOT_NORMAL -- && !record_relr (htab, htab->elf.sgot, off, htab->elf.srelgot)) -- return false; -+ && !record_relr (htab, htab->elf.sgot, off, htab->elf.srelgot)) -+ return false; - } - - return true; -@@ -2036,7 +2036,7 @@ record_relr_dyn_got_relocs (struct elf_link_hash_entry *h, void *inf) - return true; - - if (!record_relr (htab, htab->elf.sgot, h->got.offset, -- htab->elf.srelgot)) -+ htab->elf.srelgot)) - return false; - - return true; -@@ -2044,7 +2044,7 @@ record_relr_dyn_got_relocs (struct elf_link_hash_entry *h, void *inf) - - static bool - record_relr_non_got_relocs (bfd *input_bfd, struct bfd_link_info *info, -- asection *sec) -+ asection *sec) - { - asection *sreloc; - struct loongarch_elf_link_hash_table *htab; -@@ -2072,7 +2072,7 @@ record_relr_non_got_relocs (bfd *input_bfd, struct bfd_link_info *info, - symtab_hdr = &elf_symtab_hdr (input_bfd); - sym_hashes = elf_sym_hashes (input_bfd); - relocs = _bfd_elf_link_info_read_relocs (input_bfd, info, sec, NULL, -- NULL, info->keep_memory); -+ NULL, info->keep_memory); - BFD_ASSERT (relocs != NULL); - rel_end = relocs + sec->reloc_count; - for (rel = relocs; rel < rel_end; rel++) -@@ -2083,59 +2083,59 @@ record_relr_non_got_relocs (bfd *input_bfd, struct bfd_link_info *info, - asection *def_sec = NULL; - - if ((r_type != R_LARCH_64 && r_type != R_LARCH_32) -- || rel->r_offset % 2 != 0) -- continue; -+ || rel->r_offset % 2 != 0) -+ continue; - - /* The logical below must match loongarch_elf_relocate_section. */ - if (r_symndx < symtab_hdr->sh_info) -- { -- /* A local symbol. */ -- Elf_Internal_Sym *isym; -- isym = bfd_sym_from_r_symndx (&htab->elf.sym_cache, input_bfd, -- r_symndx); -- BFD_ASSERT(isym != NULL); -- -- /* Local STT_GNU_IFUNC symbol uses R_LARCH_IRELATIVE for -- R_LARCH_NN, not R_LARCH_RELATIVE. */ -- if (ELF_ST_TYPE (isym->st_info) == STT_GNU_IFUNC) -- continue; -- def_sec = bfd_section_from_elf_index (input_bfd, isym->st_shndx); -- } -+ { -+ /* A local symbol. */ -+ Elf_Internal_Sym *isym; -+ isym = bfd_sym_from_r_symndx (&htab->elf.sym_cache, input_bfd, -+ r_symndx); -+ BFD_ASSERT(isym != NULL); -+ -+ /* Local STT_GNU_IFUNC symbol uses R_LARCH_IRELATIVE for -+ R_LARCH_NN, not R_LARCH_RELATIVE. */ -+ if (ELF_ST_TYPE (isym->st_info) == STT_GNU_IFUNC) -+ continue; -+ def_sec = bfd_section_from_elf_index (input_bfd, isym->st_shndx); -+ } - else -- { -- h = sym_hashes[r_symndx - symtab_hdr->sh_info]; -- while (h->root.type == bfd_link_hash_indirect -- || h->root.type == bfd_link_hash_warning) -- h = (struct elf_link_hash_entry *) h->root.u.i.link; -- -- /* Filter out symbols that cannot have a relative reloc. */ -- if (h->dyn_relocs == NULL) -- continue; -- if (bfd_is_abs_symbol (&h->root)) -- continue; -- if (h->type == STT_GNU_IFUNC) -- continue; -- -- if (h->root.type == bfd_link_hash_defined -- || h->root.type == bfd_link_hash_defweak) -- def_sec = h->root.u.def.section; -- -- /* On LoongArch an R_LARCH_NN against undefined weak symbol -- is never converted to R_LARCH_RELATIVE: we don't have -- -z dynamic-undefined-weak, thus the reloc is either removed -- (if the symbol is LARCH_REF_LOCAL) or kept (otherwise). */ -- if (h->root.type == bfd_link_hash_undefweak) -- continue; -- -- if (!LARCH_REF_LOCAL (info, h)) -- continue; -- } -+ { -+ h = sym_hashes[r_symndx - symtab_hdr->sh_info]; -+ while (h->root.type == bfd_link_hash_indirect -+ || h->root.type == bfd_link_hash_warning) -+ h = (struct elf_link_hash_entry *) h->root.u.i.link; -+ -+ /* Filter out symbols that cannot have a relative reloc. */ -+ if (h->dyn_relocs == NULL) -+ continue; -+ if (bfd_is_abs_symbol (&h->root)) -+ continue; -+ if (h->type == STT_GNU_IFUNC) -+ continue; -+ -+ if (h->root.type == bfd_link_hash_defined -+ || h->root.type == bfd_link_hash_defweak) -+ def_sec = h->root.u.def.section; -+ -+ /* On LoongArch an R_LARCH_NN against undefined weak symbol -+ is never converted to R_LARCH_RELATIVE: we don't have -+ -z dynamic-undefined-weak, thus the reloc is either removed -+ (if the symbol is LARCH_REF_LOCAL) or kept (otherwise). */ -+ if (h->root.type == bfd_link_hash_undefweak) -+ continue; -+ -+ if (!LARCH_REF_LOCAL (info, h)) -+ continue; -+ } - - if (!def_sec || discarded_section (def_sec)) -- continue; -+ continue; - - if (!record_relr (htab, sec, rel->r_offset, sreloc)) -- return false; -+ return false; - } - - return true; -@@ -2150,7 +2150,7 @@ cmp_relr_addr (const void *p, const void *q) - - static bool - sort_relr (struct bfd_link_info *info, -- struct loongarch_elf_link_hash_table *htab) -+ struct loongarch_elf_link_hash_table *htab) - { - if (htab->relr_count == 0) - return true; -@@ -2160,17 +2160,17 @@ sort_relr (struct bfd_link_info *info, - { - addr = bfd_malloc (htab->relr_count * sizeof (*addr)); - if (!addr) -- return false; -+ return false; - htab->relr_sorted = addr; - } - - for (bfd_size_type i = 0; i < htab->relr_count; i++) - { - bfd_vma off = _bfd_elf_section_offset (info->output_bfd, info, -- htab->relr[i].sec, -- htab->relr[i].off); -+ htab->relr[i].sec, -+ htab->relr[i].off); - addr[i] = htab->relr[i].sec->output_section->vma -- + htab->relr[i].sec->output_offset + off; -+ + htab->relr[i].sec->output_offset + off; - } - qsort(addr, htab->relr_count, sizeof (*addr), cmp_relr_addr); - return true; -@@ -2178,7 +2178,7 @@ sort_relr (struct bfd_link_info *info, - - static bool - loongarch_elf_size_relative_relocs (struct bfd_link_info *info, -- bool *need_layout) -+ bool *need_layout) - { - struct loongarch_elf_link_hash_table *htab = - loongarch_elf_hash_table (info); -@@ -2200,29 +2200,29 @@ loongarch_elf_size_relative_relocs (struct bfd_link_info *info, - srelrdyn->size += NN / 8; - base += NN / 8; - while (1) -- { -- bfd_size_type start_i = i; -- while (i < htab->relr_count -- && addr[i] - base < (NN - 1) * (NN / 8) -- && (addr[i] - base) % (NN / 8) == 0) -- i++; -- if (i == start_i) -- break; -- srelrdyn->size += NN / 8; -- base += (NN - 1) * (NN / 8); -- } -+ { -+ bfd_size_type start_i = i; -+ while (i < htab->relr_count -+ && addr[i] - base < (NN - 1) * (NN / 8) -+ && (addr[i] - base) % (NN / 8) == 0) -+ i++; -+ if (i == start_i) -+ break; -+ srelrdyn->size += NN / 8; -+ base += (NN - 1) * (NN / 8); -+ } - } - if (srelrdyn->size != oldsize) - { - *need_layout = true; - /* Stop after a few iterations in case the layout does not converge, -- but we can only stop when the size would shrink (and pad the -- spare space with 1. */ -+ but we can only stop when the size would shrink (and pad the -+ spare space with 1. */ - if (htab->relr_layout_iter++ > 5 && srelrdyn->size < oldsize) -- { -- srelrdyn->size = oldsize; -- *need_layout = false; -- } -+ { -+ srelrdyn->size = oldsize; -+ *need_layout = false; -+ } - } - - htab->layout_mutating_for_relr = *need_layout; -@@ -2254,22 +2254,22 @@ loongarch_elf_finish_relative_relocs (struct bfd_link_info *info) - loc += NN / 8; - base += NN / 8; - while (1) -- { -- uintNN_t bits = 0; -- while (i < htab->relr_count) -- { -- bfd_vma delta = addr[i] - base; -- if (delta >= (NN - 1) * (NN / 8) || delta % (NN / 8) != 0) -- break; -- bits |= (uintNN_t) 1 << (delta / (NN / 8)); -- i++; -- } -- if (bits == 0) -- break; -- bfd_put_NN (dynobj, (bits << 1) | 1, loc); -- loc += NN / 8; -- base += (NN - 1) * (NN / 8); -- } -+ { -+ uintNN_t bits = 0; -+ while (i < htab->relr_count) -+ { -+ bfd_vma delta = addr[i] - base; -+ if (delta >= (NN - 1) * (NN / 8) || delta % (NN / 8) != 0) -+ break; -+ bits |= (uintNN_t) 1 << (delta / (NN / 8)); -+ i++; -+ } -+ if (bits == 0) -+ break; -+ bfd_put_NN (dynobj, (bits << 1) | 1, loc); -+ loc += NN / 8; -+ base += (NN - 1) * (NN / 8); -+ } - } - - free (addr); -@@ -2469,17 +2469,17 @@ loongarch_elf_size_dynamic_sections (bfd *output_bfd, - elf_link_hash_traverse (&htab->elf, record_relr_dyn_got_relocs, info); - - for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next) -- { -- if (!is_loongarch_elf (ibfd)) -- continue; -+ { -+ if (!is_loongarch_elf (ibfd)) -+ continue; - -- for (s = ibfd->sections; s != NULL; s = s->next) -- if (!record_relr_non_got_relocs (ibfd, info, s)) -- return false; -+ for (s = ibfd->sections; s != NULL; s = s->next) -+ if (!record_relr_non_got_relocs (ibfd, info, s)) -+ return false; - -- if (!record_relr_local_got_relocs (ibfd, info)) -- return false; -- } -+ if (!record_relr_local_got_relocs (ibfd, info)) -+ return false; -+ } - } - - /* The check_relocs and adjust_dynamic_symbol entry points have -@@ -2507,13 +2507,13 @@ loongarch_elf_size_dynamic_sections (bfd *output_bfd, - } - } - else if (s == htab->elf.srelrdyn && htab->relr_count == 0) -- { -- /* Remove .relr.dyn based on relr_count, not size, since -- it is not sized yet. */ -- s->flags |= SEC_EXCLUDE; -- /* Allocate contents later. */ -- continue; -- } -+ { -+ /* Remove .relr.dyn based on relr_count, not size, since -+ it is not sized yet. */ -+ s->flags |= SEC_EXCLUDE; -+ /* Allocate contents later. */ -+ continue; -+ } - else - { - /* It's not one of our sections. */ -@@ -3430,21 +3430,21 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, - if (unresolved_reloc - && (ARCH_SIZE == 32 || r_type != R_LARCH_32) - && !(h && (h->is_weakalias || !h->dyn_relocs))) -- { -- if (info->enable_dt_relr -- && (ELFNN_R_TYPE (outrel.r_info) == R_LARCH_RELATIVE) -- && input_section->alignment_power != 0 -- && rel->r_offset % 2 == 0) -- /* Don't emit a relative relocation that is packed, -- only apply the addend (as if we are applying the -- original R_LARCH_NN reloc in a PDE). */ -- r = perform_relocation (rel, input_section, howto, -- relocation, input_bfd, -- contents); -- else -- loongarch_elf_append_rela (output_bfd, sreloc, -- &outrel); -- } -+ { -+ if (info->enable_dt_relr -+ && (ELFNN_R_TYPE (outrel.r_info) == R_LARCH_RELATIVE) -+ && input_section->alignment_power != 0 -+ && rel->r_offset % 2 == 0) -+ /* Don't emit a relative relocation that is packed, -+ only apply the addend (as if we are applying the -+ original R_LARCH_NN reloc in a PDE). */ -+ r = perform_relocation (rel, input_section, howto, -+ relocation, input_bfd, -+ contents); -+ else -+ loongarch_elf_append_rela (output_bfd, sreloc, -+ &outrel); -+ } - } - - relocation += rel->r_addend; -@@ -5725,16 +5725,16 @@ loongarch_elf_finish_dynamic_symbol (bfd *output_bfd, - else if (bfd_link_pic (info) && LARCH_REF_LOCAL (info, h)) - { - asection *sec = h->root.u.def.section; -- bfd_vma linkaddr = h->root.u.def.value + sec->output_section->vma -- + sec->output_offset; -- -- /* Don't emit relative relocs if they are packed, but we need -- to write the addend (link-time addr) into the GOT then. */ -- if (info->enable_dt_relr) -- { -- bfd_put_NN (output_bfd, linkaddr, sgot->contents + off); -- goto skip_got_reloc; -- } -+ bfd_vma linkaddr = h->root.u.def.value + sec->output_section->vma -+ + sec->output_offset; -+ -+ /* Don't emit relative relocs if they are packed, but we need -+ to write the addend (link-time addr) into the GOT then. */ -+ if (info->enable_dt_relr) -+ { -+ bfd_put_NN (output_bfd, linkaddr, sgot->contents + off); -+ goto skip_got_reloc; -+ } - rela.r_info = ELFNN_R_INFO (0, R_LARCH_RELATIVE); - rela.r_addend = linkaddr; - } --- -2.33.0 - -- Gitee