From dd30deb6100e2b8578d4157ee4b96b5be1543487 Mon Sep 17 00:00:00 2001 From: Dengdui Huang Date: Fri, 10 May 2024 16:25:20 +0800 Subject: [PATCH] sync some patch from upstreaming Sync some patchs from upstreaming for hns3 pmd and modifications are as follow: - dma/hisilicon: remove support for HIP09 platform - net/hns3: disable SCTP verification tag for RSS hash input - net/hns3: fix variable overflow - net/hns3: fix double free for Rx/Tx queue - net/hns3: fix read Rx timestamp handle - net/hns3: fix offload flag of IEEE 1588 In addition, the following patch synchronizes the latest version - ethdev: fix strict aliasing lead to link cannot be up Signed-off-by: Dengdui Huang (cherry picked from commit 60fad33c2a49d948d5816889cb40f0184f826149) --- ...t-aliasing-lead-to-link-cannot-be-up.patch | 105 ++++++++--- ...t-hns3-fix-offload-flag-of-IEEE-1588.patch | 44 +++++ ...et-hns3-fix-read-Rx-timestamp-handle.patch | 36 ++++ ...hns3-fix-double-free-for-Rx-Tx-queue.patch | 67 +++++++ 0040-net-hns3-fix-variable-overflow.patch | 35 ++++ ...-verification-tag-for-RSS-hash-input.patch | 93 ++++++++++ ...on-remove-support-for-HIP09-platform.patch | 175 ++++++++++++++++++ dpdk.spec | 21 ++- 8 files changed, 551 insertions(+), 25 deletions(-) create mode 100644 0037-net-hns3-fix-offload-flag-of-IEEE-1588.patch create mode 100644 0038-net-hns3-fix-read-Rx-timestamp-handle.patch create mode 100644 0039-net-hns3-fix-double-free-for-Rx-Tx-queue.patch create mode 100644 0040-net-hns3-fix-variable-overflow.patch create mode 100644 0041-net-hns3-disable-SCTP-verification-tag-for-RSS-hash-input.patch create mode 100644 0042-dma-hisilicon-remove-support-for-HIP09-platform.patch diff --git a/0032-ethdev-fix-strict-aliasing-lead-to-link-cannot-be-up.patch b/0032-ethdev-fix-strict-aliasing-lead-to-link-cannot-be-up.patch index 5a85744..95504c0 100644 --- a/0032-ethdev-fix-strict-aliasing-lead-to-link-cannot-be-up.patch +++ b/0032-ethdev-fix-strict-aliasing-lead-to-link-cannot-be-up.patch @@ -1,29 +1,83 @@ -From 784ba0a03ddd16a54b9d23757d587b67b832e2b7 Mon Sep 17 00:00:00 2001 +From bdc14ddec75a529e6ecf327e78d5746c120247ff Mon Sep 17 00:00:00 2001 From: Chengwen Feng -Date: Thu, 11 Apr 2024 12:04:08 +0000 +Date: Mon, 22 Apr 2024 06:38:13 +0000 Subject: [PATCH] ethdev: fix strict aliasing lead to link cannot be up +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +[ upstream commit 8841786ab4aa72d205f97528af8708a13a851f4f ] Fix a problem introduced by a compiler upgrade (from gcc10 to gcc12.3), which will lead the hns3 NIC can't link up. The root cause is strict aliasing violation in rte_eth_linkstatus_set() with hns3 driver, see [1] for more details. -This commit use union to avoid such aliasing violation. +This commit use union to avoid such aliasing violation. Also the +impacted components (cxgbe and qos_sched) have been adapted to the +struct change. -[1] Strict aliasing problem with rte_eth_linkstatus_set() - https://marc.info/?l=dpdk-dev&m=171274148514777&w=3 +[1] https://inbox.dpdk.org/dev/8175c905-e661-b910-7f20-59b6ab605c38@huawei.com/ Cc: stable@dpdk.org Signed-off-by: Chengwen Feng Signed-off-by: Dengdui Huang +Acked-by: Morten Brørup +Acked-by: Ferruh Yigit --- - lib/ethdev/ethdev_driver.h | 23 +++++++---------------- - lib/ethdev/rte_ethdev.h | 16 ++++++++++------ - 2 files changed, 17 insertions(+), 22 deletions(-) + drivers/net/cxgbe/cxgbe_ethdev.c | 3 ++- + examples/qos_sched/init.c | 3 ++- + lib/ethdev/ethdev_driver.h | 24 +++++++++--------------- + lib/ethdev/rte_ethdev.h | 17 +++++++++++------ + 4 files changed, 24 insertions(+), 23 deletions(-) +diff --git a/drivers/net/cxgbe/cxgbe_ethdev.c b/drivers/net/cxgbe/cxgbe_ethdev.c +index 8cc3d9f..781f48c 100644 +--- a/drivers/net/cxgbe/cxgbe_ethdev.c ++++ b/drivers/net/cxgbe/cxgbe_ethdev.c +@@ -211,9 +211,9 @@ int cxgbe_dev_link_update(struct rte_eth_dev *eth_dev, + unsigned int i, work_done, budget = 32; + struct link_config *lc = &pi->link_cfg; + struct adapter *adapter = pi->adapter; +- struct rte_eth_link new_link = { 0 }; + u8 old_link = pi->link_cfg.link_ok; + struct sge *s = &adapter->sge; ++ struct rte_eth_link new_link; + + for (i = 0; i < CXGBE_LINK_STATUS_POLL_CNT; i++) { + if (!s->fw_evtq.desc) +@@ -232,6 +232,7 @@ int cxgbe_dev_link_update(struct rte_eth_dev *eth_dev, + rte_delay_ms(CXGBE_LINK_STATUS_POLL_MS); + } + ++ memset(&new_link, 0, sizeof(new_link)); + new_link.link_status = cxgbe_force_linkup(adapter) ? + RTE_ETH_LINK_UP : pi->link_cfg.link_ok; + new_link.link_autoneg = (lc->link_caps & FW_PORT_CAP32_ANEG) ? 1 : 0; +diff --git a/examples/qos_sched/init.c b/examples/qos_sched/init.c +index d8abae6..32964fd 100644 +--- a/examples/qos_sched/init.c ++++ b/examples/qos_sched/init.c +@@ -335,7 +335,7 @@ int app_init(void) + for(i = 0; i < nb_pfc; i++) { + uint32_t socket = rte_lcore_to_socket_id(qos_conf[i].rx_core); + struct rte_ring *ring; +- struct rte_eth_link link = {0}; ++ struct rte_eth_link link; + int retry_count = 100, retry_delay = 100; /* try every 100ms for 10 sec */ + + snprintf(ring_name, MAX_NAME_LEN, "ring-%u-%u", i, qos_conf[i].rx_core); +@@ -367,6 +367,7 @@ int app_init(void) + app_init_port(qos_conf[i].rx_port, qos_conf[i].mbuf_pool); + app_init_port(qos_conf[i].tx_port, qos_conf[i].mbuf_pool); + ++ memset(&link, 0, sizeof(link)); + rte_eth_link_get(qos_conf[i].tx_port, &link); + if (link.link_status == 0) + printf("Waiting for link on port %u\n", qos_conf[i].tx_port); diff --git a/lib/ethdev/ethdev_driver.h b/lib/ethdev/ethdev_driver.h -index b482cd1..12a7bfc 100644 +index b482cd1..ec56925 100644 --- a/lib/ethdev/ethdev_driver.h +++ b/lib/ethdev/ethdev_driver.h @@ -1655,18 +1655,13 @@ static inline int @@ -50,7 +104,7 @@ index b482cd1..12a7bfc 100644 } /** -@@ -1682,12 +1677,8 @@ static inline void +@@ -1682,12 +1677,11 @@ static inline void rte_eth_linkstatus_get(const struct rte_eth_dev *dev, struct rte_eth_link *link) { @@ -58,18 +112,20 @@ index b482cd1..12a7bfc 100644 - uint64_t *dst = (uint64_t *)link; - - RTE_BUILD_BUG_ON(sizeof(*link) != sizeof(uint64_t)); -- ++ struct rte_eth_link curr_link; + - *dst = rte_atomic_load_explicit(src, rte_memory_order_seq_cst); -+ link->val64 = rte_atomic_load_explicit(&dev->data->dev_link.val64, -+ rte_memory_order_seq_cst); ++ curr_link.val64 = rte_atomic_load_explicit(&dev->data->dev_link.val64, ++ rte_memory_order_seq_cst); ++ rte_atomic_store_explicit(&link->val64, curr_link.val64, rte_memory_order_seq_cst); } /** diff --git a/lib/ethdev/rte_ethdev.h b/lib/ethdev/rte_ethdev.h -index 57a9a55..b4b0357 100644 +index 57a9a55..b95ae69 100644 --- a/lib/ethdev/rte_ethdev.h +++ b/lib/ethdev/rte_ethdev.h -@@ -331,13 +331,17 @@ struct rte_eth_stats { +@@ -331,13 +331,18 @@ struct rte_eth_stats { /** * A structure used to retrieve link-level information of an Ethernet port. */ @@ -80,15 +136,16 @@ index 57a9a55..b4b0357 100644 - uint16_t link_autoneg : 1; /**< RTE_ETH_LINK_[AUTONEG/FIXED] */ - uint16_t link_status : 1; /**< RTE_ETH_LINK_[DOWN/UP] */ -} __rte_aligned(8); /**< aligned for atomic64 read/write */ -+ union { -+ RTE_ATOMIC(uint64_t) val64; /**< used for atomic64 read/write */ -+ struct { -+ uint32_t link_speed; /**< RTE_ETH_SPEED_NUM_ */ -+ uint16_t link_duplex : 1; /**< RTE_ETH_LINK_[HALF/FULL]_DUPLEX */ -+ uint16_t link_autoneg : 1; /**< RTE_ETH_LINK_[AUTONEG/FIXED] */ -+ uint16_t link_status : 1; /**< RTE_ETH_LINK_[DOWN/UP] */ -+ }; -+ }; ++ union { ++ RTE_ATOMIC(uint64_t) val64; /**< used for atomic64 read/write */ ++ __extension__ ++ struct { ++ uint32_t link_speed; /**< RTE_ETH_SPEED_NUM_ */ ++ uint16_t link_duplex : 1; /**< RTE_ETH_LINK_[HALF/FULL]_DUPLEX */ ++ uint16_t link_autoneg : 1; /**< RTE_ETH_LINK_[AUTONEG/FIXED] */ ++ uint16_t link_status : 1; /**< RTE_ETH_LINK_[DOWN/UP] */ ++ }; ++ }; +}; /**@{@name Link negotiation diff --git a/0037-net-hns3-fix-offload-flag-of-IEEE-1588.patch b/0037-net-hns3-fix-offload-flag-of-IEEE-1588.patch new file mode 100644 index 0000000..a609605 --- /dev/null +++ b/0037-net-hns3-fix-offload-flag-of-IEEE-1588.patch @@ -0,0 +1,44 @@ +From 3111c03a6329f87d84f5938dc2d371a9f7820198 Mon Sep 17 00:00:00 2001 +From: Dengdui Huang +Date: Wed, 3 Apr 2024 18:16:19 +0800 +Subject: [PATCH 37/42] net/hns3: fix offload flag of IEEE 1588 + +[ upstream commit 5fde4c41f26d2ad607935b76b528e1b64727b5c7 ] + +Currently, the RTE_MBUF_F_RX_IEEE1588_TMST offload flag will +not be set when the scatter algorithm is used. +This patch fixes it. + +Fixes: 4801f0403b58 ("net/hns3: fix IEEE 1588 PTP for scalar scattered Rx") +Cc: stable@dpdk.org + +Signed-off-by: Dengdui Huang +Signed-off-by: Jie Hai +--- + drivers/net/hns3/hns3_rxtx.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c +index 04ae8dc..dc5246b 100644 +--- a/drivers/net/hns3/hns3_rxtx.c ++++ b/drivers/net/hns3/hns3_rxtx.c +@@ -2668,6 +2668,7 @@ hns3_recv_scattered_pkts(void *rx_queue, + continue; + } + ++ first_seg->ol_flags = 0; + if (unlikely(bd_base_info & BIT(HNS3_RXD_TS_VLD_B))) + hns3_rx_ptp_timestamp_handle(rxq, first_seg, timestamp); + +@@ -2697,7 +2698,7 @@ hns3_recv_scattered_pkts(void *rx_queue, + + first_seg->port = rxq->port_id; + first_seg->hash.rss = rte_le_to_cpu_32(rxd.rx.rss_hash); +- first_seg->ol_flags = RTE_MBUF_F_RX_RSS_HASH; ++ first_seg->ol_flags |= RTE_MBUF_F_RX_RSS_HASH; + if (unlikely(bd_base_info & BIT(HNS3_RXD_LUM_B))) { + first_seg->hash.fdir.hi = + rte_le_to_cpu_16(rxd.rx.fd_id); +-- +2.33.0 + diff --git a/0038-net-hns3-fix-read-Rx-timestamp-handle.patch b/0038-net-hns3-fix-read-Rx-timestamp-handle.patch new file mode 100644 index 0000000..3345895 --- /dev/null +++ b/0038-net-hns3-fix-read-Rx-timestamp-handle.patch @@ -0,0 +1,36 @@ +From a67a0d6060ef0f806f31db80bb7e5627fedaf58c Mon Sep 17 00:00:00 2001 +From: Dengdui Huang +Date: Wed, 3 Apr 2024 18:16:20 +0800 +Subject: [PATCH 38/42] net/hns3: fix read Rx timestamp handle + +[ upstream commit 0a96792880b7eb410f3c4ae4843d82df7005a627 ] + +The flag RTE_MBUF_F_RX_IEEE1588_PTP depends on the packet +type and does not need to be set when reading Rx timestamp. + +Fixes: 38b539d96eb6 ("net/hns3: support IEEE 1588 PTP") +Cc: stable@dpdk.org + +Signed-off-by: Dengdui Huang +Signed-off-by: Jie Hai +--- + drivers/net/hns3/hns3_rxtx.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c +index dc5246b..bba29a9 100644 +--- a/drivers/net/hns3/hns3_rxtx.c ++++ b/drivers/net/hns3/hns3_rxtx.c +@@ -2388,8 +2388,7 @@ hns3_rx_ptp_timestamp_handle(struct hns3_rx_queue *rxq, struct rte_mbuf *mbuf, + { + struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(rxq->hns); + +- mbuf->ol_flags |= RTE_MBUF_F_RX_IEEE1588_PTP | +- RTE_MBUF_F_RX_IEEE1588_TMST; ++ mbuf->ol_flags |= RTE_MBUF_F_RX_IEEE1588_TMST; + if (hns3_timestamp_rx_dynflag > 0) { + *RTE_MBUF_DYNFIELD(mbuf, hns3_timestamp_dynfield_offset, + rte_mbuf_timestamp_t *) = timestamp; +-- +2.33.0 + diff --git a/0039-net-hns3-fix-double-free-for-Rx-Tx-queue.patch b/0039-net-hns3-fix-double-free-for-Rx-Tx-queue.patch new file mode 100644 index 0000000..a1f048e --- /dev/null +++ b/0039-net-hns3-fix-double-free-for-Rx-Tx-queue.patch @@ -0,0 +1,67 @@ +From 5f3efed4c06e8d68aa2089db660c4c23b21df291 Mon Sep 17 00:00:00 2001 +From: Dengdui Huang +Date: Wed, 3 Apr 2024 18:16:21 +0800 +Subject: [PATCH 39/42] net/hns3: fix double free for Rx/Tx queue + +[ upstream commit 833a5beab5bfc16708ee9b53c83e2f221cd99f90 ] + +The Pointers to some resources on the Rx/Tx queue need to be set to NULL +after free inside the hns3_rx/tx_queue_release(), as this function is +called from multiple threads (reset thread, device config thread, etc), +leading to double memory free error. + +Fixes: bba636698316 ("net/hns3: support Rx/Tx and related operations") +Cc: stable@dpdk.org + +Signed-off-by: Dengdui Huang +Signed-off-by: Jie Hai +--- + drivers/net/hns3/hns3_rxtx.c | 23 ++++++++++++++++++----- + 1 file changed, 18 insertions(+), 5 deletions(-) + +diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c +index bba29a9..d43cc96 100644 +--- a/drivers/net/hns3/hns3_rxtx.c ++++ b/drivers/net/hns3/hns3_rxtx.c +@@ -86,9 +86,14 @@ hns3_rx_queue_release(void *queue) + struct hns3_rx_queue *rxq = queue; + if (rxq) { + hns3_rx_queue_release_mbufs(rxq); +- if (rxq->mz) ++ if (rxq->mz) { + rte_memzone_free(rxq->mz); +- rte_free(rxq->sw_ring); ++ rxq->mz = NULL; ++ } ++ if (rxq->sw_ring) { ++ rte_free(rxq->sw_ring); ++ rxq->sw_ring = NULL; ++ } + rte_free(rxq); + } + } +@@ -99,10 +104,18 @@ hns3_tx_queue_release(void *queue) + struct hns3_tx_queue *txq = queue; + if (txq) { + hns3_tx_queue_release_mbufs(txq); +- if (txq->mz) ++ if (txq->mz) { + rte_memzone_free(txq->mz); +- rte_free(txq->sw_ring); +- rte_free(txq->free); ++ txq->mz = NULL; ++ } ++ if (txq->sw_ring) { ++ rte_free(txq->sw_ring); ++ txq->sw_ring = NULL; ++ } ++ if (txq->free) { ++ rte_free(txq->free); ++ txq->free = NULL; ++ } + rte_free(txq); + } + } +-- +2.33.0 + diff --git a/0040-net-hns3-fix-variable-overflow.patch b/0040-net-hns3-fix-variable-overflow.patch new file mode 100644 index 0000000..68b2b09 --- /dev/null +++ b/0040-net-hns3-fix-variable-overflow.patch @@ -0,0 +1,35 @@ +From 262dd61124d4fe105af5d36e2a01f7ed6865aa48 Mon Sep 17 00:00:00 2001 +From: Dengdui Huang +Date: Wed, 3 Apr 2024 18:16:22 +0800 +Subject: [PATCH 40/42] net/hns3: fix variable overflow + +[ upstream commit 861bfb275cb4aea37253c3171f922a0131afb1a3 ] + +The function strtoul() returns an unsigned long, which should +be received using the variable uint64_t. + +Fixes: 2fc3e696a7f1 ("net/hns3: add runtime config for mailbox limit time") +Cc: stable@dpdk.org + +Signed-off-by: Dengdui Huang +Signed-off-by: Jie Hai +--- + drivers/net/hns3/hns3_common.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/net/hns3/hns3_common.c b/drivers/net/hns3/hns3_common.c +index 28c26b0..5e6cdfd 100644 +--- a/drivers/net/hns3/hns3_common.c ++++ b/drivers/net/hns3/hns3_common.c +@@ -224,7 +224,7 @@ hns3_parse_dev_caps_mask(const char *key, const char *value, void *extra_args) + static int + hns3_parse_mbx_time_limit(const char *key, const char *value, void *extra_args) + { +- uint32_t val; ++ uint64_t val; + + RTE_SET_USED(key); + +-- +2.33.0 + diff --git a/0041-net-hns3-disable-SCTP-verification-tag-for-RSS-hash-input.patch b/0041-net-hns3-disable-SCTP-verification-tag-for-RSS-hash-input.patch new file mode 100644 index 0000000..8ca1401 --- /dev/null +++ b/0041-net-hns3-disable-SCTP-verification-tag-for-RSS-hash-input.patch @@ -0,0 +1,93 @@ +From 3645f3c0b1ad5fc6d5408d30822ad0244f0801a8 Mon Sep 17 00:00:00 2001 +From: Jie Hai +Date: Wed, 3 Apr 2024 18:16:23 +0800 +Subject: [PATCH 41/42] net/hns3: disable SCTP verification tag for RSS hash + input + +[ upstream commit 47d5fa9a91989c4671ecb8c3a7e767572846570c ] + +When the symmetric RSS algorithm is used, the same packet is +expected to be hashed to the same queue in the upstream and +downstream directions. + +The problem is that it could map the packets in the same SCTP +connection to different NIC RX queues depending on the direction +of packets. This is because the verification Tag is used as the +RSS hash input for the SCTP packets, and the value depends on the +peer end of the SCTP connection and could not be symmetrically +used in the hardware-implemented RSS algorithm. + +In addition, the ethdev framework doesn't support setting SCTP +V-tag as the RSS hash input. So disable it for all RSS hash +algorithms. + +Cc: stable@dpdk.org + +Signed-off-by: Jie Hai +--- + drivers/net/hns3/hns3_rss.c | 6 ++---- + drivers/net/hns3/hns3_rss.h | 6 ++---- + 2 files changed, 4 insertions(+), 8 deletions(-) + +diff --git a/drivers/net/hns3/hns3_rss.c b/drivers/net/hns3/hns3_rss.c +index 15feb26..3eae4ca 100644 +--- a/drivers/net/hns3/hns3_rss.c ++++ b/drivers/net/hns3/hns3_rss.c +@@ -153,8 +153,7 @@ static const struct { + BIT_ULL(HNS3_RSS_FIELD_IPV4_SCTP_EN_IP_S) | + BIT_ULL(HNS3_RSS_FIELD_IPV4_SCTP_EN_IP_D) | + BIT_ULL(HNS3_RSS_FIELD_IPV4_SCTP_EN_SCTP_S) | +- BIT_ULL(HNS3_RSS_FIELD_IPV4_SCTP_EN_SCTP_D) | +- BIT_ULL(HNS3_RSS_FIELD_IPV4_SCTP_EN_SCTP_VER), ++ BIT_ULL(HNS3_RSS_FIELD_IPV4_SCTP_EN_SCTP_D), + HNS3_RSS_TUPLE_IPV4_SCTP_M }, + + /* IPV6-FRAG */ +@@ -274,8 +273,7 @@ static const struct { + BIT_ULL(HNS3_RSS_FIELD_IPV6_SCTP_EN_IP_S) | + BIT_ULL(HNS3_RSS_FIELD_IPV6_SCTP_EN_IP_D) | + BIT_ULL(HNS3_RSS_FIELD_IPV6_SCTP_EN_SCTP_D) | +- BIT_ULL(HNS3_RSS_FIELD_IPV6_SCTP_EN_SCTP_S) | +- BIT_ULL(HNS3_RSS_FIELD_IPV6_SCTP_EN_SCTP_VER), ++ BIT_ULL(HNS3_RSS_FIELD_IPV6_SCTP_EN_SCTP_S), + HNS3_RSS_TUPLE_IPV6_SCTP_M }, + }; + +diff --git a/drivers/net/hns3/hns3_rss.h b/drivers/net/hns3/hns3_rss.h +index 9d182a8..0755760 100644 +--- a/drivers/net/hns3/hns3_rss.h ++++ b/drivers/net/hns3/hns3_rss.h +@@ -49,7 +49,6 @@ enum hns3_tuple_field { + HNS3_RSS_FIELD_IPV4_SCTP_EN_SCTP_S, + HNS3_RSS_FIELD_IPV4_SCTP_EN_IP_D, + HNS3_RSS_FIELD_IPV4_SCTP_EN_IP_S, +- HNS3_RSS_FIELD_IPV4_SCTP_EN_SCTP_VER, + + /* IPV4 ENABLE FIELD */ + HNS3_RSS_FIELD_IPV4_EN_NONFRAG_IP_D = 24, +@@ -74,7 +73,6 @@ enum hns3_tuple_field { + HNS3_RSS_FIELD_IPV6_SCTP_EN_SCTP_S, + HNS3_RSS_FIELD_IPV6_SCTP_EN_IP_D, + HNS3_RSS_FIELD_IPV6_SCTP_EN_IP_S, +- HNS3_RSS_FIELD_IPV6_SCTP_EN_SCTP_VER, + + /* IPV6 ENABLE FIELD */ + HNS3_RSS_FIELD_IPV6_NONFRAG_IP_D = 56, +@@ -96,12 +94,12 @@ enum hns3_tuple_field { + + #define HNS3_RSS_TUPLE_IPV4_TCP_M GENMASK(3, 0) + #define HNS3_RSS_TUPLE_IPV4_UDP_M GENMASK(11, 8) +-#define HNS3_RSS_TUPLE_IPV4_SCTP_M GENMASK(20, 16) ++#define HNS3_RSS_TUPLE_IPV4_SCTP_M GENMASK(19, 16) + #define HNS3_RSS_TUPLE_IPV4_NONF_M GENMASK(25, 24) + #define HNS3_RSS_TUPLE_IPV4_FLAG_M GENMASK(27, 26) + #define HNS3_RSS_TUPLE_IPV6_TCP_M GENMASK(35, 32) + #define HNS3_RSS_TUPLE_IPV6_UDP_M GENMASK(43, 40) +-#define HNS3_RSS_TUPLE_IPV6_SCTP_M GENMASK(52, 48) ++#define HNS3_RSS_TUPLE_IPV6_SCTP_M GENMASK(51, 48) + #define HNS3_RSS_TUPLE_IPV6_NONF_M GENMASK(57, 56) + #define HNS3_RSS_TUPLE_IPV6_FLAG_M GENMASK(59, 58) + +-- +2.33.0 + diff --git a/0042-dma-hisilicon-remove-support-for-HIP09-platform.patch b/0042-dma-hisilicon-remove-support-for-HIP09-platform.patch new file mode 100644 index 0000000..34377c4 --- /dev/null +++ b/0042-dma-hisilicon-remove-support-for-HIP09-platform.patch @@ -0,0 +1,175 @@ +From 87ff4ab73a91d1e045611ca55cb97ff1a5a86306 Mon Sep 17 00:00:00 2001 +From: Chengwen Feng +Date: Mon, 29 Apr 2024 15:15:31 +0800 +Subject: [PATCH 42/42] dma/hisilicon: remove support for HIP09 platform + +The DMA for HIP09 is no longer available, so delete it. + +Cc: stable@dpdk.org + +Signed-off-by: Chengwen Feng +--- + doc/guides/dmadevs/hisilicon.rst | 1 - + drivers/dma/hisilicon/hisi_dmadev.c | 38 ----------------------------- + drivers/dma/hisilicon/hisi_dmadev.h | 35 +------------------------- + 3 files changed, 1 insertion(+), 73 deletions(-) + +diff --git a/doc/guides/dmadevs/hisilicon.rst b/doc/guides/dmadevs/hisilicon.rst +index 8c1f0f8..974bc49 100644 +--- a/doc/guides/dmadevs/hisilicon.rst ++++ b/doc/guides/dmadevs/hisilicon.rst +@@ -13,7 +13,6 @@ Supported Kunpeng SoCs + ---------------------- + + * Kunpeng 920 +-* Kunpeng 930 + + + Device Setup +diff --git a/drivers/dma/hisilicon/hisi_dmadev.c b/drivers/dma/hisilicon/hisi_dmadev.c +index 0e11ca1..18078f7 100644 +--- a/drivers/dma/hisilicon/hisi_dmadev.c ++++ b/drivers/dma/hisilicon/hisi_dmadev.c +@@ -39,8 +39,6 @@ hisi_dma_queue_base(struct hisi_dma_dev *hw) + { + if (hw->reg_layout == HISI_DMA_REG_LAYOUT_HIP08) + return HISI_DMA_HIP08_QUEUE_BASE; +- else if (hw->reg_layout == HISI_DMA_REG_LAYOUT_HIP09) +- return HISI_DMA_HIP09_QUEUE_BASE; + else + return 0; + } +@@ -216,25 +214,6 @@ hisi_dma_init_hw(struct hisi_dma_dev *hw) + HISI_DMA_HIP08_QUEUE_INT_MASK_M, true); + hisi_dma_update_queue_mbit(hw, HISI_DMA_QUEUE_INT_MASK_REG, + HISI_DMA_HIP08_QUEUE_INT_MASK_M, true); +- } else if (hw->reg_layout == HISI_DMA_REG_LAYOUT_HIP09) { +- hisi_dma_update_queue_mbit(hw, HISI_DMA_QUEUE_CTRL0_REG, +- HISI_DMA_HIP09_QUEUE_CTRL0_ERR_ABORT_M, false); +- hisi_dma_update_queue_mbit(hw, HISI_DMA_QUEUE_INT_STATUS_REG, +- HISI_DMA_HIP09_QUEUE_INT_MASK_M, true); +- hisi_dma_update_queue_mbit(hw, HISI_DMA_QUEUE_INT_MASK_REG, +- HISI_DMA_HIP09_QUEUE_INT_MASK_M, true); +- hisi_dma_update_queue_mbit(hw, +- HISI_DMA_HIP09_QUEUE_ERR_INT_STATUS_REG, +- HISI_DMA_HIP09_QUEUE_ERR_INT_MASK_M, true); +- hisi_dma_update_queue_mbit(hw, +- HISI_DMA_HIP09_QUEUE_ERR_INT_MASK_REG, +- HISI_DMA_HIP09_QUEUE_ERR_INT_MASK_M, true); +- hisi_dma_update_queue_bit(hw, HISI_DMA_QUEUE_CTRL1_REG, +- HISI_DMA_HIP09_QUEUE_CTRL1_VA_ENABLE_B, true); +- hisi_dma_update_bit(hw, +- HISI_DMA_HIP09_QUEUE_CFG_REG(hw->queue_id), +- HISI_DMA_HIP09_QUEUE_CFG_LINK_DOWN_MASK_B, +- true); + } + } + +@@ -256,8 +235,6 @@ hisi_dma_reg_layout(uint8_t revision) + { + if (revision == HISI_DMA_REVISION_HIP08B) + return HISI_DMA_REG_LAYOUT_HIP08; +- else if (revision >= HISI_DMA_REVISION_HIP09A) +- return HISI_DMA_REG_LAYOUT_HIP09; + else + return HISI_DMA_REG_LAYOUT_INVALID; + } +@@ -333,9 +310,6 @@ hisi_dma_info_get(const struct rte_dma_dev *dev, + + dev_info->dev_capa = RTE_DMA_CAPA_MEM_TO_MEM | + RTE_DMA_CAPA_OPS_COPY; +- if (hw->reg_layout == HISI_DMA_REG_LAYOUT_HIP09) +- dev_info->dev_capa |= RTE_DMA_CAPA_HANDLES_ERRORS; +- + dev_info->max_vchans = 1; + dev_info->max_desc = HISI_DMA_MAX_DESC_NUM; + dev_info->min_desc = HISI_DMA_MIN_DESC_NUM; +@@ -514,18 +488,6 @@ hisi_dma_dump_common(struct hisi_dma_dev *hw, FILE *f) + { HISI_DMA_REG_LAYOUT_HIP08, + HISI_DMA_HIP08_DUMP_START_REG, + HISI_DMA_HIP08_DUMP_END_REG }, +- { HISI_DMA_REG_LAYOUT_HIP09, +- HISI_DMA_HIP09_DUMP_REGION_A_START_REG, +- HISI_DMA_HIP09_DUMP_REGION_A_END_REG }, +- { HISI_DMA_REG_LAYOUT_HIP09, +- HISI_DMA_HIP09_DUMP_REGION_B_START_REG, +- HISI_DMA_HIP09_DUMP_REGION_B_END_REG }, +- { HISI_DMA_REG_LAYOUT_HIP09, +- HISI_DMA_HIP09_DUMP_REGION_C_START_REG, +- HISI_DMA_HIP09_DUMP_REGION_C_END_REG }, +- { HISI_DMA_REG_LAYOUT_HIP09, +- HISI_DMA_HIP09_DUMP_REGION_D_START_REG, +- HISI_DMA_HIP09_DUMP_REGION_D_END_REG }, + }; + uint32_t i; + +diff --git a/drivers/dma/hisilicon/hisi_dmadev.h b/drivers/dma/hisilicon/hisi_dmadev.h +index 5a17f9f..a57b5c7 100644 +--- a/drivers/dma/hisilicon/hisi_dmadev.h ++++ b/drivers/dma/hisilicon/hisi_dmadev.h +@@ -25,22 +25,14 @@ + #define HISI_DMA_DEVICE_ID 0xA122 + #define HISI_DMA_PCI_REVISION_ID_REG 0x08 + #define HISI_DMA_REVISION_HIP08B 0x21 +-#define HISI_DMA_REVISION_HIP09A 0x30 + + #define HISI_DMA_MAX_HW_QUEUES 4 + #define HISI_DMA_MAX_DESC_NUM 8192 + #define HISI_DMA_MIN_DESC_NUM 32 + +-/** +- * The HIP08B(HiSilicon IP08) and HIP09B(HiSilicon IP09) are DMA iEPs, they +- * have the same pci device id but different pci revision. +- * Unfortunately, they have different register layouts, so two layout +- * enumerations are defined. +- */ + enum { + HISI_DMA_REG_LAYOUT_INVALID = 0, +- HISI_DMA_REG_LAYOUT_HIP08, +- HISI_DMA_REG_LAYOUT_HIP09 ++ HISI_DMA_REG_LAYOUT_HIP08 + }; + + /** +@@ -69,9 +61,6 @@ enum { + * length of queue-region. The global offset for a single queue register is + * calculated by: + * offset = queue-base + (queue-id * queue-region) + reg-offset-in-region. +- * +- * The first part of queue region is basically the same for HIP08 and HIP09 +- * register layouts, therefore, HISI_QUEUE_* registers are defined for it. + */ + #define HISI_DMA_QUEUE_SQ_BASE_L_REG 0x0 + #define HISI_DMA_QUEUE_SQ_BASE_H_REG 0x4 +@@ -110,28 +99,6 @@ enum { + #define HISI_DMA_HIP08_DUMP_START_REG 0x2000 + #define HISI_DMA_HIP08_DUMP_END_REG 0x2280 + +-/** +- * HiSilicon IP09 DMA register and field define: +- */ +-#define HISI_DMA_HIP09_QUEUE_BASE 0x2000 +-#define HISI_DMA_HIP09_QUEUE_CTRL0_ERR_ABORT_M GENMASK(31, 28) +-#define HISI_DMA_HIP09_QUEUE_CTRL1_VA_ENABLE_B 2 +-#define HISI_DMA_HIP09_QUEUE_INT_MASK_M 0x1 +-#define HISI_DMA_HIP09_QUEUE_ERR_INT_STATUS_REG 0x48 +-#define HISI_DMA_HIP09_QUEUE_ERR_INT_MASK_REG 0x4C +-#define HISI_DMA_HIP09_QUEUE_ERR_INT_MASK_M GENMASK(18, 1) +-#define HISI_DMA_HIP09_QUEUE_CFG_REG(queue_id) (0x800 + \ +- (queue_id) * 0x20) +-#define HISI_DMA_HIP09_QUEUE_CFG_LINK_DOWN_MASK_B 16 +-#define HISI_DMA_HIP09_DUMP_REGION_A_START_REG 0x0 +-#define HISI_DMA_HIP09_DUMP_REGION_A_END_REG 0x368 +-#define HISI_DMA_HIP09_DUMP_REGION_B_START_REG 0x800 +-#define HISI_DMA_HIP09_DUMP_REGION_B_END_REG 0xA08 +-#define HISI_DMA_HIP09_DUMP_REGION_C_START_REG 0x1800 +-#define HISI_DMA_HIP09_DUMP_REGION_C_END_REG 0x1A4C +-#define HISI_DMA_HIP09_DUMP_REGION_D_START_REG 0x1C00 +-#define HISI_DMA_HIP09_DUMP_REGION_D_END_REG 0x1CC4 +- + /** + * In fact, there are multiple states, but it need to pay attention to + * the following three states for the driver: +-- +2.33.0 + diff --git a/dpdk.spec b/dpdk.spec index 0e8b12d..78a0070 100644 --- a/dpdk.spec +++ b/dpdk.spec @@ -10,7 +10,7 @@ Name: dpdk Version: 23.11 -Release: 16 +Release: 17 URL: http://dpdk.org Source: https://fast.dpdk.org/rel/dpdk-%{version}.tar.xz @@ -59,6 +59,13 @@ Patch6035: 0035-net-hns3-support-new-device.patch Patch9036: 0036-require-at-least-two-segs-per-memseg-lists-in-map-pe.patch +Patch6037: 0037-net-hns3-fix-offload-flag-of-IEEE-1588.patch +Patch6038: 0038-net-hns3-fix-read-Rx-timestamp-handle.patch +Patch6039: 0039-net-hns3-fix-double-free-for-Rx-Tx-queue.patch +Patch6040: 0040-net-hns3-fix-variable-overflow.patch +Patch6041: 0041-net-hns3-disable-SCTP-verification-tag-for-RSS-hash-input.patch +Patch6042: 0042-dma-hisilicon-remove-support-for-HIP09-platform.patch + BuildRequires: meson BuildRequires: python3-pyelftools BuildRequires: diffutils @@ -259,6 +266,18 @@ strip -g $RPM_BUILD_ROOT/lib/modules/%{kern_devel_ver}/extra/dpdk/igb_uio.ko %endif %changelog +* Fri May 10 2024 huangdengdui - 23.11-17 + Sync some patchs from upstreaming for hns3 pmd and modifications + are as follow: + - dma/hisilicon: remove support for HIP09 platform + - net/hns3: disable SCTP verification tag for RSS hash input + - net/hns3: fix variable overflow + - net/hns3: fix double free for Rx/Tx queue + - net/hns3: fix read Rx timestamp handle + - net/hns3: fix offload flag of IEEE 1588 + In addition, the following patch synchronizes the latest version + - ethdev: fix strict aliasing lead to link cannot be up + * Thu May 09 2024 jiangheng - 23.11-16 - require at least two segs per memseg lists in map-perfect mode -- Gitee