diff --git a/0487-net-hns3-support-more-VLAN-fields-matching.patch b/0487-net-hns3-support-more-VLAN-fields-matching.patch new file mode 100644 index 0000000000000000000000000000000000000000..947dcdad70a8cbeed6896cfd6350691c8cf248c3 --- /dev/null +++ b/0487-net-hns3-support-more-VLAN-fields-matching.patch @@ -0,0 +1,213 @@ +From 9a053b129ac59150886e1ace0dd991c6715af745 Mon Sep 17 00:00:00 2001 +From: Jie Hai +Date: Thu, 4 Jul 2024 10:15:38 +0800 +Subject: [PATCH 487/500] net/hns3: support more VLAN fields matching + +[ upstream commit 051d4bc943ff37bd9310bb76d8b0b9dad77fa14b ] + +The commit 09315fc83861 ("ethdev: add VLAN attributes to ethernet +and VLAN items") introduces ``has_vlan`` and ``has_more_vlan`` +fields in items ETH and VLAN. This patch adds support for these +fields. The usage is documented in hns3.rst. + +Signed-off-by: Jie Hai +Signed-off-by: chenyi +--- + doc/guides/nics/hns3.rst | 68 ++++++++++++++++++++++++++++++++++++ + drivers/net/hns3/hns3_fdir.h | 4 +++ + drivers/net/hns3/hns3_flow.c | 47 ++++++++++++++++++++++--- + 3 files changed, 115 insertions(+), 4 deletions(-) + +diff --git a/doc/guides/nics/hns3.rst b/doc/guides/nics/hns3.rst +index ebe3f7f7dd..f53493cfdc 100644 +--- a/doc/guides/nics/hns3.rst ++++ b/doc/guides/nics/hns3.rst +@@ -234,6 +234,74 @@ src_port=32, dst_port=32`` to queue 1: + dst is 2.2.2.5 / udp src is 32 dst is 32 / end \ + actions mark id 1 / queue index 1 / end + ++The flow rules:: ++ ++ rule-0: flow create 0 ingress pattern eth / end \ ++ queue index 1 / end ++ rule-1: flow create 0 ingress pattern eth / vlan vid is 10 / end \ ++ queue index 1 / end ++ rule-2: flow create 0 ingress pattern eth / vlan / vlan vid is 10 / end \ ++ queue index 1 / end ++ rule-3: flow create 0 ingress pattern eth / vlan vid is 10 / vlan vid is 11 / end \ ++ queue index 1 / end ++ ++will match the following packet types with specific VLAN ID at the specified VLAN layer ++and any VLAN ID at the rest VLAN layer. ++ ++ +--------+------------------+-------------------------------------------+ ++ | rules | ``strict`` | ``nostrict`` | ++ +========+==================+===========================================+ ++ | rule-0 | untagged | untagged || single-tagged || multi-tagged | ++ +--------+------------------+-------------------------------------------+ ++ | rule-1 | single-tagged | single-tagged || multi-tagged | ++ +--------+------------------+-------------------------------------------+ ++ | rule-2 | double-tagged | multi-tagged | ++ +--------+------------------+-------------------------------------------+ ++ | rule-3 | double-tagged | multi-tagged | ++ +--------+------------------+-------------------------------------------+ ++ ++The attributes ``has_vlan`` and ``has_more_vlan`` are supported. ++The usage is as follows:: ++ ++ rule-4: flow create 0 ingress pattern eth has_vlan is 1 / end \ ++ queue index 1 / end ++ rule-5: flow create 0 ingress pattern eth has_vlan is 0 / end \ ++ queue index 1 / end ++ rule-6: flow create 0 ingress pattern eth / vlan has_more_vlan is 1 / \ ++ end queue index 1 / end ++ rule-7: flow create 0 ingress pattern eth / vlan has_more_vlan is 0 / \ ++ end queue index 1 / end ++ ++They will match the following packet types with any VLAN ID. ++ ++ +--------+------------------+-------------------------------------------+ ++ | rules | ``strict`` | ``nostrict`` | ++ +========+==================+===========================================+ ++ | rule-4 | single-tagged | untagged || single-tagged || multi-tagged | ++ +--------+------------------+-------------------------------------------+ ++ | rule-5 | untagged | untagged || single-tagged || multi-tagged | ++ +--------+------------------+-------------------------------------------+ ++ | rule-6 | double-tagged | untagged || single-tagged || multi-tagged | ++ +--------+------------------+-------------------------------------------+ ++ | rule-7 | single-tagged | untagged || single-tagged || multi-tagged | ++ +--------+------------------+-------------------------------------------+ ++ ++These two fields may be used followed by VLAN item, ++and may partially overlap or conflict with the VLAN item. ++For examples, the rule-8 will be rejected by the driver ++and rule-9, rule-10 are repeated with rule-4. ++Similar usage for ``has_more_vlan``. ++ ++:: ++ ++ rule-8: flow create 0 ingress pattern eth has_vlan is 0 / vlan / end \ ++ queue index 1 / end ++ rule-9: flow create 0 ingress pattern eth has_vlan is 1 / vlan / end \ ++ queue index 1 / end ++ rule-10: flow create 0 ingress pattern eth / vlan / end \ ++ queue index 1 / end ++ ++ + Generic flow API + ~~~~~~~~~~~~~~~~ + +diff --git a/drivers/net/hns3/hns3_fdir.h b/drivers/net/hns3/hns3_fdir.h +index 308cfbe56f..6ccd90a253 100644 +--- a/drivers/net/hns3/hns3_fdir.h ++++ b/drivers/net/hns3/hns3_fdir.h +@@ -160,6 +160,10 @@ struct hns3_fdir_rule { + uint16_t nb_queues; + uint16_t location; + struct rte_flow_action_count act_cnt; ++ bool has_vlan_m; ++ bool has_vlan_v; ++ bool has_more_vlan_m; ++ bool has_more_vlan_v; + }; + + /* FDIR filter list structure */ +diff --git a/drivers/net/hns3/hns3_flow.c b/drivers/net/hns3/hns3_flow.c +index da17fa6e69..31fc74ff78 100644 +--- a/drivers/net/hns3/hns3_flow.c ++++ b/drivers/net/hns3/hns3_flow.c +@@ -616,8 +616,8 @@ hns3_parse_eth(const struct rte_flow_item *item, struct hns3_fdir_rule *rule, + if (item->spec == NULL && item->mask == NULL) + return 0; + +- if (item->mask) { +- eth_mask = item->mask; ++ eth_mask = item->mask; ++ if (eth_mask) { + if (eth_mask->type) { + hns3_set_bit(rule->input_set, INNER_ETH_TYPE, 1); + rule->key_conf.mask.ether_type = +@@ -633,9 +633,16 @@ hns3_parse_eth(const struct rte_flow_item *item, struct hns3_fdir_rule *rule, + memcpy(rule->key_conf.mask.dst_mac, + eth_mask->dst.addr_bytes, RTE_ETHER_ADDR_LEN); + } ++ if (eth_mask->has_vlan) ++ rule->has_vlan_m = true; + } + + eth_spec = item->spec; ++ if (eth_mask && eth_mask->has_vlan && eth_spec->has_vlan) { ++ rule->key_conf.vlan_num++; ++ rule->has_vlan_v = true; ++ } ++ + rule->key_conf.spec.ether_type = rte_be_to_cpu_16(eth_spec->type); + memcpy(rule->key_conf.spec.src_mac, eth_spec->src.addr_bytes, + RTE_ETHER_ADDR_LEN); +@@ -651,6 +658,26 @@ hns3_parse_vlan(const struct rte_flow_item *item, struct hns3_fdir_rule *rule, + const struct rte_flow_item_vlan *vlan_spec; + const struct rte_flow_item_vlan *vlan_mask; + ++ if (rule->has_vlan_m && !rule->has_vlan_v) ++ return rte_flow_error_set(error, EINVAL, ++ RTE_FLOW_ERROR_TYPE_ITEM, item, ++ "VLAN item is conflict with 'has_vlan is 0' in ETH item"); ++ ++ if (rule->has_more_vlan_m && !rule->has_more_vlan_v) ++ return rte_flow_error_set(error, EINVAL, ++ RTE_FLOW_ERROR_TYPE_ITEM, item, ++ "VLAN item is conflict with 'has_more_vlan is 0' in the previous VLAN item"); ++ ++ if (rule->has_vlan_m && rule->has_vlan_v) { ++ rule->has_vlan_m = false; ++ rule->key_conf.vlan_num--; ++ } ++ ++ if (rule->has_more_vlan_m && rule->has_more_vlan_v) { ++ rule->has_more_vlan_m = false; ++ rule->key_conf.vlan_num--; ++ } ++ + rule->key_conf.vlan_num++; + if (rule->key_conf.vlan_num > VLAN_TAG_NUM_MAX) + return rte_flow_error_set(error, EINVAL, +@@ -661,8 +688,8 @@ hns3_parse_vlan(const struct rte_flow_item *item, struct hns3_fdir_rule *rule, + if (item->spec == NULL && item->mask == NULL) + return 0; + +- if (item->mask) { +- vlan_mask = item->mask; ++ vlan_mask = item->mask; ++ if (vlan_mask) { + if (vlan_mask->tci) { + if (rule->key_conf.vlan_num == 1) { + hns3_set_bit(rule->input_set, INNER_VLAN_TAG1, +@@ -676,6 +703,8 @@ hns3_parse_vlan(const struct rte_flow_item *item, struct hns3_fdir_rule *rule, + rte_be_to_cpu_16(vlan_mask->tci); + } + } ++ if (vlan_mask->has_more_vlan) ++ rule->has_more_vlan_m = true; + } + + vlan_spec = item->spec; +@@ -685,6 +714,16 @@ hns3_parse_vlan(const struct rte_flow_item *item, struct hns3_fdir_rule *rule, + else + rule->key_conf.spec.vlan_tag2 = + rte_be_to_cpu_16(vlan_spec->tci); ++ ++ if (vlan_mask && vlan_mask->has_more_vlan && vlan_spec->has_more_vlan) { ++ rule->key_conf.vlan_num++; ++ if (rule->key_conf.vlan_num > VLAN_TAG_NUM_MAX) ++ return rte_flow_error_set(error, EINVAL, ++ RTE_FLOW_ERROR_TYPE_ITEM, item, ++ "Vlan_num is more than 2"); ++ rule->has_more_vlan_v = true; ++ } ++ + return 0; + } + +-- +2.33.0 + diff --git a/0488-net-hns3-dump-queue-head-and-tail-pointer-info.patch b/0488-net-hns3-dump-queue-head-and-tail-pointer-info.patch new file mode 100644 index 0000000000000000000000000000000000000000..4e50210a0fce93bf45ee601414e85eb581fdcd89 --- /dev/null +++ b/0488-net-hns3-dump-queue-head-and-tail-pointer-info.patch @@ -0,0 +1,105 @@ +From cd042d56470d1e8838af0dc2baa6e5d0438b307c Mon Sep 17 00:00:00 2001 +From: Dengdui Huang +Date: Thu, 5 Sep 2024 14:48:03 +0800 +Subject: [PATCH 488/500] net/hns3: dump queue head and tail pointer info + +[ upstream commit 364a31b7628536ad7c5fb68603e11c5b166df248 ] + +Add dump the head and tail pointer of RxTx queue. +-- Rx queue head and tail info: + qid sw_head sw_hold hw_head hw_tail + 0 288 32 256 320 + 1 248 56 192 280 + 2 264 72 192 296 + 3 256 64 192 292 +-- Tx queue head and tail info: + qid sw_head sw_tail hw_head hw_tail + 0 0 92 84 92 + 1 32 131 128 139 + 2 32 128 120 128 + 3 96 184 176 184 + +Signed-off-by: Dengdui Huang +Signed-off-by: chenyi +--- + drivers/net/hns3/hns3_dump.c | 57 ++++++++++++++++++++++++++++++++++++ + 1 file changed, 57 insertions(+) + +diff --git a/drivers/net/hns3/hns3_dump.c b/drivers/net/hns3/hns3_dump.c +index 8d4c4d0a3b..49e1ec845b 100644 +--- a/drivers/net/hns3/hns3_dump.c ++++ b/drivers/net/hns3/hns3_dump.c +@@ -436,6 +436,62 @@ hns3_get_rxtx_queue_enable_state(FILE *file, struct rte_eth_dev *dev) + rte_free(tx_queue_state); + } + ++static void ++hns3_get_rxtx_queue_head_tail_pointer(FILE *file, struct rte_eth_dev *dev) ++{ ++ struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); ++ uint32_t reg_offset, queue_id; ++ void **rx_queues, **tx_queues; ++ struct hns3_rx_queue *rxq; ++ struct hns3_tx_queue *txq; ++ uint16_t sw_hold; ++ ++ rx_queues = dev->data->rx_queues; ++ if (rx_queues == NULL) ++ return; ++ tx_queues = dev->data->tx_queues; ++ if (tx_queues == NULL) ++ return; ++ ++ fprintf(file, "\t -- Rx queue head and tail info:\n"); ++ fprintf(file, "\t qid sw_head sw_hold hw_head hw_tail\n"); ++ for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) { ++ if (rx_queues[queue_id] == NULL) ++ continue; ++ rxq = (struct hns3_rx_queue *)rx_queues[queue_id]; ++ if (rxq->rx_deferred_start) ++ continue; ++ ++ if (dev->rx_pkt_burst == hns3_recv_pkts_vec || ++ dev->rx_pkt_burst == hns3_recv_pkts_vec_sve) ++ sw_hold = rxq->rx_rearm_nb; ++ else ++ sw_hold = rxq->rx_free_hold; ++ ++ reg_offset = hns3_get_tqp_reg_offset(queue_id); ++ fprintf(file, "\t %-5u%-9u%-9u%-9u%u\n", queue_id, ++ rxq->next_to_use, sw_hold, ++ hns3_read_dev(hw, HNS3_RING_RX_HEAD_REG + reg_offset), ++ hns3_read_dev(hw, HNS3_RING_RX_TAIL_REG + reg_offset)); ++ } ++ ++ fprintf(file, "\t -- Tx queue head and tail info:\n"); ++ fprintf(file, "\t qid sw_head sw_tail hw_head hw_tail\n"); ++ for (queue_id = 0; queue_id < dev->data->nb_tx_queues; queue_id++) { ++ if (tx_queues[queue_id] == NULL) ++ continue; ++ txq = (struct hns3_tx_queue *)tx_queues[queue_id]; ++ if (txq->tx_deferred_start) ++ continue; ++ ++ reg_offset = hns3_get_tqp_reg_offset(queue_id); ++ fprintf(file, "\t %-5u%-9u%-9u%-9u%u\n", queue_id, ++ txq->next_to_clean, txq->next_to_use, ++ hns3_read_dev(hw, HNS3_RING_TX_HEAD_REG + reg_offset), ++ hns3_read_dev(hw, HNS3_RING_TX_TAIL_REG + reg_offset)); ++ } ++} ++ + static void + hns3_get_rxtx_queue_info(FILE *file, struct rte_eth_dev *dev) + { +@@ -460,6 +516,7 @@ hns3_get_rxtx_queue_info(FILE *file, struct rte_eth_dev *dev) + + hns3_get_rxtx_fake_queue_info(file, dev); + hns3_get_rxtx_queue_enable_state(file, dev); ++ hns3_get_rxtx_queue_head_tail_pointer(file, dev); + } + + static int +-- +2.33.0 + diff --git a/0489-net-hns3-remove-some-basic-address-dump.patch b/0489-net-hns3-remove-some-basic-address-dump.patch new file mode 100644 index 0000000000000000000000000000000000000000..83554d980aa3c3ce2e4a46b7260f3a988827d9a8 --- /dev/null +++ b/0489-net-hns3-remove-some-basic-address-dump.patch @@ -0,0 +1,62 @@ +From a7b1796566f039374d949e4c141e19dd7f877cc8 Mon Sep 17 00:00:00 2001 +From: Jie Hai +Date: Thu, 26 Sep 2024 20:42:44 +0800 +Subject: [PATCH 489/500] net/hns3: remove some basic address dump + +[ upstream commit c8b7bec0ef23f53303c9cf03cfea44f1eb208738 ] + +For security reasons, some address registers are not suitable +to be exposed, remove them. + +Cc: stable@dpdk.org + +Signed-off-by: Jie Hai +Acked-by: Huisong Li +Acked-by: Chengwen Feng +Signed-off-by: chenyi +--- + drivers/net/hns3/hns3_regs.c | 12 ++---------- + 1 file changed, 2 insertions(+), 10 deletions(-) + +diff --git a/drivers/net/hns3/hns3_regs.c b/drivers/net/hns3/hns3_regs.c +index be1be6a89c..53d829a4fc 100644 +--- a/drivers/net/hns3/hns3_regs.c ++++ b/drivers/net/hns3/hns3_regs.c +@@ -17,13 +17,9 @@ + + static int hns3_get_dfx_reg_line(struct hns3_hw *hw, uint32_t *lines); + +-static const uint32_t cmdq_reg_addrs[] = {HNS3_CMDQ_TX_ADDR_L_REG, +- HNS3_CMDQ_TX_ADDR_H_REG, +- HNS3_CMDQ_TX_DEPTH_REG, ++static const uint32_t cmdq_reg_addrs[] = {HNS3_CMDQ_TX_DEPTH_REG, + HNS3_CMDQ_TX_TAIL_REG, + HNS3_CMDQ_TX_HEAD_REG, +- HNS3_CMDQ_RX_ADDR_L_REG, +- HNS3_CMDQ_RX_ADDR_H_REG, + HNS3_CMDQ_RX_DEPTH_REG, + HNS3_CMDQ_RX_TAIL_REG, + HNS3_CMDQ_RX_HEAD_REG, +@@ -44,9 +40,7 @@ static const uint32_t common_vf_reg_addrs[] = {HNS3_MISC_VECTOR_REG_BASE, + HNS3_FUN_RST_ING, + HNS3_GRO_EN_REG}; + +-static const uint32_t ring_reg_addrs[] = {HNS3_RING_RX_BASEADDR_L_REG, +- HNS3_RING_RX_BASEADDR_H_REG, +- HNS3_RING_RX_BD_NUM_REG, ++static const uint32_t ring_reg_addrs[] = {HNS3_RING_RX_BD_NUM_REG, + HNS3_RING_RX_BD_LEN_REG, + HNS3_RING_RX_EN_REG, + HNS3_RING_RX_MERGE_EN_REG, +@@ -57,8 +51,6 @@ static const uint32_t ring_reg_addrs[] = {HNS3_RING_RX_BASEADDR_L_REG, + HNS3_RING_RX_FBD_OFFSET_REG, + HNS3_RING_RX_STASH_REG, + HNS3_RING_RX_BD_ERR_REG, +- HNS3_RING_TX_BASEADDR_L_REG, +- HNS3_RING_TX_BASEADDR_H_REG, + HNS3_RING_TX_BD_NUM_REG, + HNS3_RING_TX_EN_REG, + HNS3_RING_TX_PRIORITY_REG, +-- +2.33.0 + diff --git a/0490-net-hns3-fix-dump-counter-of-registers.patch b/0490-net-hns3-fix-dump-counter-of-registers.patch new file mode 100644 index 0000000000000000000000000000000000000000..1e95934d468d1c998b26d8d553ae953fa4a99912 --- /dev/null +++ b/0490-net-hns3-fix-dump-counter-of-registers.patch @@ -0,0 +1,38 @@ +From 6a40770bb32ccec3fa9ba84be126c2c9c5170433 Mon Sep 17 00:00:00 2001 +From: Jie Hai +Date: Thu, 26 Sep 2024 20:42:45 +0800 +Subject: [PATCH 490/500] net/hns3: fix dump counter of registers + +[ upstream commit e9b82b4d54c019973ffcb5f404ba920494f70513 ] + +Since the driver dumps the queue interrupt registers according +to the intr_tqps_num, the counter should be the same. + +Fixes: acb3260fac5c ("net/hns3: fix dump register out of range") +Fixes: 936eda25e8da ("net/hns3: support dump register") +Cc: stable@dpdk.org + +Signed-off-by: Jie Hai +Acked-by: Huisong Li +Acked-by: Chengwen Feng +Signed-off-by: chenyi +--- + drivers/net/hns3/hns3_regs.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/net/hns3/hns3_regs.c b/drivers/net/hns3/hns3_regs.c +index 53d829a4fc..d9c546470d 100644 +--- a/drivers/net/hns3/hns3_regs.c ++++ b/drivers/net/hns3/hns3_regs.c +@@ -127,7 +127,7 @@ hns3_get_regs_length(struct hns3_hw *hw, uint32_t *length) + tqp_intr_lines = sizeof(tqp_intr_reg_addrs) / REG_LEN_PER_LINE + 1; + + len = (cmdq_lines + common_lines + ring_lines * hw->tqps_num + +- tqp_intr_lines * hw->num_msi) * REG_NUM_PER_LINE; ++ tqp_intr_lines * hw->intr_tqps_num) * REG_NUM_PER_LINE; + + if (!hns->is_vf) { + ret = hns3_get_regs_num(hw, ®s_num_32_bit, ®s_num_64_bit); +-- +2.33.0 + diff --git a/0491-net-hns3-remove-separators-between-register-module.patch b/0491-net-hns3-remove-separators-between-register-module.patch new file mode 100644 index 0000000000000000000000000000000000000000..314b82dc8eecbe0ad1d552c1d8e54861bf83325f --- /dev/null +++ b/0491-net-hns3-remove-separators-between-register-module.patch @@ -0,0 +1,206 @@ +From 07b4991b0c92c7ad3174c6fa929d493fa59c9456 Mon Sep 17 00:00:00 2001 +From: Jie Hai +Date: Thu, 26 Sep 2024 20:42:46 +0800 +Subject: [PATCH 491/500] net/hns3: remove separators between register module + +[ upstream commit 7fddd3cac6a3730fc016480418ce693b4a491cb5 ] + +Since the driver is going to support reporting names of +all registers, remove the counter and insert of separators +between different register modules. + +Signed-off-by: Jie Hai +Reviewed-by: Huisong Li +Acked-by: Chengwen Feng +Signed-off-by: chenyi +--- + drivers/net/hns3/hns3_regs.c | 68 ++++++++++-------------------------- + 1 file changed, 18 insertions(+), 50 deletions(-) + +diff --git a/drivers/net/hns3/hns3_regs.c b/drivers/net/hns3/hns3_regs.c +index d9c546470d..c8e3fb118e 100644 +--- a/drivers/net/hns3/hns3_regs.c ++++ b/drivers/net/hns3/hns3_regs.c +@@ -10,12 +10,9 @@ + #include "hns3_rxtx.h" + #include "hns3_regs.h" + +-#define MAX_SEPARATE_NUM 4 +-#define SEPARATOR_VALUE 0xFFFFFFFF +-#define REG_NUM_PER_LINE 4 +-#define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(uint32_t)) ++#define HNS3_64_BIT_REG_OUTPUT_SIZE (sizeof(uint64_t) / sizeof(uint32_t)) + +-static int hns3_get_dfx_reg_line(struct hns3_hw *hw, uint32_t *lines); ++static int hns3_get_dfx_reg_cnt(struct hns3_hw *hw, uint32_t *count); + + static const uint32_t cmdq_reg_addrs[] = {HNS3_CMDQ_TX_DEPTH_REG, + HNS3_CMDQ_TX_TAIL_REG, +@@ -111,23 +108,21 @@ static int + hns3_get_regs_length(struct hns3_hw *hw, uint32_t *length) + { + struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); +- uint32_t cmdq_lines, common_lines, ring_lines, tqp_intr_lines; + uint32_t regs_num_32_bit, regs_num_64_bit; +- uint32_t dfx_reg_lines; ++ uint32_t dfx_reg_cnt; ++ uint32_t common_cnt; + uint32_t len; + int ret; + +- cmdq_lines = sizeof(cmdq_reg_addrs) / REG_LEN_PER_LINE + 1; + if (hns->is_vf) +- common_lines = +- sizeof(common_vf_reg_addrs) / REG_LEN_PER_LINE + 1; ++ common_cnt = sizeof(common_vf_reg_addrs); + else +- common_lines = sizeof(common_reg_addrs) / REG_LEN_PER_LINE + 1; +- ring_lines = sizeof(ring_reg_addrs) / REG_LEN_PER_LINE + 1; +- tqp_intr_lines = sizeof(tqp_intr_reg_addrs) / REG_LEN_PER_LINE + 1; ++ common_cnt = sizeof(common_reg_addrs); + +- len = (cmdq_lines + common_lines + ring_lines * hw->tqps_num + +- tqp_intr_lines * hw->intr_tqps_num) * REG_NUM_PER_LINE; ++ len = sizeof(cmdq_reg_addrs) + common_cnt + ++ sizeof(ring_reg_addrs) * hw->tqps_num + ++ sizeof(tqp_intr_reg_addrs) * hw->intr_tqps_num; ++ len /= sizeof(uint32_t); + + if (!hns->is_vf) { + ret = hns3_get_regs_num(hw, ®s_num_32_bit, ®s_num_64_bit); +@@ -136,18 +131,16 @@ hns3_get_regs_length(struct hns3_hw *hw, uint32_t *length) + "ret = %d.", ret); + return ret; + } +- dfx_reg_lines = regs_num_32_bit * sizeof(uint32_t) / +- REG_LEN_PER_LINE + 1; +- dfx_reg_lines += regs_num_64_bit * sizeof(uint64_t) / +- REG_LEN_PER_LINE + 1; ++ dfx_reg_cnt = regs_num_32_bit + ++ regs_num_64_bit * HNS3_64_BIT_REG_OUTPUT_SIZE; + +- ret = hns3_get_dfx_reg_line(hw, &dfx_reg_lines); ++ ret = hns3_get_dfx_reg_cnt(hw, &dfx_reg_cnt); + if (ret) { + hns3_err(hw, "fail to get the number of dfx registers, " + "ret = %d.", ret); + return ret; + } +- len += dfx_reg_lines * REG_NUM_PER_LINE; ++ len += dfx_reg_cnt; + } + + *length = len; +@@ -268,18 +261,6 @@ hns3_get_64_bit_regs(struct hns3_hw *hw, uint32_t regs_num, void *data) + return 0; + } + +-static int +-hns3_insert_reg_separator(int reg_num, uint32_t *data) +-{ +- int separator_num; +- int i; +- +- separator_num = MAX_SEPARATE_NUM - reg_num % REG_NUM_PER_LINE; +- for (i = 0; i < separator_num; i++) +- *data++ = SEPARATOR_VALUE; +- return separator_num; +-} +- + static int + hns3_direct_access_regs(struct hns3_hw *hw, uint32_t *data) + { +@@ -294,7 +275,6 @@ hns3_direct_access_regs(struct hns3_hw *hw, uint32_t *data) + reg_num = sizeof(cmdq_reg_addrs) / sizeof(uint32_t); + for (i = 0; i < reg_num; i++) + *data++ = hns3_read_dev(hw, cmdq_reg_addrs[i]); +- data += hns3_insert_reg_separator(reg_num, data); + + if (hns->is_vf) + reg_num = sizeof(common_vf_reg_addrs) / sizeof(uint32_t); +@@ -305,7 +285,6 @@ hns3_direct_access_regs(struct hns3_hw *hw, uint32_t *data) + *data++ = hns3_read_dev(hw, common_vf_reg_addrs[i]); + else + *data++ = hns3_read_dev(hw, common_reg_addrs[i]); +- data += hns3_insert_reg_separator(reg_num, data); + + reg_num = sizeof(ring_reg_addrs) / sizeof(uint32_t); + for (j = 0; j < hw->tqps_num; j++) { +@@ -313,7 +292,6 @@ hns3_direct_access_regs(struct hns3_hw *hw, uint32_t *data) + for (i = 0; i < reg_num; i++) + *data++ = hns3_read_dev(hw, + ring_reg_addrs[i] + reg_offset); +- data += hns3_insert_reg_separator(reg_num, data); + } + + reg_num = sizeof(tqp_intr_reg_addrs) / sizeof(uint32_t); +@@ -322,7 +300,6 @@ hns3_direct_access_regs(struct hns3_hw *hw, uint32_t *data) + for (i = 0; i < reg_num; i++) + *data++ = hns3_read_dev(hw, tqp_intr_reg_addrs[i] + + reg_offset); +- data += hns3_insert_reg_separator(reg_num, data); + } + return data - origin_data_ptr; + } +@@ -398,17 +375,15 @@ hns3_dfx_reg_fetch_data(struct hns3_cmd_desc *desc, int bd_num, uint32_t *reg) + index = i % HNS3_CMD_DESC_DATA_NUM; + *reg++ = desc[desc_index].data[index]; + } +- reg_num += hns3_insert_reg_separator(reg_num, reg); + + return reg_num; + } + + static int +-hns3_get_dfx_reg_line(struct hns3_hw *hw, uint32_t *lines) ++hns3_get_dfx_reg_cnt(struct hns3_hw *hw, uint32_t *count) + { + int opcode_num = RTE_DIM(hns3_dfx_reg_opcode_list); + uint32_t bd_num_list[opcode_num]; +- uint32_t bd_num, data_len; + int ret; + int i; + +@@ -416,11 +391,8 @@ hns3_get_dfx_reg_line(struct hns3_hw *hw, uint32_t *lines) + if (ret) + return ret; + +- for (i = 0; i < opcode_num; i++) { +- bd_num = bd_num_list[i]; +- data_len = bd_num * HNS3_CMD_DESC_DATA_NUM * sizeof(uint32_t); +- *lines += data_len / REG_LEN_PER_LINE + 1; +- } ++ for (i = 0; i < opcode_num; i++) ++ *count += bd_num_list[i] * HNS3_CMD_DESC_DATA_NUM; + + return 0; + } +@@ -467,7 +439,6 @@ hns3_get_dfx_regs(struct hns3_hw *hw, void **data) + int + hns3_get_regs(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs) + { +-#define HNS3_64_BIT_REG_SIZE (sizeof(uint64_t) / sizeof(uint32_t)) + struct hns3_adapter *hns = eth_dev->data->dev_private; + struct hns3_hw *hw = &hns->hw; + uint32_t regs_num_32_bit; +@@ -512,16 +483,13 @@ hns3_get_regs(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs) + return ret; + } + data += regs_num_32_bit; +- data += hns3_insert_reg_separator(regs_num_32_bit, data); + + ret = hns3_get_64_bit_regs(hw, regs_num_64_bit, data); + if (ret) { + hns3_err(hw, "Get 64 bit register failed, ret = %d", ret); + return ret; + } +- data += regs_num_64_bit * HNS3_64_BIT_REG_SIZE; +- data += hns3_insert_reg_separator(regs_num_64_bit * +- HNS3_64_BIT_REG_SIZE, data); ++ data += regs_num_64_bit * HNS3_64_BIT_REG_OUTPUT_SIZE; + + return hns3_get_dfx_regs(hw, (void **)&data); + } +-- +2.33.0 + diff --git a/0492-net-hns3-refactor-register-dump.patch b/0492-net-hns3-refactor-register-dump.patch new file mode 100644 index 0000000000000000000000000000000000000000..c7a3caa30d424d07db48270410cede02ef8619be --- /dev/null +++ b/0492-net-hns3-refactor-register-dump.patch @@ -0,0 +1,276 @@ +From 4a04241dc24b9f2d685f100f6be475a5f6cb6473 Mon Sep 17 00:00:00 2001 +From: Jie Hai +Date: Thu, 26 Sep 2024 20:42:47 +0800 +Subject: [PATCH 492/500] net/hns3: refactor register dump + +[ upstream commit 8cdddc252dd5320bbbb1df948bbdd8d19f8fda22 ] + +This patch refactors codes dumping registers from firmware. + +Signed-off-by: Jie Hai +Acked-by: Chengwen Feng +Signed-off-by: chenyi +--- + drivers/net/hns3/hns3_regs.c | 203 ++++++++++++++++++++--------------- + 1 file changed, 115 insertions(+), 88 deletions(-) + +diff --git a/drivers/net/hns3/hns3_regs.c b/drivers/net/hns3/hns3_regs.c +index c8e3fb118e..c7dadbeb3e 100644 +--- a/drivers/net/hns3/hns3_regs.c ++++ b/drivers/net/hns3/hns3_regs.c +@@ -104,12 +104,93 @@ hns3_get_regs_num(struct hns3_hw *hw, uint32_t *regs_num_32_bit, + return 0; + } + ++static int ++hns3_get_32_64_regs_cnt(struct hns3_hw *hw, uint32_t *count) ++{ ++ uint32_t regs_num_32_bit, regs_num_64_bit; ++ int ret; ++ ++ ret = hns3_get_regs_num(hw, ®s_num_32_bit, ®s_num_64_bit); ++ if (ret) { ++ hns3_err(hw, "fail to get the number of registers, " ++ "ret = %d.", ret); ++ return ret; ++ } ++ ++ *count += regs_num_32_bit + regs_num_64_bit * HNS3_64_BIT_REG_OUTPUT_SIZE; ++ return 0; ++} ++ ++static int ++hns3_get_dfx_reg_bd_num(struct hns3_hw *hw, uint32_t *bd_num_list, ++ uint32_t list_size) ++{ ++#define HNS3_GET_DFX_REG_BD_NUM_SIZE 4 ++ struct hns3_cmd_desc desc[HNS3_GET_DFX_REG_BD_NUM_SIZE]; ++ uint32_t index, desc_index; ++ uint32_t bd_num; ++ uint32_t i; ++ int ret; ++ ++ for (i = 0; i < HNS3_GET_DFX_REG_BD_NUM_SIZE - 1; i++) { ++ hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_DFX_BD_NUM, true); ++ desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); ++ } ++ /* The last BD does not need a next flag */ ++ hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_DFX_BD_NUM, true); ++ ++ ret = hns3_cmd_send(hw, desc, HNS3_GET_DFX_REG_BD_NUM_SIZE); ++ if (ret) { ++ hns3_err(hw, "fail to get dfx bd num, ret = %d.", ret); ++ return ret; ++ } ++ ++ /* The first data in the first BD is a reserved field */ ++ for (i = 1; i <= list_size; i++) { ++ desc_index = i / HNS3_CMD_DESC_DATA_NUM; ++ index = i % HNS3_CMD_DESC_DATA_NUM; ++ bd_num = rte_le_to_cpu_32(desc[desc_index].data[index]); ++ bd_num_list[i - 1] = bd_num; ++ } ++ ++ return 0; ++} ++ ++static int ++hns3_get_dfx_reg_cnt(struct hns3_hw *hw, uint32_t *count) ++{ ++ int opcode_num = RTE_DIM(hns3_dfx_reg_opcode_list); ++ uint32_t bd_num_list[opcode_num]; ++ int ret; ++ int i; ++ ++ ret = hns3_get_dfx_reg_bd_num(hw, bd_num_list, opcode_num); ++ if (ret) ++ return ret; ++ ++ for (i = 0; i < opcode_num; i++) ++ *count += bd_num_list[i] * HNS3_CMD_DESC_DATA_NUM; ++ ++ return 0; ++} ++ ++static int ++hns3_get_firmware_reg_cnt(struct hns3_hw *hw, uint32_t *count) ++{ ++ int ret; ++ ++ ret = hns3_get_32_64_regs_cnt(hw, count); ++ if (ret < 0) ++ return ret; ++ ++ return hns3_get_dfx_reg_cnt(hw, count); ++} ++ + static int + hns3_get_regs_length(struct hns3_hw *hw, uint32_t *length) + { + struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); +- uint32_t regs_num_32_bit, regs_num_64_bit; +- uint32_t dfx_reg_cnt; ++ uint32_t dfx_reg_cnt = 0; + uint32_t common_cnt; + uint32_t len; + int ret; +@@ -125,16 +206,7 @@ hns3_get_regs_length(struct hns3_hw *hw, uint32_t *length) + len /= sizeof(uint32_t); + + if (!hns->is_vf) { +- ret = hns3_get_regs_num(hw, ®s_num_32_bit, ®s_num_64_bit); +- if (ret) { +- hns3_err(hw, "fail to get the number of registers, " +- "ret = %d.", ret); +- return ret; +- } +- dfx_reg_cnt = regs_num_32_bit + +- regs_num_64_bit * HNS3_64_BIT_REG_OUTPUT_SIZE; +- +- ret = hns3_get_dfx_reg_cnt(hw, &dfx_reg_cnt); ++ ret = hns3_get_firmware_reg_cnt(hw, &dfx_reg_cnt); + if (ret) { + hns3_err(hw, "fail to get the number of dfx registers, " + "ret = %d.", ret); +@@ -304,41 +376,6 @@ hns3_direct_access_regs(struct hns3_hw *hw, uint32_t *data) + return data - origin_data_ptr; + } + +-static int +-hns3_get_dfx_reg_bd_num(struct hns3_hw *hw, uint32_t *bd_num_list, +- uint32_t list_size) +-{ +-#define HNS3_GET_DFX_REG_BD_NUM_SIZE 4 +- struct hns3_cmd_desc desc[HNS3_GET_DFX_REG_BD_NUM_SIZE]; +- uint32_t index, desc_index; +- uint32_t bd_num; +- uint32_t i; +- int ret; +- +- for (i = 0; i < HNS3_GET_DFX_REG_BD_NUM_SIZE - 1; i++) { +- hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_DFX_BD_NUM, true); +- desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); +- } +- /* The last BD does not need a next flag */ +- hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_DFX_BD_NUM, true); +- +- ret = hns3_cmd_send(hw, desc, HNS3_GET_DFX_REG_BD_NUM_SIZE); +- if (ret) { +- hns3_err(hw, "fail to get dfx bd num, ret = %d.\n", ret); +- return ret; +- } +- +- /* The first data in the first BD is a reserved field */ +- for (i = 1; i <= list_size; i++) { +- desc_index = i / HNS3_CMD_DESC_DATA_NUM; +- index = i % HNS3_CMD_DESC_DATA_NUM; +- bd_num = rte_le_to_cpu_32(desc[desc_index].data[index]); +- bd_num_list[i - 1] = bd_num; +- } +- +- return 0; +-} +- + static int + hns3_dfx_reg_cmd_send(struct hns3_hw *hw, struct hns3_cmd_desc *desc, + int bd_num, uint32_t opcode) +@@ -379,24 +416,6 @@ hns3_dfx_reg_fetch_data(struct hns3_cmd_desc *desc, int bd_num, uint32_t *reg) + return reg_num; + } + +-static int +-hns3_get_dfx_reg_cnt(struct hns3_hw *hw, uint32_t *count) +-{ +- int opcode_num = RTE_DIM(hns3_dfx_reg_opcode_list); +- uint32_t bd_num_list[opcode_num]; +- int ret; +- int i; +- +- ret = hns3_get_dfx_reg_bd_num(hw, bd_num_list, opcode_num); +- if (ret) +- return ret; +- +- for (i = 0; i < opcode_num; i++) +- *count += bd_num_list[i] * HNS3_CMD_DESC_DATA_NUM; +- +- return 0; +-} +- + static int + hns3_get_dfx_regs(struct hns3_hw *hw, void **data) + { +@@ -436,13 +455,41 @@ hns3_get_dfx_regs(struct hns3_hw *hw, void **data) + return ret; + } + ++static int ++hns3_get_regs_from_firmware(struct hns3_hw *hw, uint32_t *data) ++{ ++ uint32_t regs_num_32_bit; ++ uint32_t regs_num_64_bit; ++ int ret; ++ ++ ret = hns3_get_regs_num(hw, ®s_num_32_bit, ®s_num_64_bit); ++ if (ret) { ++ hns3_err(hw, "Get register number failed, ret = %d", ret); ++ return ret; ++ } ++ ++ ret = hns3_get_32_bit_regs(hw, regs_num_32_bit, data); ++ if (ret) { ++ hns3_err(hw, "Get 32 bit register failed, ret = %d", ret); ++ return ret; ++ } ++ data += regs_num_32_bit; ++ ++ ret = hns3_get_64_bit_regs(hw, regs_num_64_bit, data); ++ if (ret) { ++ hns3_err(hw, "Get 64 bit register failed, ret = %d", ret); ++ return ret; ++ } ++ data += regs_num_64_bit * HNS3_64_BIT_REG_OUTPUT_SIZE; ++ ++ return hns3_get_dfx_regs(hw, (void **)&data); ++} ++ + int + hns3_get_regs(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs) + { + struct hns3_adapter *hns = eth_dev->data->dev_private; + struct hns3_hw *hw = &hns->hw; +- uint32_t regs_num_32_bit; +- uint32_t regs_num_64_bit; + uint32_t length; + uint32_t *data; + int ret; +@@ -470,26 +517,6 @@ hns3_get_regs(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs) + if (hns->is_vf) + return 0; + +- ret = hns3_get_regs_num(hw, ®s_num_32_bit, ®s_num_64_bit); +- if (ret) { +- hns3_err(hw, "Get register number failed, ret = %d", ret); +- return ret; +- } +- + /* fetching PF common registers values from firmware */ +- ret = hns3_get_32_bit_regs(hw, regs_num_32_bit, data); +- if (ret) { +- hns3_err(hw, "Get 32 bit register failed, ret = %d", ret); +- return ret; +- } +- data += regs_num_32_bit; +- +- ret = hns3_get_64_bit_regs(hw, regs_num_64_bit, data); +- if (ret) { +- hns3_err(hw, "Get 64 bit register failed, ret = %d", ret); +- return ret; +- } +- data += regs_num_64_bit * HNS3_64_BIT_REG_OUTPUT_SIZE; +- +- return hns3_get_dfx_regs(hw, (void **)&data); ++ return hns3_get_regs_from_firmware(hw, data); + } +-- +2.33.0 + diff --git a/0493-net-hns3-support-reporting-names-of-registers.patch b/0493-net-hns3-support-reporting-names-of-registers.patch new file mode 100644 index 0000000000000000000000000000000000000000..4e77a5c94f0b14c8d87bbf4f6d503d36568d2c7e --- /dev/null +++ b/0493-net-hns3-support-reporting-names-of-registers.patch @@ -0,0 +1,1284 @@ +From ee44ef9ea515845f648c04514ea7f03d4a5f6ba7 Mon Sep 17 00:00:00 2001 +From: Jie Hai +Date: Thu, 26 Sep 2024 20:42:48 +0800 +Subject: [PATCH 493/500] net/hns3: support reporting names of registers + +[ upstream commit dd4b8bba785faf9d1bb9c4460e75068e2822bdb3 ] + +This patch adds names for register lists, and support report +names of registers. Some registers has different names on +different platform, use names of HIP08 as default names. + +Signed-off-by: Jie Hai +Acked-by: Chengwen Feng +Signed-off-by: chenyi +--- + drivers/net/hns3/hns3_regs.c | 1088 +++++++++++++++++++++++++++++----- + 1 file changed, 955 insertions(+), 133 deletions(-) + +diff --git a/drivers/net/hns3/hns3_regs.c b/drivers/net/hns3/hns3_regs.c +index c7dadbeb3e..22151dde9a 100644 +--- a/drivers/net/hns3/hns3_regs.c ++++ b/drivers/net/hns3/hns3_regs.c +@@ -14,73 +14,827 @@ + + static int hns3_get_dfx_reg_cnt(struct hns3_hw *hw, uint32_t *count); + +-static const uint32_t cmdq_reg_addrs[] = {HNS3_CMDQ_TX_DEPTH_REG, +- HNS3_CMDQ_TX_TAIL_REG, +- HNS3_CMDQ_TX_HEAD_REG, +- HNS3_CMDQ_RX_DEPTH_REG, +- HNS3_CMDQ_RX_TAIL_REG, +- HNS3_CMDQ_RX_HEAD_REG, +- HNS3_VECTOR0_CMDQ_SRC_REG, +- HNS3_CMDQ_INTR_STS_REG, +- HNS3_CMDQ_INTR_EN_REG, +- HNS3_CMDQ_INTR_GEN_REG}; +- +-static const uint32_t common_reg_addrs[] = {HNS3_MISC_VECTOR_REG_BASE, +- HNS3_VECTOR0_OTER_EN_REG, +- HNS3_MISC_RESET_STS_REG, +- HNS3_VECTOR0_OTHER_INT_STS_REG, +- HNS3_GLOBAL_RESET_REG, +- HNS3_FUN_RST_ING, +- HNS3_GRO_EN_REG}; +- +-static const uint32_t common_vf_reg_addrs[] = {HNS3_MISC_VECTOR_REG_BASE, +- HNS3_FUN_RST_ING, +- HNS3_GRO_EN_REG}; +- +-static const uint32_t ring_reg_addrs[] = {HNS3_RING_RX_BD_NUM_REG, +- HNS3_RING_RX_BD_LEN_REG, +- HNS3_RING_RX_EN_REG, +- HNS3_RING_RX_MERGE_EN_REG, +- HNS3_RING_RX_TAIL_REG, +- HNS3_RING_RX_HEAD_REG, +- HNS3_RING_RX_FBDNUM_REG, +- HNS3_RING_RX_OFFSET_REG, +- HNS3_RING_RX_FBD_OFFSET_REG, +- HNS3_RING_RX_STASH_REG, +- HNS3_RING_RX_BD_ERR_REG, +- HNS3_RING_TX_BD_NUM_REG, +- HNS3_RING_TX_EN_REG, +- HNS3_RING_TX_PRIORITY_REG, +- HNS3_RING_TX_TC_REG, +- HNS3_RING_TX_MERGE_EN_REG, +- HNS3_RING_TX_TAIL_REG, +- HNS3_RING_TX_HEAD_REG, +- HNS3_RING_TX_FBDNUM_REG, +- HNS3_RING_TX_OFFSET_REG, +- HNS3_RING_TX_EBD_NUM_REG, +- HNS3_RING_TX_EBD_OFFSET_REG, +- HNS3_RING_TX_BD_ERR_REG, +- HNS3_RING_EN_REG}; +- +-static const uint32_t tqp_intr_reg_addrs[] = {HNS3_TQP_INTR_CTRL_REG, +- HNS3_TQP_INTR_GL0_REG, +- HNS3_TQP_INTR_GL1_REG, +- HNS3_TQP_INTR_GL2_REG, +- HNS3_TQP_INTR_RL_REG}; ++struct hns3_dirt_reg_entry { ++ const char *name; ++ uint32_t addr; ++}; ++ ++static const struct hns3_dirt_reg_entry cmdq_reg_list[] = { ++ {"cmdq_tx_depth", HNS3_CMDQ_TX_DEPTH_REG}, ++ {"cmdq_tx_tail", HNS3_CMDQ_TX_TAIL_REG}, ++ {"cmdq_tx_head", HNS3_CMDQ_TX_HEAD_REG}, ++ {"cmdq_rx_depth", HNS3_CMDQ_RX_DEPTH_REG}, ++ {"cmdq_rx_tail", HNS3_CMDQ_RX_TAIL_REG}, ++ {"cmdq_rx_head", HNS3_CMDQ_RX_HEAD_REG}, ++ {"vector0_cmdq_src", HNS3_VECTOR0_CMDQ_SRC_REG}, ++ {"cmdq_intr_sts", HNS3_CMDQ_INTR_STS_REG}, ++ {"cmdq_intr_en", HNS3_CMDQ_INTR_EN_REG}, ++ {"cmdq_intr_gen", HNS3_CMDQ_INTR_GEN_REG}, ++}; ++ ++static const struct hns3_dirt_reg_entry common_reg_list[] = { ++ {"misc_vector_reg_base", HNS3_MISC_VECTOR_REG_BASE}, ++ {"vector0_oter_en", HNS3_VECTOR0_OTER_EN_REG}, ++ {"misc_reset_sts", HNS3_MISC_RESET_STS_REG}, ++ {"vector0_other_int_sts", HNS3_VECTOR0_OTHER_INT_STS_REG}, ++ {"global_reset", HNS3_GLOBAL_RESET_REG}, ++ {"fun_rst_ing", HNS3_FUN_RST_ING}, ++ {"gro_en", HNS3_GRO_EN_REG}, ++}; ++ ++static const struct hns3_dirt_reg_entry common_vf_reg_list[] = { ++ {"misc_vector_reg_base", HNS3_MISC_VECTOR_REG_BASE}, ++ {"fun_rst_ing", HNS3_FUN_RST_ING}, ++ {"gro_en", HNS3_GRO_EN_REG}, ++}; ++ ++static const struct hns3_dirt_reg_entry ring_reg_list[] = { ++ {"ring_rx_bd_num", HNS3_RING_RX_BD_NUM_REG}, ++ {"ring_rx_bd_len", HNS3_RING_RX_BD_LEN_REG}, ++ {"ring_rx_en", HNS3_RING_RX_EN_REG}, ++ {"ring_rx_merge_en", HNS3_RING_RX_MERGE_EN_REG}, ++ {"ring_rx_tail", HNS3_RING_RX_TAIL_REG}, ++ {"ring_rx_head", HNS3_RING_RX_HEAD_REG}, ++ {"ring_rx_fbdnum", HNS3_RING_RX_FBDNUM_REG}, ++ {"ring_rx_offset", HNS3_RING_RX_OFFSET_REG}, ++ {"ring_rx_fbd_offset", HNS3_RING_RX_FBD_OFFSET_REG}, ++ {"ring_rx_stash", HNS3_RING_RX_STASH_REG}, ++ {"ring_rx_bd_err", HNS3_RING_RX_BD_ERR_REG}, ++ {"ring_tx_bd_num", HNS3_RING_TX_BD_NUM_REG}, ++ {"ring_tx_en", HNS3_RING_TX_EN_REG}, ++ {"ring_tx_priority", HNS3_RING_TX_PRIORITY_REG}, ++ {"ring_tx_tc", HNS3_RING_TX_TC_REG}, ++ {"ring_tx_merge_en", HNS3_RING_TX_MERGE_EN_REG}, ++ {"ring_tx_tail", HNS3_RING_TX_TAIL_REG}, ++ {"ring_tx_head", HNS3_RING_TX_HEAD_REG}, ++ {"ring_tx_fbdnum", HNS3_RING_TX_FBDNUM_REG}, ++ {"ring_tx_offset", HNS3_RING_TX_OFFSET_REG}, ++ {"ring_tx_ebd_num", HNS3_RING_TX_EBD_NUM_REG}, ++ {"ring_tx_ebd_offset", HNS3_RING_TX_EBD_OFFSET_REG}, ++ {"ring_tx_bd_err", HNS3_RING_TX_BD_ERR_REG}, ++ {"ring_en", HNS3_RING_EN_REG}, ++}; ++ ++static const struct hns3_dirt_reg_entry tqp_intr_reg_list[] = { ++ {"tqp_intr_ctrl", HNS3_TQP_INTR_CTRL_REG}, ++ {"tqp_intr_gl0", HNS3_TQP_INTR_GL0_REG}, ++ {"tqp_intr_gl1", HNS3_TQP_INTR_GL1_REG}, ++ {"tqp_intr_gl2", HNS3_TQP_INTR_GL2_REG}, ++ {"tqp_intr_rl", HNS3_TQP_INTR_RL_REG}, ++}; ++ ++struct hns3_dfx_reg_entry { ++ /** ++ * name_v1 -- default register name for all platforms (HIP08/HIP09/newer). ++ * name_v2 -- register name different from the default for HIP09. ++ * If there are more platform with different register name, name_vXX is extended. ++ * If the platform is newer than HIP09, use default name. ++ */ ++ const char *name_v1; ++ const char *name_v2; ++}; ++ ++static struct hns3_dfx_reg_entry regs_32_bit_list[] = { ++ {"ssu_common_err_int"}, ++ {"ssu_port_based_err_int"}, ++ {"ssu_fifo_overflow_int"}, ++ {"ssu_ets_tcg_int"}, ++ {"ssu_bp_status_0"}, ++ {"ssu_bp_status_1"}, ++ ++ {"ssu_bp_status_2"}, ++ {"ssu_bp_status_3"}, ++ {"ssu_bp_status_4"}, ++ {"ssu_bp_status_5"}, ++ {"ssu_mac_tx_pfc_ind"}, ++ {"ssu_mac_rx_pfc_ind"}, ++ ++ {"ssu_rx_oq_drop_pkt_cnt"}, ++ {"ssu_tx_oq_drop_pkt_cnt"}, ++}; ++ ++static struct hns3_dfx_reg_entry regs_64_bit_list[] = { ++ {"ppp_get_rx_pkt_cnt_l"}, ++ {"ppp_get_rx_pkt_cnt_h"}, ++ {"ppp_get_tx_pkt_cnt_l"}, ++ {"ppp_get_tx_pkt_cnt_h"}, ++ {"ppp_send_uc_prt2host_pkt_cnt_l"}, ++ {"ppp_send_uc_prt2host_pkt_cnt_h"}, ++ ++ {"ppp_send_uc_prt2prt_pkt_cnt_l"}, ++ {"ppp_send_uc_prt2prt_pkt_cnt_h"}, ++ {"ppp_send_uc_host2host_pkt_cnt_l"}, ++ {"ppp_send_uc_host2host_pkt_cnt_h"}, ++ {"ppp_send_uc_host2prt_pkt_cnt_l"}, ++ {"ppp_send_uc_host2prt_pkt_cnt_h"}, ++ {"ppp_send_mc_from_prt_cnt_l"}, ++ {"ppp_send_mc_from_prt_cnt_h"}, ++}; ++ ++static struct hns3_dfx_reg_entry dfx_bios_common_reg_list[] = { ++ {"bios_rsv0"}, ++ {"bp_cpu_state"}, ++ {"dfx_msix_info_nic_0"}, ++ {"dfx_msix_info_nic_1"}, ++ {"dfx_msix_info_nic_2"}, ++ {"dfx_msix_info_nic_3"}, ++ ++ {"dfx_msix_info_roce_0"}, ++ {"dfx_msix_info_roce_1"}, ++ {"dfx_msix_info_roce_2"}, ++ {"dfx_msix_info_roce_3"}, ++ {"bios_rsv1"}, ++ {"bios_rsv2"}, ++}; ++ ++static struct hns3_dfx_reg_entry dfx_ssu_reg_0_list[] = { ++ {"dfx_ssu0_rsv0"}, ++ {"ssu_ets_port_status"}, ++ {"ssu_ets_tcg_status"}, ++ {"dfx_ssu0_rsv1"}, ++ {"dfx_ssu0_rsv2"}, ++ {"ssu_bp_status_0"}, ++ ++ {"ssu_bp_status_1"}, ++ {"ssu_bp_status_2"}, ++ {"ssu_bp_status_3"}, ++ {"ssu_bp_status_4"}, ++ {"ssu_bp_status_5"}, ++ {"ssu_mac_tx_pfc_ind"}, ++ ++ {"mac_ssu_rx_pfc_ind"}, ++ {"btmp_ageing_st_b0"}, ++ {"btmp_ageing_st_b1"}, ++ {"btmp_ageing_st_b2"}, ++ {"dfx_ssu0_rsv3"}, ++ {"dfx_ssu0_rsv4"}, ++ ++ {"ssu_full_drop_num"}, ++ {"ssu_part_drop_num"}, ++ {"ppp_key_drop_num"}, ++ {"ppp_rlt_drop_num"}, ++ {"lo_pri_unicast_rlt_drop_num"}, ++ {"hi_pri_multicast_rlt_drop_num"}, ++ ++ {"lo_pri_multicast_rlt_drop_num"}, ++ {"ncsi_packet_curr_buffer_cnt"}, ++ {"btmp_ageing_rls_cnt_bank0", "dfx_ssu0_rsv5"}, ++ {"btmp_ageing_rls_cnt_bank1", "dfx_ssu0_rsv6"}, ++ {"btmp_ageing_rls_cnt_bank2", "dfx_ssu0_rsv7"}, ++ {"ssu_mb_rd_rlt_drop_cnt"}, ++ ++ {"ssu_ppp_mac_key_num_l"}, ++ {"ssu_ppp_mac_key_num_h"}, ++ {"ssu_ppp_host_key_num_l"}, ++ {"ssu_ppp_host_key_num_h"}, ++ {"ppp_ssu_mac_rlt_num_l"}, ++ {"ppp_ssu_mac_rlt_num_h"}, ++ ++ {"ppp_ssu_host_rlt_num_l"}, ++ {"ppp_ssu_host_rlt_num_h"}, ++ {"ncsi_rx_packet_in_cnt_l"}, ++ {"ncsi_rx_packet_in_cnt_h"}, ++ {"ncsi_tx_packet_out_cnt_l"}, ++ {"ncsi_tx_packet_out_cnt_h"}, ++ ++ {"ssu_key_drop_num"}, ++ {"mb_uncopy_num"}, ++ {"rx_oq_drop_pkt_cnt"}, ++ {"tx_oq_drop_pkt_cnt"}, ++ {"bank_unbalance_drop_cnt"}, ++ {"bank_unbalance_rx_drop_cnt"}, ++ ++ {"nic_l2_eer_drop_pkt_cnt"}, ++ {"roc_l2_eer_drop_pkt_cnt"}, ++ {"nic_l2_eer_drop_pkt_cnt_rx"}, ++ {"roc_l2_eer_drop_pkt_cnt_rx"}, ++ {"rx_oq_glb_drop_pkt_cnt"}, ++ {"dfx_ssu0_rsv8"}, ++ ++ {"lo_pri_unicast_cur_cnt"}, ++ {"hi_pri_multicast_cur_cnt"}, ++ {"lo_pri_multicast_cur_cnt"}, ++ {"dfx_ssu0_rsv9"}, ++ {"dfx_ssu0_rsv10"}, ++ {"dfx_ssu0_rsv11"}, ++}; ++ ++static struct hns3_dfx_reg_entry dfx_ssu_reg_1_list[] = { ++ {"dfx_ssu1_prt_id"}, ++ {"packet_tc_curr_buffer_cnt_0"}, ++ {"packet_tc_curr_buffer_cnt_1"}, ++ {"packet_tc_curr_buffer_cnt_2"}, ++ {"packet_tc_curr_buffer_cnt_3"}, ++ {"packet_tc_curr_buffer_cnt_4"}, ++ ++ {"packet_tc_curr_buffer_cnt_5"}, ++ {"packet_tc_curr_buffer_cnt_6"}, ++ {"packet_tc_curr_buffer_cnt_7"}, ++ {"packet_curr_buffer_cnt"}, ++ {"dfx_ssu1_rsv0"}, ++ {"dfx_ssu1_rsv1"}, ++ ++ {"rx_packet_in_cnt_l"}, ++ {"rx_packet_in_cnt_h"}, ++ {"rx_packet_out_cnt_l"}, ++ {"rx_packet_out_cnt_h"}, ++ {"tx_packet_in_cnt_l"}, ++ {"tx_packet_in_cnt_h"}, ++ ++ {"tx_packet_out_cnt_l"}, ++ {"tx_packet_out_cnt_h"}, ++ {"roc_rx_packet_in_cnt_l"}, ++ {"roc_rx_packet_in_cnt_h"}, ++ {"roc_tx_packet_in_cnt_l"}, ++ {"roc_tx_packet_in_cnt_h"}, ++ ++ {"rx_packet_tc_in_cnt_0_l"}, ++ {"rx_packet_tc_in_cnt_0_h"}, ++ {"rx_packet_tc_in_cnt_1_l"}, ++ {"rx_packet_tc_in_cnt_1_h"}, ++ {"rx_packet_tc_in_cnt_2_l"}, ++ {"rx_packet_tc_in_cnt_2_h"}, ++ ++ {"rx_packet_tc_in_cnt_3_l"}, ++ {"rx_packet_tc_in_cnt_3_h"}, ++ {"rx_packet_tc_in_cnt_4_l"}, ++ {"rx_packet_tc_in_cnt_4_h"}, ++ {"rx_packet_tc_in_cnt_5_l"}, ++ {"rx_packet_tc_in_cnt_5_h"}, ++ ++ {"rx_packet_tc_in_cnt_6_l"}, ++ {"rx_packet_tc_in_cnt_6_h"}, ++ {"rx_packet_tc_in_cnt_7_l"}, ++ {"rx_packet_tc_in_cnt_7_h"}, ++ {"rx_packet_tc_out_cnt_0_l"}, ++ {"rx_packet_tc_out_cnt_0_h"}, ++ ++ {"rx_packet_tc_out_cnt_1_l"}, ++ {"rx_packet_tc_out_cnt_1_h"}, ++ {"rx_packet_tc_out_cnt_2_l"}, ++ {"rx_packet_tc_out_cnt_2_h"}, ++ {"rx_packet_tc_out_cnt_3_l"}, ++ {"rx_packet_tc_out_cnt_3_h"}, ++ ++ {"rx_packet_tc_out_cnt_4_l"}, ++ {"rx_packet_tc_out_cnt_4_h"}, ++ {"rx_packet_tc_out_cnt_5_l"}, ++ {"rx_packet_tc_out_cnt_5_h"}, ++ {"rx_packet_tc_out_cnt_6_l"}, ++ {"rx_packet_tc_out_cnt_6_h"}, ++ ++ {"rx_packet_tc_out_cnt_7_l"}, ++ {"rx_packet_tc_out_cnt_7_h"}, ++ {"tx_packet_tc_in_cnt_0_l"}, ++ {"tx_packet_tc_in_cnt_0_h"}, ++ {"tx_packet_tc_in_cnt_1_l"}, ++ {"tx_packet_tc_in_cnt_1_h"}, ++ ++ {"tx_packet_tc_in_cnt_2_l"}, ++ {"tx_packet_tc_in_cnt_2_h"}, ++ {"tx_packet_tc_in_cnt_3_l"}, ++ {"tx_packet_tc_in_cnt_3_h"}, ++ {"tx_packet_tc_in_cnt_4_l"}, ++ {"tx_packet_tc_in_cnt_4_h"}, ++ ++ {"tx_packet_tc_in_cnt_5_l"}, ++ {"tx_packet_tc_in_cnt_5_h"}, ++ {"tx_packet_tc_in_cnt_6_l"}, ++ {"tx_packet_tc_in_cnt_6_h"}, ++ {"tx_packet_tc_in_cnt_7_l"}, ++ {"tx_packet_tc_in_cnt_7_h"}, ++ ++ {"tx_packet_tc_out_cnt_0_l"}, ++ {"tx_packet_tc_out_cnt_0_h"}, ++ {"tx_packet_tc_out_cnt_1_l"}, ++ {"tx_packet_tc_out_cnt_1_h"}, ++ {"tx_packet_tc_out_cnt_2_l"}, ++ {"tx_packet_tc_out_cnt_2_h"}, ++ ++ {"tx_packet_tc_out_cnt_3_l"}, ++ {"tx_packet_tc_out_cnt_3_h"}, ++ {"tx_packet_tc_out_cnt_4_l"}, ++ {"tx_packet_tc_out_cnt_4_h"}, ++ {"tx_packet_tc_out_cnt_5_l"}, ++ {"tx_packet_tc_out_cnt_5_h"}, ++ ++ {"tx_packet_tc_out_cnt_6_l"}, ++ {"tx_packet_tc_out_cnt_6_h"}, ++ {"tx_packet_tc_out_cnt_7_l"}, ++ {"tx_packet_tc_out_cnt_7_h"}, ++ {"dfx_ssu1_rsv2"}, ++ {"dfx_ssu1_rsv3"}, ++}; ++ ++static struct hns3_dfx_reg_entry dfx_igu_egu_reg_list[] = { ++ {"igu_egu_prt_id"}, ++ {"igu_rx_err_pkt"}, ++ {"igu_rx_no_sof_pkt"}, ++ {"egu_tx_1588_short_pkt"}, ++ {"egu_tx_1588_pkt"}, ++ {"egu_tx_1588_err_pkt"}, ++ ++ {"igu_rx_out_l2_pkt"}, ++ {"igu_rx_out_l3_pkt"}, ++ {"igu_rx_out_l4_pkt"}, ++ {"igu_rx_in_l2_pkt"}, ++ {"igu_rx_in_l3_pkt"}, ++ {"igu_rx_in_l4_pkt"}, ++ ++ {"igu_rx_el3e_pkt"}, ++ {"igu_rx_el4e_pkt"}, ++ {"igu_rx_l3e_pkt"}, ++ {"igu_rx_l4e_pkt"}, ++ {"igu_rx_rocee_pkt"}, ++ {"igu_rx_out_udp0_pkt"}, ++ ++ {"igu_rx_in_udp0_pkt"}, ++ {"igu_egu_rsv0", "igu_egu_mul_car_drop_pkt_cnt_l"}, ++ {"igu_egu_rsv1", "igu_egu_mul_car_drop_pkt_cnt_h"}, ++ {"igu_egu_rsv2", "igu_egu_bro_car_drop_pkt_cnt_l"}, ++ {"igu_egu_rsv3", "igu_egu_bro_car_drop_pkt_cnt_h"}, ++ {"igu_egu_rsv4", "igu_egu_rsv0"}, ++ ++ {"igu_rx_oversize_pkt_l"}, ++ {"igu_rx_oversize_pkt_h"}, ++ {"igu_rx_undersize_pkt_l"}, ++ {"igu_rx_undersize_pkt_h"}, ++ {"igu_rx_out_all_pkt_l"}, ++ {"igu_rx_out_all_pkt_h"}, ++ ++ {"igu_tx_out_all_pkt_l"}, ++ {"igu_tx_out_all_pkt_h"}, ++ {"igu_rx_uni_pkt_l"}, ++ {"igu_rx_uni_pkt_h"}, ++ {"igu_rx_multi_pkt_l"}, ++ {"igu_rx_multi_pkt_h"}, ++ ++ {"igu_rx_broad_pkt_l"}, ++ {"igu_rx_broad_pkt_h"}, ++ {"egu_tx_out_all_pkt_l"}, ++ {"egu_tx_out_all_pkt_h"}, ++ {"egu_tx_uni_pkt_l"}, ++ {"egu_tx_uni_pkt_h"}, ++ ++ {"egu_tx_multi_pkt_l"}, ++ {"egu_tx_multi_pkt_h"}, ++ {"egu_tx_broad_pkt_l"}, ++ {"egu_tx_broad_pkt_h"}, ++ {"igu_tx_key_num_l"}, ++ {"igu_tx_key_num_h"}, ++ ++ {"igu_rx_non_tun_pkt_l"}, ++ {"igu_rx_non_tun_pkt_h"}, ++ {"igu_rx_tun_pkt_l"}, ++ {"igu_rx_tun_pkt_h"}, ++ {"igu_egu_rsv5"}, ++ {"igu_egu_rsv6"}, ++}; ++ ++static struct hns3_dfx_reg_entry dfx_rpu_reg_0_list[] = { ++ {"rpu_tc_queue_num", "rpu_currport_tnl_index"}, ++ {"rpu_fsm_dfx_st0"}, ++ {"rpu_fsm_dfx_st1"}, ++ {"rpu_rpu_rx_pkt_drop_cnt"}, ++ {"rpu_buf_wait_timeout"}, ++ {"rpu_buf_wait_timeout_qid"}, ++}; ++ ++static struct hns3_dfx_reg_entry dfx_rpu_reg_1_list[] = { ++ {"rpu_rsv0"}, ++ {"rpu_fifo_dfx_st0"}, ++ {"rpu_fifo_dfx_st1"}, ++ {"rpu_fifo_dfx_st2"}, ++ {"rpu_fifo_dfx_st3"}, ++ {"rpu_fifo_dfx_st4"}, ++ ++ {"rpu_fifo_dfx_st5"}, ++ {"rpu_rsv1"}, ++ {"rpu_rsv2"}, ++ {"rpu_rsv3"}, ++ {"rpu_rsv4"}, ++ {"rpu_rsv5"}, ++}; ++ ++static struct hns3_dfx_reg_entry dfx_ncsi_reg_list[] = { ++ {"ncsi_rsv0"}, ++ {"ncsi_egu_tx_fifo_sts"}, ++ {"ncsi_pause_status"}, ++ {"ncsi_rx_ctrl_dmac_err_cnt"}, ++ {"ncsi_rx_ctrl_smac_err_cnt"}, ++ {"ncsi_rx_ctrl_cks_err_cnt"}, ++ ++ {"ncsi_rx_ctrl_pkt_err_cnt"}, ++ {"ncsi_rx_pt_dmac_err_cnt"}, ++ {"ncsi_rx_pt_smac_err_cnt"}, ++ {"ncsi_rx_pt_pkt_cnt"}, ++ {"ncsi_rx_fcs_err_cnt"}, ++ {"ncsi_tx_ctrl_dmac_err_cnt"}, ++ ++ {"ncsi_tx_ctrl_smac_err_cnt"}, ++ {"ncsi_tx_ctrl_pkt_cnt"}, ++ {"ncsi_tx_pt_dmac_err_cnt"}, ++ {"ncsi_tx_pt_smac_err_cnt"}, ++ {"ncsi_tx_pt_pkt_cnt"}, ++ {"ncsi_tx_pt_pkt_trun_cnt"}, ++ ++ {"ncsi_tx_pt_pkt_err_cnt"}, ++ {"ncsi_tx_ctrl_pkt_err_cnt"}, ++ {"ncsi_rx_ctrl_pkt_trun_cnt"}, ++ {"ncsi_rx_ctrl_pkt_cflit_cnt"}, ++ {"ncsi_rsv1"}, ++ {"ncsi_rsv2"}, ++ ++ {"ncsi_mac_rx_octets_ok"}, ++ {"ncsi_mac_rx_octets_bad"}, ++ {"ncsi_mac_rx_uc_pkts"}, ++ {"ncsi_mac_rx_mc_pkts"}, ++ {"ncsi_mac_rx_bc_pkts"}, ++ {"ncsi_mac_rx_pkts_64octets"}, ++ ++ {"ncsi_mac_rx_pkts_64to127_octets"}, ++ {"ncsi_mac_rx_pkts_128to255_octets"}, ++ {"ncsi_mac_rx_pkts_256to511_octets"}, ++ {"ncsi_mac_rx_pkts_512to1023_octets"}, ++ {"ncsi_mac_rx_pkts_1024to1518_octets"}, ++ {"ncsi_mac_rx_pkts_1519tomax_octets"}, ++ ++ {"ncsi_mac_rx_fcs_errors"}, ++ {"ncsi_mac_rx_long_errors"}, ++ {"ncsi_mac_rx_jabber_errors"}, ++ {"ncsi_mac_rx_runt_err_cnt"}, ++ {"ncsi_mac_rx_short_err_cnt"}, ++ {"ncsi_mac_rx_filt_pkt_cnt"}, ++ ++ {"ncsi_mac_rx_octets_total_filt"}, ++ {"ncsi_mac_tx_octets_ok"}, ++ {"ncsi_mac_tx_octets_bad"}, ++ {"ncsi_mac_tx_uc_pkts"}, ++ {"ncsi_mac_tx_mc_pkts"}, ++ {"ncsi_mac_tx_bc_pkts"}, ++ ++ {"ncsi_mac_tx_pkts_64octets"}, ++ {"ncsi_mac_tx_pkts_64to127_octets"}, ++ {"ncsi_mac_tx_pkts_128to255_octets"}, ++ {"ncsi_mac_tx_pkts_256to511_octets"}, ++ {"ncsi_mac_tx_pkts_512to1023_octets"}, ++ {"ncsi_mac_tx_pkts_1024to1518_octets"}, ++ ++ {"ncsi_mac_tx_pkts_1519tomax_octets"}, ++ {"ncsi_mac_tx_underrun"}, ++ {"ncsi_mac_tx_crc_error"}, ++ {"ncsi_mac_tx_pause_frames"}, ++ {"ncsi_mac_rx_pad_pkts"}, ++ {"ncsi_mac_rx_pause_frames"}, ++}; ++ ++static struct hns3_dfx_reg_entry dfx_rtc_reg_list[] = { ++ {"rtc_rsv0"}, ++ {"lge_igu_afifo_dfx_0"}, ++ {"lge_igu_afifo_dfx_1"}, ++ {"lge_igu_afifo_dfx_2"}, ++ {"lge_igu_afifo_dfx_3"}, ++ {"lge_igu_afifo_dfx_4"}, ++ ++ {"lge_igu_afifo_dfx_5"}, ++ {"lge_igu_afifo_dfx_6"}, ++ {"lge_igu_afifo_dfx_7"}, ++ {"lge_egu_afifo_dfx_0"}, ++ {"lge_egu_afifo_dfx_1"}, ++ {"lge_egu_afifo_dfx_2"}, ++ ++ {"lge_egu_afifo_dfx_3"}, ++ {"lge_egu_afifo_dfx_4"}, ++ {"lge_egu_afifo_dfx_5"}, ++ {"lge_egu_afifo_dfx_6"}, ++ {"lge_egu_afifo_dfx_7"}, ++ {"cge_igu_afifo_dfx_0"}, ++ ++ {"cge_igu_afifo_dfx_1"}, ++ {"cge_egu_afifo_dfx_0"}, ++ {"cge_egu_afifo_dfx_i"}, ++ {"rtc_rsv1"}, ++ {"rtc_rsv2"}, ++ {"rtc_rsv3"}, ++}; ++ ++static struct hns3_dfx_reg_entry dfx_ppp_reg_list[] = { ++ {"ppp_rsv0"}, ++ {"ppp_drop_from_prt_pkt_cnt"}, ++ {"ppp_drop_from_host_pkt_cnt"}, ++ {"ppp_drop_tx_vlan_proc_cnt"}, ++ {"ppp_drop_mng_cnt"}, ++ {"ppp_drop_fd_cnt"}, ++ ++ {"ppp_drop_no_dst_cnt"}, ++ {"ppp_drop_mc_mbid_full_cnt"}, ++ {"ppp_drop_sc_filtered"}, ++ {"ppp_ppp_mc_drop_pkt_cnt"}, ++ {"ppp_drop_pt_cnt"}, ++ {"ppp_drop_mac_anti_spoof_cnt"}, ++ ++ {"ppp_drop_ig_vfv_cnt"}, ++ {"ppp_drop_ig_prtv_cnt"}, ++ {"ppp_drop_cnm_pfc_pause_cnt"}, ++ {"ppp_drop_torus_tc_cnt"}, ++ {"ppp_drop_torus_lpbk_cnt"}, ++ {"ppp_ppp_hfs_sts"}, ++ ++ {"ppp_mc_rslt_sts"}, ++ {"ppp_p3u_sts"}, ++ {"ppp_rslt_descr_sts", "ppp_rsv1"}, ++ {"ppp_umv_sts_0"}, ++ {"ppp_umv_sts_1"}, ++ {"ppp_vfv_sts"}, ++ ++ {"ppp_gro_key_cnt"}, ++ {"ppp_gro_info_cnt"}, ++ {"ppp_gro_drop_cnt"}, ++ {"ppp_gro_out_cnt"}, ++ {"ppp_gro_key_match_data_cnt"}, ++ {"ppp_gro_key_match_tcam_cnt"}, ++ ++ {"ppp_gro_info_match_cnt"}, ++ {"ppp_gro_free_entry_cnt"}, ++ {"ppp_gro_inner_dfx_signal"}, ++ {"ppp_rsv2"}, ++ {"ppp_rsv3"}, ++ {"ppp_rsv4"}, ++ ++ {"ppp_get_rx_pkt_cnt_l"}, ++ {"ppp_get_rx_pkt_cnt_h"}, ++ {"ppp_get_tx_pkt_cnt_l"}, ++ {"ppp_get_tx_pkt_cnt_h"}, ++ {"ppp_send_uc_prt2host_pkt_cnt_l"}, ++ {"ppp_send_uc_prt2host_pkt_cnt_h"}, ++ ++ {"ppp_send_uc_prt2prt_pkt_cnt_l"}, ++ {"ppp_send_uc_prt2prt_pkt_cnt_h"}, ++ {"ppp_send_uc_host2host_pkt_cnt_l"}, ++ {"ppp_send_uc_host2host_pkt_cnt_h"}, ++ {"ppp_send_uc_host2prt_pkt_cnt_l"}, ++ {"ppp_send_uc_host2prt_pkt_cnt_h"}, ++ ++ {"ppp_send_mc_from_prt_cnt_l"}, ++ {"ppp_send_mc_from_prt_cnt_h"}, ++ {"ppp_send_mc_from_host_cnt_l"}, ++ {"ppp_send_mc_from_host_cnt_h"}, ++ {"ppp_ssu_mc_rd_cnt_l"}, ++ {"ppp_ssu_mc_rd_cnt_h"}, ++ ++ {"ppp_ssu_mc_drop_cnt_l"}, ++ {"ppp_ssu_mc_drop_cnt_h"}, ++ {"ppp_ssu_mc_rd_pkt_cnt_l"}, ++ {"ppp_ssu_mc_rd_pkt_cnt_h"}, ++ {"ppp_mc_2host_pkt_cnt_l"}, ++ {"ppp_mc_2host_pkt_cnt_h"}, ++ ++ {"ppp_mc_2prt_pkt_cnt_l"}, ++ {"ppp_mc_2prt_pkt_cnt_h"}, ++ {"ppp_ntsnos_pkt_cnt_l"}, ++ {"ppp_ntsnos_pkt_cnt_h"}, ++ {"ppp_ntup_pkt_cnt_l"}, ++ {"ppp_ntup_pkt_cnt_h"}, ++ ++ {"ppp_ntlcl_pkt_cnt_l"}, ++ {"ppp_ntlcl_pkt_cnt_h"}, ++ {"ppp_nttgt_pkt_cnt_l"}, ++ {"ppp_nttgt_pkt_cnt_h"}, ++ {"ppp_rtns_pkt_cnt_l"}, ++ {"ppp_rtns_pkt_cnt_h"}, ++ ++ {"ppp_rtlpbk_pkt_cnt_l"}, ++ {"ppp_rtlpbk_pkt_cnt_h"}, ++ {"ppp_nr_pkt_cnt_l"}, ++ {"ppp_nr_pkt_cnt_h"}, ++ {"ppp_rr_pkt_cnt_l"}, ++ {"ppp_rr_pkt_cnt_h"}, ++ ++ {"ppp_mng_tbl_hit_cnt_l"}, ++ {"ppp_mng_tbl_hit_cnt_h"}, ++ {"ppp_fd_tbl_hit_cnt_l"}, ++ {"ppp_fd_tbl_hit_cnt_h"}, ++ {"ppp_fd_lkup_cnt_l"}, ++ {"ppp_fd_lkup_cnt_h"}, ++ ++ {"ppp_bc_hit_cnt"}, ++ {"ppp_bc_hit_cnt_h"}, ++ {"ppp_um_tbl_uc_hit_cnt"}, ++ {"ppp_um_tbl_uc_hit_cnt_h"}, ++ {"ppp_um_tbl_mc_hit_cnt"}, ++ {"ppp_um_tbl_mc_hit_cnt_h"}, ++ ++ {"ppp_um_tbl_vmdq1_hit_cnt_l", "ppp_um_tbl_snq_hit_cnt_l"}, ++ {"ppp_um_tbl_vmdq1_hit_cnt_h", "ppp_um_tbl_snq_hit_cnt_h"}, ++ {"ppp_mta_tbl_hit_cnt_l", "ppp_rsv5"}, ++ {"ppp_mta_tbl_hit_cnt_h", "ppp_rsv6"}, ++ {"ppp_fwd_bonding_hit_cnt_l"}, ++ {"ppp_fwd_bonding_hit_cnt_h"}, ++ ++ {"ppp_promisc_tbl_hit_cnt_l"}, ++ {"ppp_promisc_tbl_hit_cnt_h"}, ++ {"ppp_get_tunl_pkt_cnt_l"}, ++ {"ppp_get_tunl_pkt_cnt_h"}, ++ {"ppp_get_bmc_pkt_cnt_l"}, ++ {"ppp_get_bmc_pkt_cnt_h"}, ++ ++ {"ppp_send_uc_prt2bmc_pkt_cnt_l"}, ++ {"ppp_send_uc_prt2bmc_pkt_cnt_h"}, ++ {"ppp_send_uc_host2bmc_pkt_cnt_l"}, ++ {"ppp_send_uc_host2bmc_pkt_cnt_h"}, ++ {"ppp_send_uc_bmc2host_pkt_cnt_l"}, ++ {"ppp_send_uc_bmc2host_pkt_cnt_h"}, ++ ++ {"ppp_send_uc_bmc2prt_pkt_cnt_l"}, ++ {"ppp_send_uc_bmc2prt_pkt_cnt_h"}, ++ {"ppp_mc_2bmc_pkt_cnt_l"}, ++ {"ppp_mc_2bmc_pkt_cnt_h"}, ++ {"ppp_vlan_mirr_cnt_l", "ppp_rsv7"}, ++ {"ppp_vlan_mirr_cnt_h", "ppp_rsv8"}, ++ ++ {"ppp_ig_mirr_cnt_l", "ppp_rsv9"}, ++ {"ppp_ig_mirr_cnt_h", "ppp_rsv10"}, ++ {"ppp_eg_mirr_cnt_l", "ppp_rsv11"}, ++ {"ppp_eg_mirr_cnt_h", "ppp_rsv12"}, ++ {"ppp_rx_default_host_hit_cnt_l"}, ++ {"ppp_rx_default_host_hit_cnt_h"}, ++ ++ {"ppp_lan_pair_cnt_l"}, ++ {"ppp_lan_pair_cnt_h"}, ++ {"ppp_um_tbl_mc_hit_pkt_cnt_l"}, ++ {"ppp_um_tbl_mc_hit_pkt_cnt_h"}, ++ {"ppp_mta_tbl_hit_pkt_cnt_l"}, ++ {"ppp_mta_tbl_hit_pkt_cnt_h"}, ++ ++ {"ppp_promisc_tbl_hit_pkt_cnt_l"}, ++ {"ppp_promisc_tbl_hit_pkt_cnt_h"}, ++ {"ppp_rsv13"}, ++ {"ppp_rsv14"}, ++ {"ppp_rsv15"}, ++ {"ppp_rsv16"}, ++}; ++ ++static struct hns3_dfx_reg_entry dfx_rcb_reg_list[] = { ++ {"rcb_rsv0"}, ++ {"rcb_fsm_dfx_st0"}, ++ {"rcb_fsm_dfx_st1"}, ++ {"rcb_fsm_dfx_st2"}, ++ {"rcb_fifo_dfx_st0"}, ++ {"rcb_fifo_dfx_st1"}, ++ ++ {"rcb_fifo_dfx_st2"}, ++ {"rcb_fifo_dfx_st3"}, ++ {"rcb_fifo_dfx_st4"}, ++ {"rcb_fifo_dfx_st5"}, ++ {"rcb_fifo_dfx_st6"}, ++ {"rcb_fifo_dfx_st7"}, ++ ++ {"rcb_fifo_dfx_st8"}, ++ {"rcb_fifo_dfx_st9"}, ++ {"rcb_fifo_dfx_st10"}, ++ {"rcb_fifo_dfx_st11"}, ++ {"rcb_q_credit_vld_0"}, ++ {"rcb_q_credit_vld_1"}, ++ ++ {"rcb_q_credit_vld_2"}, ++ {"rcb_q_credit_vld_3"}, ++ {"rcb_q_credit_vld_4"}, ++ {"rcb_q_credit_vld_5"}, ++ {"rcb_q_credit_vld_6"}, ++ {"rcb_q_credit_vld_7"}, ++ ++ {"rcb_q_credit_vld_8"}, ++ {"rcb_q_credit_vld_9"}, ++ {"rcb_q_credit_vld_10"}, ++ {"rcb_q_credit_vld_11"}, ++ {"rcb_q_credit_vld_12"}, ++ {"rcb_q_credit_vld_13"}, ++ ++ {"rcb_q_credit_vld_14"}, ++ {"rcb_q_credit_vld_15"}, ++ {"rcb_q_credit_vld_16"}, ++ {"rcb_q_credit_vld_17"}, ++ {"rcb_q_credit_vld_18"}, ++ {"rcb_q_credit_vld_19"}, ++ ++ {"rcb_q_credit_vld_20"}, ++ {"rcb_q_credit_vld_21"}, ++ {"rcb_q_credit_vld_22"}, ++ {"rcb_q_credit_vld_23"}, ++ {"rcb_q_credit_vld_24"}, ++ {"rcb_q_credit_vld_25"}, ++ ++ {"rcb_q_credit_vld_26"}, ++ {"rcb_q_credit_vld_27"}, ++ {"rcb_q_credit_vld_28"}, ++ {"rcb_q_credit_vld_29"}, ++ {"rcb_q_credit_vld_30"}, ++ {"rcb_q_credit_vld_31"}, ++ ++ {"rcb_gro_bd_serr_cnt"}, ++ {"rcb_gro_context_serr_cnt"}, ++ {"rcb_rx_stash_cfg_serr_cnt"}, ++ {"rcb_axi_rd_fbd_serr_cnt", "rcb_rcb_tx_mem_serr_cnt"}, ++ {"rcb_gro_bd_merr_cnt"}, ++ {"rcb_gro_context_merr_cnt"}, ++ ++ {"rcb_rx_stash_cfg_merr_cnt"}, ++ {"rcb_axi_rd_fbd_merr_cnt"}, ++ {"rcb_rsv1"}, ++ {"rcb_rsv2"}, ++ {"rcb_rsv3"}, ++ {"rcb_rsv4"}, ++}; ++ ++static struct hns3_dfx_reg_entry dfx_tqp_reg_list[] = { ++ {"dfx_tqp_q_num"}, ++ {"rcb_cfg_rx_ring_tail"}, ++ {"rcb_cfg_rx_ring_head"}, ++ {"rcb_cfg_rx_ring_fbdnum"}, ++ {"rcb_cfg_rx_ring_offset"}, ++ {"rcb_cfg_rx_ring_fbdoffset"}, ++ ++ {"rcb_cfg_rx_ring_pktnum_record"}, ++ {"rcb_cfg_tx_ring_tail"}, ++ {"rcb_cfg_tx_ring_head"}, ++ {"rcb_cfg_tx_ring_fbdnum"}, ++ {"rcb_cfg_tx_ring_offset"}, ++ {"rcb_cfg_tx_ring_ebdnum"}, ++}; ++ ++static struct hns3_dfx_reg_entry dfx_ssu_reg_2_list[] = { ++ {"dfx_ssu2_oq_index"}, ++ {"dfx_ssu2_queue_cnt"}, ++ {"dfx_ssu2_rsv0"}, ++ {"dfx_ssu2_rsv1"}, ++ {"dfx_ssu2_rsv2"}, ++ {"dfx_ssu2_rsv3"}, ++}; ++ ++enum hns3_reg_modules { ++ HNS3_BIOS_COMMON = 0, ++ HNS3_SSU_0, ++ HNS3_SSU_1, ++ HNS3_IGU_EGU, ++ HNS3_RPU_0, ++ HNS3_RPU_1, ++ HNS3_NCSI, ++ HNS3_RTC, ++ HNS3_PPP, ++ HNS3_RCB, ++ HNS3_TQP, ++ HNS3_SSU_2, ++ ++ HNS3_CMDQ = 12, ++ HNS3_COMMON_PF, ++ HNS3_COMMON_VF, ++ HNS3_RING, ++ HNS3_TQP_INTR, ++ ++ HNS3_32_BIT_DFX, ++ HNS3_64_BIT_DFX, ++}; ++ ++struct hns3_reg_list { ++ const void *reg_list; ++ uint32_t entry_num; ++}; ++ ++static struct hns3_reg_list hns3_reg_lists[] = { ++ [HNS3_BIOS_COMMON] = { dfx_bios_common_reg_list, RTE_DIM(dfx_bios_common_reg_list) }, ++ [HNS3_SSU_0] = { dfx_ssu_reg_0_list, RTE_DIM(dfx_ssu_reg_0_list) }, ++ [HNS3_SSU_1] = { dfx_ssu_reg_1_list, RTE_DIM(dfx_ssu_reg_1_list) }, ++ [HNS3_IGU_EGU] = { dfx_igu_egu_reg_list, RTE_DIM(dfx_igu_egu_reg_list) }, ++ [HNS3_RPU_0] = { dfx_rpu_reg_0_list, RTE_DIM(dfx_rpu_reg_0_list) }, ++ [HNS3_RPU_1] = { dfx_rpu_reg_1_list, RTE_DIM(dfx_rpu_reg_1_list) }, ++ [HNS3_NCSI] = { dfx_ncsi_reg_list, RTE_DIM(dfx_ncsi_reg_list) }, ++ [HNS3_RTC] = { dfx_rtc_reg_list, RTE_DIM(dfx_rtc_reg_list) }, ++ [HNS3_PPP] = { dfx_ppp_reg_list, RTE_DIM(dfx_ppp_reg_list) }, ++ [HNS3_RCB] = { dfx_rcb_reg_list, RTE_DIM(dfx_rcb_reg_list) }, ++ [HNS3_TQP] = { dfx_tqp_reg_list, RTE_DIM(dfx_tqp_reg_list) }, ++ [HNS3_SSU_2] = { dfx_ssu_reg_2_list, RTE_DIM(dfx_ssu_reg_2_list) }, ++ [HNS3_CMDQ] = { cmdq_reg_list, RTE_DIM(cmdq_reg_list) }, ++ [HNS3_COMMON_PF] = { common_reg_list, RTE_DIM(common_reg_list) }, ++ [HNS3_COMMON_VF] = { common_vf_reg_list, RTE_DIM(common_vf_reg_list) }, ++ [HNS3_RING] = { ring_reg_list, RTE_DIM(ring_reg_list) }, ++ [HNS3_TQP_INTR] = { tqp_intr_reg_list, RTE_DIM(tqp_intr_reg_list) }, ++ [HNS3_32_BIT_DFX] = { regs_32_bit_list, RTE_DIM(regs_32_bit_list) }, ++ [HNS3_64_BIT_DFX] = { regs_64_bit_list, RTE_DIM(regs_64_bit_list) }, ++}; + + static const uint32_t hns3_dfx_reg_opcode_list[] = { +- HNS3_OPC_DFX_BIOS_COMMON_REG, +- HNS3_OPC_DFX_SSU_REG_0, +- HNS3_OPC_DFX_SSU_REG_1, +- HNS3_OPC_DFX_IGU_EGU_REG, +- HNS3_OPC_DFX_RPU_REG_0, +- HNS3_OPC_DFX_RPU_REG_1, +- HNS3_OPC_DFX_NCSI_REG, +- HNS3_OPC_DFX_RTC_REG, +- HNS3_OPC_DFX_PPP_REG, +- HNS3_OPC_DFX_RCB_REG, +- HNS3_OPC_DFX_TQP_REG, +- HNS3_OPC_DFX_SSU_REG_2 ++ [HNS3_BIOS_COMMON] = HNS3_OPC_DFX_BIOS_COMMON_REG, ++ [HNS3_SSU_0] = HNS3_OPC_DFX_SSU_REG_0, ++ [HNS3_SSU_1] = HNS3_OPC_DFX_SSU_REG_1, ++ [HNS3_IGU_EGU] = HNS3_OPC_DFX_IGU_EGU_REG, ++ [HNS3_RPU_0] = HNS3_OPC_DFX_RPU_REG_0, ++ [HNS3_RPU_1] = HNS3_OPC_DFX_RPU_REG_1, ++ [HNS3_NCSI] = HNS3_OPC_DFX_NCSI_REG, ++ [HNS3_RTC] = HNS3_OPC_DFX_RTC_REG, ++ [HNS3_PPP] = HNS3_OPC_DFX_PPP_REG, ++ [HNS3_RCB] = HNS3_OPC_DFX_RCB_REG, ++ [HNS3_TQP] = HNS3_OPC_DFX_TQP_REG, ++ [HNS3_SSU_2] = HNS3_OPC_DFX_SSU_REG_2 + }; + + static int +@@ -100,6 +854,11 @@ hns3_get_regs_num(struct hns3_hw *hw, uint32_t *regs_num_32_bit, + + *regs_num_32_bit = rte_le_to_cpu_32(desc.data[0]); + *regs_num_64_bit = rte_le_to_cpu_32(desc.data[1]); ++ if (*regs_num_32_bit != RTE_DIM(regs_32_bit_list) || ++ *regs_num_64_bit * HNS3_64_BIT_REG_OUTPUT_SIZE != RTE_DIM(regs_64_bit_list)) { ++ hns3_err(hw, "Query register number differ from the list!"); ++ return -EINVAL; ++ } + + return 0; + } +@@ -161,6 +920,7 @@ hns3_get_dfx_reg_cnt(struct hns3_hw *hw, uint32_t *count) + { + int opcode_num = RTE_DIM(hns3_dfx_reg_opcode_list); + uint32_t bd_num_list[opcode_num]; ++ uint32_t reg_num; + int ret; + int i; + +@@ -168,8 +928,14 @@ hns3_get_dfx_reg_cnt(struct hns3_hw *hw, uint32_t *count) + if (ret) + return ret; + +- for (i = 0; i < opcode_num; i++) +- *count += bd_num_list[i] * HNS3_CMD_DESC_DATA_NUM; ++ for (i = 0; i < opcode_num; i++) { ++ reg_num = bd_num_list[i] * HNS3_CMD_DESC_DATA_NUM; ++ if (reg_num != hns3_reg_lists[i].entry_num) { ++ hns3_err(hw, "Query register number differ from the list!"); ++ return -EINVAL; ++ } ++ *count += reg_num; ++ } + + return 0; + } +@@ -196,14 +962,13 @@ hns3_get_regs_length(struct hns3_hw *hw, uint32_t *length) + int ret; + + if (hns->is_vf) +- common_cnt = sizeof(common_vf_reg_addrs); ++ common_cnt = RTE_DIM(common_vf_reg_list); + else +- common_cnt = sizeof(common_reg_addrs); ++ common_cnt = RTE_DIM(common_reg_list); + +- len = sizeof(cmdq_reg_addrs) + common_cnt + +- sizeof(ring_reg_addrs) * hw->tqps_num + +- sizeof(tqp_intr_reg_addrs) * hw->intr_tqps_num; +- len /= sizeof(uint32_t); ++ len = RTE_DIM(cmdq_reg_list) + common_cnt + ++ RTE_DIM(ring_reg_list) * hw->tqps_num + ++ RTE_DIM(tqp_intr_reg_list) * hw->intr_tqps_num; + + if (!hns->is_vf) { + ret = hns3_get_firmware_reg_cnt(hw, &dfx_reg_cnt); +@@ -219,13 +984,31 @@ hns3_get_regs_length(struct hns3_hw *hw, uint32_t *length) + return 0; + } + ++static void ++hns3_fill_dfx_regs_name(struct hns3_hw *hw, struct rte_dev_reg_info *regs, ++ const struct hns3_dfx_reg_entry *reg_list, uint32_t reg_num) ++{ ++ uint32_t i, cnt = regs->length; ++ const char *name; ++ ++ if (regs->names == NULL) ++ return; ++ ++ for (i = 0; i < reg_num; i++) { ++ name = reg_list[i].name_v1; ++ if (hw->revision == PCI_REVISION_ID_HIP09_A && reg_list[i].name_v2 != NULL) ++ name = reg_list[i].name_v2; ++ snprintf(regs->names[cnt++].name, RTE_ETH_REG_NAME_SIZE, "%s", name); ++ } ++} ++ + static int +-hns3_get_32_bit_regs(struct hns3_hw *hw, uint32_t regs_num, void *data) ++hns3_get_32_bit_regs(struct hns3_hw *hw, uint32_t regs_num, struct rte_dev_reg_info *regs) + { + #define HNS3_32_BIT_REG_RTN_DATANUM 8 + #define HNS3_32_BIT_DESC_NODATA_LEN 2 ++ uint32_t *reg_val = regs->data; + struct hns3_cmd_desc *desc; +- uint32_t *reg_val = data; + uint32_t *desc_data; + int cmd_num; + int i, k, n; +@@ -254,6 +1037,9 @@ hns3_get_32_bit_regs(struct hns3_hw *hw, uint32_t regs_num, void *data) + return ret; + } + ++ hns3_fill_dfx_regs_name(hw, regs, regs_32_bit_list, regs_num); ++ reg_val += regs->length; ++ regs->length += regs_num; + for (i = 0; i < cmd_num; i++) { + if (i == 0) { + desc_data = &desc[i].data[0]; +@@ -265,7 +1051,6 @@ hns3_get_32_bit_regs(struct hns3_hw *hw, uint32_t regs_num, void *data) + } + for (k = 0; k < n; k++) { + *reg_val++ = rte_le_to_cpu_32(*desc_data++); +- + regs_num--; + if (regs_num == 0) + break; +@@ -277,12 +1062,12 @@ hns3_get_32_bit_regs(struct hns3_hw *hw, uint32_t regs_num, void *data) + } + + static int +-hns3_get_64_bit_regs(struct hns3_hw *hw, uint32_t regs_num, void *data) ++hns3_get_64_bit_regs(struct hns3_hw *hw, uint32_t regs_num, struct rte_dev_reg_info *regs) + { + #define HNS3_64_BIT_REG_RTN_DATANUM 4 + #define HNS3_64_BIT_DESC_NODATA_LEN 1 ++ uint32_t *reg_val = regs->data; + struct hns3_cmd_desc *desc; +- uint64_t *reg_val = data; + uint64_t *desc_data; + int cmd_num; + int i, k, n; +@@ -311,6 +1096,9 @@ hns3_get_64_bit_regs(struct hns3_hw *hw, uint32_t regs_num, void *data) + return ret; + } + ++ hns3_fill_dfx_regs_name(hw, regs, regs_64_bit_list, regs_num * HNS3_64_BIT_REG_OUTPUT_SIZE); ++ reg_val += regs->length; ++ regs->length += regs_num * HNS3_64_BIT_REG_OUTPUT_SIZE; + for (i = 0; i < cmd_num; i++) { + if (i == 0) { + desc_data = (uint64_t *)(&desc[i].data[0]); +@@ -322,7 +1110,6 @@ hns3_get_64_bit_regs(struct hns3_hw *hw, uint32_t regs_num, void *data) + } + for (k = 0; k < n; k++) { + *reg_val++ = rte_le_to_cpu_64(*desc_data++); +- + regs_num--; + if (!regs_num) + break; +@@ -333,47 +1120,80 @@ hns3_get_64_bit_regs(struct hns3_hw *hw, uint32_t regs_num, void *data) + return 0; + } + +-static int +-hns3_direct_access_regs(struct hns3_hw *hw, uint32_t *data) ++static void ++hns3_direct_access_regs_help(struct hns3_hw *hw, struct rte_dev_reg_info *regs, ++ enum hns3_reg_modules idx) + { +- struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); +- uint32_t *origin_data_ptr = data; +- uint32_t reg_offset; +- size_t reg_num; +- uint16_t j; +- size_t i; ++ const struct hns3_dirt_reg_entry *reg_list; ++ uint32_t *data = regs->data; ++ size_t reg_num, i, cnt; ++ ++ data += regs->length; ++ reg_num = hns3_reg_lists[idx].entry_num; ++ reg_list = hns3_reg_lists[idx].reg_list; ++ cnt = regs->length; ++ for (i = 0; i < reg_num; i++) { ++ *data++ = hns3_read_dev(hw, reg_list[i].addr); ++ if (regs->names != NULL) ++ snprintf(regs->names[cnt++].name, RTE_ETH_REG_NAME_SIZE, ++ "%s", reg_list[i].name); ++ } + +- /* fetching per-PF registers values from PF PCIe register space */ +- reg_num = sizeof(cmdq_reg_addrs) / sizeof(uint32_t); +- for (i = 0; i < reg_num; i++) +- *data++ = hns3_read_dev(hw, cmdq_reg_addrs[i]); ++ regs->length += reg_num; ++} ++ ++static uint32_t ++hns3_get_module_tqp_reg_offset(enum hns3_reg_modules idx, uint16_t queue_id) ++{ ++ if (idx == HNS3_RING) ++ return hns3_get_tqp_reg_offset(queue_id); ++ else if (idx == HNS3_TQP_INTR) ++ return hns3_get_tqp_intr_reg_offset(queue_id); ++ ++ return 0; ++} ++ ++static void ++hns3_direct_access_tqp_regs_help(struct hns3_hw *hw, struct rte_dev_reg_info *regs, ++ enum hns3_reg_modules idx) ++{ ++ const struct hns3_dirt_reg_entry *reg_list; ++ uint16_t tqp_num, reg_offset; ++ uint32_t *data = regs->data; ++ uint32_t reg_num, i, j; ++ ++ if (idx != HNS3_RING && idx != HNS3_TQP_INTR) ++ return; ++ ++ tqp_num = (idx == HNS3_RING) ? hw->tqps_num : hw->intr_tqps_num; ++ reg_list = hns3_reg_lists[idx].reg_list; ++ reg_num = hns3_reg_lists[idx].entry_num; ++ data += regs->length; ++ for (i = 0; i < tqp_num; i++) { ++ reg_offset = hns3_get_module_tqp_reg_offset(idx, i); ++ for (j = 0; j < reg_num; j++) { ++ *data++ = hns3_read_dev(hw, reg_list[j].addr + reg_offset); ++ if (regs->names != NULL) ++ snprintf(regs->names[regs->length].name, ++ RTE_ETH_REG_NAME_SIZE, "Q%u_%s", i, reg_list[j].name); ++ regs->length++; ++ } ++ } ++} ++ ++static void ++hns3_direct_access_regs(struct hns3_hw *hw, struct rte_dev_reg_info *regs) ++{ ++ struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); + + if (hns->is_vf) +- reg_num = sizeof(common_vf_reg_addrs) / sizeof(uint32_t); ++ hns3_direct_access_regs_help(hw, regs, HNS3_COMMON_VF); + else +- reg_num = sizeof(common_reg_addrs) / sizeof(uint32_t); +- for (i = 0; i < reg_num; i++) +- if (hns->is_vf) +- *data++ = hns3_read_dev(hw, common_vf_reg_addrs[i]); +- else +- *data++ = hns3_read_dev(hw, common_reg_addrs[i]); +- +- reg_num = sizeof(ring_reg_addrs) / sizeof(uint32_t); +- for (j = 0; j < hw->tqps_num; j++) { +- reg_offset = hns3_get_tqp_reg_offset(j); +- for (i = 0; i < reg_num; i++) +- *data++ = hns3_read_dev(hw, +- ring_reg_addrs[i] + reg_offset); +- } ++ hns3_direct_access_regs_help(hw, regs, HNS3_COMMON_PF); + +- reg_num = sizeof(tqp_intr_reg_addrs) / sizeof(uint32_t); +- for (j = 0; j < hw->intr_tqps_num; j++) { +- reg_offset = hns3_get_tqp_intr_reg_offset(j); +- for (i = 0; i < reg_num; i++) +- *data++ = hns3_read_dev(hw, tqp_intr_reg_addrs[i] + +- reg_offset); +- } +- return data - origin_data_ptr; ++ hns3_direct_access_regs_help(hw, regs, HNS3_CMDQ); ++ hns3_direct_access_tqp_regs_help(hw, regs, HNS3_RING); ++ hns3_direct_access_tqp_regs_help(hw, regs, HNS3_TQP_INTR); + } + + static int +@@ -417,13 +1237,13 @@ hns3_dfx_reg_fetch_data(struct hns3_cmd_desc *desc, int bd_num, uint32_t *reg) + } + + static int +-hns3_get_dfx_regs(struct hns3_hw *hw, void **data) ++hns3_get_dfx_regs(struct hns3_hw *hw, struct rte_dev_reg_info *regs) + { + int opcode_num = RTE_DIM(hns3_dfx_reg_opcode_list); +- uint32_t max_bd_num, bd_num, opcode; ++ uint32_t max_bd_num, bd_num, opcode, regs_num; + uint32_t bd_num_list[opcode_num]; + struct hns3_cmd_desc *cmd_descs; +- uint32_t *reg_val = (uint32_t *)*data; ++ uint32_t *data = regs->data; + int ret; + int i; + +@@ -447,42 +1267,47 @@ hns3_get_dfx_regs(struct hns3_hw *hw, void **data) + ret = hns3_dfx_reg_cmd_send(hw, cmd_descs, bd_num, opcode); + if (ret) + break; +- reg_val += hns3_dfx_reg_fetch_data(cmd_descs, bd_num, reg_val); ++ ++ data += regs->length; ++ regs_num = hns3_dfx_reg_fetch_data(cmd_descs, bd_num, data); ++ hns3_fill_dfx_regs_name(hw, regs, hns3_reg_lists[i].reg_list, regs_num); ++ regs->length += regs_num; + } + rte_free(cmd_descs); +- *data = (void *)reg_val; + + return ret; + } + + static int +-hns3_get_regs_from_firmware(struct hns3_hw *hw, uint32_t *data) ++hns3_get_regs_from_firmware(struct hns3_hw *hw, struct rte_dev_reg_info *regs) + { ++ struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); + uint32_t regs_num_32_bit; + uint32_t regs_num_64_bit; + int ret; + ++ if (hns->is_vf) ++ return 0; ++ + ret = hns3_get_regs_num(hw, ®s_num_32_bit, ®s_num_64_bit); + if (ret) { + hns3_err(hw, "Get register number failed, ret = %d", ret); + return ret; + } + +- ret = hns3_get_32_bit_regs(hw, regs_num_32_bit, data); ++ ret = hns3_get_32_bit_regs(hw, regs_num_32_bit, regs); + if (ret) { + hns3_err(hw, "Get 32 bit register failed, ret = %d", ret); + return ret; + } +- data += regs_num_32_bit; + +- ret = hns3_get_64_bit_regs(hw, regs_num_64_bit, data); ++ ret = hns3_get_64_bit_regs(hw, regs_num_64_bit, regs); + if (ret) { + hns3_err(hw, "Get 64 bit register failed, ret = %d", ret); + return ret; + } +- data += regs_num_64_bit * HNS3_64_BIT_REG_OUTPUT_SIZE; + +- return hns3_get_dfx_regs(hw, (void **)&data); ++ return hns3_get_dfx_regs(hw, regs); + } + + int +@@ -491,15 +1316,13 @@ hns3_get_regs(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs) + struct hns3_adapter *hns = eth_dev->data->dev_private; + struct hns3_hw *hw = &hns->hw; + uint32_t length; +- uint32_t *data; + int ret; + + ret = hns3_get_regs_length(hw, &length); + if (ret) + return ret; + +- data = regs->data; +- if (data == NULL) { ++ if (regs->data == NULL) { + regs->length = length; + regs->width = sizeof(uint32_t); + return 0; +@@ -510,13 +1333,12 @@ hns3_get_regs(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs) + return -ENOTSUP; + + regs->version = hw->fw_version; ++ /* to count the number of filled registers */ ++ regs->length = 0; + + /* fetching per-PF registers values from PF PCIe register space */ +- data += hns3_direct_access_regs(hw, data); +- +- if (hns->is_vf) +- return 0; ++ hns3_direct_access_regs(hw, regs); + + /* fetching PF common registers values from firmware */ +- return hns3_get_regs_from_firmware(hw, data); ++ return hns3_get_regs_from_firmware(hw, regs); + } +-- +2.33.0 + diff --git a/0494-net-hns3-support-filtering-registers-by-module-names.patch b/0494-net-hns3-support-filtering-registers-by-module-names.patch new file mode 100644 index 0000000000000000000000000000000000000000..0c9be1463c68d0688140c476ce362499b675fe6a --- /dev/null +++ b/0494-net-hns3-support-filtering-registers-by-module-names.patch @@ -0,0 +1,441 @@ +From e6dd10c3d6d80b7ef0d268384e0d0689a80c2d6f Mon Sep 17 00:00:00 2001 +From: Jie Hai +Date: Thu, 26 Sep 2024 20:42:49 +0800 +Subject: [PATCH 494/500] net/hns3: support filtering registers by module names + +[ upstream commit 99d3bd8b85d357c8d4e7ee23765a073f4970ff74 ] + +This patch support dumping registers which module name is the +`filter` string. The module names are in lower case and so is +the `filter`. Available module names are cmdq, common_pf, +common_vf, ring, tqp_intr, 32_bit_dfx, 64_bit_dfx, bios, igu_egu, +ssu, ppp, rpu, ncsi, rtc, rcb, etc. + +Signed-off-by: Jie Hai +Acked-by: Chengwen Feng +Signed-off-by: chenyi +--- + doc/guides/nics/hns3.rst | 9 ++ + drivers/net/hns3/hns3_regs.c | 257 ++++++++++++++++++++--------------- + 2 files changed, 159 insertions(+), 107 deletions(-) + +diff --git a/doc/guides/nics/hns3.rst b/doc/guides/nics/hns3.rst +index f53493cfdc..31301e39e8 100644 +--- a/doc/guides/nics/hns3.rst ++++ b/doc/guides/nics/hns3.rst +@@ -407,6 +407,15 @@ be provided to avoid scheduling the CPU core used by DPDK application threads fo + other tasks. Before starting the Linux OS, add the kernel isolation boot parameter. + For example, "isolcpus=1-18 nohz_full=1-18 rcu_nocbs=1-18". + ++Dump registers ++-------------- ++ ++HNS3 supports dumping registers values with their names, ++and supports filtering by module names. ++The available module names are ``bios``, ``ssu``, ``igu_egu``, ++``rpu``, ``ncsi``, ``rtc``, ``ppp``, ``rcb``, ``tqp``, ``rtc``, ``cmdq``, ++``common_pf``, ``common_vf``, ``ring``, ``tqp_intr``, ``32_bit_dfx``, ++``64_bit_dfx``. + + Limitations or Known issues + --------------------------- +diff --git a/drivers/net/hns3/hns3_regs.c b/drivers/net/hns3/hns3_regs.c +index 22151dde9a..8148a6327c 100644 +--- a/drivers/net/hns3/hns3_regs.c ++++ b/drivers/net/hns3/hns3_regs.c +@@ -12,7 +12,7 @@ + + #define HNS3_64_BIT_REG_OUTPUT_SIZE (sizeof(uint64_t) / sizeof(uint32_t)) + +-static int hns3_get_dfx_reg_cnt(struct hns3_hw *hw, uint32_t *count); ++#define HNS3_MAX_MODULES_LEN 512 + + struct hns3_dirt_reg_entry { + const char *name; +@@ -795,11 +795,39 @@ enum hns3_reg_modules { + HNS3_64_BIT_DFX, + }; + ++#define HNS3_MODULE_MASK(x) RTE_BIT32(x) ++#define HNS3_VF_MODULES (HNS3_MODULE_MASK(HNS3_CMDQ) | HNS3_MODULE_MASK(HNS3_COMMON_VF) | \ ++ HNS3_MODULE_MASK(HNS3_RING) | HNS3_MODULE_MASK(HNS3_TQP_INTR)) ++#define HNS3_VF_ONLY_MODULES HNS3_MODULE_MASK(HNS3_COMMON_VF) ++ + struct hns3_reg_list { + const void *reg_list; + uint32_t entry_num; + }; + ++struct { ++ const char *name; ++ uint32_t module; ++} hns3_module_name_map[] = { ++ { "bios", HNS3_MODULE_MASK(HNS3_BIOS_COMMON) }, ++ { "ssu", HNS3_MODULE_MASK(HNS3_SSU_0) | HNS3_MODULE_MASK(HNS3_SSU_1) | ++ HNS3_MODULE_MASK(HNS3_SSU_2) }, ++ { "igu_egu", HNS3_MODULE_MASK(HNS3_IGU_EGU) }, ++ { "rpu", HNS3_MODULE_MASK(HNS3_RPU_0) | HNS3_MODULE_MASK(HNS3_RPU_1) }, ++ { "ncsi", HNS3_MODULE_MASK(HNS3_NCSI) }, ++ { "rtc", HNS3_MODULE_MASK(HNS3_RTC) }, ++ { "ppp", HNS3_MODULE_MASK(HNS3_PPP) }, ++ { "rcb", HNS3_MODULE_MASK(HNS3_RCB) }, ++ { "tqp", HNS3_MODULE_MASK(HNS3_TQP) }, ++ { "cmdq", HNS3_MODULE_MASK(HNS3_CMDQ) }, ++ { "common_pf", HNS3_MODULE_MASK(HNS3_COMMON_PF) }, ++ { "common_vf", HNS3_MODULE_MASK(HNS3_COMMON_VF) }, ++ { "ring", HNS3_MODULE_MASK(HNS3_RING) }, ++ { "tqp_intr", HNS3_MODULE_MASK(HNS3_TQP_INTR) }, ++ { "32_bit_dfx", HNS3_MODULE_MASK(HNS3_32_BIT_DFX) }, ++ { "64_bit_dfx", HNS3_MODULE_MASK(HNS3_64_BIT_DFX) }, ++}; ++ + static struct hns3_reg_list hns3_reg_lists[] = { + [HNS3_BIOS_COMMON] = { dfx_bios_common_reg_list, RTE_DIM(dfx_bios_common_reg_list) }, + [HNS3_SSU_0] = { dfx_ssu_reg_0_list, RTE_DIM(dfx_ssu_reg_0_list) }, +@@ -863,21 +891,58 @@ hns3_get_regs_num(struct hns3_hw *hw, uint32_t *regs_num_32_bit, + return 0; + } + +-static int +-hns3_get_32_64_regs_cnt(struct hns3_hw *hw, uint32_t *count) ++static const char * ++hns3_get_name_by_module(enum hns3_reg_modules module) + { +- uint32_t regs_num_32_bit, regs_num_64_bit; +- int ret; ++ size_t i; + +- ret = hns3_get_regs_num(hw, ®s_num_32_bit, ®s_num_64_bit); +- if (ret) { +- hns3_err(hw, "fail to get the number of registers, " +- "ret = %d.", ret); +- return ret; ++ for (i = 0; i < RTE_DIM(hns3_module_name_map); i++) { ++ if (hns3_module_name_map[i].module && HNS3_MODULE_MASK(module) != 0) ++ return hns3_module_name_map[i].name; + } ++ return "unknown"; ++} + +- *count += regs_num_32_bit + regs_num_64_bit * HNS3_64_BIT_REG_OUTPUT_SIZE; +- return 0; ++static void ++hns3_get_module_names(char *names, uint32_t len) ++{ ++ size_t i; ++ ++ for (i = 0; i < RTE_DIM(hns3_module_name_map); i++) { ++ strlcat(names, " ", len); ++ strlcat(names, hns3_module_name_map[i].name, len); ++ } ++} ++ ++static uint32_t ++hns3_parse_modules_by_filter(struct hns3_hw *hw, const char *filter) ++{ ++ struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); ++ char names[HNS3_MAX_MODULES_LEN] = {0}; ++ uint32_t modules = 0; ++ size_t i; ++ ++ if (filter == NULL) { ++ modules = (1 << RTE_DIM(hns3_reg_lists)) - 1; ++ } else { ++ for (i = 0; i < RTE_DIM(hns3_module_name_map); i++) { ++ if (strcmp(filter, hns3_module_name_map[i].name) == 0) { ++ modules |= hns3_module_name_map[i].module; ++ break; ++ } ++ } ++ } ++ ++ if (hns->is_vf) ++ modules &= HNS3_VF_MODULES; ++ else ++ modules &= ~HNS3_VF_ONLY_MODULES; ++ if (modules == 0) { ++ hns3_get_module_names(names, HNS3_MAX_MODULES_LEN); ++ hns3_err(hw, "mismatched module name! Available names are:%s.", ++ names); ++ } ++ return modules; + } + + static int +@@ -915,73 +980,25 @@ hns3_get_dfx_reg_bd_num(struct hns3_hw *hw, uint32_t *bd_num_list, + return 0; + } + +-static int +-hns3_get_dfx_reg_cnt(struct hns3_hw *hw, uint32_t *count) +-{ +- int opcode_num = RTE_DIM(hns3_dfx_reg_opcode_list); +- uint32_t bd_num_list[opcode_num]; +- uint32_t reg_num; +- int ret; +- int i; +- +- ret = hns3_get_dfx_reg_bd_num(hw, bd_num_list, opcode_num); +- if (ret) +- return ret; +- +- for (i = 0; i < opcode_num; i++) { +- reg_num = bd_num_list[i] * HNS3_CMD_DESC_DATA_NUM; +- if (reg_num != hns3_reg_lists[i].entry_num) { +- hns3_err(hw, "Query register number differ from the list!"); +- return -EINVAL; +- } +- *count += reg_num; +- } +- +- return 0; +-} +- +-static int +-hns3_get_firmware_reg_cnt(struct hns3_hw *hw, uint32_t *count) +-{ +- int ret; +- +- ret = hns3_get_32_64_regs_cnt(hw, count); +- if (ret < 0) +- return ret; +- +- return hns3_get_dfx_reg_cnt(hw, count); +-} +- +-static int +-hns3_get_regs_length(struct hns3_hw *hw, uint32_t *length) ++static uint32_t ++hns3_get_regs_length(struct hns3_hw *hw, uint32_t modules) + { +- struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); +- uint32_t dfx_reg_cnt = 0; +- uint32_t common_cnt; +- uint32_t len; +- int ret; +- +- if (hns->is_vf) +- common_cnt = RTE_DIM(common_vf_reg_list); +- else +- common_cnt = RTE_DIM(common_reg_list); ++ uint32_t reg_num = 0, length = 0; ++ uint32_t i; + +- len = RTE_DIM(cmdq_reg_list) + common_cnt + +- RTE_DIM(ring_reg_list) * hw->tqps_num + +- RTE_DIM(tqp_intr_reg_list) * hw->intr_tqps_num; ++ for (i = 0; i < RTE_DIM(hns3_reg_lists); i++) { ++ if ((RTE_BIT32(i) & modules) == 0) ++ continue; ++ reg_num = hns3_reg_lists[i].entry_num; ++ if (i == HNS3_RING) ++ reg_num *= hw->tqps_num; ++ else if (i == HNS3_TQP_INTR) ++ reg_num *= hw->intr_tqps_num; + +- if (!hns->is_vf) { +- ret = hns3_get_firmware_reg_cnt(hw, &dfx_reg_cnt); +- if (ret) { +- hns3_err(hw, "fail to get the number of dfx registers, " +- "ret = %d.", ret); +- return ret; +- } +- len += dfx_reg_cnt; ++ length += reg_num; + } + +- *length = len; +- return 0; ++ return length; + } + + static void +@@ -1122,12 +1139,15 @@ hns3_get_64_bit_regs(struct hns3_hw *hw, uint32_t regs_num, struct rte_dev_reg_i + + static void + hns3_direct_access_regs_help(struct hns3_hw *hw, struct rte_dev_reg_info *regs, +- enum hns3_reg_modules idx) ++ uint32_t modules, enum hns3_reg_modules idx) + { + const struct hns3_dirt_reg_entry *reg_list; + uint32_t *data = regs->data; + size_t reg_num, i, cnt; + ++ if ((modules & HNS3_MODULE_MASK(idx)) == 0) ++ return; ++ + data += regs->length; + reg_num = hns3_reg_lists[idx].entry_num; + reg_list = hns3_reg_lists[idx].reg_list; +@@ -1155,14 +1175,14 @@ hns3_get_module_tqp_reg_offset(enum hns3_reg_modules idx, uint16_t queue_id) + + static void + hns3_direct_access_tqp_regs_help(struct hns3_hw *hw, struct rte_dev_reg_info *regs, +- enum hns3_reg_modules idx) ++ uint32_t modules, enum hns3_reg_modules idx) + { + const struct hns3_dirt_reg_entry *reg_list; + uint16_t tqp_num, reg_offset; + uint32_t *data = regs->data; + uint32_t reg_num, i, j; + +- if (idx != HNS3_RING && idx != HNS3_TQP_INTR) ++ if ((modules & HNS3_MODULE_MASK(idx)) == 0) + return; + + tqp_num = (idx == HNS3_RING) ? hw->tqps_num : hw->intr_tqps_num; +@@ -1182,18 +1202,13 @@ hns3_direct_access_tqp_regs_help(struct hns3_hw *hw, struct rte_dev_reg_info *re + } + + static void +-hns3_direct_access_regs(struct hns3_hw *hw, struct rte_dev_reg_info *regs) ++hns3_direct_access_regs(struct hns3_hw *hw, struct rte_dev_reg_info *regs, uint32_t modules) + { +- struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); +- +- if (hns->is_vf) +- hns3_direct_access_regs_help(hw, regs, HNS3_COMMON_VF); +- else +- hns3_direct_access_regs_help(hw, regs, HNS3_COMMON_PF); +- +- hns3_direct_access_regs_help(hw, regs, HNS3_CMDQ); +- hns3_direct_access_tqp_regs_help(hw, regs, HNS3_RING); +- hns3_direct_access_tqp_regs_help(hw, regs, HNS3_TQP_INTR); ++ hns3_direct_access_regs_help(hw, regs, modules, HNS3_COMMON_VF); ++ hns3_direct_access_regs_help(hw, regs, modules, HNS3_COMMON_PF); ++ hns3_direct_access_regs_help(hw, regs, modules, HNS3_CMDQ); ++ hns3_direct_access_tqp_regs_help(hw, regs, modules, HNS3_RING); ++ hns3_direct_access_tqp_regs_help(hw, regs, modules, HNS3_TQP_INTR); + } + + static int +@@ -1237,7 +1252,7 @@ hns3_dfx_reg_fetch_data(struct hns3_cmd_desc *desc, int bd_num, uint32_t *reg) + } + + static int +-hns3_get_dfx_regs(struct hns3_hw *hw, struct rte_dev_reg_info *regs) ++hns3_get_dfx_regs(struct hns3_hw *hw, struct rte_dev_reg_info *regs, uint32_t modules) + { + int opcode_num = RTE_DIM(hns3_dfx_reg_opcode_list); + uint32_t max_bd_num, bd_num, opcode, regs_num; +@@ -1262,6 +1277,8 @@ hns3_get_dfx_regs(struct hns3_hw *hw, struct rte_dev_reg_info *regs) + for (i = 0; i < opcode_num; i++) { + opcode = hns3_dfx_reg_opcode_list[i]; + bd_num = bd_num_list[i]; ++ if ((modules & HNS3_MODULE_MASK(i)) == 0) ++ continue; + if (bd_num == 0) + continue; + ret = hns3_dfx_reg_cmd_send(hw, cmd_descs, bd_num, opcode); +@@ -1270,6 +1287,11 @@ hns3_get_dfx_regs(struct hns3_hw *hw, struct rte_dev_reg_info *regs) + + data += regs->length; + regs_num = hns3_dfx_reg_fetch_data(cmd_descs, bd_num, data); ++ if (regs_num != hns3_reg_lists[i].entry_num) { ++ hns3_err(hw, "Query register number differ from the list for module %s!", ++ hns3_get_name_by_module(i)); ++ return -EINVAL; ++ } + hns3_fill_dfx_regs_name(hw, regs, hns3_reg_lists[i].reg_list, regs_num); + regs->length += regs_num; + } +@@ -1279,14 +1301,14 @@ hns3_get_dfx_regs(struct hns3_hw *hw, struct rte_dev_reg_info *regs) + } + + static int +-hns3_get_regs_from_firmware(struct hns3_hw *hw, struct rte_dev_reg_info *regs) ++hns3_get_32_b4_bit_regs(struct hns3_hw *hw, struct rte_dev_reg_info *regs, uint32_t modules) + { +- struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); + uint32_t regs_num_32_bit; + uint32_t regs_num_64_bit; + int ret; + +- if (hns->is_vf) ++ if ((modules & HNS3_MODULE_MASK(HNS3_32_BIT_DFX)) == 0 && ++ (modules & HNS3_MODULE_MASK(HNS3_64_BIT_DFX)) == 0) + return 0; + + ret = hns3_get_regs_num(hw, ®s_num_32_bit, ®s_num_64_bit); +@@ -1295,19 +1317,39 @@ hns3_get_regs_from_firmware(struct hns3_hw *hw, struct rte_dev_reg_info *regs) + return ret; + } + +- ret = hns3_get_32_bit_regs(hw, regs_num_32_bit, regs); +- if (ret) { +- hns3_err(hw, "Get 32 bit register failed, ret = %d", ret); +- return ret; ++ if ((modules & HNS3_MODULE_MASK(HNS3_32_BIT_DFX)) != 0) { ++ ret = hns3_get_32_bit_regs(hw, regs_num_32_bit, regs); ++ if (ret) { ++ hns3_err(hw, "Get 32 bit register failed, ret = %d", ret); ++ return ret; ++ } + } + +- ret = hns3_get_64_bit_regs(hw, regs_num_64_bit, regs); +- if (ret) { +- hns3_err(hw, "Get 64 bit register failed, ret = %d", ret); +- return ret; ++ if ((modules & HNS3_MODULE_MASK(HNS3_64_BIT_DFX)) != 0) { ++ ret = hns3_get_64_bit_regs(hw, regs_num_64_bit, regs); ++ if (ret) { ++ hns3_err(hw, "Get 64 bit register failed, ret = %d", ret); ++ return ret; ++ } + } + +- return hns3_get_dfx_regs(hw, regs); ++ return 0; ++} ++ ++static int ++hns3_get_regs_from_firmware(struct hns3_hw *hw, struct rte_dev_reg_info *regs, uint32_t modules) ++{ ++ struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); ++ int ret; ++ ++ if (hns->is_vf) ++ return 0; ++ ++ ret = hns3_get_32_b4_bit_regs(hw, regs, modules); ++ if (ret != 0) ++ return ret; ++ ++ return hns3_get_dfx_regs(hw, regs, modules); + } + + int +@@ -1315,13 +1357,14 @@ hns3_get_regs(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs) + { + struct hns3_adapter *hns = eth_dev->data->dev_private; + struct hns3_hw *hw = &hns->hw; ++ uint32_t modules; + uint32_t length; +- int ret; + +- ret = hns3_get_regs_length(hw, &length); +- if (ret) +- return ret; ++ modules = hns3_parse_modules_by_filter(hw, regs->filter); ++ if (modules == 0) ++ return -EINVAL; + ++ length = hns3_get_regs_length(hw, modules); + if (regs->data == NULL) { + regs->length = length; + regs->width = sizeof(uint32_t); +@@ -1337,8 +1380,8 @@ hns3_get_regs(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs) + regs->length = 0; + + /* fetching per-PF registers values from PF PCIe register space */ +- hns3_direct_access_regs(hw, regs); ++ hns3_direct_access_regs(hw, regs, modules); + + /* fetching PF common registers values from firmware */ +- return hns3_get_regs_from_firmware(hw, regs); ++ return hns3_get_regs_from_firmware(hw, regs, modules); + } +-- +2.33.0 + diff --git a/0495-net-hns3-fix-integer-overflow.patch b/0495-net-hns3-fix-integer-overflow.patch new file mode 100644 index 0000000000000000000000000000000000000000..13affa369dc3745e48bec79f7c90ee7692ed8c52 --- /dev/null +++ b/0495-net-hns3-fix-integer-overflow.patch @@ -0,0 +1,39 @@ +From f6f7d9eda87c7c90963ab6580b1c796dd7aed9ec Mon Sep 17 00:00:00 2001 +From: Jie Hai +Date: Tue, 22 Oct 2024 12:01:12 +0800 +Subject: [PATCH 495/500] net/hns3: fix integer overflow + +[ upstream commit b1fefe40550836b58c4ec50dce14a6e6dbda8499 ] + +The patch fixes variable type in case of data truncation. + +Fixes: dd4b8bba785f ("net/hns3: support reporting names of registers") +Cc: stable@dpdk.org + +Signed-off-by: Jie Hai +Acked-by: Chengwen Feng +Acked-by: Huisong Li +Signed-off-by: chenyi +--- + drivers/net/hns3/hns3_regs.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/net/hns3/hns3_regs.c b/drivers/net/hns3/hns3_regs.c +index 8148a6327c..3d56098cc8 100644 +--- a/drivers/net/hns3/hns3_regs.c ++++ b/drivers/net/hns3/hns3_regs.c +@@ -1178,9 +1178,9 @@ hns3_direct_access_tqp_regs_help(struct hns3_hw *hw, struct rte_dev_reg_info *re + uint32_t modules, enum hns3_reg_modules idx) + { + const struct hns3_dirt_reg_entry *reg_list; +- uint16_t tqp_num, reg_offset; ++ uint32_t reg_num, i, j, reg_offset; + uint32_t *data = regs->data; +- uint32_t reg_num, i, j; ++ uint16_t tqp_num; + + if ((modules & HNS3_MODULE_MASK(idx)) == 0) + return; +-- +2.33.0 + diff --git a/0496-net-hns3-fix-pointer-offset-for-registers.patch b/0496-net-hns3-fix-pointer-offset-for-registers.patch new file mode 100644 index 0000000000000000000000000000000000000000..13aceca880c70e5ed6abe2fc4f8722f099ebe14e --- /dev/null +++ b/0496-net-hns3-fix-pointer-offset-for-registers.patch @@ -0,0 +1,54 @@ +From b5e02d8773c7d845271f77727ee346826c1acfbc Mon Sep 17 00:00:00 2001 +From: Jie Hai +Date: Tue, 22 Oct 2024 12:01:13 +0800 +Subject: [PATCH 496/500] net/hns3: fix pointer offset for registers + +[ upstream commit 013fdd2d7b319e6a35d966f375e33ee330d9ccb5 ] + +If the register values of multiple modules are obtained at a time, +the register values are incorrect because the data field to be filled +pointing to a wrong address. Update the pointer offset of data to +get the correct address. + +Fixes: dd4b8bba785f ("net/hns3: support reporting names of registers") +Cc: stable@dpdk.org + +Signed-off-by: Jie Hai +Acked-by: Chengwen Feng +Acked-by: Huisong Li +Signed-off-by: chenyi +--- + drivers/net/hns3/hns3_regs.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/net/hns3/hns3_regs.c b/drivers/net/hns3/hns3_regs.c +index 3d56098cc8..fa37c03f63 100644 +--- a/drivers/net/hns3/hns3_regs.c ++++ b/drivers/net/hns3/hns3_regs.c +@@ -1274,6 +1274,7 @@ hns3_get_dfx_regs(struct hns3_hw *hw, struct rte_dev_reg_info *regs, uint32_t mo + if (cmd_descs == NULL) + return -ENOMEM; + ++ data += regs->length; + for (i = 0; i < opcode_num; i++) { + opcode = hns3_dfx_reg_opcode_list[i]; + bd_num = bd_num_list[i]; +@@ -1285,7 +1286,6 @@ hns3_get_dfx_regs(struct hns3_hw *hw, struct rte_dev_reg_info *regs, uint32_t mo + if (ret) + break; + +- data += regs->length; + regs_num = hns3_dfx_reg_fetch_data(cmd_descs, bd_num, data); + if (regs_num != hns3_reg_lists[i].entry_num) { + hns3_err(hw, "Query register number differ from the list for module %s!", +@@ -1294,6 +1294,7 @@ hns3_get_dfx_regs(struct hns3_hw *hw, struct rte_dev_reg_info *regs, uint32_t mo + } + hns3_fill_dfx_regs_name(hw, regs, hns3_reg_lists[i].reg_list, regs_num); + regs->length += regs_num; ++ data += regs_num; + } + rte_free(cmd_descs); + +-- +2.33.0 + diff --git a/0497-net-hns3-fix-error-log.patch b/0497-net-hns3-fix-error-log.patch new file mode 100644 index 0000000000000000000000000000000000000000..284f6bd73bcd1f953ff6fc0c505c796005d873f3 --- /dev/null +++ b/0497-net-hns3-fix-error-log.patch @@ -0,0 +1,35 @@ +From 207a4560c9cc56ab7ff26b504836bd2a8e24ea6e Mon Sep 17 00:00:00 2001 +From: Jie Hai +Date: Wed, 23 Oct 2024 15:12:35 +0800 +Subject: [PATCH 497/500] net/hns3: fix error log + +[ upstream commit f58fd22240c27ea20cf41dd2aa15810712f518bf ] + +If register number obtained from firmware is different from the +register list driver hold, an error log occurs. The incorrect +use of `&&` makes this log inaccurate, change it to `&`. + +Fixes: 99d3bd8b85d3 ("net/hns3: support filtering registers by module names") + +Signed-off-by: Jie Hai +Signed-off-by: chenyi +--- + drivers/net/hns3/hns3_regs.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/net/hns3/hns3_regs.c b/drivers/net/hns3/hns3_regs.c +index fa37c03f63..37ac957e6c 100644 +--- a/drivers/net/hns3/hns3_regs.c ++++ b/drivers/net/hns3/hns3_regs.c +@@ -897,7 +897,7 @@ hns3_get_name_by_module(enum hns3_reg_modules module) + size_t i; + + for (i = 0; i < RTE_DIM(hns3_module_name_map); i++) { +- if (hns3_module_name_map[i].module && HNS3_MODULE_MASK(module) != 0) ++ if ((hns3_module_name_map[i].module & HNS3_MODULE_MASK(module)) != 0) + return hns3_module_name_map[i].name; + } + return "unknown"; +-- +2.33.0 + diff --git a/0498-net-hns3-remove-ROH-devices.patch b/0498-net-hns3-remove-ROH-devices.patch new file mode 100644 index 0000000000000000000000000000000000000000..c7a8ab4e2a366e513c5218b07b9164b85e83d523 --- /dev/null +++ b/0498-net-hns3-remove-ROH-devices.patch @@ -0,0 +1,67 @@ +From ed898c4c6397a40efa435b27daa0ae8736731bc7 Mon Sep 17 00:00:00 2001 +From: Dengdui Huang +Date: Sat, 26 Oct 2024 14:38:35 +0800 +Subject: [PATCH 498/500] net/hns3: remove ROH devices + +[ upstream commit feb4548ffd80bf249239d99bf9053ecf78f815d1 ] + +The devices added in commit 3f1436d7006c ("net/hns3: support new device") +is no longer available, so revert it. + +Fixes: 3f1436d7006c ("net/hns3: support new device") +Cc: stable@dpdk.org + +Signed-off-by: Dengdui Huang +Acked-by: Jie Hai +Signed-off-by: chenyi +--- + drivers/net/hns3/hns3_cmd.c | 4 +--- + drivers/net/hns3/hns3_ethdev.c | 2 -- + drivers/net/hns3/hns3_ethdev.h | 2 -- + 3 files changed, 1 insertion(+), 7 deletions(-) + +diff --git a/drivers/net/hns3/hns3_cmd.c b/drivers/net/hns3/hns3_cmd.c +index 001ff49b36..2c1664485b 100644 +--- a/drivers/net/hns3/hns3_cmd.c ++++ b/drivers/net/hns3/hns3_cmd.c +@@ -545,9 +545,7 @@ hns3_set_dcb_capability(struct hns3_hw *hw) + if (device_id == HNS3_DEV_ID_25GE_RDMA || + device_id == HNS3_DEV_ID_50GE_RDMA || + device_id == HNS3_DEV_ID_100G_RDMA_MACSEC || +- device_id == HNS3_DEV_ID_200G_RDMA || +- device_id == HNS3_DEV_ID_100G_ROH || +- device_id == HNS3_DEV_ID_200G_ROH) ++ device_id == HNS3_DEV_ID_200G_RDMA) + hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1); + } + +diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c +index 4d554a4cdb..2689f0f4d6 100644 +--- a/drivers/net/hns3/hns3_ethdev.c ++++ b/drivers/net/hns3/hns3_ethdev.c +@@ -6651,8 +6651,6 @@ static const struct rte_pci_id pci_id_hns3_map[] = { + { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) }, +- { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_ROH) }, +- { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_ROH) }, + { .vendor_id = 0, }, /* sentinel */ + }; + +diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h +index c190d5109b..00d226d71c 100644 +--- a/drivers/net/hns3/hns3_ethdev.h ++++ b/drivers/net/hns3/hns3_ethdev.h +@@ -28,9 +28,7 @@ + #define HNS3_DEV_ID_25GE_RDMA 0xA222 + #define HNS3_DEV_ID_50GE_RDMA 0xA224 + #define HNS3_DEV_ID_100G_RDMA_MACSEC 0xA226 +-#define HNS3_DEV_ID_100G_ROH 0xA227 + #define HNS3_DEV_ID_200G_RDMA 0xA228 +-#define HNS3_DEV_ID_200G_ROH 0xA22C + #define HNS3_DEV_ID_100G_VF 0xA22E + #define HNS3_DEV_ID_100G_RDMA_PFC_VF 0xA22F + +-- +2.33.0 + diff --git a/0499-net-hns3-fix-error-code-for-repeatedly-create-counte.patch b/0499-net-hns3-fix-error-code-for-repeatedly-create-counte.patch new file mode 100644 index 0000000000000000000000000000000000000000..f72aab6376d0e8336ee8db64c217ac9b33e67274 --- /dev/null +++ b/0499-net-hns3-fix-error-code-for-repeatedly-create-counte.patch @@ -0,0 +1,38 @@ +From 2119d588ef4f91c98c10e185f6ea20c4dbe0193c Mon Sep 17 00:00:00 2001 +From: Dengdui Huang +Date: Thu, 7 Nov 2024 19:56:44 +0800 +Subject: [PATCH 499/500] net/hns3: fix error code for repeatedly create + counter + +[ upstream commit 585f1f68f18c7acbc4f920053cbf4ba888e0c271 ] + +Return EINVAL instead of ENOSPC when the same counter ID is +used for multiple times to create a counter. + +Fixes: fcba820d9b9e ("net/hns3: support flow director") +Cc: stable@dpdk.org + +Signed-off-by: Dengdui Huang +Signed-off-by: Jie Hai +Acked-by: Stephen Hemminger +Signed-off-by: chenyi +--- + drivers/net/hns3/hns3_flow.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/net/hns3/hns3_flow.c b/drivers/net/hns3/hns3_flow.c +index 31fc74ff78..429edae56f 100644 +--- a/drivers/net/hns3/hns3_flow.c ++++ b/drivers/net/hns3/hns3_flow.c +@@ -283,7 +283,7 @@ hns3_counter_new(struct rte_eth_dev *dev, uint32_t indirect, uint32_t id, + cnt = hns3_counter_lookup(dev, id); + if (cnt) { + if (!cnt->indirect || cnt->indirect != indirect) +- return rte_flow_error_set(error, ENOTSUP, ++ return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ACTION_CONF, + cnt, + "Counter id is used, indirect flag not match"); +-- +2.33.0 + diff --git a/0500-net-hns3-fix-fully-use-hardware-flow-director-table.patch b/0500-net-hns3-fix-fully-use-hardware-flow-director-table.patch new file mode 100644 index 0000000000000000000000000000000000000000..9c9d248618c61db6274e8e79dfb9d16eaca3cd6b --- /dev/null +++ b/0500-net-hns3-fix-fully-use-hardware-flow-director-table.patch @@ -0,0 +1,41 @@ +From f27ac5f649c318e3b2b847ec710b3a6986384dcf Mon Sep 17 00:00:00 2001 +From: Dengdui Huang +Date: Thu, 7 Nov 2024 19:56:45 +0800 +Subject: [PATCH 500/500] net/hns3: fix fully use hardware flow director table + +[ upstream commit b8e60c33168a2999604c17322dd0198a6746428f ] + +The hns3 driver checks whether the flow rule is repeatedly inserted +based on rte_hash. Currently, the rte_hash extendable bucket table +feature is not enabled. When there are many hash conflicts, the hash +table space cannot be fully used. So the flow rule maybe cannot be +inserted even if the hardware flow director table there are still free. +This patch fix it by enabling the rte_hash extensible bucket table +feature. + +Fixes: fcba820d9b9e ("net/hns3: support flow director") +Cc: stable@dpdk.org + +Signed-off-by: Dengdui Huang +Signed-off-by: Jie Hai +Acked-by: Stephen Hemminger +Signed-off-by: chenyi +--- + drivers/net/hns3/hns3_fdir.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/net/hns3/hns3_fdir.c b/drivers/net/hns3/hns3_fdir.c +index d100e58d10..75a200c713 100644 +--- a/drivers/net/hns3/hns3_fdir.c ++++ b/drivers/net/hns3/hns3_fdir.c +@@ -836,6 +836,7 @@ int hns3_fdir_filter_init(struct hns3_adapter *hns) + .key_len = sizeof(struct hns3_fdir_key_conf), + .hash_func = rte_hash_crc, + .hash_func_init_val = 0, ++ .extra_flag = RTE_HASH_EXTRA_FLAGS_EXT_TABLE, + }; + int ret; + +-- +2.33.0 + diff --git a/dpdk.spec b/dpdk.spec index b92360c11f2add3df3380d506b8af0d96235cc28..0f071bb8ba278285831c8a662a583c0b903882b6 100644 --- a/dpdk.spec +++ b/dpdk.spec @@ -1,6 +1,6 @@ Name: dpdk Version: 21.11 -Release: 81 +Release: 82 Packager: packaging@6wind.com URL: http://dpdk.org %global source_version 21.11 @@ -521,6 +521,21 @@ Patch9484: 0484-bus-pci-fix-UIO-resource-mapping-in-secondary-proces.patch Patch9485: 0485-net-af_xdp-fix-getsockopt-ENOTSOCK-error.patch Patch9486: 0486-CVE-2024-11614-net-virtio-fix-Rx-checksum-calculation.patch +Patch9487: 0487-net-hns3-support-more-VLAN-fields-matching.patch +Patch9488: 0488-net-hns3-dump-queue-head-and-tail-pointer-info.patch +Patch9489: 0489-net-hns3-remove-some-basic-address-dump.patch +Patch9490: 0490-net-hns3-fix-dump-counter-of-registers.patch +Patch9491: 0491-net-hns3-remove-separators-between-register-module.patch +Patch9492: 0492-net-hns3-refactor-register-dump.patch +Patch9493: 0493-net-hns3-support-reporting-names-of-registers.patch +Patch9494: 0494-net-hns3-support-filtering-registers-by-module-names.patch +Patch9495: 0495-net-hns3-fix-integer-overflow.patch +Patch9496: 0496-net-hns3-fix-pointer-offset-for-registers.patch +Patch9497: 0497-net-hns3-fix-error-log.patch +Patch9498: 0498-net-hns3-remove-ROH-devices.patch +Patch9499: 0499-net-hns3-fix-error-code-for-repeatedly-create-counte.patch +Patch9500: 0500-net-hns3-fix-fully-use-hardware-flow-director-table.patch + Summary: Data Plane Development Kit core Group: System Environment/Libraries License: BSD and LGPLv2 and GPLv2 @@ -687,6 +702,22 @@ fi /usr/sbin/depmod %changelog +* Sat Dec 28 2024 chenyi - 21.11-82 + Sync some patches from upstream about bugfix, modifies are as follow: +- net/hns3: fix error code for repeatedly create counter +- net/hns3: remove ROH devices +- net/hns3: fix error log +- net/hns3: fix pointer offset for registers +- net/hns3: fix integer overflow +- net/hns3: support filtering registers by module names +- net/hns3: support reporting names of registers +- net/hns3: refactor register dump +- net/hns3: remove separators between register module +- net/hns3: fix dump counter of registers +- net/hns3: remove some basic address dump +- net/hns3: dump queue head and tail pointer info +- net/hns3: support more VLAN fields matching + * Tue Dec 24 2024 jiangheng - 21.11-81 - net/virtio: fix Rx checksum calculation