diff --git a/1000-add-LoongArch-support-not-upstream-modify-files.patch b/1000-add-LoongArch-support-not-upstream-modify-files.patch
new file mode 100644
index 0000000000000000000000000000000000000000..4bec7585afb2827ccb712fc6676799744368985f
--- /dev/null
+++ b/1000-add-LoongArch-support-not-upstream-modify-files.patch
@@ -0,0 +1,2648 @@
+diff --git a/.azurepipelines/Ubuntu-GCC5.yml b/.azurepipelines/Ubuntu-GCC5.yml
+index 7cd67c9..ceaa3e4 100644
+--- a/.azurepipelines/Ubuntu-GCC5.yml
++++ b/.azurepipelines/Ubuntu-GCC5.yml
+@@ -15,5 +15,5 @@ jobs:
+ parameters:
+ tool_chain_tag: 'GCC5'
+ vm_image: 'ubuntu-latest'
+- arch_list: "IA32,X64,ARM,AARCH64,RISCV64"
++ arch_list: "IA32,X64,ARM,AARCH64,RISCV64,LOONGARCH64"
+
+diff --git a/.pytool/CISettings.py b/.pytool/CISettings.py
+index b337d04..413f25c 100644
+--- a/.pytool/CISettings.py
++++ b/.pytool/CISettings.py
+@@ -66,7 +66,8 @@ class Settings(CiBuildSettingsManager, UpdateSettingsManager, SetupSettingsManag
+ "X64",
+ "ARM",
+ "AARCH64",
+- "RISCV64")
++ "RISCV64",
++ "LOONGARCH64")
+
+ def GetTargetsSupported(self):
+ ''' return iterable of edk2 target tags supported by this build '''
+@@ -138,6 +139,8 @@ class Settings(CiBuildSettingsManager, UpdateSettingsManager, SetupSettingsManag
+ scopes += ("gcc_arm_linux",)
+ if "RISCV64" in self.ActualArchitectures:
+ scopes += ("gcc_riscv64_unknown",)
++ if "LOONGARCH64" in self.ActualArchitectures:
++ scopes += ("gcc_loongarch64_unknown_linux",)
+
+ return scopes
+
+diff --git a/BaseTools/Conf/tools_def.template b/BaseTools/Conf/tools_def.template
+index 933b316..8a0a9d0 100755
+--- a/BaseTools/Conf/tools_def.template
++++ b/BaseTools/Conf/tools_def.template
+@@ -4,6 +4,7 @@
+ # Portions copyright (c) 2011 - 2019, ARM Ltd. All rights reserved.
+ # Copyright (c) 2015, Hewlett-Packard Development Company, L.P.
+ # (C) Copyright 2020, Hewlett Packard Enterprise Development LP
++# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
+ # Copyright (c) Microsoft Corporation
+ #
+ # SPDX-License-Identifier: BSD-2-Clause-Patent
+@@ -267,7 +268,7 @@ DEFINE DTC_BIN = ENV(DTC_PREFIX)dtc
+ # Intel(r) ACPI Compiler from
+ # https://acpica.org/downloads
+ # GCC5 -Linux,Windows- Requires:
+-# GCC 5 with LTO support, targeting x86_64-linux-gnu, aarch64-linux-gnu, arm-linux-gnueabi or riscv64-linux-gnu
++# GCC 5 with LTO support, targeting x86_64-linux-gnu, aarch64-linux-gnu, arm-linux-gnueabi, riscv64-linux-gnu or loongarch64-linux-gnu
+ # Optional:
+ # Required to build platforms or ACPI tables:
+ # Intel(r) ACPI Compiler from
+@@ -1922,6 +1923,7 @@ DEFINE GCC_ALL_CC_FLAGS = -g -Os -fshort-wchar -fno-builtin -fno-stri
+ DEFINE GCC_IA32_CC_FLAGS = DEF(GCC_ALL_CC_FLAGS) -m32 -malign-double -freorder-blocks -freorder-blocks-and-partition -O2 -mno-stack-arg-probe
+ DEFINE GCC_X64_CC_FLAGS = DEF(GCC_ALL_CC_FLAGS) -mno-red-zone -Wno-address -mno-stack-arg-probe
+ DEFINE GCC_ARM_CC_FLAGS = DEF(GCC_ALL_CC_FLAGS) -mlittle-endian -mabi=aapcs -fno-short-enums -funsigned-char -ffunction-sections -fdata-sections -fomit-frame-pointer -Wno-address -mthumb -mfloat-abi=soft -fno-pic -fno-pie
++DEFINE GCC_LOONGARCH64_CC_FLAGS = DEF(GCC_ALL_CC_FLAGS) -mabi=lp64d -fno-asynchronous-unwind-tables -fno-plt -Wno-address -fno-short-enums -fsigned-char -ffunction-sections -fdata-sections
+ DEFINE GCC_ARM_CC_XIPFLAGS = -mno-unaligned-access
+ DEFINE GCC_AARCH64_CC_FLAGS = DEF(GCC_ALL_CC_FLAGS) -mlittle-endian -fno-short-enums -fverbose-asm -funsigned-char -ffunction-sections -fdata-sections -Wno-address -fno-asynchronous-unwind-tables -fno-unwind-tables -fno-pic -fno-pie -ffixed-x18
+ DEFINE GCC_AARCH64_CC_XIPFLAGS = -mstrict-align -mgeneral-regs-only
+@@ -1929,12 +1931,15 @@ DEFINE GCC_DLINK_FLAGS_COMMON = -nostdlib --pie
+ DEFINE GCC_DLINK2_FLAGS_COMMON = -Wl,--script=$(EDK_TOOLS_PATH)/Scripts/GccBase.lds
+ DEFINE GCC_IA32_X64_DLINK_COMMON = DEF(GCC_DLINK_FLAGS_COMMON) --gc-sections
+ DEFINE GCC_ARM_AARCH64_DLINK_COMMON= -Wl,--emit-relocs -nostdlib -Wl,--gc-sections -u $(IMAGE_ENTRY_POINT) -Wl,-e,$(IMAGE_ENTRY_POINT),-Map,$(DEST_DIR_DEBUG)/$(BASE_NAME).map
++DEFINE GCC_LOONGARCH64_DLINK_COMMON= -Wl,--emit-relocs -nostdlib -Wl,--gc-sections -u $(IMAGE_ENTRY_POINT) -Wl,-e,$(IMAGE_ENTRY_POINT),-Map,$(DEST_DIR_DEBUG)/$(BASE_NAME).map
+ DEFINE GCC_ARM_DLINK_FLAGS = DEF(GCC_ARM_AARCH64_DLINK_COMMON) -z common-page-size=0x20 -Wl,--pic-veneer
+ DEFINE GCC_AARCH64_DLINK_FLAGS = DEF(GCC_ARM_AARCH64_DLINK_COMMON) -z common-page-size=0x20
++DEFINE GCC_LOONGARCH64_DLINK_FLAGS = DEF(GCC_LOONGARCH64_DLINK_COMMON) -z common-page-size=0x20
+ DEFINE GCC_ARM_AARCH64_ASLDLINK_FLAGS = -Wl,--defsym=PECOFF_HEADER_SIZE=0 DEF(GCC_DLINK2_FLAGS_COMMON) -z common-page-size=0x20
+ DEFINE GCC_IA32_X64_ASLDLINK_FLAGS = DEF(GCC_IA32_X64_DLINK_COMMON) --entry _ReferenceAcpiTable -u $(IMAGE_ENTRY_POINT)
+ DEFINE GCC_ARM_ASLDLINK_FLAGS = DEF(GCC_ARM_DLINK_FLAGS) -Wl,--entry,ReferenceAcpiTable -u $(IMAGE_ENTRY_POINT) DEF(GCC_ARM_AARCH64_ASLDLINK_FLAGS)
+ DEFINE GCC_AARCH64_ASLDLINK_FLAGS = DEF(GCC_AARCH64_DLINK_FLAGS) -Wl,--entry,ReferenceAcpiTable -u $(IMAGE_ENTRY_POINT) DEF(GCC_ARM_AARCH64_ASLDLINK_FLAGS)
++DEFINE GCC_LOONGARCH64_ASLDLINK_FLAGS = DEF(GCC_LOONGARCH64_DLINK_FLAGS) -Wl,--entry,ReferenceAcpiTable -u $(IMAGE_ENTRY_POINT)
+ DEFINE GCC_IA32_X64_DLINK_FLAGS = DEF(GCC_IA32_X64_DLINK_COMMON) --entry _$(IMAGE_ENTRY_POINT) --file-alignment 0x20 --section-alignment 0x20 -Map $(DEST_DIR_DEBUG)/$(BASE_NAME).map
+ DEFINE GCC_ASM_FLAGS = -c -x assembler -imacros AutoGen.h
+ DEFINE GCC_PP_FLAGS = -E -x assembler-with-cpp -include AutoGen.h
+@@ -1943,11 +1948,12 @@ DEFINE GCC_ASLPP_FLAGS = -x c -E -include AutoGen.h
+ DEFINE GCC_ASLCC_FLAGS = -x c
+ DEFINE GCC_WINDRES_FLAGS = -J rc -O coff
+ DEFINE GCC_DTCPP_FLAGS = -E -x assembler-with-cpp -imacros AutoGen.h -nostdinc -undef
+-DEFINE GCC_IA32_RC_FLAGS = -I binary -O elf32-i386 -B i386 --rename-section .data=.hii
+-DEFINE GCC_X64_RC_FLAGS = -I binary -O elf64-x86-64 -B i386 --rename-section .data=.hii
+-DEFINE GCC_ARM_RC_FLAGS = -I binary -O elf32-littlearm -B arm --rename-section .data=.hii
+-DEFINE GCC_AARCH64_RC_FLAGS = -I binary -O elf64-littleaarch64 -B aarch64 --rename-section .data=.hii
+-DEFINE GCC_RISCV64_RC_FLAGS = -I binary -O elf64-littleriscv -B riscv --rename-section .data=.hii
++DEFINE GCC_IA32_RC_FLAGS = -I binary -O elf32-i386 -B i386 --rename-section .data=.hii
++DEFINE GCC_X64_RC_FLAGS = -I binary -O elf64-x86-64 -B i386 --rename-section .data=.hii
++DEFINE GCC_ARM_RC_FLAGS = -I binary -O elf32-littlearm -B arm --rename-section .data=.hii
++DEFINE GCC_AARCH64_RC_FLAGS = -I binary -O elf64-littleaarch64 -B aarch64 --rename-section .data=.hii
++DEFINE GCC_RISCV64_RC_FLAGS = -I binary -O elf64-littleriscv -B riscv --rename-section .data=.hii
++DEFINE GCC_LOONGARCH64_RC_FLAGS = -I binary -O elf64-loongarch -B loongarch64 --rename-section .data=.hii
+
+ # GCC Build Flag for included header file list generation
+ DEFINE GCC_DEPS_FLAGS = -MMD -MF $@.deps
+@@ -2037,6 +2043,14 @@ DEFINE GCC5_RISCV64_CC_FLAGS = DEF(GCC5_RISCV_ALL_CC_FLAGS) DEF(GC
+ DEFINE GCC5_RISCV64_DLINK_FLAGS = DEF(GCC5_RISCV_ALL_DLINK_FLAGS) -Wl,-melf64lriscv,--oformat=elf64-littleriscv,--no-relax
+ DEFINE GCC5_RISCV64_DLINK2_FLAGS = DEF(GCC5_RISCV_ALL_DLINK2_FLAGS)
+ DEFINE GCC5_RISCV64_ASM_FLAGS = DEF(GCC5_RISCV_ALL_ASM_FLAGS) -march=DEF(GCC5_RISCV64_ARCH) -mcmodel=medany -mabi=lp64
++
++DEFINE GCC5_LOONGARCH64_CC_FLAGS = DEF(GCC_LOONGARCH64_CC_FLAGS) -march=loongarch64 -mno-memcpy -Werror -Wno-maybe-uninitialized -Wno-stringop-overflow -Wno-pointer-to-int-cast -no-pie -fno-stack-protector -mno-explicit-relocs
++DEFINE GCC5_LOONGARCH64_DLINK_FLAGS = DEF(GCC_LOONGARCH64_DLINK_FLAGS)
++DEFINE GCC5_LOONGARCH64_DLINK2_FLAGS = DEF(GCC_DLINK2_FLAGS_COMMON) -Wl,--defsym=PECOFF_HEADER_SIZE=0x228
++DEFINE GCC5_LOONGARCH64_ASLDLINK_FLAGS = DEF(GCC_LOONGARCH64_ASLDLINK_FLAGS) DEF(GCC5_LOONGARCH64_DLINK2_FLAGS)
++DEFINE GCC5_LOONGARCH64_ASM_FLAGS = -x assembler-with-cpp -mabi=lp64d -march=loongarch64 -fno-builtin -c -Wall -mno-explicit-relocs
++DEFINE GCC5_LOONGARCH64_PP_FLAGS = -mabi=lp64d -march=loongarch64 DEF(GCC_PP_FLAGS)
++
+ DEFINE GCC_PP_FLAGS = -E -x assembler-with-cpp -include AutoGen.h DEF(GCC5_RISCV_OPENSBI_TYPES)
+
+ ####################################################################################
+@@ -2514,6 +2528,34 @@ RELEASE_GCC5_AARCH64_DLINK_XIPFLAGS = -z common-page-size=0x20
+ *_GCC5_RISCV64_RC_FLAGS = DEF(GCC_RISCV64_RC_FLAGS)
+ *_GCC5_RISCV64_OBJCOPY_FLAGS =
+
++##################
++# GCC5 LOONGARCH64 definitions
++##################
++*_GCC5_LOONGARCH64_OBJCOPY_PATH = ENV(GCC5_LOONGARCH64_PREFIX)objcopy
++*_GCC5_LOONGARCH64_CC_PATH = ENV(GCC5_LOONGARCH64_PREFIX)gcc
++*_GCC5_LOONGARCH64_SLINK_PATH = ENV(GCC5_LOONGARCH64_PREFIX)gcc-ar
++*_GCC5_LOONGARCH64_DLINK_PATH = ENV(GCC5_LOONGARCH64_PREFIX)gcc
++*_GCC5_LOONGARCH64_ASLDLINK_PATH = ENV(GCC5_LOONGARCH64_PREFIX)gcc
++*_GCC5_LOONGARCH64_ASM_PATH = ENV(GCC5_LOONGARCH64_PREFIX)gcc
++*_GCC5_LOONGARCH64_PP_PATH = ENV(GCC5_LOONGARCH64_PREFIX)gcc
++*_GCC5_LOONGARCH64_VFRPP_PATH = ENV(GCC5_LOONGARCH64_PREFIX)gcc
++*_GCC5_LOONGARCH64_ASLCC_PATH = ENV(GCC5_LOONGARCH64_PREFIX)gcc
++*_GCC5_LOONGARCH64_ASLPP_PATH = ENV(GCC5_LOONGARCH64_PREFIX)gcc
++*_GCC5_LOONGARCH64_RC_PATH = ENV(GCC5_LOONGARCH64_PREFIX)objcopy
++
++*_GCC5_LOONGARCH64_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS)
++*_GCC5_LOONGARCH64_ASLDLINK_FLAGS = DEF(GCC5_LOONGARCH64_ASLDLINK_FLAGS)
++*_GCC5_LOONGARCH64_ASM_FLAGS = DEF(GCC5_LOONGARCH64_ASM_FLAGS)
++*_GCC5_LOONGARCH64_DLINK_FLAGS = DEF(GCC5_LOONGARCH64_DLINK_FLAGS)
++*_GCC5_LOONGARCH64_DLINK2_FLAGS = DEF(GCC5_LOONGARCH64_DLINK2_FLAGS)
++*_GCC5_LOONGARCH64_RC_FLAGS = DEF(GCC_LOONGARCH64_RC_FLAGS)
++*_GCC5_LOONGARCH64_OBJCOPY_FLAGS =
++*_GCC5_LOONGARCH64_NASM_FLAGS = -f elf32
++*_GCC5_LOONGARCH64_PP_FLAGS = DEF(GCC5_LOONGARCH64_PP_FLAGS)
++
++DEBUG_GCC5_LOONGARCH64_CC_FLAGS = DEF(GCC5_LOONGARCH64_CC_FLAGS)
++RELEASE_GCC5_LOONGARCH64_CC_FLAGS = DEF(GCC5_LOONGARCH64_CC_FLAGS) -Wno-unused-but-set-variable -Wno-unused-variable
++
+ ####################################################################################
+ #
+ # CLANG35 - This configuration is used to compile under Linux to produce
+diff --git a/BaseTools/Plugin/LinuxGcc5ToolChain/LinuxGcc5ToolChain.py b/BaseTools/Plugin/LinuxGcc5ToolChain/LinuxGcc5ToolChain.py
+index 8107543..6216a07 100644
+--- a/BaseTools/Plugin/LinuxGcc5ToolChain/LinuxGcc5ToolChain.py
++++ b/BaseTools/Plugin/LinuxGcc5ToolChain/LinuxGcc5ToolChain.py
+@@ -5,6 +5,7 @@
+ #
+ # Copyright (c) Microsoft Corporation
+ # Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
++# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
+ # SPDX-License-Identifier: BSD-2-Clause-Patent
+ ##
+ import os
+@@ -43,6 +44,12 @@ class LinuxGcc5ToolChain(IUefiBuildPlugin):
+ self.Logger.critical("Failed in check riscv64")
+ return ret
+
++ # Check LoongArch64 compiler
++ ret = self._check_loongarch64()
++ if ret != 0:
++ self.Logger.critical("Failed in check loongarch64")
++ return ret
++
+ return 0
+
+ def _check_arm(self):
+@@ -121,3 +128,27 @@ class LinuxGcc5ToolChain(IUefiBuildPlugin):
+ shell_environment.GetEnvironment().set_shell_var("LD_LIBRARY_PATH", prefix)
+
+ return 0
++
++ def _check_loongarch64(self):
++ # check to see if full path already configured
++ if shell_environment.GetEnvironment().get_shell_var("GCC5_LOONGARCH64_PREFIX") is not None:
++ self.Logger.info("GCC5_LOONGARCH64_PREFIX is already set.")
++
++ else:
++ # now check for install dir. If set then set the Prefix
++ install_path = shell_environment.GetEnvironment(
++ ).get_shell_var("GCC5_LOONGARCH64_INSTALL")
++ if install_path is None:
++ return 0
++
++ # make GCC5_LOONGARCH64_PREFIX to align with tools_def.txt
++ prefix = os.path.join(install_path, "bin", "loongarch64-unknown-linux-gnu-")
++ shell_environment.GetEnvironment().set_shell_var("GCC5_LOONGARCH64_PREFIX", prefix)
++
++ # now confirm it exists
++ if not os.path.exists(shell_environment.GetEnvironment().get_shell_var("GCC5_LOONGARCH64_PREFIX") + "gcc"):
++ self.Logger.error(
++ "Path for GCC5_LOONGARCH64_PREFIX toolchain is invalid")
++ return -2
++
++ return 0
+\ No newline at end of file
+diff --git a/BaseTools/Source/C/Common/BasePeCoff.c b/BaseTools/Source/C/Common/BasePeCoff.c
+index 62fbb29..5fa0cde 100644
+--- a/BaseTools/Source/C/Common/BasePeCoff.c
++++ b/BaseTools/Source/C/Common/BasePeCoff.c
+@@ -68,6 +68,14 @@ PeCoffLoaderRelocateRiscVImage (
+ IN UINT64 Adjust
+ );
+
++RETURN_STATUS
++PeCoffLoaderRelocateLoongArch64Image (
++ IN UINT16 *Reloc,
++ IN OUT CHAR8 *Fixup,
++ IN OUT CHAR8 **FixupData,
++ IN UINT64 Adjust
++ );
++
+ STATIC
+ RETURN_STATUS
+ PeCoffLoaderGetPeHeader (
+@@ -184,7 +192,8 @@ Returns:
+ ImageContext->Machine != EFI_IMAGE_MACHINE_ARMT && \
+ ImageContext->Machine != EFI_IMAGE_MACHINE_EBC && \
+ ImageContext->Machine != EFI_IMAGE_MACHINE_AARCH64 && \
+- ImageContext->Machine != EFI_IMAGE_MACHINE_RISCV64) {
++ ImageContext->Machine != EFI_IMAGE_MACHINE_RISCV64 && \
++ ImageContext->Machine != EFI_IMAGE_MACHINE_LOONGARCH64) {
+ if (ImageContext->Machine == IMAGE_FILE_MACHINE_ARM) {
+ //
+ // There are two types of ARM images. Pure ARM and ARM/Thumb.
+@@ -815,6 +824,9 @@ Returns:
+ case EFI_IMAGE_MACHINE_RISCV64:
+ Status = PeCoffLoaderRelocateRiscVImage (Reloc, Fixup, &FixupData, Adjust);
+ break;
++ case EFI_IMAGE_MACHINE_LOONGARCH64:
++ Status = PeCoffLoaderRelocateLoongArch64Image (Reloc, Fixup, &FixupData, Adjust);
++ break;
+ default:
+ Status = RETURN_UNSUPPORTED;
+ break;
+diff --git a/BaseTools/Source/C/Common/PeCoffLoaderEx.c b/BaseTools/Source/C/Common/PeCoffLoaderEx.c
+index 799f282..8a4a869 100644
+--- a/BaseTools/Source/C/Common/PeCoffLoaderEx.c
++++ b/BaseTools/Source/C/Common/PeCoffLoaderEx.c
+@@ -332,3 +332,81 @@ PeCoffLoaderRelocateArmImage (
+
+ return RETURN_SUCCESS;
+ }
++
++/**
++ Performs a LoongArch specific relocation fixup.
++
++ @param[in] Reloc Pointer to the relocation record.
++ @param[in, out] Fixup Pointer to the address to fix up.
++ @param[in, out] FixupData Pointer to a buffer to log the fixups.
++ @param[in] Adjust The offset to adjust the fixup.
++
++ @return Status code.
++**/
++RETURN_STATUS
++PeCoffLoaderRelocateLoongArch64Image (
++ IN UINT16 *Reloc,
++ IN OUT CHAR8 *Fixup,
++ IN OUT CHAR8 **FixupData,
++ IN UINT64 Adjust
++ )
++{
++ UINT8 RelocType;
++ UINT64 Value;
++ UINT64 Tmp1;
++ UINT64 Tmp2;
++
++ RelocType = ((*Reloc) >> 12);
++ Value = 0;
++ Tmp1 = 0;
++ Tmp2 = 0;
++
++ switch (RelocType) {
++ case EFI_IMAGE_REL_BASED_LOONGARCH64_MARK_LA:
++ // The next four instructions are used to load a 64 bit address, relocate all of them
++ Value = (*(UINT32 *)Fixup & 0x1ffffe0) << 7 | // lu12i.w 20bits from bit5
++ (*((UINT32 *)Fixup + 1) & 0x3ffc00) >> 10; // ori 12bits from bit10
++ Tmp1 = *((UINT32 *)Fixup + 2) & 0x1ffffe0; // lu32i.d 20bits from bit5
++ Tmp2 = *((UINT32 *)Fixup + 3) & 0x3ffc00; // lu52i.d 12bits from bit10
++ Value = Value | (Tmp1 << 27) | (Tmp2 << 42);
++ Value += Adjust;
++
++ *(UINT32 *)Fixup = (*(UINT32 *)Fixup & ~0x1ffffe0) | (((Value >> 12) & 0xfffff) << 5);
++ if (*FixupData != NULL) {
++ *FixupData = ALIGN_POINTER (*FixupData, sizeof (UINT32));
++ *(UINT32 *)(*FixupData) = *(UINT32 *)Fixup;
++ *FixupData = *FixupData + sizeof (UINT32);
++ }
++
++ Fixup += sizeof (UINT32);
++ *(UINT32 *)Fixup = (*(UINT32 *)Fixup & ~0x3ffc00) | ((Value & 0xfff) << 10);
++ if (*FixupData != NULL) {
++ *FixupData = ALIGN_POINTER (*FixupData, sizeof (UINT32));
++ *(UINT32 *)(*FixupData) = *(UINT32 *)Fixup;
++ *FixupData = *FixupData + sizeof (UINT32);
++ }
++
++ Fixup += sizeof (UINT32);
++ *(UINT32 *)Fixup = (*(UINT32 *)Fixup & ~0x1ffffe0) | (((Value >> 32) & 0xfffff) << 5);
++ if (*FixupData != NULL) {
++ *FixupData = ALIGN_POINTER (*FixupData, sizeof (UINT32));
++ *(UINT32 *)(*FixupData) = *(UINT32 *)Fixup;
++ *FixupData = *FixupData + sizeof (UINT32);
++ }
++
++ Fixup += sizeof (UINT32);
++ *(UINT32 *)Fixup = (*(UINT32 *)Fixup & ~0x3ffc00) | (((Value >> 52) & 0xfff) << 10);
++ if (*FixupData != NULL) {
++ *FixupData = ALIGN_POINTER (*FixupData, sizeof (UINT32));
++ *(UINT32 *)(*FixupData) = *(UINT32 *)Fixup;
++ *FixupData = *FixupData + sizeof (UINT32);
++ }
++
++ break;
++ default:
++ Error (NULL, 0, 3000, "", "PeCoffLoaderRelocateLoongArch64Image: Fixup[0x%x] Adjust[0x%llx] *Reloc[0x%x], type[0x%x].", *(UINT32 *)Fixup, Adjust, *Reloc, RelocType);
++ return RETURN_UNSUPPORTED;
++ }
++
++ return RETURN_SUCCESS;
++}
+\ No newline at end of file
+diff --git a/BaseTools/Source/C/GNUmakefile b/BaseTools/Source/C/GNUmakefile
+index 464f432..49db834 100644
+--- a/BaseTools/Source/C/GNUmakefile
++++ b/BaseTools/Source/C/GNUmakefile
+@@ -29,6 +29,9 @@ ifndef HOST_ARCH
+ ifneq (,$(findstring riscv64,$(uname_m)))
+ HOST_ARCH=RISCV64
+ endif
++ ifneq (,$(findstring loongarch64,$(uname_m)))
++ HOST_ARCH=LOONGARCH64
++ endif
+ ifndef HOST_ARCH
+ $(info Could not detected HOST_ARCH from uname results)
+ $(error HOST_ARCH is not defined!)
+diff --git a/BaseTools/Source/C/GenFv/GenFvInternalLib.c b/BaseTools/Source/C/GenFv/GenFvInternalLib.c
+index 6e296b8..1cdab8e 100644
+--- a/BaseTools/Source/C/GenFv/GenFvInternalLib.c
++++ b/BaseTools/Source/C/GenFv/GenFvInternalLib.c
+@@ -5,6 +5,7 @@ Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.
+ Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
+ Portions Copyright (c) 2016 HP Development Company, L.P.
+ Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
++Portions Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ **/
+@@ -39,6 +40,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ BOOLEAN mArm = FALSE;
+ BOOLEAN mRiscV = FALSE;
++BOOLEAN mLoongArch = FALSE;
+ STATIC UINT32 MaxFfsAlignment = 0;
+ BOOLEAN VtfFileFlag = FALSE;
+
+@@ -2396,6 +2398,91 @@ Returns:
+ return EFI_SUCCESS;
+ }
+
++EFI_STATUS
++UpdateLoongArchResetVectorIfNeeded (
++ IN MEMORY_FILE *FvImage,
++ IN FV_INFO *FvInfo
++ )
++/*++
++Routine Description:
++ This parses the FV looking for SEC and patches that address into the
++ beginning of the FV header.
++ For LoongArch ISA, the reset vector is at 0x1c000000.
++ We relocate it to SecCoreEntry and copy the ResetVector code to the
++ beginning of the FV.
++Arguments:
++ FvImage Memory file for the FV memory image
++ FvInfo Information read from INF file.
++Returns:
++ EFI_SUCCESS Function Completed successfully.
++ EFI_ABORTED Error encountered.
++ EFI_INVALID_PARAMETER A required parameter was NULL.
++ EFI_NOT_FOUND PEI Core file not found.
++--*/
++{
++ EFI_STATUS Status;
++ EFI_FILE_SECTION_POINTER SecPe32;
++ BOOLEAN UpdateVectorSec = FALSE;
++ UINT16 MachineType = 0;
++ EFI_PHYSICAL_ADDRESS SecCoreEntryAddress = 0;
++
++ //
++ // Verify input parameters
++ //
++ if (FvImage == NULL || FvInfo == NULL) {
++ return EFI_INVALID_PARAMETER;
++ }
++
++ //
++ // Locate an SEC Core instance and if found extract the machine type and entry point address
++ //
++ Status = FindCorePeSection(FvImage->FileImage, FvInfo->Size, EFI_FV_FILETYPE_SECURITY_CORE, &SecPe32);
++ if (!EFI_ERROR(Status)) {
++
++ Status = GetCoreMachineType(SecPe32, &MachineType);
++ if (EFI_ERROR(Status)) {
++ Error(NULL, 0, 3000, "Invalid", "Could not get the PE32 machine type for SEC Core.");
++ return EFI_ABORTED;
++ }
++
++ Status = GetCoreEntryPointAddress(FvImage->FileImage, FvInfo, SecPe32, &SecCoreEntryAddress);
++ if (EFI_ERROR(Status)) {
++ Error(NULL, 0, 3000, "Invalid", "Could not get the PE32 entry point address for SEC Core.");
++ return EFI_ABORTED;
++ }
++
++ UpdateVectorSec = TRUE;
++ }
++
++ if (!UpdateVectorSec)
++ return EFI_SUCCESS;
++
++ if (MachineType == EFI_IMAGE_MACHINE_LOONGARCH64) {
++ UINT32 ResetVector[1];
++
++ memset(ResetVector, 0, sizeof (ResetVector));
++
++ /* if we found an SEC core entry point then generate a branch instruction */
++ if (UpdateVectorSec) {
++ VerboseMsg("UpdateLoongArchResetVectorIfNeeded updating LOONGARCH64 SEC vector");
++
++ ResetVector[0] = ((SecCoreEntryAddress - FvInfo->BaseAddress) & 0x3FFFFFF) >> 2;
++ ResetVector[0] = ((ResetVector[0] & 0x0FFFF) << 10) | ((ResetVector[0] >> 16) & 0x3FF);
++ ResetVector[0] |= 0x50000000; /* b offset */
++ }
++
++ //
++ // Copy to the beginning of the FV
++ //
++ memcpy(FvImage->FileImage, ResetVector, sizeof (ResetVector));
++ } else {
++ Error(NULL, 0, 3000, "Invalid", "Unknown machine type");
++ return EFI_ABORTED;
++ }
++
++ return EFI_SUCCESS;
++}
++
+ EFI_STATUS
+ GetPe32Info (
+ IN UINT8 *Pe32,
+@@ -2489,7 +2576,7 @@ Returns:
+ //
+ if ((*MachineType != EFI_IMAGE_MACHINE_IA32) && (*MachineType != EFI_IMAGE_MACHINE_X64) && (*MachineType != EFI_IMAGE_MACHINE_EBC) &&
+ (*MachineType != EFI_IMAGE_MACHINE_ARMT) && (*MachineType != EFI_IMAGE_MACHINE_AARCH64) &&
+- (*MachineType != EFI_IMAGE_MACHINE_RISCV64)) {
++ (*MachineType != EFI_IMAGE_MACHINE_RISCV64) && (*MachineType != EFI_IMAGE_MACHINE_LOONGARCH64)) {
+ Error (NULL, 0, 3000, "Invalid", "Unrecognized machine type in the PE32 file.");
+ return EFI_UNSUPPORTED;
+ }
+@@ -2933,7 +3020,7 @@ Returns:
+ goto Finish;
+ }
+
+- if (!mArm && !mRiscV) {
++ if (!mArm && !mRiscV && !mLoongArch) {
+ //
+ // Update reset vector (SALE_ENTRY for IPF)
+ // Now for IA32 and IA64 platform, the fv which has bsf file must have the
+@@ -2984,6 +3071,19 @@ Returns:
+ FvHeader->Checksum = CalculateChecksum16 ((UINT16 *) FvHeader, FvHeader->HeaderLength / sizeof (UINT16));
+ }
+
++ if (mLoongArch) {
++ Status = UpdateLoongArchResetVectorIfNeeded (&FvImageMemoryFile, &mFvDataInfo);
++ if (EFI_ERROR (Status)) {
++ Error (NULL, 0, 3000, "Invalid", "Could not update the reset vector.");
++ goto Finish;
++ }
++ //
++ // Update Checksum for FvHeader
++ //
++ FvHeader->Checksum = 0;
++ FvHeader->Checksum = CalculateChecksum16 ((UINT16 *) FvHeader, FvHeader->HeaderLength / sizeof (UINT16));
++ }
++
+ //
+ // Update FV Alignment attribute to the largest alignment of all the FFS files in the FV
+ //
+@@ -3430,6 +3530,12 @@ Returns:
+ VerboseMsg("Located ARM/AArch64 SEC/PEI core in child FV");
+ mArm = TRUE;
+ }
++
++ // Machine type is LOONGARCH64, set a flag so LoongArch64 reset vector processed.
++ if ((MachineType == EFI_IMAGE_MACHINE_LOONGARCH64)) {
++ VerboseMsg("Located LoongArch64 SEC core in child FV");
++ mLoongArch = TRUE;
++ }
+ }
+
+ //
+@@ -3588,6 +3694,10 @@ Returns:
+ mRiscV = TRUE;
+ }
+
++ if ( (ImageContext.Machine == EFI_IMAGE_MACHINE_LOONGARCH64) ) {
++ mLoongArch = TRUE;
++ }
++
+ //
+ // Keep Image Context for PE image in FV
+ //
+@@ -3865,6 +3975,10 @@ Returns:
+ mArm = TRUE;
+ }
+
++ if ( (ImageContext.Machine == EFI_IMAGE_MACHINE_LOONGARCH64) ) {
++ mLoongArch = TRUE;
++ }
++
+ //
+ // Keep Image Context for TE image in FV
+ //
+diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c b/BaseTools/Source/C/GenFw/Elf64Convert.c
+index 4ed6b44..7d1bba0 100644
+--- a/BaseTools/Source/C/GenFw/Elf64Convert.c
++++ b/BaseTools/Source/C/GenFw/Elf64Convert.c
+@@ -4,6 +4,7 @@ Elf64 convert solution
+ Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.
+ Portions copyright (c) 2013-2014, ARM Ltd. All rights reserved.
+ Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
++Portions Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+@@ -161,7 +162,7 @@ InitializeElf64 (
+ Error (NULL, 0, 3000, "Unsupported", "ELF e_type not ET_EXEC or ET_DYN");
+ return FALSE;
+ }
+- if (!((mEhdr->e_machine == EM_X86_64) || (mEhdr->e_machine == EM_AARCH64) || (mEhdr->e_machine == EM_RISCV64))) {
++ if (!((mEhdr->e_machine == EM_X86_64) || (mEhdr->e_machine == EM_AARCH64) || (mEhdr->e_machine == EM_RISCV64) || (mEhdr->e_machine == EM_LOONGARCH))) {
+ Error (NULL, 0, 3000, "Unsupported", "ELF e_machine is not Elf64 machine.");
+ return FALSE;
+ }
+@@ -631,6 +632,7 @@ ScanSections64 (
+ case EM_X86_64:
+ case EM_AARCH64:
+ case EM_RISCV64:
++ case EM_LOONGARCH:
+ mCoffOffset += sizeof (EFI_IMAGE_NT_HEADERS64);
+ break;
+ default:
+@@ -844,6 +846,10 @@ ScanSections64 (
+ NtHdr->Pe32Plus.FileHeader.Machine = EFI_IMAGE_MACHINE_RISCV64;
+ NtHdr->Pe32Plus.OptionalHeader.Magic = EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC;
+ break;
++ case EM_LOONGARCH:
++ NtHdr->Pe32Plus.FileHeader.Machine = EFI_IMAGE_MACHINE_LOONGARCH64;
++ NtHdr->Pe32Plus.OptionalHeader.Magic = EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC;
++ break;
+
+ default:
+ VerboseMsg ("%s unknown e_machine type. Assume X64", (UINTN)mEhdr->e_machine);
+@@ -1050,10 +1056,10 @@ WriteSections64 (
+ }
+
+ //
+- // Skip error on EM_RISCV64 becasue no symble name is built
+- // from RISC-V toolchain.
++ // Skip error on EM_RISCV64 and EM_LOONGARCH because no symbol name is built
++ // from RISC-V and LoongArch toolchain.
+ //
+- if (mEhdr->e_machine != EM_RISCV64) {
++ if ((mEhdr->e_machine != EM_RISCV64) && (mEhdr->e_machine != EM_LOONGARCH)) {
+ Error (NULL, 0, 3000, "Invalid",
+ "%s: Bad definition for symbol '%s'@%#llx or unsupported symbol type. "
+ "For example, absolute and undefined symbols are not supported.",
+@@ -1317,6 +1323,178 @@ WriteSections64 (
+ // Write section for RISC-V 64 architecture.
+ //
+ WriteSectionRiscV64 (Rel, Targ, SymShdr, Sym);
++ } else if (mEhdr->e_machine == EM_LOONGARCH) {
++ switch (ELF_R_TYPE(Rel->r_info)) {
++ INT64 Offset;
++ INT32 Lo, Hi;
++
++ case R_LARCH_SOP_PUSH_ABSOLUTE:
++ //
++ // Absolute relocation.
++ //
++ *(UINT64 *)Targ = *(UINT64 *)Targ - SymShdr->sh_addr + mCoffSectionsOffset[Sym->st_shndx];
++ break;
++
++ case R_LARCH_MARK_LA:
++ case R_LARCH_64:
++ case R_LARCH_NONE:
++ case R_LARCH_32:
++ case R_LARCH_RELATIVE:
++ case R_LARCH_COPY:
++ case R_LARCH_JUMP_SLOT:
++ case R_LARCH_TLS_DTPMOD32:
++ case R_LARCH_TLS_DTPMOD64:
++ case R_LARCH_TLS_DTPREL32:
++ case R_LARCH_TLS_DTPREL64:
++ case R_LARCH_TLS_TPREL32:
++ case R_LARCH_TLS_TPREL64:
++ case R_LARCH_IRELATIVE:
++ case R_LARCH_MARK_PCREL:
++ case R_LARCH_SOP_PUSH_PCREL:
++ case R_LARCH_SOP_PUSH_DUP:
++ case R_LARCH_SOP_PUSH_GPREL:
++ case R_LARCH_SOP_PUSH_TLS_TPREL:
++ case R_LARCH_SOP_PUSH_TLS_GOT:
++ case R_LARCH_SOP_PUSH_TLS_GD:
++ case R_LARCH_SOP_PUSH_PLT_PCREL:
++ case R_LARCH_SOP_ASSERT:
++ case R_LARCH_SOP_NOT:
++ case R_LARCH_SOP_SUB:
++ case R_LARCH_SOP_SL:
++ case R_LARCH_SOP_SR:
++ case R_LARCH_SOP_ADD:
++ case R_LARCH_SOP_AND:
++ case R_LARCH_SOP_IF_ELSE:
++ case R_LARCH_SOP_POP_32_S_10_5:
++ case R_LARCH_SOP_POP_32_U_10_12:
++ case R_LARCH_SOP_POP_32_S_10_12:
++ case R_LARCH_SOP_POP_32_S_10_16:
++ case R_LARCH_SOP_POP_32_S_10_16_S2:
++ case R_LARCH_SOP_POP_32_S_5_20:
++ case R_LARCH_SOP_POP_32_S_0_5_10_16_S2:
++ case R_LARCH_SOP_POP_32_S_0_10_10_16_S2:
++ case R_LARCH_SOP_POP_32_U:
++ case R_LARCH_ADD8:
++ case R_LARCH_ADD16:
++ case R_LARCH_ADD24:
++ case R_LARCH_ADD32:
++ case R_LARCH_ADD64:
++ case R_LARCH_SUB8:
++ case R_LARCH_SUB16:
++ case R_LARCH_SUB24:
++ case R_LARCH_SUB32:
++ case R_LARCH_SUB64:
++ case R_LARCH_GNU_VTINHERIT:
++ case R_LARCH_GNU_VTENTRY:
++ case R_LARCH_B16:
++ case R_LARCH_B21:
++ case R_LARCH_B26:
++ case R_LARCH_ABS_HI20:
++ case R_LARCH_ABS_LO12:
++ case R_LARCH_ABS64_LO20:
++ case R_LARCH_ABS64_HI12:
++ case R_LARCH_PCALA_LO12:
++ case R_LARCH_PCALA64_LO20:
++ case R_LARCH_PCALA64_HI12:
++ case R_LARCH_GOT_PC_LO12:
++ case R_LARCH_GOT64_PC_LO20:
++ case R_LARCH_GOT64_PC_HI12:
++ case R_LARCH_GOT64_HI20:
++ case R_LARCH_GOT64_LO12:
++ case R_LARCH_GOT64_LO20:
++ case R_LARCH_GOT64_HI12:
++ case R_LARCH_TLS_LE_HI20:
++ case R_LARCH_TLS_LE_LO12:
++ case R_LARCH_TLS_LE64_LO20:
++ case R_LARCH_TLS_LE64_HI12:
++ case R_LARCH_TLS_IE_PC_HI20:
++ case R_LARCH_TLS_IE_PC_LO12:
++ case R_LARCH_TLS_IE64_PC_LO20:
++ case R_LARCH_TLS_IE64_PC_HI12:
++ case R_LARCH_TLS_IE64_HI20:
++ case R_LARCH_TLS_IE64_LO12:
++ case R_LARCH_TLS_IE64_LO20:
++ case R_LARCH_TLS_IE64_HI12:
++ case R_LARCH_TLS_LD_PC_HI20:
++ case R_LARCH_TLS_LD64_HI20:
++ case R_LARCH_TLS_GD_PC_HI20:
++ case R_LARCH_TLS_GD64_HI20:
++ case R_LARCH_RELAX:
++ //
++ // These types are not used or do not require fixup.
++ //
++ break;
++
++ case R_LARCH_GOT_PC_HI20:
++ Offset = Sym->st_value - (UINTN)(Targ - mCoffFile);
++ if (Offset < 0) {
++ Offset = (UINTN)(Targ - mCoffFile) - Sym->st_value;
++ Hi = Offset & ~0xfff;
++ Lo = (INT32)((Offset & 0xfff) << 20) >> 20;
++ if ((Lo < 0) && (Lo > -2048)) {
++ Hi += 0x1000;
++ Lo = ~(0x1000 - Lo) + 1;
++ }
++ Hi = ~Hi + 1;
++ Lo = ~Lo + 1;
++ } else {
++ Hi = Offset & ~0xfff;
++ Lo = (INT32)((Offset & 0xfff) << 20) >> 20;
++ if (Lo < 0) {
++ Hi += 0x1000;
++ Lo = ~(0x1000 - Lo) + 1;
++ }
++ }
++ // Re-encode the offset as PCADDU12I + ADDI.D(Convert LD.D) instruction
++ *(UINT32 *)Targ &= 0x1f;
++ *(UINT32 *)Targ |= 0x1c000000;
++ *(UINT32 *)Targ |= (((Hi >> 12) & 0xfffff) << 5);
++ *(UINT32 *)(Targ + 4) &= 0x3ff;
++ *(UINT32 *)(Targ + 4) |= 0x2c00000 | ((Lo & 0xfff) << 10);
++ break;
++
++ //
++ // Attempt to convert instruction.
++ //
++ case R_LARCH_PCALA_HI20:
++ // Decode the PCALAU12I instruction and the instruction that following it.
++ Offset = ((INT32)((*(UINT32 *)Targ & 0x1ffffe0) << 7));
++ Offset += ((INT32)((*(UINT32 *)(Targ + 4) & 0x3ffc00) << 10) >> 20);
++ //
++ // PCALA offset is relative to the previous page boundary,
++ // whereas PCADD offset is relative to the instruction itself.
++ // So fix up the offset so it points to the page containing
++ // the symbol.
++ //
++ Offset -= (UINTN)(Targ - mCoffFile) & 0xfff;
++ if (Offset < 0) {
++ Offset = -Offset;
++ Hi = Offset & ~0xfff;
++ Lo = (INT32)((Offset & 0xfff) << 20) >> 20;
++ if ((Lo < 0) && (Lo > -2048)) {
++ Hi += 0x1000;
++ Lo = ~(0x1000 - Lo) + 1;
++ }
++ Hi = ~Hi + 1;
++ Lo = ~Lo + 1;
++ } else {
++ Hi = Offset & ~0xfff;
++ Lo = (INT32)((Offset & 0xfff) << 20) >> 20;
++ if (Lo < 0) {
++ Hi += 0x1000;
++ Lo = ~(0x1000 - Lo) + 1;
++ }
++ }
++ // Convert the first instruction from PCALAU12I to PCADDU12I and re-encode the offset into them.
++ *(UINT32 *)Targ &= 0x1f;
++ *(UINT32 *)Targ |= 0x1c000000;
++ *(UINT32 *)Targ |= (((Hi >> 12) & 0xfffff) << 5);
++ *(UINT32 *)(Targ + 4) &= 0xffc003ff;
++ *(UINT32 *)(Targ + 4) |= (Lo & 0xfff) << 10;
++ break;
++ default:
++ Error (NULL, 0, 3000, "Invalid", "WriteSections64(): %s unsupported ELF EM_LOONGARCH relocation 0x%x.", mInImageName, (unsigned) ELF64_R_TYPE(Rel->r_info));
++ }
+ } else {
+ Error (NULL, 0, 3000, "Invalid", "Not a supported machine type");
+ }
+@@ -1544,6 +1722,113 @@ WriteRelocations64 (
+ default:
+ Error (NULL, 0, 3000, "Invalid", "WriteRelocations64(): %s unsupported ELF EM_RISCV64 relocation 0x%x.", mInImageName, (unsigned) ELF_R_TYPE(Rel->r_info));
+ }
++ } else if (mEhdr->e_machine == EM_LOONGARCH) {
++ switch (ELF_R_TYPE(Rel->r_info)) {
++ case R_LARCH_MARK_LA:
++ CoffAddFixup(
++ (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
++ + (Rel->r_offset - SecShdr->sh_addr)),
++ EFI_IMAGE_REL_BASED_LOONGARCH64_MARK_LA);
++ break;
++ case R_LARCH_64:
++ CoffAddFixup(
++ (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
++ + (Rel->r_offset - SecShdr->sh_addr)),
++ EFI_IMAGE_REL_BASED_DIR64);
++ break;
++ case R_LARCH_NONE:
++ case R_LARCH_32:
++ case R_LARCH_RELATIVE:
++ case R_LARCH_COPY:
++ case R_LARCH_JUMP_SLOT:
++ case R_LARCH_TLS_DTPMOD32:
++ case R_LARCH_TLS_DTPMOD64:
++ case R_LARCH_TLS_DTPREL32:
++ case R_LARCH_TLS_DTPREL64:
++ case R_LARCH_TLS_TPREL32:
++ case R_LARCH_TLS_TPREL64:
++ case R_LARCH_IRELATIVE:
++ case R_LARCH_MARK_PCREL:
++ case R_LARCH_SOP_PUSH_PCREL:
++ case R_LARCH_SOP_PUSH_ABSOLUTE:
++ case R_LARCH_SOP_PUSH_DUP:
++ case R_LARCH_SOP_PUSH_GPREL:
++ case R_LARCH_SOP_PUSH_TLS_TPREL:
++ case R_LARCH_SOP_PUSH_TLS_GOT:
++ case R_LARCH_SOP_PUSH_TLS_GD:
++ case R_LARCH_SOP_PUSH_PLT_PCREL:
++ case R_LARCH_SOP_ASSERT:
++ case R_LARCH_SOP_NOT:
++ case R_LARCH_SOP_SUB:
++ case R_LARCH_SOP_SL:
++ case R_LARCH_SOP_SR:
++ case R_LARCH_SOP_ADD:
++ case R_LARCH_SOP_AND:
++ case R_LARCH_SOP_IF_ELSE:
++ case R_LARCH_SOP_POP_32_S_10_5:
++ case R_LARCH_SOP_POP_32_U_10_12:
++ case R_LARCH_SOP_POP_32_S_10_12:
++ case R_LARCH_SOP_POP_32_S_10_16:
++ case R_LARCH_SOP_POP_32_S_10_16_S2:
++ case R_LARCH_SOP_POP_32_S_5_20:
++ case R_LARCH_SOP_POP_32_S_0_5_10_16_S2:
++ case R_LARCH_SOP_POP_32_S_0_10_10_16_S2:
++ case R_LARCH_SOP_POP_32_U:
++ case R_LARCH_ADD8:
++ case R_LARCH_ADD16:
++ case R_LARCH_ADD24:
++ case R_LARCH_ADD32:
++ case R_LARCH_ADD64:
++ case R_LARCH_SUB8:
++ case R_LARCH_SUB16:
++ case R_LARCH_SUB24:
++ case R_LARCH_SUB32:
++ case R_LARCH_SUB64:
++ case R_LARCH_GNU_VTINHERIT:
++ case R_LARCH_GNU_VTENTRY:
++ case R_LARCH_B16:
++ case R_LARCH_B21:
++ case R_LARCH_B26:
++ case R_LARCH_ABS_HI20:
++ case R_LARCH_ABS_LO12:
++ case R_LARCH_ABS64_LO20:
++ case R_LARCH_ABS64_HI12:
++ case R_LARCH_PCALA_HI20:
++ case R_LARCH_PCALA_LO12:
++ case R_LARCH_PCALA64_LO20:
++ case R_LARCH_PCALA64_HI12:
++ case R_LARCH_GOT_PC_HI20:
++ case R_LARCH_GOT_PC_LO12:
++ case R_LARCH_GOT64_PC_LO20:
++ case R_LARCH_GOT64_PC_HI12:
++ case R_LARCH_GOT64_HI20:
++ case R_LARCH_GOT64_LO12:
++ case R_LARCH_GOT64_LO20:
++ case R_LARCH_GOT64_HI12:
++ case R_LARCH_TLS_LE_HI20:
++ case R_LARCH_TLS_LE_LO12:
++ case R_LARCH_TLS_LE64_LO20:
++ case R_LARCH_TLS_LE64_HI12:
++ case R_LARCH_TLS_IE_PC_HI20:
++ case R_LARCH_TLS_IE_PC_LO12:
++ case R_LARCH_TLS_IE64_PC_LO20:
++ case R_LARCH_TLS_IE64_PC_HI12:
++ case R_LARCH_TLS_IE64_HI20:
++ case R_LARCH_TLS_IE64_LO12:
++ case R_LARCH_TLS_IE64_LO20:
++ case R_LARCH_TLS_IE64_HI12:
++ case R_LARCH_TLS_LD_PC_HI20:
++ case R_LARCH_TLS_LD64_HI20:
++ case R_LARCH_TLS_GD_PC_HI20:
++ case R_LARCH_TLS_GD64_HI20:
++ case R_LARCH_RELAX:
++ //
++ // These types are not used or do not require fixup in PE format files.
++ //
++ break;
++ default:
++ Error (NULL, 0, 3000, "Invalid", "WriteRelocations64(): %s unsupported ELF EM_LOONGARCH relocation 0x%x.", mInImageName, (unsigned) ELF64_R_TYPE(Rel->r_info));
++ }
+ } else {
+ Error (NULL, 0, 3000, "Not Supported", "This tool does not support relocations for ELF with e_machine %u (processor type).", (unsigned) mEhdr->e_machine);
+ }
+diff --git a/BaseTools/Source/C/GenFw/elf_common.h b/BaseTools/Source/C/GenFw/elf_common.h
+index b67f59e..7b7fdeb 100644
+--- a/BaseTools/Source/C/GenFw/elf_common.h
++++ b/BaseTools/Source/C/GenFw/elf_common.h
+@@ -4,6 +4,7 @@ Ported ELF include files from FreeBSD
+ Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.
+ Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
+ Portion Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
++Portions Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+
+@@ -181,6 +182,7 @@ typedef struct {
+ #define EM_AARCH64 183 /* ARM 64bit Architecture */
+ #define EM_RISCV64 243 /* 64bit RISC-V Architecture */
+ #define EM_RISCV 244 /* 32bit RISC-V Architecture */
++#define EM_LOONGARCH 258 /* LoongArch Architecture */
+
+ /* Non-standard or deprecated. */
+ #define EM_486 6 /* Intel i486. */
+@@ -1042,4 +1044,96 @@ typedef struct {
+ #define R_RISCV_SET8 54
+ #define R_RISCV_SET16 55
+ #define R_RISCV_SET32 56
++
++/*
++ * LoongArch relocation types
++ */
++#define R_LARCH_NONE 0
++#define R_LARCH_32 1
++#define R_LARCH_64 2
++#define R_LARCH_RELATIVE 3
++#define R_LARCH_COPY 4
++#define R_LARCH_JUMP_SLOT 5
++#define R_LARCH_TLS_DTPMOD32 6
++#define R_LARCH_TLS_DTPMOD64 7
++#define R_LARCH_TLS_DTPREL32 8
++#define R_LARCH_TLS_DTPREL64 9
++#define R_LARCH_TLS_TPREL32 10
++#define R_LARCH_TLS_TPREL64 11
++#define R_LARCH_IRELATIVE 12
++#define R_LARCH_MARK_LA 20
++#define R_LARCH_MARK_PCREL 21
++#define R_LARCH_SOP_PUSH_PCREL 22
++#define R_LARCH_SOP_PUSH_ABSOLUTE 23
++#define R_LARCH_SOP_PUSH_DUP 24
++#define R_LARCH_SOP_PUSH_GPREL 25
++#define R_LARCH_SOP_PUSH_TLS_TPREL 26
++#define R_LARCH_SOP_PUSH_TLS_GOT 27
++#define R_LARCH_SOP_PUSH_TLS_GD 28
++#define R_LARCH_SOP_PUSH_PLT_PCREL 29
++#define R_LARCH_SOP_ASSERT 30
++#define R_LARCH_SOP_NOT 31
++#define R_LARCH_SOP_SUB 32
++#define R_LARCH_SOP_SL 33
++#define R_LARCH_SOP_SR 34
++#define R_LARCH_SOP_ADD 35
++#define R_LARCH_SOP_AND 36
++#define R_LARCH_SOP_IF_ELSE 37
++#define R_LARCH_SOP_POP_32_S_10_5 38
++#define R_LARCH_SOP_POP_32_U_10_12 39
++#define R_LARCH_SOP_POP_32_S_10_12 40
++#define R_LARCH_SOP_POP_32_S_10_16 41
++#define R_LARCH_SOP_POP_32_S_10_16_S2 42
++#define R_LARCH_SOP_POP_32_S_5_20 43
++#define R_LARCH_SOP_POP_32_S_0_5_10_16_S2 44
++#define R_LARCH_SOP_POP_32_S_0_10_10_16_S2 45
++#define R_LARCH_SOP_POP_32_U 46
++#define R_LARCH_ADD8 47
++#define R_LARCH_ADD16 48
++#define R_LARCH_ADD24 49
++#define R_LARCH_ADD32 50
++#define R_LARCH_ADD64 51
++#define R_LARCH_SUB8 52
++#define R_LARCH_SUB16 53
++#define R_LARCH_SUB24 54
++#define R_LARCH_SUB32 55
++#define R_LARCH_SUB64 56
++#define R_LARCH_GNU_VTINHERIT 57
++#define R_LARCH_GNU_VTENTRY 58
++#define R_LARCH_B16 64
++#define R_LARCH_B21 65
++#define R_LARCH_B26 66
++#define R_LARCH_ABS_HI20 67
++#define R_LARCH_ABS_LO12 68
++#define R_LARCH_ABS64_LO20 69
++#define R_LARCH_ABS64_HI12 70
++#define R_LARCH_PCALA_HI20 71
++#define R_LARCH_PCALA_LO12 72
++#define R_LARCH_PCALA64_LO20 73
++#define R_LARCH_PCALA64_HI12 74
++#define R_LARCH_GOT_PC_HI20 75
++#define R_LARCH_GOT_PC_LO12 76
++#define R_LARCH_GOT64_PC_LO20 77
++#define R_LARCH_GOT64_PC_HI12 78
++#define R_LARCH_GOT64_HI20 79
++#define R_LARCH_GOT64_LO12 80
++#define R_LARCH_GOT64_LO20 81
++#define R_LARCH_GOT64_HI12 82
++#define R_LARCH_TLS_LE_HI20 83
++#define R_LARCH_TLS_LE_LO12 84
++#define R_LARCH_TLS_LE64_LO20 85
++#define R_LARCH_TLS_LE64_HI12 86
++#define R_LARCH_TLS_IE_PC_HI20 87
++#define R_LARCH_TLS_IE_PC_LO12 88
++#define R_LARCH_TLS_IE64_PC_LO20 89
++#define R_LARCH_TLS_IE64_PC_HI12 90
++#define R_LARCH_TLS_IE64_HI20 91
++#define R_LARCH_TLS_IE64_LO12 92
++#define R_LARCH_TLS_IE64_LO20 93
++#define R_LARCH_TLS_IE64_HI12 94
++#define R_LARCH_TLS_LD_PC_HI20 95
++#define R_LARCH_TLS_LD64_HI20 96
++#define R_LARCH_TLS_GD_PC_HI20 97
++#define R_LARCH_TLS_GD64_HI20 98
++#define R_LARCH_RELAX 99
+ #endif /* !_SYS_ELF_COMMON_H_ */
+diff --git a/BaseTools/Source/C/Include/IndustryStandard/PeImage.h b/BaseTools/Source/C/Include/IndustryStandard/PeImage.h
+index f17b8ee..162f8fd 100644
+--- a/BaseTools/Source/C/Include/IndustryStandard/PeImage.h
++++ b/BaseTools/Source/C/Include/IndustryStandard/PeImage.h
+@@ -7,6 +7,7 @@
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
+ Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
++ Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+@@ -36,23 +37,25 @@
+ //
+ // PE32+ Machine type for EFI images
+ //
+-#define IMAGE_FILE_MACHINE_I386 0x014c
+-#define IMAGE_FILE_MACHINE_EBC 0x0EBC
+-#define IMAGE_FILE_MACHINE_X64 0x8664
+-#define IMAGE_FILE_MACHINE_ARM 0x01c0 // Thumb only
+-#define IMAGE_FILE_MACHINE_ARMT 0x01c2 // 32bit Mixed ARM and Thumb/Thumb 2 Little Endian
+-#define IMAGE_FILE_MACHINE_ARM64 0xAA64 // 64bit ARM Architecture, Little Endian
+-#define IMAGE_FILE_MACHINE_RISCV64 0x5064 // 64bit RISC-V ISA
++#define IMAGE_FILE_MACHINE_I386 0x014c
++#define IMAGE_FILE_MACHINE_EBC 0x0EBC
++#define IMAGE_FILE_MACHINE_X64 0x8664
++#define IMAGE_FILE_MACHINE_ARM 0x01c0 // Thumb only
++#define IMAGE_FILE_MACHINE_ARMT 0x01c2 // 32bit Mixed ARM and Thumb/Thumb 2 Little Endian
++#define IMAGE_FILE_MACHINE_ARM64 0xAA64 // 64bit ARM Architecture, Little Endian
++#define IMAGE_FILE_MACHINE_RISCV64 0x5064 // 64bit RISC-V ISA
++#define IMAGE_FILE_MACHINE_LOONGARCH64 0x6264 // 64bit LoongArch Architecture
+
+ //
+ // Support old names for backward compatible
+ //
+-#define EFI_IMAGE_MACHINE_IA32 IMAGE_FILE_MACHINE_I386
+-#define EFI_IMAGE_MACHINE_EBC IMAGE_FILE_MACHINE_EBC
+-#define EFI_IMAGE_MACHINE_X64 IMAGE_FILE_MACHINE_X64
+-#define EFI_IMAGE_MACHINE_ARMT IMAGE_FILE_MACHINE_ARMT
+-#define EFI_IMAGE_MACHINE_AARCH64 IMAGE_FILE_MACHINE_ARM64
+-#define EFI_IMAGE_MACHINE_RISCV64 IMAGE_FILE_MACHINE_RISCV64
++#define EFI_IMAGE_MACHINE_IA32 IMAGE_FILE_MACHINE_I386
++#define EFI_IMAGE_MACHINE_EBC IMAGE_FILE_MACHINE_EBC
++#define EFI_IMAGE_MACHINE_X64 IMAGE_FILE_MACHINE_X64
++#define EFI_IMAGE_MACHINE_ARMT IMAGE_FILE_MACHINE_ARMT
++#define EFI_IMAGE_MACHINE_AARCH64 IMAGE_FILE_MACHINE_ARM64
++#define EFI_IMAGE_MACHINE_RISCV64 IMAGE_FILE_MACHINE_RISCV64
++#define EFI_IMAGE_MACHINE_LOONGARCH64 IMAGE_FILE_MACHINE_LOONGARCH64
+
+ #define EFI_IMAGE_DOS_SIGNATURE 0x5A4D // MZ
+ #define EFI_IMAGE_OS2_SIGNATURE 0x454E // NE
+@@ -500,19 +503,21 @@ typedef struct {
+ //
+ // Based relocation types.
+ //
+-#define EFI_IMAGE_REL_BASED_ABSOLUTE 0
+-#define EFI_IMAGE_REL_BASED_HIGH 1
+-#define EFI_IMAGE_REL_BASED_LOW 2
+-#define EFI_IMAGE_REL_BASED_HIGHLOW 3
+-#define EFI_IMAGE_REL_BASED_HIGHADJ 4
+-#define EFI_IMAGE_REL_BASED_MIPS_JMPADDR 5
+-#define EFI_IMAGE_REL_BASED_ARM_MOV32A 5
+-#define EFI_IMAGE_REL_BASED_RISCV_HI20 5
+-#define EFI_IMAGE_REL_BASED_ARM_MOV32T 7
+-#define EFI_IMAGE_REL_BASED_RISCV_LOW12I 7
+-#define EFI_IMAGE_REL_BASED_RISCV_LOW12S 8
+-#define EFI_IMAGE_REL_BASED_IA64_IMM64 9
+-#define EFI_IMAGE_REL_BASED_DIR64 10
++#define EFI_IMAGE_REL_BASED_ABSOLUTE 0
++#define EFI_IMAGE_REL_BASED_HIGH 1
++#define EFI_IMAGE_REL_BASED_LOW 2
++#define EFI_IMAGE_REL_BASED_HIGHLOW 3
++#define EFI_IMAGE_REL_BASED_HIGHADJ 4
++#define EFI_IMAGE_REL_BASED_MIPS_JMPADDR 5
++#define EFI_IMAGE_REL_BASED_ARM_MOV32A 5
++#define EFI_IMAGE_REL_BASED_RISCV_HI20 5
++#define EFI_IMAGE_REL_BASED_ARM_MOV32T 7
++#define EFI_IMAGE_REL_BASED_RISCV_LOW12I 7
++#define EFI_IMAGE_REL_BASED_RISCV_LOW12S 8
++#define EFI_IMAGE_REL_BASED_LOONGARCH32_MARK_LA 8
++#define EFI_IMAGE_REL_BASED_LOONGARCH64_MARK_LA 8
++#define EFI_IMAGE_REL_BASED_IA64_IMM64 9
++#define EFI_IMAGE_REL_BASED_DIR64 10
+
+
+ ///
+diff --git a/BaseTools/Source/C/Makefiles/header.makefile b/BaseTools/Source/C/Makefiles/header.makefile
+index 0df728f..4e88a4f 100644
+--- a/BaseTools/Source/C/Makefiles/header.makefile
++++ b/BaseTools/Source/C/Makefiles/header.makefile
+@@ -31,6 +31,9 @@ ifndef HOST_ARCH
+ ifneq (,$(findstring riscv64,$(uname_m)))
+ HOST_ARCH=RISCV64
+ endif
++ ifneq (,$(findstring loongarch64,$(uname_m)))
++ HOST_ARCH=LOONGARCH64
++ endif
+ ifndef HOST_ARCH
+ $(info Could not detected HOST_ARCH from uname results)
+ $(error HOST_ARCH is not defined!)
+@@ -70,6 +73,9 @@ ARCH_INCLUDE = -I $(MAKEROOT)/Include/AArch64/
+ else ifeq ($(HOST_ARCH), RISCV64)
+ ARCH_INCLUDE = -I $(MAKEROOT)/Include/RiscV64/
+
++else ifeq ($(HOST_ARCH), LOONGARCH64)
++ARCH_INCLUDE = -I $(MAKEROOT)/Include/LoongArch64/
++
+ else
+ $(error Bad HOST_ARCH)
+ endif
+diff --git a/BaseTools/Source/Python/Common/DataType.py b/BaseTools/Source/Python/Common/DataType.py
+index fb88f20..2994567 100644
+--- a/BaseTools/Source/Python/Common/DataType.py
++++ b/BaseTools/Source/Python/Common/DataType.py
+@@ -4,6 +4,7 @@
+ # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+ # Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
+ # Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
++# Portions Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
+ # SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ ##
+@@ -52,10 +53,10 @@ TAB_ARCH_X64 = 'X64'
+ TAB_ARCH_ARM = 'ARM'
+ TAB_ARCH_EBC = 'EBC'
+ TAB_ARCH_AARCH64 = 'AARCH64'
+-
+ TAB_ARCH_RISCV64 = 'RISCV64'
++TAB_ARCH_LOONGARCH64 = 'LOONGARCH64'
+
+-ARCH_SET_FULL = {TAB_ARCH_IA32, TAB_ARCH_X64, TAB_ARCH_ARM, TAB_ARCH_EBC, TAB_ARCH_AARCH64, TAB_ARCH_RISCV64, TAB_ARCH_COMMON}
++ARCH_SET_FULL = {TAB_ARCH_IA32, TAB_ARCH_X64, TAB_ARCH_ARM, TAB_ARCH_EBC, TAB_ARCH_AARCH64, TAB_ARCH_RISCV64, TAB_ARCH_LOONGARCH64, TAB_ARCH_COMMON}
+
+ SUP_MODULE_BASE = 'BASE'
+ SUP_MODULE_SEC = 'SEC'
+@@ -138,6 +139,7 @@ TAB_SOURCES_X64 = TAB_SOURCES + TAB_SPLIT + TAB_ARCH_X64
+ TAB_SOURCES_ARM = TAB_SOURCES + TAB_SPLIT + TAB_ARCH_ARM
+ TAB_SOURCES_EBC = TAB_SOURCES + TAB_SPLIT + TAB_ARCH_EBC
+ TAB_SOURCES_AARCH64 = TAB_SOURCES + TAB_SPLIT + TAB_ARCH_AARCH64
++TAB_SOURCES_LOONGARCH64 = TAB_SOURCES + TAB_SPLIT + TAB_ARCH_LOONGARCH64
+
+ TAB_BINARIES = 'Binaries'
+ TAB_BINARIES_COMMON = TAB_BINARIES + TAB_SPLIT + TAB_ARCH_COMMON
+@@ -146,6 +148,7 @@ TAB_BINARIES_X64 = TAB_BINARIES + TAB_SPLIT + TAB_ARCH_X64
+ TAB_BINARIES_ARM = TAB_BINARIES + TAB_SPLIT + TAB_ARCH_ARM
+ TAB_BINARIES_EBC = TAB_BINARIES + TAB_SPLIT + TAB_ARCH_EBC
+ TAB_BINARIES_AARCH64 = TAB_BINARIES + TAB_SPLIT + TAB_ARCH_AARCH64
++TAB_BINARIES_LOONGARCH64 = TAB_BINARIES + TAB_SPLIT + TAB_ARCH_LOONGARCH64
+
+ TAB_INCLUDES = 'Includes'
+ TAB_INCLUDES_COMMON = TAB_INCLUDES + TAB_SPLIT + TAB_ARCH_COMMON
+@@ -154,6 +157,7 @@ TAB_INCLUDES_X64 = TAB_INCLUDES + TAB_SPLIT + TAB_ARCH_X64
+ TAB_INCLUDES_ARM = TAB_INCLUDES + TAB_SPLIT + TAB_ARCH_ARM
+ TAB_INCLUDES_EBC = TAB_INCLUDES + TAB_SPLIT + TAB_ARCH_EBC
+ TAB_INCLUDES_AARCH64 = TAB_INCLUDES + TAB_SPLIT + TAB_ARCH_AARCH64
++TAB_INCLUDES_LOONGARCH64 = TAB_INCLUDES + TAB_SPLIT + TAB_ARCH_LOONGARCH64
+
+ TAB_GUIDS = 'Guids'
+ TAB_GUIDS_COMMON = TAB_GUIDS + TAB_SPLIT + TAB_ARCH_COMMON
+@@ -162,6 +166,7 @@ TAB_GUIDS_X64 = TAB_GUIDS + TAB_SPLIT + TAB_ARCH_X64
+ TAB_GUIDS_ARM = TAB_GUIDS + TAB_SPLIT + TAB_ARCH_ARM
+ TAB_GUIDS_EBC = TAB_GUIDS + TAB_SPLIT + TAB_ARCH_EBC
+ TAB_GUIDS_AARCH64 = TAB_GUIDS + TAB_SPLIT + TAB_ARCH_AARCH64
++TAB_GUIDS_LOONGARCH64 = TAB_GUIDS + TAB_SPLIT + TAB_ARCH_LOONGARCH64
+
+ TAB_PROTOCOLS = 'Protocols'
+ TAB_PROTOCOLS_COMMON = TAB_PROTOCOLS + TAB_SPLIT + TAB_ARCH_COMMON
+@@ -170,6 +175,7 @@ TAB_PROTOCOLS_X64 = TAB_PROTOCOLS + TAB_SPLIT + TAB_ARCH_X64
+ TAB_PROTOCOLS_ARM = TAB_PROTOCOLS + TAB_SPLIT + TAB_ARCH_ARM
+ TAB_PROTOCOLS_EBC = TAB_PROTOCOLS + TAB_SPLIT + TAB_ARCH_EBC
+ TAB_PROTOCOLS_AARCH64 = TAB_PROTOCOLS + TAB_SPLIT + TAB_ARCH_AARCH64
++TAB_PROTOCOLS_LOONGARCH64 = TAB_PROTOCOLS + TAB_SPLIT + TAB_ARCH_LOONGARCH64
+
+ TAB_PPIS = 'Ppis'
+ TAB_PPIS_COMMON = TAB_PPIS + TAB_SPLIT + TAB_ARCH_COMMON
+@@ -178,6 +184,7 @@ TAB_PPIS_X64 = TAB_PPIS + TAB_SPLIT + TAB_ARCH_X64
+ TAB_PPIS_ARM = TAB_PPIS + TAB_SPLIT + TAB_ARCH_ARM
+ TAB_PPIS_EBC = TAB_PPIS + TAB_SPLIT + TAB_ARCH_EBC
+ TAB_PPIS_AARCH64 = TAB_PPIS + TAB_SPLIT + TAB_ARCH_AARCH64
++TAB_PPIS_LOONGARCH64 = TAB_PPIS + TAB_SPLIT + TAB_ARCH_LOONGARCH64
+
+ TAB_LIBRARY_CLASSES = 'LibraryClasses'
+ TAB_LIBRARY_CLASSES_COMMON = TAB_LIBRARY_CLASSES + TAB_SPLIT + TAB_ARCH_COMMON
+@@ -186,6 +193,7 @@ TAB_LIBRARY_CLASSES_X64 = TAB_LIBRARY_CLASSES + TAB_SPLIT + TAB_ARCH_X64
+ TAB_LIBRARY_CLASSES_ARM = TAB_LIBRARY_CLASSES + TAB_SPLIT + TAB_ARCH_ARM
+ TAB_LIBRARY_CLASSES_EBC = TAB_LIBRARY_CLASSES + TAB_SPLIT + TAB_ARCH_EBC
+ TAB_LIBRARY_CLASSES_AARCH64 = TAB_LIBRARY_CLASSES + TAB_SPLIT + TAB_ARCH_AARCH64
++TAB_LIBRARY_CLASSES_LOONGARCH64 = TAB_LIBRARY_CLASSES + TAB_SPLIT + TAB_ARCH_LOONGARCH64
+
+ TAB_PACKAGES = 'Packages'
+ TAB_PACKAGES_COMMON = TAB_PACKAGES + TAB_SPLIT + TAB_ARCH_COMMON
+@@ -194,6 +202,7 @@ TAB_PACKAGES_X64 = TAB_PACKAGES + TAB_SPLIT + TAB_ARCH_X64
+ TAB_PACKAGES_ARM = TAB_PACKAGES + TAB_SPLIT + TAB_ARCH_ARM
+ TAB_PACKAGES_EBC = TAB_PACKAGES + TAB_SPLIT + TAB_ARCH_EBC
+ TAB_PACKAGES_AARCH64 = TAB_PACKAGES + TAB_SPLIT + TAB_ARCH_AARCH64
++TAB_PACKAGES_LOONGARCH64 = TAB_PACKAGES + TAB_SPLIT + TAB_ARCH_LOONGARCH64
+
+ TAB_PCDS = 'Pcds'
+ TAB_PCDS_FIXED_AT_BUILD = 'FixedAtBuild'
+@@ -221,6 +230,7 @@ TAB_PCDS_FIXED_AT_BUILD_X64 = TAB_PCDS + TAB_PCDS_FIXED_AT_BUILD + TAB_SPLIT + T
+ TAB_PCDS_FIXED_AT_BUILD_ARM = TAB_PCDS + TAB_PCDS_FIXED_AT_BUILD + TAB_SPLIT + TAB_ARCH_ARM
+ TAB_PCDS_FIXED_AT_BUILD_EBC = TAB_PCDS + TAB_PCDS_FIXED_AT_BUILD + TAB_SPLIT + TAB_ARCH_EBC
+ TAB_PCDS_FIXED_AT_BUILD_AARCH64 = TAB_PCDS + TAB_PCDS_FIXED_AT_BUILD + TAB_SPLIT + TAB_ARCH_AARCH64
++TAB_PCDS_FIXED_AT_BUILD_LOONGARCH64 = TAB_PCDS + TAB_PCDS_FIXED_AT_BUILD + TAB_SPLIT + TAB_ARCH_LOONGARCH64
+
+ TAB_PCDS_PATCHABLE_IN_MODULE_NULL = TAB_PCDS + TAB_PCDS_PATCHABLE_IN_MODULE
+ TAB_PCDS_PATCHABLE_IN_MODULE_COMMON = TAB_PCDS + TAB_PCDS_PATCHABLE_IN_MODULE + TAB_SPLIT + TAB_ARCH_COMMON
+@@ -229,6 +239,7 @@ TAB_PCDS_PATCHABLE_IN_MODULE_X64 = TAB_PCDS + TAB_PCDS_PATCHABLE_IN_MODULE + TAB
+ TAB_PCDS_PATCHABLE_IN_MODULE_ARM = TAB_PCDS + TAB_PCDS_PATCHABLE_IN_MODULE + TAB_SPLIT + TAB_ARCH_ARM
+ TAB_PCDS_PATCHABLE_IN_MODULE_EBC = TAB_PCDS + TAB_PCDS_PATCHABLE_IN_MODULE + TAB_SPLIT + TAB_ARCH_EBC
+ TAB_PCDS_PATCHABLE_IN_MODULE_AARCH64 = TAB_PCDS + TAB_PCDS_PATCHABLE_IN_MODULE + TAB_SPLIT + TAB_ARCH_AARCH64
++TAB_PCDS_PATCHABLE_IN_MODULE_LOONGARCH64 = TAB_PCDS + TAB_PCDS_PATCHABLE_IN_MODULE + TAB_SPLIT + TAB_ARCH_LOONGARCH64
+
+ TAB_PCDS_FEATURE_FLAG_NULL = TAB_PCDS + TAB_PCDS_FEATURE_FLAG
+ TAB_PCDS_FEATURE_FLAG_COMMON = TAB_PCDS + TAB_PCDS_FEATURE_FLAG + TAB_SPLIT + TAB_ARCH_COMMON
+@@ -237,6 +248,7 @@ TAB_PCDS_FEATURE_FLAG_X64 = TAB_PCDS + TAB_PCDS_FEATURE_FLAG + TAB_SPLIT + TAB_A
+ TAB_PCDS_FEATURE_FLAG_ARM = TAB_PCDS + TAB_PCDS_FEATURE_FLAG + TAB_SPLIT + TAB_ARCH_ARM
+ TAB_PCDS_FEATURE_FLAG_EBC = TAB_PCDS + TAB_PCDS_FEATURE_FLAG + TAB_SPLIT + TAB_ARCH_EBC
+ TAB_PCDS_FEATURE_FLAG_AARCH64 = TAB_PCDS + TAB_PCDS_FEATURE_FLAG + TAB_SPLIT + TAB_ARCH_AARCH64
++TAB_PCDS_FEATURE_FLAG_LOONGARCH64 = TAB_PCDS + TAB_PCDS_FEATURE_FLAG + TAB_SPLIT + TAB_ARCH_LOONGARCH64
+
+ TAB_PCDS_DYNAMIC_EX_NULL = TAB_PCDS + TAB_PCDS_DYNAMIC_EX
+ TAB_PCDS_DYNAMIC_EX_DEFAULT_NULL = TAB_PCDS + TAB_PCDS_DYNAMIC_EX_DEFAULT
+@@ -248,6 +260,7 @@ TAB_PCDS_DYNAMIC_EX_X64 = TAB_PCDS + TAB_PCDS_DYNAMIC_EX + TAB_SPLIT + TAB_ARCH_
+ TAB_PCDS_DYNAMIC_EX_ARM = TAB_PCDS + TAB_PCDS_DYNAMIC_EX + TAB_SPLIT + TAB_ARCH_ARM
+ TAB_PCDS_DYNAMIC_EX_EBC = TAB_PCDS + TAB_PCDS_DYNAMIC_EX + TAB_SPLIT + TAB_ARCH_EBC
+ TAB_PCDS_DYNAMIC_EX_AARCH64 = TAB_PCDS + TAB_PCDS_DYNAMIC_EX + TAB_SPLIT + TAB_ARCH_AARCH64
++TAB_PCDS_DYNAMIC_EX_LOONGARCH64 = TAB_PCDS + TAB_PCDS_DYNAMIC_EX + TAB_SPLIT + TAB_ARCH_LOONGARCH64
+
+ TAB_PCDS_DYNAMIC_NULL = TAB_PCDS + TAB_PCDS_DYNAMIC
+ TAB_PCDS_DYNAMIC_DEFAULT_NULL = TAB_PCDS + TAB_PCDS_DYNAMIC_DEFAULT
+@@ -259,6 +272,7 @@ TAB_PCDS_DYNAMIC_X64 = TAB_PCDS + TAB_PCDS_DYNAMIC + TAB_SPLIT + TAB_ARCH_X64
+ TAB_PCDS_DYNAMIC_ARM = TAB_PCDS + TAB_PCDS_DYNAMIC + TAB_SPLIT + TAB_ARCH_ARM
+ TAB_PCDS_DYNAMIC_EBC = TAB_PCDS + TAB_PCDS_DYNAMIC + TAB_SPLIT + TAB_ARCH_EBC
+ TAB_PCDS_DYNAMIC_AARCH64 = TAB_PCDS + TAB_PCDS_DYNAMIC + TAB_SPLIT + TAB_ARCH_AARCH64
++TAB_PCDS_DYNAMIC_LOONGARCH64 = TAB_PCDS + TAB_PCDS_DYNAMIC + TAB_SPLIT + TAB_ARCH_LOONGARCH64
+
+ TAB_PCDS_PATCHABLE_LOAD_FIX_ADDRESS_PEI_PAGE_SIZE = 'PcdLoadFixAddressPeiCodePageNumber'
+ TAB_PCDS_PATCHABLE_LOAD_FIX_ADDRESS_PEI_PAGE_SIZE_DATA_TYPE = 'UINT32'
+@@ -285,6 +299,7 @@ TAB_DEPEX_X64 = TAB_DEPEX + TAB_SPLIT + TAB_ARCH_X64
+ TAB_DEPEX_ARM = TAB_DEPEX + TAB_SPLIT + TAB_ARCH_ARM
+ TAB_DEPEX_EBC = TAB_DEPEX + TAB_SPLIT + TAB_ARCH_EBC
+ TAB_DEPEX_AARCH64 = TAB_DEPEX + TAB_SPLIT + TAB_ARCH_AARCH64
++TAB_DEPEX_LOONGARCH64 = TAB_DEPEX + TAB_SPLIT + TAB_ARCH_LOONGARCH64
+
+ TAB_SKUIDS = 'SkuIds'
+ TAB_DEFAULT_STORES = 'DefaultStores'
+@@ -297,6 +312,7 @@ TAB_LIBRARIES_X64 = TAB_LIBRARIES + TAB_SPLIT + TAB_ARCH_X64
+ TAB_LIBRARIES_ARM = TAB_LIBRARIES + TAB_SPLIT + TAB_ARCH_ARM
+ TAB_LIBRARIES_EBC = TAB_LIBRARIES + TAB_SPLIT + TAB_ARCH_EBC
+ TAB_LIBRARIES_AARCH64 = TAB_LIBRARIES + TAB_SPLIT + TAB_ARCH_AARCH64
++TAB_LIBRARIES_LOONGARCH64 = TAB_LIBRARIES + TAB_SPLIT + TAB_ARCH_LOONGARCH64
+
+ TAB_COMPONENTS = 'Components'
+ TAB_COMPONENTS_COMMON = TAB_COMPONENTS + TAB_SPLIT + TAB_ARCH_COMMON
+@@ -305,6 +321,7 @@ TAB_COMPONENTS_X64 = TAB_COMPONENTS + TAB_SPLIT + TAB_ARCH_X64
+ TAB_COMPONENTS_ARM = TAB_COMPONENTS + TAB_SPLIT + TAB_ARCH_ARM
+ TAB_COMPONENTS_EBC = TAB_COMPONENTS + TAB_SPLIT + TAB_ARCH_EBC
+ TAB_COMPONENTS_AARCH64 = TAB_COMPONENTS + TAB_SPLIT + TAB_ARCH_AARCH64
++TAB_COMPONENTS_LOONGARCH64 = TAB_COMPONENTS + TAB_SPLIT + TAB_ARCH_LOONGARCH64
+
+ TAB_BUILD_OPTIONS = 'BuildOptions'
+
+diff --git a/BaseTools/Source/Python/UPT/Library/DataType.py b/BaseTools/Source/Python/UPT/Library/DataType.py
+index bd21678..31ac3b6 100644
+--- a/BaseTools/Source/Python/UPT/Library/DataType.py
++++ b/BaseTools/Source/Python/UPT/Library/DataType.py
+@@ -367,10 +367,11 @@ TAB_ARCH_IA32 = 'IA32'
+ TAB_ARCH_X64 = 'X64'
+ TAB_ARCH_IPF = 'IPF'
+ TAB_ARCH_ARM = 'ARM'
++TAB_ARCH_LOONGARCH64 = 'LOONGARCH64'
+ TAB_ARCH_EBC = 'EBC'
+
+ ARCH_LIST = \
+-[TAB_ARCH_IA32, TAB_ARCH_X64, TAB_ARCH_IPF, TAB_ARCH_ARM, TAB_ARCH_EBC]
++[TAB_ARCH_IA32, TAB_ARCH_X64, TAB_ARCH_IPF, TAB_ARCH_ARM, TAB_ARCH_LOONGARCH64, TAB_ARCH_EBC]
+
+ SUP_MODULE_BASE = 'BASE'
+ SUP_MODULE_SEC = 'SEC'
+@@ -454,6 +455,7 @@ TAB_SOURCES_IA32 = TAB_SOURCES + TAB_SPLIT + TAB_ARCH_IA32
+ TAB_SOURCES_X64 = TAB_SOURCES + TAB_SPLIT + TAB_ARCH_X64
+ TAB_SOURCES_IPF = TAB_SOURCES + TAB_SPLIT + TAB_ARCH_IPF
+ TAB_SOURCES_ARM = TAB_SOURCES + TAB_SPLIT + TAB_ARCH_ARM
++TAB_SOURCES_LOONGARCH64 = TAB_SOURCES + TAB_SPLIT + TAB_ARCH_LOONGARCH64
+ TAB_SOURCES_EBC = TAB_SOURCES + TAB_SPLIT + TAB_ARCH_EBC
+
+ TAB_BINARIES = 'Binaries'
+@@ -462,6 +464,7 @@ TAB_BINARIES_IA32 = TAB_BINARIES + TAB_SPLIT + TAB_ARCH_IA32
+ TAB_BINARIES_X64 = TAB_BINARIES + TAB_SPLIT + TAB_ARCH_X64
+ TAB_BINARIES_IPF = TAB_BINARIES + TAB_SPLIT + TAB_ARCH_IPF
+ TAB_BINARIES_ARM = TAB_BINARIES + TAB_SPLIT + TAB_ARCH_ARM
++TAB_BINARIES_LOONGARCH64 = TAB_BINARIES + TAB_SPLIT + TAB_ARCH_LOONGARCH64
+ TAB_BINARIES_EBC = TAB_BINARIES + TAB_SPLIT + TAB_ARCH_EBC
+
+ TAB_INCLUDES = 'Includes'
+@@ -470,6 +473,7 @@ TAB_INCLUDES_IA32 = TAB_INCLUDES + TAB_SPLIT + TAB_ARCH_IA32
+ TAB_INCLUDES_X64 = TAB_INCLUDES + TAB_SPLIT + TAB_ARCH_X64
+ TAB_INCLUDES_IPF = TAB_INCLUDES + TAB_SPLIT + TAB_ARCH_IPF
+ TAB_INCLUDES_ARM = TAB_INCLUDES + TAB_SPLIT + TAB_ARCH_ARM
++TAB_INCLUDES_LOONGARCH64 = TAB_INCLUDES + TAB_SPLIT + TAB_ARCH_LOONGARCH64
+ TAB_INCLUDES_EBC = TAB_INCLUDES + TAB_SPLIT + TAB_ARCH_EBC
+
+ TAB_GUIDS = 'Guids'
+@@ -478,6 +482,7 @@ TAB_GUIDS_IA32 = TAB_GUIDS + TAB_SPLIT + TAB_ARCH_IA32
+ TAB_GUIDS_X64 = TAB_GUIDS + TAB_SPLIT + TAB_ARCH_X64
+ TAB_GUIDS_IPF = TAB_GUIDS + TAB_SPLIT + TAB_ARCH_IPF
+ TAB_GUIDS_ARM = TAB_GUIDS + TAB_SPLIT + TAB_ARCH_ARM
++TAB_GUIDS_LOONGARCH64 = TAB_GUIDS + TAB_SPLIT + TAB_ARCH_LOONGARCH64
+ TAB_GUIDS_EBC = TAB_GUIDS + TAB_SPLIT + TAB_ARCH_EBC
+
+ TAB_PROTOCOLS = 'Protocols'
+@@ -486,6 +491,7 @@ TAB_PROTOCOLS_IA32 = TAB_PROTOCOLS + TAB_SPLIT + TAB_ARCH_IA32
+ TAB_PROTOCOLS_X64 = TAB_PROTOCOLS + TAB_SPLIT + TAB_ARCH_X64
+ TAB_PROTOCOLS_IPF = TAB_PROTOCOLS + TAB_SPLIT + TAB_ARCH_IPF
+ TAB_PROTOCOLS_ARM = TAB_PROTOCOLS + TAB_SPLIT + TAB_ARCH_ARM
++TAB_PROTOCOLS_LOONGARCH64 = TAB_PROTOCOLS + TAB_SPLIT + TAB_ARCH_LOONGARCH64
+ TAB_PROTOCOLS_EBC = TAB_PROTOCOLS + TAB_SPLIT + TAB_ARCH_EBC
+
+ TAB_PPIS = 'Ppis'
+@@ -494,6 +500,7 @@ TAB_PPIS_IA32 = TAB_PPIS + TAB_SPLIT + TAB_ARCH_IA32
+ TAB_PPIS_X64 = TAB_PPIS + TAB_SPLIT + TAB_ARCH_X64
+ TAB_PPIS_IPF = TAB_PPIS + TAB_SPLIT + TAB_ARCH_IPF
+ TAB_PPIS_ARM = TAB_PPIS + TAB_SPLIT + TAB_ARCH_ARM
++TAB_PPIS_LOONGARCH64 = TAB_PPIS + TAB_SPLIT + TAB_ARCH_LOONGARCH64
+ TAB_PPIS_EBC = TAB_PPIS + TAB_SPLIT + TAB_ARCH_EBC
+
+ TAB_LIBRARY_CLASSES = 'LibraryClasses'
+@@ -502,6 +509,7 @@ TAB_LIBRARY_CLASSES_IA32 = TAB_LIBRARY_CLASSES + TAB_SPLIT + TAB_ARCH_IA32
+ TAB_LIBRARY_CLASSES_X64 = TAB_LIBRARY_CLASSES + TAB_SPLIT + TAB_ARCH_X64
+ TAB_LIBRARY_CLASSES_IPF = TAB_LIBRARY_CLASSES + TAB_SPLIT + TAB_ARCH_IPF
+ TAB_LIBRARY_CLASSES_ARM = TAB_LIBRARY_CLASSES + TAB_SPLIT + TAB_ARCH_ARM
++TAB_LIBRARY_CLASSES_LOONGARCH64 = TAB_LIBRARY_CLASSES + TAB_SPLIT + TAB_ARCH_LOONGARCH64
+ TAB_LIBRARY_CLASSES_EBC = TAB_LIBRARY_CLASSES + TAB_SPLIT + TAB_ARCH_EBC
+
+ TAB_PACKAGES = 'Packages'
+@@ -510,6 +518,7 @@ TAB_PACKAGES_IA32 = TAB_PACKAGES + TAB_SPLIT + TAB_ARCH_IA32
+ TAB_PACKAGES_X64 = TAB_PACKAGES + TAB_SPLIT + TAB_ARCH_X64
+ TAB_PACKAGES_IPF = TAB_PACKAGES + TAB_SPLIT + TAB_ARCH_IPF
+ TAB_PACKAGES_ARM = TAB_PACKAGES + TAB_SPLIT + TAB_ARCH_ARM
++TAB_PACKAGES_LOONGARCH64 = TAB_PACKAGES + TAB_SPLIT + TAB_ARCH_LOONGARCH64
+ TAB_PACKAGES_EBC = TAB_PACKAGES + TAB_SPLIT + TAB_ARCH_EBC
+
+ TAB_PCDS = 'Pcds'
+@@ -548,6 +557,8 @@ TAB_PCDS_FIXED_AT_BUILD_IPF = TAB_PCDS + TAB_PCDS_FIXED_AT_BUILD + \
+ TAB_SPLIT + TAB_ARCH_IPF
+ TAB_PCDS_FIXED_AT_BUILD_ARM = TAB_PCDS + TAB_PCDS_FIXED_AT_BUILD + \
+ TAB_SPLIT + TAB_ARCH_ARM
++TAB_PCDS_FIXED_AT_BUILD_LOONGARCH64 = TAB_PCDS + TAB_PCDS_FIXED_AT_BUILD + \
++TAB_SPLIT + TAB_ARCH_LOONGARCH64
+ TAB_PCDS_FIXED_AT_BUILD_EBC = TAB_PCDS + TAB_PCDS_FIXED_AT_BUILD + \
+ TAB_SPLIT + TAB_ARCH_EBC
+
+@@ -562,6 +573,8 @@ TAB_PCDS_PATCHABLE_IN_MODULE_IPF = TAB_PCDS + TAB_PCDS_PATCHABLE_IN_MODULE + \
+ TAB_SPLIT + TAB_ARCH_IPF
+ TAB_PCDS_PATCHABLE_IN_MODULE_ARM = TAB_PCDS + TAB_PCDS_PATCHABLE_IN_MODULE + \
+ TAB_SPLIT + TAB_ARCH_ARM
++TAB_PCDS_PATCHABLE_IN_MODULE_LOONGARCH64 = TAB_PCDS + TAB_PCDS_PATCHABLE_IN_MODULE + \
++TAB_SPLIT + TAB_ARCH_LOONGARCH64
+ TAB_PCDS_PATCHABLE_IN_MODULE_EBC = TAB_PCDS + TAB_PCDS_PATCHABLE_IN_MODULE + \
+ TAB_SPLIT + TAB_ARCH_EBC
+
+@@ -576,6 +589,8 @@ TAB_PCDS_FEATURE_FLAG_IPF = TAB_PCDS + TAB_PCDS_FEATURE_FLAG + TAB_SPLIT + \
+ TAB_ARCH_IPF
+ TAB_PCDS_FEATURE_FLAG_ARM = TAB_PCDS + TAB_PCDS_FEATURE_FLAG + TAB_SPLIT + \
+ TAB_ARCH_ARM
++TAB_PCDS_FEATURE_FLAG_LOONGARCH64 = TAB_PCDS + TAB_PCDS_FEATURE_FLAG + TAB_SPLIT + \
++TAB_ARCH_LOONGARCH64
+ TAB_PCDS_FEATURE_FLAG_EBC = TAB_PCDS + TAB_PCDS_FEATURE_FLAG + TAB_SPLIT + \
+ TAB_ARCH_EBC
+
+@@ -593,6 +608,8 @@ TAB_PCDS_DYNAMIC_EX_IPF = TAB_PCDS + TAB_PCDS_DYNAMIC_EX + TAB_SPLIT + \
+ TAB_ARCH_IPF
+ TAB_PCDS_DYNAMIC_EX_ARM = TAB_PCDS + TAB_PCDS_DYNAMIC_EX + TAB_SPLIT + \
+ TAB_ARCH_ARM
++TAB_PCDS_DYNAMIC_EX_LOONGARCH64 = TAB_PCDS + TAB_PCDS_DYNAMIC_EX + TAB_SPLIT + \
++TAB_ARCH_LOONGARCH64
+ TAB_PCDS_DYNAMIC_EX_EBC = TAB_PCDS + TAB_PCDS_DYNAMIC_EX + TAB_SPLIT + \
+ TAB_ARCH_EBC
+
+@@ -606,6 +623,7 @@ TAB_PCDS_DYNAMIC_IA32 = TAB_PCDS + TAB_PCDS_DYNAMIC + TAB_SPLIT + TAB_ARCH_IA32
+ TAB_PCDS_DYNAMIC_X64 = TAB_PCDS + TAB_PCDS_DYNAMIC + TAB_SPLIT + TAB_ARCH_X64
+ TAB_PCDS_DYNAMIC_IPF = TAB_PCDS + TAB_PCDS_DYNAMIC + TAB_SPLIT + TAB_ARCH_IPF
+ TAB_PCDS_DYNAMIC_ARM = TAB_PCDS + TAB_PCDS_DYNAMIC + TAB_SPLIT + TAB_ARCH_ARM
++TAB_PCDS_DYNAMIC_LOONGARCH64 = TAB_PCDS + TAB_PCDS_DYNAMIC + TAB_SPLIT + TAB_ARCH_LOONGARCH64
+ TAB_PCDS_DYNAMIC_EBC = TAB_PCDS + TAB_PCDS_DYNAMIC + TAB_SPLIT + TAB_ARCH_EBC
+
+ TAB_PCD_DYNAMIC_TYPE_LIST = [TAB_PCDS_DYNAMIC_DEFAULT_NULL, \
+@@ -646,6 +664,7 @@ TAB_DEPEX_IA32 = TAB_DEPEX + TAB_SPLIT + TAB_ARCH_IA32
+ TAB_DEPEX_X64 = TAB_DEPEX + TAB_SPLIT + TAB_ARCH_X64
+ TAB_DEPEX_IPF = TAB_DEPEX + TAB_SPLIT + TAB_ARCH_IPF
+ TAB_DEPEX_ARM = TAB_DEPEX + TAB_SPLIT + TAB_ARCH_ARM
++TAB_DEPEX_LOONGARCH64 = TAB_DEPEX + TAB_SPLIT + TAB_ARCH_LOONGARCH64
+ TAB_DEPEX_EBC = TAB_DEPEX + TAB_SPLIT + TAB_ARCH_EBC
+
+ TAB_SKUIDS = 'SkuIds'
+@@ -656,6 +675,7 @@ TAB_LIBRARIES_IA32 = TAB_LIBRARIES + TAB_SPLIT + TAB_ARCH_IA32
+ TAB_LIBRARIES_X64 = TAB_LIBRARIES + TAB_SPLIT + TAB_ARCH_X64
+ TAB_LIBRARIES_IPF = TAB_LIBRARIES + TAB_SPLIT + TAB_ARCH_IPF
+ TAB_LIBRARIES_ARM = TAB_LIBRARIES + TAB_SPLIT + TAB_ARCH_ARM
++TAB_LIBRARIES_LOONGARCH64 = TAB_LIBRARIES + TAB_SPLIT + TAB_ARCH_LOONGARCH64
+ TAB_LIBRARIES_EBC = TAB_LIBRARIES + TAB_SPLIT + TAB_ARCH_EBC
+
+ TAB_COMPONENTS = 'Components'
+@@ -664,6 +684,7 @@ TAB_COMPONENTS_IA32 = TAB_COMPONENTS + TAB_SPLIT + TAB_ARCH_IA32
+ TAB_COMPONENTS_X64 = TAB_COMPONENTS + TAB_SPLIT + TAB_ARCH_X64
+ TAB_COMPONENTS_IPF = TAB_COMPONENTS + TAB_SPLIT + TAB_ARCH_IPF
+ TAB_COMPONENTS_ARM = TAB_COMPONENTS + TAB_SPLIT + TAB_ARCH_ARM
++TAB_COMPONENTS_LOONGARCH64 = TAB_COMPONENTS + TAB_SPLIT + TAB_ARCH_LOONGARCH64
+ TAB_COMPONENTS_EBC = TAB_COMPONENTS + TAB_SPLIT + TAB_ARCH_EBC
+
+ TAB_BUILD_OPTIONS = 'BuildOptions'
+diff --git a/BaseTools/Source/Python/build/buildoptions.py b/BaseTools/Source/Python/build/buildoptions.py
+index 094af4e..0d6e8cb 100644
+--- a/BaseTools/Source/Python/build/buildoptions.py
++++ b/BaseTools/Source/Python/build/buildoptions.py
+@@ -4,6 +4,7 @@
+ # Copyright (c) 2014, Hewlett-Packard Development Company, L.P.
+ # Copyright (c) 2007 - 2019, Intel Corporation. All rights reserved.
+ # Copyright (c) 2018 - 2020, Hewlett Packard Enterprise Development, L.P.
++# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
+ #
+ # SPDX-License-Identifier: BSD-2-Clause-Patent
+ #
+@@ -40,8 +41,8 @@ class MyOptionParser():
+
+ def GetOption(self):
+ Parser = OptionParser(description=__copyright__, version=__version__, prog="build.exe", usage="%prog [options] [all|fds|genc|genmake|clean|cleanall|cleanlib|modules|libraries|run]")
+- Parser.add_option("-a", "--arch", action="append", type="choice", choices=['IA32', 'X64', 'EBC', 'ARM', 'AARCH64', 'RISCV64'], dest="TargetArch",
+- help="ARCHS is one of list: IA32, X64, ARM, AARCH64, RISCV64 or EBC, which overrides target.txt's TARGET_ARCH definition. To specify more archs, please repeat this option.")
++ Parser.add_option("-a", "--arch", action="append", type="choice", choices=['IA32', 'X64', 'EBC', 'ARM', 'AARCH64', 'RISCV64', 'LOONGARCH64'], dest="TargetArch",
++ help="ARCHS is one of list: IA32, X64, ARM, AARCH64, RISCV64, LOONGARCH64 or EBC, which overrides target.txt's TARGET_ARCH definition. To specify more archs, please repeat this option.")
+ Parser.add_option("-p", "--platform", action="callback", type="string", dest="PlatformFile", callback=SingleCheckCallback,
+ help="Build the platform specified by the DSC file name argument, overriding target.txt's ACTIVE_PLATFORM definition.")
+ Parser.add_option("-m", "--module", action="callback", type="string", dest="ModuleFile", callback=SingleCheckCallback,
+diff --git a/CryptoPkg/CryptoPkg.dsc b/CryptoPkg/CryptoPkg.dsc
+index 55383f2..7a4cd1b 100644
+--- a/CryptoPkg/CryptoPkg.dsc
++++ b/CryptoPkg/CryptoPkg.dsc
+@@ -19,7 +19,7 @@
+ PLATFORM_VERSION = 0.98
+ DSC_SPECIFICATION = 0x00010005
+ OUTPUT_DIRECTORY = Build/CryptoPkg
+- SUPPORTED_ARCHITECTURES = IA32|X64|ARM|AARCH64|RISCV64
++ SUPPORTED_ARCHITECTURES = IA32|X64|ARM|AARCH64|RISCV64|LOONGARCH64
+ BUILD_TARGETS = DEBUG|RELEASE|NOOPT
+ SKUID_IDENTIFIER = DEFAULT
+
+diff --git a/CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf b/CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf
+index 4aae2ab..4229b3a 100644
+--- a/CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf
++++ b/CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf
+@@ -8,6 +8,7 @@
+ #
+ # Copyright (c) 2009 - 2020, Intel Corporation. All rights reserved.
+ # Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
++# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
+ # SPDX-License-Identifier: BSD-2-Clause-Patent
+ #
+ ##
+@@ -24,7 +25,7 @@
+ #
+ # The following information is for reference only and not required by the build tools.
+ #
+-# VALID_ARCHITECTURES = IA32 X64 ARM AARCH64 RISCV64
++# VALID_ARCHITECTURES = IA32 X64 ARM AARCH64 RISCV64 LOONGARCH64
+ #
+
+ [Sources]
+@@ -71,6 +72,9 @@
+ [Sources.RISCV64]
+ Rand/CryptRand.c
+
++[Sources.LOONGARCH64]
++ Rand/CryptRand.c
++
+ [Packages]
+ MdePkg/MdePkg.dec
+ CryptoPkg/CryptoPkg.dec
+diff --git a/CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf b/CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf
+index 70c985e..b3f49b2 100644
+--- a/CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf
++++ b/CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf
+@@ -13,6 +13,7 @@
+ #
+ # Copyright (c) 2009 - 2020, Intel Corporation. All rights reserved.
+ # Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
++# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
+ # SPDX-License-Identifier: BSD-2-Clause-Patent
+ #
+ ##
+@@ -76,6 +77,9 @@
+ [Sources.RISCV64]
+ Rand/CryptRand.c
+
++[Sources.LOONGARCH64]
++ Rand/CryptRand.c
++
+ [Packages]
+ MdePkg/MdePkg.dec
+ CryptoPkg/CryptoPkg.dec
+diff --git a/CryptoPkg/Library/BaseCryptLibNull/BaseCryptLibNull.inf b/CryptoPkg/Library/BaseCryptLibNull/BaseCryptLibNull.inf
+index 689af4f..347f132 100644
+--- a/CryptoPkg/Library/BaseCryptLibNull/BaseCryptLibNull.inf
++++ b/CryptoPkg/Library/BaseCryptLibNull/BaseCryptLibNull.inf
+@@ -8,6 +8,7 @@
+ #
+ # Copyright (c) 2009 - 2020, Intel Corporation. All rights reserved.
+ # Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
++# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
+ # SPDX-License-Identifier: BSD-2-Clause-Patent
+ #
+ ##
+@@ -24,7 +25,7 @@
+ #
+ # The following information is for reference only and not required by the build tools.
+ #
+-# VALID_ARCHITECTURES = IA32 X64 ARM AARCH64 RISCV64
++# VALID_ARCHITECTURES = IA32 X64 ARM AARCH64 RISCV64 LOONGARCH64
+ #
+
+ [Sources]
+diff --git a/CryptoPkg/Library/BaseCryptLibOnProtocolPpi/DxeCryptLib.inf b/CryptoPkg/Library/BaseCryptLibOnProtocolPpi/DxeCryptLib.inf
+index baa4433..b4945de 100644
+--- a/CryptoPkg/Library/BaseCryptLibOnProtocolPpi/DxeCryptLib.inf
++++ b/CryptoPkg/Library/BaseCryptLibOnProtocolPpi/DxeCryptLib.inf
+@@ -4,6 +4,7 @@
+ #
+ # Copyright (C) Microsoft Corporation. All rights reserved.
+ # Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
++# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
+ # SPDX-License-Identifier: BSD-2-Clause-Patent
+ #
+ ##
+@@ -22,7 +23,7 @@
+ #
+ # The following information is for reference only and not required by the build tools.
+ #
+-# VALID_ARCHITECTURES = IA32 X64 ARM AARCH64 RISCV64
++# VALID_ARCHITECTURES = IA32 X64 ARM AARCH64 RISCV64 LOONGARCH64
+ #
+
+ [Packages]
+diff --git a/CryptoPkg/Library/BaseCryptLibOnProtocolPpi/PeiCryptLib.inf b/CryptoPkg/Library/BaseCryptLibOnProtocolPpi/PeiCryptLib.inf
+index 038ca71..e7d153d 100644
+--- a/CryptoPkg/Library/BaseCryptLibOnProtocolPpi/PeiCryptLib.inf
++++ b/CryptoPkg/Library/BaseCryptLibOnProtocolPpi/PeiCryptLib.inf
+@@ -4,6 +4,7 @@
+ #
+ # Copyright (C) Microsoft Corporation. All rights reserved.
+ # Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
++# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
+ # SPDX-License-Identifier: BSD-2-Clause-Patent
+ #
+ ##
+@@ -21,7 +22,7 @@
+ #
+ # The following information is for reference only and not required by the build tools.
+ #
+-# VALID_ARCHITECTURES = IA32 X64 ARM AARCH64 RISCV64
++# VALID_ARCHITECTURES = IA32 X64 ARM AARCH64 RISCV64 LOONGARCH64
+ #
+
+ [Packages]
+diff --git a/CryptoPkg/Library/Include/CrtLibSupport.h b/CryptoPkg/Library/Include/CrtLibSupport.h
+index 7a82f1d..74e7553 100644
+--- a/CryptoPkg/Library/Include/CrtLibSupport.h
++++ b/CryptoPkg/Library/Include/CrtLibSupport.h
+@@ -4,6 +4,7 @@
+
+ Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.
+ Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
++Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ **/
+@@ -44,7 +45,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ #define CONFIG_HEADER_BN_H
+
+-#if defined(MDE_CPU_X64) || defined(MDE_CPU_AARCH64) || defined(MDE_CPU_IA64) || defined(MDE_CPU_RISCV64)
++#if defined(MDE_CPU_X64) || defined(MDE_CPU_AARCH64) || defined(MDE_CPU_IA64) || defined(MDE_CPU_RISCV64) || defined(MDE_CPU_LOONGARCH64)
+ //
+ // With GCC we would normally use SIXTY_FOUR_BIT_LONG, but MSVC needs
+ // SIXTY_FOUR_BIT, because 'long' is 32-bit and only 'long long' is
+diff --git a/CryptoPkg/Library/OpensslLib/OpensslLib.inf b/CryptoPkg/Library/OpensslLib/OpensslLib.inf
+index ec5be59..6780840 100644
+--- a/CryptoPkg/Library/OpensslLib/OpensslLib.inf
++++ b/CryptoPkg/Library/OpensslLib/OpensslLib.inf
+@@ -3,6 +3,7 @@
+ #
+ # Copyright (c) 2010 - 2020, Intel Corporation. All rights reserved.
+ # (C) Copyright 2020 Hewlett Packard Enterprise Development LP
++# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
+ # SPDX-License-Identifier: BSD-2-Clause-Patent
+ #
+ ##
+@@ -623,6 +624,7 @@
+ GCC:*_*_ARM_CC_FLAGS = $(OPENSSL_FLAGS) -Wno-error=maybe-uninitialized -Wno-error=unused-but-set-variable
+ GCC:*_*_AARCH64_CC_FLAGS = $(OPENSSL_FLAGS) -Wno-error=maybe-uninitialized -Wno-format -Wno-error=unused-but-set-variable
+ GCC:*_*_RISCV64_CC_FLAGS = $(OPENSSL_FLAGS) -Wno-error=maybe-uninitialized -Wno-format -Wno-error=unused-but-set-variable
++ GCC:*_*_LOONGARCH64_CC_FLAGS = $(OPENSSL_FLAGS) -Wno-error=maybe-uninitialized -Wno-format -Wno-error=unused-but-set-variable
+ GCC:*_CLANG35_*_CC_FLAGS = -std=c99 -Wno-error=uninitialized
+ GCC:*_CLANG38_*_CC_FLAGS = -std=c99 -Wno-error=uninitialized
+ GCC:*_CLANGPDB_*_CC_FLAGS = -std=c99 -Wno-error=uninitialized -Wno-error=incompatible-pointer-types -Wno-error=pointer-sign -Wno-error=implicit-function-declaration -Wno-error=ignored-pragma-optimize
+diff --git a/CryptoPkg/Library/OpensslLib/OpensslLibCrypto.inf b/CryptoPkg/Library/OpensslLib/OpensslLibCrypto.inf
+index ee68e48..e5ca330 100644
+--- a/CryptoPkg/Library/OpensslLib/OpensslLibCrypto.inf
++++ b/CryptoPkg/Library/OpensslLib/OpensslLibCrypto.inf
+@@ -3,6 +3,7 @@
+ #
+ # Copyright (c) 2010 - 2020, Intel Corporation. All rights reserved.
+ # (C) Copyright 2020 Hewlett Packard Enterprise Development LP
++# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
+ # SPDX-License-Identifier: BSD-2-Clause-Patent
+ #
+ ##
+@@ -572,6 +573,7 @@
+ GCC:*_*_ARM_CC_FLAGS = $(OPENSSL_FLAGS) -Wno-error=maybe-uninitialized -Wno-error=unused-but-set-variable
+ GCC:*_*_AARCH64_CC_FLAGS = $(OPENSSL_FLAGS) -Wno-error=maybe-uninitialized -Wno-format -Wno-error=unused-but-set-variable
+ GCC:*_*_RISCV64_CC_FLAGS = $(OPENSSL_FLAGS) -Wno-error=maybe-uninitialized -Wno-format -Wno-error=unused-but-set-variable
++ GCC:*_*_LOONGARCH64_CC_FLAGS = $(OPENSSL_FLAGS) -Wno-error=maybe-uninitialized -Wno-format -Wno-error=unused-but-set-variable
+ GCC:*_CLANG35_*_CC_FLAGS = -std=c99 -Wno-error=uninitialized
+ GCC:*_CLANG38_*_CC_FLAGS = -std=c99 -Wno-error=uninitialized
+ GCC:*_CLANGPDB_*_CC_FLAGS = -std=c99 -Wno-error=uninitialized -Wno-error=incompatible-pointer-types -Wno-error=pointer-sign -Wno-error=implicit-function-declaration -Wno-error=ignored-pragma-optimize
+diff --git a/CryptoPkg/Library/TlsLib/TlsLib.inf b/CryptoPkg/Library/TlsLib/TlsLib.inf
+index 27209f4..e63e268 100644
+--- a/CryptoPkg/Library/TlsLib/TlsLib.inf
++++ b/CryptoPkg/Library/TlsLib/TlsLib.inf
+@@ -3,6 +3,7 @@
+ #
+ # Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
+ # (C) Copyright 2016-2020 Hewlett Packard Enterprise Development LP
++# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
+ # SPDX-License-Identifier: BSD-2-Clause-Patent
+ #
+ ##
+@@ -19,7 +20,7 @@
+ #
+ # The following information is for reference only and not required by the build tools.
+ #
+-# VALID_ARCHITECTURES = IA32 X64 ARM AARCH64 RISCV64
++# VALID_ARCHITECTURES = IA32 X64 ARM AARCH64 RISCV64 LOONGARCH64
+ #
+
+ [Sources]
+diff --git a/CryptoPkg/Library/TlsLibNull/TlsLibNull.inf b/CryptoPkg/Library/TlsLibNull/TlsLibNull.inf
+index b2920dd..12d7cc7 100644
+--- a/CryptoPkg/Library/TlsLibNull/TlsLibNull.inf
++++ b/CryptoPkg/Library/TlsLibNull/TlsLibNull.inf
+@@ -3,6 +3,7 @@
+ #
+ # Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
+ # (C) Copyright 2016-2020 Hewlett Packard Enterprise Development LP
++# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
+ # SPDX-License-Identifier: BSD-2-Clause-Patent
+ #
+ ##
+@@ -19,7 +20,7 @@
+ #
+ # The following information is for reference only and not required by the build tools.
+ #
+-# VALID_ARCHITECTURES = IA32 X64 ARM AARCH64 RISCV64
++# VALID_ARCHITECTURES = IA32 X64 ARM AARCH64 RISCV64 LOONGARCH64
+ #
+
+ [Sources]
+diff --git a/FatPkg/FatPkg.dsc b/FatPkg/FatPkg.dsc
+index d862560..da969c4 100644
+--- a/FatPkg/FatPkg.dsc
++++ b/FatPkg/FatPkg.dsc
+@@ -15,7 +15,7 @@
+ PLATFORM_GUID = 25b55dbc-9d0b-4a32-80da-46e1273d622c
+ PLATFORM_VERSION = 0.3
+ DSC_SPECIFICATION = 0x00010005
+- SUPPORTED_ARCHITECTURES = IA32|X64|EBC|ARM|AARCH64|RISCV64
++ SUPPORTED_ARCHITECTURES = IA32|X64|EBC|ARM|AARCH64|RISCV64|LOONGARCH64
+ OUTPUT_DIRECTORY = Build/Fat
+ BUILD_TARGETS = DEBUG|RELEASE|NOOPT
+ SKUID_IDENTIFIER = DEFAULT
+diff --git a/FmpDevicePkg/FmpDevicePkg.dsc b/FmpDevicePkg/FmpDevicePkg.dsc
+index cfeadd8..6ac9d2e 100644
+--- a/FmpDevicePkg/FmpDevicePkg.dsc
++++ b/FmpDevicePkg/FmpDevicePkg.dsc
+@@ -20,7 +20,7 @@
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x00010005
+ OUTPUT_DIRECTORY = Build/FmpDevicePkg
+- SUPPORTED_ARCHITECTURES = IA32|X64|ARM|AARCH64|RISCV64
++ SUPPORTED_ARCHITECTURES = IA32|X64|ARM|AARCH64|RISCV64|LOONGARCH64
+ BUILD_TARGETS = DEBUG|RELEASE|NOOPT
+ SKUID_IDENTIFIER = DEFAULT
+
+diff --git a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+index 19b8a4c..052ea0e 100644
+--- a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
++++ b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+@@ -8,6 +8,7 @@
+ # Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
+ # Copyright (c) 2017, AMD Incorporated. All rights reserved.
+ # Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
++# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
+ #
+ # SPDX-License-Identifier: BSD-2-Clause-Patent
+ #
+@@ -26,7 +27,7 @@
+ #
+ # The following information is for reference only and not required by the build tools.
+ #
+-# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only) AARCH64 RISCV64
++# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only) AARCH64 RISCV64 LOONGARCH64
+ #
+
+ [Sources]
+@@ -53,6 +54,9 @@
+ [Sources.RISCV64]
+ RiscV64/DxeLoadFunc.c
+
++[Sources.LOONGARCH64]
++ LoongArch64/DxeLoadFunc.c
++
+ [Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+diff --git a/MdeModulePkg/Logo/Logo.inf b/MdeModulePkg/Logo/Logo.inf
+index 70a66ca..294482c 100644
+--- a/MdeModulePkg/Logo/Logo.inf
++++ b/MdeModulePkg/Logo/Logo.inf
+@@ -3,6 +3,7 @@
+ #
+ # Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ # Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
++# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
+
+ #
+ # SPDX-License-Identifier: BSD-2-Clause-Patent
+@@ -21,7 +22,7 @@
+ #
+ # The following information is for reference only and not required by the build tools.
+ #
+-# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64
++# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64 LOONGARCH64
+ #
+
+ [Binaries]
+diff --git a/MdeModulePkg/MdeModulePkg.dsc b/MdeModulePkg/MdeModulePkg.dsc
+index 90165ca..a6f933e 100644
+--- a/MdeModulePkg/MdeModulePkg.dsc
++++ b/MdeModulePkg/MdeModulePkg.dsc
+@@ -15,7 +15,7 @@
+ PLATFORM_VERSION = 0.98
+ DSC_SPECIFICATION = 0x00010005
+ OUTPUT_DIRECTORY = Build/MdeModule
+- SUPPORTED_ARCHITECTURES = IA32|X64|EBC|ARM|AARCH64|RISCV64
++ SUPPORTED_ARCHITECTURES = IA32|X64|EBC|ARM|AARCH64|RISCV64|LOONGARCH64
+ BUILD_TARGETS = DEBUG|RELEASE|NOOPT
+ SKUID_IDENTIFIER = DEFAULT
+
+@@ -186,7 +186,7 @@
+ #
+ NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf
+
+-[LibraryClasses.EBC, LibraryClasses.RISCV64]
++[LibraryClasses.EBC, LibraryClasses.RISCV64, LibraryClasses.LOONGARCH64]
+ LockBoxLib|MdeModulePkg/Library/LockBoxNullLib/LockBoxNullLib.inf
+
+ [PcdsFeatureFlag]
+diff --git a/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf b/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+index 8bf5035..601eada 100644
+--- a/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
++++ b/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+@@ -6,6 +6,7 @@
+ #
+ # Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.
+ # Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
++# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
+ # SPDX-License-Identifier: BSD-2-Clause-Patent
+ #
+ ##
+@@ -22,20 +23,20 @@
+ #
+ # The following information is for reference only and not required by the build tools.
+ #
+-# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64
++# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64 LOONGARCH64
+ #
+
+ [Sources]
+ CapsuleService.c
+ CapsuleService.h
+
+-[Sources.Ia32, Sources.EBC, Sources.ARM, Sources.AARCH64, Sources.RISCV64]
++[Sources.Ia32, Sources.EBC, Sources.ARM, Sources.AARCH64, Sources.RISCV64, Sources.LOONGARCH64]
+ SaveLongModeContext.c
+
+-[Sources.Ia32, Sources.X64, Sources.ARM, Sources.AARCH64, Sources.RISCV64]
++[Sources.Ia32, Sources.X64, Sources.ARM, Sources.AARCH64, Sources.RISCV64, Sources.LOONGARCH64]
+ CapsuleCache.c
+
+-[Sources.Ia32, Sources.X64, Sources.EBC, Sources.RISCV64]
++[Sources.Ia32, Sources.X64, Sources.EBC, Sources.RISCV64, Sources.LOONGARCH64]
+ CapsuleReset.c
+
+ [Sources.ARM, Sources.AARCH64]
+diff --git a/MdePkg/Include/IndustryStandard/Dhcp.h b/MdePkg/Include/IndustryStandard/Dhcp.h
+index 121c48c..4bc72d9 100644
+--- a/MdePkg/Include/IndustryStandard/Dhcp.h
++++ b/MdePkg/Include/IndustryStandard/Dhcp.h
+@@ -4,6 +4,7 @@
+
+ Copyright (c) 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
++ Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+ **/
+
+@@ -257,27 +258,31 @@ typedef enum {
+
+ ///
+ /// Processor Architecture Types
+-/// These identifiers are defined by IETF:
+-/// http://www.ietf.org/assignments/dhcpv6-parameters/dhcpv6-parameters.xml
++/// These identifiers are defined by IANA:
++/// https://www.iana.org/assignments/dhcpv6-parameters/dhcpv6-parameters.xhtml
+ ///
+-#define PXE_CLIENT_ARCH_X86_BIOS 0x0000 /// x86 BIOS for PXE
+-#define PXE_CLIENT_ARCH_IPF 0x0002 /// Itanium for PXE
+-#define PXE_CLIENT_ARCH_IA32 0x0006 /// x86 uefi for PXE
+-#define PXE_CLIENT_ARCH_X64 0x0007 /// x64 uefi for PXE
+-#define PXE_CLIENT_ARCH_EBC 0x0009 /// EBC for PXE
+-#define PXE_CLIENT_ARCH_ARM 0x000A /// Arm uefi 32 for PXE
+-#define PXE_CLIENT_ARCH_AARCH64 0x000B /// Arm uefi 64 for PXE
+-#define PXE_CLIENT_ARCH_RISCV32 0x0019 /// RISC-V uefi 32 for PXE
+-#define PXE_CLIENT_ARCH_RISCV64 0x001B /// RISC-V uefi 64 for PXE
+-#define PXE_CLIENT_ARCH_RISCV128 0x001D /// RISC-V uefi 128 for PXE
++#define PXE_CLIENT_ARCH_X86_BIOS 0x0000 /// x86 BIOS for PXE
++#define PXE_CLIENT_ARCH_IPF 0x0002 /// Itanium for PXE
++#define PXE_CLIENT_ARCH_IA32 0x0006 /// x86 uefi for PXE
++#define PXE_CLIENT_ARCH_X64 0x0007 /// x64 uefi for PXE
++#define PXE_CLIENT_ARCH_EBC 0x0009 /// EBC for PXE
++#define PXE_CLIENT_ARCH_ARM 0x000A /// Arm uefi 32 for PXE
++#define PXE_CLIENT_ARCH_AARCH64 0x000B /// Arm uefi 64 for PXE
++#define PXE_CLIENT_ARCH_RISCV32 0x0019 /// RISC-V uefi 32 for PXE
++#define PXE_CLIENT_ARCH_RISCV64 0x001B /// RISC-V uefi 64 for PXE
++#define PXE_CLIENT_ARCH_RISCV128 0x001D /// RISC-V uefi 128 for PXE
++#define PXE_CLIENT_ARCH_LOONGARCH32 0x0025 /// LoongArch uefi 32 for PXE
++#define PXE_CLIENT_ARCH_LOONGARCH64 0x0027 /// LoongArch uefi 64 for PXE
+
+-#define HTTP_CLIENT_ARCH_IA32 0x000F /// x86 uefi boot from http
+-#define HTTP_CLIENT_ARCH_X64 0x0010 /// x64 uefi boot from http
+-#define HTTP_CLIENT_ARCH_EBC 0x0011 /// EBC boot from http
+-#define HTTP_CLIENT_ARCH_ARM 0x0012 /// Arm uefi 32 boot from http
+-#define HTTP_CLIENT_ARCH_AARCH64 0x0013 /// Arm uefi 64 boot from http
+-#define HTTP_CLIENT_ARCH_RISCV32 0x001A /// RISC-V uefi 32 boot from http
+-#define HTTP_CLIENT_ARCH_RISCV64 0x001C /// RISC-V uefi 64 boot from http
+-#define HTTP_CLIENT_ARCH_RISCV128 0x001E /// RISC-V uefi 128 boot from http
++#define HTTP_CLIENT_ARCH_IA32 0x000F /// x86 uefi boot from http
++#define HTTP_CLIENT_ARCH_X64 0x0010 /// x64 uefi boot from http
++#define HTTP_CLIENT_ARCH_EBC 0x0011 /// EBC boot from http
++#define HTTP_CLIENT_ARCH_ARM 0x0012 /// Arm uefi 32 boot from http
++#define HTTP_CLIENT_ARCH_AARCH64 0x0013 /// Arm uefi 64 boot from http
++#define HTTP_CLIENT_ARCH_RISCV32 0x001A /// RISC-V uefi 32 boot from http
++#define HTTP_CLIENT_ARCH_RISCV64 0x001C /// RISC-V uefi 64 boot from http
++#define HTTP_CLIENT_ARCH_RISCV128 0x001E /// RISC-V uefi 128 boot from http
++#define HTTP_CLIENT_ARCH_LOONGARCH32 0x0026 /// LoongArch uefi 32 boot from http
++#define HTTP_CLIENT_ARCH_LOONGARCH64 0x0028 /// LoongArch uefi 64 boot from http
+
+ #endif
+diff --git a/MdePkg/Include/IndustryStandard/PeImage.h b/MdePkg/Include/IndustryStandard/PeImage.h
+index 9b26700..456ea74 100644
+--- a/MdePkg/Include/IndustryStandard/PeImage.h
++++ b/MdePkg/Include/IndustryStandard/PeImage.h
+@@ -10,6 +10,7 @@
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+ Portions Copyright (c) 2016 - 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
++Portions Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+@@ -39,6 +40,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
+ #define IMAGE_FILE_MACHINE_RISCV32 0x5032
+ #define IMAGE_FILE_MACHINE_RISCV64 0x5064
+ #define IMAGE_FILE_MACHINE_RISCV128 0x5128
++#define IMAGE_FILE_MACHINE_LOONGARCH32 0x6232
++#define IMAGE_FILE_MACHINE_LOONGARCH64 0x6264
+
+ //
+ // EXE file formats
+@@ -505,6 +508,12 @@ typedef struct {
+ #define EFI_IMAGE_REL_BASED_RISCV_LOW12I 7
+ #define EFI_IMAGE_REL_BASED_RISCV_LOW12S 8
+
++//
++// Relocation types of LoongArch processor.
++//
++#define EFI_IMAGE_REL_BASED_LOONGARCH32_MARK_LA 8
++#define EFI_IMAGE_REL_BASED_LOONGARCH64_MARK_LA 8
++
+ ///
+ /// Line number format.
+ ///
+diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
+index 1171a0f..dcf1d0a 100644
+--- a/MdePkg/Include/Library/BaseLib.h
++++ b/MdePkg/Include/Library/BaseLib.h
+@@ -6,6 +6,7 @@ Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
+ Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+ Copyright (c) Microsoft Corporation.
+ Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
++Portions Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+@@ -152,6 +153,29 @@ typedef struct {
+
+ #endif // defined (MDE_CPU_RISCV64)
+
++#if defined (MDE_CPU_LOONGARCH64)
++///
++/// The LoongArch architecture context buffer used by SetJump() and LongJump()
++///
++typedef struct {
++ UINT64 S0;
++ UINT64 S1;
++ UINT64 S2;
++ UINT64 S3;
++ UINT64 S4;
++ UINT64 S5;
++ UINT64 S6;
++ UINT64 S7;
++ UINT64 S8;
++ UINT64 SP;
++ UINT64 FP;
++ UINT64 RA;
++} BASE_LIBRARY_JUMP_BUFFER;
++
++#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8
++
++#endif // defined (MDE_CPU_LOONGARCH64)
++
+ //
+ // String Services
+ //
+diff --git a/MdePkg/Include/Protocol/DebugSupport.h b/MdePkg/Include/Protocol/DebugSupport.h
+index 7fb1d3b..91e108f 100644
+--- a/MdePkg/Include/Protocol/DebugSupport.h
++++ b/MdePkg/Include/Protocol/DebugSupport.h
+@@ -658,17 +658,110 @@ typedef struct {
+ UINT64 X31;
+ } EFI_SYSTEM_CONTEXT_RISCV64;
+
++//
++// LoongArch processor exception types.
++//
++#define EXCEPT_LOONGARCH_INT 0
++#define EXCEPT_LOONGARCH_PIL 1
++#define EXCEPT_LOONGARCH_PIS 2
++#define EXCEPT_LOONGARCH_PIF 3
++#define EXCEPT_LOONGARCH_PME 4
++#define EXCEPT_LOONGARCH_PNR 5
++#define EXCEPT_LOONGARCH_PNX 6
++#define EXCEPT_LOONGARCH_PPI 7
++#define EXCEPT_LOONGARCH_ADE 8
++#define EXCEPT_LOONGARCH_ALE 9
++#define EXCEPT_LOONGARCH_BCE 10
++#define EXCEPT_LOONGARCH_SYS 11
++#define EXCEPT_LOONGARCH_BRK 12
++#define EXCEPT_LOONGARCH_INE 13
++#define EXCEPT_LOONGARCH_IPE 14
++#define EXCEPT_LOONGARCH_FPD 15
++#define EXCEPT_LOONGARCH_SXD 16
++#define EXCEPT_LOONGARCH_ASXD 17
++#define EXCEPT_LOONGARCH_FPE 18
++#define EXCEPT_LOONGARCH_TBR 64 // For code only, there is no such type in the ISA spec, the TLB refill is defined for an independent exception.
++
++//
++// LoongArch processor Interrupt types.
++//
++#define EXCEPT_LOONGARCH_INT_SIP0 0
++#define EXCEPT_LOONGARCH_INT_SIP1 1
++#define EXCEPT_LOONGARCH_INT_IP0 2
++#define EXCEPT_LOONGARCH_INT_IP1 3
++#define EXCEPT_LOONGARCH_INT_IP2 4
++#define EXCEPT_LOONGARCH_INT_IP3 5
++#define EXCEPT_LOONGARCH_INT_IP4 6
++#define EXCEPT_LOONGARCH_INT_IP5 7
++#define EXCEPT_LOONGARCH_INT_IP6 8
++#define EXCEPT_LOONGARCH_INT_IP7 9
++#define EXCEPT_LOONGARCH_INT_PMC 10
++#define EXCEPT_LOONGARCH_INT_TIMER 11
++#define EXCEPT_LOONGARCH_INT_IPI 12
++
++//
++// For coding convenience, define the maximum valid
++// LoongArch interrupt.
++//
++#define MAX_LOONGARCH_INTERRUPT 14
++
++typedef struct {
++ UINT64 R0;
++ UINT64 R1;
++ UINT64 R2;
++ UINT64 R3;
++ UINT64 R4;
++ UINT64 R5;
++ UINT64 R6;
++ UINT64 R7;
++ UINT64 R8;
++ UINT64 R9;
++ UINT64 R10;
++ UINT64 R11;
++ UINT64 R12;
++ UINT64 R13;
++ UINT64 R14;
++ UINT64 R15;
++ UINT64 R16;
++ UINT64 R17;
++ UINT64 R18;
++ UINT64 R19;
++ UINT64 R20;
++ UINT64 R21;
++ UINT64 R22;
++ UINT64 R23;
++ UINT64 R24;
++ UINT64 R25;
++ UINT64 R26;
++ UINT64 R27;
++ UINT64 R28;
++ UINT64 R29;
++ UINT64 R30;
++ UINT64 R31;
++
++ UINT64 CRMD; // CuRrent MoDe information
++ UINT64 PRMD; // PRe-exception MoDe information
++ UINT64 EUEN; // Extended component Unit ENable
++ UINT64 MISC; // MISCellaneous controller
++ UINT64 ECFG; // Exception ConFiGuration
++ UINT64 ESTAT; // Exception STATus
++ UINT64 ERA; // Exception Return Address
++ UINT64 BADV; // BAD Virtual address
++ UINT64 BADI; // BAD Instruction
++} EFI_SYSTEM_CONTEXT_LOONGARCH64;
++
+ ///
+ /// Universal EFI_SYSTEM_CONTEXT definition.
+ ///
+ typedef union {
+- EFI_SYSTEM_CONTEXT_EBC *SystemContextEbc;
+- EFI_SYSTEM_CONTEXT_IA32 *SystemContextIa32;
+- EFI_SYSTEM_CONTEXT_X64 *SystemContextX64;
+- EFI_SYSTEM_CONTEXT_IPF *SystemContextIpf;
+- EFI_SYSTEM_CONTEXT_ARM *SystemContextArm;
+- EFI_SYSTEM_CONTEXT_AARCH64 *SystemContextAArch64;
+- EFI_SYSTEM_CONTEXT_RISCV64 *SystemContextRiscV64;
++ EFI_SYSTEM_CONTEXT_EBC *SystemContextEbc;
++ EFI_SYSTEM_CONTEXT_IA32 *SystemContextIa32;
++ EFI_SYSTEM_CONTEXT_X64 *SystemContextX64;
++ EFI_SYSTEM_CONTEXT_IPF *SystemContextIpf;
++ EFI_SYSTEM_CONTEXT_ARM *SystemContextArm;
++ EFI_SYSTEM_CONTEXT_AARCH64 *SystemContextAArch64;
++ EFI_SYSTEM_CONTEXT_RISCV64 *SystemContextRiscV64;
++ EFI_SYSTEM_CONTEXT_LOONGARCH64 *SystemContextLoongArch64;
+ } EFI_SYSTEM_CONTEXT;
+
+ //
+diff --git a/MdePkg/Include/Protocol/PxeBaseCode.h b/MdePkg/Include/Protocol/PxeBaseCode.h
+index c666d31..2d242c2 100644
+--- a/MdePkg/Include/Protocol/PxeBaseCode.h
++++ b/MdePkg/Include/Protocol/PxeBaseCode.h
+@@ -4,6 +4,7 @@
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
++Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+@@ -157,6 +158,8 @@ typedef UINT16 EFI_PXE_BASE_CODE_UDP_PORT;
+ #define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x000B
+ #elif defined (MDE_CPU_RISCV64)
+ #define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x001B
++#elif defined (MDE_CPU_LOONGARCH64)
++#define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x0027
+ #endif
+
+
+diff --git a/MdePkg/Include/Uefi/UefiBaseType.h b/MdePkg/Include/Uefi/UefiBaseType.h
+index 934fc07..2aa3aa6 100644
+--- a/MdePkg/Include/Uefi/UefiBaseType.h
++++ b/MdePkg/Include/Uefi/UefiBaseType.h
+@@ -248,6 +248,12 @@ typedef union {
+ #define EFI_IMAGE_MACHINE_RISCV64 0x5064
+ #define EFI_IMAGE_MACHINE_RISCV128 0x5128
+
++///
++/// PE32+ Machine type for LoongArch 32/64 images.
++///
++#define EFI_IMAGE_MACHINE_LOONGARCH32 0x6232
++#define EFI_IMAGE_MACHINE_LOONGARCH64 0x6264
++
+ #if defined (MDE_CPU_IA32)
+
+ #define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \
+@@ -279,6 +285,12 @@ typedef union {
+ #define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \
+ ((Machine) == EFI_IMAGE_MACHINE_RISCV64)
+
++#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)
++
++#elif defined (MDE_CPU_LOONGARCH64)
++#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \
++ ((Machine) == EFI_IMAGE_MACHINE_LOONGARCH64)
++
+ #define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)
+
+ #elif defined (MDE_CPU_EBC)
+diff --git a/MdePkg/Include/Uefi/UefiSpec.h b/MdePkg/Include/Uefi/UefiSpec.h
+index 2b1b72d..0781efb 100644
+--- a/MdePkg/Include/Uefi/UefiSpec.h
++++ b/MdePkg/Include/Uefi/UefiSpec.h
+@@ -7,6 +7,7 @@
+
+ Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
+ Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
++Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+@@ -2204,12 +2205,13 @@ typedef struct {
+ //
+ // EFI File location to boot from on removable media devices
+ //
+-#define EFI_REMOVABLE_MEDIA_FILE_NAME_IA32 L"\\EFI\\BOOT\\BOOTIA32.EFI"
+-#define EFI_REMOVABLE_MEDIA_FILE_NAME_IA64 L"\\EFI\\BOOT\\BOOTIA64.EFI"
+-#define EFI_REMOVABLE_MEDIA_FILE_NAME_X64 L"\\EFI\\BOOT\\BOOTX64.EFI"
+-#define EFI_REMOVABLE_MEDIA_FILE_NAME_ARM L"\\EFI\\BOOT\\BOOTARM.EFI"
+-#define EFI_REMOVABLE_MEDIA_FILE_NAME_AARCH64 L"\\EFI\\BOOT\\BOOTAA64.EFI"
+-#define EFI_REMOVABLE_MEDIA_FILE_NAME_RISCV64 L"\\EFI\\BOOT\\BOOTRISCV64.EFI"
++#define EFI_REMOVABLE_MEDIA_FILE_NAME_IA32 L"\\EFI\\BOOT\\BOOTIA32.EFI"
++#define EFI_REMOVABLE_MEDIA_FILE_NAME_IA64 L"\\EFI\\BOOT\\BOOTIA64.EFI"
++#define EFI_REMOVABLE_MEDIA_FILE_NAME_X64 L"\\EFI\\BOOT\\BOOTX64.EFI"
++#define EFI_REMOVABLE_MEDIA_FILE_NAME_ARM L"\\EFI\\BOOT\\BOOTARM.EFI"
++#define EFI_REMOVABLE_MEDIA_FILE_NAME_AARCH64 L"\\EFI\\BOOT\\BOOTAA64.EFI"
++#define EFI_REMOVABLE_MEDIA_FILE_NAME_RISCV64 L"\\EFI\\BOOT\\BOOTRISCV64.EFI"
++#define EFI_REMOVABLE_MEDIA_FILE_NAME_LOONGARCH64 L"\\EFI\\BOOT\\BOOTLOONGARCH64.EFI"
+
+ #if defined (MDE_CPU_IA32)
+ #define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_IA32
+@@ -2222,6 +2224,8 @@ typedef struct {
+ #define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_AARCH64
+ #elif defined (MDE_CPU_RISCV64)
+ #define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_RISCV64
++#elif defined (MDE_CPU_LOONGARCH64)
++ #define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_LOONGARCH64
+ #else
+ #error Unknown Processor Type
+ #endif
+diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
+index 3311424..6fd9cbe 100644
+--- a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
++++ b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
+@@ -7,6 +7,7 @@
+ # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+ # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+ # Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
++# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
+ #
+ # SPDX-License-Identifier: BSD-2-Clause-Patent
+ #
+@@ -24,7 +25,7 @@
+
+
+ #
+-# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
++# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64 LOONGARCH64
+ #
+
+ [Sources.IA32]
+@@ -45,6 +46,9 @@
+ [Sources.RISCV64]
+ RiscVCache.c
+
++[Sources.LOONGARCH64]
++ LoongArchCache.c
++
+ [Packages]
+ MdePkg/MdePkg.dec
+
+diff --git a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf b/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
+index 950f522..3101fc6 100644
+--- a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
++++ b/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
+@@ -8,6 +8,7 @@
+ # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+ # Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
+ # Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
++# Portions Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
+ #
+ # SPDX-License-Identifier: BSD-2-Clause-Patent
+ #
+@@ -25,7 +26,7 @@
+
+
+ #
+-# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64
++# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64 LOONGARCH64
+ #
+
+ [Sources.IA32]
+@@ -63,6 +64,10 @@
+ [Sources.RISCV64]
+ RiscV/Cpu.S
+
++[Sources.LOONGARCH64]
++ LoongArch/CpuFlushTlb.S | GCC
++ LoongArch/CpuSleep.S | GCC
++
+ [Packages]
+ MdePkg/MdePkg.dec
+
+diff --git a/MdePkg/Library/BaseCpuLib/BaseCpuLib.uni b/MdePkg/Library/BaseCpuLib/BaseCpuLib.uni
+index 80dc495..7c5c8df 100644
+--- a/MdePkg/Library/BaseCpuLib/BaseCpuLib.uni
++++ b/MdePkg/Library/BaseCpuLib/BaseCpuLib.uni
+@@ -1,13 +1,14 @@
+ // /** @file
+ // Instance of CPU Library for various architecture.
+ //
+-// CPU Library implemented using ASM functions for IA-32, X64 and RISCV64,
++// CPU Library implemented using ASM functions for IA-32, X64, RISCV64 and LoongArch64,
+ // PAL CALLs for IPF, and empty functions for EBC.
+ //
+ // Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.
+ // Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+ // Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
+ // Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
++// Portions Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
+ //
+ // SPDX-License-Identifier: BSD-2-Clause-Patent
+ //
+@@ -16,5 +17,5 @@
+
+ #string STR_MODULE_ABSTRACT #language en-US "Instance of CPU Library for various architectures"
+
+-#string STR_MODULE_DESCRIPTION #language en-US "CPU Library implemented using ASM functions for IA-32, X64 and RISCV64, PAL CALLs for IPF, and empty functions for EBC."
++#string STR_MODULE_DESCRIPTION #language en-US "CPU Library implemented using ASM functions for IA-32, X64, RISCV64 and LoongArch64, PAL CALLs for IPF, and empty functions for EBC."
+
+diff --git a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+index 690b95d..3ab1db6 100644
+--- a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
++++ b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+@@ -4,13 +4,14 @@
+ # I/O Library that uses compiler intrinsics to perform IN and OUT instructions
+ # for IA-32 and x64. On IPF, I/O port requests are translated into MMIO requests.
+ # MMIO requests are forwarded directly to memory. For EBC, I/O port requests
+-# ASSERT(). For ARM, AARCH64 and RISCV64, this I/O library only provides non I/O
+-# read and write.
++# ASSERT(). For ARM, AARCH64, RISCV64 and LoongArch, this I/O library only provides
++# non I/O read and write.
+ #
+ # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+ # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+ # Copyright (c) 2017, AMD Incorporated. All rights reserved.
+ # Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
++# Portions Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
+ #
+ # SPDX-License-Identifier: BSD-2-Clause-Patent
+ #
+@@ -27,7 +28,7 @@
+
+
+ #
+-# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64
++# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64 LOONGARCH64
+ #
+
+ [Sources]
+@@ -60,6 +61,9 @@
+ [Sources.RISCV64]
+ IoLibNoIo.c
+
++[Sources.LOONGARCH64]
++ IoLibNoIo.c
++
+ [Packages]
+ MdePkg/MdePkg.dec
+
+diff --git a/MdePkg/Library/BaseIoLibIntrinsic/IoLibNoIo.c b/MdePkg/Library/BaseIoLibIntrinsic/IoLibNoIo.c
+index a107136..cb50f87 100644
+--- a/MdePkg/Library/BaseIoLibIntrinsic/IoLibNoIo.c
++++ b/MdePkg/Library/BaseIoLibIntrinsic/IoLibNoIo.c
+@@ -1,11 +1,12 @@
+ /** @file
+ I/O library for non I/O read and write access (memory map I/O read and
+- write only) architecture, such as ARM and RISC-V processor.
++ write only) architecture, such as ARM, RISC-V and LoongArch processor.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+ Copyright (c) 2017, AMD Incorporated. All rights reserved.
+ Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
++ Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf
+index 3b85c56..dfa70b6 100644
+--- a/MdePkg/Library/BaseLib/BaseLib.inf
++++ b/MdePkg/Library/BaseLib/BaseLib.inf
+@@ -21,7 +21,7 @@
+ LIBRARY_CLASS = BaseLib
+
+ #
+-# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64
++# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64 LOONGARCH64
+ #
+
+ [Sources]
+@@ -403,6 +403,20 @@
+ RiscV64/RiscVInterrupt.S | GCC
+ RiscV64/FlushCache.S | GCC
+
++[Sources.LOONGARCH64]
++ Math64.c
++ Unaligned.c
++ LoongArch64/InternalSwitchStack.c
++ LoongArch64/GetInterruptState.S | GCC
++ LoongArch64/EnableInterrupts.S | GCC
++ LoongArch64/DisableInterrupts.S | GCC
++ LoongArch64/Barrier.S | GCC
++ LoongArch64/MemoryFence.S | GCC
++ LoongArch64/CpuBreakpoint.S | GCC
++ LoongArch64/CpuPause.S | GCC
++ LoongArch64/SetJumpLongJump.S | GCC
++ LoongArch64/SwitchStack.S | GCC
++
+ [Packages]
+ MdePkg/MdePkg.dec
+
+diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoff.c b/MdePkg/Library/BasePeCoffLib/BasePeCoff.c
+index 1102833..fe1fd6b 100644
+--- a/MdePkg/Library/BasePeCoffLib/BasePeCoff.c
++++ b/MdePkg/Library/BasePeCoffLib/BasePeCoff.c
+@@ -1,6 +1,6 @@
+ /** @file
+ Base PE/COFF loader supports loading any PE32/PE32+ or TE image, but
+- only supports relocating IA32, x64, IPF, ARM, RISC-V and EBC images.
++ only supports relocating IA32, x64, IPF, ARM, RISC-V, LoongArch and EBC images.
+
+ Caution: This file requires additional review when modified.
+ This library will have external input - PE/COFF image.
+@@ -18,6 +18,7 @@
+ Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
+ Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+ Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
++ Portions Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ **/
+diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+index 110b6d5..3b8b8eb 100644
+--- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
++++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+@@ -4,6 +4,7 @@
+ # The IA32 version library support loading IA32, X64 and EBC PE/COFF images.
+ # The X64 version library support loading IA32, X64 and EBC PE/COFF images.
+ # The RISC-V version library support loading RISC-V images.
++# The LoongArch version library support loading LoongArch images.
+ #
+ # Caution: This module requires additional review when modified.
+ # This library will have external input - PE/COFF image.
+@@ -13,6 +14,7 @@
+ # Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+ # Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
++# Portions Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
+ #
+ # SPDX-License-Identifier: BSD-2-Clause-Patent
+ #
+@@ -46,6 +48,9 @@
+ [Sources.RISCV64]
+ RiscV/PeCoffLoaderEx.c
+
++[Sources.LOONGARCH64]
++ LoongArch/PeCoffLoaderEx.c
++
+ [Packages]
+ MdePkg/MdePkg.dec
+
+diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni
+index 5541702..1f73134 100644
+--- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni
++++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni
+@@ -5,6 +5,7 @@
+ // The IA32 version library support loading IA32, X64 and EBC PE/COFF images.
+ // The X64 version library support loading IA32, X64 and EBC PE/COFF images.
+ // The RISC-V version library support loading RISC-V32 and RISC-V64 PE/COFF images.
++// The LoongArch version library support loading LoongArch32 and LoongArch64 PE/COFF images.
+ //
+ // Caution: This module requires additional review when modified.
+ // This library will have external input - PE/COFF image.
+@@ -14,6 +15,7 @@
+ // Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ // Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+ // Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
++// Portions Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
+ //
+ // SPDX-License-Identifier: BSD-2-Clause-Patent
+ //
+diff --git a/MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf b/MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf
+index 40017ec..9d039f2 100644
+--- a/MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf
++++ b/MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf
+@@ -4,9 +4,10 @@
+ # This library provides helper functions to prevent integer overflow during
+ # type conversion, addition, subtraction, and multiplication.
+ #
+-# Copyright (c) 2018, Intel Corporation. All rights reserved.
++# Copyright (c) 2018, Intel Corporation. All rights reserved.
+ # Copyright (c) 2017, Microsoft Corporation
+-# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
++# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
++# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
+
+ #
+ # All rights reserved.
+@@ -25,7 +26,7 @@
+ #
+ # The following information is for reference only and not required by the build tools.
+ #
+-# VALID_ARCHITECTURES = IA32 X64 ARM AARCH64 RISCV64
++# VALID_ARCHITECTURES = IA32 X64 ARM AARCH64 RISCV64 LOONGARCH64
+ #
+
+ [Sources]
+@@ -34,7 +35,7 @@
+ [Sources.Ia32, Sources.ARM]
+ SafeIntLib32.c
+
+-[Sources.X64, Sources.AARCH64, Sources.RISCV64]
++[Sources.X64, Sources.AARCH64, Sources.RISCV64, Sources.LOONGARCH64]
+ SafeIntLib64.c
+
+ [Sources.EBC]
+diff --git a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+index 83d5b8e..687adb4 100755
+--- a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
++++ b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+@@ -4,6 +4,7 @@
+ # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+ # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+ # Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
++# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
+ #
+ # SPDX-License-Identifier: BSD-2-Clause-Patent
+ #
+@@ -83,6 +84,11 @@
+ Synchronization.c
+ RiscV64/Synchronization.S
+
++[Sources.LOONGARCH64]
++ Synchronization.c
++ LoongArch64/Synchronization.c | GCC
++ LoongArch64/AsmSynchronization.S | GCC
++
+ [Packages]
+ MdePkg/MdePkg.dec
+
+diff --git a/MdePkg/Library/DxeServicesLib/DxeServicesLib.inf b/MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+index ec3e871..a935418 100644
+--- a/MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
++++ b/MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+@@ -22,13 +22,13 @@
+ LIBRARY_CLASS = DxeServicesLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER SMM_CORE UEFI_APPLICATION UEFI_DRIVER
+
+ #
+-# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64
++# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64 LOONGARCH64
+ #
+
+ [Sources]
+ DxeServicesLib.c
+
+-[Sources.IA32, Sources.EBC, Sources.ARM, Sources.AARCH64, Sources.RISCV64]
++[Sources.IA32, Sources.EBC, Sources.ARM, Sources.AARCH64, Sources.RISCV64, Sources.LOONGARCH64]
+ Allocate.c
+
+ [Sources.X64]
+diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec
+index 3928db6..a5fbbc6 100644
+--- a/MdePkg/MdePkg.dec
++++ b/MdePkg/MdePkg.dec
+@@ -7,6 +7,7 @@
+ # Copyright (c) 2007 - 2020, Intel Corporation. All rights reserved.
+ # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+ # (C) Copyright 2016 - 2020 Hewlett Packard Enterprise Development LP
++# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
+ #
+ # SPDX-License-Identifier: BSD-2-Clause-Patent
+ #
+@@ -43,6 +44,9 @@
+ [Includes.RISCV64]
+ Include/RiscV64
+
++[Includes.LOONGARCH64]
++ Include/LoongArch64
++
+ [LibraryClasses]
+ ## @libraryclass Provides most usb APIs to support the Hid requests defined in Usb Hid 1.1 spec
+ # and the standard requests defined in Usb 1.1 spec.
+diff --git a/MdePkg/MdePkg.dsc b/MdePkg/MdePkg.dsc
+index 8d1a5b2..58e3409 100644
+--- a/MdePkg/MdePkg.dsc
++++ b/MdePkg/MdePkg.dsc
+@@ -4,6 +4,7 @@
+ # Copyright (c) 2007 - 2020, Intel Corporation. All rights reserved.
+ # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+ # (C) Copyright 2020 Hewlett Packard Enterprise Development LP
++# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
+ #
+ # SPDX-License-Identifier: BSD-2-Clause-Patent
+ #
+@@ -15,7 +16,7 @@
+ PLATFORM_VERSION = 1.08
+ DSC_SPECIFICATION = 0x00010005
+ OUTPUT_DIRECTORY = Build/Mde
+- SUPPORTED_ARCHITECTURES = IA32|X64|EBC|ARM|AARCH64|RISCV64
++ SUPPORTED_ARCHITECTURES = IA32|X64|EBC|ARM|AARCH64|RISCV64|LOONGARCH64
+ BUILD_TARGETS = DEBUG|RELEASE|NOOPT
+ SKUID_IDENTIFIER = DEFAULT
+
+diff --git a/NetworkPkg/HttpBootDxe/HttpBootDhcp4.h b/NetworkPkg/HttpBootDxe/HttpBootDhcp4.h
+index 606a466..98b32cb 100644
+--- a/NetworkPkg/HttpBootDxe/HttpBootDhcp4.h
++++ b/NetworkPkg/HttpBootDxe/HttpBootDhcp4.h
+@@ -3,6 +3,7 @@
+
+ Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
++Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ **/
+@@ -40,6 +41,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
+ #define EFI_HTTP_BOOT_CLIENT_SYSTEM_ARCHITECTURE HTTP_CLIENT_ARCH_RISCV64
+ #elif defined (MDE_CPU_EBC)
+ #define EFI_HTTP_BOOT_CLIENT_SYSTEM_ARCHITECTURE HTTP_CLIENT_ARCH_EBC
++#elif defined (MDE_CPU_LOONGARCH64)
++#define EFI_HTTP_BOOT_CLIENT_SYSTEM_ARCHITECTURE HTTP_CLIENT_ARCH_LOONGARCH64
+ #endif
+
+ /// DHCP offer types among HTTP boot.
+diff --git a/NetworkPkg/Network.dsc.inc b/NetworkPkg/Network.dsc.inc
+index 99fad88..04b515a 100644
+--- a/NetworkPkg/Network.dsc.inc
++++ b/NetworkPkg/Network.dsc.inc
+@@ -9,6 +9,7 @@
+ #
+ # Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.
+ # Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
++# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
+ #
+ # SPDX-License-Identifier: BSD-2-Clause-Patent
+ #
+@@ -38,7 +39,7 @@
+ !include NetworkPkg/NetworkComponents.dsc.inc
+
+ !else
+-[Components.IA32, Components.X64, Components.ARM, Components.AARCH64, Components.RISCV64]
++[Components.IA32, Components.X64, Components.ARM, Components.AARCH64, Components.RISCV64, Components.LOONGARCH64]
+ !include NetworkPkg/NetworkComponents.dsc.inc
+
+ !endif
+diff --git a/NetworkPkg/NetworkPkg.dsc b/NetworkPkg/NetworkPkg.dsc
+index b1250c3..be62f37 100644
+--- a/NetworkPkg/NetworkPkg.dsc
++++ b/NetworkPkg/NetworkPkg.dsc
+@@ -4,6 +4,7 @@
+ # (C) Copyright 2014 Hewlett-Packard Development Company, L.P.
+ # Copyright (c) 2009 - 2020, Intel Corporation. All rights reserved.
+ # Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
++# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
+ # SPDX-License-Identifier: BSD-2-Clause-Patent
+ #
+ ##
+@@ -14,7 +15,7 @@
+ PLATFORM_VERSION = 0.98
+ DSC_SPECIFICATION = 0x00010005
+ OUTPUT_DIRECTORY = Build/NetworkPkg
+- SUPPORTED_ARCHITECTURES = IA32|X64|EBC|ARM|AARCH64|RISCV64
++ SUPPORTED_ARCHITECTURES = IA32|X64|EBC|ARM|AARCH64|RISCV64|LOONGARCH64
+ BUILD_TARGETS = DEBUG|RELEASE|NOOPT
+ SKUID_IDENTIFIER = DEFAULT
+
+diff --git a/SecurityPkg/SecurityPkg.dsc b/SecurityPkg/SecurityPkg.dsc
+index 27b34ce..f34dbc4 100644
+--- a/SecurityPkg/SecurityPkg.dsc
++++ b/SecurityPkg/SecurityPkg.dsc
+@@ -3,6 +3,7 @@
+ #
+ # Copyright (c) 2009 - 2020, Intel Corporation. All rights reserved.
+ # (C) Copyright 2015-2020 Hewlett Packard Enterprise Development LP
++# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
+ # SPDX-License-Identifier: BSD-2-Clause-Patent
+ #
+ ##
+@@ -13,7 +14,7 @@
+ PLATFORM_VERSION = 0.98
+ DSC_SPECIFICATION = 0x00010005
+ OUTPUT_DIRECTORY = Build/SecurityPkg
+- SUPPORTED_ARCHITECTURES = IA32|X64|EBC|ARM|AARCH64|RISCV64
++ SUPPORTED_ARCHITECTURES = IA32|X64|EBC|ARM|AARCH64|RISCV64|LOONGARCH64
+ BUILD_TARGETS = DEBUG|RELEASE|NOOPT
+ SKUID_IDENTIFIER = DEFAULT
+
+diff --git a/ShellPkg/ShellPkg.dsc b/ShellPkg/ShellPkg.dsc
+index c42bc94..fb45e04 100644
+--- a/ShellPkg/ShellPkg.dsc
++++ b/ShellPkg/ShellPkg.dsc
+@@ -4,6 +4,7 @@
+ # Copyright (c) 2007 - 2019, Intel Corporation. All rights reserved.
+ # Copyright (c) 2018 - 2020, Arm Limited. All rights reserved.
+ # Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
++# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
+ #
+ # SPDX-License-Identifier: BSD-2-Clause-Patent
+ #
+@@ -15,7 +16,7 @@
+ PLATFORM_VERSION = 1.02
+ DSC_SPECIFICATION = 0x00010006
+ OUTPUT_DIRECTORY = Build/Shell
+- SUPPORTED_ARCHITECTURES = IA32|X64|EBC|ARM|AARCH64|RISCV64
++ SUPPORTED_ARCHITECTURES = IA32|X64|EBC|ARM|AARCH64|RISCV64|LOONGARCH64
+ BUILD_TARGETS = DEBUG|RELEASE|NOOPT
+ SKUID_IDENTIFIER = DEFAULT
+
+diff --git a/UnitTestFrameworkPkg/UnitTestFrameworkPkg.dsc b/UnitTestFrameworkPkg/UnitTestFrameworkPkg.dsc
+index 2f0fbfc..dc6c10c 100644
+--- a/UnitTestFrameworkPkg/UnitTestFrameworkPkg.dsc
++++ b/UnitTestFrameworkPkg/UnitTestFrameworkPkg.dsc
+@@ -3,6 +3,7 @@
+ #
+ # Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.
+ # Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
++# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
+ #
+ # SPDX-License-Identifier: BSD-2-Clause-Patent
+ #
+@@ -14,7 +15,7 @@
+ PLATFORM_VERSION = 1.00
+ DSC_SPECIFICATION = 0x00010005
+ OUTPUT_DIRECTORY = Build/UnitTestFrameworkPkg
+- SUPPORTED_ARCHITECTURES = IA32|X64|ARM|AARCH64|RISCV64
++ SUPPORTED_ARCHITECTURES = IA32|X64|ARM|AARCH64|RISCV64|LOONGARCH64
+ BUILD_TARGETS = DEBUG|RELEASE|NOOPT
+ SKUID_IDENTIFIER = DEFAULT
+
diff --git a/1001-add-LoongArch-support-not-upstream-new-files.patch b/1001-add-LoongArch-support-not-upstream-new-files.patch
new file mode 100644
index 0000000000000000000000000000000000000000..3a3004a2b17726d5d87312abd78c31992018fb8d
--- /dev/null
+++ b/1001-add-LoongArch-support-not-upstream-new-files.patch
@@ -0,0 +1,1524 @@
+diff --git a/BaseTools/Bin/gcc_loongarch64_unknown_linux_ext_dep.yaml b/BaseTools/Bin/gcc_loongarch64_unknown_linux_ext_dep.yaml
+new file mode 100644
+index 0000000..2edb38c
+--- /dev/null
++++ b/BaseTools/Bin/gcc_loongarch64_unknown_linux_ext_dep.yaml
+@@ -0,0 +1,22 @@
++## @file
++# Download GCC LoongArch64 compiler from LoongArch GitHub release site
++# Set shell variable GCC5_LOONGARCH64_INSTALL to this folder
++#
++# This is only downloaded when a build activates scope gcc_loongarch64_unknown_linux
++#
++# Copyright (c) Microsoft Corporation.
++# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
++# SPDX-License-Identifier: BSD-2-Clause-Patent
++##
++{
++ "scope": "gcc_loongarch64_unknown_linux",
++ "type": "web",
++ "name": "gcc_loongarch64_unknown_linux",
++ "source":"https://github.com/loongson/build-tools/releases/download/2022.09.06/loongarch64-clfs-6.3-cross-tools-gcc-full.tar.xz",
++ "version": "13.0.0",
++ "sha256":"27a43c5bb127794f091d0e75da0003c4d0eec28a958d8f2cc7cd290a6e6133ab",
++ "compression_type": "tar",
++ "internal_path": "/cross-tools/",
++ "flags": ["set_shell_var", ],
++ "var_name": "GCC5_LOONGARCH64_INSTALL"
++}
+\ No newline at end of file
+diff --git a/BaseTools/Source/C/Include/LoongArch64/ProcessorBind.h b/BaseTools/Source/C/Include/LoongArch64/ProcessorBind.h
+new file mode 100644
+index 0000000..6890f72
+--- /dev/null
++++ b/BaseTools/Source/C/Include/LoongArch64/ProcessorBind.h
+@@ -0,0 +1,79 @@
++/** @file
++ Processor or Compiler specific defines and types for LoongArch
++
++ Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
++
++ SPDX-License-Identifier: BSD-2-Clause-Patent
++**/
++#ifndef PROCESSOR_BIND_H_
++#define PROCESSOR_BIND_H_
++
++//
++// Define the processor type so other code can make processor based choices
++//
++#define MDE_CPU_LOONGARCH64
++
++#define EFIAPI
++
++//
++// Make sure we are using the correct packing rules per EFI specification
++//
++#ifndef __GNUC__
++#pragma pack()
++#endif
++
++//
++// Use ANSI C 2000 stdint.h integer width declarations
++//
++#include
++typedef uint8_t BOOLEAN;
++typedef int8_t INT8;
++typedef uint8_t UINT8;
++typedef int16_t INT16;
++typedef uint16_t UINT16;
++typedef int32_t INT32;
++typedef uint32_t UINT32;
++typedef int64_t INT64;
++typedef uint64_t UINT64;
++typedef char CHAR8;
++typedef uint16_t CHAR16;
++
++//
++// Unsigned value of native width. (4 bytes on supported 32-bit processor instructions,
++// 8 bytes on supported 64-bit processor instructions)
++//
++typedef UINT64 UINTN;
++
++//
++// Signed value of native width. (4 bytes on supported 32-bit processor instructions,
++// 8 bytes on supported 64-bit processor instructions)
++//
++typedef INT64 INTN;
++
++//
++// Processor specific defines
++//
++
++//
++// A value of native width with the highest bit set.
++//
++#define MAX_BIT 0x8000000000000000ULL
++//
++// A value of native width with the two highest bits set.
++//
++#define MAX_2_BITS 0xC000000000000000ULL
++
++#if defined (__GNUC__)
++//
++// For GNU assembly code, .global or .globl can declare global symbols.
++// Define this macro to unify the usage.
++//
++#define ASM_GLOBAL .globl
++#endif
++
++//
++// The stack alignment required for LoongArch
++//
++#define CPU_STACK_ALIGNMENT 16
++
++#endif
+\ No newline at end of file
+diff --git a/MdeModulePkg/Core/DxeIplPeim/LoongArch64/DxeLoadFunc.c b/MdeModulePkg/Core/DxeIplPeim/LoongArch64/DxeLoadFunc.c
+new file mode 100644
+index 0000000..27147c3
+--- /dev/null
++++ b/MdeModulePkg/Core/DxeIplPeim/LoongArch64/DxeLoadFunc.c
+@@ -0,0 +1,63 @@
++/** @file
++ LoongArch specifc functionality for DxeLoad.
++
++ Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
++
++ SPDX-License-Identifier: BSD-2-Clause-Patent
++
++**/
++
++#include "DxeIpl.h"
++
++/**
++ Transfers control to DxeCore.
++
++ This function performs a CPU architecture specific operations to execute
++ the entry point of DxeCore with the parameters of HobList.
++ It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase.
++
++ @param[in] DxeCoreEntryPoint The entry point of DxeCore.
++ @param[in] HobList The start of HobList passed to DxeCore.
++
++**/
++VOID
++HandOffToDxeCore (
++ IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint,
++ IN EFI_PEI_HOB_POINTERS HobList
++ )
++{
++ VOID *BaseOfStack;
++ VOID *TopOfStack;
++ EFI_STATUS Status;
++
++ //
++ // Allocate 128KB for the Stack
++ //
++ BaseOfStack = AllocatePages (EFI_SIZE_TO_PAGES (STACK_SIZE));
++ ASSERT (BaseOfStack != NULL);
++
++ //
++ // Compute the top of the stack we were allocated. Pre-allocate a UINTN
++ // for safety.
++ //
++ TopOfStack = (VOID *)((UINTN)BaseOfStack + EFI_SIZE_TO_PAGES (STACK_SIZE) * EFI_PAGE_SIZE - CPU_STACK_ALIGNMENT);
++ TopOfStack = ALIGN_POINTER (TopOfStack, CPU_STACK_ALIGNMENT);
++
++ //
++ // End of PEI phase signal
++ //
++ Status = PeiServicesInstallPpi (&gEndOfPeiSignalPpi);
++ ASSERT_EFI_ERROR (Status);
++
++ //
++ // Update the contents of BSP stack HOB to reflect the real stack info passed to DxeCore.
++ //
++ UpdateStackHob ((EFI_PHYSICAL_ADDRESS)(UINTN)BaseOfStack, STACK_SIZE);
++
++ SwitchStack (
++ (SWITCH_STACK_ENTRY_POINT)(UINTN)DxeCoreEntryPoint,
++ HobList.Raw,
++ NULL,
++ TopOfStack
++ );
++}
+\ No newline at end of file
+diff --git a/MdePkg/Include/LoongArch64/ProcessorBind.h b/MdePkg/Include/LoongArch64/ProcessorBind.h
+new file mode 100644
+index 0000000..e96c4ae
+--- /dev/null
++++ b/MdePkg/Include/LoongArch64/ProcessorBind.h
+@@ -0,0 +1,120 @@
++/** @file
++ Processor or Compiler specific defines and types for LoongArch
++
++ Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
++
++ SPDX-License-Identifier: BSD-2-Clause-Patent
++
++**/
++
++#ifndef PROCESSOR_BIND_H_
++#define PROCESSOR_BIND_H_
++
++//
++// Define the processor type so other code can make processor based choices
++//
++#define MDE_CPU_LOONGARCH64
++
++#define EFIAPI
++
++//
++// Make sure we are using the correct packing rules per EFI specification
++//
++#ifndef __GNUC__
++ #pragma pack()
++#endif
++
++//
++// Assume standard LoongArch 64-bit alignment.
++// Need to check portability of long long
++//
++typedef unsigned long UINT64;
++typedef long INT64;
++typedef unsigned int UINT32;
++typedef int INT32;
++typedef unsigned short UINT16;
++typedef unsigned short CHAR16;
++typedef short INT16;
++typedef unsigned char BOOLEAN;
++typedef unsigned char UINT8;
++typedef char CHAR8;
++typedef char INT8;
++
++//
++// Unsigned value of native width. (4 bytes on supported 32-bit processor instructions,
++// 8 bytes on supported 64-bit processor instructions)
++//
++
++typedef UINT64 UINTN;
++
++//
++// Signed value of native width. (4 bytes on supported 32-bit processor instructions,
++// 8 bytes on supported 64-bit processor instructions)
++//
++typedef INT64 INTN;
++
++//
++// Processor specific defines
++//
++
++//
++// A value of native width with the highest bit set.
++//
++#define MAX_BIT 0x8000000000000000ULL
++//
++// A value of native width with the two highest bits set.
++//
++#define MAX_2_BITS 0xC000000000000000ULL
++
++//
++// Maximum legal LoongArch 64-bit address
++//
++#define MAX_ADDRESS 0xFFFFFFFFFFFFFFFFULL
++
++//
++// Maximum usable address at boot time (48 bits using 4KB pages)
++//
++#define MAX_ALLOC_ADDRESS 0xFFFFFFFFFFFFULL
++
++//
++// Maximum legal LoongArch 64-bit INTN and UINTN values.
++//
++#define MAX_INTN ((INTN)0x7FFFFFFFFFFFFFFFULL)
++#define MAX_UINTN ((UINTN)0xFFFFFFFFFFFFFFFFULL)
++
++//
++// Page allocation granularity for LoongArch
++//
++#define DEFAULT_PAGE_ALLOCATION_GRANULARITY (0x1000)
++#define RUNTIME_PAGE_ALLOCATION_GRANULARITY (0x10000)
++
++#if defined (__GNUC__)
++//
++// For GNU assembly code, .global or .globl can declare global symbols.
++// Define this macro to unify the usage.
++//
++#define ASM_GLOBAL .globl
++#endif
++
++//
++// The stack alignment required for LoongArch
++//
++#define CPU_STACK_ALIGNMENT 16
++
++/**
++ Return the pointer to the first instruction of a function given a function pointer.
++ On LOONGARCH CPU architectures, these two pointer values are the same,
++ so the implementation of this macro is very simple.
++
++ @param FunctionPointer A pointer to a function.
++
++ @return The pointer to the first instruction of a function given a function pointer.
++
++**/
++#define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPointer)
++
++#ifndef __USER_LABEL_PREFIX__
++#define __USER_LABEL_PREFIX__
++#endif
++
++#endif
+\ No newline at end of file
+diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/LoongArchCache.c b/MdePkg/Library/BaseCacheMaintenanceLib/LoongArchCache.c
+new file mode 100644
+index 0000000..1a50b14
+--- /dev/null
++++ b/MdePkg/Library/BaseCacheMaintenanceLib/LoongArchCache.c
+@@ -0,0 +1,254 @@
++/** @file
++ Cache Maintenance Functions for LoongArch.
++ LoongArch cache maintenance functions has not yet been completed, and will added in later.
++ Functions are null functions now.
++
++ Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
++
++ SPDX-License-Identifier: BSD-2-Clause-Patent
++
++**/
++
++//
++// Include common header file for this module.
++//
++#include
++#include
++#include
++
++/**
++ LoongArch data barrier operation.
++**/
++VOID
++EFIAPI
++AsmDataBarrierLoongArch (
++ VOID
++ );
++
++/**
++ LoongArch instruction barrier operation.
++**/
++VOID
++EFIAPI
++AsmInstructionBarrierLoongArch (
++ VOID
++ );
++
++/**
++ Invalidates the entire instruction cache in cache coherency domain of the
++ calling CPU.
++**/
++VOID
++EFIAPI
++InvalidateInstructionCache (
++ VOID
++ )
++{
++ AsmInstructionBarrierLoongArch ();
++}
++
++/**
++ Invalidates a range of instruction cache lines in the cache coherency domain
++ of the calling CPU.
++
++ Invalidates the instruction cache lines specified by Address and Length. If
++ Address is not aligned on a cache line boundary, then entire instruction
++ cache line containing Address is invalidated. If Address + Length is not
++ aligned on a cache line boundary, then the entire instruction cache line
++ containing Address + Length -1 is invalidated. This function may choose to
++ invalidate the entire instruction cache if that is more efficient than
++ invalidating the specified range. If Length is 0, the no instruction cache
++ lines are invalidated. Address is returned.
++
++ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
++
++ @param[in] Address The base address of the instruction cache lines to
++ invalidate. If the CPU is in a physical addressing mode, then
++ Address is a physical address. If the CPU is in a virtual
++ addressing mode, then Address is a virtual address.
++
++ @param[in] Length The number of bytes to invalidate from the instruction cache.
++
++ @return Address.
++
++**/
++VOID *
++EFIAPI
++InvalidateInstructionCacheRange (
++ IN VOID *Address,
++ IN UINTN Length
++ )
++{
++ AsmInstructionBarrierLoongArch ();
++ return Address;
++}
++
++/**
++ Writes Back and Invalidates the entire data cache in cache coherency domain
++ of the calling CPU.
++
++ Writes Back and Invalidates the entire data cache in cache coherency domain
++ of the calling CPU. This function guarantees that all dirty cache lines are
++ written back to system memory, and also invalidates all the data cache lines
++ in the cache coherency domain of the calling CPU.
++
++**/
++VOID
++EFIAPI
++WriteBackInvalidateDataCache (
++ VOID
++ )
++{
++ DEBUG ((DEBUG_ERROR, "%a: Not currently implemented on LoongArch.\n", __FUNCTION__));
++}
++
++/**
++ Writes Back and Invalidates a range of data cache lines in the cache
++ coherency domain of the calling CPU.
++
++ Writes Back and Invalidate the data cache lines specified by Address and
++ Length. If Address is not aligned on a cache line boundary, then entire data
++ cache line containing Address is written back and invalidated. If Address +
++ Length is not aligned on a cache line boundary, then the entire data cache
++ line containing Address + Length -1 is written back and invalidated. This
++ function may choose to write back and invalidate the entire data cache if
++ that is more efficient than writing back and invalidating the specified
++ range. If Length is 0, the no data cache lines are written back and
++ invalidated. Address is returned.
++
++ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
++
++ @param[in] Address The base address of the data cache lines to write back and
++ invalidate. If the CPU is in a physical addressing mode, then
++ Address is a physical address. If the CPU is in a virtual
++ addressing mode, then Address is a virtual address.
++
++ @param[in] Length The number of bytes to write back and invalidate from the
++ data cache.
++
++ @return Address of cache invalidation.
++
++**/
++VOID *
++EFIAPI
++WriteBackInvalidateDataCacheRange (
++ IN VOID *Address,
++ IN UINTN Length
++ )
++{
++ DEBUG ((DEBUG_ERROR, "%a: Not currently implemented on LoongArch.\n", __FUNCTION__));
++ return Address;
++}
++
++/**
++ Writes Back the entire data cache in cache coherency domain of the calling
++ CPU.
++
++ Writes Back the entire data cache in cache coherency domain of the calling
++ CPU. This function guarantees that all dirty cache lines are written back to
++ system memory. This function may also invalidate all the data cache lines in
++ the cache coherency domain of the calling CPU.
++
++**/
++VOID
++EFIAPI
++WriteBackDataCache (
++ VOID
++ )
++{
++ WriteBackInvalidateDataCache ();
++}
++
++/**
++ Writes Back a range of data cache lines in the cache coherency domain of the
++ calling CPU.
++
++ Writes Back the data cache lines specified by Address and Length. If Address
++ is not aligned on a cache line boundary, then entire data cache line
++ containing Address is written back. If Address + Length is not aligned on a
++ cache line boundary, then the entire data cache line containing Address +
++ Length -1 is written back. This function may choose to write back the entire
++ data cache if that is more efficient than writing back the specified range.
++ If Length is 0, the no data cache lines are written back. This function may
++ also invalidate all the data cache lines in the specified range of the cache
++ coherency domain of the calling CPU. Address is returned.
++
++ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
++
++ @param[in] Address The base address of the data cache lines to write back. If
++ the CPU is in a physical addressing mode, then Address is a
++ physical address. If the CPU is in a virtual addressing
++ mode, then Address is a virtual address.
++ @param[in] Length The number of bytes to write back from the data cache.
++
++ @return Address of cache written in main memory.
++
++**/
++VOID *
++EFIAPI
++WriteBackDataCacheRange (
++ IN VOID *Address,
++ IN UINTN Length
++ )
++{
++ DEBUG ((DEBUG_ERROR, "%a: Not currently implemented on LoongArch.\n", __FUNCTION__));
++ return Address;
++}
++
++/**
++ Invalidates the entire data cache in cache coherency domain of the calling
++ CPU.
++
++ Invalidates the entire data cache in cache coherency domain of the calling
++ CPU. This function must be used with care because dirty cache lines are not
++ written back to system memory. It is typically used for cache diagnostics. If
++ the CPU does not support invalidation of the entire data cache, then a write
++ back and invalidate operation should be performed on the entire data cache.
++
++**/
++VOID
++EFIAPI
++InvalidateDataCache (
++ VOID
++ )
++{
++ AsmDataBarrierLoongArch ();
++}
++
++/**
++ Invalidates a range of data cache lines in the cache coherency domain of the
++ calling CPU.
++
++ Invalidates the data cache lines specified by Address and Length. If Address
++ is not aligned on a cache line boundary, then entire data cache line
++ containing Address is invalidated. If Address + Length is not aligned on a
++ cache line boundary, then the entire data cache line containing Address +
++ Length -1 is invalidated. This function must never invalidate any cache lines
++ outside the specified range. If Length is 0, the no data cache lines are
++ invalidated. Address is returned. This function must be used with care
++ because dirty cache lines are not written back to system memory. It is
++ typically used for cache diagnostics. If the CPU does not support
++ invalidation of a data cache range, then a write back and invalidate
++ operation should be performed on the data cache range.
++
++ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
++
++ @param[in] Address The base address of the data cache lines to invalidate. If
++ the CPU is in a physical addressing mode, then Address is a
++ physical address. If the CPU is in a virtual addressing mode,
++ then Address is a virtual address.
++ @param[in] Length The number of bytes to invalidate from the data cache.
++
++ @return Address.
++
++**/
++VOID *
++EFIAPI
++InvalidateDataCacheRange (
++ IN VOID *Address,
++ IN UINTN Length
++ )
++{
++ AsmDataBarrierLoongArch ();
++ return Address;
++}
+\ No newline at end of file
+diff --git a/MdePkg/Library/BaseCpuLib/LoongArch/CpuFlushTlb.S b/MdePkg/Library/BaseCpuLib/LoongArch/CpuFlushTlb.S
+new file mode 100644
+index 0000000..e6becf9
+--- /dev/null
++++ b/MdePkg/Library/BaseCpuLib/LoongArch/CpuFlushTlb.S
+@@ -0,0 +1,15 @@
++#------------------------------------------------------------------------------
++#
++# CpuFlushTlb() for LoongArch64
++#
++# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
++#
++# SPDX-License-Identifier: BSD-2-Clause-Patent
++#
++#------------------------------------------------------------------------------
++ASM_GLOBAL ASM_PFX(CpuFlushTlb)
++
++ASM_PFX(CpuFlushTlb):
++ tlbflush
++ jirl $zero, $ra, 0
++ .end
+\ No newline at end of file
+diff --git a/MdePkg/Library/BaseCpuLib/LoongArch/CpuSleep.S b/MdePkg/Library/BaseCpuLib/LoongArch/CpuSleep.S
+new file mode 100644
+index 0000000..3af79e1
+--- /dev/null
++++ b/MdePkg/Library/BaseCpuLib/LoongArch/CpuSleep.S
+@@ -0,0 +1,15 @@
++#------------------------------------------------------------------------------
++#
++# CpuSleep() for LoongArch64
++#
++# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
++#
++# SPDX-License-Identifier: BSD-2-Clause-Patent
++#
++#------------------------------------------------------------------------------
++ASM_GLOBAL ASM_PFX(CpuSleep)
++
++ASM_PFX(CpuSleep):
++ idle 0
++ jirl $zero, $ra, 0
++ .end
+\ No newline at end of file
+diff --git a/MdePkg/Library/BaseLib/LoongArch64/Barrier.S b/MdePkg/Library/BaseLib/LoongArch64/Barrier.S
+new file mode 100644
+index 0000000..c1e7923
+--- /dev/null
++++ b/MdePkg/Library/BaseLib/LoongArch64/Barrier.S
+@@ -0,0 +1,28 @@
++#------------------------------------------------------------------------------
++#
++# LoongArch Barrier Operations
++#
++# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
++#
++# SPDX-License-Identifier: BSD-2-Clause-Patent
++#
++#------------------------------------------------------------------------------
++
++ASM_GLOBAL ASM_PFX(AsmDataBarrierLoongArch)
++ASM_GLOBAL ASM_PFX(AsmInstructionBarrierLoongArch)
++
++#
++# Data barrier operation for LoongArch.
++#
++ASM_PFX(AsmDataBarrierLoongArch):
++ dbar 0
++ jirl $zero, $ra, 0
++
++#
++# Instruction barrier operation for LoongArch.
++#
++ASM_PFX(AsmInstructionBarrierLoongArch):
++ ibar 0
++ jirl $zero, $ra, 0
++
++ .end
+\ No newline at end of file
+diff --git a/MdePkg/Library/BaseLib/LoongArch64/CpuBreakpoint.S b/MdePkg/Library/BaseLib/LoongArch64/CpuBreakpoint.S
+new file mode 100644
+index 0000000..7213cd8
+--- /dev/null
++++ b/MdePkg/Library/BaseLib/LoongArch64/CpuBreakpoint.S
+@@ -0,0 +1,24 @@
++#------------------------------------------------------------------------------
++#
++# CpuBreakpoint for LoongArch
++#
++# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
++#
++# SPDX-License-Identifier: BSD-2-Clause-Patent
++#
++#------------------------------------------------------------------------------
++
++ASM_GLOBAL ASM_PFX(CpuBreakpoint)
++
++#/**
++# Generates a breakpoint on the CPU.
++#
++# Generates a breakpoint on the CPU. The breakpoint must be implemented such
++# that code can resume normal execution after the breakpoint.
++#
++#**/
++
++ASM_PFX(CpuBreakpoint):
++ break 3
++ jirl $zero, $ra, 0
++ .end
+\ No newline at end of file
+diff --git a/MdePkg/Library/BaseLib/LoongArch64/CpuPause.S b/MdePkg/Library/BaseLib/LoongArch64/CpuPause.S
+new file mode 100644
+index 0000000..4c3a52d
+--- /dev/null
++++ b/MdePkg/Library/BaseLib/LoongArch64/CpuPause.S
+@@ -0,0 +1,31 @@
++#------------------------------------------------------------------------------
++#
++# CpuPause for LoongArch
++#
++# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
++#
++# SPDX-License-Identifier: BSD-2-Clause-Patent
++#
++#------------------------------------------------------------------------------
++
++ASM_GLOBAL ASM_PFX(CpuPause)
++
++#/**
++# Requests CPU to pause for a short period of time.
++#
++# Requests CPU to pause for a short period of time. Typically used in MP
++# systems to prevent memory starvation while waiting for a spin lock.
++#
++#**/
++
++ASM_PFX(CpuPause):
++ nop
++ nop
++ nop
++ nop
++ nop
++ nop
++ nop
++ nop
++ jirl $zero, $ra, 0
++ .end
+\ No newline at end of file
+diff --git a/MdePkg/Library/BaseLib/LoongArch64/DisableInterrupts.S b/MdePkg/Library/BaseLib/LoongArch64/DisableInterrupts.S
+new file mode 100644
+index 0000000..bc661e2
+--- /dev/null
++++ b/MdePkg/Library/BaseLib/LoongArch64/DisableInterrupts.S
+@@ -0,0 +1,21 @@
++#------------------------------------------------------------------------------
++#
++# LoongArch interrupt disable
++#
++# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
++#
++# SPDX-License-Identifier: BSD-2-Clause-Patent
++#
++#------------------------------------------------------------------------------
++
++ASM_GLOBAL ASM_PFX(DisableInterrupts)
++
++#/**
++# Disables CPU interrupts.
++#**/
++
++ASM_PFX(DisableInterrupts):
++ li.w $t0, 0x4
++ csrxchg $zero, $t0, 0x0
++ jirl $zero, $ra, 0
++ .end
+\ No newline at end of file
+diff --git a/MdePkg/Library/BaseLib/LoongArch64/EnableInterrupts.S b/MdePkg/Library/BaseLib/LoongArch64/EnableInterrupts.S
+new file mode 100644
+index 0000000..4eb3902
+--- /dev/null
++++ b/MdePkg/Library/BaseLib/LoongArch64/EnableInterrupts.S
+@@ -0,0 +1,21 @@
++#------------------------------------------------------------------------------
++#
++# LoongArch interrupt enable
++#
++# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
++#
++# SPDX-License-Identifier: BSD-2-Clause-Patent
++#
++#------------------------------------------------------------------------------
++
++ASM_GLOBAL ASM_PFX(EnableInterrupts)
++
++#/**
++# Enables CPU interrupts.
++#**/
++
++ASM_PFX(EnableInterrupts):
++ li.w $t0, 0x4
++ csrxchg $t0, $t0, 0x0
++ jirl $zero, $ra, 0
++ .end
+\ No newline at end of file
+diff --git a/MdePkg/Library/BaseLib/LoongArch64/GetInterruptState.S b/MdePkg/Library/BaseLib/LoongArch64/GetInterruptState.S
+new file mode 100644
+index 0000000..374a1e8
+--- /dev/null
++++ b/MdePkg/Library/BaseLib/LoongArch64/GetInterruptState.S
+@@ -0,0 +1,35 @@
++#------------------------------------------------------------------------------
++#
++# Get LoongArch interrupt status
++#
++# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
++#
++# SPDX-License-Identifier: BSD-2-Clause-Patent
++#
++#------------------------------------------------------------------------------
++
++ASM_GLOBAL ASM_PFX(GetInterruptState)
++
++#/**
++# Retrieves the current CPU interrupt state.
++#
++# Returns TRUE means interrupts are currently enabled. Otherwise,
++# returns FALSE.
++#
++# @retval TRUE CPU interrupts are enabled.
++# @retval FALSE CPU interrupts are disabled.
++#
++#**/
++
++ASM_PFX(GetInterruptState):
++ li.w $t1, 0x4
++ csrrd $t0, 0x0
++ and $t0, $t0, $t1
++ beqz $t0, 1f
++ li.w $a0, 0x1
++ b 2f
++1:
++ li.w $a0, 0x0
++2:
++ jirl $zero, $ra, 0
++ .end
+\ No newline at end of file
+diff --git a/MdePkg/Library/BaseLib/LoongArch64/InternalSwitchStack.c b/MdePkg/Library/BaseLib/LoongArch64/InternalSwitchStack.c
+new file mode 100644
+index 0000000..38c4a10
+--- /dev/null
++++ b/MdePkg/Library/BaseLib/LoongArch64/InternalSwitchStack.c
+@@ -0,0 +1,58 @@
++/** @file
++ SwitchStack() function for LoongArch.
++
++ Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
++
++ SPDX-License-Identifier: BSD-2-Clause-Patent
++**/
++
++#include "BaseLibInternals.h"
++
++UINTN
++EFIAPI
++InternalSwitchStackAsm (
++ IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer
++ );
++
++/**
++ Transfers control to a function starting with a new stack.
++
++ Transfers control to the function specified by EntryPoint using the
++ new stack specified by NewStack and passing in the parameters specified
++ by Context1 and Context2. Context1 and Context2 are optional and may
++ be NULL. The function EntryPoint must never return.
++
++ If EntryPoint is NULL, then ASSERT().
++ If NewStack is NULL, then ASSERT().
++
++ @param[in] EntryPoint A pointer to function to call with the new stack.
++ @param[in] Context1 A pointer to the context to pass into the EntryPoint
++ function.
++ @param[in] Context2 A pointer to the context to pass into the EntryPoint
++ function.
++ @param[in] NewStack A pointer to the new stack to use for the EntryPoint
++ function.
++ @param[in] Marker VA_LIST marker for the variable argument list.
++
++**/
++VOID
++EFIAPI
++InternalSwitchStack (
++ IN SWITCH_STACK_ENTRY_POINT EntryPoint,
++ IN VOID *Context1 OPTIONAL,
++ IN VOID *Context2 OPTIONAL,
++ IN VOID *NewStack,
++ IN VA_LIST Marker
++ )
++
++{
++ BASE_LIBRARY_JUMP_BUFFER JumpBuffer;
++
++ JumpBuffer.RA = (UINTN)EntryPoint;
++ JumpBuffer.SP = (UINTN)NewStack - sizeof (VOID *);
++ JumpBuffer.SP -= sizeof (Context1) + sizeof (Context2);
++ ((VOID **)(UINTN)JumpBuffer.SP)[0] = Context1;
++ ((VOID **)(UINTN)JumpBuffer.SP)[1] = Context2;
++
++ InternalSwitchStackAsm (&JumpBuffer);
++}
+\ No newline at end of file
+diff --git a/MdePkg/Library/BaseLib/LoongArch64/MemoryFence.S b/MdePkg/Library/BaseLib/LoongArch64/MemoryFence.S
+new file mode 100644
+index 0000000..4bdaa0a
+--- /dev/null
++++ b/MdePkg/Library/BaseLib/LoongArch64/MemoryFence.S
+@@ -0,0 +1,18 @@
++#------------------------------------------------------------------------------
++#
++# MemoryFence() for LoongArch
++#
++# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
++#
++# SPDX-License-Identifier: BSD-2-Clause-Patent
++#
++#------------------------------------------------------------------------------
++
++ASM_GLOBAL ASM_PFX(MemoryFence)
++
++#
++# Memory fence for LoongArch
++#
++ASM_PFX(MemoryFence):
++ b AsmDataBarrierLoongArch
++ .end
+\ No newline at end of file
+diff --git a/MdePkg/Library/BaseLib/LoongArch64/SetJumpLongJump.S b/MdePkg/Library/BaseLib/LoongArch64/SetJumpLongJump.S
+new file mode 100644
+index 0000000..9db0397
+--- /dev/null
++++ b/MdePkg/Library/BaseLib/LoongArch64/SetJumpLongJump.S
+@@ -0,0 +1,49 @@
++#------------------------------------------------------------------------------
++#
++# Set/Long jump for LoongArch
++#
++# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
++#
++# SPDX-License-Identifier: BSD-2-Clause-Patent
++#
++#------------------------------------------------------------------------------
++
++#define STORE st.d /* 64 bit mode regsave instruction */
++#define LOAD ld.d /* 64 bit mode regload instruction */
++#define RSIZE 8 /* 64 bit mode register size */
++
++ASM_GLOBAL ASM_PFX(SetJump)
++ASM_GLOBAL ASM_PFX(InternalLongJump)
++
++ASM_PFX(SetJump):
++ STORE $s0, $a0, RSIZE * 0
++ STORE $s1, $a0, RSIZE * 1
++ STORE $s2, $a0, RSIZE * 2
++ STORE $s3, $a0, RSIZE * 3
++ STORE $s4, $a0, RSIZE * 4
++ STORE $s5, $a0, RSIZE * 5
++ STORE $s6, $a0, RSIZE * 6
++ STORE $s7, $a0, RSIZE * 7
++ STORE $s8, $a0, RSIZE * 8
++ STORE $sp, $a0, RSIZE * 9
++ STORE $fp, $a0, RSIZE * 10
++ STORE $ra, $a0, RSIZE * 11
++ li.w $a0, 0 # Setjmp return
++ jirl $zero, $ra, 0
++
++ASM_PFX(InternalLongJump):
++ LOAD $ra, $a0, RSIZE * 11
++ LOAD $s0, $a0, RSIZE * 0
++ LOAD $s1, $a0, RSIZE * 1
++ LOAD $s2, $a0, RSIZE * 2
++ LOAD $s3, $a0, RSIZE * 3
++ LOAD $s4, $a0, RSIZE * 4
++ LOAD $s5, $a0, RSIZE * 5
++ LOAD $s6, $a0, RSIZE * 6
++ LOAD $s7, $a0, RSIZE * 7
++ LOAD $s8, $a0, RSIZE * 8
++ LOAD $sp, $a0, RSIZE * 9
++ LOAD $fp, $a0, RSIZE * 10
++ move $a0, $a1
++ jirl $zero, $ra, 0
++ .end
+\ No newline at end of file
+diff --git a/MdePkg/Library/BaseLib/LoongArch64/SwitchStack.S b/MdePkg/Library/BaseLib/LoongArch64/SwitchStack.S
+new file mode 100644
+index 0000000..ca2707e
+--- /dev/null
++++ b/MdePkg/Library/BaseLib/LoongArch64/SwitchStack.S
+@@ -0,0 +1,39 @@
++#------------------------------------------------------------------------------
++#
++# InternalSwitchStackAsm for LoongArch
++#
++# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
++#
++# SPDX-License-Identifier: BSD-2-Clause-Patent
++#
++#------------------------------------------------------------------------------
++
++#define STORE st.d /* 64 bit mode regsave instruction */
++#define LOAD ld.d /* 64 bit mode regload instruction */
++#define RSIZE 8 /* 64 bit mode register size */
++
++ASM_GLOBAL ASM_PFX(InternalSwitchStackAsm)
++
++/**
++ This allows the caller to switch the stack and goes to the new entry point
++
++ @param JumpBuffer A pointer to CPU context buffer.
++**/
++
++ASM_PFX(InternalSwitchStackAsm):
++ LOAD $ra, $a0, RSIZE * 11
++ LOAD $s0, $a0, RSIZE * 0
++ LOAD $s1, $a0, RSIZE * 1
++ LOAD $s2, $a0, RSIZE * 2
++ LOAD $s3, $a0, RSIZE * 3
++ LOAD $s4, $a0, RSIZE * 4
++ LOAD $s5, $a0, RSIZE * 5
++ LOAD $s6, $a0, RSIZE * 6
++ LOAD $s7, $a0, RSIZE * 7
++ LOAD $s8, $a0, RSIZE * 8
++ LOAD $sp, $a0, RSIZE * 9
++ LOAD $fp, $a0, RSIZE * 10
++ LOAD $a0, $sp, 0
++ LOAD $a1, $sp, 8
++ jirl $zero, $ra, 0
++ .end
+\ No newline at end of file
+diff --git a/MdePkg/Library/BasePeCoffLib/LoongArch/PeCoffLoaderEx.c b/MdePkg/Library/BasePeCoffLib/LoongArch/PeCoffLoaderEx.c
+new file mode 100644
+index 0000000..615ebac
+--- /dev/null
++++ b/MdePkg/Library/BasePeCoffLib/LoongArch/PeCoffLoaderEx.c
+@@ -0,0 +1,137 @@
++/** @file
++ PE/Coff loader for LoongArch PE image
++
++ Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
++
++ SPDX-License-Identifier: BSD-2-Clause-Patent
++**/
++
++#include "BasePeCoffLibInternals.h"
++#include
++
++/**
++ Performs an LoongArch specific relocation fixup and is a no-op on other
++ instruction sets.
++
++ @param[in] Reloc Pointer to the relocation record.
++ @param[in, out] Fixup Pointer to the address to fix up.
++ @param[in, out] FixupData Pointer to a buffer to log the fixups.
++ @param[in] Adjust The offset to adjust the fixup.
++
++ @return Status code.
++
++**/
++RETURN_STATUS
++PeCoffLoaderRelocateImageEx (
++ IN UINT16 *Reloc,
++ IN OUT CHAR8 *Fixup,
++ IN OUT CHAR8 **FixupData,
++ IN UINT64 Adjust
++ )
++{
++ UINT8 RelocType;
++ UINT64 Value;
++ UINT64 Tmp1;
++ UINT64 Tmp2;
++
++ RelocType = (*Reloc) >> 12;
++ Value = 0;
++ Tmp1 = 0;
++ Tmp2 = 0;
++
++ switch (RelocType) {
++ case EFI_IMAGE_REL_BASED_LOONGARCH64_MARK_LA:
++ // The next four instructions are used to load a 64 bit address, relocate all of them
++ Value = (*(UINT32 *)Fixup & 0x1ffffe0) << 7 | // lu12i.w 20bits from bit5
++ (*((UINT32 *)Fixup + 1) & 0x3ffc00) >> 10; // ori 12bits from bit10
++ Tmp1 = *((UINT32 *)Fixup + 2) & 0x1ffffe0; // lu32i.d 20bits from bit5
++ Tmp2 = *((UINT32 *)Fixup + 3) & 0x3ffc00; // lu52i.d 12bits from bit10
++ Value = Value | (Tmp1 << 27) | (Tmp2 << 42);
++ Value += Adjust;
++
++ *(UINT32 *)Fixup = (*(UINT32 *)Fixup & ~0x1ffffe0) | (((Value >> 12) & 0xfffff) << 5);
++ if (*FixupData != NULL) {
++ *FixupData = ALIGN_POINTER (*FixupData, sizeof (UINT32));
++ *(UINT32 *)(*FixupData) = *(UINT32 *)Fixup;
++ *FixupData = *FixupData + sizeof (UINT32);
++ }
++
++ Fixup += sizeof (UINT32);
++ *(UINT32 *)Fixup = (*(UINT32 *)Fixup & ~0x3ffc00) | ((Value & 0xfff) << 10);
++ if (*FixupData != NULL) {
++ *FixupData = ALIGN_POINTER (*FixupData, sizeof (UINT32));
++ *(UINT32 *)(*FixupData) = *(UINT32 *)Fixup;
++ *FixupData = *FixupData + sizeof (UINT32);
++ }
++
++ Fixup += sizeof (UINT32);
++ *(UINT32 *)Fixup = (*(UINT32 *)Fixup & ~0x1ffffe0) | (((Value >> 32) & 0xfffff) << 5);
++ if (*FixupData != NULL) {
++ *FixupData = ALIGN_POINTER (*FixupData, sizeof (UINT32));
++ *(UINT32 *)(*FixupData) = *(UINT32 *)Fixup;
++ *FixupData = *FixupData + sizeof (UINT32);
++ }
++
++ Fixup += sizeof (UINT32);
++ *(UINT32 *)Fixup = (*(UINT32 *)Fixup & ~0x3ffc00) | (((Value >> 52) & 0xfff) << 10);
++ if (*FixupData != NULL) {
++ *FixupData = ALIGN_POINTER (*FixupData, sizeof (UINT32));
++ *(UINT32 *)(*FixupData) = *(UINT32 *)Fixup;
++ *FixupData = *FixupData + sizeof (UINT32);
++ }
++
++ break;
++ default:
++ return RETURN_UNSUPPORTED;
++ }
++
++ return RETURN_SUCCESS;
++}
++
++/**
++ Returns TRUE if the machine type of PE/COFF image is supported. Supported
++ does not mean the image can be executed it means the PE/COFF loader supports
++ loading and relocating of the image type. It's up to the caller to support
++ the entry point.
++
++ @param[in] Machine Machine type from the PE Header.
++
++ @return TRUE if this PE/COFF loader can load the image
++
++**/
++BOOLEAN
++PeCoffLoaderImageFormatSupported (
++ IN UINT16 Machine
++ )
++{
++ if (Machine == IMAGE_FILE_MACHINE_LOONGARCH64) {
++ return TRUE;
++ }
++
++ return FALSE;
++}
++
++/**
++ Performs an LOONGARCH-based specific re-relocation fixup and is a no-op on other
++ instruction sets. This is used to re-relocated the image into the EFI virtual
++ space for runtime calls.
++
++ @param[in] Reloc The pointer to the relocation record.
++ @param[in, out] Fixup The pointer to the address to fix up.
++ @param[in, out] FixupData The pointer to a buffer to log the fixups.
++ @param[in] Adjust The offset to adjust the fixup.
++
++ @return Status code.
++
++**/
++RETURN_STATUS
++PeHotRelocateImageEx (
++ IN UINT16 *Reloc,
++ IN OUT CHAR8 *Fixup,
++ IN OUT CHAR8 **FixupData,
++ IN UINT64 Adjust
++ )
++{
++ // To check
++ return PeCoffLoaderRelocateImageEx (Reloc, Fixup, FixupData, Adjust);
++}
+\ No newline at end of file
+diff --git a/MdePkg/Library/BaseSynchronizationLib/LoongArch64/AsmSynchronization.S b/MdePkg/Library/BaseSynchronizationLib/LoongArch64/AsmSynchronization.S
+new file mode 100644
+index 0000000..61cf4ed
+--- /dev/null
++++ b/MdePkg/Library/BaseSynchronizationLib/LoongArch64/AsmSynchronization.S
+@@ -0,0 +1,122 @@
++#------------------------------------------------------------------------------
++#
++# LoongArch synchronization ASM functions.
++#
++# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
++#
++# SPDX-License-Identifier: BSD-2-Clause-Patent
++#
++#------------------------------------------------------------------------------
++
++ASM_GLOBAL ASM_PFX(AsmInternalSyncCompareExchange16)
++ASM_GLOBAL ASM_PFX(AsmInternalSyncCompareExchange32)
++ASM_GLOBAL ASM_PFX(AsmInternalSyncCompareExchange64)
++ASM_GLOBAL ASM_PFX(AsmInternalSyncIncrement)
++ASM_GLOBAL ASM_PFX(AsmInternalSyncDecrement)
++
++/**
++UINT32
++EFIAPI
++AsmInternalSyncCompareExchange16 (
++ IN volatile UINT32 *Ptr32,
++ IN UINT64 Mask,
++ IN UINT64 LocalCompareValue,
++ IN UINT64 LocalExchangeValue
++ )
++**/
++ASM_PFX(AsmInternalSyncCompareExchange16):
++1:
++ ll.w $t0, $a0, 0x0
++ and $t1, $t0, $a1
++ bne $t1, $a2, 2f
++ andn $t1, $t0, $a1
++ or $t1, $t1, $a3
++ sc.w $t1, $a0, 0x0
++ beqz $t1, 1b
++ b 3f
++2:
++ dbar 0
++3:
++ move $a0, $t0
++ jirl $zero, $ra, 0
++
++/**
++UINT32
++EFIAPI
++AsmInternalSyncCompareExchange32 (
++ IN volatile UINT32 *Value,
++ IN UINT64 CompareValue,
++ IN UINT64 ExchangeValue
++ )
++**/
++ASM_PFX(AsmInternalSyncCompareExchange32):
++1:
++ ll.w $t0, $a0, 0x0
++ bne $t0, $a1, 2f
++ move $t0, $a2
++ sc.w $t0, $a0, 0x0
++ beqz $t0, 1b
++ b 3f
++2:
++ dbar 0
++3:
++ move $a0, $t0
++ jirl $zero, $ra, 0
++
++/**
++UINT64
++EFIAPI
++AsmInternalSyncCompareExchange64 (
++ IN volatile UINT64 *Value,
++ IN UINT64 CompareValue,
++ IN UINT64 ExchangeValue
++ )
++**/
++ASM_PFX(AsmInternalSyncCompareExchange64):
++1:
++ ll.d $t0, $a0, 0x0
++ bne $t0, $a1, 2f
++ move $t0, $a2
++ sc.d $t0, $a0, 0x0
++ beqz $t0, 1b
++ b 3f
++2:
++ dbar 0
++3:
++ move $a0, $t0
++ jirl $zero, $ra, 0
++
++/**
++UINT32
++EFIAPI
++AsmInternalSyncIncrement (
++ IN volatile UINT32 *Value
++ )
++**/
++ASM_PFX(AsmInternalSyncIncrement):
++ move $t0, $a0
++ dbar 0
++ ld.w $t1, $t0, 0x0
++ li.w $t2, 1
++ amadd.w $t1, $t2, $t0
++
++ ld.w $a0, $t0, 0x0
++ jirl $zero, $ra, 0
++
++/**
++UINT32
++EFIAPI
++AsmInternalSyncDecrement (
++ IN volatile UINT32 *Value
++ )
++**/
++ASM_PFX(AsmInternalSyncDecrement):
++ move $t0, $a0
++ dbar 0
++ ld.w $t1, $t0, 0x0
++ li.w $t2, -1
++ amadd.w $t1, $t2, $t0
++
++ ld.w $a0, $t0, 0x0
++ jirl $zero, $ra, 0
++.end
+\ No newline at end of file
+diff --git a/MdePkg/Library/BaseSynchronizationLib/LoongArch64/Synchronization.c b/MdePkg/Library/BaseSynchronizationLib/LoongArch64/Synchronization.c
+new file mode 100644
+index 0000000..e62da9d
+--- /dev/null
++++ b/MdePkg/Library/BaseSynchronizationLib/LoongArch64/Synchronization.c
+@@ -0,0 +1,233 @@
++/** @file
++ LoongArch synchronization functions.
++
++ Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
++
++ SPDX-License-Identifier: BSD-2-Clause-Patent
++
++**/
++
++#include
++
++UINT32
++EFIAPI
++AsmInternalSyncCompareExchange16 (
++ IN volatile UINT32 *,
++ IN UINT64,
++ IN UINT64,
++ IN UINT64
++ );
++
++UINT32
++EFIAPI
++AsmInternalSyncCompareExchange32 (
++ IN volatile UINT32 *,
++ IN UINT64,
++ IN UINT64
++ );
++
++UINT64
++EFIAPI
++AsmInternalSyncCompareExchange64 (
++ IN volatile UINT64 *,
++ IN UINT64,
++ IN UINT64
++ );
++
++UINT32
++EFIAPI
++AsmInternalSyncIncrement (
++ IN volatile UINT32 *
++ );
++
++UINT32
++EFIAPI
++AsmInternalSyncDecrement (
++ IN volatile UINT32 *
++ );
++
++/**
++ Performs an atomic compare exchange operation on a 16-bit
++ unsigned integer.
++
++ Performs an atomic compare exchange operation on the 16-bit
++ unsigned integer specified by Value. If Value is equal to
++ CompareValue, then Value is set to ExchangeValue and
++ CompareValue is returned. If Value is not equal to
++ CompareValue, then Value is returned. The compare exchange
++ operation must be performed using MP safe mechanisms.
++
++ @param[in] Value A pointer to the 16-bit value for the
++ compare exchange operation.
++ @param[in] CompareValue 16-bit value used in compare operation.
++ @param[in] ExchangeValue 16-bit value used in exchange operation.
++
++ @return The original *Value before exchange.
++
++**/
++UINT16
++EFIAPI
++InternalSyncCompareExchange16 (
++ IN volatile UINT16 *Value,
++ IN UINT16 CompareValue,
++ IN UINT16 ExchangeValue
++ )
++{
++ UINT32 RetValue;
++ UINT32 Shift;
++ UINT64 Mask;
++ UINT64 LocalCompareValue;
++ UINT64 LocalExchangeValue;
++ volatile UINT32 *Ptr32;
++
++ /* Check that ptr is naturally aligned */
++ ASSERT (!((UINT64)Value & (sizeof (Value) - 1)));
++
++ /* Mask inputs to the correct size. */
++ Mask = (((~0UL) - (1UL << (0)) + 1) & (~0UL >> (64 - 1 - ((sizeof (UINT16) * 8) - 1))));
++ LocalCompareValue = ((UINT64)CompareValue) & Mask;
++ LocalExchangeValue = ((UINT64)ExchangeValue) & Mask;
++
++ /*
++ * Calculate a shift & mask that correspond to the value we wish to
++ * compare & exchange within the naturally aligned 4 byte integer
++ * that includes it.
++ */
++ Shift = (UINT64)Value & 0x3;
++ Shift *= 8; /* BITS_PER_BYTE */
++ LocalCompareValue <<= Shift;
++ LocalExchangeValue <<= Shift;
++ Mask <<= Shift;
++
++ /*
++ * Calculate a pointer to the naturally aligned 4 byte integer that
++ * includes our byte of interest, and load its value.
++ */
++ Ptr32 = (UINT32 *)((UINT64)Value & ~0x3);
++
++ RetValue = AsmInternalSyncCompareExchange16 (
++ Ptr32,
++ Mask,
++ LocalCompareValue,
++ LocalExchangeValue
++ );
++
++ return (RetValue & Mask) >> Shift;
++}
++
++/**
++ Performs an atomic compare exchange operation on a 32-bit
++ unsigned integer.
++
++ Performs an atomic compare exchange operation on the 32-bit
++ unsigned integer specified by Value. If Value is equal to
++ CompareValue, then Value is set to ExchangeValue and
++ CompareValue is returned. If Value is not equal to
++ CompareValue, then Value is returned. The compare exchange
++ operation must be performed using MP safe mechanisms.
++
++ @param[in] Value A pointer to the 32-bit value for the
++ compare exchange operation.
++ @param[in] CompareValue 32-bit value used in compare operation.
++ @param[in] ExchangeValue 32-bit value used in exchange operation.
++
++ @return The original *Value before exchange.
++
++**/
++UINT32
++EFIAPI
++InternalSyncCompareExchange32 (
++ IN volatile UINT32 *Value,
++ IN UINT32 CompareValue,
++ IN UINT32 ExchangeValue
++ )
++{
++ UINT32 RetValue;
++
++ RetValue = AsmInternalSyncCompareExchange32 (
++ Value,
++ CompareValue,
++ ExchangeValue
++ );
++
++ return RetValue;
++}
++
++/**
++ Performs an atomic compare exchange operation on a 64-bit unsigned integer.
++
++ Performs an atomic compare exchange operation on the 64-bit unsigned integer specified
++ by Value. If Value is equal to CompareValue, then Value is set to ExchangeValue and
++ CompareValue is returned. If Value is not equal to CompareValue, then Value is returned.
++ The compare exchange operation must be performed using MP safe mechanisms.
++
++ @param[in] Value A pointer to the 64-bit value for the compare exchange
++ operation.
++ @param[in] CompareValue 64-bit value used in compare operation.
++ @param[in] ExchangeValue 64-bit value used in exchange operation.
++
++ @return The original *Value before exchange.
++
++**/
++UINT64
++EFIAPI
++InternalSyncCompareExchange64 (
++ IN volatile UINT64 *Value,
++ IN UINT64 CompareValue,
++ IN UINT64 ExchangeValue
++ )
++{
++ UINT64 RetValue;
++
++ RetValue = AsmInternalSyncCompareExchange64 (
++ Value,
++ CompareValue,
++ ExchangeValue
++ );
++
++ return RetValue;
++}
++
++/**
++ Performs an atomic increment of an 32-bit unsigned integer.
++
++ Performs an atomic increment of the 32-bit unsigned integer specified by
++ Value and returns the incremented value. The increment operation must be
++ performed using MP safe mechanisms. The state of the return value is not
++ guaranteed to be MP safe.
++
++ @param[in] Value A pointer to the 32-bit value to increment.
++
++ @return The incremented value.
++
++**/
++UINT32
++EFIAPI
++InternalSyncIncrement (
++ IN volatile UINT32 *Value
++ )
++{
++ return AsmInternalSyncIncrement (Value);
++}
++
++/**
++ Performs an atomic decrement of an 32-bit unsigned integer.
++
++ Performs an atomic decrement of the 32-bit unsigned integer specified by
++ Value and returns the decrement value. The decrement operation must be
++ performed using MP safe mechanisms. The state of the return value is not
++ guaranteed to be MP safe.
++
++ @param[in] Value A pointer to the 32-bit value to decrement.
++
++ @return The decrement value.
++
++**/
++UINT32
++EFIAPI
++InternalSyncDecrement (
++ IN volatile UINT32 *Value
++ )
++{
++ return AsmInternalSyncDecrement (Value);
++}
+\ No newline at end of file
diff --git a/edk2.spec b/edk2.spec
index 03cd814273defd5a05a3362fdfa8c37afaae11de..050c3c3d27cb625631051071cecb1ef89d042782 100644
--- a/edk2.spec
+++ b/edk2.spec
@@ -5,7 +5,7 @@
Name: edk2
Version: %{stable_date}
-Release: 13
+Release: 14
Summary: EFI Development Kit II
License: BSD-2-Clause-Patent
URL: https://github.com/tianocore/edk2
@@ -60,10 +60,13 @@ Patch0032: 0032-BaseTools-GenEfs-GenSec-fix-gcc12-warning.patch
Patch0033: 0033-BaseTools-LzmaCompress-fix-gcc12-warning.patch
Patch0034: 0034-Basetools-turn-off-gcc12-warning.patch
+Patch1000: 1000-add-LoongArch-support-not-upstream-modify-files.patch
+Patch1001: 1001-add-LoongArch-support-not-upstream-new-files.patch
+
BuildRequires: acpica-tools gcc gcc-c++ libuuid-devel python3 bc nasm python3-unversioned-command
%description
-EDK II is a modern, feature-rich, cross-platform firmware development environment for the UEFI and PI specifications.
+EDK II is a modern, feature-rich, cross-platform firmware development environment for the UEFI and PI specifications.
%package devel
Summary: EFI Development Kit II Tools
@@ -133,6 +136,9 @@ COMMON_FLAGS="-D NETWORK_IP6_ENABLE"
%ifarch %{ix86}
BUILD_OPTION="$BUILD_OPTION -a IA32 -p OvmfPkg/OvmfPkgIa32.dsc"
%endif
+%ifarch loongarch64
+ BUILD_OPTION="$BUILD_OPTION -a LOONGARCH64 -p ShellPkg/ShellPkg.dsc $COMMON_FLAGS"
+%endif
BUILD_OPTION="$BUILD_OPTION -D SECURE_BOOT_ENABLE=TRUE"
BUILD_OPTION="$BUILD_OPTION -D TPM2_ENABLE=TRUE"
BUILD_OPTION="$BUILD_OPTION -D TPM2_CONFIG_ENABLE=TRUE"
@@ -151,7 +157,7 @@ install BaseTools/Conf/*.template %{buildroot}%{_datadir}/%{name}/Conf
install BaseTools/Scripts/GccBase.lds %{buildroot}%{_datadir}/%{name}/Scripts
cp -R BaseTools/Source/Python %{buildroot}%{_datadir}/%{name}/Python
-find %{buildroot}%{_datadir}/%{name}/Python -name '__pycache__'|xargs rm -rf
+find %{buildroot}%{_datadir}/%{name}/Python -name '__pycache__'|xargs rm -rf
for i in build BPDG GenDepex GenFds GenPatchPcdTable PatchPcdValue Pkcs7Sign Rsa2048Sha256Sign TargetTool Trim UPT; do
echo '#!/usr/bin/env bash
@@ -260,6 +266,9 @@ chmod +x %{buildroot}%{_bindir}/Rsa2048Sha256GenerateKeys
%endif
%changelog
+* Tue May 09 2023 herengui - 202011-14
+- add support loongarch64
+
* Thu Jul 13 2023 Jiabo Feng - 202011-13
- solving the compilation failure problem of gcc 12.3.0