From aa692fe8f8e62911656ab7c8599a6995a402e5d8 Mon Sep 17 00:00:00 2001 From: jchzhou Date: Fri, 1 Aug 2025 17:43:21 +0800 Subject: [PATCH] backport RISC-V RVA23 support, phase 1 Signed-off-by: Yunqiang Su Signed-off-by: jchzhou --- ...V-Add-basic-Zaamo-and-Zalrsc-support.patch | 452 ++++++++++++ ...ing-shift-for-scatter-gather-if-appl.patch | 368 ++++++++++ ...d-Zalrsc-and-Zaamo-testsuite-support.patch | 622 +++++++++++++++++ 0004-RISC-V-Add-Zalrsc-amo-op-patterns.patch | 375 ++++++++++ ...RISC-V-Move-amo-tests-into-subfolder.patch | 645 ++++++++++++++++++ 0006-RISC-V-Fix-amoadd-call-arguments.patch | 410 +++++++++++ ...gure-check-for-Zaamo-Zalrsc-assemble.patch | 144 ++++ ...aamo-Zalrsc-to-a-when-using-an-old-b.patch | 39 ++ 0009-RISC-V-Rename-amo-testcases.patch | 315 +++++++++ ...Add-support-for-B-standard-extension.patch | 70 ++ ...figure-check-for-B-extention-support.patch | 137 ++++ ...mplies-zca-and-conditionally-zcf-zcd.patch | 202 ++++++ ...SC-V-Add-implication-for-M-extension.patch | 308 +++++++++ ...-Minimal-support-for-Zimop-extension.patch | 106 +++ gcc-14.spec | 19 +- 15 files changed, 4211 insertions(+), 1 deletion(-) create mode 100644 0001-RISC-V-Add-basic-Zaamo-and-Zalrsc-support.patch create mode 100644 0002-RISC-V-Use-widening-shift-for-scatter-gather-if-appl.patch create mode 100644 0003-RISC-V-Add-Zalrsc-and-Zaamo-testsuite-support.patch create mode 100644 0004-RISC-V-Add-Zalrsc-amo-op-patterns.patch create mode 100644 0005-RISC-V-Move-amo-tests-into-subfolder.patch create mode 100644 0006-RISC-V-Fix-amoadd-call-arguments.patch create mode 100644 0007-RISC-V-Add-configure-check-for-Zaamo-Zalrsc-assemble.patch create mode 100644 0008-RISC-V-Promote-Zaamo-Zalrsc-to-a-when-using-an-old-b.patch create mode 100644 0009-RISC-V-Rename-amo-testcases.patch create mode 100644 0010-RISC-V-Add-support-for-B-standard-extension.patch create mode 100644 0011-RISC-V-Add-configure-check-for-B-extention-support.patch create mode 100644 0012-RISC-V-c-implies-zca-and-conditionally-zcf-zcd.patch create mode 100644 0013-RISC-V-RISC-V-Add-implication-for-M-extension.patch create mode 100644 0014-RISC-V-Minimal-support-for-Zimop-extension.patch diff --git a/0001-RISC-V-Add-basic-Zaamo-and-Zalrsc-support.patch b/0001-RISC-V-Add-basic-Zaamo-and-Zalrsc-support.patch new file mode 100644 index 0000000..c0a673c --- /dev/null +++ b/0001-RISC-V-Add-basic-Zaamo-and-Zalrsc-support.patch @@ -0,0 +1,452 @@ +From 189b0f2386cb73cd8d80e0a047e8563e51e7d91a Mon Sep 17 00:00:00 2001 +From: Edwin Lu +Date: Wed, 7 Feb 2024 16:30:28 -0800 +Subject: [PATCH 01/29] RISC-V: Add basic Zaamo and Zalrsc support + +There is a proposal to split the A extension into two parts: Zaamo and Zalrsc. +This patch adds basic support by making the A extension imply Zaamo and +Zalrsc. + +Proposal: https://github.com/riscv/riscv-zaamo-zalrsc/tags + +gcc/ChangeLog: + + * common/config/riscv/riscv-common.cc: Add Zaamo and Zalrsc. + * config/riscv/arch-canonicalize: Make A imply Zaamo and Zalrsc. + * config/riscv/riscv.opt: Add Zaamo and Zalrsc + * config/riscv/sync.md: Convert TARGET_ATOMIC to TARGET_ZAAMO and + TARGET_ZALRSC. + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/attribute-15.c: Adjust expected arch string. + * gcc.target/riscv/attribute-16.c: Ditto. + * gcc.target/riscv/attribute-17.c: Ditto. + * gcc.target/riscv/attribute-18.c: Ditto. + * gcc.target/riscv/attribute-01.c: Ditto. + * gcc.target/riscv/attribute-02.c: Ditto. + * gcc.target/riscv/attribute-08.c: Ditto. + * gcc.target/riscv/attribute-11.c: Ditto. + * gcc.target/riscv/attribute-14.c: Ditto. + * gcc.target/riscv/pr110696.c: Ditto. + * gcc.target/riscv/rvv/base/pr114352-1.c: Ditto. + * gcc.target/riscv/rvv/base/pr114352-3.c: Ditto. + +Signed-off-by: Edwin Lu +Co-authored-by: Patrick O'Neill +(cherry picked from commit af139b3fc19fbdd7caa649bcb2cb75cc5a254143) +--- + gcc/common/config/riscv/riscv-common.cc | 11 +++++-- + gcc/config/riscv/arch-canonicalize | 1 + + gcc/config/riscv/riscv.opt | 6 +++- + gcc/config/riscv/sync.md | 30 +++++++++---------- + gcc/testsuite/gcc.target/riscv/attribute-15.c | 2 +- + gcc/testsuite/gcc.target/riscv/attribute-16.c | 2 +- + gcc/testsuite/gcc.target/riscv/attribute-17.c | 2 +- + gcc/testsuite/gcc.target/riscv/attribute-18.c | 2 +- + gcc/testsuite/gcc.target/riscv/pr110696.c | 2 +- + .../gcc.target/riscv/rvv/base/pr114352-1.c | 4 +-- + .../gcc.target/riscv/rvv/base/pr114352-3.c | 8 ++--- + .../gcc.target/riscv/target-attr-01.c | 2 +- + .../gcc.target/riscv/target-attr-02.c | 2 +- + .../gcc.target/riscv/target-attr-08.c | 2 +- + .../gcc.target/riscv/target-attr-11.c | 2 +- + .../gcc.target/riscv/target-attr-14.c | 4 +-- + .../gcc.target/riscv/target-attr-15.c | 4 +-- + .../gcc.target/riscv/target-attr-16.c | 4 +-- + 18 files changed, 51 insertions(+), 39 deletions(-) + +diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc +index 1c71ea43f1d..0039a27a8da 100644 +--- a/gcc/common/config/riscv/riscv-common.cc ++++ b/gcc/common/config/riscv/riscv-common.cc +@@ -79,6 +79,9 @@ static const riscv_implied_info_t riscv_implied_info[] = + {"f", "zicsr"}, + {"d", "zicsr"}, + ++ {"a", "zaamo"}, ++ {"a", "zalrsc"}, ++ + {"zdinx", "zfinx"}, + {"zfinx", "zicsr"}, + {"zdinx", "zicsr"}, +@@ -252,6 +255,8 @@ static const struct riscv_ext_version riscv_ext_version_table[] = + {"za64rs", ISA_SPEC_CLASS_NONE, 1, 0}, + {"za128rs", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zawrs", ISA_SPEC_CLASS_NONE, 1, 0}, ++ {"zaamo", ISA_SPEC_CLASS_NONE, 1, 0}, ++ {"zalrsc", ISA_SPEC_CLASS_NONE, 1, 0}, + + {"zba", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zbb", ISA_SPEC_CLASS_NONE, 1, 0}, +@@ -1527,9 +1532,11 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = + {"zifencei", &gcc_options::x_riscv_zi_subext, MASK_ZIFENCEI}, + {"zicond", &gcc_options::x_riscv_zi_subext, MASK_ZICOND}, + +- {"za64rs", &gcc_options::x_riscv_za_subext, MASK_ZA64RS}, ++ {"za64rs", &gcc_options::x_riscv_za_subext, MASK_ZA64RS}, + {"za128rs", &gcc_options::x_riscv_za_subext, MASK_ZA128RS}, +- {"zawrs", &gcc_options::x_riscv_za_subext, MASK_ZAWRS}, ++ {"zawrs", &gcc_options::x_riscv_za_subext, MASK_ZAWRS}, ++ {"zaamo", &gcc_options::x_riscv_za_subext, MASK_ZAAMO}, ++ {"zalrsc", &gcc_options::x_riscv_za_subext, MASK_ZALRSC}, + + {"zba", &gcc_options::x_riscv_zb_subext, MASK_ZBA}, + {"zbb", &gcc_options::x_riscv_zb_subext, MASK_ZBB}, +diff --git a/gcc/config/riscv/arch-canonicalize b/gcc/config/riscv/arch-canonicalize +index 8f7d040cdeb..6c10d1aa81b 100755 +--- a/gcc/config/riscv/arch-canonicalize ++++ b/gcc/config/riscv/arch-canonicalize +@@ -40,6 +40,7 @@ LONG_EXT_PREFIXES = ['z', 's', 'h', 'x'] + # + IMPLIED_EXT = { + "d" : ["f", "zicsr"], ++ "a" : ["zaamo", "zalrsc"], + "f" : ["zicsr"], + "zdinx" : ["zfinx", "zicsr"], + "zfinx" : ["zicsr"], +diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt +index 085dd616b63..8e6cba27066 100644 +--- a/gcc/config/riscv/riscv.opt ++++ b/gcc/config/riscv/riscv.opt +@@ -248,7 +248,11 @@ Mask(ZICCRSE) Var(riscv_zi_subext) + TargetVariable + int riscv_za_subext + +-Mask(ZAWRS) Var(riscv_za_subext) ++Mask(ZAWRS) Var(riscv_za_subext) ++ ++Mask(ZAAMO) Var(riscv_za_subext) ++ ++Mask(ZALRSC) Var(riscv_za_subext) + + Mask(ZA64RS) Var(riscv_za_subext) + +diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md +index be31ddb9798..f44c69d34f7 100644 +--- a/gcc/config/riscv/sync.md ++++ b/gcc/config/riscv/sync.md +@@ -93,7 +93,7 @@ + (match_operand:GPR 1 "reg_or_0_operand" "rJ")) + (match_operand:SI 2 "const_int_operand")] ;; model + UNSPEC_SYNC_OLD_OP))] +- "TARGET_ATOMIC" ++ "TARGET_ZAAMO" + "amo.%A2\tzero,%z1,%0" + [(set_attr "type" "atomic") + (set (attr "length") (const_int 4))]) +@@ -107,7 +107,7 @@ + (match_operand:GPR 2 "reg_or_0_operand" "rJ")) + (match_operand:SI 3 "const_int_operand")] ;; model + UNSPEC_SYNC_OLD_OP))] +- "TARGET_ATOMIC" ++ "TARGET_ZAAMO" + "amo.%A3\t%0,%z2,%1" + [(set_attr "type" "atomic") + (set (attr "length") (const_int 4))]) +@@ -125,7 +125,7 @@ + (match_operand:SI 5 "register_operand" "rI") ;; not_mask + (clobber (match_scratch:SI 6 "=&r")) ;; tmp_1 + (clobber (match_scratch:SI 7 "=&r"))] ;; tmp_2 +- "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" ++ "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC" + { + return "1:\;" + "lr.w%I3\t%0, %1\;" +@@ -144,7 +144,7 @@ + (not:SHORT (and:SHORT (match_operand:SHORT 1 "memory_operand") ;; mem location + (match_operand:SHORT 2 "reg_or_0_operand"))) ;; value for op + (match_operand:SI 3 "const_int_operand")] ;; model +- "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" ++ "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC" + { + /* We have no QImode/HImode atomics, so form a mask, then use + subword_atomic_fetch_strong_nand to implement a LR/SC version of the +@@ -192,7 +192,7 @@ + (match_operand:SI 5 "register_operand" "rI") ;; not_mask + (clobber (match_scratch:SI 6 "=&r")) ;; tmp_1 + (clobber (match_scratch:SI 7 "=&r"))] ;; tmp_2 +- "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" ++ "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC" + { + return "1:\;" + "lr.w%I3\t%0, %1\;" +@@ -212,7 +212,7 @@ + (any_atomic:SHORT (match_operand:SHORT 1 "memory_operand") ;; mem location + (match_operand:SHORT 2 "reg_or_0_operand")) ;; value for op + (match_operand:SI 3 "const_int_operand")] ;; model +- "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" ++ "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC" + { + /* We have no QImode/HImode atomics, so form a mask, then use + subword_atomic_fetch_strong_ to implement a LR/SC version of the +@@ -256,7 +256,7 @@ + UNSPEC_SYNC_EXCHANGE)) + (set (match_dup 1) + (match_operand:GPR 2 "register_operand" "0"))] +- "TARGET_ATOMIC" ++ "TARGET_ZAAMO" + "amoswap.%A3\t%0,%z2,%1" + [(set_attr "type" "atomic") + (set (attr "length") (const_int 4))]) +@@ -266,7 +266,7 @@ + (match_operand:SHORT 1 "memory_operand") ;; mem location + (match_operand:SHORT 2 "register_operand") ;; value + (match_operand:SI 3 "const_int_operand")] ;; model +- "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" ++ "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC" + { + rtx old = gen_reg_rtx (SImode); + rtx mem = operands[1]; +@@ -304,7 +304,7 @@ + UNSPEC_SYNC_EXCHANGE_SUBWORD)) + (match_operand:SI 4 "reg_or_0_operand" "rI") ;; not_mask + (clobber (match_scratch:SI 5 "=&r"))] ;; tmp_1 +- "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" ++ "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC" + { + return "1:\;" + "lr.w%I3\t%0, %1\;" +@@ -326,7 +326,7 @@ + (match_operand:SI 5 "const_int_operand")] ;; mod_f + UNSPEC_COMPARE_AND_SWAP)) + (clobber (match_scratch:GPR 6 "=&r"))] +- "TARGET_ATOMIC" ++ "TARGET_ZALRSC" + { + enum memmodel model_success = (enum memmodel) INTVAL (operands[4]); + enum memmodel model_failure = (enum memmodel) INTVAL (operands[5]); +@@ -352,7 +352,7 @@ + (match_operand:SI 5 "const_int_operand" "") ;; is_weak + (match_operand:SI 6 "const_int_operand" "") ;; mod_s + (match_operand:SI 7 "const_int_operand" "")] ;; mod_f +- "TARGET_ATOMIC" ++ "TARGET_ZALRSC" + { + if (word_mode != mode && operands[3] != const0_rtx) + { +@@ -395,7 +395,7 @@ + (match_operand:SI 5 "const_int_operand") ;; is_weak + (match_operand:SI 6 "const_int_operand") ;; mod_s + (match_operand:SI 7 "const_int_operand")] ;; mod_f +- "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" ++ "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC" + { + emit_insn (gen_atomic_cas_value_strong (operands[1], operands[2], + operands[3], operands[4], +@@ -440,7 +440,7 @@ + (match_operand:SI 4 "const_int_operand") ;; mod_s + (match_operand:SI 5 "const_int_operand") ;; mod_f + (match_scratch:SHORT 6)] +- "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" ++ "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC" + { + /* We have no QImode/HImode atomics, so form a mask, then use + subword_atomic_cas_strong to implement a LR/SC version of the +@@ -498,7 +498,7 @@ + (match_operand:SI 5 "register_operand" "rI") ;; mask + (match_operand:SI 6 "register_operand" "rI") ;; not_mask + (clobber (match_scratch:SI 7 "=&r"))] ;; tmp_1 +- "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" ++ "TARGET_ZALRSC && TARGET_INLINE_SUBWORD_ATOMIC" + { + return "1:\;" + "lr.w%I4\t%0, %1\;" +@@ -517,7 +517,7 @@ + [(match_operand:QI 0 "register_operand" "") ;; bool output + (match_operand:QI 1 "memory_operand" "+A") ;; memory + (match_operand:SI 2 "const_int_operand" "")] ;; model +- "TARGET_ATOMIC" ++ "TARGET_ZALRSC" + { + /* We have no QImode atomics, so use the address LSBs to form a mask, + then use an aligned SImode atomic. */ +diff --git a/gcc/testsuite/gcc.target/riscv/attribute-15.c b/gcc/testsuite/gcc.target/riscv/attribute-15.c +index 59efeb6ea45..a2e394b6489 100644 +--- a/gcc/testsuite/gcc.target/riscv/attribute-15.c ++++ b/gcc/testsuite/gcc.target/riscv/attribute-15.c +@@ -3,4 +3,4 @@ + int foo() + { + } +-/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0\"" } } */ ++/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zaamo1p0_zalrsc1p0\"" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/attribute-16.c b/gcc/testsuite/gcc.target/riscv/attribute-16.c +index 26f961efb48..d2b18160cb5 100644 +--- a/gcc/testsuite/gcc.target/riscv/attribute-16.c ++++ b/gcc/testsuite/gcc.target/riscv/attribute-16.c +@@ -3,4 +3,4 @@ + int foo() + { + } +-/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_m2p0_a2p0_f2p2_d2p2_c2p0_zicsr2p0" } } */ ++/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_m2p0_a2p0_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0\"" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/attribute-17.c b/gcc/testsuite/gcc.target/riscv/attribute-17.c +index 0abff3705d9..fc2f488a3ac 100644 +--- a/gcc/testsuite/gcc.target/riscv/attribute-17.c ++++ b/gcc/testsuite/gcc.target/riscv/attribute-17.c +@@ -3,4 +3,4 @@ + int foo() + { + } +-/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0" } } */ ++/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0\"" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/attribute-18.c b/gcc/testsuite/gcc.target/riscv/attribute-18.c +index fddbf15fc3e..eefd602103d 100644 +--- a/gcc/testsuite/gcc.target/riscv/attribute-18.c ++++ b/gcc/testsuite/gcc.target/riscv/attribute-18.c +@@ -1,4 +1,4 @@ + /* { dg-do compile } */ + /* { dg-options "-mriscv-attribute -march=rv64imafdc -mabi=lp64d -misa-spec=2.2" } */ + int foo() {} +-/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0\"" } } */ ++/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zaamo1p0_zalrsc1p0\"" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/pr110696.c b/gcc/testsuite/gcc.target/riscv/pr110696.c +index a630f04e74f..08682a047e0 100644 +--- a/gcc/testsuite/gcc.target/riscv/pr110696.c ++++ b/gcc/testsuite/gcc.target/riscv/pr110696.c +@@ -4,4 +4,4 @@ int foo() + { + } + +-/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0\"" } } */ ++/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0\"" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c +index b3f1f20fb79..faeb406498d 100644 +--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c ++++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c +@@ -54,5 +54,5 @@ test_3 (int *a, int *b, int *out, unsigned count) + out[i] = a[i] + b[i]; + } + +-/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0\"" } } */ +-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */ ++/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0\"" } } */ ++/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c +index e7af4223d6a..38815ef5bd0 100644 +--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c ++++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c +@@ -107,7 +107,7 @@ test_6 (_Float16 *a, _Float16 *b, _Float16 *out, unsigned count) + out[i] = a[i] + b[i]; + } + +-/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0\"" } } */ +-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */ +-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zbb1p0" } } */ +-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zfh1p0_zfhmin1p0" } } */ ++/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0\"" } } */ ++/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */ ++/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zbb1p0" } } */ ++/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zfh1p0_zfhmin1p0" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/target-attr-01.c b/gcc/testsuite/gcc.target/riscv/target-attr-01.c +index 1bf108e9d72..4748f6a08e7 100644 +--- a/gcc/testsuite/gcc.target/riscv/target-attr-01.c ++++ b/gcc/testsuite/gcc.target/riscv/target-attr-01.c +@@ -9,7 +9,7 @@ + ** sh1add\s*a0,a1,a0 + ** ... + */ +-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zba1p0" } } */ ++/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zba1p0" } } */ + long foo () __attribute__((target("arch=rv64gc_zba"))); + long foo (long a, long b) + { +diff --git a/gcc/testsuite/gcc.target/riscv/target-attr-02.c b/gcc/testsuite/gcc.target/riscv/target-attr-02.c +index 3d0c8a72f59..9ebf16e3675 100644 +--- a/gcc/testsuite/gcc.target/riscv/target-attr-02.c ++++ b/gcc/testsuite/gcc.target/riscv/target-attr-02.c +@@ -9,7 +9,7 @@ + ** sh1add\s*a0,a1,a0 + ** ... + */ +-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zba1p0" } } */ ++/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zba1p0" } } */ + long foo () __attribute__((target("arch=+zba"))); + long foo (long a, long b) + { +diff --git a/gcc/testsuite/gcc.target/riscv/target-attr-08.c b/gcc/testsuite/gcc.target/riscv/target-attr-08.c +index 43c7141139e..e7792c1598e 100644 +--- a/gcc/testsuite/gcc.target/riscv/target-attr-08.c ++++ b/gcc/testsuite/gcc.target/riscv/target-attr-08.c +@@ -13,7 +13,7 @@ __attribute__((target("arch=rv64gc_zba"))); + ** sh1add\s*a0,a1,a0 + ** ... + */ +-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zba1p0" } } */ ++/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zba1p0" } } */ + long foo (long a, long b) + { + return a + (b * 2); +diff --git a/gcc/testsuite/gcc.target/riscv/target-attr-11.c b/gcc/testsuite/gcc.target/riscv/target-attr-11.c +index b79e6de6468..6e02a98f120 100644 +--- a/gcc/testsuite/gcc.target/riscv/target-attr-11.c ++++ b/gcc/testsuite/gcc.target/riscv/target-attr-11.c +@@ -15,7 +15,7 @@ __attribute__((target("arch=rv64gc_zba"))); + ** sh1add\s*a0,a1,a0 + ** ... + */ +-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zba1p0" } } */ ++/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zba1p0" } } */ + long foo (long a, long b) + { + return a + (b * 2); +diff --git a/gcc/testsuite/gcc.target/riscv/target-attr-14.c b/gcc/testsuite/gcc.target/riscv/target-attr-14.c +index ad42c389287..59de060eec3 100644 +--- a/gcc/testsuite/gcc.target/riscv/target-attr-14.c ++++ b/gcc/testsuite/gcc.target/riscv/target-attr-14.c +@@ -9,7 +9,7 @@ + ** sh1add\s*a0,a1,a0 + ** ... + */ +-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zba1p0" } } */ ++/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zba1p0" } } */ + long foo () __attribute__((target("arch=rv64gc_zba"))); + long foo (long a, long b) + { +@@ -34,7 +34,7 @@ long bar (long a, long b) + ** th.addsl\s*a0,a0,a1,1 + ** ... + */ +-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_xtheadba1p0" } } */ ++/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_xtheadba1p0" } } */ + long foo_th () __attribute__((target("arch=rv64gc_xtheadba"))); + long foo_th (long a, long b) + { +diff --git a/gcc/testsuite/gcc.target/riscv/target-attr-15.c b/gcc/testsuite/gcc.target/riscv/target-attr-15.c +index 586cc581c86..5120ad7b1d6 100644 +--- a/gcc/testsuite/gcc.target/riscv/target-attr-15.c ++++ b/gcc/testsuite/gcc.target/riscv/target-attr-15.c +@@ -9,7 +9,7 @@ + ** sh1add\s*a0,a1,a0 + ** ... + */ +-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zba1p0" } } */ ++/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zba1p0" } } */ + long foo () __attribute__((target("arch=rv64gc_zba"))); + long foo (long a, long b) + { +@@ -34,7 +34,7 @@ long bar (long a, long b) + ** th.addsl\s*a0,a0,a1,1 + ** ... + */ +-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_xtheadba1p0" } } */ ++/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_xtheadba1p0" } } */ + long foo_th () __attribute__((target("arch=+xtheadba"))); + long foo_th (long a, long b) + { +diff --git a/gcc/testsuite/gcc.target/riscv/target-attr-16.c b/gcc/testsuite/gcc.target/riscv/target-attr-16.c +index 81ef2d72792..42b8cbe0f23 100644 +--- a/gcc/testsuite/gcc.target/riscv/target-attr-16.c ++++ b/gcc/testsuite/gcc.target/riscv/target-attr-16.c +@@ -24,5 +24,5 @@ void bar (void) + { + } + +-/* { dg-final { scan-assembler-times ".option arch, rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zba1p0_zbb1p0" 4 { target { rv32 } } } } */ +-/* { dg-final { scan-assembler-times ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zba1p0_zbb1p0" 4 { target { rv64 } } } } */ ++/* { dg-final { scan-assembler-times ".option arch, rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zba1p0_zbb1p0" 4 { target { rv32 } } } } */ ++/* { dg-final { scan-assembler-times ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zba1p0_zbb1p0" 4 { target { rv64 } } } } */ +-- +2.50.1 + diff --git a/0002-RISC-V-Use-widening-shift-for-scatter-gather-if-appl.patch b/0002-RISC-V-Use-widening-shift-for-scatter-gather-if-appl.patch new file mode 100644 index 0000000..373f44c --- /dev/null +++ b/0002-RISC-V-Use-widening-shift-for-scatter-gather-if-appl.patch @@ -0,0 +1,368 @@ +From 4f04f19ebaaeb37071a10c9550f6bcb113205920 Mon Sep 17 00:00:00 2001 +From: Robin Dapp +Date: Fri, 10 May 2024 13:37:03 +0200 +Subject: [PATCH 02/29] RISC-V: Use widening shift for scatter/gather if + applicable. + +With the zvbb extension we can emit a widening shift for scatter/gather +index preparation in case we need to multiply by 2 and zero extend. + +The patch also adds vwsll to the mode_idx attribute and removes the +mode from shift-count operand of the insn pattern. + +gcc/ChangeLog: + + * config/riscv/riscv-v.cc (expand_gather_scatter): Use vwsll if + applicable. + * config/riscv/vector-crypto.md: Remove mode from vwsll shift + count operator. + * config/riscv/vector.md: Add vwsll to mode iterator. + +gcc/testsuite/ChangeLog: + + * lib/target-supports.exp: Add zvbb. + * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-12-zvbb.c: New test. + +(cherry picked from commit 309ee005aa871286c8daccbce7586f82be347440) +--- + gcc/config/riscv/riscv-v.cc | 42 +++++-- + gcc/config/riscv/vector-crypto.md | 4 +- + gcc/config/riscv/vector.md | 4 +- + .../gather-scatter/gather_load_64-12-zvbb.c | 113 ++++++++++++++++++ + gcc/testsuite/lib/target-supports.exp | 48 +++++++- + 5 files changed, 193 insertions(+), 18 deletions(-) + create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-12-zvbb.c + +diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc +index bb38d8b42c7..4371971507c 100644 +--- a/gcc/config/riscv/riscv-v.cc ++++ b/gcc/config/riscv/riscv-v.cc +@@ -4060,7 +4060,7 @@ expand_gather_scatter (rtx *ops, bool is_load) + { + rtx ptr, vec_offset, vec_reg; + bool zero_extend_p; +- int scale_log2; ++ int shift; + rtx mask = ops[5]; + rtx len = ops[6]; + if (is_load) +@@ -4069,7 +4069,7 @@ expand_gather_scatter (rtx *ops, bool is_load) + ptr = ops[1]; + vec_offset = ops[2]; + zero_extend_p = INTVAL (ops[3]); +- scale_log2 = exact_log2 (INTVAL (ops[4])); ++ shift = exact_log2 (INTVAL (ops[4])); + } + else + { +@@ -4077,7 +4077,7 @@ expand_gather_scatter (rtx *ops, bool is_load) + ptr = ops[0]; + vec_offset = ops[1]; + zero_extend_p = INTVAL (ops[2]); +- scale_log2 = exact_log2 (INTVAL (ops[3])); ++ shift = exact_log2 (INTVAL (ops[3])); + } + + machine_mode vec_mode = GET_MODE (vec_reg); +@@ -4087,9 +4087,12 @@ expand_gather_scatter (rtx *ops, bool is_load) + poly_int64 nunits = GET_MODE_NUNITS (vec_mode); + bool is_vlmax = is_vlmax_len_p (vec_mode, len); + ++ bool use_widening_shift = false; ++ + /* Extend the offset element to address width. */ + if (inner_offsize < BITS_PER_WORD) + { ++ use_widening_shift = TARGET_ZVBB && zero_extend_p && shift == 1; + /* 7.2. Vector Load/Store Addressing Modes. + If the vector offset elements are narrower than XLEN, they are + zero-extended to XLEN before adding to the ptr effective address. If +@@ -4098,8 +4101,8 @@ expand_gather_scatter (rtx *ops, bool is_load) + raise an illegal instruction exception if the EEW is not supported for + offset elements. + +- RVV spec only refers to the scale_log == 0 case. */ +- if (!zero_extend_p || scale_log2 != 0) ++ RVV spec only refers to the shift == 0 case. */ ++ if (!zero_extend_p || shift) + { + if (zero_extend_p) + inner_idx_mode +@@ -4108,19 +4111,32 @@ expand_gather_scatter (rtx *ops, bool is_load) + inner_idx_mode = int_mode_for_size (BITS_PER_WORD, 0).require (); + machine_mode new_idx_mode + = get_vector_mode (inner_idx_mode, nunits).require (); +- rtx tmp = gen_reg_rtx (new_idx_mode); +- emit_insn (gen_extend_insn (tmp, vec_offset, new_idx_mode, idx_mode, +- zero_extend_p ? true : false)); +- vec_offset = tmp; ++ if (!use_widening_shift) ++ { ++ rtx tmp = gen_reg_rtx (new_idx_mode); ++ emit_insn (gen_extend_insn (tmp, vec_offset, new_idx_mode, idx_mode, ++ zero_extend_p ? true : false)); ++ vec_offset = tmp; ++ } + idx_mode = new_idx_mode; + } + } + +- if (scale_log2 != 0) ++ if (shift) + { +- rtx tmp = expand_binop (idx_mode, ashl_optab, vec_offset, +- gen_int_mode (scale_log2, Pmode), NULL_RTX, 0, +- OPTAB_DIRECT); ++ rtx tmp; ++ if (!use_widening_shift) ++ tmp = expand_binop (idx_mode, ashl_optab, vec_offset, ++ gen_int_mode (shift, Pmode), NULL_RTX, 0, ++ OPTAB_DIRECT); ++ else ++ { ++ tmp = gen_reg_rtx (idx_mode); ++ insn_code icode = code_for_pred_vwsll_scalar (idx_mode); ++ rtx ops[] = {tmp, vec_offset, const1_rtx}; ++ emit_vlmax_insn (icode, BINARY_OP, ops); ++ } ++ + vec_offset = tmp; + } + +diff --git a/gcc/config/riscv/vector-crypto.md b/gcc/config/riscv/vector-crypto.md +index e474ddf5da7..f86adafc84e 100755 +--- a/gcc/config/riscv/vector-crypto.md ++++ b/gcc/config/riscv/vector-crypto.md +@@ -295,7 +295,7 @@ + (ashift:VWEXTI + (zero_extend:VWEXTI + (match_operand: 3 "register_operand" "vr")) +- (match_operand: 4 "register_operand" "vr")) ++ (match_operand: 4 "vector_shift_operand" "vrvk")) + (match_operand:VWEXTI 2 "vector_merge_operand" "0vu")))] + "TARGET_ZVBB" + "vwsll.vv\t%0,%3,%4%p1" +@@ -316,7 +316,7 @@ + (ashift:VWEXTI + (zero_extend:VWEXTI + (match_operand: 3 "register_operand" " vr, vr")) +- (match_operand: 4 "pmode_reg_or_uimm5_operand" " rK, rK")) ++ (match_operand 4 "pmode_reg_or_uimm5_operand" " rK, rK")) + (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0")))] + "TARGET_ZVBB" + "vwsll.v%o4\t%0,%3,%4%p1" +diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md +index 80d810fbca7..1c655282e12 100644 +--- a/gcc/config/riscv/vector.md ++++ b/gcc/config/riscv/vector.md +@@ -751,10 +751,10 @@ + (const_int 1) + + (eq_attr "type" "vssegte,vmpop,vmffs") +- (const_int 2) ++ (const_int 2) + + (eq_attr "type" "vstux,vstox,vssegts,vssegtux,vssegtox,vfcvtftoi,vfwcvtitof,vfwcvtftoi, +- vfwcvtftof,vmsfs,vired,viwred,vfredu,vfredo,vfwredu,vfwredo") ++ vfwcvtftof,vmsfs,vired,viwred,vfredu,vfredo,vfwredu,vfwredo,vwsll") + (const_int 3) + + (eq_attr "type" "viwalu,viwmul,viwmuladd,vfwalu,vfwmul,vfwmuladd") +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-12-zvbb.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-12-zvbb.c +new file mode 100644 +index 00000000000..11a4031f47b +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-12-zvbb.c +@@ -0,0 +1,113 @@ ++/* { dg-do compile } */ ++/* { dg-add-options "riscv_v" } */ ++/* { dg-add-options "riscv_zvbb" } */ ++/* { dg-additional-options "-fno-vect-cost-model -fdump-tree-vect-details -mrvv-max-lmul=m4" } */ ++ ++#include ++ ++#define TEST_LOOP(DATA_TYPE, INDEX_TYPE) \ ++ void __attribute__ ((noinline, noclone)) \ ++ f_##DATA_TYPE##_##INDEX_TYPE (DATA_TYPE *restrict y, DATA_TYPE *restrict x, \ ++ INDEX_TYPE *restrict index) \ ++ { \ ++ for (int i = 0; i < 100; ++i) \ ++ { \ ++ y[i * 2] = x[index[i * 2]] + 1; \ ++ y[i * 2 + 1] = x[index[i * 2 + 1]] + 2; \ ++ } \ ++ } ++ ++TEST_LOOP (int8_t, int8_t) ++TEST_LOOP (uint8_t, int8_t) ++TEST_LOOP (int16_t, int8_t) ++TEST_LOOP (uint16_t, int8_t) ++TEST_LOOP (int32_t, int8_t) ++TEST_LOOP (uint32_t, int8_t) ++TEST_LOOP (int64_t, int8_t) ++TEST_LOOP (uint64_t, int8_t) ++TEST_LOOP (_Float16, int8_t) ++TEST_LOOP (float, int8_t) ++TEST_LOOP (double, int8_t) ++TEST_LOOP (int8_t, int16_t) ++TEST_LOOP (uint8_t, int16_t) ++TEST_LOOP (int16_t, int16_t) ++TEST_LOOP (uint16_t, int16_t) ++TEST_LOOP (int32_t, int16_t) ++TEST_LOOP (uint32_t, int16_t) ++TEST_LOOP (int64_t, int16_t) ++TEST_LOOP (uint64_t, int16_t) ++TEST_LOOP (_Float16, int16_t) ++TEST_LOOP (float, int16_t) ++TEST_LOOP (double, int16_t) ++TEST_LOOP (int8_t, int32_t) ++TEST_LOOP (uint8_t, int32_t) ++TEST_LOOP (int16_t, int32_t) ++TEST_LOOP (uint16_t, int32_t) ++TEST_LOOP (int32_t, int32_t) ++TEST_LOOP (uint32_t, int32_t) ++TEST_LOOP (int64_t, int32_t) ++TEST_LOOP (uint64_t, int32_t) ++TEST_LOOP (_Float16, int32_t) ++TEST_LOOP (float, int32_t) ++TEST_LOOP (double, int32_t) ++TEST_LOOP (int8_t, int64_t) ++TEST_LOOP (uint8_t, int64_t) ++TEST_LOOP (int16_t, int64_t) ++TEST_LOOP (uint16_t, int64_t) ++TEST_LOOP (int32_t, int64_t) ++TEST_LOOP (uint32_t, int64_t) ++TEST_LOOP (int64_t, int64_t) ++TEST_LOOP (uint64_t, int64_t) ++TEST_LOOP (_Float16, int64_t) ++TEST_LOOP (float, int64_t) ++TEST_LOOP (double, int64_t) ++TEST_LOOP (int8_t, uint8_t) ++TEST_LOOP (uint8_t, uint8_t) ++TEST_LOOP (int16_t, uint8_t) ++TEST_LOOP (uint16_t, uint8_t) ++TEST_LOOP (int32_t, uint8_t) ++TEST_LOOP (uint32_t, uint8_t) ++TEST_LOOP (int64_t, uint8_t) ++TEST_LOOP (uint64_t, uint8_t) ++TEST_LOOP (_Float16, uint8_t) ++TEST_LOOP (float, uint8_t) ++TEST_LOOP (double, uint8_t) ++TEST_LOOP (int8_t, uint16_t) ++TEST_LOOP (uint8_t, uint16_t) ++TEST_LOOP (int16_t, uint16_t) ++TEST_LOOP (uint16_t, uint16_t) ++TEST_LOOP (int32_t, uint16_t) ++TEST_LOOP (uint32_t, uint16_t) ++TEST_LOOP (int64_t, uint16_t) ++TEST_LOOP (uint64_t, uint16_t) ++TEST_LOOP (_Float16, uint16_t) ++TEST_LOOP (float, uint16_t) ++TEST_LOOP (double, uint16_t) ++TEST_LOOP (int8_t, uint32_t) ++TEST_LOOP (uint8_t, uint32_t) ++TEST_LOOP (int16_t, uint32_t) ++TEST_LOOP (uint16_t, uint32_t) ++TEST_LOOP (int32_t, uint32_t) ++TEST_LOOP (uint32_t, uint32_t) ++TEST_LOOP (int64_t, uint32_t) ++TEST_LOOP (uint64_t, uint32_t) ++TEST_LOOP (_Float16, uint32_t) ++TEST_LOOP (float, uint32_t) ++TEST_LOOP (double, uint32_t) ++TEST_LOOP (int8_t, uint64_t) ++TEST_LOOP (uint8_t, uint64_t) ++TEST_LOOP (int16_t, uint64_t) ++TEST_LOOP (uint16_t, uint64_t) ++TEST_LOOP (int32_t, uint64_t) ++TEST_LOOP (uint32_t, uint64_t) ++TEST_LOOP (int64_t, uint64_t) ++TEST_LOOP (uint64_t, uint64_t) ++TEST_LOOP (_Float16, uint64_t) ++TEST_LOOP (float, uint64_t) ++TEST_LOOP (double, uint64_t) ++ ++/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 88 "vect" } } */ ++/* { dg-final { scan-tree-dump " \.MASK_LEN_GATHER_LOAD" "vect" } } */ ++/* { dg-final { scan-tree-dump-not " \.GATHER_LOAD" "vect" } } */ ++/* { dg-final { scan-tree-dump-not " \.MASK_GATHER_LOAD" "vect" } } */ ++/* { dg-final { scan-assembler "vwsll.vi" } } */ +diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp +index d176c024f6d..4cada7f94fb 100644 +--- a/gcc/testsuite/lib/target-supports.exp ++++ b/gcc/testsuite/lib/target-supports.exp +@@ -2016,6 +2016,17 @@ proc check_effective_target_riscv_zbb { } { + }] + } + ++# Return 1 if the target arch supports the Zbb extension, 0 otherwise. ++# Cache the result. ++ ++proc check_effective_target_riscv_zvbb { } { ++ return [check_no_compiler_messages riscv_ext_zvbb assembly { ++ #ifndef __riscv_zvbb ++ #error "Not __riscv_zvbb" ++ #endif ++ }] ++} ++ + # Return 1 if the target arch supports the XTheadVector extension, 0 otherwise. + # Cache the result. + +@@ -2104,10 +2115,33 @@ proc check_effective_target_riscv_zvfh_ok { } { + return 0 + } + ++proc check_effective_target_riscv_zvbb_ok { } { ++ # If the target already supports v without any added options, ++ # we may assume we can execute just fine. ++ if { [check_effective_target_riscv_zvbb] } { ++ return 1 ++ } ++ ++ # check if we can execute vector insns with the given hardware or ++ # simulator ++ set gcc_march [regsub {[[:alnum:]]*} [riscv_get_arch] &zvbb] ++ if { [check_runtime ${gcc_march}_zvbb_exec { ++ int main() ++ { ++ asm ("vsetivli zero,8,e16,m1,ta,ma"); ++ asm ("vwsll.vi v8,v16,2" : : : "v8"); ++ return 0; ++ } } "-march=${gcc_march}"] } { ++ return 1 ++ } ++ ++ return 0 ++} ++ + proc riscv_get_arch { } { + set gcc_march "" + # ??? do we neeed to add more extensions to the list below? +- foreach ext { i m a f d q c v zicsr zifencei zfh zba zbb zbc zbs zvfh ztso } { ++ foreach ext { i m a f d q c v zicsr zifencei zfh zba zbb zbc zbs zvbb zvfh ztso } { + if { [check_no_compiler_messages riscv_ext_$ext assembly [string map [list DEF __riscv_$ext] { + #ifndef DEF + #error "Not DEF" +@@ -2202,6 +2236,18 @@ proc add_options_for_riscv_zvfh { flags } { + return "$flags -march=[riscv_get_arch]_zvfh" + } + ++proc add_options_for_riscv_zvbb { flags } { ++ if { [lsearch $flags -march=*] >= 0 } { ++ # If there are multiple -march flags, we have to adjust all of them. ++ set flags [regsub -all -- {(?:^|[[:space:]])-march=[[:alnum:]_.]*} $flags &_zvbb ] ++ return [regsub -all -- {((?:^|[[:space:]])-march=[[:alnum:]_.]*_zvbb[[:alnum:]_.]*)_zvbb} $flags \\1 ] ++ } ++ if { [check_effective_target_riscv_zvbb] } { ++ return "$flags" ++ } ++ return "$flags -march=[riscv_get_arch]_zvbb" ++} ++ + # Return 1 if the target OS supports running SSE executables, 0 + # otherwise. Cache the result. + +-- +2.50.1 + diff --git a/0003-RISC-V-Add-Zalrsc-and-Zaamo-testsuite-support.patch b/0003-RISC-V-Add-Zalrsc-and-Zaamo-testsuite-support.patch new file mode 100644 index 0000000..74e2689 --- /dev/null +++ b/0003-RISC-V-Add-Zalrsc-and-Zaamo-testsuite-support.patch @@ -0,0 +1,622 @@ +From 735049aa7e2cba842fff43e99b9716bc17c0f39d Mon Sep 17 00:00:00 2001 +From: Patrick O'Neill +Date: Mon, 10 Jun 2024 14:12:40 -0700 +Subject: [PATCH 03/29] RISC-V: Add Zalrsc and Zaamo testsuite support + +Convert testsuite infrastructure to use Zalrsc and Zaamo rather than A. + +gcc/ChangeLog: + + * doc/sourcebuild.texi: Add docs for atomic extension testsuite infra. + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/amo-table-a-6-amo-add-1.c: Use Zaamo rather than A. + * gcc.target/riscv/amo-table-a-6-amo-add-2.c: Ditto. + * gcc.target/riscv/amo-table-a-6-amo-add-3.c: Ditto. + * gcc.target/riscv/amo-table-a-6-amo-add-4.c: Ditto. + * gcc.target/riscv/amo-table-a-6-amo-add-5.c: Ditto. + * gcc.target/riscv/amo-table-a-6-compare-exchange-1.c: Use Zalrsc rather + than A. + * gcc.target/riscv/amo-table-a-6-compare-exchange-2.c: Ditto. + * gcc.target/riscv/amo-table-a-6-compare-exchange-3.c: Ditto. + * gcc.target/riscv/amo-table-a-6-compare-exchange-4.c: Ditto. + * gcc.target/riscv/amo-table-a-6-compare-exchange-5.c: Ditto. + * gcc.target/riscv/amo-table-a-6-compare-exchange-6.c: Ditto. + * gcc.target/riscv/amo-table-a-6-compare-exchange-7.c: Ditto. + * gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c: Use Zaamo rather + than A. + * gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c: Ditto. + * gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c: Ditto. + * gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c: Ditto. + * gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c: Ditto. + * gcc.target/riscv/amo-table-ztso-amo-add-1.c: Add Zaamo option. + * gcc.target/riscv/amo-table-ztso-amo-add-2.c: Ditto. + * gcc.target/riscv/amo-table-ztso-amo-add-3.c: Ditto. + * gcc.target/riscv/amo-table-ztso-amo-add-4.c: Ditto. + * gcc.target/riscv/amo-table-ztso-amo-add-5.c: Ditto. + * gcc.target/riscv/amo-table-ztso-compare-exchange-1.c: Use Zalrsc rather + than A. + * gcc.target/riscv/amo-table-ztso-compare-exchange-2.c: Ditto. + * gcc.target/riscv/amo-table-ztso-compare-exchange-3.c: Ditto. + * gcc.target/riscv/amo-table-ztso-compare-exchange-4.c: Ditto. + * gcc.target/riscv/amo-table-ztso-compare-exchange-5.c: Ditto. + * gcc.target/riscv/amo-table-ztso-compare-exchange-6.c: Ditto. + * gcc.target/riscv/amo-table-ztso-compare-exchange-7.c: Ditto. + * gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c: Ditto. + * gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c: Ditto. + * gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c: Ditto. + * gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c: Ditto. + * gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c: Ditto. + * lib/target-supports.exp: Add testsuite infrastructure support for + Zaamo and Zalrsc. + +Signed-off-by: Patrick O'Neill +(cherry picked from commit 0fea902b1b5311c8b34ae8e789f1733bd8429904) +--- + gcc/doc/sourcebuild.texi | 16 ++++++- + .../riscv/amo-table-a-6-amo-add-1.c | 2 +- + .../riscv/amo-table-a-6-amo-add-2.c | 2 +- + .../riscv/amo-table-a-6-amo-add-3.c | 2 +- + .../riscv/amo-table-a-6-amo-add-4.c | 2 +- + .../riscv/amo-table-a-6-amo-add-5.c | 2 +- + .../riscv/amo-table-a-6-compare-exchange-1.c | 2 +- + .../riscv/amo-table-a-6-compare-exchange-2.c | 2 +- + .../riscv/amo-table-a-6-compare-exchange-3.c | 2 +- + .../riscv/amo-table-a-6-compare-exchange-4.c | 2 +- + .../riscv/amo-table-a-6-compare-exchange-5.c | 2 +- + .../riscv/amo-table-a-6-compare-exchange-6.c | 2 +- + .../riscv/amo-table-a-6-compare-exchange-7.c | 2 +- + .../riscv/amo-table-a-6-subword-amo-add-1.c | 2 +- + .../riscv/amo-table-a-6-subword-amo-add-2.c | 2 +- + .../riscv/amo-table-a-6-subword-amo-add-3.c | 2 +- + .../riscv/amo-table-a-6-subword-amo-add-4.c | 2 +- + .../riscv/amo-table-a-6-subword-amo-add-5.c | 2 +- + .../riscv/amo-table-ztso-amo-add-1.c | 2 +- + .../riscv/amo-table-ztso-amo-add-2.c | 2 +- + .../riscv/amo-table-ztso-amo-add-3.c | 2 +- + .../riscv/amo-table-ztso-amo-add-4.c | 2 +- + .../riscv/amo-table-ztso-amo-add-5.c | 2 +- + .../riscv/amo-table-ztso-compare-exchange-1.c | 2 +- + .../riscv/amo-table-ztso-compare-exchange-2.c | 2 +- + .../riscv/amo-table-ztso-compare-exchange-3.c | 2 +- + .../riscv/amo-table-ztso-compare-exchange-4.c | 2 +- + .../riscv/amo-table-ztso-compare-exchange-5.c | 2 +- + .../riscv/amo-table-ztso-compare-exchange-6.c | 2 +- + .../riscv/amo-table-ztso-compare-exchange-7.c | 2 +- + .../riscv/amo-table-ztso-subword-amo-add-1.c | 2 +- + .../riscv/amo-table-ztso-subword-amo-add-2.c | 2 +- + .../riscv/amo-table-ztso-subword-amo-add-3.c | 2 +- + .../riscv/amo-table-ztso-subword-amo-add-4.c | 2 +- + .../riscv/amo-table-ztso-subword-amo-add-5.c | 2 +- + gcc/testsuite/lib/target-supports.exp | 48 ++++++++++++++++++- + 36 files changed, 95 insertions(+), 37 deletions(-) + +diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi +index c8130dc1ba9..f1f723b5d70 100644 +--- a/gcc/doc/sourcebuild.texi ++++ b/gcc/doc/sourcebuild.texi +@@ -2507,8 +2507,17 @@ Test system has an integer register width of 32 bits. + @item rv64 + Test system has an integer register width of 64 bits. + +-@item cv_bi +-Test system has support for the CORE-V BI extension. ++@item riscv_a ++Test target architecture has support for the A extension. ++ ++@item riscv_zaamo ++Test target architecture has support for the zaamo extension. ++ ++@item riscv_zlrsc ++Test target architecture has support for the zalrsc extension. ++ ++@item riscv_ztso ++Test target architecture has support for the ztso extension. + + @end table + +@@ -2528,6 +2537,9 @@ Test system has support for the CORE-V ELW extension. + @item cv_simd + Test system has support for the CORE-V SIMD extension. + ++@item cv_bi ++Test system has support for the CORE-V BI extension. ++ + @end table + + @subsubsection Other hardware attributes +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c +index 8ab1a02b40c..9c2ba39789a 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c +@@ -1,7 +1,7 @@ + /* { dg-do compile } */ + /* Verify that atomic op mappings match Table A.6's recommended mapping. */ + /* { dg-options "-O3" } */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zaamo } */ + /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + /* { dg-final { check-function-bodies "**" "" } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c +index a5a841abdcd..b7682a5bab4 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c +@@ -1,7 +1,7 @@ + /* { dg-do compile } */ + /* Verify that atomic op mappings match Table A.6's recommended mapping. */ + /* { dg-options "-O3" } */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zaamo } */ + /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + /* { dg-final { check-function-bodies "**" "" } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c +index f523821b658..c8776872d91 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c +@@ -1,7 +1,7 @@ + /* { dg-do compile } */ + /* Verify that atomic op mappings match Table A.6's recommended mapping. */ + /* { dg-options "-O3" } */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zaamo } */ + /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + /* { dg-final { check-function-bodies "**" "" } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c +index f1561b52c89..b37c4c3f242 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c +@@ -1,7 +1,7 @@ + /* { dg-do compile } */ + /* Verify that atomic op mappings match Table A.6's recommended mapping. */ + /* { dg-options "-O3" } */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zaamo } */ + /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + /* { dg-final { check-function-bodies "**" "" } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c +index 81f876ee625..8d45ca7a347 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c +@@ -1,7 +1,7 @@ + /* { dg-do compile } */ + /* Verify that atomic op mappings match Table A.6's recommended mapping. */ + /* { dg-options "-O3" } */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zaamo } */ + /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + /* { dg-final { check-function-bodies "**" "" } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c +index dc445f0316a..4917cd6bd2b 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c +@@ -1,6 +1,6 @@ + /* { dg-do compile } */ + /* Verify that compare exchange mappings match Table A.6's recommended mapping. */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zalrsc } */ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c +index 7e8ab7bb5ef..121936507e3 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c +@@ -1,6 +1,6 @@ + /* { dg-do compile } */ + /* Verify that compare exchange mappings match Table A.6's recommended mapping. */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zalrsc } */ + /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c +index 4cb6c422213..649c7d2b1fe 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c +@@ -1,6 +1,6 @@ + /* { dg-do compile } */ + /* Verify that compare exchange mappings match Table A.6's recommended mapping. */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zalrsc } */ + /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c +index da81c34b92c..5f7fdeb1b21 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c +@@ -1,6 +1,6 @@ + /* { dg-do compile } */ + /* Verify that compare exchange mappings match Table A.6's recommended mapping. */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zalrsc } */ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c +index bb16ccc754c..f4bd7d6d842 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c +@@ -1,6 +1,6 @@ + /* { dg-do compile } */ + /* Verify that compare exchange mappings match Table A.6's recommended mapping. */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zalrsc } */ + /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-6.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-6.c +index 0f3f0b49d95..154764425ae 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-6.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-6.c +@@ -1,6 +1,6 @@ + /* { dg-do compile } */ + /* Verify that compare exchange mappings match Table A.6's recommended mapping. */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zalrsc } */ + /* Mixed mappings need to be unioned. */ + /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-7.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-7.c +index d51de56cc78..16712540919 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-7.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-7.c +@@ -1,6 +1,6 @@ + /* { dg-do compile } */ + /* Verify that compare exchange mappings match Table A.6's recommended mapping. */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zalrsc } */ + /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c +index ca8aa715bed..4174fdee352 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c +@@ -1,6 +1,6 @@ + /* { dg-do compile } */ + /* Verify that subword atomic op mappings match Table A.6's recommended mapping. */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zalrsc } */ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c +index e64759a54ae..4c06c90b558 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c +@@ -1,6 +1,6 @@ + /* { dg-do compile } */ + /* Verify that subword atomic op mappings match Table A.6's recommended mapping. */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zalrsc } */ + /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c +index 9d3f69264fa..7e791c901b6 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c +@@ -1,6 +1,6 @@ + /* { dg-do compile } */ + /* Verify that subword atomic op mappings match Table A.6's recommended mapping. */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zalrsc } */ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c +index ba32ed59c2f..76f3be27110 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c +@@ -1,6 +1,6 @@ + /* { dg-do compile } */ + /* Verify that subword atomic op mappings match Table A.6's recommended mapping. */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zalrsc } */ + /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c +index f9be8c5e628..8dbfa9c4fc8 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c +@@ -1,6 +1,6 @@ + /* { dg-do compile } */ + /* Verify that subword atomic op mappings match Table A.6's recommended mapping. */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zalrsc } */ + /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ + +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-1.c +index a9edc33ff39..82169390925 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-1.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-1.c +@@ -1,7 +1,7 @@ + /* { dg-do compile } */ + /* Verify that atomic op mappings match the Ztso suggested mapping. */ + /* { dg-options "-O3" } */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zaamo } */ + /* { dg-add-options riscv_ztso } */ + /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + /* { dg-final { check-function-bodies "**" "" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-2.c +index ad843402bcc..a238c6f4403 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-2.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-2.c +@@ -1,7 +1,7 @@ + /* { dg-do compile } */ + /* Verify that atomic op mappings the Ztso suggested mapping. */ + /* { dg-options "-O3" } */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zaamo } */ + /* { dg-add-options riscv_ztso } */ + /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + /* { dg-final { check-function-bodies "**" "" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-3.c +index bdae5bb83a6..c97bf467c63 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-3.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-3.c +@@ -1,7 +1,7 @@ + /* { dg-do compile } */ + /* Verify that atomic op mappings match the Ztso suggested mapping. */ + /* { dg-options "-O3" } */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zaamo } */ + /* { dg-add-options riscv_ztso } */ + /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + /* { dg-final { check-function-bodies "**" "" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-4.c +index 815a72f1e56..14e632ba2f2 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-4.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-4.c +@@ -1,7 +1,7 @@ + /* { dg-do compile } */ + /* Verify that atomic op mappings match the Ztso suggested mapping. */ + /* { dg-options "-O3" } */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zaamo } */ + /* { dg-add-options riscv_ztso } */ + /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + /* { dg-final { check-function-bodies "**" "" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-5.c +index eda6f01096e..74d8df99ddc 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-5.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-5.c +@@ -1,7 +1,7 @@ + /* { dg-do compile } */ + /* Verify that atomic op mappings match the Ztso suggested mapping. */ + /* { dg-options "-O3" } */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zaamo } */ + /* { dg-add-options riscv_ztso } */ + /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + /* { dg-final { check-function-bodies "**" "" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-1.c +index b6315c45e85..46a9f0c918a 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-1.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-1.c +@@ -1,6 +1,6 @@ + /* { dg-do compile } */ + /* Verify that compare exchange mappings match the Ztso suggested mapping. */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zalrsc } */ + /* { dg-add-options riscv_ztso } */ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-2.c +index e487184f6cf..20e325f2e7c 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-2.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-2.c +@@ -1,6 +1,6 @@ + /* { dg-do compile } */ + /* Verify that compare exchange mappings match the Ztso suggested mapping. */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zalrsc } */ + /* { dg-add-options riscv_ztso } */ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-3.c +index e9c925f0923..0a443b461f3 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-3.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-3.c +@@ -1,6 +1,6 @@ + /* { dg-do compile } */ + /* Verify that compare exchange mappings match the Ztso suggested mapping. */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zalrsc } */ + /* { dg-add-options riscv_ztso } */ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-4.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-4.c +index 6b454559633..35e01cdc8be 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-4.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-4.c +@@ -1,6 +1,6 @@ + /* { dg-do compile } */ + /* Verify that compare exchange mappings match the Ztso suggested mapping. */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zalrsc } */ + /* { dg-add-options riscv_ztso } */ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-5.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-5.c +index 02c9f0ada77..cd884931bdf 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-5.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-5.c +@@ -1,6 +1,6 @@ + /* { dg-do compile } */ + /* Verify that compare exchange mappings match the Ztso suggested mapping. */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zalrsc } */ + /* { dg-add-options riscv_ztso } */ + /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-6.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-6.c +index 75abd5d3dfb..7da3b1dce48 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-6.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-6.c +@@ -1,6 +1,6 @@ + /* { dg-do compile } */ + /* Verify that compare exchange mappings match the Ztso suggested mapping. */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zalrsc } */ + /* { dg-add-options riscv_ztso } */ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-7.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-7.c +index 33928c0eac4..53f6e6ace0b 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-7.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-7.c +@@ -1,6 +1,6 @@ + /* { dg-do compile } */ + /* Verify that compare exchange mappings match the Ztso suggested mapping. */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zalrsc } */ + /* { dg-add-options riscv_ztso } */ + /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c +index 2a40d6b1376..5c0a8b8f6e9 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c +@@ -1,6 +1,6 @@ + /* { dg-do compile } */ + /* Verify that subword atomic op mappings match the Ztso suggested mapping. */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zalrsc } */ + /* { dg-add-options riscv_ztso } */ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c +index c79380f2611..551078186ec 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c +@@ -1,6 +1,6 @@ + /* { dg-do compile } */ + /* Verify that subword atomic op mappings match the Ztso suggested mapping. */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zalrsc } */ + /* { dg-add-options riscv_ztso } */ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c +index d1a94eccfa8..5f0f7870721 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c +@@ -1,6 +1,6 @@ + /* { dg-do compile } */ + /* Verify that subword atomic op mappings match the Ztso suggested mapping. */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zalrsc } */ + /* { dg-add-options riscv_ztso } */ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c +index 3d65bc2f64a..24f4f02dcea 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c +@@ -1,6 +1,6 @@ + /* { dg-do compile } */ + /* Verify that subword atomic op mappings match the Ztso suggested mapping. */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zalrsc } */ + /* { dg-add-options riscv_ztso } */ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c +index 10354387a13..405e498fb40 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c ++++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c +@@ -1,6 +1,6 @@ + /* { dg-do compile } */ + /* Verify that subword atomic op mappings match the Ztso suggested mapping. */ +-/* { dg-add-options riscv_a } */ ++/* { dg-add-options riscv_zalrsc } */ + /* { dg-add-options riscv_ztso } */ + /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ +diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp +index 4cada7f94fb..d293c0bb372 100644 +--- a/gcc/testsuite/lib/target-supports.exp ++++ b/gcc/testsuite/lib/target-supports.exp +@@ -1910,6 +1910,28 @@ proc check_effective_target_riscv_a { } { + }] + } + ++# Return 1 if the target arch supports the atomic LRSC extension, 0 otherwise. ++# Cache the result. ++ ++proc check_effective_target_riscv_zalrsc { } { ++ return [check_no_compiler_messages riscv_ext_zalrsc assembly { ++ #ifndef __riscv_zalrsc ++ #error "Not __riscv_zalrsc" ++ #endif ++ }] ++} ++ ++# Return 1 if the target arch supports the atomic AMO extension, 0 otherwise. ++# Cache the result. ++ ++proc check_effective_target_riscv_zaamo { } { ++ return [check_no_compiler_messages riscv_ext_zaamo assembly { ++ #ifndef __riscv_zaamo ++ #error "Not __riscv_zaamo" ++ #endif ++ }] ++} ++ + # Return 1 if the target arch supports the double precision floating point + # extension, 0 otherwise. Cache the result. + +@@ -2141,7 +2163,7 @@ proc check_effective_target_riscv_zvbb_ok { } { + proc riscv_get_arch { } { + set gcc_march "" + # ??? do we neeed to add more extensions to the list below? +- foreach ext { i m a f d q c v zicsr zifencei zfh zba zbb zbc zbs zvbb zvfh ztso } { ++ foreach ext { i m a f d q c v zicsr zifencei zfh zba zbb zbc zbs zvbb zvfh ztso zaamo zalrsc } { + if { [check_no_compiler_messages riscv_ext_$ext assembly [string map [list DEF __riscv_$ext] { + #ifndef DEF + #error "Not DEF" +@@ -2200,6 +2222,30 @@ proc add_options_for_riscv_v { flags } { + return "$flags -march=[regsub {[[:alnum:]]*} [riscv_get_arch] &v]" + } + ++proc add_options_for_riscv_zaamo { flags } { ++ if { [lsearch $flags -march=*] >= 0 } { ++ # If there are multiple -march flags, we have to adjust all of them. ++ set flags [regsub -all -- {(?:^|[[:space:]])-march=[[:alnum:]_.]*} $flags &_zaamo ] ++ return [regsub -all -- {((?:^|[[:space:]])-march=[[:alnum:]_.]*_zaamo[[:alnum:]_.]*)_zaamo} $flags \\1 ] ++ } ++ if { [check_effective_target_riscv_zaamo] } { ++ return "$flags" ++ } ++ return "$flags -march=[riscv_get_arch]_zaamo" ++} ++ ++proc add_options_for_riscv_zalrsc { flags } { ++ if { [lsearch $flags -march=*] >= 0 } { ++ # If there are multiple -march flags, we have to adjust all of them. ++ set flags [regsub -all -- {(?:^|[[:space:]])-march=[[:alnum:]_.]*} $flags &_zalrsc ] ++ return [regsub -all -- {((?:^|[[:space:]])-march=[[:alnum:]_.]*_zalrsc[[:alnum:]_.]*)_zalrsc} $flags \\1 ] ++ } ++ if { [check_effective_target_riscv_zalrsc] } { ++ return "$flags" ++ } ++ return "$flags -march=[riscv_get_arch]_zalrsc" ++} ++ + proc add_options_for_riscv_zfh { flags } { + if { [lsearch $flags -march=*] >= 0 } { + # If there are multiple -march flags, we have to adjust all of them. +-- +2.50.1 + diff --git a/0004-RISC-V-Add-Zalrsc-amo-op-patterns.patch b/0004-RISC-V-Add-Zalrsc-amo-op-patterns.patch new file mode 100644 index 0000000..e072405 --- /dev/null +++ b/0004-RISC-V-Add-Zalrsc-amo-op-patterns.patch @@ -0,0 +1,375 @@ +From 9b457e71ef17c8cdcfcedf380ceca21c67b71eba Mon Sep 17 00:00:00 2001 +From: Patrick O'Neill +Date: Wed, 7 Feb 2024 16:30:30 -0800 +Subject: [PATCH 04/29] RISC-V: Add Zalrsc amo-op patterns + +All amo patterns can be represented with lrsc sequences. +Add these patterns as a fallback when Zaamo is not enabled. + +gcc/ChangeLog: + + * config/riscv/sync.md (atomic_): New expand pattern. + (amo_atomic_): Rename amo pattern. + (atomic_fetch_): New lrsc sequence pattern. + (lrsc_atomic_): New expand pattern. + (amo_atomic_fetch_): Rename amo pattern. + (lrsc_atomic_fetch_): New lrsc sequence pattern. + (atomic_exchange): New expand pattern. + (amo_atomic_exchange): Rename amo pattern. + (lrsc_atomic_exchange): New lrsc sequence pattern. + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/amo-zaamo-preferred-over-zalrsc.c: New test. + * gcc.target/riscv/amo-zalrsc-amo-add-1.c: New test. + * gcc.target/riscv/amo-zalrsc-amo-add-2.c: New test. + * gcc.target/riscv/amo-zalrsc-amo-add-3.c: New test. + * gcc.target/riscv/amo-zalrsc-amo-add-4.c: New test. + * gcc.target/riscv/amo-zalrsc-amo-add-5.c: New test. + +Signed-off-by: Patrick O'Neill +(cherry picked from commit 1588983be6112561c805a50eb7a3c585865beffa) +--- + gcc/config/riscv/sync.md | 124 +++++++++++++++++- + .../riscv/amo-zaamo-preferred-over-zalrsc.c | 17 +++ + .../gcc.target/riscv/amo-zalrsc-amo-add-1.c | 19 +++ + .../gcc.target/riscv/amo-zalrsc-amo-add-2.c | 19 +++ + .../gcc.target/riscv/amo-zalrsc-amo-add-3.c | 19 +++ + .../gcc.target/riscv/amo-zalrsc-amo-add-4.c | 19 +++ + .../gcc.target/riscv/amo-zalrsc-amo-add-5.c | 19 +++ + 7 files changed, 231 insertions(+), 5 deletions(-) + create mode 100644 gcc/testsuite/gcc.target/riscv/amo-zaamo-preferred-over-zalrsc.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-1.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-2.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-3.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-4.c + create mode 100644 gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-5.c + +diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md +index f44c69d34f7..ee45040cfb6 100644 +--- a/gcc/config/riscv/sync.md ++++ b/gcc/config/riscv/sync.md +@@ -86,7 +86,24 @@ + DONE; + }) + +-(define_insn "atomic_" ++;; AMO ops ++ ++(define_expand "atomic_" ++ [(any_atomic:GPR (match_operand:GPR 0 "memory_operand") ;; mem location ++ (match_operand:GPR 1 "reg_or_0_operand")) ;; value for op ++ (match_operand:SI 2 "const_int_operand")] ;; model ++ "TARGET_ZAAMO || TARGET_ZALRSC" ++{ ++ if (TARGET_ZAAMO) ++ emit_insn (gen_amo_atomic_ (operands[0], operands[1], ++ operands[2])); ++ else ++ emit_insn (gen_lrsc_atomic_ (operands[0], operands[1], ++ operands[2])); ++ DONE; ++}) ++ ++(define_insn "amo_atomic_" + [(set (match_operand:GPR 0 "memory_operand" "+A") + (unspec_volatile:GPR + [(any_atomic:GPR (match_dup 0) +@@ -98,7 +115,44 @@ + [(set_attr "type" "atomic") + (set (attr "length") (const_int 4))]) + +-(define_insn "atomic_fetch_" ++(define_insn "lrsc_atomic_" ++ [(set (match_operand:GPR 0 "memory_operand" "+A") ++ (unspec_volatile:GPR ++ [(any_atomic:GPR (match_dup 0) ++ (match_operand:GPR 1 "reg_or_0_operand" "rJ")) ++ (match_operand:SI 2 "const_int_operand")] ;; model ++ UNSPEC_SYNC_OLD_OP)) ++ (clobber (match_scratch:GPR 3 "=&r"))] ;; tmp_1 ++ "!TARGET_ZAAMO && TARGET_ZALRSC" ++ { ++ return "1:\;" ++ "lr.%I2\t%3, %0\;" ++ "\t%3, %3, %1\;" ++ "sc.%J2\t%3, %3, %0\;" ++ "bnez\t%3, 1b"; ++ } ++ [(set_attr "type" "atomic") ++ (set (attr "length") (const_int 16))]) ++ ++;; AMO fetch ops ++ ++(define_expand "atomic_fetch_" ++ [(match_operand:GPR 0 "register_operand") ;; old value at mem ++ (any_atomic:GPR (match_operand:GPR 1 "memory_operand") ;; mem location ++ (match_operand:GPR 2 "reg_or_0_operand")) ;; value for op ++ (match_operand:SI 3 "const_int_operand")] ;; model ++ "TARGET_ZAAMO || TARGET_ZALRSC" ++ { ++ if (TARGET_ZAAMO) ++ emit_insn (gen_amo_atomic_fetch_ (operands[0], operands[1], ++ operands[2], operands[3])); ++ else ++ emit_insn (gen_lrsc_atomic_fetch_ (operands[0], operands[1], ++ operands[2], operands[3])); ++ DONE; ++ }) ++ ++(define_insn "amo_atomic_fetch_" + [(set (match_operand:GPR 0 "register_operand" "=&r") + (match_operand:GPR 1 "memory_operand" "+A")) + (set (match_dup 1) +@@ -112,6 +166,27 @@ + [(set_attr "type" "atomic") + (set (attr "length") (const_int 4))]) + ++(define_insn "lrsc_atomic_fetch_" ++ [(set (match_operand:GPR 0 "register_operand" "=&r") ++ (match_operand:GPR 1 "memory_operand" "+A")) ++ (set (match_dup 1) ++ (unspec_volatile:GPR ++ [(any_atomic:GPR (match_dup 1) ++ (match_operand:GPR 2 "reg_or_0_operand" "rJ")) ++ (match_operand:SI 3 "const_int_operand")] ;; model ++ UNSPEC_SYNC_OLD_OP)) ++ (clobber (match_scratch:GPR 4 "=&r"))] ;; tmp_1 ++ "!TARGET_ZAAMO && TARGET_ZALRSC" ++ { ++ return "1:\;" ++ "lr.%I3\t%0, %1\;" ++ "\t%4, %0, %2\;" ++ "sc.%J3\t%4, %4, %1\;" ++ "bnez\t%4, 1b"; ++ } ++ [(set_attr "type" "atomic") ++ (set (attr "length") (const_int 20))]) ++ + (define_insn "subword_atomic_fetch_strong_" + [(set (match_operand:SI 0 "register_operand" "=&r") ;; old value at mem + (match_operand:SI 1 "memory_operand" "+A")) ;; mem location +@@ -248,7 +323,23 @@ + DONE; + }) + +-(define_insn "atomic_exchange" ++(define_expand "atomic_exchange" ++ [(match_operand:GPR 0 "register_operand") ;; old value at mem ++ (match_operand:GPR 1 "memory_operand") ;; mem location ++ (match_operand:GPR 2 "register_operand") ;; value for op ++ (match_operand:SI 3 "const_int_operand")] ;; model ++ "TARGET_ZAAMO || TARGET_ZALRSC" ++ { ++ if (TARGET_ZAAMO) ++ emit_insn (gen_amo_atomic_exchange (operands[0], operands[1], ++ operands[2], operands[3])); ++ else ++ emit_insn (gen_lrsc_atomic_exchange (operands[0], operands[1], ++ operands[2], operands[3])); ++ DONE; ++ }) ++ ++(define_insn "amo_atomic_exchange" + [(set (match_operand:GPR 0 "register_operand" "=&r") + (unspec_volatile:GPR + [(match_operand:GPR 1 "memory_operand" "+A") +@@ -261,6 +352,26 @@ + [(set_attr "type" "atomic") + (set (attr "length") (const_int 4))]) + ++(define_insn "lrsc_atomic_exchange" ++ [(set (match_operand:GPR 0 "register_operand" "=&r") ++ (unspec_volatile:GPR ++ [(match_operand:GPR 1 "memory_operand" "+A") ++ (match_operand:SI 3 "const_int_operand")] ;; model ++ UNSPEC_SYNC_EXCHANGE)) ++ (set (match_dup 1) ++ (match_operand:GPR 2 "register_operand" "0")) ++ (clobber (match_scratch:GPR 4 "=&r"))] ;; tmp_1 ++ "!TARGET_ZAAMO && TARGET_ZALRSC" ++ { ++ return "1:\;" ++ "lr.%I3\t%4, %1\;" ++ "sc.%J3\t%0, %0, %1\;" ++ "bnez\t%0, 1b\;" ++ "mv\t%0, %4"; ++ } ++ [(set_attr "type" "atomic") ++ (set (attr "length") (const_int 20))]) ++ + (define_expand "atomic_exchange" + [(match_operand:SHORT 0 "register_operand") ;; old value at mem + (match_operand:SHORT 1 "memory_operand") ;; mem location +@@ -517,7 +628,7 @@ + [(match_operand:QI 0 "register_operand" "") ;; bool output + (match_operand:QI 1 "memory_operand" "+A") ;; memory + (match_operand:SI 2 "const_int_operand" "")] ;; model +- "TARGET_ZALRSC" ++ "TARGET_ZAAMO || TARGET_ZALRSC" + { + /* We have no QImode atomics, so use the address LSBs to form a mask, + then use an aligned SImode atomic. */ +@@ -538,7 +649,10 @@ + rtx shifted_set = gen_reg_rtx (SImode); + riscv_lshift_subword (QImode, set, shift, &shifted_set); + +- emit_insn (gen_atomic_fetch_orsi (old, aligned_mem, shifted_set, model)); ++ if (TARGET_ZAAMO) ++ emit_insn (gen_amo_atomic_fetch_orsi (old, aligned_mem, shifted_set, model)); ++ else if (TARGET_ZALRSC) ++ emit_insn (gen_lrsc_atomic_fetch_orsi (old, aligned_mem, shifted_set, model)); + + emit_move_insn (old, gen_rtx_ASHIFTRT (SImode, old, + gen_lowpart (QImode, shift))); +diff --git a/gcc/testsuite/gcc.target/riscv/amo-zaamo-preferred-over-zalrsc.c b/gcc/testsuite/gcc.target/riscv/amo-zaamo-preferred-over-zalrsc.c +new file mode 100644 +index 00000000000..1c124c2b8b1 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo-zaamo-preferred-over-zalrsc.c +@@ -0,0 +1,17 @@ ++/* { dg-do compile } */ ++/* Ensure that AMO ops are emitted when both zalrsc and zaamo are enabled. */ ++/* { dg-options "-O3" } */ ++/* { dg-add-options riscv_zalrsc } */ ++/* { dg-add-options riscv_zaamo } */ ++/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ ++/* { dg-final { check-function-bodies "**" "" } } */ ++ ++/* ++** foo: ++** amoadd\.w\tzero,a1,0\(a0\) ++** ret ++*/ ++void foo (int* bar, int* baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_RELAXED); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-1.c +new file mode 100644 +index 00000000000..3fa74332433 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-1.c +@@ -0,0 +1,19 @@ ++/* { dg-do compile } */ ++/* Verify that lrsc atomic op mappings match Table A.6's recommended mapping. */ ++/* { dg-options "-O3 -march=rv64id_zalrsc -mabi=lp64d" } */ ++/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ ++/* { dg-final { check-function-bodies "**" "" } } */ ++ ++/* ++** foo: ++** 1: ++** lr.w\t[atx][0-9]+, 0\(a0\) ++** add\t[atx][0-9]+, [atx][0-9]+, a1 ++** sc.w\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) ++** bnez\t[atx][0-9]+, 1b ++** ret ++*/ ++void foo (int* bar, int* baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_RELAXED); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-2.c +new file mode 100644 +index 00000000000..af0a2d50d38 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-2.c +@@ -0,0 +1,19 @@ ++/* { dg-do compile } */ ++/* Verify that lrsc atomic op mappings match Table A.6's recommended mapping. */ ++/* { dg-options "-O3 -march=rv64id_zalrsc -mabi=lp64d" } */ ++/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ ++/* { dg-final { check-function-bodies "**" "" } } */ ++ ++/* ++** foo: ++** 1: ++** lr.w.aq\t[atx][0-9]+, 0\(a0\) ++** add\t[atx][0-9]+, [atx][0-9]+, a1 ++** sc.w\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) ++** bnez\t[atx][0-9]+, 1b ++** ret ++*/ ++void foo (int* bar, int* baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_ACQUIRE); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-3.c +new file mode 100644 +index 00000000000..521869b2165 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-3.c +@@ -0,0 +1,19 @@ ++/* { dg-do compile } */ ++/* Verify that lrsc atomic op mappings match Table A.6's recommended mapping. */ ++/* { dg-options "-O3 -march=rv64id_zalrsc -mabi=lp64d" } */ ++/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ ++/* { dg-final { check-function-bodies "**" "" } } */ ++ ++/* ++** foo: ++** 1: ++** lr.w\t[atx][0-9]+, 0\(a0\) ++** add\t[atx][0-9]+, [atx][0-9]+, a1 ++** sc.w.rl\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) ++** bnez\t[atx][0-9]+, 1b ++** ret ++*/ ++void foo (int* bar, int* baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_RELEASE); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-4.c +new file mode 100644 +index 00000000000..8b6e7579f6f +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-4.c +@@ -0,0 +1,19 @@ ++/* { dg-do compile } */ ++/* Verify that lrsc atomic op mappings match Table A.6's recommended mapping. */ ++/* { dg-options "-O3 -march=rv64id_zalrsc -mabi=lp64d" } */ ++/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ ++/* { dg-final { check-function-bodies "**" "" } } */ ++ ++/* ++** foo: ++** 1: ++** lr.w.aq\t[atx][0-9]+, 0\(a0\) ++** add\t[atx][0-9]+, [atx][0-9]+, a1 ++** sc.w.rl\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) ++** bnez\t[atx][0-9]+, 1b ++** ret ++*/ ++void foo (int* bar, int* baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_ACQ_REL); ++} +diff --git a/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-5.c +new file mode 100644 +index 00000000000..0bdc47d5c46 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-5.c +@@ -0,0 +1,19 @@ ++/* { dg-do compile } */ ++/* Verify that lrsc atomic op mappings match Table A.6's recommended mapping. */ ++/* { dg-options "-O3 -march=rv64id_zalrsc -mabi=lp64d" } */ ++/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ ++/* { dg-final { check-function-bodies "**" "" } } */ ++ ++/* ++** foo: ++** 1: ++** lr.w.aqrl\t[atx][0-9]+, 0\(a0\) ++** add\t[atx][0-9]+, [atx][0-9]+, a1 ++** sc.w.rl\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) ++** bnez\t[atx][0-9]+, 1b ++** ret ++*/ ++void foo (int* bar, int* baz) ++{ ++ __atomic_add_fetch(bar, baz, __ATOMIC_SEQ_CST); ++} +-- +2.50.1 + diff --git a/0005-RISC-V-Move-amo-tests-into-subfolder.patch b/0005-RISC-V-Move-amo-tests-into-subfolder.patch new file mode 100644 index 0000000..5f87a06 --- /dev/null +++ b/0005-RISC-V-Move-amo-tests-into-subfolder.patch @@ -0,0 +1,645 @@ +From 675be7771e3f66864dcb8d60e9051e0be1300e6b Mon Sep 17 00:00:00 2001 +From: Patrick O'Neill +Date: Mon, 10 Jun 2024 16:32:11 -0700 +Subject: [PATCH 05/29] RISC-V: Move amo tests into subfolder + +There's a large number of atomic related testcases in the riscv folder. +Move them into a subfolder similar to what was done for rvv testcases. + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/amo-table-a-6-amo-add-1.c: Move to... + * gcc.target/riscv/amo/amo-table-a-6-amo-add-1.c: ...here. + * gcc.target/riscv/amo-table-a-6-amo-add-2.c: Move to... + * gcc.target/riscv/amo/amo-table-a-6-amo-add-2.c: ...here. + * gcc.target/riscv/amo-table-a-6-amo-add-3.c: Move to... + * gcc.target/riscv/amo/amo-table-a-6-amo-add-3.c: ...here. + * gcc.target/riscv/amo-table-a-6-amo-add-4.c: Move to... + * gcc.target/riscv/amo/amo-table-a-6-amo-add-4.c: ...here. + * gcc.target/riscv/amo-table-a-6-amo-add-5.c: Move to... + * gcc.target/riscv/amo/amo-table-a-6-amo-add-5.c: ...here. + * gcc.target/riscv/amo-table-a-6-compare-exchange-1.c: Move to... + * gcc.target/riscv/amo/amo-table-a-6-compare-exchange-1.c: ...here. + * gcc.target/riscv/amo-table-a-6-compare-exchange-2.c: Move to... + * gcc.target/riscv/amo/amo-table-a-6-compare-exchange-2.c: ...here. + * gcc.target/riscv/amo-table-a-6-compare-exchange-3.c: Move to... + * gcc.target/riscv/amo/amo-table-a-6-compare-exchange-3.c: ...here. + * gcc.target/riscv/amo-table-a-6-compare-exchange-4.c: Move to... + * gcc.target/riscv/amo/amo-table-a-6-compare-exchange-4.c: ...here. + * gcc.target/riscv/amo-table-a-6-compare-exchange-5.c: Move to... + * gcc.target/riscv/amo/amo-table-a-6-compare-exchange-5.c: ...here. + * gcc.target/riscv/amo-table-a-6-compare-exchange-6.c: Move to... + * gcc.target/riscv/amo/amo-table-a-6-compare-exchange-6.c: ...here. + * gcc.target/riscv/amo-table-a-6-compare-exchange-7.c: Move to... + * gcc.target/riscv/amo/amo-table-a-6-compare-exchange-7.c: ...here. + * gcc.target/riscv/amo-table-a-6-fence-1.c: Move to... + * gcc.target/riscv/amo/amo-table-a-6-fence-1.c: ...here. + * gcc.target/riscv/amo-table-a-6-fence-2.c: Move to... + * gcc.target/riscv/amo/amo-table-a-6-fence-2.c: ...here. + * gcc.target/riscv/amo-table-a-6-fence-3.c: Move to... + * gcc.target/riscv/amo/amo-table-a-6-fence-3.c: ...here. + * gcc.target/riscv/amo-table-a-6-fence-4.c: Move to... + * gcc.target/riscv/amo/amo-table-a-6-fence-4.c: ...here. + * gcc.target/riscv/amo-table-a-6-fence-5.c: Move to... + * gcc.target/riscv/amo/amo-table-a-6-fence-5.c: ...here. + * gcc.target/riscv/amo-table-a-6-load-1.c: Move to... + * gcc.target/riscv/amo/amo-table-a-6-load-1.c: ...here. + * gcc.target/riscv/amo-table-a-6-load-2.c: Move to... + * gcc.target/riscv/amo/amo-table-a-6-load-2.c: ...here. + * gcc.target/riscv/amo-table-a-6-load-3.c: Move to... + * gcc.target/riscv/amo/amo-table-a-6-load-3.c: ...here. + * gcc.target/riscv/amo-table-a-6-store-1.c: Move to... + * gcc.target/riscv/amo/amo-table-a-6-store-1.c: ...here. + * gcc.target/riscv/amo-table-a-6-store-2.c: Move to... + * gcc.target/riscv/amo/amo-table-a-6-store-2.c: ...here. + * gcc.target/riscv/amo-table-a-6-store-compat-3.c: Move to... + * gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c: ...here. + * gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c: Move to... + * gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-1.c: ...here. + * gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c: Move to... + * gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-2.c: ...here. + * gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c: Move to... + * gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-3.c: ...here. + * gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c: Move to... + * gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-4.c: ...here. + * gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c: Move to... + * gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-5.c: ...here. + * gcc.target/riscv/amo-table-ztso-amo-add-1.c: Move to... + * gcc.target/riscv/amo/amo-table-ztso-amo-add-1.c: ...here. + * gcc.target/riscv/amo-table-ztso-amo-add-2.c: Move to... + * gcc.target/riscv/amo/amo-table-ztso-amo-add-2.c: ...here. + * gcc.target/riscv/amo-table-ztso-amo-add-3.c: Move to... + * gcc.target/riscv/amo/amo-table-ztso-amo-add-3.c: ...here. + * gcc.target/riscv/amo-table-ztso-amo-add-4.c: Move to... + * gcc.target/riscv/amo/amo-table-ztso-amo-add-4.c: ...here. + * gcc.target/riscv/amo-table-ztso-amo-add-5.c: Move to... + * gcc.target/riscv/amo/amo-table-ztso-amo-add-5.c: ...here. + * gcc.target/riscv/amo-table-ztso-compare-exchange-1.c: Move to... + * gcc.target/riscv/amo/amo-table-ztso-compare-exchange-1.c: ...here. + * gcc.target/riscv/amo-table-ztso-compare-exchange-2.c: Move to... + * gcc.target/riscv/amo/amo-table-ztso-compare-exchange-2.c: ...here. + * gcc.target/riscv/amo-table-ztso-compare-exchange-3.c: Move to... + * gcc.target/riscv/amo/amo-table-ztso-compare-exchange-3.c: ...here. + * gcc.target/riscv/amo-table-ztso-compare-exchange-4.c: Move to... + * gcc.target/riscv/amo/amo-table-ztso-compare-exchange-4.c: ...here. + * gcc.target/riscv/amo-table-ztso-compare-exchange-5.c: Move to... + * gcc.target/riscv/amo/amo-table-ztso-compare-exchange-5.c: ...here. + * gcc.target/riscv/amo-table-ztso-compare-exchange-6.c: Move to... + * gcc.target/riscv/amo/amo-table-ztso-compare-exchange-6.c: ...here. + * gcc.target/riscv/amo-table-ztso-compare-exchange-7.c: Move to... + * gcc.target/riscv/amo/amo-table-ztso-compare-exchange-7.c: ...here. + * gcc.target/riscv/amo-table-ztso-fence-1.c: Move to... + * gcc.target/riscv/amo/amo-table-ztso-fence-1.c: ...here. + * gcc.target/riscv/amo-table-ztso-fence-2.c: Move to... + * gcc.target/riscv/amo/amo-table-ztso-fence-2.c: ...here. + * gcc.target/riscv/amo-table-ztso-fence-3.c: Move to... + * gcc.target/riscv/amo/amo-table-ztso-fence-3.c: ...here. + * gcc.target/riscv/amo-table-ztso-fence-4.c: Move to... + * gcc.target/riscv/amo/amo-table-ztso-fence-4.c: ...here. + * gcc.target/riscv/amo-table-ztso-fence-5.c: Move to... + * gcc.target/riscv/amo/amo-table-ztso-fence-5.c: ...here. + * gcc.target/riscv/amo-table-ztso-load-1.c: Move to... + * gcc.target/riscv/amo/amo-table-ztso-load-1.c: ...here. + * gcc.target/riscv/amo-table-ztso-load-2.c: Move to... + * gcc.target/riscv/amo/amo-table-ztso-load-2.c: ...here. + * gcc.target/riscv/amo-table-ztso-load-3.c: Move to... + * gcc.target/riscv/amo/amo-table-ztso-load-3.c: ...here. + * gcc.target/riscv/amo-table-ztso-store-1.c: Move to... + * gcc.target/riscv/amo/amo-table-ztso-store-1.c: ...here. + * gcc.target/riscv/amo-table-ztso-store-2.c: Move to... + * gcc.target/riscv/amo/amo-table-ztso-store-2.c: ...here. + * gcc.target/riscv/amo-table-ztso-store-3.c: Move to... + * gcc.target/riscv/amo/amo-table-ztso-store-3.c: ...here. + * gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c: Move to... + * gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-1.c: ...here. + * gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c: Move to... + * gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-2.c: ...here. + * gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c: Move to... + * gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-3.c: ...here. + * gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c: Move to... + * gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-4.c: ...here. + * gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c: Move to... + * gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-5.c: ...here. + * gcc.target/riscv/amo-zaamo-preferred-over-zalrsc.c: Move to... + * gcc.target/riscv/amo/amo-zaamo-preferred-over-zalrsc.c: ...here. + * gcc.target/riscv/amo-zalrsc-amo-add-1.c: Move to... + * gcc.target/riscv/amo/amo-zalrsc-amo-add-1.c: ...here. + * gcc.target/riscv/amo-zalrsc-amo-add-2.c: Move to... + * gcc.target/riscv/amo/amo-zalrsc-amo-add-2.c: ...here. + * gcc.target/riscv/amo-zalrsc-amo-add-3.c: Move to... + * gcc.target/riscv/amo/amo-zalrsc-amo-add-3.c: ...here. + * gcc.target/riscv/amo-zalrsc-amo-add-4.c: Move to... + * gcc.target/riscv/amo/amo-zalrsc-amo-add-4.c: ...here. + * gcc.target/riscv/amo-zalrsc-amo-add-5.c: Move to... + * gcc.target/riscv/amo/amo-zalrsc-amo-add-5.c: ...here. + * gcc.target/riscv/inline-atomics-1.c: Move to... + * gcc.target/riscv/amo/inline-atomics-1.c: ...here. + * gcc.target/riscv/inline-atomics-2.c: Move to... + * gcc.target/riscv/amo/inline-atomics-2.c: ...here. + * gcc.target/riscv/inline-atomics-3.c: Move to... + * gcc.target/riscv/amo/inline-atomics-3.c: ...here. + * gcc.target/riscv/inline-atomics-4.c: Move to... + * gcc.target/riscv/amo/inline-atomics-4.c: ...here. + * gcc.target/riscv/inline-atomics-5.c: Move to... + * gcc.target/riscv/amo/inline-atomics-5.c: ...here. + * gcc.target/riscv/inline-atomics-6.c: Move to... + * gcc.target/riscv/amo/inline-atomics-6.c: ...here. + * gcc.target/riscv/inline-atomics-7.c: Move to... + * gcc.target/riscv/amo/inline-atomics-7.c: ...here. + * gcc.target/riscv/inline-atomics-8.c: Move to... + * gcc.target/riscv/amo/inline-atomics-8.c: ...here. + * gcc.target/riscv/pr114130.c: Move to... + * gcc.target/riscv/amo/pr114130.c: ...here. + * gcc.target/riscv/pr89835.c: Move to... + * gcc.target/riscv/amo/pr89835.c: ...here. + * gcc.target/riscv/amo/amo.exp: New file. + +Signed-off-by: Patrick O'Neill +(cherry picked from commit 8c944f2559ff279ed7e04c2a75881c04c0c31a9b) +--- + .../riscv/{ => amo}/amo-table-a-6-amo-add-1.c | 0 + .../riscv/{ => amo}/amo-table-a-6-amo-add-2.c | 0 + .../riscv/{ => amo}/amo-table-a-6-amo-add-3.c | 0 + .../riscv/{ => amo}/amo-table-a-6-amo-add-4.c | 0 + .../riscv/{ => amo}/amo-table-a-6-amo-add-5.c | 0 + .../amo-table-a-6-compare-exchange-1.c | 0 + .../amo-table-a-6-compare-exchange-2.c | 0 + .../amo-table-a-6-compare-exchange-3.c | 0 + .../amo-table-a-6-compare-exchange-4.c | 0 + .../amo-table-a-6-compare-exchange-5.c | 0 + .../amo-table-a-6-compare-exchange-6.c | 0 + .../amo-table-a-6-compare-exchange-7.c | 0 + .../riscv/{ => amo}/amo-table-a-6-fence-1.c | 0 + .../riscv/{ => amo}/amo-table-a-6-fence-2.c | 0 + .../riscv/{ => amo}/amo-table-a-6-fence-3.c | 0 + .../riscv/{ => amo}/amo-table-a-6-fence-4.c | 0 + .../riscv/{ => amo}/amo-table-a-6-fence-5.c | 0 + .../riscv/{ => amo}/amo-table-a-6-load-1.c | 0 + .../riscv/{ => amo}/amo-table-a-6-load-2.c | 0 + .../riscv/{ => amo}/amo-table-a-6-load-3.c | 0 + .../riscv/{ => amo}/amo-table-a-6-store-1.c | 0 + .../riscv/{ => amo}/amo-table-a-6-store-2.c | 0 + .../{ => amo}/amo-table-a-6-store-compat-3.c | 0 + .../amo-table-a-6-subword-amo-add-1.c | 0 + .../amo-table-a-6-subword-amo-add-2.c | 0 + .../amo-table-a-6-subword-amo-add-3.c | 0 + .../amo-table-a-6-subword-amo-add-4.c | 0 + .../amo-table-a-6-subword-amo-add-5.c | 0 + .../{ => amo}/amo-table-ztso-amo-add-1.c | 0 + .../{ => amo}/amo-table-ztso-amo-add-2.c | 0 + .../{ => amo}/amo-table-ztso-amo-add-3.c | 0 + .../{ => amo}/amo-table-ztso-amo-add-4.c | 0 + .../{ => amo}/amo-table-ztso-amo-add-5.c | 0 + .../amo-table-ztso-compare-exchange-1.c | 0 + .../amo-table-ztso-compare-exchange-2.c | 0 + .../amo-table-ztso-compare-exchange-3.c | 0 + .../amo-table-ztso-compare-exchange-4.c | 0 + .../amo-table-ztso-compare-exchange-5.c | 0 + .../amo-table-ztso-compare-exchange-6.c | 0 + .../amo-table-ztso-compare-exchange-7.c | 0 + .../riscv/{ => amo}/amo-table-ztso-fence-1.c | 0 + .../riscv/{ => amo}/amo-table-ztso-fence-2.c | 0 + .../riscv/{ => amo}/amo-table-ztso-fence-3.c | 0 + .../riscv/{ => amo}/amo-table-ztso-fence-4.c | 0 + .../riscv/{ => amo}/amo-table-ztso-fence-5.c | 0 + .../riscv/{ => amo}/amo-table-ztso-load-1.c | 0 + .../riscv/{ => amo}/amo-table-ztso-load-2.c | 0 + .../riscv/{ => amo}/amo-table-ztso-load-3.c | 0 + .../riscv/{ => amo}/amo-table-ztso-store-1.c | 0 + .../riscv/{ => amo}/amo-table-ztso-store-2.c | 0 + .../riscv/{ => amo}/amo-table-ztso-store-3.c | 0 + .../amo-table-ztso-subword-amo-add-1.c | 0 + .../amo-table-ztso-subword-amo-add-2.c | 0 + .../amo-table-ztso-subword-amo-add-3.c | 0 + .../amo-table-ztso-subword-amo-add-4.c | 0 + .../amo-table-ztso-subword-amo-add-5.c | 0 + .../amo-zaamo-preferred-over-zalrsc.c | 0 + .../riscv/{ => amo}/amo-zalrsc-amo-add-1.c | 0 + .../riscv/{ => amo}/amo-zalrsc-amo-add-2.c | 0 + .../riscv/{ => amo}/amo-zalrsc-amo-add-3.c | 0 + .../riscv/{ => amo}/amo-zalrsc-amo-add-4.c | 0 + .../riscv/{ => amo}/amo-zalrsc-amo-add-5.c | 0 + gcc/testsuite/gcc.target/riscv/amo/amo.exp | 41 +++++++++++++++++++ + .../riscv/{ => amo}/inline-atomics-1.c | 0 + .../riscv/{ => amo}/inline-atomics-2.c | 0 + .../riscv/{ => amo}/inline-atomics-3.c | 0 + .../riscv/{ => amo}/inline-atomics-4.c | 0 + .../riscv/{ => amo}/inline-atomics-5.c | 0 + .../riscv/{ => amo}/inline-atomics-6.c | 0 + .../riscv/{ => amo}/inline-atomics-7.c | 0 + .../riscv/{ => amo}/inline-atomics-8.c | 0 + .../gcc.target/riscv/{ => amo}/pr114130.c | 0 + .../gcc.target/riscv/{ => amo}/pr89835.c | 0 + 73 files changed, 41 insertions(+) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-a-6-amo-add-1.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-a-6-amo-add-2.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-a-6-amo-add-3.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-a-6-amo-add-4.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-a-6-amo-add-5.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-a-6-compare-exchange-1.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-a-6-compare-exchange-2.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-a-6-compare-exchange-3.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-a-6-compare-exchange-4.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-a-6-compare-exchange-5.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-a-6-compare-exchange-6.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-a-6-compare-exchange-7.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-a-6-fence-1.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-a-6-fence-2.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-a-6-fence-3.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-a-6-fence-4.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-a-6-fence-5.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-a-6-load-1.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-a-6-load-2.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-a-6-load-3.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-a-6-store-1.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-a-6-store-2.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-a-6-store-compat-3.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-a-6-subword-amo-add-1.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-a-6-subword-amo-add-2.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-a-6-subword-amo-add-3.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-a-6-subword-amo-add-4.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-a-6-subword-amo-add-5.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-ztso-amo-add-1.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-ztso-amo-add-2.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-ztso-amo-add-3.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-ztso-amo-add-4.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-ztso-amo-add-5.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-ztso-compare-exchange-1.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-ztso-compare-exchange-2.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-ztso-compare-exchange-3.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-ztso-compare-exchange-4.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-ztso-compare-exchange-5.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-ztso-compare-exchange-6.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-ztso-compare-exchange-7.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-ztso-fence-1.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-ztso-fence-2.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-ztso-fence-3.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-ztso-fence-4.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-ztso-fence-5.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-ztso-load-1.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-ztso-load-2.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-ztso-load-3.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-ztso-store-1.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-ztso-store-2.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-ztso-store-3.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-ztso-subword-amo-add-1.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-ztso-subword-amo-add-2.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-ztso-subword-amo-add-3.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-ztso-subword-amo-add-4.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-table-ztso-subword-amo-add-5.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-zaamo-preferred-over-zalrsc.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-zalrsc-amo-add-1.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-zalrsc-amo-add-2.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-zalrsc-amo-add-3.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-zalrsc-amo-add-4.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/amo-zalrsc-amo-add-5.c (100%) + create mode 100644 gcc/testsuite/gcc.target/riscv/amo/amo.exp + rename gcc/testsuite/gcc.target/riscv/{ => amo}/inline-atomics-1.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/inline-atomics-2.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/inline-atomics-3.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/inline-atomics-4.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/inline-atomics-5.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/inline-atomics-6.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/inline-atomics-7.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/inline-atomics-8.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/pr114130.c (100%) + rename gcc/testsuite/gcc.target/riscv/{ => amo}/pr89835.c (100%) + +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-1.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-1.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-2.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-2.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-3.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-3.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-4.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-4.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-5.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-5.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-1.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-1.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-2.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-2.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-3.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-3.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-4.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-4.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-5.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-5.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-6.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-6.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-6.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-6.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-7.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-7.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-7.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-7.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-1.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-1.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-1.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-2.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-2.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-2.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-3.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-3.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-3.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-4.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-4.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-4.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-4.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-5.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-5.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-5.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-fence-5.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-1.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-1.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-1.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-2.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-2.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-2.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-3.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-3.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-3.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-1.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-1.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-1.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-2.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-2.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-2.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-compat-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-compat-3.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-1.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-1.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-2.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-2.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-3.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-3.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-4.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-4.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-5.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-5.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-1.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-1.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-1.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-2.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-2.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-2.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-3.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-3.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-3.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-4.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-4.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-4.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-5.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-5.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-5.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-compare-exchange-1.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-1.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-compare-exchange-1.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-compare-exchange-2.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-2.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-compare-exchange-2.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-compare-exchange-3.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-3.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-compare-exchange-3.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-4.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-compare-exchange-4.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-4.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-compare-exchange-4.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-5.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-compare-exchange-5.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-5.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-compare-exchange-5.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-6.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-compare-exchange-6.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-6.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-compare-exchange-6.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-7.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-compare-exchange-7.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-7.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-compare-exchange-7.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-fence-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-fence-1.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-ztso-fence-1.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-fence-1.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-fence-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-fence-2.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-ztso-fence-2.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-fence-2.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-fence-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-fence-3.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-ztso-fence-3.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-fence-3.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-fence-4.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-fence-4.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-ztso-fence-4.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-fence-4.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-fence-5.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-fence-5.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-ztso-fence-5.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-fence-5.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-load-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-1.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-ztso-load-1.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-1.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-load-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-2.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-ztso-load-2.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-2.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-load-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-3.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-ztso-load-3.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-3.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-store-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-1.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-ztso-store-1.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-1.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-store-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-2.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-ztso-store-2.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-2.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-store-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-3.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-ztso-store-3.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-3.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-1.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-1.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-2.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-2.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-3.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-3.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-4.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-4.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-5.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-5.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-zaamo-preferred-over-zalrsc.c b/gcc/testsuite/gcc.target/riscv/amo/amo-zaamo-preferred-over-zalrsc.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-zaamo-preferred-over-zalrsc.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-zaamo-preferred-over-zalrsc.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-1.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-1.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-1.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-2.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-2.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-2.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-3.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-3.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-3.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-4.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-4.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-4.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-5.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-5.c +rename to gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-5.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo.exp b/gcc/testsuite/gcc.target/riscv/amo/amo.exp +new file mode 100644 +index 00000000000..2806f4bda7a +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo.exp +@@ -0,0 +1,41 @@ ++# Copyright (C) 2024-2024 Free Software Foundation, Inc. ++ ++# This program is free software; you can redistribute it and/or modify ++# it under the terms of the GNU General Public License as published by ++# the Free Software Foundation; either version 3 of the License, or ++# (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with GCC; see the file COPYING3. If not see ++# . ++ ++# GCC testsuite that uses the `dg.exp' driver. ++ ++# Exit immediately if this isn't a RISC-V target. ++if ![istarget riscv*-*-*] then { ++ return ++} ++ ++# Load support procs. ++load_lib gcc-dg.exp ++ ++# If a testcase doesn't have special options, use these. ++global DEFAULT_CFLAGS ++if ![info exists DEFAULT_CFLAGS] then { ++ set DEFAULT_CFLAGS " -ansi -pedantic-errors" ++} ++ ++# Initialize `dg'. ++dg-init ++ ++# Main loop. ++dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \ ++ "" $DEFAULT_CFLAGS ++ ++# All done. ++dg-finish +diff --git a/gcc/testsuite/gcc.target/riscv/inline-atomics-1.c b/gcc/testsuite/gcc.target/riscv/amo/inline-atomics-1.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/inline-atomics-1.c +rename to gcc/testsuite/gcc.target/riscv/amo/inline-atomics-1.c +diff --git a/gcc/testsuite/gcc.target/riscv/inline-atomics-2.c b/gcc/testsuite/gcc.target/riscv/amo/inline-atomics-2.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/inline-atomics-2.c +rename to gcc/testsuite/gcc.target/riscv/amo/inline-atomics-2.c +diff --git a/gcc/testsuite/gcc.target/riscv/inline-atomics-3.c b/gcc/testsuite/gcc.target/riscv/amo/inline-atomics-3.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/inline-atomics-3.c +rename to gcc/testsuite/gcc.target/riscv/amo/inline-atomics-3.c +diff --git a/gcc/testsuite/gcc.target/riscv/inline-atomics-4.c b/gcc/testsuite/gcc.target/riscv/amo/inline-atomics-4.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/inline-atomics-4.c +rename to gcc/testsuite/gcc.target/riscv/amo/inline-atomics-4.c +diff --git a/gcc/testsuite/gcc.target/riscv/inline-atomics-5.c b/gcc/testsuite/gcc.target/riscv/amo/inline-atomics-5.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/inline-atomics-5.c +rename to gcc/testsuite/gcc.target/riscv/amo/inline-atomics-5.c +diff --git a/gcc/testsuite/gcc.target/riscv/inline-atomics-6.c b/gcc/testsuite/gcc.target/riscv/amo/inline-atomics-6.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/inline-atomics-6.c +rename to gcc/testsuite/gcc.target/riscv/amo/inline-atomics-6.c +diff --git a/gcc/testsuite/gcc.target/riscv/inline-atomics-7.c b/gcc/testsuite/gcc.target/riscv/amo/inline-atomics-7.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/inline-atomics-7.c +rename to gcc/testsuite/gcc.target/riscv/amo/inline-atomics-7.c +diff --git a/gcc/testsuite/gcc.target/riscv/inline-atomics-8.c b/gcc/testsuite/gcc.target/riscv/amo/inline-atomics-8.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/inline-atomics-8.c +rename to gcc/testsuite/gcc.target/riscv/amo/inline-atomics-8.c +diff --git a/gcc/testsuite/gcc.target/riscv/pr114130.c b/gcc/testsuite/gcc.target/riscv/amo/pr114130.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/pr114130.c +rename to gcc/testsuite/gcc.target/riscv/amo/pr114130.c +diff --git a/gcc/testsuite/gcc.target/riscv/pr89835.c b/gcc/testsuite/gcc.target/riscv/amo/pr89835.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/pr89835.c +rename to gcc/testsuite/gcc.target/riscv/amo/pr89835.c +-- +2.50.1 + diff --git a/0006-RISC-V-Fix-amoadd-call-arguments.patch b/0006-RISC-V-Fix-amoadd-call-arguments.patch new file mode 100644 index 0000000..c538011 --- /dev/null +++ b/0006-RISC-V-Fix-amoadd-call-arguments.patch @@ -0,0 +1,410 @@ +From c57fb7fc6c2d195a2b7421d3bc5442483007c9f0 Mon Sep 17 00:00:00 2001 +From: Patrick O'Neill +Date: Mon, 10 Jun 2024 16:58:12 -0700 +Subject: [PATCH 06/29] RISC-V: Fix amoadd call arguments + +Update __atomic_add_fetch arguments to be a pointer and value rather +than two pointers. + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/amo/amo-table-a-6-amo-add-1.c: Update + __atomic_add_fetch args. + * gcc.target/riscv/amo/amo-table-a-6-amo-add-2.c: Ditto. + * gcc.target/riscv/amo/amo-table-a-6-amo-add-3.c: Ditto. + * gcc.target/riscv/amo/amo-table-a-6-amo-add-4.c: Ditto. + * gcc.target/riscv/amo/amo-table-a-6-amo-add-5.c: Ditto. + * gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-1.c: Ditto. + * gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-2.c: Ditto. + * gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-3.c: Ditto. + * gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-4.c: Ditto. + * gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-5.c: Ditto. + * gcc.target/riscv/amo/amo-table-ztso-amo-add-1.c: Ditto. + * gcc.target/riscv/amo/amo-table-ztso-amo-add-2.c: Ditto. + * gcc.target/riscv/amo/amo-table-ztso-amo-add-3.c: Ditto. + * gcc.target/riscv/amo/amo-table-ztso-amo-add-4.c: Ditto. + * gcc.target/riscv/amo/amo-table-ztso-amo-add-5.c: Ditto. + * gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-1.c: Ditto. + * gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-2.c: Ditto. + * gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-3.c: Ditto. + * gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-4.c: Ditto. + * gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-5.c: Ditto. + * gcc.target/riscv/amo/amo-zaamo-preferred-over-zalrsc.c: Ditto. + * gcc.target/riscv/amo/amo-zalrsc-amo-add-1.c: Ditto. + * gcc.target/riscv/amo/amo-zalrsc-amo-add-2.c: Ditto. + * gcc.target/riscv/amo/amo-zalrsc-amo-add-3.c: Ditto. + * gcc.target/riscv/amo/amo-zalrsc-amo-add-4.c: Ditto. + * gcc.target/riscv/amo/amo-zalrsc-amo-add-5.c: Ditto. + +Signed-off-by: Patrick O'Neill +(cherry picked from commit 6343adcef7de1a1214c9b6dd845810aa4a0d19e5) +--- + gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-1.c | 2 +- + gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-2.c | 2 +- + gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-3.c | 2 +- + gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-4.c | 2 +- + gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-5.c | 2 +- + .../gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-1.c | 2 +- + .../gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-2.c | 2 +- + .../gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-3.c | 2 +- + .../gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-4.c | 2 +- + .../gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-5.c | 2 +- + gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-1.c | 2 +- + gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-2.c | 2 +- + gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-3.c | 2 +- + gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-4.c | 2 +- + gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-5.c | 2 +- + .../gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-1.c | 2 +- + .../gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-2.c | 2 +- + .../gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-3.c | 2 +- + .../gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-4.c | 2 +- + .../gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-5.c | 2 +- + .../gcc.target/riscv/amo/amo-zaamo-preferred-over-zalrsc.c | 2 +- + gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-1.c | 2 +- + gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-2.c | 2 +- + gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-3.c | 2 +- + gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-4.c | 2 +- + gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-5.c | 2 +- + 26 files changed, 26 insertions(+), 26 deletions(-) + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-1.c +index 9c2ba39789a..2e53abf28aa 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-1.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-1.c +@@ -10,7 +10,7 @@ + ** amoadd\.w\tzero,a1,0\(a0\) + ** ret + */ +-void foo (int* bar, int* baz) ++void foo (int* bar, int baz) + { + __atomic_add_fetch(bar, baz, __ATOMIC_RELAXED); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-2.c +index b7682a5bab4..14d6b7e4b1b 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-2.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-2.c +@@ -10,7 +10,7 @@ + ** amoadd\.w\.aq\tzero,a1,0\(a0\) + ** ret + */ +-void foo (int* bar, int* baz) ++void foo (int* bar, int baz) + { + __atomic_add_fetch(bar, baz, __ATOMIC_ACQUIRE); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-3.c +index c8776872d91..937a00daf4c 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-3.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-3.c +@@ -10,7 +10,7 @@ + ** amoadd\.w\.rl\tzero,a1,0\(a0\) + ** ret + */ +-void foo (int* bar, int* baz) ++void foo (int* bar, int baz) + { + __atomic_add_fetch(bar, baz, __ATOMIC_RELEASE); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-4.c +index b37c4c3f242..7d7f4e11dd4 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-4.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-4.c +@@ -10,7 +10,7 @@ + ** amoadd\.w\.aqrl\tzero,a1,0\(a0\) + ** ret + */ +-void foo (int* bar, int* baz) ++void foo (int* bar, int baz) + { + __atomic_add_fetch(bar, baz, __ATOMIC_ACQ_REL); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-5.c +index 8d45ca7a347..e5cf1e2e9cf 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-5.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-5.c +@@ -10,7 +10,7 @@ + ** amoadd\.w\.aqrl\tzero,a1,0\(a0\) + ** ret + */ +-void foo (int* bar, int* baz) ++void foo (int* bar, int baz) + { + __atomic_add_fetch(bar, baz, __ATOMIC_SEQ_CST); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-1.c +index 4174fdee352..348b9c8db9c 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-1.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-1.c +@@ -4,7 +4,7 @@ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ + +-void foo (short* bar, short* baz) ++void foo (short* bar, short baz) + { + __atomic_add_fetch(bar, baz, __ATOMIC_RELAXED); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-2.c +index 4c06c90b558..31011580684 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-2.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-2.c +@@ -4,7 +4,7 @@ + /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ + +-void foo (short* bar, short* baz) ++void foo (short* bar, short baz) + { + __atomic_add_fetch(bar, baz, __ATOMIC_ACQUIRE); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-3.c +index 7e791c901b6..38bedcd6b41 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-3.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-3.c +@@ -4,7 +4,7 @@ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ + +-void foo (short* bar, short* baz) ++void foo (short* bar, short baz) + { + __atomic_add_fetch(bar, baz, __ATOMIC_RELEASE); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-4.c +index 76f3be27110..d69610e2d9e 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-4.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-4.c +@@ -4,7 +4,7 @@ + /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ + +-void foo (short* bar, short* baz) ++void foo (short* bar, short baz) + { + __atomic_add_fetch(bar, baz, __ATOMIC_ACQ_REL); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-5.c +index 8dbfa9c4fc8..976f8909bdd 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-5.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-5.c +@@ -4,7 +4,7 @@ + /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ + +-void foo (short* bar, short* baz) ++void foo (short* bar, short baz) + { + __atomic_add_fetch(bar, baz, __ATOMIC_SEQ_CST); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-1.c +index 82169390925..000407a2583 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-1.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-1.c +@@ -11,7 +11,7 @@ + ** amoadd\.w\tzero,a1,0\(a0\) + ** ret + */ +-void foo (int* bar, int* baz) ++void foo (int* bar, int baz) + { + __atomic_add_fetch(bar, baz, __ATOMIC_RELAXED); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-2.c +index a238c6f4403..3e441cadbf3 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-2.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-2.c +@@ -11,7 +11,7 @@ + ** amoadd\.w\tzero,a1,0\(a0\) + ** ret + */ +-void foo (int* bar, int* baz) ++void foo (int* bar, int baz) + { + __atomic_add_fetch(bar, baz, __ATOMIC_ACQUIRE); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-3.c +index c97bf467c63..8af1a2f79a4 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-3.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-3.c +@@ -11,7 +11,7 @@ + ** amoadd\.w\tzero,a1,0\(a0\) + ** ret + */ +-void foo (int* bar, int* baz) ++void foo (int* bar, int baz) + { + __atomic_add_fetch(bar, baz, __ATOMIC_RELEASE); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-4.c +index 14e632ba2f2..0b3a7e59689 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-4.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-4.c +@@ -11,7 +11,7 @@ + ** amoadd\.w\tzero,a1,0\(a0\) + ** ret + */ +-void foo (int* bar, int* baz) ++void foo (int* bar, int baz) + { + __atomic_add_fetch(bar, baz, __ATOMIC_ACQ_REL); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-5.c +index 74d8df99ddc..f189827d6cf 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-5.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-5.c +@@ -11,7 +11,7 @@ + ** amoadd\.w\tzero,a1,0\(a0\) + ** ret + */ +-void foo (int* bar, int* baz) ++void foo (int* bar, int baz) + { + __atomic_add_fetch(bar, baz, __ATOMIC_SEQ_CST); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-1.c +index 5c0a8b8f6e9..a44d6980ece 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-1.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-1.c +@@ -5,7 +5,7 @@ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ + +-void foo (short* bar, short* baz) ++void foo (short* bar, short baz) + { + __atomic_add_fetch(bar, baz, __ATOMIC_RELAXED); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-2.c +index 551078186ec..8d28569c79c 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-2.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-2.c +@@ -5,7 +5,7 @@ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ + +-void foo (short* bar, short* baz) ++void foo (short* bar, short baz) + { + __atomic_add_fetch(bar, baz, __ATOMIC_ACQUIRE); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-3.c +index 5f0f7870721..fb803ab9cbf 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-3.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-3.c +@@ -5,7 +5,7 @@ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ + +-void foo (short* bar, short* baz) ++void foo (short* bar, short baz) + { + __atomic_add_fetch(bar, baz, __ATOMIC_RELEASE); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-4.c +index 24f4f02dcea..a88e409063a 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-4.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-4.c +@@ -5,7 +5,7 @@ + /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ + +-void foo (short* bar, short* baz) ++void foo (short* bar, short baz) + { + __atomic_add_fetch(bar, baz, __ATOMIC_ACQ_REL); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-5.c +index 405e498fb40..d851e5e5944 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-5.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-5.c +@@ -5,7 +5,7 @@ + /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */ + /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ + +-void foo (short* bar, short* baz) ++void foo (short* bar, short baz) + { + __atomic_add_fetch(bar, baz, __ATOMIC_SEQ_CST); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-zaamo-preferred-over-zalrsc.c b/gcc/testsuite/gcc.target/riscv/amo/amo-zaamo-preferred-over-zalrsc.c +index 1c124c2b8b1..dae30c32e01 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-zaamo-preferred-over-zalrsc.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-zaamo-preferred-over-zalrsc.c +@@ -11,7 +11,7 @@ + ** amoadd\.w\tzero,a1,0\(a0\) + ** ret + */ +-void foo (int* bar, int* baz) ++void foo (int* bar, int baz) + { + __atomic_add_fetch(bar, baz, __ATOMIC_RELAXED); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-1.c +index 3fa74332433..49c1a181d69 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-1.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-1.c +@@ -13,7 +13,7 @@ + ** bnez\t[atx][0-9]+, 1b + ** ret + */ +-void foo (int* bar, int* baz) ++void foo (int* bar, int baz) + { + __atomic_add_fetch(bar, baz, __ATOMIC_RELAXED); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-2.c +index af0a2d50d38..af93c9a182b 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-2.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-2.c +@@ -13,7 +13,7 @@ + ** bnez\t[atx][0-9]+, 1b + ** ret + */ +-void foo (int* bar, int* baz) ++void foo (int* bar, int baz) + { + __atomic_add_fetch(bar, baz, __ATOMIC_ACQUIRE); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-3.c +index 521869b2165..ce68af841ea 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-3.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-3.c +@@ -13,7 +13,7 @@ + ** bnez\t[atx][0-9]+, 1b + ** ret + */ +-void foo (int* bar, int* baz) ++void foo (int* bar, int baz) + { + __atomic_add_fetch(bar, baz, __ATOMIC_RELEASE); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-4.c +index 8b6e7579f6f..be9f847782e 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-4.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-4.c +@@ -13,7 +13,7 @@ + ** bnez\t[atx][0-9]+, 1b + ** ret + */ +-void foo (int* bar, int* baz) ++void foo (int* bar, int baz) + { + __atomic_add_fetch(bar, baz, __ATOMIC_ACQ_REL); + } +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-5.c +index 0bdc47d5c46..b31170c15db 100644 +--- a/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-5.c ++++ b/gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-5.c +@@ -13,7 +13,7 @@ + ** bnez\t[atx][0-9]+, 1b + ** ret + */ +-void foo (int* bar, int* baz) ++void foo (int* bar, int baz) + { + __atomic_add_fetch(bar, baz, __ATOMIC_SEQ_CST); + } +-- +2.50.1 + diff --git a/0007-RISC-V-Add-configure-check-for-Zaamo-Zalrsc-assemble.patch b/0007-RISC-V-Add-configure-check-for-Zaamo-Zalrsc-assemble.patch new file mode 100644 index 0000000..606deb3 --- /dev/null +++ b/0007-RISC-V-Add-configure-check-for-Zaamo-Zalrsc-assemble.patch @@ -0,0 +1,144 @@ +From 5b5725249cd33a43c7858e2e630917163ed95cee Mon Sep 17 00:00:00 2001 +From: Patrick O'Neill +Date: Mon, 17 Jun 2024 09:46:05 -0700 +Subject: [PATCH 07/29] RISC-V: Add configure check for Zaamo/Zalrsc assembler + support + +Binutils 2.42 and before don't support Zaamo/Zalrsc. Add a configure +check to prevent emitting Zaamo/Zalrsc in the arch string when the +assember does not support it. + +gcc/ChangeLog: + + * common/config/riscv/riscv-common.cc + (riscv_subset_list::to_string): Skip zaamo/zalrsc when not + supported by the assembler. + * config.in: Regenerate. + * configure: Regenerate. + * configure.ac: Add zaamo/zalrsc assmeber check. + +Signed-off-by: Patrick O'Neill +Acked-by: Palmer Dabbelt # RISC-V +Reviewed-by: Palmer Dabbelt # RISC-V +(cherry picked from commit 4f18f75c5648d0b46a72f18e321bec279a6964be) +--- + gcc/common/config/riscv/riscv-common.cc | 11 +++++++++ + gcc/config.in | 6 +++++ + gcc/configure | 31 +++++++++++++++++++++++++ + gcc/configure.ac | 5 ++++ + 4 files changed, 53 insertions(+) + +diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc +index 0039a27a8da..cca7e4fc49a 100644 +--- a/gcc/common/config/riscv/riscv-common.cc ++++ b/gcc/common/config/riscv/riscv-common.cc +@@ -821,6 +821,7 @@ riscv_subset_list::to_string (bool version_p) const + riscv_subset_t *subset; + + bool skip_zifencei = false; ++ bool skip_zaamo_zalrsc = false; + bool skip_zicsr = false; + bool i2p0 = false; + +@@ -848,6 +849,10 @@ riscv_subset_list::to_string (bool version_p) const + a mistake in that binutils 2.35 supports zicsr but not zifencei. */ + skip_zifencei = true; + #endif ++#ifndef HAVE_AS_MARCH_ZAAMO_ZALRSC ++ /* Skip since binutils 2.42 and earlier don't recognize zaamo/zalrsc. */ ++ skip_zaamo_zalrsc = true; ++#endif + + for (subset = m_head; subset != NULL; subset = subset->next) + { +@@ -859,6 +864,12 @@ riscv_subset_list::to_string (bool version_p) const + subset->name == "zicsr") + continue; + ++ if (skip_zaamo_zalrsc && subset->name == "zaamo") ++ continue; ++ ++ if (skip_zaamo_zalrsc && subset->name == "zalrsc") ++ continue; ++ + /* For !version_p, we only separate extension with underline for + multi-letter extension. */ + if (!first && +diff --git a/gcc/config.in b/gcc/config.in +index 3daa90be0e8..21a7e12376b 100644 +--- a/gcc/config.in ++++ b/gcc/config.in +@@ -629,6 +629,12 @@ + #endif + + ++/* Define if the assembler understands -march=rv*_zaamo_zalrsc. */ ++#ifndef USED_FOR_TARGET ++#undef HAVE_AS_MARCH_ZAAMO_ZALRSC ++#endif ++ ++ + /* Define if the assembler understands -march=rv*_zifencei. */ + #ifndef USED_FOR_TARGET + #undef HAVE_AS_MARCH_ZIFENCEI +diff --git a/gcc/configure b/gcc/configure +index a4dcd131783..c0dd02ffff5 100755 +--- a/gcc/configure ++++ b/gcc/configure +@@ -31069,6 +31069,37 @@ if test $gcc_cv_as_riscv_march_zifencei = yes; then + + $as_echo "#define HAVE_AS_MARCH_ZIFENCEI 1" >>confdefs.h + ++fi ++ ++ { $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for -march=rv32i_zaamo_zalrsc support" >&5 ++$as_echo_n "checking assembler for -march=rv32i_zaamo_zalrsc support... " >&6; } ++if ${gcc_cv_as_riscv_march_zaamo_zalrsc+:} false; then : ++ $as_echo_n "(cached) " >&6 ++else ++ gcc_cv_as_riscv_march_zaamo_zalrsc=no ++ if test x$gcc_cv_as != x; then ++ $as_echo '' > conftest.s ++ if { ac_try='$gcc_cv_as $gcc_cv_as_flags -march=rv32i_zaamo_zalrsc -o conftest.o conftest.s >&5' ++ { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5 ++ (eval $ac_try) 2>&5 ++ ac_status=$? ++ $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 ++ test $ac_status = 0; }; } ++ then ++ gcc_cv_as_riscv_march_zaamo_zalrsc=yes ++ else ++ echo "configure: failed program was" >&5 ++ cat conftest.s >&5 ++ fi ++ rm -f conftest.o conftest.s ++ fi ++fi ++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_as_riscv_march_zaamo_zalrsc" >&5 ++$as_echo "$gcc_cv_as_riscv_march_zaamo_zalrsc" >&6; } ++if test $gcc_cv_as_riscv_march_zaamo_zalrsc = yes; then ++ ++$as_echo "#define HAVE_AS_MARCH_ZAAMO_ZALRSC 1" >>confdefs.h ++ + fi + + ;; +diff --git a/gcc/configure.ac b/gcc/configure.ac +index cb743b5a875..09ffd6bca3c 100644 +--- a/gcc/configure.ac ++++ b/gcc/configure.ac +@@ -5518,6 +5518,11 @@ configured with --enable-newlib-nano-formatted-io.]) + [-march=rv32i_zifencei2p0],,, + [AC_DEFINE(HAVE_AS_MARCH_ZIFENCEI, 1, + [Define if the assembler understands -march=rv*_zifencei.])]) ++ gcc_GAS_CHECK_FEATURE([-march=rv32i_zaamo_zalrsc support], ++ gcc_cv_as_riscv_march_zaamo_zalrsc, ++ [-march=rv32i_zaamo_zalrsc],,, ++ [AC_DEFINE(HAVE_AS_MARCH_ZAAMO_ZALRSC, 1, ++ [Define if the assembler understands -march=rv*_zaamo_zalrsc.])]) + ;; + loongarch*-*-*) + gcc_GAS_CHECK_FEATURE([.dtprelword support], +-- +2.50.1 + diff --git a/0008-RISC-V-Promote-Zaamo-Zalrsc-to-a-when-using-an-old-b.patch b/0008-RISC-V-Promote-Zaamo-Zalrsc-to-a-when-using-an-old-b.patch new file mode 100644 index 0000000..28d4c90 --- /dev/null +++ b/0008-RISC-V-Promote-Zaamo-Zalrsc-to-a-when-using-an-old-b.patch @@ -0,0 +1,39 @@ +From be974fb879efd669bf9d40dede3008234fa0129e Mon Sep 17 00:00:00 2001 +From: Patrick O'Neill +Date: Tue, 18 Jun 2024 14:40:15 -0700 +Subject: [PATCH 08/29] RISC-V: Promote Zaamo/Zalrsc to a when using an old + binutils + +Binutils 2.42 and before don't support Zaamo/Zalrsc. When users specify +both Zaamo and Zalrsc, promote them to 'a' in the -march string. + +This does not affect testsuite results for users with old versions of binutils. +Testcases that failed due to 'call'/isa string continue to fail after this PATCH +when using an old version of binutils. + +gcc/ChangeLog: + + * common/config/riscv/riscv-common.cc: Add 'a' extension to + riscv_combine_info. + +Signed-off-by: Patrick O'Neill +(cherry picked from commit e03583e7ee99552276a90a4094776fda55ab2e02) +--- + gcc/common/config/riscv/riscv-common.cc | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc +index cca7e4fc49a..f4f7f50af76 100644 +--- a/gcc/common/config/riscv/riscv-common.cc ++++ b/gcc/common/config/riscv/riscv-common.cc +@@ -396,6 +396,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] = + /* Combine extensions defined in this table */ + static const struct riscv_ext_version riscv_combine_info[] = + { ++ {"a", ISA_SPEC_CLASS_20191213, 2, 1}, + {"zk", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zkn", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zks", ISA_SPEC_CLASS_NONE, 1, 0}, +-- +2.50.1 + diff --git a/0009-RISC-V-Rename-amo-testcases.patch b/0009-RISC-V-Rename-amo-testcases.patch new file mode 100644 index 0000000..79eed7c --- /dev/null +++ b/0009-RISC-V-Rename-amo-testcases.patch @@ -0,0 +1,315 @@ +From b75025d5809d39b41244605234112def3a94bc4b Mon Sep 17 00:00:00 2001 +From: Patrick O'Neill +Date: Tue, 25 Jun 2024 14:14:16 -0700 +Subject: [PATCH 09/29] RISC-V: Rename amo testcases + +Rename riscv/amo/ testcases to follow a '{ext}-{model}-{name}-{memory order}.c' +naming convention. + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/amo/amo-table-a-6-load-2.c: Move to... + * gcc.target/riscv/amo/a-rvwmo-load-acquire.c: ...here. + * gcc.target/riscv/amo/amo-table-a-6-load-1.c: Move to... + * gcc.target/riscv/amo/a-rvwmo-load-relaxed.c: ...here. + * gcc.target/riscv/amo/amo-table-a-6-load-3.c: Move to... + * gcc.target/riscv/amo/a-rvwmo-load-seq-cst.c: ...here. + * gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c: Move to... + * gcc.target/riscv/amo/a-rvwmo-store-compat-seq-cst.c: ...here. + * gcc.target/riscv/amo/amo-table-a-6-store-1.c: Move to... + * gcc.target/riscv/amo/a-rvwmo-store-relaxed.c: ...here. + * gcc.target/riscv/amo/amo-table-a-6-store-2.c: Move to... + * gcc.target/riscv/amo/a-rvwmo-store-release.c: ...here. + * gcc.target/riscv/amo/amo-table-ztso-load-2.c: Move to... + * gcc.target/riscv/amo/a-ztso-load-acquire.c: ...here. + * gcc.target/riscv/amo/amo-table-ztso-load-1.c: Move to... + * gcc.target/riscv/amo/a-ztso-load-relaxed.c: ...here. + * gcc.target/riscv/amo/amo-table-ztso-load-3.c: Move to... + * gcc.target/riscv/amo/a-ztso-load-seq-cst.c: ...here. + * gcc.target/riscv/amo/amo-table-ztso-store-3.c: Move to... + * gcc.target/riscv/amo/a-ztso-store-compat-seq-cst.c: ...here. + * gcc.target/riscv/amo/amo-table-ztso-store-1.c: Move to... + * gcc.target/riscv/amo/a-ztso-store-relaxed.c: ...here. + * gcc.target/riscv/amo/amo-table-ztso-store-2.c: Move to... + * gcc.target/riscv/amo/a-ztso-store-release.c: ...here. + * gcc.target/riscv/amo/amo-zaamo-preferred-over-zalrsc.c: Move to... + * gcc.target/riscv/amo/zaamo-preferred-over-zalrsc.c: ...here. + * gcc.target/riscv/amo/amo-table-a-6-compare-exchange-6.c: Move to... + * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire-release.c: ...here. + * gcc.target/riscv/amo/amo-table-a-6-compare-exchange-3.c: Move to... + * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire.c: ...here. + * gcc.target/riscv/amo/amo-table-a-6-compare-exchange-2.c: Move to... + * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-consume.c: ...here. + * gcc.target/riscv/amo/amo-table-a-6-compare-exchange-1.c: Move to... + * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-relaxed.c: ...here. + * gcc.target/riscv/amo/amo-table-a-6-compare-exchange-4.c: Move to... + * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-release.c: ...here. + * gcc.target/riscv/amo/amo-table-a-6-compare-exchange-7.c: Move to... + * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst-relaxed.c: ...here. + * gcc.target/riscv/amo/amo-table-a-6-compare-exchange-5.c: Move to... + * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst.c: ...here. + * gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-4.c: Move to... + * gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acq-rel.c: ...here. + * gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-2.c: Move to... + * gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acquire.c: ...here. + * gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-1.c: Move to... + * gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-relaxed.c: ...here. + * gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-3.c: Move to... + * gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-release.c: ...here. + * gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-5.c: Move to... + * gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-seq-cst.c: ...here. + * gcc.target/riscv/amo/amo-table-ztso-compare-exchange-6.c: Move to... + * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire-release.c: ...here. + * gcc.target/riscv/amo/amo-table-ztso-compare-exchange-3.c: Move to... + * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire.c: ...here. + * gcc.target/riscv/amo/amo-table-ztso-compare-exchange-2.c: Move to... + * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-consume.c: ...here. + * gcc.target/riscv/amo/amo-table-ztso-compare-exchange-1.c: Move to... + * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-relaxed.c: ...here. + * gcc.target/riscv/amo/amo-table-ztso-compare-exchange-4.c: Move to... + * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-release.c: ...here. + * gcc.target/riscv/amo/amo-table-ztso-compare-exchange-7.c: Move to... + * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst-relaxed.c: ...here. + * gcc.target/riscv/amo/amo-table-ztso-compare-exchange-5.c: Move to... + * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst.c: ...here. + * gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-4.c: Move to... + * gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acq-rel.c: ...here. + * gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-2.c: Move to... + * gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acquire.c: ...here. + * gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-1.c: Move to... + * gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-relaxed.c: ...here. + * gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-3.c: Move to... + * gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-release.c: ...here. + * gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-5.c: Move to... + * gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-seq-cst.c: ...here. + +Signed-off-by: Patrick O'Neill +(cherry picked from commit 08498f81f0595eb8a90ea33afd7dab44bb76b293) +--- + .../riscv/amo/{amo-table-a-6-load-2.c => a-rvwmo-load-acquire.c} | 0 + .../riscv/amo/{amo-table-a-6-load-1.c => a-rvwmo-load-relaxed.c} | 0 + .../riscv/amo/{amo-table-a-6-load-3.c => a-rvwmo-load-seq-cst.c} | 0 + ...-table-a-6-store-compat-3.c => a-rvwmo-store-compat-seq-cst.c} | 0 + .../amo/{amo-table-a-6-store-1.c => a-rvwmo-store-relaxed.c} | 0 + .../amo/{amo-table-a-6-store-2.c => a-rvwmo-store-release.c} | 0 + .../riscv/amo/{amo-table-ztso-load-2.c => a-ztso-load-acquire.c} | 0 + .../riscv/amo/{amo-table-ztso-load-1.c => a-ztso-load-relaxed.c} | 0 + .../riscv/amo/{amo-table-ztso-load-3.c => a-ztso-load-seq-cst.c} | 0 + .../{amo-table-ztso-store-3.c => a-ztso-store-compat-seq-cst.c} | 0 + .../amo/{amo-table-ztso-store-1.c => a-ztso-store-relaxed.c} | 0 + .../amo/{amo-table-ztso-store-2.c => a-ztso-store-release.c} | 0 + ...aamo-preferred-over-zalrsc.c => zaamo-preferred-over-zalrsc.c} | 0 + ...ge-6.c => zalrsc-rvwmo-compare-exchange-int-acquire-release.c} | 0 + ...e-exchange-3.c => zalrsc-rvwmo-compare-exchange-int-acquire.c} | 0 + ...e-exchange-2.c => zalrsc-rvwmo-compare-exchange-int-consume.c} | 0 + ...e-exchange-1.c => zalrsc-rvwmo-compare-exchange-int-relaxed.c} | 0 + ...e-exchange-4.c => zalrsc-rvwmo-compare-exchange-int-release.c} | 0 + ...ge-7.c => zalrsc-rvwmo-compare-exchange-int-seq-cst-relaxed.c} | 0 + ...e-exchange-5.c => zalrsc-rvwmo-compare-exchange-int-seq-cst.c} | 0 + ...rd-amo-add-4.c => zalrsc-rvwmo-subword-amo-add-char-acq-rel.c} | 0 + ...rd-amo-add-2.c => zalrsc-rvwmo-subword-amo-add-char-acquire.c} | 0 + ...rd-amo-add-1.c => zalrsc-rvwmo-subword-amo-add-char-relaxed.c} | 0 + ...rd-amo-add-3.c => zalrsc-rvwmo-subword-amo-add-char-release.c} | 0 + ...rd-amo-add-5.c => zalrsc-rvwmo-subword-amo-add-char-seq-cst.c} | 0 + ...nge-6.c => zalrsc-ztso-compare-exchange-int-acquire-release.c} | 0 + ...re-exchange-3.c => zalrsc-ztso-compare-exchange-int-acquire.c} | 0 + ...re-exchange-2.c => zalrsc-ztso-compare-exchange-int-consume.c} | 0 + ...re-exchange-1.c => zalrsc-ztso-compare-exchange-int-relaxed.c} | 0 + ...re-exchange-4.c => zalrsc-ztso-compare-exchange-int-release.c} | 0 + ...nge-7.c => zalrsc-ztso-compare-exchange-int-seq-cst-relaxed.c} | 0 + ...re-exchange-5.c => zalrsc-ztso-compare-exchange-int-seq-cst.c} | 0 + ...ord-amo-add-4.c => zalrsc-ztso-subword-amo-add-char-acq-rel.c} | 0 + ...ord-amo-add-2.c => zalrsc-ztso-subword-amo-add-char-acquire.c} | 0 + ...ord-amo-add-1.c => zalrsc-ztso-subword-amo-add-char-relaxed.c} | 0 + ...ord-amo-add-3.c => zalrsc-ztso-subword-amo-add-char-release.c} | 0 + ...ord-amo-add-5.c => zalrsc-ztso-subword-amo-add-char-seq-cst.c} | 0 + 37 files changed, 0 insertions(+), 0 deletions(-) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-a-6-load-2.c => a-rvwmo-load-acquire.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-a-6-load-1.c => a-rvwmo-load-relaxed.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-a-6-load-3.c => a-rvwmo-load-seq-cst.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-a-6-store-compat-3.c => a-rvwmo-store-compat-seq-cst.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-a-6-store-1.c => a-rvwmo-store-relaxed.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-a-6-store-2.c => a-rvwmo-store-release.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-ztso-load-2.c => a-ztso-load-acquire.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-ztso-load-1.c => a-ztso-load-relaxed.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-ztso-load-3.c => a-ztso-load-seq-cst.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-ztso-store-3.c => a-ztso-store-compat-seq-cst.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-ztso-store-1.c => a-ztso-store-relaxed.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-ztso-store-2.c => a-ztso-store-release.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-zaamo-preferred-over-zalrsc.c => zaamo-preferred-over-zalrsc.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-a-6-compare-exchange-6.c => zalrsc-rvwmo-compare-exchange-int-acquire-release.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-a-6-compare-exchange-3.c => zalrsc-rvwmo-compare-exchange-int-acquire.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-a-6-compare-exchange-2.c => zalrsc-rvwmo-compare-exchange-int-consume.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-a-6-compare-exchange-1.c => zalrsc-rvwmo-compare-exchange-int-relaxed.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-a-6-compare-exchange-4.c => zalrsc-rvwmo-compare-exchange-int-release.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-a-6-compare-exchange-7.c => zalrsc-rvwmo-compare-exchange-int-seq-cst-relaxed.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-a-6-compare-exchange-5.c => zalrsc-rvwmo-compare-exchange-int-seq-cst.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-a-6-subword-amo-add-4.c => zalrsc-rvwmo-subword-amo-add-char-acq-rel.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-a-6-subword-amo-add-2.c => zalrsc-rvwmo-subword-amo-add-char-acquire.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-a-6-subword-amo-add-1.c => zalrsc-rvwmo-subword-amo-add-char-relaxed.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-a-6-subword-amo-add-3.c => zalrsc-rvwmo-subword-amo-add-char-release.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-a-6-subword-amo-add-5.c => zalrsc-rvwmo-subword-amo-add-char-seq-cst.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-ztso-compare-exchange-6.c => zalrsc-ztso-compare-exchange-int-acquire-release.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-ztso-compare-exchange-3.c => zalrsc-ztso-compare-exchange-int-acquire.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-ztso-compare-exchange-2.c => zalrsc-ztso-compare-exchange-int-consume.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-ztso-compare-exchange-1.c => zalrsc-ztso-compare-exchange-int-relaxed.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-ztso-compare-exchange-4.c => zalrsc-ztso-compare-exchange-int-release.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-ztso-compare-exchange-7.c => zalrsc-ztso-compare-exchange-int-seq-cst-relaxed.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-ztso-compare-exchange-5.c => zalrsc-ztso-compare-exchange-int-seq-cst.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-ztso-subword-amo-add-4.c => zalrsc-ztso-subword-amo-add-char-acq-rel.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-ztso-subword-amo-add-2.c => zalrsc-ztso-subword-amo-add-char-acquire.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-ztso-subword-amo-add-1.c => zalrsc-ztso-subword-amo-add-char-relaxed.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-ztso-subword-amo-add-3.c => zalrsc-ztso-subword-amo-add-char-release.c} (100%) + rename gcc/testsuite/gcc.target/riscv/amo/{amo-table-ztso-subword-amo-add-5.c => zalrsc-ztso-subword-amo-add-char-seq-cst.c} (100%) + +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-2.c b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-acquire.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-2.c +rename to gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-acquire.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-1.c b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-relaxed.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-1.c +rename to gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-relaxed.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-3.c b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-seq-cst.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-3.c +rename to gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-seq-cst.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-compat-seq-cst.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c +rename to gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-compat-seq-cst.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-1.c b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-relaxed.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-1.c +rename to gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-relaxed.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-2.c b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-release.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-2.c +rename to gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-release.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-2.c b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-acquire.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-2.c +rename to gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-acquire.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-1.c b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-relaxed.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-1.c +rename to gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-relaxed.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-3.c b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-seq-cst.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-3.c +rename to gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-seq-cst.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-3.c b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-compat-seq-cst.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-3.c +rename to gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-compat-seq-cst.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-1.c b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-relaxed.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-1.c +rename to gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-relaxed.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-2.c b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-release.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-2.c +rename to gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-release.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-zaamo-preferred-over-zalrsc.c b/gcc/testsuite/gcc.target/riscv/amo/zaamo-preferred-over-zalrsc.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-zaamo-preferred-over-zalrsc.c +rename to gcc/testsuite/gcc.target/riscv/amo/zaamo-preferred-over-zalrsc.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-6.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire-release.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-6.c +rename to gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire-release.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-3.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-3.c +rename to gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-2.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-consume.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-2.c +rename to gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-consume.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-1.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-relaxed.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-1.c +rename to gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-relaxed.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-4.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-release.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-4.c +rename to gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-release.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-7.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst-relaxed.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-7.c +rename to gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst-relaxed.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-5.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-compare-exchange-5.c +rename to gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acq-rel.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-4.c +rename to gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acq-rel.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acquire.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-2.c +rename to gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acquire.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-relaxed.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-1.c +rename to gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-relaxed.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-release.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-3.c +rename to gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-release.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-seq-cst.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-5.c +rename to gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-seq-cst.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-compare-exchange-6.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire-release.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-compare-exchange-6.c +rename to gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire-release.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-compare-exchange-3.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-compare-exchange-3.c +rename to gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-compare-exchange-2.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-consume.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-compare-exchange-2.c +rename to gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-consume.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-compare-exchange-1.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-relaxed.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-compare-exchange-1.c +rename to gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-relaxed.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-compare-exchange-4.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-release.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-compare-exchange-4.c +rename to gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-release.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-compare-exchange-7.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst-relaxed.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-compare-exchange-7.c +rename to gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst-relaxed.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-compare-exchange-5.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-compare-exchange-5.c +rename to gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acq-rel.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-4.c +rename to gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acq-rel.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acquire.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-2.c +rename to gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acquire.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-relaxed.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-1.c +rename to gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-relaxed.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-release.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-3.c +rename to gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-release.c +diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-seq-cst.c +similarity index 100% +rename from gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-5.c +rename to gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-seq-cst.c +-- +2.50.1 + diff --git a/0010-RISC-V-Add-support-for-B-standard-extension.patch b/0010-RISC-V-Add-support-for-B-standard-extension.patch new file mode 100644 index 0000000..475b70d --- /dev/null +++ b/0010-RISC-V-Add-support-for-B-standard-extension.patch @@ -0,0 +1,70 @@ +From f2ab2a7c1e7da58a10b1eb22f2ce36d417a32bae Mon Sep 17 00:00:00 2001 +From: Edwin Lu +Date: Wed, 10 Jul 2024 09:44:48 -0700 +Subject: [PATCH 10/29] RISC-V: Add support for B standard extension + +This patch adds support for recognizing the B standard extension to be the +collection of Zba, Zbb, Zbs extensions for consistency and conciseness +across toolchains + +https://github.com/riscv/riscv-b/tags + +gcc/ChangeLog: + + * common/config/riscv/riscv-common.cc: Add imply rules for B extension + * config/riscv/arch-canonicalize: Ditto + +Signed-off-by: Edwin Lu +(cherry picked from commit 2a90c41a131080e5fdd2b5554fcdba5c654cb93f) +--- + gcc/common/config/riscv/riscv-common.cc | 7 +++++++ + gcc/config/riscv/arch-canonicalize | 1 + + 2 files changed, 8 insertions(+) + +diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc +index f4f7f50af76..00c73887e8c 100644 +--- a/gcc/common/config/riscv/riscv-common.cc ++++ b/gcc/common/config/riscv/riscv-common.cc +@@ -82,6 +82,10 @@ static const riscv_implied_info_t riscv_implied_info[] = + {"a", "zaamo"}, + {"a", "zalrsc"}, + ++ {"b", "zba"}, ++ {"b", "zbb"}, ++ {"b", "zbs"}, ++ + {"zdinx", "zfinx"}, + {"zfinx", "zicsr"}, + {"zdinx", "zicsr"}, +@@ -240,6 +244,8 @@ static const struct riscv_ext_version riscv_ext_version_table[] = + {"c", ISA_SPEC_CLASS_20190608, 2, 0}, + {"c", ISA_SPEC_CLASS_2P2, 2, 0}, + ++ {"b", ISA_SPEC_CLASS_NONE, 1, 0}, ++ + {"h", ISA_SPEC_CLASS_NONE, 1, 0}, + + {"v", ISA_SPEC_CLASS_NONE, 1, 0}, +@@ -397,6 +403,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] = + static const struct riscv_ext_version riscv_combine_info[] = + { + {"a", ISA_SPEC_CLASS_20191213, 2, 1}, ++ {"b", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zk", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zkn", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zks", ISA_SPEC_CLASS_NONE, 1, 0}, +diff --git a/gcc/config/riscv/arch-canonicalize b/gcc/config/riscv/arch-canonicalize +index 6c10d1aa81b..bb9dea42872 100755 +--- a/gcc/config/riscv/arch-canonicalize ++++ b/gcc/config/riscv/arch-canonicalize +@@ -42,6 +42,7 @@ IMPLIED_EXT = { + "d" : ["f", "zicsr"], + "a" : ["zaamo", "zalrsc"], + "f" : ["zicsr"], ++ "b" : ["zba", "zbb", "zbs"], + "zdinx" : ["zfinx", "zicsr"], + "zfinx" : ["zicsr"], + "zhinx" : ["zhinxmin", "zfinx", "zicsr"], +-- +2.50.1 + diff --git a/0011-RISC-V-Add-configure-check-for-B-extention-support.patch b/0011-RISC-V-Add-configure-check-for-B-extention-support.patch new file mode 100644 index 0000000..c79c727 --- /dev/null +++ b/0011-RISC-V-Add-configure-check-for-B-extention-support.patch @@ -0,0 +1,137 @@ +From 8e96c10c51effcb20b4c769df13f630d89d3c821 Mon Sep 17 00:00:00 2001 +From: Edwin Lu +Date: Wed, 24 Jul 2024 16:37:18 -0700 +Subject: [PATCH 11/29] RISC-V: Add configure check for B extention support + +Binutils 2.42 and before don't recognize the b extension in the march +strings even though it supports zba_zbb_zbs. Add a configure check to +ignore the b in the march string if found. + +gcc/ChangeLog: + + * common/config/riscv/riscv-common.cc (riscv_subset_list::to_string): + Skip b in march string + * config.in: Regenerate. + * configure: Regenerate. + * configure.ac: Add B assembler check + +Signed-off-by: Edwin Lu +(cherry picked from commit 7ef8a9d4b1cea3fea3791859074df79b71abd549) +--- + gcc/common/config/riscv/riscv-common.cc | 8 +++++++ + gcc/config.in | 6 +++++ + gcc/configure | 31 +++++++++++++++++++++++++ + gcc/configure.ac | 5 ++++ + 4 files changed, 50 insertions(+) + +diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc +index 00c73887e8c..9529cd92f5e 100644 +--- a/gcc/common/config/riscv/riscv-common.cc ++++ b/gcc/common/config/riscv/riscv-common.cc +@@ -831,6 +831,7 @@ riscv_subset_list::to_string (bool version_p) const + bool skip_zifencei = false; + bool skip_zaamo_zalrsc = false; + bool skip_zicsr = false; ++ bool skip_b = false; + bool i2p0 = false; + + /* For RISC-V ISA version 2.2 or earlier version, zicsr and zifencei is +@@ -861,6 +862,10 @@ riscv_subset_list::to_string (bool version_p) const + /* Skip since binutils 2.42 and earlier don't recognize zaamo/zalrsc. */ + skip_zaamo_zalrsc = true; + #endif ++#ifndef HAVE_AS_MARCH_B ++ /* Skip since binutils 2.42 and earlier don't recognize b. */ ++ skip_b = true; ++#endif + + for (subset = m_head; subset != NULL; subset = subset->next) + { +@@ -878,6 +883,9 @@ riscv_subset_list::to_string (bool version_p) const + if (skip_zaamo_zalrsc && subset->name == "zalrsc") + continue; + ++ if (skip_b && subset->name == "b") ++ continue; ++ + /* For !version_p, we only separate extension with underline for + multi-letter extension. */ + if (!first && +diff --git a/gcc/config.in b/gcc/config.in +index 21a7e12376b..c2dad93a53a 100644 +--- a/gcc/config.in ++++ b/gcc/config.in +@@ -629,6 +629,12 @@ + #endif + + ++/* Define if the assembler understands -march=rv*_b. */ ++#ifndef USED_FOR_TARGET ++#undef HAVE_AS_MARCH_B ++#endif ++ ++ + /* Define if the assembler understands -march=rv*_zaamo_zalrsc. */ + #ifndef USED_FOR_TARGET + #undef HAVE_AS_MARCH_ZAAMO_ZALRSC +diff --git a/gcc/configure b/gcc/configure +index c0dd02ffff5..ded2d1078e1 100755 +--- a/gcc/configure ++++ b/gcc/configure +@@ -31100,6 +31100,37 @@ if test $gcc_cv_as_riscv_march_zaamo_zalrsc = yes; then + + $as_echo "#define HAVE_AS_MARCH_ZAAMO_ZALRSC 1" >>confdefs.h + ++fi ++ ++ { $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for -march=rv32i_b support" >&5 ++$as_echo_n "checking assembler for -march=rv32i_b support... " >&6; } ++if ${gcc_cv_as_riscv_march_b+:} false; then : ++ $as_echo_n "(cached) " >&6 ++else ++ gcc_cv_as_riscv_march_b=no ++ if test x$gcc_cv_as != x; then ++ $as_echo '' > conftest.s ++ if { ac_try='$gcc_cv_as $gcc_cv_as_flags -march=rv32i_b -o conftest.o conftest.s >&5' ++ { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5 ++ (eval $ac_try) 2>&5 ++ ac_status=$? ++ $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 ++ test $ac_status = 0; }; } ++ then ++ gcc_cv_as_riscv_march_b=yes ++ else ++ echo "configure: failed program was" >&5 ++ cat conftest.s >&5 ++ fi ++ rm -f conftest.o conftest.s ++ fi ++fi ++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_as_riscv_march_b" >&5 ++$as_echo "$gcc_cv_as_riscv_march_b" >&6; } ++if test $gcc_cv_as_riscv_march_b = yes; then ++ ++$as_echo "#define HAVE_AS_MARCH_B 1" >>confdefs.h ++ + fi + + ;; +diff --git a/gcc/configure.ac b/gcc/configure.ac +index 09ffd6bca3c..f8e6e66b872 100644 +--- a/gcc/configure.ac ++++ b/gcc/configure.ac +@@ -5523,6 +5523,11 @@ configured with --enable-newlib-nano-formatted-io.]) + [-march=rv32i_zaamo_zalrsc],,, + [AC_DEFINE(HAVE_AS_MARCH_ZAAMO_ZALRSC, 1, + [Define if the assembler understands -march=rv*_zaamo_zalrsc.])]) ++ gcc_GAS_CHECK_FEATURE([-march=rv32i_b support], ++ gcc_cv_as_riscv_march_b, ++ [-march=rv32i_b],,, ++ [AC_DEFINE(HAVE_AS_MARCH_B, 1, ++ [Define if the assembler understands -march=rv*_b.])]) + ;; + loongarch*-*-*) + gcc_GAS_CHECK_FEATURE([.dtprelword support], +-- +2.50.1 + diff --git a/0012-RISC-V-c-implies-zca-and-conditionally-zcf-zcd.patch b/0012-RISC-V-c-implies-zca-and-conditionally-zcf-zcd.patch new file mode 100644 index 0000000..0cb5c12 --- /dev/null +++ b/0012-RISC-V-c-implies-zca-and-conditionally-zcf-zcd.patch @@ -0,0 +1,202 @@ +From 0c4e606e4dc50580968ae70b000474402b8b6695 Mon Sep 17 00:00:00 2001 +From: Fei Gao +Date: Wed, 10 Jul 2024 10:12:02 +0000 +Subject: [PATCH 12/29] RISC-V: c implies zca, and conditionally zcf & zcd + +According to Zc-1.0.4-3.pdf from +https://github.com/riscvarchive/riscv-code-size-reduction/releases/tag/v1.0.4-3 +The rule is that: +- C always implies Zca +- C+F implies Zcf (RV32 only) +- C+D implies Zcd + +Signed-off-by: Fei Gao +gcc/ChangeLog: + + * common/config/riscv/riscv-common.cc: + c implies zca, and conditionally zcf & zcd. + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/attribute-15.c: adapt TC. + * gcc.target/riscv/attribute-16.c: likewise. + * gcc.target/riscv/attribute-17.c: likewise. + * gcc.target/riscv/attribute-18.c: likewise. + * gcc.target/riscv/pr110696.c: likewise. + * gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c: likewise. + * gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c: likewise. + * gcc.target/riscv/rvv/base/pr114352-1.c: likewise. + * gcc.target/riscv/rvv/base/pr114352-3.c: likewise. + * gcc.target/riscv/arch-39.c: New test. + * gcc.target/riscv/arch-40.c: New test. + +(cherry picked from commit 36e5e409190e595638cec053ea034d20d5c74d6b) +--- + gcc/common/config/riscv/riscv-common.cc | 12 ++++++++++++ + gcc/testsuite/gcc.target/riscv/arch-39.c | 7 +++++++ + gcc/testsuite/gcc.target/riscv/arch-40.c | 7 +++++++ + gcc/testsuite/gcc.target/riscv/attribute-15.c | 2 +- + gcc/testsuite/gcc.target/riscv/attribute-16.c | 2 +- + gcc/testsuite/gcc.target/riscv/attribute-17.c | 2 +- + gcc/testsuite/gcc.target/riscv/attribute-18.c | 2 +- + gcc/testsuite/gcc.target/riscv/pr110696.c | 2 +- + .../riscv/rvv/base/abi-callee-saved-1-zcmp.c | 2 +- + .../riscv/rvv/base/abi-callee-saved-2-zcmp.c | 2 +- + gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c | 4 ++-- + gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c | 8 ++++---- + 12 files changed, 39 insertions(+), 13 deletions(-) + create mode 100644 gcc/testsuite/gcc.target/riscv/arch-39.c + create mode 100644 gcc/testsuite/gcc.target/riscv/arch-40.c + +diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc +index 9529cd92f5e..b0fe529d4e5 100644 +--- a/gcc/common/config/riscv/riscv-common.cc ++++ b/gcc/common/config/riscv/riscv-common.cc +@@ -82,6 +82,18 @@ static const riscv_implied_info_t riscv_implied_info[] = + {"a", "zaamo"}, + {"a", "zalrsc"}, + ++ {"c", "zca"}, ++ {"c", "zcf", ++ [] (const riscv_subset_list *subset_list) -> bool ++ { ++ return subset_list->xlen () == 32 && subset_list->lookup ("f"); ++ }}, ++ {"c", "zcd", ++ [] (const riscv_subset_list *subset_list) -> bool ++ { ++ return subset_list->lookup ("d"); ++ }}, ++ + {"b", "zba"}, + {"b", "zbb"}, + {"b", "zbs"}, +diff --git a/gcc/testsuite/gcc.target/riscv/arch-39.c b/gcc/testsuite/gcc.target/riscv/arch-39.c +new file mode 100644 +index 00000000000..beeb81e44c5 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/arch-39.c +@@ -0,0 +1,7 @@ ++/* { dg-do compile } */ ++/* { dg-options "-march=rv64idc_zcmt -mabi=lp64d" } */ ++int ++foo () ++{} ++ ++/* { dg-error "zcd conflicts with zcmt" "" { target *-*-* } 0 } */ +diff --git a/gcc/testsuite/gcc.target/riscv/arch-40.c b/gcc/testsuite/gcc.target/riscv/arch-40.c +new file mode 100644 +index 00000000000..eaefaf1d0d7 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/arch-40.c +@@ -0,0 +1,7 @@ ++/* { dg-do compile } */ ++/* { dg-options "-march=rv64idc_zcmp -mabi=lp64d" } */ ++int ++foo () ++{} ++ ++/* { dg-error "zcd conflicts with zcmp" "" { target *-*-* } 0 } */ +diff --git a/gcc/testsuite/gcc.target/riscv/attribute-15.c b/gcc/testsuite/gcc.target/riscv/attribute-15.c +index a2e394b6489..ac6caaecd4f 100644 +--- a/gcc/testsuite/gcc.target/riscv/attribute-15.c ++++ b/gcc/testsuite/gcc.target/riscv/attribute-15.c +@@ -3,4 +3,4 @@ + int foo() + { + } +-/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zaamo1p0_zalrsc1p0\"" } } */ ++/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0\"" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/attribute-16.c b/gcc/testsuite/gcc.target/riscv/attribute-16.c +index d2b18160cb5..539e426ca97 100644 +--- a/gcc/testsuite/gcc.target/riscv/attribute-16.c ++++ b/gcc/testsuite/gcc.target/riscv/attribute-16.c +@@ -3,4 +3,4 @@ + int foo() + { + } +-/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_m2p0_a2p0_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0\"" } } */ ++/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_m2p0_a2p0_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0\"" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/attribute-17.c b/gcc/testsuite/gcc.target/riscv/attribute-17.c +index fc2f488a3ac..30928cb5b68 100644 +--- a/gcc/testsuite/gcc.target/riscv/attribute-17.c ++++ b/gcc/testsuite/gcc.target/riscv/attribute-17.c +@@ -3,4 +3,4 @@ + int foo() + { + } +-/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0\"" } } */ ++/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0\"" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/attribute-18.c b/gcc/testsuite/gcc.target/riscv/attribute-18.c +index eefd602103d..9f7199f331a 100644 +--- a/gcc/testsuite/gcc.target/riscv/attribute-18.c ++++ b/gcc/testsuite/gcc.target/riscv/attribute-18.c +@@ -1,4 +1,4 @@ + /* { dg-do compile } */ + /* { dg-options "-mriscv-attribute -march=rv64imafdc -mabi=lp64d -misa-spec=2.2" } */ + int foo() {} +-/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zaamo1p0_zalrsc1p0\"" } } */ ++/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0\"" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/pr110696.c b/gcc/testsuite/gcc.target/riscv/pr110696.c +index 08682a047e0..aae2afc6b28 100644 +--- a/gcc/testsuite/gcc.target/riscv/pr110696.c ++++ b/gcc/testsuite/gcc.target/riscv/pr110696.c +@@ -4,4 +4,4 @@ int foo() + { + } + +-/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0\"" } } */ ++/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0\"" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c +index dedcef9b353..b6b708f1a58 100644 +--- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c ++++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* { dg-options "-O1 -march=rv64gcv_zfh_zca_zcmp -mabi=lp64d -fno-shrink-wrap-separate" } */ ++/* { dg-options "-O1 -march=rv64gv_zfh_zca_zcmp -mabi=lp64d -fno-shrink-wrap-separate" } */ + /* { dg-final { check-function-bodies "**" "" } } */ + + #include +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c +index 14fb2c400a4..5f8f96f86a9 100644 +--- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c ++++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* { dg-options "-O1 -march=rv64gcv_zfh_zca_zcmp -mabi=lp64d -fno-shrink-wrap-separate" } */ ++/* { dg-options "-O1 -march=rv64gv_zfh_zca_zcmp -mabi=lp64d -fno-shrink-wrap-separate" } */ + /* { dg-final { check-function-bodies "**" "" } } */ + + #include +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c +index faeb406498d..300d87324c6 100644 +--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c ++++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c +@@ -54,5 +54,5 @@ test_3 (int *a, int *b, int *out, unsigned count) + out[i] = a[i] + b[i]; + } + +-/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0\"" } } */ +-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */ ++/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0\"" } } */ ++/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c +index 38815ef5bd0..da7a44ba08a 100644 +--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c ++++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c +@@ -107,7 +107,7 @@ test_6 (_Float16 *a, _Float16 *b, _Float16 *out, unsigned count) + out[i] = a[i] + b[i]; + } + +-/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0\"" } } */ +-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */ +-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zbb1p0" } } */ +-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zfh1p0_zfhmin1p0" } } */ ++/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0\"" } } */ ++/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */ ++/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zbb1p0" } } */ ++/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zfh1p0_zfhmin1p0_zca1p0_zcd1p0" } } */ +-- +2.50.1 + diff --git a/0013-RISC-V-RISC-V-Add-implication-for-M-extension.patch b/0013-RISC-V-RISC-V-Add-implication-for-M-extension.patch new file mode 100644 index 0000000..85061ac --- /dev/null +++ b/0013-RISC-V-RISC-V-Add-implication-for-M-extension.patch @@ -0,0 +1,308 @@ +From b6bdb5115982d3a8cfb67a447375f85c9c805b4e Mon Sep 17 00:00:00 2001 +From: Tsung Chun Lin +Date: Tue, 29 Oct 2024 09:47:57 -0600 +Subject: [PATCH 13/29] [RISC-V] RISC-V: Add implication for M extension. + +That M implies Zmmul. + +gcc/ChangeLog: + + * common/config/riscv/riscv-common.cc: M implies Zmmul. + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/attribute-15.c: Add _zmmul1p0 to arch string. + * gcc.target/riscv/attribute-16.c: Ditto. + * gcc.target/riscv/attribute-17.c: Ditto. + * gcc.target/riscv/attribute-18.c: Ditto. + * gcc.target/riscv/attribute-19.c: Ditto. + * gcc.target/riscv/pr110696.c: Ditto. + * gcc.target/riscv/target-attr-01.c: Ditto. + * gcc.target/riscv/target-attr-02.c: Ditto. + * gcc.target/riscv/target-attr-03.c: Ditto. + * gcc.target/riscv/target-attr-04.c: Ditto. + * gcc.target/riscv/target-attr-08.c: Ditto. + * gcc.target/riscv/target-attr-11.c: Ditto. + * gcc.target/riscv/target-attr-14.c: Ditto. + * gcc.target/riscv/target-attr-15.c: Ditto. + * gcc.target/riscv/target-attr-16.c: Ditto. + * gcc.target/riscv/rvv/base/pr114352-1.c: Likewise. + * gcc.target/riscv/rvv/base/pr114352-3.c: Likewise. + * gcc.dg/pr90838.c: Fix search string for rv64. + + Co-Authored-By: Jeff Law + +(cherry picked from commit f003834badbfd9d0c0ad132de8b2f3d550ed120f) +--- + gcc/common/config/riscv/riscv-common.cc | 2 ++ + gcc/testsuite/gcc.dg/pr90838.c | 2 +- + gcc/testsuite/gcc.target/riscv/attribute-15.c | 2 +- + gcc/testsuite/gcc.target/riscv/attribute-16.c | 2 +- + gcc/testsuite/gcc.target/riscv/attribute-17.c | 2 +- + gcc/testsuite/gcc.target/riscv/attribute-18.c | 2 +- + gcc/testsuite/gcc.target/riscv/attribute-19.c | 2 +- + gcc/testsuite/gcc.target/riscv/pr110696.c | 2 +- + gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c | 4 ++-- + gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c | 8 ++++---- + gcc/testsuite/gcc.target/riscv/target-attr-01.c | 2 +- + gcc/testsuite/gcc.target/riscv/target-attr-02.c | 2 +- + gcc/testsuite/gcc.target/riscv/target-attr-03.c | 2 +- + gcc/testsuite/gcc.target/riscv/target-attr-04.c | 2 +- + gcc/testsuite/gcc.target/riscv/target-attr-08.c | 2 +- + gcc/testsuite/gcc.target/riscv/target-attr-11.c | 2 +- + gcc/testsuite/gcc.target/riscv/target-attr-14.c | 4 ++-- + gcc/testsuite/gcc.target/riscv/target-attr-15.c | 4 ++-- + gcc/testsuite/gcc.target/riscv/target-attr-16.c | 4 ++-- + 19 files changed, 27 insertions(+), 25 deletions(-) + +diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc +index b0fe529d4e5..c870b5f4fed 100644 +--- a/gcc/common/config/riscv/riscv-common.cc ++++ b/gcc/common/config/riscv/riscv-common.cc +@@ -75,6 +75,8 @@ struct riscv_implied_info_t + /* Implied ISA info, must end with NULL sentinel. */ + static const riscv_implied_info_t riscv_implied_info[] = + { ++ {"m", "zmmul"}, ++ + {"d", "f"}, + {"f", "zicsr"}, + {"d", "zicsr"}, +diff --git a/gcc/testsuite/gcc.dg/pr90838.c b/gcc/testsuite/gcc.dg/pr90838.c +index 40aad70499d..db7bcec3ea9 100644 +--- a/gcc/testsuite/gcc.dg/pr90838.c ++++ b/gcc/testsuite/gcc.dg/pr90838.c +@@ -77,7 +77,7 @@ int ctz4 (unsigned long x) + /* { dg-final { scan-assembler-times "ctz\t" 1 { target { rv64 } } } } */ + /* { dg-final { scan-assembler-times "ctzw\t" 3 { target { rv64 } } } } */ + /* { dg-final { scan-assembler-times "andi\t" 2 { target { rv64 } } } } */ +-/* { dg-final { scan-assembler-not "mul" { target { rv64 } } } } */ ++/* { dg-final { scan-assembler-not "mul\t" { target { rv64 } } } } */ + + /* { dg-final { scan-tree-dump-times {= \.CTZ} 3 "forwprop2" { target { rv32 } } } } */ + /* { dg-final { scan-assembler-times "ctz\t" 3 { target { rv32 } } } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/attribute-15.c b/gcc/testsuite/gcc.target/riscv/attribute-15.c +index ac6caaecd4f..d7a70e86aa1 100644 +--- a/gcc/testsuite/gcc.target/riscv/attribute-15.c ++++ b/gcc/testsuite/gcc.target/riscv/attribute-15.c +@@ -3,4 +3,4 @@ + int foo() + { + } +-/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0\"" } } */ ++/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0\"" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/attribute-16.c b/gcc/testsuite/gcc.target/riscv/attribute-16.c +index 539e426ca97..4818cbe90d4 100644 +--- a/gcc/testsuite/gcc.target/riscv/attribute-16.c ++++ b/gcc/testsuite/gcc.target/riscv/attribute-16.c +@@ -3,4 +3,4 @@ + int foo() + { + } +-/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_m2p0_a2p0_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0\"" } } */ ++/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_m2p0_a2p0_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0\"" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/attribute-17.c b/gcc/testsuite/gcc.target/riscv/attribute-17.c +index 30928cb5b68..64b11b6a28c 100644 +--- a/gcc/testsuite/gcc.target/riscv/attribute-17.c ++++ b/gcc/testsuite/gcc.target/riscv/attribute-17.c +@@ -3,4 +3,4 @@ + int foo() + { + } +-/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0\"" } } */ ++/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0\"" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/attribute-18.c b/gcc/testsuite/gcc.target/riscv/attribute-18.c +index 9f7199f331a..43ae37b5089 100644 +--- a/gcc/testsuite/gcc.target/riscv/attribute-18.c ++++ b/gcc/testsuite/gcc.target/riscv/attribute-18.c +@@ -1,4 +1,4 @@ + /* { dg-do compile } */ + /* { dg-options "-mriscv-attribute -march=rv64imafdc -mabi=lp64d -misa-spec=2.2" } */ + int foo() {} +-/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0\"" } } */ ++/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0\"" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/attribute-19.c b/gcc/testsuite/gcc.target/riscv/attribute-19.c +index 8150452f5b1..c9301589a19 100644 +--- a/gcc/testsuite/gcc.target/riscv/attribute-19.c ++++ b/gcc/testsuite/gcc.target/riscv/attribute-19.c +@@ -1,4 +1,4 @@ + /* { dg-do compile } */ + /* { dg-options "-mriscv-attribute -march=rv64im -mabi=lp64 -misa-spec=2.2" } */ + int foo() {} +-/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p0_m2p0\"" } } */ ++/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p0_m2p0_zmmul1p0\"" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/pr110696.c b/gcc/testsuite/gcc.target/riscv/pr110696.c +index aae2afc6b28..8fb373d6c6b 100644 +--- a/gcc/testsuite/gcc.target/riscv/pr110696.c ++++ b/gcc/testsuite/gcc.target/riscv/pr110696.c +@@ -4,4 +4,4 @@ int foo() + { + } + +-/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0\"" } } */ ++/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0\"" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c +index 300d87324c6..c21be05889e 100644 +--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c ++++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c +@@ -54,5 +54,5 @@ test_3 (int *a, int *b, int *out, unsigned count) + out[i] = a[i] + b[i]; + } + +-/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0\"" } } */ +-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */ ++/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0\"" } } */ ++/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c +index da7a44ba08a..a764afbbbc1 100644 +--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c ++++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c +@@ -107,7 +107,7 @@ test_6 (_Float16 *a, _Float16 *b, _Float16 *out, unsigned count) + out[i] = a[i] + b[i]; + } + +-/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0\"" } } */ +-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */ +-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zbb1p0" } } */ +-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zfh1p0_zfhmin1p0_zca1p0_zcd1p0" } } */ ++/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0\"" } } */ ++/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" } } */ ++/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zbb1p0" } } */ ++/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zfh1p0_zfhmin1p0_zca1p0_zcd1p0" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/target-attr-01.c b/gcc/testsuite/gcc.target/riscv/target-attr-01.c +index 4748f6a08e7..9830ab2f1b6 100644 +--- a/gcc/testsuite/gcc.target/riscv/target-attr-01.c ++++ b/gcc/testsuite/gcc.target/riscv/target-attr-01.c +@@ -9,7 +9,7 @@ + ** sh1add\s*a0,a1,a0 + ** ... + */ +-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zba1p0" } } */ ++/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0" } } */ + long foo () __attribute__((target("arch=rv64gc_zba"))); + long foo (long a, long b) + { +diff --git a/gcc/testsuite/gcc.target/riscv/target-attr-02.c b/gcc/testsuite/gcc.target/riscv/target-attr-02.c +index 9ebf16e3675..3338ae46942 100644 +--- a/gcc/testsuite/gcc.target/riscv/target-attr-02.c ++++ b/gcc/testsuite/gcc.target/riscv/target-attr-02.c +@@ -9,7 +9,7 @@ + ** sh1add\s*a0,a1,a0 + ** ... + */ +-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zba1p0" } } */ ++/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0" } } */ + long foo () __attribute__((target("arch=+zba"))); + long foo (long a, long b) + { +diff --git a/gcc/testsuite/gcc.target/riscv/target-attr-03.c b/gcc/testsuite/gcc.target/riscv/target-attr-03.c +index 1cba2c25744..673c0670106 100644 +--- a/gcc/testsuite/gcc.target/riscv/target-attr-03.c ++++ b/gcc/testsuite/gcc.target/riscv/target-attr-03.c +@@ -10,7 +10,7 @@ + ** add\s*a0,a1,a0 + ** ... + */ +-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0" } } */ ++/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0" } } */ + long foo () __attribute__((target("arch=rv64gc"))); + long foo (long a, long b) + { +diff --git a/gcc/testsuite/gcc.target/riscv/target-attr-04.c b/gcc/testsuite/gcc.target/riscv/target-attr-04.c +index 1193dcfa30e..58c1698fac3 100644 +--- a/gcc/testsuite/gcc.target/riscv/target-attr-04.c ++++ b/gcc/testsuite/gcc.target/riscv/target-attr-04.c +@@ -12,7 +12,7 @@ + ** add\s*a0,a1,a0 + ** ... + */ +-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0" } } */ ++/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zmmul1p0_zaamo1p0_zalrsc1p0" } } */ + long foo () __attribute__((target("cpu=sifive-u74"))); + long foo (long a, long b) + { +diff --git a/gcc/testsuite/gcc.target/riscv/target-attr-08.c b/gcc/testsuite/gcc.target/riscv/target-attr-08.c +index e7792c1598e..3cab5ff803c 100644 +--- a/gcc/testsuite/gcc.target/riscv/target-attr-08.c ++++ b/gcc/testsuite/gcc.target/riscv/target-attr-08.c +@@ -13,7 +13,7 @@ __attribute__((target("arch=rv64gc_zba"))); + ** sh1add\s*a0,a1,a0 + ** ... + */ +-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zba1p0" } } */ ++/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0" } } */ + long foo (long a, long b) + { + return a + (b * 2); +diff --git a/gcc/testsuite/gcc.target/riscv/target-attr-11.c b/gcc/testsuite/gcc.target/riscv/target-attr-11.c +index 6e02a98f120..0a215b4ae9c 100644 +--- a/gcc/testsuite/gcc.target/riscv/target-attr-11.c ++++ b/gcc/testsuite/gcc.target/riscv/target-attr-11.c +@@ -15,7 +15,7 @@ __attribute__((target("arch=rv64gc_zba"))); + ** sh1add\s*a0,a1,a0 + ** ... + */ +-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zba1p0" } } */ ++/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0" } } */ + long foo (long a, long b) + { + return a + (b * 2); +diff --git a/gcc/testsuite/gcc.target/riscv/target-attr-14.c b/gcc/testsuite/gcc.target/riscv/target-attr-14.c +index 59de060eec3..4e615dbb323 100644 +--- a/gcc/testsuite/gcc.target/riscv/target-attr-14.c ++++ b/gcc/testsuite/gcc.target/riscv/target-attr-14.c +@@ -9,7 +9,7 @@ + ** sh1add\s*a0,a1,a0 + ** ... + */ +-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zba1p0" } } */ ++/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0" } } */ + long foo () __attribute__((target("arch=rv64gc_zba"))); + long foo (long a, long b) + { +@@ -34,7 +34,7 @@ long bar (long a, long b) + ** th.addsl\s*a0,a0,a1,1 + ** ... + */ +-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_xtheadba1p0" } } */ ++/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_xtheadba1p0" } } */ + long foo_th () __attribute__((target("arch=rv64gc_xtheadba"))); + long foo_th (long a, long b) + { +diff --git a/gcc/testsuite/gcc.target/riscv/target-attr-15.c b/gcc/testsuite/gcc.target/riscv/target-attr-15.c +index 5120ad7b1d6..bccb81aaad9 100644 +--- a/gcc/testsuite/gcc.target/riscv/target-attr-15.c ++++ b/gcc/testsuite/gcc.target/riscv/target-attr-15.c +@@ -9,7 +9,7 @@ + ** sh1add\s*a0,a1,a0 + ** ... + */ +-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zba1p0" } } */ ++/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0" } } */ + long foo () __attribute__((target("arch=rv64gc_zba"))); + long foo (long a, long b) + { +@@ -34,7 +34,7 @@ long bar (long a, long b) + ** th.addsl\s*a0,a0,a1,1 + ** ... + */ +-/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_xtheadba1p0" } } */ ++/* { dg-final { scan-assembler ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_xtheadba1p0" } } */ + long foo_th () __attribute__((target("arch=+xtheadba"))); + long foo_th (long a, long b) + { +diff --git a/gcc/testsuite/gcc.target/riscv/target-attr-16.c b/gcc/testsuite/gcc.target/riscv/target-attr-16.c +index 42b8cbe0f23..f997ae8a9d1 100644 +--- a/gcc/testsuite/gcc.target/riscv/target-attr-16.c ++++ b/gcc/testsuite/gcc.target/riscv/target-attr-16.c +@@ -24,5 +24,5 @@ void bar (void) + { + } + +-/* { dg-final { scan-assembler-times ".option arch, rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zba1p0_zbb1p0" 4 { target { rv32 } } } } */ +-/* { dg-final { scan-assembler-times ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zba1p0_zbb1p0" 4 { target { rv64 } } } } */ ++/* { dg-final { scan-assembler-times ".option arch, rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0_zba1p0_zbb1p0" 4 { target { rv32 } } } } */ ++/* { dg-final { scan-assembler-times ".option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0_zbb1p0" 4 { target { rv64 } } } } */ +-- +2.50.1 + diff --git a/0014-RISC-V-Minimal-support-for-Zimop-extension.patch b/0014-RISC-V-Minimal-support-for-Zimop-extension.patch new file mode 100644 index 0000000..f15c98d --- /dev/null +++ b/0014-RISC-V-Minimal-support-for-Zimop-extension.patch @@ -0,0 +1,106 @@ +From a741289416dbb26cc323542a4813eaf196e0b46f Mon Sep 17 00:00:00 2001 +From: Jiawei +Date: Fri, 2 Aug 2024 23:23:14 +0800 +Subject: [PATCH 14/29] RISC-V: Minimal support for Zimop extension. + +This patch support Zimop and Zcmop extension[1].To enable GCC to recognize +and process Zimop and Zcmop extension correctly at compile time. + +https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc + +gcc/ChangeLog: + + * common/config/riscv/riscv-common.cc: New extension. + * config/riscv/riscv.opt: New mask. + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/arch-42.c: New test. + * gcc.target/riscv/arch-43.c: New test. + +(cherry picked from commit c8f3fdd53871a20838be532b58ef610bf1dd75e1) +--- + gcc/common/config/riscv/riscv-common.cc | 8 ++++++++ + gcc/config/riscv/riscv.opt | 7 +++++++ + gcc/testsuite/gcc.target/riscv/arch-42.c | 5 +++++ + gcc/testsuite/gcc.target/riscv/arch-43.c | 5 +++++ + 4 files changed, 25 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/riscv/arch-42.c + create mode 100644 gcc/testsuite/gcc.target/riscv/arch-43.c + +diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc +index c870b5f4fed..7df302d8586 100644 +--- a/gcc/common/config/riscv/riscv-common.cc ++++ b/gcc/common/config/riscv/riscv-common.cc +@@ -100,6 +100,8 @@ static const riscv_implied_info_t riscv_implied_info[] = + {"b", "zbb"}, + {"b", "zbs"}, + ++ {"zcmop", "zca"}, ++ + {"zdinx", "zfinx"}, + {"zfinx", "zicsr"}, + {"zdinx", "zicsr"}, +@@ -311,6 +313,9 @@ static const struct riscv_ext_version riscv_ext_version_table[] = + {"zicclsm", ISA_SPEC_CLASS_NONE, 1, 0}, + {"ziccrse", ISA_SPEC_CLASS_NONE, 1, 0}, + ++ {"zimop", ISA_SPEC_CLASS_NONE, 1, 0}, ++ {"zcmop", ISA_SPEC_CLASS_NONE, 1, 0}, ++ + {"zicntr", ISA_SPEC_CLASS_NONE, 2, 0}, + {"zihpm", ISA_SPEC_CLASS_NONE, 2, 0}, + +@@ -1612,6 +1617,9 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = + {"zicbop", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOP}, + {"zic64b", &gcc_options::x_riscv_zicmo_subext, MASK_ZIC64B}, + ++ {"zimop", &gcc_options::x_riscv_mop_subext, MASK_ZIMOP}, ++ {"zcmop", &gcc_options::x_riscv_mop_subext, MASK_ZCMOP}, ++ + {"zve32x", &gcc_options::x_target_flags, MASK_VECTOR}, + {"zve32f", &gcc_options::x_target_flags, MASK_VECTOR}, + {"zve64x", &gcc_options::x_target_flags, MASK_VECTOR}, +diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt +index 8e6cba27066..dea339a24d3 100644 +--- a/gcc/config/riscv/riscv.opt ++++ b/gcc/config/riscv/riscv.opt +@@ -394,6 +394,13 @@ Mask(ZICBOP) Var(riscv_zicmo_subext) + + Mask(ZIC64B) Var(riscv_zicmo_subext) + ++TargetVariable ++int riscv_mop_subext ++ ++Mask(ZIMOP) Var(riscv_mop_subext) ++ ++Mask(ZCMOP) Var(riscv_mop_subext) ++ + TargetVariable + int riscv_zf_subext + +diff --git a/gcc/testsuite/gcc.target/riscv/arch-42.c b/gcc/testsuite/gcc.target/riscv/arch-42.c +new file mode 100644 +index 00000000000..83f78d28dbe +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/arch-42.c +@@ -0,0 +1,5 @@ ++/* { dg-do compile } */ ++/* { dg-options "-march=rv64i_zimop -mabi=lp64" } */ ++int foo() ++{ ++} +diff --git a/gcc/testsuite/gcc.target/riscv/arch-43.c b/gcc/testsuite/gcc.target/riscv/arch-43.c +new file mode 100644 +index 00000000000..4a300a165fd +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/arch-43.c +@@ -0,0 +1,5 @@ ++/* { dg-do compile } */ ++/* { dg-options "-march=rv64i_zcmop -mabi=lp64" } */ ++int foo() ++{ ++} +-- +2.50.1 + diff --git a/gcc-14.spec b/gcc-14.spec index 9f213c9..8a9f2f4 100644 --- a/gcc-14.spec +++ b/gcc-14.spec @@ -90,7 +90,7 @@ Summary: Various compilers (C, C++, Objective-C, ...) Name: %{?_scl_prefix}gcc%{gcc_ver} Version: 14.3.1 -Release: 3 +Release: 4 # libgcc, libgfortran, libgomp, libstdc++ and crtstuff have # GCC Runtime Exception. License: GPLv3+ and GPLv3+ with exceptions and GPLv2+ with exceptions and LGPLv2+ and BSD @@ -175,6 +175,20 @@ Patch1004: GCC14-1004-riscv-lib64.patch Patch1005: GCC14-1005-libstdc-compat-Update-symbol-list-for-RISC-V-64.patch Patch1006: GCC14-1006-Add-multi-version-lto-symbol-parse-cross-lto-units-i.patch Patch1007: GCC14-1007-Add-hip09-machine-discribtion.patch +Patch1008: 0001-RISC-V-Add-basic-Zaamo-and-Zalrsc-support.patch +Patch1009: 0002-RISC-V-Use-widening-shift-for-scatter-gather-if-appl.patch +Patch1010: 0003-RISC-V-Add-Zalrsc-and-Zaamo-testsuite-support.patch +Patch1011: 0004-RISC-V-Add-Zalrsc-amo-op-patterns.patch +Patch1012: 0005-RISC-V-Move-amo-tests-into-subfolder.patch +Patch1013: 0006-RISC-V-Fix-amoadd-call-arguments.patch +Patch1014: 0007-RISC-V-Add-configure-check-for-Zaamo-Zalrsc-assemble.patch +Patch1015: 0008-RISC-V-Promote-Zaamo-Zalrsc-to-a-when-using-an-old-b.patch +Patch1016: 0009-RISC-V-Rename-amo-testcases.patch +Patch1017: 0010-RISC-V-Add-support-for-B-standard-extension.patch +Patch1018: 0011-RISC-V-Add-configure-check-for-B-extention-support.patch +Patch1019: 0012-RISC-V-c-implies-zca-and-conditionally-zcf-zcd.patch +Patch1020: 0013-RISC-V-RISC-V-Add-implication-for-M-extension.patch +Patch1021: 0014-RISC-V-Minimal-support-for-Zimop-extension.patch # On ARM EABI systems, we do want -gnueabi to be part of the # target triple. @@ -2205,6 +2219,9 @@ end %doc rpm.doc/changelogs/libcc1/ChangeLog* %changelog +* Fri Aug 01 2025 jchzhou - 14.3.1-4 +- Backport RISC-V RVA23 support, phase 1 + * Tue Jul 22 2025 huang-xiaoquan - 14.3.1-3 - [Sync] Sync hip09 -- Gitee