From aba7bd2037ddb53b268c0cf0334e4698f51e12b0 Mon Sep 17 00:00:00 2001 From: jchzhou Date: Tue, 26 Aug 2025 14:49:11 +0800 Subject: [PATCH] backport RISC-V RVA23 support, phase 2 Signed-off-by: Yunqiang Su Signed-off-by: jchzhou --- ...RISC-V-Support-RISC-V-Profiles-20-22.patch | 282 ++++++++++++++++++ 0016-RISC-V-Support-RISC-V-Profiles-23.patch | 94 ++++++ ...te-Fix-RISC-V-arch-52.c-format-issue.patch | 31 ++ ...Recognized-svadu-and-svade-extension.patch | 114 +++++++ ...gmented-hypervisor-series-extensions.patch | 164 ++++++++++ ...ly-zicsr-for-svade-and-svadu-extensi.patch | 35 +++ 0021-RISC-V-Support-Ssccptr-extension.patch | 85 ++++++ ...ISC-V-Support-Sscounterenw-extension.patch | 90 ++++++ 0023-RISC-V-Support-Sstvala-extension.patch | 90 ++++++ 0024-RISC-V-Support-Sstvecd-extension.patch | 90 ++++++ 0025-RISC-V-Support-Ssu64xl-extension.patch | 89 ++++++ ...upport-for-ssnpm-smnpm-and-smmpm-ext.patch | 180 +++++++++++ ...ISC-V-Update-Profiles-string-in-RV23.patch | 58 ++++ ...SC-V-Add-Profiles-RVA-B23S64-support.patch | 102 +++++++ ...PATCH-v2-RISC-V-Add-svbare-extension.patch | 94 ++++++ gcc-14.spec | 20 +- 16 files changed, 1617 insertions(+), 1 deletion(-) create mode 100644 0015-RISC-V-Support-RISC-V-Profiles-20-22.patch create mode 100644 0016-RISC-V-Support-RISC-V-Profiles-23.patch create mode 100644 0017-testsuite-Fix-RISC-V-arch-52.c-format-issue.patch create mode 100644 0018-PATCH-RISC-V-Recognized-svadu-and-svade-extension.patch create mode 100644 0019-RISC-V-Add-augmented-hypervisor-series-extensions.patch create mode 100644 0020-PATCH-RISC-V-Imply-zicsr-for-svade-and-svadu-extensi.patch create mode 100644 0021-RISC-V-Support-Ssccptr-extension.patch create mode 100644 0022-RISC-V-Support-Sscounterenw-extension.patch create mode 100644 0023-RISC-V-Support-Sstvala-extension.patch create mode 100644 0024-RISC-V-Support-Sstvecd-extension.patch create mode 100644 0025-RISC-V-Support-Ssu64xl-extension.patch create mode 100644 0026-RISC-V-Minimal-support-for-ssnpm-smnpm-and-smmpm-ext.patch create mode 100644 0027-RISC-V-Update-Profiles-string-in-RV23.patch create mode 100644 0028-RISC-V-Add-Profiles-RVA-B23S64-support.patch create mode 100644 0029-PATCH-v2-RISC-V-Add-svbare-extension.patch diff --git a/0015-RISC-V-Support-RISC-V-Profiles-20-22.patch b/0015-RISC-V-Support-RISC-V-Profiles-20-22.patch new file mode 100644 index 0000000..6f35cf6 --- /dev/null +++ b/0015-RISC-V-Support-RISC-V-Profiles-20-22.patch @@ -0,0 +1,282 @@ +From 0754babe4daf572d862304f6be7c4d7aab80f6c5 Mon Sep 17 00:00:00 2001 +From: Jiawei +Date: Sat, 10 May 2025 20:25:52 +0800 +Subject: [PATCH 15/29] RISC-V: Support RISC-V Profiles 20/22. + +This patch introduces support for RISC-V Profiles RV20 and RV22 [1], +enabling developers to utilize these profiles through the -march option. + +[1] https://github.com/riscv/riscv-profiles/releases/tag/v1.0 + +Version log: +Using lowercase letters to present Profiles. +Using '_' as divsor between Profiles and other RISC-V extension. +Add descriptions in invoke.texi. +Checking if there exist '_' between Profiles and additional extensions. +Using std::string to avoid memory problems. + +gcc/ChangeLog: + + * common/config/riscv/riscv-common.cc (struct riscv_profiles): New struct. + (riscv_subset_list::parse_profiles): New parser. + (riscv_subset_list::parse_base_ext): Ditto. + * config/riscv/riscv-subset.h: New def. + * doc/invoke.texi: New option descriptions. + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/arch-49.c: New test. + * gcc.target/riscv/arch-50.c: New test. + * gcc.target/riscv/arch-51.c: New test. + * gcc.target/riscv/arch-52.c: New test. + +(cherry picked from commit 43b450e3f72a53c744e77f55393962f1d349373a) +--- + gcc/common/config/riscv/riscv-common.cc | 85 +++++++++++++++++++++++- + gcc/config/riscv/riscv-subset.h | 2 + + gcc/doc/invoke.texi | 17 +++-- + gcc/testsuite/gcc.target/riscv/arch-49.c | 5 ++ + gcc/testsuite/gcc.target/riscv/arch-50.c | 12 ++++ + gcc/testsuite/gcc.target/riscv/arch-51.c | 12 ++++ + gcc/testsuite/gcc.target/riscv/arch-52.c | 6 ++ + 7 files changed, 130 insertions(+), 9 deletions(-) + create mode 100644 gcc/testsuite/gcc.target/riscv/arch-49.c + create mode 100644 gcc/testsuite/gcc.target/riscv/arch-50.c + create mode 100644 gcc/testsuite/gcc.target/riscv/arch-51.c + create mode 100644 gcc/testsuite/gcc.target/riscv/arch-52.c + +diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc +index 7df302d8586..ce62bdfe39b 100644 +--- a/gcc/common/config/riscv/riscv-common.cc ++++ b/gcc/common/config/riscv/riscv-common.cc +@@ -228,6 +228,12 @@ struct riscv_ext_version + int minor_version; + }; + ++struct riscv_profiles ++{ ++ const char *profile_name; ++ const char *profile_string; ++}; ++ + /* All standard extensions defined in all supported ISA spec. */ + static const struct riscv_ext_version riscv_ext_version_table[] = + { +@@ -436,6 +442,31 @@ static const struct riscv_ext_version riscv_combine_info[] = + {NULL, ISA_SPEC_CLASS_NONE, 0, 0} + }; + ++/* This table records the mapping form RISC-V Profiles into march string. */ ++static const riscv_profiles riscv_profiles_table[] = ++{ ++ /* RVI20U only contains the base extension 'i' as mandatory extension. */ ++ {"rvi20u64", "rv64i"}, ++ {"rvi20u32", "rv32i"}, ++ ++ /* RVA20U contains the 'i,m,a,f,d,c,zicsr,zicntr,ziccif,ziccrse,ziccamoa, ++ zicclsm,za128rs' as mandatory extensions. */ ++ {"rva20u64", "rv64imafdc_zicsr_zicntr_ziccif_ziccrse_ziccamoa" ++ "_zicclsm_za128rs"}, ++ ++ /* RVA22U contains the 'i,m,a,f,d,c,zicsr,zihintpause,zba,zbb,zbs,zicntr, ++ zihpm,ziccif,ziccrse,ziccamoa, zicclsm,zic64b,za64rs,zicbom,zicbop,zicboz, ++ zfhmin,zkt' as mandatory extensions. */ ++ {"rva22u64", "rv64imafdc_zicsr_zicntr_ziccif_ziccrse_ziccamoa" ++ "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop" ++ "_zicboz_zfhmin_zkt"}, ++ ++ /* Currently we do not define S/M mode Profiles in gcc part. */ ++ ++ /* Terminate the list. */ ++ {NULL, NULL} ++}; ++ + static const riscv_cpu_info riscv_cpu_tables[] = + { + #define RISCV_CORE(CORE_NAME, ARCH, TUNE) \ +@@ -1041,6 +1072,52 @@ riscv_subset_list::parsing_subset_version (const char *ext, + return p; + } + ++/* Parsing RISC-V Profiles in -march string. ++ Return string with mandatory extensions of Profiles. */ ++std::string ++riscv_subset_list::parse_profiles (const char *arch) ++{ ++ /* Checking if input string contains a Profiles. ++ There are two cases use Profiles in -march option: ++ ++ 1. Only use Profiles in '-march' as input ++ 2. Mixed Profiles with other extensions ++ ++ Use '_' to split Profiles and other extension. */ ++ std::string p(arch); ++ const size_t p_len = p.size(); ++ ++ for (int i = 0; riscv_profiles_table[i].profile_name != nullptr; ++i) ++ { ++ const std::string& p_name = riscv_profiles_table[i].profile_name; ++ const std::string& p_str = riscv_profiles_table[i].profile_string; ++ size_t pos = p.find(p_name); ++ /* Find profile at the begin. */ ++ if (pos == 0 && pos + p_name.size() <= p_len) ++ { ++ size_t after_pos = pos + p_name.size(); ++ std::string after_part = p.substr(after_pos); ++ ++ /* If there're only profile, return the profile_string directly. */ ++ if (after_part[0] == '\0') ++ return p_str; ++ ++ /* If isn't '_' after profile, need to add it and mention the user. */ ++ if (after_part[0] != '_') ++ { ++ warning_at (m_loc, 0, "Should use \"%c\" to contact Profiles with other " ++ "extensions", '_'); ++ return p_str + "_" + after_part; ++ } ++ ++ /* Return 'profiles_additional' extensions. */ ++ return p_str + after_part; ++ } ++ } ++ /* Not found profile, return directly. */ ++ return p; ++} ++ + /* Parsing function for base extensions, rv[32|64][i|e|g] + + Return Value: +@@ -1067,8 +1144,8 @@ riscv_subset_list::parse_base_ext (const char *p) + } + else + { +- error_at (m_loc, "%<-march=%s%>: ISA string must begin with rv32 or rv64", +- m_arch); ++ error_at (m_loc, "%<-march=%s%>: ISA string must begin with rv32, rv64 " ++ "or Profiles", m_arch); + return NULL; + } + +@@ -1459,8 +1536,10 @@ riscv_subset_list::parse (const char *arch, location_t loc) + return NULL; + + riscv_subset_list *subset_list = new riscv_subset_list (arch, loc); ++ + const char *p = arch; +- p = subset_list->parse_base_ext (p); ++ std::string a = subset_list->parse_profiles(p); ++ p = subset_list->parse_base_ext (a.c_str()); + if (p == NULL) + goto fail; + +diff --git a/gcc/config/riscv/riscv-subset.h b/gcc/config/riscv/riscv-subset.h +index 4d2bf9d9201..a0f542331aa 100644 +--- a/gcc/config/riscv/riscv-subset.h ++++ b/gcc/config/riscv/riscv-subset.h +@@ -80,6 +80,8 @@ private: + const char *parse_single_multiletter_ext (const char *, const char *, + const char *, bool); + ++ std::string parse_profiles (const char*); ++ + void handle_implied_ext (const char *); + bool check_implied_ext (); + void handle_combine_ext (); +diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi +index 64728fead51..6f80bfad6af 100644 +--- a/gcc/doc/invoke.texi ++++ b/gcc/doc/invoke.texi +@@ -1245,7 +1245,7 @@ See RS/6000 and PowerPC Options. + -mfdiv -mno-fdiv + -mdiv -mno-div + -misa-spec=@var{ISA-spec-string} +--march=@var{ISA-string} ++-march=@var{ISA-string|Profiles|Profiles_ISA-string} + -mtune=@var{processor-string} + -mpreferred-stack-boundary=@var{num} + -msmall-data-limit=@var{N-bytes} +@@ -30493,11 +30493,16 @@ The default is @option{-misa-spec=20191213} unless GCC has been configured + with @option{--with-isa-spec=} specifying a different default version. + + @opindex march +-@item -march=@var{ISA-string} +-Generate code for given RISC-V ISA (e.g.@: @samp{rv64im}). ISA strings must be +-lower-case. Examples include @samp{rv64i}, @samp{rv32g}, @samp{rv32e}, and +-@samp{rv32imaf}. Additionally, a special value @option{help} +-(@option{-march=help}) is accepted to list all supported extensions. ++@item -march=@var{ISA-string|Profiles|Profile_ISA-string} ++Generate code for given RISC-V ISA or Profiles or a combination of them ++(e.g.@: @samp{rv64im} @samp{rvi20u64} @samp{rvi20u64_zbb}). ISA strings and ++Profiles must be lower-case. Examples include @samp{rv64i}, @samp{rv32g}, ++@samp{rv32e}, @samp{rv32imaf}, @samp{rva22u64} and @samp{rva23u64}. ++To combine Profiles and optional RISC-V ISA extention, the profile should start ++at the beginning of the option, then use underline connect ISA-string (e.g.@: ++@samp{rvi20u64_zca_zcb} @samp{rva23u64_zacas}). Additionally, a special value ++@option{help} (@option{-march=help}) is accepted to list all supported ++extensions. + + The syntax of the ISA string is defined as follows: + +diff --git a/gcc/testsuite/gcc.target/riscv/arch-49.c b/gcc/testsuite/gcc.target/riscv/arch-49.c +new file mode 100644 +index 00000000000..6b86ae9fb3f +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/arch-49.c +@@ -0,0 +1,5 @@ ++/* { dg-do compile } */ ++/* { dg-options "-march=rvi20u64 -mabi=lp64" } */ ++int ++foo () ++{} +diff --git a/gcc/testsuite/gcc.target/riscv/arch-50.c b/gcc/testsuite/gcc.target/riscv/arch-50.c +new file mode 100644 +index 00000000000..072180d4f1f +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/arch-50.c +@@ -0,0 +1,12 @@ ++/* { dg-do compile } */ ++/* { dg-options "-march=rvi20u64_mafdc -mabi=lp64d" } */ ++#if !(defined __riscv_mul) || \ ++ !(defined __riscv_atomic) || \ ++ !(defined __riscv_flen) || \ ++ !(defined __riscv_div) || \ ++ !(defined __riscv_compressed) ++#error "Feature macros not defined" ++#endif ++int ++foo () ++{} +diff --git a/gcc/testsuite/gcc.target/riscv/arch-51.c b/gcc/testsuite/gcc.target/riscv/arch-51.c +new file mode 100644 +index 00000000000..5af983cbca9 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/arch-51.c +@@ -0,0 +1,12 @@ ++/* { dg-do compile } */ ++/* { dg-options "-march=rva20u64 -mabi=lp64d" } */ ++#if !(defined __riscv_mul) || \ ++ !(defined __riscv_atomic) || \ ++ !(defined __riscv_flen) || \ ++ !(defined __riscv_div) || \ ++ !(defined __riscv_compressed) ++#error "Feature macros not defined" ++#endif ++int ++foo () ++{} +diff --git a/gcc/testsuite/gcc.target/riscv/arch-52.c b/gcc/testsuite/gcc.target/riscv/arch-52.c +new file mode 100644 +index 00000000000..da6aea8fd94 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/arch-52.c +@@ -0,0 +1,6 @@ ++/* { dg-do compile } */ ++/* { dg-options "-march=rva22u64v -mabi=lp64" } */ ++/* { dg-warning "*Should use \"_\" to contact Profiles with other extensions" } */ ++int ++foo () ++{} +-- +2.50.1 + diff --git a/0016-RISC-V-Support-RISC-V-Profiles-23.patch b/0016-RISC-V-Support-RISC-V-Profiles-23.patch new file mode 100644 index 0000000..65616da --- /dev/null +++ b/0016-RISC-V-Support-RISC-V-Profiles-23.patch @@ -0,0 +1,94 @@ +From 54c35da73f037c090a816c56d865735bf8ad7720 Mon Sep 17 00:00:00 2001 +From: Jiawei +Date: Sat, 10 May 2025 19:26:35 +0800 +Subject: [PATCH 16/29] RISC-V: Support RISC-V Profiles 23. + +This patch introduces support for RISC-V Profiles RV23A and RV23B [1], +enabling developers to utilize these profiles through the -march option. + +[1] https://github.com/riscv/riscv-profiles/releases/tag/rva23-rvb23-ratified + +Version log: +Update the testcases, using lowercase letter. + +gcc/ChangeLog: + + * common/config/riscv/riscv-common.cc: New profile. + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/arch-53.c: New test. + * gcc.target/riscv/arch-54.c: New test. + +(cherry picked from commit 66d17ba3cb47980455ee9d6b4123dce61aef2fa2) +--- + gcc/common/config/riscv/riscv-common.cc | 16 ++++++++++++++++ + gcc/testsuite/gcc.target/riscv/arch-53.c | 11 +++++++++++ + gcc/testsuite/gcc.target/riscv/arch-54.c | 10 ++++++++++ + 3 files changed, 37 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/riscv/arch-53.c + create mode 100644 gcc/testsuite/gcc.target/riscv/arch-54.c + +diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc +index ce62bdfe39b..ee2180dcf4b 100644 +--- a/gcc/common/config/riscv/riscv-common.cc ++++ b/gcc/common/config/riscv/riscv-common.cc +@@ -461,6 +461,22 @@ static const riscv_profiles riscv_profiles_table[] = + "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop" + "_zicboz_zfhmin_zkt"}, + ++ /* RVA23 contains all mandatory base ISA for RVA22U64 and the new extension ++ 'v,zihintntl,zvfhmin,zvbb,zvkt,zicond,zimop,zcmop,zfa,zawrs' as mandatory ++ extensions. */ ++ {"rva23u64", "rv64imafdcv_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa" ++ "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop" ++ "_zicboz_zfhmin_zkt_zvfhmin_zvbb_zvkt_zihintntl_zicond_zimop_zcmop_zcb" ++ "_zfa_zawrs"}, ++ ++ /* RVB23 contains all mandatory base ISA for RVA22U64 and the new extension ++ 'zihintntl,zicond,zimop,zcmop,zfa,zawrs' as mandatory ++ extensions. */ ++ {"rvb23u64", "rv64imafdc_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa" ++ "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop" ++ "_zicboz_zfhmin_zkt_zihintntl_zicond_zimop_zcmop_zcb" ++ "_zfa_zawrs"}, ++ + /* Currently we do not define S/M mode Profiles in gcc part. */ + + /* Terminate the list. */ +diff --git a/gcc/testsuite/gcc.target/riscv/arch-53.c b/gcc/testsuite/gcc.target/riscv/arch-53.c +new file mode 100644 +index 00000000000..8210978ee8b +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/arch-53.c +@@ -0,0 +1,11 @@ ++/* { dg-do compile } */ ++/* { dg-options "-march=rva23u64 -mabi=lp64d" } */ ++ ++void foo(){} ++ ++/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0" ++"_b1p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0" ++_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0" ++_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0" ++_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0" ++_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0\"" } } */ +diff --git a/gcc/testsuite/gcc.target/riscv/arch-54.c b/gcc/testsuite/gcc.target/riscv/arch-54.c +new file mode 100644 +index 00000000000..6d242dfba50 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/arch-54.c +@@ -0,0 +1,10 @@ ++/* { dg-do compile } */ ++/* { dg-options "-march=rvb23u64 -mabi=lp64d" } */ ++ ++void foo(){} ++ ++/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0" ++"_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0" ++"_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_za64rs1p0" ++"_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0_zba1p0" ++"_zbb1p0_zbs1p0_zkt1p0\"" } } */ +-- +2.50.1 + diff --git a/0017-testsuite-Fix-RISC-V-arch-52.c-format-issue.patch b/0017-testsuite-Fix-RISC-V-arch-52.c-format-issue.patch new file mode 100644 index 0000000..130bb6d --- /dev/null +++ b/0017-testsuite-Fix-RISC-V-arch-52.c-format-issue.patch @@ -0,0 +1,31 @@ +From 5bf34725d04f88206eb3ea95b27d57bb2f4fa4fb Mon Sep 17 00:00:00 2001 +From: Jiawei +Date: Mon, 12 May 2025 13:23:50 +0800 +Subject: [PATCH 17/29] testsuite: Fix RISC-V arch-52.c format issue. + +Fix incorrect regular expression. + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/arch-52.c: Fix regular expression. + +(cherry picked from commit 63d26b0e1f11043552404d2ba6448ec74840fa48) +--- + gcc/testsuite/gcc.target/riscv/arch-52.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/gcc/testsuite/gcc.target/riscv/arch-52.c b/gcc/testsuite/gcc.target/riscv/arch-52.c +index da6aea8fd94..6133370b68a 100644 +--- a/gcc/testsuite/gcc.target/riscv/arch-52.c ++++ b/gcc/testsuite/gcc.target/riscv/arch-52.c +@@ -1,6 +1,6 @@ + /* { dg-do compile } */ + /* { dg-options "-march=rva22u64v -mabi=lp64" } */ +-/* { dg-warning "*Should use \"_\" to contact Profiles with other extensions" } */ ++/* { dg-warning "Should use \"_\" to contact Profiles with other extensions" "" { target *-*-* } 0 } */ + int + foo () + {} +-- +2.50.1 + diff --git a/0018-PATCH-RISC-V-Recognized-svadu-and-svade-extension.patch b/0018-PATCH-RISC-V-Recognized-svadu-and-svade-extension.patch new file mode 100644 index 0000000..2a4ccd3 --- /dev/null +++ b/0018-PATCH-RISC-V-Recognized-svadu-and-svade-extension.patch @@ -0,0 +1,114 @@ +From 9c5259c0f497ef26d119708a22dd77d2072fbbba Mon Sep 17 00:00:00 2001 +From: Mingzhu Yan +Date: Tue, 6 May 2025 16:59:09 -0600 +Subject: [PATCH 18/29] [PATCH] RISC-V: Recognized svadu and svade extension + +This patch support svadu and svade extension. +To enable GCC to recognize and process svadu and svade extension correctly at compile time. + +gcc/ChangeLog: + + * common/config/riscv/riscv-common.cc (riscv_ext_version_table): New + extension. + (riscv_ext_flag_table) Ditto. + * config/riscv/riscv.opt: New mask. + + * doc/invoke.texi (RISC-V Options): New extension + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/arch-45.c: New test. + * gcc.target/riscv/arch-46.c: New test. + +(cherry picked from commit aed2a447c7ff4282621aa7941f840cb2ddc90354) +--- + gcc/common/config/riscv/riscv-common.cc | 4 ++++ + gcc/config/riscv/riscv.opt | 4 ++++ + gcc/doc/invoke.texi | 8 ++++++++ + gcc/testsuite/gcc.target/riscv/arch-45.c | 5 +++++ + gcc/testsuite/gcc.target/riscv/arch-46.c | 5 +++++ + 5 files changed, 26 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/riscv/arch-45.c + create mode 100644 gcc/testsuite/gcc.target/riscv/arch-46.c + +diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc +index ee2180dcf4b..aadfce29306 100644 +--- a/gcc/common/config/riscv/riscv-common.cc ++++ b/gcc/common/config/riscv/riscv-common.cc +@@ -394,6 +394,8 @@ static const struct riscv_ext_version riscv_ext_version_table[] = + {"ssstateen", ISA_SPEC_CLASS_NONE, 1, 0}, + {"sstc", ISA_SPEC_CLASS_NONE, 1, 0}, + ++ {"svade", ISA_SPEC_CLASS_NONE, 1, 0}, ++ {"svadu", ISA_SPEC_CLASS_NONE, 1, 0}, + {"svinval", ISA_SPEC_CLASS_NONE, 1, 0}, + {"svnapot", ISA_SPEC_CLASS_NONE, 1, 0}, + {"svpbmt", ISA_SPEC_CLASS_NONE, 1, 0}, +@@ -1784,6 +1786,8 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = + {"zcmp", &gcc_options::x_riscv_zc_subext, MASK_ZCMP}, + {"zcmt", &gcc_options::x_riscv_zc_subext, MASK_ZCMT}, + ++ {"svade", &gcc_options::x_riscv_sv_subext, MASK_SVADE}, ++ {"svadu", &gcc_options::x_riscv_sv_subext, MASK_SVADU}, + {"svinval", &gcc_options::x_riscv_sv_subext, MASK_SVINVAL}, + {"svnapot", &gcc_options::x_riscv_sv_subext, MASK_SVNAPOT}, + +diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt +index dea339a24d3..3097d02db63 100644 +--- a/gcc/config/riscv/riscv.opt ++++ b/gcc/config/riscv/riscv.opt +@@ -446,6 +446,10 @@ Mask(XCVBI) Var(riscv_xcv_subext) + TargetVariable + int riscv_sv_subext + ++Mask(SVADE) Var(riscv_sv_subext) ++ ++Mask(SVADU) Var(riscv_sv_subext) ++ + Mask(SVINVAL) Var(riscv_sv_subext) + + Mask(SVNAPOT) Var(riscv_sv_subext) +diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi +index 6f80bfad6af..a519f11773d 100644 +--- a/gcc/doc/invoke.texi ++++ b/gcc/doc/invoke.texi +@@ -30931,6 +30931,14 @@ to @samp{zvks} and @samp{zvkg}. + @tab 1.0 + @tab Supervisor-mode timer interrupts extension. + ++@item svade ++@tab 1.0 ++@tab Cause exception when hardware updating of A/D bits is disabled ++ ++@item svadu ++@tab 1.0 ++@tab Hardware Updating of A/D Bits extension. ++ + @item svinval + @tab 1.0 + @tab Fine-grained address-translation cache invalidation extension. +diff --git a/gcc/testsuite/gcc.target/riscv/arch-45.c b/gcc/testsuite/gcc.target/riscv/arch-45.c +new file mode 100644 +index 00000000000..afffb995578 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/arch-45.c +@@ -0,0 +1,5 @@ ++/* { dg-do compile } */ ++/* { dg-options "-march=rv64gc_svadu -mabi=lp64" } */ ++int foo() ++{ ++} +diff --git a/gcc/testsuite/gcc.target/riscv/arch-46.c b/gcc/testsuite/gcc.target/riscv/arch-46.c +new file mode 100644 +index 00000000000..2a062172e75 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/arch-46.c +@@ -0,0 +1,5 @@ ++/* { dg-do compile } */ ++/* { dg-options "-march=rv64gc_svade -mabi=lp64" } */ ++int foo() ++{ ++} +-- +2.50.1 + diff --git a/0019-RISC-V-Add-augmented-hypervisor-series-extensions.patch b/0019-RISC-V-Add-augmented-hypervisor-series-extensions.patch new file mode 100644 index 0000000..7e80bb0 --- /dev/null +++ b/0019-RISC-V-Add-augmented-hypervisor-series-extensions.patch @@ -0,0 +1,164 @@ +From a4c5a56d3c6c6ff2f7057f19a9e7ad4f5a0a3e51 Mon Sep 17 00:00:00 2001 +From: Jiawei +Date: Tue, 13 May 2025 15:23:39 +0800 +Subject: [PATCH 19/29] RISC-V: Add augmented hypervisor series extensions. +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The augmented hypervisor series extensions 'sha'[1] is a new profile-defined +extension series that captures the full set of features that are mandated to +be supported along with the 'H' extension. + +[1] https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc#rva23s64-profile + +Version log: Update implements， fix testcase format. + +gcc/ChangeLog: + + * config/riscv/riscv-ext.def: New extension defs. + * config/riscv/riscv-ext.opt: Ditto. + * doc/riscv-ext.texi: Ditto. + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/arch-55.c: New test. + +(cherry picked from commit 0cbace3b142c087335e245245e97f6605a6cd1f7) +--- + gcc/common/config/riscv/riscv-common.cc | 25 +++++++++++++++++++++ + gcc/config/riscv/riscv.opt | 17 ++++++++++++++ + gcc/doc/invoke.texi | 28 ++++++++++++++++++++++++ + gcc/testsuite/gcc.target/riscv/arch-55.c | 9 ++++++++ + 4 files changed, 79 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/riscv/arch-55.c + +diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc +index aadfce29306..9f571f5f81a 100644 +--- a/gcc/common/config/riscv/riscv-common.cc ++++ b/gcc/common/config/riscv/riscv-common.cc +@@ -207,6 +207,23 @@ static const riscv_implied_info_t riscv_implied_info[] = + return subset_list->xlen () == 32 && subset_list->lookup ("f"); + }}, + ++ {"sha", "h"}, ++ {"sha", "shcounterenw"}, ++ {"sha", "shgatpa"}, ++ {"sha", "shtvala"}, ++ {"sha", "shvstvala"}, ++ {"sha", "shvstvecd"}, ++ {"sha", "shvsatpa"}, ++ {"sha", "ssstateen"}, ++ {"shcounterenw", "h"}, ++ {"shcounterenw", "zihpm"}, ++ {"shgatpa", "h"}, ++ {"shgatpa", "ssstateen"}, ++ {"shtvala", "h"}, ++ {"shvstvala", "h"}, ++ {"shvstvecd", "h"}, ++ {"shvsatpa", "h"}, ++ + {"smaia", "ssaia"}, + {"smstateen", "ssstateen"}, + {"smepmp", "zicsr"}, +@@ -385,6 +402,14 @@ static const struct riscv_ext_version riscv_ext_version_table[] = + {"zcmp", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zcmt", ISA_SPEC_CLASS_NONE, 1, 0}, + ++ {"sha", ISA_SPEC_CLASS_NONE, 1, 0}, ++ {"shcounterenw", ISA_SPEC_CLASS_NONE, 1, 0}, ++ {"shgatpa", ISA_SPEC_CLASS_NONE, 1, 0}, ++ {"shtvala", ISA_SPEC_CLASS_NONE, 1, 0}, ++ {"shvstvala", ISA_SPEC_CLASS_NONE, 1, 0}, ++ {"shvstvecd", ISA_SPEC_CLASS_NONE, 1, 0}, ++ {"shvsatpa", ISA_SPEC_CLASS_NONE, 1, 0}, ++ + {"smaia", ISA_SPEC_CLASS_NONE, 1, 0}, + {"smepmp", ISA_SPEC_CLASS_NONE, 1, 0}, + {"smstateen", ISA_SPEC_CLASS_NONE, 1, 0}, +diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt +index 3097d02db63..6dce8529d99 100644 +--- a/gcc/config/riscv/riscv.opt ++++ b/gcc/config/riscv/riscv.opt +@@ -443,6 +443,23 @@ Mask(ZCMT) Var(riscv_zc_subext) + + Mask(XCVBI) Var(riscv_xcv_subext) + ++TargetVariable ++int riscv_sh_subext ++ ++Mask(SHA) Var(riscv_sh_subext) ++ ++Mask(SHCOUNTERENW) Var(riscv_sh_subext) ++ ++Mask(SHGATPA) Var(riscv_sh_subext) ++ ++Mask(SHTVALA) Var(riscv_sh_subext) ++ ++Mask(SHVSTVALA) Var(riscv_sh_subext) ++ ++Mask(SHVSTVECD) Var(riscv_sh_subext) ++ ++Mask(SHVSATPA) Var(riscv_sh_subext) ++ + TargetVariable + int riscv_sv_subext + +diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi +index a519f11773d..d7ed579c521 100644 +--- a/gcc/doc/invoke.texi ++++ b/gcc/doc/invoke.texi +@@ -30903,6 +30903,34 @@ to @samp{zvks} and @samp{zvkg}. + @tab 1.0 + @tab Table jump instruction extension. + ++@item sha ++@tab 1.0 ++@tab The augmented hypervisor extension ++ ++@item shcounterenw ++@tab 1.0 ++@tab Support writeable enables for any supported counter ++ ++@item shgatpa ++@tab 1.0 ++@tab SvNNx4 mode supported for all modes supported by satp ++ ++@item shtvala ++@tab 1.0 ++@tab The htval register provides all needed values ++ ++@item shvstvala ++@tab 1.0 ++@tab The vstval register provides all needed values ++ ++@item shvstvecd ++@tab 1.0 ++@tab The vstvec register supports Direct mode ++ ++@item shvsatpa ++@tab 1.0 ++@tab The vsatp register supports all modes supported by satp ++ + @item smaia + @tab 1.0 + @tab Advanced interrupt architecture extension. +diff --git a/gcc/testsuite/gcc.target/riscv/arch-55.c b/gcc/testsuite/gcc.target/riscv/arch-55.c +new file mode 100644 +index 00000000000..0e8a2940b58 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/arch-55.c +@@ -0,0 +1,9 @@ ++/* { dg-do compile } */ ++/* { dg-options "-march=rv64g_sha -mabi=lp64d" } */ ++ ++void foo(){} ++ ++/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2" ++"_d2p2_h1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_sha1p0" ++"_shcounterenw1p0_shgatpa1p0_shtvala1p0_shvsatpa1p0_shvstvala1p0_shvstvecd1p0" ++"_ssstateen1p0\"" } } */ +\ No newline at end of file +-- +2.50.1 + diff --git a/0020-PATCH-RISC-V-Imply-zicsr-for-svade-and-svadu-extensi.patch b/0020-PATCH-RISC-V-Imply-zicsr-for-svade-and-svadu-extensi.patch new file mode 100644 index 0000000..6f078b6 --- /dev/null +++ b/0020-PATCH-RISC-V-Imply-zicsr-for-svade-and-svadu-extensi.patch @@ -0,0 +1,35 @@ +From afd624641924b80bfd7a53d933aad94de9a19abe Mon Sep 17 00:00:00 2001 +From: Dongyan Chen +Date: Wed, 4 Jun 2025 08:03:31 -0600 +Subject: [PATCH 20/29] [PATCH] RISC-V: Imply zicsr for svade and svadu + extensions. + +This patch implies zicsr for svade and svadu extensions. +According to the riscv-privileged spec, the svade and svadu extensions +are privileged instructions, so they should imply zicsr. + +gcc/ChangeLog: + + * common/config/riscv/riscv-common.cc: Imply zicsr. + +(cherry picked from commit 28106a0c5d18173832d8013dccbb6fcc71646868) +--- + gcc/common/config/riscv/riscv-common.cc | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc +index 9f571f5f81a..4ec4ab019be 100644 +--- a/gcc/common/config/riscv/riscv-common.cc ++++ b/gcc/common/config/riscv/riscv-common.cc +@@ -231,6 +231,8 @@ static const riscv_implied_info_t riscv_implied_info[] = + {"sscofpmf", "zicsr"}, + {"ssstateen", "zicsr"}, + {"sstc", "zicsr"}, ++ {"svadu", "zicsr"}, ++ {"svade", "zicsr"}, + + {NULL, NULL} + }; +-- +2.50.1 + diff --git a/0021-RISC-V-Support-Ssccptr-extension.patch b/0021-RISC-V-Support-Ssccptr-extension.patch new file mode 100644 index 0000000..f11b2ed --- /dev/null +++ b/0021-RISC-V-Support-Ssccptr-extension.patch @@ -0,0 +1,85 @@ +From 6769b1723f1ae8d476fb84299885c591a6768f84 Mon Sep 17 00:00:00 2001 +From: Jiawei +Date: Thu, 5 Jun 2025 13:15:02 +0800 +Subject: [PATCH 21/29] RISC-V: Support Ssccptr extension. + +Support the Ssccptr extension, which allows the main memory to support +page table reads. + +gcc/ChangeLog: + + * config/riscv/riscv-ext.def: New extension definition. + * config/riscv/riscv-ext.opt: New extension mask. + * doc/riscv-ext.texi: Document the new extension. + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/arch-ssccptr.c: New test. + +Signed-off-by: Jiawei +(cherry picked from commit a84b388c84aa7bfed62bf3733330f3c82d37c943) +--- + gcc/common/config/riscv/riscv-common.cc | 1 + + gcc/config/riscv/riscv.opt | 5 +++++ + gcc/doc/invoke.texi | 4 ++++ + gcc/testsuite/gcc.target/riscv/arch-ssccptr.c | 5 +++++ + 4 files changed, 15 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/riscv/arch-ssccptr.c + +diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc +index 4ec4ab019be..6c3070fe400 100644 +--- a/gcc/common/config/riscv/riscv-common.cc ++++ b/gcc/common/config/riscv/riscv-common.cc +@@ -417,6 +417,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] = + {"smstateen", ISA_SPEC_CLASS_NONE, 1, 0}, + + {"ssaia", ISA_SPEC_CLASS_NONE, 1, 0}, ++ {"ssccptr", ISA_SPEC_CLASS_NONE, 1, 0}, + {"sscofpmf", ISA_SPEC_CLASS_NONE, 1, 0}, + {"ssstateen", ISA_SPEC_CLASS_NONE, 1, 0}, + {"sstc", ISA_SPEC_CLASS_NONE, 1, 0}, +diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt +index 6dce8529d99..70b246f93f1 100644 +--- a/gcc/config/riscv/riscv.opt ++++ b/gcc/config/riscv/riscv.opt +@@ -460,6 +460,11 @@ Mask(SHVSTVECD) Var(riscv_sh_subext) + + Mask(SHVSATPA) Var(riscv_sh_subext) + ++TargetVariable ++int riscv_ss_subext ++ ++Mask(SSCCPTR) Var(riscv_ss_subext) ++ + TargetVariable + int riscv_sv_subext + +diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi +index d7ed579c521..5e097b0738e 100644 +--- a/gcc/doc/invoke.texi ++++ b/gcc/doc/invoke.texi +@@ -30947,6 +30947,10 @@ to @samp{zvks} and @samp{zvkg}. + @tab 1.0 + @tab Advanced interrupt architecture extension for supervisor-mode. + ++@item ssccptr ++@tab 1.0 ++@tab Main memory supports page table reads ++ + @item sscofpmf + @tab 1.0 + @tab Count overflow & filtering extension. +diff --git a/gcc/testsuite/gcc.target/riscv/arch-ssccptr.c b/gcc/testsuite/gcc.target/riscv/arch-ssccptr.c +new file mode 100644 +index 00000000000..902155a0818 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/arch-ssccptr.c +@@ -0,0 +1,5 @@ ++/* { dg-do compile } */ ++/* { dg-options "-march=rv64i_ssccptr -mabi=lp64" } */ ++int foo() ++{ ++} +-- +2.50.1 + diff --git a/0022-RISC-V-Support-Sscounterenw-extension.patch b/0022-RISC-V-Support-Sscounterenw-extension.patch new file mode 100644 index 0000000..2064695 --- /dev/null +++ b/0022-RISC-V-Support-Sscounterenw-extension.patch @@ -0,0 +1,90 @@ +From c41f70704011120d2922b4b6713233a2e8d3a87d Mon Sep 17 00:00:00 2001 +From: Jiawei +Date: Thu, 5 Jun 2025 13:33:21 +0800 +Subject: [PATCH 22/29] RISC-V: Support Sscounterenw extension. + +Support the Sscounterenw extension, which allows writeable enables for any +supported counter. + +gcc/ChangeLog: + + * config/riscv/riscv-ext.def: New extension definition. + * config/riscv/riscv-ext.opt: New extension mask. + * doc/riscv-ext.texi: Document the new extension. + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/arch-sscounterenw.c: New test. + +Signed-off-by: Jiawei +(cherry picked from commit 6a2a0ab8b71e0985f6950f450f8c34437a2fbdcc) +--- + gcc/common/config/riscv/riscv-common.cc | 2 ++ + gcc/config/riscv/riscv.opt | 2 ++ + gcc/doc/invoke.texi | 4 ++++ + gcc/testsuite/gcc.target/riscv/arch-sscounterenw.c | 5 +++++ + 4 files changed, 13 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/riscv/arch-sscounterenw.c + +diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc +index 6c3070fe400..a17c340643a 100644 +--- a/gcc/common/config/riscv/riscv-common.cc ++++ b/gcc/common/config/riscv/riscv-common.cc +@@ -229,6 +229,7 @@ static const riscv_implied_info_t riscv_implied_info[] = + {"smepmp", "zicsr"}, + {"ssaia", "zicsr"}, + {"sscofpmf", "zicsr"}, ++ {"sscounterenw", "zicsr"}, + {"ssstateen", "zicsr"}, + {"sstc", "zicsr"}, + {"svadu", "zicsr"}, +@@ -419,6 +420,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] = + {"ssaia", ISA_SPEC_CLASS_NONE, 1, 0}, + {"ssccptr", ISA_SPEC_CLASS_NONE, 1, 0}, + {"sscofpmf", ISA_SPEC_CLASS_NONE, 1, 0}, ++ {"sscounterenw", ISA_SPEC_CLASS_NONE, 1, 0}, + {"ssstateen", ISA_SPEC_CLASS_NONE, 1, 0}, + {"sstc", ISA_SPEC_CLASS_NONE, 1, 0}, + +diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt +index 70b246f93f1..5e12ea2f7e9 100644 +--- a/gcc/config/riscv/riscv.opt ++++ b/gcc/config/riscv/riscv.opt +@@ -465,6 +465,8 @@ int riscv_ss_subext + + Mask(SSCCPTR) Var(riscv_ss_subext) + ++Mask(SSCOUNTERENW) Var(riscv_ss_subext) ++ + TargetVariable + int riscv_sv_subext + +diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi +index 5e097b0738e..b88205d4a09 100644 +--- a/gcc/doc/invoke.texi ++++ b/gcc/doc/invoke.texi +@@ -30955,6 +30955,10 @@ to @samp{zvks} and @samp{zvkg}. + @tab 1.0 + @tab Count overflow & filtering extension. + ++@item sscounterenw ++@tab 1.0 ++@tab Support writeable enables for any supported counter ++ + @item ssstateen + @tab 1.0 + @tab State-enable extension for supervisor-mode. +diff --git a/gcc/testsuite/gcc.target/riscv/arch-sscounterenw.c b/gcc/testsuite/gcc.target/riscv/arch-sscounterenw.c +new file mode 100644 +index 00000000000..901b6bc6c9e +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/arch-sscounterenw.c +@@ -0,0 +1,5 @@ ++/* { dg-do compile } */ ++/* { dg-options "-march=rv64i_sscounterenw -mabi=lp64" } */ ++int foo() ++{ ++} +-- +2.50.1 + diff --git a/0023-RISC-V-Support-Sstvala-extension.patch b/0023-RISC-V-Support-Sstvala-extension.patch new file mode 100644 index 0000000..aa9e647 --- /dev/null +++ b/0023-RISC-V-Support-Sstvala-extension.patch @@ -0,0 +1,90 @@ +From 755043db737c1608cd6de0d1e2bf224ec4cd1006 Mon Sep 17 00:00:00 2001 +From: Jiawei +Date: Thu, 5 Jun 2025 13:46:39 +0800 +Subject: [PATCH 23/29] RISC-V: Support Sstvala extension. + +Support the Sstvala extension, which provides all needed values in +Supervisor Trap Value register (stval). + +gcc/ChangeLog: + + * config/riscv/riscv-ext.def: New extension definition. + * config/riscv/riscv-ext.opt: New extension mask. + * doc/riscv-ext.texi: Document the new extension. + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/arch-sstvala.c: New test. + +Signed-off-by: Jiawei +(cherry picked from commit 37f0e8395c279b5eb969bf678e5c571c1f3d3b32) +--- + gcc/common/config/riscv/riscv-common.cc | 2 ++ + gcc/config/riscv/riscv.opt | 2 ++ + gcc/doc/invoke.texi | 4 ++++ + gcc/testsuite/gcc.target/riscv/arch-sstvala.c | 5 +++++ + 4 files changed, 13 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/riscv/arch-sstvala.c + +diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc +index a17c340643a..e4a45597fec 100644 +--- a/gcc/common/config/riscv/riscv-common.cc ++++ b/gcc/common/config/riscv/riscv-common.cc +@@ -232,6 +232,7 @@ static const riscv_implied_info_t riscv_implied_info[] = + {"sscounterenw", "zicsr"}, + {"ssstateen", "zicsr"}, + {"sstc", "zicsr"}, ++ {"sstvala", "zicsr"}, + {"svadu", "zicsr"}, + {"svade", "zicsr"}, + +@@ -423,6 +424,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] = + {"sscounterenw", ISA_SPEC_CLASS_NONE, 1, 0}, + {"ssstateen", ISA_SPEC_CLASS_NONE, 1, 0}, + {"sstc", ISA_SPEC_CLASS_NONE, 1, 0}, ++ {"sstvala", ISA_SPEC_CLASS_NONE, 1, 0}, + + {"svade", ISA_SPEC_CLASS_NONE, 1, 0}, + {"svadu", ISA_SPEC_CLASS_NONE, 1, 0}, +diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt +index 5e12ea2f7e9..99da24dc915 100644 +--- a/gcc/config/riscv/riscv.opt ++++ b/gcc/config/riscv/riscv.opt +@@ -467,6 +467,8 @@ Mask(SSCCPTR) Var(riscv_ss_subext) + + Mask(SSCOUNTERENW) Var(riscv_ss_subext) + ++Mask(SSTVALA) Var(riscv_ss_subext) ++ + TargetVariable + int riscv_sv_subext + +diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi +index b88205d4a09..af961acacc0 100644 +--- a/gcc/doc/invoke.texi ++++ b/gcc/doc/invoke.texi +@@ -30967,6 +30967,10 @@ to @samp{zvks} and @samp{zvkg}. + @tab 1.0 + @tab Supervisor-mode timer interrupts extension. + ++@item sstvala ++@tab 1.0 ++@tab Stval provides all needed values ++ + @item svade + @tab 1.0 + @tab Cause exception when hardware updating of A/D bits is disabled +diff --git a/gcc/testsuite/gcc.target/riscv/arch-sstvala.c b/gcc/testsuite/gcc.target/riscv/arch-sstvala.c +new file mode 100644 +index 00000000000..21ea8a6360c +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/arch-sstvala.c +@@ -0,0 +1,5 @@ ++/* { dg-do compile } */ ++/* { dg-options "-march=rv64i_sstvala -mabi=lp64" } */ ++int foo() ++{ ++} +-- +2.50.1 + diff --git a/0024-RISC-V-Support-Sstvecd-extension.patch b/0024-RISC-V-Support-Sstvecd-extension.patch new file mode 100644 index 0000000..bd0391d --- /dev/null +++ b/0024-RISC-V-Support-Sstvecd-extension.patch @@ -0,0 +1,90 @@ +From de07baac3a1fde61c5f219904d461e04b491c34a Mon Sep 17 00:00:00 2001 +From: Jiawei +Date: Thu, 5 Jun 2025 13:52:08 +0800 +Subject: [PATCH 24/29] RISC-V: Support Sstvecd extension. + +Support the Sstvecd extension, which allows Supervisor Trap Vector +Base Address register (stvec) to support Direct mode. + +gcc/ChangeLog: + + * config/riscv/riscv-ext.def: New extension definition. + * config/riscv/riscv-ext.opt: New extension mask. + * doc/riscv-ext.texi: Document the new extension. + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/arch-sstvecd.c: New test. + +Signed-off-by: Jiawei +(cherry picked from commit a3c4f30ecfc4f7b23df9aa2827068a1bfa57637e) +--- + gcc/common/config/riscv/riscv-common.cc | 2 ++ + gcc/config/riscv/riscv.opt | 2 ++ + gcc/doc/invoke.texi | 4 ++++ + gcc/testsuite/gcc.target/riscv/arch-sstvecd.c | 5 +++++ + 4 files changed, 13 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/riscv/arch-sstvecd.c + +diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc +index e4a45597fec..022ed483204 100644 +--- a/gcc/common/config/riscv/riscv-common.cc ++++ b/gcc/common/config/riscv/riscv-common.cc +@@ -233,6 +233,7 @@ static const riscv_implied_info_t riscv_implied_info[] = + {"ssstateen", "zicsr"}, + {"sstc", "zicsr"}, + {"sstvala", "zicsr"}, ++ {"sstvecd", "zicsr"}, + {"svadu", "zicsr"}, + {"svade", "zicsr"}, + +@@ -425,6 +426,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] = + {"ssstateen", ISA_SPEC_CLASS_NONE, 1, 0}, + {"sstc", ISA_SPEC_CLASS_NONE, 1, 0}, + {"sstvala", ISA_SPEC_CLASS_NONE, 1, 0}, ++ {"sstvecd", ISA_SPEC_CLASS_NONE, 1, 0}, + + {"svade", ISA_SPEC_CLASS_NONE, 1, 0}, + {"svadu", ISA_SPEC_CLASS_NONE, 1, 0}, +diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt +index 99da24dc915..d1aa608811d 100644 +--- a/gcc/config/riscv/riscv.opt ++++ b/gcc/config/riscv/riscv.opt +@@ -469,6 +469,8 @@ Mask(SSCOUNTERENW) Var(riscv_ss_subext) + + Mask(SSTVALA) Var(riscv_ss_subext) + ++Mask(SSTVECD) Var(riscv_ss_subext) ++ + TargetVariable + int riscv_sv_subext + +diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi +index af961acacc0..1176ef632f8 100644 +--- a/gcc/doc/invoke.texi ++++ b/gcc/doc/invoke.texi +@@ -30971,6 +30971,10 @@ to @samp{zvks} and @samp{zvkg}. + @tab 1.0 + @tab Stval provides all needed values + ++@item sstvecd ++@tab 1.0 ++@tab Stvec supports Direct mode ++ + @item svade + @tab 1.0 + @tab Cause exception when hardware updating of A/D bits is disabled +diff --git a/gcc/testsuite/gcc.target/riscv/arch-sstvecd.c b/gcc/testsuite/gcc.target/riscv/arch-sstvecd.c +new file mode 100644 +index 00000000000..e76f78818ee +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/arch-sstvecd.c +@@ -0,0 +1,5 @@ ++/* { dg-do compile } */ ++/* { dg-options "-march=rv64i_sstvecd -mabi=lp64" } */ ++int foo() ++{ ++} +-- +2.50.1 + diff --git a/0025-RISC-V-Support-Ssu64xl-extension.patch b/0025-RISC-V-Support-Ssu64xl-extension.patch new file mode 100644 index 0000000..cb1b9f0 --- /dev/null +++ b/0025-RISC-V-Support-Ssu64xl-extension.patch @@ -0,0 +1,89 @@ +From 266dfc5db9cd5975d981e837b46057aeed079ffe Mon Sep 17 00:00:00 2001 +From: Jiawei +Date: Thu, 5 Jun 2025 13:59:14 +0800 +Subject: [PATCH 25/29] RISC-V: Support Ssu64xl extension. + +Support the Ssu64xl extension, which requires UXLEN to be 64. + +gcc/ChangeLog: + + * config/riscv/riscv-ext.def: New extension definition. + * config/riscv/riscv-ext.opt: New extension mask. + * doc/riscv-ext.texi: Document the new extension. + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/arch-ssu64xl.c: New test. + +Signed-off-by: Jiawei +(cherry picked from commit 8e1f06d1d1c8bb25c44c321f90c39f36eb18f344) +--- + gcc/common/config/riscv/riscv-common.cc | 2 ++ + gcc/config/riscv/riscv.opt | 2 ++ + gcc/doc/invoke.texi | 4 ++++ + gcc/testsuite/gcc.target/riscv/arch-ssu64xl.c | 5 +++++ + 4 files changed, 13 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/riscv/arch-ssu64xl.c + +diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc +index 022ed483204..916b214f03d 100644 +--- a/gcc/common/config/riscv/riscv-common.cc ++++ b/gcc/common/config/riscv/riscv-common.cc +@@ -234,6 +234,7 @@ static const riscv_implied_info_t riscv_implied_info[] = + {"sstc", "zicsr"}, + {"sstvala", "zicsr"}, + {"sstvecd", "zicsr"}, ++ {"ssu64xl", "zicsr"}, + {"svadu", "zicsr"}, + {"svade", "zicsr"}, + +@@ -427,6 +428,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] = + {"sstc", ISA_SPEC_CLASS_NONE, 1, 0}, + {"sstvala", ISA_SPEC_CLASS_NONE, 1, 0}, + {"sstvecd", ISA_SPEC_CLASS_NONE, 1, 0}, ++ {"ssu64xl", ISA_SPEC_CLASS_NONE, 1, 0}, + + {"svade", ISA_SPEC_CLASS_NONE, 1, 0}, + {"svadu", ISA_SPEC_CLASS_NONE, 1, 0}, +diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt +index d1aa608811d..c91f797899a 100644 +--- a/gcc/config/riscv/riscv.opt ++++ b/gcc/config/riscv/riscv.opt +@@ -471,6 +471,8 @@ Mask(SSTVALA) Var(riscv_ss_subext) + + Mask(SSTVECD) Var(riscv_ss_subext) + ++Mask(SSU64XL) Var(riscv_ss_subext) ++ + TargetVariable + int riscv_sv_subext + +diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi +index 1176ef632f8..60b8db2749d 100644 +--- a/gcc/doc/invoke.texi ++++ b/gcc/doc/invoke.texi +@@ -30975,6 +30975,10 @@ to @samp{zvks} and @samp{zvkg}. + @tab 1.0 + @tab Stvec supports Direct mode + ++@item ssu64xl ++@tab 1.0 ++@tab UXLEN=64 must be supported ++ + @item svade + @tab 1.0 + @tab Cause exception when hardware updating of A/D bits is disabled +diff --git a/gcc/testsuite/gcc.target/riscv/arch-ssu64xl.c b/gcc/testsuite/gcc.target/riscv/arch-ssu64xl.c +new file mode 100644 +index 00000000000..6e151c14f9b +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/arch-ssu64xl.c +@@ -0,0 +1,5 @@ ++/* { dg-do compile } */ ++/* { dg-options "-march=rv64i_ssu64xl -mabi=lp64" } */ ++int foo() ++{ ++} +-- +2.50.1 + diff --git a/0026-RISC-V-Minimal-support-for-ssnpm-smnpm-and-smmpm-ext.patch b/0026-RISC-V-Minimal-support-for-ssnpm-smnpm-and-smmpm-ext.patch new file mode 100644 index 0000000..17a2a5d --- /dev/null +++ b/0026-RISC-V-Minimal-support-for-ssnpm-smnpm-and-smmpm-ext.patch @@ -0,0 +1,180 @@ +From 19eb8764d6631d6c0df3a75bd9be5bb96a3535ef Mon Sep 17 00:00:00 2001 +From: Dongyan Chen +Date: Mon, 12 May 2025 17:19:24 +0800 +Subject: [PATCH 26/29] RISC-V: Minimal support for ssnpm, smnpm and smmpm + extensions. + +This patch support ssnpm, smnpm, smmpm, sspm and supm extensions[1]. +To enable GCC to recognize and process ssnpm, smnpm, smmpm, sspm and +supm extensions correctly at compile time. + +[1]https://github.com/riscv/riscv-j-extension/blob/master/zjpm/instructions.adoc + +Changes for v5: +- Fix the testsuite error in arch-50.c. +Changes for v4: +- Fix the code based on the commit id 9b13bea07706a7cae0185f8a860d67209308c050. +Changes for v3: +- Fix the error messages in gcc/testsuite/gcc.target/riscv/arch-46.c +Changes for v2: +- Add the sspm and supm extensions. +- Add the check_conflict_ext function to check the compatibility of ssnpm, smnpm, smmpm, sspm and supm extensions. +- Add the test cases for ssnpm, smnpm, smmpm, sspm and supm extensions. + +gcc/ChangeLog: + + * common/config/riscv/riscv-common.cc + (riscv_subset_list::check_conflict_ext): New extension. + * config/riscv/riscv.opt: Ditto. + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/arch-ss-1.c: New test. + * gcc.target/riscv/arch-ss-2.c: New test. + +(cherry picked from commit 7e5f5fd101f8686d34532f7afab9314f252e71cd) +--- + gcc/common/config/riscv/riscv-common.cc | 37 ++++++++++++++++++++++ + gcc/config/riscv/riscv.opt | 16 ++++++++++ + gcc/testsuite/gcc.target/riscv/arch-ss-1.c | 5 +++ + gcc/testsuite/gcc.target/riscv/arch-ss-2.c | 10 ++++++ + 4 files changed, 68 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/riscv/arch-ss-1.c + create mode 100644 gcc/testsuite/gcc.target/riscv/arch-ss-2.c + +diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc +index 916b214f03d..9f3ede393d5 100644 +--- a/gcc/common/config/riscv/riscv-common.cc ++++ b/gcc/common/config/riscv/riscv-common.cc +@@ -238,6 +238,10 @@ static const riscv_implied_info_t riscv_implied_info[] = + {"svadu", "zicsr"}, + {"svade", "zicsr"}, + ++ {"ssnpm", "zicsr"}, ++ {"smnpm", "zicsr"}, ++ {"smmpm", "zicsr"}, ++ + {NULL, NULL} + }; + +@@ -430,6 +434,12 @@ static const struct riscv_ext_version riscv_ext_version_table[] = + {"sstvecd", ISA_SPEC_CLASS_NONE, 1, 0}, + {"ssu64xl", ISA_SPEC_CLASS_NONE, 1, 0}, + ++ {"ssnpm", ISA_SPEC_CLASS_NONE, 1, 0}, ++ {"smnpm", ISA_SPEC_CLASS_NONE, 1, 0}, ++ {"smmpm", ISA_SPEC_CLASS_NONE, 1, 0}, ++ {"sspm", ISA_SPEC_CLASS_NONE, 1, 0}, ++ {"supm", ISA_SPEC_CLASS_NONE, 1, 0}, ++ + {"svade", ISA_SPEC_CLASS_NONE, 1, 0}, + {"svadu", ISA_SPEC_CLASS_NONE, 1, 0}, + {"svinval", ISA_SPEC_CLASS_NONE, 1, 0}, +@@ -1410,6 +1420,26 @@ riscv_subset_list::check_conflict_ext () + error_at (m_loc, "%<-march=%s%>: zcf extension supports in rv32 only", + m_arch); + ++ if (lookup ("ssnpm") && m_xlen == 32) ++ error_at (m_loc, "%<-march=%s%>: ssnpm extension supports in rv64 only", ++ m_arch); ++ ++ if (lookup ("smnpm") && m_xlen == 32) ++ error_at (m_loc, "%<-march=%s%>: smnpm extension supports in rv64 only", ++ m_arch); ++ ++ if (lookup ("smmpm") && m_xlen == 32) ++ error_at (m_loc, "%<-march=%s%>: smmpm extension supports in rv64 only", ++ m_arch); ++ ++ if (lookup ("sspm") && m_xlen == 32) ++ error_at (m_loc, "%<-march=%s%>: sspm extension supports in rv64 only", ++ m_arch); ++ ++ if (lookup ("supm") && m_xlen == 32) ++ error_at (m_loc, "%<-march=%s%>: supm extension supports in rv64 only", ++ m_arch); ++ + if (lookup ("zfinx") && lookup ("f")) + error_at (m_loc, + "%<-march=%s%>: z*inx conflicts with floating-point " +@@ -1824,9 +1854,16 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = + + {"svade", &gcc_options::x_riscv_sv_subext, MASK_SVADE}, + {"svadu", &gcc_options::x_riscv_sv_subext, MASK_SVADU}, ++ + {"svinval", &gcc_options::x_riscv_sv_subext, MASK_SVINVAL}, + {"svnapot", &gcc_options::x_riscv_sv_subext, MASK_SVNAPOT}, + ++ {"ssnpm", &gcc_options::x_riscv_ss_subext, MASK_SSNPM}, ++ {"smnpm", &gcc_options::x_riscv_sm_subext, MASK_SMNPM}, ++ {"smmpm", &gcc_options::x_riscv_sm_subext, MASK_SMMPM}, ++ {"sspm", &gcc_options::x_riscv_ss_subext, MASK_SSPM}, ++ {"supm", &gcc_options::x_riscv_su_subext, MASK_SUPM}, ++ + {"ztso", &gcc_options::x_riscv_ztso_subext, MASK_ZTSO}, + + {"xcvmac", &gcc_options::x_riscv_xcv_subext, MASK_XCVMAC}, +diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt +index c91f797899a..5e61fbc4973 100644 +--- a/gcc/config/riscv/riscv.opt ++++ b/gcc/config/riscv/riscv.opt +@@ -463,6 +463,10 @@ Mask(SHVSATPA) Var(riscv_sh_subext) + TargetVariable + int riscv_ss_subext + ++Mask(SSNPM) Var(riscv_ss_subext) ++ ++Mask(SSPM) Var(riscv_ss_subext) ++ + Mask(SSCCPTR) Var(riscv_ss_subext) + + Mask(SSCOUNTERENW) Var(riscv_ss_subext) +@@ -484,6 +488,18 @@ Mask(SVINVAL) Var(riscv_sv_subext) + + Mask(SVNAPOT) Var(riscv_sv_subext) + ++TargetVariable ++int riscv_sm_subext ++ ++Mask(SMNPM) Var(riscv_sm_subext) ++ ++Mask(SMMPM) Var(riscv_sm_subext) ++ ++TargetVariable ++int riscv_su_subext ++ ++Mask(SUPM) Var(riscv_su_subext) ++ + TargetVariable + int riscv_ztso_subext + +diff --git a/gcc/testsuite/gcc.target/riscv/arch-ss-1.c b/gcc/testsuite/gcc.target/riscv/arch-ss-1.c +new file mode 100644 +index 00000000000..8f95737b248 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/arch-ss-1.c +@@ -0,0 +1,5 @@ ++/* { dg-do compile } */ ++/* { dg-options "-march=rv64gc_ssnpm_smnpm_smmpm_sspm_supm -mabi=lp64" } */ ++int foo() ++{ ++} +diff --git a/gcc/testsuite/gcc.target/riscv/arch-ss-2.c b/gcc/testsuite/gcc.target/riscv/arch-ss-2.c +new file mode 100644 +index 00000000000..d5924104285 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/arch-ss-2.c +@@ -0,0 +1,10 @@ ++/* { dg-do compile } */ ++/* { dg-options "-march=rv32gc_ssnpm_smnpm_smmpm_sspm_supm -mabi=ilp32d" } */ ++int foo() ++{ ++} ++/* { dg-error "'-march=rv32gc_ssnpm_smnpm_smmpm_sspm_supm': ssnpm extension supports in rv64 only" "" { target *-*-* } 0 } */ ++/* { dg-error "'-march=rv32gc_ssnpm_smnpm_smmpm_sspm_supm': smnpm extension supports in rv64 only" "" { target *-*-* } 0 } */ ++/* { dg-error "'-march=rv32gc_ssnpm_smnpm_smmpm_sspm_supm': smmpm extension supports in rv64 only" "" { target *-*-* } 0 } */ ++/* { dg-error "'-march=rv32gc_ssnpm_smnpm_smmpm_sspm_supm': sspm extension supports in rv64 only" "" { target *-*-* } 0 } */ ++/* { dg-error "'-march=rv32gc_ssnpm_smnpm_smmpm_sspm_supm': supm extension supports in rv64 only" "" { target *-*-* } 0 } */ +-- +2.50.1 + diff --git a/0027-RISC-V-Update-Profiles-string-in-RV23.patch b/0027-RISC-V-Update-Profiles-string-in-RV23.patch new file mode 100644 index 0000000..e5e4fae --- /dev/null +++ b/0027-RISC-V-Update-Profiles-string-in-RV23.patch @@ -0,0 +1,58 @@ +From e58d6f2970ac13019887dae0ddd803ebbc69e27d Mon Sep 17 00:00:00 2001 +From: Jiawei +Date: Mon, 16 Jun 2025 11:21:29 +0800 +Subject: [PATCH 27/29] RISC-V: Update Profiles string in RV23. + +Add b-ext in RVA/B23 as independent extension flags and add supm in +RVA23. + +gcc/ChangeLog: + + * common/config/riscv/riscv-common.cc: Add b-ext and supm. + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/arch-53.c: Update testcase. + +(cherry picked from commit b2af07bac21862d038bc1583cff97c2f3fb99e74) +--- + gcc/common/config/riscv/riscv-common.cc | 6 +++--- + gcc/testsuite/gcc.target/riscv/arch-53.c | 2 +- + 2 files changed, 4 insertions(+), 4 deletions(-) + +diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc +index 9f3ede393d5..3401c5a848c 100644 +--- a/gcc/common/config/riscv/riscv-common.cc ++++ b/gcc/common/config/riscv/riscv-common.cc +@@ -512,15 +512,15 @@ static const riscv_profiles riscv_profiles_table[] = + /* RVA23 contains all mandatory base ISA for RVA22U64 and the new extension + 'v,zihintntl,zvfhmin,zvbb,zvkt,zicond,zimop,zcmop,zfa,zawrs' as mandatory + extensions. */ +- {"rva23u64", "rv64imafdcv_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa" ++ {"rva23u64", "rv64imafdcbv_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa" + "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop" + "_zicboz_zfhmin_zkt_zvfhmin_zvbb_zvkt_zihintntl_zicond_zimop_zcmop_zcb" +- "_zfa_zawrs"}, ++ "_zfa_zawrs_supm"}, + + /* RVB23 contains all mandatory base ISA for RVA22U64 and the new extension + 'zihintntl,zicond,zimop,zcmop,zfa,zawrs' as mandatory + extensions. */ +- {"rvb23u64", "rv64imafdc_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa" ++ {"rvb23u64", "rv64imafdcb_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa" + "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop" + "_zicboz_zfhmin_zkt_zihintntl_zicond_zimop_zcmop_zcb" + "_zfa_zawrs"}, +diff --git a/gcc/testsuite/gcc.target/riscv/arch-53.c b/gcc/testsuite/gcc.target/riscv/arch-53.c +index 8210978ee8b..43ab23aee4d 100644 +--- a/gcc/testsuite/gcc.target/riscv/arch-53.c ++++ b/gcc/testsuite/gcc.target/riscv/arch-53.c +@@ -8,4 +8,4 @@ void foo(){} + _ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0" + _za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0" + _zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0" +-_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0\"" } } */ ++_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_supm1p0\"" } } */ +-- +2.50.1 + diff --git a/0028-RISC-V-Add-Profiles-RVA-B23S64-support.patch b/0028-RISC-V-Add-Profiles-RVA-B23S64-support.patch new file mode 100644 index 0000000..8af8903 --- /dev/null +++ b/0028-RISC-V-Add-Profiles-RVA-B23S64-support.patch @@ -0,0 +1,102 @@ +From f42c120438902b5fc81a26bba2fa490de4acd8c0 Mon Sep 17 00:00:00 2001 +From: Jiawei +Date: Tue, 24 Jun 2025 17:34:05 +0800 +Subject: [PATCH 28/29] RISC-V: Add Profiles RVA/B23S64 support. + +This patch adds support for the RISC-V Profiles RVA23S64 and RVB23S64. + +gcc/ChangeLog: + + * common/config/riscv/riscv-common.cc: New Profiles. + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/arch-rva23s.c: New test. + * gcc.target/riscv/arch-rvb23s.c: New test. + +(cherry picked from commit e858dc702147b7de560afad165e7f16e3ee7d6c9) +--- + gcc/common/config/riscv/riscv-common.cc | 18 +++++++++++++++++- + gcc/testsuite/gcc.target/riscv/arch-rva23s.c | 14 ++++++++++++++ + gcc/testsuite/gcc.target/riscv/arch-rvb23s.c | 12 ++++++++++++ + 3 files changed, 43 insertions(+), 1 deletion(-) + create mode 100644 gcc/testsuite/gcc.target/riscv/arch-rva23s.c + create mode 100644 gcc/testsuite/gcc.target/riscv/arch-rvb23s.c + +diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc +index 3401c5a848c..f7720295cd4 100644 +--- a/gcc/common/config/riscv/riscv-common.cc ++++ b/gcc/common/config/riscv/riscv-common.cc +@@ -517,6 +517,15 @@ static const riscv_profiles riscv_profiles_table[] = + "_zicboz_zfhmin_zkt_zvfhmin_zvbb_zvkt_zihintntl_zicond_zimop_zcmop_zcb" + "_zfa_zawrs_supm"}, + ++ /* RVA23S contains all mandatory base ISA for RVA23U64 and the privileged ++ extensions as mandatory extensions. */ ++ {"rva23s64", "rv64imafdcbv_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa" ++ "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop" ++ "_zicboz_zfhmin_zkt_zvfhmin_zvbb_zvkt_zihintntl_zicond_zimop_zcmop_zcb" ++ "_zfa_zawrs_svbare_svade_ssccptr_sstvecd_sstvala_sscounterenw_svpbmt" ++ "_svinval_svnapot_sstc_sscofpmf_ssnpm_ssu64xl_sha_supm" ++ }, ++ + /* RVB23 contains all mandatory base ISA for RVA22U64 and the new extension + 'zihintntl,zicond,zimop,zcmop,zfa,zawrs' as mandatory + extensions. */ +@@ -525,7 +534,14 @@ static const riscv_profiles riscv_profiles_table[] = + "_zicboz_zfhmin_zkt_zihintntl_zicond_zimop_zcmop_zcb" + "_zfa_zawrs"}, + +- /* Currently we do not define S/M mode Profiles in gcc part. */ ++ /* RVB23S contains all mandatory base ISA for RVB23U64 and the privileged ++ extensions as mandatory extensions. */ ++ {"rvb23s64", "rv64imafdcb_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa" ++ "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop" ++ "_zicboz_zfhmin_zkt_zvfhmin_zvbb_zvkt_zihintntl_zicond_zimop_zcmop_zcb" ++ "_zfa_zawrs_svbare_svade_ssccptr_sstvecd_sstvala_sscounterenw_svpbmt" ++ "_svinval_svnapot_sstc_sscofpmf_ssu64xl_supm" ++ }, + + /* Terminate the list. */ + {NULL, NULL} +diff --git a/gcc/testsuite/gcc.target/riscv/arch-rva23s.c b/gcc/testsuite/gcc.target/riscv/arch-rva23s.c +new file mode 100644 +index 00000000000..215249d52b1 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/arch-rva23s.c +@@ -0,0 +1,14 @@ ++/* { dg-do compile } */ ++/* { dg-options "-march=rva23s64 -mabi=lp64d" } */ ++ ++void foo(){} ++ ++/* { dg-final { scan-assembler-times ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0" ++"_b1p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0" ++"_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0" ++"_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0" ++"_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0" ++"_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_sha1p0_shcounterenw1p0" ++"_shgatpa1p0_shtvala1p0_shvsatpa1p0_shvstvala1p0_shvstvecd1p0_ssccptr1p0_sscofpmf1p0" ++"_sscounterenw1p0_ssnpm1p0_ssstateen1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_supm1p0" ++"_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0\" 1} } */ +diff --git a/gcc/testsuite/gcc.target/riscv/arch-rvb23s.c b/gcc/testsuite/gcc.target/riscv/arch-rvb23s.c +new file mode 100644 +index 00000000000..aa71f7dad7d +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/arch-rvb23s.c +@@ -0,0 +1,12 @@ ++/* { dg-do compile } */ ++/* { dg-options "-march=rvb23s64 -mabi=lp64d" } */ ++ ++void foo(){} ++ ++/* { dg-final { scan-assembler-times ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0" ++"_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0" ++"_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0" ++"_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0" ++"_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0" ++"_zvl32b1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_sstc1p0_sstvala1p0_sstvecd1p0" ++"_ssu64xl1p0_supm1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0\" 1} } */ +-- +2.50.1 + diff --git a/0029-PATCH-v2-RISC-V-Add-svbare-extension.patch b/0029-PATCH-v2-RISC-V-Add-svbare-extension.patch new file mode 100644 index 0000000..1cea4c2 --- /dev/null +++ b/0029-PATCH-v2-RISC-V-Add-svbare-extension.patch @@ -0,0 +1,94 @@ +From 90be7a74997281c8c1ad2dbe7314af03f46182ff Mon Sep 17 00:00:00 2001 +From: YunQiang Su +Date: Tue, 29 Jul 2025 15:06:37 +0800 +Subject: [PATCH 29/29] [PATCH v2] RISC-V: Add svbare extension. + +This patch support svbare extension, which is an extension in RVA23 profile. +To enable GCC to recognize and process svbare extension correctly at compile time. + +gcc/ChangeLog: + + * common/config/riscv/riscv-common.cc: New extension defs. + * config/riscv/riscv.opt: Ditto. + * doc/invoke.texi: Ditto. + +gcc/testsuite/ChangeLog: + + * gcc.target/riscv/arch-60.c: New test. + +Based on: +(Author: Dongyan Chen ) +(Date: Wed Jun 4 07:57:01 2025 -0600) +(cherry picked from commit 07e3ed74a2b648c0ce8e823bbf5bd8f23383efa1) +to fit gcc14 codebase. +--- + gcc/common/config/riscv/riscv-common.cc | 3 +++ + gcc/config/riscv/riscv.opt | 2 ++ + gcc/doc/invoke.texi | 4 ++++ + gcc/testsuite/gcc.target/riscv/arch-60.c | 5 +++++ + 4 files changed, 14 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/riscv/arch-60.c + +diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc +index f7720295cd4..fb99b1915ab 100644 +--- a/gcc/common/config/riscv/riscv-common.cc ++++ b/gcc/common/config/riscv/riscv-common.cc +@@ -242,6 +242,8 @@ static const riscv_implied_info_t riscv_implied_info[] = + {"smnpm", "zicsr"}, + {"smmpm", "zicsr"}, + ++ {"svbare", "zicsr"}, ++ + {NULL, NULL} + }; + +@@ -445,6 +447,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] = + {"svinval", ISA_SPEC_CLASS_NONE, 1, 0}, + {"svnapot", ISA_SPEC_CLASS_NONE, 1, 0}, + {"svpbmt", ISA_SPEC_CLASS_NONE, 1, 0}, ++ {"svbare", ISA_SPEC_CLASS_NONE, 1, 0}, + + {"xcvmac", ISA_SPEC_CLASS_NONE, 1, 0}, + {"xcvalu", ISA_SPEC_CLASS_NONE, 1, 0}, +diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt +index 5e61fbc4973..d31bd94829f 100644 +--- a/gcc/config/riscv/riscv.opt ++++ b/gcc/config/riscv/riscv.opt +@@ -488,6 +488,8 @@ Mask(SVINVAL) Var(riscv_sv_subext) + + Mask(SVNAPOT) Var(riscv_sv_subext) + ++Mask(SVBARE) Var(riscv_sv_subext) ++ + TargetVariable + int riscv_sm_subext + +diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi +index 60b8db2749d..8aab3067d41 100644 +--- a/gcc/doc/invoke.texi ++++ b/gcc/doc/invoke.texi +@@ -30999,6 +30999,10 @@ to @samp{zvks} and @samp{zvkg}. + @tab 1.0 + @tab Page-based memory types extension. + ++@item svbare ++@tab 1.0 ++@tab Satp mode bare is supported ++ + @item xcvmac + @tab 1.0 + @tab Core-V multiply-accumulate extension. +diff --git a/gcc/testsuite/gcc.target/riscv/arch-60.c b/gcc/testsuite/gcc.target/riscv/arch-60.c +new file mode 100644 +index 00000000000..ea599f20522 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/riscv/arch-60.c +@@ -0,0 +1,5 @@ ++/* { dg-do compile } */ ++/* { dg-options "-march=rv64i_svbare -mabi=lp64" } */ ++int foo() ++{ ++} +-- +2.50.1 + diff --git a/gcc-14.spec b/gcc-14.spec index 8a9f2f4..a86aaad 100644 --- a/gcc-14.spec +++ b/gcc-14.spec @@ -90,7 +90,7 @@ Summary: Various compilers (C, C++, Objective-C, ...) Name: %{?_scl_prefix}gcc%{gcc_ver} Version: 14.3.1 -Release: 4 +Release: 5 # libgcc, libgfortran, libgomp, libstdc++ and crtstuff have # GCC Runtime Exception. License: GPLv3+ and GPLv3+ with exceptions and GPLv2+ with exceptions and LGPLv2+ and BSD @@ -189,6 +189,21 @@ Patch1018: 0011-RISC-V-Add-configure-check-for-B-extention-support.patch Patch1019: 0012-RISC-V-c-implies-zca-and-conditionally-zcf-zcd.patch Patch1020: 0013-RISC-V-RISC-V-Add-implication-for-M-extension.patch Patch1021: 0014-RISC-V-Minimal-support-for-Zimop-extension.patch +Patch1022: 0015-RISC-V-Support-RISC-V-Profiles-20-22.patch +Patch1023: 0016-RISC-V-Support-RISC-V-Profiles-23.patch +Patch1024: 0017-testsuite-Fix-RISC-V-arch-52.c-format-issue.patch +Patch1025: 0018-PATCH-RISC-V-Recognized-svadu-and-svade-extension.patch +Patch1026: 0019-RISC-V-Add-augmented-hypervisor-series-extensions.patch +Patch1027: 0020-PATCH-RISC-V-Imply-zicsr-for-svade-and-svadu-extensi.patch +Patch1028: 0021-RISC-V-Support-Ssccptr-extension.patch +Patch1029: 0022-RISC-V-Support-Sscounterenw-extension.patch +Patch1030: 0023-RISC-V-Support-Sstvala-extension.patch +Patch1031: 0024-RISC-V-Support-Sstvecd-extension.patch +Patch1032: 0025-RISC-V-Support-Ssu64xl-extension.patch +Patch1033: 0026-RISC-V-Minimal-support-for-ssnpm-smnpm-and-smmpm-ext.patch +Patch1034: 0027-RISC-V-Update-Profiles-string-in-RV23.patch +Patch1035: 0028-RISC-V-Add-Profiles-RVA-B23S64-support.patch +Patch1036: 0029-PATCH-v2-RISC-V-Add-svbare-extension.patch # On ARM EABI systems, we do want -gnueabi to be part of the # target triple. @@ -2219,6 +2234,9 @@ end %doc rpm.doc/changelogs/libcc1/ChangeLog* %changelog +* Fri Aug 01 2025 jchzhou - 14.3.1-5 +- Backport RISC-V RVA23 support, phase 2 + * Fri Aug 01 2025 jchzhou - 14.3.1-4 - Backport RISC-V RVA23 support, phase 1 -- Gitee