From 6f4977918a6eb440a56bd34eb0306131d56793f7 Mon Sep 17 00:00:00 2001 From: eastb233 Date: Mon, 28 Jun 2021 21:36:37 +0800 Subject: [PATCH 1/2] Fix ICEs when compiling simde - fix-PR83666-punt-BLKmode-when-expand_debug_expr.patch: New patch for bugfix - fix-AArch64-128-bit-immediate-ICEs.patch: Likewise - gcc.spec: Add new patch --- fix-AArch64-128-bit-immediate-ICEs.patch | 214 ++++++++++++++++++ ...-punt-BLKmode-when-expand_debug_expr.patch | 50 ++++ gcc.spec | 13 +- 3 files changed, 275 insertions(+), 2 deletions(-) create mode 100644 fix-AArch64-128-bit-immediate-ICEs.patch create mode 100644 fix-PR83666-punt-BLKmode-when-expand_debug_expr.patch diff --git a/fix-AArch64-128-bit-immediate-ICEs.patch b/fix-AArch64-128-bit-immediate-ICEs.patch new file mode 100644 index 0000000..298018c --- /dev/null +++ b/fix-AArch64-128-bit-immediate-ICEs.patch @@ -0,0 +1,214 @@ +This backport contains 3 patch from gcc main stream tree. +The commit id of these patchs list as following in the order of time. + +0001-Remove-from-movsi-di-ti-patterns.patch +ff76f0b5f6e6a4144fabb9ae984a9ee9dcaa2d08 + +0001-Improve-aarch64_legitimate_constant_p.patch +26895c21eb10cfd6c00285e13e6f13a75cccc1d9 + +0001-AArch64-PR82964-Fix-128-bit-immediate-ICEs.patch +c0bb5bc54feab4bac0df04f358ec9e839a32b2a2 + +diff -Nurp a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c +--- a/gcc/config/aarch64/aarch64.c 2021-06-20 21:43:53.688000000 -0400 ++++ b/gcc/config/aarch64/aarch64.c 2021-06-20 22:25:42.428000000 -0400 +@@ -2090,6 +2090,23 @@ aarch64_internal_mov_immediate (rtx dest + return num_insns; + } + ++/* Return whether imm is a 128-bit immediate which is simple enough to ++ expand inline. */ ++bool ++aarch64_mov128_immediate (rtx imm) ++{ ++ if (GET_CODE (imm) == CONST_INT) ++ return true; ++ ++ gcc_assert (CONST_WIDE_INT_NUNITS (imm) == 2); ++ ++ rtx lo = GEN_INT (CONST_WIDE_INT_ELT (imm, 0)); ++ rtx hi = GEN_INT (CONST_WIDE_INT_ELT (imm, 1)); ++ ++ return aarch64_internal_mov_immediate (NULL_RTX, lo, false, DImode) ++ + aarch64_internal_mov_immediate (NULL_RTX, hi, false, DImode) <= 4; ++} ++ + + void + aarch64_expand_mov_immediate (rtx dest, rtx imm) +@@ -10180,44 +10197,43 @@ aarch64_legitimate_pic_operand_p (rtx x) + return true; + } + +-/* Return true if X holds either a quarter-precision or +- floating-point +0.0 constant. */ +-static bool +-aarch64_valid_floating_const (machine_mode mode, rtx x) +-{ +- if (!CONST_DOUBLE_P (x)) +- return false; +- +- if (aarch64_float_const_zero_rtx_p (x)) +- return true; +- +- /* We only handle moving 0.0 to a TFmode register. */ +- if (!(mode == SFmode || mode == DFmode)) +- return false; +- +- return aarch64_float_const_representable_p (x); +-} ++/* Implement TARGET_LEGITIMATE_CONSTANT_P hook. Return true for constants ++ that should be rematerialized rather than spilled. */ + + static bool + aarch64_legitimate_constant_p (machine_mode mode, rtx x) + { ++ /* Support CSE and rematerialization of common constants. */ ++ if (CONST_INT_P (x) ++ || (CONST_DOUBLE_P (x) ++ && (mode == SFmode || mode == DFmode || mode == TFmode)) ++ || GET_CODE (x) == CONST_VECTOR) ++ return true; ++ + /* Do not allow vector struct mode constants. We could support + 0 and -1 easily, but they need support in aarch64-simd.md. */ +- if (TARGET_SIMD && aarch64_vect_struct_mode_p (mode)) ++ if (aarch64_vect_struct_mode_p (mode)) + return false; + +- /* This could probably go away because +- we now decompose CONST_INTs according to expand_mov_immediate. */ +- if ((GET_CODE (x) == CONST_VECTOR +- && aarch64_simd_valid_immediate (x, mode, false, NULL)) +- || CONST_INT_P (x) || aarch64_valid_floating_const (mode, x)) +- return !targetm.cannot_force_const_mem (mode, x); ++ /* Do not allow const (plus (anchor_symbol, const_int)). */ ++ if (GET_CODE (x) == CONST) ++ { ++ rtx offset; ++ ++ split_const (x, &x, &offset); + +- if (GET_CODE (x) == HIGH +- && aarch64_valid_symref (XEXP (x, 0), GET_MODE (XEXP (x, 0)))) ++ if (SYMBOL_REF_P (x) && SYMBOL_REF_ANCHOR_P (x)) ++ return false; ++ } ++ ++ if (GET_CODE (x) == HIGH) ++ x = XEXP (x, 0); ++ ++ /* Label references are always constant. */ ++ if (GET_CODE (x) == LABEL_REF) + return true; + +- return aarch64_constant_address_p (x); ++ return false; + } + + rtx +diff -Nurp a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md +--- a/gcc/config/aarch64/aarch64.md 2021-06-20 21:43:53.712000000 -0400 ++++ b/gcc/config/aarch64/aarch64.md 2021-06-20 22:22:37.848000000 -0400 +@@ -1131,9 +1131,9 @@ + + (define_insn "*movti_aarch64" + [(set (match_operand:TI 0 +- "nonimmediate_operand" "=r, *w,r ,*w,r,m,m,*w,m") ++ "nonimmediate_operand" "= r,w, r,w,r,m,m,w,m") + (match_operand:TI 1 +- "aarch64_movti_operand" " rn,r ,*w,*w,m,r,Z, m,*w"))] ++ "aarch64_movti_operand" " rUti,r, w,w,m,r,Z,m,w"))] + "(register_operand (operands[0], TImode) + || aarch64_reg_or_zero (operands[1], TImode))" + "@ +diff -Nurp a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h +--- a/gcc/config/aarch64/aarch64-protos.h 2021-06-20 21:43:53.584000000 -0400 ++++ b/gcc/config/aarch64/aarch64-protos.h 2021-06-20 22:22:37.844000000 -0400 +@@ -414,6 +414,8 @@ void aarch64_split_128bit_move (rtx, rtx + + bool aarch64_split_128bit_move_p (rtx, rtx); + ++bool aarch64_mov128_immediate (rtx); ++ + void aarch64_split_simd_combine (rtx, rtx, rtx); + + void aarch64_split_simd_move (rtx, rtx); +diff -Nurp a/gcc/config/aarch64/constraints.md b/gcc/config/aarch64/constraints.md +--- a/gcc/config/aarch64/constraints.md 2017-01-01 07:07:43.905435000 -0500 ++++ b/gcc/config/aarch64/constraints.md 2021-06-20 22:22:37.852000000 -0400 +@@ -69,6 +69,12 @@ + (and (match_code "const_int") + (match_test "aarch64_move_imm (ival, DImode)"))) + ++(define_constraint "Uti" ++ "A constant that can be used with a 128-bit MOV immediate operation." ++ (and (ior (match_code "const_int") ++ (match_code "const_wide_int")) ++ (match_test "aarch64_mov128_immediate (op)"))) ++ + (define_constraint "UsO" + "A constant that can be used with a 32-bit and operation." + (and (match_code "const_int") +diff -Nurp a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md +--- a/gcc/config/aarch64/predicates.md 2021-06-20 21:43:53.588000000 -0400 ++++ b/gcc/config/aarch64/predicates.md 2021-06-20 22:22:37.852000000 -0400 +@@ -224,15 +224,14 @@ + (match_test "aarch64_mov_operand_p (op, mode)"))))) + + (define_predicate "aarch64_movti_operand" +- (and (match_code "reg,subreg,mem,const_int") +- (ior (match_operand 0 "register_operand") +- (ior (match_operand 0 "memory_operand") +- (match_operand 0 "const_int_operand"))))) ++ (ior (match_operand 0 "register_operand") ++ (match_operand 0 "memory_operand") ++ (and (match_operand 0 "const_scalar_int_operand") ++ (match_test "aarch64_mov128_immediate (op)")))) + + (define_predicate "aarch64_reg_or_imm" +- (and (match_code "reg,subreg,const_int") +- (ior (match_operand 0 "register_operand") +- (match_operand 0 "const_int_operand")))) ++ (ior (match_operand 0 "register_operand") ++ (match_operand 0 "const_scalar_int_operand"))) + + ;; True for integer comparisons and for FP comparisons other than LTGT or UNEQ. + (define_special_predicate "aarch64_comparison_operator" +diff -Nurp a/gcc/testsuite/gcc.target/aarch64/pr78733.c b/gcc/testsuite/gcc.target/aarch64/pr78733.c +--- a/gcc/testsuite/gcc.target/aarch64/pr78733.c 2016-12-09 09:26:07.297066000 -0500 ++++ b/gcc/testsuite/gcc.target/aarch64/pr78733.c 2021-06-20 22:22:37.852000000 -0400 +@@ -1,10 +1,13 @@ + /* { dg-do compile } */ +-/* { dg-options "-O2 -mpc-relative-literal-loads" } */ ++/* { dg-options "-O2 -mcmodel=large -mpc-relative-literal-loads" } */ ++/* { dg-require-effective-target lp64 } */ ++/* { dg-skip-if "-mcmodel=large, no support for -fpic" { aarch64-*-* } { "-fpic" } { "" } } */ + + __int128 + t (void) + { +- return (__int128)1 << 80; ++ return ((__int128)0x123456789abcdef << 64) | 0xfedcba987654321; + } + + /* { dg-final { scan-assembler "adr" } } */ ++/* { dg-final { scan-assembler-not "adrp" } } */ +diff -Nurp a/gcc/testsuite/gcc.target/aarch64/pr79041-2.c b/gcc/testsuite/gcc.target/aarch64/pr79041-2.c +--- a/gcc/testsuite/gcc.target/aarch64/pr79041-2.c 2017-07-26 07:57:57.970160000 -0400 ++++ b/gcc/testsuite/gcc.target/aarch64/pr79041-2.c 2021-06-20 22:22:37.852000000 -0400 +@@ -1,11 +1,12 @@ + /* { dg-do compile } */ + /* { dg-options "-O2 -mcmodel=large -mpc-relative-literal-loads" } */ + /* { dg-require-effective-target lp64 } */ ++/* { dg-skip-if "-mcmodel=large, no support for -fpic" { aarch64-*-* } { "-fpic" } { "" } } */ + + __int128 + t (void) + { +- return (__int128)1 << 80; ++ return ((__int128)0x123456789abcdef << 64) | 0xfedcba987654321; + } + + /* { dg-final { scan-assembler "adr" } } */ diff --git a/fix-PR83666-punt-BLKmode-when-expand_debug_expr.patch b/fix-PR83666-punt-BLKmode-when-expand_debug_expr.patch new file mode 100644 index 0000000..e391836 --- /dev/null +++ b/fix-PR83666-punt-BLKmode-when-expand_debug_expr.patch @@ -0,0 +1,50 @@ +This backport contains 1 patch from gcc main stream tree. +The commit id of these patchs list as following in the order of time. + +0001-re-PR-debug-83666-ICE-SIGFPE-with-O2-g-param-sccvn-m.patch +c54af0682ce0881ecde74a3b7502287a53ced378 + +diff -Nurp a/gcc/cfgexpand.c b/gcc/cfgexpand.c +--- a/gcc/cfgexpand.c 2021-06-20 21:43:53.568000000 -0400 ++++ b/gcc/cfgexpand.c 2021-06-20 22:04:33.432000000 -0400 +@@ -4516,7 +4516,7 @@ expand_debug_expr (tree exp) + if (bitpos < 0) + return NULL; + +- if (GET_MODE (op0) == BLKmode) ++ if (GET_MODE (op0) == BLKmode || mode == BLKmode) + return NULL; + + if ((bitpos % BITS_PER_UNIT) == 0 +diff -Nurp a/gcc/testsuite/gcc.dg/pr83666.c b/gcc/testsuite/gcc.dg/pr83666.c +--- a/gcc/testsuite/gcc.dg/pr83666.c 1969-12-31 19:00:00.000000000 -0500 ++++ b/gcc/testsuite/gcc.dg/pr83666.c 2021-06-20 22:04:33.432000000 -0400 +@@ -0,0 +1,28 @@ ++/* PR debug/83666 */ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -g --param=sccvn-max-scc-size=10 -Wno-psabi" } */ ++ ++typedef int __attribute__ ((vector_size (64))) V; ++ ++int c, d; ++short e; ++V g; ++ ++V ++bar (void) ++{ ++ g[1] = d; ++ do ++ { ++ e += c; ++ g = g > 0; ++ } ++ while (g[1]); ++ return g; ++} ++ ++void ++foo (void) ++{ ++ int x = bar ()[3]; ++} diff --git a/gcc.spec b/gcc.spec index b4251a6..8f374d1 100644 --- a/gcc.spec +++ b/gcc.spec @@ -1,4 +1,4 @@ -%global DATE 20210719 +%global DATE 20211123 %define debug_package %{nil} %global gcc_version 7.3.0 @@ -37,7 +37,7 @@ Summary: Various compilers (C, C++, Objective-C, Java, ...) Name: gcc Version: 7.3.0 -Release: %{DATE}.41 +Release: %{DATE}.42 License: GPLv3+ and GPLv3+ with exceptions and GPLv2+ with exceptions and LGPLv2+ and BSD Group: Development/Languages #Source0: hcc-aarch64-linux-release.tar.bz2 @@ -88,6 +88,8 @@ Patch35: turn-on-funwind-tables-by-default.patch Patch36: fix-trivially_constructible-PR81589.patch Patch37: Add-full-steady_clock-support-to-condition_variable.patch Patch38: fix-pre-improve-fake-exit-edge-placement.patch +Patch39: fix-PR83666-punt-BLKmode-when-expand_debug_expr.patch +Patch40: fix-AArch64-128-bit-immediate-ICEs.patch #AutoReqProv: off AutoReq: true @@ -550,6 +552,8 @@ package or when debugging this package. %patch36 -p1 %patch37 -p1 %patch38 -p1 +%patch39 -p1 +%patch40 -p1 %if 0%{?_enable_debug_packages} cat > split-debuginfo.sh <<\EOF @@ -3290,6 +3294,11 @@ fi %changelog +* Tue Nov 23 2021 eastb233 - 7.3.0-20211123.42 +- fix-PR83666-punt-BLKmode-when-expand_debug_expr.patch: New patch for bugfix +- fix-AArch64-128-bit-immediate-ICEs.patch: Likewise +- gcc.spec: Add new patch + * Tue Jul 27 2021 yuanxin - 7.3.0-20210719.41 - Type:bugfix - ID:NA -- Gitee From fd4a4364cae720ce8f76bd5ed535180401cbae47 Mon Sep 17 00:00:00 2001 From: LiYanCheng <412998149@qq.com> Date: Tue, 23 Nov 2021 15:34:23 +0800 Subject: [PATCH 2/2] Backport PR c++/83227 - C++17 ICE with init-list derived-to-base conversion. --- ...3227-C-17-ICE-with-init-list-derived.patch | 81 +++++++++++++++++++ gcc.spec | 8 +- 2 files changed, 88 insertions(+), 1 deletion(-) create mode 100644 PR-c-83227-C-17-ICE-with-init-list-derived.patch diff --git a/PR-c-83227-C-17-ICE-with-init-list-derived.patch b/PR-c-83227-C-17-ICE-with-init-list-derived.patch new file mode 100644 index 0000000..2f8c008 --- /dev/null +++ b/PR-c-83227-C-17-ICE-with-init-list-derived.patch @@ -0,0 +1,81 @@ +From ac9de5374b4e2f4aa45c0e4f720a9727b44ab534 Mon Sep 17 00:00:00 2001 +From: LiYanCheng <412998149@qq.com> +Date: Sat, 20 Nov 2021 15:50:38 +0800 +Subject: [PATCH] Backport PR c++/83227 - C++17 ICE with init-list + derived-to-base conversion. + +--- + gcc/cp/ChangeLog | 6 ++++++ + gcc/cp/call.c | 9 +++++---- + gcc/testsuite/g++.dg/cpp0x/initlist98.C | 17 +++++++++++++++++ + 3 files changed, 28 insertions(+), 4 deletions(-) + create mode 100644 gcc/testsuite/g++.dg/cpp0x/initlist98.C + +diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog +index b5d15c7b6..6aa0075b5 100644 +--- a/gcc/cp/ChangeLog ++++ b/gcc/cp/ChangeLog +@@ -1,3 +1,9 @@ ++2018-02-15 Jason Merrill ++ ++ PR c++/83227 - C++17 ICE with init-list derived-to-base conversion. ++ * call.c (convert_like_real): Don't use the copy-list-initialization ++ shortcut for ck_base. ++ + 2018-01-25 Release Manager + + * GCC 7.3.0 released. +diff --git a/gcc/cp/call.c b/gcc/cp/call.c +index 56f6b9323..0993c2acf 100644 +--- a/gcc/cp/call.c ++++ b/gcc/cp/call.c +@@ -6886,6 +6886,11 @@ convert_like_real (conversion *convs, tree expr, tree fn, int argnum, + && DECL_INHERITED_CTOR (current_function_decl)) + return expr; + ++ if (TREE_CODE (expr) == TARGET_EXPR ++ && TARGET_EXPR_LIST_INIT_P (expr)) ++ /* Copy-list-initialization doesn't actually involve a copy. */ ++ return expr; ++ + /* Fall through. */ + case ck_base: + if (convs->kind == ck_base && !convs->need_temporary_p) +@@ -6911,10 +6916,6 @@ convert_like_real (conversion *convs, tree expr, tree fn, int argnum, + flags |= LOOKUP_ONLYCONVERTING; + if (convs->rvaluedness_matches_p) + flags |= LOOKUP_PREFER_RVALUE; +- if (TREE_CODE (expr) == TARGET_EXPR +- && TARGET_EXPR_LIST_INIT_P (expr)) +- /* Copy-list-initialization doesn't actually involve a copy. */ +- return expr; + expr = build_temp (expr, totype, flags, &diag_kind, complain); + if (diag_kind && complain) + { +diff --git a/gcc/testsuite/g++.dg/cpp0x/initlist98.C b/gcc/testsuite/g++.dg/cpp0x/initlist98.C +new file mode 100644 +index 000000000..4f2fcd202 +--- /dev/null ++++ b/gcc/testsuite/g++.dg/cpp0x/initlist98.C +@@ -0,0 +1,17 @@ ++// PR c++/83227 ++// { dg-do compile { target c++11 } } ++ ++#include ++ ++template struct f { ++ f(std::initializer_list) {} ++}; ++ ++struct h {}; ++struct i : h { ++ i(); ++}; ++void foo(f); ++int main() { ++ foo({i{}}); ++} +-- +2.27.0 + + diff --git a/gcc.spec b/gcc.spec index 8f374d1..582c890 100644 --- a/gcc.spec +++ b/gcc.spec @@ -37,7 +37,7 @@ Summary: Various compilers (C, C++, Objective-C, Java, ...) Name: gcc Version: 7.3.0 -Release: %{DATE}.42 +Release: %{DATE}.43 License: GPLv3+ and GPLv3+ with exceptions and GPLv2+ with exceptions and LGPLv2+ and BSD Group: Development/Languages #Source0: hcc-aarch64-linux-release.tar.bz2 @@ -90,6 +90,7 @@ Patch37: Add-full-steady_clock-support-to-condition_variable.patch Patch38: fix-pre-improve-fake-exit-edge-placement.patch Patch39: fix-PR83666-punt-BLKmode-when-expand_debug_expr.patch Patch40: fix-AArch64-128-bit-immediate-ICEs.patch +Patch41: PR-c-83227-C-17-ICE-with-init-list-derived.patch #AutoReqProv: off AutoReq: true @@ -554,6 +555,7 @@ package or when debugging this package. %patch38 -p1 %patch39 -p1 %patch40 -p1 +%patch41 -p1 %if 0%{?_enable_debug_packages} cat > split-debuginfo.sh <<\EOF @@ -3294,6 +3296,10 @@ fi %changelog +* Tue Nov 23 2021 liyancheng <412998149@qq.com> - 7.3.0-20211122.43 +- PR-c-83227-C-17-ICE-with-init-list-derived.patch: New file +- gcc.spec: Add new patch + * Tue Nov 23 2021 eastb233 - 7.3.0-20211123.42 - fix-PR83666-punt-BLKmode-when-expand_debug_expr.patch: New patch for bugfix - fix-AArch64-128-bit-immediate-ICEs.patch: Likewise -- Gitee