diff --git a/0036-remove-unused-csr.patch b/0036-remove-unused-csr.patch new file mode 100644 index 0000000000000000000000000000000000000000..8749efb19aa9c5d3a48ab7634657139a480d377c --- /dev/null +++ b/0036-remove-unused-csr.patch @@ -0,0 +1,292 @@ +diff -uNr gcc-10.3.0.org/gcc/config/loongarch/constraints.md gcc-10.3.0/gcc/config/loongarch/constraints.md +--- gcc-10.3.0.org/gcc/config/loongarch/constraints.md 2022-04-06 17:10:57.747036120 +0800 ++++ gcc-10.3.0/gcc/config/loongarch/constraints.md 2022-04-09 10:44:02.355999239 +0800 +@@ -120,8 +120,8 @@ + (define_register_constraint "e" "JALR_REGS" + "@internal") + +-(define_register_constraint "q" "LVZ_REGS" +- "A general-purpose register except for $r0 and $r1 for lvz.") ++(define_register_constraint "q" "CSR_REGS" ++ "A general-purpose register except for $r0 and $r1 for csr.") + + (define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : NO_REGS" + "A floating-point register (if available).") +diff -uNr gcc-10.3.0.org/gcc/config/loongarch/loongarch-builtins.c gcc-10.3.0/gcc/config/loongarch/loongarch-builtins.c +--- gcc-10.3.0.org/gcc/config/loongarch/loongarch-builtins.c 2022-04-06 17:10:57.773035833 +0800 ++++ gcc-10.3.0/gcc/config/loongarch/loongarch-builtins.c 2022-04-09 10:44:02.355999239 +0800 +@@ -134,7 +134,6 @@ + }; + + AVAIL_ALL (hard_float, TARGET_HARD_FLOAT_ABI) +-AVAIL_ALL (lvz, TARGET_LVZ) + + /* Construct a loongarch_builtin_description from the given arguments. + +@@ -170,14 +169,6 @@ + LARCH_BUILTIN (INSN, f, #INSN, LARCH_BUILTIN_DIRECT_NO_TARGET, \ + FUNCTION_TYPE, AVAIL) + +-/* Define an LVZ LARCH_BUILTIN_DIRECT function __builtin_lvz_ +- for instruction CODE_FOR_lvz_. FUNCTION_TYPE is a builtin_description +- field. */ +-#define LVZ_BUILTIN(INSN, FUNCTION_TYPE) \ +- { CODE_FOR_lvz_ ## INSN, LARCH_FP_COND_f, \ +- "__builtin_lvz_" #INSN, LARCH_BUILTIN_DIRECT, \ +- FUNCTION_TYPE, loongarch_builtin_avail_lvz } +- + /* Loongson support loongarch64r6 */ + #define CODE_FOR_loongarch_fmax_sf CODE_FOR_smaxsf3 + #define CODE_FOR_loongarch_fmax_df CODE_FOR_smaxdf3 +@@ -279,14 +270,6 @@ + DIRECT_BUILTIN (crcc_w_w_w, LARCH_SI_FTYPE_SI_SI, default), + DIRECT_BUILTIN (crcc_w_d_w, LARCH_SI_FTYPE_DI_SI, default), + +- /* Built-in functions for LVZ. */ +- LVZ_BUILTIN (gcsrrd, LARCH_USI_FTYPE_USI), +- LVZ_BUILTIN (gcsrwr, LARCH_USI_FTYPE_USI_USI), +- LVZ_BUILTIN (gcsrxchg, LARCH_USI_FTYPE_USI_USI_USI), +- LVZ_BUILTIN (dgcsrrd, LARCH_UDI_FTYPE_USI), +- LVZ_BUILTIN (dgcsrwr, LARCH_UDI_FTYPE_UDI_USI), +- LVZ_BUILTIN (dgcsrxchg, LARCH_UDI_FTYPE_UDI_UDI_USI), +- + DIRECT_BUILTIN (csrrd, LARCH_USI_FTYPE_USI, default), + DIRECT_BUILTIN (dcsrrd, LARCH_UDI_FTYPE_USI, default), + DIRECT_BUILTIN (csrwr, LARCH_USI_FTYPE_USI_USI, default), +diff -uNr gcc-10.3.0.org/gcc/config/loongarch/loongarch.h gcc-10.3.0/gcc/config/loongarch/loongarch.h +--- gcc-10.3.0.org/gcc/config/loongarch/loongarch.h 2022-04-06 17:10:57.752036065 +0800 ++++ gcc-10.3.0/gcc/config/loongarch/loongarch.h 2022-04-09 10:44:02.355999239 +0800 +@@ -337,18 +337,9 @@ + {"fix-loongson3-llsc", "%{!mfix-loongson3-llsc: \ + %{!mno-fix-loongson3-llsc:-m%(VALUE)}}" } + ++#define BASE_DRIVER_SELF_SPECS "" + +-/* A spec that infers the: +- -mlvz setting from a -march=gs464v argument. */ +-#define BASE_DRIVER_SELF_SPECS \ +- LARCH_ASE_LVZ_SPEC +- +-#define LARCH_ASE_LVZ_SPEC \ +- "%{!mno-lvz: \ +- %{march=gs464v: -mlvz}}" +- +-#define DRIVER_SELF_SPECS \ +- BASE_DRIVER_SELF_SPECS ++#define DRIVER_SELF_SPECS "" + + /* from N_LARCH */ + #define ABI_SPEC \ +@@ -398,9 +389,6 @@ + /* ISA has instructions for accessing top part of 64-bit fp regs. */ + #define ISA_HAS_MXFRH (!TARGET_FLOAT32) + +-/* The LoongArch VZ is available. */ +-#define ISA_HAS_LVZ (TARGET_LVZ) +- + /* Tell collect what flags to pass to nm. */ + #ifndef NM_FLAGS + #define NM_FLAGS "-Bn" +@@ -927,7 +915,7 @@ + SIBCALL_REGS, /* SIBCALL_REGS */ + JALR_REGS, /* JALR_REGS */ + GR_REGS, /* integer registers */ +- LVZ_REGS, /* integer registers except for $r0 and $r1 for lvz. */ ++ CSR_REGS, /* integer registers except for $r0 and $r1 for csr. */ + FP_REGS, /* floating point registers */ + ST_REGS, /* status registers (fp status) */ + FRAME_REGS, /* $arg and $frame */ +diff -uNr gcc-10.3.0.org/gcc/config/loongarch/loongarch.md gcc-10.3.0/gcc/config/loongarch/loongarch.md +--- gcc-10.3.0.org/gcc/config/loongarch/loongarch.md 2022-04-06 17:10:57.774035822 +0800 ++++ gcc-10.3.0/gcc/config/loongarch/loongarch.md 2022-04-09 10:44:02.356999227 +0800 +@@ -4275,9 +4275,6 @@ + + (include "sync.md") + +-; LoongArch csr +-(include "lvz.md") +- + (define_c_enum "unspec" [ + UNSPEC_ADDRESS_FIRST + ]) +diff -uNr gcc-10.3.0.org/gcc/config/loongarch/loongarch.opt gcc-10.3.0/gcc/config/loongarch/loongarch.opt +--- gcc-10.3.0.org/gcc/config/loongarch/loongarch.opt 2022-04-06 17:10:57.754036043 +0800 ++++ gcc-10.3.0/gcc/config/loongarch/loongarch.opt 2022-04-09 10:44:02.356999227 +0800 +@@ -185,10 +185,6 @@ + Target Report Var(TARGET_LOAD_STORE_PAIRS) Init(1) + Enable load/store bonding. + +-mlvz +-Target Report Var(TARGET_LVZ) +-Use LoongArch Privileged state (LVZ) instructions. +- + mmax-inline-memcpy-size= + Target Joined RejectNegative UInteger Var(loongarch_max_inline_memcpy_size) Init(1024) + -mmax-inline-memcpy-size=SIZE Set the max size of memcpy to inline, default is 1024. +diff -uNr gcc-10.3.0.org/gcc/config/loongarch/lvzintrin.h gcc-10.3.0/gcc/config/loongarch/lvzintrin.h +--- gcc-10.3.0.org/gcc/config/loongarch/lvzintrin.h 2022-04-06 17:10:57.754036043 +0800 ++++ gcc-10.3.0/gcc/config/loongarch/lvzintrin.h 1970-01-01 08:00:00.000000000 +0800 +@@ -1,87 +0,0 @@ +-/* Intrinsics for LoongArch vz operations. +- +- Copyright (C) 2019 Free Software Foundation, Inc. +- Contributed by xuchenghua@loongson.cn. +- +- This file is part of GCC. +- +- GCC is free software; you can redistribute it and/or modify it +- under the terms of the GNU General Public License as published +- by the Free Software Foundation; either version 3, or (at your +- option) any later version. +- +- GCC is distributed in the hope that it will be useful, but WITHOUT +- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +- License for more details. +- +- Under Section 7 of GPL version 3, you are granted additional +- permissions described in the GCC Runtime Library Exception, version +- 3.1, as published by the Free Software Foundation. +- +- You should have received a copy of the GNU General Public License and +- a copy of the GCC Runtime Library Exception along with this program; +- see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +- . */ +- +-#ifndef _GCC_LOONGARCH_LVZ_H +-#define _GCC_LOONGARCH_LVZ_H +- +-#define __lvz_gcsrrd __builtin_lvz_gcsrrd +-#define __lvz_gcsrwr __builtin_lvz_gcsrwr +-#define __lvz_gcsrxchg __builtin_lvz_gcsrxchg +-#define __lvz_dgcsrrd __builtin_lvz_dgcsrrd +-#define __lvz_dgcsrwr __builtin_lvz_dgcsrwr +-#define __lvz_dgcsrxchg __builtin_lvz_dgcsrxchg +- +-extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +-__builtin_lvz_gtlbsrch (void) +-{ +- __asm__ volatile ("gtlbsrch\n\t"); +-} +-#define __lvz_gtlbsrch __builtin_lvz_gtlbsrch +- +-extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +-__builtin_lvz_gtlbrd (void) +-{ +- __asm__ volatile ("gtlbrd\n\t"); +-} +-#define __lvz_gtlbrd __builtin_lvz_gtlbrd +- +-extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +-__builtin_lvz_gtlbwr (void) +-{ +- __asm__ volatile ("gtlbwr\n\t"); +-} +-#define __lvz_gtlbwr __builtin_lvz_gtlbwr +- +-extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +-__builtin_lvz_gtlbfill (void) +-{ +- __asm__ volatile ("gtlbfill\n\t"); +-} +-#define __lvz_gtlbfill __builtin_lvz_gtlbfill +- +-extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +-__builtin_lvz_gtlbclr (void) +-{ +- __asm__ volatile ("gtlbclr\n\t"); +-} +-#define __lvz_gtlbclr __builtin_lvz_gtlbclr +- +-extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +-__builtin_lvz_gtlbflush (void) +-{ +- __asm__ volatile ("gtlbflush\n\t"); +-} +-#define __lvz_gtlbflush __builtin_lvz_gtlbflush +- +-extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +-__builtin_lvz_hvcl (void) +-{ +- __asm__ volatile ("hvcl\n\t"); +-} +-#define __lvz_hvcl __builtin_lvz_hvcl +- +- +-#endif /*_GCC_LOONGARCH_LVZ_H */ +diff -uNr gcc-10.3.0.org/gcc/config/loongarch/lvz.md gcc-10.3.0/gcc/config/loongarch/lvz.md +--- gcc-10.3.0.org/gcc/config/loongarch/lvz.md 2022-04-06 17:10:57.754036043 +0800 ++++ gcc-10.3.0/gcc/config/loongarch/lvz.md 1970-01-01 08:00:00.000000000 +0800 +@@ -1,60 +0,0 @@ +-;; Machine Description for LoongArch vz instructions. +-;; Copyright (C) 1989-2014 Free Software Foundation, Inc. +-;; Contributed by xuchenghua@loongson.cn +- +-;; This file is part of GCC. +- +-;; GCC is free software; you can redistribute it and/or modify +-;; it under the terms of the GNU General Public License as published by +-;; the Free Software Foundation; either version 3, or (at your option) +-;; any later version. +- +-;; GCC is distributed in the hope that it will be useful, +-;; but WITHOUT ANY WARRANTY; without even the implied warranty of +-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-;; GNU General Public License for more details. +- +-;; You should have received a copy of the GNU General Public License +-;; along with GCC; see the file COPYING3. If not see +-;; . +- +-(define_c_enum "unspec" [ +- ;; lvz +- UNSPEC_LVZ_GCSRXCHG +- UNSPEC_LVZ_GCSRRD +- UNSPEC_LVZ_GCSRWR +- +-]) +- +-(define_insn "lvz_

gcsrxchg" +- [(set (match_operand:GPR 0 "register_operand" "=d") +- (unspec_volatile:GPR +- [(match_operand:GPR 1 "register_operand" "0") +- (match_operand:GPR 2 "register_operand" "q") +- (match_operand 3 "const_uimm14_operand")] +- UNSPEC_LVZ_GCSRXCHG))] +- "ISA_HAS_LVZ" +- "gcsrxchg\t%0,%2,%3" +- [(set_attr "type" "load") +- (set_attr "mode" "")]) +- +-(define_insn "lvz_

gcsrrd" +- [(set (match_operand:GPR 0 "register_operand" "=d") +- (unspec_volatile:GPR [(match_operand 1 "const_uimm14_operand")] +- UNSPEC_LVZ_GCSRRD))] +- "ISA_HAS_LVZ" +- "gcsrrd\t%0,%1" +- [(set_attr "type" "load") +- (set_attr "mode" "")]) +- +-(define_insn "lvz_

gcsrwr" +- [(set (match_operand:GPR 0 "register_operand" "=d") +- (unspec_volatile:GPR +- [(match_operand:GPR 1 "register_operand" "0") +- (match_operand 2 "const_uimm14_operand")] +- UNSPEC_LVZ_GCSRWR))] +- "ISA_HAS_LVZ" +- "gcsrwr\t%0,%2" +- [(set_attr "type" "store") +- (set_attr "mode" "")]) +- +diff -uNr gcc-10.3.0.org/gcc/config.gcc gcc-10.3.0/gcc/config.gcc +--- gcc-10.3.0.org/gcc/config.gcc 2022-04-06 17:10:57.756036021 +0800 ++++ gcc-10.3.0/gcc/config.gcc 2022-04-09 10:44:02.355999239 +0800 +@@ -480,7 +480,7 @@ + loongarch*-*-*) + cpu_type=loongarch + d_target_objs="loongarch-d.o" +- extra_headers="lvzintrin.h larchintrin.h" ++ extra_headers="larchintrin.h" + extra_objs="frame-header-opt.o loongarch-c.o loongarch-builtins.o" + extra_options="${extra_options} g.opt fused-madd.opt loongarch/loongarch-tables.opt" + diff --git a/gcc.spec b/gcc.spec index 97c3e996c3f05f5fcfaa269709a4922b9b618acb..34bca746e18bfce69758042678ffb7ce60299df8 100644 --- a/gcc.spec +++ b/gcc.spec @@ -61,7 +61,7 @@ Summary: Various compilers (C, C++, Objective-C, ...) Name: gcc Version: %{gcc_version} -Release: 12 +Release: 13 License: GPLv3+ and GPLv3+ with exceptions and GPLv2+ with exceptions and LGPLv2+ and BSD URL: https://gcc.gnu.org @@ -151,6 +151,7 @@ Patch32: 0032-Autoprefetch-Prune-invaild-loops-containing-edges-wh.patch Patch33: 0033-Add-Loongarch-backend-support.patch Patch34: 0034-Loongarch-add-clobber-for-csr-builtin.patch Patch35: 0035-Fixup-missing-file-error.patch +Patch36: 0036-remove-unused-csr.patch %global gcc_target_platform %{_arch}-linux-gnu @@ -627,6 +628,7 @@ not stable, so plugins must be rebuilt any time GCC is updated. %patch33 -p1 %patch34 -p1 %patch35 -p1 +%patch36 -p1 %build @@ -2596,6 +2598,12 @@ end %doc rpm.doc/changelogs/libcc1/ChangeLog* %changelog +* Wed Apr 20 2022 lixing - 10.3.1-13 +- Type:requirements +- ID:NA +- SUG:NA +- DESC:Remove unused csr definition + * Mon Apr 06 2022 lixing - 10.3.1-12 - Type:requirements - ID:NA