diff --git a/0189-Add-hip11-CPU-pipeline-scheduling.patch b/0189-Add-hip11-CPU-pipeline-scheduling.patch
new file mode 100644
index 0000000000000000000000000000000000000000..b4532667804f363473e686fe370d44c97ef8e468
--- /dev/null
+++ b/0189-Add-hip11-CPU-pipeline-scheduling.patch
@@ -0,0 +1,739 @@
+From 431f80e6d3a323e3382f73a80bf7fc7ee7a73f02 Mon Sep 17 00:00:00 2001
+From: XingYuShuai <1150775134@qq.com>
+Date: Mon, 26 Feb 2024 20:34:06 +0800
+Subject: [PATCH] Add hip11 CPU pipeline scheduling
+
+This patch adds an mcpu: hip11. It has been tested on aarch64
+and no regressions from this patch.
+---
+ gcc/config/aarch64/aarch64-cores.def | 3 +-
+ gcc/config/aarch64/aarch64-cost-tables.h | 104 ++++++
+ gcc/config/aarch64/aarch64-tune.md | 2 +-
+ gcc/config/aarch64/aarch64.c | 83 +++++
+ gcc/config/aarch64/aarch64.md | 1 +
+ gcc/config/aarch64/hip11.md | 418 +++++++++++++++++++++++
+ gcc/doc/invoke.texi | 2 +-
+ 7 files changed, 610 insertions(+), 3 deletions(-)
+ create mode 100644 gcc/config/aarch64/hip11.md
+
+diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def
+index 9c2902924..53125f6bd 100644
+--- a/gcc/config/aarch64/aarch64-cores.def
++++ b/gcc/config/aarch64/aarch64-cores.def
+@@ -123,7 +123,7 @@ AARCH64_CORE("octeontx2f95mm", octeontx2f95mm, cortexa57, 8_2A, AARCH64_FL_FOR_
+ AARCH64_CORE("a64fx", a64fx, a64fx, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_SVE, a64fx, 0x46, 0x001, -1)
+
+ /* HiSilicon ('H') cores. */
+-AARCH64_CORE("tsv110", tsv110, tsv110, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_CRYPTO | AARCH64_FL_F16 | AARCH64_FL_AES | AARCH64_FL_SHA2, tsv110, 0x48, 0xd01, -1)
++AARCH64_CORE("tsv110", tsv110, tsv110, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_CRYPTO | AARCH64_FL_F16 | AARCH64_FL_AES | AARCH64_FL_SHA2, tsv110, 0x48, 0xd01, -1)
+
+ /* ARMv8.3-A Architecture Processors. */
+
+@@ -141,6 +141,7 @@ AARCH64_CORE("saphira", saphira, saphira, 8_4A, AARCH64_FL_FOR_ARCH8_
+
+ /* Armv8.5-A Architecture Processors. */
+ AARCH64_CORE("neoverse-n2", neoversen2, cortexa57, 8_5A, AARCH64_FL_FOR_ARCH8_5 | AARCH64_FL_I8MM | AARCH64_FL_BF16 | AARCH64_FL_F16 | AARCH64_FL_SVE | AARCH64_FL_SVE2 | AARCH64_FL_SVE2_BITPERM | AARCH64_FL_RNG | AARCH64_FL_MEMTAG, neoversen2, 0x41, 0xd49, -1)
++AARCH64_CORE("hip11", hip11, hip11, 8_5A, AARCH64_FL_FOR_ARCH8_5| AARCH64_FL_SVE | AARCH64_FL_SVE2 | AARCH64_FL_F16, hip11, 0x48, 0xd22, -1)
+
+ /* ARMv8-A big.LITTLE implementations. */
+
+diff --git a/gcc/config/aarch64/aarch64-cost-tables.h b/gcc/config/aarch64/aarch64-cost-tables.h
+index c6805717f..377650be0 100644
+--- a/gcc/config/aarch64/aarch64-cost-tables.h
++++ b/gcc/config/aarch64/aarch64-cost-tables.h
+@@ -541,6 +541,110 @@ const struct cpu_cost_table tsv110_extra_costs =
+ }
+ };
+
++const struct cpu_cost_table hip11_extra_costs =
++{
++ /* ALU */
++ {
++ 0, /* arith. */
++ 0, /* logical. */
++ 0, /* shift. */
++ 0, /* shift_reg. */
++ COSTS_N_INSNS (1), /* arith_shift. */
++ COSTS_N_INSNS (1), /* arith_shift_reg. */
++ COSTS_N_INSNS (1), /* log_shift. */
++ COSTS_N_INSNS (1), /* log_shift_reg. */
++ 0, /* extend. */
++ COSTS_N_INSNS (1), /* extend_arith. */
++ 0, /* bfi. */
++ 0, /* bfx. */
++ 0, /* clz. */
++ 0, /* rev. */
++ 0, /* non_exec. */
++ true /* non_exec_costs_exec. */
++ },
++
++ {
++ /* MULT SImode */
++ {
++ COSTS_N_INSNS (2), /* simple. */
++ COSTS_N_INSNS (2), /* flag_setting. */
++ COSTS_N_INSNS (2), /* extend. */
++ COSTS_N_INSNS (2), /* add. */
++ COSTS_N_INSNS (2), /* extend_add. */
++ COSTS_N_INSNS (11) /* idiv. */
++ },
++ /* MULT DImode */
++ {
++ COSTS_N_INSNS (3), /* simple. */
++ 0, /* flag_setting (N/A). */
++ COSTS_N_INSNS (3), /* extend. */
++ COSTS_N_INSNS (3), /* add. */
++ COSTS_N_INSNS (3), /* extend_add. */
++ COSTS_N_INSNS (19) /* idiv. */
++ }
++ },
++ /* LD/ST */
++ {
++ COSTS_N_INSNS (3), /* load. */
++ COSTS_N_INSNS (4), /* load_sign_extend. */
++ COSTS_N_INSNS (3), /* ldrd. */
++ COSTS_N_INSNS (3), /* ldm_1st. */
++ 1, /* ldm_regs_per_insn_1st. */
++ 2, /* ldm_regs_per_insn_subsequent. */
++ COSTS_N_INSNS (4), /* loadf. */
++ COSTS_N_INSNS (4), /* loadd. */
++ COSTS_N_INSNS (4), /* load_unaligned. */
++ 0, /* store. */
++ 0, /* strd. */
++ 0, /* stm_1st. */
++ 1, /* stm_regs_per_insn_1st. */
++ 2, /* stm_regs_per_insn_subsequent. */
++ 0, /* storef. */
++ 0, /* stored. */
++ COSTS_N_INSNS (1), /* store_unaligned. */
++ COSTS_N_INSNS (4), /* loadv. */
++ COSTS_N_INSNS (4) /* storev. */
++ },
++ {
++ /* FP SFmode */
++ {
++ COSTS_N_INSNS (10), /* div. */
++ COSTS_N_INSNS (4), /* mult. */
++ COSTS_N_INSNS (4), /* mult_addsub. */
++ COSTS_N_INSNS (4), /* fma. */
++ COSTS_N_INSNS (4), /* addsub. */
++ COSTS_N_INSNS (1), /* fpconst. */
++ COSTS_N_INSNS (1), /* neg. */
++ COSTS_N_INSNS (1), /* compare. */
++ COSTS_N_INSNS (2), /* widen. */
++ COSTS_N_INSNS (2), /* narrow. */
++ COSTS_N_INSNS (2), /* toint. */
++ COSTS_N_INSNS (1), /* fromint. */
++ COSTS_N_INSNS (2) /* roundint. */
++ },
++ /* FP DFmode */
++ {
++ COSTS_N_INSNS (17), /* div. */
++ COSTS_N_INSNS (4), /* mult. */
++ COSTS_N_INSNS (6), /* mult_addsub. */
++ COSTS_N_INSNS (6), /* fma. */
++ COSTS_N_INSNS (3), /* addsub. */
++ COSTS_N_INSNS (1), /* fpconst. */
++ COSTS_N_INSNS (1), /* neg. */
++ COSTS_N_INSNS (1), /* compare. */
++ COSTS_N_INSNS (2), /* widen. */
++ COSTS_N_INSNS (2), /* narrow. */
++ COSTS_N_INSNS (2), /* toint. */
++ COSTS_N_INSNS (1), /* fromint. */
++ COSTS_N_INSNS (2) /* roundint. */
++ }
++ },
++ /* Vector */
++ {
++ COSTS_N_INSNS (1) /* alu. */
++ }
++};
++
+ const struct cpu_cost_table a64fx_extra_costs =
+ {
+ /* ALU */
+diff --git a/gcc/config/aarch64/aarch64-tune.md b/gcc/config/aarch64/aarch64-tune.md
+index 7fda2294b..f33a3330d 100644
+--- a/gcc/config/aarch64/aarch64-tune.md
++++ b/gcc/config/aarch64/aarch64-tune.md
+@@ -1,5 +1,5 @@
+ ;; -*- buffer-read-only: t -*-
+ ;; Generated automatically by gentune.sh from aarch64-cores.def
+ (define_attr "tune"
+- "cortexa34,cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,octeontx,octeontxt81,octeontxt83,thunderxt81,thunderxt83,emag,xgene1,falkor,qdf24xx,exynosm1,phecda,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,cortexa76ae,cortexa77,cortexa65,cortexa65ae,ares,neoversen1,neoversee1,octeontx2,octeontx2t98,octeontx2t96,octeontx2t93,octeontx2f95,octeontx2f95n,octeontx2f95mm,a64fx,tsv110,thunderx3t110,zeus,neoversev1,saphira,neoversen2,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55,cortexa76cortexa55"
++ "cortexa34,cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,octeontx,octeontxt81,octeontxt83,thunderxt81,thunderxt83,emag,xgene1,falkor,qdf24xx,exynosm1,phecda,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,cortexa76ae,cortexa77,cortexa65,cortexa65ae,ares,neoversen1,neoversee1,octeontx2,octeontx2t98,octeontx2t96,octeontx2t93,octeontx2f95,octeontx2f95n,octeontx2f95mm,a64fx,tsv110,thunderx3t110,zeus,neoversev1,saphira,neoversen2,hip11,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55,cortexa76cortexa55"
+ (const (symbol_ref "((enum attr_tune) aarch64_tune)")))
+diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
+index da4983236..938948f29 100644
+--- a/gcc/config/aarch64/aarch64.c
++++ b/gcc/config/aarch64/aarch64.c
+@@ -448,6 +448,22 @@ static const struct cpu_addrcost_table tsv110_addrcost_table =
+ 0, /* imm_offset */
+ };
+
++static const struct cpu_addrcost_table hip11_addrcost_table =
++{
++ {
++ 1, /* hi */
++ 0, /* si */
++ 0, /* di */
++ 1, /* ti */
++ },
++ 0, /* pre_modify */
++ 0, /* post_modify */
++ 0, /* register_offset */
++ 1, /* register_sextend */
++ 1, /* register_zextend */
++ 0, /* imm_offset */
++};
++
+ static const struct cpu_addrcost_table qdf24xx_addrcost_table =
+ {
+ {
+@@ -575,6 +591,16 @@ static const struct cpu_regmove_cost tsv110_regmove_cost =
+ 2 /* FP2FP */
+ };
+
++static const struct cpu_regmove_cost hip11_regmove_cost =
++{
++ 1, /* GP2GP */
++ /* Avoid the use of slow int<->fp moves for spilling by setting
++ their cost higher than memmov_cost. */
++ 2, /* GP2FP */
++ 3, /* FP2GP */
++ 2 /* FP2FP */
++};
++
+ static const struct cpu_regmove_cost a64fx_regmove_cost =
+ {
+ 1, /* GP2GP */
+@@ -664,6 +690,25 @@ static const struct cpu_vector_cost tsv110_vector_cost =
+ 1 /* cond_not_taken_branch_cost */
+ };
+
++static const struct cpu_vector_cost hip11_vector_cost =
++{
++ 1, /* scalar_int_stmt_cost */
++ 1, /* scalar_fp_stmt_cost */
++ 5, /* scalar_load_cost */
++ 1, /* scalar_store_cost */
++ 2, /* vec_int_stmt_cost */
++ 2, /* vec_fp_stmt_cost */
++ 2, /* vec_permute_cost */
++ 5, /* vec_to_scalar_cost */
++ 5, /* scalar_to_vec_cost */
++ 5, /* vec_align_load_cost */
++ 5, /* vec_unalign_load_cost */
++ 1, /* vec_unalign_store_cost */
++ 1, /* vec_store_cost */
++ 1, /* cond_taken_branch_cost */
++ 1 /* cond_not_taken_branch_cost */
++};
++
+ /* Generic costs for vector insn classes. */
+ static const struct cpu_vector_cost cortexa57_vector_cost =
+ {
+@@ -902,6 +947,17 @@ static const cpu_prefetch_tune tsv110_prefetch_tune =
+ -1 /* default_opt_level */
+ };
+
++static const cpu_prefetch_tune hip11_prefetch_tune =
++{
++ 0, /* num_slots */
++ 64, /* l1_cache_size */
++ 64, /* l1_cache_line_size */
++ 512, /* l2_cache_size */
++ true, /* prefetch_dynamic_strides */
++ -1, /* minimum_stride */
++ -1 /* default_opt_level */
++};
++
+ static const cpu_prefetch_tune xgene1_prefetch_tune =
+ {
+ 8, /* num_slots */
+@@ -1196,6 +1252,33 @@ static const struct tune_params tsv110_tunings =
+ &tsv110_prefetch_tune
+ };
+
++static const struct tune_params hip11_tunings =
++{
++ &hip11_extra_costs,
++ &hip11_addrcost_table,
++ &hip11_regmove_cost,
++ &hip11_vector_cost,
++ &generic_branch_cost,
++ &generic_approx_modes,
++ SVE_512, /* sve_width */
++ 4, /* memmov_cost */
++ 4, /* issue_rate */
++ (AARCH64_FUSE_AES_AESMC | AARCH64_FUSE_ALU_BRANCH
++ | AARCH64_FUSE_ALU_CBZ), /* fusible_ops */
++ "16", /* function_align. */
++ "4", /* jump_align. */
++ "8", /* loop_align. */
++ 2, /* int_reassoc_width. */
++ 4, /* fp_reassoc_width. */
++ 1, /* vec_reassoc_width. */
++ 2, /* min_div_recip_mul_sf. */
++ 2, /* min_div_recip_mul_df. */
++ 0, /* max_case_values. */
++ tune_params::AUTOPREFETCHER_WEAK, /* autoprefetcher_model. */
++ (AARCH64_EXTRA_TUNE_PREFER_ADVSIMD_AUTOVEC), /* tune_flags. */
++ &hip11_prefetch_tune
++};
++
+ static const struct tune_params xgene1_tunings =
+ {
+ &xgene1_extra_costs,
+diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
+index 7c2562f49..38af8d000 100644
+--- a/gcc/config/aarch64/aarch64.md
++++ b/gcc/config/aarch64/aarch64.md
+@@ -452,6 +452,7 @@
+ (include "../arm/cortex-a57.md")
+ (include "../arm/exynos-m1.md")
+ (include "falkor.md")
++(include "hip11.md")
+ (include "saphira.md")
+ (include "thunderx.md")
+ (include "../arm/xgene1.md")
+diff --git a/gcc/config/aarch64/hip11.md b/gcc/config/aarch64/hip11.md
+new file mode 100644
+index 000000000..57944fbc2
+--- /dev/null
++++ b/gcc/config/aarch64/hip11.md
+@@ -0,0 +1,418 @@
++;; hip11 pipeline description
++;; Copyright (C) 2018-2024 Free Software Foundation, Inc.
++;;
++;; This file is part of GCC.
++;;
++;; GCC is free software; you can redistribute it and/or modify it
++;; under the terms of the GNU General Public License as published by
++;; the Free Software Foundation; either version 3, or (at your option)
++;; any later version.
++;;
++;; GCC is distributed in the hope that it will be useful, but
++;; WITHOUT ANY WARRANTY; without even the implied warranty of
++;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
++;; General Public License for more details.
++;;
++;; You should have received a copy of the GNU General Public License
++;; along with GCC; see the file COPYING3. If not see
++;; .
++
++(define_automaton "hip11")
++
++;; The hip11 core is modelled as issues pipeline that has
++;; the following functional units.
++;; 1. Three pipelines for integer operations: ALU1, ALU2, ALU3
++
++(define_cpu_unit "hip11_alu1_issue" "hip11")
++(define_reservation "hip11_alu1" "hip11_alu1_issue")
++
++(define_cpu_unit "hip11_alu2_issue" "hip11")
++(define_reservation "hip11_alu2" "hip11_alu2_issue")
++
++(define_cpu_unit "hip11_alu3_issue" "hip11")
++(define_reservation "hip11_alu3" "hip11_alu3_issue")
++
++(define_reservation "hip11alu" "hip11_alu1|hip11_alu2|hip11_alu3")
++
++;; 2. One pipeline for complex integer operations: MDU
++
++(define_cpu_unit "hip11_mdu_issue" "hip11")
++(define_reservation "hip11_mdu" "hip11_mdu_issue")
++
++;; 3. Two asymmetric pipelines for Asimd and FP operations: FSU1, FSU2
++(define_automaton "hip11_fsu")
++
++(define_cpu_unit "hip11_fsu1_issue"
++ "hip11_fsu")
++(define_cpu_unit "hip11_fsu2_issue"
++ "hip11_fsu")
++
++(define_reservation "hip11_fsu1" "hip11_fsu1_issue")
++(define_reservation "hip11_fsu2" "hip11_fsu2_issue")
++(define_reservation "hip11_fsu_pipe" "hip11_fsu1|hip11_fsu2")
++
++;; 4. Two pipeline for branch operations but same with alu2 and alu3: BRU1, BRU2
++
++;; 5. Two pipelines for load and store operations: LS1, LS2.
++
++(define_cpu_unit "hip11_ls1_issue" "hip11")
++(define_cpu_unit "hip11_ls2_issue" "hip11")
++(define_reservation "hip11_ls1" "hip11_ls1_issue")
++(define_reservation "hip11_ls2" "hip11_ls2_issue")
++
++;; Block all issue queues.
++
++(define_reservation "hip11_block" "hip11_fsu1_issue + hip11_fsu2_issue
++ + hip11_mdu_issue + hip11_alu1_issue
++ + hip11_alu2_issue + hip11_alu3_issue + hip11_ls1_issue + hip11_ls2_issue")
++
++;; Branch execution Unit
++;;
++(define_insn_reservation "hip11_branch" 1
++ (and (eq_attr "tune" "hip11")
++ (eq_attr "type" "branch"))
++ "hip11_alu2|hip11_alu3")
++
++(define_insn_reservation "hip11_return_from_subroutine" 6
++ (and (eq_attr "tune" "hip11")
++ (eq_attr "type" "branch")
++ (eq_attr "sls_length" "retbr"))
++ "hip11_mdu,(hip11_alu2|hip11_alu3)")
++
++ ;; Simple Execution Unit:
++;;
++;; Simple ALU without shift
++(define_insn_reservation "hip11_alu" 1
++ (and (eq_attr "tune" "hip11")
++ (eq_attr "type" "alu_imm,logic_imm,\
++ alu_sreg,logic_reg,\
++ adc_imm,adc_reg,\
++ adr,bfm,clz,rbit,rev,\
++ shift_imm,shift_reg,\
++ mov_imm,mov_reg,\
++ mvn_imm,mvn_reg,\
++ mrs,multiple,csel,\
++ rotate_imm"))
++ "hip11_alu1|hip11_alu2|hip11_alu3")
++
++(define_insn_reservation "hip11_alus" 1
++ (and (eq_attr "tune" "hip11")
++ (eq_attr "type" "alus_imm,logics_imm,\
++ alus_sreg,logics_reg,\
++ adcs_imm,adcs_reg"))
++ "hip11_alu2|hip11_alu3")
++
++;; ALU ops with shift
++(define_insn_reservation "hip11_alu_shift" 2
++ (and (eq_attr "tune" "hip11")
++ (eq_attr "type" "extend,\
++ alu_shift_imm,alu_shift_reg,\
++ crc,logic_shift_imm,logic_shift_reg,\
++ mov_shift,mvn_shift,\
++ mov_shift_reg,mvn_shift_reg"))
++ "hip11_mdu")
++
++(define_insn_reservation "hip11_alus_shift" 2
++ (and (eq_attr "tune" "hip11")
++ (eq_attr "type" "alus_shift_imm,alus_shift_reg,\
++ logics_shift_imm,logics_shift_reg"))
++ "hip11_alu2|hip11_alu3")
++
++;; Multiplies instructions
++(define_insn_reservation "hip11_mult" 3
++ (and (eq_attr "tune" "hip11")
++ (ior (eq_attr "mul32" "yes")
++ (eq_attr "widen_mul64" "yes")))
++ "hip11_mdu")
++
++;; Integer divide
++(define_insn_reservation "hip11_div" 10
++ (and (eq_attr "tune" "hip11")
++ (eq_attr "type" "udiv,sdiv"))
++ "hip11_mdu")
++
++(define_insn_reservation "hip11_mla" 4
++ (and (eq_attr "tune" "hip11")
++ (eq_attr "type" "mla,smlal,umlal,smull,umull"))
++ "hip11_mdu")
++
++;; Block all issue pipes for a cycle
++(define_insn_reservation "hip11_block" 1
++ (and (eq_attr "tune" "hip11")
++ (eq_attr "type" "block"))
++ "hip11_block")
++
++;; Load-store execution Unit
++;;
++(define_insn_reservation "hip11_load1" 4
++ (and (eq_attr "tune" "hip11")
++ (eq_attr "type" "load_4,load_8,load_16"))
++ "hip11_ls1|hip11_ls2")
++
++(define_insn_reservation "hip11_fp_load" 5
++ (and (eq_attr "tune" "hip11")
++ (eq_attr "type" "f_loads,f_loadd"))
++ "hip11_ls1|hip11_ls2")
++
++(define_insn_reservation "hip11_neon_ld1_single" 7
++ (and (eq_attr "tune" "hip11")
++ (eq_attr "type" "neon_load1_one_lane,neon_load1_one_lane_q,\
++ neon_load1_all_lanes,neon_load1_all_lanes_q"))
++ "(hip11_ls1|hip11_ls2)+hip11_fsu1")
++
++(define_insn_reservation "hip11_neon_ld1_1reg" 5
++ (and (eq_attr "tune" "hip11")
++ (eq_attr "type" "neon_load1_1reg,neon_load1_1reg_q"))
++ "hip11_ls1|hip11_ls2")
++
++(define_insn_reservation "hip11_neon_ld1_2reg" 6
++ (and (eq_attr "tune" "hip11")
++ (eq_attr "type" "neon_load1_2reg,neon_load1_2reg_q"))
++ "hip11_ls1|hip11_ls2")
++
++(define_insn_reservation "hip11_neon_ld1_3reg" 7
++ (and (eq_attr "tune" "hip11")
++ (eq_attr "type" "neon_load1_3reg,neon_load1_3reg_q"))
++ "hip11_ls1|hip11_ls2")
++
++(define_insn_reservation "hip11_neon_ld1_4reg" 8
++ (and (eq_attr "tune" "hip11")
++ (eq_attr "type" "neon_load1_4reg,neon_load1_4reg_q"))
++ "hip11_ls1|hip11_ls2")
++
++(define_insn_reservation "hip11_neon_ld2" 8
++ (and (eq_attr "tune" "hip11")
++ (eq_attr "type" "neon_load2_one_lane,neon_load2_one_lane_q,\
++ neon_load2_all_lanes,neon_load2_all_lanes_q,\
++ neon_load2_2reg,neon_load2_2reg_q,\
++ neon_load2_4reg,neon_load2_4reg_q"))
++ "(hip11_ls1|hip11_ls2)+hip11_fsu1")
++
++(define_insn_reservation "hip11_neon_ld3_single" 9
++ (and (eq_attr "tune" "hip11")
++ (eq_attr "type" "neon_load3_one_lane,neon_load3_one_lane_q,\
++ neon_load3_all_lanes,neon_load3_all_lanes_q"))
++ "(hip11_ls1|hip11_ls2)+hip11_fsu1")
++
++(define_insn_reservation "hip11_neon_ld3_multiple" 13
++ (and (eq_attr "tune" "hip11")
++ (eq_attr "type" "neon_load3_3reg,neon_load3_3reg_q"))
++ "(hip11_ls1|hip11_ls2)+hip11_fsu1")
++
++(define_insn_reservation "hip11_neon_ld4_single" 10
++ (and (eq_attr "tune" "hip11")
++ (eq_attr "type" "neon_load4_one_lane,neon_load4_one_lane_q,\
++ neon_load4_all_lanes,neon_load4_all_lanes_q"))
++ "(hip11_ls1|hip11_ls2)+hip11_fsu1")
++
++(define_insn_reservation "hip11_neon_ld4_multiple" 11
++ (and (eq_attr "tune" "hip11")
++ (eq_attr "type" "neon_load4_4reg,neon_load4_4reg_q"))
++ "(hip11_ls1|hip11_ls2)+hip11_fsu1")
++
++;; Stores of up to two words.
++(define_insn_reservation "hip11_store1" 1
++ (and (eq_attr "tune" "hip11")
++ (eq_attr "type" "store_4,store_8,store_16,\
++ f_stored,f_stores"))
++ "hip11_ls1|hip11_ls2")
++
++;; Floating-Point Operations.
++(define_insn_reservation "hip11_fp_arith" 2
++ (and (eq_attr "tune" "hip11")
++ (eq_attr "type" "ffariths,ffarithd,f_minmaxs,\
++ f_minmaxd,fadds,faddd,neon_fcadd"))
++ "hip11_fsu_pipe")
++
++(define_insn_reservation "hip11_fp_mul" 3
++ (and (eq_attr "tune" "hip11")
++ (eq_attr "type" "neon_fp_mul_d,neon_fp_mul_d_q,\
++ neon_fp_mul_s_scalar,neon_fp_mul_s_scalar_q,\
++ neon_fp_mul_d_scalar_q,fmuld,fmuls"))
++ "hip11_fsu_pipe")
++
++(define_insn_reservation "hip11_fp_cmp" 2
++ (and (eq_attr "tune" "hip11")
++ (eq_attr "type" "fccmpd,fccmps"))
++ "hip11alu,hip11_fsu_pipe")
++
++(define_insn_reservation "hip11_fp_csel" 2
++ (and (eq_attr "tune" "hip11")
++ (eq_attr "type" "fcsel"))
++ "hip11alu,hip11_fsu1")
++
++(define_insn_reservation "hip11_fp_fcmp" 1
++ (and (eq_attr "tune" "hip11")
++ (eq_attr "type" "fcmpd,fcmps"))
++ "hip11_fsu_pipe")
++
++(define_insn_reservation "hip11_fp_divs" 7
++ (and (eq_attr "tune" "hip11")
++ (eq_attr "type" "fdivs"))
++ "hip11_fsu1")
++
++(define_insn_reservation "hip11_fp_divd" 10
++ (and (eq_attr "tune" "hip11")
++ (eq_attr "type" "fdivd"))
++ "hip11_fsu1")
++
++(define_insn_reservation "hip11_fp_sqrts" 9
++ (and (eq_attr "tune" "hip11")
++ (eq_attr "type" "fsqrts"))
++ "hip11_fsu1")
++
++(define_insn_reservation "hip11_fp_sqrtd" 15
++ (and (eq_attr "tune" "hip11")
++ (eq_attr "type" "fsqrtd"))
++ "hip11_fsu1")
++
++(define_insn_reservation "hip11_fp_mac" 4
++ (and (eq_attr "tune" "hip11")
++ (eq_attr "type" "fmacs,ffmas,fmacd,ffmad"))
++ "hip11_fsu_pipe")
++
++(define_insn_reservation "hip11_fp_mov" 1
++ (and (eq_attr "tune" "hip11")
++ (eq_attr "type" "fmov,neon_dup,neon_dup_q,\
++ neon_from_gp,neon_from_gp_q,\
++ neon_ins,neon_ins_q,\
++ neon_to_gp,neon_to_gp_q,\
++ neon_move,neon_move_q,\
++ neon_rev,neon_rev_q,\
++ neon_permute,neon_permute_q,\
++ neon_shift_imm_narrow_q,\
++ neon_ext,neon_ext_q,\
++ neon_rbit,\
++ crypto_sha3,neon_tbl1,neon_tbl1_q,\
++ neon_tbl2_q,f_mcr,neon_tst,neon_tst_q,\
++ neon_move_narrow_q"))
++ "hip11_fsu1")
++
++;; ASIMD instructions
++(define_insn_reservation "hip11_asimd_simple_arithmetic" 2
++ (and (eq_attr "tune" "hip11")
++ (eq_attr "type" "neon_abs,neon_abs_q,neon_neg,neon_neg_q,\
++ neon_abd,neon_abd_q,\
++ neon_add_long,neon_sub_long,neon_sub_widen,neon_add_widen,\
++ neon_add_halve_narrow_q,neon_sub_halve_narrow_q,\
++ neon_arith_acc,neon_arith_acc_q,\
++ neon_compare,neon_compare_q,\
++ neon_compare_zero,neon_compare_zero_q,\
++ neon_minmax,neon_minmax_q,\
++ neon_logic,neon_logic_q,\
++ neon_reduc_add,neon_reduc_add_q,\
++ neon_reduc_minmax,neon_reduc_minmax_q,\
++ neon_fp_to_int_s,neon_fp_to_int_s_q,\
++ neon_fp_to_int_d,neon_fp_to_int_d_q,\
++ neon_fp_cvt_widen_s,\
++ neon_fp_cvt_narrow_d_q,\
++ neon_cls,neon_cls_q,\
++ neon_cnt,neon_cnt_q,\
++ f_rints,f_rintd,f_cvtf2i,f_cvt,\
++ neon_tbl3,neon_fp_round_s,neon_fp_round_s_q,\
++ neon_fp_round_d,neon_fp_round_d_q,\
++ neon_int_to_fp_s,neon_fp_recpe_s,neon_fp_recpe_s_q,\
++ neon_fp_recpe_d,neon_fp_recpe_d_q,\
++ neon_fp_cvt_narrow_s_q,\
++ crypto_aese,crypto_aesmc,\
++ crypto_sha1_fast,crypto_sha1_xor,\
++ crypto_sha1_slow,\
++ crypto_sha256_fast,\
++ crypto_sha512,crypto_sm3,\
++ neon_qabs,neon_qabs_q,\
++ neon_qneg,neon_qneg_q,\
++ neon_qadd,neon_qadd_q,\
++ neon_qsub,neon_qsub_q,\
++ neon_add_halve,neon_add_halve_q,\
++ neon_sub_halve,neon_sub_halve_q,\
++ neon_fp_reduc_minmax_s,neon_fp_reduc_minmax_s_q,\
++ neon_fp_reduc_minmax_d,neon_fp_reduc_minmax_d_q,\
++ neon_fp_rsqrte_s,neon_fp_rsqrte_s_q,\
++ neon_fp_rsqrte_d,neon_fp_rsqrte_d_q"))
++ "hip11_fsu1")
++
++(define_insn_reservation "hip11_asimd_complex_arithmetic" 4
++ (and (eq_attr "tune" "hip11")
++ (eq_attr "type" "neon_mul_b,neon_mul_b_q,\
++ neon_mul_h,neon_mul_h_q,\
++ neon_mul_s,neon_mul_s_q,\
++ neon_mla_b,neon_mla_b_q,\
++ neon_mla_h,neon_mla_h_q,\
++ neon_mla_s,\
++ neon_mla_h_scalar,neon_mla_h_scalar_q,\
++ neon_mla_s_scalar,neon_mla_s_scalar_q,\
++ neon_sat_mul_h_scalar,neon_sat_mul_h_scalar_q,\
++ neon_sat_mul_s_scalar,neon_sat_mul_s_scalar_q,\
++ neon_sat_mul_b,neon_sat_mul_b_q,\
++ neon_sat_mul_h,neon_sat_mul_h_q,\
++ neon_sat_mul_s,neon_sat_mul_s_q,\
++ neon_mla_b_long,neon_mla_h_long,neon_mla_s_long,\
++ neon_mul_b_long,neon_mul_h_long,neon_mul_s_long,\
++ neon_sat_mla_b_long,neon_sat_mla_h_long,neon_sat_mla_s_long,\
++ neon_sat_mla_h_scalar_long,neon_sat_mla_s_scalar_long,\
++ neon_sat_mul_b_long,neon_sat_mul_h_long,neon_sat_mul_s_long,\
++ neon_sat_mul_h_scalar_long,neon_sat_mul_s_scalar_long,\
++ crypto_pmull,\
++ neon_sat_shift_reg,neon_sat_shift_reg_q,\
++ neon_shift_reg,neon_shift_reg_q,\
++ neon_shift_imm,neon_shift_imm_q,\
++ neon_shift_imm_long,\
++ neon_sat_shift_imm,neon_sat_shift_imm_q,\
++ neon_sat_shift_imm_narrow_q,\
++ neon_shift_acc,neon_shift_acc_q,\
++ crypto_sha256_slow"))
++ "hip11_fsu1")
++
++(define_insn_reservation "hip11_asimd_fp_compare" 2
++ (and (eq_attr "tune" "hip11")
++ (eq_attr "type" "neon_fp_abs_s,neon_fp_abs_s_q,\
++ neon_fp_abs_d,neon_fp_abs_d_q,\
++ neon_fp_neg_s,neon_fp_neg_s_q,\
++ neon_fp_neg_d,neon_fp_neg_d_q,\
++ neon_fp_compare_s,neon_fp_compare_s_q,\
++ neon_fp_compare_d,neon_fp_compare_d_q,\
++ neon_fp_minmax_s,neon_fp_minmax_s_q,\
++ neon_fp_minmax_d,neon_fp_minmax_d_q,\
++ neon_fp_addsub_s,neon_fp_addsub_s_q,\
++ neon_fp_addsub_d,neon_fp_addsub_d_q,\
++ neon_fp_reduc_add_s,neon_fp_reduc_add_s_q,\
++ neon_fp_reduc_add_d,neon_fp_reduc_add_d_q,\
++ neon_fp_abd_s,neon_fp_abd_s_q,\
++ neon_fp_abd_d,neon_fp_abd_d_q"))
++ "hip11_fsu_pipe")
++
++(define_insn_reservation "hip11_asimd_fdiv" 10
++ (and (eq_attr "tune" "hip11")
++ (eq_attr "type" "neon_fp_div_s,neon_fp_div_s_q,\
++ neon_fp_div_d,neon_fp_div_d_q"))
++ "hip11_fsu1")
++
++(define_insn_reservation "hip11_asimd_fsqrt" 15
++ (and (eq_attr "tune" "hip11")
++ (eq_attr "type" "neon_fp_sqrt_s,neon_fp_sqrt_s_q,\
++ neon_fp_sqrt_d,neon_fp_sqrt_d_q"))
++ "hip11_fsu1")
++
++(define_insn_reservation "hip11_asimd_fp_multiply_add" 4
++ (and (eq_attr "tune" "hip11")
++ (eq_attr "type" "neon_fp_mla_s,neon_fp_mla_s_q,\
++ neon_fp_mla_d,neon_fp_mla_d_q,\
++ neon_fp_mla_s_scalar,neon_fp_mla_s_scalar_q,\
++ neon_fp_mul_s,neon_fp_mul_s_q,neon_fcmla,\
++ neon_fp_recps_s,neon_fp_recps_s_q,\
++ neon_fp_recps_d,neon_fp_recps_d_q,\
++ neon_fp_rsqrts_s,neon_fp_rsqrts_s_q,\
++ neon_fp_rsqrts_d,neon_fp_rsqrts_d_q"))
++ "hip11_fsu_pipe")
++
++(define_insn_reservation "hip11_asimd_frecpx" 3
++ (and (eq_attr "tune" "hip11")
++ (eq_attr "type" "neon_fp_recpx_s,neon_fp_recpx_s_q,\
++ neon_fp_recpx_d,neon_fp_recpx_d_q,neon_tbl4,\
++ neon_dot,neon_dot_q"))
++ "hip11_fsu1")
++
++(define_insn_reservation "hip11_asimd_mmla" 6
++ (and (eq_attr "tune" "hip11")
++ (eq_attr "type" "neon_mla_s_q"))
++ "hip11_fsu1")
+diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
+index a0a84c20b..ce0dd2ff6 100644
+--- a/gcc/doc/invoke.texi
++++ b/gcc/doc/invoke.texi
+@@ -17049,7 +17049,7 @@ performance of the code. Permissible values for this option are:
+ @samp{octeontx2}, @samp{octeontx2t98}, @samp{octeontx2t96}
+ @samp{octeontx2t93}, @samp{octeontx2f95}, @samp{octeontx2f95n},
+ @samp{octeontx2f95mm},
+-@samp{a64fx},
++@samp{a64fx},@samp{hip11}
+ @samp{thunderx}, @samp{thunderxt88},
+ @samp{thunderxt88p1}, @samp{thunderxt81}, @samp{tsv110},
+ @samp{thunderxt83}, @samp{thunderx2t99}, @samp{thunderx3t110}, @samp{zeus},
+--
+2.33.0
+
diff --git a/gcc.spec b/gcc.spec
index 5b438aab3cfbea4a762a38c2d4ce0994f2199e1d..6c2b1de9d73b58e72f8bb96676b737afe4e3032c 100644
--- a/gcc.spec
+++ b/gcc.spec
@@ -61,7 +61,7 @@
Summary: Various compilers (C, C++, Objective-C, ...)
Name: gcc
Version: %{gcc_version}
-Release: 51
+Release: 52
License: GPLv3+ and GPLv3+ with exceptions and GPLv2+ with exceptions and LGPLv2+ and BSD
URL: https://gcc.gnu.org
@@ -296,6 +296,7 @@ Patch185: 0185-Fix-fail-in-IPA-prefetch-src-openEuler-gcc-I8RV7T.patch
Patch186: 0186-Loop-CRC-Solving-the-problem-of-insufficient-CRC-tab.patch
Patch187: 0187-Add-IPA-prefetch-test.patch
Patch188: 0188-Fix-fails-in-ICP-for-src-openEuler-gcc-I90P7M-I91CZ8.patch
+Patch189: 0189-Add-hip11-CPU-pipeline-scheduling.patch
%global gcc_target_platform %{_arch}-linux-gnu
@@ -937,6 +938,7 @@ not stable, so plugins must be rebuilt any time GCC is updated.
%patch186 -p1
%patch187 -p1
%patch188 -p1
+%patch189 -p1
%build
@@ -2961,6 +2963,12 @@ end
%doc rpm.doc/changelogs/libcc1/ChangeLog*
%changelog
+* Mon Apr 8 2024 Chenhui Zheng - 10.3.1-52
+- Type:Sync
+- ID:NA
+- SUG:NA
+- DESC: Sync patch from openeuler/gcc
+
* Fri Feb 23 2024 Chenhui Zheng - 10.3.1-51
- Type:Sync
- ID:NA