diff --git a/0379-x86-64-Don-t-use-temp-for-argument-in-a-TImode-regis.patch b/0379-x86-64-Don-t-use-temp-for-argument-in-a-TImode-regis.patch new file mode 100644 index 0000000000000000000000000000000000000000..075dbbbd70151733ce2ce69fb41af7222d87aa1a --- /dev/null +++ b/0379-x86-64-Don-t-use-temp-for-argument-in-a-TImode-regis.patch @@ -0,0 +1,119 @@ +From 3466859f47306e3e3006e810cc5a7fb64be2266a Mon Sep 17 00:00:00 2001 +From: "H.J. Lu" +Date: Fri, 6 Sep 2024 05:24:07 -0700 +Subject: [PATCH 1/4] x86-64: Don't use temp for argument in a TImode register + +Don't use temp for a PARALLEL BLKmode argument of an EXPR_LIST expression +in a TImode register. Otherwise, the TImode variable will be put in +the GPR save area which guarantees only 8-byte alignment. + +gcc/ + + PR target/116621 + * config/i386/i386.cc (ix86_gimplify_va_arg): Don't use temp for + a PARALLEL BLKmode container of an EXPR_LIST expression in a + TImode register. + +gcc/testsuite/ + + PR target/116621 + * gcc.target/i386/pr116621.c: New test. + +Signed-off-by: H.J. Lu +(cherry picked from commit fa7bbb065c63aa802e0bbb04d605407dad58cf94) +--- + gcc/config/i386/i386.cc | 22 ++++++++++-- + gcc/testsuite/gcc.target/i386/pr116621.c | 43 ++++++++++++++++++++++++ + 2 files changed, 63 insertions(+), 2 deletions(-) + create mode 100644 gcc/testsuite/gcc.target/i386/pr116621.c + +diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc +index e2743e0bd..8a5730a6b 100644 +--- a/gcc/config/i386/i386.cc ++++ b/gcc/config/i386/i386.cc +@@ -4780,13 +4780,31 @@ ix86_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p, + + examine_argument (nat_mode, type, 0, &needed_intregs, &needed_sseregs); + +- need_temp = (!REG_P (container) ++ bool container_in_reg = false; ++ if (REG_P (container)) ++ container_in_reg = true; ++ else if (GET_CODE (container) == PARALLEL ++ && GET_MODE (container) == BLKmode ++ && XVECLEN (container, 0) == 1) ++ { ++ /* Check if it is a PARALLEL BLKmode container of an EXPR_LIST ++ expression in a TImode register. In this case, temp isn't ++ needed. Otherwise, the TImode variable will be put in the ++ GPR save area which guarantees only 8-byte alignment. */ ++ rtx x = XVECEXP (container, 0, 0); ++ if (GET_CODE (x) == EXPR_LIST ++ && REG_P (XEXP (x, 0)) ++ && XEXP (x, 1) == const0_rtx) ++ container_in_reg = true; ++ } ++ ++ need_temp = (!container_in_reg + && ((needed_intregs && TYPE_ALIGN (type) > 64) + || TYPE_ALIGN (type) > 128)); + + /* In case we are passing structure, verify that it is consecutive block + on the register save area. If not we need to do moves. */ +- if (!need_temp && !REG_P (container)) ++ if (!need_temp && !container_in_reg) + { + /* Verify that all registers are strictly consecutive */ + if (SSE_REGNO_P (REGNO (XEXP (XVECEXP (container, 0, 0), 0)))) +diff --git a/gcc/testsuite/gcc.target/i386/pr116621.c b/gcc/testsuite/gcc.target/i386/pr116621.c +new file mode 100644 +index 000000000..704266458 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/i386/pr116621.c +@@ -0,0 +1,43 @@ ++/* { dg-do run } */ ++/* { dg-options "-O2" } */ ++ ++#include ++#include ++ ++union S8302 ++{ ++ union ++ { ++ double b; ++ int c; ++ } a; ++ long double d; ++ unsigned short int f[5]; ++}; ++ ++union S8302 s8302; ++extern void check8302va (int i, ...); ++ ++int ++main (void) ++{ ++ memset (&s8302, '\0', sizeof (s8302)); ++ s8302.a.b = -221438.250000; ++ check8302va (1, s8302); ++ return 0; ++} ++ ++__attribute__((noinline, noclone)) ++void ++check8302va (int z, ...) ++{ ++ union S8302 arg, *p; ++ va_list ap; ++ ++ __builtin_va_start (ap, z); ++ p = &s8302; ++ arg = __builtin_va_arg (ap, union S8302); ++ if (p->a.b != arg.a.b) ++ __builtin_abort (); ++ __builtin_va_end (ap); ++} +-- +2.31.1 + diff --git a/0380-x86-Don-t-use-address-override-with-segment-regsiter.patch b/0380-x86-Don-t-use-address-override-with-segment-regsiter.patch new file mode 100644 index 0000000000000000000000000000000000000000..88301aa517daeb34458d960bfbd703bdc655be42 --- /dev/null +++ b/0380-x86-Don-t-use-address-override-with-segment-regsiter.patch @@ -0,0 +1,126 @@ +From 9b75fdadfe3541634accd204d3ec5d8573978acf Mon Sep 17 00:00:00 2001 +From: "H.J. Lu" +Date: Wed, 25 Sep 2024 16:39:04 +0800 +Subject: [PATCH 2/4] x86: Don't use address override with segment regsiter + +Address override only applies to the (reg32) part in the thread address +fs:(reg32). Don't rewrite thread address like + +(set (reg:CCZ 17 flags) + (compare:CCZ (reg:SI 98 [ __gmpfr_emax.0_1 ]) + (mem/c:SI (plus:SI (plus:SI (unspec:SI [ + (const_int 0 [0]) + ] UNSPEC_TP) + (reg:SI 107)) + (const:SI (unspec:SI [ + (symbol_ref:SI ("previous_emax") [flags 0x1a] ) + ] UNSPEC_DTPOFF))) [1 previous_emax+0 S4 A32]))) + +if address override is used to avoid the invalid memory operand like + + cmpl %fs:previous_emax@dtpoff(%eax), %r12d + +gcc/ + + PR target/116839 + * config/i386/i386.cc (ix86_rewrite_tls_address_1): Make it + static. Return if TLS address is thread register plus an integer + register. + +gcc/testsuite/ + + PR target/116839 + * gcc.target/i386/pr116839.c: New file. + +Signed-off-by: H.J. Lu +(cherry picked from commit c79cc30862d7255ca15884aa956d1ccfa279d86a) +--- + gcc/config/i386/i386.cc | 9 ++++- + gcc/testsuite/gcc.target/i386/pr116839.c | 48 ++++++++++++++++++++++++ + 2 files changed, 56 insertions(+), 1 deletion(-) + create mode 100644 gcc/testsuite/gcc.target/i386/pr116839.c + +diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc +index 8a5730a6b..0b9556f8e 100644 +--- a/gcc/config/i386/i386.cc ++++ b/gcc/config/i386/i386.cc +@@ -11786,7 +11786,7 @@ ix86_tls_address_pattern_p (rtx op) + } + + /* Rewrite *LOC so that it refers to a default TLS address space. */ +-void ++static void + ix86_rewrite_tls_address_1 (rtx *loc) + { + subrtx_ptr_iterator::array_type array; +@@ -11808,6 +11808,13 @@ ix86_rewrite_tls_address_1 (rtx *loc) + if (GET_CODE (u) == UNSPEC + && XINT (u, 1) == UNSPEC_TP) + { ++ /* NB: Since address override only applies to the ++ (reg32) part in fs:(reg32), return if address ++ override is used. */ ++ if (Pmode != word_mode ++ && REG_P (XEXP (*x, 1 - i))) ++ return; ++ + addr_space_t as = DEFAULT_TLS_SEG_REG; + + *x = XEXP (*x, 1 - i); +diff --git a/gcc/testsuite/gcc.target/i386/pr116839.c b/gcc/testsuite/gcc.target/i386/pr116839.c +new file mode 100644 +index 000000000..e5df82562 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/i386/pr116839.c +@@ -0,0 +1,48 @@ ++/* { dg-do compile { target { ! ia32 } } } */ ++/* { dg-require-effective-target maybe_x32 } */ ++/* { dg-options "-mx32 -O2 -fPIC -mtls-dialect=gnu2" } */ ++/* { dg-final { scan-assembler-not "cmpl\[ \t\]+%fs:previous_emax@dtpoff\\(%eax\\)" } } */ ++ ++typedef long mpfr_prec_t; ++typedef long mpfr_exp_t; ++typedef struct { ++ mpfr_prec_t _mpfr_prec; ++} __mpfr_struct; ++typedef __mpfr_struct mpfr_t[1]; ++extern _Thread_local mpfr_exp_t __gmpfr_emax; ++static _Thread_local mpfr_exp_t previous_emax; ++static _Thread_local mpfr_t bound_emax; ++extern const mpfr_t __gmpfr_const_log2_RNDD; ++extern const mpfr_t __gmpfr_const_log2_RNDU; ++ ++typedef enum { ++ MPFR_RNDN=0, ++ MPFR_RNDZ, ++ MPFR_RNDU, ++ MPFR_RNDD, ++ MPFR_RNDA, ++ MPFR_RNDF, ++ MPFR_RNDNA=-1 ++} mpfr_rnd_t; ++typedef __mpfr_struct *mpfr_ptr; ++typedef const __mpfr_struct *mpfr_srcptr; ++void mpfr_mul (mpfr_ptr, mpfr_srcptr, mpfr_rnd_t); ++ ++void ++foo (void) ++{ ++ mpfr_exp_t saved_emax; ++ ++ if (__gmpfr_emax != previous_emax) ++ { ++ saved_emax = __gmpfr_emax; ++ ++ bound_emax->_mpfr_prec = 32; ++ ++ mpfr_mul (bound_emax, saved_emax < 0 ? ++ __gmpfr_const_log2_RNDD : __gmpfr_const_log2_RNDU, ++ MPFR_RNDU); ++ previous_emax = saved_emax; ++ __gmpfr_emax = saved_emax; ++ } ++} +-- +2.31.1 + diff --git a/0381-x86-Disable-stack-protector-for-naked-functions.patch b/0381-x86-Disable-stack-protector-for-naked-functions.patch new file mode 100644 index 0000000000000000000000000000000000000000..dd50ce1d53ab145fce7678f05b3de084b8be47de --- /dev/null +++ b/0381-x86-Disable-stack-protector-for-naked-functions.patch @@ -0,0 +1,77 @@ +From 8ff948ada01311776617730bd62434ac2c9d6ef5 Mon Sep 17 00:00:00 2001 +From: "H.J. Lu" +Date: Fri, 4 Oct 2024 16:21:15 +0800 +Subject: [PATCH 3/4] x86: Disable stack protector for naked functions + +Since naked functions should not enable stack protector, define +TARGET_STACK_PROTECT_RUNTIME_ENABLED_P to disable stack protector +for naked functions. + +gcc/ + + PR target/116962 + * config/i386/i386.cc (ix86_stack_protect_runtime_enabled_p): New + function. + (TARGET_STACK_PROTECT_RUNTIME_ENABLED_P): New. + +gcc/testsuite/ + + PR target/116962 + * gcc.target/i386/pr116962.c: New file. + +Signed-off-by: H.J. Lu +(cherry picked from commit 7d2845da112214f064e7b24531cc67e256b5177e) +--- + gcc/config/i386/i386.cc | 11 +++++++++++ + gcc/testsuite/gcc.target/i386/pr116962.c | 10 ++++++++++ + 2 files changed, 21 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/i386/pr116962.c + +diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc +index 0b9556f8e..3e7e1b138 100644 +--- a/gcc/config/i386/i386.cc ++++ b/gcc/config/i386/i386.cc +@@ -22606,6 +22606,13 @@ ix86_stack_protect_guard (void) + return default_stack_protect_guard (); + } + ++static bool ++ix86_stack_protect_runtime_enabled_p (void) ++{ ++ /* Naked functions should not enable stack protector. */ ++ return !ix86_function_naked (current_function_decl); ++} ++ + /* For 32-bit code we can save PIC register setup by using + __stack_chk_fail_local hidden function instead of calling + __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC +@@ -24626,6 +24633,10 @@ ix86_libgcc_floating_mode_supported_p + #undef TARGET_STACK_PROTECT_GUARD + #define TARGET_STACK_PROTECT_GUARD ix86_stack_protect_guard + ++#undef TARGET_STACK_PROTECT_RUNTIME_ENABLED_P ++#define TARGET_STACK_PROTECT_RUNTIME_ENABLED_P \ ++ ix86_stack_protect_runtime_enabled_p ++ + #if !TARGET_MACHO + #undef TARGET_STACK_PROTECT_FAIL + #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail +diff --git a/gcc/testsuite/gcc.target/i386/pr116962.c b/gcc/testsuite/gcc.target/i386/pr116962.c +new file mode 100644 +index 000000000..ced16eee7 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/i386/pr116962.c +@@ -0,0 +1,10 @@ ++/* { dg-do compile { target fstack_protector } } */ ++/* { dg-options "-O2 -fstack-protector-all" } */ ++/* { dg-final { scan-assembler-not "__stack_chk_fail" } } */ ++ ++__attribute__ ((naked)) ++void ++foo (void) ++{ ++ asm ("ret"); ++} +-- +2.31.1 + diff --git a/0382-x86-Correct-ASM_OUTPUT_SYMBOL_REF.patch b/0382-x86-Correct-ASM_OUTPUT_SYMBOL_REF.patch new file mode 100644 index 0000000000000000000000000000000000000000..e48656b5342368f96a0751a53138d5cc064758f9 --- /dev/null +++ b/0382-x86-Correct-ASM_OUTPUT_SYMBOL_REF.patch @@ -0,0 +1,36 @@ +From 501d9c6c6af740c4b4327e720bd9957317e9e355 Mon Sep 17 00:00:00 2001 +From: "H.J. Lu" +Date: Tue, 11 Feb 2025 13:47:54 +0800 +Subject: [PATCH 4/4] x86: Correct ASM_OUTPUT_SYMBOL_REF + +x is not a macro argument. It just happens to work as final.cc passes +x for 2nd argument: + +final.cc: ASM_OUTPUT_SYMBOL_REF (file, x); + + PR target/118825 + * config/i386/i386.h (ASM_OUTPUT_SYMBOL_REF): Replace x with + SYM. + +Signed-off-by: H.J. Lu +(cherry picked from commit 7317fc0b03380a83ad03a5fc4fabef5f38c44c9d) +--- + gcc/config/i386/i386.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h +index 5052f878d..a198e36a1 100644 +--- a/gcc/config/i386/i386.h ++++ b/gcc/config/i386/i386.h +@@ -2177,7 +2177,7 @@ extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER]; + #define ASM_OUTPUT_SYMBOL_REF(FILE, SYM) \ + do { \ + const char *name \ +- = assemble_name_resolve (XSTR (x, 0)); \ ++ = assemble_name_resolve (XSTR (SYM, 0)); \ + /* In -masm=att wrap identifiers that start with $ \ + into parens. */ \ + if (ASSEMBLER_DIALECT == ASM_ATT \ +-- +2.31.1 + diff --git a/gcc.spec b/gcc.spec index 8f5090e00905f4b60457c79939acdcc7160e6b4d..ed74bee0449639b9042f1607b7fcb22d273f89f7 100644 --- a/gcc.spec +++ b/gcc.spec @@ -2,7 +2,7 @@ %global gcc_major 12 # Note, gcc_release must be integer, if you want to add suffixes to # %%{release}, append them after %%{gcc_release} on Release: line. -%global gcc_release 83 +%global gcc_release 84 %global _unpackaged_files_terminate_build 0 %global _performance_build 1 @@ -488,6 +488,10 @@ Patch375: 0375-SVE-Fix-gcc-cross-compile-error.patch Patch376: 0376-Struct-dynamic-field-compression-optimization.patch Patch377: 0377-oeAware-Fix-.GCC4OE_oeAware-section-dup-in-namespace.patch Patch378: 0378-Add-alignment-propagation-localize-array-array-dse.patch +Patch379: 0379-x86-64-Don-t-use-temp-for-argument-in-a-TImode-regis.patch +Patch380: 0380-x86-Don-t-use-address-override-with-segment-regsiter.patch +Patch381: 0381-x86-Disable-stack-protector-for-naked-functions.patch +Patch382: 0382-x86-Correct-ASM_OUTPUT_SYMBOL_REF.patch # Part 1001-1999 %ifarch sw_64 @@ -1652,6 +1656,10 @@ not stable, so plugins must be rebuilt any time GCC is updated. %patch -P376 -p1 %patch -P377 -p1 %patch -P378 -p1 +%patch -P379 -p1 +%patch -P380 -p1 +%patch -P381 -p1 +%patch -P382 -p1 %ifarch sw_64 %patch -P1001 -p1 @@ -4279,6 +4287,10 @@ end %doc rpm.doc/changelogs/libcc1/ChangeLog* %changelog +* Fri May 30 2025 Hu,Lin1 - 12.3.1-84 +- Type: Sync +- DESC: Sync patches from openeuler/gcc. + * Tue May 20 2025 huzife <634763349@qq.com> - 12.3.1-83 - Type: Sync - DESC: Sync patches from openeuler/gcc.