From 3fc9028574c392855f54bcd0a38a0a5ae8bee83b Mon Sep 17 00:00:00 2001 From: liyunfei Date: Thu, 12 Jun 2025 09:44:32 +0800 Subject: [PATCH] Modify cores definition for hip cores (cherry picked from commit a54a84d255572fa0f924df468d43787ef23cf14d) --- ...odify-cores-definition-for-hip-cores.patch | 55 +++++++++++++++++++ gcc.spec | 8 ++- 2 files changed, 62 insertions(+), 1 deletion(-) create mode 100644 0392-Modify-cores-definition-for-hip-cores.patch diff --git a/0392-Modify-cores-definition-for-hip-cores.patch b/0392-Modify-cores-definition-for-hip-cores.patch new file mode 100644 index 0000000..a189635 --- /dev/null +++ b/0392-Modify-cores-definition-for-hip-cores.patch @@ -0,0 +1,55 @@ +From 003adcdf4b918a346c5e2826e726430fe9af13a1 Mon Sep 17 00:00:00 2001 +From: liyunfei +Date: Tue, 10 Jun 2025 16:06:41 +0800 +Subject: [PATCH] Modify cores definition for hip cores + +Remove F32MM and F64MM, which is no longer supported after hip09 +Add RNG and SPE support for hip10a and hip12 +--- + gcc/config/aarch64/aarch64-cores.def | 10 +++++----- + gcc/config/aarch64/aarch64-tune.md | 2 +- + 2 files changed, 6 insertions(+), 6 deletions(-) + +diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def +index 2cb752ca1dc..e69e13c0275 100644 +--- a/gcc/config/aarch64/aarch64-cores.def ++++ b/gcc/config/aarch64/aarch64-cores.def +@@ -130,9 +130,9 @@ AARCH64_CORE("a64fx", a64fx, a64fx, V8_2A, (F16, SVE), a64fx, 0x46, 0x001, -1) + + /* HiSilicon ('H') cores. */ + AARCH64_CORE("tsv110", tsv110, tsv110, V8_2A, (CRYPTO, F16), tsv110, 0x48, 0xd01, -1) +-AARCH64_CORE("hip09", hip09, hip09, V8_5A, (SVE, I8MM, F32MM, F64MM, PROFILE, PREDRES), hip09, 0x48, 0xd02, 0x0) +-AARCH64_CORE("hip10a", hip10a, hip10a, V8_5A, (SVE, I8MM, BF16, F32MM, F64MM, SSBS, SHA3, SM4, PREDRES, SVE2, SVE2_BITPERM, DOTPROD, F16FML), hip10a, 0x48, 0xd03, 0x0) +-AARCH64_CORE("hip10c", hip10c, hip10c, V8_5A, (SVE, I8MM, BF16, F32MM, F64MM, FLAGM, PAUTH, SSBS, SHA3, SM4, PROFILE, PREDRES), hip10c, 0x48, 0xd45, 0x0) ++AARCH64_CORE("hip09", hip09, hip09, V8_5A, (SVE, I8MM, F32MM, F64MM, PROFILE, PREDRES, RNG), hip09, 0x48, 0xd02, -1) ++AARCH64_CORE("hip10c", hip10c, hip10c, V8_5A, (SVE, I8MM, BF16, FLAGM, PAUTH, SSBS, SHA3, SM4, PROFILE, PREDRES, RNG), hip10c, 0x48, 0xd45, -1) ++AARCH64_CORE("hip11", hip11, hip11, V8_5A, (SVE, SVE2, F16), hip11, 0x48, 0xd22, -1) + + /* ARMv8.3-A Architecture Processors. */ + +@@ -174,10 +174,10 @@ AARCH64_CORE("cortex-a710", cortexa710, cortexa57, V9A, (SVE2_BITPERM, MEMTAG, + AARCH64_CORE("cortex-x2", cortexx2, cortexa57, V9A, (SVE2_BITPERM, MEMTAG, I8MM, BF16), neoversen2, 0x41, 0xd48, -1) + + AARCH64_CORE("neoverse-n2", neoversen2, cortexa57, V9A, (I8MM, BF16, SVE2_BITPERM, RNG, MEMTAG, PROFILE), neoversen2, 0x41, 0xd49, -1) +-AARCH64_CORE("hip11", hip11, hip11, V8_5A, (SVE, SVE2, F16), hip11, 0x48, 0xd22, -1) + + AARCH64_CORE("demeter", demeter, cortexa57, V9A, (I8MM, BF16, SVE2_BITPERM, RNG, MEMTAG, PROFILE), neoversev2, 0x41, 0xd4f, -1) + AARCH64_CORE("neoverse-v2", neoversev2, cortexa57, V9A, (I8MM, BF16, SVE2_BITPERM, RNG, MEMTAG, PROFILE), neoversev2, 0x41, 0xd4f, -1) + +-AARCH64_CORE("hip12", hip12, hip12, V9_2A, (SVE, SVE2, SVE2_BITPERM, SVE2_AES, SVE2_SM4, SVE2_SHA3, F16, RCPC, BF16, DOTPROD, LSE, SIMD, PAUTH, RDMA, LS64), hip12, 0x48, 0xd06, -1) ++AARCH64_CORE("hip10a", hip10a, hip10a, V9A, (SVE, I8MM, BF16, SSBS, SHA3, SM4, PREDRES, SVE2, SVE2_BITPERM, DOTPROD, F16FML, RNG, PROFILE), hip10a, 0x48, 0xd03, -1) ++AARCH64_CORE("hip12", hip12, hip12, V9_2A, (SVE, SVE2, SVE2_BITPERM, SVE2_AES, SVE2_SM4, SVE2_SHA3, F16, RCPC, BF16, DOTPROD, LSE, SIMD, PAUTH, RDMA, LS64, RNG, PROFILE), hip12, 0x48, 0xd06, -1) + #undef AARCH64_CORE +diff --git a/gcc/config/aarch64/aarch64-tune.md b/gcc/config/aarch64/aarch64-tune.md +index 488e39b7cbb..c40faa2f26e 100644 +--- a/gcc/config/aarch64/aarch64-tune.md ++++ b/gcc/config/aarch64/aarch64-tune.md +@@ -1,5 +1,5 @@ + ;; -*- buffer-read-only: t -*- + ;; Generated automatically by gentune.sh from aarch64-cores.def + (define_attr "tune" +- "cortexa34,cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,octeontx,octeontxt81,octeontxt83,thunderxt81,thunderxt83,ampere1,ampere1a,emag,xgene1,falkor,qdf24xx,exynosm1,phecda,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,cortexa76ae,cortexa77,cortexa78,cortexa78ae,cortexa78c,cortexa65,cortexa65ae,cortexx1,ares,neoversen1,neoversee1,octeontx2,octeontx2t98,octeontx2t96,octeontx2t93,octeontx2f95,octeontx2f95n,octeontx2f95mm,a64fx,tsv110,hip09,hip10a,hip10c,thunderx3t110,zeus,neoversev1,neoverse512tvb,saphira,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55,cortexa76cortexa55,cortexr82,cortexa510,cortexa710,cortexx2,neoversen2,hip11,demeter,neoversev2,hip12" ++ "cortexa34,cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,octeontx,octeontxt81,octeontxt83,thunderxt81,thunderxt83,ampere1,ampere1a,emag,xgene1,falkor,qdf24xx,exynosm1,phecda,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,cortexa76ae,cortexa77,cortexa78,cortexa78ae,cortexa78c,cortexa65,cortexa65ae,cortexx1,ares,neoversen1,neoversee1,octeontx2,octeontx2t98,octeontx2t96,octeontx2t93,octeontx2f95,octeontx2f95n,octeontx2f95mm,a64fx,tsv110,hip09,hip10c,hip11,thunderx3t110,zeus,neoversev1,neoverse512tvb,saphira,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55,cortexa76cortexa55,cortexr82,cortexa510,cortexa710,cortexx2,neoversen2,demeter,neoversev2,hip10a,hip12" + (const (symbol_ref "((enum attr_tune) aarch64_tune)"))) +-- +Gitee diff --git a/gcc.spec b/gcc.spec index b08faf7..bbe844a 100644 --- a/gcc.spec +++ b/gcc.spec @@ -2,7 +2,7 @@ %global gcc_major 12 # Note, gcc_release must be integer, if you want to add suffixes to # %%{release}, append them after %%{gcc_release} on Release: line. -%global gcc_release 92 +%global gcc_release 93 %global _unpackaged_files_terminate_build 0 %global _performance_build 1 @@ -501,6 +501,7 @@ Patch388: 0388-struct-reorg-Escapes-some-void-pointers.patch Patch389: 0389-deja-Correct-pass-number-in-options.patch Patch390: 0390-struct-reorg-Check-ADDR_EXPR-in-pointer-plus-assign.patch Patch391: 0391-oeAware-Fix-.GCC4OE_oeAware-section-dup-in-LTO.patch +Patch392: 0392-Modify-cores-definition-for-hip-cores.patch # Part 1001-1999 %ifarch sw_64 @@ -1678,6 +1679,7 @@ not stable, so plugins must be rebuilt any time GCC is updated. %patch -P389 -p1 %patch -P390 -p1 %patch -P391 -p1 +%patch -P392 -p1 %ifarch sw_64 %patch -P1001 -p1 @@ -4305,6 +4307,10 @@ end %doc rpm.doc/changelogs/libcc1/ChangeLog* %changelog +* Thu Jun 12 2025 liyunfei - 12.3.1-93 +- Type: Sync +- DESC: Modify cores definition for hip cores + * Sat Jun 7 2025 liyancheng <412998149@qq.com> - 12.3.1-92 - Type: Sync - DESC: Sync patches from openeuler/gcc. -- Gitee