From 22bd036374e3716216be33866345c66105021412 Mon Sep 17 00:00:00 2001 From: Xie jiamei Date: Fri, 20 Jun 2025 15:15:38 +0800 Subject: [PATCH] x86: Avoid non_tempoal_threshold calculation to HYGON CPUs Multiplying non_temporal_threshold by thread count can result in an excessively high non_temporal_threshold, causing the non-temporal path to be skipped. This logic was introduced to address issues specific to Intel platforms and is not present in the upstream master branch. To avoid regressions on Hygon CPUs, limit this behavior. Signed-off-by: Xie jiamei (cherry picked from commit d09f76e291dee21e47611d179aa0517f7b87d3c0) --- glibc.spec | 7 +- ...chitecture-type-for-Hygon-processors.patch | 115 ++++++++++++++++++ ...mporal_threshold-calculation-to-Hygo.patch | 32 +++++ 3 files changed, 153 insertions(+), 1 deletion(-) create mode 100644 x86-Add-new-architecture-type-for-Hygon-processors.patch create mode 100644 x86-Avoid-non_temporal_threshold-calculation-to-Hygo.patch diff --git a/glibc.spec b/glibc.spec index ab27942..8e58dff 100644 --- a/glibc.spec +++ b/glibc.spec @@ -71,7 +71,7 @@ ############################################################################## Name: glibc Version: 2.34 -Release: 167 +Release: 168 Summary: The GNU libc libraries License: %{all_license} URL: http://www.gnu.org/software/glibc/ @@ -377,6 +377,8 @@ Patch9051: elf-the-hugepage-feature-of-dynamic-library-keep-com.patch Patch9052: elf-add-some-debug-info-for-dynamic-library-hugepage.patch Patch9053: Use-THP-for-dynamic-shared-library.patch Patch9054: try-to-enable-system-thp-ability-when-LD_HUGEPAGE_LI.patch +Patch9055: x86-Add-new-architecture-type-for-Hygon-processors.patch +Patch9056: x86-Avoid-non_temporal_threshold-calculation-to-Hygo.patch Provides: ldconfig rtld(GNU_HASH) bundled(gnulib) @@ -1552,6 +1554,9 @@ fi %endif %changelog +* Fri June 20 2025 Xie jiamei - 2.34-168 +- x86: Avoid non_temporal_threshold calculation to Hygon CPUs + * Wed May 21 2025 shixuantong - 2.34-167 - Type:CVE - CVE:CVE-2025-4802 diff --git a/x86-Add-new-architecture-type-for-Hygon-processors.patch b/x86-Add-new-architecture-type-for-Hygon-processors.patch new file mode 100644 index 0000000..da9c6c8 --- /dev/null +++ b/x86-Add-new-architecture-type-for-Hygon-processors.patch @@ -0,0 +1,115 @@ +From a9002d89b96085a9102332bfefbd72344526d411 Mon Sep 17 00:00:00 2001 +From: Feifei Wang +Date: Mon, 19 Aug 2024 14:57:53 +0800 +Subject: [PATCH 1/2] x86: Add new architecture type for Hygon processors + +Add a new architecture type arch_kind_hygon to spilt Hygon branch +from AMD. This is to facilitate the Hygon processors to make settings +that are suitable for its own characteristics. + +Signed-off-by: Feifei Wang +Reviewed-by: Jing Li +Reviewed-by: H.J. Lu +--- + sysdeps/x86/cpu-features.c | 19 ++++++++++++++++--- + sysdeps/x86/dl-cacheinfo.h | 4 ++-- + sysdeps/x86/include/cpu-features.h | 1 + + sysdeps/x86/tst-cpu-features-cpuinfo.c | 4 ++-- + 4 files changed, 21 insertions(+), 7 deletions(-) + +diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c +index de4e3c3b72..60066824ee 100644 +--- a/sysdeps/x86/cpu-features.c ++++ b/sysdeps/x86/cpu-features.c +@@ -589,9 +589,8 @@ disable_tsx: + cpu_features->preferred[index_arch_Avoid_Short_Distance_REP_MOVSB] + |= bit_arch_Avoid_Short_Distance_REP_MOVSB; + } +- /* This spells out "AuthenticAMD" or "HygonGenuine". */ +- else if ((ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65) +- || (ebx == 0x6f677948 && ecx == 0x656e6975 && edx == 0x6e65476e)) ++ /* This spells out "AuthenticAMD". */ ++ else if (ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65) + { + unsigned int extended_model; + +@@ -681,6 +680,20 @@ disable_tsx: + } + } + } ++ /* This spells out "HygonGenuine". */ ++ else if (ebx == 0x6f677948 && ecx == 0x656e6975 && edx == 0x6e65476e) ++ { ++ unsigned int extended_model; ++ ++ kind = arch_kind_hygon; ++ ++ get_common_indices (cpu_features, &family, &model, &extended_model, ++ &stepping); ++ ++ get_extended_indices (cpu_features); ++ ++ update_active (cpu_features); ++ } + else + { + kind = arch_kind_other; +diff --git a/sysdeps/x86/dl-cacheinfo.h b/sysdeps/x86/dl-cacheinfo.h +index 1cf8c9310b..da7bb63493 100644 +--- a/sysdeps/x86/dl-cacheinfo.h ++++ b/sysdeps/x86/dl-cacheinfo.h +@@ -769,7 +769,7 @@ dl_init_cacheinfo (struct cpu_features *cpu_features) + + get_common_cache_info (&shared, &threads, core); + } +- else if (cpu_features->basic.kind == arch_kind_amd) ++ else if (cpu_features->basic.kind == arch_kind_amd || cpu_features->basic.kind == arch_kind_hygon) + { + data = handle_amd (_SC_LEVEL1_DCACHE_SIZE); + core = handle_amd (_SC_LEVEL2_CACHE_SIZE); +@@ -901,7 +901,7 @@ dl_init_cacheinfo (struct cpu_features *cpu_features) + performing poorly for data above L2 cache size. Henceforth, adding + an upper bound threshold parameter to limit the usage of Enhanced + REP MOVSB operations and setting its value to L2 cache size. */ +- if (cpu_features->basic.kind == arch_kind_amd) ++ if (cpu_features->basic.kind == arch_kind_amd || cpu_features->basic.kind == arch_kind_hygon) + rep_movsb_stop_threshold = core; + /* Setting the upper bound of ERMS to the computed value of + non-temporal threshold for architectures other than AMD. */ +diff --git a/sysdeps/x86/include/cpu-features.h b/sysdeps/x86/include/cpu-features.h +index 28be3e0c0a..4e3e7cffdf 100644 +--- a/sysdeps/x86/include/cpu-features.h ++++ b/sysdeps/x86/include/cpu-features.h +@@ -824,6 +824,7 @@ enum cpu_features_kind + arch_kind_intel, + arch_kind_amd, + arch_kind_zhaoxin, ++ arch_kind_hygon, + arch_kind_other + }; + +diff --git a/sysdeps/x86/tst-cpu-features-cpuinfo.c b/sysdeps/x86/tst-cpu-features-cpuinfo.c +index 2d4927f5e5..9633da5cb5 100644 +--- a/sysdeps/x86/tst-cpu-features-cpuinfo.c ++++ b/sysdeps/x86/tst-cpu-features-cpuinfo.c +@@ -166,7 +166,7 @@ do_test (int argc, char **argv) + fails += CHECK_PROC (ibrs, IBRS_IBPB); + fails += CHECK_PROC (stibp, STIBP); + } +- else if (cpu_features->basic.kind == arch_kind_amd) ++ else if (cpu_features->basic.kind == arch_kind_amd || cpu_features->basic.kind == arch_kind_hygon) + { + fails += CHECK_PROC (ibpb, AMD_IBPB); + fails += CHECK_PROC (ibrs, AMD_IBRS); +@@ -235,7 +235,7 @@ do_test (int argc, char **argv) + fails += CHECK_PROC (ss, SS); + if (cpu_features->basic.kind == arch_kind_intel) + fails += CHECK_PROC (ssbd, SSBD); +- else if (cpu_features->basic.kind == arch_kind_amd) ++ else if (cpu_features->basic.kind == arch_kind_amd || cpu_features->basic.kind == arch_kind_hygon) + { + /* This feature is implemented in 2 different ways on AMD processors: + newer systems provides AMD_SSBD (function 8000_0008, EBX[24]), +-- +2.17.1 + diff --git a/x86-Avoid-non_temporal_threshold-calculation-to-Hygo.patch b/x86-Avoid-non_temporal_threshold-calculation-to-Hygo.patch new file mode 100644 index 0000000..f92b675 --- /dev/null +++ b/x86-Avoid-non_temporal_threshold-calculation-to-Hygo.patch @@ -0,0 +1,32 @@ +From 56bfb5164291e727e8876f171e55db986d002c92 Mon Sep 17 00:00:00 2001 +From: Xie jiamei +Date: Fri, 20 Jun 2025 15:03:06 +0800 +Subject: [PATCH 2/2] x86: Avoid non_temporal_threshold calculation to Hygon + CPUs + +Multiplying non_temporal_threshold by thread count can result in an excessively +high non_temporal_threshold, causing the non-temporal path to be skipped. +This change reverts that logic for Hygon CPUs, which is not present in the +upstream master. + +Signed-off-by: Xie jiamei +--- + sysdeps/x86/dl-cacheinfo.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/sysdeps/x86/dl-cacheinfo.h b/sysdeps/x86/dl-cacheinfo.h +index da7bb63493..a88c31a10c 100644 +--- a/sysdeps/x86/dl-cacheinfo.h ++++ b/sysdeps/x86/dl-cacheinfo.h +@@ -925,7 +925,7 @@ dl_init_cacheinfo (struct cpu_features *cpu_features) + shared = tunable_size; + + /* keep x86 to use the same non_temporal_threshold like glibc2.28 */ +- if (threads != 0) ++ if (threads != 0 && cpu_features->basic.kind != arch_kind_hygon) + non_temporal_threshold *= threads; + + tunable_size = TUNABLE_GET (x86_non_temporal_threshold, long int, NULL); +-- +2.17.1 + -- Gitee