diff --git a/x86-Add-the-virtual-machine-detection-in-init_cacheinfo.patch b/x86-Add-the-virtual-machine-detection-in-init_cacheinfo.patch new file mode 100644 index 0000000000000000000000000000000000000000..c5054211ec5c8900ee9c6588c60a6d16e0619f1d --- /dev/null +++ b/x86-Add-the-virtual-machine-detection-in-init_cacheinfo.patch @@ -0,0 +1,81 @@ +From 790b67242e7cb24b0c9020f46c27a3ad9487286a Mon Sep 17 00:00:00 2001 +From: May Shao +Date: Fri, 2 Sep 2022 13:47:05 +0800 +Subject: [PATCH] x86: Add the virtual machine detection in init_cacheinfo + +Use CPUID.01H.ECX[31] to indicate guest status and add 3 +macros to cpu-features.h. + +Set the default threads=1 to use non_temporal_threshold on +hosts with a single processor. +--- + sysdeps/x86/cacheinfo.c | 10 ++++++---- + sysdeps/x86/cpu-features.h | 3 +++ + 2 files changed, 9 insertions(+), 4 deletions(-) + +diff --git a/sysdeps/x86/cacheinfo.c b/sysdeps/x86/cacheinfo.c +index 7615334e..278939ba 100644 +--- a/sysdeps/x86/cacheinfo.c ++++ b/sysdeps/x86/cacheinfo.c +@@ -495,7 +495,7 @@ init_cacheinfo (void) + long int data = -1; + long int shared = -1; + unsigned int level; +- unsigned int threads = 0; ++ unsigned int threads = 1; + const struct cpu_features *cpu_features = __get_cpu_features (); + int max_cpuid = cpu_features->max_cpuid; + +@@ -532,7 +532,11 @@ init_cacheinfo (void) + + /* A value of 0 for the HTT bit indicates there is only a single + logical processor. */ +- if (HAS_CPU_FEATURE (HTT)) ++ if (HAS_CPU_FEATURE (VM)) ++ { ++ threads = 1; ++ } ++ else if (HAS_CPU_FEATURE (HTT)) + { + /* Figure out the number of logical threads that share the + highest cache level. */ +@@ -691,8 +695,6 @@ intel_bug_no_cache_info: + if (shared > 0 && threads > 0) + shared /= threads; + } +- else +- threads = 1; + + /* Account for non-inclusive L2 and L3 caches. */ + if (!inclusive_cache) +diff --git a/sysdeps/x86/cpu-features.h b/sysdeps/x86/cpu-features.h +index 347a4b11..75d8c5fb 100644 +--- a/sysdeps/x86/cpu-features.h ++++ b/sysdeps/x86/cpu-features.h +@@ -61,6 +61,7 @@ + #define bit_cpu_LZCNT (1 << 5) + #define bit_cpu_MOVBE (1 << 22) + #define bit_cpu_POPCNT (1 << 23) ++#define bit_cpu_VM (1 << 31) + + /* COMMON_CPUID_INDEX_7. */ + #define bit_cpu_BMI1 (1 << 3) +@@ -187,6 +188,7 @@ extern const struct cpu_features *__get_cpu_features (void) + # define index_cpu_SSE4_1 COMMON_CPUID_INDEX_1 + # define index_cpu_SSE4_2 COMMON_CPUID_INDEX_1 + # define index_cpu_AVX COMMON_CPUID_INDEX_1 ++# define index_cpu_VM COMMON_CPUID_INDEX_1 + # define index_cpu_AVX2 COMMON_CPUID_INDEX_7 + # define index_cpu_AVX512F COMMON_CPUID_INDEX_7 + # define index_cpu_AVX512DQ COMMON_CPUID_INDEX_7 +@@ -219,6 +221,7 @@ extern const struct cpu_features *__get_cpu_features (void) + # define reg_SSE4_1 ecx + # define reg_SSE4_2 ecx + # define reg_AVX ecx ++# define reg_VM ecx + # define reg_AVX2 ebx + # define reg_AVX512F ebx + # define reg_AVX512DQ ebx +-- +2.17.1 +