From d9e752212bb7a05d6012185b94d03e202dfaad5b Mon Sep 17 00:00:00 2001 From: Mingzheng Xing Date: Mon, 3 Nov 2025 10:13:17 +0800 Subject: [PATCH] riscv: upgrade to 6.6.0-115.0.0 - RISC-V kernel upgrade to 6.6.0-115.0.0 - Remove CI-related file changes - riscv: Backport steal-time support for RISC-V - riscv: RISC-V SBI debug console extension support - riscv: Add support for kernel mode vector Signed-off-by: Mingzheng Xing --- 0001-riscv-kernel.patch | 4080 +++++++++++++++++++++++++++++++++++---- kernel.spec | 9 +- 2 files changed, 3670 insertions(+), 419 deletions(-) diff --git a/0001-riscv-kernel.patch b/0001-riscv-kernel.patch index 9ee1fe2..1af6523 100644 --- a/0001-riscv-kernel.patch +++ b/0001-riscv-kernel.patch @@ -1,11 +1,10 @@ -From ada38d466e22fe6ebdb687bd441c6ad3347b03d5 Mon Sep 17 00:00:00 2001 +From c3cef44f1214d884ee99bbd1b9752ef06789eb12 Mon Sep 17 00:00:00 2001 From: Mingzheng Xing -Date: Fri, 17 Oct 2025 10:24:50 +0800 +Date: Wed, 5 Nov 2025 22:20:23 +0800 Subject: [PATCH] riscv kernel Signed-off-by: Mingzheng Xing --- - .github/workflows/main.yml | 20 + Documentation/arch/index.rst | 2 +- Documentation/{ => arch}/riscv/acpi.rst | 0 .../{ => arch}/riscv/boot-image-header.rst | 0 @@ -70,7 +69,7 @@ Signed-off-by: Mingzheng Xing arch/loongarch/include/asm/pgalloc.h | 1 + arch/loongarch/kernel/dma.c | 9 +- arch/mips/include/asm/pgalloc.h | 1 + - arch/riscv/Kconfig | 135 +- + arch/riscv/Kconfig | 176 +- arch/riscv/Kconfig.socs | 59 + arch/riscv/Kconfig.vendor | 19 + arch/riscv/Makefile | 23 +- @@ -109,14 +108,16 @@ Signed-off-by: Mingzheng Xing .../boot/dts/thead/th1520-lpi4a-dsi0.dts | 63 + .../boot/dts/thead/th1520-lpi4a-hx8279.dts | 63 + arch/riscv/boot/dts/thead/th1520.dtsi | 2048 +- - arch/riscv/boot/dts/ultrarisc/Makefile | 2 + + arch/riscv/boot/dts/ultrarisc/Makefile | 4 + .../dts/ultrarisc/dp1000-evb-pinctrl.dtsi | 149 + - .../boot/dts/ultrarisc/dp1000-evb-v1.dts | 53 + - arch/riscv/boot/dts/ultrarisc/dp1000.dts | 533 + - arch/riscv/configs/defconfig | 23 +- + .../boot/dts/ultrarisc/dp1000-evb-v1.dts | 61 + + .../boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi | 146 + + .../riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts | 60 + + arch/riscv/boot/dts/ultrarisc/dp1000.dts | 526 + + arch/riscv/configs/defconfig | 24 +- arch/riscv/configs/dp1000_defconfig | 5530 ++++++ arch/riscv/configs/k1_defconfig | 31 + - arch/riscv/configs/openeuler_defconfig | 1968 +- + arch/riscv/configs/openeuler_defconfig | 1969 +- arch/riscv/configs/sg2042_defconfig | 9 + arch/riscv/configs/th1520_defconfig | 470 + arch/riscv/errata/andes/errata.c | 13 +- @@ -125,6 +126,7 @@ Signed-off-by: Mingzheng Xing arch/riscv/include/asm/acpi.h | 21 +- arch/riscv/include/asm/arch_hweight.h | 78 + arch/riscv/include/asm/archrandom.h | 72 + + arch/riscv/include/asm/asm-prototypes.h | 27 + arch/riscv/include/asm/atomic.h | 17 +- arch/riscv/include/asm/barrier.h | 58 +- arch/riscv/include/asm/bitops.h | 258 +- @@ -135,6 +137,7 @@ Signed-off-by: Mingzheng Xing arch/riscv/include/asm/csr.h | 13 + arch/riscv/include/asm/dmi.h | 24 + arch/riscv/include/asm/elf.h | 2 +- + arch/riscv/include/asm/entry-common.h | 17 + arch/riscv/include/asm/errata_list.h | 45 +- arch/riscv/include/asm/fence.h | 10 +- arch/riscv/include/asm/hwcap.h | 141 +- @@ -144,55 +147,83 @@ Signed-off-by: Mingzheng Xing arch/riscv/include/asm/irq.h | 60 + arch/riscv/include/asm/kvm_aia_aplic.h | 58 - arch/riscv/include/asm/kvm_aia_imsic.h | 38 - + arch/riscv/include/asm/kvm_host.h | 9 + + arch/riscv/include/asm/kvm_vcpu_sbi.h | 25 +- arch/riscv/include/asm/membarrier.h | 19 + arch/riscv/include/asm/mmio.h | 5 +- arch/riscv/include/asm/mmiowb.h | 2 +- + arch/riscv/include/asm/paravirt.h | 28 + + arch/riscv/include/asm/paravirt_api_clock.h | 1 + arch/riscv/include/asm/pgalloc.h | 53 +- arch/riscv/include/asm/pgtable-64.h | 14 +- arch/riscv/include/asm/pgtable.h | 21 +- - arch/riscv/include/asm/processor.h | 6 + - arch/riscv/include/asm/sbi.h | 9 + + arch/riscv/include/asm/processor.h | 47 +- + arch/riscv/include/asm/sbi.h | 42 + + arch/riscv/include/asm/simd.h | 64 + arch/riscv/include/asm/sparsemem.h | 2 +- arch/riscv/include/asm/suspend.h | 5 +- - arch/riscv/include/asm/switch_to.h | 17 +- + arch/riscv/include/asm/switch_to.h | 20 +- arch/riscv/include/asm/sync_core.h | 29 + + arch/riscv/include/asm/thread_info.h | 2 + arch/riscv/include/asm/tlb.h | 18 + arch/riscv/include/asm/vdso/processor.h | 8 +- - arch/riscv/include/asm/vector.h | 12 +- + arch/riscv/include/asm/vector.h | 102 +- arch/riscv/include/asm/vendor_extensions.h | 103 + .../include/asm/vendor_extensions/andes.h | 19 + arch/riscv/include/asm/vendorid_list.h | 2 +- + arch/riscv/include/asm/xor.h | 68 + arch/riscv/include/uapi/asm/hwprobe.h | 52 +- - arch/riscv/kernel/Makefile | 4 + + arch/riscv/include/uapi/asm/kvm.h | 14 + + arch/riscv/kernel/Makefile | 6 + arch/riscv/kernel/acpi.c | 135 +- arch/riscv/kernel/acpi_numa.c | 130 + arch/riscv/kernel/alternative.c | 2 +- arch/riscv/kernel/cpufeature.c | 579 +- + arch/riscv/kernel/entry.S | 24 +- + arch/riscv/kernel/head.S | 18 +- + arch/riscv/kernel/kernel_mode_vector.c | 247 + + arch/riscv/kernel/mcount.S | 10 +- arch/riscv/kernel/module.c | 83 +- - arch/riscv/kernel/process.c | 3 + + arch/riscv/kernel/paravirt.c | 135 + + arch/riscv/kernel/process.c | 16 +- + arch/riscv/kernel/ptrace.c | 7 +- arch/riscv/kernel/sbi-ipi.c | 46 +- + arch/riscv/kernel/sbi.c | 66 + arch/riscv/kernel/setup.c | 8 +- + arch/riscv/kernel/signal.c | 20 +- arch/riscv/kernel/smp.c | 17 + arch/riscv/kernel/smpboot.c | 4 +- arch/riscv/kernel/suspend.c | 100 +- arch/riscv/kernel/sys_hwprobe.c | 349 + arch/riscv/kernel/sys_riscv.c | 267 - + arch/riscv/kernel/time.c | 3 + arch/riscv/kernel/vdso/hwprobe.c | 86 +- - arch/riscv/kernel/vector.c | 8 +- + arch/riscv/kernel/vector.c | 61 +- arch/riscv/kernel/vendor_extensions.c | 56 + arch/riscv/kernel/vendor_extensions/Makefile | 3 + arch/riscv/kernel/vendor_extensions/andes.c | 18 + + arch/riscv/kvm/Kconfig | 1 + + arch/riscv/kvm/Makefile | 1 + arch/riscv/kvm/aia.c | 37 +- arch/riscv/kvm/aia_aplic.c | 2 +- arch/riscv/kvm/aia_device.c | 2 +- arch/riscv/kvm/aia_imsic.c | 2 +- arch/riscv/kvm/main.c | 2 +- arch/riscv/kvm/tlb.c | 2 +- + arch/riscv/kvm/vcpu.c | 13 + arch/riscv/kvm/vcpu_fp.c | 2 +- - arch/riscv/kvm/vcpu_onereg.c | 2 +- + arch/riscv/kvm/vcpu_onereg.c | 98 +- + arch/riscv/kvm/vcpu_sbi.c | 189 +- + arch/riscv/kvm/vcpu_sbi_replace.c | 32 + + arch/riscv/kvm/vcpu_sbi_sta.c | 208 + arch/riscv/kvm/vcpu_vector.c | 2 +- - arch/riscv/lib/Makefile | 1 + + arch/riscv/lib/Makefile | 8 +- arch/riscv/lib/crc32.c | 294 + + arch/riscv/lib/memmove.S | 54 +- + arch/riscv/lib/riscv_v_helpers.c | 45 + + arch/riscv/lib/uaccess.S | 10 + + arch/riscv/lib/uaccess_vector.S | 53 + + arch/riscv/lib/xor.S | 81 + arch/riscv/mm/cacheflush.c | 25 +- arch/riscv/mm/dma-noncoherent.c | 9 +- arch/riscv/mm/pgtable.c | 2 + @@ -1171,11 +1202,12 @@ Signed-off-by: Mingzheng Xing .../controller/cadence/pcie-cadence-sophgo.h | 6 + drivers/pci/controller/dwc/Kconfig | 26 + drivers/pci/controller/dwc/Makefile | 2 + - .../pci/controller/dwc/pcie-designware-host.c | 86 + + .../pci/controller/dwc/pcie-designware-host.c | 81 + + drivers/pci/controller/dwc/pcie-designware.c | 4 + drivers/pci/controller/dwc/pcie-designware.h | 39 + drivers/pci/controller/dwc/pcie-dw-sophgo.c | 1687 ++ drivers/pci/controller/dwc/pcie-dw-sophgo.h | 251 + - drivers/pci/controller/dwc/pcie-ultrarisc.c | 139 + + drivers/pci/controller/dwc/pcie-ultrarisc.c | 156 + drivers/pci/msi/msi.c | 61 +- drivers/pci/pci-acpi.c | 248 +- drivers/pci/pci.h | 4 +- @@ -1446,13 +1478,16 @@ Signed-off-by: Mingzheng Xing drivers/tee/optee/Kconfig | 2 +- drivers/tee/optee/call.c | 2 + drivers/tee/optee/smc_abi.c | 37 + + drivers/tty/hvc/Kconfig | 2 +- + drivers/tty/hvc/hvc_riscv_sbi.c | 37 +- drivers/tty/serial/8250/8250_dma.c | 134 +- drivers/tty/serial/8250/8250_dw.c | 167 +- drivers/tty/serial/8250/8250_dwlib.c | 3 +- drivers/tty/serial/8250/8250_dwlib.h | 33 +- drivers/tty/serial/8250/8250_port.c | 12 +- - drivers/tty/serial/Kconfig | 19 +- + drivers/tty/serial/Kconfig | 21 +- drivers/tty/serial/Makefile | 1 + + drivers/tty/serial/earlycon-riscv-sbi.c | 27 +- drivers/tty/serial/serial_port.c | 145 + drivers/tty/serial/spacemit_k1x_uart.c | 1979 ++ drivers/ufs/host/ufs-qcom.c | 9 +- @@ -1573,13 +1608,15 @@ Signed-off-by: Mingzheng Xing tools/testing/selftests/hid/Makefile | 10 +- tools/testing/selftests/hid/progs/hid.c | 3 - .../selftests/hid/progs/hid_bpf_helpers.h | 77 + + .../selftests/kvm/include/riscv/processor.h | 40 +- + .../selftests/kvm/lib/riscv/processor.c | 4 +- + .../selftests/kvm/riscv/get-reg-list.c | 4 +- .../testing/selftests/riscv/hwprobe/Makefile | 9 +- tools/testing/selftests/riscv/hwprobe/cbo.c | 228 + .../testing/selftests/riscv/hwprobe/hwprobe.c | 64 +- .../testing/selftests/riscv/hwprobe/hwprobe.h | 15 + .../selftests/riscv/vector/vstate_prctl.c | 10 +- - 1573 files changed, 606683 insertions(+), 2584 deletions(-) - create mode 100644 .github/workflows/main.yml + 1611 files changed, 608647 insertions(+), 2794 deletions(-) rename Documentation/{ => arch}/riscv/acpi.rst (100%) rename Documentation/{ => arch}/riscv/boot-image-header.rst (100%) rename Documentation/{ => arch}/riscv/boot.rst (100%) @@ -1653,6 +1690,8 @@ Signed-off-by: Mingzheng Xing create mode 100644 arch/riscv/boot/dts/ultrarisc/Makefile create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts + create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi + create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000.dts create mode 100644 arch/riscv/configs/dp1000_defconfig create mode 100644 arch/riscv/configs/k1_defconfig @@ -1664,15 +1703,25 @@ Signed-off-by: Mingzheng Xing create mode 100644 arch/riscv/include/asm/dmi.h delete mode 100644 arch/riscv/include/asm/kvm_aia_aplic.h delete mode 100644 arch/riscv/include/asm/kvm_aia_imsic.h + create mode 100644 arch/riscv/include/asm/paravirt.h + create mode 100644 arch/riscv/include/asm/paravirt_api_clock.h + create mode 100644 arch/riscv/include/asm/simd.h create mode 100644 arch/riscv/include/asm/sync_core.h create mode 100644 arch/riscv/include/asm/vendor_extensions.h create mode 100644 arch/riscv/include/asm/vendor_extensions/andes.h + create mode 100644 arch/riscv/include/asm/xor.h create mode 100644 arch/riscv/kernel/acpi_numa.c + create mode 100644 arch/riscv/kernel/kernel_mode_vector.c + create mode 100644 arch/riscv/kernel/paravirt.c create mode 100644 arch/riscv/kernel/sys_hwprobe.c create mode 100644 arch/riscv/kernel/vendor_extensions.c create mode 100644 arch/riscv/kernel/vendor_extensions/Makefile create mode 100644 arch/riscv/kernel/vendor_extensions/andes.c + create mode 100644 arch/riscv/kvm/vcpu_sbi_sta.c create mode 100644 arch/riscv/lib/crc32.c + create mode 100644 arch/riscv/lib/riscv_v_helpers.c + create mode 100644 arch/riscv/lib/uaccess_vector.S + create mode 100644 arch/riscv/lib/xor.S create mode 100644 drivers/acpi/mipi-disco-img.c create mode 100644 drivers/acpi/riscv/cppc.c create mode 100644 drivers/acpi/riscv/cpuidle.c @@ -2811,32 +2860,6 @@ Signed-off-by: Mingzheng Xing create mode 100644 tools/testing/selftests/riscv/hwprobe/cbo.c create mode 100644 tools/testing/selftests/riscv/hwprobe/hwprobe.h -diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml -new file mode 100644 -index 000000000000..c0755aecee33 ---- /dev/null -+++ b/.github/workflows/main.yml -@@ -0,0 +1,20 @@ -+name: rvck ci -+ -+on: -+ pull_request_target: -+ types: [opened,reopened,synchronize] -+ issues: -+ types: [opened,reopened] -+ issue_comment: -+ types: [created] -+ -+jobs: -+ rvck-ci: -+ permissions: -+ issues: write -+ pull-requests: write -+ uses: OERV-RVCI/RVCK-RAVA/.github/workflows/rvck-actions.yml@main -+ secrets: -+ LAVA_TOKEN: ${{ secrets.LAVA_TOKEN }} -+ RSYNC_PASSPHRASE: ${{ secrets.RSYNC_PASSPHRASE }} -+ diff --git a/Documentation/arch/index.rst b/Documentation/arch/index.rst index 84b80255b851..f4794117e56b 100644 --- a/Documentation/arch/index.rst @@ -5780,10 +5803,10 @@ index 33eeabab5088..c34609dd468e 100644 RNBD BLOCK DRIVERS M: Md. Haris Iqbal diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig -index 5fb0190e8e9a..4c7454c05fe1 100644 +index 95974b69e202..9193cd32a807 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig -@@ -1619,7 +1619,6 @@ config ARM64_BOOTPARAM_HOTPLUG_CPU0 +@@ -1632,7 +1632,6 @@ config ARM64_BOOTPARAM_HOTPLUG_CPU0 config NUMA bool "NUMA Memory Allocation and Scheduler Support" select GENERIC_ARCH_NUMA @@ -6090,7 +6113,7 @@ index 40e40a7eb94a..f4440edcd8fe 100644 pud_init(pud); diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig -index 3be10e723b2c..b20dc27077c2 100644 +index 3be10e723b2c..a5be297fc1b6 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -13,7 +13,10 @@ config 32BIT @@ -6212,7 +6235,7 @@ index 3be10e723b2c..b20dc27077c2 100644 help Say N here if you want to disable all vector related procedure in the kernel. -@@ -525,6 +554,53 @@ config RISCV_ISA_V_DEFAULT_ENABLE +@@ -525,6 +554,75 @@ config RISCV_ISA_V_DEFAULT_ENABLE If you don't know what to do here, say Y. @@ -6262,11 +6285,33 @@ index 3be10e723b2c..b20dc27077c2 100644 + cmpxchg operations when it is detected at boot. + + If you don't know what to do here, say Y. ++ ++config RISCV_ISA_V_UCOPY_THRESHOLD ++ int "Threshold size for vectorized user copies" ++ depends on RISCV_ISA_V ++ default 768 ++ help ++ Prefer using vectorized copy_to_user()/copy_from_user() when the ++ workload size exceeds this value. ++ ++config RISCV_ISA_V_PREEMPTIVE ++ bool "Run kernel-mode Vector with kernel preemption" ++ depends on PREEMPTION ++ depends on RISCV_ISA_V ++ default y ++ help ++ Usually, in-kernel SIMD routines are run with preemption disabled. ++ Functions which envoke long running SIMD thus must yield core's ++ vector unit to prevent blocking other tasks for too long. ++ ++ This config allows kernel to run SIMD without explicitly disable ++ preemption. Enabling this config will result in higher memory ++ consumption due to the allocation of per-task's kernel Vector context. + config TOOLCHAIN_HAS_ZBB bool default y -@@ -549,6 +625,29 @@ config RISCV_ISA_ZBB +@@ -549,6 +647,29 @@ config RISCV_ISA_ZBB If you don't know what to do here, say Y. @@ -6296,7 +6341,7 @@ index 3be10e723b2c..b20dc27077c2 100644 config RISCV_ISA_ZICBOM bool "Zicbom extension support for non-coherent DMA operation" depends on MMU -@@ -579,13 +678,6 @@ config RISCV_ISA_ZICBOZ +@@ -579,13 +700,6 @@ config RISCV_ISA_ZICBOZ If you don't know what to do here, say Y. @@ -6310,7 +6355,7 @@ index 3be10e723b2c..b20dc27077c2 100644 config TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI def_bool y # https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=aed44286efa8ae8717a77d94b51ac3614e2ca6dc -@@ -697,6 +789,20 @@ config ARCH_SUPPORTS_KEXEC_PURGATORY +@@ -697,6 +811,20 @@ config ARCH_SUPPORTS_KEXEC_PURGATORY config ARCH_SUPPORTS_CRASH_DUMP def_bool y @@ -6331,7 +6376,33 @@ index 3be10e723b2c..b20dc27077c2 100644 config COMPAT bool "Kernel support for 32-bit U-mode" default 64BIT -@@ -811,6 +917,17 @@ config EFI +@@ -709,6 +837,25 @@ config COMPAT + + If you want to execute 32-bit userspace applications, say Y. + ++config PARAVIRT ++ bool "Enable paravirtualization code" ++ depends on RISCV_SBI ++ help ++ This changes the kernel so it can modify itself when it is run ++ under a hypervisor, potentially improving performance significantly ++ over full virtualization. ++ ++config PARAVIRT_TIME_ACCOUNTING ++ bool "Paravirtual steal time accounting" ++ depends on PARAVIRT ++ help ++ Select this option to enable fine granularity task steal time ++ accounting. Time spent executing other tasks in parallel with ++ the current vCPU is discounted from the vCPU power. To account for ++ that, there can be a small performance impact. ++ ++ If in doubt, say N here. ++ + config RELOCATABLE + bool "Build a relocatable kernel" + depends on MMU && 64BIT && !XIP_KERNEL +@@ -811,6 +958,17 @@ config EFI allow the kernel to be booted as an EFI application. This is only useful on systems that have UEFI firmware. @@ -22066,15 +22137,17 @@ index ff364709a6df..a47bf9f15d9a 100644 }; diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile new file mode 100644 -index 000000000000..ef70e28e0b65 +index 000000000000..9eac56549340 --- /dev/null +++ b/arch/riscv/boot/dts/ultrarisc/Makefile -@@ -0,0 +1,2 @@ +@@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 -+dtb-y += dp1000.dtb dp1000-evb-v1.dtb ++dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000.dtb ++dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-evb-v1.dtb ++dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-mo-v1.dtb diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi new file mode 100644 -index 000000000000..b443b3fd48a8 +index 000000000000..1d6442c2bff7 --- /dev/null +++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi @@ -0,0 +1,149 @@ @@ -22151,8 +22224,8 @@ index 000000000000..b443b3fd48a8 + + uart0_pins: uart0_pins { + pinctrl-pins = < -+ UR_DP1000_IOMUX_A 8 UR_FUNC0 -+ UR_DP1000_IOMUX_A 9 UR_FUNC0 ++ UR_DP1000_IOMUX_A 8 UR_FUNC1 ++ UR_DP1000_IOMUX_A 9 UR_FUNC1 + >; + + pinconf-pins = < @@ -22229,10 +22302,10 @@ index 000000000000..b443b3fd48a8 +}; diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts new file mode 100644 -index 000000000000..c2ca8ae53dda +index 000000000000..4080b26957ff --- /dev/null +++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts -@@ -0,0 +1,53 @@ +@@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * UltraRISC DP1000 device Tree Source @@ -22263,6 +22336,232 @@ index 000000000000..c2ca8ae53dda +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; ++ ++ mmc0: mmc@0 { ++ compatible = "mmc-spi-slot"; ++ spi-max-frequency = <15625000>; ++ reg = <0x00>; ++ voltage-ranges = <3300 3300>; ++ disable-wp; ++ }; ++}; ++ ++&spi1 { ++ num-cs = <1>; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi1_pins>; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pins>; ++}; ++ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>; ++}; ++ ++&uart2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart2_pins>; ++}; +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi +new file mode 100644 +index 000000000000..6af61ea8a6da +--- /dev/null ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi +@@ -0,0 +1,146 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. ++ */ ++ ++#include ++ ++/ { ++ ++ soc { ++ pmx0: pinmux@11081000 { ++ compatible = "ultrarisc,dp1000-pinctrl"; ++ reg = <0x0 0x11081000 0x0 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ #pinctrl-cells = <2>; ++ pinctrl-single,register-width = <32>; ++ pinctrl-single,function-mask = <0x3ff>; ++ pinctrl-use-default; ++ ++ i2c0_pins: i2c0_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_A 12 UR_FUNC0 ++ UR_DP1000_IOMUX_A 13 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_A 12 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 13 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ i2c1_pins: i2c1_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_B 6 UR_FUNC0 ++ UR_DP1000_IOMUX_B 7 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_B 6 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_B 7 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ i2c2_pins: i2c2_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_C 0 UR_FUNC0 ++ UR_DP1000_IOMUX_C 1 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_C 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_C 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ i2c3_pins: i2c3_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_C 2 UR_FUNC0 ++ UR_DP1000_IOMUX_C 3 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_C 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_C 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ uart0_pins: uart0_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_A 8 UR_FUNC1 ++ UR_DP1000_IOMUX_A 9 UR_FUNC1 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_A 8 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 9 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ uart1_pins: uart1_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_B 4 UR_FUNC0 ++ UR_DP1000_IOMUX_B 5 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_B 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_B 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ uart2_pins: uart2_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_C 4 UR_FUNC0 ++ UR_DP1000_IOMUX_C 5 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_C 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_C 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ spi0_pins: spi0_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_D 0 UR_FUNC1 ++ UR_DP1000_IOMUX_D 1 UR_FUNC1 ++ UR_DP1000_IOMUX_D 2 UR_FUNC1 ++ UR_DP1000_IOMUX_D 3 UR_FUNC1 ++ UR_DP1000_IOMUX_D 4 UR_FUNC1 ++ UR_DP1000_IOMUX_D 5 UR_FUNC1 ++ UR_DP1000_IOMUX_D 6 UR_FUNC1 ++ UR_DP1000_IOMUX_D 7 UR_FUNC1 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_D 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 6 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 7 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ spi1_pins: spi1_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_A 0 UR_FUNC0 ++ UR_DP1000_IOMUX_A 1 UR_FUNC0 ++ UR_DP1000_IOMUX_A 2 UR_FUNC0 ++ UR_DP1000_IOMUX_A 3 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_A 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts +new file mode 100644 +index 000000000000..a74714629566 +--- /dev/null ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts +@@ -0,0 +1,60 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. ++ */ ++ ++#include "dp1000.dts" ++#include "dp1000-mo-pinctrl.dtsi" ++#include ++ ++&i2c0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0_pins>; ++}; ++ ++&i2c1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins>; ++}; ++ ++&i2c2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c2_pins>; ++ ++ rtc@32 { ++ compatible = "whwave,sd3078"; ++ reg = <0x32>; ++ }; ++}; ++ ++&i2c3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c3_pins>; ++}; ++ ++&spi0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi0_pins>; +}; + +&spi1 { @@ -22288,10 +22587,10 @@ index 000000000000..c2ca8ae53dda +}; diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dts b/arch/riscv/boot/dts/ultrarisc/dp1000.dts new file mode 100644 -index 000000000000..7e753f891d7b +index 000000000000..bce0a46c5425 --- /dev/null +++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dts -@@ -0,0 +1,533 @@ +@@ -0,0 +1,526 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2019-2022 UltraRISC Technology (Shanghai) Co., Ltd. @@ -22552,13 +22851,6 @@ index 000000000000..7e753f891d7b + clock-names = "device_clk"; + num-cs = <3>; + spi-max-frequency = <62500000>; -+ mmc0: mmc@0 { -+ compatible = "mmc-spi-slot"; -+ spi-max-frequency = <15625000>; -+ reg = <0x00>; -+ voltage-ranges = <3300 3300>; -+ disable-wp; -+ }; + }; + + spi1: spi@20420000 { @@ -22826,7 +23118,7 @@ index 000000000000..7e753f891d7b + }; +}; diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig -index ab86ec3b9eab..33159406ee58 100644 +index ab86ec3b9eab..8f88aed3d5d8 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -28,6 +28,7 @@ CONFIG_PROFILING=y @@ -22845,7 +23137,15 @@ index ab86ec3b9eab..33159406ee58 100644 CONFIG_VIRTUALIZATION=y CONFIG_KVM=m CONFIG_ACPI=y -@@ -142,6 +144,13 @@ CONFIG_SPI_SUN6I=y +@@ -133,6 +135,7 @@ CONFIG_SERIAL_8250_DW=y + CONFIG_SERIAL_OF_PLATFORM=y + CONFIG_SERIAL_SH_SCI=y + CONFIG_VIRTIO_CONSOLE=y ++CONFIG_SERIAL_EARLYCON_RISCV_SBI=y + CONFIG_HW_RANDOM=y + CONFIG_HW_RANDOM_VIRTIO=y + CONFIG_I2C_MV64XXX=m +@@ -142,6 +145,13 @@ CONFIG_SPI_SUN6I=y # CONFIG_PTP_1588_CLOCK is not set CONFIG_GPIO_SIFIVE=y CONFIG_WATCHDOG=y @@ -22859,7 +23159,7 @@ index ab86ec3b9eab..33159406ee58 100644 CONFIG_SUNXI_WATCHDOG=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y -@@ -168,21 +177,25 @@ CONFIG_MMC=y +@@ -168,21 +178,25 @@ CONFIG_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SDHCI_CADENCE=y @@ -22885,7 +23185,7 @@ index ab86ec3b9eab..33159406ee58 100644 CONFIG_ARCH_R9A07G043=y CONFIG_PHY_SUN4I_USB=m CONFIG_LIBNVDIMM=y -@@ -238,5 +251,13 @@ CONFIG_DEBUG_SG=y +@@ -238,5 +252,13 @@ CONFIG_DEBUG_SG=y # CONFIG_RCU_TRACE is not set CONFIG_RCU_EQS_DEBUG=y # CONFIG_FTRACE is not set @@ -28474,7 +28774,7 @@ index 000000000000..72df9883c25c +CONFIG_K1_EMAC=m + diff --git a/arch/riscv/configs/openeuler_defconfig b/arch/riscv/configs/openeuler_defconfig -index 61f2b2f12589..a09cebedc1c8 100644 +index 61f2b2f12589..4ef5c9933ef9 100644 --- a/arch/riscv/configs/openeuler_defconfig +++ b/arch/riscv/configs/openeuler_defconfig @@ -2,6 +2,7 @@ @@ -28575,7 +28875,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_PGTABLE_LEVELS=5 CONFIG_LOCKDEP_SUPPORT=y CONFIG_RISCV_DMA_NONCOHERENT=y -@@ -306,15 +313,20 @@ CONFIG_RISCV_DMA_NONCOHERENT=y +@@ -306,15 +313,21 @@ CONFIG_RISCV_DMA_NONCOHERENT=y # SoC selection # # CONFIG_SOC_MICROCHIP_POLARFIRE is not set @@ -28590,6 +28890,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 +CONFIG_ARCH_SUNXI=y CONFIG_ARCH_THEAD=y +CONFIG_ARCH_XUANTIE=y ++# CONFIG_ARCH_ULTRARISC is not set CONFIG_ARCH_VIRT=y CONFIG_SOC_VIRT=y +CONFIG_SOC_SPACEMIT=y @@ -28598,7 +28899,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # end of SoC selection # -@@ -330,6 +342,18 @@ CONFIG_ERRATA_THEAD_CMO=y +@@ -330,6 +343,18 @@ CONFIG_ERRATA_THEAD_CMO=y CONFIG_ERRATA_THEAD_PMU=y # end of CPU errata selection @@ -28617,7 +28918,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # # Platform type # -@@ -339,7 +363,7 @@ CONFIG_ARCH_RV64I=y +@@ -339,7 +364,7 @@ CONFIG_ARCH_RV64I=y CONFIG_CMODEL_MEDANY=y CONFIG_MODULE_SECTIONS=y CONFIG_SMP=y @@ -28626,25 +28927,28 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_NR_CPUS=512 CONFIG_HOTPLUG_CPU=y CONFIG_TUNE_GENERIC=y -@@ -351,11 +375,14 @@ CONFIG_RISCV_ISA_C=y - CONFIG_RISCV_ISA_SVNAPOT=y - CONFIG_RISCV_ISA_SVPBMT=y +@@ -353,9 +378,10 @@ CONFIG_RISCV_ISA_SVPBMT=y CONFIG_TOOLCHAIN_HAS_V=y --CONFIG_RISCV_ISA_V=y --CONFIG_RISCV_ISA_V_DEFAULT_ENABLE=y -+# CONFIG_RISCV_ISA_V is not set + CONFIG_RISCV_ISA_V=y + CONFIG_RISCV_ISA_V_DEFAULT_ENABLE=y +CONFIG_RISCV_ISA_ZAWRS=y -+CONFIG_TOOLCHAIN_HAS_ZBB=y -+CONFIG_RISCV_ISA_ZBB=y -+CONFIG_TOOLCHAIN_HAS_ZBC=y -+CONFIG_RISCV_ISA_ZBC=y ++CONFIG_RISCV_ISA_V_UCOPY_THRESHOLD=768 CONFIG_RISCV_ISA_ZICBOM=y CONFIG_RISCV_ISA_ZICBOZ=y -CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE=y CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI=y CONFIG_FPU=y CONFIG_IRQ_STACKS=y -@@ -390,6 +417,7 @@ CONFIG_COMPAT=y +@@ -380,6 +406,8 @@ CONFIG_ARCH_SELECTS_KEXEC_FILE=y + CONFIG_ARCH_SUPPORTS_KEXEC_PURGATORY=y + CONFIG_ARCH_SUPPORTS_CRASH_DUMP=y + CONFIG_COMPAT=y ++CONFIG_PARAVIRT=y ++CONFIG_PARAVIRT_TIME_ACCOUNTING=y + # CONFIG_RELOCATABLE is not set + # CONFIG_RANDOMIZE_BASE is not set + # end of Kernel features +@@ -390,6 +418,7 @@ CONFIG_COMPAT=y CONFIG_CMDLINE="" CONFIG_EFI_STUB=y CONFIG_EFI=y @@ -28652,7 +28956,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y CONFIG_STACKPROTECTOR_PER_TASK=y CONFIG_RISCV_ISA_FALLBACK=y -@@ -420,7 +448,7 @@ CONFIG_PM_GENERIC_DOMAINS=y +@@ -420,7 +449,7 @@ CONFIG_PM_GENERIC_DOMAINS=y CONFIG_PM_GENERIC_DOMAINS_SLEEP=y CONFIG_PM_GENERIC_DOMAINS_OF=y CONFIG_CPU_PM=y @@ -28661,7 +28965,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_ARCH_SUSPEND_POSSIBLE=y # end of Power management options -@@ -436,6 +464,7 @@ CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y +@@ -436,6 +465,7 @@ CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y # CONFIG_CPU_IDLE_GOV_LADDER is not set CONFIG_CPU_IDLE_GOV_MENU=y CONFIG_CPU_IDLE_GOV_TEO=y @@ -28669,7 +28973,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_DT_IDLE_STATES=y CONFIG_DT_IDLE_GENPD=y -@@ -471,6 +500,8 @@ CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y +@@ -471,6 +501,8 @@ CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y # CONFIG_CPUFREQ_DT=y CONFIG_CPUFREQ_DT_PLATDEV=y @@ -28678,7 +28982,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # end of CPU Frequency scaling # end of CPU Power Management -@@ -485,9 +516,52 @@ CONFIG_HAVE_KVM_VCPU_ASYNC_IOCTL=y +@@ -485,9 +517,53 @@ CONFIG_HAVE_KVM_VCPU_ASYNC_IOCTL=y CONFIG_KVM_XFER_TO_GUEST_WORK=y CONFIG_KVM_GENERIC_HARDWARE_ENABLING=y CONFIG_VIRTUALIZATION=y @@ -28727,13 +29031,14 @@ index 61f2b2f12589..a09cebedc1c8 100644 +CONFIG_LIVEPATCH_STOP_MACHINE_CONSISTENCY=y +CONFIG_LIVEPATCH_STACK=y +CONFIG_LIVEPATCH_RESTRICT_KPROBE=y ++CONFIG_LIVEPATCH_LONG_SYMBOL_SUPPORT=y +# end of Enable Livepatch + +CONFIG_CPU_MITIGATIONS=y # # General architecture-dependent options -@@ -524,6 +598,8 @@ CONFIG_HAVE_PERF_REGS=y +@@ -524,6 +600,8 @@ CONFIG_HAVE_PERF_REGS=y CONFIG_HAVE_PERF_USER_STACK_DUMP=y CONFIG_HAVE_ARCH_JUMP_LABEL=y CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y @@ -28742,7 +29047,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_MMU_LAZY_TLB_REFCOUNT=y CONFIG_HAVE_ARCH_SECCOMP=y CONFIG_HAVE_ARCH_SECCOMP_FILTER=y -@@ -565,7 +641,7 @@ CONFIG_VMAP_STACK=y +@@ -565,7 +643,7 @@ CONFIG_VMAP_STACK=y CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y @@ -28751,15 +29056,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y CONFIG_STRICT_MODULE_RWX=y CONFIG_ARCH_USE_MEMREMAP_PROT=y -@@ -576,7 +652,6 @@ CONFIG_HAVE_PREEMPT_DYNAMIC_KEY=y - CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y - CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y - CONFIG_ARCH_SUPPORTS_PAGE_TABLE_CHECK=y --CONFIG_DYNAMIC_SIGFRAME=y - - # - # GCOV-based kernel profiling -@@ -585,6 +660,11 @@ CONFIG_DYNAMIC_SIGFRAME=y +@@ -585,6 +663,11 @@ CONFIG_DYNAMIC_SIGFRAME=y CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y # end of GCOV-based kernel profiling @@ -28771,7 +29068,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_HAVE_GCC_PLUGINS=y CONFIG_FUNCTION_ALIGNMENT=0 # end of General architecture-dependent options -@@ -646,6 +726,7 @@ CONFIG_BLK_INLINE_ENCRYPTION=y +@@ -646,6 +729,7 @@ CONFIG_BLK_INLINE_ENCRYPTION=y CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK=y # CONFIG_BLK_DEV_DETECT_WRITING_PART0 is not set # CONFIG_BLK_DEV_WRITE_MOUNTED_DUMP is not set @@ -28779,7 +29076,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_BLK_IO_HIERARCHY_STATS is not set # -@@ -706,6 +787,8 @@ CONFIG_QUEUED_RWLOCKS=y +@@ -706,6 +790,8 @@ CONFIG_QUEUED_RWLOCKS=y CONFIG_ARCH_HAS_MMIOWB=y CONFIG_MMIOWB=y CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y @@ -28788,7 +29085,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y # CONFIG_PID_MAX_PER_NAMESPACE is not set CONFIG_FREEZER=y -@@ -771,6 +854,8 @@ CONFIG_SPARSEMEM_EXTREME=y +@@ -771,6 +857,8 @@ CONFIG_SPARSEMEM_EXTREME=y CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y CONFIG_SPARSEMEM_VMEMMAP=y CONFIG_ARCH_WANT_OPTIMIZE_HUGETLB_VMEMMAP=y @@ -28797,7 +29094,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_MEMORY_ISOLATION=y CONFIG_EXCLUSIVE_SYSTEM_RAM=y CONFIG_SPLIT_PTLOCK_CPUS=4 -@@ -795,13 +880,14 @@ CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y +@@ -795,13 +883,14 @@ CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y # CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set CONFIG_THP_SWAP=y # CONFIG_READ_ONLY_THP_FOR_FS is not set @@ -28815,7 +29112,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_GENERIC_EARLY_IOREMAP=y # CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set CONFIG_PAGE_IDLE_FLAG=y -@@ -833,6 +919,8 @@ CONFIG_LOCK_MM_AND_FIND_VMA=y +@@ -833,6 +922,8 @@ CONFIG_LOCK_MM_AND_FIND_VMA=y # # CONFIG_DAMON is not set # end of Data Access Monitoring @@ -28824,7 +29121,15 @@ index 61f2b2f12589..a09cebedc1c8 100644 # end of Memory Management options CONFIG_NET=y -@@ -1346,10 +1434,10 @@ CONFIG_L2TP_DEBUGFS=m +@@ -870,6 +961,7 @@ CONFIG_NET_KEY=m + CONFIG_NET_KEY_MIGRATE=y + # CONFIG_SMC is not set + # CONFIG_XDP_SOCKETS is not set ++# CONFIG_OENETCLS is not set + CONFIG_NET_HANDSHAKE=y + CONFIG_INET=y + CONFIG_IP_MULTICAST=y +@@ -1346,10 +1438,10 @@ CONFIG_L2TP_DEBUGFS=m CONFIG_L2TP_V3=y CONFIG_L2TP_IP=m CONFIG_L2TP_ETH=m @@ -28837,7 +29142,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_BRIDGE_IGMP_SNOOPING=y CONFIG_BRIDGE_VLAN_FILTERING=y # CONFIG_BRIDGE_MRP is not set -@@ -1358,7 +1446,7 @@ CONFIG_BRIDGE_VLAN_FILTERING=y +@@ -1358,7 +1450,7 @@ CONFIG_BRIDGE_VLAN_FILTERING=y CONFIG_VLAN_8021Q=m CONFIG_VLAN_8021Q_GVRP=y CONFIG_VLAN_8021Q_MVRP=y @@ -28846,7 +29151,15 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_LLC2 is not set # CONFIG_ATALK is not set # CONFIG_X25 is not set -@@ -1513,7 +1601,54 @@ CONFIG_CAN_BCM=m +@@ -1496,6 +1588,7 @@ CONFIG_CGROUP_NET_CLASSID=y + CONFIG_NET_RX_BUSY_POLL=y + CONFIG_BQL=y + # CONFIG_BPF_STREAM_PARSER is not set ++# CONFIG_HISOCK is not set + CONFIG_NET_FLOW_LIMIT=y + + # +@@ -1513,7 +1606,54 @@ CONFIG_CAN_BCM=m CONFIG_CAN_GW=m # CONFIG_CAN_J1939 is not set # CONFIG_CAN_ISOTP is not set @@ -28902,7 +29215,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_AF_RXRPC is not set # CONFIG_AF_KCM is not set CONFIG_STREAM_PARSER=y -@@ -1522,7 +1657,7 @@ CONFIG_FIB_RULES=y +@@ -1522,7 +1662,7 @@ CONFIG_FIB_RULES=y CONFIG_WIRELESS=y CONFIG_WEXT_CORE=y CONFIG_WEXT_PROC=y @@ -28911,7 +29224,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_NL80211_TESTMODE is not set # CONFIG_CFG80211_DEVELOPER_WARNINGS is not set # CONFIG_CFG80211_CERTIFICATION_ONUS is not set -@@ -1532,7 +1667,7 @@ CONFIG_CFG80211_DEFAULT_PS=y +@@ -1532,7 +1672,7 @@ CONFIG_CFG80211_DEFAULT_PS=y # CONFIG_CFG80211_DEBUGFS is not set CONFIG_CFG80211_CRDA_SUPPORT=y CONFIG_CFG80211_WEXT=y @@ -28920,7 +29233,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_MAC80211_HAS_RC=y CONFIG_MAC80211_RC_MINSTREL=y CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y -@@ -1543,7 +1678,7 @@ CONFIG_MAC80211_DEBUGFS=y +@@ -1543,7 +1683,7 @@ CONFIG_MAC80211_DEBUGFS=y # CONFIG_MAC80211_MESSAGE_TRACING is not set # CONFIG_MAC80211_DEBUG_MENU is not set CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 @@ -28929,7 +29242,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_RFKILL_LEDS=y CONFIG_RFKILL_INPUT=y CONFIG_RFKILL_GPIO=m -@@ -1573,6 +1708,7 @@ CONFIG_FAILOVER=y +@@ -1573,6 +1713,7 @@ CONFIG_FAILOVER=y CONFIG_ETHTOOL_NETLINK=y CONFIG_NETACC_BPF=y CONFIG_NETACC_TERRACE=y @@ -28937,7 +29250,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # # Device Drivers -@@ -1595,6 +1731,7 @@ CONFIG_PCIEASPM_DEFAULT=y +@@ -1595,6 +1736,7 @@ CONFIG_PCIEASPM_DEFAULT=y CONFIG_PCIE_PME=y CONFIG_PCIE_DPC=y # CONFIG_PCIE_PTM is not set @@ -28945,7 +29258,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_PCI_MSI=y CONFIG_PCI_QUIRKS=y # CONFIG_PCI_DEBUG is not set -@@ -1606,6 +1743,7 @@ CONFIG_PCI_ECAM=y +@@ -1606,6 +1748,7 @@ CONFIG_PCI_ECAM=y CONFIG_PCI_IOV=y CONFIG_PCI_PRI=y CONFIG_PCI_PASID=y @@ -28953,7 +29266,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_PCI_DYNAMIC_OF_NODES is not set # CONFIG_PCIE_BUS_TUNE_OFF is not set CONFIG_PCIE_BUS_DEFAULT=y -@@ -1615,6 +1753,7 @@ CONFIG_PCIE_BUS_DEFAULT=y +@@ -1615,6 +1758,7 @@ CONFIG_PCIE_BUS_DEFAULT=y CONFIG_VGA_ARB=y CONFIG_VGA_ARB_MAX_GPUS=64 CONFIG_HOTPLUG_PCI=y @@ -28961,7 +29274,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_HOTPLUG_PCI_CPCI is not set CONFIG_HOTPLUG_PCI_SHPC=y -@@ -1625,6 +1764,8 @@ CONFIG_HOTPLUG_PCI_SHPC=y +@@ -1625,6 +1769,8 @@ CONFIG_HOTPLUG_PCI_SHPC=y CONFIG_PCI_HOST_COMMON=y CONFIG_PCI_HOST_GENERIC=y CONFIG_PCIE_MICROCHIP_HOST=y @@ -28970,7 +29283,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_PCIE_XILINX=y # -@@ -1636,6 +1777,7 @@ CONFIG_PCIE_CADENCE_EP=y +@@ -1636,6 +1782,7 @@ CONFIG_PCIE_CADENCE_EP=y CONFIG_PCIE_CADENCE_PLAT=y CONFIG_PCIE_CADENCE_PLAT_HOST=y CONFIG_PCIE_CADENCE_PLAT_EP=y @@ -28978,7 +29291,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_PCI_J721E=y CONFIG_PCI_J721E_HOST=y # CONFIG_PCI_J721E_EP is not set -@@ -1647,6 +1789,7 @@ CONFIG_PCI_J721E_HOST=y +@@ -1647,6 +1794,7 @@ CONFIG_PCI_J721E_HOST=y CONFIG_PCIE_DW=y CONFIG_PCIE_DW_HOST=y CONFIG_PCIE_DW_EP=y @@ -28986,7 +29299,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_PCI_MESON is not set CONFIG_PCIE_DW_PLAT=y CONFIG_PCIE_DW_PLAT_HOST=y -@@ -1697,7 +1840,9 @@ CONFIG_FW_LOADER=y +@@ -1697,7 +1845,9 @@ CONFIG_FW_LOADER=y CONFIG_FW_LOADER_DEBUG=y CONFIG_EXTRA_FIRMWARE="" # CONFIG_FW_LOADER_USER_HELPER is not set @@ -28997,7 +29310,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_FW_CACHE=y # CONFIG_FW_UPLOAD is not set # end of Firmware loader -@@ -1709,10 +1854,12 @@ CONFIG_WANT_DEV_COREDUMP=y +@@ -1709,10 +1859,12 @@ CONFIG_WANT_DEV_COREDUMP=y # CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set # CONFIG_TEST_ASYNC_DRIVER_PROBE is not set CONFIG_GENERIC_CPU_DEVICES=y @@ -29012,7 +29325,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_DMA_SHARED_BUFFER=y # CONFIG_DMA_FENCE_TRACE is not set CONFIG_GENERIC_ARCH_TOPOLOGY=y -@@ -1724,6 +1871,8 @@ CONFIG_GENERIC_ARCH_NUMA=y +@@ -1724,6 +1876,8 @@ CONFIG_GENERIC_ARCH_NUMA=y # Bus devices # # CONFIG_MOXTET is not set @@ -29021,7 +29334,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_MHI_BUS is not set # CONFIG_MHI_BUS_EP is not set # end of Bus devices -@@ -1747,6 +1896,10 @@ CONFIG_PROC_EVENTS=y +@@ -1747,6 +1901,10 @@ CONFIG_PROC_EVENTS=y # end of ARM System Control and Management Interface Protocol # CONFIG_FIRMWARE_MEMMAP is not set @@ -29032,7 +29345,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_SYSFB=y CONFIG_SYSFB_SIMPLEFB=y # CONFIG_GOOGLE_FIRMWARE is not set -@@ -1767,6 +1920,7 @@ CONFIG_EFI_GENERIC_STUB=y +@@ -1767,6 +1925,7 @@ CONFIG_EFI_GENERIC_STUB=y # CONFIG_RESET_ATTACK_MITIGATION is not set # CONFIG_EFI_DISABLE_PCI_DMA is not set CONFIG_EFI_EARLYCON=y @@ -29040,7 +29353,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_EFI_DISABLE_RUNTIME is not set # CONFIG_EFI_COCO_SECRET is not set # end of EFI (Extensible Firmware Interface) Support -@@ -1775,11 +1929,14 @@ CONFIG_EFI_EARLYCON=y +@@ -1775,11 +1934,15 @@ CONFIG_EFI_EARLYCON=y # Tegra firmware driver # # end of Tegra firmware driver @@ -29049,6 +29362,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 +CONFIG_TH1520_AON_PD=y # end of Firmware Drivers ++# CONFIG_FWCTL is not set # CONFIG_GNSS is not set -CONFIG_MTD=m -# CONFIG_MTD_TESTS is not set @@ -29057,7 +29371,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # # Partition parsers -@@ -1793,9 +1950,8 @@ CONFIG_MTD_OF_PARTS=m +@@ -1793,9 +1956,8 @@ CONFIG_MTD_OF_PARTS=m # # User Modules And Translation Layers # @@ -29069,7 +29383,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # # Note that in some cases UBI block is preferred. See MTD_UBI_BLOCK. -@@ -1862,8 +2018,8 @@ CONFIG_MTD_PHYSMAP_OF=y +@@ -1862,8 +2024,8 @@ CONFIG_MTD_PHYSMAP_OF=y # CONFIG_MTD_MCHP23K256 is not set # CONFIG_MTD_MCHP48L640 is not set # CONFIG_MTD_SST25L is not set @@ -29080,7 +29394,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_MTD_MTDRAM is not set CONFIG_MTD_BLOCK2MTD=m -@@ -1876,13 +2032,15 @@ CONFIG_MTD_BLOCK2MTD=m +@@ -1876,13 +2038,15 @@ CONFIG_MTD_BLOCK2MTD=m # # NAND # @@ -29097,7 +29411,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_MTD_NAND_ECC_SW_HAMMING is not set # CONFIG_MTD_NAND_ECC_SW_BCH is not set # CONFIG_MTD_NAND_ECC_MXIC is not set -@@ -1895,12 +2053,13 @@ CONFIG_MTD_BLOCK2MTD=m +@@ -1895,12 +2059,13 @@ CONFIG_MTD_BLOCK2MTD=m # CONFIG_MTD_LPDDR is not set # end of LPDDR & LPDDR2 PCM memory drivers @@ -29113,7 +29427,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_MTD_UBI_WL_THRESHOLD=4096 CONFIG_MTD_UBI_BEB_LIMIT=20 # CONFIG_MTD_UBI_FASTMAP is not set -@@ -1921,6 +2080,13 @@ CONFIG_OF_RESOLVE=y +@@ -1921,6 +2086,13 @@ CONFIG_OF_RESOLVE=y CONFIG_OF_OVERLAY=y CONFIG_OF_NUMA=y # CONFIG_PARPORT is not set @@ -29127,7 +29441,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_BLK_DEV=y CONFIG_BLK_DEV_NULL_BLK=m CONFIG_CDROM=y -@@ -1939,7 +2105,7 @@ CONFIG_BLK_DEV_LOOP=y +@@ -1939,7 +2111,7 @@ CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP_MIN_COUNT=0 CONFIG_BLK_DEV_DRBD=m # CONFIG_DRBD_FAULT_INJECTION is not set @@ -29136,7 +29450,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_BLK_DEV_RAM=m CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=16384 -@@ -2008,7 +2174,7 @@ CONFIG_MISC_RTSX=m +@@ -2008,7 +2180,7 @@ CONFIG_MISC_RTSX=m # # EEPROM support # @@ -29145,7 +29459,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_EEPROM_AT25 is not set CONFIG_EEPROM_LEGACY=m CONFIG_EEPROM_MAX6875=m -@@ -2028,7 +2194,6 @@ CONFIG_CB710_DEBUG_ASSUMPTIONS=y +@@ -2028,7 +2200,6 @@ CONFIG_CB710_DEBUG_ASSUMPTIONS=y # CONFIG_TI_ST is not set # end of Texas Instruments shared transport line discipline @@ -29153,7 +29467,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_SENSORS_LIS3_I2C=m CONFIG_ALTERA_STAPL=m # CONFIG_GENWQE is not set -@@ -2109,7 +2274,9 @@ CONFIG_SCSI_MPT3SAS=m +@@ -2109,7 +2280,9 @@ CONFIG_SCSI_MPT3SAS=m CONFIG_SCSI_MPT2SAS_MAX_SGE=128 CONFIG_SCSI_MPT3SAS_MAX_SGE=128 CONFIG_SCSI_MPT2SAS=m @@ -29163,7 +29477,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_SCSI_SMARTPQI=m # CONFIG_SCSI_HPTIOP is not set # CONFIG_SCSI_BUSLOGIC is not set -@@ -2156,8 +2323,11 @@ CONFIG_SCSI_DH_ALUA=y +@@ -2156,8 +2329,11 @@ CONFIG_SCSI_DH_ALUA=y CONFIG_ATA=y CONFIG_SATA_HOST=y @@ -29175,7 +29489,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_SATA_PMP=y # -@@ -2168,6 +2338,7 @@ CONFIG_SATA_MOBILE_LPM_POLICY=0 +@@ -2168,6 +2344,7 @@ CONFIG_SATA_MOBILE_LPM_POLICY=0 CONFIG_SATA_AHCI_PLATFORM=y # CONFIG_AHCI_DWC is not set # CONFIG_AHCI_CEVA is not set @@ -29183,7 +29497,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_SATA_INIC162X is not set # CONFIG_SATA_ACARD_AHCI is not set # CONFIG_SATA_SIL24 is not set -@@ -2189,6 +2360,7 @@ CONFIG_ATA_PIIX=m +@@ -2189,6 +2366,7 @@ CONFIG_ATA_PIIX=m # CONFIG_SATA_MV is not set # CONFIG_SATA_NV is not set # CONFIG_SATA_PROMISE is not set @@ -29191,7 +29505,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_SATA_SIL is not set # CONFIG_SATA_SIS is not set # CONFIG_SATA_SVW is not set -@@ -2247,6 +2419,7 @@ CONFIG_ATA_PIIX=m +@@ -2247,6 +2425,7 @@ CONFIG_ATA_PIIX=m # # Generic fallback / legacy drivers # @@ -29199,7 +29513,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_ATA_GENERIC=m # CONFIG_PATA_LEGACY is not set CONFIG_MD=y -@@ -2265,14 +2438,14 @@ CONFIG_BCACHE=m +@@ -2265,14 +2444,14 @@ CONFIG_BCACHE=m # CONFIG_BCACHE_CLOSURES_DEBUG is not set # CONFIG_BCACHE_ASYNC_REGISTRATION is not set CONFIG_BLK_DEV_DM_BUILTIN=y @@ -29216,7 +29530,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_DM_SNAPSHOT=m CONFIG_DM_THIN_PROVISIONING=m CONFIG_DM_CACHE=m -@@ -2292,6 +2465,7 @@ CONFIG_DM_MULTIPATH_ST=m +@@ -2292,6 +2471,7 @@ CONFIG_DM_MULTIPATH_ST=m # CONFIG_DM_MULTIPATH_IOA is not set CONFIG_DM_DELAY=m # CONFIG_DM_DUST is not set @@ -29224,7 +29538,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_DM_UEVENT=y CONFIG_DM_FLAKEY=m CONFIG_DM_VERITY=m -@@ -2322,7 +2496,7 @@ CONFIG_ISCSI_TARGET_CXGB4=m +@@ -2322,7 +2502,7 @@ CONFIG_ISCSI_TARGET_CXGB4=m # end of IEEE 1394 (FireWire) support CONFIG_NETDEVICES=y @@ -29233,7 +29547,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_NET_CORE=y CONFIG_BONDING=m CONFIG_DUMMY=m -@@ -2366,10 +2540,13 @@ CONFIG_VSOCKMON=m +@@ -2366,10 +2546,13 @@ CONFIG_VSOCKMON=m CONFIG_ETHERNET=y CONFIG_MDIO=m # CONFIG_NET_VENDOR_3COM is not set @@ -29247,7 +29561,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_NET_VENDOR_ALTEON is not set # CONFIG_ALTERA_TSE is not set CONFIG_NET_VENDOR_AMAZON=y -@@ -2406,14 +2583,13 @@ CONFIG_BNXT_DCB=y +@@ -2406,14 +2589,13 @@ CONFIG_BNXT_DCB=y # CONFIG_BNXT_HWMON is not set CONFIG_NET_VENDOR_CADENCE=y CONFIG_MACB=y @@ -29263,7 +29577,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_LIQUIDIO_CORE=m CONFIG_LIQUIDIO=m CONFIG_LIQUIDIO_VF=m -@@ -2441,7 +2617,10 @@ CONFIG_NET_VENDOR_ENGLEDER=y +@@ -2441,7 +2623,10 @@ CONFIG_NET_VENDOR_ENGLEDER=y CONFIG_NET_VENDOR_FUNGIBLE=y # CONFIG_FUN_ETH is not set CONFIG_NET_VENDOR_GOOGLE=y @@ -29274,7 +29588,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_NET_VENDOR_I825XX is not set CONFIG_NET_VENDOR_INTEL=y # CONFIG_E100 is not set -@@ -2464,8 +2643,13 @@ CONFIG_ICE=m +@@ -2464,8 +2649,13 @@ CONFIG_ICE=m CONFIG_ICE_SWITCHDEV=y CONFIG_FM10K=m # CONFIG_IGC is not set @@ -29288,7 +29602,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_JME is not set CONFIG_NET_VENDOR_ADI=y # CONFIG_ADIN1110 is not set -@@ -2506,6 +2690,8 @@ CONFIG_MLXFW=m +@@ -2506,6 +2696,8 @@ CONFIG_MLXFW=m CONFIG_NET_VENDOR_MICROSEMI=y # CONFIG_MSCC_OCELOT_SWITCH is not set CONFIG_NET_VENDOR_MICROSOFT=y @@ -29297,7 +29611,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_NET_VENDOR_MYRI=y # CONFIG_MYRI10GE is not set # CONFIG_FEALNX is not set -@@ -2539,6 +2725,7 @@ CONFIG_QED_OOO=y +@@ -2539,6 +2731,7 @@ CONFIG_QED_OOO=y # CONFIG_NET_VENDOR_BROCADE is not set CONFIG_NET_VENDOR_QUALCOMM=y # CONFIG_QCA7000_SPI is not set @@ -29305,7 +29619,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_QCOM_EMAC=m # CONFIG_RMNET is not set # CONFIG_NET_VENDOR_RDC is not set -@@ -2564,13 +2751,24 @@ CONFIG_SFC_MCDI_MON=y +@@ -2564,13 +2757,25 @@ CONFIG_SFC_MCDI_MON=y CONFIG_SFC_SRIOV=y CONFIG_SFC_MCDI_LOGGING=y # CONFIG_SFC_FALCON is not set @@ -29328,11 +29642,12 @@ index 61f2b2f12589..a09cebedc1c8 100644 +CONFIG_DWMAC_XUANTIE=y +CONFIG_DWMAC_SOPHGO=y +# CONFIG_DWMAC_INTEL_PLAT is not set ++# CONFIG_DWMAC_ULTRARISC is not set +# CONFIG_STMMAC_PCI is not set # CONFIG_NET_VENDOR_SUN is not set # CONFIG_NET_VENDOR_SYNOPSYS is not set # CONFIG_NET_VENDOR_TEHUTI is not set -@@ -2584,8 +2782,14 @@ CONFIG_NGBE=m +@@ -2584,8 +2789,14 @@ CONFIG_NGBE=m CONFIG_TXGBE=m # CONFIG_NET_VENDOR_WIZNET is not set # CONFIG_NET_VENDOR_XILINX is not set @@ -29347,7 +29662,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_PHYLINK=y CONFIG_PHYLIB=y CONFIG_SWPHY=y -@@ -2661,6 +2865,7 @@ CONFIG_CAN_CALC_BITTIMING=y +@@ -2661,6 +2872,7 @@ CONFIG_CAN_CALC_BITTIMING=y # CONFIG_CAN_GRCAN is not set # CONFIG_CAN_KVASER_PCIEFD is not set CONFIG_CAN_SLCAN=m @@ -29355,7 +29670,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_CAN_C_CAN=m CONFIG_CAN_C_CAN_PLATFORM=m CONFIG_CAN_C_CAN_PCI=m -@@ -2672,6 +2877,8 @@ CONFIG_CAN_CC770_PLATFORM=m +@@ -2672,6 +2884,8 @@ CONFIG_CAN_CC770_PLATFORM=m # CONFIG_CAN_IFI_CANFD is not set # CONFIG_CAN_M_CAN is not set # CONFIG_CAN_PEAK_PCIEFD is not set @@ -29364,7 +29679,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_CAN_SJA1000=m CONFIG_CAN_EMS_PCI=m # CONFIG_CAN_F81601 is not set -@@ -2711,7 +2918,9 @@ CONFIG_MDIO_DEVICE=y +@@ -2711,7 +2925,9 @@ CONFIG_MDIO_DEVICE=y CONFIG_MDIO_BUS=y CONFIG_FWNODE_MDIO=y CONFIG_OF_MDIO=y @@ -29374,7 +29689,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_MDIO_BITBANG=m CONFIG_MDIO_BCM_UNIMAC=m CONFIG_MDIO_CAVIUM=m -@@ -2728,6 +2937,7 @@ CONFIG_MDIO_THUNDER=m +@@ -2728,6 +2944,7 @@ CONFIG_MDIO_THUNDER=m # # MDIO Multiplexers # @@ -29382,7 +29697,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_MDIO_BUS_MUX_GPIO is not set # CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set # CONFIG_MDIO_BUS_MUX_MMIOREG is not set -@@ -2735,7 +2945,7 @@ CONFIG_MDIO_THUNDER=m +@@ -2735,7 +2952,7 @@ CONFIG_MDIO_THUNDER=m # # PCS device drivers # @@ -29391,7 +29706,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # end of PCS device drivers CONFIG_PPP=m -@@ -2768,8 +2978,8 @@ CONFIG_USB_RTL8150=m +@@ -2768,8 +2985,8 @@ CONFIG_USB_RTL8150=m CONFIG_USB_RTL8152=m CONFIG_USB_LAN78XX=m CONFIG_USB_USBNET=m @@ -29402,7 +29717,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_USB_NET_CDCETHER=m CONFIG_USB_NET_CDC_EEM=m CONFIG_USB_NET_CDC_NCM=m -@@ -2781,7 +2991,7 @@ CONFIG_USB_NET_SR9700=m +@@ -2781,7 +2998,7 @@ CONFIG_USB_NET_SR9700=m CONFIG_USB_NET_SMSC75XX=m CONFIG_USB_NET_SMSC95XX=m CONFIG_USB_NET_GL620A=m @@ -29411,7 +29726,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_USB_NET_PLUSB=m CONFIG_USB_NET_MCS7830=m CONFIG_USB_NET_RNDIS_HOST=m -@@ -2865,7 +3075,39 @@ CONFIG_RT2X00_LIB_CRYPTO=y +@@ -2865,7 +3082,39 @@ CONFIG_RT2X00_LIB_CRYPTO=y CONFIG_RT2X00_LIB_LEDS=y # CONFIG_RT2X00_LIB_DEBUGFS is not set # CONFIG_RT2X00_DEBUG is not set @@ -29452,7 +29767,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_WLAN_VENDOR_RSI is not set CONFIG_WLAN_VENDOR_SILABS=y # CONFIG_WFX is not set -@@ -2876,6 +3118,10 @@ CONFIG_WLAN_VENDOR_SILABS=y +@@ -2876,6 +3125,10 @@ CONFIG_WLAN_VENDOR_SILABS=y # CONFIG_USB_NET_RNDIS_WLAN is not set # CONFIG_MAC80211_HWSIM is not set # CONFIG_VIRT_WIFI is not set @@ -29463,7 +29778,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_WAN=y CONFIG_HDLC=m CONFIG_HDLC_RAW=m -@@ -2900,6 +3146,7 @@ CONFIG_HDLC_PPP=m +@@ -2900,6 +3153,7 @@ CONFIG_HDLC_PPP=m # end of Wireless WAN # CONFIG_VMXNET3 is not set @@ -29471,7 +29786,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_USB4_NET=m # CONFIG_NETDEVSIM is not set CONFIG_NET_FAILOVER=y -@@ -2930,6 +3177,7 @@ CONFIG_INPUT_EVDEV=y +@@ -2930,6 +3184,7 @@ CONFIG_INPUT_EVDEV=y # Input Device Drivers # CONFIG_INPUT_KEYBOARD=y @@ -29479,7 +29794,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_KEYBOARD_ADP5588 is not set # CONFIG_KEYBOARD_ADP5589 is not set CONFIG_KEYBOARD_ATKBD=y -@@ -2955,6 +3203,7 @@ CONFIG_KEYBOARD_GPIO=y +@@ -2955,6 +3210,7 @@ CONFIG_KEYBOARD_GPIO=y # CONFIG_KEYBOARD_GOLDFISH_EVENTS is not set # CONFIG_KEYBOARD_STOWAWAY is not set # CONFIG_KEYBOARD_SUNKBD is not set @@ -29487,7 +29802,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_KEYBOARD_OMAP4 is not set # CONFIG_KEYBOARD_TM2_TOUCHKEY is not set # CONFIG_KEYBOARD_XTKBD is not set -@@ -2987,7 +3236,83 @@ CONFIG_MOUSE_SYNAPTICS_I2C=m +@@ -2987,7 +3243,83 @@ CONFIG_MOUSE_SYNAPTICS_I2C=m CONFIG_MOUSE_SYNAPTICS_USB=m # CONFIG_INPUT_JOYSTICK is not set # CONFIG_INPUT_TABLET is not set @@ -29572,7 +29887,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_INPUT_MISC=y # CONFIG_INPUT_AD714X is not set # CONFIG_INPUT_ATMEL_CAPTOUCH is not set -@@ -3004,7 +3329,7 @@ CONFIG_INPUT_MISC=y +@@ -3004,7 +3336,7 @@ CONFIG_INPUT_MISC=y # CONFIG_INPUT_YEALINK is not set # CONFIG_INPUT_CM109 is not set # CONFIG_INPUT_REGULATOR_HAPTIC is not set @@ -29581,7 +29896,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_INPUT_PCF8574 is not set # CONFIG_INPUT_PWM_BEEPER is not set # CONFIG_INPUT_PWM_VIBRA is not set -@@ -3017,9 +3342,11 @@ CONFIG_INPUT_UINPUT=m +@@ -3017,9 +3349,11 @@ CONFIG_INPUT_UINPUT=m # CONFIG_INPUT_IQS626A is not set # CONFIG_INPUT_IQS7222 is not set # CONFIG_INPUT_CMA3000 is not set @@ -29593,7 +29908,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_RMI4_CORE=m CONFIG_RMI4_I2C=m CONFIG_RMI4_SPI=m -@@ -3048,6 +3375,7 @@ CONFIG_SERIO_ALTERA_PS2=m +@@ -3048,6 +3382,7 @@ CONFIG_SERIO_ALTERA_PS2=m # CONFIG_SERIO_PS2MULT is not set CONFIG_SERIO_ARC_PS2=m # CONFIG_SERIO_APBPS2 is not set @@ -29601,7 +29916,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_SERIO_GPIO_PS2 is not set # CONFIG_USERIO is not set # CONFIG_GAMEPORT is not set -@@ -3075,6 +3403,7 @@ CONFIG_LDISC_AUTOLOAD=y +@@ -3075,6 +3410,7 @@ CONFIG_LDISC_AUTOLOAD=y CONFIG_SERIAL_EARLYCON=y CONFIG_SERIAL_8250=y # CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set @@ -29609,7 +29924,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_SERIAL_8250_16550A_VARIANTS=y # CONFIG_SERIAL_8250_FINTEK is not set CONFIG_SERIAL_8250_CONSOLE=y -@@ -3082,8 +3411,8 @@ CONFIG_SERIAL_8250_DMA=y +@@ -3082,8 +3418,8 @@ CONFIG_SERIAL_8250_DMA=y CONFIG_SERIAL_8250_PCILIB=y CONFIG_SERIAL_8250_PCI=y CONFIG_SERIAL_8250_EXAR=y @@ -29620,7 +29935,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_SERIAL_8250_EXTENDED=y CONFIG_SERIAL_8250_MANY_PORTS=y # CONFIG_SERIAL_8250_PCI1XXXX is not set -@@ -3092,6 +3421,7 @@ CONFIG_SERIAL_8250_SHARE_IRQ=y +@@ -3092,6 +3428,7 @@ CONFIG_SERIAL_8250_SHARE_IRQ=y CONFIG_SERIAL_8250_RSA=y CONFIG_SERIAL_8250_DWLIB=y CONFIG_SERIAL_8250_DW=y @@ -29628,7 +29943,11 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_SERIAL_8250_RT288X=y CONFIG_SERIAL_8250_PERICOM=y CONFIG_SERIAL_OF_PLATFORM=y -@@ -3105,7 +3435,14 @@ CONFIG_SERIAL_OF_PLATFORM=y +@@ -3102,10 +3439,18 @@ CONFIG_SERIAL_OF_PLATFORM=y + # CONFIG_SERIAL_AMBA_PL010 is not set + # CONFIG_SERIAL_AMBA_PL011 is not set + # CONFIG_SERIAL_EARLYCON_SEMIHOST is not set ++CONFIG_SERIAL_EARLYCON_RISCV_SBI=y # CONFIG_SERIAL_KGDB_NMI is not set # CONFIG_SERIAL_MAX3100 is not set # CONFIG_SERIAL_MAX310X is not set @@ -29643,9 +29962,11 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_CONSOLE_POLL=y -@@ -3136,10 +3473,12 @@ CONFIG_N_GSM=m +@@ -3135,11 +3480,14 @@ CONFIG_N_GSM=m + # CONFIG_NOZOMI is not set # CONFIG_NULL_TTY is not set CONFIG_HVC_DRIVER=y ++# CONFIG_HVC_RISCV_SBI is not set # CONFIG_RPMSG_TTY is not set -# CONFIG_SERIAL_DEV_BUS is not set +CONFIG_SERIAL_DEV_BUS=y @@ -29657,7 +29978,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_IPMI_PLAT_DATA=y # CONFIG_IPMI_PANIC_EVENT is not set CONFIG_IPMI_DEVICE_INTERFACE=m -@@ -3154,6 +3493,7 @@ CONFIG_HW_RANDOM=y +@@ -3154,6 +3502,7 @@ CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_TIMERIOMEM=m # CONFIG_HW_RANDOM_BA431 is not set CONFIG_HW_RANDOM_VIRTIO=y @@ -29665,7 +29986,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_HW_RANDOM_CCTRNG is not set # CONFIG_HW_RANDOM_XIPHERA is not set # CONFIG_HW_RANDOM_JH7110 is not set -@@ -3172,7 +3512,10 @@ CONFIG_TCG_TIS_I2C_ATMEL=m +@@ -3172,7 +3521,10 @@ CONFIG_TCG_TIS_I2C_ATMEL=m CONFIG_TCG_TIS_I2C_INFINEON=m CONFIG_TCG_TIS_I2C_NUVOTON=m CONFIG_TCG_ATMEL=m @@ -29676,7 +29997,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_TCG_TIS_ST33ZP24=m CONFIG_TCG_TIS_ST33ZP24_I2C=m CONFIG_TCG_TIS_ST33ZP24_SPI=m -@@ -3184,6 +3527,7 @@ CONFIG_TCG_TIS_ST33ZP24_SPI=m +@@ -3184,6 +3536,7 @@ CONFIG_TCG_TIS_ST33ZP24_SPI=m # I2C support # CONFIG_I2C=y @@ -29684,7 +30005,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_I2C_BOARDINFO=y CONFIG_I2C_COMPAT=y CONFIG_I2C_CHARDEV=y -@@ -3221,6 +3565,7 @@ CONFIG_I2C_CCGX_UCSI=m +@@ -3221,6 +3574,7 @@ CONFIG_I2C_CCGX_UCSI=m # CONFIG_I2C_ALI15X3 is not set # CONFIG_I2C_AMD756 is not set # CONFIG_I2C_AMD8111 is not set @@ -29692,7 +30013,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_I2C_I801 is not set # CONFIG_I2C_ISCH is not set # CONFIG_I2C_PIIX4 is not set -@@ -3229,9 +3574,15 @@ CONFIG_I2C_NFORCE2=m +@@ -3229,9 +3583,15 @@ CONFIG_I2C_NFORCE2=m # CONFIG_I2C_SIS5595 is not set # CONFIG_I2C_SIS630 is not set # CONFIG_I2C_SIS96X is not set @@ -29708,7 +30029,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # # I2C system bus drivers (mostly embedded / system-on-chip) # -@@ -3243,12 +3594,17 @@ CONFIG_I2C_DESIGNWARE_PCI=m +@@ -3243,12 +3603,17 @@ CONFIG_I2C_DESIGNWARE_PCI=m # CONFIG_I2C_EMEV2 is not set CONFIG_I2C_GPIO=m # CONFIG_I2C_GPIO_FAULT_INJECTOR is not set @@ -29726,7 +30047,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # # External I2C/SMBus adapter drivers -@@ -3290,6 +3646,7 @@ CONFIG_SPI_MEM=y +@@ -3290,6 +3655,7 @@ CONFIG_SPI_MEM=y CONFIG_SPI_CADENCE=m # CONFIG_SPI_CADENCE_QUADSPI is not set # CONFIG_SPI_CADENCE_XSPI is not set @@ -29734,7 +30055,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_SPI_DESIGNWARE=y # CONFIG_SPI_DW_DMA is not set CONFIG_SPI_DW_PCI=m -@@ -3302,9 +3659,17 @@ CONFIG_SPI_DW_MMIO=y +@@ -3302,9 +3668,17 @@ CONFIG_SPI_DW_MMIO=y # CONFIG_SPI_PCI1XXXX is not set # CONFIG_SPI_PL022 is not set # CONFIG_SPI_PXA2XX is not set @@ -29752,7 +30073,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_SPI_MXIC is not set # CONFIG_SPI_XCOMM is not set # CONFIG_SPI_XILINX is not set -@@ -3319,7 +3684,7 @@ CONFIG_SPI_SIFIVE=y +@@ -3319,7 +3693,7 @@ CONFIG_SPI_SIFIVE=y # # SPI Protocol Masters # @@ -29761,7 +30082,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_SPI_LOOPBACK_TEST is not set # CONFIG_SPI_TLE62X0 is not set # CONFIG_SPI_SLAVE is not set -@@ -3343,14 +3708,8 @@ CONFIG_PPS_CLIENT_GPIO=m +@@ -3343,14 +3717,8 @@ CONFIG_PPS_CLIENT_GPIO=m # # PTP clock support # @@ -29777,7 +30098,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # end of PTP clock support CONFIG_PINCTRL=y -@@ -3360,26 +3719,57 @@ CONFIG_GENERIC_PINMUX_FUNCTIONS=y +@@ -3360,26 +3728,58 @@ CONFIG_GENERIC_PINMUX_FUNCTIONS=y CONFIG_PINCONF=y CONFIG_GENERIC_PINCONF=y # CONFIG_DEBUG_PINCTRL is not set @@ -29828,6 +30149,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 +# CONFIG_PINCTRL_SUN50I_H6_R is not set +# CONFIG_PINCTRL_SUN50I_H616 is not set +# CONFIG_PINCTRL_SUN50I_H616_R is not set ++# CONFIG_PINCTRL_ULTRARISC_DP1000 is not set CONFIG_GPIOLIB=y CONFIG_GPIOLIB_FASTPATH_LIMIT=512 CONFIG_OF_GPIO=y @@ -29835,7 +30157,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_GPIOLIB_IRQCHIP=y # CONFIG_DEBUG_GPIO is not set CONFIG_GPIO_SYSFS=y -@@ -3392,6 +3782,7 @@ CONFIG_GPIO_GENERIC=y +@@ -3392,6 +3792,7 @@ CONFIG_GPIO_GENERIC=y # # CONFIG_GPIO_74XX_MMIO is not set # CONFIG_GPIO_ALTERA is not set @@ -29843,7 +30165,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_GPIO_CADENCE=m CONFIG_GPIO_DWAPB=y # CONFIG_GPIO_EXAR is not set -@@ -3402,6 +3793,7 @@ CONFIG_GPIO_GENERIC_PLATFORM=m +@@ -3402,6 +3803,7 @@ CONFIG_GPIO_GENERIC_PLATFORM=m # CONFIG_GPIO_LOGICVC is not set # CONFIG_GPIO_MB86S7X is not set # CONFIG_GPIO_PL061 is not set @@ -29851,7 +30173,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_GPIO_SIFIVE=y # CONFIG_GPIO_SYSCON is not set # CONFIG_GPIO_XILINX is not set -@@ -3417,7 +3809,8 @@ CONFIG_GPIO_SIFIVE=y +@@ -3417,7 +3819,8 @@ CONFIG_GPIO_SIFIVE=y # CONFIG_GPIO_GW_PLD is not set # CONFIG_GPIO_MAX7300 is not set # CONFIG_GPIO_MAX732X is not set @@ -29861,7 +30183,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_GPIO_PCA9570 is not set # CONFIG_GPIO_PCF857X is not set # CONFIG_GPIO_TPIC2810 is not set -@@ -3461,6 +3854,7 @@ CONFIG_GPIO_SIFIVE=y +@@ -3461,6 +3864,7 @@ CONFIG_GPIO_SIFIVE=y # CONFIG_GPIO_MOCKUP is not set # CONFIG_GPIO_VIRTIO is not set # CONFIG_GPIO_SIM is not set @@ -29869,7 +30191,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # end of Virtual GPIO drivers # CONFIG_W1 is not set -@@ -3477,6 +3871,7 @@ CONFIG_POWER_RESET_SYSCON_POWEROFF=y +@@ -3477,6 +3881,7 @@ CONFIG_POWER_RESET_SYSCON_POWEROFF=y CONFIG_POWER_SUPPLY=y # CONFIG_POWER_SUPPLY_DEBUG is not set CONFIG_POWER_SUPPLY_HWMON=y @@ -29877,7 +30199,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_IP5XXX_POWER is not set # CONFIG_TEST_POWER is not set # CONFIG_CHARGER_ADP5061 is not set -@@ -3565,6 +3960,7 @@ CONFIG_SENSORS_G762=m +@@ -3565,6 +3970,7 @@ CONFIG_SENSORS_G762=m # CONFIG_SENSORS_HS3001 is not set CONFIG_SENSORS_IBMAEM=m CONFIG_SENSORS_IBMPEX=m @@ -29885,7 +30207,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_SENSORS_IT87=m CONFIG_SENSORS_JC42=m CONFIG_SENSORS_POWR1220=m -@@ -3600,7 +3996,7 @@ CONFIG_SENSORS_MAX31790=m +@@ -3600,7 +4006,7 @@ CONFIG_SENSORS_MAX31790=m CONFIG_SENSORS_MCP3021=m # CONFIG_SENSORS_TC654 is not set # CONFIG_SENSORS_TPS23861 is not set @@ -29894,7 +30216,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_SENSORS_ADCXX=m CONFIG_SENSORS_LM63=m CONFIG_SENSORS_LM70=m -@@ -3620,6 +4016,7 @@ CONFIG_SENSORS_LM95241=m +@@ -3620,6 +4026,7 @@ CONFIG_SENSORS_LM95241=m CONFIG_SENSORS_LM95245=m CONFIG_SENSORS_PC87360=m CONFIG_SENSORS_PC87427=m @@ -29902,7 +30224,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_SENSORS_NCT6683=m # CONFIG_SENSORS_NCT6775 is not set # CONFIG_SENSORS_NCT6775_I2C is not set -@@ -3680,7 +4077,7 @@ CONFIG_SENSORS_UCD9200=m +@@ -3680,7 +4087,7 @@ CONFIG_SENSORS_UCD9200=m # CONFIG_SENSORS_XDPE152 is not set # CONFIG_SENSORS_XDPE122 is not set CONFIG_SENSORS_ZL6100=m @@ -29911,7 +30233,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_SENSORS_SBTSI is not set # CONFIG_SENSORS_SBRMI is not set CONFIG_SENSORS_SHT15=m -@@ -3733,9 +4130,14 @@ CONFIG_SENSORS_W83L785TS=m +@@ -3733,9 +4140,14 @@ CONFIG_SENSORS_W83L785TS=m CONFIG_SENSORS_W83L786NG=m CONFIG_SENSORS_W83627HF=m CONFIG_SENSORS_W83627EHF=m @@ -29927,7 +30249,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 CONFIG_THERMAL_HWMON=y CONFIG_THERMAL_OF=y -@@ -3743,41 +4145,62 @@ CONFIG_THERMAL_OF=y +@@ -3743,41 +4155,62 @@ CONFIG_THERMAL_OF=y CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y # CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set # CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set @@ -29993,7 +30315,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # # PCI-based Watchdog Cards -@@ -3804,8 +4227,9 @@ CONFIG_BCMA_DRIVER_GPIO=y +@@ -3804,8 +4237,9 @@ CONFIG_BCMA_DRIVER_GPIO=y # # Multifunction device drivers # @@ -30004,7 +30326,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_MFD_AS3711 is not set # CONFIG_MFD_SMPRO is not set # CONFIG_MFD_AS3722 is not set -@@ -3877,8 +4301,8 @@ CONFIG_MFD_CORE=m +@@ -3877,8 +4311,8 @@ CONFIG_MFD_CORE=m # CONFIG_MFD_SM501 is not set # CONFIG_MFD_SKY81452 is not set # CONFIG_MFD_STMPE is not set @@ -30014,7 +30336,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_MFD_LP3943 is not set # CONFIG_MFD_LP8788 is not set # CONFIG_MFD_TI_LMU is not set -@@ -3921,6 +4345,8 @@ CONFIG_MFD_SYSCON=y +@@ -3921,6 +4355,8 @@ CONFIG_MFD_SYSCON=y # CONFIG_MFD_STMFX is not set # CONFIG_MFD_ATC260X_I2C is not set # CONFIG_MFD_QCOM_PM8008 is not set @@ -30023,7 +30345,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_MFD_INTEL_M10_BMC_SPI is not set # CONFIG_MFD_RSMU_I2C is not set # CONFIG_MFD_RSMU_SPI is not set -@@ -3987,6 +4413,7 @@ CONFIG_REGULATOR_PWM=y +@@ -3987,6 +4423,7 @@ CONFIG_REGULATOR_PWM=y # CONFIG_REGULATOR_RTQ6752 is not set # CONFIG_REGULATOR_RTQ2208 is not set # CONFIG_REGULATOR_SLG51000 is not set @@ -30031,7 +30353,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_REGULATOR_SY8106A is not set # CONFIG_REGULATOR_SY8824X is not set # CONFIG_REGULATOR_SY8827N is not set -@@ -3999,6 +4426,7 @@ CONFIG_REGULATOR_PWM=y +@@ -3999,6 +4436,7 @@ CONFIG_REGULATOR_PWM=y # CONFIG_REGULATOR_TPS65132 is not set # CONFIG_REGULATOR_TPS6524X is not set # CONFIG_REGULATOR_VCTRL is not set @@ -30039,7 +30361,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_RC_CORE is not set # -@@ -4007,7 +4435,7 @@ CONFIG_REGULATOR_PWM=y +@@ -4007,7 +4445,7 @@ CONFIG_REGULATOR_PWM=y # CONFIG_MEDIA_CEC_SUPPORT is not set # end of CEC support @@ -30048,7 +30370,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_MEDIA_SUPPORT_FILTER is not set # CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set -@@ -4131,10 +4559,12 @@ CONFIG_RADIO_ADAPTERS=m +@@ -4131,10 +4569,12 @@ CONFIG_RADIO_ADAPTERS=m # CONFIG_USB_RAREMONO is not set # CONFIG_RADIO_SI470X is not set CONFIG_MEDIA_PLATFORM_DRIVERS=y @@ -30063,7 +30385,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # # Allegro DVT media platform drivers -@@ -4173,6 +4603,7 @@ CONFIG_MEDIA_PLATFORM_DRIVERS=y +@@ -4173,6 +4613,7 @@ CONFIG_MEDIA_PLATFORM_DRIVERS=y # # Marvell media platform drivers # @@ -30071,7 +30393,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # # Mediatek media platform drivers -@@ -4197,6 +4628,15 @@ CONFIG_MEDIA_PLATFORM_DRIVERS=y +@@ -4197,6 +4638,15 @@ CONFIG_MEDIA_PLATFORM_DRIVERS=y # # Renesas media platform drivers # @@ -30087,7 +30409,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # # Rockchip media platform drivers -@@ -4213,6 +4653,11 @@ CONFIG_MEDIA_PLATFORM_DRIVERS=y +@@ -4213,6 +4663,11 @@ CONFIG_MEDIA_PLATFORM_DRIVERS=y # # Sunxi media platform drivers # @@ -30099,7 +30421,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # # Texas Instruments drivers -@@ -4221,6 +4666,7 @@ CONFIG_MEDIA_PLATFORM_DRIVERS=y +@@ -4221,6 +4676,7 @@ CONFIG_MEDIA_PLATFORM_DRIVERS=y # # Verisilicon media platform drivers # @@ -30107,7 +30429,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # # VIA media platform drivers -@@ -4229,6 +4675,7 @@ CONFIG_MEDIA_PLATFORM_DRIVERS=y +@@ -4229,6 +4685,7 @@ CONFIG_MEDIA_PLATFORM_DRIVERS=y # # Xilinx media platform drivers # @@ -30115,7 +30437,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # # MMC/SDIO DVB adapters -@@ -4283,6 +4730,7 @@ CONFIG_VIDEO_CAMERA_SENSOR=y +@@ -4283,6 +4740,7 @@ CONFIG_VIDEO_CAMERA_SENSOR=y # CONFIG_VIDEO_OV2659 is not set # CONFIG_VIDEO_OV2680 is not set # CONFIG_VIDEO_OV2685 is not set @@ -30123,7 +30445,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_VIDEO_OV4689 is not set # CONFIG_VIDEO_OV5640 is not set # CONFIG_VIDEO_OV5645 is not set -@@ -4304,6 +4752,7 @@ CONFIG_VIDEO_CAMERA_SENSOR=y +@@ -4304,6 +4762,7 @@ CONFIG_VIDEO_CAMERA_SENSOR=y # CONFIG_VIDEO_OV9282 is not set # CONFIG_VIDEO_OV9640 is not set # CONFIG_VIDEO_OV9650 is not set @@ -30131,7 +30453,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_VIDEO_RDACM20 is not set # CONFIG_VIDEO_RDACM21 is not set # CONFIG_VIDEO_RJ54N1 is not set -@@ -4341,6 +4790,7 @@ CONFIG_VIDEO_CAMERA_SENSOR=y +@@ -4341,6 +4800,7 @@ CONFIG_VIDEO_CAMERA_SENSOR=y # CONFIG_VIDEO_CS53L32A is not set # CONFIG_VIDEO_MSP3400 is not set # CONFIG_VIDEO_SONY_BTF_MPX is not set @@ -30139,7 +30461,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_VIDEO_TDA7432 is not set # CONFIG_VIDEO_TDA9840 is not set # CONFIG_VIDEO_TEA6415C is not set -@@ -4451,7 +4901,7 @@ CONFIG_CXD2880_SPI_DRV=m +@@ -4451,7 +4911,7 @@ CONFIG_CXD2880_SPI_DRV=m # CONFIG_VIDEO_GS1662 is not set # end of Media SPI Adapters @@ -30148,7 +30470,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # # Customize TV tuners -@@ -4668,6 +5118,7 @@ CONFIG_DVB_SP2=m +@@ -4668,6 +5128,7 @@ CONFIG_DVB_SP2=m # Graphics support # CONFIG_APERTURE_HELPERS=y @@ -30156,7 +30478,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_VIDEO_CMDLINE=y CONFIG_VIDEO_NOMODESET=y CONFIG_AUXDISPLAY=y -@@ -4679,6 +5130,7 @@ CONFIG_AUXDISPLAY=y +@@ -4679,6 +5140,7 @@ CONFIG_AUXDISPLAY=y # CONFIG_CHARLCD_BL_ON is not set CONFIG_CHARLCD_BL_FLASH=y CONFIG_DRM=y @@ -30164,7 +30486,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_DRM_DEBUG_MM is not set CONFIG_DRM_KMS_HELPER=y # CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set -@@ -4687,7 +5139,7 @@ CONFIG_DRM_FBDEV_EMULATION=y +@@ -4687,7 +5149,7 @@ CONFIG_DRM_FBDEV_EMULATION=y CONFIG_DRM_FBDEV_OVERALLOC=100 # CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set CONFIG_DRM_LOAD_EDID_FIRMWARE=y @@ -30173,7 +30495,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_DRM_DISPLAY_DP_HELPER=y CONFIG_DRM_DISPLAY_HDCP_HELPER=y CONFIG_DRM_DISPLAY_HDMI_HELPER=y -@@ -4720,7 +5172,7 @@ CONFIG_DRM_I2C_NXP_TDA998X=m +@@ -4720,7 +5182,7 @@ CONFIG_DRM_I2C_NXP_TDA998X=m CONFIG_DRM_RADEON=m CONFIG_DRM_RADEON_USERPTR=y CONFIG_DRM_AMDGPU=m @@ -30182,7 +30504,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_DRM_AMDGPU_CIK=y CONFIG_DRM_AMDGPU_USERPTR=y # CONFIG_DRM_AMDGPU_WERROR is not set -@@ -4735,9 +5187,13 @@ CONFIG_DRM_AMDGPU_USERPTR=y +@@ -4735,9 +5197,13 @@ CONFIG_DRM_AMDGPU_USERPTR=y # Display Engine Configuration # CONFIG_DRM_AMD_DC=y @@ -30196,7 +30518,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_DRM_NOUVEAU=m CONFIG_NOUVEAU_DEBUG=5 CONFIG_NOUVEAU_DEBUG_DEFAULT=3 -@@ -4749,6 +5205,9 @@ CONFIG_DRM_NOUVEAU_BACKLIGHT=y +@@ -4749,6 +5215,9 @@ CONFIG_DRM_NOUVEAU_BACKLIGHT=y CONFIG_DRM_UDL=m CONFIG_DRM_AST=m CONFIG_DRM_MGAG200=m @@ -30206,7 +30528,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_DRM_QXL=m CONFIG_DRM_VIRTIO_GPU=m CONFIG_DRM_VIRTIO_GPU_KMS=y -@@ -4759,36 +5218,89 @@ CONFIG_DRM_PANEL=y +@@ -4759,36 +5228,89 @@ CONFIG_DRM_PANEL=y # # CONFIG_DRM_PANEL_ABT_Y030XX067A is not set # CONFIG_DRM_PANEL_ARM_VERSATILE is not set @@ -30297,7 +30619,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # end of Display Panels CONFIG_DRM_BRIDGE=y -@@ -4834,10 +5346,16 @@ CONFIG_DRM_PANEL_BRIDGE=y +@@ -4834,10 +5356,16 @@ CONFIG_DRM_PANEL_BRIDGE=y # CONFIG_DRM_I2C_ADV7511 is not set # CONFIG_DRM_CDNS_DSI is not set # CONFIG_DRM_CDNS_MHDP8546 is not set @@ -30315,7 +30637,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_DRM_LOGICVC is not set # CONFIG_DRM_ARCPGU is not set CONFIG_DRM_BOCHS=m -@@ -4856,6 +5374,14 @@ CONFIG_DRM_CIRRUS_QEMU=m +@@ -4856,6 +5384,14 @@ CONFIG_DRM_CIRRUS_QEMU=m # CONFIG_TINYDRM_ST7735R is not set # CONFIG_DRM_GUD is not set # CONFIG_DRM_SSD130X is not set @@ -30330,7 +30652,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_DRM_LEGACY is not set CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y -@@ -4894,6 +5420,7 @@ CONFIG_FB_RADEON_BACKLIGHT=y +@@ -4894,6 +5430,7 @@ CONFIG_FB_RADEON_BACKLIGHT=y # CONFIG_FB_ARK is not set # CONFIG_FB_PM3 is not set # CONFIG_FB_CARMINE is not set @@ -30338,7 +30660,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_FB_SMSCUFX is not set # CONFIG_FB_UDL is not set # CONFIG_FB_IBM_GXT4500 is not set -@@ -4919,6 +5446,7 @@ CONFIG_FB_SYS_IMAGEBLIT=y +@@ -4919,6 +5456,7 @@ CONFIG_FB_SYS_IMAGEBLIT=y # CONFIG_FB_FOREIGN_ENDIAN is not set CONFIG_FB_SYS_FOPS=y CONFIG_FB_DEFERRED_IO=y @@ -30346,7 +30668,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_FB_IOMEM_HELPERS=y CONFIG_FB_SYSMEM_HELPERS=y CONFIG_FB_SYSMEM_HELPERS_DEFERRED=y -@@ -4946,7 +5474,7 @@ CONFIG_LCD_PLATFORM=m +@@ -4946,7 +5484,7 @@ CONFIG_LCD_PLATFORM=m CONFIG_BACKLIGHT_CLASS_DEVICE=y # CONFIG_BACKLIGHT_KTD253 is not set # CONFIG_BACKLIGHT_KTZ8866 is not set @@ -30355,7 +30677,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_BACKLIGHT_QCOM_WLED is not set # CONFIG_BACKLIGHT_ADP8860 is not set # CONFIG_BACKLIGHT_ADP8870 is not set -@@ -4960,6 +5488,7 @@ CONFIG_BACKLIGHT_GPIO=m +@@ -4960,6 +5498,7 @@ CONFIG_BACKLIGHT_GPIO=m # CONFIG_BACKLIGHT_LED is not set # end of Backlight & LCD device support @@ -30363,7 +30685,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_HDMI=y # -@@ -4983,10 +5512,13 @@ CONFIG_LOGO_LINUX_CLUT224=y +@@ -4983,10 +5522,13 @@ CONFIG_LOGO_LINUX_CLUT224=y # end of Graphics support # CONFIG_DRM_ACCEL is not set @@ -30381,7 +30703,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_SND_HWDEP=m CONFIG_SND_RAWMIDI=m CONFIG_SND_JACK=y -@@ -5010,6 +5542,7 @@ CONFIG_SND_ALOOP=m +@@ -5010,6 +5552,7 @@ CONFIG_SND_ALOOP=m # CONFIG_SND_PCMTEST is not set # CONFIG_SND_MTPAV is not set # CONFIG_SND_SERIAL_U16550 is not set @@ -30389,7 +30711,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_SND_MPU401 is not set CONFIG_SND_PCI=y # CONFIG_SND_AD1889 is not set -@@ -5074,6 +5607,11 @@ CONFIG_SND_HDA_INTEL=m +@@ -5074,6 +5617,11 @@ CONFIG_SND_HDA_INTEL=m # CONFIG_SND_HDA_RECONFIG is not set # CONFIG_SND_HDA_INPUT_BEEP is not set # CONFIG_SND_HDA_PATCH_LOADER is not set @@ -30401,7 +30723,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_SND_HDA_CODEC_REALTEK is not set # CONFIG_SND_HDA_CODEC_ANALOG is not set # CONFIG_SND_HDA_CODEC_SIGMATEL is not set -@@ -5095,7 +5633,9 @@ CONFIG_SND_HDA_POWER_SAVE_DEFAULT=0 +@@ -5095,7 +5643,9 @@ CONFIG_SND_HDA_POWER_SAVE_DEFAULT=0 CONFIG_SND_HDA_CORE=m CONFIG_SND_HDA_COMPONENT=y CONFIG_SND_HDA_PREALLOC_SIZE=64 @@ -30411,7 +30733,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_SND_SPI=y CONFIG_SND_USB=y CONFIG_SND_USB_AUDIO=m -@@ -5110,7 +5650,273 @@ CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y +@@ -5110,7 +5660,273 @@ CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y # CONFIG_SND_USB_PODHD is not set # CONFIG_SND_USB_TONEPORT is not set # CONFIG_SND_USB_VARIAX is not set @@ -30686,7 +31008,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_SND_VIRTIO is not set CONFIG_HID_SUPPORT=y CONFIG_HID=y -@@ -5195,6 +6001,7 @@ CONFIG_HID_MULTITOUCH=m +@@ -5195,6 +6011,7 @@ CONFIG_HID_MULTITOUCH=m # CONFIG_HID_NINTENDO is not set # CONFIG_HID_NTI is not set CONFIG_HID_NTRIG=y @@ -30694,7 +31016,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_HID_ORTEK=m CONFIG_HID_PANTHERLORD=m # CONFIG_PANTHERLORD_FF is not set -@@ -5261,6 +6068,7 @@ CONFIG_USB_HIDDEV=y +@@ -5261,6 +6078,7 @@ CONFIG_USB_HIDDEV=y # end of USB HID support CONFIG_I2C_HID=y @@ -30702,7 +31024,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_I2C_HID_OF is not set # CONFIG_I2C_HID_OF_ELAN is not set # CONFIG_I2C_HID_OF_GOODIX is not set -@@ -5297,6 +6105,7 @@ CONFIG_USB_XHCI_HCD=y +@@ -5297,6 +6115,7 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_PCI=y # CONFIG_USB_XHCI_PCI_RENESAS is not set CONFIG_USB_XHCI_PLATFORM=y @@ -30710,7 +31032,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_ROOT_HUB_TT=y CONFIG_USB_EHCI_TT_NEWSCHED=y -@@ -5314,6 +6123,7 @@ CONFIG_USB_UHCI_HCD=y +@@ -5314,6 +6133,7 @@ CONFIG_USB_UHCI_HCD=y # CONFIG_USB_R8A66597_HCD is not set # CONFIG_USB_HCD_BCMA is not set # CONFIG_USB_HCD_TEST_MODE is not set @@ -30718,7 +31040,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # # USB Device Class drivers -@@ -5338,8 +6148,8 @@ CONFIG_USB_STORAGE_DATAFAB=m +@@ -5338,8 +6158,8 @@ CONFIG_USB_STORAGE_DATAFAB=m CONFIG_USB_STORAGE_FREECOM=m CONFIG_USB_STORAGE_ISD200=m CONFIG_USB_STORAGE_USBAT=m @@ -30729,7 +31051,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_USB_STORAGE_JUMPSHOT=m CONFIG_USB_STORAGE_ALAUDA=m CONFIG_USB_STORAGE_ONETOUCH=m -@@ -5360,7 +6170,19 @@ CONFIG_USB_MICROTEK=m +@@ -5360,7 +6180,19 @@ CONFIG_USB_MICROTEK=m # # CONFIG_USB_CDNS_SUPPORT is not set # CONFIG_USB_MUSB_HDRC is not set @@ -30750,7 +31072,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_USB_DWC2 is not set # CONFIG_USB_CHIPIDEA is not set # CONFIG_USB_ISP1760 is not set -@@ -5452,7 +6274,7 @@ CONFIG_USB_HSIC_USB3503=m +@@ -5452,7 +6284,7 @@ CONFIG_USB_HSIC_USB3503=m # CONFIG_USB_HSIC_USB4604 is not set # CONFIG_USB_LINK_LAYER_TEST is not set CONFIG_USB_CHAOSKEY=m @@ -30759,7 +31081,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_USB_ATM=m # CONFIG_USB_SPEEDTOUCH is not set CONFIG_USB_CXACRU=m -@@ -5467,7 +6289,101 @@ CONFIG_USB_XUSBATM=m +@@ -5467,7 +6299,101 @@ CONFIG_USB_XUSBATM=m # CONFIG_USB_ISP1301 is not set # end of USB Physical Layer drivers @@ -30862,7 +31184,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_TYPEC=m CONFIG_TYPEC_TCPM=m CONFIG_TYPEC_TCPCI=m -@@ -5476,6 +6392,7 @@ CONFIG_TYPEC_TCPCI=m +@@ -5476,6 +6402,7 @@ CONFIG_TYPEC_TCPCI=m # CONFIG_TYPEC_FUSB302 is not set CONFIG_TYPEC_UCSI=m # CONFIG_UCSI_CCG is not set @@ -30870,7 +31192,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_UCSI_STM32G0 is not set # CONFIG_TYPEC_TPS6598X is not set # CONFIG_TYPEC_ANX7411 is not set -@@ -5500,7 +6417,7 @@ CONFIG_TYPEC_DP_ALTMODE=m +@@ -5500,7 +6427,7 @@ CONFIG_TYPEC_DP_ALTMODE=m # CONFIG_TYPEC_NVIDIA_ALTMODE is not set # end of USB Type-C Alternate Mode drivers @@ -30879,7 +31201,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_MMC=y CONFIG_PWRSEQ_EMMC=m CONFIG_PWRSEQ_SIMPLE=m -@@ -5519,15 +6436,19 @@ CONFIG_MMC_SDHCI=y +@@ -5519,15 +6446,19 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_IO_ACCESSORS=y CONFIG_MMC_SDHCI_PCI=m CONFIG_MMC_RICOH_MMC=y @@ -30900,7 +31222,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_MMC_CB710=m CONFIG_MMC_VIA_SDMMC=m CONFIG_MMC_DW=m -@@ -5538,18 +6459,18 @@ CONFIG_MMC_DW_BLUEFIELD=m +@@ -5538,18 +6469,18 @@ CONFIG_MMC_DW_BLUEFIELD=m # CONFIG_MMC_DW_K3 is not set CONFIG_MMC_DW_PCI=m # CONFIG_MMC_DW_STARFIVE is not set @@ -30921,7 +31243,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_SCSI_UFSHCD is not set CONFIG_MEMSTICK=m # CONFIG_MEMSTICK_DEBUG is not set -@@ -5590,7 +6511,7 @@ CONFIG_LEDS_LM3530=m +@@ -5590,7 +6521,7 @@ CONFIG_LEDS_LM3530=m # CONFIG_LEDS_LM3642 is not set # CONFIG_LEDS_LM3692X is not set # CONFIG_LEDS_PCA9532 is not set @@ -30930,7 +31252,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_LEDS_LP3944=m # CONFIG_LEDS_LP3952 is not set # CONFIG_LEDS_LP50XX is not set -@@ -5672,6 +6593,7 @@ CONFIG_INFINIBAND_USER_MEM=y +@@ -5672,6 +6603,7 @@ CONFIG_INFINIBAND_USER_MEM=y CONFIG_INFINIBAND_ON_DEMAND_PAGING=y CONFIG_INFINIBAND_ADDR_TRANS=y CONFIG_INFINIBAND_ADDR_TRANS_CONFIGFS=y @@ -30938,7 +31260,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_INFINIBAND_VIRT_DMA=y CONFIG_INFINIBAND_BNXT_RE=m CONFIG_INFINIBAND_CXGB4=m -@@ -5753,6 +6675,7 @@ CONFIG_RTC_DRV_EM3027=m +@@ -5753,6 +6685,7 @@ CONFIG_RTC_DRV_EM3027=m # CONFIG_RTC_DRV_RV3032 is not set CONFIG_RTC_DRV_RV8803=m # CONFIG_RTC_DRV_SD3078 is not set @@ -30946,7 +31268,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # # SPI RTC drivers -@@ -5804,21 +6727,28 @@ CONFIG_RTC_DRV_M48T35=m +@@ -5804,21 +6737,28 @@ CONFIG_RTC_DRV_M48T35=m CONFIG_RTC_DRV_M48T59=m CONFIG_RTC_DRV_MSM6242=m CONFIG_RTC_DRV_RP5C01=m @@ -30975,7 +31297,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_DMADEVICES=y # CONFIG_DMADEVICES_DEBUG is not set -@@ -5826,12 +6756,16 @@ CONFIG_DMADEVICES=y +@@ -5826,12 +6766,16 @@ CONFIG_DMADEVICES=y # DMA Devices # CONFIG_DMA_ENGINE=y @@ -30993,7 +31315,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_PL330_DMA is not set # CONFIG_PLX_DMA is not set # CONFIG_XILINX_DMA is not set -@@ -5844,6 +6778,8 @@ CONFIG_DW_DMAC=m +@@ -5844,6 +6788,8 @@ CONFIG_DW_DMAC=m CONFIG_DW_DMAC_PCI=m # CONFIG_DW_EDMA is not set # CONFIG_SF_PDMA is not set @@ -31002,7 +31324,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # # DMA Clients -@@ -5855,11 +6791,11 @@ CONFIG_ASYNC_TX_DMA=y +@@ -5855,11 +6801,11 @@ CONFIG_ASYNC_TX_DMA=y # DMABUF options # CONFIG_SYNC_FILE=y @@ -31017,7 +31339,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_DMABUF_HEAPS is not set # CONFIG_DMABUF_SYSFS_STATS is not set # end of DMABUF options -@@ -5879,6 +6815,7 @@ CONFIG_VFIO_GROUP=y +@@ -5879,6 +6825,7 @@ CONFIG_VFIO_GROUP=y CONFIG_VFIO_CONTAINER=y CONFIG_VFIO_NOIOMMU=y CONFIG_VFIO_VIRQFD=y @@ -31025,7 +31347,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # # VFIO support for PCI devices -@@ -5948,8 +6885,11 @@ CONFIG_COMMON_CLK=y +@@ -5948,8 +6895,11 @@ CONFIG_COMMON_CLK=y # CONFIG_COMMON_CLK_VC7 is not set # CONFIG_COMMON_CLK_FIXED_MMIO is not set CONFIG_CLK_ANALOGBITS_WRPLL_CLN28HPC=y @@ -31037,7 +31359,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_CLK_STARFIVE_JH71X0=y CONFIG_CLK_STARFIVE_JH7100=y CONFIG_CLK_STARFIVE_JH7100_AUDIO=m -@@ -5959,15 +6899,27 @@ CONFIG_CLK_STARFIVE_JH7110_AON=m +@@ -5959,15 +6909,27 @@ CONFIG_CLK_STARFIVE_JH7110_AON=m CONFIG_CLK_STARFIVE_JH7110_STG=m CONFIG_CLK_STARFIVE_JH7110_ISP=m CONFIG_CLK_STARFIVE_JH7110_VOUT=m @@ -31065,7 +31387,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_RISCV_TIMER=y # end of Clock Source drivers -@@ -5976,8 +6928,11 @@ CONFIG_MAILBOX=y +@@ -5976,8 +6938,11 @@ CONFIG_MAILBOX=y # CONFIG_ARM_MHU_V2 is not set # CONFIG_PLATFORM_MHU is not set # CONFIG_PL320_MBOX is not set @@ -31077,7 +31399,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_IOMMU_API=y CONFIG_IOMMU_SUPPORT=y -@@ -5992,6 +6947,9 @@ CONFIG_IOMMU_DEFAULT_DMA_LAZY=y +@@ -5992,6 +6957,9 @@ CONFIG_IOMMU_DEFAULT_DMA_LAZY=y # CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set CONFIG_OF_IOMMU=y # CONFIG_IOMMUFD is not set @@ -31087,7 +31409,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # # Remoteproc drivers -@@ -6007,6 +6965,7 @@ CONFIG_RPMSG_CHAR=y +@@ -6007,6 +6975,7 @@ CONFIG_RPMSG_CHAR=y CONFIG_RPMSG_CTRL=y CONFIG_RPMSG_NS=y # CONFIG_RPMSG_QCOM_GLINK_RPM is not set @@ -31095,7 +31417,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_RPMSG_VIRTIO=y # end of Rpmsg drivers -@@ -6055,22 +7014,72 @@ CONFIG_RPMSG_VIRTIO=y +@@ -6055,22 +7024,72 @@ CONFIG_RPMSG_VIRTIO=y # CONFIG_QCOM_PMIC_GLINK is not set # end of Qualcomm SoC drivers @@ -31169,7 +31491,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_EXTCON_FSA9480 is not set CONFIG_EXTCON_GPIO=m # CONFIG_EXTCON_MAX3355 is not set -@@ -6080,7 +7089,540 @@ CONFIG_EXTCON_GPIO=m +@@ -6080,7 +7099,540 @@ CONFIG_EXTCON_GPIO=m # CONFIG_EXTCON_USB_GPIO is not set # CONFIG_EXTCON_USBC_TUSB320 is not set # CONFIG_MEMORY is not set @@ -31711,7 +32033,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_NTB is not set CONFIG_PWM=y CONFIG_PWM_SYSFS=y -@@ -6090,7 +7632,12 @@ CONFIG_PWM_SYSFS=y +@@ -6090,7 +7642,12 @@ CONFIG_PWM_SYSFS=y # CONFIG_PWM_DWC is not set # CONFIG_PWM_FSL_FTM is not set # CONFIG_PWM_PCA9685 is not set @@ -31724,7 +32046,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_PWM_XILINX is not set # -@@ -6099,15 +7646,24 @@ CONFIG_PWM_SIFIVE=m +@@ -6099,15 +7656,24 @@ CONFIG_PWM_SIFIVE=m CONFIG_IRQCHIP=y # CONFIG_AL_FIC is not set # CONFIG_XILINX_INTC is not set @@ -31749,7 +32071,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_RESET_STARFIVE_JH71X0=y CONFIG_RESET_STARFIVE_JH7100=y CONFIG_RESET_STARFIVE_JH7110=y -@@ -6116,7 +7672,12 @@ CONFIG_RESET_STARFIVE_JH7110=y +@@ -6116,7 +7682,12 @@ CONFIG_RESET_STARFIVE_JH7110=y # PHY Subsystem # CONFIG_GENERIC_PHY=y @@ -31762,7 +32084,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # # PHY drivers for Broadcom platforms -@@ -6132,14 +7693,21 @@ CONFIG_GENERIC_PHY=y +@@ -6132,14 +7703,21 @@ CONFIG_GENERIC_PHY=y # CONFIG_PHY_PXA_28NM_HSIC is not set # CONFIG_PHY_PXA_28NM_USB2 is not set # CONFIG_PHY_LAN966X_SERDES is not set @@ -31784,7 +32106,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # end of PHY Subsystem # CONFIG_POWERCAP is not set -@@ -6151,6 +7719,7 @@ CONFIG_GENERIC_PHY=y +@@ -6151,6 +7729,7 @@ CONFIG_GENERIC_PHY=y CONFIG_RISCV_PMU=y CONFIG_RISCV_PMU_LEGACY=y CONFIG_RISCV_PMU_SBI=y @@ -31792,7 +32114,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # end of Performance monitor support CONFIG_RAS=y -@@ -6191,7 +7760,9 @@ CONFIG_NVMEM_SYSFS=y +@@ -6191,7 +7770,9 @@ CONFIG_NVMEM_SYSFS=y # end of Layout Types # CONFIG_NVMEM_RMEM is not set @@ -31802,7 +32124,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # # HW tracing support -@@ -6202,6 +7773,8 @@ CONFIG_NVMEM_SYSFS=y +@@ -6202,6 +7783,8 @@ CONFIG_NVMEM_SYSFS=y # CONFIG_FPGA is not set # CONFIG_FSI is not set @@ -31811,7 +32133,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_PM_OPP=y # CONFIG_SIOX is not set # CONFIG_SLIMBUS is not set -@@ -6223,6 +7796,7 @@ CONFIG_INTERCONNECT=y +@@ -6223,6 +7806,7 @@ CONFIG_INTERCONNECT=y # CONFIG_VALIDATE_FS_PARSER=y CONFIG_FS_IOMAP=y @@ -31819,7 +32141,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_BUFFER_HEAD=y CONFIG_LEGACY_DIRECT_IO=y # CONFIG_EXT2_FS is not set -@@ -6235,6 +7809,7 @@ CONFIG_EXT4_FS_POSIX_ACL=y +@@ -6235,6 +7819,7 @@ CONFIG_EXT4_FS_POSIX_ACL=y CONFIG_EXT4_FS_SECURITY=y # CONFIG_EXT4_DEBUG is not set # CONFIG_EXT4_ERROR_REPORT is not set @@ -31827,7 +32149,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_JBD2=y # CONFIG_JBD2_DEBUG is not set CONFIG_FS_MBCACHE=y -@@ -6289,10 +7864,11 @@ CONFIG_QUOTA_TREE=y +@@ -6289,10 +7874,11 @@ CONFIG_QUOTA_TREE=y CONFIG_QFMT_V2=y CONFIG_QUOTACTL=y CONFIG_AUTOFS_FS=y @@ -31841,7 +32163,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_OVERLAY_FS_REDIRECT_DIR is not set CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y # CONFIG_OVERLAY_FS_INDEX is not set -@@ -6363,9 +7939,9 @@ CONFIG_TMPFS_XATTR=y +@@ -6363,9 +7949,9 @@ CONFIG_TMPFS_XATTR=y # CONFIG_TMPFS_QUOTA is not set CONFIG_ARCH_SUPPORTS_HUGETLBFS=y CONFIG_HUGETLBFS=y @@ -31852,7 +32174,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_HUGETLB_ALLOC_LIMIT is not set CONFIG_ARCH_HAS_GIGANTIC_PAGE=y CONFIG_CONFIGFS_FS=y -@@ -6382,8 +7958,24 @@ CONFIG_MISC_FILESYSTEMS=y +@@ -6382,8 +7968,24 @@ CONFIG_MISC_FILESYSTEMS=y # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set @@ -31879,7 +32201,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_CRAMFS=m CONFIG_CRAMFS_BLOCKDEV=y # CONFIG_CRAMFS_MTD is not set -@@ -6432,7 +8024,7 @@ CONFIG_NFS_V4=y +@@ -6432,7 +8034,7 @@ CONFIG_NFS_V4=y CONFIG_NFS_V4_1=y CONFIG_NFS_V4_2=y CONFIG_PNFS_FILE_LAYOUT=y @@ -31888,7 +32210,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_PNFS_FLEXFILE_LAYOUT=m CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org" # CONFIG_NFS_V4_1_MIGRATION is not set -@@ -6518,7 +8110,7 @@ CONFIG_NLS_ISO8859_8=m +@@ -6518,7 +8120,7 @@ CONFIG_NLS_ISO8859_8=m CONFIG_NLS_CODEPAGE_1250=m CONFIG_NLS_CODEPAGE_1251=m CONFIG_NLS_ASCII=y @@ -31897,7 +32219,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_NLS_ISO8859_2=m CONFIG_NLS_ISO8859_3=m CONFIG_NLS_ISO8859_4=m -@@ -6557,6 +8149,7 @@ CONFIG_KEYS=y +@@ -6557,6 +8159,7 @@ CONFIG_KEYS=y CONFIG_PERSISTENT_KEYRINGS=y CONFIG_TRUSTED_KEYS=y CONFIG_TRUSTED_KEYS_TPM=y @@ -31905,7 +32227,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_ENCRYPTED_KEYS=y # CONFIG_USER_DECRYPTED_DATA is not set # CONFIG_KEY_DH_OPERATIONS is not set -@@ -6635,6 +8228,7 @@ CONFIG_IMA_MEASURE_ASYMMETRIC_KEYS=y +@@ -6635,6 +8238,7 @@ CONFIG_IMA_MEASURE_ASYMMETRIC_KEYS=y CONFIG_IMA_QUEUE_EARLY_BOOT_KEYS=y # CONFIG_IMA_DISABLE_HTABLE is not set # CONFIG_IMA_DIGEST_LIST is not set @@ -31913,16 +32235,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_EVM=y # CONFIG_EVM_DEFAULT_HASH_SHA1 is not set CONFIG_EVM_DEFAULT_HASH_SHA256=y -@@ -6657,6 +8251,8 @@ CONFIG_LSM="lockdown,yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,appar - # Memory initialization - # - CONFIG_INIT_STACK_NONE=y -+# CONFIG_INIT_STACK_ALL_PATTERN is not set -+# CONFIG_INIT_STACK_ALL_ZERO is not set - # CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set - # CONFIG_INIT_ON_FREE_DEFAULT_ON is not set - # CONFIG_ZERO_CALL_USED_REGS is not set -@@ -6671,8 +8267,6 @@ CONFIG_LIST_HARDENED=y +@@ -6671,8 +8275,6 @@ CONFIG_LIST_HARDENED=y CONFIG_RANDSTRUCT_NONE=y # end of Kernel hardening options @@ -31931,7 +32244,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # end of Security options CONFIG_XOR_BLOCKS=m -@@ -6693,6 +8287,7 @@ CONFIG_CRYPTO_ALGAPI=y +@@ -6693,6 +8295,7 @@ CONFIG_CRYPTO_ALGAPI=y CONFIG_CRYPTO_ALGAPI2=y CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_AEAD2=y @@ -31939,7 +32252,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_CRYPTO_SIG2=y CONFIG_CRYPTO_SKCIPHER=y CONFIG_CRYPTO_SKCIPHER2=y -@@ -6704,18 +8299,18 @@ CONFIG_CRYPTO_RNG_DEFAULT=y +@@ -6704,18 +8307,18 @@ CONFIG_CRYPTO_RNG_DEFAULT=y CONFIG_CRYPTO_AKCIPHER2=y CONFIG_CRYPTO_AKCIPHER=y CONFIG_CRYPTO_KPP2=y @@ -31961,7 +32274,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_CRYPTO_TEST=m CONFIG_CRYPTO_ENGINE=y # end of Crypto core or helper -@@ -6724,14 +8319,14 @@ CONFIG_CRYPTO_ENGINE=y +@@ -6724,14 +8327,14 @@ CONFIG_CRYPTO_ENGINE=y # Public-key cryptography # CONFIG_CRYPTO_RSA=y @@ -31980,7 +32293,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # end of Public-key cryptography # -@@ -6747,7 +8342,7 @@ CONFIG_CRYPTO_CAMELLIA=m +@@ -6747,7 +8350,7 @@ CONFIG_CRYPTO_CAMELLIA=m CONFIG_CRYPTO_CAST_COMMON=m CONFIG_CRYPTO_CAST5=m CONFIG_CRYPTO_CAST6=m @@ -31989,7 +32302,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_CRYPTO_FCRYPT=m CONFIG_CRYPTO_KHAZAD=m CONFIG_CRYPTO_SEED=m -@@ -6764,7 +8359,7 @@ CONFIG_CRYPTO_TWOFISH_COMMON=m +@@ -6764,7 +8367,7 @@ CONFIG_CRYPTO_TWOFISH_COMMON=m # # CONFIG_CRYPTO_ADIANTUM is not set CONFIG_CRYPTO_ARC4=m @@ -31998,7 +32311,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_CRYPTO_CBC=y # CONFIG_CRYPTO_CFB is not set CONFIG_CRYPTO_CTR=y -@@ -6773,35 +8368,35 @@ CONFIG_CRYPTO_ECB=y +@@ -6773,35 +8376,35 @@ CONFIG_CRYPTO_ECB=y # CONFIG_CRYPTO_HCTR2 is not set # CONFIG_CRYPTO_KEYWRAP is not set CONFIG_CRYPTO_LRW=m @@ -32041,7 +32354,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_CRYPTO_RMD160=m CONFIG_CRYPTO_SHA1=y CONFIG_CRYPTO_SHA256=y -@@ -6864,6 +8459,10 @@ CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y +@@ -6864,6 +8467,10 @@ CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y CONFIG_CRYPTO_HASH_INFO=y CONFIG_CRYPTO_HW=y @@ -32052,7 +32365,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_CRYPTO_DEV_ATMEL_ECC is not set # CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set # CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set -@@ -6871,6 +8470,7 @@ CONFIG_CRYPTO_HW=y +@@ -6871,6 +8478,7 @@ CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_QAT_C3XXX is not set # CONFIG_CRYPTO_DEV_QAT_C62X is not set # CONFIG_CRYPTO_DEV_QAT_4XXX is not set @@ -32060,7 +32373,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_CRYPTO_DEV_QAT_DH895xCCVF is not set # CONFIG_CRYPTO_DEV_QAT_C3XXXVF is not set # CONFIG_CRYPTO_DEV_QAT_C62XVF is not set -@@ -6933,16 +8533,16 @@ CONFIG_GENERIC_PCI_IOMAP=y +@@ -6933,16 +8541,16 @@ CONFIG_GENERIC_PCI_IOMAP=y # CONFIG_CRYPTO_LIB_UTILS=y CONFIG_CRYPTO_LIB_AES=y @@ -32082,7 +32395,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_CRYPTO_LIB_POLY1305 is not set # CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set CONFIG_CRYPTO_LIB_SHA1=y -@@ -7013,6 +8613,7 @@ CONFIG_HAS_IOPORT_MAP=y +@@ -7013,6 +8621,7 @@ CONFIG_HAS_IOPORT_MAP=y CONFIG_HAS_DMA=y CONFIG_NEED_DMA_MAP_STATE=y CONFIG_ARCH_DMA_ADDR_T_64BIT=y @@ -32090,7 +32403,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_DMA_DECLARE_COHERENT=y CONFIG_ARCH_HAS_SETUP_DMA_OPS=y CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y -@@ -7032,7 +8633,7 @@ CONFIG_DMA_CMA=y +@@ -7032,7 +8641,7 @@ CONFIG_DMA_CMA=y # # Default contiguous memory area size: # @@ -32099,7 +32412,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_CMA_SIZE_SEL_MBYTES=y # CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set # CONFIG_CMA_SIZE_SEL_MIN is not set -@@ -7043,7 +8644,6 @@ CONFIG_DMA_MAP_BENCHMARK=y +@@ -7043,7 +8652,6 @@ CONFIG_DMA_MAP_BENCHMARK=y CONFIG_SGL_ALLOC=y CONFIG_CHECK_SIGNATURE=y # CONFIG_CPUMASK_OFFSTACK is not set @@ -32107,15 +32420,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_CPU_RMAP=y CONFIG_DQL=y CONFIG_GLOB=y -@@ -7113,6 +8713,7 @@ CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y - # CONFIG_DEBUG_INFO_REDUCED is not set - CONFIG_DEBUG_INFO_COMPRESSED_NONE=y - # CONFIG_DEBUG_INFO_COMPRESSED_ZLIB is not set -+# CONFIG_DEBUG_INFO_SPLIT is not set - CONFIG_DEBUG_INFO_BTF=y - CONFIG_PAHOLE_HAS_SPLIT_BTF=y - CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y -@@ -7179,7 +8780,6 @@ CONFIG_SLUB_DEBUG=y +@@ -7179,7 +8787,6 @@ CONFIG_SLUB_DEBUG=y # CONFIG_PAGE_TABLE_CHECK is not set # CONFIG_PAGE_POISONING is not set # CONFIG_DEBUG_PAGE_REF is not set @@ -32123,7 +32428,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_ARCH_HAS_DEBUG_WX=y # CONFIG_DEBUG_WX is not set CONFIG_GENERIC_PTDUMP=y -@@ -7257,7 +8857,7 @@ CONFIG_LOCK_DEBUGGING_SUPPORT=y +@@ -7257,7 +8864,7 @@ CONFIG_LOCK_DEBUGGING_SUPPORT=y # CONFIG_DEBUG_LOCK_ALLOC is not set CONFIG_DEBUG_ATOMIC_SLEEP=y # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set @@ -32132,7 +32437,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_WW_MUTEX_SELFTEST is not set # CONFIG_SCF_TORTURE_TEST is not set # CONFIG_CSD_LOCK_WAIT_DEBUG is not set -@@ -7281,8 +8881,9 @@ CONFIG_DEBUG_LIST=y +@@ -7281,8 +8888,9 @@ CONFIG_DEBUG_LIST=y # # RCU Debugging # @@ -32143,7 +32448,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 # CONFIG_RCU_REF_SCALE_TEST is not set CONFIG_RCU_CPU_STALL_TIMEOUT=60 CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=0 -@@ -7358,7 +8959,38 @@ CONFIG_RING_BUFFER_BENCHMARK=m +@@ -7358,7 +8966,38 @@ CONFIG_RING_BUFFER_BENCHMARK=m # CONFIG_SYNTH_EVENT_GEN_TEST is not set # CONFIG_KPROBE_EVENT_GEN_TEST is not set # CONFIG_RV is not set @@ -32183,7 +32488,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_STRICT_DEVMEM=y CONFIG_IO_STRICT_DEVMEM=y -@@ -7376,7 +9008,47 @@ CONFIG_FUNCTION_ERROR_INJECTION=y +@@ -7376,7 +9015,47 @@ CONFIG_FUNCTION_ERROR_INJECTION=y # CONFIG_FAULT_INJECTION is not set CONFIG_ARCH_HAS_KCOV=y # CONFIG_KCOV is not set @@ -32232,7 +32537,7 @@ index 61f2b2f12589..a09cebedc1c8 100644 CONFIG_ARCH_USE_MEMTEST=y # CONFIG_MEMTEST is not set # end of Kernel Testing and Coverage -@@ -7388,9 +9060,3 @@ CONFIG_ARCH_USE_MEMTEST=y +@@ -7388,9 +9067,3 @@ CONFIG_ARCH_USE_MEMTEST=y # end of Kernel hacking # CONFIG_KWORKER_NUMA_AFFINITY is not set @@ -33025,6 +33330,44 @@ index 000000000000..5345360adfb9 +} + +#endif /* ASM_RISCV_ARCHRANDOM_H */ +diff --git a/arch/riscv/include/asm/asm-prototypes.h b/arch/riscv/include/asm/asm-prototypes.h +index 36b955c762ba..cd627ec289f1 100644 +--- a/arch/riscv/include/asm/asm-prototypes.h ++++ b/arch/riscv/include/asm/asm-prototypes.h +@@ -9,6 +9,33 @@ long long __lshrti3(long long a, int b); + long long __ashrti3(long long a, int b); + long long __ashlti3(long long a, int b); + ++#ifdef CONFIG_RISCV_ISA_V ++ ++#ifdef CONFIG_MMU ++asmlinkage int enter_vector_usercopy(void *dst, void *src, size_t n); ++#endif /* CONFIG_MMU */ ++ ++void xor_regs_2_(unsigned long bytes, unsigned long *__restrict p1, ++ const unsigned long *__restrict p2); ++void xor_regs_3_(unsigned long bytes, unsigned long *__restrict p1, ++ const unsigned long *__restrict p2, ++ const unsigned long *__restrict p3); ++void xor_regs_4_(unsigned long bytes, unsigned long *__restrict p1, ++ const unsigned long *__restrict p2, ++ const unsigned long *__restrict p3, ++ const unsigned long *__restrict p4); ++void xor_regs_5_(unsigned long bytes, unsigned long *__restrict p1, ++ const unsigned long *__restrict p2, ++ const unsigned long *__restrict p3, ++ const unsigned long *__restrict p4, ++ const unsigned long *__restrict p5); ++ ++#ifdef CONFIG_RISCV_ISA_V_PREEMPTIVE ++asmlinkage void riscv_v_context_nesting_start(struct pt_regs *regs); ++asmlinkage void riscv_v_context_nesting_end(struct pt_regs *regs); ++#endif /* CONFIG_RISCV_ISA_V_PREEMPTIVE */ ++ ++#endif /* CONFIG_RISCV_ISA_V */ + + #define DECLARE_DO_ERROR_INFO(name) asmlinkage void name(struct pt_regs *regs) + diff --git a/arch/riscv/include/asm/atomic.h b/arch/riscv/include/asm/atomic.h index f5dfef6c2153..0e0522e588ca 100644 --- a/arch/riscv/include/asm/atomic.h @@ -34306,6 +34649,34 @@ index b3b2dfbdf945..06c236bfab53 100644 /* * These are used to set parameters in the core dumps. +diff --git a/arch/riscv/include/asm/entry-common.h b/arch/riscv/include/asm/entry-common.h +index 6e4dee49d84b..b75b39a4fc10 100644 +--- a/arch/riscv/include/asm/entry-common.h ++++ b/arch/riscv/include/asm/entry-common.h +@@ -4,6 +4,23 @@ + #define _ASM_RISCV_ENTRY_COMMON_H + + #include ++#include ++#include ++ ++static inline void arch_exit_to_user_mode_prepare(struct pt_regs *regs, ++ unsigned long ti_work) ++{ ++ if (ti_work & _TIF_RISCV_V_DEFER_RESTORE) { ++ clear_thread_flag(TIF_RISCV_V_DEFER_RESTORE); ++ /* ++ * We are already called with irq disabled, so go without ++ * keeping track of riscv_v_flags. ++ */ ++ riscv_v_vstate_restore(¤t->thread.vstate, regs); ++ } ++} ++ ++#define arch_exit_to_user_mode_prepare arch_exit_to_user_mode_prepare + + void handle_page_fault(struct pt_regs *regs); + void handle_break(struct pt_regs *regs); diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h index d3f3c237adad..5469341b60ce 100644 --- a/arch/riscv/include/asm/errata_list.h @@ -34843,6 +35214,103 @@ index da5881d2bde0..000000000000 -#define IMSIC_MMIO_SETIPNUM_BE 0x04 - -#endif +diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h +index 459e61ad7d2b..a2a9dff0c07f 100644 +--- a/arch/riscv/include/asm/kvm_host.h ++++ b/arch/riscv/include/asm/kvm_host.h +@@ -41,6 +41,7 @@ + KVM_ARCH_REQ_FLAGS(4, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) + #define KVM_REQ_HFENCE \ + KVM_ARCH_REQ_FLAGS(5, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) ++#define KVM_REQ_STEAL_UPDATE KVM_ARCH_REQ(6) + + enum kvm_riscv_hfence_type { + KVM_RISCV_HFENCE_UNKNOWN = 0, +@@ -245,6 +246,12 @@ struct kvm_vcpu_arch { + + /* Performance monitoring context */ + struct kvm_pmu pmu_context; ++ ++ /* SBI steal-time accounting */ ++ struct { ++ gpa_t shmem; ++ u64 last_steal; ++ } sta; + }; + + static inline void kvm_arch_sync_events(struct kvm *kvm) {} +@@ -356,6 +363,8 @@ void __kvm_riscv_vcpu_power_off(struct kvm_vcpu *vcpu); + void kvm_riscv_vcpu_power_off(struct kvm_vcpu *vcpu); + void __kvm_riscv_vcpu_power_on(struct kvm_vcpu *vcpu); + void kvm_riscv_vcpu_power_on(struct kvm_vcpu *vcpu); ++void kvm_riscv_vcpu_sbi_sta_reset(struct kvm_vcpu *vcpu); ++void kvm_riscv_vcpu_record_steal_time(struct kvm_vcpu *vcpu); + bool kvm_riscv_vcpu_stopped(struct kvm_vcpu *vcpu); + + #endif /* __RISCV_KVM_HOST_H__ */ +diff --git a/arch/riscv/include/asm/kvm_vcpu_sbi.h b/arch/riscv/include/asm/kvm_vcpu_sbi.h +index cdcf0ff07be7..b96705258cf9 100644 +--- a/arch/riscv/include/asm/kvm_vcpu_sbi.h ++++ b/arch/riscv/include/asm/kvm_vcpu_sbi.h +@@ -11,13 +11,14 @@ + + #define KVM_SBI_IMPID 3 + +-#define KVM_SBI_VERSION_MAJOR 1 ++#define KVM_SBI_VERSION_MAJOR 2 + #define KVM_SBI_VERSION_MINOR 0 + + enum kvm_riscv_sbi_ext_status { +- KVM_RISCV_SBI_EXT_UNINITIALIZED, +- KVM_RISCV_SBI_EXT_AVAILABLE, +- KVM_RISCV_SBI_EXT_UNAVAILABLE, ++ KVM_RISCV_SBI_EXT_STATUS_UNINITIALIZED, ++ KVM_RISCV_SBI_EXT_STATUS_UNAVAILABLE, ++ KVM_RISCV_SBI_EXT_STATUS_ENABLED, ++ KVM_RISCV_SBI_EXT_STATUS_DISABLED, + }; + + struct kvm_vcpu_sbi_context { +@@ -35,6 +36,9 @@ struct kvm_vcpu_sbi_return { + struct kvm_vcpu_sbi_extension { + unsigned long extid_start; + unsigned long extid_end; ++ ++ bool default_disabled; ++ + /** + * SBI extension handler. It can be defined for a given extension or group of + * extension. But it should always return linux error codes rather than SBI +@@ -56,9 +60,20 @@ int kvm_riscv_vcpu_set_reg_sbi_ext(struct kvm_vcpu *vcpu, + const struct kvm_one_reg *reg); + int kvm_riscv_vcpu_get_reg_sbi_ext(struct kvm_vcpu *vcpu, + const struct kvm_one_reg *reg); ++int kvm_riscv_vcpu_set_reg_sbi(struct kvm_vcpu *vcpu, ++ const struct kvm_one_reg *reg); ++int kvm_riscv_vcpu_get_reg_sbi(struct kvm_vcpu *vcpu, ++ const struct kvm_one_reg *reg); + const struct kvm_vcpu_sbi_extension *kvm_vcpu_sbi_find_ext( + struct kvm_vcpu *vcpu, unsigned long extid); ++bool riscv_vcpu_supports_sbi_ext(struct kvm_vcpu *vcpu, int idx); + int kvm_riscv_vcpu_sbi_ecall(struct kvm_vcpu *vcpu, struct kvm_run *run); ++void kvm_riscv_vcpu_sbi_init(struct kvm_vcpu *vcpu); ++ ++int kvm_riscv_vcpu_get_reg_sbi_sta(struct kvm_vcpu *vcpu, unsigned long reg_num, ++ unsigned long *reg_val); ++int kvm_riscv_vcpu_set_reg_sbi_sta(struct kvm_vcpu *vcpu, unsigned long reg_num, ++ unsigned long reg_val); + + #ifdef CONFIG_RISCV_SBI_V01 + extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_v01; +@@ -69,6 +84,8 @@ extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_ipi; + extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_rfence; + extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_srst; + extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_hsm; ++extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_dbcn; ++extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_sta; + extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_experimental; + extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_vendor; + diff --git a/arch/riscv/include/asm/membarrier.h b/arch/riscv/include/asm/membarrier.h index 6c016ebb5020..47b240d0d596 100644 --- a/arch/riscv/include/asm/membarrier.h @@ -34909,6 +35377,47 @@ index 0b2333e71fdc..52ce4a399d9b 100644 #include #include +diff --git a/arch/riscv/include/asm/paravirt.h b/arch/riscv/include/asm/paravirt.h +new file mode 100644 +index 000000000000..c0abde70fc2c +--- /dev/null ++++ b/arch/riscv/include/asm/paravirt.h +@@ -0,0 +1,28 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++#ifndef _ASM_RISCV_PARAVIRT_H ++#define _ASM_RISCV_PARAVIRT_H ++ ++#ifdef CONFIG_PARAVIRT ++#include ++ ++struct static_key; ++extern struct static_key paravirt_steal_enabled; ++extern struct static_key paravirt_steal_rq_enabled; ++ ++u64 dummy_steal_clock(int cpu); ++ ++DECLARE_STATIC_CALL(pv_steal_clock, dummy_steal_clock); ++ ++static inline u64 paravirt_steal_clock(int cpu) ++{ ++ return static_call(pv_steal_clock)(cpu); ++} ++ ++int __init pv_time_init(void); ++ ++#else ++ ++#define pv_time_init() do {} while (0) ++ ++#endif /* CONFIG_PARAVIRT */ ++#endif /* _ASM_RISCV_PARAVIRT_H */ +diff --git a/arch/riscv/include/asm/paravirt_api_clock.h b/arch/riscv/include/asm/paravirt_api_clock.h +new file mode 100644 +index 000000000000..65ac7cee0dad +--- /dev/null ++++ b/arch/riscv/include/asm/paravirt_api_clock.h +@@ -0,0 +1 @@ ++#include diff --git a/arch/riscv/include/asm/pgalloc.h b/arch/riscv/include/asm/pgalloc.h index d169a4f41a2e..deaf971253a2 100644 --- a/arch/riscv/include/asm/pgalloc.h @@ -35072,7 +35581,7 @@ index e58315cedfd3..e93155c2c200 100644 { return pte_dirty(pmd_pte(pmd)); diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h -index 4f6af8c6cfa0..0de0e2e29a82 100644 +index 4f6af8c6cfa0..eb458e4cb93e 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -57,6 +57,12 @@ @@ -35088,19 +35597,100 @@ index 4f6af8c6cfa0..0de0e2e29a82 100644 /* * This decides where the kernel will search for a free chunk of vm * space during mmap's. +@@ -72,6 +78,43 @@ + struct task_struct; + struct pt_regs; + ++/* ++ * We use a flag to track in-kernel Vector context. Currently the flag has the ++ * following meaning: ++ * ++ * - bit 0: indicates whether the in-kernel Vector context is active. The ++ * activation of this state disables the preemption. On a non-RT kernel, it ++ * also disable bh. ++ * - bits 8: is used for tracking preemptible kernel-mode Vector, when ++ * RISCV_ISA_V_PREEMPTIVE is enabled. Calling kernel_vector_begin() does not ++ * disable the preemption if the thread's kernel_vstate.datap is allocated. ++ * Instead, the kernel set this bit field. Then the trap entry/exit code ++ * knows if we are entering/exiting the context that owns preempt_v. ++ * - 0: the task is not using preempt_v ++ * - 1: the task is actively using preempt_v. But whether does the task own ++ * the preempt_v context is decided by bits in RISCV_V_CTX_DEPTH_MASK. ++ * - bit 16-23 are RISCV_V_CTX_DEPTH_MASK, used by context tracking routine ++ * when preempt_v starts: ++ * - 0: the task is actively using, and own preempt_v context. ++ * - non-zero: the task was using preempt_v, but then took a trap within. ++ * Thus, the task does not own preempt_v. Any use of Vector will have to ++ * save preempt_v, if dirty, and fallback to non-preemptible kernel-mode ++ * Vector. ++ * - bit 30: The in-kernel preempt_v context is saved, and requries to be ++ * restored when returning to the context that owns the preempt_v. ++ * - bit 31: The in-kernel preempt_v context is dirty, as signaled by the ++ * trap entry code. Any context switches out-of current task need to save ++ * it to the task's in-kernel V context. Also, any traps nesting on-top-of ++ * preempt_v requesting to use V needs a save. ++ */ ++#define RISCV_V_CTX_DEPTH_MASK 0x00ff0000 ++ ++#define RISCV_V_CTX_UNIT_DEPTH 0x00010000 ++#define RISCV_KERNEL_MODE_V 0x00000001 ++#define RISCV_PREEMPT_V 0x00000100 ++#define RISCV_PREEMPT_V_DIRTY 0x80000000 ++#define RISCV_PREEMPT_V_NEED_RESTORE 0x40000000 ++ + /* CPU-specific state of a task */ + struct thread_struct { + /* Callee-saved registers */ +@@ -80,8 +123,10 @@ struct thread_struct { + unsigned long s[12]; /* s[0]: frame pointer */ + struct __riscv_d_ext_state fstate; + unsigned long bad_cause; +- unsigned long vstate_ctrl; ++ u32 riscv_v_flags; ++ u32 vstate_ctrl; + struct __riscv_v_ext_state vstate; ++ struct __riscv_v_ext_state kernel_vstate; + }; + + /* Whitelist the fstate from the task_struct for hardened usercopy */ diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h -index 3ed853b8a8c8..8d261a317175 100644 +index 3ed853b8a8c8..d9a7fd7eb8d6 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h -@@ -29,6 +29,7 @@ enum sbi_ext_id { +@@ -29,7 +29,10 @@ enum sbi_ext_id { SBI_EXT_RFENCE = 0x52464E43, SBI_EXT_HSM = 0x48534D, SBI_EXT_SRST = 0x53525354, + SBI_EXT_SUSP = 0x53555350, SBI_EXT_PMU = 0x504D55, ++ SBI_EXT_DBCN = 0x4442434E, ++ SBI_EXT_STA = 0x535441, /* Experimentals extensions must lie within this range */ -@@ -113,6 +114,14 @@ enum sbi_srst_reset_reason { + SBI_EXT_EXPERIMENTAL_START = 0x08000000, +@@ -85,6 +88,21 @@ enum sbi_hsm_hart_state { + SBI_HSM_STATE_RESUME_PENDING, + }; + ++/* SBI STA (steal-time accounting) extension */ ++enum sbi_ext_sta_fid { ++ SBI_EXT_STA_STEAL_TIME_SET_SHMEM = 0, ++}; ++ ++struct sbi_sta_struct { ++ __le32 sequence; ++ __le32 flags; ++ __le64 steal; ++ u8 preempted; ++ u8 pad[47]; ++} __packed; ++ ++#define SBI_STA_SHMEM_DISABLE -1 ++ + #define SBI_HSM_SUSP_BASE_MASK 0x7fffffff + #define SBI_HSM_SUSP_NON_RET_BIT 0x80000000 + #define SBI_HSM_SUSP_PLAT_BASE 0x10000000 +@@ -113,6 +131,14 @@ enum sbi_srst_reset_reason { SBI_SRST_RESET_REASON_SYS_FAILURE, }; @@ -35115,6 +35705,115 @@ index 3ed853b8a8c8..8d261a317175 100644 enum sbi_ext_pmu_fid { SBI_EXT_PMU_NUM_COUNTERS = 0, SBI_EXT_PMU_COUNTER_GET_INFO, +@@ -236,6 +262,12 @@ enum sbi_pmu_ctr_type { + /* Flags defined for counter stop function */ + #define SBI_PMU_STOP_FLAG_RESET (1 << 0) + ++enum sbi_ext_dbcn_fid { ++ SBI_EXT_DBCN_CONSOLE_WRITE = 0, ++ SBI_EXT_DBCN_CONSOLE_READ = 1, ++ SBI_EXT_DBCN_CONSOLE_WRITE_BYTE = 2, ++}; ++ + #define SBI_SPEC_VERSION_DEFAULT 0x1 + #define SBI_SPEC_VERSION_MAJOR_SHIFT 24 + #define SBI_SPEC_VERSION_MAJOR_MASK 0x7f +@@ -264,8 +296,13 @@ struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0, + unsigned long arg3, unsigned long arg4, + unsigned long arg5); + ++#ifdef CONFIG_RISCV_SBI_V01 + void sbi_console_putchar(int ch); + int sbi_console_getchar(void); ++#else ++static inline void sbi_console_putchar(int ch) { } ++static inline int sbi_console_getchar(void) { return -ENOENT; } ++#endif + long sbi_get_mvendorid(void); + long sbi_get_marchid(void); + long sbi_get_mimpid(void); +@@ -322,6 +359,11 @@ static inline unsigned long sbi_mk_version(unsigned long major, + } + + int sbi_err_map_linux_errno(int err); ++ ++extern bool sbi_debug_console_available; ++int sbi_debug_console_write(const char *bytes, unsigned int num_bytes); ++int sbi_debug_console_read(char *bytes, unsigned int num_bytes); ++ + #else /* CONFIG_RISCV_SBI */ + static inline int sbi_remote_fence_i(const struct cpumask *cpu_mask) { return -1; } + static inline void sbi_init(void) {} +diff --git a/arch/riscv/include/asm/simd.h b/arch/riscv/include/asm/simd.h +new file mode 100644 +index 000000000000..54efbf523d49 +--- /dev/null ++++ b/arch/riscv/include/asm/simd.h +@@ -0,0 +1,64 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++/* ++ * Copyright (C) 2017 Linaro Ltd. ++ * Copyright (C) 2023 SiFive ++ */ ++ ++#ifndef __ASM_SIMD_H ++#define __ASM_SIMD_H ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#ifdef CONFIG_RISCV_ISA_V ++/* ++ * may_use_simd - whether it is allowable at this time to issue vector ++ * instructions or access the vector register file ++ * ++ * Callers must not assume that the result remains true beyond the next ++ * preempt_enable() or return from softirq context. ++ */ ++static __must_check inline bool may_use_simd(void) ++{ ++ /* ++ * RISCV_KERNEL_MODE_V is only set while preemption is disabled, ++ * and is clear whenever preemption is enabled. ++ */ ++ if (in_hardirq() || in_nmi()) ++ return false; ++ ++ /* ++ * Nesting is acheived in preempt_v by spreading the control for ++ * preemptible and non-preemptible kernel-mode Vector into two fields. ++ * Always try to match with prempt_v if kernel V-context exists. Then, ++ * fallback to check non preempt_v if nesting happens, or if the config ++ * is not set. ++ */ ++ if (IS_ENABLED(CONFIG_RISCV_ISA_V_PREEMPTIVE) && current->thread.kernel_vstate.datap) { ++ if (!riscv_preempt_v_started(current)) ++ return true; ++ } ++ /* ++ * Non-preemptible kernel-mode Vector temporarily disables bh. So we ++ * must not return true on irq_disabled(). Otherwise we would fail the ++ * lockdep check calling local_bh_enable() ++ */ ++ return !irqs_disabled() && !(riscv_v_flags() & RISCV_KERNEL_MODE_V); ++} ++ ++#else /* ! CONFIG_RISCV_ISA_V */ ++ ++static __must_check inline bool may_use_simd(void) ++{ ++ return false; ++} ++ ++#endif /* ! CONFIG_RISCV_ISA_V */ ++ ++#endif diff --git a/arch/riscv/include/asm/sparsemem.h b/arch/riscv/include/asm/sparsemem.h index 2f901a410586..87ab782be702 100644 --- a/arch/riscv/include/asm/sparsemem.h @@ -35150,7 +35849,7 @@ index 02f87867389a..4ffb022b097f 100644 +int riscv_sbi_hart_suspend(u32 state); #endif diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/switch_to.h -index a727be723c56..7508f3ec8063 100644 +index a727be723c56..774a17b39c7d 100644 --- a/arch/riscv/include/asm/switch_to.h +++ b/arch/riscv/include/asm/switch_to.h @@ -9,7 +9,7 @@ @@ -35162,7 +35861,17 @@ index a727be723c56..7508f3ec8063 100644 #include #include #include -@@ -63,6 +63,21 @@ static __always_inline bool has_fpu(void) +@@ -53,8 +53,7 @@ static inline void __switch_to_fpu(struct task_struct *prev, + struct pt_regs *regs; + + regs = task_pt_regs(prev); +- if (unlikely(regs->status & SR_SD)) +- fstate_save(prev, regs); ++ fstate_save(prev, regs); + fstate_restore(next, task_pt_regs(next)); + } + +@@ -63,6 +62,21 @@ static __always_inline bool has_fpu(void) return riscv_has_extension_likely(RISCV_ISA_EXT_f) || riscv_has_extension_likely(RISCV_ISA_EXT_d); } @@ -35219,6 +35928,25 @@ index 000000000000..9153016da8f1 +#endif /* CONFIG_SMP */ + +#endif /* _ASM_RISCV_SYNC_CORE_H */ +diff --git a/arch/riscv/include/asm/thread_info.h b/arch/riscv/include/asm/thread_info.h +index 8c72d1bcdf14..fb10cdf02b97 100644 +--- a/arch/riscv/include/asm/thread_info.h ++++ b/arch/riscv/include/asm/thread_info.h +@@ -94,12 +94,14 @@ int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src); + #define TIF_NOTIFY_SIGNAL 9 /* signal notifications exist */ + #define TIF_UPROBE 10 /* uprobe breakpoint or singlestep */ + #define TIF_32BIT 11 /* compat-mode 32bit process */ ++#define TIF_RISCV_V_DEFER_RESTORE 12 /* restore Vector before returing to user */ + + #define _TIF_NOTIFY_RESUME (1 << TIF_NOTIFY_RESUME) + #define _TIF_SIGPENDING (1 << TIF_SIGPENDING) + #define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED) + #define _TIF_NOTIFY_SIGNAL (1 << TIF_NOTIFY_SIGNAL) + #define _TIF_UPROBE (1 << TIF_UPROBE) ++#define _TIF_RISCV_V_DEFER_RESTORE (1 << TIF_RISCV_V_DEFER_RESTORE) + + #define _TIF_WORK_MASK \ + (_TIF_NOTIFY_RESUME | _TIF_SIGPENDING | _TIF_NEED_RESCHED | \ diff --git a/arch/riscv/include/asm/tlb.h b/arch/riscv/include/asm/tlb.h index 50b63b5c15bd..1f6c38420d8e 100644 --- a/arch/riscv/include/asm/tlb.h @@ -35279,10 +36007,10 @@ index 96b65a5396df..8f383f05a290 100644 } diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h -index c5ee07b3df07..be77ae870829 100644 +index c5ee07b3df07..f371376f411c 100644 --- a/arch/riscv/include/asm/vector.h +++ b/arch/riscv/include/asm/vector.h -@@ -15,7 +15,7 @@ +@@ -15,17 +15,29 @@ #include #include #include @@ -35291,7 +36019,21 @@ index c5ee07b3df07..be77ae870829 100644 #include #include -@@ -25,7 +25,7 @@ bool riscv_v_first_use_handler(struct pt_regs *regs); + extern unsigned long riscv_v_vsize; + int riscv_v_setup_vsize(void); + bool riscv_v_first_use_handler(struct pt_regs *regs); ++void kernel_vector_begin(void); ++void kernel_vector_end(void); ++void get_cpu_vector_context(void); ++void put_cpu_vector_context(void); ++void riscv_v_thread_free(struct task_struct *tsk); ++void __init riscv_v_setup_ctx_cache(void); ++void riscv_v_thread_alloc(struct task_struct *tsk); ++ ++static inline u32 riscv_v_flags(void) ++{ ++ return READ_ONCE(current->thread.riscv_v_flags); ++} static __always_inline bool has_vector(void) { @@ -35300,7 +36042,7 @@ index c5ee07b3df07..be77ae870829 100644 } static inline void __riscv_v_vstate_clean(struct pt_regs *regs) -@@ -79,7 +79,7 @@ static __always_inline void __vstate_csr_restore(struct __riscv_v_ext_state *src +@@ -79,7 +91,7 @@ static __always_inline void __vstate_csr_restore(struct __riscv_v_ext_state *src { asm volatile ( ".option push\n\t" @@ -35309,7 +36051,7 @@ index c5ee07b3df07..be77ae870829 100644 "vsetvl x0, %2, %1\n\t" ".option pop\n\t" "csrw " __stringify(CSR_VSTART) ", %0\n\t" -@@ -97,7 +97,7 @@ static inline void __riscv_v_vstate_save(struct __riscv_v_ext_state *save_to, +@@ -97,7 +109,7 @@ static inline void __riscv_v_vstate_save(struct __riscv_v_ext_state *save_to, __vstate_csr_save(save_to); asm volatile ( ".option push\n\t" @@ -35318,7 +36060,7 @@ index c5ee07b3df07..be77ae870829 100644 "vsetvli %0, x0, e8, m8, ta, ma\n\t" "vse8.v v0, (%1)\n\t" "add %1, %1, %0\n\t" -@@ -119,7 +119,7 @@ static inline void __riscv_v_vstate_restore(struct __riscv_v_ext_state *restore_ +@@ -119,7 +131,7 @@ static inline void __riscv_v_vstate_restore(struct __riscv_v_ext_state *restore_ riscv_v_enable(); asm volatile ( ".option push\n\t" @@ -35327,7 +36069,7 @@ index c5ee07b3df07..be77ae870829 100644 "vsetvli %0, x0, e8, m8, ta, ma\n\t" "vle8.v v0, (%1)\n\t" "add %1, %1, %0\n\t" -@@ -141,7 +141,7 @@ static inline void __riscv_v_vstate_discard(void) +@@ -141,7 +153,7 @@ static inline void __riscv_v_vstate_discard(void) riscv_v_enable(); asm volatile ( ".option push\n\t" @@ -35336,6 +36078,122 @@ index c5ee07b3df07..be77ae870829 100644 "vsetvli %0, x0, e8, m8, ta, ma\n\t" "vmv.v.i v0, -1\n\t" "vmv.v.i v8, -1\n\t" +@@ -162,36 +174,89 @@ static inline void riscv_v_vstate_discard(struct pt_regs *regs) + __riscv_v_vstate_dirty(regs); + } + +-static inline void riscv_v_vstate_save(struct task_struct *task, ++static inline void riscv_v_vstate_save(struct __riscv_v_ext_state *vstate, + struct pt_regs *regs) + { + if ((regs->status & SR_VS) == SR_VS_DIRTY) { +- struct __riscv_v_ext_state *vstate = &task->thread.vstate; +- + __riscv_v_vstate_save(vstate, vstate->datap); + __riscv_v_vstate_clean(regs); + } + } + +-static inline void riscv_v_vstate_restore(struct task_struct *task, ++static inline void riscv_v_vstate_restore(struct __riscv_v_ext_state *vstate, + struct pt_regs *regs) + { + if ((regs->status & SR_VS) != SR_VS_OFF) { +- struct __riscv_v_ext_state *vstate = &task->thread.vstate; +- + __riscv_v_vstate_restore(vstate, vstate->datap); + __riscv_v_vstate_clean(regs); + } + } + ++static inline void riscv_v_vstate_set_restore(struct task_struct *task, ++ struct pt_regs *regs) ++{ ++ if ((regs->status & SR_VS) != SR_VS_OFF) { ++ set_tsk_thread_flag(task, TIF_RISCV_V_DEFER_RESTORE); ++ riscv_v_vstate_on(regs); ++ } ++} ++ ++#ifdef CONFIG_RISCV_ISA_V_PREEMPTIVE ++static inline bool riscv_preempt_v_dirty(struct task_struct *task) ++{ ++ return !!(task->thread.riscv_v_flags & RISCV_PREEMPT_V_DIRTY); ++} ++ ++static inline bool riscv_preempt_v_restore(struct task_struct *task) ++{ ++ return !!(task->thread.riscv_v_flags & RISCV_PREEMPT_V_NEED_RESTORE); ++} ++ ++static inline void riscv_preempt_v_clear_dirty(struct task_struct *task) ++{ ++ barrier(); ++ task->thread.riscv_v_flags &= ~RISCV_PREEMPT_V_DIRTY; ++} ++ ++static inline void riscv_preempt_v_set_restore(struct task_struct *task) ++{ ++ barrier(); ++ task->thread.riscv_v_flags |= RISCV_PREEMPT_V_NEED_RESTORE; ++} ++ ++static inline bool riscv_preempt_v_started(struct task_struct *task) ++{ ++ return !!(task->thread.riscv_v_flags & RISCV_PREEMPT_V); ++} ++ ++#else /* !CONFIG_RISCV_ISA_V_PREEMPTIVE */ ++static inline bool riscv_preempt_v_dirty(struct task_struct *task) { return false; } ++static inline bool riscv_preempt_v_restore(struct task_struct *task) { return false; } ++static inline bool riscv_preempt_v_started(struct task_struct *task) { return false; } ++#define riscv_preempt_v_clear_dirty(tsk) do {} while (0) ++#define riscv_preempt_v_set_restore(tsk) do {} while (0) ++#endif /* CONFIG_RISCV_ISA_V_PREEMPTIVE */ ++ + static inline void __switch_to_vector(struct task_struct *prev, + struct task_struct *next) + { + struct pt_regs *regs; + +- regs = task_pt_regs(prev); +- riscv_v_vstate_save(prev, regs); +- riscv_v_vstate_restore(next, task_pt_regs(next)); ++ if (riscv_preempt_v_started(prev)) { ++ if (riscv_preempt_v_dirty(prev)) { ++ __riscv_v_vstate_save(&prev->thread.kernel_vstate, ++ prev->thread.kernel_vstate.datap); ++ riscv_preempt_v_clear_dirty(prev); ++ } ++ } else { ++ regs = task_pt_regs(prev); ++ riscv_v_vstate_save(&prev->thread.vstate, regs); ++ } ++ ++ if (riscv_preempt_v_started(next)) ++ riscv_preempt_v_set_restore(next); ++ else ++ riscv_v_vstate_set_restore(next, task_pt_regs(next)); + } + + void riscv_v_vstate_ctrl_init(struct task_struct *tsk); +@@ -208,11 +273,14 @@ static inline bool riscv_v_vstate_query(struct pt_regs *regs) { return false; } + static inline bool riscv_v_vstate_ctrl_user_allowed(void) { return false; } + #define riscv_v_vsize (0) + #define riscv_v_vstate_discard(regs) do {} while (0) +-#define riscv_v_vstate_save(task, regs) do {} while (0) +-#define riscv_v_vstate_restore(task, regs) do {} while (0) ++#define riscv_v_vstate_save(vstate, regs) do {} while (0) ++#define riscv_v_vstate_restore(vstate, regs) do {} while (0) + #define __switch_to_vector(__prev, __next) do {} while (0) + #define riscv_v_vstate_off(regs) do {} while (0) + #define riscv_v_vstate_on(regs) do {} while (0) ++#define riscv_v_thread_free(tsk) do {} while (0) ++#define riscv_v_setup_ctx_cache() do {} while (0) ++#define riscv_v_thread_alloc(tsk) do {} while (0) + + #endif /* CONFIG_RISCV_ISA_V */ + diff --git a/arch/riscv/include/asm/vendor_extensions.h b/arch/riscv/include/asm/vendor_extensions.h new file mode 100644 index 000000000000..0517ce38c5be @@ -35483,6 +36341,80 @@ index e55407ace0c3..2f2bb0c84f9a 100644 #define SIFIVE_VENDOR_ID 0x489 #define THEAD_VENDOR_ID 0x5b7 +diff --git a/arch/riscv/include/asm/xor.h b/arch/riscv/include/asm/xor.h +new file mode 100644 +index 000000000000..96011861e46b +--- /dev/null ++++ b/arch/riscv/include/asm/xor.h +@@ -0,0 +1,68 @@ ++/* SPDX-License-Identifier: GPL-2.0-or-later */ ++/* ++ * Copyright (C) 2021 SiFive ++ */ ++ ++#include ++#include ++#ifdef CONFIG_RISCV_ISA_V ++#include ++#include ++#include ++ ++static void xor_vector_2(unsigned long bytes, unsigned long *__restrict p1, ++ const unsigned long *__restrict p2) ++{ ++ kernel_vector_begin(); ++ xor_regs_2_(bytes, p1, p2); ++ kernel_vector_end(); ++} ++ ++static void xor_vector_3(unsigned long bytes, unsigned long *__restrict p1, ++ const unsigned long *__restrict p2, ++ const unsigned long *__restrict p3) ++{ ++ kernel_vector_begin(); ++ xor_regs_3_(bytes, p1, p2, p3); ++ kernel_vector_end(); ++} ++ ++static void xor_vector_4(unsigned long bytes, unsigned long *__restrict p1, ++ const unsigned long *__restrict p2, ++ const unsigned long *__restrict p3, ++ const unsigned long *__restrict p4) ++{ ++ kernel_vector_begin(); ++ xor_regs_4_(bytes, p1, p2, p3, p4); ++ kernel_vector_end(); ++} ++ ++static void xor_vector_5(unsigned long bytes, unsigned long *__restrict p1, ++ const unsigned long *__restrict p2, ++ const unsigned long *__restrict p3, ++ const unsigned long *__restrict p4, ++ const unsigned long *__restrict p5) ++{ ++ kernel_vector_begin(); ++ xor_regs_5_(bytes, p1, p2, p3, p4, p5); ++ kernel_vector_end(); ++} ++ ++static struct xor_block_template xor_block_rvv = { ++ .name = "rvv", ++ .do_2 = xor_vector_2, ++ .do_3 = xor_vector_3, ++ .do_4 = xor_vector_4, ++ .do_5 = xor_vector_5 ++}; ++ ++#undef XOR_TRY_TEMPLATES ++#define XOR_TRY_TEMPLATES \ ++ do { \ ++ xor_speed(&xor_block_8regs); \ ++ xor_speed(&xor_block_32regs); \ ++ if (has_vector()) { \ ++ xor_speed(&xor_block_rvv);\ ++ } \ ++ } while (0) ++#endif diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h index 006bfb48343d..6fdaefa62e14 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h @@ -35560,11 +36492,46 @@ index 006bfb48343d..6fdaefa62e14 100644 +#define RISCV_HWPROBE_WHICH_CPUS (1 << 0) + #endif +diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h +index 992c5e407104..d25800e04cf2 100644 +--- a/arch/riscv/include/uapi/asm/kvm.h ++++ b/arch/riscv/include/uapi/asm/kvm.h +@@ -148,9 +148,17 @@ enum KVM_RISCV_SBI_EXT_ID { + KVM_RISCV_SBI_EXT_PMU, + KVM_RISCV_SBI_EXT_EXPERIMENTAL, + KVM_RISCV_SBI_EXT_VENDOR, ++ KVM_RISCV_SBI_EXT_DBCN, ++ KVM_RISCV_SBI_EXT_STA, + KVM_RISCV_SBI_EXT_MAX, + }; + ++/* SBI STA extension registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ ++struct kvm_riscv_sbi_sta { ++ unsigned long shmem_lo; ++ unsigned long shmem_hi; ++}; ++ + /* Possible states for kvm_riscv_timer */ + #define KVM_RISCV_TIMER_STATE_OFF 0 + #define KVM_RISCV_TIMER_STATE_ON 1 +@@ -229,6 +237,12 @@ enum KVM_RISCV_SBI_EXT_ID { + #define KVM_REG_RISCV_VECTOR_REG(n) \ + ((n) + sizeof(struct __riscv_v_ext_state) / sizeof(unsigned long)) + ++/* Registers for specific SBI extensions are mapped as type 10 */ ++#define KVM_REG_RISCV_SBI_STATE (0x0a << KVM_REG_RISCV_TYPE_SHIFT) ++#define KVM_REG_RISCV_SBI_STA (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT) ++#define KVM_REG_RISCV_SBI_STA_REG(name) \ ++ (offsetof(struct kvm_riscv_sbi_sta, name) / sizeof(unsigned long)) ++ + /* Device Control API: RISC-V AIA */ + #define KVM_DEV_RISCV_APLIC_ALIGN 0x1000 + #define KVM_DEV_RISCV_APLIC_SIZE 0x4000 diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile -index a2499fcc1cf3..70d04e1875f0 100644 +index a2499fcc1cf3..1fd2ac7f0c6b 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile -@@ -52,12 +52,15 @@ obj-y += setup.o +@@ -52,18 +52,22 @@ obj-y += setup.o obj-y += signal.o obj-y += syscall_table.o obj-y += sys_riscv.o @@ -35580,7 +36547,22 @@ index a2499fcc1cf3..70d04e1875f0 100644 obj-y += probes/ obj-$(CONFIG_MMU) += vdso.o vdso/ -@@ -104,3 +107,4 @@ obj-$(CONFIG_COMPAT) += compat_vdso/ + obj-$(CONFIG_RISCV_M_MODE) += traps_misaligned.o + obj-$(CONFIG_FPU) += fpu.o + obj-$(CONFIG_RISCV_ISA_V) += vector.o ++obj-$(CONFIG_RISCV_ISA_V) += kernel_mode_vector.o + obj-$(CONFIG_SMP) += smpboot.o + obj-$(CONFIG_SMP) += smp.o + obj-$(CONFIG_SMP) += cpu_ops.o +@@ -86,6 +90,7 @@ obj-$(CONFIG_SMP) += sbi-ipi.o + obj-$(CONFIG_SMP) += cpu_ops_sbi.o + endif + obj-$(CONFIG_HOTPLUG_CPU) += cpu-hotplug.o ++obj-$(CONFIG_PARAVIRT) += paravirt.o + obj-$(CONFIG_KGDB) += kgdb.o + obj-$(CONFIG_KEXEC_CORE) += kexec_relocate.o crash_save_regs.o machine_kexec.o + obj-$(CONFIG_KEXEC_FILE) += elf_kexec.o machine_kexec_file.o +@@ -104,3 +109,4 @@ obj-$(CONFIG_COMPAT) += compat_vdso/ obj-$(CONFIG_64BIT) += pi/ obj-$(CONFIG_ACPI) += acpi.o obj-$(CONFIG_LIVEPATCH_WO_FTRACE) += livepatch.o @@ -36703,6 +37685,437 @@ index bb5fb2b820a2..820f579e4581 100644 oldptr = ALT_OLD_PTR(alt); altptr = ALT_ALT_PTR(alt); +diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S +index 1f90fee24a8b..6d239ba461ad 100644 +--- a/arch/riscv/kernel/entry.S ++++ b/arch/riscv/kernel/entry.S +@@ -25,9 +25,9 @@ SYM_CODE_START(handle_exception) + * register will contain 0, and we should continue on the current TP. + */ + csrrw tp, CSR_SCRATCH, tp +- bnez tp, _save_context ++ bnez tp, .Lsave_context + +-_restore_kernel_tpsp: ++.Lrestore_kernel_tpsp: + csrr tp, CSR_SCRATCH + REG_S sp, TASK_TI_KERNEL_SP(tp) + +@@ -39,7 +39,7 @@ _restore_kernel_tpsp: + REG_L sp, TASK_TI_KERNEL_SP(tp) + #endif + +-_save_context: ++.Lsave_context: + REG_S sp, TASK_TI_USER_SP(tp) + REG_L sp, TASK_TI_KERNEL_SP(tp) + addi sp, sp, -(PT_SIZE_ON_STACK) +@@ -81,6 +81,11 @@ _save_context: + .option norelax + la gp, __global_pointer$ + .option pop ++ ++#ifdef CONFIG_RISCV_ISA_V_PREEMPTIVE ++ move a0, sp ++ call riscv_v_context_nesting_start ++#endif + move a0, sp /* pt_regs */ + la ra, ret_from_exception + +@@ -134,6 +139,10 @@ SYM_CODE_START_NOALIGN(ret_from_exception) + */ + csrw CSR_SCRATCH, tp + 1: ++#ifdef CONFIG_RISCV_ISA_V_PREEMPTIVE ++ move a0, sp ++ call riscv_v_context_nesting_end ++#endif + REG_L a0, PT_STATUS(sp) + /* + * The current load reservation is effectively part of the processor's +@@ -279,7 +288,7 @@ SYM_FUNC_END(__switch_to) + .section ".rodata" + .align LGREG + /* Exception vector table */ +-SYM_CODE_START(excp_vect_table) ++SYM_DATA_START_LOCAL(excp_vect_table) + RISCV_PTR do_trap_insn_misaligned + ALT_INSN_FAULT(RISCV_PTR do_trap_insn_fault) + RISCV_PTR do_trap_insn_illegal +@@ -297,12 +306,11 @@ SYM_CODE_START(excp_vect_table) + RISCV_PTR do_page_fault /* load page fault */ + RISCV_PTR do_trap_unknown + RISCV_PTR do_page_fault /* store page fault */ +-excp_vect_table_end: +-SYM_CODE_END(excp_vect_table) ++SYM_DATA_END_LABEL(excp_vect_table, SYM_L_LOCAL, excp_vect_table_end) + + #ifndef CONFIG_MMU +-SYM_CODE_START(__user_rt_sigreturn) ++SYM_DATA_START(__user_rt_sigreturn) + li a7, __NR_rt_sigreturn + ecall +-SYM_CODE_END(__user_rt_sigreturn) ++SYM_DATA_END(__user_rt_sigreturn) + #endif +diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S +index fa3443bbff21..8eec82355f92 100644 +--- a/arch/riscv/kernel/head.S ++++ b/arch/riscv/kernel/head.S +@@ -169,12 +169,12 @@ secondary_start_sbi: + XIP_FIXUP_OFFSET a0 + call relocate_enable_mmu + #endif +- call setup_trap_vector ++ call .Lsetup_trap_vector + tail smp_callin + #endif /* CONFIG_SMP */ + + .align 2 +-setup_trap_vector: ++.Lsetup_trap_vector: + /* Set trap vector to exception handler */ + la a0, handle_exception + csrw CSR_TVEC, a0 +@@ -211,7 +211,7 @@ SYM_CODE_START(_start_kernel) + * not implement PMPs, so we set up a quick trap handler to just skip + * touching the PMPs on any trap. + */ +- la a0, pmp_done ++ la a0, .Lpmp_done + csrw CSR_TVEC, a0 + + li a0, -1 +@@ -219,7 +219,7 @@ SYM_CODE_START(_start_kernel) + li a0, (PMP_A_NAPOT | PMP_R | PMP_W | PMP_X) + csrw CSR_PMPCFG0, a0 + .align 2 +-pmp_done: ++.Lpmp_done: + + /* + * The hartid in a0 is expected later on, and we have no firmware +@@ -283,12 +283,12 @@ pmp_done: + /* Clear BSS for flat non-ELF images */ + la a3, __bss_start + la a4, __bss_stop +- ble a4, a3, clear_bss_done +-clear_bss: ++ ble a4, a3, .Lclear_bss_done ++.Lclear_bss: + REG_S zero, (a3) + add a3, a3, RISCV_SZPTR +- blt a3, a4, clear_bss +-clear_bss_done: ++ blt a3, a4, .Lclear_bss ++.Lclear_bss_done: + #endif + la a2, boot_cpu_hartid + XIP_FIXUP_OFFSET a2 +@@ -315,7 +315,7 @@ clear_bss_done: + call relocate_enable_mmu + #endif /* CONFIG_MMU */ + +- call setup_trap_vector ++ call .Lsetup_trap_vector + /* Restore C environment */ + la tp, init_task + la sp, init_thread_union + THREAD_SIZE +diff --git a/arch/riscv/kernel/kernel_mode_vector.c b/arch/riscv/kernel/kernel_mode_vector.c +new file mode 100644 +index 000000000000..6afe80c7f03a +--- /dev/null ++++ b/arch/riscv/kernel/kernel_mode_vector.c +@@ -0,0 +1,247 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later ++/* ++ * Copyright (C) 2012 ARM Ltd. ++ * Author: Catalin Marinas ++ * Copyright (C) 2017 Linaro Ltd. ++ * Copyright (C) 2021 SiFive ++ */ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#ifdef CONFIG_RISCV_ISA_V_PREEMPTIVE ++#include ++#endif ++ ++static inline void riscv_v_flags_set(u32 flags) ++{ ++ WRITE_ONCE(current->thread.riscv_v_flags, flags); ++} ++ ++static inline void riscv_v_start(u32 flags) ++{ ++ int orig; ++ ++ orig = riscv_v_flags(); ++ BUG_ON((orig & flags) != 0); ++ riscv_v_flags_set(orig | flags); ++ barrier(); ++} ++ ++static inline void riscv_v_stop(u32 flags) ++{ ++ int orig; ++ ++ barrier(); ++ orig = riscv_v_flags(); ++ BUG_ON((orig & flags) == 0); ++ riscv_v_flags_set(orig & ~flags); ++} ++ ++/* ++ * Claim ownership of the CPU vector context for use by the calling context. ++ * ++ * The caller may freely manipulate the vector context metadata until ++ * put_cpu_vector_context() is called. ++ */ ++void get_cpu_vector_context(void) ++{ ++ /* ++ * disable softirqs so it is impossible for softirqs to nest ++ * get_cpu_vector_context() when kernel is actively using Vector. ++ */ ++ if (!IS_ENABLED(CONFIG_PREEMPT_RT)) ++ local_bh_disable(); ++ else ++ preempt_disable(); ++ ++ riscv_v_start(RISCV_KERNEL_MODE_V); ++} ++ ++/* ++ * Release the CPU vector context. ++ * ++ * Must be called from a context in which get_cpu_vector_context() was ++ * previously called, with no call to put_cpu_vector_context() in the ++ * meantime. ++ */ ++void put_cpu_vector_context(void) ++{ ++ riscv_v_stop(RISCV_KERNEL_MODE_V); ++ ++ if (!IS_ENABLED(CONFIG_PREEMPT_RT)) ++ local_bh_enable(); ++ else ++ preempt_enable(); ++} ++ ++#ifdef CONFIG_RISCV_ISA_V_PREEMPTIVE ++static __always_inline u32 *riscv_v_flags_ptr(void) ++{ ++ return ¤t->thread.riscv_v_flags; ++} ++ ++static inline void riscv_preempt_v_set_dirty(void) ++{ ++ *riscv_v_flags_ptr() |= RISCV_PREEMPT_V_DIRTY; ++} ++ ++static inline void riscv_preempt_v_reset_flags(void) ++{ ++ *riscv_v_flags_ptr() &= ~(RISCV_PREEMPT_V_DIRTY | RISCV_PREEMPT_V_NEED_RESTORE); ++} ++ ++static inline void riscv_v_ctx_depth_inc(void) ++{ ++ *riscv_v_flags_ptr() += RISCV_V_CTX_UNIT_DEPTH; ++} ++ ++static inline void riscv_v_ctx_depth_dec(void) ++{ ++ *riscv_v_flags_ptr() -= RISCV_V_CTX_UNIT_DEPTH; ++} ++ ++static inline u32 riscv_v_ctx_get_depth(void) ++{ ++ return *riscv_v_flags_ptr() & RISCV_V_CTX_DEPTH_MASK; ++} ++ ++static int riscv_v_stop_kernel_context(void) ++{ ++ if (riscv_v_ctx_get_depth() != 0 || !riscv_preempt_v_started(current)) ++ return 1; ++ ++ riscv_preempt_v_clear_dirty(current); ++ riscv_v_stop(RISCV_PREEMPT_V); ++ return 0; ++} ++ ++static int riscv_v_start_kernel_context(bool *is_nested) ++{ ++ struct __riscv_v_ext_state *kvstate, *uvstate; ++ ++ kvstate = ¤t->thread.kernel_vstate; ++ if (!kvstate->datap) ++ return -ENOENT; ++ ++ if (riscv_preempt_v_started(current)) { ++ WARN_ON(riscv_v_ctx_get_depth() == 0); ++ *is_nested = true; ++ get_cpu_vector_context(); ++ if (riscv_preempt_v_dirty(current)) { ++ __riscv_v_vstate_save(kvstate, kvstate->datap); ++ riscv_preempt_v_clear_dirty(current); ++ } ++ riscv_preempt_v_set_restore(current); ++ return 0; ++ } ++ ++ /* Transfer the ownership of V from user to kernel, then save */ ++ riscv_v_start(RISCV_PREEMPT_V | RISCV_PREEMPT_V_DIRTY); ++ if ((task_pt_regs(current)->status & SR_VS) == SR_VS_DIRTY) { ++ uvstate = ¤t->thread.vstate; ++ __riscv_v_vstate_save(uvstate, uvstate->datap); ++ } ++ riscv_preempt_v_clear_dirty(current); ++ return 0; ++} ++ ++/* low-level V context handling code, called with irq disabled */ ++asmlinkage void riscv_v_context_nesting_start(struct pt_regs *regs) ++{ ++ int depth; ++ ++ if (!riscv_preempt_v_started(current)) ++ return; ++ ++ depth = riscv_v_ctx_get_depth(); ++ if (depth == 0 && (regs->status & SR_VS) == SR_VS_DIRTY) ++ riscv_preempt_v_set_dirty(); ++ ++ riscv_v_ctx_depth_inc(); ++} ++ ++asmlinkage void riscv_v_context_nesting_end(struct pt_regs *regs) ++{ ++ struct __riscv_v_ext_state *vstate = ¤t->thread.kernel_vstate; ++ u32 depth; ++ ++ WARN_ON(!irqs_disabled()); ++ ++ if (!riscv_preempt_v_started(current)) ++ return; ++ ++ riscv_v_ctx_depth_dec(); ++ depth = riscv_v_ctx_get_depth(); ++ if (depth == 0) { ++ if (riscv_preempt_v_restore(current)) { ++ __riscv_v_vstate_restore(vstate, vstate->datap); ++ __riscv_v_vstate_clean(regs); ++ riscv_preempt_v_reset_flags(); ++ } ++ } ++} ++#else ++#define riscv_v_start_kernel_context(nested) (-ENOENT) ++#define riscv_v_stop_kernel_context() (-ENOENT) ++#endif /* CONFIG_RISCV_ISA_V_PREEMPTIVE */ ++ ++/* ++ * kernel_vector_begin(): obtain the CPU vector registers for use by the calling ++ * context ++ * ++ * Must not be called unless may_use_simd() returns true. ++ * Task context in the vector registers is saved back to memory as necessary. ++ * ++ * A matching call to kernel_vector_end() must be made before returning from the ++ * calling context. ++ * ++ * The caller may freely use the vector registers until kernel_vector_end() is ++ * called. ++ */ ++void kernel_vector_begin(void) ++{ ++ bool nested = false; ++ ++ if (WARN_ON(!has_vector())) ++ return; ++ ++ BUG_ON(!may_use_simd()); ++ ++ if (riscv_v_start_kernel_context(&nested)) { ++ get_cpu_vector_context(); ++ riscv_v_vstate_save(¤t->thread.vstate, task_pt_regs(current)); ++ } ++ ++ if (!nested) ++ riscv_v_vstate_set_restore(current, task_pt_regs(current)); ++ ++ riscv_v_enable(); ++} ++EXPORT_SYMBOL_GPL(kernel_vector_begin); ++ ++/* ++ * kernel_vector_end(): give the CPU vector registers back to the current task ++ * ++ * Must be called from a context in which kernel_vector_begin() was previously ++ * called, with no call to kernel_vector_end() in the meantime. ++ * ++ * The caller must not use the vector registers after this function is called, ++ * unless kernel_vector_begin() is called again in the meantime. ++ */ ++void kernel_vector_end(void) ++{ ++ if (WARN_ON(!has_vector())) ++ return; ++ ++ riscv_v_disable(); ++ ++ if (riscv_v_stop_kernel_context()) ++ put_cpu_vector_context(); ++} ++EXPORT_SYMBOL_GPL(kernel_vector_end); +diff --git a/arch/riscv/kernel/mcount.S b/arch/riscv/kernel/mcount.S +index 4d8b2819920f..b4dd9ed6849e 100644 +--- a/arch/riscv/kernel/mcount.S ++++ b/arch/riscv/kernel/mcount.S +@@ -85,16 +85,16 @@ SYM_FUNC_START(MCOUNT_NAME) + #ifdef CONFIG_FUNCTION_GRAPH_TRACER + la t0, ftrace_graph_return + REG_L t1, 0(t0) +- bne t1, t4, do_ftrace_graph_caller ++ bne t1, t4, .Ldo_ftrace_graph_caller + + la t3, ftrace_graph_entry + REG_L t2, 0(t3) + la t6, ftrace_graph_entry_stub +- bne t2, t6, do_ftrace_graph_caller ++ bne t2, t6, .Ldo_ftrace_graph_caller + #endif + la t3, ftrace_trace_function + REG_L t5, 0(t3) +- bne t5, t4, do_trace ++ bne t5, t4, .Ldo_trace + ret + + #ifdef CONFIG_FUNCTION_GRAPH_TRACER +@@ -102,7 +102,7 @@ SYM_FUNC_START(MCOUNT_NAME) + * A pseudo representation for the function graph tracer: + * prepare_to_return(&ra_to_caller_of_caller, ra_to_caller) + */ +-do_ftrace_graph_caller: ++.Ldo_ftrace_graph_caller: + addi a0, s0, -SZREG + mv a1, ra + #ifdef HAVE_FUNCTION_GRAPH_FP_TEST +@@ -118,7 +118,7 @@ do_ftrace_graph_caller: + * A pseudo representation for the function tracer: + * (*ftrace_trace_function)(ra_to_caller, ra_to_caller_of_caller) + */ +-do_trace: ++.Ldo_trace: + REG_L a1, -SZREG(s0) + mv a0, ra + diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c index df4f6fec5d17..ced5a09abaaa 100644 --- a/arch/riscv/kernel/module.c @@ -36808,17 +38221,214 @@ index df4f6fec5d17..ced5a09abaaa 100644 if (j == sechdrs[relsec].sh_size / sizeof(*rel)) { pr_err( "%s: Can not find HI20 relocation information\n", +diff --git a/arch/riscv/kernel/paravirt.c b/arch/riscv/kernel/paravirt.c +new file mode 100644 +index 000000000000..8e114f5930ce +--- /dev/null ++++ b/arch/riscv/kernel/paravirt.c +@@ -0,0 +1,135 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Copyright (c) 2023 Ventana Micro Systems Inc. ++ */ ++ ++#define pr_fmt(fmt) "riscv-pv: " fmt ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++struct static_key paravirt_steal_enabled; ++struct static_key paravirt_steal_rq_enabled; ++ ++static u64 native_steal_clock(int cpu) ++{ ++ return 0; ++} ++ ++DEFINE_STATIC_CALL(pv_steal_clock, native_steal_clock); ++ ++static bool steal_acc = true; ++static int __init parse_no_stealacc(char *arg) ++{ ++ steal_acc = false; ++ return 0; ++} ++ ++early_param("no-steal-acc", parse_no_stealacc); ++ ++DEFINE_PER_CPU(struct sbi_sta_struct, steal_time) __aligned(64); ++ ++static bool __init has_pv_steal_clock(void) ++{ ++ if (sbi_spec_version >= sbi_mk_version(2, 0) && ++ sbi_probe_extension(SBI_EXT_STA) > 0) { ++ pr_info("SBI STA extension detected\n"); ++ return true; ++ } ++ ++ return false; ++} ++ ++static int sbi_sta_steal_time_set_shmem(unsigned long lo, unsigned long hi, ++ unsigned long flags) ++{ ++ struct sbiret ret; ++ ++ ret = sbi_ecall(SBI_EXT_STA, SBI_EXT_STA_STEAL_TIME_SET_SHMEM, ++ lo, hi, flags, 0, 0, 0); ++ if (ret.error) { ++ if (lo == SBI_STA_SHMEM_DISABLE && hi == SBI_STA_SHMEM_DISABLE) ++ pr_warn("Failed to disable steal-time shmem"); ++ else ++ pr_warn("Failed to set steal-time shmem"); ++ return sbi_err_map_linux_errno(ret.error); ++ } ++ ++ return 0; ++} ++ ++static int pv_time_cpu_online(unsigned int cpu) ++{ ++ struct sbi_sta_struct *st = this_cpu_ptr(&steal_time); ++ phys_addr_t pa = __pa(st); ++ unsigned long lo = (unsigned long)pa; ++ unsigned long hi = IS_ENABLED(CONFIG_32BIT) ? upper_32_bits((u64)pa) : 0; ++ ++ return sbi_sta_steal_time_set_shmem(lo, hi, 0); ++} ++ ++static int pv_time_cpu_down_prepare(unsigned int cpu) ++{ ++ return sbi_sta_steal_time_set_shmem(SBI_STA_SHMEM_DISABLE, ++ SBI_STA_SHMEM_DISABLE, 0); ++} ++ ++static u64 pv_time_steal_clock(int cpu) ++{ ++ struct sbi_sta_struct *st = per_cpu_ptr(&steal_time, cpu); ++ u32 sequence; ++ u64 steal; ++ ++ /* ++ * Check the sequence field before and after reading the steal ++ * field. Repeat the read if it is different or odd. ++ */ ++ do { ++ sequence = READ_ONCE(st->sequence); ++ virt_rmb(); ++ steal = READ_ONCE(st->steal); ++ virt_rmb(); ++ } while ((le32_to_cpu(sequence) & 1) || ++ sequence != READ_ONCE(st->sequence)); ++ ++ return le64_to_cpu(steal); ++} ++ ++int __init pv_time_init(void) ++{ ++ int ret; ++ ++ if (!has_pv_steal_clock()) ++ return 0; ++ ++ ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, ++ "riscv/pv_time:online", ++ pv_time_cpu_online, ++ pv_time_cpu_down_prepare); ++ if (ret < 0) ++ return ret; ++ ++ static_call_update(pv_steal_clock, pv_time_steal_clock); ++ ++ static_key_slow_inc(¶virt_steal_enabled); ++ if (steal_acc) ++ static_key_slow_inc(¶virt_steal_rq_enabled); ++ ++ pr_info("Computing paravirt steal-time\n"); ++ ++ return 0; ++} diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c -index 83e223318822..dd973216e31c 100644 +index 83e223318822..d90413ededd2 100644 --- a/arch/riscv/kernel/process.c +++ b/arch/riscv/kernel/process.c -@@ -204,3 +204,6 @@ int copy_thread(struct task_struct *p, const struct kernel_clone_args *args) +@@ -151,6 +151,7 @@ void flush_thread(void) + riscv_v_vstate_off(task_pt_regs(current)); + kfree(current->thread.vstate.datap); + memset(¤t->thread.vstate, 0, sizeof(struct __riscv_v_ext_state)); ++ clear_tsk_thread_flag(current, TIF_RISCV_V_DEFER_RESTORE); + #endif + } + +@@ -158,7 +159,7 @@ void arch_release_task_struct(struct task_struct *tsk) + { + /* Free the vector context of datap. */ + if (has_vector()) +- kfree(tsk->thread.vstate.datap); ++ riscv_v_thread_free(tsk); + } + + int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) +@@ -167,6 +168,8 @@ int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) + *dst = *src; + /* clear entire V context, including datap for a new task */ + memset(&dst->thread.vstate, 0, sizeof(struct __riscv_v_ext_state)); ++ memset(&dst->thread.kernel_vstate, 0, sizeof(struct __riscv_v_ext_state)); ++ clear_tsk_thread_flag(dst, TIF_RISCV_V_DEFER_RESTORE); + + return 0; + } +@@ -200,7 +203,18 @@ int copy_thread(struct task_struct *p, const struct kernel_clone_args *args) + childregs->a0 = 0; /* Return value of fork() */ + p->thread.s[0] = 0; + } ++ p->thread.riscv_v_flags = 0; ++ if (has_vector()) ++ riscv_v_thread_alloc(p); + p->thread.ra = (unsigned long)ret_from_fork; p->thread.sp = (unsigned long)childregs; /* kernel sp */ return 0; } + ++void __init arch_task_cache_init(void) ++{ ++ riscv_v_setup_ctx_cache(); ++} ++ +EXPORT_SYMBOL_GPL(__fstate_save); +EXPORT_SYMBOL_GPL(__fstate_restore); +diff --git a/arch/riscv/kernel/ptrace.c b/arch/riscv/kernel/ptrace.c +index 2afe460de16a..e8515aa9d80b 100644 +--- a/arch/riscv/kernel/ptrace.c ++++ b/arch/riscv/kernel/ptrace.c +@@ -99,8 +99,11 @@ static int riscv_vr_get(struct task_struct *target, + * Ensure the vector registers have been saved to the memory before + * copying them to membuf. + */ +- if (target == current) +- riscv_v_vstate_save(current, task_pt_regs(current)); ++ if (target == current) { ++ get_cpu_vector_context(); ++ riscv_v_vstate_save(¤t->thread.vstate, task_pt_regs(current)); ++ put_cpu_vector_context(); ++ } + + ptrace_vstate.vstart = vstate->vstart; + ptrace_vstate.vl = vstate->vl; diff --git a/arch/riscv/kernel/sbi-ipi.c b/arch/riscv/kernel/sbi-ipi.c index a4559695ce62..0e2e19352469 100644 --- a/arch/riscv/kernel/sbi-ipi.c @@ -36910,6 +38520,97 @@ index a4559695ce62..0e2e19352469 100644 + return 0; } +IRQCHIP_DECLARE(riscv_aclint_sswi, "riscv,aclint-sswi", aclint_sswi_probe); +diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c +index 5a62ed1da453..e66e0999a800 100644 +--- a/arch/riscv/kernel/sbi.c ++++ b/arch/riscv/kernel/sbi.c +@@ -7,6 +7,7 @@ + + #include + #include ++#include + #include + #include + #include +@@ -571,6 +572,66 @@ long sbi_get_mimpid(void) + } + EXPORT_SYMBOL_GPL(sbi_get_mimpid); + ++bool sbi_debug_console_available; ++ ++int sbi_debug_console_write(const char *bytes, unsigned int num_bytes) ++{ ++ phys_addr_t base_addr; ++ struct sbiret ret; ++ ++ if (!sbi_debug_console_available) ++ return -EOPNOTSUPP; ++ ++ if (is_vmalloc_addr(bytes)) ++ base_addr = page_to_phys(vmalloc_to_page(bytes)) + ++ offset_in_page(bytes); ++ else ++ base_addr = __pa(bytes); ++ if (PAGE_SIZE < (offset_in_page(bytes) + num_bytes)) ++ num_bytes = PAGE_SIZE - offset_in_page(bytes); ++ ++ if (IS_ENABLED(CONFIG_32BIT)) ++ ret = sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_WRITE, ++ num_bytes, lower_32_bits(base_addr), ++ upper_32_bits(base_addr), 0, 0, 0); ++ else ++ ret = sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_WRITE, ++ num_bytes, base_addr, 0, 0, 0, 0); ++ ++ if (ret.error == SBI_ERR_FAILURE) ++ return -EIO; ++ return ret.error ? sbi_err_map_linux_errno(ret.error) : ret.value; ++} ++ ++int sbi_debug_console_read(char *bytes, unsigned int num_bytes) ++{ ++ phys_addr_t base_addr; ++ struct sbiret ret; ++ ++ if (!sbi_debug_console_available) ++ return -EOPNOTSUPP; ++ ++ if (is_vmalloc_addr(bytes)) ++ base_addr = page_to_phys(vmalloc_to_page(bytes)) + ++ offset_in_page(bytes); ++ else ++ base_addr = __pa(bytes); ++ if (PAGE_SIZE < (offset_in_page(bytes) + num_bytes)) ++ num_bytes = PAGE_SIZE - offset_in_page(bytes); ++ ++ if (IS_ENABLED(CONFIG_32BIT)) ++ ret = sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_READ, ++ num_bytes, lower_32_bits(base_addr), ++ upper_32_bits(base_addr), 0, 0, 0); ++ else ++ ret = sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_READ, ++ num_bytes, base_addr, 0, 0, 0, 0); ++ ++ if (ret.error == SBI_ERR_FAILURE) ++ return -EIO; ++ return ret.error ? sbi_err_map_linux_errno(ret.error) : ret.value; ++} ++ + void __init sbi_init(void) + { + int ret; +@@ -612,6 +673,11 @@ void __init sbi_init(void) + sbi_srst_reboot_nb.priority = 192; + register_restart_handler(&sbi_srst_reboot_nb); + } ++ if ((sbi_spec_version >= sbi_mk_version(2, 0)) && ++ (sbi_probe_extension(SBI_EXT_DBCN) > 0)) { ++ pr_info("SBI DBCN extension detected\n"); ++ sbi_debug_console_available = true; ++ } + } else { + __sbi_set_timer = __sbi_set_timer_v01; + __sbi_send_ipi = __sbi_send_ipi_v01; diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c index c2cdf812ebd0..d949fd3c0884 100644 --- a/arch/riscv/kernel/setup.c @@ -36946,6 +38647,51 @@ index c2cdf812ebd0..d949fd3c0884 100644 } bool arch_cpu_is_hotpluggable(int cpu) +diff --git a/arch/riscv/kernel/signal.c b/arch/riscv/kernel/signal.c +index 048b9b23d754..0e3bdd520617 100644 +--- a/arch/riscv/kernel/signal.c ++++ b/arch/riscv/kernel/signal.c +@@ -86,7 +86,10 @@ static long save_v_state(struct pt_regs *regs, void __user **sc_vec) + /* datap is designed to be 16 byte aligned for better performance */ + WARN_ON(unlikely(!IS_ALIGNED((unsigned long)datap, 16))); + +- riscv_v_vstate_save(current, regs); ++ get_cpu_vector_context(); ++ riscv_v_vstate_save(¤t->thread.vstate, regs); ++ put_cpu_vector_context(); ++ + /* Copy everything of vstate but datap. */ + err = __copy_to_user(&state->v_state, ¤t->thread.vstate, + offsetof(struct __riscv_v_ext_state, datap)); +@@ -116,6 +119,13 @@ static long __restore_v_state(struct pt_regs *regs, void __user *sc_vec) + struct __sc_riscv_v_state __user *state = sc_vec; + void __user *datap; + ++ /* ++ * Mark the vstate as clean prior performing the actual copy, ++ * to avoid getting the vstate incorrectly clobbered by the ++ * discarded vector state. ++ */ ++ riscv_v_vstate_set_restore(current, regs); ++ + /* Copy everything of __sc_riscv_v_state except datap. */ + err = __copy_from_user(¤t->thread.vstate, &state->v_state, + offsetof(struct __riscv_v_ext_state, datap)); +@@ -130,13 +140,7 @@ static long __restore_v_state(struct pt_regs *regs, void __user *sc_vec) + * Copy the whole vector content from user space datap. Use + * copy_from_user to prevent information leak. + */ +- err = copy_from_user(current->thread.vstate.datap, datap, riscv_v_vsize); +- if (unlikely(err)) +- return err; +- +- riscv_v_vstate_restore(current, regs); +- +- return err; ++ return copy_from_user(current->thread.vstate.datap, datap, riscv_v_vsize); + } + #else + #define save_v_state(task, regs) (0) diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c index 40420afbb1a0..ccb0f93c9786 100644 --- a/arch/riscv/kernel/smp.c @@ -37797,6 +39543,25 @@ index 473159b5f303..f1c1416a9f1e 100644 /* Not defined using SYSCALL_DEFINE0 to avoid error injection */ asmlinkage long __riscv_sys_ni_syscall(const struct pt_regs *__unused) { +diff --git a/arch/riscv/kernel/time.c b/arch/riscv/kernel/time.c +index 23641e82a9df..ba3477197789 100644 +--- a/arch/riscv/kernel/time.c ++++ b/arch/riscv/kernel/time.c +@@ -12,6 +12,7 @@ + #include + #include + #include ++#include + + unsigned long riscv_timebase __ro_after_init; + EXPORT_SYMBOL_GPL(riscv_timebase); +@@ -45,4 +46,6 @@ void __init time_init(void) + timer_probe(); + + tick_setup_hrtimer_broadcast(); ++ ++ pv_time_init(); + } diff --git a/arch/riscv/kernel/vdso/hwprobe.c b/arch/riscv/kernel/vdso/hwprobe.c index cadf725ef798..1e926e4b5881 100644 --- a/arch/riscv/kernel/vdso/hwprobe.c @@ -37916,20 +39681,98 @@ index cadf725ef798..1e926e4b5881 100644 + cpus, flags); +} diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c -index 81886fc36ed6..a0d1841c4388 100644 +index 81886fc36ed6..d8f721195008 100644 --- a/arch/riscv/kernel/vector.c +++ b/arch/riscv/kernel/vector.c -@@ -83,7 +83,8 @@ static bool insn_is_vector(u32 insn_buf) - static int riscv_v_thread_zalloc(void) +@@ -21,6 +21,10 @@ + #include + + static bool riscv_v_implicit_uacc = IS_ENABLED(CONFIG_RISCV_ISA_V_DEFAULT_ENABLE); ++static struct kmem_cache *riscv_v_user_cachep; ++#ifdef CONFIG_RISCV_ISA_V_PREEMPTIVE ++static struct kmem_cache *riscv_v_kernel_cachep; ++#endif + + unsigned long riscv_v_vsize __read_mostly; + EXPORT_SYMBOL_GPL(riscv_v_vsize); +@@ -47,6 +51,21 @@ int riscv_v_setup_vsize(void) + return 0; + } + ++void __init riscv_v_setup_ctx_cache(void) ++{ ++ if (!has_vector()) ++ return; ++ ++ riscv_v_user_cachep = kmem_cache_create_usercopy("riscv_vector_ctx", ++ riscv_v_vsize, 16, SLAB_PANIC, ++ 0, riscv_v_vsize, NULL); ++#ifdef CONFIG_RISCV_ISA_V_PREEMPTIVE ++ riscv_v_kernel_cachep = kmem_cache_create("riscv_vector_kctx", ++ riscv_v_vsize, 16, ++ SLAB_PANIC, NULL); ++#endif ++} ++ + static bool insn_is_vector(u32 insn_buf) + { + u32 opcode = insn_buf & __INSN_OPCODE_MASK; +@@ -80,20 +99,38 @@ static bool insn_is_vector(u32 insn_buf) + return false; + } + +-static int riscv_v_thread_zalloc(void) ++static int riscv_v_thread_zalloc(struct kmem_cache *cache, ++ struct __riscv_v_ext_state *ctx) { void *datap; - +- datap = kzalloc(riscv_v_vsize, GFP_KERNEL); + if (!riscv_v_vsize) + return -EINVAL; - datap = kzalloc(riscv_v_vsize, GFP_KERNEL); ++ datap = kmem_cache_zalloc(cache, GFP_KERNEL); if (!datap) return -ENOMEM; -@@ -136,8 +137,11 @@ bool riscv_v_first_use_handler(struct pt_regs *regs) + +- current->thread.vstate.datap = datap; +- memset(¤t->thread.vstate, 0, offsetof(struct __riscv_v_ext_state, +- datap)); ++ ctx->datap = datap; ++ memset(ctx, 0, offsetof(struct __riscv_v_ext_state, datap)); + return 0; + } + ++void riscv_v_thread_alloc(struct task_struct *tsk) ++{ ++#ifdef CONFIG_RISCV_ISA_V_PREEMPTIVE ++ riscv_v_thread_zalloc(riscv_v_kernel_cachep, &tsk->thread.kernel_vstate); ++#endif ++} ++ ++void riscv_v_thread_free(struct task_struct *tsk) ++{ ++ if (tsk->thread.vstate.datap) ++ kmem_cache_free(riscv_v_user_cachep, tsk->thread.vstate.datap); ++#ifdef CONFIG_RISCV_ISA_V_PREEMPTIVE ++ if (tsk->thread.kernel_vstate.datap) ++ kmem_cache_free(riscv_v_kernel_cachep, tsk->thread.kernel_vstate.datap); ++#endif ++} ++ + #define VSTATE_CTRL_GET_CUR(x) ((x) & PR_RISCV_V_VSTATE_CTRL_CUR_MASK) + #define VSTATE_CTRL_GET_NEXT(x) (((x) & PR_RISCV_V_VSTATE_CTRL_NEXT_MASK) >> 2) + #define VSTATE_CTRL_MAKE_NEXT(x) (((x) << 2) & PR_RISCV_V_VSTATE_CTRL_NEXT_MASK) +@@ -122,7 +159,8 @@ static inline void riscv_v_ctrl_set(struct task_struct *tsk, int cur, int nxt, + ctrl |= VSTATE_CTRL_MAKE_NEXT(nxt); + if (inherit) + ctrl |= PR_RISCV_V_VSTATE_CTRL_INHERIT; +- tsk->thread.vstate_ctrl = ctrl; ++ tsk->thread.vstate_ctrl &= ~PR_RISCV_V_VSTATE_CTRL_MASK; ++ tsk->thread.vstate_ctrl |= ctrl; + } + + bool riscv_v_vstate_ctrl_user_allowed(void) +@@ -136,8 +174,11 @@ bool riscv_v_first_use_handler(struct pt_regs *regs) u32 __user *epc = (u32 __user *)regs->epc; u32 insn = (u32)regs->badaddr; @@ -37942,6 +39785,21 @@ index 81886fc36ed6..a0d1841c4388 100644 return false; /* If V has been enabled then it is not the first-use trap */ +@@ -162,12 +203,12 @@ bool riscv_v_first_use_handler(struct pt_regs *regs) + * context where VS has been off. So, try to allocate the user's V + * context and resume execution. + */ +- if (riscv_v_thread_zalloc()) { ++ if (riscv_v_thread_zalloc(riscv_v_user_cachep, ¤t->thread.vstate)) { + force_sig(SIGBUS); + return true; + } + riscv_v_vstate_on(regs); +- riscv_v_vstate_restore(current, regs); ++ riscv_v_vstate_set_restore(current, regs); + return true; + } + diff --git a/arch/riscv/kernel/vendor_extensions.c b/arch/riscv/kernel/vendor_extensions.c new file mode 100644 index 000000000000..aeb8839d2f8a @@ -38037,6 +39895,30 @@ index 000000000000..4d8dfc974f00 + .ext_data_count = ARRAY_SIZE(riscv_isa_vendor_ext_andes), + .ext_data = riscv_isa_vendor_ext_andes, +}; +diff --git a/arch/riscv/kvm/Kconfig b/arch/riscv/kvm/Kconfig +index dfc237d7875b..148e52b516cf 100644 +--- a/arch/riscv/kvm/Kconfig ++++ b/arch/riscv/kvm/Kconfig +@@ -32,6 +32,7 @@ config KVM + select KVM_XFER_TO_GUEST_WORK + select MMU_NOTIFIER + select PREEMPT_NOTIFIERS ++ select SCHED_INFO + help + Support hosting virtualized guest machines. + +diff --git a/arch/riscv/kvm/Makefile b/arch/riscv/kvm/Makefile +index 4c2067fc59fc..c9646521f113 100644 +--- a/arch/riscv/kvm/Makefile ++++ b/arch/riscv/kvm/Makefile +@@ -26,6 +26,7 @@ kvm-$(CONFIG_RISCV_SBI_V01) += vcpu_sbi_v01.o + kvm-y += vcpu_sbi_base.o + kvm-y += vcpu_sbi_replace.o + kvm-y += vcpu_sbi_hsm.o ++kvm-y += vcpu_sbi_sta.o + kvm-y += vcpu_timer.o + kvm-$(CONFIG_RISCV_PMU_SBI) += vcpu_pmu.o vcpu_sbi_pmu.o + kvm-y += aia.o diff --git a/arch/riscv/kvm/aia.c b/arch/riscv/kvm/aia.c index 74bb27440527..596209f1a6ff 100644 --- a/arch/riscv/kvm/aia.c @@ -38201,6 +40083,51 @@ index 44bc324aeeb0..23c0e82b5103 100644 #include #define has_svinval() riscv_has_extension_unlikely(RISCV_ISA_EXT_SVINVAL) +diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c +index 9584d62c96ee..ea0b599608ef 100644 +--- a/arch/riscv/kvm/vcpu.c ++++ b/arch/riscv/kvm/vcpu.c +@@ -83,6 +83,8 @@ static void kvm_riscv_reset_vcpu(struct kvm_vcpu *vcpu) + vcpu->arch.hfence_tail = 0; + memset(vcpu->arch.hfence_queue, 0, sizeof(vcpu->arch.hfence_queue)); + ++ kvm_riscv_vcpu_sbi_sta_reset(vcpu); ++ + /* Reset the guest CSRs for hotplug usecase */ + if (loaded) + kvm_arch_vcpu_load(vcpu, smp_processor_id()); +@@ -143,6 +145,12 @@ int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) + if (rc) + return rc; + ++ /* ++ * Setup SBI extensions ++ * NOTE: This must be the last thing to be initialized. ++ */ ++ kvm_riscv_vcpu_sbi_init(vcpu); ++ + /* Reset VCPU */ + kvm_riscv_reset_vcpu(vcpu); + +@@ -544,6 +552,8 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) + + kvm_riscv_vcpu_aia_load(vcpu, cpu); + ++ kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); ++ + vcpu->cpu = cpu; + } + +@@ -617,6 +627,9 @@ static void kvm_riscv_check_vcpu_requests(struct kvm_vcpu *vcpu) + + if (kvm_check_request(KVM_REQ_HFENCE, vcpu)) + kvm_riscv_hfence_process(vcpu); ++ ++ if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) ++ kvm_riscv_vcpu_record_steal_time(vcpu); + } + } + diff --git a/arch/riscv/kvm/vcpu_fp.c b/arch/riscv/kvm/vcpu_fp.c index 08ba48a395aa..030904d82b58 100644 --- a/arch/riscv/kvm/vcpu_fp.c @@ -38215,7 +40142,7 @@ index 08ba48a395aa..030904d82b58 100644 #ifdef CONFIG_FPU void kvm_riscv_vcpu_fp_reset(struct kvm_vcpu *vcpu) diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c -index d520b25d8561..9e7e755163a9 100644 +index d520b25d8561..6fe35616ad43 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -13,7 +13,7 @@ @@ -38227,6 +40154,673 @@ index d520b25d8561..9e7e755163a9 100644 #include #include +@@ -865,59 +865,66 @@ static inline unsigned long num_isa_ext_regs(const struct kvm_vcpu *vcpu) + return copy_isa_ext_reg_indices(vcpu, NULL);; + } + +-static inline unsigned long num_sbi_ext_regs(void) ++static int copy_sbi_ext_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices) + { +- /* +- * number of KVM_REG_RISCV_SBI_SINGLE + +- * 2 x (number of KVM_REG_RISCV_SBI_MULTI) +- */ +- return KVM_RISCV_SBI_EXT_MAX + 2*(KVM_REG_RISCV_SBI_MULTI_REG_LAST+1); +-} +- +-static int copy_sbi_ext_reg_indices(u64 __user *uindices) +-{ +- int n; ++ unsigned int n = 0; + +- /* copy KVM_REG_RISCV_SBI_SINGLE */ +- n = KVM_RISCV_SBI_EXT_MAX; +- for (int i = 0; i < n; i++) { ++ for (int i = 0; i < KVM_RISCV_SBI_EXT_MAX; i++) { + u64 size = IS_ENABLED(CONFIG_32BIT) ? + KVM_REG_SIZE_U32 : KVM_REG_SIZE_U64; + u64 reg = KVM_REG_RISCV | size | KVM_REG_RISCV_SBI_EXT | + KVM_REG_RISCV_SBI_SINGLE | i; + ++ if (!riscv_vcpu_supports_sbi_ext(vcpu, i)) ++ continue; ++ + if (uindices) { + if (put_user(reg, uindices)) + return -EFAULT; + uindices++; + } ++ ++ n++; + } + +- /* copy KVM_REG_RISCV_SBI_MULTI */ +- n = KVM_REG_RISCV_SBI_MULTI_REG_LAST + 1; +- for (int i = 0; i < n; i++) { +- u64 size = IS_ENABLED(CONFIG_32BIT) ? +- KVM_REG_SIZE_U32 : KVM_REG_SIZE_U64; +- u64 reg = KVM_REG_RISCV | size | KVM_REG_RISCV_SBI_EXT | +- KVM_REG_RISCV_SBI_MULTI_EN | i; ++ return n; ++} + +- if (uindices) { +- if (put_user(reg, uindices)) +- return -EFAULT; +- uindices++; +- } ++static unsigned long num_sbi_ext_regs(struct kvm_vcpu *vcpu) ++{ ++ return copy_sbi_ext_reg_indices(vcpu, NULL); ++} + +- reg = KVM_REG_RISCV | size | KVM_REG_RISCV_SBI_EXT | +- KVM_REG_RISCV_SBI_MULTI_DIS | i; ++static int copy_sbi_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices) ++{ ++ struct kvm_vcpu_sbi_context *scontext = &vcpu->arch.sbi_context; ++ int total = 0; + +- if (uindices) { +- if (put_user(reg, uindices)) +- return -EFAULT; +- uindices++; ++ if (scontext->ext_status[KVM_RISCV_SBI_EXT_STA] == KVM_RISCV_SBI_EXT_STATUS_ENABLED) { ++ u64 size = IS_ENABLED(CONFIG_32BIT) ? KVM_REG_SIZE_U32 : KVM_REG_SIZE_U64; ++ int n = sizeof(struct kvm_riscv_sbi_sta) / sizeof(unsigned long); ++ ++ for (int i = 0; i < n; i++) { ++ u64 reg = KVM_REG_RISCV | size | ++ KVM_REG_RISCV_SBI_STATE | ++ KVM_REG_RISCV_SBI_STA | i; ++ ++ if (uindices) { ++ if (put_user(reg, uindices)) ++ return -EFAULT; ++ uindices++; ++ } + } ++ ++ total += n; + } + +- return num_sbi_ext_regs(); ++ return total; ++} ++ ++static inline unsigned long num_sbi_regs(struct kvm_vcpu *vcpu) ++{ ++ return copy_sbi_reg_indices(vcpu, NULL); + } + + /* +@@ -936,7 +943,8 @@ unsigned long kvm_riscv_vcpu_num_regs(struct kvm_vcpu *vcpu) + res += num_fp_f_regs(vcpu); + res += num_fp_d_regs(vcpu); + res += num_isa_ext_regs(vcpu); +- res += num_sbi_ext_regs(); ++ res += num_sbi_ext_regs(vcpu); ++ res += num_sbi_regs(vcpu); + + return res; + } +@@ -984,9 +992,15 @@ int kvm_riscv_vcpu_copy_reg_indices(struct kvm_vcpu *vcpu, + return ret; + uindices += ret; + +- ret = copy_sbi_ext_reg_indices(uindices); ++ ret = copy_sbi_ext_reg_indices(vcpu, uindices); + if (ret < 0) + return ret; ++ uindices += ret; ++ ++ ret = copy_sbi_reg_indices(vcpu, uindices); ++ if (ret < 0) ++ return ret; ++ uindices += ret; + + return 0; + } +@@ -1009,12 +1023,14 @@ int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcpu, + case KVM_REG_RISCV_FP_D: + return kvm_riscv_vcpu_set_reg_fp(vcpu, reg, + KVM_REG_RISCV_FP_D); ++ case KVM_REG_RISCV_VECTOR: ++ return kvm_riscv_vcpu_set_reg_vector(vcpu, reg); + case KVM_REG_RISCV_ISA_EXT: + return kvm_riscv_vcpu_set_reg_isa_ext(vcpu, reg); + case KVM_REG_RISCV_SBI_EXT: + return kvm_riscv_vcpu_set_reg_sbi_ext(vcpu, reg); +- case KVM_REG_RISCV_VECTOR: +- return kvm_riscv_vcpu_set_reg_vector(vcpu, reg); ++ case KVM_REG_RISCV_SBI_STATE: ++ return kvm_riscv_vcpu_set_reg_sbi(vcpu, reg); + default: + break; + } +@@ -1040,12 +1056,14 @@ int kvm_riscv_vcpu_get_reg(struct kvm_vcpu *vcpu, + case KVM_REG_RISCV_FP_D: + return kvm_riscv_vcpu_get_reg_fp(vcpu, reg, + KVM_REG_RISCV_FP_D); ++ case KVM_REG_RISCV_VECTOR: ++ return kvm_riscv_vcpu_get_reg_vector(vcpu, reg); + case KVM_REG_RISCV_ISA_EXT: + return kvm_riscv_vcpu_get_reg_isa_ext(vcpu, reg); + case KVM_REG_RISCV_SBI_EXT: + return kvm_riscv_vcpu_get_reg_sbi_ext(vcpu, reg); +- case KVM_REG_RISCV_VECTOR: +- return kvm_riscv_vcpu_get_reg_vector(vcpu, reg); ++ case KVM_REG_RISCV_SBI_STATE: ++ return kvm_riscv_vcpu_get_reg_sbi(vcpu, reg); + default: + break; + } +diff --git a/arch/riscv/kvm/vcpu_sbi.c b/arch/riscv/kvm/vcpu_sbi.c +index be43278109f4..7de128be8db9 100644 +--- a/arch/riscv/kvm/vcpu_sbi.c ++++ b/arch/riscv/kvm/vcpu_sbi.c +@@ -66,6 +66,14 @@ static const struct kvm_riscv_sbi_extension_entry sbi_ext[] = { + .ext_idx = KVM_RISCV_SBI_EXT_PMU, + .ext_ptr = &vcpu_sbi_ext_pmu, + }, ++ { ++ .ext_idx = KVM_RISCV_SBI_EXT_DBCN, ++ .ext_ptr = &vcpu_sbi_ext_dbcn, ++ }, ++ { ++ .ext_idx = KVM_RISCV_SBI_EXT_STA, ++ .ext_ptr = &vcpu_sbi_ext_sta, ++ }, + { + .ext_idx = KVM_RISCV_SBI_EXT_EXPERIMENTAL, + .ext_ptr = &vcpu_sbi_ext_experimental, +@@ -76,6 +84,34 @@ static const struct kvm_riscv_sbi_extension_entry sbi_ext[] = { + }, + }; + ++static const struct kvm_riscv_sbi_extension_entry * ++riscv_vcpu_get_sbi_ext(struct kvm_vcpu *vcpu, unsigned long idx) ++{ ++ const struct kvm_riscv_sbi_extension_entry *sext = NULL; ++ ++ if (idx >= KVM_RISCV_SBI_EXT_MAX) ++ return NULL; ++ ++ for (int i = 0; i < ARRAY_SIZE(sbi_ext); i++) { ++ if (sbi_ext[i].ext_idx == idx) { ++ sext = &sbi_ext[i]; ++ break; ++ } ++ } ++ ++ return sext; ++} ++ ++bool riscv_vcpu_supports_sbi_ext(struct kvm_vcpu *vcpu, int idx) ++{ ++ struct kvm_vcpu_sbi_context *scontext = &vcpu->arch.sbi_context; ++ const struct kvm_riscv_sbi_extension_entry *sext; ++ ++ sext = riscv_vcpu_get_sbi_ext(vcpu, idx); ++ ++ return sext && scontext->ext_status[sext->ext_idx] != KVM_RISCV_SBI_EXT_STATUS_UNAVAILABLE; ++} ++ + void kvm_riscv_vcpu_sbi_forward(struct kvm_vcpu *vcpu, struct kvm_run *run) + { + struct kvm_cpu_context *cp = &vcpu->arch.guest_context; +@@ -139,34 +175,19 @@ static int riscv_vcpu_set_sbi_ext_single(struct kvm_vcpu *vcpu, + unsigned long reg_num, + unsigned long reg_val) + { +- unsigned long i; +- const struct kvm_riscv_sbi_extension_entry *sext = NULL; + struct kvm_vcpu_sbi_context *scontext = &vcpu->arch.sbi_context; +- +- if (reg_num >= KVM_RISCV_SBI_EXT_MAX) +- return -ENOENT; ++ const struct kvm_riscv_sbi_extension_entry *sext; + + if (reg_val != 1 && reg_val != 0) + return -EINVAL; + +- for (i = 0; i < ARRAY_SIZE(sbi_ext); i++) { +- if (sbi_ext[i].ext_idx == reg_num) { +- sext = &sbi_ext[i]; +- break; +- } +- } +- if (!sext) ++ sext = riscv_vcpu_get_sbi_ext(vcpu, reg_num); ++ if (!sext || scontext->ext_status[sext->ext_idx] == KVM_RISCV_SBI_EXT_STATUS_UNAVAILABLE) + return -ENOENT; + +- /* +- * We can't set the extension status to available here, since it may +- * have a probe() function which needs to confirm availability first, +- * but it may be too early to call that here. We can set the status to +- * unavailable, though. +- */ +- if (!reg_val) +- scontext->ext_status[sext->ext_idx] = +- KVM_RISCV_SBI_EXT_UNAVAILABLE; ++ scontext->ext_status[sext->ext_idx] = (reg_val) ? ++ KVM_RISCV_SBI_EXT_STATUS_ENABLED : ++ KVM_RISCV_SBI_EXT_STATUS_DISABLED; + + return 0; + } +@@ -175,31 +196,15 @@ static int riscv_vcpu_get_sbi_ext_single(struct kvm_vcpu *vcpu, + unsigned long reg_num, + unsigned long *reg_val) + { +- unsigned long i; +- const struct kvm_riscv_sbi_extension_entry *sext = NULL; + struct kvm_vcpu_sbi_context *scontext = &vcpu->arch.sbi_context; ++ const struct kvm_riscv_sbi_extension_entry *sext; + +- if (reg_num >= KVM_RISCV_SBI_EXT_MAX) ++ sext = riscv_vcpu_get_sbi_ext(vcpu, reg_num); ++ if (!sext || scontext->ext_status[sext->ext_idx] == KVM_RISCV_SBI_EXT_STATUS_UNAVAILABLE) + return -ENOENT; + +- for (i = 0; i < ARRAY_SIZE(sbi_ext); i++) { +- if (sbi_ext[i].ext_idx == reg_num) { +- sext = &sbi_ext[i]; +- break; +- } +- } +- if (!sext) +- return -ENOENT; +- +- /* +- * If the extension status is still uninitialized, then we should probe +- * to determine if it's available, but it may be too early to do that +- * here. The best we can do is report that the extension has not been +- * disabled, i.e. we return 1 when the extension is available and also +- * when it only may be available. +- */ +- *reg_val = scontext->ext_status[sext->ext_idx] != +- KVM_RISCV_SBI_EXT_UNAVAILABLE; ++ *reg_val = scontext->ext_status[sext->ext_idx] == ++ KVM_RISCV_SBI_EXT_STATUS_ENABLED; + + return 0; + } +@@ -323,6 +328,69 @@ int kvm_riscv_vcpu_get_reg_sbi_ext(struct kvm_vcpu *vcpu, + return 0; + } + ++int kvm_riscv_vcpu_set_reg_sbi(struct kvm_vcpu *vcpu, ++ const struct kvm_one_reg *reg) ++{ ++ unsigned long __user *uaddr = ++ (unsigned long __user *)(unsigned long)reg->addr; ++ unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | ++ KVM_REG_SIZE_MASK | ++ KVM_REG_RISCV_SBI_STATE); ++ unsigned long reg_subtype, reg_val; ++ ++ if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) ++ return -EINVAL; ++ ++ if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id))) ++ return -EFAULT; ++ ++ reg_subtype = reg_num & KVM_REG_RISCV_SUBTYPE_MASK; ++ reg_num &= ~KVM_REG_RISCV_SUBTYPE_MASK; ++ ++ switch (reg_subtype) { ++ case KVM_REG_RISCV_SBI_STA: ++ return kvm_riscv_vcpu_set_reg_sbi_sta(vcpu, reg_num, reg_val); ++ default: ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++int kvm_riscv_vcpu_get_reg_sbi(struct kvm_vcpu *vcpu, ++ const struct kvm_one_reg *reg) ++{ ++ unsigned long __user *uaddr = ++ (unsigned long __user *)(unsigned long)reg->addr; ++ unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | ++ KVM_REG_SIZE_MASK | ++ KVM_REG_RISCV_SBI_STATE); ++ unsigned long reg_subtype, reg_val; ++ int ret; ++ ++ if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) ++ return -EINVAL; ++ ++ reg_subtype = reg_num & KVM_REG_RISCV_SUBTYPE_MASK; ++ reg_num &= ~KVM_REG_RISCV_SUBTYPE_MASK; ++ ++ switch (reg_subtype) { ++ case KVM_REG_RISCV_SBI_STA: ++ ret = kvm_riscv_vcpu_get_reg_sbi_sta(vcpu, reg_num, ®_val); ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ if (ret) ++ return ret; ++ ++ if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id))) ++ return -EFAULT; ++ ++ return 0; ++} ++ + const struct kvm_vcpu_sbi_extension *kvm_vcpu_sbi_find_ext( + struct kvm_vcpu *vcpu, unsigned long extid) + { +@@ -338,20 +406,10 @@ const struct kvm_vcpu_sbi_extension *kvm_vcpu_sbi_find_ext( + if (ext->extid_start <= extid && ext->extid_end >= extid) { + if (entry->ext_idx >= KVM_RISCV_SBI_EXT_MAX || + scontext->ext_status[entry->ext_idx] == +- KVM_RISCV_SBI_EXT_AVAILABLE) ++ KVM_RISCV_SBI_EXT_STATUS_ENABLED) + return ext; +- if (scontext->ext_status[entry->ext_idx] == +- KVM_RISCV_SBI_EXT_UNAVAILABLE) +- return NULL; +- if (ext->probe && !ext->probe(vcpu)) { +- scontext->ext_status[entry->ext_idx] = +- KVM_RISCV_SBI_EXT_UNAVAILABLE; +- return NULL; +- } + +- scontext->ext_status[entry->ext_idx] = +- KVM_RISCV_SBI_EXT_AVAILABLE; +- return ext; ++ return NULL; + } + } + +@@ -422,3 +480,26 @@ int kvm_riscv_vcpu_sbi_ecall(struct kvm_vcpu *vcpu, struct kvm_run *run) + + return ret; + } ++ ++void kvm_riscv_vcpu_sbi_init(struct kvm_vcpu *vcpu) ++{ ++ struct kvm_vcpu_sbi_context *scontext = &vcpu->arch.sbi_context; ++ const struct kvm_riscv_sbi_extension_entry *entry; ++ const struct kvm_vcpu_sbi_extension *ext; ++ int i; ++ ++ for (i = 0; i < ARRAY_SIZE(sbi_ext); i++) { ++ entry = &sbi_ext[i]; ++ ext = entry->ext_ptr; ++ ++ if (ext->probe && !ext->probe(vcpu)) { ++ scontext->ext_status[entry->ext_idx] = ++ KVM_RISCV_SBI_EXT_STATUS_UNAVAILABLE; ++ continue; ++ } ++ ++ scontext->ext_status[entry->ext_idx] = ext->default_disabled ? ++ KVM_RISCV_SBI_EXT_STATUS_DISABLED : ++ KVM_RISCV_SBI_EXT_STATUS_ENABLED; ++ } ++} +diff --git a/arch/riscv/kvm/vcpu_sbi_replace.c b/arch/riscv/kvm/vcpu_sbi_replace.c +index 87ec68ed52d7..5fbf3f94f1e8 100644 +--- a/arch/riscv/kvm/vcpu_sbi_replace.c ++++ b/arch/riscv/kvm/vcpu_sbi_replace.c +@@ -184,3 +184,35 @@ const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_srst = { + .extid_end = SBI_EXT_SRST, + .handler = kvm_sbi_ext_srst_handler, + }; ++ ++static int kvm_sbi_ext_dbcn_handler(struct kvm_vcpu *vcpu, ++ struct kvm_run *run, ++ struct kvm_vcpu_sbi_return *retdata) ++{ ++ struct kvm_cpu_context *cp = &vcpu->arch.guest_context; ++ unsigned long funcid = cp->a6; ++ ++ switch (funcid) { ++ case SBI_EXT_DBCN_CONSOLE_WRITE: ++ case SBI_EXT_DBCN_CONSOLE_READ: ++ case SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: ++ /* ++ * The SBI debug console functions are unconditionally ++ * forwarded to the userspace. ++ */ ++ kvm_riscv_vcpu_sbi_forward(vcpu, run); ++ retdata->uexit = true; ++ break; ++ default: ++ retdata->err_val = SBI_ERR_NOT_SUPPORTED; ++ } ++ ++ return 0; ++} ++ ++const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_dbcn = { ++ .extid_start = SBI_EXT_DBCN, ++ .extid_end = SBI_EXT_DBCN, ++ .default_disabled = true, ++ .handler = kvm_sbi_ext_dbcn_handler, ++}; +diff --git a/arch/riscv/kvm/vcpu_sbi_sta.c b/arch/riscv/kvm/vcpu_sbi_sta.c +new file mode 100644 +index 000000000000..01f09fe8c3b0 +--- /dev/null ++++ b/arch/riscv/kvm/vcpu_sbi_sta.c +@@ -0,0 +1,208 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2023 Ventana Micro Systems Inc. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++void kvm_riscv_vcpu_sbi_sta_reset(struct kvm_vcpu *vcpu) ++{ ++ vcpu->arch.sta.shmem = INVALID_GPA; ++ vcpu->arch.sta.last_steal = 0; ++} ++ ++void kvm_riscv_vcpu_record_steal_time(struct kvm_vcpu *vcpu) ++{ ++ gpa_t shmem = vcpu->arch.sta.shmem; ++ u64 last_steal = vcpu->arch.sta.last_steal; ++ u32 *sequence_ptr, sequence; ++ u64 *steal_ptr, steal; ++ unsigned long hva; ++ gfn_t gfn; ++ ++ if (shmem == INVALID_GPA) ++ return; ++ ++ /* ++ * shmem is 64-byte aligned (see the enforcement in ++ * kvm_sbi_sta_steal_time_set_shmem()) and the size of sbi_sta_struct ++ * is 64 bytes, so we know all its offsets are in the same page. ++ */ ++ gfn = shmem >> PAGE_SHIFT; ++ hva = kvm_vcpu_gfn_to_hva(vcpu, gfn); ++ ++ if (WARN_ON(kvm_is_error_hva(hva))) { ++ vcpu->arch.sta.shmem = INVALID_GPA; ++ return; ++ } ++ ++ sequence_ptr = (u32 *)(hva + offset_in_page(shmem) + ++ offsetof(struct sbi_sta_struct, sequence)); ++ steal_ptr = (u64 *)(hva + offset_in_page(shmem) + ++ offsetof(struct sbi_sta_struct, steal)); ++ ++ if (WARN_ON(get_user(sequence, sequence_ptr))) ++ return; ++ ++ sequence = le32_to_cpu(sequence); ++ sequence += 1; ++ ++ if (WARN_ON(put_user(cpu_to_le32(sequence), sequence_ptr))) ++ return; ++ ++ if (!WARN_ON(get_user(steal, steal_ptr))) { ++ steal = le64_to_cpu(steal); ++ vcpu->arch.sta.last_steal = READ_ONCE(current->sched_info.run_delay); ++ steal += vcpu->arch.sta.last_steal - last_steal; ++ WARN_ON(put_user(cpu_to_le64(steal), steal_ptr)); ++ } ++ ++ sequence += 1; ++ WARN_ON(put_user(cpu_to_le32(sequence), sequence_ptr)); ++ ++ kvm_vcpu_mark_page_dirty(vcpu, gfn); ++} ++ ++static int kvm_sbi_sta_steal_time_set_shmem(struct kvm_vcpu *vcpu) ++{ ++ struct kvm_cpu_context *cp = &vcpu->arch.guest_context; ++ unsigned long shmem_phys_lo = cp->a0; ++ unsigned long shmem_phys_hi = cp->a1; ++ u32 flags = cp->a2; ++ struct sbi_sta_struct zero_sta = {0}; ++ unsigned long hva; ++ bool writable; ++ gpa_t shmem; ++ int ret; ++ ++ if (flags != 0) ++ return SBI_ERR_INVALID_PARAM; ++ ++ if (shmem_phys_lo == SBI_STA_SHMEM_DISABLE && ++ shmem_phys_hi == SBI_STA_SHMEM_DISABLE) { ++ vcpu->arch.sta.shmem = INVALID_GPA; ++ return 0; ++ } ++ ++ if (shmem_phys_lo & (SZ_64 - 1)) ++ return SBI_ERR_INVALID_PARAM; ++ ++ shmem = shmem_phys_lo; ++ ++ if (shmem_phys_hi != 0) { ++ if (IS_ENABLED(CONFIG_32BIT)) ++ shmem |= ((gpa_t)shmem_phys_hi << 32); ++ else ++ return SBI_ERR_INVALID_ADDRESS; ++ } ++ ++ hva = kvm_vcpu_gfn_to_hva_prot(vcpu, shmem >> PAGE_SHIFT, &writable); ++ if (kvm_is_error_hva(hva) || !writable) ++ return SBI_ERR_INVALID_ADDRESS; ++ ++ ret = kvm_vcpu_write_guest(vcpu, shmem, &zero_sta, sizeof(zero_sta)); ++ if (ret) ++ return SBI_ERR_FAILURE; ++ ++ vcpu->arch.sta.shmem = shmem; ++ vcpu->arch.sta.last_steal = current->sched_info.run_delay; ++ ++ return 0; ++} ++ ++static int kvm_sbi_ext_sta_handler(struct kvm_vcpu *vcpu, struct kvm_run *run, ++ struct kvm_vcpu_sbi_return *retdata) ++{ ++ struct kvm_cpu_context *cp = &vcpu->arch.guest_context; ++ unsigned long funcid = cp->a6; ++ int ret; ++ ++ switch (funcid) { ++ case SBI_EXT_STA_STEAL_TIME_SET_SHMEM: ++ ret = kvm_sbi_sta_steal_time_set_shmem(vcpu); ++ break; ++ default: ++ ret = SBI_ERR_NOT_SUPPORTED; ++ break; ++ } ++ ++ retdata->err_val = ret; ++ ++ return 0; ++} ++ ++static unsigned long kvm_sbi_ext_sta_probe(struct kvm_vcpu *vcpu) ++{ ++ return !!sched_info_on(); ++} ++ ++const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_sta = { ++ .extid_start = SBI_EXT_STA, ++ .extid_end = SBI_EXT_STA, ++ .handler = kvm_sbi_ext_sta_handler, ++ .probe = kvm_sbi_ext_sta_probe, ++}; ++ ++int kvm_riscv_vcpu_get_reg_sbi_sta(struct kvm_vcpu *vcpu, ++ unsigned long reg_num, ++ unsigned long *reg_val) ++{ ++ switch (reg_num) { ++ case KVM_REG_RISCV_SBI_STA_REG(shmem_lo): ++ *reg_val = (unsigned long)vcpu->arch.sta.shmem; ++ break; ++ case KVM_REG_RISCV_SBI_STA_REG(shmem_hi): ++ if (IS_ENABLED(CONFIG_32BIT)) ++ *reg_val = upper_32_bits(vcpu->arch.sta.shmem); ++ else ++ *reg_val = 0; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++int kvm_riscv_vcpu_set_reg_sbi_sta(struct kvm_vcpu *vcpu, ++ unsigned long reg_num, ++ unsigned long reg_val) ++{ ++ switch (reg_num) { ++ case KVM_REG_RISCV_SBI_STA_REG(shmem_lo): ++ if (IS_ENABLED(CONFIG_32BIT)) { ++ gpa_t hi = upper_32_bits(vcpu->arch.sta.shmem); ++ ++ vcpu->arch.sta.shmem = reg_val; ++ vcpu->arch.sta.shmem |= hi << 32; ++ } else { ++ vcpu->arch.sta.shmem = reg_val; ++ } ++ break; ++ case KVM_REG_RISCV_SBI_STA_REG(shmem_hi): ++ if (IS_ENABLED(CONFIG_32BIT)) { ++ gpa_t lo = lower_32_bits(vcpu->arch.sta.shmem); ++ ++ vcpu->arch.sta.shmem = ((gpa_t)reg_val << 32); ++ vcpu->arch.sta.shmem |= lo; ++ } else if (reg_val != 0) { ++ return -EINVAL; ++ } ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ return 0; ++} diff --git a/arch/riscv/kvm/vcpu_vector.c b/arch/riscv/kvm/vcpu_vector.c index b430cbb69521..b339a2682f25 100644 --- a/arch/riscv/kvm/vcpu_vector.c @@ -38241,16 +40835,25 @@ index b430cbb69521..b339a2682f25 100644 #include diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile -index 26cb2502ecf8..183bf2097d57 100644 +index 26cb2502ecf8..4157f446d5bc 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile -@@ -9,5 +9,6 @@ lib-y += strncmp.o - lib-$(CONFIG_MMU) += uaccess.o +@@ -6,8 +6,14 @@ lib-y += memmove.o + lib-y += strcmp.o + lib-y += strlen.o + lib-y += strncmp.o +-lib-$(CONFIG_MMU) += uaccess.o ++ifeq ($(CONFIG_MMU), y) ++lib-y += uaccess.o ++lib-$(CONFIG_RISCV_ISA_V) += uaccess_vector.o ++endif lib-$(CONFIG_64BIT) += tishift.o lib-$(CONFIG_RISCV_ISA_ZICBOZ) += clear_page.o +lib-$(CONFIG_RISCV_ISA_ZBC) += crc32.o obj-$(CONFIG_FUNCTION_ERROR_INJECTION) += error-inject.o ++lib-$(CONFIG_RISCV_ISA_V) += xor.o ++lib-$(CONFIG_RISCV_ISA_V) += riscv_v_helpers.o diff --git a/arch/riscv/lib/crc32.c b/arch/riscv/lib/crc32.c new file mode 100644 index 000000000000..d7dc599af3ef @@ -38551,6 +41154,393 @@ index 000000000000..d7dc599af3ef +legacy: + return crc32_be_base(crc, p, len); +} +diff --git a/arch/riscv/lib/memmove.S b/arch/riscv/lib/memmove.S +index 21d0a171c0ba..cb3e2e7ef0ba 100644 +--- a/arch/riscv/lib/memmove.S ++++ b/arch/riscv/lib/memmove.S +@@ -25,8 +25,8 @@ SYM_FUNC_START(__memmove) + */ + + /* Return if nothing to do */ +- beq a0, a1, return_from_memmove +- beqz a2, return_from_memmove ++ beq a0, a1, .Lreturn_from_memmove ++ beqz a2, .Lreturn_from_memmove + + /* + * Register Uses +@@ -59,7 +59,7 @@ SYM_FUNC_START(__memmove) + * small enough not to bother. + */ + andi t0, a2, -(2 * SZREG) +- beqz t0, byte_copy ++ beqz t0, .Lbyte_copy + + /* + * Now solve for t5 and t6. +@@ -86,14 +86,14 @@ SYM_FUNC_START(__memmove) + */ + xor t0, a0, a1 + andi t1, t0, (SZREG - 1) +- beqz t1, coaligned_copy ++ beqz t1, .Lcoaligned_copy + /* Fall through to misaligned fixup copy */ + +-misaligned_fixup_copy: +- bltu a1, a0, misaligned_fixup_copy_reverse ++.Lmisaligned_fixup_copy: ++ bltu a1, a0, .Lmisaligned_fixup_copy_reverse + +-misaligned_fixup_copy_forward: +- jal t0, byte_copy_until_aligned_forward ++.Lmisaligned_fixup_copy_forward: ++ jal t0, .Lbyte_copy_until_aligned_forward + + andi a5, a1, (SZREG - 1) /* Find the alignment offset of src (a1) */ + slli a6, a5, 3 /* Multiply by 8 to convert that to bits to shift */ +@@ -152,10 +152,10 @@ misaligned_fixup_copy_forward: + mv t3, t6 /* Fix the dest pointer in case the loop was broken */ + + add a1, t3, a5 /* Restore the src pointer */ +- j byte_copy_forward /* Copy any remaining bytes */ ++ j .Lbyte_copy_forward /* Copy any remaining bytes */ + +-misaligned_fixup_copy_reverse: +- jal t0, byte_copy_until_aligned_reverse ++.Lmisaligned_fixup_copy_reverse: ++ jal t0, .Lbyte_copy_until_aligned_reverse + + andi a5, a4, (SZREG - 1) /* Find the alignment offset of src (a4) */ + slli a6, a5, 3 /* Multiply by 8 to convert that to bits to shift */ +@@ -214,18 +214,18 @@ misaligned_fixup_copy_reverse: + mv t4, t5 /* Fix the dest pointer in case the loop was broken */ + + add a4, t4, a5 /* Restore the src pointer */ +- j byte_copy_reverse /* Copy any remaining bytes */ ++ j .Lbyte_copy_reverse /* Copy any remaining bytes */ + + /* + * Simple copy loops for SZREG co-aligned memory locations. + * These also make calls to do byte copies for any unaligned + * data at their terminations. + */ +-coaligned_copy: +- bltu a1, a0, coaligned_copy_reverse ++.Lcoaligned_copy: ++ bltu a1, a0, .Lcoaligned_copy_reverse + +-coaligned_copy_forward: +- jal t0, byte_copy_until_aligned_forward ++.Lcoaligned_copy_forward: ++ jal t0, .Lbyte_copy_until_aligned_forward + + 1: + REG_L t1, ( 0 * SZREG)(a1) +@@ -234,10 +234,10 @@ coaligned_copy_forward: + REG_S t1, (-1 * SZREG)(t3) + bne t3, t6, 1b + +- j byte_copy_forward /* Copy any remaining bytes */ ++ j .Lbyte_copy_forward /* Copy any remaining bytes */ + +-coaligned_copy_reverse: +- jal t0, byte_copy_until_aligned_reverse ++.Lcoaligned_copy_reverse: ++ jal t0, .Lbyte_copy_until_aligned_reverse + + 1: + REG_L t1, (-1 * SZREG)(a4) +@@ -246,7 +246,7 @@ coaligned_copy_reverse: + REG_S t1, ( 0 * SZREG)(t4) + bne t4, t5, 1b + +- j byte_copy_reverse /* Copy any remaining bytes */ ++ j .Lbyte_copy_reverse /* Copy any remaining bytes */ + + /* + * These are basically sub-functions within the function. They +@@ -257,7 +257,7 @@ coaligned_copy_reverse: + * up from where they were left and we avoid code duplication + * without any overhead except the call in and return jumps. + */ +-byte_copy_until_aligned_forward: ++.Lbyte_copy_until_aligned_forward: + beq t3, t5, 2f + 1: + lb t1, 0(a1) +@@ -268,7 +268,7 @@ byte_copy_until_aligned_forward: + 2: + jalr zero, 0x0(t0) /* Return to multibyte copy loop */ + +-byte_copy_until_aligned_reverse: ++.Lbyte_copy_until_aligned_reverse: + beq t4, t6, 2f + 1: + lb t1, -1(a4) +@@ -284,10 +284,10 @@ byte_copy_until_aligned_reverse: + * These will byte copy until they reach the end of data to copy. + * At that point, they will call to return from memmove. + */ +-byte_copy: +- bltu a1, a0, byte_copy_reverse ++.Lbyte_copy: ++ bltu a1, a0, .Lbyte_copy_reverse + +-byte_copy_forward: ++.Lbyte_copy_forward: + beq t3, t4, 2f + 1: + lb t1, 0(a1) +@@ -298,7 +298,7 @@ byte_copy_forward: + 2: + ret + +-byte_copy_reverse: ++.Lbyte_copy_reverse: + beq t4, t3, 2f + 1: + lb t1, -1(a4) +@@ -308,7 +308,7 @@ byte_copy_reverse: + bne t4, t3, 1b + 2: + +-return_from_memmove: ++.Lreturn_from_memmove: + ret + + SYM_FUNC_END(__memmove) +diff --git a/arch/riscv/lib/riscv_v_helpers.c b/arch/riscv/lib/riscv_v_helpers.c +new file mode 100644 +index 000000000000..be38a93cedae +--- /dev/null ++++ b/arch/riscv/lib/riscv_v_helpers.c +@@ -0,0 +1,45 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later ++/* ++ * Copyright (C) 2023 SiFive ++ * Author: Andy Chiu ++ */ ++#include ++#include ++ ++#include ++#include ++ ++#ifdef CONFIG_MMU ++#include ++#endif ++ ++#ifdef CONFIG_MMU ++size_t riscv_v_usercopy_threshold = CONFIG_RISCV_ISA_V_UCOPY_THRESHOLD; ++int __asm_vector_usercopy(void *dst, void *src, size_t n); ++int fallback_scalar_usercopy(void *dst, void *src, size_t n); ++asmlinkage int enter_vector_usercopy(void *dst, void *src, size_t n) ++{ ++ size_t remain, copied; ++ ++ /* skip has_vector() check because it has been done by the asm */ ++ if (!may_use_simd()) ++ goto fallback; ++ ++ kernel_vector_begin(); ++ remain = __asm_vector_usercopy(dst, src, n); ++ kernel_vector_end(); ++ ++ if (remain) { ++ copied = n - remain; ++ dst += copied; ++ src += copied; ++ n = remain; ++ goto fallback; ++ } ++ ++ return remain; ++ ++fallback: ++ return fallback_scalar_usercopy(dst, src, n); ++} ++#endif +diff --git a/arch/riscv/lib/uaccess.S b/arch/riscv/lib/uaccess.S +index 3ab438f30d13..a1e4a3c42925 100644 +--- a/arch/riscv/lib/uaccess.S ++++ b/arch/riscv/lib/uaccess.S +@@ -3,6 +3,8 @@ + #include + #include + #include ++#include ++#include + + .macro fixup op reg addr lbl + 100: +@@ -11,6 +13,13 @@ + .endm + + SYM_FUNC_START(__asm_copy_to_user) ++#ifdef CONFIG_RISCV_ISA_V ++ ALTERNATIVE("j fallback_scalar_usercopy", "nop", 0, RISCV_ISA_EXT_v, CONFIG_RISCV_ISA_V) ++ REG_L t0, riscv_v_usercopy_threshold ++ bltu a2, t0, fallback_scalar_usercopy ++ tail enter_vector_usercopy ++#endif ++SYM_FUNC_START(fallback_scalar_usercopy) + + /* Enable access to user memory */ + li t6, SR_SUM +@@ -181,6 +190,7 @@ SYM_FUNC_START(__asm_copy_to_user) + sub a0, t5, a0 + ret + SYM_FUNC_END(__asm_copy_to_user) ++SYM_FUNC_END(fallback_scalar_usercopy) + EXPORT_SYMBOL(__asm_copy_to_user) + SYM_FUNC_ALIAS(__asm_copy_from_user, __asm_copy_to_user) + EXPORT_SYMBOL(__asm_copy_from_user) +diff --git a/arch/riscv/lib/uaccess_vector.S b/arch/riscv/lib/uaccess_vector.S +new file mode 100644 +index 000000000000..51ab5588e9ff +--- /dev/null ++++ b/arch/riscv/lib/uaccess_vector.S +@@ -0,0 +1,53 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#define pDst a0 ++#define pSrc a1 ++#define iNum a2 ++ ++#define iVL a3 ++ ++#define ELEM_LMUL_SETTING m8 ++#define vData v0 ++ ++ .macro fixup op reg addr lbl ++100: ++ \op \reg, \addr ++ _asm_extable 100b, \lbl ++ .endm ++ ++SYM_FUNC_START(__asm_vector_usercopy) ++ /* Enable access to user memory */ ++ li t6, SR_SUM ++ csrs CSR_STATUS, t6 ++ ++loop: ++ vsetvli iVL, iNum, e8, ELEM_LMUL_SETTING, ta, ma ++ fixup vle8.v vData, (pSrc), 10f ++ sub iNum, iNum, iVL ++ add pSrc, pSrc, iVL ++ fixup vse8.v vData, (pDst), 11f ++ add pDst, pDst, iVL ++ bnez iNum, loop ++ ++ /* Exception fixup for vector load is shared with normal exit */ ++10: ++ /* Disable access to user memory */ ++ csrc CSR_STATUS, t6 ++ mv a0, iNum ++ ret ++ ++ /* Exception fixup code for vector store. */ ++11: ++ /* Undo the subtraction after vle8.v */ ++ add iNum, iNum, iVL ++ /* Make sure the scalar fallback skip already processed bytes */ ++ csrr t2, CSR_VSTART ++ sub iNum, iNum, t2 ++ j 10b ++SYM_FUNC_END(__asm_vector_usercopy) +diff --git a/arch/riscv/lib/xor.S b/arch/riscv/lib/xor.S +new file mode 100644 +index 000000000000..b28f2430e52f +--- /dev/null ++++ b/arch/riscv/lib/xor.S +@@ -0,0 +1,81 @@ ++/* SPDX-License-Identifier: GPL-2.0-or-later */ ++/* ++ * Copyright (C) 2021 SiFive ++ */ ++#include ++#include ++#include ++ ++SYM_FUNC_START(xor_regs_2_) ++ vsetvli a3, a0, e8, m8, ta, ma ++ vle8.v v0, (a1) ++ vle8.v v8, (a2) ++ sub a0, a0, a3 ++ vxor.vv v16, v0, v8 ++ add a2, a2, a3 ++ vse8.v v16, (a1) ++ add a1, a1, a3 ++ bnez a0, xor_regs_2_ ++ ret ++SYM_FUNC_END(xor_regs_2_) ++EXPORT_SYMBOL(xor_regs_2_) ++ ++SYM_FUNC_START(xor_regs_3_) ++ vsetvli a4, a0, e8, m8, ta, ma ++ vle8.v v0, (a1) ++ vle8.v v8, (a2) ++ sub a0, a0, a4 ++ vxor.vv v0, v0, v8 ++ vle8.v v16, (a3) ++ add a2, a2, a4 ++ vxor.vv v16, v0, v16 ++ add a3, a3, a4 ++ vse8.v v16, (a1) ++ add a1, a1, a4 ++ bnez a0, xor_regs_3_ ++ ret ++SYM_FUNC_END(xor_regs_3_) ++EXPORT_SYMBOL(xor_regs_3_) ++ ++SYM_FUNC_START(xor_regs_4_) ++ vsetvli a5, a0, e8, m8, ta, ma ++ vle8.v v0, (a1) ++ vle8.v v8, (a2) ++ sub a0, a0, a5 ++ vxor.vv v0, v0, v8 ++ vle8.v v16, (a3) ++ add a2, a2, a5 ++ vxor.vv v0, v0, v16 ++ vle8.v v24, (a4) ++ add a3, a3, a5 ++ vxor.vv v16, v0, v24 ++ add a4, a4, a5 ++ vse8.v v16, (a1) ++ add a1, a1, a5 ++ bnez a0, xor_regs_4_ ++ ret ++SYM_FUNC_END(xor_regs_4_) ++EXPORT_SYMBOL(xor_regs_4_) ++ ++SYM_FUNC_START(xor_regs_5_) ++ vsetvli a6, a0, e8, m8, ta, ma ++ vle8.v v0, (a1) ++ vle8.v v8, (a2) ++ sub a0, a0, a6 ++ vxor.vv v0, v0, v8 ++ vle8.v v16, (a3) ++ add a2, a2, a6 ++ vxor.vv v0, v0, v16 ++ vle8.v v24, (a4) ++ add a3, a3, a6 ++ vxor.vv v0, v0, v24 ++ vle8.v v8, (a5) ++ add a4, a4, a6 ++ vxor.vv v16, v0, v8 ++ add a5, a5, a6 ++ vse8.v v16, (a1) ++ add a1, a1, a6 ++ bnez a0, xor_regs_5_ ++ ret ++SYM_FUNC_END(xor_regs_5_) ++EXPORT_SYMBOL(xor_regs_5_) diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c index f1387272a551..55a34f2020a8 100644 --- a/arch/riscv/mm/cacheflush.c @@ -38721,7 +41711,7 @@ index 324e8cd9b502..a9f4af9f7f3f 100644 local_flush_tlb_page_asid(start, asid); start += stride; diff --git a/arch/sw_64/Kconfig b/arch/sw_64/Kconfig -index 7af20faf9f43..2224afa91cc8 100644 +index 75b3cf116dc8..7a67b60074fb 100644 --- a/arch/sw_64/Kconfig +++ b/arch/sw_64/Kconfig @@ -430,7 +430,6 @@ source "kernel/livepatch/Kconfig" @@ -38760,7 +41750,7 @@ index 8e1ef5345b7a..a67bb8f982bd 100644 paravirt_tlb_remove_table(tlb, virt_to_page(pud)); } diff --git a/drivers/acpi/Kconfig b/drivers/acpi/Kconfig -index c4746869d67b..34dfe1430d75 100644 +index e66874d4c3e3..535df8bb14f4 100644 --- a/drivers/acpi/Kconfig +++ b/drivers/acpi/Kconfig @@ -281,7 +281,7 @@ config ACPI_CPPC_LIB @@ -40732,10 +43722,10 @@ index 2ea14648a661..e84106a4ef59 100644 acpi_get_physical_device_location(acpi_handle handle, struct acpi_pld_info **pld) { diff --git a/drivers/base/arch_numa.c b/drivers/base/arch_numa.c -index 96281de7010d..7f3ea78722fa 100644 +index 0e615ed23635..f1918652ddec 100644 --- a/drivers/base/arch_numa.c +++ b/drivers/base/arch_numa.c -@@ -530,7 +530,7 @@ static int __init arch_acpi_numa_init(void) +@@ -535,7 +535,7 @@ static int __init arch_acpi_numa_init(void) ret = acpi_numa_init(); if (ret) { @@ -377789,25 +380779,25 @@ index 000000000000..cfc44b7901ae +MODULE_DESCRIPTION("Spacemit P1 Power Key driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig -index 56eafa478c34..9b2fa5a6ae29 100644 +index 567f15f5b842..30dc1c332a7d 100644 --- a/drivers/iommu/Kconfig +++ b/drivers/iommu/Kconfig -@@ -196,6 +196,7 @@ source "drivers/iommu/amd/Kconfig" - source "drivers/iommu/intel/Kconfig" +@@ -205,6 +205,7 @@ source "drivers/iommu/intel/Kconfig" source "drivers/iommu/iommufd/Kconfig" source "drivers/iommu/sw64/Kconfig" + source "drivers/iommu/hisilicon/Kconfig" +source "drivers/iommu/riscv/Kconfig" config IRQ_REMAP bool "Support for Interrupt Remapping" diff --git a/drivers/iommu/Makefile b/drivers/iommu/Makefile -index e3ecb2040808..6fb28db17118 100644 +index 99b8b0d856d8..4189cd3f6015 100644 --- a/drivers/iommu/Makefile +++ b/drivers/iommu/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 --obj-y += amd/ intel/ arm/ iommufd/ sw64/ -+obj-y += amd/ intel/ arm/ iommufd/ sw64/ riscv/ +-obj-y += amd/ intel/ arm/ iommufd/ sw64/ hisilicon/ ++obj-y += amd/ intel/ arm/ iommufd/ sw64/ hisilicon/ riscv/ obj-$(CONFIG_IOMMU_API) += iommu.o obj-$(CONFIG_IOMMU_API) += iommu-traces.o obj-$(CONFIG_IOMMU_API) += iommu-sysfs.o @@ -377826,10 +380816,10 @@ index ef3ee95706da..eb1e62cd499a 100644 struct apple_dart_master_cfg *cfg = dev_iommu_priv_get(dev); struct platform_device *iommu_pdev = of_find_device_by_node(args->np); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c -index 1569090b1b12..1fdc413e2aa2 100644 +index 3628c83763e2..a0c5ab209471 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c -@@ -3912,7 +3912,8 @@ static int arm_smmu_clear_dirty_log(struct iommu_domain *domain, +@@ -3913,7 +3913,8 @@ static int arm_smmu_clear_dirty_log(struct iommu_domain *domain, } #endif @@ -377839,7 +380829,7 @@ index 1569090b1b12..1fdc413e2aa2 100644 { return iommu_fwspec_add_ids(dev, args->args, 1); } -@@ -4459,7 +4460,8 @@ static int arm_smmu_update_gbpa(struct arm_smmu_device *smmu, u32 set, u32 clr) +@@ -4460,7 +4461,8 @@ static int arm_smmu_update_gbpa(struct arm_smmu_device *smmu, u32 set, u32 clr) static void arm_smmu_free_msis(void *data) { struct device *dev = data; @@ -377849,7 +380839,7 @@ index 1569090b1b12..1fdc413e2aa2 100644 } static void arm_smmu_write_msi_msg(struct msi_desc *desc, struct msi_msg *msg) -@@ -4516,7 +4518,7 @@ static void arm_smmu_setup_msis(struct arm_smmu_device *smmu) +@@ -4517,7 +4519,7 @@ static void arm_smmu_setup_msis(struct arm_smmu_device *smmu) } /* Allocate MSIs for evtq, gerror and priq. Ignore cmdq */ @@ -377900,7 +380890,7 @@ index 2c6e9094f1e9..d98c9161948a 100644 struct platform_device *sysmmu = of_find_device_by_node(spec->np); struct exynos_iommu_owner *owner = dev_iommu_priv_get(dev); diff --git a/drivers/iommu/intel/dmar.c b/drivers/iommu/intel/dmar.c -index e14d496a9cbd..2bb40c1d7843 100644 +index d587bcec3198..2a5fd7b0d785 100644 --- a/drivers/iommu/intel/dmar.c +++ b/drivers/iommu/intel/dmar.c @@ -32,6 +32,7 @@ @@ -377911,7 +380901,7 @@ index e14d496a9cbd..2bb40c1d7843 100644 #include "perf.h" #include "trace.h" #include "perfmon.h" -@@ -1242,7 +1243,7 @@ static void free_iommu(struct intel_iommu *iommu) +@@ -1244,7 +1245,7 @@ static void free_iommu(struct intel_iommu *iommu) } if (iommu->qi) { @@ -377920,7 +380910,7 @@ index e14d496a9cbd..2bb40c1d7843 100644 kfree(iommu->qi->desc_status); kfree(iommu->qi); } -@@ -1794,7 +1795,8 @@ static void __dmar_enable_qi(struct intel_iommu *iommu) +@@ -1796,7 +1797,8 @@ static void __dmar_enable_qi(struct intel_iommu *iommu) int dmar_enable_qi(struct intel_iommu *iommu) { struct q_inval *qi; @@ -377930,7 +380920,7 @@ index e14d496a9cbd..2bb40c1d7843 100644 if (!ecap_qis(iommu->ecap)) return -ENOENT; -@@ -1815,19 +1817,19 @@ int dmar_enable_qi(struct intel_iommu *iommu) +@@ -1817,19 +1819,19 @@ int dmar_enable_qi(struct intel_iommu *iommu) * Need two pages to accommodate 256 descriptors of 256 bits each * if the remapping hardware supports scalable mode translation. */ @@ -378474,10 +381464,10 @@ index 000000000000..5a222d0ad25c + +#endif /* __IOMMU_PAGES_H */ diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c -index e9f9e8a23006..94b926bbac67 100644 +index 4d76e3a6afaa..99a096b52390 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c -@@ -3090,7 +3090,7 @@ void iommu_fwspec_free(struct device *dev) +@@ -3104,7 +3104,7 @@ void iommu_fwspec_free(struct device *dev) } EXPORT_SYMBOL_GPL(iommu_fwspec_free); @@ -381445,10 +384435,10 @@ index 34db37fd9675..04048f64a2c0 100644 return iommu_fwspec_add_ids(dev, args->args, 1); } diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig -index 6edafab595e6..bd40d887b9ee 100644 +index a15fbf9fa85f..a14c244dd769 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig -@@ -454,6 +454,14 @@ config LS_SCFG_MSI +@@ -461,6 +461,14 @@ config LS_SCFG_MSI config PARTITION_PERCPU bool @@ -381463,7 +384453,7 @@ index 6edafab595e6..bd40d887b9ee 100644 config STM32_EXTI bool select IRQ_DOMAIN -@@ -602,12 +610,49 @@ config RISCV_INTC +@@ -609,12 +617,49 @@ config RISCV_INTC depends on RISCV select IRQ_DOMAIN_HIERARCHY @@ -381514,10 +384504,10 @@ index 6edafab595e6..bd40d887b9ee 100644 bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile -index f4697c1a39c0..f3c0245f38e6 100644 +index d8778ff3f260..fbb2d1c21fa8 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile -@@ -92,6 +92,7 @@ obj-$(CONFIG_MVEBU_SEI) += irq-mvebu-sei.o +@@ -93,6 +93,7 @@ obj-$(CONFIG_MVEBU_SEI) += irq-mvebu-sei.o obj-$(CONFIG_LS_EXTIRQ) += irq-ls-extirq.o obj-$(CONFIG_LS_SCFG_MSI) += irq-ls-scfg-msi.o obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o irq-aspeed-i2c-ic.o irq-aspeed-scu-ic.o @@ -381525,7 +384515,7 @@ index f4697c1a39c0..f3c0245f38e6 100644 obj-$(CONFIG_STM32_EXTI) += irq-stm32-exti.o obj-$(CONFIG_QCOM_IRQ_COMBINER) += qcom-irq-combiner.o obj-$(CONFIG_IRQ_UNIPHIER_AIDET) += irq-uniphier-aidet.o -@@ -103,7 +104,11 @@ obj-$(CONFIG_QCOM_MPM) += irq-qcom-mpm.o +@@ -104,7 +105,11 @@ obj-$(CONFIG_QCOM_MPM) += irq-qcom-mpm.o obj-$(CONFIG_CSKY_MPINTC) += irq-csky-mpintc.o obj-$(CONFIG_CSKY_APB_INTC) += irq-csky-apb-intc.o obj-$(CONFIG_RISCV_INTC) += irq-riscv-intc.o @@ -482580,7 +485570,7 @@ index bf5c311875a1..b8ce73d09446 100644 # The following drivers are for devices that use the generic ACPI # pci_root.c driver but don't support standard ECAM config access. diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c -index a7170fd0e847..5699c374ce48 100644 +index a7170fd0e847..5203dcc21128 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -45,6 +45,9 @@ static struct irq_chip dw_pcie_msi_irq_chip = { @@ -482640,17 +485630,8 @@ index a7170fd0e847..5699c374ce48 100644 .irq_mask = dw_pci_bottom_mask, .irq_unmask = dw_pci_bottom_unmask, }; -@@ -640,10 +675,57 @@ EXPORT_SYMBOL_GPL(dw_pcie_own_conf_map_bus); - - static struct pci_ops dw_pcie_ops = { - .map_bus = dw_pcie_own_conf_map_bus, -+#if IS_ENABLED(CONFIG_PCIE_ULTRARISC) -+ .read = pci_generic_config_read32, -+ .write = pci_generic_config_write32, -+#else - .read = pci_generic_config_read, +@@ -644,6 +679,48 @@ static struct pci_ops dw_pcie_ops = { .write = pci_generic_config_write, -+#endif }; +/** @@ -482698,7 +485679,7 @@ index a7170fd0e847..5699c374ce48 100644 static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); -@@ -674,10 +756,14 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) +@@ -674,10 +751,14 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) if (pci->num_ob_windows <= ++i) break; @@ -482713,6 +485694,21 @@ index a7170fd0e847..5699c374ce48 100644 if (ret) { dev_err(pci->dev, "Failed to set MEM range %pr\n", entry->res); +diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c +index 2b60d20dfdf5..454ba04805a8 100644 +--- a/drivers/pci/controller/dwc/pcie-designware.c ++++ b/drivers/pci/controller/dwc/pcie-designware.c +@@ -765,6 +765,10 @@ static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes) + plc |= PORT_LINK_MODE_8_LANES; + lwsc |= PORT_LOGIC_LINK_WIDTH_8_LANES; + break; ++ case 16: ++ plc |= PORT_LINK_MODE_16_LANES; ++ lwsc |= PORT_LOGIC_LINK_WIDTH_16_LANES; ++ break; + default: + dev_err(pci->dev, "num-lanes %u: invalid value\n", num_lanes); + return; diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index ef0b2efa9f93..f46ce5f0dabb 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h @@ -484736,10 +487732,10 @@ index 000000000000..000ac313bed6 +#endif diff --git a/drivers/pci/controller/dwc/pcie-ultrarisc.c b/drivers/pci/controller/dwc/pcie-ultrarisc.c new file mode 100644 -index 000000000000..0be9d5d97f01 +index 000000000000..9a11fc7ad7d7 --- /dev/null +++ b/drivers/pci/controller/dwc/pcie-ultrarisc.c -@@ -0,0 +1,139 @@ +@@ -0,0 +1,156 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DWC PCIe RC driver for UltraRISC DP1000 SoC @@ -484775,7 +487771,24 @@ index 000000000000..0be9d5d97f01 + +static const struct of_device_id ultrarisc_pcie_of_match[]; + ++static struct pci_ops ultrarisc_pci_ops = { ++ .map_bus = dw_pcie_own_conf_map_bus, ++ .read = pci_generic_config_read32, ++ .write = pci_generic_config_write32, ++}; ++ ++static int ultrarisc_pcie_host_init(struct dw_pcie_rp *pp) ++{ ++ struct pci_host_bridge *bridge = pp->bridge; ++ ++ /* Set the bus ops */ ++ bridge->ops = &ultrarisc_pci_ops; ++ ++ return 0; ++} ++ +static const struct dw_pcie_host_ops ultrarisc_pcie_host_ops = { ++ .host_init = ultrarisc_pcie_host_init, +}; + +static int ultrarisc_pcie_establish_link(struct dw_pcie *pci) @@ -484815,7 +487828,7 @@ index 000000000000..0be9d5d97f01 + return 0; +} + -+static const struct dw_pcie_ops ultrarisc_pcie_ops = { ++static const struct dw_pcie_ops dw_pcie_ops = { + .start_link = ultrarisc_pcie_establish_link, +}; + @@ -484836,7 +487849,7 @@ index 000000000000..0be9d5d97f01 + return -ENOMEM; + + pci->dev = dev; -+ pci->ops = &ultrarisc_pcie_ops; ++ pci->ops = &dw_pcie_ops; + + /* Set a default value suitable for at most 16 in and 16 out windows */ + pci->atu_size = SZ_8K; @@ -609019,6 +612032,75 @@ index d5b28fd35d66..9eb9da3291cc 100644 pr_warn("invalid \"method\" property: %s\n", method); return ERR_PTR(-EINVAL); +diff --git a/drivers/tty/hvc/Kconfig b/drivers/tty/hvc/Kconfig +index 4f9264d005c0..6e05c5c7bca1 100644 +--- a/drivers/tty/hvc/Kconfig ++++ b/drivers/tty/hvc/Kconfig +@@ -108,7 +108,7 @@ config HVC_DCC_SERIALIZE_SMP + + config HVC_RISCV_SBI + bool "RISC-V SBI console support" +- depends on RISCV_SBI_V01 ++ depends on RISCV_SBI + select HVC_DRIVER + help + This enables support for console output via RISC-V SBI calls, which +diff --git a/drivers/tty/hvc/hvc_riscv_sbi.c b/drivers/tty/hvc/hvc_riscv_sbi.c +index 31f53fa77e4a..2f3571f17ecd 100644 +--- a/drivers/tty/hvc/hvc_riscv_sbi.c ++++ b/drivers/tty/hvc/hvc_riscv_sbi.c +@@ -39,21 +39,44 @@ static int hvc_sbi_tty_get(uint32_t vtermno, char *buf, int count) + return i; + } + +-static const struct hv_ops hvc_sbi_ops = { ++static const struct hv_ops hvc_sbi_v01_ops = { + .get_chars = hvc_sbi_tty_get, + .put_chars = hvc_sbi_tty_put, + }; + +-static int __init hvc_sbi_init(void) ++static int hvc_sbi_dbcn_tty_put(uint32_t vtermno, const char *buf, int count) + { +- return PTR_ERR_OR_ZERO(hvc_alloc(0, 0, &hvc_sbi_ops, 16)); ++ return sbi_debug_console_write(buf, count); + } +-device_initcall(hvc_sbi_init); + +-static int __init hvc_sbi_console_init(void) ++static int hvc_sbi_dbcn_tty_get(uint32_t vtermno, char *buf, int count) + { +- hvc_instantiate(0, 0, &hvc_sbi_ops); ++ return sbi_debug_console_read(buf, count); ++} ++ ++static const struct hv_ops hvc_sbi_dbcn_ops = { ++ .put_chars = hvc_sbi_dbcn_tty_put, ++ .get_chars = hvc_sbi_dbcn_tty_get, ++}; ++ ++static int __init hvc_sbi_init(void) ++{ ++ int err; ++ ++ if (sbi_debug_console_available) { ++ err = PTR_ERR_OR_ZERO(hvc_alloc(0, 0, &hvc_sbi_dbcn_ops, 256)); ++ if (err) ++ return err; ++ hvc_instantiate(0, 0, &hvc_sbi_dbcn_ops); ++ } else if (IS_ENABLED(CONFIG_RISCV_SBI_V01)) { ++ err = PTR_ERR_OR_ZERO(hvc_alloc(0, 0, &hvc_sbi_v01_ops, 256)); ++ if (err) ++ return err; ++ hvc_instantiate(0, 0, &hvc_sbi_v01_ops); ++ } else { ++ return -ENODEV; ++ } + + return 0; + } +-console_initcall(hvc_sbi_console_init); ++device_initcall(hvc_sbi_init); diff --git a/drivers/tty/serial/8250/8250_dma.c b/drivers/tty/serial/8250/8250_dma.c index 7f23037813bc..eaa808e16861 100644 --- a/drivers/tty/serial/8250/8250_dma.c @@ -609554,7 +612636,7 @@ index f13e91f2cace..7dd2a8e7b780 100644 { if (p->iotype == UPIO_MEM32BE) diff --git a/drivers/tty/serial/8250/8250_port.c b/drivers/tty/serial/8250/8250_port.c -index d5ad6cae6b65..87a7bbb8aa19 100644 +index 23aed9e89e30..45729185fc3c 100644 --- a/drivers/tty/serial/8250/8250_port.c +++ b/drivers/tty/serial/8250/8250_port.c @@ -1535,7 +1535,7 @@ static inline void __start_tx(struct uart_port *port) @@ -609575,7 +612657,7 @@ index d5ad6cae6b65..87a7bbb8aa19 100644 status = serial8250_rx_chars(up, status); } serial8250_modem_status(up); -@@ -2451,6 +2451,14 @@ int serial8250_do_startup(struct uart_port *port) +@@ -2450,6 +2450,14 @@ int serial8250_do_startup(struct uart_port *port) dev_warn_ratelimited(port->dev, "%s\n", msg); up->dma = NULL; } @@ -609591,9 +612673,18 @@ index d5ad6cae6b65..87a7bbb8aa19 100644 /* diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig -index bdc568a4ab66..6336fadff23e 100644 +index bdc568a4ab66..2df72d126498 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig +@@ -87,7 +87,7 @@ config SERIAL_EARLYCON_SEMIHOST + + config SERIAL_EARLYCON_RISCV_SBI + bool "Early console using RISC-V SBI" +- depends on RISCV_SBI_V01 ++ depends on RISCV_SBI + select SERIAL_CORE + select SERIAL_CORE_CONSOLE + select SERIAL_EARLYCON @@ -411,7 +411,8 @@ config SERIAL_PXA depends on ARCH_PXA || ARCH_MMP select SERIAL_CORE @@ -609639,6 +612730,52 @@ index 138abbc89738..0feb268753fb 100644 obj-$(CONFIG_SERIAL_SA1100) += sa1100.o obj-$(CONFIG_SERIAL_BCM63XX) += bcm63xx_uart.o obj-$(CONFIG_SERIAL_SAMSUNG) += samsung_tty.o +diff --git a/drivers/tty/serial/earlycon-riscv-sbi.c b/drivers/tty/serial/earlycon-riscv-sbi.c +index 27afb0b74ea7..0162155f0c83 100644 +--- a/drivers/tty/serial/earlycon-riscv-sbi.c ++++ b/drivers/tty/serial/earlycon-riscv-sbi.c +@@ -15,17 +15,38 @@ static void sbi_putc(struct uart_port *port, unsigned char c) + sbi_console_putchar(c); + } + +-static void sbi_console_write(struct console *con, +- const char *s, unsigned n) ++static void sbi_0_1_console_write(struct console *con, ++ const char *s, unsigned int n) + { + struct earlycon_device *dev = con->data; + uart_console_write(&dev->port, s, n, sbi_putc); + } + ++static void sbi_dbcn_console_write(struct console *con, ++ const char *s, unsigned int n) ++{ ++ int ret; ++ ++ while (n) { ++ ret = sbi_debug_console_write(s, n); ++ if (ret < 0) ++ break; ++ ++ s += ret; ++ n -= ret; ++ } ++} ++ + static int __init early_sbi_setup(struct earlycon_device *device, + const char *opt) + { +- device->con->write = sbi_console_write; ++ if (sbi_debug_console_available) ++ device->con->write = sbi_dbcn_console_write; ++ else if (IS_ENABLED(CONFIG_RISCV_SBI_V01)) ++ device->con->write = sbi_0_1_console_write; ++ else ++ return -ENODEV; ++ + return 0; + } + EARLYCON_DECLARE(sbi, early_sbi_setup); diff --git a/drivers/tty/serial/serial_port.c b/drivers/tty/serial/serial_port.c index ed3953bd0407..469ad26cde48 100644 --- a/drivers/tty/serial/serial_port.c @@ -615233,10 +618370,10 @@ index 000000000000..b88ae8727c29 + +#endif diff --git a/include/linux/iommu.h b/include/linux/iommu.h -index 0dea4c637fd2..afd79ee6363a 100644 +index 3dcf3118fbef..5bb55e5c2661 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h -@@ -696,7 +696,7 @@ struct iommu_ops { +@@ -744,7 +744,7 @@ struct iommu_ops { /* Request/Free a list of reserved regions for a device */ void (*get_resv_regions)(struct device *dev, struct list_head *list); @@ -615245,7 +618382,7 @@ index 0dea4c637fd2..afd79ee6363a 100644 bool (*is_attach_deferred)(struct device *dev); /* Per device IOMMU features */ -@@ -1242,7 +1242,7 @@ struct iommu_mm_data { +@@ -1293,7 +1293,7 @@ struct iommu_mm_data { int iommu_fwspec_init(struct device *dev, struct fwnode_handle *iommu_fwnode, const struct iommu_ops *ops); void iommu_fwspec_free(struct device *dev); @@ -615536,18 +618673,18 @@ index 8594cd9b642e..2992c1851b63 100644 static inline void irq_dispose_mapping(unsigned int virq) { } static inline struct irq_domain *irq_find_matching_fwnode( diff --git a/include/linux/irqdomain_defs.h b/include/linux/irqdomain_defs.h -index c29921fd8cd1..5c1fe6f1fcde 100644 +index 7a82107b0f3a..f2d9b8eb0d8d 100644 --- a/include/linux/irqdomain_defs.h +++ b/include/linux/irqdomain_defs.h -@@ -26,6 +26,8 @@ enum irq_domain_bus_token { +@@ -28,6 +28,8 @@ enum irq_domain_bus_token { DOMAIN_BUS_DMAR, DOMAIN_BUS_AMDVI, DOMAIN_BUS_PCI_DEVICE_IMS, + DOMAIN_BUS_DEVICE_MSI, + DOMAIN_BUS_WIRED_TO_MSI, + KABI_EXTEND_ENUM(DOMAIN_BUS_UB_MSI) }; - #endif /* _LINUX_IRQDOMAIN_DEFS_H */ diff --git a/include/linux/mfd/spacemit_p1.h b/include/linux/mfd/spacemit_p1.h new file mode 100644 index 000000000000..52614b8dca58 @@ -615818,7 +618955,7 @@ index 27f42f713c89..7617930d3157 100644 #define MLX4_IS_LEGACY_EQ_MODE(dev_cap) ((dev_cap).num_comp_vectors < \ (dev_cap).num_ports * MIN_MSIX_P_PORT) diff --git a/include/linux/mm.h b/include/linux/mm.h -index 1f36bf9ee02f..9f1207c2ec33 100644 +index 55bb6ba97a63..df173e9aacf7 100644 --- a/include/linux/mm.h +++ b/include/linux/mm.h @@ -3182,6 +3182,22 @@ static inline spinlock_t *pud_lock(struct mm_struct *mm, pud_t *pud) @@ -615845,10 +618982,10 @@ index 1f36bf9ee02f..9f1207c2ec33 100644 extern void free_initmem(void); diff --git a/include/linux/msi.h b/include/linux/msi.h -index 5fd8a6caae98..b0ac7a49b529 100644 +index 468319fac33d..86e79e630cdf 100644 --- a/include/linux/msi.h +++ b/include/linux/msi.h -@@ -420,6 +420,7 @@ bool arch_restore_msi_irqs(struct pci_dev *dev); +@@ -437,6 +437,7 @@ bool arch_restore_msi_irqs(struct pci_dev *dev); struct irq_domain; struct irq_domain_ops; struct irq_chip; @@ -615856,7 +618993,7 @@ index 5fd8a6caae98..b0ac7a49b529 100644 struct device_node; struct fwnode_handle; struct msi_domain_info; -@@ -439,6 +440,8 @@ struct msi_domain_info; +@@ -456,6 +457,8 @@ struct msi_domain_info; * function. * @msi_post_free: Optional function which is invoked after freeing * all interrupts. @@ -615865,7 +619002,7 @@ index 5fd8a6caae98..b0ac7a49b529 100644 * * @get_hwirq, @msi_init and @msi_free are callbacks used by the underlying * irqdomain. -@@ -476,6 +479,8 @@ struct msi_domain_ops { +@@ -493,6 +496,8 @@ struct msi_domain_ops { struct device *dev); void (*msi_post_free)(struct irq_domain *domain, struct device *dev); @@ -615874,7 +619011,7 @@ index 5fd8a6caae98..b0ac7a49b529 100644 }; /** -@@ -555,6 +560,10 @@ enum { +@@ -572,6 +577,10 @@ enum { MSI_FLAG_ALLOC_SIMPLE_MSI_DESCS = (1 << 5), /* Free MSI descriptors */ MSI_FLAG_FREE_MSI_DESCS = (1 << 6), @@ -615885,7 +619022,7 @@ index 5fd8a6caae98..b0ac7a49b529 100644 /* Mask for the generic functionality */ MSI_GENERIC_FLAGS_MASK = GENMASK(15, 0), -@@ -580,6 +589,11 @@ enum { +@@ -598,6 +607,11 @@ enum { * struct msi_parent_ops - MSI parent domain callbacks and configuration info * * @supported_flags: Required: The supported MSI flags of the parent domain @@ -615897,7 +619034,7 @@ index 5fd8a6caae98..b0ac7a49b529 100644 * @prefix: Optional: Prefix for the domain and chip name * @init_dev_msi_info: Required: Callback for MSI parent domains to setup parent * domain specific domain flags, domain ops and interrupt chip -@@ -587,6 +601,9 @@ enum { +@@ -605,6 +619,9 @@ enum { */ struct msi_parent_ops { u32 supported_flags; @@ -615907,7 +619044,7 @@ index 5fd8a6caae98..b0ac7a49b529 100644 const char *prefix; bool (*init_dev_msi_info)(struct device *dev, struct irq_domain *domain, struct irq_domain *msi_parent_domain, -@@ -635,13 +652,6 @@ struct msi_domain_info *msi_get_domain_info(struct irq_domain *domain); +@@ -653,13 +670,6 @@ struct msi_domain_info *msi_get_domain_info(struct irq_domain *domain); struct irq_domain *platform_msi_create_irq_domain(struct fwnode_handle *fwnode, struct msi_domain_info *info, struct irq_domain *parent); @@ -615921,7 +619058,7 @@ index 5fd8a6caae98..b0ac7a49b529 100644 /* When an MSI domain is used as an intermediate domain */ int msi_domain_prepare_irqs(struct irq_domain *domain, struct device *dev, -@@ -668,6 +678,10 @@ int platform_msi_device_domain_alloc(struct irq_domain *domain, unsigned int vir +@@ -686,6 +696,10 @@ int platform_msi_device_domain_alloc(struct irq_domain *domain, unsigned int vir void platform_msi_device_domain_free(struct irq_domain *domain, unsigned int virq, unsigned int nvec); void *platform_msi_get_host_data(struct irq_domain *domain); @@ -616700,10 +619837,10 @@ index 75d0ae490e29..8f222d1cccec 100644 } diff --git a/kernel/irq/msi.c b/kernel/irq/msi.c -index 5a4717a82024..915a4c2b1f65 100644 +index 038a05ae83dd..7b25d32e44ae 100644 --- a/kernel/irq/msi.c +++ b/kernel/irq/msi.c -@@ -726,11 +726,26 @@ static void msi_domain_free(struct irq_domain *domain, unsigned int virq, +@@ -733,11 +733,26 @@ static void msi_domain_free(struct irq_domain *domain, unsigned int virq, irq_domain_free_irqs_top(domain, virq, nr_irqs); } @@ -616730,7 +619867,7 @@ index 5a4717a82024..915a4c2b1f65 100644 }; static irq_hw_number_t msi_domain_ops_get_hwirq(struct msi_domain_info *info, -@@ -830,8 +845,11 @@ static struct irq_domain *__msi_create_irq_domain(struct fwnode_handle *fwnode, +@@ -837,8 +852,11 @@ static struct irq_domain *__msi_create_irq_domain(struct fwnode_handle *fwnode, domain = irq_domain_create_hierarchy(parent, flags | IRQ_DOMAIN_FLAG_MSI, 0, fwnode, &msi_domain_ops, info); @@ -616743,7 +619880,7 @@ index 5a4717a82024..915a4c2b1f65 100644 return domain; } -@@ -945,9 +963,9 @@ bool msi_create_device_irq_domain(struct device *dev, unsigned int domid, +@@ -952,9 +970,9 @@ bool msi_create_device_irq_domain(struct device *dev, unsigned int domid, void *chip_data) { struct irq_domain *domain, *parent = dev->msi.domain; @@ -616755,7 +619892,7 @@ index 5a4717a82024..915a4c2b1f65 100644 if (!irq_domain_is_msi_parent(parent)) return false; -@@ -970,7 +988,19 @@ bool msi_create_device_irq_domain(struct device *dev, unsigned int domid, +@@ -977,7 +995,19 @@ bool msi_create_device_irq_domain(struct device *dev, unsigned int domid, pops->prefix ? : "", bundle->chip.name, dev_name(dev)); bundle->chip.name = bundle->name; @@ -616776,7 +619913,7 @@ index 5a4717a82024..915a4c2b1f65 100644 if (!fwnode) goto free_bundle; -@@ -997,7 +1027,7 @@ bool msi_create_device_irq_domain(struct device *dev, unsigned int domid, +@@ -1004,7 +1034,7 @@ bool msi_create_device_irq_domain(struct device *dev, unsigned int domid, fail: msi_unlock_descs(dev); free_fwnode: @@ -616785,7 +619922,7 @@ index 5a4717a82024..915a4c2b1f65 100644 free_bundle: kfree(bundle); return false; -@@ -1431,34 +1461,10 @@ int msi_domain_alloc_irqs_all_locked(struct device *dev, unsigned int domid, int +@@ -1438,34 +1468,10 @@ int msi_domain_alloc_irqs_all_locked(struct device *dev, unsigned int domid, int return msi_domain_alloc_locked(dev, &ctrl); } @@ -616824,7 +619961,7 @@ index 5a4717a82024..915a4c2b1f65 100644 { struct msi_ctrl ctrl = { .domid = domid, .nirqs = 1, }; struct irq_domain *domain; -@@ -1466,17 +1472,16 @@ struct msi_map msi_domain_alloc_irq_at(struct device *dev, unsigned int domid, u +@@ -1473,17 +1479,16 @@ struct msi_map msi_domain_alloc_irq_at(struct device *dev, unsigned int domid, u struct msi_desc *desc; int ret; @@ -616844,7 +619981,7 @@ index 5a4717a82024..915a4c2b1f65 100644 } if (icookie) -@@ -1485,7 +1490,7 @@ struct msi_map msi_domain_alloc_irq_at(struct device *dev, unsigned int domid, u +@@ -1492,7 +1497,7 @@ struct msi_map msi_domain_alloc_irq_at(struct device *dev, unsigned int domid, u ret = msi_insert_desc(dev, desc, domid, index); if (ret) { map.index = ret; @@ -616853,7 +619990,7 @@ index 5a4717a82024..915a4c2b1f65 100644 } ctrl.first = ctrl.last = desc->msi_index; -@@ -1498,11 +1503,90 @@ struct msi_map msi_domain_alloc_irq_at(struct device *dev, unsigned int domid, u +@@ -1505,11 +1510,90 @@ struct msi_map msi_domain_alloc_irq_at(struct device *dev, unsigned int domid, u map.index = desc->msi_index; map.virq = desc->irq; } @@ -616945,7 +620082,7 @@ index 5a4717a82024..915a4c2b1f65 100644 static void __msi_domain_free_irqs(struct device *dev, struct irq_domain *domain, struct msi_ctrl *ctrl) { -@@ -1628,6 +1712,30 @@ void msi_domain_free_irqs_all(struct device *dev, unsigned int domid) +@@ -1635,6 +1719,30 @@ void msi_domain_free_irqs_all(struct device *dev, unsigned int domid) msi_unlock_descs(dev); } @@ -616977,7 +620114,7 @@ index 5a4717a82024..915a4c2b1f65 100644 * msi_get_domain_info - Get the MSI interrupt domain info for @domain * @domain: The interrupt domain to retrieve data from diff --git a/kernel/panic.c b/kernel/panic.c -index b78d80596617..018efee81805 100644 +index f352869feb25..6f88d7031594 100644 --- a/kernel/panic.c +++ b/kernel/panic.c @@ -37,6 +37,7 @@ @@ -616988,7 +620125,7 @@ index b78d80596617..018efee81805 100644 #define PANIC_TIMER_STEP 100 #define PANIC_BLINK_SPD 18 -@@ -282,6 +283,13 @@ void panic(const char *fmt, ...) +@@ -285,6 +286,13 @@ void panic(const char *fmt, ...) int old_cpu, this_cpu; bool _crash_kexec_post_notifiers = crash_kexec_post_notifiers; @@ -617003,10 +620140,10 @@ index b78d80596617..018efee81805 100644 /* * This thread may hit another WARN() in the panic path. diff --git a/kernel/sched/core.c b/kernel/sched/core.c -index 47877f3b52f6..b8316cecdf81 100644 +index 2740e9b918f5..bde5f0de1759 100644 --- a/kernel/sched/core.c +++ b/kernel/sched/core.c -@@ -6679,7 +6679,9 @@ static void __sched notrace __schedule(unsigned int sched_mode) +@@ -6691,7 +6691,9 @@ static void __sched notrace __schedule(unsigned int sched_mode) * if (signal_pending_state()) if (p->state & @state) * * Also, the membarrier system call requires a full memory barrier @@ -617017,7 +620154,7 @@ index 47877f3b52f6..b8316cecdf81 100644 */ rq_lock(rq, &rf); smp_mb__after_spinlock(); -@@ -6757,6 +6759,13 @@ static void __sched notrace __schedule(unsigned int sched_mode) +@@ -6769,6 +6771,13 @@ static void __sched notrace __schedule(unsigned int sched_mode) * architectures where spin_unlock is a full barrier, * - switch_to() for arm64 (weakly-ordered, spin_unlock * is a RELEASE barrier), @@ -617032,10 +620169,10 @@ index 47877f3b52f6..b8316cecdf81 100644 ++*switch_count; diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c -index b22f3c072d20..baa23111b7e7 100644 +index 6b30b3811c88..d7e331c50e3f 100644 --- a/kernel/sched/fair.c +++ b/kernel/sched/fair.c -@@ -10848,6 +10848,9 @@ int can_migrate_task(struct task_struct *p, struct lb_env *env) +@@ -10844,6 +10844,9 @@ int can_migrate_task(struct task_struct *p, struct lb_env *env) if (kthread_is_per_cpu(p)) return 0; @@ -628872,6 +632009,113 @@ index 4fff31dbe0e7..65e657ac1198 100644 /* following are kfuncs exported by HID for HID-BPF */ extern __u8 *hid_bpf_get_data(struct hid_bpf_ctx *ctx, unsigned int offset, +diff --git a/tools/testing/selftests/kvm/include/riscv/processor.h b/tools/testing/selftests/kvm/include/riscv/processor.h +index 5b62a3d2aa9b..e70ccda2011b 100644 +--- a/tools/testing/selftests/kvm/include/riscv/processor.h ++++ b/tools/testing/selftests/kvm/include/riscv/processor.h +@@ -10,10 +10,10 @@ + #include "kvm_util.h" + #include + +-static inline uint64_t __kvm_reg_id(uint64_t type, uint64_t idx, +- uint64_t size) ++static inline uint64_t __kvm_reg_id(uint64_t type, uint64_t subtype, ++ uint64_t idx, uint64_t size) + { +- return KVM_REG_RISCV | type | idx | size; ++ return KVM_REG_RISCV | type | subtype | idx | size; + } + + #if __riscv_xlen == 64 +@@ -22,24 +22,30 @@ static inline uint64_t __kvm_reg_id(uint64_t type, uint64_t idx, + #define KVM_REG_SIZE_ULONG KVM_REG_SIZE_U32 + #endif + +-#define RISCV_CONFIG_REG(name) __kvm_reg_id(KVM_REG_RISCV_CONFIG, \ +- KVM_REG_RISCV_CONFIG_REG(name), \ +- KVM_REG_SIZE_ULONG) ++#define RISCV_CONFIG_REG(name) __kvm_reg_id(KVM_REG_RISCV_CONFIG, 0, \ ++ KVM_REG_RISCV_CONFIG_REG(name), \ ++ KVM_REG_SIZE_ULONG) + +-#define RISCV_CORE_REG(name) __kvm_reg_id(KVM_REG_RISCV_CORE, \ +- KVM_REG_RISCV_CORE_REG(name), \ +- KVM_REG_SIZE_ULONG) ++#define RISCV_CORE_REG(name) __kvm_reg_id(KVM_REG_RISCV_CORE, 0, \ ++ KVM_REG_RISCV_CORE_REG(name), \ ++ KVM_REG_SIZE_ULONG) + +-#define RISCV_CSR_REG(name) __kvm_reg_id(KVM_REG_RISCV_CSR, \ +- KVM_REG_RISCV_CSR_REG(name), \ +- KVM_REG_SIZE_ULONG) ++#define RISCV_GENERAL_CSR_REG(name) __kvm_reg_id(KVM_REG_RISCV_CSR, \ ++ KVM_REG_RISCV_CSR_GENERAL, \ ++ KVM_REG_RISCV_CSR_REG(name), \ ++ KVM_REG_SIZE_ULONG) + +-#define RISCV_TIMER_REG(name) __kvm_reg_id(KVM_REG_RISCV_TIMER, \ +- KVM_REG_RISCV_TIMER_REG(name), \ +- KVM_REG_SIZE_U64) ++#define RISCV_TIMER_REG(name) __kvm_reg_id(KVM_REG_RISCV_TIMER, 0, \ ++ KVM_REG_RISCV_TIMER_REG(name), \ ++ KVM_REG_SIZE_U64) + +-#define RISCV_ISA_EXT_REG(idx) __kvm_reg_id(KVM_REG_RISCV_ISA_EXT, \ +- idx, KVM_REG_SIZE_ULONG) ++#define RISCV_ISA_EXT_REG(idx) __kvm_reg_id(KVM_REG_RISCV_ISA_EXT, \ ++ KVM_REG_RISCV_ISA_SINGLE, \ ++ idx, KVM_REG_SIZE_ULONG) ++ ++#define RISCV_SBI_EXT_REG(idx) __kvm_reg_id(KVM_REG_RISCV_SBI_EXT, \ ++ KVM_REG_RISCV_SBI_SINGLE, \ ++ idx, KVM_REG_SIZE_ULONG) + + /* L3 index Bit[47:39] */ + #define PGTBL_L3_INDEX_MASK 0x0000FF8000000000ULL +diff --git a/tools/testing/selftests/kvm/lib/riscv/processor.c b/tools/testing/selftests/kvm/lib/riscv/processor.c +index d146ca71e0c0..6c25f7843ef4 100644 +--- a/tools/testing/selftests/kvm/lib/riscv/processor.c ++++ b/tools/testing/selftests/kvm/lib/riscv/processor.c +@@ -201,7 +201,7 @@ void riscv_vcpu_mmu_setup(struct kvm_vcpu *vcpu) + satp = (vm->pgd >> PGTBL_PAGE_SIZE_SHIFT) & SATP_PPN; + satp |= SATP_MODE_48; + +- vcpu_set_reg(vcpu, RISCV_CSR_REG(satp), satp); ++ vcpu_set_reg(vcpu, RISCV_GENERAL_CSR_REG(satp), satp); + } + + void vcpu_arch_dump(FILE *stream, struct kvm_vcpu *vcpu, uint8_t indent) +@@ -315,7 +315,7 @@ struct kvm_vcpu *vm_arch_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id, + vcpu_set_reg(vcpu, RISCV_CORE_REG(regs.pc), (unsigned long)guest_code); + + /* Setup default exception vector of guest */ +- vcpu_set_reg(vcpu, RISCV_CSR_REG(stvec), (unsigned long)guest_unexp_trap); ++ vcpu_set_reg(vcpu, RISCV_GENERAL_CSR_REG(stvec), (unsigned long)guest_unexp_trap); + + return vcpu; + } +diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c +index 9f99ea42f45f..d8b7c9d78ad1 100644 +--- a/tools/testing/selftests/kvm/riscv/get-reg-list.c ++++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c +@@ -366,6 +366,7 @@ static const char *sbi_ext_single_id_to_str(__u64 reg_off) + "KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_PMU", + "KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_EXPERIMENTAL", + "KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_VENDOR", ++ "KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_DBCN", + }; + + if (reg_off >= ARRAY_SIZE(kvm_sbi_ext_reg_name)) { +@@ -545,8 +546,7 @@ static __u64 base_regs[] = { + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_PMU, + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_EXPERIMENTAL, + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_VENDOR, +- KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_MULTI_EN | 0, +- KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_MULTI_DIS | 0, ++ KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_DBCN, + }; + + /* diff --git a/tools/testing/selftests/riscv/hwprobe/Makefile b/tools/testing/selftests/riscv/hwprobe/Makefile index ebdbb3c22e54..f224b84591fb 100644 --- a/tools/testing/selftests/riscv/hwprobe/Makefile diff --git a/kernel.spec b/kernel.spec index 2e2322a..8a2bd7a 100644 --- a/kernel.spec +++ b/kernel.spec @@ -42,7 +42,7 @@ rm -f test_openEuler_sign.ko test_openEuler_sign.ko.sig %global upstream_sublevel 0 %global devel_release 115 %global maintenance_release .0.0 -%global pkg_release .119 +%global pkg_release .120 %global openeuler_lts 1 %global openeuler_major 2403 @@ -1087,6 +1087,13 @@ fi %endif %changelog +* Wed Nov 05 2025 Mingzheng Xing - 6.6.0-115.0.0.120 +- RISC-V kernel upgrade to 6.6.0-115.0.0 +- Remove CI-related file changes +- riscv: Backport steal-time support for RISC-V +- riscv: RISC-V SBI debug console extension support +- riscv: Add support for kernel mode vector + * Wed Nov 05 2025 Li Nan - 6.6.0-115.0.0.119 - !18713 iommu: Enabling Broadcast TLB Maintenance (BTM) for UMMU on ARM64 - iommu: Fix kabi breakage due to opening KVM_PINNED_VMID -- Gitee