From 0ebf66fe7c75ac476f977d16fead065b9720167a Mon Sep 17 00:00:00 2001 From: liyunfei Date: Wed, 19 Jul 2023 17:43:39 +0800 Subject: [PATCH] [Backport][RISCV] Handle "o" inline asm memory constraint --- ...andle-o-inline-asm-memory-constraint.patch | 117 ++++++++++++++++++ llvm.spec | 12 +- 2 files changed, 126 insertions(+), 3 deletions(-) create mode 100644 0001-Backport-RISCV-Handle-o-inline-asm-memory-constraint.patch diff --git a/0001-Backport-RISCV-Handle-o-inline-asm-memory-constraint.patch b/0001-Backport-RISCV-Handle-o-inline-asm-memory-constraint.patch new file mode 100644 index 0000000..96b5888 --- /dev/null +++ b/0001-Backport-RISCV-Handle-o-inline-asm-memory-constraint.patch @@ -0,0 +1,117 @@ +From a831cf03a32854ac193389819189e6ee93b0ecaf Mon Sep 17 00:00:00 2001 +From: wangpc +Date: Tue, 6 Jun 2023 17:49:58 +0800 +Subject: [Backport][RISCV] Handle "o" inline asm memory constraint + +Reference: https://reviews.llvm.org/rG26e41a80d07c + +Originally By: wangpc + +This is the same as D100412. + +We just found the same crash when we tried to compile some packages +like mariadb, php, etc. + +For constraint "o", it means "A memory operand is allowed, but +only if the address is offsettable". So I think it can be handled +just like constraint "m" for RISCV target. + +And we print verbose information when unsupported constraints occur. + +Reviewed By: asb + +Differential Revision: https://reviews.llvm.org/D151979 +--- + lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 4 +- + test/CodeGen/RISCV/inline-asm.ll | 53 ++++++++++++++++++++++++++ + 2 files changed, 56 insertions(+), 1 deletion(-) + +diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp +index d5826b46d738..a98dcea7dd8d 100644 +--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp ++++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp +@@ -1733,6 +1733,7 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) { + bool RISCVDAGToDAGISel::SelectInlineAsmMemoryOperand( + const SDValue &Op, unsigned ConstraintID, std::vector &OutOps) { + switch (ConstraintID) { ++ case InlineAsm::Constraint_o: + case InlineAsm::Constraint_m: + // We just support simple memory operands that have a single address + // operand and need no special handling. +@@ -1742,7 +1743,8 @@ bool RISCVDAGToDAGISel::SelectInlineAsmMemoryOperand( + OutOps.push_back(Op); + return false; + default: +- break; ++ report_fatal_error("Unexpected asm memory constraint " + ++ InlineAsm::getMemConstraintName(ConstraintID)); + } + + return true; +diff --git a/llvm/test/CodeGen/RISCV/inline-asm.ll b/llvm/test/CodeGen/RISCV/inline-asm.ll +index 0b04a7df2d18..feaa40b14e9d 100644 +--- a/llvm/test/CodeGen/RISCV/inline-asm.ll ++++ b/llvm/test/CodeGen/RISCV/inline-asm.ll +@@ -82,6 +82,59 @@ define i32 @constraint_m2(i32* %a) nounwind { + ret i32 %1 + } + ++define void @constraint_o(ptr %a) nounwind { ++; RV32I-LABEL: constraint_o: ++; RV32I: # %bb.0: ++; RV32I-NEXT: #APP ++; RV32I-NEXT: #NO_APP ++; RV32I-NEXT: ret ++; ++; RV64I-LABEL: constraint_o: ++; RV64I: # %bb.0: ++; RV64I-NEXT: #APP ++; RV64I-NEXT: #NO_APP ++; RV64I-NEXT: ret ++ call void asm sideeffect "", "=*o"(ptr elementtype(i32) %a) ++ ret void ++} ++ ++define i32 @constraint_o2(ptr %a) nounwind { ++; RV32I-LABEL: constraint_o2: ++; RV32I: # %bb.0: ++; RV32I-NEXT: #APP ++; RV32I-NEXT: lw a0, 0(a0) ++; RV32I-NEXT: #NO_APP ++; RV32I-NEXT: ret ++; ++; RV64I-LABEL: constraint_o2: ++; RV64I: # %bb.0: ++; RV64I-NEXT: #APP ++; RV64I-NEXT: lw a0, 0(a0) ++; RV64I-NEXT: #NO_APP ++; RV64I-NEXT: ret ++ %1 = tail call i32 asm "lw $0, $1", "=r,*o"(ptr elementtype(i32) %a) ++ ret i32 %1 ++} ++ ++define i32 @constraint_o_with_offset(ptr %a) nounwind { ++; RV32I-LABEL: constraint_o_with_offset: ++; RV32I: # %bb.0: ++; RV32I-NEXT: #APP ++; RV32I-NEXT: lw a0, 4(a0) ++; RV32I-NEXT: #NO_APP ++; RV32I-NEXT: ret ++; ++; RV64I-LABEL: constraint_o_with_offset: ++; RV64I: # %bb.0: ++; RV64I-NEXT: #APP ++; RV64I-NEXT: lw a0, 4(a0) ++; RV64I-NEXT: #NO_APP ++; RV64I-NEXT: ret ++ %1 = getelementptr i32, ptr %a, i32 1 ++ %2 = tail call i32 asm "lw $0, $1", "=r,*o"(ptr elementtype(i32) %1) ++ ret i32 %2 ++} ++ + define void @constraint_I() nounwind { + ; RV32I-LABEL: constraint_I: + ; RV32I: # %bb.0: +-- +2.28.0.windows.1 + diff --git a/llvm.spec b/llvm.spec index 342b1e8..4e25bca 100644 --- a/llvm.spec +++ b/llvm.spec @@ -35,7 +35,7 @@ Name: %{pkg_name} Version: %{maj_ver}.%{min_ver}.%{patch_ver} -Release: 3 +Release: 4 Summary: The Low Level Virtual Machine License: NCSA @@ -43,6 +43,8 @@ URL: http://llvm.org Source0: https://github.com/llvm/llvm-project/releases/download/llvmorg-%{version}/llvm-%{version}.src.tar.xz Source1: https://github.com/llvm/llvm-project/releases/download/llvmorg-%{version}/cmake-%{version}.src.tar.xz +Patch1: 0001-Backport-RISCV-Handle-o-inline-asm-memory-constraint.patch + BuildRequires: binutils-devel BuildRequires: cmake BuildRequires: gcc @@ -128,7 +130,8 @@ LLVM's modified googletest sources. %setup -T -q -b 1 -n cmake-%{version}.src cd .. mv cmake-%{version}.src cmake -%autosetup -n llvm-%{version}.src +%setup -T -q -b 0 -n llvm-%{version}.src +%autopatch -p2 pathfix.py -i %{__python3} -pn \ test/BugPoint/compile-custom.ll.py \ @@ -290,7 +293,10 @@ LD_LIBRARY_PATH=%{buildroot}/%{install_libdir} %{__ninja} check-all -C ./_build %{install_libdir}/libLLVMTestingSupport.a %changelog -* May 19 2023 cf-zhao -15.0.7-3 +* Wed Jul 19 2023 liyunfei - 15.0.7-4 +- [RISCV] Handle "o" inline asm memory constraint. + +* Fri May 19 2023 cf-zhao - 15.0.7-3 - Make this spec file support both system-version and multi-version. * Wed Jun 7 2023 Chenxi Mao - 15.0.7-2 -- Gitee