diff --git a/0001-Backport-RISCV-Handle-o-inline-asm-memory-constraint.patch b/0001-Backport-RISCV-Handle-o-inline-asm-memory-constraint.patch
index 96b5888a92ec7f12f5e3ebbc2b3fc952f4ea633a..c3a5f0a90f7cddf730aa8b710d8a581847ce4dc5 100644
--- a/0001-Backport-RISCV-Handle-o-inline-asm-memory-constraint.patch
+++ b/0001-Backport-RISCV-Handle-o-inline-asm-memory-constraint.patch
@@ -52,11 +52,11 @@ diff --git a/llvm/test/CodeGen/RISCV/inline-asm.ll b/llvm/test/CodeGen/RISCV/inl
 index 0b04a7df2d18..feaa40b14e9d 100644
 --- a/llvm/test/CodeGen/RISCV/inline-asm.ll
 +++ b/llvm/test/CodeGen/RISCV/inline-asm.ll
-@@ -82,6 +82,59 @@ define i32 @constraint_m2(i32* %a) nounwind {
+@@ -82,6 +82,40 @@ define i32 @constraint_m2(i32* %a) nounwind {
    ret i32 %1
  }
  
-+define void @constraint_o(ptr %a) nounwind {
++define void @constraint_o(i32* %a) nounwind {
 +; RV32I-LABEL: constraint_o:
 +; RV32I:       # %bb.0:
 +; RV32I-NEXT:    #APP
@@ -68,11 +68,11 @@ index 0b04a7df2d18..feaa40b14e9d 100644
 +; RV64I-NEXT:    #APP
 +; RV64I-NEXT:    #NO_APP
 +; RV64I-NEXT:    ret
-+  call void asm sideeffect "", "=*o"(ptr elementtype(i32) %a)
++  call void asm sideeffect "", "=*o"(i32* elementtype(i32) %a)
 +  ret void
 +}
 +
-+define i32 @constraint_o2(ptr %a) nounwind {
++define i32 @constraint_o2(i32* %a) nounwind {
 +; RV32I-LABEL: constraint_o2:
 +; RV32I:       # %bb.0:
 +; RV32I-NEXT:    #APP
@@ -86,28 +86,9 @@ index 0b04a7df2d18..feaa40b14e9d 100644
 +; RV64I-NEXT:    lw a0, 0(a0)
 +; RV64I-NEXT:    #NO_APP
 +; RV64I-NEXT:    ret
-+  %1 = tail call i32 asm "lw $0, $1", "=r,*o"(ptr elementtype(i32) %a)
++  %1 = tail call i32 asm "lw $0, $1", "=r,*o"(i32* elementtype(i32) %a)
 +  ret i32 %1
 +}
-+
-+define i32 @constraint_o_with_offset(ptr %a) nounwind {
-+; RV32I-LABEL: constraint_o_with_offset:
-+; RV32I:       # %bb.0:
-+; RV32I-NEXT:    #APP
-+; RV32I-NEXT:    lw a0, 4(a0)
-+; RV32I-NEXT:    #NO_APP
-+; RV32I-NEXT:    ret
-+;
-+; RV64I-LABEL: constraint_o_with_offset:
-+; RV64I:       # %bb.0:
-+; RV64I-NEXT:    #APP
-+; RV64I-NEXT:    lw a0, 4(a0)
-+; RV64I-NEXT:    #NO_APP
-+; RV64I-NEXT:    ret
-+  %1 = getelementptr i32, ptr %a, i32 1
-+  %2 = tail call i32 asm "lw $0, $1", "=r,*o"(ptr elementtype(i32) %1)
-+  ret i32 %2
-+}
 +
  define void @constraint_I() nounwind {
  ; RV32I-LABEL: constraint_I:
diff --git a/llvm.spec b/llvm.spec
index 4e25bca9eb7dc54ce5586e895f978055783b8b71..3c8979b56fea05ba719b383d47b9d92af84c9e17 100644
--- a/llvm.spec
+++ b/llvm.spec
@@ -35,7 +35,7 @@
 
 Name:		%{pkg_name}
 Version:	%{maj_ver}.%{min_ver}.%{patch_ver}
-Release:	4
+Release:	5
 Summary:	The Low Level Virtual Machine
 
 License:	NCSA
@@ -293,6 +293,9 @@ LD_LIBRARY_PATH=%{buildroot}/%{install_libdir}  %{__ninja} check-all -C ./_build
 %{install_libdir}/libLLVMTestingSupport.a
 
 %changelog
+* Wed Aug 9 2023 liyunfei <liyunfei33@huawei.com> - 15.0.7-5
+- Solve opaque pointer issue in Backport testcase.
+
 * Wed Jul 19 2023 liyunfei <liyunfei33@huawei.com> - 15.0.7-4
 - [RISCV] Handle "o" inline asm memory constraint.