From a408fa01b2e373724ae8d15c8ae80562310b1a12 Mon Sep 17 00:00:00 2001 From: root Date: Fri, 13 Sep 2024 14:11:55 +0800 Subject: [PATCH] add sw64-8A support --- mysql-Add-sw64-8A-architecture.patch | 786 +++++++++++++++++++++++++++ mysql.spec | 7 +- 2 files changed, 792 insertions(+), 1 deletion(-) create mode 100644 mysql-Add-sw64-8A-architecture.patch diff --git a/mysql-Add-sw64-8A-architecture.patch b/mysql-Add-sw64-8A-architecture.patch new file mode 100644 index 0000000..19e7033 --- /dev/null +++ b/mysql-Add-sw64-8A-architecture.patch @@ -0,0 +1,786 @@ +diff -uNar mysql-8.0.38.org/boost/boost_1_77_0/boost/atomic/detail/core_arch_ops_gcc_sw_64.hpp mysql-8.0.38.sw/boost/boost_1_77_0/boost/atomic/detail/core_arch_ops_gcc_sw_64.hpp +--- mysql-8.0.38.org/boost/boost_1_77_0/boost/atomic/detail/core_arch_ops_gcc_sw_64.hpp 2024-09-12 21:42:42.286762636 +0800 ++++ mysql-8.0.38.sw/boost/boost_1_77_0/boost/atomic/detail/core_arch_ops_gcc_sw_64.hpp 2024-09-12 22:04:46.869785910 +0800 +@@ -115,18 +115,15 @@ + static BOOST_FORCEINLINE storage_type exchange(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, tmp; +- storage_type tmp1, tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n\t" +- "ldi %2,%4\n\t" +- "ldi %3,1\n\t" +- "mov %5, %1\n\t" ++ "ldi %2,%3\n\t" ++ "mov %4, %1\n\t" + "lldw %0, 0(%2)\n\t" +- "wr_f %3\n\t" + "lstw %1, 0(%2)\n\t" +- "rd_f %1\n\t" + "beq %1, 2f\n\t" + + ".subsection 2\n\t" +@@ -134,11 +131,10 @@ + ".previous\n\t" + + : "=&r" (original), // %0 +- "=&r" (tmp), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp), // %1 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); +@@ -158,11 +154,9 @@ + "ldi %4,%6\n\t" + "lldw %2, 0(%4)\n\t" // current = *(&storage) + "cmpeq %2, %0, %5\n\t" // success = current == expected +- "wr_f %5\n\t" // success = current == expected ++ "beq %5, 2f\n\t" // if (success == 0) goto end + "mov %2, %0\n\t" // expected = current + "lstw %1, 0(%4)\n\t" // storage = desired; desired = store succeeded +- "rd_f %1\n\t" // storage = desired; desired = store succeeded +- "beq %5, 2f\n\t" // if (success == 0) goto end + "mov %1, %3\n\t" // success = desired + "2:\n\t" + : "+r" (expected), // %0 +@@ -195,11 +189,9 @@ + "mov %7, %1\n\t" // tmp = desired + "lldw %2, 0(%4)\n\t" // current = *(&storage) + "cmpeq %2, %0, %5\n\t" // success = current == expected +- "wr_f %5\n\t" // success = current == expected ++ "beq %5, 2f\n\t" // if (success == 0) goto end + "mov %2, %0\n\t" // expected = current + "lstw %1, 0(%4)\n\t" // storage = tmp; tmp = store succeeded +- "rd_f %1\n\t" // storage = tmp; tmp = store succeeded +- "beq %5, 2f\n\t" // if (success == 0) goto end + "beq %1, 3f\n\t" // if (tmp == 0) goto retry + "mov %1, %3\n\t" // success = tmp + "2:\n\t" +@@ -228,18 +220,15 @@ + static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1, tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n\t" +- "ldi %2,%4\n\t" +- "ldi %3,1\n\t" ++ "ldi %2,%3\n\t" + "lldw %0, 0(%2)\n\t" +- "wr_f %3\n\t" +- "addw %0, %5, %1\n\t" ++ "addw %0, %4, %1\n\t" + "lstw %1, 0(%2)\n\t" +- "rd_f %1\n\t" + "beq %1, 2f\n\t" + + ".subsection 2\n\t" +@@ -248,10 +237,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); +@@ -261,18 +249,15 @@ + static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1, tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n\t" +- "ldi %2,%4\n\t" +- "ldi %3,1\n\t" ++ "ldi %2,%3\n\t" + "lldw %0, 0(%2)\n\t" +- "wr_f %3\n\t" +- "subw %0, %5, %1\n\t" ++ "subw %0, %4, %1\n\t" + "lstw %1, 0(%2)\n\t" +- "rd_f %1\n\t" + "beq %1, 2f\n\t" + + ".subsection 2\n\t" +@@ -280,11 +265,10 @@ + ".previous\n\t" + + : "=&r" (original), // %0 +- "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (modified), // %1 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); +@@ -294,18 +278,15 @@ + static BOOST_FORCEINLINE storage_type fetch_and(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1,tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n\t" +- "ldi %2,%4\n\t" +- "ldi %3,1\n\t" ++ "ldi %2,%3\n\t" + "lldw %0, 0(%2)\n\t" +- "wr_f %3\n\t" +- "and %0, %5, %1\n\t" ++ "and %0, %4, %1\n\t" + "lstw %1, 0(%2)\n\t" +- "rd_f %1\n\t" + "beq %1, 2f\n\t" + + ".subsection 2\n\t" +@@ -313,11 +294,10 @@ + ".previous\n\t" + + : "=&r" (original), // %0 +- "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (modified), // %1 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); +@@ -327,18 +307,15 @@ + static BOOST_FORCEINLINE storage_type fetch_or(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1,tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n" +- "ldi %2,%4\n" +- "ldi %3,1\n" ++ "ldi %2,%3\n" + "lldw %0, 0(%2)\n" +- "wr_f %? \n" +- "bis %0, %5, %1\n" ++ "bis %0, %4, %1\n" + "lstw %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -347,10 +324,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); +@@ -360,18 +336,15 @@ + static BOOST_FORCEINLINE storage_type fetch_xor(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1, tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n" +- "ldi %2,%4\n" +- "ldi %3,1\n" ++ "ldi %2,%3\n" + "lldw %0, 0(%2)\n" +- "wr_f %3 \n" +- "xor %0, %5, %1\n" ++ "xor %0, %4, %1\n" + "lstw %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -380,10 +353,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); +@@ -412,19 +384,16 @@ + static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1, tmp2; ++ storage_type tmp1; + base_type::fence_before(order); + __asm__ __volatile__ + ( + "1:\n" +- "ldi %2,%4\n" +- "ldi %3,1\n" ++ "ldi %2,%3\n" + "lldw %0, 0(%2)\n" +- "wr_f %3 \n" +- "addw %0, %5, %1\n" ++ "addw %0, %4, %1\n" + "zapnot %1, #1, %1\n" + "lstw %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -433,10 +402,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + base_type::fence_after(order); +@@ -446,19 +414,16 @@ + static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1, tmp2; ++ storage_type tmp1; + base_type::fence_before(order); + __asm__ __volatile__ + ( + "1:\n" +- "ldi %2,%4\n" +- "ldi %3,1\n" ++ "ldi %2,%3\n" + "lldw %0, 0(%2)\n" +- "wr_f %3 \n" +- "subw %0, %5, %1\n" ++ "subw %0, %4, %1\n" + "zapnot %1, #1, %1\n" + "lstw %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -467,10 +432,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + base_type::fence_after(order); +@@ -488,19 +452,16 @@ + static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1,tmp2; ++ storage_type tmp1; + base_type::fence_before(order); + __asm__ __volatile__ + ( + "1:\n" +- "ldi %2,%4\n" +- "ldi %3,1\n" ++ "ldi %2,%3\n" + "lldw %0, 0(%2)\n" +- "wr_f %3 \n" +- "addw %0, %5, %1\n" ++ "addw %0, %4, %1\n" + "sextb %1, %1\n" + "lstw %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -509,10 +470,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + base_type::fence_after(order); +@@ -522,19 +482,16 @@ + static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1,tmp2; ++ storage_type tmp1; + base_type::fence_before(order); + __asm__ __volatile__ + ( + "1:\n" +- "ldi %2,%4\n" +- "ldi %3,1\n" ++ "ldi %2,%3\n" + "lldw %0, 0(%2)\n" +- "wr_f %3 \n" +- "subw %0, %5, %1\n" ++ "subw %0, %4, %1\n" + "sextb %1, %1\n" + "lstw %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -543,10 +500,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + base_type::fence_after(order); +@@ -565,19 +521,16 @@ + static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1,tmp2; ++ storage_type tmp1; + base_type::fence_before(order); + __asm__ __volatile__ + ( + "1:\n" +- "ldi %2,%4\n" +- "ldi %3\n" ++ "ldi %2,%3\n" + "lldw %0, 0(%2)\n" +- "wr_f %3 \n" +- "addw %0, %5, %1\n" ++ "addw %0, %4, %1\n" + "zapnot %1, #3, %1\n" + "lstw %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -586,10 +539,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + base_type::fence_after(order); +@@ -599,19 +551,16 @@ + static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1,tmp2; ++ storage_type tmp1; + base_type::fence_before(order); + __asm__ __volatile__ + ( + "1:\n" +- "ldi %2,%4\n" +- "ldi %3,1\n" ++ "ldi %2,%3\n" + "lldw %0, 0(%2)\n" +- "wr_f %3 \n" +- "subw %0, %5, %1\n" ++ "subw %0, %4, %1\n" + "zapnot %1, #3, %1\n" + "lstw %1, %2\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -620,10 +569,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + base_type::fence_after(order); +@@ -641,18 +589,15 @@ + static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1,tmp2; ++ storage_type tmp1; + base_type::fence_before(order); + __asm__ __volatile__ + ( +- "ldi %2,%4\n" +- "ldi %3,1\n" ++ "ldi %2,%3\n" + "lldw %0, 0(%2)\n" +- "wr_f %3 \n" +- "addw %0, %5, %1\n" ++ "addw %0, %4, %1\n" + "sexth %1, %1\n" + "lstw %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -661,10 +606,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + base_type::fence_after(order); +@@ -674,19 +618,16 @@ + static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1,tmp2; ++ storage_type tmp1; + base_type::fence_before(order); + __asm__ __volatile__ + ( + "1:\n" +- "ldi %2,%4\n" +- "ldi %3,1\n" ++ "ldi %2,%3\n" + "lldw %0, 0(%2)\n" +- "wr_f %3 \n" +- "subw %0, %5, %1\n" ++ "subw %0, %4, %1\n" + "sexth %1, %1\n" + "lstw %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -695,10 +636,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + base_type::fence_after(order); +@@ -735,18 +675,15 @@ + static BOOST_FORCEINLINE storage_type exchange(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, tmp; +- storage_type tmp1,tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n" + "ldi %2,%4\n" +- "ldi %3,1\n" + "mov %5, %1\n" + "lldl %0, 0(%2)\n" +- "wr_f %3 \n" + "lstl %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -755,10 +692,9 @@ + + : "=&r" (original), // %0 + "=&r" (tmp), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); +@@ -778,11 +714,9 @@ + "ldi %4,%6\n" + "lldl %2, 0(%4)\n" // current = *(&storage) + "cmpeq %2, %0, %5\n" // success = current == expected +- "wr_f %5 \n" ++ "beq %5, 2f\n" // if (success == 0) goto end + "mov %2, %0\n" // expected = current + "lstl %1, 0(%4)\n" // storage = desired; desired = store succeeded +- "rd_f %1 \n" +- "beq %5, 2f\n" // if (success == 0) goto end + "mov %1, %3\n" // success = desired + "2:\n\t" + : "+r" (expected), // %0 +@@ -815,11 +749,10 @@ + "mov %7, %1\n" // tmp = desired + "lldl %2, 0(%4)\n" // current = *(&storage) + "cmpeq %2, %0, %5\n" // success = current == expected +- "wr_f %5 \n" ++ "beq %5, 2f\n" // if (success == 0) goto end + "mov %2, %0\n" // expected = current + "lstl %1, 0(%4)\n" // storage = tmp; tmp = store succeeded + "rd_f %1 \n" +- "beq %5, 2f\n" // if (success == 0) goto end + "beq %1, 3f\n" // if (tmp == 0) goto retry + "mov %1, %3\n" // success = tmp + "2:\n\t" +@@ -848,18 +781,15 @@ + static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1, tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n" +- "ldi %2,%4\n" +- "ldi %3,1\n" ++ "ldi %2,%3\n" + "lldl %0, 0(%2)\n" +- "wr_f %3 \n" +- "addl %0, %5, %1\n" ++ "addl %0, %4, %1\n" + "lstl %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -868,10 +798,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); +@@ -881,18 +810,15 @@ + static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1,tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n" +- "ldi %2,%4\n" +- "ldi %3,1\n" ++ "ldi %2,%3\n" + "lldl %0, 0(%2)\n" +- "wr_f %3 \n" +- "subl %0, %5, %1\n" ++ "subl %0, %4, %1\n" + "lstl %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -901,10 +827,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); +@@ -914,18 +839,15 @@ + static BOOST_FORCEINLINE storage_type fetch_and(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1,tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n" +- "ldi %2,%4\n" +- "ldi %3,1\n" ++ "ldi %2,%3\n" + "lldl %0, 0(%2)\n" +- "wr_f %3 \n" +- "and %0, %5, %1\n" ++ "and %0, %4, %1\n" + "lstl %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -934,10 +856,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); +@@ -947,18 +868,15 @@ + static BOOST_FORCEINLINE storage_type fetch_or(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1,tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n" +- "ldi %2,%4\n" +- "ldi %3,1\n" ++ "ldi %2,%3\n" + "lldl %0, 0(%2)\n" +- "wr_f %3 \n" +- "bis %0, %5, %1\n" ++ "bis %0, %4, %1\n" + "lstl %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -967,10 +885,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); +@@ -980,18 +897,15 @@ + static BOOST_FORCEINLINE storage_type fetch_xor(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1,tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n" +- "ldi %2,%4\n" +- "ldi %3,1\n" ++ "ldi %2,%3\n" + "lldl %0, 0(%2)\n" +- "wr_f %3 \n" +- "xor %0, %5, %1\n" ++ "xor %0, %4, %1\n" + "lstl %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -1000,10 +914,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); diff --git a/mysql.spec b/mysql.spec index 9c64a22..3a8f5f8 100644 --- a/mysql.spec +++ b/mysql.spec @@ -30,7 +30,7 @@ %global sameevr %{?epoch:%{epoch}:}%{version}-%{release} Name: mysql Version: 8.0.38 -Release: 1 +Release: 2 Summary: MySQL client programs and shared libraries URL: http://www.mysql.com License: GPL-2.0-or-later AND LGPL-2.1-only AND BSL-1.0 AND GPL-1.0-or-later OR Artistic-1.0-Perl AND BSD-2-Clause @@ -61,6 +61,7 @@ Patch81: disable-moutline-atomics-for-aarch64.patch Patch115: boost-1.58.0-pool.patch Patch125: boost-1.57.0-mpl-print.patch Patch126: mysql-Add-sw64-architecture.patch +Patch127: mysql-Add-sw64-8A-architecture.patch BuildRequires: cmake gcc-c++ libaio-devel libedit-devel libevent-devel libicu-devel lz4 BuildRequires: lz4-devel mecab-devel bison libzstd-devel @@ -229,6 +230,7 @@ pushd boost/boost_$(echo %{boost_bundled_version}| tr . _) popd %ifarch sw_64 %patch126 -p1 +%patch127 -p1 %endif pushd mysql-test add_test () { @@ -543,6 +545,9 @@ fi %{_mandir}/man1/mysql_config.1* %changelog +* Fri Sep 13 2024 wuzx - 8.0.38-2 +- add sw64-8A support + * Mon Jul 22 2024 wangkai <13474090681@163.com> - 8.0.38-1 - Update to 8.0.38 for fix CVEs(CVE-2024-21125,CVE-2024-21142,CVE-2024-21179, CVE-2024-21171,CVE-2024-21130,CVE-2024-21162,CVE-2024-21177,CVE-2024-20996, -- Gitee