diff --git a/nspr-Add-sw64-8A-architecture.patch b/nspr-Add-sw64-8A-architecture.patch
new file mode 100644
index 0000000000000000000000000000000000000000..0581fd90667ee2e04fc6ae2777dd56c4ec374123
--- /dev/null
+++ b/nspr-Add-sw64-8A-architecture.patch
@@ -0,0 +1,79 @@
+diff -uNar nspr-4.32.org/nspr/pr/include/md/_linux.h nspr-4.32.sw/nspr/pr/include/md/_linux.h
+--- nspr-4.32.org/nspr/pr/include/md/_linux.h	2024-09-12 22:16:13.135797968 +0800
++++ nspr-4.32.sw/nspr/pr/include/md/_linux.h	2024-09-12 22:23:27.759805605 +0800
+@@ -271,16 +271,13 @@
+ #define _MD_INIT_ATOMIC()
+ #define _MD_ATOMIC_ADD(ptr, i) ({               \
+     PRInt32 __atomic_tmp, __atomic_ret;   \
+-    PRInt32 __atomic_tmp1, __atomic_tmp2;   \
++    PRInt32 __atomic_tmp1;   \
+     __asm__ __volatile__(                       \
+     "1: ldi    %[tmp1],%[val]      \n"     \
+-    "   ldi    %[tmp2],1          \n"     \
+     "   lldw   %[ret], 0(%[tmp1])          \n"     \
+-    "   wr_f   %[tmp2]          \n"     \
+     "   addw   %[ret], %[inc], %[tmp]  \n"     \
+     "   addw    %[ret], %[inc], %[ret]  \n"     \
+     "   lstw   %[tmp], 0(%[tmp1])          \n"     \
+-    "   rd_f   %[tmp]        \n"     \
+     "   beq     %[tmp], 2f              \n"     \
+     ".subsection 2                      \n"     \
+     "2: br      1b                      \n"     \
+@@ -288,7 +285,6 @@
+     : [ret] "=&r" (__atomic_ret),               \
+       [tmp] "=&r" (__atomic_tmp),               \
+       [tmp1] "=&r" (__atomic_tmp1),               \
+-      [tmp2] "=&r" (__atomic_tmp2),               \
+       [val] "=m" (*ptr)                         \
+     : [inc] "Ir" (i), "m" (*ptr));              \
+     __atomic_ret;                               \
+@@ -296,16 +292,13 @@
+ #define _MD_ATOMIC_INCREMENT(ptr) _MD_ATOMIC_ADD(ptr, 1)
+ #define _MD_ATOMIC_DECREMENT(ptr) ({            \
+     PRInt32 __atomic_tmp, __atomic_ret;   \
+-    PRInt32 __atomic_tmp1, __atomic_tmp2;   \
++    PRInt32 __atomic_tmp1;   \
+     __asm__ __volatile__(                       \
+     "1: ldi    %[tmp1],%[val]      \n"     \
+-    "   ldi    %[tmp2],1          \n"     \
+     "   lldw   %[ret], 0(%[tmp1])          \n"     \
+-    "   wr_f   %[tmp2]          \n"     \
+     "   subw    %[ret], 1, %[tmp]       \n"     \
+     "   subw    %[ret], 1, %[ret]       \n"     \
+     "   lstw   %[tmp], 0(%[tmp1])          \n"     \
+-    "   rd_f   %[tmp]        \n"     \
+     "   beq     %[tmp], 2f              \n"     \
+     ".subsection 2                      \n"     \
+     "2: br      1b                      \n"     \
+@@ -313,22 +306,18 @@
+     : [ret] "=&r" (__atomic_ret),               \
+       [tmp] "=&r" (__atomic_tmp),               \
+       [tmp1] "=&r" (__atomic_tmp1),               \
+-      [tmp2] "=&r" (__atomic_tmp2),               \
+       [val] "=m" (*ptr)                         \
+     : "m" (*ptr));                              \
+     __atomic_ret;                               \
+ })
+ #define _MD_ATOMIC_SET(ptr, n) ({               \
+     PRInt32 __atomic_tmp, __atomic_ret;   \
+-    PRInt32 __atomic_tmp1, __atomic_tmp2;   \
++    PRInt32 __atomic_tmp1;   \
+     __asm__ __volatile__(                       \
+     "1: ldi    %[tmp1],%[val]      \n"     \
+-    "   ldi    %[tmp2],1          \n"     \
+     "   lldw   %[ret], 0(%[tmp1])          \n"     \
+-    "   wr_f   %[tmp2]          \n"     \
+     "   mov     %[newval], %[tmp]       \n"     \
+     "   lstw   %[tmp], 0(%[tmp1])          \n"     \
+-    "   rd_f   %[tmp]        \n"     \
+     "   beq     %[tmp], 2f              \n"     \
+     ".subsection 2                      \n"     \
+     "2: br      1b                      \n"     \
+@@ -336,7 +325,6 @@
+     : [ret] "=&r" (__atomic_ret),               \
+       [tmp] "=&r"(__atomic_tmp),                \
+       [tmp1] "=&r" (__atomic_tmp1),               \
+-      [tmp2] "=&r" (__atomic_tmp2),               \
+       [val] "=m" (*ptr)                         \
+     : [newval] "Ir" (n), "m" (*ptr));           \
+     __atomic_ret;                               \
diff --git a/nspr.spec b/nspr.spec
index d2f6508e49b02298ba0b2a17ca7055e5101af1c1..33387be4a3296d8ab54b1872ec6cb71b627330a3 100644
--- a/nspr.spec
+++ b/nspr.spec
@@ -1,7 +1,7 @@
 %global nspr_version 4.32
 Name:           nspr
 Version:        4.32.0
-Release:        5
+Release:        6
 Summary:        Netscape Portable Runtime
 License:        MPLv2.0
 URL:            http://www.mozilla.org/projects/nspr
@@ -16,6 +16,7 @@ Patch2: support-loongarch64-build.patch
 %endif
 %ifarch sw_64
 Patch3:         nspr-Add-sw64-architecture.patch
+Patch4:         nspr-Add-sw64-8A-architecture.patch
 %endif
 
 %description
@@ -91,6 +92,9 @@ install -c -m 644 nspr-config.1 $RPM_BUILD_ROOT%{_mandir}/man1/nspr-config.1
 %{_mandir}/man*/*
 
 %changelog
+* Fri Sep 13 2024 wuzx<wuzx1226@qq.com> - 4.32.0-6
+- Add sw64-8A support
+
 * Fri Feb 24 2023 Wenyu Liu<liuwenyu7@huawei.com> - 4.32.0-5
 - disable debug option