diff --git a/8352716-tz-Update-Timezone-Data-to-2025b.patch b/8352716-tz-Update-Timezone-Data-to-2025b.patch new file mode 100644 index 0000000000000000000000000000000000000000..6ee6f3e405f68b74dff1cc4ee6356d0ed7e7fcdf --- /dev/null +++ b/8352716-tz-Update-Timezone-Data-to-2025b.patch @@ -0,0 +1,465 @@ +From ab296b2d0baf20428d3f8196ff50d36bc03f849c Mon Sep 17 00:00:00 2001 +Date: Tue, 29 Apr 2025 11:13:06 +0800 +Subject: [PATCH] 8352716: (tz) Update Timezone Data to 2025b + +--- + jdk/make/data/tzdata/VERSION | 2 +- + jdk/make/data/tzdata/asia | 12 ++- + jdk/make/data/tzdata/northamerica | 9 ++ + jdk/make/data/tzdata/southamerica | 86 +++++++++++++++---- + jdk/make/data/tzdata/zone.tab | 3 +- + .../java/util/TimeZone/TimeZoneData/VERSION | 2 +- + jdk/test/sun/util/calendar/zi/tzdata/VERSION | 2 +- + jdk/test/sun/util/calendar/zi/tzdata/asia | 12 ++- + .../sun/util/calendar/zi/tzdata/northamerica | 9 ++ + .../sun/util/calendar/zi/tzdata/southamerica | 86 +++++++++++++++---- + jdk/test/sun/util/calendar/zi/tzdata/zone.tab | 3 +- + 11 files changed, 187 insertions(+), 39 deletions(-) + +diff --git a/jdk/make/data/tzdata/VERSION b/jdk/make/data/tzdata/VERSION +index 9c056fac3..4bd54efbc 100644 +--- a/jdk/make/data/tzdata/VERSION ++++ b/jdk/make/data/tzdata/VERSION +@@ -21,4 +21,4 @@ + # or visit www.oracle.com if you need additional information or have any + # questions. + # +-tzdata2025a ++tzdata2025b +diff --git a/jdk/make/data/tzdata/asia b/jdk/make/data/tzdata/asia +index 73cccd39a..d52e8de87 100644 +--- a/jdk/make/data/tzdata/asia ++++ b/jdk/make/data/tzdata/asia +@@ -1523,6 +1523,16 @@ Zone Asia/Jayapura 9:22:48 - LMT 1932 Nov + # (UIT No. 143 17.XI.1977) and not 23 September (UIT No. 141 13.IX.1977). + # UIT is the Operational Bulletin of International Telecommunication Union. + ++# From Roozbeh Pournader (2025-03-18): ++# ... the exact time of Iran's transition from +0400 to +0330 ... was Friday ++# 1357/8/19 AP=1978-11-10. Here's a newspaper clip from the Ettela'at ++# newspaper, dated 1357/8/14 AP=1978-11-05, translated from Persian ++# (at https://w.wiki/DUEY): ++# Following the government's decision about returning the official time ++# to the previous status, the spokesperson for the Ministry of Energy ++# announced today: At the hour 24 of Friday 19th of Aban (=1978-11-10), ++# the country's time will be pulled back half an hour. ++# + # From Roozbeh Pournader (2003-03-15): + # This is an English translation of what I just found (originally in Persian). + # The Gregorian dates in brackets are mine: +@@ -1650,7 +1660,7 @@ Rule Iran 2021 2022 - Sep 21 24:00 0 - + Zone Asia/Tehran 3:25:44 - LMT 1916 + 3:25:44 - TMT 1935 Jun 13 # Tehran Mean Time + 3:30 Iran +0330/+0430 1977 Oct 20 24:00 +- 4:00 Iran +04/+05 1979 ++ 4:00 Iran +04/+05 1978 Nov 10 24:00 + 3:30 Iran +0330/+0430 + + +diff --git a/jdk/make/data/tzdata/northamerica b/jdk/make/data/tzdata/northamerica +index e735d43e3..b0687f0fc 100644 +--- a/jdk/make/data/tzdata/northamerica ++++ b/jdk/make/data/tzdata/northamerica +@@ -1634,6 +1634,15 @@ Zone America/Moncton -4:19:08 - LMT 1883 Dec 9 + # For more on Orillia, see: Daubs K. Bold attempt at daylight saving + # time became a comic failure in Orillia. Toronto Star 2017-07-08. + # https://www.thestar.com/news/insight/2017/07/08/bold-attempt-at-daylight-saving-time-became-a-comic-failure-in-orillia.html ++# From Paul Eggert (2025-03-20): ++# Also see the 1912-06-17 front page of The Evening Sunbeam, ++# reproduced in: Richardson M. "Daylight saving was a confusing ++# time in Orillia" in the 2025-03-15 Orillia Matters. Richardson writes, ++# "The first Sunday after the switch was made, [DST proponent and ++# Orillia mayor William Sword] Frost walked into church an hour late. ++# This became a symbol of the downfall of daylight saving in Orillia." ++# The mayor became known as "Daylight Bill". ++# https://www.orilliamatters.com/local-news/column-daylight-saving-was-a-confusing-time-in-orillia-10377529 + + # From Mark Brader (2010-03-06): + # +diff --git a/jdk/make/data/tzdata/southamerica b/jdk/make/data/tzdata/southamerica +index 8fc2bf8ce..3b0b65be4 100644 +--- a/jdk/make/data/tzdata/southamerica ++++ b/jdk/make/data/tzdata/southamerica +@@ -1269,35 +1269,45 @@ Zone America/Rio_Branco -4:31:12 - LMT 1914 + # dates to 2014. + # DST End: last Saturday of April 2014 (Sun 27 Apr 2014 03:00 UTC) + # DST Start: first Saturday of September 2014 (Sun 07 Sep 2014 04:00 UTC) +-# http://www.diariooficial.interior.gob.cl//media/2014/02/19/do-20140219.pdf ++# From Tim Parenti (2025-03-22): ++# Decreto 307 of 2014 of the Ministry of the Interior and Public Security, ++# promulgated 2014-01-30 and published 2014-02-19: ++# https://www.diariooficial.interior.gob.cl/media/2014/02/19/do-20140219.pdf#page=1 ++# https://www.bcn.cl/leychile/navegar?idNorma=1059557 + + # From Eduardo Romero Urra (2015-03-03): + # Today has been published officially that Chile will use the DST time + # permanently until March 25 of 2017 +-# http://www.diariooficial.interior.gob.cl/media/2015/03/03/1-large.jpg +-# +-# From Paul Eggert (2015-03-03): +-# For now, assume that the extension will persist indefinitely. ++# From Tim Parenti (2025-03-22): ++# Decreto 106 of 2015 of the Ministry of the Interior and Public Security, ++# promulgated 2015-01-27 and published 2015-03-03: ++# https://www.diariooficial.interior.gob.cl/media/2015/03/03/do-20150303.pdf#page=1 ++# https://www.bcn.cl/leychile/navegar?idNorma=1075157 + + # From Juan Correa (2016-03-18): +-# The decree regarding DST has been published in today's Official Gazette: +-# http://www.diariooficial.interior.gob.cl/versiones-anteriores/do/20160318/ +-# http://www.leychile.cl/Navegar?idNorma=1088502 ++# The decree regarding DST has been published in today's Official Gazette... + # It does consider the second Saturday of May and August as the dates + # for the transition; and it lists DST dates until 2019, but I think + # this scheme will stick. +-# + # From Paul Eggert (2016-03-18): +-# For now, assume the pattern holds for the indefinite future. + # The decree says transitions occur at 24:00; in practice this appears + # to mean 24:00 mainland time, not 24:00 local time, so that Easter + # Island is always two hours behind the mainland. ++# From Tim Parenti (2025-03-22): ++# Decreto 253 of 2016 of the Ministry of the Interior and Public Security, ++# promulgated 2016-03-16 and published 2016-03-18. ++# https://www.diariooficial.interior.gob.cl/media/2016/03/18/do-20160318.pdf#page=1 ++# https://www.bcn.cl/leychile/navegar?idNorma=1088502 + + # From Juan Correa (2016-12-04): + # Magallanes region ... will keep DST (UTC -3) all year round.... + # http://www.soychile.cl/Santiago/Sociedad/2016/12/04/433428/Bachelet-firmo-el-decreto-para-establecer-un-horario-unico-para-la-Region-de-Magallanes.aspx +-# From Deborah Goldsmith (2017-01-19): +-# http://www.diariooficial.interior.gob.cl/publicaciones/2017/01/17/41660/01/1169626.pdf ++# From Tim Parenti (2025-03-22), via Deborah Goldsmith (2017-01-19): ++# Decreto 1820 of 2016 of the Ministry of the Interior and Public Security, ++# promulgated 2016-12-02 and published 2017-01-17: ++# https://www.diariooficial.interior.gob.cl/publicaciones/2017/01/17/41660/01/1169626.pdf ++# https://www.bcn.cl/leychile/Navegar?idNorma=1099217 ++# Model this as a change to standard offset effective 2016-12-04. + + # From Juan Correa (2018-08-13): + # As of moments ago, the Ministry of Energy in Chile has announced the new +@@ -1316,13 +1326,20 @@ Zone America/Rio_Branco -4:31:12 - LMT 1914 + # https://twitter.com/MinEnergia/status/1029009354001973248 + # "We will keep the new time policy unchanged for at least the next 4 years." + # So we extend the new rules on Saturdays at 24:00 mainland time indefinitely. +-# From Juan Correa (2019-02-04): +-# http://www.diariooficial.interior.gob.cl/publicaciones/2018/11/23/42212/01/1498738.pdf ++# From Tim Parenti (2025-03-22), via Juan Correa (2019-02-04): ++# Decreto 1286 of 2018 of the Ministry of the Interior and Public Security, ++# promulgated 2018-09-21 and published 2018-11-23: ++# https://www.diariooficial.interior.gob.cl/publicaciones/2018/11/23/42212/01/1498738.pdf ++# https://www.bcn.cl/leychile/Navegar?idNorma=1125760 + + # From Juan Correa (2022-04-02): + # I found there was a decree published last Thursday that will keep +-# Magallanes region to UTC -3 "indefinitely". The decree is available at ++# Magallanes region to UTC -3 "indefinitely". ++# From Tim Parenti (2025-03-22): ++# Decreto 143 of 2022 of the Ministry of the Interior and Public Security, ++# promulgated 2022-03-29 and published 2022-03-31: + # https://www.diariooficial.interior.gob.cl/publicaciones/2022/03/31/43217-B/01/2108910.pdf ++# https://www.bcn.cl/leychile/Navegar?idNorma=1174342 + + # From Juan Correa (2022-08-09): + # the Internal Affairs Ministry (Ministerio del Interior) informed DST +@@ -1331,13 +1348,36 @@ Zone America/Rio_Branco -4:31:12 - LMT 1914 + # will keep UTC -3 "indefinitely"... This is because on September 4th + # we will have a voting whether to approve a new Constitution. + # +-# From Eduardo Romero Urra (2022-08-17): ++# From Tim Parenti (2025-03-22), via Eduardo Romero Urra (2022-08-17): ++# Decreto 224 of 2022 of the Ministry of the Interior and Public Security, ++# promulgated 2022-07-14 and published 2022-08-13: + # https://www.diariooficial.interior.gob.cl/publicaciones/2022/08/13/43327/01/2172567.pdf ++# https://www.bcn.cl/leychile/navegar?idNorma=1179983 + # + # From Paul Eggert (2022-08-17): + # Although the presidential decree stops at fall 2026, assume that + # similar DST rules will continue thereafter. + ++# From Paul Eggert (2025-01-15): ++# Diario Regional Aysén's Sebastián Martel reports that 94% of Aysén ++# citizens polled in November favored changing the rules from ++# -04/-03-with-DST to -03 all year... ++# https://www.diarioregionalaysen.cl/noticia/actualidad/2024/12/presentan-decision-que-gano-la-votacion-sobre-el-cambio-del-huso-horario-en-aysen ++# ++# From Yonathan Dossow (2025-03-20): ++# [T]oday we have more confirmation of the change. [Aysén] region will keep ++# UTC-3 all year... ++# https://www.cnnchile.com/pais/region-de-aysen-mantendra-horario-de-verano-todo-el-ano_20250320/ ++# https://www.latercera.com/nacional/noticia/tras-consulta-ciudadana-region-de-aysen-mantendra-el-horario-de-verano-durante-todo-el-ano/ ++# https://x.com/min_interior/status/1902692504270672098 ++# ++# From Tim Parenti (2025-03-22), via Eduardo Romero Urra (2025-03-20): ++# Decreto 93 of 2025 of the Ministry of the Interior and Public Security, ++# promulgated 2025-03-11 and published 2025-03-20: ++# https://www.diariooficial.interior.gob.cl/publicaciones/2025/03/20/44104/01/2624263.pdf ++# https://www.bcn.cl/leychile/Navegar?idNorma=1211955 ++# Model this as a change to standard offset effective 2025-03-20. ++ + # Rule NAME FROM TO - IN ON AT SAVE LETTER/S + Rule Chile 1927 1931 - Sep 1 0:00 1:00 - + Rule Chile 1928 1932 - Apr 1 0:00 0 - +@@ -1394,6 +1434,20 @@ Zone America/Santiago -4:42:45 - LMT 1890 + -5:00 1:00 -04 1947 Mar 31 24:00 + -5:00 - -05 1947 May 21 23:00 + -4:00 Chile -04/-03 ++Zone America/Coyhaique -4:48:16 - LMT 1890 ++ -4:42:45 - SMT 1910 Jan 10 ++ -5:00 - -05 1916 Jul 1 ++ -4:42:45 - SMT 1918 Sep 10 ++ -4:00 - -04 1919 Jul 1 ++ -4:42:45 - SMT 1927 Sep 1 ++ -5:00 Chile -05/-04 1932 Sep 1 ++ -4:00 - -04 1942 Jun 1 ++ -5:00 - -05 1942 Aug 1 ++ -4:00 - -04 1946 Aug 28 24:00 ++ -5:00 1:00 -04 1947 Mar 31 24:00 ++ -5:00 - -05 1947 May 21 23:00 ++ -4:00 Chile -04/-03 2025 Mar 20 ++ -3:00 - -03 + Zone America/Punta_Arenas -4:43:40 - LMT 1890 + -4:42:45 - SMT 1910 Jan 10 + -5:00 - -05 1916 Jul 1 +diff --git a/jdk/make/data/tzdata/zone.tab b/jdk/make/data/tzdata/zone.tab +index e7a4868c3..c8fc60104 100644 +--- a/jdk/make/data/tzdata/zone.tab ++++ b/jdk/make/data/tzdata/zone.tab +@@ -162,7 +162,8 @@ CH +4723+00832 Europe/Zurich + CI +0519-00402 Africa/Abidjan + CK -2114-15946 Pacific/Rarotonga + CL -3327-07040 America/Santiago most of Chile +-CL -5309-07055 America/Punta_Arenas Region of Magallanes ++CL -4534-07204 America/Coyhaique Aysen Region ++CL -5309-07055 America/Punta_Arenas Magallanes Region + CL -2709-10926 Pacific/Easter Easter Island + CM +0403+00942 Africa/Douala + CN +3114+12128 Asia/Shanghai Beijing Time +diff --git a/jdk/test/java/util/TimeZone/TimeZoneData/VERSION b/jdk/test/java/util/TimeZone/TimeZoneData/VERSION +index 5159b3786..750d9fae2 100644 +--- a/jdk/test/java/util/TimeZone/TimeZoneData/VERSION ++++ b/jdk/test/java/util/TimeZone/TimeZoneData/VERSION +@@ -1 +1 @@ +-tzdata2025a ++tzdata2025b +diff --git a/jdk/test/sun/util/calendar/zi/tzdata/VERSION b/jdk/test/sun/util/calendar/zi/tzdata/VERSION +index 9c056fac3..4bd54efbc 100644 +--- a/jdk/test/sun/util/calendar/zi/tzdata/VERSION ++++ b/jdk/test/sun/util/calendar/zi/tzdata/VERSION +@@ -21,4 +21,4 @@ + # or visit www.oracle.com if you need additional information or have any + # questions. + # +-tzdata2025a ++tzdata2025b +diff --git a/jdk/test/sun/util/calendar/zi/tzdata/asia b/jdk/test/sun/util/calendar/zi/tzdata/asia +index 73cccd39a..d52e8de87 100644 +--- a/jdk/test/sun/util/calendar/zi/tzdata/asia ++++ b/jdk/test/sun/util/calendar/zi/tzdata/asia +@@ -1523,6 +1523,16 @@ Zone Asia/Jayapura 9:22:48 - LMT 1932 Nov + # (UIT No. 143 17.XI.1977) and not 23 September (UIT No. 141 13.IX.1977). + # UIT is the Operational Bulletin of International Telecommunication Union. + ++# From Roozbeh Pournader (2025-03-18): ++# ... the exact time of Iran's transition from +0400 to +0330 ... was Friday ++# 1357/8/19 AP=1978-11-10. Here's a newspaper clip from the Ettela'at ++# newspaper, dated 1357/8/14 AP=1978-11-05, translated from Persian ++# (at https://w.wiki/DUEY): ++# Following the government's decision about returning the official time ++# to the previous status, the spokesperson for the Ministry of Energy ++# announced today: At the hour 24 of Friday 19th of Aban (=1978-11-10), ++# the country's time will be pulled back half an hour. ++# + # From Roozbeh Pournader (2003-03-15): + # This is an English translation of what I just found (originally in Persian). + # The Gregorian dates in brackets are mine: +@@ -1650,7 +1660,7 @@ Rule Iran 2021 2022 - Sep 21 24:00 0 - + Zone Asia/Tehran 3:25:44 - LMT 1916 + 3:25:44 - TMT 1935 Jun 13 # Tehran Mean Time + 3:30 Iran +0330/+0430 1977 Oct 20 24:00 +- 4:00 Iran +04/+05 1979 ++ 4:00 Iran +04/+05 1978 Nov 10 24:00 + 3:30 Iran +0330/+0430 + + +diff --git a/jdk/test/sun/util/calendar/zi/tzdata/northamerica b/jdk/test/sun/util/calendar/zi/tzdata/northamerica +index e735d43e3..b0687f0fc 100644 +--- a/jdk/test/sun/util/calendar/zi/tzdata/northamerica ++++ b/jdk/test/sun/util/calendar/zi/tzdata/northamerica +@@ -1634,6 +1634,15 @@ Zone America/Moncton -4:19:08 - LMT 1883 Dec 9 + # For more on Orillia, see: Daubs K. Bold attempt at daylight saving + # time became a comic failure in Orillia. Toronto Star 2017-07-08. + # https://www.thestar.com/news/insight/2017/07/08/bold-attempt-at-daylight-saving-time-became-a-comic-failure-in-orillia.html ++# From Paul Eggert (2025-03-20): ++# Also see the 1912-06-17 front page of The Evening Sunbeam, ++# reproduced in: Richardson M. "Daylight saving was a confusing ++# time in Orillia" in the 2025-03-15 Orillia Matters. Richardson writes, ++# "The first Sunday after the switch was made, [DST proponent and ++# Orillia mayor William Sword] Frost walked into church an hour late. ++# This became a symbol of the downfall of daylight saving in Orillia." ++# The mayor became known as "Daylight Bill". ++# https://www.orilliamatters.com/local-news/column-daylight-saving-was-a-confusing-time-in-orillia-10377529 + + # From Mark Brader (2010-03-06): + # +diff --git a/jdk/test/sun/util/calendar/zi/tzdata/southamerica b/jdk/test/sun/util/calendar/zi/tzdata/southamerica +index 8fc2bf8ce..3b0b65be4 100644 +--- a/jdk/test/sun/util/calendar/zi/tzdata/southamerica ++++ b/jdk/test/sun/util/calendar/zi/tzdata/southamerica +@@ -1269,35 +1269,45 @@ Zone America/Rio_Branco -4:31:12 - LMT 1914 + # dates to 2014. + # DST End: last Saturday of April 2014 (Sun 27 Apr 2014 03:00 UTC) + # DST Start: first Saturday of September 2014 (Sun 07 Sep 2014 04:00 UTC) +-# http://www.diariooficial.interior.gob.cl//media/2014/02/19/do-20140219.pdf ++# From Tim Parenti (2025-03-22): ++# Decreto 307 of 2014 of the Ministry of the Interior and Public Security, ++# promulgated 2014-01-30 and published 2014-02-19: ++# https://www.diariooficial.interior.gob.cl/media/2014/02/19/do-20140219.pdf#page=1 ++# https://www.bcn.cl/leychile/navegar?idNorma=1059557 + + # From Eduardo Romero Urra (2015-03-03): + # Today has been published officially that Chile will use the DST time + # permanently until March 25 of 2017 +-# http://www.diariooficial.interior.gob.cl/media/2015/03/03/1-large.jpg +-# +-# From Paul Eggert (2015-03-03): +-# For now, assume that the extension will persist indefinitely. ++# From Tim Parenti (2025-03-22): ++# Decreto 106 of 2015 of the Ministry of the Interior and Public Security, ++# promulgated 2015-01-27 and published 2015-03-03: ++# https://www.diariooficial.interior.gob.cl/media/2015/03/03/do-20150303.pdf#page=1 ++# https://www.bcn.cl/leychile/navegar?idNorma=1075157 + + # From Juan Correa (2016-03-18): +-# The decree regarding DST has been published in today's Official Gazette: +-# http://www.diariooficial.interior.gob.cl/versiones-anteriores/do/20160318/ +-# http://www.leychile.cl/Navegar?idNorma=1088502 ++# The decree regarding DST has been published in today's Official Gazette... + # It does consider the second Saturday of May and August as the dates + # for the transition; and it lists DST dates until 2019, but I think + # this scheme will stick. +-# + # From Paul Eggert (2016-03-18): +-# For now, assume the pattern holds for the indefinite future. + # The decree says transitions occur at 24:00; in practice this appears + # to mean 24:00 mainland time, not 24:00 local time, so that Easter + # Island is always two hours behind the mainland. ++# From Tim Parenti (2025-03-22): ++# Decreto 253 of 2016 of the Ministry of the Interior and Public Security, ++# promulgated 2016-03-16 and published 2016-03-18. ++# https://www.diariooficial.interior.gob.cl/media/2016/03/18/do-20160318.pdf#page=1 ++# https://www.bcn.cl/leychile/navegar?idNorma=1088502 + + # From Juan Correa (2016-12-04): + # Magallanes region ... will keep DST (UTC -3) all year round.... + # http://www.soychile.cl/Santiago/Sociedad/2016/12/04/433428/Bachelet-firmo-el-decreto-para-establecer-un-horario-unico-para-la-Region-de-Magallanes.aspx +-# From Deborah Goldsmith (2017-01-19): +-# http://www.diariooficial.interior.gob.cl/publicaciones/2017/01/17/41660/01/1169626.pdf ++# From Tim Parenti (2025-03-22), via Deborah Goldsmith (2017-01-19): ++# Decreto 1820 of 2016 of the Ministry of the Interior and Public Security, ++# promulgated 2016-12-02 and published 2017-01-17: ++# https://www.diariooficial.interior.gob.cl/publicaciones/2017/01/17/41660/01/1169626.pdf ++# https://www.bcn.cl/leychile/Navegar?idNorma=1099217 ++# Model this as a change to standard offset effective 2016-12-04. + + # From Juan Correa (2018-08-13): + # As of moments ago, the Ministry of Energy in Chile has announced the new +@@ -1316,13 +1326,20 @@ Zone America/Rio_Branco -4:31:12 - LMT 1914 + # https://twitter.com/MinEnergia/status/1029009354001973248 + # "We will keep the new time policy unchanged for at least the next 4 years." + # So we extend the new rules on Saturdays at 24:00 mainland time indefinitely. +-# From Juan Correa (2019-02-04): +-# http://www.diariooficial.interior.gob.cl/publicaciones/2018/11/23/42212/01/1498738.pdf ++# From Tim Parenti (2025-03-22), via Juan Correa (2019-02-04): ++# Decreto 1286 of 2018 of the Ministry of the Interior and Public Security, ++# promulgated 2018-09-21 and published 2018-11-23: ++# https://www.diariooficial.interior.gob.cl/publicaciones/2018/11/23/42212/01/1498738.pdf ++# https://www.bcn.cl/leychile/Navegar?idNorma=1125760 + + # From Juan Correa (2022-04-02): + # I found there was a decree published last Thursday that will keep +-# Magallanes region to UTC -3 "indefinitely". The decree is available at ++# Magallanes region to UTC -3 "indefinitely". ++# From Tim Parenti (2025-03-22): ++# Decreto 143 of 2022 of the Ministry of the Interior and Public Security, ++# promulgated 2022-03-29 and published 2022-03-31: + # https://www.diariooficial.interior.gob.cl/publicaciones/2022/03/31/43217-B/01/2108910.pdf ++# https://www.bcn.cl/leychile/Navegar?idNorma=1174342 + + # From Juan Correa (2022-08-09): + # the Internal Affairs Ministry (Ministerio del Interior) informed DST +@@ -1331,13 +1348,36 @@ Zone America/Rio_Branco -4:31:12 - LMT 1914 + # will keep UTC -3 "indefinitely"... This is because on September 4th + # we will have a voting whether to approve a new Constitution. + # +-# From Eduardo Romero Urra (2022-08-17): ++# From Tim Parenti (2025-03-22), via Eduardo Romero Urra (2022-08-17): ++# Decreto 224 of 2022 of the Ministry of the Interior and Public Security, ++# promulgated 2022-07-14 and published 2022-08-13: + # https://www.diariooficial.interior.gob.cl/publicaciones/2022/08/13/43327/01/2172567.pdf ++# https://www.bcn.cl/leychile/navegar?idNorma=1179983 + # + # From Paul Eggert (2022-08-17): + # Although the presidential decree stops at fall 2026, assume that + # similar DST rules will continue thereafter. + ++# From Paul Eggert (2025-01-15): ++# Diario Regional Aysén's Sebastián Martel reports that 94% of Aysén ++# citizens polled in November favored changing the rules from ++# -04/-03-with-DST to -03 all year... ++# https://www.diarioregionalaysen.cl/noticia/actualidad/2024/12/presentan-decision-que-gano-la-votacion-sobre-el-cambio-del-huso-horario-en-aysen ++# ++# From Yonathan Dossow (2025-03-20): ++# [T]oday we have more confirmation of the change. [Aysén] region will keep ++# UTC-3 all year... ++# https://www.cnnchile.com/pais/region-de-aysen-mantendra-horario-de-verano-todo-el-ano_20250320/ ++# https://www.latercera.com/nacional/noticia/tras-consulta-ciudadana-region-de-aysen-mantendra-el-horario-de-verano-durante-todo-el-ano/ ++# https://x.com/min_interior/status/1902692504270672098 ++# ++# From Tim Parenti (2025-03-22), via Eduardo Romero Urra (2025-03-20): ++# Decreto 93 of 2025 of the Ministry of the Interior and Public Security, ++# promulgated 2025-03-11 and published 2025-03-20: ++# https://www.diariooficial.interior.gob.cl/publicaciones/2025/03/20/44104/01/2624263.pdf ++# https://www.bcn.cl/leychile/Navegar?idNorma=1211955 ++# Model this as a change to standard offset effective 2025-03-20. ++ + # Rule NAME FROM TO - IN ON AT SAVE LETTER/S + Rule Chile 1927 1931 - Sep 1 0:00 1:00 - + Rule Chile 1928 1932 - Apr 1 0:00 0 - +@@ -1394,6 +1434,20 @@ Zone America/Santiago -4:42:45 - LMT 1890 + -5:00 1:00 -04 1947 Mar 31 24:00 + -5:00 - -05 1947 May 21 23:00 + -4:00 Chile -04/-03 ++Zone America/Coyhaique -4:48:16 - LMT 1890 ++ -4:42:45 - SMT 1910 Jan 10 ++ -5:00 - -05 1916 Jul 1 ++ -4:42:45 - SMT 1918 Sep 10 ++ -4:00 - -04 1919 Jul 1 ++ -4:42:45 - SMT 1927 Sep 1 ++ -5:00 Chile -05/-04 1932 Sep 1 ++ -4:00 - -04 1942 Jun 1 ++ -5:00 - -05 1942 Aug 1 ++ -4:00 - -04 1946 Aug 28 24:00 ++ -5:00 1:00 -04 1947 Mar 31 24:00 ++ -5:00 - -05 1947 May 21 23:00 ++ -4:00 Chile -04/-03 2025 Mar 20 ++ -3:00 - -03 + Zone America/Punta_Arenas -4:43:40 - LMT 1890 + -4:42:45 - SMT 1910 Jan 10 + -5:00 - -05 1916 Jul 1 +diff --git a/jdk/test/sun/util/calendar/zi/tzdata/zone.tab b/jdk/test/sun/util/calendar/zi/tzdata/zone.tab +index e7a4868c3..c8fc60104 100644 +--- a/jdk/test/sun/util/calendar/zi/tzdata/zone.tab ++++ b/jdk/test/sun/util/calendar/zi/tzdata/zone.tab +@@ -162,7 +162,8 @@ CH +4723+00832 Europe/Zurich + CI +0519-00402 Africa/Abidjan + CK -2114-15946 Pacific/Rarotonga + CL -3327-07040 America/Santiago most of Chile +-CL -5309-07055 America/Punta_Arenas Region of Magallanes ++CL -4534-07204 America/Coyhaique Aysen Region ++CL -5309-07055 America/Punta_Arenas Magallanes Region + CL -2709-10926 Pacific/Easter Easter Island + CM +0403+00942 Africa/Douala + CN +3114+12128 Asia/Shanghai Beijing Time +-- + diff --git a/GCC-12-reports-some-compiler-warnings.patch b/GCC-12-reports-some-compiler-warnings.patch index 60c289f0f9a44e8bff745f0cccda3961da40c168..4b8bbd21853ffeb05bf9934c4abec8273e42b4fe 100644 --- a/GCC-12-reports-some-compiler-warnings.patch +++ b/GCC-12-reports-some-compiler-warnings.patch @@ -18,24 +18,6 @@ index 7dde7f096..d122f0eae 100644 ifeq ($(USE_CLANG),) # Since GCC 4.3, -Wconversion has changed its meanings to warn these implicit -diff --git a/hotspot/src/share/vm/opto/type.cpp b/hotspot/src/share/vm/opto/type.cpp -index 58572f137..92d4e6b70 100644 ---- a/hotspot/src/share/vm/opto/type.cpp -+++ b/hotspot/src/share/vm/opto/type.cpp -@@ -2553,8 +2553,11 @@ TypeOopPtr::TypeOopPtr(TYPES t, PTR ptr, ciKlass* k, bool xk, ciObject* o, int o - _offset >= InstanceMirrorKlass::offset_of_static_fields()) { - // Static fields - assert(o != NULL, "must be constant"); -- ciInstanceKlass* k = o->as_instance()->java_lang_Class_klass()->as_instance_klass(); -- ciField* field = k->get_field_by_offset(_offset, true); -+ ciField* field = NULL; -+ if (o != NULL) { -+ ciInstanceKlass* k = o->as_instance()->java_lang_Class_klass()->as_instance_klass(); -+ field = k->get_field_by_offset(_offset, true); -+ } - assert(field != NULL, "missing field"); - BasicType basic_elem_type = field->layout_type(); - _is_ptr_to_narrowoop = UseCompressedOops && (basic_elem_type == T_OBJECT || -- 2.22.0 diff --git a/add-missing-test-case.patch b/add-missing-test-case.patch index 280da923823eee16f759c2218e8ea0b7f0f5c584..b59b82035bbc246a48c245fb3dd2a1a1485460ae 100644 --- a/add-missing-test-case.patch +++ b/add-missing-test-case.patch @@ -91,7 +91,7 @@ index 00000000..9b614024 --- /dev/null +++ b/version.txt @@ -0,0 +1 @@ -+8.442.8.0.13 ++8.452.8.0.13 -- 2.23.0 diff --git a/add-sw_64-support.patch b/add-sw_64-support.patch new file mode 100644 index 0000000000000000000000000000000000000000..8cb2f17c68d2698d65cdecde11389bc143fe369f --- /dev/null +++ b/add-sw_64-support.patch @@ -0,0 +1,82748 @@ +diff --git a/Changelog.md b/Changelog.md +new file mode 100644 +index 0000000000..4dec164a35 +--- /dev/null ++++ b/Changelog.md +@@ -0,0 +1,26 @@ ++swjdk8u312-sw1.3.1(20240914)版主要修改 ++1.优化byte,short类型的arraycopy ++2.优化加负立即数 ++3.优化浮点比较 ++4.新增sun.misc.Unsafe.copyMemory的intrinsic实现 ++5.优化UseCRC32Intrinsics ++6.优化反序列化 ++7.修复slowdebug版本开启-XX:+VerifyOops报错问题 ++8.修复Truncate.java报SIGBUS问题 ++9.优化rsa ++10.优化MembarRelease ++ ++swjdk8u312-sw1.3.0(20240328)版主要修改 ++1.8A与6B代码同源，通过读取cpuinfo自动适配8A ++2.实现部分Core4新增指令优化 ++ ++swjdk8u312-sw1.2.0(20240304)版主要修改： ++1.按照6B平台本地方法栈帧结构，实现NMT及JFR； ++2.解决hadoop集群测试报出的偶发IllegalMonitorStateExeption错; ++3.解决jdk stram NullPointerException错，添加2处memb指令(UseNecessaryMembar，使得6B平台SPECjvm以及SPECjbb的Max-Jops和critical-Jops下降约4%)； ++4.增加ReservedCodeCacheSize大小到240M，防止发生性能异常下降; ++ ++swjdk8u312-sw1.1.0(20230710)修改: ++1. 实现兼容8A的锁序列(commit id:afbe8497c741845149eb41ddb9a7cd6f0910eff8); ++2. lldx指令前删除无用的memb指令(commit id:57edcc5c6ad4e93255054e24ae8b5e3bf5e934c0). ++ +diff --git a/README_SW64 b/README_SW64 +new file mode 100644 +index 0000000000..d2689355b8 +--- /dev/null ++++ b/README_SW64 +@@ -0,0 +1,18 @@ ++README: ++ ++Simple Build Instructions: ++ ++ 1. If you don't have a swjdk8 install it, ++ Add the /bin directory of this installation to your PATH environment variable. ++ ++ 2. Configure the build: ++ bash ./native_configure_sw64 release ++ If you want to build debug swjdk use "bash native_configure_sw64 slowdebug". ++ ++ 3. Build the OpenJDK: ++ make all ++ The resulting JDK image should be found in build/*/images/j2sdk-image. ++If the build environment no git, you must do "bash version_patch.sh" on the environment has git to get the git id, ++then copy the swjdk8u src to the target envirinment. ++ 1. bash configure --disable-zip-debug-info --with-debug-level=release(slowdebug) ++ 2. make all +diff --git a/READYJ b/READYJ +new file mode 100644 +index 0000000000..34a4813a17 +--- /dev/null ++++ b/READYJ +@@ -0,0 +1,16 @@ ++Read me for cross compile, for native compile, see README_SW64 ++ ++configure: ++>bash cross_swcompile_clean ++this will gen release&slowdebug n&c configuration in build dir ++ ++gen ide: ++>bear make CONF=sw64-slowdebug-c LOG=debug hotspot ++then open compile_commands.json ++ ++make: ++mount and make sure dirs are corresponds and same ++modify ip/n ip/c in cross_mk to use your c or n version sw ++copy a j2sdk-image-sw-n and j2sdk-image-sw-c to your build root, then ++>make -f cross_mk c lvl=release ++this will make hotspot for sw release and copy result to j2sdk-image-sw-c, same for n and slowdebug +diff --git a/THIRD_PARTY_README b/THIRD_PARTY_README +index f9aea78d64..975fe94fef 100644 +--- a/THIRD_PARTY_README ++++ b/THIRD_PARTY_README +@@ -3043,14 +3043,14 @@ performance, or use of this material. + + ------------------------------------------------------------------------------- + +-%% This notice is provided with respect to zlib v1.3.1, which may be included ++%% This notice is provided with respect to zlib v1.2.13, which may be included + with JRE 8, JDK 8, and OpenJDK 8. + + --- begin of LICENSE --- + +- version 1.3.1, January 22, 2024 ++ version 1.2.13, October 13th, 2022 + +- Copyright (C) 1995-2024 Jean-loup Gailly and Mark Adler ++ Copyright (C) 1995-2022 Jean-loup Gailly and Mark Adler + + This software is provided 'as-is', without any express or implied + warranty. In no event will the authors be held liable for any damages +diff --git a/c4_cross_swcompile b/c4_cross_swcompile +new file mode 100755 +index 0000000000..36d240462f +--- /dev/null ++++ b/c4_cross_swcompile +@@ -0,0 +1,63 @@ ++#!/bin/bash ++ ++# JDK_DIR can not cross make, because our cross_compiler is not regular sys-root. ++# Some include files use x86_64's include files in jdk directory, so it leads to ++# some macros are not correct. ++# I suggest to compile images in sw_64 platform, while compile hotspot as cross model. ++ ++ JDK_DIR=${PWD}/build/linux-sw64-normal-server-slowdebug/images/j2sdk-image ++ if [ $# -gt 0 ] ++ then ++ JDK_DIR="$2" ++ fi ++ JVMPATH_DST=${JDK_DIR}/jre/lib/sw64/server ++ ++# $1: debug level (release, fastdebug, slowdebug) ++case "$1" in ++ slowdebug) ++ MYCONF=linux-sw64-normal-server-slowdebug ++ JVMPATH_SRC=${PWD}/build/linux-sw64-normal-server-slowdebug/hotspot/dist/jre/lib/sw64/server ++ JVMPATH_DST=${PWD}/$2/jre/lib/sw64/server ++# JVMPATH_DST=${PWD}/build_native/linux-sw64-normal-server-slowdebug/images/j2sdk-image/jre/lib/sw64/server ++ ;; ++ release) ++ MYCONF=linux-sw64-normal-server-release ++ JVMPATH_SRC=${PWD}/build/linux-sw64-normal-server-release/hotspot/dist/jre/lib/sw64/server ++ JVMPATH_DST=${PWD}/$2/jre/lib/sw64/server ++# JVMPATH_DST=${PWD}/build_native/linux-sw64-normal-server-release/images/j2sdk-image/jre/lib/sw64/server ++ ;; ++ *) ++ echo " Usage:" ++ echo " bash c4_cross_swcompile {release|slowdebug} JDK_DIR" ++ exit 1 ++ ;; ++esac ++ ++# 1) make ++echo make STRIP_POLICY=no_strip POST_STRIP_CMD="" LOG="debug" CONF=${MYCONF} hotspot ++make LOG="debug" CONF=${MYCONF} hotspot ++ ++# 2) copy libjvm.so to JDK directory! (no libjvm.diz, because I have disable-zip-debug-info in cross_swconfigure) ++# JVMPATH_SRC=${PWD}/build/linux-sw64-normal-server-slowdebug/hotspot/dist/jre/lib/sw64/server ++# JVMPATH_DST=${PWD}/build_native/linux-sw64-normal-server-slowdebug/images/j2sdk-image/jre/lib/sw64/server ++ ++echo ++echo ++echo " * =========================================================================================================" ++echo " * Now copy libjvm.so ......" ++echo " * dst is : $JVMPATH_DST " ++echo " * ---------------------------------------------------------------------------------------------------------" ++echo ++if [ -d ${JVMPATH_DST} ] ; then ++ echo " * cp -f ${JVMPATH_SRC}/libjvm.debuginfo ${JVMPATH_DST}" ++ cp -f ${JVMPATH_SRC}/libjvm.debuginfo ${JVMPATH_DST} ++ echo " * cp -f ${JVMPATH_SRC}/libjvm.so ${JVMPATH_DST}" ++ cp -f ${JVMPATH_SRC}/libjvm.so ${JVMPATH_DST} ++else ++ echo " Copy FAILED! No corresponding jdk images: ${JVMPATH_DST}" ++fi ++echo ++echo " * ---------------------------------------------------------------------------------------------------------" ++echo " * End of cross compiling hotspot for swjdk8 ." ++echo " * =========================================================================================================" ++echo +diff --git a/c4_cross_swconfigure b/c4_cross_swconfigure +new file mode 100755 +index 0000000000..a8d122cc9f +--- /dev/null ++++ b/c4_cross_swconfigure +@@ -0,0 +1,39 @@ ++#!/bin/bash ++# $1: debug level (release, fastdebug, slowdebug) ++ ++#which is used for 9906 ++#crosscompiler=swgcc710-cross-6c-peak-1 ++ ++#which is used for 9916 ++crosscompiler=swgcc830_cross_tools ++ ++case "$1" in ++ slowdebug) ++ bash configure \ ++ --openjdk-target=sw_64-unknown-linux-gnu \ ++ --with-devkit=/usr/sw/$crosscompiler/usr/ \ ++ --x-includes=/usr/sw/$crosscompiler/usr/include \ ++ --x-libraries=/usr/sw/$crosscompiler/usr/lib \ ++ --with-freetype-include=/usr/sw/$crosscompiler/usr/include/freetype2 \ ++ --with-freetype-lib=/usr/sw/$crosscompiler/usr/lib/sw_64-linux-gnu \ ++ --disable-zip-debug-info \ ++ --with-debug-level=slowdebug \ ++ --disable-ccache ++ ;; ++ release) ++ bash configure \ ++ --openjdk-target=sw_64-unknown-linux-gnu \ ++ --with-devkit=/usr/sw/$crosscompiler/usr/ \ ++ --x-includes=/usr/sw/$crosscompiler/usr/include \ ++ --x-libraries=/usr/sw/$crosscompiler/usr/lib \ ++ --with-freetype-include=/usr/sw/$crosscompiler/usr/include/freetype2 \ ++ --with-freetype-lib=/usr/sw/$crosscompiler/usr/lib/sw_64-linux-gnu \ ++ --disable-zip-debug-info \ ++ --with-debug-level=release \ ++ --disable-ccache ++ ;; ++ *) ++ echo " Usage:" ++ echo " ./c4_cross_swconfigure {release|slowdebug}" ++ ;; ++esac +diff --git a/common/autoconf/build-aux/autoconf-config.guess b/common/autoconf/build-aux/autoconf-config.guess +index 15ee438926..05659616a5 100644 +--- a/common/autoconf/build-aux/autoconf-config.guess ++++ b/common/autoconf/build-aux/autoconf-config.guess +@@ -907,6 +907,9 @@ EOF + if test "$?" = 0 ; then LIBC="libc1" ; else LIBC="" ; fi + echo ${UNAME_MACHINE}-unknown-linux-gnu${LIBC} + exit ;; ++ sw_64:Linux:*:*) ++ echo ${UNAME_MACHINE}-unknown-linux-gnu ++ exit ;; + arm*:Linux:*:*) + eval $set_cc_for_build + if echo __ARM_EABI__ | $CC_FOR_BUILD -E - 2>/dev/null \ +diff --git a/common/autoconf/build-performance.m4 b/common/autoconf/build-performance.m4 +index 8f03538301..4faa0f79bc 100644 +--- a/common/autoconf/build-performance.m4 ++++ b/common/autoconf/build-performance.m4 +@@ -32,6 +32,9 @@ AC_DEFUN([BPERF_CHECK_CORES], + if test -f /proc/cpuinfo; then + # Looks like a Linux (or cygwin) system + NUM_CORES=`cat /proc/cpuinfo | grep -c processor` ++ if test "$NUM_CORES" -eq "0"; then # for n version os ?? ++ NUM_CORES=`cat /proc/cpuinfo | grep "cpus active" | awk '{ print [$]4 }'` ++ fi + FOUND_CORES=yes + elif test -x /usr/sbin/psrinfo; then + # Looks like a Solaris system +@@ -71,6 +74,9 @@ AC_DEFUN([BPERF_CHECK_MEMORY_SIZE], + if test -f /proc/meminfo; then + # Looks like a Linux (or cygwin) system + MEMORY_SIZE=`cat /proc/meminfo | grep MemTotal | awk '{print [$]2}'` ++ if test "x$OPENJDK_TARGET_CPU_ARCH" = xsw64; then ++ MEMORY_SIZE=`cat /proc/meminfo | grep MemTotal | grep -v PhyMemTotal | awk '{print [$]2}'` ++ fi + MEMORY_SIZE=`expr $MEMORY_SIZE / 1024` + FOUND_MEM=yes + elif test -x /usr/sbin/prtconf; then +diff --git a/common/autoconf/generated-configure.sh b/common/autoconf/generated-configure.sh +index ad3f7f232e..b51bddceb3 100644 +--- a/common/autoconf/generated-configure.sh ++++ b/common/autoconf/generated-configure.sh +@@ -13880,6 +13880,12 @@ test -n "$target_alias" && + VAR_CPU_BITS=64 + VAR_CPU_ENDIAN=little + ;; ++ sw_64) ++ VAR_CPU=sw64 ++ VAR_CPU_ARCH=sw64 ++ VAR_CPU_BITS=64 ++ VAR_CPU_ENDIAN=little ++ ;; + powerpc) + VAR_CPU=ppc + VAR_CPU_ARCH=ppc +@@ -14024,6 +14030,12 @@ $as_echo "$OPENJDK_BUILD_OS-$OPENJDK_BUILD_CPU" >&6; } + VAR_CPU_BITS=64 + VAR_CPU_ENDIAN=little + ;; ++ sw_64) ++ VAR_CPU=sw64 ++ VAR_CPU_ARCH=sw64 ++ VAR_CPU_BITS=64 ++ VAR_CPU_ENDIAN=little ++ ;; + powerpc) + VAR_CPU=ppc + VAR_CPU_ARCH=ppc +@@ -42818,6 +42830,10 @@ fi + ppc ) + # on ppc we don't prevent gcc to omit frame pointer nor strict-aliasing + ;; ++ sw64 ) ++ COMMON_CCXXFLAGS_JDK="$COMMON_CCXXFLAGS_JDK -O2 -mieee -fno-omit-frame-pointer -fno-delete-null-pointer-checks -fno-lifetime-dse" ++ CFLAGS_JDK="${CFLAGS_JDK} -O2 -mieee -fno-strict-aliasing -fno-delete-null-pointer-checks -fno-lifetime-dse" ++ ;; + * ) + CCXXFLAGS_JDK="$CCXXFLAGS_JDK -fno-omit-frame-pointer" + CFLAGS_JDK="${CFLAGS_JDK} -fno-strict-aliasing" +@@ -49141,7 +49157,11 @@ $as_echo "$as_me: The path of FREETYPE_LIB_PATH, which resolves as \"$path\", is + if test "x$OPENJDK_TARGET_OS" = xwindows; then + FREETYPE_LIBS="$FREETYPE_LIB_PATH/freetype.lib" + else ++ if test "x$OPENJDK_TARGET_CPU_ARCH" = xsw64; then ++ FREETYPE_LIBS="-L$FREETYPE_LIB_PATH -lfreetype -lz -lpng" ++ else + FREETYPE_LIBS="-L$FREETYPE_LIB_PATH -lfreetype" ++ fi + fi + fi + +@@ -55348,6 +55368,9 @@ $as_echo_n "checking for memory size... " >&6; } + if test -f /proc/meminfo; then + # Looks like a Linux (or cygwin) system + MEMORY_SIZE=`cat /proc/meminfo | grep MemTotal | awk '{print $2}'` ++ if test "x$OPENJDK_TARGET_CPU_ARCH" = xsw64; then ++ MEMORY_SIZE=`cat /proc/meminfo | grep MemTotal | grep -v PhyMemTotal | awk '{print $2}'` ++ fi + MEMORY_SIZE=`expr $MEMORY_SIZE / 1024` + FOUND_MEM=yes + elif test -x /usr/sbin/prtconf; then +diff --git a/common/autoconf/libraries.m4 b/common/autoconf/libraries.m4 +index 6efae578ea..a13cc38818 100644 +--- a/common/autoconf/libraries.m4 ++++ b/common/autoconf/libraries.m4 +@@ -583,7 +583,11 @@ AC_DEFUN_ONCE([LIB_SETUP_FREETYPE], + if test "x$OPENJDK_TARGET_OS" = xwindows; then + FREETYPE_LIBS="$FREETYPE_LIB_PATH/freetype.lib" + else +- FREETYPE_LIBS="-L$FREETYPE_LIB_PATH -lfreetype" ++ if test "x$OPENJDK_TARGET_CPU_ARCH" = xsw64; then ++ FREETYPE_LIBS="-L$FREETYPE_LIB_PATH -lfreetype -lz -lpng" ++ else ++ FREETYPE_LIBS="-L$FREETYPE_LIB_PATH -lfreetype" ++ fi + fi + fi + +diff --git a/common/autoconf/platform.m4 b/common/autoconf/platform.m4 +index f54942acf2..c5269e3a35 100644 +--- a/common/autoconf/platform.m4 ++++ b/common/autoconf/platform.m4 +@@ -54,6 +54,12 @@ AC_DEFUN([PLATFORM_EXTRACT_VARS_FROM_CPU], + VAR_CPU_BITS=64 + VAR_CPU_ENDIAN=little + ;; ++ sw_64) ++ VAR_CPU=sw64 ++ VAR_CPU_ARCH=sw64 ++ VAR_CPU_BITS=64 ++ VAR_CPU_ENDIAN=little ++ ;; + powerpc) + VAR_CPU=ppc + VAR_CPU_ARCH=ppc +diff --git a/common/autoconf/spec.gmk.in b/common/autoconf/spec.gmk.in +index 9573bb2cbd..3e494f2f8a 100644 +--- a/common/autoconf/spec.gmk.in ++++ b/common/autoconf/spec.gmk.in +@@ -213,7 +213,11 @@ else + endif + + ifneq ($(USER_RELEASE_SUFFIX), ) +- FULL_VERSION=$(RELEASE)-$(USER_RELEASE_SUFFIX)-$(JDK_BUILD_NUMBER) ++ ifeq ($(OPENJDK_BUILD_CPU_ARCH), sw64) ++ FULL_VERSION=$(RELEASE)-$(JDK_BUILD_NUMBER)-$(USER_RELEASE_SUFFIX) ++ else ++ FULL_VERSION=$(RELEASE)-$(USER_RELEASE_SUFFIX)-$(JDK_BUILD_NUMBER) ++ endif + else + FULL_VERSION=$(RELEASE)-$(JDK_BUILD_NUMBER) + endif +diff --git a/corba/THIRD_PARTY_README b/corba/THIRD_PARTY_README +new file mode 100644 +index 0000000000..f26a5f3ec5 +--- /dev/null ++++ b/corba/THIRD_PARTY_README +@@ -0,0 +1,3371 @@ ++DO NOT TRANSLATE OR LOCALIZE. ++----------------------------- ++ ++%% This notice is provided with respect to ASM Bytecode Manipulation ++Framework v5.0.3, which may be included with JRE 8, and JDK 8, and ++OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++Copyright (c) 2000-2011 France T??l??com ++All rights reserved. ++ ++Redistribution and use in source and binary forms, with or without ++modification, are permitted provided that the following conditions ++are met: ++ ++1. Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++2. Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++3. Neither the name of the copyright holders nor the names of its ++ contributors may be used to endorse or promote products derived from ++ this software without specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF ++THE POSSIBILITY OF SUCH DAMAGE. ++ ++--- end of LICENSE --- ++ ++-------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to BSDiff v4.3, which may be ++included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++Copyright 2003-2005 Colin Percival ++All rights reserved ++ ++Redistribution and use in source and binary forms, with or without ++modification, are permitted providing that the following conditions ++are met: ++1. Redistributions of source code must retain the above copyright ++notice, this list of conditions and the following disclaimer. ++2. Redistributions in binary form must reproduce the above copyright ++notice, this list of conditions and the following disclaimer in the ++documentation and/or other materials provided with the distribution. ++ ++THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ARE DISCLAIMED. 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Scott Ananian, Michael Petter ++ ++Permission to use, copy, modify, and distribute this software and its ++documentation for any purpose and without fee is hereby granted, provided ++that the above copyright notice appear in all copies and that both the ++copyright notice and this permission notice and warranty disclaimer appear in ++supporting documentation, and that the names of the authors or their ++employers not be used in advertising or publicity pertaining to distribution of ++the software without specific, written prior permission. ++ ++The authors and their employers disclaim all warranties with regard to ++this software, including all implied warranties of merchantability and fitness. ++In no event shall the authors or their employers be liable for any special, ++indirect or consequential damages or any damages whatsoever resulting from ++loss of use, data or profits, whether in an action of contract, negligence or ++other tortious action, arising out of or in connection with the use or ++performance of this software. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to DejaVu fonts v2.34, which may be ++included with JRE 8, and JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++Fonts are (c) Bitstream (see below). DejaVu changes are in public domain. ++Glyphs imported from Arev fonts are (c) Tavmjong Bah (see below) ++ ++ ++Bitstream Vera Fonts Copyright ++------------------------------ ++ ++Copyright (c) 2003 by Bitstream, Inc. All Rights Reserved. Bitstream Vera is ++a trademark of Bitstream, Inc. ++ ++Permission is hereby granted, free of charge, to any person obtaining a copy ++of the fonts accompanying this license ("Fonts") and associated ++documentation files (the "Font Software"), to reproduce and distribute the ++Font Software, including without limitation the rights to use, copy, merge, ++publish, distribute, and/or sell copies of the Font Software, and to permit ++persons to whom the Font Software is furnished to do so, subject to the ++following conditions: ++ ++The above copyright and trademark notices and this permission notice shall ++be included in all copies of one or more of the Font Software typefaces. ++ ++The Font Software may be modified, altered, or added to, and in particular ++the designs of glyphs or characters in the Fonts may be modified and ++additional glyphs or characters may be added to the Fonts, only if the fonts ++are renamed to names not containing either the words "Bitstream" or the word ++"Vera". ++ ++This License becomes null and void to the extent applicable to Fonts or Font ++Software that has been modified and is distributed under the "Bitstream ++Vera" names. ++ ++The Font Software may be sold as part of a larger software package but no ++copy of one or more of the Font Software typefaces may be sold by itself. ++ ++THE FONT SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++OR IMPLIED, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OF MERCHANTABILITY, ++FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT OF COPYRIGHT, PATENT, ++TRADEMARK, OR OTHER RIGHT. IN NO EVENT SHALL BITSTREAM OR THE GNOME ++FOUNDATION BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, INCLUDING ++ANY GENERAL, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, ++WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF ++THE USE OR INABILITY TO USE THE FONT SOFTWARE OR FROM OTHER DEALINGS IN THE ++FONT SOFTWARE. ++ ++Except as contained in this notice, the names of Gnome, the Gnome ++Foundation, and Bitstream Inc., shall not be used in advertising or ++otherwise to promote the sale, use or other dealings in this Font Software ++without prior written authorization from the Gnome Foundation or Bitstream ++Inc., respectively. For further information, contact: fonts at gnome dot ++org. ++ ++Arev Fonts Copyright ++------------------------------ ++ ++Copyright (c) 2006 by Tavmjong Bah. All Rights Reserved. ++ ++Permission is hereby granted, free of charge, to any person obtaining ++a copy of the fonts accompanying this license ("Fonts") and ++associated documentation files (the "Font Software"), to reproduce ++and distribute the modifications to the Bitstream Vera Font Software, ++including without limitation the rights to use, copy, merge, publish, ++distribute, and/or sell copies of the Font Software, and to permit ++persons to whom the Font Software is furnished to do so, subject to ++the following conditions: ++ ++The above copyright and trademark notices and this permission notice ++shall be included in all copies of one or more of the Font Software ++typefaces. ++ ++The Font Software may be modified, altered, or added to, and in ++particular the designs of glyphs or characters in the Fonts may be ++modified and additional glyphs or characters may be added to the ++Fonts, only if the fonts are renamed to names not containing either ++the words "Tavmjong Bah" or the word "Arev". ++ ++This License becomes null and void to the extent applicable to Fonts ++or Font Software that has been modified and is distributed under the ++"Tavmjong Bah Arev" names. ++ ++The Font Software may be sold as part of a larger software package but ++no copy of one or more of the Font Software typefaces may be sold by ++itself. ++ ++THE FONT SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OF ++MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT ++OF COPYRIGHT, PATENT, TRADEMARK, OR OTHER RIGHT. IN NO EVENT SHALL ++TAVMJONG BAH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++INCLUDING ANY GENERAL, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL ++DAMAGES, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++FROM, OUT OF THE USE OR INABILITY TO USE THE FONT SOFTWARE OR FROM ++OTHER DEALINGS IN THE FONT SOFTWARE. ++ ++Except as contained in this notice, the name of Tavmjong Bah shall not ++be used in advertising or otherwise to promote the sale, use or other ++dealings in this Font Software without prior written authorization ++from Tavmjong Bah. For further information, contact: tavmjong @ free ++. fr. ++ ++TeX Gyre DJV Math ++----------------- ++Fonts are (c) Bitstream (see below). DejaVu changes are in public domain. ++ ++Math extensions done by B. Jackowski, P. Strzelczyk and P. Pianowski ++(on behalf of TeX users groups) are in public domain. ++ ++Letters imported from Euler Fraktur from AMSfonts are (c) American ++Mathematical Society (see below). ++Bitstream Vera Fonts Copyright ++Copyright (c) 2003 by Bitstream, Inc. All Rights Reserved. Bitstream Vera ++is a trademark of Bitstream, Inc. ++ ++Permission is hereby granted, free of charge, to any person obtaining a copy ++of the fonts accompanying this license ("Fonts") and associated documentation ++files (the "Font Software"), to reproduce and distribute the Font Software, ++including without limitation the rights to use, copy, merge, publish, ++distribute, and/or sell copies of the Font Software, and to permit persons ++to whom the Font Software is furnished to do so, subject to the following ++conditions: ++ ++The above copyright and trademark notices and this permission notice ++shall be included in all copies of one or more of the Font Software typefaces. ++ ++The Font Software may be modified, altered, or added to, and in particular ++the designs of glyphs or characters in the Fonts may be modified and ++additional glyphs or characters may be added to the Fonts, only if the ++fonts are renamed to names not containing either the words "Bitstream" ++or the word "Vera". ++ ++This License becomes null and void to the extent applicable to Fonts or ++Font Software that has been modified and is distributed under the ++"Bitstream Vera" names. ++ ++The Font Software may be sold as part of a larger software package but ++no copy of one or more of the Font Software typefaces may be sold by itself. ++ ++THE FONT SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++OR IMPLIED, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OF MERCHANTABILITY, ++FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT OF COPYRIGHT, PATENT, ++TRADEMARK, OR OTHER RIGHT. IN NO EVENT SHALL BITSTREAM OR THE GNOME ++FOUNDATION BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, INCLUDING ++ANY GENERAL, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, ++WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT ++OF THE USE OR INABILITY TO USE THE FONT SOFTWARE OR FROM OTHER DEALINGS IN ++THE FONT SOFTWARE. ++Except as contained in this notice, the names of GNOME, the GNOME ++Foundation, and Bitstream Inc., shall not be used in advertising or ++otherwise to promote the sale, use or other dealings in this Font Software ++without prior written authorization from the GNOME Foundation or ++Bitstream Inc., respectively. ++For further information, contact: fonts at gnome dot org. ++ ++AMSFonts (v. 2.2) copyright ++ ++The PostScript Type 1 implementation of the AMSFonts produced by and ++previously distributed by Blue Sky Research and Y&Y, Inc. are now freely ++available for general use. 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All rights reserved. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Kerberos functionality from ++FundsXpress, INC., which may be included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++ Copyright (C) 1998 by the FundsXpress, INC. ++ ++ All rights reserved. ++ ++ Export of this software from the United States of America may require ++ a specific license from the United States Government. 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It is provided "as is" without express ++ or implied warranty. ++ ++ THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR ++ IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED ++ WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. ++ ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Kronos OpenGL headers, which may be ++included with JDK 8 and OpenJDK 8 source distributions. ++ ++--- begin of LICENSE --- ++ ++ Copyright (c) 2007 The Khronos Group Inc. ++ ++ Permission is hereby granted, free of charge, to any person obtaining a copy ++ of this software and/or associated documentation files (the "Materials"), to ++ deal in the Materials without restriction, including without limitation the ++ rights to use, copy, modify, merge, publish, distribute, sublicense, and/or ++ sell copies of the Materials, and to permit persons to whom the Materials are ++ furnished to do so, subject to the following conditions: ++ ++ The above copyright notice and this permission notice shall be included in all ++ copies or substantial portions of the Materials. ++ ++ THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE ++ AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ++ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, ++ OUT OF OR IN CONNECTION WITH THE MATERIALS OR THE USE OR OTHER DEALINGS IN THE ++ MATERIALS. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% Portions Copyright Eastman Kodak Company 1991-2003 ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to libpng 1.6.39, which may be ++included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++COPYRIGHT NOTICE, DISCLAIMER, and LICENSE ++========================================= ++ ++PNG Reference Library License version 2 ++--------------------------------------- ++ ++Copyright (c) 1995-2022 The PNG Reference Library Authors. ++Copyright (c) 2018-2022 Cosmin Truta ++Copyright (c) 1998-2018 Glenn Randers-Pehrson ++Copyright (c) 1996-1997 Andreas Dilger ++Copyright (c) 1995-1996 Guy Eric Schalnat, Group 42, Inc. ++ ++The software is supplied "as is", without warranty of any kind, ++express or implied, including, without limitation, the warranties ++of merchantability, fitness for a particular purpose, title, and ++non-infringement. In no event shall the Copyright owners, or ++anyone distributing the software, be liable for any damages or ++other liability, whether in contract, tort or otherwise, arising ++from, out of, or in connection with the software, or the use or ++other dealings in the software, even if advised of the possibility ++of such damage. ++ ++Permission is hereby granted to use, copy, modify, and distribute ++this software, or portions hereof, for any purpose, without fee, ++subject to the following restrictions: ++ ++ 1. The origin of this software must not be misrepresented; you ++ must not claim that you wrote the original software. If you ++ use this software in a product, an acknowledgment in the product ++ documentation would be appreciated, but is not required. ++ ++ 2. Altered source versions must be plainly marked as such, and must ++ not be misrepresented as being the original software. ++ ++ 3. This Copyright notice may not be removed or altered from any ++ source or altered source distribution. ++ ++ ++PNG Reference Library License version 1 (for libpng 0.5 through 1.6.35) ++----------------------------------------------------------------------- ++ ++libpng versions 1.0.7, July 1, 2000, through 1.6.35, July 15, 2018 are ++Copyright (c) 2000-2002, 2004, 2006-2018 Glenn Randers-Pehrson, are ++derived from libpng-1.0.6, and are distributed according to the same ++disclaimer and license as libpng-1.0.6 with the following individuals ++added to the list of Contributing Authors: ++ ++ Simon-Pierre Cadieux ++ Eric S. Raymond ++ Mans Rullgard ++ Cosmin Truta ++ Gilles Vollant ++ James Yu ++ Mandar Sahastrabuddhe ++ Google Inc. ++ Vadim Barkov ++ ++and with the following additions to the disclaimer: ++ ++ There is no warranty against interference with your enjoyment of ++ the library or against infringement. There is no warranty that our ++ efforts or the library will fulfill any of your particular purposes ++ or needs. This library is provided with all faults, and the entire ++ risk of satisfactory quality, performance, accuracy, and effort is ++ with the user. ++ ++Some files in the "contrib" directory and some configure-generated ++files that are distributed with libpng have other copyright owners, and ++are released under other open source licenses. ++ ++libpng versions 0.97, January 1998, through 1.0.6, March 20, 2000, are ++Copyright (c) 1998-2000 Glenn Randers-Pehrson, are derived from ++libpng-0.96, and are distributed according to the same disclaimer and ++license as libpng-0.96, with the following individuals added to the ++list of Contributing Authors: ++ ++ Tom Lane ++ Glenn Randers-Pehrson ++ Willem van Schaik ++ ++libpng versions 0.89, June 1996, through 0.96, May 1997, are ++Copyright (c) 1996-1997 Andreas Dilger, are derived from libpng-0.88, ++and are distributed according to the same disclaimer and license as ++libpng-0.88, with the following individuals added to the list of ++Contributing Authors: ++ ++ John Bowler ++ Kevin Bracey ++ Sam Bushell ++ Magnus Holmgren ++ Greg Roelofs ++ Tom Tanner ++ ++Some files in the "scripts" directory have other copyright owners, ++but are released under this license. ++ ++libpng versions 0.5, May 1995, through 0.88, January 1996, are ++Copyright (c) 1995-1996 Guy Eric Schalnat, Group 42, Inc. ++ ++For the purposes of this copyright and license, "Contributing Authors" ++is defined as the following set of individuals: ++ ++ Andreas Dilger ++ Dave Martindale ++ Guy Eric Schalnat ++ Paul Schmidt ++ Tim Wegner ++ ++The PNG Reference Library is supplied "AS IS". The Contributing ++Authors and Group 42, Inc. disclaim all warranties, expressed or ++implied, including, without limitation, the warranties of ++merchantability and of fitness for any purpose. The Contributing ++Authors and Group 42, Inc. assume no liability for direct, indirect, ++incidental, special, exemplary, or consequential damages, which may ++result from the use of the PNG Reference Library, even if advised of ++the possibility of such damage. ++ ++Permission is hereby granted to use, copy, modify, and distribute this ++source code, or portions hereof, for any purpose, without fee, subject ++to the following restrictions: ++ ++ 1. The origin of this source code must not be misrepresented. ++ ++ 2. Altered versions must be plainly marked as such and must not ++ be misrepresented as being the original source. ++ ++ 3. This Copyright notice may not be removed or altered from any ++ source or altered source distribution. ++ ++The Contributing Authors and Group 42, Inc. specifically permit, ++without fee, and encourage the use of this source code as a component ++to supporting the PNG file format in commercial products. If you use ++this source code in a product, acknowledgment is not required but would ++be appreciated. ++ ++TRADEMARK: ++ ++The name "libpng" has not been registered by the Copyright owners ++as a trademark in any jurisdiction. However, because libpng has ++been distributed and maintained world-wide, continually since 1995, ++the Copyright owners claim "common-law trademark protection" in any ++jurisdiction where common-law trademark is recognized. ++ ++OSI CERTIFICATION: ++ ++Libpng is OSI Certified Open Source Software. OSI Certified Open Source is ++a certification mark of the Open Source Initiative. OSI has not addressed ++the additional disclaimers inserted at version 1.0.7. ++ ++EXPORT CONTROL: ++ ++The Copyright owner believes that the Export Control Classification ++Number (ECCN) for libpng is EAR99, which means not subject to export ++controls or International Traffic in Arms Regulations (ITAR) because ++it is open source, publicly available software, that does not contain ++any encryption software. See the EAR, paragraphs 734.3(b)(3) and ++734.7(b). ++ ++Glenn Randers-Pehrson ++glennrp at users.sourceforge.net ++July 15, 2018 ++ ++AUTHORS File Information: ++ ++PNG REFERENCE LIBRARY AUTHORS ++============================= ++ ++This is the list of PNG Reference Library ("libpng") Contributing ++Authors, for copyright and licensing purposes. ++ ++ * Andreas Dilger ++ * Cosmin Truta ++ * Dave Martindale ++ * Eric S. Raymond ++ * Gilles Vollant ++ * Glenn Randers-Pehrson ++ * Greg Roelofs ++ * Guy Eric Schalnat ++ * James Yu ++ * John Bowler ++ * Kevin Bracey ++ * Magnus Holmgren ++ * Mandar Sahastrabuddhe ++ * Mans Rullgard ++ * Matt Sarett ++ * Mike Klein ++ * Pascal Massimino ++ * Paul Schmidt ++ * Qiang Zhou ++ * Sam Bushell ++ * Samuel Williams ++ * Simon-Pierre Cadieux ++ * Tim Wegner ++ * Tom Lane ++ * Tom Tanner ++ * Vadim Barkov ++ * Willem van Schaik ++ * Zhijie Liang ++ * Arm Holdings ++ - Richard Townsend ++ * Google Inc. ++ - Dan Field ++ - Leon Scroggins III ++ - Matt Sarett ++ - Mike Klein ++ - Sami Boukortt ++ ++The build projects, the build scripts, the test scripts, and other ++files in the "ci", "projects", "scripts" and "tests" directories, have ++other copyright owners, but are released under the libpng license. ++ ++Some files in the "contrib" directory, and some tools-generated files ++that are distributed with libpng, have other copyright owners, and are ++released under other open source licenses. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to GIFLIB 5.2.1 & libungif 4.1.3, ++which may be included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++The GIFLIB distribution is Copyright (c) 1997 Eric S. Raymond ++ ++Permission is hereby granted, free of charge, to any person obtaining a copy ++of this software and associated documentation files (the "Software"), to deal ++in the Software without restriction, including without limitation the rights ++to use, copy, modify, merge, publish, distribute, sublicense, and/or sell ++copies of the Software, and to permit persons to whom the Software is ++furnished to do so, subject to the following conditions: ++ ++The above copyright notice and this permission notice shall be included in ++all copies or substantial portions of the Software. ++ ++THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE ++AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ++LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, ++OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN ++THE SOFTWARE. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Little CMS 2.11, which may be ++included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++Little CMS ++Copyright (c) 1998-2020 Marti Maria Saguer ++ ++Permission is hereby granted, free of charge, to any person obtaining a copy ++of this software and associated documentation files (the "Software"), to deal ++in the Software without restriction, including without limitation the rights ++to use, copy, modify, merge, publish, distribute, sublicense, and/or sell ++copies of the Software, and to permit persons to whom the Software is ++furnished to do so, subject to the following conditions: ++ ++The above copyright notice and this permission notice shall be included in all ++copies or substantial portions of the Software. ++ ++THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE ++AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ++LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, ++OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE ++SOFTWARE. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% Lucida is a registered trademark or trademark of Bigelow & Holmes in the ++U.S. and other countries. ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Mesa 3D Graphics Library v4.1, ++which may be included with JRE 8, JDK 8, and OpenJDK 8 source distributions. ++ ++--- begin of LICENSE --- ++ ++ Mesa 3-D Graphics Library v19.2.1 ++ ++ Copyright (C) 1999-2007 Brian Paul All Rights Reserved. ++ ++ Permission is hereby granted, free of charge, to any person obtaining a ++ copy of this software and associated documentation files (the "Software"), ++ to deal in the Software without restriction, including without limitation ++ the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ and/or sell copies of the Software, and to permit persons to whom the ++ Software is furnished to do so, subject to the following conditions: ++ ++ The above copyright notice and this permission notice shall be included ++ in all copies or substantial portions of the Software. ++ ++ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ++ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, ++ OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE ++ SOFTWARE. ++ ++Attention, Contributors ++ ++When contributing to the Mesa project you must agree to the licensing terms ++of the component to which you're contributing. ++The following section lists the primary components of the Mesa distribution ++and their respective licenses. ++Mesa Component Licenses ++ ++ ++ ++Component Location License ++------------------------------------------------------------------ ++Main Mesa code src/mesa/ MIT ++Device drivers src/mesa/drivers/* MIT, generally ++ ++Gallium code src/gallium/ MIT ++ ++Ext headers GL/glext.h Khronos ++ GL/glxext.h Khronos ++ GL/wglext.h Khronos ++ KHR/khrplatform.h Khronos ++ ++***************************************************************************** ++ ++---- ++include/GL/gl.h : ++ ++ ++ Mesa 3-D graphics library ++ ++ Copyright (C) 1999-2006 Brian Paul All Rights Reserved. ++ Copyright (C) 2009 VMware, Inc. All Rights Reserved. ++ ++ Permission is hereby granted, free of charge, to any person obtaining a ++ copy of this software and associated documentation files (the "Software"), ++ to deal in the Software without restriction, including without limitation ++ the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ and/or sell copies of the Software, and to permit persons to whom the ++ Software is furnished to do so, subject to the following conditions: ++ ++ The above copyright notice and this permission notice shall be included ++ in all copies or substantial portions of the Software. ++ ++ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ OTHER DEALINGS IN THE SOFTWARE. ++ ++ ***************************************************************************** ++ ++---- ++include/GL/glext.h ++include/GL/glxext.h ++include/GL/wglxext.h : ++ ++ ++ Copyright (c) 2013 - 2018 The Khronos Group Inc. ++ ++ Permission is hereby granted, free of charge, to any person obtaining a ++ copy of this software and/or associated documentation files (the ++ "Materials"), to deal in the Materials without restriction, including ++ without limitation the rights to use, copy, modify, merge, publish, ++ distribute, sublicense, and/or sell copies of the Materials, and to ++ permit persons to whom the Materials are furnished to do so, subject to ++ the following conditions: ++ ++ The above copyright notice and this permission notice shall be included ++ in all copies or substantial portions of the Materials. ++ ++ THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. ++ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY ++ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, ++ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE ++ MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS. ++ ++ ***************************************************************************** ++ ++---- ++include/KHR/khrplatform.h : ++ ++ Copyright (c) 2008 - 2018 The Khronos Group Inc. ++ ++ Permission is hereby granted, free of charge, to any person obtaining a ++ copy of this software and/or associated documentation files (the ++ "Materials"), to deal in the Materials without restriction, including ++ without limitation the rights to use, copy, modify, merge, publish, ++ distribute, sublicense, and/or sell copies of the Materials, and to ++ permit persons to whom the Materials are furnished to do so, subject to ++ the following conditions: ++ ++ The above copyright notice and this permission notice shall be included ++ in all copies or substantial portions of the Materials. ++ ++ THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. ++ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY ++ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, ++ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE ++ MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS. ++ ++ ***************************************************************************** ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Mozilla Network Security ++Services (NSS), which is supplied with the JDK test suite in the OpenJDK ++source code repository. It is licensed under Mozilla Public License (MPL), ++version 2.0. ++ ++The NSS libraries are supplied in executable form, built from unmodified ++NSS source code labeled with the "NSS_3_16_RTM" HG tag. ++ ++The NSS source code is available in the OpenJDK source code repository at: ++ jdk/test/sun/security/pkcs11/nss/src ++ ++The NSS libraries are available in the OpenJDK source code repository at: ++ jdk/test/sun/security/pkcs11/nss/lib ++ ++--- begin of LICENSE --- ++ ++Mozilla Public License Version 2.0 ++================================== ++ ++1. Definitions ++-------------- ++ ++1.1. "Contributor" ++ means each individual or legal entity that creates, contributes to ++ the creation of, or owns Covered Software. ++ ++1.2. "Contributor Version" ++ means the combination of the Contributions of others (if any) used ++ by a Contributor and that particular Contributor's Contribution. ++ ++1.3. "Contribution" ++ means Covered Software of a particular Contributor. ++ ++1.4. "Covered Software" ++ means Source Code Form to which the initial Contributor has attached ++ the notice in Exhibit A, the Executable Form of such Source Code ++ Form, and Modifications of such Source Code Form, in each case ++ including portions thereof. ++ ++1.5. "Incompatible With Secondary Licenses" ++ means ++ ++ (a) that the initial Contributor has attached the notice described ++ in Exhibit B to the Covered Software; or ++ ++ (b) that the Covered Software was made available under the terms of ++ version 1.1 or earlier of the License, but not also under the ++ terms of a Secondary License. ++ ++1.6. "Executable Form" ++ means any form of the work other than Source Code Form. ++ ++1.7. "Larger Work" ++ means a work that combines Covered Software with other material, in ++ a separate file or files, that is not Covered Software. ++ ++1.8. "License" ++ means this document. ++ ++1.9. "Licensable" ++ means having the right to grant, to the maximum extent possible, ++ whether at the time of the initial grant or subsequently, any and ++ all of the rights conveyed by this License. ++ ++1.10. "Modifications" ++ means any of the following: ++ ++ (a) any file in Source Code Form that results from an addition to, ++ deletion from, or modification of the contents of Covered ++ Software; or ++ ++ (b) any new file in Source Code Form that contains any Covered ++ Software. ++ ++1.11. "Patent Claims" of a Contributor ++ means any patent claim(s), including without limitation, method, ++ process, and apparatus claims, in any patent Licensable by such ++ Contributor that would be infringed, but for the grant of the ++ License, by the making, using, selling, offering for sale, having ++ made, import, or transfer of either its Contributions or its ++ Contributor Version. ++ ++1.12. "Secondary License" ++ means either the GNU General Public License, Version 2.0, the GNU ++ Lesser General Public License, Version 2.1, the GNU Affero General ++ Public License, Version 3.0, or any later versions of those ++ licenses. ++ ++1.13. "Source Code Form" ++ means the form of the work preferred for making modifications. ++ ++1.14. "You" (or "Your") ++ means an individual or a legal entity exercising rights under this ++ License. For legal entities, "You" includes any entity that ++ controls, is controlled by, or is under common control with You. For ++ purposes of this definition, "control" means (a) the power, direct ++ or indirect, to cause the direction or management of such entity, ++ whether by contract or otherwise, or (b) ownership of more than ++ fifty percent (50%) of the outstanding shares or beneficial ++ ownership of such entity. ++ ++2. License Grants and Conditions ++-------------------------------- ++ ++2.1. Grants ++ ++Each Contributor hereby grants You a world-wide, royalty-free, ++non-exclusive license: ++ ++(a) under intellectual property rights (other than patent or trademark) ++ Licensable by such Contributor to use, reproduce, make available, ++ modify, display, perform, distribute, and otherwise exploit its ++ Contributions, either on an unmodified basis, with Modifications, or ++ as part of a Larger Work; and ++ ++(b) under Patent Claims of such Contributor to make, use, sell, offer ++ for sale, have made, import, and otherwise transfer either its ++ Contributions or its Contributor Version. ++ ++2.2. Effective Date ++ ++The licenses granted in Section 2.1 with respect to any Contribution ++become effective for each Contribution on the date the Contributor first ++distributes such Contribution. ++ ++2.3. Limitations on Grant Scope ++ ++The licenses granted in this Section 2 are the only rights granted under ++this License. No additional rights or licenses will be implied from the ++distribution or licensing of Covered Software under this License. ++Notwithstanding Section 2.1(b) above, no patent license is granted by a ++Contributor: ++ ++(a) for any code that a Contributor has removed from Covered Software; ++ or ++ ++(b) for infringements caused by: (i) Your and any other third party's ++ modifications of Covered Software, or (ii) the combination of its ++ Contributions with other software (except as part of its Contributor ++ Version); or ++ ++(c) under Patent Claims infringed by Covered Software in the absence of ++ its Contributions. ++ ++This License does not grant any rights in the trademarks, service marks, ++or logos of any Contributor (except as may be necessary to comply with ++the notice requirements in Section 3.4). ++ ++2.4. Subsequent Licenses ++ ++No Contributor makes additional grants as a result of Your choice to ++distribute the Covered Software under a subsequent version of this ++License (see Section 10.2) or under the terms of a Secondary License (if ++permitted under the terms of Section 3.3). ++ ++2.5. Representation ++ ++Each Contributor represents that the Contributor believes its ++Contributions are its original creation(s) or it has sufficient rights ++to grant the rights to its Contributions conveyed by this License. ++ ++2.6. Fair Use ++ ++This License is not intended to limit any rights You have under ++applicable copyright doctrines of fair use, fair dealing, or other ++equivalents. ++ ++2.7. Conditions ++ ++Sections 3.1, 3.2, 3.3, and 3.4 are conditions of the licenses granted ++in Section 2.1. ++ ++3. Responsibilities ++------------------- ++ ++3.1. Distribution of Source Form ++ ++All distribution of Covered Software in Source Code Form, including any ++Modifications that You create or to which You contribute, must be under ++the terms of this License. You must inform recipients that the Source ++Code Form of the Covered Software is governed by the terms of this ++License, and how they can obtain a copy of this License. You may not ++attempt to alter or restrict the recipients' rights in the Source Code ++Form. ++ ++3.2. Distribution of Executable Form ++ ++If You distribute Covered Software in Executable Form then: ++ ++(a) such Covered Software must also be made available in Source Code ++ Form, as described in Section 3.1, and You must inform recipients of ++ the Executable Form how they can obtain a copy of such Source Code ++ Form by reasonable means in a timely manner, at a charge no more ++ than the cost of distribution to the recipient; and ++ ++(b) You may distribute such Executable Form under the terms of this ++ License, or sublicense it under different terms, provided that the ++ license for the Executable Form does not attempt to limit or alter ++ the recipients' rights in the Source Code Form under this License. ++ ++3.3. Distribution of a Larger Work ++ ++You may create and distribute a Larger Work under terms of Your choice, ++provided that You also comply with the requirements of this License for ++the Covered Software. If the Larger Work is a combination of Covered ++Software with a work governed by one or more Secondary Licenses, and the ++Covered Software is not Incompatible With Secondary Licenses, this ++License permits You to additionally distribute such Covered Software ++under the terms of such Secondary License(s), so that the recipient of ++the Larger Work may, at their option, further distribute the Covered ++Software under the terms of either this License or such Secondary ++License(s). ++ ++3.4. Notices ++ ++You may not remove or alter the substance of any license notices ++(including copyright notices, patent notices, disclaimers of warranty, ++or limitations of liability) contained within the Source Code Form of ++the Covered Software, except that You may alter any license notices to ++the extent required to remedy known factual inaccuracies. ++ ++3.5. Application of Additional Terms ++ ++You may choose to offer, and to charge a fee for, warranty, support, ++indemnity or liability obligations to one or more recipients of Covered ++Software. However, You may do so only on Your own behalf, and not on ++behalf of any Contributor. You must make it absolutely clear that any ++such warranty, support, indemnity, or liability obligation is offered by ++You alone, and You hereby agree to indemnify every Contributor for any ++liability incurred by such Contributor as a result of warranty, support, ++indemnity or liability terms You offer. You may include additional ++disclaimers of warranty and limitations of liability specific to any ++jurisdiction. ++ ++4. Inability to Comply Due to Statute or Regulation ++--------------------------------------------------- ++ ++If it is impossible for You to comply with any of the terms of this ++License with respect to some or all of the Covered Software due to ++statute, judicial order, or regulation then You must: (a) comply with ++the terms of this License to the maximum extent possible; and (b) ++describe the limitations and the code they affect. Such description must ++be placed in a text file included with all distributions of the Covered ++Software under this License. Except to the extent prohibited by statute ++or regulation, such description must be sufficiently detailed for a ++recipient of ordinary skill to be able to understand it. ++ ++5. Termination ++-------------- ++ ++5.1. The rights granted under this License will terminate automatically ++if You fail to comply with any of its terms. However, if You become ++compliant, then the rights granted under this License from a particular ++Contributor are reinstated (a) provisionally, unless and until such ++Contributor explicitly and finally terminates Your grants, and (b) on an ++ongoing basis, if such Contributor fails to notify You of the ++non-compliance by some reasonable means prior to 60 days after You have ++come back into compliance. Moreover, Your grants from a particular ++Contributor are reinstated on an ongoing basis if such Contributor ++notifies You of the non-compliance by some reasonable means, this is the ++first time You have received notice of non-compliance with this License ++from such Contributor, and You become compliant prior to 30 days after ++Your receipt of the notice. ++ ++5.2. If You initiate litigation against any entity by asserting a patent ++infringement claim (excluding declaratory judgment actions, ++counter-claims, and cross-claims) alleging that a Contributor Version ++directly or indirectly infringes any patent, then the rights granted to ++You by any and all Contributors for the Covered Software under Section ++2.1 of this License shall terminate. ++ ++5.3. In the event of termination under Sections 5.1 or 5.2 above, all ++end user license agreements (excluding distributors and resellers) which ++have been validly granted by You or Your distributors under this License ++prior to termination shall survive termination. ++ ++************************************************************************ ++* * ++* 6. Disclaimer of Warranty * ++* ------------------------- * ++* * ++* Covered Software is provided under this License on an "as is" * ++* basis, without warranty of any kind, either expressed, implied, or * ++* statutory, including, without limitation, warranties that the * ++* Covered Software is free of defects, merchantable, fit for a * ++* particular purpose or non-infringing. The entire risk as to the * ++* quality and performance of the Covered Software is with You. * ++* Should any Covered Software prove defective in any respect, You * ++* (not any Contributor) assume the cost of any necessary servicing, * ++* repair, or correction. This disclaimer of warranty constitutes an * ++* essential part of this License. No use of any Covered Software is * ++* authorized under this License except under this disclaimer. * ++* * ++************************************************************************ ++ ++************************************************************************ ++* * ++* 7. Limitation of Liability * ++* -------------------------- * ++* * ++* Under no circumstances and under no legal theory, whether tort * ++* (including negligence), contract, or otherwise, shall any * ++* Contributor, or anyone who distributes Covered Software as * ++* permitted above, be liable to You for any direct, indirect, * ++* special, incidental, or consequential damages of any character * ++* including, without limitation, damages for lost profits, loss of * ++* goodwill, work stoppage, computer failure or malfunction, or any * ++* and all other commercial damages or losses, even if such party * ++* shall have been informed of the possibility of such damages. This * ++* limitation of liability shall not apply to liability for death or * ++* personal injury resulting from such party's negligence to the * ++* extent applicable law prohibits such limitation. Some * ++* jurisdictions do not allow the exclusion or limitation of * ++* incidental or consequential damages, so this exclusion and * ++* limitation may not apply to You. * ++* * ++************************************************************************ ++ ++8. Litigation ++------------- ++ ++Any litigation relating to this License may be brought only in the ++courts of a jurisdiction where the defendant maintains its principal ++place of business and such litigation shall be governed by laws of that ++jurisdiction, without reference to its conflict-of-law provisions. ++Nothing in this Section shall prevent a party's ability to bring ++cross-claims or counter-claims. ++ ++9. Miscellaneous ++---------------- ++ ++This License represents the complete agreement concerning the subject ++matter hereof. If any provision of this License is held to be ++unenforceable, such provision shall be reformed only to the extent ++necessary to make it enforceable. Any law or regulation which provides ++that the language of a contract shall be construed against the drafter ++shall not be used to construe this License against a Contributor. ++ ++10. Versions of the License ++--------------------------- ++ ++10.1. New Versions ++ ++Mozilla Foundation is the license steward. Except as provided in Section ++10.3, no one other than the license steward has the right to modify or ++publish new versions of this License. Each version will be given a ++distinguishing version number. ++ ++10.2. Effect of New Versions ++ ++You may distribute the Covered Software under the terms of the version ++of the License under which You originally received the Covered Software, ++or under the terms of any subsequent version published by the license ++steward. ++ ++10.3. Modified Versions ++ ++If you create software not governed by this License, and you want to ++create a new license for such software, you may create and use a ++modified version of this License if you rename the license and remove ++any references to the name of the license steward (except to note that ++such modified license differs from this License). ++ ++10.4. Distributing Source Code Form that is Incompatible With Secondary ++Licenses ++ ++If You choose to distribute Source Code Form that is Incompatible With ++Secondary Licenses under the terms of this version of the License, the ++notice described in Exhibit B of this License must be attached. ++ ++Exhibit A - Source Code Form License Notice ++------------------------------------------- ++ ++ This Source Code Form is subject to the terms of the Mozilla Public ++ License, v. 2.0. If a copy of the MPL was not distributed with this ++ file, You can obtain one at http://mozilla.org/MPL/2.0/. ++ ++If it is not possible or desirable to put the notice in a particular ++file, then You may include the notice in a location (such as a LICENSE ++file in a relevant directory) where a recipient would be likely to look ++for such a notice. ++ ++You may add additional accurate notices of copyright ownership. ++ ++Exhibit B - "Incompatible With Secondary Licenses" Notice ++--------------------------------------------------------- ++ ++ This Source Code Form is "Incompatible With Secondary Licenses", as ++ defined by the Mozilla Public License, v. 2.0. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to PC/SC Lite v1.8.26, ++which may be included with JRE 8, JDK 8, and OpenJDK 8 on Linux and Solaris. ++ ++--- begin of LICENSE --- ++ ++Copyright (c) 1999-2003 David Corcoran ++Copyright (c) 2001-2011 Ludovic Rousseau ++All rights reserved. ++ ++Redistribution and use in source and binary forms, with or without ++modification, are permitted provided that the following conditions ++are met: ++ ++1. Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++2. Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++3. The name of the author may not be used to endorse or promote products ++ derived from this software without specific prior written permission. ++ ++Changes to this license can be made only by the copyright author with ++explicit written consent. ++ ++THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to PorterStemmer v4, which may be ++included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++See: http://tartarus.org/~martin/PorterStemmer ++ ++The software is completely free for any purpose, unless notes at the head of ++the program text indicates otherwise (which is rare). In any case, the notes ++about licensing are never more restrictive than the BSD License. ++ ++In every case where the software is not written by me (Martin Porter), this ++licensing arrangement has been endorsed by the contributor, and it is ++therefore unnecessary to ask the contributor again to confirm it. ++ ++I have not asked any contributors (or their employers, if they have them) for ++proofs that they have the right to distribute their software in this way. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Relax NG Object/Parser v.20050510, ++which may be included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++Copyright (c) Kohsuke Kawaguchi ++ ++Permission is hereby granted, free of charge, to any person obtaining a copy ++of this software and associated documentation files (the "Software"), to deal ++in the Software without restriction, including without limitation the rights ++to use, copy, modify, merge, publish, distribute, sublicense, and/or sell ++copies of the Software, and to permit persons to whom the Software is ++furnished to do so, subject to the following conditions: The above copyright ++notice and this permission notice shall be included in all copies or ++substantial portions of the Software. ++ ++THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE ++AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ++LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, ++OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE ++SOFTWARE. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to RelaxNGCC v1.12, which may be ++included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++Copyright (c) 2000-2003 Daisuke Okajima and Kohsuke Kawaguchi. ++All rights reserved. ++ ++Redistribution and use in source and binary forms, with or without ++modification, are permitted provided that the following conditions are met: ++ ++1. Redistributions of source code must retain the above copyright notice, this ++ list of conditions and the following disclaimer. ++ ++2. Redistributions in binary form must reproduce the above copyright notice, ++ this list of conditions and the following disclaimer in the documentation ++ and/or other materials provided with the distribution. ++ ++3. The end-user documentation included with the redistribution, if any, must ++ include the following acknowledgment: ++ ++ "This product includes software developed by Daisuke Okajima ++ and Kohsuke Kawaguchi (http://relaxngcc.sf.net/)." ++ ++Alternately, this acknowledgment may appear in the software itself, if and ++wherever such third-party acknowledgments normally appear. ++ ++4. The names of the copyright holders must not be used to endorse or promote ++ products derived from this software without prior written permission. For ++ written permission, please contact the copyright holders. ++ ++5. Products derived from this software may not be called "RELAXNGCC", nor may ++ "RELAXNGCC" appear in their name, without prior written permission of the ++ copyright holders. ++ ++THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESSED OR IMPLIED WARRANTIES, ++INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND ++FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.IN NO EVENT SHALL THE APACHE ++SOFTWARE FOUNDATION OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ++INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ++EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Relax NG Datatype 1.0, which ++may be included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++Copyright (c) 2005, 2010 Thai Open Source Software Center Ltd ++All rights reserved. ++ ++Redistribution and use in source and binary forms, with or without ++modification, are permitted provided that the following conditions are ++met: ++ ++ Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ Neither the names of the copyright holders nor the names of its ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR ++CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++--- end of LICENSE --- ++ ++-------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to SoftFloat version 2b, which may be ++included with JRE 8, JDK 8, and OpenJDK 8 on Linux/ARM. ++ ++--- begin of LICENSE --- ++ ++Use of any of this software is governed by the terms of the license below: ++ ++SoftFloat was written by me, John R. Hauser. This work was made possible in ++part by the International Computer Science Institute, located at Suite 600, ++1947 Center Street, Berkeley, California 94704. Funding was partially ++provided by the National Science Foundation under grant MIP-9311980. The ++original version of this code was written as part of a project to build ++a fixed-point vector processor in collaboration with the University of ++California at Berkeley, overseen by Profs. Nelson Morgan and John Wawrzynek. ++ ++THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort ++has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT ++TIMES RESULT IN INCORRECT BEHAVIOR. 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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR HOLDERS INCLUDED IN ++THIS NOTICE BE LIABLE FOR ANY CLAIM, OR ANY SPECIAL INDIRECT OR CONSEQUENTIAL ++DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR ++PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ++ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THE ++DATA FILES OR SOFTWARE. ++ ++Except as contained in this notice, the name of a copyright holder shall not ++be used in advertising or otherwise to promote the sale, use or other dealings ++in these Data Files or Software without prior written authorization of the ++copyright holder. ++ ++Unicode and the Unicode logo are trademarks of Unicode, Inc. in the United ++States and other countries. All third party trademarks referenced herein are ++the property of their respective owners. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to UPX v3.01, which may be included ++with JRE 8 on Windows. ++ ++--- begin of LICENSE --- ++ ++Use of any of this software is governed by the terms of the license below: ++ ++ ++ ooooo ooo ooooooooo. ooooooo ooooo ++ `888' `8' `888 `Y88. `8888 d8' ++ 888 8 888 .d88' Y888..8P ++ 888 8 888ooo88P' `8888' ++ 888 8 888 .8PY888. ++ `88. .8' 888 d8' `888b ++ `YbodP' o888o o888o o88888o ++ ++ ++ The Ultimate Packer for eXecutables ++ Copyright (c) 1996-2000 Markus Oberhumer & Laszlo Molnar ++ http://wildsau.idv.uni-linz.ac.at/mfx/upx.html ++ http://www.nexus.hu/upx ++ http://upx.tsx.org ++ ++ ++PLEASE CAREFULLY READ THIS LICENSE AGREEMENT, ESPECIALLY IF YOU PLAN ++TO MODIFY THE UPX SOURCE CODE OR USE A MODIFIED UPX VERSION. ++ ++ ++ABSTRACT ++======== ++ ++ UPX and UCL are copyrighted software distributed under the terms ++ of the GNU General Public License (hereinafter the "GPL"). ++ ++ The stub which is imbedded in each UPX compressed program is part ++ of UPX and UCL, and contains code that is under our copyright. The ++ terms of the GNU General Public License still apply as compressing ++ a program is a special form of linking with our stub. ++ ++ As a special exception we grant the free usage of UPX for all ++ executables, including commercial programs. ++ See below for details and restrictions. ++ ++ ++COPYRIGHT ++========= ++ ++ UPX and UCL are copyrighted software. All rights remain with the authors. ++ ++ UPX is Copyright (C) 1996-2000 Markus Franz Xaver Johannes Oberhumer ++ UPX is Copyright (C) 1996-2000 Laszlo Molnar ++ ++ UCL is Copyright (C) 1996-2000 Markus Franz Xaver Johannes Oberhumer ++ ++ ++GNU GENERAL PUBLIC LICENSE ++========================== ++ ++ UPX and the UCL library are free software; you can redistribute them ++ and/or modify them under the terms of the GNU General Public License as ++ published by the Free Software Foundation; either version 2 of ++ the License, or (at your option) any later version. ++ ++ UPX and UCL are distributed in the hope that they will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ GNU General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with this program; see the file COPYING. ++ ++ ++SPECIAL EXCEPTION FOR COMPRESSED EXECUTABLES ++============================================ ++ ++ The stub which is imbedded in each UPX compressed program is part ++ of UPX and UCL, and contains code that is under our copyright. The ++ terms of the GNU General Public License still apply as compressing ++ a program is a special form of linking with our stub. ++ ++ Hereby Markus F.X.J. Oberhumer and Laszlo Molnar grant you special ++ permission to freely use and distribute all UPX compressed programs ++ (including commercial ones), subject to the following restrictions: ++ ++ 1. You must compress your program with a completely unmodified UPX ++ version; either with our precompiled version, or (at your option) ++ with a self compiled version of the unmodified UPX sources as ++ distributed by us. ++ 2. This also implies that the UPX stub must be completely unmodfied, i.e. ++ the stub imbedded in your compressed program must be byte-identical ++ to the stub that is produced by the official unmodified UPX version. ++ 3. The decompressor and any other code from the stub must exclusively get ++ used by the unmodified UPX stub for decompressing your program at ++ program startup. No portion of the stub may get read, copied, ++ called or otherwise get used or accessed by your program. ++ ++ ++ANNOTATIONS ++=========== ++ ++ - You can use a modified UPX version or modified UPX stub only for ++ programs that are compatible with the GNU General Public License. ++ ++ - We grant you special permission to freely use and distribute all UPX ++ compressed programs. But any modification of the UPX stub (such as, ++ but not limited to, removing our copyright string or making your ++ program non-decompressible) will immediately revoke your right to ++ use and distribute a UPX compressed program. ++ ++ - UPX is not a software protection tool; by requiring that you use ++ the unmodified UPX version for your proprietary programs we ++ make sure that any user can decompress your program. This protects ++ both you and your users as nobody can hide malicious code - ++ any program that cannot be decompressed is highly suspicious ++ by definition. ++ ++ - You can integrate all or part of UPX and UCL into projects that ++ are compatible with the GNU GPL, but obviously you cannot grant ++ any special exceptions beyond the GPL for our code in your project. ++ ++ - We want to actively support manufacturers of virus scanners and ++ similar security software. Please contact us if you would like to ++ incorporate parts of UPX or UCL into such a product. ++ ++ ++ ++Markus F.X.J. Oberhumer Laszlo Molnar ++markus.oberhumer@jk.uni-linz.ac.at ml1050@cdata.tvnet.hu ++ ++Linz, Austria, 25 Feb 2000 ++ ++Additional License(s) ++ ++The UPX license file is at http://upx.sourceforge.net/upx-license.html. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Xfree86-VidMode Extension 1.0, ++which may be included with JRE 8, JDK 8, and OpenJDK 8 on Linux and Solaris. ++ ++--- begin of LICENSE --- ++ ++Version 1.1 of XFree86 ProjectLicence. ++ ++Copyright (C) 1994-2004 The XFree86 Project, Inc. All rights reserved. ++ ++Permission is hereby granted, free of charge, to any person obtaining a copy of ++this software and associated documentation files (the "Software"), to deal ++in the Software without restriction, including without limitation the rights ++to use, copy, modify, merge, publish, distribute, sublicence, and/or sell ++copies of the Software, and to permit persons to whom the Software is furnished ++to do so,subject to the following conditions: ++ ++ 1. Redistributions of source code must retain the above copyright ++ notice,this list of conditions, and the following disclaimer. ++ ++ 2. Redistributions in binary form must reproduce the above copyright notice, ++ this list of conditions and the following disclaimer in the documentation ++ and/or other materials provided with the distribution, and in the same place ++ and form as other copyright, license and disclaimer information. ++ ++ 3. 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do ++for level in ${levels[@]}; do ++for i in {0..1}; do ++ nOrC=${nc[i]} ++ crosscompiler=${cc[i]} ++ rm -rf build/sw64-$level-$nOrC ++ bash configure \ ++ --openjdk-target=sw_64-unknown-linux-gnu \ ++ --with-devkit=/usr/sw/$crosscompiler/usr/ \ ++ --x-includes=/usr/sw/$crosscompiler/usr/include \ ++ --x-libraries=/usr/sw/$crosscompiler/usr/lib \ ++ --with-freetype-include=/usr/sw/$crosscompiler/usr/include/freetype2 \ ++ --with-freetype-lib=/usr/sw/$crosscompiler/usr/lib/sw_64-linux-gnu \ ++ --disable-zip-debug-info \ ++ --with-debug-level=$level \ ++ --with-conf-name=sw64-$level-$nOrC ++done ++done ++ +diff --git a/hotspot/THIRD_PARTY_README b/hotspot/THIRD_PARTY_README +new file mode 100644 +index 0000000000..f26a5f3ec5 +--- /dev/null ++++ b/hotspot/THIRD_PARTY_README +@@ -0,0 +1,3371 @@ ++DO NOT TRANSLATE OR LOCALIZE. ++----------------------------- ++ ++%% This notice is provided with respect to ASM Bytecode Manipulation ++Framework v5.0.3, which may be included with JRE 8, and JDK 8, and ++OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++Copyright (c) 2000-2011 France T??l??com ++All rights reserved. ++ ++Redistribution and use in source and binary forms, with or without ++modification, are permitted provided that the following conditions ++are met: ++ ++1. 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DejaVu changes are in public domain. ++Glyphs imported from Arev fonts are (c) Tavmjong Bah (see below) ++ ++ ++Bitstream Vera Fonts Copyright ++------------------------------ ++ ++Copyright (c) 2003 by Bitstream, Inc. All Rights Reserved. Bitstream Vera is ++a trademark of Bitstream, Inc. ++ ++Permission is hereby granted, free of charge, to any person obtaining a copy ++of the fonts accompanying this license ("Fonts") and associated ++documentation files (the "Font Software"), to reproduce and distribute the ++Font Software, including without limitation the rights to use, copy, merge, ++publish, distribute, and/or sell copies of the Font Software, and to permit ++persons to whom the Font Software is furnished to do so, subject to the ++following conditions: ++ ++The above copyright and trademark notices and this permission notice shall ++be included in all copies of one or more of the Font Software typefaces. ++ ++The Font Software may be modified, altered, or added to, and in particular ++the designs of glyphs or characters in the Fonts may be modified and ++additional glyphs or characters may be added to the Fonts, only if the fonts ++are renamed to names not containing either the words "Bitstream" or the word ++"Vera". ++ ++This License becomes null and void to the extent applicable to Fonts or Font ++Software that has been modified and is distributed under the "Bitstream ++Vera" names. ++ ++The Font Software may be sold as part of a larger software package but no ++copy of one or more of the Font Software typefaces may be sold by itself. ++ ++THE FONT SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++OR IMPLIED, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OF MERCHANTABILITY, ++FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT OF COPYRIGHT, PATENT, ++TRADEMARK, OR OTHER RIGHT. IN NO EVENT SHALL BITSTREAM OR THE GNOME ++FOUNDATION BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, INCLUDING ++ANY GENERAL, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, ++WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF ++THE USE OR INABILITY TO USE THE FONT SOFTWARE OR FROM OTHER DEALINGS IN THE ++FONT SOFTWARE. ++ ++Except as contained in this notice, the names of Gnome, the Gnome ++Foundation, and Bitstream Inc., shall not be used in advertising or ++otherwise to promote the sale, use or other dealings in this Font Software ++without prior written authorization from the Gnome Foundation or Bitstream ++Inc., respectively. For further information, contact: fonts at gnome dot ++org. ++ ++Arev Fonts Copyright ++------------------------------ ++ ++Copyright (c) 2006 by Tavmjong Bah. All Rights Reserved. ++ ++Permission is hereby granted, free of charge, to any person obtaining ++a copy of the fonts accompanying this license ("Fonts") and ++associated documentation files (the "Font Software"), to reproduce ++and distribute the modifications to the Bitstream Vera Font Software, ++including without limitation the rights to use, copy, merge, publish, ++distribute, and/or sell copies of the Font Software, and to permit ++persons to whom the Font Software is furnished to do so, subject to ++the following conditions: ++ ++The above copyright and trademark notices and this permission notice ++shall be included in all copies of one or more of the Font Software ++typefaces. ++ ++The Font Software may be modified, altered, or added to, and in ++particular the designs of glyphs or characters in the Fonts may be ++modified and additional glyphs or characters may be added to the ++Fonts, only if the fonts are renamed to names not containing either ++the words "Tavmjong Bah" or the word "Arev". ++ ++This License becomes null and void to the extent applicable to Fonts ++or Font Software that has been modified and is distributed under the ++"Tavmjong Bah Arev" names. ++ ++The Font Software may be sold as part of a larger software package but ++no copy of one or more of the Font Software typefaces may be sold by ++itself. ++ ++THE FONT SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OF ++MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT ++OF COPYRIGHT, PATENT, TRADEMARK, OR OTHER RIGHT. IN NO EVENT SHALL ++TAVMJONG BAH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++INCLUDING ANY GENERAL, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL ++DAMAGES, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++FROM, OUT OF THE USE OR INABILITY TO USE THE FONT SOFTWARE OR FROM ++OTHER DEALINGS IN THE FONT SOFTWARE. ++ ++Except as contained in this notice, the name of Tavmjong Bah shall not ++be used in advertising or otherwise to promote the sale, use or other ++dealings in this Font Software without prior written authorization ++from Tavmjong Bah. For further information, contact: tavmjong @ free ++. fr. ++ ++TeX Gyre DJV Math ++----------------- ++Fonts are (c) Bitstream (see below). DejaVu changes are in public domain. ++ ++Math extensions done by B. Jackowski, P. Strzelczyk and P. Pianowski ++(on behalf of TeX users groups) are in public domain. ++ ++Letters imported from Euler Fraktur from AMSfonts are (c) American ++Mathematical Society (see below). ++Bitstream Vera Fonts Copyright ++Copyright (c) 2003 by Bitstream, Inc. All Rights Reserved. Bitstream Vera ++is a trademark of Bitstream, Inc. ++ ++Permission is hereby granted, free of charge, to any person obtaining a copy ++of the fonts accompanying this license ("Fonts") and associated documentation ++files (the "Font Software"), to reproduce and distribute the Font Software, ++including without limitation the rights to use, copy, merge, publish, ++distribute, and/or sell copies of the Font Software, and to permit persons ++to whom the Font Software is furnished to do so, subject to the following ++conditions: ++ ++The above copyright and trademark notices and this permission notice ++shall be included in all copies of one or more of the Font Software typefaces. ++ ++The Font Software may be modified, altered, or added to, and in particular ++the designs of glyphs or characters in the Fonts may be modified and ++additional glyphs or characters may be added to the Fonts, only if the ++fonts are renamed to names not containing either the words "Bitstream" ++or the word "Vera". ++ ++This License becomes null and void to the extent applicable to Fonts or ++Font Software that has been modified and is distributed under the ++"Bitstream Vera" names. ++ ++The Font Software may be sold as part of a larger software package but ++no copy of one or more of the Font Software typefaces may be sold by itself. ++ ++THE FONT SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++OR IMPLIED, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OF MERCHANTABILITY, ++FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT OF COPYRIGHT, PATENT, ++TRADEMARK, OR OTHER RIGHT. IN NO EVENT SHALL BITSTREAM OR THE GNOME ++FOUNDATION BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, INCLUDING ++ANY GENERAL, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, ++WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT ++OF THE USE OR INABILITY TO USE THE FONT SOFTWARE OR FROM OTHER DEALINGS IN ++THE FONT SOFTWARE. ++Except as contained in this notice, the names of GNOME, the GNOME ++Foundation, and Bitstream Inc., shall not be used in advertising or ++otherwise to promote the sale, use or other dealings in this Font Software ++without prior written authorization from the GNOME Foundation or ++Bitstream Inc., respectively. ++For further information, contact: fonts at gnome dot org. ++ ++AMSFonts (v. 2.2) copyright ++ ++The PostScript Type 1 implementation of the AMSFonts produced by and ++previously distributed by Blue Sky Research and Y&Y, Inc. are now freely ++available for general use. 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All rights reserved. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Kerberos functionality from ++FundsXpress, INC., which may be included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++ Copyright (C) 1998 by the FundsXpress, INC. ++ ++ All rights reserved. ++ ++ Export of this software from the United States of America may require ++ a specific license from the United States Government. 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It is provided "as is" without express ++ or implied warranty. ++ ++ THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR ++ IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED ++ WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. ++ ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Kronos OpenGL headers, which may be ++included with JDK 8 and OpenJDK 8 source distributions. ++ ++--- begin of LICENSE --- ++ ++ Copyright (c) 2007 The Khronos Group Inc. ++ ++ Permission is hereby granted, free of charge, to any person obtaining a copy ++ of this software and/or associated documentation files (the "Materials"), to ++ deal in the Materials without restriction, including without limitation the ++ rights to use, copy, modify, merge, publish, distribute, sublicense, and/or ++ sell copies of the Materials, and to permit persons to whom the Materials are ++ furnished to do so, subject to the following conditions: ++ ++ The above copyright notice and this permission notice shall be included in all ++ copies or substantial portions of the Materials. ++ ++ THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE ++ AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ++ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, ++ OUT OF OR IN CONNECTION WITH THE MATERIALS OR THE USE OR OTHER DEALINGS IN THE ++ MATERIALS. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% Portions Copyright Eastman Kodak Company 1991-2003 ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to libpng 1.6.39, which may be ++included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++COPYRIGHT NOTICE, DISCLAIMER, and LICENSE ++========================================= ++ ++PNG Reference Library License version 2 ++--------------------------------------- ++ ++Copyright (c) 1995-2022 The PNG Reference Library Authors. ++Copyright (c) 2018-2022 Cosmin Truta ++Copyright (c) 1998-2018 Glenn Randers-Pehrson ++Copyright (c) 1996-1997 Andreas Dilger ++Copyright (c) 1995-1996 Guy Eric Schalnat, Group 42, Inc. ++ ++The software is supplied "as is", without warranty of any kind, ++express or implied, including, without limitation, the warranties ++of merchantability, fitness for a particular purpose, title, and ++non-infringement. In no event shall the Copyright owners, or ++anyone distributing the software, be liable for any damages or ++other liability, whether in contract, tort or otherwise, arising ++from, out of, or in connection with the software, or the use or ++other dealings in the software, even if advised of the possibility ++of such damage. ++ ++Permission is hereby granted to use, copy, modify, and distribute ++this software, or portions hereof, for any purpose, without fee, ++subject to the following restrictions: ++ ++ 1. The origin of this software must not be misrepresented; you ++ must not claim that you wrote the original software. If you ++ use this software in a product, an acknowledgment in the product ++ documentation would be appreciated, but is not required. ++ ++ 2. Altered source versions must be plainly marked as such, and must ++ not be misrepresented as being the original software. ++ ++ 3. This Copyright notice may not be removed or altered from any ++ source or altered source distribution. ++ ++ ++PNG Reference Library License version 1 (for libpng 0.5 through 1.6.35) ++----------------------------------------------------------------------- ++ ++libpng versions 1.0.7, July 1, 2000, through 1.6.35, July 15, 2018 are ++Copyright (c) 2000-2002, 2004, 2006-2018 Glenn Randers-Pehrson, are ++derived from libpng-1.0.6, and are distributed according to the same ++disclaimer and license as libpng-1.0.6 with the following individuals ++added to the list of Contributing Authors: ++ ++ Simon-Pierre Cadieux ++ Eric S. Raymond ++ Mans Rullgard ++ Cosmin Truta ++ Gilles Vollant ++ James Yu ++ Mandar Sahastrabuddhe ++ Google Inc. ++ Vadim Barkov ++ ++and with the following additions to the disclaimer: ++ ++ There is no warranty against interference with your enjoyment of ++ the library or against infringement. There is no warranty that our ++ efforts or the library will fulfill any of your particular purposes ++ or needs. This library is provided with all faults, and the entire ++ risk of satisfactory quality, performance, accuracy, and effort is ++ with the user. ++ ++Some files in the "contrib" directory and some configure-generated ++files that are distributed with libpng have other copyright owners, and ++are released under other open source licenses. ++ ++libpng versions 0.97, January 1998, through 1.0.6, March 20, 2000, are ++Copyright (c) 1998-2000 Glenn Randers-Pehrson, are derived from ++libpng-0.96, and are distributed according to the same disclaimer and ++license as libpng-0.96, with the following individuals added to the ++list of Contributing Authors: ++ ++ Tom Lane ++ Glenn Randers-Pehrson ++ Willem van Schaik ++ ++libpng versions 0.89, June 1996, through 0.96, May 1997, are ++Copyright (c) 1996-1997 Andreas Dilger, are derived from libpng-0.88, ++and are distributed according to the same disclaimer and license as ++libpng-0.88, with the following individuals added to the list of ++Contributing Authors: ++ ++ John Bowler ++ Kevin Bracey ++ Sam Bushell ++ Magnus Holmgren ++ Greg Roelofs ++ Tom Tanner ++ ++Some files in the "scripts" directory have other copyright owners, ++but are released under this license. ++ ++libpng versions 0.5, May 1995, through 0.88, January 1996, are ++Copyright (c) 1995-1996 Guy Eric Schalnat, Group 42, Inc. ++ ++For the purposes of this copyright and license, "Contributing Authors" ++is defined as the following set of individuals: ++ ++ Andreas Dilger ++ Dave Martindale ++ Guy Eric Schalnat ++ Paul Schmidt ++ Tim Wegner ++ ++The PNG Reference Library is supplied "AS IS". The Contributing ++Authors and Group 42, Inc. disclaim all warranties, expressed or ++implied, including, without limitation, the warranties of ++merchantability and of fitness for any purpose. The Contributing ++Authors and Group 42, Inc. assume no liability for direct, indirect, ++incidental, special, exemplary, or consequential damages, which may ++result from the use of the PNG Reference Library, even if advised of ++the possibility of such damage. ++ ++Permission is hereby granted to use, copy, modify, and distribute this ++source code, or portions hereof, for any purpose, without fee, subject ++to the following restrictions: ++ ++ 1. The origin of this source code must not be misrepresented. ++ ++ 2. Altered versions must be plainly marked as such and must not ++ be misrepresented as being the original source. ++ ++ 3. This Copyright notice may not be removed or altered from any ++ source or altered source distribution. ++ ++The Contributing Authors and Group 42, Inc. specifically permit, ++without fee, and encourage the use of this source code as a component ++to supporting the PNG file format in commercial products. If you use ++this source code in a product, acknowledgment is not required but would ++be appreciated. ++ ++TRADEMARK: ++ ++The name "libpng" has not been registered by the Copyright owners ++as a trademark in any jurisdiction. However, because libpng has ++been distributed and maintained world-wide, continually since 1995, ++the Copyright owners claim "common-law trademark protection" in any ++jurisdiction where common-law trademark is recognized. ++ ++OSI CERTIFICATION: ++ ++Libpng is OSI Certified Open Source Software. OSI Certified Open Source is ++a certification mark of the Open Source Initiative. OSI has not addressed ++the additional disclaimers inserted at version 1.0.7. ++ ++EXPORT CONTROL: ++ ++The Copyright owner believes that the Export Control Classification ++Number (ECCN) for libpng is EAR99, which means not subject to export ++controls or International Traffic in Arms Regulations (ITAR) because ++it is open source, publicly available software, that does not contain ++any encryption software. See the EAR, paragraphs 734.3(b)(3) and ++734.7(b). ++ ++Glenn Randers-Pehrson ++glennrp at users.sourceforge.net ++July 15, 2018 ++ ++AUTHORS File Information: ++ ++PNG REFERENCE LIBRARY AUTHORS ++============================= ++ ++This is the list of PNG Reference Library ("libpng") Contributing ++Authors, for copyright and licensing purposes. ++ ++ * Andreas Dilger ++ * Cosmin Truta ++ * Dave Martindale ++ * Eric S. Raymond ++ * Gilles Vollant ++ * Glenn Randers-Pehrson ++ * Greg Roelofs ++ * Guy Eric Schalnat ++ * James Yu ++ * John Bowler ++ * Kevin Bracey ++ * Magnus Holmgren ++ * Mandar Sahastrabuddhe ++ * Mans Rullgard ++ * Matt Sarett ++ * Mike Klein ++ * Pascal Massimino ++ * Paul Schmidt ++ * Qiang Zhou ++ * Sam Bushell ++ * Samuel Williams ++ * Simon-Pierre Cadieux ++ * Tim Wegner ++ * Tom Lane ++ * Tom Tanner ++ * Vadim Barkov ++ * Willem van Schaik ++ * Zhijie Liang ++ * Arm Holdings ++ - Richard Townsend ++ * Google Inc. ++ - Dan Field ++ - Leon Scroggins III ++ - Matt Sarett ++ - Mike Klein ++ - Sami Boukortt ++ ++The build projects, the build scripts, the test scripts, and other ++files in the "ci", "projects", "scripts" and "tests" directories, have ++other copyright owners, but are released under the libpng license. ++ ++Some files in the "contrib" directory, and some tools-generated files ++that are distributed with libpng, have other copyright owners, and are ++released under other open source licenses. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to GIFLIB 5.2.1 & libungif 4.1.3, ++which may be included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++The GIFLIB distribution is Copyright (c) 1997 Eric S. Raymond ++ ++Permission is hereby granted, free of charge, to any person obtaining a copy ++of this software and associated documentation files (the "Software"), to deal ++in the Software without restriction, including without limitation the rights ++to use, copy, modify, merge, publish, distribute, sublicense, and/or sell ++copies of the Software, and to permit persons to whom the Software is ++furnished to do so, subject to the following conditions: ++ ++The above copyright notice and this permission notice shall be included in ++all copies or substantial portions of the Software. ++ ++THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE ++AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ++LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, ++OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN ++THE SOFTWARE. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Little CMS 2.11, which may be ++included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++Little CMS ++Copyright (c) 1998-2020 Marti Maria Saguer ++ ++Permission is hereby granted, free of charge, to any person obtaining a copy ++of this software and associated documentation files (the "Software"), to deal ++in the Software without restriction, including without limitation the rights ++to use, copy, modify, merge, publish, distribute, sublicense, and/or sell ++copies of the Software, and to permit persons to whom the Software is ++furnished to do so, subject to the following conditions: ++ ++The above copyright notice and this permission notice shall be included in all ++copies or substantial portions of the Software. ++ ++THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE ++AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ++LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, ++OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE ++SOFTWARE. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% Lucida is a registered trademark or trademark of Bigelow & Holmes in the ++U.S. and other countries. ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Mesa 3D Graphics Library v4.1, ++which may be included with JRE 8, JDK 8, and OpenJDK 8 source distributions. ++ ++--- begin of LICENSE --- ++ ++ Mesa 3-D Graphics Library v19.2.1 ++ ++ Copyright (C) 1999-2007 Brian Paul All Rights Reserved. ++ ++ Permission is hereby granted, free of charge, to any person obtaining a ++ copy of this software and associated documentation files (the "Software"), ++ to deal in the Software without restriction, including without limitation ++ the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ and/or sell copies of the Software, and to permit persons to whom the ++ Software is furnished to do so, subject to the following conditions: ++ ++ The above copyright notice and this permission notice shall be included ++ in all copies or substantial portions of the Software. ++ ++ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ++ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, ++ OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE ++ SOFTWARE. ++ ++Attention, Contributors ++ ++When contributing to the Mesa project you must agree to the licensing terms ++of the component to which you're contributing. ++The following section lists the primary components of the Mesa distribution ++and their respective licenses. ++Mesa Component Licenses ++ ++ ++ ++Component Location License ++------------------------------------------------------------------ ++Main Mesa code src/mesa/ MIT ++Device drivers src/mesa/drivers/* MIT, generally ++ ++Gallium code src/gallium/ MIT ++ ++Ext headers GL/glext.h Khronos ++ GL/glxext.h Khronos ++ GL/wglext.h Khronos ++ KHR/khrplatform.h Khronos ++ ++***************************************************************************** ++ ++---- ++include/GL/gl.h : ++ ++ ++ Mesa 3-D graphics library ++ ++ Copyright (C) 1999-2006 Brian Paul All Rights Reserved. ++ Copyright (C) 2009 VMware, Inc. All Rights Reserved. ++ ++ Permission is hereby granted, free of charge, to any person obtaining a ++ copy of this software and associated documentation files (the "Software"), ++ to deal in the Software without restriction, including without limitation ++ the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ and/or sell copies of the Software, and to permit persons to whom the ++ Software is furnished to do so, subject to the following conditions: ++ ++ The above copyright notice and this permission notice shall be included ++ in all copies or substantial portions of the Software. ++ ++ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ OTHER DEALINGS IN THE SOFTWARE. ++ ++ ***************************************************************************** ++ ++---- ++include/GL/glext.h ++include/GL/glxext.h ++include/GL/wglxext.h : ++ ++ ++ Copyright (c) 2013 - 2018 The Khronos Group Inc. ++ ++ Permission is hereby granted, free of charge, to any person obtaining a ++ copy of this software and/or associated documentation files (the ++ "Materials"), to deal in the Materials without restriction, including ++ without limitation the rights to use, copy, modify, merge, publish, ++ distribute, sublicense, and/or sell copies of the Materials, and to ++ permit persons to whom the Materials are furnished to do so, subject to ++ the following conditions: ++ ++ The above copyright notice and this permission notice shall be included ++ in all copies or substantial portions of the Materials. ++ ++ THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. ++ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY ++ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, ++ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE ++ MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS. ++ ++ ***************************************************************************** ++ ++---- ++include/KHR/khrplatform.h : ++ ++ Copyright (c) 2008 - 2018 The Khronos Group Inc. ++ ++ Permission is hereby granted, free of charge, to any person obtaining a ++ copy of this software and/or associated documentation files (the ++ "Materials"), to deal in the Materials without restriction, including ++ without limitation the rights to use, copy, modify, merge, publish, ++ distribute, sublicense, and/or sell copies of the Materials, and to ++ permit persons to whom the Materials are furnished to do so, subject to ++ the following conditions: ++ ++ The above copyright notice and this permission notice shall be included ++ in all copies or substantial portions of the Materials. ++ ++ THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. ++ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY ++ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, ++ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE ++ MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS. ++ ++ ***************************************************************************** ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Mozilla Network Security ++Services (NSS), which is supplied with the JDK test suite in the OpenJDK ++source code repository. It is licensed under Mozilla Public License (MPL), ++version 2.0. ++ ++The NSS libraries are supplied in executable form, built from unmodified ++NSS source code labeled with the "NSS_3_16_RTM" HG tag. ++ ++The NSS source code is available in the OpenJDK source code repository at: ++ jdk/test/sun/security/pkcs11/nss/src ++ ++The NSS libraries are available in the OpenJDK source code repository at: ++ jdk/test/sun/security/pkcs11/nss/lib ++ ++--- begin of LICENSE --- ++ ++Mozilla Public License Version 2.0 ++================================== ++ ++1. Definitions ++-------------- ++ ++1.1. "Contributor" ++ means each individual or legal entity that creates, contributes to ++ the creation of, or owns Covered Software. ++ ++1.2. "Contributor Version" ++ means the combination of the Contributions of others (if any) used ++ by a Contributor and that particular Contributor's Contribution. ++ ++1.3. "Contribution" ++ means Covered Software of a particular Contributor. ++ ++1.4. "Covered Software" ++ means Source Code Form to which the initial Contributor has attached ++ the notice in Exhibit A, the Executable Form of such Source Code ++ Form, and Modifications of such Source Code Form, in each case ++ including portions thereof. ++ ++1.5. "Incompatible With Secondary Licenses" ++ means ++ ++ (a) that the initial Contributor has attached the notice described ++ in Exhibit B to the Covered Software; or ++ ++ (b) that the Covered Software was made available under the terms of ++ version 1.1 or earlier of the License, but not also under the ++ terms of a Secondary License. ++ ++1.6. "Executable Form" ++ means any form of the work other than Source Code Form. ++ ++1.7. "Larger Work" ++ means a work that combines Covered Software with other material, in ++ a separate file or files, that is not Covered Software. ++ ++1.8. "License" ++ means this document. ++ ++1.9. "Licensable" ++ means having the right to grant, to the maximum extent possible, ++ whether at the time of the initial grant or subsequently, any and ++ all of the rights conveyed by this License. ++ ++1.10. "Modifications" ++ means any of the following: ++ ++ (a) any file in Source Code Form that results from an addition to, ++ deletion from, or modification of the contents of Covered ++ Software; or ++ ++ (b) any new file in Source Code Form that contains any Covered ++ Software. ++ ++1.11. "Patent Claims" of a Contributor ++ means any patent claim(s), including without limitation, method, ++ process, and apparatus claims, in any patent Licensable by such ++ Contributor that would be infringed, but for the grant of the ++ License, by the making, using, selling, offering for sale, having ++ made, import, or transfer of either its Contributions or its ++ Contributor Version. ++ ++1.12. "Secondary License" ++ means either the GNU General Public License, Version 2.0, the GNU ++ Lesser General Public License, Version 2.1, the GNU Affero General ++ Public License, Version 3.0, or any later versions of those ++ licenses. ++ ++1.13. "Source Code Form" ++ means the form of the work preferred for making modifications. ++ ++1.14. "You" (or "Your") ++ means an individual or a legal entity exercising rights under this ++ License. For legal entities, "You" includes any entity that ++ controls, is controlled by, or is under common control with You. For ++ purposes of this definition, "control" means (a) the power, direct ++ or indirect, to cause the direction or management of such entity, ++ whether by contract or otherwise, or (b) ownership of more than ++ fifty percent (50%) of the outstanding shares or beneficial ++ ownership of such entity. ++ ++2. License Grants and Conditions ++-------------------------------- ++ ++2.1. Grants ++ ++Each Contributor hereby grants You a world-wide, royalty-free, ++non-exclusive license: ++ ++(a) under intellectual property rights (other than patent or trademark) ++ Licensable by such Contributor to use, reproduce, make available, ++ modify, display, perform, distribute, and otherwise exploit its ++ Contributions, either on an unmodified basis, with Modifications, or ++ as part of a Larger Work; and ++ ++(b) under Patent Claims of such Contributor to make, use, sell, offer ++ for sale, have made, import, and otherwise transfer either its ++ Contributions or its Contributor Version. ++ ++2.2. Effective Date ++ ++The licenses granted in Section 2.1 with respect to any Contribution ++become effective for each Contribution on the date the Contributor first ++distributes such Contribution. ++ ++2.3. Limitations on Grant Scope ++ ++The licenses granted in this Section 2 are the only rights granted under ++this License. No additional rights or licenses will be implied from the ++distribution or licensing of Covered Software under this License. ++Notwithstanding Section 2.1(b) above, no patent license is granted by a ++Contributor: ++ ++(a) for any code that a Contributor has removed from Covered Software; ++ or ++ ++(b) for infringements caused by: (i) Your and any other third party's ++ modifications of Covered Software, or (ii) the combination of its ++ Contributions with other software (except as part of its Contributor ++ Version); or ++ ++(c) under Patent Claims infringed by Covered Software in the absence of ++ its Contributions. ++ ++This License does not grant any rights in the trademarks, service marks, ++or logos of any Contributor (except as may be necessary to comply with ++the notice requirements in Section 3.4). ++ ++2.4. Subsequent Licenses ++ ++No Contributor makes additional grants as a result of Your choice to ++distribute the Covered Software under a subsequent version of this ++License (see Section 10.2) or under the terms of a Secondary License (if ++permitted under the terms of Section 3.3). ++ ++2.5. Representation ++ ++Each Contributor represents that the Contributor believes its ++Contributions are its original creation(s) or it has sufficient rights ++to grant the rights to its Contributions conveyed by this License. ++ ++2.6. Fair Use ++ ++This License is not intended to limit any rights You have under ++applicable copyright doctrines of fair use, fair dealing, or other ++equivalents. ++ ++2.7. Conditions ++ ++Sections 3.1, 3.2, 3.3, and 3.4 are conditions of the licenses granted ++in Section 2.1. ++ ++3. Responsibilities ++------------------- ++ ++3.1. Distribution of Source Form ++ ++All distribution of Covered Software in Source Code Form, including any ++Modifications that You create or to which You contribute, must be under ++the terms of this License. You must inform recipients that the Source ++Code Form of the Covered Software is governed by the terms of this ++License, and how they can obtain a copy of this License. You may not ++attempt to alter or restrict the recipients' rights in the Source Code ++Form. ++ ++3.2. Distribution of Executable Form ++ ++If You distribute Covered Software in Executable Form then: ++ ++(a) such Covered Software must also be made available in Source Code ++ Form, as described in Section 3.1, and You must inform recipients of ++ the Executable Form how they can obtain a copy of such Source Code ++ Form by reasonable means in a timely manner, at a charge no more ++ than the cost of distribution to the recipient; and ++ ++(b) You may distribute such Executable Form under the terms of this ++ License, or sublicense it under different terms, provided that the ++ license for the Executable Form does not attempt to limit or alter ++ the recipients' rights in the Source Code Form under this License. ++ ++3.3. Distribution of a Larger Work ++ ++You may create and distribute a Larger Work under terms of Your choice, ++provided that You also comply with the requirements of this License for ++the Covered Software. If the Larger Work is a combination of Covered ++Software with a work governed by one or more Secondary Licenses, and the ++Covered Software is not Incompatible With Secondary Licenses, this ++License permits You to additionally distribute such Covered Software ++under the terms of such Secondary License(s), so that the recipient of ++the Larger Work may, at their option, further distribute the Covered ++Software under the terms of either this License or such Secondary ++License(s). ++ ++3.4. Notices ++ ++You may not remove or alter the substance of any license notices ++(including copyright notices, patent notices, disclaimers of warranty, ++or limitations of liability) contained within the Source Code Form of ++the Covered Software, except that You may alter any license notices to ++the extent required to remedy known factual inaccuracies. ++ ++3.5. Application of Additional Terms ++ ++You may choose to offer, and to charge a fee for, warranty, support, ++indemnity or liability obligations to one or more recipients of Covered ++Software. However, You may do so only on Your own behalf, and not on ++behalf of any Contributor. You must make it absolutely clear that any ++such warranty, support, indemnity, or liability obligation is offered by ++You alone, and You hereby agree to indemnify every Contributor for any ++liability incurred by such Contributor as a result of warranty, support, ++indemnity or liability terms You offer. You may include additional ++disclaimers of warranty and limitations of liability specific to any ++jurisdiction. ++ ++4. Inability to Comply Due to Statute or Regulation ++--------------------------------------------------- ++ ++If it is impossible for You to comply with any of the terms of this ++License with respect to some or all of the Covered Software due to ++statute, judicial order, or regulation then You must: (a) comply with ++the terms of this License to the maximum extent possible; and (b) ++describe the limitations and the code they affect. Such description must ++be placed in a text file included with all distributions of the Covered ++Software under this License. Except to the extent prohibited by statute ++or regulation, such description must be sufficiently detailed for a ++recipient of ordinary skill to be able to understand it. ++ ++5. Termination ++-------------- ++ ++5.1. The rights granted under this License will terminate automatically ++if You fail to comply with any of its terms. However, if You become ++compliant, then the rights granted under this License from a particular ++Contributor are reinstated (a) provisionally, unless and until such ++Contributor explicitly and finally terminates Your grants, and (b) on an ++ongoing basis, if such Contributor fails to notify You of the ++non-compliance by some reasonable means prior to 60 days after You have ++come back into compliance. Moreover, Your grants from a particular ++Contributor are reinstated on an ongoing basis if such Contributor ++notifies You of the non-compliance by some reasonable means, this is the ++first time You have received notice of non-compliance with this License ++from such Contributor, and You become compliant prior to 30 days after ++Your receipt of the notice. ++ ++5.2. If You initiate litigation against any entity by asserting a patent ++infringement claim (excluding declaratory judgment actions, ++counter-claims, and cross-claims) alleging that a Contributor Version ++directly or indirectly infringes any patent, then the rights granted to ++You by any and all Contributors for the Covered Software under Section ++2.1 of this License shall terminate. ++ ++5.3. In the event of termination under Sections 5.1 or 5.2 above, all ++end user license agreements (excluding distributors and resellers) which ++have been validly granted by You or Your distributors under this License ++prior to termination shall survive termination. ++ ++************************************************************************ ++* * ++* 6. Disclaimer of Warranty * ++* ------------------------- * ++* * ++* Covered Software is provided under this License on an "as is" * ++* basis, without warranty of any kind, either expressed, implied, or * ++* statutory, including, without limitation, warranties that the * ++* Covered Software is free of defects, merchantable, fit for a * ++* particular purpose or non-infringing. The entire risk as to the * ++* quality and performance of the Covered Software is with You. * ++* Should any Covered Software prove defective in any respect, You * ++* (not any Contributor) assume the cost of any necessary servicing, * ++* repair, or correction. This disclaimer of warranty constitutes an * ++* essential part of this License. No use of any Covered Software is * ++* authorized under this License except under this disclaimer. * ++* * ++************************************************************************ ++ ++************************************************************************ ++* * ++* 7. Limitation of Liability * ++* -------------------------- * ++* * ++* Under no circumstances and under no legal theory, whether tort * ++* (including negligence), contract, or otherwise, shall any * ++* Contributor, or anyone who distributes Covered Software as * ++* permitted above, be liable to You for any direct, indirect, * ++* special, incidental, or consequential damages of any character * ++* including, without limitation, damages for lost profits, loss of * ++* goodwill, work stoppage, computer failure or malfunction, or any * ++* and all other commercial damages or losses, even if such party * ++* shall have been informed of the possibility of such damages. This * ++* limitation of liability shall not apply to liability for death or * ++* personal injury resulting from such party's negligence to the * ++* extent applicable law prohibits such limitation. Some * ++* jurisdictions do not allow the exclusion or limitation of * ++* incidental or consequential damages, so this exclusion and * ++* limitation may not apply to You. * ++* * ++************************************************************************ ++ ++8. Litigation ++------------- ++ ++Any litigation relating to this License may be brought only in the ++courts of a jurisdiction where the defendant maintains its principal ++place of business and such litigation shall be governed by laws of that ++jurisdiction, without reference to its conflict-of-law provisions. ++Nothing in this Section shall prevent a party's ability to bring ++cross-claims or counter-claims. ++ ++9. Miscellaneous ++---------------- ++ ++This License represents the complete agreement concerning the subject ++matter hereof. If any provision of this License is held to be ++unenforceable, such provision shall be reformed only to the extent ++necessary to make it enforceable. Any law or regulation which provides ++that the language of a contract shall be construed against the drafter ++shall not be used to construe this License against a Contributor. ++ ++10. Versions of the License ++--------------------------- ++ ++10.1. New Versions ++ ++Mozilla Foundation is the license steward. Except as provided in Section ++10.3, no one other than the license steward has the right to modify or ++publish new versions of this License. Each version will be given a ++distinguishing version number. ++ ++10.2. Effect of New Versions ++ ++You may distribute the Covered Software under the terms of the version ++of the License under which You originally received the Covered Software, ++or under the terms of any subsequent version published by the license ++steward. ++ ++10.3. Modified Versions ++ ++If you create software not governed by this License, and you want to ++create a new license for such software, you may create and use a ++modified version of this License if you rename the license and remove ++any references to the name of the license steward (except to note that ++such modified license differs from this License). ++ ++10.4. Distributing Source Code Form that is Incompatible With Secondary ++Licenses ++ ++If You choose to distribute Source Code Form that is Incompatible With ++Secondary Licenses under the terms of this version of the License, the ++notice described in Exhibit B of this License must be attached. ++ ++Exhibit A - Source Code Form License Notice ++------------------------------------------- ++ ++ This Source Code Form is subject to the terms of the Mozilla Public ++ License, v. 2.0. If a copy of the MPL was not distributed with this ++ file, You can obtain one at http://mozilla.org/MPL/2.0/. ++ ++If it is not possible or desirable to put the notice in a particular ++file, then You may include the notice in a location (such as a LICENSE ++file in a relevant directory) where a recipient would be likely to look ++for such a notice. ++ ++You may add additional accurate notices of copyright ownership. ++ ++Exhibit B - "Incompatible With Secondary Licenses" Notice ++--------------------------------------------------------- ++ ++ This Source Code Form is "Incompatible With Secondary Licenses", as ++ defined by the Mozilla Public License, v. 2.0. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to PC/SC Lite v1.8.26, ++which may be included with JRE 8, JDK 8, and OpenJDK 8 on Linux and Solaris. ++ ++--- begin of LICENSE --- ++ ++Copyright (c) 1999-2003 David Corcoran ++Copyright (c) 2001-2011 Ludovic Rousseau ++All rights reserved. ++ ++Redistribution and use in source and binary forms, with or without ++modification, are permitted provided that the following conditions ++are met: ++ ++1. Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++2. Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++3. The name of the author may not be used to endorse or promote products ++ derived from this software without specific prior written permission. ++ ++Changes to this license can be made only by the copyright author with ++explicit written consent. ++ ++THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to PorterStemmer v4, which may be ++included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++See: http://tartarus.org/~martin/PorterStemmer ++ ++The software is completely free for any purpose, unless notes at the head of ++the program text indicates otherwise (which is rare). In any case, the notes ++about licensing are never more restrictive than the BSD License. ++ ++In every case where the software is not written by me (Martin Porter), this ++licensing arrangement has been endorsed by the contributor, and it is ++therefore unnecessary to ask the contributor again to confirm it. ++ ++I have not asked any contributors (or their employers, if they have them) for ++proofs that they have the right to distribute their software in this way. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Relax NG Object/Parser v.20050510, ++which may be included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++Copyright (c) Kohsuke Kawaguchi ++ ++Permission is hereby granted, free of charge, to any person obtaining a copy ++of this software and associated documentation files (the "Software"), to deal ++in the Software without restriction, including without limitation the rights ++to use, copy, modify, merge, publish, distribute, sublicense, and/or sell ++copies of the Software, and to permit persons to whom the Software is ++furnished to do so, subject to the following conditions: The above copyright ++notice and this permission notice shall be included in all copies or ++substantial portions of the Software. ++ ++THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE ++AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ++LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, ++OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE ++SOFTWARE. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to RelaxNGCC v1.12, which may be ++included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++Copyright (c) 2000-2003 Daisuke Okajima and Kohsuke Kawaguchi. ++All rights reserved. ++ ++Redistribution and use in source and binary forms, with or without ++modification, are permitted provided that the following conditions are met: ++ ++1. Redistributions of source code must retain the above copyright notice, this ++ list of conditions and the following disclaimer. ++ ++2. Redistributions in binary form must reproduce the above copyright notice, ++ this list of conditions and the following disclaimer in the documentation ++ and/or other materials provided with the distribution. ++ ++3. The end-user documentation included with the redistribution, if any, must ++ include the following acknowledgment: ++ ++ "This product includes software developed by Daisuke Okajima ++ and Kohsuke Kawaguchi (http://relaxngcc.sf.net/)." ++ ++Alternately, this acknowledgment may appear in the software itself, if and ++wherever such third-party acknowledgments normally appear. ++ ++4. The names of the copyright holders must not be used to endorse or promote ++ products derived from this software without prior written permission. For ++ written permission, please contact the copyright holders. ++ ++5. Products derived from this software may not be called "RELAXNGCC", nor may ++ "RELAXNGCC" appear in their name, without prior written permission of the ++ copyright holders. ++ ++THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESSED OR IMPLIED WARRANTIES, ++INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND ++FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.IN NO EVENT SHALL THE APACHE ++SOFTWARE FOUNDATION OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ++INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ++EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Relax NG Datatype 1.0, which ++may be included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++Copyright (c) 2005, 2010 Thai Open Source Software Center Ltd ++All rights reserved. ++ ++Redistribution and use in source and binary forms, with or without ++modification, are permitted provided that the following conditions are ++met: ++ ++ Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ Neither the names of the copyright holders nor the names of its ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR ++CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++--- end of LICENSE --- ++ ++-------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to SoftFloat version 2b, which may be ++included with JRE 8, JDK 8, and OpenJDK 8 on Linux/ARM. ++ ++--- begin of LICENSE --- ++ ++Use of any of this software is governed by the terms of the license below: ++ ++SoftFloat was written by me, John R. Hauser. This work was made possible in ++part by the International Computer Science Institute, located at Suite 600, ++1947 Center Street, Berkeley, California 94704. Funding was partially ++provided by the National Science Foundation under grant MIP-9311980. The ++original version of this code was written as part of a project to build ++a fixed-point vector processor in collaboration with the University of ++California at Berkeley, overseen by Profs. Nelson Morgan and John Wawrzynek. ++ ++THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort ++has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT ++TIMES RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO ++PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL ++LOSSES, COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO ++FURTHERMORE EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER ++SCIENCE INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES, ++COSTS, OR OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE ++SOFTWARE. ++ ++Derivative works are acceptable, even for commercial purposes, provided ++that the minimal documentation requirements stated in the source code are ++satisfied. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Sparkle 1.5, ++which may be included with JRE 8 on Mac OS X. ++ ++--- begin of LICENSE --- ++ ++Copyright (c) 2012 Sparkle.org and Andy Matuschak ++ ++Permission is hereby granted, free of charge, to any person obtaining a copy ++of this software and associated documentation files (the "Software"), to deal ++in the Software without restriction, including without limitation the rights ++to use, copy, modify, merge, publish, distribute, sublicense, and/or sell ++copies of the Software, and to permit persons to whom the Software is ++furnished to do so, subject to the following conditions: ++ ++The above copyright notice and this permission notice shall be included in all ++copies or substantial portions of the Software. ++ ++THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 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Distributed under the ++Terms of Use in http://www.unicode.org/copyright.html. ++ ++Permission is hereby granted, free of charge, to any person obtaining a copy ++of the Unicode data files and any associated documentation (the "Data Files") ++or Unicode software and any associated documentation (the "Software") to deal ++in the Data Files or Software without restriction, including without ++limitation the rights to use, copy, modify, merge, publish, distribute, and/or ++sell copies of the Data Files or Software, and to permit persons to whom the ++Data Files or Software are furnished to do so, provided that (a) the above ++copyright notice(s) and this permission notice appear with all copies of the ++Data Files or Software, (b) both the above copyright notice(s) and this ++permission notice appear in associated documentation, and (c) there is clear ++notice in each modified Data File or in the Software as well as in the ++documentation associated with the Data File(s) or Software that the data or ++software has been modified. ++ ++THE DATA FILES AND SOFTWARE ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY ++KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT OF THIRD ++PARTY RIGHTS. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR HOLDERS INCLUDED IN ++THIS NOTICE BE LIABLE FOR ANY CLAIM, OR ANY SPECIAL INDIRECT OR CONSEQUENTIAL ++DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR ++PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ++ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THE ++DATA FILES OR SOFTWARE. ++ ++Except as contained in this notice, the name of a copyright holder shall not ++be used in advertising or otherwise to promote the sale, use or other dealings ++in these Data Files or Software without prior written authorization of the ++copyright holder. ++ ++Unicode and the Unicode logo are trademarks of Unicode, Inc. in the United ++States and other countries. All third party trademarks referenced herein are ++the property of their respective owners. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to UPX v3.01, which may be included ++with JRE 8 on Windows. ++ ++--- begin of LICENSE --- ++ ++Use of any of this software is governed by the terms of the license below: ++ ++ ++ ooooo ooo ooooooooo. ooooooo ooooo ++ `888' `8' `888 `Y88. `8888 d8' ++ 888 8 888 .d88' Y888..8P ++ 888 8 888ooo88P' `8888' ++ 888 8 888 .8PY888. ++ `88. .8' 888 d8' `888b ++ `YbodP' o888o o888o o88888o ++ ++ ++ The Ultimate Packer for eXecutables ++ Copyright (c) 1996-2000 Markus Oberhumer & Laszlo Molnar ++ http://wildsau.idv.uni-linz.ac.at/mfx/upx.html ++ http://www.nexus.hu/upx ++ http://upx.tsx.org ++ ++ ++PLEASE CAREFULLY READ THIS LICENSE AGREEMENT, ESPECIALLY IF YOU PLAN ++TO MODIFY THE UPX SOURCE CODE OR USE A MODIFIED UPX VERSION. ++ ++ ++ABSTRACT ++======== ++ ++ UPX and UCL are copyrighted software distributed under the terms ++ of the GNU General Public License (hereinafter the "GPL"). ++ ++ The stub which is imbedded in each UPX compressed program is part ++ of UPX and UCL, and contains code that is under our copyright. The ++ terms of the GNU General Public License still apply as compressing ++ a program is a special form of linking with our stub. ++ ++ As a special exception we grant the free usage of UPX for all ++ executables, including commercial programs. ++ See below for details and restrictions. ++ ++ ++COPYRIGHT ++========= ++ ++ UPX and UCL are copyrighted software. All rights remain with the authors. ++ ++ UPX is Copyright (C) 1996-2000 Markus Franz Xaver Johannes Oberhumer ++ UPX is Copyright (C) 1996-2000 Laszlo Molnar ++ ++ UCL is Copyright (C) 1996-2000 Markus Franz Xaver Johannes Oberhumer ++ ++ ++GNU GENERAL PUBLIC LICENSE ++========================== ++ ++ UPX and the UCL library are free software; you can redistribute them ++ and/or modify them under the terms of the GNU General Public License as ++ published by the Free Software Foundation; either version 2 of ++ the License, or (at your option) any later version. ++ ++ UPX and UCL are distributed in the hope that they will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ GNU General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with this program; see the file COPYING. ++ ++ ++SPECIAL EXCEPTION FOR COMPRESSED EXECUTABLES ++============================================ ++ ++ The stub which is imbedded in each UPX compressed program is part ++ of UPX and UCL, and contains code that is under our copyright. The ++ terms of the GNU General Public License still apply as compressing ++ a program is a special form of linking with our stub. ++ ++ Hereby Markus F.X.J. Oberhumer and Laszlo Molnar grant you special ++ permission to freely use and distribute all UPX compressed programs ++ (including commercial ones), subject to the following restrictions: ++ ++ 1. You must compress your program with a completely unmodified UPX ++ version; either with our precompiled version, or (at your option) ++ with a self compiled version of the unmodified UPX sources as ++ distributed by us. ++ 2. This also implies that the UPX stub must be completely unmodfied, i.e. ++ the stub imbedded in your compressed program must be byte-identical ++ to the stub that is produced by the official unmodified UPX version. ++ 3. The decompressor and any other code from the stub must exclusively get ++ used by the unmodified UPX stub for decompressing your program at ++ program startup. No portion of the stub may get read, copied, ++ called or otherwise get used or accessed by your program. ++ ++ ++ANNOTATIONS ++=========== ++ ++ - You can use a modified UPX version or modified UPX stub only for ++ programs that are compatible with the GNU General Public License. ++ ++ - We grant you special permission to freely use and distribute all UPX ++ compressed programs. But any modification of the UPX stub (such as, ++ but not limited to, removing our copyright string or making your ++ program non-decompressible) will immediately revoke your right to ++ use and distribute a UPX compressed program. ++ ++ - UPX is not a software protection tool; by requiring that you use ++ the unmodified UPX version for your proprietary programs we ++ make sure that any user can decompress your program. This protects ++ both you and your users as nobody can hide malicious code - ++ any program that cannot be decompressed is highly suspicious ++ by definition. ++ ++ - You can integrate all or part of UPX and UCL into projects that ++ are compatible with the GNU GPL, but obviously you cannot grant ++ any special exceptions beyond the GPL for our code in your project. ++ ++ - We want to actively support manufacturers of virus scanners and ++ similar security software. Please contact us if you would like to ++ incorporate parts of UPX or UCL into such a product. ++ ++ ++ ++Markus F.X.J. Oberhumer Laszlo Molnar ++markus.oberhumer@jk.uni-linz.ac.at ml1050@cdata.tvnet.hu ++ ++Linz, Austria, 25 Feb 2000 ++ ++Additional License(s) ++ ++The UPX license file is at http://upx.sourceforge.net/upx-license.html. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Xfree86-VidMode Extension 1.0, ++which may be included with JRE 8, JDK 8, and OpenJDK 8 on Linux and Solaris. ++ ++--- begin of LICENSE --- ++ ++Version 1.1 of XFree86 ProjectLicence. ++ ++Copyright (C) 1994-2004 The XFree86 Project, Inc. All rights reserved. ++ ++Permission is hereby granted, free of charge, to any person obtaining a copy of ++this software and associated documentation files (the "Software"), to deal ++in the Software without restriction, including without limitation the rights ++to use, copy, modify, merge, publish, distribute, sublicence, and/or sell ++copies of the Software, and to permit persons to whom the Software is furnished ++to do so,subject to the following conditions: ++ ++ 1. Redistributions of source code must retain the above copyright ++ notice,this list of conditions, and the following disclaimer. ++ ++ 2. Redistributions in binary form must reproduce the above copyright notice, ++ this list of conditions and the following disclaimer in the documentation ++ and/or other materials provided with the distribution, and in the same place ++ and form as other copyright, license and disclaimer information. ++ ++ 3. The end-user documentation included with the redistribution, if any,must ++ include the following acknowledgment: "This product includes ++ software developed by The XFree86 Project, Inc (http://www.xfree86.org/) and ++ its contributors", in the same place and form as other third-party ++ acknowledgments. Alternately, this acknowledgment may appear in the software ++ itself, in the same form and location as other such third-party ++ acknowledgments. ++ ++ 4. Except as contained in this notice, the name of The XFree86 Project,Inc ++ shall not be used in advertising or otherwise to promote the sale, use ++ or other dealings in this Software without prior written authorization from ++ The XFree86 Project, Inc. ++ ++ THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESSED OR IMPLIED ++ WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF ++ MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO ++ EVENT SHALL THE XFREE86 PROJECT, INC OR ITS CONTRIBUTORS BE LIABLE FOR ANY ++ DIRECT, INDIRECT, INCIDENTAL,SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ (INCLUDING, BUT NOT LIMITED TO,PROCUREMENT OF SUBSTITUTE GOODS OR ++ SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ DAMAGE. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to xwd v1.0.7, which may be ++included with JRE 8, JDK 8, and OpenJDK 8 on Linux and Solaris. ++ ++xwd utility ++ ++--- begin of LICENSE --- ++ ++Copyright 1994 Hewlett-Packard Co. ++Copyright 1996, 1998 The Open Group ++ ++Permission to use, copy, modify, distribute, and sell this software and its ++documentation for any purpose is hereby granted without fee, provided that ++the above copyright notice appear in all copies and that both that ++copyright notice and this permission notice appear in supporting ++documentation. ++ ++The above copyright notice and this permission notice shall be included ++in all copies or substantial portions of the Software. ++ ++THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. ++IN NO EVENT SHALL THE OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR ++OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++OTHER DEALINGS IN THE SOFTWARE. ++ ++Except as contained in this notice, the name of The Open Group shall ++not be used in advertising or otherwise to promote the sale, use or ++other dealings in this Software without prior written authorization ++from The Open Group. ++ ++--- end of LICENSE --- ++_____________________________ ++Copyright notice for HPkeysym.h: ++/* ++ ++Copyright 1987, 1998 The Open Group ++ ++All Rights Reserved. ++ ++The above copyright notice and this permission notice shall be included ++in all copies or substantial portions of the Software. ++ ++THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. ++IN NO EVENT SHALL THE OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR ++OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++OTHER DEALINGS IN THE SOFTWARE. ++ ++Except as contained in this notice, the name of The Open Group shall ++not be used in advertising or otherwise to promote the sale, use or ++other dealings in this Software without prior written authorization ++from The Open Group. ++ ++Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts, ++ ++All Rights Reserved ++ ++Permission to use, copy, modify, and distribute this software and its ++documentation for any purpose and without fee is hereby granted, ++provided that the above copyright notice appear in all copies and that ++both that copyright notice and this permission notice appear in ++supporting documentation, and that the names of Hewlett Packard ++or Digital not be ++used in advertising or publicity pertaining to distribution of the ++software without specific, written prior permission. ++ ++DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING ++ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL ++DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ++ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, ++WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ++ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS ++SOFTWARE. ++ ++HEWLETT-PACKARD MAKES NO WARRANTY OF ANY KIND WITH REGARD ++TO THIS SOFWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++PURPOSE. Hewlett-Packard shall not be liable for errors ++contained herein or direct, indirect, special, incidental or ++consequential damages in connection with the furnishing, ++performance, or use of this material. ++ ++*/ ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to zlib v1.2.11, which may be included ++with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++ version 1.2.11, January 15th, 2017 ++ ++ Copyright (C) 1995-2017 Jean-loup Gailly and Mark Adler ++ ++ This software is provided 'as-is', without any express or implied ++ warranty. In no event will the authors be held liable for any damages ++ arising from the use of this software. ++ ++ Permission is granted to anyone to use this software for any purpose, ++ including commercial applications, and to alter it and redistribute it ++ freely, subject to the following restrictions: ++ ++ 1. The origin of this software must not be misrepresented; you must not ++ claim that you wrote the original software. If you use this software ++ in a product, an acknowledgment in the product documentation would be ++ appreciated but is not required. ++ 2. Altered source versions must be plainly marked as such, and must not be ++ misrepresented as being the original software. ++ 3. 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Copies of claims of rights made available for publication and ++any assurances of licenses to be made available, or the result of an ++attempt made to obtain a general license or permission for the use of ++such proprietary rights by implementers or users of this OASIS Standards ++Final Deliverable, can be obtained from the OASIS TC Administrator. ++OASIS makes no representation that any information or list of ++intellectual property rights will at any time be complete, or that any ++claims in such list are, in fact, Essential Claims.] ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- +diff --git a/hotspot/agent/make/Makefile b/hotspot/agent/make/Makefile +index 0f6210941b..061a51021c 100644 +--- a/hotspot/agent/make/Makefile ++++ b/hotspot/agent/make/Makefile +@@ -60,6 +60,7 @@ sun.jvm.hotspot.debugger.linux \ + sun.jvm.hotspot.debugger.linux.amd64 \ + sun.jvm.hotspot.debugger.linux.aarch64 \ + sun.jvm.hotspot.debugger.linux.x86 \ ++sun.jvm.hotspot.debugger.linux.sw64 \ + sun.jvm.hotspot.debugger.posix \ + sun.jvm.hotspot.debugger.posix.elf \ + sun.jvm.hotspot.debugger.proc \ +@@ -67,11 +68,14 @@ sun.jvm.hotspot.debugger.proc.amd64 \ + sun.jvm.hotspot.debugger.proc.aarch64 \ + sun.jvm.hotspot.debugger.proc.sparc \ + sun.jvm.hotspot.debugger.proc.x86 \ ++sun.jvm.hotspot.debugger.proc.sw64 \ + sun.jvm.hotspot.debugger.remote \ + sun.jvm.hotspot.debugger.remote.amd64 \ + sun.jvm.hotspot.debugger.remote.sparc \ ++sun.jvm.hotspot.debugger.remote.sw64 \ + sun.jvm.hotspot.debugger.remote.x86 \ + sun.jvm.hotspot.debugger.sparc \ ++sun.jvm.hotspot.debugger.sw64 \ + sun.jvm.hotspot.debugger.win32.coff \ + sun.jvm.hotspot.debugger.windbg \ + sun.jvm.hotspot.debugger.windbg.amd64 \ +@@ -98,12 +102,14 @@ sun.jvm.hotspot.runtime.linux \ + sun.jvm.hotspot.runtime.linux_amd64 \ + sun.jvm.hotspot.runtime.linux_aarch64 \ + sun.jvm.hotspot.runtime.linux_sparc \ ++sun.jvm.hotspot.runtime.linux_sw64 \ + sun.jvm.hotspot.runtime.linux_x86 \ + sun.jvm.hotspot.runtime.posix \ + sun.jvm.hotspot.runtime.solaris_amd64 \ + sun.jvm.hotspot.runtime.solaris_sparc \ + sun.jvm.hotspot.runtime.solaris_x86 \ + sun.jvm.hotspot.runtime.sparc \ ++sun.jvm.hotspot.runtime.sw64 \ + sun.jvm.hotspot.runtime.win32_amd64 \ + sun.jvm.hotspot.runtime.win32_x86 \ + sun.jvm.hotspot.runtime.x86 \ +@@ -146,6 +152,7 @@ sun/jvm/hotspot/debugger/cdbg/basic/amd64/*.java \ + sun/jvm/hotspot/debugger/cdbg/basic/x86/*.java \ + sun/jvm/hotspot/debugger/dummy/*.java \ + sun/jvm/hotspot/debugger/linux/*.java \ ++sun/jvm/hotspot/debugger/linux/sw64/*.java \ + sun/jvm/hotspot/debugger/linux/x86/*.java \ + sun/jvm/hotspot/debugger/linux/aarch64/*.java \ + sun/jvm/hotspot/debugger/posix/*.java \ +@@ -153,11 +160,13 @@ sun/jvm/hotspot/debugger/posix/elf/*.java \ + sun/jvm/hotspot/debugger/proc/*.java \ + sun/jvm/hotspot/debugger/proc/amd64/*.java \ + sun/jvm/hotspot/debugger/proc/sparc/*.java \ ++sun/jvm/hotspot/debugger/proc/sw64/*.java \ + sun/jvm/hotspot/debugger/proc/x86/*.java \ + sun/jvm/hotspot/debugger/proc/aarch64/*.java \ + sun/jvm/hotspot/debugger/remote/*.java \ + sun/jvm/hotspot/debugger/remote/amd64/*.java \ + sun/jvm/hotspot/debugger/remote/sparc/*.java \ ++sun/jvm/hotspot/debugger/remote/sw64/*.java \ + sun/jvm/hotspot/debugger/remote/x86/*.java \ + sun/jvm/hotspot/debugger/sparc/*.java \ + sun/jvm/hotspot/debugger/win32/coff/*.java \ +@@ -183,12 +192,14 @@ sun/jvm/hotspot/runtime/linux/*.java \ + sun/jvm/hotspot/runtime/linux_amd64/*.java \ + sun/jvm/hotspot/runtime/linux_aarch64/*.java \ + sun/jvm/hotspot/runtime/linux_sparc/*.java \ ++sun/jvm/hotspot/runtime/linux_sw64/*.java \ + sun/jvm/hotspot/runtime/linux_x86/*.java \ + sun/jvm/hotspot/runtime/posix/*.java \ + sun/jvm/hotspot/runtime/solaris_amd64/*.java \ + sun/jvm/hotspot/runtime/solaris_sparc/*.java \ + sun/jvm/hotspot/runtime/solaris_x86/*.java \ + sun/jvm/hotspot/runtime/sparc/*.java \ ++sun/jvm/hotspot/runtime/sw64/*.java \ + sun/jvm/hotspot/runtime/win32_amd64/*.java \ + sun/jvm/hotspot/runtime/win32_x86/*.java \ + sun/jvm/hotspot/runtime/x86/*.java \ +diff --git a/hotspot/agent/make/saenv.sh b/hotspot/agent/make/saenv.sh +index ab9a0a431c..c3e4f9bb7b 100644 +--- a/hotspot/agent/make/saenv.sh ++++ b/hotspot/agent/make/saenv.sh +@@ -42,6 +42,10 @@ if [ "$OS" = "Linux" ]; then + SA_LIBPATH=$STARTDIR/../src/os/linux/amd64:$STARTDIR/linux/amd64 + OPTIONS="-Dsa.library.path=$SA_LIBPATH" + CPU=amd64 ++ elif [ "$ARCH" = "sw_64" ] ; then ++ SA_LIBPATH=$STARTDIR/../src/os/linux/sw64:$STARTDIR/linux/sw64 ++ OPTIONS="-Dsa.library.path=$SA_LIBPATH" ++ CPU=sw64 + else + SA_LIBPATH=$STARTDIR/../src/os/linux/i386:$STARTDIR/linux/i386 + OPTIONS="-Dsa.library.path=$SA_LIBPATH" +diff --git a/hotspot/agent/src/os/linux/LinuxDebuggerLocal.c b/hotspot/agent/src/os/linux/LinuxDebuggerLocal.c +index d6a0c7d9a9..a8d8ca307f 100644 +--- a/hotspot/agent/src/os/linux/LinuxDebuggerLocal.c ++++ b/hotspot/agent/src/os/linux/LinuxDebuggerLocal.c +@@ -49,6 +49,10 @@ + #include "sun_jvm_hotspot_debugger_sparc_SPARCThreadContext.h" + #endif + ++#ifdef sw64 ++#include "sun_jvm_hotspot_debugger_sw64_SW64ThreadContext.h" ++#endif ++ + #ifdef aarch64 + #include "sun_jvm_hotspot_debugger_aarch64_AARCH64ThreadContext.h" + #endif +@@ -337,7 +341,7 @@ JNIEXPORT jbyteArray JNICALL Java_sun_jvm_hotspot_debugger_linux_LinuxDebuggerLo + return (err == PS_OK)? array : 0; + } + +-#if defined(i386) || defined(amd64) || defined(sparc) || defined(sparcv9) || defined(aarch64) ++#if defined(i386) || defined(amd64) || defined(sparc) || defined(sparcv9) || defined(aarch64) || defined(sw64) + JNIEXPORT jlongArray JNICALL Java_sun_jvm_hotspot_debugger_linux_LinuxDebuggerLocal_getThreadIntegerRegisterSet0 + (JNIEnv *env, jobject this_obj, jint lwp_id) { + +@@ -364,6 +368,9 @@ JNIEXPORT jlongArray JNICALL Java_sun_jvm_hotspot_debugger_linux_LinuxDebuggerLo + #endif + #if defined(sparc) || defined(sparcv9) + #define NPRGREG sun_jvm_hotspot_debugger_sparc_SPARCThreadContext_NPRGREG ++#endif ++#ifdef sw64 ++#define NPRGREG sun_jvm_hotspot_debugger_sw64_SW64ThreadContext_NPRGREG + #endif + + array = (*env)->NewLongArray(env, NPRGREG); +@@ -457,6 +464,44 @@ JNIEXPORT jlongArray JNICALL Java_sun_jvm_hotspot_debugger_linux_LinuxDebuggerLo + regs[REG_INDEX(R_O7)] = gregs.u_regs[14]; + #endif /* sparc */ + ++#ifdef sw64 ++ ++#define REG_INDEX(reg) sun_jvm_hotspot_debugger_sw64_SW64ThreadContext_##reg ++ ++ regs[REG_INDEX(V0)] = gregs.regs[0]; ++ regs[REG_INDEX(T0)] = gregs.regs[1]; ++ regs[REG_INDEX(T1)] = gregs.regs[2]; ++ regs[REG_INDEX(T2)] = gregs.regs[3]; ++ regs[REG_INDEX(T3)] = gregs.regs[4]; ++ regs[REG_INDEX(T4)] = gregs.regs[5]; ++ regs[REG_INDEX(T5)] = gregs.regs[6]; ++ regs[REG_INDEX(T6)] = gregs.regs[7]; ++ regs[REG_INDEX(T7)] = gregs.regs[8]; ++ regs[REG_INDEX(S0)] = gregs.regs[9]; ++ regs[REG_INDEX(S1)] = gregs.regs[10]; ++ regs[REG_INDEX(S2)] = gregs.regs[11]; ++ regs[REG_INDEX(S3)] = gregs.regs[12]; ++ regs[REG_INDEX(S4)] = gregs.regs[13]; ++ regs[REG_INDEX(S5)] = gregs.regs[14]; ++ regs[REG_INDEX(FP)] = gregs.regs[15]; ++ regs[REG_INDEX(A3)] = gregs.regs[16]; ++ regs[REG_INDEX(A4)] = gregs.regs[17]; ++ regs[REG_INDEX(A5)] = gregs.regs[18]; ++ regs[REG_INDEX(T8)] = gregs.regs[19]; ++ regs[REG_INDEX(T9)] = gregs.regs[20]; ++ regs[REG_INDEX(T10)] = gregs.regs[21]; ++ regs[REG_INDEX(T11)] = gregs.regs[22]; ++ regs[REG_INDEX(RA)] = gregs.regs[23]; ++ regs[REG_INDEX(T12)] = gregs.regs[24]; ++ regs[REG_INDEX(AT)] = gregs.regs[25]; ++ regs[REG_INDEX(SP)] = gregs.sp; ++ regs[REG_INDEX(PS)] = gregs.ps; ++ regs[REG_INDEX(PC)] = gregs.pc; ++ regs[REG_INDEX(GP)] = gregs.gp; ++ regs[REG_INDEX(A0)] = gregs.r_regs[0]; ++ regs[REG_INDEX(A1)] = gregs.r_regs[1]; ++ regs[REG_INDEX(A2)] = gregs.r_regs[2]; ++#endif /* sw64 */ + #if defined(aarch64) + + #define REG_INDEX(reg) sun_jvm_hotspot_debugger_aarch64_AARCH64ThreadContext_##reg +diff --git a/hotspot/agent/src/os/linux/Makefile b/hotspot/agent/src/os/linux/Makefile +index c0b5c869c1..7094b552c8 100644 +--- a/hotspot/agent/src/os/linux/Makefile ++++ b/hotspot/agent/src/os/linux/Makefile +@@ -53,8 +53,9 @@ $(ARCH)/LinuxDebuggerLocal.o: LinuxDebuggerLocal.c + $(JAVAH) -jni -classpath ../../../build/classes -d $(ARCH) \ + sun.jvm.hotspot.debugger.x86.X86ThreadContext \ + sun.jvm.hotspot.debugger.sparc.SPARCThreadContext \ ++ sun.jvm.hotspot.debugger.sw64.SW64ThreadContext \ + sun.jvm.hotspot.debugger.amd64.AMD64ThreadContext \ +- sun.jvm.hotspot.debugger.aarch64.AARCH64ThreadContext ++ sun.jvm.hotspot.debugger.aarch64.AARCH64ThreadContext + $(GCC) $(CFLAGS) $< -o $@ + + $(ARCH)/sadis.o: ../../share/native/sadis.c +diff --git a/hotspot/agent/src/os/linux/libproc.h b/hotspot/agent/src/os/linux/libproc.h +index 6b6e41cab4..c6987ab312 100644 +--- a/hotspot/agent/src/os/linux/libproc.h ++++ b/hotspot/agent/src/os/linux/libproc.h +@@ -80,6 +80,21 @@ combination of ptrace and /proc calls. + #define user_regs_struct user_pt_regs + #endif + ++#if defined(sw64) ++struct j_user_regs_struct { ++ // V0, T0-T7, S0-S5, FP, A3-A5, ++ // T8-T11, RA, T12, AT ++ unsigned long regs[26]; ++ unsigned long sp; ++ unsigned long ps; ++ unsigned long pc; ++ unsigned long gp; ++ // remainder regs (A0-A2) ++ unsigned long r_regs[3]; ++}; ++#define user_regs_struct j_user_regs_struct ++#endif ++ + // This C bool type must be int for compatibility with Linux calls and + // it would be a mistake to equivalence it to C++ bool on many platforms + +diff --git a/hotspot/agent/src/os/linux/libproc_impl.h b/hotspot/agent/src/os/linux/libproc_impl.h +index 1d25a0922b..e423905970 100644 +--- a/hotspot/agent/src/os/linux/libproc_impl.h ++++ b/hotspot/agent/src/os/linux/libproc_impl.h +@@ -32,6 +32,13 @@ + + // data structures in this file mimic those of Solaris 8.0 - libproc's Pcontrol.h + ++#ifndef NAME_MAX ++#define NAME_MAX 255 /* # chars in a file name */ ++#endif ++#ifndef PATH_MAX ++#define PATH_MAX 4096 /* # chars in a path name including nul */ ++#endif ++ + #define BUF_SIZE (PATH_MAX + NAME_MAX + 1) + + // list of shared objects +diff --git a/hotspot/agent/src/share/classes/sun/jvm/hotspot/HotSpotAgent.java b/hotspot/agent/src/share/classes/sun/jvm/hotspot/HotSpotAgent.java +index c963350591..23266427fa 100644 +--- a/hotspot/agent/src/share/classes/sun/jvm/hotspot/HotSpotAgent.java ++++ b/hotspot/agent/src/share/classes/sun/jvm/hotspot/HotSpotAgent.java +@@ -34,6 +34,7 @@ import sun.jvm.hotspot.debugger.JVMDebugger; + import sun.jvm.hotspot.debugger.MachineDescription; + import sun.jvm.hotspot.debugger.MachineDescriptionAMD64; + import sun.jvm.hotspot.debugger.MachineDescriptionIA64; ++import sun.jvm.hotspot.debugger.MachineDescriptionSW64; + import sun.jvm.hotspot.debugger.MachineDescriptionIntelX86; + import sun.jvm.hotspot.debugger.MachineDescriptionSPARC32Bit; + import sun.jvm.hotspot.debugger.MachineDescriptionSPARC64Bit; +@@ -588,6 +589,8 @@ public class HotSpotAgent { + machDesc = new MachineDescriptionIA64(); + } else if (cpu.equals("amd64")) { + machDesc = new MachineDescriptionAMD64(); ++ } else if (cpu.equals("sw64")) { ++ machDesc = new MachineDescriptionSW64(); + } else if (cpu.equals("sparc")) { + if (LinuxDebuggerLocal.getAddressSize()==8) { + machDesc = new MachineDescriptionSPARC64Bit(); +diff --git a/hotspot/agent/src/share/classes/sun/jvm/hotspot/debugger/MachineDescriptionSW64.java b/hotspot/agent/src/share/classes/sun/jvm/hotspot/debugger/MachineDescriptionSW64.java +new file mode 100644 +index 0000000000..17d8877896 +--- /dev/null ++++ b/hotspot/agent/src/share/classes/sun/jvm/hotspot/debugger/MachineDescriptionSW64.java +@@ -0,0 +1,39 @@ ++/* ++ * Copyright (c) 2003, 2008, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++package sun.jvm.hotspot.debugger; ++ ++public class MachineDescriptionSW64 extends MachineDescriptionTwosComplement implements MachineDescription { ++ public long getAddressSize() { ++ return 8; ++ } ++ ++ public boolean isLP64() { ++ return true; ++ } ++ ++ public boolean isBigEndian() { ++ return false; ++ } ++} +diff --git a/hotspot/agent/src/share/classes/sun/jvm/hotspot/debugger/linux/LinuxCDebugger.java b/hotspot/agent/src/share/classes/sun/jvm/hotspot/debugger/linux/LinuxCDebugger.java +index f178d6a6e7..e81c4376eb 100644 +--- a/hotspot/agent/src/share/classes/sun/jvm/hotspot/debugger/linux/LinuxCDebugger.java ++++ b/hotspot/agent/src/share/classes/sun/jvm/hotspot/debugger/linux/LinuxCDebugger.java +@@ -31,9 +31,11 @@ import sun.jvm.hotspot.debugger.*; + import sun.jvm.hotspot.debugger.cdbg.*; + import sun.jvm.hotspot.debugger.x86.*; + import sun.jvm.hotspot.debugger.amd64.*; ++import sun.jvm.hotspot.debugger.sw64.*; + import sun.jvm.hotspot.debugger.sparc.*; + import sun.jvm.hotspot.debugger.linux.x86.*; + import sun.jvm.hotspot.debugger.linux.amd64.*; ++import sun.jvm.hotspot.debugger.linux.sw64.*; + import sun.jvm.hotspot.debugger.aarch64.*; + import sun.jvm.hotspot.debugger.linux.aarch64.*; + import sun.jvm.hotspot.debugger.linux.sparc.*; +@@ -106,6 +108,13 @@ class LinuxCDebugger implements CDebugger { + Address pc = context.getRegisterAsAddress(AARCH64ThreadContext.PC); + if (pc == null) return null; + return new LinuxAARCH64CFrame(dbg, fp, pc); ++ } else if (cpu.equals("sw64")) { ++ SW64ThreadContext context = (SW64ThreadContext) thread.getContext(); ++ Address sp = context.getRegisterAsAddress(SW64ThreadContext.SP); ++ if (sp == null) return null; ++ Address pc = context.getRegisterAsAddress(SW64ThreadContext.PC); ++ if (pc == null) return null; ++ return new LinuxSW64CFrame(dbg, sp, pc); + } else { + // Runtime exception thrown by LinuxThreadContextFactory if unknown cpu + ThreadContext context = (ThreadContext) thread.getContext(); +diff --git a/hotspot/agent/src/share/classes/sun/jvm/hotspot/debugger/linux/LinuxDebuggerLocal.java b/hotspot/agent/src/share/classes/sun/jvm/hotspot/debugger/linux/LinuxDebuggerLocal.java +index f282a228df..7a85d9d9e4 100644 +--- a/hotspot/agent/src/share/classes/sun/jvm/hotspot/debugger/linux/LinuxDebuggerLocal.java ++++ b/hotspot/agent/src/share/classes/sun/jvm/hotspot/debugger/linux/LinuxDebuggerLocal.java +@@ -212,6 +212,8 @@ public class LinuxDebuggerLocal extends DebuggerBase implements LinuxDebugger { + // (FIXME: should pick this up from the debugger.) + if (getCPU().equals("ia64")) { + initCache(16384, parseCacheNumPagesProperty(1024)); ++ } else if (getCPU().equals("sw64") || getCPU().equals("sw_64")) { ++ initCache(8192, parseCacheNumPagesProperty(2048)); // = 16*1024*1024/8192 + } else { + initCache(4096, parseCacheNumPagesProperty(4096)); + } +diff --git a/hotspot/agent/src/share/classes/sun/jvm/hotspot/debugger/linux/sw64/LinuxSW64CFrame.java b/hotspot/agent/src/share/classes/sun/jvm/hotspot/debugger/linux/sw64/LinuxSW64CFrame.java +new file mode 100755 +index 0000000000..1b1d3c5a6a +--- /dev/null ++++ b/hotspot/agent/src/share/classes/sun/jvm/hotspot/debugger/linux/sw64/LinuxSW64CFrame.java +@@ -0,0 +1,80 @@ ++/* ++ * Copyright (c) 2003, 2012, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++package sun.jvm.hotspot.debugger.linux.sw64; ++ ++import sun.jvm.hotspot.debugger.*; ++import sun.jvm.hotspot.debugger.linux.*; ++import sun.jvm.hotspot.debugger.cdbg.*; ++import sun.jvm.hotspot.debugger.cdbg.basic.*; ++import sun.jvm.hotspot.debugger.sw64.*; ++ ++final public class LinuxSW64CFrame extends BasicCFrame { ++ // package/class internals only ++ public LinuxSW64CFrame(LinuxDebugger dbg, Address fp, Address pc) { ++ super(dbg.getCDebugger()); ++ this.fp = fp; ++ this.pc = pc; ++ this.dbg = dbg; ++ } ++ ++ // override base class impl to avoid ELF parsing ++ public ClosestSymbol closestSymbolToPC() { ++ // try native lookup in debugger. ++ return dbg.lookup(dbg.getAddressValue(pc())); ++ } ++ ++ public Address pc() { ++ return pc; ++ } ++ ++ public Address localVariableBase() { ++ return fp; ++ } ++ ++ public CFrame sender(ThreadProxy thread) { ++ SW64ThreadContext context = (SW64ThreadContext) thread.getContext(); ++ Address rsp = context.getRegisterAsAddress(SW64ThreadContext.SP); ++ ++ if ( (fp == null) || fp.lessThan(rsp) ) { ++ return null; ++ } ++ ++ Address nextPC = fp.getAddressAt( 0 * ADDRESS_SIZE); ++ if (nextPC == null) { ++ return null; ++ } ++ Address nextFP = fp.getAddressAt( 1 * ADDRESS_SIZE); ++ if (nextFP == null) { ++ return null; ++ } ++ return new LinuxSW64CFrame(dbg, nextFP, nextPC); ++ } ++ ++ // package/class internals only ++ private static final int ADDRESS_SIZE = 8; ++ private Address pc; ++ private Address fp; ++ private LinuxDebugger dbg; ++} +diff --git a/hotspot/agent/src/share/classes/sun/jvm/hotspot/debugger/linux/sw64/LinuxSW64ThreadContext.java b/hotspot/agent/src/share/classes/sun/jvm/hotspot/debugger/linux/sw64/LinuxSW64ThreadContext.java +new file mode 100755 +index 0000000000..b1e04689fe +--- /dev/null ++++ b/hotspot/agent/src/share/classes/sun/jvm/hotspot/debugger/linux/sw64/LinuxSW64ThreadContext.java +@@ -0,0 +1,46 @@ ++/* ++ * Copyright (c) 2003, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++package sun.jvm.hotspot.debugger.linux.sw64; ++ ++import sun.jvm.hotspot.debugger.*; ++import sun.jvm.hotspot.debugger.sw64.*; ++import sun.jvm.hotspot.debugger.linux.*; ++ ++public class LinuxSW64ThreadContext extends SW64ThreadContext { ++ private LinuxDebugger debugger; ++ ++ public LinuxSW64ThreadContext(LinuxDebugger debugger) { ++ super(); ++ this.debugger = debugger; ++ } ++ ++ public void setRegisterAsAddress(int index, Address value) { ++ setRegister(index, debugger.getAddressValue(value)); ++ } ++ ++ public Address getRegisterAsAddress(int index) { ++ return debugger.newAddress(getRegister(index)); ++ } ++} +diff --git a/hotspot/agent/src/share/classes/sun/jvm/hotspot/debugger/proc/ProcDebuggerLocal.java b/hotspot/agent/src/share/classes/sun/jvm/hotspot/debugger/proc/ProcDebuggerLocal.java +index ca1a2575ff..28b3f7af4f 100644 +--- a/hotspot/agent/src/share/classes/sun/jvm/hotspot/debugger/proc/ProcDebuggerLocal.java ++++ b/hotspot/agent/src/share/classes/sun/jvm/hotspot/debugger/proc/ProcDebuggerLocal.java +@@ -33,10 +33,12 @@ import sun.jvm.hotspot.debugger.cdbg.*; + import sun.jvm.hotspot.debugger.proc.amd64.*; + import sun.jvm.hotspot.debugger.proc.aarch64.*; + import sun.jvm.hotspot.debugger.proc.sparc.*; ++import sun.jvm.hotspot.debugger.proc.sw64.*; + import sun.jvm.hotspot.debugger.proc.x86.*; + import sun.jvm.hotspot.debugger.amd64.*; + import sun.jvm.hotspot.debugger.aarch64.*; + import sun.jvm.hotspot.debugger.sparc.*; ++import sun.jvm.hotspot.debugger.sw64.*; + import sun.jvm.hotspot.debugger.x86.*; + import sun.jvm.hotspot.utilities.*; + +@@ -88,6 +90,10 @@ public class ProcDebuggerLocal extends DebuggerBase implements ProcDebugger { + threadFactory = new ProcAMD64ThreadFactory(this); + pcRegIndex = AMD64ThreadContext.RIP; + fpRegIndex = AMD64ThreadContext.RBP; ++ } else if (cpu.equals("sw64") || cpu.equals("sw_64")) { ++ threadFactory = new ProcSW64ThreadFactory(this); ++ pcRegIndex = SW64ThreadContext.PC; ++ fpRegIndex = SW64ThreadContext.FP; + } else if (cpu.equals("aarch64")) { + threadFactory = new ProcAARCH64ThreadFactory(this); + pcRegIndex = AARCH64ThreadContext.PC; +@@ -398,8 +404,9 @@ public class ProcDebuggerLocal extends DebuggerBase implements ProcDebugger { + if (pagesize == -1) { + // return the hard coded default value. + if (PlatformInfo.getCPU().equals("sparc") || ++ PlatformInfo.getCPU().equals("sw64") || PlatformInfo.getCPU().equals("sw_64") || + PlatformInfo.getCPU().equals("amd64") ) +- pagesize = 8196; ++ pagesize = 8192; + else + pagesize = 4096; + } +diff --git a/hotspot/agent/src/share/classes/sun/jvm/hotspot/debugger/proc/sw64/ProcSW64Thread.java b/hotspot/agent/src/share/classes/sun/jvm/hotspot/debugger/proc/sw64/ProcSW64Thread.java +new file mode 100755 +index 0000000000..8ea0b218ab +--- /dev/null ++++ b/hotspot/agent/src/share/classes/sun/jvm/hotspot/debugger/proc/sw64/ProcSW64Thread.java +@@ -0,0 +1,87 @@ ++/* ++ * Copyright (c) 2002, 2003, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++package sun.jvm.hotspot.debugger.proc.sw64; ++ ++import sun.jvm.hotspot.debugger.*; ++import sun.jvm.hotspot.debugger.sw64.*; ++import sun.jvm.hotspot.debugger.proc.*; ++import sun.jvm.hotspot.utilities.*; ++ ++public class ProcSW64Thread implements ThreadProxy { ++ private ProcDebugger debugger; ++ private int id; ++ ++ public ProcSW64Thread(ProcDebugger debugger, Address addr) { ++ this.debugger = debugger; ++ ++ // FIXME: the size here should be configurable. However, making it ++ // so would produce a dependency on the "types" package from the ++ // debugger package, which is not desired. ++ this.id = (int) addr.getCIntegerAt(0, 4, true); ++ } ++ ++ public ProcSW64Thread(ProcDebugger debugger, long id) { ++ this.debugger = debugger; ++ this.id = (int) id; ++ } ++ ++ public ThreadContext getContext() throws IllegalThreadStateException { ++ ProcSW64ThreadContext context = new ProcSW64ThreadContext(debugger); ++ long[] regs = debugger.getThreadIntegerRegisterSet(id); ++ ++ if (Assert.ASSERTS_ENABLED) { ++ Assert.that(regs.length <= SW64ThreadContext.NPRGREG, "size of register set is greater than " + SW64ThreadContext.NPRGREG); ++ } ++ for (int i = 0; i < regs.length; i++) { ++ context.setRegister(i, regs[i]); ++ } ++ return context; ++ } ++ ++ public boolean canSetContext() throws DebuggerException { ++ return false; ++ } ++ ++ public void setContext(ThreadContext context) ++ throws IllegalThreadStateException, DebuggerException { ++ throw new DebuggerException("Unimplemented"); ++ } ++ ++ public String toString() { ++ return "t@" + id; ++ } ++ ++ public boolean equals(Object obj) { ++ if ((obj == null) || !(obj instanceof ProcSW64Thread)) { ++ return false; ++ } ++ ++ return (((ProcSW64Thread) obj).id == id); ++ } ++ ++ public int hashCode() { ++ return id; ++ } ++} +diff --git a/hotspot/agent/src/share/classes/sun/jvm/hotspot/debugger/proc/sw64/ProcSW64ThreadContext.java b/hotspot/agent/src/share/classes/sun/jvm/hotspot/debugger/proc/sw64/ProcSW64ThreadContext.java +new file mode 100755 +index 0000000000..fd2aa3d611 +--- /dev/null ++++ b/hotspot/agent/src/share/classes/sun/jvm/hotspot/debugger/proc/sw64/ProcSW64ThreadContext.java +@@ -0,0 +1,46 @@ ++/* ++ * Copyright (c) 2002, 2003, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++package sun.jvm.hotspot.debugger.proc.sw64; ++ ++import sun.jvm.hotspot.debugger.*; ++import sun.jvm.hotspot.debugger.sw64.*; ++import sun.jvm.hotspot.debugger.proc.*; ++ ++public class ProcSW64ThreadContext extends SW64ThreadContext { ++ private ProcDebugger debugger; ++ ++ public ProcSW64ThreadContext(ProcDebugger debugger) { ++ super(); ++ this.debugger = debugger; ++ } ++ ++ public void setRegisterAsAddress(int index, Address value) { ++ setRegister(index, debugger.getAddressValue(value)); ++ } ++ ++ public Address getRegisterAsAddress(int index) { ++ return debugger.newAddress(getRegister(index)); ++ } ++} +diff --git a/hotspot/agent/src/share/classes/sun/jvm/hotspot/debugger/proc/sw64/ProcSW64ThreadFactory.java b/hotspot/agent/src/share/classes/sun/jvm/hotspot/debugger/proc/sw64/ProcSW64ThreadFactory.java +new file mode 100755 +index 0000000000..9ecdb2cfd9 +--- /dev/null ++++ b/hotspot/agent/src/share/classes/sun/jvm/hotspot/debugger/proc/sw64/ProcSW64ThreadFactory.java +@@ -0,0 +1,44 @@ ++/* ++ * Copyright (c) 2002, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++package sun.jvm.hotspot.debugger.proc.sw64; ++ ++import sun.jvm.hotspot.debugger.*; ++import sun.jvm.hotspot.debugger.proc.*; ++ ++public class ProcSW64ThreadFactory implements ProcThreadFactory { ++ private ProcDebugger debugger; ++ ++ public ProcSW64ThreadFactory(ProcDebugger debugger) { ++ this.debugger = debugger; ++ } ++ ++ public ThreadProxy createThreadWrapper(Address threadIdentifierAddr) { ++ return new ProcSW64Thread(debugger, threadIdentifierAddr); ++ } ++ ++ public ThreadProxy createThreadWrapper(long id) { ++ return new ProcSW64Thread(debugger, id); ++ } ++} +diff --git a/hotspot/agent/src/share/classes/sun/jvm/hotspot/debugger/remote/RemoteDebuggerClient.java b/hotspot/agent/src/share/classes/sun/jvm/hotspot/debugger/remote/RemoteDebuggerClient.java +index ffa61b548e..fbea18117c 100644 +--- a/hotspot/agent/src/share/classes/sun/jvm/hotspot/debugger/remote/RemoteDebuggerClient.java ++++ b/hotspot/agent/src/share/classes/sun/jvm/hotspot/debugger/remote/RemoteDebuggerClient.java +@@ -31,6 +31,7 @@ import java.lang.reflect.*; + import sun.jvm.hotspot.debugger.*; + import sun.jvm.hotspot.debugger.cdbg.*; + import sun.jvm.hotspot.debugger.remote.sparc.*; ++import sun.jvm.hotspot.debugger.remote.sw64.*; + import sun.jvm.hotspot.debugger.remote.x86.*; + import sun.jvm.hotspot.debugger.remote.amd64.*; + +@@ -70,6 +71,10 @@ public class RemoteDebuggerClient extends DebuggerBase implements JVMDebugger { + cachePageSize = 4096; + cacheNumPages = parseCacheNumPagesProperty(cacheSize / cachePageSize); + unalignedAccessesOkay = true; ++ } else if (cpu.equals("sw64") || cpu.equals("sw_64")) { ++ threadFactory = new RemoteSW64ThreadFactory(this); ++ cachePageSize = 8192; ++ cacheNumPages = parseCacheNumPagesProperty(cacheSize / cachePageSize); + } else { + try { + Class tf = Class.forName("sun.jvm.hotspot.debugger.remote." + +diff --git a/hotspot/agent/src/share/classes/sun/jvm/hotspot/debugger/remote/sw64/RemoteSW64Thread.java b/hotspot/agent/src/share/classes/sun/jvm/hotspot/debugger/remote/sw64/RemoteSW64Thread.java +new file mode 100755 +index 0000000000..a0f1e6fe72 +--- /dev/null ++++ b/hotspot/agent/src/share/classes/sun/jvm/hotspot/debugger/remote/sw64/RemoteSW64Thread.java +@@ -0,0 +1,54 @@ ++/* ++ * Copyright (c) 2004, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2015, Red Hat Inc. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++package sun.jvm.hotspot.debugger.remote.sw64; ++ ++import sun.jvm.hotspot.debugger.*; ++import sun.jvm.hotspot.debugger.sw64.*; ++import sun.jvm.hotspot.debugger.remote.*; ++import sun.jvm.hotspot.utilities.*; ++ ++public class RemoteSW64Thread extends RemoteThread { ++ public RemoteSW64Thread(RemoteDebuggerClient debugger, Address addr) { ++ super(debugger, addr); ++ } ++ ++ public RemoteSW64Thread(RemoteDebuggerClient debugger, long id) { ++ super(debugger, id); ++ } ++ ++ public ThreadContext getContext() throws IllegalThreadStateException { ++ RemoteSW64ThreadContext context = new RemoteSW64ThreadContext(debugger); ++ long[] regs = (addr != null)? debugger.getThreadIntegerRegisterSet(addr) : ++ debugger.getThreadIntegerRegisterSet(id); ++ if (Assert.ASSERTS_ENABLED) { ++ Assert.that(regs.length == SW64ThreadContext.NPRGREG, "size of register set must match"); ++ } ++ for (int i = 0; i < regs.length; i++) { ++ context.setRegister(i, regs[i]); ++ } ++ return context; ++ } ++} +diff --git a/hotspot/agent/src/share/classes/sun/jvm/hotspot/debugger/remote/sw64/RemoteSW64ThreadContext.java b/hotspot/agent/src/share/classes/sun/jvm/hotspot/debugger/remote/sw64/RemoteSW64ThreadContext.java +new file mode 100755 +index 0000000000..fcaf8d2597 +--- /dev/null ++++ b/hotspot/agent/src/share/classes/sun/jvm/hotspot/debugger/remote/sw64/RemoteSW64ThreadContext.java +@@ -0,0 +1,47 @@ ++/* ++ * Copyright (c) 2004, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2015, Red Hat Inc. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++package sun.jvm.hotspot.debugger.remote.sw64; ++ ++import sun.jvm.hotspot.debugger.*; ++import sun.jvm.hotspot.debugger.sw64.*; ++import sun.jvm.hotspot.debugger.remote.*; ++ ++public class RemoteSW64ThreadContext extends SW64ThreadContext { ++ private RemoteDebuggerClient debugger; ++ ++ public RemoteSW64ThreadContext(RemoteDebuggerClient debugger) { ++ super(); ++ this.debugger = debugger; ++ } ++ ++ public void setRegisterAsAddress(int index, Address value) { ++ setRegister(index, debugger.getAddressValue(value)); ++ } ++ ++ public Address getRegisterAsAddress(int index) { ++ return debugger.newAddress(getRegister(index)); ++ } ++} +diff --git a/hotspot/agent/src/share/classes/sun/jvm/hotspot/debugger/remote/sw64/RemoteSW64ThreadFactory.java b/hotspot/agent/src/share/classes/sun/jvm/hotspot/debugger/remote/sw64/RemoteSW64ThreadFactory.java +new file mode 100755 +index 0000000000..618764c882 +--- /dev/null ++++ b/hotspot/agent/src/share/classes/sun/jvm/hotspot/debugger/remote/sw64/RemoteSW64ThreadFactory.java +@@ -0,0 +1,45 @@ ++/* ++ * Copyright (c) 2004, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2015, Red Hat Inc. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++package sun.jvm.hotspot.debugger.remote.sw64; ++ ++import sun.jvm.hotspot.debugger.*; ++import sun.jvm.hotspot.debugger.remote.*; ++ ++public class RemoteSW64ThreadFactory implements RemoteThreadFactory { ++ private RemoteDebuggerClient debugger; ++ ++ public RemoteSW64ThreadFactory(RemoteDebuggerClient debugger) { ++ this.debugger = debugger; ++ } ++ ++ public ThreadProxy createThreadWrapper(Address threadIdentifierAddr) { ++ return new RemoteSW64Thread(debugger, threadIdentifierAddr); ++ } ++ ++ public ThreadProxy createThreadWrapper(long id) { ++ return new RemoteSW64Thread(debugger, id); ++ } ++} +diff --git a/hotspot/agent/src/share/classes/sun/jvm/hotspot/debugger/sw64/SW64ThreadContext.java b/hotspot/agent/src/share/classes/sun/jvm/hotspot/debugger/sw64/SW64ThreadContext.java +new file mode 100755 +index 0000000000..51f85c02b8 +--- /dev/null ++++ b/hotspot/agent/src/share/classes/sun/jvm/hotspot/debugger/sw64/SW64ThreadContext.java +@@ -0,0 +1,124 @@ ++/* ++ * Copyright (c) 2000, 2012, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++package sun.jvm.hotspot.debugger.sw64; ++ ++import sun.jvm.hotspot.debugger.*; ++import sun.jvm.hotspot.debugger.cdbg.*; ++ ++/** Specifies the thread context on sw64 platforms; only a sub-portion ++ of the context is guaranteed to be present on all operating ++ systems. */ ++ ++public abstract class SW64ThreadContext implements ThreadContext { ++ // Taken from /usr/include/asm/reg.h on Linux/sw* ++ ++ // NOTE: the indices for the various registers must be maintained as ++ // listed across various operating systems. However, only a small ++ // subset of the registers' values are guaranteed to be present (and ++ // must be present for the SA's stack walking to work): EF_V0, ... ++ ++ // Exception frame offsets, copy from asm/reg.h ++ public static final int V0 = 0; ++ public static final int T0 = 1; ++ public static final int T1 = 2; ++ public static final int T2 = 3; ++ public static final int T3 = 4; ++ public static final int T4 = 5; ++ public static final int T5 = 6; ++ public static final int T6 = 7; ++ public static final int T7 = 8; ++ public static final int S0 = 9; ++ public static final int S1 = 10; ++ public static final int S2 = 11; ++ public static final int S3 = 12; ++ public static final int S4 = 13; ++ public static final int S5 = 14; ++ public static final int FP = 15; ++ public static final int A3 = 16; ++ public static final int A4 = 17; ++ public static final int A5 = 18; ++ public static final int T8 = 19; ++ public static final int T9 = 20; ++ public static final int T10 = 21; ++ public static final int T11 = 22; ++ public static final int RA = 23; ++ public static final int T12 = 24; ++ public static final int AT = 25; ++ public static final int SP = 26; ++ public static final int PS = 27; ++ public static final int PC = 28; ++ public static final int GP = 29; ++ public static final int A0 = 30; ++ public static final int A1 = 31; ++ public static final int A2 = 32; ++ ++ ++ public static final int NPRGREG = 33; ++ ++ private static final String[] regNames = { ++ "V0", "T0", "T1", "T2", ++ "T3", "T4", "T5", "T6", ++ "T7", "S0", "S1", "S2", ++ "S3", "S4", "S5", "FP", ++ "A3", "A4", "A5", "T8", "T9", ++ "T10", "T11", "RA", "T12", ++ "AT", "SP", "PS", "PC", ++ "GP", "A0", "A1", "A2" ++ }; ++ ++ private long[] data; ++ ++ public SW64ThreadContext() { ++ data = new long[NPRGREG]; ++ } ++ ++ public int getNumRegisters() { ++ return NPRGREG; ++ } ++ ++ public String getRegisterName(int index) { ++ return regNames[index]; ++ } ++ ++ public void setRegister(int index, long value) { ++ data[index] = value; ++ } ++ ++ public long getRegister(int index) { ++ return data[index]; ++ } ++ ++ public CFrame getTopFrame(Debugger dbg) { ++ return null; ++ } ++ ++ /** This can't be implemented in this class since we would have to ++ tie the implementation to, for example, the debugging system */ ++ public abstract void setRegisterAsAddress(int index, Address value); ++ ++ /** This can't be implemented in this class since we would have to ++ tie the implementation to, for example, the debugging system */ ++ public abstract Address getRegisterAsAddress(int index); ++} +diff --git a/hotspot/agent/src/share/classes/sun/jvm/hotspot/runtime/Threads.java b/hotspot/agent/src/share/classes/sun/jvm/hotspot/runtime/Threads.java +index 842a3b357d..d1a6f19dfa 100644 +--- a/hotspot/agent/src/share/classes/sun/jvm/hotspot/runtime/Threads.java ++++ b/hotspot/agent/src/share/classes/sun/jvm/hotspot/runtime/Threads.java +@@ -35,6 +35,7 @@ import sun.jvm.hotspot.runtime.win32_x86.Win32X86JavaThreadPDAccess; + import sun.jvm.hotspot.runtime.linux_x86.LinuxX86JavaThreadPDAccess; + import sun.jvm.hotspot.runtime.linux_amd64.LinuxAMD64JavaThreadPDAccess; + import sun.jvm.hotspot.runtime.linux_sparc.LinuxSPARCJavaThreadPDAccess; ++import sun.jvm.hotspot.runtime.linux_sw64.LinuxSW64JavaThreadPDAccess; + import sun.jvm.hotspot.runtime.linux_aarch64.LinuxAARCH64JavaThreadPDAccess; + import sun.jvm.hotspot.runtime.bsd_x86.BsdX86JavaThreadPDAccess; + import sun.jvm.hotspot.runtime.bsd_amd64.BsdAMD64JavaThreadPDAccess; +@@ -88,6 +89,8 @@ public class Threads { + access = new LinuxAMD64JavaThreadPDAccess(); + } else if (cpu.equals("sparc")) { + access = new LinuxSPARCJavaThreadPDAccess(); ++ } else if (cpu.equals("sw64")) { ++ access = new LinuxSW64JavaThreadPDAccess(); + } else if (cpu.equals("aarch64")) { + access = new LinuxAARCH64JavaThreadPDAccess(); + } else { +diff --git a/hotspot/agent/src/share/classes/sun/jvm/hotspot/runtime/VM.java b/hotspot/agent/src/share/classes/sun/jvm/hotspot/runtime/VM.java +index 29bf9efea7..9608883567 100644 +--- a/hotspot/agent/src/share/classes/sun/jvm/hotspot/runtime/VM.java ++++ b/hotspot/agent/src/share/classes/sun/jvm/hotspot/runtime/VM.java +@@ -206,37 +206,39 @@ public class VM { + }; + + private static void checkVMVersion(String vmRelease) { +- if (System.getProperty("sun.jvm.hotspot.runtime.VM.disableVersionCheck") == null) { +- // read sa build version. +- String versionProp = "sun.jvm.hotspot.runtime.VM.saBuildVersion"; +- String saVersion = saProps.getProperty(versionProp); +- if (saVersion == null) +- throw new RuntimeException("Missing property " + versionProp); +- +- // Strip nonproduct VM version substring (note: saVersion doesn't have it). +- String vmVersion = vmRelease.replaceAll("(-fastdebug)|(-debug)|(-jvmg)|(-optimized)|(-profiled)",""); +- +- if (saVersion.equals(vmVersion)) { +- // Exact match +- return; +- } +- if (saVersion.indexOf('-') == saVersion.lastIndexOf('-') && +- vmVersion.indexOf('-') == vmVersion.lastIndexOf('-')) { +- // Throw exception if different release versions: +- // .-b +- throw new VMVersionMismatchException(saVersion, vmRelease); +- } else { +- // Otherwise print warning to allow mismatch not release versions +- // during development. +- System.err.println("WARNING: Hotspot VM version " + vmRelease + +- " does not match with SA version " + saVersion + +- "." + " You may see unexpected results. "); +- } +- } else { +- System.err.println("WARNING: You have disabled SA and VM version check. You may be " + +- "using incompatible version of SA and you may see unexpected " + +- "results."); +- } ++//ZHJ20191021 Disable checkVMVersion for all kinds of java tools in agent ++//ZHJ20191021 if (System.getProperty("sun.jvm.hotspot.runtime.VM.disableVersionCheck") == null) { ++//ZHJ20191021 // read sa build version. ++//ZHJ20191021 String versionProp = "sun.jvm.hotspot.runtime.VM.saBuildVersion"; ++//ZHJ20191021 String saVersion = saProps.getProperty(versionProp); ++//ZHJ20191021 if (saVersion == null) ++//ZHJ20191021 throw new RuntimeException("Missing property " + versionProp); ++//ZHJ20191021 ++//ZHJ20191021 // Strip nonproduct VM version substring (note: saVersion doesn't have it). ++//ZHJ20191021 String vmVersion = vmRelease.replaceAll("(-fastdebug)|(-debug)|(-jvmg)|(-optimized)|(-profiled)",""); ++//ZHJ20191021 ++//ZHJ20191021 if (saVersion.equals(vmVersion)) { ++//ZHJ20191021 // Exact match ++//ZHJ20191021 return; ++//ZHJ20191021 } ++//ZHJ20191021 if (saVersion.indexOf('-') == saVersion.lastIndexOf('-') && ++//ZHJ20191021 vmVersion.indexOf('-') == vmVersion.lastIndexOf('-')) { ++//ZHJ20191021 // Throw exception if different release versions: ++//ZHJ20191021 // .-b ++//ZHJ20191021 throw new VMVersionMismatchException(saVersion, vmRelease); ++//ZHJ20191021 } else { ++//ZHJ20191021 // Otherwise print warning to allow mismatch not release versions ++//ZHJ20191021 // during development. ++//ZHJ20191021 System.err.println("WARNING: Hotspot VM version " + vmRelease + ++//ZHJ20191021 " does not match with SA version " + saVersion + ++//ZHJ20191021 "." + " You may see unexpected results. "); ++//ZHJ20191021 } ++//ZHJ20191021 } else { ++//ZHJ20191021 System.err.println("WARNING: You have disabled SA and VM version check. You may be " + ++//ZHJ20191021 "using incompatible version of SA and you may see unexpected " + ++//ZHJ20191021 "results."); ++//ZHJ20191021 } ++// throw new RuntimeException("Missing property "); + } + + private static final boolean disableDerivedPointerTableCheck; +diff --git a/hotspot/agent/src/share/classes/sun/jvm/hotspot/runtime/linux_sw64/LinuxSW64JavaThreadPDAccess.java b/hotspot/agent/src/share/classes/sun/jvm/hotspot/runtime/linux_sw64/LinuxSW64JavaThreadPDAccess.java +new file mode 100755 +index 0000000000..31dba70845 +--- /dev/null ++++ b/hotspot/agent/src/share/classes/sun/jvm/hotspot/runtime/linux_sw64/LinuxSW64JavaThreadPDAccess.java +@@ -0,0 +1,132 @@ ++/* ++ * Copyright (c) 2003, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2015, Red Hat Inc. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++package sun.jvm.hotspot.runtime.linux_sw64; ++ ++import java.io.*; ++import java.util.*; ++import sun.jvm.hotspot.debugger.*; ++import sun.jvm.hotspot.debugger.sw64.*; ++import sun.jvm.hotspot.runtime.*; ++import sun.jvm.hotspot.runtime.sw64.*; ++import sun.jvm.hotspot.types.*; ++import sun.jvm.hotspot.utilities.*; ++ ++public class LinuxSW64JavaThreadPDAccess implements JavaThreadPDAccess { ++ private static AddressField lastJavaFPField; ++ private static AddressField osThreadField; ++ ++ // Field from OSThread ++ private static CIntegerField osThreadThreadIDField; ++ ++ // This is currently unneeded but is being kept in case we change ++ // the currentFrameGuess algorithm ++ private static final long GUESS_SCAN_RANGE = 128 * 1024; ++ ++ static { ++ VM.registerVMInitializedObserver(new Observer() { ++ public void update(Observable o, Object data) { ++ initialize(VM.getVM().getTypeDataBase()); ++ } ++ }); ++ } ++ ++ private static synchronized void initialize(TypeDataBase db) { ++ Type type = db.lookupType("JavaThread"); ++ osThreadField = type.getAddressField("_osthread"); ++ ++ Type anchorType = db.lookupType("JavaFrameAnchor"); ++ lastJavaFPField = anchorType.getAddressField("_last_Java_fp"); ++ ++ Type osThreadType = db.lookupType("OSThread"); ++ osThreadThreadIDField = osThreadType.getCIntegerField("_thread_id"); ++ } ++ ++ public Address getLastJavaFP(Address addr) { ++ return lastJavaFPField.getValue(addr.addOffsetTo(sun.jvm.hotspot.runtime.JavaThread.getAnchorField().getOffset())); ++ } ++ ++ public Address getLastJavaPC(Address addr) { ++ return null; ++ } ++ ++ public Address getBaseOfStackPointer(Address addr) { ++ return null; ++ } ++ ++ public Frame getLastFramePD(JavaThread thread, Address addr) { ++ Address fp = thread.getLastJavaFP(); ++ if (fp == null) { ++ return null; // no information ++ } ++ return new SW64Frame(thread.getLastJavaSP(), fp); ++ } ++ ++ public RegisterMap newRegisterMap(JavaThread thread, boolean updateMap) { ++ return new SW64RegisterMap(thread, updateMap); ++ } ++ ++ public Frame getCurrentFrameGuess(JavaThread thread, Address addr) { ++ ThreadProxy t = getThreadProxy(addr); ++ SW64ThreadContext context = (SW64ThreadContext) t.getContext(); ++ SW64CurrentFrameGuess guesser = new SW64CurrentFrameGuess(context, thread); ++ if (!guesser.run(GUESS_SCAN_RANGE)) { ++ return null; ++ } ++ if (guesser.getPC() == null) { ++ return new SW64Frame(guesser.getSP(), guesser.getFP()); ++ } else { ++ return new SW64Frame(guesser.getSP(), guesser.getFP(), guesser.getPC()); ++ } ++ } ++ ++ public void printThreadIDOn(Address addr, PrintStream tty) { ++ tty.print(getThreadProxy(addr)); ++ } ++ ++ public void printInfoOn(Address threadAddr, PrintStream tty) { ++ tty.print("Thread id: "); ++ printThreadIDOn(threadAddr, tty); ++// tty.println("\nPostJavaState: " + getPostJavaState(threadAddr)); ++ } ++ ++ public Address getLastSP(Address addr) { ++ ThreadProxy t = getThreadProxy(addr); ++ SW64ThreadContext context = (SW64ThreadContext) t.getContext(); ++ return context.getRegisterAsAddress(SW64ThreadContext.SP); ++ } ++ ++ public ThreadProxy getThreadProxy(Address addr) { ++ // Addr is the address of the JavaThread. ++ // Fetch the OSThread (for now and for simplicity, not making a ++ // separate "OSThread" class in this package) ++ Address osThreadAddr = osThreadField.getValue(addr); ++ // Get the address of the _thread_id from the OSThread ++ Address threadIdAddr = osThreadAddr.addOffsetTo(osThreadThreadIDField.getOffset()); ++ ++ JVMDebugger debugger = VM.getVM().getDebugger(); ++ return debugger.getThreadForIdentifierAddress(threadIdAddr); ++ } ++} +diff --git a/hotspot/agent/src/share/classes/sun/jvm/hotspot/runtime/sw64/SW64CurrentFrameGuess.java b/hotspot/agent/src/share/classes/sun/jvm/hotspot/runtime/sw64/SW64CurrentFrameGuess.java +new file mode 100755 +index 0000000000..80a3b6bf5c +--- /dev/null ++++ b/hotspot/agent/src/share/classes/sun/jvm/hotspot/runtime/sw64/SW64CurrentFrameGuess.java +@@ -0,0 +1,244 @@ ++/* ++ * Copyright (c) 2003, 2006, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2015, Red Hat Inc. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++package sun.jvm.hotspot.runtime.sw64; ++ ++import sun.jvm.hotspot.debugger.*; ++import sun.jvm.hotspot.debugger.sw64.*; ++import sun.jvm.hotspot.code.*; ++import sun.jvm.hotspot.interpreter.*; ++import sun.jvm.hotspot.runtime.*; ++import sun.jvm.hotspot.runtime.sw64.*; ++ ++/**

Should be able to be used on all sw64 platforms we support ++ (Linux/sw64) to implement JavaThread's "currentFrameGuess()" ++ functionality. Input is an SW64ThreadContext; output is SP, FP, ++ and PC for an SW64Frame. Instantiation of the SW64Frame is ++ left to the caller, since we may need to subclass SW64Frame to ++ support signal handler frames on Unix platforms.

++ ++

Algorithm is to walk up the stack within a given range (say, ++ 512K at most) looking for a plausible PC and SP for a Java frame, ++ also considering those coming in from the context. If we find a PC ++ that belongs to the VM (i.e., in generated code like the ++ interpreter or CodeCache) then we try to find an associated FP. ++ We repeat this until we either find a complete frame or run out of ++ stack to look at.

*/ ++ ++public class SW64CurrentFrameGuess { ++ private SW64ThreadContext context; ++ private JavaThread thread; ++ private Address spFound; ++ private Address fpFound; ++ private Address pcFound; ++ ++ private static final boolean DEBUG = System.getProperty("sun.jvm.hotspot.runtime.sw64.SW64Frame.DEBUG") ++ != null; ++ ++ public SW64CurrentFrameGuess(SW64ThreadContext context, ++ JavaThread thread) { ++ this.context = context; ++ this.thread = thread; ++ } ++ ++ /** Returns false if not able to find a frame within a reasonable range. */ ++ public boolean run(long regionInBytesToSearch) { ++ Address sp = context.getRegisterAsAddress(SW64ThreadContext.SP); ++ Address pc = context.getRegisterAsAddress(SW64ThreadContext.PC); ++ Address fp = context.getRegisterAsAddress(SW64ThreadContext.FP); ++ if (sp == null) { ++ // Bail out if no last java frame either ++ if (thread.getLastJavaSP() != null) { ++ setValues(thread.getLastJavaSP(), thread.getLastJavaFP(), null); ++ return true; ++ } ++ return false; ++ } ++ Address end = sp.addOffsetTo(regionInBytesToSearch); ++ VM vm = VM.getVM(); ++ ++ setValues(null, null, null); // Assume we're not going to find anything ++ ++ if (vm.isJavaPCDbg(pc)) { ++ if (vm.isClientCompiler()) { ++ // If the topmost frame is a Java frame, we are (pretty much) ++ // guaranteed to have a viable FP. We should be more robust ++ // than this (we have the potential for losing entire threads' ++ // stack traces) but need to see how much work we really have ++ // to do here. Searching the stack for an (SP, FP) pair is ++ // hard since it's easy to misinterpret inter-frame stack ++ // pointers as base-of-frame pointers; we also don't know the ++ // sizes of C1 frames (not registered in the nmethod) so can't ++ // derive them from SP. ++ ++ setValues(sp, fp, pc); ++ return true; ++ } else { ++ if (vm.getInterpreter().contains(pc)) { ++ if (DEBUG) { ++ System.out.println("CurrentFrameGuess: choosing interpreter frame: sp = " + ++ sp + ", fp = " + fp + ", pc = " + pc); ++ } ++ setValues(sp, fp, pc); ++ return true; ++ } ++ ++ // For the server compiler, FP is not guaranteed to be valid ++ // for compiled code. In addition, an earlier attempt at a ++ // non-searching algorithm (see below) failed because the ++ // stack pointer from the thread context was pointing ++ // (considerably) beyond the ostensible end of the stack, into ++ // garbage; walking from the topmost frame back caused a crash. ++ // ++ // This algorithm takes the current PC as a given and tries to ++ // find the correct corresponding SP by walking up the stack ++ // and repeatedly performing stackwalks (very inefficient). ++ // ++ // FIXME: there is something wrong with stackwalking across ++ // adapter frames...this is likely to be the root cause of the ++ // failure with the simpler algorithm below. ++ ++ for (long offset = 0; ++ offset < regionInBytesToSearch; ++ offset += vm.getAddressSize()) { ++ try { ++ Address curSP = sp.addOffsetTo(offset); ++ Frame frame = new SW64Frame(curSP, null, pc); ++ RegisterMap map = thread.newRegisterMap(false); ++ while (frame != null) { ++ if (frame.isEntryFrame() && frame.entryFrameIsFirst()) { ++ // We were able to traverse all the way to the ++ // bottommost Java frame. ++ // This sp looks good. Keep it. ++ if (DEBUG) { ++ System.out.println("CurrentFrameGuess: Choosing sp = " + curSP + ", pc = " + pc); ++ } ++ setValues(curSP, null, pc); ++ return true; ++ } ++ frame = frame.sender(map); ++ } ++ } catch (Exception e) { ++ if (DEBUG) { ++ System.out.println("CurrentFrameGuess: Exception " + e + " at offset " + offset); ++ } ++ // Bad SP. Try another. ++ } ++ } ++ ++ // Were not able to find a plausible SP to go with this PC. ++ // Bail out. ++ return false; ++ ++ /* ++ // Original algorithm which does not work because SP was ++ // pointing beyond where it should have: ++ ++ // For the server compiler, FP is not guaranteed to be valid ++ // for compiled code. We see whether the PC is in the ++ // interpreter and take care of that, otherwise we run code ++ // (unfortunately) duplicated from SW64Frame.senderForCompiledFrame. ++ ++ CodeCache cc = vm.getCodeCache(); ++ if (cc.contains(pc)) { ++ CodeBlob cb = cc.findBlob(pc); ++ ++ // See if we can derive a frame pointer from SP and PC ++ // NOTE: This is the code duplicated from SW64Frame ++ Address saved_fp = null; ++ int llink_offset = cb.getLinkOffset(); ++ if (llink_offset >= 0) { ++ // Restore base-pointer, since next frame might be an interpreter frame. ++ Address fp_addr = sp.addOffsetTo(VM.getVM().getAddressSize() * llink_offset); ++ saved_fp = fp_addr.getAddressAt(0); ++ } ++ ++ setValues(sp, saved_fp, pc); ++ return true; ++ } ++ */ ++ } ++ } else { ++ // If the current program counter was not known to us as a Java ++ // PC, we currently assume that we are in the run-time system ++ // and attempt to look to thread-local storage for saved SP and ++ // FP. Note that if these are null (because we were, in fact, ++ // in Java code, i.e., vtable stubs or similar, and the SA ++ // didn't have enough insight into the target VM to understand ++ // that) then we are going to lose the entire stack trace for ++ // the thread, which is sub-optimal. FIXME. ++ ++ if (DEBUG) { ++ System.out.println("CurrentFrameGuess: choosing last Java frame: sp = " + ++ thread.getLastJavaSP() + ", fp = " + thread.getLastJavaFP()); ++ } ++ if (thread.getLastJavaSP() == null) { ++ return false; // No known Java frames on stack ++ } ++ ++ // The runtime has a nasty habit of not saving fp in the frame ++ // anchor, leaving us to grovel about in the stack to find a ++ // plausible address. Fortunately, this only happens in ++ // compiled code; there we always have a valid PC, and we always ++ // push LR and FP onto the stack as a pair, with FP at the lower ++ // address. ++ pc = thread.getLastJavaPC(); ++ fp = thread.getLastJavaFP(); ++ sp = thread.getLastJavaSP(); ++ ++ if (fp == null) { ++ CodeCache cc = vm.getCodeCache(); ++ if (cc.contains(pc)) { ++ CodeBlob cb = cc.findBlob(pc); ++ if (DEBUG) { ++ System.out.println("FP is null. Found blob frame size " + cb.getFrameSize()); ++ } ++ // See if we can derive a frame pointer from SP and PC ++ long link_offset = cb.getFrameSize() - 2 * VM.getVM().getAddressSize(); ++ if (link_offset >= 0) { ++ fp = sp.addOffsetTo(link_offset); ++ } ++ } ++ } ++ ++ setValues(sp, fp, null); ++ ++ return true; ++ } ++ } ++ ++ public Address getSP() { return spFound; } ++ public Address getFP() { return fpFound; } ++ /** May be null if getting values from thread-local storage; take ++ care to call the correct SW64Frame constructor to recover this if ++ necessary */ ++ public Address getPC() { return pcFound; } ++ ++ private void setValues(Address sp, Address fp, Address pc) { ++ spFound = sp; ++ fpFound = fp; ++ pcFound = pc; ++ } ++} +diff --git a/hotspot/agent/src/share/classes/sun/jvm/hotspot/runtime/sw64/SW64Frame.java b/hotspot/agent/src/share/classes/sun/jvm/hotspot/runtime/sw64/SW64Frame.java +new file mode 100755 +index 0000000000..a5ab731590 +--- /dev/null ++++ b/hotspot/agent/src/share/classes/sun/jvm/hotspot/runtime/sw64/SW64Frame.java +@@ -0,0 +1,557 @@ ++/* ++ * Copyright (c) 2001, 2012, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2015, Red Hat Inc. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++package sun.jvm.hotspot.runtime.sw64; ++ ++import java.util.*; ++import sun.jvm.hotspot.code.*; ++import sun.jvm.hotspot.compiler.*; ++import sun.jvm.hotspot.debugger.*; ++import sun.jvm.hotspot.oops.*; ++import sun.jvm.hotspot.runtime.*; ++import sun.jvm.hotspot.types.*; ++import sun.jvm.hotspot.utilities.*; ++ ++/** Specialization of and implementation of abstract methods of the ++ Frame class for the sw64 family of CPUs. */ ++ ++public class SW64Frame extends Frame { ++ private static final boolean DEBUG; ++ static { ++ DEBUG = System.getProperty("sun.jvm.hotspot.runtime.sw64.SW64Frame.DEBUG") != null; ++ } ++ ++ // All frames ++ private static final int LINK_OFFSET = 0; ++ private static final int RETURN_ADDR_OFFSET = 1; ++ private static final int SENDER_SP_OFFSET = 2; ++ ++ // Interpreter frames ++ private static final int INTERPRETER_FRAME_MIRROR_OFFSET = 2; // for native calls only ++ private static final int INTERPRETER_FRAME_SENDER_SP_OFFSET = -1; ++ private static final int INTERPRETER_FRAME_LAST_SP_OFFSET = INTERPRETER_FRAME_SENDER_SP_OFFSET - 1; ++ private static final int INTERPRETER_FRAME_LOCALS_OFFSET = INTERPRETER_FRAME_LAST_SP_OFFSET - 1; ++ private static int INTERPRETER_FRAME_METHOD_OFFSET; ++ private static int INTERPRETER_FRAME_MDX_OFFSET; // Non-core builds only ++ private static int INTERPRETER_FRAME_CACHE_OFFSET; ++//ZHJ private static int INTERPRETER_FRAME_LOCALS_OFFSET; ++ private static int INTERPRETER_FRAME_BCX_OFFSET; ++ private static int INTERPRETER_FRAME_INITIAL_SP_OFFSET; ++ private static int INTERPRETER_FRAME_MONITOR_BLOCK_TOP_OFFSET; ++ private static int INTERPRETER_FRAME_MONITOR_BLOCK_BOTTOM_OFFSET; ++ ++ // Entry frames ++ private static int ENTRY_FRAME_CALL_WRAPPER_OFFSET = -9; ++ ++ // Native frames ++ private static final int NATIVE_FRAME_INITIAL_PARAM_OFFSET = 2; ++ ++ private static VMReg fp = new VMReg(15); ++ ++ static { ++ VM.registerVMInitializedObserver(new Observer() { ++ public void update(Observable o, Object data) { ++ initialize(VM.getVM().getTypeDataBase()); ++ } ++ }); ++ } ++ ++ private static synchronized void initialize(TypeDataBase db) { ++ INTERPRETER_FRAME_METHOD_OFFSET = INTERPRETER_FRAME_LOCALS_OFFSET - 1; ++ INTERPRETER_FRAME_MDX_OFFSET = INTERPRETER_FRAME_METHOD_OFFSET - 1; ++ INTERPRETER_FRAME_CACHE_OFFSET = INTERPRETER_FRAME_MDX_OFFSET - 1; ++//ZHJ INTERPRETER_FRAME_LOCALS_OFFSET = INTERPRETER_FRAME_CACHE_OFFSET - 1; ++ INTERPRETER_FRAME_BCX_OFFSET = INTERPRETER_FRAME_CACHE_OFFSET - 1; ++ INTERPRETER_FRAME_INITIAL_SP_OFFSET = INTERPRETER_FRAME_BCX_OFFSET - 1; ++ INTERPRETER_FRAME_MONITOR_BLOCK_TOP_OFFSET = INTERPRETER_FRAME_INITIAL_SP_OFFSET; ++ INTERPRETER_FRAME_MONITOR_BLOCK_BOTTOM_OFFSET = INTERPRETER_FRAME_INITIAL_SP_OFFSET; ++ } ++ ++ ++ // an additional field beyond sp and pc: ++ Address raw_fp; // frame pointer ++ private Address raw_unextendedSP; ++ ++ private SW64Frame() { ++ } ++ ++ private void adjustForDeopt() { ++ if ( pc != null) { ++ // Look for a deopt pc and if it is deopted convert to original pc ++ CodeBlob cb = VM.getVM().getCodeCache().findBlob(pc); ++ if (cb != null && cb.isJavaMethod()) { ++ NMethod nm = (NMethod) cb; ++ if (pc.equals(nm.deoptHandlerBegin())) { ++ if (Assert.ASSERTS_ENABLED) { ++ Assert.that(this.getUnextendedSP() != null, "null SP in Java frame"); ++ } ++ // adjust pc if frame is deoptimized. ++ pc = this.getUnextendedSP().getAddressAt(nm.origPCOffset()); ++ deoptimized = true; ++ } ++ } ++ } ++ } ++ ++ public SW64Frame(Address raw_sp, Address raw_fp, Address pc) { ++ this.raw_sp = raw_sp; ++ this.raw_unextendedSP = raw_sp; ++ this.raw_fp = raw_fp; ++ this.pc = pc; ++ adjustUnextendedSP(); ++ ++ // Frame must be fully constructed before this call ++ adjustForDeopt(); ++ ++ if (DEBUG) { ++ System.out.println("SW64Frame(sp, fp, pc): " + this); ++ dumpStack(); ++ } ++ } ++ ++ public SW64Frame(Address raw_sp, Address raw_fp) { ++ this.raw_sp = raw_sp; ++ this.raw_unextendedSP = raw_sp; ++ this.raw_fp = raw_fp; ++ this.pc = raw_sp.getAddressAt(-1 * VM.getVM().getAddressSize()); ++ adjustUnextendedSP(); ++ ++ // Frame must be fully constructed before this call ++ adjustForDeopt(); ++ ++ if (DEBUG) { ++ System.out.println("SW64Frame(sp, fp): " + this); ++ dumpStack(); ++ } ++ } ++ ++ public SW64Frame(Address raw_sp, Address raw_unextendedSp, Address raw_fp, Address pc) { ++ this.raw_sp = raw_sp; ++ this.raw_unextendedSP = raw_unextendedSp; ++ this.raw_fp = raw_fp; ++ this.pc = pc; ++ adjustUnextendedSP(); ++ ++ // Frame must be fully constructed before this call ++ adjustForDeopt(); ++ ++ if (DEBUG) { ++ System.out.println("SW64Frame(sp, unextendedSP, fp, pc): " + this); ++ dumpStack(); ++ } ++ ++ } ++ ++ public Object clone() { ++ SW64Frame frame = new SW64Frame(); ++ frame.raw_sp = raw_sp; ++ frame.raw_unextendedSP = raw_unextendedSP; ++ frame.raw_fp = raw_fp; ++ frame.pc = pc; ++ frame.deoptimized = deoptimized; ++ return frame; ++ } ++ ++ public boolean equals(Object arg) { ++ if (arg == null) { ++ return false; ++ } ++ ++ if (!(arg instanceof SW64Frame)) { ++ return false; ++ } ++ ++ SW64Frame other = (SW64Frame) arg; ++ ++ return (AddressOps.equal(getSP(), other.getSP()) && ++ AddressOps.equal(getUnextendedSP(), other.getUnextendedSP()) && ++ AddressOps.equal(getFP(), other.getFP()) && ++ AddressOps.equal(getPC(), other.getPC())); ++ } ++ ++ public int hashCode() { ++ if (raw_sp == null) { ++ return 0; ++ } ++ ++ return raw_sp.hashCode(); ++ } ++ ++ public String toString() { ++ return "sp: " + (getSP() == null? "null" : getSP().toString()) + ++ ", unextendedSP: " + (getUnextendedSP() == null? "null" : getUnextendedSP().toString()) + ++ ", fp: " + (getFP() == null? "null" : getFP().toString()) + ++ ", pc: " + (pc == null? "null" : pc.toString()); ++ } ++ ++ // accessors for the instance variables ++ public Address getFP() { return raw_fp; } ++ public Address getSP() { return raw_sp; } ++ public Address getID() { return raw_sp; } ++ ++ // FIXME: not implemented yet ++ public boolean isSignalHandlerFrameDbg() { return false; } ++ public int getSignalNumberDbg() { return 0; } ++ public String getSignalNameDbg() { return null; } ++ ++ public boolean isInterpretedFrameValid() { ++ if (Assert.ASSERTS_ENABLED) { ++ Assert.that(isInterpretedFrame(), "Not an interpreted frame"); ++ } ++ ++ // These are reasonable sanity checks ++ if (getFP() == null || getFP().andWithMask(0x3) != null) { ++ return false; ++ } ++ ++ if (getSP() == null || getSP().andWithMask(0x3) != null) { ++ return false; ++ } ++ ++ if (getFP().addOffsetTo(INTERPRETER_FRAME_INITIAL_SP_OFFSET * VM.getVM().getAddressSize()).lessThan(getSP())) { ++ return false; ++ } ++ ++ // These are hacks to keep us out of trouble. ++ // The problem with these is that they mask other problems ++ if (getFP().lessThanOrEqual(getSP())) { ++ // this attempts to deal with unsigned comparison above ++ return false; ++ } ++ ++ if (getFP().minus(getSP()) > 8192 * VM.getVM().getAddressSize()) { ++ // stack frames shouldn't be large. ++ return false; ++ } ++ ++ return true; ++ } ++ ++ // FIXME: not applicable in current system ++ // void patch_pc(Thread* thread, address pc); ++ ++ public Frame sender(RegisterMap regMap, CodeBlob cb) { ++ SW64RegisterMap map = (SW64RegisterMap) regMap; ++ ++ if (Assert.ASSERTS_ENABLED) { ++ Assert.that(map != null, "map must be set"); ++ } ++ ++ // Default is we done have to follow them. The sender_for_xxx will ++ // update it accordingly ++ map.setIncludeArgumentOops(false); ++ ++ if (isEntryFrame()) return senderForEntryFrame(map); ++ if (isInterpretedFrame()) return senderForInterpreterFrame(map); ++ ++ if(cb == null) { ++ cb = VM.getVM().getCodeCache().findBlob(getPC()); ++ } else { ++ if (Assert.ASSERTS_ENABLED) { ++ Assert.that(cb.equals(VM.getVM().getCodeCache().findBlob(getPC())), "Must be the same"); ++ } ++ } ++ ++ if (cb != null) { ++ return senderForCompiledFrame(map, cb); ++ } ++ ++ // Must be native-compiled frame, i.e. the marshaling code for native ++ // methods that exists in the core system. ++ return new SW64Frame(getSenderSP(), getLink(), getSenderPC()); ++ } ++ ++ private Frame senderForEntryFrame(SW64RegisterMap map) { ++ if (DEBUG) { ++ System.out.println("senderForEntryFrame"); ++ } ++ if (Assert.ASSERTS_ENABLED) { ++ Assert.that(map != null, "map must be set"); ++ } ++ // Java frame called from C; skip all C frames and return top C ++ // frame of that chunk as the sender ++ SW64JavaCallWrapper jcw = (SW64JavaCallWrapper) getEntryFrameCallWrapper(); ++ if (Assert.ASSERTS_ENABLED) { ++ Assert.that(!entryFrameIsFirst(), "next Java fp must be non zero"); ++ Assert.that(jcw.getLastJavaSP().greaterThan(getSP()), "must be above this frame on stack"); ++ } ++ SW64Frame fr; ++ if (jcw.getLastJavaPC() != null) { ++ fr = new SW64Frame(jcw.getLastJavaSP(), jcw.getLastJavaFP(), jcw.getLastJavaPC()); ++ } else { ++ fr = new SW64Frame(jcw.getLastJavaSP(), jcw.getLastJavaFP()); ++ } ++ map.clear(); ++ if (Assert.ASSERTS_ENABLED) { ++ Assert.that(map.getIncludeArgumentOops(), "should be set by clear"); ++ } ++ return fr; ++ } ++ ++ //------------------------------------------------------------------------------ ++ // frame::adjust_unextended_sp ++ private void adjustUnextendedSP() { ++ // If we are returning to a compiled MethodHandle call site, the ++ // saved_fp will in fact be a saved value of the unextended SP. The ++ // simplest way to tell whether we are returning to such a call site ++ // is as follows: ++ ++ CodeBlob cb = cb(); ++ NMethod senderNm = (cb == null) ? null : cb.asNMethodOrNull(); ++ if (senderNm != null) { ++ // If the sender PC is a deoptimization point, get the original ++ // PC. For MethodHandle call site the unextended_sp is stored in ++ // saved_fp. ++ if (senderNm.isDeoptMhEntry(getPC())) { ++ // DEBUG_ONLY(verifyDeoptMhOriginalPc(senderNm, getFP())); ++ raw_unextendedSP = getFP(); ++ } ++ else if (senderNm.isDeoptEntry(getPC())) { ++ // DEBUG_ONLY(verifyDeoptOriginalPc(senderNm, raw_unextendedSp)); ++ } ++ else if (senderNm.isMethodHandleReturn(getPC())) { ++ raw_unextendedSP = getFP(); ++ } ++ } ++ } ++ ++ private Frame senderForInterpreterFrame(SW64RegisterMap map) { ++ if (DEBUG) { ++ System.out.println("senderForInterpreterFrame"); ++ } ++ Address unextendedSP = addressOfStackSlot(INTERPRETER_FRAME_SENDER_SP_OFFSET).getAddressAt(0); ++ Address sp = addressOfStackSlot(SENDER_SP_OFFSET); ++ // We do not need to update the callee-save register mapping because above ++ // us is either another interpreter frame or a converter-frame, but never ++ // directly a compiled frame. ++ // 11/24/04 SFG. With the removal of adapter frames this is no longer true. ++ // However c2 no longer uses callee save register for java calls so there ++ // are no callee register to find. ++ ++ if (map.getUpdateMap()) ++ updateMapWithSavedLink(map, addressOfStackSlot(LINK_OFFSET)); ++ ++ return new SW64Frame(sp, unextendedSP, getLink(), getSenderPC()); ++ } ++ ++ private void updateMapWithSavedLink(RegisterMap map, Address savedFPAddr) { ++ map.setLocation(fp, savedFPAddr); ++ } ++ ++ private Frame senderForCompiledFrame(SW64RegisterMap map, CodeBlob cb) { ++ if (DEBUG) { ++ System.out.println("senderForCompiledFrame"); ++ } ++ ++ // ++ // NOTE: some of this code is (unfortunately) duplicated SW64CurrentFrameGuess ++ // ++ ++ if (Assert.ASSERTS_ENABLED) { ++ Assert.that(map != null, "map must be set"); ++ } ++ ++ // frame owned by optimizing compiler ++ if (Assert.ASSERTS_ENABLED) { ++ Assert.that(cb.getFrameSize() >= 0, "must have non-zero frame size"); ++ } ++ Address senderSP = getUnextendedSP().addOffsetTo(cb.getFrameSize()); ++ ++ // The return_address is always the word on the stack ++ Address senderPC = senderSP.getAddressAt(-1 * VM.getVM().getAddressSize()); ++ ++ // This is the saved value of FP which may or may not really be an FP. ++ // It is only an FP if the sender is an interpreter frame. ++ Address savedFPAddr = senderSP.addOffsetTo(- SENDER_SP_OFFSET * VM.getVM().getAddressSize()); ++ ++ if (map.getUpdateMap()) { ++ // Tell GC to use argument oopmaps for some runtime stubs that need it. ++ // For C1, the runtime stub might not have oop maps, so set this flag ++ // outside of update_register_map. ++ map.setIncludeArgumentOops(cb.callerMustGCArguments()); ++ ++ if (cb.getOopMaps() != null) { ++ OopMapSet.updateRegisterMap(this, cb, map, true); ++ } ++ ++ // Since the prolog does the save and restore of FP there is no oopmap ++ // for it so we must fill in its location as if there was an oopmap entry ++ // since if our caller was compiled code there could be live jvm state in it. ++ updateMapWithSavedLink(map, savedFPAddr); ++ } ++ ++ return new SW64Frame(senderSP, savedFPAddr.getAddressAt(0), senderPC); ++ } ++ ++ protected boolean hasSenderPD() { ++ return true; ++ } ++ ++ public long frameSize() { ++ return (getSenderSP().minus(getSP()) / VM.getVM().getAddressSize()); ++ } ++ ++ public Address getLink() { ++ try { ++ if (DEBUG) { ++ System.out.println("Reading link at " + addressOfStackSlot(LINK_OFFSET) ++ + " = " + addressOfStackSlot(LINK_OFFSET).getAddressAt(0)); ++ } ++ return addressOfStackSlot(LINK_OFFSET).getAddressAt(0); ++ } catch (Exception e) { ++ if (DEBUG) ++ System.out.println("Returning null"); ++ return null; ++ } ++ } ++ ++ // FIXME: not implementable yet ++ //inline void frame::set_link(intptr_t* addr) { *(intptr_t **)addr_at(link_offset) = addr; } ++ ++ public Address getUnextendedSP() { return raw_unextendedSP; } ++ ++ // Return address: ++ public Address getSenderPCAddr() { return addressOfStackSlot(RETURN_ADDR_OFFSET); } ++ public Address getSenderPC() { return getSenderPCAddr().getAddressAt(0); } ++ ++ // return address of param, zero origin index. ++ public Address getNativeParamAddr(int idx) { ++ return addressOfStackSlot(NATIVE_FRAME_INITIAL_PARAM_OFFSET + idx); ++ } ++ ++ public Address getSenderSP() { return addressOfStackSlot(SENDER_SP_OFFSET); } ++ ++ public Address addressOfInterpreterFrameLocals() { ++ return addressOfStackSlot(INTERPRETER_FRAME_LOCALS_OFFSET); ++ } ++ ++ private Address addressOfInterpreterFrameBCX() { ++ return addressOfStackSlot(INTERPRETER_FRAME_BCX_OFFSET); ++ } ++ ++ public int getInterpreterFrameBCI() { ++ // FIXME: this is not atomic with respect to GC and is unsuitable ++ // for use in a non-debugging, or reflective, system. Need to ++ // figure out how to express this. ++ Address bcp = addressOfInterpreterFrameBCX().getAddressAt(0); ++ Address methodHandle = addressOfInterpreterFrameMethod().getAddressAt(0); ++ Method method = (Method)Metadata.instantiateWrapperFor(methodHandle); ++ return bcpToBci(bcp, method); ++ } ++ ++ public Address addressOfInterpreterFrameMDX() { ++ return addressOfStackSlot(INTERPRETER_FRAME_MDX_OFFSET); ++ } ++ ++ // FIXME ++ //inline int frame::interpreter_frame_monitor_size() { ++ // return BasicObjectLock::size(); ++ //} ++ ++ // expression stack ++ // (the max_stack arguments are used by the GC; see class FrameClosure) ++ ++ public Address addressOfInterpreterFrameExpressionStack() { ++ Address monitorEnd = interpreterFrameMonitorEnd().address(); ++ return monitorEnd.addOffsetTo(-1 * VM.getVM().getAddressSize()); ++ } ++ ++ public int getInterpreterFrameExpressionStackDirection() { return -1; } ++ ++ // top of expression stack ++ public Address addressOfInterpreterFrameTOS() { ++ return getSP(); ++ } ++ ++ /** Expression stack from top down */ ++ public Address addressOfInterpreterFrameTOSAt(int slot) { ++ return addressOfInterpreterFrameTOS().addOffsetTo(slot * VM.getVM().getAddressSize()); ++ } ++ ++ public Address getInterpreterFrameSenderSP() { ++ if (Assert.ASSERTS_ENABLED) { ++ Assert.that(isInterpretedFrame(), "interpreted frame expected"); ++ } ++ return addressOfStackSlot(INTERPRETER_FRAME_SENDER_SP_OFFSET).getAddressAt(0); ++ } ++ ++ // Monitors ++ public BasicObjectLock interpreterFrameMonitorBegin() { ++ return new BasicObjectLock(addressOfStackSlot(INTERPRETER_FRAME_MONITOR_BLOCK_BOTTOM_OFFSET)); ++ } ++ ++ public BasicObjectLock interpreterFrameMonitorEnd() { ++ Address result = addressOfStackSlot(INTERPRETER_FRAME_MONITOR_BLOCK_TOP_OFFSET).getAddressAt(0); ++ if (Assert.ASSERTS_ENABLED) { ++ // make sure the pointer points inside the frame ++ Assert.that(AddressOps.gt(getFP(), result), "result must < than frame pointer"); ++ Assert.that(AddressOps.lte(getSP(), result), "result must >= than stack pointer"); ++ } ++ return new BasicObjectLock(result); ++ } ++ ++ public int interpreterFrameMonitorSize() { ++ return BasicObjectLock.size(); ++ } ++ ++ // Method ++ public Address addressOfInterpreterFrameMethod() { ++ return addressOfStackSlot(INTERPRETER_FRAME_METHOD_OFFSET); ++ } ++ ++ // Constant pool cache ++ public Address addressOfInterpreterFrameCPCache() { ++ return addressOfStackSlot(INTERPRETER_FRAME_CACHE_OFFSET); ++ } ++ ++ // Entry frames ++ public JavaCallWrapper getEntryFrameCallWrapper() { ++ return new SW64JavaCallWrapper(addressOfStackSlot(ENTRY_FRAME_CALL_WRAPPER_OFFSET).getAddressAt(0)); ++ } ++ ++ protected Address addressOfSavedOopResult() { ++ // offset is 2 for compiler2 and 3 for compiler1 ++ return getSP().addOffsetTo((VM.getVM().isClientCompiler() ? 2 : 3) * ++ VM.getVM().getAddressSize()); ++ } ++ ++ protected Address addressOfSavedReceiver() { ++ return getSP().addOffsetTo(-4 * VM.getVM().getAddressSize()); ++ } ++ ++ private void dumpStack() { ++ for (Address addr = getSP().addOffsetTo(-4 * VM.getVM().getAddressSize()); ++ AddressOps.lt(addr, getSP()); ++ addr = addr.addOffsetTo(VM.getVM().getAddressSize())) { ++ System.out.println(addr + ": " + addr.getAddressAt(0)); ++ } ++ System.out.println("-----------------------"); ++ for (Address addr = getSP(); ++ AddressOps.lte(addr, getSP().addOffsetTo(20 * VM.getVM().getAddressSize())); ++ addr = addr.addOffsetTo(VM.getVM().getAddressSize())) { ++ System.out.println(addr + ": " + addr.getAddressAt(0)); ++ } ++ } ++} +diff --git a/hotspot/agent/src/share/classes/sun/jvm/hotspot/runtime/sw64/SW64JavaCallWrapper.java b/hotspot/agent/src/share/classes/sun/jvm/hotspot/runtime/sw64/SW64JavaCallWrapper.java +new file mode 100755 +index 0000000000..1f6b5b1f40 +--- /dev/null ++++ b/hotspot/agent/src/share/classes/sun/jvm/hotspot/runtime/sw64/SW64JavaCallWrapper.java +@@ -0,0 +1,57 @@ ++/* ++ * Copyright (c) 2003, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2015, Red Hat Inc. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++package sun.jvm.hotspot.runtime.sw64; ++ ++import java.util.*; ++import sun.jvm.hotspot.debugger.*; ++import sun.jvm.hotspot.types.*; ++import sun.jvm.hotspot.runtime.*; ++ ++public class SW64JavaCallWrapper extends JavaCallWrapper { ++ private static AddressField lastJavaFPField; ++ ++ static { ++ VM.registerVMInitializedObserver(new Observer() { ++ public void update(Observable o, Object data) { ++ initialize(VM.getVM().getTypeDataBase()); ++ } ++ }); ++ } ++ ++ private static synchronized void initialize(TypeDataBase db) { ++ Type type = db.lookupType("JavaFrameAnchor"); ++ ++ lastJavaFPField = type.getAddressField("_last_Java_fp"); ++ } ++ ++ public SW64JavaCallWrapper(Address addr) { ++ super(addr); ++ } ++ ++ public Address getLastJavaFP() { ++ return lastJavaFPField.getValue(addr.addOffsetTo(anchorField.getOffset())); ++ } ++} +diff --git a/hotspot/agent/src/share/classes/sun/jvm/hotspot/runtime/sw64/SW64RegisterMap.java b/hotspot/agent/src/share/classes/sun/jvm/hotspot/runtime/sw64/SW64RegisterMap.java +new file mode 100755 +index 0000000000..ded1591a6b +--- /dev/null ++++ b/hotspot/agent/src/share/classes/sun/jvm/hotspot/runtime/sw64/SW64RegisterMap.java +@@ -0,0 +1,52 @@ ++/* ++ * Copyright (c) 2001, 2012, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2015, Red Hat Inc. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++package sun.jvm.hotspot.runtime.sw64; ++ ++import sun.jvm.hotspot.debugger.*; ++import sun.jvm.hotspot.runtime.*; ++ ++public class SW64RegisterMap extends RegisterMap { ++ ++ /** This is the only public constructor */ ++ public SW64RegisterMap(JavaThread thread, boolean updateMap) { ++ super(thread, updateMap); ++ } ++ ++ protected SW64RegisterMap(RegisterMap map) { ++ super(map); ++ } ++ ++ public Object clone() { ++ SW64RegisterMap retval = new SW64RegisterMap(this); ++ return retval; ++ } ++ ++ // no PD state to clear or copy: ++ protected void clearPD() {} ++ protected void initializePD() {} ++ protected void initializeFromPD(RegisterMap map) {} ++ protected Address getLocationPD(VMReg reg) { return null; } ++} +diff --git a/hotspot/agent/src/share/classes/sun/jvm/hotspot/utilities/PlatformInfo.java b/hotspot/agent/src/share/classes/sun/jvm/hotspot/utilities/PlatformInfo.java +index aa69257866..1522853002 100644 +--- a/hotspot/agent/src/share/classes/sun/jvm/hotspot/utilities/PlatformInfo.java ++++ b/hotspot/agent/src/share/classes/sun/jvm/hotspot/utilities/PlatformInfo.java +@@ -61,6 +61,8 @@ public class PlatformInfo { + return "x86"; + } else if (cpu.equals("sparc") || cpu.equals("sparcv9")) { + return "sparc"; ++ } else if (cpu.equals("sw_64") || cpu.equals("sw64")) { ++ return "sw64"; + } else if (cpu.equals("ia64") || cpu.equals("amd64") || cpu.equals("x86_64")) { + return cpu; + } else if (cpu.equals("aarch64")) { +diff --git a/hotspot/make/defs.make b/hotspot/make/defs.make +index a3573da56f..d35cabf230 100644 +--- a/hotspot/make/defs.make ++++ b/hotspot/make/defs.make +@@ -285,7 +285,7 @@ ifneq ($(OSNAME),windows) + + # Use uname output for SRCARCH, but deal with platform differences. If ARCH + # is not explicitly listed below, it is treated as x86. +- SRCARCH ?= $(ARCH/$(filter sparc sparc64 ia64 amd64 x86_64 ppc ppc64 ppc64le zero aarch64,$(ARCH))) ++ SRCARCH ?= $(ARCH/$(filter sparc sparc64 ia64 amd64 x86_64 ppc ppc64 ppc64le zero aarch64 sw64,$(ARCH))) + ARCH/ = x86 + ARCH/sparc = sparc + ARCH/sparc64= sparc +@@ -295,6 +295,7 @@ ifneq ($(OSNAME),windows) + ARCH/ppc64 = ppc + ARCH/ppc64le= ppc + ARCH/ppc = ppc ++ ARCH/sw64 = sw64 + ARCH/zero = zero + ARCH/aarch64 = aarch64 + +@@ -332,9 +333,10 @@ ifneq ($(OSNAME),windows) + LIBARCH/sparcv9 = sparcv9 + LIBARCH/ia64 = ia64 + LIBARCH/ppc64 = ppc64 ++ LIBARCH/sw64 = sw64 + LIBARCH/zero = $(ZERO_LIBARCH) + +- LP64_ARCH += sparcv9 amd64 ia64 ppc64 aarch64 zero ++ LP64_ARCH += sparcv9 amd64 ia64 ppc64 aarch64 sw64 zero + endif + + # Required make macro settings for all platforms +diff --git a/hotspot/make/linux/Makefile b/hotspot/make/linux/Makefile +index e8f2010412..0132ec0c30 100644 +--- a/hotspot/make/linux/Makefile ++++ b/hotspot/make/linux/Makefile +@@ -75,6 +75,12 @@ ifneq (,$(findstring $(ARCH), ppc ppc64)) + endif + endif + ++# C1 is not ported on sw64, so we cannot build a tiered VM: ++# SW TODO ++ifeq ($(ARCH),sw64) ++ FORCE_TIERED=0 ++endif ++ + ifdef LP64 + ifeq ("$(filter $(LP64_ARCH),$(BUILDARCH))","") + _JUNK_ := $(shell echo >&2 \ +diff --git a/hotspot/make/linux/makefiles/buildtree.make b/hotspot/make/linux/makefiles/buildtree.make +index d453d980fd..39130e1659 100644 +--- a/hotspot/make/linux/makefiles/buildtree.make ++++ b/hotspot/make/linux/makefiles/buildtree.make +@@ -202,6 +202,7 @@ DATA_MODE/sparcv9 = 64 + DATA_MODE/amd64 = 64 + DATA_MODE/ppc64 = 64 + DATA_MODE/aarch64 = 64 ++DATA_MODE/sw64 = 64 + + DATA_MODE = $(DATA_MODE/$(BUILDARCH)) + +diff --git a/hotspot/make/linux/makefiles/defs.make b/hotspot/make/linux/makefiles/defs.make +index ec414639d2..22a822149e 100644 +--- a/hotspot/make/linux/makefiles/defs.make ++++ b/hotspot/make/linux/makefiles/defs.make +@@ -83,6 +83,15 @@ ifneq (,$(findstring $(ARCH), sparc)) + HS_ARCH = sparc + endif + ++# sw64 ++ifeq ($(ARCH), sw64) ++ ARCH_DATA_MODEL = 64 ++ MAKE_ARGS += LP64=1 ++ VM_PLATFORM = linux_sw64 ++ PLATFORM = linux-sw64 ++ HS_ARCH = sw64 ++endif ++ + # i686/i586 and amd64/x86_64 + ifneq (,$(findstring $(ARCH), amd64 x86_64 i686 i586)) + ifeq ($(ARCH_DATA_MODEL), 64) +@@ -309,6 +318,8 @@ ADD_SA_BINARIES/x86 = $(EXPORT_JRE_LIB_ARCH_DIR)/libsaproc.$(LIBRARY_SUFFIX) \ + $(EXPORT_LIB_DIR)/sa-jdi.jar + ADD_SA_BINARIES/sparc = $(EXPORT_JRE_LIB_ARCH_DIR)/libsaproc.$(LIBRARY_SUFFIX) \ + $(EXPORT_LIB_DIR)/sa-jdi.jar ++ADD_SA_BINARIES/sw64 = $(EXPORT_JRE_LIB_ARCH_DIR)/libsaproc.$(LIBRARY_SUFFIX) \ ++ $(EXPORT_LIB_DIR)/sa-jdi.jar + ADD_SA_BINARIES/aarch64 = $(EXPORT_JRE_LIB_ARCH_DIR)/libsaproc.$(LIBRARY_SUFFIX) \ + $(EXPORT_LIB_DIR)/sa-jdi.jar + ifeq ($(ENABLE_FULL_DEBUG_SYMBOLS),1) +@@ -317,10 +328,12 @@ ifeq ($(ENABLE_FULL_DEBUG_SYMBOLS),1) + ADD_SA_BINARIES/x86 += $(EXPORT_JRE_LIB_ARCH_DIR)/libsaproc.diz + ADD_SA_BINARIES/sparc += $(EXPORT_JRE_LIB_ARCH_DIR)/libsaproc.diz + ADD_SA_BINARIES/aarch64 += $(EXPORT_JRE_LIB_ARCH_DIR)/libsaproc.diz ++ ADD_SA_BINARIES/sw64 += $(EXPORT_JRE_LIB_ARCH_DIR)/libsaproc.diz + else + ADD_SA_BINARIES/x86 += $(EXPORT_JRE_LIB_ARCH_DIR)/libsaproc.debuginfo + ADD_SA_BINARIES/sparc += $(EXPORT_JRE_LIB_ARCH_DIR)/libsaproc.debuginfo + ADD_SA_BINARIES/aarch64 += $(EXPORT_JRE_LIB_ARCH_DIR)/libsaproc.debuginfo ++ ADD_SA_BINARIES/sw64 += $(EXPORT_JRE_LIB_ARCH_DIR)/libsaproc.debuginfo + endif + endif + endif +diff --git a/hotspot/make/linux/makefiles/dtrace.make b/hotspot/make/linux/makefiles/dtrace.make +index 386e94b1fe..0d633f3610 100644 +--- a/hotspot/make/linux/makefiles/dtrace.make ++++ b/hotspot/make/linux/makefiles/dtrace.make +@@ -42,7 +42,11 @@ ifneq ($(ALT_SDT_H),) + else + SDT_H_FILE = /usr/include/sys/sdt.h + endif ++ifeq ($(ARCH), sw64) # SW TODO ++DTRACE_ENABLED = ++else + DTRACE_ENABLED = $(shell test -f $(SDT_H_FILE) && echo $(SDT_H_FILE)) ++endif + REASON = "$(SDT_H_FILE) not found" + + ifneq ($(DTRACE_ENABLED),) +diff --git a/hotspot/make/linux/makefiles/gcc.make b/hotspot/make/linux/makefiles/gcc.make +index 70b130b203..88b1cbcab8 100644 +--- a/hotspot/make/linux/makefiles/gcc.make ++++ b/hotspot/make/linux/makefiles/gcc.make +@@ -179,6 +179,7 @@ ARCHFLAG/sparc = -m32 -mcpu=v9 + ARCHFLAG/sparcv9 = -m64 -mcpu=v9 + ARCHFLAG/zero = $(ZERO_ARCHFLAG) + ARCHFLAG/ppc64 = -m64 ++ARCHFLAG/sw64 = -mieee + + CFLAGS += $(ARCHFLAG) + AOUT_FLAGS += $(ARCHFLAG) +@@ -202,7 +203,7 @@ else + endif + + # Compiler warnings are treated as errors +-WARNINGS_ARE_ERRORS = -Werror ++#WARNINGS_ARE_ERRORS = -Werror # SW TODO + + ifeq ($(USE_CLANG), true) + # However we need to clean the code up before we can unrestrictedly enable this option with Clang +@@ -240,7 +241,7 @@ endif + + # The flags to use for an Optimized g++ build + OPT_CFLAGS/SIZE=-Os +-OPT_CFLAGS/SPEED=-O3 ++OPT_CFLAGS/SPEED=-O2 # SW TODO -O3 + + # Hotspot uses very unstrict aliasing turn this optimization off + # This option is added to CFLAGS rather than OPT_CFLAGS +@@ -305,7 +306,7 @@ ifeq ($(USE_CLANG),) + endif + + # Enable linker optimization +-LFLAGS += -Xlinker -O1 ++LFLAGS += -Xlinker -O0 # SW TODO -O1 + + ifeq ($(USE_CLANG),) + # If this is a --hash-style=gnu system, use --hash-style=both +@@ -350,6 +351,7 @@ endif + ifeq ($(DEBUG_BINARIES), true) + CFLAGS += -g + else ++ DEBUG_CFLAGS/sw64 = -g -O0 -mieee # SW TODO + DEBUG_CFLAGS += $(DEBUG_CFLAGS/$(BUILDARCH)) + ifeq ($(DEBUG_CFLAGS/$(BUILDARCH)),) + DEBUG_CFLAGS += -g +diff --git a/hotspot/make/linux/makefiles/sa.make b/hotspot/make/linux/makefiles/sa.make +index cdcb16a1a3..d2532b86c5 100644 +--- a/hotspot/make/linux/makefiles/sa.make ++++ b/hotspot/make/linux/makefiles/sa.make +@@ -108,6 +108,7 @@ $(GENERATED)/sa-jdi.jar:: $(AGENT_FILES) + $(QUIETLY) $(REMOTE) $(RUN.JAR) uf $@ -C $(AGENT_SRC_DIR) META-INF/services/com.sun.jdi.connect.Connector + $(QUIETLY) $(REMOTE) $(RUN.JAVAH) -classpath $(SA_CLASSDIR) -d $(GENERATED) -jni sun.jvm.hotspot.debugger.x86.X86ThreadContext + $(QUIETLY) $(REMOTE) $(RUN.JAVAH) -classpath $(SA_CLASSDIR) -d $(GENERATED) -jni sun.jvm.hotspot.debugger.amd64.AMD64ThreadContext ++ $(QUIETLY) $(REMOTE) $(RUN.JAVAH) -classpath $(SA_CLASSDIR) -d $(GENERATED) -jni sun.jvm.hotspot.debugger.sw64.SW64ThreadContext + $(QUIETLY) $(REMOTE) $(RUN.JAVAH) -classpath $(SA_CLASSDIR) -d $(GENERATED) -jni sun.jvm.hotspot.debugger.aarch64.AARCH64ThreadContext + $(QUIETLY) $(REMOTE) $(RUN.JAVAH) -classpath $(SA_CLASSDIR) -d $(GENERATED) -jni sun.jvm.hotspot.debugger.sparc.SPARCThreadContext + $(QUIETLY) $(REMOTE) $(RUN.JAVAH) -classpath $(SA_CLASSDIR) -d $(GENERATED) -jni sun.jvm.hotspot.asm.Disassembler +diff --git a/hotspot/make/linux/makefiles/sw64.make b/hotspot/make/linux/makefiles/sw64.make +new file mode 100644 +index 0000000000..429f4975fd +--- /dev/null ++++ b/hotspot/make/linux/makefiles/sw64.make +@@ -0,0 +1,49 @@ ++# ++# Copyright (c) 1999, 2010, Oracle and/or its affiliates. All rights reserved. ++# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++# ++# This code is free software; you can redistribute it and/or modify it ++# under the terms of the GNU General Public License version 2 only, as ++# published by the Free Software Foundation. ++# ++# This code is distributed in the hope that it will be useful, but WITHOUT ++# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++# version 2 for more details (a copy is included in the LICENSE file that ++# accompanied this code). ++# ++# You should have received a copy of the GNU General Public License version ++# 2 along with this work; if not, write to the Free Software Foundation, ++# Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++# ++# Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++# or visit www.oracle.com if you need additional information or have any ++# questions. ++# ++# ++ ++# Not included in includeDB because it has no dependencies ++Obj_Files += linux_sw64.o ++ ++# The copied fdlibm routines in sharedRuntimeTrig.o must not be optimized ++OPT_CFLAGS/sharedRuntimeTrig.o = $(OPT_CFLAGS/NOOPT) ++# The copied fdlibm routines in sharedRuntimeTrans.o must not be optimized ++OPT_CFLAGS/sharedRuntimeTrans.o = $(OPT_CFLAGS/NOOPT) ++# Must also specify if CPU is little endian ++CFLAGS += -DVM_LITTLE_ENDIAN ++ ++CFLAGS += -D_LP64=1 ++ ++# The serviceability agent relies on frame pointer (%rbp) to walk thread stack ++CFLAGS += -fno-omit-frame-pointer ++ ++OPT_CFLAGS/compactingPermGenGen.o = -O1 ++OPT_CFLAGS/cardTableExtension.o= -O1 ++#OPT_CFLAGS/subnode.o = -mieee -O3 ++#OPT_CFLAGS/mulnode.o = -mieee -O3 ++#OPT_CFLAGS/connode.o = -mieee -O3 ++#OPT_CFLAGS/addnode.o = -mieee -O3 ++#OPT_CFLAGS/parse2.o = -mieee -O3 ++#OPT_CFLAGS/heapDumper.o = -mieee -O3 ++#OPT_CFLAGS/sharedRuntime.o = -mieee -O2 ++#OPT_CFLAGS/copy.o = -O2 +diff --git a/hotspot/make/linux/platform_sw64 b/hotspot/make/linux/platform_sw64 +new file mode 100755 +index 0000000000..0d874ef792 +--- /dev/null ++++ b/hotspot/make/linux/platform_sw64 +@@ -0,0 +1,17 @@ ++os_family = linux ++ ++arch = sw64 ++ ++arch_model = sw64 ++ ++os_arch = linux_sw64 ++ ++os_arch_model = linux_sw64 ++ ++lib_arch = sw64 ++ ++compiler = gcc ++ ++gnu_dis_arch = sw64 ++ ++sysdefs = -DLINUX -D_GNU_SOURCE -DSW64 +diff --git a/hotspot/make/sa.files b/hotspot/make/sa.files +index d6e728a9a8..8b48e765a7 100644 +--- a/hotspot/make/sa.files ++++ b/hotspot/make/sa.files +@@ -55,6 +55,7 @@ $(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/linux/amd64/*.java \ + $(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/linux/x86/*.java \ + $(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/linux/aarch64/*.java \ + $(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/linux/sparc/*.java \ ++$(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/linux/sw64/*.java \ + $(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/posix/*.java \ + $(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/posix/elf/*.java \ + $(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/proc/*.java \ +@@ -62,10 +63,12 @@ $(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/proc/amd64/*.java \ + $(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/proc/aarch64/*.java \ + $(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/proc/sparc/*.java \ + $(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/proc/x86/*.java \ ++$(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/proc/sw64/*.java \ + $(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/remote/*.java \ + $(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/remote/amd64/*.java \ + $(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/remote/sparc/*.java \ + $(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/remote/x86/*.java \ ++$(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/remote/sw64/*.java \ + $(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/remote/aarch64/*.java \ + $(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/sparc/*.java \ + $(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/win32/coff/*.java \ +@@ -75,6 +78,7 @@ $(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/windbg/x86/*.java \ + $(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/windows/x86/*.java \ + $(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/windows/amd64/*.java \ + $(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/x86/*.java \ ++$(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/sw64/*.java \ + $(AGENT_SRC_DIR)/sun/jvm/hotspot/gc_implementation/g1/*.java \ + $(AGENT_SRC_DIR)/sun/jvm/hotspot/gc_implementation/parallelScavenge/*.java \ + $(AGENT_SRC_DIR)/sun/jvm/hotspot/gc_implementation/shared/*.java \ +@@ -96,11 +100,13 @@ $(AGENT_SRC_DIR)/sun/jvm/hotspot/runtime/linux_amd64/*.java \ + $(AGENT_SRC_DIR)/sun/jvm/hotspot/runtime/linux_aarch64/*.java \ + $(AGENT_SRC_DIR)/sun/jvm/hotspot/runtime/linux_x86/*.java \ + $(AGENT_SRC_DIR)/sun/jvm/hotspot/runtime/linux_sparc/*.java \ ++$(AGENT_SRC_DIR)/sun/jvm/hotspot/runtime/linux_sw64/*.java \ + $(AGENT_SRC_DIR)/sun/jvm/hotspot/runtime/posix/*.java \ + $(AGENT_SRC_DIR)/sun/jvm/hotspot/runtime/solaris_amd64/*.java \ + $(AGENT_SRC_DIR)/sun/jvm/hotspot/runtime/solaris_sparc/*.java \ + $(AGENT_SRC_DIR)/sun/jvm/hotspot/runtime/solaris_x86/*.java \ + $(AGENT_SRC_DIR)/sun/jvm/hotspot/runtime/sparc/*.java \ ++$(AGENT_SRC_DIR)/sun/jvm/hotspot/runtime/sw64/*.java \ + $(AGENT_SRC_DIR)/sun/jvm/hotspot/runtime/x86/*.java \ + $(AGENT_SRC_DIR)/sun/jvm/hotspot/tools/*.java \ + $(AGENT_SRC_DIR)/sun/jvm/hotspot/tools/jcore/*.java \ +diff --git a/hotspot/src/cpu/sw64/vm/assembler_sw64.cpp b/hotspot/src/cpu/sw64/vm/assembler_sw64.cpp +new file mode 100755 +index 0000000000..81b736919f +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/assembler_sw64.cpp +@@ -0,0 +1,432 @@ ++/* ++ * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#include "precompiled.hpp" ++#include "asm/assembler.hpp" ++#include "asm/assembler.inline.hpp" ++#include "gc_interface/collectedHeap.inline.hpp" ++#include "interpreter/interpreter.hpp" ++#include "memory/cardTableModRefBS.hpp" ++#include "memory/resourceArea.hpp" ++#include "prims/methodHandles.hpp" ++#include "runtime/biasedLocking.hpp" ++#include "runtime/interfaceSupport.hpp" ++#include "runtime/objectMonitor.hpp" ++#include "runtime/os.hpp" ++#include "runtime/sharedRuntime.hpp" ++#include "runtime/stubRoutines.hpp" ++#if INCLUDE_ALL_GCS ++#include "gc_implementation/g1/g1CollectedHeap.inline.hpp" ++#include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp" ++#include "gc_implementation/g1/heapRegion.hpp" ++#endif // INCLUDE_ALL_GCS ++ ++#ifdef PRODUCT ++#define BLOCK_COMMENT(str) /* nothing */ ++#define STOP(error) stop(error) ++#else ++#define BLOCK_COMMENT(str) { char line[1024]; sprintf(line,"%s:%s:%d",str,__FILE__, __LINE__); block_comment(line); } ++#define STOP(error) block_comment(error); stop(error) ++#endif ++ ++#define BIND(label) bind(label); BLOCK_COMMENT(#label ":") ++ ++// Implementation of AddressLiteral ++ ++AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) { ++ _is_lval = false; ++ _target = target; ++ _rspec = rspec_from_rtype(rtype, target); ++} ++ ++// Implementation of Address ++ ++Address Address::make_array(ArrayAddress adr) { ++ AddressLiteral base = adr.base(); ++ Address index = adr.index(); ++ assert(index._disp == 0, "must not have disp"); // maybe it can? ++ Address array(index._base, index._index, index._scale, (intptr_t) base.target()); ++ array._rspec = base._rspec; ++ return array; ++} ++ ++// exceedingly dangerous constructor ++Address::Address(address loc, RelocationHolder spec) { ++ _base = noreg; ++ _index = noreg; ++ _scale = no_scale; ++ _disp = (intptr_t) loc; ++ _rspec = spec; ++} ++ ++int Assembler::is_int_mask(int x) { ++ int xx = x; ++ int count = 0; ++ ++ while (x != 0) { ++ x &= (x - 1); ++ count++; ++ } ++ ++ if ((1<>16; ++ int16_t low = (int16_t)(imm); ++ if(is_simm16(imm)){ ++ ldi(reg, R0, imm); ++ } else { ++ ldih(reg, R0, high); ++ ldi(reg, reg, low); ++ if( ((int)high == (-32768)) && (low < 0) ) ++ addw(reg, reg, 0); ++ } ++} ++ ++void Assembler::lldw(Register rt, Address src){ ++ assert(src.index() == noreg, "bad address in Assembler::lldw"); ++ lldw(rt, src.base(), src.disp()); ++} ++ ++void Assembler::lldl(Register rt, Address src){ ++ assert(src.index() == noreg, "bad address in Assembler::lldl"); ++ lldl(rt, src.base(), src.disp()); ++} ++ ++ ++void Assembler::ldw_unsigned(Register rt, Address src){ ++ assert(src.index() == noreg, "bad address in Assembler::ldw_unsigned"); ++ ldw_unsigned(rt, src.base(), src.disp()); ++} ++ ++void Assembler::stb(Register rt, Address dst) { ++ assert(dst.index() == noreg, "bad address in Assembler::stb"); ++ stb(rt, dst.base(), dst.disp()); ++} ++ ++void Assembler::stl(Register rt, Address dst) { ++ Register src = rt; ++ Register base = dst.base(); ++ Register index = dst.index(); ++ ++ int scale = dst.scale(); ++ int disp = dst.disp(); ++ ++ if(index != noreg) { ++ if(is_simm16(disp)) { ++ if (scale == 0) { ++ addl(AT, base, index); ++ } else { ++ slll(AT, index, scale); ++ addl(AT, base, AT); ++ } ++ stl(src, AT, disp); ++ } else { ++ if (scale == 0) { ++ li32(AT,disp); ++ addl(AT, AT, base); ++ addl(AT, AT, index); ++ stl(src, AT, 0); ++ } else { ++ stl(T12, SP, -wordSize);//This should be T12 instead of T9. jx ++ add_simm16(SP, SP, -wordSize); ++ ++ slll(AT, index, scale); ++ addl(AT, base, AT); ++ li32(T12,disp); ++ addl(AT, AT, T12); ++ stl(src, AT, 0); ++ ++ ldl(T12, SP, 0); ++ add_simm16(SP, SP, wordSize); ++ } ++ } ++ } else { ++ if(is_simm16(disp)) { ++ stl(src, base, disp); ++ } else { ++ li32(AT,disp); ++ addl(AT, base, AT); ++ stl(src, AT, 0); ++ } ++ } ++} ++ ++void Assembler::sth(Register rt, Address dst) { ++ assert(dst.index() == noreg, "bad address in Assembler::sth"); ++ sth(rt, dst.base(), dst.disp()); ++} ++ ++void Assembler::stw(Register rt, Address dst) { ++ Register src = rt; ++ Register base = dst.base(); ++ Register index = dst.index(); ++ ++ int scale = dst.scale(); ++ int disp = dst.disp(); ++ ++ if(index != noreg) { ++ if( Assembler::is_simm16(disp) ) { ++ if (scale == 0) { ++ addl(AT, base, index); ++ } else { ++ slll(AT, index, scale); ++ addl(AT, base, AT); ++ } ++ stw(src, AT, disp); ++ } else { ++ if (scale == 0) { ++ li32(AT,disp); ++ addl(AT, AT, base); ++ addl(AT, AT, index); ++ stw(src, AT, 0); ++ } else { ++ stl(T12, SP, -wordSize); ++ add_simm16(SP, SP, -wordSize); ++ ++ slll(AT, index, scale); ++ addl(AT, base, AT); ++ li32(T12,disp); ++ addl(AT, AT, T12); ++ stw(src, AT, 0); ++ ++ ldl(T12, SP, 0); ++ add_simm16(SP, SP, wordSize); ++ } ++ } ++ } else { ++ if( Assembler::is_simm16(disp) ) { ++ stw(src, base, disp); ++ } else { ++ li32(AT,disp); ++ addl(AT, base, AT); ++ stw(src, AT, 0); ++ } ++} ++} ++ ++void Assembler::lstw(Register rt, Address dst) { ++ assert(dst.index() == noreg, "bad address in Assembler::lstw"); ++ lstw(rt, dst.base(), dst.disp()); ++} ++ ++void Assembler::lstl(Register rt, Address dst) { ++ assert(dst.index() == noreg, "bad address in Assembler::lstl"); ++ lstl(rt, dst.base(), dst.disp()); ++} ++ ++void Assembler::flds(FloatRegister rt, Address src) { ++ assert(src.index() == noreg, "bad address in Assembler::flds"); ++ flds(rt, src.base(), src.disp()); ++} ++ ++void Assembler::fldd(FloatRegister rt, Address src) { ++ assert(src.index() == noreg, "bad address in Assembler::fldd"); ++ fldd(rt, src.base(), src.disp()); ++} ++ ++void Assembler::fsts(FloatRegister rt, Address dst) { ++ assert(dst.index() == noreg, "bad address in Assembler::fsts"); ++ fsts(rt, dst.base(), dst.disp()); ++} ++ ++void Assembler::fstd(FloatRegister rt, Address dst) { ++ assert(dst.index() == noreg, "bad address in Assembler::fstd"); ++ fstd(rt, dst.base(), dst.disp()); ++} ++ ++////void Assembler::j(address entry) { ++//// Unimplemented(); ++////} ++//// ++////void Assembler::jal(address entry) { ++//// Unimplemented(); ++////} +diff --git a/hotspot/src/cpu/sw64/vm/assembler_sw64.hpp b/hotspot/src/cpu/sw64/vm/assembler_sw64.hpp +new file mode 100755 +index 0000000000..f0d777be76 +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/assembler_sw64.hpp +@@ -0,0 +1,2437 @@ ++/* ++ * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_SW64_VM_ASSEMBLER_SW64_HPP ++#define CPU_SW64_VM_ASSEMBLER_SW64_HPP ++ ++#include "asm/register.hpp" ++ ++class BiasedLockingCounters; ++ ++// Define some macros to help SW64 Instructions' implementation. ++#define OP(x) (((x) & 0x3F) << 26) ++#define PCD(oo) (OP(oo)) ++#define OPMEM(oo) (OP(oo)) ++#define BRA(oo) (OP(oo)) ++#define OFP(oo,ff) (OP(oo) | (((ff) & 0xFF) << 5)) ++#define FMA(oo,ff) (OP(oo) | (((ff) & 0x3F) << 10)) ++#define MFC(oo,ff) (OP(oo) | ((ff) & 0xFFFF)) ++#define MBR(oo,h) (OP(oo) | (((h) & 3) << 14)) ++#define OPR(oo,ff) (OP(oo) | (((ff) & 0xFF) << 5)) ++#define OPRL(oo,ff) (OP(oo) | (((ff) & 0xFF) << 5)) ++#define TOPR(oo,ff) (OP(oo) | (((ff) & 0x07) << 10)) ++#define TOPRL(oo,ff) (OP(oo) | (((ff) & 0x07) << 10)) ++ ++#define ATMEM(oo,h) (OP(oo) | (((h) & 0xF) << 12)) ++#define PRIRET(oo,h) (OP(oo) | (((h) & 0x1) << 20)) ++#define EV6HWMEM(oo,ff) (OP(oo) | (((ff) & 0xF) << 12)) ++#define CSR(oo,ff) (OP(oo) | (((ff) & 0xFF) << 8)) ++ ++#define LOGX(oo,ff) (OP(oo) | (((ff) & 0x3F) << 10)) ++#define PSE_LOGX(oo,ff) (OP(oo) | (((ff) & 0x3F) << 10) | (((ff) >> 0x6) << 26 ) | 0x3E0 ) ++ ++// Note: A register location is represented via a Register, not ++// via an address for efficiency & simplicity reasons. ++ ++class ArrayAddress; ++ ++class Address VALUE_OBJ_CLASS_SPEC { ++ public: ++ enum ScaleFactor { ++ no_scale = -1, ++ times_1 = 0, ++ times_2 = 1, ++ times_4 = 2, ++ times_8 = 3, ++ times_ptr = times_8 ++ }; ++ ++ static ScaleFactor times(int size) { ++ assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size"); ++ if (size == 8) return times_8; ++ if (size == 4) return times_4; ++ if (size == 2) return times_2; ++ return times_1; ++ } ++ ++ private: ++ Register _base; ++ Register _index; ++ ScaleFactor _scale; ++ int _disp; ++ RelocationHolder _rspec; ++ ++ // Easily misused constructors make them private ++ Address(address loc, RelocationHolder spec); ++ Address(int disp, address loc, relocInfo::relocType rtype); ++ Address(int disp, address loc, RelocationHolder spec); ++ ++ public: ++ ++ // creation ++ Address() ++ : _base(noreg), ++ _index(noreg), ++ _scale(no_scale), ++ _disp(0) { ++ } ++ ++ // No default displacement otherwise Register can be implicitly ++ // converted to 0(Register) which is quite a different animal. ++ ++ Address(Register base, int disp = 0) ++ : _base(base), ++ _index(noreg), ++ _scale(no_scale), ++ _disp(disp) { ++ } ++ ++ Address(Register base, Register index, ScaleFactor scale, int disp = 0) ++ : _base (base), ++ _index(index), ++ _scale(scale), ++ _disp (disp) { ++ assert(!index->is_valid() == (scale == Address::no_scale), ++ "inconsistent address"); ++ } ++ ++ // The following two overloads are used in connection with the ++ // ByteSize type (see sizes.hpp). They simplify the use of ++ // ByteSize'd arguments in assembly code. Note that their equivalent ++ // for the optimized build are the member functions with int disp ++ // argument since ByteSize is mapped to an int type in that case. ++ // ++ // Note: DO NOT introduce similar overloaded functions for WordSize ++ // arguments as in the optimized mode, both ByteSize and WordSize ++ // are mapped to the same type and thus the compiler cannot make a ++ // distinction anymore (=> compiler errors). ++ ++#ifdef ASSERT ++ Address(Register base, ByteSize disp) ++ : _base(base), ++ _index(noreg), ++ _scale(no_scale), ++ _disp(in_bytes(disp)) { ++ } ++ ++ Address(Register base, Register index, ScaleFactor scale, ByteSize disp) ++ : _base(base), ++ _index(index), ++ _scale(scale), ++ _disp(in_bytes(disp)) { ++ assert(!index->is_valid() == (scale == Address::no_scale), ++ "inconsistent address"); ++ } ++#endif // ASSERT ++ ++ // accessors ++ bool uses(Register reg) const { return _base == reg || _index == reg; } ++ Register base() const { return _base; } ++ Register index() const { return _index; } ++ ScaleFactor scale() const { return _scale; } ++ int disp() const { return _disp; } ++ ++ static Address make_array(ArrayAddress); ++ ++ friend class Assembler; ++ friend class MacroAssembler; ++ friend class LIR_Assembler; // base/index/scale/disp ++}; ++ ++ ++// Calling convention ++class Argument VALUE_OBJ_CLASS_SPEC { ++ private: ++ int _number; ++ public: ++ enum { ++ n_register_parameters = 6, // 6 integer registers used to pass parameters ++ n_float_register_parameters = 6 // 6 float registers used to pass parameters ++ }; ++ ++ Argument(int number):_number(number){ } ++ Argument successor() {return Argument(number() + 1);} ++ ++ int number()const {return _number;} ++ bool is_Register()const {return _number < n_register_parameters;} ++ bool is_FloatRegister()const {return _number < n_float_register_parameters;} ++ ++ Register as_Register()const { ++ assert(is_Register(), "must be a register argument"); ++ return ::as_Register(A0->encoding() + _number); ++ } ++ FloatRegister as_FloatRegister()const { ++ assert(is_FloatRegister(), "must be a float register argument"); ++ return ::as_FloatRegister(F16->encoding() + _number); ++ } ++ ++ Address as_caller_address()const {return Address(SP, (number() LP64_ONLY( -n_register_parameters)) * wordSize);} ++}; ++ ++ ++ ++// ++// AddressLiteral has been split out from Address because operands of this type ++// need to be treated specially on 32bit vs. 64bit platforms. By splitting it out ++// the few instructions that need to deal with address literals are unique and the ++// MacroAssembler does not have to implement every instruction in the Assembler ++// in order to search for address literals that may need special handling depending ++// on the instruction and the platform. As small step on the way to merging i486/amd64 ++// directories. ++// ++class AddressLiteral VALUE_OBJ_CLASS_SPEC { ++ friend class ArrayAddress; ++ RelocationHolder _rspec; ++ // Typically we use AddressLiterals we want to use their rval ++ // However in some situations we want the lval (effect address) of the item. ++ // We provide a special factory for making those lvals. ++ bool _is_lval; ++ ++ // If the target is far we'll need to load the ea of this to ++ // a register to reach it. Otherwise if near we can do rip ++ // relative addressing. ++ address _target; ++ ++ protected: ++ // creation ++ AddressLiteral() ++ : _is_lval(false), ++ _target(NULL) ++ {} ++ ++ public: ++ ++ AddressLiteral(address target, relocInfo::relocType rtype); ++ ++ AddressLiteral(address target, RelocationHolder const& rspec) ++ : _rspec(rspec), ++ _is_lval(false), ++ _target(target) ++ {} ++ ++ // 32-bit complains about a multiple declaration for int*. ++ AddressLiteral(intptr_t* addr, relocInfo::relocType rtype = relocInfo::none) ++ : _target((address) addr), ++ _rspec(rspec_from_rtype(rtype, (address) addr)) {} ++ ++ AddressLiteral addr() { ++ AddressLiteral ret = *this; ++ ret._is_lval = true; ++ return ret; ++ } ++ ++ ++ private: ++ ++ address target() { return _target; } ++ bool is_lval() { return _is_lval; } ++ ++ relocInfo::relocType reloc() const { return _rspec.type(); } ++ const RelocationHolder& rspec() const { return _rspec; } ++ ++ friend class Assembler; ++ friend class MacroAssembler; ++ friend class Address; ++ friend class LIR_Assembler; ++ ++ RelocationHolder rspec_from_rtype(relocInfo::relocType rtype, address addr) { ++ switch (rtype) { ++ case relocInfo::external_word_type: ++ return external_word_Relocation::spec(addr); ++ case relocInfo::internal_word_type: ++ return internal_word_Relocation::spec(addr); ++ case relocInfo::opt_virtual_call_type: ++ return opt_virtual_call_Relocation::spec(); ++ case relocInfo::static_call_type: ++ return static_call_Relocation::spec(); ++ case relocInfo::runtime_call_type: ++ return runtime_call_Relocation::spec(); ++ case relocInfo::poll_type: ++ case relocInfo::poll_return_type: ++ return Relocation::spec_simple(rtype); ++ case relocInfo::none: ++ case relocInfo::oop_type: ++ // Oops are a special case. Normally they would be their own section ++ // but in cases like icBuffer they are literals in the code stream that ++ // we don't have a section for. We use none so that we get a literal address ++ // which is always patchable. ++ return RelocationHolder(); ++ default: ++ ShouldNotReachHere(); ++ return RelocationHolder(); ++ } ++ } ++ ++}; ++ ++// Convience classes ++class RuntimeAddress: public AddressLiteral { ++ ++ public: ++ ++ RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {} ++ ++}; ++ ++class OopAddress: public AddressLiteral { ++ ++ public: ++ ++ OopAddress(address target) : AddressLiteral(target, relocInfo::oop_type){} ++ ++}; ++ ++class ExternalAddress: public AddressLiteral { ++ ++ public: ++ ++ ExternalAddress(address target) : AddressLiteral(target, relocInfo::external_word_type){} ++ ++}; ++ ++class InternalAddress: public AddressLiteral { ++ ++ public: ++ ++ InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {} ++ ++}; ++ ++// x86 can do array addressing as a single operation since disp can be an absolute ++// address amd64 can't. We create a class that expresses the concept but does extra ++// magic on amd64 to get the final result ++ ++class ArrayAddress VALUE_OBJ_CLASS_SPEC { ++ private: ++ ++ AddressLiteral _base; ++ Address _index; ++ ++ public: ++ ++ ArrayAddress() {}; ++ ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {}; ++ AddressLiteral base() { return _base; } ++ Address index() { return _index; } ++ ++}; ++ ++const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY( 512 / wordSize); ++ ++// The SW Assembler: Pure assembler doing NO optimizations on the instruction ++// level ; i.e., what you write is what you get. The Assembler is generating code into ++// a CodeBuffer. ++ ++class Assembler : public AbstractAssembler { ++ friend class AbstractAssembler; // for the non-virtual hack ++ friend class LIR_Assembler; // as_Address() ++ friend class StubGenerator; ++ ++ public: ++ enum Condition { ++ zero , ++ notZero , ++ equal , ++ notEqual , ++ less , ++ lessEqual , ++ greater , ++ greaterEqual , ++ below , ++ belowEqual , ++ above , ++ aboveEqual ++ }; ++ ++ static const int LogInstructionSize = 2; ++ static const int InstructionSize = 1 << LogInstructionSize; ++ ++ enum WhichOperand { ++ imm_operand = 0, // embedded 32-bit|64-bit immediate operand ++ disp32_operand = 1, // embedded 32-bit displacement or address ++ call32_operand = 2, // embedded 32-bit self-relative displacement ++ narrow_oop_operand = 3, // embedded 32-bit immediate narrow oop ++ _WhichOperand_limit = 4 ++ }; ++ ++ static int opcode(int insn) { return (insn>>26)&0x3f; } ++ static int rs(int insn) { return (insn>>21)&0x1f; } ++ static int rt(int insn) { return (insn>>16)&0x1f; } ++ static int rd(int insn) { return (insn>>11)&0x1f; } ++ static int sa(int insn) { return (insn>>6)&0x1f; } ++ static int special(int insn) { return insn&0x3f; } ++ static int imm_off(int insn) { return (short)low16(insn); } ++ ++ static int low (int x, int l) { return bitfield(x, 0, l); } ++ static int low16(int x) { return low(x, 16); } ++ static int low26(int x) { return low(x, 26); } ++ ++/* SW64 new instrunction enum code */ ++ public: ++ enum ops_mem { ++ op_call = OPMEM(0x01), ++ op_ret = OPMEM(0x02), ++ op_jmp = OPMEM(0x03), ++ op_ldwe = OPMEM(0x09), op_fillcs = op_ldwe, ++ op_ldse = OPMEM(0x0A), op_e_fillcs = op_ldse, ++ op_ldde = OPMEM(0x0B), op_fillcs_e = op_ldde, ++ op_vlds = OPMEM(0x0C), op_e_fillde = op_vlds, ++ op_vldd = OPMEM(0x0D), ++ op_vsts = OPMEM(0x0E), ++ op_vstd = OPMEM(0x0F), ++ op_ldbu = OPMEM(0x20), op_flushd = op_ldbu, ++ op_ldhu = OPMEM(0x21), op_evictdg = op_ldhu, ++ op_ldw = OPMEM(0x22), op_s_fillcs = op_ldw, ++ op_ldl = OPMEM(0x23), op_s_fillde = op_ldl, ++ op_ldl_u = OPMEM(0x24), op_evictdl = op_ldl_u, ++ op_flds = OPMEM(0x26), op_fillde = op_flds, ++ op_fldd = OPMEM(0x27), op_fillde_e = op_fldd, ++ op_stb = OPMEM(0x28), ++ op_sth = OPMEM(0x29), ++ op_stw = OPMEM(0x2A), ++ op_stl = OPMEM(0x2B), ++ op_stl_u = OPMEM(0x2C), ++ op_fsts = OPMEM(0x2E), ++ op_fstd = OPMEM(0x2F), ++ op_ldi = OPMEM(0x3E), ++ op_ldih = OPMEM(0x3F) ++// unop = OPMEM(0x3F) | (30 << 16), ++ }; ++ ++ enum ops_atmem { ++ op_lldw = ATMEM(0x08, 0x0), ++ op_lldl = ATMEM(0x08, 0x1), ++ op_ldw_inc = ATMEM(0x08, 0x2), //SW2F ++ op_ldl_inc = ATMEM(0x08, 0x3), //SW2F ++ op_ldw_dec = ATMEM(0x08, 0x4), //SW2F ++ op_ldl_dec = ATMEM(0x08, 0x5), //SW2F ++ op_ldw_set = ATMEM(0x08, 0x6), //SW2F ++ op_ldl_set = ATMEM(0x08, 0x7), //SW2F ++ op_lstw = ATMEM(0x08, 0x8), ++ op_lstl = ATMEM(0x08, 0x9), ++ op_ldw_nc = ATMEM(0x08, 0xA), ++ op_ldl_nc = ATMEM(0x08, 0xB), ++ op_ldd_nc = ATMEM(0x08, 0xC), ++ op_stw_nc = ATMEM(0x08, 0xD), ++ op_stl_nc = ATMEM(0x08, 0xE), ++ op_std_nc = ATMEM(0x08, 0xF), ++ op_vldw_u = ATMEM(0x1C, 0x0), ++ op_vstw_u = ATMEM(0x1C, 0x1), ++ op_vlds_u = ATMEM(0x1C, 0x2), ++ op_vsts_u = ATMEM(0x1C, 0x3), ++ op_vldd_u = ATMEM(0x1C, 0x4), ++ op_vstd_u = ATMEM(0x1C, 0x5), ++ op_vstw_ul = ATMEM(0x1C, 0x8), ++ op_vstw_uh = ATMEM(0x1C, 0x9), ++ op_vsts_ul = ATMEM(0x1C, 0xA), ++ op_vsts_uh = ATMEM(0x1C, 0xB), ++ op_vstd_ul = ATMEM(0x1C, 0xC), ++ op_vstd_uh = ATMEM(0x1C, 0xD), ++ op_vldd_nc = ATMEM(0x1C, 0xE), ++ op_vstd_nc = ATMEM(0x1C, 0xF), ++ op_ldbu_a = ATMEM(0x1E, 0x0), //SW8A ++ op_ldhu_a = ATMEM(0x1E, 0x1), //SW8A ++ op_ldw_a = ATMEM(0x1E, 0x2), //SW8A ++ op_ldl_a = ATMEM(0x1E, 0x3), //SW8A ++ op_flds_a = ATMEM(0x1E, 0x4), //SW8A ++ op_fldd_a = ATMEM(0x1E, 0x5), //SW8A ++ op_stb_a = ATMEM(0x1E, 0x6), //SW8A ++ op_sth_a = ATMEM(0x1E, 0x7), //SW8A ++ op_stw_a = ATMEM(0x1E, 0x8), //SW8A ++ op_stl_a = ATMEM(0x1E, 0x9), //SW8A ++ op_fsts_a = ATMEM(0x1E, 0xA), //SW8A ++ op_fstd_a = ATMEM(0x1E, 0xB) //SW8A ++ }; ++ ++ enum ops_ev6hwmem { ++ op_pri_ld = EV6HWMEM(0x25, 0x0), ++ op_pri_st = EV6HWMEM(0x2D, 0x0), ++ }; ++ ++ enum ops_opr { ++ op_addw = OPR(0x10, 0x00), ++ op_subw = OPR(0x10, 0x01), ++ op_s4addw = OPR(0x10, 0x02), ++ op_s4subw = OPR(0x10, 0x03), ++ op_s8addw = OPR(0x10, 0x04), ++ op_s8subw = OPR(0x10, 0x05), ++ op_addl = OPR(0x10, 0x08), ++ op_subl = OPR(0x10, 0x09), ++ op_s4addl = OPR(0x10, 0x0A), ++ op_s4subl = OPR(0x10, 0x0B), ++ op_s8addl = OPR(0x10, 0x0C), ++ op_s8subl = OPR(0x10, 0x0D), ++ op_mulw = OPR(0x10, 0x10), ++ op_divw = OPR(0x10, 0x11), //SW8A ++ op_udivw = OPR(0x10, 0x12), //SW8A ++ op_remw = OPR(0x10, 0x13), //SW8A ++ op_uremw = OPR(0x10, 0x14), //SW8A ++ op_mull = OPR(0x10, 0x18), ++ op_umulh = OPR(0x10, 0x19), ++ op_divl = OPR(0x10, 0x1A), //SW8A ++ op_udivl = OPR(0x10, 0x1B), //SW8A ++ op_reml = OPR(0x10, 0x1C), //SW8A ++ op_ureml = OPR(0x10, 0x1D), //SW8A ++ op_addpi = OPR(0x10, 0x1E), //SW8A ++ op_addpis = OPR(0x10, 0x1F), //SW8A ++ op_crc32b = OPR(0x10, 0x20), //SW8A ++ op_crc32h = OPR(0x10, 0x21), //SW8A ++ op_crc32w = OPR(0x10, 0x22), //SW8A ++ op_crc32l = OPR(0x10, 0x23), //SW8A ++ op_crc32cb = OPR(0x10, 0x24), //SW8A ++ op_crc32ch = OPR(0x10, 0x25), //SW8A ++ op_crc32cw = OPR(0x10, 0x26), //SW8A ++ op_crc32cl = OPR(0x10, 0x27), //SW8A ++ op_cmpeq = OPR(0x10, 0x28), ++ op_cmplt = OPR(0x10, 0x29), ++ op_cmple = OPR(0x10, 0x2A), ++ op_cmpult = OPR(0x10, 0x2B), ++ op_cmpule = OPR(0x10, 0x2C), ++ op_sbt = OPR(0x10, 0x2D), //SW8A ++ op_cbt = OPR(0x10, 0x2E), //SW8A ++ op_and = OPR(0x10, 0x38), ++ op_bic = OPR(0x10, 0x39), ++ op_bis = OPR(0x10, 0x3A), ++ op_ornot = OPR(0x10, 0x3B), ++ op_xor = OPR(0x10, 0x3C), ++ op_eqv = OPR(0x10, 0x3D), ++ op_inslb = OPR(0x10, 0x40), //0x10.40~0x10.47 ++ op_inslh = OPR(0x10, 0x41), ++ op_inslw = OPR(0x10, 0x42), ++ op_insll = OPR(0x10, 0x43), ++ op_inshb = OPR(0x10, 0x44), ++ op_inshh = OPR(0x10, 0x45), ++ op_inshw = OPR(0x10, 0x46), ++ op_inshl = OPR(0x10, 0x47), ++ op_slll = OPR(0x10, 0x48), ++ op_srll = OPR(0x10, 0x49), ++ op_sral = OPR(0x10, 0x4A), ++ op_roll = OPR(0x10, 0x4B), //SW8A ++ op_sllw = OPR(0x10, 0x4C), //SW8A ++ op_srlw = OPR(0x10, 0x4D), //SW8A ++ op_sraw = OPR(0x10, 0x4E), //SW8A ++ op_rolw = OPR(0x10, 0x4F), //SW8A ++ op_extlb = OPR(0x10, 0x50), //0x10.50~0x10.57 ++ op_extlh = OPR(0x10, 0x51), ++ op_extlw = OPR(0x10, 0x52), ++ op_extll = OPR(0x10, 0x53), ++ op_exthb = OPR(0x10, 0x54), ++ op_exthh = OPR(0x10, 0x55), ++ op_exthw = OPR(0x10, 0x56), ++ op_exthl = OPR(0x10, 0x57), ++ op_ctpop = OPR(0x10, 0x58), ++ op_ctlz = OPR(0x10, 0x59), ++ op_cttz = OPR(0x10, 0x5A), ++ op_revbh = OPR(0x10, 0x5B), //SW8A ++ op_revbw = OPR(0x10, 0x5C), //SW8A ++ op_revbl = OPR(0x10, 0x5D), //SW8A ++ op_casw = OPR(0x10, 0x5E), //SW8A ++ op_casl = OPR(0x10, 0x5F), //SW8A ++ op_masklb = OPR(0x10, 0x60), //0x10.60~0x10.67 ++ op_masklh = OPR(0x10, 0x61), ++ op_masklw = OPR(0x10, 0x62), ++ op_maskll = OPR(0x10, 0x63), ++ op_maskhb = OPR(0x10, 0x64), ++ op_maskhh = OPR(0x10, 0x65), ++ op_maskhw = OPR(0x10, 0x66), ++ op_maskhl = OPR(0x10, 0x67), ++ op_zap = OPR(0x10, 0x68), ++ op_zapnot = OPR(0x10, 0x69), ++ op_sextb = OPR(0x10, 0x6A), ++ op_sexth = OPR(0x10, 0x6B), ++ op_cmpgeb = OPR(0x10, 0x6C), //0x10.6C ++ op_fimovs = OPR(0x10, 0x70), ++ op_fimovd = OPR(0x10, 0x78), ++ op_cmovdl = OFP(0x10, 0x72), ++ op_cmovdl_g = OFP(0x10, 0x74), ++ op_cmovdl_p = OFP(0x10, 0x7A), ++ op_cmovdl_z = OFP(0x10, 0x7C), ++ op_cmovdl_n = OFP(0x10, 0x80), ++ op_cmovdlu = OFP(0x10, 0x81), ++ op_cmovdlu_g= OFP(0x10, 0x82), ++ op_cmovdlu_p= OFP(0x10, 0x83), ++ op_cmovdlu_z= OFP(0x10, 0x84), ++ op_cmovdlu_n= OFP(0x10, 0x85), ++ op_cmovdw = OFP(0x10, 0x8B), ++ op_cmovdw_g = OFP(0x10, 0x8C), ++ op_cmovdw_p = OFP(0x10, 0x8D), ++ op_cmovdw_z = OFP(0x10, 0x8E), ++ op_cmovdw_n = OFP(0x10, 0x8F), ++ op_cmovdwu = OFP(0x10, 0x86), ++ op_cmovdwu_g= OFP(0x10, 0x87), ++ op_cmovdwu_p= OFP(0x10, 0x88), ++ op_cmovdwu_z= OFP(0x10, 0x89), ++ op_cmovdwu_n= OFP(0x10, 0x8A), ++ op_seleq = TOPR(0x11, 0x0), ++ op_selge = TOPR(0x11, 0x1), ++ op_selgt = TOPR(0x11, 0x2), ++ op_selle = TOPR(0x11, 0x3), ++ op_sellt = TOPR(0x11, 0x4), ++ op_selne = TOPR(0x11, 0x5), ++ op_sellbc = TOPR(0x11, 0x6), ++ op_sellbs = TOPR(0x11, 0x7) ++ }; ++ ++ enum ops_oprl{ ++ op_addw_l = OPRL(0x12, 0x00), ++ op_subw_l = OPRL(0x12, 0x01), ++ op_s4addw_l = OPRL(0x12, 0x02), ++ op_s4subw_l = OPRL(0x12, 0x03), ++ op_s8addw_l = OPRL(0x12, 0x04), ++ op_s8subw_l = OPRL(0x12, 0x05), ++ op_addl_l = OPRL(0x12, 0x08), ++ op_subl_l = OPRL(0x12, 0x09), ++ op_s4addl_l = OPRL(0x12, 0x0A), ++ op_s4subl_l = OPRL(0x12, 0x0B), ++ op_s8addl_l = OPRL(0x12, 0x0C), ++ op_s8subl_l = OPRL(0x12, 0x0D), ++ op_mulw_l = OPRL(0x12, 0x10), ++ op_mull_l = OPRL(0x12, 0x18), ++ op_umulh_l = OPRL(0x12, 0x19), ++ op_cmpeq_l = OPRL(0x12, 0x28), ++ op_cmplt_l = OPRL(0x12, 0x29), ++ op_cmple_l = OPRL(0x12, 0x2A), ++ op_cmpult_l = OPRL(0x12, 0x2B), ++ op_cmpule_l = OPRL(0x12, 0x2C), ++ op_sbt_l = OPRL(0x12, 0x2D), //SW8A ++ op_cbt_l = OPRL(0x12, 0x2E), //SW8A ++ op_and_l = OPRL(0x12, 0x38), ++ op_bic_l = OPRL(0x12, 0x39), ++ op_bis_l = OPRL(0x12, 0x3A), ++ op_ornot_l = OPRL(0x12, 0x3B), ++ op_xor_l = OPRL(0x12, 0x3C), ++ op_eqv_l = OPRL(0x12, 0x3D), ++ op_inslb_l = OPRL(0x12, 0x40), //0x12.40~0x12.47 ++ op_inslh_l = OPRL(0x12, 0x41), ++ op_inslw_l = OPRL(0x12, 0x42), ++ op_insll_l = OPRL(0x12, 0x43), ++ op_inshb_l = OPRL(0x12, 0x44), ++ op_inshh_l = OPRL(0x12, 0x45), ++ op_inshw_l = OPRL(0x12, 0x46), ++ op_inshl_l = OPRL(0x12, 0x47), ++ op_slll_l = OPRL(0x12, 0x48), ++ op_srll_l = OPRL(0x12, 0x49), ++ op_sral_l = OPRL(0x12, 0x4A), ++ op_roll_l = OPRL(0x12, 0x4B), //SW8A ++ op_sllw_l = OPRL(0x12, 0x4C), //SW8A ++ op_srlw_l = OPRL(0x12, 0x4D), //SW8A ++ op_sraw_l = OPRL(0x12, 0x4E), //SW8A ++ op_rolw_l = OPRL(0x12, 0x4F), //SW8A ++ op_extlb_l = OPRL(0x12, 0x50), //0x12.50~0x12.57 ++ op_extlh_l = OPRL(0x12, 0x51), ++ op_extlw_l = OPRL(0x12, 0x52), ++ op_extll_l = OPRL(0x12, 0x53), ++ op_exthb_l = OPRL(0x12, 0x54), ++ op_exthh_l = OPRL(0x12, 0x55), ++ op_exthw_l = OPRL(0x12, 0x56), ++ op_exthl_l = OPRL(0x12, 0x57), ++ op_masklb_l = OPRL(0x12, 0x60), //0x12.60~0x12.67 ++ op_masklh_l = OPRL(0x12, 0x61), ++ op_masklw_l = OPRL(0x12, 0x62), ++ op_maskll_l = OPRL(0x12, 0x63), ++ op_maskhb_l = OPRL(0x12, 0x64), ++ op_maskhh_l = OPRL(0x12, 0x65), ++ op_maskhw_l = OPRL(0x12, 0x66), ++ op_maskhl_l = OPRL(0x12, 0x67), ++ op_zap_l = OPRL(0x12, 0x68), ++ op_zapnot_l = OPRL(0x12, 0x69), ++ op_sextb_l = OPRL(0x12, 0x6A), ++ op_sexth_l = OPRL(0x12, 0x6B), ++ op_cmpgeb_l = OPRL(0x12, 0x6C), //0x12.6C ++ op_seleq_l = TOPRL(0x13, 0x0), ++ op_selge_l = TOPRL(0x13, 0x1), ++ op_selgt_l = TOPRL(0x13, 0x2), ++ op_selle_l = TOPRL(0x13, 0x3), ++ op_sellt_l = TOPRL(0x13, 0x4), ++ op_selne_l = TOPRL(0x13, 0x5), ++ op_sellbc_l = TOPRL(0x13, 0x6), ++ op_sellbs_l = TOPRL(0x13, 0x7) ++ }; ++ ++ enum ops_bra { ++ op_br = BRA(0x04), ++ op_bsr = BRA(0x05), ++ op_beq = BRA(0x30), ++ op_bne = BRA(0x31), ++ op_blt = BRA(0x32), ++ op_ble = BRA(0x33), ++ op_bgt = BRA(0x34), ++ op_bge = BRA(0x35), ++ op_blbc = BRA(0x36), ++ op_blbs = BRA(0x37), ++ op_fbeq = BRA(0x38), ++ op_fbne = BRA(0x39), ++ op_fblt = BRA(0x3A), ++ op_fble = BRA(0x3B), ++ op_fbgt = BRA(0x3C), ++ op_fbge = BRA(0x3D) ++ }; ++ ++ enum ops_fp { ++ op_fadds = OFP(0x18, 0x00), ++ op_faddd = OFP(0x18, 0x01), ++ op_fsubs = OFP(0x18, 0x02), ++ op_fsubd = OFP(0x18, 0x03), ++ op_fmuls = OFP(0x18, 0x04), ++ op_fmuld = OFP(0x18, 0x05), ++ op_fdivs = OFP(0x18, 0x06), ++ op_fdivd = OFP(0x18, 0x07), ++ op_fsqrts = OFP(0x18, 0x08), ++ op_fsqrtd = OFP(0x18, 0x09), ++ op_fcmpeq = OFP(0x18, 0x10), ++ op_fcmple = OFP(0x18, 0x11), ++ op_fcmplt = OFP(0x18, 0x12), ++ op_fcmpun = OFP(0x18, 0x13), ++ op_fcvtsd = OFP(0x18, 0x20), ++ op_fcvtds = OFP(0x18, 0x21), ++ op_fcvtdl_g = OFP(0x18, 0x22), ++ op_fcvtdl_p = OFP(0x18, 0x23), ++ op_fcvtdl_z = OFP(0x18, 0x24), ++ op_fcvtdl_n = OFP(0x18, 0x25), ++ op_fcvtdl = OFP(0x18, 0x27), ++ op_fcvtwl = OFP(0x18, 0x28), ++ op_fcvtlw = OFP(0x18, 0x29), ++ op_fcvtls = OFP(0x18, 0x2D), ++ op_fcvtld = OFP(0x18, 0x2F), ++ op_fcpys = OFP(0x18, 0x30), ++ op_fcpyse = OFP(0x18, 0x31), ++ op_fcpysn = OFP(0x18, 0x32), ++ op_ifmovs = OFP(0x18, 0x40), ++ op_ifmovd = OFP(0x18, 0x41), ++ op_cmovls = OFP(0x18, 0x48), ++ op_cmovld = OFP(0x18, 0x4A), ++ op_cmovuls = OFP(0x18, 0x4C), ++ op_cmovuld = OFP(0x18, 0x4E), ++ op_cmovws = OFP(0x18, 0x49), ++ op_cmovwd = OFP(0x18, 0x4B), ++ op_cmovuws = OFP(0x18, 0x4D), ++ op_cmovuwd = OFP(0x18, 0x4F), ++ op_rfpcr = OFP(0x18, 0x50), ++ op_wfpcr = OFP(0x18, 0x51), ++ op_setfpec0 = OFP(0x18, 0x54), ++ op_setfpec1 = OFP(0x18, 0x55), ++ op_setfpec2 = OFP(0x18, 0x56), ++ op_setfpec3 = OFP(0x18, 0x57), ++ op_frecs = OFP(0x18, 0x58), //SW8A ++ op_frecd = OFP(0x18, 0x59), //SW8A ++ op_fris = OFP(0x18, 0x5A), //SW8A ++ op_fris_g = OFP(0x18, 0x5B), //SW8A ++ op_fris_p = OFP(0x18, 0x5C), //SW8A ++ op_fris_z = OFP(0x18, 0x5D), //SW8A ++ op_fris_n = OFP(0x18, 0x5F), //SW8A ++ op_frid = OFP(0x18, 0x60), //SW8A ++ op_frid_g = OFP(0x18, 0x61), //SW8A ++ op_frid_p = OFP(0x18, 0x62), //SW8A ++ op_frid_z = OFP(0x18, 0x63), //SW8A ++ op_frid_n = OFP(0x18, 0x64), //SW8A ++ op_vaddw = OFP(0x1A, 0x00), ++ op_vsubw = OFP(0x1A, 0x01), ++ op_vcmpgew = OFP(0x1A, 0x02), ++ op_vcmpeqw = OFP(0x1A, 0x03), ++ op_vcmplew = OFP(0x1A, 0x04), ++ op_vcmpltw = OFP(0x1A, 0x05), ++ op_vcmpulew = OFP(0x1A, 0x06), ++ op_vcmpultw = OFP(0x1A, 0x07), ++ op_vsllw = OFP(0x1A, 0x08), ++ op_vsrlw = OFP(0x1A, 0x09), ++ op_vsraw = OFP(0x1A, 0x0A), ++ op_vrolw = OFP(0x1A, 0x0B), ++ op_sllow = OFP(0x1A, 0x0C), ++ op_srlow = OFP(0x1A, 0x0D), ++ op_vaddl = OFP(0x1A, 0x0E), ++ op_vsubl = OFP(0x1A, 0x0F), ++ op_vsllb = OFP(0x1A, 0x10), //SW8A ++ op_vsrlb = OFP(0x1A, 0x11), //SW8A ++ op_vsrab = OFP(0x1A, 0x12), //SW8A ++ op_vrolb = OFP(0x1A, 0x13), //SW8A ++ op_vsllh = OFP(0x1A, 0x14), //SW8A ++ op_vsrlh = OFP(0x1A, 0x15), //SW8A ++ op_vsrah = OFP(0x1A, 0x16), //SW8A ++ op_vrolh = OFP(0x1A, 0x17), //SW8A ++ op_ctpopow = OFP(0x1A, 0x18), ++ op_ctlzow = OFP(0x1A, 0x19), ++ op_vslll = OFP(0x1A, 0x1A), //SW8A ++ op_vsrll = OFP(0x1A, 0x1B), //SW8A ++ op_vsral = OFP(0x1A, 0x1C), //SW8A ++ op_vroll = OFP(0x1A, 0x1D), //SW8A ++ op_vmaxb = OFP(0x1A, 0x1E), //SW8A ++ op_vminb = OFP(0x1A, 0x1F), //SW8A ++ op_vucaddw = OFP(0x1A, 0x40), ++ op_vucsubw = OFP(0x1A, 0x41), ++ op_vucaddh = OFP(0x1A, 0x42), ++ op_vucsubh = OFP(0x1A, 0x43), ++ op_vucaddb = OFP(0x1A, 0x44), ++ op_vucsubb = OFP(0x1A, 0x45), ++ op_sraow = OFP(0x1A, 0x46), //SW8A ++ op_vsumw = OFP(0x1A, 0x47), //SW8A ++ op_vsuml = OFP(0x1A, 0x48), //SW8A ++ op_vsm4r = OFP(0x1A, 0x49), //SW8A, ENCRYPT ++ op_vbinvw = OFP(0x1A, 0x4A), //SW8A, ENCRYPT ++ op_vcmpueqb = OFP(0x1A, 0x4B), //SW8A ++ op_vcmpugtb = OFP(0x1A, 0x4C), //SW8A ++ op_vsm3msw = OFP(0x1A, 0x4D), //SW8A, ENCRYPT ++ op_vmaxh = OFP(0x1A, 0x50), //SW8A ++ op_vminh = OFP(0x1A, 0x51), //SW8A ++ op_vmaxw = OFP(0x1A, 0x52), //SW8A ++ op_vminw = OFP(0x1A, 0x53), //SW8A ++ op_vmaxl = OFP(0x1A, 0x54), //SW8A ++ op_vminl = OFP(0x1A, 0x55), //SW8A ++ op_vumaxb = OFP(0x1A, 0x56), //SW8A ++ op_vuminb = OFP(0x1A, 0x57), //SW8A ++ op_vumaxh = OFP(0x1A, 0x58), //SW8A ++ op_vuminh = OFP(0x1A, 0x59), //SW8A ++ op_vumaxw = OFP(0x1A, 0x5A), //SW8A ++ op_vuminw = OFP(0x1A, 0x5B), //SW8A ++ op_vumaxl = OFP(0x1A, 0x5C), //SW8A ++ op_vuminl = OFP(0x1A, 0x5D), //SW8A ++ op_vadds = OFP(0x1A, 0x80), ++ op_vaddd = OFP(0x1A, 0x81), ++ op_vsubs = OFP(0x1A, 0x82), ++ op_vsubd = OFP(0x1A, 0x83), ++ op_vmuls = OFP(0x1A, 0x84), ++ op_vmuld = OFP(0x1A, 0x85), ++ op_vdivs = OFP(0x1A, 0x86), ++ op_vdivd = OFP(0x1A, 0x87), ++ op_vsqrts = OFP(0x1A, 0x88), ++ op_vsqrtd = OFP(0x1A, 0x89), ++ op_vfcmpeq = OFP(0x1A, 0x8C), ++ op_vfcmple = OFP(0x1A, 0x8D), ++ op_vfcmplt = OFP(0x1A, 0x8E), ++ op_vfcmpun = OFP(0x1A, 0x8F), ++ op_vcpys = OFP(0x1A, 0x90), ++ op_vcpyse = OFP(0x1A, 0x91), ++ op_vcpysn = OFP(0x1A, 0x92), ++ op_vsums = OFP(0x1A, 0x93), //SW8A ++ op_vsumd = OFP(0x1A, 0x94), //SW8A ++ op_vfcvtsd = OFP(0x1A, 0x95), //SW8A ++ op_vfcvtds = OFP(0x1A, 0x96), //SW8A ++ op_vfcvtls = OFP(0x1A, 0x99), //SW8A ++ op_vfcvtld = OFP(0x1A, 0x9A), //SW8A ++ op_vfcvtdl = OFP(0x1A, 0x9B), //SW8A ++ op_vfcvtdl_g = OFP(0x1A, 0x9C), //SW8A ++ op_vfcvtdl_p = OFP(0x1A, 0x9D), //SW8A ++ op_vfcvtdl_z = OFP(0x1A, 0x9E), //SW8A ++ op_vfcvtdl_n = OFP(0x1A, 0x9F), //SW8A ++ op_vfris = OFP(0x1A, 0xA0), //SW8A ++ op_vfris_g = OFP(0x1A, 0xA1), //SW8A ++ op_vfris_p = OFP(0x1A, 0xA2), //SW8A ++ op_vfris_z = OFP(0x1A, 0xA3), //SW8A ++ op_vfris_n = OFP(0x1A, 0xA4), //SW8A ++ op_vfrid = OFP(0x1A, 0xA5), //SW8A ++ op_vfrid_g = OFP(0x1A, 0xA6), //SW8A ++ op_vfrid_p = OFP(0x1A, 0xA7), //SW8A ++ op_vfrid_z = OFP(0x1A, 0xA8), //SW8A ++ op_vfrid_n = OFP(0x1A, 0xA9), //SW8A ++ op_vfrecs = OFP(0x1A, 0xAA), //SW8A ++ op_vfrecd = OFP(0x1A, 0xAB), //SW8A ++ op_vmaxs = OFP(0x1A, 0xAC), //SW8A ++ op_vmins = OFP(0x1A, 0xAD), //SW8A ++ op_vmaxd = OFP(0x1A, 0xAE), //SW8A ++ op_vmind = OFP(0x1A, 0xAF), //SW8A ++ }; ++ ++ enum ops_fpl { ++ op_vaddw_l = OFP(0x1A, 0x20), ++ op_vsubw_l = OFP(0x1A, 0x21), ++ op_vcmpgew_l = OFP(0x1A, 0x22), ++ op_vcmpeqw_l = OFP(0x1A, 0x23), ++ op_vcmplew_l = OFP(0x1A, 0x24), ++ op_vcmpltw_l = OFP(0x1A, 0x25), ++ op_vcmpulew_l = OFP(0x1A, 0x26), ++ op_vcmpultw_l = OFP(0x1A, 0x27), ++ op_vsllw_l = OFP(0x1A, 0x28), ++ op_vsrlw_l = OFP(0x1A, 0x29), ++ op_vsraw_l = OFP(0x1A, 0x2A), ++ op_vrolw_l = OFP(0x1A, 0x2B), ++ op_sllow_l = OFP(0x1A, 0x2C), ++ op_srlow_l = OFP(0x1A, 0x2D), ++ op_vaddl_l = OFP(0x1A, 0x2E), ++ op_vsubl_l = OFP(0x1A, 0x2F), ++ op_vsllb_l = OFP(0x1A, 0x30), //SW8A ++ op_vsrlb_l = OFP(0x1A, 0x31), //SW8A ++ op_vsrab_l = OFP(0x1A, 0x32), //SW8A ++ op_vrolb_l = OFP(0x1A, 0x33), //SW8A ++ op_vsllh_l = OFP(0x1A, 0x34), //SW8A ++ op_vsrlh_l = OFP(0x1A, 0x35), //SW8A ++ op_vsrah_l = OFP(0x1A, 0x36), //SW8A ++ op_vrolh_l = OFP(0x1A, 0x37), //SW8A ++ op_vslll_l = OFP(0x1A, 0x3A), //SW8A ++ op_vsrll_l = OFP(0x1A, 0x3B), //SW8A ++ op_vsral_l = OFP(0x1A, 0x3C), //SW8A ++ op_vroll_l = OFP(0x1A, 0x3D), //SW8A ++ op_vucaddw_l = OFP(0x1A, 0x60), ++ op_vucsubw_l = OFP(0x1A, 0x61), ++ op_vucaddh_l = OFP(0x1A, 0x62), ++ op_vucsubh_l = OFP(0x1A, 0x63), ++ op_vucaddb_l = OFP(0x1A, 0x64), ++ op_vucsubb_l = OFP(0x1A, 0x65), ++ op_sraow_l = OFP(0x1A, 0x66), //SW8A ++ op_vsm4key_l = OFP(0x1A, 0x68), //SW8A, ENCRYPT ++ op_vcmpueqb_l = OFP(0x1A, 0x6B), //SW8A ++ op_vcmpugtb_l = OFP(0x1A, 0x6C), //SW8A ++ op_vfcvtsh_l = OFP(0x1B, 0x35), //SW8A ++ op_vfcvths_l = OFP(0x1B, 0x36) //SW8A ++ }; ++ ++ enum ops_fma { ++ op_fmas = FMA(0x19, 0x00), ++ op_fmad = FMA(0x19, 0x01), ++ op_fmss = FMA(0x19, 0x02), ++ op_fmsd = FMA(0x19, 0x03), ++ op_fnmas = FMA(0x19, 0x04), ++ op_fnmad = FMA(0x19, 0x05), ++ op_fnmss = FMA(0x19, 0x06), ++ op_fnmsd = FMA(0x19, 0x07), ++ op_fseleq = FMA(0x19, 0x10), ++ op_fselne = FMA(0x19, 0x11), ++ op_fsellt = FMA(0x19, 0x12), ++ op_fselle = FMA(0x19, 0x13), ++ op_fselgt = FMA(0x19, 0x14), ++ op_fselge = FMA(0x19, 0x15), ++ op_vmas = FMA(0x1B, 0x00), ++ op_vmad = FMA(0x1B, 0x01), ++ op_vmss = FMA(0x1B, 0x02), ++ op_vmsd = FMA(0x1B, 0x03), ++ op_vnmas = FMA(0x1B, 0x04), ++ op_vnmad = FMA(0x1B, 0x05), ++ op_vnmss = FMA(0x1B, 0x06), ++ op_vnmsd = FMA(0x1B, 0x07), ++ op_vfseleq = FMA(0x1B, 0x10), ++ op_vfsellt = FMA(0x1B, 0x12), ++ op_vfselle = FMA(0x1B, 0x13), ++ op_vseleqw = FMA(0x1B, 0x18), ++ op_vsellbcw = FMA(0x1B, 0x19), ++ op_vselltw = FMA(0x1B, 0x1A), ++ op_vsellew = FMA(0x1B, 0x1B), ++ op_vcpyw = FMA(0x1B, 0x24), ++ op_vcpyf = FMA(0x1B, 0x25), ++ op_vconw = FMA(0x1B, 0x26), ++ op_vshfw = FMA(0x1B, 0x27), ++ op_vcons = FMA(0x1B, 0x28), ++ op_vcond = FMA(0x1B, 0x29), ++ op_vinsectlh = FMA(0x1B, 0x2C), //SW8A ++ op_vinsectlw = FMA(0x1B, 0x2D), //SW8A ++ op_vinsectll = FMA(0x1B, 0x2E), //SW8A ++ op_vinsectlb = FMA(0x1B, 0x2F), //SW8A ++ op_vshfqb = FMA(0x1B, 0x31), //SW8A ++ op_vcpyb = FMA(0x1B, 0x32), //SW8A ++ op_vcpyh = FMA(0x1B, 0x33) //SW8A ++ }; ++ ++ enum ops_fmal { ++ op_vinsw_l = FMA(0x1B, 0x20), ++ op_vinsf_l = FMA(0x1B, 0x21), ++ op_vextw_l = FMA(0x1B, 0x22), ++ op_vextf_l = FMA(0x1B, 0x23), ++ op_vinsb_l = FMA(0x1B, 0x2A), //SW8A ++ op_vinsh_l = FMA(0x1B, 0x2B), //SW8A ++ op_vshfq_l = FMA(0x1B, 0x30), //SW8A ++ op_vsm3r_l = FMA(0x1B, 0x34), //SW8A, ENCRYPT ++ op_vseleqw_l = FMA(0x1B, 0x38), ++ op_vsellbcw_l = FMA(0x1B, 0x39), ++ op_vselltw_l = FMA(0x1B, 0x3A), ++ op_vsellew_l = FMA(0x1B, 0x3B) ++ }; ++ ++ enum ops_extra { ++ op_sys_call = PCD(0x00), ++ op_memb = MFC(0x06, 0x0000), ++ op_imemb = MFC(0x06, 0x0001), //SW8A ++ op_wmemb = MFC(0x06, 0x0002), //SW8A ++ op_rtc = MFC(0x06, 0x0020), ++ op_rcid = MFC(0x06, 0x0040), ++ op_halt = MFC(0x06, 0x0080), ++ op_rd_f = MFC(0x06, 0x1000), //SW2F ++ op_wr_f = MFC(0x06, 0x1020), //SW2F ++ op_rtid = MFC(0x06, 0x1040), ++ op_csrws = CSR(0x06, 0xFC), //SW8A ++ op_csrwc = CSR(0x06, 0xFD), //SW8A ++ op_csrr = CSR(0x06, 0xFE), ++ op_csrw = CSR(0x06, 0xFF), ++ op_pri_ret = PRIRET(0x07, 0x0), ++ op_vlog = LOGX(0x14, 0x00), ++ op_vbisw = PSE_LOGX(0x14, 0x30), ++ op_vxorw = PSE_LOGX(0x14, 0x3c), ++ op_vandw = PSE_LOGX(0x14, 0xc0), ++ op_veqvw = PSE_LOGX(0x14, 0xc3), ++ op_vornotw = PSE_LOGX(0x14, 0xf3), ++ op_vbicw = PSE_LOGX(0x14, 0xfc), ++ op_lbr = PCD(0x1D), //SW8A ++ op_dpfhr = ATMEM(0x1E, 0xE), //SW8A ++ op_dpfhw = ATMEM(0x1E, 0xF), //SW8A ++ }; ++ ++ static int sw2_op(int inst) {return (int)(inst & OP(-1)); } ++ static int sw2_arith_op(int inst) {return (int)(inst & OPR(-1, -1)); } ++ static int sw2_bra_op(int inst) {return (int)(inst & BRA(-1)); } ++ static int sw2_mfc_op(int inst) {return (int)(inst & MFC(-1, -1)); } ++ ++ static Register sw2_ra( int x ) { return as_Register(inv_u_field(x, 25, 21)); } ++ static Register sw2_rb( int x ) { return as_Register(inv_u_field(x, 20, 16)); } ++ static Register sw2_rc( int x ) { return as_Register(inv_u_field(x, 4, 0)); } ++ static int sw2_lit( int x ) { return inv_u_field(x, 20, 13); } ++ static int sw2_bdisp( int x ) { return inv_wdisp(x, 0, 21); } ++ static int sw2_mdisp( int x ) { return inv_simm16(x); } ++ ++ protected: ++ ++ static int insn_ORRI(int op, int rs, int rt, int imm) { assert(is_simm16(imm), "not a signed 16-bit int"); return (op<<26) | (rs<<21) | (rt<<16) | low16(imm); } ++ ++ static int insn_RRRO(int rs, int rt, int rd, int op) { return (rs<<21) | (rt<<16) | (rd<<11) | op; } ++ static int insn_RRSO(int rt, int rd, int sa, int op) { return (rt<<16) | (rd<<11) | (sa<<6) | op; } ++ static int insn_RRCO(int rs, int rt, int code, int op) { return (rs<<21) | (rt<<16) | (code<<6) | op; } ++ ++ //get the offset field of jump/branch instruction ++ int offset(address entry) { ++ assert(is_simm21((entry - pc() - 4) / 4), "change this code"); ++ if (!is_simm21((entry - pc() - 4) / 4)) { ++ tty->print_cr("!!! is_simm21: %x", (entry - pc() - 4) / 4); ++ } ++ return (entry - pc() - 4) / 4; ++ } ++ ++ // x is supposed to fit in a field "nbits" wide ++ // and be sign-extended. Check the range. ++ ++ static void assert_signed_range(intptr_t x, int nbits) { ++ assert(nbits == 32 || (-(1 << nbits-1) <= x && x < ( 1 << nbits-1)), ++ err_msg("value out of range: x=" INTPTR_FORMAT ", nbits=%d", x, nbits)); ++ } ++ ++ static void assert_unsigned_range(intptr_t x, int nbits) { ++ assert( nbits == 32 ++ || 0 <= x && x < ( 1 << nbits), ++ err_msg("value out of range: x=" INTPTR_FORMAT ", nbits=%d", x, nbits)); ++ } ++ ++ static void assert_signed_word_disp_range(intptr_t x, int nbits) { ++ assert( (x & 3) == 0, "not word aligned"); ++ assert_signed_range(x, nbits + 2); ++ } ++ ++ static void assert_unsigned_const(int x, int nbits) { ++ assert( juint(x) < juint(1 << nbits), "unsigned constant out of range"); ++ } ++ ++ // fields: note bits numbered from LSB = 0, ++ // fields known by inclusive bit range ++ ++ static int fmask(juint hi_bit, juint lo_bit) { ++ assert( hi_bit >= lo_bit && 0 <= lo_bit && hi_bit < 32, "bad bits"); ++ return (1 << ( hi_bit-lo_bit + 1 )) - 1; ++ } ++ ++ // inverse of u_field ++ ++ static int inv_u_field(int x, int hi_bit, int lo_bit) { ++ juint r = juint(x) >> lo_bit; ++ r &= fmask( hi_bit, lo_bit); ++ return int(r); ++ } ++ ++#ifdef ASSERT ++ static int u_field(int x, int hi_bit, int lo_bit) { ++ assert( ( x & ~fmask(hi_bit, lo_bit)) == 0, ++ "value out of range"); ++ int r = x << lo_bit; ++ assert( inv_u_field(r, hi_bit, lo_bit) == x, "just checking"); ++ return r; ++ } ++#else ++ // make sure this is inlined as it will reduce code size significantly ++ #define u_field(x, hi_bit, lo_bit) ((x) << (lo_bit)) ++#endif ++ ++ static intptr_t inv_wdisp( int x, intptr_t pos, int nbits ) { ++ int pre_sign_extend = x & (( 1 << nbits ) - 1); ++ int r = pre_sign_extend >= ( 1 << (nbits-1) ) ++ ? pre_sign_extend | ~(( 1 << nbits ) - 1) ++ : pre_sign_extend; ++ return (r << 2) + pos; ++ } ++ ++ static int wdisp( intptr_t x, intptr_t off, int nbits ) { ++ intptr_t xx = x - off; ++ assert_signed_word_disp_range(xx, nbits); ++ int r = (xx >> 2) & (( 1 << nbits ) - 1); ++ assert( inv_wdisp( r, off, nbits ) == x, "inverse not inverse"); ++ return r; ++ } ++ ++ // compute inverse of simm ++ static int inv_simm(int x, int nbits) { ++ return (int)(x << (32 - nbits)) >> (32 - nbits); ++ } ++ ++ static int inv_simm16( int x ) { return inv_simm(x, 16); } //ZHJ20110307 modified ++ ++ // signed immediate, in low bits, nbits long ++ static int simm(int x, int nbits) { ++ assert_signed_range(x, nbits); ++ return x & (( 1 << nbits ) - 1); ++ } ++ ++ // unsigned immediate, in low bits, nbits long //ZHJ20110307 added. ++ static int uimm(int x, int nbits) { ++ assert_unsigned_range(x, nbits); ++ return x & (( 1 << nbits ) - 1); ++ } ++ ++ // instruction only in sw2, including sw2f, sw4a, sw6a ++ static void sw2_only() { assert( VM_Version::sw2only(), "This instruction only works on sw2f, sw4a or sw6a"); } ++ // instruction only in sw3, including sw6b ++ static void sw3_only() { assert( VM_Version::sw3only(), "This instruction only works on sw6b"); } ++ // instruction only in sw3, including sw8A ++ static void sw4_only() { assert( VM_Version::is_sw8a(), "This instruction only works on sw8a"); } ++public: ++ using AbstractAssembler::offset; ++ ++ //sign expand with the sign bit is h ++ static int expand(int x, int h) { return -(x & (1<encoding(), 25, 21 ); }; ++ static int is_rb (Register rb) { return u_field ( rb->encoding(), 20, 16 ); }; ++ static int is_rc (Register rc) { return u_field ( rc->encoding(), 4, 0 ); }; ++ /* for the third operand of ternary operands integer insn. */ ++ static int is_r3 (Register r3) { return u_field ( r3->encoding(), 9, 5 ); }; ++ /* th th fields for dpfhr and dpfhw instructions */ ++ static int is_th (int th) { return u_field ( th, 25, 21 ); }; ++ ++ /* the plain fp register fields. */ ++ static int is_fa (FloatRegister fa) { return u_field ( fa->encoding() ,25, 21 ); }; ++ static int is_fb (FloatRegister fb) { return u_field ( fb->encoding() ,20, 16 ); }; ++ static int is_fc (FloatRegister fc) { return u_field ( fc->encoding(), 4, 0 ); }; ++ /* the plain fp register fields */ ++ static int is_f3 (FloatRegister f3) { return u_field ( f3->encoding(), 9, 5 ); }; ++ ++ /* the integer registers when they are zero. */ ++ static int is_za (void ) { return u_field ( 31 ,25, 21 ); }; ++ static int is_zb (void ) { return u_field ( 31, 20, 16 ); }; ++ static int is_zc (void ) { return u_field ( 31, 4, 0 ); }; ++ ++ /* the rb field when it needs parentheses. */ ++ static int is_prb (Register prb) { return u_field ( prb->encoding(), 20, 16 ); }; ++ ++ /* the rb field when it needs parentheses _and_ a preceding comma. */ ++ static int is_cprb (Register cprb) { return u_field ( cprb->encoding(),20, 16); }; ++ ++ /* the unsigned 8-bit literal of operate format insns. */ ++ static int is_lit (int lit) { return u_field ( lit ,20, 13 ); }; ++ ++ /* the unsigned 13-bit literal of operate format insns. */ ++ static int is_apint (int apint) { return u_field ( apint ,25, 13 ); }; ++ ++ /* the signed 16-bit displacement of memory format insns. from here ++ we can't tell what relocation should be used, so don't use a default. */ ++ static int is_mdisp (int mdisp) { return simm ( mdisp ,16 ); }; ++ ++ /* the signed "23-bit" aligned displacement of branch format insns. */ ++ static int is_bdisp (int bdisp) { return simm ( bdisp ,21 ); }; ++ ++ /* the 26-bit palcode function */ ++ static int is_palfn (int palfn) { return simm ( palfn, 26 ); }; ++ /* the optional signed "16-bit" aligned displacement of the jmp/jsr hint */ ++ static int is_jmphint (int jmphint) { return simm ( jmphint, 16); }; ++ ++ /* the optional hint to ret/jsr_coroutine */ ++ static int is_rethint (int rethint) { return simm ( rethint, 16); }; ++ /* the 12-bit displacement for the ev[46] hw_{ return u_field (ld,st} (pal1b/pal1f) insns. */ ++ static int is_ev6hwdisp (int ev6hwdisp) { return simm ( ev6hwdisp, 12 ); }; ++ ++ /* the 16-bit combined index/scoreboard mask for the ev6 ++ hw_m[ft]pr (pal19/pal1d) insns. */ ++ static int is_ev6hwindex (int ev6hwindex) { return simm ( ev6hwindex,16 ); }; ++ ++ /* the 13-bit branch hint for the ev6 hw_jmp/jsr (pal1e) insn. */ ++ static int is_ev6hwjmphint (int ev6wjmphint) { return simm ( ev6wjmphint,8); }; ++ /* sw2 simd settle instruction lit */ ++ static int is_fmalit (int fmalit) { return u_field ( fmalit ,9 ,5 ); };//v1.1 ++ /*for pal to check disp which must be plus sign and less than 0x8000,wch20080901*/ ++ static int is_lmdisp (int lmdisp ) { return u_field ( lmdisp, 14, 0 ); }; ++ static int is_rpiindex (int rpiindex) { return u_field ( rpiindex ,7, 0 ); }; ++ ++ static int is_atmdisp ( int atmdisp ) { return u_field ( atmdisp, 10, 0 ); }; ++ ++ static int is_vlog_h ( int vlog ) { return u_field ( (vlog & 0xff) >>6 , 27, 26 ); }; ++ static int is_vlog_l ( int vlog ) { return u_field ( vlog & 0x3f , 15, 10 ); }; ++ ++public: ++ ++ void flush() { ++ AbstractAssembler::flush(); ++ } ++ ++ inline void emit_long(int); // shadows AbstractAssembler::emit_long ++ inline void emit_data(int x) { emit_long(x); } ++ inline void emit_data(int, RelocationHolder const&); ++ inline void emit_data(int, relocInfo::relocType rtype); ++ ++ inline void emit_sw2_long(int); // shadows AbstractAssembler::emit_long ++ inline void emit_sw2_data(int x) { emit_sw2_long(x); } ++ inline void emit_sw2_data(int, RelocationHolder const&); ++ inline void emit_sw2_data(int, relocInfo::relocType rtype); ++ ++ ++ // Generic instructions ++ // Does 32bit or 64bit as needed for the platform. In some sense these ++ // belong in macro assembler but there is no need for both varieties to exist ++ ++public: // arithmetic instructions ++ ++ void add_simm16 (Register rt, Register rs, int imm) ++ { ++ ldi(rt, rs, imm); ++ } ++ void add_s(FloatRegister fd, FloatRegister fs, FloatRegister ft) { ++ if (FRegisterConflict) { ++ assert_different_registers(fs, F28); ++ assert_different_registers(ft, F28); ++ if (fs == ft && ft == fd){ ++ fadds(F28, fs, ft); ++ fmovs(fd, F28); ++ }else if (fs == fd){ ++ fmovs(F28, fs); ++ fadds(fd, F28, ft); ++ }else if (ft == fd){ ++ fmovs(F28, ft); ++ fadds(fd, fs, F28); ++ }else{ ++ fadds(fd, fs, ft); ++ } ++ } else ++ fadds(fd, fs, ft); ++ } ++ void sub_s(FloatRegister fd, FloatRegister fs, FloatRegister ft) { ++ if (FRegisterConflict) { ++ assert_different_registers(fs, F28); ++ assert_different_registers(ft, F28); ++ if (fs == ft && ft == fd){ ++ fsubs(F28, fs, ft); ++ fmovs(fd, F28); ++ }else if (fs == fd){ ++ fmovs(F28, fs); ++ fsubs(fd, F28, ft); ++ }else if (ft == fd){ ++ fmovs(F28, ft); ++ fsubs(fd, fs, F28); ++ }else{ ++ fsubs(fd, fs, ft); ++ } ++ } else ++ fsubs(fd, fs, ft); ++ } ++ void mul_s(FloatRegister fd, FloatRegister fs, FloatRegister ft) { ++ if (FRegisterConflict) { ++ assert_different_registers(fs, F28); ++ assert_different_registers(ft, F28); ++ if (fs == ft && ft == fd){ ++ fmuls(F28, fs, ft); ++ fmovs(fd, F28); ++ }else if (fs == fd){ ++ fmovs(F28, fs); ++ fmuls(fd, F28, ft); ++ }else if (ft == fd){ ++ fmovs(F28, ft); ++ fmuls(fd, fs, F28); ++ }else{ ++ fmuls(fd, fs, ft); ++ } ++ } else ++ fmuls(fd, fs, ft); ++ } ++ void div_s(FloatRegister fd, FloatRegister fs, FloatRegister ft) { ++ if (FRegisterConflict) { ++ assert_different_registers(fs, F28); ++ assert_different_registers(ft, F28); ++ if (fs == ft && ft == fd){ ++ fdivs(F28, fs, ft); ++ fmovs(fd, F28); ++ }else if (fs == fd){ ++ fmovs(F28, fs); ++ fdivs(fd, F28, ft); ++ }else if (ft == fd){ ++ fmovs(F28, ft); ++ fdivs(fd, fs, F28); ++ }else{ ++ fdivs(fd, fs, ft); ++ } ++ } else ++ fdivs(fd, fs, ft); ++ } ++ void idiv_sw(Register rs, Register rt, Register rd){ ++ if(rt == R0){ ++ ShouldNotReachHere(); ++ }else{ ++ FloatRegister fsrc1 = f22; ++ FloatRegister fsrc2 = f23; ++ FloatRegister fdest = f24; ++ ifmovd(fsrc1, rs); ++ ifmovd(fsrc2, rt); ++ fcvtld(fsrc1, fsrc1); ++ fcvtld(fsrc2, fsrc2); ++ fdivd(fdest, fsrc1, fsrc2); ++ fcvtdl_z(fdest, fdest); ++ fcvtlw(fsrc1, fdest); ++ fimovs(rd, fsrc1); ++ } ++ } ++ void irem_sw(Register rs, Register rt, Register rd){ ++ if(rt == R0){ ++ ShouldNotReachHere(); ++ }else{ ++ FloatRegister fsrc1 = f22; ++ FloatRegister fsrc2 = f23; ++ FloatRegister fdest = f24; ++ Register tem1 = AT; ++ Register tem2 = GP; ++ ifmovd(fsrc1, rs); ++ ifmovd(fsrc2, rt); ++ fcvtld(fsrc1, fsrc1); ++ fcvtld(fsrc2, fsrc2); ++ fdivd(fdest, fsrc1, fsrc2); ++ fcvtdl_z(fdest, fdest); ++ fimovd(tem1, fdest); ++ mulw(tem2, tem1, rt); ++ subw(rd, rs, tem2); ++ } ++ } ++ void ldiv_sw(Register rs, Register rt, Register rd){ ++ if(rt == R0){ ++ ShouldNotReachHere(); ++ }else{ ++ FloatRegister fsrc1 = f23; ++ FloatRegister fsrc2 = f24; ++ FloatRegister fdest = f25; ++ ifmovd(fsrc1, rs); ++ ifmovd(fsrc2, rt); ++ fcvtld(fsrc1, fsrc1); ++ fcvtld(fsrc2, fsrc2); ++ fdivd(fdest, fsrc1, fsrc2); ++ fcvtdl_z(fdest, fdest); ++ fimovd(rd, fdest); ++ } ++ } ++ void lrem_sw(Register rs, Register rt, Register rd){ ++ if(rt == R0){ ++ ShouldNotReachHere(); ++ }else{ ++ FloatRegister fsrc1 = f23; ++ FloatRegister fsrc2 = f24; ++ FloatRegister fdest = f25; ++ Register tem1 = AT; ++ Register tem2 = GP; ++ ifmovd(fsrc1, rs); ++ ifmovd(fsrc2, rt); ++ fcvtld(fsrc1, fsrc1); ++ fcvtld(fsrc2, fsrc2); ++ fdivd(fdest, fsrc1, fsrc2); ++ fcvtdl_z(fdest, fdest); ++ fimovd(tem1, fdest); ++ mull(tem1, rt, tem2); ++ subl(rd, rs, tem2); ++ } ++ } ++ void sqrt_s(FloatRegister fd, FloatRegister fs) { ++ if (FRegisterConflict) { ++ if(fs == fd){ ++ fmovs(F28, fs); ++ fsqrts(fd, F28); ++ } else ++ fsqrts(fd, fs); ++ } else ++ fsqrts(fd, fs); ++ } ++ void sllw_signed (Register rd, Register rt, int sa){ ++ slll(rd, rt, sa&0x1f); addw(rd, rd, 0); ++ } ++ ++ void corrected_idivw(Register ra, Register rb, Register rc) { ++ Label special_case, done; ++ Register tem1 = GP; ++ ++ if(rb == R0) { ++ ShouldNotReachHere(); ++ } else { ++ // load -1 in register ++ ldi(tem1, R0, -1); ++ ++ // check for special case, e.g. rb = -1 ++ cmpeq(tem1, rb, tem1); ++ bne(tem1, special_case); ++ ++ // handle normal case ++ divw(ra, rb, rc); ++ beq(R0, done); ++ ++ // handle special case ++ bind(special_case); ++ subw(rc, R0, ra); ++ ++ // normal and special case exit ++ bind(done); ++ } ++ } ++ ++ void corrected_idivl(Register ra, Register rb, Register rc) { ++ Label special_case, done; ++ Register tem1 = GP; ++ ++ if (rb == R0) { ++ ShouldNotReachHere(); ++ } else { ++ // load -1 in register ++ ldi(tem1, R0, -1); ++ ++ // check for special case, e.g. rb = -1l ++ cmpeq(tem1, rb, tem1); ++ bne(tem1, special_case); ++ ++ // handle normal case ++ divl(ra, rb, rc); ++ beq(R0, done); ++ ++ // handle special case ++ bind(special_case); ++ subl(rc, R0, ra); ++ ++ // normal and special case exit ++ bind(done); ++ } ++ } ++ ++public: //load&store instructions ++ ++ void load( int width, Register ra, int mdisp, Register rb ){ ++ if(width == 0) ldbu(ra, rb , mdisp); ++ else if(width == 1) ldhu(ra, rb, mdisp); ++ else if(width == 2) ldw( ra, rb , mdisp); ++ else ldl( ra,rb ,mdisp); ++ } ++ void store( int width, Register ra, int mdisp, Register rb ){ ++ if(width == 0) stb(ra, rb, mdisp); ++ else if(width == 1) sth(ra, rb, mdisp); ++ else if(width == 2) stw( ra, rb, mdisp); ++ else stl( ra, rb , mdisp); ++ } ++ void ldb_signed(Register rt, Register base, int off) { ldbu(rt, base, off); sextb (rt, rt); } ++ void ldbu(Register rt, Register base, int off); ++ void ldh_signed(Register rt, Register base, int off) { ldhu(rt, base, off); sexth(rt, rt); } ++ void ldhu( Register rt, Register rs, int off ); ++ void ldw(Register rt, Register rs, int off); ++ void ldw_unsigned(Register rt, Register base, int off) { ldw(rt, base, off); zapnot(rt, rt, 0xF); } ++ void ldl(Register rt, Register base, int off); ++ void ldl_unaligned (Register rt, Register addr/*, int off*/, Register tmp1) { ++ assert_different_registers(addr, tmp1, rt); ++ ldl_u(tmp1, addr, 0) ; ++ ldl_u(rt, addr, 7) ; ++ extll(tmp1, tmp1, addr); ++ exthl(rt, rt, addr); ++ or_ins(rt, tmp1, rt); ++ } ++ void ldb_signed(Register rt, Address src); ++ void ldbu(Register rt, Address src); ++ void ldh_signed(Register rt, Address src); ++ void ldh_unsigned(Register rt, Address src); ++ void ldw_signed(Register rt, Address src); ++ void ldw_unsigned(Register rt, Address src); ++ void ldw (Register rt, Address src); ++ void ldl (Register rt, Address src); ++ void lea (Register rt, Address src); ++ void li32(Register rt, int imm); ++ void lldw(Register rt, Address src); ++ void lldl(Register rt, Address src); ++ void stw (Register rt, Register base, int off); ++ void stl (Register rt, Register base, int off); ++ void stb (Register rt, Address dst); ++ void sth (Register rt, Address dst); ++ void stw (Register rt, Address dst); ++ void stl (Register rt, Address dst); ++ void lstw(Register rt, Address dst); ++ void lstl(Register rt, Address dst); ++ ++ ++public: //branch instructions ++ void beq (Register rs, Register rt, int off, Register cc = GP) { ++ if ( rt == R0 ) { ++ beq(rs, off); ++ } else if (rs == R0) { ++ beq(rt, off); ++ } else { ++ cmpeq(cc, rs, rt); ++ bne(cc, off); ++ } ++ } ++ void beq (Register rs, Register rt, Label& L, Register cc = GP) { ++ if ( rt == R0 ) { ++ beq(rs, offset(target(L))); ++ } else if (rs == R0) { ++ beq(rt, offset(target(L))); ++ } else { ++ cmpeq(cc, rs, rt); ++ bne(cc, offset(target(L))); ++ } ++ } ++ void beq (Register rs, Register rt, address entry, Register cc = GP) { ++ if ( rt == R0 ) { ++ beq(rs, offset(entry)); ++ } else if (rs == R0) { ++ beq(rt, offset(entry)); ++ } else { ++ cmpeq(cc, rs, rt); ++ bne(cc, offset(entry)); ++ } ++ } ++ void bne (Register rs, Register rt, int off, Register cc = GP) { ++ if ( rt == R0 ) { ++ bne(rs, off); ++ } else if (rs == R0) { ++ bne(rt, off); ++ } else { ++ cmpeq(cc, rs, rt); ++ beq(cc, off); ++ } ++ } ++ void bne (Register rs, Register rt, Label& L, Register cc = GP){ ++ if ( rt == R0 ) { ++ bne(rs, offset(target(L))); ++ } else if (rs == R0) { ++ bne(rt, offset(target(L))); ++ } else { ++ cmpeq(cc, rs, rt); ++ beq(cc, offset(target(L))); ++ } ++ } ++ void bne (Register rs, Register rt, address entry, Register cc = GP) { ++ if ( rt == R0 ) { ++ bne(rs, offset(entry)); ++ } else if (rs == R0) { ++ bne(rt, offset(entry)); ++ } else { ++ cmpeq(cc, rs, rt); ++ beq(cc, offset(entry)); ++ } ++ } ++ void blt(Register rs, Register rt, Label& L, Register cc = GP) { ++ cmpult(cc, rs, rt); ++ bne(cc, offset(target(L))); ++ } ++ void bge(Register rs, Register rt, Label& L, Register cc = GP) { ++ cmpule(cc, rt, rs); ++ bne(cc, offset(target(L))); ++ } ++ void bge(Register rs, Register rt, address entry, Register cc = GP) { ++ cmpule(cc, rt, rs); ++ bne(cc, offset(entry)); ++ } ++ void bge(Register rs, address entry) { bge (rs, offset(entry)); } ++ void bgt(Register rs, address entry) { bgt (rs, offset(entry)); } ++ void ble(Register rs, address entry) { ble (rs, offset(entry)); } ++ void blt(Register rs, address entry) { blt (rs, offset(entry)); } ++ void beq( Register a, Label& L ) { beq( a, offset(target(L))); } ++ void beq_a (Register a, address entry) { beq(a, offset(entry)); } ++ void bne( Register a, Label& L ) { bne( a, offset(target(L))); } ++ void blt( Register a, Label& L ) { blt( a, offset(target(L))); } ++ void ble( Register a, Label& L ) { ble( a, offset(target(L))); } ++ void bgt( Register a, Label& L ) { bgt( a, offset(target(L))); } ++ void bge( Register a, Label& L ) { bge( a, offset(target(L))); } ++ ++ ++public: //float arithmrtic instructions ++ ++ void fabs(FloatRegister fd, FloatRegister fs) { fcpys(fd, F31, fs); } ++ void fmovs(FloatRegister fd, FloatRegister fs); ++ void fmovd(FloatRegister fd, FloatRegister fs); ++ void fneg (FloatRegister fd, FloatRegister fs){ fcpysn(fd, fs, fs); } ++ ++ void add_d(FloatRegister fd, FloatRegister fs, FloatRegister ft) { ++ if (FRegisterConflict) { ++ assert_different_registers(fs, F28); ++ assert_different_registers(ft, F28); ++ if (fs == ft && ft == fd){ ++ faddd(F28, fs, ft); ++ fmovd(fd, F28); ++ }else if (fs == fd){ ++ fmovd(F28, fs); ++ faddd(fd, F28, ft); ++ }else if (ft == fd){ ++ fmovd(F28, ft); ++ faddd(fd, fs, F28); ++ }else{ ++ faddd(fd, fs, ft); ++ } ++ } else ++ faddd(fd, fs, ft); ++ } ++ void sub_d(FloatRegister fd, FloatRegister fs, FloatRegister ft) { ++ if (FRegisterConflict) { ++ assert_different_registers(fs, F28); ++ assert_different_registers(ft, F28); ++ if (fs == ft && ft == fd){ ++ fsubd(F28, fs, ft); ++ fmovd(fd, F28); ++ }else if (fs == fd){ ++ fmovd(F28, fs); ++ fsubd(fd, F28, ft); ++ }else if (ft == fd){ ++ fmovd(F28, ft); ++ fsubd(fd, fs, F28); ++ }else{ ++ fsubd(fd, fs, ft); ++ } ++ } else ++ fsubd(fd, fs, ft); ++ } ++ void mul_d(FloatRegister fd, FloatRegister fs, FloatRegister ft) { ++ if (FRegisterConflict) { ++ assert_different_registers(fs, F28); ++ assert_different_registers(ft, F28); ++ if (fs == ft && ft == fd){ ++ fmuld(F28, fs, ft); ++ fmovd(fd, F28); ++ }else if (fs == fd){ ++ fmovd(F28, fs); ++ fmuld(fd, F28, ft); ++ }else if (ft == fd){ ++ fmovd(F28, ft); ++ fmuld(fd, fs, F28); ++ }else{ ++ fmuld(fd, fs, ft); ++ } ++ } else ++ fmuld(fd, fs, ft); ++ } ++ void div_d(FloatRegister fd, FloatRegister fs, FloatRegister ft) { ++ if (FRegisterConflict) { ++ assert_different_registers(fs, F28); ++ assert_different_registers(ft, F28); ++ if (fs == ft && ft == fd){ ++ fdivd(F28, fs, ft); ++ fmovd(fd, F28); ++ }else if (fs == fd){ ++ fmovd(F28, fs); ++ fdivd(fd, F28, ft); ++ }else if (ft == fd){ ++ fmovd(F28, ft); ++ fdivd(fd, fs, F28); ++ }else{ ++ fdivd(fd, fs, ft); ++ } ++ } else ++ fdivd(fd, fs, ft); ++ } ++ void sqrt_d(FloatRegister fd, FloatRegister fs) { ++ if (FRegisterConflict) { ++ if (fs == fd) { ++ fmovd(F28, fs); ++ fsqrtd(fd, F28); ++ } else ++ fsqrtd(fd, fs); ++ } else ++ fsqrtd(fd, fs); ++ } ++ ++ ++public: //float load&store instructions ++ void fldd(FloatRegister ft, Register rs, int off); ++ void flds(FloatRegister ft, Register rs, int off); ++ void fldd(FloatRegister ft, Address src); ++ void flds(FloatRegister ft, Address src); ++ ++ void fstd(FloatRegister ft, Register base, int off); ++ void fstd(FloatRegister ft, Address dst); ++ void fsts(FloatRegister ft, Register base, int off); ++ void fsts(FloatRegister ft, Address dst); ++ ++ ++public: //float compare instructions ++ // return true if fs lt ft, or either of fs & ft is NaN ++ void fcmplt_un (FloatRegister fd, FloatRegister fs, FloatRegister ft) { ++ fcmpun(fd, fs, ft); ++ fbne(fd, 1); ++ fcmplt(fd, fs, ft); ++ } ++ // return true if fs le ft, or either of fs & ft is NaN ++ void fcmple_un (FloatRegister fd, FloatRegister fs, FloatRegister ft) { ++ fcmpun(fd, fs, ft); ++ fbne(fd, 1); ++ fcmple(fd, fs, ft); ++ } ++ ++ ++public: //float branch instructions ++ void fbne(FloatRegister rs, Label& L) { fbne(rs, offset(target(L))); } ++ void fbeq(FloatRegister rs, Label& L) { fbeq(rs, offset(target(L))); } ++ void fblt(FloatRegister a, Label& L) { fblt( a, offset(target(L))); } ++ void fble(FloatRegister a, Label& L) { fble( a, offset(target(L))); } ++ void fbgt(FloatRegister a, Label& L) { fbgt( a, offset(target(L))); } ++ void fbge(FloatRegister a, Label& L) { fbge( a, offset(target(L))); } ++ ++ ++public: //fcvt instructions ++ void trunc_l_s(FloatRegister fd, FloatRegister fs) { ++ assert_different_registers(fs, F28); ++ assert_different_registers(fd, F28); ++ fcvtsd(F28, fd); ++ fcvtdl_z(fd, F28); ++ } ++ void trunc_l_d(FloatRegister fd, FloatRegister fs) { ++ if (FRegisterConflict) { ++ assert_different_registers(fs, F28); ++ assert_different_registers(fd, F28); ++ if(fs == fd){ ++ fmovd(F28, fs); ++ fcvtdl_z(fd, F28); ++ } else ++ fcvtdl_z(fd, fs); ++ } else ++ fcvtdl_z(fd, fs); ++ } ++ void fcvtS2D(FloatRegister fd, FloatRegister fs) { ++ if (FRegisterConflict) { ++ assert_different_registers(fs, F28); ++ assert_different_registers(fd, F28); ++ if (fs == fd){ ++ fmovd(F28, fs); ++ fcvtds(fd, F28); ++ } else ++ fcvtds(fd, fs); ++ } else ++ fcvtds(fd, fs); ++ } ++ void fcvtS2W(FloatRegister fd, FloatRegister fs) { ++ assert_different_registers(fs, F28); ++ assert_different_registers(fd, F28); ++ fcvtwl(F28, fs); ++ fcvtls(fd, F28); ++ } ++ void fcvtS2L(FloatRegister fd, FloatRegister fs) { ++ if (FRegisterConflict) { ++ assert_different_registers(fs, F28); ++ assert_different_registers(fd, F28); ++ if (fs == fd){ ++ fmovd(F28, fs); ++ fcvtls(fd, F28); ++ }else{ ++ fcvtls(fd, fs); ++ } ++ } else ++ fcvtls(fd, fs); ++ } ++ void fcvtD2S(FloatRegister fd, FloatRegister fs) { ++ if (FRegisterConflict) { ++ assert_different_registers(fs, F28); ++ assert_different_registers(fd, F28); ++ if (fs == fd){ ++ fmovs(F28, fs); ++ fcvtsd(fd, F28); ++ }else{ ++ fcvtsd(fd, fs); ++ } ++ } else ++ fcvtsd(fd, fs); ++ } ++ void fcvtD2W(FloatRegister fd, FloatRegister fs) { ++ assert_different_registers(fs, F28); ++ assert_different_registers(fd, F28); ++ fcvtwl(F28, fs); ++ fcvtld(fd, F28); ++ } ++ void fcvtD2L(FloatRegister fd, FloatRegister fs) { ++ if (FRegisterConflict) { ++ assert_different_registers(fs, F28); ++ assert_different_registers(fd, F28); ++ if (fs == fd){ ++ fmovd(F28, fs); ++ fcvtld(fd, F28); ++ }else{ ++ fcvtld(fd, fs); ++ } ++ } else ++ fcvtld(fd, fs); ++ } ++ ++ void ret() { ret(R0, RA, 0); } ++ //void sync () { memb(); } ++ void syscall(int code) { sys_call(code); } ++ void brk (int code) { sys_call(0x80); } ++ ++ void nop() { emit_sw2_long( op_ldi | is_ra(R0) ); } ++ ++ void int3(); ++ static void print_instruction(int); ++ int patched_branch(int dest_pos, int inst, int inst_pos); ++ int branch_destination(int inst, int pos); ++ ++// SW64 extension ++ ++ public: ++ // SW64 Generic instructions ++ inline void sys_call_b( int palfn ); ++ inline void sys_call ( int palfn ); ++ //jump ++ inline void call ( Register ra, Register rb, int jmphint ); ++ inline void ret ( Register ra, Register rb, int rethint ); ++ inline void jmp ( Register ra, Register rb, int jmphint ); ++ //arithmetic ++ inline void addw ( Register rd, Register rs, Register rt ); ++ inline void addw ( Register rd, Register rs, int lit ); ++ inline void subw ( Register rd, Register rs, Register rt ); ++ inline void subw ( Register rd, Register rs, int lit ); ++ inline void s4addw ( Register rd, Register rs, Register rt ); ++ inline void s4addw ( Register rd, Register rs, int lit ); ++ inline void s4subw ( Register rd, Register rs, Register rt ); ++ inline void s4subw ( Register rd, Register rs, int lit ); ++ inline void s8addw ( Register rd, Register rs, Register rt ); ++ inline void s8addw ( Register rd, Register rs, int lit ); ++ inline void s8subw ( Register rd, Register rs, Register rt ); ++ inline void s8subw ( Register rd, Register rs, int lit ); ++ inline void addl ( Register rd, Register rs, Register rt ); ++ inline void addl ( Register rd, Register rs, int lit ); ++ inline void subl ( Register rd, Register rs, Register rt ); ++ inline void subl ( Register rd, Register rs, int lit ); ++ inline void s4addl ( Register rd, Register rs, Register rt ); ++ inline void s4addl ( Register rd, Register rs, int lit ); ++ inline void s4subl ( Register rd, Register rs, Register rt ); ++ inline void s4subl ( Register rd, Register rs, int lit ); ++ inline void s8addl ( Register rd, Register rs, Register rt ); ++ inline void s8addl ( Register rd, Register rs, int lit ); ++ inline void s8subl ( Register rd, Register rs, Register rt ); ++ inline void s8subl ( Register rd, Register rs, int lit ); ++ inline void mulw ( Register rd, Register rs, Register rt ); ++ inline void mulw ( Register rd, Register rs, int lit ); ++ inline void and_reg ( Register rd, Register rs, Register rt ); ++ inline void and_imm8 ( Register rd, Register rs, int lit ); ++ inline void bic ( Register rd, Register rs, Register rt ); ++ inline void bic ( Register rd, Register rs, int lit ); ++ inline void andnot ( Register rd, Register rs, Register rt ) { ++ bic( rd, rs, rt ); ++ } ++ inline void andnot ( Register rd, Register rs, int lit ) { ++ bic( rd, rs, lit ); ++ } ++ inline void bis ( Register rd, Register rs, Register rt ); ++ inline void bis ( Register rd, Register rs, int lit ); ++ inline void or_ins ( Register rd, Register rs, Register rt ) { ++ bis( rd, rs, rt ); ++ } ++ inline void or_ins ( Register rd, Register rs, int lit ) { ++ bis( rd, rs, lit ); ++ } ++ inline void ornot ( Register rd, Register rs, Register rt ); ++ inline void ornot ( Register rd, Register rs, int lit ); ++ inline void xor_ins ( Register rd, Register rs, Register rt ); ++ inline void xor_ins ( Register rd, Register rs, int lit ); ++ inline void eqv ( Register rd, Register rs, Register rt ); ++ inline void eqv ( Register rd, Register rs, int lit ); ++ inline void inslb ( Register rd, Register rs, Register rt ); ++ inline void inslb ( Register rd, Register rs, int lit ); ++ inline void inslh ( Register rd, Register rs, Register rt ); ++ inline void inslh ( Register rd, Register rs, int lit ); ++ inline void inslw ( Register rd, Register rs, Register rt ); ++ inline void inslw ( Register rd, Register rs, int lit ); ++ inline void insll ( Register rd, Register rs, Register rt ); ++ inline void insll ( Register rd, Register rs, int lit ); ++ inline void inshb ( Register rd, Register rs, Register rt ); ++ inline void inshb ( Register rd, Register rs, int lit ); ++ inline void inshh ( Register rd, Register rs, Register rt ); ++ inline void inshh ( Register rd, Register rs, int lit ); ++ inline void inshw ( Register rd, Register rs, Register rt ); ++ inline void inshw ( Register rd, Register rs, int lit ); ++ inline void inshl ( Register rd, Register rs, Register rt ); ++ inline void inshl ( Register rd, Register rs, int lit ); ++ inline void slll ( Register rd, Register rs, Register rt ); ++ inline void slll ( Register rt, Register rs, int lit ); ++ inline void srll ( Register rd, Register rt, Register rs ); ++ inline void srll ( Register rt, Register rs, int lit ); ++ inline void sral ( Register rd, Register rt, Register rs ); ++ inline void sral ( Register rt, Register rs, int lit ); ++ inline void extlb ( Register rd, Register rs, Register rt ); ++ inline void extlb ( Register rd, Register rs, int lit ); ++ inline void extlh ( Register rd, Register rs, Register rt ); ++ inline void extlh ( Register rd, Register rs, int lit ); ++ inline void extlw ( Register rd, Register rt, Register rs ); ++ inline void extlw ( Register rd, Register rs, int lit ); ++ inline void extll ( Register rd, Register rs, Register rt ); ++ inline void extll ( Register rd, Register rs, int lit ); ++ inline void exthb ( Register rd, Register rs, Register rt ); ++ inline void exthb ( Register rd, Register rs, int lit ); ++ inline void exthh ( Register rd, Register rs, Register rt ); ++ inline void exthh ( Register rd, Register rs, int lit ); ++ inline void exthw ( Register rd, Register rs, Register rt ); ++ inline void exthw ( Register rd, Register rs, int lit ); ++ inline void exthl ( Register rd, Register rs, Register rt ); ++ inline void exthl ( Register rd, Register rs, int lit ); ++ inline void ctpop ( Register rc, Register rb ); ++ inline void ctlz ( Register rc, Register rb ); ++ inline void cttz ( Register rc, Register rb ); ++ inline void masklb ( Register rd, Register rs, Register rt ); ++ inline void masklb ( Register rd, Register rs, int lit ); ++ inline void masklh ( Register rd, Register rs, Register rt ); ++ inline void masklh ( Register rd, Register rs, int lit ); ++ inline void masklw ( Register rd, Register rs, Register rt ); ++ inline void masklw ( Register rd, Register rs, int lit ); ++ inline void maskll ( Register rd, Register rs, Register rt ); ++ inline void maskll ( Register rd, Register rs, int lit ); ++ inline void maskhb ( Register rd, Register rs, Register rt ); ++ inline void maskhb ( Register rd, Register rs, int lit ); ++ inline void maskhh ( Register rd, Register rs, Register rt ); ++ inline void maskhh ( Register rd, Register rs, int lit ); ++ inline void maskhw ( Register rd, Register rs, Register rt ); ++ inline void maskhw ( Register rd, Register rs, int lit ); ++ inline void maskhl ( Register rd, Register rs, Register rt ); ++ inline void maskhl ( Register rd, Register rs, int lit ); ++ inline void zap ( Register rd, Register rs, Register rt ); ++ inline void zap ( Register rd, Register rs, int lit ); ++ inline void zapnot ( Register rd, Register rs, Register rt ); ++ inline void zapnot ( Register rd, Register rs, int lit ); ++ inline void sextb ( Register rc, Register rb ); ++ inline void sextb ( Register rc, int lit ); ++ inline void sexth ( Register rc, Register rb ); ++ inline void sexth ( Register rc, int lit ); ++ //load&store ++ inline void ldl_u ( Register ra, Register rb, int mdisp ); ++ inline void stb ( Register ra, Register rb, int mdisp ); ++ inline void sth ( Register ra, Register rb, int mdisp ); ++ inline void stl_u ( Register ra, Register rb, int mdisp ); ++ inline void ldi ( Register ra, Register rb, int mdisp ); ++ inline void ldih ( Register ra, Register rb, int mdisp ); ++ inline void ldw_nc ( Register rt, Register rs, int atmdisp ); ++ inline void ldl_nc ( Register rt, Register rs, int atmdisp ); ++ inline void ldd_nc ( Register rt, Register rs, int atmdisp ); ++ inline void stw_nc ( Register rt, Register rs, int atmdisp ); ++ inline void stl_nc ( Register rt, Register rs, int atmdisp ); ++ inline void std_nc ( Register rt, Register rs, int atmdisp ); ++ inline void lldw ( Register rt, Register rs, int atmdisp );//lock ++ inline void lldl ( Register rt, Register rs, int atmdisp ); ++ inline void lstw ( Register ra, Register rb, int atmdisp ); ++ inline void lstl ( Register ra, Register rb, int atmdisp ); ++ inline void rd_f ( Register ra ); //SW2F ++ inline void wr_f ( Register ra ); //SW2F ++ inline void ldw_inc ( Register rt, Register rs, int atmdisp );//atom ++ inline void ldl_inc ( Register rt, Register rs, int atmdisp ); ++ inline void ldw_dec ( Register rt, Register rs, int atmdisp ); ++ inline void ldl_dec ( Register rt, Register rs, int atmdisp ); ++ inline void ldw_set ( Register rt, Register rs, int atmdisp ); ++ inline void ldl_set ( Register rt, Register rs, int atmdisp ); ++ //compare ++ inline void cmpeq ( Register rd, Register rs, Register rt ); ++ inline void cmpeq ( Register rd, Register rs, int lit ); ++ inline void cmplt ( Register rd, Register rs, Register rt ); ++ inline void cmplt ( Register rd, Register rs, int lit ); ++ inline void cmple ( Register rd, Register rs, Register rt ); ++ inline void cmple ( Register rd, Register rs, int lit ); ++ inline void cmpult ( Register rd, Register rs, Register rt ); ++ inline void cmpult ( Register rd, Register rs, int lit ); ++ inline void cmpule ( Register rd, Register rs, Register rt ); ++ inline void cmpule ( Register rd, Register rs, int lit ); ++ inline void cmpgeb ( Register rc, Register ra, Register rb ); ++ inline void cmpgeb ( Register rc, Register ra, int lit ); ++ //branch ++ inline void br ( Register ra, int bdisp ); ++ inline void bsr ( Register ra, int bdisp ); ++ inline void beq ( Register ra, int bdisp ); ++ inline void bne ( Register ra, int bdisp ); ++ inline void blt ( Register ra, int bdisp ); ++ inline void ble ( Register ra, int bdisp ); ++ inline void bgt ( Register ra, int bdisp ); ++ inline void bge ( Register ra, int bdisp ); ++ inline void blbc ( Register ra, int bdisp ); ++ inline void blbs ( Register ra, int bdisp ); ++ //select ++ inline void seleq ( Register ra, Register rb,Register r3, Register rc ); ++ inline void seleq ( Register ra, int lit, Register r3, Register rc ); ++ inline void selge ( Register ra, Register rb,Register r3, Register rc ); ++ inline void selge ( Register ra, int lit, Register r3, Register rc ); ++ inline void selgt ( Register ra, Register rb,Register r3, Register rc ); ++ inline void selgt ( Register ra, int lit, Register r3, Register rc ); ++ inline void selle ( Register ra, Register rb,Register r3, Register rc ); ++ inline void selle ( Register ra, int lit, Register r3, Register rc ); ++ inline void sellt ( Register ra, Register rb,Register r3, Register rc ); ++ inline void sellt ( Register ra, int lit, Register r3, Register rc ); ++ inline void selne ( Register ra, Register rb,Register r3, Register rc ); ++ inline void selne ( Register ra, int lit, Register r3, Register rc ); ++ inline void sellbc ( Register ra, Register rb,Register r3, Register rc ); ++ inline void sellbc ( Register ra, int lit, Register r3, Register rc ); ++ inline void sellbs ( Register ra, Register rb,Register r3, Register rc ); ++ inline void sellbs ( Register ra, int lit, Register r3, Register rc ); ++ //mov ++ inline void fimovs ( Register rc, FloatRegister fa); // For sw4a SQData ++ inline void fimovd ( Register rc, FloatRegister fa); // For sw4a SQData ++ ++ //float ++ //arithmetic instrctions ++ inline void fadds ( FloatRegister fd, FloatRegister fs, FloatRegister ft ); ++ inline void faddd ( FloatRegister fd, FloatRegister fs, FloatRegister ft ); ++ inline void fsubs ( FloatRegister fd, FloatRegister fs, FloatRegister ft ); ++ inline void fsubd ( FloatRegister fd, FloatRegister fs, FloatRegister ft ); ++ inline void fmuls ( FloatRegister fd, FloatRegister fs, FloatRegister ft ); ++ inline void fmuld ( FloatRegister fd, FloatRegister fs, FloatRegister ft ); ++ inline void fdivs ( FloatRegister fd, FloatRegister fs, FloatRegister ft ); ++ inline void fdivd ( FloatRegister fd, FloatRegister fs, FloatRegister ft ); ++ inline void fsqrts ( FloatRegister fc, FloatRegister fb ); ++ inline void fsqrtd ( FloatRegister fc, FloatRegister fb ); ++ inline void fmas ( FloatRegister fa, FloatRegister fb, FloatRegister f3, FloatRegister fc ); ++ inline void fmad ( FloatRegister fa, FloatRegister fb, FloatRegister f3, FloatRegister fc ); ++ inline void fmss ( FloatRegister fa, FloatRegister fb, FloatRegister f3, FloatRegister fc ); ++ inline void fmsd ( FloatRegister fa, FloatRegister fb, FloatRegister f3, FloatRegister fc ); ++ inline void fnmas ( FloatRegister fa, FloatRegister fb, FloatRegister f3, FloatRegister fc ); ++ inline void fnmad ( FloatRegister fa, FloatRegister fb, FloatRegister f3, FloatRegister fc ); ++ inline void fnmss ( FloatRegister fa, FloatRegister fb, FloatRegister f3, FloatRegister fc ); ++ inline void fnmsd ( FloatRegister fa, FloatRegister fb, FloatRegister f3, FloatRegister fc ); ++ //compare ++ inline void fcmpeq ( FloatRegister fc, FloatRegister fa, FloatRegister fb ); ++ inline void fcmple ( FloatRegister fc, FloatRegister fa, FloatRegister fb ); ++ inline void fcmplt ( FloatRegister fc, FloatRegister fa, FloatRegister fb ); ++ inline void fcmpun ( FloatRegister fc, FloatRegister fa, FloatRegister fb ); ++ //branch ++ inline void fbeq ( FloatRegister fa, int bdisp ); ++ inline void fbne ( FloatRegister fa, int bdisp ); ++ inline void fblt ( FloatRegister fa, int bdisp ); ++ inline void fble ( FloatRegister fa, int bdisp ); ++ inline void fbgt ( FloatRegister fa, int bdisp ); ++ inline void fbge ( FloatRegister fa, int bdisp ); ++ //select ++ inline void fseleq ( FloatRegister fa, FloatRegister fb, FloatRegister f3, FloatRegister fc ); ++ inline void fselne ( FloatRegister fa, FloatRegister fb, FloatRegister f3, FloatRegister fc ); ++ inline void fsellt ( FloatRegister fa, FloatRegister fb, FloatRegister f3, FloatRegister fc ); ++ inline void fselle ( FloatRegister fa, FloatRegister fb, FloatRegister f3, FloatRegister fc ); ++ inline void fselgt ( FloatRegister fa, FloatRegister fb, FloatRegister f3, FloatRegister fc ); ++ inline void fselge ( FloatRegister fa, FloatRegister fb, FloatRegister f3, FloatRegister fc ); ++ //mov ++ inline void fcpys ( FloatRegister fc, FloatRegister fa, FloatRegister fb ); ++ inline void fcpyse ( FloatRegister fc, FloatRegister fa, FloatRegister fb ); ++ inline void fcpysn ( FloatRegister fc, FloatRegister fa, FloatRegister fb ); ++ inline void ifmovs ( FloatRegister fc, Register ra ); // For sw4a SQData ++ inline void ifmovd ( FloatRegister fc, Register ra ); // For sw4a SQData ++ //cmov ++ inline void cmovdl ( Register rc, FloatRegister fb ); ++ inline void cmovdl_g ( Register rc, FloatRegister fb ); ++ inline void cmovdl_p ( Register rc, FloatRegister fb ); ++ inline void cmovdl_z ( Register rc, FloatRegister fb ); ++ inline void cmovdl_n ( Register rc, FloatRegister fb ); ++ ++ inline void cmovdlu ( Register rc, FloatRegister fb ); ++ inline void cmovdlu_g ( Register rc, FloatRegister fb ); ++ inline void cmovdlu_p ( Register rc, FloatRegister fb ); ++ inline void cmovdlu_z ( Register rc, FloatRegister fb ); ++ inline void cmovdlu_n ( Register rc, FloatRegister fb ); ++ ++ inline void cmovdw ( Register rc, FloatRegister fb ); ++ inline void cmovdw_g ( Register rc, FloatRegister fb ); ++ inline void cmovdw_p ( Register rc, FloatRegister fb ); ++ inline void cmovdw_z ( Register rc, FloatRegister fb ); ++ inline void cmovdw_n ( Register rc, FloatRegister fb ); ++ ++ inline void cmovdwu ( Register rc, FloatRegister fb ); ++ inline void cmovdwu_g ( Register rc, FloatRegister fb ); ++ inline void cmovdwu_p ( Register rc, FloatRegister fb ); ++ inline void cmovdwu_z ( Register rc, FloatRegister fb ); ++ inline void cmovdwu_n ( Register rc, FloatRegister fb ); ++ ++ inline void cmovls ( FloatRegister fc, Register rb ); ++ inline void cmovld ( FloatRegister fc, Register rb ); ++ inline void cmovuls ( FloatRegister fc, Register rb ); ++ inline void cmovuld ( FloatRegister fc, Register rb ); ++ inline void cmovws ( FloatRegister fc, Register rb ); ++ inline void cmovwd ( FloatRegister fc, Register rb ); ++ inline void cmovuws ( FloatRegister fc, Register rb ); ++ inline void cmovuwd ( FloatRegister fc, Register rb ); ++ //fcvt ++ inline void fcvtsd ( FloatRegister fc, FloatRegister fb ); ++ inline void fcvtds ( FloatRegister fc, FloatRegister fb ); ++ inline void fcvtdl_g ( FloatRegister fc, FloatRegister fb ); ++ inline void fcvtdl_p ( FloatRegister fc, FloatRegister fb ); ++ inline void fcvtdl_z ( FloatRegister fc, FloatRegister fb ); ++ inline void fcvtdl_n ( FloatRegister fc, FloatRegister fb ); ++ inline void fcvtdl ( FloatRegister fc, FloatRegister fb ); ++ inline void fcvtwl ( FloatRegister fc, FloatRegister fb ); ++ inline void fcvtlw ( FloatRegister fc, FloatRegister fb ); ++ inline void fcvtls ( FloatRegister fc, FloatRegister fb ); ++ inline void fcvtld ( FloatRegister fc, FloatRegister fb ); ++ //set FPCR ++ inline void rfpcr ( FloatRegister fa); ++ inline void wfpcr ( FloatRegister fa); ++ inline void setfpec0 (); ++ inline void setfpec1 (); ++ inline void setfpec2 (); ++ inline void setfpec3 (); ++ //SIMD ++ inline void ldwe ( FloatRegister fa, Register rb, int mdisp ); ++ inline void ldse ( FloatRegister fa, Register rb, int mdisp ); ++ inline void ldde ( FloatRegister fa, Register rb, int mdisp ); ++ inline void vlds ( FloatRegister fa, Register rb, int mdisp ); ++ inline void vldd ( FloatRegister fa, Register rb, int mdisp ); ++ inline void vsts ( FloatRegister fa, Register rb, int mdisp ); ++ inline void vstd ( FloatRegister fa, Register rb, int mdisp ); ++ inline void vaddw ( FloatRegister fc, FloatRegister fa, FloatRegister fb ); ++ inline void vaddw ( FloatRegister fc, FloatRegister fa, int lit ); ++ inline void vsubw ( FloatRegister fc, FloatRegister fa, FloatRegister fb ); ++ inline void vsubw ( FloatRegister fc, FloatRegister fa, int lit ); ++ inline void vcmpgew ( FloatRegister fc, FloatRegister fa, FloatRegister fb ); ++ inline void vcmpgew ( FloatRegister fc, FloatRegister fa, int lit ); ++ inline void vcmpeqw ( FloatRegister fc, FloatRegister fa, FloatRegister fb ); ++ inline void vcmpeqw ( FloatRegister fc, FloatRegister fa, int lit ); ++ inline void vcmplew ( FloatRegister fc, FloatRegister fa, FloatRegister fb ); ++ inline void vcmplew ( FloatRegister fc, FloatRegister fa, int lit ); ++ inline void vcmpltw ( FloatRegister fc, FloatRegister fa, FloatRegister fb ); ++ inline void vcmpltw ( FloatRegister fc, FloatRegister fa, int lit ); ++ inline void vcmpulew ( FloatRegister fc, FloatRegister fa, FloatRegister fb ); ++ inline void vcmpulew ( FloatRegister fc, FloatRegister fa, int lit ); ++ inline void vcmpultw ( FloatRegister fc, FloatRegister fa, FloatRegister fb ); ++ inline void vcmpultw ( FloatRegister fc, FloatRegister fa, int lit ); ++ inline void vsllw ( FloatRegister fc, FloatRegister fa, FloatRegister fb ); ++ inline void vsllw ( FloatRegister fc, FloatRegister fa, int lit ); ++ inline void vsrlw ( FloatRegister fc, FloatRegister fa, FloatRegister fb ); ++ inline void vsrlw ( FloatRegister fc, FloatRegister fa, int lit ); ++ inline void vsraw ( FloatRegister fc, FloatRegister fa, FloatRegister fb ); ++ inline void vsraw ( FloatRegister fc, FloatRegister fa, int lit ); ++ inline void vrolw ( FloatRegister fc, FloatRegister fa, FloatRegister fb ); ++ inline void vrolw ( FloatRegister fc, FloatRegister fa, int lit ); ++ inline void sllow ( FloatRegister fc, FloatRegister fa, FloatRegister fb ); ++ inline void sllow ( FloatRegister fc, FloatRegister fa, int lit ); ++ inline void srlow ( FloatRegister fc, FloatRegister fa, FloatRegister fb ); ++ inline void srlow ( FloatRegister fc, FloatRegister fa, int lit ); ++ inline void vaddl ( FloatRegister fc, FloatRegister fa, FloatRegister fb ); ++ inline void vaddl ( FloatRegister fc, FloatRegister fa, int lit ); ++ inline void vsubl ( FloatRegister fc, FloatRegister fa, FloatRegister fb ); ++ inline void vsubl ( FloatRegister fc, FloatRegister fa, int lit ); ++ inline void ctpopow ( FloatRegister fc, FloatRegister fa ); ++ inline void ctlzow ( FloatRegister fc, FloatRegister fa ); ++ ++ inline void vucaddw ( FloatRegister fc, FloatRegister fa, FloatRegister fb ); ++ inline void vucaddw ( FloatRegister fc, FloatRegister fa, int lit ); ++ inline void vucsubw ( FloatRegister fc, FloatRegister fa, FloatRegister fb ); ++ inline void vucsubw ( FloatRegister fc, FloatRegister fa, int lit ); ++ inline void vucaddh ( FloatRegister fc, FloatRegister fa, FloatRegister fb ); ++ inline void vucaddh ( FloatRegister fc, FloatRegister fa, int lit ); ++ inline void vucsubh ( FloatRegister fc, FloatRegister fa, FloatRegister fb ); ++ inline void vucsubh ( FloatRegister fc, FloatRegister fa, int lit ); ++ inline void vucaddb ( FloatRegister fc, FloatRegister fa, FloatRegister fb ); ++ inline void vucaddb ( FloatRegister fc, FloatRegister fa, int lit ); ++ inline void vucsubb ( FloatRegister fc, FloatRegister fa, FloatRegister fb ); ++ inline void vucsubb ( FloatRegister fc, FloatRegister fa, int lit ); ++ ++ inline void vseleqw ( FloatRegister fa, FloatRegister fb, FloatRegister f3, FloatRegister fc ); ++ inline void vseleqw ( FloatRegister fa, FloatRegister fb, int fmalit, FloatRegister fc ); ++ inline void vsellbcw ( FloatRegister fa, FloatRegister fb, FloatRegister f3, FloatRegister fc ); ++ inline void vsellbcw ( FloatRegister fa, FloatRegister fb, int fmalit, FloatRegister fc ); ++ inline void vselltw ( FloatRegister fa, FloatRegister fb, FloatRegister f3, FloatRegister fc ); ++ inline void vselltw ( FloatRegister fa, FloatRegister fb, int fmalit, FloatRegister fc ); ++ inline void vsellew ( FloatRegister fa, FloatRegister fb, FloatRegister f3, FloatRegister fc ); ++ inline void vsellew ( FloatRegister fa, FloatRegister fb, int fmalit, FloatRegister fc ); ++ ++ inline void vadds ( FloatRegister fd, FloatRegister fs, FloatRegister ft ); ++ inline void vaddd ( FloatRegister fd, FloatRegister fs, FloatRegister ft ); ++ inline void vsubs ( FloatRegister fd, FloatRegister fs, FloatRegister ft ); ++ inline void vsubd ( FloatRegister fd, FloatRegister fs, FloatRegister ft ); ++ inline void vmuls ( FloatRegister fd, FloatRegister fs, FloatRegister ft ); ++ inline void vmuld ( FloatRegister fd, FloatRegister fs, FloatRegister ft ); ++ inline void vdivs ( FloatRegister fd, FloatRegister fs, FloatRegister ft ); ++ inline void vdivd ( FloatRegister fd, FloatRegister fs, FloatRegister ft ); ++ inline void vsqrts ( FloatRegister fc, FloatRegister fb ); ++ inline void vsqrtd ( FloatRegister fc, FloatRegister fb ); ++ inline void vfcmpeq ( FloatRegister fc, FloatRegister fa, FloatRegister fb ); ++ inline void vfcmple ( FloatRegister fc, FloatRegister fa, FloatRegister fb ); ++ inline void vfcmplt ( FloatRegister fc, FloatRegister fa, FloatRegister fb ); ++ inline void vfcmpun ( FloatRegister fc, FloatRegister fa, FloatRegister fb ); ++ inline void vcpys ( FloatRegister fc, FloatRegister fa, FloatRegister fb ); ++ inline void vfmov ( FloatRegister fc, FloatRegister fa ); ++ inline void vcpyse ( FloatRegister fc, FloatRegister fa, FloatRegister fb ); ++ inline void vcpysn ( FloatRegister fc, FloatRegister fa, FloatRegister fb ); ++ ++ inline void vmas ( FloatRegister fa, FloatRegister fb, FloatRegister f3, FloatRegister fc ); ++ inline void vmad ( FloatRegister fa, FloatRegister fb, FloatRegister f3, FloatRegister fc ); ++ inline void vmss ( FloatRegister fa, FloatRegister fb, FloatRegister f3, FloatRegister fc ); ++ inline void vmsd ( FloatRegister fa, FloatRegister fb, FloatRegister f3, FloatRegister fc ); ++ inline void vnmas ( FloatRegister fa, FloatRegister fb, FloatRegister f3, FloatRegister fc ); ++ inline void vnmad ( FloatRegister fa, FloatRegister fb, FloatRegister f3, FloatRegister fc ); ++ inline void vnmss ( FloatRegister fa, FloatRegister fb, FloatRegister f3, FloatRegister fc ); ++ inline void vnmsd ( FloatRegister fa, FloatRegister fb, FloatRegister f3, FloatRegister fc ); ++ ++ inline void vfseleq ( FloatRegister fa, FloatRegister fb, FloatRegister f3, FloatRegister fc ); ++ inline void vfsellt ( FloatRegister fa, FloatRegister fb, FloatRegister f3, FloatRegister fc ); ++ inline void vfselle ( FloatRegister fa, FloatRegister fb, FloatRegister f3, FloatRegister fc ); ++ ++ inline void vinsw ( FloatRegister fa, FloatRegister fb, int fmalit, FloatRegister fc ); ++ inline void vinsf ( FloatRegister fa, FloatRegister fb, int fmalit, FloatRegister fc ); ++ inline void vextw ( FloatRegister fa, int fmalit, FloatRegister fc); ++ inline void vextf ( FloatRegister fa, int fmalit, FloatRegister fc); ++ inline void vcpyw ( FloatRegister fa, FloatRegister fc); ++ inline void vcpyf ( FloatRegister fa, FloatRegister fc); ++ inline void vconw ( FloatRegister va, FloatRegister vb, FloatRegister fc, FloatRegister vd ); ++ inline void vshfw ( FloatRegister va, FloatRegister vb, FloatRegister fc, FloatRegister vd ); ++ inline void vcons ( FloatRegister va, FloatRegister vb, FloatRegister fc, FloatRegister vd ); ++ inline void vcond ( FloatRegister va, FloatRegister vb, FloatRegister fc, FloatRegister vd ); ++ inline void vldw_u ( FloatRegister fa, Register rb, int atmdisp );//load&store ++ inline void vstw_u ( FloatRegister fa, Register rb, int atmdisp ); ++ inline void vlds_u ( FloatRegister fa, Register rb, int atmdisp ); ++ inline void vsts_u ( FloatRegister fa, Register rb, int atmdisp ); ++ inline void vldd_u ( FloatRegister fa, Register rb, int atmdisp ); ++ inline void vstd_u ( FloatRegister fa, Register rb, int atmdisp ); ++ inline void vstw_ul ( FloatRegister fa, Register rb, int atmdisp ); ++ inline void vstw_uh ( FloatRegister fa, Register rb, int atmdisp ); ++ inline void vsts_ul ( FloatRegister fa, Register rb, int atmdisp ); ++ inline void vsts_uh ( FloatRegister fa, Register rb, int atmdisp ); ++ inline void vstd_ul ( FloatRegister fa, Register rb, int atmdisp ); ++ inline void vstd_uh ( FloatRegister fa, Register rb, int atmdisp ); ++ ++ inline void vlog ( int vlog, FloatRegister fa,FloatRegister fb,FloatRegister f3, FloatRegister fc ); ++ inline void vbisw ( FloatRegister fc, FloatRegister fa, FloatRegister fb ); ++ inline void vxorw ( FloatRegister fc, FloatRegister fa, FloatRegister fb ); ++ inline void vandw ( FloatRegister fc, FloatRegister fa, FloatRegister fb ); ++ inline void veqvw ( FloatRegister fc, FloatRegister fa, FloatRegister fb ); ++ inline void vornotw ( FloatRegister fc, FloatRegister fa, FloatRegister fb ); ++ inline void vbicw ( FloatRegister fc, FloatRegister fa, FloatRegister fb ); ++ /* ++ inline void vseleq ( FloatRegister fa, FloatRegister fb, FloatRegister f3, FloatRegister fc ); ++ inline void vselne ( FloatRegister fa, FloatRegister fb, FloatRegister f3, FloatRegister fc ); ++ inline void vsellt ( FloatRegister fa, FloatRegister fb, FloatRegister f3, FloatRegister fc ); ++ inline void vselle ( FloatRegister fa, FloatRegister fb, FloatRegister f3, FloatRegister fc ); ++ inline void vselgt ( FloatRegister fa, FloatRegister fb, FloatRegister f3, FloatRegister fc ); ++ inline void vselge ( FloatRegister fa, FloatRegister fb, FloatRegister f3, FloatRegister fc ); ++ */ ++ ++ //priority instructions ++ inline void pri_ret ( Register ra ); ++ inline void pri_ld ( Register ra, Register rb, int ev6hwdisp ); ++ inline void pri_st ( Register ra, Register rb, int ev6hwdisp ); ++ // cache control instructions ++ inline void s_fillcs ( Register rb, int mdisp ); ++ inline void s_fillde ( Register rb, int mdisp ); ++ inline void fillde ( Register rb, int mdisp ); ++ inline void fillde_e ( Register rb, int mdisp ); ++ inline void fillcs ( Register rb, int mdisp ); ++ inline void fillcs_e ( Register rb, int mdisp ); ++ inline void e_fillcs ( Register rb, int mdisp ); ++ inline void e_fillde ( Register rb, int mdisp ); ++ inline void flushd ( Register rb, int mdisp ); ++ inline void evictdl ( Register rb, int mdisp ); ++ inline void evictdg ( Register rb, int mdisp ); ++ //others ++ inline void memb ( void ); ++ inline void rtc ( Register ra, Register rb ); ++ inline void rcid ( Register ra); ++ inline void halt ( void); ++ inline void rtid ( Register ra); ++ inline void csrr ( Register ra, int rpiindex ); ++ inline void csrw ( Register ra, int rpiindex ); ++ //SW8A instructions ++ inline void imemb ( void ); //SW8A ++ inline void wmemb ( void ); //SW8A ++ inline void csrws ( Register ra, int rpiindex ); //SW8A ++ inline void csrwc ( Register ra, int rpiindex ); //SW8A ++ inline void divw ( Register ra, Register rb, Register rc ); //SW8A ++ inline void udivw ( Register ra, Register rb, Register rc ); //SW8A ++ inline void remw ( Register ra, Register rb, Register rc ); //SW8A ++ inline void uremw ( Register ra, Register rb, Register rc ); //SW8A ++ inline void mull ( Register ra, Register rb, Register rc ); //SW8A ++ inline void mull ( Register ra, int lit, Register rc ); //SW8A ++ inline void umulh ( Register ra, Register rb, Register rc ); //SW8A ++ inline void umulh ( Register ra, int lit, Register rc ); //SW8A ++ inline void divl ( Register ra, Register rb, Register rc ); //SW8A ++ inline void udivl ( Register ra, Register rb, Register rc ); //SW8A ++ inline void reml ( Register ra, Register rb, Register rc ); //SW8A ++ inline void ureml ( Register ra, Register rb, Register rc ); //SW8A ++ inline void addpi ( int apint, Register rc ); //SW8A ++ inline void addpis ( int apint, Register rc ); //SW8A ++ inline void sbt ( Register ra, Register rb, Register rc ); //SW8A ++ inline void sbt ( Register ra, int lit, Register rc ); //SW8A ++ inline void cbt ( Register ra, Register rb, Register rc ); //SW8A ++ inline void cbt ( Register ra, int lit, Register rc ); //SW8A ++ inline void roll ( Register ra, Register rb, Register rc ); //SW8A ++ inline void roll ( Register ra, int lit, Register rc ); //SW8A ++ inline void sllw ( Register ra, Register rb, Register rc ); //SW8A ++ inline void sllw ( Register ra, int lit, Register rc ); //SW8A ++ inline void srlw ( Register ra, Register rb, Register rc ); //SW8A ++ inline void srlw ( Register ra, int lit, Register rc ); //SW8A ++ inline void sraw ( Register ra, Register rb, Register rc ); //SW8A ++ inline void sraw ( Register ra, int lit, Register rc ); //SW8A ++ inline void rolw ( Register ra, Register rb, Register rc ); //SW8A ++ inline void rolw ( Register ra, int lit, Register rc ); //SW8A ++ inline void revbh ( Register rb, Register rc ); //SW8A ++ inline void revbw ( Register rb, Register rc ); //SW8A ++ inline void revbl ( Register rb, Register rc ); //SW8A ++ inline void casw ( Register ra, Register rb, Register rc ); //SW8A ++ inline void casl ( Register ra, Register rb, Register rc ); //SW8A ++ inline void frecs ( FloatRegister fa, FloatRegister fc ); //SW8A ++ inline void frecd ( FloatRegister fa, FloatRegister fc ); //SW8A ++ inline void fris ( FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void fris_g ( FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void fris_p ( FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void fris_z ( FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void fris_n ( FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void frid ( FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void frid_g ( FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void frid_p ( FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void frid_z ( FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void frid_n ( FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vsllb ( FloatRegister fa, FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vsllb ( FloatRegister fa, int lit, FloatRegister fc ); //SW8A ++ inline void vsrlb ( FloatRegister fa, FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vsrlb ( FloatRegister fa, int lit, FloatRegister fc ); //SW8A ++ inline void vsrab ( FloatRegister fa, FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vsrab ( FloatRegister fa, int lit, FloatRegister fc ); //SW8A ++ inline void vrolb ( FloatRegister fa, FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vrolb ( FloatRegister fa, int lit, FloatRegister fc ); //SW8A ++ inline void vsllh ( FloatRegister fa, FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vsllh ( FloatRegister fa, int lit, FloatRegister fc ); //SW8A ++ inline void vsrlh ( FloatRegister fa, FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vsrlh ( FloatRegister fa, int lit, FloatRegister fc ); //SW8A ++ inline void vsrah ( FloatRegister fa, FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vsrah ( FloatRegister fa, int lit, FloatRegister fc ); //SW8A ++ inline void vrolh ( FloatRegister fa, FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vrolh ( FloatRegister fa, int lit, FloatRegister fc ); //SW8A ++ inline void vslll ( FloatRegister fa, FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vslll ( FloatRegister fa, int lit, FloatRegister fc ); //SW8A ++ inline void vsrll ( FloatRegister fa, FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vsrll ( FloatRegister fa, int lit, FloatRegister fc ); //SW8A ++ inline void vsral ( FloatRegister fa, FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vsral ( FloatRegister fa, int lit, FloatRegister fc ); //SW8A ++ inline void vroll ( FloatRegister fa, FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vroll ( FloatRegister fa, int lit, FloatRegister fc ); //SW8A ++ inline void vmaxb ( FloatRegister fa, FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vminb ( FloatRegister fa, FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void sraow ( FloatRegister fa, FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void sraow ( FloatRegister fa, int lit, FloatRegister fc ); //SW8A ++ inline void vsumw ( FloatRegister fa, FloatRegister fc ); //SW8A ++ inline void vsuml ( FloatRegister fa, FloatRegister fc ); //SW8A ++ inline void vcmpueqb ( FloatRegister fa, FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vcmpueqb ( FloatRegister fa, int lit, FloatRegister fc ); //SW8A ++ inline void vcmpugtb ( FloatRegister fa, FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vcmpugtb ( FloatRegister fa, int lit, FloatRegister fc ); //SW8A ++ inline void vmaxh ( FloatRegister fa, FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vminh ( FloatRegister fa, FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vmaxw ( FloatRegister fa, FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vminw ( FloatRegister fa, FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vmaxl ( FloatRegister fa, FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vminl ( FloatRegister fa, FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vsm3msw ( FloatRegister fa, FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vsm4key ( FloatRegister fa, int lit, FloatRegister fc ); //SW8A ++ inline void vsm4r ( FloatRegister fa, FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vbinvw ( FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vumaxb ( FloatRegister fa, FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vuminb ( FloatRegister fa, FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vumaxh ( FloatRegister fa, FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vuminh ( FloatRegister fa, FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vumaxw ( FloatRegister fa, FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vuminw ( FloatRegister fa, FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vumaxl ( FloatRegister fa, FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vuminl ( FloatRegister fa, FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vsums ( FloatRegister fa, FloatRegister fc ); //SW8A ++ inline void vsumd ( FloatRegister fa, FloatRegister fc ); //SW8A ++ inline void vfrecs ( FloatRegister fa, FloatRegister fc ); //SW8A ++ inline void vfrecd ( FloatRegister fa, FloatRegister fc ); //SW8A ++ inline void vfcvtsd ( FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vfcvtds ( FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vfcvtls ( FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vfcvtld ( FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vfcvtdl ( FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vfcvtdl_g ( FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vfcvtdl_p ( FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vfcvtdl_z ( FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vfcvtdl_n ( FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vfris ( FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vfris_g ( FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vfris_p ( FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vfris_z ( FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vfris_n ( FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vfrid ( FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vfrid_g ( FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vfrid_p ( FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vfrid_z ( FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vfrid_n ( FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vmaxs ( FloatRegister fa, FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vmins ( FloatRegister fa, FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vmaxd ( FloatRegister fa, FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vmind ( FloatRegister fa, FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vinsb ( FloatRegister fa, FloatRegister fb, int fmalit, FloatRegister fc ); //SW8A ++ inline void vinsh ( FloatRegister fa, FloatRegister fb, int fmalit, FloatRegister fc ); //SW8A ++ inline void vinsectlh ( FloatRegister fa, FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vinsectlw ( FloatRegister fa, FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vinsectll ( FloatRegister fa, FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vinsectlb ( FloatRegister fa, FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vshfq ( FloatRegister fa, FloatRegister fb, int fmalit, FloatRegister fc ); //SW8A ++ inline void vshfqb ( FloatRegister fa, FloatRegister fb, FloatRegister fc ); //SW8A ++ inline void vcpyb ( FloatRegister fa, FloatRegister fc ); //SW8A ++ inline void vcpyh ( FloatRegister fa, FloatRegister fc ); //SW8A ++ inline void vsm3r ( FloatRegister fa, FloatRegister fb, int fmalit, FloatRegister fc ); //SW8A ++ inline void vfcvtsh ( FloatRegister fa, FloatRegister fb, int fmalit, FloatRegister fc ); //SW8A ++ inline void vfcvths ( FloatRegister fa, FloatRegister fb, int fmalit, FloatRegister fc ); //SW8A ++ inline void lbr ( int palfn ); //SW8A ++ inline void ldbu_a ( Register ra, int atmdisp, Register rb ); //SW8A ++ inline void ldhu_a ( Register ra, int atmdisp, Register rb ); //SW8A ++ inline void ldw_a ( Register ra, int atmdisp, Register rb ); //SW8A ++ inline void ldl_a ( Register ra, int atmdisp, Register rb ); //SW8A ++ inline void stb_a ( Register ra, int atmdisp, Register rb ); //SW8A ++ inline void sth_a ( Register ra, int atmdisp, Register rb ); //SW8A ++ inline void stw_a ( Register ra, int atmdisp, Register rb ); //SW8A ++ inline void stl_a ( Register ra, int atmdisp, Register rb ); //SW8A ++ inline void flds_a ( FloatRegister fa, int atmdisp, Register rb ); //SW8A ++ inline void fldd_a ( FloatRegister fa, int atmdisp, Register rb ); //SW8A ++ inline void fsts_a ( FloatRegister fa, int atmdisp, Register rb ); //SW8A ++ inline void fstd_a ( FloatRegister fa, int atmdisp, Register rb ); //SW8A ++ inline void dpfhr ( int th, int atmdisp, Register rb ); //SW8A ++ inline void dpfhw ( int th, int atmdisp, Register rb ); //SW8A ++ inline void crc32b ( Register rd, Register rs, Register rt ); //SW8A ++ inline void crc32h ( Register rd, Register rs, Register rt ); //SW8A ++ inline void crc32w ( Register rd, Register rs, Register rt ); //SW8A ++ inline void crc32l ( Register rd, Register rs, Register rt ); //SW8A ++ inline void crc32cb ( Register rd, Register rs, Register rt ); //SW8A ++ inline void crc32ch ( Register rd, Register rs, Register rt ); //SW8A ++ inline void crc32cw ( Register rd, Register rs, Register rt ); //SW8A ++ inline void crc32cl ( Register rd, Register rs, Register rt ); //SW8A ++ ++public: ++ // Creation ++ Assembler(CodeBuffer* code) : AbstractAssembler(code) { ++ } ++}; ++ ++ ++#endif // CPU_SW64_VM_ASSEMBLER_SW64_HPP +diff --git a/hotspot/src/cpu/sw64/vm/assembler_sw64.inline.hpp b/hotspot/src/cpu/sw64/vm/assembler_sw64.inline.hpp +new file mode 100755 +index 0000000000..85391a3baa +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/assembler_sw64.inline.hpp +@@ -0,0 +1,1292 @@ ++/* ++ * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2015, 2018, Wuxi Institute of Advanced Technology. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_SW64_VM_ASSEMBLER_SW64_INLINE_HPP ++#define CPU_SW64_VM_ASSEMBLER_SW64_INLINE_HPP ++ ++#include "asm/assembler.inline.hpp" ++#include "asm/codeBuffer.hpp" ++#include "code/codeCache.hpp" ++ ++ ++inline void Assembler::emit_long(int x) { ++ Unimplemented(); ++ AbstractAssembler::emit_int32(x); ++} ++ ++inline void Assembler::emit_data(int x, relocInfo::relocType rtype) { ++ Unimplemented(); ++ relocate(rtype); ++ emit_long(x); ++} ++ ++inline void Assembler::emit_data(int x, RelocationHolder const& rspec) { ++ Unimplemented(); ++ relocate(rspec); ++ emit_long(x); ++} ++ ++inline void Assembler::emit_sw2_long(int x) { ++ AbstractAssembler::emit_int32(x); ++} ++ ++inline void Assembler::emit_sw2_data(int x, relocInfo::relocType rtype) { ++ relocate(rtype); ++ emit_sw2_long(x); ++} ++ ++inline void Assembler::emit_sw2_data(int x, RelocationHolder const& rspec) { ++ relocate(rspec); ++ emit_sw2_long(x); ++} ++ ++ inline void Assembler::sys_call_b( int palfn ) ++ { emit_sw2_long( op_sys_call | is_palfn(palfn) ); } ++ inline void Assembler::sys_call( int palfn ) ++ { sys_call_b(palfn); /* emit_sw2_long( op_sys_call | ( 0x1 << 25 ) | is_palfn(palfn) );*/ } ++ ++//jump instructions ++ inline void Assembler::call( Register ra, Register rb, int jmphint ) ++ { emit_sw2_long( op_call | is_ra(ra) | is_rb(rb) | is_jmphint(jmphint) ); } ++ inline void Assembler::ret( Register ra, Register rb, int rethint ) ++ { emit_sw2_long( op_ret | is_ra(ra) | is_rb(rb) | is_rethint(rethint) ); } ++ inline void Assembler::jmp( Register ra, Register rb, int jmphint ) ++#ifdef YJDEBUG ++ { emit_sw2_long( op_call | is_ra(GP) | is_rb(rb) | is_jmphint(jmphint) ); } ++#else ++ { emit_sw2_long( op_jmp | is_ra(ra) | is_rb(rb) | is_jmphint(jmphint) ); } ++#endif ++ ++ //arithmetic ++ inline void Assembler::addw( Register rd, Register rs, Register rt ) ++ { emit_sw2_long( op_addw | is_ra(rs) | is_rb(rt) | is_rc(rd) ); } ++ inline void Assembler::addw(Register rd, Register rs , int lit) ++ { emit_sw2_long( op_addw_l | is_ra(rs) | is_lit(lit) | is_rc(rd) ); } ++ inline void Assembler::subw(Register rd, Register rs, Register rt) ++ { emit_sw2_long( op_subw | is_ra(rs) | is_rb(rt) | is_rc(rd) ); } ++ inline void Assembler::subw( Register rd, Register rs, int lit ) ++ { emit_sw2_long( op_subw_l | is_ra(rs) | is_lit(lit) | is_rc(rd) ); } ++ inline void Assembler::s4addw( Register rd, Register rs, Register rt ) ++ { emit_sw2_long( op_s4addw | is_ra(rs) | is_rb(rt) | is_rc(rd) ); } ++ inline void Assembler::s4addw( Register rd, Register rs, int lit ) ++ { emit_sw2_long( op_s4addw_l | is_ra(rs) | is_lit(lit) | is_rc(rd) ); } ++ inline void Assembler::s4subw( Register rd, Register rs, Register rt ) ++ { emit_sw2_long( op_s4subw | is_ra(rs) | is_rb(rt) | is_rc(rd) ); } ++ inline void Assembler::s4subw( Register rd, Register rs, int lit ) ++ { emit_sw2_long( op_s4subw_l | is_ra(rs) | is_lit(lit) | is_rc(rd) ); } ++ inline void Assembler::s8addw( Register rd, Register rs, Register rt ) ++ { emit_sw2_long( op_s8addw | is_ra(rs) | is_rb(rt) | is_rc(rd) ); } ++ inline void Assembler::s8addw( Register rd, Register rs, int lit ) ++ { emit_sw2_long( op_s8addw_l | is_ra(rs) | is_lit(lit) | is_rc(rd) ); } ++ inline void Assembler::s8subw( Register rd, Register rs, Register rt ) ++ { emit_sw2_long( op_s8subw | is_ra(rs) | is_rb(rt) | is_rc(rd) ); } ++ inline void Assembler::s8subw( Register rd, Register rs, int lit ) ++ { emit_sw2_long( op_s8subw_l | is_ra(rs) | is_lit(lit) | is_rc(rd) ); } ++ ++ inline void Assembler::addl( Register rd, Register rs, Register rt ) ++ { emit_sw2_long( op_addl | is_ra(rs) | is_rb(rt) | is_rc(rd) ); } ++ inline void Assembler::addl(Register rd, Register rs, int lit) ++ { emit_sw2_long( op_addl_l | is_ra(rs) | is_lit(lit) | is_rc(rd) ); } ++ inline void Assembler::subl( Register rd, Register rs, Register rt ) ++ { emit_sw2_long( op_subl | is_ra(rs) | is_rb(rt) | is_rc(rd) ); } ++ inline void Assembler::subl(Register rd, Register rs, int lit) ++ { emit_sw2_long( op_subl_l | is_ra(rs) | is_lit(lit) | is_rc(rd) ); } ++ inline void Assembler::s4addl( Register rd, Register rs, Register rt ) ++ { emit_sw2_long( op_s4addl | is_ra(rs) | is_rb(rt) | is_rc(rd) ); } ++ inline void Assembler::s4addl( Register rd, Register rs, int lit ) ++ { emit_sw2_long( op_s4addl_l | is_ra(rs) | is_lit(lit) | is_rc(rd) ); } ++ inline void Assembler::s4subl( Register ra, Register rb, Register rc ) ++ { emit_sw2_long( op_s4subl | is_ra(ra) | is_rb(rb) | is_rc(rc) ); } ++ inline void Assembler::s4subl( Register rd, Register rs, int lit ) ++ { emit_sw2_long( op_s4subl_l | is_ra(rs) | is_lit(lit) | is_rc(rd) ); } ++ inline void Assembler::s8addl( Register rd, Register rs, Register rt ) ++ { emit_sw2_long( op_s8addl | is_ra(rs) | is_rb(rt) | is_rc(rd) ); } ++ inline void Assembler::s8addl( Register rd, Register rs, int lit ) ++ { emit_sw2_long( op_s8addl_l | is_ra(rs) | is_lit(lit) | is_rc(rd) ); } ++ inline void Assembler::s8subl( Register rd, Register rs, Register rt ) ++ { emit_sw2_long( op_s8subl | is_ra(rs) | is_rb(rt) | is_rc(rd) ); } ++ inline void Assembler::s8subl( Register rd, Register rs, int lit ) ++ { emit_sw2_long( op_s8subl_l | is_ra(rs) | is_lit(lit) | is_rc(rd) ); } ++ ++ inline void Assembler::mulw(Register rd, Register rs, Register rt) ++ { emit_sw2_long( op_mulw | is_ra(rs) | is_rb(rt) | is_rc(rd) ); } ++ inline void Assembler::mulw( Register rd, Register rs, int lit ) ++ { emit_sw2_long( op_mulw_l | is_ra(rs) | is_lit(lit) | is_rc(rd) ); } ++ ++ inline void Assembler::mull( Register ra, Register rb, Register rc ) ++ { emit_sw2_long( op_mull | is_ra(ra) | is_rb(rb) | is_rc(rc) ); } ++ inline void Assembler::mull( Register ra, int lit, Register rc ) ++ { emit_sw2_long( op_mull_l | is_ra(ra) | is_lit(lit) | is_rc(rc) ); } ++ inline void Assembler::umulh( Register ra, Register rb, Register rc ) ++ { emit_sw2_long( op_umulh | is_ra(ra) | is_rb(rb) | is_rc(rc) ); } ++ inline void Assembler::umulh( Register ra, int lit, Register rc ) ++ { emit_sw2_long( op_umulh_l | is_ra(ra) | is_lit(lit) | is_rc(rc) ); } ++ ++ inline void Assembler::and_reg(Register rd, Register rs, Register rt) ++ { emit_sw2_long( op_and | is_ra(rs) | is_rb(rt) | is_rc(rd) ); } ++ inline void Assembler::and_imm8(Register rd, Register rs, int lit) ++ { emit_sw2_long( op_and_l | is_ra(rs) | is_lit(lit) | is_rc(rd) ); } ++ inline void Assembler::bic( Register rd, Register rs, Register rt ) ++ { emit_sw2_long( op_bic | is_ra(rs) | is_rb(rt) | is_rc(rd) ); } ++ inline void Assembler::bic( Register rd, Register rs, int lit ) ++ { emit_sw2_long( op_bic_l | is_ra(rs) | is_lit(lit) | is_rc(rd) ); } ++ inline void Assembler::bis(Register rd, Register rs, Register rt) ++ { emit_sw2_long( op_bis | is_ra(rs) | is_rb(rt) | is_rc(rd) ); } ++ inline void Assembler::bis( Register rd, Register rs, int lit ) ++ { emit_sw2_long( op_bis_l | is_ra(rs) | is_lit(lit) | is_rc(rd) ); } ++ inline void Assembler::ornot( Register rd, Register rs, Register rt) ++ { emit_sw2_long( op_ornot | is_ra(rs) | is_rb(rt) | is_rc(rd) ); } ++ inline void Assembler::ornot( Register rd, Register rs, int lit ) ++ { emit_sw2_long( op_ornot_l | is_ra(rs) | is_lit(lit) | is_rc(rd) ); } ++ inline void Assembler::xor_ins(Register rd, Register rs, Register rt ) ++ { emit_sw2_long( op_xor | is_ra(rs) | is_rb(rt) | is_rc(rd) ); } ++ inline void Assembler::xor_ins( Register rd, Register rs, int lit ) ++ { emit_sw2_long( op_xor_l | is_ra(rs) | is_lit(lit) | is_rc(rd) ); } ++ inline void Assembler::eqv( Register rd, Register rs, Register rt ) ++ { emit_sw2_long( op_eqv | is_ra(rs) | is_rb(rt) | is_rc(rd) ); } ++ inline void Assembler::eqv( Register rd, Register rs, int lit ) ++ { emit_sw2_long( op_eqv_l | is_ra(rs) | is_lit(lit) | is_rc(rd) ); } ++ ++ inline void Assembler::inslb( Register rd, Register rs, Register rt ) ++ { emit_sw2_long( op_inslb | is_ra(rs) | is_rb(rt) | is_rc(rd) ); } ++ inline void Assembler::inslb( Register rd, Register rs, int lit ) ++ { emit_sw2_long( op_inslb_l | is_ra(rs) | is_lit(lit) | is_rc(rd) ); } ++ inline void Assembler::inslh( Register rd, Register rs, Register rt ) ++ { emit_sw2_long( op_inslh | is_ra(rs) | is_rb(rt) | is_rc(rd) ); } ++ inline void Assembler::inslh( Register rd, Register rs, int lit ) ++ { emit_sw2_long( op_inslh_l | is_ra(rs) | is_lit(lit) | is_rc(rd) ); } ++ inline void Assembler::inslw( Register rd, Register rs, Register rt ) ++ { emit_sw2_long( op_inslw | is_ra(rs) | is_rb(rt) | is_rc(rd) ); } ++ inline void Assembler::inslw( Register rd, Register rs, int lit ) ++ { emit_sw2_long( op_inslw_l | is_ra(rs) | is_lit(lit) | is_rc(rd) ); } ++ inline void Assembler::insll( Register rd, Register rs, Register rt ) ++ { emit_sw2_long( op_insll | is_ra(rs) | is_rb(rt) | is_rc(rd) ); } ++ inline void Assembler::insll( Register rd, Register rs, int lit ) ++ { emit_sw2_long( op_insll_l | is_ra(rs) | is_lit(lit) | is_rc(rd) ); } ++ inline void Assembler::inshb( Register rd, Register rs, Register rt ) ++ { emit_sw2_long( op_inshb | is_ra(rs) | is_rb(rt) | is_rc(rd) ); } ++ inline void Assembler::inshb( Register rd, Register rs, int lit ) ++ { emit_sw2_long( op_inshb_l | is_ra(rs) | is_lit(lit) | is_rc(rd) ); } ++ inline void Assembler::inshh( Register rd, Register rs, Register rt ) ++ { emit_sw2_long( op_inshh | is_ra(rs) | is_rb(rt) | is_rc(rd) ); } ++ inline void Assembler::inshh( Register rd, Register rs, int lit ) ++ { emit_sw2_long( op_inshh_l | is_ra(rs) | is_lit(lit) | is_rc(rd) ); } ++ inline void Assembler::inshw( Register rd, Register rs, Register rt ) ++ { emit_sw2_long( op_inshw | is_ra(rs) | is_rb(rt) | is_rc(rd) ); } ++ inline void Assembler::inshw( Register rd, Register rs, int lit ) ++ { emit_sw2_long( op_inshw_l | is_ra(rs) | is_lit(lit) | is_rc(rd) ); } ++ inline void Assembler::inshl( Register rd, Register rs, Register rt ) ++ { emit_sw2_long( op_inshl | is_ra(rs) | is_rb(rt) | is_rc(rd) ); } ++ inline void Assembler::inshl( Register rd, Register rs, int lit ) ++ { emit_sw2_long( op_inshl_l | is_ra(rs) | is_lit(lit) | is_rc(rd) ); } ++ inline void Assembler::slll( Register rd, Register rt, Register rs ) ++ { emit_sw2_long( op_slll | is_ra(rt) | is_rb(rs) | is_rc(rd) ); } ++ inline void Assembler::slll( Register rt, Register rs, int lit ) ++ { emit_sw2_long( op_slll_l | is_ra(rs) | is_lit(lit) | is_rc(rt) ); } ++ inline void Assembler::srll(Register rd, Register rt, Register rs) ++ { emit_sw2_long( op_srll | is_ra(rt) | is_rb(rs) | is_rc(rd) ); } ++ inline void Assembler::srll(Register rd, Register rs, int lit) ++ { emit_sw2_long( op_srll_l | is_ra(rs) | is_lit(lit) | is_rc(rd) ); } ++ inline void Assembler::sral(Register rd, Register rt, Register rs) ++ { emit_sw2_long( op_sral | is_ra(rt) | is_rb(rs) | is_rc(rd) ); } ++ inline void Assembler::sral(Register rt, Register rs, int lit) ++ { emit_sw2_long( op_sral_l | is_ra(rs) | is_lit(lit) | is_rc(rt) ); } ++ ++ inline void Assembler::extlb( Register rd, Register rs, Register rt ) ++ { emit_sw2_long( op_extlb | is_ra(rs) | is_rb(rt) | is_rc(rd) ); } ++ inline void Assembler::extlb( Register rd, Register rs, int lit ) ++ { emit_sw2_long( op_extlb_l | is_ra(rs) | is_lit(lit) | is_rc(rd) ); } ++ inline void Assembler::extlh( Register rd, Register rs, Register rt ) ++ { emit_sw2_long( op_extlh | is_ra(rs) | is_rb(rt) | is_rc(rd) ); } ++ inline void Assembler::extlh( Register rd, Register rs, int lit ) ++ { emit_sw2_long( op_extlh_l | is_ra(rs) | is_lit(lit) | is_rc(rd) ); } ++ inline void Assembler::extlw( Register rd, Register rs, Register rt ) ++ { emit_sw2_long( op_extlw | is_ra(rs) | is_rb(rt) | is_rc(rd) ); } ++ inline void Assembler::extlw( Register rd, Register rs, int lit ) ++ { emit_sw2_long( op_extlw_l | is_ra(rs) | is_lit(lit) | is_rc(rd) ); } ++ inline void Assembler::extll( Register rd, Register rs, Register rt ) ++ { emit_sw2_long( op_extll | is_ra(rs) | is_rb(rt) | is_rc(rd) ); } ++ inline void Assembler::extll( Register rd, Register rs, int lit ) ++ { emit_sw2_long( op_extll_l | is_ra(rs) | is_lit(lit) | is_rc(rd) ); } ++ inline void Assembler::exthb( Register rd, Register rs, Register rt ) ++ { emit_sw2_long( op_exthb | is_ra(rs) | is_rb(rt) | is_rc(rd) ); } ++ inline void Assembler::exthb( Register rd, Register rs, int lit ) ++ { emit_sw2_long( op_exthb_l | is_ra(rs) | is_lit(lit) | is_rc(rd) ); } ++ inline void Assembler::exthh( Register rd, Register rs, Register rt ) ++ { emit_sw2_long( op_exthh | is_ra(rs) | is_rb(rt) | is_rc(rd) ); } ++ inline void Assembler::exthh( Register rd, Register rs, int lit ) ++ { emit_sw2_long( op_exthh_l | is_ra(rs) | is_lit(lit) | is_rc(rd) ); } ++ inline void Assembler::exthw( Register rd, Register rs, Register rt ) ++ { emit_sw2_long( op_exthw | is_ra(rs) | is_rb(rt) | is_rc(rd) ); } ++ inline void Assembler::exthw( Register rd, Register rs, int lit ) ++ { emit_sw2_long( op_exthw_l | is_ra(rs) | is_lit(lit) | is_rc(rd) ); } ++ inline void Assembler::exthl( Register rd, Register rs, Register rt ) ++ { emit_sw2_long( op_exthl | is_ra(rs) | is_rb(rt) | is_rc(rd) ); } ++ inline void Assembler::exthl( Register rd, Register rs, int lit ) ++ { emit_sw2_long( op_exthl_l | is_ra(rs) | is_lit(lit) | is_rc(rd) ); } ++ ++ inline void Assembler::ctpop( Register rc, Register rb ) ++ { emit_sw2_long( op_ctpop | is_rb(rb) | is_rc(rc) ); } ++ inline void Assembler::ctlz( Register rc, Register rb ) ++ { emit_sw2_long( op_ctlz | is_rb(rb) | is_rc(rc) ); } ++ inline void Assembler::cttz( Register rc, Register rb ) ++ { emit_sw2_long( op_cttz | is_rb(rb) | is_rc(rc) ); } ++ ++ inline void Assembler::masklb( Register rd, Register rs, Register rt ) ++ { emit_sw2_long( op_masklb | is_ra(rs) | is_rb(rt) | is_rc(rd) ); } ++ inline void Assembler::masklb( Register rd, Register rs, int lit ) ++ { emit_sw2_long( op_masklb_l | is_ra(rs) | is_lit(lit) | is_rc(rd) ); } ++ inline void Assembler::masklh( Register rd, Register rs, Register rt ) ++ { emit_sw2_long( op_masklh | is_ra(rs) | is_rb(rt) | is_rc(rd) ); } ++ inline void Assembler::masklh( Register rd, Register rs, int lit ) ++ { emit_sw2_long( op_masklh_l | is_ra(rs) | is_lit(lit) | is_rc(rd) ); } ++ inline void Assembler::masklw( Register rd, Register rs, Register rt ) ++ { emit_sw2_long( op_masklw | is_ra(rs) | is_rb(rt) | is_rc(rd) ); } ++ inline void Assembler::masklw( Register rd, Register rs, int lit ) ++ { emit_sw2_long( op_masklw_l | is_ra(rs) | is_lit(lit) | is_rc(rd) ); } ++ inline void Assembler::maskll( Register rd, Register rs, Register rt ) ++ { emit_sw2_long( op_maskll | is_ra(rs) | is_rb(rt) | is_rc(rd) ); } ++ inline void Assembler::maskll( Register rd, Register rs, int lit ) ++ { emit_sw2_long( op_maskll_l | is_ra(rs) | is_lit(lit) | is_rc(rd) ); } ++ inline void Assembler::maskhb( Register rd, Register rs, Register rt ) ++ { emit_sw2_long( op_maskhb | is_ra(rs) | is_rb(rt) | is_rc(rd) ); } ++ inline void Assembler::maskhb( Register rd, Register rs, int lit ) ++ { emit_sw2_long( op_maskhb_l | is_ra(rs) | is_lit(lit) | is_rc(rd) ); } ++ inline void Assembler::maskhh( Register rd, Register rs, Register rt ) ++ { emit_sw2_long( op_maskhh | is_ra(rs) | is_rb(rt) | is_rc(rd) ); } ++ inline void Assembler::maskhh( Register rd, Register rs, int lit ) ++ { emit_sw2_long( op_maskhh_l | is_ra(rs) | is_lit(lit) | is_rc(rd) ); } ++ inline void Assembler::maskhw( Register rd, Register rs, Register rt ) ++ { emit_sw2_long( op_maskhw | is_ra(rs) | is_rb(rt) | is_rc(rd) ); } ++ inline void Assembler::maskhw( Register rd, Register rs, int lit ) ++ { emit_sw2_long( op_maskhw_l | is_ra(rs) | is_lit(lit) | is_rc(rd) ); } ++ inline void Assembler::maskhl( Register rd, Register rs, Register rt ) ++ { emit_sw2_long( op_maskhl | is_ra(rs) | is_rb(rt) | is_rc(rd) ); } ++ inline void Assembler::maskhl( Register rd, Register rs, int lit ) ++ { emit_sw2_long( op_maskhl_l | is_ra(rs) | is_lit(lit) | is_rc(rd) ); } ++ ++ inline void Assembler::zap( Register rd, Register rs, Register rt ) ++ { emit_sw2_long( op_zap | is_ra(rs) | is_rb(rt) | is_rc(rd) ); } ++ inline void Assembler::zap( Register rd, Register rs, int lit ) ++ { emit_sw2_long( op_zap_l | is_ra(rs) | is_lit(lit) | is_rc(rd) ); } ++ inline void Assembler::zapnot( Register rd, Register rs, Register rt ) ++ { emit_sw2_long( op_zapnot | is_ra(rs) | is_rb(rt) | is_rc(rd) ); } ++ inline void Assembler::zapnot( Register rd, Register rs, int lit ) ++ { emit_sw2_long( op_zapnot_l | is_ra(rs) | is_lit(lit) | is_rc(rd) ); } ++ inline void Assembler::sextb( Register rc, Register rb) ++ { emit_sw2_long( op_sextb | is_ra(R0) | is_rb(rb) | is_rc(rc) ); } ++ inline void Assembler::sextb( Register rc, int lit ) ++ { emit_sw2_long( op_sextb_l | is_ra(R0) | is_lit(lit) | is_rc(rc) ); } ++ inline void Assembler::sexth( Register rc, Register rb ) ++ { emit_sw2_long( op_sexth | is_ra(R0) | is_rb(rb) | is_rc(rc) ); } ++ inline void Assembler::sexth( Register rc, int lit ) ++ { emit_sw2_long( op_sexth_l | is_ra(R0) | is_lit(lit) | is_rc(rc) ); } ++ //load&store ++ inline void Assembler::ldbu( Register rt, Register rs, int mdisp ) ++ { emit_sw2_long( op_ldbu | is_ra(rt) | is_mdisp(mdisp) | is_rb(rs) ); } ++ inline void Assembler::ldhu( Register rt, Register rs, int mdisp ) ++ { emit_sw2_long( op_ldhu | is_ra(rt) | is_mdisp(mdisp) | is_rb(rs) ); } ++ inline void Assembler::ldw( Register rt, Register rs, int mdisp ) ++ { emit_sw2_long( op_ldw | is_ra(rt) | is_mdisp(mdisp) | is_rb(rs) ); } ++ inline void Assembler::ldl( Register rt, Register rs, int mdisp ) ++ { emit_sw2_long( op_ldl | is_ra(rt) | is_mdisp(mdisp) | is_rb(rs) ); } ++ inline void Assembler::ldl_u( Register ra, Register rb, int mdisp ) ++ { emit_sw2_long( op_ldl_u | is_ra(ra) | is_mdisp(mdisp) | is_rb(rb) ); } ++ ++ inline void Assembler::stb( Register rt, Register rs, int mdisp ) ++ { emit_sw2_long( op_stb | is_ra(rt) | is_mdisp(mdisp) | is_rb(rs) ); } ++ inline void Assembler::sth(Register ra, Register rb , int mdisp) ++ { emit_sw2_long( op_sth | is_ra(ra) | is_mdisp(mdisp) | is_rb(rb) ); } ++ inline void Assembler::stw( Register rt, Register rs, int mdisp ) ++ { emit_sw2_long( op_stw | is_ra(rt) | is_mdisp(mdisp) | is_rb(rs) ); } ++ inline void Assembler::stl( Register rt, Register rs, int mdisp ) ++ { emit_sw2_long( op_stl | is_ra(rt) | is_mdisp(mdisp) | is_rb(rs) ); } ++ inline void Assembler::stl_u( Register ra, Register rb, int mdisp ) ++ { emit_sw2_long( op_stl_u | is_ra(ra) | is_mdisp(mdisp) | is_rb(rb) ); } ++ ++ inline void Assembler::ldi( Register ra, Register rb, int mdisp ) ++ { emit_sw2_long( op_ldi | is_ra(ra) | is_mdisp(mdisp) | is_rb(rb) ); } ++ inline void Assembler::ldih( Register ra, Register rb, int mdisp ) ++ { emit_sw2_long( op_ldih | is_ra(ra) | is_mdisp(mdisp) | is_rb(rb) ); } ++ ++ inline void Assembler::ldw_nc( Register rd, Register rs , int atmdisp ) ++ { emit_sw2_long( op_ldw_nc | is_ra(rd) | is_atmdisp(atmdisp) | is_rc(rs) ); } ++ inline void Assembler::ldl_nc( Register rd, Register rs , int atmdisp ) ++ { emit_sw2_long( op_ldl_nc | is_ra(rd) | is_atmdisp(atmdisp) | is_rc(rs) ); } ++ inline void Assembler::ldd_nc( Register rd, Register rs , int atmdisp ) ++ { emit_sw2_long( op_ldd_nc | is_ra(rd) | is_atmdisp(atmdisp) | is_rc(rs) ); } ++ inline void Assembler::stw_nc( Register rd, Register rs , int atmdisp ) ++ { emit_sw2_long( op_stw_nc | is_ra(rd) | is_atmdisp(atmdisp) | is_rc(rs) ); } ++ inline void Assembler::stl_nc( Register rd, Register rs , int atmdisp ) ++ { emit_sw2_long( op_stl_nc | is_ra(rd) | is_atmdisp(atmdisp) | is_rc(rs) ); } ++ inline void Assembler::std_nc( Register rd, Register rs , int atmdisp ) ++ { emit_sw2_long( op_std_nc | is_ra(rd) | is_atmdisp(atmdisp) | is_rc(rs) ); } ++ ++ inline void Assembler::lldw( Register rt, Register rs, int atmdisp )//lock ++ { emit_sw2_long( op_lldw | is_ra(rt) | is_atmdisp(atmdisp) | is_rb(rs) ); } ++ inline void Assembler::lldl( Register rt, Register rs, int atmdisp ) ++ { emit_sw2_long( op_lldl | is_ra(rt) | is_atmdisp(atmdisp) | is_rb(rs) ); } ++ inline void Assembler::lstw( Register rt, Register rs, int atmdisp ) ++ { emit_sw2_long( op_lstw | is_ra(rt) | is_atmdisp(atmdisp) | is_rb(rs) ); } ++ inline void Assembler::lstl( Register rt, Register rs, int atmdisp ) ++ { emit_sw2_long( op_lstl | is_ra(rt) | is_atmdisp(atmdisp) | is_rb(rs) ); } ++ inline void Assembler::rd_f( Register ra ) { ++ if (UseSW8A) { nop(); } else { sw2_only(); emit_sw2_long( op_rd_f | is_ra(ra) | is_rb(R0) ); } ++ } ++ inline void Assembler::wr_f( Register ra ) { ++ if (UseSW8A) { nop(); } else { sw2_only(); emit_sw2_long( op_wr_f | is_ra(ra) | is_rb(R0) ); } ++ } ++ ++ inline void Assembler::ldw_inc( Register rd, Register rs , int atmdisp )//atom ++ { sw2_only(); emit_sw2_long( op_ldw_inc | is_ra(rs) | is_atmdisp(atmdisp) | is_rc(rd) ); } ++ inline void Assembler::ldl_inc( Register rd, Register rs , int atmdisp ) ++ { sw2_only(); emit_sw2_long( op_ldl_inc | is_ra(rs) | is_atmdisp(atmdisp) | is_rc(rd) ); } ++ inline void Assembler::ldw_dec( Register rd, Register rs , int atmdisp ) ++ { sw2_only(); emit_sw2_long( op_ldw_dec | is_ra(rs) | is_atmdisp(atmdisp) | is_rc(rd) ); } ++ inline void Assembler::ldl_dec( Register rd, Register rs , int atmdisp ) ++ { sw2_only(); emit_sw2_long( op_ldl_dec | is_ra(rs) | is_atmdisp(atmdisp) | is_rc(rd) ); } ++ inline void Assembler::ldw_set( Register rd, Register rs , int atmdisp ) ++ { sw2_only(); emit_sw2_long( op_ldw_set | is_ra(rs) | is_atmdisp(atmdisp) | is_rc(rd) ); } ++ inline void Assembler::ldl_set( Register rd, Register rs , int atmdisp ) ++ { sw2_only(); emit_sw2_long( op_ldl_set | is_ra(rs) | is_atmdisp(atmdisp) | is_rc(rd) ); } ++ //compare ++ inline void Assembler::cmpeq( Register rd, Register rs, Register rt ) ++ { emit_sw2_long( op_cmpeq | is_ra(rs) | is_rb(rt) | is_rc(rd) ); } ++ inline void Assembler::cmpeq( Register rd, Register rs, int lit) ++ { emit_sw2_long( op_cmpeq_l | is_ra(rs) | is_lit(lit) | is_rc(rd) ); } ++ inline void Assembler::cmplt(Register rd, Register rs, Register rt) ++ { emit_sw2_long( op_cmplt | is_ra(rs) | is_rb(rt) | is_rc(rd) ); } ++ inline void Assembler::cmplt( Register rd, Register rs, int lit) ++ { emit_sw2_long( op_cmplt_l | is_ra(rs) | is_lit(lit) | is_rc(rd) ); } ++ inline void Assembler::cmple( Register rd, Register rs, Register rt ) ++ { emit_sw2_long( op_cmpule | is_ra(rs) | is_rb(rt) | is_rc(rd) ); } ++ inline void Assembler::cmple( Register rd, Register rs, int lit ) ++ { emit_sw2_long( op_cmple_l | is_ra(rs) | is_lit(lit) | is_rc(rd) ); } ++ inline void Assembler::cmpult( Register rd, Register rs, Register rt ) ++ { emit_sw2_long( op_cmpult | is_ra(rs) | is_rb(rt) | is_rc(rd) ); } ++ inline void Assembler::cmpult(Register rd, Register rs, int lit) ++ { emit_sw2_long( op_cmpult_l | is_ra(rs) | is_lit(lit) | is_rc(rd) ); } ++ inline void Assembler::cmpule( Register rd, Register rs, Register rt ) ++ { emit_sw2_long( op_cmpule | is_ra(rs) | is_rb(rt) | is_rc(rd) ); } ++ inline void Assembler::cmpule( Register rd, Register rs, int lit ) ++ { emit_sw2_long( op_cmpule_l | is_ra(rs) | is_lit(lit) | is_rc(rd) ); } ++ inline void Assembler::cmpgeb( Register rc, Register ra, Register rb ) ++ { emit_sw2_long( op_cmpgeb | is_ra(ra) | is_rb(rb) | is_rc(rc) ); } ++ inline void Assembler::cmpgeb( Register rc, Register ra, int lit ) ++ { emit_sw2_long( op_cmpgeb_l | is_ra(ra) | is_lit(lit) | is_rc(rc) ); } ++ //branch ++ inline void Assembler::br( Register ra, int bdisp ) ++ { emit_sw2_long( op_br | is_ra(ra) | is_bdisp(bdisp) ); } ++ inline void Assembler::bsr( Register ra, int bdisp ) ++ { emit_sw2_long( op_bsr | is_ra(ra) | is_bdisp(bdisp) ); } ++ inline void Assembler::beq( Register ra, int bdisp ) ++ { emit_sw2_long( op_beq | is_ra(ra) | is_bdisp(bdisp) ); } ++ inline void Assembler::bne( Register ra, int bdisp ) ++ { emit_sw2_long( op_bne | is_ra(ra) | is_bdisp(bdisp) ); } ++ inline void Assembler::blt( Register ra, int bdisp ) ++ { emit_sw2_long( op_blt | is_ra(ra) | is_bdisp(bdisp) ); } ++ inline void Assembler::ble( Register ra, int bdisp ) ++ { emit_sw2_long( op_ble | is_ra(ra) | is_bdisp(bdisp) ); } ++ inline void Assembler::bgt( Register ra, int bdisp ) ++ { emit_sw2_long( op_bgt | is_ra(ra) | is_bdisp(bdisp) ); } ++ inline void Assembler::bge( Register ra, int bdisp ) ++ { emit_sw2_long( op_bge | is_ra(ra) | is_bdisp(bdisp) ); } ++ inline void Assembler::blbc( Register ra, int bdisp ) ++ { emit_sw2_long( op_blbc | is_ra(ra) | is_bdisp(bdisp) ); } ++ inline void Assembler::blbs( Register ra, int bdisp ) ++ { emit_sw2_long( op_blbs | is_ra(ra) | is_bdisp(bdisp) ); } ++ //select ++ inline void Assembler::seleq( Register ra, Register rb,Register r3, Register rc ) ++ { emit_sw2_long( op_seleq | is_ra(ra) | is_rb(rb) | is_r3(r3) | is_rc(rc) ); } ++ inline void Assembler::seleq( Register ra, int lit, Register r3,Register rc ) ++ { emit_sw2_long( op_seleq_l | is_ra(ra) | is_lit(lit) | is_r3(r3) | is_rc(rc) ); } ++ inline void Assembler::selge( Register ra, Register rb,Register r3, Register rc ) ++ { emit_sw2_long( op_selge | is_ra(ra) | is_rb(rb) | is_r3(r3) | is_rc(rc) ); } ++ inline void Assembler::selge( Register ra, int lit, Register r3,Register rc ) ++ { emit_sw2_long( op_selge_l | is_ra(ra) | is_lit(lit) | is_r3(r3) | is_rc(rc) ); } ++ inline void Assembler::selgt( Register ra, Register rb,Register r3, Register rc ) ++ { emit_sw2_long( op_selgt | is_ra(ra) | is_rb(rb) | is_r3(r3) | is_rc(rc) ); } ++ inline void Assembler::selgt( Register ra, int lit, Register r3,Register rc ) ++ { emit_sw2_long( op_selgt_l | is_ra(ra) | is_lit(lit) | is_r3(r3) | is_rc(rc) ); } ++ inline void Assembler::selle( Register ra, Register rb,Register r3, Register rc ) ++ { emit_sw2_long( op_selle | is_ra(ra) | is_rb(rb) | is_r3(r3) | is_rc(rc) ); } ++ inline void Assembler::selle( Register ra, int lit, Register r3,Register rc ) ++ { emit_sw2_long( op_selle_l | is_ra(ra) | is_lit(lit) | is_r3(r3) | is_rc(rc) ); } ++ inline void Assembler::sellt( Register ra, Register rb,Register r3, Register rc ) ++ { emit_sw2_long( op_sellt | is_ra(ra) | is_rb(rb) | is_r3(r3) | is_rc(rc) ); } ++ inline void Assembler::sellt( Register ra, int lit, Register r3,Register rc ) ++ { emit_sw2_long( op_sellt_l | is_ra(ra) | is_lit(lit) | is_r3(r3) | is_rc(rc) ); } ++ inline void Assembler::selne( Register ra, Register rb,Register r3, Register rc ) ++ { emit_sw2_long( op_selne | is_ra(ra) | is_rb(rb) | is_r3(r3) | is_rc(rc) ); } ++ inline void Assembler::selne( Register ra, int lit, Register r3,Register rc ) ++ { emit_sw2_long( op_selne_l | is_ra(ra) | is_lit(lit) | is_r3(r3) | is_rc(rc) ); } ++ inline void Assembler::sellbc( Register ra, Register rb,Register r3, Register rc ) ++ { emit_sw2_long( op_sellbc | is_ra(ra) | is_rb(rb) | is_r3(r3) | is_rc(rc) ); } ++ inline void Assembler::sellbc( Register ra, int lit, Register r3,Register rc ) ++ { emit_sw2_long( op_sellbc_l | is_ra(ra) | is_lit(lit) | is_r3(r3) | is_rc(rc) ); } ++ inline void Assembler::sellbs( Register ra, Register rb,Register r3, Register rc ) ++ { emit_sw2_long( op_sellbs | is_ra(ra) | is_rb(rb) | is_r3(r3) | is_rc(rc) ); } ++ inline void Assembler::sellbs( Register ra, int lit, Register r3,Register rc ) ++ { emit_sw2_long( op_sellbs_l | is_ra(ra) | is_lit(lit) | is_r3(r3) | is_rc(rc) ); } ++ ++ //mov ++ inline void Assembler::fimovs( Register rc, FloatRegister fa ) // For sw4a SQData ++ { emit_sw2_long( op_fimovs | is_fa(fa) | is_rc(rc) ); } ++ inline void Assembler::fimovd( Register rt, FloatRegister fs ) // For sw4a SQData ++ { emit_sw2_long( op_fimovd | is_fa(fs) |is_rc(rt) ); } ++ //priority instructions ++ inline void Assembler::pri_ret( Register ra ) ++ { emit_sw2_long( op_pri_ret | is_ra(ra) ); } ++ inline void Assembler::pri_ld( Register ra, Register rb, int ev6hwdisp ) ++ { emit_sw2_long( op_pri_ld | is_ra(ra) | is_ev6hwdisp(ev6hwdisp) | is_rb(rb) ); } ++ inline void Assembler::pri_st( Register ra, Register rb, int ev6hwdisp ) ++ { emit_sw2_long( op_pri_st | is_ra(ra) | is_ev6hwdisp(ev6hwdisp) | is_rb(rb) ); } ++ // cache control instruction ++ inline void Assembler::s_fillcs( Register rb, int mdisp ) ++ { ldw( R0, rb, mdisp); } ++ inline void Assembler::s_fillde( Register rb, int mdisp ) ++ { ldl( R0, rb, mdisp); } ++ inline void Assembler::fillde( Register rb, int mdisp ) ++ { flds( F31, rb, mdisp); } ++ inline void Assembler::fillde_e( Register rb, int mdisp ) ++ { fldd( F31, rb, mdisp); } ++ inline void Assembler::fillcs( Register rb, int mdisp ) ++ { ldwe( F31, rb, mdisp); } ++ inline void Assembler::fillcs_e( Register rb, int mdisp ) ++ { ldde( F31, rb, mdisp); } ++ inline void Assembler::e_fillcs( Register rb, int mdisp ) ++ { ldse( F31, rb, mdisp); } ++ inline void Assembler::e_fillde( Register rb, int mdisp ) ++ { vlds( F31/*V31*/, rb, mdisp); } ++ inline void Assembler::flushd( Register rb, int mdisp ) ++ { ldbu( R0, rb, mdisp); } ++ inline void Assembler::evictdl( Register rb, int mdisp ) ++ { ldl_u( R0, rb, mdisp); } ++ inline void Assembler::evictdg( Register rb, int mdisp ) ++ { ldhu( R0, rb, mdisp); } ++ ++ //other ++ inline void Assembler::memb( void ) ++ { emit_sw2_long( op_memb); } ++ inline void Assembler::rtc( Register ra, Register rb ) ++ { emit_sw2_long( op_rtc | is_ra(ra) | is_rb(rb) ); } ++ inline void Assembler::rcid( Register ra ) ++ { emit_sw2_long( op_rcid | is_ra(ra) ); } ++ inline void Assembler::halt( void ) ++ { emit_sw2_long( op_halt ); } ++ inline void Assembler::rtid( Register ra ) ++ { emit_sw2_long( op_rtid | is_ra(ra) ); } ++ inline void Assembler::csrr( Register ra, int rpiindex ) ++ { emit_sw2_long( op_csrr | is_ra(ra) | is_rpiindex(rpiindex) ); } ++ inline void Assembler::csrw( Register ra, int rpiindex ) ++ { emit_sw2_long( op_csrw | is_ra(ra) | is_rpiindex(rpiindex) ); } ++ ++ //float ++ //arithmetic instrctions ++ inline void Assembler::fadds( FloatRegister fd, FloatRegister fs, FloatRegister ft ) ++ { emit_sw2_long( op_fadds | is_fa(fs) | is_fb(ft) | is_fc(fd) ); } ++ inline void Assembler::faddd( FloatRegister fd, FloatRegister fs, FloatRegister ft ) ++ { emit_sw2_long( op_faddd | is_fa(fs) | is_fb(ft) | is_fc(fd) ); } ++ inline void Assembler::fsubs( FloatRegister fd, FloatRegister fs, FloatRegister ft ) ++ { emit_sw2_long( op_fsubs | is_fa(fs) | is_fb(ft) | is_fc(fd) ); } ++ inline void Assembler::fsubd( FloatRegister fd, FloatRegister fs, FloatRegister ft ) ++ { emit_sw2_long( op_fsubd | is_fa(fs) | is_fb(ft) | is_fc(fd) ); } ++ inline void Assembler::fmuls( FloatRegister fd, FloatRegister fs, FloatRegister ft ) ++ { emit_sw2_long( op_fmuls | is_fa(fs) | is_fb(ft) | is_fc(fd) ); } ++ inline void Assembler::fmuld( FloatRegister fd, FloatRegister fs, FloatRegister ft ) ++ { emit_sw2_long( op_fmuld | is_fa(fs) | is_fb(ft) | is_fc(fd) ); } ++ inline void Assembler::fdivs( FloatRegister fd, FloatRegister fs, FloatRegister ft ) ++ { emit_sw2_long( op_fdivs | is_fa(fs) | is_fb(ft) | is_fc(fd) ); } ++ inline void Assembler::fdivd( FloatRegister fd, FloatRegister fs, FloatRegister ft ) ++ { emit_sw2_long( op_fdivd | is_fa(fs) | is_fb(ft) | is_fc(fd) ); } ++ inline void Assembler::fsqrts( FloatRegister fc, FloatRegister fb ) ++ { emit_sw2_long( op_fsqrts | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::fsqrtd( FloatRegister fc, FloatRegister fb ) ++ { emit_sw2_long( op_fsqrtd | is_fb(fb) | is_fc(fc) ); } ++ //load&store ++ inline void Assembler::flds( FloatRegister ft, Register rs, int mdisp ) ++ { emit_sw2_long( op_flds | is_fa(ft) | is_mdisp(mdisp) | is_rb(rs) ); } ++ inline void Assembler::fldd( FloatRegister ft, Register rs, int mdisp ) ++ { emit_sw2_long( op_fldd | is_fa(ft) | is_mdisp(mdisp) | is_rb(rs) ); } ++ inline void Assembler::fsts( FloatRegister ft, Register rs, int mdisp ) ++ { emit_sw2_long( op_fsts | is_fa(ft) | is_mdisp(mdisp) | is_rb(rs) ); } ++ inline void Assembler::fstd( FloatRegister fa, Register rb, int mdisp ) ++ { emit_sw2_long( op_fstd | is_fa(fa) | is_mdisp(mdisp) | is_rb(rb) ); } ++ inline void Assembler::fmas( FloatRegister fa,FloatRegister fb,FloatRegister f3, FloatRegister fc ) ++ { emit_sw2_long( op_fmas | is_fa(fa) | is_fb(fb) | is_f3(f3) | is_fc(fc) ); } ++ inline void Assembler::fmad( FloatRegister fa,FloatRegister fb,FloatRegister f3, FloatRegister fc ) ++ { emit_sw2_long( op_fmad | is_fa(fa) | is_fb(fb) | is_f3(f3) | is_fc(fc) ); } ++ inline void Assembler::fmss( FloatRegister fa,FloatRegister fb,FloatRegister f3, FloatRegister fc ) ++ { emit_sw2_long( op_fmss | is_fa(fa) | is_fb(fb) | is_f3(f3) | is_fc(fc) ); } ++ inline void Assembler::fmsd( FloatRegister fa,FloatRegister fb,FloatRegister f3, FloatRegister fc ) ++ { emit_sw2_long( op_fmsd | is_fa(fa) | is_fb(fb) | is_f3(f3) | is_fc(fc) ); } ++ inline void Assembler::fnmas( FloatRegister fa,FloatRegister fb,FloatRegister f3, FloatRegister fc ) ++ { emit_sw2_long( op_fnmas | is_fa(fa) | is_fb(fb) | is_f3(f3) | is_fc(fc) ); } ++ inline void Assembler::fnmad( FloatRegister fa,FloatRegister fb,FloatRegister f3, FloatRegister fc ) ++ { emit_sw2_long( op_fnmad | is_fa(fa) | is_fb(fb) | is_f3(f3) | is_fc(fc) ); } ++ inline void Assembler::fnmss( FloatRegister fa,FloatRegister fb,FloatRegister f3, FloatRegister fc ) ++ { emit_sw2_long( op_fnmss | is_fa(fa) | is_fb(fb) | is_f3(f3) | is_fc(fc) ); } ++ inline void Assembler::fnmsd( FloatRegister fa,FloatRegister fb,FloatRegister f3, FloatRegister fc ) ++ { emit_sw2_long( op_fnmsd | is_fa(fa) | is_fb(fb) | is_f3(f3) | is_fc(fc) ); } ++ //compare ++ // return true if fa eq fb, either flase (including NaN) ++ inline void Assembler::fcmpeq( FloatRegister fc, FloatRegister fa, FloatRegister fb ) ++ { emit_sw2_long( op_fcmpeq | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ // return true if fa le fb, either flase (including NaN) ++ inline void Assembler::fcmple( FloatRegister fc, FloatRegister fa, FloatRegister fb ) ++ { emit_sw2_long( op_fcmple | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ // return true if fa lt fb, either flase (including NaN) ++ inline void Assembler::fcmplt( FloatRegister fc, FloatRegister fa, FloatRegister fb ) ++ { emit_sw2_long( op_fcmplt | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ // return true if either of fa & fb is NaN ++ inline void Assembler::fcmpun( FloatRegister fc, FloatRegister fa, FloatRegister fb ) ++ { emit_sw2_long( op_fcmpun | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ //branch ++ inline void Assembler::fbeq( FloatRegister fa, int bdisp ) ++ { emit_sw2_long( op_fbeq | is_fa(fa) | is_bdisp(bdisp) ); } ++ inline void Assembler::fbne( FloatRegister fa, int bdisp ) ++ { emit_sw2_long( op_fbne | is_fa(fa) | is_bdisp(bdisp) ); } ++ inline void Assembler::fblt( FloatRegister fa, int bdisp ) ++ { emit_sw2_long( op_fblt | is_fa(fa) | is_bdisp(bdisp) ); } ++ inline void Assembler::fble( FloatRegister fa, int bdisp ) ++ { emit_sw2_long( op_fble | is_fa(fa) | is_bdisp(bdisp) ); } ++ inline void Assembler::fbgt( FloatRegister fa, int bdisp ) ++ { emit_sw2_long( op_fbgt | is_fa(fa) | is_bdisp(bdisp) ); } ++ inline void Assembler::fbge( FloatRegister fa, int bdisp ) ++ { emit_sw2_long( op_fbge | is_fa(fa) | is_bdisp(bdisp) ); } ++ //select ++ inline void Assembler::fseleq( FloatRegister fa,FloatRegister fb,FloatRegister f3, FloatRegister fc ) ++ { emit_sw2_long( op_fseleq | is_fa(fa) | is_fb(fb) | is_f3(f3) | is_fc(fc) ); } ++ inline void Assembler::fselne( FloatRegister fa,FloatRegister fb,FloatRegister f3, FloatRegister fc ) ++ { emit_sw2_long( op_fselne | is_fa(fa) | is_fb(fb) | is_f3(f3) | is_fc(fc) ); } ++ inline void Assembler::fsellt( FloatRegister fa,FloatRegister fb,FloatRegister f3, FloatRegister fc ) ++ { emit_sw2_long( op_fsellt | is_fa(fa) | is_fb(fb) | is_f3(f3) | is_fc(fc) ); } ++ inline void Assembler::fselle( FloatRegister fa,FloatRegister fb,FloatRegister f3, FloatRegister fc ) ++ { emit_sw2_long( op_fselle | is_fa(fa) | is_fb(fb) | is_f3(f3) | is_fc(fc) ); } ++ inline void Assembler::fselgt( FloatRegister fa,FloatRegister fb,FloatRegister f3, FloatRegister fc ) ++ { emit_sw2_long( op_fselgt | is_fa(fa) | is_fb(fb) | is_f3(f3) | is_fc(fc) ); } ++ inline void Assembler::fselge( FloatRegister fa,FloatRegister fb,FloatRegister f3, FloatRegister fc ) ++ { emit_sw2_long( op_fselge | is_fa(fa) | is_fb(fb) | is_f3(f3) | is_fc(fc) ); } ++ //mov ++ inline void Assembler::fcpys( FloatRegister fc, FloatRegister fa, FloatRegister fb ) ++ { emit_sw2_long( op_fcpys | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::fmovd( FloatRegister fd, FloatRegister fs ) ++ { emit_sw2_long( op_fcpys | is_fa(fs) | is_fb(fs) | is_fc(fd) ); } ++ inline void Assembler::fmovs( FloatRegister fd, FloatRegister fs ) ++ { emit_sw2_long( op_fcpys | is_fa(fs) | is_fb(fs) | is_fc(fd) ); } ++ inline void Assembler::fcpyse( FloatRegister fc, FloatRegister fa, FloatRegister fb ) ++ { emit_sw2_long( op_fcpyse | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::fcpysn( FloatRegister fc, FloatRegister fa, FloatRegister fb ) ++ { emit_sw2_long( op_fcpysn | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::ifmovs( FloatRegister fc, Register ra ) ++ { emit_sw2_long( op_ifmovs | is_ra(ra) | is_fc(fc) ); } ++ inline void Assembler::ifmovd( FloatRegister fc, Register ra ) ++ { emit_sw2_long( op_ifmovd | is_ra(ra) | is_fc(fc) ); } ++ //cmov ++ inline void Assembler::cmovdl( Register rc, FloatRegister fb ) ++ {sw4_only(); emit_sw2_long( op_cmovdl | is_fb(fb) | is_rc(rc) ); } ++ inline void Assembler::cmovdl_g( Register rc, FloatRegister fb ) ++ {sw4_only(); emit_sw2_long( op_cmovdl_g | is_fb(fb) | is_rc(rc) ); } ++ inline void Assembler::cmovdl_p( Register rc, FloatRegister fb ) ++ {sw4_only(); emit_sw2_long( op_cmovdl_p | is_fb(fb) | is_rc(rc) ); } ++ inline void Assembler::cmovdl_z( Register rc, FloatRegister fb ) ++ {sw4_only(); emit_sw2_long( op_cmovdl_z | is_fb(fb) | is_rc(rc) ); } ++ inline void Assembler::cmovdl_n( Register rc, FloatRegister fb ) ++ {sw4_only(); emit_sw2_long( op_cmovdl_n | is_fb(fb) | is_rc(rc) ); } ++ ++ inline void Assembler::cmovdlu( Register rc, FloatRegister fb ) ++ {sw4_only(); emit_sw2_long( op_cmovdlu | is_fb(fb) | is_rc(rc) ); } ++ inline void Assembler::cmovdlu_g( Register rc, FloatRegister fb ) ++ {sw4_only(); emit_sw2_long( op_cmovdlu_g | is_fb(fb) | is_rc(rc) ); } ++ inline void Assembler::cmovdlu_p( Register rc, FloatRegister fb ) ++ {sw4_only(); emit_sw2_long( op_cmovdlu_p | is_fb(fb) | is_rc(rc) ); } ++ inline void Assembler::cmovdlu_z( Register rc, FloatRegister fb ) ++ {sw4_only(); emit_sw2_long( op_cmovdlu_z | is_fb(fb) | is_rc(rc) ); } ++ inline void Assembler::cmovdlu_n( Register rc, FloatRegister fb ) ++ {sw4_only(); emit_sw2_long( op_cmovdlu_n | is_fb(fb) | is_rc(rc) ); } ++ ++ inline void Assembler::cmovdw( Register rc, FloatRegister fb ) ++ {sw4_only(); emit_sw2_long( op_cmovdw | is_fb(fb) | is_rc(rc) ); } ++ inline void Assembler::cmovdw_g( Register rc, FloatRegister fb ) ++ {sw4_only(); emit_sw2_long( op_cmovdw_g | is_fb(fb) | is_rc(rc) ); } ++ inline void Assembler::cmovdw_p( Register rc, FloatRegister fb ) ++ {sw4_only(); emit_sw2_long( op_cmovdw_p | is_fb(fb) | is_rc(rc) ); } ++ inline void Assembler::cmovdw_z( Register rc, FloatRegister fb ) ++ {sw4_only(); emit_sw2_long( op_cmovdw_z | is_fb(fb) | is_rc(rc) ); } ++ inline void Assembler::cmovdw_n( Register rc, FloatRegister fb ) ++ {sw4_only(); emit_sw2_long( op_cmovdw_n | is_fb(fb) | is_rc(rc) ); } ++ ++ inline void Assembler::cmovdwu( Register rc, FloatRegister fb ) ++ {sw4_only(); emit_sw2_long( op_cmovdwu | is_fb(fb) | is_rc(rc) ); } ++ inline void Assembler::cmovdwu_g( Register rc, FloatRegister fb ) ++ {sw4_only(); emit_sw2_long( op_cmovdwu_g | is_fb(fb) | is_rc(rc) ); } ++ inline void Assembler::cmovdwu_p( Register rc, FloatRegister fb ) ++ {sw4_only(); emit_sw2_long( op_cmovdwu_p | is_fb(fb) | is_rc(rc) ); } ++ inline void Assembler::cmovdwu_z( Register rc, FloatRegister fb ) ++ {sw4_only(); emit_sw2_long( op_cmovdwu_z | is_fb(fb) | is_rc(rc) ); } ++ inline void Assembler::cmovdwu_n( Register rc, FloatRegister fb ) ++ {sw4_only(); emit_sw2_long( op_cmovdwu_n | is_fb(fb) | is_rc(rc) ); } ++ ++ inline void Assembler::cmovls( FloatRegister fc, Register rb ) ++ {sw4_only(); emit_sw2_long( op_cmovls | is_rb(rb) | is_fc(fc) ); } ++ inline void Assembler::cmovld( FloatRegister fc, Register rb ) ++ {sw4_only(); emit_sw2_long( op_cmovld | is_rb(rb) | is_fc(fc) ); } ++ inline void Assembler::cmovuls( FloatRegister fc, Register rb ) ++ {sw4_only(); emit_sw2_long( op_cmovuls | is_rb(rb) | is_fc(fc) ); } ++ inline void Assembler::cmovuld( FloatRegister fc, Register rb ) ++ {sw4_only(); emit_sw2_long( op_cmovuld | is_rb(rb) | is_fc(fc) ); } ++ inline void Assembler::cmovws( FloatRegister fc, Register rb ) ++ {sw4_only(); emit_sw2_long( op_cmovws | is_rb(rb) | is_fc(fc) ); } ++ inline void Assembler::cmovwd( FloatRegister fc, Register rb ) ++ {sw4_only(); emit_sw2_long( op_cmovwd | is_rb(rb) | is_fc(fc) ); } ++ inline void Assembler::cmovuws( FloatRegister fc, Register rb ) ++ {sw4_only(); emit_sw2_long( op_cmovuws | is_rb(rb) | is_fc(fc) ); } ++ inline void Assembler::cmovuwd( FloatRegister fc, Register rb ) ++ {sw4_only(); emit_sw2_long( op_cmovuwd | is_rb(rb) | is_fc(fc) ); } ++ //fcvt ++ inline void Assembler::fcvtsd( FloatRegister fc, FloatRegister fb ) ++ { emit_sw2_long( op_fcvtsd | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::fcvtds( FloatRegister fc, FloatRegister fb ) ++ { emit_sw2_long( op_fcvtds | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::fcvtdl_g( FloatRegister fc, FloatRegister fb ) ++ { emit_sw2_long( op_fcvtdl_g | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::fcvtdl_p( FloatRegister fc, FloatRegister fb ) ++ { emit_sw2_long( op_fcvtdl_p | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::fcvtdl_z( FloatRegister fc, FloatRegister fb ) ++ { emit_sw2_long( op_fcvtdl_z | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::fcvtdl_n( FloatRegister fc, FloatRegister fb ) ++ { emit_sw2_long( op_fcvtdl_n | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::fcvtdl( FloatRegister fc, FloatRegister fb ) ++ { emit_sw2_long( op_fcvtdl | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::fcvtwl( FloatRegister fc, FloatRegister fb ) ++ { emit_sw2_long( op_fcvtwl | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::fcvtlw( FloatRegister fc, FloatRegister fb ) ++ { emit_sw2_long( op_fcvtlw | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::fcvtls( FloatRegister fc, FloatRegister fb ) ++ { emit_sw2_long( op_fcvtls | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::fcvtld( FloatRegister fc, FloatRegister fb ) ++ { emit_sw2_long( op_fcvtld | is_fb(fb) | is_fc(fc) ); } ++ //set FPCR ++ inline void Assembler::rfpcr( FloatRegister fa) ++ { emit_sw2_long( op_rfpcr | is_fa(fa) ); } ++ inline void Assembler::wfpcr( FloatRegister fa) ++ { emit_sw2_long( op_wfpcr | is_fa(fa) ); } ++ inline void Assembler::setfpec0() { emit_sw2_long( op_setfpec0 ); } ++ inline void Assembler::setfpec1() { emit_sw2_long( op_setfpec1 ); } ++ inline void Assembler::setfpec2() { emit_sw2_long( op_setfpec2 ); } ++ inline void Assembler::setfpec3() { emit_sw2_long( op_setfpec3 ); } ++ ++ //SIMD ++ inline void Assembler::ldwe( FloatRegister fa, Register rb, int mdisp ) ++ { emit_sw2_long( op_ldwe | is_fa(fa) | is_mdisp(mdisp) | is_rb(rb) ); } ++ inline void Assembler::ldse( FloatRegister fa, Register rb, int mdisp ) ++ { emit_sw2_long( op_ldse | is_fa(fa) | is_mdisp(mdisp) | is_rb(rb) ); } ++ inline void Assembler::ldde( FloatRegister fa, Register rb, int mdisp ) ++ { emit_sw2_long( op_ldde | is_fa(fa) | is_mdisp(mdisp) | is_rb(rb) ); } ++ inline void Assembler::vlds( FloatRegister fa, Register rb, int mdisp ) ++ { emit_sw2_long( op_vlds | is_fa(fa) | is_mdisp(mdisp) | is_rb(rb) ); } ++ inline void Assembler::vldd( FloatRegister fa, Register rb, int mdisp ) ++ { emit_sw2_long( op_vldd | is_fa(fa) | is_mdisp(mdisp) | is_rb(rb) ); } ++ inline void Assembler::vsts( FloatRegister fa, Register rb, int mdisp ) ++ { emit_sw2_long( op_vsts | is_fa(fa) | is_mdisp(mdisp) | is_rb(rb) ); } ++ inline void Assembler::vstd( FloatRegister fa, Register rb, int mdisp ) ++ { emit_sw2_long( op_vstd | is_fa(fa) | is_mdisp(mdisp) | is_rb(rb) ); } ++ inline void Assembler::vaddw( FloatRegister fc, FloatRegister fa, FloatRegister fb ) ++ { emit_sw2_long( op_vaddw | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vaddw( FloatRegister fc, FloatRegister fa, int lit ) ++ { emit_sw2_long( op_vaddw_l | is_fa(fa) | is_lit(lit) | is_fc(fc) ); } ++ inline void Assembler::vsubw( FloatRegister fc, FloatRegister fa, FloatRegister fb ) ++ { emit_sw2_long( op_vsubw | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vsubw( FloatRegister fc, FloatRegister fa, int lit ) ++ { emit_sw2_long( op_vsubw_l | is_fa(fa) | is_lit(lit) | is_fc(fc) ); } ++ ++ inline void Assembler::vcmpgew( FloatRegister fc, FloatRegister fa, FloatRegister fb ) ++ { emit_sw2_long( op_vcmpgew | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vcmpgew( FloatRegister fc, FloatRegister fa, int lit ) ++ { emit_sw2_long( op_vcmpgew_l | is_fa(fa) | is_lit(lit) | is_fc(fc) ); } ++ inline void Assembler::vcmpeqw( FloatRegister fc, FloatRegister fa, FloatRegister fb ) ++ { emit_sw2_long( op_vcmpeqw | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vcmpeqw( FloatRegister fc, FloatRegister fa, int lit ) ++ { emit_sw2_long( op_vcmpeqw_l | is_fa(fa) | is_lit(lit) | is_fc(fc) ); } ++ inline void Assembler::vcmplew( FloatRegister fc, FloatRegister fa, FloatRegister fb ) ++ { emit_sw2_long( op_vcmplew | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vcmplew( FloatRegister fc, FloatRegister fa, int lit ) ++ { emit_sw2_long( op_vcmplew_l | is_fa(fa) | is_lit(lit) | is_fc(fc) ); } ++ inline void Assembler::vcmpltw( FloatRegister fc, FloatRegister fa, FloatRegister fb ) ++ { emit_sw2_long( op_vcmpltw | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vcmpltw( FloatRegister fc, FloatRegister fa, int lit ) ++ { emit_sw2_long( op_vcmpltw_l | is_fa(fa) | is_lit(lit) | is_fc(fc) ); } ++ inline void Assembler::vcmpulew( FloatRegister fc, FloatRegister fa, FloatRegister fb ) ++ { emit_sw2_long( op_vcmpulew | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vcmpulew( FloatRegister fc, FloatRegister fa, int lit ) ++ { emit_sw2_long( op_vcmpulew_l | is_fa(fa) | is_lit(lit) | is_fc(fc) ); } ++ inline void Assembler::vcmpultw( FloatRegister fc, FloatRegister fa, FloatRegister fb ) ++ { emit_sw2_long( op_vcmpultw | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vcmpultw( FloatRegister fc, FloatRegister fa, int lit ) ++ { emit_sw2_long( op_vcmpultw_l | is_fa(fa) | is_lit(lit) | is_fc(fc) ); } ++ ++ inline void Assembler::vsllw( FloatRegister fc, FloatRegister fa, FloatRegister fb ) ++ { emit_sw2_long( op_vsllw | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vsllw( FloatRegister fc, FloatRegister fa, int lit ) ++ { emit_sw2_long( op_vsllw_l | is_fa(fa) | is_lit(lit) | is_fc(fc) ); } ++ inline void Assembler::vsrlw( FloatRegister fc, FloatRegister fa, FloatRegister fb ) ++ { emit_sw2_long( op_vsrlw | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vsrlw( FloatRegister fc, FloatRegister fa, int lit ) ++ { emit_sw2_long( op_vsrlw_l | is_fa(fa) | is_lit(lit) | is_fc(fc) ); } ++ inline void Assembler::vsraw( FloatRegister fc, FloatRegister fa, FloatRegister fb ) ++ { emit_sw2_long( op_vsraw | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vsraw( FloatRegister fc, FloatRegister fa, int lit ) ++ { emit_sw2_long( op_vsraw_l | is_fa(fa) | is_lit(lit) | is_fc(fc) ); } ++ inline void Assembler::vrolw( FloatRegister fc, FloatRegister fa, FloatRegister fb ) ++ { emit_sw2_long( op_vrolw | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vrolw( FloatRegister fc, FloatRegister fa, int lit ) ++ { emit_sw2_long( op_vrolw_l | is_fa(fa) | is_lit(lit) | is_fc(fc) ); } ++ inline void Assembler::sllow( FloatRegister fc, FloatRegister fa, FloatRegister fb ) ++ { emit_sw2_long( op_sllow | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::sllow( FloatRegister fc, FloatRegister fa, int lit ) ++ { emit_sw2_long( op_sllow_l | is_fa(fa) | is_lit(lit) | is_fc(fc) ); } ++ inline void Assembler::srlow( FloatRegister fc, FloatRegister fa, FloatRegister fb ) ++ { emit_sw2_long( op_srlow | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::srlow( FloatRegister fc, FloatRegister fa, int lit ) ++ { emit_sw2_long( op_srlow_l | is_fa(fa) | is_lit(lit) | is_fc(fc) ); } ++ ++ inline void Assembler::vaddl( FloatRegister fc, FloatRegister fa, FloatRegister fb ) ++ { emit_sw2_long( op_vaddl | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vaddl( FloatRegister fc, FloatRegister fa, int lit ) ++ { emit_sw2_long( op_vaddl_l | is_fa(fa) | is_lit(lit) | is_fc(fc) ); } ++ inline void Assembler::vsubl( FloatRegister fc, FloatRegister fa, FloatRegister fb ) ++ { emit_sw2_long( op_vsubl | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vsubl( FloatRegister fc, FloatRegister fa, int lit ) ++ { emit_sw2_long( op_vsubl_l | is_fa(fa) | is_lit(lit) | is_fc(fc) ); } ++ ++ ++ inline void Assembler::ctpopow( FloatRegister fc, FloatRegister fa ) ++ { emit_sw2_long( op_ctpopow | is_fa(fa) | is_fc(fc) ); } ++ inline void Assembler::ctlzow( FloatRegister fc, FloatRegister fa ) ++ { emit_sw2_long( op_ctlzow | is_fa(fa) | is_fc(fc) ); } ++ ++ inline void Assembler::vucaddw( FloatRegister fc, FloatRegister fa, FloatRegister fb ) ++ { emit_sw2_long( op_vucaddw | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vucaddw( FloatRegister fc, FloatRegister fa, int lit ) ++ { emit_sw2_long( op_vucaddw_l | is_fa(fa) | is_lit(lit) | is_fc(fc) ); } ++ inline void Assembler::vucsubw( FloatRegister fc, FloatRegister fa, FloatRegister fb ) ++ { emit_sw2_long( op_vucsubw | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vucsubw( FloatRegister fc, FloatRegister fa, int lit ) ++ { emit_sw2_long( op_vucsubw_l | is_fa(fa) | is_lit(lit) | is_fc(fc) ); } ++ inline void Assembler::vucaddh( FloatRegister fc, FloatRegister fa, FloatRegister fb ) ++ { emit_sw2_long( op_vucaddh | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vucaddh( FloatRegister fc, FloatRegister fa, int lit ) ++ { emit_sw2_long( op_vucaddh_l | is_fa(fa) | is_lit(lit) | is_fc(fc) ); } ++ inline void Assembler::vucsubh( FloatRegister fc, FloatRegister fa, FloatRegister fb ) ++ { emit_sw2_long( op_vucsubh | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vucsubh( FloatRegister fc, FloatRegister fa, int lit ) ++ { emit_sw2_long( op_vucsubh_l | is_fa(fa) | is_lit(lit) | is_fc(fc) ); } ++ inline void Assembler::vucaddb( FloatRegister fc, FloatRegister fa, FloatRegister fb ) ++ { emit_sw2_long( op_vucaddb | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vucaddb( FloatRegister fc, FloatRegister fa, int lit ) ++ { emit_sw2_long( op_vucaddb_l | is_fa(fa) | is_lit(lit) | is_fc(fc) ); } ++ inline void Assembler::vucsubb( FloatRegister fc, FloatRegister fa, FloatRegister fb ) ++ { emit_sw2_long( op_vucsubb | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vucsubb( FloatRegister fc, FloatRegister fa, int lit ) ++ { emit_sw2_long( op_vucsubb_l | is_fa(fa) | is_lit(lit) | is_fc(fc) ); } ++ ++ inline void Assembler::vseleqw( FloatRegister fa,FloatRegister fb,FloatRegister f3, FloatRegister fc ) ++ { emit_sw2_long( op_vseleqw | is_fa(fa) | is_fb(fb) | is_f3(f3) | is_fc(fc) ); } ++ inline void Assembler::vseleqw( FloatRegister fa,FloatRegister fb, int fmalit, FloatRegister fc ) ++ { emit_sw2_long( op_vseleqw_l | is_fa(fa) | is_fb(fb) | is_fmalit(fmalit) | is_fc(fc) ); } ++ inline void Assembler::vsellbcw( FloatRegister fa,FloatRegister fb,FloatRegister f3, FloatRegister fc ) ++ { emit_sw2_long( op_vsellbcw | is_fa(fa) | is_fb(fb) | is_f3(f3) | is_fc(fc) ); } ++ inline void Assembler::vsellbcw( FloatRegister fa,FloatRegister fb, int fmalit, FloatRegister fc ) ++ { emit_sw2_long( op_vsellbcw_l | is_fa(fa) | is_fb(fb) | is_fmalit(fmalit) | is_fc(fc) ); } ++ inline void Assembler::vselltw( FloatRegister fa,FloatRegister fb,FloatRegister f3, FloatRegister fc ) ++ { emit_sw2_long( op_vselltw | is_fa(fa) | is_fb(fb) | is_f3(f3) | is_fc(fc) ); } ++ inline void Assembler::vselltw( FloatRegister fa,FloatRegister fb, int fmalit, FloatRegister fc ) ++ { emit_sw2_long( op_vselltw_l | is_fa(fa) | is_fb(fb) | is_fmalit(fmalit) | is_fc(fc) ); } ++ inline void Assembler::vsellew( FloatRegister fa,FloatRegister fb,FloatRegister f3, FloatRegister fc ) ++ { emit_sw2_long( op_vsellew | is_fa(fa) | is_fb(fb) | is_f3(f3) | is_fc(fc) ); } ++ inline void Assembler::vsellew( FloatRegister fa,FloatRegister fb, int fmalit, FloatRegister fc ) ++ { emit_sw2_long( op_vsellew_l | is_fa(fa) | is_fb(fb) | is_fmalit(fmalit) | is_fc(fc) ); } ++ ++ inline void Assembler::vadds( FloatRegister fd, FloatRegister fs, FloatRegister ft ) ++ { emit_sw2_long( op_vadds | is_fa(fs) | is_fb(ft) | is_fc(fd) ); } ++ inline void Assembler::vaddd( FloatRegister fd, FloatRegister fs, FloatRegister ft ) ++ { emit_sw2_long( op_vaddd | is_fa(fs) | is_fb(ft) | is_fc(fd) ); } ++ inline void Assembler::vsubs( FloatRegister fd, FloatRegister fs, FloatRegister ft ) ++ { emit_sw2_long( op_vsubs | is_fa(fs) | is_fb(ft) | is_fc(fd) ); } ++ inline void Assembler::vsubd( FloatRegister fd, FloatRegister fs, FloatRegister ft ) ++ { emit_sw2_long( op_vsubd | is_fa(fs) | is_fb(ft) | is_fc(fd) ); } ++ inline void Assembler::vmuls( FloatRegister fd, FloatRegister fs, FloatRegister ft ) ++ { emit_sw2_long( op_vmuls | is_fa(fs) | is_fb(ft) | is_fc(fd) ); } ++ inline void Assembler::vmuld( FloatRegister fd, FloatRegister fs, FloatRegister ft ) ++ { emit_sw2_long( op_vmuld | is_fa(fs) | is_fb(ft) | is_fc(fd) ); } ++ inline void Assembler::vdivs( FloatRegister fd, FloatRegister fs, FloatRegister ft ) ++ { emit_sw2_long( op_vdivs | is_fa(fs) | is_fb(ft) | is_fc(fd) ); } ++ inline void Assembler::vdivd( FloatRegister fd, FloatRegister fs, FloatRegister ft ) ++ { emit_sw2_long( op_vdivd | is_fa(fs) | is_fb(ft) | is_fc(fd) ); } ++ inline void Assembler::vsqrts( FloatRegister fc, FloatRegister fb ) ++ { emit_sw2_long( op_vsqrts | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vsqrtd( FloatRegister fc, FloatRegister fb ) ++ { emit_sw2_long( op_vsqrtd | is_fb(fb) | is_fc(fc) ); } ++ ++ inline void Assembler::vfcmpeq( FloatRegister fc, FloatRegister fa, FloatRegister fb ) ++ { emit_sw2_long( op_vfcmpeq | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vfcmple( FloatRegister fc, FloatRegister fa, FloatRegister fb ) ++ { emit_sw2_long( op_vfcmple | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vfcmplt( FloatRegister fc, FloatRegister fa, FloatRegister fb ) ++ { emit_sw2_long( op_vfcmplt | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vfcmpun( FloatRegister fc, FloatRegister fa, FloatRegister fb ) ++ { emit_sw2_long( op_vfcmpun | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vcpys( FloatRegister fc, FloatRegister fa, FloatRegister fb ) ++ { emit_sw2_long( op_vcpys | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vfmov( FloatRegister fc, FloatRegister fa ) ++ { emit_sw2_long( op_vcpys | is_fa(fa) | is_fb(fa) | is_fc(fc) ); } ++ inline void Assembler::vcpyse( FloatRegister fc, FloatRegister fa, FloatRegister fb ) ++ { emit_sw2_long( op_vcpyse | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vcpysn( FloatRegister fc, FloatRegister fa, FloatRegister fb ) ++ { emit_sw2_long( op_vcpysn | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ ++ inline void Assembler::vmas( FloatRegister fa,FloatRegister fb,FloatRegister f3, FloatRegister fc ) ++ { emit_sw2_long( op_vmas | is_fa(fa) | is_fb(fb) | is_f3(f3) | is_fc(fc) ); } ++ inline void Assembler::vmad( FloatRegister fa,FloatRegister fb,FloatRegister f3, FloatRegister fc ) ++ { emit_sw2_long( op_vmad | is_fa(fa) | is_fb(fb) | is_f3(f3) | is_fc(fc) ); } ++ inline void Assembler::vmss( FloatRegister fa,FloatRegister fb,FloatRegister f3, FloatRegister fc ) ++ { emit_sw2_long( op_vmss | is_fa(fa) | is_fb(fb) | is_f3(f3) | is_fc(fc) ); } ++ inline void Assembler::vmsd( FloatRegister fa,FloatRegister fb,FloatRegister f3, FloatRegister fc ) ++ { emit_sw2_long( op_vmsd | is_fa(fa) | is_fb(fb) | is_f3(f3) | is_fc(fc) ); } ++ inline void Assembler::vnmas( FloatRegister fa,FloatRegister fb,FloatRegister f3, FloatRegister fc ) ++ { emit_sw2_long( op_vnmas | is_fa(fa) | is_fb(fb) | is_f3(f3) | is_fc(fc) ); } ++ inline void Assembler::vnmad( FloatRegister fa,FloatRegister fb,FloatRegister f3, FloatRegister fc ) ++ { emit_sw2_long( op_vnmad | is_fa(fa) | is_fb(fb) | is_f3(f3) | is_fc(fc) ); } ++ inline void Assembler::vnmss( FloatRegister fa,FloatRegister fb,FloatRegister f3, FloatRegister fc ) ++ { emit_sw2_long( op_vnmss | is_fa(fa) | is_fb(fb) | is_f3(f3) | is_fc(fc) ); } ++ inline void Assembler::vnmsd( FloatRegister fa,FloatRegister fb,FloatRegister f3, FloatRegister fc ) ++ { emit_sw2_long( op_vnmsd | is_fa(fa) | is_fb(fb) | is_f3(f3) | is_fc(fc) ); } ++ ++ inline void Assembler::vfseleq( FloatRegister fa,FloatRegister fb,FloatRegister f3, FloatRegister fc ) ++ { emit_sw2_long( op_vfseleq | is_fa(fa) | is_fb(fb) | is_f3(f3) | is_fc(fc) ); } ++ inline void Assembler::vfsellt( FloatRegister fa,FloatRegister fb,FloatRegister f3, FloatRegister fc ) ++ { emit_sw2_long( op_vfsellt | is_fa(fa) | is_fb(fb) | is_f3(f3) | is_fc(fc) ); } ++ inline void Assembler::vfselle( FloatRegister fa,FloatRegister fb,FloatRegister f3, FloatRegister fc ) ++ { emit_sw2_long( op_vfselle | is_fa(fa) | is_fb(fb) | is_f3(f3) | is_fc(fc) ); } ++ ++ inline void Assembler::vinsw( FloatRegister fa,FloatRegister fb, int fmalit, FloatRegister fc ) ++ { emit_sw2_long( op_vinsw_l | is_fa(fa) | is_fb(fb) | is_fmalit(fmalit) | is_fc(fc) ); } ++ inline void Assembler::vinsf( FloatRegister fa,FloatRegister fb, int fmalit, FloatRegister fc ) ++ { emit_sw2_long( op_vinsf_l | is_fa(fa) | is_fb(fb) | is_fmalit(fmalit) | is_fc(fc) ); } ++ inline void Assembler::vextw( FloatRegister fa, int fmalit, FloatRegister fc) ++ { emit_sw2_long( op_vextw_l | is_fa(fa) | is_fmalit(fmalit) | is_fc(fc) ); } ++ inline void Assembler::vextf( FloatRegister fa, int fmalit, FloatRegister fc) ++ { emit_sw2_long( op_vextf_l | is_fa(fa) | is_fmalit(fmalit) | is_fc(fc) ); } ++ inline void Assembler::vcpyw( FloatRegister fa, FloatRegister fc) ++ { emit_sw2_long( op_vcpyw | is_fa(fa) | is_fc(fc) ); } ++ inline void Assembler::vcpyf( FloatRegister fa, FloatRegister fc) ++ { emit_sw2_long( op_vcpyf | is_fa(fa) | is_fc(fc) ); } ++ inline void Assembler::vconw( FloatRegister fa,FloatRegister fb,FloatRegister f3, FloatRegister fc ) ++ { emit_sw2_long( op_vconw | is_fa(fa) | is_fb(fb) | is_f3(f3) | is_fc(fc) ); } ++ inline void Assembler::vshfw( FloatRegister fa,FloatRegister fb,FloatRegister f3, FloatRegister fc ) ++ { emit_sw2_long( op_vshfw | is_fa(fa) | is_fb(fb) | is_f3(f3) | is_fc(fc) ); } ++ inline void Assembler::vcons( FloatRegister fa,FloatRegister fb,FloatRegister f3, FloatRegister fc ) ++ { emit_sw2_long( op_vcons | is_fa(fa) | is_fb(fb) | is_f3(f3) | is_fc(fc) ); } ++ inline void Assembler::vcond( FloatRegister fa,FloatRegister fb,FloatRegister f3, FloatRegister fc ) ++ { emit_sw2_long( op_vcond | is_fa(fa) | is_fb(fb) | is_f3(f3) | is_fc(fc) ); } ++ inline void Assembler::vldw_u( FloatRegister fa, Register rb, int atmdisp )//load&store ++ { emit_sw2_long( op_vldw_u | is_fa(fa) | is_atmdisp(atmdisp) | is_rb(rb) ); } ++ inline void Assembler::vstw_u( FloatRegister fa, Register rb, int atmdisp ) ++ { emit_sw2_long( op_vstw_u | is_fa(fa) | is_atmdisp(atmdisp) | is_rb(rb) ); } ++ inline void Assembler::vlds_u( FloatRegister fa, Register rb, int atmdisp ) ++ { emit_sw2_long( op_vsts_u | is_fa(fa) | is_atmdisp(atmdisp) | is_rb(rb) ); } ++ inline void Assembler::vsts_u( FloatRegister fa, Register rb, int atmdisp ) ++ { emit_sw2_long( op_vsts_u | is_fa(fa) | is_atmdisp(atmdisp) | is_rb(rb) ); } ++ inline void Assembler::vldd_u( FloatRegister fa, Register rb, int atmdisp ) ++ { emit_sw2_long( op_vldd_u | is_fa(fa) | is_atmdisp(atmdisp) | is_rb(rb) ); } ++ inline void Assembler::vstd_u( FloatRegister fa, Register rb, int atmdisp ) ++ { emit_sw2_long( op_vstd_u | is_fa(fa) | is_atmdisp(atmdisp) | is_rb(rb) ); } ++ inline void Assembler::vstw_ul( FloatRegister fa, Register rb, int atmdisp ) ++ { emit_sw2_long( op_vstw_ul | is_fa(fa) | is_atmdisp(atmdisp) | is_rb(rb) ); } ++ inline void Assembler::vstw_uh( FloatRegister fa, Register rb, int atmdisp ) ++ { emit_sw2_long( op_vstw_uh | is_fa(fa) | is_atmdisp(atmdisp) | is_rb(rb) ); } ++ inline void Assembler::vsts_ul( FloatRegister fa, Register rb, int atmdisp ) ++ { emit_sw2_long( op_vsts_ul | is_fa(fa) | is_atmdisp(atmdisp) | is_rb(rb) ); } ++ inline void Assembler::vsts_uh( FloatRegister fa, Register rb, int atmdisp ) ++ { emit_sw2_long( op_vsts_uh | is_fa(fa) | is_atmdisp(atmdisp) | is_rb(rb) ); } ++ inline void Assembler::vstd_ul( FloatRegister fa, Register rb, int atmdisp ) ++ { emit_sw2_long( op_vstd_ul | is_fa(fa) | is_atmdisp(atmdisp) | is_rb(rb) ); } ++ inline void Assembler::vstd_uh( FloatRegister fa, Register rb, int atmdisp ) ++ { emit_sw2_long( op_vstd_uh | is_fa(fa) | is_atmdisp(atmdisp) | is_rb(rb) ); } ++ ++ inline void Assembler::vlog( int vlog ,FloatRegister fa,FloatRegister fb,FloatRegister f3, FloatRegister fc ) ++ { emit_sw2_long( op_vlog | is_vlog_h(vlog) | is_vlog_l(vlog) | is_fa(fa) | is_fb(fb) | is_f3(f3) | is_fc(fc) ); } ++ inline void Assembler::vbisw( FloatRegister fc , FloatRegister fa , FloatRegister fb ) ++ { emit_sw2_long( op_vbisw | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vxorw( FloatRegister fc , FloatRegister fa , FloatRegister fb ) ++ { emit_sw2_long( op_vxorw | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vandw( FloatRegister fc , FloatRegister fa , FloatRegister fb ) ++ { emit_sw2_long( op_vandw | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::veqvw( FloatRegister fc , FloatRegister fa , FloatRegister fb ) ++ { emit_sw2_long( op_veqvw | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vornotw( FloatRegister fc , FloatRegister fa , FloatRegister fb ) ++ { emit_sw2_long( op_vornotw | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vbicw( FloatRegister fc , FloatRegister fa , FloatRegister fb ) ++ { emit_sw2_long( op_vbicw | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ ++ ++ // SW8A instructions ++ inline void Assembler::imemb( void ) ++ { sw3_only(); emit_sw2_long( op_imemb); } ++ inline void Assembler::wmemb( void ) ++ { sw4_only(); emit_sw2_long( op_wmemb); } ++ inline void Assembler::csrws( Register ra, int rpiindex ) ++ { sw4_only(); emit_sw2_long( op_csrws | is_ra(ra) | is_rpiindex(rpiindex) ); } ++ inline void Assembler::csrwc( Register ra, int rpiindex ) ++ { sw4_only(); emit_sw2_long( op_csrwc | is_ra(ra) | is_rpiindex(rpiindex) ); } ++ inline void Assembler::divw( Register ra, Register rb, Register rc ) ++ { sw4_only(); emit_sw2_long( op_divw | is_ra(ra) | is_rb(rb) | is_rc(rc) ); } ++ inline void Assembler::udivw( Register ra, Register rb, Register rc ) ++ { sw4_only(); emit_sw2_long( op_udivw | is_ra(ra) | is_rb(rb) | is_rc(rc) ); } ++ inline void Assembler::remw( Register ra, Register rb, Register rc ) ++ { sw4_only(); emit_sw2_long( op_remw | is_ra(ra) | is_rb(rb) | is_rc(rc) ); } ++ inline void Assembler::uremw( Register ra, Register rb, Register rc ) ++ { sw4_only(); emit_sw2_long( op_uremw | is_ra(ra) | is_rb(rb) | is_rc(rc) ); } ++ inline void Assembler::divl( Register ra, Register rb, Register rc ) ++ { sw4_only(); emit_sw2_long( op_divl | is_ra(ra) | is_rb(rb) | is_rc(rc) ); } ++ inline void Assembler::udivl( Register ra, Register rb, Register rc ) ++ { sw4_only(); emit_sw2_long( op_udivl | is_ra(ra) | is_rb(rb) | is_rc(rc) ); } ++ inline void Assembler::reml( Register ra, Register rb, Register rc ) ++ { sw4_only(); emit_sw2_long( op_reml | is_ra(ra) | is_rb(rb) | is_rc(rc) ); } ++ inline void Assembler::ureml( Register ra, Register rb, Register rc ) ++ { sw4_only(); emit_sw2_long( op_ureml | is_ra(ra) | is_rb(rb) | is_rc(rc) ); } ++ ++ inline void Assembler::addpi( int apint, Register rc ) ++ { sw4_only(); emit_sw2_long( op_addpi | is_apint(apint) | is_rc(rc) ); } ++ inline void Assembler::addpis( int apint, Register rc ) ++ { sw4_only(); emit_sw2_long( op_addpis | is_apint(apint) | is_rc(rc) ); } ++ inline void Assembler::sbt( Register ra, Register rb, Register rc ) ++ { sw4_only(); emit_sw2_long( op_sbt | is_ra(ra) | is_rb(rb) | is_rc(rc) ); } ++ inline void Assembler::sbt( Register ra, int lit, Register rc ) ++ { sw4_only(); emit_sw2_long( op_sbt_l | is_ra(ra) | is_lit(lit) | is_rc(rc) ); } ++ inline void Assembler::cbt( Register ra, Register rb, Register rc ) ++ { sw4_only(); emit_sw2_long( op_cbt | is_ra(ra) | is_rb(rb) | is_rc(rc) ); } ++ inline void Assembler::cbt( Register ra, int lit, Register rc ) ++ { sw4_only(); emit_sw2_long( op_cbt_l | is_ra(ra) | is_lit(lit) | is_rc(rc) ); } ++ ++ inline void Assembler::roll( Register ra, Register rb, Register rc ) ++ { sw4_only(); emit_sw2_long( op_roll | is_ra(ra) | is_rb(rb) | is_rc(rc) ); } ++ inline void Assembler::roll( Register ra, int lit, Register rc ) ++ { sw4_only(); emit_sw2_long( op_roll_l | is_ra(ra) | is_lit(lit) | is_rc(rc) ); } ++ inline void Assembler::sllw( Register ra, Register rb, Register rc ) ++ { sw4_only(); emit_sw2_long( op_sllw | is_ra(ra) | is_rb(rb) | is_rc(rc) ); } ++ inline void Assembler::sllw( Register ra, int lit, Register rc ) ++ { sw4_only(); emit_sw2_long( op_sllw_l | is_ra(ra) | is_lit(lit) | is_rc(rc) ); } ++ inline void Assembler::srlw( Register ra, Register rb, Register rc ) ++ { sw4_only(); emit_sw2_long( op_srlw | is_ra(ra) | is_rb(rb) | is_rc(rc) ); } ++ inline void Assembler::srlw( Register ra, int lit, Register rc ) ++ { sw4_only(); emit_sw2_long( op_srlw_l | is_ra(ra) | is_lit(lit) | is_rc(rc) ); } ++ inline void Assembler::sraw( Register ra, Register rb, Register rc ) ++ { sw4_only(); emit_sw2_long( op_sraw | is_ra(ra) | is_rb(rb) | is_rc(rc) ); } ++ inline void Assembler::sraw( Register ra, int lit, Register rc ) ++ { sw4_only(); emit_sw2_long( op_sraw_l | is_ra(ra) | is_lit(lit) | is_rc(rc) ); } ++ inline void Assembler::rolw( Register ra, Register rb, Register rc ) ++ { sw4_only(); emit_sw2_long( op_rolw | is_ra(ra) | is_rb(rb) | is_rc(rc) ); } ++ inline void Assembler::rolw( Register ra, int lit, Register rc ) ++ { sw4_only(); emit_sw2_long( op_rolw_l | is_ra(ra) | is_lit(lit) | is_rc(rc) ); } ++ ++ inline void Assembler::crc32b( Register rd, Register rs, Register rt ) ++ { sw4_only(); emit_sw2_long( op_crc32b | is_ra(rs) | is_rb(rt) | is_rc(rd) ); } ++ inline void Assembler::crc32h( Register rd, Register rs, Register rt ) ++ { sw4_only(); emit_sw2_long( op_crc32h | is_ra(rs) | is_rb(rt) | is_rc(rd) ); } ++ inline void Assembler::crc32w( Register rd, Register rs, Register rt ) ++ { sw4_only(); emit_sw2_long( op_crc32w | is_ra(rs) | is_rb(rt) | is_rc(rd) ); } ++ inline void Assembler::crc32l( Register rd, Register rs, Register rt ) ++ { sw4_only(); emit_sw2_long( op_crc32l | is_ra(rs) | is_rb(rt) | is_rc(rd) ); } ++ inline void Assembler::crc32cb( Register rd, Register rs, Register rt ) ++ { sw4_only(); emit_sw2_long( op_crc32cb | is_ra(rs) | is_rb(rt) | is_rc(rd) ); } ++ inline void Assembler::crc32ch( Register rd, Register rs, Register rt ) ++ { sw4_only(); emit_sw2_long( op_crc32ch | is_ra(rs) | is_rb(rt) | is_rc(rd) ); } ++ inline void Assembler::crc32cw( Register rd, Register rs, Register rt ) ++ { sw4_only(); emit_sw2_long( op_crc32cw | is_ra(rs) | is_rb(rt) | is_rc(rd) ); } ++ inline void Assembler::crc32cl( Register rd, Register rs, Register rt ) ++ { sw4_only(); emit_sw2_long( op_crc32cl | is_ra(rs) | is_rb(rt) | is_rc(rd) ); } ++ ++ inline void Assembler::revbh( Register rb, Register rc ) ++ { sw4_only(); emit_sw2_long( op_revbh | is_rb(rb) | is_rc(rc) ); } ++ inline void Assembler::revbw( Register rb, Register rc ) ++ { sw4_only(); emit_sw2_long( op_revbw | is_rb(rb) | is_rc(rc) ); } ++ inline void Assembler::revbl( Register rb, Register rc ) ++ { sw4_only(); emit_sw2_long( op_revbl | is_rb(rb) | is_rc(rc) ); } ++ inline void Assembler::casw( Register ra, Register rb, Register rc ) ++ { sw4_only(); emit_sw2_long( op_casw | is_ra(ra) | is_rb(rb) | is_rc(rc) ); } ++ inline void Assembler::casl( Register ra, Register rb, Register rc ) ++ { sw4_only(); emit_sw2_long( op_casl | is_ra(ra) | is_rb(rb) | is_rc(rc) ); } ++ inline void Assembler::frecs( FloatRegister fa, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_frecs | is_fa(fa) | is_fc(fc) ); } ++ inline void Assembler::frecd( FloatRegister fa, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_frecd | is_fa(fa) | is_fc(fc) ); } ++ inline void Assembler::fris( FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_fris | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::fris_g( FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_fris_g | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::fris_p( FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_fris_p | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::fris_z( FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_fris_z | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::fris_n( FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_fris_n | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::frid( FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_frid | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::frid_g( FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_frid_g | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::frid_p( FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_frid_p | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::frid_z( FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_frid_z | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::frid_n( FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_frid_n | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vsllb( FloatRegister fa, FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vsllb | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vsllb( FloatRegister fa, int lit, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vsllb_l | is_fa(fa) | is_lit(lit) | is_fc(fc) ); } ++ inline void Assembler::vsrlb( FloatRegister fa, FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vsrlb | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vsrlb( FloatRegister fa, int lit, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vsrlb_l | is_fa(fa) | is_lit(lit) | is_fc(fc) ); } ++ inline void Assembler::vsrab( FloatRegister fa, FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vsrab | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vsrab( FloatRegister fa, int lit, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vsrab_l | is_fa(fa) | is_lit(lit) | is_fc(fc) ); } ++ inline void Assembler::vrolb( FloatRegister fa, FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vrolb | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vrolb( FloatRegister fa, int lit, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vrolb_l | is_fa(fa) | is_lit(lit) | is_fc(fc) ); } ++ inline void Assembler::vsllh( FloatRegister fa, FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vsllh | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vsllh( FloatRegister fa, int lit, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vsllh_l | is_fa(fa) | is_lit(lit) | is_fc(fc) ); } ++ inline void Assembler::vsrlh( FloatRegister fa, FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vsrlh | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vsrlh( FloatRegister fa, int lit, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vsrlh_l | is_fa(fa) | is_lit(lit) | is_fc(fc) ); } ++ inline void Assembler::vsrah( FloatRegister fa, FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vsrah | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vsrah( FloatRegister fa, int lit, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vsrah_l | is_fa(fa) | is_lit(lit) | is_fc(fc) ); } ++ inline void Assembler::vrolh( FloatRegister fa, FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vrolh | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vrolh( FloatRegister fa, int lit, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vrolh_l | is_fa(fa) | is_lit(lit) | is_fc(fc) ); } ++ ++ inline void Assembler::vslll( FloatRegister fa, FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vslll | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vslll( FloatRegister fa, int lit, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vslll_l | is_fa(fa) | is_lit(lit) | is_fc(fc) ); } ++ inline void Assembler::vsrll( FloatRegister fa, FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vsrll | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vsrll( FloatRegister fa, int lit, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vsrll_l | is_fa(fa) | is_lit(lit) | is_fc(fc) ); } ++ inline void Assembler::vsral( FloatRegister fa, FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vsral | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vsral( FloatRegister fa, int lit, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vsral_l | is_fa(fa) | is_lit(lit) | is_fc(fc) ); } ++ inline void Assembler::vroll( FloatRegister fa, FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vroll | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vroll( FloatRegister fa, int lit, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vroll_l | is_fa(fa) | is_lit(lit) | is_fc(fc) ); } ++ inline void Assembler::vmaxb( FloatRegister fa, FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vmaxb | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vminb( FloatRegister fa, FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vminb | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::sraow( FloatRegister fa, FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_sraow | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::sraow( FloatRegister fa, int lit, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long(op_sraow_l | is_fa(fa) | is_lit(lit) | is_fc(fc) ); } ++ inline void Assembler::vsumw( FloatRegister fa, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vsumw | is_fa(fa) | is_fc(fc) ); } ++ inline void Assembler::vsuml( FloatRegister fa, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vsuml | is_fa(fa) | is_fc(fc) ); } ++ inline void Assembler::vcmpueqb( FloatRegister fa, FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vcmpueqb | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vcmpueqb( FloatRegister fa, int lit, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vcmpueqb_l | is_fa(fa) | is_lit(lit) | is_fc(fc) ); } ++ inline void Assembler::vcmpugtb( FloatRegister fa, FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vcmpugtb | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vcmpugtb( FloatRegister fa, int lit, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vcmpugtb_l | is_fa(fa) | is_lit(lit) | is_fc(fc) ); } ++ inline void Assembler::vmaxh( FloatRegister fa, FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vmaxh | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vminh( FloatRegister fa, FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vminh | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vmaxw( FloatRegister fa, FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vmaxw | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vminw( FloatRegister fa, FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vminw | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vmaxl( FloatRegister fa, FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vmaxl | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vminl( FloatRegister fa, FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vminl | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vsm3msw( FloatRegister fa, FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vsm3msw | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vsm4key( FloatRegister fa, int lit, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vsm4key_l | is_fa(fa) | is_lit(lit) | is_fc(fc) ); } ++ inline void Assembler::vsm4r( FloatRegister fa, FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vsm4r | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vbinvw( FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vbinvw | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vumaxb( FloatRegister fa, FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vumaxb | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vuminb( FloatRegister fa, FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vuminb | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vumaxh( FloatRegister fa, FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vumaxh | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vuminh( FloatRegister fa, FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vuminh | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vumaxw( FloatRegister fa, FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vumaxw | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vuminw( FloatRegister fa, FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vuminw | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vumaxl( FloatRegister fa, FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vumaxl | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vuminl( FloatRegister fa, FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vuminl | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vsums( FloatRegister fa, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vsums | is_fa(fa) | is_fc(fc) ); } ++ inline void Assembler::vsumd( FloatRegister fa, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vsumd | is_fa(fa) | is_fc(fc) ); } ++ inline void Assembler::vfcvtsd( FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vfcvtsd | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vfcvtds( FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vfcvtds | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vfcvtls( FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vfcvtls | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vfcvtld( FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vfcvtld | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vfcvtdl( FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vfcvtdl | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vfcvtdl_g( FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vfcvtdl_g | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vfcvtdl_p( FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vfcvtdl_p | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vfcvtdl_z( FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vfcvtdl_z | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vfcvtdl_n( FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vfcvtdl_n | is_fb(fb) | is_fc(fc) ); } ++ ++ inline void Assembler::vfris( FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vfris | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vfris_g( FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vfris_g | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vfris_p( FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vfris_p | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vfris_z( FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vfris_z | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vfris_n( FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vfris_n | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vfrid( FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vfrid | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vfrid_g( FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vfrid_g | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vfrid_p( FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vfrid_p | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vfrid_z( FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vfrid_z | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vfrid_n( FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vfrid_n | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vfrecs( FloatRegister fa, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vfrecs | is_fa(fa) | is_fc(fc) ); } ++ inline void Assembler::vfrecd( FloatRegister fa, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vfrecd | is_fa(fa) | is_fc(fc) ); } ++ inline void Assembler::vmaxs( FloatRegister fa, FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vmaxs | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vmins( FloatRegister fa, FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vmins | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vmaxd( FloatRegister fa, FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vmaxd | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vmind( FloatRegister fa, FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vmind | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ ++ inline void Assembler::vinsb( FloatRegister fa,FloatRegister fb, int fmalit, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vinsb_l | is_fa(fa) | is_fb(fb) | is_fmalit(fmalit) | is_fc(fc) ); } ++ inline void Assembler::vinsh( FloatRegister fa,FloatRegister fb, int fmalit, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vinsh_l | is_fa(fa) | is_fb(fb) | is_fmalit(fmalit) | is_fc(fc) ); } ++ inline void Assembler::vinsectlh( FloatRegister fa, FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vinsectlh | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vinsectlw( FloatRegister fa, FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vinsectlw | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vinsectll( FloatRegister fa, FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vinsectll | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vinsectlb( FloatRegister fa, FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vinsectlb | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vshfq( FloatRegister fa,FloatRegister fb, int fmalit, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vshfq_l | is_fa(fa) | is_fb(fb) | is_fmalit(fmalit) | is_fc(fc) ); } ++ inline void Assembler::vshfqb( FloatRegister fa, FloatRegister fb, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vshfqb | is_fa(fa) | is_fb(fb) | is_fc(fc) ); } ++ inline void Assembler::vcpyb( FloatRegister fa, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vcpyb | is_fa(fa) | is_fc(fc) ); } ++ inline void Assembler::vcpyh( FloatRegister fa, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vcpyh | is_fa(fa) | is_fc(fc) ); } ++ inline void Assembler::vsm3r( FloatRegister fa,FloatRegister fb, int fmalit, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vsm3r_l | is_fa(fa) | is_fb(fb) | is_fmalit(fmalit) | is_fc(fc) ); } ++ inline void Assembler::vfcvtsh( FloatRegister fa,FloatRegister fb, int fmalit, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vfcvtsh_l | is_fa(fa) | is_fb(fb) | is_fmalit(fmalit) | is_fc(fc) ); } ++ inline void Assembler::vfcvths( FloatRegister fa,FloatRegister fb, int fmalit, FloatRegister fc ) ++ { sw4_only(); emit_sw2_long( op_vfcvths_l | is_fa(fa) | is_fb(fb) | is_fmalit(fmalit) | is_fc(fc) ); } ++ inline void Assembler::lbr( int palfn ) ++ { sw4_only(); emit_sw2_long( op_lbr | is_palfn(palfn) ); } ++ ++ inline void Assembler::ldbu_a( Register ra, int atmdisp, Register rb ) ++ { sw4_only(); emit_sw2_long( op_ldbu_a | is_ra(ra) | is_atmdisp(atmdisp) | is_rb(rb) ); } ++ inline void Assembler::ldhu_a( Register ra, int atmdisp, Register rb ) ++ { sw4_only(); emit_sw2_long( op_ldhu_a | is_ra(ra) | is_atmdisp(atmdisp) | is_rb(rb) ); } ++ inline void Assembler::ldw_a( Register ra, int atmdisp, Register rb ) ++ { sw4_only(); emit_sw2_long( op_ldw_a | is_ra(ra) | is_atmdisp(atmdisp) | is_rb(rb) ); } ++ inline void Assembler::ldl_a( Register ra, int atmdisp, Register rb ) ++ { sw4_only(); emit_sw2_long( op_ldl_a | is_ra(ra) | is_atmdisp(atmdisp) | is_rb(rb) ); } ++ inline void Assembler::stb_a( Register ra, int atmdisp, Register rb ) ++ { sw4_only(); emit_sw2_long( op_stb_a | is_ra(ra) | is_atmdisp(atmdisp) | is_rb(rb) ); } ++ inline void Assembler::sth_a( Register ra, int atmdisp, Register rb ) ++ { sw4_only(); emit_sw2_long( op_sth_a | is_ra(ra) | is_atmdisp(atmdisp) | is_rb(rb) ); } ++ inline void Assembler::stw_a( Register ra, int atmdisp, Register rb ) ++ { sw4_only(); emit_sw2_long( op_stw_a | is_ra(ra) | is_atmdisp(atmdisp) | is_rb(rb) ); } ++ inline void Assembler::stl_a( Register ra, int atmdisp, Register rb ) ++ { sw4_only(); emit_sw2_long( op_stl_a | is_ra(ra) | is_atmdisp(atmdisp) | is_rb(rb) ); } ++ inline void Assembler::flds_a( FloatRegister fa, int atmdisp, Register rb ) ++ { sw4_only(); emit_sw2_long( op_flds_a | is_fa(fa) | is_atmdisp(atmdisp) | is_rb(rb) ); } ++ inline void Assembler::fldd_a( FloatRegister fa, int atmdisp, Register rb ) ++ { sw4_only(); emit_sw2_long( op_fldd_a | is_fa(fa) | is_atmdisp(atmdisp) | is_rb(rb) ); } ++ inline void Assembler::fsts_a( FloatRegister fa, int atmdisp, Register rb ) ++ { sw4_only(); emit_sw2_long( op_fsts_a | is_fa(fa) | is_atmdisp(atmdisp) | is_rb(rb) ); } ++ inline void Assembler::fstd_a( FloatRegister fa, int atmdisp, Register rb ) ++ { sw4_only(); emit_sw2_long( op_fstd_a | is_fa(fa) | is_atmdisp(atmdisp) | is_rb(rb) ); } ++ inline void Assembler::dpfhr( int th, int atmdisp, Register rb ) ++ { sw4_only(); emit_sw2_long( op_dpfhr | is_th(th) | is_atmdisp(atmdisp) | is_rb(rb) ); } ++ inline void Assembler::dpfhw( int th, int atmdisp, Register rb ) ++ { sw4_only(); emit_sw2_long( op_dpfhw | is_th(th) | is_atmdisp(atmdisp) | is_rb(rb) ); } ++ ++ ++ ++ ++ ++ ++ ++ ++#endif // CPU_SW64_VM_ASSEMBLER_SW64_INLINE_HPP +diff --git a/hotspot/src/cpu/sw64/vm/bytecodeInterpreter_sw64.cpp b/hotspot/src/cpu/sw64/vm/bytecodeInterpreter_sw64.cpp +new file mode 100755 +index 0000000000..f9c3185f45 +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/bytecodeInterpreter_sw64.cpp +@@ -0,0 +1,47 @@ ++/* ++ * Copyright (c) 2007, 2013, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#include "precompiled.hpp" ++#include "asm/assembler.hpp" ++#include "interpreter/bytecodeInterpreter.hpp" ++#include "interpreter/bytecodeInterpreter.inline.hpp" ++#include "interpreter/interpreter.hpp" ++#include "interpreter/interpreterRuntime.hpp" ++#include "oops/methodData.hpp" ++#include "oops/method.hpp" ++#include "oops/oop.inline.hpp" ++#include "prims/jvmtiExport.hpp" ++#include "prims/jvmtiThreadState.hpp" ++#include "runtime/deoptimization.hpp" ++#include "runtime/frame.inline.hpp" ++#include "runtime/sharedRuntime.hpp" ++#include "runtime/stubRoutines.hpp" ++#include "runtime/synchronizer.hpp" ++#include "runtime/vframeArray.hpp" ++#include "utilities/debug.hpp" ++#include "interp_masm_sw64.hpp" ++ ++#ifdef CC_INTERP ++ ++#endif // CC_INTERP (all) +diff --git a/hotspot/src/cpu/sw64/vm/bytecodeInterpreter_sw64.hpp b/hotspot/src/cpu/sw64/vm/bytecodeInterpreter_sw64.hpp +new file mode 100755 +index 0000000000..ab2b1b1bdb +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/bytecodeInterpreter_sw64.hpp +@@ -0,0 +1,110 @@ ++/* ++ * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_SW64_VM_BYTECODEINTERPRETER_SW64_HPP ++#define CPU_SW64_VM_BYTECODEINTERPRETER_SW64_HPP ++ ++// Platform specific for C++ based Interpreter ++#define LOTS_OF_REGS /* Lets interpreter use plenty of registers */ ++ ++private: ++ ++ // save the bottom of the stack after frame manager setup. For ease of restoration after return ++ // from recursive interpreter call ++ intptr_t* _frame_bottom; /* saved bottom of frame manager frame */ ++ intptr_t* _last_Java_pc; /* pc to return to in frame manager */ ++ intptr_t* _sender_sp; /* sender's sp before stack (locals) extension */ ++ interpreterState _self_link; /* Previous interpreter state */ /* sometimes points to self??? */ ++ double _native_fresult; /* save result of native calls that might return floats */ ++ intptr_t _native_lresult; /* save result of native calls that might return handle/longs */ ++ ++public: ++ ++ static void pd_layout_interpreterState(interpreterState istate, address last_Java_pc, intptr_t* last_Java_fp); ++ inline intptr_t* sender_sp() { ++ return _sender_sp; ++ } ++ ++ ++#define SET_LAST_JAVA_FRAME() ++ ++#define RESET_LAST_JAVA_FRAME() THREAD->frame_anchor()->set_flags(0); ++ ++/* ++ * Macros for accessing the stack. ++ */ ++#undef STACK_INT ++#undef STACK_FLOAT ++#undef STACK_ADDR ++#undef STACK_OBJECT ++#undef STACK_DOUBLE ++#undef STACK_LONG ++ ++// JavaStack Implementation ++ ++#define GET_STACK_SLOT(offset) (*((intptr_t*) &topOfStack[-(offset)])) ++#define STACK_SLOT(offset) ((address) &topOfStack[-(offset)]) ++#define STACK_ADDR(offset) (*((address *) &topOfStack[-(offset)])) ++#define STACK_INT(offset) (*((jint*) &topOfStack[-(offset)])) ++#define STACK_FLOAT(offset) (*((jfloat *) &topOfStack[-(offset)])) ++#define STACK_OBJECT(offset) (*((oop *) &topOfStack [-(offset)])) ++#define STACK_DOUBLE(offset) (((VMJavaVal64*) &topOfStack[-(offset)])->d) ++#define STACK_LONG(offset) (((VMJavaVal64 *) &topOfStack[-(offset)])->l) ++ ++#define SET_STACK_SLOT(value, offset) (*(intptr_t*)&topOfStack[-(offset)] = *(intptr_t*)(value)) ++#define SET_STACK_ADDR(value, offset) (*((address *)&topOfStack[-(offset)]) = (value)) ++#define SET_STACK_INT(value, offset) (*((jint *)&topOfStack[-(offset)]) = (value)) ++#define SET_STACK_FLOAT(value, offset) (*((jfloat *)&topOfStack[-(offset)]) = (value)) ++#define SET_STACK_OBJECT(value, offset) (*((oop *)&topOfStack[-(offset)]) = (value)) ++#define SET_STACK_DOUBLE(value, offset) (((VMJavaVal64*)&topOfStack[-(offset)])->d = (value)) ++#define SET_STACK_DOUBLE_FROM_ADDR(addr, offset) (((VMJavaVal64*)&topOfStack[-(offset)])->d = \ ++ ((VMJavaVal64*)(addr))->d) ++#define SET_STACK_LONG(value, offset) (((VMJavaVal64*)&topOfStack[-(offset)])->l = (value)) ++#define SET_STACK_LONG_FROM_ADDR(addr, offset) (((VMJavaVal64*)&topOfStack[-(offset)])->l = \ ++ ((VMJavaVal64*)(addr))->l) ++// JavaLocals implementation ++ ++#define LOCALS_SLOT(offset) ((intptr_t*)&locals[-(offset)]) ++#define LOCALS_ADDR(offset) ((address)locals[-(offset)]) ++#define LOCALS_INT(offset) (*((jint*)&locals[-(offset)])) ++#define LOCALS_FLOAT(offset) (*((jfloat*)&locals[-(offset)])) ++#define LOCALS_OBJECT(offset) (cast_to_oop(locals[-(offset)])) ++#define LOCALS_DOUBLE(offset) (((VMJavaVal64*)&locals[-((offset) + 1)])->d) ++#define LOCALS_LONG(offset) (((VMJavaVal64*)&locals[-((offset) + 1)])->l) ++#define LOCALS_LONG_AT(offset) (((address)&locals[-((offset) + 1)])) ++#define LOCALS_DOUBLE_AT(offset) (((address)&locals[-((offset) + 1)])) ++ ++#define SET_LOCALS_SLOT(value, offset) (*(intptr_t*)&locals[-(offset)] = *(intptr_t *)(value)) ++#define SET_LOCALS_ADDR(value, offset) (*((address *)&locals[-(offset)]) = (value)) ++#define SET_LOCALS_INT(value, offset) (*((jint *)&locals[-(offset)]) = (value)) ++#define SET_LOCALS_FLOAT(value, offset) (*((jfloat *)&locals[-(offset)]) = (value)) ++#define SET_LOCALS_OBJECT(value, offset) (*((oop *)&locals[-(offset)]) = (value)) ++#define SET_LOCALS_DOUBLE(value, offset) (((VMJavaVal64*)&locals[-((offset)+1)])->d = (value)) ++#define SET_LOCALS_LONG(value, offset) (((VMJavaVal64*)&locals[-((offset)+1)])->l = (value)) ++#define SET_LOCALS_DOUBLE_FROM_ADDR(addr, offset) (((VMJavaVal64*)&locals[-((offset)+1)])->d = \ ++ ((VMJavaVal64*)(addr))->d) ++#define SET_LOCALS_LONG_FROM_ADDR(addr, offset) (((VMJavaVal64*)&locals[-((offset)+1)])->l = \ ++ ((VMJavaVal64*)(addr))->l) ++ ++#endif // CPU_SW64_VM_BYTECODEINTERPRETER_SW64_HPP +diff --git a/hotspot/src/cpu/sw64/vm/bytecodeInterpreter_sw64.inline.hpp b/hotspot/src/cpu/sw64/vm/bytecodeInterpreter_sw64.inline.hpp +new file mode 100755 +index 0000000000..fdde7ea8d4 +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/bytecodeInterpreter_sw64.inline.hpp +@@ -0,0 +1,282 @@ ++/* ++ * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_SW64_VM_BYTECODEINTERPRETER_SW64_INLINE_HPP ++#define CPU_SW64_VM_BYTECODEINTERPRETER_SW64_INLINE_HPP ++ ++// Inline interpreter functions for SW64 ++ ++inline jfloat BytecodeInterpreter::VMfloatAdd(jfloat op1, jfloat op2) { return op1 + op2; } ++inline jfloat BytecodeInterpreter::VMfloatSub(jfloat op1, jfloat op2) { return op1 - op2; } ++inline jfloat BytecodeInterpreter::VMfloatMul(jfloat op1, jfloat op2) { return op1 * op2; } ++inline jfloat BytecodeInterpreter::VMfloatDiv(jfloat op1, jfloat op2) { return op1 / op2; } ++inline jfloat BytecodeInterpreter::VMfloatRem(jfloat op1, jfloat op2) { return fmod(op1, op2); } ++ ++inline jfloat BytecodeInterpreter::VMfloatNeg(jfloat op) { return -op; } ++ ++inline int32_t BytecodeInterpreter::VMfloatCompare(jfloat op1, jfloat op2, int32_t direction) { ++ return ( op1 < op2 ? -1 : ++ op1 > op2 ? 1 : ++ op1 == op2 ? 0 : ++ (direction == -1 || direction == 1) ? direction : 0); ++ ++} ++ ++inline void BytecodeInterpreter::VMmemCopy64(uint32_t to[2], const uint32_t from[2]) { ++ // x86 can do unaligned copies but not 64bits at a time ++ to[0] = from[0]; to[1] = from[1]; ++} ++ ++// The long operations depend on compiler support for "long long" on x86 ++ ++inline jlong BytecodeInterpreter::VMlongAdd(jlong op1, jlong op2) { ++ return op1 + op2; ++} ++ ++inline jlong BytecodeInterpreter::VMlongAnd(jlong op1, jlong op2) { ++ return op1 & op2; ++} ++ ++inline jlong BytecodeInterpreter::VMlongDiv(jlong op1, jlong op2) { ++ return op1 / op2; ++} ++ ++inline jlong BytecodeInterpreter::VMlongMul(jlong op1, jlong op2) { ++ return op1 * op2; ++} ++ ++inline jlong BytecodeInterpreter::VMlongOr(jlong op1, jlong op2) { ++ return op1 | op2; ++} ++ ++inline jlong BytecodeInterpreter::VMlongSub(jlong op1, jlong op2) { ++ return op1 - op2; ++} ++ ++inline jlong BytecodeInterpreter::VMlongXor(jlong op1, jlong op2) { ++ return op1 ^ op2; ++} ++ ++inline jlong BytecodeInterpreter::VMlongRem(jlong op1, jlong op2) { ++ return op1 % op2; ++} ++ ++inline jlong BytecodeInterpreter::VMlongUshr(jlong op1, jint op2) { ++ return ((unsigned long long) op1) >> (op2 & 0x3F); ++} ++ ++inline jlong BytecodeInterpreter::VMlongShr(jlong op1, jint op2) { ++ return op1 >> (op2 & 0x3F); ++} ++ ++inline jlong BytecodeInterpreter::VMlongShl(jlong op1, jint op2) { ++ return op1 << (op2 & 0x3F); ++} ++ ++inline jlong BytecodeInterpreter::VMlongNeg(jlong op) { ++ return -op; ++} ++ ++inline jlong BytecodeInterpreter::VMlongNot(jlong op) { ++ return ~op; ++} ++ ++inline int32_t BytecodeInterpreter::VMlongLtz(jlong op) { ++ return (op <= 0); ++} ++ ++inline int32_t BytecodeInterpreter::VMlongGez(jlong op) { ++ return (op >= 0); ++} ++ ++inline int32_t BytecodeInterpreter::VMlongEqz(jlong op) { ++ return (op == 0); ++} ++ ++inline int32_t BytecodeInterpreter::VMlongEq(jlong op1, jlong op2) { ++ return (op1 == op2); ++} ++ ++inline int32_t BytecodeInterpreter::VMlongNe(jlong op1, jlong op2) { ++ return (op1 != op2); ++} ++ ++inline int32_t BytecodeInterpreter::VMlongGe(jlong op1, jlong op2) { ++ return (op1 >= op2); ++} ++ ++inline int32_t BytecodeInterpreter::VMlongLe(jlong op1, jlong op2) { ++ return (op1 <= op2); ++} ++ ++inline int32_t BytecodeInterpreter::VMlongLt(jlong op1, jlong op2) { ++ return (op1 < op2); ++} ++ ++inline int32_t BytecodeInterpreter::VMlongGt(jlong op1, jlong op2) { ++ return (op1 > op2); ++} ++ ++inline int32_t BytecodeInterpreter::VMlongCompare(jlong op1, jlong op2) { ++ return (VMlongLt(op1, op2) ? -1 : VMlongGt(op1, op2) ? 1 : 0); ++} ++ ++// Long conversions ++ ++inline jdouble BytecodeInterpreter::VMlong2Double(jlong val) { ++ return (jdouble) val; ++} ++ ++inline jfloat BytecodeInterpreter::VMlong2Float(jlong val) { ++ return (jfloat) val; ++} ++ ++inline jint BytecodeInterpreter::VMlong2Int(jlong val) { ++ return (jint) val; ++} ++ ++// Double Arithmetic ++ ++inline jdouble BytecodeInterpreter::VMdoubleAdd(jdouble op1, jdouble op2) { ++ return op1 + op2; ++} ++ ++inline jdouble BytecodeInterpreter::VMdoubleDiv(jdouble op1, jdouble op2) { ++ return op1 / op2; ++} ++ ++inline jdouble BytecodeInterpreter::VMdoubleMul(jdouble op1, jdouble op2) { ++ return op1 * op2; ++} ++ ++inline jdouble BytecodeInterpreter::VMdoubleNeg(jdouble op) { ++ return -op; ++} ++ ++inline jdouble BytecodeInterpreter::VMdoubleRem(jdouble op1, jdouble op2) { ++ return fmod(op1, op2); ++} ++ ++inline jdouble BytecodeInterpreter::VMdoubleSub(jdouble op1, jdouble op2) { ++ return op1 - op2; ++} ++ ++inline int32_t BytecodeInterpreter::VMdoubleCompare(jdouble op1, jdouble op2, int32_t direction) { ++ return ( op1 < op2 ? -1 : ++ op1 > op2 ? 1 : ++ op1 == op2 ? 0 : ++ (direction == -1 || direction == 1) ? direction : 0); ++} ++ ++// Double Conversions ++ ++inline jfloat BytecodeInterpreter::VMdouble2Float(jdouble val) { ++ return (jfloat) val; ++} ++ ++// Float Conversions ++ ++inline jdouble BytecodeInterpreter::VMfloat2Double(jfloat op) { ++ return (jdouble) op; ++} ++ ++// Integer Arithmetic ++ ++inline jint BytecodeInterpreter::VMintAdd(jint op1, jint op2) { ++ return op1 + op2; ++} ++ ++inline jint BytecodeInterpreter::VMintAnd(jint op1, jint op2) { ++ return op1 & op2; ++} ++ ++inline jint BytecodeInterpreter::VMintDiv(jint op1, jint op2) { ++ // it's possible we could catch this special case implicitly ++ if ((juint)op1 == 0x80000000 && op2 == -1) return op1; ++ else return op1 / op2; ++} ++ ++inline jint BytecodeInterpreter::VMintMul(jint op1, jint op2) { ++ return op1 * op2; ++} ++ ++inline jint BytecodeInterpreter::VMintNeg(jint op) { ++ return -op; ++} ++ ++inline jint BytecodeInterpreter::VMintOr(jint op1, jint op2) { ++ return op1 | op2; ++} ++ ++inline jint BytecodeInterpreter::VMintRem(jint op1, jint op2) { ++ // it's possible we could catch this special case implicitly ++ if ((juint)op1 == 0x80000000 && op2 == -1) return 0; ++ else return op1 % op2; ++} ++ ++inline jint BytecodeInterpreter::VMintShl(jint op1, jint op2) { ++ return op1 << op2; ++} ++ ++inline jint BytecodeInterpreter::VMintShr(jint op1, jint op2) { ++ return op1 >> (op2 & 0x1f); // QQ op2 & 0x1f?? ++} ++ ++inline jint BytecodeInterpreter::VMintSub(jint op1, jint op2) { ++ return op1 - op2; ++} ++ ++inline jint BytecodeInterpreter::VMintUshr(jint op1, jint op2) { ++ return ((juint) op1) >> (op2 & 0x1f); // QQ op2 & 0x1f?? ++} ++ ++inline jint BytecodeInterpreter::VMintXor(jint op1, jint op2) { ++ return op1 ^ op2; ++} ++ ++inline jdouble BytecodeInterpreter::VMint2Double(jint val) { ++ return (jdouble) val; ++} ++ ++inline jfloat BytecodeInterpreter::VMint2Float(jint val) { ++ return (jfloat) val; ++} ++ ++inline jlong BytecodeInterpreter::VMint2Long(jint val) { ++ return (jlong) val; ++} ++ ++inline jchar BytecodeInterpreter::VMint2Char(jint val) { ++ return (jchar) val; ++} ++ ++inline jshort BytecodeInterpreter::VMint2Short(jint val) { ++ return (jshort) val; ++} ++ ++inline jbyte BytecodeInterpreter::VMint2Byte(jint val) { ++ return (jbyte) val; ++} ++ ++#endif // CPU_SW64_VM_BYTECODEINTERPRETER_SW64_INLINE_HPP +diff --git a/hotspot/src/cpu/sw64/vm/bytecodes_sw64.cpp b/hotspot/src/cpu/sw64/vm/bytecodes_sw64.cpp +new file mode 100755 +index 0000000000..f82f92c66f +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/bytecodes_sw64.cpp +@@ -0,0 +1,43 @@ ++/* ++ * Copyright (c) 1998, 2010, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#include "precompiled.hpp" ++#include "interpreter/bytecodes.hpp" ++ ++ ++void Bytecodes::pd_initialize() { ++ // No sw64 specific initialization ++ if (SafePatch) { ++ NativeCall::instruction_size = 6 * BytesPerInstWord; ++ NativeCall::return_address_offset = 6 * BytesPerInstWord; ++ NativeCall::return_address_offset_long = 6 * BytesPerInstWord; ++ NativeGeneralJump::instruction_size = 6 * BytesPerInstWord; ++ } ++} ++ ++ ++Bytecodes::Code Bytecodes::pd_base_code_for(Code code) { ++ // No sw64 specific bytecodes ++ return code; ++} +diff --git a/hotspot/src/cpu/sw64/vm/bytecodes_sw64.hpp b/hotspot/src/cpu/sw64/vm/bytecodes_sw64.hpp +new file mode 100755 +index 0000000000..e6c88afeb4 +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/bytecodes_sw64.hpp +@@ -0,0 +1,30 @@ ++/* ++ * Copyright (c) 1998, 2010, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_SW64_VM_BYTECODES_SW64_HPP ++#define CPU_SW64_VM_BYTECODES_SW64_HPP ++ ++// No Sw64 specific bytecodes ++ ++#endif // CPU_SW64_VM_BYTECODES_SW64_HPP +diff --git a/hotspot/src/cpu/sw64/vm/bytes_sw64.hpp b/hotspot/src/cpu/sw64/vm/bytes_sw64.hpp +new file mode 100755 +index 0000000000..237636c28c +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/bytes_sw64.hpp +@@ -0,0 +1,265 @@ ++/* ++ * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_SW64_VM_BYTES_SW64_HPP ++#define CPU_SW64_VM_BYTES_SW64_HPP ++ ++#include "memory/allocation.hpp" ++ ++class Bytes: AllStatic { ++ private: ++ // Helper function for swap_u8, not used in SW. ++ static inline u8 swap_u8_base(u4 x, u4 y) {} // compiler-dependent implementation ++ ++ public: ++ // Returns true if the byte ordering used by Java is different from the native byte ordering ++ // of the underlying machine. For example, this is true for Intel x86, but false for Solaris ++ // on Sparc. ++ static inline bool is_Java_byte_ordering_different(){ return true; } ++ ++ ++ // Efficient reading and writing of unaligned unsigned data in platform-specific byte ordering ++ // (no special code is needed since x86 CPUs can access unaligned data) ++ static inline u2 get_native_u2(address p) { ++ if ((intptr_t)p & 0x1) { ++ return ((u2)p[1] << 8) | (u2)p[0]; ++ } else { ++ return *(u2*)p; ++ } ++ } ++ ++ static inline u4 get_native_u4(address p) { ++// return *(u4*)p; ++ switch (intptr_t(p) & 3) { ++ case 0: return *(u4*)p; ++ ++ case 2: return ( u4( ((u2*)p)[1] ) << 16 ) ++ | ( u4( ((u2*)p)[0] ) ); ++ ++ default: return ( u4(p[3]) << 24 ) ++ | ( u4(p[2]) << 16 ) ++ | ( u4(p[1]) << 8 ) ++ | u4(p[0]); ++ } ++ } ++ ++ static inline u8 get_native_u8(address p) { ++// return *(u8*)p; ++ switch (intptr_t(p) & 7) { ++ case 0: return *(u8*)p; ++ ++ case 4: return ( u8( ((u4*)p)[1] ) << 32 ) ++ | ( u8( ((u4*)p)[0] ) ); ++ ++ case 2: return ( u8( ((u2*)p)[3] ) << 48 ) ++ | ( u8( ((u2*)p)[2] ) << 32 ) ++ | ( u8( ((u2*)p)[1] ) << 16 ) ++ | ( u8( ((u2*)p)[0] ) ); ++ ++ default: return ( u8(p[7]) << 56 ) ++ | ( u8(p[6]) << 48 ) ++ | ( u8(p[5]) << 40 ) ++ | ( u8(p[4]) << 32 ) ++ | ( u8(p[3]) << 24 ) ++ | ( u8(p[2]) << 16 ) ++ | ( u8(p[1]) << 8 ) ++ | u8(p[0]); ++ } ++ } ++ ++ static inline void put_native_u2(address p, u2 x) { ++ if((intptr_t)p & 0x1) { ++ p[0] = (u_char)(x); ++ p[1] = (u_char)(x>>8); ++ } else { ++ *(u2*)p = x; ++ } ++ } ++ ++ static inline void put_native_u4(address p, u4 x) { ++ // refer to sparc implementation. ++ switch ( intptr_t(p) & 3 ) { ++ case 0: *(u4*)p = x; ++ break; ++ ++ case 2: ((u2*)p)[1] = x >> 16; ++ ((u2*)p)[0] = x; ++ break; ++ ++ default: ((u1*)p)[3] = x >> 24; ++ ((u1*)p)[2] = x >> 16; ++ ((u1*)p)[1] = x >> 8; ++ ((u1*)p)[0] = x; ++ break; ++ } ++ } ++ ++ static inline void put_native_u8(address p, u8 x) { ++ // refer to sparc implementation. ++ // Note that sparc is big-endian, while sw64 is little-endian ++ switch ( intptr_t(p) & 7 ) { ++ case 0: *(u8*)p = x; ++ break; ++ ++ case 4: ((u4*)p)[1] = x >> 32; ++ ((u4*)p)[0] = x; ++ break; ++ ++ case 2: ((u2*)p)[3] = x >> 48; ++ ((u2*)p)[2] = x >> 32; ++ ((u2*)p)[1] = x >> 16; ++ ((u2*)p)[0] = x; ++ break; ++ ++ default: ((u1*)p)[7] = x >> 56; ++ ((u1*)p)[6] = x >> 48; ++ ((u1*)p)[5] = x >> 40; ++ ((u1*)p)[4] = x >> 32; ++ ((u1*)p)[3] = x >> 24; ++ ((u1*)p)[2] = x >> 16; ++ ((u1*)p)[1] = x >> 8; ++ ((u1*)p)[0] = x; ++ } ++ } ++ ++ ++ // Efficient reading and writing of unaligned unsigned data in Java ++ // byte ordering (i.e. big-endian ordering). Byte-order reversal is ++ // needed since SW64 CPUs use little-endian format. ++ static inline u2 get_Java_u2(address p) { ++// return (p[0] << 8) | p[1]; ++ if((intptr_t)p & 0x1) { ++ return (p[0] << 8) | p[1]; ++ } else { ++ return swap_u2(*(u2*)p); ++ } ++ } ++ static inline u4 get_Java_u4(address p) { ++// return swap_u4(get_native_u4(p)); ++ switch (intptr_t(p) & 3) { ++ case 0: return swap_u4(*(u4*)p); ++ ++ case 2: return swap_u4(( u4( ((u2*)p)[1] << 16)) ++ | ( u4( ((u2*)p)[0] ) )); ++ ++ default: return ( u4(p[3]) ) ++ | ( u4(p[2]) << 8 ) ++ | ( u4(p[1]) << 16 ) ++ | ( u4(p[0]) << 24 ); ++ } ++ } ++ static inline u8 get_Java_u8(address p) { ++// return swap_u8(get_native_u8(p)); ++ switch (intptr_t(p) & 7) { ++ case 0: return swap_u8(*(u8*)p); ++ ++ case 4: return swap_u8(( u8( ((u4*)p)[1] ) << 32 ) ++ | ( u8( ((u4*)p)[0] ) )); ++ ++ case 2: return swap_u8(( u8( ((u2*)p)[3] ) << 48 ) ++ | ( u8( ((u2*)p)[2] ) << 32 ) ++ | ( u8( ((u2*)p)[1] ) << 16 ) ++ | ( u8( ((u2*)p)[0] ) )); ++ ++ default: return ( u8(p[7]) ) ++ | ( u8(p[6]) << 8 ) ++ | ( u8(p[5]) << 16 ) ++ | ( u8(p[4]) << 24 ) ++ | ( u8(p[3]) << 32 ) ++ | ( u8(p[2]) << 40 ) ++ | ( u8(p[1]) << 48 ) ++ | ( u8(p[0]) << 56 ); ++ } ++ } ++ ++ static inline void put_Java_u2(address p, u2 x) { ++ if((intptr_t)p & 0x1) { ++ p[0] = (u_char)(x >> 8); ++ p[1] = (u_char)(x); ++ } else { ++ *(u2*)p = swap_u2(x); ++ } ++ } ++ ++ static inline void put_Java_u4(address p, u4 x) { ++// put_native_u4(p, swap_u4(x)); ++ switch ( intptr_t(p) & 3 ) { ++ case 0: *(u4*)p = swap_u4(x); ++ break; ++ ++ case 2: x = swap_u4(x); ++ ((u2*)p)[1] = x >> 16; ++ ((u2*)p)[0] = x; ++ break; ++ ++ default: ((u1*)p)[0] = x >> 24; ++ ((u1*)p)[1] = x >> 16; ++ ((u1*)p)[2] = x >> 8; ++ ((u1*)p)[3] = x; ++ break; ++ } ++ } ++ static inline void put_Java_u8(address p, u8 x) { ++// put_native_u8(p, swap_u8(x)); ++ switch ( intptr_t(p) & 7 ) { ++ case 0: *(u8*)p = swap_u8(x); ++ break; ++ ++ case 4: x = swap_u8(x); ++ ((u4*)p)[1] = x >> 32; ++ ((u4*)p)[0] = x; ++ break; ++ ++ case 2: x = swap_u8(x); ++ ((u2*)p)[3] = x >> 48; ++ ((u2*)p)[2] = x >> 32; ++ ((u2*)p)[1] = x >> 16; ++ ((u2*)p)[0] = x; ++ break; ++ ++ default: ((u1*)p)[0] = x >> 56; ++ ((u1*)p)[1] = x >> 48; ++ ((u1*)p)[2] = x >> 40; ++ ((u1*)p)[3] = x >> 32; ++ ((u1*)p)[4] = x >> 24; ++ ((u1*)p)[5] = x >> 16; ++ ((u1*)p)[6] = x >> 8; ++ ((u1*)p)[7] = x; ++ } ++ } ++ ++ ++ // Efficient swapping of byte ordering ++ static inline u2 swap_u2(u2 x); // compiler-dependent implementation ++ static inline u4 swap_u4(u4 x); // compiler-dependent implementation ++ static inline u8 swap_u8(u8 x); ++}; ++ ++ ++// The following header contains the implementations of swap_u2, swap_u4, and swap_u8[_base] ++#ifdef TARGET_OS_ARCH_linux_sw64 ++# include "bytes_linux_sw64.inline.hpp" ++#endif ++ ++#endif // CPU_SW64_VM_BYTES_SW64_HPP +diff --git a/hotspot/src/cpu/sw64/vm/c2_globals_sw64.hpp b/hotspot/src/cpu/sw64/vm/c2_globals_sw64.hpp +new file mode 100755 +index 0000000000..d3ed6468ff +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/c2_globals_sw64.hpp +@@ -0,0 +1,87 @@ ++/* ++ * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_SW64_VM_C2_GLOBALS_SW64_HPP ++#define CPU_SW64_VM_C2_GLOBALS_SW64_HPP ++ ++#include "utilities/globalDefinitions.hpp" ++#include "utilities/macros.hpp" ++ ++// Sets the default values for platform dependent flags used by the server compiler. ++// (see c2_globals.hpp). Alpha-sorted. ++define_pd_global(bool, BackgroundCompilation, true); ++define_pd_global(bool, UseTLAB, true); ++define_pd_global(bool, ResizeTLAB, true); ++define_pd_global(bool, CICompileOSR, true); ++define_pd_global(bool, InlineIntrinsics, true); ++define_pd_global(bool, PreferInterpreterNativeStubs, false); ++define_pd_global(bool, ProfileTraps, true); ++define_pd_global(bool, UseOnStackReplacement, true); ++#ifdef CC_INTERP ++define_pd_global(bool, ProfileInterpreter, false); ++#else ++define_pd_global(bool, ProfileInterpreter, true); ++#endif // CC_INTERP ++define_pd_global(bool, TieredCompilation, false); // Disable C1 in server JIT ++define_pd_global(intx, CompileThreshold, 10000); ++define_pd_global(intx, BackEdgeThreshold, 100000); ++ ++define_pd_global(intx, OnStackReplacePercentage, 140); ++define_pd_global(intx, ConditionalMoveLimit, 3); ++define_pd_global(intx, FLOATPRESSURE, 12); //TODO check lsp set 32 caused SPECjvm2008 sunflow failed ++define_pd_global(intx, FreqInlineSize, 325); ++define_pd_global(intx, MinJumpTableSize, 10); ++define_pd_global(intx, INTPRESSURE, 22); //TODO check lsp ++define_pd_global(intx, InteriorEntryAlignment, 16); ++define_pd_global(intx, NewSizeThreadIncrease, ScaleForWordSize(4*K)); ++define_pd_global(intx, LoopUnrollLimit, 60); ++ ++// InitialCodeCacheSize derived from specjbb2000 run. ++define_pd_global(intx, InitialCodeCacheSize, 2496*K); // Integral multiple of CodeCacheExpansionSize ++define_pd_global(intx, CodeCacheExpansionSize, 64*K); ++ ++// Ergonomics related flags ++define_pd_global(uint64_t,MaxRAM, 128ULL*G); ++define_pd_global(intx, RegisterCostAreaRatio, 16000); ++ ++// Peephole and CISC spilling both break the graph, and so makes the ++// scheduler sick. ++define_pd_global(bool, OptoPeephole, false); ++define_pd_global(bool, UseCISCSpill, false); ++define_pd_global(bool, OptoScheduling, false); ++define_pd_global(bool, OptoBundling, false); ++ ++define_pd_global(intx, ReservedCodeCacheSize, 240*M); ++define_pd_global(uintx, CodeCacheMinBlockLength, 4); ++define_pd_global(uintx, CodeCacheMinimumUseSpace, 400*K /*8*M*/); ++ ++define_pd_global(bool, TrapBasedRangeChecks, false); // Not needed on x86. ++ ++// Heap related flags ++define_pd_global(uintx,MetaspaceSize, ScaleForWordSize(16*M)); ++ ++// Ergonomics related flags ++define_pd_global(bool, NeverActAsServerClassMachine, false); ++ ++#endif // CPU_SW64_VM_C2_GLOBALS_SW64_HPP +diff --git a/hotspot/src/cpu/sw64/vm/c2_init_sw64.cpp b/hotspot/src/cpu/sw64/vm/c2_init_sw64.cpp +new file mode 100755 +index 0000000000..4e14453842 +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/c2_init_sw64.cpp +@@ -0,0 +1,33 @@ ++/* ++ * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#include "precompiled.hpp" ++#include "opto/compile.hpp" ++#include "opto/node.hpp" ++ ++// processor dependent initialization for SW64 ++ ++void Compile::pd_compiler2_init() { ++ guarantee(CodeEntryAlignment >= InteriorEntryAlignment, "" ); ++} +diff --git a/hotspot/src/cpu/sw64/vm/codeBuffer_sw64.hpp b/hotspot/src/cpu/sw64/vm/codeBuffer_sw64.hpp +new file mode 100755 +index 0000000000..97c0111c70 +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/codeBuffer_sw64.hpp +@@ -0,0 +1,34 @@ ++/* ++ * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_SW64_VM_CODEBUFFER_SW64_HPP ++#define CPU_SW64_VM_CODEBUFFER_SW64_HPP ++ ++private: ++ void pd_initialize() {} ++ ++public: ++ void flush_bundle(bool start_new_bundle) {} ++ ++#endif // CPU_SW64_VM_CODEBUFFER_SW64_HPP +diff --git a/hotspot/src/cpu/sw64/vm/compiledIC_sw64.cpp b/hotspot/src/cpu/sw64/vm/compiledIC_sw64.cpp +new file mode 100755 +index 0000000000..eb80569ebc +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/compiledIC_sw64.cpp +@@ -0,0 +1,158 @@ ++/* ++ * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#include "precompiled.hpp" ++#include "asm/macroAssembler.inline.hpp" ++#include "code/compiledIC.hpp" ++#include "code/icBuffer.hpp" ++#include "code/nmethod.hpp" ++#include "memory/resourceArea.hpp" ++#include "runtime/mutexLocker.hpp" ++#include "runtime/safepoint.hpp" ++ ++// Release the CompiledICHolder* associated with this call site is there is one. ++void CompiledIC::cleanup_call_site(virtual_call_Relocation* call_site) { ++ // This call site might have become stale so inspect it carefully. ++ NativeCall* call = nativeCall_at(call_site->addr()); ++ if (is_icholder_entry(call->destination())) { ++ NativeMovConstReg* value = nativeMovConstReg_at(call_site->cached_value()); ++ InlineCacheBuffer::queue_for_release((CompiledICHolder*)value->data()); ++ } ++} ++ ++bool CompiledIC::is_icholder_call_site(virtual_call_Relocation* call_site) { ++ // This call site might have become stale so inspect it carefully. ++ NativeCall* call = nativeCall_at(call_site->addr()); ++ return is_icholder_entry(call->destination()); ++} ++ ++// ---------------------------------------------------------------------------- ++ ++#define __ _masm. ++address CompiledStaticCall::emit_to_interp_stub(CodeBuffer &cbuf) { ++ ++ address mark = cbuf.insts_mark(); // get mark within main instrs section ++ ++ // Note that the code buffer's insts_mark is always relative to insts. ++ // That's why we must use the macroassembler to generate a stub. ++ MacroAssembler _masm(&cbuf); ++ ++ address base = __ start_a_stub(Compile::MAX_stubs_size); ++ if (base == NULL) return NULL; // CodeBuffer::expand failed ++ // static stub relocation stores the instruction address of the call ++ ++ __ relocate(static_stub_Relocation::spec(mark), 0); ++ ++ // Rmethod contains methodOop, it should be relocated for GC ++ ++ // static stub relocation also tags the methodOop in the code-stream. ++ __ patchable_set48(S3, (long)0); ++ // This is recognized as unresolved by relocs/nativeInst/ic code ++ ++ __ relocate(relocInfo::runtime_call_type); ++ ++ cbuf.set_insts_mark(); ++ address call_pc = (address)-1; ++ __ patchable_jump(call_pc); ++ __ align(16); ++ // Update current stubs pointer and restore code_end. ++ __ end_a_stub(); ++ return base; ++} ++#undef __ ++ ++int CompiledStaticCall::to_interp_stub_size() { ++ int size = 4 * 4 + NativeCall::instruction_size; // sizeof(li48) + NativeCall::instruction_size ++ return round_to(size, 16); ++} ++ ++// Relocation entries for call stub, compiled java to interpreter. ++int CompiledStaticCall::reloc_to_interp_stub() { ++ return 16; ++} ++ ++void CompiledStaticCall::set_to_interpreted(methodHandle callee, address entry) { ++ address stub = find_stub(); ++ guarantee(stub != NULL, "stub not found"); ++ ++ if (TraceICs) { ++ ResourceMark rm; ++ tty->print_cr("CompiledStaticCall@" INTPTR_FORMAT ": set_to_interpreted %s", ++ instruction_address(), ++ callee->name_and_sig_as_C_string()); ++ } ++ ++ // Creation also verifies the object. ++ NativeMovConstReg* method_holder = nativeMovConstReg_at(stub); ++ NativeGeneralJump* jump = nativeGeneralJump_at(method_holder->next_instruction_address()); ++ ++ assert(method_holder->data() == 0 || method_holder->data() == (intptr_t)callee(), ++ "a) MT-unsafe modification of inline cache"); ++ assert(jump->jump_destination() == (address)-1 || jump->jump_destination() == entry, ++ "b) MT-unsafe modification of inline cache"); ++ ++ // Update stub. ++ method_holder->set_data((intptr_t)callee()); ++ jump->set_jump_destination(entry); ++ ++ // Update jump to call. ++ set_destination_mt_safe(stub); ++} ++ ++void CompiledStaticCall::set_stub_to_clean(static_stub_Relocation* static_stub) { ++ assert (CompiledIC_lock->is_locked() || SafepointSynchronize::is_at_safepoint(), "mt unsafe call"); ++ // Reset stub. ++ address stub = static_stub->addr(); ++ assert(stub != NULL, "stub not found"); ++ // Creation also verifies the object. ++ NativeMovConstReg* method_holder = nativeMovConstReg_at(stub); ++ NativeGeneralJump* jump = nativeGeneralJump_at(method_holder->next_instruction_address()); ++ method_holder->set_data(0); ++ jump->set_jump_destination((address)-1); ++} ++ ++//----------------------------------------------------------------------------- ++// Non-product mode code ++#ifndef PRODUCT ++ ++void CompiledStaticCall::verify() { ++ // Verify call. ++ NativeCall::verify(); ++ if (os::is_MP()) { ++ verify_alignment(); ++ } ++ ++ // Verify stub. ++ address stub = find_stub(); ++ assert(stub != NULL, "no stub found for static call"); ++ // Creation also verifies the object. ++ NativeMovConstReg* method_holder = nativeMovConstReg_at(stub); ++ NativeGeneralJump* jump = nativeGeneralJump_at(method_holder->next_instruction_address()); ++ ++ ++ // Verify state. ++ assert(is_clean() || is_call_to_compiled() || is_call_to_interpreted(), "sanity check"); ++} ++ ++#endif // !PRODUCT +diff --git a/hotspot/src/cpu/sw64/vm/copy_sw64.hpp b/hotspot/src/cpu/sw64/vm/copy_sw64.hpp +new file mode 100755 +index 0000000000..7fff8fa08b +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/copy_sw64.hpp +@@ -0,0 +1,71 @@ ++/* ++ * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_SW64_VM_COPY_SW64_HPP ++#define CPU_SW64_VM_COPY_SW64_HPP ++ ++// Inline functions for memory copy and fill. ++// ++// // Contains inline asm implementations ++#ifdef TARGET_OS_ARCH_linux_sw64 ++# include "copy_linux_sw64.inline.hpp" ++#endif ++#ifdef TARGET_OS_ARCH_solaris_sw64 ++# include "copy_solaris_sw64.inline.hpp" ++#endif ++#ifdef TARGET_OS_ARCH_windows_sw64 ++# include "copy_windows_sw64.inline.hpp" ++#endif ++#ifdef TARGET_OS_ARCH_bsd_sw64 ++# include "copy_bsd_sw64.inline.hpp" ++#endif ++// Inline functions for memory copy and fill. ++ ++// Contains inline asm implementations ++ ++static void pd_fill_to_words(HeapWord* tohw, size_t count, juint value) { ++ julong* to = (julong*) tohw; ++ julong v = ((julong) value << 32) | value; ++ while (count-- > 0) { ++ *to++ = v; ++ } ++} ++ ++static void pd_fill_to_aligned_words(HeapWord* tohw, size_t count, juint value) { ++ pd_fill_to_words(tohw, count, value); ++} ++ ++static void pd_fill_to_bytes(void* to, size_t count, jubyte value) { ++ (void)memset(to, value, count); ++} ++ ++static void pd_zero_to_words(HeapWord* tohw, size_t count) { ++ pd_fill_to_words(tohw, count, 0); ++} ++ ++static void pd_zero_to_bytes(void* to, size_t count) { ++ (void)memset(to, 0, count); ++} ++ ++#endif //CPU_SW64_VM_COPY_SW64_HPP +diff --git a/hotspot/src/cpu/sw64/vm/cppInterpreterGenerator_sw64.hpp b/hotspot/src/cpu/sw64/vm/cppInterpreterGenerator_sw64.hpp +new file mode 100755 +index 0000000000..a434788072 +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/cppInterpreterGenerator_sw64.hpp +@@ -0,0 +1,37 @@ ++/* ++ * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_SW64_VM_CPPINTERPRETERGENERATOR_SW64_HPP ++#define CPU_SW64_VM_CPPINTERPRETERGENERATOR_SW64_HPP ++ ++ protected: ++ void generate_more_monitors(); ++ void generate_deopt_handling(); ++ address generate_interpreter_frame_manager(bool synchronized); // C++ interpreter only ++ void generate_compute_interpreter_state(const Register state, ++ const Register prev_state, ++ const Register sender_sp, ++ bool native); // C++ interpreter only ++ ++#endif // CPU_SW64_VM_CPPINTERPRETERGENERATOR_SW64_HPP +diff --git a/hotspot/src/cpu/sw64/vm/cppInterpreter_sw64.cpp b/hotspot/src/cpu/sw64/vm/cppInterpreter_sw64.cpp +new file mode 100755 +index 0000000000..c37c065325 +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/cppInterpreter_sw64.cpp +@@ -0,0 +1,214 @@ ++/* ++ * Copyright (c) 2007, 2013, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#include "precompiled.hpp" ++#include "asm/macroAssembler.hpp" ++#include "interpreter/bytecodeHistogram.hpp" ++#include "interpreter/cppInterpreter.hpp" ++#include "interpreter/interpreter.hpp" ++#include "interpreter/interpreterGenerator.hpp" ++#include "interpreter/interpreterRuntime.hpp" ++#include "oops/arrayOop.hpp" ++#include "oops/methodData.hpp" ++#include "oops/method.hpp" ++#include "oops/oop.inline.hpp" ++#include "prims/jvmtiExport.hpp" ++#include "prims/jvmtiThreadState.hpp" ++#include "runtime/arguments.hpp" ++#include "runtime/deoptimization.hpp" ++#include "runtime/frame.inline.hpp" ++#include "runtime/interfaceSupport.hpp" ++#include "runtime/sharedRuntime.hpp" ++#include "runtime/stubRoutines.hpp" ++#include "runtime/synchronizer.hpp" ++#include "runtime/timer.hpp" ++#include "runtime/vframeArray.hpp" ++#include "utilities/debug.hpp" ++#ifdef SHARK ++#include "shark/shark_globals.hpp" ++#endif ++ ++#ifdef CC_INTERP ++ ++// Routine exists to make tracebacks look decent in debugger ++// while "shadow" interpreter frames are on stack. It is also ++// used to distinguish interpreter frames. ++ ++extern "C" void RecursiveInterpreterActivation(interpreterState istate) { ++ ShouldNotReachHere(); ++} ++ ++bool CppInterpreter::contains(address pc) { ++ Unimplemented(); ++} ++ ++#define STATE(field_name) Lstate, in_bytes(byte_offset_of(BytecodeInterpreter, field_name)) ++#define __ _masm-> ++ ++Label frame_manager_entry; ++Label fast_accessor_slow_entry_path; // fast accessor methods need to be able to jmp to unsynchronized ++ // c++ interpreter entry point this holds that entry point label. ++ ++static address unctrap_frame_manager_entry = NULL; ++ ++static address interpreter_return_address = NULL; ++static address deopt_frame_manager_return_atos = NULL; ++static address deopt_frame_manager_return_btos = NULL; ++static address deopt_frame_manager_return_itos = NULL; ++static address deopt_frame_manager_return_ltos = NULL; ++static address deopt_frame_manager_return_ftos = NULL; ++static address deopt_frame_manager_return_dtos = NULL; ++static address deopt_frame_manager_return_vtos = NULL; ++ ++const Register prevState = G1_scratch; ++ ++void InterpreterGenerator::save_native_result(void) { ++ Unimplemented(); ++} ++ ++void InterpreterGenerator::restore_native_result(void) { ++ Unimplemented(); ++} ++ ++// A result handler converts/unboxes a native call result into ++// a java interpreter/compiler result. The current frame is an ++// interpreter frame. The activation frame unwind code must be ++// consistent with that of TemplateTable::_return(...). In the ++// case of native methods, the caller's SP was not modified. ++address CppInterpreterGenerator::generate_result_handler_for(BasicType type) { ++ Unimplemented(); ++} ++ ++address CppInterpreterGenerator::generate_tosca_to_stack_converter(BasicType type) { ++ Unimplemented(); ++} ++ ++address CppInterpreterGenerator::generate_stack_to_stack_converter(BasicType type) { ++ Unimplemented(); ++} ++ ++address CppInterpreterGenerator::generate_stack_to_native_abi_converter(BasicType type) { ++ Unimplemented(); ++} ++ ++address CppInterpreter::return_entry(TosState state, int length) { ++ Unimplemented(); ++} ++ ++address CppInterpreter::deopt_entry(TosState state, int length) { ++ Unimplemented(); ++} ++ ++void InterpreterGenerator::generate_counter_incr(Label* overflow, Label* profile_method, Label* profile_method_continue) { ++ Unimplemented(); ++} ++ ++address InterpreterGenerator::generate_empty_entry(void) { ++ Unimplemented(); ++} ++ ++address InterpreterGenerator::generate_accessor_entry(void) { ++ Unimplemented(); ++} ++ ++address InterpreterGenerator::generate_native_entry(bool synchronized) { ++ Unimplemented(); ++} ++ ++void CppInterpreterGenerator::generate_compute_interpreter_state(const Register state, ++ const Register prev_state, ++ bool native) { ++ Unimplemented(); ++} ++ ++void InterpreterGenerator::lock_method(void) { ++ Unimplemented(); ++} ++ ++void CppInterpreterGenerator::generate_deopt_handling() { ++ Unimplemented(); ++} ++ ++void CppInterpreterGenerator::generate_more_monitors() { ++ Unimplemented(); ++} ++ ++ ++static address interpreter_frame_manager = NULL; ++ ++void CppInterpreterGenerator::adjust_callers_stack(Register args) { ++ Unimplemented(); ++} ++ ++address InterpreterGenerator::generate_normal_entry(bool synchronized) { ++ Unimplemented(); ++} ++ ++InterpreterGenerator::InterpreterGenerator(StubQueue* code) ++ : CppInterpreterGenerator(code) { ++ Unimplemented(); ++} ++ ++ ++static int size_activation_helper(int callee_extra_locals, int max_stack, int monitor_size) { ++ Unimplemented(); ++} ++ ++int AbstractInterpreter::size_top_interpreter_activation(methodOop method) { ++ Unimplemented(); ++} ++ ++void BytecodeInterpreter::layout_interpreterState(interpreterState to_fill, ++ frame* caller, ++ frame* current, ++ methodOop method, ++ intptr_t* locals, ++ intptr_t* stack, ++ intptr_t* stack_base, ++ intptr_t* monitor_base, ++ intptr_t* frame_bottom, ++ bool is_top_frame ++ ) ++{ ++ Unimplemented(); ++} ++ ++void BytecodeInterpreter::pd_layout_interpreterState(interpreterState istate, address last_Java_pc, intptr_t* last_Java_fp) { ++ Unimplemented(); ++} ++ ++ ++int AbstractInterpreter::layout_activation(methodOop method, ++ int tempcount, // Number of slots on java expression stack in use ++ int popframe_extra_args, ++ int moncount, // Number of active monitors ++ int callee_param_size, ++ int callee_locals_size, ++ frame* caller, ++ frame* interpreter_frame, ++ bool is_top_frame) { ++ Unimplemented(); ++} ++ ++#endif // CC_INTERP +diff --git a/hotspot/src/cpu/sw64/vm/cppInterpreter_sw64.hpp b/hotspot/src/cpu/sw64/vm/cppInterpreter_sw64.hpp +new file mode 100755 +index 0000000000..5fb1d1f066 +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/cppInterpreter_sw64.hpp +@@ -0,0 +1,39 @@ ++/* ++ * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_SW64_VM_CPPINTERPRETER_SW64_HPP ++#define CPU_SW64_VM_CPPINTERPRETER_SW64_HPP ++ // Size of interpreter code. Increase if too small. Interpreter will ++ // fail with a guarantee ("not enough space for interpreter generation"); ++ // if too small. ++ // Run with +PrintInterpreter to get the VM to print out the size. ++ // Max size with JVMTI and TaggedStackInterpreter ++ ++ // QQQ this is proably way too large for c++ interpreter ++ ++ // The sethi() instruction generates lots more instructions when shell ++ // stack limit is unlimited, so that's why this is much bigger. ++ const static int InterpreterCodeSize = 210 * K; ++ ++#endif // CPU_SW64_VM_CPPINTERPRETER_SW64_HPP +diff --git a/hotspot/src/cpu/sw64/vm/debug_sw64.cpp b/hotspot/src/cpu/sw64/vm/debug_sw64.cpp +new file mode 100755 +index 0000000000..4dc2998756 +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/debug_sw64.cpp +@@ -0,0 +1,50 @@ ++/* ++ * Copyright (c) 1999, 2010, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#include "precompiled.hpp" ++#include "code/codeCache.hpp" ++#include "code/nmethod.hpp" ++#include "runtime/frame.hpp" ++#include "runtime/init.hpp" ++#include "runtime/os.hpp" ++#include "utilities/debug.hpp" ++#include "utilities/top.hpp" ++ ++#ifndef PRODUCT ++ ++void pd_ps(frame f) { ++ intptr_t* sp = f.sp(); ++ intptr_t* prev_sp = sp - 1; ++ intptr_t *pc = NULL; ++ intptr_t *next_pc = NULL; ++ int count = 0; ++ tty->print("register window backtrace from %#x:\n", sp); ++} ++ ++// This function is used to add platform specific info ++// to the error reporting code. ++ ++void pd_obfuscate_location(char *buf,int buflen) {} ++ ++#endif // PRODUCT +diff --git a/hotspot/src/cpu/sw64/vm/depChecker_sw64.cpp b/hotspot/src/cpu/sw64/vm/depChecker_sw64.cpp +new file mode 100755 +index 0000000000..a4fb933fe5 +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/depChecker_sw64.cpp +@@ -0,0 +1,29 @@ ++/* ++ * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#include "precompiled.hpp" ++#include "compiler/disassembler.hpp" ++#include "depChecker_sw64.hpp" ++ ++// Nothing to do on sw64 +diff --git a/hotspot/src/cpu/sw64/vm/depChecker_sw64.hpp b/hotspot/src/cpu/sw64/vm/depChecker_sw64.hpp +new file mode 100755 +index 0000000000..4b9498af87 +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/depChecker_sw64.hpp +@@ -0,0 +1,30 @@ ++/* ++ * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_SW64_VM_DEPCHECKER_SW64_HPP ++#define CPU_SW64_VM_DEPCHECKER_SW64_HPP ++ ++// Nothing to do on SW64 ++ ++#endif // CPU_SW64_VM_DEPCHECKER_SW64_HPP +diff --git a/hotspot/src/cpu/sw64/vm/disassembler_sw64.cpp b/hotspot/src/cpu/sw64/vm/disassembler_sw64.cpp +new file mode 100755 +index 0000000000..851c1d7d3c +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/disassembler_sw64.cpp +@@ -0,0 +1,23 @@ ++/* ++ * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ +\ No newline at end of file +diff --git a/hotspot/src/cpu/sw64/vm/disassembler_sw64.hpp b/hotspot/src/cpu/sw64/vm/disassembler_sw64.hpp +new file mode 100755 +index 0000000000..4c7e959044 +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/disassembler_sw64.hpp +@@ -0,0 +1,36 @@ ++/* ++ * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_SW64_VM_DISASSEMBLER_SW64_HPP ++#define CPU_SW64_VM_DISASSEMBLER_SW64_HPP ++ ++ static int pd_instruction_alignment() { ++ return sizeof(int); ++ } ++ ++ static const char* pd_cpu_opts() { ++ return "sw64only"; ++ } ++ ++#endif // CPU_SW64_VM_DISASSEMBLER_SW64_HPP +diff --git a/hotspot/src/cpu/sw64/vm/frame_sw64.cpp b/hotspot/src/cpu/sw64/vm/frame_sw64.cpp +new file mode 100755 +index 0000000000..54f5a95f8d +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/frame_sw64.cpp +@@ -0,0 +1,668 @@ ++/* ++ * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#include "precompiled.hpp" ++#include "interpreter/interpreter.hpp" ++#include "memory/resourceArea.hpp" ++#include "oops/markOop.hpp" ++#include "oops/method.hpp" ++#include "oops/oop.inline.hpp" ++#include "prims/methodHandles.hpp" ++#include "runtime/frame.inline.hpp" ++#include "runtime/handles.inline.hpp" ++#include "runtime/javaCalls.hpp" ++#include "runtime/monitorChunk.hpp" ++#include "runtime/signature.hpp" ++#include "runtime/stubCodeGenerator.hpp" ++#include "runtime/stubRoutines.hpp" ++#include "vmreg_sw64.inline.hpp" ++#ifdef COMPILER1 ++#include "c1/c1_Runtime1.hpp" ++#include "runtime/vframeArray.hpp" ++#endif ++ ++#ifdef ASSERT ++void RegisterMap::check_location_valid() { ++} ++#endif ++ ++ ++// Profiling/safepoint support ++// for Profiling - acting on another frame. walks sender frames ++// if valid. ++// frame profile_find_Java_sender_frame(JavaThread *thread); ++ ++bool frame::safe_for_sender(JavaThread *thread) { ++ address sp = (address)_sp; ++ address fp = (address)_fp; ++ bool sp_safe = (sp != NULL && ++ (sp <= thread->stack_base()) && ++ (sp >= thread->stack_base() - thread->stack_size())); ++ bool fp_safe = (fp != NULL && ++ (fp <= thread->stack_base()) && ++ (fp >= thread->stack_base() - thread->stack_size())); ++ ++ // init_sender_for_c_frame can only be called when fp is guarenteed be safe. ++ if(_is_c_frame && !_is_sender_for_c_frame_initialized && fp_safe)init_sender_for_c_frame(); ++ ++ if (sp_safe && fp_safe) { ++ CodeBlob *cb = CodeCache::find_blob_unsafe(_pc); ++ // First check if frame is complete and tester is reliable ++ // Unfortunately we can only check frame complete for runtime stubs and nmethod ++ // other generic buffer blobs are more problematic so we just assume they are ++ // ok. adapter blobs never have a frame complete and are never ok. ++ if (cb != NULL){ ++ // `is_frame_complete_at` always return true for `AdapterBlob`? ++ if(cb->is_adapter_blob())return false; ++ // no `fp` and `ra` saved. ++ if(!is_interpreted_frame()) ++ if(0 == cb->frame_size())return false; ++ ++ if (!cb->is_frame_complete_at(_pc) && (cb->is_nmethod() || cb->is_runtime_stub())) { ++ return false; ++ } ++ } ++ return true; ++ } ++ // Note: fp == NULL is not really a prerequisite for this to be safe to ++ // walk for c2. However we've modified the code such that if we get ++ // a failure with fp != NULL that we then try with FP == NULL. ++ // This is basically to mimic what a last_frame would look like if ++ // c2 had generated it. ++ if (sp_safe && fp == NULL) { ++ CodeBlob *cb = CodeCache::find_blob_unsafe(_pc); ++ // frame must be complete if fp == NULL as fp == NULL is only sensible ++ // if we are looking at a nmethod and frame complete assures us of that. ++ if (cb != NULL && cb->is_frame_complete_at(_pc) && cb->is_compiled_by_c2()) { ++ return true; ++ } ++ } ++ return false; ++} ++ ++ ++void frame::patch_pc(Thread* thread, address pc) { ++ if (TracePcPatching) { ++ tty->print_cr("patch_pc at address 0x%x [0x%x -> 0x%x] ", &((address *)_sp)[-1], ((address *)_sp)[-1], pc); ++ } ++ ++ RegisterMap map((JavaThread *)thread, false); ++ frame check = ((JavaThread *)thread)->last_frame(); ++ if (id() != check.id()) ++ { ++ while (id() != check.sender(&map).id()) { ++ check = check.sender(&map); ++ } ++ if (check.is_interpreted_frame()) ++ *(check.fp() + 1) = (intptr_t)pc; ++ else ++ ((address *)_sp)[-1] = pc; ++ } ++ ++ _cb = CodeCache::find_blob(pc); ++ if (_cb != NULL && _cb->is_nmethod() && ((nmethod*)_cb)->is_deopt_pc(_pc)) { ++ address orig = (((nmethod*)_cb)->get_original_pc(this)); ++ assert(orig == _pc, "expected original to be stored before patching"); ++ _deopt_state = is_deoptimized; ++ // leave _pc as is ++ } else { ++ _deopt_state = not_deoptimized; ++ _pc = pc; ++ } ++} ++ ++bool frame::is_interpreted_frame() const { ++ return Interpreter::contains(pc()); ++} ++ ++int frame::frame_size(RegisterMap* map) const { ++ frame sender = this->sender(map); ++ return sender.sp() - sp(); ++} ++ ++intptr_t* frame::entry_frame_argument_at(int offset) const { ++ // convert offset to index to deal with tsi ++ int index = (Interpreter::expr_offset_in_bytes(offset)/wordSize); ++ // Entry frame's arguments are always in relation to unextended_sp() ++ return &unextended_sp()[index]; ++} ++ ++// sender_sp ++#ifdef CC_INTERP ++intptr_t* frame::interpreter_frame_sender_sp() const { ++ assert(is_interpreted_frame(), "interpreted frame expected"); ++ // QQQ why does this specialize method exist if frame::sender_sp() does same thing? ++ // seems odd and if we always know interpreted vs. non then sender_sp() is really ++ // doing too much work. ++ return get_interpreterState()->sender_sp(); ++} ++ ++// monitor elements ++ ++BasicObjectLock* frame::interpreter_frame_monitor_begin() const { ++ return get_interpreterState()->monitor_base(); ++} ++ ++BasicObjectLock* frame::interpreter_frame_monitor_end() const { ++ return (BasicObjectLock*) get_interpreterState()->stack_base(); ++} ++ ++#else // CC_INTERP ++ ++intptr_t* frame::interpreter_frame_sender_sp() const { ++ assert(is_interpreted_frame(), "interpreted frame expected"); ++ return (intptr_t*) at(interpreter_frame_sender_sp_offset); ++} ++ ++void frame::set_interpreter_frame_sender_sp(intptr_t* sender_sp) { ++ assert(is_interpreted_frame(), "interpreted frame expected"); ++ int_at_put(interpreter_frame_sender_sp_offset, (intptr_t) sender_sp); ++} ++ ++ ++// monitor elements ++ ++BasicObjectLock* frame::interpreter_frame_monitor_begin() const { ++ return (BasicObjectLock*) addr_at(interpreter_frame_monitor_block_bottom_offset); ++} ++ ++BasicObjectLock* frame::interpreter_frame_monitor_end() const { ++ BasicObjectLock* result = (BasicObjectLock*) *addr_at(interpreter_frame_monitor_block_top_offset); ++ // make sure the pointer points inside the frame ++ assert((intptr_t) fp() > (intptr_t) result, "result must < than frame pointer"); ++ assert((intptr_t) sp() <= (intptr_t) result, "result must >= than stack pointer"); ++ return result; ++} ++ ++void frame::interpreter_frame_set_monitor_end(BasicObjectLock* value) { ++ *((BasicObjectLock**)addr_at(interpreter_frame_monitor_block_top_offset)) = value; ++} ++ ++// Used by template based interpreter deoptimization ++void frame::interpreter_frame_set_last_sp(intptr_t* sp) { ++ *((intptr_t**)addr_at(interpreter_frame_last_sp_offset)) = sp; ++} ++#endif // CC_INTERP ++ ++frame frame::sender_for_entry_frame(RegisterMap* map) const { ++ assert(map != NULL, "map must be set"); ++ // Java frame called from C; skip all C frames and return top C ++ // frame of that chunk as the sender ++ JavaFrameAnchor* jfa = entry_frame_call_wrapper()->anchor(); ++ assert(!entry_frame_is_first(), "next Java fp must be non zero"); ++ assert(jfa->last_Java_sp() > sp(), "must be above this frame on stack"); ++ map->clear(); ++ assert(map->include_argument_oops(), "should be set by clear"); ++ if (jfa->last_Java_pc() != NULL ) { ++ frame fr(jfa->last_Java_sp(), jfa->last_Java_fp(), jfa->last_Java_pc()); ++ return fr; ++ } ++ frame fr(jfa->last_Java_sp(), jfa->last_Java_fp()); ++ return fr; ++} ++ ++frame frame::sender_for_interpreter_frame(RegisterMap* map) const { ++ // sp is the raw sp from the sender after adapter or interpreter extension ++ intptr_t* sp = (intptr_t*) at(interpreter_frame_sender_sp_offset); ++ ++ // This is the sp before any possible extension (adapter/locals). ++ //intptr_t* unextended_sp = interpreter_frame_sender_sp(); ++ ++ // The interpreter and compiler(s) always save FP in a known ++ // location on entry. We must record where that location is ++ // so this if FP was live on callout from c2 we can find ++ // the saved copy no matter what it called. ++ ++ // Since the interpreter always saves FP if we record where it is then ++ // we don't have to always save FP on entry and exit to c2 compiled ++ // code, on entry will be enough. ++#ifdef COMPILER2 ++ if (map->update_map()) { ++ map->set_location(FP->as_VMReg(), (address) addr_at(link_offset)); ++ } ++#endif /* COMPILER2 */ ++ return frame(sp, link(), sender_pc()); ++} ++ ++ ++//------------------------------------------------------------------------------ ++// frame::verify_deopt_original_pc ++// ++// Verifies the calculated original PC of a deoptimization PC for the ++// given unextended SP. The unextended SP might also be the saved SP ++// for MethodHandle call sites. ++#ifdef ASSERT ++void frame::verify_deopt_original_pc(nmethod* nm, intptr_t* unextended_sp, bool is_method_handle_return) { ++ frame fr; ++ ++ // This is ugly but it's better than to change {get,set}_original_pc ++ // to take an SP value as argument. And it's only a debugging ++ // method anyway. ++ fr._unextended_sp = unextended_sp; ++ ++ address original_pc = nm->get_original_pc(&fr); ++ assert(nm->insts_contains(original_pc), "original PC must be in nmethod"); ++ assert(nm->is_method_handle_return(original_pc) == is_method_handle_return, "must be"); ++} ++#endif ++ ++ ++//------------------------------------------------------------------------------ ++// frame::adjust_unextended_sp ++void frame::adjust_unextended_sp() { ++ // On SW64, sites calling method handle intrinsics and lambda forms are treated ++ // as any other call site. Therefore, no special action is needed when we are ++ // returning to any of these call sites. ++ ++ nmethod* sender_nm = (_cb == NULL) ? NULL : _cb->as_nmethod_or_null(); ++ if (sender_nm != NULL) { ++ // If the sender PC is a deoptimization point, get the original PC. ++ if (sender_nm->is_deopt_entry(_pc) || ++ sender_nm->is_deopt_mh_entry(_pc)) { ++ DEBUG_ONLY(verify_deopt_original_pc(sender_nm, _unextended_sp)); ++ } ++ } ++} ++ ++//------------------------------sender_for_compiled_frame----------------------- ++frame frame::sender_for_compiled_frame(RegisterMap* map) const { ++ assert(map != NULL, "map must be set"); ++ ++ // frame owned by optimizing compiler ++ assert(_cb->frame_size() >= 0, "must have non-zero frame size"); ++ ++ intptr_t* sender_sp = sender_sp = sp() + _cb->frame_size(); ++#ifdef ASSERT ++ const bool c1_compiled = _cb->is_compiled_by_c1(); ++ bool native = _cb->is_nmethod() && ((nmethod*)_cb)->is_native_method(); ++ if (c1_compiled && native) { ++ assert(sender_sp == fp() + frame::sender_sp_offset, "incorrect frame size"); ++ } ++#endif // ASSERT ++ // On Intel the return_address is always the word on the stack ++ // the fp in compiler points to sender fp, but in interpreter, fp points to return address, ++ // so getting sender for compiled frame is not same as interpreter frame. ++ // we hard code here temporarily ++ // spark ++ address sender_pc = (address) *(sender_sp-1); ++ ++ intptr_t** saved_fp_addr = (intptr_t**) (sender_sp - frame::sender_sp_offset); ++ ++ if (map->update_map()) { ++ // Tell GC to use argument oopmaps for some runtime stubs that need it. ++ // For C1, the runtime stub might not have oop maps, so set this flag ++ // outside of update_register_map. ++ map->set_include_argument_oops(_cb->caller_must_gc_arguments(map->thread())); ++ if (_cb->oop_maps() != NULL) { ++ OopMapSet::update_register_map(this, map); ++ } ++ ++ // Since the prolog does the save and restore of epb there is no oopmap ++ // for it so we must fill in its location as if there was an oopmap entry ++ // since if our caller was compiled code there could be live jvm state in it. ++ map->set_location(FP->as_VMReg(), (address) saved_fp_addr); ++ } ++ assert(sender_sp != sp(), "must have changed"); ++ return frame(sender_sp, *saved_fp_addr, sender_pc); ++} ++ ++frame frame::sender(RegisterMap* map) const { ++ // Default is we done have to follow them. The sender_for_xxx will ++ // update it accordingly ++ map->set_include_argument_oops(false); ++ ++ if (is_entry_frame()) return sender_for_entry_frame(map); ++ if (is_interpreted_frame()) return sender_for_interpreter_frame(map); ++ assert(_cb == CodeCache::find_blob(pc()),"Must be the same"); ++ ++ if (_cb != NULL) { ++ return sender_for_compiled_frame(map); ++ } ++ // Must be native-compiled frame, i.e. the marshaling code for native ++ // methods that exists in the core system. ++ frame ret(sender_sp(), link(), sender_pc()); ++ ++ // For compiled sender frame with locals, sp and fp should never equal, but if ++ // the callee is native frame, it will set sp == fp, this is definitly a mistake. ++ // So fix sp here according to the frame size. ++ if(_is_c_frame)ret.fix_sp(); ++ ++ return ret; ++} ++ ++void frame::fix_sp(){ ++ if(is_compiled_frame() && _sp == _fp && 2 < _cb->frame_size()){ ++ assert(NULL != _sp, "sp can't be NULL."); ++ _sp = _sp - (_cb->frame_size() - 2); ++ _unextended_sp = _sp; ++ } ++} ++ ++ ++bool frame::interpreter_frame_equals_unpacked_fp(intptr_t* fp) { ++ assert(is_interpreted_frame(), "must be interpreter frame"); ++ Method* method = interpreter_frame_method(); ++ // When unpacking an optimized frame the frame pointer is ++ // adjusted with: ++ int diff = (method->max_locals() - method->size_of_parameters()) * ++ Interpreter::stackElementWords; ++ printf("^^^^^^^^^^^^^^^adjust fp in deopt fp = 0%x \n", (intptr_t)(fp - diff)); ++ return _fp == (fp - diff); ++} ++ ++void frame::pd_gc_epilog() { ++ // nothing done here now ++} ++ ++bool frame::is_interpreted_frame_valid(JavaThread* thread) const { ++// QQQ ++#ifdef CC_INTERP ++#else ++ assert(is_interpreted_frame(), "Not an interpreted frame"); ++ // These are reasonable sanity checks ++ if (fp() == 0 || (intptr_t(fp()) & (wordSize-1)) != 0) { ++ return false; ++ } ++ if (sp() == 0 || (intptr_t(sp()) & (wordSize-1)) != 0) { ++ return false; ++ } ++ if (fp() + interpreter_frame_initial_sp_offset < sp()) { ++ return false; ++ } ++ // These are hacks to keep us out of trouble. ++ // The problem with these is that they mask other problems ++ if (fp() <= sp()) { // this attempts to deal with unsigned comparison above ++ return false; ++ } ++ ++ // do some validation of frame elements ++ ++ // first the method ++ ++ Method* m = *interpreter_frame_method_addr(); ++ ++ // validate the method we'd find in this potential sender ++ if (!m->is_valid_method()) return false; ++ ++ // stack frames shouldn't be much larger than max_stack elements ++ ++ //if (fp() - sp() > 1024 + m->max_stack()*Interpreter::stackElementSize()) { ++ if (fp() - sp() > 4096) { // stack frames shouldn't be large. ++ return false; ++ } ++ ++ // validate bci/bcx ++ ++ intptr_t bcx = interpreter_frame_bcx(); ++ if (m->validate_bci_from_bcx(bcx) < 0) { ++ return false; ++ } ++ ++ // validate ConstantPoolCache* ++ ++ ConstantPoolCache* cp = *interpreter_frame_cache_addr(); ++ ++ if (cp == NULL || !cp->is_metaspace_object()) return false; ++ ++ // validate locals ++ ++ address locals = (address) *interpreter_frame_locals_addr(); ++ ++ if (locals > thread->stack_base() || locals < (address) fp()) return false; ++ ++ // We'd have to be pretty unlucky to be mislead at this point ++ ++#endif // CC_INTERP ++ return true; ++} ++ ++BasicType frame::interpreter_frame_result(oop* oop_result, jvalue* value_result) { ++#ifdef CC_INTERP ++ // Needed for JVMTI. The result should always be in the interpreterState object ++ assert(false, "NYI"); ++ interpreterState istate = get_interpreterState(); ++#endif // CC_INTERP ++ assert(is_interpreted_frame(), "interpreted frame expected"); ++ Method* method = interpreter_frame_method(); ++ BasicType type = method->result_type(); ++ ++ intptr_t* tos_addr; ++ if (method->is_native()) { ++ // Prior to calling into the runtime to report the method_exit the possible ++ // return value is pushed to the native stack. If the result is a jfloat/jdouble ++ // then ST0 is saved. See the note in generate_native_result ++ tos_addr = (intptr_t*)sp(); ++ if (type == T_FLOAT || type == T_DOUBLE) { ++ tos_addr += 2; ++ } ++ } else { ++ tos_addr = (intptr_t*)interpreter_frame_tos_address(); ++ } ++ ++ switch (type) { ++ case T_OBJECT : ++ case T_ARRAY : { ++ oop obj; ++ if (method->is_native()) { ++#ifdef CC_INTERP ++ obj = istate->_oop_temp; ++#else ++ obj = cast_to_oop(at(interpreter_frame_oop_temp_offset)); ++#endif // CC_INTERP ++ } else { ++ oop* obj_p = (oop*)tos_addr; ++ obj = (obj_p == NULL) ? (oop)NULL : *obj_p; ++ } ++ assert(obj == NULL || Universe::heap()->is_in(obj), "sanity check"); ++ *oop_result = obj; ++ break; ++ } ++ case T_BOOLEAN : value_result->z = *(jboolean*)tos_addr; break; ++ case T_BYTE : value_result->b = *(jbyte*)tos_addr; break; ++ case T_CHAR : value_result->c = *(jchar*)tos_addr; break; ++ case T_SHORT : value_result->s = *(jshort*)tos_addr; break; ++ case T_INT : value_result->i = *(jint*)tos_addr; break; ++ case T_LONG : value_result->j = *(jlong*)tos_addr; break; ++ case T_FLOAT : value_result->f = *(jfloat*)tos_addr; break; ++// yj not sure ++// case T_FLOAT : { ++// if (method->is_native()) { ++// jdouble d = *(jdouble*)tos_addr; // Result was in ST0 so need to convert to jfloat ++// value_result->f = (jfloat)d; ++// } else { ++// value_result->f = *(jfloat*)tos_addr; ++// } ++// break; ++// } ++ case T_DOUBLE : value_result->d = *(jdouble*)tos_addr; break; ++ case T_VOID : /* Nothing to do */ break; ++ default : ShouldNotReachHere(); ++ } ++ ++ return type; ++} ++ ++ ++intptr_t* frame::interpreter_frame_tos_at(jint offset) const { ++ int index = (Interpreter::expr_offset_in_bytes(offset)/wordSize); ++ return &interpreter_frame_tos_address()[index]; ++} ++ ++#ifndef PRODUCT ++ ++#define DESCRIBE_FP_OFFSET(name) \ ++ values.describe(frame_no, fp() + frame::name##_offset, #name) ++ ++void frame::describe_pd(FrameValues& values, int frame_no) { ++ if (is_interpreted_frame()) { ++ DESCRIBE_FP_OFFSET(interpreter_frame_sender_sp); ++ DESCRIBE_FP_OFFSET(interpreter_frame_last_sp); ++ DESCRIBE_FP_OFFSET(interpreter_frame_method); ++ DESCRIBE_FP_OFFSET(interpreter_frame_mdx); ++ DESCRIBE_FP_OFFSET(interpreter_frame_cache); ++ DESCRIBE_FP_OFFSET(interpreter_frame_locals); ++ DESCRIBE_FP_OFFSET(interpreter_frame_bcx); ++ DESCRIBE_FP_OFFSET(interpreter_frame_initial_sp); ++ } ++} ++#endif ++ ++intptr_t *frame::initial_deoptimization_info() { ++ // used to reset the saved FP ++ return fp(); ++} ++ ++intptr_t* frame::real_fp() const { ++ if (_cb != NULL) { ++ // use the frame size if valid ++ int size = _cb->frame_size(); ++ if (size > 0) { ++ return unextended_sp() + size; ++ } ++ } ++ // else rely on fp() ++ assert(! is_compiled_frame(), "unknown compiled frame size"); ++ return fp(); ++} ++ ++ ++void frame::init(intptr_t* sp, intptr_t* fp, address pc) { ++ _sp = sp; ++ _unextended_sp = sp; ++ _fp = fp; ++ _pc = pc; ++ assert(pc != NULL, "no pc?"); ++ _cb = CodeCache::find_blob(pc); ++ adjust_unextended_sp(); ++ ++ address original_pc = nmethod::get_deopt_original_pc(this); ++ if (original_pc != NULL) { ++ _pc = original_pc; ++ _deopt_state = is_deoptimized; ++ } else { ++ _deopt_state = not_deoptimized; ++ } ++ ++ _sender_fp_for_c_frame = NULL; ++ _sender_address_for_c_frame = NULL; ++ ++ if (is_java_frame() || ++ is_native_frame() || ++ is_runtime_frame() || ++ is_stub_frame()) { ++ _is_c_frame = false; ++ _is_sender_for_c_frame_initialized = true; ++ }else{ ++ _is_c_frame = true; ++ _is_sender_for_c_frame_initialized = false; ++ } ++} ++ ++void frame::init_sender_for_c_frame() { ++ _is_sender_for_c_frame_initialized = true; ++ if(!_is_c_frame)return; ++ if (_fp == NULL) return; ++ if ((long)_pc < 0x8000000 || (long)_pc > 0x4000000000000000) return; ++ bool stop_flag = false; ++ address pinsn = _pc ; ++ while ((_sender_fp_for_c_frame == NULL || _sender_address_for_c_frame == NULL) && (*((int *) pinsn)) && !stop_flag) { ++ int insn = *((int *) pinsn); ++ if (_sender_fp_for_c_frame == NULL && (insn & 0xffff0000) == 0xadfe0000) { // stl fp,yy(sp) ++ int yy = (insn & 0x0000ffff) / 8; ++ _sender_fp_for_c_frame = (intptr_t *) (*(_fp + yy)); ++ } else if ( _sender_address_for_c_frame == NULL && (insn & 0xffff0000) == 0xaf5e0000) { // stl ra,xx(sp) ++ int xx = (insn & 0x0000ffff) / 8; ++ _sender_address_for_c_frame = (address) (*(_fp + xx)); ++ } else if ((insn & 0xffff0000) == 0xffbb0000){ // ldih gp,zz(t12) ++ stop_flag = true; ++ } ++ pinsn -= 4; ++ // scan function to _pc ++ } ++} ++void frame::init_sender_for_c_frame(address f_start_pc) { ++ do{ ++ int insn = *((int *) f_start_pc); ++ if ( _sender_address_for_c_frame == NULL && (insn & 0xffff0000) == 0xaf5e0000) { // stl ra,xx(sp) ++ int xx = (insn & 0x0000ffff) / 8; ++ _sender_address_for_c_frame = (address) (*(_sp + xx)); ++ } else if (_sender_fp_for_c_frame == NULL && (insn & 0xffff0000) == 0xadfe0000) { // stl fp,yy(sp) ++ int yy = (insn & 0x0000ffff) / 8; ++ _sender_fp_for_c_frame = (intptr_t *) (*(_sp + yy)); ++ } ++ f_start_pc += 4; ++ // scan function to _pc ++ } while ((_sender_fp_for_c_frame == NULL || _sender_address_for_c_frame == NULL) && (*((int *) f_start_pc))); ++} ++// when thread stop before stl ra at stack ++void frame::fixRa(const void* ucVoid) { ++ if (!_is_c_frame) return; ++ if (_sender_address_for_c_frame != NULL) { ++ return; ++ } else { ++ const ucontext_t *uc = (const ucontext_t *) ucVoid; ++ if (uc != NULL) { ++ _sender_address_for_c_frame = os::ucontext_get_ra(uc); ++ } else { ++ _sender_address_for_c_frame = NULL; ++ } ++ } ++} ++ ++intptr_t* frame::sender_sp() const { ++ if (_is_c_frame) { ++ assert(_is_sender_for_c_frame_initialized, "safe_for_sender must be called first."); ++ return _sender_fp_for_c_frame;// for sw C frame, sp is always the same as fp ++ } else { ++ return addr_at(sender_sp_offset); ++ } ++} ++ ++intptr_t* frame::link() const { ++ if (_is_c_frame) ++ { ++ assert(_is_sender_for_c_frame_initialized, "safe_for_sender must be called first."); ++ return _sender_fp_for_c_frame; ++ } ++ else ++ return (intptr_t*) *(intptr_t **)addr_at(link_offset); ++} ++ ++address frame::sender_pc() const { ++ if (_is_c_frame) ++ { ++ assert(_is_sender_for_c_frame_initialized, "safe_for_sender must be called first."); ++ return _sender_address_for_c_frame; ++ } ++ else { ++ return *sender_pc_addr(); ++ } ++} ++ ++#ifndef PRODUCT ++// This is a generic constructor which is only used by pns() in debug.cpp. ++frame::frame(void* sp, void* fp, void* pc) { ++ init((intptr_t*)sp, (intptr_t*)fp, (address)pc); ++} ++#endif +diff --git a/hotspot/src/cpu/sw64/vm/frame_sw64.hpp b/hotspot/src/cpu/sw64/vm/frame_sw64.hpp +new file mode 100755 +index 0000000000..c4a87858b0 +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/frame_sw64.hpp +@@ -0,0 +1,233 @@ ++/* ++ * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_SW64_VM_FRAME_SW64_HPP ++#define CPU_SW64_VM_FRAME_SW64_HPP ++ ++#include "runtime/synchronizer.hpp" ++#include "utilities/top.hpp" ++ ++// A frame represents a physical stack frame (an activation). Frames can be ++// C or Java frames, and the Java frames can be interpreted or compiled. ++// In contrast, vframes represent source-level activations, so that one physical frame ++// can correspond to multiple source level frames because of inlining. ++// A frame is comprised of {pc, fp, sp} ++// ------------------------------ Asm interpreter ---------------------------------------- ++// Layout of asm interpreter frame: ++// [expression stack ] * <- sp ++// [monitors ] \ ++// ... | monitor block size ++// [monitors ] / ++// [monitor block size ] ++// [byte code index/pointr] = bcx() bcx_offset ++// [pointer to locals ] = locals() locals_offset ++// [constant pool cache ] = cache() cache_offset ++// [methodData ] = mdp() mdx_offset ++// [methodOop ] = method() method_offset ++// [last sp ] = last_sp() last_sp_offset ++// [old stack pointer ] (sender_sp) sender_sp_offset ++// [old frame pointer ] <- fp = link() ++// [return pc ] ++// [oop temp ] (only for native calls) ++// [locals and parameters ] ++// <- sender sp ++// ------------------------------ Asm interpreter ---------------------------------------- ++ ++// ------------------------------ C++ interpreter ---------------------------------------- ++// ++// Layout of C++ interpreter frame: (While executing in BytecodeInterpreter::run) ++// ++// <- SP (current sp) ++// [local variables ] BytecodeInterpreter::run local variables ++// ... BytecodeInterpreter::run local variables ++// [local variables ] BytecodeInterpreter::run local variables ++// [old frame pointer ] fp [ BytecodeInterpreter::run's fp ] ++// [return pc ] (return to frame manager) ++// [interpreter_state* ] (arg to BytecodeInterpreter::run) -------------- ++// [expression stack ] <- last_Java_sp | ++// [... ] * <- interpreter_state.stack | ++// [expression stack ] * <- interpreter_state.stack_base | ++// [monitors ] \ | ++// ... | monitor block size | ++// [monitors ] / <- interpreter_state.monitor_base | ++// [struct interpretState ] <-----------------------------------------| ++// [return pc ] (return to callee of frame manager [1] ++// [locals and parameters ] ++// <- sender sp ++ ++// [1] When the c++ interpreter calls a new method it returns to the frame ++// manager which allocates a new frame on the stack. In that case there ++// is no real callee of this newly allocated frame. The frame manager is ++// aware of the additional frame(s) and will pop them as nested calls ++// complete. Howevers tTo make it look good in the debugger the frame ++// manager actually installs a dummy pc pointing to RecursiveInterpreterActivation ++// with a fake interpreter_state* parameter to make it easy to debug ++// nested calls. ++ ++// Note that contrary to the layout for the assembly interpreter the ++// expression stack allocated for the C++ interpreter is full sized. ++// However this is not as bad as it seems as the interpreter frame_manager ++// will truncate the unused space on succesive method calls. ++// ++// ------------------------------ C++ interpreter ---------------------------------------- ++ ++// Layout of interpreter frame: ++// ++// [ monitor entry ] <--- sp ++// ... ++// [ monitor entry ] ++// -7 [ monitor block top ] ( the top monitor entry ) ++// -6 [ byte code pointer ] (if native, bcp = 0) ++// -5 [ constant pool cache ] ++// -4 [ methodData ] mdx_offset(not core only) ++// -3 [ methodOop ] ++// -2 [ locals offset ] ++// -1 [ sender's sp ] ++// 0 [ sender's fp ] <--fp ++// 1 [ return address ] ++// 2 [ oop temp offset ] (only for native calls) ++// 3 [ result handler offset ] (only for native calls) ++// 4 [ result type info ] (only for native calls) ++// [ local var m-1 ] ++// ... ++// [ local var 0 ] ++// [ argumnet word n-1 ] <--- ( sender's sp ) ++// ... ++// [ argument word 0 ] <--- S1 ++ ++ public: ++ enum { ++ pc_return_offset = 0, ++ // All frames ++ link_offset = 0, ++ return_addr_offset = 1, ++ // non-interpreter frames ++ sender_sp_offset = 2, ++ ++#ifndef CC_INTERP ++ ++ // Interpreter frames ++ interpreter_frame_return_addr_offset = 1, ++ interpreter_frame_result_handler_offset = 3, // for native calls only ++ interpreter_frame_oop_temp_offset = 2, // for native calls only ++ ++ interpreter_frame_sender_fp_offset = 0, ++ interpreter_frame_sender_sp_offset = -1, ++ // outgoing sp before a call to an invoked method ++ interpreter_frame_last_sp_offset = interpreter_frame_sender_sp_offset - 1, ++ interpreter_frame_locals_offset = interpreter_frame_last_sp_offset - 1, ++ interpreter_frame_method_offset = interpreter_frame_locals_offset - 1, ++ interpreter_frame_mdx_offset = interpreter_frame_method_offset - 1, ++ interpreter_frame_cache_offset = interpreter_frame_mdx_offset - 1, ++ interpreter_frame_bcx_offset = interpreter_frame_cache_offset - 1, ++ interpreter_frame_initial_sp_offset = interpreter_frame_bcx_offset - 1, ++ ++ interpreter_frame_monitor_block_top_offset = interpreter_frame_initial_sp_offset, ++ interpreter_frame_monitor_block_bottom_offset = interpreter_frame_initial_sp_offset, ++ ++#endif // CC_INTERP ++ ++ // Entry frames ++ entry_frame_call_wrapper_offset = -17, ++ ++ // Native frames ++ ++ native_frame_initial_param_offset = 2 ++ ++ }; ++ ++ intptr_t ptr_at(int offset) const { ++ return *ptr_at_addr(offset); ++ } ++ ++ void ptr_at_put(int offset, intptr_t value) { ++ *ptr_at_addr(offset) = value; ++ } ++ ++ void fix_sp(); ++ ++private: ++ // an additional field beyond _sp and _pc: ++ intptr_t* _fp; // frame pointer ++ // The interpreter and adapters will extend the frame of the caller. ++ // Since oopMaps are based on the sp of the caller before extension ++ // we need to know that value. However in order to compute the address ++ // of the return address we need the real "raw" sp. Since sparc already ++ // uses sp() to mean "raw" sp and unextended_sp() to mean the caller's ++ // original sp we use that convention. ++ bool _is_c_frame; ++ bool _is_sender_for_c_frame_initialized; ++ intptr_t* _sender_fp_for_c_frame; ++ address _sender_address_for_c_frame; ++ // The caller must guarantee fp is safe. ++ void init_sender_for_c_frame(); ++ ++ intptr_t* _unextended_sp; ++ void adjust_unextended_sp(); ++ ++ intptr_t* ptr_at_addr(int offset) const { ++ return (intptr_t*) addr_at(offset); ++ } ++#ifdef ASSERT ++ // Used in frame::sender_for_{interpreter,compiled}_frame ++ static void verify_deopt_original_pc( nmethod* nm, intptr_t* unextended_sp, bool is_method_handle_return = false); ++ static void verify_deopt_mh_original_pc(nmethod* nm, intptr_t* unextended_sp) { ++ verify_deopt_original_pc(nm, unextended_sp, true); ++ } ++#endif ++ ++ public: ++ // Constructors ++ ++ frame(intptr_t* sp, intptr_t* fp, address pc); ++ ++ frame(intptr_t* sp, intptr_t* unextended_sp, intptr_t* fp, address pc); ++ ++ frame(intptr_t* sp, intptr_t* fp); ++ ++ void init(intptr_t* sp, intptr_t* fp, address pc); ++ ++ // accessors for the instance variables ++ intptr_t* fp() const { return _fp; } ++ ++ inline address* sender_pc_addr() const; ++ ++ // return address of param, zero origin index. ++ inline address* native_param_addr(int idx) const; ++ ++ // expression stack tos if we are nested in a java call ++ intptr_t* interpreter_frame_last_sp() const; ++ void fixRa(const void* ucVoid); ++ void init_sender_for_c_frame(address f_start_pc); ++ ++#ifndef CC_INTERP ++ // deoptimization support ++ void interpreter_frame_set_last_sp(intptr_t* sp); ++#endif // CC_INTERP ++ ++#ifdef CC_INTERP ++ inline interpreterState get_interpreterState() const; ++#endif // CC_INTERP ++ ++#endif // CPU_SW64_VM_FRAME_SW64_HPP +diff --git a/hotspot/src/cpu/sw64/vm/frame_sw64.inline.hpp b/hotspot/src/cpu/sw64/vm/frame_sw64.inline.hpp +new file mode 100755 +index 0000000000..fa82f90d0e +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/frame_sw64.inline.hpp +@@ -0,0 +1,319 @@ ++/* ++ * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_SW64_VM_FRAME_SW64_INLINE_HPP ++#define CPU_SW64_VM_FRAME_SW64_INLINE_HPP ++ ++#include "code/codeCache.hpp" ++ ++// Inline functions for SW frames: ++ ++// Constructors: ++ ++inline frame::frame() { ++ _pc = NULL; ++ _sp = NULL; ++ _unextended_sp = NULL; ++ _fp = NULL; ++ _cb = NULL; ++ _deopt_state = unknown; ++} ++ ++//inline void frame::init(intptr_t* sp, intptr_t* fp, address pc) { ++// _sp = sp; ++// _unextended_sp = sp; ++// _fp = fp; ++// _pc = pc; ++// assert(pc != NULL, "no pc?"); ++// _cb = CodeCache::find_blob(pc); ++// adjust_unextended_sp(); ++// ++// address original_pc = nmethod::get_deopt_original_pc(this); ++// if (original_pc != NULL) { ++// _pc = original_pc; ++// _deopt_state = is_deoptimized; ++// } else { ++// _deopt_state = not_deoptimized; ++// } ++//} ++ ++inline frame::frame(intptr_t* sp, intptr_t* fp, address pc) { ++ init(sp, fp, pc); ++} ++ ++inline frame::frame(intptr_t* sp, intptr_t* unextended_sp, intptr_t* fp, address pc) { ++ _sp = sp; ++ _unextended_sp = unextended_sp; ++ _fp = fp; ++ _pc = pc; ++ assert(pc != NULL, "no pc?"); ++ _cb = CodeCache::find_blob(pc); ++ adjust_unextended_sp(); ++ ++ address original_pc = nmethod::get_deopt_original_pc(this); ++ if (original_pc != NULL) { ++ _pc = original_pc; ++ _deopt_state = is_deoptimized; ++ } else { ++ if (_cb->is_deoptimization_stub()) { ++ _deopt_state = is_deoptimized; ++ } else { ++ _deopt_state = not_deoptimized; ++ } ++ } ++ _is_c_frame = false; ++} ++ ++inline frame::frame(intptr_t* sp, intptr_t* fp) { ++ _sp = sp; ++ _unextended_sp = sp; ++ _fp = fp; ++ _pc = (address)(sp[-1]); ++ Unimplemented(); //ZHJ20170712 ++ ++ // Here's a sticky one. This constructor can be called via AsyncGetCallTrace ++ // when last_Java_sp is non-null but the pc fetched is junk. If we are truly ++ // unlucky the junk value could be to a zombied method and we'll die on the ++ // find_blob call. This is also why we can have no asserts on the validity ++ // of the pc we find here. AsyncGetCallTrace -> pd_get_top_frame_for_signal_handler ++ // -> pd_last_frame should use a specialized version of pd_last_frame which could ++ // call a specilaized frame constructor instead of this one. ++ // Then we could use the assert below. However this assert is of somewhat dubious ++ // value. ++ // assert(_pc != NULL, "no pc?"); ++ ++ _cb = CodeCache::find_blob(_pc); ++ adjust_unextended_sp(); ++ address original_pc = nmethod::get_deopt_original_pc(this); ++ if (original_pc != NULL) { ++ _pc = original_pc; ++ _deopt_state = is_deoptimized; ++ } else { ++ _deopt_state = not_deoptimized; ++ } ++} ++ ++// Accessors ++ ++inline bool frame::equal(frame other) const { ++ bool ret = sp() == other.sp() ++ && unextended_sp() == other.unextended_sp() ++ && fp() == other.fp() ++ && pc() == other.pc(); ++ assert(!ret || ret && cb() == other.cb() && _deopt_state == other._deopt_state, "inconsistent construction"); ++ return ret; ++} ++ ++// Return unique id for this frame. The id must have a value where we can distinguish ++// identity and younger/older relationship. NULL represents an invalid (incomparable) ++// frame. ++inline intptr_t* frame::id(void) const { return unextended_sp(); } ++ ++// Relationals on frames based ++// Return true if the frame is younger (more recent activation) than the frame represented by id ++inline bool frame::is_younger(intptr_t* id) const { assert(this->id() != NULL && id != NULL, "NULL frame id"); ++ return this->id() < id ; } ++ ++// Return true if the frame is older (less recent activation) than the frame represented by id ++inline bool frame::is_older(intptr_t* id) const { assert(this->id() != NULL && id != NULL, "NULL frame id"); ++ return this->id() > id ; } ++ ++ ++ ++//inline intptr_t* frame::link() const { return (intptr_t*) *(intptr_t **)addr_at(link_offset); } ++inline void frame::set_link(intptr_t* addr) { *(intptr_t **)addr_at(link_offset) = addr; } ++ ++ ++inline intptr_t* frame::unextended_sp() const { return _unextended_sp; } ++ ++// Return address: ++ ++inline address* frame::sender_pc_addr() const { return (address*) addr_at( return_addr_offset); } ++//inline address frame::sender_pc() const { return *sender_pc_addr(); } ++ ++// return address of param, zero origin index. ++inline address* frame::native_param_addr(int idx) const { return (address*) addr_at( native_frame_initial_param_offset+idx); } ++ ++#ifdef CC_INTERP ++ ++inline interpreterState frame::get_interpreterState() const { ++ return ((interpreterState)addr_at( -sizeof(BytecodeInterpreter)/wordSize )); ++} ++ ++inline intptr_t* frame::sender_sp() const { ++ // Hmm this seems awfully expensive QQQ, is this really called with interpreted frames? ++ if (is_interpreted_frame()) { ++ assert(false, "should never happen"); ++ return get_interpreterState()->sender_sp(); ++ } else { ++ return addr_at(sender_sp_offset); ++ } ++} ++ ++inline intptr_t** frame::interpreter_frame_locals_addr() const { ++ assert(is_interpreted_frame(), "must be interpreted"); ++ return &(get_interpreterState()->_locals); ++} ++ ++inline intptr_t* frame::interpreter_frame_bcx_addr() const { ++ assert(is_interpreted_frame(), "must be interpreted"); ++ return (intptr_t*) &(get_interpreterState()->_bcp); ++} ++ ++ ++// Constant pool cache ++ ++inline ConstantPoolCache** frame::interpreter_frame_cache_addr() const { ++ assert(is_interpreted_frame(), "must be interpreted"); ++ return &(get_interpreterState()->_constants); ++} ++ ++// Method ++ ++inline Method** frame::interpreter_frame_method_addr() const { ++ assert(is_interpreted_frame(), "must be interpreted"); ++ return &(get_interpreterState()->_method); ++} ++ ++inline intptr_t* frame::interpreter_frame_mdx_addr() const { ++ assert(is_interpreted_frame(), "must be interpreted"); ++ return (intptr_t*) &(get_interpreterState()->_mdx); ++} ++ ++// top of expression stack ++inline intptr_t* frame::interpreter_frame_tos_address() const { ++ assert(is_interpreted_frame(), "wrong frame type"); ++ return get_interpreterState()->_stack + 1; ++} ++ ++#else // asm interpreter ++//inline intptr_t* frame::sender_sp() const { return addr_at(sender_sp_offset); } ++ ++inline intptr_t** frame::interpreter_frame_locals_addr() const { ++ return (intptr_t**)addr_at(interpreter_frame_locals_offset); ++} ++ ++inline intptr_t* frame::interpreter_frame_last_sp() const { ++ return *(intptr_t**)addr_at(interpreter_frame_last_sp_offset); ++} ++ ++inline intptr_t* frame::interpreter_frame_bcx_addr() const { ++ return (intptr_t*)addr_at(interpreter_frame_bcx_offset); ++} ++ ++ ++inline intptr_t* frame::interpreter_frame_mdx_addr() const { ++ return (intptr_t*)addr_at(interpreter_frame_mdx_offset); ++} ++ ++ ++ ++// Constant pool cache ++ ++inline ConstantPoolCache** frame::interpreter_frame_cache_addr() const { ++ return (ConstantPoolCache**)addr_at(interpreter_frame_cache_offset); ++} ++ ++// Method ++ ++inline Method** frame::interpreter_frame_method_addr() const { ++ static Method* invalid_method = NULL; ++ if(NULL == _fp)return &invalid_method; ++ return (Method**)addr_at(interpreter_frame_method_offset); ++} ++ ++// top of expression stack ++inline intptr_t* frame::interpreter_frame_tos_address() const { ++ intptr_t* last_sp = interpreter_frame_last_sp(); ++ if (last_sp == NULL ) { ++ return sp(); ++ } else { ++ // sp() may have been extended by an adapter ++ assert(last_sp <= (intptr_t*)interpreter_frame_monitor_end(), "bad tos"); ++ return last_sp; ++ } ++} ++ ++inline oop* frame::interpreter_frame_temp_oop_addr() const { ++ return (oop *)(fp() + interpreter_frame_oop_temp_offset); ++} ++ ++#endif // CC_INTERP ++ ++inline int frame::pd_oop_map_offset_adjustment() const { ++ return 0; ++} ++ ++inline int frame::interpreter_frame_monitor_size() { ++ return BasicObjectLock::size(); ++} ++ ++ ++// expression stack ++// (the max_stack arguments are used by the GC; see class FrameClosure) ++ ++inline intptr_t* frame::interpreter_frame_expression_stack() const { ++ intptr_t* monitor_end = (intptr_t*) interpreter_frame_monitor_end(); ++ return monitor_end-1; ++} ++ ++ ++inline jint frame::interpreter_frame_expression_stack_direction() { return -1; } ++ ++ ++// Entry frames ++ ++inline JavaCallWrapper** frame::entry_frame_call_wrapper_addr() const { ++ return (JavaCallWrapper**)addr_at(entry_frame_call_wrapper_offset); ++} ++ ++// Compiled frames ++ ++inline int frame::local_offset_for_compiler(int local_index, int nof_args, int max_nof_locals, int max_nof_monitors) { ++ return (nof_args - local_index + (local_index < nof_args ? 1: -1)); ++} ++ ++inline int frame::monitor_offset_for_compiler(int local_index, int nof_args, int max_nof_locals, int max_nof_monitors) { ++ return local_offset_for_compiler(local_index, nof_args, max_nof_locals, max_nof_monitors); ++} ++ ++inline int frame::min_local_offset_for_compiler(int nof_args, int max_nof_locals, int max_nof_monitors) { ++ return (nof_args - (max_nof_locals + max_nof_monitors*2) - 1); ++} ++ ++inline bool frame::volatile_across_calls(Register reg) { ++ return true; ++} ++ ++ ++ ++inline oop frame::saved_oop_result(RegisterMap* map) const { ++ return *((oop*) map->location(V0->as_VMReg())); ++} ++ ++inline void frame::set_saved_oop_result(RegisterMap* map, oop obj) { ++ *((oop*) map->location(V0->as_VMReg())) = obj; ++} ++ ++#endif // CPU_SW64_VM_FRAME_SW64_INLINE_HPP +diff --git a/hotspot/src/cpu/sw64/vm/globalDefinitions_sw64.hpp b/hotspot/src/cpu/sw64/vm/globalDefinitions_sw64.hpp +new file mode 100755 +index 0000000000..f61a1bf2fd +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/globalDefinitions_sw64.hpp +@@ -0,0 +1,41 @@ ++/* ++ * Copyright (c) 1999, 2013, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_SW64_VM_GLOBALDEFINITIONS_SW64_HPP ++#define CPU_SW64_VM_GLOBALDEFINITIONS_SW64_HPP ++const int BytesPerInstWord = 4; ++ ++const int StackAlignmentInBytes = (2*wordSize); ++ ++#define SUPPORTS_NATIVE_CX8 ++// Indicates whether the C calling conventions require that ++// 32-bit integer argument values are properly extended to 64 bits. ++// If set, SharedRuntime::c_calling_convention() must adapt ++// signatures accordingly. ++const bool CCallingConventionRequiresIntsAsLongs = false; ++ ++#define SUPPORT_NATIVE_CX8 ++#define SUPPORTS_NATIVE_CX8 ++ ++#endif // CPU_SW64_VM_GLOBALDEFINITIONS_SW64_HPP +diff --git a/hotspot/src/cpu/sw64/vm/globals_sw64.hpp b/hotspot/src/cpu/sw64/vm/globals_sw64.hpp +new file mode 100755 +index 0000000000..09f785f339 +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/globals_sw64.hpp +@@ -0,0 +1,155 @@ ++/* ++ * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_SW64_VM_GLOBALS_SW64_HPP ++#define CPU_SW64_VM_GLOBALS_SW64_HPP ++ ++#include "utilities/globalDefinitions.hpp" ++#include "utilities/macros.hpp" ++ ++// Sets the default values for platform dependent flags used by the runtime system. ++// (see globals.hpp) ++ ++#ifdef CORE ++define_pd_global(bool, UseSSE, 0); ++#endif /* CORE */ ++define_pd_global(bool, ConvertSleepToYield, true); ++define_pd_global(bool, ShareVtableStubs, true); ++define_pd_global(bool, CountInterpCalls, true); ++ ++define_pd_global(bool, ImplicitNullChecks, true); // Generate code for implicit null checks ++define_pd_global(bool, TrapBasedNullChecks, false); // Not needed on x86. ++define_pd_global(bool, UncommonNullCast, true); // Uncommon-trap NULLs passed to check cast ++define_pd_global(bool, NeedsDeoptSuspend, false); // only register window machines need this ++ ++// See 4827828 for this change. There is no globals_core_i486.hpp. I can't ++// assign a different value for C2 without touching a number of files. Use ++// #ifdef to minimize the change as it's late in Mantis. -- FIXME. ++// c1 doesn't have this problem because the fix to 4858033 assures us ++// the the vep is aligned at CodeEntryAlignment whereas c2 only aligns ++// the uep and the vep doesn't get real alignment but just slops on by ++// only assured that the entry instruction meets the 5 byte size requirement. ++define_pd_global(intx, CodeEntryAlignment, 16); ++define_pd_global(intx, OptoLoopAlignment, 16); ++define_pd_global(intx, InlineFrequencyCount, 100); ++define_pd_global(intx, InlineSmallCode, 4000); ++ ++define_pd_global(uintx, TLABSize, 0); ++define_pd_global(uintx, NewSize, 1024 * K); ++define_pd_global(intx, PreInflateSpin, 10); ++ ++//define_pd_global(intx, PrefetchCopyIntervalInBytes, 256); ++//define_pd_global(intx, PrefetchScanIntervalInBytes, 256); ++//define_pd_global(intx, PrefetchFieldsAhead, -1); ++ ++define_pd_global(intx, StackYellowPages, 2); ++define_pd_global(intx, StackRedPages, 1); ++define_pd_global(intx, StackShadowPages, 3 DEBUG_ONLY(+1)); ++ ++define_pd_global(bool, RewriteBytecodes, true); ++define_pd_global(bool, RewriteFrequentPairs, true); ++#ifdef _ALLBSD_SOURCE ++define_pd_global(bool, UseMembar, true); ++#else ++define_pd_global(bool, UseMembar, false); ++#endif ++// GC Ergo Flags ++define_pd_global(intx, CMSYoungGenPerWorker, 64*M); // default max size of CMS young gen, per GC worker thread ++ ++define_pd_global(uintx, TypeProfileLevel, 111); ++ ++define_pd_global(bool, PreserveFramePointer, false); ++// Only c2 cares about this at the moment ++//define_pd_global(intx, AllocatePrefetchStyle, 2); ++//define_pd_global(intx, AllocatePrefetchDistance, 256); ++ ++#define ARCH_FLAGS(develop, product, diagnostic, experimental, notproduct) \ ++ \ ++ product(bool, UseSW6B, false, \ ++ "Use SW6B on Shenwei CPUs") \ ++ \ ++ product(bool, UseSW8A, false, \ ++ "Use SW8A on Shenwei CPUs") \ ++ \ ++ product(bool, UseAddpi, false, \ ++ "Use addpi of SW8A's instructions") \ ++ \ ++ product(bool, UseCAS, false, \ ++ "Use CASx of SW8A's instructions") \ ++ \ ++ product(bool, UseWmemb, false, \ ++ "Use wmemb on SW8A CPU") \ ++ product(bool, UseNecessaryMembar, true, \ ++ "Use necessary Membar") \ ++ product(bool, UseCRC32, false, \ ++ "Use CRC32 instructions for CRC32 computation") \ ++ product(bool, SolveAlignment, false, \ ++ "solve alignment when SolveAlignment is true, otherwise ignore") \ ++ product(bool, UseUnsafeCopyIntrinsic, true, \ ++ "Use unsafe_arraycopy Intrinsic") \ ++ product(bool, UseSimdForward, false, \ ++ "arraycopy disjoint stubs with SIMD instructions") \ ++ product(bool, UseSimdBackward, false, \ ++ "arraycopy conjoint stubs with SIMD instructions") \ ++ product(bool, UseSimdLongOop, false, \ ++ "conjoint oop copy with SIMD instructions") \ ++ /* product(bool, UseCodeCacheAllocOpt, true, */ \ ++ /* "Allocate code cache within 32-bit memory address space") */ \ ++ \ ++ product(bool, UseCountLeadingZerosInstruction, true, \ ++ "Use count leading zeros instruction") \ ++ \ ++ product(bool, UseCountTrailingZerosInstruction, false, \ ++ "Use count trailing zeros instruction") \ ++ \ ++ product(bool, FastIntDiv, false, \ ++ "make Integer division faster") \ ++ \ ++ product(bool, FastLongDiv, false, \ ++ "make Long division faster") \ ++ \ ++ product(bool, FastIntRem, false, \ ++ "make Integer remainder faster") \ ++ \ ++ product(bool, FastLongRem, false, \ ++ "make Long remainder faster") \ ++ \ ++ product(bool, SafePatch, true, \ ++ "make patch operations safer, for SPECjvm2008 performance lost about 2%") \ ++ \ ++ product(bool, FRegisterConflict, true, \ ++ "When FRegisterConflict is true, prevent source and destination FloatRegisters from being the same. " \ ++ "When FRegisterConflict is false, ignore the conflict") \ ++ \ ++ product(bool, UseGetLongIntrinsic, false, \ ++ "Use Unsafe.getLong intrinsic") \ ++ \ ++ product(intx, PrefetchUnsafeCopyInBytes, -1, \ ++ "How far ahead to prefetch destination area (<= 0 means off)") \ ++ \ ++ product(bool, Usesetfpec1, true, \ ++ "When Usesetfpec1 is true, which is used for 9906" \ ++ "When Usesetfpec1 is false, which is used for 9916") ++ ++#endif // CPU_SW64_VM_GLOBALS_SW64_HPP +diff --git a/hotspot/src/cpu/sw64/vm/icBuffer_sw64.cpp b/hotspot/src/cpu/sw64/vm/icBuffer_sw64.cpp +new file mode 100755 +index 0000000000..b4f389b669 +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/icBuffer_sw64.cpp +@@ -0,0 +1,81 @@ ++/* ++ * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#include "precompiled.hpp" ++#include "asm/macroAssembler.hpp" ++#include "asm/macroAssembler.inline.hpp" ++#include "code/icBuffer.hpp" ++#include "gc_interface/collectedHeap.inline.hpp" ++#include "interpreter/bytecodes.hpp" ++#include "memory/resourceArea.hpp" ++#include "nativeInst_sw64.hpp" ++#include "oops/oop.inline.hpp" ++#include "oops/oop.inline2.hpp" ++ ++int InlineCacheBuffer::ic_stub_code_size() { ++ return NativeMovConstReg::instruction_size + ++ NativeGeneralJump::instruction_size + ++ 1; ++ // so that code_end can be set in CodeBuffer ++ // 64bit 15 = 6 + 8 bytes + 1 byte ++ // 32bit 7 = 2 + 4 bytes + 1 byte ++} ++ ++ ++// we use T1 as cached oop(klass) now. this is the target of virtual call, ++// when reach here, the receiver in A1 (not T0) ++// refer to shareRuntime_sw64.cpp,gen_i2c2i_adapters ++void InlineCacheBuffer::assemble_ic_buffer_code(address code_begin, void* cached_value, address entry_point) { ++ ResourceMark rm; ++ CodeBuffer code(code_begin, ic_stub_code_size()); ++ MacroAssembler* masm = new MacroAssembler(&code); ++ // note: even though the code contains an embedded oop, we do not need reloc info ++ // because ++ // (1) the oop is old (i.e., doesn't matter for scavenges) ++ // (2) these ICStubs are removed *before* a GC happens, so the roots disappear ++// assert(cached_oop == NULL || cached_oop->is_perm(), "must be perm oop"); ++#define __ masm-> ++ __ patchable_set48(T1, (long)cached_value); ++ ++ __ patchable_jump(entry_point); ++ __ flush(); ++#undef __ ++} ++ ++ ++address InlineCacheBuffer::ic_buffer_entry_point(address code_begin) { ++ NativeMovConstReg* move = nativeMovConstReg_at(code_begin); // creation also verifies the object ++ NativeGeneralJump* jump = nativeGeneralJump_at(move->next_instruction_address()); ++ return jump->jump_destination(); ++} ++ ++ ++void* InlineCacheBuffer::ic_buffer_cached_value(address code_begin) { ++ // creation also verifies the object ++ NativeMovConstReg* move = nativeMovConstReg_at(code_begin); ++ // Verifies the jump ++ NativeGeneralJump* jump = nativeGeneralJump_at(move->next_instruction_address()); ++ void* o= (void*)move->data(); ++ return o; ++} +diff --git a/hotspot/src/cpu/sw64/vm/icache_sw64.cpp b/hotspot/src/cpu/sw64/vm/icache_sw64.cpp +new file mode 100755 +index 0000000000..2034d66d94 +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/icache_sw64.cpp +@@ -0,0 +1,57 @@ ++/* ++ * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#include "precompiled.hpp" ++#include "asm/macroAssembler.hpp" ++#include "runtime/icache.hpp" ++ ++ #define CACHE_OPT 1 ++ ++//no need, we just call cacheflush system call to flush cache ++//flush cache is a very frequent operation, flush all the cache decrease the performance sharply, so i modify it. ++void ICacheStubGenerator::generate_icache_flush(ICache::flush_icache_stub_t* flush_icache_stub) {}; ++ ++void ICache::call_flush_stub(address start, int lines) { ++ //in fact, the current os implementation simply flush all ICACHE&DCACHE ++// __asm__ __volatile__ ("ldi $0,266"); ++// __asm__ __volatile__ ("sys_call 0x83"); ++} ++ ++void ICache::invalidate_word(address addr) { ++ //cacheflush(addr, 4, ICACHE); ++ ++// __asm__ __volatile__ ("ldi $0,266"); ++// __asm__ __volatile__ ("sys_call 0x83"); ++} ++ ++void ICache::invalidate_range(address start, int nbytes) { ++// __asm__ __volatile__ ("ldi $0,266"); ++// __asm__ __volatile__ ("sys_call 0x83"); ++} ++ ++void ICache::invalidate_all() { ++// __asm__ __volatile__ ("ldi $0,266"); ++// __asm__ __volatile__ ("sys_call 0x83"); ++} ++ +diff --git a/hotspot/src/cpu/sw64/vm/icache_sw64.hpp b/hotspot/src/cpu/sw64/vm/icache_sw64.hpp +new file mode 100755 +index 0000000000..ab17add4c2 +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/icache_sw64.hpp +@@ -0,0 +1,62 @@ ++/* ++ * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_SW64_VM_ICACHE_SW64_HPP ++#define CPU_SW64_VM_ICACHE_SW64_HPP ++ ++// Interface for updating the instruction cache. Whenever the VM modifies ++// code, part of the processor instruction cache potentially has to be flushed. ++ ++// On the x86, this is a no-op -- the I-cache is guaranteed to be consistent ++// after the next jump, and the VM never modifies instructions directly ahead ++// of the instruction fetch path. ++ ++// [phh] It's not clear that the above comment is correct, because on an MP ++// system where the dcaches are not snooped, only the thread doing the invalidate ++// will see the update. Even in the snooped case, a memory fence would be ++// necessary if stores weren't ordered. Fortunately, they are on all known ++// x86 implementations. ++ ++class ICache : public AbstractICache { ++ public: ++ enum { ++ stub_size = 0, // Size of the icache flush stub in bytes ++ line_size = 32, // flush instruction affects a dword ++ log2_line_size = 5 // log2(line_size) ++ }; ++ ++ //nothing to do ++ static void initialize() {} ++ ++ static void call_flush_stub(address start, int lines); ++ ++ static void invalidate_word(address addr); ++ ++ static void invalidate_range(address start, int nbytes); ++ ++ static void invalidate_all(); ++ ++}; ++ ++#endif // CPU_SW64_VM_ICACHE_SW64_HPP +diff --git a/hotspot/src/cpu/sw64/vm/interp_masm_sw64.cpp b/hotspot/src/cpu/sw64/vm/interp_masm_sw64.cpp +new file mode 100755 +index 0000000000..4ad18b333f +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/interp_masm_sw64.cpp +@@ -0,0 +1,2032 @@ ++/* ++ * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#include "precompiled.hpp" ++#include "interp_masm_sw64.hpp" ++#include "interpreter/interpreter.hpp" ++#include "interpreter/interpreterRuntime.hpp" ++#include "oops/arrayOop.hpp" ++#include "oops/markOop.hpp" ++#include "oops/methodData.hpp" ++#include "oops/method.hpp" ++#include "prims/jvmtiExport.hpp" ++#include "prims/jvmtiRedefineClassesTrace.hpp" ++#include "prims/jvmtiThreadState.hpp" ++#include "runtime/basicLock.hpp" ++#include "runtime/biasedLocking.hpp" ++#include "runtime/sharedRuntime.hpp" ++#include "runtime/thread.inline.hpp" ++ ++ ++#ifdef PRODUCT ++#define BLOCK_COMMENT(str) /* nothing */ ++#define STOP(error) stop(error) ++#else ++#define BLOCK_COMMENT(str) { char line[1024]; \ ++ sprintf(line, "%s:%s:%d",str, __FILE__, __LINE__); \ ++ block_comment(line); } ++#define STOP(error) block_comment(error); stop(error) ++#endif ++ ++#define BIND(label) bind(label); BLOCK_COMMENT(#label ":") ++ ++// Implementation of InterpreterMacroAssembler ++ ++#ifdef CC_INTERP ++void InterpreterMacroAssembler::get_method(Register reg) { ++} ++#endif // CC_INTERP ++ ++void InterpreterMacroAssembler::get_2_byte_integer_at_bcp(Register reg, Register tmp, int offset) { ++ // The runtime address of BCP may be unaligned. ++ // Refer to the SPARC implementation. ++ ldbu(reg, BCP, offset+1); ++ ldbu(tmp, BCP, offset); ++ slll(reg, reg, 8); ++ addl(reg, tmp, reg); ++} ++ ++void InterpreterMacroAssembler::get_4_byte_integer_at_bcp(Register reg, Register tmp, int offset) { ++ assert(reg != tmp, "need separate temp register"); ++ if (offset & 3) { // Offset unaligned? ++ ldbu(reg, BCP, offset+3); ++ ldbu(tmp, BCP, offset+2); ++#ifdef _LP64 ++ slll(reg, reg, 8); ++ addl(reg, tmp, reg); ++ ldbu(tmp, BCP, offset+1); ++ slll(reg, reg, 8); ++ addl(reg, tmp, reg); ++ ldbu(tmp, BCP, offset); ++ slll(reg, reg, 8); ++ addl(reg, tmp, reg); ++#endif ++ } else { ++ ldw_unsigned(reg, BCP, offset); ++ } ++} ++ ++#ifndef CC_INTERP ++ ++void InterpreterMacroAssembler::call_VM_leaf_base(address entry_point, ++ int number_of_arguments) { ++ // interpreter specific ++ // ++ // Note: No need to save/restore bcp & locals (r13 & r14) pointer ++ // since these are callee saved registers and no blocking/ ++ // GC can happen in leaf calls. ++ // Further Note: DO NOT save/restore bcp/locals. If a caller has ++ // already saved them so that it can use BCP/LVP as temporaries ++ // then a save/restore here will DESTROY the copy the caller ++ // saved! There used to be a save_bcp() that only happened in ++ // the ASSERT path (no restore_bcp). Which caused bizarre failures ++ // when jvm built with ASSERTs. ++#ifdef ASSERT ++ save_bcp(); ++ { ++ Label L; ++ ldl(AT,FP,frame::interpreter_frame_last_sp_offset * wordSize); ++ beq(AT, L); ++ stop("InterpreterMacroAssembler::call_VM_leaf_base: last_sp != NULL"); ++ BIND(L); ++ } ++#endif ++ // super call ++ MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments); ++ // interpreter specific ++ // LP64: Used to ASSERT that BCP/LVP were equal to frame's bcp/locals ++ // but since they may not have been saved (and we don't want to ++ // save them here (see note above) the assert is invalid. ++} ++ ++void InterpreterMacroAssembler::call_VM_base(Register oop_result, ++ Register java_thread, ++ Register last_java_sp, ++ address entry_point, ++ int number_of_arguments, ++ bool check_exceptions) { ++ // interpreter specific ++ // ++ // Note: Could avoid restoring locals ptr (callee saved) - however doesn't ++ // really make a difference for these runtime calls, since they are ++ // slow anyway. Btw., bcp must be saved/restored since it may change ++ // due to GC. ++ assert(java_thread == noreg , "not expecting a precomputed java thread"); ++ save_bcp(); ++#ifdef ASSERT ++ { ++ Label L; ++ ldl(AT, FP, frame::interpreter_frame_last_sp_offset * wordSize); ++ beq(AT, L); ++ stop("InterpreterMacroAssembler::call_VM_base: last_sp != NULL"); ++ BIND(L); ++ } ++#endif /* ASSERT */ ++ // super call ++ MacroAssembler::call_VM_base(oop_result, java_thread, last_java_sp, ++ entry_point, number_of_arguments, ++ check_exceptions); ++ // interpreter specific ++ restore_bcp(); ++ restore_locals(); ++} ++ ++ ++void InterpreterMacroAssembler::check_and_handle_popframe(Register java_thread) { ++ if (JvmtiExport::can_pop_frame()) { ++ Label L; ++ // Initiate popframe handling only if it is not already being ++ // processed. If the flag has the popframe_processing bit set, it ++ // means that this code is called *during* popframe handling - we ++ // don't want to reenter. ++ // This method is only called just after the call into the vm in ++ // call_VM_base, so the arg registers are available. ++ // Not clear if any other register is available, so load AT twice ++ assert(AT != java_thread, "check"); ++ ldw(AT, java_thread, in_bytes(JavaThread::popframe_condition_offset())); ++ and_imm8(AT, AT, JavaThread::popframe_pending_bit); ++ beq(AT, L); ++ ldw(AT, java_thread, in_bytes(JavaThread::popframe_condition_offset())); ++ and_imm8(AT, AT, JavaThread::popframe_processing_bit); ++ bne(AT, L); ++ call_VM_leaf(CAST_FROM_FN_PTR(address, Interpreter::remove_activation_preserving_args_entry)); ++ jmp(V0); ++ BIND(L); ++ } ++} ++ ++ ++void InterpreterMacroAssembler::load_earlyret_value(TosState state) { ++ Register thread = T11; ++ move(T11, S2thread); ++ ld_ptr(thread, thread, in_bytes(JavaThread::jvmti_thread_state_offset())); ++ const Address tos_addr (thread, in_bytes(JvmtiThreadState::earlyret_tos_offset())); ++ const Address oop_addr (thread, in_bytes(JvmtiThreadState::earlyret_oop_offset())); ++ const Address val_addr (thread, in_bytes(JvmtiThreadState::earlyret_value_offset())); ++ //V0, oop_addr,V1,val_addr ++ switch (state) { ++ case atos: ++ ld_ptr(V0, oop_addr); ++ st_ptr(R0, oop_addr); ++ verify_oop(V0, state); ++ break; ++ case ltos: ++ ld_ptr(V0, val_addr); // fall through ++ break; ++ case btos: // fall through ++ case ztos: // fall through ++ case ctos: // fall through ++ case stos: // fall through ++ case itos: ++ ldw_signed(V0, val_addr); ++ break; ++ case ftos: ++ flds(F0, thread, in_bytes(JvmtiThreadState::earlyret_value_offset())); ++ break; ++ case dtos: ++ fldd(F0, thread, in_bytes(JvmtiThreadState::earlyret_value_offset())); ++ break; ++ case vtos: /* nothing to do */ break; ++ default : ShouldNotReachHere(); ++ } ++ // Clean up tos value in the thread object ++ move(AT, (int)ilgl); ++ stw(AT, tos_addr); ++ stw(R0, thread, in_bytes(JvmtiThreadState::earlyret_value_offset())); ++} ++ ++ ++void InterpreterMacroAssembler::check_and_handle_earlyret(Register java_thread) { ++ if (JvmtiExport::can_force_early_return()) { ++ Label L; ++ Register tmp = T12; ++ ++ assert(java_thread != AT, "check"); ++ assert(java_thread != tmp, "check"); ++ ld_ptr(AT,java_thread, in_bytes(JavaThread::jvmti_thread_state_offset())); ++ beq(AT, L); ++ ++ // Initiate earlyret handling only if it is not already being processed. ++ // If the flag has the earlyret_processing bit set, it means that this code ++ // is called *during* earlyret handling - we don't want to reenter. ++ ldw(AT, AT, in_bytes(JvmtiThreadState::earlyret_state_offset())); ++ move(tmp, JvmtiThreadState::earlyret_pending); ++ bne(tmp, AT, L); ++ ++ // Call Interpreter::remove_activation_early_entry() to get the address of the ++ // same-named entrypoint in the generated interpreter code. ++ ld_ptr(tmp,java_thread, in_bytes(JavaThread::jvmti_thread_state_offset())); ++ ldw(AT,tmp, in_bytes(JvmtiThreadState::earlyret_tos_offset())); ++ move(A0, AT); ++ call_VM_leaf(CAST_FROM_FN_PTR(address, Interpreter::remove_activation_early_entry), A0); ++ jmp(V0); ++ BIND(L); ++ } ++} ++ ++ ++void InterpreterMacroAssembler::get_unsigned_2_byte_index_at_bcp(Register reg, ++ int bcp_offset) { ++ assert(bcp_offset >= 0, "bcp is still pointing to start of bytecode"); ++#if 1 //ZHJ20180716 ++ ldbu(AT, BCP, bcp_offset); ++ ldbu(reg, BCP, bcp_offset + 1); ++ slll(AT, AT, 8); ++ or_ins(reg, reg, AT); ++#else // it is also OK! ++ get_2_byte_integer_at_bcp(reg, AT, bcp_offset); ++ huswap(reg); //ZHJ20180716 hswap(reg); ++#endif ++} ++ ++ ++void InterpreterMacroAssembler::get_cache_index_at_bcp(Register index, ++ int bcp_offset, ++ size_t index_size) { ++ assert(bcp_offset > 0, "bcp is still pointing to start of bytecode"); ++ if (index_size == sizeof(u2)) { ++ get_2_byte_integer_at_bcp(index, AT, bcp_offset); ++ } else if (index_size == sizeof(u4)) { ++ assert(EnableInvokeDynamic, "giant index used only for JSR 292"); ++ get_4_byte_integer_at_bcp(index, AT, bcp_offset); ++ // Check if the secondary index definition is still ~x, otherwise ++ // we have to change the following assembler code to calculate the ++ // plain index. ++ assert(ConstantPool::decode_invokedynamic_index(~123) == 123, "else change next line"); ++ ornot(index, R0, index); ++ addw(index, index, 0); ++ } else if (index_size == sizeof(u1)) { ++ ldbu(index, BCP, bcp_offset); ++ } else { ++ ShouldNotReachHere(); ++ } ++} ++ ++ ++void InterpreterMacroAssembler::get_cache_and_index_at_bcp(Register cache, ++ Register index, ++ int bcp_offset, ++ size_t index_size) { ++ assert_different_registers(cache, index); ++ get_cache_index_at_bcp(index, bcp_offset, index_size); ++ ldl(cache, FP, frame::interpreter_frame_cache_offset * wordSize); ++ assert(sizeof(ConstantPoolCacheEntry) == 4 * wordSize, "adjust code below"); ++ assert(exact_log2(in_words(ConstantPoolCacheEntry::size())) == 2, "else change next line"); ++ shl(index, 2); ++} ++ ++ ++void InterpreterMacroAssembler::get_cache_and_index_and_bytecode_at_bcp(Register cache, ++ Register index, ++ Register bytecode, ++ int byte_no, ++ int bcp_offset, ++ size_t index_size) { ++ get_cache_and_index_at_bcp(cache, index, bcp_offset, index_size); ++ // We use a 32-bit load here since the layout of 64-bit words on ++ // little-endian machines allow us that. ++ slll(AT, index, Address::times_ptr); ++ addl(AT, cache, AT); ++ ldw(bytecode, AT, in_bytes(ConstantPoolCache::base_offset() + ConstantPoolCacheEntry::indices_offset())); ++ ++ const int shift_count = (1 + byte_no) * BitsPerByte; ++ assert((byte_no == TemplateTable::f1_byte && shift_count == ConstantPoolCacheEntry::bytecode_1_shift) || ++ (byte_no == TemplateTable::f2_byte && shift_count == ConstantPoolCacheEntry::bytecode_2_shift), ++ "correct shift count"); ++ srll(bytecode, bytecode, shift_count); ++ assert(ConstantPoolCacheEntry::bytecode_1_mask == ConstantPoolCacheEntry::bytecode_2_mask, "common mask"); ++ move(AT, ConstantPoolCacheEntry::bytecode_1_mask); ++ and_reg(bytecode, bytecode, AT); ++} ++ ++void InterpreterMacroAssembler::get_cache_entry_pointer_at_bcp(Register cache, ++ Register tmp, ++ int bcp_offset, ++ size_t index_size) { ++ assert(bcp_offset > 0, "bcp is still pointing to start of bytecode"); ++ assert(cache != tmp, "must use different register"); ++ get_cache_index_at_bcp(tmp, bcp_offset, index_size); ++ assert(sizeof(ConstantPoolCacheEntry) == 4 * wordSize, "adjust code below"); ++ // convert from field index to ConstantPoolCacheEntry index ++ // and from word offset to byte offset ++ assert(exact_log2(in_bytes(ConstantPoolCacheEntry::size_in_bytes())) == 2 + LogBytesPerWord, "else change next line"); ++ shl(tmp, 2 + LogBytesPerWord); ++ ldl(cache, FP, frame::interpreter_frame_cache_offset * wordSize); ++ // skip past the header ++ add_simm16(cache, cache, in_bytes(ConstantPoolCache::base_offset())); ++ addl(cache, cache, tmp); ++} ++ ++void InterpreterMacroAssembler::get_method_counters(Register method, ++ Register mcs, Label& skip) { ++ Label has_counters; ++ ldl(mcs, method, in_bytes(Method::method_counters_offset())); ++ bne(mcs, has_counters); ++ call_VM(noreg, CAST_FROM_FN_PTR(address, ++ InterpreterRuntime::build_method_counters), method); ++ ldl(mcs, method, in_bytes(Method::method_counters_offset())); ++ beq(mcs, skip); // No MethodCounters allocated, OutOfMemory ++ BIND(has_counters); ++} ++ ++// Load object from cpool->resolved_references(index) ++void InterpreterMacroAssembler::load_resolved_reference_at_index( ++ Register result, Register index) { ++ assert_different_registers(result, index); ++ // convert from field index to resolved_references() index and from ++ // word index to byte offset. Since this is a java object, it can be compressed ++ Register tmp = index; // reuse ++ shl(tmp, LogBytesPerHeapOop); ++ ++ get_constant_pool(result); ++ // load pointer for resolved_references[] objArray ++ ldl(result, result, ConstantPool::resolved_references_offset_in_bytes()); ++ // JNIHandles::resolve(obj); ++ ldl(result, result, 0); //? is needed? ++ // Add in the index ++ addl(result, result, tmp); ++ load_heap_oop(result, Address(result, arrayOopDesc::base_offset_in_bytes(T_OBJECT))); ++} ++ ++// Resets LVP to locals. Register sub_klass cannot be any of the above. ++void InterpreterMacroAssembler::gen_subtype_check( Register Rsup_klass, Register Rsub_klass, Label &ok_is_subtype ) { ++ assert( Rsub_klass != Rsup_klass, "Rsup_klass holds superklass" ); ++ assert( Rsub_klass != T1, "T1 holds 2ndary super array length" ); ++ assert( Rsub_klass != T0, "T0 holds 2ndary super array scan ptr" ); ++ // Profile the not-null value's klass. ++ // Here T12 and T1 are used as temporary registers. ++ profile_typecheck(T12, Rsub_klass, T1); // blows T12, reloads T1 ++ ++// Do the check. ++ check_klass_subtype(Rsub_klass, Rsup_klass, T1, ok_is_subtype); // blows T1 ++ ++// Profile the failure of the check. ++ profile_typecheck_failed(T12); // blows T12 ++} ++ ++ ++ ++// Java Expression Stack ++ ++void InterpreterMacroAssembler::pop_ptr(Register r) { ++ if (UseSW8A) { ++ ldl_a(r, Interpreter::stackElementSize, SP); ++ } else { ++ ldl(r, SP, 0); ++ addl(SP, SP, Interpreter::stackElementSize); ++ } ++} ++ ++void InterpreterMacroAssembler::pop_i(Register r) { ++ if (UseSW8A) { ++ ldw_a(r, Interpreter::stackElementSize, SP); ++ } else { ++ ldw(r, SP, 0); ++ addl(SP, SP, Interpreter::stackElementSize); ++ } ++} ++ ++void InterpreterMacroAssembler::pop_l(Register r) { ++ if (UseSW8A) { ++ ldl_a(r, 2 * Interpreter::stackElementSize, SP); ++ } else { ++ ldl(r, SP, 0); ++ addl(SP, SP, 2 * Interpreter::stackElementSize); ++ } ++} ++ ++void InterpreterMacroAssembler::pop_f(FloatRegister r) { ++ if (UseSW8A) { ++ flds_a(r, Interpreter::stackElementSize, SP); ++ } else { ++ flds(r, SP, 0); ++ addl(SP, SP, Interpreter::stackElementSize); ++ } ++} ++ ++void InterpreterMacroAssembler::pop_d(FloatRegister r) { ++ if (UseSW8A) { ++ fldd_a(r, 2 * Interpreter::stackElementSize, SP); ++ } else { ++ fldd(r, SP, 0); ++ addl(SP, SP, 2 * Interpreter::stackElementSize); ++ } ++} ++ ++void InterpreterMacroAssembler::push_ptr(Register r) { ++ subl(SP, SP, Interpreter::stackElementSize); ++ stl(r, SP, 0); ++} ++ ++void InterpreterMacroAssembler::push_i(Register r) { ++ subl(SP, SP, Interpreter::stackElementSize); ++ // For compatibility reason, don't change to sw. ++ stl(r, SP, 0); ++} ++ ++void InterpreterMacroAssembler::push_l(Register r) { ++ subl(SP, SP, 2 * Interpreter::stackElementSize); ++ stl(r, SP, 0); ++} ++ ++void InterpreterMacroAssembler::push_f(FloatRegister r) { ++ subl(SP, SP, Interpreter::stackElementSize); ++ fsts(r, SP, 0); ++} ++ ++void InterpreterMacroAssembler::push_d(FloatRegister r) { ++ subl(SP, SP, 2 * Interpreter::stackElementSize); ++ fstd(r, SP, 0); ++} ++ ++void InterpreterMacroAssembler::pop(TosState state) { ++ switch (state) { ++ case atos: pop_ptr(); break; ++ case btos: ++ case ztos: ++ case ctos: ++ case stos: ++ case itos: pop_i(); break; ++ case ltos: pop_l(); break; ++ case ftos: pop_f(); break; ++ case dtos: pop_d(); break; ++ case vtos: /* nothing to do */ break; ++ default: ShouldNotReachHere(); ++ } ++ verify_oop(FSR, state); ++} ++ ++//FSR=V0,SSR=T4 ++void InterpreterMacroAssembler::push(TosState state) { ++ verify_oop(FSR, state); ++ switch (state) { ++ case atos: push_ptr(); break; ++ case btos: ++ case ztos: ++ case ctos: ++ case stos: ++ case itos: push_i(); break; ++ case ltos: push_l(); break; ++ case ftos: push_f(); break; ++ case dtos: push_d(); break; ++ case vtos: /* nothing to do */ break; ++ default : ShouldNotReachHere(); ++ } ++} ++ ++ ++ ++void InterpreterMacroAssembler::load_ptr(int n, Register val) { ++ ldl(val, SP, Interpreter::expr_offset_in_bytes(n)); ++} ++ ++void InterpreterMacroAssembler::store_ptr(int n, Register val) { ++ stl(val, SP, Interpreter::expr_offset_in_bytes(n)); ++} ++ ++// Jump to from_interpreted entry of a call unless single stepping is possible ++// in this thread in which case we must call the i2i entry ++void InterpreterMacroAssembler::jump_from_interpreted(Register method, Register temp) { ++ // record last_sp ++ move(Rsender, SP); ++ stl(SP, FP, frame::interpreter_frame_last_sp_offset * wordSize); ++ ++ if (JvmtiExport::can_post_interpreter_events()) { ++ Label run_compiled_code; ++ // JVMTI events, such as single-stepping, are implemented partly by avoiding running ++ // compiled code in threads for which the event is enabled. Check here for ++ // interp_only_mode if these events CAN be enabled. ++ move(temp, S2thread); ++ // interp_only is an int, on little endian it is sufficient to test the byte only ++ // Is a cmpl faster? ++ ldw(AT, temp, in_bytes(JavaThread::interp_only_mode_offset())); ++ beq(AT, run_compiled_code); ++ ldl(AT, method, in_bytes(Method::interpreter_entry_offset())); ++ jmp(AT); ++ BIND(run_compiled_code); ++ } ++ ++ ldl(AT, method, in_bytes(Method::from_interpreted_offset())); ++ jmp(AT); ++} ++ ++ ++// The following two routines provide a hook so that an implementation ++// can schedule the dispatch in two parts. sw64 does not do this. ++void InterpreterMacroAssembler::dispatch_prolog(TosState state, int step) { ++ // Nothing sw64 specific to be done here ++} ++ ++void InterpreterMacroAssembler::dispatch_epilog(TosState state, int step) { ++ dispatch_next(state, step); ++} ++ ++// assume the next bytecode in T11. ++void InterpreterMacroAssembler::dispatch_base(TosState state, ++ address* table, ++ bool verifyoop) { ++ if (VerifyActivationFrameSize) { ++ Label L; ++ ++ subl(T2, FP, SP); ++ int min_frame_size = (frame::link_offset - ++ frame::interpreter_frame_initial_sp_offset) * wordSize; ++ add_simm16(T2, T2,- min_frame_size); ++ bge(T2, L); ++ stop("broken stack frame"); ++ BIND(L); ++ } ++ // FIXME: I do not know which register should pass to verify_oop ++ if (verifyoop) verify_oop(FSR, state); ++ slll(T2, Rnext, LogBytesPerWord); ++ ++ li(GP, (long)table); ++ addl(T3, T2, GP); ++ ldl(T3, T3, 0); ++ jmp(T3); ++} ++ ++void InterpreterMacroAssembler::dispatch_only(TosState state) { ++ dispatch_base(state, Interpreter::dispatch_table(state)); ++} ++ ++void InterpreterMacroAssembler::dispatch_only_normal(TosState state) { ++ dispatch_base(state, Interpreter::normal_table(state)); ++} ++ ++void InterpreterMacroAssembler::dispatch_only_noverify(TosState state) { ++ dispatch_base(state, Interpreter::normal_table(state), false); ++} ++ ++ ++void InterpreterMacroAssembler::dispatch_next(TosState state, int step) { ++ // load next bytecode (load before advancing r13 to prevent AGI) ++ ldbu(Rnext, BCP, step); ++ increment(BCP, step); ++ dispatch_base(state, Interpreter::dispatch_table(state)); ++} ++ ++void InterpreterMacroAssembler::dispatch_via(TosState state, address* table) { ++ // load current bytecode ++ ldbu(Rnext, BCP, 0); ++ dispatch_base(state, table); ++} ++ ++// remove activation ++// ++// Unlock the receiver if this is a synchronized method. ++// Unlock any Java monitors from syncronized blocks. ++// Remove the activation from the stack. ++// ++// If there are locked Java monitors ++// If throw_monitor_exception ++// throws IllegalMonitorStateException ++// Else if install_monitor_exception ++// installs IllegalMonitorStateException ++// Else ++// no error processing ++// used registers : T1, T2, T3, T11 ++// T1 : thread, method access flags ++// T2 : monitor entry pointer ++// T3 : method, monitor top ++// T11 : unlock flag ++void InterpreterMacroAssembler::remove_activation( ++ TosState state, ++ Register ret_addr, ++ bool throw_monitor_exception, ++ bool install_monitor_exception, ++ bool notify_jvmdi) { ++ // Note: Registers V0, T4 and F0, F1 may be in use for the result ++ // check if synchronized method ++ Label unlocked, unlock, no_unlock; ++ ++ // get the value of _do_not_unlock_if_synchronized into T11 ++ Register thread = S2thread; ++ ldbu(T11, thread, in_bytes(JavaThread::do_not_unlock_if_synchronized_offset())); ++ // reset the flag ++ stb(R0, thread, in_bytes(JavaThread::do_not_unlock_if_synchronized_offset())); ++ // get method access flags ++ ldl(T3, FP, frame::interpreter_frame_method_offset * wordSize); ++ ldw(T1, T3, in_bytes(Method::access_flags_offset())); ++ and_imm8(T1, T1, JVM_ACC_SYNCHRONIZED); ++ beq(T1, unlocked); ++ ++ // Don't unlock anything if the _do_not_unlock_if_synchronized flag is set. ++ bne(T11, no_unlock); ++ // unlock monitor ++ push(state); // save result ++ ++ // BasicObjectLock will be first in list, since this is a ++ // synchronized method. However, need to check that the object has ++ // not been unlocked by an explicit monitorexit bytecode. ++ add_simm16(c_rarg0, FP, frame::interpreter_frame_initial_sp_offset * wordSize ++ - (int)sizeof(BasicObjectLock)); ++ // address of first monitor ++ ldl(T1, c_rarg0, BasicObjectLock::obj_offset_in_bytes()); ++ bne(T1, unlock); ++ pop(state); ++ if (throw_monitor_exception) { ++ empty_FPU_stack(); ++ call_VM(NOREG, CAST_FROM_FN_PTR(address, ++ InterpreterRuntime::throw_illegal_monitor_state_exception)); ++ should_not_reach_here(); ++ } else { ++ // Monitor already unlocked during a stack unroll. If requested, ++ // install an illegal_monitor_state_exception. Continue with ++ // stack unrolling. ++ if (install_monitor_exception) { ++ // remove possible return value from FPU-stack, ++ // otherwise stack could overflow ++ empty_FPU_stack(); ++ call_VM(NOREG, CAST_FROM_FN_PTR(address, ++ InterpreterRuntime::new_illegal_monitor_state_exception)); ++ ++ } ++ ++ beq(R0, unlocked); ++ } ++ ++ BIND(unlock); ++ unlock_object(c_rarg0); ++ pop(state); ++ ++ // Check that for block-structured locking (i.e., that all locked ++ // objects has been unlocked) ++ BIND(unlocked); ++ ++ // V0, T4: Might contain return value ++ ++ // Check that all monitors are unlocked ++ { ++ Label loop, exception, entry, restart; ++ const int entry_size = frame::interpreter_frame_monitor_size() * wordSize; ++ const Address monitor_block_top(FP, ++ frame::interpreter_frame_monitor_block_top_offset * wordSize); ++ ++ BIND(restart); ++ // points to current entry, starting with top-most entry ++ ldl(c_rarg0, monitor_block_top); ++ // points to word before bottom of monitor block ++ add_simm16(T3, FP, frame::interpreter_frame_initial_sp_offset * wordSize); ++ beq(R0, entry); ++ ++ // Entry already locked, need to throw exception ++ BIND(exception); ++ ++ if (throw_monitor_exception) { ++ // Throw exception ++ // remove possible return value from FPU-stack, ++ // otherwise stack could overflow ++ empty_FPU_stack(); ++ MacroAssembler::call_VM(NOREG, CAST_FROM_FN_PTR(address, ++ InterpreterRuntime::throw_illegal_monitor_state_exception)); ++ should_not_reach_here(); ++ } else { ++ // Stack unrolling. Unlock object and install illegal_monitor_exception ++ // Unlock does not block, so don't have to worry about the frame ++ // We don't have to preserve c_rarg0, since we are going to ++ // throw an exception ++ unlock_object(c_rarg0); ++ if (install_monitor_exception) { ++ empty_FPU_stack(); ++ call_VM(NOREG, CAST_FROM_FN_PTR(address, ++ InterpreterRuntime::new_illegal_monitor_state_exception)); ++ } ++ ++ beq(R0, restart); ++ } ++ ++ BIND(loop); ++ ldl(T1, c_rarg0, BasicObjectLock::obj_offset_in_bytes()); ++ bne(T1, exception);// check if current entry is used ++ ++ ++ add_simm16(c_rarg0, c_rarg0, entry_size);// otherwise advance to next entry ++ BIND(entry); ++ bne(c_rarg0, T3, loop); // check if bottom reached ++ } ++ ++ BIND(no_unlock); ++ ++ // jvmpi support (jvmdi does not generate MethodExit on exception / popFrame) ++ if (notify_jvmdi) { ++ notify_method_exit(false,state,NotifyJVMTI); // preserve TOSCA ++ } else { ++ notify_method_exit(false,state,SkipNotifyJVMTI);// preserve TOSCA ++ } ++ ++ // remove activation ++ // rewind sp to where the old sp saved on the stack, and coincidentally the ++ // stack contents we care about are all above this point. ++ ldi(SP, FP, frame::interpreter_frame_sender_sp_offset * wordSize); ++ ldl(ret_addr, FP, frame::interpreter_frame_return_addr_offset * wordSize); ++ ldl(FP, FP, frame::interpreter_frame_sender_fp_offset * wordSize); ++ // restore the old sp. ++ ldl(SP, SP, 0); ++} ++ ++#endif // C_INTERP ++ ++// Lock object ++// ++// Args: ++// c_rarg1: BasicObjectLock to be used for locking ++// ++// Kills: ++// c_rarg0, c_rarg1, c_rarg2, c_rarg3, .. (param regs) ++// rscratch1, rscratch2 (scratch regs) ++void InterpreterMacroAssembler::lock_object(Register lock_reg) { ++ assert(lock_reg == c_rarg0, "The argument is only for looks. It must be c_rarg0"); ++ ++ if (UseHeavyMonitors) { ++ call_VM(NOREG, CAST_FROM_FN_PTR(address, InterpreterRuntime::monitorenter), ++ lock_reg); ++ } else { ++ Label done; ++ ++ const Register swap_reg = T2; // Must use T2 for cmpxchg instruction ++ const Register obj_reg = T1; // Will contain the oop ++ ++ const int obj_offset = BasicObjectLock::obj_offset_in_bytes(); ++ const int lock_offset = BasicObjectLock::lock_offset_in_bytes (); ++ const int mark_offset = lock_offset + ++ BasicLock::displaced_header_offset_in_bytes(); ++ ++ Label slow_case; ++ ++ // Load object pointer into obj_reg %T1 ++ ldl(obj_reg, lock_reg, obj_offset); ++ ++ if (UseBiasedLocking) { ++ // Note: we use noreg for the temporary register since it's hard ++ // to come up with a free register on all incoming code paths ++ biased_locking_enter(lock_reg, obj_reg, swap_reg, noreg, false, done, &slow_case); ++ } ++ ++ ++ // Load (object->mark() | 1) into swap_reg %T2 ++ ldl(AT, obj_reg, 0); ++ or_ins( swap_reg, AT, 1); ++ ++ ++ // Save (object->mark() | 1) into BasicLock's displaced header ++ stl(swap_reg, lock_reg, mark_offset); ++ ++ assert(lock_offset == 0, "displached header must be first word in BasicObjectLock"); ++ //if (os::is_MP()) { ++ // lock(); ++ //} ++ cmpxchg(lock_reg, Address(obj_reg, 0), swap_reg); ++ ++ if (PrintBiasedLockingStatistics) { ++ Label L; ++ beq(AT, L); ++ push(T0); ++ push(T1); ++ atomic_inc32((address)BiasedLocking::fast_path_entry_count_addr(), 1, T0, T1); ++ pop(T1); ++ pop(T0); ++ BIND(L); ++ } ++ ++ bne(AT, done); ++ ++ // Test if the oopMark is an obvious stack pointer, i.e., ++ // 1) (mark & 3) == 0, and ++ // 2) SP <= mark < SP + os::pagesize() ++ // ++ // These 3 tests can be done by evaluating the following ++ // expression: ((mark - sp) & (3 - os::vm_page_size())), ++ // assuming both stack pointer and pagesize have their ++ // least significant 2 bits clear. ++ // NOTE: the oopMark is in swap_reg %T2 as the result of cmpxchg ++ ++ subl(swap_reg, swap_reg, SP); ++ move(AT, 3 - os::vm_page_size()); ++ and_reg(swap_reg, swap_reg, AT); ++ // Save the test result, for recursive case, the result is zero ++ stl(swap_reg, lock_reg, mark_offset); ++ if (PrintBiasedLockingStatistics) { ++ Label L; ++ bne(swap_reg, L); ++ push(T0); ++ push(T1); ++ atomic_inc32((address)BiasedLocking::fast_path_entry_count_addr(), 1, T0, T1); ++ pop(T1); ++ pop(T0); ++ BIND(L); ++ } ++ ++ beq(swap_reg, done); ++ BIND(slow_case); ++ // Call the runtime routine for slow case ++ call_VM(NOREG, CAST_FROM_FN_PTR(address, InterpreterRuntime::monitorenter), lock_reg); ++ ++ BIND(done); ++ } ++} ++ ++ ++// Unlocks an object. Used in monitorexit bytecode and ++// remove_activation. Throws an IllegalMonitorException if object is ++// not locked by current thread. ++// ++// Args: ++// c_rarg1: BasicObjectLock for lock ++// ++// Kills: ++// c_rarg0, c_rarg1, c_rarg2, c_rarg3, ... (param regs) ++// rscratch1, rscratch2 (scratch regs) ++// Argument: T6 : Points to BasicObjectLock structure for lock ++// Argument: c_rarg0 : Points to BasicObjectLock structure for lock ++// Throw an IllegalMonitorException if object is not locked by current thread ++void InterpreterMacroAssembler::unlock_object(Register lock_reg) { ++ assert(lock_reg == c_rarg0, "The argument is only for looks. It must be c_rarg0"); ++ ++ if (UseHeavyMonitors) { ++ call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::monitorexit), lock_reg); ++ } else { ++ Label done; ++ ++ const Register swap_reg = T2; // Must use T2 for cmpxchg instruction ++ const Register header_reg = T3; // Will contain the old oopMark ++ const Register obj_reg = T1; // Will contain the oop ++ ++ save_bcp(); // Save in case of exception ++ ++ // Convert from BasicObjectLock structure to object and BasicLock structure ++ // Store the BasicLock address into %T2 ++ add_simm16(swap_reg, lock_reg, BasicObjectLock::lock_offset_in_bytes()); ++ ++ // Load oop into obj_reg(%T1) ++ ldl(obj_reg, lock_reg, BasicObjectLock::obj_offset_in_bytes ()); ++ //free entry ++ stl(R0, lock_reg, BasicObjectLock::obj_offset_in_bytes()); ++ if (UseBiasedLocking) { ++ biased_locking_exit(obj_reg, header_reg, done); ++ } ++ ++ // Load the old header from BasicLock structure ++ ldl(header_reg, swap_reg, BasicLock::displaced_header_offset_in_bytes()); ++ // zero for recursive case ++ beq(header_reg, done); ++ ++ // Atomic swap back the old header ++ if (os::is_MP()); //lock(); ++ cmpxchg(header_reg, Address(obj_reg, 0), swap_reg); ++ ++ // zero for recursive case ++ bne(AT, done); ++ ++ // Call the runtime routine for slow case. ++ stl(obj_reg, lock_reg, BasicObjectLock::obj_offset_in_bytes()); // restore obj ++ call_VM(NOREG, ++ CAST_FROM_FN_PTR(address, InterpreterRuntime::monitorexit), ++ lock_reg); ++ ++ BIND(done); ++ ++ restore_bcp(); ++ } ++} ++ ++#ifndef CC_INTERP ++ ++void InterpreterMacroAssembler::test_method_data_pointer(Register mdp, ++ Label& zero_continue) { ++ assert(ProfileInterpreter, "must be profiling interpreter"); ++ ldl(mdp, Address(FP, frame::interpreter_frame_mdx_offset * wordSize)); ++ beq(mdp, zero_continue); ++} ++ ++ ++// Set the method data pointer for the current bcp. ++void InterpreterMacroAssembler::set_method_data_pointer_for_bcp() { ++ assert(ProfileInterpreter, "must be profiling interpreter"); ++ Label set_mdp; ++ ++ // V0 and T0 will be used as two temporary registers. ++ stl(V0, SP, (-1) * wordSize); ++ stl(T0, SP, (-2) * wordSize); ++ add_simm16(SP, SP, (-2) * wordSize); ++ ++ get_method(T0); ++ // Test MDO to avoid the call if it is NULL. ++ ldl(V0, T0, in_bytes(Method::method_data_offset())); ++ beq(V0, set_mdp); ++ ++ // method: T0 ++ // bcp: BCP --> S0 ++ call_VM_leaf(CAST_FROM_FN_PTR(address, InterpreterRuntime::bcp_to_di), T0, BCP); ++ // mdi: V0 ++ // mdo is guaranteed to be non-zero here, we checked for it before the call. ++ get_method(T0); ++ ldl(T0, T0, in_bytes(Method::method_data_offset())); ++ add_simm16(T0, T0, in_bytes(MethodData::data_offset())); ++ addl(V0, T0, V0); ++ BIND(set_mdp); ++ stl(V0, FP, frame::interpreter_frame_mdx_offset * wordSize); ++ add_simm16(SP, SP, 2 * wordSize); ++ ldl(V0, SP, (-1) * wordSize); ++ ldl(T0, SP, (-2) * wordSize); ++} ++ ++void InterpreterMacroAssembler::verify_method_data_pointer() { ++ assert(ProfileInterpreter, "must be profiling interpreter"); ++#ifdef ASSERT ++ Label verify_continue; ++ Register method = V0; ++ Register mdp = T4; ++ Register tmp = A0; ++ push(method); ++ push(mdp); ++ push(tmp); ++ test_method_data_pointer(mdp, verify_continue); // If mdp is zero, continue ++ get_method(method); ++ ++ // If the mdp is valid, it will point to a DataLayout header which is ++ // consistent with the bcp. The converse is highly probable also. ++ ldhu(tmp, mdp, in_bytes(DataLayout::bci_offset())); ++ ldl(AT, method, in_bytes(Method::const_offset())); ++ addl(tmp, tmp, AT); ++ add_simm16(tmp, tmp, in_bytes(ConstMethod::codes_offset())); ++ beq(tmp, BCP, verify_continue); ++ call_VM_leaf(CAST_FROM_FN_PTR(address, InterpreterRuntime::verify_mdp), method, BCP, mdp); ++ BIND(verify_continue); ++ pop(tmp); ++ pop(mdp); ++ pop(method); ++#endif // ASSERT ++} ++ ++ ++void InterpreterMacroAssembler::set_mdp_data_at(Register mdp_in, ++ int constant, ++ Register value) { ++ assert(ProfileInterpreter, "must be profiling interpreter"); ++ Address data(mdp_in, constant); ++ stl(value, data); ++} ++ ++ ++void InterpreterMacroAssembler::increment_mdp_data_at(Register mdp_in, ++ int constant, ++ bool decrement) { ++ // Counter address ++ Address data(mdp_in, constant); ++ ++ increment_mdp_data_at(data, decrement); ++} ++ ++void InterpreterMacroAssembler::increment_mdp_data_at(Address data, ++ bool decrement) { ++ assert(ProfileInterpreter, "must be profiling interpreter"); ++ // %%% this does 64bit counters at best it is wasting space ++ // at worst it is a rare bug when counters overflow ++ Register tmp = S0; ++ push(tmp); ++ if (decrement) { ++ // Decrement the register. ++ ldl(AT, data); ++ add_simm16(tmp, AT, (int32_t) -DataLayout::counter_increment); ++ // If the decrement causes the counter to overflow, stay negative ++ Label L; ++ cmplt(AT, tmp, R0); ++ bne(AT, L); ++ add_simm16(tmp, tmp, (int32_t) DataLayout::counter_increment); ++ BIND(L); ++ stl(tmp, data); ++ } else { ++ assert(DataLayout::counter_increment == 1, ++ "flow-free idiom only works with 1"); ++ ldl(AT, data); ++ // Increment the register. ++ add_simm16(tmp, AT, DataLayout::counter_increment); ++ // If the increment causes the counter to overflow, pull back by 1. ++ cmplt(AT, tmp, R0); ++ subl(tmp, tmp, AT); ++ stl(tmp, data); ++ } ++ pop(tmp); ++} ++ ++ ++void InterpreterMacroAssembler::increment_mdp_data_at(Register mdp_in, ++ Register reg, ++ int constant, ++ bool decrement) { ++ Register tmp = S0; ++ push(S0); ++ if (decrement) { ++ // Decrement the register. ++ addl(AT, mdp_in, reg); ++ assert(Assembler::is_simm16(constant), "constant is not a simm16 !"); ++ ldl(AT, AT, constant); ++ ++ add_simm16(tmp, AT, (int32_t) -DataLayout::counter_increment); ++ // If the decrement causes the counter to overflow, stay negative ++ Label L; ++ cmplt(AT, tmp, R0); ++ bne(AT, L); ++ add_simm16(tmp, tmp, (int32_t) DataLayout::counter_increment); ++ BIND(L); ++ ++ addl(AT, mdp_in, reg); ++ stl(tmp, AT, constant); ++ } else { ++ addl(AT, mdp_in, reg); ++ assert(Assembler::is_simm16(constant), "constant is not a simm16 !"); ++ ldl(AT, AT, constant); ++ ++ // Increment the register. ++ add_simm16(tmp, AT, DataLayout::counter_increment); ++ // If the increment causes the counter to overflow, pull back by 1. ++ cmplt(AT, tmp, R0); ++ subl(tmp, tmp, AT); ++ ++ addl(AT, mdp_in, reg); ++ stl(tmp, AT, constant); ++ } ++ pop(S0); ++} ++ ++void InterpreterMacroAssembler::set_mdp_flag_at(Register mdp_in, ++ int flag_byte_constant) { ++ assert(ProfileInterpreter, "must be profiling interpreter"); ++ int header_offset = in_bytes(DataLayout::header_offset()); ++ int header_bits = DataLayout::flag_mask_to_header_mask(flag_byte_constant); ++ // Set the flag ++ ldw_signed(AT, Address(mdp_in, header_offset)); ++ if(Assembler::is_uimm8(header_bits)) { ++ or_ins( AT, AT, header_bits); ++ } else { ++ ldi(GP, R0, header_bits); ++ or_ins(AT, AT, GP); ++ } ++ stw(AT, Address(mdp_in, header_offset)); ++} ++ ++ ++ ++void InterpreterMacroAssembler::test_mdp_data_at(Register mdp_in, ++ int offset, ++ Register value, ++ Register test_value_out, ++ Label& not_equal_continue) { ++ assert(ProfileInterpreter, "must be profiling interpreter"); ++ if (test_value_out == noreg) { ++ ldl(AT, Address(mdp_in, offset)); ++ bne(AT, value, not_equal_continue); ++ } else { ++ // Put the test value into a register, so caller can use it: ++ ldl(test_value_out, Address(mdp_in, offset)); ++ bne(value, test_value_out, not_equal_continue); ++ } ++} ++ ++ ++void InterpreterMacroAssembler::update_mdp_by_offset(Register mdp_in, ++ int offset_of_disp) { ++ assert(ProfileInterpreter, "must be profiling interpreter"); ++ assert(Assembler::is_simm16(offset_of_disp), "offset is not an simm16"); ++ ldl(AT, mdp_in, offset_of_disp); ++ addl(mdp_in, mdp_in, AT); ++ stl(mdp_in, Address(FP, frame::interpreter_frame_mdx_offset * wordSize)); ++} ++ ++ ++void InterpreterMacroAssembler::update_mdp_by_offset(Register mdp_in, ++ Register reg, ++ int offset_of_disp) { ++ assert(ProfileInterpreter, "must be profiling interpreter"); ++ addl(AT, reg, mdp_in); ++ assert(Assembler::is_simm16(offset_of_disp), "offset is not an simm16"); ++ ldl(AT, AT, offset_of_disp); ++ addl(mdp_in, mdp_in, AT); ++ stl(mdp_in, Address(FP, frame::interpreter_frame_mdx_offset * wordSize)); ++} ++ ++ ++void InterpreterMacroAssembler::update_mdp_by_constant(Register mdp_in, ++ int constant) { ++ assert(ProfileInterpreter, "must be profiling interpreter"); ++ if(Assembler::is_simm16(constant)) { ++ add_simm16(mdp_in, mdp_in, constant); ++ } else { ++ move(AT, constant); ++ addl(mdp_in, mdp_in, AT); ++ } ++ stl(mdp_in, Address(FP, frame::interpreter_frame_mdx_offset * wordSize)); ++} ++ ++ ++void InterpreterMacroAssembler::update_mdp_for_ret(Register return_bci) { ++ assert(ProfileInterpreter, "must be profiling interpreter"); ++ push(return_bci); // save/restore across call_VM ++ call_VM(noreg, ++ CAST_FROM_FN_PTR(address, InterpreterRuntime::update_mdp_for_ret), ++ return_bci); ++ pop(return_bci); ++} ++ ++ ++void InterpreterMacroAssembler::profile_taken_branch(Register mdp, ++ Register bumped_count) { ++ if (ProfileInterpreter) { ++ Label profile_continue; ++ ++ // If no method data exists, go to profile_continue. ++ // Otherwise, assign to mdp ++ test_method_data_pointer(mdp, profile_continue); ++ ++ // We are taking a branch. Increment the taken count. ++ // We inline increment_mdp_data_at to return bumped_count in a register ++ // increment_mdp_data_at(mdp, in_bytes(JumpData::taken_offset())); ++ ldl(bumped_count, mdp, in_bytes(JumpData::taken_offset())); ++ assert(DataLayout::counter_increment == 1, ++ "flow-free idiom only works with 1"); ++ push(T11); ++ // T11 is used as a temporary register. ++ add_simm16(T11, bumped_count, DataLayout::counter_increment); ++ cmplt(AT, T11, R0); ++ subl(bumped_count, T11, AT); ++ pop(T11); ++ stl(bumped_count, mdp, in_bytes(JumpData::taken_offset())); // Store back out ++ // The method data pointer needs to be updated to reflect the new target. ++ update_mdp_by_offset(mdp, in_bytes(JumpData::displacement_offset())); ++ BIND(profile_continue); ++ } ++} ++ ++ ++void InterpreterMacroAssembler::profile_not_taken_branch(Register mdp) { ++ if (ProfileInterpreter) { ++ Label profile_continue; ++ ++ // If no method data exists, go to profile_continue. ++ test_method_data_pointer(mdp, profile_continue); ++ ++ // We are taking a branch. Increment the not taken count. ++ increment_mdp_data_at(mdp, in_bytes(BranchData::not_taken_offset())); ++ ++ // The method data pointer needs to be updated to correspond to ++ // the next bytecode ++ update_mdp_by_constant(mdp, in_bytes(BranchData::branch_data_size())); ++ BIND(profile_continue); ++ } ++} ++ ++ ++void InterpreterMacroAssembler::profile_call(Register mdp) { ++ if (ProfileInterpreter) { ++ Label profile_continue; ++ ++ // If no method data exists, go to profile_continue. ++ test_method_data_pointer(mdp, profile_continue); ++ ++ // We are making a call. Increment the count. ++ increment_mdp_data_at(mdp, in_bytes(CounterData::count_offset())); ++ ++ // The method data pointer needs to be updated to reflect the new target. ++ update_mdp_by_constant(mdp, in_bytes(CounterData::counter_data_size())); ++ BIND(profile_continue); ++ } ++} ++ ++ ++void InterpreterMacroAssembler::profile_final_call(Register mdp) { ++ if (ProfileInterpreter) { ++ Label profile_continue; ++ ++ // If no method data exists, go to profile_continue. ++ test_method_data_pointer(mdp, profile_continue); ++ ++ // We are making a call. Increment the count. ++ increment_mdp_data_at(mdp, in_bytes(CounterData::count_offset())); ++ ++ // The method data pointer needs to be updated to reflect the new target. ++ update_mdp_by_constant(mdp, ++ in_bytes(VirtualCallData:: ++ virtual_call_data_size())); ++ BIND(profile_continue); ++ } ++} ++ ++ ++void InterpreterMacroAssembler::profile_virtual_call(Register receiver, ++ Register mdp, ++ Register reg2, ++ bool receiver_can_be_null) { ++ if (ProfileInterpreter) { ++ Label profile_continue; ++ ++ // If no method data exists, go to profile_continue. ++ test_method_data_pointer(mdp, profile_continue); ++ ++ Label skip_receiver_profile; ++ if (receiver_can_be_null) { ++ Label not_null; ++ bne(receiver, not_null); ++ // We are making a call. Increment the count. ++ increment_mdp_data_at(mdp, in_bytes(CounterData::count_offset())); ++ beq(R0, skip_receiver_profile); ++ BIND(not_null); ++ } ++ ++ // Record the receiver type. ++ record_klass_in_profile(receiver, mdp, reg2, true); ++ BIND(skip_receiver_profile); ++ ++ // The method data pointer needs to be updated to reflect the new target. ++ update_mdp_by_constant(mdp, ++ in_bytes(VirtualCallData:: ++ virtual_call_data_size())); ++ BIND(profile_continue); ++ } ++} ++ ++// This routine creates a state machine for updating the multi-row ++// type profile at a virtual call site (or other type-sensitive bytecode). ++// The machine visits each row (of receiver/count) until the receiver type ++// is found, or until it runs out of rows. At the same time, it remembers ++// the location of the first empty row. (An empty row records null for its ++// receiver, and can be allocated for a newly-observed receiver type.) ++// Because there are two degrees of freedom in the state, a simple linear ++// search will not work; it must be a decision tree. Hence this helper ++// function is recursive, to generate the required tree structured code. ++// It's the interpreter, so we are trading off code space for speed. ++// See below for example code. ++void InterpreterMacroAssembler::record_klass_in_profile_helper( ++ Register receiver, Register mdp, ++ Register reg2, int start_row, ++ Label& done, bool is_virtual_call) { ++ if (TypeProfileWidth == 0) { ++ if (is_virtual_call) { ++ increment_mdp_data_at(mdp, in_bytes(CounterData::count_offset())); ++ } ++ return; ++ } ++ ++ int last_row = VirtualCallData::row_limit() - 1; ++ assert(start_row <= last_row, "must be work left to do"); ++ // Test this row for both the receiver and for null. ++ // Take any of three different outcomes: ++ // 1. found receiver => increment count and goto done ++ // 2. found null => keep looking for case 1, maybe allocate this cell ++ // 3. found something else => keep looking for cases 1 and 2 ++ // Case 3 is handled by a recursive call. ++ for (int row = start_row; row <= last_row; row++) { ++ Label next_test; ++ bool test_for_null_also = (row == start_row); ++ ++ // See if the receiver is receiver[n]. ++ int recvr_offset = in_bytes(VirtualCallData::receiver_offset(row)); ++ test_mdp_data_at(mdp, recvr_offset, receiver, ++ (test_for_null_also ? reg2 : noreg), ++ next_test); ++ // (Reg2 now contains the receiver from the CallData.) ++ ++ // The receiver is receiver[n]. Increment count[n]. ++ int count_offset = in_bytes(VirtualCallData::receiver_count_offset(row)); ++ increment_mdp_data_at(mdp, count_offset); ++ beq(R0, done); ++ BIND(next_test); ++ ++ if (test_for_null_also) { ++ Label found_null; ++ // Failed the equality check on receiver[n]... Test for null. ++ if (start_row == last_row) { ++ // The only thing left to do is handle the null case. ++ if (is_virtual_call) { ++ beq(reg2, found_null); ++ // Receiver did not match any saved receiver and there is no empty row for it. ++ // Increment total counter to indicate polymorphic case. ++ increment_mdp_data_at(mdp, in_bytes(CounterData::count_offset())); ++ beq(R0, done); ++ BIND(found_null); ++ } else { ++ bne(reg2, done); ++ } ++ break; ++ } ++ // Since null is rare, make it be the branch-taken case. ++ beq(reg2, found_null); ++ ++ // Put all the "Case 3" tests here. ++ record_klass_in_profile_helper(receiver, mdp, reg2, start_row + 1, done, is_virtual_call); ++ ++ // Found a null. Keep searching for a matching receiver, ++ // but remember that this is an empty (unused) slot. ++ BIND(found_null); ++ } ++ } ++ ++ // In the fall-through case, we found no matching receiver, but we ++ // observed the receiver[start_row] is NULL. ++ ++ // Fill in the receiver field and increment the count. ++ int recvr_offset = in_bytes(VirtualCallData::receiver_offset(start_row)); ++ set_mdp_data_at(mdp, recvr_offset, receiver); ++ int count_offset = in_bytes(VirtualCallData::receiver_count_offset(start_row)); ++ move(reg2, DataLayout::counter_increment); ++ set_mdp_data_at(mdp, count_offset, reg2); ++ if (start_row > 0) { ++ beq(R0, done); ++ } ++} ++ ++// Example state machine code for three profile rows: ++// // main copy of decision tree, rooted at row[1] ++// if (row[0].rec == rec) { row[0].incr(); goto done; } ++// if (row[0].rec != NULL) { ++// // inner copy of decision tree, rooted at row[1] ++// if (row[1].rec == rec) { row[1].incr(); goto done; } ++// if (row[1].rec != NULL) { ++// // degenerate decision tree, rooted at row[2] ++// if (row[2].rec == rec) { row[2].incr(); goto done; } ++// if (row[2].rec != NULL) { goto done; } // overflow ++// row[2].init(rec); goto done; ++// } else { ++// // remember row[1] is empty ++// if (row[2].rec == rec) { row[2].incr(); goto done; } ++// row[1].init(rec); goto done; ++// } ++// } else { ++// // remember row[0] is empty ++// if (row[1].rec == rec) { row[1].incr(); goto done; } ++// if (row[2].rec == rec) { row[2].incr(); goto done; } ++// row[0].init(rec); goto done; ++// } ++// done: ++ ++void InterpreterMacroAssembler::record_klass_in_profile(Register receiver, ++ Register mdp, Register reg2, ++ bool is_virtual_call) { ++ assert(ProfileInterpreter, "must be profiling"); ++ Label done; ++ ++ record_klass_in_profile_helper(receiver, mdp, reg2, 0, done, is_virtual_call); ++ ++ BIND (done); ++} ++ ++void InterpreterMacroAssembler::profile_ret(Register return_bci, ++ Register mdp) { ++ if (ProfileInterpreter) { ++ Label profile_continue; ++ uint row; ++ ++ // If no method data exists, go to profile_continue. ++ test_method_data_pointer(mdp, profile_continue); ++ ++ // Update the total ret count. ++ increment_mdp_data_at(mdp, in_bytes(CounterData::count_offset())); ++ ++ for (row = 0; row < RetData::row_limit(); row++) { ++ Label next_test; ++ ++ // See if return_bci is equal to bci[n]: ++ test_mdp_data_at(mdp, ++ in_bytes(RetData::bci_offset(row)), ++ return_bci, noreg, ++ next_test); ++ ++ // return_bci is equal to bci[n]. Increment the count. ++ increment_mdp_data_at(mdp, in_bytes(RetData::bci_count_offset(row))); ++ ++ // The method data pointer needs to be updated to reflect the new target. ++ update_mdp_by_offset(mdp, ++ in_bytes(RetData::bci_displacement_offset(row))); ++ beq(R0, profile_continue); ++ BIND(next_test); ++ } ++ ++ update_mdp_for_ret(return_bci); ++ ++ BIND(profile_continue); ++ } ++} ++ ++ ++void InterpreterMacroAssembler::profile_null_seen(Register mdp) { ++ if (ProfileInterpreter) { ++ Label profile_continue; ++ ++ // If no method data exists, go to profile_continue. ++ test_method_data_pointer(mdp, profile_continue); ++ ++ set_mdp_flag_at(mdp, BitData::null_seen_byte_constant()); ++ ++ // The method data pointer needs to be updated. ++ int mdp_delta = in_bytes(BitData::bit_data_size()); ++ if (TypeProfileCasts) { ++ mdp_delta = in_bytes(VirtualCallData::virtual_call_data_size()); ++ } ++ update_mdp_by_constant(mdp, mdp_delta); ++ ++ BIND(profile_continue); ++ } ++} ++ ++ ++void InterpreterMacroAssembler::profile_typecheck_failed(Register mdp) { ++ if (ProfileInterpreter && TypeProfileCasts) { ++ Label profile_continue; ++ ++ // If no method data exists, go to profile_continue. ++ test_method_data_pointer(mdp, profile_continue); ++ ++ int count_offset = in_bytes(CounterData::count_offset()); ++ // Back up the address, since we have already bumped the mdp. ++ count_offset -= in_bytes(VirtualCallData::virtual_call_data_size()); ++ ++ // *Decrement* the counter. We expect to see zero or small negatives. ++ increment_mdp_data_at(mdp, count_offset, true); ++ ++ BIND (profile_continue); ++ } ++} ++ ++ ++void InterpreterMacroAssembler::profile_typecheck(Register mdp, Register klass, Register reg2) { ++ if (ProfileInterpreter) { ++ Label profile_continue; ++ ++ // If no method data exists, go to profile_continue. ++ test_method_data_pointer(mdp, profile_continue); ++ ++ // The method data pointer needs to be updated. ++ int mdp_delta = in_bytes(BitData::bit_data_size()); ++ if (TypeProfileCasts) { ++ mdp_delta = in_bytes(VirtualCallData::virtual_call_data_size()); ++ ++ // Record the object type. ++ record_klass_in_profile(klass, mdp, reg2, false); ++ } ++ update_mdp_by_constant(mdp, mdp_delta); ++ ++ BIND(profile_continue); ++ } ++} ++ ++ ++void InterpreterMacroAssembler::profile_switch_default(Register mdp) { ++ if (ProfileInterpreter) { ++ Label profile_continue; ++ ++ // If no method data exists, go to profile_continue. ++ test_method_data_pointer(mdp, profile_continue); ++ ++ // Update the default case count ++ increment_mdp_data_at(mdp, ++ in_bytes(MultiBranchData::default_count_offset())); ++ ++ // The method data pointer needs to be updated. ++ update_mdp_by_offset(mdp, ++ in_bytes(MultiBranchData:: ++ default_displacement_offset())); ++ ++ BIND(profile_continue); ++ } ++} ++ ++ ++void InterpreterMacroAssembler::profile_switch_case(Register index, ++ Register mdp, ++ Register reg2) { ++ if (ProfileInterpreter) { ++ Label profile_continue; ++ ++ // If no method data exists, go to profile_continue. ++ test_method_data_pointer(mdp, profile_continue); ++ ++ // Build the base (index * per_case_size_in_bytes()) + ++ // case_array_offset_in_bytes() ++ move(reg2, in_bytes(MultiBranchData::per_case_size())); ++ mull(index, reg2, index); ++ add_simm16(index, index, in_bytes(MultiBranchData::case_array_offset())); ++ ++ // Update the case count ++ increment_mdp_data_at(mdp, ++ index, ++ in_bytes(MultiBranchData::relative_count_offset())); ++ ++ // The method data pointer needs to be updated. ++ update_mdp_by_offset(mdp, ++ index, ++ in_bytes(MultiBranchData:: ++ relative_displacement_offset())); ++ ++ BIND(profile_continue); ++ } ++} ++ ++ ++void InterpreterMacroAssembler::narrow(Register result) { ++ ++ // Get method->_constMethod->_result_type ++ ldl(T9, FP, frame::interpreter_frame_method_offset * wordSize); ++ ldl(T9, T9, in_bytes(Method::const_offset())); ++ ldbu(T9, T9, in_bytes(ConstMethod::result_type_offset())); ++ ++ Label done, notBool, notByte, notChar; ++ ++ // common case first ++ subl(AT, T9, T_INT); ++ beq(AT, done); ++ ++ // mask integer result to narrower return type. ++ subl(AT, T9, T_BOOLEAN); ++ bne(AT, notBool); ++ and_imm8(result, result, 0x1); ++ beq(R0, done); ++ ++ BIND(notBool); ++ subl(AT, T9, T_BYTE); ++ bne(AT, notByte); ++ sextb(result, result); ++ beq(R0, done); ++ ++ BIND(notByte); ++ subl(AT, T9, T_CHAR); ++ bne(AT, notChar); ++ zapnot(result, result, 0x3); ++ beq(R0, done); ++ ++ BIND(notChar); ++ sexth(result, result); ++ ++ // Nothing to do for T_INT ++ BIND(done); ++} ++ ++ ++void InterpreterMacroAssembler::profile_obj_type(Register obj, const Address& mdo_addr) { ++ Label update, next, none; ++ ++ verify_oop(obj); ++ ++ bne(obj, update); ++ ++ push(T1); ++ if (mdo_addr.index() == noreg) { ++ ldl(T1, mdo_addr.base(), mdo_addr.disp()); ++ } else { ++ guarantee(T1 != mdo_addr.base(), "The base register will be corrupted !"); ++ guarantee(T1 != mdo_addr.index(), "The index register will be corrupted !"); ++ ++ slll(AT, mdo_addr.index(), mdo_addr.scale()); ++ addl(AT, mdo_addr.base(), AT); ++ ldl(T1, AT, mdo_addr.disp()); ++ } ++ or_ins( AT, T1, TypeEntries::null_seen); ++ if (mdo_addr.index() == noreg) { ++ stl(AT, mdo_addr); ++ } else { ++ guarantee(T1 != mdo_addr.base(), "The base register will be corrupted !"); ++ guarantee(T1 != mdo_addr.index(), "The index register will be corrupted !"); ++ ++ slll(T1, mdo_addr.index(), mdo_addr.scale()); ++ addl(T1, T1, mdo_addr.base()); ++ stl(AT, T1, mdo_addr.disp()); ++ } ++ pop(T1); ++ ++ beq(R0, next); ++ ++ BIND(update); ++ load_klass(obj, obj); ++ ++ if (mdo_addr.index() == noreg) { ++ ldl(AT, mdo_addr.base(), mdo_addr.disp()); ++ } else { ++ slll(AT, mdo_addr.index(), mdo_addr.scale()); ++ addl(AT, AT, mdo_addr.base()); ++ ldl(AT, AT, mdo_addr.disp()); ++ } ++ xor_ins(obj, obj, AT); ++ ++ ldi(AT, R0, TypeEntries::type_klass_mask); ++ and_reg(AT, obj, AT); ++ beq(AT, next); ++ ++ and_imm8(AT, obj, TypeEntries::type_unknown); ++ bne(AT, next); ++ ++ if (mdo_addr.index() == noreg) { ++ ldl(AT, mdo_addr.base(), mdo_addr.disp()); ++ } else { ++ slll(AT, mdo_addr.index(), mdo_addr.scale()); ++ addl(AT, AT, mdo_addr.base()); ++ ldl(AT, AT, mdo_addr.disp()); ++ } ++ beq(AT, none); ++ ++ push(T1); ++ if (mdo_addr.index() == noreg) { ++ ldl(T1, mdo_addr.base(), mdo_addr.disp()); ++ } else { ++ guarantee(T1 != mdo_addr.base(), "The base register will be corrupted !"); ++ guarantee(T1 != mdo_addr.index(), "The index register will be corrupted !"); ++ ++ slll(AT, mdo_addr.index(), mdo_addr.scale()); ++ addl(AT, AT, mdo_addr.base()); ++ ldl(T1, AT, mdo_addr.disp()); ++ } ++ subl(T1, AT, TypeEntries::null_seen); ++ pop(T1); ++ beq(AT, none); ++ ++ // There is a chance that the checks above (re-reading profiling ++ // data from memory) fail if another thread has just set the ++ // profiling to this obj's klass ++ if (mdo_addr.index() == noreg) { ++ ldl(AT, mdo_addr.base(), mdo_addr.disp()); ++ } else { ++ slll(AT, mdo_addr.index(), mdo_addr.scale()); ++ addl(AT, AT, mdo_addr.base()); ++ ldl(AT, AT, mdo_addr.disp()); ++ } ++ xor_ins(obj, obj, AT); ++ ldi(AT, R0, TypeEntries::type_klass_mask); ++ and_reg(AT, obj, AT); ++ beq(AT, next); ++ ++ // different than before. Cannot keep accurate profile. ++ push(T1); ++ if (mdo_addr.index() == noreg) { ++ ldl(T1, mdo_addr.base(), mdo_addr.disp()); ++ } else { ++ guarantee(T1 != mdo_addr.base(), "The base register will be corrupted !"); ++ guarantee(T1 != mdo_addr.index(), "The index register will be corrupted !"); ++ ++ slll(AT, mdo_addr.index(), mdo_addr.scale()); ++ addl(AT, AT, mdo_addr.base()); ++ ldl(T1, AT, mdo_addr.disp()); ++ } ++ or_ins( AT, T1, TypeEntries::type_unknown); ++ if (mdo_addr.index() == noreg) { ++ stl(AT, mdo_addr); ++ } else { ++ guarantee(T1 != mdo_addr.base(), "The base register will be corrupted !"); ++ guarantee(T1 != mdo_addr.index(), "The index register will be corrupted !"); ++ ++ slll(T1, mdo_addr.index(), mdo_addr.scale()); ++ addl(T1, T1, mdo_addr.base()); ++ stl(AT, T1, mdo_addr.disp()); ++ } ++ pop(T1); ++ beq(R0, next); ++ ++ ++ BIND(none); ++ // first time here. Set profile type. ++ if (mdo_addr.index() == noreg) { ++ stl(obj, mdo_addr); ++ } else { ++ slll(AT, mdo_addr.index(), mdo_addr.scale()); ++ addl(AT, AT, mdo_addr.base()); ++ stl(obj, AT, mdo_addr.disp()); ++ } ++ ++ BIND(next); ++} ++ ++void InterpreterMacroAssembler::profile_arguments_type(Register mdp, Register callee, Register tmp, bool is_virtual) { ++ if (!ProfileInterpreter) { ++ return; ++ } ++ ++ if (MethodData::profile_arguments() || MethodData::profile_return()) { ++ Label profile_continue; ++ ++ test_method_data_pointer(mdp, profile_continue); ++ ++ int off_to_start = is_virtual ? in_bytes(VirtualCallData::virtual_call_data_size()) : in_bytes(CounterData::counter_data_size()); ++ ++ ldbu(AT, mdp, in_bytes(DataLayout::tag_offset()) - off_to_start); ++ cmpeq(GP, AT, is_virtual ? DataLayout::virtual_call_type_data_tag : DataLayout::call_type_data_tag); ++ beq(GP, profile_continue); ++ ++ ++ if (MethodData::profile_arguments()) { ++ Label done; ++ int off_to_args = in_bytes(TypeEntriesAtCall::args_data_offset()); ++ if (Assembler::is_simm16(off_to_args)) { ++ add_simm16(mdp, mdp, off_to_args); ++ } else { ++ move(AT, off_to_args); ++ addl(mdp, mdp, AT); ++ } ++ ++ ++ for (int i = 0; i < TypeProfileArgsLimit; i++) { ++ if (i > 0 || MethodData::profile_return()) { ++ // If return value type is profiled we may have no argument to profile ++ ldl(tmp, mdp, in_bytes(TypeEntriesAtCall::cell_count_offset())-off_to_args); ++ ++ if (Assembler::is_simm16(i * TypeStackSlotEntries::per_arg_count())) { ++ ldi(tmp, tmp, -1 * i * TypeStackSlotEntries::per_arg_count()); ++ } else { ++ li(AT, i*TypeStackSlotEntries::per_arg_count()); ++ subl(tmp, tmp, AT); ++ } ++ ++ cmplt(AT, tmp, TypeStackSlotEntries::per_arg_count()); ++ bne(AT, done); ++ } ++ ldl(tmp, callee, in_bytes(Method::const_offset())); ++ ++ ldhu(tmp, tmp, in_bytes(ConstMethod::size_of_parameters_offset())); ++ ++ // stack offset o (zero based) from the start of the argument ++ // list, for n arguments translates into offset n - o - 1 from ++ // the end of the argument list ++ ldl(AT, mdp, in_bytes(TypeEntriesAtCall::stack_slot_offset(i))-off_to_args); ++ subl(tmp, tmp, AT); ++ ++ subl(tmp, tmp, 1); ++ ++ Address arg_addr = argument_address(tmp); ++ ldl(tmp, arg_addr.base(), arg_addr.disp()); ++ ++ Address mdo_arg_addr(mdp, in_bytes(TypeEntriesAtCall::argument_type_offset(i))-off_to_args); ++ profile_obj_type(tmp, mdo_arg_addr); ++ ++ int to_add = in_bytes(TypeStackSlotEntries::per_arg_size()); ++ if (Assembler::is_simm16(to_add)) { ++ add_simm16(mdp, mdp, to_add); ++ } else { ++ move(AT, to_add); ++ addl(mdp, mdp, AT); ++ } ++ ++ off_to_args += to_add; ++ } ++ ++ if (MethodData::profile_return()) { ++ ldl(tmp, mdp, in_bytes(TypeEntriesAtCall::cell_count_offset())-off_to_args); ++ ++ int tmp_arg_counts = TypeProfileArgsLimit*TypeStackSlotEntries::per_arg_count(); ++ if (Assembler::is_simm16(-1 * tmp_arg_counts)) { ++ subl(tmp, tmp, 1 * tmp_arg_counts); ++ } else { ++ move(AT, tmp_arg_counts); ++ subw(mdp, mdp, AT); ++ } ++ } ++ ++ BIND(done); ++ ++ if (MethodData::profile_return()) { ++ // We're right after the type profile for the last ++ // argument. tmp is the number of cells left in the ++ // CallTypeData/VirtualCallTypeData to reach its end. Non null ++ // if there's a return to profile. ++ assert(ReturnTypeEntry::static_cell_count() < TypeStackSlotEntries::per_arg_count(), "can't move past ret type"); ++ sllw_signed(tmp, tmp, exact_log2(DataLayout::cell_size)); ++ addl(mdp, mdp, tmp); ++ } ++ stl(mdp, FP, frame::interpreter_frame_mdx_offset * wordSize); ++ } else { ++ assert(MethodData::profile_return(), "either profile call args or call ret"); ++ update_mdp_by_constant(mdp, in_bytes(TypeEntriesAtCall::return_only_size())); ++ } ++ ++ // mdp points right after the end of the ++ // CallTypeData/VirtualCallTypeData, right after the cells for the ++ // return value type if there's one ++ ++ BIND(profile_continue); ++ } ++} ++ ++void InterpreterMacroAssembler::profile_return_type(Register mdp, Register ret, Register tmp) { ++ assert_different_registers(mdp, ret, tmp, _bcp_register); ++ if (ProfileInterpreter && MethodData::profile_return()) { ++ Label profile_continue, done; ++ ++ test_method_data_pointer(mdp, profile_continue); ++ ++ if (MethodData::profile_return_jsr292_only()) { ++ // If we don't profile all invoke bytecodes we must make sure ++ // it's a bytecode we indeed profile. We can't go back to the ++ // begining of the ProfileData we intend to update to check its ++ // type because we're right after it and we don't known its ++ // length ++ Label do_profile; ++ ldbu(AT, _bcp_register, 0); ++ add_simm16(AT, AT, -1 * Bytecodes::_invokedynamic); ++ beq(AT, do_profile); ++ ++ ldbu(AT, _bcp_register, 0); ++ add_simm16(AT, AT, -1 * Bytecodes::_invokehandle); ++ beq(AT, do_profile); ++ ++ get_method(tmp); ++ ldbu(tmp, tmp, Method::intrinsic_id_offset_in_bytes()); ++ cmpeq(AT, tmp, vmIntrinsics::_compiledLambdaForm); ++ beq(AT, offset(target(profile_continue))); ++ ++ BIND(do_profile); ++ } ++ ++ Address mdo_ret_addr(mdp, -in_bytes(ReturnTypeEntry::size())); ++ addl(tmp, ret, R0); ++ profile_obj_type(tmp, mdo_ret_addr); ++ ++ BIND(profile_continue); ++ } ++} ++ ++void InterpreterMacroAssembler::profile_parameters_type(Register mdp, Register tmp1, Register tmp2) { ++ ++ if (ProfileInterpreter && MethodData::profile_parameters()) { ++ Label profile_continue, done; ++ ++ test_method_data_pointer(mdp, profile_continue); ++ ++ // Load the offset of the area within the MDO used for ++ // parameters. If it's negative we're not profiling any parameters ++ ldw(tmp1, mdp, in_bytes(MethodData::parameters_type_data_di_offset()) - in_bytes(MethodData::data_offset())); ++ blt(tmp1, profile_continue); ++ ++ // Compute a pointer to the area for parameters from the offset ++ // and move the pointer to the slot for the last ++ // parameters. Collect profiling from last parameter down. ++ // mdo start + parameters offset + array length - 1 ++ addl(mdp, mdp, tmp1); ++ ldl(tmp1, mdp, in_bytes(ArrayData::array_len_offset())); ++ decrement(tmp1, TypeStackSlotEntries::per_arg_count()); ++ ++ ++ Label loop; ++ BIND(loop); ++ ++ int off_base = in_bytes(ParametersTypeData::stack_slot_offset(0)); ++ int type_base = in_bytes(ParametersTypeData::type_offset(0)); ++ Address::ScaleFactor per_arg_scale = Address::times(DataLayout::cell_size); ++ Address arg_type(mdp, tmp1, per_arg_scale, type_base); ++ ++ // load offset on the stack from the slot for this parameter ++ slll(AT, tmp1, per_arg_scale); ++ addl(AT, AT, mdp); ++ ldl(tmp2, AT, off_base); ++ ++ subl(tmp2, R0, tmp2); ++ ++ // read the parameter from the local area ++ slll(AT, tmp2, Interpreter::stackElementScale()); ++ addl(AT, AT, _locals_register); ++ ldl(tmp2, AT, 0); ++ ++ // profile the parameter ++ profile_obj_type(tmp2, arg_type); ++ ++ // go to next parameter ++ decrement(tmp1, TypeStackSlotEntries::per_arg_count()); ++ bgt(tmp1, loop); ++ ++ BIND(profile_continue); ++ } ++} ++ ++void InterpreterMacroAssembler::verify_oop(Register reg, TosState state) { ++ if (state == atos) { ++ MacroAssembler::verify_oop(reg); ++ } ++} ++ ++void InterpreterMacroAssembler::verify_FPU(int stack_depth, TosState state) { ++} ++#endif // !CC_INTERP ++ ++ ++void InterpreterMacroAssembler::notify_method_entry() { ++ // Whenever JVMTI is interp_only_mode, method entry/exit events are sent to ++ // track stack depth. If it is possible to enter interp_only_mode we add ++ // the code to check if the event should be sent. ++ Register tempreg = T0; ++ move(T11, S2thread); ++ if (JvmtiExport::can_post_interpreter_events()) { ++ Label L; ++ ldw(tempreg, T11, in_bytes(JavaThread::interp_only_mode_offset())); ++ beq(tempreg, L); ++ call_VM(noreg, CAST_FROM_FN_PTR(address, ++ InterpreterRuntime::post_method_entry)); ++ BIND(L); ++ } ++ ++ { ++ SkipIfEqual skip_if(this, &DTraceMethodProbes, 0); ++ get_method(S3); ++ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_entry), ++ //Rthread, ++ T11, ++ //Rmethod); ++ S3); ++ } ++ ++} ++ ++void InterpreterMacroAssembler::notify_method_exit( ++ //TosState state, NotifyMethodExitMode mode) { ++ bool is_native_method, TosState state, NotifyMethodExitMode mode) { ++ // Whenever JVMTI is interp_only_mode, method entry/exit events are sent to ++ // track stack depth. If it is possible to enter interp_only_mode we add ++ // the code to check if the event should be sent. ++ Register tempreg = T0; ++ move(T11, S2thread); ++ if (mode == NotifyJVMTI && JvmtiExport::can_post_interpreter_events()) { ++ Label skip; ++ ldw(tempreg, T11, in_bytes(JavaThread::interp_only_mode_offset())); ++ beq(tempreg, skip); ++ // Note: frame::interpreter_frame_result has a dependency on how the ++ // method result is saved across the call to post_method_exit. If this ++ // is changed then the interpreter_frame_result implementation will ++ // need to be updated too. ++ ++ // For c++ interpreter the result is always stored at a known location in the frame ++ // template interpreter will leave it on the top of the stack. ++ save_return_value(state, is_native_method); ++ call_VM(noreg, ++ CAST_FROM_FN_PTR(address, InterpreterRuntime::post_method_exit)); ++ restore_return_value(state, is_native_method); ++ BIND(skip); ++ } ++ ++ { ++ // Dtrace notification ++ SkipIfEqual skip_if(this, &DTraceMethodProbes, 0); ++ save_return_value(state, is_native_method); ++ get_method(S3); ++ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), ++ //Rthread, Rmethod); ++ T11, S3); ++ restore_return_value(state, is_native_method); ++ } ++} ++ ++void InterpreterMacroAssembler::save_return_value(TosState state, bool is_native_call) { ++ if (is_native_call) { ++ // save any potential method result value ++ stw(V0, FP, (-9) * wordSize); ++ fsts(F0, FP, (-10) * wordSize); ++ } else { ++ push(state); ++ } ++} ++ ++void InterpreterMacroAssembler::restore_return_value(TosState state, bool is_native_call) { ++ if (is_native_call) { ++ // Restore any method result value ++ ldw(V0, FP, (-9) * wordSize); ++ flds(F0, FP, (-10) * wordSize); ++ } else { ++ pop(state); ++ } ++} ++ ++// Jump if ((*counter_addr += increment) & mask) satisfies the condition. ++void InterpreterMacroAssembler::increment_mask_and_jump(Address counter_addr, ++ int increment, int mask, ++ Register scratch, bool preloaded, ++ Condition cond, Label* where) { ++ assert_different_registers(scratch, AT); ++ ++ if (!preloaded) { ++ ldw_signed(scratch, counter_addr); ++ } ++ addl(scratch, scratch, increment); ++ stw(scratch, counter_addr); ++ ++ move(AT, mask); ++ and_reg(scratch, scratch, AT); ++ ++ if (cond == Assembler::zero) { ++ beq(scratch, *where); ++ } else { ++ unimplemented(); ++ } ++} +diff --git a/hotspot/src/cpu/sw64/vm/interp_masm_sw64.hpp b/hotspot/src/cpu/sw64/vm/interp_masm_sw64.hpp +new file mode 100755 +index 0000000000..366dadaca3 +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/interp_masm_sw64.hpp +@@ -0,0 +1,270 @@ ++/* ++ * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_SW64_VM_INTERP_MASM_SW64_HPP ++#define CPU_SW64_VM_INTERP_MASM_SW64_HPP ++ ++#include "asm/assembler.hpp" ++#include "asm/macroAssembler.hpp" ++#include "asm/macroAssembler.inline.hpp" ++#include "interpreter/invocationCounter.hpp" ++#include "runtime/frame.hpp" ++ ++// This file specializes the assember with interpreter-specific macros ++ ++ ++class InterpreterMacroAssembler: public MacroAssembler { ++#ifndef CC_INTERP ++ private: ++ ++ Register _locals_register; // register that contains the pointer to the locals ++ Register _bcp_register; // register that contains the bcp ++ ++ protected: ++ // Interpreter specific version of call_VM_base ++ virtual void call_VM_leaf_base(address entry_point, ++ int number_of_arguments); ++ ++ virtual void call_VM_base(Register oop_result, ++ Register java_thread, ++ Register last_java_sp, ++ address entry_point, ++ int number_of_arguments, ++ bool check_exceptions); ++ ++ virtual void check_and_handle_popframe(Register java_thread); ++ virtual void check_and_handle_earlyret(Register java_thread); ++ ++ // base routine for all dispatches ++ void dispatch_base(TosState state, address* table, bool verifyoop = true); ++#endif // CC_INTERP ++ ++ public: ++ // narrow int return value ++ void narrow(Register result); ++ ++ InterpreterMacroAssembler(CodeBuffer* code) : MacroAssembler(code), _locals_register(LVP), _bcp_register(BCP) {} ++ ++ void get_2_byte_integer_at_bcp(Register reg, Register tmp, int offset); ++ void get_4_byte_integer_at_bcp(Register reg, Register tmp, int offset); ++ ++ void load_earlyret_value(TosState state); ++ ++#ifdef CC_INTERP ++ void save_bcp() { /* not needed in c++ interpreter and harmless */ } ++ void restore_bcp() { /* not needed in c++ interpreter and harmless */ } ++ ++ // Helpers for runtime call arguments/results ++ void get_method(Register reg); ++ ++#else ++ ++ // Interpreter-specific registers ++ void save_bcp() { ++ stl(BCP, FP, frame::interpreter_frame_bcx_offset * wordSize); ++ } ++ ++ void restore_bcp() { ++ ldl(BCP, FP, frame::interpreter_frame_bcx_offset * wordSize); ++ } ++ ++ void restore_locals() { ++ ldl(LVP, FP, frame::interpreter_frame_locals_offset * wordSize); ++ } ++ ++ // Helpers for runtime call arguments/results ++ void get_method(Register reg) { ++ ldl(reg, FP, frame::interpreter_frame_method_offset * wordSize); ++ } ++ ++ void get_const(Register reg){ ++ get_method(reg); ++ ldl(reg, reg, in_bytes(Method::const_offset())); ++ } ++ ++ void get_constant_pool(Register reg) { ++ get_const(reg); ++ ldl(reg, reg, in_bytes(ConstMethod::constants_offset())); ++ } ++ ++ void get_constant_pool_cache(Register reg) { ++ get_constant_pool(reg); ++ ldl(reg, reg, ConstantPool::cache_offset_in_bytes()); ++ } ++ ++ void get_cpool_and_tags(Register cpool, Register tags) { ++ get_constant_pool(cpool); ++ ldl(tags, cpool, ConstantPool::tags_offset_in_bytes()); ++ } ++ ++ void get_unsigned_2_byte_index_at_bcp(Register reg, int bcp_offset); ++ void get_cache_and_index_at_bcp(Register cache, Register index, int bcp_offset, size_t index_size = sizeof(u2)); ++ void get_cache_and_index_and_bytecode_at_bcp(Register cache, Register index, Register bytecode, int byte_no, int bcp_offset, size_t index_size = sizeof(u2)); ++ void get_cache_entry_pointer_at_bcp(Register cache, Register tmp, int bcp_offset, size_t index_size = sizeof(u2)); ++ void get_cache_index_at_bcp(Register index, int bcp_offset, size_t index_size = sizeof(u2)); ++ void get_method_counters(Register method, Register mcs, Label& skip); ++ ++ // load cpool->resolved_references(index); ++ void load_resolved_reference_at_index(Register result, Register index); ++ ++ void pop_ptr( Register r = FSR); ++ void pop_i( Register r = FSR); ++ void pop_l( Register r = FSR); ++ void pop_f(FloatRegister r = FSF); ++ void pop_d(FloatRegister r = FSF); ++ ++ void push_ptr( Register r = FSR); ++ void push_i( Register r = FSR); ++ void push_l( Register r = FSR); ++ void push_f(FloatRegister r = FSF); ++ void push_d(FloatRegister r = FSF); ++ ++ void pop(Register r) { ((MacroAssembler*)this)->pop(r); } ++ ++ void push(Register r) { ((MacroAssembler*)this)->push(r); } ++ ++ void pop(TosState state); // transition vtos -> state ++ void push(TosState state); // transition state -> vtos ++ ++ void empty_expression_stack() { ++ ldl(SP, FP, frame::interpreter_frame_monitor_block_top_offset * wordSize); ++ // NULL last_sp until next java call ++ stl(R0, FP, frame::interpreter_frame_last_sp_offset * wordSize); ++ } ++ ++ // Super call_VM calls - correspond to MacroAssembler::call_VM(_leaf) calls ++ void load_ptr(int n, Register val); ++ void store_ptr(int n, Register val); ++ ++ // Generate a subtype check: branch to ok_is_subtype if sub_klass is ++ // a subtype of super_klass. ++ //void gen_subtype_check( Register sub_klass, Label &ok_is_subtype ); ++ void gen_subtype_check( Register Rsup_klass, Register sub_klass, Label &ok_is_subtype ); ++ ++ // Dispatching ++ void dispatch_prolog(TosState state, int step = 0); ++ void dispatch_epilog(TosState state, int step = 0); ++ void dispatch_only(TosState state); ++ void dispatch_only_normal(TosState state); ++ void dispatch_only_noverify(TosState state); ++ void dispatch_next(TosState state, int step = 0); ++ void dispatch_via (TosState state, address* table); ++ ++ // jump to an invoked target ++ void prepare_to_jump_from_interpreted(); ++ void jump_from_interpreted(Register method, Register temp); ++ ++ ++ // Returning from interpreted functions ++ // ++ // Removes the current activation (incl. unlocking of monitors) ++ // and sets up the return address. This code is also used for ++ // exception unwindwing. In that case, we do not want to throw ++ // IllegalMonitorStateExceptions, since that might get us into an ++ // infinite rethrow exception loop. ++ // Additionally this code is used for popFrame and earlyReturn. ++ // In popFrame case we want to skip throwing an exception, ++ // installing an exception, and notifying jvmdi. ++ // In earlyReturn case we only want to skip throwing an exception ++ // and installing an exception. ++ void remove_activation(TosState state, Register ret_addr, ++ bool throw_monitor_exception = true, ++ bool install_monitor_exception = true, ++ bool notify_jvmdi = true); ++#endif // CC_INTERP ++ ++ // Object locking ++ void lock_object (Register lock_reg); ++ void unlock_object(Register lock_reg); ++ ++#ifndef CC_INTERP ++ ++ // Interpreter profiling operations ++ void set_method_data_pointer_for_bcp(); ++ void test_method_data_pointer(Register mdp, Label& zero_continue); ++ void verify_method_data_pointer(); ++ ++ void set_mdp_data_at(Register mdp_in, int constant, Register value); ++ void increment_mdp_data_at(Address data, bool decrement = false); ++ void increment_mdp_data_at(Register mdp_in, int constant, ++ bool decrement = false); ++ void increment_mdp_data_at(Register mdp_in, Register reg, int constant, ++ bool decrement = false); ++ void increment_mask_and_jump(Address counter_addr, ++ int increment, int mask, ++ Register scratch, bool preloaded, ++ Condition cond, Label* where); ++ void set_mdp_flag_at(Register mdp_in, int flag_constant); ++ void test_mdp_data_at(Register mdp_in, int offset, Register value, ++ Register test_value_out, ++ Label& not_equal_continue); ++ ++ void record_klass_in_profile(Register receiver, Register mdp, ++ Register reg2, bool is_virtual_call); ++ void record_klass_in_profile_helper(Register receiver, Register mdp, ++ Register reg2, int start_row, ++ Label& done, bool is_virtual_call); ++ ++ void update_mdp_by_offset(Register mdp_in, int offset_of_offset); ++ void update_mdp_by_offset(Register mdp_in, Register reg, int offset_of_disp); ++ void update_mdp_by_constant(Register mdp_in, int constant); ++ void update_mdp_for_ret(Register return_bci); ++ ++ void profile_taken_branch(Register mdp, Register bumped_count); ++ void profile_not_taken_branch(Register mdp); ++ void profile_call(Register mdp); ++ void profile_final_call(Register mdp); ++ void profile_virtual_call(Register receiver, Register mdp, ++ Register scratch2, ++ bool receiver_can_be_null = false); ++ void profile_ret(Register return_bci, Register mdp); ++ void profile_null_seen(Register mdp); ++ void profile_typecheck(Register mdp, Register klass, Register scratch); ++ void profile_typecheck_failed(Register mdp); ++ void profile_switch_default(Register mdp); ++ void profile_switch_case(Register index_in_scratch, Register mdp, ++ Register scratch2); ++ ++ // Debugging ++ // only if +VerifyOops && state == atos ++ void verify_oop(Register reg, TosState state = atos); ++ // only if +VerifyFPU && (state == ftos || state == dtos) ++ void verify_FPU(int stack_depth, TosState state = ftos); ++ ++ void profile_obj_type(Register obj, const Address& mdo_addr); ++ void profile_arguments_type(Register mdp, Register callee, Register tmp, bool is_virtual); ++ void profile_return_type(Register mdp, Register ret, Register tmp); ++ void profile_parameters_type(Register mdp, Register tmp1, Register tmp2); ++#endif // !CC_INTERP ++ ++ typedef enum { NotifyJVMTI, SkipNotifyJVMTI } NotifyMethodExitMode; ++ ++ // support for jvmti/dtrace ++ void notify_method_entry(); ++ void notify_method_exit(bool is_native_method, TosState state, NotifyMethodExitMode mode); ++ void save_return_value(TosState state, bool is_native_call); ++ void restore_return_value(TosState state, bool is_native_call); ++}; ++ ++#endif // CPU_SW64_VM_INTERP_MASM_SW64_HPP +diff --git a/hotspot/src/cpu/sw64/vm/interpreterGenerator_sw64.hpp b/hotspot/src/cpu/sw64/vm/interpreterGenerator_sw64.hpp +new file mode 100755 +index 0000000000..c4bfb8d8d9 +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/interpreterGenerator_sw64.hpp +@@ -0,0 +1,51 @@ ++/* ++ * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_SW64_VM_INTERPRETERGENERATOR_SW64_HPP ++#define CPU_SW64_VM_INTERPRETERGENERATOR_SW64_HPP ++ ++ ++// Generation of Interpreter ++// ++ friend class AbstractInterpreterGenerator; ++ ++ private: ++ ++ address generate_normal_entry(bool synchronized); ++ address generate_native_entry(bool synchronized); ++ address generate_abstract_entry(void); ++ address generate_math_entry(AbstractInterpreter::MethodKind kind); ++ address generate_empty_entry(void); ++ address generate_accessor_entry(void); ++ address generate_Reference_get_entry(); ++ address generate_CRC32_update_entry(); ++ address generate_CRC32_updateBytes_entry(AbstractInterpreter::MethodKind kind); ++ ++ void lock_method(void); ++ void generate_stack_overflow_check(void); ++ ++ void generate_counter_incr(Label* overflow, Label* profile_method, Label* profile_method_continue); ++ void generate_counter_overflow(Label* do_continue); ++ ++#endif // CPU_SW64_VM_INTERPRETERGENERATOR_SW64_HPP +diff --git a/hotspot/src/cpu/sw64/vm/interpreterRT_sw64.cpp b/hotspot/src/cpu/sw64/vm/interpreterRT_sw64.cpp +new file mode 100755 +index 0000000000..d07b2f8952 +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/interpreterRT_sw64.cpp +@@ -0,0 +1,240 @@ ++/* ++ * Copyright (c) 2003, 2012, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#include "precompiled.hpp" ++#include "interpreter/interpreter.hpp" ++#include "interpreter/interpreterRuntime.hpp" ++#include "memory/allocation.inline.hpp" ++#include "memory/universe.inline.hpp" ++#include "oops/method.hpp" ++#include "oops/oop.inline.hpp" ++#include "runtime/handles.inline.hpp" ++#include "runtime/icache.hpp" ++#include "runtime/interfaceSupport.hpp" ++#include "runtime/signature.hpp" ++ ++#define __ _masm-> ++ ++#ifdef PRODUCT ++#define BLOCK_COMMENT(str) /* nothing */ ++#else ++#define BLOCK_COMMENT(str) { char line[1024];sprintf(line,"%s:%s:%d",str,__FILE__, __LINE__); __ block_comment(line);} ++#endif ++ ++#define BIND(label) bind(label); BLOCK_COMMENT(#label ":") ++ ++// Implementation of SignatureHandlerGenerator ++ ++void InterpreterRuntime::SignatureHandlerGenerator::move(int from_offset, int to_offset) { ++ __ ldl(temp(), from(), Interpreter::local_offset_in_bytes(from_offset)); ++ __ stl(temp(), to(), to_offset * longSize); ++} ++ ++void InterpreterRuntime::SignatureHandlerGenerator::box(int from_offset, int to_offset) { ++ __ add_simm16(temp(), from(), Interpreter::local_offset_in_bytes(from_offset) ); ++ __ ldw(AT, from(), Interpreter::local_offset_in_bytes(from_offset) ); ++ ++ Label L; ++ __ bne(AT, L); ++ __ move(temp(), R0); ++ __ BIND(L); ++ __ stw(temp(), to(), to_offset * wordSize); ++} ++ ++void InterpreterRuntime::SignatureHandlerGenerator::generate(uint64_t fingerprint) { ++ // generate code to handle arguments ++ iterate(fingerprint); ++ // return result handler ++ __ li(V0, AbstractInterpreter::result_handler(method()->result_type())); ++ // return ++ __ ret(); ++ ++ __ flush(); ++} ++ ++void InterpreterRuntime::SignatureHandlerGenerator::pass_int() { ++ Argument jni_arg(jni_offset()); ++ __ ldw(temp(), from(), Interpreter::local_offset_in_bytes(offset())); ++ __ store_int_argument(temp(), jni_arg); ++} ++ ++void InterpreterRuntime::SignatureHandlerGenerator::pass_object() { ++ Argument jni_arg(jni_offset()); ++ ++ Register Rtmp1 = temp(); ++ ++ // the handle for a receiver will never be null ++ bool do_NULL_check = offset() != 0 || is_static(); ++ __ ldl(Rtmp1, from(), Interpreter::local_offset_in_bytes(offset())); ++ ++ Label L; ++ __ beq(Rtmp1, L); ++ __ add_simm16(Rtmp1, from(), Interpreter::local_offset_in_bytes(offset())); ++ __ BIND(L); ++ ++ __ store_ptr_argument(Rtmp1, jni_arg); ++} ++ ++//the jvm specifies that long type takes 2 stack spaces, so in do_long(), _offset += 2. ++void InterpreterRuntime::SignatureHandlerGenerator::pass_long() { ++ Argument jni_arg(jni_offset()); ++ __ ldl(temp(), from(), Interpreter::local_offset_in_bytes(offset() + 1)); ++ if(jni_arg.is_Register()) { ++ __ move(jni_arg.as_Register(), temp()); ++ } else { ++ __ stl(temp(), jni_arg.as_caller_address()); ++ } ++} ++ ++//not sure ++////#if (defined _LP64) || (defined N32) ++void InterpreterRuntime::SignatureHandlerGenerator::pass_float() { ++ Argument jni_arg(jni_offset()); ++ __ flds(F16, from(), Interpreter::local_offset_in_bytes(offset())); ++ __ store_float_argument(F16, jni_arg); ++} ++ ++ ++//the jvm specifies that double type takes 2 stack spaces, so in do_double(), _offset += 2. ++void InterpreterRuntime::SignatureHandlerGenerator::pass_double() { ++ Argument jni_arg(jni_offset()); ++ __ fldd(F16, from(), Interpreter::local_offset_in_bytes(offset() + 1)); ++ __ store_double_argument(F16, jni_arg); ++} ++////#endif ++ ++ ++Register InterpreterRuntime::SignatureHandlerGenerator::from() { return LVP; } ++Register InterpreterRuntime::SignatureHandlerGenerator::to() { return SP; } ++Register InterpreterRuntime::SignatureHandlerGenerator::temp() { return RT4; } ++ ++// Implementation of SignatureHandlerLibrary ++ ++void SignatureHandlerLibrary::pd_set_handler(address handler) {} ++ ++ ++class SlowSignatureHandler ++ : public NativeSignatureIterator { ++ private: ++ address _from; ++ intptr_t* _to; ++ intptr_t* _reg_args; ++ intptr_t* _fp_identifiers; ++ unsigned int _num_args; ++ ++ virtual void pass_int() ++ { ++ jint from_obj = *(jint *)(_from+Interpreter::local_offset_in_bytes(0)); ++ _from -= Interpreter::stackElementSize; ++ ++ if (_num_args < Argument::n_register_parameters) { ++ *_reg_args++ = from_obj; ++ _num_args++; ++ } else { ++ *_to++ = from_obj; ++ } ++ } ++ ++ virtual void pass_long() ++ { ++ intptr_t from_obj = *(intptr_t*)(_from+Interpreter::local_offset_in_bytes(1)); ++ _from -= 2 * Interpreter::stackElementSize; ++ ++ if (_num_args < Argument::n_register_parameters) { ++ *_reg_args++ = from_obj; ++ _num_args++; ++ } else { ++ *_to++ = from_obj; ++ } ++ } ++ ++ virtual void pass_object() ++ { ++ intptr_t *from_addr = (intptr_t*)(_from + Interpreter::local_offset_in_bytes(0)); ++ _from -= Interpreter::stackElementSize; ++ if (_num_args < Argument::n_register_parameters) { ++ *_reg_args++ = (*from_addr == 0) ? NULL : (intptr_t) from_addr; ++ _num_args++; ++ } else { ++ *_to++ = (*from_addr == 0) ? NULL : (intptr_t) from_addr; ++ } ++ } ++ ++ virtual void pass_float() ++ { ++ jint from_obj = *(jint *)(_from+Interpreter::local_offset_in_bytes(0)); ++ _from -= Interpreter::stackElementSize; ++ ++ if (_num_args < Argument::n_float_register_parameters) { ++ *_reg_args++ = from_obj; ++ *_fp_identifiers |= (0x01 << (_num_args*2)); // mark as float ++ _num_args++; ++ } else { ++ *_to++ = from_obj; ++ } ++ } ++ ++ virtual void pass_double() ++ { ++ intptr_t from_obj = *(intptr_t*)(_from+Interpreter::local_offset_in_bytes(1)); ++ _from -= 2*Interpreter::stackElementSize; ++ ++ if (_num_args < Argument::n_float_register_parameters) { ++ *_reg_args++ = from_obj; ++ *_fp_identifiers |= (0x3 << (_num_args*2)); // mark as double ++ _num_args++; ++ } else { ++ *_to++ = from_obj; ++ } ++ } ++ ++ public: ++ SlowSignatureHandler(methodHandle method, address from, intptr_t* to) ++ : NativeSignatureIterator(method) ++ { ++ _from = from; ++ _to = to; ++ ++ _reg_args = to - Argument::n_register_parameters + jni_offset() - 1; ++ _fp_identifiers = to - 1; ++ *(int*) _fp_identifiers = 0; ++ _num_args = jni_offset(); ++ } ++}; ++ ++ ++IRT_ENTRY(address, ++ InterpreterRuntime::slow_signature_handler(JavaThread* thread, ++ Method* method, ++ intptr_t* from, ++ intptr_t* to)) ++ methodHandle m(thread, (Method*)method); ++ assert(m->is_native(), "sanity check"); ++ ++ // handle arguments ++ SlowSignatureHandler(m, (address)from, to).iterate(UCONST64(-1)); ++ ++ // return result handler ++ return Interpreter::result_handler(m->result_type()); ++IRT_END +diff --git a/hotspot/src/cpu/sw64/vm/interpreterRT_sw64.hpp b/hotspot/src/cpu/sw64/vm/interpreterRT_sw64.hpp +new file mode 100755 +index 0000000000..59e2720840 +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/interpreterRT_sw64.hpp +@@ -0,0 +1,60 @@ ++/* ++ * Copyright (c) 1998, 2010, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_SW64_VM_INTERPRETERRT_SW64_HPP ++#define CPU_SW64_VM_INTERPRETERRT_SW64_HPP ++ ++#include "memory/allocation.hpp" ++ ++// native method calls ++ ++class SignatureHandlerGenerator: public NativeSignatureIterator { ++ private: ++ MacroAssembler* _masm; ++ ++ void move(int from_offset, int to_offset); ++ ++ void box(int from_offset, int to_offset); ++ void pass_int(); ++ void pass_long(); ++ void pass_object(); ++ void pass_float(); ++ void pass_double(); ++ ++ public: ++ // Creation ++ SignatureHandlerGenerator(methodHandle method, CodeBuffer* buffer) : NativeSignatureIterator(method) { ++ _masm = new MacroAssembler(buffer); ++ } ++ ++ // Code generation ++ void generate(uint64_t fingerprint); ++ ++ // Code generation support ++ static Register from(); ++ static Register to(); ++ static Register temp(); ++}; ++ ++#endif // CPU_SW64_VM_INTERPRETERRT_SW64_HPP +diff --git a/hotspot/src/cpu/sw64/vm/interpreter_sw64.cpp b/hotspot/src/cpu/sw64/vm/interpreter_sw64.cpp +new file mode 100755 +index 0000000000..27a744d2e3 +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/interpreter_sw64.cpp +@@ -0,0 +1,265 @@ ++/* ++ * Copyright (c) 2003, 2014, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#include "precompiled.hpp" ++#include "asm/macroAssembler.hpp" ++#include "interpreter/bytecodeHistogram.hpp" ++#include "interpreter/interpreter.hpp" ++#include "interpreter/interpreterGenerator.hpp" ++#include "interpreter/interpreterRuntime.hpp" ++#include "interpreter/templateTable.hpp" ++#include "oops/arrayOop.hpp" ++#include "oops/methodData.hpp" ++#include "oops/method.hpp" ++#include "oops/oop.inline.hpp" ++#include "prims/jvmtiExport.hpp" ++#include "prims/jvmtiThreadState.hpp" ++#include "prims/methodHandles.hpp" ++#include "runtime/arguments.hpp" ++#include "runtime/deoptimization.hpp" ++#include "runtime/frame.inline.hpp" ++#include "runtime/sharedRuntime.hpp" ++#include "runtime/stubRoutines.hpp" ++#include "runtime/synchronizer.hpp" ++#include "runtime/timer.hpp" ++#include "runtime/vframeArray.hpp" ++#include "utilities/debug.hpp" ++#ifdef COMPILER1 ++#include "c1/c1_Runtime1.hpp" ++#endif ++ ++#define __ _masm-> ++ ++#ifdef PRODUCT ++#define BLOCK_COMMENT(str) /* nothing */ ++#else ++#define BLOCK_COMMENT(str) { char line[1024];sprintf(line,"%s:%s:%d",str,__FILE__, __LINE__); __ block_comment(line);} ++#endif ++ ++#define BIND(label) bind(label); BLOCK_COMMENT(#label ":") ++ ++address AbstractInterpreterGenerator::generate_slow_signature_handler() { ++ address entry = __ pc(); ++ ++ // Rmethod: method ++ // LVP: pointer to locals ++ // T3: first stack arg - wordSize ++ __ move(T3, SP); ++ __ pushad(); ++ __ call_VM(noreg, ++ CAST_FROM_FN_PTR(address, ++ InterpreterRuntime::slow_signature_handler), ++ Rmethod, LVP, T3); ++ __ move(S0, V0); ++ __ popad(); ++ __ move(V0, S0); ++ ++ // V0: result handler ++ ++ // Stack layout: ++ // ... ++ ++ // Do FP first so we can use c_rarg3 as temp ++ __ ldl(T3, Address(SP, -1 * wordSize)); // float/double identifiers ++ ++ // A0 is for env. ++ // If the mothed is not static, A1 will be corrected in generate_native_entry. ++ for ( int i= 1; i < Argument::n_register_parameters; i++ ) { ++ Register reg = as_Register(i + A0->encoding()); ++ FloatRegister floatreg = as_FloatRegister(i + F16->encoding()); ++ Label isfloatordouble, isdouble, next; ++ ++ __ set64(AT, 1 << (i*2)); // Float or Double? ++ __ and_reg(AT, T3, AT); ++ __ bne(AT, isfloatordouble); ++ ++ // Do Int register here ++ __ ldl(reg, Address(SP, -(Argument::n_register_parameters + 1 -i) * wordSize)); ++ __ beq(R0, next); ++ ++ __ BIND(isfloatordouble); ++ __ set64(AT, 1 << ((i*2)+1)); // Double? ++ __ and_reg(AT, T3, AT); ++ __ bne(AT, isdouble); ++ ++ // Do Float Here ++ __ flds(floatreg, Address(SP, -(Argument::n_float_register_parameters + 1 -i) * wordSize)); ++ __ beq(R0, next); ++ ++ // Do Double here ++ __ BIND(isdouble); ++ __ fldd(floatreg, Address(SP, -(Argument::n_float_register_parameters + 1 -i) * wordSize)); ++ ++ __ BIND(next); ++ } ++ ++ __ ret(); ++ return entry; ++} ++ ++ ++// ++// Various method entries ++// ++ ++address InterpreterGenerator::generate_math_entry(AbstractInterpreter::MethodKind kind) { ++ ++ // Rmethod: methodOop ++ // V0: scratrch ++ // Rsender: send 's sp ++ ++ if (!InlineIntrinsics) return NULL; // Generate a vanilla entry ++ ++ address entry_point = __ pc(); ++ ++ // These don't need a safepoint check because they aren't virtually ++ // callable. We won't enter these intrinsics from compiled code. ++ // If in the future we added an intrinsic which was virtually callable ++ // we'd have to worry about how to safepoint so that this code is used. ++ ++ // mathematical functions inlined by compiler ++ // (interpreter must provide identical implementation ++ // in order to avoid monotonicity bugs when switching ++ // from interpreter to compiler in the middle of some ++ // computation) ++ // ++ // stack: [ lo(arg) ] <-- sp ++ // [ hi(arg) ] ++ { ++ // Note: For JDK 1.3 StrictMath exists and Math.sin/cos/sqrt are ++ // java methods. Interpreter::method_kind(...) will select ++ // this entry point for the corresponding methods in JDK 1.3. ++ __ fldd(F16, SP, 0 * wordSize); ++ __ fldd(F17, SP, 1 * wordSize); ++ __ stl(RA, SP, (-1) * wordSize); ++ __ stl(FP, SP, (-2) * wordSize); ++ __ move(FP, SP); ++ __ add_simm16(SP, SP, (-2) * wordSize); ++ ++ // [ fp ] <-- sp ++ // [ ra ] ++ // [ lo ] <-- fp ++ // [ hi ] ++ switch (kind) { ++ case Interpreter::java_lang_math_sin : ++ __ trigfunc('s'); ++ break; ++ case Interpreter::java_lang_math_cos : ++ __ trigfunc('c'); ++ break; ++ case Interpreter::java_lang_math_tan : ++ __ trigfunc('t'); ++ break; ++ case Interpreter::java_lang_math_sqrt: ++ __ sqrt_d(F0, F16); ++ break; ++ case Interpreter::java_lang_math_abs: ++ __ fabs(F0, F16); ++ break; ++ case Interpreter::java_lang_math_log: ++ // Store to stack to convert 80bit precision back to 64bits ++ break; ++ case Interpreter::java_lang_math_log10: ++ // Store to stack to convert 80bit precision back to 64bits ++ break; ++ case Interpreter::java_lang_math_pow: ++ break; ++ case Interpreter::java_lang_math_exp: ++ break; ++ ++ default : ++ ShouldNotReachHere(); ++ } ++ ++ __ ldl(RA, FP, (-1) * wordSize); ++ __ move(SP, Rsender); ++ __ ldl(FP, FP, (-2) * wordSize); ++ __ ret(); ++ } ++ return entry_point; ++} ++ ++ ++// Abstract method entry ++// Attempt to execute abstract method. Throw exception ++address InterpreterGenerator::generate_abstract_entry(void) { ++ ++ // Rmethod: methodOop ++ // V0: receiver (unused) ++ // Rsender : sender 's sp ++ address entry_point = __ pc(); ++ ++ // abstract method entry ++ // throw exception ++ // adjust stack to what a normal return would do ++ __ empty_expression_stack(); ++ __ restore_bcp(); ++ __ restore_locals(); ++ __ call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::throw_AbstractMethodError)); ++ // the call_VM checks for exception, so we should never return here. ++ __ should_not_reach_here(); ++ ++ return entry_point; ++} ++ ++ ++// Empty method, generate a very fast return. ++ ++address InterpreterGenerator::generate_empty_entry(void) { ++ ++ // Rmethod: methodOop ++ // V0: receiver (unused) ++ if (!UseFastEmptyMethods) return NULL; ++ ++ address entry_point = __ pc(); ++ ++ Label slow_path; ++ __ li(RT0, SafepointSynchronize::address_of_state()); ++ __ ldw(AT, RT0, 0); ++ __ move(RT0, (SafepointSynchronize::_not_synchronized)); ++ __ bne(AT, RT0, slow_path); ++ __ move(SP, Rsender); ++ __ ret(); ++ __ BIND(slow_path); ++ (void) generate_normal_entry(false); ++ ++ return entry_point; ++ ++} ++ ++void Deoptimization::unwind_callee_save_values(frame* f, vframeArray* vframe_array) { ++ ++ // This code is sort of the equivalent of C2IAdapter::setup_stack_frame back in ++ // the days we had adapter frames. When we deoptimize a situation where a ++ // compiled caller calls a compiled caller will have registers it expects ++ // to survive the call to the callee. If we deoptimize the callee the only ++ // way we can restore these registers is to have the oldest interpreter ++ // frame that we create restore these values. That is what this routine ++ // will accomplish. ++ ++ // At the moment we have modified c2 to not have any callee save registers ++ // so this problem does not exist and this routine is just a place holder. ++ ++ assert(f->is_interpreted_frame(), "must be interpreted"); ++} +diff --git a/hotspot/src/cpu/sw64/vm/interpreter_sw64.hpp b/hotspot/src/cpu/sw64/vm/interpreter_sw64.hpp +new file mode 100755 +index 0000000000..20d3b6ee7b +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/interpreter_sw64.hpp +@@ -0,0 +1,50 @@ ++/* ++ * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_SW64_VM_INTERPRETER_SW64_HPP ++#define CPU_SW64_VM_INTERPRETER_SW64_HPP ++ ++ public: ++ ++ // Sentinel placed in the code for interpreter returns so ++ // that i2c adapters and osr code can recognize an interpreter ++ // return address and convert the return to a specialized ++ // block of code to handle compiedl return values and cleaning ++ // the fpu stack. ++ static const int return_sentinel; ++ ++ static Address::ScaleFactor stackElementScale() { ++ return Address::times_8; ++ } ++ ++ // Offset from sp (which points to the last stack element) ++ static int expr_offset_in_bytes(int i) { return stackElementSize * i; } ++ // Size of interpreter code. Increase if too small. Interpreter will ++ // fail with a guarantee ("not enough space for interpreter generation"); ++ // if too small. ++ // Run with +PrintInterpreterSize to get the VM to print out the size. ++ // Max size with JVMTI and TaggedStackInterpreter ++ const static int InterpreterCodeSize = 168 * 1024; ++ ++#endif // CPU_SW64_VM_INTERPRETER_SW64_HPP +diff --git a/hotspot/src/cpu/sw64/vm/javaFrameAnchor_sw64.hpp b/hotspot/src/cpu/sw64/vm/javaFrameAnchor_sw64.hpp +new file mode 100755 +index 0000000000..c02722b879 +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/javaFrameAnchor_sw64.hpp +@@ -0,0 +1,86 @@ ++/* ++ * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_SW64_VM_JAVAFRAMEANCHOR_SW64_HPP ++#define CPU_SW64_VM_JAVAFRAMEANCHOR_SW64_HPP ++ ++private: ++ ++ // FP value associated with _last_Java_sp: ++ intptr_t* volatile _last_Java_fp; // pointer is volatile not what it points to ++ ++public: ++ // Each arch must define reset, save, restore ++ // These are used by objects that only care about: ++ // 1 - initializing a new state (thread creation, javaCalls) ++ // 2 - saving a current state (javaCalls) ++ // 3 - restoring an old state (javaCalls) ++ ++ void clear(void) { ++ // clearing _last_Java_sp must be first ++ _last_Java_sp = NULL; ++ // fence? ++ _last_Java_fp = NULL; ++ _last_Java_pc = NULL; ++ } ++ ++ void copy(JavaFrameAnchor* src) { ++ // In order to make sure the transition state is valid for "this" ++ // We must clear _last_Java_sp before copying the rest of the new data ++ // ++ // Hack Alert: Temporary bugfix for 4717480/4721647 ++ // To act like previous version (pd_cache_state) don't NULL _last_Java_sp ++ // unless the value is changing ++ // ++ if (_last_Java_sp != src->_last_Java_sp) ++ _last_Java_sp = NULL; ++ ++ _last_Java_fp = src->_last_Java_fp; ++ _last_Java_pc = src->_last_Java_pc; ++ // Must be last so profiler will always see valid frame if has_last_frame() is true ++ _last_Java_sp = src->_last_Java_sp; ++ } ++ ++ // Always walkable ++ bool walkable(void) { return true; } ++ // Never any thing to do since we are always walkable and can find address of return addresses ++ void make_walkable(JavaThread* thread) { } ++ ++ intptr_t* last_Java_sp(void) const { return _last_Java_sp; } ++ ++ address last_Java_pc(void) { return _last_Java_pc; } ++ ++private: ++ ++ static ByteSize last_Java_fp_offset() { return byte_offset_of(JavaFrameAnchor, _last_Java_fp); } ++ ++public: ++ ++ void set_last_Java_sp(intptr_t* sp) { _last_Java_sp = sp; } ++ ++ intptr_t* last_Java_fp(void) { return _last_Java_fp; } ++ // Assert (last_Java_sp == NULL || fp == NULL) ++ void set_last_Java_fp(intptr_t* fp) { _last_Java_fp = fp; } ++ ++#endif // CPU_SW64_VM_JAVAFRAMEANCHOR_SW64_HPP +diff --git a/hotspot/src/cpu/sw64/vm/jniFastGetField_sw64.cpp b/hotspot/src/cpu/sw64/vm/jniFastGetField_sw64.cpp +new file mode 100755 +index 0000000000..b55f059c22 +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/jniFastGetField_sw64.cpp +@@ -0,0 +1,220 @@ ++/* ++ * Copyright (c) 2004, 2010, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#include "precompiled.hpp" ++#include "asm/macroAssembler.hpp" ++#include "memory/resourceArea.hpp" ++#include "prims/jniFastGetField.hpp" ++#include "prims/jvm_misc.hpp" ++#include "runtime/safepoint.hpp" ++ ++#define __ masm-> ++ ++#ifdef PRODUCT ++#define BLOCK_COMMENT(str) /* nothing */ ++#else ++#define BLOCK_COMMENT(str) { char line[1024];sprintf(line,"%s:%s:%d",str,__FILE__, __LINE__); __ block_comment(line);} ++#endif ++ ++#define BIND(label) bind(label); BLOCK_COMMENT(#label ":") ++ ++#define BUFFER_SIZE 30*wordSize ++ ++// Instead of issuing lfence for LoadLoad barrier, we create data dependency ++// between loads, which is more efficient than lfence. ++ ++address JNI_FastGetField::generate_fast_get_int_field0(BasicType type) { ++ const char *name = NULL; ++ switch (type) { ++ case T_BOOLEAN: name = "jni_fast_GetBooleanField"; break; ++ case T_BYTE: name = "jni_fast_GetByteField"; break; ++ case T_CHAR: name = "jni_fast_GetCharField"; break; ++ case T_SHORT: name = "jni_fast_GetShortField"; break; ++ case T_INT: name = "jni_fast_GetIntField"; break; ++ case T_LONG: name = "jni_fast_GetLongField"; break; ++ default: ShouldNotReachHere(); ++ } ++ ResourceMark rm; ++ BufferBlob* blob = BufferBlob::create(name, BUFFER_SIZE); ++ CodeBuffer cbuf(blob); ++ MacroAssembler* masm = new MacroAssembler(&cbuf); ++ address fast_entry = __ pc(); ++ ++ Label slow; ++ ++ // return pc RA ++ // jni env A0 ++ // obj A1 ++ // jfieldID A2 ++ ++ address counter_addr = SafepointSynchronize::safepoint_counter_addr(); ++ // Parameters(A0~A3) should not be modified, since they will be used in slow path ++ ++ __ set64(AT, (long)counter_addr); ++ __ ldw(T1, AT, 0); ++ ++ __ and_imm8(AT, T1, 1); ++ __ bne(AT, slow); ++ ++ __ move(T0, A1); ++ __ clear_jweak_tag(T0); ++ ++ __ ldl(T0, T0, 0); // unbox, *obj ++ __ move(T2, A2); ++ __ srll(T2, T2, 2); // offset ++ __ addl(T0, T0, T2); ++ ++ assert(count < LIST_CAPACITY, "LIST_CAPACITY too small"); ++ speculative_load_pclist[count] = __ pc(); ++ switch (type) { ++ case T_BOOLEAN: __ ldbu(V0, T0, 0); break; ++ case T_BYTE: __ ldb_signed(V0, T0, 0); break; ++ case T_CHAR: __ ldhu(V0, T0, 0); break; ++ case T_SHORT: __ ldh_signed(V0, T0, 0); break; ++ case T_INT: __ ldw(V0, T0, 0); break; ++ case T_LONG: __ ldl(V0, T0, 0); break; ++ default: ShouldNotReachHere(); ++ } ++ ++ __ set64(AT, (long)counter_addr); ++ __ ldw(AT, AT, 0); ++ __ bne(T1, AT, slow); ++ ++ __ ret(); ++ ++ slowcase_entry_pclist[count++] = __ pc(); ++ __ BIND (slow); ++ address slow_case_addr = NULL; ++ switch (type) { ++ case T_BOOLEAN: slow_case_addr = jni_GetBooleanField_addr(); break; ++ case T_BYTE: slow_case_addr = jni_GetByteField_addr(); break; ++ case T_CHAR: slow_case_addr = jni_GetCharField_addr(); break; ++ case T_SHORT: slow_case_addr = jni_GetShortField_addr(); break; ++ case T_INT: slow_case_addr = jni_GetIntField_addr(); break; ++ case T_LONG: slow_case_addr = jni_GetLongField_addr(); ++ } ++ __ jmp(slow_case_addr); ++ ++ __ flush (); ++ ++ return fast_entry; ++} ++ ++address JNI_FastGetField::generate_fast_get_boolean_field() { ++ return generate_fast_get_int_field0(T_BOOLEAN); ++} ++ ++address JNI_FastGetField::generate_fast_get_byte_field() { ++ return generate_fast_get_int_field0(T_BYTE); ++} ++ ++address JNI_FastGetField::generate_fast_get_char_field() { ++ return generate_fast_get_int_field0(T_CHAR); ++} ++ ++address JNI_FastGetField::generate_fast_get_short_field() { ++ return generate_fast_get_int_field0(T_SHORT); ++} ++ ++address JNI_FastGetField::generate_fast_get_int_field() { ++ return generate_fast_get_int_field0(T_INT); ++} ++ ++address JNI_FastGetField::generate_fast_get_long_field() { ++ return generate_fast_get_int_field0(T_LONG); ++} ++ ++address JNI_FastGetField::generate_fast_get_float_field0(BasicType type) { ++ const char *name =NULL; ++ switch (type) { ++ case T_FLOAT: name = "jni_fast_GetFloatField"; break; ++ case T_DOUBLE: name = "jni_fast_GetDoubleField"; break; ++ default: ShouldNotReachHere(); ++ } ++ ResourceMark rm; ++ BufferBlob* blob = BufferBlob::create(name, BUFFER_SIZE); ++ CodeBuffer cbuf(blob); ++ MacroAssembler* masm = new MacroAssembler(&cbuf); ++ address fast_entry = __ pc(); ++ ++ Label slow; ++ ++ // return pc RA ++ // jni env A0 ++ // obj A1 ++ // jfieldID A2 ++ ++ address counter_addr = SafepointSynchronize::safepoint_counter_addr(); ++ __ set64(AT, (intptr_t)counter_addr); ++ __ ldw(T1, AT, 0); ++ __ and_imm8(AT, T1, 1); ++ __ bne(AT, slow); ++ ++ __ clear_jweak_tag(A1); ++ ++ __ ldl(A1, A1, 0); // unbox, *obj ++ __ srll(A2, A2, 2); // offset ++ __ addl(A1, A1, A2); ++ ++ assert(count < LIST_CAPACITY, "LIST_CAPACITY too small"); ++ speculative_load_pclist[count] = __ pc(); ++ switch (type) { ++ case T_FLOAT: ++ __ flds(F0, A1, 0); ++ break; ++ case T_DOUBLE: ++ __ fldd(F0, A1, 0); ++ break; ++ default: ShouldNotReachHere(); ++ } ++ ++ __ set64(AT, (intptr_t)counter_addr); ++ __ ldw(AT, AT, 0); ++ __ bne(T1, AT, slow); ++ ++ __ ret(); ++ ++ ++ slowcase_entry_pclist[count++] = __ pc(); ++ __ BIND (slow); ++ address slow_case_addr = NULL; ++ switch (type) { ++ case T_FLOAT: slow_case_addr = jni_GetFloatField_addr(); break; ++ case T_DOUBLE: slow_case_addr = jni_GetDoubleField_addr(); break; ++ default: ShouldNotReachHere(); ++ } ++ __ jmp(slow_case_addr); ++ ++ __ flush (); ++ ++ return fast_entry; ++} ++ ++address JNI_FastGetField::generate_fast_get_float_field() { ++ return generate_fast_get_float_field0(T_FLOAT); ++} ++ ++address JNI_FastGetField::generate_fast_get_double_field() { ++ return generate_fast_get_float_field0(T_DOUBLE); ++} +diff --git a/hotspot/src/cpu/sw64/vm/jniTypes_sw64.hpp b/hotspot/src/cpu/sw64/vm/jniTypes_sw64.hpp +new file mode 100755 +index 0000000000..9f556c920b +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/jniTypes_sw64.hpp +@@ -0,0 +1,143 @@ ++/* ++ * Copyright (c) 1998, 2010, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_SW64_VM_JNITYPES_SW64_HPP ++#define CPU_SW64_VM_JNITYPES_SW64_HPP ++ ++#include "memory/allocation.hpp" ++#include "oops/oop.hpp" ++#include "prims/jni.h" ++ ++// This file holds platform-dependent routines used to write primitive jni ++// types to the array of arguments passed into JavaCalls::call ++ ++class JNITypes : AllStatic { ++ // These functions write a java primitive type (in native format) ++ // to a java stack slot array to be passed as an argument to JavaCalls:calls. ++ // I.e., they are functionally 'push' operations if they have a 'pos' ++ // formal parameter. Note that jlong's and jdouble's are written ++ // _in reverse_ of the order in which they appear in the interpreter ++ // stack. This is because call stubs (see stubGenerator_sparc.cpp) ++ // reverse the argument list constructed by JavaCallArguments (see ++ // javaCalls.hpp). ++ ++private: ++ ++ // 32bit Helper routines. ++ static inline void put_int2r(jint *from, intptr_t *to) { *(jint *)(to++) = from[1]; ++ *(jint *)(to ) = from[0]; } ++ static inline void put_int2r(jint *from, intptr_t *to, int& pos) { put_int2r(from, to + pos); pos += 2; } ++ ++public: ++ // In SW64, the sizeof intptr_t is 8 bytes, and each unit in JavaCallArguments::_value_buffer[] is 8 bytes. ++ // If we only write the low 4 bytes with (jint *), the high 4-bits will be left with uncertain values. ++ // Then, in JavaCallArguments::parameters(), the whole 8 bytes of a T_INT parameter is loaded. ++ // This error occurs in ReflectInvoke.java ++ // The parameter of DD(int) should be 4 instead of 0x550000004. ++ // ++ // See: [runtime/javaCalls.hpp] ++ ++ static inline void put_int(jint from, intptr_t *to) { *(intptr_t *)(to + 0 ) = from; } ++ static inline void put_int(jint from, intptr_t *to, int& pos) { *(intptr_t *)(to + pos++) = from; } ++ static inline void put_int(jint *from, intptr_t *to, int& pos) { *(intptr_t *)(to + pos++) = *from; } ++ ++ // Longs are stored in native format in one JavaCallArgument slot at ++ // *(to). ++ // In theory, *(to + 1) is an empty slot. But, for several Java2D testing programs (TestBorderLayout, SwingTest), ++ // *(to + 1) must contains a copy of the long value. Otherwise it will corrupts. ++ static inline void put_long(jlong from, intptr_t *to) { ++ *(jlong*) (to + 1) = from; ++ *(jlong*) (to) = from; ++ } ++ ++ // A long parameter occupies two slot. ++ // It must fit the layout rule in methodHandle. ++ // ++ // See: [runtime/reflection.cpp] Reflection::invoke() ++ // assert(java_args.size_of_parameters() == method->size_of_parameters(), "just checking"); ++ ++ static inline void put_long(jlong from, intptr_t *to, int& pos) { ++ *(jlong*) (to + 1 + pos) = from; ++ *(jlong*) (to + pos) = from; ++ pos += 2; ++ } ++ ++ static inline void put_long(jlong *from, intptr_t *to, int& pos) { ++ *(jlong*) (to + 1 + pos) = *from; ++ *(jlong*) (to + pos) = *from; ++ pos += 2; ++ } ++ ++ // Oops are stored in native format in one JavaCallArgument slot at *to. ++ static inline void put_obj(oop from, intptr_t *to) { *(oop *)(to + 0 ) = from; } ++ static inline void put_obj(oop from, intptr_t *to, int& pos) { *(oop *)(to + pos++) = from; } ++ static inline void put_obj(oop *from, intptr_t *to, int& pos) { *(oop *)(to + pos++) = *from; } ++ ++ // Floats are stored in native format in one JavaCallArgument slot at *to. ++ static inline void put_float(jfloat from, intptr_t *to) { *(jfloat *)(to + 0 ) = from; } ++ static inline void put_float(jfloat from, intptr_t *to, int& pos) { *(jfloat *)(to + pos++) = from; } ++ static inline void put_float(jfloat *from, intptr_t *to, int& pos) { *(jfloat *)(to + pos++) = *from; } ++ ++#undef _JNI_SLOT_OFFSET ++#define _JNI_SLOT_OFFSET 0 ++ ++ // Longs are stored in native format in one JavaCallArgument slot at ++ // *(to). ++ // In theory, *(to + 1) is an empty slot. But, for several Java2D testing programs (TestBorderLayout, SwingTest), ++ // *(to + 1) must contains a copy of the long value. Otherwise it will corrupts. ++ static inline void put_double(jdouble from, intptr_t *to) { ++ *(jdouble*) (to + 1) = from; ++ *(jdouble*) (to) = from; ++ } ++ ++ // A long parameter occupies two slot. ++ // It must fit the layout rule in methodHandle. ++ // ++ // See: [runtime/reflection.cpp] Reflection::invoke() ++ // assert(java_args.size_of_parameters() == method->size_of_parameters(), "just checking"); ++ ++ static inline void put_double(jdouble from, intptr_t *to, int& pos) { ++ *(jdouble*) (to + 1 + pos) = from; ++ *(jdouble*) (to + pos) = from; ++ pos += 2; ++ } ++ ++ static inline void put_double(jdouble *from, intptr_t *to, int& pos) { ++ *(jdouble*) (to + 1 + pos) = *from; ++ *(jdouble*) (to + pos) = *from; ++ pos += 2; ++ } ++ ++ ++ // The get_xxx routines, on the other hand, actually _do_ fetch ++ // java primitive types from the interpreter stack. ++ static inline jint get_int (intptr_t *from) { return *(jint *) from; } ++ static inline jlong get_long (intptr_t *from) { return *(jlong *) (from + _JNI_SLOT_OFFSET); } ++ static inline oop get_obj (intptr_t *from) { return *(oop *) from; } ++ static inline jfloat get_float (intptr_t *from) { return *(jfloat *) from; } ++ static inline jdouble get_double(intptr_t *from) { return *(jdouble *)(from + _JNI_SLOT_OFFSET); } ++#undef _JNI_SLOT_OFFSET ++}; ++ ++#endif // CPU_SW64_VM_JNITYPES_SW64_HPP +diff --git a/hotspot/src/cpu/sw64/vm/jni_sw64.h b/hotspot/src/cpu/sw64/vm/jni_sw64.h +new file mode 100755 +index 0000000000..fffe74870c +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/jni_sw64.h +@@ -0,0 +1,51 @@ ++/* ++ * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. Oracle designates this ++ * particular file as subject to the "Classpath" exception as provided ++ * by Oracle in the LICENSE file that accompanied this code. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ */ ++ ++#ifndef _JAVASOFT_JNI_MD_H_ ++#define _JAVASOFT_JNI_MD_H_ ++ ++// Note: please do not change these without also changing jni_md.h in the JDK ++// repository ++#ifndef __has_attribute ++ #define __has_attribute(x) 0 ++#endif ++ ++#if (defined(__GNUC__) && ((__GNUC__ > 4) || (__GNUC__ == 4) && (__GNUC_MINOR__ > 2))) || __has_attribute(visibility) ++ #define JNIEXPORT __attribute__((visibility("default"))) ++ #define JNIIMPORT __attribute__((visibility("default"))) ++#else ++ #define JNIEXPORT ++ #define JNIIMPORT ++#endif ++ ++#define JNICALL ++ ++typedef int jint; ++ ++ typedef long jlong; ++ ++typedef signed char jbyte; ++ ++#endif +diff --git a/hotspot/src/cpu/sw64/vm/macroAssembler_sw64.cpp b/hotspot/src/cpu/sw64/vm/macroAssembler_sw64.cpp +new file mode 100755 +index 0000000000..d31df20fae +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/macroAssembler_sw64.cpp +@@ -0,0 +1,3861 @@ ++/* ++ * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#include "precompiled.hpp" ++#include "asm/assembler.hpp" ++#include "asm/assembler.inline.hpp" ++#include "asm/macroAssembler.inline.hpp" ++#include "compiler/disassembler.hpp" ++#include "gc_interface/collectedHeap.inline.hpp" ++#include "interpreter/interpreter.hpp" ++#include "memory/cardTableModRefBS.hpp" ++#include "memory/resourceArea.hpp" ++#include "memory/universe.hpp" ++#include "prims/methodHandles.hpp" ++#include "runtime/biasedLocking.hpp" ++#include "runtime/interfaceSupport.hpp" ++#include "runtime/objectMonitor.hpp" ++#include "runtime/os.hpp" ++#include "runtime/sharedRuntime.hpp" ++#include "runtime/stubRoutines.hpp" ++#include "utilities/macros.hpp" ++#if INCLUDE_ALL_GCS ++#include "gc_implementation/g1/g1CollectedHeap.inline.hpp" ++#include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp" ++#include "gc_implementation/g1/heapRegion.hpp" ++#endif // INCLUDE_ALL_GCS ++ ++#ifdef PRODUCT ++#define BLOCK_COMMENT(str) /* nothing */ ++#define STOP(error) stop(error) ++#else ++#define BLOCK_COMMENT(str) { char line[1024]; sprintf(line,"%s:%s:%d",str,__FILE__, __LINE__); block_comment(line); } ++#define STOP(error) block_comment(error); stop(error) ++#endif ++ ++#define BIND(label) bind(label); BLOCK_COMMENT(#label ":") ++ ++// Implementation of MacroAssembler ++ ++intptr_t MacroAssembler::i[32] = {0}; ++float MacroAssembler::f[32] = {0.0}; ++ ++void MacroAssembler::print(outputStream *s) { ++ unsigned int k; ++ for(k=0; kprint_cr("i%d = 0x%.16lx", k, i[k]); ++ } ++ s->cr(); ++ ++ for(k=0; kprint_cr("f%d = %f", k, f[k]); ++ } ++ s->cr(); ++} ++ ++int MacroAssembler::i_offset(unsigned int k) { return (intptr_t)&((MacroAssembler*)0)->i[k]; } ++int MacroAssembler::f_offset(unsigned int k) { return (intptr_t)&((MacroAssembler*)0)->f[k]; } ++ ++void MacroAssembler::save_registers(MacroAssembler *masm) { ++#define __ masm-> ++ for(int k=0; k<32; k++) { ++ __ stw (as_Register(k), A0, i_offset(k)); ++ } ++ ++ for(int k=0; k<32; k++) { ++ __ fsts(as_FloatRegister(k), A0, f_offset(k)); ++ } ++#undef __ ++} ++ ++void MacroAssembler::restore_registers(MacroAssembler *masm) { ++#define __ masm-> ++ for(int k=0; k<32; k++) { ++ __ ldw (as_Register(k), A0, i_offset(k)); ++ } ++ ++ for(int k=0; k<32; k++) { ++ __ flds (as_FloatRegister(k), A0, f_offset(k)); ++ } ++#undef __ ++} ++ ++ ++void MacroAssembler::pd_patch_instruction(address branch, address target) { ++ jint& stub_inst = *(jint*) branch; ++ stub_inst = patched_branch(target - branch, stub_inst, 0); ++} ++ ++static inline address first_cache_address() { ++ return CodeCache::low_bound() + sizeof(HeapBlock::Header); ++} ++ ++static inline address last_cache_address() { ++ return CodeCache::high_bound() - Assembler::InstructionSize; ++} ++ ++// in the code cache (because code can be relocated)? ++bool MacroAssembler::reachable_from_cache(address target) { ++ return false; ++} ++ ++void MacroAssembler::general_jump(address target) { ++ if (reachable_from_cache(target)) { ++ beq(R0, offset(target)); ++ } else { ++ set64(T12, (long)target); ++ jmp(T12); ++ } ++} ++ ++int MacroAssembler::insts_for_general_jump(address target) { ++ if (reachable_from_cache(target)) { ++ return 1; //ZHJ return 2; ++ } else { ++ return insts_for_set64((jlong)target) + 1; //ZHJ return insts_for_set64((jlong)target) + 2; ++ } ++} ++ ++void MacroAssembler::patchable_jump(address target) { ++ if (reachable_from_cache(target)) { ++ nop(); ++ nop(); ++ nop(); ++ nop(); ++ beq(R0, offset(target)); ++ } else { ++ if (SafePatch) { ++ if(offset() % 8 == 0) { ++ nop(); ++ br(T12, 2); ++ emit_int64((long)target); ++ ldl(T12, T12, 0); ++ }else { ++ br(T12, 2); ++ emit_int64((long)target); ++ ldl(T12, T12, 0); ++ nop(); ++ } ++ } else { ++ patchable_set48(T12, (long)target); ++ } ++ jmp(T12); ++ } ++} ++ ++int MacroAssembler::insts_for_patchable_jump(address target) { ++ //ZHJ return 6; ++ return 5; ++} ++ ++void MacroAssembler::general_call(address target) { ++ if (reachable_from_cache(target)) { ++ bsr(RA, (int)(long)target); ++ } else { ++ set64(T12, (long)target); ++ call(T12); ++ } ++} ++ ++int MacroAssembler::insts_for_general_call(address target) { ++ Unimplemented(); ++ if (reachable_from_cache(target)) { ++ return 1; //ZHJ return 2; ++ } else { ++ return insts_for_set64((jlong)target) + 1; ++ } ++} ++ ++void MacroAssembler::patchable_call(address target) { ++ if (reachable_from_cache(target)) { ++ nop(); ++ nop(); ++ nop(); ++ nop(); ++ bsr(RA, (int)(long)target); ++ } else { ++ if (SafePatch) { ++ if(offset() % 8 == 0) { ++ nop(); ++ br(T12, 2); ++ emit_int64((long)target); ++ ldl(T12, T12, 0); ++ }else { ++ br(T12, 2); ++ emit_int64((long)target); ++ ldl(T12, T12, 0); ++ nop(); ++ } ++ } else { ++ patchable_set48(T12, (long)target); ++ } ++ call(T12); ++ } ++} ++ ++void MacroAssembler::patchable_call_setfpec1(address target) { ++ if (reachable_from_cache(target)) { ++ nop(); ++ nop(); ++ nop(); ++ nop(); ++ bsr(RA, (int)(long)target); ++ } else { ++ if (SafePatch) { ++ if(offset() % 8 == 0) { ++ nop(); ++ br(T12, 2); ++ emit_int64((long)target); ++ ldl(T12, T12, 0); ++ }else { ++ br(T12, 2); ++ emit_int64((long)target); ++ ldl(T12, T12, 0); ++ nop(); ++ } ++ } else { ++ li48(T12, (long)target); ++ } ++ Assembler::call(RA, T12, 0); ++ if (Usesetfpec1) { ++ setfpec1(); ++ } else { ++ nop(); ++ } ++ } ++} ++ ++int MacroAssembler::insts_for_patchable_call(address target) { ++ if (SafePatch) { ++ return 6; ++ } else { ++ return 5; ++ } ++} ++ ++void MacroAssembler::beq_long(Register rs, Register rt, Label& L) { ++ Label not_taken; ++ ++ bne(rs, rt, not_taken); ++ ++ jmp_far(L); ++ ++ BIND(not_taken); ++} ++ ++void MacroAssembler::bne_long(Register rs, Register rt, Label& L) { ++ Label not_taken; ++ ++ beq(rs, rt, not_taken); ++ ++ jmp_far(L); ++ ++ BIND(not_taken); ++} ++ ++void MacroAssembler::bc1t_long(Label& L) { ++ Label not_taken; ++ ++ fbeq(FcmpRES, not_taken); ++ ++ jmp_far(L); ++ ++ BIND(not_taken); ++} ++ ++void MacroAssembler::bc1f_long(Label& L) { ++ Label not_taken; ++ ++ fbne(FcmpRES, not_taken); ++ ++ jmp_far(L); ++ ++ BIND(not_taken); ++} ++ ++void MacroAssembler::b_far(Label& L) { ++ Assembler::beq(R0, L); ++} ++ ++void MacroAssembler::b_far(address entry) { ++ Assembler::beq(R0, offset(entry)); ++} ++ ++void MacroAssembler::ld_ptr(Register rt, Register offset, Register base) { ++ addu_long(AT, base, offset); ++ ld_ptr(rt, 0, AT); ++} ++ ++void MacroAssembler::st_ptr(Register rt, Register offset, Register base) { ++ addu_long(AT, base, offset); ++ st_ptr(rt, 0, AT); ++} ++ ++void MacroAssembler::ld_long(Register rt, Register offset, Register base) { ++ addu_long(AT, base, offset); ++ ld_long(rt, 0, AT); ++} ++ ++void MacroAssembler::st_long(Register rt, Register offset, Register base) { ++ addu_long(AT, base, offset); ++ st_long(rt, 0, AT); ++} ++ ++Address MacroAssembler::as_Address(AddressLiteral adr) { ++ return Address(adr.target(), adr.rspec()); ++} ++ ++Address MacroAssembler::as_Address(ArrayAddress adr) { ++ return Address::make_array(adr); ++} ++ ++// tmp_reg1 and tmp_reg2 should be saved outside of atomic_inc32 (caller saved). ++void MacroAssembler::atomic_inc32(address counter_addr, int inc, Register tmp_reg1, Register tmp_reg2) { ++ Label again; ++ if (UseSW8A) { ++ li(tmp_reg1, counter_addr); ++ BIND(again); ++ lldw(tmp_reg2, tmp_reg1, 0); ++ add_simm16(tmp_reg2, tmp_reg2, inc); ++ move(AT, tmp_reg2); ++ lstw(AT, tmp_reg1, 0); ++ beq(AT, again); ++ } else { ++ SizedScope sc(this, 60); ++ li(tmp_reg1, counter_addr); ++ BIND(again); ++ lldw(tmp_reg2, tmp_reg1, 0); ++ ldi(GP, R0, 1); ++ wr_f(GP); ++ add_simm16(tmp_reg2, tmp_reg2, inc); ++ move(AT, tmp_reg2); ++ align(8); // must align ++ lstw(AT, tmp_reg1, 0); ++ rd_f(AT); ++ beq(AT, again); ++ } ++} ++ ++int MacroAssembler::biased_locking_enter(Register lock_reg, ++ Register obj_reg, ++ Register swap_reg, ++ Register tmp_reg, ++ bool swap_reg_contains_mark, ++ Label& done, ++ Label* slow_case, ++ BiasedLockingCounters* counters) { ++ assert(UseBiasedLocking, "why call this otherwise?"); ++ bool need_tmp_reg = false; ++ if (tmp_reg == noreg) { ++ need_tmp_reg = true; ++ tmp_reg = T12; ++ } ++ assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg, AT); ++ assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout"); ++ Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes()); ++ Address saved_mark_addr(lock_reg, 0); ++ ++ // Biased locking ++ // See whether the lock is currently biased toward our thread and ++ // whether the epoch is still valid ++ // Note that the runtime guarantees sufficient alignment of JavaThread ++ // pointers to allow age to be placed into low bits ++ // First check to see whether biasing is even enabled for this object ++ Label cas_label; ++ int null_check_offset = -1; ++ if (!swap_reg_contains_mark) { ++ null_check_offset = offset(); ++ ld_ptr(swap_reg, mark_addr); ++ } ++ ++ if (need_tmp_reg) { ++ push(tmp_reg); ++ } ++ move(tmp_reg, swap_reg); ++ and_imm8(tmp_reg, tmp_reg, markOopDesc::biased_lock_mask_in_place); ++ add_simm16(AT, R0, markOopDesc::biased_lock_pattern); ++ subl(AT, AT, tmp_reg); ++ if (need_tmp_reg) { ++ pop(tmp_reg); ++ } ++ ++ bne(AT, cas_label); ++ ++ st_ptr(swap_reg, saved_mark_addr); ++ if (need_tmp_reg) { ++ push(tmp_reg); ++ } ++ if (swap_reg_contains_mark) { ++ null_check_offset = offset(); ++ } ++ load_prototype_header(tmp_reg, obj_reg); ++ xor_ins(tmp_reg, tmp_reg, swap_reg); ++ get_thread(swap_reg); ++ xor_ins(swap_reg, swap_reg, tmp_reg); ++ ++ move(AT, ~((int) markOopDesc::age_mask_in_place)); ++ and_reg(swap_reg, swap_reg, AT); ++ ++ if (PrintBiasedLockingStatistics) { ++ Label L; ++ bne(swap_reg, L); ++ push(tmp_reg); ++ push(A0); ++ atomic_inc32((address)BiasedLocking::biased_lock_entry_count_addr(), 1, A0, tmp_reg); ++ pop(A0); ++ pop(tmp_reg); ++ BIND(L); ++ } ++ if (need_tmp_reg) { ++ pop(tmp_reg); ++ } ++ beq(swap_reg, done); ++ Label try_revoke_bias; ++ Label try_rebias; ++ ++ // At this point we know that the header has the bias pattern and ++ // that we are not the bias owner in the current epoch. We need to ++ // figure out more details about the state of the header in order to ++ // know what operations can be legally performed on the object's ++ // header. ++ ++ // If the low three bits in the xor result aren't clear, that means ++ // the prototype header is no longer biased and we have to revoke ++ // the bias on this object. ++ ++ move(AT, markOopDesc::biased_lock_mask_in_place); ++ and_reg(AT, swap_reg, AT); ++ bne(AT, try_revoke_bias); ++ // Biasing is still enabled for this data type. See whether the ++ // epoch of the current bias is still valid, meaning that the epoch ++ // bits of the mark word are equal to the epoch bits of the ++ // prototype header. (Note that the prototype header's epoch bits ++ // only change at a safepoint.) If not, attempt to rebias the object ++ // toward the current thread. Note that we must be absolutely sure ++ // that the current epoch is invalid in order to do this because ++ // otherwise the manipulations it performs on the mark word are ++ // illegal. ++ ++ move(AT, markOopDesc::epoch_mask_in_place); ++ and_reg(AT,swap_reg, AT); ++ bne(AT, try_rebias); ++ // The epoch of the current bias is still valid but we know nothing ++ // about the owner; it might be set or it might be clear. Try to ++ // acquire the bias of the object using an atomic operation. If this ++ // fails we will go in to the runtime to revoke the object's bias. ++ // Note that we first construct the presumed unbiased header so we ++ // don't accidentally blow away another thread's valid bias. ++ ++ ld_ptr(swap_reg, saved_mark_addr); ++ ++ move(AT, markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place); ++ and_reg(swap_reg, swap_reg, AT); ++ ++ if (need_tmp_reg) { ++ push(tmp_reg); ++ } ++ get_thread(tmp_reg); ++ or_ins(tmp_reg, tmp_reg, swap_reg); ++ //if (os::is_MP()) { ++ // memb(); ++ //} ++ cmpxchg(tmp_reg, Address(obj_reg, 0), swap_reg); ++ if (need_tmp_reg) { ++ pop(tmp_reg); ++ } ++ // If the biasing toward our thread failed, this means that ++ // another thread succeeded in biasing it toward itself and we ++ // need to revoke that bias. The revocation will occur in the ++ // interpreter runtime in the slow case. ++ if (PrintBiasedLockingStatistics) { ++ Label L; ++ bne(AT, L); ++ push(tmp_reg); ++ push(A0); ++ atomic_inc32((address)BiasedLocking::anonymously_biased_lock_entry_count_addr(), 1, A0, tmp_reg); ++ pop(A0); ++ pop(tmp_reg); ++ BIND(L); ++ } ++ if (slow_case != NULL) { ++ beq(AT, *slow_case); ++ } ++ beq(R0, done); ++ ++ BIND(try_rebias); ++ // At this point we know the epoch has expired, meaning that the ++ // current "bias owner", if any, is actually invalid. Under these ++ // circumstances _only_, we are allowed to use the current header's ++ // value as the comparison value when doing the cas to acquire the ++ // bias in the current epoch. In other words, we allow transfer of ++ // the bias from one thread to another directly in this situation. ++ // ++ if (need_tmp_reg) { ++ push(tmp_reg); ++ } ++ load_prototype_header(tmp_reg, obj_reg); ++ get_thread(swap_reg); ++ or_ins(tmp_reg, tmp_reg, swap_reg); ++ ld_ptr(swap_reg, saved_mark_addr); ++ ++ cmpxchg(tmp_reg, Address(obj_reg, 0), swap_reg); ++ if (need_tmp_reg) { ++ pop(tmp_reg); ++ } ++ // If the biasing toward our thread failed, then another thread ++ // succeeded in biasing it toward itself and we need to revoke that ++ // bias. The revocation will occur in the runtime in the slow case. ++ if (PrintBiasedLockingStatistics) { ++ Label L; ++ bne(AT, L); ++ push(AT); ++ push(tmp_reg); ++ atomic_inc32((address)BiasedLocking::rebiased_lock_entry_count_addr(), 1, AT, tmp_reg); ++ pop(tmp_reg); ++ pop(AT); ++ BIND(L); ++ } ++ if (slow_case != NULL) { ++ beq(AT, *slow_case); ++ } ++ ++ beq(R0, done); ++ BIND(try_revoke_bias); ++ // The prototype mark in the klass doesn't have the bias bit set any ++ // more, indicating that objects of this data type are not supposed ++ // to be biased any more. We are going to try to reset the mark of ++ // this object to the prototype value and fall through to the ++ // CAS-based locking scheme. Note that if our CAS fails, it means ++ // that another thread raced us for the privilege of revoking the ++ // bias of this particular object, so it's okay to continue in the ++ // normal locking code. ++ // ++ ld_ptr(swap_reg, saved_mark_addr); ++ ++ if (need_tmp_reg) { ++ push(tmp_reg); ++ } ++ load_prototype_header(tmp_reg, obj_reg); ++ //if (os::is_MP()) { ++ // lock(); ++ //} ++ cmpxchg(tmp_reg, Address(obj_reg, 0), swap_reg); ++ if (need_tmp_reg) { ++ pop(tmp_reg); ++ } ++ // Fall through to the normal CAS-based lock, because no matter what ++ // the result of the above CAS, some thread must have succeeded in ++ // removing the bias bit from the object's header. ++ if (PrintBiasedLockingStatistics) { ++ Label L; ++ bne(AT, L); ++ push(AT); ++ push(tmp_reg); ++ atomic_inc32((address)BiasedLocking::revoked_lock_entry_count_addr(), 1, AT, tmp_reg); ++ pop(tmp_reg); ++ pop(AT); ++ BIND(L); ++ } ++ ++ BIND(cas_label); ++ return null_check_offset; ++} ++ ++void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) { ++ assert(UseBiasedLocking, "why call this otherwise?"); ++ ++ // Check for biased locking unlock case, which is a no-op ++ // Note: we do not have to check the thread ID for two reasons. ++ // First, the interpreter checks for IllegalMonitorStateException at ++ // a higher level. Second, if the bias was revoked while we held the ++ // lock, the object could not be rebiased toward another thread, so ++ // the bias bit would be clear. ++ ldl(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes())); ++ and_imm8(temp_reg, temp_reg, markOopDesc::biased_lock_mask_in_place); ++ add_simm16(AT, R0, markOopDesc::biased_lock_pattern); ++ ++ beq(AT, temp_reg, done); ++} ++ ++// the stack pointer adjustment is needed. see InterpreterMacroAssembler::super_call_VM_leaf ++// this method will handle the stack problem, you need not to preserve the stack space for the argument now ++void MacroAssembler::call_VM_leaf_base(address entry_point, int number_of_arguments) { ++ Label L, E; ++ ++ assert(number_of_arguments <= 4, "just check"); ++ ++ and_imm8(AT, SP, 0xf); ++ beq(AT, L); ++ subl(SP, SP, 8); ++ call(entry_point, relocInfo::runtime_call_type); ++ addl(SP, SP, 8); ++ beq(R0, E); ++ ++ BIND(L); ++ call(entry_point, relocInfo::runtime_call_type); ++ BIND(E); ++} ++ ++ ++void MacroAssembler::jmp(Register reg) { ++ Assembler::jmp(AT, reg, 0); ++} ++ ++void MacroAssembler::jmp(address entry) { ++ patchable_jump(entry); ++} ++ ++void MacroAssembler::jmp(address entry, relocInfo::relocType rtype) { ++ switch (rtype) { ++ case relocInfo::runtime_call_type: ++ case relocInfo::none: ++ jmp(entry); ++ break; ++ default: ++ { ++ InstructionMark im(this); ++ relocate(rtype); ++ patchable_jump(entry); ++ } ++ break; ++ } ++} ++ ++void MacroAssembler::jmp_far(Label& L) { ++ if (L.is_bound()) { ++ address entry = target(L); ++ assert(entry != NULL, "jmp most probably wrong"); ++ InstructionMark im(this); ++ ++ relocate(relocInfo::internal_word_type); ++ if (SafePatch) { ++ if(offset() % 8 == 0) { ++ nop(); ++ br(T12, 2); ++ emit_int64((long)entry); ++ ldl(T12, T12, 0); ++ }else { ++ br(T12, 2); ++ emit_int64((long)entry); ++ ldl(T12, T12, 0); ++ nop(); ++ } ++ } else { ++ patchable_set48(T12, (long)entry); ++ } ++ jmp(T12); ++ } else { ++ InstructionMark im(this); ++ L.add_patch_at(code(), locator()); ++ ++ relocate(relocInfo::internal_word_type); ++ if (SafePatch) { ++ if(offset() % 8 == 0) { ++ nop(); ++ br(T12, 2); ++ emit_int64((long)pc()); ++ ldl(T12, T12, 0); ++ }else { ++ br(T12, 2); ++ emit_int64((long)pc()); ++ ldl(T12, T12, 0); ++ nop(); ++ } ++ } else { ++ patchable_set48(T12, (long)pc()); ++ } ++ jmp(T12); ++ } ++} ++ ++void MacroAssembler::mov_metadata(Address dst, Metadata* obj) { ++ int oop_index; ++ if (obj) { ++ oop_index = oop_recorder()->find_index(obj); ++ } else { ++ oop_index = oop_recorder()->allocate_metadata_index(obj); ++ } ++ relocate(metadata_Relocation::spec(oop_index)); ++ patchable_set48(AT, (long)obj); ++ stl(AT, dst); ++} ++ ++void MacroAssembler::mov_metadata(Register dst, Metadata* obj) { ++ int oop_index; ++ if (obj) { ++ oop_index = oop_recorder()->find_index(obj); ++ } else { ++ oop_index = oop_recorder()->allocate_metadata_index(obj); ++ } ++ relocate(metadata_Relocation::spec(oop_index)); ++ patchable_set48(dst, (long)obj); ++} ++ ++void MacroAssembler::call(Register reg) { ++ Assembler::call(RA, reg, 0); ++ nop(); ++} ++ ++void MacroAssembler::call(address entry) { ++// c/c++ code assume T12 is entry point, so we just always move entry to t12 ++// maybe there is some more graceful method to handle this. ++// For more info, see class NativeCall. ++ patchable_call(entry); ++} ++ ++void MacroAssembler::call(address entry, relocInfo::relocType rtype) { ++ switch (rtype) { ++ case relocInfo::runtime_call_type: ++ patchable_call_setfpec1(entry); ++ break; ++ case relocInfo::none: ++ call(entry); ++ break; ++ default: ++ { ++ InstructionMark im(this); ++ relocate(rtype); ++ call(entry); ++ } ++ break; ++ } ++} ++ ++void MacroAssembler::call(address entry, RelocationHolder& rh) ++{ ++ switch (rh.type()) { ++ case relocInfo::runtime_call_type: ++ patchable_call_setfpec1(entry); ++ break; ++ case relocInfo::none: ++ call(entry); ++ break; ++ default: ++ { ++ InstructionMark im(this); ++ relocate(rh); ++ call(entry); ++ } ++ break; ++ } ++} ++ ++void MacroAssembler::ic_call(address entry) { ++ RelocationHolder rh = virtual_call_Relocation::spec(pc()); ++ patchable_set48(IC_Klass, (long)Universe::non_oop_word()); ++ assert(entry != NULL, "call most probably wrong"); ++ InstructionMark im(this); ++ relocate(rh); ++ patchable_call(entry); ++} ++ ++void MacroAssembler::c2bool(Register r) { ++ Assembler::selne(r, 1, R0, r); ++} ++ ++#ifndef PRODUCT ++extern "C" void findpc(intptr_t x); ++#endif ++ ++void MacroAssembler::debug(char* msg/*, RegistersForDebugging* regs*/) { ++ if ( ShowMessageBoxOnError ) { ++ JavaThreadState saved_state = JavaThread::current()->thread_state(); ++ JavaThread::current()->set_thread_state(_thread_in_vm); ++ { ++ // In order to get locks work, we need to fake a in_VM state ++ ttyLocker ttyl; ++ ::tty->print_cr("EXECUTION STOPPED: %s\n", msg); ++ if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { ++ BytecodeCounter::print(); ++ } ++ ++ } ++ ThreadStateTransition::transition(JavaThread::current(), _thread_in_vm, saved_state); ++ } ++ else ++ ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg); ++} ++ ++ ++void MacroAssembler::stop(const char* msg) { ++ li(A0, (long)msg); ++ call(CAST_FROM_FN_PTR(address, MacroAssembler::debug), relocInfo::runtime_call_type); ++ brk(17); ++} ++ ++void MacroAssembler::warn(const char* msg) { ++ pushad(); ++ li(A0, (long)msg); ++ push(S2); ++ move(AT, -(StackAlignmentInBytes)); ++ move(S2, SP); // use S2 as a sender SP holder ++ and_reg(SP, SP, AT); // align stack as required by ABI ++ call(CAST_FROM_FN_PTR(address, MacroAssembler::debug), relocInfo::runtime_call_type); ++ move(SP, S2); // use S2 as a sender SP holder ++ pop(S2); ++ popad(); ++} ++ ++//void MacroAssembler::print_reg(Register reg) { ++// void * cur_pc = pc(); ++// pushad(); ++// NOT_LP64(push(FP);) ++// ++// li(A0, (long)reg->name()); ++// if (reg == SP) ++// add_simm16(A1, SP, wordSize * 23); //23 registers saved in pushad() ++// else if (reg == A0) ++// ldl(A1, SP, wordSize * 19); //A0 has been modified by li(A0, (long)reg->name()). Ugly Code! ++// else ++// move(A1, reg); ++// li(A2, (long)cur_pc); ++// push(S2); ++// move(AT, -(StackAlignmentInBytes)); ++// move(S2, SP); // use S2 as a sender SP holder ++// and_reg(SP, SP, AT); // align stack as required by ABI ++// call(CAST_FROM_FN_PTR(address, SharedRuntime::print_reg_with_pc),relocInfo::runtime_call_type); ++// move(SP, S2); // use S2 as a sender SP holder ++// pop(S2); ++// NOT_LP64(pop(FP);) ++// popad(); ++// ++//} ++ ++//void MacroAssembler::print_reg(FloatRegister reg) { ++// void * cur_pc = pc(); ++// pushad(); ++// NOT_LP64(push(FP);) ++// li(A0, (long)reg->name()); ++// push(S2); ++// move(AT, -(StackAlignmentInBytes)); ++// move(S2, SP); // use S2 as a sender SP holder ++// and_reg(SP, SP, AT); // align stack as required by ABI ++// call(CAST_FROM_FN_PTR(address, SharedRuntime::print_str),relocInfo::runtime_call_type); ++// move(SP, S2); // use S2 as a sender SP holder ++// pop(S2); ++// NOT_LP64(pop(FP);) ++// popad(); ++// ++// pushad(); ++// NOT_LP64(push(FP);) ++// move(FP, SP); ++// move(AT, -(StackAlignmentInBytes)); ++// and_reg(SP , SP , AT); ++// fmovd(F16, reg); ++// call(CAST_FROM_FN_PTR(address, SharedRuntime::print_double),relocInfo::runtime_call_type); ++// move(SP, FP); ++// NOT_LP64(pop(FP);) ++// popad(); ++// ++//} ++ ++void MacroAssembler::increment(Register reg, int imm) { ++ if (!imm) return; ++ if (is_simm16(imm)) { ++ add_simm16(reg, reg, imm); ++ } else { ++ move(AT, imm); ++ addl(reg, reg, AT); ++ } ++} ++ ++void MacroAssembler::decrement(Register reg, int imm) { ++ increment(reg, -imm); ++} ++ ++ ++void MacroAssembler::call_VM(Register oop_result, ++ address entry_point, ++ bool check_exceptions) { ++ call_VM_helper(oop_result, entry_point, 0, check_exceptions); ++} ++ ++void MacroAssembler::call_VM(Register oop_result, ++ address entry_point, ++ Register arg_1, ++ bool check_exceptions) { ++ if (arg_1!=A1) move(A1, arg_1); ++ call_VM_helper(oop_result, entry_point, 1, check_exceptions); ++} ++ ++void MacroAssembler::call_VM(Register oop_result, ++ address entry_point, ++ Register arg_1, ++ Register arg_2, ++ bool check_exceptions) { ++ if (arg_1!=A1) move(A1, arg_1); ++ if (arg_2!=A2) move(A2, arg_2); ++ assert(arg_2 != A1, "smashed argument"); ++ call_VM_helper(oop_result, entry_point, 2, check_exceptions); ++} ++ ++void MacroAssembler::call_VM(Register oop_result, ++ address entry_point, ++ Register arg_1, ++ Register arg_2, ++ Register arg_3, ++ bool check_exceptions) { ++ if (arg_1!=A1) move(A1, arg_1); ++ if (arg_2!=A2) move(A2, arg_2); assert(arg_2 != A1, "smashed argument"); ++ if (arg_3!=A3) move(A3, arg_3); assert(arg_3 != A1 && arg_3 != A2, "smashed argument"); ++ call_VM_helper(oop_result, entry_point, 3, check_exceptions); ++} ++ ++void MacroAssembler::call_VM(Register oop_result, ++ Register last_java_sp, ++ address entry_point, ++ int number_of_arguments, ++ bool check_exceptions) { ++ call_VM_base(oop_result, NOREG, last_java_sp, entry_point, number_of_arguments, check_exceptions); ++} ++ ++void MacroAssembler::call_VM(Register oop_result, ++ Register last_java_sp, ++ address entry_point, ++ Register arg_1, ++ bool check_exceptions) { ++ if (arg_1 != A1) move(A1, arg_1); ++ call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); ++} ++ ++void MacroAssembler::call_VM(Register oop_result, ++ Register last_java_sp, ++ address entry_point, ++ Register arg_1, ++ Register arg_2, ++ bool check_exceptions) { ++ if (arg_1 != A1) move(A1, arg_1); ++ if (arg_2 != A2) move(A2, arg_2); assert(arg_2 != A1, "smashed argument"); ++ call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); ++} ++ ++void MacroAssembler::call_VM(Register oop_result, ++ Register last_java_sp, ++ address entry_point, ++ Register arg_1, ++ Register arg_2, ++ Register arg_3, ++ bool check_exceptions) { ++ if (arg_1 != A1) move(A1, arg_1); ++ if (arg_2 != A2) move(A2, arg_2); assert(arg_2 != A1, "smashed argument"); ++ if (arg_3 != A3) move(A3, arg_3); assert(arg_3 != A1 && arg_3 != A2, "smashed argument"); ++ call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); ++} ++ ++void MacroAssembler::call_VM_base(Register oop_result, ++ Register java_thread, ++ Register last_java_sp, ++ address entry_point, ++ int number_of_arguments, ++ bool check_exceptions) { ++ ++ address before_call_pc; ++ // determine java_thread register ++ if (!java_thread->is_valid()) { ++ java_thread = S2thread; ++ } ++ // determine last_java_sp register ++ if (!last_java_sp->is_valid()) { ++ last_java_sp = SP; ++ } ++ // debugging support ++ assert(number_of_arguments >= 0 , "cannot have negative number of arguments"); ++ assert(number_of_arguments <= 4 , "cannot have negative number of arguments"); ++ assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result"); ++ assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp"); ++ ++ assert(last_java_sp != FP, "this code doesn't work for last_java_sp == fp, which currently can't portably work anyway since C2 doesn't save fp"); ++ ++ // set last Java frame before call ++ before_call_pc = (address)pc(); ++ set_last_Java_frame(java_thread, last_java_sp, FP, before_call_pc); ++ ++ // do the call ++ move(A0, java_thread); ++ call(entry_point, relocInfo::runtime_call_type); ++ ++ // restore the thread (cannot use the pushed argument since arguments ++ // may be overwritten by C code generated by an optimizing compiler); ++ // however can use the register value directly if it is callee saved. ++#ifdef ASSERT ++ { ++ Label L; ++ get_thread(AT); ++ beq(java_thread, AT, L); ++ stop("MacroAssembler::call_VM_base: TREG not callee saved?"); ++ BIND(L); ++ } ++#endif ++ ++ // discard thread and arguments ++ ld_ptr(SP, java_thread, in_bytes(JavaThread::last_Java_sp_offset())); ++ // reset last Java frame ++ reset_last_Java_frame(java_thread, false); ++ ++ check_and_handle_popframe(java_thread); ++ check_and_handle_earlyret(java_thread); ++ if (check_exceptions) { ++ // check for pending exceptions (java_thread is set upon return) ++ Label L; ++ ldl(AT, java_thread, in_bytes(Thread::pending_exception_offset())); ++ beq(AT, L); ++ li(AT, before_call_pc); ++ push(AT); ++ jmp(StubRoutines::forward_exception_entry(), relocInfo::runtime_call_type); ++ BIND(L); ++ } ++ ++ // get oop result if there is one and reset the value in the thread ++ if (oop_result->is_valid()) { ++ ldl(oop_result, java_thread, in_bytes(JavaThread::vm_result_offset())); ++ stl(R0, java_thread, in_bytes(JavaThread::vm_result_offset())); ++ // verify_oop(oop_result); ++ } ++} ++ ++void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) { ++ ++ move(V0, SP); ++ //we also reserve space for java_thread here ++ move(AT, -(StackAlignmentInBytes)); ++ and_reg(SP, SP, AT); ++ call_VM_base(oop_result, NOREG, V0, entry_point, number_of_arguments, check_exceptions); ++ ++} ++ ++void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) { ++ call_VM_leaf_base(entry_point, number_of_arguments); ++} ++ ++void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) { ++ if (arg_0 != A0) move(A0, arg_0); ++ call_VM_leaf(entry_point, 1); ++} ++ ++void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { ++ if (arg_0 != A0) move(A0, arg_0); ++ if (arg_1 != A1) move(A1, arg_1); assert(arg_1 != A0, "smashed argument"); ++ call_VM_leaf(entry_point, 2); ++} ++ ++void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) { ++ if (arg_0 != A0) move(A0, arg_0); ++ if (arg_1 != A1) move(A1, arg_1); assert(arg_1 != A0, "smashed argument"); ++ if (arg_2 != A2) move(A2, arg_2); assert(arg_2 != A0 && arg_2 != A1, "smashed argument"); ++ call_VM_leaf(entry_point, 3); ++} ++void MacroAssembler::super_call_VM_leaf(address entry_point) { ++ MacroAssembler::call_VM_leaf_base(entry_point, 0); ++} ++ ++ ++void MacroAssembler::super_call_VM_leaf(address entry_point, ++ Register arg_1) { ++ if (arg_1 != A0) move(A0, arg_1); ++ MacroAssembler::call_VM_leaf_base(entry_point, 1); ++} ++ ++ ++void MacroAssembler::super_call_VM_leaf(address entry_point, ++ Register arg_1, ++ Register arg_2) { ++ if (arg_1 != A0) move(A0, arg_1); ++ if (arg_2 != A1) move(A1, arg_2); assert(arg_2 != A0, "smashed argument"); ++ MacroAssembler::call_VM_leaf_base(entry_point, 2); ++} ++ ++ ++void MacroAssembler::super_call_VM_leaf(address entry_point, ++ Register arg_1, ++ Register arg_2, ++ Register arg_3) { ++ if (arg_1 != A0) move(A0, arg_1); ++ if (arg_2 != A1) move(A1, arg_2); assert(arg_2 != A0, "smashed argument"); ++ if (arg_3 != A2) move(A2, arg_3); assert(arg_3 != A0 && arg_3 != A1, "smashed argument"); ++ MacroAssembler::call_VM_leaf_base(entry_point, 3); ++} ++ ++void MacroAssembler::check_and_handle_earlyret(Register java_thread) { ++} ++ ++void MacroAssembler::check_and_handle_popframe(Register java_thread) { ++} ++ ++void MacroAssembler::null_check(Register reg, int offset) { ++ if (needs_explicit_null_check(offset)) { ++ // provoke OS NULL exception if reg = NULL by ++ // accessing M[reg] w/o changing any (non-CC) registers ++ // NOTE: cmpl is plenty here to provoke a segv ++ ldw(AT, reg, 0); ++ } else { ++ // nothing to do, (later) access of M[reg + offset] ++ // will provoke OS NULL exception if reg = NULL ++ } ++} ++ ++void MacroAssembler::enter() { ++ push2(RA, FP); ++ move(FP, SP); ++} ++ ++void MacroAssembler::leave() { ++ add_simm16(SP, FP, 2 * wordSize); ++ ldl(RA, SP, - 1 * wordSize); ++ ldl(FP, SP, - 2 * wordSize); ++} ++ ++void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp) { ++ // determine java_thread register ++ if (!java_thread->is_valid()) { ++ java_thread = S2thread; ++ } ++ // we must set sp to zero to clear frame ++ st_ptr(R0, java_thread, in_bytes(JavaThread::last_Java_sp_offset())); ++ // must clear fp, so that compiled frames are not confused; it is possible ++ // that we need it only for debugging ++ if(clear_fp) { ++ st_ptr(R0, java_thread, in_bytes(JavaThread::last_Java_fp_offset())); ++ } ++ ++ // Always clear the pc because it could have been set by make_walkable() ++ st_ptr(R0, java_thread, in_bytes(JavaThread::last_Java_pc_offset())); ++} ++ ++void MacroAssembler::reset_last_Java_frame(bool clear_fp) { ++ Register thread = S2thread; ++ // we must set sp to zero to clear frame ++ stl(R0, Address(thread, JavaThread::last_Java_sp_offset())); ++ // must clear fp, so that compiled frames are not confused; it is ++ // possible that we need it only for debugging ++ if (clear_fp) { ++ stl(R0, Address(thread, JavaThread::last_Java_fp_offset())); ++ } ++ ++ // Always clear the pc because it could have been set by make_walkable() ++ stl(R0, Address(thread, JavaThread::last_Java_pc_offset())); ++} ++ ++// Write serialization page so VM thread can do a pseudo remote membar. ++// We use the current thread pointer to calculate a thread specific ++// offset to write to within the page. This minimizes bus traffic ++// due to cache line collision. ++void MacroAssembler::serialize_memory(Register thread, Register tmp) { ++ move(tmp, thread); ++ zapnot(tmp, tmp, 0xf); ++ srll(tmp, tmp, os::get_serialize_page_shift_count()); ++ move(AT, (os::vm_page_size() - sizeof(int))); ++ and_reg(tmp, tmp, AT); ++ stw(tmp, Address(tmp, (intptr_t)os::get_memory_serialize_page())); ++} ++ ++// Calls to C land ++// ++// When entering C land, the fp, & sp of the last Java frame have to be recorded ++// in the (thread-local) JavaThread object. When leaving C land, the last Java fp ++// has to be reset to 0. This is required to allow proper stack traversal. ++void MacroAssembler::set_last_Java_frame(Register java_thread, ++ Register last_java_sp, ++ Register last_java_fp, ++ address last_java_pc) { ++ // determine java_thread register ++ if (!java_thread->is_valid()) { ++ java_thread = S2thread; ++ } ++ // determine last_java_sp register ++ if (!last_java_sp->is_valid()) { ++ last_java_sp = SP; ++ } ++ ++ // last_java_fp is optional ++ if (last_java_fp->is_valid()) { ++ st_ptr(last_java_fp, java_thread, in_bytes(JavaThread::last_Java_fp_offset())); ++ } ++ ++ // last_java_pc is optional ++ if (last_java_pc != NULL) { ++ relocate(relocInfo::internal_word_type); ++ patchable_set48(AT, (long)last_java_pc); ++ st_ptr(AT, java_thread, in_bytes(JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset())); ++ } ++ st_ptr(last_java_sp, java_thread, in_bytes(JavaThread::last_Java_sp_offset())); ++} ++ ++void MacroAssembler::set_last_Java_frame(Register last_java_sp, ++ Register last_java_fp, ++ address last_java_pc) { ++ // determine last_java_sp register ++ if (!last_java_sp->is_valid()) { ++ last_java_sp = SP; ++ } ++ ++ Register thread = S2thread; ++ // last_java_fp is optional ++ if (last_java_fp->is_valid()) { ++ stl(last_java_fp, Address(thread, JavaThread::last_Java_fp_offset())); ++ } ++ ++ // last_java_pc is optional ++ if (last_java_pc != NULL) { ++ relocate(relocInfo::internal_word_type); ++ patchable_set48(AT, (long)last_java_pc); ++ st_ptr(AT, thread, in_bytes(JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset())); ++ } ++ ++ stl(last_java_sp, Address(thread, JavaThread::last_Java_sp_offset())); ++} ++ ++void MacroAssembler::resolve_jobject(Register value, ++ Register thread, ++ Register tmp) { ++ assert_different_registers(value, thread, tmp); ++ Label done, not_weak; ++ beq(value, done); // Use NULL as-is. ++ ldi(AT, R0, JNIHandles::weak_tag_mask); ++ and_reg(AT, value, AT); ++ beq(AT, not_weak); ++ // Resolve jweak. ++ ldl(value, value, -JNIHandles::weak_tag_value); ++ verify_oop(value); ++#if INCLUDE_ALL_GCS ++ if (UseG1GC) { ++ g1_write_barrier_pre(noreg /* obj */, ++ value /* pre_val */, ++ thread /* thread */, ++ tmp /* tmp */, ++ true /* tosca_live */, ++ true /* expand_call */); ++ } ++#endif // INCLUDE_ALL_GCS ++ beq(R0, done); ++ BIND(not_weak); ++ // Resolve (untagged) jobject. ++ ldl(value, value, 0); ++ verify_oop(value); ++ BIND(done); ++} ++ ++void MacroAssembler::clear_jweak_tag(Register possibly_jweak) { ++ const int32_t inverted_jweak_mask = ~static_cast(JNIHandles::weak_tag_mask); ++ STATIC_ASSERT(inverted_jweak_mask == -2); // otherwise check this code ++ // The inverted mask is sign-extended ++ move(AT, inverted_jweak_mask); ++ and_reg(possibly_jweak, possibly_jweak, AT); ++} ++ ++////////////////////////////////////////////////////////////////////////////////// ++#if INCLUDE_ALL_GCS ++ ++void MacroAssembler::g1_write_barrier_pre(Register obj, ++ Register pre_val, ++ Register thread, ++ Register tmp, ++ bool tosca_live, ++ bool expand_call) { ++ ++ // If expand_call is true then we expand the call_VM_leaf macro ++ // directly to skip generating the check by ++ // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp. ++ ++ assert(thread == S2thread, "must be"); ++ ++ Label done; ++ Label runtime; ++ ++ assert(pre_val != noreg, "check this code"); ++ ++ if (obj != noreg) { ++ assert_different_registers(obj, pre_val, tmp); ++ assert(pre_val != V0, "check this code"); ++ } ++ ++ Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() + ++ PtrQueue::byte_offset_of_active())); ++ Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() + ++ PtrQueue::byte_offset_of_index())); ++ Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() + ++ PtrQueue::byte_offset_of_buf())); ++ ++ ++ // Is marking active? ++ if (in_bytes(PtrQueue::byte_width_of_active()) == 4) { ++ ldw_signed(AT, in_progress); ++ } else { ++ assert(in_bytes(PtrQueue::byte_width_of_active()) == 1, "Assumption"); ++ ldb_signed(AT, in_progress); ++ } ++ beq(AT, done); ++ ++ // Do we need to load the previous value? ++ if (obj != noreg) { ++ load_heap_oop(pre_val, Address(obj, 0)); ++ } ++ ++ // Is the previous value null? ++ beq(pre_val, done); ++ ++ // Can we store original value in the thread's buffer? ++ // Is index == 0? ++ // (The index field is typed as size_t.) ++ ++ ldl(tmp, index); ++ beq(tmp, runtime); ++ ++ add_simm16(tmp, tmp, -1 * wordSize); ++ stl(tmp, index); ++ ldl(AT, buffer); ++ addl(tmp, tmp, AT); ++ ++ // Record the previous value ++ stl(pre_val, tmp, 0); ++ beq(R0, done); ++ ++ BIND(runtime); ++ // save the live input values ++ if (tosca_live) push(V0); ++ ++ if (obj != noreg && obj != V0) push(obj); ++ ++ if (pre_val != V0) push(pre_val); ++ ++ // Calling the runtime using the regular call_VM_leaf mechanism generates ++ // code (generated by InterpreterMacroAssember::call_VM_leaf_base) ++ // that checks that the *(fp+frame::interpreter_frame_last_sp) == NULL. ++ // ++ // If we care generating the pre-barrier without a frame (e.g. in the ++ // intrinsified Reference.get() routine) then fp might be pointing to ++ // the caller frame and so this check will most likely fail at runtime. ++ // ++ // Expanding the call directly bypasses the generation of the check. ++ // So when we do not have have a full interpreter frame on the stack ++ // expand_call should be passed true. ++ ++ NOT_LP64( push(thread); ) ++ ++ if (expand_call) { ++ LP64_ONLY( assert(pre_val != A1, "smashed arg"); ) ++ if (thread != A1) move(A1, thread); ++ if (pre_val != A0) move(A0, pre_val); ++ MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), 2); ++ } else { ++ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), pre_val, thread); ++ } ++ ++ NOT_LP64( pop(thread); ) ++ ++ // save the live input values ++ if (pre_val != V0) ++ pop(pre_val); ++ ++ if (obj != noreg && obj != V0) ++ pop(obj); ++ ++ if(tosca_live) pop(V0); ++ ++ BIND(done); ++} ++ ++void MacroAssembler::g1_write_barrier_post(Register store_addr, ++ Register new_val, ++ Register thread, ++ Register tmp, ++ Register tmp2) { ++ assert(tmp != AT, "must be"); ++ assert(tmp2 != AT, "must be"); ++ assert(thread == S2thread, "must be"); ++ ++ Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() + ++ PtrQueue::byte_offset_of_index())); ++ Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() + ++ PtrQueue::byte_offset_of_buf())); ++ ++ BarrierSet* bs = Universe::heap()->barrier_set(); ++ CardTableModRefBS* ct = (CardTableModRefBS*)bs; ++ assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); ++ ++ Label done; ++ Label runtime; ++ ++ // Does store cross heap regions? ++ xor_ins(AT, store_addr, new_val); ++ srll(AT, AT, HeapRegion::LogOfHRGrainBytes); ++ beq(AT, done); ++ ++ ++ // crosses regions, storing NULL? ++ beq(new_val, done); ++ ++ // storing region crossing non-NULL, is card already dirty? ++ const Register card_addr = tmp; ++ const Register cardtable = tmp2; ++ ++ move(card_addr, store_addr); ++ srll(card_addr, card_addr, CardTableModRefBS::card_shift); ++ // Do not use ExternalAddress to load 'byte_map_base', since 'byte_map_base' is NOT ++ // a valid address and therefore is not properly handled by the relocation code. ++ set64(cardtable, (intptr_t)ct->byte_map_base); ++ addl(card_addr, card_addr, cardtable); ++ ++ ldbu(AT, card_addr, 0); ++ add_simm16(AT, AT, -1 * (int)G1SATBCardTableModRefBS::g1_young_card_val()); ++ beq(AT, done); ++ ++ memb(); ++ ldbu(AT, card_addr, 0); ++ add_simm16(AT, AT, -1 * (int)(int)CardTableModRefBS::dirty_card_val()); ++ beq(AT, done); ++ ++ ++ // storing a region crossing, non-NULL oop, card is clean. ++ // dirty card and log. ++ move(AT, (int)CardTableModRefBS::dirty_card_val()); ++ stb(AT, card_addr, 0); ++ ++ ldw_signed(AT, queue_index); ++ beq(AT, runtime); ++ add_simm16(AT, AT, -1 * wordSize); ++ stw(AT, queue_index); ++ ldl(tmp2, buffer); ++ ldl(AT, queue_index); ++ addl(tmp2, tmp2, AT); ++ stl(card_addr, tmp2, 0); ++ beq(R0, done); ++ ++ BIND(runtime); ++ // save the live input values ++ push(store_addr); ++ push(new_val); ++ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, S2thread); ++ pop(new_val); ++ pop(store_addr); ++ ++ BIND(done); ++} ++ ++#endif // INCLUDE_ALL_GCS ++////////////////////////////////////////////////////////////////////////////////// ++ ++ ++void MacroAssembler::store_check(Register obj) { ++ // Does a store check for the oop in register obj. The content of ++ // register obj is destroyed afterwards. ++ store_check_part_1(obj); ++ store_check_part_2(obj); ++} ++ ++void MacroAssembler::store_check(Register obj, Address dst) { ++ store_check(obj); ++} ++ ++ ++// split the store check operation so that other instructions can be scheduled inbetween ++void MacroAssembler::store_check_part_1(Register obj) { ++ BarrierSet* bs = Universe::heap()->barrier_set(); ++ assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind"); ++ srll(obj, obj, CardTableModRefBS::card_shift); ++} ++ ++void MacroAssembler::store_check_part_2(Register obj) { ++ BarrierSet* bs = Universe::heap()->barrier_set(); ++ assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind"); ++ CardTableModRefBS* ct = (CardTableModRefBS*)bs; ++ assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); ++ ++ set64(AT, (long)ct->byte_map_base); ++ addl(AT, AT, obj); ++ if (UseConcMarkSweepGC) ++ if(UseWmemb) ++ wmemb(); ++ else ++ memb(); ++ stb(R0, AT, 0); ++} ++ ++// Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes. ++void MacroAssembler::tlab_allocate(Register obj, Register var_size_in_bytes, int con_size_in_bytes, ++ Register t1, Register t2, Label& slow_case) { ++ assert_different_registers(obj, var_size_in_bytes, t1, t2, AT); ++ ++ Register end = t2; ++ Register thread = S2thread; ++ verify_tlab(t1, t2);//blows t1&t2 ++ ++ ld_ptr(obj, thread, in_bytes(JavaThread::tlab_top_offset())); ++ ++ if (var_size_in_bytes == NOREG) { ++ set64(AT, con_size_in_bytes); ++ addl(end, obj, AT); ++ } else { ++ addl(end, obj, var_size_in_bytes); ++ } ++ ++ ld_ptr(AT, thread, in_bytes(JavaThread::tlab_end_offset())); ++ cmpult(AT, AT, end); ++ bne(AT, slow_case); ++ ++ ++ // update the tlab top pointer ++ st_ptr(end, thread, in_bytes(JavaThread::tlab_top_offset())); ++ ++ verify_tlab(t1, t2); ++} ++ ++// Defines obj, preserves var_size_in_bytes ++void MacroAssembler::eden_allocate(Register obj, Register var_size_in_bytes, int con_size_in_bytes, ++ Register t1, Register t2, Label& slow_case) { ++ assert_different_registers(obj, var_size_in_bytes, t1, AT); ++ if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) { ++ // No allocation in the shared eden. ++ b_far(slow_case); ++ } else { ++ ++ Address heap_top(t1); ++ li(t1, (long)Universe::heap()->top_addr()); ++ ld_ptr(obj, heap_top); ++ ++ Register end = t2; ++ Label retry; ++ ++ BIND(retry); ++ if (var_size_in_bytes == NOREG) { ++ set64(AT, con_size_in_bytes); ++ addl(end, obj, AT); ++ } else { ++ addl(end, obj, var_size_in_bytes); ++ } ++ // if end < obj then we wrapped around => object too long => slow case ++ cmpult(AT, end, obj); ++ bne(AT, slow_case); ++ ++ li(AT, (long)Universe::heap()->end_addr()); ++ ld_ptr(AT, AT, 0); ++ cmpult(AT, AT, end); ++ bne(AT, slow_case); ++ // Compare obj with the top addr, and if still equal, store the new top addr in ++ // end at the address of the top addr pointer. Sets ZF if was equal, and clears ++ // it otherwise. Use lock prefix for atomicity on MPs. ++ //if (os::is_MP()) { ++ // memb(); ++ //} ++ ++ // if someone beat us on the allocation, try again, otherwise continue ++ cmpxchg(end, heap_top, obj); ++ beq(AT, retry); ++ } ++} ++ ++// C2 doesn't invoke this one. ++void MacroAssembler::tlab_refill(Label& retry, Label& try_eden, Label& slow_case) { ++ Register top = T0; ++ Register t1 = T1; ++ Register t2 = T12; ++ Register t3 = T3; ++ Register thread_reg = T11; ++ assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ T2, A4); ++ Label do_refill, discard_tlab; ++ if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) { ++ // No allocation in the shared eden. ++ beq(R0, slow_case); ++ } ++ ++ get_thread(thread_reg); ++ ++ ldl(top, thread_reg, in_bytes(JavaThread::tlab_top_offset())); ++ ldl(t1, thread_reg, in_bytes(JavaThread::tlab_end_offset())); ++ ++ // calculate amount of free space ++ subl(t1, t1, top); ++ srll(t1, t1, LogHeapWordSize); ++ ++ // Retain tlab and allocate object in shared space if ++ // the amount free in the tlab is too large to discard. ++ ldl(t2, thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())); ++ cmplt(AT, t2, t1); ++ beq(AT, discard_tlab); ++ ++ // Retain ++ add_simm16(t2, t2, ThreadLocalAllocBuffer::refill_waste_limit_increment()); ++ stl(t2, thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())); ++ ++ if (TLABStats) { ++ // increment number of slow_allocations ++ ldw(AT, thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())); ++ addl(AT, AT, 1); ++ stw(AT, thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())); ++ } ++ beq(R0, try_eden); ++ ++ BIND(discard_tlab); ++ if (TLABStats) { ++ // increment number of refills ++ ldw(AT, thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())); ++ addl(AT, AT, 1); ++ stw(AT, thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())); ++ // accumulate wastage -- t1 is amount free in tlab ++ ldw(AT, thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())); ++ addl(AT, AT, t1); ++ stw(AT, thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())); ++ } ++ ++ // if tlab is currently allocated (top or end != null) then ++ // fill [top, end + alignment_reserve) with array object ++ beq(top, do_refill); ++ ++ // set up the mark word ++ li(AT, (long)markOopDesc::prototype()->copy_set_hash(0x2)); ++ stl(AT, top, oopDesc::mark_offset_in_bytes()); ++ ++ // set the length to the remaining space ++ add_simm16(t1, t1, - typeArrayOopDesc::header_size(T_INT)); ++ add_simm16(t1, t1, ThreadLocalAllocBuffer::alignment_reserve()); ++ slll(t1, t1, log2_intptr(HeapWordSize/sizeof(jint))); ++ stw(t1, top, arrayOopDesc::length_offset_in_bytes()); ++ ++ // set klass to intArrayKlass ++ li(AT, (intptr_t)Universe::intArrayKlassObj_addr()); ++ ldl(t1,AT,0); ++ //st_ptr(t1, top, oopDesc::klass_offset_in_bytes()); ++ store_klass(top, t1); ++ ++ ldl(t1, thread_reg, in_bytes(JavaThread::tlab_start_offset())); ++ subl(t1, top, t1); ++ incr_allocated_bytes(thread_reg, t1, 0); ++ ++ // refill the tlab with an eden allocation ++ BIND(do_refill); ++ ldl(t1, thread_reg, in_bytes(JavaThread::tlab_size_offset())); ++ slll(t1, t1, LogHeapWordSize); ++ // add object_size ?? ++ eden_allocate(top, t1, 0, t2, t3, slow_case); ++ ++ // Check that t1 was preserved in eden_allocate. ++#ifdef ASSERT ++ if (UseTLAB) { ++ Label ok; ++ assert_different_registers(thread_reg, t1); ++ ldl(AT, thread_reg, in_bytes(JavaThread::tlab_size_offset())); ++ slll(AT, AT, LogHeapWordSize); ++ beq(AT, t1, ok); ++ stop("assert(t1 != tlab size)"); ++ should_not_reach_here(); ++ ++ BIND(ok); ++ } ++#endif ++ stl(top, thread_reg, in_bytes(JavaThread::tlab_start_offset())); ++ stl(top, thread_reg, in_bytes(JavaThread::tlab_top_offset())); ++ addl(top, top, t1); ++ add_simm16(top, top, - ThreadLocalAllocBuffer::alignment_reserve_in_bytes()); ++ stl(top, thread_reg, in_bytes(JavaThread::tlab_end_offset())); ++ verify_tlab(t1, t2); ++ beq(R0, retry); ++} ++ ++/** ++ * Emits code to update CRC-32 with a byte value according to constants in table ++ * ++ * @param [in,out]crc Register containing the crc. ++ * @param [in]val Register containing the byte to fold into the CRC. ++ * @param [in]table Register containing the table of crc constants. ++ * ++ * uint32_t crc; ++ * val = crc_table[(val ^ crc) & 0xFF]; ++ * crc = val ^ (crc >> 8); ++ * ++ */ ++void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) { ++ xor_ins(val, crc, val); ++ and_imm8(val, val, 0xFF); ++ srll(crc, crc, 8); // unsigned shift ++// zapnot(crc, crc, 0xF); ++ ++ slll(AT, val, Address::times_4); ++ addl(AT, table, AT); ++ ldw(AT, AT, 0); ++ zapnot(AT, AT, 0xF); ++ xor_ins(crc, AT, crc); ++} ++ ++/** ++ * @param crc register containing existing CRC (32-bit) ++ * @param buf register pointing to input byte buffer (byte*) ++ * @param len register containing number of bytes ++ * @param tmp scratch register ++ */ ++void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register tmp, Register tmp3) { ++ assert_different_registers(crc, buf, len, tmp, tmp3, V0); ++ Label L_begin_loop, L_aligned, CRC_by64_loop, CRC_by4_loop, CRC_by1_loop, L_exit; ++ ++ ornot(crc, R0, crc); ++ if(SolveAlignment) { ++ beq(len, L_exit); ++ BIND(L_begin_loop); ++ and_imm8(AT, buf, 7); ++ beq(AT, L_aligned); ++ ldbu_a(tmp, 1, buf); ++ subl(len, len, 1); ++ crc32b(crc, crc, tmp); ++ bgt(len, L_begin_loop); ++ beq(R0, L_exit); ++ } ++ ++ BIND (L_aligned); ++ subl(len, len, 64); ++ bge(len, CRC_by64_loop); ++ addl(len, len, 64-4); ++ bge(len, CRC_by4_loop); ++ addl(len, len, 4); ++ bgt(len, CRC_by1_loop); ++ beq(R0, L_exit); ++ ++ BIND(CRC_by4_loop); ++ ldw_a(tmp, 4, buf); ++ subl(len, len, 4); ++ crc32w(crc, crc, tmp); ++ bge(len, CRC_by4_loop); ++ addl(len, len, 4); ++ ble(len, L_exit); ++ BIND(CRC_by1_loop); ++ ldbu_a(tmp, 1, buf); ++ subl(len, len, 1); ++ crc32b(crc, crc, tmp); ++ bgt(len, CRC_by1_loop); ++ beq(R0, L_exit); ++ ++ align(CodeEntryAlignment); ++ BIND(CRC_by64_loop); ++ subl(len, len, 64); ++ ldl_a(tmp, 8, buf); ++ ldl_a(tmp3, 8, buf); ++ crc32l(crc, crc, tmp); ++ crc32l(crc, crc, tmp3); ++ ldl_a(tmp, 8, buf); ++ ldl_a(tmp3, 8, buf); ++ crc32l(crc, crc, tmp); ++ crc32l(crc, crc, tmp3); ++ ldl_a(tmp, 8, buf); ++ ldl_a(tmp3, 8, buf); ++ crc32l(crc, crc, tmp); ++ crc32l(crc, crc, tmp3); ++ ldl_a(tmp, 8, buf); ++ ldl_a(tmp3, 8, buf); ++ crc32l(crc, crc, tmp); ++ crc32l(crc, crc, tmp3); ++ bge(len, CRC_by64_loop); ++ addl(len, len, 64-4); ++ bge(len, CRC_by4_loop); ++ addl(len, len, 4); ++ bgt(len, CRC_by1_loop); ++ BIND(L_exit); ++ ornot(crc, R0, crc); ++ ++ move(V0, crc); ++} ++ ++void MacroAssembler::incr_allocated_bytes(Register thread, ++ Register var_size_in_bytes, ++ int con_size_in_bytes, ++ Register t1) { ++ if (!thread->is_valid()) { ++ thread = S2thread; ++ } ++ ++ ld_ptr(AT, thread, in_bytes(JavaThread::allocated_bytes_offset())); ++ if (var_size_in_bytes->is_valid()) { ++ addl(AT, AT, var_size_in_bytes); ++ } else { ++ add_simm16(AT, AT, con_size_in_bytes); ++ } ++ st_ptr(AT, thread, in_bytes(JavaThread::allocated_bytes_offset())); ++} ++ ++static const double pi_4 = 0.7853981633974483; ++ ++// must get argument(a double) in F16/F17 ++//void MacroAssembler::trigfunc(char trig, bool preserve_cpu_regs, int num_fpu_regs_in_use) { ++//We need to preseve the register which maybe modified during the Call ++void MacroAssembler::trigfunc(char trig, int num_fpu_regs_in_use) { ++//save all modified register here ++ pushad(); ++//we should preserve the stack space before we call ++ add_simm16(SP, SP, -wordSize * 2); ++ switch (trig){ ++ case 's' : ++ call( CAST_FROM_FN_PTR(address, SharedRuntime::dsin), relocInfo::runtime_call_type ); ++ break; ++ case 'c': ++ call( CAST_FROM_FN_PTR(address, SharedRuntime::dcos), relocInfo::runtime_call_type ); ++ break; ++ case 't': ++ call( CAST_FROM_FN_PTR(address, SharedRuntime::dtan), relocInfo::runtime_call_type ); ++ break; ++ default:assert (false, "bad intrinsic"); ++ break; ++ } ++ ++ add_simm16(SP, SP, wordSize * 2); ++ popad(); ++} ++ ++void MacroAssembler::li(Register rd, long imm) { ++ int32_t lsb32 = (int32_t) (imm); ++ int32_t msb32 = (int32_t) ((imm - lsb32) >> 32); ++ int16_t msb_h = (msb32-(int16_t)msb32) >> 16; ++ int16_t msb_l = (int16_t)msb32; ++ int16_t lsb_h = (lsb32-(int16_t)lsb32) >> 16; ++ int16_t lsb_l = (int16_t)lsb32; ++ ++ if(msb_h == 0) { ++ ldi(rd, R0, msb_l); ++ } else { ++ ldih(rd, R0, msb_h); ++ if(msb_l != 0) ++ ldi(rd, rd, msb_l); ++ } ++ slll(rd, rd, 32); ++ if( ((int)lsb_h == -32768) && (lsb_l < 0) ) { ++ ldih(rd, rd, 0x4000); ++ ldih(rd, rd, 0x4000); ++ ldi(rd, rd, lsb_l); ++ } else { ++ ldih(rd, rd, lsb_h); ++ ldi(rd, rd, lsb_l); ++ } ++} ++ ++ ++void MacroAssembler::boundary_test(FloatRegister ft, Register res){ ++ Register tmp1 = AT; ++ Register tmp2 = GP; ++ fimovd(tmp1, ft); ++ slll(tmp2, tmp1, 0x1); ++ srll(tmp2, tmp2, 53); ++ ldi(tmp1, R0, 2047); ++ subl(res, tmp2, tmp1); ++} ++ ++void MacroAssembler::set64(Register d, jlong value) { ++ ++ int32_t lo = (int32_t) (value); ++ int32_t hi = (int32_t) ((value - lo) >> 32); ++ ++ int16_t lo_h16 = (lo - (int16_t)(lo))>>16; ++ int16_t lo_l16 = (int16_t)(lo); ++ int16_t hi_h16 = (hi - (int16_t)(hi))>>16; ++ int16_t hi_l16 = (int16_t)(hi); ++ ++ if ( is_simm16(value) ) { ++ ldi(d, R0, value); ++ } else if ( hi != 0 ) { ++ if ( is_simm16(hi) ) { ++ ldi(d, R0, hi); ++ } else { ++ ldih(d, R0, hi_h16); ++ if (hi_l16 != 0) ++ ldi(d, d, hi_l16); ++ } ++ slll(d, d, 32); ++ if ( lo != 0 ) { ++ if ( ((int)lo_h16 == -32768) && ((int)lo_l16 < 0)) { ++ // original val was in range 0x7FFF8000..0x7FFFFFFF ++ ldih(d, d, 0x4000); ++ ldih(d, d, 0x4000); ++ if (lo_l16 != 0) ++ ldi(d, d, lo_l16); ++ } else { ++ ldih(d, d, lo_h16); ++ if (lo_l16 != 0) ++ ldi(d, d, lo_l16); ++ } ++ } ++ } else if ( (hi == 0) && (lo != 0) ) { ++ if ( ((int)lo_h16 == -32768) && ((int)lo_l16 < 0)) { ++ // original val was in range 0x7FFF8000..0x7FFFFFFF ++ /* ldih(d, R0, lo_h16); ++ * ldi(d, d, lo_l16); ++ * addw(d, 0, d); */ ++ ldih(d, R0, 0x4000); ++ ldih(d, d, 0x4000); ++ if (lo_l16 != 0) ++ ldi(d, d, lo_l16); ++ } else { ++ ldih(d, R0, lo_h16); ++ if (lo_l16 != 0) ++ ldi(d, d, lo_l16); ++ } ++ } else { ++ tty->print_cr("value = 0x%x", value); ++ guarantee(false, "Not supported yet in set64!"); ++ } ++} ++ ++ ++int MacroAssembler::insts_for_set64(jlong value) { ++ ++ int count = 0; ++ ++ int32_t lo = (int32_t) (value); ++ int32_t hi = (int32_t) ((value - lo) >> 32); ++ ++ int16_t lo_h16 = (lo - (int16_t)(lo))>>16; ++ int16_t lo_l16 = (int16_t)(lo); ++ int16_t hi_h16 = (hi - (int16_t)(hi))>>16; ++ int16_t hi_l16 = (int16_t)(hi); ++ ++ if ( is_simm16(value) ) { ++ count += 1; ++ } else if ( hi != 0 ) { ++ if ( is_simm16(hi) ) { ++ count += 1; ++ } else { ++ count += 1; ++ if (hi_l16 != 0) ++ count += 1; ++ } ++ count += 1; ++ if ( lo != 0 ) { ++ if ( ((int)lo_h16 == -32768) && ((int)lo_l16 < 0)) { ++ count += 2; ++ if (lo_l16 != 0) ++ count += 1; ++ } else { ++ count += 1; ++ if (lo_l16 != 0) ++ count += 1; ++ } ++ } ++ } else if ( (hi == 0) && (lo != 0) ) { ++ if ( ((int)lo_h16 == -32768) && ((int)lo_l16 < 0)) { ++ count += 2; ++ if (lo_l16 != 0) ++ count += 1; ++ } else { ++ count += 1; ++ if (lo_l16 != 0) ++ count += 1; ++ } ++ } else { ++ guarantee(false, "Not supported yet in insts_for_set64!"); ++ } ++ ++ return count; ++} ++ ++ ++void MacroAssembler::patchable_set48(Register d, jlong value) { ++//TODO: optimize it ++ li48(d, value); ++} ++ ++void MacroAssembler::set_narrow_klass(Register dst, Klass* k) { ++ assert(UseCompressedClassPointers, "should only be used for compressed header"); ++ assert(oop_recorder() != NULL, "this assembler needs an OopRecorder"); ++ ++ int klass_index = oop_recorder()->find_index(k); ++ RelocationHolder rspec = metadata_Relocation::spec(klass_index); ++ long narrowKlass = (long)Klass::encode_klass(k); ++ ++ relocate(rspec, Assembler::narrow_oop_operand); ++ patchable_set48(dst, narrowKlass); ++} ++ ++ ++void MacroAssembler::set_narrow_oop(Register dst, jobject obj) { ++ assert(UseCompressedOops, "should only be used for compressed header"); ++ assert(oop_recorder() != NULL, "this assembler needs an OopRecorder"); ++ ++ int oop_index = oop_recorder()->find_index(obj); ++ RelocationHolder rspec = oop_Relocation::spec(oop_index); ++ ++ relocate(rspec, Assembler::narrow_oop_operand); ++ patchable_set48(dst, oop_index); ++} ++ ++void MacroAssembler::li64(Register rd, long imm) { ++ //Unimplemented(); ++ ++ int32_t lsb32 = (int32_t) (imm); ++ int32_t msb32 = (int32_t) ((imm - lsb32) >> 32); ++ int16_t msb_h = (msb32-(int16_t)msb32) >> 16; ++ int16_t msb_l = (int16_t)msb32; ++ int16_t lsb_h = (lsb32-(int16_t)lsb32) >> 16; ++ int16_t lsb_l = (int16_t)lsb32; ++ assert((int)lsb_h != (-32768), "wrong number in li64"); ++ ++ ldih(rd, R0, msb_h); ++ ldi(rd, rd, msb_l); ++ slll(rd, rd, 32); ++ ldih(rd, rd, lsb_h); ++ ldi(rd, rd, lsb_l); ++} ++ ++void MacroAssembler::li48(Register rd, long imm) { ++ assert(is_simm16(imm >> 32), "Not a 48-bit address"); ++ ++ int16_t msb_l, lsb_h, lsb_l; ++ NativeInstruction::imm48_split(imm, msb_l, lsb_h, lsb_l); ++ ++ ldi(rd, R0, msb_l); ++ slll(rd, rd, 32); ++ ldih(rd, rd, lsb_h); ++ ldi(rd, rd, lsb_l); ++} ++ ++void MacroAssembler::verify_oop(Register reg, const char* s) { ++ if (!VerifyOops) return; ++ const char * b = NULL; ++ stringStream ss; ++ ss.print("verify_oop: %s: %s", reg->name(), s); ++ b = code_string(ss.as_string()); ++ pushad(); ++ move(A1, reg); ++ li(A0, (long)b); ++ li(AT, (long)StubRoutines::verify_oop_subroutine_entry_address()); ++ ldl(T12, AT, 0); ++ call(T12); ++ popad(); ++} ++ ++ ++void MacroAssembler::verify_oop_addr(Address addr, const char* s) { ++ if (!VerifyOops) { ++ return; ++ } ++ // Pass register number to verify_oop_subroutine ++ const char * b = NULL; ++ stringStream ss; ++ ss.print("verify_oop_addr: %s", s); ++ b = code_string(ss.as_string()); ++ ++ st_ptr(T0, SP, - wordSize); ++ st_ptr(T1, SP, - 2*wordSize); ++ st_ptr(RA, SP, - 3*wordSize); ++ st_ptr(A0, SP, - 4*wordSize); ++ st_ptr(A1, SP, - 5*wordSize); ++ st_ptr(AT, SP, - 6*wordSize); ++ st_ptr(T12, SP, - 7*wordSize); ++ ld_ptr(A1, addr); // addr may use SP, so load from it before change SP ++ add_simm16(SP, SP, - 7 * wordSize); ++ ++ li(A0, (long)b); ++ // call indirectly to solve generation ordering problem ++ li(AT, (long)StubRoutines::verify_oop_subroutine_entry_address()); ++ ld_ptr(T12, AT, 0); ++ call(T12); ++ ld_ptr(T0, SP, 6* wordSize); ++ ld_ptr(T1, SP, 5* wordSize); ++ ld_ptr(RA, SP, 4* wordSize); ++ ld_ptr(A0, SP, 3* wordSize); ++ ld_ptr(A1, SP, 2* wordSize); ++ ld_ptr(AT, SP, 1* wordSize); ++ ld_ptr(T12, SP, 0* wordSize); ++ add_simm16(SP, SP, 7 * wordSize); ++} ++ ++// used registers : T0, T1 ++void MacroAssembler::verify_oop_subroutine() { ++ // RA: ra ++ // A0: char* error message ++ // A1: oop object to verify ++ ++ Label exit, error; ++ // increment counter ++ li(T0, (long)StubRoutines::verify_oop_count_addr()); ++ ldw(AT, T0, 0); ++ addl(AT, AT, 1); ++ stw(AT, T0, 0); ++ ++ // make sure object is 'reasonable' ++ beq(A1, exit); // if obj is NULL it is ok ++ ++ // Check if the oop is in the right area of memory ++ //const int oop_mask = Universe::verify_oop_mask(); ++ //const int oop_bits = Universe::verify_oop_bits(); ++ const uintptr_t oop_mask = Universe::verify_oop_mask(); ++ const uintptr_t oop_bits = Universe::verify_oop_bits(); ++ if (Assembler::is_simm8(oop_mask)) { ++ and_imm8(T0, A1, oop_mask); ++ } else { ++ li(AT, oop_mask); ++ and_reg(T0, A1, AT); ++ } ++ if (Assembler::is_simm8(oop_bits)) { ++ cmpeq(AT, T0, oop_bits); ++ beq(AT, offset(target(error))); ++ } else { ++ li(AT, oop_bits); ++ bne(T0, AT, error); ++ } ++ ++ // make sure klass is 'reasonable' ++ //add for compressedoops ++ reinit_heapbase(); ++ //add for compressedoops ++ load_klass(T0, A1); ++ beq(T0, error); // if klass is NULL it is broken ++ // return if everything seems ok ++ BIND(exit); ++ ++ ret(); ++ ++ // handle errors ++ BIND(error); ++ pushad(); ++ call(CAST_FROM_FN_PTR(address, MacroAssembler::debug), relocInfo::runtime_call_type); ++ popad(); ++ ret(); ++} ++ ++void MacroAssembler::verify_tlab(Register t1, Register t2) { ++#ifdef ASSERT ++ assert_different_registers(t1, t2, AT); ++ if (UseTLAB && VerifyOops) { ++ Label next, ok; ++ ++ get_thread(t1); ++ ++ ld_ptr(t2, t1, in_bytes(JavaThread::tlab_top_offset())); ++ ld_ptr(AT, t1, in_bytes(JavaThread::tlab_start_offset())); ++ cmpult(AT, t2, AT); ++ beq(AT, next); ++ ++ stop("assert(top >= start)"); ++ ++ BIND(next); ++ ld_ptr(AT, t1, in_bytes(JavaThread::tlab_end_offset())); ++ cmpult(AT, AT, t2); ++ beq(AT, ok); ++ ++ stop("assert(top <= end)"); ++ ++ BIND(ok); ++ ++ } ++#endif ++} ++ ++RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr, ++ Register tmp, ++ int offset) { ++ intptr_t value = *delayed_value_addr; ++ if (value != 0) ++ return RegisterOrConstant(value + offset); ++ AddressLiteral a(delayed_value_addr); ++ // load indirectly to solve generation ordering problem ++ // movptr(tmp, ExternalAddress((address) delayed_value_addr)); ++ // ld(tmp, a); ++ if (offset != 0) ++ add_simm16(tmp,tmp, offset); ++ ++ return RegisterOrConstant(tmp); ++} ++ ++void MacroAssembler::hswap(Register reg) { ++ if (UseSW8A) { ++ revbh(reg, reg); ++ sexth(reg, reg); ++ } else { ++ /* The following two version's are all OK! */ ++ srll(AT, reg, 8); ++ slll(reg, reg, 24); ++ addw(reg, reg, 0); ++ sral(reg, reg, 16); ++ or_ins(reg, reg, AT); ++ } ++} ++ ++void MacroAssembler::huswap(Register reg) { ++ if (UseSW8A) { ++ revbh(reg, reg); ++ } else { ++ /* The following two version's are all OK! */ ++ srll(AT, reg, 8); ++ slll(reg, reg, 8); ++ zapnot(reg, reg, 0x2); ++ or_ins(reg, reg, AT); ++ } ++} ++ ++// something funny to do this will only one more register AT ++// 32 bits ++void MacroAssembler::swap(Register reg) { ++ if (UseSW8A) { ++ revbw(reg, reg); ++ } else { ++ assert_different_registers(reg, AT); ++ zapnot (reg, reg, 0xf); ++ srll(AT, reg, 8); ++ slll(reg, reg, 24); ++ or_ins(reg, reg, AT); ++ srll(AT, AT, 16); ++ xor_ins(AT, AT, reg); ++ and_imm8(AT, AT, 0xff); ++ xor_ins(reg, reg, AT); ++ slll(AT, AT, 16); ++ xor_ins(reg, reg, AT); ++ addw(reg, reg, 0x0); ++ } ++} ++ ++void MacroAssembler::saveTRegisters(){ ++ Register regs[] = {T0, T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, A0, A1, A2, A3, A4, A5, GP, V0, AT}; ++ int len = sizeof(regs) / sizeof(regs[0]); ++ ++ subl(SP, SP, 176); ++ for (int i = 0; i < len; i++) { ++ stl(regs[i], SP, 8*i); ++ } ++} ++ ++void MacroAssembler::restoreTRegisters(){ ++ Register regs[] = {T0, T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, A0, A1, A2, A3, A4, A5, GP, V0, AT}; ++ int len = sizeof(regs) / sizeof(regs[0]); ++ ++ for (int i = (len - 1); i >= 0; i--) { ++ ldl(regs[i], SP, 8*i); ++ } ++ addl(SP, SP, 176); ++} ++ ++void MacroAssembler::cmpxchg32(Register x_reg, Address dest, Register c_reg) { ++ assert_different_registers(AT, GP, T10, x_reg, dest.base()); ++ assert_different_registers(AT, GP, T10, c_reg, dest.base()); ++ SizedScope sc(this, 60); ++ Label again, nequal, done; ++ if (UseSW8A) { ++ if (UseCAS) { ++ move(GP, x_reg); ++ if (dest.disp() != 0) { ++ ldi(AT, dest.base(), dest.disp()); ++ casw(c_reg, AT, GP); ++ } else { ++ casw(c_reg, dest.base(), GP); ++ } ++ cmpeq(AT, c_reg, GP); ++ move(c_reg, GP); ++ } else { ++ BIND(again); ++ lldw(AT, dest); ++ bne(AT, c_reg, nequal); ++ move(AT, x_reg); ++ lstw(AT, dest); ++ beq(AT, again); ++ beq(R0, done); ++ // not xchged ++ BIND(nequal); ++ move(c_reg, AT); ++ move(AT, R0); ++ BIND(done); ++ } ++ } else { ++ subl(SP, SP, 16); ++ stl(T10, SP, 0); ++ ++ BIND(again); ++ lldw(T10, dest.base(), dest.disp()); ++ cmpeq(GP, T10, c_reg); ++ wr_f(GP); ++ move(AT, x_reg); ++ align(8); ++ lstw(AT, dest.base(), dest.disp()); ++ rd_f(AT); ++ beq(GP, nequal); ++ beq(AT, again); ++ // not xchged ++ BIND(nequal); ++ move(c_reg, T10); ++ ++ ldl(T10, SP, 0); ++ addl(SP, SP, 16); ++ } ++} ++ ++void MacroAssembler::cmpxchg(Register x_reg, Address dest, Register c_reg) { ++ assert_different_registers(AT, GP, T10, x_reg, dest.base()); ++ assert_different_registers(AT, GP, T10, c_reg, dest.base()); ++ SizedScope sc(this, 60); ++ Label again, nequal, done; ++ if (UseSW8A) { ++ if (UseCAS) { ++ move(GP, x_reg); ++ if (dest.disp() != 0) { ++ ldi(AT, dest.base(), dest.disp()); ++ casl(c_reg, AT, GP); ++ } else { ++ casl(c_reg, dest.base(), GP); ++ } ++ cmpeq(AT, c_reg, GP); ++ move(c_reg, GP); ++ } else { ++ BIND(again); ++ lldl(AT, dest); ++ bne(AT, c_reg, nequal); ++ move(AT, x_reg); ++ lstl(AT, dest); ++ beq(AT, again); ++ beq(R0, done); ++ // not xchged ++ BIND(nequal); ++ move(c_reg, AT); ++ move(AT, R0); ++ BIND(done); ++ } ++ } else { ++ subl(SP, SP, 16); ++ stl(T10, SP, 0); ++ ++ BIND(again); ++ lldl(T10, dest.base(), dest.disp()); ++ cmpeq(GP, T10, c_reg); ++ wr_f(GP); ++ move(AT, x_reg); ++ align(8); ++ lstl(AT, dest.base(), dest.disp()); ++ rd_f(AT); ++ beq(GP, nequal); ++ beq(AT, again); ++ // not xchged ++ BIND(nequal); ++ move(c_reg, T10); ++ ++ ldl(T10, SP, 0); ++ addl(SP, SP, 16); ++ } ++} ++ ++// be sure the three register is different ++void MacroAssembler::rem_s(FloatRegister fd, FloatRegister fs, FloatRegister ft, FloatRegister tmp) { ++ assert_different_registers(tmp, fs, ft); ++ div_s(tmp, fs, ft); ++ trunc_l_s(tmp, tmp); ++ fcvtS2L(tmp, tmp); ++ mul_s(tmp, tmp, ft); ++ sub_s(fd, fs, tmp); ++} ++ ++// be sure the three register is different ++void MacroAssembler::rem_d(FloatRegister fd, FloatRegister fs, FloatRegister ft, FloatRegister tmp) { ++ assert_different_registers(tmp, fs, ft); ++ div_d(tmp, fs, ft); ++ trunc_l_d(tmp, tmp); ++ fcvtD2L(tmp, tmp); ++ mul_d(tmp, tmp, ft); ++ sub_d(fd, fs, tmp); ++} ++ ++// Fast_Lock and Fast_Unlock used by C2 ++ ++// Because the transitions from emitted code to the runtime ++// monitorenter/exit helper stubs are so slow it's critical that ++// we inline both the stack-locking fast-path and the inflated fast path. ++// ++// See also: cmpFastLock and cmpFastUnlock. ++// ++// What follows is a specialized inline transliteration of the code ++// in slow_enter() and slow_exit(). If we're concerned about I$ bloat ++// another option would be to emit TrySlowEnter and TrySlowExit methods ++// at startup-time. These methods would accept arguments as ++// (Obj, Self, box, Scratch) and return success-failure ++// indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply ++// marshal the arguments and emit calls to TrySlowEnter and TrySlowExit. ++// In practice, however, the # of lock sites is bounded and is usually small. ++// Besides the call overhead, TrySlowEnter and TrySlowExit might suffer ++// if the processor uses simple bimodal branch predictors keyed by EIP ++// Since the helper routines would be called from multiple synchronization ++// sites. ++// ++// An even better approach would be write "MonitorEnter()" and "MonitorExit()" ++// in java - using j.u.c and unsafe - and just bind the lock and unlock sites ++// to those specialized methods. That'd give us a mostly platform-independent ++// implementation that the JITs could optimize and inline at their pleasure. ++// Done correctly, the only time we'd need to cross to native could would be ++// to park() or unpark() threads. We'd also need a few more unsafe operators ++// to (a) prevent compiler-JIT reordering of non-volatile accesses, and ++// (b) explicit barriers or fence operations. ++// ++// TODO: ++// ++// * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr). ++// This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals. ++// Given TLAB allocation, Self is usually manifested in a register, so passing it into ++// the lock operators would typically be faster than reifying Self. ++// ++// * Ideally I'd define the primitives as: ++// fast_lock (nax Obj, nax box, tmp, nax scr) where box, tmp and scr are KILLED. ++// fast_unlock (nax Obj, box, nax tmp) where box and tmp are KILLED ++// Unfortunately ADLC bugs prevent us from expressing the ideal form. ++// Instead, we're stuck with a rather awkward and brittle register assignments below. ++// Furthermore the register assignments are overconstrained, possibly resulting in ++// sub-optimal code near the synchronization site. ++// ++// * Eliminate the sp-proximity tests and just use "== Self" tests instead. ++// Alternately, use a better sp-proximity test. ++// ++// * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value. ++// Either one is sufficient to uniquely identify a thread. ++// TODO: eliminate use of sp in _owner and use get_thread(tr) instead. ++// ++// * Intrinsify notify() and notifyAll() for the common cases where the ++// object is locked by the calling thread but the waitlist is empty. ++// avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll(). ++// ++// * use jccb and jmpb instead of jcc and jmp to improve code density. ++// But beware of excessive branch density on AMD Opterons. ++// ++// * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success ++// or failure of the fast-path. If the fast-path fails then we pass ++// control to the slow-path, typically in C. In Fast_Lock and ++// Fast_Unlock we often branch to DONE_LABEL, just to find that C2 ++// will emit a conditional branch immediately after the node. ++// So we have branches to branches and lots of ICC.ZF games. ++// Instead, it might be better to have C2 pass a "FailureLabel" ++// into Fast_Lock and Fast_Unlock. In the case of success, control ++// will drop through the node. ICC.ZF is undefined at exit. ++// In the case of failure, the node will branch directly to the ++// FailureLabel ++ ++ ++// obj: object to lock ++// box: on-stack box address (displaced header location) - KILLED ++// tmp: tmp -- KILLED ++// scr: tmp -- KILLED ++void MacroAssembler::fast_lock(Register objReg, Register boxReg, Register tmpReg, Register scrReg) { ++ ++ // Ensure the register assignents are disjoint ++ guarantee (objReg != boxReg, "") ; ++ guarantee (objReg != tmpReg, "") ; ++ guarantee (objReg != scrReg, "") ; ++ guarantee (boxReg != tmpReg, "") ; ++ guarantee (boxReg != scrReg, "") ; ++ ++ ++ block_comment("FastLock"); ++ if (PrintBiasedLockingStatistics) { ++ push(tmpReg); ++ atomic_inc32((address)BiasedLocking::total_entry_count_addr(), 1, AT, tmpReg); ++ pop(tmpReg); ++ } ++ ++ if (EmitSync & 1) { ++ move(AT, 0x0); ++ return; ++ } else ++ if (EmitSync & 2) { ++ Label DONE_LABEL ; ++ if (UseBiasedLocking) { ++ // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument. ++ biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL); ++ } ++ ++ ldl(tmpReg, Address(objReg, 0)) ; // fetch markword ++ or_ins(tmpReg, tmpReg, 0x1); ++ stl(tmpReg, Address(boxReg, 0)); // Anticipate successful CAS ++ ++ cmpxchg(boxReg, Address(objReg, 0), tmpReg); // Updates tmpReg ++ bne(AT, DONE_LABEL); ++ ++ // Recursive locking ++ subl(tmpReg, tmpReg, SP); ++ ++ if (Assembler::is_simm16(7 - os::vm_page_size())) { ++ ldi(AT, R0, (7 - os::vm_page_size() )); ++ } else { ++ li(AT, (7 - os::vm_page_size() )); ++ } ++ and_reg(tmpReg, tmpReg, AT); ++ stl(tmpReg, Address(boxReg, 0)); ++ BIND(DONE_LABEL) ; ++ } else { ++ // Possible cases that we'll encounter in fast_lock ++ // ------------------------------------------------ ++ // * Inflated ++ // -- unlocked ++ // -- Locked ++ // = by self ++ // = by other ++ // * biased ++ // -- by Self ++ // -- by other ++ // * neutral ++ // * stack-locked ++ // -- by self ++ // = sp-proximity test hits ++ // = sp-proximity test generates false-negative ++ // -- by other ++ // ++ ++ Label IsInflated, DONE_LABEL, PopDone ; ++ ++ // TODO: optimize away redundant LDs of obj->mark and improve the markword triage ++ // order to reduce the number of conditional branches in the most common cases. ++ // Beware -- there's a subtle invariant that fetch of the markword ++ // at [FETCH], below, will never observe a biased encoding (*101b). ++ // If this invariant is not held we risk exclusion (safety) failure. ++ if (UseBiasedLocking && !UseOptoBiasInlining) { ++ biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL); ++ } ++ ++ ldl(tmpReg, Address(objReg, 0)) ; //Fetch the markword of the object. ++ and_imm8(AT, tmpReg, markOopDesc::monitor_value); ++ bne(AT, IsInflated); // inflated vs stack-locked|neutral|bias ++ ++ // Attempt stack-locking ... ++ or_ins(tmpReg, tmpReg, markOopDesc::unlocked_value); ++ stl(tmpReg, Address(boxReg, 0)); // Anticipate successful CAS ++ //if (os::is_MP()) { ++ // memb(); ++ //} ++ ++ cmpxchg(boxReg, Address(objReg, 0), tmpReg); // Updates tmpReg ++ //AT == 1: unlocked ++ ++ if (PrintBiasedLockingStatistics) { ++ Label L; ++ beq(AT, L); ++ push(T0); ++ push(T1); ++ atomic_inc32((address)BiasedLocking::fast_path_entry_count_addr(), 1, T0, T1); ++ pop(T1); ++ pop(T0); ++ BIND(L); ++ } ++ bne(AT, DONE_LABEL); ++ ++ // Recursive locking ++ // The object is stack-locked: markword contains stack pointer to BasicLock. ++ // Locked by current thread if difference with current SP is less than one page. ++ subl(tmpReg, tmpReg, SP); ++ if (Assembler::is_simm16(7 - os::vm_page_size())) { ++ ldi(AT, R0, (7 - os::vm_page_size())); ++ } else { ++ li(AT, 7 - os::vm_page_size() ); ++ } ++ and_reg(tmpReg, tmpReg, AT); ++ stl(tmpReg, Address(boxReg, 0)); ++ if (PrintBiasedLockingStatistics) { ++ Label L; ++ // tmpReg == 0 => BiasedLocking::_fast_path_entry_count++ ++ bne(tmpReg, L); ++ push(T0); ++ push(T1); ++ atomic_inc32((address)BiasedLocking::fast_path_entry_count_addr(), 1, T0, T1); ++ pop(T1); ++ pop(T0); ++ BIND(L); ++ } ++ cmpult(AT, tmpReg, 1); ++ beq(R0, DONE_LABEL) ; ++ ++ BIND(IsInflated) ; ++ // The object's monitor m is unlocked iff m->owner == NULL, ++ // otherwise m->owner may contain a thread or a stack address. ++ ++ // TODO: someday avoid the ST-before-CAS penalty by ++ // relocating (deferring) the following ST. ++ // We should also think about trying a CAS without having ++ // fetched _owner. If the CAS is successful we may ++ // avoid an RTO->RTS upgrade on the $line. ++ // Without cast to int32_t a movptr will destroy r10 which is typically obj ++ if (Assembler::is_simm16((int32_t)intptr_t(markOopDesc::unused_mark()))) { ++ ldi(AT, R0, (int32_t)intptr_t(markOopDesc::unused_mark())); ++ } else { ++ li(AT, (int32_t)intptr_t(markOopDesc::unused_mark())); ++ } ++ stl(AT, Address(boxReg, 0)); ++ ++ move(boxReg, tmpReg) ; ++ ldl(tmpReg, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; ++ // if (m->owner != 0) => AT = 0, goto slow path. ++ move(AT, R0); ++ bne(tmpReg, DONE_LABEL); ++ ++ // It's inflated and appears unlocke ++ //if (os::is_MP()) { ++ // memb(); ++ //} ++ cmpxchg(S2thread, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), tmpReg) ; ++ // Intentional fall-through into DONE_LABEL ... ++ ++ ++ // DONE_LABEL is a hot target - we'd really like to place it at the ++ // start of cache line by padding with NOPs. ++ // See the AMD and Intel software optimization manuals for the ++ // most efficient "long" NOP encodings. ++ // Unfortunately none of our alignment mechanisms suffice. ++ BIND(DONE_LABEL); ++ ++ // At DONE_LABEL the AT is set as follows ... ++ // Fast_Unlock uses the same protocol. ++ // AT == 1 -> Success ++ // AT == 0 -> Failure - force control through the slow-path ++ ++ // Avoid branch-to-branch on AMD processors ++ // This appears to be superstition. ++ if (EmitSync & 32) nop(); ++ ++ } ++} ++ ++// obj: object to unlock ++// box: box address (displaced header location), killed. ++// tmp: killed tmp; cannot be obj nor box. ++// ++// Some commentary on balanced locking: ++// ++// Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites. ++// Methods that don't have provably balanced locking are forced to run in the ++// interpreter - such methods won't be compiled to use fast_lock and fast_unlock. ++// The interpreter provides two properties: ++// I1: At return-time the interpreter automatically and quietly unlocks any ++// objects acquired the current activation (frame). Recall that the ++// interpreter maintains an on-stack list of locks currently held by ++// a frame. ++// I2: If a method attempts to unlock an object that is not held by the ++// the frame the interpreter throws IMSX. ++// ++// Lets say A(), which has provably balanced locking, acquires O and then calls B(). ++// B() doesn't have provably balanced locking so it runs in the interpreter. ++// Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O ++// is still locked by A(). ++// ++// The only other source of unbalanced locking would be JNI. The "Java Native Interface: ++// Programmer's Guide and Specification" claims that an object locked by jni_monitorenter ++// should not be unlocked by "normal" java-level locking and vice-versa. The specification ++// doesn't specify what will occur if a program engages in such mixed-mode locking, however. ++ ++void MacroAssembler::fast_unlock(Register objReg, Register boxReg, Register tmpReg) { ++ ++ guarantee (objReg != boxReg, "") ; ++ guarantee (objReg != tmpReg, "") ; ++ guarantee (boxReg != tmpReg, "") ; ++ ++ block_comment("FastUnlock"); ++ ++ ++ if (EmitSync & 4) { ++ // Disable - inhibit all inlining. Force control through the slow-path ++ move(AT, 0x0); ++ return; ++ } else ++ if (EmitSync & 8) { ++ Label DONE_LABEL ; ++ if (UseBiasedLocking) { ++ biased_locking_exit(objReg, tmpReg, DONE_LABEL); ++ } ++ // classic stack-locking code ... ++ ldl(tmpReg, Address(boxReg, 0)) ; ++ move(AT, 0x1); // should set 0x1 before branch ++ beq(tmpReg, DONE_LABEL) ; ++ ++ cmpxchg(tmpReg, Address(objReg, 0), boxReg); // Uses EAX which is box ++ BIND(DONE_LABEL); ++ } else { ++ Label DONE_LABEL, Stacked, CheckSucc, Inflated ; ++ ++ // Critically, the biased locking test must have precedence over ++ // and appear before the (box->dhw == 0) recursive stack-lock test. ++ if (UseBiasedLocking && !UseOptoBiasInlining) { ++ biased_locking_exit(objReg, tmpReg, DONE_LABEL); ++ } ++ ++ ldl(GP, Address(boxReg, 0)) ; // Examine the displaced header ++ addl(AT, R0, 0x1); ++ beq(GP, DONE_LABEL) ; // 0 indicates recursive stack-lock ++ ++ ldl(tmpReg, Address(objReg, 0)) ; // Examine the object's markword ++ and_imm8(AT, tmpReg, markOopDesc::monitor_value) ; // Inflated? ++ beq(AT, Stacked) ; // Inflated? ++ ++ BIND(Inflated) ; ++ // It's inflated. ++ // Despite our balanced locking property we still check that m->_owner == Self ++ // as java routines or native JNI code called by this thread might ++ // have released the lock. ++ // Refer to the comments in synchronizer.cpp for how we might encode extra ++ // state in _succ so we can avoid fetching EntryList|cxq. ++ // ++ // I'd like to add more cases in fast_lock() and fast_unlock() -- ++ // such as recursive enter and exit -- but we have to be wary of ++ // I$ bloat, T$ effects and BP$ effects. ++ // ++ // If there's no contention try a 1-0 exit. That is, exit without ++ // a costly MEMBAR or CAS. See synchronizer.cpp for details on how ++ // we detect and recover from the race that the 1-0 exit admits. ++ // ++ // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier ++ // before it STs null into _owner, releasing the lock. Updates ++ // to data protected by the critical section must be visible before ++ // we drop the lock (and thus before any other thread could acquire ++ // the lock and observe the fields protected by the lock). ++ // It's inflated ++ ldl(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; ++ xor_ins(boxReg, boxReg, S2thread); ++ ++ ldl(AT, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ; ++ or_ins(boxReg, boxReg, AT); ++ ++ move(AT, R0); ++ bne(boxReg, DONE_LABEL); ++ ++ ldl(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ; ++ ldl(AT, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ; ++ or_ins(boxReg, boxReg, AT); ++ ++ move(AT, R0); ++ bne(boxReg, DONE_LABEL); ++ ++ memb(); ++ stl(R0, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; ++ move(AT, 0x1); ++ beq(R0, DONE_LABEL); ++ ++ BIND (Stacked); ++ ldl(tmpReg, Address(boxReg, 0)) ; ++ //if (os::is_MP()) { memb(); } ++ cmpxchg(tmpReg, Address(objReg, 0), boxReg); ++ ++ if (EmitSync & 65536) { ++ BIND (CheckSucc); ++ } ++ ++ BIND(DONE_LABEL); ++ ++ // Avoid branch to branch on AMD processors ++ if (EmitSync & 32768) { nop(); } ++ } ++} ++ ++void MacroAssembler::align(int modulus) { ++ while (offset() % modulus != 0) nop(); ++} ++ ++void MacroAssembler::verify_FPU(int stack_depth, const char* s) { ++ //Unimplemented(); ++} ++ ++Register caller_saved_registers[] = {V0, T0, T1, T2, T3, T4, T5, T6, T7, FP, A0, A1, A2, A3, A4, A5, T8, T9, T10, T11, RA, T12, AT, GP}; ++Register caller_saved_registers_except_RA[] = {V0, T0, T1, T2, T3, T4, T5, T6, T7, FP, A0, A1, A2, A3, A4, A5, T8, T9, T10, T11, T12, AT, GP}; ++ ++// In SW64, F0~23 are all caller-saved registers ++FloatRegister caller_saved_fpu_registers[] = {F0, F16, F17}; ++ ++//We preserve all caller-saved register ++void MacroAssembler::pushad(){ ++ int i; ++ ++ // Fixed-point registers ++ int len = sizeof(caller_saved_registers) / sizeof(caller_saved_registers[0]); ++ add_simm16(SP, SP, -1 * len * wordSize); ++ for (i = 0; i < len; i++) ++ { ++ stl(caller_saved_registers[i], SP, (len - i - 1) * wordSize); ++ } ++ ++ /* Floating-point registers */ ++ len = sizeof(caller_saved_fpu_registers) / sizeof(caller_saved_fpu_registers[0]); ++ add_simm16(SP, SP, -1 * len * wordSize); ++ for (i = 0; i < len; i++) ++ { ++ fstd(caller_saved_fpu_registers[i], SP, (len - i - 1) * wordSize); ++ } ++}; ++ ++void MacroAssembler::popad(){ ++ int i; ++ ++ /* Floating-point registers */ ++ int len = sizeof(caller_saved_fpu_registers) / sizeof(caller_saved_fpu_registers[0]); ++ for (i = 0; i < len; i++) ++ { ++ fldd(caller_saved_fpu_registers[i], SP, (len - i - 1) * wordSize); ++ } ++ add_simm16(SP, SP, len * wordSize); ++ ++ /* Fixed-point registers */ ++ len = sizeof(caller_saved_registers) / sizeof(caller_saved_registers[0]); ++ for (i = 0; i < len; i++) ++ { ++ ldl(caller_saved_registers[i], SP, (len - i - 1) * wordSize); ++ } ++ add_simm16(SP, SP, len * wordSize); ++}; ++ ++// We preserve all caller-saved register except V0 ++void MacroAssembler::pushad_except_RA() { ++ int i; ++ ++ // Fixed-point registers ++ int len = sizeof(caller_saved_registers_except_RA) / sizeof(caller_saved_registers_except_RA[0]); ++ add_simm16(SP, SP, -1 * len * wordSize); ++ for (i = 0; i < len; i++) { ++ stl(caller_saved_registers_except_RA[i], SP, (len - i - 1) * wordSize); ++ } ++ ++ // Floating-point registers ++ len = sizeof(caller_saved_fpu_registers) / sizeof(caller_saved_fpu_registers[0]); ++ add_simm16(SP, SP, -1 * len * wordSize); ++ for (i = 0; i < len; i++) { ++ fstd(caller_saved_fpu_registers[i], SP, (len - i - 1) * wordSize); ++ } ++} ++ ++void MacroAssembler::popad_except_RA() { ++ int i; ++ ++ // Floating-point registers ++ int len = sizeof(caller_saved_fpu_registers) / sizeof(caller_saved_fpu_registers[0]); ++ for (i = 0; i < len; i++) { ++ fldd(caller_saved_fpu_registers[i], SP, (len - i - 1) * wordSize); ++ } ++ add_simm16(SP, SP, len * wordSize); ++ ++ // Fixed-point registers ++ len = sizeof(caller_saved_registers_except_RA) / sizeof(caller_saved_registers_except_RA[0]); ++ for (i = 0; i < len; i++) { ++ ldl(caller_saved_registers_except_RA[i], SP, (len - i - 1) * wordSize); ++ } ++ add_simm16(SP, SP, len * wordSize); ++} ++ ++void MacroAssembler::push2(Register reg1, Register reg2) { ++ subl(SP, SP, 16); ++ stl(reg2, SP, 0); ++ stl(reg1, SP, 8); ++} ++ ++void MacroAssembler::pop(Register reg) { ++ if (UseSW8A){ ++ ldl_a(reg, 8, SP); ++ }else { ++ ldl(reg, SP, 0); addl(SP, SP, 8); ++ } ++} ++ ++void MacroAssembler::pop(FloatRegister reg) { ++ if (UseSW8A){ ++ fldd_a(reg, 8, SP); ++ }else { ++ fldd(reg, SP, 0); addl(SP, SP, 8); ++ } ++} ++ ++void MacroAssembler::pop2(Register reg1, Register reg2) { ++ if (UseSW8A){ ++ ldl_a(reg1, 8, SP); ++ ldl_a(reg2, 8, SP); ++ } else { ++ ldl(reg1, SP, 0); ++ ldl(reg2, SP, 8); ++ addl(SP, SP, 16); ++ } ++} ++ ++//for UseCompressedOops Option ++void MacroAssembler::load_klass(Register dst, Register src) { ++ if(UseCompressedClassPointers){ ++ ldw_unsigned(dst, Address(src, oopDesc::klass_offset_in_bytes())); ++ decode_klass_not_null(dst); ++ } else ++ ldl(dst, src, oopDesc::klass_offset_in_bytes()); ++} ++ ++void MacroAssembler::store_klass(Register dst, Register src) { ++ if(UseCompressedClassPointers){ ++ encode_klass_not_null(src); ++ stw(src, dst, oopDesc::klass_offset_in_bytes()); ++ } else { ++ stl(src, dst, oopDesc::klass_offset_in_bytes()); ++ } ++} ++ ++void MacroAssembler::load_prototype_header(Register dst, Register src) { ++ load_klass(dst, src); ++ ldl(dst, Address(dst, Klass::prototype_header_offset())); ++} ++ ++void MacroAssembler::store_klass_gap(Register dst, Register src) { ++ if (UseCompressedClassPointers) { ++ stw(src, dst, oopDesc::klass_gap_offset_in_bytes()); ++ } ++} ++ ++void MacroAssembler::load_heap_oop(Register dst, Address src) { ++ if(UseCompressedOops){ ++ ldw_unsigned(dst, src); ++ decode_heap_oop(dst); ++ } else { ++ ldl(dst, src); ++ } ++} ++ ++void MacroAssembler::store_heap_oop(Address dst, Register src){ ++ if(UseCompressedOops){ ++ assert(!dst.uses(src), "not enough registers"); ++ encode_heap_oop(src); ++ stw(src, dst); ++ } else { ++ stl(src, dst); ++ } ++} ++ ++void MacroAssembler::store_heap_oop_null(Address dst){ ++ if(UseCompressedOops){ ++ stw(R0, dst); ++ } else { ++ stl(R0, dst); ++ } ++} ++ ++#ifdef ASSERT ++void MacroAssembler::verify_heapbase(const char* msg) { ++ assert (UseCompressedOops || UseCompressedClassPointers, "should be compressed"); ++ assert (Universe::heap() != NULL, "java heap should be initialized"); ++} ++#endif ++ ++ ++// Algorithm must match oop.inline.hpp encode_heap_oop. ++void MacroAssembler::encode_heap_oop(Register r) { ++#ifdef ASSERT ++ verify_heapbase("MacroAssembler::encode_heap_oop:heap base corrupted?"); ++#endif ++ verify_oop(r, "broken oop in encode_heap_oop"); ++ if (Universe::narrow_oop_base() == NULL) { ++ if (Universe::narrow_oop_shift() != 0) { ++ assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); ++ shr(r, LogMinObjAlignmentInBytes); ++ } ++ return; ++ } ++ ++ seleq(r, S5_heapbase, r, r); ++ subl(r, r, S5_heapbase); ++ if (Universe::narrow_oop_shift() != 0) { ++ assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); ++ shr(r, LogMinObjAlignmentInBytes); ++ } ++} ++ ++void MacroAssembler::encode_heap_oop(Register dst, Register src) { ++#ifdef ASSERT ++ verify_heapbase("MacroAssembler::encode_heap_oop:heap base corrupted?"); ++#endif ++ verify_oop(src, "broken oop in encode_heap_oop"); ++ if (Universe::narrow_oop_base() == NULL) { ++ if (Universe::narrow_oop_shift() != 0) { ++ assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); ++ srll(dst, src, LogMinObjAlignmentInBytes); ++ } else { ++ if (dst != src) move(dst, src); ++ } ++ } else { ++ if (dst == src) { ++ seleq(dst, S5_heapbase, dst, dst); ++ subl(dst, dst, S5_heapbase); ++ if (Universe::narrow_oop_shift() != 0) { ++ assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); ++ shr(dst, LogMinObjAlignmentInBytes); ++ } ++ } else { ++ subl(dst, src, S5_heapbase); ++ if (Universe::narrow_oop_shift() != 0) { ++ assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); ++ shr(dst, LogMinObjAlignmentInBytes); ++ } ++ seleq(src, R0, dst, dst); ++ } ++ } ++} ++ ++void MacroAssembler::encode_heap_oop_not_null(Register r) { ++ assert (UseCompressedOops, "should be compressed"); ++#ifdef ASSERT ++ if (CheckCompressedOops) { ++ Label ok; ++ bne(r, ok); ++ stop("null oop passed to encode_heap_oop_not_null"); ++ BIND(ok); ++ } ++#endif ++ verify_oop(r, "broken oop in encode_heap_oop_not_null"); ++ if (Universe::narrow_oop_base() != NULL) { ++ subl(r, r, S5_heapbase); ++ } ++ if (Universe::narrow_oop_shift() != 0) { ++ assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); ++ shr(r, LogMinObjAlignmentInBytes); ++ } ++ ++} ++ ++void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) { ++ assert (UseCompressedOops, "should be compressed"); ++#ifdef ASSERT ++ if (CheckCompressedOops) { ++ Label ok; ++ bne(src, ok); ++ stop("null oop passed to encode_heap_oop_not_null2"); ++ BIND(ok); ++ } ++#endif ++ verify_oop(src, "broken oop in encode_heap_oop_not_null2"); ++ ++ if (Universe::narrow_oop_base() != NULL) { ++ subl(dst, src, S5_heapbase); ++ if (Universe::narrow_oop_shift() != 0) { ++ assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); ++ shr(dst, LogMinObjAlignmentInBytes); ++ } ++ } else { ++ if (Universe::narrow_oop_shift() != 0) { ++ assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); ++ srll(dst, src, LogMinObjAlignmentInBytes); ++ } else { ++ if (dst != src) move(dst, src); ++ } ++ } ++} ++ ++void MacroAssembler::decode_heap_oop(Register r) { ++#ifdef ASSERT ++ verify_heapbase("MacroAssembler::decode_heap_oop corrupted?"); ++#endif ++ if (Universe::narrow_oop_base() == NULL) { ++ if (Universe::narrow_oop_shift() != 0) { ++ assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); ++ shl(r, LogMinObjAlignmentInBytes); ++ } ++ } else { ++ move(AT, r); ++ if (Universe::narrow_oop_shift() != 0) { ++ assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); ++ shl(r, LogMinObjAlignmentInBytes); ++ } ++ addl(r, r, S5_heapbase); ++ seleq(AT, R0, r, r); ++ } ++ verify_oop(r, "broken oop in decode_heap_oop"); ++} ++ ++void MacroAssembler::decode_heap_oop(Register dst, Register src) { ++#ifdef ASSERT ++ verify_heapbase("MacroAssembler::decode_heap_oop corrupted?"); ++#endif ++ if (Universe::narrow_oop_base() == NULL) { ++ if (Universe::narrow_oop_shift() != 0) { ++ assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); ++ if (dst != src) nop(); // DON'T DELETE THIS GUY. ++ slll(dst, src, LogMinObjAlignmentInBytes); ++ } else { ++ if (dst != src) move(dst, src); ++ } ++ } else { ++ if (dst == src) { ++ move(AT, dst); ++ if (Universe::narrow_oop_shift() != 0) { ++ assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); ++ shl(dst, LogMinObjAlignmentInBytes); ++ } ++ addl(dst, dst, S5_heapbase); ++ seleq(AT, R0, dst, dst); ++ } else { ++ if (Universe::narrow_oop_shift() != 0) { ++ assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); ++ slll(dst, src, LogMinObjAlignmentInBytes); ++ addl(dst, dst, S5_heapbase); ++ } else { ++ addl(dst, src, S5_heapbase); ++ } ++ seleq(src, R0, dst, dst); ++ } ++ } ++ verify_oop(dst, "broken oop in decode_heap_oop"); ++} ++ ++void MacroAssembler::decode_heap_oop_not_null(Register r) { ++ // Note: it will change flags ++ assert (UseCompressedOops, "should only be used for compressed headers"); ++ assert (Universe::heap() != NULL, "java heap should be initialized"); ++ // Cannot assert, unverified entry point counts instructions (see .ad file) ++ // vtableStubs also counts instructions in pd_code_size_limit. ++ // Also do not verify_oop as this is called by verify_oop. ++ if (Universe::narrow_oop_shift() != 0) { ++ assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); ++ shl(r, LogMinObjAlignmentInBytes); ++ if (Universe::narrow_oop_base() != NULL) { ++ addl(r, r, S5_heapbase); ++ } ++ } else { ++ assert (Universe::narrow_oop_base() == NULL, "sanity"); ++ } ++} ++ ++void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) { ++ assert (UseCompressedOops, "should only be used for compressed headers"); ++ assert (Universe::heap() != NULL, "java heap should be initialized"); ++ ++ // Cannot assert, unverified entry point counts instructions (see .ad file) ++ // vtableStubs also counts instructions in pd_code_size_limit. ++ // Also do not verify_oop as this is called by verify_oop. ++ //lea(dst, Address(S5_heapbase, src, Address::times_8, 0)); ++ if (Universe::narrow_oop_shift() != 0) { ++ assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); ++ if (LogMinObjAlignmentInBytes == Address::times_8) { ++ slll(dst, src, LogMinObjAlignmentInBytes); ++ addl(dst, dst, S5_heapbase); ++ } else { ++ slll(dst, src, LogMinObjAlignmentInBytes); ++ if (Universe::narrow_oop_base() != NULL) { ++ addl(dst, dst, S5_heapbase); ++ } ++ } ++ } else { ++ assert (Universe::narrow_oop_base() == NULL, "sanity"); ++ if (dst != src) { ++ move(dst, src); ++ } ++ } ++} ++ ++// Compare char[] arrays aligned to 4 bytes. ++void MacroAssembler::char_arrays_equals(Register ary1, Register ary2, ++ Register limit, Register result, ++ Register chr1, Register chr2, Label& Ldone) { ++ ++ assert_different_registers(GP, ary1, ary2, limit, result); ++ ++ Label Lvector, Lloop, Ldone_before1, Ldone_before2, Lexit; ++ assert(chr1 == result, "should be the same"); ++ ++ // Note: limit contains number of bytes (2*char_elements) != 0. ++ and_imm8(chr1, limit, 0x2); // trailing character ? ++ beq(chr1, Lvector); ++ ++ // compare the trailing char ++ subl(limit, limit, sizeof(jchar)); ++ addl(chr1, ary1, limit); ++ ldhu(chr1, chr1, 0); ++ addl(chr2, ary2, limit); ++ ldhu(chr2, chr2, 0); ++ cmpeq(GP, chr1, chr2); ++ beq(GP, Ldone_before1); ++ ++ // only one char ? ++ beq(limit, Ldone_before2); ++ ++ // word by word compare, dont't need alignment check ++ BIND(Lvector); ++ // Shift ary1 and ary2 to the end of the arrays, negate limit ++ addl(ary1, ary1, limit); ++ addl(ary2, ary2, limit); ++ subl(limit, R0, limit); ++ ++ BIND(Lloop);// YJ20111018 ++ addl(chr1, ary1, limit); ++ ldw(chr1, chr1, 0); ++ zapnot(chr1, chr1, 0xf); ++ addl(chr2, ary2, limit); ++ ldw(chr2, chr2, 0); ++ zapnot(chr2, chr2, 0xf); ++ cmpeq(GP, chr1, chr2); ++ beq(GP, Ldone_before1); ++ addl(limit, limit, 2*sizeof(jchar)); ++ // annul LDUW if branch is not taken to prevent access past end of array ++ bne(limit, Lloop); ++ ++ beq(R0, Lexit); ++ ++ BIND(Ldone_before1); ++ or_ins(result, R0, 0); // not equal ++ beq(R0, Ldone); ++ ++ BIND(Ldone_before2); ++ or_ins(result, R0, 1); // zero-length arrays are equal ++ beq(R0, Ldone); ++ ++ BIND(Lexit); ++} ++ ++void MacroAssembler::encode_klass_not_null(Register r) { ++ if (Universe::narrow_klass_base() != NULL) { ++ assert(r != AT, "Encoding a klass in AT"); ++ set64(AT, (int64_t)Universe::narrow_klass_base()); ++ subl(r, r, AT); ++ } ++ if (Universe::narrow_klass_shift() != 0) { ++ assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); ++ shr(r, LogKlassAlignmentInBytes); ++ } ++} ++ ++void MacroAssembler::encode_klass_not_null(Register dst, Register src) { ++ if (dst == src) { ++ encode_klass_not_null(src); ++ } else { ++ if (Universe::narrow_klass_base() != NULL) { ++ set64(dst, (int64_t)Universe::narrow_klass_base()); ++ subl(dst, src, dst); ++ if (Universe::narrow_klass_shift() != 0) { ++ assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); ++ shr(dst, LogKlassAlignmentInBytes); ++ } ++ } else { ++ if (Universe::narrow_klass_shift() != 0) { ++ assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); ++ srll(dst, src, LogKlassAlignmentInBytes); ++ } else { ++ move(dst, src); ++ } ++ } ++ } ++} ++ ++// Function instr_size_for_decode_klass_not_null() counts the instructions ++// generated by decode_klass_not_null(register r) and reinit_heapbase(), ++// when (Universe::heap() != NULL). Hence, if the instructions they ++// generate change, then this method needs to be updated. ++int MacroAssembler::instr_size_for_decode_klass_not_null() { ++ assert (UseCompressedClassPointers, "only for compressed klass ptrs"); ++ if (Universe::narrow_klass_base() != NULL) { ++ // mov64 + addq + shlq? + mov64 (for reinit_heapbase()). ++ return (Universe::narrow_klass_shift() == 0 ? 4 * 9 : 4 * 10); ++ } else { ++ // longest load decode klass function, mov64, leaq ++ return (Universe::narrow_klass_shift() == 0 ? 4 * 0 : 4 * 1); ++ } ++} ++ ++void MacroAssembler::decode_klass_not_null(Register r) { ++ assert (UseCompressedClassPointers, "should only be used for compressed headers"); ++ assert(r != AT, "Decoding a klass in AT"); ++ // Cannot assert, unverified entry point counts instructions (see .ad file) ++ // vtableStubs also counts instructions in pd_code_size_limit. ++ // Also do not verify_oop as this is called by verify_oop. ++ if (Universe::narrow_klass_shift() != 0) { ++ assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); ++ shl(r, LogKlassAlignmentInBytes); ++ } ++ if (Universe::narrow_klass_base() != NULL) { ++ set64(AT, (int64_t)Universe::narrow_klass_base()); ++ addl(r, r, AT); ++ //Not neccessary for SW64 at all. ++ //reinit_heapbase(); ++ } ++} ++ ++void MacroAssembler::decode_klass_not_null(Register dst, Register src) { ++ assert (UseCompressedClassPointers, "should only be used for compressed headers"); ++ ++ if (dst == src) { ++ decode_klass_not_null(dst); ++ } else { ++ // Cannot assert, unverified entry point counts instructions (see .ad file) ++ // vtableStubs also counts instructions in pd_code_size_limit. ++ // Also do not verify_oop as this is called by verify_oop. ++ set64(dst, (int64_t)Universe::narrow_klass_base()); ++ if (Universe::narrow_klass_shift() != 0) { ++ assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); ++ assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?"); ++ slll(AT, src, Address::times_8); ++ addl(dst, dst, AT); ++ } else { ++ addl(dst, src, dst); ++ } ++ } ++} ++ ++void MacroAssembler::incrementl(Register reg, int value) { ++ if (value == min_jint) { ++ move(AT, value); ++ addw(reg, reg, AT); ++ return; ++ } ++ if (value < 0) { decrementl(reg, -value); return; } ++ if (value == 0) { ; return; } ++ ++ if(Assembler::is_simm16(value)) { ++ move(AT, value); addw(reg, reg, AT); ++ } else { ++ move(AT, value); ++ addw(reg, reg, AT); ++ } ++} ++ ++void MacroAssembler::decrementl(Register reg, int value) { ++ if (value == min_jint) { ++ move(AT, value); ++ subw(reg, reg, AT); ++ return; ++ } ++ if (value < 0) { incrementl(reg, -value); return; } ++ if (value == 0) { ; return; } ++ ++ if (Assembler::is_simm16(value)) { ++ move(AT, value); subw(reg, reg, AT); ++ } else { ++ move(AT, value); ++ subw(reg, reg, AT); ++ } ++} ++ ++void MacroAssembler::reinit_heapbase() { ++ if (UseCompressedOops || UseCompressedClassPointers) { ++ if (Universe::heap() != NULL) { ++ if (Universe::narrow_oop_base() == NULL) { ++ move(S5_heapbase, R0); ++ } else { ++ set64(S5_heapbase, (int64_t)Universe::narrow_ptrs_base()); ++ } ++ } else { ++ set64(S5_heapbase, (intptr_t)Universe::narrow_ptrs_base_addr()); ++ ldl(S5_heapbase, S5_heapbase, 0); ++ } ++ } ++} ++ ++void MacroAssembler::check_klass_subtype(Register sub_klass, ++ Register super_klass, ++ Register temp_reg, ++ Label& L_success) { ++//implement ind gen_subtype_check ++ Label L_failure; ++ check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL); ++ check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL); ++ BIND(L_failure); ++} ++ ++SkipIfEqual::SkipIfEqual( ++ MacroAssembler* masm, const bool* flag_addr, bool value) { ++ _masm = masm; ++ _masm->li(AT, (address)flag_addr); ++ _masm->ldbu(AT, AT, 0); ++ _masm->add_simm16(AT,AT,-value); ++ _masm->beq(AT,_label); ++} ++void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass, ++ Register super_klass, ++ Register temp_reg, ++ Label* L_success, ++ Label* L_failure, ++ Label* L_slow_path, ++ RegisterOrConstant super_check_offset) { ++ assert_different_registers(sub_klass, super_klass, temp_reg); ++ bool must_load_sco = (super_check_offset.constant_or_zero() == -1); ++ if (super_check_offset.is_register()) { ++ assert_different_registers(sub_klass, super_klass, ++ super_check_offset.as_register()); ++ } else if (must_load_sco) { ++ assert(temp_reg != noreg, "supply either a temp or a register offset"); ++ } ++ ++ Label L_fallthrough; ++ int label_nulls = 0; ++ if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } ++ if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } ++ if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; } ++ assert(label_nulls <= 1, "at most one NULL in the batch"); ++ ++ int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); ++ int sco_offset = in_bytes(Klass::super_check_offset_offset()); ++ // If the pointers are equal, we are done (e.g., String[] elements). ++ // This self-check enables sharing of secondary supertype arrays among ++ // non-primary types such as array-of-interface. Otherwise, each such ++ // type would need its own customized SSA. ++ // We move this check to the front of the fast path because many ++ // type checks are in fact trivially successful in this manner, ++ // so we get a nicely predicted branch right at the start of the check. ++ beq(sub_klass, super_klass, *L_success); ++ // Check the supertype display: ++ if (must_load_sco) { ++ // Positive movl does right thing on LP64. ++ ldw_unsigned(temp_reg, super_klass, sco_offset); ++ super_check_offset = RegisterOrConstant(temp_reg); ++ } ++ slll(AT, super_check_offset.register_or_noreg(), Address::times_1); ++ addl(AT, sub_klass, AT); ++ ldl(AT, AT, super_check_offset.constant_or_zero()*Address::times_1); ++ ++ // This check has worked decisively for primary supers. ++ // Secondary supers are sought in the super_cache ('super_cache_addr'). ++ // (Secondary supers are interfaces and very deeply nested subtypes.) ++ // This works in the same check above because of a tricky aliasing ++ // between the super_cache and the primary super display elements. ++ // (The 'super_check_addr' can address either, as the case requires.) ++ // Note that the cache is updated below if it does not help us find ++ // what we need immediately. ++ // So if it was a primary super, we can just fail immediately. ++ // Otherwise, it's the slow path for us (no success at this point). ++ ++ if (super_check_offset.is_register()) { ++ beq(super_klass, AT, *L_success); ++ add_simm16(AT, super_check_offset.as_register(), -sc_offset); ++ if (L_failure == &L_fallthrough) { ++ beq(AT, *L_slow_path); ++ } else { ++ bne(AT, *L_failure); ++ beq(R0, *L_slow_path); ++ } ++ } else if (super_check_offset.as_constant() == sc_offset) { ++ // Need a slow path; fast failure is impossible. ++ if (L_slow_path == &L_fallthrough) { ++ beq(super_klass, AT, *L_success); ++ } else { ++ bne(super_klass, AT, *L_slow_path); ++ beq(R0, *L_success); ++ } ++ } else { ++ // No slow path; it's a fast decision. ++ if (L_failure == &L_fallthrough) { ++ beq(super_klass, AT, *L_success); ++ } else { ++ bne(super_klass, AT, *L_failure); ++ beq(R0, *L_success); ++ } ++ } ++ ++ BIND(L_fallthrough); ++ ++} ++ ++ ++void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass, ++ Register super_klass, ++ Register temp_reg, ++ Register temp2_reg, ++ Label* L_success, ++ Label* L_failure, ++ bool set_cond_codes) { ++ assert_different_registers(sub_klass, super_klass, temp_reg); ++ if (temp2_reg != noreg) ++ assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg); ++ else ++ temp2_reg = T12; ++#define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg) ++ ++ Label L_fallthrough; ++ int label_nulls = 0; ++ if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } ++ if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } ++ assert(label_nulls <= 1, "at most one NULL in the batch"); ++ ++ // a couple of useful fields in sub_klass: ++ int ss_offset = in_bytes(Klass::secondary_supers_offset()); ++ int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); ++ Address secondary_supers_addr(sub_klass, ss_offset); ++ Address super_cache_addr( sub_klass, sc_offset); ++ ++ // Do a linear scan of the secondary super-klass chain. ++ // This code is rarely used, so simplicity is a virtue here. ++ // The repne_scan instruction uses fixed registers, which we must spill. ++ // Don't worry too much about pre-existing connections with the input regs. ++ ++#ifndef PRODUCT ++ int* pst_counter = &SharedRuntime::_partial_subtype_ctr; ++ ExternalAddress pst_counter_addr((address) pst_counter); ++ NOT_LP64( incrementl(pst_counter_addr) ); ++#endif //PRODUCT ++ ++ // We will consult the secondary-super array. ++ ldl(temp_reg, secondary_supers_addr); ++ // Load the array length. (Positive movl does right thing on LP64.) ++ ldw_signed(temp2_reg, Address(temp_reg, Array::length_offset_in_bytes())); ++ // Skip to start of data. ++ add_simm16(temp_reg, temp_reg, Array::base_offset_in_bytes()); ++ ++ // OpenJDK8 never compresses klass pointers in secondary-super array. ++ Label Loop, subtype; ++ BIND(Loop); ++ beq(temp2_reg, *L_failure); ++ ldl(AT, temp_reg, 0); ++ beq(AT, super_klass, subtype); ++ add_simm16(temp_reg, temp_reg, 1 * wordSize); ++ subl(temp2_reg, temp2_reg, 1); ++ beq(R0, Loop); ++ ++ BIND(subtype); ++ stl(super_klass, super_cache_addr); ++ if (L_success != &L_fallthrough) { ++ beq(R0, *L_success); ++ } ++ ++ // Success. Cache the super we found and proceed in triumph. ++#undef IS_A_TEMP ++ ++ BIND(L_fallthrough); ++} ++ ++void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) { ++ ldl(oop_result, Address(java_thread, JavaThread::vm_result_offset())); ++ stl(R0, Address(java_thread, JavaThread::vm_result_offset())); ++ verify_oop(oop_result, "broken oop in call_VM_base"); ++} ++ ++void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) { ++ ldl(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset())); ++ stl(R0, Address(java_thread, JavaThread::vm_result_2_offset())); ++} ++ ++Address MacroAssembler::argument_address(RegisterOrConstant arg_slot, ++ int extra_slot_offset) { ++ // cf. TemplateTable::prepare_invoke(), if (load_receiver). ++ int stackElementSize = Interpreter::stackElementSize; ++ int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0); ++#ifdef ASSERT ++ int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1); ++ assert(offset1 - offset == stackElementSize, "correct arithmetic"); ++#endif ++ Register scale_reg = NOREG; ++ Address::ScaleFactor scale_factor = Address::no_scale; ++ if (arg_slot.is_constant()) { ++ offset += arg_slot.as_constant() * stackElementSize; ++ } else { ++ scale_reg = arg_slot.as_register(); ++ scale_factor = Address::times_8; ++ } ++ // We don't push RA on stack in prepare_invoke. ++ // offset += wordSize; // return PC is on stack ++ if(scale_reg==NOREG) return Address(SP, offset); ++ else { ++ slll(scale_reg, scale_reg, scale_factor); ++ addl(scale_reg, SP, scale_reg); ++ return Address(scale_reg, offset); ++ } ++} ++ ++SkipIfEqual::~SkipIfEqual() { ++ _masm->bind(_label); ++} ++ ++void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) { ++ switch (size_in_bytes) { ++ case 8: ldl(dst, src); break; ++ case 4: ldw_signed(dst, src); break; ++ case 2: is_signed ? ldh_signed(dst, src) : ldh_unsigned(dst, src); break; ++ case 1: is_signed ? ldb_signed( dst, src) : ldbu( dst, src); break; ++ default: ShouldNotReachHere(); ++ } ++} ++ ++void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) { ++ switch (size_in_bytes) { ++ case 8: stl(src, dst); break; ++ case 4: stw(src, dst); break; ++ case 2: sth(src, dst); break; ++ case 1: stb(src, dst); break; ++ default: ShouldNotReachHere(); ++ } ++} ++ ++// Look up the method for a megamorphic invokeinterface call. ++// The target method is determined by . ++// The receiver klass is in recv_klass. ++// On success, the result will be in method_result, and execution falls through. ++// On failure, execution transfers to the given label. ++void MacroAssembler::lookup_interface_method(Register recv_klass, ++ Register intf_klass, ++ RegisterOrConstant itable_index, ++ Register method_result, ++ Register scan_temp, ++ Label& L_no_such_interface, ++ bool return_method) { ++ assert_different_registers(recv_klass, intf_klass, scan_temp, AT); ++ assert_different_registers(method_result, intf_klass, scan_temp, AT); ++ assert(recv_klass != method_result || !return_method, ++ "recv_klass can be destroyed when method isn't needed"); ++ ++ assert(itable_index.is_constant() || itable_index.as_register() == method_result, ++ "caller must use same register for non-constant itable index as for method"); ++ ++ // Compute start of first itableOffsetEntry (which is at the end of the vtable) ++ int vtable_base = InstanceKlass::vtable_start_offset() * wordSize; ++ int itentry_off = itableMethodEntry::method_offset_in_bytes(); ++ int scan_step = itableOffsetEntry::size() * wordSize; ++ int vte_size = vtableEntry::size() * wordSize; ++ Address::ScaleFactor times_vte_scale = Address::times_ptr; ++ assert(vte_size == wordSize, "else adjust times_vte_scale"); ++ ++ ldw_signed(scan_temp, Address(recv_klass, InstanceKlass::vtable_length_offset() * wordSize)); ++ ++ // %%% Could store the aligned, prescaled offset in the klassoop. ++ slll(scan_temp, scan_temp, times_vte_scale); ++ addl(scan_temp, recv_klass, scan_temp); ++ add_simm16(scan_temp, scan_temp, vtable_base); ++ if (HeapWordsPerLong > 1) { ++ // Round up to align_object_offset boundary ++ // see code for InstanceKlass::start_of_itable! ++ round_to(scan_temp, BytesPerLong); ++ } ++ ++ if (return_method) { ++ // Adjust recv_klass by scaled itable_index, so we can free itable_index. ++ assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below"); ++ if (itable_index.is_constant()) { ++ set64(AT, (int)itable_index.is_constant()); ++ slll(AT, AT, (int)Address::times_ptr); ++ } else { ++ slll(AT, itable_index.as_register(), (int)Address::times_ptr); ++ } ++ addl(AT, AT, recv_klass); ++ add_simm16(recv_klass, AT, itentry_off); ++ } ++ ++ Label search, found_method; ++ ++ for (int peel = 1; peel >= 0; peel--) { ++ ldl(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes())); ++ ++ if (peel) { ++ beq(intf_klass, method_result, found_method); ++ } else { ++ bne(intf_klass, method_result, search); ++ // (invert the test to fall through to found_method...) ++ } ++ ++ if (!peel) break; ++ ++ BIND(search); ++ ++ // Check that the previous entry is non-null. A null entry means that ++ // the receiver class doesn't implement the interface, and wasn't the ++ // same as when the caller was compiled. ++ beq(method_result, L_no_such_interface); ++ add_simm16(scan_temp, scan_temp, scan_step); ++ } ++ ++ BIND(found_method); ++ ++ if (return_method) { ++ // Got a hit. ++ ldw_signed(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes())); ++ addl(AT, recv_klass, scan_temp); ++ ldl(method_result, AT); ++ } ++} ++ ++// virtual method calling ++void MacroAssembler::lookup_virtual_method(Register recv_klass, ++ RegisterOrConstant vtable_index, ++ Register method_result) { ++ Register tmp = GP; ++ push(tmp); ++ ++ if (vtable_index.is_constant()) { ++ assert_different_registers(recv_klass, method_result, tmp); ++ } else { ++ assert_different_registers(recv_klass, method_result, vtable_index.as_register(), tmp); ++ } ++ const int base = InstanceKlass::vtable_start_offset() * wordSize; ++ assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below"); ++ if (vtable_index.is_constant()) { ++ set64(AT, vtable_index.as_constant()); ++ slll(AT, AT, (int)Address::times_ptr); ++ } else { ++ slll(AT, vtable_index.as_register(), (int)Address::times_ptr); ++ } ++ set64(tmp, base + vtableEntry::method_offset_in_bytes()); ++ addl(tmp, tmp, AT); ++ addl(tmp, tmp, recv_klass); ++ ldl(method_result, tmp, 0); ++ ++ pop(tmp); ++} ++ ++void MacroAssembler::store_for_type_by_register(Register src_reg, Register tmp_reg, int disp, BasicType type, bool wide) { ++ switch (type) { ++ case T_LONG: ++ st_ptr(src_reg, tmp_reg, disp); ++ break; ++ case T_ARRAY: ++ case T_OBJECT: ++ if (UseCompressedOops && !wide) { ++ stw(src_reg, tmp_reg, disp); ++ } else { ++ st_ptr(src_reg, tmp_reg, disp); ++ } ++ break; ++ case T_ADDRESS: ++ st_ptr(src_reg, tmp_reg, disp); ++ break; ++ case T_INT: ++ stw(src_reg, tmp_reg, disp); ++ break; ++ case T_CHAR: ++ case T_SHORT: ++ sth(src_reg, tmp_reg, disp); ++ break; ++ case T_BYTE: ++ case T_BOOLEAN: ++ stb(src_reg, tmp_reg, disp); ++ break; ++ default: ++ ShouldNotReachHere(); ++ } ++} ++ ++//C1 ++void MacroAssembler::store_for_type(Register src_reg, Address addr, BasicType type, bool wide) { ++ Register tmp_reg = T9; ++ ++ int disp = addr.disp(); ++ bool disp_is_simm16 = true; ++ if (!Assembler::is_simm16(disp)) { ++ disp_is_simm16 = false; ++ } ++ ++ Register base_reg = addr.base(); ++ if (!disp_is_simm16) { ++ assert_different_registers(tmp_reg, base_reg); ++ move(tmp_reg, disp); ++ addl(tmp_reg, base_reg, tmp_reg); ++ } ++ store_for_type_by_register(src_reg, disp_is_simm16 ? base_reg : tmp_reg, disp_is_simm16 ? disp : 0, type, wide); ++} ++ ++void MacroAssembler::store_for_type_by_register(FloatRegister src_reg, Register tmp_reg, int disp, BasicType type) { ++ switch (type) { ++ case T_DOUBLE: ++ fstd(src_reg, tmp_reg, disp); ++ break; ++ case T_FLOAT: ++ fsts(src_reg, tmp_reg, disp); ++ break; ++ default: ++ ShouldNotReachHere(); ++ } ++} ++ ++//C1 ++void MacroAssembler::store_for_type(FloatRegister src_reg, Address addr, BasicType type) { ++ Register tmp_reg = T9; ++ ++ int disp = addr.disp(); ++ bool disp_is_simm16 = true; ++ if (!Assembler::is_simm16(disp)) { ++ disp_is_simm16 = false; ++ } ++ ++ Register base_reg = addr.base(); ++ if (!disp_is_simm16) { ++ assert_different_registers(tmp_reg, base_reg); ++ move(tmp_reg, disp); ++ addl(tmp_reg, base_reg, tmp_reg); ++ } ++ store_for_type_by_register(src_reg, disp_is_simm16 ? base_reg : tmp_reg, disp_is_simm16 ? disp : 0, type); ++} ++ ++void MacroAssembler::load_for_type_by_register(Register dst_reg, Register tmp_reg, int disp, BasicType type, bool wide) { ++ switch (type) { ++ case T_LONG: ++ ld_ptr(dst_reg, tmp_reg, disp); ++ break; ++ case T_ARRAY: ++ case T_OBJECT: ++ if (UseCompressedOops && !wide) { ++ ldw_unsigned(dst_reg, tmp_reg, disp); ++ } else { ++ ld_ptr(dst_reg, tmp_reg, disp); ++ } ++ break; ++ case T_ADDRESS: ++ if (UseCompressedClassPointers && disp == oopDesc::klass_offset_in_bytes()) { ++ ldw_unsigned(dst_reg, tmp_reg, disp); ++ } else { ++ ld_ptr(dst_reg, tmp_reg, disp); ++ } ++ break; ++ case T_INT: ++ ldw(dst_reg, tmp_reg, disp); ++ break; ++ case T_CHAR: ++ ldhu(dst_reg, tmp_reg, disp); ++ break; ++ case T_SHORT: ++ ldh_signed(dst_reg, tmp_reg, disp); ++ break; ++ case T_BYTE: ++ case T_BOOLEAN: ++ ldb_signed(dst_reg, tmp_reg, disp); ++ break; ++ default: ++ ShouldNotReachHere(); ++ } ++} ++ ++//C1 ++int MacroAssembler::load_for_type(Register dst_reg, Address addr, BasicType type, bool wide) { ++ int code_offset = 0; ++ Register tmp_reg = T9; ++ ++ int disp = addr.disp(); ++ bool disp_is_simm16 = true; ++ if (!Assembler::is_simm16(disp)) { ++ disp_is_simm16 = false; ++ } ++ ++ Register base_reg = addr.base(); ++ if (!disp_is_simm16) { ++ assert_different_registers(tmp_reg, base_reg); ++ move(tmp_reg, disp); ++ addl(tmp_reg, base_reg, tmp_reg); ++ } ++ code_offset = offset(); ++ load_for_type_by_register(dst_reg, disp_is_simm16 ? base_reg : tmp_reg, disp_is_simm16 ? disp : 0, type, wide); ++ ++ return code_offset; ++} ++ ++void MacroAssembler::load_for_type_by_register(FloatRegister dst_reg, Register tmp_reg, int disp, BasicType type) { ++ switch (type) { ++ case T_DOUBLE: ++ fldd(dst_reg, tmp_reg, disp); ++ break; ++ case T_FLOAT: ++ flds(dst_reg, tmp_reg, disp); ++ break; ++ default: ++ ShouldNotReachHere(); ++ } ++} ++ ++//C1 ++int MacroAssembler::load_for_type(FloatRegister dst_reg, Address addr, BasicType type) { ++ int code_offset = 0; ++ Register tmp_reg = T9; ++ ++ int disp = addr.disp(); ++ bool disp_is_simm16 = true; ++ if (!Assembler::is_simm16(disp)) { ++ disp_is_simm16 = false; ++ } ++ ++ Register base_reg = addr.base(); ++ if (!disp_is_simm16) { ++ assert_different_registers(tmp_reg, base_reg); ++ move(tmp_reg, disp); ++ addl(tmp_reg, base_reg, tmp_reg); ++ } ++ code_offset = offset(); ++ load_for_type_by_register(dst_reg, disp_is_simm16 ? base_reg : tmp_reg, disp_is_simm16 ? disp : 0, type); ++ ++ return code_offset; ++} +diff --git a/hotspot/src/cpu/sw64/vm/macroAssembler_sw64.hpp b/hotspot/src/cpu/sw64/vm/macroAssembler_sw64.hpp +new file mode 100755 +index 0000000000..d139742529 +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/macroAssembler_sw64.hpp +@@ -0,0 +1,712 @@ ++/* ++ * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_SW64_VM_MACROASSEMBLER_SW64_HPP ++#define CPU_SW64_VM_MACROASSEMBLER_SW64_HPP ++ ++#include "asm/assembler.hpp" ++#include "utilities/macros.hpp" ++#include "runtime/rtmLocking.hpp" ++ ++ ++// MacroAssembler extends Assembler by frequently used macros. ++// ++// Instructions for which a 'better' code sequence exists depending ++// on arguments should also go in here. ++ ++class MacroAssembler: public Assembler { ++ friend class LIR_Assembler; ++ friend class Runtime1; // as_Address() ++ ++ protected: ++ ++ Address as_Address(AddressLiteral adr); ++ Address as_Address(ArrayAddress adr); ++ ++ // Support for VM calls ++ // ++ // This is the base routine called by the different versions of call_VM_leaf. The interpreter ++ // may customize this version by overriding it for its purposes (e.g., to save/restore ++ // additional registers when doing a VM call). ++#ifdef CC_INTERP ++ // c++ interpreter never wants to use interp_masm version of call_VM ++ #define VIRTUAL ++#else ++ #define VIRTUAL virtual ++#endif ++ ++ VIRTUAL void call_VM_leaf_base( ++ address entry_point, // the entry point ++ int number_of_arguments // the number of arguments to pop after the call ++ ); ++ ++ // This is the base routine called by the different versions of call_VM. The interpreter ++ // may customize this version by overriding it for its purposes (e.g., to save/restore ++ // additional registers when doing a VM call). ++ // ++ // If no java_thread register is specified (noreg) than S2Thread will be used instead. call_VM_base ++ // returns the register which contains the thread upon return. If a thread register has been ++ // specified, the return value will correspond to that register. If no last_java_sp is specified ++ // (noreg) than sp will be used instead. ++ VIRTUAL void call_VM_base( // returns the register containing the thread upon return ++ Register oop_result, // where an oop-result ends up if any; use noreg otherwise ++ Register java_thread, // the thread if computed before ; use noreg otherwise ++ Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise ++ address entry_point, // the entry point ++ int number_of_arguments, // the number of arguments (w/o thread) to pop after the call ++ bool check_exceptions // whether to check for pending exceptions after return ++ ); ++ ++ // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code. ++ // The implementation is only non-empty for the InterpreterMacroAssembler, ++ // as only the interpreter handles PopFrame and ForceEarlyReturn requests. ++ virtual void check_and_handle_popframe(Register java_thread); ++ virtual void check_and_handle_earlyret(Register java_thread); ++ ++ void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true); ++ ++ // helpers for FPU flag access ++ // tmp is a temporary register, if none is available use noreg ++ ++ public: ++ static intptr_t i[32]; ++ static float f[32]; ++ static void print(outputStream *s); ++ ++ static int i_offset(unsigned int k); ++ static int f_offset(unsigned int k); ++ ++ static void save_registers(MacroAssembler *masm); ++ static void restore_registers(MacroAssembler *masm); ++ ++ MacroAssembler(CodeBuffer* code) : Assembler(code) {} ++ ++ // Support for NULL-checks ++ // ++ // Generates code that causes a NULL OS exception if the content of reg is NULL. ++ // If the accessed location is M[reg + offset] and the offset is known, provide the ++ // offset. No explicit code generation is needed if the offset is within a certain ++ // range (0 <= offset <= page_size). ++ ++ void null_check(Register reg, int offset = -1); ++ static bool needs_explicit_null_check(intptr_t offset); ++ ++ // Required platform-specific helpers for Label::patch_instructions. ++ // They _shadow_ the declarations in AbstractAssembler, which are undefined. ++ void pd_patch_instruction(address branch, address target); ++ ++ // Support for inc/dec with optimal instruction selection depending on value ++ void incrementl(Register reg, int value = 1); ++ void decrementl(Register reg, int value = 1); ++ ++ ++ // Alignment ++ void align(int modulus); ++ ++ ++ // Stack frame creation/removal ++ void enter(); ++ void leave(); ++ ++ // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information) ++ // The pointer will be loaded into the thread register. ++ void get_thread(Register thread); ++ ++ ++ // Support for VM calls ++ // ++ // It is imperative that all calls into the VM are handled via the call_VM macros. ++ // They make sure that the stack linkage is setup correctly. call_VM's correspond ++ // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points. ++ ++ ++ void call_VM(Register oop_result, ++ address entry_point, ++ bool check_exceptions = true); ++ void call_VM(Register oop_result, ++ address entry_point, ++ Register arg_1, ++ bool check_exceptions = true); ++ void call_VM(Register oop_result, ++ address entry_point, ++ Register arg_1, Register arg_2, ++ bool check_exceptions = true); ++ void call_VM(Register oop_result, ++ address entry_point, ++ Register arg_1, Register arg_2, Register arg_3, ++ bool check_exceptions = true); ++ ++ // Overloadings with last_Java_sp ++ void call_VM(Register oop_result, ++ Register last_java_sp, ++ address entry_point, ++ int number_of_arguments = 0, ++ bool check_exceptions = true); ++ void call_VM(Register oop_result, ++ Register last_java_sp, ++ address entry_point, ++ Register arg_1, bool ++ check_exceptions = true); ++ void call_VM(Register oop_result, ++ Register last_java_sp, ++ address entry_point, ++ Register arg_1, Register arg_2, ++ bool check_exceptions = true); ++ void call_VM(Register oop_result, ++ Register last_java_sp, ++ address entry_point, ++ Register arg_1, Register arg_2, Register arg_3, ++ bool check_exceptions = true); ++ ++ void get_vm_result (Register oop_result, Register thread); ++ void get_vm_result_2(Register metadata_result, Register thread); ++ void call_VM_leaf(address entry_point, ++ int number_of_arguments = 0); ++ void call_VM_leaf(address entry_point, ++ Register arg_1); ++ void call_VM_leaf(address entry_point, ++ Register arg_1, Register arg_2); ++ void call_VM_leaf(address entry_point, ++ Register arg_1, Register arg_2, Register arg_3); ++ ++ // Super call_VM calls - correspond to MacroAssembler::call_VM(_leaf) calls ++ void super_call_VM_leaf(address entry_point); ++ void super_call_VM_leaf(address entry_point, Register arg_1); ++ void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2); ++ void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3); ++ ++ // last Java Frame (fills frame anchor) ++ void set_last_Java_frame(Register thread, ++ Register last_java_sp, ++ Register last_java_fp, ++ address last_java_pc); ++ ++ // thread in the default location (S2) ++ void set_last_Java_frame(Register last_java_sp, ++ Register last_java_fp, ++ address last_java_pc); ++ ++ void reset_last_Java_frame(Register thread, bool clear_fp); ++ ++ // thread in the default location (S2) ++ void reset_last_Java_frame(bool clear_fp); ++ ++ // Stores ++ void store_check(Register obj); // store check for obj - register is destroyed afterwards ++ void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed) ++ ++ void resolve_jobject(Register value, Register thread, Register tmp); ++ void clear_jweak_tag(Register possibly_jweak); ++ ++#if INCLUDE_ALL_GCS ++ ++ void g1_write_barrier_pre(Register obj, ++ Register pre_val, ++ Register thread, ++ Register tmp, ++ bool tosca_live, ++ bool expand_call); ++ ++ void g1_write_barrier_post(Register store_addr, ++ Register new_val, ++ Register thread, ++ Register tmp, ++ Register tmp2); ++ ++#endif // INCLUDE_ALL_GCS ++ ++ // split store_check(Register obj) to enhance instruction interleaving ++ void store_check_part_1(Register obj); ++ void store_check_part_2(Register obj); ++ ++ // C 'boolean' to Java boolean: x == 0 ? 0 : 1 ++ void c2bool(Register x); ++ //add for compressedoops ++ void load_klass(Register dst, Register src); ++ void store_klass(Register dst, Register src); ++ void load_prototype_header(Register dst, Register src); ++ ++ void store_klass_gap(Register dst, Register src); ++ ++ void load_heap_oop(Register dst, Address src); ++ void store_heap_oop(Address dst, Register src); ++ void store_heap_oop_null(Address dst); ++ void encode_heap_oop(Register r); ++ void encode_heap_oop(Register dst, Register src); ++ void decode_heap_oop(Register r); ++ void decode_heap_oop(Register dst, Register src); ++ void encode_heap_oop_not_null(Register r); ++ void decode_heap_oop_not_null(Register r); ++ void encode_heap_oop_not_null(Register dst, Register src); ++ void decode_heap_oop_not_null(Register dst, Register src); ++ ++ void encode_klass_not_null(Register r); ++ void decode_klass_not_null(Register r); ++ void encode_klass_not_null(Register dst, Register src); ++ void decode_klass_not_null(Register dst, Register src); ++ ++ // Returns the byte size of the instructions generated by decode_klass_not_null() ++ // when compressed klass pointers are being used. ++ static int instr_size_for_decode_klass_not_null(); ++ ++ // if heap base register is used - reinit it with the correct value ++ void reinit_heapbase(); ++ ++ DEBUG_ONLY(void verify_heapbase(const char* msg);) ++ ++ void set_narrow_klass(Register dst, Klass* k); ++ void set_narrow_oop(Register dst, jobject obj); ++ ++ void int3(); ++ // Sign extension ++ void sign_extend_short(Register reg) { sexth(reg, reg); } ++ void sign_extend_byte(Register reg) { sextb(reg, reg); } ++ void rem_s(FloatRegister fd, FloatRegister fs, FloatRegister ft, FloatRegister tmp); ++ void rem_d(FloatRegister fd, FloatRegister fs, FloatRegister ft, FloatRegister tmp); ++ ++ void trigfunc(char trig, int num_fpu_regs_in_use = 1); ++ // allocation ++ void eden_allocate( ++ Register obj, // result: pointer to object after successful allocation ++ Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise ++ int con_size_in_bytes, // object size in bytes if known at compile time ++ Register t1, // temp register ++ Register t2, ++ Label& slow_case // continuation point if fast allocation fails ++ ); ++ void tlab_allocate( ++ Register obj, // result: pointer to object after successful allocation ++ Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise ++ int con_size_in_bytes, // object size in bytes if known at compile time ++ Register t1, // temp register ++ Register t2, // temp register ++ Label& slow_case // continuation point if fast allocation fails ++ ); ++ void update_byte_crc32(Register crc, Register val, Register table); ++ void kernel_crc32(Register crc, Register buf, Register len, Register tmp, Register tmp3); ++ void tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); ++ void incr_allocated_bytes(Register thread, ++ Register var_size_in_bytes, int con_size_in_bytes, ++ Register t1 = noreg); ++ // interface method calling ++ void lookup_interface_method(Register recv_klass, ++ Register intf_klass, ++ RegisterOrConstant itable_index, ++ Register method_result, ++ Register scan_temp, ++ Label& no_such_interface, ++ bool return_method = true); ++ ++ // virtual method calling ++ void lookup_virtual_method(Register recv_klass, ++ RegisterOrConstant vtable_index, ++ Register method_result); ++ ++ // Test sub_klass against super_klass, with fast and slow paths. ++ ++ // The fast path produces a tri-state answer: yes / no / maybe-slow. ++ // One of the three labels can be NULL, meaning take the fall-through. ++ // If super_check_offset is -1, the value is loaded up from super_klass. ++ // No registers are killed, except temp_reg. ++ void check_klass_subtype_fast_path(Register sub_klass, ++ Register super_klass, ++ Register temp_reg, ++ Label* L_success, ++ Label* L_failure, ++ Label* L_slow_path, ++ RegisterOrConstant super_check_offset = RegisterOrConstant(-1)); ++ ++ // The rest of the type check; must be wired to a corresponding fast path. ++ // It does not repeat the fast path logic, so don't use it standalone. ++ // The temp_reg and temp2_reg can be noreg, if no temps are available. ++ // Updates the sub's secondary super cache as necessary. ++ // If set_cond_codes, condition codes will be Z on success, NZ on failure. ++ void check_klass_subtype_slow_path(Register sub_klass, ++ Register super_klass, ++ Register temp_reg, ++ Register temp2_reg, ++ Label* L_success, ++ Label* L_failure, ++ bool set_cond_codes = false); ++ ++ // Simplified, combined version, good for typical uses. ++ // Falls through on failure. ++ void check_klass_subtype(Register sub_klass, ++ Register super_klass, ++ Register temp_reg, ++ Label& L_success); ++ ++ ++ // Debugging ++ ++ // only if +VerifyOops ++ void verify_oop(Register reg, const char* s = "broken oop"); ++ void verify_oop_addr(Address addr, const char * s = "broken oop addr"); ++ void verify_oop_subroutine(); ++ // TODO: verify method and klass metadata (compare against vptr?) ++ void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {} ++ void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){} ++ ++ #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__) ++ #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__) ++ ++ // only if +VerifyFPU ++ void verify_FPU(int stack_depth, const char* s = "illegal FPU state"); ++ ++ // prints msg, dumps registers and stops execution ++ void stop(const char* msg); ++ ++ // prints msg and continues ++ void warn(const char* msg); ++ ++ static void debug(char* msg/*, RegistersForDebugging* regs*/); ++ static void debug64(char* msg, int64_t pc, int64_t regs[]); ++ ++// void print_reg(Register reg); ++// void print_reg(FloatRegister reg); ++ //void os_breakpoint(); ++ ++ void untested() { stop("untested"); } ++ ++ void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, sizeof(b), "unimplemented: %s", what); stop(b); } ++ ++ void should_not_reach_here() { stop("should not reach here"); } ++ ++ void print_CPU_state(); ++ ++ // Stack overflow checking ++ void bang_stack_with_offset(int offset) { ++ // stack grows down, caller passes positive offset ++ assert(offset > 0, "must bang with negative offset"); ++ if (offset <= 32768) { ++ stw(R0, SP, -offset); // sw(A0, SP, -offset); ++ } else { ++ li(AT, offset); ++ subl(AT, SP, AT); ++ stw(R0, AT, 0); // sw(A0, AT, 0); ++ } ++ } ++ ++ // Writes to stack successive pages until offset reached to check for ++ // stack overflow + shadow pages. Also, clobbers tmp ++ void bang_stack_size(Register size, Register tmp); ++ ++ virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr, ++ Register tmp, ++ int offset); ++ ++ // Support for serializing memory accesses between threads ++ void serialize_memory(Register thread, Register tmp); ++ ++ //void verify_tlab(); ++ void verify_tlab(Register t1, Register t2); ++ ++ // Compare char[] arrays aligned to 4 bytes. ++ void char_arrays_equals(Register ary1, Register ary2, ++ Register limit, Register result, ++ Register chr1, Register chr2, Label& Ldone); ++ ++ // Biased locking support ++ // lock_reg and obj_reg must be loaded up with the appropriate values. ++ // tmp_reg is optional. If it is supplied (i.e., != noreg) it will ++ // be killed; if not supplied, push/pop will be used internally to ++ // allocate a temporary (inefficient, avoid if possible). ++ // Optional slow case is for implementations (interpreter and C1) which branch to ++ // slow case directly. Leaves condition codes set for C2's Fast_Lock node. ++ // Returns offset of first potentially-faulting instruction for null ++ // check info (currently consumed only by C1). If ++ // swap_reg_contains_mark is true then returns -1 as it is assumed ++ // the calling code has already passed any potential faults. ++ int biased_locking_enter(Register lock_reg, Register obj_reg, ++ Register swap_reg, Register tmp_reg, ++ bool swap_reg_contains_mark, ++ Label& done, Label* slow_case = NULL, ++ BiasedLockingCounters* counters = NULL); ++ void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done); ++#ifdef COMPILER2 ++ void fast_lock(Register obj, Register box, Register tmp, Register scr); ++ void fast_unlock(Register obj, Register box, Register tmp); ++#endif ++ ++ ++ // Arithmetics ++ // Regular vs. d* versions ++ inline void addu_long(Register rd, Register rs, Register rt) { ++ addl(rd, rs, rt); ++ } ++ ++ inline void addu_long(Register rd, Register rs, long imm32_64) { ++ add_simm16(rd, rs, imm32_64); ++ } ++ ++ void round_to(Register reg, int modulus) { ++ assert_different_registers(reg, AT); ++ increment(reg, modulus - 1); ++ move(AT, - modulus); ++ and_reg(reg, reg, AT); ++ } ++ ++ // the follow two might use AT register, be sure you have no meanful data in AT before you call them ++ void increment(Register reg, int imm); ++ void decrement(Register reg, int imm); ++ ++ void shl(Register reg, int sa) { slll(reg, reg, sa); } ++ void shr(Register reg, int sa) { srll(reg, reg, sa); } ++ void sar(Register reg, int sa) { sral(reg, reg, sa); } ++ // Helper functions for statistics gathering. ++ void atomic_inc32(address counter_addr, int inc, Register tmp_reg1, Register tmp_reg2); ++ ++ // Calls ++ void call(address entry); ++ void call(Register reg); ++ void call(address entry, relocInfo::relocType rtype); ++ void call(address entry, RelocationHolder& rh); ++ // Emit the CompiledIC call idiom ++ void ic_call(address entry); ++ ++ // Jumps ++ void jmp(address entry); ++ void jmp(Register reg); ++ void jmp(address entry, relocInfo::relocType rtype); ++ void jmp_far(Label& L); // always long jumps ++ ++ /* branches may exceed 16-bit offset */ ++ void b_far(address entry); ++ void b_far(Label& L); ++ ++ // For C2 to support long branches ++ void beq_long (Register rs, Register rt, Label& L); ++ void bne_long (Register rs, Register rt, Label& L); ++ void bc1t_long (Label& L); ++ void bc1f_long (Label& L); ++ ++ void patchable_call(address target); ++ void patchable_call_setfpec1(address target); ++ void general_call(address target); ++ ++ void patchable_jump(address target); ++ void general_jump(address target); ++ ++ static int insts_for_patchable_call(address target); ++ static int insts_for_general_call(address target); ++ ++ static int insts_for_patchable_jump(address target); ++ static int insts_for_general_jump(address target); ++ ++ // Floating ++ // Data ++ ++ // Argument ops ++ inline void store_int_argument(Register s, Argument &a) { ++ if(a.is_Register()) { ++ move(a.as_Register(), s); ++ } else { ++ stw(s, a.as_caller_address()); ++ } ++ } ++ ++ inline void store_long_argument(Register s, Argument &a) { ++ Argument a1 = a.successor(); ++ if(a.is_Register() && a1.is_Register()) { ++ move(a.as_Register(), s); ++ move(a.as_Register(), s); ++ } else { ++ stl(s, a.as_caller_address()); ++ } ++ } ++ ++ inline void store_float_argument(FloatRegister s, Argument &a) { ++ if(a.is_Register()) { ++ fmovs(a.as_FloatRegister(), s); ++ } else { ++ fsts(s, a.as_caller_address()); ++ } ++ } ++ ++ inline void store_double_argument(FloatRegister s, Argument &a) { ++ if(a.is_Register()) { ++ fmovd(a.as_FloatRegister(), s); ++ } else { ++ fstd(s, a.as_caller_address()); ++ } ++ } ++ ++ inline void store_ptr_argument(Register s, Argument &a) { ++ if(a.is_Register()) { ++ move(a.as_Register(), s); ++ } else { ++ st_ptr(s, a.as_caller_address()); ++ } ++ } ++ ++ // Load and store values by size and signed-ness ++ void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg); ++ void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg); ++ ++ inline void ld_ptr(Register rt, Address a){ ++ ldl(rt, a.base(), a.disp()); ++ } ++ inline void ld_ptr(Register rt, Register base, int offset16){ ++ ldl(rt, base, offset16); ++ } ++ inline void st_ptr(Register rt, Address a){ ++ stl(rt, a.base(), a.disp()); ++ } ++ inline void st_ptr(Register rt, Register base, int offset16) { ++ stl(rt, base, offset16); ++ } ++ ++ void ld_ptr(Register rt, Register offset, Register base); ++ void st_ptr(Register rt, Register offset, Register base); ++ ++ inline void ld_long(Register rt, Register base, int offset16); ++ inline void st_long(Register rt, Register base, int offset16); ++ inline void ld_long(Register rt, Address a); ++ inline void st_long(Register rt, Address a); ++ void ld_long(Register rt, Register offset, Register base); ++ void st_long(Register rt, Register offset, Register base); ++ ++ // swap the two byte of the low 16-bit halfword ++ // this directive will use AT, be sure the high 16-bit of reg is zero ++ void hswap(Register reg); ++ void huswap(Register reg); ++ ++ // convert big endian integer to little endian integer ++ void swap(Register reg); ++ void saveTRegisters(); ++ void restoreTRegisters(); ++ ++ // implement the x86 instruction semantic ++ // if c_reg == *dest then *dest <= x_reg ++ // else c_reg <= *dest ++ // the AT indicate if xchg occurred, 1 for xchged, else 0 ++ void cmpxchg(Register x_reg, Address dest, Register c_reg); ++ void cmpxchg32(Register x_reg, Address dest, Register c_reg); ++ ++ void extend_sign(Register rh, Register rl) { stop("extend_sign"); } ++ void push (Register reg) { subl(SP, SP, 8); stl (reg, SP, 0); } ++ void push (FloatRegister reg) { subl(SP, SP, 8); fstd(reg, SP, 0); } ++ void pop (Register reg); ++ void pop (FloatRegister reg); ++ void pop () { addl(SP, SP, 8); } ++ void pop2 () { addl(SP, SP, 16); } ++ void push2(Register reg1, Register reg2); ++ void pop2 (Register reg1, Register reg2); ++ void dpush (Register reg) { subl(SP, SP, 8); stl (reg, SP, 0); } ++ void dpop (Register reg) { ldl (reg, SP, 0); addl(SP, SP, 8); } ++ //we need 2 fun to save and resotre general register ++ void pushad(); ++ void popad(); ++ void pushad_except_RA(); ++ void popad_except_RA(); ++ ++ //move an 32-bit immediate to Register ++ void move(Register reg, int imm32) { li32(reg, imm32); } ++ void li (Register rd, long imm); ++ void li (Register rd, address addr) { li(rd, (long)addr); } ++ //replace move(Register reg, int imm) ++ void boundary_test(FloatRegister ft, Register res); ++ void set64(Register d, jlong value); ++ static int insts_for_set64(jlong value); ++ ++ void patchable_set48(Register d, jlong value); ++ ++ static bool reachable_from_cache(address target); ++ ++ ++ void dli(Register rd, long imm) { li(rd, imm); } ++ void li64(Register rd, long imm); ++ void li48(Register rd, long imm); ++ ++ void move(Register rd, Register rs) { if (rs != rd) or_ins(rd, R0, rs); } ++ void move_u32(Register rd, Register rs) { if(rs != rd) or_ins(rd, R0, rs); } ++ void dmove(Register rd, Register rs) { if (rs != rd) or_ins(rd, R0, rs); } ++ void mov_metadata(Register dst, Metadata* obj); ++ void mov_metadata(Address dst, Metadata* obj); ++ ++ void store_for_type_by_register(Register src_reg, Register tmp_reg, int disp, BasicType type, bool wide); ++ void store_for_type_by_register(FloatRegister src_reg, Register tmp_reg, int disp, BasicType type); ++ void store_for_type(Register src_reg, Address addr, BasicType type = T_INT, bool wide = false); ++ void store_for_type(FloatRegister src_reg, Address addr, BasicType type = T_INT); ++ void load_for_type_by_register(Register dst_reg, Register tmp_reg, int disp, BasicType type, bool wide); ++ void load_for_type_by_register(FloatRegister dst_reg, Register tmp_reg, int disp, BasicType type); ++ int load_for_type(Register dst_reg, Address addr, BasicType type = T_INT, bool wide = false); ++ int load_for_type(FloatRegister dst_reg, Address addr, BasicType type = T_INT); ++ ++#ifndef PRODUCT ++ static void pd_print_patched_instruction(address branch) { ++ jint stub_inst = *(jint*) branch; ++ print_instruction(stub_inst); ++ ::tty->print("%s", " (unresolved)"); ++ } ++#endif ++ ++ void empty_FPU_stack(){/*need implemented*/}; ++ ++ ++ Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0); ++ ++#undef VIRTUAL ++ ++}; ++ ++/** ++ * class SkipIfEqual: ++ * ++ * Instantiating this class will result in assembly code being output that will ++ * jump around any code emitted between the creation of the instance and it's ++ * automatic destruction at the end of a scope block, depending on the value of ++ * the flag passed to the constructor, which will be checked at run-time. ++ */ ++class SkipIfEqual { ++ private: ++ MacroAssembler* _masm; ++ Label _label; ++ ++ public: ++ SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value); ++ ~SkipIfEqual(); ++}; ++ ++class SizedScope { ++private: ++ int _size; ++ MacroAssembler* _masm; ++ address _start; ++public: ++ SizedScope(MacroAssembler* masm, int size) { ++ _masm = masm; ++ _size = size; ++ _start = _masm->pc(); ++ } ++ ~SizedScope() { ++ if (_masm->pc() - _start > _size) Unimplemented(); ++ while (_masm->pc() - _start < _size) _masm->nop(); ++ } ++}; ++#ifdef ASSERT ++inline bool AbstractAssembler::pd_check_instruction_mark() { return true; } ++#endif ++ ++#endif // CPU_SW64_VM_MACROASSEMBLER_SW64_HPP +diff --git a/hotspot/src/cpu/sw64/vm/macroAssembler_sw64.inline.hpp b/hotspot/src/cpu/sw64/vm/macroAssembler_sw64.inline.hpp +new file mode 100755 +index 0000000000..aa33708b46 +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/macroAssembler_sw64.inline.hpp +@@ -0,0 +1,33 @@ ++/* ++ * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_SW64_VM_MACROASSEMBLER_SW64_INLINE_HPP ++#define CPU_SW64_VM_MACROASSEMBLER_SW64_INLINE_HPP ++ ++#include "asm/assembler.inline.hpp" ++#include "asm/macroAssembler.hpp" ++#include "asm/codeBuffer.hpp" ++#include "code/codeCache.hpp" ++ ++#endif // CPU_SW64_VM_MACROASSEMBLER_SW64_INLINE_HPP +diff --git a/hotspot/src/cpu/sw64/vm/metaspaceShared_sw64.cpp b/hotspot/src/cpu/sw64/vm/metaspaceShared_sw64.cpp +new file mode 100755 +index 0000000000..b0c08f362a +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/metaspaceShared_sw64.cpp +@@ -0,0 +1,114 @@ ++/* ++ * Copyright (c) 2004, 2012, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#include "precompiled.hpp" ++#include "asm/macroAssembler.hpp" ++#include "asm/codeBuffer.hpp" ++#include "memory/metaspaceShared.hpp" ++ ++// Generate the self-patching vtable method: ++// ++// This method will be called (as any other Klass virtual method) with ++// the Klass itself as the first argument. Example: ++// ++// oop obj; ++// int size = obj->klass()->klass_part()->oop_size(this); ++// ++// for which the virtual method call is Klass::oop_size(); ++// ++// The dummy method is called with the Klass object as the first ++// operand, and an object as the second argument. ++// ++ ++//===================================================================== ++ ++// All of the dummy methods in the vtable are essentially identical, ++// differing only by an ordinal constant, and they bear no releationship ++// to the original method which the caller intended. Also, there needs ++// to be 'vtbl_list_size' instances of the vtable in order to ++// differentiate between the 'vtable_list_size' original Klass objects. ++ ++#define __ masm-> ++ ++#ifdef PRODUCT ++#define BLOCK_COMMENT(str) /* nothing */ ++#else ++#define BLOCK_COMMENT(str) { char line[1024];sprintf(line,"%s:%s:%d",str,__FILE__, __LINE__); __ block_comment(line);} ++#endif ++ ++#define BIND(label) bind(label); BLOCK_COMMENT(#label ":") ++ ++void MetaspaceShared::generate_vtable_methods(void** vtbl_list, ++ void** vtable, ++ char** md_top, ++ char* md_end, ++ char** mc_top, ++ char* mc_end) { ++ ++ intptr_t vtable_bytes = (num_virtuals * vtbl_list_size) * sizeof(void*); ++ *(intptr_t *)(*md_top) = vtable_bytes; ++ *md_top += sizeof(intptr_t); ++ void** dummy_vtable = (void**)*md_top; ++ *vtable = dummy_vtable; ++ *md_top += vtable_bytes; ++ ++ // Get ready to generate dummy methods. ++ ++ CodeBuffer cb((unsigned char*)*mc_top, mc_end - *mc_top); ++ MacroAssembler* masm = new MacroAssembler(&cb); ++ ++ Label common_code; ++ for (int i = 0; i < vtbl_list_size; ++i) { ++ for (int j = 0; j < num_virtuals; ++j) { ++ dummy_vtable[num_virtuals * i + j] = (void*)masm->pc(); ++ ++ // Load V0 with a value indicating vtable/offset pair. ++ // -- bits[ 7..0] (8 bits) which virtual method in table? ++ // -- bits[12..8] (5 bits) which virtual method table? ++ // -- must fit in 13-bit instruction immediate field. ++ __ move(V0, (i << 8) + j); ++ __ beq(R0, common_code); ++ } ++ } ++ ++ __ BIND(common_code); ++ ++ __ zapnot(T12, V0, 0xf); ++ __ srll(T12, T12, 8); // isolate vtable identifier. ++ __ slll(T12, T12, LogBytesPerWord); ++ __ li(AT, (long)vtbl_list); ++ __ addl(T12, AT, T12); ++ __ ldl(T12, T12, 0); // get correct vtable address. ++ __ stl(T12, A0, 0); // update vtable pointer. ++ ++ __ and_imm8(V0, V0, 0x00ff); // isolate vtable method index ++ __ slll(V0, V0, LogBytesPerWord); ++ __ addl(T12, T12, V0); ++ __ ldl(T12, T12, 0); // address of real method pointer. ++ __ jmp(T12); // get real method pointer. ++ ++ __ flush(); ++ ++ *mc_top = (char*)__ pc(); ++} +diff --git a/hotspot/src/cpu/sw64/vm/methodHandles_sw64.cpp b/hotspot/src/cpu/sw64/vm/methodHandles_sw64.cpp +new file mode 100755 +index 0000000000..43a92c72ba +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/methodHandles_sw64.cpp +@@ -0,0 +1,549 @@ ++/* ++ * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#include "precompiled.hpp" ++#include "asm/macroAssembler.hpp" ++#include "interpreter/interpreter.hpp" ++#include "interpreter/interpreterRuntime.hpp" ++#include "memory/allocation.inline.hpp" ++#include "prims/methodHandles.hpp" ++ ++#define __ _masm-> ++ ++#ifdef PRODUCT ++#define BLOCK_COMMENT(str) /* nothing */ ++#define STOP(error) stop(error) ++#else ++#define BLOCK_COMMENT(str) { char line[1024];sprintf(line,"%s:%s:%d",str,__FILE__, __LINE__); __ block_comment(line); } ++#define STOP(error) block_comment(error); __ stop(error) ++#endif ++ ++#define BIND(label) bind(label); BLOCK_COMMENT(#label ":") ++ ++void MethodHandles::load_klass_from_Class(MacroAssembler* _masm, Register klass_reg) { ++ if (VerifyMethodHandles) ++ verify_klass(_masm, klass_reg, SystemDictionary::WK_KLASS_ENUM_NAME(java_lang_Class), ++ "MH argument is a Class"); ++ __ ldl(klass_reg, Address(klass_reg, java_lang_Class::klass_offset_in_bytes())); ++} ++ ++#ifdef ASSERT ++static int check_nonzero(const char* xname, int x) { ++ assert(x != 0, err_msg("%s should be nonzero", xname)); ++ return x; ++} ++#define NONZERO(x) check_nonzero(#x, x) ++#else //ASSERT ++#define NONZERO(x) (x) ++#endif //ASSERT ++ ++#ifdef ASSERT ++void MethodHandles::verify_klass(MacroAssembler* _masm, ++ Register obj, SystemDictionary::WKID klass_id, ++ const char* error_message) { ++} ++ ++void MethodHandles::verify_ref_kind(MacroAssembler* _masm, int ref_kind, Register member_reg, Register temp) { ++ Label L; ++ BLOCK_COMMENT("verify_ref_kind {"); ++ __ ldw_signed(temp, Address(member_reg, NONZERO(java_lang_invoke_MemberName::flags_offset_in_bytes()))); ++ __ sral(temp, temp, java_lang_invoke_MemberName::MN_REFERENCE_KIND_SHIFT&0x1f); ++ __ move(AT, java_lang_invoke_MemberName::MN_REFERENCE_KIND_MASK); ++ __ and_reg(temp, temp, AT); ++ __ move(AT, ref_kind); ++ __ beq(temp, AT, L); ++ { char* buf = NEW_C_HEAP_ARRAY(char, 100, mtInternal); ++ jio_snprintf(buf, 100, "verify_ref_kind expected %x", ref_kind); ++ if (ref_kind == JVM_REF_invokeVirtual || ++ ref_kind == JVM_REF_invokeSpecial) ++ // could do this for all ref_kinds, but would explode assembly code size ++ trace_method_handle(_masm, buf); ++ __ STOP(buf); ++ } ++ BLOCK_COMMENT("} verify_ref_kind"); ++ __ BIND(L); ++} ++ ++#endif //ASSERT ++ ++void MethodHandles::jump_from_method_handle(MacroAssembler* _masm, Register method, Register temp, ++ bool for_compiler_entry) { ++ assert(method == Rmethod, "interpreter calling convention"); ++ ++ Label L_no_such_method; ++ __ beq(method, L_no_such_method); ++ ++ __ verify_method_ptr(method); ++ ++ if (!for_compiler_entry && JvmtiExport::can_post_interpreter_events()) { ++ Label run_compiled_code; ++ // JVMTI events, such as single-stepping, are implemented partly by avoiding running ++ // compiled code in threads for which the event is enabled. Check here for ++ // interp_only_mode if these events CAN be enabled. ++ Register rthread = S2thread; ++ // interp_only is an int, on little endian it is sufficient to test the byte only ++ // Is a cmpl faster? ++ __ ldbu(AT, rthread, in_bytes(JavaThread::interp_only_mode_offset())); ++ __ beq(AT, run_compiled_code); ++ __ ldl(T12, method, in_bytes(Method::interpreter_entry_offset())); ++ __ jmp(T12); ++ __ BIND(run_compiled_code); ++ } ++ ++ const ByteSize entry_offset = for_compiler_entry ? Method::from_compiled_offset() : ++ Method::from_interpreted_offset(); ++ __ ldl(T12, method, in_bytes(entry_offset)); ++ __ jmp(T12); ++ ++ __ BIND(L_no_such_method); ++ address wrong_method = StubRoutines::throw_AbstractMethodError_entry(); ++ __ jmp(wrong_method, relocInfo::runtime_call_type); ++} ++ ++void MethodHandles::jump_to_lambda_form(MacroAssembler* _masm, ++ Register recv, Register method_temp, ++ Register temp2, ++ bool for_compiler_entry) { ++ BLOCK_COMMENT("jump_to_lambda_form {"); ++ // This is the initial entry point of a lazy method handle. ++ // After type checking, it picks up the invoker from the LambdaForm. ++ assert_different_registers(recv, method_temp, temp2); ++ assert(recv != noreg, "required register"); ++ assert(method_temp == Rmethod, "required register for loading method"); ++ ++ //NOT_PRODUCT({ FlagSetting fs(TraceMethodHandles, true); trace_method_handle(_masm, "LZMH"); }); ++ ++ // Load the invoker, as MH -> MH.form -> LF.vmentry ++ __ verify_oop(recv); ++ __ load_heap_oop(method_temp, Address(recv, NONZERO(java_lang_invoke_MethodHandle::form_offset_in_bytes()))); ++ __ verify_oop(method_temp); ++ __ load_heap_oop(method_temp, Address(method_temp, NONZERO(java_lang_invoke_LambdaForm::vmentry_offset_in_bytes()))); ++ __ verify_oop(method_temp); ++ // the following assumes that a Method* is normally compressed in the vmtarget field: ++ __ ldl(method_temp, Address(method_temp, NONZERO(java_lang_invoke_MemberName::vmtarget_offset_in_bytes()))); ++ ++ if (VerifyMethodHandles && !for_compiler_entry) { ++ // make sure recv is already on stack ++ __ ldl(temp2, Address(method_temp, Method::const_offset())); ++ __ load_sized_value(temp2, ++ Address(temp2, ConstMethod::size_of_parameters_offset()), ++ sizeof(u2), false); ++ // assert(sizeof(u2) == sizeof(Method::_size_of_parameters), ""); ++ Label L; ++ Address recv_addr = __ argument_address(temp2, -1); ++ __ ldl(AT, recv_addr); ++ __ beq(recv, AT, L); ++ ++ recv_addr = __ argument_address(temp2, -1); ++ __ ldl(V0, recv_addr); ++ __ STOP("receiver not on stack"); ++ __ BIND(L); ++ } ++ ++ jump_from_method_handle(_masm, method_temp, temp2, for_compiler_entry); ++ BLOCK_COMMENT("} jump_to_lambda_form"); ++} ++ ++ ++// Code generation ++address MethodHandles::generate_method_handle_interpreter_entry(MacroAssembler* _masm, ++ vmIntrinsics::ID iid) { ++ const bool not_for_compiler_entry = false; // this is the interpreter entry ++ assert(is_signature_polymorphic(iid), "expected invoke iid"); ++ if (iid == vmIntrinsics::_invokeGeneric || ++ iid == vmIntrinsics::_compiledLambdaForm) { ++ // Perhaps surprisingly, the symbolic references visible to Java are not directly used. ++ // They are linked to Java-generated adapters via MethodHandleNatives.linkMethod. ++ // They all allow an appendix argument. ++ __ stop("empty stubs make SG sick"); ++ return NULL; ++ } ++ ++ // Rmethod: Method* ++ // T9: argument locator (parameter slot count, added to sp) ++ // S7: used as temp to hold mh or receiver ++ Register t12_argp = T12; // argument list ptr, live on error paths ++ Register s1_mh = S1; // MH receiver; dies quickly and is recycled ++ Register rm_method = Rmethod; // eventual target of this invocation ++ ++ // here's where control starts out: ++ __ align(CodeEntryAlignment); ++ address entry_point = __ pc(); ++ ++ if (VerifyMethodHandles) { ++ Label L; ++ BLOCK_COMMENT("verify_intrinsic_id {"); ++ __ ldbu(AT, rm_method, Method::intrinsic_id_offset_in_bytes()); ++ guarantee(Assembler::is_simm16(iid), "Oops, iid is not simm16! Change the instructions."); ++ __ add_simm16(AT, AT, -1 * (int) iid); ++ __ beq(AT, L); ++ if (iid == vmIntrinsics::_linkToVirtual || ++ iid == vmIntrinsics::_linkToSpecial) { ++ // could do this for all kinds, but would explode assembly code size ++ trace_method_handle(_masm, "bad Method*::intrinsic_id"); ++ } ++ __ STOP("bad Method*::intrinsic_id"); ++ __ BIND(L); ++ BLOCK_COMMENT("} verify_intrinsic_id"); ++ } ++ ++ // First task: Find out how big the argument list is. ++ Address t12_first_arg_addr; ++ int ref_kind = signature_polymorphic_intrinsic_ref_kind(iid); ++ assert(ref_kind != 0 || iid == vmIntrinsics::_invokeBasic, "must be _invokeBasic or a linkTo intrinsic"); ++ if (ref_kind == 0 || MethodHandles::ref_kind_has_receiver(ref_kind)) { ++ __ ldl(t12_argp, Address(rm_method, Method::const_offset())); ++ __ load_sized_value(t12_argp, ++ Address(t12_argp, ConstMethod::size_of_parameters_offset()), ++ sizeof(u2), false); ++ // assert(sizeof(u2) == sizeof(Method::_size_of_parameters), ""); ++ t12_first_arg_addr = __ argument_address(t12_argp, -1); ++ } else { ++ DEBUG_ONLY(t12_argp = noreg); ++ } ++ ++ if (!is_signature_polymorphic_static(iid)) { ++ __ ldl(s1_mh, t12_first_arg_addr); ++ DEBUG_ONLY(t12_argp = noreg); ++ } ++ ++ // t12_first_arg_addr is live! ++ ++ trace_method_handle_interpreter_entry(_masm, iid); ++ ++ if (iid == vmIntrinsics::_invokeBasic) { ++ generate_method_handle_dispatch(_masm, iid, s1_mh, noreg, not_for_compiler_entry); ++ ++ } else { ++ // Adjust argument list by popping the trailing MemberName argument. ++ Register r_recv = noreg; ++ if (MethodHandles::ref_kind_has_receiver(ref_kind)) { ++ // Load the receiver (not the MH; the actual MemberName's receiver) up from the interpreter stack. ++ __ ldl(r_recv = T2, t12_first_arg_addr); ++ } ++ DEBUG_ONLY(t12_argp = noreg); ++ Register rm_member = rm_method; // MemberName ptr; incoming method ptr is dead now ++ __ pop(rm_member); // extract last argument ++ generate_method_handle_dispatch(_masm, iid, r_recv, rm_member, not_for_compiler_entry); ++ } ++ ++ return entry_point; ++} ++ ++void MethodHandles::generate_method_handle_dispatch(MacroAssembler* _masm, ++ vmIntrinsics::ID iid, ++ Register receiver_reg, ++ Register member_reg, ++ bool for_compiler_entry) { ++ assert(is_signature_polymorphic(iid), "expected invoke iid"); ++ Register rm_method = Rmethod; // eventual target of this invocation ++ // temps used in this code are not used in *either* compiled or interpreted calling sequences ++ Register j_rarg0 = A1; ++ Register j_rarg1 = A2; ++ Register j_rarg2 = A3; ++ Register j_rarg3 = A4; ++ Register j_rarg4 = A5; ++ Register j_rarg5 = A0; ++ ++ Register temp1 = T11; ++ Register temp2 = T12; ++ Register temp3 = V0; ++ if (for_compiler_entry) { ++ assert(receiver_reg == (iid == vmIntrinsics::_linkToStatic ? noreg : j_rarg0), "only valid assignment"); ++ assert_different_registers(temp1, j_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4, j_rarg5); ++ assert_different_registers(temp2, j_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4, j_rarg5); ++ assert_different_registers(temp3, j_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4, j_rarg5); ++ } ++ else { ++ assert_different_registers(temp1, temp2, temp3, saved_last_sp_register()); // don't trash lastSP ++ } ++ assert_different_registers(temp1, temp2, temp3, receiver_reg); ++ assert_different_registers(temp1, temp2, temp3, member_reg); ++ ++ if (iid == vmIntrinsics::_invokeBasic) { ++ // indirect through MH.form.vmentry.vmtarget ++ jump_to_lambda_form(_masm, receiver_reg, rm_method, temp1, for_compiler_entry); ++ ++ } else { ++ // The method is a member invoker used by direct method handles. ++ if (VerifyMethodHandles) { ++ // make sure the trailing argument really is a MemberName (caller responsibility) ++ verify_klass(_masm, member_reg, SystemDictionary::WK_KLASS_ENUM_NAME(java_lang_invoke_MemberName), ++ "MemberName required for invokeVirtual etc."); ++ } ++ ++ Address member_clazz( member_reg, NONZERO(java_lang_invoke_MemberName::clazz_offset_in_bytes())); ++ Address member_vmindex( member_reg, NONZERO(java_lang_invoke_MemberName::vmindex_offset_in_bytes())); ++ Address member_vmtarget( member_reg, NONZERO(java_lang_invoke_MemberName::vmtarget_offset_in_bytes())); ++ ++ Register temp1_recv_klass = temp1; ++ if (iid != vmIntrinsics::_linkToStatic) { ++ __ verify_oop(receiver_reg); ++ if (iid == vmIntrinsics::_linkToSpecial) { ++ // Don't actually load the klass; just null-check the receiver. ++ __ null_check(receiver_reg); ++ } else { ++ // load receiver klass itself ++ __ null_check(receiver_reg, oopDesc::klass_offset_in_bytes()); ++ __ load_klass(temp1_recv_klass, receiver_reg); ++ __ verify_klass_ptr(temp1_recv_klass); ++ } ++ BLOCK_COMMENT("check_receiver {"); ++ // The receiver for the MemberName must be in receiver_reg. ++ // Check the receiver against the MemberName.clazz ++ if (VerifyMethodHandles && iid == vmIntrinsics::_linkToSpecial) { ++ // Did not load it above... ++ __ load_klass(temp1_recv_klass, receiver_reg); ++ __ verify_klass_ptr(temp1_recv_klass); ++ } ++ if (VerifyMethodHandles && iid != vmIntrinsics::_linkToInterface) { ++ Label L_ok; ++ Register temp2_defc = temp2; ++ __ load_heap_oop(temp2_defc, member_clazz); ++ load_klass_from_Class(_masm, temp2_defc); ++ __ verify_klass_ptr(temp2_defc); ++ __ check_klass_subtype(temp1_recv_klass, temp2_defc, temp3, L_ok); ++ // If we get here, the type check failed! ++ __ STOP("receiver class disagrees with MemberName.clazz"); ++ __ BIND(L_ok); ++ } ++ BLOCK_COMMENT("} check_receiver"); ++ } ++ if (iid == vmIntrinsics::_linkToSpecial || ++ iid == vmIntrinsics::_linkToStatic) { ++ DEBUG_ONLY(temp1_recv_klass = noreg); // these guys didn't load the recv_klass ++ } ++ ++ // Live registers at this point: ++ // member_reg - MemberName that was the trailing argument ++ // temp1_recv_klass - klass of stacked receiver, if needed ++ ++ Label L_incompatible_class_change_error; ++ switch (iid) { ++ case vmIntrinsics::_linkToSpecial: ++ if (VerifyMethodHandles) { ++ verify_ref_kind(_masm, JVM_REF_invokeSpecial, member_reg, temp3); ++ } ++ __ ldl(rm_method, member_vmtarget); ++ break; ++ ++ case vmIntrinsics::_linkToStatic: ++ if (VerifyMethodHandles) { ++ verify_ref_kind(_masm, JVM_REF_invokeStatic, member_reg, temp3); ++ } ++ __ ldl(rm_method, member_vmtarget); ++ break; ++ ++ case vmIntrinsics::_linkToVirtual: ++ { ++ // same as TemplateTable::invokevirtual, ++ // minus the CP setup and profiling: ++ ++ if (VerifyMethodHandles) { ++ verify_ref_kind(_masm, JVM_REF_invokeVirtual, member_reg, temp3); ++ } ++ ++ // pick out the vtable index from the MemberName, and then we can discard it: ++ Register temp2_index = temp2; ++ __ ldl(temp2_index, member_vmindex); ++ ++ if (VerifyMethodHandles) { ++ Label L_index_ok; ++ __ cmplt(AT, R0, temp2_index); ++ __ bne(AT, L_index_ok); ++ __ STOP("no virtual index"); ++ __ BIND(L_index_ok); ++ } ++ ++ // Note: The verifier invariants allow us to ignore MemberName.clazz and vmtarget ++ // at this point. And VerifyMethodHandles has already checked clazz, if needed. ++ ++ // get target Method* & entry point ++ __ lookup_virtual_method(temp1_recv_klass, temp2_index, rm_method); ++ break; ++ } ++ ++ case vmIntrinsics::_linkToInterface: ++ { ++ // same as TemplateTable::invokeinterface ++ // (minus the CP setup and profiling, with different argument motion) ++ if (VerifyMethodHandles) { ++ verify_ref_kind(_masm, JVM_REF_invokeInterface, member_reg, temp3); ++ } ++ ++ Register temp3_intf = temp3; ++ __ load_heap_oop(temp3_intf, member_clazz); ++ load_klass_from_Class(_masm, temp3_intf); ++ __ verify_klass_ptr(temp3_intf); ++ ++ Register rm_index = rm_method; ++ __ ldl(rm_index, member_vmindex); ++ if (VerifyMethodHandles) { ++ Label L; ++ __ cmplt(AT, rm_index, R0); ++ __ beq(AT, L); ++ __ STOP("invalid vtable index for MH.invokeInterface"); ++ __ BIND(L); ++ } ++ ++ // given intf, index, and recv klass, dispatch to the implementation method ++ __ lookup_interface_method(temp1_recv_klass, temp3_intf, ++ // note: next two args must be the same: ++ rm_index, rm_method, ++ temp2, ++ L_incompatible_class_change_error); ++ break; ++ } ++ ++ default: ++ fatal(err_msg_res("unexpected intrinsic %d: %s", iid, vmIntrinsics::name_at(iid))); ++ break; ++ } ++ ++ // Live at this point: ++ // rm_method ++ ++ // After figuring out which concrete method to call, jump into it. ++ // Note that this works in the interpreter with no data motion. ++ // But the compiled version will require that r_recv be shifted out. ++ __ verify_method_ptr(rm_method); ++ jump_from_method_handle(_masm, rm_method, temp1, for_compiler_entry); ++ ++ if (iid == vmIntrinsics::_linkToInterface) { ++ __ BIND(L_incompatible_class_change_error); ++ address icce_entry= StubRoutines::throw_IncompatibleClassChangeError_entry(); ++ __ jmp(icce_entry, relocInfo::runtime_call_type); ++ } ++ } ++} ++ ++#ifndef PRODUCT ++void trace_method_handle_stub(const char* adaptername, ++ oop mh, ++ intptr_t* saved_regs, ++ intptr_t* entry_sp) { ++ // called as a leaf from native code: do not block the JVM! ++ bool has_mh = (strstr(adaptername, "/static") == NULL && ++ strstr(adaptername, "linkTo") == NULL); // static linkers don't have MH ++ const char* mh_reg_name = has_mh ? "s1_mh" : "s1"; ++ tty->print_cr("MH %s %s="PTR_FORMAT" sp="PTR_FORMAT, ++ adaptername, mh_reg_name, ++ (void *)mh, entry_sp); ++ ++ if (Verbose) { ++ tty->print_cr("Registers:"); ++ const int saved_regs_count = RegisterImpl::number_of_registers; ++ for (int i = 0; i < saved_regs_count; i++) { ++ Register r = as_Register(i); ++ // The registers are stored in reverse order on the stack (by pusha). ++ tty->print("%3s=" PTR_FORMAT, r->name(), saved_regs[((saved_regs_count - 1) - i)]); ++ if ((i + 1) % 4 == 0) { ++ tty->cr(); ++ } else { ++ tty->print(", "); ++ } ++ } ++ tty->cr(); ++ ++ { ++ // dumping last frame with frame::describe ++ ++ JavaThread* p = JavaThread::active(); ++ ++ ResourceMark rm; ++ PRESERVE_EXCEPTION_MARK; // may not be needed by safer and unexpensive here ++ FrameValues values; ++ ++ // Note: We want to allow trace_method_handle from any call site. ++ // While trace_method_handle creates a frame, it may be entered ++ // without a PC on the stack top (e.g. not just after a call). ++ // Walking that frame could lead to failures due to that invalid PC. ++ // => carefully detect that frame when doing the stack walking ++ ++ // Current C frame ++ frame cur_frame = os::current_frame(); ++ ++ // Robust search of trace_calling_frame (independant of inlining). ++ // Assumes saved_regs comes from a pusha in the trace_calling_frame. ++ assert(cur_frame.sp() < saved_regs, "registers not saved on stack ?"); ++ frame trace_calling_frame = os::get_sender_for_C_frame(&cur_frame); ++ while (trace_calling_frame.fp() < saved_regs) { ++ trace_calling_frame = os::get_sender_for_C_frame(&trace_calling_frame); ++ } ++ ++ // safely create a frame and call frame::describe ++ intptr_t *dump_sp = trace_calling_frame.sender_sp(); ++ intptr_t *dump_fp = trace_calling_frame.link(); ++ ++ bool walkable = has_mh; // whether the traced frame shoud be walkable ++ ++ if (walkable) { ++ // The previous definition of walkable may have to be refined ++ // if new call sites cause the next frame constructor to start ++ // failing. Alternatively, frame constructors could be ++ // modified to support the current or future non walkable ++ // frames (but this is more intrusive and is not considered as ++ // part of this RFE, which will instead use a simpler output). ++ frame dump_frame = frame(dump_sp, dump_fp); ++ dump_frame.describe(values, 1); ++ } else { ++ // Stack may not be walkable (invalid PC above FP): ++ // Add descriptions without building a Java frame to avoid issues ++ values.describe(-1, dump_fp, "fp for #1 "); ++ values.describe(-1, dump_sp, "sp for #1"); ++ } ++ values.describe(-1, entry_sp, "raw top of stack"); ++ ++ tty->print_cr("Stack layout:"); ++ values.print(p); ++ } ++ if (has_mh && mh->is_oop()) { ++ mh->print(); ++ if (java_lang_invoke_MethodHandle::is_instance(mh)) { ++ if (java_lang_invoke_MethodHandle::form_offset_in_bytes() != 0) ++ java_lang_invoke_MethodHandle::form(mh)->print(); ++ } ++ } ++ } ++} ++ ++// The stub wraps the arguments in a struct on the stack to avoid ++// dealing with the different calling conventions for passing 6 ++// arguments. ++struct MethodHandleStubArguments { ++ const char* adaptername; ++ oopDesc* mh; ++ intptr_t* saved_regs; ++ intptr_t* entry_sp; ++}; ++void trace_method_handle_stub_wrapper(MethodHandleStubArguments* args) { ++ trace_method_handle_stub(args->adaptername, ++ args->mh, ++ args->saved_regs, ++ args->entry_sp); ++} ++ ++void MethodHandles::trace_method_handle(MacroAssembler* _masm, const char* adaptername) { ++} ++#endif //PRODUCT +diff --git a/hotspot/src/cpu/sw64/vm/methodHandles_sw64.hpp b/hotspot/src/cpu/sw64/vm/methodHandles_sw64.hpp +new file mode 100755 +index 0000000000..8db1d6625b +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/methodHandles_sw64.hpp +@@ -0,0 +1,61 @@ ++/* ++ * Copyright (c) 2010, 2012, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++// Platform-specific definitions for method handles. ++// These definitions are inlined into class MethodHandles. ++ ++// Adapters ++enum /* platform_dependent_constants */ { ++ adapter_code_size = NOT_LP64(16000 DEBUG_ONLY(+ 25000)) LP64_ONLY(32000 DEBUG_ONLY(+ 150000)) ++}; ++ ++// Additional helper methods for MethodHandles code generation: ++public: ++ static void load_klass_from_Class(MacroAssembler* _masm, Register klass_reg); ++ ++ static void verify_klass(MacroAssembler* _masm, ++ Register obj, SystemDictionary::WKID klass_id, ++ const char* error_message = "wrong klass") NOT_DEBUG_RETURN; ++ ++ static void verify_method_handle(MacroAssembler* _masm, Register mh_reg) { ++ verify_klass(_masm, mh_reg, SystemDictionary::WK_KLASS_ENUM_NAME(java_lang_invoke_MethodHandle), ++ "reference is a MH"); ++ } ++ ++ static void verify_ref_kind(MacroAssembler* _masm, int ref_kind, Register member_reg, Register temp) NOT_DEBUG_RETURN; ++ ++ // Similar to InterpreterMacroAssembler::jump_from_interpreted. ++ // Takes care of special dispatch from single stepping too. ++ static void jump_from_method_handle(MacroAssembler* _masm, Register method, Register temp, ++ bool for_compiler_entry); ++ ++ static void jump_to_lambda_form(MacroAssembler* _masm, ++ Register recv, Register method_temp, ++ Register temp2, ++ bool for_compiler_entry); ++ ++ static Register saved_last_sp_register() { ++ // Should be in sharedRuntime, not here. ++ return I29; ++ } +diff --git a/hotspot/src/cpu/sw64/vm/nativeInst_sw64.cpp b/hotspot/src/cpu/sw64/vm/nativeInst_sw64.cpp +new file mode 100755 +index 0000000000..3e35dae0f2 +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/nativeInst_sw64.cpp +@@ -0,0 +1,561 @@ ++/* ++ * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#include "precompiled.hpp" ++#include "asm/macroAssembler.hpp" ++#include "memory/resourceArea.hpp" ++#include "nativeInst_sw64.hpp" ++#include "oops/oop.inline.hpp" ++#include "runtime/handles.hpp" ++#include "runtime/sharedRuntime.hpp" ++#include "runtime/stubRoutines.hpp" ++#include "utilities/ostream.hpp" ++#ifdef COMPILER1 ++#include "c1/c1_Runtime1.hpp" ++#endif ++ ++#include ++ ++int NativeCall::instruction_size = 5 * BytesPerInstWord; ++int NativeCall::return_address_offset = 5 * BytesPerInstWord; ++int NativeCall::return_address_offset_long = 5 * BytesPerInstWord; ++int NativeGeneralJump::instruction_size = 5 * BytesPerInstWord; ++void NativeInstruction::wrote(int offset) { ++ ICache::invalidate_word(addr_at(offset)); ++} ++ ++void NativeInstruction::imm48_split(long imm48, int16_t &msb_l, int16_t &lsb_h, int16_t &lsb_l) { ++ int32_t lsb32 = (int32_t) ((intptr_t) imm48); ++ int32_t msb32 = (int32_t) (((intptr_t) imm48 - lsb32) >> 32); ++ ++ msb_l = (int16_t) msb32; ++ lsb_h = (lsb32 - (int16_t) lsb32) >> 16; ++ lsb_l = (int16_t) lsb32; ++ guarantee((msb_l >= 0x0 && msb_l < 0x7fff) || (msb_l == 0x7fff && lsb32 >= 0x0 && lsb32 < 0x7fff8000), "wrong number in li48 "); ++ if (lsb32 >= 0x7fff8000) ++ msb_l = msb_l + 1; ++} ++ ++void NativeInstruction::set_address(address dest) { ++ int16_t msb_l, lsb_h, lsb_l; ++ NativeInstruction::imm48_split((long) dest, msb_l, lsb_h, lsb_l); ++ if (SafePatch) { ++ if (is_op(int_at(0), Assembler::op_ldi) && ++ is_op(int_at(4), Assembler::op_br) && ++ is_op(int_at(16), Assembler::op_ldl)) { ++ set_long_at(8, (long) dest); ++ } else if (is_op(int_at(0), Assembler::op_br) && ++ is_op(int_at(12), Assembler::op_ldl) && ++ is_op(int_at(16), Assembler::op_ldi)) { ++ set_long_at(4, (long) dest); ++ } else { ++ tty->print_cr("\nError!\nset_address: 0x%lx", addr_at(0)); ++ Disassembler::decode(addr_at(0) - 10 * 4, addr_at(0) + 10 * 4, tty); ++ fatal("not a call "); ++ } ++ } else { ++ OrderAccess::fence(); ++ /* li48 or li64 */ ++ if (is_op(int_at(0), Assembler::op_ldi) && is_op(int_at(4), Assembler::op_slll_l)) { ++ int first_word = int_at(0); ++ set_int_at(0, 0x13FFFFFF); /* .1: br .1 */ ++ set_int_at(8, (int_at(8) & 0xffff0000) | (lsb_h & 0xffff)); ++ set_int_at(12, (int_at(12) & 0xffff0000) | (lsb_l & 0xffff)); ++ set_int_at(0, (first_word & 0xffff0000) | (msb_l & 0xffff)); ++ ++ ICache::invalidate_range(addr_at(0), 16); ++ } else if (is_op(int_at(0), Assembler::op_ldih) && is_op(int_at(8), Assembler::op_slll_l)) { ++ Unimplemented(); ++ } else { ++ fatal("not a call "); ++ } ++ } ++} ++void NativeInstruction::set_long_at(int offset, long i) { ++ address addr = addr_at(offset); ++ *(long*) addr = i; ++ ICache::invalidate_range(addr, 8); ++} ++ ++static int illegal_instruction_bits = 0; ++ ++int NativeInstruction::illegal_instruction() { ++ if (illegal_instruction_bits == 0) { ++ ResourceMark rm; ++ char buf[40]; ++ CodeBuffer cbuf((address)&buf[0], 20); ++ MacroAssembler* a = new MacroAssembler(&cbuf); ++ address ia = a->pc(); ++#ifdef SW64 //ZHJ20100508 ++ a->sys_call(0x80); ++ int bits = *(int*) ia; ++ assert((Assembler::sw2_op(bits) == Assembler::op_sys_call), "bad instruction"); ++#else ++ a->brk(11); ++ int bits = *(int*) ia; ++#endif ++ illegal_instruction_bits = bits; ++ } ++ return illegal_instruction_bits; ++} ++ ++bool NativeInstruction::is_int_branch() { ++ // is it the output of MacroAssembler::fb? ++ int x = long_at(0); ++ int op = Assembler::sw2_op(x); ++ ++ if (op >= Assembler::op_beq && op <= Assembler::op_blbs) ++ return true; ++ ++ if ((op == Assembler::op_br) || (op == Assembler::op_bsr)) ++ return true; ++ ++ return false; ++} ++ ++bool NativeInstruction::is_float_branch() { ++ // is it the output of MacroAssembler::fb? ++ int x = long_at(0); ++ int op = Assembler::sw2_op(x); ++ ++ if (op >= Assembler::op_fbeq && op <= Assembler::op_fbge) ++ return true; ++ ++ return false; ++} ++ ++ ++//------------------------------------------------------------------- ++ ++void NativeCall::verify() { ++ // make sure code pattern is actually a call instruction ++ /* li64 or li48 */ ++ int li_64 = 0; ++ int li_48 = 0; ++ if (SafePatch) { ++ if (is_op(Assembler::op_br) && ++ is_op(int_at(12), Assembler::op_ldl) && ++ is_op(int_at(16), Assembler::op_ldi) && ++ (is_op(int_at(20), Assembler::op_call)||is_op(int_at(20), Assembler::op_jmp))) { ++ li_48 = 1; ++ } ++ if (is_op(Assembler::op_ldi) && ++ is_op(int_at(4), Assembler::op_br) && ++ is_op(int_at(16), Assembler::op_ldl) && ++ (is_op(int_at(20), Assembler::op_call)||is_op(int_at(20), Assembler::op_jmp))) { ++ li_48 = 1; ++ } ++ ++ if (!li_64 && !li_48) { ++ tty->print_cr("NativeCall::verify addr=%lx", addr_at(0)); ++ fatal("not a call"); ++ } ++ } else { ++ // wait until the first inst is not spin any more. spin is 13ffffff(>0), ldi and ldih is fxxxxxxx < 0 ++ // ldw (t1, 0, a0); ++ // bgt (t1, -2); ++ __asm__ __volatile__( ++ "1: ldw $2, 0($16) \n\t" ++ " bgt $2, 1b \n\t" ++ ); ++ ++ if (is_op(Assembler::op_ldih) && ++ is_op(int_at(4), Assembler::op_ldi) && ++ is_op(int_at(8), Assembler::op_slll_l) && ++ is_op(int_at(12), Assembler::op_ldih) && ++ is_op(int_at(16), Assembler::op_ldi) && ++ is_op(int_at(24), Assembler::op_call)) { ++ li_64 = 1; ++ } ++ ++ if (is_op(Assembler::op_ldi) && ++ is_op(int_at(4), Assembler::op_slll_l) && ++ is_op(int_at(8), Assembler::op_ldih) && ++ is_op(int_at(12), Assembler::op_ldi) && ++ is_op(int_at(16), Assembler::op_call)) { ++ li_48 = 1; ++ } ++ ++ if (!li_64 && !li_48) { ++ tty->print_cr("NativeCall::verify addr=%lx", addr_at(0)); ++ fatal("not a call"); ++ } ++ } ++} ++ ++address NativeCall::destination() const { ++ if (SafePatch) { ++ if (is_op(int_at(0), Assembler::op_ldi) && ++ is_op(int_at(4), Assembler::op_br) && ++ is_op(int_at(16), Assembler::op_ldl)) { ++ return (address) long_at(8); ++ } else if (is_op(int_at(0), Assembler::op_br) && ++ is_op(int_at(12), Assembler::op_ldl) && ++ is_op(int_at(16), Assembler::op_ldi)) { ++ return (address) long_at(4); ++ } else { ++ tty->print_cr("\nError!\ndestination: 0x%lx", addr_at(0)); ++ Disassembler::decode(addr_at(0) - 10 * 4, addr_at(0) + 10 * 4, tty); ++ fatal("not a call "); ++ } ++ } else { ++ // wait until the first inst is not spin any more. spin is 13ffffff(>0), ldi and ldih is fxxxxxxx < 0 ++ // ldw (t1, 0, a0); ++ // bgt (t1, -2); ++ __asm__ __volatile__( ++ "1: ldw $2, 0($16) \n\t" ++ " bgt $2, 1b \n\t" ++ ); ++ ++ if (is_op(int_at(0), Assembler::op_ldih) && is_op(int_at(8), Assembler::op_slll_l)) { ++ /* li64 */ ++ int16_t msb_h = int_at(0)&0xffff; ++ int16_t msb_l = int_at(4)&0xffff; ++ int16_t lsb_h = int_at(12)&0xffff; ++ int16_t lsb_l = int_at(16)&0xffff; ++ ++ return (address)( ( ((intptr_t)(msb_h << 16) + (intptr_t)(msb_l)) << 32 ) + ++ ( ((intptr_t)(lsb_h << 16) + (intptr_t)(lsb_l)) ) ); ++ } ++ ++ if ( is_op(int_at(0), Assembler::op_ldi) && is_op(int_at(16), Assembler::op_call)) { ++ /* li48 */ ++ int16_t msb_l = int_at(0)&0xffff; ++ int16_t lsb_h = int_at(8)&0xffff; ++ int16_t lsb_l = int_at(12)&0xffff; ++ ++ // -1 should be 0xffff ffff ffff ffff, so we can not use low 48 bits ++ return (address) (((intptr_t) (msb_l) << 32) + ((intptr_t) (lsb_h) << 16) + (intptr_t) (lsb_l)); ++ } ++ } ++ ++ Unimplemented(); ++} ++ ++typedef void (* atomic_store64_ptr)(long *addr, int offset, long data64); ++ ++static int *buf; ++ ++static atomic_store64_ptr get_atomic_store64_func() { ++ static atomic_store64_ptr p = NULL; ++ if (p != NULL) ++ return p; ++ ++ buf = (int *)mmap(NULL, 64, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_PRIVATE | MAP_ANONYMOUS, ++ -1, 0); ++ buf[0] = 0x42110110; ++ buf[1] = 0xae500000; ++ buf[2] = 0x0bfa0001; ++ buf[3] = 0x43ff075f; /* nop */ ++ ++ p = (atomic_store64_ptr) buf; ++ return p; ++} ++ ++void NativeCall::set_destination(address dest) { ++ set_address(dest); ++} ++ ++void NativeCall::print() { ++ tty->print_cr(PTR_FORMAT ": call " PTR_FORMAT, ++ instruction_address(), destination()); ++} ++ ++// Inserts a native call instruction at a given pc ++void NativeCall::insert(address code_pos, address entry) { ++ NativeCall *call = nativeCall_at(code_pos); ++ CodeBuffer cb(call->addr_at(0), instruction_size); ++ MacroAssembler masm(&cb); ++#define __ masm. ++ if (SafePatch) { ++ if (__ offset() % 8 == 0) { ++ __ nop(); ++ __ br(T12, 2); ++ __ emit_int64((long) entry); ++ __ ldl(T12, T12, 0); ++ } else { ++ __ br(T12, 2); ++ __ emit_int64((long) entry); ++ __ ldl(T12, T12, 0); ++ __ nop(); ++ } ++ } else { ++ __ li48(T12, (long) entry); ++ } ++ __ call(T12); ++#undef __ ++ ++ ICache::invalidate_range(call->addr_at(0), instruction_size); ++} ++ ++//------------------------------------------------------------------- ++ ++void NativeMovConstReg::verify() { ++ /* li64 or li48 */ ++ int li_64 = 0; ++ int li_48 = 0; ++ ++ if (is_op(Assembler::op_ldih) && ++ is_op(int_at(4), Assembler::op_ldi) && ++ is_op(int_at(8), Assembler::op_slll_l) && ++ is_op(int_at(12), Assembler::op_ldih) && ++ is_op(int_at(16), Assembler::op_ldi)) { ++ li_64 = 1; ++ } ++ ++ if (is_op(Assembler::op_ldi) && ++ is_op(int_at(4), Assembler::op_slll_l) && ++ is_op(int_at(8), Assembler::op_ldih) && ++ is_op(int_at(12), Assembler::op_ldi)) { ++ li_48 = 1; ++ } ++ ++ if (is_op(int_at(0), Assembler::op_ldi) && ++ is_op(int_at(4), Assembler::op_br) && ++ is_op(int_at(16), Assembler::op_ldl)) { ++ li_48 = 1; ++ } ++ if (is_op(int_at(0), Assembler::op_br) && ++ is_op(int_at(12), Assembler::op_ldl) && ++ is_op(int_at(16), Assembler::op_ldi)) { ++ li_48 = 1; ++ } ++ ++ if (!li_64 && !li_48) { ++ fatal("not a mov reg, imm64/imm48"); ++ } ++} ++ ++void NativeMovConstReg::print() { ++ tty->print_cr(PTR_FORMAT ": mov reg, " INTPTR_FORMAT, ++ instruction_address(), data()); ++} ++ ++intptr_t NativeMovConstReg::data() const { ++ if (is_op(int_at(0), Assembler::op_ldi) && ++ is_op(int_at(4), Assembler::op_br) && ++ is_op(int_at(16), Assembler::op_ldl)) { ++ return (intptr_t) long_at(8); ++ } ++ if (is_op(int_at(0), Assembler::op_br) && ++ is_op(int_at(12), Assembler::op_ldl) && ++ is_op(int_at(16), Assembler::op_ldi)) { ++ return (intptr_t) long_at(4); ++ } ++ if (is_op(int_at(0), Assembler::op_ldih) && is_op(long_at(8), Assembler::op_slll_l)) { ++ /* li64 */ ++ int16_t msb_h = int_at(0)&0xffff; ++ int16_t msb_l = int_at(4)&0xffff; ++ int16_t lsb_h = int_at(12)&0xffff; ++ int16_t lsb_l = int_at(16)&0xffff; ++ ++ return ( (((intptr_t) (msb_h << 16) + (intptr_t) (msb_l)) << 32) + ((intptr_t) (lsb_h << 16) + (intptr_t) (lsb_l))); ++ ++ } else if (is_op(int_at(0), Assembler::op_ldi) && is_op(long_at(4), Assembler::op_slll_l)) { ++ /* li48 */ ++ int16_t msb_l = int_at(0)&0xffff; ++ int16_t lsb_h = int_at(8)&0xffff; ++ int16_t lsb_l = int_at(12)&0xffff; ++ ++ // -1 should be 0xffff ffff ffff ffff, so we can not use low 48 bits ++ return ((intptr_t) (msb_l) << 32) + ((intptr_t) (lsb_h) << 16) + (intptr_t) (lsb_l); ++ ++ } else { ++ fatal(" fatal in NativeMovConstReg::data() "); ++ } ++} ++ ++void NativeMovConstReg::set_data(intptr_t x) { ++ // for fix_oop_relocation,sw64 set oop use li48 ++ OrderAccess::fence(); ++ int16_t msb_l, lsb_h, lsb_l; ++ NativeInstruction::imm48_split((long)x, msb_l, lsb_h, lsb_l); ++ /* li48 or li64 */ ++ if (is_op(int_at(0), Assembler::op_ldi) && is_op(int_at(4), Assembler::op_slll_l)) { ++ set_int_at(0, (int_at(0) & 0xffff0000) | (msb_l & 0xffff)); ++ set_int_at(8, (int_at(8) & 0xffff0000) | (lsb_h & 0xffff)); ++ set_int_at(12, (int_at(12) & 0xffff0000) | (lsb_l & 0xffff)); ++ ICache::invalidate_range(addr_at(0), 16); ++ } else if (is_op(int_at(0), Assembler::op_ldih) && is_op(int_at(8), Assembler::op_slll_l)) { ++ Unimplemented(); ++ } else { ++ fatal("not a call "); ++ } ++} ++ ++//------------------------------------------------------------------- ++ ++int NativeMovRegMem::offset() const { ++ Unimplemented(); ++} ++ ++void NativeMovRegMem::set_offset(int x) { ++ Unimplemented(); ++} ++ ++void NativeMovRegMem::verify() { ++ Unimplemented(); ++} ++ ++void NativeMovRegMem::print() { ++ tty->print_cr("0x%x: mov reg, [reg + %x]", instruction_address(), offset()); ++} ++ ++bool NativeInstruction::is_sigill_zombie_not_entrant() { ++ return uint_at(0) == NativeIllegalInstruction::instruction_code; ++} ++ ++void NativeIllegalInstruction::insert(address code_pos) { ++ *(juint*)code_pos = instruction_code; ++ ICache::invalidate_range(code_pos, instruction_size); ++} ++ ++void NativeGeneralJump::verify() { ++ assert(((NativeInstruction *)this)->is_jump() || ++ ((NativeInstruction *)this)->is_cond_jump(), "not a general jump instruction"); ++} ++ ++void NativeGeneralJump::set_jump_destination(address dest) { ++ set_address(dest); ++} ++ ++address NativeGeneralJump::jump_destination() { ++ if (is_short()) { ++ Unimplemented(); ++ } ++ ++ if (SafePatch) { ++ if (is_op(int_at(0), Assembler::op_ldi) && ++ is_op(int_at(4), Assembler::op_br) && ++ is_op(int_at(16), Assembler::op_ldl)) { ++ return (address) long_at(8); ++ } else if (is_op(int_at(0), Assembler::op_br) && ++ is_op(int_at(12), Assembler::op_ldl) && ++ is_op(int_at(16), Assembler::op_ldi)) { ++ return (address) long_at(4); ++ } else { ++ tty->print_cr("\nError!\nNativeGeneralJump destination: 0x%lx", addr_at(0)); ++ Disassembler::decode(addr_at(0) - 10 * 4, addr_at(0) + 10 * 4, tty); ++ fatal(" fatal in NativeGeneralJump::jump_destination() "); ++ ShouldNotReachHere(); ++ } ++ } else { ++ /* li64 */ ++ if (is_op(int_at(0), Assembler::op_ldih) && is_op(long_at(8), Assembler::op_slll_l)) { ++ int16_t msb_h = int_at(0)&0xffff; ++ int16_t msb_l = int_at(4)&0xffff; ++ int16_t lsb_h = int_at(12)&0xffff; ++ int16_t lsb_l = int_at(16)&0xffff; ++ return (address) ((((intptr_t) (msb_h << 16)+(intptr_t) msb_l) << 32)+((intptr_t) (lsb_h << 16)+(intptr_t) lsb_l)); ++ } ++ ++ /* li48 */ ++ if (is_op(int_at(0), Assembler::op_ldi) && is_op(long_at(4), Assembler::op_slll_l)) { ++ int16_t msb_l = int_at(0)&0xffff; ++ int16_t lsb_h = int_at(8)&0xffff; ++ int16_t lsb_l = int_at(12)&0xffff; ++ return (address) (((intptr_t) (msb_l) << 32)+((intptr_t) (lsb_h << 16)+(intptr_t) lsb_l)); ++ } ++ } ++ ++ Unimplemented(); ++} ++ ++/* Must ensure atomicity */ ++void NativeGeneralJump::patch_verified_entry(address entry, address verified_entry, address dest) { ++ // ensure 100% atomicity. ++ // The destination is fixed and can be cached in JavaThread. ++ // ++// guarantee(!os::is_MP() || (((long)verified_entry % BytesPerWord) == 0), "destination must be aligned"); ++// bool is_aligned = !os::is_MP() || (((long)verified_entry % BytesPerWord) == 0); ++// ++// if (is_aligned) { ++// int code_buffer[4]; ++// ++// CodeBuffer cb((address)code_buffer, instruction_size); ++// MacroAssembler masm(&cb); ++//#define __ masm. ++// __ ldl(T12, S2thread, in_bytes(JavaThread::handle_wrong_method_stub_offset())); ++// __ jmp(T12); ++// __ nop(); ++// __ nop(); ++// ++// atomic_store64_ptr func = get_atomic_store64_func(); ++// (*func)((long *)verified_entry, 0, *(long *)&code_buffer[0]); ++// } else { ++ // We use an illegal instruction for marking a method as ++ // not_entrant or zombie ++ NativeIllegalInstruction::insert(verified_entry); ++// } ++ ICache::invalidate_range(verified_entry, instruction_size); ++} ++ ++bool NativeInstruction::is_jump() { ++ if (SafePatch) { ++ if (is_op(int_at(0), Assembler::op_ldi) && ++ is_op(int_at(4), Assembler::op_br) && ++ is_op(int_at(16), Assembler::op_ldl)) { ++ return true; ++ } else if (is_op(int_at(0), Assembler::op_br) && ++ is_op(int_at(12), Assembler::op_ldl) && ++ is_op(int_at(16), Assembler::op_ldi)) { ++ return true; ++ } else { ++ tty->print_cr("\nError!\nNativeGeneralJump destination"); ++ ShouldNotReachHere(); ++ } ++ } else { ++ if (is_op(Assembler::op_ldi) && ++ is_op(int_at(4), Assembler::op_slll_l) && ++ is_op(int_at(8), Assembler::op_ldih) && ++ is_op(int_at(12), Assembler::op_ldi)) ++ return true; ++ } ++ ++ if (is_op(Assembler::op_ldih) && ++ is_op(int_at(4), Assembler::op_ldi) && ++ is_op(int_at(8), Assembler::op_slll_l) && ++ is_op(int_at(12), Assembler::op_ldih) && ++ is_op(int_at(16), Assembler::op_ldi)) ++ return true; ++ ++ // Unimplemented(); ++ return false; ++} ++ ++bool NativeInstruction::is_safepoint_poll() { ++ ++ //refer to relocInfo::poll_return_type in sw64.ad ++ int x = long_at(0); ++ int op = Assembler::sw2_op(x); ++ if (op != Assembler::op_ldw) return false; ++ ++ Register ra = Assembler::sw2_ra(x); ++ if (ra != AT) return false; ++ ++ int mdisp = Assembler::sw2_mdisp(x); ++ if (mdisp != 0) return false; ++ ++ return true; ++} +diff --git a/hotspot/src/cpu/sw64/vm/nativeInst_sw64.hpp b/hotspot/src/cpu/sw64/vm/nativeInst_sw64.hpp +new file mode 100755 +index 0000000000..385f601a30 +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/nativeInst_sw64.hpp +@@ -0,0 +1,501 @@ ++/* ++ * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_SW64_VM_NATIVEINST_SW64_HPP ++#define CPU_SW64_VM_NATIVEINST_SW64_HPP ++ ++#include "asm/assembler.hpp" ++#include "memory/allocation.hpp" ++#include "runtime/icache.hpp" ++#include "runtime/os.hpp" ++#include "utilities/top.hpp" ++ ++// We have interfaces for the following instructions: ++// - NativeInstruction ++// - - NativeCall ++// - - NativeMovConstReg ++// - - NativeMovConstRegPatching ++// - - NativeMovRegMem ++// - - NativeMovRegMemPatching ++// - - NativeJump ++// - - NativeIllegalOpCode ++// - - NativeGeneralJump ++// - - NativeReturn ++// - - NativeReturnX (return with argument) ++// - - NativePushConst ++// - - NativeTstRegMem ++ ++// The base class for different kinds of native instruction abstractions. ++// Provides the primitive operations to manipulate code relative to this. ++ ++class NativeInstruction VALUE_OBJ_CLASS_SPEC { ++ friend class Relocation; ++ ++ public: ++ enum sw64_specific_constants { ++ nop_instruction_code = 0, ++ nop_instruction_size = 4 ++ }; ++ static void imm48_split(long imm48, int16_t &msb_l, int16_t &lsb_h, int16_t &lsb_l); ++ ++ bool is_nop() { return is_op(Assembler::op_ldi) && Assembler::is_ra(R0); } ++ bool is_memb() { return is_op(Assembler::op_memb); } ++ inline bool is_call(); ++ inline bool is_illegal(); ++ inline bool is_return(); ++ bool is_jump(); ++ inline bool is_cond_jump(); ++ bool is_safepoint_poll(); ++ ++ //sw64 has no instruction to generate a illegal instrucion exception ++ //we define ours: break 11 ++ static int illegal_instruction(); ++ ++ bool is_int_branch(); ++ bool is_float_branch(); ++ ++ //We use an illegal instruction for marking a method as not_entrant or zombie. ++ bool is_sigill_zombie_not_entrant(); ++ ++ protected: ++ address addr_at(int offset) const { return address(this) + offset; } ++ address instruction_address() const { return addr_at(0); } ++ address next_instruction_address() const { return addr_at(BytesPerInstWord); } ++ address prev_instruction_address() const { return addr_at(-BytesPerInstWord); } ++ ++ s_char sbyte_at(int offset) const { return *(s_char*) addr_at(offset); } ++ u_char ubyte_at(int offset) const { return *(u_char*) addr_at(offset); } ++ ++ jint int_at(int offset) const { return *(jint*) addr_at(offset); } ++ juint uint_at(int offset) const { return *(juint*) addr_at(offset); } ++ ++ intptr_t ptr_at(int offset) const { return *(intptr_t*) addr_at(offset); } ++ ++ oop oop_at (int offset) const { return *(oop*) addr_at(offset); } ++ jlong long_at(int offset) const { return *(jlong*)addr_at(offset); } ++ ++ void set_address(address dest); ++ void set_char_at(int offset, char c) { *addr_at(offset) = (u_char)c; wrote(offset); } ++ void set_int_at(int offset, jint i) { OrderAccess::fence(); *(jint*)addr_at(offset) = i; wrote(offset); } ++ void set_ptr_at (int offset, intptr_t ptr) { *(intptr_t*) addr_at(offset) = ptr; wrote(offset); } ++ void set_oop_at (int offset, oop o) { *(oop*) addr_at(offset) = o; wrote(offset); } ++ void set_long_at(int offset, long i); ++ ++ int insn_word() const { return long_at(0); } ++ static bool is_op (int insn, Assembler::ops_mem op) { return Assembler::sw2_op(insn) == (int)op; } ++ bool is_op (Assembler::ops_mem op) const { return is_op(insn_word(), op); } ++ static bool is_op (int insn, Assembler::ops_opr op) { return Assembler::sw2_arith_op(insn) == (int)op; } ++ bool is_op (Assembler::ops_opr op) const { return is_op(insn_word(), op); } ++ static bool is_op (int insn, Assembler::ops_oprl op) { return Assembler::sw2_arith_op(insn) == (int)op; } ++ bool is_op (Assembler::ops_oprl op) const { return is_op(insn_word(), op); } ++ static bool is_op (int insn, Assembler::ops_extra op) { return Assembler::sw2_mfc_op(insn) == (int)op; } ++ bool is_op (Assembler::ops_extra op) const { return is_op(insn_word(), op); } ++ static bool is_op (int insn, Assembler::ops_bra op) { return Assembler::sw2_op(insn) == (int)op; } ++ bool is_op (Assembler::ops_bra op) const { return is_op(insn_word(), op); } ++ static bool is_op (int insn, Assembler::ops_fp op) { return Assembler::sw2_op(insn) == (int)op; } ++ ++ bool is_rs (int insn, Register rs) const { return Assembler::rs(insn) == (int)rs->encoding(); } ++ bool is_rs (Register rs) const { return is_rs(insn_word(), rs); } ++ bool is_rt (int insn, Register rt) const { return Assembler::rt(insn) == (int)rt->encoding(); } ++ bool is_rt (Register rt) const { return is_rt(insn_word(), rt); } ++ ++ void wrote(int offset); ++ ++ public: ++ ++ // unit test stuff ++ static void test() {} // override for testing ++ ++ inline friend NativeInstruction* nativeInstruction_at(address address); ++}; ++ ++inline NativeInstruction* nativeInstruction_at(address address) { ++ NativeInstruction* inst = (NativeInstruction*)address; ++#ifdef ASSERT ++ //inst->verify(); ++#endif ++ return inst; ++} ++ ++inline NativeCall* nativeCall_at(address address); ++// The NativeCall is an abstraction for accessing/manipulating native call sw64 ++// instructions (used to manipulate inline caches, primitive & dll calls, etc.). ++// a call was done like this: ++// SW64 li64 bits: ++// ldih rd, msb_h(R0); ++// ldi rd, msb_l(rd); ++// slll rd, 32, rd; ++// ldih rd, lsb_h(rd); ++// ldi rd, lsb_l(rd); ++// call ra, rd, (hint) ++// setfpec1 ++// ++ ++// we just consider the above for instruction as one call instruction ++class NativeCall: public NativeInstruction { ++ public: ++ enum sw64_specific_constants { ++ instruction_offset = 0, ++// instruction_size = 5 * BytesPerInstWord, ++// return_address_offset = 5 * BytesPerInstWord, ++// return_address_offset_long = 5 * BytesPerInstWord, //equal to return_address_offset ++ displacement_offset = 0 ++ }; ++ static int instruction_size; //The three member variables can be reassigned in the bytecodes_sw64.cpp when SafePatch is true. ++ static int return_address_offset; ++ static int return_address_offset_long; ++ ++ address instruction_address() const { return addr_at(instruction_offset); } ++ address next_instruction_address() const { return addr_at(return_address_offset); } ++ address return_address() const { return addr_at(return_address_offset); } ++ ++ address destination() const; ++ void set_destination(address dest); ++ void set_destination_mt_safe(address dest) { set_destination(dest);} ++ void set_long_at(int offset, long i); ++ ++ void verify_alignment() { } ++ void verify(); ++ void print(); ++ ++ // Creation ++ inline friend NativeCall* nativeCall_at(address address); ++ inline friend NativeCall* nativeCall_before(address return_address); ++ ++ static bool is_call_at(address instr) { ++ return nativeInstruction_at(instr)->is_call(); ++ } ++ ++ static bool is_call_before(address return_address) { ++ return is_call_at(return_address - NativeCall::return_address_offset); ++ } ++ ++ static bool is_call_to(address instr, address target) { ++ return nativeInstruction_at(instr)->is_call() && ++ nativeCall_at(instr)->destination() == target; ++ } ++ ++ // MT-safe patching of a call instruction. ++ static void insert(address code_pos, address entry); ++}; ++ ++inline NativeCall* nativeCall_at(address address) { ++ NativeCall* call = (NativeCall*)(address - NativeCall::instruction_offset); ++#ifdef ASSERT ++ call->verify(); ++#endif ++ return call; ++} ++ ++inline NativeCall* nativeCall_before(address return_address) { ++ NativeCall* call = (NativeCall*)(return_address - NativeCall::return_address_offset); ++#ifdef ASSERT ++ call->verify(); ++#endif ++ return call; ++} ++ ++// SW64 li48 bits: ++// ldi rd, msb_l(rd); ++// slll rd, 32, rd; ++// ldih rd, lsb_h(rd); ++// ldi rd, lsb_l(rd); ++// call ra, rd, (hint) ++// setfpec1 ++// ++class NativeMovConstReg: public NativeInstruction { ++ public: ++ enum sw64_specific_constants { ++ instruction_offset = 0, ++ instruction_size = 4 * BytesPerInstWord, ++ next_instruction_offset = 4 * BytesPerInstWord, ++ }; ++ ++ int insn_word() const { return long_at(instruction_offset); } ++ address instruction_address() const { return addr_at(0); } ++ address next_instruction_address() const { return addr_at(next_instruction_offset); } ++ intptr_t data() const; ++ void set_data(intptr_t x); ++ ++ void verify(); ++ void print(); ++ ++ // unit test stuff ++ static void test() {} ++ ++ // Creation ++ inline friend NativeMovConstReg* nativeMovConstReg_at(address address); ++ inline friend NativeMovConstReg* nativeMovConstReg_before(address address); ++}; ++ ++inline NativeMovConstReg* nativeMovConstReg_at(address address) { ++ NativeMovConstReg* test = (NativeMovConstReg*)(address - NativeMovConstReg::instruction_offset); ++#ifdef ASSERT ++ test->verify(); ++#endif ++ return test; ++} ++ ++inline NativeMovConstReg* nativeMovConstReg_before(address address) { ++ NativeMovConstReg* test = (NativeMovConstReg*)(address - NativeMovConstReg::instruction_size - NativeMovConstReg::instruction_offset); ++#ifdef ASSERT ++ test->verify(); ++#endif ++ return test; ++} ++ ++class NativeMovConstRegPatching: public NativeMovConstReg { ++ private: ++ friend NativeMovConstRegPatching* nativeMovConstRegPatching_at(address address) { ++ NativeMovConstRegPatching* test = (NativeMovConstRegPatching*)(address - instruction_offset); ++ #ifdef ASSERT ++ test->verify(); ++ #endif ++ return test; ++ } ++}; ++ ++ ++class NativeMovRegMem: public NativeInstruction { ++ public: ++ enum sw64_specific_constants { ++ instruction_offset = 0, ++ hiword_offset = 4, ++ ldst_offset = 12, ++ immediate_size = 4, ++ ldst_size = 16 ++ }; ++ ++ //offset is less than 16 bits. ++ bool is_immediate() const { return !is_op(long_at(instruction_offset), Assembler::op_ldih); } ++ bool is_64ldst() const { ++ if (is_immediate()) { ++ return (Assembler::opcode(long_at(hiword_offset)) == Assembler::opcode(long_at(instruction_offset))) && ++ (Assembler::imm_off(long_at(hiword_offset)) == Assembler::imm_off(long_at(instruction_offset)) + wordSize); ++ } else { ++ return (Assembler::opcode(long_at(ldst_offset+hiword_offset)) == Assembler::opcode(long_at(ldst_offset))) && ++ (Assembler::imm_off(long_at(ldst_offset+hiword_offset)) == Assembler::imm_off(long_at(ldst_offset)) + wordSize); ++ } ++ } ++ ++ address instruction_address() const { return addr_at(instruction_offset); } ++ address next_instruction_address() const { ++ return addr_at( (is_immediate()? immediate_size : ldst_size) + (is_64ldst()? 4 : 0)); ++ } ++ ++ int offset() const; ++ ++ void set_offset(int x); ++ ++ void add_offset_in_bytes(int add_offset) { set_offset ( ( offset() + add_offset ) ); } ++ ++ void verify(); ++ void print (); ++ ++ // unit test stuff ++ static void test() {} ++ ++ private: ++ inline friend NativeMovRegMem* nativeMovRegMem_at (address address); ++}; ++ ++inline NativeMovRegMem* nativeMovRegMem_at (address address) { ++ NativeMovRegMem* test = (NativeMovRegMem*)(address - NativeMovRegMem::instruction_offset); ++#ifdef ASSERT ++ test->verify(); ++#endif ++ return test; ++} ++ ++class NativeMovRegMemPatching: public NativeMovRegMem { ++ private: ++ friend NativeMovRegMemPatching* nativeMovRegMemPatching_at (address address) { ++ NativeMovRegMemPatching* test = (NativeMovRegMemPatching*)(address - instruction_offset); ++ #ifdef ASSERT ++ test->verify(); ++ #endif ++ return test; ++ } ++}; ++ ++ ++// SW64 li64 bits: ++// ldih rd, msb_h(R0); ++// ldi rd, msb_l(rd); ++// slll rd, 32, rd; ++// ldih rd, lsb_h(rd); ++// ldi rd, lsb_l(rd); ++// call ra, rd, (hint) ++// setfpec1 ++// ++ ++class NativeGeneralJump: public NativeInstruction { ++public: ++ enum sw64_specific_constants { ++ instruction_offset = 0, ++// instruction_size = 5 * BytesPerInstWord ++ }; ++ static int instruction_size; //This member variable can be reassigned in the bytecodes_sw64.cpp when SafePatch is true. ++ ++ bool is_short() { ++ int x = long_at(0); ++ int op = Assembler::sw2_op(x); ++ if(op >= Assembler::op_beq && op <= Assembler::op_fbge) ++ return true; ++ return false; ++ } ++ address instruction_address() const { return addr_at(instruction_offset); } ++ address jump_destination(); ++ ++ void set_jump_destination(address dest); ++ ++ // Creation ++ inline friend NativeGeneralJump* nativeGeneralJump_at(address address); ++ ++ // Insertion of native general jump instruction ++ static void check_verified_entry_alignment(address entry, address verified_entry){} ++ static void patch_verified_entry(address entry, address verified_entry, address dest); ++ ++ void verify(); ++}; ++ ++inline NativeGeneralJump* nativeGeneralJump_at(address address) { ++ NativeGeneralJump* jump = (NativeGeneralJump*)(address); ++ debug_only(jump->verify();) ++ return jump; ++} ++ ++ ++class NativeIllegalInstruction: public NativeInstruction { ++public: ++ enum sw64_specific_constants { ++ instruction_code = 0x0000DEAD, // Special instruction ++ instruction_size = 4, ++ instruction_offset = 0, ++ next_instruction_offset = 4 ++ }; ++ ++ // Insert illegal opcode as specific address ++ static void insert(address code_pos); ++}; ++ ++// return instruction that does not pop values of the stack for sw64. ++// call RA ++// setfpec1 ++class NativeReturn: public NativeInstruction { ++ public: ++ enum sw64_specific_constants { ++ instruction_size = 8, ++ instruction_offset = 0, ++ next_instruction_offset = 8 ++ }; ++}; ++ ++ ++ ++ ++class NativeCondJump; ++inline NativeCondJump* nativeCondJump_at(address address); ++class NativeCondJump: public NativeInstruction { ++ public: ++ enum sw64_specific_constants { ++ instruction_size = 16, ++ instruction_offset = 12, ++ next_instruction_offset = 20 ++ }; ++ ++ ++ int insn_word() const { return long_at(instruction_offset); } ++ address instruction_address() const { return addr_at(0); } ++ address next_instruction_address() const { return addr_at(next_instruction_offset); } ++ ++ // Creation ++ inline friend NativeCondJump* nativeCondJump_at(address address); ++ ++ address jump_destination() const { ++ return ::nativeCondJump_at(addr_at(12))->jump_destination(); ++ } ++ ++ void set_jump_destination(address dest) { ++ ::nativeCondJump_at(addr_at(12))->set_jump_destination(dest); ++ } ++ ++}; ++ ++inline NativeCondJump* nativeCondJump_at(address address) { ++ NativeCondJump* jump = (NativeCondJump*)(address); ++ return jump; ++} ++ ++ ++ ++inline bool NativeInstruction::is_illegal() { return insn_word() == illegal_instruction(); } ++ ++inline bool NativeInstruction::is_call() { ++ ++ if (is_op(long_at(0), Assembler::op_call)&&is_op(long_at(4), Assembler::op_setfpec1)){ ++ return true; ++ } ++ ++ /* li64 or li48 */ ++ if (is_op(long_at(0), Assembler::op_ldih)) { ++ /* li64 */ ++ return is_op(long_at(0),Assembler::op_ldih) && ++ is_op(int_at(4), Assembler::op_ldi) && ++ is_op(int_at(8), Assembler::op_slll_l) && ++ is_op(int_at(12), Assembler::op_ldih) && ++ is_op(int_at(16), Assembler::op_ldi) && ++ is_op(long_at(24), Assembler::op_call); ++ } else { ++ /* li48 */ ++ if (SafePatch) { ++ return (is_op(int_at(0), Assembler::op_ldi) && ++ is_op(int_at(4), Assembler::op_br) && ++ is_op(int_at(16), Assembler::op_ldl) )|| (is_op(int_at(0), Assembler::op_br) && ++ is_op(int_at(12), Assembler::op_ldl) && ++ is_op(int_at(16), Assembler::op_ldi) ); ++ } else { ++ return is_op(long_at(0),Assembler::op_ldi) && ++ is_op(int_at(4), Assembler::op_slll_l) && ++ is_op(int_at(8), Assembler::op_ldih) && ++ is_op(int_at(12), Assembler::op_ldi) && ++ is_op(long_at(16), Assembler::op_call); ++ } ++ } ++} ++ ++inline bool NativeInstruction::is_return() { ++ return is_op(Assembler::op_jmp) && is_rs(RA); ++} ++ ++inline bool NativeInstruction::is_cond_jump(){ ++ int x = long_at(0); ++ int op = Assembler::sw2_op(x); ++ if(op>=Assembler::op_beq && op<=Assembler::op_fbge) ++ return true; ++ return false; ++} ++ ++#endif // CPU_SW64_VM_NATIVEINST_SW64_HPP ++ +diff --git a/hotspot/src/cpu/sw64/vm/registerMap_sw64.hpp b/hotspot/src/cpu/sw64/vm/registerMap_sw64.hpp +new file mode 100755 +index 0000000000..d77615c437 +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/registerMap_sw64.hpp +@@ -0,0 +1,47 @@ ++/* ++ * Copyright (c) 1998, 2010, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_SW64_VM_REGISTERMAP_SW64_HPP ++#define CPU_SW64_VM_REGISTERMAP_SW64_HPP ++ ++// machine-dependent implemention for register maps ++ friend class frame; ++ ++ private: ++#ifndef CORE ++ // This is the hook for finding a register in an "well-known" location, ++ // such as a register block of a predetermined format. ++ // Since there is none, we just return NULL. ++ // See registerMap_sparc.hpp for an example of grabbing registers ++ // from register save areas of a standard layout. ++ address pd_location(VMReg reg) const {return NULL;} ++#endif ++ ++ // no PD state to clear or copy: ++ void pd_clear() {} ++ void pd_initialize() {} ++ void pd_initialize_from(const RegisterMap* map) {} ++ ++#endif // CPU_SW64_VM_REGISTERMAP_SW64_HPP ++ +diff --git a/hotspot/src/cpu/sw64/vm/register_definitions_sw64.cpp b/hotspot/src/cpu/sw64/vm/register_definitions_sw64.cpp +new file mode 100755 +index 0000000000..0b0fb16f07 +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/register_definitions_sw64.cpp +@@ -0,0 +1,98 @@ ++/* ++ * Copyright (c) 2002, 2013, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#include "precompiled.hpp" ++#include "asm/assembler.hpp" ++#include "asm/register.hpp" ++#include "register_sw64.hpp" ++#include "interp_masm_sw64.hpp" ++ ++ ++REGISTER_DEFINITION(Register, noreg); ++REGISTER_DEFINITION(Register, i0); ++REGISTER_DEFINITION(Register, i1); ++REGISTER_DEFINITION(Register, i2); ++REGISTER_DEFINITION(Register, i3); ++REGISTER_DEFINITION(Register, i4); ++REGISTER_DEFINITION(Register, i5); ++REGISTER_DEFINITION(Register, i6); ++REGISTER_DEFINITION(Register, i7); ++REGISTER_DEFINITION(Register, i8); ++REGISTER_DEFINITION(Register, i9); ++REGISTER_DEFINITION(Register, i10); ++REGISTER_DEFINITION(Register, i11); ++REGISTER_DEFINITION(Register, i12); ++REGISTER_DEFINITION(Register, i13); ++REGISTER_DEFINITION(Register, i14); ++REGISTER_DEFINITION(Register, i15); ++REGISTER_DEFINITION(Register, i16); ++REGISTER_DEFINITION(Register, i17); ++REGISTER_DEFINITION(Register, i18); ++REGISTER_DEFINITION(Register, i19); ++REGISTER_DEFINITION(Register, i20); ++REGISTER_DEFINITION(Register, i21); ++REGISTER_DEFINITION(Register, i22); ++REGISTER_DEFINITION(Register, i23); ++REGISTER_DEFINITION(Register, i24); ++REGISTER_DEFINITION(Register, i25); ++REGISTER_DEFINITION(Register, i26); ++REGISTER_DEFINITION(Register, i27); ++REGISTER_DEFINITION(Register, i28); ++REGISTER_DEFINITION(Register, i29); ++REGISTER_DEFINITION(Register, i30); ++REGISTER_DEFINITION(Register, i31); ++ ++REGISTER_DEFINITION(FloatRegister, fnoreg); ++REGISTER_DEFINITION(FloatRegister, f0); ++REGISTER_DEFINITION(FloatRegister, f1); ++REGISTER_DEFINITION(FloatRegister, f2); ++REGISTER_DEFINITION(FloatRegister, f3); ++REGISTER_DEFINITION(FloatRegister, f4); ++REGISTER_DEFINITION(FloatRegister, f5); ++REGISTER_DEFINITION(FloatRegister, f6); ++REGISTER_DEFINITION(FloatRegister, f7); ++REGISTER_DEFINITION(FloatRegister, f8); ++REGISTER_DEFINITION(FloatRegister, f9); ++REGISTER_DEFINITION(FloatRegister, f10); ++REGISTER_DEFINITION(FloatRegister, f11); ++REGISTER_DEFINITION(FloatRegister, f12); ++REGISTER_DEFINITION(FloatRegister, f13); ++REGISTER_DEFINITION(FloatRegister, f14); ++REGISTER_DEFINITION(FloatRegister, f15); ++REGISTER_DEFINITION(FloatRegister, f16); ++REGISTER_DEFINITION(FloatRegister, f17); ++REGISTER_DEFINITION(FloatRegister, f18); ++REGISTER_DEFINITION(FloatRegister, f19); ++REGISTER_DEFINITION(FloatRegister, f20); ++REGISTER_DEFINITION(FloatRegister, f21); ++REGISTER_DEFINITION(FloatRegister, f22); ++REGISTER_DEFINITION(FloatRegister, f23); ++REGISTER_DEFINITION(FloatRegister, f24); ++REGISTER_DEFINITION(FloatRegister, f25); ++REGISTER_DEFINITION(FloatRegister, f26); ++REGISTER_DEFINITION(FloatRegister, f27); ++REGISTER_DEFINITION(FloatRegister, f28); ++REGISTER_DEFINITION(FloatRegister, f29); ++REGISTER_DEFINITION(FloatRegister, f30); ++REGISTER_DEFINITION(FloatRegister, f31); +diff --git a/hotspot/src/cpu/sw64/vm/register_sw64.cpp b/hotspot/src/cpu/sw64/vm/register_sw64.cpp +new file mode 100755 +index 0000000000..653326c1a4 +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/register_sw64.cpp +@@ -0,0 +1,52 @@ ++/* ++ * Copyright (c) 2000, 2012, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#include "precompiled.hpp" ++#include "register_sw64.hpp" ++ ++const int ConcreteRegisterImpl::max_gpr = RegisterImpl::number_of_registers << 1; ++const int ConcreteRegisterImpl::max_fpr = ConcreteRegisterImpl::max_gpr + ++ 2 * FloatRegisterImpl::number_of_registers; ++ ++ ++const char* RegisterImpl::name() const { ++ const char* names[number_of_registers] = { ++ "v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6", ++ "t7", "s0", "s1", "s2", "s3", "s4", "s5", "fp", ++ "a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9", ++ "t10", "t11", "ra", "t12", "at", "gp", "sp", "zero" ++ }; ++ return is_valid() ? names[encoding()] : "noreg"; ++} ++ ++const char* FloatRegisterImpl::name() const { ++ const char* names[number_of_registers] = { ++ "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", ++ "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", ++ "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", ++ "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31" ++ }; ++ return is_valid() ? names[encoding()] : "fnoreg"; ++} ++ +diff --git a/hotspot/src/cpu/sw64/vm/register_sw64.hpp b/hotspot/src/cpu/sw64/vm/register_sw64.hpp +new file mode 100755 +index 0000000000..3f6722316c +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/register_sw64.hpp +@@ -0,0 +1,332 @@ ++/* ++ * Copyright (c) 2000, 2012, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_SW64_VM_REGISTER_SW64_HPP ++#define CPU_SW64_VM_REGISTER_SW64_HPP ++ ++#include "asm/register.hpp" ++#include "vm_version_sw64.hpp" ++ ++class VMRegImpl; ++typedef VMRegImpl* VMReg; ++ ++// Use Register as shortcut ++class RegisterImpl; ++typedef RegisterImpl* Register; ++ ++ ++// The implementation of integer registers for the SW64 architecture ++inline Register as_Register(int encoding) { ++ return (Register)(intptr_t) encoding; ++} ++ ++class RegisterImpl: public AbstractRegisterImpl { ++ public: ++ enum { ++ number_of_registers = 32 ++ }; ++ ++ // derived registers, offsets, and addresses ++ Register successor() const { return as_Register(encoding() + 1); } ++ ++ // construction ++ inline friend Register as_Register(int encoding); ++ ++ VMReg as_VMReg(); ++ ++ // accessors ++ int encoding() const { assert(is_valid(),err_msg( "invalid register (%d)", (int)(intptr_t)this)); return (intptr_t)this; } ++ bool is_valid() const { return 0 <= (intptr_t)this && (intptr_t)this < number_of_registers; } ++ const char* name() const; ++}; ++ ++ ++// The integer registers of the SW64 architecture ++CONSTANT_REGISTER_DECLARATION(Register, noreg, (-1)); ++ ++ ++CONSTANT_REGISTER_DECLARATION(Register, i0, (0)); ++CONSTANT_REGISTER_DECLARATION(Register, i1, (1)); ++CONSTANT_REGISTER_DECLARATION(Register, i2, (2)); ++CONSTANT_REGISTER_DECLARATION(Register, i3, (3)); ++CONSTANT_REGISTER_DECLARATION(Register, i4, (4)); ++CONSTANT_REGISTER_DECLARATION(Register, i5, (5)); ++CONSTANT_REGISTER_DECLARATION(Register, i6, (6)); ++CONSTANT_REGISTER_DECLARATION(Register, i7, (7)); ++CONSTANT_REGISTER_DECLARATION(Register, i8, (8)); ++CONSTANT_REGISTER_DECLARATION(Register, i9, (9)); ++CONSTANT_REGISTER_DECLARATION(Register, i10, (10)); ++CONSTANT_REGISTER_DECLARATION(Register, i11, (11)); ++CONSTANT_REGISTER_DECLARATION(Register, i12, (12)); ++CONSTANT_REGISTER_DECLARATION(Register, i13, (13)); ++CONSTANT_REGISTER_DECLARATION(Register, i14, (14)); ++CONSTANT_REGISTER_DECLARATION(Register, i15, (15)); ++CONSTANT_REGISTER_DECLARATION(Register, i16, (16)); ++CONSTANT_REGISTER_DECLARATION(Register, i17, (17)); ++CONSTANT_REGISTER_DECLARATION(Register, i18, (18)); ++CONSTANT_REGISTER_DECLARATION(Register, i19, (19)); ++CONSTANT_REGISTER_DECLARATION(Register, i20, (20)); ++CONSTANT_REGISTER_DECLARATION(Register, i21, (21)); ++CONSTANT_REGISTER_DECLARATION(Register, i22, (22)); ++CONSTANT_REGISTER_DECLARATION(Register, i23, (23)); ++CONSTANT_REGISTER_DECLARATION(Register, i24, (24)); ++CONSTANT_REGISTER_DECLARATION(Register, i25, (25)); ++CONSTANT_REGISTER_DECLARATION(Register, i26, (26)); ++CONSTANT_REGISTER_DECLARATION(Register, i27, (27)); ++CONSTANT_REGISTER_DECLARATION(Register, i28, (28)); ++CONSTANT_REGISTER_DECLARATION(Register, i29, (29)); ++CONSTANT_REGISTER_DECLARATION(Register, i30, (30)); ++CONSTANT_REGISTER_DECLARATION(Register, i31, (31)); ++ ++#ifndef DONT_USE_REGISTER_DEFINES ++#define NOREG ((Register)(noreg_RegisterEnumValue)) ++ ++#define I0 ((Register)(i0_RegisterEnumValue)) ++#define I1 ((Register)(i1_RegisterEnumValue)) ++#define I2 ((Register)(i2_RegisterEnumValue)) ++#define I3 ((Register)(i3_RegisterEnumValue)) ++#define I4 ((Register)(i4_RegisterEnumValue)) ++#define I5 ((Register)(i5_RegisterEnumValue)) ++#define I6 ((Register)(i6_RegisterEnumValue)) ++#define I7 ((Register)(i7_RegisterEnumValue)) ++#define I8 ((Register)(i8_RegisterEnumValue)) ++#define I9 ((Register)(i9_RegisterEnumValue)) ++#define I10 ((Register)(i10_RegisterEnumValue)) ++#define I11 ((Register)(i11_RegisterEnumValue)) ++#define I12 ((Register)(i12_RegisterEnumValue)) ++#define I13 ((Register)(i13_RegisterEnumValue)) ++#define I14 ((Register)(i14_RegisterEnumValue)) ++#define I15 ((Register)(i15_RegisterEnumValue)) ++#define I16 ((Register)(i16_RegisterEnumValue)) ++#define I17 ((Register)(i17_RegisterEnumValue)) ++#define I18 ((Register)(i18_RegisterEnumValue)) ++#define I19 ((Register)(i19_RegisterEnumValue)) ++#define I20 ((Register)(i20_RegisterEnumValue)) ++#define I21 ((Register)(i21_RegisterEnumValue)) ++#define I22 ((Register)(i22_RegisterEnumValue)) ++#define I23 ((Register)(i23_RegisterEnumValue)) ++#define I24 ((Register)(i24_RegisterEnumValue)) ++#define I25 ((Register)(i25_RegisterEnumValue)) ++#define I26 ((Register)(i26_RegisterEnumValue)) ++#define I27 ((Register)(i27_RegisterEnumValue)) ++#define I28 ((Register)(i28_RegisterEnumValue)) ++#define I29 ((Register)(i29_RegisterEnumValue)) ++#define I30 ((Register)(i30_RegisterEnumValue)) ++#define I31 ((Register)(i31_RegisterEnumValue)) ++ ++ ++#define V0 ((Register)(i0_RegisterEnumValue)) ++#define T0 ((Register)(i1_RegisterEnumValue)) ++#define T1 ((Register)(i2_RegisterEnumValue)) ++#define T2 ((Register)(i3_RegisterEnumValue)) ++#define T3 ((Register)(i4_RegisterEnumValue)) ++#define T4 ((Register)(i5_RegisterEnumValue)) ++#define T5 ((Register)(i6_RegisterEnumValue)) ++#define T6 ((Register)(i7_RegisterEnumValue)) ++#define T7 ((Register)(i8_RegisterEnumValue)) ++#define S0 ((Register)(i9_RegisterEnumValue)) ++#define S1 ((Register)(i10_RegisterEnumValue)) ++#define S2 ((Register)(i11_RegisterEnumValue)) ++#define S3 ((Register)(i12_RegisterEnumValue)) ++#define S4 ((Register)(i13_RegisterEnumValue)) ++#define S5 ((Register)(i14_RegisterEnumValue)) ++#define FP ((Register)(i15_RegisterEnumValue)) ++#define A0 ((Register)(i16_RegisterEnumValue)) ++#define A1 ((Register)(i17_RegisterEnumValue)) ++#define A2 ((Register)(i18_RegisterEnumValue)) ++#define A3 ((Register)(i19_RegisterEnumValue)) ++#define A4 ((Register)(i20_RegisterEnumValue)) ++#define A5 ((Register)(i21_RegisterEnumValue)) ++#define T8 ((Register)(i22_RegisterEnumValue)) ++#define T9 ((Register)(i23_RegisterEnumValue)) ++#define T10 ((Register)(i24_RegisterEnumValue)) ++#define T11 ((Register)(i25_RegisterEnumValue)) ++#define RA ((Register)(i26_RegisterEnumValue)) ++#define T12 ((Register)(i27_RegisterEnumValue)) ++#define AT ((Register)(i28_RegisterEnumValue)) ++#define GP ((Register)(i29_RegisterEnumValue)) ++#define SP ((Register)(i30_RegisterEnumValue)) ++#define R0 ((Register)(i31_RegisterEnumValue)) ++ ++ ++#define c_rarg0 T0 ++#define c_rarg1 T1 ++#define Rmethod S3 ++#define Rsender S4 ++#define Rnext T8 ++ ++#define RT0 T0 ++#define RT1 T1 ++#define RT2 T2 ++#define RT3 T3 ++#define RT4 T11 ++#define RT5 T12 ++ ++//for interpreter frame ++// bytecode pointer register ++#define BCP S0 ++// local variable pointer register ++#define LVP S1 ++ ++#define OPT_SAFEPOINT 1 ++#define S2thread S2 ++#define S5_heapbase S5 ++#define mh_SP_save SP ++ ++#define FSR V0 ++#define SSR T4 ++#define FSF F0 ++#define SSF F1 ++#define FTF F14 ++#define STF F15 ++ ++#define AFT F30 ++#define FcmpRES F29 ++ ++#define IC_Klass T1 ++ ++#endif // DONT_USE_REGISTER_DEFINES ++ ++// Use FloatRegister as shortcut ++class FloatRegisterImpl; ++typedef FloatRegisterImpl* FloatRegister; ++ ++inline FloatRegister as_FloatRegister(int encoding) { ++ return (FloatRegister)(intptr_t) encoding; ++} ++ ++// The implementation of floating point registers for the SW64 architecture ++class FloatRegisterImpl: public AbstractRegisterImpl { ++ public: ++ enum { ++ float_arg_base = 16, ++ number_of_registers = 32 ++ }; ++ ++ // construction ++ inline friend FloatRegister as_FloatRegister(int encoding); ++ ++ VMReg as_VMReg(); ++ ++ // derived registers, offsets, and addresses ++ FloatRegister successor() const { return as_FloatRegister(encoding() + 1); } ++ ++ // accessors ++ int encoding() const { assert(is_valid(), "invalid register"); return (intptr_t)this; } ++ bool is_valid() const { return 0 <= (intptr_t)this && (intptr_t)this < number_of_registers; } ++ const char* name() const; ++ ++}; ++ ++CONSTANT_REGISTER_DECLARATION(FloatRegister, fnoreg , (-1)); ++ ++CONSTANT_REGISTER_DECLARATION(FloatRegister, f0 , ( 0)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, f1 , ( 1)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, f2 , ( 2)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, f3 , ( 3)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, f4 , ( 4)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, f5 , ( 5)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, f6 , ( 6)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, f7 , ( 7)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, f8 , ( 8)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, f9 , ( 9)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, f10 , (10)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, f11 , (11)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, f12 , (12)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, f13 , (13)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, f14 , (14)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, f15 , (15)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, f16 , (16)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, f17 , (17)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, f18 , (18)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, f19 , (19)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, f20 , (20)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, f21 , (21)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, f22 , (22)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, f23 , (23)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, f24 , (24)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, f25 , (25)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, f26 , (26)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, f27 , (27)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, f28 , (28)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, f29 , (29)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, f30 , (30)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, f31 , (31)); ++ ++#ifndef DONT_USE_REGISTER_DEFINES ++#define FNOREG ((FloatRegister)(fnoreg_FloatRegisterEnumValue)) ++#define F0 ((FloatRegister)( f0_FloatRegisterEnumValue)) ++#define F1 ((FloatRegister)( f1_FloatRegisterEnumValue)) ++#define F2 ((FloatRegister)( f2_FloatRegisterEnumValue)) ++#define F3 ((FloatRegister)( f3_FloatRegisterEnumValue)) ++#define F4 ((FloatRegister)( f4_FloatRegisterEnumValue)) ++#define F5 ((FloatRegister)( f5_FloatRegisterEnumValue)) ++#define F6 ((FloatRegister)( f6_FloatRegisterEnumValue)) ++#define F7 ((FloatRegister)( f7_FloatRegisterEnumValue)) ++#define F8 ((FloatRegister)( f8_FloatRegisterEnumValue)) ++#define F9 ((FloatRegister)( f9_FloatRegisterEnumValue)) ++#define F10 ((FloatRegister)( f10_FloatRegisterEnumValue)) ++#define F11 ((FloatRegister)( f11_FloatRegisterEnumValue)) ++#define F12 ((FloatRegister)( f12_FloatRegisterEnumValue)) ++#define F13 ((FloatRegister)( f13_FloatRegisterEnumValue)) ++#define F14 ((FloatRegister)( f14_FloatRegisterEnumValue)) ++#define F15 ((FloatRegister)( f15_FloatRegisterEnumValue)) ++#define F16 ((FloatRegister)( f16_FloatRegisterEnumValue)) ++#define F17 ((FloatRegister)( f17_FloatRegisterEnumValue)) ++#define F18 ((FloatRegister)( f18_FloatRegisterEnumValue)) ++#define F19 ((FloatRegister)( f19_FloatRegisterEnumValue)) ++#define F20 ((FloatRegister)( f20_FloatRegisterEnumValue)) ++#define F21 ((FloatRegister)( f21_FloatRegisterEnumValue)) ++#define F22 ((FloatRegister)( f22_FloatRegisterEnumValue)) ++#define F23 ((FloatRegister)( f23_FloatRegisterEnumValue)) ++#define F24 ((FloatRegister)( f24_FloatRegisterEnumValue)) ++#define F25 ((FloatRegister)( f25_FloatRegisterEnumValue)) ++#define F26 ((FloatRegister)( f26_FloatRegisterEnumValue)) ++#define F27 ((FloatRegister)( f27_FloatRegisterEnumValue)) ++#define F28 ((FloatRegister)( f28_FloatRegisterEnumValue)) ++#define F29 ((FloatRegister)( f29_FloatRegisterEnumValue)) ++#define F30 ((FloatRegister)( f30_FloatRegisterEnumValue)) ++#define F31 ((FloatRegister)( f31_FloatRegisterEnumValue)) ++#endif // DONT_USE_REGISTER_DEFINES ++ ++ ++// Need to know the total number of registers of all sorts for SharedInfo. ++// Define a class that exports it. ++class ConcreteRegisterImpl : public AbstractRegisterImpl { ++ public: ++ enum { ++ // A big enough number for C2: all the registers plus flags ++ // This number must be large enough to cover REG_COUNT (defined by c2) registers. ++ // There is no requirement that any ordering here matches any ordering c2 gives ++ // it's optoregs. ++ number_of_registers = (RegisterImpl::number_of_registers + FloatRegisterImpl::number_of_registers) ++ LP64_ONLY( * 2) ++ }; ++ ++ static const int max_gpr; ++ static const int max_fpr; ++ ++ ++}; ++#endif //CPU_SW64_VM_REGISTER_SW64_HPP +diff --git a/hotspot/src/cpu/sw64/vm/relocInfo_sw64.cpp b/hotspot/src/cpu/sw64/vm/relocInfo_sw64.cpp +new file mode 100755 +index 0000000000..f37225bd29 +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/relocInfo_sw64.cpp +@@ -0,0 +1,126 @@ ++/* ++ * Copyright (c) 1998, 2013, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#include "precompiled.hpp" ++#include "asm/macroAssembler.hpp" ++#include "code/relocInfo.hpp" ++#include "nativeInst_sw64.hpp" ++#include "oops/oop.inline.hpp" ++#include "runtime/safepoint.hpp" ++ ++ ++void Relocation::pd_set_data_value(address x, intptr_t o, bool verify_only) { ++ x += o; ++ typedef Assembler::WhichOperand WhichOperand; ++ WhichOperand which = (WhichOperand) format(); // that is, disp32 or imm, call32, narrow oop ++ assert(which == Assembler::disp32_operand || ++ which == Assembler::narrow_oop_operand || ++ which == Assembler::imm_operand, "format unpacks ok"); ++ if (which == Assembler::imm_operand) { ++ if (verify_only) { ++ assert(nativeMovConstReg_at(addr())->data() == (long)x, "instructions must match"); ++ } else { ++ nativeMovConstReg_at(addr())->set_data((intptr_t)(x)); ++ } ++ } else if (which == Assembler::narrow_oop_operand) { ++ // both compressed oops and compressed classes look the same ++ if (Universe::heap()->is_in_reserved((oop)x)) { ++ if (verify_only) { ++ assert(nativeMovConstReg_at(addr())->data() == (long)oopDesc::encode_heap_oop((oop)x), "instructions must match"); ++ } else { ++ nativeMovConstReg_at(addr())->set_data((intptr_t)(oopDesc::encode_heap_oop((oop)x))); ++ } ++ } else { ++ if (verify_only) { ++ assert(nativeMovConstReg_at(addr())->data() == (long)Klass::encode_klass((Klass*)x), "instructions must match"); ++ } else { ++ nativeMovConstReg_at(addr())->set_data((intptr_t)(Klass::encode_klass((Klass*)x))); ++ } ++ } ++ } else { ++ // Note: Use runtime_call_type relocations for call32_operand. ++ assert(0, "call32_operand not supported in SW64"); ++ } ++} ++ ++ ++//NOTICE HERE, this relocate is not need for SW64, since SW64 USE abosolutly target, ++//Maybe We should FORGET CALL RELOCATION ++address Relocation::pd_call_destination(address orig_addr) { ++ intptr_t adj = 0; ++ NativeInstruction* ni = nativeInstruction_at(addr()); ++ if (ni->is_call()) { ++ return nativeCall_at(addr())->destination() + adj; ++ } else if (ni->is_jump()) { ++ return nativeGeneralJump_at(addr())->jump_destination() + adj; ++ } else if (ni->is_cond_jump()) { ++ return nativeCondJump_at(addr())->jump_destination() +adj; ++ } else { ++ tty->print_cr("\nError!\ncall destination: 0x%lx", addr()); ++ Disassembler::decode(addr() - 10 * 4, addr() + 10 * 4, tty); ++ ShouldNotReachHere(); ++ return NULL; ++ } ++} ++ ++ ++void Relocation::pd_set_call_destination(address x) { ++ NativeInstruction* ni = nativeInstruction_at(addr()); ++ if (ni->is_call()) { ++ nativeCall_at(addr())->set_destination(x); ++ } else if (ni->is_jump()) ++ nativeGeneralJump_at(addr())->set_jump_destination(x); ++ else if (ni->is_cond_jump()) ++ nativeCondJump_at(addr())->set_jump_destination(x); ++ else ++ { ShouldNotReachHere(); } ++ ++ // Unresolved jumps are recognized by a destination of -1 ++ // However 64bit can't actually produce such an address ++ // and encodes a jump to self but jump_destination will ++ // return a -1 as the signal. We must not relocate this ++ // jmp or the ic code will not see it as unresolved. ++} ++ ++ ++address* Relocation::pd_address_in_code() { ++ return (address*)addr(); ++} ++ ++ ++address Relocation::pd_get_address_from_code() { ++ NativeMovConstReg* ni = nativeMovConstReg_at(addr()); ++ return (address)ni->data(); ++} ++ ++ ++ ++void poll_Relocation::fix_relocation_after_move(const CodeBuffer* src, CodeBuffer* dest) { ++} ++ ++void poll_return_Relocation::fix_relocation_after_move(const CodeBuffer* src, CodeBuffer* dest) { ++} ++ ++void metadata_Relocation::pd_fix_value(address x) { ++} +diff --git a/hotspot/src/cpu/sw64/vm/relocInfo_sw64.hpp b/hotspot/src/cpu/sw64/vm/relocInfo_sw64.hpp +new file mode 100755 +index 0000000000..96120d3e2d +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/relocInfo_sw64.hpp +@@ -0,0 +1,39 @@ ++/* ++ * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_SW64_VM_RELOCINFO_SW64_HPP ++#define CPU_SW64_VM_RELOCINFO_SW64_HPP ++ ++ // machine-dependent parts of class relocInfo ++ private: ++ enum { ++ // Since SW64 instructions are whole words, ++ // the two low-order offset bits can always be discarded. ++ offset_unit = 4, ++ ++ // imm_oop_operand vs. narrow_oop_operand ++ format_width = 2 ++ }; ++ ++#endif // CPU_SW64_VM_RELOCINFO_SW64_HPP +diff --git a/hotspot/src/cpu/sw64/vm/runtime_sw64.cpp b/hotspot/src/cpu/sw64/vm/runtime_sw64.cpp +new file mode 100755 +index 0000000000..a0762103be +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/runtime_sw64.cpp +@@ -0,0 +1,189 @@ ++/* ++ * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#include "precompiled.hpp" ++#ifdef COMPILER2 ++#include "asm/macroAssembler.hpp" ++#include "asm/macroAssembler.inline.hpp" ++#include "classfile/systemDictionary.hpp" ++#include "code/vmreg.hpp" ++#include "interpreter/interpreter.hpp" ++#include "opto/runtime.hpp" ++#include "runtime/interfaceSupport.hpp" ++#include "runtime/sharedRuntime.hpp" ++#include "runtime/stubRoutines.hpp" ++#include "runtime/vframeArray.hpp" ++#include "utilities/globalDefinitions.hpp" ++#include "vmreg_sw64.inline.hpp" ++#endif ++ ++#define __ masm-> ++ ++//-------------- generate_exception_blob ----------- ++// creates _exception_blob. ++// The exception blob is jumped to from a compiled method. ++// (see emit_exception_handler in sparc.ad file) ++// ++// Given an exception pc at a call we call into the runtime for the ++// handler in this method. This handler might merely restore state ++// (i.e. callee save registers) unwind the frame and jump to the ++// exception handler for the nmethod if there is no Java level handler ++// for the nmethod. ++// ++// This code is entered with a jump, and left with a jump. ++// ++// Arguments: ++// V0: exception oop ++// T4: exception pc ++// ++// Results: ++// A0: exception oop ++// A1: exception pc in caller or ??? ++// jumps to: exception handler of caller ++// ++// Note: the exception pc MUST be at a call (precise debug information) ++// ++// [stubGenerator_sw64.cpp] generate_forward_exception() ++// |- V0, T4 are created ++// |- T12 <= SharedRuntime::exception_handler_for_return_address ++// `- jr T12 ++// `- the caller's exception_handler ++// `- jr OptoRuntime::exception_blob ++// `- here ++// ++void OptoRuntime::generate_exception_blob() { ++ // Capture info about frame layout ++ enum layout { ++ fp_off, ++ return_off, // slot for return address ++ framesize ++ }; ++ ++ // allocate space for the code ++ ResourceMark rm; ++ // setup code generation tools ++ CodeBuffer buffer("exception_blob", 5120, 5120); ++ MacroAssembler* masm = new MacroAssembler(&buffer); ++ ++ ++ address start = __ pc(); ++ ++ __ add_simm16(SP, SP, -1 * framesize * wordSize); // Prolog! ++ ++ // this frame will be treated as the original caller method. ++ // So, the return pc should be filled with the original exception pc. ++ // ref: X86's implementation ++ __ stl(T4, SP, return_off *wordSize); // return address ++ __ stl(FP, SP, fp_off *wordSize); ++ ++ // Save callee saved registers. None for UseSSE=0, ++ // floats-only for UseSSE=1, and doubles for UseSSE=2. ++ ++ __ add_simm16(FP, SP, fp_off * wordSize); ++ ++ // Store exception in Thread object. We cannot pass any arguments to the ++ // handle_exception call, since we do not want to make any assumption ++ // about the size of the frame where the exception happened in. ++ Register thread = S2thread; ++ ++ __ stl(V0, Address(thread, JavaThread::exception_oop_offset())); ++ __ stl(T4, Address(thread, JavaThread::exception_pc_offset())); ++ ++ // This call does all the hard work. It checks if an exception handler ++ // exists in the method. ++ // If so, it returns the handler address. ++ // If not, it prepares for stack-unwinding, restoring the callee-save ++ // registers of the frame being removed. ++ __ set_last_Java_frame(thread, NOREG, NOREG, NULL); ++ ++ __ move(AT, -(StackAlignmentInBytes)); ++ __ and_reg(SP, SP, AT); // Fix stack alignment as required by ABI ++ ++#ifdef ZHJ20180909 ++ __ relocate(relocInfo::internal_pc_type); ++ { ++ long save_pc = (long)__ pc() + 24 + NativeCall::return_address_offset; ++ __ patchable_set48(AT, save_pc); ++ } ++#else ++ { ++ if(UseAddpi){ ++ intptr_t patch_off = 2 + NativeCall::return_address_offset/BytesPerInstWord; ++ __ addpi(patch_off, AT); ++ }else { ++ intptr_t patch_off = 3 * BytesPerInstWord + NativeCall::return_address_offset; ++ __ br(AT, 0); ++ __ addl(AT, AT, patch_off); ++ } ++ } ++#endif ++ __ stl(AT, thread, in_bytes(JavaThread::last_Java_pc_offset())); ++ ++ __ move(A0, thread); ++ __ patchable_call_setfpec1((address)OptoRuntime::handle_exception_C); ++ ++ // Set an oopmap for the call site ++ OopMapSet *oop_maps = new OopMapSet(); ++ OopMap* map = new OopMap( framesize, 0 ); ++ ++ oop_maps->add_gc_map( __ offset() - 4, map); ++ ++ __ reset_last_Java_frame(thread, true); ++ ++ // Pop self-frame. ++ __ leave(); // Epilog! ++ ++ // V0: exception handler ++ ++ // We have a handler in V0, (could be deopt blob) ++ __ move(T12, V0); ++ ++ // Get the exception ++ __ ldl(A0, Address(thread, JavaThread::exception_oop_offset())); ++ // Get the exception pc in case we are deoptimized ++ __ ldl(A1, Address(thread, JavaThread::exception_pc_offset())); ++#ifdef ASSERT ++ __ stl(R0, Address(thread, JavaThread::exception_handler_pc_offset())); ++ __ stl(R0, Address(thread, JavaThread::exception_pc_offset())); ++#endif ++ // Clear the exception oop so GC no longer processes it as a root. ++ __ stl(R0, Address(thread, JavaThread::exception_oop_offset())); ++ ++ // Fix seg fault when running: ++ // Eclipse + Plugin + Debug As ++ // This is the only condition where C2 calls SharedRuntime::generate_deopt_blob() ++ // ++ __ move(V0, A0); ++ __ move(T4, A1); ++ ++ // V0: exception oop ++ // T12: exception handler ++ // A1: exception pc ++ __ jmp(T12); ++ ++ // make sure all code is generated ++ masm->flush(); ++ ++ _exception_blob = ExceptionBlob::create(&buffer, oop_maps, framesize); ++} +diff --git a/hotspot/src/cpu/sw64/vm/sharedRuntime_sw64.cpp b/hotspot/src/cpu/sw64/vm/sharedRuntime_sw64.cpp +new file mode 100755 +index 0000000000..f75d2e08b8 +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/sharedRuntime_sw64.cpp +@@ -0,0 +1,3848 @@ ++/* ++ * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#include "precompiled.hpp" ++#include "asm/macroAssembler.hpp" ++#include "asm/macroAssembler.inline.hpp" ++#include "code/debugInfoRec.hpp" ++#include "code/icBuffer.hpp" ++#include "code/vtableStubs.hpp" ++#include "interpreter/interpreter.hpp" ++#include "oops/compiledICHolder.hpp" ++#include "prims/jvmtiRedefineClassesTrace.hpp" ++#include "runtime/sharedRuntime.hpp" ++#include "runtime/vframeArray.hpp" ++#include "vmreg_sw64.inline.hpp" ++#ifdef COMPILER1 ++#include "c1/c1_Runtime1.hpp" ++#endif ++#ifdef COMPILER2 ++#include "opto/runtime.hpp" ++#endif ++ ++#include ++ ++#define __ masm-> ++ ++#ifdef PRODUCT ++#define BLOCK_COMMENT(str) /* nothing */ ++#else ++#define BLOCK_COMMENT(str) { char line[1024];sprintf(line,"%s:%s:%d",str,__FILE__, __LINE__); __ block_comment(line);} ++#endif ++ ++#define BIND(label) bind(label); BLOCK_COMMENT(#label ":") ++ ++const int StackAlignmentInSlots = StackAlignmentInBytes / VMRegImpl::stack_slot_size; ++ ++class RegisterSaver { ++ enum { FPU_regs_live = 32 }; ++ // Capture info about frame layout ++ enum layout { ++#define DEF_LAYOUT_OFFS(regname) regname ## _off, regname ## H_off, ++ DEF_LAYOUT_OFFS(for_16_bytes_aligned) ++ DEF_LAYOUT_OFFS(fpr0) ++ DEF_LAYOUT_OFFS(fpr1) ++ DEF_LAYOUT_OFFS(fpr2) ++ DEF_LAYOUT_OFFS(fpr3) ++ DEF_LAYOUT_OFFS(fpr4) ++ DEF_LAYOUT_OFFS(fpr5) ++ DEF_LAYOUT_OFFS(fpr6) ++ DEF_LAYOUT_OFFS(fpr7) ++ DEF_LAYOUT_OFFS(fpr8) ++ DEF_LAYOUT_OFFS(fpr9) ++ DEF_LAYOUT_OFFS(fpr10) ++ DEF_LAYOUT_OFFS(fpr11) ++ DEF_LAYOUT_OFFS(fpr12) ++ DEF_LAYOUT_OFFS(fpr13) ++ DEF_LAYOUT_OFFS(fpr14) ++ DEF_LAYOUT_OFFS(fpr15) ++ DEF_LAYOUT_OFFS(fpr16) ++ DEF_LAYOUT_OFFS(fpr17) ++ DEF_LAYOUT_OFFS(fpr18) ++ DEF_LAYOUT_OFFS(fpr19) ++ DEF_LAYOUT_OFFS(fpr20) ++ DEF_LAYOUT_OFFS(fpr21) ++ DEF_LAYOUT_OFFS(fpr22) ++ DEF_LAYOUT_OFFS(fpr23) ++ DEF_LAYOUT_OFFS(fpr24) ++ DEF_LAYOUT_OFFS(fpr25) ++ DEF_LAYOUT_OFFS(fpr26) ++ DEF_LAYOUT_OFFS(fpr27) ++ DEF_LAYOUT_OFFS(fpr28) ++ DEF_LAYOUT_OFFS(fpr29) ++ DEF_LAYOUT_OFFS(fpr30) ++ DEF_LAYOUT_OFFS(fpr31) ++ ++ DEF_LAYOUT_OFFS(v0) ++ DEF_LAYOUT_OFFS(t0) ++ DEF_LAYOUT_OFFS(t1) ++ DEF_LAYOUT_OFFS(t2) ++ DEF_LAYOUT_OFFS(t3) ++ DEF_LAYOUT_OFFS(t4) ++ DEF_LAYOUT_OFFS(t5) ++ DEF_LAYOUT_OFFS(t6) ++ DEF_LAYOUT_OFFS(t7) ++ DEF_LAYOUT_OFFS(s0) ++ DEF_LAYOUT_OFFS(s1) ++ DEF_LAYOUT_OFFS(s2) ++ DEF_LAYOUT_OFFS(s3) ++ DEF_LAYOUT_OFFS(s4) ++ DEF_LAYOUT_OFFS(s5) ++ // FP move down ++ DEF_LAYOUT_OFFS(a0) ++ DEF_LAYOUT_OFFS(a1) ++ DEF_LAYOUT_OFFS(a2) ++ DEF_LAYOUT_OFFS(a3) ++ DEF_LAYOUT_OFFS(a4) ++ DEF_LAYOUT_OFFS(a5) ++ DEF_LAYOUT_OFFS(t8) ++ DEF_LAYOUT_OFFS(t9) ++ DEF_LAYOUT_OFFS(t10) ++ DEF_LAYOUT_OFFS(t11) ++ // RA move down ++ DEF_LAYOUT_OFFS(t12) ++ // no AT ++ DEF_LAYOUT_OFFS(gp) ++ // no SP ++ // no R0 ++ DEF_LAYOUT_OFFS(fp) ++ DEF_LAYOUT_OFFS(return) ++ reg_save_size ++ }; ++ ++ public: ++ ++ static OopMap* save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words, bool save_vectors =false ); ++ static void restore_live_registers(MacroAssembler* masm, bool restore_vectors = false); ++ static int raOffset(void) { return return_off / 2; } ++ //Rmethod ++ static int methodOffset(void) { return s3_off / 2; } ++ ++ static int v0Offset(void) { return v0_off / 2; } ++ ++ static int fpResultOffset(void) { return fpr0_off / 2; } ++ ++ // During deoptimization only the result register need to be restored ++ // all the other values have already been extracted. ++ static void restore_result_registers(MacroAssembler* masm); ++}; ++ ++OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words, bool save_vectors ) { ++ ++ // Always make the frame size 16-byte aligned ++ int frame_size_in_bytes = round_to(additional_frame_words*wordSize + ++ reg_save_size*BytesPerInt, 16); ++ // OopMap frame size is in compiler stack slots (jint's) not bytes or words ++ int frame_size_in_slots = frame_size_in_bytes / BytesPerInt; ++ // The caller will allocate additional_frame_words ++ int additional_frame_slots = additional_frame_words*wordSize / BytesPerInt; ++ // CodeBlob frame size is in words. ++ int frame_size_in_words = frame_size_in_bytes / wordSize; ++ *total_frame_words = frame_size_in_words; ++ ++ // save registers ++ ++ __ add_simm16(SP, SP, - reg_save_size * jintSize); ++ ++ __ fstd(F0, SP, fpr0_off * jintSize); __ fstd(F1, SP, fpr1_off * jintSize); ++ __ fstd(F2, SP, fpr2_off * jintSize); __ fstd(F3, SP, fpr3_off * jintSize); ++ __ fstd(F4, SP, fpr4_off * jintSize); __ fstd(F5, SP, fpr5_off * jintSize); ++ __ fstd(F6, SP, fpr6_off * jintSize); __ fstd(F7, SP, fpr7_off * jintSize); ++ __ fstd(F8, SP, fpr8_off * jintSize); __ fstd(F9, SP, fpr9_off * jintSize); ++ __ fstd(F10, SP, fpr10_off * jintSize); __ fstd(F11, SP, fpr11_off * jintSize); ++ __ fstd(F12, SP, fpr12_off * jintSize); __ fstd(F13, SP, fpr13_off * jintSize); ++ __ fstd(F14, SP, fpr14_off * jintSize); __ fstd(F15, SP, fpr15_off * jintSize); ++ __ fstd(F16, SP, fpr16_off * jintSize); __ fstd(F17, SP, fpr17_off * jintSize); ++ __ fstd(F18, SP, fpr18_off * jintSize); __ fstd(F19, SP, fpr19_off * jintSize); ++ __ fstd(F20, SP, fpr20_off * jintSize); __ fstd(F21, SP, fpr21_off * jintSize); ++ __ fstd(F22, SP, fpr22_off * jintSize); __ fstd(F23, SP, fpr23_off * jintSize); ++ __ fstd(F24, SP, fpr24_off * jintSize); __ fstd(F25, SP, fpr25_off * jintSize); ++ __ fstd(F26, SP, fpr26_off * jintSize); __ fstd(F27, SP, fpr27_off * jintSize); ++ __ fstd(F28, SP, fpr28_off * jintSize); __ fstd(F29, SP, fpr29_off * jintSize); ++ __ fstd(F30, SP, fpr30_off * jintSize); ++ __ stl(V0, SP, v0_off * jintSize); ++ __ stl(T0, SP, t0_off * jintSize); ++ __ stl(T1, SP, t1_off * jintSize); ++ __ stl(T2, SP, t2_off * jintSize); ++ __ stl(T3, SP, t3_off * jintSize); ++ __ stl(T4, SP, t4_off * jintSize); ++ __ stl(T5, SP, t5_off * jintSize); ++ __ stl(T6, SP, t6_off * jintSize); ++ __ stl(T7, SP, t7_off * jintSize); ++ __ stl(S0, SP, s0_off * jintSize); ++ __ stl(S1, SP, s1_off * jintSize); ++ __ stl(S2, SP, s2_off * jintSize); ++ __ stl(S3, SP, s3_off * jintSize); ++ __ stl(S4, SP, s4_off * jintSize); ++ __ stl(S5, SP, s5_off * jintSize); ++ __ stl(A0, SP, a0_off * jintSize); __ stl(A1, SP, a1_off * jintSize); ++ __ stl(A2, SP, a2_off * jintSize); __ stl(A3, SP, a3_off * jintSize); ++ __ stl(A4, SP, a4_off * jintSize); __ stl(A5, SP, a5_off * jintSize); ++ __ stl(T8, SP, t8_off * jintSize); ++ __ stl(T9, SP, t9_off * jintSize); ++ __ stl(T10, SP, t10_off * jintSize); ++ __ stl(T11, SP, t11_off * jintSize); ++ __ stl(T12, SP, t12_off * jintSize); ++ ++ __ stl(GP, SP, gp_off * jintSize); ++ __ stl(FP, SP, fp_off * jintSize); ++ __ stl(RA, SP, return_off * jintSize); ++ __ add_simm16(FP, SP, fp_off * jintSize); ++ ++ OopMapSet *oop_maps = new OopMapSet(); ++ OopMap* map = new OopMap( frame_size_in_slots, 0 ); ++ ++ ++#define STACK_OFFSET(x) VMRegImpl::stack2reg((x) + additional_frame_slots) ++ map->set_callee_saved(STACK_OFFSET( v0_off), V0->as_VMReg()); ++ map->set_callee_saved(STACK_OFFSET( t0_off), T0->as_VMReg()); ++ map->set_callee_saved(STACK_OFFSET( t1_off), T1->as_VMReg()); ++ map->set_callee_saved(STACK_OFFSET( t2_off), T2->as_VMReg()); ++ map->set_callee_saved(STACK_OFFSET( t3_off), T3->as_VMReg()); ++ map->set_callee_saved(STACK_OFFSET( t4_off), T4->as_VMReg()); ++ map->set_callee_saved(STACK_OFFSET( t5_off), T5->as_VMReg()); ++ map->set_callee_saved(STACK_OFFSET( t6_off), T6->as_VMReg()); ++ map->set_callee_saved(STACK_OFFSET( t7_off), T7->as_VMReg()); ++ map->set_callee_saved(STACK_OFFSET( s0_off), S0->as_VMReg()); ++ map->set_callee_saved(STACK_OFFSET( s1_off), S1->as_VMReg()); ++ map->set_callee_saved(STACK_OFFSET( s2_off), S2->as_VMReg()); ++ map->set_callee_saved(STACK_OFFSET( s3_off), S3->as_VMReg()); ++ map->set_callee_saved(STACK_OFFSET( s4_off), S4->as_VMReg()); ++ map->set_callee_saved(STACK_OFFSET( s5_off), S5->as_VMReg()); ++ map->set_callee_saved(STACK_OFFSET( a0_off), A0->as_VMReg()); ++ map->set_callee_saved(STACK_OFFSET( a1_off), A1->as_VMReg()); ++ map->set_callee_saved(STACK_OFFSET( a2_off), A2->as_VMReg()); ++ map->set_callee_saved(STACK_OFFSET( a3_off), A3->as_VMReg()); ++ map->set_callee_saved(STACK_OFFSET( a4_off), A4->as_VMReg()); ++ map->set_callee_saved(STACK_OFFSET( a5_off), A5->as_VMReg()); ++ map->set_callee_saved(STACK_OFFSET( t8_off), T8->as_VMReg()); ++ map->set_callee_saved(STACK_OFFSET( t9_off), T9->as_VMReg()); ++ map->set_callee_saved(STACK_OFFSET( t10_off), T10->as_VMReg()); ++ map->set_callee_saved(STACK_OFFSET( t11_off), T11->as_VMReg()); ++ map->set_callee_saved(STACK_OFFSET( t12_off), T12->as_VMReg()); ++ map->set_callee_saved(STACK_OFFSET( gp_off), GP->as_VMReg()); ++ map->set_callee_saved(STACK_OFFSET( fp_off), FP->as_VMReg()); ++ map->set_callee_saved(STACK_OFFSET( return_off), RA->as_VMReg()); ++ ++ map->set_callee_saved(STACK_OFFSET( fpr0_off), F0->as_VMReg()); ++ map->set_callee_saved(STACK_OFFSET( fpr1_off), F1->as_VMReg()); ++ map->set_callee_saved(STACK_OFFSET( fpr2_off), F2->as_VMReg()); ++ map->set_callee_saved(STACK_OFFSET( fpr3_off), F3->as_VMReg()); ++ map->set_callee_saved(STACK_OFFSET( fpr4_off), F4->as_VMReg()); ++ map->set_callee_saved(STACK_OFFSET( fpr5_off), F5->as_VMReg()); ++ map->set_callee_saved(STACK_OFFSET( fpr6_off), F6->as_VMReg()); ++ map->set_callee_saved(STACK_OFFSET( fpr7_off), F7->as_VMReg()); ++ map->set_callee_saved(STACK_OFFSET( fpr8_off), F8->as_VMReg()); ++ map->set_callee_saved(STACK_OFFSET( fpr9_off), F9->as_VMReg()); ++ map->set_callee_saved(STACK_OFFSET( fpr10_off), F10->as_VMReg()); ++ map->set_callee_saved(STACK_OFFSET( fpr11_off), F11->as_VMReg()); ++ map->set_callee_saved(STACK_OFFSET( fpr12_off), F12->as_VMReg()); ++ map->set_callee_saved(STACK_OFFSET( fpr13_off), F13->as_VMReg()); ++ map->set_callee_saved(STACK_OFFSET( fpr14_off), F14->as_VMReg()); ++ map->set_callee_saved(STACK_OFFSET( fpr15_off), F15->as_VMReg()); ++ map->set_callee_saved(STACK_OFFSET( fpr16_off), F16->as_VMReg()); ++ map->set_callee_saved(STACK_OFFSET( fpr17_off), F17->as_VMReg()); ++ map->set_callee_saved(STACK_OFFSET( fpr18_off), F18->as_VMReg()); ++ map->set_callee_saved(STACK_OFFSET( fpr19_off), F19->as_VMReg()); ++ map->set_callee_saved(STACK_OFFSET( fpr20_off), F20->as_VMReg()); ++ map->set_callee_saved(STACK_OFFSET( fpr21_off), F21->as_VMReg()); ++ map->set_callee_saved(STACK_OFFSET( fpr22_off), F22->as_VMReg()); ++ map->set_callee_saved(STACK_OFFSET( fpr23_off), F23->as_VMReg()); ++ map->set_callee_saved(STACK_OFFSET( fpr24_off), F24->as_VMReg()); ++ map->set_callee_saved(STACK_OFFSET( fpr25_off), F25->as_VMReg()); ++ map->set_callee_saved(STACK_OFFSET( fpr26_off), F26->as_VMReg()); ++ map->set_callee_saved(STACK_OFFSET( fpr27_off), F27->as_VMReg()); ++ map->set_callee_saved(STACK_OFFSET( fpr28_off), F28->as_VMReg()); ++ map->set_callee_saved(STACK_OFFSET( fpr29_off), F29->as_VMReg()); ++ map->set_callee_saved(STACK_OFFSET( fpr30_off), F30->as_VMReg()); ++ ++#undef STACK_OFFSET ++ return map; ++} ++ ++ ++// Pop the current frame and restore all the registers that we ++// saved. ++void RegisterSaver::restore_live_registers(MacroAssembler* masm, bool restore_vectors) { ++ __ fldd(F0, SP, fpr0_off * jintSize); __ fldd(F1, SP, fpr1_off * jintSize); ++ __ fldd(F2, SP, fpr2_off * jintSize); __ fldd(F3, SP, fpr3_off * jintSize); ++ __ fldd(F4, SP, fpr4_off * jintSize); __ fldd(F5, SP, fpr5_off * jintSize); ++ __ fldd(F6, SP, fpr6_off * jintSize); __ fldd(F7, SP, fpr7_off * jintSize); ++ __ fldd(F8, SP, fpr8_off * jintSize); __ fldd(F9, SP, fpr9_off * jintSize); ++ __ fldd(F10, SP, fpr10_off * jintSize); __ fldd(F11, SP, fpr11_off * jintSize); ++ __ fldd(F12, SP, fpr12_off * jintSize); __ fldd(F13, SP, fpr13_off * jintSize); ++ __ fldd(F14, SP, fpr14_off * jintSize); __ fldd(F15, SP, fpr15_off * jintSize); ++ __ fldd(F16, SP, fpr16_off * jintSize); __ fldd(F17, SP, fpr17_off * jintSize); ++ __ fldd(F18, SP, fpr18_off * jintSize); __ fldd(F19, SP, fpr19_off * jintSize); ++ __ fldd(F20, SP, fpr20_off * jintSize); __ fldd(F21, SP, fpr21_off * jintSize); ++ __ fldd(F22, SP, fpr22_off * jintSize); __ fldd(F23, SP, fpr23_off * jintSize); ++ __ fldd(F24, SP, fpr24_off * jintSize); __ fldd(F25, SP, fpr25_off * jintSize); ++ __ fldd(F26, SP, fpr26_off * jintSize); __ fldd(F27, SP, fpr27_off * jintSize); ++ __ fldd(F28, SP, fpr28_off * jintSize); __ fldd(F29, SP, fpr29_off * jintSize); ++ __ fldd(F30, SP, fpr30_off * jintSize); ++ ++ __ ldl(V0, SP, v0_off * jintSize); ++ __ ldl(T0, SP, t0_off * jintSize); ++ __ ldl(T1, SP, t1_off * jintSize); ++ __ ldl(T2, SP, t2_off * jintSize); ++ __ ldl(T3, SP, t3_off * jintSize); ++ __ ldl(T4, SP, t4_off * jintSize); ++ __ ldl(T5, SP, t5_off * jintSize); ++ __ ldl(T6, SP, t6_off * jintSize); ++ __ ldl(T7, SP, t7_off * jintSize); ++ __ ldl(S0, SP, s0_off * jintSize); ++ __ ldl(S1, SP, s1_off * jintSize); ++ __ ldl(S2, SP, s2_off * jintSize); ++ __ ldl(S3, SP, s3_off * jintSize); ++ __ ldl(S4, SP, s4_off * jintSize); ++ __ ldl(S5, SP, s5_off * jintSize); ++ __ ldl(A0, SP, a0_off * jintSize); __ ldl(A1, SP, a1_off * jintSize); ++ __ ldl(A2, SP, a2_off * jintSize); __ ldl(A3, SP, a3_off * jintSize); ++ __ ldl(A4, SP, a4_off * jintSize); __ ldl(A5, SP, a5_off * jintSize); ++ __ ldl(T8, SP, t8_off * jintSize); ++ __ ldl(T9, SP, t9_off * jintSize); ++ __ ldl(T10, SP, t10_off * jintSize); ++ __ ldl(T11, SP, t11_off * jintSize); ++ __ ldl(T12, SP, t12_off * jintSize); ++ ++ __ ldl(GP, SP, gp_off * jintSize); ++ __ ldl(FP, SP, fp_off * jintSize); ++ __ ldl(RA, SP, return_off * jintSize); ++ ++ __ add_simm16(SP, SP, reg_save_size * jintSize); ++} ++ ++// Pop the current frame and restore the registers that might be holding ++// a result. ++void RegisterSaver::restore_result_registers(MacroAssembler* masm) { ++ ++ // Just restore result register. Only used by deoptimization. By ++ // now any callee save register that needs to be restore to a c2 ++ // caller of the deoptee has been extracted into the vframeArray ++ // and will be stuffed into the c2i adapter we create for later ++ // restoration so only result registers need to be restored here. ++ ++ __ ldl(V0, SP, v0_off * jintSize); ++ __ add_simm16(SP, SP, return_off * jintSize); ++} ++ ++// Is vector's size (in bytes) bigger than a size saved by default? ++// 16 bytes XMM registers are saved by default using fxsave/fxrstor instructions. ++bool SharedRuntime::is_wide_vector(int size) { ++ return size > 16; ++} ++ ++// The java_calling_convention describes stack locations as ideal slots on ++// a frame with no abi restrictions. Since we must observe abi restrictions ++// (like the placement of the register window) the slots must be biased by ++// the following value. ++ ++static int reg2offset_in(VMReg r) { ++ // Account for saved fp and return address ++ // This should really be in_preserve_stack_slots ++ return (r->reg2stack() + 2 * VMRegImpl::slots_per_word) * VMRegImpl::stack_slot_size; // + 2 * VMRegImpl::stack_slot_size); ++} ++ ++static int reg2offset_out(VMReg r) { ++ return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size; ++} ++ ++// --------------------------------------------------------------------------- ++// Read the array of BasicTypes from a signature, and compute where the ++// arguments should go. Values in the VMRegPair regs array refer to 4-byte ++// quantities. Values less than SharedInfo::stack0 are registers, those above ++// refer to 4-byte stack slots. All stack slots are based off of the stack pointer ++// as framesizes are fixed. ++// VMRegImpl::stack0 refers to the first slot 0(sp). ++// and VMRegImpl::stack0+1 refers to the memory word 4-byes higher. Register ++// up to RegisterImpl::number_of_registers) are the 32-bit ++// integer registers. ++ ++// Pass first five oop/int args in registers T0, A0 - A3. ++// Pass float/double/long args in stack. ++// Doubles have precedence, so if you pass a mix of floats and doubles ++// the doubles will grab the registers before the floats will. ++ ++// Note: the INPUTS in sig_bt are in units of Java argument words, which are ++// either 32-bit or 64-bit depending on the build. The OUTPUTS are in 32-bit ++// units regardless of build. ++ ++ ++// --------------------------------------------------------------------------- ++// The compiled Java calling convention. ++// Pass first five oop/int args in registers T0, A0 - A3. ++// Pass float/double/long args in stack. ++// Doubles have precedence, so if you pass a mix of floats and doubles ++// the doubles will grab the registers before the floats will. ++ ++int SharedRuntime::java_calling_convention(const BasicType *sig_bt, ++ VMRegPair *regs, ++ int total_args_passed, ++ int is_outgoing) { ++ ++ // Create the mapping between argument positions and ++ // registers. ++ static const Register INT_ArgReg[Argument::n_register_parameters] = { ++ A1, A2, A3, A4, A5, A0 ++ }; ++ ++ static const FloatRegister FP_ArgReg[Argument::n_float_register_parameters] = { ++ F16, F17, F18, F19, F20, F21 ++ }; ++ ++ ++ uint args = 0; ++ uint stk_args = 0; // inc by 2 each time ++ ++ for (int i = 0; i < total_args_passed; i++) { ++ switch (sig_bt[i]) { ++ case T_VOID: ++ // halves of T_LONG or T_DOUBLE ++ assert(i != 0 && (sig_bt[i - 1] == T_LONG || sig_bt[i - 1] == T_DOUBLE), "expecting half"); ++ regs[i].set_bad(); ++ break; ++ case T_BOOLEAN: ++ case T_CHAR: ++ case T_BYTE: ++ case T_SHORT: ++ case T_INT: ++ if (args < Argument::n_register_parameters) { ++ regs[i].set1(INT_ArgReg[args++]->as_VMReg()); ++ } else { ++ regs[i].set1(VMRegImpl::stack2reg(stk_args)); ++ stk_args += 2; ++ } ++ break; ++ case T_LONG: ++ assert(sig_bt[i + 1] == T_VOID, "expecting half"); ++ // fall through ++ case T_OBJECT: ++ case T_ARRAY: ++ case T_ADDRESS: ++ if (args < Argument::n_register_parameters) { ++ regs[i].set2(INT_ArgReg[args++]->as_VMReg()); ++ } else { ++ regs[i].set2(VMRegImpl::stack2reg(stk_args)); ++ stk_args += 2; ++ } ++ break; ++ case T_FLOAT: ++ if (args < Argument::n_float_register_parameters) { ++ regs[i].set1(FP_ArgReg[args++]->as_VMReg()); ++ } else { ++ regs[i].set1(VMRegImpl::stack2reg(stk_args)); ++ stk_args += 2; ++ } ++ break; ++ case T_DOUBLE: ++ assert(sig_bt[i + 1] == T_VOID, "expecting half"); ++ if (args < Argument::n_float_register_parameters) { ++ regs[i].set2(FP_ArgReg[args++]->as_VMReg()); ++ } else { ++ regs[i].set2(VMRegImpl::stack2reg(stk_args)); ++ stk_args += 2; ++ } ++ break; ++ default: ++ ShouldNotReachHere(); ++ break; ++ } ++ } ++ ++ return round_to(stk_args, 2); ++} ++ ++// Helper class mostly to avoid passing masm everywhere, and handle store ++// displacement overflow logic for LP64 ++class AdapterGenerator { ++ MacroAssembler *masm; ++ Register Rdisp; ++ void set_Rdisp(Register r) { Rdisp = r; } ++ ++ void patch_callers_callsite(); ++ ++ // base+st_off points to top of argument ++ int arg_offset(const int st_off) { return st_off; } ++ int next_arg_offset(const int st_off) { ++ return st_off - Interpreter::stackElementSize; ++ } ++ ++ // On _LP64 argument slot values are loaded first into a register ++ // because they might not fit into displacement. ++ Register arg_slot(const int st_off); ++ Register next_arg_slot(const int st_off); ++ ++ // Stores long into offset pointed to by base ++ void store_c2i_long(Register r, Register base, ++ const int st_off, bool is_stack); ++ void store_c2i_object(Register r, Register base, ++ const int st_off); ++ void store_c2i_int(Register r, Register base, ++ const int st_off); ++ void store_c2i_double(VMReg r_2, ++ VMReg r_1, Register base, const int st_off); ++ void store_c2i_float(FloatRegister f, Register base, ++ const int st_off); ++ ++ public: ++ //void tag_stack(const BasicType sig, int st_off); ++ void gen_c2i_adapter(int total_args_passed, ++ // VMReg max_arg, ++ int comp_args_on_stack, // VMRegStackSlots ++ const BasicType *sig_bt, ++ const VMRegPair *regs, ++ Label& skip_fixup); ++ void gen_i2c_adapter(int total_args_passed, ++ // VMReg max_arg, ++ int comp_args_on_stack, // VMRegStackSlots ++ const BasicType *sig_bt, ++ const VMRegPair *regs); ++ ++ AdapterGenerator(MacroAssembler *_masm) : masm(_masm) {} ++}; ++ ++ ++// Patch the callers callsite with entry to compiled code if it exists. ++void AdapterGenerator::patch_callers_callsite() { ++ Label L; ++ // __ verify_oop(Rmethod); ++ __ ld_ptr(AT, Rmethod, in_bytes(Method::code_offset())); ++ __ beq(AT, L); ++ // Schedule the branch target address early. ++ // Call into the VM to patch the caller, then jump to compiled callee ++ // V0 isn't live so capture return address while we easily can ++ __ move(V0, RA); ++ ++ __ pushad(); ++#ifdef COMPILER2 ++ // C2 may leave the stack dirty if not in SSE2+ mode ++ __ empty_FPU_stack(); ++#endif ++ ++ // VM needs caller's callsite ++ // VM needs target method ++ ++ __ move(A0, Rmethod); ++ __ move(A1, V0); ++//we should preserve the return address ++ //__ verify_oop(Rmethod); ++ __ move(S0, SP); ++ __ move(AT, -(StackAlignmentInBytes)); // align the stack ++ __ and_reg(SP, SP, AT); ++ __ call(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite), ++ relocInfo::runtime_call_type); ++ ++ __ move(SP, S0); ++ __ popad(); ++ __ BIND(L); ++} ++ ++Register AdapterGenerator::arg_slot(const int st_off) { ++ Unimplemented(); ++} ++ ++Register AdapterGenerator::next_arg_slot(const int st_off){ ++ Unimplemented(); ++} ++ ++// Stores long into offset pointed to by base ++void AdapterGenerator::store_c2i_long(Register r, Register base, ++ const int st_off, bool is_stack) { ++ Unimplemented(); ++} ++ ++void AdapterGenerator::store_c2i_object(Register r, Register base, ++ const int st_off) { ++ Unimplemented(); ++} ++ ++void AdapterGenerator::store_c2i_int(Register r, Register base, ++ const int st_off) { ++ Unimplemented(); ++} ++ ++// Stores into offset pointed to by base ++void AdapterGenerator::store_c2i_double(VMReg r_2, ++ VMReg r_1, Register base, const int st_off) { ++ Unimplemented(); ++} ++ ++void AdapterGenerator::store_c2i_float(FloatRegister f, Register base, ++ const int st_off) { ++ Unimplemented(); ++} ++ ++void AdapterGenerator::gen_c2i_adapter( ++ int total_args_passed, ++ // VMReg max_arg, ++ int comp_args_on_stack, // VMRegStackSlots ++ const BasicType *sig_bt, ++ const VMRegPair *regs, ++ Label& skip_fixup) { ++ ++ // Before we get into the guts of the C2I adapter, see if we should be here ++ // at all. We've come from compiled code and are attempting to jump to the ++ // interpreter, which means the caller made a static call to get here ++ // (vcalls always get a compiled target if there is one). Check for a ++ // compiled target. If there is one, we need to patch the caller's call. ++ // However we will run interpreted if we come thru here. The next pass ++ // thru the call site will run compiled. If we ran compiled here then ++ // we can (theorectically) do endless i2c->c2i->i2c transitions during ++ // deopt/uncommon trap cycles. If we always go interpreted here then ++ // we can have at most one and don't need to play any tricks to keep ++ // from endlessly growing the stack. ++ // ++ // Actually if we detected that we had an i2c->c2i transition here we ++ // ought to be able to reset the world back to the state of the interpreted ++ // call and not bother building another interpreter arg area. We don't ++ // do that at this point. ++ ++ patch_callers_callsite(); ++ ++ __ BIND(skip_fixup); ++ ++#ifdef COMPILER2 ++ __ empty_FPU_stack(); ++#endif ++ //this is for native ? ++ // Since all args are passed on the stack, total_args_passed * interpreter_ ++ // stack_element_size is the ++ // space we need. ++ int extraspace = total_args_passed * Interpreter::stackElementSize; ++ ++ // stack is aligned, keep it that way ++ extraspace = round_to(extraspace, 2*wordSize); ++ ++ // Get return address ++ __ move(V0, RA); ++ // set senderSP value ++ __ move(Rsender, SP); ++ __ add_simm16(SP, SP, -extraspace); ++ ++ // Now write the args into the outgoing interpreter space ++ for (int i = 0; i < total_args_passed; i++) { ++ if (sig_bt[i] == T_VOID) { ++ assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half"); ++ continue; ++ } ++ ++ // st_off points to lowest address on stack. ++ int st_off = ((total_args_passed - 1) - i) * Interpreter::stackElementSize; ++ // Say 4 args: ++ // i st_off ++ // 0 12 T_LONG ++ // 1 8 T_VOID ++ // 2 4 T_OBJECT ++ // 3 0 T_BOOL ++ VMReg r_1 = regs[i].first(); ++ VMReg r_2 = regs[i].second(); ++ if (!r_1->is_valid()) { ++ assert(!r_2->is_valid(), ""); ++ continue; ++ } ++ if (r_1->is_stack()) { ++ // memory to memory use fpu stack top ++ int ld_off = r_1->reg2stack() * VMRegImpl::stack_slot_size + extraspace; ++ if (!r_2->is_valid()) { ++ __ ld_ptr(AT, SP, ld_off); ++ __ st_ptr(AT, SP, st_off); ++ ++ } else { ++ ++ ++ int next_off = st_off - Interpreter::stackElementSize; ++ __ ld_ptr(AT, SP, ld_off); ++ __ st_ptr(AT, SP, st_off); ++ ++ // Ref to is_Register condition ++ if(sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) ++ __ st_ptr(AT,SP,st_off - 8); ++ } ++ } else if (r_1->is_Register()) { ++ Register r = r_1->as_Register(); ++ if (!r_2->is_valid()) { ++ __ stl(r,SP, st_off); ++ } else { ++ // long/double in gpr ++ __ stl(r,SP, st_off); ++ // In [java/util/zip/ZipFile.java] ++ // ++ // private static native long open(String name, int mode, long lastModified); ++ // private static native int getTotal(long jzfile); ++ // ++ // We need to transfer T_LONG paramenters from a compiled method to a native method. ++ // It's a complex process: ++ // ++ // Caller -> lir_static_call -> gen_resolve_stub ++ // -> -- resolve_static_call_C ++ // `- gen_c2i_adapter() [*] ++ // | ++ // `- AdapterHandlerLibrary::get_create_apapter_index ++ // -> generate_native_entry ++ // -> InterpreterRuntime::SignatureHandlerGenerator::pass_long [**] ++ // ++ // In [**], T_Long parameter is stored in stack as: ++ // ++ // (high) ++ // | | ++ // ----------- ++ // | 8 bytes | ++ // | (void) | ++ // ----------- ++ // | 8 bytes | ++ // | (long) | ++ // ----------- ++ // | | ++ // (low) ++ // ++ // However, the sequence is reversed here: ++ // ++ // (high) ++ // | | ++ // ----------- ++ // | 8 bytes | ++ // | (long) | ++ // ----------- ++ // | 8 bytes | ++ // | (void) | ++ // ----------- ++ // | | ++ // (low) ++ // ++ // So I stored another 8 bytes in the T_VOID slot. It then can be accessed from generate_native_entry(). ++ // ++ if (sig_bt[i] == T_LONG) ++ __ stl(r,SP, st_off - 8); ++ } ++ } else if (r_1->is_FloatRegister()) { ++ assert(sig_bt[i] == T_FLOAT || sig_bt[i] == T_DOUBLE, "Must be a float register"); ++ ++ FloatRegister fr = r_1->as_FloatRegister(); ++ if (sig_bt[i] == T_FLOAT) ++ __ fsts(fr,SP, st_off); ++ else { ++ __ fstd(fr,SP, st_off); ++ __ fstd(fr,SP, st_off - 8); // T_DOUBLE needs two slots ++ } ++ } ++ } ++ ++ // Schedule the branch target address early. ++ __ ld_ptr(AT, Rmethod,in_bytes(Method::interpreter_entry_offset()) ); ++ // And repush original return address ++ __ move(RA, V0); ++ __ jmp(AT); ++} ++ ++void AdapterGenerator::gen_i2c_adapter(int total_args_passed, ++ // VMReg max_arg, ++ int comp_args_on_stack, // VMRegStackSlots ++ const BasicType *sig_bt, ++ const VMRegPair *regs) { ++ ++ // Generate an I2C adapter: adjust the I-frame to make space for the C-frame ++ // layout. Lesp was saved by the calling I-frame and will be restored on ++ // return. Meanwhile, outgoing arg space is all owned by the callee ++ // C-frame, so we can mangle it at will. After adjusting the frame size, ++ // hoist register arguments and repack other args according to the compiled ++ // code convention. Finally, end in a jump to the compiled code. The entry ++ // point address is the start of the buffer. ++ ++ // We will only enter here from an interpreted frame and never from after ++ // passing thru a c2i. Azul allowed this but we do not. If we lose the ++ // race and use a c2i we will remain interpreted for the race loser(s). ++ // the possibility of having c2i -> i2c -> c2i -> ... endless transitions. ++ ++ ++ __ move(T12, SP); ++ ++ // Cut-out for having no stack args. Since up to 2 int/oop args are passed ++ // in registers, we will occasionally have no stack args. ++ int comp_words_on_stack = 0; ++ if (comp_args_on_stack) { ++ // Sig words on the stack are greater-than VMRegImpl::stack0. Those in ++ // registers are below. By subtracting stack0, we either get a negative ++ // number (all values in registers) or the maximum stack slot accessed. ++ // int comp_args_on_stack = VMRegImpl::reg2stack(max_arg); ++ // Convert 4-byte stack slots to words. ++ comp_words_on_stack = round_to(comp_args_on_stack*4, wordSize)>>LogBytesPerWord; ++ // Round up to miminum stack alignment, in wordSize ++ comp_words_on_stack = round_to(comp_words_on_stack, 2); ++ __ add_simm16(SP, SP, -comp_words_on_stack * wordSize); ++ } ++ ++ // Align the outgoing SP ++ __ move(AT, -(StackAlignmentInBytes)); ++ __ and_reg(SP, SP, AT); ++ // push the return address on the stack (note that pushing, rather ++ // than storing it, yields the correct frame alignment for the callee) ++ // Put saved SP in another register ++ const Register saved_sp = V0; ++ __ move(saved_sp, T12); ++ ++ ++ // Will jump to the compiled code just as if compiled code was doing it. ++ // Pre-load the register-jump target early, to schedule it better. ++ __ ldl(T12, Rmethod, in_bytes(Method::from_compiled_offset())); ++ ++ // Now generate the shuffle code. Pick up all register args and move the ++ // rest through the floating point stack top. ++ for (int i = 0; i < total_args_passed; i++) { ++ if (sig_bt[i] == T_VOID) { ++ // Longs and doubles are passed in native word order, but misaligned ++ // in the 32-bit build. ++ assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half"); ++ continue; ++ } ++ ++ // Pick up 0, 1 or 2 words from SP+offset. ++ ++ //assert(!regs[i].second()->is_valid() || regs[i].first()->next() == regs[i].second(), "scrambled load targets?"); ++ // Load in argument order going down. ++ int ld_off = (total_args_passed -1 - i)*Interpreter::stackElementSize; ++ // Point to interpreter value (vs. tag) ++ int next_off = ld_off - Interpreter::stackElementSize; ++ VMReg r_1 = regs[i].first(); ++ VMReg r_2 = regs[i].second(); ++ if (!r_1->is_valid()) { ++ assert(!r_2->is_valid(), ""); ++ continue; ++ } ++ if (r_1->is_stack()) { ++ // Convert stack slot to an SP offset (+ wordSize to account for return address ) ++ int st_off = regs[i].first()->reg2stack()*VMRegImpl::stack_slot_size; ++ //+ wordSize; ++ ++ if (!r_2->is_valid()) { ++ __ ldl(AT, saved_sp, ld_off); ++ __ stl(AT, SP, st_off); ++ } else { ++ __ ldl(AT, saved_sp, ld_off); ++ if (sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) ++ __ ldl(AT, saved_sp, ld_off - 8); ++ __ stl(AT, SP, st_off); ++ } ++ } else if (r_1->is_Register()) { // Register argument ++ Register r = r_1->as_Register(); ++ if (r_2->is_valid()) { ++ // So r_2 gets loaded from high address regardless of the platform ++ assert(r_2->as_Register() == r_1->as_Register(), ""); ++ __ ldl(r, saved_sp, ld_off); ++ ++ // ++ // For T_LONG type, the real layout is as below: ++ // ++ // (high) ++ // | | ++ // ----------- ++ // | 8 bytes | ++ // | (void) | ++ // ----------- ++ // | 8 bytes | ++ // | (long) | ++ // ----------- ++ // | | ++ // (low) ++ // ++ // We should load the low-8 bytes. ++ // ++ if (sig_bt[i] == T_LONG) ++ __ ldl(r, saved_sp, ld_off - 8); ++ } else { ++ __ ldw(r, saved_sp, ld_off); ++ } ++ } else if (r_1->is_FloatRegister()) { // Float Register ++ assert(sig_bt[i] == T_FLOAT || sig_bt[i] == T_DOUBLE, "Must be a float register"); ++ ++ FloatRegister fr = r_1->as_FloatRegister(); ++ if (sig_bt[i] == T_FLOAT) ++ __ flds(fr, saved_sp, ld_off); ++ else { ++ __ fldd(fr, saved_sp, ld_off); ++ __ fldd(fr, saved_sp, ld_off - 8); ++ } ++ } ++ } ++ ++ // 6243940 We might end up in handle_wrong_method if ++ // the callee is deoptimized as we race thru here. If that ++ // happens we don't want to take a safepoint because the ++ // caller frame will look interpreted and arguments are now ++ // "compiled" so it is much better to make this transition ++ // invisible to the stack walking code. Unfortunately if ++ // we try and find the callee by normal means a safepoint ++ // is possible. So we stash the desired callee in the thread ++ // and the vm will find there should this case occur. ++ __ get_thread(T11); ++ __ stl(Rmethod, T11, in_bytes(JavaThread::callee_target_offset())); ++ ++ // move methodOop to V0 in case we end up in an c2i adapter. ++ // the c2i adapters expect methodOop in V0 (c2) because c2's ++ // resolve stubs return the result (the method) in V0. ++ // I'd love to fix this. ++ __ move(V0, Rmethod); ++ __ jmp(T12); ++} ++ ++// --------------------------------------------------------------- ++AdapterHandlerEntry* SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm, ++ int total_args_passed, ++ // VMReg max_arg, ++ int comp_args_on_stack, // VMRegStackSlots ++ const BasicType *sig_bt, ++ const VMRegPair *regs, ++ AdapterFingerPrint* fingerprint) { ++ address i2c_entry = __ pc(); ++ ++ AdapterGenerator agen(masm); ++ ++ agen.gen_i2c_adapter(total_args_passed, comp_args_on_stack, sig_bt, regs); ++ ++ ++ // ------------------------------------------------------------------------- ++ // Generate a C2I adapter. On entry we know S3 holds the methodOop. The ++ // args start out packed in the compiled layout. They need to be unpacked ++ // into the interpreter layout. This will almost always require some stack ++ // space. We grow the current (compiled) stack, then repack the args. We ++ // finally end in a jump to the generic interpreter entry point. On exit ++ // from the interpreter, the interpreter will restore our SP (lest the ++ // compiled code, which relys solely on SP and not FP, get sick). ++ ++ address c2i_unverified_entry = __ pc(); ++ Label skip_fixup; ++ { ++ Register holder = T1; ++ Register receiver = A1; ++ Register temp = T11; ++ address ic_miss = SharedRuntime::get_ic_miss_stub(); ++ ++ Label missed; ++ ++ __ verify_oop(holder); ++ //add for compressedoops ++ __ load_klass(temp, receiver); ++ __ verify_oop(temp); ++ ++ __ ld_ptr(AT, holder, CompiledICHolder::holder_klass_offset()); ++ __ ld_ptr(Rmethod, holder, CompiledICHolder::holder_metadata_offset()); ++ __ bne(AT, temp, missed); ++ // Method might have been compiled since the call site was patched to ++ // interpreted if that is the case treat it as a miss so we can get ++ // the call site corrected. ++ __ ld_ptr(AT, Rmethod, in_bytes(Method::code_offset())); ++ __ beq(AT, skip_fixup); ++ __ BIND(missed); ++ ++ __ jmp(ic_miss, relocInfo::runtime_call_type); ++ } ++ ++ address c2i_entry = __ pc(); ++ ++ agen.gen_c2i_adapter(total_args_passed, comp_args_on_stack, sig_bt, regs, skip_fixup); ++ ++ __ flush(); ++ return AdapterHandlerLibrary::new_entry(fingerprint,i2c_entry, c2i_entry, c2i_unverified_entry); ++} ++ ++int SharedRuntime::c_calling_convention(const BasicType *sig_bt, ++ VMRegPair *regs, ++ VMRegPair *regs2, ++ int total_args_passed) { ++ assert(regs2 == NULL, "not needed on SW64"); ++ // Return the number of VMReg stack_slots needed for the args. ++ // This value does not include an abi space (like register window ++ // save area). ++ ++ // The native convention is V8 if !LP64 ++ // The LP64 convention is the V9 convention which is slightly more sane. ++ ++ // We return the amount of VMReg stack slots we need to reserve for all ++ // the arguments NOT counting out_preserve_stack_slots. Since we always ++ // have space for storing at least 6 registers to memory we start with that. ++ // See int_stk_helper for a further discussion. ++ // We return the amount of VMRegImpl stack slots we need to reserve for all ++ // the arguments NOT counting out_preserve_stack_slots. ++ static const Register INT_ArgReg[Argument::n_register_parameters] = { ++ A0, A1, A2, A3, A4, A5 ++ }; ++ static const FloatRegister FP_ArgReg[Argument::n_float_register_parameters] = { ++ F16, F17, F18, F19, F20, F21 ++ }; ++ uint args = 0; ++ uint stk_args = 0; // inc by 2 each time ++ ++// Example: ++// n java.lang.UNIXProcess::forkAndExec ++// private native int forkAndExec(byte[] prog, ++// byte[] argBlock, int argc, ++// byte[] envBlock, int envc, ++// byte[] dir, ++// boolean redirectErrorStream, ++// FileDescriptor stdin_fd, ++// FileDescriptor stdout_fd, ++// FileDescriptor stderr_fd) ++// JNIEXPORT jint JNICALL ++// Java_java_lang_UNIXProcess_forkAndExec(JNIEnv *env, ++// jobject process, ++// jbyteArray prog, ++// jbyteArray argBlock, jint argc, ++// jbyteArray envBlock, jint envc, ++// jbyteArray dir, ++// jboolean redirectErrorStream, ++// jobject stdin_fd, ++// jobject stdout_fd, ++// jobject stderr_fd) ++// ++// ::c_calling_convention ++// 0: // env <-- a0 ++// 1: L // klass/obj <-- t0 => a1 ++// 2: [ // prog[] <-- a0 => a2 ++// 3: [ // argBlock[] <-- a1 => a3 ++// 4: I // argc ++// 5: [ // envBlock[] <-- a3 => a5 ++// 6: I // envc ++// 7: [ // dir[] <-- a5 => a7 ++// 8: Z // redirectErrorStream a6 => sp[0] ++// 9: L // stdin a7 => sp[8] ++// 10: L // stdout fp[16] => sp[16] ++// 11: L // stderr fp[24] => sp[24] ++// ++ for (int i = 0; i < total_args_passed; i++) { ++ switch (sig_bt[i]) { ++ case T_VOID: // Halves of longs and doubles ++ assert(i != 0 && (sig_bt[i - 1] == T_LONG || sig_bt[i - 1] == T_DOUBLE), "expecting half"); ++ regs[i].set_bad(); ++ break; ++ case T_BOOLEAN: ++ case T_CHAR: ++ case T_BYTE: ++ case T_SHORT: ++ case T_INT: ++ if (args < Argument::n_register_parameters) { ++ regs[i].set1(INT_ArgReg[args++]->as_VMReg()); ++ } else { ++ regs[i].set1(VMRegImpl::stack2reg(stk_args)); ++ stk_args += 2; ++ } ++ break; ++ case T_LONG: ++ assert(sig_bt[i + 1] == T_VOID, "expecting half"); ++ // fall through ++ case T_OBJECT: ++ case T_ARRAY: ++ case T_ADDRESS: ++ case T_METADATA: ++ if (args < Argument::n_register_parameters) { ++ regs[i].set2(INT_ArgReg[args++]->as_VMReg()); ++ } else { ++ regs[i].set2(VMRegImpl::stack2reg(stk_args)); ++ stk_args += 2; ++ } ++ break; ++ case T_FLOAT: ++ if (args < Argument::n_float_register_parameters) { ++ regs[i].set1(FP_ArgReg[args++]->as_VMReg()); ++ } else { ++ regs[i].set1(VMRegImpl::stack2reg(stk_args)); ++ stk_args += 2; ++ } ++ break; ++ case T_DOUBLE: ++ assert(sig_bt[i + 1] == T_VOID, "expecting half"); ++ if (args < Argument::n_float_register_parameters) { ++ regs[i].set2(FP_ArgReg[args++]->as_VMReg()); ++ } else { ++ regs[i].set2(VMRegImpl::stack2reg(stk_args)); ++ stk_args += 2; ++ } ++ break; ++ default: ++ ShouldNotReachHere(); ++ break; ++ } ++ } ++ ++ return round_to(stk_args, 2); ++} ++ ++// --------------------------------------------------------------------------- ++void SharedRuntime::save_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) { ++ // We always ignore the frame_slots arg and just use the space just below frame pointer ++ // which by this time is free to use ++ switch (ret_type) { ++ case T_FLOAT: ++ __ fsts(FSF, FP, -wordSize); ++ break; ++ case T_DOUBLE: ++ __ fstd(FSF, FP, -wordSize ); ++ break; ++ case T_VOID: break; ++ case T_LONG: ++ __ stl(V0, FP, -wordSize); ++ break; ++ case T_OBJECT: ++ case T_ARRAY: ++ __ stl(V0, FP, -wordSize); ++ break; ++ default: { ++ __ stw(V0, FP, -wordSize); ++ } ++ } ++} ++ ++void SharedRuntime::restore_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) { ++ // We always ignore the frame_slots arg and just use the space just below frame pointer ++ // which by this time is free to use ++ switch (ret_type) { ++ case T_FLOAT: ++ __ flds(FSF, FP, -wordSize); ++ break; ++ case T_DOUBLE: ++ __ fldd(FSF, FP, -wordSize ); ++ break; ++ case T_LONG: ++ __ ldl(V0, FP, -wordSize); ++ break; ++ case T_VOID: break; ++ case T_OBJECT: ++ case T_ARRAY: ++ __ ldl(V0, FP, -wordSize); ++ break; ++ default: { ++ __ ldw(V0, FP, -wordSize); ++ } ++ } ++} ++ ++static void save_args(MacroAssembler *masm, int arg_count, int first_arg, VMRegPair *args) { ++ for ( int i = first_arg ; i < arg_count ; i++ ) { ++ if (args[i].first()->is_Register()) { ++ __ push(args[i].first()->as_Register()); ++ } else if (args[i].first()->is_FloatRegister()) { ++ __ push(args[i].first()->as_FloatRegister()); ++ } ++ } ++} ++ ++static void restore_args(MacroAssembler *masm, int arg_count, int first_arg, VMRegPair *args) { ++ for ( int i = arg_count - 1 ; i >= first_arg ; i-- ) { ++ if (args[i].first()->is_Register()) { ++ __ pop(args[i].first()->as_Register()); ++ } else if (args[i].first()->is_FloatRegister()) { ++ __ pop(args[i].first()->as_FloatRegister()); ++ } ++ } ++} ++ ++// A simple move of integer like type ++static void simple_move32(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { ++ if (src.first()->is_stack()) { ++ if (dst.first()->is_stack()) { ++ // stack to stack ++ __ ldw(AT, FP, reg2offset_in(src.first())); ++ __ stl(AT,SP, reg2offset_out(dst.first())); ++ } else { ++ // stack to reg ++ __ ldw(dst.first()->as_Register(), FP, reg2offset_in(src.first())); ++ } ++ } else if (dst.first()->is_stack()) { ++ // reg to stack ++ __ stl(src.first()->as_Register(), SP, reg2offset_out(dst.first())); ++ } else { ++ if (dst.first() != src.first()){ ++ __ move(dst.first()->as_Register(), src.first()->as_Register()); ++ } ++ } ++} ++ ++// An oop arg. Must pass a handle not the oop itself ++static void object_move(MacroAssembler* masm, ++ OopMap* map, ++ int oop_handle_offset, ++ int framesize_in_slots, ++ VMRegPair src, ++ VMRegPair dst, ++ bool is_receiver, ++ int* receiver_offset) { ++ ++ // must pass a handle. First figure out the location we use as a handle ++ ++ if (src.first()->is_stack()) { ++ // Oop is already on the stack as an argument ++ Register rHandle = V0; ++ Label nil; ++ __ xor_ins(rHandle, rHandle, rHandle); ++ __ ldl(AT, FP, reg2offset_in(src.first())); ++ __ beq(AT, nil); ++ __ lea(rHandle, Address(FP, reg2offset_in(src.first()))); ++ __ BIND(nil); ++ if(dst.first()->is_stack())__ stl( rHandle, SP, reg2offset_out(dst.first())); ++ else __ move( (dst.first())->as_Register(),rHandle); ++ //if dst is register ++ int offset_in_older_frame = src.first()->reg2stack() ++ + SharedRuntime::out_preserve_stack_slots(); ++ map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots)); ++ if (is_receiver) { ++ *receiver_offset = (offset_in_older_frame ++ + framesize_in_slots) * VMRegImpl::stack_slot_size; ++ } ++ } else { ++ // Oop is in an a register we must store it to the space we reserve ++ // on the stack for oop_handles ++ const Register rOop = src.first()->as_Register(); ++ assert( (rOop->encoding() >= A0->encoding()) && (rOop->encoding() <= A5->encoding()),"wrong register"); ++ const Register rHandle = V0; ++ //Important: refer to java_calling_convertion ++ int oop_slot = (rOop->encoding() - A0->encoding()) * VMRegImpl::slots_per_word + oop_handle_offset; ++ int offset = oop_slot*VMRegImpl::stack_slot_size; ++ Label skip; ++ __ stl( rOop , SP, offset ); ++ map->set_oop(VMRegImpl::stack2reg(oop_slot)); ++ __ xor_ins( rHandle, rHandle, rHandle); ++ __ beq(rOop, skip); ++ __ lea(rHandle, Address(SP, offset)); ++ __ BIND(skip); ++ // Store the handle parameter ++ if(dst.first()->is_stack())__ stl( rHandle, SP, reg2offset_out(dst.first())); ++ else __ move((dst.first())->as_Register(), rHandle); ++ //if dst is register ++ ++ if (is_receiver) { ++ *receiver_offset = offset; ++ } ++ } ++} ++ ++// A float arg may have to do float reg int reg conversion ++static void float_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { ++ assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move"); ++ ++ if (src.first()->is_stack()) { ++ if(dst.first()->is_stack()) { ++ __ flds(F16 , FP, reg2offset_in(src.first())); ++ __ fsts(F16 ,SP, reg2offset_out(dst.first())); ++ } ++ else ++ __ flds( dst.first()->as_FloatRegister(), FP, reg2offset_in(src.first())); ++ } else { ++ // reg to stack ++ if(dst.first()->is_stack()) ++ __ fsts( src.first()->as_FloatRegister(),SP, reg2offset_out(dst.first())); ++ else ++ __ fmovs( dst.first()->as_FloatRegister(), src.first()->as_FloatRegister()); ++ } ++} ++ ++// A long move ++static void long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { ++ ++ // The only legal possibility for a long_move VMRegPair is: ++ // 1: two stack slots (possibly unaligned) ++ // as neither the java or C calling convention will use registers ++ // for longs. ++ ++ if (src.first()->is_stack()) { ++ assert(src.second()->is_stack() && dst.second()->is_stack(), "must be all stack"); ++ if( dst.first()->is_stack()){ ++ __ ldl(AT, FP, reg2offset_in(src.first())); ++ __ stl(AT, SP, reg2offset_out(dst.first())); ++ } else { ++ __ ldl( (dst.first())->as_Register() , FP, reg2offset_in(src.first())); ++ } ++ } else { ++ if( dst.first()->is_stack()){ ++ __ stl( (src.first())->as_Register(), SP, reg2offset_out(dst.first())); ++ } else{ ++ __ move( (dst.first())->as_Register() , (src.first())->as_Register()); ++ } ++ } ++} ++ ++// A double move ++static void double_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { ++ ++ // The only legal possibilities for a double_move VMRegPair are: ++ // The painful thing here is that like long_move a VMRegPair might be ++ ++ // Because of the calling convention we know that src is either ++ // 1: a single physical register (xmm registers only) ++ // 2: two stack slots (possibly unaligned) ++ // dst can only be a pair of stack slots. ++ ++ ++ if (src.first()->is_stack()) { ++ // source is all stack ++ if( dst.first()->is_stack()){ ++ __ fldd(F16, FP, reg2offset_in(src.first())); ++ __ fstd(F16, SP, reg2offset_out(dst.first())); ++ } else{ ++ __ fldd( (dst.first())->as_FloatRegister(), FP, reg2offset_in(src.first())); ++ } ++ ++ } else { ++ // reg to stack ++ // No worries about stack alignment ++ if( dst.first()->is_stack()){ ++ __ fstd( src.first()->as_FloatRegister(),SP, reg2offset_out(dst.first())); ++ } ++ else ++ __ fmovd( dst.first()->as_FloatRegister(), src.first()->as_FloatRegister()); ++ ++ } ++} ++ ++static void verify_oop_args(MacroAssembler* masm, ++ methodHandle method, ++ const BasicType* sig_bt, ++ const VMRegPair* regs) { ++ Register temp_reg = T12; // not part of any compiled calling seq ++ if (VerifyOops) { ++ for (int i = 0; i < method->size_of_parameters(); i++) { ++ if (sig_bt[i] == T_OBJECT || ++ sig_bt[i] == T_ARRAY) { ++ VMReg r = regs[i].first(); ++ assert(r->is_valid(), "bad oop arg"); ++ if (r->is_stack()) { ++ __ ldl(temp_reg, Address(SP, r->reg2stack() * VMRegImpl::stack_slot_size + wordSize)); ++ __ verify_oop(temp_reg); ++ } else { ++ __ verify_oop(r->as_Register()); ++ } ++ } ++ } ++ } ++} ++ ++static void gen_special_dispatch(MacroAssembler* masm, ++ methodHandle method, ++ const BasicType* sig_bt, ++ const VMRegPair* regs) { ++ verify_oop_args(masm, method, sig_bt, regs); ++ vmIntrinsics::ID iid = method->intrinsic_id(); ++ ++ // Now write the args into the outgoing interpreter space ++ bool has_receiver = false; ++ Register receiver_reg = noreg; ++ int member_arg_pos = -1; ++ Register member_reg = noreg; ++ int ref_kind = MethodHandles::signature_polymorphic_intrinsic_ref_kind(iid); ++ if (ref_kind != 0) { ++ member_arg_pos = method->size_of_parameters() - 1; // trailing MemberName argument ++ member_reg = S3; // known to be free at this point ++ has_receiver = MethodHandles::ref_kind_has_receiver(ref_kind); ++ } else if (iid == vmIntrinsics::_invokeBasic) { ++ has_receiver = true; ++ } else { ++ fatal(err_msg_res("unexpected intrinsic id %d", iid)); ++ } ++ ++ if (member_reg != noreg) { ++ // Load the member_arg into register, if necessary. ++ SharedRuntime::check_member_name_argument_is_last_argument(method, sig_bt, regs); ++ VMReg r = regs[member_arg_pos].first(); ++ if (r->is_stack()) { ++ __ ldl(member_reg, Address(SP, r->reg2stack() * VMRegImpl::stack_slot_size)); ++ } else { ++ // no data motion is needed ++ member_reg = r->as_Register(); ++ } ++ } ++ ++ if (has_receiver) { ++ // Make sure the receiver is loaded into a register. ++ assert(method->size_of_parameters() > 0, "oob"); ++ assert(sig_bt[0] == T_OBJECT, "receiver argument must be an object"); ++ VMReg r = regs[0].first(); ++ assert(r->is_valid(), "bad receiver arg"); ++ if (r->is_stack()) { ++ // Porting note: This assumes that compiled calling conventions always ++ // pass the receiver oop in a register. If this is not true on some ++ // platform, pick a temp and load the receiver from stack. ++ fatal("receiver always in a register"); ++ receiver_reg = SSR; // known to be free at this point ++ __ ldl(receiver_reg, Address(SP, r->reg2stack() * VMRegImpl::stack_slot_size)); ++ } else { ++ // no data motion is needed ++ receiver_reg = r->as_Register(); ++ } ++ } ++ ++ // Figure out which address we are really jumping to: ++ MethodHandles::generate_method_handle_dispatch(masm, iid, ++ receiver_reg, member_reg, /*for_compiler_entry:*/ true); ++} ++ ++// --------------------------------------------------------------------------- ++// Generate a native wrapper for a given method. The method takes arguments ++// in the Java compiled code convention, marshals them to the native ++// convention (handlizes oops, etc), transitions to native, makes the call, ++// returns to java state (possibly blocking), unhandlizes any result and ++// returns. ++nmethod *SharedRuntime::generate_native_wrapper(MacroAssembler* masm, ++ methodHandle method, ++ int compile_id, ++ BasicType* in_sig_bt, ++ VMRegPair* in_regs, ++ BasicType ret_type) { ++ if (method->is_method_handle_intrinsic()) { ++ vmIntrinsics::ID iid = method->intrinsic_id(); ++ intptr_t start = (intptr_t)__ pc(); ++ int vep_offset = ((intptr_t)__ pc()) - start; ++ gen_special_dispatch(masm, ++ method, ++ in_sig_bt, ++ in_regs); ++ int frame_complete = ((intptr_t)__ pc()) - start; // not complete, period ++ __ flush(); ++ int stack_slots = SharedRuntime::out_preserve_stack_slots(); // no out slots at all, actually ++ return nmethod::new_native_nmethod(method, ++ compile_id, ++ masm->code(), ++ vep_offset, ++ frame_complete, ++ stack_slots / VMRegImpl::slots_per_word, ++ in_ByteSize(-1), ++ in_ByteSize(-1), ++ (OopMapSet*)NULL); ++ } ++ bool is_critical_native = true; ++ address native_func = method->critical_native_function(); ++ if (native_func == NULL) { ++ native_func = method->native_function(); ++ is_critical_native = false; ++ } ++ assert(native_func != NULL, "must have function"); ++ ++ // Native nmethod wrappers never take possesion of the oop arguments. ++ // So the caller will gc the arguments. The only thing we need an ++ // oopMap for is if the call is static ++ // ++ // An OopMap for lock (and class if static), and one for the VM call itself ++ OopMapSet *oop_maps = new OopMapSet(); ++ ++ // We have received a description of where all the java arg are located ++ // on entry to the wrapper. We need to convert these args to where ++ // the jni function will expect them. To figure out where they go ++ // we convert the java signature to a C signature by inserting ++ // the hidden arguments as arg[0] and possibly arg[1] (static method) ++ ++ const int total_in_args = method->size_of_parameters(); ++ int total_c_args = total_in_args; ++ if (!is_critical_native) { ++ total_c_args += 1; ++ if (method->is_static()) { ++ total_c_args++; ++ } ++ } else { ++ for (int i = 0; i < total_in_args; i++) { ++ if (in_sig_bt[i] == T_ARRAY) { ++ total_c_args++; ++ } ++ } ++ } ++ ++ BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_c_args); ++ VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_c_args); ++ BasicType* in_elem_bt = NULL; ++ ++ int argc = 0; ++ if (!is_critical_native) { ++ out_sig_bt[argc++] = T_ADDRESS; ++ if (method->is_static()) { ++ out_sig_bt[argc++] = T_OBJECT; ++ } ++ ++ for (int i = 0; i < total_in_args ; i++ ) { ++ out_sig_bt[argc++] = in_sig_bt[i]; ++ } ++ } else { ++ Thread* THREAD = Thread::current(); ++ in_elem_bt = NEW_RESOURCE_ARRAY(BasicType, total_in_args); ++ SignatureStream ss(method->signature()); ++ for (int i = 0; i < total_in_args ; i++ ) { ++ if (in_sig_bt[i] == T_ARRAY) { ++ // Arrays are passed as int, elem* pair ++ out_sig_bt[argc++] = T_INT; ++ out_sig_bt[argc++] = T_ADDRESS; ++ Symbol* atype = ss.as_symbol(CHECK_NULL); ++ const char* at = atype->as_C_string(); ++ if (strlen(at) == 2) { ++ assert(at[0] == '[', "must be"); ++ switch (at[1]) { ++ case 'B': in_elem_bt[i] = T_BYTE; break; ++ case 'C': in_elem_bt[i] = T_CHAR; break; ++ case 'D': in_elem_bt[i] = T_DOUBLE; break; ++ case 'F': in_elem_bt[i] = T_FLOAT; break; ++ case 'I': in_elem_bt[i] = T_INT; break; ++ case 'J': in_elem_bt[i] = T_LONG; break; ++ case 'S': in_elem_bt[i] = T_SHORT; break; ++ case 'Z': in_elem_bt[i] = T_BOOLEAN; break; ++ default: ShouldNotReachHere(); ++ } ++ } ++ } else { ++ out_sig_bt[argc++] = in_sig_bt[i]; ++ in_elem_bt[i] = T_VOID; ++ } ++ if (in_sig_bt[i] != T_VOID) { ++ assert(in_sig_bt[i] == ss.type(), "must match"); ++ ss.next(); ++ } ++ } ++ } ++ ++ // Now figure out where the args must be stored and how much stack space ++ // they require (neglecting out_preserve_stack_slots but space for storing ++ // the 1st six register arguments). It's weird see int_stk_helper. ++ int out_arg_slots; ++ out_arg_slots = c_calling_convention(out_sig_bt, out_regs, NULL, total_c_args); ++ ++ // Compute framesize for the wrapper. We need to handlize all oops in ++ // registers. We must create space for them here that is disjoint from ++ // the windowed save area because we have no control over when we might ++ // flush the window again and overwrite values that gc has since modified. ++ // (The live window race) ++ // ++ // We always just allocate 6 word for storing down these object. This allow ++ // us to simply record the base and use the Ireg number to decide which ++ // slot to use. (Note that the reg number is the inbound number not the ++ // outbound number). ++ // We must shuffle args to match the native convention, and include var-args space. ++ ++ // Calculate the total number of stack slots we will need. ++ ++ // First count the abi requirement plus all of the outgoing args ++ int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots; ++ ++ // Now the space for the inbound oop handle area ++ int total_save_slots = 6 * VMRegImpl::slots_per_word; // 6 arguments passed in registers ++ if (is_critical_native) { ++ // Critical natives may have to call out so they need a save area ++ // for register arguments. ++ int double_slots = 0; ++ int single_slots = 0; ++ for ( int i = 0; i < total_in_args; i++) { ++ if (in_regs[i].first()->is_Register()) { ++ const Register reg = in_regs[i].first()->as_Register(); ++ switch (in_sig_bt[i]) { ++ case T_BOOLEAN: ++ case T_BYTE: ++ case T_SHORT: ++ case T_CHAR: ++ case T_INT: single_slots++; break; ++ case T_ARRAY: // specific to LP64 (7145024) ++ case T_LONG: double_slots++; break; ++ default: ShouldNotReachHere(); ++ } ++ } else if (in_regs[i].first()->is_FloatRegister()) { ++ switch (in_sig_bt[i]) { ++ case T_FLOAT: single_slots++; break; ++ case T_DOUBLE: double_slots++; break; ++ default: ShouldNotReachHere(); ++ } ++ } ++ } ++ total_save_slots = double_slots * 2 + single_slots; ++ // align the save area ++ if (double_slots != 0) { ++ stack_slots = round_to(stack_slots, 2); ++ } ++ } ++ ++ int oop_handle_offset = stack_slots; ++ stack_slots += total_save_slots; ++ ++ // Now any space we need for handlizing a klass if static method ++ ++ int klass_slot_offset = 0; ++ int klass_offset = -1; ++ int lock_slot_offset = 0; ++ bool is_static = false; ++ ++ if (method->is_static()) { ++ klass_slot_offset = stack_slots; ++ stack_slots += VMRegImpl::slots_per_word; ++ klass_offset = klass_slot_offset * VMRegImpl::stack_slot_size; ++ is_static = true; ++ } ++ ++ // Plus a lock if needed ++ ++ if (method->is_synchronized()) { ++ lock_slot_offset = stack_slots; ++ stack_slots += VMRegImpl::slots_per_word; ++ } ++ ++ // Now a place to save return value or as a temporary for any gpr -> fpr moves ++ // + 2 for return address (which we own) and saved fp ++ stack_slots += 2 + 6 * VMRegImpl::slots_per_word; // (A1, A2, A3, A4, A5, A0) ++ ++ // Ok The space we have allocated will look like: ++ // ++ // ++ // FP-> | | ++ // |---------------------| ++ // | 2 slots for moves | ++ // |---------------------| ++ // | lock box (if sync) | ++ // |---------------------| <- lock_slot_offset ++ // | klass (if static) | ++ // |---------------------| <- klass_slot_offset ++ // | oopHandle area | ++ // |---------------------| <- oop_handle_offset ++ // | outbound memory | ++ // | based arguments | ++ // | | ++ // |---------------------| ++ // | vararg area | ++ // |---------------------| ++ // | | ++ // SP-> | out_preserved_slots | ++ // ++ // ++ ++ ++ // Now compute actual number of stack words we need rounding to make ++ // stack properly aligned. ++ stack_slots = round_to(stack_slots, StackAlignmentInSlots); ++ ++ int stack_size = stack_slots * VMRegImpl::stack_slot_size; ++ ++ intptr_t start = (intptr_t)__ pc(); ++ ++ ++ ++ // First thing make an ic check to see if we should even be here ++ address ic_miss = SharedRuntime::get_ic_miss_stub(); ++ ++ // We are free to use all registers as temps without saving them and ++ // restoring them except fp. fp is the only callee save register ++ // as far as the interpreter and the compiler(s) are concerned. ++ ++ const Register ic_reg = T1; ++ const Register receiver = A1; ++ ++ Label hit; ++ Label exception_pending; ++ ++ __ verify_oop(receiver); ++ //add for compressedoops ++ __ load_klass(T12, receiver); ++ __ beq(T12, ic_reg, hit); ++ __ jmp(ic_miss, relocInfo::runtime_call_type); ++ // verified entry must be aligned for code patching. ++ // and the first 5 bytes must be in the same cache line ++ // if we align at 8 then we will be sure 5 bytes are in the same line ++ __ align(8); ++ ++ __ BIND(hit); ++ ++ ++ int vep_offset = ((intptr_t)__ pc()) - start; ++ ++ // The instruction at the verified entry point must be 5 bytes or longer ++ // because it can be patched on the fly by make_non_entrant. The stack bang ++ // instruction fits that requirement. ++ ++ // Generate stack overflow check ++ ++ if (UseStackBanging) { ++ __ bang_stack_with_offset(StackShadowPages*os::vm_page_size()); ++ } else { ++ // need a 5 byte instruction to allow MT safe patching to non-entrant ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ } ++ // Generate a new frame for the wrapper. ++ __ st_ptr(SP, S2thread, in_bytes(JavaThread::last_Java_sp_offset())); ++ __ move(AT, -(StackAlignmentInBytes)); ++ __ and_reg(SP, SP, AT); ++ ++ __ enter(); ++ // -2 because return address is already present and so is saved fp ++ __ add_simm16(SP, SP, -1 * (stack_size - 2*wordSize)); ++ ++ // Frame is now completed as far a size and linkage. ++ ++ int frame_complete = ((intptr_t)__ pc()) - start; ++ ++ // Calculate the difference between sp and fp. We need to know it ++ // after the native call because on windows Java Natives will pop ++ // the arguments and it is painful to do sp relative addressing ++ // in a platform independent way. So after the call we switch to ++ // fp relative addressing. ++ int fp_adjustment = stack_size - 2*wordSize; ++ ++#ifdef COMPILER2 ++ // C2 may leave the stack dirty if not in SSE2+ mode ++ __ empty_FPU_stack(); ++#endif ++ ++ // Compute the fp offset for any slots used after the jni call ++ ++ int lock_slot_fp_offset = (lock_slot_offset*VMRegImpl::stack_slot_size) - fp_adjustment; ++ // We use S2thread as a thread pointer because it is callee save and ++ // if we load it once it is usable thru the entire wrapper ++ const Register thread = S2thread; ++ ++ // We use S4 as the oop handle for the receiver/klass ++ // It is callee save so it survives the call to native ++ ++ const Register oop_handle_reg = S4; ++ if (is_critical_native) { ++ __ stop("generate_native_wrapper in sharedRuntime <2>"); ++ } ++ ++ // ++ // We immediately shuffle the arguments so that any vm call we have to ++ // make from here on out (sync slow path, jvmpi, etc.) we will have ++ // captured the oops from our caller and have a valid oopMap for ++ // them. ++ ++ // ----------------- ++ // The Grand Shuffle ++ // ++ // Natives require 1 or 2 extra arguments over the normal ones: the JNIEnv* ++ // and, if static, the class mirror instead of a receiver. This pretty much ++ // parms though amd does). Since the native abi doesn't use register args ++ // and the java conventions does we don't have to worry about collisions. ++ // All of our moved are reg->stack or stack->stack. ++ // We ignore the extra arguments during the shuffle and handle them at the ++ // last moment. The shuffle is described by the two calling convention ++ // vectors we have in our possession. We simply walk the java vector to ++ // get the source locations and the c vector to get the destinations. ++ ++ int c_arg = method->is_static() ? 2 : 1 ; ++ ++ // Record sp-based slot for receiver on stack for non-static methods ++ int receiver_offset = -1; ++ ++ // This is a trick. We double the stack slots so we can claim ++ // the oops in the caller's frame. Since we are sure to have ++ // more args than the caller doubling is enough to make ++ // sure we can capture all the incoming oop args from the ++ // caller. ++ // ++ OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/); ++ ++ // Mark location of fp (someday) ++ // map->set_callee_saved(VMRegImpl::stack2reg( stack_slots - 2), stack_slots * 2, 0, vmreg(fp)); ++ ++#ifdef ASSERT ++ bool reg_destroyed[RegisterImpl::number_of_registers]; ++ bool freg_destroyed[FloatRegisterImpl::number_of_registers]; ++ for ( int r = 0 ; r < RegisterImpl::number_of_registers ; r++ ) { ++ reg_destroyed[r] = false; ++ } ++ for ( int f = 0 ; f < FloatRegisterImpl::number_of_registers ; f++ ) { ++ freg_destroyed[f] = false; ++ } ++#endif /* ASSERT */ ++ ++ // This may iterate in two different directions depending on the ++ // kind of native it is. The reason is that for regular JNI natives ++ // the incoming and outgoing registers are offset upwards and for ++ // critical natives they are offset down. ++ GrowableArray arg_order(2 * total_in_args); ++ VMRegPair tmp_vmreg; ++ tmp_vmreg.set1(T11->as_VMReg()); ++ ++ if (!is_critical_native) { ++ for (int i = total_in_args - 1, c_arg = total_c_args - 1; i >= 0; i--, c_arg--) { ++ arg_order.push(i); ++ arg_order.push(c_arg); ++ } ++ } else { ++ // Compute a valid move order, using tmp_vmreg to break any cycles ++ __ stop("generate_native_wrapper in sharedRuntime <2>"); ++// ComputeMoveOrder cmo(total_in_args, in_regs, total_c_args, out_regs, in_sig_bt, arg_order, tmp_vmreg); ++ } ++ ++ int temploc = -1; ++ for (int ai = 0; ai < arg_order.length(); ai += 2) { ++ int i = arg_order.at(ai); ++ int c_arg = arg_order.at(ai + 1); ++ __ block_comment(err_msg("move %d -> %d", i, c_arg)); ++ if (c_arg == -1) { ++ assert(is_critical_native, "should only be required for critical natives"); ++ // This arg needs to be moved to a temporary ++ __ move(tmp_vmreg.first()->as_Register(), in_regs[i].first()->as_Register()); ++ in_regs[i] = tmp_vmreg; ++ temploc = i; ++ continue; ++ } else if (i == -1) { ++ assert(is_critical_native, "should only be required for critical natives"); ++ // Read from the temporary location ++ assert(temploc != -1, "must be valid"); ++ i = temploc; ++ temploc = -1; ++ } ++#ifdef ASSERT ++ if (in_regs[i].first()->is_Register()) { ++ assert(!reg_destroyed[in_regs[i].first()->as_Register()->encoding()], "destroyed reg!"); ++ } else if (in_regs[i].first()->is_FloatRegister()) { ++ assert(!freg_destroyed[in_regs[i].first()->as_FloatRegister()->encoding()], "destroyed reg!"); ++ } ++ if (out_regs[c_arg].first()->is_Register()) { ++ reg_destroyed[out_regs[c_arg].first()->as_Register()->encoding()] = true; ++ } else if (out_regs[c_arg].first()->is_FloatRegister()) { ++ freg_destroyed[out_regs[c_arg].first()->as_FloatRegister()->encoding()] = true; ++ } ++#endif /* ASSERT */ ++ switch (in_sig_bt[i]) { ++ case T_ARRAY: ++ if (is_critical_native) { ++ __ stop("generate_native_wrapper in sharedRuntime <2>"); ++ // unpack_array_argument(masm, in_regs[i], in_elem_bt[i], out_regs[c_arg + 1], out_regs[c_arg]); ++ c_arg++; ++#ifdef ASSERT ++ if (out_regs[c_arg].first()->is_Register()) { ++ reg_destroyed[out_regs[c_arg].first()->as_Register()->encoding()] = true; ++ } else if (out_regs[c_arg].first()->is_FloatRegister()) { ++ freg_destroyed[out_regs[c_arg].first()->as_FloatRegister()->encoding()] = true; ++ } ++#endif ++ break; ++ } ++ case T_OBJECT: ++ assert(!is_critical_native, "no oop arguments"); ++ object_move(masm, map, oop_handle_offset, stack_slots, in_regs[i], out_regs[c_arg], ++ ((i == 0) && (!is_static)), ++ &receiver_offset); ++ break; ++ case T_VOID: ++ break; ++ ++ case T_FLOAT: ++ float_move(masm, in_regs[i], out_regs[c_arg]); ++ break; ++ ++ case T_DOUBLE: ++ assert( i + 1 < total_in_args && ++ in_sig_bt[i + 1] == T_VOID && ++ out_sig_bt[c_arg+1] == T_VOID, "bad arg list"); ++ double_move(masm, in_regs[i], out_regs[c_arg]); ++ break; ++ ++ case T_LONG : ++ long_move(masm, in_regs[i], out_regs[c_arg]); ++ break; ++ ++ case T_ADDRESS: assert(false, "found T_ADDRESS in java args"); ++ ++ default: ++ simple_move32(masm, in_regs[i], out_regs[c_arg]); ++ } ++ } ++ ++ // point c_arg at the first arg that is already loaded in case we ++ // need to spill before we call out ++ c_arg = total_c_args - total_in_args; ++ // Pre-load a static method's oop. Used both by locking code and ++ // the normal JNI call code. ++ ++ __ move(oop_handle_reg, A1); ++ ++ if (method->is_static() && !is_critical_native) { ++ ++ // load opp into a register ++ int oop_index = __ oop_recorder()->find_index(JNIHandles::make_local( ++ (method->method_holder())->java_mirror())); ++ ++ ++ RelocationHolder rspec = oop_Relocation::spec(oop_index); ++ __ relocate(rspec); ++ __ patchable_set48(oop_handle_reg, (long)JNIHandles::make_local((method->method_holder())->java_mirror())); ++ // Now handlize the static class mirror it's known not-null. ++ __ stl( oop_handle_reg, SP, klass_offset); ++ map->set_oop(VMRegImpl::stack2reg(klass_slot_offset)); ++ ++ // Now get the handle ++ __ lea(oop_handle_reg, Address(SP, klass_offset)); ++ // store the klass handle as second argument ++ __ move(A1, oop_handle_reg); ++ // and protect the arg if we must spill ++ c_arg--; ++ } ++ ++ // Change state to native (we save the return address in the thread, since it might not ++ // be pushed on the stack when we do a a stack traversal). It is enough that the pc() ++ // points into the right code segment. It does not have to be the correct return pc. ++ // We use the same pc/oopMap repeatedly when we call out ++ ++ intptr_t the_pc = (intptr_t) __ pc(); ++ oop_maps->add_gc_map(the_pc - start, map); ++ ++#ifdef ZHJ20180909 ++ __ set_last_Java_frame(SP, noreg, NULL); ++ ++ __ relocate(relocInfo::internal_pc_type); ++ { ++ intptr_t save_pc = (intptr_t)the_pc ; ++ __ patchable_set48(AT, save_pc); ++ } ++ __ sd(AT, thread, in_bytes(JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset())); ++#else ++ if(UseAddpi) ++ __ addpi(-1, AT); ++ else { ++ __ br(AT, 0); ++ __ subl(AT, AT, 4); // the_pc = last_Java_pc = $(AT) - br (1) ++ } ++ __ stl(AT, thread, in_bytes(JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset())); ++ ++ // move from upside, want to avoid patching ++ __ set_last_Java_frame(SP, noreg, NULL); ++#endif ++ ++ // We have all of the arguments setup at this point. We must not touch any register ++ // argument registers at this point (what if we save/restore them there are no oop? ++ { ++ SkipIfEqual skip_if(masm, &DTraceMethodProbes, 0); ++ int metadata_index = __ oop_recorder()->find_index(method()); ++ RelocationHolder rspec = metadata_Relocation::spec(metadata_index); ++ __ relocate(rspec); ++ __ patchable_set48(AT, (long)(method())); ++ ++ __ call_VM_leaf( ++ CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_entry), ++ thread, AT); ++ ++ } ++ ++ // These are register definitions we need for locking/unlocking ++ const Register swap_reg = T11; // Must use T11 for cmpxchg instruction ++ const Register obj_reg = T12; // Will contain the oop ++ //const Register lock_reg = T6; // Address of compiler lock object (BasicLock) ++ const Register lock_reg = c_rarg0; // Address of compiler lock object (BasicLock) ++ ++ ++ ++ Label slow_path_lock; ++ Label lock_done; ++ ++ // Lock a synchronized method ++ if (method->is_synchronized()) { ++ assert(!is_critical_native, "unhandled"); ++ ++ const int mark_word_offset = BasicLock::displaced_header_offset_in_bytes(); ++ ++ // Get the handle (the 2nd argument) ++ __ move(oop_handle_reg, A1); ++ ++ // Get address of the box ++ __ lea(lock_reg, Address(FP, lock_slot_fp_offset)); ++ ++ // Load the oop from the handle ++ __ ldl(obj_reg, oop_handle_reg, 0); ++ ++ if (UseBiasedLocking) { ++ // Note that oop_handle_reg is trashed during this call ++ __ biased_locking_enter(lock_reg, obj_reg, swap_reg, A1, false, lock_done, &slow_path_lock); ++ } ++ ++ // Load immediate 1 into swap_reg %T11 ++ __ move(swap_reg, 1); ++ ++ __ ldl(AT, obj_reg, 0); ++ __ or_ins(swap_reg, swap_reg, AT); ++ ++ __ stl(swap_reg, lock_reg, mark_word_offset); ++ __ cmpxchg(lock_reg, Address(obj_reg, 0), swap_reg); ++ __ bne(AT, lock_done); ++ ++ // Test if the oopMark is an obvious stack pointer, i.e., ++ // 1) (mark & 3) == 0, and ++ // 2) sp <= mark < mark + os::pagesize() ++ // These 3 tests can be done by evaluating the following ++ // expression: ((mark - sp) & (3 - os::vm_page_size())), ++ // assuming both stack pointer and pagesize have their ++ // least significant 2 bits clear. ++ // NOTE: the oopMark is in swap_reg %T11 as the result of cmpxchg ++ ++ __ subl(swap_reg, swap_reg, SP); ++ __ move(AT, 3 - os::vm_page_size()); ++ __ and_reg(swap_reg , swap_reg, AT); ++ // Save the test result, for recursive case, the result is zero ++ __ stl(swap_reg, lock_reg, mark_word_offset); ++ __ bne(swap_reg, slow_path_lock); ++ // Slow path will re-enter here ++ __ BIND(lock_done); ++ ++ if (UseBiasedLocking) { ++ // Re-fetch oop_handle_reg as we trashed it above ++ __ move(A1, oop_handle_reg); ++ } ++ } ++ ++ ++ // Finally just about ready to make the JNI call ++ ++ ++ // get JNIEnv* which is first argument to native ++ if (!is_critical_native) { ++ __ add_simm16(A0, thread, in_bytes(JavaThread::jni_environment_offset())); ++ } ++ ++ // Example: Java_java_lang_ref_Finalizer_invokeFinalizeMethod(JNIEnv *env, jclass clazz, jobject ob) ++ // Load the second arguments into A1 ++ //__ ldl(A1, SP , wordSize ); // klass ++ ++ // Now set thread in native ++ __ add_simm16(AT, R0, _thread_in_native); ++ __ stw(AT, thread, in_bytes(JavaThread::thread_state_offset())); ++ // do the call ++ __ call(method->native_function(), relocInfo::runtime_call_type); ++ // WARNING - on Windows Java Natives use pascal calling convention and pop the ++ // arguments off of the stack. We could just re-adjust the stack pointer here ++ // and continue to do SP relative addressing but we instead switch to FP ++ // relative addressing. ++ ++ // Unpack native results. ++ switch (ret_type) { ++ case T_BOOLEAN: __ c2bool(V0); break; ++ case T_CHAR : __ zapnot(V0, V0, 0x3); break; ++ case T_BYTE : __ sign_extend_byte (V0); break; ++ case T_SHORT : __ sign_extend_short(V0); break; ++ case T_INT : // nothing to do break; ++ case T_DOUBLE : ++ case T_FLOAT : ++ // Result is in st0 we'll save as needed ++ break; ++ case T_ARRAY: // Really a handle ++ case T_OBJECT: // Really a handle ++ break; // can't de-handlize until after safepoint check ++ case T_VOID: break; ++ case T_LONG: break; ++ default : ShouldNotReachHere(); ++ } ++ ++ // Switch thread to "native transition" state before reading the synchronization state. ++ // This additional state is necessary because reading and testing the synchronization ++ // state is not atomic w.r.t. GC, as this scenario demonstrates: ++ // Java thread A, in _thread_in_native state, loads _not_synchronized and is preempted. ++ // VM thread changes sync state to synchronizing and suspends threads for GC. ++ // Thread A is resumed to finish this native method, but doesn't block here since it ++ // didn't see any synchronization is progress, and escapes. ++ __ add_simm16(AT, R0, _thread_in_native_trans); ++ __ stw(AT, thread, in_bytes(JavaThread::thread_state_offset())); ++ ++ Label after_transition; ++ ++ // check for safepoint operation in progress and/or pending suspend requests ++ { ++ Label Continue; ++ __ li(AT, SafepointSynchronize::address_of_state()); ++ __ ldw(A0, AT, 0); ++ __ add_simm16(AT, A0, -SafepointSynchronize::_not_synchronized); ++ Label L; ++ __ bne(AT, L); ++ __ ldw(AT, thread, in_bytes(JavaThread::suspend_flags_offset())); ++ __ beq(AT, Continue); ++ __ BIND(L); ++ ++ // Don't use call_VM as it will see a possible pending exception and forward it ++ // and never return here preventing us from clearing _last_native_pc down below. ++ // ++ save_native_result(masm, ret_type, stack_slots); ++ __ move(A0, thread); ++ __ add_simm16(SP, SP, -wordSize); ++ __ push(S2); ++ __ move(AT, -(StackAlignmentInBytes)); ++ __ move(S2, SP); // use S2 as a sender SP holder ++ __ and_reg(SP, SP, AT); // align stack as required by ABI ++ if (!is_critical_native) { ++ __ call(CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans), relocInfo::runtime_call_type); ++ } else { ++ __ call(CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans_and_transition), relocInfo::runtime_call_type); ++ } ++ __ move(SP, S2); // use S2 as a sender SP holder ++ __ pop(S2); ++ __ add_simm16(SP,SP, wordSize); ++ //add for compressedoops ++ __ reinit_heapbase(); ++ // Restore any method result value ++ restore_native_result(masm, ret_type, stack_slots); ++ ++ if (is_critical_native) { ++ // The call above performed the transition to thread_in_Java so ++ // skip the transition logic below. ++ __ beq(R0, after_transition); ++ } ++ ++ __ BIND(Continue); ++ } ++ ++ // change thread state ++ __ add_simm16(AT, R0, _thread_in_Java); ++ __ stw(AT, thread, in_bytes(JavaThread::thread_state_offset())); ++ __ BIND(after_transition); ++ Label reguard; ++ Label reguard_done; ++ __ ldw(AT, thread, in_bytes(JavaThread::stack_guard_state_offset())); ++ __ add_simm16(AT, AT, -JavaThread::stack_guard_yellow_disabled); ++ __ beq(AT, reguard); ++ // slow path reguard re-enters here ++ __ BIND(reguard_done); ++ ++ // Handle possible exception (will unlock if necessary) ++ ++ // native result if any is live ++ ++ // Unlock ++ Label slow_path_unlock; ++ Label unlock_done; ++ if (method->is_synchronized()) { ++ ++ Label done; ++ ++ // Get locked oop from the handle we passed to jni ++ __ ldl( obj_reg, oop_handle_reg, 0); ++ if (UseBiasedLocking) { ++ __ biased_locking_exit(obj_reg, T11, done); ++ } ++ ++ // Simple recursive lock? ++ ++ __ ldl(AT, FP, lock_slot_fp_offset); ++ __ beq(AT, done); ++ // Must save FSF if if it is live now because cmpxchg must use it ++ if (ret_type != T_FLOAT && ret_type != T_DOUBLE && ret_type != T_VOID) { ++ save_native_result(masm, ret_type, stack_slots); ++ } ++ ++ // get old displaced header ++ __ ldl (T11, FP, lock_slot_fp_offset); ++ // get address of the stack lock ++ __ add_simm16 (c_rarg0, FP, lock_slot_fp_offset); ++ // Atomic swap old header if oop still contains the stack lock ++ __ cmpxchg(T11, Address(obj_reg, 0), c_rarg0); ++ ++ __ beq(AT, slow_path_unlock); ++ // slow path re-enters here ++ __ BIND(unlock_done); ++ if (ret_type != T_FLOAT && ret_type != T_DOUBLE && ret_type != T_VOID) { ++ restore_native_result(masm, ret_type, stack_slots); ++ } ++ ++ __ BIND(done); ++ ++ } ++ { ++ SkipIfEqual skip_if(masm, &DTraceMethodProbes, 0); ++ // Tell dtrace about this method exit ++ save_native_result(masm, ret_type, stack_slots); ++ int metadata_index = __ oop_recorder()->find_index( (method())); ++ RelocationHolder rspec = metadata_Relocation::spec(metadata_index); ++ __ relocate(rspec); ++ __ patchable_set48(AT, (long)(method())); ++ ++ __ call_VM_leaf( ++ CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), ++ thread, AT); ++ restore_native_result(masm, ret_type, stack_slots); ++ } ++ ++ // We can finally stop using that last_Java_frame we setup ages ago ++ ++ __ reset_last_Java_frame(false); ++ ++ // Unbox oop result, e.g. JNIHandles::resolve value. ++ if (ret_type == T_OBJECT || ret_type == T_ARRAY) { ++ __ resolve_jobject(V0 /* value */, ++ thread /* thread */, ++ AT/* tmp */); ++ } ++ ++ if (!is_critical_native) { ++ // reset handle block ++ __ ldl(AT, thread, in_bytes(JavaThread::active_handles_offset())); ++ __ stw(R0, AT, JNIHandleBlock::top_offset_in_bytes()); ++ } ++ ++ if (!is_critical_native) { ++ // Any exception pending? ++ __ ldl(AT, thread, in_bytes(Thread::pending_exception_offset())); ++ __ bne(AT, exception_pending); ++ } ++ // no exception, we're almost done ++ ++ // check that only result value is on FPU stack ++ __ verify_FPU(ret_type == T_FLOAT || ret_type == T_DOUBLE ? 1 : 0, "native_wrapper normal exit"); ++ ++ // Return ++ //__ ld_ptr(SP, S2thread, in_bytes(JavaThread::last_Java_sp_offset())); ++ __ leave(); ++ ++ __ ret(); ++ ++ // Unexpected paths are out of line and go here ++ // Slow path locking & unlocking ++ if (method->is_synchronized()) { ++ ++ // BEGIN Slow path lock ++ ++ __ BIND(slow_path_lock); ++ ++ // protect the args we've loaded ++ save_args(masm, total_c_args, c_arg, out_regs); ++ ++ // has last_Java_frame setup. No exceptions so do vanilla call not call_VM ++ // args are (oop obj, BasicLock* lock, JavaThread* thread) ++ ++ __ move(A0, obj_reg); ++ __ move(A1, lock_reg); ++ __ move(A2, thread); ++ __ add_simm16(SP, SP, - 3*wordSize); ++ __ push(S2); ++ __ move(AT, -(StackAlignmentInBytes)); ++ __ move(S2, SP); // use S2 as a sender SP holder ++ __ and_reg(SP, SP, AT); // align stack as required by ABI ++ ++ __ call(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_locking_C), relocInfo::runtime_call_type); ++ __ move(SP, S2); ++ __ pop(S2); ++ __ add_simm16(SP, SP, 3*wordSize); ++ ++ restore_args(masm, total_c_args, c_arg, out_regs); ++ ++#ifdef ASSERT ++ { Label L; ++ __ ldl(AT, thread, in_bytes(Thread::pending_exception_offset())); ++ __ beq(AT, L); ++ __ stop("no pending exception allowed on exit from monitorenter"); ++ __ BIND(L); ++ } ++#endif ++ __ beq(R0, lock_done); ++ // END Slow path lock ++ ++ // BEGIN Slow path unlock ++ __ BIND(slow_path_unlock); ++ ++ // Slow path unlock ++ ++ if (ret_type == T_FLOAT || ret_type == T_DOUBLE ) { ++ save_native_result(masm, ret_type, stack_slots); ++ } ++ // Save pending exception around call to VM (which contains an EXCEPTION_MARK) ++ ++ __ ldl(AT, thread, in_bytes(Thread::pending_exception_offset())); ++ __ push(AT); ++ __ stl(R0, thread, in_bytes(Thread::pending_exception_offset())); ++ ++ __ push(S2); ++ __ move(AT, -(StackAlignmentInBytes)); ++ __ move(S2, SP); // use S2 as a sender SP holder ++ __ and_reg(SP, SP, AT); // align stack as required by ABI ++ ++ // should be a peal ++ // +wordSize because of the push above ++ __ add_simm16(A1, FP, lock_slot_fp_offset); ++ ++ __ move(A0, obj_reg); ++ __ add_simm16(SP,SP, -2*wordSize); ++ __ call(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_unlocking_C), ++ relocInfo::runtime_call_type); ++ __ add_simm16(SP,SP, 2*wordSize); ++ __ move(SP, S2); ++ __ pop(S2); ++ ++ //add for compressedoops ++ __ reinit_heapbase(); ++#ifdef ASSERT ++ { ++ Label L; ++ __ ldw( AT, thread, in_bytes(Thread::pending_exception_offset())); ++ __ beq(AT, L); ++ __ stop("no pending exception allowed on exit complete_monitor_unlocking_C"); ++ __ BIND(L); ++ } ++#endif /* ASSERT */ ++ ++ __ pop(AT); ++ __ stl(AT, thread, in_bytes(Thread::pending_exception_offset())); ++ if (ret_type == T_FLOAT || ret_type == T_DOUBLE ) { ++ restore_native_result(masm, ret_type, stack_slots); ++ } ++ __ beq(R0, unlock_done); ++ // END Slow path unlock ++ ++ } ++ ++ // SLOW PATH Reguard the stack if needed ++ ++ __ BIND(reguard); ++ save_native_result(masm, ret_type, stack_slots); ++ __ call(CAST_FROM_FN_PTR(address, SharedRuntime::reguard_yellow_pages), ++ relocInfo::runtime_call_type); ++ //add for compressedoops ++ __ reinit_heapbase(); ++ restore_native_result(masm, ret_type, stack_slots); ++ __ beq(R0, reguard_done); ++ ++ // BEGIN EXCEPTION PROCESSING ++ if (!is_critical_native) { ++ // Forward the exception ++ __ BIND(exception_pending); ++ ++ // remove possible return value from FPU register stack ++ __ empty_FPU_stack(); ++ ++ // pop our frame ++ // forward_exception_entry need return address on stack ++ __ add_simm16(SP, FP, wordSize); ++ __ ldl(FP, SP, (-1) * wordSize); ++ ++ // and forward the exception ++ __ jmp(StubRoutines::forward_exception_entry(), relocInfo::runtime_call_type); ++ } ++ __ flush(); ++ ++ nmethod *nm = nmethod::new_native_nmethod(method, ++ compile_id, ++ masm->code(), ++ vep_offset, ++ frame_complete, ++ stack_slots / VMRegImpl::slots_per_word, ++ (is_static ? in_ByteSize(klass_offset) : in_ByteSize(receiver_offset)), ++ in_ByteSize(lock_slot_offset*VMRegImpl::stack_slot_size), ++ oop_maps); ++ ++ if (is_critical_native) { ++ nm->set_lazy_critical_native(true); ++ } ++ ++ return nm; ++ ++} ++ ++// this function returns the adjust size (in number of words) to a c2i adapter ++// activation for use during deoptimization ++int Deoptimization::last_frame_adjust(int callee_parameters, int callee_locals) { ++ return (callee_locals - callee_parameters) * Interpreter::stackElementWords; ++} ++ ++// "Top of Stack" slots that may be unused by the calling convention but must ++// otherwise be preserved. ++// On Intel these are not necessary and the value can be zero. ++// On Sparc this describes the words reserved for storing a register window ++// when an interrupt occurs. ++uint SharedRuntime::out_preserve_stack_slots() { ++ return 0; ++} ++ ++//------------------------------generate_deopt_blob---------------------------- ++// Ought to generate an ideal graph & compile, but here's some SPARC ASM ++// instead. ++void SharedRuntime::generate_deopt_blob() { ++ // allocate space for the code ++ ResourceMark rm; ++ // setup code generation tools ++ //CodeBuffer buffer ("deopt_blob", 4000, 2048); ++ CodeBuffer buffer ("deopt_blob", 8000, 2048); ++ MacroAssembler* masm = new MacroAssembler( & buffer); ++ int frame_size_in_words; ++ OopMap* map = NULL; ++ // Account for the extra args we place on the stack ++ // by the time we call fetch_unroll_info ++ const int additional_words = 2; // deopt kind, thread ++ ++ OopMapSet *oop_maps = new OopMapSet(); ++ ++ address start = __ pc(); ++ Label cont; ++ // we use S3 for DeOpt reason register ++ Register reason = S3; ++ // use S2 for thread register ++ Register thread = S2thread; ++ // use S1 for fetch_unroll_info returned UnrollBlock ++ Register unroll = S1; ++ // Prolog for non exception case! ++ // Correct the return address we were given. ++ __ add_simm16(RA, RA, - (NativeCall::return_address_offset)); ++ // Save everything in sight. ++ map = RegisterSaver::save_live_registers(masm, additional_words, &frame_size_in_words); ++ // Normal deoptimization ++ __ move(reason, Deoptimization::Unpack_deopt); ++ __ beq(R0, cont); ++ ++ int reexecute_offset = __ pc() - start; ++ ++ // Reexecute case ++ // return address is the pc describes what bci to do re-execute at ++ ++ // No need to update map as each call to save_live_registers will produce identical oopmap ++ (void) RegisterSaver::save_live_registers(masm, additional_words, &frame_size_in_words); ++ __ move(reason, Deoptimization::Unpack_reexecute); ++ __ beq(R0, cont); ++ ++ int exception_offset = __ pc() - start; ++ // Prolog for exception case ++ ++ // all registers are dead at this entry point, except for V0 and ++ // T4 which contain the exception oop and exception pc ++ // respectively. Set them in TLS and fall thru to the ++ // unpack_with_exception_in_tls entry point. ++ ++ __ get_thread(thread); ++ __ st_ptr(T4, thread, in_bytes(JavaThread::exception_pc_offset())); ++ __ st_ptr(V0, thread, in_bytes(JavaThread::exception_oop_offset())); ++ int exception_in_tls_offset = __ pc() - start; ++ // new implementation because exception oop is now passed in JavaThread ++ ++ // Prolog for exception case ++ // All registers must be preserved because they might be used by LinearScan ++ // Exceptiop oop and throwing PC are passed in JavaThread ++ // tos: stack at point of call to method that threw the exception (i.e. only ++ // args are on the stack, no return address) ++ ++ // Return address will be patched later with the throwing pc. The correct value is not ++ // available now because loading it from memory would destroy registers. ++ // Save everything in sight. ++ // No need to update map as each call to save_live_registers will produce identical oopmap ++ __ add_simm16(RA, RA, - (NativeCall::return_address_offset)); ++ (void) RegisterSaver::save_live_registers(masm, additional_words, &frame_size_in_words); ++ ++ // Now it is safe to overwrite any register ++ // store the correct deoptimization type ++ __ move(reason, Deoptimization::Unpack_exception); ++ // load throwing pc from JavaThread and patch it as the return address ++ // of the current frame. Then clear the field in JavaThread ++ __ get_thread(thread); ++ __ ld_ptr(T4, thread, in_bytes(JavaThread::exception_pc_offset())); ++ __ st_ptr(T4, SP, RegisterSaver::raOffset() * wordSize); //save ra ++ __ st_ptr(R0, thread, in_bytes(JavaThread::exception_pc_offset())); ++ ++ ++#ifdef ASSERT ++ // verify that there is really an exception oop in JavaThread ++ __ ld_ptr(AT, thread, in_bytes(JavaThread::exception_oop_offset())); ++ __ verify_oop(AT); ++ // verify that there is no pending exception ++ Label no_pending_exception; ++ __ ld_ptr(AT, thread, in_bytes(Thread::pending_exception_offset())); ++ __ beq(AT, no_pending_exception); ++ __ stop("must not have pending exception here"); ++ __ BIND(no_pending_exception); ++#endif ++ __ BIND(cont); ++ // Compiled code leaves the floating point stack dirty, empty it. ++ __ empty_FPU_stack(); ++ ++ ++ // Call C code. Need thread and this frame, but NOT official VM entry ++ // crud. We cannot block on this call, no GC can happen. ++ ++ __ move(A0, thread); ++ __ add_simm16(SP, SP, -additional_words * wordSize); ++ ++ __ set_last_Java_frame(NOREG, NOREG, NULL); ++ ++ // Call fetch_unroll_info(). Need thread and this frame, but NOT official VM entry - cannot block on ++ // this call, no GC can happen. Call should capture return values. ++ ++#ifdef ZHJ20180909 ++ __ relocate(relocInfo::internal_pc_type); ++ { ++ intptr_t save_pc = (intptr_t)__ pc() + NativeMovConstReg::instruction_size + NativeCall::return_address_offset + 4; ++ __ patchable_set48(AT, save_pc); ++ } ++#else ++ { ++ if(UseAddpi){ ++ intptr_t patch_off = 1 + (NativeCall::return_address_offset)/BytesPerInstWord; ++ __ addpi(patch_off, AT); ++ }else { ++ intptr_t patch_off = 2 * BytesPerInstWord + NativeCall::return_address_offset; ++ __ br(AT, 0); ++ __ addl(AT, AT, patch_off); ++ } ++ } ++#endif ++ __ stl(AT, thread, in_bytes(JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset())); ++ ++ __ call((address)Deoptimization::fetch_unroll_info, relocInfo::runtime_call_type); ++ ++ // use jalr + setfpec1, so we should -4. ++ oop_maps->add_gc_map(__ pc() - start - 4, map); ++ ++ __ add_simm16(SP, SP, additional_words * wordSize); ++ __ get_thread(thread); ++ __ reset_last_Java_frame(false); ++ ++ // Load UnrollBlock into S1 ++ __ move(unroll, V0); ++ ++ ++ // Move the unpack kind to a safe place in the UnrollBlock because ++ // we are very short of registers ++ ++ Address unpack_kind(unroll, Deoptimization::UnrollBlock::unpack_kind_offset_in_bytes()); ++ __ stw(reason, unpack_kind); ++ // save the unpack_kind value ++ // Retrieve the possible live values (return values) ++ // All callee save registers representing jvm state ++ // are now in the vframeArray. ++ ++ Label noException; ++ __ move(AT, Deoptimization::Unpack_exception); ++ __ bne(AT, reason, noException);// Was exception pending? ++ __ ld_ptr(V0, thread, in_bytes(JavaThread::exception_oop_offset())); ++ __ ld_ptr(T4, thread, in_bytes(JavaThread::exception_pc_offset())); ++ __ st_ptr(R0, thread, in_bytes(JavaThread::exception_pc_offset())); ++ __ st_ptr(R0, thread, in_bytes(JavaThread::exception_oop_offset())); ++ ++ __ verify_oop(V0); ++ ++ // Overwrite the result registers with the exception results. ++ __ st_ptr(V0, SP, RegisterSaver::v0Offset()*wordSize); ++ ++ __ BIND(noException); ++ ++ ++ // Stack is back to only having register save data on the stack. ++ // Now restore the result registers. Everything else is either dead or captured ++ // in the vframeArray. ++ ++ RegisterSaver::restore_result_registers(masm); ++ // All of the register save area has been popped of the stack. Only the ++ // return address remains. ++ // Pop all the frames we must move/replace. ++ // Frame picture (youngest to oldest) ++ // 1: self-frame (no frame link) ++ // 2: deopting frame (no frame link) ++ // 3: caller of deopting frame (could be compiled/interpreted). ++ // ++ // Note: by leaving the return address of self-frame on the stack ++ // and using the size of frame 2 to adjust the stack ++ // when we are done the return to frame 3 will still be on the stack. ++ ++ // register for the sender's sp ++ Register sender_sp = Rsender; ++ // register for frame pcs ++ Register pcs = T0; ++ // register for frame sizes ++ Register sizes = T1; ++ // register for frame count ++ Register count = T3; ++ ++ // Pop deoptimized frame ++ __ ldw(AT, unroll, Deoptimization::UnrollBlock::size_of_deoptimized_frame_offset_in_bytes()); ++ __ addl(SP, SP, AT); ++ // sp should be pointing at the return address to the caller (3) ++ ++ // Load array of frame pcs into pcs ++ __ ld_ptr(pcs, unroll, Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes()); ++ __ add_simm16(SP, SP, wordSize); // trash the old pc ++ // Load array of frame sizes into T6 ++ __ ld_ptr(sizes, unroll, Deoptimization::UnrollBlock::frame_sizes_offset_in_bytes()); ++ ++ ++ ++ // Load count of frams into T3 ++ __ ldw(count, unroll, Deoptimization::UnrollBlock::number_of_frames_offset_in_bytes()); ++ // Pick up the initial fp we should save ++ __ ldl(FP, unroll, Deoptimization::UnrollBlock::initial_info_offset_in_bytes()); ++ // Now adjust the caller's stack to make up for the extra locals ++ // but record the original sp so that we can save it in the skeletal interpreter ++ // frame and the stack walking of interpreter_sender will get the unextended sp ++ // value and not the "real" sp value. ++ __ move(sender_sp, SP); ++ __ ldw(AT, unroll, Deoptimization::UnrollBlock::caller_adjustment_offset_in_bytes()); ++ __ subl(SP, SP, AT); ++ ++// pcs[0] = frame_pcs[0] = deopt_sender.raw_pc(); regex.split ++ Label loop; ++ __ BIND(loop); ++ __ ldl(T2, sizes, 0); // Load frame size ++ __ ld_ptr(AT, pcs, 0); // save return address ++ __ add_simm16(T2, T2, -2*wordSize); // we'll push pc and fp, by hand ++ __ push2(AT, FP); ++ __ move(FP, SP); ++ __ subl(SP, SP, T2); // Prolog! ++ // This value is corrected by layout_activation_impl ++ __ stl(R0, FP, frame::interpreter_frame_last_sp_offset * wordSize); ++ __ stl(sender_sp, FP, frame::interpreter_frame_sender_sp_offset * wordSize);// Make it walkable ++ __ move(sender_sp, SP); // pass to next frame ++ __ subl(count, count, 1); // decrement counter ++ __ add_simm16(sizes, sizes, wordSize); // Bump array pointer (sizes) ++ __ add_simm16(pcs, pcs, wordSize); ++ __ bne(count, loop); ++ __ ldl(AT, pcs, 0); // frame_pcs[number_of_frames] = Interpreter::deopt_entry(vtos, 0); ++ // Re-push self-frame ++ __ push2(AT, FP); ++ __ move(FP, SP); ++ __ stl(R0, FP, frame::interpreter_frame_last_sp_offset * wordSize); ++ __ stl(sender_sp, FP, frame::interpreter_frame_sender_sp_offset * wordSize); ++ __ add_simm16(SP, SP, -(frame_size_in_words - 2 - additional_words) * wordSize); ++ ++ // Restore frame locals after moving the frame ++ __ stl(V0, SP, RegisterSaver::v0Offset() * wordSize); ++ __ fstd(F0, SP, RegisterSaver::fpResultOffset()* wordSize);// Pop float stack and store in local ++ __ fstd(F1, SP, (RegisterSaver::fpResultOffset() + 1) * wordSize); ++ ++ ++ // Call unpack_frames(). Need thread and this frame, but NOT official VM entry - cannot block on ++ // this call, no GC can happen. ++ __ move(A1, reason); // exec_mode ++ __ get_thread(thread); ++ __ move(A0, thread); // thread ++ __ add_simm16(SP, SP, (-additional_words) *wordSize); ++ ++ // set last_Java_sp, last_Java_fp ++ __ set_last_Java_frame(NOREG, FP, NULL); ++ ++ __ move(AT, -(StackAlignmentInBytes)); ++ __ and_reg(SP, SP, AT); // Fix stack alignment as required by ABI ++ ++#ifdef ZHJ20180909 ++ __ relocate(relocInfo::internal_pc_type); ++ { ++ intptr_t save_pc = (intptr_t)__ pc() + NativeMovConstReg::instruction_size + NativeCall::return_address_offset + 4; ++ __ patchable_set48(AT, save_pc); ++ } ++#else ++ { ++ if(UseAddpi){ ++ intptr_t patch_off = 1 + (NativeCall::return_address_offset)/BytesPerInstWord; ++ __ addpi(patch_off, AT); ++ }else { ++ intptr_t patch_off = 2 * BytesPerInstWord + NativeCall::return_address_offset; ++ __ br(AT, 0); ++ __ addl(AT, AT, patch_off); ++ } ++ } ++#endif ++ __ stl(AT, thread, in_bytes(JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset())); ++ ++ __ call(CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames), relocInfo::runtime_call_type); ++ // Revert SP alignment after call since we're going to do some SP relative addressing below ++ __ ldl(SP, thread, in_bytes(JavaThread::last_Java_sp_offset())); ++ ++ // Set an oopmap for the call site ++ oop_maps->add_gc_map(__ offset() - 4, new OopMap( frame_size_in_words , 0)); ++ ++ __ push(V0); ++ ++ __ get_thread(thread); ++ __ reset_last_Java_frame(true); ++ ++ // Collect return values ++ __ ldl(V0, SP, (RegisterSaver::v0Offset() + additional_words +1) * wordSize); ++ __ fldd(F0, SP, RegisterSaver::fpResultOffset()* wordSize);// Pop float stack and store in local ++ __ fldd(F1, SP, (RegisterSaver::fpResultOffset() + 1) * wordSize); ++ // Clear floating point stack before returning to interpreter ++ __ empty_FPU_stack(); ++ // Push a float or double return value if necessary. ++ __ leave(); ++ ++ // Jump to interpreter ++ __ ret(); ++ ++ masm->flush(); ++ _deopt_blob = DeoptimizationBlob::create(&buffer, oop_maps, 0, exception_offset, reexecute_offset, frame_size_in_words); ++ _deopt_blob->set_unpack_with_exception_in_tls_offset(exception_in_tls_offset); ++} ++ ++#ifdef COMPILER2 ++ ++//------------------------------generate_uncommon_trap_blob-------------------- ++// Ought to generate an ideal graph & compile, but here's some SPARC ASM ++// instead. ++void SharedRuntime::generate_uncommon_trap_blob() { ++ // allocate space for the code ++ ResourceMark rm; ++ // setup code generation tools ++ CodeBuffer buffer ("uncommon_trap_blob", 512*80 , 512*40 ); ++ MacroAssembler* masm = new MacroAssembler(&buffer); ++ ++ enum frame_layout { ++ s0_off, s0_off2, ++ s1_off, s1_off2, ++ s2_off, s2_off2, ++ s3_off, s3_off2, ++ s4_off, s4_off2, ++ s5_off, s5_off2, ++ fp_off, fp_off2, ++ return_off, return_off2, // slot for return address sp + 9 ++ framesize ++ }; ++ assert(framesize % 4 == 0, "sp not 16-byte aligned"); ++ ++ address start = __ pc(); ++ ++ // Push self-frame. ++ __ add_simm16(SP, SP, -framesize * BytesPerInt); ++ ++ __ stl(RA, SP, return_off * BytesPerInt); ++ __ stl(FP, SP, fp_off * BytesPerInt); ++ ++ // Save callee saved registers. None for UseSSE=0, ++ // floats-only for UseSSE=1, and doubles for UseSSE=2. ++ __ stl(S0, SP, s0_off * BytesPerInt); ++ __ stl(S1, SP, s1_off * BytesPerInt); ++ __ stl(S2, SP, s2_off * BytesPerInt); ++ __ stl(S3, SP, s3_off * BytesPerInt); ++ __ stl(S4, SP, s4_off * BytesPerInt); ++ __ stl(S5, SP, s5_off * BytesPerInt); ++ ++ __ add_simm16(FP, SP, fp_off * BytesPerInt); ++ ++ // Clear the floating point exception stack ++ __ empty_FPU_stack(); ++ ++ Register thread = S2thread; ++ ++ // set last_Java_sp ++ __ set_last_Java_frame(NOREG, FP, NULL); ++#ifdef ZHJ20180909 ++ __ relocate(relocInfo::internal_pc_type); ++ if (SafePatch) { ++ assert(NativeCall::return_address_offset == 24, "in sharedRuntime return_address_offset"); ++ } else { ++ assert(NativeCall::return_address_offset == 20, "in sharedRuntime return_address_offset"); ++ } ++ { ++ long save_pc = (long)__ pc() + (6 * BytesPerInstWord) + NativeCall::return_address_offset; ++ __ patchable_set48(AT, (long)save_pc); ++ } ++#else ++ if (SafePatch) { ++ assert(NativeCall::return_address_offset == 24, "in sharedRuntime return_address_offset"); ++ } else { ++ assert(NativeCall::return_address_offset == 20, "in sharedRuntime return_address_offset"); ++ } ++ { ++ if(UseAddpi){ ++ // stl (1) + move (1) + patchable_call_setfpec1 ++ intptr_t patch_off = 2 + (NativeCall::return_address_offset)/BytesPerInstWord; ++ __ addpi(patch_off, AT); ++ }else { ++ // addl (1) + stl (1) + move (1) + patchable_call_setfpec1 ++ intptr_t patch_off = 3 * BytesPerInstWord + NativeCall::return_address_offset; ++ __ br(AT, 0); ++ __ addl(AT, AT, patch_off); ++ } ++ } ++#endif ++ __ stl(AT, thread, in_bytes(JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset())); ++ ++ // Call C code. Need thread but NOT official VM entry ++ // crud. We cannot block on this call, no GC can happen. Call should ++ // capture callee-saved registers as well as return values. ++ __ move(A0, thread); ++ // argument already in A1 ++ __ patchable_call_setfpec1((address)Deoptimization::uncommon_trap); ++ ++ // Set an oopmap for the call site ++ OopMapSet *oop_maps = new OopMapSet(); ++ OopMap* map = new OopMap( framesize, 0 ); ++ ++ map->set_callee_saved( VMRegImpl::stack2reg(s0_off ), S0->as_VMReg() ); ++ map->set_callee_saved( VMRegImpl::stack2reg(s1_off ), S1->as_VMReg() ); ++ map->set_callee_saved( VMRegImpl::stack2reg(s2_off ), S2->as_VMReg() ); ++ map->set_callee_saved( VMRegImpl::stack2reg(s3_off ), S3->as_VMReg() ); ++ map->set_callee_saved( VMRegImpl::stack2reg(s4_off ), S4->as_VMReg() ); ++ map->set_callee_saved( VMRegImpl::stack2reg(s5_off ), S5->as_VMReg() ); ++ ++ // use jalr + setfpec1, so we should -4. ++ oop_maps->add_gc_map( __ offset() - 4, map); ++ ++ __ reset_last_Java_frame(false); ++ ++ // Load UnrollBlock into S1 ++ Register unroll = S1; ++ __ move(unroll, V0); ++ ++ // Pop all the frames we must move/replace. ++ // ++ // Frame picture (youngest to oldest) ++ // 1: self-frame (no frame link) ++ // 2: deopting frame (no frame link) ++ // 3: possible-i2c-adapter-frame ++ // 4: caller of deopting frame (could be compiled/interpreted. If interpreted we will create an ++ // and c2i here) ++ ++ __ add_simm16(SP, SP, framesize * BytesPerInt); ++ ++ // Pop deoptimized frame ++ __ ldw(AT, unroll, Deoptimization::UnrollBlock::size_of_deoptimized_frame_offset_in_bytes()); ++ __ addl(SP, SP, AT); ++ ++ // register for frame pcs ++ Register pcs = T11; ++ // register for frame sizes ++ Register sizes = T12; ++ // register for frame count ++ Register count = T3; ++ // register for the sender's sp ++ Register sender_sp = T1; ++ ++ // sp should be pointing at the return address to the caller (4) ++ // Load array of frame pcs ++ __ ldl(pcs, unroll, Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes()); ++ ++ // Load array of frame sizes ++ __ ldl(sizes, unroll, Deoptimization::UnrollBlock::frame_sizes_offset_in_bytes()); ++ __ ldw_unsigned(count, unroll, Deoptimization::UnrollBlock::number_of_frames_offset_in_bytes()); ++ ++ // Pick up the initial fp we should save ++ __ ldl(FP, unroll, Deoptimization::UnrollBlock::initial_info_offset_in_bytes()); ++ // Now adjust the caller's stack to make up for the extra locals ++ // but record the original sp so that we can save it in the skeletal interpreter ++ // frame and the stack walking of interpreter_sender will get the unextended sp ++ // value and not the "real" sp value. ++ ++ __ move(sender_sp, SP); ++ __ ldw(AT, unroll, Deoptimization::UnrollBlock::caller_adjustment_offset_in_bytes()); ++ __ subl(SP, SP, AT); ++ // Push interpreter frames in a loop ++ Label loop; ++ __ BIND(loop); ++ __ ldl(T2, sizes, 0); // Load frame size ++ __ ldl(AT, pcs, 0); // save return address ++ __ add_simm16(T2, T2, -2*wordSize); // we'll push pc and fp, by hand ++ __ push2(AT, FP); ++ __ move(FP, SP); ++ __ subl(SP, SP, T2); // Prolog! ++ // This value is corrected by layout_activation_impl ++ __ stl(R0, FP, frame::interpreter_frame_last_sp_offset * wordSize); ++ __ stl(sender_sp, FP, frame::interpreter_frame_sender_sp_offset * wordSize);// Make it walkable ++ __ move(sender_sp, SP); // pass to next frame ++ __ subl(count, count, 1); // decrement counter ++ __ add_simm16(sizes, sizes, wordSize); // Bump array pointer (sizes) ++ __ add_simm16(pcs, pcs, wordSize); // Bump array pointer (pcs) ++ __ bne(count, loop); ++ ++ __ ldl(RA, pcs, 0); ++ ++ // Re-push self-frame ++ __ add_simm16(SP, SP, - 2 * wordSize); // save old & set new FP ++ __ stl(FP, SP, 0 * wordSize); // save final return address ++ __ stl(RA, SP, 1 * wordSize); ++ __ move(FP, SP); ++ __ add_simm16(SP, SP, -(framesize / 2 - 2) * wordSize); ++ ++ // set last_Java_sp, last_Java_fp ++ __ set_last_Java_frame(NOREG, FP, NULL); ++ ++ __ move(AT, -(StackAlignmentInBytes)); ++ __ and_reg(SP, SP, AT); // Fix stack alignment as required by ABI ++ ++#ifdef ZHJ20180909 ++ __ relocate(relocInfo::internal_pc_type); ++ { ++ long save_pc = (long)__ pc() + (7 * BytesPerInstWord) + NativeCall::return_address_offset; ++ __ patchable_set48(AT, (long)save_pc); ++ } ++#else ++ { ++ if(UseAddpi){ ++ intptr_t patch_off = 3 + (NativeCall::return_address_offset)/BytesPerInstWord; ++ __ addpi(patch_off, AT); ++ }else { ++ intptr_t patch_off = 4 * BytesPerInstWord + NativeCall::return_address_offset; ++ __ br(AT, 0); ++ __ addl(AT, AT, patch_off); ++ } ++ } ++#endif ++ __ stl(AT, thread, in_bytes(JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset())); ++ ++ // Call C code. Need thread but NOT official VM entry ++ // crud. We cannot block on this call, no GC can happen. Call should ++ // restore return values to their stack-slots with the new SP. ++ __ move(A0, thread); ++ __ move(A1, Deoptimization::Unpack_uncommon_trap); ++ __ patchable_call_setfpec1((address)Deoptimization::unpack_frames); ++ ++ // Set an oopmap for the call site ++ // use jalr + setfpec1, so we should -4. ++ oop_maps->add_gc_map( __ offset() - 4, new OopMap( framesize, 0 ) ); ++ ++ __ reset_last_Java_frame(true); ++ ++ // Pop self-frame. ++ __ leave(); // Epilog! ++ ++ // Jump to interpreter ++ __ ret(); ++ ++ // ------------- ++ // make sure all code is generated ++ masm->flush(); ++ ++ _uncommon_trap_blob = UncommonTrapBlob::create(&buffer, oop_maps, framesize / 2); ++} ++ ++#endif // COMPILER2 ++ ++//------------------------------generate_handler_blob------------------- ++// ++// Generate a special Compile2Runtime blob that saves all registers, and sets ++// up an OopMap and calls safepoint code to stop the compiled code for ++// a safepoint. ++// ++// This blob is jumped to (via a breakpoint and the signal handler) from a ++// safepoint in compiled code. ++ ++SafepointBlob* SharedRuntime::generate_handler_blob(address call_ptr, int pool_type) { ++ ++ // Account for thread arg in our frame ++ const int additional_words = 0; ++ int frame_size_in_words; ++ ++ assert (StubRoutines::forward_exception_entry() != NULL, "must be generated before"); ++ ++ ResourceMark rm; ++ OopMapSet *oop_maps = new OopMapSet(); ++ OopMap* map; ++ ++ // allocate space for the code ++ // setup code generation tools ++ CodeBuffer buffer ("handler_blob", 2048, 512); ++ MacroAssembler* masm = new MacroAssembler( &buffer); ++ ++ const Register thread = S2thread; ++ address start = __ pc(); ++ address call_pc = NULL; ++ bool cause_return = (pool_type == POLL_AT_RETURN); ++ bool save_vectors = (pool_type == POLL_AT_VECTOR_LOOP); ++ ++ // If cause_return is true we are at a poll_return and there is ++ // the return address in RA to the caller on the nmethod ++ // that is safepoint. We can leave this return in RA and ++ // effectively complete the return and safepoint in the caller. ++ // Otherwise we load exception pc to RA. ++ __ push(thread); ++ ++ if(!cause_return) { ++ __ ld_ptr(RA, Address(thread, JavaThread::saved_exception_pc_offset())); ++ } ++ ++ __ pop(thread); ++ map = RegisterSaver::save_live_registers(masm, additional_words, &frame_size_in_words, save_vectors); ++ ++ // The following is basically a call_VM. However, we need the precise ++ // address of the call in order to generate an oopmap. Hence, we do all the ++ // work outselvs. ++ ++ __ move(A0, thread); ++ __ set_last_Java_frame(NOREG, NOREG, NULL); ++ ++ //set last_Java_pc ++ if(UseAddpi){ ++ intptr_t patch_off = 1 + (NativeCall::return_address_offset)/BytesPerInstWord; ++ __ addpi(patch_off, AT); ++ }else { ++ intptr_t patch_off = 2 * BytesPerInstWord + NativeCall::return_address_offset; ++ __ br(AT, 0); ++ __ addl(AT, AT, patch_off); ++ } ++ __ stl(AT, thread, in_bytes(JavaThread::last_Java_pc_offset())); ++ ++ // do the call ++ __ patchable_call_setfpec1(call_ptr); ++ ++ // Set an oopmap for the call site. This oopmap will map all ++ // oop-registers and debug-info registers as callee-saved. This ++ // will allow deoptimization at this safepoint to find all possible ++ // debug-info recordings, as well as let GC find all oops. ++ // use jalr + setfpec1, so we should -4. ++ oop_maps->add_gc_map(__ offset() - 4, map); ++ ++ Label noException; ++ ++ // Clear last_Java_sp again ++ __ reset_last_Java_frame(false); ++ ++ __ ld_ptr(AT, thread, in_bytes(Thread::pending_exception_offset())); ++ __ beq(AT, noException); ++ ++ // Exception pending ++ ++ RegisterSaver::restore_live_registers(masm, save_vectors); ++ //forward_exception_entry need return address on the stack ++ __ push(RA); ++ __ patchable_jump((address)StubRoutines::forward_exception_entry()); ++ ++ // No exception case ++ __ BIND(noException); ++ // Normal exit, register restoring and exit ++ RegisterSaver::restore_live_registers(masm, save_vectors); ++ __ ret(); ++ ++ masm->flush(); ++ ++ // Fill-out other meta info ++ return SafepointBlob::create(&buffer, oop_maps, frame_size_in_words); ++} ++ ++// ++// generate_resolve_blob - call resolution (static/virtual/opt-virtual/ic-miss ++// ++// Generate a stub that calls into vm to find out the proper destination ++// of a java call. All the argument registers are live at this point ++// but since this is generic code we don't know what they are and the caller ++// must do any gc of the args. ++// ++RuntimeStub* SharedRuntime::generate_resolve_blob(address destination, const char* name) { ++ assert (StubRoutines::forward_exception_entry() != NULL, "must be generated before"); ++ ++ // allocate space for the code ++ ResourceMark rm; ++ ++ //CodeBuffer buffer(name, 1000, 512); ++ CodeBuffer buffer(name, 20000, 2048); ++ MacroAssembler* masm = new MacroAssembler(&buffer); ++ ++ int frame_size_words; ++ //we put the thread in A0 ++ ++ OopMapSet *oop_maps = new OopMapSet(); ++ OopMap* map = NULL; ++ ++ int start = __ offset(); ++ map = RegisterSaver::save_live_registers(masm, 0, &frame_size_words); ++ ++ ++ int frame_complete = __ offset(); ++ ++ const Register thread = T11; ++ __ get_thread(thread); ++ ++ __ move(A0, thread); ++ __ set_last_Java_frame(noreg, FP, NULL); ++ //align the stack before invoke native ++ __ move(AT, -(StackAlignmentInBytes)); ++ __ and_reg(SP, SP, AT); ++#ifdef ZHJ20180909 ++ __ relocate(relocInfo::internal_pc_type); ++ { ++ intptr_t save_pc = (intptr_t)__ pc() + NativeMovConstReg::instruction_size + NativeCall::return_address_offset + 1 * BytesPerInstWord; ++ __ patchable_set48(AT, save_pc); ++ } ++#else ++ { ++ if(UseAddpi){ ++ intptr_t patch_off = 1 + (NativeCall::return_address_offset)/BytesPerInstWord; ++ __ addpi(patch_off, AT); ++ }else { ++ intptr_t patch_off = 2 * BytesPerInstWord + NativeCall::return_address_offset; ++ __ br(AT, 0); ++ __ addl(AT, AT, patch_off); ++ } ++ } ++#endif ++ __ stl(AT, thread, in_bytes(JavaThread::last_Java_pc_offset())); ++ ++ __ patchable_call_setfpec1(destination); ++ ++ // Set an oopmap for the call site. ++ // We need this not only for callee-saved registers, but also for volatile ++ // registers that the compiler might be keeping live across a safepoint. ++ // use jalr + setfpec1, so we should -4. ++ oop_maps->add_gc_map( __ offset() - start - 4, map); ++ ++ // V0 contains the address we are going to jump to assuming no exception got installed ++ __ get_thread(thread); ++ __ ld_ptr(SP, thread, in_bytes(JavaThread::last_Java_sp_offset())); ++ // clear last_Java_sp ++ __ reset_last_Java_frame(true); ++ // check for pending exceptions ++ Label pending; ++ __ ld_ptr(AT, thread, in_bytes(Thread::pending_exception_offset())); ++ __ bne(AT, pending); ++ ++ // get the returned Method* ++ __ get_vm_result_2(Rmethod, thread); // Refer to OpenJDK8 ++ __ st_ptr(Rmethod, SP, RegisterSaver::methodOffset() * wordSize); ++ __ st_ptr(V0, SP, RegisterSaver::v0Offset() * wordSize); ++ RegisterSaver::restore_live_registers(masm); ++ ++ // We are back the the original state on entry and ready to go the callee method. ++ __ jmp(V0); ++ ++ // Pending exception after the safepoint ++ ++ __ BIND(pending); ++ ++ RegisterSaver::restore_live_registers(masm); ++ ++ // exception pending => remove activation and forward to exception handler ++ //forward_exception_entry need return address on the stack ++ __ push(RA); ++ __ get_thread(thread); ++ __ st_ptr(R0, thread, in_bytes(JavaThread::vm_result_offset())); ++ __ ld_ptr(V0, thread, in_bytes(Thread::pending_exception_offset())); ++ __ jmp(StubRoutines::forward_exception_entry(), relocInfo::runtime_call_type); ++ // ++ // make sure all code is generated ++ masm->flush(); ++ ++ RuntimeStub* tmp= RuntimeStub::new_runtime_stub(name, &buffer, frame_complete, frame_size_words, oop_maps, true); ++ return tmp; ++} ++ ++//ADD BY LJ ++ ++//------------------------------Montgomery multiplication------------------------ ++// ++ ++ ++#define ASM_SUBTRACT ++ ++#ifdef ASM_SUBTRACT ++typedef int __attribute__((mode(TI))) int128; ++ ++// Subtract 0:b from carry:a. Return carry. ++static unsigned long ++sub(unsigned long a[], unsigned long b[], unsigned long carry, int len) { ++ int128 tmp = 0; ++ int i; ++ for (i = 0; i < len; i++) { ++ tmp += a[i]; ++ tmp -= b[i]; ++ a[i] = tmp; ++ tmp >>= 64; ++ assert(-1 <= tmp && tmp <= 0, "invariant"); ++ } ++ return tmp + carry; ++} ++#endif // ! ASM_SUBTRACT ++ ++// Multiply (unsigned) Long A by Long B, accumulating the double- ++// length result into the accumulator formed of T0, T1, and T2. ++inline void MACC(unsigned long A, unsigned long B, unsigned long &t0, unsigned long &t1, unsigned long &t2) { ++ unsigned long hi, lo, carry = 0, t = 0; ++ __asm__ __volatile__( ++ "mull %[A], %[B] , %[lo] \n" ++ "umulh %[A], %[B] , %[hi] \n" ++ "addl %[lo], %[t0], %[t0] \n" ++ "cmpult %[t0], %[lo], %[carry] \n" ++ "addl %[t1], %[carry], %[t1] \n" ++ "cmpult %[t1], %[carry], %[t] \n" ++ "addl %[t1], %[hi], %[t1] \n" ++ "cmpult %[t1], %[hi], %[carry] \n" ++ "bis %[carry], %[t] , %[carry] \n" ++ "addl %[t2], %[carry], %[t2] \n" ++ : [hi]"=&r"(hi), [lo]"=&r"(lo), [t0]"+r"(t0), [t1]"+r"(t1), [t2]"+r"(t2), [carry]"+r"(carry), [t]"+r"(t) ++ : [A]"r"(A), [B]"r"(B) ++ : ++ ); ++} ++ ++// As above, but add twice the double-length result into the ++// accumulator. ++inline void MACC2(unsigned long A, unsigned long B, unsigned long &t0, unsigned long &t1, unsigned long &t2) { ++ unsigned long hi, lo, carry = 0, t = 0; ++ __asm__ __volatile__( ++ "mull %[A], %[B] , %[lo] \n" ++ "umulh %[A], %[B] , %[hi] \n" ++ "addl %[t0], %[lo], %[t0] \n" ++ "cmpult %[t0], %[lo], %[carry] \n" ++ "addl %[t1], %[carry], %[t1] \n" ++ "cmpult %[t1], %[carry], %[t] \n" ++ "addl %[t1], %[hi], %[t1] \n" ++ "cmpult %[t1], %[hi], %[carry] \n" ++ "bis %[carry], %[t], %[carry] \n" ++ "addl %[t2], %[carry], %[t2] \n" ++ "addl %[t0], %[lo], %[t0] \n" ++ "cmpult %[t0], %[lo], %[carry] \n" ++ "addl %[t1], %[carry], %[t1] \n" ++ "cmpult %[t1], %[carry], %[t] \n" ++ "addl %[t1], %[hi], %[t1] \n" ++ "cmpult %[t1], %[hi], %[carry] \n" ++ "bis %[carry], %[t], %[carry] \n" ++ "addl %[t2], %[carry], %[t2] \n" ++ : [hi]"=&r"(hi), [lo]"=&r"(lo), [t0]"+r"(t0), [t1]"+r"(t1), [t2]"+r"(t2), [carry]"+r"(carry), [t]"+r"(t) ++ : [A]"r"(A), [B]"r"(B) ++ : ++ ); ++} ++ ++// Fast Montgomery multiplication. The derivation of the algorithm is ++// in A Cryptographic Library for the Motorola DSP56000, ++// Dusse and Kaliski, Proc. EUROCRYPT 90, pp. 230-237. ++ ++static void __attribute__((noinline)) ++montgomery_multiply(unsigned long a[], unsigned long b[], unsigned long n[], ++ unsigned long m[], unsigned long inv, int len) { ++ unsigned long t0 = 0, t1 = 0, t2 = 0; // Triple-precision accumulator ++ int i; ++ assert(inv * n[0] == -1UL, "broken inverse in Montgomery multiply"); ++/* ++static long count=0; ++count++; ++if( (count%1000)==0 ) ++ printf("montgomery_multiply,,,\n"); ++*/ ++ for (i = 0; i < len; i++) { ++ int j; ++ for (j = 0; j < i; j++) { ++ MACC(a[j], b[i-j], t0, t1, t2); ++ MACC(m[j], n[i-j], t0, t1, t2); ++ } ++ MACC(a[i], b[0], t0, t1, t2); ++ m[i] = t0 * inv; ++ MACC(m[i], n[0], t0, t1, t2); ++ ++ assert(t0 == 0, "broken Montgomery multiply"); ++ ++ t0 = t1; t1 = t2; t2 = 0; ++ } ++ ++ for (i = len; i < 2*len; i++) { ++ int j; ++ for (j = i-len+1; j < len; j++) { ++ MACC(a[j], b[i-j], t0, t1, t2); ++ MACC(m[j], n[i-j], t0, t1, t2); ++ } ++ m[i-len] = t0; ++ t0 = t1; t1 = t2; t2 = 0; ++ } ++ ++ while (t0) ++ t0 = sub(m, n, t0, len); ++} ++ ++// Fast Montgomery squaring. This uses asymptotically 25% fewer ++// multiplies so it should be up to 25% faster than Montgomery ++// multiplication. However, its loop control is more complex and it ++// may actually run slower on some machines. ++ ++static void __attribute__((noinline)) ++montgomery_square(unsigned long a[], unsigned long n[], ++ unsigned long m[], unsigned long inv, int len) { ++ unsigned long t0 = 0, t1 = 0, t2 = 0; // Triple-precision accumulator ++ int i; ++ ++ assert(inv * n[0] == -1UL, "broken inverse in Montgomery multiply"); ++ ++ for (i = 0; i < len; i++) { ++ int j; ++ int end = (i+1)/2; ++ for (j = 0; j < end; j++) { ++ MACC2(a[j], a[i-j], t0, t1, t2); ++ MACC(m[j], n[i-j], t0, t1, t2); ++ } ++ if ((i & 1) == 0) { ++ MACC(a[j], a[j], t0, t1, t2); ++ } ++ for (; j < i; j++) { ++ MACC(m[j], n[i-j], t0, t1, t2); ++ } ++ m[i] = t0 * inv; ++ MACC(m[i], n[0], t0, t1, t2); ++ ++ assert(t0 == 0, "broken Montgomery square"); ++ ++ t0 = t1; t1 = t2; t2 = 0; ++ } ++ ++ for (i = len; i < 2*len; i++) { ++ int start = i-len+1; ++ int end = start + (len - start)/2; ++ int j; ++ for (j = start; j < end; j++) { ++ MACC2(a[j], a[i-j], t0, t1, t2); ++ MACC(m[j], n[i-j], t0, t1, t2); ++ } ++ if ((i & 1) == 0) { ++ MACC(a[j], a[j], t0, t1, t2); ++ } ++ for (; j < len; j++) { ++ MACC(m[j], n[i-j], t0, t1, t2); ++ } ++ m[i-len] = t0; ++ t0 = t1; t1 = t2; t2 = 0; ++ } ++ ++ while (t0) ++ t0 = sub(m, n, t0, len); ++} ++ ++// Swap words in a longword. ++static unsigned long swap(unsigned long x) { ++ return (x << 32) | (x >> 32); ++} ++ ++// Copy len longwords from s to d, word-swapping as we go. The ++// destination array is reversed. ++static void reverse_words(unsigned long *s, unsigned long *d, int len) { ++ d += len; ++ while(len-- > 0) { ++ d--; ++ *d = swap(*s); ++ s++; ++ } ++} ++ ++// The threshold at which squaring is advantageous was determined ++// experimentally on an i7-3930K (Ivy Bridge) CPU @ 3.5GHz. ++#define MONTGOMERY_SQUARING_THRESHOLD 64 ++ ++/* ========================================================================= */ ++static const int crc_table[8][256] = ++{ ++ { ++ 0x00000000UL, 0x77073096UL, 0xee0e612cUL, 0x990951baUL, 0x076dc419UL, ++ 0x706af48fUL, 0xe963a535UL, 0x9e6495a3UL, 0x0edb8832UL, 0x79dcb8a4UL, ++ 0xe0d5e91eUL, 0x97d2d988UL, 0x09b64c2bUL, 0x7eb17cbdUL, 0xe7b82d07UL, ++ 0x90bf1d91UL, 0x1db71064UL, 0x6ab020f2UL, 0xf3b97148UL, 0x84be41deUL, ++ 0x1adad47dUL, 0x6ddde4ebUL, 0xf4d4b551UL, 0x83d385c7UL, 0x136c9856UL, ++ 0x646ba8c0UL, 0xfd62f97aUL, 0x8a65c9ecUL, 0x14015c4fUL, 0x63066cd9UL, ++ 0xfa0f3d63UL, 0x8d080df5UL, 0x3b6e20c8UL, 0x4c69105eUL, 0xd56041e4UL, ++ 0xa2677172UL, 0x3c03e4d1UL, 0x4b04d447UL, 0xd20d85fdUL, 0xa50ab56bUL, ++ 0x35b5a8faUL, 0x42b2986cUL, 0xdbbbc9d6UL, 0xacbcf940UL, 0x32d86ce3UL, ++ 0x45df5c75UL, 0xdcd60dcfUL, 0xabd13d59UL, 0x26d930acUL, 0x51de003aUL, ++ 0xc8d75180UL, 0xbfd06116UL, 0x21b4f4b5UL, 0x56b3c423UL, 0xcfba9599UL, ++ 0xb8bda50fUL, 0x2802b89eUL, 0x5f058808UL, 0xc60cd9b2UL, 0xb10be924UL, ++ 0x2f6f7c87UL, 0x58684c11UL, 0xc1611dabUL, 0xb6662d3dUL, 0x76dc4190UL, ++ 0x01db7106UL, 0x98d220bcUL, 0xefd5102aUL, 0x71b18589UL, 0x06b6b51fUL, ++ 0x9fbfe4a5UL, 0xe8b8d433UL, 0x7807c9a2UL, 0x0f00f934UL, 0x9609a88eUL, ++ 0xe10e9818UL, 0x7f6a0dbbUL, 0x086d3d2dUL, 0x91646c97UL, 0xe6635c01UL, ++ 0x6b6b51f4UL, 0x1c6c6162UL, 0x856530d8UL, 0xf262004eUL, 0x6c0695edUL, ++ 0x1b01a57bUL, 0x8208f4c1UL, 0xf50fc457UL, 0x65b0d9c6UL, 0x12b7e950UL, ++ 0x8bbeb8eaUL, 0xfcb9887cUL, 0x62dd1ddfUL, 0x15da2d49UL, 0x8cd37cf3UL, ++ 0xfbd44c65UL, 0x4db26158UL, 0x3ab551ceUL, 0xa3bc0074UL, 0xd4bb30e2UL, ++ 0x4adfa541UL, 0x3dd895d7UL, 0xa4d1c46dUL, 0xd3d6f4fbUL, 0x4369e96aUL, ++ 0x346ed9fcUL, 0xad678846UL, 0xda60b8d0UL, 0x44042d73UL, 0x33031de5UL, ++ 0xaa0a4c5fUL, 0xdd0d7cc9UL, 0x5005713cUL, 0x270241aaUL, 0xbe0b1010UL, ++ 0xc90c2086UL, 0x5768b525UL, 0x206f85b3UL, 0xb966d409UL, 0xce61e49fUL, ++ 0x5edef90eUL, 0x29d9c998UL, 0xb0d09822UL, 0xc7d7a8b4UL, 0x59b33d17UL, ++ 0x2eb40d81UL, 0xb7bd5c3bUL, 0xc0ba6cadUL, 0xedb88320UL, 0x9abfb3b6UL, ++ 0x03b6e20cUL, 0x74b1d29aUL, 0xead54739UL, 0x9dd277afUL, 0x04db2615UL, ++ 0x73dc1683UL, 0xe3630b12UL, 0x94643b84UL, 0x0d6d6a3eUL, 0x7a6a5aa8UL, ++ 0xe40ecf0bUL, 0x9309ff9dUL, 0x0a00ae27UL, 0x7d079eb1UL, 0xf00f9344UL, ++ 0x8708a3d2UL, 0x1e01f268UL, 0x6906c2feUL, 0xf762575dUL, 0x806567cbUL, ++ 0x196c3671UL, 0x6e6b06e7UL, 0xfed41b76UL, 0x89d32be0UL, 0x10da7a5aUL, ++ 0x67dd4accUL, 0xf9b9df6fUL, 0x8ebeeff9UL, 0x17b7be43UL, 0x60b08ed5UL, ++ 0xd6d6a3e8UL, 0xa1d1937eUL, 0x38d8c2c4UL, 0x4fdff252UL, 0xd1bb67f1UL, ++ 0xa6bc5767UL, 0x3fb506ddUL, 0x48b2364bUL, 0xd80d2bdaUL, 0xaf0a1b4cUL, ++ 0x36034af6UL, 0x41047a60UL, 0xdf60efc3UL, 0xa867df55UL, 0x316e8eefUL, ++ 0x4669be79UL, 0xcb61b38cUL, 0xbc66831aUL, 0x256fd2a0UL, 0x5268e236UL, ++ 0xcc0c7795UL, 0xbb0b4703UL, 0x220216b9UL, 0x5505262fUL, 0xc5ba3bbeUL, ++ 0xb2bd0b28UL, 0x2bb45a92UL, 0x5cb36a04UL, 0xc2d7ffa7UL, 0xb5d0cf31UL, ++ 0x2cd99e8bUL, 0x5bdeae1dUL, 0x9b64c2b0UL, 0xec63f226UL, 0x756aa39cUL, ++ 0x026d930aUL, 0x9c0906a9UL, 0xeb0e363fUL, 0x72076785UL, 0x05005713UL, ++ 0x95bf4a82UL, 0xe2b87a14UL, 0x7bb12baeUL, 0x0cb61b38UL, 0x92d28e9bUL, ++ 0xe5d5be0dUL, 0x7cdcefb7UL, 0x0bdbdf21UL, 0x86d3d2d4UL, 0xf1d4e242UL, ++ 0x68ddb3f8UL, 0x1fda836eUL, 0x81be16cdUL, 0xf6b9265bUL, 0x6fb077e1UL, ++ 0x18b74777UL, 0x88085ae6UL, 0xff0f6a70UL, 0x66063bcaUL, 0x11010b5cUL, ++ 0x8f659effUL, 0xf862ae69UL, 0x616bffd3UL, 0x166ccf45UL, 0xa00ae278UL, ++ 0xd70dd2eeUL, 0x4e048354UL, 0x3903b3c2UL, 0xa7672661UL, 0xd06016f7UL, ++ 0x4969474dUL, 0x3e6e77dbUL, 0xaed16a4aUL, 0xd9d65adcUL, 0x40df0b66UL, ++ 0x37d83bf0UL, 0xa9bcae53UL, 0xdebb9ec5UL, 0x47b2cf7fUL, 0x30b5ffe9UL, ++ 0xbdbdf21cUL, 0xcabac28aUL, 0x53b39330UL, 0x24b4a3a6UL, 0xbad03605UL, ++ 0xcdd70693UL, 0x54de5729UL, 0x23d967bfUL, 0xb3667a2eUL, 0xc4614ab8UL, ++ 0x5d681b02UL, 0x2a6f2b94UL, 0xb40bbe37UL, 0xc30c8ea1UL, 0x5a05df1bUL, ++ 0x2d02ef8dUL ++ }, ++ { ++ 0x00000000UL, 0x191b3141UL, 0x32366282UL, 0x2b2d53c3UL, 0x646cc504UL, ++ 0x7d77f445UL, 0x565aa786UL, 0x4f4196c7UL, 0xc8d98a08UL, 0xd1c2bb49UL, ++ 0xfaefe88aUL, 0xe3f4d9cbUL, 0xacb54f0cUL, 0xb5ae7e4dUL, 0x9e832d8eUL, ++ 0x87981ccfUL, 0x4ac21251UL, 0x53d92310UL, 0x78f470d3UL, 0x61ef4192UL, ++ 0x2eaed755UL, 0x37b5e614UL, 0x1c98b5d7UL, 0x05838496UL, 0x821b9859UL, ++ 0x9b00a918UL, 0xb02dfadbUL, 0xa936cb9aUL, 0xe6775d5dUL, 0xff6c6c1cUL, ++ 0xd4413fdfUL, 0xcd5a0e9eUL, 0x958424a2UL, 0x8c9f15e3UL, 0xa7b24620UL, ++ 0xbea97761UL, 0xf1e8e1a6UL, 0xe8f3d0e7UL, 0xc3de8324UL, 0xdac5b265UL, ++ 0x5d5daeaaUL, 0x44469febUL, 0x6f6bcc28UL, 0x7670fd69UL, 0x39316baeUL, ++ 0x202a5aefUL, 0x0b07092cUL, 0x121c386dUL, 0xdf4636f3UL, 0xc65d07b2UL, ++ 0xed705471UL, 0xf46b6530UL, 0xbb2af3f7UL, 0xa231c2b6UL, 0x891c9175UL, ++ 0x9007a034UL, 0x179fbcfbUL, 0x0e848dbaUL, 0x25a9de79UL, 0x3cb2ef38UL, ++ 0x73f379ffUL, 0x6ae848beUL, 0x41c51b7dUL, 0x58de2a3cUL, 0xf0794f05UL, ++ 0xe9627e44UL, 0xc24f2d87UL, 0xdb541cc6UL, 0x94158a01UL, 0x8d0ebb40UL, ++ 0xa623e883UL, 0xbf38d9c2UL, 0x38a0c50dUL, 0x21bbf44cUL, 0x0a96a78fUL, ++ 0x138d96ceUL, 0x5ccc0009UL, 0x45d73148UL, 0x6efa628bUL, 0x77e153caUL, ++ 0xbabb5d54UL, 0xa3a06c15UL, 0x888d3fd6UL, 0x91960e97UL, 0xded79850UL, ++ 0xc7cca911UL, 0xece1fad2UL, 0xf5facb93UL, 0x7262d75cUL, 0x6b79e61dUL, ++ 0x4054b5deUL, 0x594f849fUL, 0x160e1258UL, 0x0f152319UL, 0x243870daUL, ++ 0x3d23419bUL, 0x65fd6ba7UL, 0x7ce65ae6UL, 0x57cb0925UL, 0x4ed03864UL, ++ 0x0191aea3UL, 0x188a9fe2UL, 0x33a7cc21UL, 0x2abcfd60UL, 0xad24e1afUL, ++ 0xb43fd0eeUL, 0x9f12832dUL, 0x8609b26cUL, 0xc94824abUL, 0xd05315eaUL, ++ 0xfb7e4629UL, 0xe2657768UL, 0x2f3f79f6UL, 0x362448b7UL, 0x1d091b74UL, ++ 0x04122a35UL, 0x4b53bcf2UL, 0x52488db3UL, 0x7965de70UL, 0x607eef31UL, ++ 0xe7e6f3feUL, 0xfefdc2bfUL, 0xd5d0917cUL, 0xcccba03dUL, 0x838a36faUL, ++ 0x9a9107bbUL, 0xb1bc5478UL, 0xa8a76539UL, 0x3b83984bUL, 0x2298a90aUL, ++ 0x09b5fac9UL, 0x10aecb88UL, 0x5fef5d4fUL, 0x46f46c0eUL, 0x6dd93fcdUL, ++ 0x74c20e8cUL, 0xf35a1243UL, 0xea412302UL, 0xc16c70c1UL, 0xd8774180UL, ++ 0x9736d747UL, 0x8e2de606UL, 0xa500b5c5UL, 0xbc1b8484UL, 0x71418a1aUL, ++ 0x685abb5bUL, 0x4377e898UL, 0x5a6cd9d9UL, 0x152d4f1eUL, 0x0c367e5fUL, ++ 0x271b2d9cUL, 0x3e001cddUL, 0xb9980012UL, 0xa0833153UL, 0x8bae6290UL, ++ 0x92b553d1UL, 0xddf4c516UL, 0xc4eff457UL, 0xefc2a794UL, 0xf6d996d5UL, ++ 0xae07bce9UL, 0xb71c8da8UL, 0x9c31de6bUL, 0x852aef2aUL, 0xca6b79edUL, ++ 0xd37048acUL, 0xf85d1b6fUL, 0xe1462a2eUL, 0x66de36e1UL, 0x7fc507a0UL, ++ 0x54e85463UL, 0x4df36522UL, 0x02b2f3e5UL, 0x1ba9c2a4UL, 0x30849167UL, ++ 0x299fa026UL, 0xe4c5aeb8UL, 0xfdde9ff9UL, 0xd6f3cc3aUL, 0xcfe8fd7bUL, ++ 0x80a96bbcUL, 0x99b25afdUL, 0xb29f093eUL, 0xab84387fUL, 0x2c1c24b0UL, ++ 0x350715f1UL, 0x1e2a4632UL, 0x07317773UL, 0x4870e1b4UL, 0x516bd0f5UL, ++ 0x7a468336UL, 0x635db277UL, 0xcbfad74eUL, 0xd2e1e60fUL, 0xf9ccb5ccUL, ++ 0xe0d7848dUL, 0xaf96124aUL, 0xb68d230bUL, 0x9da070c8UL, 0x84bb4189UL, ++ 0x03235d46UL, 0x1a386c07UL, 0x31153fc4UL, 0x280e0e85UL, 0x674f9842UL, ++ 0x7e54a903UL, 0x5579fac0UL, 0x4c62cb81UL, 0x8138c51fUL, 0x9823f45eUL, ++ 0xb30ea79dUL, 0xaa1596dcUL, 0xe554001bUL, 0xfc4f315aUL, 0xd7626299UL, ++ 0xce7953d8UL, 0x49e14f17UL, 0x50fa7e56UL, 0x7bd72d95UL, 0x62cc1cd4UL, ++ 0x2d8d8a13UL, 0x3496bb52UL, 0x1fbbe891UL, 0x06a0d9d0UL, 0x5e7ef3ecUL, ++ 0x4765c2adUL, 0x6c48916eUL, 0x7553a02fUL, 0x3a1236e8UL, 0x230907a9UL, ++ 0x0824546aUL, 0x113f652bUL, 0x96a779e4UL, 0x8fbc48a5UL, 0xa4911b66UL, ++ 0xbd8a2a27UL, 0xf2cbbce0UL, 0xebd08da1UL, 0xc0fdde62UL, 0xd9e6ef23UL, ++ 0x14bce1bdUL, 0x0da7d0fcUL, 0x268a833fUL, 0x3f91b27eUL, 0x70d024b9UL, ++ 0x69cb15f8UL, 0x42e6463bUL, 0x5bfd777aUL, 0xdc656bb5UL, 0xc57e5af4UL, ++ 0xee530937UL, 0xf7483876UL, 0xb809aeb1UL, 0xa1129ff0UL, 0x8a3fcc33UL, ++ 0x9324fd72UL ++ }, ++ { ++ 0x00000000UL, 0x01c26a37UL, 0x0384d46eUL, 0x0246be59UL, 0x0709a8dcUL, ++ 0x06cbc2ebUL, 0x048d7cb2UL, 0x054f1685UL, 0x0e1351b8UL, 0x0fd13b8fUL, ++ 0x0d9785d6UL, 0x0c55efe1UL, 0x091af964UL, 0x08d89353UL, 0x0a9e2d0aUL, ++ 0x0b5c473dUL, 0x1c26a370UL, 0x1de4c947UL, 0x1fa2771eUL, 0x1e601d29UL, ++ 0x1b2f0bacUL, 0x1aed619bUL, 0x18abdfc2UL, 0x1969b5f5UL, 0x1235f2c8UL, ++ 0x13f798ffUL, 0x11b126a6UL, 0x10734c91UL, 0x153c5a14UL, 0x14fe3023UL, ++ 0x16b88e7aUL, 0x177ae44dUL, 0x384d46e0UL, 0x398f2cd7UL, 0x3bc9928eUL, ++ 0x3a0bf8b9UL, 0x3f44ee3cUL, 0x3e86840bUL, 0x3cc03a52UL, 0x3d025065UL, ++ 0x365e1758UL, 0x379c7d6fUL, 0x35dac336UL, 0x3418a901UL, 0x3157bf84UL, ++ 0x3095d5b3UL, 0x32d36beaUL, 0x331101ddUL, 0x246be590UL, 0x25a98fa7UL, ++ 0x27ef31feUL, 0x262d5bc9UL, 0x23624d4cUL, 0x22a0277bUL, 0x20e69922UL, ++ 0x2124f315UL, 0x2a78b428UL, 0x2bbade1fUL, 0x29fc6046UL, 0x283e0a71UL, ++ 0x2d711cf4UL, 0x2cb376c3UL, 0x2ef5c89aUL, 0x2f37a2adUL, 0x709a8dc0UL, ++ 0x7158e7f7UL, 0x731e59aeUL, 0x72dc3399UL, 0x7793251cUL, 0x76514f2bUL, ++ 0x7417f172UL, 0x75d59b45UL, 0x7e89dc78UL, 0x7f4bb64fUL, 0x7d0d0816UL, ++ 0x7ccf6221UL, 0x798074a4UL, 0x78421e93UL, 0x7a04a0caUL, 0x7bc6cafdUL, ++ 0x6cbc2eb0UL, 0x6d7e4487UL, 0x6f38fadeUL, 0x6efa90e9UL, 0x6bb5866cUL, ++ 0x6a77ec5bUL, 0x68315202UL, 0x69f33835UL, 0x62af7f08UL, 0x636d153fUL, ++ 0x612bab66UL, 0x60e9c151UL, 0x65a6d7d4UL, 0x6464bde3UL, 0x662203baUL, ++ 0x67e0698dUL, 0x48d7cb20UL, 0x4915a117UL, 0x4b531f4eUL, 0x4a917579UL, ++ 0x4fde63fcUL, 0x4e1c09cbUL, 0x4c5ab792UL, 0x4d98dda5UL, 0x46c49a98UL, ++ 0x4706f0afUL, 0x45404ef6UL, 0x448224c1UL, 0x41cd3244UL, 0x400f5873UL, ++ 0x4249e62aUL, 0x438b8c1dUL, 0x54f16850UL, 0x55330267UL, 0x5775bc3eUL, ++ 0x56b7d609UL, 0x53f8c08cUL, 0x523aaabbUL, 0x507c14e2UL, 0x51be7ed5UL, ++ 0x5ae239e8UL, 0x5b2053dfUL, 0x5966ed86UL, 0x58a487b1UL, 0x5deb9134UL, ++ 0x5c29fb03UL, 0x5e6f455aUL, 0x5fad2f6dUL, 0xe1351b80UL, 0xe0f771b7UL, ++ 0xe2b1cfeeUL, 0xe373a5d9UL, 0xe63cb35cUL, 0xe7fed96bUL, 0xe5b86732UL, ++ 0xe47a0d05UL, 0xef264a38UL, 0xeee4200fUL, 0xeca29e56UL, 0xed60f461UL, ++ 0xe82fe2e4UL, 0xe9ed88d3UL, 0xebab368aUL, 0xea695cbdUL, 0xfd13b8f0UL, ++ 0xfcd1d2c7UL, 0xfe976c9eUL, 0xff5506a9UL, 0xfa1a102cUL, 0xfbd87a1bUL, ++ 0xf99ec442UL, 0xf85cae75UL, 0xf300e948UL, 0xf2c2837fUL, 0xf0843d26UL, ++ 0xf1465711UL, 0xf4094194UL, 0xf5cb2ba3UL, 0xf78d95faUL, 0xf64fffcdUL, ++ 0xd9785d60UL, 0xd8ba3757UL, 0xdafc890eUL, 0xdb3ee339UL, 0xde71f5bcUL, ++ 0xdfb39f8bUL, 0xddf521d2UL, 0xdc374be5UL, 0xd76b0cd8UL, 0xd6a966efUL, ++ 0xd4efd8b6UL, 0xd52db281UL, 0xd062a404UL, 0xd1a0ce33UL, 0xd3e6706aUL, ++ 0xd2241a5dUL, 0xc55efe10UL, 0xc49c9427UL, 0xc6da2a7eUL, 0xc7184049UL, ++ 0xc25756ccUL, 0xc3953cfbUL, 0xc1d382a2UL, 0xc011e895UL, 0xcb4dafa8UL, ++ 0xca8fc59fUL, 0xc8c97bc6UL, 0xc90b11f1UL, 0xcc440774UL, 0xcd866d43UL, ++ 0xcfc0d31aUL, 0xce02b92dUL, 0x91af9640UL, 0x906dfc77UL, 0x922b422eUL, ++ 0x93e92819UL, 0x96a63e9cUL, 0x976454abUL, 0x9522eaf2UL, 0x94e080c5UL, ++ 0x9fbcc7f8UL, 0x9e7eadcfUL, 0x9c381396UL, 0x9dfa79a1UL, 0x98b56f24UL, ++ 0x99770513UL, 0x9b31bb4aUL, 0x9af3d17dUL, 0x8d893530UL, 0x8c4b5f07UL, ++ 0x8e0de15eUL, 0x8fcf8b69UL, 0x8a809decUL, 0x8b42f7dbUL, 0x89044982UL, ++ 0x88c623b5UL, 0x839a6488UL, 0x82580ebfUL, 0x801eb0e6UL, 0x81dcdad1UL, ++ 0x8493cc54UL, 0x8551a663UL, 0x8717183aUL, 0x86d5720dUL, 0xa9e2d0a0UL, ++ 0xa820ba97UL, 0xaa6604ceUL, 0xaba46ef9UL, 0xaeeb787cUL, 0xaf29124bUL, ++ 0xad6fac12UL, 0xacadc625UL, 0xa7f18118UL, 0xa633eb2fUL, 0xa4755576UL, ++ 0xa5b73f41UL, 0xa0f829c4UL, 0xa13a43f3UL, 0xa37cfdaaUL, 0xa2be979dUL, ++ 0xb5c473d0UL, 0xb40619e7UL, 0xb640a7beUL, 0xb782cd89UL, 0xb2cddb0cUL, ++ 0xb30fb13bUL, 0xb1490f62UL, 0xb08b6555UL, 0xbbd72268UL, 0xba15485fUL, ++ 0xb853f606UL, 0xb9919c31UL, 0xbcde8ab4UL, 0xbd1ce083UL, 0xbf5a5edaUL, ++ 0xbe9834edUL ++ }, ++ { ++ 0x00000000UL, 0xb8bc6765UL, 0xaa09c88bUL, 0x12b5afeeUL, 0x8f629757UL, ++ 0x37def032UL, 0x256b5fdcUL, 0x9dd738b9UL, 0xc5b428efUL, 0x7d084f8aUL, ++ 0x6fbde064UL, 0xd7018701UL, 0x4ad6bfb8UL, 0xf26ad8ddUL, 0xe0df7733UL, ++ 0x58631056UL, 0x5019579fUL, 0xe8a530faUL, 0xfa109f14UL, 0x42acf871UL, ++ 0xdf7bc0c8UL, 0x67c7a7adUL, 0x75720843UL, 0xcdce6f26UL, 0x95ad7f70UL, ++ 0x2d111815UL, 0x3fa4b7fbUL, 0x8718d09eUL, 0x1acfe827UL, 0xa2738f42UL, ++ 0xb0c620acUL, 0x087a47c9UL, 0xa032af3eUL, 0x188ec85bUL, 0x0a3b67b5UL, ++ 0xb28700d0UL, 0x2f503869UL, 0x97ec5f0cUL, 0x8559f0e2UL, 0x3de59787UL, ++ 0x658687d1UL, 0xdd3ae0b4UL, 0xcf8f4f5aUL, 0x7733283fUL, 0xeae41086UL, ++ 0x525877e3UL, 0x40edd80dUL, 0xf851bf68UL, 0xf02bf8a1UL, 0x48979fc4UL, ++ 0x5a22302aUL, 0xe29e574fUL, 0x7f496ff6UL, 0xc7f50893UL, 0xd540a77dUL, ++ 0x6dfcc018UL, 0x359fd04eUL, 0x8d23b72bUL, 0x9f9618c5UL, 0x272a7fa0UL, ++ 0xbafd4719UL, 0x0241207cUL, 0x10f48f92UL, 0xa848e8f7UL, 0x9b14583dUL, ++ 0x23a83f58UL, 0x311d90b6UL, 0x89a1f7d3UL, 0x1476cf6aUL, 0xaccaa80fUL, ++ 0xbe7f07e1UL, 0x06c36084UL, 0x5ea070d2UL, 0xe61c17b7UL, 0xf4a9b859UL, ++ 0x4c15df3cUL, 0xd1c2e785UL, 0x697e80e0UL, 0x7bcb2f0eUL, 0xc377486bUL, ++ 0xcb0d0fa2UL, 0x73b168c7UL, 0x6104c729UL, 0xd9b8a04cUL, 0x446f98f5UL, ++ 0xfcd3ff90UL, 0xee66507eUL, 0x56da371bUL, 0x0eb9274dUL, 0xb6054028UL, ++ 0xa4b0efc6UL, 0x1c0c88a3UL, 0x81dbb01aUL, 0x3967d77fUL, 0x2bd27891UL, ++ 0x936e1ff4UL, 0x3b26f703UL, 0x839a9066UL, 0x912f3f88UL, 0x299358edUL, ++ 0xb4446054UL, 0x0cf80731UL, 0x1e4da8dfUL, 0xa6f1cfbaUL, 0xfe92dfecUL, ++ 0x462eb889UL, 0x549b1767UL, 0xec277002UL, 0x71f048bbUL, 0xc94c2fdeUL, ++ 0xdbf98030UL, 0x6345e755UL, 0x6b3fa09cUL, 0xd383c7f9UL, 0xc1366817UL, ++ 0x798a0f72UL, 0xe45d37cbUL, 0x5ce150aeUL, 0x4e54ff40UL, 0xf6e89825UL, ++ 0xae8b8873UL, 0x1637ef16UL, 0x048240f8UL, 0xbc3e279dUL, 0x21e91f24UL, ++ 0x99557841UL, 0x8be0d7afUL, 0x335cb0caUL, 0xed59b63bUL, 0x55e5d15eUL, ++ 0x47507eb0UL, 0xffec19d5UL, 0x623b216cUL, 0xda874609UL, 0xc832e9e7UL, ++ 0x708e8e82UL, 0x28ed9ed4UL, 0x9051f9b1UL, 0x82e4565fUL, 0x3a58313aUL, ++ 0xa78f0983UL, 0x1f336ee6UL, 0x0d86c108UL, 0xb53aa66dUL, 0xbd40e1a4UL, ++ 0x05fc86c1UL, 0x1749292fUL, 0xaff54e4aUL, 0x322276f3UL, 0x8a9e1196UL, ++ 0x982bbe78UL, 0x2097d91dUL, 0x78f4c94bUL, 0xc048ae2eUL, 0xd2fd01c0UL, ++ 0x6a4166a5UL, 0xf7965e1cUL, 0x4f2a3979UL, 0x5d9f9697UL, 0xe523f1f2UL, ++ 0x4d6b1905UL, 0xf5d77e60UL, 0xe762d18eUL, 0x5fdeb6ebUL, 0xc2098e52UL, ++ 0x7ab5e937UL, 0x680046d9UL, 0xd0bc21bcUL, 0x88df31eaUL, 0x3063568fUL, ++ 0x22d6f961UL, 0x9a6a9e04UL, 0x07bda6bdUL, 0xbf01c1d8UL, 0xadb46e36UL, ++ 0x15080953UL, 0x1d724e9aUL, 0xa5ce29ffUL, 0xb77b8611UL, 0x0fc7e174UL, ++ 0x9210d9cdUL, 0x2aacbea8UL, 0x38191146UL, 0x80a57623UL, 0xd8c66675UL, ++ 0x607a0110UL, 0x72cfaefeUL, 0xca73c99bUL, 0x57a4f122UL, 0xef189647UL, ++ 0xfdad39a9UL, 0x45115eccUL, 0x764dee06UL, 0xcef18963UL, 0xdc44268dUL, ++ 0x64f841e8UL, 0xf92f7951UL, 0x41931e34UL, 0x5326b1daUL, 0xeb9ad6bfUL, ++ 0xb3f9c6e9UL, 0x0b45a18cUL, 0x19f00e62UL, 0xa14c6907UL, 0x3c9b51beUL, ++ 0x842736dbUL, 0x96929935UL, 0x2e2efe50UL, 0x2654b999UL, 0x9ee8defcUL, ++ 0x8c5d7112UL, 0x34e11677UL, 0xa9362eceUL, 0x118a49abUL, 0x033fe645UL, ++ 0xbb838120UL, 0xe3e09176UL, 0x5b5cf613UL, 0x49e959fdUL, 0xf1553e98UL, ++ 0x6c820621UL, 0xd43e6144UL, 0xc68bceaaUL, 0x7e37a9cfUL, 0xd67f4138UL, ++ 0x6ec3265dUL, 0x7c7689b3UL, 0xc4caeed6UL, 0x591dd66fUL, 0xe1a1b10aUL, ++ 0xf3141ee4UL, 0x4ba87981UL, 0x13cb69d7UL, 0xab770eb2UL, 0xb9c2a15cUL, ++ 0x017ec639UL, 0x9ca9fe80UL, 0x241599e5UL, 0x36a0360bUL, 0x8e1c516eUL, ++ 0x866616a7UL, 0x3eda71c2UL, 0x2c6fde2cUL, 0x94d3b949UL, 0x090481f0UL, ++ 0xb1b8e695UL, 0xa30d497bUL, 0x1bb12e1eUL, 0x43d23e48UL, 0xfb6e592dUL, ++ 0xe9dbf6c3UL, 0x516791a6UL, 0xccb0a91fUL, 0x740cce7aUL, 0x66b96194UL, ++ 0xde0506f1UL ++ }, ++ { ++ 0x00000000UL, 0x96300777UL, 0x2c610eeeUL, 0xba510999UL, 0x19c46d07UL, ++ 0x8ff46a70UL, 0x35a563e9UL, 0xa395649eUL, 0x3288db0eUL, 0xa4b8dc79UL, ++ 0x1ee9d5e0UL, 0x88d9d297UL, 0x2b4cb609UL, 0xbd7cb17eUL, 0x072db8e7UL, ++ 0x911dbf90UL, 0x6410b71dUL, 0xf220b06aUL, 0x4871b9f3UL, 0xde41be84UL, ++ 0x7dd4da1aUL, 0xebe4dd6dUL, 0x51b5d4f4UL, 0xc785d383UL, 0x56986c13UL, ++ 0xc0a86b64UL, 0x7af962fdUL, 0xecc9658aUL, 0x4f5c0114UL, 0xd96c0663UL, ++ 0x633d0ffaUL, 0xf50d088dUL, 0xc8206e3bUL, 0x5e10694cUL, 0xe44160d5UL, ++ 0x727167a2UL, 0xd1e4033cUL, 0x47d4044bUL, 0xfd850dd2UL, 0x6bb50aa5UL, ++ 0xfaa8b535UL, 0x6c98b242UL, 0xd6c9bbdbUL, 0x40f9bcacUL, 0xe36cd832UL, ++ 0x755cdf45UL, 0xcf0dd6dcUL, 0x593dd1abUL, 0xac30d926UL, 0x3a00de51UL, ++ 0x8051d7c8UL, 0x1661d0bfUL, 0xb5f4b421UL, 0x23c4b356UL, 0x9995bacfUL, ++ 0x0fa5bdb8UL, 0x9eb80228UL, 0x0888055fUL, 0xb2d90cc6UL, 0x24e90bb1UL, ++ 0x877c6f2fUL, 0x114c6858UL, 0xab1d61c1UL, 0x3d2d66b6UL, 0x9041dc76UL, ++ 0x0671db01UL, 0xbc20d298UL, 0x2a10d5efUL, 0x8985b171UL, 0x1fb5b606UL, ++ 0xa5e4bf9fUL, 0x33d4b8e8UL, 0xa2c90778UL, 0x34f9000fUL, 0x8ea80996UL, ++ 0x18980ee1UL, 0xbb0d6a7fUL, 0x2d3d6d08UL, 0x976c6491UL, 0x015c63e6UL, ++ 0xf4516b6bUL, 0x62616c1cUL, 0xd8306585UL, 0x4e0062f2UL, 0xed95066cUL, ++ 0x7ba5011bUL, 0xc1f40882UL, 0x57c40ff5UL, 0xc6d9b065UL, 0x50e9b712UL, ++ 0xeab8be8bUL, 0x7c88b9fcUL, 0xdf1ddd62UL, 0x492dda15UL, 0xf37cd38cUL, ++ 0x654cd4fbUL, 0x5861b24dUL, 0xce51b53aUL, 0x7400bca3UL, 0xe230bbd4UL, ++ 0x41a5df4aUL, 0xd795d83dUL, 0x6dc4d1a4UL, 0xfbf4d6d3UL, 0x6ae96943UL, ++ 0xfcd96e34UL, 0x468867adUL, 0xd0b860daUL, 0x732d0444UL, 0xe51d0333UL, ++ 0x5f4c0aaaUL, 0xc97c0dddUL, 0x3c710550UL, 0xaa410227UL, 0x10100bbeUL, ++ 0x86200cc9UL, 0x25b56857UL, 0xb3856f20UL, 0x09d466b9UL, 0x9fe461ceUL, ++ 0x0ef9de5eUL, 0x98c9d929UL, 0x2298d0b0UL, 0xb4a8d7c7UL, 0x173db359UL, ++ 0x810db42eUL, 0x3b5cbdb7UL, 0xad6cbac0UL, 0x2083b8edUL, 0xb6b3bf9aUL, ++ 0x0ce2b603UL, 0x9ad2b174UL, 0x3947d5eaUL, 0xaf77d29dUL, 0x1526db04UL, ++ 0x8316dc73UL, 0x120b63e3UL, 0x843b6494UL, 0x3e6a6d0dUL, 0xa85a6a7aUL, ++ 0x0bcf0ee4UL, 0x9dff0993UL, 0x27ae000aUL, 0xb19e077dUL, 0x44930ff0UL, ++ 0xd2a30887UL, 0x68f2011eUL, 0xfec20669UL, 0x5d5762f7UL, 0xcb676580UL, ++ 0x71366c19UL, 0xe7066b6eUL, 0x761bd4feUL, 0xe02bd389UL, 0x5a7ada10UL, ++ 0xcc4add67UL, 0x6fdfb9f9UL, 0xf9efbe8eUL, 0x43beb717UL, 0xd58eb060UL, ++ 0xe8a3d6d6UL, 0x7e93d1a1UL, 0xc4c2d838UL, 0x52f2df4fUL, 0xf167bbd1UL, ++ 0x6757bca6UL, 0xdd06b53fUL, 0x4b36b248UL, 0xda2b0dd8UL, 0x4c1b0aafUL, ++ 0xf64a0336UL, 0x607a0441UL, 0xc3ef60dfUL, 0x55df67a8UL, 0xef8e6e31UL, ++ 0x79be6946UL, 0x8cb361cbUL, 0x1a8366bcUL, 0xa0d26f25UL, 0x36e26852UL, ++ 0x95770cccUL, 0x03470bbbUL, 0xb9160222UL, 0x2f260555UL, 0xbe3bbac5UL, ++ 0x280bbdb2UL, 0x925ab42bUL, 0x046ab35cUL, 0xa7ffd7c2UL, 0x31cfd0b5UL, ++ 0x8b9ed92cUL, 0x1daede5bUL, 0xb0c2649bUL, 0x26f263ecUL, 0x9ca36a75UL, ++ 0x0a936d02UL, 0xa906099cUL, 0x3f360eebUL, 0x85670772UL, 0x13570005UL, ++ 0x824abf95UL, 0x147ab8e2UL, 0xae2bb17bUL, 0x381bb60cUL, 0x9b8ed292UL, ++ 0x0dbed5e5UL, 0xb7efdc7cUL, 0x21dfdb0bUL, 0xd4d2d386UL, 0x42e2d4f1UL, ++ 0xf8b3dd68UL, 0x6e83da1fUL, 0xcd16be81UL, 0x5b26b9f6UL, 0xe177b06fUL, ++ 0x7747b718UL, 0xe65a0888UL, 0x706a0fffUL, 0xca3b0666UL, 0x5c0b0111UL, ++ 0xff9e658fUL, 0x69ae62f8UL, 0xd3ff6b61UL, 0x45cf6c16UL, 0x78e20aa0UL, ++ 0xeed20dd7UL, 0x5483044eUL, 0xc2b30339UL, 0x612667a7UL, 0xf71660d0UL, ++ 0x4d476949UL, 0xdb776e3eUL, 0x4a6ad1aeUL, 0xdc5ad6d9UL, 0x660bdf40UL, ++ 0xf03bd837UL, 0x53aebca9UL, 0xc59ebbdeUL, 0x7fcfb247UL, 0xe9ffb530UL, ++ 0x1cf2bdbdUL, 0x8ac2bacaUL, 0x3093b353UL, 0xa6a3b424UL, 0x0536d0baUL, ++ 0x9306d7cdUL, 0x2957de54UL, 0xbf67d923UL, 0x2e7a66b3UL, 0xb84a61c4UL, ++ 0x021b685dUL, 0x942b6f2aUL, 0x37be0bb4UL, 0xa18e0cc3UL, 0x1bdf055aUL, ++ 0x8def022dUL ++ }, ++ { ++ 0x00000000UL, 0x41311b19UL, 0x82623632UL, 0xc3532d2bUL, 0x04c56c64UL, ++ 0x45f4777dUL, 0x86a75a56UL, 0xc796414fUL, 0x088ad9c8UL, 0x49bbc2d1UL, ++ 0x8ae8effaUL, 0xcbd9f4e3UL, 0x0c4fb5acUL, 0x4d7eaeb5UL, 0x8e2d839eUL, ++ 0xcf1c9887UL, 0x5112c24aUL, 0x1023d953UL, 0xd370f478UL, 0x9241ef61UL, ++ 0x55d7ae2eUL, 0x14e6b537UL, 0xd7b5981cUL, 0x96848305UL, 0x59981b82UL, ++ 0x18a9009bUL, 0xdbfa2db0UL, 0x9acb36a9UL, 0x5d5d77e6UL, 0x1c6c6cffUL, ++ 0xdf3f41d4UL, 0x9e0e5acdUL, 0xa2248495UL, 0xe3159f8cUL, 0x2046b2a7UL, ++ 0x6177a9beUL, 0xa6e1e8f1UL, 0xe7d0f3e8UL, 0x2483dec3UL, 0x65b2c5daUL, ++ 0xaaae5d5dUL, 0xeb9f4644UL, 0x28cc6b6fUL, 0x69fd7076UL, 0xae6b3139UL, ++ 0xef5a2a20UL, 0x2c09070bUL, 0x6d381c12UL, 0xf33646dfUL, 0xb2075dc6UL, ++ 0x715470edUL, 0x30656bf4UL, 0xf7f32abbUL, 0xb6c231a2UL, 0x75911c89UL, ++ 0x34a00790UL, 0xfbbc9f17UL, 0xba8d840eUL, 0x79dea925UL, 0x38efb23cUL, ++ 0xff79f373UL, 0xbe48e86aUL, 0x7d1bc541UL, 0x3c2ade58UL, 0x054f79f0UL, ++ 0x447e62e9UL, 0x872d4fc2UL, 0xc61c54dbUL, 0x018a1594UL, 0x40bb0e8dUL, ++ 0x83e823a6UL, 0xc2d938bfUL, 0x0dc5a038UL, 0x4cf4bb21UL, 0x8fa7960aUL, ++ 0xce968d13UL, 0x0900cc5cUL, 0x4831d745UL, 0x8b62fa6eUL, 0xca53e177UL, ++ 0x545dbbbaUL, 0x156ca0a3UL, 0xd63f8d88UL, 0x970e9691UL, 0x5098d7deUL, ++ 0x11a9ccc7UL, 0xd2fae1ecUL, 0x93cbfaf5UL, 0x5cd76272UL, 0x1de6796bUL, ++ 0xdeb55440UL, 0x9f844f59UL, 0x58120e16UL, 0x1923150fUL, 0xda703824UL, ++ 0x9b41233dUL, 0xa76bfd65UL, 0xe65ae67cUL, 0x2509cb57UL, 0x6438d04eUL, ++ 0xa3ae9101UL, 0xe29f8a18UL, 0x21cca733UL, 0x60fdbc2aUL, 0xafe124adUL, ++ 0xeed03fb4UL, 0x2d83129fUL, 0x6cb20986UL, 0xab2448c9UL, 0xea1553d0UL, ++ 0x29467efbUL, 0x687765e2UL, 0xf6793f2fUL, 0xb7482436UL, 0x741b091dUL, ++ 0x352a1204UL, 0xf2bc534bUL, 0xb38d4852UL, 0x70de6579UL, 0x31ef7e60UL, ++ 0xfef3e6e7UL, 0xbfc2fdfeUL, 0x7c91d0d5UL, 0x3da0cbccUL, 0xfa368a83UL, ++ 0xbb07919aUL, 0x7854bcb1UL, 0x3965a7a8UL, 0x4b98833bUL, 0x0aa99822UL, ++ 0xc9fab509UL, 0x88cbae10UL, 0x4f5def5fUL, 0x0e6cf446UL, 0xcd3fd96dUL, ++ 0x8c0ec274UL, 0x43125af3UL, 0x022341eaUL, 0xc1706cc1UL, 0x804177d8UL, ++ 0x47d73697UL, 0x06e62d8eUL, 0xc5b500a5UL, 0x84841bbcUL, 0x1a8a4171UL, ++ 0x5bbb5a68UL, 0x98e87743UL, 0xd9d96c5aUL, 0x1e4f2d15UL, 0x5f7e360cUL, ++ 0x9c2d1b27UL, 0xdd1c003eUL, 0x120098b9UL, 0x533183a0UL, 0x9062ae8bUL, ++ 0xd153b592UL, 0x16c5f4ddUL, 0x57f4efc4UL, 0x94a7c2efUL, 0xd596d9f6UL, ++ 0xe9bc07aeUL, 0xa88d1cb7UL, 0x6bde319cUL, 0x2aef2a85UL, 0xed796bcaUL, ++ 0xac4870d3UL, 0x6f1b5df8UL, 0x2e2a46e1UL, 0xe136de66UL, 0xa007c57fUL, ++ 0x6354e854UL, 0x2265f34dUL, 0xe5f3b202UL, 0xa4c2a91bUL, 0x67918430UL, ++ 0x26a09f29UL, 0xb8aec5e4UL, 0xf99fdefdUL, 0x3accf3d6UL, 0x7bfde8cfUL, ++ 0xbc6ba980UL, 0xfd5ab299UL, 0x3e099fb2UL, 0x7f3884abUL, 0xb0241c2cUL, ++ 0xf1150735UL, 0x32462a1eUL, 0x73773107UL, 0xb4e17048UL, 0xf5d06b51UL, ++ 0x3683467aUL, 0x77b25d63UL, 0x4ed7facbUL, 0x0fe6e1d2UL, 0xccb5ccf9UL, ++ 0x8d84d7e0UL, 0x4a1296afUL, 0x0b238db6UL, 0xc870a09dUL, 0x8941bb84UL, ++ 0x465d2303UL, 0x076c381aUL, 0xc43f1531UL, 0x850e0e28UL, 0x42984f67UL, ++ 0x03a9547eUL, 0xc0fa7955UL, 0x81cb624cUL, 0x1fc53881UL, 0x5ef42398UL, ++ 0x9da70eb3UL, 0xdc9615aaUL, 0x1b0054e5UL, 0x5a314ffcUL, 0x996262d7UL, ++ 0xd85379ceUL, 0x174fe149UL, 0x567efa50UL, 0x952dd77bUL, 0xd41ccc62UL, ++ 0x138a8d2dUL, 0x52bb9634UL, 0x91e8bb1fUL, 0xd0d9a006UL, 0xecf37e5eUL, ++ 0xadc26547UL, 0x6e91486cUL, 0x2fa05375UL, 0xe836123aUL, 0xa9070923UL, ++ 0x6a542408UL, 0x2b653f11UL, 0xe479a796UL, 0xa548bc8fUL, 0x661b91a4UL, ++ 0x272a8abdUL, 0xe0bccbf2UL, 0xa18dd0ebUL, 0x62defdc0UL, 0x23efe6d9UL, ++ 0xbde1bc14UL, 0xfcd0a70dUL, 0x3f838a26UL, 0x7eb2913fUL, 0xb924d070UL, ++ 0xf815cb69UL, 0x3b46e642UL, 0x7a77fd5bUL, 0xb56b65dcUL, 0xf45a7ec5UL, ++ 0x370953eeUL, 0x763848f7UL, 0xb1ae09b8UL, 0xf09f12a1UL, 0x33cc3f8aUL, ++ 0x72fd2493UL ++ }, ++ { ++ 0x00000000UL, 0x376ac201UL, 0x6ed48403UL, 0x59be4602UL, 0xdca80907UL, ++ 0xebc2cb06UL, 0xb27c8d04UL, 0x85164f05UL, 0xb851130eUL, 0x8f3bd10fUL, ++ 0xd685970dUL, 0xe1ef550cUL, 0x64f91a09UL, 0x5393d808UL, 0x0a2d9e0aUL, ++ 0x3d475c0bUL, 0x70a3261cUL, 0x47c9e41dUL, 0x1e77a21fUL, 0x291d601eUL, ++ 0xac0b2f1bUL, 0x9b61ed1aUL, 0xc2dfab18UL, 0xf5b56919UL, 0xc8f23512UL, ++ 0xff98f713UL, 0xa626b111UL, 0x914c7310UL, 0x145a3c15UL, 0x2330fe14UL, ++ 0x7a8eb816UL, 0x4de47a17UL, 0xe0464d38UL, 0xd72c8f39UL, 0x8e92c93bUL, ++ 0xb9f80b3aUL, 0x3cee443fUL, 0x0b84863eUL, 0x523ac03cUL, 0x6550023dUL, ++ 0x58175e36UL, 0x6f7d9c37UL, 0x36c3da35UL, 0x01a91834UL, 0x84bf5731UL, ++ 0xb3d59530UL, 0xea6bd332UL, 0xdd011133UL, 0x90e56b24UL, 0xa78fa925UL, ++ 0xfe31ef27UL, 0xc95b2d26UL, 0x4c4d6223UL, 0x7b27a022UL, 0x2299e620UL, ++ 0x15f32421UL, 0x28b4782aUL, 0x1fdeba2bUL, 0x4660fc29UL, 0x710a3e28UL, ++ 0xf41c712dUL, 0xc376b32cUL, 0x9ac8f52eUL, 0xada2372fUL, 0xc08d9a70UL, ++ 0xf7e75871UL, 0xae591e73UL, 0x9933dc72UL, 0x1c259377UL, 0x2b4f5176UL, ++ 0x72f11774UL, 0x459bd575UL, 0x78dc897eUL, 0x4fb64b7fUL, 0x16080d7dUL, ++ 0x2162cf7cUL, 0xa4748079UL, 0x931e4278UL, 0xcaa0047aUL, 0xfdcac67bUL, ++ 0xb02ebc6cUL, 0x87447e6dUL, 0xdefa386fUL, 0xe990fa6eUL, 0x6c86b56bUL, ++ 0x5bec776aUL, 0x02523168UL, 0x3538f369UL, 0x087faf62UL, 0x3f156d63UL, ++ 0x66ab2b61UL, 0x51c1e960UL, 0xd4d7a665UL, 0xe3bd6464UL, 0xba032266UL, ++ 0x8d69e067UL, 0x20cbd748UL, 0x17a11549UL, 0x4e1f534bUL, 0x7975914aUL, ++ 0xfc63de4fUL, 0xcb091c4eUL, 0x92b75a4cUL, 0xa5dd984dUL, 0x989ac446UL, ++ 0xaff00647UL, 0xf64e4045UL, 0xc1248244UL, 0x4432cd41UL, 0x73580f40UL, ++ 0x2ae64942UL, 0x1d8c8b43UL, 0x5068f154UL, 0x67023355UL, 0x3ebc7557UL, ++ 0x09d6b756UL, 0x8cc0f853UL, 0xbbaa3a52UL, 0xe2147c50UL, 0xd57ebe51UL, ++ 0xe839e25aUL, 0xdf53205bUL, 0x86ed6659UL, 0xb187a458UL, 0x3491eb5dUL, ++ 0x03fb295cUL, 0x5a456f5eUL, 0x6d2fad5fUL, 0x801b35e1UL, 0xb771f7e0UL, ++ 0xeecfb1e2UL, 0xd9a573e3UL, 0x5cb33ce6UL, 0x6bd9fee7UL, 0x3267b8e5UL, ++ 0x050d7ae4UL, 0x384a26efUL, 0x0f20e4eeUL, 0x569ea2ecUL, 0x61f460edUL, ++ 0xe4e22fe8UL, 0xd388ede9UL, 0x8a36abebUL, 0xbd5c69eaUL, 0xf0b813fdUL, ++ 0xc7d2d1fcUL, 0x9e6c97feUL, 0xa90655ffUL, 0x2c101afaUL, 0x1b7ad8fbUL, ++ 0x42c49ef9UL, 0x75ae5cf8UL, 0x48e900f3UL, 0x7f83c2f2UL, 0x263d84f0UL, ++ 0x115746f1UL, 0x944109f4UL, 0xa32bcbf5UL, 0xfa958df7UL, 0xcdff4ff6UL, ++ 0x605d78d9UL, 0x5737bad8UL, 0x0e89fcdaUL, 0x39e33edbUL, 0xbcf571deUL, ++ 0x8b9fb3dfUL, 0xd221f5ddUL, 0xe54b37dcUL, 0xd80c6bd7UL, 0xef66a9d6UL, ++ 0xb6d8efd4UL, 0x81b22dd5UL, 0x04a462d0UL, 0x33cea0d1UL, 0x6a70e6d3UL, ++ 0x5d1a24d2UL, 0x10fe5ec5UL, 0x27949cc4UL, 0x7e2adac6UL, 0x494018c7UL, ++ 0xcc5657c2UL, 0xfb3c95c3UL, 0xa282d3c1UL, 0x95e811c0UL, 0xa8af4dcbUL, ++ 0x9fc58fcaUL, 0xc67bc9c8UL, 0xf1110bc9UL, 0x740744ccUL, 0x436d86cdUL, ++ 0x1ad3c0cfUL, 0x2db902ceUL, 0x4096af91UL, 0x77fc6d90UL, 0x2e422b92UL, ++ 0x1928e993UL, 0x9c3ea696UL, 0xab546497UL, 0xf2ea2295UL, 0xc580e094UL, ++ 0xf8c7bc9fUL, 0xcfad7e9eUL, 0x9613389cUL, 0xa179fa9dUL, 0x246fb598UL, ++ 0x13057799UL, 0x4abb319bUL, 0x7dd1f39aUL, 0x3035898dUL, 0x075f4b8cUL, ++ 0x5ee10d8eUL, 0x698bcf8fUL, 0xec9d808aUL, 0xdbf7428bUL, 0x82490489UL, ++ 0xb523c688UL, 0x88649a83UL, 0xbf0e5882UL, 0xe6b01e80UL, 0xd1dadc81UL, ++ 0x54cc9384UL, 0x63a65185UL, 0x3a181787UL, 0x0d72d586UL, 0xa0d0e2a9UL, ++ 0x97ba20a8UL, 0xce0466aaUL, 0xf96ea4abUL, 0x7c78ebaeUL, 0x4b1229afUL, ++ 0x12ac6fadUL, 0x25c6adacUL, 0x1881f1a7UL, 0x2feb33a6UL, 0x765575a4UL, ++ 0x413fb7a5UL, 0xc429f8a0UL, 0xf3433aa1UL, 0xaafd7ca3UL, 0x9d97bea2UL, ++ 0xd073c4b5UL, 0xe71906b4UL, 0xbea740b6UL, 0x89cd82b7UL, 0x0cdbcdb2UL, ++ 0x3bb10fb3UL, 0x620f49b1UL, 0x55658bb0UL, 0x6822d7bbUL, 0x5f4815baUL, ++ 0x06f653b8UL, 0x319c91b9UL, 0xb48adebcUL, 0x83e01cbdUL, 0xda5e5abfUL, ++ 0xed3498beUL ++ }, ++ { ++ 0x00000000UL, 0x6567bcb8UL, 0x8bc809aaUL, 0xeeafb512UL, 0x5797628fUL, ++ 0x32f0de37UL, 0xdc5f6b25UL, 0xb938d79dUL, 0xef28b4c5UL, 0x8a4f087dUL, ++ 0x64e0bd6fUL, 0x018701d7UL, 0xb8bfd64aUL, 0xddd86af2UL, 0x3377dfe0UL, ++ 0x56106358UL, 0x9f571950UL, 0xfa30a5e8UL, 0x149f10faUL, 0x71f8ac42UL, ++ 0xc8c07bdfUL, 0xada7c767UL, 0x43087275UL, 0x266fcecdUL, 0x707fad95UL, ++ 0x1518112dUL, 0xfbb7a43fUL, 0x9ed01887UL, 0x27e8cf1aUL, 0x428f73a2UL, ++ 0xac20c6b0UL, 0xc9477a08UL, 0x3eaf32a0UL, 0x5bc88e18UL, 0xb5673b0aUL, ++ 0xd00087b2UL, 0x6938502fUL, 0x0c5fec97UL, 0xe2f05985UL, 0x8797e53dUL, ++ 0xd1878665UL, 0xb4e03addUL, 0x5a4f8fcfUL, 0x3f283377UL, 0x8610e4eaUL, ++ 0xe3775852UL, 0x0dd8ed40UL, 0x68bf51f8UL, 0xa1f82bf0UL, 0xc49f9748UL, ++ 0x2a30225aUL, 0x4f579ee2UL, 0xf66f497fUL, 0x9308f5c7UL, 0x7da740d5UL, ++ 0x18c0fc6dUL, 0x4ed09f35UL, 0x2bb7238dUL, 0xc518969fUL, 0xa07f2a27UL, ++ 0x1947fdbaUL, 0x7c204102UL, 0x928ff410UL, 0xf7e848a8UL, 0x3d58149bUL, ++ 0x583fa823UL, 0xb6901d31UL, 0xd3f7a189UL, 0x6acf7614UL, 0x0fa8caacUL, ++ 0xe1077fbeUL, 0x8460c306UL, 0xd270a05eUL, 0xb7171ce6UL, 0x59b8a9f4UL, ++ 0x3cdf154cUL, 0x85e7c2d1UL, 0xe0807e69UL, 0x0e2fcb7bUL, 0x6b4877c3UL, ++ 0xa20f0dcbUL, 0xc768b173UL, 0x29c70461UL, 0x4ca0b8d9UL, 0xf5986f44UL, ++ 0x90ffd3fcUL, 0x7e5066eeUL, 0x1b37da56UL, 0x4d27b90eUL, 0x284005b6UL, ++ 0xc6efb0a4UL, 0xa3880c1cUL, 0x1ab0db81UL, 0x7fd76739UL, 0x9178d22bUL, ++ 0xf41f6e93UL, 0x03f7263bUL, 0x66909a83UL, 0x883f2f91UL, 0xed589329UL, ++ 0x546044b4UL, 0x3107f80cUL, 0xdfa84d1eUL, 0xbacff1a6UL, 0xecdf92feUL, ++ 0x89b82e46UL, 0x67179b54UL, 0x027027ecUL, 0xbb48f071UL, 0xde2f4cc9UL, ++ 0x3080f9dbUL, 0x55e74563UL, 0x9ca03f6bUL, 0xf9c783d3UL, 0x176836c1UL, ++ 0x720f8a79UL, 0xcb375de4UL, 0xae50e15cUL, 0x40ff544eUL, 0x2598e8f6UL, ++ 0x73888baeUL, 0x16ef3716UL, 0xf8408204UL, 0x9d273ebcUL, 0x241fe921UL, ++ 0x41785599UL, 0xafd7e08bUL, 0xcab05c33UL, 0x3bb659edUL, 0x5ed1e555UL, ++ 0xb07e5047UL, 0xd519ecffUL, 0x6c213b62UL, 0x094687daUL, 0xe7e932c8UL, ++ 0x828e8e70UL, 0xd49eed28UL, 0xb1f95190UL, 0x5f56e482UL, 0x3a31583aUL, ++ 0x83098fa7UL, 0xe66e331fUL, 0x08c1860dUL, 0x6da63ab5UL, 0xa4e140bdUL, ++ 0xc186fc05UL, 0x2f294917UL, 0x4a4ef5afUL, 0xf3762232UL, 0x96119e8aUL, ++ 0x78be2b98UL, 0x1dd99720UL, 0x4bc9f478UL, 0x2eae48c0UL, 0xc001fdd2UL, ++ 0xa566416aUL, 0x1c5e96f7UL, 0x79392a4fUL, 0x97969f5dUL, 0xf2f123e5UL, ++ 0x05196b4dUL, 0x607ed7f5UL, 0x8ed162e7UL, 0xebb6de5fUL, 0x528e09c2UL, ++ 0x37e9b57aUL, 0xd9460068UL, 0xbc21bcd0UL, 0xea31df88UL, 0x8f566330UL, ++ 0x61f9d622UL, 0x049e6a9aUL, 0xbda6bd07UL, 0xd8c101bfUL, 0x366eb4adUL, ++ 0x53090815UL, 0x9a4e721dUL, 0xff29cea5UL, 0x11867bb7UL, 0x74e1c70fUL, ++ 0xcdd91092UL, 0xa8beac2aUL, 0x46111938UL, 0x2376a580UL, 0x7566c6d8UL, ++ 0x10017a60UL, 0xfeaecf72UL, 0x9bc973caUL, 0x22f1a457UL, 0x479618efUL, ++ 0xa939adfdUL, 0xcc5e1145UL, 0x06ee4d76UL, 0x6389f1ceUL, 0x8d2644dcUL, ++ 0xe841f864UL, 0x51792ff9UL, 0x341e9341UL, 0xdab12653UL, 0xbfd69aebUL, ++ 0xe9c6f9b3UL, 0x8ca1450bUL, 0x620ef019UL, 0x07694ca1UL, 0xbe519b3cUL, ++ 0xdb362784UL, 0x35999296UL, 0x50fe2e2eUL, 0x99b95426UL, 0xfcdee89eUL, ++ 0x12715d8cUL, 0x7716e134UL, 0xce2e36a9UL, 0xab498a11UL, 0x45e63f03UL, ++ 0x208183bbUL, 0x7691e0e3UL, 0x13f65c5bUL, 0xfd59e949UL, 0x983e55f1UL, ++ 0x2106826cUL, 0x44613ed4UL, 0xaace8bc6UL, 0xcfa9377eUL, 0x38417fd6UL, ++ 0x5d26c36eUL, 0xb389767cUL, 0xd6eecac4UL, 0x6fd61d59UL, 0x0ab1a1e1UL, ++ 0xe41e14f3UL, 0x8179a84bUL, 0xd769cb13UL, 0xb20e77abUL, 0x5ca1c2b9UL, ++ 0x39c67e01UL, 0x80fea99cUL, 0xe5991524UL, 0x0b36a036UL, 0x6e511c8eUL, ++ 0xa7166686UL, 0xc271da3eUL, 0x2cde6f2cUL, 0x49b9d394UL, 0xf0810409UL, ++ 0x95e6b8b1UL, 0x7b490da3UL, 0x1e2eb11bUL, 0x483ed243UL, 0x2d596efbUL, ++ 0xc3f6dbe9UL, 0xa6916751UL, 0x1fa9b0ccUL, 0x7ace0c74UL, 0x9461b966UL, ++ 0xf10605deUL ++ } ++}; ++/* ========================================================================= */ ++#define DOLIT4 c ^= *buf4++; \ ++ c = crc_table[3][c & 0xff] ^ crc_table[2][(c >> 8) & 0xff] ^ \ ++ crc_table[1][(c >> 16) & 0xff] ^ crc_table[0][c >> 24] ++#define DOLIT32 DOLIT4; DOLIT4; DOLIT4; DOLIT4; DOLIT4; DOLIT4; DOLIT4; DOLIT4 ++ ++unsigned int SharedRuntime::updateBytesCRC32(unsigned long crc, const unsigned char *buf, unsigned int len) { ++ if (buf == 0) return 0UL; ++ ++ register unsigned int c; ++ register const unsigned int *buf4; ++ c = (unsigned int)crc; ++ c = ~c; ++ while (len && ((ptrdiff_t)buf & 3)) { ++ c = crc_table[0][(c ^ *buf++) & 0xff] ^ (c >> 8); ++ len--; ++ } ++ ++ buf4 = (const unsigned int *) (const void *)buf; ++ while (len >= 32) { ++ DOLIT32; ++ len -= 32; ++ } ++ while (len >= 4) { ++ DOLIT4; ++ len -= 4; ++ } ++ buf = (const unsigned char *)buf4; ++ ++ if (len) do { ++ c = crc_table[0][(c ^ *buf++) & 0xff] ^ (c >> 8); ++ } while (--len); ++ c = ~c; ++ return (unsigned long)c; ++} ++ ++void SharedRuntime::montgomery_multiply(jint *a_ints, jint *b_ints, jint *n_ints, ++ jint len, jlong inv, ++ jint *m_ints) { ++ assert(len % 2 == 0, "array length in montgomery_multiply must be even"); ++ int longwords = len/2; ++ ++ // Make very sure we don't use so much space that the stack might ++ // overflow. 512 jints corresponds to an 16384-bit integer and ++ // will use here a total of 8k bytes of stack space. ++ int total_allocation = longwords * sizeof (unsigned long) * 4; ++ guarantee(total_allocation <= 8192, "must be"); ++ unsigned long *scratch = (unsigned long *)alloca(total_allocation); ++ ++ // Local scratch arrays ++ unsigned long ++ *a = scratch + 0 * longwords, ++ *b = scratch + 1 * longwords, ++ *n = scratch + 2 * longwords, ++ *m = scratch + 3 * longwords; ++ ++ reverse_words((unsigned long *)a_ints, a, longwords); ++ reverse_words((unsigned long *)b_ints, b, longwords); ++ reverse_words((unsigned long *)n_ints, n, longwords); ++ ++ ::montgomery_multiply(a, b, n, m, (unsigned long)inv, longwords); ++ ++ reverse_words(m, (unsigned long *)m_ints, longwords); ++} ++ ++void SharedRuntime::montgomery_square(jint *a_ints, jint *n_ints, ++ jint len, jlong inv, ++ jint *m_ints) { ++ assert(len % 2 == 0, "array length in montgomery_square must be even"); ++ int longwords = len/2; ++ ++ // Make very sure we don't use so much space that the stack might ++ // overflow. 512 jints corresponds to an 16384-bit integer and ++ // will use here a total of 6k bytes of stack space. ++ int total_allocation = longwords * sizeof (unsigned long) * 3; ++ guarantee(total_allocation <= 8192, "must be"); ++ unsigned long *scratch = (unsigned long *)alloca(total_allocation); ++ ++ // Local scratch arrays ++ unsigned long ++ *a = scratch + 0 * longwords, ++ *n = scratch + 1 * longwords, ++ *m = scratch + 2 * longwords; ++ ++ reverse_words((unsigned long *)a_ints, a, longwords); ++ reverse_words((unsigned long *)n_ints, n, longwords); ++ ++ //montgomery_square fails to pass BigIntegerTest on solaris amd64 ++ //on jdk7 and jdk8. ++#ifndef SOLARIS ++ if (len >= MONTGOMERY_SQUARING_THRESHOLD) { ++#else ++ if (0) { ++#endif ++ ::montgomery_square(a, n, m, (unsigned long)inv, longwords); ++ } else { ++ ::montgomery_multiply(a, a, n, m, (unsigned long)inv, longwords); ++ } ++ ++ reverse_words(m, (unsigned long *)m_ints, longwords); ++} ++ ++extern "C" int SpinPause() {return 0;} +diff --git a/hotspot/src/cpu/sw64/vm/stubGenerator_sw64.cpp b/hotspot/src/cpu/sw64/vm/stubGenerator_sw64.cpp +new file mode 100755 +index 0000000000..d7ea9b2dbe +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/stubGenerator_sw64.cpp +@@ -0,0 +1,3894 @@ ++/* ++ * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#include "precompiled.hpp" ++#include "asm/macroAssembler.hpp" ++#include "asm/macroAssembler.inline.hpp" ++#include "interpreter/interpreter.hpp" ++#include "nativeInst_sw64.hpp" ++#include "oops/instanceOop.hpp" ++#include "oops/method.hpp" ++#include "oops/objArrayKlass.hpp" ++#include "oops/oop.inline.hpp" ++#include "prims/methodHandles.hpp" ++#include "runtime/frame.inline.hpp" ++#include "runtime/handles.inline.hpp" ++#include "runtime/sharedRuntime.hpp" ++#include "runtime/stubCodeGenerator.hpp" ++#include "runtime/stubRoutines.hpp" ++#include "runtime/thread.inline.hpp" ++#include "utilities/top.hpp" ++#ifdef COMPILER2 ++#include "opto/runtime.hpp" ++#endif ++ ++// Declaration and definition of StubGenerator (no .hpp file). ++// For a more detailed description of the stub routine structure ++// see the comment in stubRoutines.hpp ++ ++#define __ _masm-> ++#define TIMES_OOP (UseCompressedOops ? Address::times_4 : Address::times_8) ++//#define a__ ((Assembler*)_masm)-> ++ ++#ifdef PRODUCT ++#define BLOCK_COMMENT(str) /* nothing */ ++#else ++#define BLOCK_COMMENT(str) { char line[1024]; sprintf(line,"%s:%s:%d",str,__FILE__, __LINE__); __ block_comment(line);} ++#endif ++ ++#define BIND(label) bind(label); BLOCK_COMMENT(#label ":") ++ ++const int MXCSR_MASK = 0xFFC0; // Mask out any pending exceptions ++ ++// Stub Code definitions ++ ++static address handle_unsafe_access() { ++ JavaThread* thread = JavaThread::current(); ++ address pc = thread->saved_exception_pc(); ++ // pc is the instruction which we must emulate ++ // doing a no-op is fine: return garbage from the load ++ // therefore, compute npc ++ address npc = (address)((unsigned long)pc + sizeof(unsigned int)); ++ ++ // request an async exception ++ thread->set_pending_unsafe_access_error(); ++ ++ // return address of next instruction to execute ++ return npc; ++} ++ ++class StubGenerator: public StubCodeGenerator { ++ private: ++ ++#ifdef PRODUCT ++#define inc_counter_np(counter) ((void)0) ++#else ++ void inc_counter_np_(int& counter) { ++ __ li64(GP, (long )&counter); ++ __ ldw(AT, GP, 0); ++ __ addw(AT, AT, 1); ++ __ stw(AT, GP, 0); ++ } ++#define inc_counter_np(counter) \ ++ BLOCK_COMMENT("inc_counter " #counter); \ ++ inc_counter_np_(counter); ++#endif ++ // ABI sw64 ++ // This fig is not SW64 ABI. It is call Java from C ABI. ++ // Call stubs are used to call Java from C ++ // ++ // [ return_from_Java ] ++ // [ argument word n-1 ] <--- sp ++ // ... ++ // [ argument word 0 ] ++ // ... ++ //-10 [ S2 ] ++ // -9 [ S5 ] ++ // -8 [ S4 ] ++ // -7 [ S3 ] ++ // -6 [ S0 ] ++ // -5 [ TSR(T5err) ] ++ // -4 [ LVP(S1) ] ++ // -3 [ BCP(T10) ] ++ // -2 [ saved fp ] <--- fp_after_call ++ // -1 [ return address ] ++ // 0 [ ptr. to call wrapper ] <--- a0 (old sp -->)fp ++ // 1 [ result ] <--- a1 ++ // 2 [ result_type ] <--- a2 ++ // 3 [ method ] <--- a3 ++ // 4 [ entry_point ] <--- a4 ++ // 5 [ parameters ] <--- a5 ++ // 6 [ parameter_size ] <--- a6 ++ // 7 [ thread ] <--- a7 ++ ++ // ++ // _LP64: n64 does not save paras in sp. ++ // ++ // [ return_from_Java ] ++ // [ argument word n-1 ] <--- sp ++ // ... ++ // [ argument word 0 ] ++ // ... ++ //-14 [ thread ] ++ //-13 [ result_type ] <--- a2 ++ //-12 [ result ] <--- a1 ++ //-11 [ ptr. to call wrapper ] <--- a0 ++ //-10 [ S2 ] ++ // -9 [ S5 ] ++ // -8 [ S4 ] ++ // -7 [ S3 ] ++ // -6 [ S0 ] ++ // -5 [ TSR(T5err) ] ++ // -4 [ LVP(S1) ] ++ // -3 [ BCP(T10) ] ++ // -2 [ saved fp ] <--- fp_after_call ++ // -1 [ return address ] ++ // 0 [ ] <--- old sp ++ ++ // Call stubs are used to call Java from C ++ //SW64 Incoming arguments: ++ // ++ // AR0 : call wrapper address ++ // AR1 : result (address) ++ // AR2 : result type ++ // AR3 : method ++ // AR4 : (interpreter) entry point ++ // AR5 : parameters (address) ++ // [sp + 0x0] : parameter size (in words) ++ // [sp + 0x8] : thread ++ ++ ++ enum call_stub_layout { ++ RA_off = -1, ++ FP_off = -2, ++ S0_off = -3, ++ S1_off = -4, ++ S2_off = -5, ++ S3_off = -6, ++ S4_off = -7, ++ S5_off = -8, ++ F2_off = -9, ++ F3_off = -10, ++ F4_off = -11, ++ F5_off = -12, ++ F6_off = -13, ++ F7_off = -14, ++ F8_off = -15, ++ F9_off = -16, ++ result_off = -17, ++ result_type_off = -18, ++ total_off = result_type_off - 1, ++ }; ++ ++ address generate_call_stub(address& return_address) { ++ ++ StubCodeMark mark(this, "StubRoutines", "call_stub"); ++ address start = __ pc(); ++ const Address parameter_size(FP, BytesPerWord * 2); ++ const Address thread(FP, BytesPerWord * 3); ++ ++ // call Java method from C function, by LIX20170503 ++ if (Usesetfpec1) { ++ __ setfpec1(); ++ } ++ ++ //set FPCR in kernel ++// if (SetFPCR) { ++// __ rfpcr(F28); ++// __ fimovd(AT, F28); ++// __ sbt(AT, 45, AT); ++// __ ifmovd(F28, AT); ++// __ wfpcr(F28); ++//// __ setfpec0(); ++// } ++ ++ // same as in generate_catch_exception()! ++ ++ // stub code ++ // save ra and fp ++ __ add_simm16(SP, SP, total_off * wordSize); ++ // save ra and fp ++ __ stl(RA, SP, (RA_off - total_off) * wordSize); ++ __ stl(FP, SP, (FP_off - total_off) * wordSize); ++ __ stl(S0, SP, (S0_off - total_off) * wordSize); ++ __ stl(S1, SP, (S1_off - total_off) * wordSize); ++ __ stl(S2, SP, (S2_off - total_off) * wordSize); ++ __ stl(S3, SP, (S3_off - total_off) * wordSize); ++ __ stl(S4, SP, (S4_off - total_off) * wordSize); ++ __ stl(S5, SP, (S5_off - total_off) * wordSize); ++ __ stl(A1, SP, (result_off - total_off) * wordSize); ++ __ stl(A2, SP, (result_type_off - total_off) * wordSize); ++ ++ __ fstd(F2, SP, (F2_off - total_off) * wordSize); ++ __ fstd(F3, SP, (F3_off - total_off) * wordSize); ++ __ fstd(F4, SP, (F4_off - total_off) * wordSize); ++ __ fstd(F5, SP, (F5_off - total_off) * wordSize); ++ __ fstd(F6, SP, (F6_off - total_off) * wordSize); ++ __ fstd(F7, SP, (F7_off - total_off) * wordSize); ++ __ fstd(F8, SP, (F8_off - total_off) * wordSize); ++ __ fstd(F9, SP, (F9_off - total_off) * wordSize); ++ ++ ++ // I think 14 is the max gap between argument and callee saved register ++ __ add_simm16(FP, SP, (FP_off - total_off) * wordSize); ++ ++ __ stl(A0, FP, frame::entry_frame_call_wrapper_offset * wordSize); ++ ++ ++ ++ // -9 [ ptr. to call wrapper]<--- a0<----SP ++ // -8 [ result_type ]<--- a2 ++ // -7 [ result ]<--- a1 ++ // -6 [ S5 ] ++ // -5 [ S4 ] ++ // -4 [ S3 ] ++ // -3 [ S2 ] ++ // -2 [ S1 ] ++ // -1 [ S0 ] ++ // -0 [ saved fp ] <--- fp_after_call ++ // 1 [ RA ] ++ // 2 [ parameter size ] <--- old_SP ++ // 3 [ thread ] ++ ++ __ ld_ptr(S2thread, thread); ++ ++ //add for compressedoops ++ __ reinit_heapbase(); ++ ++#ifdef ASSERT ++ // make sure we have no pending exceptions ++ { ++ Label L; ++ __ ldl(AT, S2thread, in_bytes(Thread::pending_exception_offset())); ++ __ beq(AT, L); ++ __ stop("StubRoutines::call_stub: entered with pending exception"); ++ __ BIND(L); ++ } ++#endif ++ ++ // pass parameters if any ++ // A5: parameter ++ // T6 parameter_size ++ // T0: parameter_size_tmp(--) ++ // T2: offset(++) ++ // T3: tmp ++ Label parameters_done; ++ // judge if the parameter_size equals 0 ++ __ ld_ptr(T6, parameter_size); ++ __ beq(T6, parameters_done); ++ __ slll(AT, T6, Interpreter::logStackElementSize); ++ __ subl(SP, SP, AT); ++ __ move(AT, -StackAlignmentInBytes); ++ __ and_reg(SP, SP , AT); ++ // Copy Java parameters in reverse order (receiver last) ++ // Note that the argument order is inverted in the process ++ Label loop; ++ __ move(T0, T6); ++ __ move(T2, R0); ++ __ BIND(loop); ++ ++ // get parameter ++ __ slll(T3, T0, LogBytesPerWord); ++ __ addl(T3, T3, A5); //A5 parameters (address) ++ __ ldl(AT, T3, -wordSize); ++ __ slll(T3, T2, LogBytesPerWord); ++ __ addl(T3, T3, SP); ++ __ stl(AT, T3, Interpreter::expr_offset_in_bytes(0)); ++ __ addl(T2, T2, 1); ++ __ subl(T0, T0, 1); ++ __ bne(T0, loop); ++ // advance to next parameter ++ ++ // call Java function ++ __ BIND(parameters_done); ++ ++ // receiver in V0, methodOop in Rmethod ++ ++ __ move(Rmethod, A3); //A3 method ++ __ move(Rsender, SP); //set sender sp ++ __ Assembler::call(RA, A4, 0);//A4 (interpreter) entry point ++ return_address = __ pc(); ++ ++ Label common_return; ++ __ BIND(common_return); ++ ++ // restore ++ __ add_simm16(SP, FP, 2 * wordSize ); ++ __ ldl(RA, SP, RA_off * wordSize); ++ __ ldl(FP, SP, FP_off * wordSize); ++ __ ldl(S0, SP, S0_off * wordSize); ++ __ ldl(S1, SP, S1_off * wordSize); ++ __ ldl(S2, SP, S2_off * wordSize); ++ __ ldl(S3, SP, S3_off * wordSize); ++ __ ldl(S4, SP, S4_off * wordSize); ++ __ ldl(S5, SP, S5_off * wordSize); ++ __ ldl(A1, SP, result_off * wordSize); ++ __ ldl(A2, SP, result_type_off * wordSize); ++ ++ ++ __ fldd(F2, SP, F2_off * wordSize); ++ __ fldd(F3, SP, F3_off * wordSize); ++ __ fldd(F4, SP, F4_off * wordSize); ++ __ fldd(F5, SP, F5_off * wordSize); ++ __ fldd(F6, SP, F6_off * wordSize); ++ __ fldd(F7, SP, F7_off * wordSize); ++ __ fldd(F8, SP, F8_off * wordSize); ++ __ fldd(F9, SP, F9_off * wordSize); ++ ++ // store result depending on type ++ // (everything that is not T_LONG, T_FLOAT or T_DOUBLE is treated as T_INT) ++ const Register a1_resultAddr = A1; ++ const Register a2_resultType = A2; ++ Label is_long, is_float, is_double, exit; ++ __ add_simm16(T3, a2_resultType, (-1) * T_LONG); ++ __ beq(T3, is_long); ++ __ add_simm16(T3, a2_resultType, (-1) * T_FLOAT); ++ __ beq(T3, is_float); ++ __ add_simm16(T3, a2_resultType, (-1) * T_DOUBLE); ++ __ beq(T3, is_double); ++ ++ // handle T_INT case ++ __ stl(V0, a1_resultAddr, 0 * wordSize); ++ __ BIND(exit); ++ ++ // return ++ __ ret(); ++ ++ // handle return types different from T_INT ++ __ BIND(is_long); ++ __ stl(V0, a1_resultAddr, 0 * wordSize); ++ __ beq(R0, exit); ++ ++ __ BIND(is_float); ++ __ fsts(F0, a1_resultAddr, 0 * wordSize); ++ __ beq(R0, exit); ++ ++ __ BIND(is_double); ++ __ fstd(F0, a1_resultAddr, 0 * wordSize); ++ __ beq(R0, exit); ++ ++ StubRoutines::sw64::set_call_stub_compiled_return(__ pc()); ++ __ beq(R0, common_return); ++ return start; ++ } ++ ++ // Return point for a Java call if there's an exception thrown in ++ // Java code. The exception is caught and transformed into a ++ // pending exception stored in JavaThread that can be tested from ++ // within the VM. ++ // ++ // Note: Usually the parameters are removed by the callee. In case ++ // of an exception crossing an activation frame boundary, that is ++ // not the case if the callee is compiled code => need to setup the ++ // sp. ++ // ++ // V0: exception oop ++ ++ address generate_catch_exception() { ++ StubCodeMark mark(this, "StubRoutines", "catch_exception"); ++ address start = __ pc(); ++ ++ Register thread = S2thread; ++ ++ // get thread directly ++ ++#ifdef ASSERT ++ // verify that threads correspond ++ { Label L; ++ __ get_thread(T11); ++ __ beq(T11, thread, L); ++ __ stop("StubRoutines::catch_exception: threads must correspond"); ++ __ BIND(L); ++ } ++#endif ++ // set pending exception ++ __ verify_oop(V0); ++ __ stl(V0, thread, in_bytes(Thread::pending_exception_offset())); ++ __ li(AT, (long)__FILE__); ++ __ stl(AT, thread, in_bytes(Thread::exception_file_offset ())); ++ __ li(AT, (long)__LINE__); ++ __ stl(AT, thread, in_bytes(Thread::exception_line_offset ())); ++ ++ // complete return to VM ++ assert(StubRoutines::_call_stub_return_address != NULL, "_call_stub_return_address must have been generated before"); ++ __ jmp(StubRoutines::_call_stub_return_address, relocInfo::none); ++ ++ return start; ++ } ++ ++ // Continuation point for runtime calls returning with a pending ++ // exception. The pending exception check happened in the runtime ++ // or native call stub. The pending exception in Thread is ++ // converted into a Java-level exception. ++ // ++ // Contract with Java-level exception handlers: ++ // V0: exception ++ // T4: throwing pc ++ // ++ // NOTE: At entry of this stub, exception-pc must be on stack !! ++ ++ address generate_forward_exception() { ++ StubCodeMark mark(this, "StubRoutines", "forward exception"); ++ Register thread = S2thread; ++ address start = __ pc(); ++ ++ // Upon entry, the sp points to the return address returning into ++ // Java (interpreted or compiled) code; i.e., the return address ++ // throwing pc. ++ // ++ // Arguments pushed before the runtime call are still on the stack ++ // but the exception handler will reset the stack pointer -> ++ // ignore them. A potential result in registers can be ignored as ++ // well. ++ ++#ifdef ASSERT ++ // make sure this code is only executed if there is a pending exception ++ { ++ Label L; ++ __ ldl(AT, thread, in_bytes(Thread::pending_exception_offset())); ++ __ bne(AT, L); ++ __ stop("StubRoutines::forward exception: no pending exception (1)"); ++ __ BIND(L); ++ } ++#endif ++ ++ // compute exception handler into T12 ++ __ ldl(A1, SP, 0); ++ __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::exception_handler_for_return_address), thread, A1); ++ __ move(T12, V0); ++ __ pop(T4); ++ ++ __ ldl(V0, thread, in_bytes(Thread::pending_exception_offset())); ++ __ stl(R0, thread, in_bytes(Thread::pending_exception_offset())); ++ ++#ifdef ASSERT ++ // make sure exception is set ++ { ++ Label L; ++ __ bne(V0, L); ++ __ stop("StubRoutines::forward exception: no pending exception (2)"); ++ __ BIND(L); ++ } ++#endif ++ ++ // continue at exception handler (return address removed) ++ // V0: exception ++ // T12: exception handler ++ // T4: throwing pc ++ __ verify_oop(V0); ++ __ jmp(T12); ++ ++ return start; ++ } ++ ++ // Support for intptr_t get_previous_fp() ++ // ++ // This routine is used to find the previous frame pointer for the ++ // caller (current_frame_guess). This is used as part of debugging ++ // ps() is seemingly lost trying to find frames. ++ // This code assumes that caller current_frame_guess) has a frame. ++ address generate_get_previous_fp() { ++ StubCodeMark mark(this, "StubRoutines", "get_previous_fp"); ++ const Address old_fp (FP, 0); ++ const Address older_fp (V0, 0); ++ address start = __ pc(); ++ __ enter(); ++ __ ldw_signed(V0, old_fp); // callers fp ++ __ ldw_signed(V0, older_fp); // the frame for ps() ++ __ leave(); ++ __ ret(); ++ return start; ++ } ++ ++ // The following routine generates a subroutine to throw an ++ // asynchronous UnknownError when an unsafe access gets a fault that ++ // could not be reasonably prevented by the programmer. (Example: ++ // SIGBUS/OBJERR.) ++ address generate_handler_for_unsafe_access() { ++ StubCodeMark mark(this, "StubRoutines", "handler_for_unsafe_access"); ++ address start = __ pc(); ++ __ pushad_except_RA(); // push registers ++ // Address next_pc(esp, RegisterImpl::number_of_registers * BytesPerWord); ++ __ call(CAST_FROM_FN_PTR(address, handle_unsafe_access), relocInfo::runtime_call_type); ++ __ move(RA,V0); ++ __ popad_except_RA(); ++ __ ret(); ++ return start; ++ } ++ ++ // Non-destructive plausibility checks for oops ++ // ++ address generate_verify_oop() { ++ StubCodeMark mark(this, "StubRoutines", "verify_oop"); ++ address start = __ pc(); ++ __ reinit_heapbase(); ++ __ verify_oop_subroutine(); ++ address end = __ pc(); ++ return start; ++ } ++ ++ // ++ // Generate overlap test for array copy stubs ++ // ++ // Input: ++ // A0 - array1 ++ // A1 - array2 ++ // A2 - element count ++ // ++ ++ // use T12 as temp ++ void array_overlap_test(address no_overlap_target, int log2_elem_size) { ++ int elem_size = 1 << log2_elem_size; ++ Address::ScaleFactor sf = Address::times_1; ++ ++ switch (log2_elem_size) { ++ case 0: sf = Address::times_1; break; ++ case 1: sf = Address::times_2; break; ++ case 2: sf = Address::times_4; break; ++ case 3: sf = Address::times_8; break; ++ } ++ ++ __ slll(AT, A2, sf); ++ __ addl(AT, AT, A0); ++ __ add_simm16(T12, AT, -elem_size); ++ __ subl(AT, A1, A0); ++ __ ble(AT, no_overlap_target); ++ __ subl(AT, A1, T12); ++ __ bgt(AT, no_overlap_target); ++ ++ // If A0 = 0xf... and A1 = 0x0..., than goto no_overlap_target ++ Label L; ++ __ bge(A0, L); ++ __ bgt(A1, no_overlap_target); ++ __ BIND(L); ++ ++ } ++ ++ // ++ // Generate store check for array ++ // ++ // Input: ++ // T0 - starting address ++ // T1 - element count ++ // ++ // The 2 input registers are overwritten ++ // ++ ++//lsp to do check if array_store_check is necessary?? ++ void array_store_check(Register tmp) { ++ assert_different_registers(tmp, AT, T0, T1); ++ BarrierSet* bs = Universe::heap()->barrier_set(); ++ assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind"); ++ CardTableModRefBS* ct = (CardTableModRefBS*)bs; ++ assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); ++ Label l_0; ++ ++ if (UseConcMarkSweepGC) __ memb(); ++ ++ __ set64(tmp, (long)ct->byte_map_base); ++ ++ __ slll(AT, T1, TIMES_OOP); ++ __ addl(AT, T0, AT); ++ __ add_simm16(T1, AT, - BytesPerHeapOop); ++ ++ __ shr(T0, CardTableModRefBS::card_shift); ++ __ shr(T1, CardTableModRefBS::card_shift); ++ ++ __ subl(T1, T1, T0); // end --> cards count ++ __ BIND(l_0); ++ ++ __ addl(AT, tmp, T0); ++ __ addl(AT, AT, T1); ++ __ stb(R0, AT, 0); ++ ++ __ subl(T1, T1, 1); ++ __ bge(T1, l_0); ++ ++ } ++ ++ // Generate code for an array write pre barrier ++ // ++ // addr - starting address ++ // count - element count ++ // tmp - scratch register ++ // ++ // Destroy no registers! ++ // ++ void gen_write_ref_array_pre_barrier(Register addr, Register count, bool dest_uninitialized) { ++ BarrierSet* bs = Universe::heap()->barrier_set(); ++ switch (bs->kind()) { ++ case BarrierSet::G1SATBCT: ++ case BarrierSet::G1SATBCTLogging: ++ // With G1, don't generate the call if we statically know that the target in uninitialized ++ if (!dest_uninitialized) { ++ __ pushad(); // push registers ++ if (count == A0) { ++ if (addr == A1) { ++ // exactly backwards!! ++ //__ xchgptr(c_rarg1, c_rarg0); ++ __ move(AT, A0); ++ __ move(A0, A1); ++ __ move(A1, AT); ++ } else { ++ __ move(A1, count); ++ __ move(A0, addr); ++ } ++ } else { ++ __ move(A0, addr); ++ __ move(A1, count); ++ } ++ __ call_VM_leaf(CAST_FROM_FN_PTR(address, BarrierSet::static_write_ref_array_pre), 2); ++ __ popad(); ++ } ++ break; ++ case BarrierSet::CardTableModRef: ++ case BarrierSet::CardTableExtension: ++ case BarrierSet::ModRef: ++ break; ++ default: ++ ShouldNotReachHere(); ++ ++ } ++ } ++ ++ // ++ // Generate code for an array write post barrier ++ // ++ // Input: ++ // start - register containing starting address of destination array ++ // count - elements count ++ // scratch - scratch register ++ // ++ // The input registers are overwritten. ++ // ++ void gen_write_ref_array_post_barrier(Register start, Register count, Register scratch) { ++ Register tmp1 = GP; ++ assert_different_registers(start, count, scratch, AT); ++ BarrierSet* bs = Universe::heap()->barrier_set(); ++ switch (bs->kind()) { ++ case BarrierSet::G1SATBCT: ++ case BarrierSet::G1SATBCTLogging: ++ { ++ __ pushad(); // push registers (overkill) ++ if (count == A0) { ++ if (start == A1) { ++ // exactly backwards!! ++ //__ xchgptr(c_rarg1, c_rarg0); ++ __ move(AT, A0); ++ __ move(A0, A1); ++ __ move(A1, AT); ++ } else { ++ __ move(A1, count); ++ __ move(A0, start); ++ } ++ } else { ++ __ move(A0, start); ++ __ move(A1, count); ++ } ++ __ call_VM_leaf(CAST_FROM_FN_PTR(address, BarrierSet::static_write_ref_array_post), 2); ++ __ popad(); ++ } ++ break; ++ case BarrierSet::CardTableModRef: ++ case BarrierSet::CardTableExtension: ++ { ++ CardTableModRefBS* ct = (CardTableModRefBS*)bs; ++ assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); ++ ++ Label L_loop; ++ const Register end = count; ++ ++ if (UseConcMarkSweepGC) ++ if(UseWmemb) ++ __ wmemb(); ++ else ++ __ memb(); ++ int64_t disp = (int64_t) ct->byte_map_base; ++ __ set64(scratch, disp); ++ ++ __ lea(end, Address(start, count, TIMES_OOP, 0)); ++ __ add_simm16(end, end, -BytesPerHeapOop); // end - 1 to make inclusive ++ __ shr(start, CardTableModRefBS::card_shift); ++ __ shr(end, CardTableModRefBS::card_shift); ++ __ subl(end, end, start); // end --> cards count ++ ++ __ addl(start, start, scratch); ++ ++ __ BIND(L_loop); ++ __ addl(AT, start, count); ++ __ stb(R0, AT, 0); ++ __ subl(count, count, 1); ++ __ cmplt(AT, count, R0); ++ __ beq(AT, L_loop); ++ } ++ break; ++ default: ++ ShouldNotReachHere(); ++ } ++ } ++ ++ // conjoint large copy ++ // void generate_conjoint_large_copy(Label &entry, const char *name) { ++ void generate_conjoint_large_copy(const char *name) { ++// StubCodeMark mark(this, "StubRoutines", name); ++// __ align(CodeEntryAlignment); ++ ++ { ++ Label loop, le32, le16, le8, lt8; ++ ++ // __ bind(entry); ++ __ addl(A3, A1, A2); ++ __ addl(A2, A0, A2); ++ __ ldl(T6, A0, 0); ++ __ ldl(T7, A2, -8); ++ ++ __ and_imm8(T1, A2, 7); ++ __ subl(A2, A2, T1); ++ __ subl(A5, A3, T1); ++ ++ __ addl(A4, A0, 64); ++ __ bge(A4, A2, le32); ++ ++ __ bind(loop); ++ __ ldl(T0, A2, -8); ++ __ ldl(T1, A2, -16); ++ __ ldl(T2, A2, -24); ++ __ ldl(T3, A2, -32); ++ __ ldl(T4, A2, -40); ++ __ ldl(T5, A2, -48); ++ __ ldl(T6, A2, -56); ++ __ ldl(T7, A2, -64); ++ __ ldi(A2, A2, -64); ++ __ stl(T0, A5, -8); ++ __ stl(T1, A5, -16); ++ __ stl(T2, A5, -24); ++ __ stl(T3, A5, -32); ++ __ stl(T4, A5, -40); ++ __ stl(T5, A5, -48); ++ __ stl(T6, A5, -56); ++ __ stl(T7, A5, -64); ++ __ ldi(A5, A5, -64); ++ __ blt(A4, A2, loop); ++ ++ __ bind(le32); ++ __ ldi(A4, A0, 32); ++ __ bge(A4, A2, le16); ++ __ ldl(T0, A2, -8); ++ __ ldl(T1, A2, -16); ++ __ ldl(T2, A2, -24); ++ __ ldl(T3, A2, -32); ++ __ ldi(A2, A2, -32); ++ __ stl(T0, A5, -8); ++ __ stl(T1, A5, -16); ++ __ stl(T2, A5, -24); ++ __ stl(T3, A5, -32); ++ __ ldi(A5, A5, -32); ++ ++ __ bind(le16); ++ __ ldi(A4, A0, 16); ++ __ bge(A4, A2, le8); ++ __ ldl(T0, A2, -8); ++ __ ldl(T1, A2, -16); ++ __ ldi(A2, A2, -16); ++ __ stl(T0, A5, -8); ++ __ stl(T1, A5, -16); ++ __ ldi(A5, A5, -16); ++ ++ __ bind(le8); ++ __ ldi(A4, A0, 8); ++ __ bge(A4, A2, lt8); ++ __ ldl(T0, A2, -8); ++ __ stl(T0, A5, -8); ++ ++ __ bind(lt8); ++ __ stl(T6, A1, 0); ++ __ stl(T7, A3, -8); ++ } ++ ++// __ ret(); ++ } ++ // conjoint large copy lasx ++ // void generate_conjoint_large_copy_simd(Label &entry, const char *name) { ++ void generate_conjoint_large_copy_simd( const char *name) { ++// StubCodeMark mark(this, "StubRoutines", name); ++// __ align(CodeEntryAlignment); ++ ++ { ++ Label loop, le128, le64, le32, lt32; ++ //__ bind(entry); ++ __ addl(A3, A1, A2); ++ __ addl(A2, A0, A2); ++ __ vldd(F20, A0, 0); ++ __ vldd(F21, A2, -32); ++ ++ __ and_imm8(T1, A2, 31); ++ __ subl(A2, A2, T1); ++ __ subl(A5, A3, T1); ++ ++ __ ldi(A4, A0, 256); ++ __ bge(A4, A2, le128); ++ ++ __ bind(loop); ++ __ vldd(F10, A2, -32); ++ __ vldd(F11, A2, -64); ++ __ vldd(F12, A2, -96); ++ __ vldd(F13, A2, -128); ++ __ vldd(F14, A2, -160); ++ __ vldd(F15, A2, -192); ++ __ vldd(F16, A2, -224); ++ __ vldd(F17, A2, -256); ++ __ ldi(A2, A2, -256); ++ __ vstd(F10, A5, -32); ++ __ vstd(F11, A5, -64); ++ __ vstd(F12, A5, -96); ++ __ vstd(F13, A5, -128); ++ __ vstd(F14, A5, -160); ++ __ vstd(F15, A5, -192); ++ __ vstd(F16, A5, -224); ++ __ vstd(F17, A5, -256); ++ __ ldi(A5, A5, -256); ++ __ blt(A4, A2, loop); ++ ++ __ bind(le128); ++ __ ldi(A4, A0, 128); ++ __ bge(A4, A2, le64); ++ __ vldd(F10, A2, -32); ++ __ vldd(F11, A2, -64); ++ __ vldd(F12, A2, -96); ++ __ vldd(F13, A2, -128); ++ __ ldi(A2, A2, -128); ++ __ vstd(F10, A5, -32); ++ __ vstd(F11, A5, -64); ++ __ vstd(F12, A5, -96); ++ __ vstd(F13, A5, -128); ++ __ ldi(A5, A5, -128); ++ ++ __ bind(le64); ++ __ ldi(A4, A0, 64); ++ __ bge(A4, A2, le32); ++ __ vldd(F10, A2, -32); ++ __ vldd(F11, A2, -64); ++ __ ldi(A2, A2, -64); ++ __ vstd(F10, A5, -32); ++ __ vstd(F11, A5, -64); ++ __ ldi(A5, A5, -64); ++ ++ __ bind(le32); ++ __ ldi(A4, A0, 32); ++ __ bge(A4, A2, lt32); ++ __ vldd(F10, A2, -32); ++ __ vstd(F10, A5, -32); ++ ++ __ bind(lt32); ++ __ vstd(F20, A1, 0); ++ __ vstd(F21, A3, -32); ++ } ++ ++ //__ ret(); ++ } ++ void array_overlap_test2(address no_overlap_target, int log2_elem_size) { ++ __ slll(T4, A2, log2_elem_size); ++ __ subl(AT, A1, A0); ++ __ bge(AT, T4, no_overlap_target); ++ } ++ // disjoint large copy ++ //void generate_disjoint_large_copy(Label &entry, const char *name) { ++ void generate_disjoint_large_copy(const char *name) { ++// StubCodeMark mark(this, "StubRoutines", name); ++// __ align(CodeEntryAlignment); ++ ++ { ++ Label loop, le32, le16, le8, lt8; ++ ++// __ BIND(entry); ++ __ addl(A3, A1, A2); ++ __ addl(A2, A0, A2); ++ __ ldl(T6, A0, 0); ++ __ ldl(T7, A2, -8); ++ ++ __ and_imm8(T1, A0, 7); ++ __ subl(T0, R0, T1); ++ __ addl(T0, T0, 8); ++ ++ __ addl(A0, A0, T0); ++ __ addl(A5, A1, T0); ++ ++ __ subl(A4, A2, 64); ++ __ bge(A0, A4, le32); ++ ++ __ BIND(loop); ++ __ ldl(T0, A0, 0); ++ __ ldl(T1, A0, 8); ++ __ ldl(T2, A0, 16); ++ __ ldl(T3, A0, 24); ++ __ ldl(T4, A0, 32); ++ __ ldl(T5, A0, 40); ++ __ ldl(T6, A0, 48); ++ __ ldl(T7, A0, 56); ++ __ addl(A0, A0, 64); ++ __ stl(T0, A5, 0); ++ __ stl(T1, A5, 8); ++ __ stl(T2, A5, 16); ++ __ stl(T3, A5, 24); ++ __ stl(T4, A5, 32); ++ __ stl(T5, A5, 40); ++ __ stl(T6, A5, 48); ++ __ stl(T7, A5, 56); ++ __ addl(A5, A5, 64); ++ __ blt(A0, A4, loop); ++ ++ __ BIND(le32); ++ __ subl(A4, A2, 32); ++ __ bge(A0, A4, le16); ++ __ ldl(T0, A0, 0); ++ __ ldl(T1, A0, 8); ++ __ ldl(T2, A0, 16); ++ __ ldl(T3, A0, 24); ++ __ addl(A0, A0, 32); ++ __ stl(T0, A5, 0); ++ __ stl(T1, A5, 8); ++ __ stl(T2, A5, 16); ++ __ stl(T3, A5, 24); ++ __ addl(A5, A5, 32); ++ ++ __ BIND(le16); ++ __ subl(A4, A2, 16); ++ __ bge(A0, A4, le8); ++ __ ldl(T0, A0, 0); ++ __ ldl(T1, A0, 8); ++ __ addl(A0, A0, 16); ++ __ stl(T0, A5, 0); ++ __ stl(T1, A5, 8); ++ __ addl(A5, A5, 16); ++ ++ __ BIND(le8); ++ __ subl(A4, A2, 8); ++ __ bge(A0, A4, lt8); ++ __ ldl(T0, A0, 0); ++ __ stl(T0, A5, 0); ++ ++ __ BIND(lt8); ++ __ stl(T6, A1, 0); ++ __ stl(T7, A3, -8); ++ } ++// __ ret(); ++ } ++ ++ // disjoint large copy lasx ++// void generate_disjoint_large_copy_simd(Label &entry, const char *name) { ++ void generate_disjoint_large_copy_simd( const char *name) { ++// StubCodeMark mark(this, "StubRoutines", name); ++// __ align(CodeEntryAlignment); ++ ++ { ++ Label loop, le128, le64, le32, lt32; ++ ++ // __ BIND(entry); ++ __ addl(A3, A1, A2); ++ __ addl(A2, A0, A2); ++ __ vldd(F20, A0, 0); ++ __ vldd(F21, A2, -32); ++ ++ __ and_imm8(T1, A0, 31); ++ __ subl(T0, R0, T1); ++ __ addl(T0, T0, 32); ++ ++ __ addl(A0, A0, T0); ++ __ addl(A5, A1, T0); ++ ++ __ ldi(A4, A2, -256); ++ __ bge(A0, A4, le128); ++ ++ __ BIND(loop); ++ __ vldd(F10, A0, 0); ++ __ vldd(F11, A0, 32); ++ __ vldd(F12, A0, 64); ++ __ vldd(F13, A0, 96); ++ __ vldd(F14, A0, 128); ++ __ vldd(F15, A0, 160); ++ __ vldd(F16, A0, 192); ++ __ vldd(F17, A0, 224); ++ __ ldi(A0, A0, 256); ++ __ vstd(F10, A5, 0); ++ __ vstd(F11, A5, 32); ++ __ vstd(F12, A5, 64); ++ __ vstd(F13, A5, 96); ++ __ vstd(F14, A5, 128); ++ __ vstd(F15, A5, 160); ++ __ vstd(F16, A5, 192); ++ __ vstd(F17, A5, 224); ++ __ ldi(A5, A5, 256); ++ __ blt( A0, A4, loop); ++ ++ __ BIND(le128); ++ __ ldi(A4, A2, -128); ++ __ bge(A0, A4, le64); ++ __ vldd(F10, A0, 0); ++ __ vldd(F11, A0, 32); ++ __ vldd(F12, A0, 64); ++ __ vldd(F13, A0, 96); ++ __ ldi(A0, A0, 128); ++ __ vstd(F10, A5, 0); ++ __ vstd(F11, A5, 32); ++ __ vstd(F12, A5, 64); ++ __ vstd(F13, A5, 96); ++ __ ldi(A5, A5, 128); ++ ++ __ BIND(le64); ++ __ ldi(A4, A2, -64); ++ __ bge(A0, A4, le32); ++ __ vldd(F10, A0, 0); ++ __ vldd(F11, A0, 32); ++ __ ldi(A0, A0, 64); ++ __ vstd(F10, A5, 0); ++ __ vstd(F11, A5, 32); ++ __ ldi(A5, A5, 64); ++ ++ __ BIND(le32); ++ __ ldi(A4, A2, -32); ++ __ bge(A0, A4, lt32); ++ __ vldd(F10, A0, 0); ++ __ vstd(F10, A5, 0); ++ ++ __ BIND(lt32); ++ __ vstd(F20, A1, 0); ++ __ vstd(F21, A3, -32); ++ } ++// __ ret(); ++ } ++ void generate_byte_small_copy(Label &entry, const char *name) { ++ StubCodeMark mark(this, "StubRoutines", name); ++ __ align(CodeEntryAlignment); ++ __ BIND(entry); ++ __ br(AT, 0); ++ __ addl(AT, AT, 16);//__ addpi(3, AT) ++ __ slll(A2, A2, 6); ++ __ addl(AT, AT, A2); ++ __ jmp(AT); ++ ++ // 0: ++ __ ret(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ ++ // 1: ++ __ ldbu(AT, A0, 0); ++ __ stb(AT, A1, 0); ++ __ ret(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ ++ // 2: ++ __ ldhu(AT, A0, 0); ++ __ sth(AT, A1, 0); ++ __ ret(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ ++ // 3: ++ __ ldhu(AT, A0, 0); ++ __ ldbu(T0, A0, 2); ++ __ sth(AT, A1, 0); ++ __ stb(T0, A1, 2); ++ __ ret(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ ++ // 4: ++ __ ldw(AT, A0, 0); ++ __ stw(AT, A1, 0); ++ __ ret(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ ++ // 5: ++ __ ldw(AT, A0, 0); ++ __ ldbu(T2, A0, 4); ++ __ stw(AT, A1, 0); ++ __ stb(T2, A1, 4); ++ __ ret(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ ++ // 6: ++ __ ldw(AT, A0, 0); ++ __ ldhu(T2, A0, 4); ++ __ stw(AT, A1, 0); ++ __ sth(T2, A1, 4); ++ __ ret(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ ++ // 7: ++ __ ldw(AT, A0, 0); ++ __ ldw(A2, A0, 3); ++ __ stw(AT, A1, 0); ++ __ stw(A2, A1, 3); ++ __ ret(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ ++ // 8: ++ __ ldl(AT, A0, 0); ++ __ stl(AT, A1, 0); ++ __ ret(); ++// if (!UseUnaligned) ++// return; ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ ++ // 9: ++ __ ldl(AT, A0, 0); ++ __ ldbu(A2, A0, 8); ++ __ stl(AT, A1, 0); ++ __ stb(A2, A1, 8); ++ __ ret(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ ++ // 10: ++ __ ldl(AT, A0, 0); ++ __ ldhu(A2, A0, 8); ++ __ stl(AT, A1, 0); ++ __ sth(A2, A1, 8); ++ __ ret(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ ++ // 11: ++ __ ldl(AT, A0, 0); ++ __ ldw(A2, A0, 7); ++ __ stl(AT, A1, 0); ++ __ stw(A2, A1, 7); ++ __ ret(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ ++ // 12: ++ __ ldl(AT, A0, 0); ++ __ ldw(A2, A0, 8); ++ __ stl(AT, A1, 0); ++ __ stw(A2, A1, 8); ++ __ ret(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ ++ // 13: ++ __ ldl(AT, A0, 0); ++ __ ldl(A2, A0, 5); ++ __ stl(AT, A1, 0); ++ __ stl(A2, A1, 5); ++ __ ret(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ ++ // 14: ++ __ ldl(AT, A0, 0); ++ __ ldl(A2, A0, 6); ++ __ stl(AT, A1, 0); ++ __ stl(A2, A1, 6); ++ __ ret(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ ++ // 15: ++ __ ldl(AT, A0, 0); ++ __ ldl(A2, A0, 7); ++ __ stl(AT, A1, 0); ++ __ stl(A2, A1, 7); ++ __ ret(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ ++ // 16: ++ __ ldl(AT, A0, 0); ++ __ ldl(A2, A0, 8); ++ __ stl(AT, A1, 0); ++ __ stl(A2, A1, 8); ++ __ ret(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ ++ ++ // 17: ++ __ ldl(AT, A0, 0); ++ __ ldl(A2, A0, 8); ++ __ ldbu(A3, A0, 16); ++ __ stl(AT, A1, 0); ++ __ stl(A2, A1, 8); ++ __ stb(A3, A1, 16); ++ __ ret(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ ++ // 18: ++ __ ldl(AT, A0, 0); ++ __ ldl(A2, A0, 8); ++ __ ldhu(A3, A0, 16); ++ __ stl(AT, A1, 0); ++ __ stl(A2, A1, 8); ++ __ sth(A3, A1, 16); ++ __ ret(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ ++ // 19: ++ __ ldl(AT, A0, 0); ++ __ ldl(A2, A0, 8); ++ __ ldw(A3, A0, 15); ++ __ stl(AT, A1, 0); ++ __ stl(A2, A1, 8); ++ __ stw(A3, A1, 15); ++ __ ret(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ ++ // 20: ++ __ ldl(AT, A0, 0); ++ __ ldl(A2, A0, 8); ++ __ ldw(A3, A0, 16); ++ __ stl(AT, A1, 0); ++ __ stl(A2, A1, 8); ++ __ stw(A3, A1, 16); ++ __ ret(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ ++ // 21: ++ __ ldl(AT, A0, 0); ++ __ ldl(A2, A0, 8); ++ __ ldl(A3, A0, 13); ++ __ stl(AT, A1, 0); ++ __ stl(A2, A1, 8); ++ __ stl(A3, A1, 13); ++ __ ret(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ ++ // 22: ++ __ ldl(AT, A0, 0); ++ __ ldl(A2, A0, 8); ++ __ ldl(A3, A0, 14); ++ __ stl(AT, A1, 0); ++ __ stl(A2, A1, 8); ++ __ stl(A3, A1, 14); ++ __ ret(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ ++ // 23: ++ __ ldl(AT, A0, 0); ++ __ ldl(A2, A0, 8); ++ __ ldl(A3, A0, 15); ++ __ stl(AT, A1, 0); ++ __ stl(A2, A1, 8); ++ __ stl(A3, A1, 15); ++ __ ret(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ ++ // 24: ++ __ ldl(AT, A0, 0); ++ __ ldl(A2, A0, 8); ++ __ ldl(A3, A0, 16); ++ __ stl(AT, A1, 0); ++ __ stl(A2, A1, 8); ++ __ stl(A3, A1, 16); ++ __ ret(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ ++ // 25: ++ __ ldl(AT, A0, 0); ++ __ ldl(A2, A0, 8); ++ __ ldl(A3, A0, 16); ++ __ ldbu(A4, A0, 24); ++ __ stl(AT, A1, 0); ++ __ stl(A2, A1, 8); ++ __ stl(A3, A1, 16); ++ __ stb(A4, A1, 24); ++ __ ret(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ ++ // 26: ++ __ ldl(AT, A0, 0); ++ __ ldl(A2, A0, 8); ++ __ ldl(A3, A0, 16); ++ __ ldhu(A4, A0, 24); ++ __ stl(AT, A1, 0); ++ __ stl(A2, A1, 8); ++ __ stl(A3, A1, 16); ++ __ sth(A4, A1, 24); ++ __ ret(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ ++ // 27: ++ __ ldl(AT, A0, 0); ++ __ ldl(A2, A0, 8); ++ __ ldl(A3, A0, 16); ++ __ ldw(A4, A0, 23); ++ __ stl(AT, A1, 0); ++ __ stl(A2, A1, 8); ++ __ stl(A3, A1, 16); ++ __ stw(A4, A1, 23); ++ __ ret(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ ++ // 28: ++ __ ldl(AT, A0, 0); ++ __ ldl(A2, A0, 8); ++ __ ldl(A3, A0, 16); ++ __ ldw(A4, A0, 24); ++ __ stl(AT, A1, 0); ++ __ stl(A2, A1, 8); ++ __ stl(A3, A1, 16); ++ __ stw(A4, A1, 24); ++ __ ret(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ ++ // 29: ++ __ ldl(AT, A0, 0); ++ __ ldl(A2, A0, 8); ++ __ ldl(A3, A0, 16); ++ __ ldl(A4, A0, 21); ++ __ stl(AT, A1, 0); ++ __ stl(A2, A1, 8); ++ __ stl(A3, A1, 16); ++ __ stl(A4, A1, 21); ++ __ ret(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ // 30: ++ __ ldl(AT, A0, 0); ++ __ ldl(A2, A0, 8); ++ __ ldl(A3, A0, 16); ++ __ ldl(A4, A0, 22); ++ __ stl(AT, A1, 0); ++ __ stl(A2, A1, 8); ++ __ stl(A3, A1, 16); ++ __ stl(A4, A1, 22); ++ __ ret(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ ++ // 31: ++ __ ldl(AT, A0, 0); ++ __ ldl(A2, A0, 8); ++ __ ldl(A3, A0, 16); ++ __ ldl(A4, A0, 23); ++ __ stl(AT, A1, 0); ++ __ stl(A2, A1, 8); ++ __ stl(A3, A1, 16); ++ __ stl(A4, A1, 23); ++ __ ret(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ ++ // 32: ++ __ ldl(AT, A0, 0); ++ __ ldl(A2, A0, 8); ++ __ ldl(A3, A0, 16); ++ __ ldl(A4, A0, 24); ++ __ stl(AT, A1, 0); ++ __ stl(A2, A1, 8); ++ __ stl(A3, A1, 16); ++ __ stl(A4, A1, 24); ++ __ ret(); ++ ++ } ++ ++ // Short small copy: less than { int:9, lsx:9, lasx:17 } elements. ++ void generate_short_small_copy(Label &entry, const char *name) { ++ StubCodeMark mark(this, "StubRoutines", name); ++ __ align(CodeEntryAlignment); ++ Label L; ++ __ BIND(entry); ++ __ br(AT, 0); ++ __ addl(AT, AT, 16);//__ addpi(3, AT) ++ __ slll(A2, A2, 6); ++ __ addl(AT, AT, A2); ++ __ jmp(AT); ++ ++ __ BIND(L); ++ // 0: ++ __ ret(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ ++ // 1: ++ __ ldhu(AT, A0, 0); ++ __ sth(AT, A1, 0); ++ __ ret(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ ++ // 2: ++ __ ldw(AT, A0, 0); ++ __ stw(AT, A1, 0); ++ __ ret(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ ++ // 3: ++ __ ldw(AT, A0, 0); ++ __ ldhu(A2, A0, 4); ++ __ stw(AT, A1, 0); ++ __ sth(A2, A1, 4); ++ __ ret(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ ++ // 4: ++ __ ldl(AT, A0, 0); ++ __ stl(AT, A1, 0); ++ __ ret(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ ++ // 5: ++ __ ldl(AT, A0, 0); ++ __ ldhu(A2, A0, 8); ++ __ stl(AT, A1, 0); ++ __ sth(A2, A1, 8); ++ __ ret(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ ++ // 6: ++ __ ldl(AT, A0, 0); ++ __ ldw(A2, A0, 8); ++ __ stl(AT, A1, 0); ++ __ stw(A2, A1, 8); ++ __ ret(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ ++ // 7: ++ __ ldl(AT, A0, 0); ++ __ ldl(A2, A0, 6); ++ __ stl(AT, A1, 0); ++ __ stl(A2, A1, 6); ++ __ ret(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ ++ // 8: ++ __ ldl(AT, A0, 0); ++ __ ldl(A2, A0, 8); ++ __ stl(AT, A1, 0); ++ __ stl(A2, A1, 8); ++ __ ret(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ ++ // 9: ++ __ ldl(AT, A0, 0); ++ __ ldl(A2, A0, 8); ++ __ ldhu(A3, A0, 16); ++ __ stl(AT, A1, 0); ++ __ stl(A2, A1, 8); ++ __ sth(A3, A1, 16); ++ __ ret(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ ++ // 10: ++ __ ldl(AT, A0, 0); ++ __ ldl(A2, A0, 8); ++ __ ldw(A3, A0, 16); ++ __ stl(AT, A1, 0); ++ __ stl(A2, A1, 8); ++ __ stw(A3, A1, 16); ++ __ ret(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ ++ // 11: ++ __ ldl(AT, A0, 0); ++ __ ldl(A2, A0, 8); ++ __ ldl(A3, A0, 14); ++ __ stl(AT, A1, 0); ++ __ stl(A2, A1, 8); ++ __ stl(A3, A1, 14); ++ __ ret(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ ++ // 12: ++ __ ldl(AT, A0, 0); ++ __ ldl(A2, A0, 8); ++ __ ldl(A3, A0, 16); ++ __ stl(AT, A1, 0); ++ __ stl(A2, A1, 8); ++ __ stl(A3, A1, 16); ++ __ ret(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ ++ // 13: ++ __ ldl(AT, A0, 0); ++ __ ldl(A2, A0, 8); ++ __ ldl(A3, A0, 16); ++ __ ldhu(A4, A0, 24); ++ __ stl(AT, A1, 0); ++ __ stl(A2, A1, 8); ++ __ stl(A3, A1, 16); ++ __ sth(A4, A1, 24); ++ __ ret(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ ++ // 14: ++ __ ldl(AT, A0, 0); ++ __ ldl(A2, A0, 8); ++ __ ldl(A3, A0, 16); ++ __ ldw(A4, A0, 24); ++ __ stl(AT, A1, 0); ++ __ stl(A2, A1, 8); ++ __ stl(A3, A1, 16); ++ __ stw(A4, A1, 24); ++ __ ret(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ ++ // 15: ++ __ ldl(AT, A0, 0); ++ __ ldl(A2, A0, 8); ++ __ ldl(A3, A0, 16); ++ __ ldl(A4, A0, 22); ++ __ stl(AT, A1, 0); ++ __ stl(A2, A1, 8); ++ __ stl(A3, A1, 16); ++ __ stl(A4, A1, 22); ++ __ ret(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ ++ // 16: ++ __ ldl(AT, A0, 0); ++ __ ldl(A2, A0, 8); ++ __ ldl(A3, A0, 16); ++ __ ldl(A4, A0, 24); ++ __ stl(AT, A1, 0); ++ __ stl(A2, A1, 8); ++ __ stl(A3, A1, 16); ++ __ stl(A4, A1, 24); ++ __ ret(); ++ } ++// Int small copy: less than { int:7, lsx:7, lasx:9 } elements. ++ void generate_int_small_copy(Label &entry, const char *name) { ++ StubCodeMark mark(this, "StubRoutines", name); ++ __ align(CodeEntryAlignment); ++ ++ Label L; ++ __ BIND(entry); ++ __ br(AT, 0); ++ __ addl(AT, AT, 16);//__ addpi(3, AT) ++ __ slll(A2, A2, 6); ++ __ addl(AT, AT, A2); ++ __ jmp(AT); ++ ++ ++ __ BIND(L); ++ // 0: ++ __ ret(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ ++ // 1: ++ __ ldw(AT, A0, 0); ++ __ stw(AT, A1, 0); ++ __ ret(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ ++ // 2: ++ __ ldl(AT, A0, 0); ++ __ stl(AT, A1, 0); ++ __ ret(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ ++ // 3: ++ __ ldl(AT, A0, 0); ++ __ ldw(A2, A0, 8); ++ __ stl(AT, A1, 0); ++ __ stw(A2, A1, 8); ++ __ ret(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ ++ // 4: ++ __ ldl(AT, A0, 0); ++ __ ldl(A2, A0, 8); ++ __ stl(AT, A1, 0); ++ __ stl(A2, A1, 8); ++ __ ret(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ ++ // 5: ++ __ ldl(AT, A0, 0); ++ __ ldl(A2, A0, 8); ++ __ ldw(A3, A0, 16); ++ __ stl(AT, A1, 0); ++ __ stl(A2, A1, 8); ++ __ stw(A3, A1, 16); ++ __ ret(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ ++ // 6: ++ __ ldl(AT, A0, 0); ++ __ ldl(A2, A0, 8); ++ __ ldl(A3, A0, 16); ++ __ stl(AT, A1, 0); ++ __ stl(A2, A1, 8); ++ __ stl(A3, A1, 16); ++ __ ret(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ ++ // 7: ++ __ ldl(AT, A0, 0); ++ __ ldl(A2, A0, 8); ++ __ ldl(A3, A0, 16); ++ __ ldw(A4, A0, 24); ++ __ stl(AT, A1, 0); ++ __ stl(A2, A1, 8); ++ __ stl(A3, A1, 16); ++ __ stw(A4, A1, 24); ++ __ ret(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ ++ // 8: ++ __ vldd(F10, A0, 0); ++ __ vstd(F10, A1, 0); ++ __ ret(); ++ } ++ ++ // Long small copy: less than { int:4, lsx:4, lasx:5 } elements. ++ void generate_long_small_copy(Label &entry, const char *name) { ++ StubCodeMark mark(this, "StubRoutines", name); ++ __ align(CodeEntryAlignment); ++ ++// Label L; ++ __ BIND(entry); ++ __ br(AT, 0); ++ __ addl(AT, AT, 16);//__ addpi(3, AT) ++ __ slll(A2, A2, 5); ++ __ addl(AT, AT, A2); ++ __ jmp(AT); ++ ++// __ BIND(L); ++ // 0: ++ __ ret(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ ++ // 1: ++ __ ldl(AT, A0, 0); ++ __ stl(AT, A1, 0); ++ __ ret(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ ++ // 2: ++ __ ldl(AT, A0, 0); ++ __ ldl(A2, A0, 8); ++ __ stl(AT, A1, 0); ++ __ stl(A2, A1, 8); ++ __ ret(); ++ __ nop(); ++ __ nop(); ++ __ nop(); ++ ++ // 3: ++ __ ldl(AT, A0, 0); ++ __ ldl(A2, A0, 8); ++ __ ldl(A3, A0, 16); ++ __ stl(AT, A1, 0); ++ __ stl(A2, A1, 8); ++ __ stl(A3, A1, 16); ++ __ ret(); ++ __ nop(); ++ ++ // 4: ++ __ vldd(F10, A0, 0); ++ __ vstd(F10, A1, 0); ++ __ ret(); ++ } ++ // Arguments: ++ // aligned - true => Input and output aligned on a HeapWord == 8-byte boundary ++ // ignored ++ // name - stub name string ++ // ++ // Inputs: ++ // c_rarg0 - source array address ++ // c_rarg1 - destination array address ++ // c_rarg2 - element count, treated as ssize_t, can be zero ++ // ++ // If 'from' and/or 'to' are aligned on 4-, 2-, or 1-byte boundaries, ++ // we let the hardware handle it. The one to eight bytes within words, ++ // dwords or qwords that span cache line boundaries will still be loaded ++ // and stored atomically. ++ // ++ // Side Effects: ++ // disjoint_byte_copy_entry is set to the no-overlap entry point ++ // used by generate_conjoint_byte_copy(). ++ // ++ address generate_disjoint_byte_copy(bool aligned, Label &small, Label &large, ++ Label &large_aligned, const char * name) { ++ StubCodeMark mark(this, "StubRoutines", name); ++ __ align(CodeEntryAlignment); ++ address start = __ pc(); ++ ++ __ cmplt(T0, A2, 33); ++ __ bne(T0, small); ++ ++ generate_disjoint_large_copy_simd("StubRoutines generate_disjoint_byte_copy"); ++ __ ret(); ++ return start; ++ } ++ ++ address generate_disjoint_short_copy(bool aligned, Label &small, Label &large, ++ Label &large_aligned, const char * name) { ++ StubCodeMark mark(this, "StubRoutines", name); ++ __ align(CodeEntryAlignment); ++ address start = __ pc(); ++ ++ __ cmpult(T0, A2, 17); ++ __ bne(T0, small); ++ ++ __ slll(A2, A2, 1); ++ generate_disjoint_large_copy_simd("StubRoutines generate_disjoint_short_copy"); ++ __ ret(); ++ return start; ++ } ++// Arguments: ++ // aligned - true => Input and output aligned on a HeapWord == 8-byte boundary ++ // ignored ++ // name - stub name string ++ // ++ // Inputs: ++ // A0 - source array address ++ // A1 - destination array address ++ // A2 - element count, treated as ssize_t, can be zero ++ // ++ // If 'from' and/or 'to' are aligned on 4-, 2-, or 1-byte boundaries, ++ // we let the hardware handle it. The one to eight bytes within words, ++ // dwords or qwords that span cache line boundaries will still be loaded ++ // and stored atomically. ++ // ++ address generate_conjoint_byte_copy(bool aligned, Label &small, Label &large, ++ Label &large_aligned, const char *name) { ++ StubCodeMark mark(this, "StubRoutines", name); ++ __ align(CodeEntryAlignment); ++ address start = __ pc(); ++ ++ array_overlap_test2(StubRoutines::jbyte_disjoint_arraycopy(), 0); ++ ++ ++ __ cmpult(T0, A2, 33); ++ __ bne(T0, small); ++ ++ generate_conjoint_large_copy_simd("StubRoutines generate_disjoint_short_copy"); ++ __ ret(); ++ ++ return start; ++ } ++ // Arguments: ++ // aligned - true => Input and output aligned on a HeapWord == 8-byte boundary ++ // ignored ++ // name - stub name string ++ // ++ // Inputs: ++ // A0 - source array address ++ // A1 - destination array address ++ // A2 - element count, treated as ssize_t, can be zero ++ // ++ // If 'from' and/or 'to' are aligned on 4-, 2-, or 1-byte boundaries, ++ // we let the hardware handle it. The one to eight bytes within words, ++ // dwords or qwords that span cache line boundaries will still be loaded ++ // and stored atomically. ++ // ++ // Side Effects: ++ // disjoint_short_copy_entry is set to the no-overlap entry point ++ // used by generate_conjoint_short_copy(). ++ // ++ address generate_conjoint_short_copy(bool aligned, Label &small, Label &large, ++ Label &large_aligned, const char * name) { ++ StubCodeMark mark(this, "StubRoutines", name); ++ __ align(CodeEntryAlignment); ++ address start = __ pc(); ++ array_overlap_test2(StubRoutines::jshort_disjoint_arraycopy(), 1); ++ __ cmpult(T0, A2, 17); ++ __ bne(T0, small); ++ ++ __ slll(A2, A2, 1); ++ generate_conjoint_large_copy_simd("StubRoutines generate_conjoint_short_copy"); ++ __ ret(); ++ return start; ++ } ++ ++ // Arguments: ++ // aligned - true => Input and output aligned on a HeapWord == 8-byte boundary ++ // ignored ++ // name - stub name string ++ // ++ // Inputs: ++ // c_rarg0 - source array address ++ // c_rarg1 - destination array address ++ // c_rarg2 - element count, treated as ssize_t, can be zero ++ // ++ // If 'from' and/or 'to' are aligned on 4-, 2-, or 1-byte boundaries, ++ // we let the hardware handle it. The one to eight bytes within words, ++ // dwords or qwords that span cache line boundaries will still be loaded ++ // and stored atomically. ++ // ++ // Side Effects: ++ // disjoint_byte_copy_entry is set to the no-overlap entry point ++ // used by generate_conjoint_byte_copy(). ++ // ++ address generate_disjoint_byte_copy(bool aligned, const char * name) { ++ StubCodeMark mark(this, "StubRoutines", name); ++ __ align(CodeEntryAlignment); ++ ++ Register src = T0; ++ Register dst = T1; ++ Register count = T3; ++ Register tmp1 = AT; ++ Register tmp2 = GP; ++ ++ address start = __ pc(); ++ ++ __ move(src, A0); ++ __ move(dst, A1); ++ __ move(count, A2); ++ ++ ++ Label l_align_dst, l_align_src, l_tail_bytes, l_end, l_tail; ++ ++ if(UseSimdForward){ ++ __ beq(count, l_end); ++ ++ __ cmple(tmp1, count, 63); ++ __ bne(tmp1, l_tail_bytes); //when count <= 63, don't use simd ++ ++ __ BIND(l_align_dst); ++ __ and_imm8(tmp1, dst, 31); //is dst 0mod32? ++ __ beq(tmp1, l_align_src); ++ ++ __ ldbu(tmp1, src, 0); //grab 1 byte at a time, until dst is 0mod32 ++ __ stb(tmp1, dst, 0); ++ __ subl(count, count, 1); ++ __ addl(dst, dst, 1); ++ __ addl(src, src, 1); ++ __ beq(R0, l_align_dst); ++ ++ __ BIND(l_align_src); ++ copy_core_forward(32, src, dst, count, tmp1, tmp2); ++ ++ __ BIND(l_tail); ++ __ ble(count, l_end); ++ ++ //copy tail bytes. ++ __ BIND(l_tail_bytes); ++ __ ldbu(tmp1, src, 0); ++ __ stb(tmp1, dst, 0); ++ __ addl(src, src, 1); ++ __ addl(dst, dst, 1); ++ __ subl(count, count, 1); ++ __ bne(count, l_tail_bytes); ++ ++ __ BIND(l_end); ++ ++ }else{ ++ generate_disjoint_copy(0, src, dst, count); ++ } ++ __ ret(); ++ ++ return start; ++} ++ ++ ++ void generate_disjoint_copy(int widthInByte, Register src, Register dst, Register count) { ++ // Label lblMissAlignInByte, lblMissAlignInShort, lblMissAlignInWord, lblMissAlignInLong; ++ Label lblMissAlign[4]; ++ // Label lblSkipByte, lblSkipInShort, lblSkipInWord, lblSkipInLong; ++ Label lblSkip[4]; ++ // Label lblCopyByte, lblCopyShort, lblCopyWord, lblCopyLong; ++ Label lblCopy[4]; ++ ++ ++// __ subl(count, 9, AT); //why the number is 9 ? ++ if (widthInByte == 0) {__ subl(AT, count, 9); __ ble(AT, lblMissAlign[1]);} ++ if (widthInByte == 1) {__ subl(AT, count, 9); __ ble(AT, lblMissAlign[2]);} ++ ++ for (int i = widthInByte; i < 3; i++) { ++ __ xor_ins(AT, src, dst); ++ __ and_imm8(AT, AT, 1 << i); // if the backward ith bit of src and and dst is the same ++ __ bne(AT, lblMissAlign[i+1]); // if arrays don't have the same alignment, ... ++ ++ __ and_imm8(AT, src, 1 << i); ++ __ beq(AT, lblSkip[i]); // have same alignment but extra byte/short/int ++ ++ __ load(i, AT, 0, src); ++ __ store(i, AT, 0, dst); ++ __ addl(src, src, 1 << i); ++ __ addl(dst, dst, 1 << i); ++ __ subl(count, count, 1 << i); ++ ++ __ BIND(lblSkip[i]); ++ } ++ ++ for (int i = 3; i >= widthInByte; i--) { // FasterArrayCopy ++ if(i == widthInByte){ ++ __ beq(count, lblMissAlign[i]); ++ }else{ ++ __ cmplt(AT, count, 1 << i); ++ __ bne(AT, lblMissAlign[i]); ++ } ++ __ BIND(lblCopy[i]); ++ __ load(i, AT, 0, src); ++ __ store(i, AT, 0, dst); ++ __ addl(src, src, 1 << i); ++ __ addl(dst, dst, 1 << i); ++ __ subl(count, count, 1 << i); ++ if(i == widthInByte){ ++ __ bne(count, lblCopy[i]); ++ }else{ ++ __ subl(AT, count, 1 << i); ++ __ bge(AT, lblCopy[i]); ++ } ++ __ BIND(lblMissAlign[i]); ++ } ++ } ++ void generate_conjoint_copy(int widthInByte,Register src, Register dst, Register count) { ++ // Label lblMissAlignInByte, lblMissAlignInShort, lblMissAlignInWord, lblMissAlignInLong; ++ Label lblMissAlign[4]; ++ // Label lblSkipByte, lblSkipInShort, lblSkipInWord, lblSkipInLong; ++ Label lblSkip[4]; ++ // Label lblCopyByte, lblCopyShort, lblCopyWord, lblCopyLong; ++ Label lblCopy[4]; ++ ++ if (widthInByte == 0) {__ subl(AT, count, 9); __ ble(AT, lblMissAlign[1]);} ++ if (widthInByte == 1) {__ subl(AT, count, 9); __ ble(AT, lblMissAlign[2]);} ++ ++ for (int i = widthInByte; i < 3; i++) { ++ __ xor_ins(AT, src, dst); ++ __ and_imm8(AT, AT, 1 << i); // if the backward ith bit of src and and dst is the same ++ __ bne(AT, lblMissAlign[i+1]); // if arrays don't have the same alignment, ... ++ ++ __ and_imm8(AT, src, 1 << i); ++ __ beq(AT, lblSkip[i]); // have same alignment but extra byte/short/int ++ ++ __ subl(src, src, 1 << i); ++ __ subl(dst, dst, 1 << i); ++ __ load(i, AT, 0, src); ++ __ store(i, AT, 0, dst); ++ __ subl(count, count, 1 << i); ++ ++ __ BIND(lblSkip[i]); ++ } ++ ++ for (int i = 3; i >= widthInByte; i--) { // FasterArrayCopy ++ if(i == widthInByte){ ++ __ beq(count, lblMissAlign[i]); ++ }else{ ++ __ cmplt(AT, count, 1 << i); ++ __ bne(AT, lblMissAlign[i]); ++ } ++ ++ __ BIND(lblCopy[i]); ++ __ subl(src, src, 1 << i); ++ __ subl(dst, dst, 1 << i); ++ __ load(i, AT, 0, src); ++ __ store(i, AT, 0, dst); ++ __ subl(count, count, 1 << i); ++ if(i == widthInByte){ ++ __ bne(count, lblCopy[i]); ++ }else{ ++ __ subl(AT, count, 1 << i); ++ __ bge(AT, lblCopy[i]); ++ } ++ __ BIND(lblMissAlign[i]); ++ } ++} ++ ++ // Arguments: ++ // aligned - true => Input and output aligned on a HeapWord == 8-byte boundary ++ // ignored ++ // name - stub name string ++ // ++ // Inputs: ++ // A0 - source array address ++ // A1 - destination array address ++ // A2 - element count, treated as ssize_t, can be zero ++ // ++ // If 'from' and/or 'to' are aligned on 4-, 2-, or 1-byte boundaries, ++ // we let the hardware handle it. The one to eight bytes within words, ++ // dwords or qwords that span cache line boundaries will still be loaded ++ // and stored atomically. ++ // ++ address generate_conjoint_byte_copy(bool aligned, address *entry, const char *name) { ++ __ align(CodeEntryAlignment); ++ StubCodeMark mark(this, "StubRoutines", name); ++ ++ address start = __ pc(); ++ ++ Label l_exit; ++ Label l_copy_byte; ++ Label l_align_dst, l_align_src, l_tail_bytes, l_end, l_tail; ++ ++ if (entry != NULL) { ++ *entry = start; ++ // caller can pass a 64-bit byte count here (from Unsafe.copyMemory) ++ BLOCK_COMMENT("Entry:"); ++ } ++ ++ address nooverlap_target = aligned ? ++ StubRoutines::arrayof_jbyte_disjoint_arraycopy() : ++ StubRoutines::jbyte_disjoint_arraycopy(); ++ ++ array_overlap_test(nooverlap_target, 0); ++ ++ Register src = A0; // source array address ++ Register dst = A1; // destination array address ++ Register count = A2; // elements count ++ Register end_src = T3; // source array end address ++ Register end_dst = T0; // destination array end address ++ Register end_count = T1; // destination array end address ++ Register tmp1 = AT; ++ Register tmp2 = GP; ++ ++ ++ // copy from high to low ++ __ move(end_count, count); ++ __ addl(end_src, src, end_count); ++ __ addl(end_dst, dst, end_count); ++ ++ if(UseSimdBackward){ ++ ++ __ beq(count, l_end); ++ ++ __ cmple(tmp1, count, 63); ++ __ bne(tmp1, l_tail_bytes); //when count <= 63, don't use simd ++ ++ __ BIND(l_align_dst); ++ __ and_imm8(tmp1, end_dst, 31); //is dst 0mod32? ++ __ beq(tmp1, l_align_src); ++ ++ __ ldbu(tmp2, end_src, -1); //grab 1 bytes at a time, until dst is 0mod32 ++ __ stb(tmp2, end_dst, -1); ++ __ subl(count, count, 1); ++ __ subl(end_dst, end_dst, 1); ++ __ subl(end_src, end_src, 1); ++ __ beq(R0, l_align_dst); ++ ++ __ BIND(l_align_src); ++ copy_core_backward(32, end_src, end_dst, count, tmp1, tmp2); ++ ++ __ BIND(l_tail); ++ __ ble(count, l_end); ++ ++ __ BIND(l_tail_bytes); ++ __ ldbu(tmp1, end_src, -1); ++ __ stb(tmp1, end_dst, -1); ++ __ subl(end_src, end_src, 1); ++ __ subl(end_dst, end_dst, 1); ++ __ subl(count, count, 1); ++ __ bne(count, l_tail_bytes); ++ ++ __ BIND(l_end); ++ ++ } else { ++ generate_conjoint_copy(0, end_src, end_dst, end_count); ++ } ++ __ ret(); ++ return start; ++ } ++ // ++ // Generate 'unsafe' array copy stub ++ // Though just as safe as the other stubs, it takes an unscaled ++ // size_t argument instead of an element count. ++ // ++ // Input: ++ // c_rarg0 - source array address ++ // c_rarg1 - destination array address ++ // c_rarg2 - byte count, treated as ssize_t, can be zero ++ // ++ // Examines the alignment of the operands and dispatches ++ // to a long, int, short, or byte copy loop. ++ // ++ address generate_unsafe_copy(const char *name, ++ address byte_copy_entry, ++ address short_copy_entry, ++ address int_copy_entry, ++ address long_copy_entry) { ++ Label L_long_aligned, L_int_aligned, L_short_aligned; ++ Register s = A0, d = A1, count = A2; ++ ++ __ align(CodeEntryAlignment); ++ StubCodeMark mark(this, "StubRoutines", name); ++ address start = __ pc(); ++ //__ enter(); // required for proper stackwalking of RuntimeStub frame ++ ++ // bump this on entry, not on exit: ++ // inc_counter_np(SharedRuntime::_unsafe_array_copy_ctr); ++ ++ __ bis(AT, s, d); ++ __ bis(AT, AT, count); ++ if (PrefetchUnsafeCopyInBytes > 0) ++ __ fillcs(s, PrefetchUnsafeCopyInBytes); ++ ++ __ and_imm8(AT, AT, BytesPerLong - 1); ++ __ beq(AT, L_long_aligned); ++ __ and_imm8(AT, AT, BytesPerInt - 1); ++ __ beq(AT, L_int_aligned); ++ __ and_imm8(AT, AT, BytesPerShort - 1); ++ __ beq(AT, L_short_aligned); ++ __ beq_a(R0, byte_copy_entry); ++ ++ __ BIND(L_short_aligned); ++ __ srll(count, count, LogBytesPerShort); // size => short_count ++ __ beq_a(R0, short_copy_entry); ++ __ BIND(L_int_aligned); ++ __ srll(count, count, LogBytesPerInt); // size => int_count ++ __ beq_a(R0, int_copy_entry); ++ __ BIND(L_long_aligned); ++ __ srll(count, count, LogBytesPerLong); // size => long_count ++ __ beq_a(R0, long_copy_entry); ++ ++ return start; ++ } ++ // ++ // Generate 'unsafe' array copy stub ++ // Though just as safe as the other stubs, it takes an unscaled ++ // size_t argument instead of an element count. ++ // ++ // Input: ++ // A0 - source array address ++ // A1 - destination array address ++ // A2 - byte count, treated as ssize_t, can be zero ++ // ++ // Examines the alignment of the operands and dispatches ++ // to a long, int, short, or byte copy loop. ++ // ++ address generate_unsafe_copy(const char *name) { ++ Label L_long_aligned, L_int_aligned, L_short_aligned; ++ Register s = A0, d = A1, count = A2; ++ ++ __ align(CodeEntryAlignment); ++ StubCodeMark mark(this, "StubRoutines", name); ++ address start = __ pc(); ++ ++ __ bis(AT, s, d); ++ __ bis(AT, AT, count); ++ ++ __ and_imm8(AT, AT, BytesPerLong-1); ++ __ beq(AT, L_long_aligned); ++ __ and_imm8(AT, AT, BytesPerInt-1); ++ __ beq(AT, L_int_aligned); ++ __ and_imm8(AT, AT, BytesPerShort-1); ++ __ beq(AT, L_short_aligned); ++ __ beq_a(R0, StubRoutines::_jbyte_arraycopy); ++ ++ __ bind(L_short_aligned); ++ __ srll(count, count, LogBytesPerShort); // size => short_count ++ __ beq_a(R0, StubRoutines::_jshort_arraycopy); ++ __ bind(L_int_aligned); ++ __ srll(count, count, LogBytesPerInt); // size => int_count ++ __ beq_a(R0, StubRoutines::_jint_arraycopy); ++ __ bind(L_long_aligned); ++ __ srll(count, count, LogBytesPerLong); // size => long_count ++ __ beq_a(R0, StubRoutines::_jlong_arraycopy); ++ ++ return start; ++ } ++ // Generate stub for disjoint short copy. If "aligned" is true, the ++ // "from" and "to" addresses are assumed to be heapword aligned. ++ // ++ // Arguments for generated stub: ++ // from: A0 ++ // to: A1 ++ // elm.count: A2 treated as signed ++ // one element: 2 bytes ++ // ++ // Strategy for aligned==true: ++ // ++ // If length <= 9: ++ // 1. copy 1 elements at a time (l_5) ++ // ++ // If length > 9: ++ // 1. copy 4 elements at a time until less than 4 elements are left (l_7) ++ // 2. copy 2 elements at a time until less than 2 elements are left (l_6) ++ // 3. copy last element if one was left in step 2. (l_1) ++ // ++ // ++ // Strategy for aligned==false: ++ // ++ // If length <= 9: same as aligned==true case ++ // ++ // If length > 9: ++ // 1. continue with step 7. if the alignment of from and to mod 4 ++ // is different. ++ // 2. align from and to to 4 bytes by copying 1 element if necessary ++ // 3. at l_2 from and to are 4 byte aligned; continue with ++ // 6. if they cannot be aligned to 8 bytes because they have ++ // got different alignment mod 8. ++ // 4. at this point we know that both, from and to, have the same ++ // alignment mod 8, now copy one element if necessary to get ++ // 8 byte alignment of from and to. ++ // 5. copy 4 elements at a time until less than 4 elements are ++ // left; depending on step 3. all load/stores are aligned. ++ // 6. copy 2 elements at a time until less than 2 elements are ++ // left. (l_6) ++ // 7. copy 1 element at a time. (l_5) ++ // 8. copy last element if one was left in step 6. (l_1) ++ ++ address generate_disjoint_short_copy(bool aligned, const char * name) { ++ StubCodeMark mark(this, "StubRoutines", name); ++ __ align(CodeEntryAlignment); ++ ++ Register src = T0; ++ Register dst = T1; ++ Register count = T3; ++ Register tmp1 = GP; ++ Register tmp2 = AT; ++ ++ Register tmp4 = T11; ++ Register tmp5 = T12; ++ Register tmp6 = T2; ++ ++ address start = __ pc(); ++ ++ __ move(src, A0); ++ __ move(dst, A1); ++ __ move(count, A2); ++ ++ Label l_1, l_2, l_3, l_4, l_5, l_6, l_7, l_8, l_9, l_10, l_11, l_12, l_13, l_14; ++ Label l_debug; ++ Label l_align_dst, l_align_src, l_tail_2_bytes, l_end, l_tail; ++ // don't try anything fancy if arrays don't have many elements ++ ++ if(UseSimdForward){ ++ ++ __ cmple(tmp1, count, 31); //if count < 32(bytes < 64), then copy 2 bytes at a time ++ __ bne(tmp1, l_tail); ++ ++ __ BIND(l_align_dst); ++ __ and_imm8(tmp1, dst, 31); ++ __ beq(tmp1, l_align_src); ++ ++ __ ldhu(tmp2, src, 0); ++ __ subl(count, count, 1); ++ __ sth(tmp2, dst, 0); ++ __ addl(src, src, 2); ++ __ addl(dst, dst, 2); ++ __ beq(R0, l_align_dst); ++ ++ __ BIND(l_align_src); ++ copy_core_forward(16, src, dst, count, tmp1, tmp2); ++ ++ __ BIND(l_tail); ++ __ ble(count, l_end); ++ ++ __ BIND(l_tail_2_bytes); ++ __ ldhu(tmp1, src, 0); ++ __ sth(tmp1, dst, 0); ++ __ addl(src, src, 2); ++ __ addl(dst, dst, 2); ++ __ subl(count, count, 1); ++ __ bne(count, R0, l_tail_2_bytes); ++ ++ ++ __ BIND(l_end); ++ ++ } else { ++ __ slll(count, count, 1); ++ generate_disjoint_copy(1, src, dst, count); ++ } ++ __ ret(); ++ ++ __ stop("generate_disjoint_short_copy should not reach here"); ++ return start; ++ } ++ ++ // Arguments: ++ // aligned - true => Input and output aligned on a HeapWord == 8-byte boundary ++ // ignored ++ // name - stub name string ++ // ++ // Inputs: ++ // c_rarg0 - source array address ++ // c_rarg1 - destination array address ++ // c_rarg2 - element count, treated as ssize_t, can be zero ++ // ++ // If 'from' and/or 'to' are aligned on 4- or 2-byte boundaries, we ++ // let the hardware handle it. The two or four words within dwords ++ // or qwords that span cache line boundaries will still be loaded ++ // and stored atomically. ++ // ++ address generate_conjoint_short_copy(bool aligned, address *entry, const char *name) { ++ Label l_tail_2_bytes, l_align_dst, l_align_src, l_tail, l_end, l_exit, l_copy_2_bytes; ++ StubCodeMark mark(this, "StubRoutines", name); ++ __ align(CodeEntryAlignment); ++ address start = __ pc(); ++ address nooverlap_target = aligned ? ++ StubRoutines::arrayof_jshort_disjoint_arraycopy() : ++ StubRoutines::jshort_disjoint_arraycopy(); ++ ++ array_overlap_test(nooverlap_target, 1); ++ ++ if (entry != NULL) { ++ *entry = start; ++ // caller can pass a 64-bit byte count here (from Unsafe.copyMemory) ++ BLOCK_COMMENT("Entry:"); ++ } ++ ++ Register end_src = T3; ++ Register end_dst = T0; ++ Register count = T1; ++ Register tmp1 = AT; ++ Register tmp2 = GP; ++ ++ ++ __ move(T1, A2); ++ __ move(T3, A0); ++ __ move(T0, A1); ++ ++ if(UseSimdBackward){ ++ ++ __ beq(count, R0, l_end); ++ ++ __ sllw_signed(tmp1, T1, Address::times_2); ++ __ addl(end_src, T3, tmp1); ++ __ addl(end_dst, T0, tmp1); ++ ++ __ cmple(tmp1, count, 31); ++ __ bne(tmp1, l_tail_2_bytes); //when count <= 31, don't use simd ++ ++ __ BIND(l_align_dst); ++ __ and_imm8(tmp1, end_dst, 31); //is dst 0mod32? ++ __ beq(tmp1, l_align_src); ++ ++ __ ldhu(tmp2, end_src, -2); //grab 2 bytes at a time, until dst is 0mod32 ++ __ sth(tmp2, end_dst, -2); ++ __ subl(count, count, 1); ++ __ subl(end_dst, end_dst, 2); ++ __ subl(end_src, end_src, 2); ++ __ beq(R0, l_align_dst); ++ ++ __ BIND(l_align_src); ++ copy_core_backward(16, end_src, end_dst, count, tmp1, tmp2); ++ ++ __ BIND(l_tail); ++ __ ble(count, l_end); ++ ++ __ BIND(l_tail_2_bytes); ++ __ ldhu(tmp1, end_src, -2); ++ __ sth(tmp1, end_dst, -2); ++ __ subl(end_src, end_src, 2); ++ __ subl(end_dst, end_dst, 2); ++ __ subl(count, count, 1); ++ __ bne(count, R0, l_tail_2_bytes); ++ ++ __ BIND(l_end); ++ ++ }else{ ++ __ slll(count, count, 1); ++ __ addl(end_src, T3, count); ++ __ addl(end_dst, T0, count); ++ generate_conjoint_copy(1, end_src, end_dst, count); ++ } ++ __ ret(); ++ return start; ++ } ++ ++ // Arguments: ++ // aligned - true => Input and output aligned on a HeapWord == 8-byte boundary ++ // ignored ++ // is_oop - true => oop array, so generate store check code ++ // name - stub name string ++ // ++ // Inputs: ++ // c_rarg0 - source array address ++ // c_rarg1 - destination array address ++ // c_rarg2 - element count, treated as ssize_t, can be zero ++ // ++ // If 'from' and/or 'to' are aligned on 4-byte boundaries, we let ++ // the hardware handle it. The two dwords within qwords that span ++ // cache line boundaries will still be loaded and stored atomicly. ++ // ++ // Side Effects: ++ // disjoint_int_copy_entry is set to the no-overlap entry point ++ // used by generate_conjoint_int_oop_copy(). ++ // ++ address generate_disjoint_int_oop_copy(bool aligned, bool is_oop, const char *name, bool dest_uninitialized = false) { ++ Label l_tail_4_bytes, l_align_dst, l_align_src, l_align_simd, l_misalign, l_misalign_simd, l_tail, l_before_tail, l_end; ++ StubCodeMark mark(this, "StubRoutines", name); ++ ++ Register src = T3; ++ Register dst = T0; ++ Register count = T1; ++ Register tmp1 = AT; ++ Register tmp2 = GP; ++ __ align(CodeEntryAlignment); ++ address start = __ pc(); ++ __ move(count, A2); ++ __ move(src, A0); ++ __ move(dst, A1); ++ ++ if (is_oop) { ++ gen_write_ref_array_pre_barrier(A1, A2, dest_uninitialized); ++ } ++ ++ if(UseSimdForward){ ++ ++ __ cmple(tmp1, count, 15); ++ __ bne(tmp1, l_tail); ++ ++ __ BIND(l_align_dst); ++ __ and_imm8(tmp1, dst, 31); ++ __ beq(tmp1, l_align_src); ++ ++ __ ldw(tmp1, src, 0); ++ __ subl(count, count, 1); ++ __ stw(tmp1, dst, 0); ++ __ addl(src, src, 4); ++ __ addl(dst, dst, 4); ++ __ beq(R0, l_align_dst); ++ ++ __ BIND(l_align_src); ++ copy_core_forward(8, src, dst, count, tmp1, tmp2); ++ ++ __ BIND(l_tail); ++ __ ble(count, l_end); ++ ++ __ BIND(l_tail_4_bytes); ++ __ ldw(tmp2, src, 0); ++ __ stw(tmp2, dst, 0); ++ __ addl(src, src, 4); ++ __ addl(dst, dst, 4); ++ __ subl(count, count, 1); ++ __ bne(count, R0, l_tail_4_bytes); ++ ++ ++ __ BIND(l_end); ++ ++ } else { ++ __ slll(count, count, 2); ++ generate_disjoint_copy(2, src, dst, count); ++ } ++ if (is_oop) { ++ gen_write_ref_array_post_barrier(A1, A2, T1); ++ } ++ __ ret(); ++ return start; ++ } ++ ++ // Arguments: ++ // aligned - true => Input and output aligned on a HeapWord == 8-byte boundary ++ // ignored ++ // is_oop - true => oop array, so generate store check code ++ // name - stub name string ++ // ++ // Inputs: ++ // c_rarg0 - source array address ++ // c_rarg1 - destination array address ++ // c_rarg2 - element count, treated as ssize_t, can be zero ++ // ++ // If 'from' and/or 'to' are aligned on 4-byte boundaries, we let ++ // the hardware handle it. The two dwords within qwords that span ++ // cache line boundaries will still be loaded and stored atomicly. ++ // ++ address generate_conjoint_int_oop_copy(bool aligned, bool is_oop, address *entry, const char *name, bool dest_uninitialized = false) { ++ Label l_2, l_4; ++ Label l_tail_4_bytes, l_align_dst, l_align_src, l_tail, l_end; ++ StubCodeMark mark(this, "StubRoutines", name); ++ __ align(CodeEntryAlignment); ++ address start = __ pc(); ++ address nooverlap_target; ++ ++ if (entry != NULL) { ++ *entry = start; ++ // caller can pass a 64-bit byte count here (from Unsafe.copyMemory) ++ BLOCK_COMMENT("Entry:"); ++ } ++ ++ if (is_oop) { ++ nooverlap_target = aligned ? ++ StubRoutines::arrayof_oop_disjoint_arraycopy() : ++ StubRoutines::oop_disjoint_arraycopy(); ++ }else { ++ nooverlap_target = aligned ? ++ StubRoutines::arrayof_jint_disjoint_arraycopy() : ++ StubRoutines::jint_disjoint_arraycopy(); ++ } ++ ++ array_overlap_test(nooverlap_target, 2); ++ ++ Register end_src = T3; ++ Register end_dst = T0; ++ Register count = T1; ++ Register tmp1 = AT; ++ Register tmp2 = GP; ++ ++ if (is_oop) { ++ gen_write_ref_array_pre_barrier(A1, A2, dest_uninitialized); ++ } ++ ++ ++ __ move(T1, A2); ++ __ move(T3, A0); ++ __ move(T0, A1); ++ ++ // T3: source array address ++ // T0: destination array address ++ // T1: element count ++ ++ if(UseSimdBackward){ ++ ++ __ beq(count, R0, l_end); ++ ++ __ sllw_signed(tmp1, T1, Address::times_4); ++ __ addl(end_src, T3, tmp1); ++ __ addl(end_dst, T0, tmp1); ++ ++ __ cmple(tmp1, count, 15); ++ __ bne(tmp1, l_tail_4_bytes); //when count <= 15, don't use simd ++ ++ __ BIND(l_align_dst); ++ __ and_imm8(tmp1, end_dst, 31); //is dst 0mod32? ++ __ beq(tmp1, l_align_src); ++ ++ __ ldw(tmp1, end_src, -4); //grab 4 bytes at a time, until dst is 0mod32 ++ __ stw(tmp1, end_dst, -4); ++ __ subl(count, count, 1); ++ __ subl(end_dst, end_dst, 4); ++ __ subl(end_src, end_src, 4); ++ __ beq(R0, l_align_dst); ++ ++ __ BIND(l_align_src); ++ copy_core_backward(8, end_src, end_dst, count, tmp1, tmp2); ++ ++ __ BIND(l_tail); ++ __ ble(count, l_end); ++ ++ __ BIND(l_tail_4_bytes); ++ __ ldw(tmp1, end_src, -4); ++ __ stw(tmp1, end_dst, -4); ++ __ subl(end_src, end_src, 4); ++ __ subl(end_dst, end_dst, 4); ++ __ subl(count, count, 1); ++ __ bne(count, R0, l_tail_4_bytes); ++ ++ __ BIND(l_end); ++ ++ }else{ ++ __ slll(count, count, 2); ++ __ addl(end_src, T3, count); ++ __ addl(end_dst, T0, count); ++ generate_conjoint_copy(2, end_src, end_dst, count); ++ } ++ ++ if (is_oop) { ++ gen_write_ref_array_post_barrier(A1, A2, T1); ++ } ++ __ ret(); ++ return start; ++ } ++ ++ // Arguments: ++ // aligned - true => Input and output aligned on a HeapWord == 8-byte boundary ++ // ignored ++ // is_oop - true => oop array, so generate store check code ++ // name - stub name string ++ // ++ // Inputs: ++ // c_rarg0 - source array address ++ // c_rarg1 - destination array address ++ // c_rarg2 - element count, treated as ssize_t, can be zero ++ // ++ // If 'from' and/or 'to' are aligned on 4-byte boundaries, we let ++ // the hardware handle it. The two dwords within qwords that span ++ // cache line boundaries will still be loaded and stored atomicly. ++ // ++ // Side Effects: ++ // disjoint_int_copy_entry is set to the no-overlap entry point ++ // used by generate_conjoint_int_oop_copy(). ++ // ++ address generate_disjoint_long_oop_copy(bool aligned, bool is_oop, const char *name, bool dest_uninitialized = false) { ++ Label l_3, l_4; ++ Label l_tail_8_bytes, l_align_dst, l_align_src, l_tail, l_end; ++ ++ Register src = T3; ++ Register dst = T0; ++ Register count = T1; ++ Register tmp1 = AT; ++ Register tmp2 = GP; ++ ++ StubCodeMark mark(this, "StubRoutines", name); ++ __ align(CodeEntryAlignment); ++ address start = __ pc(); ++ ++ if (is_oop) { ++ gen_write_ref_array_pre_barrier(A1, A2, dest_uninitialized); ++ } ++ ++ ++ __ move(T1, A2); ++ __ move(T3, A0); ++ __ move(T0, A1); ++ ++ // T3: source array address ++ // T0: destination array address ++ // T1: element count ++ if(UseSimdForward){ ++ __ align(16); ++ __ beq(count, R0, l_end); ++ ++ __ cmple(tmp1, count, 7); ++ __ bne(tmp1, l_tail_8_bytes); //when count <= 7, don't use simd ++ ++ __ BIND(l_align_dst); ++ __ and_imm8(tmp1, dst, 31); //is dst 0mod32? ++ __ beq(tmp1, l_align_src); ++ ++ __ ldl(tmp1, src, 0); //grab 8 bytes at a time, until dst is 0mod32 ++ __ stl(tmp1, dst, 0); ++ __ subl(count, count, 1); ++ __ addl(dst, dst, 8); ++ __ addl(src, src, 8); ++ __ beq(R0, l_align_dst); ++ ++ __ BIND(l_align_src); ++ copy_core_forward(4, src, dst, count, tmp1, tmp2); ++ ++ __ BIND(l_tail); ++ __ ble(count, l_end); ++ ++ __ BIND(l_tail_8_bytes); ++ __ ldl(tmp1, src, 0); ++ __ stl(tmp1, dst, 0); ++ __ addl(src, src, 8); ++ __ addl(dst, dst, 8); ++ __ subl(count, count, 1); ++ __ bne(count, R0, l_tail_8_bytes); ++ ++ __ BIND(l_end); ++ ++ }else{ ++ __ slll(count, count, 3); ++ generate_disjoint_copy(3, src, dst, count); ++ } ++ if (is_oop) { ++ gen_write_ref_array_post_barrier(A1, A2, T1); ++ } ++ __ ret(); ++ return start; ++ } ++ ++ // Arguments: ++ // aligned - true => Input and output aligned on a HeapWord == 8-byte boundary ++ // ignored ++ // is_oop - true => oop array, so generate store check code ++ // name - stub name string ++ // ++ // Inputs: ++ // c_rarg0 - source array address ++ // c_rarg1 - destination array address ++ // c_rarg2 - element count, treated as ssize_t, can be zero ++ // ++ // If 'from' and/or 'to' are aligned on 4-byte boundaries, we let ++ // the hardware handle it. The two dwords within qwords that span ++ // cache line boundaries will still be loaded and stored atomicly. ++ // ++ address generate_conjoint_long_oop_copy(bool aligned, bool is_oop, const char *name, bool dest_uninitialized = false) { ++ Label l_2, l_4; ++ Label l_tail_8_bytes, l_align_dst, l_align_src, l_tail, l_end; ++ StubCodeMark mark(this, "StubRoutines", name); ++ __ align(CodeEntryAlignment); ++ address start = __ pc(); ++ address nooverlap_target; ++ ++ if (is_oop) { ++ nooverlap_target = aligned ? ++ StubRoutines::arrayof_oop_disjoint_arraycopy() : ++ StubRoutines::oop_disjoint_arraycopy(); ++ }else { ++ nooverlap_target = aligned ? ++ StubRoutines::arrayof_jlong_disjoint_arraycopy() : ++ StubRoutines::jlong_disjoint_arraycopy(); ++ } ++ ++ array_overlap_test(nooverlap_target, 3); ++ ++ Register end_src = T3; ++ Register end_dst = T0; ++ Register count = T1; ++ Register tmp1 = AT; ++ Register tmp2 = GP; ++ ++ if (is_oop) { ++ gen_write_ref_array_pre_barrier(A1, A2, dest_uninitialized); ++ } ++ ++ ++ __ move(T1, A2); ++ __ move(T3, A0); ++ __ move(T0, A1); ++ ++ if(UseSimdLongOop){ ++ __ align(16); ++ __ beq(count, R0, l_end); ++ ++ __ sllw_signed(tmp1, T1, Address::times_8); ++ __ addl(end_src, T3, tmp1); ++ __ addl(end_dst, T0, tmp1); ++ ++ __ cmple(tmp1, count, 7); ++ __ bne(tmp1, l_tail_8_bytes); //when count <= 7, don't use simd ++ ++ __ BIND(l_align_dst); ++ __ and_imm8(tmp1, end_dst, 31); //is dst 0mod32? ++ __ beq(tmp1, l_align_src); ++ ++ __ ldl(tmp1, end_src, -8); //grab 8 bytes at a time, until dst is 0mod32 ++ __ stl(tmp1, end_dst, -8); ++ __ subl(count, count, 1); ++ __ subl(end_dst, end_dst, 8); ++ __ subl(end_src, end_src, 8); ++ __ beq(R0, l_align_dst); ++ ++ __ BIND(l_align_src); ++ copy_core_backward(4, end_src, end_dst, count, tmp1, tmp2); ++ ++ __ BIND(l_tail); ++ __ ble(count, l_end); ++ ++ __ BIND(l_tail_8_bytes); ++ __ ldl(tmp1, end_src, -8); ++ __ stl(tmp1, end_dst, -8); ++ __ subl(end_src, end_src, 8); ++ __ subl(end_dst, end_dst, 8); ++ __ subl(count, count, 1); ++ __ bne(count, R0, l_tail_8_bytes); ++ ++ __ BIND(l_end); ++ ++ }else{ ++ __ slll(count, count, Address::times_8); ++ __ addl(end_src, T3, count); ++ __ addl(end_dst, T0, count); ++ generate_conjoint_copy(3, end_src, end_dst, count); ++ } ++ ++ if (is_oop) { ++ gen_write_ref_array_post_barrier(A1, A2, T1); ++ } ++ __ ret(); ++ return start; ++ } ++ ++ //FIXME ++ address generate_disjoint_long_copy(bool aligned, const char *name) { ++ Label l_1, l_2; ++ Label l_tail_8_bytes, l_align_dst, l_align_src, l_tail, l_end; ++ StubCodeMark mark(this, "StubRoutines", name); ++ __ align(CodeEntryAlignment); ++ address start = __ pc(); ++ ++ Register src = T3; ++ Register dst = T0; ++ Register count = T1; ++ Register tmp1 = AT; ++ Register tmp2 = GP; ++ ++ __ move(T1, A2); ++ __ move(T3, A0); ++ __ move(T0, A1); ++ ++ if(UseSimdForward){ ++ __ align(16); ++ __ beq(count, R0, l_end); ++ ++ __ cmple(tmp1, count, 7); ++ __ bne(tmp1, l_tail_8_bytes); //when count <= 7, don't use simd ++ ++ __ BIND(l_align_dst); ++ __ and_imm8(tmp1, dst, 31); //is dst 0mod32? ++ __ beq(tmp1, l_align_src); ++ ++ __ ldl(tmp1, src, 0); //grab 8 bytes at a time, until dst is 0mod32 ++ __ stl(tmp1, dst, 0); ++ __ subl(count, count, 1); ++ __ addl(dst, dst, 8); ++ __ addl(src, src, 8); ++ __ ble(count, l_end); ++ __ beq(R0, l_align_dst); ++ ++ __ BIND(l_align_src); ++ copy_core_forward(4, src, dst, count, tmp1, tmp2); ++ ++ __ BIND(l_tail); ++ __ ble(count, l_end); ++ ++ __ BIND(l_tail_8_bytes); ++ __ ldl(tmp1, src, 0); ++ __ stl(tmp1, dst, 0); ++ __ addl(src, src, 8); ++ __ addl(dst, dst, 8); ++ __ subl(count, count, 1); ++ __ bne(count, R0, l_tail); ++ ++ __ BIND(l_end); ++ ++ }else{ ++ __ slll(count, count, 3); ++ generate_disjoint_copy(3, src, dst, count); ++ } ++ __ ret(); ++ return start; ++ } ++ ++ ++ address generate_conjoint_long_copy(bool aligned, address *entry, const char *name) { ++ Label l_1, l_2; ++ Label l_tail_8_bytes, l_align_dst, l_align_src, l_tail, l_end; ++ ++ StubCodeMark mark(this, "StubRoutines", name); ++ __ align(CodeEntryAlignment); ++ address start = __ pc(); ++ ++ if (entry != NULL) { ++ *entry = start; ++ // caller can pass a 64-bit byte count here (from Unsafe.copyMemory) ++ BLOCK_COMMENT("Entry:"); ++ } ++ ++ address nooverlap_target = aligned ? ++ StubRoutines::arrayof_jlong_disjoint_arraycopy() : ++ StubRoutines::jlong_disjoint_arraycopy(); ++ array_overlap_test(nooverlap_target, 3); ++ ++ Register end_src = T3; ++ Register end_dst = T0; ++ Register count = T1; ++ Register tmp1 = AT; ++ Register tmp2 = GP; ++ ++ ++ __ move(T1, A2); ++ __ move(T3, A0); ++ __ move(T0, A1); ++ ++ if(UseSimdBackward){ ++ __ align(16); ++ __ beq(count, R0, l_end); ++ ++ __ sllw_signed(tmp1, T1, Address::times_8); ++ __ addl(end_src, T3, tmp1); ++ __ addl(end_dst, T0, tmp1); ++ ++ __ cmple(tmp1, count, 7); ++ __ bne(tmp1, l_tail_8_bytes); //when count <= 7, don't use simd ++ ++ __ BIND(l_align_dst); ++ __ and_imm8(tmp1, end_dst, 31); //is dst 0mod32? ++ __ beq(tmp1, l_align_src); ++ ++ __ ldl(tmp1, end_src, -8); //grab 8 bytes at a time, until dst is 0mod32 ++ __ stl(tmp1, end_dst, -8); ++ __ subl(count, count, 1); ++ __ subl(end_dst, end_dst, 8); ++ __ subl(end_src, end_src, 8); ++ __ ble(count, l_end); ++ __ beq(R0, l_align_dst); ++ ++ __ BIND(l_align_src); ++ copy_core_backward(4, end_src, end_dst, count, tmp1, tmp2); ++ ++ __ BIND(l_tail); ++ __ ble(count, l_end); ++ ++ __ BIND(l_tail_8_bytes); ++ __ ldl(tmp1, end_src, -8); ++ __ stl(tmp1, end_dst, -8); ++ __ subl(end_src, end_src, 8); ++ __ subl(end_dst, end_dst, 8); ++ __ subl(count, count, 1); ++ __ bne(count, R0, l_tail_8_bytes); ++ ++ __ BIND(l_end); ++ ++ }else{ ++ __ slll(count, count, Address::times_8); ++ __ addl(end_src, T3, count); ++ __ addl(end_dst, T0, count); ++ generate_conjoint_copy(3, end_src, end_dst, count); ++ } ++ __ ret(); ++ return start; ++ } ++ ++ void copy_core_forward(int limit, Register src, Register dst, Register count, Register tmp1, Register tmp2){ ++ Label l_misalign, l_misalign_simd, l_align_simd, l_before_tail, l_exit; ++ ++ ++ __ and_imm8(tmp1, src, 31); ++ __ beq(tmp1, l_align_simd); ++ ++ __ BIND(l_misalign); ++ __ and_imm8(tmp1, src, 31); //from low-5-bit = src mod 32 ++ __ slll(tmp1, tmp1, 3); ++ __ ifmovs(F15, tmp1); ++ __ ldi(tmp2, R0, 256); ++ __ subl(tmp1, tmp2, tmp1); ++ __ ifmovs(F17, tmp1); ++ __ andnot(tmp1, src, 31); ++ __ vldd(F10, tmp1, 0); //load 32 bytes from src ++ ++ __ BIND(l_misalign_simd); ++ __ srlow(F12, F10, F15);//get high feild bytes of 32 bytes ++ __ vldd(F10, tmp1, 32); //load next 32 bytes from src+32 ++ __ sllow(F13, F10, F17);//get low field bytes of 32 bytes ++ __ vlog(0xfc, F12, F13, F31, F12); //merge F12, F13, into F12 ++ __ vstd(F12, dst, 0); ++ ++ __ addl(tmp1, tmp1, 32); ++ __ addl(dst, dst, 32); ++ __ subl(count, count, limit); ++ ++ __ cmple(tmp2, count, limit-1); //At least one more trip? ++ __ beq(tmp2, l_misalign_simd); ++ __ beq(R0, l_before_tail); ++ ++ __ BIND(l_align_simd); ++ __ vldd(F10, src, 0); ++ __ vstd(F10, dst, 0); ++ __ subl(count, count, limit); ++ __ addl(src, src, 32); ++ __ addl(dst, dst, 32); ++ __ cmple(tmp1, count, limit-1); //while count >=32, do simd ++ __ beq(tmp1, l_align_simd); ++ __ beq(R0, l_exit); ++ ++ __ BIND(l_before_tail); ++ __ and_imm8(src, src, 31); ++ __ addl(src, tmp1, src); ++ ++ __ BIND(l_exit); ++ } ++ ++ void copy_core_backward(int limit, Register end_src, Register end_dst, Register count, Register tmp1, Register tmp2){ ++ Label l_misalign, l_misalign_simd, l_align_simd, l_before_tail, l_exit; ++ ++ __ and_imm8(tmp1, end_src, 31); ++ __ beq(tmp1, l_align_simd); ++ ++ __ BIND(l_misalign); ++ __ and_imm8(tmp1, end_src, 31); //from low-5-bit = src mod 32 ++ __ slll(tmp1, tmp1, 3); ++ __ ifmovs(F15, tmp1); ++ __ ldi(tmp2, R0, 256); ++ __ subl(tmp1, tmp2, tmp1); ++ __ ifmovs(F17, tmp1); ++ __ andnot(tmp1, end_src, 31); ++ __ vldd(F10, tmp1, 0); //load 32 bytes from src ++ ++ __ BIND(l_misalign_simd); ++ __ sllow(F13, F10, F17);//get low field bytes of 32 bytes ++ __ vldd(F10, tmp1, -32); //load next 32 bytes from src+32 ++ __ srlow(F12, F10, F15);//get high feild bytes of 32 bytes ++ __ vlog(0xfc, F12, F13, F31, F12); //merge F12, F13, into F12 ++ __ vstd(F12, end_dst, -32); ++ ++ __ subl(tmp1, tmp1, 32); ++ __ subl(end_dst, end_dst, 32); ++ __ subl(count, count, limit); ++ ++ __ cmple(tmp2, count, limit-1); //At least one more trip? ++ __ beq(tmp2, l_misalign_simd); ++ __ beq(R0, l_before_tail); ++ ++ __ BIND(l_align_simd); ++ __ vldd(F10, end_src, -32); ++ __ vstd(F10, end_dst, -32); ++ __ subl(count, count, limit); ++ __ subl(end_src, end_src, 32); ++ __ subl(end_dst, end_dst, 32); ++ __ cmple(tmp1, count, limit-1); //while count >=32, do simd ++ __ beq(tmp1, l_align_simd); ++ __ beq(R0, l_exit); ++ ++ __ BIND(l_before_tail); ++ __ and_imm8(end_src, end_src, 31); ++ __ addl(end_src, tmp1, end_src); ++ ++ __ BIND(l_exit); ++ } ++ ++ void generate_arraycopy_stubs() { ++ address entry; ++ address entry_jbyte_arraycopy; ++ address entry_jshort_arraycopy; ++ address entry_jint_arraycopy; ++ address entry_oop_arraycopy; ++ address entry_jlong_arraycopy; ++ address entry_checkcast_arraycopy; ++ Label byte_small_copy, short_small_copy, int_small_copy, long_small_copy; ++ Label disjoint_large_copy, conjoint_large_copy, disjoint_large_copy_simd, conjoint_large_copy_simd; ++ generate_disjoint_large_copy_simd("disjoint_large_copy_simd"); ++ generate_disjoint_large_copy("disjoint_large_copy"); ++ generate_conjoint_large_copy_simd("disjoint_large_copy_simd"); ++ generate_conjoint_large_copy("disjoint_large_copy"); ++ generate_byte_small_copy(byte_small_copy, "jbyte_small_copy"); ++ generate_short_small_copy(short_small_copy, "jshort_small_copy"); ++// generate_int_small_copy(int_small_copy, "jint_small_copy"); ++// generate_long_small_copy(long_small_copy, "jlong_small_copy"); ++ if (UseCompressedOops) { ++ StubRoutines::_oop_disjoint_arraycopy = generate_disjoint_int_oop_copy(false, true, ++ "oop_disjoint_arraycopy"); ++ StubRoutines::_oop_arraycopy = generate_conjoint_int_oop_copy(false, true, &entry_jint_arraycopy, ++ "oop_arraycopy"); ++ StubRoutines::_oop_disjoint_arraycopy_uninit = generate_disjoint_int_oop_copy(false, true, ++ "oop_disjoint_arraycopy_uninit", true); ++ StubRoutines::_oop_arraycopy_uninit = generate_conjoint_int_oop_copy(false, true, &entry_jint_arraycopy, ++ "oop_arraycopy_uninit", true); ++ } else { ++ StubRoutines::_oop_disjoint_arraycopy = generate_disjoint_long_oop_copy(false, true, ++ "oop_disjoint_arraycopy"); ++ StubRoutines::_oop_arraycopy = generate_conjoint_long_oop_copy(false, true, ++ "oop_arraycopy"); ++ StubRoutines::_oop_disjoint_arraycopy_uninit = generate_disjoint_long_oop_copy(false, true, ++ "oop_disjoint_arraycopy_uninit", true); ++ StubRoutines::_oop_arraycopy_uninit = generate_conjoint_long_oop_copy(false, true, ++ "oop_arraycopy_uninit", true); ++ } ++ if(SolveAlignment) { ++ StubRoutines::_jbyte_disjoint_arraycopy = generate_disjoint_byte_copy(false, "jbyte_disjoint_arraycopy"); ++ StubRoutines::_jshort_disjoint_arraycopy = generate_disjoint_short_copy(false, "jshort_disjoint_arraycopy"); ++ StubRoutines::_jbyte_arraycopy = generate_conjoint_byte_copy(false, &entry_jbyte_arraycopy, "jbyte_arraycopy"); ++ StubRoutines::_jshort_arraycopy = generate_conjoint_short_copy(false, &entry_jshort_arraycopy, "jshort_arraycopy"); ++ } else { ++ StubRoutines::_jbyte_disjoint_arraycopy = generate_disjoint_byte_copy(false, byte_small_copy, disjoint_large_copy_simd, disjoint_large_copy, "jbyte_disjoint_arraycopy"); ++ StubRoutines::_jshort_disjoint_arraycopy = generate_disjoint_short_copy(false, short_small_copy, disjoint_large_copy_simd, disjoint_large_copy, "jshort_disjoint_arraycopy"); ++ StubRoutines::_jbyte_arraycopy = generate_conjoint_byte_copy(false, byte_small_copy, conjoint_large_copy_simd, conjoint_large_copy, "jbyte_arraycopy"); ++ StubRoutines::_jshort_arraycopy = generate_conjoint_short_copy(false, short_small_copy, conjoint_large_copy_simd, conjoint_large_copy, "jshort_arraycopy"); ++ } ++ StubRoutines::_jint_disjoint_arraycopy = generate_disjoint_int_oop_copy(false, false, "jint_disjoint_arraycopy"); ++ StubRoutines::_jlong_disjoint_arraycopy = generate_disjoint_long_copy(false, "jlong_disjoint_arraycopy"); ++ StubRoutines::_jint_arraycopy = generate_conjoint_int_oop_copy(false, false, &entry_jint_arraycopy, "jint_arraycopy"); ++ StubRoutines::_jlong_arraycopy = generate_conjoint_long_copy(false, &entry_jlong_arraycopy, "jlong_arraycopy"); ++ ++ // We don't generate specialized code for HeapWord-aligned source ++ // arrays, so just use the code we've already generated ++ StubRoutines::_arrayof_jbyte_disjoint_arraycopy = StubRoutines::_jbyte_disjoint_arraycopy; ++ StubRoutines::_arrayof_jbyte_arraycopy = StubRoutines::_jbyte_arraycopy; ++ ++ StubRoutines::_arrayof_jshort_disjoint_arraycopy = StubRoutines::_jshort_disjoint_arraycopy; ++ StubRoutines::_arrayof_jshort_arraycopy = StubRoutines::_jshort_arraycopy; ++ ++ StubRoutines::_arrayof_jint_disjoint_arraycopy = StubRoutines::_jint_disjoint_arraycopy; ++ StubRoutines::_arrayof_jint_arraycopy = StubRoutines::_jint_arraycopy; ++ ++ StubRoutines::_arrayof_jlong_disjoint_arraycopy = StubRoutines::_jlong_disjoint_arraycopy; ++ StubRoutines::_arrayof_jlong_arraycopy = StubRoutines::_jlong_arraycopy; ++ ++ StubRoutines::_arrayof_oop_disjoint_arraycopy = StubRoutines::_oop_disjoint_arraycopy; ++ StubRoutines::_arrayof_oop_arraycopy = StubRoutines::_oop_arraycopy; ++ ++ StubRoutines::_arrayof_oop_disjoint_arraycopy_uninit = StubRoutines::_oop_disjoint_arraycopy_uninit; ++ StubRoutines::_arrayof_oop_arraycopy_uninit = StubRoutines::_oop_arraycopy_uninit; ++ if(UseUnsafeCopyIntrinsic){ ++ StubRoutines::_unsafe_arraycopy = generate_unsafe_copy("unsafe_arraycopy"); ++ } ++ } ++ ++ // add a function to implement SafeFetch32 and SafeFetchN ++ void generate_safefetch(const char* name, int size, address* entry, ++ address* fault_pc, address* continuation_pc) { ++ // safefetch signatures: ++ // int SafeFetch32(int* adr, int errValue); ++ // intptr_t SafeFetchN (intptr_t* adr, intptr_t errValue); ++ // ++ // arguments: ++ // A0 = adr ++ // A1 = errValue ++ // ++ // result: ++ // PPC_RET = *adr or errValue ++ ++ StubCodeMark mark(this, "StubRoutines", name); ++ ++ // Entry point, pc or function descriptor. ++ *entry = __ pc(); ++ ++ // Load *adr into A1, may fault. ++ *fault_pc = __ pc(); ++ switch (size) { ++ case 4: ++ // int32_t ++ __ ldw(A1, A0, 0); ++ break; ++ case 8: ++ // int64_t ++ __ ldl(A1, A0, 0); ++ break; ++ default: ++ ShouldNotReachHere(); ++ } ++ ++ // return errValue or *adr ++ *continuation_pc = __ pc(); ++ __ addl(V0,A1,R0); ++ __ ret(); ++ } ++ ++ /** ++ * Arguments: ++ * ++ * Inputs: ++ * A0 - int crc ++ * A1 - byte* buf ++ * A2 - int length ++ * ++ * Output: ++ * V0 - int crc result ++ * ++ */ ++ address generate_updateBytesCRC32() { ++ assert(UseCRC32Intrinsics, "what are we doing here?"); ++ ++ __ align(CodeEntryAlignment); ++ StubCodeMark mark(this, "StubRoutines", "updateBytesCRC32"); ++ ++ address start = __ pc(); ++ ++ const Register crc = A0; // crc ++ const Register buf = A1; // source java byte array address ++ const Register len = A2; // length ++ const Register table = A3; // crc_table address ++ const Register tmp = A4; ++ const Register tmp3 = A5; ++ ++ BLOCK_COMMENT("Entry:"); ++ __ enter(); // required for proper stackwalking of RuntimeStub frame ++ ++ __ kernel_crc32(crc, buf, len, tmp, tmp3); ++ ++ __ leave(); // required for proper stackwalking of RuntimeStub frame ++ __ ret(); ++ ++ return start; ++ } ++ ++#undef __ ++#define __ masm-> ++ ++ // Continuation point for throwing of implicit exceptions that are ++ // not handled in the current activation. Fabricates an exception ++ // oop and initiates normal exception dispatching in this ++ // frame. Since we need to preserve callee-saved values (currently ++ // only for C2, but done for C1 as well) we need a callee-saved oop ++ // map and therefore have to make these stubs into RuntimeStubs ++ // rather than BufferBlobs. If the compiler needs all registers to ++ // be preserved between the fault point and the exception handler ++ // then it must assume responsibility for that in ++ // AbstractCompiler::continuation_for_implicit_null_exception or ++ // continuation_for_implicit_division_by_zero_exception. All other ++ // implicit exceptions (e.g., NullPointerException or ++ // AbstractMethodError on entry) are either at call sites or ++ // otherwise assume that stack unwinding will be initiated, so ++ // caller saved registers were assumed volatile in the compiler. ++ address generate_throw_exception(const char* name, ++ address runtime_entry, ++ bool restore_saved_exception_pc) { ++ // Information about frame layout at time of blocking runtime call. ++ // Note that we only have to preserve callee-saved registers since ++ // the compilers are responsible for supplying a continuation point ++ // if they expect all registers to be preserved. ++ enum layout { ++ thread_off, // last_java_sp ++ S5_off, // callee saved register sp + 3 ++ S4_off, // callee saved register sp + 4 ++ S3_off, // callee saved register sp + 5 ++ S2_off, // callee saved register sp + 6 ++ S1_off, // callee saved register sp + 7 ++ S0_off, // callee saved register sp + 8 ++ FP_off, ++ ret_address, ++ framesize ++ }; ++ ++ int insts_size = 2048; ++ int locs_size = 32; ++ ++ // CodeBuffer* code = new CodeBuffer(insts_size, locs_size, 0, 0, 0, false, ++ // NULL, NULL, NULL, false, NULL, name, false); ++ CodeBuffer code (name , insts_size, locs_size); ++ OopMapSet* oop_maps = new OopMapSet(); ++ MacroAssembler* masm = new MacroAssembler(&code); ++ ++ address start = __ pc(); ++ ++ // This is an inlined and slightly modified version of call_VM ++ // which has the ability to fetch the return PC out of ++ // thread-local storage and also sets up last_Java_sp slightly ++ // differently than the real call_VM ++ Register java_thread = S2thread; ++ if (restore_saved_exception_pc) { ++ __ ldl(RA, java_thread, in_bytes(JavaThread::saved_exception_pc_offset())); ++ } ++ ++ __ enter(); // required for proper stackwalking of RuntimeStub frame ++ ++ __ add_simm16(SP, SP, (-1) * (framesize-2) * wordSize); // prolog ++ __ stl(S0, SP, S0_off * wordSize); ++ __ stl(S1, SP, S1_off * wordSize); ++ __ stl(S2, SP, S2_off * wordSize); ++ __ stl(S3, SP, S3_off * wordSize); ++ __ stl(S4, SP, S4_off * wordSize); ++ __ stl(S5, SP, S5_off * wordSize); ++ ++ int frame_complete = __ pc() - start; ++ // push java thread (becomes first argument of C function) ++ __ stl(java_thread, SP, thread_off * wordSize); ++ if (java_thread != A0) ++ __ move(A0, java_thread); ++ ++ // Set up last_Java_sp and last_Java_fp ++ __ set_last_Java_frame(java_thread, SP, FP, NULL); ++ // Align stack ++ __ set64(AT, -(StackAlignmentInBytes)); ++ __ and_reg(SP, SP, AT); ++ ++#ifdef ZHJ20180909 ++ __ relocate(relocInfo::internal_pc_type); ++ { ++ // patchable_set48 (4) + sd (1) + call ++ intptr_t save_pc = (intptr_t)__ pc() + NativeMovConstReg::instruction_size + NativeCall::return_address_offset + 4; ++ __ patchable_set48(AT, save_pc); ++ } ++#else ++ { ++ if(UseAddpi){ ++ intptr_t patch_off = 1 + (NativeCall::return_address_offset)/BytesPerInstWord; ++ __ addpi(patch_off, AT); ++ }else { ++ intptr_t patch_off = 2 * BytesPerInstWord + NativeCall::return_address_offset; ++ __ br(AT, 0); ++ __ addl(AT, AT, patch_off); ++ } ++ } ++#endif ++ __ stl(AT, java_thread, in_bytes(JavaThread::last_Java_pc_offset())); ++ ++ // Call runtime ++ __ call(runtime_entry); ++ // Generate oop map ++ OopMap* map = new OopMap(framesize, 0); ++ oop_maps->add_gc_map(__ offset() - 4, map); ++ ++ // restore the thread (cannot use the pushed argument since arguments ++ // may be overwritten by C code generated by an optimizing compiler); ++ // however can use the register value directly if it is callee saved. ++ ++ __ ldl(SP, java_thread, in_bytes(JavaThread::last_Java_sp_offset())); ++ __ reset_last_Java_frame(java_thread, true); ++ ++ // Restore callee save registers. This must be done after resetting the Java frame ++ __ ldl(S0, SP, S0_off * wordSize); ++ __ ldl(S1, SP, S1_off * wordSize); ++ __ ldl(S2, SP, S2_off * wordSize); ++ __ ldl(S3, SP, S3_off * wordSize); ++ __ ldl(S4, SP, S4_off * wordSize); ++ __ ldl(S5, SP, S5_off * wordSize); ++ ++ // discard arguments ++ __ add_simm16(SP, SP, (framesize-2) * wordSize); // epilog ++ __ add_simm16(SP, FP, wordSize); ++ __ ldl(FP, SP, -1*wordSize); ++ // check for pending exceptions ++#ifdef ASSERT ++ Label L; ++ __ ldw(AT, java_thread, in_bytes(Thread::pending_exception_offset())); ++ __ bne(AT, L); ++ __ should_not_reach_here(); ++ __ BIND(L); ++#endif //ASSERT ++ __ jmp(StubRoutines::forward_exception_entry(), relocInfo::runtime_call_type); ++ RuntimeStub* stub = RuntimeStub::new_runtime_stub(name, ++ &code, ++ frame_complete, ++ framesize, ++ oop_maps, false); ++ return stub->entry_point(); ++ } ++ ++ // Initialization ++ void generate_initial() { ++ // Generates all stubs and initializes the entry points ++ ++ //------------------------------------------------------------- ++ //----------------------------------------------------------- ++ // entry points that exist in all platforms ++ // Note: This is code that could be shared among different platforms - however the benefit seems to be smaller ++ // than the disadvantage of having a much more complicated generator structure. ++ // See also comment in stubRoutines.hpp. ++ StubRoutines::_forward_exception_entry = generate_forward_exception(); ++ StubRoutines::_call_stub_entry = generate_call_stub(StubRoutines::_call_stub_return_address); ++ // is referenced by megamorphic call ++ StubRoutines::_catch_exception_entry = generate_catch_exception(); ++ ++ StubRoutines::_handler_for_unsafe_access_entry = generate_handler_for_unsafe_access(); ++ ++ StubRoutines::_throw_StackOverflowError_entry = generate_throw_exception("StackOverflowError throw_exception", ++ CAST_FROM_FN_PTR(address, SharedRuntime::throw_StackOverflowError), false); ++ // platform dependent ++ StubRoutines::sw64::_get_previous_fp_entry = generate_get_previous_fp(); ++ ++ if (UseCRC32Intrinsics) { ++ // set table address before stub generation which use it ++ StubRoutines::_crc_table_adr = (address)StubRoutines::sw64::_crc_table; ++ if (UseCRC32) { ++ StubRoutines::_updateBytesCRC32 = generate_updateBytesCRC32(); ++ } else { ++ StubRoutines::_updateBytesCRC32 = CAST_FROM_FN_PTR(address, SharedRuntime::updateBytesCRC32); ++ } ++ } ++ } ++ ++ void generate_all() { ++ // Generates all stubs and initializes the entry points ++ ++ // These entry points require SharedInfo::stack0 to be set up in ++ // non-core builds and need to be relocatable, so they each ++ // fabricate a RuntimeStub internally. ++ StubRoutines::_throw_AbstractMethodError_entry = generate_throw_exception("AbstractMethodError throw_exception", ++ CAST_FROM_FN_PTR(address, SharedRuntime::throw_AbstractMethodError), false); ++ ++ StubRoutines::_throw_IncompatibleClassChangeError_entry = generate_throw_exception("IncompatibleClassChangeError throw_exception", ++ CAST_FROM_FN_PTR(address, SharedRuntime:: throw_IncompatibleClassChangeError), false); ++ ++ StubRoutines::_throw_NullPointerException_at_call_entry = generate_throw_exception("NullPointerException at call throw_exception", ++ CAST_FROM_FN_PTR(address, SharedRuntime::throw_NullPointerException_at_call), false); ++ ++ // entry points that are platform specific ++ ++ // support for verify_oop (must happen after universe_init) ++ StubRoutines::_verify_oop_subroutine_entry = generate_verify_oop(); ++#ifndef CORE ++ // arraycopy stubs used by compilers ++ generate_arraycopy_stubs(); ++#endif ++ ++ // Safefetch stubs. ++ generate_safefetch("SafeFetch32", sizeof(int), &StubRoutines::_safefetch32_entry, ++ &StubRoutines::_safefetch32_fault_pc, ++ &StubRoutines::_safefetch32_continuation_pc); ++ generate_safefetch("SafeFetchN", sizeof(intptr_t), &StubRoutines::_safefetchN_entry, ++ &StubRoutines::_safefetchN_fault_pc, ++ &StubRoutines::_safefetchN_continuation_pc); ++ if (UseMontgomeryMultiplyIntrinsic) { ++ StubRoutines::_montgomeryMultiply ++ = CAST_FROM_FN_PTR(address, SharedRuntime::montgomery_multiply); ++ } ++ if (UseMontgomerySquareIntrinsic) { ++ StubRoutines::_montgomerySquare ++ = CAST_FROM_FN_PTR(address, SharedRuntime::montgomery_square); ++ } ++ ++ } ++ ++ public: ++ StubGenerator(CodeBuffer* code, bool all) : StubCodeGenerator(code) { ++ if (all) { ++ generate_all(); ++ } else { ++ generate_initial(); ++ } ++ } ++}; // end class declaration ++ ++void StubGenerator_generate(CodeBuffer* code, bool all) { ++ StubGenerator g(code, all); ++} +diff --git a/hotspot/src/cpu/sw64/vm/stubRoutines_sw64.cpp b/hotspot/src/cpu/sw64/vm/stubRoutines_sw64.cpp +new file mode 100755 +index 0000000000..b05527f192 +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/stubRoutines_sw64.cpp +@@ -0,0 +1,91 @@ ++/* ++ * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#include "precompiled.hpp" ++#include "runtime/deoptimization.hpp" ++#include "runtime/frame.inline.hpp" ++#include "runtime/stubRoutines.hpp" ++#include "runtime/thread.inline.hpp" ++ ++// a description of how to extend it, see the stubRoutines.hpp file. ++ ++//find the last fp value ++address StubRoutines::sw64::_get_previous_fp_entry = NULL; ++address StubRoutines::sw64::_call_stub_compiled_return = NULL; ++ ++juint StubRoutines::sw64::_crc_table[] = ++{ ++ 0x00000000UL, 0x77073096UL, 0xee0e612cUL, 0x990951baUL, 0x076dc419UL, ++ 0x706af48fUL, 0xe963a535UL, 0x9e6495a3UL, 0x0edb8832UL, 0x79dcb8a4UL, ++ 0xe0d5e91eUL, 0x97d2d988UL, 0x09b64c2bUL, 0x7eb17cbdUL, 0xe7b82d07UL, ++ 0x90bf1d91UL, 0x1db71064UL, 0x6ab020f2UL, 0xf3b97148UL, 0x84be41deUL, ++ 0x1adad47dUL, 0x6ddde4ebUL, 0xf4d4b551UL, 0x83d385c7UL, 0x136c9856UL, ++ 0x646ba8c0UL, 0xfd62f97aUL, 0x8a65c9ecUL, 0x14015c4fUL, 0x63066cd9UL, ++ 0xfa0f3d63UL, 0x8d080df5UL, 0x3b6e20c8UL, 0x4c69105eUL, 0xd56041e4UL, ++ 0xa2677172UL, 0x3c03e4d1UL, 0x4b04d447UL, 0xd20d85fdUL, 0xa50ab56bUL, ++ 0x35b5a8faUL, 0x42b2986cUL, 0xdbbbc9d6UL, 0xacbcf940UL, 0x32d86ce3UL, ++ 0x45df5c75UL, 0xdcd60dcfUL, 0xabd13d59UL, 0x26d930acUL, 0x51de003aUL, ++ 0xc8d75180UL, 0xbfd06116UL, 0x21b4f4b5UL, 0x56b3c423UL, 0xcfba9599UL, ++ 0xb8bda50fUL, 0x2802b89eUL, 0x5f058808UL, 0xc60cd9b2UL, 0xb10be924UL, ++ 0x2f6f7c87UL, 0x58684c11UL, 0xc1611dabUL, 0xb6662d3dUL, 0x76dc4190UL, ++ 0x01db7106UL, 0x98d220bcUL, 0xefd5102aUL, 0x71b18589UL, 0x06b6b51fUL, ++ 0x9fbfe4a5UL, 0xe8b8d433UL, 0x7807c9a2UL, 0x0f00f934UL, 0x9609a88eUL, ++ 0xe10e9818UL, 0x7f6a0dbbUL, 0x086d3d2dUL, 0x91646c97UL, 0xe6635c01UL, ++ 0x6b6b51f4UL, 0x1c6c6162UL, 0x856530d8UL, 0xf262004eUL, 0x6c0695edUL, ++ 0x1b01a57bUL, 0x8208f4c1UL, 0xf50fc457UL, 0x65b0d9c6UL, 0x12b7e950UL, ++ 0x8bbeb8eaUL, 0xfcb9887cUL, 0x62dd1ddfUL, 0x15da2d49UL, 0x8cd37cf3UL, ++ 0xfbd44c65UL, 0x4db26158UL, 0x3ab551ceUL, 0xa3bc0074UL, 0xd4bb30e2UL, ++ 0x4adfa541UL, 0x3dd895d7UL, 0xa4d1c46dUL, 0xd3d6f4fbUL, 0x4369e96aUL, ++ 0x346ed9fcUL, 0xad678846UL, 0xda60b8d0UL, 0x44042d73UL, 0x33031de5UL, ++ 0xaa0a4c5fUL, 0xdd0d7cc9UL, 0x5005713cUL, 0x270241aaUL, 0xbe0b1010UL, ++ 0xc90c2086UL, 0x5768b525UL, 0x206f85b3UL, 0xb966d409UL, 0xce61e49fUL, ++ 0x5edef90eUL, 0x29d9c998UL, 0xb0d09822UL, 0xc7d7a8b4UL, 0x59b33d17UL, ++ 0x2eb40d81UL, 0xb7bd5c3bUL, 0xc0ba6cadUL, 0xedb88320UL, 0x9abfb3b6UL, ++ 0x03b6e20cUL, 0x74b1d29aUL, 0xead54739UL, 0x9dd277afUL, 0x04db2615UL, ++ 0x73dc1683UL, 0xe3630b12UL, 0x94643b84UL, 0x0d6d6a3eUL, 0x7a6a5aa8UL, ++ 0xe40ecf0bUL, 0x9309ff9dUL, 0x0a00ae27UL, 0x7d079eb1UL, 0xf00f9344UL, ++ 0x8708a3d2UL, 0x1e01f268UL, 0x6906c2feUL, 0xf762575dUL, 0x806567cbUL, ++ 0x196c3671UL, 0x6e6b06e7UL, 0xfed41b76UL, 0x89d32be0UL, 0x10da7a5aUL, ++ 0x67dd4accUL, 0xf9b9df6fUL, 0x8ebeeff9UL, 0x17b7be43UL, 0x60b08ed5UL, ++ 0xd6d6a3e8UL, 0xa1d1937eUL, 0x38d8c2c4UL, 0x4fdff252UL, 0xd1bb67f1UL, ++ 0xa6bc5767UL, 0x3fb506ddUL, 0x48b2364bUL, 0xd80d2bdaUL, 0xaf0a1b4cUL, ++ 0x36034af6UL, 0x41047a60UL, 0xdf60efc3UL, 0xa867df55UL, 0x316e8eefUL, ++ 0x4669be79UL, 0xcb61b38cUL, 0xbc66831aUL, 0x256fd2a0UL, 0x5268e236UL, ++ 0xcc0c7795UL, 0xbb0b4703UL, 0x220216b9UL, 0x5505262fUL, 0xc5ba3bbeUL, ++ 0xb2bd0b28UL, 0x2bb45a92UL, 0x5cb36a04UL, 0xc2d7ffa7UL, 0xb5d0cf31UL, ++ 0x2cd99e8bUL, 0x5bdeae1dUL, 0x9b64c2b0UL, 0xec63f226UL, 0x756aa39cUL, ++ 0x026d930aUL, 0x9c0906a9UL, 0xeb0e363fUL, 0x72076785UL, 0x05005713UL, ++ 0x95bf4a82UL, 0xe2b87a14UL, 0x7bb12baeUL, 0x0cb61b38UL, 0x92d28e9bUL, ++ 0xe5d5be0dUL, 0x7cdcefb7UL, 0x0bdbdf21UL, 0x86d3d2d4UL, 0xf1d4e242UL, ++ 0x68ddb3f8UL, 0x1fda836eUL, 0x81be16cdUL, 0xf6b9265bUL, 0x6fb077e1UL, ++ 0x18b74777UL, 0x88085ae6UL, 0xff0f6a70UL, 0x66063bcaUL, 0x11010b5cUL, ++ 0x8f659effUL, 0xf862ae69UL, 0x616bffd3UL, 0x166ccf45UL, 0xa00ae278UL, ++ 0xd70dd2eeUL, 0x4e048354UL, 0x3903b3c2UL, 0xa7672661UL, 0xd06016f7UL, ++ 0x4969474dUL, 0x3e6e77dbUL, 0xaed16a4aUL, 0xd9d65adcUL, 0x40df0b66UL, ++ 0x37d83bf0UL, 0xa9bcae53UL, 0xdebb9ec5UL, 0x47b2cf7fUL, 0x30b5ffe9UL, ++ 0xbdbdf21cUL, 0xcabac28aUL, 0x53b39330UL, 0x24b4a3a6UL, 0xbad03605UL, ++ 0xcdd70693UL, 0x54de5729UL, 0x23d967bfUL, 0xb3667a2eUL, 0xc4614ab8UL, ++ 0x5d681b02UL, 0x2a6f2b94UL, 0xb40bbe37UL, 0xc30c8ea1UL, 0x5a05df1bUL, ++ 0x2d02ef8dUL ++}; +diff --git a/hotspot/src/cpu/sw64/vm/stubRoutines_sw64.hpp b/hotspot/src/cpu/sw64/vm/stubRoutines_sw64.hpp +new file mode 100755 +index 0000000000..d5bdd8f124 +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/stubRoutines_sw64.hpp +@@ -0,0 +1,65 @@ ++/* ++ * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_SW64_VM_STUBROUTINES_SW64_HPP ++#define CPU_SW64_VM_STUBROUTINES_SW64_HPP ++ ++// This file holds the platform specific parts of the StubRoutines ++// definition. See stubRoutines.hpp for a description on how to ++// extend it. ++ ++static bool returns_to_call_stub(address return_pc) { ++ return return_pc == _call_stub_return_address || return_pc == sw64::get_call_stub_compiled_return(); ++} ++ ++enum platform_dependent_constants { ++ code_size1 = 20000, // simply increase if too small (assembler will crash if too small) ++ code_size2 = 40000 // simply increase if too small (assembler will crash if too small) ++}; ++ ++class sw64 { ++ friend class StubGenerator; ++ friend class VMStructs; ++ private: ++ // If we call compiled code directly from the call stub we will ++ // need to adjust the return back to the call stub to a specialized ++ // piece of code that can handle compiled results and cleaning the fpu ++ // stack. The variable holds that location. ++ static address _call_stub_compiled_return; ++ static address _get_previous_fp_entry; ++ static address _verify_mxcsr_entry; ++ // shuffle mask for fixing up 128-bit words consisting of big-endian 32-bit integers ++ static address _key_shuffle_mask_addr; ++ // masks and table for CRC32 ++ static uint64_t _crc_by128_masks[]; ++ static juint _crc_table[]; ++public: ++ // Call back points for traps in compiled code ++ static address get_previous_fp_entry() { return _get_previous_fp_entry; } ++ static address get_call_stub_compiled_return() { return _call_stub_compiled_return; } ++ static void set_call_stub_compiled_return(address ret) { _call_stub_compiled_return = ret; } ++ ++}; ++ ++#endif // CPU_SW64_VM_STUBROUTINES_SW64_HPP +diff --git a/hotspot/src/cpu/sw64/vm/sw64.ad b/hotspot/src/cpu/sw64/vm/sw64.ad +new file mode 100755 +index 0000000000..70acb68887 +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/sw64.ad +@@ -0,0 +1,13510 @@ ++// ++// Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. ++// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++// ++// This code is free software; you can redistribute it and/or modify it ++// under the terms of the GNU General Public License version 2 only, as ++// published by the Free Software Foundation. ++// ++// This code is distributed in the hope that it will be useful, but WITHOUT ++// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// version 2 for more details (a copy is included in the LICENSE file that ++// accompanied this code). ++// ++// You should have received a copy of the GNU General Public License version ++// 2 along with this work; if not, write to the Free Software Foundation, ++// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++// ++// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++// or visit www.oracle.com if you need additional information or have any ++// questions. ++// ++// ++ ++// SW64 Architecture Description File ++ ++//----------REGISTER DEFINITION BLOCK------------------------------------------ ++// This information is used by the matcher and the register allocator to ++// describe individual registers and classes of registers within the target ++// archtecture. ++ ++// format: ++// reg_def name (call convention, c-call convention, ideal type, encoding); ++// call convention : ++// NS = No-Save ++// SOC = Save-On-Call ++// SOE = Save-On-Entry ++// AS = Always-Save ++// ideal type : ++// see opto/opcodes.hpp for more info ++// reg_class name (reg, ...); ++// alloc_class name (reg, ...); ++ ++register %{ ++ ++// General Registers ++// Integer Registers ++reg_def V0 (SOC, SOC, Op_RegI, 0, V0->as_VMReg()); ++reg_def V0_H (SOC, SOC, Op_RegI, 0, V0->as_VMReg()->next()); ++ ++reg_def T0 (SOC, SOC, Op_RegI, 1, T0->as_VMReg()); ++reg_def T0_H (SOC, SOC, Op_RegI, 1, T0->as_VMReg()->next()); ++reg_def T1 (SOC, SOC, Op_RegI, 2, T1->as_VMReg()); ++reg_def T1_H (SOC, SOC, Op_RegI, 2, T1->as_VMReg()->next()); ++reg_def T2 (SOC, SOC, Op_RegI, 3, T2->as_VMReg()); ++reg_def T2_H (SOC, SOC, Op_RegI, 3, T2->as_VMReg()->next()); ++reg_def T3 (SOC, SOC, Op_RegI, 4, T3->as_VMReg()); ++reg_def T3_H (SOC, SOC, Op_RegI, 4, T3->as_VMReg()->next()); ++reg_def T4 (SOC, SOC, Op_RegI, 5, T4->as_VMReg()); ++reg_def T4_H (SOC, SOC, Op_RegI, 5, T4->as_VMReg()->next()); ++reg_def T5 (SOC, SOC, Op_RegI, 6, T5->as_VMReg()); ++reg_def T5_H (SOC, SOC, Op_RegI, 6, T5->as_VMReg()->next()); ++reg_def T6 (SOC, SOC, Op_RegI, 7, T6->as_VMReg()); ++reg_def T6_H (SOC, SOC, Op_RegI, 7, T6->as_VMReg()->next()); ++reg_def T7 (SOC, SOC, Op_RegI, 8, T7->as_VMReg()); ++reg_def T7_H (SOC, SOC, Op_RegI, 8, T7->as_VMReg()->next()); ++ ++reg_def S0 (SOC, SOE, Op_RegI, 9, S0->as_VMReg()); ++reg_def S0_H (SOC, SOE, Op_RegI, 9, S0->as_VMReg()->next()); ++reg_def S1 (SOC, SOE, Op_RegI, 10, S1->as_VMReg()); ++reg_def S1_H (SOC, SOE, Op_RegI, 10, S1->as_VMReg()->next()); ++reg_def S2 (SOC, SOE, Op_RegI, 11, S2->as_VMReg()); ++reg_def S2_H (SOC, SOE, Op_RegI, 11, S2->as_VMReg()->next()); ++reg_def S3 (SOC, SOE, Op_RegI, 12, S3->as_VMReg()); ++reg_def S3_H (SOC, SOE, Op_RegI, 12, S3->as_VMReg()->next()); ++reg_def S4 (SOC, SOE, Op_RegI, 13, S4->as_VMReg()); ++reg_def S4_H (SOC, SOE, Op_RegI, 13, S4->as_VMReg()->next()); ++reg_def S5 (SOC, SOE, Op_RegI, 14, S5->as_VMReg()); ++reg_def S5_H (SOC, SOE, Op_RegI, 14, S5->as_VMReg()->next()); ++reg_def FP ( NS, NS, Op_RegI, 15, FP->as_VMReg()); ++reg_def FP_H ( NS, NS, Op_RegI, 15, FP->as_VMReg()->next()); ++ ++reg_def A0 (SOC, SOC, Op_RegI, 16, A0->as_VMReg()); ++reg_def A0_H (SOC, SOC, Op_RegI, 16, A0->as_VMReg()->next()); ++reg_def A1 (SOC, SOC, Op_RegI, 17, A1->as_VMReg()); ++reg_def A1_H (SOC, SOC, Op_RegI, 17, A1->as_VMReg()->next()); ++reg_def A2 (SOC, SOC, Op_RegI, 18, A2->as_VMReg()); ++reg_def A2_H (SOC, SOC, Op_RegI, 18, A2->as_VMReg()->next()); ++reg_def A3 (SOC, SOC, Op_RegI, 19, A3->as_VMReg()); ++reg_def A3_H (SOC, SOC, Op_RegI, 19, A3->as_VMReg()->next()); ++reg_def A4 (SOC, SOC, Op_RegI, 20, A4->as_VMReg()); ++reg_def A4_H (SOC, SOC, Op_RegI, 20, A4->as_VMReg()->next()); ++reg_def A5 (SOC, SOC, Op_RegI, 21, A5->as_VMReg()); ++reg_def A5_H (SOC, SOC, Op_RegI, 21, A5->as_VMReg()->next()); ++ ++reg_def T8 (SOC, SOC, Op_RegI, 22, T8->as_VMReg()); ++reg_def T8_H (SOC, SOC, Op_RegI, 22, T8->as_VMReg()->next()); ++reg_def T9 (SOC, SOC, Op_RegI, 23, T9->as_VMReg()); ++reg_def T9_H (SOC, SOC, Op_RegI, 23, T9->as_VMReg()->next()); ++reg_def T10 (SOC, SOC, Op_RegI, 24, T10->as_VMReg()); ++reg_def T10_H (SOC, SOC, Op_RegI, 24, T10->as_VMReg()->next()); ++reg_def T11 (SOC, SOC, Op_RegI, 25, T11->as_VMReg()); ++reg_def T11_H (SOC, SOC, Op_RegI, 25, T11->as_VMReg()->next()); ++reg_def RA ( NS, NS, Op_RegI, 26, RA->as_VMReg()); ++reg_def RA_H ( NS, NS, Op_RegI, 26, RA->as_VMReg()->next()); ++reg_def T12 (SOC, SOC, Op_RegI, 27, T12->as_VMReg()); ++reg_def T12_H (SOC, SOC, Op_RegI, 27, T12->as_VMReg()->next()); ++reg_def AT ( NS, NS, Op_RegI, 28, AT->as_VMReg()); ++reg_def AT_H ( NS, NS, Op_RegI, 28, AT->as_VMReg()->next()); ++reg_def GP ( NS, NS, Op_RegI, 29, GP->as_VMReg()); ++reg_def GP_H ( NS, NS, Op_RegI, 29, GP->as_VMReg()->next()); ++reg_def SP ( NS, NS, Op_RegI, 30, SP->as_VMReg()); ++reg_def SP_H ( NS, NS, Op_RegI, 30, SP->as_VMReg()->next()); ++reg_def R0 ( NS, NS, Op_RegI, 31, VMRegImpl::Bad()); ++ ++// Floating registers. ++reg_def F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg()); ++reg_def F0_H ( SOC, SOC, Op_RegF, 0, F0->as_VMReg()->next()); ++reg_def F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg()); ++reg_def F1_H ( SOC, SOC, Op_RegF, 1, F1->as_VMReg()->next()); ++reg_def F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg()); ++reg_def F2_H ( SOC, SOC, Op_RegF, 2, F2->as_VMReg()->next()); ++reg_def F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg()); ++reg_def F3_H ( SOC, SOC, Op_RegF, 3, F3->as_VMReg()->next()); ++reg_def F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg()); ++reg_def F4_H ( SOC, SOC, Op_RegF, 4, F4->as_VMReg()->next()); ++reg_def F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg()); ++reg_def F5_H ( SOC, SOC, Op_RegF, 5, F5->as_VMReg()->next()); ++reg_def F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg()); ++reg_def F6_H ( SOC, SOC, Op_RegF, 6, F6->as_VMReg()->next()); ++reg_def F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg()); ++reg_def F7_H ( SOC, SOC, Op_RegF, 7, F7->as_VMReg()->next()); ++reg_def F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg()); ++reg_def F8_H ( SOC, SOC, Op_RegF, 8, F8->as_VMReg()->next()); ++reg_def F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg()); ++reg_def F9_H ( SOC, SOC, Op_RegF, 9, F9->as_VMReg()->next()); ++reg_def F10 ( SOC, SOC, Op_RegF, 10, F10->as_VMReg()); ++reg_def F10_H ( SOC, SOC, Op_RegF, 10, F10->as_VMReg()->next()); ++reg_def F11 ( SOC, SOC, Op_RegF, 11, F11->as_VMReg()); ++reg_def F11_H ( SOC, SOC, Op_RegF, 11, F11->as_VMReg()->next()); ++reg_def F12 ( SOC, SOC, Op_RegF, 12, F12->as_VMReg()); ++reg_def F12_H ( SOC, SOC, Op_RegF, 12, F12->as_VMReg()->next()); ++reg_def F13 ( SOC, SOC, Op_RegF, 13, F13->as_VMReg()); ++reg_def F13_H ( SOC, SOC, Op_RegF, 13, F13->as_VMReg()->next()); ++reg_def F14 ( SOC, SOC, Op_RegF, 14, F14->as_VMReg()); ++reg_def F14_H ( SOC, SOC, Op_RegF, 14, F14->as_VMReg()->next()); ++reg_def F15 ( SOC, SOC, Op_RegF, 15, F15->as_VMReg()); ++reg_def F15_H ( SOC, SOC, Op_RegF, 15, F15->as_VMReg()->next()); ++reg_def F16 ( SOC, SOC, Op_RegF, 16, F16->as_VMReg()); ++reg_def F16_H ( SOC, SOC, Op_RegF, 16, F16->as_VMReg()->next()); ++reg_def F17 ( SOC, SOC, Op_RegF, 17, F17->as_VMReg()); ++reg_def F17_H ( SOC, SOC, Op_RegF, 17, F17->as_VMReg()->next()); ++reg_def F18 ( SOC, SOC, Op_RegF, 18, F18->as_VMReg()); ++reg_def F18_H ( SOC, SOC, Op_RegF, 18, F18->as_VMReg()->next()); ++reg_def F19 ( SOC, SOC, Op_RegF, 19, F19->as_VMReg()); ++reg_def F19_H ( SOC, SOC, Op_RegF, 19, F19->as_VMReg()->next()); ++reg_def F20 ( SOC, SOC, Op_RegF, 20, F20->as_VMReg()); ++reg_def F20_H ( SOC, SOC, Op_RegF, 20, F20->as_VMReg()->next()); ++reg_def F21 ( SOC, SOC, Op_RegF, 21, F21->as_VMReg()); ++reg_def F21_H ( SOC, SOC, Op_RegF, 21, F21->as_VMReg()->next()); ++reg_def F22 ( SOC, SOC, Op_RegF, 22, F22->as_VMReg()); ++reg_def F22_H ( SOC, SOC, Op_RegF, 22, F22->as_VMReg()->next()); ++reg_def F23 ( SOC, SOC, Op_RegF, 23, F23->as_VMReg()); ++reg_def F23_H ( SOC, SOC, Op_RegF, 23, F23->as_VMReg()->next()); ++reg_def F24 ( SOC, SOC, Op_RegF, 24, F24->as_VMReg()); ++reg_def F24_H ( SOC, SOC, Op_RegF, 24, F24->as_VMReg()->next()); ++reg_def F25 ( SOC, SOC, Op_RegF, 25, F25->as_VMReg()); ++reg_def F25_H ( SOC, SOC, Op_RegF, 25, F25->as_VMReg()->next()); ++reg_def F26 ( SOC, SOC, Op_RegF, 26, F26->as_VMReg()); ++reg_def F26_H ( SOC, SOC, Op_RegF, 26, F26->as_VMReg()->next()); ++reg_def F27 ( SOC, SOC, Op_RegF, 27, F27->as_VMReg()); ++reg_def F27_H ( SOC, SOC, Op_RegF, 27, F27->as_VMReg()->next()); ++reg_def F28 ( SOC, SOC, Op_RegF, 28, F28->as_VMReg()); ++reg_def F28_H ( SOC, SOC, Op_RegF, 28, F28->as_VMReg()->next()); ++reg_def F29 ( SOC, SOC, Op_RegF, 29, F29->as_VMReg()); ++reg_def F29_H ( SOC, SOC, Op_RegF, 29, F29->as_VMReg()->next()); ++reg_def F30 ( SOC, SOC, Op_RegF, 30, F30->as_VMReg()); ++reg_def F30_H ( SOC, SOC, Op_RegF, 30, F30->as_VMReg()->next()); ++reg_def F31 ( SOC, SOC, Op_RegF, 31, F31->as_VMReg()); ++reg_def F31_H ( SOC, SOC, Op_RegF, 31, F31->as_VMReg()->next()); ++ ++ ++// ---------------------------- ++// Special Registers ++// Condition Codes Flag Registers ++reg_def SW64_FLAG (SOC, SOC, Op_RegFlags, 1, as_Register(1)->as_VMReg()); ++ ++//S2 is used for get_thread(S2) ++//S5 is uesd for heapbase of compressed oop ++alloc_class chunk0( ++ S0, S0_H, ++ S1, S1_H, ++ S3, S3_H, ++ S4, S4_H, ++ S5, S5_H, ++ S2, S2_H, ++ T2, T2_H, ++ T3, T3_H, ++ T11, T11_H, ++ T12, T12_H, ++ T1, T1_H, // inline_cache_reg ++ A5, A5_H, ++ A4, A4_H, ++ V0, V0_H, ++ A3, A3_H, ++ A2, A2_H, ++ A1, A1_H, ++ A0, A0_H, ++ T0, T0_H, ++ T4, T4_H, ++ T5, T5_H, ++ T6, T6_H, ++ T7, T7_H, ++ T8, T8_H, ++ T9, T9_H, ++ T10, T10_H, ++ GP, GP_H ++ RA, RA_H, ++ SP, SP_H, // stack_pointer ++ FP, FP_H // frame_pointer ++ ); ++ ++alloc_class chunk1( F0, F0_H, ++ F1, F1_H, ++ F2, F2_H, ++ F3, F3_H, ++ F4, F4_H, ++ F5, F5_H, ++ F6, F6_H, ++ F7, F7_H, ++ F8, F8_H, ++ F9, F9_H, ++ F10, F10_H, ++ F11, F11_H, ++ F20, F20_H, ++ F21, F21_H, ++ F22, F22_H, ++ F23, F23_H, ++ F24, F24_H, ++ F25, F25_H, ++ F26, F26_H, ++ F27, F27_H, ++ F28, F28_H, ++ F19, F19_H, ++ F18, F18_H, ++ F17, F17_H, ++ F16, F16_H, ++ F15, F15_H, ++ F14, F14_H, ++ F13, F13_H, ++ F12, F12_H, ++ F29, F29_H, ++ F30, F30_H, ++ F31, F31_H); ++ ++alloc_class chunk2(SW64_FLAG); ++ ++reg_class s_reg( S0, S1, S2, S3, S4, S5 ); ++reg_class s0_reg( S0 ); ++reg_class s1_reg( S1 ); ++reg_class s2_reg( S2 ); ++reg_class s3_reg( S3 ); ++reg_class s4_reg( S4 ); ++reg_class s5_reg( S5 ); ++ ++reg_class t_reg( T0, T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12 ); ++reg_class t0_reg( T0 ); ++reg_class t1_reg( T1 ); ++reg_class t2_reg( T2 ); ++reg_class t3_reg( T3 ); ++reg_class t4_reg( T4 ); ++reg_class t5_reg( T5 ); ++reg_class t6_reg( T6 ); ++reg_class t7_reg( T7 ); ++reg_class t8_reg( T8 ); ++reg_class t9_reg( T9 ); ++reg_class t10_reg( T10 ); ++reg_class t11_reg( T11 ); ++reg_class t12_reg( T12 ); ++ ++reg_class a_reg( A0, A1, A2, A3, A4, A5 ); ++reg_class a0_reg( A0 ); ++reg_class a1_reg( A1 ); ++reg_class a2_reg( A2 ); ++reg_class a3_reg( A3 ); ++reg_class a4_reg( A4 ); ++reg_class a5_reg( A5 ); ++ ++reg_class v0_reg( V0 ); ++ ++reg_class sp_reg( SP, SP_H ); ++reg_class fp_reg( FP, FP_H ); ++ ++reg_class sw64_flags(SW64_FLAG); ++ ++reg_class v0_long_reg( V0, V0_H ); ++ ++reg_class t0_long_reg( T0, T0_H ); ++reg_class t1_long_reg( T1, T1_H ); ++reg_class t2_long_reg( T2, T2_H ); ++reg_class t3_long_reg( T3, T3_H ); ++reg_class t4_long_reg( T4, T4_H ); ++reg_class t5_long_reg( T5, T5_H ); ++reg_class t6_long_reg( T6, T6_H ); ++reg_class t7_long_reg( T7, T7_H ); ++reg_class t8_long_reg( T8, T8_H ); ++reg_class t9_long_reg( T9, T9_H ); ++reg_class t10_long_reg( T10, T10_H ); ++reg_class t11_long_reg( T11, T11_H ); ++reg_class t12_long_reg( T12, T12_H ); ++ ++reg_class a0_long_reg( A0, A0_H ); ++reg_class a1_long_reg( A1, A1_H ); ++reg_class a2_long_reg( A2, A2_H ); ++reg_class a3_long_reg( A3, A3_H ); ++reg_class a4_long_reg( A4, A4_H ); ++reg_class a5_long_reg( A5, A5_H ); ++ ++reg_class s0_long_reg( S0, S0_H ); ++reg_class s1_long_reg( S1, S1_H ); ++reg_class s2_long_reg( S2, S2_H ); ++reg_class s3_long_reg( S3, S3_H ); ++reg_class s4_long_reg( S4, S4_H ); ++reg_class s5_long_reg( S5, S5_H ); ++ ++reg_class int_reg( S1, S0, S4, S3, T11, T2, T3, T1, A5, A4, V0, A3, A2, A1, A0, T0, T4, T5, T6, T7, T8, T9, T10 ); ++ ++reg_class no_Ax_int_reg( S1, S0, S4, S3, T11, T2, T3, T1, V0, T0, T4, T5, T6, T7, T8, T9, T10 ); ++ ++reg_class p_reg( ++ S1, S1_H, ++ S0, S0_H, ++ S4, S4_H, ++ S3, S3_H, ++ T11, T11_H, ++ T2, T2_H, ++ T3, T3_H, ++ T1, T1_H, ++ A5, A5_H, ++ A4, A4_H, ++ A3, A3_H, ++ A2, A2_H, ++ A1, A1_H, ++ A0, A0_H, ++ T0, T0_H, ++ T4, T4_H, ++ T5, T5_H, ++ T6, T6_H, ++ T7, T7_H, ++ T8, T8_H, ++ T9, T9_H, ++ T10, T10_H ++ ); ++ ++reg_class no_T11_p_reg( ++ S1, S1_H, ++ S0, S0_H, ++ S4, S4_H, ++ S3, S3_H, ++ T2, T2_H, ++ T3, T3_H, ++ T1, T1_H, ++ A5, A5_H, ++ A4, A4_H, ++ A3, A3_H, ++ A2, A2_H, ++ A1, A1_H, ++ A0, A0_H, ++ T0, T0_H, ++ T4, T4_H, ++ T5, T5_H, ++ T6, T6_H, ++ T7, T7_H, ++ T8, T8_H, ++ T9, T9_H, ++ T10, T10_H ++ ); ++ ++reg_class long_reg( ++ S1, S1_H, ++ S0, S0_H, ++ S4, S4_H, ++ S3, S3_H, ++ T11, T11_H, ++ T2, T2_H, ++ T3, T3_H, ++ T1, T1_H, ++ A5, A5_H, ++ A4, A4_H, ++ A3, A3_H, ++ A2, A2_H, ++ A1, A1_H, ++ A0, A0_H, ++ T0, T0_H, ++ T4, T4_H, ++ T5, T5_H, ++ T6, T6_H, ++ T7, T7_H, ++ T8, T8_H, ++ T9, T9_H, ++ T10, T10_H ++ ); ++ ++ ++// Floating point registers. ++// 2012/8/23 Fu: F30/F31 are used as temporary registers in D2I ++//2017/9/6 zyh: F28&F29 are used as temporary registers in float cmp instructs ++reg_class flt_reg( F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15, F16, F17 F18, F19, F20, F21, F22, F23, F24, F25, F26, F27); ++reg_class dbl_reg( F0, F0_H, ++ F1, F1_H, ++ F2, F2_H, ++ F3, F3_H, ++ F4, F4_H, ++ F5, F5_H, ++ F6, F6_H, ++ F7, F7_H, ++ F8, F8_H, ++ F9, F9_H, ++ F10, F10_H, ++ F11, F11_H, ++ F12, F12_H, ++ F13, F13_H, ++ F14, F14_H, ++ F15, F15_H, ++ F16, F16_H, ++ F17, F17_H, ++ F18, F18_H, ++ F19, F19_H, ++ F20, F20_H, ++ F21, F21_H, ++ F22, F22_H, ++ F23, F23_H, ++ F24, F24_H, ++ F25, F25_H, ++ F26, F26_H, ++ F27, F27_H, ++// F28, F28_H, ++// F29, F29_H ++ ); ++ ++reg_class flt_arg0( F16 ); ++reg_class dbl_arg0( F16, F16_H ); ++reg_class dbl_arg1( F17, F17_H ); ++ ++%} ++ ++//----------DEFINITION BLOCK--------------------------------------------------- ++// Define name --> value mappings to inform the ADLC of an integer valued name ++// Current support includes integer values in the range [0, 0x7FFFFFFF] ++// Format: ++// int_def ( , ); ++// Generated Code in ad_.hpp ++// #define () ++// // value == ++// Generated code in ad_.cpp adlc_verification() ++// assert( == , "Expect () to equal "); ++// ++definitions %{ ++ int_def DEFAULT_COST ( 100, 100); ++ int_def HUGE_COST (1000000, 1000000); ++ ++ // Memory refs are twice as expensive as run-of-the-mill. ++ int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2); ++ ++ // Branches are even more expensive. ++ int_def BRANCH_COST ( 300, DEFAULT_COST * 3); ++ // we use jr instruction to construct call, so more expensive ++ int_def CALL_COST ( 500, DEFAULT_COST * 5); ++%} ++ ++ ++ ++//----------SOURCE BLOCK------------------------------------------------------- ++// This is a block of C++ code which provides values, functions, and ++// definitions necessary in the rest of the architecture description ++ ++source_hpp %{ ++// Header information of the source block. ++// Method declarations/definitions which are used outside ++// the ad-scope can conveniently be defined here. ++// ++// To keep related declarations/definitions/uses close together, ++// we switch between source %{ }% and source_hpp %{ }% freely as needed. ++ ++class CallStubImpl { ++ ++ //-------------------------------------------------------------- ++ //---< Used for optimization in Compile::shorten_branches >--- ++ //-------------------------------------------------------------- ++ ++ public: ++ // Size of call trampoline stub. ++ static uint size_call_trampoline() { ++ return 0; // no call trampolines on this platform ++ } ++ ++ // number of relocations needed by a call trampoline stub ++ static uint reloc_call_trampoline() { ++ return 0; // no call trampolines on this platform ++ } ++}; ++ ++class HandlerImpl { ++ ++ public: ++ ++ static int emit_exception_handler(CodeBuffer &cbuf); ++ static int emit_deopt_handler(CodeBuffer& cbuf); ++ ++ static uint size_exception_handler() { ++ // NativeCall instruction size is the same as NativeJump. ++ // exception handler starts out as jump and can be patched to ++ // a call be deoptimization. (4932387) ++ // Note that this value is also credited (in output.cpp) to ++ // the size of the code section. ++ int size = NativeCall::instruction_size; ++ return round_to(size, 16); ++ } ++ ++ static uint size_deopt_handler() { ++ int size = NativeCall::instruction_size; ++ return round_to(size, 16); ++ } ++}; ++ ++ bool is_CAS(int opcode); ++ bool unnecessary_release(const Node *barrier); ++ // predicate controlling translation of StoreCM ++ bool unnecessary_storestore(const Node *storecm); ++ ++%} // end source_hpp ++ ++source %{ ++ ++#define NO_INDEX 0 ++#define RELOC_IMM64 Assembler::imm_operand ++#define RELOC_DISP32 Assembler::disp32_operand ++ ++ ++#define __ _masm. ++ ++#ifdef PRODUCT ++#define BLOCK_COMMENT(str) /* nothing */ ++#else ++#define BLOCK_COMMENT(str) { char line[1024];sprintf(line,"%s:%s:%d",str,__FILE__, __LINE__); __ block_comment(line);} ++#endif ++ ++#define BIND(label) bind(label); BLOCK_COMMENT(#label ":") ++ ++// Emit exception handler code. ++// Stuff framesize into a register and call a VM stub routine. ++int HandlerImpl::emit_exception_handler(CodeBuffer& cbuf) { ++ // Note that the code buffer's insts_mark is always relative to insts. ++ // That's why we must use the macroassembler to generate a handler. ++ MacroAssembler _masm(&cbuf); ++ address base = __ start_a_stub(size_exception_handler()); ++ if (base == NULL) { ++ ciEnv::current()->record_failure("CodeCache is full"); ++ return 0; // CodeBuffer::expand failed ++ } ++ ++ int offset = __ offset(); ++ ++ __ block_comment("; emit_exception_handler"); ++ ++ cbuf.set_insts_mark(); ++ __ relocate(relocInfo::runtime_call_type); ++ __ patchable_jump((address)OptoRuntime::exception_blob()->entry_point()); ++ __ align(16); ++ assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); ++ __ end_a_stub(); ++ return offset; ++} ++ ++// Emit deopt handler code. ++int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) { ++ // Note that the code buffer's insts_mark is always relative to insts. ++ // That's why we must use the macroassembler to generate a handler. ++ MacroAssembler _masm(&cbuf); ++ address base = __ start_a_stub(size_deopt_handler()); ++ if (base == NULL) { ++ ciEnv::current()->record_failure("CodeCache is full"); ++ return 0; // CodeBuffer::expand failed ++ } ++ ++ int offset = __ offset(); ++ ++ __ block_comment("; emit_deopt_handler"); ++ ++ cbuf.set_insts_mark(); ++ __ relocate(relocInfo::runtime_call_type); ++ __ patchable_call_setfpec1(SharedRuntime::deopt_blob()->unpack()); ++ __ align(16); ++ assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); ++ __ end_a_stub(); ++ return offset; ++} ++ ++ ++const bool Matcher::match_rule_supported(int opcode) { ++ if (!has_match_rule(opcode)) ++ return false; ++ ++ switch (opcode) { ++ case Op_CountLeadingZerosI: ++ case Op_CountLeadingZerosL: ++ if (!UseCountLeadingZerosInstruction) ++ return false; ++ break; ++ case Op_CountTrailingZerosI: ++ case Op_CountTrailingZerosL: ++ if (!UseCountTrailingZerosInstruction) ++ return false; ++ break; ++ } ++ ++ return true; // Per default match rules are supported. ++} ++ ++// emit call stub, compiled java to interpreter ++void emit_java_to_interp(CodeBuffer &cbuf ) { ++ // Stub is fixed up when the corresponding call is converted from calling ++ // compiled code to calling interpreted code. ++ // mov S3,0 ++ // jmp -1 ++ ++ address mark = cbuf.insts_mark(); // get mark within main instrs section ++ ++ // Note that the code buffer's insts_mark is always relative to insts. ++ // That's why we must use the macroassembler to generate a stub. ++ MacroAssembler _masm(&cbuf); ++ ++ address base = __ start_a_stub(Compile::MAX_stubs_size); ++ if (base == NULL) { // CodeBuffer::expand failed ++ ciEnv::current()->record_failure("CodeCache is full"); ++ } ++ ++ // static stub relocation stores the instruction address of the call ++ ++ __ relocate(static_stub_Relocation::spec(mark), 0); ++ ++ // static stub relocation also tags the methodOop in the code-stream. ++ __ patchable_set48(S3, (long)0); ++ // This is recognized as unresolved by relocs/nativeInst/ic code ++ ++ __ relocate(relocInfo::runtime_call_type); ++ ++ cbuf.set_insts_mark(); ++ address call_pc = (address)-1; ++ __ patchable_jump(call_pc); ++ __ align(16); ++ __ end_a_stub(); ++ // Update current stubs pointer and restore code_end. ++} ++ ++// size of call stub, compiled java to interpretor ++uint size_java_to_interp() { ++ int size = 4 * 4 + NativeCall::instruction_size; // sizeof(li48) + NativeCall::instruction_size ++ return round_to(size, 16); ++} ++ ++// relocation entries for call stub, compiled java to interpreter ++uint reloc_java_to_interp() { ++ return 16; // in emit_java_to_interp + in Java_Static_Call ++} ++ ++bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) { ++ int offs = offset - br_size + 4; ++ // To be conservative on SW64 ++ // branch node should be end with branch inst ++ const int safety_zone = 3 * BytesPerInstWord; ++ return Assembler::is_simm16((offs<0 ? offs-safety_zone : offs+safety_zone) >> 2); ++ } ++ ++ ++// No additional cost for CMOVL. ++const int Matcher::long_cmove_cost() { return 0; } ++ ++// No CMOVF/CMOVD with SSE2 ++const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; } ++ ++// Does the CPU require late expand (see block.cpp for description of late expand)? ++const bool Matcher::require_postalloc_expand = false; ++ ++// Should the Matcher clone shifts on addressing modes, expecting them ++// to be subsumed into complex addressing expressions or compute them ++// into registers? True for Intel but false for most RISCs ++const bool Matcher::clone_shift_expressions = false; ++ ++// Do we need to mask the count passed to shift instructions or does ++// the cpu only look at the lower 5/6 bits anyway? ++const bool Matcher::need_masked_shift_count = false; ++ ++bool Matcher::narrow_oop_use_complex_address() { ++ NOT_LP64(ShouldNotCallThis()); ++ assert(UseCompressedOops, "only for compressed oops code"); ++ return false; ++} ++ ++bool Matcher::narrow_klass_use_complex_address() { ++ NOT_LP64(ShouldNotCallThis()); ++ assert(UseCompressedClassPointers, "only for compressed klass code"); ++ return false; ++} ++ ++// This is UltraSparc specific, true just means we have fast l2f conversion ++const bool Matcher::convL2FSupported(void) { ++ return true; ++} ++ ++// Max vector size in bytes. 0 if not supported. ++const int Matcher::vector_width_in_bytes(BasicType bt) { ++ if (MaxVectorSize == 0) ++ return 0; ++ assert(MaxVectorSize == 8, ""); ++ return 8; ++} ++ ++// Vector ideal reg ++const uint Matcher::vector_ideal_reg(int size) { ++ assert(MaxVectorSize == 8, ""); ++ switch(size) { ++ case 8: return Op_VecD; ++ } ++ ShouldNotReachHere(); ++ return 0; ++} ++ ++// Only lowest bits of xmm reg are used for vector shift count. ++const uint Matcher::vector_shift_count_ideal_reg(int size) { ++ fatal("vector shift is not supported"); ++ return Node::NotAMachineReg; ++} ++ ++// Limits on vector size (number of elements) loaded into vector. ++const int Matcher::max_vector_size(const BasicType bt) { ++ assert(is_java_primitive(bt), "only primitive type vectors"); ++ return vector_width_in_bytes(bt)/type2aelembytes(bt); ++} ++ ++const int Matcher::min_vector_size(const BasicType bt) { ++ return max_vector_size(bt); // Same as max. ++} ++ ++// SW64 supports misaligned vectors store/load ++const bool Matcher::misaligned_vectors_ok() { ++ return false; ++} ++ ++// Register for DIVI projection of divmodI ++RegMask Matcher::divI_proj_mask() { ++ ShouldNotReachHere(); ++ return RegMask(); ++} ++ ++// Register for MODI projection of divmodI ++RegMask Matcher::modI_proj_mask() { ++ ShouldNotReachHere(); ++ return RegMask(); ++} ++ ++// Register for DIVL projection of divmodL ++RegMask Matcher::divL_proj_mask() { ++ ShouldNotReachHere(); ++ return RegMask(); ++} ++ ++int Matcher::regnum_to_fpu_offset(int regnum) { ++ return regnum - 32; // The FP registers are in the second chunk ++} ++ ++ ++const bool Matcher::isSimpleConstant64(jlong value) { ++ // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. ++ return true; ++} ++ ++ // is_CAS(int opcode) ++ // ++ // return true if opcode is one of the possible CompareAndSwapX ++ // values otherwise false. ++ ++bool is_CAS(int opcode) ++{ ++ switch(opcode) { ++ // We handle these ++ case Op_CompareAndSwapI: ++ case Op_CompareAndSwapL: ++ case Op_CompareAndSwapP: ++ case Op_CompareAndSwapN: ++ case Op_GetAndSetI: ++ case Op_GetAndSetL: ++ case Op_GetAndSetP: ++ case Op_GetAndSetN: ++ case Op_GetAndAddI: ++ case Op_GetAndAddL: ++ return true; ++ default: ++ return false; ++ } ++} ++ ++bool unnecessary_release(const Node *n) ++{ ++ assert((n->is_MemBar() && ++ n->Opcode() == Op_MemBarRelease), ++ "expecting a release membar"); ++ ++ MemBarNode *barrier = n->as_MemBar(); ++ ++ if (!barrier->leading()) { ++ return false; ++ } else { ++ Node* trailing = barrier->trailing_membar(); ++ MemBarNode* trailing_mb = trailing->as_MemBar(); ++ assert(trailing_mb->trailing(), "Not a trailing membar?"); ++ assert(trailing_mb->leading_membar() == n, "inconsistent leading/trailing membars"); ++ ++ Node* mem = trailing_mb->in(MemBarNode::Precedent); ++ if (!mem->is_Store()) { ++ assert(mem->is_LoadStore(), ""); ++ assert(trailing_mb->Opcode() == Op_MemBarAcquire, ""); ++ return is_CAS(mem->Opcode()); ++ } ++ } ++ ++ return false; ++} ++ ++bool unnecessary_storestore(const Node *storecm) ++{ ++ assert(storecm->Opcode() == Op_StoreCM, "expecting a StoreCM"); ++ // we need to generate a dmb ishst between an object put and the ++ // associated card mark when we are using CMS without conditional ++ // card marking ++ if (UseConcMarkSweepGC && !UseCondCardMark) { ++ return false; ++ } ++ // a storestore is unnecesary in all other cases ++ return true; ++} ++ ++// Return whether or not this register is ever used as an argument. This ++// function is used on startup to build the trampoline stubs in generateOptoStub. ++// Registers not mentioned will be killed by the VM call in the trampoline, and ++// arguments in those registers not be available to the callee. ++bool Matcher::can_be_java_arg( int reg ) { ++ /* Refer to: [sharedRuntime_sw64.cpp] SharedRuntime::java_calling_convention() */ ++ if ( /* reg == T0_num || reg == T0_H_num ++ || */ reg == A0_num || reg == A0_H_num ++ || reg == A1_num || reg == A1_H_num ++ || reg == A2_num || reg == A2_H_num ++ || reg == A3_num || reg == A3_H_num ++ || reg == A4_num || reg == A4_H_num ++ || reg == A5_num || reg == A5_H_num ) ++ return true; ++ ++ if ( reg == F16_num || reg == F16_H_num ++ || reg == F17_num || reg == F17_H_num ++ || reg == F18_num || reg == F18_H_num ++ || reg == F19_num || reg == F19_H_num ++ || reg == F20_num || reg == F20_H_num ++ || reg == F21_num || reg == F21_H_num ) ++ return true; ++ ++ return false; ++} ++ ++bool Matcher::is_spillable_arg( int reg ) { ++ return can_be_java_arg(reg); ++} ++ ++bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) { ++ return false; ++} ++ ++// Register for MODL projection of divmodL ++RegMask Matcher::modL_proj_mask() { ++ ShouldNotReachHere(); ++ return RegMask(); ++} ++ ++const RegMask Matcher::method_handle_invoke_SP_save_mask() { ++ return FP_REG_mask(); ++} ++ ++// SW64 doesn't support AES intrinsics ++const bool Matcher::pass_original_key_for_aes() { ++ return false; ++} ++ ++#ifdef ZHJPAD ++// The address of the call instruction needs to be 16-byte aligned to ++// ensure that it does not span a cache line so that it can be patched. ++ ++int CallStaticJavaDirectNode::compute_padding(int current_offset) const { ++ //ldi ++ //sll ++ //ldih ++ //lsi ++ //call ++ //nop ++ return round_to(current_offset, alignment_required()) - current_offset; ++} ++ ++// The address of the call instruction needs to be 16-byte aligned to ++// ensure that it does not span a cache line so that it can be patched. ++int CallDynamicJavaDirectNode::compute_padding(int current_offset) const { ++ //li48 <--- skip ++ ++ //ldi ++ //slll ++ //ldih ++ //ldi ++ //call ++ //nop ++ ++//ZHJ current_offset += 4 * 6; // skip li64 ++ current_offset += 4 * BytesPerInstWord; // skip li48 ++ return round_to(current_offset, alignment_required()) - current_offset; ++} ++#endif ++ ++int CallLeafNoFPDirectNode::compute_padding(int current_offset) const { ++ //ldi ++ //slll ++ //ldih ++ //ldi ++ //call ++ //nop ++ return round_to(current_offset, alignment_required()) - current_offset; ++} ++ ++int CallLeafDirectNode::compute_padding(int current_offset) const { ++ return round_to(current_offset, alignment_required()) - current_offset; ++} ++ ++int CallRuntimeDirectNode::compute_padding(int current_offset) const { ++ return round_to(current_offset, alignment_required()) - current_offset; ++} ++ ++// If CPU can load and store mis-aligned doubles directly then no fixup is ++// needed. Else we split the double into 2 integer pieces and move it ++// piece-by-piece. Only happens when passing doubles into C code as the ++// Java calling convention forces doubles to be aligned. ++const bool Matcher::misaligned_doubles_ok = false; ++// Do floats take an entire double register or just half? ++bool Matcher::float_in_double() { return true; } //TODO: ZHJ20180613 ++// Threshold size for cleararray. ++const int Matcher::init_array_short_size = 8 * BytesPerLong; ++// Do ints take an entire long register or just half? ++const bool Matcher::int_in_long = true; ++// Is it better to copy float constants, or load them directly from memory? ++// Intel can load a float constant from a direct address, requiring no ++// extra registers. Most RISCs will have to materialize an address into a ++// register first, so they would do better to copy the constant from stack. ++const bool Matcher::rematerialize_float_constants = false; ++// Advertise here if the CPU requires explicit rounding operations ++// to implement the UseStrictFP mode. ++const bool Matcher::strict_fp_requires_explicit_rounding = false; ++// false => size gets scaled to BytesPerLong, ok. ++const bool Matcher::init_array_count_is_in_bytes = false; ++ ++// Indicate if the safepoint node needs the polling page as an input. ++// Since SW64 doesn't have absolute addressing, it needs. ++bool SafePointNode::needs_polling_address_input() { ++ //TODO: ZHJ20180613 ++ return true; ++} ++ ++// Special hack to get all type of calls to specify the byte offset ++// from the start of the call to the point where the return address ++// will point. ++int MachCallStaticJavaNode::ret_addr_offset() { ++ if (SafePatch) { ++ assert(NativeCall::instruction_size == 24, "in MachCallStaticJavaNode::ret_addr_offset"); ++ } else { ++ assert(NativeCall::instruction_size == 20, "in MachCallStaticJavaNode::ret_addr_offset"); ++ } ++ return NativeCall::instruction_size; ++} ++ ++int MachCallDynamicJavaNode::ret_addr_offset() { ++ if (SafePatch) { ++ assert(NativeCall::instruction_size == 24, "in MachCallDynamicJavaNode::ret_addr_offset"); ++ } else { ++ assert(NativeCall::instruction_size == 20, "in MachCallStaticJavaNode::ret_addr_offset"); // don't consider setfpec1 ++ } ++ //li48 IC_Klass, ++ ++ //ldi T12 ++ //slll T12 ++ //ldih T12 ++ //ldi T12 ++ //call T12 ++ //nop ++ return 4 * BytesPerInstWord + NativeCall::instruction_size; // don't consider setfpec1 ++} ++ ++//============================================================================= ++ ++// Figure out which register class each belongs in: rc_int, rc_float, rc_stack ++enum RC { rc_bad, rc_int, rc_float, rc_stack }; ++static enum RC rc_class( OptoReg::Name reg ) { ++ if( !OptoReg::is_valid(reg) ) return rc_bad; ++ if (OptoReg::is_stack(reg)) return rc_stack; ++ VMReg r = OptoReg::as_VMReg(reg); ++ if (r->is_Register()) return rc_int; ++ assert(r->is_FloatRegister(), "must be"); ++ return rc_float; ++} ++ ++uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const { ++ // Get registers to move ++ OptoReg::Name src_second = ra_->get_reg_second(in(1)); ++ OptoReg::Name src_first = ra_->get_reg_first(in(1)); ++ OptoReg::Name dst_second = ra_->get_reg_second(this ); ++ OptoReg::Name dst_first = ra_->get_reg_first(this ); ++ ++ enum RC src_second_rc = rc_class(src_second); ++ enum RC src_first_rc = rc_class(src_first); ++ enum RC dst_second_rc = rc_class(dst_second); ++ enum RC dst_first_rc = rc_class(dst_first); ++ ++ assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" ); ++ ++ // Generate spill code! ++ int size = 0; ++ ++ if( src_first == dst_first && src_second == dst_second ) ++ return 0; // Self copy, no move ++ ++ if (src_first_rc == rc_stack) { ++ // mem -> ++ if (dst_first_rc == rc_stack) { ++ // mem -> mem ++ assert(src_second != dst_first, "overlap"); ++ if ((src_first & 1) == 0 && src_first + 1 == src_second && ++ (dst_first & 1) == 0 && dst_first + 1 == dst_second) { ++ // 64-bit ++ int src_offset = ra_->reg2offset(src_first); ++ int dst_offset = ra_->reg2offset(dst_first); ++ if (cbuf) { ++ MacroAssembler _masm(cbuf); ++ __ ldl(AT, Address(SP, src_offset)); ++ __ stl(AT, Address(SP, dst_offset)); ++#ifndef PRODUCT ++ } else { ++ if(!do_size){ ++ if (size != 0) st->print("\n\t"); ++ st->print("ldl AT, [SP + #%d]\t# 64-bit mem-mem spill 1\n\t" ++ "stl AT, [SP + #%d]", ++ src_offset, dst_offset); ++ } ++#endif ++ } ++ size += 8; ++ } else { ++ // 32-bit ++ assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); ++ assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); ++ int src_offset = ra_->reg2offset(src_first); ++ int dst_offset = ra_->reg2offset(dst_first); ++ if (cbuf) { ++ MacroAssembler _masm(cbuf); ++ __ ldw_signed(AT, Address(SP, src_offset)); ++ __ stw(AT, Address(SP, dst_offset)); ++#ifndef PRODUCT ++ } else { ++ if(!do_size){ ++ if (size != 0) st->print("\n\t"); ++ st->print("ldw AT, [SP + #%d] spill 2\n\t" ++ "stw AT, [SP + #%d]\n\t", ++ src_offset, dst_offset); ++ } ++#endif ++ } ++ size += 8; ++ } ++ return size; ++ } else if (dst_first_rc == rc_int) { ++ // mem -> gpr ++ if ((src_first & 1) == 0 && src_first + 1 == src_second && ++ (dst_first & 1) == 0 && dst_first + 1 == dst_second) { ++ // 64-bit ++ int offset = ra_->reg2offset(src_first); ++ if (cbuf) { ++ MacroAssembler _masm(cbuf); ++ __ ldl(as_Register(Matcher::_regEncode[dst_first]), Address(SP, offset)); ++#ifndef PRODUCT ++ } else { ++ if(!do_size){ ++ if (size != 0) st->print("\n\t"); ++ st->print("ldl %s, [SP + #%d]\t# spill 3", ++ Matcher::regName[dst_first], ++ offset); ++ } ++#endif ++ } ++ size += 4; ++ } else { ++ // 32-bit ++ assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); ++ assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); ++ int offset = ra_->reg2offset(src_first); ++ if (cbuf) { ++ MacroAssembler _masm(cbuf); ++ if (this->ideal_reg() == Op_RegI) ++ __ ldw_signed(as_Register(Matcher::_regEncode[dst_first]), Address(SP, offset)); ++ else ++ __ ldw_unsigned(as_Register(Matcher::_regEncode[dst_first]), Address(SP, offset)); ++#ifndef PRODUCT ++ } else { ++ if(!do_size){ ++ if (size != 0) st->print("\n\t"); ++ if (this->ideal_reg() == Op_RegI) ++ st->print("ldw %s, [SP + #%d]\t# spill 4", ++ Matcher::regName[dst_first], ++ offset); ++ else ++ st->print("ldwu %s, [SP + #%d]\t# spill 5", ++ Matcher::regName[dst_first], ++ offset); ++ } ++#endif ++ } ++ if (this->ideal_reg() == Op_RegI) { ++ size += 4; ++ } else { ++ size += 8; ++ } ++ } ++ return size; ++ } else if (dst_first_rc == rc_float) { ++ // mem-> xmm ++ if ((src_first & 1) == 0 && src_first + 1 == src_second && ++ (dst_first & 1) == 0 && dst_first + 1 == dst_second) { ++ // 64-bit ++ int offset = ra_->reg2offset(src_first); ++ if (cbuf) { ++ MacroAssembler _masm(cbuf); ++ __ fldd( as_FloatRegister(Matcher::_regEncode[dst_first]), Address(SP, offset)); ++#ifndef PRODUCT ++ } else { ++ if(!do_size){ ++ if (size != 0) st->print("\n\t"); ++ st->print("fldd %s, [SP + #%d]\t# spill 6", ++ Matcher::regName[dst_first], ++ offset); ++ } ++#endif ++ } ++ size += 4; ++ } else { ++ // 32-bit ++ assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); ++ assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); ++ int offset = ra_->reg2offset(src_first); ++ if (cbuf) { ++ MacroAssembler _masm(cbuf); ++ __ flds( as_FloatRegister(Matcher::_regEncode[dst_first]), Address(SP, offset)); ++#ifndef PRODUCT ++ } else { ++ if(!do_size){ ++ if (size != 0) st->print("\n\t"); ++ st->print("flds %s, [SP + #%d]\t# spill 7", ++ Matcher::regName[dst_first], ++ offset); ++ } ++#endif ++ } ++ size += 4; ++ } ++ return size; ++ } ++ } else if (src_first_rc == rc_int) { ++ // gpr -> ++ if (dst_first_rc == rc_stack) { ++ // gpr -> mem ++ if ((src_first & 1) == 0 && src_first + 1 == src_second && ++ (dst_first & 1) == 0 && dst_first + 1 == dst_second) { ++ // 64-bit ++ int offset = ra_->reg2offset(dst_first); ++ if (cbuf) { ++ MacroAssembler _masm(cbuf); ++ __ stl(as_Register(Matcher::_regEncode[src_first]), Address(SP, offset)); ++#ifndef PRODUCT ++ } else { ++ if(!do_size){ ++ if (size != 0) st->print("\n\t"); ++ st->print("stl %s, [SP + #%d] # spill 8", ++ Matcher::regName[src_first], ++ offset); ++ } ++#endif ++ } ++ size += 4; ++ } else { ++ // 32-bit ++ assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); ++ assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); ++ int offset = ra_->reg2offset(dst_first); ++ if (cbuf) { ++ MacroAssembler _masm(cbuf); ++ __ stw(as_Register(Matcher::_regEncode[src_first]), Address(SP, offset)); ++#ifndef PRODUCT ++ } else { ++ if (!do_size) { ++ if (size != 0) st->print("\n\t"); ++ st->print("stl %s, [SP + #%d]\t# spill 9", ++ Matcher::regName[src_first], offset); ++ } ++#endif ++ } ++ size += 4; ++ } ++ return size; ++ } else if (dst_first_rc == rc_int) { ++ // gpr -> gpr ++ if ((src_first & 1) == 0 && src_first + 1 == src_second && ++ (dst_first & 1) == 0 && dst_first + 1 == dst_second) { ++ // 64-bit ++ if (cbuf) { ++ MacroAssembler _masm(cbuf); ++ __ addl(as_Register(Matcher::_regEncode[dst_first]), ++ as_Register(Matcher::_regEncode[src_first]), R0); ++#ifndef PRODUCT ++ } else { ++ if(!do_size){ ++ if (size != 0) st->print("\n\t"); ++ st->print("move(64bit) %s <-- %s\t# spill 10", ++ Matcher::regName[dst_first], ++ Matcher::regName[src_first]); ++ } ++#endif ++ } ++ size += 4; ++ return size; ++ } else { ++ // 32-bit ++ assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); ++ assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); ++ if (cbuf) { ++ MacroAssembler _masm(cbuf); ++ if (this->ideal_reg() == Op_RegI) ++ __ addw(as_Register(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]), R0); ++ else ++ __ addl(as_Register(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]), R0); ++#ifndef PRODUCT ++ } else { ++ if (!do_size) { ++ if (size != 0) st->print("\n\t"); ++ st->print("move(32-bit) %s <-- %s\t# spill 11", ++ Matcher::regName[dst_first], ++ Matcher::regName[src_first]); ++ } ++#endif ++ } ++ size += 4; ++ return size; ++ } ++ } else if (dst_first_rc == rc_float) { ++ // gpr -> xmm ++ if ((src_first & 1) == 0 && src_first + 1 == src_second && ++ (dst_first & 1) == 0 && dst_first + 1 == dst_second) { ++ // 64-bit ++ if (cbuf) { ++ MacroAssembler _masm(cbuf); ++ __ ifmovd(as_FloatRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first])); ++#ifndef PRODUCT ++ } else { ++ if(!do_size){ ++ if (size != 0) st->print("\n\t"); ++ st->print("ifmovd %s, %s\t# spill 12", ++ Matcher::regName[dst_first], ++ Matcher::regName[src_first]); ++ } ++#endif ++ } ++ size += 4; ++ } else { ++ // 32-bit ++ assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); ++ assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); ++ if (cbuf) { ++ MacroAssembler _masm(cbuf); ++ __ ifmovs(as_FloatRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first])); ++#ifndef PRODUCT ++ } else { ++ if(!do_size){ ++ if (size != 0) st->print("\n\t"); ++ st->print("ifmovs %s, %s\t# spill 13", ++ Matcher::regName[dst_first], ++ Matcher::regName[src_first]); ++ } ++#endif ++ } ++ size += 4; ++ } ++ return size; ++ } ++ } else if (src_first_rc == rc_float) { ++ // xmm -> ++ if (dst_first_rc == rc_stack) { ++ // xmm -> mem ++ if ((src_first & 1) == 0 && src_first + 1 == src_second && ++ (dst_first & 1) == 0 && dst_first + 1 == dst_second) { ++ // 64-bit ++ int offset = ra_->reg2offset(dst_first); ++ if (cbuf) { ++ MacroAssembler _masm(cbuf); ++ __ fstd( as_FloatRegister(Matcher::_regEncode[src_first]), Address(SP, offset) ); ++#ifndef PRODUCT ++ } else { ++ if(!do_size){ ++ if (size != 0) st->print("\n\t"); ++ st->print("fstd %s, [SP + #%d]\t# spill 14", ++ Matcher::regName[src_first], ++ offset); ++ } ++#endif ++ } ++ size += 4; ++ } else { ++ // 32-bit ++ assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); ++ assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); ++ int offset = ra_->reg2offset(dst_first); ++ if (cbuf) { ++ MacroAssembler _masm(cbuf); ++ __ fsts(as_FloatRegister(Matcher::_regEncode[src_first]), Address(SP, offset)); ++#ifndef PRODUCT ++ } else { ++ if(!do_size){ ++ if (size != 0) st->print("\n\t"); ++ st->print("fsts %s, [SP + #%d]\t# spill 15", ++ Matcher::regName[src_first], ++ offset); ++ } ++#endif ++ } ++ size += 4; ++ } ++ return size; ++ } else if (dst_first_rc == rc_int) { ++ // xmm -> gpr ++ if ((src_first & 1) == 0 && src_first + 1 == src_second && ++ (dst_first & 1) == 0 && dst_first + 1 == dst_second) { ++ // 64-bit ++ if (cbuf) { ++ MacroAssembler _masm(cbuf); ++ __ fimovd(as_Register(Matcher::_regEncode[dst_first]), as_FloatRegister(Matcher::_regEncode[src_first])); ++#ifndef PRODUCT ++ } else { ++ if(!do_size){ ++ if (size != 0) st->print("\n\t"); ++ st->print("fimovd %s, %s\t# spill 16", ++ Matcher::regName[src_first], ++ Matcher::regName[dst_first]); ++ } ++#endif ++ } ++ size += 4; ++ } else { ++ // 32-bit ++ assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); ++ assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); ++ if (cbuf) { ++ MacroAssembler _masm(cbuf); ++ __ fimovs(as_Register(Matcher::_regEncode[dst_first]), as_FloatRegister(Matcher::_regEncode[src_first])); ++#ifndef PRODUCT ++ } else { ++ if(!do_size){ ++ if (size != 0) st->print("\n\t"); ++ st->print("fimovs %s, %s\t# spill 17", ++ Matcher::regName[src_first], ++ Matcher::regName[dst_first]); ++ } ++#endif ++ } ++ size += 4; ++ } ++ return size; ++ } else if (dst_first_rc == rc_float) { ++ // xmm -> xmm ++ if ((src_first & 1) == 0 && src_first + 1 == src_second && ++ (dst_first & 1) == 0 && dst_first + 1 == dst_second) { ++ // 64-bit ++ if (cbuf) { ++ MacroAssembler _masm(cbuf); ++ __ fmovd( as_FloatRegister(Matcher::_regEncode[dst_first]), as_FloatRegister(Matcher::_regEncode[src_first])); ++#ifndef PRODUCT ++ } else { ++ if(!do_size){ ++ if (size != 0) st->print("\n\t"); ++ st->print("fmovd %s <-- %s\t# spill 18", ++ Matcher::regName[dst_first], ++ Matcher::regName[src_first]); ++ } ++#endif ++ } ++ size += 4; ++ } else { ++ // 32-bit ++ assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); ++ assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); ++ if (cbuf) { ++ MacroAssembler _masm(cbuf); ++ __ fmovs( as_FloatRegister(Matcher::_regEncode[dst_first]), as_FloatRegister(Matcher::_regEncode[src_first])); ++#ifndef PRODUCT ++ } else { ++ if(!do_size){ ++ if (size != 0) st->print("\n\t"); ++ st->print("fmovs %s <-- %s\t# spill 19", ++ Matcher::regName[dst_first], ++ Matcher::regName[src_first]); ++ } ++#endif ++ } ++ size += 4; ++ } ++ return size; ++ } ++ } ++ ++ assert(0," foo "); ++ Unimplemented(); ++ return size; ++ ++} ++ ++#ifndef PRODUCT ++void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { ++ implementation( NULL, ra_, false, st ); ++} ++#endif ++ ++void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { ++ implementation( &cbuf, ra_, false, NULL ); ++} ++ ++uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { ++ return implementation( NULL, ra_, true, NULL ); ++} ++ ++//============================================================================= ++# ++ ++#ifndef PRODUCT ++void MachBreakpointNode::format( PhaseRegAlloc *, outputStream* st ) const { ++ st->print("INT3"); ++} ++#endif ++ ++void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc* ra_) const { ++ MacroAssembler _masm(&cbuf); ++ __ int3(); ++} ++ ++uint MachBreakpointNode::size(PhaseRegAlloc* ra_) const { ++ return MachNode::size(ra_); ++} ++ ++ ++//============================================================================= ++#ifndef PRODUCT ++void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { ++ Compile *C = ra_->C; ++ int framesize = C->frame_size_in_bytes(); ++ ++ assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); ++ ++ st->print("ldl RA, SP, %d # Restore RA @ MachEpilogNode", framesize - wordSize); ++ st->cr(); st->print("\t"); ++ st->print("ldl FP, SP, %d # Restore FP @ MachEpilogNode", framesize - wordSize*2); ++ st->cr(); st->print("\t"); ++ st->print("add_simm16 SP, SP, %d # Rlease stack @ MachEpilogNode",framesize); ++ st->cr(); st->print("\t"); ++ ++ if( do_polling() && C->is_method_compilation() ) { ++ st->print("\t"); ++ st->print_cr("Poll Safepoint # MachEpilogNode"); ++ } ++} ++#endif ++ ++void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { ++ Compile *C = ra_->C; ++ MacroAssembler _masm(&cbuf); ++ int framesize = C->frame_size_in_bytes(); ++ ++ assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); ++ ++ __ ldl(RA, SP, framesize - wordSize); ++ __ ldl(FP, SP, framesize - wordSize * 2 ); ++ __ add_simm16(SP, SP, framesize); ++ ++ if( do_polling() && C->is_method_compilation() ) { ++ __ set64(AT, (long)os::get_polling_page()); ++ __ relocate(relocInfo::poll_return_type); ++ __ ldw(AT, AT, 0); ++ } ++} ++ ++uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { ++ return MachNode::size(ra_); ++} ++ ++int MachEpilogNode::reloc() const { ++ return 0; ++} ++ ++const Pipeline * MachEpilogNode::pipeline() const { ++ return MachNode::pipeline_class(); ++} ++ ++int MachEpilogNode::safepoint_offset() const { return 0; } ++ ++//============================================================================= ++ ++#ifndef PRODUCT ++void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { ++ int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); ++ int reg = ra_->get_reg_first(this); ++ st->print("addl %s, SP, %d @BoxLockNode",Matcher::regName[reg],offset); ++} ++#endif ++ ++ ++uint BoxLockNode::size(PhaseRegAlloc *ra_) const { ++ return 8; // TODO: Why use 8? ++} ++ ++void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { ++ MacroAssembler _masm(&cbuf); ++ int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); ++ int reg = ra_->get_encode(this); ++ ++ __ add_simm16(as_Register(reg), SP, offset); ++} ++ ++ ++//static int sizeof_FFree_Float_Stack_All = -1; ++ ++int MachCallRuntimeNode::ret_addr_offset() { ++ //li48 ++ //call ++ ++ if (SafePatch) { ++ assert(NativeCall::instruction_size == 24, "in MachCallRuntimeNode::ret_addr_offset()"); ++ } else { ++ assert(NativeCall::instruction_size == 20, "in MachCallRuntimeNode::ret_addr_offset()"); ++ } ++ return 4 * BytesPerInstWord + NativeCall::instruction_size; // don't consider setfpec1 ++} ++ ++ ++//============================================================================= ++#ifndef PRODUCT ++void MachNopNode::format( PhaseRegAlloc *, outputStream* st ) const { ++ st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count); ++} ++#endif ++ ++void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const { ++ MacroAssembler _masm(&cbuf); ++ int i = 0; ++ for(i = 0; i < _count; i++) ++ __ nop(); ++} ++ ++uint MachNopNode::size(PhaseRegAlloc *) const { ++ return 4 * _count; ++} ++ ++const Pipeline* MachNopNode::pipeline() const { ++ return MachNode::pipeline_class(); ++} ++ ++//============================================================================= ++ ++//============================================================================= ++#ifndef PRODUCT ++void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { ++ st->print_cr("load_klass(T12, A1)"); ++ st->print_cr("\tbeq(T12, iCache, L)"); ++ st->print_cr("\tjmp(SharedRuntime::get_ic_miss_stub(), relocInfo::runtime_call_type)"); ++ st->print_cr("\tnop"); ++ st->print_cr(" L:"); ++} ++#endif ++ ++ ++void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { ++ MacroAssembler _masm(&cbuf); ++#ifdef ASSERT ++ //uint code_size = cbuf.code_size(); ++#endif ++ int ic_reg = Matcher::inline_cache_reg_encode(); ++ Label L; ++ Register receiver = A1; ++ Register iCache = as_Register(ic_reg); ++ __ load_klass(T12, receiver); ++ __ beq(T12, iCache, L); ++ ++ __ relocate(relocInfo::runtime_call_type); ++ __ patchable_jump((address)SharedRuntime::get_ic_miss_stub()); ++ ++ // WARNING these NOPs are critical so that verified entry point is properly ++ // 8 bytes aligned for patching by NativeJump::patch_verified_entry() ++ __ align(CodeEntryAlignment); ++ __ BIND(L); ++} ++ ++uint MachUEPNode::size(PhaseRegAlloc *ra_) const { ++ return MachNode::size(ra_); ++} ++ ++ ++ ++//============================================================================= ++ ++const RegMask& MachConstantBaseNode::_out_RegMask = P_REG_mask(); ++ ++int Compile::ConstantTable::calculate_table_base_offset() const { ++ return 0; // absolute addressing, no offset ++} ++ ++bool MachConstantBaseNode::requires_postalloc_expand() const { return false; } ++void MachConstantBaseNode::postalloc_expand(GrowableArray *nodes, PhaseRegAlloc *ra_) { ++ ShouldNotReachHere(); ++} ++ ++void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { ++ Compile* C = ra_->C; ++ Compile::ConstantTable& constant_table = C->constant_table(); ++ MacroAssembler _masm(&cbuf); ++ ++ Register Rtoc = as_Register(ra_->get_encode(this)); ++ CodeSection* consts_section = __ code()->consts(); ++ int consts_size = consts_section->align_at_start(consts_section->size()); ++ assert(constant_table.size() == consts_size, "must be equal"); ++ ++ if (consts_section->size()) { ++ // Materialize the constant table base. ++ address baseaddr = consts_section->start() + -(constant_table.table_base_offset()); ++ // RelocationHolder rspec = internal_word_Relocation::spec(baseaddr); ++ __ relocate(relocInfo::internal_word_type); ++ __ patchable_set48(Rtoc, (long)baseaddr); ++ } ++} ++ ++uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const { ++ // patchable_set48 (4 insts) ++ return 4 * 4; ++} ++ ++#ifndef PRODUCT ++void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { ++ Register r = as_Register(ra_->get_encode(this)); ++ st->print("patchable_set48 %s, &constanttable (constant table base) @ MachConstantBaseNode", r->name()); ++} ++#endif ++ ++ ++//============================================================================= ++#ifndef PRODUCT ++void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { ++ Compile* C = ra_->C; ++ ++ int framesize = C->frame_size_in_bytes(); ++ int bangsize = C->bang_size_in_bytes(); ++ assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); ++ ++ // Calls to C2R adapters often do not accept exceptional returns. ++ // We require that their callers must bang for them. But be careful, because ++ // some VM calls (such as call site linkage) can use several kilobytes of ++ // stack. But the stack safety zone should account for that. ++ // See bugs 4446381, 4468289, 4497237. ++ if (C->need_stack_bang(bangsize)) { ++ st->print_cr("# stack bang"); st->print("\t"); ++ } ++ st->print("add_simm16 SP, SP, -%d \t",framesize); ++ st->print("stl RA, %d(SP) @ MachPrologNode\n\t", framesize-wordSize); ++ st->print("stl FP, %d(SP) @ MachPrologNode\n\t", framesize-wordSize*2); ++ st->print("add_simm16 FP, SP, %d \n\t", framesize-wordSize*2); ++} ++#endif ++ ++ ++void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { ++ Compile* C = ra_->C; ++ MacroAssembler _masm(&cbuf); ++ ++ int framesize = C->frame_size_in_bytes(); ++ int bangsize = C->bang_size_in_bytes(); ++ ++ assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); ++ ++ if (C->need_stack_bang(bangsize)) { ++ __ generate_stack_overflow_check(bangsize); ++ } ++ ++ __ add_simm16(SP, SP, -framesize); ++ __ stl(RA, SP, framesize - wordSize); ++ __ stl(FP, SP, framesize - wordSize*2); ++ __ add_simm16(FP, SP, framesize - wordSize*2); ++ __ nop(); // Make enough room for patch_verified_entry() ++ __ nop(); ++ ++ C->set_frame_complete(cbuf.insts_size()); ++ if (C->has_mach_constant_base_node()) { ++ // NOTE: We set the table base offset here because users might be ++ // emitted before MachConstantBaseNode. ++ Compile::ConstantTable& constant_table = C->constant_table(); ++ constant_table.set_table_base_offset(constant_table.calculate_table_base_offset()); ++ } ++ ++} ++ ++ ++uint MachPrologNode::size(PhaseRegAlloc *ra_) const { ++ return MachNode::size(ra_); // too many variables; just compute it the hard way ++} ++ ++int MachPrologNode::reloc() const { ++ return 0; // a large enough number ++} ++ ++%} ++ ++//----------ENCODING BLOCK----------------------------------------------------- ++// This block specifies the encoding classes used by the compiler to output ++// byte streams. Encoding classes generate functions which are called by ++// Machine Instruction Nodes in order to generate the bit encoding of the ++// instruction. Operands specify their base encoding interface with the ++// interface keyword. There are currently supported four interfaces, ++// REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an ++// operand to generate a function which returns its register number when ++// queried. CONST_INTER causes an operand to generate a function which ++// returns the value of the constant when queried. MEMORY_INTER causes an ++// operand to generate four functions which return the Base Register, the ++// Index Register, the Scale Value, and the Offset Value of the operand when ++// queried. COND_INTER causes an operand to generate six functions which ++// return the encoding code (ie - encoding bits for the instruction) ++// associated with each basic boolean condition for a conditional instruction. ++// Instructions specify two basic values for encoding. They use the ++// ins_encode keyword to specify their encoding class (which must be one of ++// the class names specified in the encoding block), and they use the ++// opcode keyword to specify, in order, their primary, secondary, and ++// tertiary opcode. Only the opcode sections which a particular instruction ++// needs for encoding need to be specified. ++encode %{ ++ ++ //Load byte signed ++ enc_class load_B_enc (mRegI dst, memory mem) %{ ++ MacroAssembler _masm(&cbuf); ++ int dst = $dst$$reg; ++ int base = $mem$$base; ++ int disp = $mem$$disp; ++ ++ if( Assembler::is_simm16(disp) ) { ++ __ ldb_signed(as_Register(dst), as_Register(base), disp); ++ } else { ++ __ move(T12, disp); ++ __ addl(AT, as_Register(base), T12); ++ __ ldb_signed(as_Register(dst), AT, 0); ++ } ++ %} ++ ++ //Load byte unsigned ++ enc_class load_UB_enc (mRegI dst, memory mem) %{ ++ MacroAssembler _masm(&cbuf); ++ int dst = $dst$$reg; ++ int base = $mem$$base; ++ int disp = $mem$$disp; ++ ++ if( Assembler::is_simm16(disp) ) { ++ __ ldbu(as_Register(dst), as_Register(base), disp); ++ } else { ++ __ move(T12, disp); ++ __ addl(AT, as_Register(base), T12); ++ __ ldbu(as_Register(dst), AT, 0); ++ } ++ %} ++ ++ enc_class store_B_reg_enc (memory mem, mRegI src) %{ ++ MacroAssembler _masm(&cbuf); ++ int src = $src$$reg; ++ int base = $mem$$base; ++ int disp = $mem$$disp; ++ ++ if( Assembler::is_simm16(disp) ) { ++ __ stb(as_Register(src), as_Register(base), disp); ++ } else { ++ __ move(T12, disp); ++ __ addl(AT, as_Register(base), T12); ++ __ stb(as_Register(src), AT, 0); ++ } ++ %} ++ ++ /* no necessary ++ enc_class store_B_reg_enc_sync (memory mem, mRegI src) %{ ++ MacroAssembler _masm(&cbuf); ++ int src = $src$$reg; ++ int base = $mem$$base; ++ int disp = $mem$$disp; ++ ++ if( Assembler::is_simm16(disp) ) { ++ __ stb(as_Register(src), as_Register(base), disp); ++ } else { ++ Unimplemented(); ++ } ++ __ memb(); ++ %}*/ ++ ++ enc_class store_B_immI0_enc_sync (memory mem, immI0 src) %{ ++ MacroAssembler _masm(&cbuf); ++ int base = $mem$$base; ++ int disp = $mem$$disp; ++ if(UseWmemb) ++ __ wmemb(); ++ else ++ __ memb(); ++ if( Assembler::is_simm16(disp) ) { ++ __ stb(R0, as_Register(base), disp); ++ } else { ++ Unimplemented(); ++ } ++ %} ++ ++ enc_class store_B_immI0 (memory mem, immI0 src) %{ ++ MacroAssembler _masm(&cbuf); ++ int base = $mem$$base; ++ int disp = $mem$$disp; ++ ++ if( Assembler::is_simm16(disp) ) { ++ __ stb(R0, as_Register(base), disp); ++ } else { ++ Unimplemented(); ++ } ++ %} ++ ++ // Load Short (16bit signed) ++ enc_class load_S_enc (mRegI dst, memory mem) %{ ++ MacroAssembler _masm(&cbuf); ++ int dst = $dst$$reg; ++ int base = $mem$$base; ++ int disp = $mem$$disp; ++ ++ if( Assembler::is_simm16(disp) ) { ++ __ ldh_signed(as_Register(dst), as_Register(base), disp); ++ } else { ++ __ move(T12, disp); ++ __ addl(AT, as_Register(base), T12); ++ __ ldh_signed(as_Register(dst), AT, 0); ++ } ++ %} ++ ++ // Load Char (16bit unsigned) ++ enc_class load_C_enc (mRegI dst, memory mem) %{ ++ MacroAssembler _masm(&cbuf); ++ int dst = $dst$$reg; ++ int base = $mem$$base; ++ int disp = $mem$$disp; ++ ++ if( Assembler::is_simm16(disp) ) { ++ __ ldhu(as_Register(dst), as_Register(base), disp); ++ } else { ++ __ move(T12, disp); ++ __ addl(AT, as_Register(base), T12); ++ __ ldhu(as_Register(dst), AT, 0); ++ } ++ %} ++ ++ // Store Char (16bit unsigned) ++ enc_class store_C_reg_enc (memory mem, mRegI src) %{ ++ MacroAssembler _masm(&cbuf); ++ int src = $src$$reg; ++ int base = $mem$$base; ++ int disp = $mem$$disp; ++ ++ if( Assembler::is_simm16(disp) ) { ++ __ sth(as_Register(src), as_Register(base), disp); ++ } else { ++ __ move(T12, disp); ++ __ addl(AT, as_Register(base), T12); ++ __ sth(as_Register(src), AT, 0); ++ } ++ %} ++ ++ enc_class store_C0_enc (memory mem) %{ ++ MacroAssembler _masm(&cbuf); ++ int base = $mem$$base; ++ int disp = $mem$$disp; ++ ++ if( Assembler::is_simm16(disp) ) { ++ __ sth(R0, as_Register(base), disp); ++ } else { ++ __ move(T12, disp); ++ __ addl(AT, as_Register(base), T12); ++ __ sth(R0, AT, 0); ++ } ++ %} ++ ++ enc_class load_I_enc (mRegI dst, memory mem) %{ ++ MacroAssembler _masm(&cbuf); ++ int dst = $dst$$reg; ++ int base = $mem$$base; ++ int disp = $mem$$disp; ++ ++ if( Assembler::is_simm16(disp) ) { ++ __ ldw(as_Register(dst), as_Register(base), disp); ++ } else { ++ __ move(T12, disp); ++ __ addl(AT, as_Register(base), T12); ++ __ ldw(as_Register(dst), AT, 0); ++ } ++ ++ %} ++ ++ enc_class store_I_reg_enc (memory mem, mRegI src) %{ ++ MacroAssembler _masm(&cbuf); ++ int src = $src$$reg; ++ int base = $mem$$base; ++ int disp = $mem$$disp; ++ ++ if( Assembler::is_simm16(disp) ) { ++ __ stw(as_Register(src), as_Register(base), disp); ++ } else { ++ __ move(T12, disp); ++ __ addl(AT, as_Register(base), T12); ++ __ stw(as_Register(src), AT, 0); ++ } ++ %} ++ ++ enc_class store_I_immI0_enc (memory mem, immI0 src) %{ ++ MacroAssembler _masm(&cbuf); ++ int base = $mem$$base; ++ int disp = $mem$$disp; ++ ++ if (Assembler::is_simm16(disp) ) { ++ __ stw(R0, as_Register(base), disp); ++ } else { ++ Unimplemented(); ++ } ++ %} ++ ++ enc_class load_N_enc (mRegN dst, memory mem) %{ ++ MacroAssembler _masm(&cbuf); ++ int dst = $dst$$reg; ++ int base = $mem$$base; ++ int disp = $mem$$disp; ++ ++ relocInfo::relocType disp_reloc = $mem->disp_reloc(); ++ assert(disp_reloc == relocInfo::none, "cannot have disp"); ++ ++ if( Assembler::is_simm16(disp) ) { ++ __ ldw_unsigned(as_Register(dst), as_Register(base), disp); ++ } else { ++ __ set64(T12, disp); ++ __ addl(AT, as_Register(base), T12); ++ __ ldw_unsigned(as_Register(dst), AT, 0); ++ } ++ ++ %} ++ ++ ++ enc_class load_P_enc (mRegP dst, memory mem) %{ ++ MacroAssembler _masm(&cbuf); ++ int dst = $dst$$reg; ++ int base = $mem$$base; ++ int disp = $mem$$disp; ++ ++ relocInfo::relocType disp_reloc = $mem->disp_reloc(); ++ assert(disp_reloc == relocInfo::none, "cannot have disp"); ++ ++ if( Assembler::is_simm16(disp) ) { ++ __ ldl(as_Register(dst), as_Register(base), disp); ++ } else { ++ __ set64(T12, disp); ++ __ addl(AT, as_Register(base), T12); ++ __ ldl(as_Register(dst), AT, 0); ++ } ++ %} ++ ++ // Load acquire. ++ // load_P_enc + sync ++ enc_class load_P_enc_ac (mRegP dst, memory mem) %{ ++ MacroAssembler _masm(&cbuf); ++ int dst = $dst$$reg; ++ int base = $mem$$base; ++ int disp = $mem$$disp; ++ relocInfo::relocType disp_reloc = $mem->disp_reloc(); ++ assert(disp_reloc == relocInfo::none, "cannot have disp"); ++ ++ if( Assembler::is_simm16(disp) ) { ++ __ ldl(as_Register(dst), as_Register(base), disp); ++ } else { ++ __ set64(T9, disp); ++ __ addl(AT, as_Register(base), T9); ++ __ ldl(as_Register(dst), AT, 0); ++ } ++ __ memb(); ++ %} ++ ++ enc_class store_P_reg_enc (memory mem, mRegP src) %{ ++ MacroAssembler _masm(&cbuf); ++ int src = $src$$reg; ++ int base = $mem$$base; ++ int disp = $mem$$disp; ++ ++ if( Assembler::is_simm16(disp) ) { ++ __ stl(as_Register(src), as_Register(base), disp); ++ } else { ++ __ move(T12, disp); ++ __ addl(AT, as_Register(base), T12); ++ __ stl(as_Register(src), AT, 0); ++ } ++ %} ++ ++ enc_class store_N_reg_enc (memory mem, mRegN src) %{ ++ MacroAssembler _masm(&cbuf); ++ int src = $src$$reg; ++ int base = $mem$$base; ++ int disp = $mem$$disp; ++ ++ if( Assembler::is_simm16(disp) ) { ++ __ stw(as_Register(src), as_Register(base), disp); ++ } else { ++ __ move(T12, disp); ++ __ addl(AT, as_Register(base), T12); ++ __ stw(as_Register(src), AT, 0); ++ } ++ %} ++ ++ enc_class store_P_immP0_enc (memory mem) %{ ++ MacroAssembler _masm(&cbuf); ++ int base = $mem$$base; ++ int disp = $mem$$disp; ++ ++ if( Assembler::is_simm16(disp) ) { ++ __ stl(R0, as_Register(base), disp); ++ } else { ++ __ move(T12, disp); ++ __ addl(AT, as_Register(base), T12); ++ __ stl(R0, AT, 0); ++ } ++ %} ++ ++ enc_class storeImmN0_enc(memory mem, ImmN0 src) %{ ++ MacroAssembler _masm(&cbuf); ++ int base = $mem$$base; ++ int disp = $mem$$disp; ++ ++ if( Assembler::is_simm16(disp) ) { ++ __ stw(R0, as_Register(base), disp); ++ } else { ++ __ move(T12, disp); ++ __ addl(AT, as_Register(base), T12); ++ __ stw(R0, AT, 0); ++ } ++ %} ++ ++ enc_class load_L_enc (mRegL dst, memory mem) %{ ++ MacroAssembler _masm(&cbuf); ++ int base = $mem$$base; ++ int disp = $mem$$disp; ++ Register dst_reg = as_Register($dst$$reg); ++ ++ // For implicit null check ++ __ ldb_signed(AT, as_Register(base), 0); ++ ++ if( Assembler::is_simm16(disp) ) { ++ __ ldl(dst_reg, as_Register(base), disp); ++ } else { ++ __ move(T12, disp); ++ __ addl(AT, as_Register(base), T12); ++ __ ldl(dst_reg, AT, 0); ++ } ++ %} ++ ++ enc_class store_L_reg_enc (memory mem, mRegL src) %{ ++ MacroAssembler _masm(&cbuf); ++ int base = $mem$$base; ++ int disp = $mem$$disp; ++ Register src_reg = as_Register($src$$reg); ++ ++ if( Assembler::is_simm16(disp) ) { ++ __ stl(src_reg, as_Register(base), disp); ++ } else { ++ __ move(T12, disp); ++ __ addl(AT, as_Register(base), T12); ++ __ stl(src_reg, AT, 0); ++ } ++ %} ++ ++ enc_class store_L_immL0_enc (memory mem, immL0 src) %{ ++ MacroAssembler _masm(&cbuf); ++ int base = $mem$$base; ++ int disp = $mem$$disp; ++ ++ if( Assembler::is_simm16(disp) ) { ++ __ stl(R0, as_Register(base), disp); ++ } else { ++ __ move(T12, disp); ++ __ addl(AT, as_Register(base), T12); ++ __ stl(R0, AT, 0); ++ } ++ %} ++ ++ enc_class load_F_enc (regF dst, memory mem) %{ ++ MacroAssembler _masm(&cbuf); ++ int base = $mem$$base; ++ int disp = $mem$$disp; ++ FloatRegister dst = $dst$$FloatRegister; ++ ++ if( Assembler::is_simm16(disp) ) { ++ __ flds(dst, as_Register(base), disp); ++ } else { ++ __ move(T12, disp); ++ __ addl(AT, as_Register(base), T12); ++ __ flds(dst, AT, 0); ++ } ++ %} ++ ++ enc_class store_F_reg_enc (memory mem, regF src) %{ ++ MacroAssembler _masm(&cbuf); ++ int base = $mem$$base; ++ int disp = $mem$$disp; ++ FloatRegister src = $src$$FloatRegister; ++ ++ if( Assembler::is_simm16(disp) ) { ++ __ fsts(src, as_Register(base), disp); ++ } else { ++ __ move(T12, disp); ++ __ addl(AT, as_Register(base), T12); ++ __ fsts(src, AT, 0); ++ } ++ %} ++ ++ enc_class load_D_enc (regD dst, memory mem) %{ ++ MacroAssembler _masm(&cbuf); ++ int base = $mem$$base; ++ int disp = $mem$$disp; ++ FloatRegister dst_reg = as_FloatRegister($dst$$reg); ++ ++ if( Assembler::is_simm16(disp) ) { ++ __ fldd(dst_reg, as_Register(base), disp); ++ } else { ++ __ move(T12, disp); ++ __ addl(AT, as_Register(base), T12); ++ __ fldd(dst_reg, AT, 0); ++ } ++ %} ++ ++ enc_class store_D_reg_enc (memory mem, regD src) %{ ++ MacroAssembler _masm(&cbuf); ++ int base = $mem$$base; ++ int disp = $mem$$disp; ++ FloatRegister src_reg = as_FloatRegister($src$$reg); ++ if( Assembler::is_simm16(disp) ) { ++ __ fstd(src_reg, as_Register(base), disp); ++ } else { ++ __ move(T12, disp); ++ __ addl(AT, as_Register(base), T12); ++ __ fstd(src_reg, AT, 0); ++ } ++ %} ++ ++ enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf ++ MacroAssembler _masm(&cbuf); ++ // This is the instruction starting address for relocation info. ++ __ block_comment("Java_To_Runtime"); ++ if(UseAddpi){ ++ intptr_t patch_off = 2 + (NativeCall::return_address_offset)/BytesPerInstWord; ++ __ addpi(patch_off, AT); ++ }else { ++ intptr_t patch_off = 3 * BytesPerInstWord + NativeCall::return_address_offset; ++ __ br(AT, 0); ++ __ addl(AT, AT, patch_off); ++ } ++ __ stl(AT, S2thread, in_bytes(JavaThread::last_Java_pc_offset())); ++ __ nop(); // need it by zhj. ++ ++ cbuf.set_insts_mark(); ++ __ relocate(relocInfo::runtime_call_type); ++ ++ __ patchable_call_setfpec1((address)$meth$$method); ++ %} ++ ++ enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL ++ // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine ++ // who we intended to call. ++ MacroAssembler _masm(&cbuf); ++ cbuf.set_insts_mark(); ++ ++ if ( !_method ) { ++ __ relocate(relocInfo::runtime_call_type); ++ } else if(_optimized_virtual) { ++ __ relocate(relocInfo::opt_virtual_call_type); ++ } else { ++ __ relocate(relocInfo::static_call_type); ++ } ++ ++ __ patchable_call((address)($meth$$method)); ++ if( _method ) { // Emit stub for static call ++ emit_java_to_interp(cbuf); ++ } ++ %} ++ ++ ++ // ++ // [Ref: LIR_Assembler::ic_call() ] ++ // ++ enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL ++ MacroAssembler _masm(&cbuf); ++ __ block_comment("Java_Dynamic_Call"); ++ __ ic_call((address)$meth$$method); ++ %} ++ ++ ++ enc_class Set_Flags_After_Fast_Lock_Unlock(FlagsReg cr) %{ ++ Register flags = $cr$$Register; ++ Label L; ++ ++ MacroAssembler _masm(&cbuf); ++ ++ __ addl(flags, R0, R0); ++ __ beq(AT, L); ++ __ move(flags, 0xFFFFFFFF); ++ __ BIND(L); ++ %} ++ ++ enc_class enc_PartialSubtypeCheck(mRegP result, mRegP sub, mRegP super, mRegI tmp) %{ ++ Register result = $result$$Register; ++ Register sub = $sub$$Register; ++ Register super = $super$$Register; ++ Register length = $tmp$$Register; ++ Register tmp = T12; ++ Label miss; ++ ++ ++ MacroAssembler _masm(&cbuf); ++ Label done; ++ __ check_klass_subtype_slow_path(sub, super, length, tmp, ++ NULL, &miss, ++ /*set_cond_codes:*/ true); ++ // Refer to X86_64's RDI ++ __ move(result, 0); ++ __ beq(R0, done); ++ ++ __ BIND(miss); ++ __ move(result, 1); ++ __ BIND(done); ++ %} ++ ++%} ++ ++ ++//---------SW64 FRAME-------------------------------------------------------------- ++// Definition of frame structure and management information. ++// ++// S T A C K L A Y O U T Allocators stack-slot number ++// | (to get allocators register number ++// G Owned by | | v add SharedInfo::stack0) ++// r CALLER | | ++// o | +--------+ pad to even-align allocators stack-slot ++// w V | pad0 | numbers; owned by CALLER ++// t -----------+--------+----> Matcher::_in_arg_limit, unaligned ++// h ^ | in | 5 ++// | | args | 4 Holes in incoming args owned by SELF ++// | | old | | 3 ++// | | SP-+--------+----> Matcher::_old_SP, even aligned ++// v | | ret | 3 return address ++// Owned by +--------+ ++// Self | pad2 | 2 pad to align old SP ++// | +--------+ 1 ++// | | locks | 0 ++// | +--------+----> SharedInfo::stack0, even aligned ++// | | pad1 | 11 pad to align new SP ++// | +--------+ ++// | | | 10 ++// | | spills | 9 spills ++// V | | 8 (pad0 slot for callee) ++// -----------+--------+----> Matcher::_out_arg_limit, unaligned ++// ^ | out | 7 ++// | | args | 6 Holes in outgoing args owned by CALLEE ++// Owned by new | | ++// Callee SP-+--------+----> Matcher::_new_SP, even aligned ++// | | ++// ++// Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is ++// known from SELF's arguments and the Java calling convention. ++// Region 6-7 is determined per call site. ++// Note 2: If the calling convention leaves holes in the incoming argument ++// area, those holes are owned by SELF. Holes in the outgoing area ++// are owned by the CALLEE. Holes should not be nessecary in the ++// incoming area, as the Java calling convention is completely under ++// the control of the AD file. Doubles can be sorted and packed to ++// avoid holes. Holes in the outgoing arguments may be nessecary for ++// varargs C calling conventions. ++// Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is ++// even aligned with pad0 as needed. ++// Region 6 is even aligned. Region 6-7 is NOT even aligned; ++// region 6-11 is even aligned; it may be padded out more so that ++// the region from SP to FP meets the minimum stack alignment. ++// Note 4: For I2C adapters, the incoming FP may not meet the minimum stack ++// alignment. Region 11, pad1, may be dynamically extended so that ++// SP meets the minimum alignment. ++ ++ ++frame %{ ++ ++ stack_direction(TOWARDS_LOW); ++ ++ // These two registers define part of the calling convention ++ // between compiled code and the interpreter. ++ // SEE StartI2CNode::calling_convention & StartC2INode::calling_convention & StartOSRNode::calling_convention ++ // for more information. ++ ++ inline_cache_reg(T1); // Inline Cache Register ++ interpreter_method_oop_reg(S3); // Method Oop Register when calling interpreter ++ ++ // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset] ++ cisc_spilling_operand_name(indOffset32); ++ ++ // Number of stack slots consumed by locking an object ++ // generate Compile::sync_stack_slots ++ sync_stack_slots(2); ++ ++ frame_pointer(SP); ++ ++ // Interpreter stores its frame pointer in a register which is ++ // stored to the stack by I2CAdaptors. ++ // I2CAdaptors convert from interpreted java to compiled java. ++ ++ interpreter_frame_pointer(FP); ++ ++ // generate Matcher::stack_alignment ++ stack_alignment(StackAlignmentInBytes); //wordSize = sizeof(char*); ++ ++ // Number of stack slots between incoming argument block and the start of ++ // a new frame. The PROLOG must add this many slots to the stack. The ++ // EPILOG must remove this many slots. ++ in_preserve_stack_slots(4); //Now VerifyStackAtCalls is defined as false ! Leave two stack slots for ra and fp ++ ++ // Number of outgoing stack slots killed above the out_preserve_stack_slots ++ // for calls to C. Supports the var-args backing area for register parms. ++ varargs_C_out_slots_killed(0); ++ ++ // The after-PROLOG location of the return address. Location of ++ // return address specifies a type (REG or STACK) and a number ++ // representing the register number (i.e. - use a register name) or ++ // stack slot. ++ // Ret Addr is on stack in slot 0 if no locks or verification or alignment. ++ // Otherwise, it is above the locks and verification slot and alignment word ++ //return_addr(STACK -1+ round_to(1+VerifyStackAtCalls+Compile::current()->sync()*Compile::current()->sync_stack_slots(),WordsPerLong)); ++ return_addr(REG RA); ++ ++ // Body of function which returns an integer array locating ++ // arguments either in registers or in stack slots. Passed an array ++ // of ideal registers called "sig" and a "length" count. Stack-slot ++ // offsets are based on outgoing arguments, i.e. a CALLER setting up ++ // arguments for a CALLEE. Incoming stack arguments are ++ // automatically biased by the preserve_stack_slots field above. ++ ++ ++ // will generated to Matcher::calling_convention(OptoRegPair *sig, uint length, bool is_outgoing) ++ // StartNode::calling_convention call this. ++ calling_convention %{ ++ SharedRuntime::java_calling_convention(sig_bt, regs, length, false); ++ %} ++ ++ ++ ++ ++ // Body of function which returns an integer array locating ++ // arguments either in registers or in stack slots. Passed an array ++ // of ideal registers called "sig" and a "length" count. Stack-slot ++ // offsets are based on outgoing arguments, i.e. a CALLER setting up ++ // arguments for a CALLEE. Incoming stack arguments are ++ // automatically biased by the preserve_stack_slots field above. ++ ++ ++ // SEE CallRuntimeNode::calling_convention for more information. ++ c_calling_convention %{ ++ (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length); ++ %} ++ ++ ++ // Location of C & interpreter return values ++ // register(s) contain(s) return value for Op_StartI2C and Op_StartOSR. ++ // SEE Matcher::match. ++ c_return_value %{ ++ assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); ++ /* -- , -- , Op_RegN, Op_RegI, Op_RegP, Op_RegF, Op_RegD, Op_RegL */ ++ static int lo[Op_RegL+1] = { 0, 0, V0_num, V0_num, V0_num, F0_num, F0_num, V0_num }; ++ static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, V0_H_num, OptoReg::Bad, F0_H_num, V0_H_num }; ++ return OptoRegPair(hi[ideal_reg],lo[ideal_reg]); ++ %} ++ ++ // Location of return values ++ // register(s) contain(s) return value for Op_StartC2I and Op_Start. ++ // SEE Matcher::match. ++ ++ return_value %{ ++ assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); ++ /* -- , -- , Op_RegN, Op_RegI, Op_RegP, Op_RegF, Op_RegD, Op_RegL */ ++ static int lo[Op_RegL+1] = { 0, 0, V0_num, V0_num, V0_num, F0_num, F0_num, V0_num }; ++ static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, V0_H_num, OptoReg::Bad, F0_H_num, V0_H_num}; ++ return OptoRegPair(hi[ideal_reg],lo[ideal_reg]); ++ %} ++ ++%} ++ ++//----------ATTRIBUTES--------------------------------------------------------- ++//----------Operand Attributes------------------------------------------------- ++op_attrib op_cost(0); // Required cost attribute ++ ++//----------Instruction Attributes--------------------------------------------- ++ins_attrib ins_cost(100); // Required cost attribute ++ins_attrib ins_size(32); // Required size attribute (in bits) ++ins_attrib ins_pc_relative(0); // Required PC Relative flag ++ins_attrib ins_short_branch(0); // Required flag: is this instruction a ++ // non-matching short branch variant of some ++ // long branch? ++ins_attrib ins_alignment(4); // Required alignment attribute (must be a power of 2) ++ // specifies the alignment that some part of the instruction (not ++ // necessarily the start) requires. If > 1, a compute_padding() ++ // function must be provided for the instruction ++ ++//----------OPERANDS----------------------------------------------------------- ++// Operand definitions must precede instruction definitions for correct parsing ++// in the ADLC because operands constitute user defined types which are used in ++// instruction definitions. ++ ++// Vectors ++operand vecD() %{ ++ constraint(ALLOC_IN_RC(dbl_reg)); ++ match(VecD); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++// Flags register, used as output of compare instructions ++operand FlagsReg() %{ ++ constraint(ALLOC_IN_RC(sw64_flags)); ++ match(RegFlags); ++ ++ format %{ "AT" %} ++ interface(REG_INTER); ++%} ++ ++//----------Simple Operands---------------------------------------------------- ++//TODO: Should we need to define some more special immediate number ? ++// Immediate Operands ++// Integer Immediate ++operand immI() %{ ++ match(ConI); ++ ++ op_cost(20); ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++// Long Immediate 8-bit ++operand immL8() ++%{ ++ predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L); ++ match(ConL); ++ ++ op_cost(5); ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++// Constant for test vs zero ++operand immI0() %{ ++ predicate(n->get_int() == 0); ++ match(ConI); ++ ++ op_cost(0); ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++// Constant for increment ++operand immI1() %{ ++ predicate(n->get_int() == 1); ++ match(ConI); ++ ++ op_cost(0); ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++// Constant for decrement ++operand immI_M1() %{ ++ predicate(n->get_int() == -1); ++ match(ConI); ++ ++ op_cost(0); ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++operand immI_M1_255() %{ ++ predicate(-255 <= n->get_int() && (n->get_int() <= -1)); ++ match(ConI); ++ ++ op_cost(0); ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++operand immI_MaxI() %{ ++ predicate(n->get_int() == 2147483647); ++ match(ConI); ++ ++ op_cost(0); ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++// Valid scale values for addressing modes ++operand immI2() %{ ++ predicate(0 <= n->get_int() && (n->get_int() <= 3)); ++ match(ConI); ++ ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++operand immI16() %{ ++ predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767)); ++ match(ConI); ++ ++ op_cost(10); ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++// Constant for long shifts ++operand immI_32() %{ ++ predicate( n->get_int() == 32 ); ++ match(ConI); ++ ++ op_cost(0); ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++operand immI_64() %{ ++ predicate(n->get_int() == 64); ++ match(ConI); ++ ++ op_cost(0); ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++operand immI_0_31() %{ ++ predicate( n->get_int() >= 0 && n->get_int() <= 31 ); ++ match(ConI); ++ op_cost(0); ++ ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++operand immI_0_63() %{ ++ predicate( n->get_int() >= 0 && n->get_int() <= 63 ); ++ match(ConI); ++ ++ op_cost(0); ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++// Operand for non-negtive integer mask ++ ++operand immI16_sub() %{ ++ predicate((-32767 <= n->get_int()) && (n->get_int() <= 32768)); ++ match(ConI); ++ ++ op_cost(10); ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++operand immI_0_255() %{ ++ predicate( n->get_int() >= 0 && n->get_int() <= 255 ); ++ match(ConI); ++ op_cost(0); ++ ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++operand immI_32_63() %{ ++ predicate(n->get_int() >= 32 && n->get_int() <= 63); ++ match(ConI); ++ op_cost(0); ++ ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++operand immI_1() %{ ++ predicate( n->get_int() == 1 ); ++ match(ConI); ++ ++ op_cost(0); ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++operand immI_2() %{ ++ predicate( n->get_int() == 2 ); ++ match(ConI); ++ ++ op_cost(0); ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++operand immI_3() %{ ++ predicate( n->get_int() == 3 ); ++ match(ConI); ++ ++ op_cost(0); ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++operand immI_7() %{ ++ predicate( n->get_int() == 7 ); ++ match(ConI); ++ ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++// Immediates for special shifts (sign extend) ++ ++// Constants for increment ++operand immI_16() %{ ++ predicate( n->get_int() == 16 ); ++ match(ConI); ++ ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++operand immI_24() %{ ++ predicate( n->get_int() == 24 ); ++ match(ConI); ++ ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++operand immI_31() %{ ++ predicate( n->get_int() == 31 ); ++ match(ConI); ++ ++ op_cost(0); ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++operand immI_63() %{ ++ predicate( n->get_int() == 63 ); ++ match(ConI); ++ ++ op_cost(0); ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++// Constant for byte-wide masking ++operand immI_255() %{ ++ predicate( n->get_int() == 255 ); ++ match(ConI); ++ ++ op_cost(0); ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++operand immI_65535() %{ ++ predicate( n->get_int() == 65535 ); ++ match(ConI); ++ ++ op_cost(5); ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++operand immI_65536() %{ ++ predicate( n->get_int() == 65536 ); ++ match(ConI); ++ ++ op_cost(5); ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++operand immI_M65536() %{ ++ predicate( n->get_int() == -65536 ); ++ match(ConI); ++ ++ op_cost(5); ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++// Pointer Immediate ++operand immP() %{ ++ match(ConP); ++ ++ op_cost(10); ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++// NULL Pointer Immediate ++operand immP0() %{ ++ predicate( n->get_ptr() == 0 ); ++ match(ConP); ++ op_cost(0); ++ ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++// Pointer Immediate: 64-bit ++operand immP_set() %{ ++ match(ConP); ++ ++ op_cost(5); ++ // formats are generated automatically for constants and base registers ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++// Pointer Immediate: 64-bit ++operand immP_load() %{ ++ predicate(n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set64(n->get_ptr()) > 3)); ++ match(ConP); ++ ++ op_cost(5); ++ // formats are generated automatically for constants and base registers ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++// Pointer Immediate: 64-bit ++operand immP_no_oop_cheap() %{ ++ predicate(!n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set64(n->get_ptr()) <= 3)); ++ match(ConP); ++ ++ op_cost(5); ++ // formats are generated automatically for constants and base registers ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++// Pointer for polling page ++operand immP_poll() %{ ++ predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page()); ++ match(ConP); ++ op_cost(5); ++ ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++// Pointer Immediate ++operand immN() %{ ++ match(ConN); ++ ++ op_cost(10); ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++operand immNKlass() %{ ++ match(ConNKlass); ++ ++ op_cost(10); ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++// NULL Pointer Immediate ++operand immN0() %{ ++ predicate(n->get_narrowcon() == 0); ++ match(ConN); ++ ++ op_cost(5); ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++// Long Immediate ++operand immL() %{ ++ match(ConL); ++ ++ op_cost(20); ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++// Long Immediate zero ++operand immL0() %{ ++ predicate( n->get_long() == 0L ); ++ match(ConL); ++ op_cost(0); ++ ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++operand immL7() %{ ++ predicate( n->get_long() == 7L ); ++ match(ConL); ++ op_cost(0); ++ ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++operand immL_M1() %{ ++ predicate( n->get_long() == -1L ); ++ match(ConL); ++ op_cost(0); ++ ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++// bit 0..2 zero ++operand immL_M8() %{ ++ predicate( n->get_long() == -8L ); ++ match(ConL); ++ op_cost(0); ++ ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++// bit 2 zero ++operand immL_M5() %{ ++ predicate( n->get_long() == -5L ); ++ match(ConL); ++ op_cost(0); ++ ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++// bit 1..2 zero ++operand immL_M7() %{ ++ predicate( n->get_long() == -7L ); ++ match(ConL); ++ op_cost(0); ++ ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++// bit 0..1 zero ++operand immL_M4() %{ ++ predicate( n->get_long() == -4L ); ++ match(ConL); ++ op_cost(0); ++ ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++// bit 3..6 zero ++operand immL_M121() %{ ++ predicate( n->get_long() == -121L ); ++ match(ConL); ++ op_cost(0); ++ ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++// Long immediate from 0 to 127. ++// Used for a shorter form of long mul by 10. ++operand immL_127() %{ ++ predicate((0 <= n->get_long()) && (n->get_long() <= 127)); ++ match(ConL); ++ op_cost(0); ++ ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++operand immL_0_255() %{ ++ predicate( n->get_long() >= 0 && n->get_long() <= 255 ); ++ match(ConL); ++ op_cost(0); ++ ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++// Long Immediate: cheap (materialize in <= 3 instructions) ++operand immL_cheap() %{ ++ predicate(MacroAssembler::insts_for_set64(n->get_long()) <= 3); ++ match(ConL); ++ op_cost(0); ++ ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++// Long Immediate: expensive (materialize in > 3 instructions) ++operand immL_expensive() %{ ++ predicate(MacroAssembler::insts_for_set64(n->get_long()) > 3); ++ match(ConL); ++ op_cost(0); ++ ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++operand immL16() %{ ++ predicate((-32768 <= n->get_long()) && (n->get_long() <= 32767)); ++ match(ConL); ++ ++ op_cost(10); ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++operand immL16_sub() %{ ++ predicate((-32767 <= n->get_long()) && (n->get_long() <= 32768)); ++ match(ConL); ++ ++ op_cost(10); ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++// Long Immediate: low 32-bit mask ++operand immL_32bits() %{ ++ predicate(n->get_long() == 0xFFFFFFFFL); ++ match(ConL); ++ op_cost(20); ++ ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++// Long Immediate 32-bit signed ++operand immL32() ++%{ ++ predicate(n->get_long() == (int) (n->get_long())); ++ match(ConL); ++ ++ op_cost(15); ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++ ++//single-precision floating-point zero ++operand immF0() %{ ++ predicate(jint_cast(n->getf()) == 0); ++ match(ConF); ++ ++ op_cost(5); ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++//single-precision floating-point immediate ++operand immF() %{ ++ match(ConF); ++ ++ op_cost(20); ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++//double-precision floating-point zero ++operand immD0() %{ ++ predicate(jlong_cast(n->getd()) == 0); ++ match(ConD); ++ ++ op_cost(5); ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++//double-precision floating-point immediate ++operand immD() %{ ++ match(ConD); ++ ++ op_cost(20); ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++// Register Operands ++// Integer Register ++operand mRegI() %{ ++ constraint(ALLOC_IN_RC(int_reg)); ++ match(RegI); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand no_Ax_mRegI() %{ ++ constraint(ALLOC_IN_RC(no_Ax_int_reg)); ++ match(RegI); ++ match(mRegI); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand mS0RegI() %{ ++ constraint(ALLOC_IN_RC(s0_reg)); ++ match(RegI); ++ match(mRegI); ++ ++ format %{ "S0" %} ++ interface(REG_INTER); ++%} ++ ++operand mS1RegI() %{ ++ constraint(ALLOC_IN_RC(s1_reg)); ++ match(RegI); ++ match(mRegI); ++ ++ format %{ "S1" %} ++ interface(REG_INTER); ++%} ++ ++operand mS2RegI() %{ ++ constraint(ALLOC_IN_RC(s2_reg)); ++ match(RegI); ++ match(mRegI); ++ ++ format %{ "S2" %} ++ interface(REG_INTER); ++%} ++ ++operand mS3RegI() %{ ++ constraint(ALLOC_IN_RC(s3_reg)); ++ match(RegI); ++ match(mRegI); ++ ++ format %{ "S3" %} ++ interface(REG_INTER); ++%} ++ ++operand mS4RegI() %{ ++ constraint(ALLOC_IN_RC(s4_reg)); ++ match(RegI); ++ match(mRegI); ++ ++ format %{ "S4" %} ++ interface(REG_INTER); ++%} ++ ++operand mS5RegI() %{ ++ constraint(ALLOC_IN_RC(s5_reg)); ++ match(RegI); ++ match(mRegI); ++ ++ format %{ "S5" %} ++ interface(REG_INTER); ++%} ++ ++operand mT0RegI() %{ ++ constraint(ALLOC_IN_RC(t0_reg)); ++ match(RegI); ++ match(mRegI); ++ ++ format %{ "T0" %} ++ interface(REG_INTER); ++%} ++ ++operand mT1RegI() %{ ++ constraint(ALLOC_IN_RC(t1_reg)); ++ match(RegI); ++ match(mRegI); ++ ++ format %{ "T1" %} ++ interface(REG_INTER); ++%} ++ ++operand mT2RegI() %{ ++ constraint(ALLOC_IN_RC(t2_reg)); ++ match(RegI); ++ match(mRegI); ++ ++ format %{ "T2" %} ++ interface(REG_INTER); ++%} ++ ++operand mT3RegI() %{ ++ constraint(ALLOC_IN_RC(t3_reg)); ++ match(RegI); ++ match(mRegI); ++ ++ format %{ "T3" %} ++ interface(REG_INTER); ++%} ++ ++operand mT4RegI() %{ ++ constraint(ALLOC_IN_RC(t4_reg)); ++ match(RegI); ++ match(mRegI); ++ ++ format %{ "T4" %} ++ interface(REG_INTER); ++%} ++ ++operand mT5RegI() %{ ++ constraint(ALLOC_IN_RC(t5_reg)); ++ match(RegI); ++ match(mRegI); ++ ++ format %{ "T5" %} ++ interface(REG_INTER); ++%} ++ ++operand mT6RegI() %{ ++ constraint(ALLOC_IN_RC(t6_reg)); ++ match(RegI); ++ match(mRegI); ++ ++ format %{ "T6" %} ++ interface(REG_INTER); ++%} ++ ++operand mT7RegI() %{ ++ constraint(ALLOC_IN_RC(t7_reg)); ++ match(RegI); ++ match(mRegI); ++ ++ format %{ "T7" %} ++ interface(REG_INTER); ++%} ++ ++operand mT8RegI() %{ ++ constraint(ALLOC_IN_RC(t8_reg)); ++ match(RegI); ++ match(mRegI); ++ ++ format %{ "T8" %} ++ interface(REG_INTER); ++%} ++ ++operand mT9RegI() %{ ++ constraint(ALLOC_IN_RC(t9_reg)); ++ match(RegI); ++ match(mRegI); ++ ++ format %{ "T9" %} ++ interface(REG_INTER); ++%} ++ ++operand mT10RegI() %{ ++ constraint(ALLOC_IN_RC(t10_reg)); ++ match(RegI); ++ match(mRegI); ++ ++ format %{ "T10" %} ++ interface(REG_INTER); ++%} ++ ++operand mT11RegI() %{ ++ constraint(ALLOC_IN_RC(t11_reg)); ++ match(RegI); ++ match(mRegI); ++ ++ format %{ "T11" %} ++ interface(REG_INTER); ++%} ++ ++operand mT12RegI() %{ ++ constraint(ALLOC_IN_RC(t12_reg)); ++ match(RegI); ++ match(mRegI); ++ ++ format %{ "T12" %} ++ interface(REG_INTER); ++%} ++ ++operand mA0RegI() %{ ++ constraint(ALLOC_IN_RC(a0_reg)); ++ match(RegI); ++ match(mRegI); ++ ++ format %{ "A0" %} ++ interface(REG_INTER); ++%} ++ ++operand mA1RegI() %{ ++ constraint(ALLOC_IN_RC(a1_reg)); ++ match(RegI); ++ match(mRegI); ++ ++ format %{ "A1" %} ++ interface(REG_INTER); ++%} ++ ++operand mA2RegI() %{ ++ constraint(ALLOC_IN_RC(a2_reg)); ++ match(RegI); ++ match(mRegI); ++ ++ format %{ "A2" %} ++ interface(REG_INTER); ++%} ++ ++operand mA3RegI() %{ ++ constraint(ALLOC_IN_RC(a3_reg)); ++ match(RegI); ++ match(mRegI); ++ ++ format %{ "A3" %} ++ interface(REG_INTER); ++%} ++ ++operand mA4RegI() %{ ++ constraint(ALLOC_IN_RC(a4_reg)); ++ match(RegI); ++ match(mRegI); ++ ++ format %{ "A4" %} ++ interface(REG_INTER); ++%} ++ ++operand mA5RegI() %{ ++ constraint(ALLOC_IN_RC(a5_reg)); ++ match(RegI); ++ match(mRegI); ++ ++ format %{ "A5" %} ++ interface(REG_INTER); ++%} ++ ++operand mV0RegI() %{ ++ constraint(ALLOC_IN_RC(v0_reg)); ++ match(RegI); ++ match(mRegI); ++ ++ format %{ "V0" %} ++ interface(REG_INTER); ++%} ++ ++operand mRegN() %{ ++ constraint(ALLOC_IN_RC(int_reg)); ++ match(RegN); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand t0_RegN() %{ ++ constraint(ALLOC_IN_RC(t0_reg)); ++ match(RegN); ++ match(mRegN); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand t1_RegN() %{ ++ constraint(ALLOC_IN_RC(t1_reg)); ++ match(RegN); ++ match(mRegN); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand t2_RegN() %{ ++ constraint(ALLOC_IN_RC(t2_reg)); ++ match(RegN); ++ match(mRegN); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand t3_RegN() %{ ++ constraint(ALLOC_IN_RC(t3_reg)); ++ match(RegN); ++ match(mRegN); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand t4_RegN() %{ ++ constraint(ALLOC_IN_RC(t4_reg)); ++ match(RegN); ++ match(mRegN); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand t5_RegN() %{ ++ constraint(ALLOC_IN_RC(t5_reg)); ++ match(RegN); ++ match(mRegN); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand t6_RegN() %{ ++ constraint(ALLOC_IN_RC(t6_reg)); ++ match(RegN); ++ match(mRegN); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand t7_RegN() %{ ++ constraint(ALLOC_IN_RC(t7_reg)); ++ match(RegN); ++ match(mRegN); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand t8_RegN() %{ ++ constraint(ALLOC_IN_RC(t8_reg)); ++ match(RegN); ++ match(mRegN); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand t9_RegN() %{ ++ constraint(ALLOC_IN_RC(t9_reg)); ++ match(RegN); ++ match(mRegN); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand t10_RegN() %{ ++ constraint(ALLOC_IN_RC(t10_reg)); ++ match(RegN); ++ match(mRegN); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand t11_RegN() %{ ++ constraint(ALLOC_IN_RC(t11_reg)); ++ match(RegN); ++ match(mRegN); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand t12_RegN() %{ ++ constraint(ALLOC_IN_RC(t12_reg)); ++ match(RegN); ++ match(mRegN); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand a0_RegN() %{ ++ constraint(ALLOC_IN_RC(a0_reg)); ++ match(RegN); ++ match(mRegN); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand a1_RegN() %{ ++ constraint(ALLOC_IN_RC(a1_reg)); ++ match(RegN); ++ match(mRegN); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand a2_RegN() %{ ++ constraint(ALLOC_IN_RC(a2_reg)); ++ match(RegN); ++ match(mRegN); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand a3_RegN() %{ ++ constraint(ALLOC_IN_RC(a3_reg)); ++ match(RegN); ++ match(mRegN); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand a4_RegN() %{ ++ constraint(ALLOC_IN_RC(a4_reg)); ++ match(RegN); ++ match(mRegN); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand a5_RegN() %{ ++ constraint(ALLOC_IN_RC(a5_reg)); ++ match(RegN); ++ match(mRegN); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand s0_RegN() %{ ++ constraint(ALLOC_IN_RC(s0_reg)); ++ match(RegN); ++ match(mRegN); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand s1_RegN() %{ ++ constraint(ALLOC_IN_RC(s1_reg)); ++ match(RegN); ++ match(mRegN); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand s2_RegN() %{ ++ constraint(ALLOC_IN_RC(s2_reg)); ++ match(RegN); ++ match(mRegN); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand s3_RegN() %{ ++ constraint(ALLOC_IN_RC(s3_reg)); ++ match(RegN); ++ match(mRegN); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand s4_RegN() %{ ++ constraint(ALLOC_IN_RC(s4_reg)); ++ match(RegN); ++ match(mRegN); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand s5_RegN() %{ ++ constraint(ALLOC_IN_RC(s5_reg)); ++ match(RegN); ++ match(mRegN); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand v0_RegN() %{ ++ constraint(ALLOC_IN_RC(v0_reg)); ++ match(RegN); ++ match(mRegN); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++// Pointer Register ++operand mRegP() %{ ++ constraint(ALLOC_IN_RC(p_reg)); ++ match(RegP); ++ match(a0_RegP); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand no_T11_mRegP() %{ ++ constraint(ALLOC_IN_RC(no_T11_p_reg)); ++ match(RegP); ++ match(mRegP); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand s0_RegP() ++%{ ++ constraint(ALLOC_IN_RC(s0_long_reg)); ++ match(RegP); ++ match(mRegP); ++ match(no_T11_mRegP); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand s1_RegP() ++%{ ++ constraint(ALLOC_IN_RC(s1_long_reg)); ++ match(RegP); ++ match(mRegP); ++ match(no_T11_mRegP); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand s2_RegP() ++%{ ++ constraint(ALLOC_IN_RC(s2_long_reg)); ++ match(RegP); ++ match(mRegP); ++ match(no_T11_mRegP); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand s3_RegP() ++%{ ++ constraint(ALLOC_IN_RC(s3_long_reg)); ++ match(RegP); ++ match(mRegP); ++ match(no_T11_mRegP); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand s4_RegP() ++%{ ++ constraint(ALLOC_IN_RC(s4_long_reg)); ++ match(RegP); ++ match(mRegP); ++ match(no_T11_mRegP); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand s5_RegP() ++%{ ++ constraint(ALLOC_IN_RC(s5_long_reg)); ++ match(RegP); ++ match(mRegP); ++ match(no_T11_mRegP); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand t0_RegP() ++%{ ++ constraint(ALLOC_IN_RC(t0_long_reg)); ++ match(RegP); ++ match(mRegP); ++ match(no_T11_mRegP); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand t1_RegP() ++%{ ++ constraint(ALLOC_IN_RC(t1_long_reg)); ++ match(RegP); ++ match(mRegP); ++ match(no_T11_mRegP); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand t2_RegP() ++%{ ++ constraint(ALLOC_IN_RC(t2_long_reg)); ++ match(RegP); ++ match(mRegP); ++ match(no_T11_mRegP); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand t3_RegP() ++%{ ++ constraint(ALLOC_IN_RC(t3_long_reg)); ++ match(RegP); ++ match(mRegP); ++ match(no_T11_mRegP); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand t4_RegP() ++%{ ++ constraint(ALLOC_IN_RC(t4_long_reg)); ++ match(RegP); ++ match(mRegP); ++ match(no_T11_mRegP); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand t5_RegP() ++%{ ++ constraint(ALLOC_IN_RC(t5_long_reg)); ++ match(RegP); ++ match(mRegP); ++ match(no_T11_mRegP); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand t6_RegP() ++%{ ++ constraint(ALLOC_IN_RC(t6_long_reg)); ++ match(RegP); ++ match(mRegP); ++ match(no_T11_mRegP); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand t7_RegP() ++%{ ++ constraint(ALLOC_IN_RC(t7_long_reg)); ++ match(RegP); ++ match(mRegP); ++ match(no_T11_mRegP); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand t8_RegP() ++%{ ++ constraint(ALLOC_IN_RC(t8_long_reg)); ++ match(RegP); ++ match(mRegP); ++ match(no_T11_mRegP); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand t9_RegP() ++%{ ++ constraint(ALLOC_IN_RC(t9_long_reg)); ++ match(RegP); ++ match(mRegP); ++ match(no_T11_mRegP); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand t10_RegP() ++%{ ++ constraint(ALLOC_IN_RC(t10_long_reg)); ++ match(RegP); ++ match(mRegP); ++ match(no_T11_mRegP); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand t11_RegP() ++%{ ++ constraint(ALLOC_IN_RC(t11_long_reg)); ++ match(RegP); ++ match(mRegP); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand t12_RegP() ++%{ ++ constraint(ALLOC_IN_RC(t12_long_reg)); ++ match(RegP); ++ match(mRegP); ++ match(no_T11_mRegP); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand a0_RegP() ++%{ ++ constraint(ALLOC_IN_RC(a0_long_reg)); ++ match(RegP); ++ match(mRegP); ++ match(no_T11_mRegP); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand a1_RegP() ++%{ ++ constraint(ALLOC_IN_RC(a1_long_reg)); ++ match(RegP); ++ match(mRegP); ++ match(no_T11_mRegP); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand a2_RegP() ++%{ ++ constraint(ALLOC_IN_RC(a2_long_reg)); ++ match(RegP); ++ match(mRegP); ++ match(no_T11_mRegP); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand a3_RegP() ++%{ ++ constraint(ALLOC_IN_RC(a3_long_reg)); ++ match(RegP); ++ match(mRegP); ++ match(no_T11_mRegP); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand a4_RegP() ++%{ ++ constraint(ALLOC_IN_RC(a4_long_reg)); ++ match(RegP); ++ match(mRegP); ++ match(no_T11_mRegP); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++ ++operand a5_RegP() ++%{ ++ constraint(ALLOC_IN_RC(a5_long_reg)); ++ match(RegP); ++ match(mRegP); ++ match(no_T11_mRegP); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand v0_RegP() ++%{ ++ constraint(ALLOC_IN_RC(v0_long_reg)); ++ match(RegP); ++ match(mRegP); ++ match(no_T11_mRegP); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand mRegL() %{ ++ constraint(ALLOC_IN_RC(long_reg)); ++ match(RegL); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand mRegI2L(mRegI reg) %{ ++ match(ConvI2L reg); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand v0RegL() %{ ++ constraint(ALLOC_IN_RC(v0_long_reg)); ++ match(RegL); ++ match(mRegL); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand t0RegL() %{ ++ constraint(ALLOC_IN_RC(t0_long_reg)); ++ match(RegL); ++ match(mRegL); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand t1RegL() %{ ++ constraint(ALLOC_IN_RC(t1_long_reg)); ++ match(RegL); ++ match(mRegL); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand t2RegL() %{ ++ constraint(ALLOC_IN_RC(t2_long_reg)); ++ match(RegL); ++ match(mRegL); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand t3RegL() %{ ++ constraint(ALLOC_IN_RC(t3_long_reg)); ++ match(RegL); ++ match(mRegL); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand t4RegL() %{ ++ constraint(ALLOC_IN_RC(t4_long_reg)); ++ match(RegL); ++ match(mRegL); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand t5RegL() %{ ++ constraint(ALLOC_IN_RC(t5_long_reg)); ++ match(RegL); ++ match(mRegL); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand t6RegL() %{ ++ constraint(ALLOC_IN_RC(t6_long_reg)); ++ match(RegL); ++ match(mRegL); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand t7RegL() %{ ++ constraint(ALLOC_IN_RC(t7_long_reg)); ++ match(RegL); ++ match(mRegL); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand s0RegL() %{ ++ constraint(ALLOC_IN_RC(s0_long_reg)); ++ match(RegL); ++ match(mRegL); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand s1RegL() %{ ++ constraint(ALLOC_IN_RC(s1_long_reg)); ++ match(RegL); ++ match(mRegL); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand s2RegL() %{ ++ constraint(ALLOC_IN_RC(s2_long_reg)); ++ match(RegL); ++ match(mRegL); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand s3RegL() %{ ++ constraint(ALLOC_IN_RC(s3_long_reg)); ++ match(RegL); ++ match(mRegL); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand s4RegL() %{ ++ constraint(ALLOC_IN_RC(s4_long_reg)); ++ match(RegL); ++ match(mRegL); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand s5RegL() %{ ++ constraint(ALLOC_IN_RC(s5_long_reg)); ++ match(RegL); ++ match(mRegL); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand a0RegL() %{ ++ constraint(ALLOC_IN_RC(a0_long_reg)); ++ match(RegL); ++ match(mRegL); ++ ++ format %{ "A0" %} ++ interface(REG_INTER); ++%} ++ ++operand a1RegL() %{ ++ constraint(ALLOC_IN_RC(a1_long_reg)); ++ match(RegL); ++ match(mRegL); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand a2RegL() %{ ++ constraint(ALLOC_IN_RC(a2_long_reg)); ++ match(RegL); ++ match(mRegL); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand a3RegL() %{ ++ constraint(ALLOC_IN_RC(a3_long_reg)); ++ match(RegL); ++ match(mRegL); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand a4RegL() %{ ++ constraint(ALLOC_IN_RC(a4_long_reg)); ++ match(RegL); ++ match(mRegL); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand a5RegL() %{ ++ constraint(ALLOC_IN_RC(a5_long_reg)); ++ match(RegL); ++ match(mRegL); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand indOffset16(mRegP reg, immL16 off) ++%{ ++ constraint(ALLOC_IN_RC(p_reg)); ++ match(AddP reg off); ++ ++ op_cost(10); ++ format %{ "[$reg + $off (16-bit)] @ indOffset16" %} ++ interface(MEMORY_INTER) %{ ++ base($reg); ++ index(0x0); /* NO_INDEX */ ++ scale(0x0); ++ disp($off); ++ %} ++%} ++ ++operand t8RegL() %{ ++ constraint(ALLOC_IN_RC(t8_long_reg)); ++ match(RegL); ++ match(mRegL); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand t9RegL() %{ ++ constraint(ALLOC_IN_RC(t9_long_reg)); ++ match(RegL); ++ match(mRegL); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand t10RegL() %{ ++ constraint(ALLOC_IN_RC(t10_long_reg)); ++ match(RegL); ++ match(mRegL); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++operand t11RegL() %{ ++ constraint(ALLOC_IN_RC(t11_long_reg)); ++ match(RegL); ++ match(mRegL); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++// Floating register operands ++operand regF() %{ ++ constraint(ALLOC_IN_RC(flt_reg)); ++ match(RegF); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++//Double Precision Floating register operands ++operand regD() %{ ++ constraint(ALLOC_IN_RC(dbl_reg)); ++ match(RegD); ++ ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++//----------Memory Operands---------------------------------------------------- ++// Indirect Memory Operand ++operand indirect(mRegP reg) %{ ++ constraint(ALLOC_IN_RC(p_reg)); ++ match(reg); ++ ++ format %{ "[$reg] @ indirect" %} ++ interface(MEMORY_INTER) %{ ++ base($reg); ++ index(0x0); /* NO_INDEX */ ++ scale(0x0); ++ disp(0x0); ++ %} ++%} ++ ++// Indirect Memory Plus Short Offset Operand ++operand indOffset8(mRegP reg, immL8 off) ++%{ ++ constraint(ALLOC_IN_RC(p_reg)); ++ match(AddP reg off); ++ ++ op_cost(10); ++ format %{ "[$reg + $off (8-bit)] @ indOffset8" %} ++ interface(MEMORY_INTER) %{ ++ base($reg); ++ index(0x0); /* NO_INDEX */ ++ scale(0x0); ++ disp($off); ++ %} ++%} ++ ++ ++// Indirect Memory Plus Long Offset Operand ++operand indOffset32(mRegP reg, immL32 off) %{ ++ constraint(ALLOC_IN_RC(p_reg)); ++ op_cost(20); ++ match(AddP reg off); ++ ++ format %{ "[$reg + $off (32-bit)] @ indOffset32" %} ++ interface(MEMORY_INTER) %{ ++ base($reg); ++ index(0x0); /* NO_INDEX */ ++ scale(0x0); ++ disp($off); ++ %} ++%} ++ ++operand indirectNarrowKlass(mRegN reg) ++%{ ++ predicate(Universe::narrow_klass_shift() == 0); ++ constraint(ALLOC_IN_RC(p_reg)); ++ op_cost(10); ++ match(DecodeNKlass reg); ++ ++ format %{ "[$reg] @ indirectNarrowKlass" %} ++ interface(MEMORY_INTER) %{ ++ base($reg); ++ index(0x0); ++ scale(0x0); ++ disp(0x0); ++ %} ++%} ++ ++operand indOffset8NarrowKlass(mRegN reg, immL8 off) ++%{ ++ predicate(Universe::narrow_klass_shift() == 0); ++ constraint(ALLOC_IN_RC(p_reg)); ++ op_cost(10); ++ match(AddP (DecodeNKlass reg) off); ++ ++ format %{ "[$reg + $off (8-bit)] @ indOffset8NarrowKlass" %} ++ interface(MEMORY_INTER) %{ ++ base($reg); ++ index(0x0); ++ scale(0x0); ++ disp($off); ++ %} ++%} ++ ++operand indOffset32NarrowKlass(mRegN reg, immL32 off) ++%{ ++ predicate(Universe::narrow_klass_shift() == 0); ++ constraint(ALLOC_IN_RC(p_reg)); ++ op_cost(10); ++ match(AddP (DecodeNKlass reg) off); ++ ++ format %{ "[$reg + $off (32-bit)] @ indOffset32NarrowKlass" %} ++ interface(MEMORY_INTER) %{ ++ base($reg); ++ index(0x0); ++ scale(0x0); ++ disp($off); ++ %} ++%} ++ ++// Indirect Memory Operand ++operand indirectNarrow(mRegN reg) ++%{ ++ predicate(Universe::narrow_oop_shift() == 0); ++ constraint(ALLOC_IN_RC(p_reg)); ++ op_cost(10); ++ match(DecodeN reg); ++ ++ format %{ "[$reg] @ indirectNarrow" %} ++ interface(MEMORY_INTER) %{ ++ base($reg); ++ index(0x0); ++ scale(0x0); ++ disp(0x0); ++ %} ++%} ++ ++operand indOffset16Narrow(mRegN reg, immL16 off) ++%{ ++ predicate(Universe::narrow_oop_shift() == 0); ++ constraint(ALLOC_IN_RC(p_reg)); ++ op_cost(10); ++ match(AddP (DecodeN reg) off); ++ ++ format %{ "[$reg + $off (16-bit)] @ indOffset16Narrow" %} ++ interface(MEMORY_INTER) %{ ++ base($reg); ++ index(0x0); ++ scale(0x0); ++ disp($off); ++ %} ++%} ++ ++// Indirect Memory Plus Short Offset Operand ++operand indOffset8Narrow(mRegN reg, immL8 off) ++%{ ++ predicate(Universe::narrow_oop_shift() == 0); ++ constraint(ALLOC_IN_RC(p_reg)); ++ op_cost(10); ++ match(AddP (DecodeN reg) off); ++ ++ format %{ "[$reg + $off (8-bit)] @ indOffset8Narrow" %} ++ interface(MEMORY_INTER) %{ ++ base($reg); ++ index(0x0); ++ scale(0x0); ++ disp($off); ++ %} ++%} ++ ++//----------Load Long Memory Operands------------------------------------------ ++// The load-long idiom will use it's address expression again after loading ++// the first word of the long. If the load-long destination overlaps with ++// registers used in the addressing expression, the 2nd half will be loaded ++// from a clobbered address. Fix this by requiring that load-long use ++// address registers that do not overlap with the load-long target. ++ ++// load-long support ++operand load_long_RegP() %{ ++ constraint(ALLOC_IN_RC(p_reg)); ++ match(RegP); ++ match(mRegP); ++ op_cost(100); ++ format %{ %} ++ interface(REG_INTER); ++%} ++ ++// Indirect Memory Operand Long ++operand load_long_indirect(load_long_RegP reg) %{ ++ constraint(ALLOC_IN_RC(p_reg)); ++ match(reg); ++ ++ format %{ "[$reg]" %} ++ interface(MEMORY_INTER) %{ ++ base($reg); ++ index(0x0); ++ scale(0x0); ++ disp(0x0); ++ %} ++%} ++ ++operand load_long_indOffset16(load_long_RegP reg, immL16 off) %{ ++ match(AddP reg off); ++ ++ format %{ "[$reg + $off(16-bit)]" %} ++ interface(MEMORY_INTER) %{ ++ base($reg); ++ index(0x0); ++ scale(0x0); ++ disp($off); ++ %} ++%} ++ ++// Indirect Memory Plus Long Offset Operand ++operand load_long_indOffset32(load_long_RegP reg, immL32 off) %{ ++ match(AddP reg off); ++ ++ format %{ "[$reg + $off]" %} ++ interface(MEMORY_INTER) %{ ++ base($reg); ++ index(0x0); ++ scale(0x0); ++ disp($off); ++ %} ++%} ++ ++//----------Conditional Branch Operands---------------------------------------- ++// Comparison Op - This is the operation of the comparison, and is limited to ++// the following set of codes: ++// L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) ++// ++// Other attributes of the comparison, such as unsignedness, are specified ++// by the comparison instruction that sets a condition code flags register. ++// That result is represented by a flags operand whose subtype is appropriate ++// to the unsignedness (etc.) of the comparison. ++// ++// Later, the instruction which matches both the Comparison Op (a Bool) and ++// the flags (produced by the Cmp) specifies the coding of the comparison op ++// by matching a specific subtype of Bool operand below, such as cmpOpU. ++ ++// Comparision Code ++operand cmpOp() %{ ++ match(Bool); ++ ++ format %{ "" %} ++ interface(COND_INTER) %{ ++ equal(0x01); ++ not_equal(0x02); ++ greater(0x03); ++ greater_equal(0x04); ++ less(0x05); ++ less_equal(0x06); ++ overflow(0x7); ++ no_overflow(0x8); ++ %} ++%} ++ ++ ++// Comparision Code ++// Comparison Code, unsigned compare. Used by FP also, with ++// C2 (unordered) turned into GT or LT already. The other bits ++// C0 and C3 are turned into Carry & Zero flags. ++operand cmpOpU() %{ ++ match(Bool); ++ ++ format %{ "" %} ++ interface(COND_INTER) %{ ++ equal(0x01); ++ not_equal(0x02); ++ greater(0x03); ++ greater_equal(0x04); ++ less(0x05); ++ less_equal(0x06); ++ overflow(0x7); ++ no_overflow(0x8); ++ %} ++%} ++ ++ ++//----------Special Memory Operands-------------------------------------------- ++// Stack Slot Operand - This operand is used for loading and storing temporary ++// values on the stack where a match requires a value to ++// flow through memory. ++operand stackSlotP(sRegP reg) %{ ++ constraint(ALLOC_IN_RC(stack_slots)); ++ // No match rule because this operand is only generated in matching ++ op_cost(50); ++ format %{ "[$reg]" %} ++ interface(MEMORY_INTER) %{ ++ base(0x1d); // SP ++ index(0x0); // No Index ++ scale(0x0); // No Scale ++ disp($reg); // Stack Offset ++ %} ++%} ++ ++operand stackSlotI(sRegI reg) %{ ++ constraint(ALLOC_IN_RC(stack_slots)); ++ // No match rule because this operand is only generated in matching ++ op_cost(50); ++ format %{ "[$reg]" %} ++ interface(MEMORY_INTER) %{ ++ base(0x1d); // SP ++ index(0x0); // No Index ++ scale(0x0); // No Scale ++ disp($reg); // Stack Offset ++ %} ++%} ++ ++operand stackSlotF(sRegF reg) %{ ++ constraint(ALLOC_IN_RC(stack_slots)); ++ // No match rule because this operand is only generated in matching ++ op_cost(50); ++ format %{ "[$reg]" %} ++ interface(MEMORY_INTER) %{ ++ base(0x1d); // SP ++ index(0x0); // No Index ++ scale(0x0); // No Scale ++ disp($reg); // Stack Offset ++ %} ++%} ++ ++operand stackSlotD(sRegD reg) %{ ++ constraint(ALLOC_IN_RC(stack_slots)); ++ // No match rule because this operand is only generated in matching ++ op_cost(50); ++ format %{ "[$reg]" %} ++ interface(MEMORY_INTER) %{ ++ base(0x1d); // SP ++ index(0x0); // No Index ++ scale(0x0); // No Scale ++ disp($reg); // Stack Offset ++ %} ++%} ++ ++operand stackSlotL(sRegL reg) %{ ++ constraint(ALLOC_IN_RC(stack_slots)); ++ // No match rule because this operand is only generated in matching ++ op_cost(50); ++ format %{ "[$reg]" %} ++ interface(MEMORY_INTER) %{ ++ base(0x1d); // SP ++ index(0x0); // No Index ++ scale(0x0); // No Scale ++ disp($reg); // Stack Offset ++ %} ++%} ++ ++ ++//------------------------OPERAND CLASSES-------------------------------------- ++//opclass memory( direct, indirect, indOffset16, indOffset32, indOffset32X, indIndexOffset ); ++//opclass memory( indirect, indirectNarrow, indOffset8, indOffset32, load_long_indirect, load_long_indOffset32, indOffset8Narrow); ++opclass memory( indirect, indirectNarrow, indOffset16, load_long_indirect, load_long_indOffset16, indOffset16Narrow); ++opclass mRegLorI2L(mRegI2L, mRegL); ++//----------PIPELINE----------------------------------------------------------- ++// Rules which define the behavior of the target architectures pipeline. ++ ++pipeline %{ ++ ++//----------ATTRIBUTES--------------------------------------------------------- ++attributes %{ ++ fixed_size_instructions; // Fixed size instructions ++ max_instructions_per_bundle = 1; // 1 instruction per bundle ++ max_bundles_per_cycle = 4; // Up to 4 bundles per cycle ++ bundle_unit_size=4; ++ instruction_unit_size = 4; // An instruction is 4 bytes long ++ instruction_fetch_unit_size = 16; // The processor fetches one line ++ instruction_fetch_units = 1; // of 16 bytes ++ ++ // List of nop instructions ++ nops( MachNop ); ++ %} ++ ++ //----------RESOURCES---------------------------------------------------------- ++ // Resources are the functional units available to the machine ++ ++ resources(D1, D2, D3, D4, DECODE = D1 | D2 | D3| D4, ALU1, ALU2, ALU = ALU1 | ALU2, FPU1, FPU2, FPU = FPU1 | FPU2, MEM, BR); ++ ++ //----------PIPELINE DESCRIPTION----------------------------------------------- ++ // Pipeline Description specifies the stages in the machine's pipeline ++ ++ // IF: fetch ++ // ID: decode ++ // RD: read ++ // CA: caculate ++ // WB: write back ++ // CM: commit ++ ++ pipe_desc(IF, ID, RD, CA, WB, CM); ++ ++ ++ //----------PIPELINE CLASSES--------------------------------------------------- ++ // Pipeline Classes describe the stages in which input and output are ++ // referenced by the hardware pipeline. ++ ++ //No.1 Integer ALU reg-reg operation : dst <-- reg1 op reg2 ++ pipe_class ialu_regI_regI(mRegI dst, mRegI src1, mRegI src2) %{ ++ single_instruction; ++ src1 : RD(read); ++ src2 : RD(read); ++ dst : WB(write)+1; ++ DECODE : ID; ++ ALU : CA; ++ %} ++ ++ //No.19 Integer mult operation : dst <-- reg1 mult reg2 ++ pipe_class ialu_mult(mRegI dst, mRegI src1, mRegI src2) %{ ++ src1 : RD(read); ++ src2 : RD(read); ++ dst : WB(write)+5; ++ DECODE : ID; ++ ALU2 : CA; ++ %} ++ ++ pipe_class mulL_reg_reg(mRegL dst, mRegL src1, mRegL src2) %{ ++ src1 : RD(read); ++ src2 : RD(read); ++ dst : WB(write)+10; ++ DECODE : ID; ++ ALU2 : CA; ++ %} ++ ++ pipe_class ialu_mult_imm(mRegI dst, mRegI src1, immI_0_255 src2) %{ ++ src1 : RD(read); ++ dst : WB(write)+5; ++ DECODE : ID; ++ ALU2 : CA; ++ %} ++ ++ pipe_class mulL_reg_imm(mRegL dst, mRegL src1, immL_0_255 src2) %{ ++ src1 : RD(read); ++ dst : WB(write)+10; ++ DECODE : ID; ++ ALU2 : CA; ++ %} ++ ++ //No.19 Integer div operation : dst <-- reg1 div reg2 ++ pipe_class ialu_div(mRegI dst, mRegI src1, mRegI src2) %{ ++ src1 : RD(read); ++ src2 : RD(read); ++ dst : WB(write)+10; ++ DECODE : ID; ++ ALU2 : CA; ++ %} ++ ++ //No.19 Integer mod operation : dst <-- reg1 mod reg2 ++ pipe_class ialu_mod(mRegI dst, mRegI src1, mRegI src2) %{ ++ instruction_count(2); ++ src1 : RD(read); ++ src2 : RD(read); ++ dst : WB(write)+10; ++ DECODE : ID; ++ ALU2 : CA; ++ %} ++ ++ //No.15 Long ALU reg-reg operation : dst <-- reg1 op reg2 ++ pipe_class ialu_regL_regL(mRegL dst, mRegL src1, mRegL src2) %{ ++ instruction_count(2); ++ src1 : RD(read); ++ src2 : RD(read); ++ dst : WB(write); ++ DECODE : ID; ++ ALU : CA; ++ %} ++ ++ //No.18 Long ALU reg-imm operation : dst <-- reg1 op immL_0_255 ++ pipe_class ialu_regL_imm(mRegL dst, mRegL src) %{ ++ instruction_count(2); ++ src : RD(read); ++ dst : WB(write); ++ DECODE : ID; ++ ALU : CA; ++ %} ++ ++ //No.18 Long ALU reg-imm16 operation : dst <-- reg1 op imm16 ++ pipe_class ialu_regL_imm16(mRegL dst, mRegL src) %{ ++ instruction_count(2); ++ src : RD(read); ++ dst : WB(write); ++ DECODE : ID; ++ ALU : CA; ++ %} ++ ++ //no.16 load Long from memory : ++ pipe_class ialu_loadL(mRegL dst, memory mem) %{ ++ instruction_count(2); ++ mem : RD(read); ++ dst : WB(write)+5; ++ DECODE : ID; ++ MEM : RD; ++ %} ++ ++ //No.17 Store Long to Memory : ++ pipe_class ialu_storeL(mRegL src, memory mem) %{ ++ instruction_count(2); ++ mem : RD(read); ++ src : RD(read); ++ DECODE : ID; ++ MEM : RD; ++ %} ++ ++ //No.2 Integer ALU reg-imm16 operation : dst <-- reg1 op imm16 ++ pipe_class ialu_regI_imm16(mRegI dst, mRegI src) %{ ++ single_instruction; ++ src : RD(read); ++ dst : WB(write); ++ DECODE : ID; ++ ALU : CA; ++ %} ++ ++ //No.3 Integer move operation : dst <-- reg ++ pipe_class ialu_regI_mov(mRegI dst, mRegI src) %{ ++ src : RD(read); ++ dst : WB(write); ++ DECODE : ID; ++ ALU : CA; ++ %} ++ ++ //No.4 No instructions : do nothing ++ pipe_class empty( ) %{ ++ instruction_count(0); ++ %} ++ ++ //No.5 UnConditional branch : ++ pipe_class pipe_jump( label labl ) %{ ++ multiple_bundles; ++ DECODE : ID; ++ BR : RD; ++ %} ++ ++ //No.6 ALU Conditional branch : ++ pipe_class pipe_alu_branch(mRegI src1, mRegI src2, label labl ) %{ ++ multiple_bundles; ++ src1 : RD(read); ++ src2 : RD(read); ++ DECODE : ID; ++ BR : RD; ++ %} ++ ++ //no.7 load integer from memory : ++ pipe_class ialu_loadI(mRegI dst, memory mem) %{ ++ mem : RD(read); ++ dst : WB(write)+3; ++ DECODE : ID; ++ MEM : RD; ++ %} ++ ++ //No.8 Store Integer to Memory : ++ pipe_class ialu_storeI(mRegI src, memory mem) %{ ++ mem : RD(read); ++ src : RD(read); ++ DECODE : ID; ++ MEM : RD; ++ %} ++ ++ ++ //No.10 Floating FPU reg-reg operation : dst <-- reg1 op reg2 ++ pipe_class fpu_regF_regF(regF dst, regF src1, regF src2) %{ ++ src1 : RD(read); ++ src2 : RD(read); ++ dst : WB(write); ++ DECODE : ID; ++ FPU : CA; ++ %} ++ ++ //No.22 Floating div operation : dst <-- reg1 div reg2 ++ pipe_class fpu_div(regF dst, regF src1, regF src2) %{ ++ src1 : RD(read); ++ src2 : RD(read); ++ dst : WB(write); ++ DECODE : ID; ++ FPU2 : CA; ++ %} ++ ++ pipe_class fcvt_I2D(regD dst, mRegI src) %{ ++ src : RD(read); ++ dst : WB(write); ++ DECODE : ID; ++ FPU1 : CA; ++ %} ++ ++ pipe_class fcvt_D2I(mRegI dst, regD src) %{ ++ src : RD(read); ++ dst : WB(write); ++ DECODE : ID; ++ FPU1 : CA; ++ %} ++ ++ ++ //No.23 Floating sqrt operation : dst <-- reg1 sqrt reg2 ++ pipe_class fpu_sqrt(regF dst, regF src1, regF src2) %{ ++ multiple_bundles; ++ src1 : RD(read); ++ src2 : RD(read); ++ dst : WB(write); ++ DECODE : ID; ++ FPU2 : CA; ++ %} ++ ++ //No.11 Load Floating from Memory : ++ pipe_class fpu_loadF(regF dst, memory mem) %{ ++ instruction_count(1); ++ mem : RD(read); ++ dst : WB(write)+3; ++ DECODE : ID; ++ MEM : RD; ++ %} ++ ++ //No.12 Store Floating to Memory : ++ pipe_class fpu_storeF(regF src, memory mem) %{ ++ instruction_count(1); ++ mem : RD(read); ++ src : RD(read); ++ DECODE : ID; ++ MEM : RD; ++ %} ++ ++ //No.13 FPU Conditional branch : ++ pipe_class pipe_fpu_branch(regF src1, regF src2, label labl ) %{ ++ multiple_bundles; ++ src1 : RD(read); ++ src2 : RD(read); ++ DECODE : ID; ++ BR : RD; ++ %} ++ ++//No.14 Floating FPU reg operation : dst <-- op reg ++ pipe_class fpu1_regF(regF dst, regF src) %{ ++ src : RD(read); ++ dst : WB(write); ++ DECODE : ID; ++ FPU : CA; ++ %} ++ ++ pipe_class long_memory_op() %{ ++ instruction_count(10); multiple_bundles; force_serialization; ++ fixed_latency(30); ++ %} ++ ++ pipe_class simple_call() %{ ++ instruction_count(10); multiple_bundles; force_serialization; ++ fixed_latency(200); ++ BR : RD; ++ %} ++ ++ pipe_class call() %{ ++ instruction_count(10); multiple_bundles; force_serialization; ++ fixed_latency(200); ++ %} ++ ++ ++ //No.9 Piple slow : for multi-instructions ++ pipe_class pipe_slow( ) %{ ++ instruction_count(20); ++ force_serialization; ++ multiple_bundles; ++ fixed_latency(50); ++ %} ++ ++%} ++ ++ ++ ++//----------INSTRUCTIONS------------------------------------------------------- ++// ++// match -- States which machine-independent subtree may be replaced ++// by this instruction. ++// ins_cost -- The estimated cost of this instruction is used by instruction ++// selection to identify a minimum cost tree of machine ++// instructions that matches a tree of machine-independent ++// instructions. ++// format -- A string providing the disassembly for this instruction. ++// The value of an instruction's operand may be inserted ++// by referring to it with a '$' prefix. ++// opcode -- Three instruction opcodes may be provided. These are referred ++// to within an encode class as $primary, $secondary, and $tertiary ++// respectively. The primary opcode is commonly used to ++// indicate the type of machine instruction, while secondary ++// and tertiary are often used for prefix options or addressing ++// modes. ++// ins_encode -- A list of encode classes with parameters. The encode class ++// name must have been defined in an 'enc_class' specification ++// in the encode section of the architecture description. ++ ++instruct s4AddLp(mRegP dst, mRegI index, immI_2 dis,mRegP base) %{ ++ match(Set dst (AddP base (LShiftL (ConvI2L index) dis))); ++ ins_cost(10); ++ format %{ " s4addl $index,$base,$dst @ s4AddLp " %} ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ Register op1 = as_Register($index$$reg); ++ Register op2 = as_Register($base$$reg); ++ __ s4addl(dst, op1, op2); ++ %} ++ ins_pipe( ialu_regL_regL ); ++%} ++ ++instruct s8AddLp(mRegP dst, mRegI index, immI_3 scale,mRegP base) %{ ++ match(Set dst (AddP base (LShiftL (ConvI2L index) scale))); ++ ins_cost(10); ++ format %{ " s8addl $index,$base,$dst @ s8AddLp " %} ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ Register op1 = as_Register($index$$reg); ++ Register op2 = as_Register($base$$reg); ++ __ s8addl(dst, op1, op2); ++ %} ++ ins_pipe( ialu_regL_regL ); ++%} ++ ++instruct s4AddWp(mRegI dst, mRegI index, immI_2 scale, mRegI base) %{ ++ match(Set dst (AddI base (LShiftI index scale))); ++ ins_cost(10); ++ format %{ " s4addw $index,$base,$dst @ s4AddWp " %} ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ Register op1 = as_Register($index$$reg); ++ Register op2 = as_Register($base$$reg); ++ __ s4addw(dst, op1, op2); ++ %} ++ ins_pipe( ialu_regI_regI ); ++%} ++ ++instruct s8AddWp(mRegI dst, mRegI index, immI_3 scale, mRegI base) %{ ++ match(Set dst (AddI base (LShiftI index scale))); ++ ins_cost(10); ++ format %{ " s8addw $index,$base,$dst @ s8AddWp " %} ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ Register op1 = as_Register($index$$reg); ++ Register op2 = as_Register($base$$reg); ++ __ s8addw(dst, op1, op2); ++ %} ++ ins_pipe( ialu_regI_regI ); ++%} ++ ++ ++// Load Integer ++instruct loadI(mRegI dst, memory mem) %{ ++ match(Set dst (LoadI mem)); ++ ++ ins_cost(125); ++ format %{ "ldw $dst, $mem #@loadI" %} ++ ins_encode (load_I_enc(dst, mem)); ++ ins_pipe( ialu_loadI ); ++%} ++ ++instruct loadI_convI2L(mRegL dst, memory mem) %{ ++ match(Set dst (ConvI2L (LoadI mem))); ++ ++ ins_cost(125); ++ format %{ "ldw $dst, $mem #@loadI_convI2L" %} ++ ins_encode (load_I_enc(dst, mem)); ++ ins_pipe( ialu_loadI ); ++%} ++ ++// Load Integer (32 bit signed) to Byte (8 bit signed) ++instruct loadI2B(mRegI dst, memory mem, immI_24 twentyfour) %{ ++ match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); ++ ++ ins_cost(125); ++ format %{ "ldb_signed $dst, $mem\t# int -> byte #@loadI2B" %} ++ ins_encode(load_B_enc(dst, mem)); ++ ins_pipe(ialu_loadI); ++%} ++ ++// Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned) ++instruct loadI2UB(mRegI dst, memory mem, immI_255 mask) %{ ++ match(Set dst (AndI (LoadI mem) mask)); ++ ++ ins_cost(125); ++ format %{ "ldbu $dst, $mem\t# int -> ubyte #@loadI2UB" %} ++ ins_encode(load_UB_enc(dst, mem)); ++ ins_pipe(ialu_loadI); ++%} ++ ++// Load Integer (32 bit signed) to Short (16 bit signed) ++instruct loadI2S(mRegI dst, memory mem, immI_16 sixteen) %{ ++ match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); ++ ++ ins_cost(125); ++ format %{ "ldh $dst, $mem\t# int -> short #@loadI2S" %} ++ ins_encode(load_S_enc(dst, mem)); ++ ins_pipe(ialu_loadI); ++%} ++ ++// Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned) ++instruct loadI2US(mRegI dst, memory mem, immI_65535 mask) %{ ++ match(Set dst (AndI (LoadI mem) mask)); ++ ++ ins_cost(125); ++ format %{ "ldhu $dst, $mem\t# int -> ushort/char #@loadI2US" %} ++ ins_encode(load_C_enc(dst, mem)); ++ ins_pipe(ialu_loadI); ++%} ++ ++// Load Long. ++instruct loadL(mRegL dst, memory mem) %{ ++// predicate(!((LoadLNode*)n)->require_atomic_access()); ++ match(Set dst (LoadL mem)); ++ ++ ins_cost(250); ++ format %{ "ldl $dst, $mem #@loadL" %} ++ ins_encode %{ ++ if (UseGetLongIntrinsic) { ++ MacroAssembler _masm(&cbuf); ++ int base = $mem$$base; ++ int disp = $mem$$disp; ++ Register dst_reg = as_Register($dst$$reg); ++ Register tem1 = AT; ++ Register tem2 = GP; ++ ++ // For implicit null check ++ __ ldbu(tem1, as_Register(base), disp); ++ ++ __ li32(tem2, disp); ++ __ addl(tem1, as_Register(base), tem2); ++ __ ldl_u(tem2, tem1, 0); // load long whether the data is aligned or not ++ __ ldl_u(dst_reg, tem1, 7); ++ __ extll(tem2, tem2, tem1); ++ __ exthl(dst_reg, dst_reg, tem1); ++ __ or_ins(dst_reg, tem2, dst_reg); ++ } else { ++ MacroAssembler _masm(&cbuf); ++ int base = $mem$$base; ++ int disp = $mem$$disp; ++ Register dst_reg = as_Register($dst$$reg); ++ ++ // For implicit null check ++ __ ldbu(AT, as_Register(base), disp); ++ ++ if( Assembler::is_simm16(disp) ) { ++ __ ldl(dst_reg, as_Register(base), disp); ++ } else { ++ Unimplemented(); ++ } ++ } ++ %} ++ ins_pipe( ialu_loadL ); ++%} ++ ++// Load Long - UNaligned ++instruct loadL_unaligned(mRegL dst, memory mem) %{ ++ match(Set dst (LoadL_unaligned mem)); ++ ++ ins_cost(450); ++ format %{ "ldl $dst, $mem #@loadL_unaligned\n\t" %} ++ ins_encode(load_L_enc(dst, mem)); ++ ins_pipe( ialu_loadL ); ++%} ++ ++// Store Long ++instruct storeL_reg(memory mem, mRegL src) %{ ++ match(Set mem (StoreL mem src)); ++ ++ ins_cost(200); ++ format %{ "stl $mem, $src #@storeL_reg\n" %} ++ ins_encode(store_L_reg_enc(mem, src)); ++ ins_pipe( ialu_storeL ); ++%} ++ ++instruct storeL_immL0(memory mem, immL0 zero) %{ ++ match(Set mem (StoreL mem zero)); ++ ++ ins_cost(180); ++ format %{ "stl zero, $mem #@storeL_immL0" %} ++ ins_encode(store_L_immL0_enc(mem, zero)); ++ ins_pipe( ialu_storeL ); ++%} ++ ++// Load Compressed Pointer ++instruct loadN(mRegN dst, memory mem) ++%{ ++ match(Set dst (LoadN mem)); ++ ++ ins_cost(125); // XXX ++ format %{ "ldwu $dst, $mem\t# compressed ptr @ loadN" %} ++ ins_encode (load_N_enc(dst, mem)); ++ ins_pipe( ialu_loadI ); // XXX ++%} ++ ++instruct loadN2P(mRegP dst, memory mem) ++%{ ++ match(Set dst (DecodeN (LoadN mem))); ++ predicate(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0); ++ ++ ins_cost(125); // XXX ++ format %{ "ldwu $dst, $mem\t# @ loadN2P" %} ++ ins_encode (load_N_enc(dst, mem)); ++ ins_pipe( ialu_loadI ); // XXX ++%} ++ ++// Load Pointer ++instruct loadP(mRegP dst, memory mem) %{ ++ match(Set dst (LoadP mem)); ++ ++ ins_cost(125); ++ format %{ "ldl $dst, $mem #@loadP" %} ++ ins_encode (load_P_enc(dst, mem)); ++ ins_pipe( ialu_loadI ); ++%} ++ ++// Load Klass Pointer ++instruct loadKlass(mRegP dst, memory mem) %{ ++ match(Set dst (LoadKlass mem)); ++ ++ ins_cost(125); ++ format %{ "MOV $dst,$mem @ loadKlass" %} ++ ins_encode (load_P_enc(dst, mem)); ++ ins_pipe( ialu_loadI ); ++%} ++ ++// Load narrow Klass Pointer ++instruct loadNKlass(mRegN dst, memory mem) ++%{ ++ match(Set dst (LoadNKlass mem)); ++ ++ ins_cost(125); // XXX ++ format %{ "ldwu $dst, $mem\t# compressed klass ptr @ loadNKlass" %} ++ ins_encode (load_N_enc(dst, mem)); ++ ins_pipe( ialu_loadI ); // XXX ++%} ++ ++instruct loadN2PKlass(mRegP dst, memory mem) ++%{ ++ match(Set dst (DecodeNKlass (LoadNKlass mem))); ++ predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0); ++ ++ ins_cost(125); // XXX ++ format %{ "ldwu $dst, $mem\t# compressed klass ptr @ loadN2PKlass" %} ++ ins_encode (load_N_enc(dst, mem)); ++ ins_pipe( ialu_loadI ); // XXX ++%} ++ ++// Load Constant ++instruct loadConI(mRegI dst, immI src) %{ ++ match(Set dst src); ++ ++ ins_cost(150); ++ format %{ "mov $dst, $src #@loadConI" %} ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ int value = $src$$constant; ++ __ move(dst, value); ++ %} ++ ins_pipe( ialu_regI_regI ); ++%} ++ ++ ++instruct loadConL_set64(mRegL dst, immL src) %{ ++ match(Set dst src); ++ ins_cost(120); ++ format %{ "li $dst, $src @ loadConL_set64" %} ++ ins_encode %{ ++ __ set64($dst$$Register, $src$$constant); ++ %} ++ ins_pipe(ialu_regL_regL); ++%} ++ ++ ++instruct loadConL16(mRegL dst, immL16 src) %{ ++ match(Set dst src); ++ ins_cost(105); ++ format %{ "mov $dst, $src #@loadConL16" %} ++ ins_encode %{ ++ Register dst_reg = as_Register($dst$$reg); ++ int value = $src$$constant; ++ __ add_simm16(dst_reg, R0, value); ++ %} ++ ins_pipe( ialu_regL_regL ); ++%} ++ ++ ++instruct loadConL0(mRegL dst, immL0 src) %{ ++ match(Set dst src); ++ ins_cost(100); ++ format %{ "mov $dst, zero #@loadConL0" %} ++ ins_encode %{ ++ Register dst_reg = as_Register($dst$$reg); ++ __ addl(dst_reg, R0, R0); ++ %} ++ ins_pipe( ialu_regL_regL ); ++%} ++ ++// Load Range ++instruct loadRange(mRegI dst, memory mem) %{ ++ match(Set dst (LoadRange mem)); ++ ++ ins_cost(125); ++ format %{ "MOV $dst,$mem @ loadRange" %} ++ ins_encode(load_I_enc(dst, mem)); ++ ins_pipe( ialu_loadI ); ++%} ++ ++ ++instruct storeP(memory mem, mRegP src ) %{ ++ match(Set mem (StoreP mem src)); ++ ++ ins_cost(125); ++ format %{ "stl $src, $mem #@storeP" %} ++ ins_encode(store_P_reg_enc(mem, src)); ++ ins_pipe( ialu_storeI ); ++%} ++ ++// Store NULL Pointer, mark word, or other simple pointer constant. ++instruct storeImmP0(memory mem, immP0 zero) %{ ++ match(Set mem (StoreP mem zero)); ++ ++ ins_cost(125); ++ format %{ "mov $mem, $zero #@storeImmP0" %} ++ ins_encode(store_P_immP0_enc(mem)); ++ ins_pipe( ialu_storeI ); ++%} ++ ++// Store Compressed Pointer ++instruct storeN(memory mem, mRegN src) ++%{ ++ match(Set mem (StoreN mem src)); ++ ++ ins_cost(125); // XXX ++ format %{ "stw $mem, $src\t# compressed ptr @ storeN" %} ++ ins_encode(store_N_reg_enc(mem, src)); ++ ins_pipe( ialu_storeI ); ++%} ++ ++instruct storeP2N(memory mem, mRegP src) ++%{ ++ match(Set mem (StoreN mem (EncodeP src))); ++ predicate(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0); ++ ++ ins_cost(125); // XXX ++ format %{ "stw $mem, $src\t# @ storeP2N" %} ++ ins_encode(store_N_reg_enc(mem, src)); ++ ins_pipe( ialu_storeI ); ++%} ++ ++instruct storeNKlass(memory mem, mRegN src) ++%{ ++ match(Set mem (StoreNKlass mem src)); ++ ++ ins_cost(125); // XXX ++ format %{ "stw $mem, $src\t# compressed klass ptr @ storeNKlass" %} ++ ins_encode(store_N_reg_enc(mem, src)); ++ ins_pipe( ialu_storeI ); ++%} ++ ++instruct storeP2NKlass(memory mem, mRegP src) ++%{ ++ match(Set mem (StoreNKlass mem (EncodePKlass src))); ++ predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0); ++ ++ ins_cost(125); // XXX ++ format %{ "stw $mem, $src\t# @ storeP2NKlass" %} ++ ins_encode(store_N_reg_enc(mem, src)); ++ ins_pipe( ialu_storeI ); ++%} ++ ++instruct storeImmN0(memory mem, immN0 zero) ++%{ ++ match(Set mem (StoreN mem zero)); ++ ++ ins_cost(125); // XXX ++ format %{ "storeN0 zero, $mem\t# compressed ptr" %} ++ ins_encode(storeImmN0_enc(mem, zero)); ++ ins_pipe( ialu_storeI ); ++%} ++ ++// Store Byte ++instruct storeB(memory mem, mRegI src) %{ ++ match(Set mem (StoreB mem src)); ++ ++ ins_cost(125); ++ format %{ "stb $src, $mem #@storeB" %} ++ ins_encode(store_B_reg_enc(mem, src)); ++ ins_pipe( ialu_storeI ); ++%} ++ ++instruct storeB_convL2I(memory mem, mRegL src) %{ ++ match(Set mem (StoreB mem (ConvL2I src))); ++ ++ ins_cost(125); ++ format %{ "stb $src, $mem #@storeB_convL2I" %} ++ ins_encode(store_B_reg_enc(mem, src)); ++ ins_pipe( ialu_storeI ); ++%} ++ ++// Load Byte (8bit signed) ++instruct loadB(mRegI dst, memory mem) %{ ++ match(Set dst (LoadB mem)); ++ ++ ins_cost(125); ++ format %{ "ldbu $dst, $mem #@loadB" %} ++ ins_encode(load_B_enc(dst, mem)); ++ ins_pipe( ialu_loadI ); ++%} ++ ++instruct loadB_convI2L(mRegL dst, memory mem) %{ ++ match(Set dst (ConvI2L (LoadB mem))); ++ ++ ins_cost(125); ++ format %{ "ldb_signed $dst, $mem #@loadB_convI2L" %} ++ ins_encode(load_B_enc(dst, mem)); ++ ins_pipe( ialu_loadI ); ++%} ++ ++// Load Byte (8bit UNsigned) ++instruct loadUB(mRegI dst, memory mem) %{ ++ match(Set dst (LoadUB mem)); ++ ++ ins_cost(125); ++ format %{ "lbu $dst, $mem #@loadUB" %} ++ ins_encode(load_UB_enc(dst, mem)); ++ ins_pipe( ialu_loadI ); ++%} ++ ++instruct loadUB_convI2L(mRegL dst, memory mem) %{ ++ match(Set dst (ConvI2L (LoadUB mem))); ++ ++ ins_cost(125); ++ format %{ "ldbu $dst, $mem #@loadUB_convI2L" %} ++ ins_encode(load_UB_enc(dst, mem)); ++ ins_pipe( ialu_loadI ); ++%} ++ ++// Load Short (16bit signed) ++instruct loadS(mRegI dst, memory mem) %{ ++ match(Set dst (LoadS mem)); ++ ++ ins_cost(125); ++ format %{ "ldh $dst, $mem #@loadS" %} ++ ins_encode(load_S_enc(dst, mem)); ++ ins_pipe( ialu_loadI ); ++%} ++ ++// Load Short (16 bit signed) to Byte (8 bit signed) ++instruct loadS2B(mRegI dst, memory mem, immI_24 twentyfour) %{ ++ match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); ++ ++ ins_cost(125); ++ format %{ "ldb_signed $dst, $mem\t# short -> byte #@loadS2B" %} ++ ins_encode(load_B_enc(dst, mem)); ++ ins_pipe(ialu_loadI); ++%} ++ ++instruct loadS_convI2L(mRegL dst, memory mem) %{ ++ match(Set dst (ConvI2L (LoadS mem))); ++ ++ ins_cost(125); ++ format %{ "ldh $dst, $mem #@loadS_convI2L" %} ++ ins_encode(load_S_enc(dst, mem)); ++ ins_pipe( ialu_loadI ); ++%} ++ ++// Store Integer Immediate 0 ++instruct storeImmI0(memory mem, immI0 src) %{ ++ match(Set mem (StoreI mem src)); ++ ++ ins_cost(150); ++ format %{ "mov $mem, $src #@storeImmI0" %} ++ ins_encode(store_I_immI0_enc(mem, src)); ++ ins_pipe( ialu_storeI ); ++%} ++ ++// Store Integer ++instruct storeI(memory mem, mRegI src) %{ ++ match(Set mem (StoreI mem src)); ++ ++ ins_cost(125); ++ format %{ "stw $mem, $src #@storeI" %} ++ ins_encode(store_I_reg_enc(mem, src)); ++ ins_pipe( ialu_storeI ); ++%} ++ ++instruct storeI_convL2I(memory mem, mRegL src) %{ ++ match(Set mem (StoreI mem (ConvL2I src))); ++ ++ ins_cost(125); ++ format %{ "stw $mem, $src #@storeI_convL2I" %} ++ ins_encode(store_I_reg_enc(mem, src)); ++ ins_pipe( ialu_storeI ); ++%} ++ ++// Load Float ++instruct loadF(regF dst, memory mem) %{ ++ match(Set dst (LoadF mem)); ++ ++ ins_cost(150); ++ format %{ "loadF $dst, $mem #@loadF" %} ++ ins_encode(load_F_enc(dst, mem)); ++ ins_pipe( ialu_loadI ); ++%} ++ ++instruct loadConP_general(mRegP dst, immP src) %{ ++ match(Set dst src); ++ ++ ins_cost(120); ++ format %{ "li $dst, $src #@loadConP_general" %} ++ ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ long* value = (long*)$src$$constant; ++ ++ if($src->constant_reloc() == relocInfo::metadata_type){ ++ int klass_index = __ oop_recorder()->find_index((Klass*)value); ++ RelocationHolder rspec = metadata_Relocation::spec(klass_index); ++ ++ __ relocate(rspec); ++ __ patchable_set48(dst, (long)value); ++ }else if($src->constant_reloc() == relocInfo::oop_type){ ++ int oop_index = __ oop_recorder()->find_index((jobject)value); ++ RelocationHolder rspec = oop_Relocation::spec(oop_index); ++ ++ __ relocate(rspec); ++ __ patchable_set48(dst, (long)value); ++ } else if ($src->constant_reloc() == relocInfo::none) { ++ __ set64(dst, (long)value); ++ } ++ %} ++ ++ ins_pipe( ialu_regI_regI ); ++%} ++ ++ ++instruct loadConP_no_oop_cheap(mRegP dst, immP_no_oop_cheap src) %{ ++ match(Set dst src); ++ ++ ins_cost(80); ++ format %{ "li $dst, $src @ loadConP_no_oop_cheap" %} ++ ++ ins_encode %{ ++ __ set64($dst$$Register, $src$$constant); ++ %} ++ ++ ins_pipe(ialu_regI_regI); ++%} ++ ++ ++instruct loadConP_poll(mRegP dst, immP_poll src) %{ ++ match(Set dst src); ++ ++ ins_cost(50); ++ format %{ "li $dst, $src #@loadConP_poll" %} ++ ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ intptr_t value = (intptr_t)$src$$constant; ++ ++ __ set64(dst, (jlong)value); ++ %} ++ ++ ins_pipe( ialu_regI_regI ); ++%} ++ ++instruct loadConP0(mRegP dst, immP0 src) ++%{ ++ match(Set dst src); ++ ++ ins_cost(50); ++ format %{ "mov $dst, R0\t# ptr" %} ++ ins_encode %{ ++ Register dst_reg = $dst$$Register; ++ __ addl(dst_reg, R0, R0); ++ %} ++ ins_pipe( ialu_regI_regI ); ++%} ++ ++instruct loadConN0(mRegN dst, immN0 src) %{ ++ match(Set dst src); ++ format %{ "move $dst, R0\t# compressed NULL ptr" %} ++ ins_encode %{ ++ __ move($dst$$Register, R0); ++ %} ++ ins_pipe( ialu_regI_regI ); ++%} ++ ++instruct loadConN(mRegN dst, immN src) %{ ++ match(Set dst src); ++ ++ ins_cost(125); ++ format %{ "li $dst, $src\t# compressed ptr @ loadConN" %} ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ __ set_narrow_oop(dst, (jobject)$src$$constant); ++ %} ++ ins_pipe( ialu_regI_regI ); // XXX ++%} ++ ++instruct loadConNKlass(mRegN dst, immNKlass src) %{ ++ match(Set dst src); ++ ++ ins_cost(125); ++ format %{ "li $dst, $src\t# compressed klass ptr @ loadConNKlass" %} ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ __ set_narrow_klass(dst, (Klass*)$src$$constant); ++ %} ++ ins_pipe( ialu_regI_regI ); // XXX ++%} ++ ++ ++// Tail Call; Jump from runtime stub to Java code. ++// Also known as an 'interprocedural jump'. ++// Target of jump will eventually return to caller. ++// TailJump below removes the return address. ++instruct TailCalljmpInd(mRegP jump_target, mRegP method_oop) %{ ++ match(TailCall jump_target method_oop ); ++ ins_cost(300); ++ format %{ "JMP $jump_target \t# @TailCalljmpInd" %} ++ ++ ins_encode %{ ++ Register target = $jump_target$$Register; ++ Register oop = $method_oop$$Register; ++ ++ // RA will be used in generate_forward_exception() ++ __ push(RA); ++ ++ __ move(S3, oop); ++ __ jmp(target); ++ %} ++ ++ ins_pipe( pipe_jump ); ++%} ++ ++// Create exception oop: created by stack-crawling runtime code. ++// Created exception is now available to this handler, and is setup ++// just prior to jumping to this handler. No code emitted. ++instruct CreateException( a0_RegP ex_oop ) ++%{ ++ match(Set ex_oop (CreateEx)); ++ ++ // use the following format syntax ++ format %{ "# exception oop is in A0; no code emitted @CreateException" %} ++ ins_encode %{ ++ // SW64 leaves this function empty ++ __ block_comment("CreateException is empty in SW64"); ++ %} ++ ins_pipe( empty ); ++%} ++ ++// The exception oop will come in the first argument position. ++// Then JUMP (not call) to the rethrow stub code. ++instruct RethrowException() ++%{ ++ match(Rethrow); ++ ++ // use the following format syntax ++ format %{ "JMP rethrow_stub #@RethrowException" %} ++ ins_encode %{ ++ __ block_comment("@ RethrowException"); ++ ++ cbuf.set_insts_mark(); ++ cbuf.relocate(cbuf.insts_mark(), runtime_call_Relocation::spec()); ++ ++ // call OptoRuntime::rethrow_stub to get the exception handler in parent method ++ __ patchable_jump((address)OptoRuntime::rethrow_stub()); ++ %} ++ ins_pipe( pipe_jump ); ++%} ++ ++//SW64:OKOK: ++instruct branchConP_zero(cmpOpU cmp, mRegP op1, immP0 zero, label labl) %{ ++ match(If cmp (CmpP op1 zero)); ++ effect(USE labl); ++ ++ ins_cost(180); ++ format %{ "b$cmp $op1, R0, $labl #@branchConP_zero_short" %} ++ ++ ins_encode %{ ++ Register op1 = $op1$$Register; ++ Register op2 = R0; ++ Label &L = *($labl$$label); ++ int flag = $cmp$$cmpcode; ++ ++ switch(flag) { ++ case 0x01: //equal ++ if (&L) ++ __ beq(op1, op2, L); ++ else ++ __ beq(op1, op2, (int)0); ++ break; ++ case 0x02: //not_equal ++ if (&L) ++ __ bne(op1, op2, L); ++ else ++ __ bne(op1, op2, (int)0); ++ break; ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pc_relative(1); ++ ins_pipe( pipe_alu_branch ); ++%} ++ ++instruct branchConN2P_zero_short(cmpOpU cmp, mRegN op1, immP0 zero, label labl) %{ ++ match(If cmp (CmpP (DecodeN op1) zero)); ++ predicate(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0); ++ effect(USE labl); ++ ++ ins_cost(180); ++ format %{ "b$cmp $op1, R0, $labl #@branchConN2P_zero_short" %} ++ ++ ins_encode %{ ++ Register op1 = $op1$$Register; ++ Register op2 = R0; ++ Label &L = *($labl$$label); ++ int flag = $cmp$$cmpcode; ++ ++ switch(flag) ++ { ++ case 0x01: //equal ++ if (&L) ++ __ beq(op1, op2, L); ++ else ++ __ beq(op1, op2, (int)0); ++ break; ++ case 0x02: //not_equal ++ if (&L) ++ __ bne(op1, op2, L); ++ else ++ __ bne(op1, op2, (int)0); ++ break; ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pc_relative(1); ++ ins_pipe( pipe_alu_branch ); ++%} ++ ++ ++instruct branchConP_short(cmpOpU cmp, mRegP op1, mRegP op2, label labl) %{ ++ match(If cmp (CmpP op1 op2)); ++// predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); ++ effect(USE labl); ++ ++ ins_cost(200); ++ format %{ "b$cmp $op1, $op2, $labl #@branchConP_short" %} ++ ++ ins_encode %{ ++ Register op1 = $op1$$Register; ++ Register op2 = $op2$$Register; ++ Label &L = *($labl$$label); ++ int flag = $cmp$$cmpcode; ++ ++ switch(flag) { ++ case 0x01: //equal ++ if (&L) ++ __ beq(op1, op2, L); ++ else ++ __ beq(op1, op2, (int)0); ++ break; ++ case 0x02: //not_equal ++ if (&L) ++ __ bne(op1, op2, L); ++ else ++ __ bne(op1, op2, (int)0); ++ break; ++ case 0x03: //above ++ __ cmpult(AT, op2, op1); ++ if(&L) ++ __ bne(AT, L); ++ else ++ __ bne(AT, (int)0); ++ break; ++ case 0x04: //above_equal ++ __ cmpult(AT, op1, op2); ++ if(&L) ++ __ beq(AT, L); ++ else ++ __ beq(AT, (int)0); ++ break; ++ case 0x05: //below ++ __ cmpult(AT, op1, op2); ++ if(&L) ++ __ bne(AT, L); ++ else ++ __ bne(AT, (int)0); ++ break; ++ case 0x06: //below_equal ++ __ cmpult(AT, op2, op1); ++ if(&L) ++ __ beq(AT, L); ++ else ++ __ beq(AT, (int)0); ++ break; ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pc_relative(1); ++ ins_pipe( pipe_alu_branch ); ++%} ++ ++instruct cmpN_null_branch_short(cmpOp cmp, mRegN op1, immN0 null, label labl) %{ ++ match(If cmp (CmpN op1 null)); ++ effect(USE labl); ++ ++ ins_cost(180); ++ format %{ "CMP $op1,0\t! compressed ptr\n\t" ++ "BP$cmp $labl @ cmpN_null_branch_short" %} ++ ins_encode %{ ++ Register op1 = $op1$$Register; ++ Register op2 = R0; ++ Label &L = *($labl$$label); ++ int flag = $cmp$$cmpcode; ++ ++ switch(flag) { ++ case 0x01: //equal ++ if (&L) ++ __ beq(op1, op2, L); ++ else ++ __ beq(op1, op2, (int)0); ++ break; ++ case 0x02: //not_equal ++ if (&L) ++ __ bne(op1, op2, L); ++ else ++ __ bne(op1, op2, (int)0); ++ break; ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++//TODO: pipe_branchP or create pipe_branchN LEE ++ ins_pc_relative(1); ++ ins_pipe( pipe_alu_branch ); ++%} ++ ++instruct cmpN_reg_branch_short(cmpOp cmp, mRegN op1, mRegN op2, label labl) %{ ++ match(If cmp (CmpN op1 op2)); ++ effect(USE labl); ++ ++ ins_cost(180); ++ format %{ "CMP $op1,$op2\t! compressed ptr\n\t" ++ "BP$cmp $labl @ cmpN_reg_branch_short" %} ++ ins_encode %{ ++ Register op1_reg = $op1$$Register; ++ Register op2_reg = $op2$$Register; ++ Label &L = *($labl$$label); ++ int flag = $cmp$$cmpcode; ++ ++ switch(flag) { ++ case 0x01: //equal ++ if (&L) ++ __ beq(op1_reg, op2_reg, L); ++ else ++ __ beq(op1_reg, op2_reg, (int)0); ++ break; ++ case 0x02: //not_equal ++ if (&L) ++ __ bne(op1_reg, op2_reg, L); ++ else ++ __ bne(op1_reg, op2_reg, (int)0); ++ break; ++ case 0x03: //above ++ __ cmpult(AT, op2_reg, op1_reg); ++ if(&L) ++ __ bne(AT, L); ++ else ++ __ bne(AT, (int)0); ++ break; ++ case 0x04: //above_equal ++ __ cmpult(AT, op1_reg, op2_reg); ++ if(&L) ++ __ beq(AT, L); ++ else ++ __ beq(AT, (int)0); ++ break; ++ case 0x05: //below ++ __ cmpult(AT, op1_reg, op2_reg); ++ if(&L) ++ __ bne(AT, L); ++ else ++ __ bne(AT, (int)0); ++ break; ++ case 0x06: //below_equal ++ __ cmpult(AT, op2_reg, op1_reg); ++ if(&L) ++ __ beq(AT, L); ++ else ++ __ beq(AT, (int)0); ++ break; ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pc_relative(1); ++ ins_pipe( pipe_alu_branch ); ++%} ++ ++instruct branchConIU_reg_reg_short(cmpOpU cmp, mRegI src1, mRegI src2, label labl) %{ ++ match( If cmp (CmpU src1 src2) ); ++ effect(USE labl); ++ format %{ "BR$cmp $src1, $src2, $labl #@branchConIU_reg_reg_short" %} ++ ++ ins_encode %{ ++ Register op1 = $src1$$Register; ++ Register op2 = $src2$$Register; ++ Label &L = *($labl$$label); ++ int flag = $cmp$$cmpcode; ++ ++ switch(flag) { ++ case 0x01: //equal ++ if (&L) ++ __ beq(op1, op2, L); ++ else ++ __ beq(op1, op2, (int)0); ++ break; ++ case 0x02: //not_equal ++ if (&L) ++ __ bne(op1, op2, L); ++ else ++ __ bne(op1, op2, (int)0); ++ break; ++ case 0x03: //above ++ __ cmpult(AT, op2, op1); ++ if(&L) ++ __ bne(AT, L); ++ else ++ __ bne(AT, (int)0); ++ break; ++ case 0x04: //above_equal ++ __ cmpult(AT, op1, op2); ++ if(&L) ++ __ beq(AT, L); ++ else ++ __ beq(AT, (int)0); ++ break; ++ case 0x05: //below ++ __ cmpult(AT, op1, op2); ++ if(&L) ++ __ bne(AT, L); ++ else ++ __ bne(AT, (int)0); ++ break; ++ case 0x06: //below_equal ++ __ cmpult(AT, op2, op1); ++ if(&L) ++ __ beq(AT, L); ++ else ++ __ beq(AT, (int)0); ++ break; ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pc_relative(1); ++ ins_pipe( pipe_alu_branch ); ++%} ++ ++ ++instruct branchConIU_reg_imm_short(cmpOpU cmp, mRegI src1, immI src2, label labl) %{ ++ match( If cmp (CmpU src1 src2) ); ++ effect(USE labl); ++ format %{ "BR$cmp $src1, $src2, $labl #@branchConIU_reg_imm_short" %} ++ ++ ins_encode %{ ++ Register op1 = $src1$$Register; ++ int val = $src2$$constant; ++ Label &L = *($labl$$label); ++ int flag = $cmp$$cmpcode; ++ ++ __ move(AT, val); ++ switch(flag) { ++ case 0x01: //equal ++ if (&L) ++ __ beq(op1, AT, L); ++ else ++ __ beq(op1, AT, (int)0); ++ break; ++ case 0x02: //not_equal ++ if (&L) ++ __ bne(op1, AT, L); ++ else ++ __ bne(op1, AT, (int)0); ++ break; ++ case 0x03: //above ++ __ cmpult(AT, AT, op1); ++ if(&L) ++ __ bne(AT, L); ++ else ++ __ bne(AT, (int)0); ++ break; ++ case 0x04: //above_equal ++ __ cmpult(AT, op1, AT); ++ if(&L) ++ __ beq(AT, L); ++ else ++ __ beq(AT, (int)0); ++ break; ++ case 0x05: //below ++ __ cmpult(AT, op1, AT); ++ if(&L) ++ __ bne(AT, L); ++ else ++ __ bne(AT, (int)0); ++ break; ++ case 0x06: //below_equal ++ __ cmpult(AT, AT, op1); ++ if(&L) ++ __ beq(AT, L); ++ else ++ __ beq(AT, (int)0); ++ break; ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pc_relative(1); ++ ins_pipe( pipe_alu_branch ); ++%} ++ ++instruct branchConI_reg_reg_short(cmpOp cmp, mRegI src1, mRegI src2, label labl) %{ ++ match( If cmp (CmpI src1 src2) ); ++ effect(USE labl); ++ format %{ "BR$cmp $src1, $src2, $labl #@branchConI_reg_reg_short" %} ++ ++ ins_encode %{ ++ Register op1 = $src1$$Register; ++ Register op2 = $src2$$Register; ++ Label &L = *($labl$$label); ++ int flag = $cmp$$cmpcode; ++ ++ switch(flag) { ++ case 0x01: //equal ++ if (&L) ++ __ beq(op1, op2, L); ++ else ++ __ beq(op1, op2, (int)0); ++ break; ++ case 0x02: //not_equal ++ if (&L) ++ __ bne(op1, op2, L); ++ else ++ __ bne(op1, op2, (int)0); ++ break; ++ case 0x03: //above ++ __ cmplt(AT, op2, op1); ++ if(&L) ++ __ bne(AT, L); ++ else ++ __ bne(AT, (int)0); ++ break; ++ case 0x04: //above_equal ++ __ cmplt(AT, op1, op2); ++ if(&L) ++ __ beq(AT, L); ++ else ++ __ beq(AT, (int)0); ++ break; ++ case 0x05: //below ++ __ cmplt(AT, op1, op2); ++ if(&L) ++ __ bne(AT, L); ++ else ++ __ bne(AT, (int)0); ++ break; ++ case 0x06: //below_equal ++ __ cmplt(AT, op2, op1); ++ if(&L) ++ __ beq(AT, L); ++ else ++ __ beq(AT, (int)0); ++ break; ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pc_relative(1); ++ ins_pipe( pipe_alu_branch ); ++%} ++ ++instruct branchConI_reg_imm0_short(cmpOp cmp, mRegI src1, immI0 src2, label labl) %{ ++ match( If cmp (CmpI src1 src2) ); ++ effect(USE labl); ++ ins_cost(170); ++ format %{ "BR$cmp $src1, $src2, $labl #@branchConI_reg_imm0_short" %} ++ ++ ins_encode %{ ++ Register op1 = $src1$$Register; ++ Label &L = *($labl$$label); ++ int flag = $cmp$$cmpcode; ++ ++ switch(flag) { ++ case 0x01: //equal ++ if (&L) ++ __ beq(op1, L); ++ else ++ __ beq(op1, (int)0); ++ break; ++ case 0x02: //not_equal ++ if (&L) ++ __ bne(op1, L); ++ else ++ __ bne(op1, (int)0); ++ break; ++ case 0x03: //greater ++ if(&L) ++ __ bgt(op1, L); ++ else ++ __ bgt(op1, (int)0); ++ break; ++ case 0x04: //greater_equal ++ if(&L) ++ __ bge(op1, L); ++ else ++ __ bge(op1, (int)0); ++ break; ++ case 0x05: //less ++ if(&L) ++ __ blt(op1, L); ++ else ++ __ blt(op1, (int)0); ++ break; ++ case 0x06: //less_equal ++ if(&L) ++ __ ble(op1, L); ++ else ++ __ ble(op1, (int)0); ++ break; ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pc_relative(1); ++ ins_pipe( pipe_alu_branch ); ++%} ++ ++ ++instruct branchConI_reg_imm_short(cmpOp cmp, mRegI src1, immI src2, label labl) %{ ++ match( If cmp (CmpI src1 src2) ); ++ effect(USE labl); ++ ins_cost(200); ++ format %{ "BR$cmp $src1, $src2, $labl #@branchConI_reg_imm_short" %} ++ ++ ins_encode %{ ++ Register op1 = $src1$$Register; ++ int val = $src2$$constant; ++ Label &L = *($labl$$label); ++ int flag = $cmp$$cmpcode; ++ ++ __ move(AT, val); ++ switch(flag) { ++ case 0x01: //equal ++ if (&L) ++ __ beq(op1, AT, L); ++ else ++ __ beq(op1, AT, (int)0); ++ break; ++ case 0x02: //not_equal ++ if (&L) ++ __ bne(op1, AT, L); ++ else ++ __ bne(op1, AT, (int)0); ++ break; ++ case 0x03: //greater ++ __ cmplt(AT, AT, op1); ++ if(&L) ++ __ bne(AT, L); ++ else ++ __ bne(AT, (int)0); ++ break; ++ case 0x04: //greater_equal ++ __ cmplt(AT, op1, AT); ++ if(&L) ++ __ beq(AT, L); ++ else ++ __ beq(AT, (int)0); ++ break; ++ case 0x05: //less ++ __ cmplt(AT, op1, AT); ++ if(&L) ++ __ bne(AT, L); ++ else ++ __ bne(AT, (int)0); ++ break; ++ case 0x06: //less_equal ++ __ cmplt(AT, AT, op1); ++ if(&L) ++ __ beq(AT, L); ++ else ++ __ beq(AT, (int)0); ++ break; ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pc_relative(1); ++ ins_pipe( pipe_alu_branch ); ++%} ++ ++instruct branchConIU_reg_imm0_short(cmpOpU cmp, mRegI src1, immI0 zero, label labl) %{ ++ match( If cmp (CmpU src1 zero) ); ++ effect(USE labl); ++ format %{ "BR$cmp $src1, zero, $labl #@branchConIU_reg_imm0_short" %} ++ ++ ins_encode %{ ++ Register op1 = $src1$$Register; ++ Label &L = *($labl$$label); ++ int flag = $cmp$$cmpcode; ++ ++ switch(flag) { ++ case 0x01: //equal ++ if (&L) ++ __ beq(op1, L); ++ else ++ __ beq(op1, (int)0); ++ break; ++ case 0x02: //not_equal ++ if (&L) ++ __ bne(op1, L); ++ else ++ __ bne(op1, (int)0); ++ break; ++ case 0x03: //above ++ if(&L) ++ __ bne(op1, L); ++ else ++ __ bne(op1, (int)0); ++ break; ++ case 0x04: //above_equal ++ if(&L) ++ __ beq(R0, L); ++ else ++ __ beq(R0, (int)0); ++ break; ++ case 0x05: //below ++ return; ++ break; ++ case 0x06: //below_equal ++ if(&L) ++ __ beq(op1, L); ++ else ++ __ beq(op1, (int)0); ++ break; ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pc_relative(1); ++ ins_pipe( pipe_alu_branch ); ++%} ++ ++////instruct branchConIU_reg_imm_0_255(cmpOpU cmp, mRegI src1, immI_0_255 src2, label labl) %{ ++//// match( If cmp (CmpU src1 src2) ); ++//// effect(USE labl); ++//// ins_cost(180); ++//// format %{ "BR$cmp $src1, $src2, $labl #@branchConIU_reg_imm_0_255" %} ++//// ++//// ins_encode %{ ++//// Register op1 = $src1$$Register; ++//// int val = $src2$$constant; ++//// Label &L = *($labl$$label); ++//// int flag = $cmp$$cmpcode; ++//// ++//// __ subl(AT, op1, val); ++//// switch(flag) ++//// { ++//// case 0x01: //equal ++//// if (&L) ++//// __ beq(AT, L); ++//// else ++//// __ beq(AT, (int)0); ++//// break; ++//// case 0x02: //not_equal ++//// if (&L) ++//// __ bne(AT, L); ++//// else ++//// __ bne(AT, (int)0); ++//// break; ++//// case 0x03: //above ++//// if(&L) ++//// __ bgtz(AT, L); ++//// else ++//// __ bgt(AT, (int)0); ++//// break; ++//// case 0x04: //above_equal ++//// if(&L) ++//// __ bgez(AT, L); ++//// else ++//// __ bge(AT, (int)0); ++//// break; ++//// case 0x05: //below ++//// if(&L) ++//// __ bltz(AT, L); ++//// else ++//// __ blt(AT, (int)0); ++//// break; ++//// case 0x06: //below_equal ++//// if(&L) ++//// __ blez(AT, L); ++//// else ++//// __ ble(AT, (int)0); ++//// break; ++//// default: ++//// Unimplemented(); ++//// } ++//// %} ++//// ++//// ins_pc_relative(1); ++//// ins_pipe( pipe_alu_branch ); ++////%} ++ ++instruct branchConIU_reg_immI16_short(cmpOpU cmp, mRegI src1, immI16_sub src2, label labl) %{ ++ match( If cmp (CmpU src1 src2) ); ++ effect(USE labl); ++ ins_cost(180); ++ format %{ "BR$cmp $src1, $src2, $labl #@branchConIU_reg_immI16_short" %} ++ ++ ins_encode %{ ++ Register op1 = $src1$$Register; ++ int val = $src2$$constant; ++ Label &L = *($labl$$label); ++ int flag = $cmp$$cmpcode; ++ ++ __ add_simm16(AT, op1, -1 * val); ++ switch(flag) { ++ case 0x01: //equal ++ if (&L) ++ __ beq(AT, L); ++ else ++ __ beq(AT, (int)0); ++ break; ++ case 0x02: //not_equal ++ if (&L) ++ __ bne(AT, L); ++ else ++ __ bne(AT, (int)0); ++ break; ++ case 0x03: //above ++ if(&L) ++ __ bgt(AT, L); ++ else ++ __ bgt(AT, (int)0); ++ break; ++ case 0x04: //above_equal ++ if(&L) ++ __ bge(AT, L); ++ else ++ __ bge(AT, (int)0); ++ break; ++ case 0x05: //below ++ if(&L) ++ __ blt(AT, L); ++ else ++ __ blt(AT, (int)0); ++ break; ++ case 0x06: //below_equal ++ if(&L) ++ __ ble(AT, L); ++ else ++ __ ble(AT, (int)0); ++ break; ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pc_relative(1); ++ ins_pipe( pipe_alu_branch ); ++%} ++ ++ ++instruct branchConL_regL_regL_short(cmpOp cmp, mRegL src1, mRegL src2, label labl) %{ ++ match( If cmp (CmpL src1 src2) ); ++ effect(USE labl); ++ format %{ "BR$cmp $src1, $src2, $labl #@branchConL_regL_regL_short" %} ++ ins_cost(250); ++ ++ ins_encode %{ ++ Register opr1_reg = as_Register($src1$$reg); ++ Register opr2_reg = as_Register($src2$$reg); ++ ++ Label &target = *($labl$$label); ++ int flag = $cmp$$cmpcode; ++ ++ switch(flag) { ++ case 0x01: //equal ++ if (&target) ++ __ beq(opr1_reg, opr2_reg, target); ++ else ++ __ beq(opr1_reg, opr2_reg, (int)0); ++ break; ++ ++ case 0x02: //not_equal ++ if(&target) ++ __ bne(opr1_reg, opr2_reg, target); ++ else ++ __ bne(opr1_reg, opr2_reg, (int)0); ++ break; ++ ++ case 0x03: //greater ++ __ cmplt(AT, opr2_reg, opr1_reg); ++ if(&target) ++ __ bne(AT, target); ++ else ++ __ bne(AT, (int)0); ++ break; ++ ++ case 0x04: //greater_equal ++ __ cmplt(AT, opr1_reg, opr2_reg); ++ if(&target) ++ __ beq(AT, target); ++ else ++ __ beq(AT, (int)0); ++ break; ++ ++ case 0x05: //less ++ __ cmplt(AT, opr1_reg, opr2_reg); ++ if(&target) ++ __ bne(AT, target); ++ else ++ __ bne(AT, (int)0); ++ break; ++ ++ case 0x06: //less_equal ++ __ cmplt(AT, opr2_reg, opr1_reg); ++ if(&target) ++ __ beq(AT, target); ++ else ++ __ beq(AT, (int)0); ++ break; ++ ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pc_relative(1); ++ ins_pipe( pipe_alu_branch ); ++%} ++ ++////instruct branchConI_reg_imm_0_255_sub(cmpOp cmp, mRegI src1, immI_0_255 src2, label labl) %{ ++//// match( If cmp (CmpI src1 src2) ); ++//// effect(USE labl); ++//// ins_cost(180); ++//// format %{ "BR$cmp $src1, $src2, $labl #@branchConI_reg_imm_0_255_sub" %} ++//// ++//// ins_encode %{ ++//// Register op1 = $src1$$Register; ++//// int val = $src2$$constant; ++//// Label &L = *($labl$$label); ++//// int flag = $cmp$$cmpcode; ++//// ++//// __ subl(AT, op1, val); ++//// switch(flag) ++//// { ++//// case 0x01: //equal ++//// if (&L) ++//// __ beq(AT, L); ++//// else ++//// __ beq(AT, (int)0); ++//// break; ++//// case 0x02: //not_equal ++//// if (&L) ++//// __ bne(AT, L); ++//// else ++//// __ bne(AT, (int)0); ++//// break; ++//// case 0x03: //greater ++//// if(&L) ++//// __ bgtz(AT, L); ++//// else ++//// __ bgt(AT, (int)0); ++//// break; ++//// case 0x04: //greater_equal ++//// if(&L) ++//// __ bgez(AT, L); ++//// else ++//// __ bge(AT, (int)0); ++//// break; ++//// case 0x05: //less ++//// if(&L) ++//// __ bltz(AT, L); ++//// else ++//// __ blt(AT, (int)0); ++//// break; ++//// case 0x06: //less_equal ++//// if(&L) ++//// __ blez(AT, L); ++//// else ++//// __ ble(AT, (int)0); ++//// break; ++//// default: ++//// Unimplemented(); ++//// } ++//// %} ++//// ++//// ins_pc_relative(1); ++//// ins_pipe( pipe_alu_branch ); ++////%} ++ ++instruct branchConI_reg_imm16_sub(cmpOp cmp, mRegI src1, immI16_sub src2, label labl) %{ ++ match( If cmp (CmpI src1 src2) ); ++ effect(USE labl); ++ ins_cost(180); ++ format %{ "BR$cmp $src1, $src2, $labl #@branchConI_reg_imm16_sub" %} ++ ++ ins_encode %{ ++ Register op1 = $src1$$Register; ++ int val = $src2$$constant; ++ Label &L = *($labl$$label); ++ int flag = $cmp$$cmpcode; ++ ++ __ add_simm16(AT, op1, -1 * val); ++ switch(flag) ++ { ++ case 0x01: //equal ++ if (&L) ++ __ beq(AT, L); ++ else ++ __ beq(AT, (int)0); ++ break; ++ case 0x02: //not_equal ++ if (&L) ++ __ bne(AT, L); ++ else ++ __ bne(AT, (int)0); ++ break; ++ case 0x03: //greater ++ if(&L) ++ __ bgt(AT, L); ++ else ++ __ bgt(AT, (int)0); ++ break; ++ case 0x04: //greater_equal ++ if(&L) ++ __ bge(AT, L); ++ else ++ __ bge(AT, (int)0); ++ break; ++ case 0x05: //less ++ if(&L) ++ __ blt(AT, L); ++ else ++ __ blt(AT, (int)0); ++ break; ++ case 0x06: //less_equal ++ if(&L) ++ __ ble(AT, L); ++ else ++ __ ble(AT, (int)0); ++ break; ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pc_relative(1); ++ ins_pipe( pipe_alu_branch ); ++%} ++ ++instruct branchConL_regL_immL0_short(cmpOp cmp, mRegL src1, immL0 zero, label labl) %{ ++ match( If cmp (CmpL src1 zero) ); ++ effect(USE labl); ++ format %{ "BR$cmp $src1, zero, $labl #@branchConL_regL_immL0_short" %} ++ ins_cost(150); ++ ++ ins_encode %{ ++ Register opr1_reg = as_Register($src1$$reg); ++ Label &target = *($labl$$label); ++ int flag = $cmp$$cmpcode; ++ ++ switch(flag) { ++ case 0x01: //equal ++ if (&target) ++ __ beq(opr1_reg, target); ++ else ++ __ beq(opr1_reg, int(0)); ++ break; ++ ++ case 0x02: //not_equal ++ if(&target) ++ __ bne(opr1_reg, target); ++ else ++ __ bne(opr1_reg, (int)0); ++ break; ++ ++ case 0x03: //greater ++ if(&target) ++ __ bgt(opr1_reg, target); ++ else ++ __ bgt(opr1_reg, (int)0); ++ break; ++ ++ case 0x04: //greater_equal ++ if(&target) ++ __ bge(opr1_reg, target); ++ else ++ __ bge(opr1_reg, (int)0); ++ break; ++ ++ case 0x05: //less ++ if (&target) ++ __ blt(opr1_reg, target); ++ else ++ __ blt(opr1_reg, int(0)); ++ break; ++ ++ case 0x06: //less_equal ++ if (&target) ++ __ ble(opr1_reg, target); ++ else ++ __ ble(opr1_reg, int(0)); ++ break; ++ ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pc_relative(1); ++ ins_pipe( pipe_alu_branch ); ++%} ++ ++instruct branchConL_regL_immL_short(cmpOp cmp, mRegL src1, immL src2, label labl) %{ ++ match( If cmp (CmpL src1 src2) ); ++ effect(USE labl); ++ format %{ "BR$cmp $src1, $src2, $labl #@branchConL_regL_immL_short" %} ++ ins_cost(180); ++ ++ ins_encode %{ ++ Register opr1_reg = as_Register($src1$$reg); ++ Register opr2_reg = AT; ++ ++ Label &target = *($labl$$label); ++ int flag = $cmp$$cmpcode; ++ ++ __ set64(opr2_reg, $src2$$constant); ++ switch(flag) { ++ case 0x01: //equal ++ if (&target) ++ __ beq(opr1_reg, opr2_reg, target); ++ else ++ __ beq(opr1_reg, opr2_reg, (int)0); ++ break; ++ ++ case 0x02: //not_equal ++ if(&target) ++ __ bne(opr1_reg, opr2_reg, target); ++ else ++ __ bne(opr1_reg, opr2_reg, (int)0); ++ break; ++ ++ case 0x03: //greater ++ __ cmplt(AT, opr2_reg, opr1_reg); ++ if(&target) ++ __ bne(AT, target); ++ else ++ __ bne(AT, (int)0); ++ break; ++ ++ case 0x04: //greater_equal ++ __ cmplt(AT, opr1_reg, opr2_reg); ++ if(&target) ++ __ beq(AT, target); ++ else ++ __ beq(AT, (int)0); ++ break; ++ ++ case 0x05: //less ++ __ cmplt(AT, opr1_reg, opr2_reg); ++ if(&target) ++ __ bne(AT, target); ++ else ++ __ bne(AT, (int)0); ++ break; ++ ++ case 0x06: //less_equal ++ __ cmplt(AT, opr2_reg, opr1_reg); ++ if(&target) ++ __ beq(AT, target); ++ else ++ __ beq(AT, (int)0); ++ break; ++ ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pc_relative(1); ++ ins_pipe( pipe_alu_branch ); ++%} ++ ++ ++ ++instruct branchConF_reg_reg_short(cmpOp cmp, regF src1, regF src2, label labl) %{ ++ match( If cmp (CmpF src1 src2) ); ++ effect(USE labl); ++ format %{ "BR$cmp $src1, $src2, $labl #@branchConF_reg_reg_short" %} ++ ++ ins_encode %{ ++ FloatRegister reg_op1 = $src1$$FloatRegister; ++ FloatRegister reg_op2 = $src2$$FloatRegister; ++ Label &L = *($labl$$label); ++ int flag = $cmp$$cmpcode; ++ ++ if (!&L) ++ Unimplemented(); ++ ++ switch(flag) { ++ case 0x01: //equal ++ __ fcmpeq(FcmpRES, reg_op1, reg_op2); ++ __ fbne(FcmpRES, L); ++ break; ++ case 0x02: //not_equal ++ __ fcmpeq(FcmpRES, reg_op1, reg_op2); ++ __ fbeq(FcmpRES, L); ++ break; ++ case 0x03: //greater ++ __ fcmplt(FcmpRES, reg_op2, reg_op1); ++ __ fbne(FcmpRES, L); ++ break; ++ case 0x04: //greater_equal ++ __ fcmple(FcmpRES, reg_op2, reg_op1); ++ __ fbne(FcmpRES, L); ++ break; ++ case 0x05: //less ++ __ fcmple(FcmpRES, reg_op2, reg_op1); ++ __ fbeq(FcmpRES, L); ++ break; ++ case 0x06: //less_equal ++ __ fcmplt(FcmpRES, reg_op2, reg_op1); ++ __ fbeq(FcmpRES, L); ++ break; ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pc_relative(1); ++ ins_pipe(pipe_slow); ++%} ++ ++instruct branchConD_reg_reg_short(cmpOp cmp, regD src1, regD src2, label labl) %{ ++ match( If cmp (CmpD src1 src2) ); ++ effect(USE labl); ++ format %{ "BR$cmp $src1, $src2, $labl #@branchConD_reg_reg_short" %} ++ ++ ins_encode %{ ++ FloatRegister reg_op1 = $src1$$FloatRegister; ++ FloatRegister reg_op2 = $src2$$FloatRegister; ++ Label &L = *($labl$$label); ++ int flag = $cmp$$cmpcode; ++ ++ switch(flag) { ++ case 0x01: //equal ++ __ fcmpeq(FcmpRES, reg_op1, reg_op2); ++ if (&L) ++ __ fbne(FcmpRES, L); ++ else ++ __ fbne(FcmpRES, (int)0); ++ break; ++ case 0x02: //not_equal ++ // c_ueq_d cannot distinguish NaN from equal. Double.isNaN(Double) is implemented by 'f != f', so the use of c_ueq_d causes bugs. ++ __ fcmpeq(FcmpRES, reg_op1, reg_op2); ++ if (&L) ++ __ fbeq(FcmpRES, L); ++ else ++ __ fbeq(FcmpRES, (int)0); ++ break; ++ case 0x03: //greater ++ __ fcmplt(FcmpRES, reg_op2, reg_op1); ++ if(&L) ++ __ fbne(FcmpRES, L); ++ else ++ __ fbne(FcmpRES, (int)0); ++ break; ++ case 0x04: //greater_equal ++ __ fcmple(FcmpRES, reg_op2, reg_op1); ++ if(&L) ++ __ fbne(FcmpRES, L); ++ else ++ __ fbne(FcmpRES, (int)0); ++ break; ++ case 0x05: //less ++ __ fcmple(FcmpRES, reg_op2, reg_op1); ++ if(&L) ++ __ fbeq(FcmpRES, L); ++ else ++ __ fbeq(FcmpRES, (int)0); ++ break; ++ case 0x06: //less_equal ++ __ fcmplt(FcmpRES, reg_op2, reg_op1); ++ if(&L) ++ __ fbeq(FcmpRES, L); ++ else ++ __ fbeq(FcmpRES, (int)0); ++ break; ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pc_relative(1); ++ ins_pipe(pipe_slow); ++%} ++ ++// =================== End of branch instructions ========================== ++ ++// Call Runtime Instruction ++instruct CallRuntimeDirect(method meth) %{ ++ match(CallRuntime ); ++ effect(USE meth); ++ ++ ins_cost(300); ++ format %{ "CALL,runtime #@CallRuntimeDirect" %} ++ ins_encode( Java_To_Runtime( meth ) ); ++ ins_pipe( pipe_slow ); ++ ins_alignment(16); ++%} ++ ++//------------------------BSWAP Instructions------------------------------- ++instruct bytes_reverse_int(mRegI dst, mRegI src) %{ ++ match(Set dst (ReverseBytesI src)); ++ predicate(UseSW8A); ++ ins_cost(10); ++ format %{ "revbw $dst, $src" %} ++ ++ ins_encode %{ ++ Register dst = as_Register($dst$$reg); ++ Register src = as_Register($src$$reg); ++ if(UseSW8A) { ++ __ revbw(src, dst); ++ }else{ ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pipe(ialu_regI_regI); ++%} ++ ++instruct bytes_reverse_long(mRegL dst, mRegL src) %{ ++ match(Set dst (ReverseBytesL src)); ++ predicate(UseSW8A); ++ ins_cost(10); ++ format %{ "revbl $dst, $src" %} ++ ++ ins_encode %{ ++ Register dst = as_Register($dst$$reg); ++ Register src = as_Register($src$$reg); ++ if(UseSW8A) { ++ __ revbl(src, dst); ++ }else{ ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pipe(ialu_regI_regI); ++%} ++ ++instruct bytes_reverse_unsigned_short(mRegI dst, mRegI src) %{ ++ match(Set dst (ReverseBytesUS src)); ++ predicate(UseSW8A); ++ ins_cost(10); ++ format %{ "revbh $dst, $src" %} ++ ++ ins_encode %{ ++ Register dst = as_Register($dst$$reg); ++ Register src = as_Register($src$$reg); ++ if(UseSW8A) { ++ __ revbh(src, dst); ++ }else{ ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pipe(ialu_regI_regI); ++%} ++ ++instruct bytes_reverse_short(mRegI dst, mRegI src) %{ ++ match(Set dst (ReverseBytesS src)); ++ predicate(UseSW8A); ++ ins_cost(10); ++ format %{ "revbh $dst, $src\n\t" ++ "sexth $dst, $dst" %} ++ ++ ins_encode %{ ++ Register dst = as_Register($dst$$reg); ++ Register src = as_Register($src$$reg); ++ if(UseSW8A) { ++ __ revbh(src, dst); ++ __ sexth(dst, dst); ++ }else{ ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pipe(ialu_regI_regI); ++%} ++ ++//------------------------MemBar Instructions------------------------------- ++//Memory barrier flavors ++ ++instruct membar_acquire() %{ ++ match(MemBarAcquire); ++ ins_cost(0); ++ ++ size(4); ++ format %{ "MEMBAR-acquire @ membar_acquire" %} ++ ins_encode %{ ++ if (UseNecessaryMembar) { ++ __ memb(); ++ } ++ %} ++ ins_pipe(empty); ++%} ++ ++instruct load_fence() %{ ++ match(LoadFence); ++ ins_cost(400); ++ ++ format %{ "MEMBAR @ load_fence" %} ++ ins_encode %{ ++ __ memb(); ++ %} ++ ins_pipe(pipe_slow); ++%} ++ ++instruct membar_acquire_lock() %{ ++ match(MemBarAcquireLock); ++ ins_cost(0); ++ ++ size(0); ++ format %{ "MEMBAR-acquire (acquire as part of CAS in prior FastLock so empty encoding) @ membar_acquire_lock" %} ++ ins_encode(); ++ ins_pipe(empty); ++%} ++ ++instruct unnecessary_membar_release() %{ ++ predicate(unnecessary_release(n)); ++ match(MemBarRelease); ++ ins_cost(0); ++ ++ format %{ "membar_release (elided)" %} ++ ++ ins_encode %{ ++ __ block_comment("membar_release (elided)"); ++ %} ++ ins_pipe(pipe_slow); ++%} ++ ++instruct membar_release() %{ ++ match(MemBarRelease); ++ ins_cost(400); ++ ++ format %{ "MEMBAR-release @ membar_release" %} ++ ++ ins_encode %{ ++ // Attention: DO NOT DELETE THIS GUY! ++ __ memb(); ++ %} ++ ++ ins_pipe(pipe_slow); ++%} ++ ++instruct store_fence() %{ ++ match(StoreFence); ++ ins_cost(400); ++ ++ format %{ "MEMBAR @ store_fence" %} ++ ++ ins_encode %{ ++ __ memb(); ++ %} ++ ++ ins_pipe(pipe_slow); ++%} ++ ++instruct membar_release_lock() %{ ++ match(MemBarReleaseLock); ++ ins_cost(0); ++ ++ size(0); ++ format %{ "MEMBAR-release-lock (release in FastUnlock so empty) @ membar_release_lock" %} ++ ins_encode(); ++ ins_pipe(empty); ++%} ++ ++ ++instruct membar_volatile() %{ ++ match(MemBarVolatile); ++ ins_cost(400); ++ ++ format %{ "MEMBAR-volatile" %} ++ ins_encode %{ ++ if( !os::is_MP() ) return; // Not needed on single CPU ++ __ memb(); ++ ++ %} ++ ins_pipe(pipe_slow); ++%} ++ ++instruct unnecessary_membar_volatile() %{ ++ match(MemBarVolatile); ++ predicate(Matcher::post_store_load_barrier(n)); ++ ins_cost(0); ++ ++ size(0); ++ format %{ "MEMBAR-volatile (unnecessary so empty encoding) @ unnecessary_membar_volatile" %} ++ ins_encode( ); ++ ins_pipe(empty); ++%} ++ ++instruct membar_storestore() %{ ++ match(MemBarStoreStore); ++ ++ ins_cost(0); ++ size(4); ++ format %{ "MEMBAR-storestore @ membar_storestore" %} ++ ins_encode %{ ++ if (UseWmemb && UseNecessaryMembar) { ++ __ wmemb(); ++ } else if (UseNecessaryMembar) { ++ __ memb(); ++ } ++ %} ++ ins_pipe(empty); ++%} ++ ++//----------Move Instructions-------------------------------------------------- ++instruct castX2P(mRegP dst, mRegL src) %{ ++ match(Set dst (CastX2P src)); ++ format %{ "castX2P $dst, $src @ castX2P" %} ++ ins_encode %{ ++ Register src = $src$$Register; ++ Register dst = $dst$$Register; ++ ++ if(src != dst) ++ __ move(dst, src); ++ %} ++ ins_cost(10); ++ ins_pipe( ialu_regI_mov ); ++%} ++ ++instruct castP2X(mRegL dst, mRegP src ) %{ ++ match(Set dst (CastP2X src)); ++ ++ format %{ "mov $dst, $src\t #@castP2X" %} ++ ins_encode %{ ++ Register src = $src$$Register; ++ Register dst = $dst$$Register; ++ ++ if(src != dst) ++ __ move(dst, src); ++ %} ++ ins_pipe( ialu_regI_mov ); ++%} ++ ++instruct MoveF2I_reg_reg(mRegI dst, regF src) %{ ++ match(Set dst (MoveF2I src)); ++ effect(DEF dst, USE src); ++ ins_cost(85); ++ format %{ "MoveF2I $dst, $src @ MoveF2I_reg_reg" %} ++ ins_encode %{ ++ Register dst = as_Register($dst$$reg); ++ FloatRegister src = as_FloatRegister($src$$reg); ++ ++ __ fimovs(dst, src); ++ __ addw(dst, dst, 0); ++ %} ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct MoveI2F_reg_reg(regF dst, mRegI src) %{ ++ match(Set dst (MoveI2F src)); ++ effect(DEF dst, USE src); ++ ins_cost(85); ++ format %{ "MoveI2F $dst, $src @ MoveI2F_reg_reg" %} ++ ins_encode %{ ++ Register src = as_Register($src$$reg); ++ FloatRegister dst = as_FloatRegister($dst$$reg); ++ ++ __ ifmovs(dst, src); ++ %} ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct MoveD2L_reg_reg(mRegL dst, regD src) %{ ++ match(Set dst (MoveD2L src)); ++ effect(DEF dst, USE src); ++ ins_cost(85); ++ format %{ "MoveD2L $dst, $src @ MoveD2L_reg_reg" %} ++ ins_encode %{ ++ Register dst = as_Register($dst$$reg); ++ FloatRegister src = as_FloatRegister($src$$reg); ++ ++ __ fimovd(dst, src); ++ %} ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct MoveL2D_reg_reg(regD dst, mRegL src) %{ ++ match(Set dst (MoveL2D src)); ++ effect(DEF dst, USE src); ++ ins_cost(85); ++ format %{ "MoveL2D $dst, $src @ MoveL2D_reg_reg" %} ++ ins_encode %{ ++ FloatRegister dst = as_FloatRegister($dst$$reg); ++ Register src = as_Register($src$$reg); ++ ++ __ ifmovd(dst, src); ++ %} ++ ins_pipe( pipe_slow ); ++%} ++ ++//----------Conditional Move--------------------------------------------------- ++// Conditional move ++instruct cmovI_cmpI_reg_reg2(mRegI dst, mRegI src1, mRegI src2, mRegI tmp1, mRegI tmp2, cmpOp cop ) %{ ++ match(Set dst (CMoveI (Binary cop (CmpI tmp1 tmp2)) (Binary src2 src1))); ++ ins_cost(80); ++ format %{ ++ "CMP$cop $tmp1, $tmp2\t @cmovI_cmpI_reg_reg\n" ++ "\tCMOV $dst,$src1,$src2 \t @cmovI_cmpI_reg_reg" ++ %} ++ ++ ins_encode %{ ++ Register op1 = $tmp1$$Register; ++ Register op2 = $tmp2$$Register; ++ Register dst = $dst$$Register; ++ Register src1 = $src1$$Register; ++ Register src2 = $src2$$Register; ++ int flag = $cop$$cmpcode; ++ ++ switch(flag) { ++ case 0x01: //equal ++ __ subw(AT, op1, op2); ++ __ seleq(AT, src1, src2, dst); ++ break; ++ ++ case 0x02: //not_equal ++ __ subw(AT, op1, op2); ++ __ selne(AT, src1, src2, dst); ++ break; ++ ++ case 0x03: //great ++ __ cmplt(AT, op2, op1); ++ __ selne(AT, src1, src2, dst); ++ break; ++ ++ case 0x04: //great_equal ++ __ cmplt(AT, op1, op2); ++ __ seleq(AT, src1, src2, dst); ++ break; ++ ++ case 0x05: //less ++ __ cmplt(AT, op1, op2); ++ __ selne(AT, src1, src2, dst); ++ break; ++ ++ case 0x06: //less_equal ++ __ cmplt(AT, op2, op1); ++ __ seleq(AT, src1, src2, dst); ++ break; ++ ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct cmovI_cmpI_reg_imm(mRegI dst, immI_0_255 src1, mRegI src2, mRegI tmp1, mRegI tmp2, cmpOp cop ) %{ ++ match(Set dst (CMoveI (Binary cop (CmpI tmp1 tmp2)) (Binary src2 src1))); ++ ins_cost(80); ++ format %{ ++ "CMP$cop $tmp1, $tmp2\t @cmovI_cmpI_reg_reg\n" ++ "\tCMOV $dst,$src1,$src2 \t @cmovI_cmpI_reg_imm" ++ %} ++ ++ ins_encode %{ ++ Register op1 = $tmp1$$Register; ++ Register op2 = $tmp2$$Register; ++ Register dst = $dst$$Register; ++ Register src2 = $src2$$Register; ++ int src1 = $src1$$constant & ((1<<8)-1); ++ int flag = $cop$$cmpcode; ++ ++ switch(flag) ++ { ++ case 0x01: //equal ++ __ subl(AT, op1, op2); ++ __ seleq(AT,src1,src2,dst); ++ break; ++ ++ case 0x02: //not_equal ++ __ subl(AT, op1, op2); ++ __ selne(AT,src1,src2,dst); ++ break; ++ ++ case 0x03: //great ++ __ cmplt(AT, op2, op1); ++ __ selne(AT,src1,src2,dst); ++ break; ++ ++ case 0x04: //great_equal ++ __ cmplt(AT, op1, op2); ++ __ seleq(AT,src1,src2,dst); ++ break; ++ ++ case 0x05: //less ++ __ cmplt(AT, op1, op2); ++ __ selne(AT,src1,src2,dst); ++ break; ++ ++ case 0x06: //less_equal ++ __ cmplt(AT, op2, op1); ++ __ seleq(AT,src1,src2,dst); ++ break; ++ ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct cmovI_cmpP_reg_reg(mRegI dst, mRegI src, mRegP tmp1, mRegP tmp2, cmpOpU cop ) %{ ++ match(Set dst (CMoveI (Binary cop (CmpP tmp1 tmp2)) (Binary dst src))); ++ ins_cost(80); ++ format %{ ++ "CMPU$cop $tmp1,$tmp2\t @cmovI_cmpP_reg_reg\n\t" ++ "CMOV $dst,$src\t @cmovI_cmpP_reg_reg" ++ %} ++ ins_encode %{ ++ Register op1 = $tmp1$$Register; ++ Register op2 = $tmp2$$Register; ++ Register dst = $dst$$Register; ++ Register src = $src$$Register; ++ int flag = $cop$$cmpcode; ++ ++ switch(flag) { ++ case 0x01: //equal ++ __ subl(AT, op1, op2); ++ __ seleq(AT, src, dst, dst); ++ break; ++ ++ case 0x02: //not_equal ++ __ subl(AT, op1, op2); ++ __ selne(AT, src, dst, dst); ++ break; ++ ++ case 0x03: //above ++ __ cmpult(AT, op2, op1); ++ __ selne(AT, src, dst, dst); ++ break; ++ ++ case 0x04: //above_equal ++ __ cmpult(AT, op1, op2); ++ __ seleq(AT, src, dst, dst); ++ break; ++ ++ case 0x05: //below ++ __ cmpult(AT, op1, op2); ++ __ selne(AT, src, dst, dst); ++ break; ++ ++ case 0x06: //below_equal ++ __ cmpult(AT, op2, op1); ++ __ seleq(AT, src, dst, dst); ++ break; ++ ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct cmovI_cmpP_reg_imm(mRegI dst, immI_0_255 src, mRegP tmp1, mRegP tmp2, cmpOpU cop ) %{ ++ match(Set dst (CMoveI (Binary cop (CmpP tmp1 tmp2)) (Binary dst src))); ++ ins_cost(80); ++ format %{ ++ "CMPU$cop $tmp1,$tmp2\t @cmovI_cmpP_reg_reg\n\t" ++ "CMOV $dst,$src\t @cmovI_cmpP_reg_reg" ++ %} ++ ins_encode %{ ++ Register op1 = $tmp1$$Register; ++ Register op2 = $tmp2$$Register; ++ Register dst = $dst$$Register; ++ int src = $src$$constant & ((1<<8)-1); // Mask to 8 bits ++ int flag = $cop$$cmpcode; ++ ++ switch(flag) ++ { ++ case 0x01: //equal ++ __ subl(AT, op1, op2); ++ __ seleq(AT,src,dst,dst); ++ break; ++ ++ case 0x02: //not_equal ++ __ subl(AT, op1, op2); ++ __ selne(AT,src,dst,dst); ++ break; ++ ++ case 0x03: //above ++ __ cmpult(AT, op2, op1); ++ __ selne(AT,src,dst,dst); ++ break; ++ ++ case 0x04: //above_equal ++ __ cmpult(AT, op1, op2); ++ __ seleq(AT,src,dst,dst); ++ break; ++ ++ case 0x05: //below ++ __ cmpult(AT, op1, op2); ++ __ selne(AT,src,dst,dst); ++ break; ++ ++ case 0x06: //below_equal ++ __ cmpult(AT, op2, op1); ++ __ seleq(AT,src,dst,dst); ++ break; ++ ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pipe( pipe_slow ); ++ %} ++ ++instruct cmovI_cmpN_reg_reg(mRegI dst, mRegI src, mRegN tmp1, mRegN tmp2, cmpOpU cop ) %{ ++ match(Set dst (CMoveI (Binary cop (CmpN tmp1 tmp2)) (Binary dst src))); ++ ins_cost(80); ++ format %{ ++ "CMPU$cop $tmp1,$tmp2\t @cmovI_cmpN_reg_reg\n\t" ++ "CMOV $dst,$src\t @cmovI_cmpN_reg_reg" ++ %} ++ ins_encode %{ ++ Register op1 = $tmp1$$Register; ++ Register op2 = $tmp2$$Register; ++ Register dst = $dst$$Register; ++ Register src = $src$$Register; ++ int flag = $cop$$cmpcode; ++ ++ switch(flag) { ++ case 0x01: //equal ++ __ subw(AT, op1, op2); ++ __ seleq(AT, src, dst, dst); ++ break; ++ ++ case 0x02: //not_equal ++ __ subw(AT, op1, op2); ++ __ selne(AT, src, dst, dst); ++ break; ++ ++ case 0x03: //above ++ __ cmpult(AT, op2, op1); ++ __ selne(AT, src, dst, dst); ++ break; ++ ++ case 0x04: //above_equal ++ __ cmpult(AT, op1, op2); ++ __ seleq(AT, src, dst, dst); ++ break; ++ ++ case 0x05: //below ++ __ cmpult(AT, op1, op2); ++ __ selne(AT, src, dst, dst); ++ break; ++ ++ case 0x06: //below_equal ++ __ cmpult(AT, op2, op1); ++ __ seleq(AT, src, dst, dst); ++ break; ++ ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct cmovI_cmpN_reg_imm(mRegI dst, immI_0_255 src, mRegN tmp1, mRegN tmp2, cmpOpU cop ) %{ ++ match(Set dst (CMoveI (Binary cop (CmpN tmp1 tmp2)) (Binary dst src))); ++ ins_cost(80); ++ format %{ ++ "CMPU$cop $tmp1,$tmp2\t @cmovI_cmpN_reg_imm\n\t" ++ "CMOV $dst,$src\t @cmovI_cmpN_reg_imm" ++ %} ++ ins_encode %{ ++ Register op1 = $tmp1$$Register; ++ Register op2 = $tmp2$$Register; ++ Register dst = $dst$$Register; ++ int src = $src$$constant & ((1<<8)-1); // Mask to 8 bits ++ int flag = $cop$$cmpcode; ++ ++ switch(flag) ++ { ++ case 0x01: //equal ++ __ subl(AT, op1, op2); ++ __ seleq(AT,src,dst,dst); ++ break; ++ ++ case 0x02: //not_equal ++ __ subl(AT, op1, op2); ++ __ selne(AT,src,dst,dst); ++ break; ++ ++ case 0x03: //above ++ __ cmpult(AT, op2, op1); ++ __ selne(AT,src,dst,dst); ++ break; ++ ++ case 0x04: //above_equal ++ __ cmpult(AT, op1, op2); ++ __ seleq(AT,src,dst,dst); ++ break; ++ ++ case 0x05: //below ++ __ cmpult(AT, op1, op2); ++ __ selne(AT,src,dst,dst); ++ break; ++ ++ case 0x06: //below_equal ++ __ cmpult(AT, op2, op1); ++ __ seleq(AT,src,dst,dst); ++ break; ++ ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct cmovP_cmpU_reg_reg(mRegP dst, mRegP src, mRegI tmp1, mRegI tmp2, cmpOpU cop ) %{ ++ match(Set dst (CMoveP (Binary cop (CmpU tmp1 tmp2)) (Binary dst src))); ++ ins_cost(80); ++ format %{ ++ "CMPU$cop $tmp1,$tmp2\t @cmovP_cmpU_reg_reg\n\t" ++ "CMOV $dst,$src\t @cmovP_cmpU_reg_reg" ++ %} ++ ins_encode %{ ++ Register op1 = $tmp1$$Register; ++ Register op2 = $tmp2$$Register; ++ Register dst = $dst$$Register; ++ Register src = $src$$Register; ++ int flag = $cop$$cmpcode; ++ ++ switch(flag) { ++ case 0x01: //equal ++ __ subw(AT, op1, op2); ++ __ seleq(AT, src, dst, dst); ++ break; ++ ++ case 0x02: //not_equal ++ __ subw(AT, op1, op2); ++ __ selne(AT, src, dst, dst); ++ break; ++ ++ case 0x03: //above ++ __ cmpult(AT, op2, op1); ++ __ selne(AT, src, dst, dst); ++ break; ++ ++ case 0x04: //above_equal ++ __ cmpult(AT, op1, op2); ++ __ seleq(AT, src, dst, dst); ++ break; ++ ++ case 0x05: //below ++ __ cmpult(AT, op1, op2); ++ __ selne(AT, src, dst, dst); ++ break; ++ ++ case 0x06: //below_equal ++ __ cmpult(AT, op2, op1); ++ __ seleq(AT, src, dst, dst); ++ break; ++ ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct cmovP_cmpF_reg_reg(mRegP dst, mRegP src, regF tmp1, regF tmp2, cmpOp cop ) %{ ++ match(Set dst (CMoveP (Binary cop (CmpF tmp1 tmp2)) (Binary dst src))); ++ ins_cost(80); ++ format %{ ++ "CMP$cop $tmp1, $tmp2\t @cmovP_cmpF_reg_reg\n" ++ "\tCMOV $dst,$src \t @cmovP_cmpF_reg_reg" ++ %} ++ ++ ins_encode %{ ++ FloatRegister reg_op1 = $tmp1$$FloatRegister; ++ FloatRegister reg_op2 = $tmp2$$FloatRegister; ++ Register dst = $dst$$Register; ++ Register src = $src$$Register; ++ int flag = $cop$$cmpcode; ++ ++ switch(flag) { ++ case 0x01: //equal ++ __ fcmpeq(FcmpRES, reg_op1, reg_op2); ++ __ fimovd(GP, FcmpRES); ++ __ selne(GP, src, dst, dst); ++ break; ++ case 0x02: //not_equal ++ __ fcmpeq(FcmpRES, reg_op1, reg_op2); ++ __ fimovd(GP, FcmpRES); ++ __ seleq(GP, src, dst, dst); ++ break; ++ case 0x03: //greater ++ __ fcmple(FcmpRES, reg_op1, reg_op2); ++ __ fimovd(GP, FcmpRES); ++ __ seleq(GP, src, dst, dst); ++ break; ++ case 0x04: //greater_equal ++ __ fcmplt(FcmpRES, reg_op1, reg_op2); ++ __ fimovd(GP, FcmpRES); ++ __ seleq(GP, src, dst, dst); ++ break; ++ case 0x05: //less ++ __ fcmple(FcmpRES, reg_op2, reg_op1); ++ __ fimovd(GP, FcmpRES); ++ __ seleq(GP, src, dst, dst); ++ break; ++ case 0x06: //less_equal ++ __ fcmplt(FcmpRES, reg_op2, reg_op1); ++ __ fimovd(GP, FcmpRES); ++ __ seleq(GP, src, dst, dst); ++ break; ++ default: ++ Unimplemented(); ++ } ++ %} ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct cmovP_cmpN_reg_reg(mRegP dst, mRegP src, mRegN tmp1, mRegN tmp2, cmpOpU cop ) %{ ++ match(Set dst (CMoveP (Binary cop (CmpN tmp1 tmp2)) (Binary dst src))); ++ ins_cost(80); ++ format %{ ++ "CMPU$cop $tmp1,$tmp2\t @cmovP_cmpN_reg_reg\n\t" ++ "CMOV $dst,$src\t @cmovP_cmpN_reg_reg" ++ %} ++ ins_encode %{ ++ Register op1 = $tmp1$$Register; ++ Register op2 = $tmp2$$Register; ++ Register dst = $dst$$Register; ++ Register src = $src$$Register; ++ int flag = $cop$$cmpcode; ++ ++ switch(flag) { ++ case 0x01: //equal ++ __ subw(AT, op1, op2); ++ __ seleq(AT, src, dst, dst); ++ break; ++ ++ case 0x02: //not_equal ++ __ subw(AT, op1, op2); ++ __ selne(AT, src, dst, dst); ++ break; ++ ++ case 0x03: //above ++ __ cmpult(AT, op2, op1); ++ __ selne(AT, src, dst, dst); ++ break; ++ ++ case 0x04: //above_equal ++ __ cmpult(AT, op1, op2); ++ __ seleq(AT, src, dst, dst); ++ break; ++ ++ case 0x05: //below ++ __ cmpult(AT, op1, op2); ++ __ selne(AT, src, dst, dst); ++ break; ++ ++ case 0x06: //below_equal ++ __ cmpult(AT, op2, op1); ++ __ seleq(AT, src, dst, dst); ++ break; ++ ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct cmovN_cmpP_reg_reg(mRegN dst, mRegN src, mRegP tmp1, mRegP tmp2, cmpOpU cop ) %{ ++ match(Set dst (CMoveN (Binary cop (CmpP tmp1 tmp2)) (Binary dst src))); ++ ins_cost(80); ++ format %{ ++ "CMPU$cop $tmp1,$tmp2\t @cmovN_cmpP_reg_reg\n\t" ++ "CMOV $dst,$src\t @cmovN_cmpP_reg_reg" ++ %} ++ ins_encode %{ ++ Register op1 = $tmp1$$Register; ++ Register op2 = $tmp2$$Register; ++ Register dst = $dst$$Register; ++ Register src = $src$$Register; ++ int flag = $cop$$cmpcode; ++ ++ switch(flag) { ++ case 0x01: //equal ++ __ subl(AT, op1, op2); ++ __ seleq(AT, src, dst, dst); ++ break; ++ ++ case 0x02: //not_equal ++ __ subl(AT, op1, op2); ++ __ selne(AT, src, dst, dst); ++ break; ++ ++ case 0x03: //above ++ __ cmpult(AT, op2, op1); ++ __ selne(AT, src, dst, dst); ++ break; ++ ++ case 0x04: //above_equal ++ __ cmpult(AT, op1, op2); ++ __ seleq(AT, src, dst, dst); ++ break; ++ ++ case 0x05: //below ++ __ cmpult(AT, op1, op2); ++ __ selne(AT, src, dst, dst); ++ break; ++ ++ case 0x06: //below_equal ++ __ cmpult(AT, op2, op1); ++ __ seleq(AT, src, dst, dst); ++ break; ++ ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct cmovN_cmpP_reg_imm(mRegN dst, immI_0_255 src, mRegP tmp1, mRegP tmp2, cmpOpU cop ) %{ ++ match(Set dst (CMoveN (Binary cop (CmpP tmp1 tmp2)) (Binary dst src))); ++ ins_cost(80); ++ format %{ ++ "CMPU$cop $tmp1,$tmp2\t @cmovN_cmpP_reg_imm\n\t" ++ "CMOV $dst,$src\t @cmovN_cmpP_reg_imm" ++ %} ++ ins_encode %{ ++ Register op1 = $tmp1$$Register; ++ Register op2 = $tmp2$$Register; ++ Register dst = $dst$$Register; ++ int src = $src$$constant & ((1<<8)-1); // Mask to 8 bits ++ int flag = $cop$$cmpcode; ++ ++ switch(flag) ++ { ++ case 0x01: //equal ++ __ subl(AT, op1, op2); ++ __ seleq(AT,src,dst,dst); ++ break; ++ ++ case 0x02: //not_equal ++ __ subl(AT, op1, op2); ++ __ selne(AT,src,dst,dst); ++ break; ++ ++ case 0x03: //above ++ __ cmpult(AT, op2, op1); ++ __ selne(AT,src,dst,dst); ++ break; ++ ++ case 0x04: //above_equal ++ __ cmpult(AT, op1, op2); ++ __ seleq(AT,src,dst,dst); ++ break; ++ ++ case 0x05: //below ++ __ cmpult(AT, op1, op2); ++ __ selne(AT,src,dst,dst); ++ break; ++ ++ case 0x06: //below_equal ++ __ cmpult(AT, op2, op1); ++ __ seleq(AT,src,dst,dst); ++ break; ++ ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct cmovP_cmpD_reg_reg(mRegP dst, mRegP src, regD tmp1, regD tmp2, cmpOp cop ) %{ ++ match(Set dst (CMoveP (Binary cop (CmpD tmp1 tmp2)) (Binary dst src))); ++ ins_cost(80); ++ format %{ ++ "CMP$cop $tmp1, $tmp2\t @cmovP_cmpD_reg_reg\n" ++ "\tCMOV $dst,$src \t @cmovP_cmpD_reg_reg" ++ %} ++ ins_encode %{ ++ FloatRegister reg_op1 = as_FloatRegister($tmp1$$reg); ++ FloatRegister reg_op2 = as_FloatRegister($tmp2$$reg); ++ Register dst = as_Register($dst$$reg); ++ Register src = as_Register($src$$reg); ++ ++ int flag = $cop$$cmpcode; ++ ++ switch(flag) { ++ case 0x01: //equal ++ __ fcmpeq(FcmpRES, reg_op1, reg_op2); ++ __ fimovd(GP, FcmpRES); ++ __ selne(GP, src, dst, dst); ++ break; ++ case 0x02: //not_equal ++ __ fcmpeq(FcmpRES, reg_op1, reg_op2); ++ __ fimovd(GP, FcmpRES); ++ __ seleq(GP, src, dst, dst); ++ break; ++ case 0x03: //greater ++ __ fcmple(FcmpRES, reg_op1, reg_op2); ++ __ fimovd(GP, FcmpRES); ++ __ seleq(GP, src, dst, dst); ++ break; ++ case 0x04: //greater_equal ++ __ fcmplt(FcmpRES, reg_op1, reg_op2); ++ __ fimovd(GP, FcmpRES); ++ __ seleq(GP, src, dst, dst); ++ break; ++ case 0x05: //less ++ __ fcmple(FcmpRES, reg_op2, reg_op1); ++ __ fimovd(GP, FcmpRES); ++ __ seleq(GP, src, dst, dst); ++ break; ++ case 0x06: //less_equal ++ __ fcmplt(FcmpRES, reg_op2, reg_op1); ++ __ fimovd(GP, FcmpRES); ++ __ seleq(GP, src, dst, dst); ++ break; ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pipe( pipe_slow ); ++%} ++ ++ ++instruct cmovN_cmpN_reg_reg(mRegN dst, mRegN src, mRegN tmp1, mRegN tmp2, cmpOpU cop ) %{ ++ match(Set dst (CMoveN (Binary cop (CmpN tmp1 tmp2)) (Binary dst src))); ++ ins_cost(80); ++ format %{ ++ "CMPU$cop $tmp1,$tmp2\t @cmovN_cmpN_reg_reg\n\t" ++ "CMOV $dst,$src\t @cmovN_cmpN_reg_reg" ++ %} ++ ins_encode %{ ++ Register op1 = $tmp1$$Register; ++ Register op2 = $tmp2$$Register; ++ Register dst = $dst$$Register; ++ Register src = $src$$Register; ++ int flag = $cop$$cmpcode; ++ ++ switch(flag) { ++ case 0x01: //equal ++ __ subw(AT, op1, op2); ++ __ seleq(AT, src, dst, dst); ++ break; ++ ++ case 0x02: //not_equal ++ __ subw(AT, op1, op2); ++ __ selne(AT, src, dst, dst); ++ break; ++ ++ case 0x03: //above ++ __ cmpult(AT, op2, op1); ++ __ selne(AT, src, dst, dst); ++ break; ++ ++ case 0x04: //above_equal ++ __ cmpult(AT, op1, op2); ++ __ seleq(AT, src, dst, dst); ++ break; ++ ++ case 0x05: //below ++ __ cmpult(AT, op1, op2); ++ __ selne(AT, src, dst, dst); ++ break; ++ ++ case 0x06: //below_equal ++ __ cmpult(AT, op2, op1); ++ __ seleq(AT, src, dst, dst); ++ break; ++ ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct cmovN_cmpN_reg_imm(mRegN dst, immI_0_255 src, mRegN tmp1, mRegN tmp2, cmpOpU cop ) %{ ++ match(Set dst (CMoveN (Binary cop (CmpN tmp1 tmp2)) (Binary dst src))); ++ ins_cost(80); ++ format %{ ++ "CMPU$cop $tmp1,$tmp2\t @cmovN_cmpN_reg_imm\n\t" ++ "CMOV $dst,$src\t @cmovN_cmpN_reg_imm" ++ %} ++ ins_encode %{ ++ Register op1 = $tmp1$$Register; ++ Register op2 = $tmp2$$Register; ++ Register dst = $dst$$Register; ++ int src = $src$$constant & ((1<<8)-1); // Mask to 8 bits ++ int flag = $cop$$cmpcode; ++ ++ switch(flag) ++ { ++ case 0x01: //equal ++ __ subl(AT, op1, op2); ++ __ seleq(AT,src,dst,dst); ++ break; ++ ++ case 0x02: //not_equal ++ __ subl(AT, op1, op2); ++ __ selne(AT,src,dst,dst); ++ break; ++ ++ case 0x03: //above ++ __ cmpult(AT, op2, op1); ++ __ selne(AT,src,dst,dst); ++ break; ++ ++ case 0x04: //above_equal ++ __ cmpult(AT, op1, op2); ++ __ seleq(AT,src,dst,dst); ++ break; ++ ++ case 0x05: //below ++ __ cmpult(AT, op1, op2); ++ __ selne(AT,src,dst,dst); ++ break; ++ ++ case 0x06: //below_equal ++ __ cmpult(AT, op2, op1); ++ __ seleq(AT,src,dst,dst); ++ break; ++ ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct cmovI_cmpU_reg_reg(mRegI dst, mRegI src, mRegI tmp1, mRegI tmp2, cmpOpU cop ) %{ ++ match(Set dst (CMoveI (Binary cop (CmpU tmp1 tmp2)) (Binary dst src))); ++ ins_cost(80); ++ format %{ ++ "CMPU$cop $tmp1,$tmp2\t @cmovI_cmpU_reg_reg\n\t" ++ "CMOV $dst,$src\t @cmovI_cmpU_reg_reg" ++ %} ++ ins_encode %{ ++ Register op1 = $tmp1$$Register; ++ Register op2 = $tmp2$$Register; ++ Register dst = $dst$$Register; ++ Register src = $src$$Register; ++ int flag = $cop$$cmpcode; ++ ++ switch(flag) { ++ case 0x01: //equal ++ __ subl(AT, op1, op2); ++ __ seleq(AT, src, dst, dst); ++ break; ++ ++ case 0x02: //not_equal ++ __ subl(AT, op1, op2); ++ __ selne(AT, src, dst, dst); ++ break; ++ ++ case 0x03: //above ++ __ cmpult(AT, op2, op1); ++ __ selne(AT, src, dst, dst); ++ break; ++ ++ case 0x04: //above_equal ++ __ cmpult(AT, op1, op2); ++ __ seleq(AT, src, dst, dst); ++ break; ++ ++ case 0x05: //below ++ __ cmpult(AT, op1, op2); ++ __ selne(AT, src, dst, dst); ++ break; ++ ++ case 0x06: //below_equal ++ __ cmpult(AT, op2, op1); ++ __ seleq(AT, src, dst, dst); ++ break; ++ ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct cmovI_cmpU_reg_imm(mRegI dst, immI_0_255 src, mRegI tmp1, mRegI tmp2, cmpOpU cop ) %{ ++ match(Set dst (CMoveI (Binary cop (CmpU tmp1 tmp2)) (Binary dst src))); ++ ins_cost(80); ++ format %{ ++ "CMPU$cop $tmp1,$tmp2\t @cmovI_cmpU_reg_imm\n\t" ++ "CMOV $dst,$src\t @cmovI_cmpU_reg_imm" ++ %} ++ ins_encode %{ ++ Register op1 = $tmp1$$Register; ++ Register op2 = $tmp2$$Register; ++ Register dst = $dst$$Register; ++ int src = $src$$constant & ((1<<8)-1); // Mask to 8 bits ++ int flag = $cop$$cmpcode; ++ ++ switch(flag) ++ { ++ case 0x01: //equal ++ __ subl(AT, op1, op2); ++ __ seleq(AT,src,dst,dst); ++ break; ++ ++ case 0x02: //not_equal ++ __ subl(AT, op1, op2); ++ __ selne(AT,src,dst,dst); ++ break; ++ ++ case 0x03: //above ++ __ cmpult(AT, op2, op1); ++ __ selne(AT,src,dst,dst); ++ break; ++ ++ case 0x04: //above_equal ++ __ cmpult(AT, op1, op2); ++ __ seleq(AT,src,dst,dst); ++ break; ++ ++ case 0x05: //below ++ __ cmpult(AT, op1, op2); ++ __ selne(AT,src,dst,dst); ++ break; ++ ++ case 0x06: //below_equal ++ __ cmpult(AT, op2, op1); ++ __ seleq(AT,src,dst,dst); ++ break; ++ ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct cmovI_cmpL_reg_reg(mRegI dst, mRegI src, mRegL tmp1, mRegL tmp2, cmpOp cop ) %{ ++ match(Set dst (CMoveI (Binary cop (CmpL tmp1 tmp2)) (Binary dst src))); ++ ins_cost(80); ++ format %{ ++ "CMP$cop $tmp1, $tmp2\t @cmovI_cmpL_reg_reg\n" ++ "\tCMOV $dst,$src \t @cmovI_cmpL_reg_reg" ++ %} ++ ins_encode %{ ++ Register opr1 = as_Register($tmp1$$reg); ++ Register opr2 = as_Register($tmp2$$reg); ++ Register dst = $dst$$Register; ++ Register src = $src$$Register; ++ int flag = $cop$$cmpcode; ++ ++ switch(flag) { ++ case 0x01: //equal ++ __ subl(AT, opr1, opr2); ++ __ seleq(AT, src, dst, dst); ++ break; ++ ++ case 0x02: //not_equal ++ __ subl(AT, opr1, opr2); ++ __ selne(AT, src, dst, dst); ++ break; ++ ++ case 0x03: //greater ++ __ cmplt(AT, opr2, opr1); ++ __ selne(AT, src, dst, dst); ++ break; ++ ++ case 0x04: //greater_equal ++ __ cmplt(AT, opr1, opr2); ++ __ seleq(AT, src, dst, dst); ++ break; ++ ++ case 0x05: //less ++ __ cmplt(AT, opr1, opr2); ++ __ selne(AT, src, dst, dst); ++ break; ++ ++ case 0x06: //less_equal ++ __ cmplt(AT, opr2, opr1); ++ __ seleq(AT, src, dst, dst); ++ break; ++ ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct cmovI_cmpL_reg_imm(mRegI dst, immI_0_255 src1, mRegI src2, mRegL tmp1, mRegL tmp2, cmpOp cop ) %{ ++ match(Set dst (CMoveI (Binary cop (CmpL tmp1 tmp2)) (Binary src2 src1))); ++ ins_cost(80); ++ format %{ ++ "CMP$cop $tmp1, $tmp2\t @cmovI_cmpL_reg_imm\n" ++ "\tCMOV $src2,$src1 \t @cmovI_cmpL_reg_imm" ++ %} ++ ins_encode %{ ++ Register opr1 = as_Register($tmp1$$reg); ++ Register opr2 = as_Register($tmp2$$reg); ++ Register dst = $dst$$Register; ++ int src1 = $src1$$constant & ((1<<8)-1); // Mask to 8 bits ++ Register src2 = $src2$$Register; ++ int flag = $cop$$cmpcode; ++ ++ switch(flag) ++ { ++ case 0x01: //equal ++ __ subl(AT, opr1, opr2); ++ __ seleq(AT, src1, src2, dst); ++ break; ++ ++ case 0x02: //not_equal ++ __ subl(AT, opr1, opr2); ++ __ selne(AT, src1, src2, dst); ++ break; ++ ++ case 0x03: //greater ++ __ cmplt(AT, opr2, opr1); ++ __ selne(AT, src1, src2, dst); ++ break; ++ ++ case 0x04: //greater_equal ++ __ cmplt(AT, opr1, opr2); ++ __ seleq(AT, src1, src2, dst); ++ break; ++ ++ case 0x05: //less ++ __ cmplt(AT, opr1, opr2); ++ __ selne(AT, src1, src2, dst); ++ break; ++ ++ case 0x06: //less_equal ++ __ cmplt(AT, opr2, opr1); ++ __ seleq(AT, src1, src2, dst); ++ break; ++ ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct cmovP_cmpL_reg_reg(mRegP dst, mRegP src, mRegL tmp1, mRegL tmp2, cmpOp cop ) %{ ++ match(Set dst (CMoveP (Binary cop (CmpL tmp1 tmp2)) (Binary dst src))); ++ ins_cost(80); ++ format %{ ++ "CMP$cop $tmp1, $tmp2\t @cmovP_cmpL_reg_reg\n" ++ "\tCMOV $dst,$src \t @cmovP_cmpL_reg_reg" ++ %} ++ ins_encode %{ ++ Register opr1 = as_Register($tmp1$$reg); ++ Register opr2 = as_Register($tmp2$$reg); ++ Register dst = $dst$$Register; ++ Register src = $src$$Register; ++ int flag = $cop$$cmpcode; ++ ++ switch(flag) { ++ case 0x01: //equal ++ __ subl(AT, opr1, opr2); ++ __ seleq(AT, src, dst, dst); ++ break; ++ ++ case 0x02: //not_equal ++ __ subl(AT, opr1, opr2); ++ __ selne(AT, src, dst, dst); ++ break; ++ ++ case 0x03: //greater ++ __ cmplt(AT, opr2, opr1); ++ __ selne(AT, src, dst, dst); ++ break; ++ ++ case 0x04: //greater_equal ++ __ cmplt(AT, opr1, opr2); ++ __ seleq(AT, src, dst, dst); ++ break; ++ ++ case 0x05: //less ++ __ cmplt(AT, opr1, opr2); ++ __ selne(AT, src, dst, dst); ++ break; ++ ++ case 0x06: //less_equal ++ __ cmplt(AT, opr2, opr1); ++ __ seleq(AT, src, dst, dst); ++ break; ++ ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct cmovI_cmpD_reg_reg(mRegI dst, mRegI src1, mRegI src2, regD tmp1, regD tmp2, cmpOp cop ) %{ ++ match(Set dst (CMoveI (Binary cop (CmpD tmp1 tmp2)) (Binary src2 src1))); ++ ins_cost(80); ++ format %{ ++ "CMP$cop $tmp1, $tmp2\t @cmovI_cmpD_reg_reg\n" ++ "\tCMOV $dst,$src1,$src2 \t @cmovI_cmpD_reg_reg" ++ %} ++ ins_encode %{ ++ FloatRegister reg_op1 = as_FloatRegister($tmp1$$reg); ++ FloatRegister reg_op2 = as_FloatRegister($tmp2$$reg); ++ Register dst = as_Register($dst$$reg); ++ Register src1 = as_Register($src1$$reg); ++ Register src2 = as_Register($src2$$reg); ++ ++ int flag = $cop$$cmpcode; ++ ++ switch(flag) { ++ case 0x01: //equal ++ __ fcmpeq(FcmpRES, reg_op1, reg_op2); ++ __ fimovd(GP, FcmpRES); ++ __ selne(GP, src1, src2, dst); ++ break; ++ case 0x02: //not_equal ++ // See instruct branchConD_reg_reg. The change in branchConD_reg_reg fixed a bug. It seems similar here, so I made thesame change. ++ __ fcmpeq(FcmpRES, reg_op1, reg_op2); ++ __ fimovd(GP, FcmpRES); ++ __ seleq(GP, src1, src2, dst); ++ break; ++ case 0x03: //greater ++ __ fcmple(FcmpRES, reg_op1, reg_op2); ++ __ fimovd(GP, FcmpRES); ++ __ seleq(GP, src1, src2, dst); ++ break; ++ case 0x04: //greater_equal ++ __ fcmplt(FcmpRES, reg_op1, reg_op2); ++ __ fimovd(GP, FcmpRES); ++ __ seleq(GP, src1, src2, dst); ++ break; ++ case 0x05: //less ++ __ fcmple(FcmpRES, reg_op2, reg_op1); ++ __ fimovd(GP, FcmpRES); ++ __ seleq(GP, src1, src2, dst); ++ break; ++ case 0x06: //less_equal ++ __ fcmplt(FcmpRES, reg_op2, reg_op1); ++ __ fimovd(GP, FcmpRES); ++ __ seleq(GP, src1, src2, dst); ++ break; ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct cmovI_cmpD_reg_imm(mRegI dst, immI_0_255 src1, mRegI src2, regD tmp1, regD tmp2, cmpOp cop ) %{ ++ match(Set dst (CMoveI (Binary cop (CmpD tmp1 tmp2)) (Binary src2 src1))); ++ ins_cost(80); ++ format %{ ++ "CMP$cop $tmp1, $tmp2\t @cmovI_cmpD_reg_imm\n" ++ "\tCMOV $dst,$src1,$src2 \t @cmovI_cmpD_reg_imm" ++ %} ++ ins_encode %{ ++ FloatRegister reg_op1 = as_FloatRegister($tmp1$$reg); ++ FloatRegister reg_op2 = as_FloatRegister($tmp2$$reg); ++ Register dst = as_Register($dst$$reg); ++ Register src2 = as_Register($src2$$reg); ++ int src1 = $src1$$constant & ((1<<8)-1); // Mask to 8 bits ++ ++ int flag = $cop$$cmpcode; ++ ++ switch(flag) ++ { ++ case 0x01: //equal ++ __ fcmpeq(FcmpRES, reg_op1, reg_op2); ++ __ fimovd(GP, FcmpRES); ++ __ selne(GP, src1, src2, dst); ++ break; ++ case 0x02: //not_equal ++ __ fcmpeq(FcmpRES, reg_op1, reg_op2); ++ __ fimovd(GP, FcmpRES); ++ __ seleq(GP, src1, src2, dst); ++ break; ++ case 0x03: //greater ++ __ fcmple(FcmpRES, reg_op1, reg_op2); ++ __ fimovd(GP, FcmpRES); ++ __ seleq(GP, src1, src2, dst); ++ break; ++ case 0x04: //greater_equal ++ __ fcmplt(FcmpRES, reg_op1, reg_op2); ++ __ fimovd(GP, FcmpRES); ++ __ seleq(GP, src1, src2, dst); ++ break; ++ case 0x05: //less ++ __ fcmplt(FcmpRES, reg_op1, reg_op2); ++ __ fimovd(GP, FcmpRES); ++ __ selne(GP, src1, src2, dst); ++ break; ++ case 0x06: //less_equal ++ __ fcmple(FcmpRES, reg_op1, reg_op2); ++ __ fimovd(GP, FcmpRES); ++ __ selne(GP, src1, src2, dst); ++ break; ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct cmovP_cmpP_reg_reg(mRegP dst, mRegP src, mRegP tmp1, mRegP tmp2, cmpOpU cop ) %{ ++ match(Set dst (CMoveP (Binary cop (CmpP tmp1 tmp2)) (Binary dst src))); ++ ins_cost(80); ++ format %{ ++ "CMPU$cop $tmp1,$tmp2\t @cmovP_cmpP_reg_reg\n\t" ++ "CMOV $dst,$src\t @cmovP_cmpP_reg_reg" ++ %} ++ ins_encode %{ ++ Register op1 = $tmp1$$Register; ++ Register op2 = $tmp2$$Register; ++ Register dst = $dst$$Register; ++ Register src = $src$$Register; ++ int flag = $cop$$cmpcode; ++ ++ switch(flag) { ++ case 0x01: //equal ++ __ subl(AT, op1, op2); ++ __ seleq(AT, src, dst, dst); ++ break; ++ ++ case 0x02: //not_equal ++ __ subl(AT, op1, op2); ++ __ selne(AT, src, dst, dst); ++ break; ++ ++ case 0x03: //above ++ __ cmpult(AT, op2, op1); ++ __ selne(AT, src, dst, dst); ++ break; ++ ++ case 0x04: //above_equal ++ __ cmpult(AT, op1, op2); ++ __ seleq(AT, src, dst, dst); ++ break; ++ ++ case 0x05: //below ++ __ cmpult(AT, op1, op2); ++ __ selne(AT, src, dst, dst); ++ break; ++ ++ case 0x06: //below_equal ++ __ cmpult(AT, op2, op1); ++ __ seleq(AT, src, dst, dst); ++ break; ++ ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct cmovP_cmpI_reg_reg(mRegP dst, mRegP src, mRegI tmp1, mRegI tmp2, cmpOp cop ) %{ ++ match(Set dst (CMoveP (Binary cop (CmpI tmp1 tmp2)) (Binary dst src))); ++ ins_cost(80); ++ format %{ ++ "CMP$cop $tmp1,$tmp2\t @cmovP_cmpI_reg_reg\n\t" ++ "CMOV $dst,$src\t @cmovP_cmpI_reg_reg" ++ %} ++ ins_encode %{ ++ Register op1 = $tmp1$$Register; ++ Register op2 = $tmp2$$Register; ++ Register dst = $dst$$Register; ++ Register src = $src$$Register; ++ int flag = $cop$$cmpcode; ++ ++ switch(flag) { ++ case 0x01: //equal ++ __ subw(AT, op1, op2); ++ __ seleq(AT, src, dst, dst); ++ break; ++ ++ case 0x02: //not_equal ++ __ subw(AT, op1, op2); ++ __ selne(AT, src, dst, dst); ++ break; ++ ++ case 0x03: //above ++ __ cmplt(AT, op2, op1); ++ __ selne(AT, src, dst, dst); ++ break; ++ ++ case 0x04: //above_equal ++ __ cmplt(AT, op1, op2); ++ __ seleq(AT, src, dst, dst); ++ break; ++ ++ case 0x05: //below ++ __ cmplt(AT, op1, op2); ++ __ selne(AT, src, dst, dst); ++ break; ++ ++ case 0x06: //below_equal ++ __ cmplt(AT, op2, op1); ++ __ seleq(AT, src, dst, dst); ++ break; ++ ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct cmovL_cmpP_reg_reg(mRegL dst, mRegL src, mRegP tmp1, mRegP tmp2, cmpOpU cop ) %{ ++ match(Set dst (CMoveL (Binary cop (CmpP tmp1 tmp2)) (Binary dst src))); ++ ins_cost(80); ++ format %{ ++ "CMPU$cop $tmp1,$tmp2\t @cmovL_cmpP_reg_reg\n\t" ++ "CMOV $dst,$src\t @cmovL_cmpP_reg_reg" ++ %} ++ ins_encode %{ ++ Register op1 = $tmp1$$Register; ++ Register op2 = $tmp2$$Register; ++ Register dst = $dst$$Register; ++ Register src = $src$$Register; ++ int flag = $cop$$cmpcode; ++ ++ switch(flag) { ++ case 0x01: //equal ++ __ subl(AT, op1, op2); ++ __ seleq(AT, src, dst, dst); ++ break; ++ ++ case 0x02: //not_equal ++ __ subl(AT, op1, op2); ++ __ selne(AT, src, dst, dst); ++ break; ++ ++ case 0x03: //above ++ __ cmpult(AT, op2, op1); ++ __ selne(AT, src, dst, dst); ++ break; ++ ++ case 0x04: //above_equal ++ __ cmpult(AT, op1, op2); ++ __ seleq(AT, src, dst, dst); ++ break; ++ ++ case 0x05: //below ++ __ cmpult(AT, op1, op2); ++ __ selne(AT, src, dst, dst); ++ break; ++ ++ case 0x06: //below_equal ++ __ cmpult(AT, op2, op1); ++ __ seleq(AT, src, dst, dst); ++ break; ++ ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct cmovN_cmpU_reg_reg(mRegN dst, mRegN src, mRegI tmp1, mRegI tmp2, cmpOpU cop ) %{ ++ match(Set dst (CMoveN (Binary cop (CmpU tmp1 tmp2)) (Binary dst src))); ++ ins_cost(80); ++ format %{ ++ "CMPU$cop $tmp1,$tmp2\t @cmovN_cmpU_reg_reg\n\t" ++ "CMOV $dst,$src\t @cmovN_cmpU_reg_reg" ++ %} ++ ins_encode %{ ++ Register op1 = $tmp1$$Register; ++ Register op2 = $tmp2$$Register; ++ Register dst = $dst$$Register; ++ Register src = $src$$Register; ++ int flag = $cop$$cmpcode; ++ ++ switch(flag) { ++ case 0x01: //equal ++ __ subw(AT, op1, op2); ++ __ seleq(AT, src, dst, dst); ++ break; ++ ++ case 0x02: //not_equal ++ __ subw(AT, op1, op2); ++ __ selne(AT, src, dst, dst); ++ break; ++ ++ case 0x03: //above ++ __ cmpult(AT, op2, op1); ++ __ selne(AT, src, dst, dst); ++ break; ++ ++ case 0x04: //above_equal ++ __ cmpult(AT, op1, op2); ++ __ seleq(AT, src, dst, dst); ++ break; ++ ++ case 0x05: //below ++ __ cmpult(AT, op1, op2); ++ __ selne(AT, src, dst, dst); ++ break; ++ ++ case 0x06: //below_equal ++ __ cmpult(AT, op2, op1); ++ __ seleq(AT, src, dst, dst); ++ break; ++ ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct cmovN_cmpL_reg_reg(mRegN dst, mRegN src, mRegL tmp1, mRegL tmp2, cmpOp cop) %{ ++ match(Set dst (CMoveN (Binary cop (CmpL tmp1 tmp2)) (Binary dst src))); ++ ins_cost(80); ++ format %{ ++ "CMP$cop $tmp1, $tmp2\t @cmovN_cmpL_reg_reg\n" ++ "\tCMOV $dst,$src \t @cmovN_cmpL_reg_reg" ++ %} ++ ins_encode %{ ++ Register opr1 = as_Register($tmp1$$reg); ++ Register opr2 = as_Register($tmp2$$reg); ++ Register dst = $dst$$Register; ++ Register src = $src$$Register; ++ int flag = $cop$$cmpcode; ++ ++ switch(flag) { ++ case 0x01: //equal ++ __ subl(AT, opr1, opr2); ++ __ seleq(AT, src, dst, dst); ++ break; ++ ++ case 0x02: //not_equal ++ __ subl(AT, opr1, opr2); ++ __ selne(AT, src, dst, dst); ++ break; ++ ++ case 0x03: //greater ++ __ cmplt(AT, opr2, opr1); ++ __ selne(AT, src, dst, dst); ++ break; ++ ++ case 0x04: //greater_equal ++ __ cmplt(AT, opr1, opr2); ++ __ seleq(AT, src, dst, dst); ++ break; ++ ++ case 0x05: //less ++ __ cmplt(AT, opr1, opr2); ++ __ selne(AT, src, dst, dst); ++ break; ++ ++ case 0x06: //less_equal ++ __ cmplt(AT, opr2, opr1); ++ __ seleq(AT, src, dst, dst); ++ break; ++ ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct cmovN_cmpI_reg_reg(mRegN dst, mRegN src, mRegI tmp1, mRegI tmp2, cmpOp cop ) %{ ++ match(Set dst (CMoveN (Binary cop (CmpI tmp1 tmp2)) (Binary dst src))); ++ ins_cost(80); ++ format %{ ++ "CMP$cop $tmp1,$tmp2\t @cmovN_cmpI_reg_reg\n\t" ++ "CMOV $dst,$src\t @cmovN_cmpI_reg_reg" ++ %} ++ ins_encode %{ ++ Register op1 = $tmp1$$Register; ++ Register op2 = $tmp2$$Register; ++ Register dst = $dst$$Register; ++ Register src = $src$$Register; ++ int flag = $cop$$cmpcode; ++ ++ switch(flag) { ++ case 0x01: //equal ++ __ subw(AT, op1, op2); ++ __ seleq(AT, src, dst, dst); ++ break; ++ ++ case 0x02: //not_equal ++ __ subw(AT, op1, op2); ++ __ selne(AT, src, dst, dst); ++ break; ++ ++ case 0x03: //above ++ __ cmplt(AT, op2, op1); ++ __ selne(AT, src, dst, dst); ++ break; ++ ++ case 0x04: //above_equal ++ __ cmplt(AT, op1, op2); ++ __ seleq(AT, src, dst, dst); ++ break; ++ ++ case 0x05: //below ++ __ cmplt(AT, op1, op2); ++ __ selne(AT, src, dst, dst); ++ break; ++ ++ case 0x06: //below_equal ++ __ cmplt(AT, op2, op1); ++ __ seleq(AT, src, dst, dst); ++ break; ++ ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct cmovN_cmpI_reg_imm(mRegN dst, immI_0_255 src, mRegI tmp1, mRegI tmp2, cmpOp cop ) %{ ++ match(Set dst (CMoveN (Binary cop (CmpI tmp1 tmp2)) (Binary dst src))); ++ ins_cost(80); ++ format %{ ++ "CMP$cop $tmp1,$tmp2\t @cmovN_cmpI_reg_imm\n\t" ++ "CMOV $dst,$src\t @cmovN_cmpI_reg_imm" ++ %} ++ ins_encode %{ ++ Register op1 = $tmp1$$Register; ++ Register op2 = $tmp2$$Register; ++ Register dst = $dst$$Register; ++ int src = $src$$constant & ((1<<8)-1); // Mask to 8 bits ++ int flag = $cop$$cmpcode; ++ ++ switch(flag) ++ { ++ case 0x01: //equal ++ __ subl(AT, op1, op2); ++ __ seleq(AT,src,dst,dst); ++ break; ++ ++ case 0x02: //not_equal ++ __ subl(AT, op1, op2); ++ __ selne(AT,src,dst,dst); ++ break; ++ ++ case 0x03: //above ++ __ cmplt(AT, op2, op1); ++ __ selne(AT,src,dst,dst); ++ break; ++ ++ case 0x04: //above_equal ++ __ cmplt(AT, op1, op2); ++ __ seleq(AT,src,dst,dst); ++ break; ++ ++ case 0x05: //below ++ __ cmplt(AT, op1, op2); ++ __ selne(AT,src,dst,dst); ++ break; ++ ++ case 0x06: //below_equal ++ __ cmplt(AT, op2, op1); ++ __ seleq(AT,src,dst,dst); ++ break; ++ ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct cmovL_cmpU_reg_reg(mRegL dst, mRegL src1, mRegL src2, mRegI tmp1, mRegI tmp2, cmpOpU cop ) %{ ++ match(Set dst (CMoveL (Binary cop (CmpU tmp1 tmp2)) (Binary src2 src1))); ++ ins_cost(80); ++ format %{ ++ "CMPU$cop $tmp1,$tmp2\t @cmovL_cmpU_reg_reg\n\t" ++ "CMOV $src2,$src1\t @cmovL_cmpU_reg_reg" ++ %} ++ ins_encode %{ ++ Register op1 = $tmp1$$Register; ++ Register op2 = $tmp2$$Register; ++ Register dst = $dst$$Register; ++ Register src1 = $src1$$Register; ++ Register src2 = $src2$$Register; ++ int flag = $cop$$cmpcode; ++ ++ switch(flag) { ++ case 0x01: //equal ++ __ subw(AT, op1, op2); ++ __ seleq(AT, src1, src2, dst); ++ break; ++ ++ case 0x02: //not_equal ++ __ subw(AT, op1, op2); ++ __ selne(AT, src1, src2, dst); ++ break; ++ ++ case 0x03: //above ++ __ cmpult(AT, op2, op1); ++ __ selne(AT, src1, src2, dst); ++ break; ++ ++ case 0x04: //above_equal ++ __ cmpult(AT, op1, op2); ++ __ seleq(AT, src1, src2, dst); ++ break; ++ ++ case 0x05: //below ++ __ cmpult(AT, op1, op2); ++ __ selne(AT, src1, src2, dst); ++ break; ++ ++ case 0x06: //below_equal ++ __ cmpult(AT, op2, op1); ++ __ seleq(AT, src1, src2, dst); ++ break; ++ ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct cmovL_cmpF_reg_reg(mRegL dst, mRegL src1, mRegL src2, regF tmp1, regF tmp2, cmpOp cop ) %{ ++ match(Set dst (CMoveL (Binary cop (CmpF tmp1 tmp2)) (Binary src2 src1))); ++ ins_cost(80); ++ format %{ ++ "CMP$cop $tmp1, $tmp2\t @cmovL_cmpF_reg_reg\n" ++ "\tCMOV $src2,$src1 \t @cmovL_cmpF_reg_reg" ++ %} ++ ++ ins_encode %{ ++ FloatRegister reg_op1 = $tmp1$$FloatRegister; ++ FloatRegister reg_op2 = $tmp2$$FloatRegister; ++ Register dst = $dst$$Register; ++ Register src1 = $src1$$Register; ++ Register src2 = $src2$$Register; ++ int flag = $cop$$cmpcode; ++ ++ switch(flag) { ++ case 0x01: //equal ++ __ fcmpeq(FcmpRES, reg_op1, reg_op2); ++ __ fimovd(GP, FcmpRES); ++ __ selne(GP, src1, src2, dst); ++ break; ++ case 0x02: //not_equal ++ __ fcmpeq(FcmpRES, reg_op1, reg_op2); ++ __ fimovd(GP, FcmpRES); ++ __ seleq(GP, src1, src2, dst); ++ break; ++ case 0x03: //greater ++ __ fcmple(FcmpRES, reg_op1, reg_op2); ++ __ fimovd(GP, FcmpRES); ++ __ seleq(GP, src1, src2, dst); ++ break; ++ case 0x04: //greater_equal ++ __ fcmplt(FcmpRES, reg_op1, reg_op2); ++ __ fimovd(GP, FcmpRES); ++ __ seleq(GP, src1, src2, dst); ++ break; ++ case 0x05: //less ++ __ fcmple(FcmpRES, reg_op2, reg_op1); ++ __ fimovd(GP, FcmpRES); ++ __ seleq(GP, src1, src2, dst); ++ break; ++ case 0x06: //less_equal ++ __ fcmplt(FcmpRES, reg_op2, reg_op1); ++ __ fimovd(GP, FcmpRES); ++ __ seleq(GP, src1, src2, dst); ++ break; ++ default: ++ Unimplemented(); ++ } ++ %} ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct cmovL_cmpI_reg_reg(mRegL dst, mRegL src1, mRegL src2, mRegI tmp1, mRegI tmp2, cmpOp cop ) %{ ++ match(Set dst (CMoveL (Binary cop (CmpI tmp1 tmp2)) (Binary src2 src1))); ++ ins_cost(80); ++ format %{ ++ "CMP$cop $tmp1, $tmp2\t @cmovL_cmpI_reg_reg\n" ++ "\tCMOV $src2,$src1 \t @cmovL_cmpI_reg_reg" ++ %} ++ ++ ins_encode %{ ++ Register op1 = $tmp1$$Register; ++ Register op2 = $tmp2$$Register; ++ Register dst = as_Register($dst$$reg); ++ Register src1 = as_Register($src1$$reg); ++ Register src2 = as_Register($src2$$reg); ++ int flag = $cop$$cmpcode; ++ ++ switch(flag) ++ { ++ case 0x01: //equal ++ __ subw(AT, op1, op2); ++ __ seleq(AT, src1, src2, dst); ++ break; ++ ++ case 0x02: //not_equal ++ __ subw(AT, op1, op2); ++ __ selne(AT, src1, src2, dst); ++ break; ++ ++ case 0x03: //great ++ __ cmplt(AT, op2, op1); ++ __ selne(AT, src1, src2, dst); ++ break; ++ ++ case 0x04: //great_equal ++ __ cmplt(AT, op1, op2); ++ __ seleq(AT, src1, src2, dst); ++ break; ++ ++ case 0x05: //less ++ __ cmplt(AT, op1, op2); ++ __ selne(AT, src1, src2, dst); ++ break; ++ ++ case 0x06: //less_equal ++ __ cmplt(AT, op2, op1); ++ __ seleq(AT, src1, src2, dst); ++ break; ++ ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct cmovL_cmpI_reg_imm(mRegL dst, immI_0_255 src1, mRegL src2, mRegI tmp1, mRegI tmp2, cmpOp cop ) %{ ++ match(Set dst (CMoveL (Binary cop (CmpI tmp1 tmp2)) (Binary src2 src1))); ++ ins_cost(80); ++ format %{ ++ "CMP$cop $tmp1, $tmp2\t @cmovL_cmpI_reg_imm\n" ++ "\tCMOV $src2,$src1 \t @cmovL_cmpI_reg_imm" ++ %} ++ ++ ins_encode %{ ++ Register op1 = $tmp1$$Register; ++ Register op2 = $tmp2$$Register; ++ Register dst = as_Register($dst$$reg); ++ int src1 = $src1$$constant & ((1<<8)-1); // Mask to 8 bits ++ Register src2 = as_Register($src2$$reg); ++ int flag = $cop$$cmpcode; ++ ++ switch(flag) ++ { ++ case 0x01: //equal ++ __ subl(AT, op1, op2); ++ __ seleq(AT, src1, src2, dst); ++ break; ++ ++ case 0x02: //not_equal ++ __ subl(AT, op1, op2); ++ __ selne(AT, src1, src2, dst); ++ break; ++ ++ case 0x03: //great ++ __ cmplt(AT, op2, op1); ++ __ selne(AT, src1, src2, dst); ++ break; ++ ++ case 0x04: //great_equal ++ __ cmplt(AT, op1, op2); ++ __ seleq(AT, src1, src2, dst); ++ break; ++ ++ case 0x05: //less ++ __ cmplt(AT, op1, op2); ++ __ selne(AT, src1, src2, dst); ++ break; ++ ++ case 0x06: //less_equal ++ __ cmplt(AT, op2, op1); ++ __ seleq(AT, src1, src2, dst); ++ break; ++ ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct cmovL_cmpL_reg_reg(mRegL dst, mRegL src1, mRegL src2, mRegL tmp1, mRegL tmp2, cmpOp cop ) %{ ++ match(Set dst (CMoveL (Binary cop (CmpL tmp1 tmp2)) (Binary src2 src1))); ++ ins_cost(80); ++ format %{ ++ "CMP$cop $tmp1, $tmp2\t @cmovL_cmpL_reg_reg\n" ++ "\tCMOV $src2,$src1 \t @cmovL_cmpL_reg_reg" ++ %} ++ ins_encode %{ ++ Register opr1 = as_Register($tmp1$$reg); ++ Register opr2 = as_Register($tmp2$$reg); ++ Register dst = as_Register($dst$$reg); ++ Register src1 = as_Register($src1$$reg); ++ Register src2 = as_Register($src2$$reg); ++ int flag = $cop$$cmpcode; ++ ++ switch(flag) { ++ case 0x01: //equal ++ __ subl(AT, opr1, opr2); ++ __ seleq(AT, src1, src2, dst); ++ break; ++ ++ case 0x02: //not_equal ++ __ subl(AT, opr1, opr2); ++ __ selne(AT, src1, src2, dst); ++ break; ++ ++ case 0x03: //greater ++ __ cmplt(AT, opr2, opr1); ++ __ selne(AT, src1, src2, dst); ++ break; ++ ++ case 0x04: //greater_equal ++ __ cmplt(AT, opr1, opr2); ++ __ seleq(AT, src1, src2, dst); ++ break; ++ ++ case 0x05: //less ++ __ cmplt(AT, opr1, opr2); ++ __ selne(AT, src1, src2, dst); ++ break; ++ ++ case 0x06: //less_equal ++ __ cmplt(AT, opr2, opr1); ++ __ seleq(AT, src1, src2, dst); ++ break; ++ ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct cmovL_cmpL_reg_imm(mRegL dst, immI_0_255 src1, mRegL src2, mRegL tmp1, mRegL tmp2, cmpOp cop ) %{ ++ match(Set dst (CMoveL (Binary cop (CmpL tmp1 tmp2)) (Binary src2 src1))); ++ ins_cost(80); ++ format %{ ++ "CMP$cop $tmp1, $tmp2\t @cmovL_cmpL_reg_imm\n" ++ "\tCMOV $src2,$src1 \t @cmovL_cmpL_reg_imm" ++ %} ++ ins_encode %{ ++ Register opr1 = as_Register($tmp1$$reg); ++ Register opr2 = as_Register($tmp2$$reg); ++ Register dst = as_Register($dst$$reg); ++ int src1 = $src1$$constant & ((1<<8)-1); // Mask to 8 bits ++ Register src2 = as_Register($src2$$reg); ++ int flag = $cop$$cmpcode; ++ ++ switch(flag) ++ { ++ case 0x01: //equal ++ __ subl(AT, opr1, opr2); ++ __ seleq(AT, src1, src2, dst); ++ break; ++ ++ case 0x02: //not_equal ++ __ subl(AT, opr1, opr2); ++ __ selne(AT, src1, src2, dst); ++ break; ++ ++ case 0x03: //greater ++ __ cmplt(AT, opr2, opr1); ++ __ selne(AT, src1, src2, dst); ++ break; ++ ++ case 0x04: //greater_equal ++ __ cmplt(AT, opr1, opr2); ++ __ seleq(AT, src1, src2, dst); ++ break; ++ ++ case 0x05: //less ++ __ cmplt(AT, opr1, opr2); ++ __ selne(AT, src1, src2, dst); ++ break; ++ ++ case 0x06: //less_equal ++ __ cmplt(AT, opr2, opr1); ++ __ seleq(AT, src1, src2, dst); ++ break; ++ ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct cmovL_cmpN_reg_reg(mRegL dst, mRegL src, mRegN tmp1, mRegN tmp2, cmpOpU cop ) %{ ++ match(Set dst (CMoveL (Binary cop (CmpN tmp1 tmp2)) (Binary dst src))); ++ ins_cost(80); ++ format %{ ++ "CMPU$cop $tmp1,$tmp2\t @cmovL_cmpN_reg_reg\n\t" ++ "CMOV $dst,$src\t @cmovL_cmpN_reg_reg" ++ %} ++ ins_encode %{ ++ Register op1 = $tmp1$$Register; ++ Register op2 = $tmp2$$Register; ++ Register dst = $dst$$Register; ++ Register src = $src$$Register; ++ int flag = $cop$$cmpcode; ++ ++ switch(flag) { ++ case 0x01: //equal ++ __ subw(AT, op1, op2); ++ __ seleq(AT, src, dst, dst); ++ break; ++ ++ case 0x02: //not_equal ++ __ subw(AT, op1, op2); ++ __ selne(AT, src, dst, dst); ++ break; ++ ++ case 0x03: //above ++ __ cmpult(AT, op2, op1); ++ __ selne(AT, src, dst, dst); ++ break; ++ ++ case 0x04: //above_equal ++ __ cmpult(AT, op1, op2); ++ __ seleq(AT, src, dst, dst); ++ break; ++ ++ case 0x05: //below ++ __ cmpult(AT, op1, op2); ++ __ selne(AT, src, dst, dst); ++ break; ++ ++ case 0x06: //below_equal ++ __ cmpult(AT, op2, op1); ++ __ seleq(AT, src, dst, dst); ++ break; ++ ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct cmovL_cmpN_reg_imm(mRegL dst, immI_0_255 src, mRegN tmp1, mRegN tmp2, cmpOpU cop ) %{ ++ match(Set dst (CMoveL (Binary cop (CmpN tmp1 tmp2)) (Binary dst src))); ++ ins_cost(80); ++ format %{ ++ "CMPU$cop $tmp1,$tmp2\t @cmovL_cmpN_reg_imm\n\t" ++ "CMOV $dst,$src\t @cmovL_cmpN_reg_imm" ++ %} ++ ins_encode %{ ++ Register op1 = $tmp1$$Register; ++ Register op2 = $tmp2$$Register; ++ Register dst = $dst$$Register; ++ int src = $src$$constant & ((1<<8)-1); // Mask to 8 bits ++ int flag = $cop$$cmpcode; ++ ++ switch(flag) ++ { ++ case 0x01: //equal ++ __ subl(AT, op1, op2); ++ __ seleq(AT,src,dst,dst); ++ break; ++ ++ case 0x02: //not_equal ++ __ subl(AT, op1, op2); ++ __ selne(AT,src,dst,dst); ++ break; ++ ++ case 0x03: //above ++ __ cmpult(AT, op2, op1); ++ __ selne(AT,src,dst,dst); ++ break; ++ ++ case 0x04: //above_equal ++ __ cmpult(AT, op1, op2); ++ __ seleq(AT,src,dst,dst); ++ break; ++ ++ case 0x05: //below ++ __ cmpult(AT, op1, op2); ++ __ selne(AT,src,dst,dst); ++ break; ++ ++ case 0x06: //below_equal ++ __ cmpult(AT, op2, op1); ++ __ seleq(AT,src,dst,dst); ++ break; ++ ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct cmovL_cmpD_reg_reg(mRegL dst, mRegL src1, mRegL src2, regD tmp1, regD tmp2, cmpOp cop ) %{ ++ match(Set dst (CMoveL (Binary cop (CmpD tmp1 tmp2)) (Binary src2 src1))); ++ ins_cost(80); ++ format %{ ++ "CMP$cop $tmp1, $tmp2\t @cmovL_cmpD_reg_reg\n" ++ "\tCMOV $src2,$src1 \t @cmovL_cmpD_reg_reg" ++ %} ++ ins_encode %{ ++ FloatRegister reg_op1 = as_FloatRegister($tmp1$$reg); ++ FloatRegister reg_op2 = as_FloatRegister($tmp2$$reg); ++ Register dst = as_Register($dst$$reg); ++ Register src1 = as_Register($src1$$reg); ++ Register src2 = as_Register($src2$$reg); ++ ++ int flag = $cop$$cmpcode; ++ ++ switch(flag) { ++ case 0x01: //equal ++ __ fcmpeq(FcmpRES, reg_op1, reg_op2); ++ __ fimovd(GP, FcmpRES); ++ __ selne(GP, src1, src2, dst); ++ break; ++ case 0x02: //not_equal ++ __ fcmpeq(FcmpRES, reg_op1, reg_op2); ++ __ fimovd(GP, FcmpRES); ++ __ seleq(GP, src1, src2, dst); ++ break; ++ case 0x03: //greater ++ __ fcmple(FcmpRES, reg_op1, reg_op2); ++ __ fimovd(GP, FcmpRES); ++ __ seleq(GP, src1, src2, dst); ++ break; ++ case 0x04: //greater_equal ++ __ fcmplt(FcmpRES, reg_op1, reg_op2); ++ __ fimovd(GP, FcmpRES); ++ __ seleq(GP, src1, src2, dst); ++ break; ++ case 0x05: //less ++ __ fcmple(FcmpRES, reg_op2, reg_op1); ++ __ fimovd(GP, FcmpRES); ++ __ seleq(GP, src1, src2, dst); ++ break; ++ case 0x06: //less_equal ++ __ fcmplt(FcmpRES, reg_op2, reg_op1); ++ __ fimovd(GP, FcmpRES); ++ __ seleq(GP, src1, src2, dst); ++ break; ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct cmovL_cmpD_reg_imm(mRegL dst, immI_0_255 src1, mRegL src2, regD tmp1, regD tmp2, cmpOp cop ) %{ ++ match(Set dst (CMoveL (Binary cop (CmpD tmp1 tmp2)) (Binary src2 src1))); ++ ins_cost(80); ++ format %{ ++ "CMP$cop $tmp1, $tmp2\t @cmovL_cmpD_reg_imm\n" ++ "\tCMOV $src2,$src1 \t @cmovL_cmpD_reg_imm" ++ %} ++ ins_encode %{ ++ FloatRegister reg_op1 = as_FloatRegister($tmp1$$reg); ++ FloatRegister reg_op2 = as_FloatRegister($tmp2$$reg); ++ Register dst = as_Register($dst$$reg); ++ int src1 = $src1$$constant & ((1<<8)-1); // Mask to 8 bits ++ Register src2 = as_Register($src2$$reg); ++ ++ int flag = $cop$$cmpcode; ++ ++ switch(flag) ++ { ++ case 0x01: //equal ++ __ fcmpeq(FcmpRES, reg_op1, reg_op2); ++ __ fimovd(GP, FcmpRES); ++ __ selne(GP, src1, src2, dst); ++ break; ++ case 0x02: //not_equal ++ __ fcmpeq(FcmpRES, reg_op1, reg_op2); ++ __ fimovd(GP, FcmpRES); ++ __ seleq(GP, src1, src2, dst); ++ break; ++ case 0x03: //greater ++ __ fcmple(FcmpRES, reg_op1, reg_op2); ++ __ fimovd(GP, FcmpRES); ++ __ seleq(GP, src1, src2, dst); ++ break; ++ case 0x04: //greater_equal ++ __ fcmplt(FcmpRES, reg_op1, reg_op2); ++ __ fimovd(GP, FcmpRES); ++ __ seleq(GP, src1, src2, dst); ++ break; ++ case 0x05: //less ++ __ fcmple(FcmpRES, reg_op2, reg_op1); ++ __ fimovd(GP, FcmpRES); ++ __ seleq(GP, src1, src2, dst); ++ break; ++ case 0x06: //less_equal ++ __ fcmplt(FcmpRES, reg_op2, reg_op1); ++ __ fimovd(GP, FcmpRES); ++ __ seleq(GP, src1, src2, dst); ++ break; ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct cmovD_cmpD_reg_reg(regD dst, regD src1, regD src2, regD tmp1, regD tmp2, cmpOp cop ) %{ ++ match(Set dst (CMoveD (Binary cop (CmpD tmp1 tmp2)) (Binary src2 src1))); ++ ins_cost(200); ++ format %{ ++ "CMP$cop $tmp1, $tmp2\t @cmovD_cmpD_reg_reg\n" ++ "\tCMOV $dst,$src1 \t @cmovD_cmpD_reg_reg" ++ %} ++ ins_encode %{ ++ FloatRegister reg_op1 = as_FloatRegister($tmp1$$reg); ++ FloatRegister reg_op2 = as_FloatRegister($tmp2$$reg); ++ FloatRegister dst = as_FloatRegister($dst$$reg); ++ FloatRegister src1 = as_FloatRegister($src1$$reg); ++ FloatRegister src2 = as_FloatRegister($src2$$reg); ++ ++ int flag = $cop$$cmpcode; ++ ++ switch(flag) { ++ case 0x01: //equal ++ __ fcmpeq(FcmpRES, reg_op1, reg_op2); ++ __ fselne(FcmpRES, src1, src2, dst); ++ break; ++ case 0x02: //not_equal ++ __ fcmpeq(FcmpRES, reg_op1, reg_op2); ++ __ fseleq(FcmpRES, src1, src2, dst); ++ break; ++ case 0x03: //greater ++ __ fcmple(FcmpRES, reg_op1, reg_op2); ++ __ fseleq(FcmpRES, src1, src2, dst); ++ break; ++ case 0x04: //greater_equal ++ __ fcmplt(FcmpRES, reg_op1, reg_op2); ++ __ fseleq(FcmpRES, src1, src2, dst); ++ break; ++ case 0x05: //less ++ __ fcmple(FcmpRES, reg_op2, reg_op1); ++ __ fseleq(FcmpRES, src1, src2, dst); ++ break; ++ case 0x06: //less_equal ++ __ fcmplt(FcmpRES, reg_op2, reg_op1); ++ __ fseleq(FcmpRES, src1, src2, dst); ++ break; ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct cmovD_cmpF_reg_reg(regD dst, regD src1, regD src2, regF tmp1, regF tmp2, cmpOp cop ) %{ ++ match(Set dst (CMoveD (Binary cop (CmpF tmp1 tmp2)) (Binary src2 src1))); ++ ins_cost(200); ++ format %{ ++ "CMP$cop $tmp1, $tmp2\t @cmovD_cmpF_reg_reg\n" ++ "\tCMOV $src2,$src1 \t @cmovD_cmpF_reg_reg" ++ %} ++ ins_encode %{ ++ FloatRegister reg_op1 = as_FloatRegister($tmp1$$reg); ++ FloatRegister reg_op2 = as_FloatRegister($tmp2$$reg); ++ FloatRegister dst = as_FloatRegister($dst$$reg); ++ FloatRegister src1 = as_FloatRegister($src1$$reg); ++ FloatRegister src2 = as_FloatRegister($src2$$reg); ++ ++ int flag = $cop$$cmpcode; ++ ++ Label L; ++ ++ switch(flag) ++ { ++ case 0x01: //equal ++ __ fcmpeq(FcmpRES, reg_op1, reg_op2); ++ __ fselne(FcmpRES, src1, src2, dst); ++ break; ++ case 0x02: //not_equal ++ __ fcmpeq(FcmpRES, reg_op1, reg_op2); ++ __ fseleq(FcmpRES, src1, src2, dst); ++ break; ++ case 0x03: //greater ++ __ fcmple(FcmpRES, reg_op1, reg_op2); ++ __ fseleq(FcmpRES, src1, src2, dst); ++ break; ++ case 0x04: //greater_equal ++ __ fcmplt(FcmpRES, reg_op1, reg_op2); ++ __ fseleq(FcmpRES, src1, src2, dst); ++ break; ++ case 0x05: //less ++ __ fcmple(FcmpRES, reg_op2, reg_op1); ++ __ fseleq(FcmpRES, src1, src2, dst); ++ break; ++ case 0x06: //less_equal ++ __ fcmplt(FcmpRES, reg_op2, reg_op1); ++ __ fseleq(FcmpRES, src1, src2, dst); ++ break; ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pipe( pipe_slow ); ++ ++ %} ++ ++instruct cmovF_cmpI_reg_reg(regF dst, regF src, mRegI tmp1, mRegI tmp2, cmpOp cop ) %{ ++ match(Set dst (CMoveF (Binary cop (CmpI tmp1 tmp2)) (Binary dst src))); ++ ins_cost(200); ++ format %{ ++ "CMP$cop $tmp1, $tmp2\t @cmovF_cmpI_reg_reg\n" ++ "\tCMOV $dst, $src \t @cmovF_cmpI_reg_reg" ++ %} ++ ++ ins_encode %{ ++ Register op1 = $tmp1$$Register; ++ Register op2 = $tmp2$$Register; ++ FloatRegister dst = as_FloatRegister($dst$$reg); ++ FloatRegister src = as_FloatRegister($src$$reg); ++ int flag = $cop$$cmpcode; ++ Label L; ++ ++ switch(flag) { ++ case 0x01: //equal ++ __ bne(op1, op2, L); ++ __ fmovs(dst, src); ++ __ BIND(L); ++ break; ++ case 0x02: //not_equal ++ __ beq(op1, op2, L); ++ __ fmovs(dst, src); ++ __ BIND(L); ++ break; ++ case 0x03: //great ++ __ cmplt(AT, op2, op1); ++ __ beq(AT, L); ++ __ fmovs(dst, src); ++ __ BIND(L); ++ break; ++ case 0x04: //great_equal ++ __ cmplt(AT, op1, op2); ++ __ bne(AT, L); ++ __ fmovs(dst, src); ++ __ BIND(L); ++ break; ++ case 0x05: //less ++ __ cmplt(AT, op1, op2); ++ __ beq(AT, L); ++ __ fmovs(dst, src); ++ __ BIND(L); ++ break; ++ case 0x06: //less_equal ++ __ cmplt(AT, op2, op1); ++ __ bne(AT, L); ++ __ fmovs(dst, src); ++ __ BIND(L); ++ break; ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct cmovD_cmpI_reg_reg(regD dst, regD src, mRegI tmp1, mRegI tmp2, cmpOp cop ) %{ ++ match(Set dst (CMoveD (Binary cop (CmpI tmp1 tmp2)) (Binary dst src))); ++ ins_cost(200); ++ format %{ ++ "CMP$cop $tmp1, $tmp2\t @cmovD_cmpI_reg_reg\n" ++ "\tCMOV $dst, $src \t @cmovD_cmpI_reg_reg" ++ %} ++ ++ ins_encode %{ ++ Register op1 = $tmp1$$Register; ++ Register op2 = $tmp2$$Register; ++ FloatRegister dst = as_FloatRegister($dst$$reg); ++ FloatRegister src = as_FloatRegister($src$$reg); ++ int flag = $cop$$cmpcode; ++ Label L; ++ ++ switch(flag) { ++ case 0x01: //equal ++ __ bne(op1, op2, L); ++ __ fmovd(dst, src); ++ __ BIND(L); ++ break; ++ case 0x02: //not_equal ++ __ beq(op1, op2, L); ++ __ fmovd(dst, src); ++ __ BIND(L); ++ break; ++ case 0x03: //great ++ __ cmplt(AT, op2, op1); ++ __ beq(AT, L); ++ __ fmovd(dst, src); ++ __ BIND(L); ++ break; ++ case 0x04: //great_equal ++ __ cmplt(AT, op1, op2); ++ __ bne(AT, L); ++ __ fmovd(dst, src); ++ __ BIND(L); ++ break; ++ case 0x05: //less ++ __ cmplt(AT, op1, op2); ++ __ beq(AT, L); ++ __ fmovd(dst, src); ++ __ BIND(L); ++ break; ++ case 0x06: //less_equal ++ __ cmplt(AT, op2, op1); ++ __ bne(AT, L); ++ __ fmovd(dst, src); ++ __ BIND(L); ++ break; ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct cmovD_cmpP_reg_reg(regD dst, regD src, mRegP tmp1, mRegP tmp2, cmpOp cop ) %{ ++ match(Set dst (CMoveD (Binary cop (CmpP tmp1 tmp2)) (Binary dst src))); ++ ins_cost(200); ++ format %{ ++ "CMP$cop $tmp1, $tmp2\t @cmovD_cmpP_reg_reg\n" ++ "\tCMOV $dst, $src \t @cmovD_cmpP_reg_reg" ++ %} ++ ++ ins_encode %{ ++ Register op1 = $tmp1$$Register; ++ Register op2 = $tmp2$$Register; ++ FloatRegister dst = as_FloatRegister($dst$$reg); ++ FloatRegister src = as_FloatRegister($src$$reg); ++ int flag = $cop$$cmpcode; ++ Label L; ++ ++ switch(flag) { ++ case 0x01: //equal ++ __ bne(op1, op2, L); ++ __ fmovd(dst, src); ++ __ BIND(L); ++ break; ++ case 0x02: //not_equal ++ __ beq(op1, op2, L); ++ __ fmovd(dst, src); ++ __ BIND(L); ++ break; ++ case 0x03: //great ++ __ cmplt(AT, op2, op1); ++ __ beq(AT, L); ++ __ fmovd(dst, src); ++ __ BIND(L); ++ break; ++ case 0x04: //great_equal ++ __ cmplt(AT, op1, op2); ++ __ bne(AT, L); ++ __ fmovd(dst, src); ++ __ BIND(L); ++ break; ++ case 0x05: //less ++ __ cmplt(AT, op1, op2); ++ __ beq(AT, L); ++ __ fmovd(dst, src); ++ __ BIND(L); ++ break; ++ case 0x06: //less_equal ++ __ cmplt(AT, op2, op1); ++ __ bne(AT, L); ++ __ fmovd(dst, src); ++ __ BIND(L); ++ break; ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pipe( pipe_slow ); ++%} ++ ++ ++instruct cmovI_cmpF_reg_reg(mRegI dst, mRegI src1, mRegI src2, regF tmp1, regF tmp2, cmpOp cop ) %{ ++ match(Set dst (CMoveI (Binary cop (CmpF tmp1 tmp2)) (Binary src2 src1))); ++ ins_cost(80); ++ format %{ ++ "CMP$cop $tmp1, $tmp2\t @cmovI_cmpF_reg_reg\n" ++ "\tCMOV $src2,$src1 \t @cmovI_cmpF_reg_reg" ++ %} ++ ++ ins_encode %{ ++ FloatRegister reg_op1 = $tmp1$$FloatRegister; ++ FloatRegister reg_op2 = $tmp2$$FloatRegister; ++ Register dst = $dst$$Register; ++ Register src1 = $src1$$Register; ++ Register src2 = $src2$$Register; ++ int flag = $cop$$cmpcode; ++ ++ switch(flag) { ++ case 0x01: //equal ++ __ fcmpeq(FcmpRES, reg_op1, reg_op2); ++ __ fimovd(GP, FcmpRES); ++ __ selne(GP, src1, src2, dst); ++ break; ++ case 0x02: //not_equal ++ __ fcmpeq(FcmpRES, reg_op1, reg_op2); ++ __ fimovd(GP, FcmpRES); ++ __ seleq(GP, src1, src2, dst); ++ break; ++ case 0x03: //greater ++ __ fcmple(FcmpRES, reg_op1, reg_op2); ++ __ fimovd(GP, FcmpRES); ++ __ seleq(GP, src1, src2, dst); ++ break; ++ case 0x04: //greater_equal ++ __ fcmplt(FcmpRES, reg_op1, reg_op2); ++ __ fimovd(GP, FcmpRES); ++ __ seleq(GP, src1, src2, dst); ++ break; ++ case 0x05: //less ++ __ fcmple(FcmpRES, reg_op2, reg_op1); ++ __ fimovd(GP, FcmpRES); ++ __ seleq(GP, src1, src2, dst); ++ break; ++ case 0x06: //less_equal ++ __ fcmplt(FcmpRES, reg_op2, reg_op1); ++ __ fimovd(GP, FcmpRES); ++ __ seleq(GP, src1, src2, dst); ++ break; ++ default: ++ Unimplemented(); ++ } ++ %} ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct cmovI_cmpF_reg_imm(mRegI dst, immI_0_255 src1, mRegI src2, regF tmp1, regF tmp2, cmpOp cop ) %{ ++ match(Set dst (CMoveI (Binary cop (CmpF tmp1 tmp2)) (Binary src2 src1))); ++ ins_cost(80); ++ format %{ ++ "CMP$cop $tmp1, $tmp2\t @cmovI_cmpF_reg_imm\n" ++ "\tCMOV $src2,$src1 \t @cmovI_cmpF_reg_imm" ++ %} ++ ++ ins_encode %{ ++ FloatRegister reg_op1 = $tmp1$$FloatRegister; ++ FloatRegister reg_op2 = $tmp2$$FloatRegister; ++ Register dst = $dst$$Register; ++ int src1 = $src1$$constant & ((1<<8)-1); // Mask to 8 bits ++ Register src2 = $src2$$Register; ++ int flag = $cop$$cmpcode; ++ ++ switch(flag) ++ { ++ case 0x01: //equal ++ __ fcmpeq(FcmpRES, reg_op1, reg_op2); ++ __ fimovd(GP, FcmpRES); ++ __ selne(GP, src1, src2, dst); ++ break; ++ case 0x02: //not_equal ++ __ fcmpeq(FcmpRES, reg_op1, reg_op2); ++ __ fimovd(GP, FcmpRES); ++ __ seleq(GP, src1, src2, dst); ++ break; ++ case 0x03: //greater ++ __ fcmple(FcmpRES, reg_op1, reg_op2); ++ __ fimovd(GP, FcmpRES); ++ __ seleq(GP, src1, src2, dst); ++ break; ++ case 0x04: //greater_equal ++ __ fcmplt(FcmpRES, reg_op1, reg_op2); ++ __ fimovd(GP, FcmpRES); ++ __ seleq(GP, src1, src2, dst); ++ break; ++ case 0x05: //less ++ __ fcmple(FcmpRES, reg_op2, reg_op1); ++ __ fimovd(GP, FcmpRES); ++ __ seleq(GP, src1, src2, dst); ++ break; ++ case 0x06: //less_equal ++ __ fcmplt(FcmpRES, reg_op2, reg_op1); ++ __ fimovd(GP, FcmpRES); ++ __ seleq(GP, src1, src2, dst); ++ break; ++ default: ++ Unimplemented(); ++ } ++ %} ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct cmovF_cmpF_reg_reg(regF dst, regF src1, regF src2, regF tmp1, regF tmp2, cmpOp cop ) %{ ++ match(Set dst (CMoveF (Binary cop (CmpF tmp1 tmp2)) (Binary src2 src1))); ++ ins_cost(200); ++ format %{ ++ "CMP$cop $tmp1, $tmp2\t @cmovF_cmpF_reg_reg\n" ++ "\tCMOV $src2,$src1 \t @cmovF_cmpF_reg_reg" ++ %} ++ ++ ins_encode %{ ++ FloatRegister reg_op1 = $tmp1$$FloatRegister; ++ FloatRegister reg_op2 = $tmp2$$FloatRegister; ++ FloatRegister dst = $dst$$FloatRegister; ++ FloatRegister src1 = $src1$$FloatRegister; ++ FloatRegister src2 = $src2$$FloatRegister; ++ int flag = $cop$$cmpcode; ++ ++ switch(flag) { ++ case 0x01: //equal ++ __ fcmpeq(FcmpRES, reg_op1, reg_op2); ++ __ fselne(FcmpRES, src1, src2, dst); ++ break; ++ case 0x02: //not_equal ++ __ fcmpeq(FcmpRES, reg_op1, reg_op2); ++ __ fseleq(FcmpRES, src1, src2, dst); ++ break; ++ case 0x03: //greater ++ __ fcmple(FcmpRES, reg_op1, reg_op2); ++ __ fseleq(FcmpRES, src1, src2, dst); ++ break; ++ case 0x04: //greater_equal ++ __ fcmplt(FcmpRES, reg_op1, reg_op2); ++ __ fseleq(FcmpRES, src1, src2, dst); ++ break; ++ case 0x05: //less ++ __ fcmple(FcmpRES, reg_op2, reg_op1); ++ __ fseleq(FcmpRES, src1, src2, dst); ++ break; ++ case 0x06: //less_equal ++ __ fcmplt(FcmpRES, reg_op2, reg_op1); ++ __ fseleq(FcmpRES, src1, src2, dst); ++ break; ++ default: ++ Unimplemented(); ++ } ++ %} ++ ins_pipe( pipe_slow ); ++%} ++ ++// Manifest a CmpL result in an integer register. Very painful. ++// This is the test to avoid. ++instruct cmpL3_reg_reg(mRegI dst, mRegL src1, mRegL src2) %{ ++ match(Set dst (CmpL3 src1 src2)); ++ ins_cost(1000); ++ format %{ "cmpL3 $dst, $src1, $src2 @ cmpL3_reg_reg" %} ++ ins_encode %{ ++ Register opr1 = as_Register($src1$$reg); ++ Register opr2 = as_Register($src2$$reg); ++ Register dst = as_Register($dst$$reg); ++ ++ Label done; ++ ++ __ subl(AT, opr1, opr2); ++ __ subl(dst, R0, 1); ++ __ blt(AT, done); ++ ++ __ selgt(AT, 1, R0, dst); ++ __ BIND(done); ++ %} ++ ins_pipe( pipe_slow ); ++%} ++ ++// ++// less_rsult = -1 ++// greater_result = 1 ++// equal_result = 0 ++// nan_result = -1 ++// ++instruct cmpF3_reg_reg(mRegI dst, regF src1, regF src2) %{ ++ match(Set dst (CmpF3 src1 src2)); ++ ins_cost(1000); ++ format %{ "cmpF3 $dst, $src1, $src2 @ cmpF3_reg_reg" %} ++ ins_encode %{ ++ FloatRegister src1 = as_FloatRegister($src1$$reg); ++ FloatRegister src2 = as_FloatRegister($src2$$reg); ++ Register dst = as_Register($dst$$reg); ++ ++ Label Done; ++ ++ __ move(dst, -1); ++ __ fcmple(FcmpRES, src2, src1); ++ __ fbeq(FcmpRES, Done); ++ ++ __ fcmpeq(FcmpRES, src1, src2); ++ __ move(dst, 1); ++ __ fimovd(GP, FcmpRES); ++ __ selne(GP, R0, dst, dst); ++ ++ __ BIND(Done); ++ %} ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct cmpD3_reg_reg(mRegI dst, regD src1, regD src2) %{ ++ match(Set dst (CmpD3 src1 src2)); ++ ins_cost(1000); ++ format %{ "cmpD3 $dst, $src1, $src2 @ cmpD3_reg_reg" %} ++ ins_encode %{ ++ FloatRegister src1 = as_FloatRegister($src1$$reg); ++ FloatRegister src2 = as_FloatRegister($src2$$reg); ++ Register dst = as_Register($dst$$reg); ++ ++ Label Done; ++ ++ __ move(dst, -1); ++ __ fcmple(FcmpRES, src2, src1); ++ __ fbeq(FcmpRES, Done); ++ ++ __ fcmpeq(FcmpRES, src1, src2); ++ __ move(dst, 1); ++ __ fimovd(GP, FcmpRES); ++ __ selne(GP, R0, dst, dst); ++ ++ __ BIND(Done); ++ %} ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct clear_array(mRegL cnt, mRegP base, Universe dummy) %{ ++ match(Set dummy (ClearArray cnt base)); ++ format %{ "CLEAR_ARRAY base = $base, cnt = $cnt # Clear doublewords" %} ++ ins_encode %{ ++ //Assume cnt is the number of bytes in an array to be cleared, ++ //and base points to the starting address of the array. ++ Register base = $base$$Register; ++ Register num = $cnt$$Register; ++ Label Loop, done; ++ ++ __ move(T12, num); /* T12 = words */ ++ __ beq(T12, done); ++ __ move(AT, base); ++ ++ __ BIND(Loop); ++ __ stl(R0, Address(AT, 0)); ++ __ addl(AT, AT, wordSize); ++ __ subl(T12, T12, 1); ++ __ bne(T12, Loop); ++ __ BIND(done); ++ %} ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct string_compare(a4_RegP str1, mA5RegI cnt1, t6_RegP str2, mT7RegI cnt2, mT3RegI result) %{ ++ match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); ++ effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2); ++ ++ format %{ "String Compare $str1[len: $cnt1], $str2[len: $cnt2] -> $result @ string_compare" %} ++ ins_encode %{ ++ // Get the first character position in both strings ++ // [8] char array, [12] offset, [16] count ++ Register str1 = $str1$$Register; ++ Register str2 = $str2$$Register; ++ Register cnt1 = $cnt1$$Register; ++ Register cnt2 = $cnt2$$Register; ++ Register result = $result$$Register; ++ ++ Label L, Loop, haveResult, done; ++ ++ // compute the and difference of lengths (in result) ++ __ subl(result, cnt1, cnt2); // result holds the difference of two lengths ++ ++ // compute the shorter length (in cnt1) ++ __ cmplt(AT, cnt2, cnt1); ++ __ selne(AT, cnt2, cnt1, cnt1); ++ ++ // Now the shorter length is in cnt1 and cnt2 can be used as a tmp register ++ __ BIND(Loop); // Loop begin ++ __ ldhu(AT, str1, 0); ++ __ beq(cnt1, done); ++ ++ // compare current character ++ __ ldhu(cnt2, str2, 0); ++ __ addl(str1, str1, 2); ++ __ bne(AT, cnt2, haveResult); ++ __ addl(str2, str2, 2); ++ __ subl(cnt1, cnt1, 1); ++ __ beq(R0, Loop); ++ ++ __ BIND(haveResult); ++ __ subl(result, AT, cnt2); ++ ++ __ BIND(done); ++ %} ++ ++ ins_pipe( pipe_slow ); ++%} ++ ++// intrinsic optimization ++instruct string_equals(a4_RegP str1, a5_RegP str2, mT6RegI cnt, mT7RegI temp, no_Ax_mRegI result) %{ ++ match(Set result (StrEquals (Binary str1 str2) cnt)); ++ effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL temp); ++ ++ format %{ "String Equal $str1, $str2, len:$cnt tmp:$temp -> $result @ string_equals" %} ++ ins_encode %{ ++ // Get the first character position in both strings ++ // [8] char array, [12] offset, [16] count ++ Register str1 = $str1$$Register; ++ Register str2 = $str2$$Register; ++ Register cnt = $cnt$$Register; ++ Register tmp = $temp$$Register; ++ Register result = $result$$Register; ++ ++ Label L, Loop, haveResult, done; ++ ++ __ cmpeq(result, str1, str2); //same char[] ? ++ __ bne(result, done); ++ ++ __ or_ins(result, R0, 1); ++ __ beq(cnt,done); ++ ++ //check for alignment and position the pointers to the ends ++ __ or_ins(result, str1, str2); ++ __ and_imm8(result, result, 0x3); ++ // notZero means at least one not 4-byte aligned. ++ // We could optimize the case when both arrays are not aligned ++ // but it is not frequent case and it requires additional checks. ++ __ slll(cnt, cnt, exact_log2(sizeof(jchar))); // set byte count ++ __ bne(result, Loop); // char by char compare ++ ++ // Compare char[] arrays aligned to 4 bytes. ++ __ char_arrays_equals(str1, str2, cnt, result, ++ result, tmp, done); ++ __ or_ins(result, R0, 1); ++ __ beq(R0, done); ++ ++ // char by char compare ++ __ BIND(Loop); ++ __ ldhu(AT, str1, 0); // Loop begin ++ __ beq(cnt, done); // count == 0 ++ ++ // compare current character ++ __ ldhu(tmp, str2, 0); ++ __ addl(str1, str1, 2); ++ __ bne(AT, tmp, haveResult); ++ __ addl(str2, str2, 2); ++ __ subl(cnt, cnt, 2); ++ __ beq(R0, Loop); ++ ++ __ BIND(haveResult); ++ __ subl(result, AT, tmp); ++ ++ __ BIND(done); ++ %} ++ ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct array_equals(a4_RegP ary1, a5_RegP ary2, no_Ax_mRegI result) %{ ++ match(Set result (AryEq ary1 ary2)); ++ effect(USE_KILL ary1, USE_KILL ary2); ++ ++ format %{ "Array Equals $ary1,$ary2 -> $result @ array_equals" %} ++ ins_encode %{ ++ ++ Register ary1 = $ary1$$Register; ++ Register ary2 = $ary2$$Register; ++ Register result = $result$$Register; ++ ++ Label Lvector, Ldone, Lloop; ++ Label Ldone_hop, Lloop_hop, Ldone1; ++ ++ int length_offset = arrayOopDesc::length_offset_in_bytes(); ++ int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); ++ ++ // return true if the same array ++ __ cmpeq(GP, ary1, ary2); ++ __ bne(GP, Ldone); ++ ++ __ beq(ary1, Ldone1); ++ __ beq(ary2, Ldone1); ++ ++ //load the lengths of arrays ++ __ ldw_signed(AT, Address(ary1, length_offset)); ++ __ ldw_signed(GP, Address(ary2, length_offset)); ++ ++ // return false if the two arrays are not equal length ++ __ cmpeq(GP, AT, GP); ++ __ beq(GP, Ldone1); ++ __ beq(AT, Ldone); ++ ++ // load array addresses ++ __ ldi(ary1, ary1, base_offset); ++ __ ldi(ary2, ary2, base_offset); ++ ++ // set byte count ++ __ slll(AT, AT, exact_log2(sizeof(jchar))); ++ ++ // Compare char[] arrays aligned to 4 bytes. ++ __ char_arrays_equals(ary1, ary2, AT, result, ++ result, GP, Ldone_hop); ++ __ or_ins(result, R0, 1); // equals ++ __ beq(R0, Ldone_hop); ++ ++ __ BIND(Ldone); ++ __ or_ins(result, R0, 1); // equal ++ __ beq(R0, Ldone_hop); ++ ++ __ BIND(Ldone1); ++ __ or_ins(result, R0, 0); // not equal ++ ++ __ BIND(Ldone_hop); ++ %} ++ ++ ins_pipe( pipe_slow ); ++%} ++ ++//----------Arithmetic Instructions------------------------------------------- ++//----------Addition Instructions--------------------------------------------- ++instruct addI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{ ++ match(Set dst (AddI src1 src2)); ++ ++ format %{ "addw $dst, $src1, $src2 #@addI_Reg_Reg" %} ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ Register src1 = $src1$$Register; ++ Register src2 = $src2$$Register; ++ __ addw(dst, src1, src2); ++ %} ++ ins_pipe( ialu_regI_regI ); ++%} ++ ++instruct addI_Reg_imm_0_255(mRegI dst, mRegI src1, immI_0_255 src2) %{ ++ match(Set dst (AddI src1 src2)); ++ ++ ins_cost(40); ++ format %{ "addw $dst, $src1, $src2 #@addI_Reg_imm_0_255" %} ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ Register src1 = $src1$$Register; ++ int imm = $src2$$constant; ++ __ addw(dst, src1, imm); ++ %} ++ ins_pipe( ialu_regI_imm16 ); ++%} ++ ++//instruct addI_Reg_imm(mRegI dst, mRegI src1, immI src2) %{ ++// match(Set dst (AddI src1 src2)); ++// ++// format %{ "addw $dst, $src1, $src2 #@addI_Reg_imm" %} ++// ins_encode %{ ++// Register dst = $dst$$Register; ++// Register src1 = $src1$$Register; ++// int imm = $src2$$constant; ++// ++// if(Assembler::is_uimm8(imm)) { ++// __ addw(dst, src1, imm); ++// } else { ++// __ move(AT, imm); ++// __ addw(dst, src1, AT); ++// } ++// %} ++// ins_pipe( ialu_regI_regI ); ++//%} ++ ++instruct addP_reg_reg(mRegP dst, mRegP src1, mRegLorI2L src2) %{ ++ match(Set dst (AddP src1 src2)); ++ ++ format %{ "ADDP $dst, $src1, $src2 #@addP_reg_reg" %} ++ ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ Register src1 = $src1$$Register; ++ Register src2 = $src2$$Register; ++ __ addl(dst, src1, src2); ++ %} ++ ++ ins_pipe( ialu_regI_regI ); ++%} ++ ++instruct addP_reg_reg_convI2L(mRegP dst, mRegP src1, mRegI src2) %{ ++ match(Set dst (AddP src1 (ConvI2L src2))); ++ ++ format %{ "dadd $dst, $src1, $src2 #@addP_reg_reg_convI2L" %} ++ ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ Register src1 = $src1$$Register; ++ Register src2 = $src2$$Register; ++ __ addl(dst, src1, src2); ++ %} ++ ++ ins_pipe( ialu_regI_regI ); ++%} ++ ++instruct addP_reg_imm_0_255(mRegP dst, mRegP src1, immL_0_255 src2) %{ ++ match(Set dst (AddP src1 src2)); ++ ++ ins_cost(40); ++ format %{ "dadd $dst, $src1, $src2 #@addP_reg_imm_0_255" %} ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ Register src1 = $src1$$Register; ++ int imm = $src2$$constant; ++ __ addl(dst, src1, imm); ++ %} ++ ins_pipe( ialu_regL_imm16 ); ++%} ++ ++instruct addP_reg_imm(mRegP dst, mRegP src1, immL src2) %{ ++ match(Set dst (AddP src1 src2)); ++ ++ format %{ "add_simm16 $dst, $src1, $src2 #@addP_reg_imm" %} ++ ins_encode %{ ++ Register src1 = $src1$$Register; ++ long src2 = $src2$$constant; ++ Register dst = $dst$$Register; ++ ++ if(Assembler::is_simm16(src2)) { ++ __ add_simm16(dst, src1, src2); ++ } else { ++ __ set64(AT, src2); ++ __ addl(dst, src1, AT); ++ } ++ %} ++ ins_pipe( ialu_regI_imm16 ); ++%} ++ ++// Add Long Register with Register ++instruct addL_Reg_Reg(mRegL dst, mRegLorI2L src1, mRegLorI2L src2) %{ ++ match(Set dst (AddL src1 src2)); ++ ins_cost(200); ++ format %{ "ADDL $dst, $src1, $src2 #@addL_Reg_Reg\t" %} ++ ++ ins_encode %{ ++ Register dst_reg = as_Register($dst$$reg); ++ Register src1_reg = as_Register($src1$$reg); ++ Register src2_reg = as_Register($src2$$reg); ++ ++ __ addl(dst_reg, src1_reg, src2_reg); ++ %} ++ ++ ins_pipe( ialu_regL_regL ); ++%} ++ ++instruct addL_Reg_imm(mRegL dst, mRegLorI2L src1, immL16 src2) ++%{ ++ match(Set dst (AddL src1 src2)); ++ ++ format %{ "ADDL $dst, $src1, $src2 #@addL_Reg_immL16 " %} ++ ins_encode %{ ++ Register dst_reg = as_Register($dst$$reg); ++ Register src1_reg = as_Register($src1$$reg); ++ int src2_imm = $src2$$constant; ++ ++ __ add_simm16(dst_reg, src1_reg, src2_imm); ++ %} ++ ++ ins_pipe( ialu_regL_regL ); ++%} ++ ++ ++instruct addI_Reg_immI_M1_255(mRegI dst, mRegI src1, immI_M1_255 src2) %{ ++ match(Set dst (AddI src1 src2)); ++ ++ ins_cost(10); ++ format %{ "addw $dst, $src1, $src2 #@addI_Reg_immI_M1_255" %} ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ Register src1 = $src1$$Register; ++ int imm = $src2$$constant; ++ __ subw(dst, src1, -imm); ++ %} ++ ins_pipe( ialu_regI_imm16 ); ++%} ++ ++//----------Subtraction Instructions------------------------------------------- ++// Integer Subtraction Instructions ++instruct subI_Reg_immI_M1(mRegI dst, mRegI src1, immI_M1_255 src2) %{ ++ match(Set dst (SubI src1 src2)); ++ ++ ins_cost(10); ++ format %{ "subw $dst, $src1, $src2 #@subI_Reg_immI_M1" %} ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ Register src1 = $src1$$Register; ++ int imm = $src2$$constant; ++ __ addw(dst, src1, -imm); ++ %} ++ ins_pipe( ialu_regI_imm16 ); ++%} ++ ++instruct subL_Reg_immL16(mRegL dst, mRegL src1, immL16_sub src2) %{ ++ match(Set dst (SubL src1 src2)); ++ ++ ins_cost(10); ++ format %{ "sul $dst, $src1, $src2 #@subL_Reg_immI_M1" %} ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ Register src1 = $src1$$Register; ++ int imm = $src2$$constant; ++ __ ldi(dst, src1, -1 * imm); ++ %} ++ ins_pipe( ialu_regI_imm16 ); ++%} ++ ++instruct subI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{ ++ match(Set dst (SubI src1 src2)); ++ ins_cost(100); ++ ++ format %{ "subw $dst, $src1, $src2 #@subI_Reg_Reg" %} ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ Register src1 = $src1$$Register; ++ Register src2 = $src2$$Register; ++ __ subw(dst, src1, src2); ++ %} ++ ins_pipe( ialu_regI_regI ); ++%} ++ ++instruct subI_Reg_imm_0_255(mRegI dst, mRegI src1, immI_0_255 src2) %{ ++ match(Set dst (SubI src1 src2)); ++ ins_cost(80); ++ ++ format %{ "subw $dst, $src1, $src2 #@subI_Reg_imm_0_255" %} ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ Register src1 = $src1$$Register; ++ int imm = $src2$$constant; ++ __ subw(dst, src1, imm); ++ %} ++ ins_pipe( ialu_regI_imm16 ); ++%} ++ ++instruct negI_reg(mRegI dst, immI0 zero, mRegI src2) %{ ++ match(Set dst (SubI zero src2)); ++ ins_cost(80); ++ ++ format %{ "NEG $src2,$dst #@negI_reg" %} ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ Register src = $src2$$Register; ++ __ subw (dst, R0, src); ++ %} ++ ins_pipe( ialu_regI_regI ); ++%} ++ ++instruct negL_Reg(mRegL dst, immL0 zero, mRegLorI2L src) %{ ++ match(Set dst (SubL zero src)); ++ ins_cost(80); ++ ++ format %{ "neg $dst, $src #@negL_Reg" %} ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ Register src = $src$$Register; ++ __ subl(dst, R0, src); ++ %} ++ ins_pipe( ialu_regI_regI ); ++%} ++ ++instruct subL_Reg_imm_0_255(mRegL dst, mRegL src1, immI_0_255 src2) %{ ++ match(Set dst (SubL src1 src2)); ++ ins_cost(80); ++ format %{ "SubL $dst, $src1, $src2 #@subL_Reg_imm_0_255" %} ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ Register src1 = $src1$$Register; ++ int imm = $src2$$constant; ++ __ subl(dst, src1, imm); ++ %} ++ ins_pipe( ialu_regL_imm16 ); ++%} ++ ++ ++// Subtract Long Register with Register. ++instruct subL_Reg_Reg(mRegL dst, mRegLorI2L src1, mRegLorI2L src2) %{ ++ match(Set dst (SubL src1 src2)); ++ ins_cost(100); ++ format %{ "SubL $dst, $src1, $src2 @ subL_Reg_Reg" %} ++ ins_encode %{ ++ Register dst = as_Register($dst$$reg); ++ Register src1 = as_Register($src1$$reg); ++ Register src2 = as_Register($src2$$reg); ++ ++ __ subl(dst, src1, src2); ++ %} ++ ins_pipe( ialu_regL_regL ); ++%} ++ ++ ++// Integer MOD with Register ++instruct modI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2, mT12RegI scratch) %{ ++ match(Set dst (ModI src1 src2)); ++ ins_cost(300); ++ format %{ "modi $dst, $src1, $src2 @ modI_Reg_Reg" %} ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ Register src1 = $src1$$Register; ++ Register src2 = $src2$$Register; ++ Register scratch = $scratch$$Register; ++ ++ if (UseSW8A) { ++ __ remw(src1, src2, dst); ++ } else if (FastIntRem) { ++ __ irem_sw(src1, src2, dst); ++ } else { ++ __ saveTRegisters(); ++ __ move(A0, src2); ++ if(src1==A0) ++ __ ldl(A1, SP, 96); ++ else ++ __ move(A1, src1); ++ __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::srem), 2); ++ __ move(scratch, V0); ++ __ restoreTRegisters(); ++ __ move(dst, scratch); ++ } ++ %} ++ ++ //ins_pipe( ialu_mod ); ++ ins_pipe( ialu_regI_regI ); ++%} ++ ++instruct modL_reg_reg(mRegL dst, mRegLorI2L src1, mRegLorI2L src2, t12_RegP scratch) %{ ++ match(Set dst (ModL src1 src2)); ++ format %{ "modL $dst, $src1, $src2 @modL_reg_reg" %} ++ ++ ins_encode %{ ++ Register dst = as_Register($dst$$reg); ++ Register op1 = as_Register($src1$$reg); ++ Register op2 = as_Register($src2$$reg); ++ Register scratch = $scratch$$Register; ++ ++ if (UseSW8A) { ++ __ reml(op1, op2, dst); ++ } else if (FastLongRem) { ++ Label lrem, exit; ++ Register tem = AT; ++ ++ __ slll(tem, op1, 0xb); ++ __ sral(tem, tem, 0xb); ++ __ cmpeq(tem, op1, tem); ++ __ bne(tem, lrem); ++ ++ __ saveTRegisters(); ++ __ move(A0, op2); ++ if(op1==A0) ++ __ ldl(A1, SP, 96); ++ else ++ __ move(A1, op1); ++ __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::lrem), 2); ++ __ move(scratch, V0); ++ __ restoreTRegisters(); ++ __ move(dst, scratch); ++ __ beq(R0, exit); ++ ++ __ BIND(lrem); ++ __ lrem_sw(op1, op2, dst); ++ ++ __ BIND(exit); ++ } else { ++ __ saveTRegisters(); ++ __ move(A0, op2); ++ if(op1==A0) ++ __ ldl(A1, SP, 96); ++ else ++ __ move(A1, op1); ++ __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::lrem), 2); ++ __ move(scratch, V0); ++ __ restoreTRegisters(); ++ __ move(dst, scratch); ++ } ++ %} ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct mulI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{ ++ match(Set dst (MulI src1 src2)); ++ ++ ins_cost(300); ++ format %{ "mul $dst, $src1, $src2 @ mulI_Reg_Reg" %} ++ ins_encode %{ ++ Register src1 = $src1$$Register; ++ Register src2 = $src2$$Register; ++ Register dst = $dst$$Register; ++ ++ __ mulw(dst, src1, src2); ++ %} ++ ins_pipe( ialu_mult ); ++%} ++ ++instruct mulI_Reg_imm_0_255(mRegI dst, mRegI src1, immI_0_255 src2) %{ ++ match(Set dst (MulI src1 src2)); ++ ++ ins_cost(300); ++ format %{ "mul $dst, $src1, $src2 @ mulI_Reg_imm_0_255" %} ++ ins_encode %{ ++ Register src1 = $src1$$Register; ++ int src2 = $src2$$constant; ++ Register dst = $dst$$Register; ++ ++ __ mulw(dst, src1, src2); ++ %} ++ ins_pipe( ialu_mult_imm ); ++%} ++ ++instruct maddI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2, mRegI src3) %{ ++ match(Set dst (AddI (MulI src1 src2) src3)); ++ ++ ins_cost(999); ++ format %{ "madd $dst, $src1 * $src2 + $src3 #@maddI_Reg_Reg" %} ++ ins_encode %{ ++ Register src1 = $src1$$Register; ++ Register src2 = $src2$$Register; ++ Register src3 = $src3$$Register; ++ Register dst = $dst$$Register; ++ ++ __ mulw(src1, src2, AT); ++ __ addw(dst, AT, src3); ++ %} ++ ins_pipe( ialu_mult ); ++%} ++ ++//SW64:OKOK:lix 20170526 ++instruct divI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2, mT12RegI scratch) %{ ++ match(Set dst (DivI src1 src2)); ++ ++ ++ format %{ "div $dst, $src1, $src2 @ divI_Reg_Reg" %} ++ ins_encode %{ ++ Register src1 = $src1$$Register; ++ Register src2 = $src2$$Register; ++ Register dst = $dst$$Register; ++ Register scratch = $scratch$$Register; ++ ++ if (UseSW8A) { ++ __ corrected_idivw(src1, src2, dst); ++ } else if (FastIntDiv) { ++ __ idiv_sw(src1, src2, dst); ++ } else { ++ __ saveTRegisters(); ++ __ move(A0, src2); ++ if(src1==A0) ++ __ ldl(A1, SP, 96); ++ else ++ __ move(A1, src1); ++ __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::sdiv), 2); ++ __ move(scratch, V0); ++ __ restoreTRegisters(); ++ __ move(dst, scratch); ++ } ++ %} ++ ins_pipe( ialu_mod ); ++%} ++ ++instruct divF_Reg_Reg(regF dst, regF src1, regF src2) %{ ++ match(Set dst (DivF src1 src2)); ++ ++ ins_cost(300); ++ format %{ "divF $dst, $src1, $src2 @ divF_Reg_Reg" %} ++ ins_encode %{ ++ FloatRegister src1 = $src1$$FloatRegister; ++ FloatRegister src2 = $src2$$FloatRegister; ++ FloatRegister dst = $dst$$FloatRegister; ++ ++ /* Here do we need to trap an exception manually ? */ ++ __ div_s(dst, src1, src2); ++ %} ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct divD_Reg_Reg(regD dst, regD src1, regD src2) %{ ++ match(Set dst (DivD src1 src2)); ++ ++ ins_cost(300); ++ format %{ "divD $dst, $src1, $src2 @ divD_Reg_Reg" %} ++ ins_encode %{ ++ FloatRegister src1 = $src1$$FloatRegister; ++ FloatRegister src2 = $src2$$FloatRegister; ++ FloatRegister dst = $dst$$FloatRegister; ++ ++ /* Here do we need to trap an exception manually ? */ ++ __ div_d(dst, src1, src2); ++ %} ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct mulL_reg_reg(mRegL dst, mRegLorI2L src1, mRegLorI2L src2) %{ ++ match(Set dst (MulL src1 src2)); ++ format %{ "mulL $dst, $src1, $src2 @mulL_reg_reg" %} ++ ins_encode %{ ++ Register dst = as_Register($dst$$reg); ++ Register op1 = as_Register($src1$$reg); ++ Register op2 = as_Register($src2$$reg); ++ ++ __ mull(op1, op2, dst); ++ %} ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct mulL_reg_regI2L(mRegL dst, mRegL src1, mRegI src2) %{ ++ match(Set dst (MulL src1 (ConvI2L src2))); ++ format %{ "mulL $dst, $src1, $src2 @mulL_reg_regI2L" %} ++ ins_encode %{ ++ Register dst = as_Register($dst$$reg); ++ Register op1 = as_Register($src1$$reg); ++ Register op2 = as_Register($src2$$reg); ++ ++ __ mull(op1, op2, dst); ++ %} ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct mulL_reg_imm_0_255(mRegL dst, mRegL src1, immL_0_255 src2) %{ ++ match(Set dst (MulI src1 src2)); ++ ins_cost(80); ++ format %{ "mul $dst, $src1, $src2 @ mulL_reg_imm_0_255" %} ++ ins_encode %{ ++ Register src1 = $src1$$Register; ++ int src2 = $src2$$constant; ++ Register dst = $dst$$Register; ++ ++ __ mull(src1, src2, dst); ++ %} ++ ins_pipe( mulL_reg_imm ); ++%} ++ ++instruct divL_reg_reg(mRegL dst, mRegL src1, mRegL src2, t12_RegP scratch) %{ ++ match(Set dst (DivL src1 src2)); ++ format %{ "divL $dst, $src1, $src2 @divL_reg_reg" %} ++ ++ ins_encode %{ ++ Register dst = as_Register($dst$$reg); ++ Register op1 = as_Register($src1$$reg); ++ Register op2 = as_Register($src2$$reg); ++ Register scratch = $scratch$$Register; ++ ++ if (UseSW8A) { ++ __ corrected_idivl(op1, op2, dst); ++ } else if (FastLongDiv) { ++ Label ldiv, exit; ++ Register tem = AT; ++ ++ __ slll(tem, op1, 0xb); ++ __ sral(tem, tem, 0xb); ++ __ cmpeq(tem, op1, tem); ++ __ bne(tem, ldiv); ++ ++ __ saveTRegisters(); ++ __ move(A0, op2); ++ if(op1 == A0) ++ __ ldl(A1, SP, 96); ++ else ++ __ move(A1, op1); ++ __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::ldiv), 2); ++ __ move(scratch, V0); ++ __ restoreTRegisters(); ++ __ move(dst, scratch); ++ __ beq(R0, exit); ++ ++ __ BIND(ldiv); ++ __ ldiv_sw(op1, op2, dst); ++ ++ __ BIND(exit); ++ } else { ++ __ saveTRegisters(); ++ __ move(A0, op2); ++ if(op1 == A0) ++ __ ldl(A1, SP, 96); ++ else ++ __ move(A1, op1); ++ __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::ldiv), 2); ++ __ move(scratch, V0); ++ __ restoreTRegisters(); ++ __ move(dst, scratch); ++ } ++ %} ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct addF_reg_reg(regF dst, regF src1, regF src2) %{ ++ match(Set dst (AddF src1 src2)); ++ format %{ "AddF $dst, $src1, $src2 @addF_reg_reg" %} ++ ins_encode %{ ++ FloatRegister src1 = as_FloatRegister($src1$$reg); ++ FloatRegister src2 = as_FloatRegister($src2$$reg); ++ FloatRegister dst = as_FloatRegister($dst$$reg); ++ ++ __ add_s(dst, src1, src2); ++ %} ++ ins_pipe( fpu_regF_regF ); ++%} ++ ++instruct subF_reg_reg(regF dst, regF src1, regF src2) %{ ++ match(Set dst (SubF src1 src2)); ++ format %{ "SubF $dst, $src1, $src2 @subF_reg_reg" %} ++ ins_encode %{ ++ FloatRegister src1 = as_FloatRegister($src1$$reg); ++ FloatRegister src2 = as_FloatRegister($src2$$reg); ++ FloatRegister dst = as_FloatRegister($dst$$reg); ++ ++ __ sub_s(dst, src1, src2); ++ %} ++ ins_pipe( fpu_regF_regF ); ++%} ++ ++instruct addD_reg_reg(regD dst, regD src1, regD src2) %{ ++ match(Set dst (AddD src1 src2)); ++ format %{ "AddD $dst, $src1, $src2 @addD_reg_reg" %} ++ ins_encode %{ ++ FloatRegister src1 = as_FloatRegister($src1$$reg); ++ FloatRegister src2 = as_FloatRegister($src2$$reg); ++ FloatRegister dst = as_FloatRegister($dst$$reg); ++ ++ __ add_d(dst, src1, src2); ++ %} ++ ins_pipe( fpu_regF_regF ); ++%} ++ ++instruct subD_reg_reg(regD dst, regD src1, regD src2) %{ ++ match(Set dst (SubD src1 src2)); ++ format %{ "SubD $dst, $src1, $src2 @subD_reg_reg" %} ++ ins_encode %{ ++ FloatRegister src1 = as_FloatRegister($src1$$reg); ++ FloatRegister src2 = as_FloatRegister($src2$$reg); ++ FloatRegister dst = as_FloatRegister($dst$$reg); ++ ++ __ sub_d(dst, src1, src2); ++ %} ++ ins_pipe( fpu_regF_regF ); ++%} ++ ++instruct negF_reg(regF dst, regF src) %{ ++ match(Set dst (NegF src)); ++ format %{ "negF $dst, $src @negF_reg" %} ++ ins_encode %{ ++ FloatRegister src = as_FloatRegister($src$$reg); ++ FloatRegister dst = as_FloatRegister($dst$$reg); ++ ++ __ fneg(dst, src); ++ %} ++ ins_pipe( fpu_regF_regF ); ++%} ++ ++instruct negD_reg(regD dst, regD src) %{ ++ match(Set dst (NegD src)); ++ format %{ "negD $dst, $src @negD_reg" %} ++ ins_encode %{ ++ FloatRegister src = as_FloatRegister($src$$reg); ++ FloatRegister dst = as_FloatRegister($dst$$reg); ++ ++ __ fneg(dst, src); ++ %} ++ ins_pipe( fpu_regF_regF ); ++%} ++ ++ ++instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{ ++ match(Set dst (MulF src1 src2)); ++ format %{ "MULF $dst, $src1, $src2 @mulF_reg_reg" %} ++ ins_encode %{ ++ FloatRegister src1 = $src1$$FloatRegister; ++ FloatRegister src2 = $src2$$FloatRegister; ++ FloatRegister dst = $dst$$FloatRegister; ++ ++ __ mul_s(dst, src1, src2); ++ %} ++ ins_pipe( fpu_regF_regF ); ++%} ++ ++instruct maddF_reg_reg(regF dst, regF src1, regF src2, regF src3) %{ ++ match(Set dst (AddF (MulF src1 src2) src3)); ++ ins_cost(10000); ++ format %{ "maddF $dst, $src1, $src2, $src3 @maddF_reg_reg" %} ++ ins_encode %{ ++ FloatRegister src1 = $src1$$FloatRegister; ++ FloatRegister src2 = $src2$$FloatRegister; ++ FloatRegister src3 = $src3$$FloatRegister; ++ FloatRegister dst = $dst$$FloatRegister; ++ ++ __ mul_s(F29, src1, src2); //F29 as FcmpRes, here use as tmp FloatRegister ++ __ add_s(dst, F29, src3); ++ %} ++ ins_pipe( fpu_regF_regF ); ++%} ++ ++// Mul two double precision floating piont number ++instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{ ++ match(Set dst (MulD src1 src2)); ++ format %{ "MULD $dst, $src1, $src2 @mulD_reg_reg" %} ++ ins_encode %{ ++ FloatRegister src1 = $src1$$FloatRegister; ++ FloatRegister src2 = $src2$$FloatRegister; ++ FloatRegister dst = $dst$$FloatRegister; ++ ++ __ mul_d(dst, src1, src2); ++ %} ++ ins_pipe( fpu_regF_regF ); ++%} ++ ++instruct maddD_reg_reg(regD dst, regD src1, regD src2, regD src3) %{ ++ match(Set dst (AddD (MulD src1 src2) src3)); ++ ins_cost(10000); ++ format %{ "maddD $dst, $src1, $src2, $src3 @maddD_reg_reg" %} ++ ins_encode %{ ++ FloatRegister src1 = $src1$$FloatRegister; ++ FloatRegister src2 = $src2$$FloatRegister; ++ FloatRegister src3 = $src3$$FloatRegister; ++ FloatRegister dst = $dst$$FloatRegister; ++ ++ __ mul_d(F29, src1, src2); //F29 as FcmpRes, here use as tmp FloatRegister ++ __ add_d(dst, F29, src3); ++ %} ++ ins_pipe( fpu_regF_regF ); ++%} ++ ++instruct absF_reg(regF dst, regF src) %{ ++ match(Set dst (AbsF src)); ++ ins_cost(100); ++ format %{ "absF $dst, $src @absF_reg" %} ++ ins_encode %{ ++ FloatRegister src = as_FloatRegister($src$$reg); ++ FloatRegister dst = as_FloatRegister($dst$$reg); ++ ++ __ fabs(dst, src); ++ %} ++ ins_pipe( fpu_regF_regF ); ++%} ++ ++ ++// intrinsics for math_native. ++// AbsD SqrtD CosD SinD TanD LogD Log10D ++ ++instruct absD_reg(regD dst, regD src) %{ ++ match(Set dst (AbsD src)); ++ ins_cost(100); ++ format %{ "absD $dst, $src @absD_reg" %} ++ ins_encode %{ ++ FloatRegister src = as_FloatRegister($src$$reg); ++ FloatRegister dst = as_FloatRegister($dst$$reg); ++ ++ __ fabs(dst, src); ++ %} ++ ins_pipe( fpu_regF_regF ); ++%} ++ ++instruct sqrtD_reg(regD dst, regD src) %{ ++ match(Set dst (SqrtD src)); ++ ins_cost(100); ++ format %{ "SqrtD $dst, $src @sqrtD_reg" %} ++ ins_encode %{ ++ FloatRegister src = as_FloatRegister($src$$reg); ++ FloatRegister dst = as_FloatRegister($dst$$reg); ++ ++ __ sqrt_d(dst, src); ++ %} ++ ins_pipe( fpu_regF_regF ); ++%} ++ ++instruct sqrtF_reg(regF dst, regF src) %{ ++ match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); ++ ins_cost(100); ++ format %{ "SqrtF $dst, $src @sqrtF_reg" %} ++ ins_encode %{ ++ FloatRegister src = as_FloatRegister($src$$reg); ++ FloatRegister dst = as_FloatRegister($dst$$reg); ++ ++ __ sqrt_s(dst, src); ++ %} ++ ins_pipe( fpu_regF_regF ); ++%} ++ ++//----------------------------------Logical Instructions---------------------- ++//__________________________________Integer Logical Instructions------------- ++ ++//And Instuctions ++// And Register with Immediate ++instruct andI_Reg_immI(mRegI dst, mRegI src1, immI src2) %{ ++ match(Set dst (AndI src1 src2)); ++ ++ format %{ "and $dst, $src1, $src2 #@andI_Reg_immI" %} ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ Register src = $src1$$Register; ++ int val = $src2$$constant; ++ ++ __ move(AT, val); ++ __ and_reg(dst, src, AT); ++ %} ++ ins_pipe( ialu_regI_regI ); ++%} ++ ++instruct andI_Reg_imm_0_255(mRegI dst, mRegI src1, immI_0_255 src2) %{ ++ match(Set dst (AndI src1 src2)); ++ ins_cost(60); ++ ++ format %{ "and $dst, $src1, $src2 #@andI_Reg_imm_0_255" %} ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ Register src = $src1$$Register; ++ int val = $src2$$constant; ++ ++ __ and_imm8(dst, src, val); ++ %} ++ ins_pipe( ialu_regI_regI ); ++%} ++ ++instruct xorI_Reg_imm_0_255(mRegI dst, mRegI src1, immI_0_255 src2) %{ ++ match(Set dst (XorI src1 src2)); ++ ins_cost(60); ++ ++ format %{ "xori $dst, $src1, $src2 #@xorI_Reg_imm_0_255" %} ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ Register src = $src1$$Register; ++ int val = $src2$$constant; ++ ++ __ xor_ins(dst, src, val); ++ %} ++ ins_pipe( ialu_regI_regI ); ++%} ++ ++instruct xorL_Reg_imm_0_255(mRegL dst, mRegL src1, immL_0_255 src2) %{ ++ match(Set dst (XorL src1 src2)); ++ ins_cost(60); ++ ++ format %{ "xori $dst, $src1, $src2 #@xorL_Reg_imm_0_255" %} ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ Register src = $src1$$Register; ++ int val = $src2$$constant; ++ ++ __ xor_ins(dst, src, val); ++ %} ++ ins_pipe( ialu_regI_regI ); ++%} ++ ++ ++instruct lbu_and_lmask(mRegI dst, memory mem, immI_255 mask) %{ ++ match(Set dst (AndI mask (LoadB mem))); ++ ins_cost(60); ++ ++ format %{ "lhu $dst, $mem #@lbu_and_lmask" %} ++ ins_encode(load_UB_enc(dst, mem)); ++ ins_pipe( ialu_loadI ); ++%} ++ ++instruct lbu_and_rmask(mRegI dst, memory mem, immI_255 mask) %{ ++ match(Set dst (AndI (LoadB mem) mask)); ++ ins_cost(60); ++ ++ format %{ "lhu $dst, $mem #@lbu_and_rmask" %} ++ ins_encode(load_UB_enc(dst, mem)); ++ ins_pipe( ialu_loadI ); ++%} ++ ++instruct andI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{ ++ match(Set dst (AndI src1 src2)); ++ ++ format %{ "and $dst, $src1, $src2 #@andI_Reg_Reg" %} ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ Register src1 = $src1$$Register; ++ Register src2 = $src2$$Register; ++ __ and_reg(dst, src1, src2); ++ %} ++ ins_pipe( ialu_regI_regI ); ++%} ++ ++// And Long Register with Register ++instruct andL_Reg_Reg(mRegL dst, mRegL src1, mRegLorI2L src2) %{ ++ match(Set dst (AndL src1 src2)); ++ format %{ "AND $dst, $src1, $src2 @ andL_Reg_Reg\n\t" %} ++ ins_encode %{ ++ Register dst_reg = as_Register($dst$$reg); ++ Register src1_reg = as_Register($src1$$reg); ++ Register src2_reg = as_Register($src2$$reg); ++ ++ __ and_reg(dst_reg, src1_reg, src2_reg); ++ %} ++ ins_pipe( ialu_regL_regL ); ++%} ++ ++instruct andL_Reg_imm_0_255(mRegL dst, mRegL src1, immL_0_255 src2) %{ ++ match(Set dst (AndL src1 src2)); ++ ins_cost(60); ++ ++ format %{ "and $dst, $src1, $src2 #@andL_Reg_imm_0_255" %} ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ Register src = $src1$$Register; ++ long val = $src2$$constant; ++ ++ __ and_imm8(dst, src, val); ++ %} ++ ins_pipe( ialu_regI_regI ); ++%} ++ ++instruct andL2I_Reg_imm_0_255(mRegI dst, mRegL src1, immL_0_255 src2) %{ ++ match(Set dst (ConvL2I (AndL src1 src2))); ++ ins_cost(60); ++ ++ format %{ "and $dst, $src1, $src2 #@andL2I_Reg_imm_0_255" %} ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ Register src = $src1$$Register; ++ long val = $src2$$constant; ++ ++ __ and_imm8(dst, src, val); ++ %} ++ ins_pipe( ialu_regI_regI ); ++%} ++ ++// Or Long Register with Register ++instruct orL_Reg_Reg(mRegL dst, mRegLorI2L src1, mRegLorI2L src2) %{ ++ match(Set dst (OrL src1 src2)); ++ format %{ "OR $dst, $src1, $src2 @ orL_Reg_Reg\t" %} ++ ins_encode %{ ++ Register dst_reg = $dst$$Register; ++ Register src1_reg = $src1$$Register; ++ Register src2_reg = $src2$$Register; ++ ++ __ or_ins(dst_reg, src1_reg, src2_reg); ++ %} ++ ins_pipe( ialu_regL_regL ); ++%} ++ ++instruct orL_Reg_P2XReg(mRegL dst, mRegP src1, mRegLorI2L src2) %{ ++ match(Set dst (OrL (CastP2X src1) src2)); ++ format %{ "OR $dst, $src1, $src2 @ orL_Reg_P2XReg\t" %} ++ ins_encode %{ ++ Register dst_reg = $dst$$Register; ++ Register src1_reg = $src1$$Register; ++ Register src2_reg = $src2$$Register; ++ ++ __ or_ins(dst_reg, src1_reg, src2_reg); ++ %} ++ ins_pipe( ialu_regL_regL ); ++%} ++ ++instruct orL_Reg_imm_0_255(mRegL dst, mRegL src1, immL_0_255 src2) %{ ++ match(Set dst (OrL src1 src2)); ++ ins_cost(80); ++ format %{ "OR $dst, $src1, $src2 @ orL_Reg_imm_0_255\t" %} ++ ins_encode %{ ++ Register dst_reg = $dst$$Register; ++ Register src1_reg = $src1$$Register; ++ int src2 = $src2$$constant; ++ ++ __ or_ins(dst_reg, src1_reg, src2); ++ %} ++ ins_pipe( ialu_regL_regL ); ++%} ++ ++// Xor Long Register with Register ++instruct xorL_Reg_Reg(mRegL dst, mRegL src1, mRegL src2) %{ ++ match(Set dst (XorL src1 src2)); ++ format %{ "XOR $dst, $src1, $src2 @ xorL_Reg_Reg\t" %} ++ ins_encode %{ ++ Register dst_reg = as_Register($dst$$reg); ++ Register src1_reg = as_Register($src1$$reg); ++ Register src2_reg = as_Register($src2$$reg); ++ ++ __ xor_ins(dst_reg, src1_reg, src2_reg); ++ %} ++ ins_pipe( ialu_regL_regL ); ++%} ++ ++// Bic Int Register with Register ++instruct andI_Reg_not_Reg(mRegI dst, mRegI src1, mRegI src2, immI_M1 m1) %{ ++ match(Set dst (AndI src1 (XorI src2 m1))); ++ ++ format %{ "ANDNOT $dst, $src1, $src2 #@bicI_Reg_Reg\t" %} ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ Register src1 = $src1$$Register; ++ Register src2 = $src2$$Register; ++ __ bic(dst, src1, src2); ++ %} ++ ins_pipe( ialu_regI_regI ); ++%} ++ ++// Bic long Register with Register ++instruct andL_Reg_not_Reg(mRegL dst, mRegL src1, mRegL src2, immL_M1 m1) %{ ++ match(Set dst (AndL src1 (XorL src2 m1))); ++ ++ format %{ "ANDNOT $dst, $src1, $src2 #@bicL_Reg_Reg\t" %} ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ Register src1 = $src1$$Register; ++ Register src2 = $src2$$Register; ++ __ bic(dst, src1, src2); ++ %} ++ ins_pipe( ialu_regL_regL ); ++%} ++ ++// Shift Left by 8-bit immediate ++instruct salI_Reg_imm(mRegI dst, mRegI src, immI_0_255 shift) %{ ++ match(Set dst (LShiftI src shift)); ++ ++ format %{ "SHL $dst, $src, $shift #@salI_Reg_imm" %} ++ ins_encode %{ ++ Register src = $src$$Register; ++ Register dst = $dst$$Register; ++ int shamt = $shift$$constant; ++ if(UseSW8A) { ++ __ sllw(src, shamt, dst); ++ } else { ++ __ sllw_signed(dst, src, shamt); ++ } ++ %} ++ ins_pipe( ialu_regI_regI ); ++%} ++ ++instruct land7_2_s(mRegI dst, mRegL src, immL7 seven, immI_16 sixteen) ++%{ ++ match(Set dst (RShiftI (LShiftI (ConvL2I (AndL src seven)) sixteen) sixteen)); ++ ++ format %{ "andi $dst, $src, 7\t# @land7_2_s" %} ++ ins_encode %{ ++ Register src = $src$$Register; ++ Register dst = $dst$$Register; ++ ++ __ and_imm8(dst, src, 7); ++ %} ++ ins_pipe(ialu_regI_regI); ++%} ++ ++// Logical Shift Right by 16, followed by Arithmetic Shift Left by 16. ++// This idiom is used by the compiler the i2s bytecode. ++instruct i2s(mRegI dst, mRegI src, immI_16 sixteen) ++%{ ++ match(Set dst (RShiftI (LShiftI src sixteen) sixteen)); ++ ++ format %{ "i2s $dst, $src\t# @i2s" %} ++ ins_encode %{ ++ Register src = $src$$Register; ++ Register dst = $dst$$Register; ++ ++ __ sexth(dst, src); // __ seh(dst, src); ++ %} ++ ins_pipe(ialu_regI_regI); ++%} ++ ++// Logical Shift Right by 24, followed by Arithmetic Shift Left by 24. ++// This idiom is used by the compiler for the i2b bytecode. ++instruct i2b(mRegI dst, mRegI src, immI_24 twentyfour) ++%{ ++ match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour)); ++ ++ format %{ "i2b $dst, $src\t# @i2b" %} ++ ins_encode %{ ++ Register src = $src$$Register; ++ Register dst = $dst$$Register; ++ ++ __ sextb(dst, src); // __ seb(dst, src); ++ %} ++ ins_pipe(ialu_regI_regI); ++%} ++ ++ ++instruct salI_RegL2I_imm(mRegI dst, mRegL src, immI_0_255 shift) %{ ++ match(Set dst (LShiftI (ConvL2I src) shift)); ++ ++ format %{ "SHL $dst, $src, $shift #@salI_RegL2I_imm" %} ++ ins_encode %{ ++ Register src = $src$$Register; ++ Register dst = $dst$$Register; ++ int shamt = $shift$$constant; ++ if(UseSW8A) { ++ __ sllw(src, shamt, dst); ++ } else { ++ __ sllw_signed(dst, src, shamt); ++ } ++ %} ++ ins_pipe( ialu_regI_regI ); ++%} ++ ++// Shift Left by 8-bit immediate ++instruct salI_Reg_Reg(mRegI dst, mRegI src, mRegI shift) %{ ++ match(Set dst (LShiftI src shift)); ++ ++ format %{ "SHL $dst, $src, $shift #@salI_Reg_Reg" %} ++ ins_encode %{ ++ Register src = $src$$Register; ++ Register dst = $dst$$Register; ++ Register shamt = $shift$$Register; ++ ++ if (UseSW8A) { ++ __ sllw(src, shamt, dst); ++ } else { ++ __ and_imm8(GP, shamt, 0x1f); ++ __ slll(dst, src, GP); ++ __ addw(dst, dst, 0x0); ++ } ++ %} ++ ins_pipe( ialu_regI_regI ); ++%} ++ ++ ++// Shift Left Long ++instruct salL_Reg_imm(mRegL dst, mRegLorI2L src, immI_0_255 shift) %{ ++ //predicate(UseNewLongLShift); ++ match(Set dst (LShiftL src shift)); ++ ins_cost(100); ++ format %{ "salL $dst, $src, $shift @ salL_Reg_imm" %} ++ ins_encode %{ ++ Register src_reg = as_Register($src$$reg); ++ Register dst_reg = as_Register($dst$$reg); ++ int shamt = $shift$$constant; ++ ++ __ slll(dst_reg, src_reg, shamt); ++ %} ++ ins_pipe( ialu_regL_regL ); ++%} ++ ++// Shift Left Long ++instruct salL_Reg_Reg(mRegL dst, mRegLorI2L src, mRegI shift) %{ ++ //predicate(UseNewLongLShift); ++ match(Set dst (LShiftL src shift)); ++ ins_cost(100); ++ format %{ "salL $dst, $src, $shift @ salL_Reg_Reg" %} ++ ins_encode %{ ++ Register src_reg = as_Register($src$$reg); ++ Register dst_reg = as_Register($dst$$reg); ++ ++ __ slll(dst_reg, src_reg, $shift$$Register); ++ %} ++ ins_pipe( ialu_regL_regL ); ++%} ++ ++// Shift Right Long ++instruct sarL_Reg_imm(mRegL dst, mRegLorI2L src, immI_0_255 shift) %{ ++ match(Set dst (RShiftL src shift)); ++ ins_cost(100); ++ format %{ "sarL $dst, $src, $shift @ sarL_Reg_imm" %} ++ ins_encode %{ ++ __ sral($dst$$Register, $src$$Register, $shift$$constant); ++ %} ++ ins_pipe( ialu_regL_regL ); ++%} ++ ++// Shift Right Long arithmetically ++instruct sarL_Reg_Reg(mRegL dst, mRegLorI2L src, mRegI shift) %{ ++ ++ match(Set dst (RShiftL src shift)); ++ ins_cost(100); ++ format %{ "sarL $dst, $src, $shift @ sarL_Reg_Reg" %} ++ ins_encode %{ ++ Register src_reg = as_Register($src$$reg); ++ Register dst_reg = as_Register($dst$$reg); ++ ++ __ sral(dst_reg, src_reg, $shift$$Register); ++ %} ++ ins_pipe( ialu_regL_regL ); ++%} ++ ++// Shift Right Long logically ++instruct slrL_Reg_Reg(mRegL dst, mRegL src, mRegI shift) %{ ++ match(Set dst (URShiftL src shift)); ++ ins_cost(100); ++ format %{ "slrL $dst, $src, $shift @ slrL_Reg_Reg" %} ++ ins_encode %{ ++ Register src_reg = as_Register($src$$reg); ++ Register dst_reg = as_Register($dst$$reg); ++ ++ __ srll(dst_reg, src_reg, $shift$$Register); ++ %} ++ ins_pipe( ialu_regL_regL ); ++%} ++ ++instruct slrL_Reg_immI_0_63(mRegL dst, mRegLorI2L src, immI_0_63 shift) %{ ++ match(Set dst (URShiftL src shift)); ++ ins_cost(80); ++ format %{ "slrL $dst, $src, $shift @ slrL_Reg_immI_0_63" %} ++ ins_encode %{ ++ Register src_reg = as_Register($src$$reg); ++ Register dst_reg = as_Register($dst$$reg); ++ int shamt = $shift$$constant; ++ ++ __ srll(dst_reg, src_reg, shamt); ++ %} ++ ins_pipe( ialu_regL_regL ); ++%} ++ ++instruct slrL_P2XReg_immI_0_63(mRegL dst, mRegP src, immI_0_63 shift) %{ ++ match(Set dst (URShiftL (CastP2X src) shift)); ++ ins_cost(80); ++ format %{ "slrL $dst, $src, $shift @ slrL_P2XReg_immI_0_63" %} ++ ins_encode %{ ++ Register src_reg = as_Register($src$$reg); ++ Register dst_reg = as_Register($dst$$reg); ++ int shamt = $shift$$constant; ++ ++ __ srll(dst_reg, src_reg, shamt); ++ %} ++ ins_pipe( ialu_regL_regL ); ++%} ++ ++// Xor Instructions ++// Xor Register with Register ++instruct xorI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{ ++ match(Set dst (XorI src1 src2)); ++ ++ format %{ "XOR $dst, $src1, $src2 #@xorI_Reg_Reg" %} ++ ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ Register src1 = $src1$$Register; ++ Register src2 = $src2$$Register; ++ __ xor_ins(dst, src1, src2); ++ %} ++ ++ ins_pipe( ialu_regI_regI ); ++%} ++ ++// Or Instructions ++// Or Register with Register ++instruct orI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{ ++ match(Set dst (OrI src1 src2)); ++ ++ format %{ "OR $dst, $src1, $src2 #@orI_Reg_Reg" %} ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ Register src1 = $src1$$Register; ++ Register src2 = $src2$$Register; ++ __ or_ins(dst, src1, src2); ++ %} ++ ++ ins_pipe( ialu_regI_regI ); ++%} ++ ++instruct orI_Reg_castP2X(mRegL dst, mRegL src1, mRegP src2) %{ ++ match(Set dst (OrI src1 (CastP2X src2))); ++ ++ format %{ "OR $dst, $src1, $src2 #@orI_Reg_castP2X" %} ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ Register src1 = $src1$$Register; ++ Register src2 = $src2$$Register; ++ __ or_ins(dst, src1, src2); ++ %} ++ ++ ins_pipe( ialu_regI_regI ); ++%} ++ ++instruct orI_Reg_imm_0_255(mRegI dst, mRegI src1, immI_0_255 src2) %{ ++ match(Set dst (OrI src1 src2)); ++ ins_cost(80); ++ ++ format %{ "OR $dst, $src1, $src2 #@orI_Reg_imm_0_255" %} ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ Register src1 = $src1$$Register; ++ int src2 = $src2$$constant; ++ __ or_ins(dst, src1, src2); ++ %} ++ ++ ins_pipe( ialu_regI_imm16 ); ++%} ++ ++// Logical Shift Right by 8-bit immediate ++instruct shr_logical_Reg_imm(mRegI dst, mRegI src, immI_0_255 shift) %{ ++ match(Set dst (URShiftI src shift)); ++ // effect(KILL cr); ++ ++ format %{ "SRL $dst, $src, $shift #@shr_logical_Reg_imm" %} ++ ins_encode %{ ++ Register src = $src$$Register; ++ Register dst = $dst$$Register; ++ int shift = $shift$$constant; ++ if(UseSW8A) { ++ __ srlw(src, shift, dst); ++ } else { ++ __ zapnot(dst, src, 0xf); ++ __ srll(dst, dst, shift&0x1f); ++ } ++ %} ++ ins_pipe( ialu_regI_regI ); ++%} ++ ++// Logical Shift Right ++instruct shr_logical_Reg_Reg(mRegI dst, mRegI src, mRegI shift) %{ ++ match(Set dst (URShiftI src shift)); ++ ++ format %{ "SRL $dst, $src, $shift #@shr_logical_Reg_Reg" %} ++ ins_encode %{ ++ Register src = $src$$Register; ++ Register dst = $dst$$Register; ++ Register shift = $shift$$Register; ++ if(UseSW8A) { ++ __ srlw(src, shift, dst); ++ } else { ++ __ and_imm8(GP, shift, 0x1f); ++ __ zapnot(dst, src, 0xf); ++ __ srll(dst, dst, GP); ++ } ++ %} ++ ins_pipe( ialu_regI_regI ); ++%} ++ ++ ++instruct shr_arith_Reg_imm(mRegI dst, mRegI src, immI_0_255 shift) %{ ++ match(Set dst (RShiftI src shift)); ++ // effect(KILL cr); ++ ++ format %{ "SRA $dst, $src, $shift #@shr_arith_Reg_imm" %} ++ ins_encode %{ ++ Register src = $src$$Register; ++ Register dst = $dst$$Register; ++ int shift = $shift$$constant; ++ if(UseSW8A) { ++ __ sraw(src, shift, dst); ++ } else { ++ __ sral(dst, src, shift&0x1f); ++ } ++ %} ++ ins_pipe( ialu_regI_regI ); ++%} ++ ++instruct shr_arith_Reg_Reg(mRegI dst, mRegI src, mRegI shift) %{ ++ match(Set dst (RShiftI src shift)); ++ // effect(KILL cr); ++ ++ format %{ "SRA $dst, $src, $shift #@shr_arith_Reg_Reg" %} ++ ins_encode %{ ++ Register src = $src$$Register; ++ Register dst = $dst$$Register; ++ Register shift = $shift$$Register; ++ if(UseSW8A) { ++ __ sraw(src, shift, dst); ++ } else { ++ __ and_imm8(GP, shift, 0x1f); ++ __ addw(dst, src, 0); ++ __ sral(dst, dst, GP); ++ } ++ %} ++ ins_pipe( ialu_regI_regI ); ++%} ++ ++instruct signExtract(mRegI dst, mRegI src1, immI_31 div1, immI_31 div2) %{ ++ match(Set dst (URShiftI (RShiftI src1 div1) div2)); ++ predicate(UseSW8A); ++ ins_cost(100); ++ format %{ "srlw $dst, $src1, $div1" %} ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ Register src = $src1$$Register; ++ int shamt = $div1$$constant; ++ if (UseSW8A) { ++ __ srlw(src, shamt, dst); ++ }else{ ++ Unimplemented(); ++ } ++ %} ++ ins_pipe(ialu_regI_regI); ++%} ++ ++instruct signExtractL(mRegL dst, mRegL src1, immI_63 div1, immI_63 div2) %{ ++ match(Set dst (URShiftL (RShiftL src1 div1) div2)); ++ ins_cost(100); ++ format %{ "srll $dst, $src1, $div1" %} ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ Register src = $src1$$Register; ++ int shamt = $div1$$constant; ++ __ srll(dst, src, shamt); ++ %} ++ ins_pipe(ialu_regL_regL); ++%} ++ ++instruct rolOrI(mRegI dst, mRegI src, immI lshift, immI rshift) %{ ++ predicate((0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f))&&UseSW8A); ++ match(Set dst (OrI (LShiftI src lshift) (URShiftI src rshift))); ++ ++ ins_cost(100); ++ format %{ "rolI $dst, $src, $lshift #@rolOrI" %} ++ ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ Register src = $src$$Register; ++ int sa = $lshift$$constant & 0x1f; ++ ++ if (UseSW8A) { ++ __ rolw(src, sa, dst); ++ }else{ ++ Unimplemented(); ++ } ++ %} ++ ins_pipe(ialu_regI_regI); ++%} ++ ++instruct rolOrL(mRegL dst, mRegL src, immL lshift, immL rshift) %{ ++ predicate((0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f))&&UseSW8A); ++ match(Set dst (OrL (LShiftL src lshift) (URShiftL src rshift))); ++ ++ ins_cost(100); ++ format %{ "rolL $dst, $src, $lshift #@rolOrL" %} ++ ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ Register src = $src$$Register; ++ int sa = $lshift$$constant & 0x3f; ++ ++ if (UseSW8A) { ++ __ roll(src, sa, dst); ++ }else{ ++ Unimplemented(); ++ } ++ %} ++ ins_pipe(ialu_regL_regL); ++%} ++ ++instruct rolAddI(mRegI dst, mRegI src, immI lshift, immI rshift) %{ ++ predicate((0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f))&&UseSW8A); ++ match(Set dst (AddI (LShiftI src lshift) (URShiftI src rshift))); ++ ++ ins_cost(100); ++ format %{ "rolI $dst, $src, $lshift #@rolAddI" %} ++ ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ Register src = $src$$Register; ++ int sa = $lshift$$constant & 0x1f; ++ ++ if (UseSW8A) { ++ __ rolw(src, sa, dst); ++ }else{ ++ Unimplemented(); ++ } ++ %} ++ ins_pipe(ialu_regI_regI); ++%} ++ ++instruct rolAddL(mRegL dst, mRegL src, immL lshift, immL rshift) %{ ++ predicate((0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f))&&UseSW8A); ++ match(Set dst (AddL (LShiftL src lshift) (URShiftL src rshift))); ++ ++ ins_cost(100); ++ format %{ "rolL $dst, $src, $lshift #@rolAddL" %} ++ ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ Register src = $src$$Register; ++ int sa = $lshift$$constant & 0x3f; ++ ++ if (UseSW8A) { ++ __ roll(src, sa, dst); ++ }else{ ++ Unimplemented(); ++ } ++ %} ++ ins_pipe(ialu_regL_regL); ++%} ++ ++instruct rolI_Reg_Var_c_0(mRegI dst, mRegI src, mRegI shift, immI0 c_0) %{ ++ match(Set dst (OrI (LShiftI src shift) (URShiftI src (SubI c_0 shift)))); ++ predicate(UseSW8A); ++ ins_cost(100); ++ format %{ "rolI $dst, $src, $shift #@rolI_Reg_Var_c_0" %} ++ ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ Register src = $src$$Register; ++ Register sa = $shift$$Register; ++ ++ if (UseSW8A) { ++ __ rolw(src, sa, dst); ++ }else{ ++ Unimplemented(); ++ } ++ %} ++ ins_pipe(ialu_regI_regI); ++%} ++ ++instruct rolL_Reg_Var_c_0(mRegL dst, mRegL src, mRegI shift, immI0 c_0) %{ ++ match(Set dst (OrL (LShiftL src shift) (URShiftL src (SubI c_0 shift)))); ++ predicate(UseSW8A); ++ ins_cost(100); ++ format %{ "rolL $dst, $src, $shift #@rolL_Reg_Var_c_0" %} ++ ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ Register src = $src$$Register; ++ Register sa = $shift$$Register; ++ ++ if (UseSW8A) { ++ __ roll(src, sa, dst); ++ }else{ ++ Unimplemented(); ++ } ++ %} ++ ins_pipe(ialu_regL_regL); ++%} ++ ++instruct rolI_Reg_Var_c_32(mRegI dst, mRegI src, mRegI shift, immI_32 c_32) %{ ++ match(Set dst (OrI (LShiftI src shift) (URShiftI src (SubI c_32 shift)))); ++ predicate(UseSW8A); ++ ins_cost(100); ++ format %{ "rolI $dst, $src, $shift #@rolI_Reg_Var_c_32" %} ++ ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ Register src = $src$$Register; ++ Register sa = $shift$$Register; ++ ++ if (UseSW8A) { ++ __ rolw(src, sa, dst); ++ }else{ ++ Unimplemented(); ++ } ++ %} ++ ins_pipe(ialu_regI_regI); ++%} ++ ++instruct rolL_Reg_Var_c_64(mRegL dst, mRegL src, mRegI shift, immI_64 c_64) %{ ++ match(Set dst (OrL (LShiftL src shift) (URShiftL src (SubI c_64 shift)))); ++ predicate(UseSW8A); ++ ins_cost(100); ++ format %{ "rolL $dst, $src, $shift #@rolL_Reg_Var_c_64" %} ++ ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ Register src = $src$$Register; ++ Register sa = $shift$$Register; ++ ++ if (UseSW8A) { ++ __ roll(src, sa, dst); ++ }else{ ++ Unimplemented(); ++ } ++ %} ++ ins_pipe(ialu_regL_regL); ++%} ++ ++instruct rorI_Reg_Var_c_0(mRegI dst, mRegI src, mRegI shift, immI0 c_0) %{ ++ match(Set dst (OrI (URShiftI src shift) (LShiftI src (SubI c_0 shift)))); ++ predicate(UseSW8A); ++ ins_cost(100); ++ format %{ "rorI $dst, $src, $shift #@rorI_Reg_Var_c_0" %} ++ ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ Register src = $src$$Register; ++ Register sa = $shift$$Register; ++ ++ if (UseSW8A) { ++ __ and_imm8(GP, sa, 0x1f); ++ __ subw(GP, R0, GP); ++ __ rolw(src, GP, dst); ++ }else{ ++ Unimplemented(); ++ } ++ %} ++ ins_pipe(ialu_regI_regI); ++%} ++ ++instruct rorL_Reg_Var_c_0(mRegL dst, mRegL src, mRegI shift, immI0 c_0) %{ ++ match(Set dst (OrL (URShiftL src shift) (LShiftL src (SubI c_0 shift)))); ++ predicate(UseSW8A); ++ ins_cost(100); ++ format %{ "rorL $dst, $src, $shift #@rorL_Reg_Var_c_0" %} ++ ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ Register src = $src$$Register; ++ Register sa = $shift$$Register; ++ ++ if (UseSW8A) { ++ __ and_imm8(GP, sa, 0x3f); ++ __ subw(GP, R0, GP); ++ __ roll(src, GP, dst); ++ }else{ ++ Unimplemented(); ++ } ++ %} ++ ins_pipe(ialu_regL_regL); ++%} ++ ++instruct rorI_Reg_Var_c_32(mRegI dst, mRegI src, mRegI shift, immI_32 c_32) %{ ++ match(Set dst (OrI (URShiftI src shift) (LShiftI src (SubI c_32 shift)))); ++ predicate(UseSW8A); ++ ins_cost(100); ++ format %{ "rorI $dst, $src, $shift #@rorI_Reg_Var_c_32" %} ++ ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ Register src = $src$$Register; ++ Register sa = $shift$$Register; ++ ++ if (UseSW8A) { ++ __ and_imm8(GP, sa, 0x1f); ++ __ subw(GP, R0, GP); ++ __ rolw(src, GP, dst); ++ }else{ ++ Unimplemented(); ++ } ++ %} ++ ins_pipe(ialu_regI_regI); ++%} ++ ++instruct rorL_Reg_Var_c_64(mRegL dst, mRegL src, mRegI shift, immI_64 c_64) %{ ++ match(Set dst (OrL (URShiftL src shift) (LShiftL src (SubI c_64 shift)))); ++ predicate(UseSW8A); ++ ins_cost(100); ++ format %{ "rorL $dst, $src, $shift #@rorL_Reg_Var_c_64" %} ++ ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ Register src = $src$$Register; ++ Register sa = $shift$$Register; ++ ++ if (UseSW8A) { ++ __ and_imm8(GP, sa, 0x3f); ++ __ subw(GP, R0, GP); ++ __ roll(src, GP, dst); ++ }else{ ++ Unimplemented(); ++ } ++ %} ++ ins_pipe(ialu_regL_regL); ++%} ++ ++//----------Convert Int to Boolean--------------------------------------------- ++ ++instruct movI_nocopy(mRegI dst, mRegI src) %{ ++ effect( DEF dst, USE src ); ++ format %{ "MOV $dst, $src @ movI_nocopy" %} ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ Register src = $src$$Register; ++ __ move(dst, src); ++ %} ++ ins_pipe( ialu_regI_regI ); ++%} ++ ++instruct ci2b(mRegI dst, mRegI src) %{ ++ effect( USE_DEF dst, USE src ); ++ ++ format %{ "NEG $dst @ ci2b\n\t" ++ "ADC $dst,$src @ ci2b" %} ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ Register src = $src$$Register; ++ Label L; ++//If ( dst != 0 ) CF = 1; ++ guarantee(dst != src, "in ci2b"); ++ __ move(AT, src); ++ __ beq(dst, L); ++ __ addl(AT, AT, 1); ++ __ BIND(L); ++// __ neg(dst); ++ __ subw(dst, R0, dst); ++ __ addl(dst, dst, AT); ++ %} ++ ++ ins_pipe( ialu_regL_regL ); ++%} ++ ++ ++instruct convI2B(mRegI dst, mRegI src) %{ ++ match(Set dst (Conv2B src)); ++ ++ ins_cost(100); ++ format %{ "convI2B $dst, $src @ convI2B" %} ++ ins_encode %{ ++ Register dst = as_Register($dst$$reg); ++ Register src = as_Register($src$$reg); ++ ++ __ selne(src, 1, src, dst); ++ %} ++ ++ ins_pipe( ialu_regL_regL ); ++%} ++ ++instruct convI2L_reg( mRegL dst, mRegI src) %{ ++ match(Set dst (ConvI2L src)); ++ ++ ins_cost(100); ++ format %{ "SLL $dst, $src @ convI2L_reg\t" %} ++ ins_encode %{ ++ Register dst = as_Register($dst$$reg); ++ Register src = as_Register($src$$reg); ++ ++ if(dst != src) __ addw(dst, src, 0); ++ %} ++ ins_pipe( ialu_regL_regL ); ++%} ++ ++ ++instruct convL2I_reg( mRegI dst, mRegLorI2L src ) %{ ++ match(Set dst (ConvL2I src)); ++ ++ format %{ "MOV $dst, $src @ convL2I_reg" %} ++ ins_encode %{ ++ Register dst = as_Register($dst$$reg); ++ Register src = as_Register($src$$reg); ++ ++ __ addw(dst, src, 0); ++ %} ++ ++ ins_pipe( ialu_regI_regI ); ++%} ++ ++instruct convL2I2L_reg( mRegL dst, mRegL src ) %{ ++ match(Set dst (ConvI2L (ConvL2I src))); ++ ++ format %{ "sll $dst, $src, 0 @ convL2I2L_reg" %} ++ ins_encode %{ ++ Register dst = as_Register($dst$$reg); ++ Register src = as_Register($src$$reg); ++ ++ __ sllw_signed(dst, src, 0); ++ %} ++ ++ ins_pipe( ialu_regI_regI ); ++%} ++ ++instruct convL2D_reg( regD dst, mRegL src ) %{ ++ match(Set dst (ConvL2D src)); ++ format %{ "convL2D $dst, $src @ convL2D_reg" %} ++ ins_encode %{ ++ Register src = as_Register($src$$reg); ++ FloatRegister dst = as_FloatRegister($dst$$reg); ++ if (UseSW8A) { ++ __ cmovld(dst, src); ++ } else { ++ __ ifmovd(F30, src); ++ __ fcvtld(dst, F30); ++ } ++ %} ++ ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct convD2L_reg_fast( mRegL dst, regD src ) %{ ++ match(Set dst (ConvD2L src)); ++ ins_cost(150); ++ format %{ "convD2L $dst, $src @ convD2L_reg_fast" %} ++ ins_encode %{ ++ Register dst = as_Register($dst$$reg); ++ FloatRegister src = as_FloatRegister($src$$reg); ++ if (UseSW8A) { ++ __ cmovdl_z(dst, src); ++ } else { ++ FloatRegister temp_float_reg = F30; ++ FloatRegister temp_float_reg1 = F28; ++ assert((temp_float_reg1 != $src$$FloatRegister), "can not use F28"); ++ assert((temp_float_reg1 != $dst$$FloatRegister), "can not use F28"); ++ ++ Label Convert,Overflow,Done; ++ __ fcmpun(temp_float_reg, src, src); ++ __ fbne(temp_float_reg, Convert); //If Unorder,Jump to Convert Label ++ ++ __ or_ins(T12, R0, 1); ++ __ slll(T12, T12, 63); ++ ++ __ ifmovd(temp_float_reg, T12); ++ __ fcvtld(temp_float_reg1, temp_float_reg); ++ __ fcmple(temp_float_reg, src, temp_float_reg1); ++ __ fbne(temp_float_reg, Overflow); //If less than min_long(0x8000000000000000),jump to Skip Label ++ ++ __ subl(T12, T12, 0x1); ++ __ ifmovd(temp_float_reg, T12); ++ __ fcvtld(temp_float_reg1, temp_float_reg); ++ __ fcmple(temp_float_reg, temp_float_reg1, src); ++ __ fbne (temp_float_reg, Overflow); //If >= max_long(0x7fffffffffffffff),jump to Skip Label ++ ++ //Label Convert ++ __ BIND(Convert); ++ __ fcvtdl_z(temp_float_reg, src);//lx20121018,result is rounded toward zero ++ __ fimovd(dst, temp_float_reg); ++ __ beq (R0, Done); ++ //Labe Skip ++ __ BIND(Overflow); ++ __ move(dst,T12); ++ __ BIND(Done); ++ } ++ %} ++ ++ ins_pipe( pipe_slow ); ++%} ++ ++ ++instruct convD2L_reg_slow( mRegL dst, regD src ) %{ ++ match(Set dst (ConvD2L src)); ++ ins_cost(250); ++ format %{ "convD2L $dst, $src @ convD2L_reg_slow" %} ++ ins_encode %{ ++ Register dst = as_Register($dst$$reg); ++ FloatRegister src = as_FloatRegister($src$$reg); ++ ++ __ saveTRegisters(); ++ __ fmovd(F16, src); ++ __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::d2l), 1); ++ __ move(T12, V0); ++ __ restoreTRegisters(); ++ __ move(dst, T12); ++ %} ++ ++ ins_pipe( pipe_slow ); ++%} ++ ++ ++instruct convF2I_reg_fast( mRegI dst, regF src ) %{ ++ match(Set dst (ConvF2I src)); ++ ins_cost(150); ++ format %{ "convf2i $dst, $src @ convF2I_reg_fast" %} ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ FloatRegister src = $src$$FloatRegister; ++ if (UseSW8A) { ++ __ cmovdw_z(dst, src); ++ } else { ++ Register temp_reg = T12; ++ FloatRegister temp_float_reg = F30; ++ FloatRegister temp_float_reg1 = F28; ++ Label Convert,Overflow,Done; ++ ++ __ fcmpun(temp_float_reg, src, src); ++ __ fbne(temp_float_reg,Convert); //If Unorder,Jump to Convert Label ++ ++ __ or_ins(temp_reg, R0, 1); ++ __ slll(temp_reg, temp_reg, 31); ++ ++ __ ifmovs(temp_float_reg, temp_reg); ++ __ fcvtwl(temp_float_reg1, temp_float_reg); ++ __ fcvtls(temp_float_reg, temp_float_reg1); ++ __ fcmple(temp_float_reg1, src, temp_float_reg); ++ __ fbne(temp_float_reg1,Overflow); //If less than min_int(0x80000000),jump to Skip Label ++ ++ __ subw(temp_reg, temp_reg,0x1); ++ __ ifmovs(temp_float_reg, temp_reg); ++ __ fcvtwl(temp_float_reg1, temp_float_reg); ++ __ fcvtls(temp_float_reg, temp_float_reg1); ++ __ fcmple(temp_float_reg1, temp_float_reg, src); ++ __ fbne(temp_float_reg1,Overflow); //If >= max_int(0x7fffffff),jump to Skip Label ++ ++ //Lable Convert ++ __ BIND(Convert); ++ __ fcvtsd(temp_float_reg, src); ++ __ fcvtdl_z(temp_float_reg1, temp_float_reg); ++ __ fcvtlw(temp_float_reg, temp_float_reg1); ++ __ fimovs(dst, temp_float_reg); ++ __ addw(dst, dst, 0); ++ __ beq(R0,Done); ++ ++ //Lable Skip ++ __ BIND(Overflow) ++ __ addw(dst, temp_reg, 0); ++ __ BIND(Done); ++ } ++ %} ++ ++ ins_pipe( pipe_slow ); ++%} ++ ++ ++ ++instruct convF2I_reg_slow( mRegI dst, regF src ) %{ ++ match(Set dst (ConvF2I src)); ++ ins_cost(250); ++ format %{ "convf2i $dst, $src @ convF2I_reg_slow" %} ++ ins_encode %{ ++ Register dreg = $dst$$Register; ++ FloatRegister fval = $src$$FloatRegister; ++ ++ __ saveTRegisters(); ++ __ fmovs(F16, fval); ++ __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::f2i), 1); ++ __ move(T12, V0); ++ __ restoreTRegisters(); ++ __ move(dreg, T12); ++ %} ++ ++ ins_pipe( pipe_slow ); ++%} ++ ++ ++instruct convF2L_reg_fast( mRegL dst, regF src ) %{ ++ match(Set dst (ConvF2L src)); ++ ins_cost(150); ++ format %{ "convf2l $dst, $src @ convF2L_reg_fast" %} ++ ins_encode %{ ++ Register dst = as_Register($dst$$reg); ++ FloatRegister src = $src$$FloatRegister; ++ if(UseSW8A) { ++ __ cmovdl_z(dst, src); ++ }else { ++ Label Convert,Overflow,Done; ++ FloatRegister temp_float_reg = F30; ++ FloatRegister temp_float_reg1 = F28; ++ ++ __ fcmpun(temp_float_reg, src, src); ++ __ fbne(temp_float_reg,Convert); ++ ++ __ or_ins(T12, R0, 1); ++ __ slll(T12, T12, 63); ++ ++ __ ifmovd(temp_float_reg, T12); ++ __ fcvtls(temp_float_reg1, temp_float_reg); ++ __ fcmple(temp_float_reg, src,temp_float_reg1); ++ __ fbne(temp_float_reg,Overflow); //if less than min_long(0x8000000000000000),jump to Skip Lable ++ ++ __ subl(T12,T12,1); ++ __ ifmovd(temp_float_reg, T12); ++ __ fcvtls(temp_float_reg1, temp_float_reg); ++ __ fcmple(temp_float_reg, temp_float_reg1,src); ++ __ fbne(temp_float_reg,Overflow); // if >=max_long(0x7fffffffffffffff),jump to Skip Lable ++ ++ //Lable Convert ++ __ BIND(Convert); ++ __ fcvtsd(temp_float_reg, src); ++ __ fcvtdl_z(temp_float_reg1, temp_float_reg); ++ __ fimovd(dst, temp_float_reg1); ++ __ beq(R0,Done); ++ ++ //Lable Skip ++ __ BIND(Overflow); ++ __ move(dst,T12); ++ __ BIND(Done); ++ } ++ %} ++ ++ ins_pipe( pipe_slow ); ++%} ++ ++ ++instruct convF2L_reg_slow( mRegL dst, regF src ) %{ ++ match(Set dst (ConvF2L src)); ++ ins_cost(250); ++ format %{ "convf2l $dst, $src @ convF2L_reg_slow" %} ++ ins_encode %{ ++ Register dst = as_Register($dst$$reg); ++ FloatRegister fval = $src$$FloatRegister; ++ ++ __ saveTRegisters(); ++ __ fmovs(F16, fval); ++ __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::f2l), 1); ++ __ move(T12, V0); ++ __ restoreTRegisters(); ++ __ move(dst, T12); ++ %} ++ ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct convL2F_reg( regF dst, mRegL src ) %{ ++ match(Set dst (ConvL2F src)); ++ format %{ "convl2f $dst, $src @ convL2F_reg" %} ++ ins_encode %{ ++ FloatRegister dst = $dst$$FloatRegister; ++ Register src = as_Register($src$$reg); ++ if (UseSW8A){ ++ __ cmovls(dst, src); ++ } else { ++ __ ifmovd(F30, src); ++ __ fcvtls(dst, F30); ++ } ++ %} ++ ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct convI2F_reg( regF dst, mRegI src ) %{ ++ match(Set dst (ConvI2F src)); ++ format %{ "convi2f $dst, $src @ convI2F_reg" %} ++ ins_encode %{ ++ Register src = $src$$Register; ++ FloatRegister dst = $dst$$FloatRegister; ++ if (UseSW8A) { ++ __ cmovws(dst, src); ++ } else { ++ __ ifmovs(F30, src); ++ __ fcvtwl(F28, F30); ++ __ fcvtls(dst, F28); ++ } ++ ++ %} ++ ++ ins_pipe( fpu_regF_regF ); ++%} ++ ++instruct cmpLTMask_immI0( mRegI dst, mRegI p, immI0 zero ) %{ ++ match(Set dst (CmpLTMask p zero)); ++ ins_cost(100); ++ ++ format %{ "sra $dst, $p, 31 @ cmpLTMask_immI0" %} ++ ins_encode %{ ++ Register src = $p$$Register; ++ Register dst = $dst$$Register; ++ if(UseSW8A) { ++ __ sraw(src, 31, dst); ++ } else { ++ __ sral(dst, src, 31&0x1f); ++ } ++ %} ++ ins_pipe( pipe_slow ); ++%} ++ ++ ++instruct cmpLTMask( mRegI dst, mRegI p, mRegI q ) %{ ++ match(Set dst (CmpLTMask p q)); ++ ins_cost(400); ++ ++ format %{ "cmpLTMask $dst, $p, $q @ cmpLTMask" %} ++ ins_encode %{ ++ Register p = $p$$Register; ++ Register q = $q$$Register; ++ Register dst = $dst$$Register; ++ ++ __ cmplt(dst, p, q); ++ __ subl(dst, R0, dst); ++ %} ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct convP2B(mRegI dst, mRegP src) %{ ++ match(Set dst (Conv2B src)); ++ ++ ins_cost(100); ++ format %{ "convP2B $dst, $src @convP2B" %} ++ ins_encode %{ ++ Register dst = as_Register($dst$$reg); ++ Register src = as_Register($src$$reg); ++ ++ __ selne(src, 1, src, dst); ++ %} ++ ++ ins_pipe( ialu_regL_regL ); ++%} ++ ++ ++instruct convI2D_reg_reg(regD dst, mRegI src) %{ ++ match(Set dst (ConvI2D src)); ++ format %{ "conI2D $dst, $src @convI2D_reg" %} ++ ins_encode %{ ++ Register src = $src$$Register; ++ FloatRegister dst = $dst$$FloatRegister; ++ if (UseSW8A){ ++ __ cmovwd(dst, src); ++ } else { ++ __ ifmovd(F30, src); ++ __ fcvtld(dst, F30); ++ } ++ %} ++ ins_pipe( fpu_regF_regF ); ++%} ++ ++instruct convF2D_reg_reg(regD dst, regF src) %{ ++ match(Set dst (ConvF2D src)); ++ format %{ "convF2D $dst, $src\t# @convF2D_reg_reg" %} ++ ins_encode %{ ++ FloatRegister dst = $dst$$FloatRegister; ++ FloatRegister src = $src$$FloatRegister; ++ ++ __ fcvtD2S(dst, src); ++ %} ++ ins_pipe( fpu_regF_regF ); ++%} ++ ++instruct convD2F_reg_reg(regF dst, regD src) %{ ++ match(Set dst (ConvD2F src)); ++ format %{ "convD2F $dst, $src\t# @convD2F_reg_reg" %} ++ ins_encode %{ ++ FloatRegister dst = $dst$$FloatRegister; ++ FloatRegister src = $src$$FloatRegister; ++ ++ __ fcvtS2D(dst, src); ++ %} ++ ins_pipe( fpu_regF_regF ); ++%} ++ ++ ++// Convert a double to an int. If the double is a NAN, stuff a zero in instead. ++instruct convD2I_reg_reg_fast( mRegI dst, regD src ) %{ ++ match(Set dst (ConvD2I src)); ++ ++ ins_cost(150); ++ format %{ "convD2I $dst, $src\t# @ convD2I_reg_reg_fast" %} ++ ++ ins_encode %{ ++ FloatRegister src = $src$$FloatRegister; ++ Register dst = $dst$$Register; ++ if (UseSW8A) { ++ __ cmovdw_z(dst, src); ++ } else { ++ FloatRegister temp_float_reg = F30; ++ FloatRegister temp_float_reg1 = F28; ++ FloatRegister tmp = F27; ++ ++ assert( (temp_float_reg1 != src), "can not use F28"); ++ assert( (temp_float_reg != src), "can not use F28"); ++ Label Convert,Overflow,Done; ++ __ fcmpun(temp_float_reg, src, src); ++ __ fbne (temp_float_reg, Convert); //If Unorder,Jump to Convert Label ++ ++ __ bis (T12, R0, 1); ++ __ slll(T12, T12, 31); ++ __ ifmovs(temp_float_reg, T12); ++ __ fcvtwl(temp_float_reg1, temp_float_reg); ++ __ fcvtld(temp_float_reg, temp_float_reg1); ++ __ fcmple(temp_float_reg1, src, temp_float_reg); ++ __ fbne (temp_float_reg1, Overflow); //If less than min_int(0x80000000),jump to Skip Label ++ ++ __ subw(T12, T12, 0x1); ++ __ ifmovs(temp_float_reg, T12); ++ __ fcvtwl(temp_float_reg1, temp_float_reg); ++ __ fcvtld(temp_float_reg, temp_float_reg1); ++ __ fcmple(temp_float_reg1, temp_float_reg, src); ++ __ fbne (temp_float_reg1, Overflow); //If >= max_int(0x7fffffff),jump to Skip Label ++ ++ //Label Convert ++ __ BIND(Convert); ++ __ fcvtdl_z(temp_float_reg, src);//lx20121018,result is rounded toward zero ++ __ fcvtlw(tmp, temp_float_reg); ++ __ fimovs(dst, tmp); ++ __ addw(dst, dst, 0); ++ __ beq (R0, Done); ++ //Labe Overflow ++ __ BIND(Overflow); ++ __ addw(dst, T12, 0); ++ __ BIND(Done); ++ } ++ %} ++ ins_pipe( pipe_slow ); ++%} ++ ++ ++instruct convD2I_reg_reg_slow( mRegI dst, regD src ) %{ ++ match(Set dst (ConvD2I src)); ++ ++ ins_cost(250); ++ format %{ "convD2I $dst, $src\t# @ convD2I_reg_reg_slow" %} ++ ++ ins_encode %{ ++ FloatRegister src = $src$$FloatRegister; ++ Register dst = $dst$$Register; ++ ++ __ saveTRegisters(); ++ __ fmovd(F16, src); ++ __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::d2i), 1); ++ __ move(T12, V0); ++ __ restoreTRegisters(); ++ __ move(dst, T12); ++ %} ++ ins_pipe( pipe_slow ); ++%} ++ ++// Convert oop pointer into compressed form ++instruct encodeHeapOop(mRegN dst, mRegP src) %{ ++ predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull); ++ match(Set dst (EncodeP src)); ++ format %{ "encode_heap_oop $dst,$src" %} ++ ins_encode %{ ++ Register src = $src$$Register; ++ Register dst = $dst$$Register; ++ ++ __ encode_heap_oop(dst, src); ++ %} ++ ins_pipe( ialu_regL_regL ); ++%} ++ ++instruct encodeHeapOop_not_null(mRegN dst, mRegP src) %{ ++ predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull); ++ match(Set dst (EncodeP src)); ++ format %{ "encode_heap_oop_not_null $dst,$src @ encodeHeapOop_not_null" %} ++ ins_encode %{ ++ __ encode_heap_oop_not_null($dst$$Register, $src$$Register); ++ %} ++ ins_pipe( ialu_regL_regL ); ++%} ++ ++instruct decodeHeapOop(mRegP dst, mRegN src) %{ ++ predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull && ++ n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant); ++ match(Set dst (DecodeN src)); ++ format %{ "decode_heap_oop $dst,$src @ decodeHeapOop" %} ++ ins_encode %{ ++ Register s = $src$$Register; ++ Register d = $dst$$Register; ++ ++ __ decode_heap_oop(d, s); ++ %} ++ ins_pipe( ialu_regL_regL ); ++%} ++ ++instruct decodeHeapOop_not_null(mRegP dst, mRegN src) %{ ++ predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull || ++ n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant); ++ match(Set dst (DecodeN src)); ++ format %{ "decode_heap_oop_not_null $dst,$src @ decodeHeapOop_not_null" %} ++ ins_encode %{ ++ Register s = $src$$Register; ++ Register d = $dst$$Register; ++ if (s != d) { ++ __ decode_heap_oop_not_null(d, s); ++ } else { ++ __ decode_heap_oop_not_null(d); ++ } ++ %} ++ ins_pipe( ialu_regL_regL ); ++%} ++ ++instruct encodeKlass_not_null(mRegN dst, mRegP src) %{ ++ match(Set dst (EncodePKlass src)); ++ format %{ "encode_heap_oop_not_null $dst,$src @ encodeKlass_not_null" %} ++ ins_encode %{ ++ __ encode_klass_not_null($dst$$Register, $src$$Register); ++ %} ++ ins_pipe( ialu_regL_regL ); ++%} ++ ++instruct decodeKlass_not_null(mRegP dst, mRegN src) %{ ++ match(Set dst (DecodeNKlass src)); ++ format %{ "decode_heap_klass_not_null $dst,$src" %} ++ ins_encode %{ ++ Register s = $src$$Register; ++ Register d = $dst$$Register; ++ if (s != d) { ++ __ decode_klass_not_null(d, s); ++ } else { ++ __ decode_klass_not_null(d); ++ } ++ %} ++ ins_pipe( ialu_regL_regL ); ++%} ++ ++ ++instruct tlsLoadP(mRegP dst) %{ ++ match(Set dst (ThreadLocal)); ++ ++ ins_cost(0); ++ format %{ " get_thread in $dst #@tlsLoadP" %} ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ __ move(dst, S2thread); ++ %} ++ ++ ins_pipe( ialu_loadI ); ++%} ++ ++ ++instruct checkCastPP( mRegP dst ) %{ ++ match(Set dst (CheckCastPP dst)); ++ ++ format %{ "#checkcastPP of $dst (empty encoding) #@chekCastPP" %} ++ ins_encode( /*empty encoding*/ ); ++ ins_pipe( empty ); ++%} ++ ++instruct castPP(mRegP dst) ++%{ ++ match(Set dst (CastPP dst)); ++ ++ size(0); ++ format %{ "# castPP of $dst" %} ++ ins_encode(/* empty encoding */); ++ ins_pipe(empty); ++%} ++ ++instruct castII( mRegI dst ) %{ ++ match(Set dst (CastII dst)); ++ format %{ "#castII of $dst empty encoding" %} ++ ins_encode( /*empty encoding*/ ); ++ ins_cost(0); ++ ins_pipe( empty ); ++%} ++ ++// Return Instruction ++// Remove the return address & jump to it. ++instruct Ret() %{ ++ match(Return); ++ format %{ "RET #@Ret" %} ++ ++ ins_encode %{ ++ __ ret(); ++ %} ++ ++ ins_pipe( pipe_jump ); ++%} ++ ++/* ++// Jr seems too slow, so this rule shouldn't be imported. ++instruct jumpXtnd(mRegL switch_val) %{ ++ match(Jump switch_val); ++ ++ ins_cost(350); ++ ++ format %{ "load T12 <-- [$constanttablebase, $switch_val, $constantoffset] @ jumpXtnd\n\t" ++ "jr T12\n\t" %} ++ ins_encode %{ ++ Register table_base = $constanttablebase; ++ int con_offset = $constantoffset; ++ Register switch_reg = $switch_val$$Register; ++ ++ if (Assembler::is_simm16(con_offset)) { ++ __ addl(T12, table_base, switch_reg); ++ __ ldl(T12, T12, con_offset); ++ } else { ++ __ move(T12, con_offset); ++ __ addl(AT, table_base, switch_reg); ++ __ addl(AT, T12, AT); ++ __ ldl(T12, AT, 0); ++ } ++ ++ __ jmp(T12); ++ ++ %} ++ ins_pipe(pipe_jump); ++%} ++*/ ++ ++// Jump Direct - Label defines a relative address from JMP ++instruct jmpDir(label labl) %{ ++ match(Goto); ++ effect(USE labl); ++ ins_cost(300); ++ format %{ "JMP $labl #@jmpDir" %} ++ ins_encode %{ ++ Label &L = *($labl$$label); ++ if(&L) ++ __ beq(R0, L); ++ else ++ __ beq(R0, int(0)); ++ %} ++ ins_pipe( pipe_jump ); ++ ins_pc_relative(1); ++%} ++ ++// Tail Jump; remove the return address; jump to target. ++// TailCall above leaves the return address around. ++// TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2). ++// ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a ++// "restore" before this instruction (in Epilogue), we need to materialize it ++// in %i0. ++ ++instruct tailjmpInd(mRegP jump_target,mRegP ex_oop) %{ ++ match( TailJump jump_target ex_oop ); ++ ins_cost(200); ++ format %{ "Jmp $jump_target ; ex_oop = $ex_oop #@tailjmpInd" %} ++ ins_encode %{ ++ Register target = $jump_target$$Register; ++ ++ // V0, T4 are indicated in: ++ // [stubGenerator_sw64.cpp] generate_forward_exception() ++ // [runtime_sw64.cpp] OptoRuntime::generate_exception_blob() ++ // ++ Register oop = $ex_oop$$Register; ++ Register exception_oop = V0; ++ Register exception_pc = T4; ++ ++ __ move(exception_pc, RA); ++ __ move(exception_oop, oop); ++ ++ __ jmp(target); ++ %} ++ ins_pipe( pipe_jump ); ++%} ++ ++// ============================================================================ ++// Procedure Call/Return Instructions ++// Call Java Static Instruction ++// Note: If this code changes, the corresponding ret_addr_offset() and ++// compute_padding() functions will have to be adjusted. ++instruct CallStaticJavaDirect(method meth) %{ ++ match(CallStaticJava); ++ effect(USE meth); ++ ++ ins_cost(300); ++ format %{ "CALL,static #@CallStaticJavaDirect " %} ++ ins_encode( Java_Static_Call( meth ) ); ++ ins_pipe( pipe_slow ); ++ ins_pc_relative(1); ++%} ++ ++// Call Java Dynamic Instruction ++// Note: If this code changes, the corresponding ret_addr_offset() and ++// compute_padding() functions will have to be adjusted. ++instruct CallDynamicJavaDirect(method meth) %{ ++ match(CallDynamicJava); ++ effect(USE meth); ++ ++ ins_cost(300); ++ format %{"MOV IC_Klass, #Universe::non_oop_word()\n\t" ++ "CallDynamic @ CallDynamicJavaDirect" %} ++ ins_encode( Java_Dynamic_Call( meth ) ); ++ ins_pipe( pipe_slow ); ++ ins_pc_relative(1); ++%} ++ ++instruct CallLeafNoFPDirect(method meth) %{ ++ match(CallLeafNoFP); ++ effect(USE meth); ++ ++ ins_cost(300); ++ format %{ "CALL_LEAF_NOFP,runtime " %} ++ ins_encode(Java_To_Runtime(meth)); ++ ins_pipe( pipe_slow ); ++ ins_pc_relative(1); ++ ins_alignment(16); ++%} ++ ++// Prefetch instructions. ++ ++instruct prefetchrNTA( memory mem ) %{ ++ match(PrefetchRead mem); ++ ins_cost(125); ++ ++ format %{ "pref $mem\t# Prefetch into non-temporal cache for read @ prefetchrNTA" %} ++ ins_encode %{ ++ int base = $mem$$base; ++ int disp = $mem$$disp; ++ ++ if( Assembler::is_simm16(disp) ) { ++ __ add_simm16(AT, as_Register(base), disp); ++ } else { ++ __ move(T9, disp); ++ __ addl(AT, as_Register(base), T9); ++ } ++ __ fillcs(AT, 0); ++ ++ %} ++ ins_pipe(pipe_slow); ++%} ++ ++instruct prefetchwNTA( memory mem ) %{ ++ match(PrefetchWrite mem); ++ ins_cost(125); ++ format %{ "pref $mem\t# Prefetch to non-temporal cache for write @ prefetchwNTA" %} ++ ins_encode %{ ++ int base = $mem$$base; ++ int disp = $mem$$disp; ++ ++ if( Assembler::is_simm16(disp) ) { ++ __ add_simm16(AT, as_Register(base), disp); ++ } else { ++ __ move(T9, disp); ++ __ addl(AT, as_Register(base), T9); ++ } ++ __ fillde(AT, 0); ++ ++ %} ++ ins_pipe(pipe_slow); ++%} ++ ++// Prefetch instructions for allocation. ++ ++instruct prefetchAllocNTA( memory mem ) %{ ++ match(PrefetchAllocation mem); ++ ins_cost(125); ++ format %{ "pref $mem\t# Prefetch allocation @ prefetchAllocNTA" %} ++ ins_encode %{ ++ int base = $mem$$base; ++ int disp = $mem$$disp; ++ ++ Register dst = R0; ++ ++ if( Assembler::is_simm16(disp) ) { ++ __ fillde(as_Register(base), disp); ++ } else { ++ __ move(T9, disp); ++ __ addl(AT, as_Register(base), T9); ++ __ fillde(AT, 0); ++ } ++// } ++ %} ++ ins_pipe(pipe_slow); ++%} ++ ++ ++// Call runtime without safepoint ++instruct CallLeafDirect(method meth) %{ ++ match(CallLeaf); ++ effect(USE meth); ++ ++ ins_cost(300); ++ format %{ "CALL_LEAF,runtime #@CallLeafDirect " %} ++ ins_encode(Java_To_Runtime(meth)); ++ ins_pipe( pipe_slow ); ++ ins_pc_relative(1); ++ ins_alignment(16); ++%} ++ ++// Load Char (16bit unsigned) ++instruct loadUS(mRegI dst, memory mem) %{ ++ match(Set dst (LoadUS mem)); ++ ++ ins_cost(125); ++ format %{ "loadUS $dst,$mem @ loadC" %} ++ ins_encode(load_C_enc(dst, mem)); ++ ins_pipe( ialu_loadI ); ++%} ++ ++instruct loadUS_convI2L(mRegL dst, memory mem) %{ ++ match(Set dst (ConvI2L (LoadUS mem))); ++ ++ ins_cost(125); ++ format %{ "loadUS $dst,$mem @ loadUS_convI2L" %} ++ ins_encode(load_C_enc(dst, mem)); ++ ins_pipe( ialu_loadI ); ++%} ++ ++// Store Char (16bit unsigned) ++instruct storeC(memory mem, mRegI src) %{ ++ match(Set mem (StoreC mem src)); ++ ++ ins_cost(125); ++ format %{ "storeC $src, $mem @ storeC" %} ++ ins_encode(store_C_reg_enc(mem, src)); ++ ins_pipe( ialu_loadI ); ++%} ++ ++instruct storeC0(memory mem, immI0 zero) %{ ++ match(Set mem (StoreC mem zero)); ++ ++ ins_cost(125); ++ format %{ "storeC $zero, $mem @ storeC0" %} ++ ins_encode(store_C0_enc(mem)); ++ ins_pipe( ialu_loadI ); ++%} ++ ++ ++instruct loadConF0(regF dst, immF0 zero) %{ ++ match(Set dst zero); ++ ins_cost(100); ++ ++ format %{ "mov $dst, zero @ loadConF0\n"%} ++ ins_encode %{ ++ FloatRegister dst = $dst$$FloatRegister; ++ ++ __ ifmovs(dst, R0); ++ %} ++ ins_pipe( fpu_loadF ); ++%} ++ ++ ++instruct loadConF(regF dst, immF src) %{ ++ match(Set dst src); ++ ins_cost(125); ++ ++ format %{ "flds $dst, $constantoffset[$constanttablebase] # load FLOAT $src from table @ loadConF" %} ++ ins_encode %{ ++ int con_offset = $constantoffset($src); ++ ++ if (Assembler::is_simm16(con_offset)) { ++ __ flds($dst$$FloatRegister, $constanttablebase, con_offset); ++ } else { ++ __ set64(AT, con_offset); ++ __ addl(AT, $constanttablebase, AT); ++ __ flds($dst$$FloatRegister, AT, 0); ++ } ++ %} ++ ins_pipe( fpu_loadF ); ++%} ++ ++ ++instruct loadConD0(regD dst, immD0 zero) %{ ++ match(Set dst zero); ++ ins_cost(100); ++ ++ format %{ "mov $dst, zero @ loadConD0"%} ++ ins_encode %{ ++ FloatRegister dst = as_FloatRegister($dst$$reg); ++ ++ __ ifmovd(dst, R0); ++ %} ++ ins_pipe( fpu_loadF ); ++%} ++ ++instruct loadConD(regD dst, immD src) %{ ++ match(Set dst src); ++ ins_cost(125); ++ ++ format %{ "fldd $dst, $constantoffset[$constanttablebase] # load DOUBLE $src from table @ loadConD" %} ++ ins_encode %{ ++ int con_offset = $constantoffset($src); ++ ++ if (Assembler::is_simm16(con_offset)) { ++ __ fldd($dst$$FloatRegister, $constanttablebase, con_offset); ++ } else { ++ __ set64(AT, con_offset); ++ __ addl(AT, $constanttablebase, AT); ++ __ fldd($dst$$FloatRegister, AT, 0); ++ } ++ %} ++ ins_pipe( fpu_loadF ); ++%} ++ ++// Store register Float value (it is faster than store from FPU register) ++instruct storeF_reg( memory mem, regF src) %{ ++ match(Set mem (StoreF mem src)); ++ ++ ins_cost(50); ++ format %{ "store $mem, $src\t# store float @ storeF_reg" %} ++ ins_encode(store_F_reg_enc(mem, src)); ++ ins_pipe( fpu_storeF ); ++%} ++ ++instruct storeF_imm0( memory mem, immF0 zero) %{ ++ match(Set mem (StoreF mem zero)); ++ ++ ins_cost(40); ++ format %{ "store $mem, zero\t# store float @ storeF_imm0" %} ++ ins_encode %{ ++ int base = $mem$$base; ++ int disp = $mem$$disp; ++ ++ if( Assembler::is_simm16(disp) ) { ++ __ fsts(F31, as_Register(base), disp); ++ } else { ++ __ move(T12, disp); ++ __ addl(AT, as_Register(base), T12); ++ __ fsts(F31, AT, 0); ++ } ++ %} ++ ins_pipe( ialu_storeI ); ++%} ++ ++// Load Double ++instruct loadD(regD dst, memory mem) %{ ++ match(Set dst (LoadD mem)); ++ ++ ins_cost(150); ++ format %{ "loadD $dst, $mem #@loadD" %} ++ ins_encode(load_D_enc(dst, mem)); ++ ins_pipe( ialu_loadI ); ++%} ++ ++// Load Double - UNaligned ++instruct loadD_unaligned(regD dst, memory mem ) %{ ++ match(Set dst (LoadD_unaligned mem)); ++ ins_cost(250); ++ format %{ "loadD_unaligned $dst, $mem #@loadD_unaligned" %} ++ ins_encode(load_D_enc(dst, mem)); ++ ins_pipe( ialu_loadI ); ++%} ++ ++instruct storeD_reg( memory mem, regD src) %{ ++ match(Set mem (StoreD mem src)); ++ ++ ins_cost(50); ++ format %{ "store $mem, $src\t# store float @ storeD_reg" %} ++ ins_encode(store_D_reg_enc(mem, src)); ++ ins_pipe( fpu_storeF ); ++%} ++ ++instruct storeD_imm0( memory mem, immD0 zero) %{ ++ match(Set mem (StoreD mem zero)); ++ ++ ins_cost(40); ++ format %{ "store $mem, zero\t# store float @ storeD_imm0" %} ++ ins_encode %{ ++ int base = $mem$$base; ++ int disp = $mem$$disp; ++ ++ if( Assembler::is_simm16(disp) ) { ++ __ fstd(F31, as_Register(base), disp); ++ } else { ++ __ move(T12, disp); ++ __ addl(AT, as_Register(base), T12); ++ __ fstd(F31, AT, 0); ++ } ++ %} ++ ins_pipe( ialu_storeI ); ++%} ++ ++instruct loadSSI(mRegI dst, stackSlotI src) ++%{ ++ match(Set dst src); ++ ++ ins_cost(125); ++ format %{ "ldw $dst, $src\t# int stk @ loadSSI" %} ++ ins_encode %{ ++ guarantee( Assembler::is_simm16($src$$disp), "disp too long (loadSSI) !"); ++ __ ldw($dst$$Register, SP, $src$$disp); ++ %} ++ ins_pipe(ialu_loadI); ++%} ++ ++instruct storeSSI(stackSlotI dst, mRegI src) ++%{ ++ match(Set dst src); ++ ++ ins_cost(100); ++ format %{ "stw $dst, $src\t# int stk @ storeSSI" %} ++ ins_encode %{ ++ guarantee( Assembler::is_simm16($dst$$disp), "disp too long (storeSSI) !"); ++ __ stw($src$$Register, SP, $dst$$disp); ++ %} ++ ins_pipe(ialu_storeI); ++%} ++ ++instruct loadSSL(mRegL dst, stackSlotL src) ++%{ ++ match(Set dst src); ++ ++ ins_cost(125); ++ format %{ "ld $dst, $src\t# long stk @ loadSSL" %} ++ ins_encode %{ ++ guarantee( Assembler::is_simm16($src$$disp), "disp too long (loadSSL) !"); ++ __ ldl($dst$$Register, SP, $src$$disp); ++ %} ++ ins_pipe(ialu_loadI); ++%} ++ ++instruct storeSSL(stackSlotL dst, mRegL src) ++%{ ++ match(Set dst src); ++ ++ ins_cost(100); ++ format %{ "stl $dst, $src\t# long stk @ storeSSL" %} ++ ins_encode %{ ++ guarantee( Assembler::is_simm16($dst$$disp), "disp too long (storeSSL) !"); ++ __ stl($src$$Register, SP, $dst$$disp); ++ %} ++ ins_pipe(ialu_storeI); ++%} ++ ++instruct loadSSP(mRegP dst, stackSlotP src) ++%{ ++ match(Set dst src); ++ ++ ins_cost(125); ++ format %{ "ld $dst, $src\t# ptr stk @ loadSSP" %} ++ ins_encode %{ ++ guarantee( Assembler::is_simm16($src$$disp), "disp too long (loadSSP) !"); ++ __ ldl($dst$$Register, SP, $src$$disp); ++ %} ++ ins_pipe(ialu_loadI); ++%} ++ ++instruct storeSSP(stackSlotP dst, mRegP src) ++%{ ++ match(Set dst src); ++ ++ ins_cost(100); ++ format %{ "stl $dst, $src\t# ptr stk @ storeSSP" %} ++ ins_encode %{ ++ guarantee( Assembler::is_simm16($dst$$disp), "disp too long (storeSSP) !"); ++ __ stl($src$$Register, SP, $dst$$disp); ++ %} ++ ins_pipe(ialu_storeI); ++%} ++ ++instruct loadSSF(regF dst, stackSlotF src) ++%{ ++ match(Set dst src); ++ ++ ins_cost(125); ++ format %{ "flds $dst, $src\t# float stk @ loadSSF" %} ++ ins_encode %{ ++ guarantee( Assembler::is_simm16($src$$disp), "disp too long (loadSSF) !"); ++ __ flds($dst$$FloatRegister, SP, $src$$disp); ++ %} ++ ins_pipe(ialu_loadI); ++%} ++ ++instruct storeSSF(stackSlotF dst, regF src) ++%{ ++ match(Set dst src); ++ ++ ins_cost(100); ++ format %{ "fsts $dst, $src\t# float stk @ storeSSF" %} ++ ins_encode %{ ++ guarantee( Assembler::is_simm16($dst$$disp), "disp too long (storeSSF) !"); ++ __ fsts($src$$FloatRegister, SP, $dst$$disp); ++ %} ++ ins_pipe(fpu_storeF); ++%} ++ ++// Use the same format since predicate() can not be used here. ++instruct loadSSD(regD dst, stackSlotD src) ++%{ ++ match(Set dst src); ++ ++ ins_cost(125); ++ format %{ "fldd $dst, $src\t# double stk @ loadSSD" %} ++ ins_encode %{ ++ guarantee( Assembler::is_simm16($src$$disp), "disp too long (loadSSD) !"); ++ __ fldd($dst$$FloatRegister, SP, $src$$disp); ++ %} ++ ins_pipe(ialu_loadI); ++%} ++ ++instruct storeSSD(stackSlotD dst, regD src) ++%{ ++ match(Set dst src); ++ ++ ins_cost(100); ++ format %{ "fstd $dst, $src\t# double stk @ storeSSD" %} ++ ins_encode %{ ++ guarantee( Assembler::is_simm16($dst$$disp), "disp too long (storeSSD) !"); ++ __ fstd($src$$FloatRegister, SP, $dst$$disp); ++ %} ++ ins_pipe(fpu_storeF); ++%} ++ ++instruct cmpFastLock( FlagsReg cr, mRegP object, s0_RegP box, mRegI tmp, mRegP scr, t10RegL tmpT10) %{ ++ match( Set cr (FastLock object box) ); ++ effect( TEMP tmp, TEMP scr, TEMP tmpT10, USE_KILL box ); ++ ins_cost(300); ++ format %{ "FASTLOCK $cr $object, $box, $tmp #@ cmpFastLock" %} ++ ins_encode %{ ++ __ fast_lock($object$$Register, $box$$Register, $tmp$$Register, $scr$$Register); ++ %} ++ ++ ins_pipe( pipe_slow ); ++ ins_pc_relative(1); ++%} ++ ++instruct cmpFastUnlock( FlagsReg cr, mRegP object, s0_RegP box, mRegP tmp, t10RegL tmpT10) %{ ++ match( Set cr (FastUnlock object box) ); ++ effect( TEMP tmp, TEMP tmpT10, USE_KILL box ); ++ ins_cost(300); ++ //size(144); //ZHJ20170905 ++ format %{ "FASTUNLOCK $object, $box, $tmp #@cmpFastUnlock" %} ++ ins_encode %{ ++ __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register); ++ %} ++ ++ ins_pipe( pipe_slow ); ++ ins_pc_relative(1); ++%} ++ ++/* no necessary // Store CMS card-mark ++instruct storeImmCM(memory mem, mRegI src) %{ ++ match(Set mem (StoreCM mem src)); ++ ++ ins_cost(200); ++ format %{ "MOV8 $mem,$src\t! CMS card-mark" %} ++ ins_encode(store_B_reg_enc_sync(mem, src)); ++ ins_pipe( ialu_storeI ); ++%} ++*/ ++ ++instruct storeimmCM0_ordered(memory mem, immI0 src) %{ ++ match(Set mem (StoreCM mem src)); ++ ins_cost(200); ++ format %{ "MOV8 $mem,$src\t! CMS card-mark imm0 ordered" %} ++ ins_encode(store_B_immI0_enc_sync(mem, src)); ++ ins_pipe( ialu_storeI ); ++%} ++ ++instruct storeImm0CM(memory mem, immI0 src) %{ ++ match(Set mem (StoreCM mem src)); ++ predicate(unnecessary_storestore(n)); ++ ins_cost(100); ++ format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %} ++ ins_encode(store_B_immI0(mem, src)); ++ ins_pipe( ialu_storeI ); ++%} ++ ++// Die now ++instruct ShouldNotReachHere( ) ++%{ ++ match(Halt); ++ ins_cost(300); ++ ++ // Use the following format syntax ++ format %{ "ILLTRAP ;#@ShouldNotReachHere" %} ++ ins_encode %{ ++ // Here we should emit illtrap ! ++ ++ __ stop("in ShoudNotReachHere"); ++ ++ %} ++ ins_pipe( pipe_jump ); ++%} ++ ++instruct leaP8Narrow(mRegP dst, indOffset8Narrow mem) ++%{ ++ predicate(Universe::narrow_oop_shift() == 0); ++ match(Set dst mem); ++ ++ ins_cost(110); ++ format %{ "leaq $dst, $mem\t# ptr off8narrow @ leaP8Narrow" %} ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ Register base = as_Register($mem$$base); ++ int disp = $mem$$disp; ++ ++ __ add_simm16(dst, base, disp); ++ %} ++ ins_pipe( ialu_regI_imm16 ); ++%} ++ ++// Jump Direct Conditional - Label defines a relative address from Jcc+1 ++instruct jmpLoopEnd(cmpOp cop, mRegI src1, mRegI src2, label labl) %{ ++ match(CountedLoopEnd cop (CmpI src1 src2)); ++ effect(USE labl); ++ ++ ins_cost(300); ++ format %{ "J$cop $src1, $src2, $labl\t# Loop end @ jmpLoopEnd" %} ++ ins_encode %{ ++ Register op1 = $src1$$Register; ++ Register op2 = $src2$$Register; ++ Label &L = *($labl$$label); ++ int flag = $cop$$cmpcode; ++ ++ switch(flag) ++ { ++ case 0x01: //equal ++ if (&L) ++ __ beq(op1, op2, L); ++ else ++ __ beq(op1, op2, (int)0); ++ break; ++ case 0x02: //not_equal ++ if (&L) ++ __ bne(op1, op2, L); ++ else ++ __ bne(op1, op2, (int)0); ++ break; ++ case 0x03: //above ++ __ cmplt(AT, op2, op1); ++ if(&L) ++ __ bne(AT, L); ++ else ++ __ bne(AT, (int)0); ++ break; ++ case 0x04: //above_equal ++ __ cmplt(AT, op1, op2); ++ if(&L) ++ __ beq(AT, L); ++ else ++ __ beq(AT, (int)0); ++ break; ++ case 0x05: //below ++ __ cmplt(AT, op1, op2); ++ if(&L) ++ __ bne(AT, L); ++ else ++ __ bne(AT, (int)0); ++ break; ++ case 0x06: //below_equal ++ __ cmplt(AT, op2, op1); ++ if(&L) ++ __ beq(AT, L); ++ else ++ __ beq(AT, (int)0); ++ break; ++ default: ++ Unimplemented(); ++ } ++ %} ++ ins_pipe( pipe_jump ); ++ ins_pc_relative(1); ++%} ++ ++ instruct jmpLoopEnd_reg_imm16(cmpOp cop, mRegI src1, immI16_sub src2, label labl) %{ ++ match(CountedLoopEnd cop (CmpI src1 src2)); ++ effect(USE labl); ++ ++ ins_cost(150); ++ format %{ "J$cop $src1, $src2, $labl\t# Loop end @ jmpLoopEnd_reg_imm_16_sub" %} ++ ins_encode %{ ++ Register op1 = $src1$$Register; ++ int val = $src2$$constant; ++ Label &L = *($labl$$label); ++ int flag = $cop$$cmpcode; ++ ++ __ add_simm16(AT, op1, -1 * val); ++ switch(flag) ++ { ++ case 0x01: //equal ++ if (&L) ++ __ beq(AT, L); ++ else ++ __ beq(AT, (int)0); ++ break; ++ case 0x02: //not_equal ++ if (&L) ++ __ bne(AT, L); ++ else ++ __ bne(AT, (int)0); ++ break; ++ case 0x03: //above ++ if(&L) ++ __ bgt(AT, L); ++ else ++ __ bgt(AT, (int)0); ++ break; ++ case 0x04: //above_equal ++ if(&L) ++ __ bge(AT, L); ++ else ++ __ bge(AT,(int)0); ++ break; ++ case 0x05: //below ++ if(&L) ++ __ blt(AT, L); ++ else ++ __ blt(AT, (int)0); ++ break; ++ case 0x06: //below_equal ++ if(&L) ++ __ ble(AT, L); ++ else ++ __ ble(AT, (int)0); ++ break; ++ default: ++ Unimplemented(); ++ } ++ %} ++ ins_pipe( pipe_jump ); ++ ins_pc_relative(1); ++%} ++ ++ instruct jmpLoopEnd_reg_immI(cmpOp cop, mRegI src1, immI src2, label labl) %{ ++ match(CountedLoopEnd cop (CmpI src1 src2)); ++ effect(USE labl); ++ ++ ins_cost(300); ++ format %{ "J$cop $src1, $src2, $labl\t# Loop end @ jmpLoopEnd_reg_immI" %} ++ ins_encode %{ ++ Register op1 = $src1$$Register; ++ Register op2 = AT; ++ Label &L = *($labl$$label); ++ int flag = $cop$$cmpcode; ++ ++ __ move(op2, $src2$$constant); ++ __ subl(AT, op1, AT); ++ switch(flag) ++ { ++ case 0x01: //equal ++ if (&L) ++ __ beq(AT, L); ++ else ++ __ beq(AT, (int)0); ++ break; ++ case 0x02: //not_equal ++ if (&L) ++ __ bne(AT, L); ++ else ++ __ bne(AT, (int)0); ++ break; ++ case 0x03: //above ++ if(&L) ++ __ bgt(AT, L); ++ else ++ __ bgt(AT, (int)0); ++ break; ++ case 0x04: //above_equal ++ if(&L) ++ __ bge(AT, L); ++ else ++ __ bge(AT,(int)0); ++ break; ++ case 0x05: //below ++ if(&L) ++ __ blt(AT, L); ++ else ++ __ blt(AT, (int)0); ++ break; ++ case 0x06: //below_equal ++ if(&L) ++ __ ble(AT, L); ++ else ++ __ ble(AT, (int)0); ++ break; ++ default: ++ Unimplemented(); ++ } ++ %} ++ ins_pipe( pipe_jump ); ++ ins_pc_relative(1); ++%} ++ ++ instruct jmpLoopEnd_reg_immI0(cmpOp cop, mRegI src1, immI0 src2, label labl) %{ ++ match( CountedLoopEnd cop (CmpI src1 src2) ); ++ effect(USE labl); ++ ins_cost(170); ++ format %{ "J$cop $src1, $src2, $labl\t# Loop end @ jmpLoopEnd_reg_imm0_short" %} ++ ++ ins_encode %{ ++ Register op1 = $src1$$Register; ++ Label &L = *($labl$$label); ++ int flag = $cop$$cmpcode; ++ ++ switch(flag) { ++ case 0x01: //equal ++ if (&L) ++ __ beq(op1, L); ++ else ++ __ beq(op1, (int)0); ++ break; ++ case 0x02: //not_equal ++ if (&L) ++ __ bne(op1, L); ++ else ++ __ bne(op1, (int)0); ++ break; ++ case 0x03: //greater ++ if(&L) ++ __ bgt(op1, L); ++ else ++ __ bgt(op1, (int)0); ++ break; ++ case 0x04: //greater_equal ++ if(&L) ++ __ bge(op1, L); ++ else ++ __ bge(op1, (int)0); ++ break; ++ case 0x05: //less ++ if(&L) ++ __ blt(op1, L); ++ else ++ __ blt(op1, (int)0); ++ break; ++ case 0x06: //less_equal ++ if(&L) ++ __ ble(op1, L); ++ else ++ __ ble(op1, (int)0); ++ break; ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pipe( pipe_jump ); ++ ins_pc_relative(1); ++//ZLONG ins_short_branch(1); ++%} ++ ++instruct jmpCon_flags(cmpOp cop, FlagsReg cr, label labl) %{ ++ match(If cop cr); ++ effect(USE labl); ++ ++ ins_cost(300); ++ format %{ "J$cop $labl #sw64 uses AT as eflag @jmpCon_flags" %} ++ ++ ins_encode %{ ++ Label &L = *($labl$$label); ++ switch($cop$$cmpcode) ++ { ++ case 0x01: //equal ++ if (&L) ++ __ bne(AT, L); ++ else ++ __ bne(AT, (int)0); ++ break; ++ case 0x02: //not equal ++ if (&L) ++ __ beq(AT, L); ++ else ++ __ beq(AT, (int)0); ++ break; ++ default: ++ Unimplemented(); ++ } ++ %} ++ ++ ins_pipe( pipe_jump ); ++ ins_pc_relative(1); ++%} ++ ++ ++// ============================================================================ ++// The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass ++// array for an instance of the superklass. Set a hidden internal cache on a ++// hit (cache is checked with exposed code in gen_subtype_check()). Return ++// NZ for a miss or zero for a hit. The encoding ALSO sets flags. ++instruct partialSubtypeCheck( mRegP result, no_T11_mRegP sub, no_T11_mRegP super, mT11RegI tmp ) %{ ++ match(Set result (PartialSubtypeCheck sub super)); ++ effect(KILL tmp); ++ ins_cost(1100); // slightly larger than the next version ++ format %{ "partialSubtypeCheck result=$result, sub=$sub, super=$super, tmp=$tmp " %} ++ ++ ins_encode( enc_PartialSubtypeCheck(result, sub, super, tmp) ); ++ ins_pipe( pipe_slow ); ++%} ++ ++// Conditional-store of an int value. ++// ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel. ++instruct storeIConditional( indirect mem, mRegI oldval, mRegI newval, FlagsReg cr ) %{ ++ match(Set cr (StoreIConditional mem (Binary oldval newval))); ++// effect(KILL oldval); ++ format %{ "CMPXCHG $newval, $mem, $oldval \t# @storeIConditional" %} ++ ++ ins_encode %{ ++ Register oldval = $oldval$$Register; ++ Register newval = $newval$$Register; ++ Address addr(as_Register($mem$$base), $mem$$disp); ++ Label again, nequal; ++ ++ int index = $mem$$index; ++ int disp = $mem$$disp; ++ SizedScope sc(&_masm, 40); ++ guarantee(disp == 0, "impossible encoding storeIConditional"); ++ if (UseSW8A) { ++ if (UseCAS) { ++ __ move(GP, newval); ++ __ casw(oldval, addr.base(), GP); ++ __ cmpeq(AT, GP, oldval); ++ } else { ++ __ BIND(again); ++ __ lldw(GP, addr.base(), addr.disp()); ++ __ cmpeq(AT, GP, oldval); ++ __ beq(AT, nequal); ++ __ move(AT, newval); ++ __ lstw(AT, addr.base(), addr.disp()); ++ __ beq(AT, again); ++ __ BIND(nequal); ++ } ++ } else { ++ __ BIND(again); ++ __ lldw(AT, addr.base(), addr.disp()); ++ __ cmpeq(GP, AT, oldval); ++ __ wr_f(GP); ++ __ move(AT, newval); ++ __ align(8); ++ __ lstw(AT, addr.base(), addr.disp()); ++ __ rd_f(AT); ++ __ beq(GP, nequal); ++ __ beq(AT, again); ++ __ BIND(nequal); ++ } ++%} ++ ins_pipe( long_memory_op ); ++%} ++ ++// LoadP-locked same as a regular LoadP when used with compare-swap ++instruct loadPLocked(mRegP dst, memory mem) ++%{ ++ match(Set dst (LoadPLocked mem)); ++ ++ ins_cost(125); ++ format %{ "ld $dst, $mem #@loadPLocked" %} ++ ins_encode (load_P_enc(dst, mem)); ++ ins_pipe( ialu_loadI ); ++%} ++ ++// Conditional-store of a long value. ++// ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG. ++instruct storeLConditional(indirect mem, t2RegL oldval, mRegL newval, FlagsReg cr ) %{ ++ match(Set cr (StoreLConditional mem (Binary oldval newval))); ++ effect(KILL oldval); ++ format %{ "StoreLConditional cmpxchg $mem, $newval\t# If $oldval == $mem then store $newval into $mem" %} ++ ins_encode%{ ++ Register oldval = $oldval$$Register; ++ Register newval = $newval$$Register; ++ Address addr(as_Register($mem$$base), $mem$$disp); ++ Label again, nequal; ++ ++ int index = $mem$$index; ++ int disp = $mem$$disp; ++ ++ guarantee(disp == 0, "impossible encoding storeLConditional"); ++ SizedScope sc(&_masm, 40); ++ if (UseSW8A) { ++ if (UseCAS) { ++ __ move(GP, newval); ++ __ casl(oldval, addr.base(), GP); ++ __ cmpeq(AT, GP, oldval); ++ } else { ++ __ BIND(again); ++ __ lldl(GP, addr.base(), addr.disp()); ++ __ cmpeq(AT, GP, oldval); ++ __ beq(AT, nequal); ++ __ move(AT, newval); ++ __ lstl(AT, addr.base(), addr.disp()); ++ __ beq(AT, again); ++ __ BIND(nequal); ++ } ++ } else { ++ __ BIND(again); ++ __ lldl(AT, addr.base(), addr.disp()); ++ __ cmpeq(GP, AT, oldval); ++ __ wr_f(GP); ++ __ move(AT, newval); ++ __ align(8); ++ __ lstl(AT, addr.base(), addr.disp()); ++ __ rd_f(AT); ++ __ beq(GP, nequal); ++ __ beq(AT, again); ++ __ BIND(nequal); ++ } ++ %} ++ ins_pipe( long_memory_op ); ++%} ++ ++instruct storePConditional(indirect mem, t2_RegP oldval, mRegP newval, FlagsReg cr ) %{ ++ match(Set cr (StorePConditional mem (Binary oldval newval))); ++ effect(KILL oldval); ++ format %{ "StorePConditional cmpxchg $mem, $newval\t# If $oldval == $mem then store $newval into $mem" %} ++ ins_encode%{ ++ Register oldval = $oldval$$Register; ++ Register newval = $newval$$Register; ++ Address addr(as_Register($mem$$base), $mem$$disp); ++ Label again, nequal; ++ ++ int index = $mem$$index; ++ int disp = $mem$$disp; ++ ++ guarantee(disp == 0, "impossible encoding storePConditional"); ++ SizedScope sc(&_masm, 40); ++ if (UseSW8A) { ++ if (UseCAS) { ++ __ move(GP, newval); ++ __ casl(oldval, addr.base(), GP); ++ __ cmpeq(AT, GP, oldval); ++ } else { ++ __ BIND(again); ++ __ lldl(GP, addr.base(), addr.disp()); ++ __ cmpeq(AT, GP, oldval); ++ __ beq(AT, nequal); ++ __ move(AT, newval); ++ __ lstl(AT, addr.base(), addr.disp()); ++ __ beq(AT, again); ++ __ BIND(nequal); ++ } ++ } else { ++ __ BIND(again); ++ __ lldl(AT, addr.base(), addr.disp()); ++ __ cmpeq(GP, AT, oldval); ++ __ wr_f(GP); ++ __ move(AT, newval); ++ __ align(8); ++ __ lstl(AT, addr.base(), addr.disp()); ++ __ rd_f(AT); ++ __ beq(GP, nequal); ++ __ beq(AT, again); ++ __ BIND(nequal); ++ } ++ %} ++ ins_pipe( long_memory_op ); ++%} ++ ++instruct compareAndSwapI( mRegI res, mRegP mem_ptr, mT5RegI oldval, mRegI newval, mT10RegI tmpt10) %{ ++ match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); ++ effect(TEMP tmpt10, USE_KILL oldval); ++ // size(60); ++// match(CompareAndSwapI mem_ptr (Binary oldval newval)); ++ format %{ "CMPXCHG $newval, [$mem_ptr], $oldval @ compareAndSwapI\n\t" ++ "MOV $res, 1 @ compareAndSwapI\n\t" ++ "BNE AT, R0 @ compareAndSwapI\n\t" ++ "MOV $res, 0 @ compareAndSwapI\n" ++ "L:" %} ++ ins_encode %{ ++ Register newval = $newval$$Register; ++ Register oldval = $oldval$$Register; ++ Register res = $res$$Register; ++ Address addr($mem_ptr$$Register, 0); ++ Label L; ++ ++ __ cmpxchg32(newval, addr, oldval); ++ __ move(res, AT); ++ %} ++ ins_pipe( long_memory_op ); ++%} ++ ++instruct compareAndSwapL( mRegI res, mRegP mem_ptr, t5RegL oldval, mRegL newval, t10_RegP tmpt10) %{ ++ predicate(VM_Version::supports_cx8()); ++ match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); ++ effect(TEMP tmpt10, USE_KILL oldval); ++ // size(60); //TODO: ZHJ20180613 ++ format %{ "CMPXCHG $newval, [$mem_ptr], $oldval @ compareAndSwapL\n\t" ++ "MOV $res, AT @ compareAndSwapL\n\t" ++ "L:" %} ++ ins_encode %{ ++ Register newval = $newval$$Register; ++ Register oldval = $oldval$$Register; ++ Register res = $res$$Register; ++ Address addr($mem_ptr$$Register, 0); ++ Label L; ++ ++ __ cmpxchg(newval, addr, oldval); ++ __ move(res, AT); ++ %} ++ ins_pipe( long_memory_op ); ++%} ++ ++instruct compareAndSwapP( mRegI res, mRegP mem_ptr, t5_RegP oldval, mRegP newval, t10_RegP tmpt10) %{ ++ match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); ++ effect(TEMP tmpt10, USE_KILL oldval); ++ // size(60); ++ format %{ "CMPXCHG $newval, [$mem_ptr], $oldval @ compareAndSwapP\n\t" ++ "MOV $res, AT @ compareAndSwapP\n\t" ++ "L:" %} ++ ins_encode %{ ++ Register newval = $newval$$Register; ++ Register oldval = $oldval$$Register; ++ Register res = $res$$Register; ++ Address addr($mem_ptr$$Register, 0); ++ Label L; ++ ++ __ cmpxchg(newval, addr, oldval); ++ __ move(res, AT); ++ %} ++ ins_pipe( long_memory_op ); ++%} ++ ++instruct compareAndSwapN( mRegI res, mRegP mem_ptr, t2_RegN oldval, mRegN newval, t10_RegN tmpT10) %{ ++ match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval))); ++ effect(TEMP tmpT10, USE_KILL oldval); ++ //size(64); ++ format %{ "CMPXCHG $newval, [$mem_ptr], $oldval @ compareAndSwapN\n\t" ++ "MOV $res, AT @ compareAndSwapN\n\t" ++ "L:" %} ++ ins_encode %{ ++ Register newval = $newval$$Register; ++ Register oldval = $oldval$$Register; ++ Register res = $res$$Register; ++ Address addr($mem_ptr$$Register, 0); ++ Label L; ++ ++ // cmpxchg32 is implemented with lldw, which will do sign extension. ++ // so we should extend oldval's sign for correct comparision. ++ __ addw(oldval, oldval, 0); ++ ++ __ cmpxchg32(newval, addr, oldval); ++ __ move(res, AT); ++ %} ++ ins_pipe( long_memory_op ); ++%} ++ ++instruct getAndAddI(memory mem, mRegI add, mRegI val) %{ ++ // predicate( n->get_int() == 1 && n->get_int() == -1); ++ // val = *mem & *mem = *mem + add ++ match(Set val (GetAndAddI mem add)); ++ format %{ "getAndAddI [$mem],$add" %} ++ ins_encode %{ ++ Register base = as_Register($mem$$base); ++ int disp = $mem$$disp; ++ Register value = $val$$Register; ++ Register add = $add$$Register; ++ Label again; ++ SizedScope sc(&_masm, 40); ++ guarantee(Assembler::is_simm(disp,12), "getAndAddI"); ++ if (UseSW8A) { ++ __ BIND(again); ++ __ lldw(AT, base, disp); ++ __ addw(GP, AT, add); ++ __ lstw(GP, base, disp); ++ __ beq(GP, again); ++ __ move(value, AT); ++ } else { ++ __ BIND(again); ++ __ lldw(AT, base, disp); ++ __ ldi(GP, R0, 1); ++ __ wr_f(GP); ++ __ addw(GP, AT, add); ++ __ align(8); // must align ++ __ lstw(GP, base, disp); ++ __ rd_f(GP); ++ __ beq(GP, again); ++ __ move(value, AT); ++ } ++ %} ++ ins_pipe( long_memory_op ); ++%} ++ ++instruct getAndAddL( memory mem, mRegL add, mRegL val) %{ ++ // val = *mem & *mem = *mem + add ++ match(Set val (GetAndAddL mem add)); ++ format %{ "getAndAddL [$mem],$add" %} ++ ins_encode %{ ++ Register base = as_Register($mem$$base); ++ int disp = $mem$$disp; ++ Register value = $val$$Register; ++ Register add = $add$$Register; ++ Label again; ++ SizedScope sc(&_masm, 40); ++ guarantee(Assembler::is_simm(disp,12), "getAndAddL"); ++ if (UseSW8A) { ++ __ BIND(again); ++ __ lldl(AT, base, disp); ++ __ addl(GP, AT, add); ++ __ lstl(GP, base, disp); ++ __ beq(GP, again); ++ __ move(value, AT); ++ } else { ++ __ BIND(again); ++ __ lldl(AT, base, disp); ++ __ ldi(GP, R0, 1); ++ __ wr_f(GP); ++ __ addl(GP, AT, add); ++ __ align(8); // must align ++ __ lstl(GP, base, disp); ++ __ rd_f(GP); ++ __ beq(GP, again); ++ __ move(value, AT); ++ } ++ %} ++ ins_pipe( long_memory_op ); ++%} ++ ++//----------Max and Min-------------------------------------------------------- ++// Min Instructions ++// *** Min and Max using the conditional move are slower than the ++// *** branch version on a Pentium III. ++// // Conditional move for min ++ ++// Min Register with Register (generic version) ++instruct minI_Reg_Reg(mRegI dst, mRegI src) %{ ++ match(Set dst (MinI dst src)); ++ //effect(KILL flags); ++ ins_cost(80); ++ ++ format %{ "MIN $dst, $src @minI_Reg_Reg" %} ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ Register src = $src$$Register; ++ ++ __ cmplt(AT, src, dst); ++ __ selne(AT, src, dst, dst); ++ ++ %} ++ ++ ins_pipe( pipe_slow ); ++%} ++ ++ ++// Max Register with Register (generic version) ++instruct maxI_Reg_Reg(mRegI dst, mRegI src) %{ ++ match(Set dst (MaxI dst src)); ++ ins_cost(80); ++ ++ format %{ "MAX $dst, $src @maxI_Reg_Reg" %} ++ ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ Register src = $src$$Register; ++ ++ __ cmplt(AT, dst, src); ++ __ selne(AT, src, dst, dst); ++ ++ %} ++ ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct maxI_Reg_zero(mRegI dst, immI0 zero) %{ ++ match(Set dst (MaxI dst zero)); ++ ins_cost(50); ++ ++ format %{ "MAX $dst, 0 @maxI_Reg_zero" %} ++ ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ ++ __ cmplt(AT, dst, R0); ++ __ selne(AT, R0, dst, dst); ++ ++ %} ++ ++ ins_pipe( pipe_slow ); ++%} ++ ++instruct zerox_long_reg_reg(mRegL dst, mRegL src, immL_32bits mask) ++%{ ++ match(Set dst (AndL src mask)); ++ ++ format %{ "movl $dst, $src\t# zero-extend long @ zerox_long_reg_reg" %} ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ Register src = $src$$Register; ++ ++ __ zapnot(dst, src, 0xf); // __ dext(dst, src, 0, 32); ++ ++ %} ++ ins_pipe(ialu_regI_regI); ++%} ++ ++// Zero-extend convert int to long ++instruct convI2L_reg_reg_zex(mRegL dst, mRegI src, immL_32bits mask) ++%{ ++ match(Set dst (AndL (ConvI2L src) mask)); ++ ++ format %{ "movl $dst, $src\t# i2l zero-extend @ convI2L_reg_reg_zex" %} ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ Register src = $src$$Register; ++ ++ __ zapnot(dst, src, 0xf); // __ dext(dst, src, 0, 32); ++ ++ %} ++ ins_pipe(ialu_regI_regI); ++%} ++ ++instruct convL2I2L_reg_reg_zex(mRegL dst, mRegL src, immL_32bits mask) ++%{ ++ match(Set dst (AndL (ConvI2L (ConvL2I src)) mask)); ++ ++ format %{ "movl $dst, $src\t# i2l zero-extend @ convL2I2L_reg_reg_zex" %} ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ Register src = $src$$Register; ++ ++ __ zapnot(dst, src, 0xf); // __ dext(dst, src, 0, 32); ++ ++ %} ++ ins_pipe(ialu_regI_regI); ++%} ++ ++// Match loading integer and casting it to unsigned int in long register. ++// LoadI + ConvI2L + AndL 0xffffffff. ++instruct loadUI2L_rmask(mRegL dst, memory mem, immL_32bits mask) %{ ++ match(Set dst (AndL (ConvI2L (LoadI mem)) mask)); ++ ++ format %{ "lwu $dst, $mem \t// zero-extend to long @ loadUI2L_rmask" %} ++ ins_encode (load_N_enc(dst, mem)); ++ ins_pipe(ialu_loadI); ++%} ++ ++instruct loadUI2L_lmask(mRegL dst, memory mem, immL_32bits mask) %{ ++ match(Set dst (AndL mask (ConvI2L (LoadI mem)))); ++ ++ format %{ "lwu $dst, $mem \t// zero-extend to long @ loadUI2L_lmask" %} ++ ins_encode (load_N_enc(dst, mem)); ++ ins_pipe(ialu_loadI); ++%} ++ ++ ++// ============================================================================ ++// Safepoint Instruction ++instruct safePoint_poll_reg(mRegP poll) %{ ++ match(SafePoint poll); ++ effect(USE poll); ++ ++ ins_cost(125); ++ format %{ "Safepoint @ [$poll] : poll for GC @ safePoint_poll_reg" %} ++ ++ ins_encode %{ ++ Register poll_reg = $poll$$Register; ++ ++ __ block_comment("Safepoint:"); ++ __ relocate(relocInfo::poll_type); ++ __ ldw(AT, poll_reg, 0); ++ %} ++ ++ ins_pipe( ialu_storeI ); ++%} ++ ++/* instruct safePoint_poll() %{ ++ match(SafePoint); ++ ++ ins_cost(105); ++ format %{ "poll for GC @ safePoint_poll" %} ++ ++ ins_encode %{ ++ __ block_comment("Safepoint:"); ++ __ set64(T12, (long)os::get_polling_page()); ++ __ relocate(relocInfo::poll_type); ++ __ ldw(AT, T12, 0); ++ %} ++ ++ ins_pipe( ialu_storeI ); ++%} */ ++ ++//----------Arithmetic Conversion Instructions--------------------------------- ++ ++instruct roundFloat_nop(regF dst) ++%{ ++ match(Set dst (RoundFloat dst)); ++ ++ ins_cost(0); ++ ins_encode(); ++ ins_pipe(empty); ++%} ++ ++instruct roundDouble_nop(regD dst) ++%{ ++ match(Set dst (RoundDouble dst)); ++ ++ ins_cost(0); ++ ins_encode(); ++ ins_pipe(empty); ++%} ++ ++//---------- Zeros Count Instructions ------------------------------------------ ++// CountLeadingZerosINode CountTrailingZerosINode ++instruct countLeadingZerosI(mRegI dst, mRegI src) %{ ++ predicate(UseCountLeadingZerosInstruction); ++ match(Set dst (CountLeadingZerosI src)); ++ ++ format %{ "CTLZ $dst, $dst #@countLeadingZerosI" %} ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ Register src = $src$$Register; ++ ++ __ zapnot(dst, src, 0xf); ++ __ ctlz(dst, dst); ++ __ subw(dst, dst, 32); ++ %} ++ ins_pipe( ialu_regL_regL ); ++%} ++ ++instruct countLeadingZerosL(mRegI dst, mRegL src) %{ ++ predicate(UseCountLeadingZerosInstruction); ++ match(Set dst (CountLeadingZerosL src)); ++ ++ format %{ "CTLZ $src,$dst #@countLeadingZerosL" %} ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ Register src = $src$$Register; ++ ++ __ ctlz(dst, src); ++ %} ++ ins_pipe(ialu_regL_regL); ++%} ++ ++instruct countTrailingZerosI(mRegI dst, mRegI src) %{ ++ predicate(UseCountTrailingZerosInstruction); ++ match(Set dst (CountTrailingZerosI src)); ++ ++ format %{ "CTTZ $src, $dst\n\t #@countTrailingZerosI"%} ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ Register src = $src$$Register; ++ ++ __ slll(dst, src, 32); ++ __ cttz(dst, dst); ++ __ subw(dst, dst, 32); ++ %} ++ ins_pipe( ialu_regL_regL ); ++%} ++ ++instruct countTrailingZerosL(mRegI dst, mRegL src) %{ ++ predicate(UseCountTrailingZerosInstruction); ++ match(Set dst (CountTrailingZerosL src)); ++ ++ format %{ "CTTZ $src,$dst #@countTrailingZerosL" %} ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ Register src = $src$$Register; ++ ++ __ cttz(dst, src); ++ %} ++ ins_pipe( ialu_regL_regL ); ++%} ++ ++//---------- Population Count Instructions ------------------------------------- ++instruct popCountI(mRegI dst, mRegI src) %{ ++ predicate(UsePopCountInstruction); ++ match(Set dst (PopCountI src)); ++ ++ format %{ "CTPOP $src, $dst #@popCountI" %} ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ Register src = $src$$Register; ++ ++ __ zapnot(dst, src, 0xf); ++ __ ctpop(dst, dst); ++ %} ++ ins_pipe(ialu_regL_regL); ++%} ++ ++// Note: Long.bitCount(long) returns an int. ++instruct popCountL(mRegI dst, mRegL src) %{ ++ predicate(UsePopCountInstruction); ++ match(Set dst (PopCountL src)); ++ ++ format %{ "CTPOP $src, $dst #@popCountL" %} ++ ins_encode %{ ++ Register dst = $dst$$Register; ++ Register src = $src$$Register; ++ ++ __ ctpop(dst, src); ++ %} ++ ins_pipe(ialu_regL_regL); ++%} ++ ++// ====================VECTOR INSTRUCTIONS===================================== ++ ++ ++// ====================VECTOR ARITHMETIC======================================= ++ ++// --------------------------------- ADD -------------------------------------- ++ ++// Floats vector add ++ ++// --------------------------------- SUB -------------------------------------- ++ ++// Floats vector sub ++ ++// --------------------------------- MUL -------------------------------------- ++ ++// Floats vector mul ++ ++// --------------------------------- DIV -------------------------------------- ++ ++// --------------------------------- MADD -------------------------------------- ++// Floats vector madd ++ ++ ++//----------PEEPHOLE RULES----------------------------------------------------- ++// These must follow all instruction definitions as they use the names ++// defined in the instructions definitions. ++// ++// peepmatch ( root_instr_name [preceeding_instruction]* ); ++// ++// peepconstraint %{ ++// (instruction_number.operand_name relational_op instruction_number.operand_name ++// [, ...] ); ++// // instruction numbers are zero-based using left to right order in peepmatch ++// ++// peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); ++// // provide an instruction_number.operand_name for each operand that appears ++// // in the replacement instruction's match rule ++// ++// ---------VM FLAGS--------------------------------------------------------- ++// ++// All peephole optimizations can be turned off using -XX:-OptoPeephole ++// ++// Each peephole rule is given an identifying number starting with zero and ++// increasing by one in the order seen by the parser. An individual peephole ++// can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# ++// on the command-line. ++// ++// ---------CURRENT LIMITATIONS---------------------------------------------- ++// ++// Only match adjacent instructions in same basic block ++// Only equality constraints ++// Only constraints between operands, not (0.dest_reg == EAX_enc) ++// Only one replacement instruction ++// ++// ---------EXAMPLE---------------------------------------------------------- ++// ++// // pertinent parts of existing instructions in architecture description ++// instruct movI(eRegI dst, eRegI src) %{ ++// match(Set dst (CopyI src)); ++// %} ++// ++// instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ ++// match(Set dst (AddI dst src)); ++// effect(KILL cr); ++// %} ++// ++// // Change (inc mov) to lea ++// peephole %{ ++// // increment preceeded by register-register move ++// peepmatch ( incI_eReg movI ); ++// // require that the destination register of the increment ++// // match the destination register of the move ++// peepconstraint ( 0.dst == 1.dst ); ++// // construct a replacement instruction that sets ++// // the destination to ( move's source register + one ) ++// peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); ++// %} ++// ++// Implementation no longer uses movX instructions since ++// machine-independent system no longer uses CopyX nodes. ++// ++// peephole %{ ++// peepmatch ( incI_eReg movI ); ++// peepconstraint ( 0.dst == 1.dst ); ++// peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); ++// %} ++// ++// peephole %{ ++// peepmatch ( decI_eReg movI ); ++// peepconstraint ( 0.dst == 1.dst ); ++// peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); ++// %} ++// ++// peephole %{ ++// peepmatch ( addI_eReg_imm movI ); ++// peepconstraint ( 0.dst == 1.dst ); ++// peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); ++// %} ++// ++// peephole %{ ++// peepmatch ( addP_eReg_imm movP ); ++// peepconstraint ( 0.dst == 1.dst ); ++// peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) ); ++// %} ++ ++// // Change load of spilled value to only a spill ++// instruct storeI(memory mem, eRegI src) %{ ++// match(Set mem (StoreI mem src)); ++// %} ++// ++// instruct loadI(eRegI dst, memory mem) %{ ++// match(Set dst (LoadI mem)); ++// %} ++// ++//peephole %{ ++// peepmatch ( loadI storeI ); ++// peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); ++// peepreplace ( storeI( 1.mem 1.mem 1.src ) ); ++//%} ++ ++//----------SMARTSPILL RULES--------------------------------------------------- ++// These must follow all instruction definitions as they use the names ++// defined in the instructions definitions. ++ +diff --git a/hotspot/src/cpu/sw64/vm/templateInterpreterGenerator_sw64.hpp b/hotspot/src/cpu/sw64/vm/templateInterpreterGenerator_sw64.hpp +new file mode 100755 +index 0000000000..f084295d93 +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/templateInterpreterGenerator_sw64.hpp +@@ -0,0 +1,34 @@ ++/* ++ * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_SW64_VM_TEMPLATEINTERPRETERGENERATOR_SW64_HPP ++#define CPU_SW64_VM_TEMPLATEINTERPRETERGENERATOR_SW64_HPP ++ ++ protected: ++ ++ void generate_fixed_frame(bool native_call); ++ ++ // address generate_asm_interpreter_entry(bool synchronized); ++ ++#endif // CPU_SW64_VM_TEMPLATEINTERPRETERGENERATOR_SW64_HPP +diff --git a/hotspot/src/cpu/sw64/vm/templateInterpreter_sw64.cpp b/hotspot/src/cpu/sw64/vm/templateInterpreter_sw64.cpp +new file mode 100755 +index 0000000000..c78ac10712 +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/templateInterpreter_sw64.cpp +@@ -0,0 +1,2244 @@ ++/* ++ * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#include "precompiled.hpp" ++#include "asm/macroAssembler.hpp" ++#include "interpreter/bytecodeHistogram.hpp" ++#include "interpreter/interpreter.hpp" ++#include "interpreter/interpreterGenerator.hpp" ++#include "interpreter/interpreterRuntime.hpp" ++#include "interpreter/templateTable.hpp" ++#include "oops/arrayOop.hpp" ++#include "oops/methodData.hpp" ++#include "oops/method.hpp" ++#include "oops/oop.inline.hpp" ++#include "prims/jvmtiExport.hpp" ++#include "prims/jvmtiThreadState.hpp" ++#include "runtime/arguments.hpp" ++#include "runtime/deoptimization.hpp" ++#include "runtime/frame.inline.hpp" ++#include "runtime/sharedRuntime.hpp" ++#include "runtime/stubRoutines.hpp" ++#include "runtime/synchronizer.hpp" ++#include "runtime/timer.hpp" ++#include "runtime/vframeArray.hpp" ++#include "utilities/debug.hpp" ++ ++#define __ _masm-> ++ ++#ifdef PRODUCT ++#define BLOCK_COMMENT(str) /* nothing */ ++#else ++#define BLOCK_COMMENT(str) { char line[1024]; sprintf(line,"%s:%s:%d",str,__FILE__, __LINE__); __ block_comment(line);} ++#endif ++#define BIND(label) bind(label); BLOCK_COMMENT(#label ":") ++ ++#ifndef CC_INTERP ++ ++// asm based interpreter deoptimization helpers ++int AbstractInterpreter::size_activation(int max_stack, ++ int temps, ++ int extra_args, ++ int monitors, ++ int callee_params, ++ int callee_locals, ++ bool is_top_frame) { ++ // Note: This calculation must exactly parallel the frame setup ++ // in AbstractInterpreterGenerator::generate_method_entry. ++ ++ // fixed size of an interpreter frame: ++ int overhead = frame::sender_sp_offset - ++ frame::interpreter_frame_initial_sp_offset; ++ // Our locals were accounted for by the caller (or last_frame_adjust ++ // on the transistion) Since the callee parameters already account ++ // for the callee's params we only need to account for the extra ++ // locals. ++ int size = overhead + ++ (callee_locals - callee_params)*Interpreter::stackElementWords + ++ monitors * frame::interpreter_frame_monitor_size() + ++ temps* Interpreter::stackElementWords + extra_args; ++ ++ return size; ++} ++ ++ ++const int Interpreter::return_sentinel = 0xfeedbeed; ++const int method_offset = frame::interpreter_frame_method_offset * wordSize; ++const int bci_offset = frame::interpreter_frame_bcx_offset * wordSize; ++const int locals_offset = frame::interpreter_frame_locals_offset * wordSize; ++ ++//----------------------------------------------------------------------------- ++ ++address TemplateInterpreterGenerator::generate_StackOverflowError_handler() { ++ address entry = __ pc(); ++ ++#ifdef ASSERT ++ { ++ Label L; ++ __ add_simm16(T1, FP, frame::interpreter_frame_monitor_block_top_offset * wordSize); ++ __ subl(T1, T1, SP); // T1 = maximal sp for current fp ++ __ bge(T1, L); // check if frame is complete ++ __ stop("interpreter frame not set up"); ++ __ BIND(L); ++ } ++#endif // ASSERT ++ ++ // Restore bcp under the assumption that the current frame is still ++ // interpreted ++ // S0 is the conventional register for bcp ++ __ restore_bcp(); ++ ++ // expression stack must be empty before entering the VM if an ++ // exception happened ++ __ empty_expression_stack(); ++ // throw exception ++ __ call_VM(NOREG, CAST_FROM_FN_PTR(address, InterpreterRuntime::throw_StackOverflowError)); ++ return entry; ++} ++ ++address TemplateInterpreterGenerator::generate_ArrayIndexOutOfBounds_handler( ++ const char* name) { ++ address entry = __ pc(); ++ // expression stack must be empty before entering the VM if an exception happened ++ __ empty_expression_stack(); ++ __ li(A1, (long)name); ++ __ call_VM(noreg, CAST_FROM_FN_PTR(address, ++ InterpreterRuntime::throw_ArrayIndexOutOfBoundsException), A1, A2); ++ return entry; ++} ++ ++address TemplateInterpreterGenerator::generate_ClassCastException_handler() { ++ address entry = __ pc(); ++ ++ // expression stack must be empty before entering the VM if an exception happened ++ __ empty_expression_stack(); ++ __ empty_FPU_stack(); ++ __ call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::throw_ClassCastException), FSR); ++ return entry; ++} ++ ++address TemplateInterpreterGenerator::generate_exception_handler_common( ++ const char* name, const char* message, bool pass_oop) { ++ assert(!pass_oop || message == NULL, "either oop or message but not both"); ++ address entry = __ pc(); ++ ++ // expression stack must be empty before entering the VM if an exception happened ++ __ empty_expression_stack(); ++ // setup parameters ++ __ li(A1, (long)name); ++ if (pass_oop) { ++ __ call_VM(V0, ++ CAST_FROM_FN_PTR(address, InterpreterRuntime::create_klass_exception), A1, FSR); ++ } else { ++ __ li(A2, (long)message); ++ __ call_VM(V0, ++ CAST_FROM_FN_PTR(address, InterpreterRuntime::create_exception), A1, A2); ++ } ++ // throw exception ++ __ jmp(Interpreter::throw_exception_entry(), relocInfo::none); ++ return entry; ++} ++ ++ ++address TemplateInterpreterGenerator::generate_continuation_for(TosState state) { ++ address entry = __ pc(); ++ // NULL last_sp until next java call ++ __ stl(R0,Address(FP, frame::interpreter_frame_last_sp_offset * wordSize)); ++ __ dispatch_next(state); ++ return entry; ++} ++ ++ ++address TemplateInterpreterGenerator::generate_return_entry_for(TosState state, int step, size_t index_size) { ++ ++ address entry = __ pc(); ++ ++ // Restore stack bottom in case i2c adjusted stack ++ __ ldl(SP, Address(FP, frame::interpreter_frame_last_sp_offset * wordSize)); ++ // and NULL it as marker that sp is now tos until next java call ++ __ stl(R0, FP, frame::interpreter_frame_last_sp_offset * wordSize); ++ ++ __ restore_bcp(); ++ __ restore_locals(); ++ ++ // mdp: T11 ++ // ret: FSR ++ // tmp: T12 ++ if (state == atos) { ++ Register mdp = T11; ++ Register tmp = T12; ++ __ profile_return_type(mdp, FSR, tmp); ++ } ++ ++ ++ const Register cache = T12; ++ const Register index = T3; ++ __ get_cache_and_index_at_bcp(cache, index, 1, index_size); ++ ++ const Register flags = cache; ++ __ slll(AT, index, Address::times_ptr); ++ __ addl(AT, cache, AT); ++ __ ldw(flags, AT, in_bytes(ConstantPoolCache::base_offset() + ConstantPoolCacheEntry::flags_offset())); ++ __ and_imm8(flags, flags, ConstantPoolCacheEntry::parameter_size_mask); ++ __ slll(AT, flags, Interpreter::stackElementScale()); ++ __ addl(SP, SP, AT); ++ ++ __ dispatch_next(state, step); ++ ++ return entry; ++} ++ ++ ++address TemplateInterpreterGenerator::generate_deopt_entry_for(TosState state, ++ int step) { ++ address entry = __ pc(); ++ // NULL last_sp until next java call ++ __ stl(R0, FP, frame::interpreter_frame_last_sp_offset * wordSize); ++ __ restore_bcp(); ++ __ restore_locals(); ++ // handle exceptions ++ { ++ Label L; ++ const Register thread = S2thread; ++ __ ldw(AT, thread, in_bytes(Thread::pending_exception_offset())); ++ __ beq(AT, L); ++ __ call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::throw_pending_exception)); ++ __ should_not_reach_here(); ++ __ BIND(L); ++ } ++ __ dispatch_next(state, step); ++ return entry; ++} ++ ++int AbstractInterpreter::BasicType_as_index(BasicType type) { ++ int i = 0; ++ switch (type) { ++ case T_BOOLEAN: i = 0; break; ++ case T_CHAR : i = 1; break; ++ case T_BYTE : i = 2; break; ++ case T_SHORT : i = 3; break; ++ case T_INT : // fall through ++ case T_LONG : // fall through ++ case T_VOID : i = 4; break; ++ case T_FLOAT : i = 5; break; ++ case T_DOUBLE : i = 6; break; ++ case T_OBJECT : // fall through ++ case T_ARRAY : i = 7; break; ++ default : ShouldNotReachHere(); ++ } ++ assert(0 <= i && i < AbstractInterpreter::number_of_result_handlers, ++ "index out of bounds"); ++ return i; ++} ++ ++ ++address TemplateInterpreterGenerator::generate_result_handler_for( ++ BasicType type) { ++ address entry = __ pc(); ++ switch (type) { ++ case T_BOOLEAN: __ c2bool(V0); break; ++ case T_CHAR : __ zapnot(V0, V0, 0x3); break; ++ case T_BYTE : __ sign_extend_byte (V0); break; ++ case T_SHORT : __ sign_extend_short(V0); break; ++ case T_INT : /* nothing to do */ break; ++ case T_FLOAT : /* nothing to do */ break; ++ case T_DOUBLE : /* nothing to do */ break; ++ case T_OBJECT : ++ { ++ __ ldl(V0, FP, frame::interpreter_frame_oop_temp_offset * wordSize); ++ __ verify_oop(V0); // and verify it ++ } ++ break; ++ default : ShouldNotReachHere(); ++ } ++ __ ret(); // return from result handler ++ return entry; ++} ++ ++address TemplateInterpreterGenerator::generate_safept_entry_for( ++ TosState state, ++ address runtime_entry) { ++ address entry = __ pc(); ++ __ push(state); ++ __ call_VM(noreg, runtime_entry); ++ __ dispatch_via(vtos, Interpreter::_normal_table.table_for(vtos)); ++ return entry; ++} ++ ++ ++ ++// Helpers for commoning out cases in the various type of method entries. ++// ++ ++ ++// increment invocation count & check for overflow ++// ++// Note: checking for negative value instead of overflow ++// so we have a 'sticky' overflow test ++// ++// Rmethod: method ++// T3 : invocation counter ++// ++void InterpreterGenerator::generate_counter_incr( ++ Label* overflow, ++ Label* profile_method, ++ Label* profile_method_continue) { ++ Label done; ++ if (TieredCompilation) { ++ int increment = InvocationCounter::count_increment; ++ int mask = ((1 << Tier0InvokeNotifyFreqLog) - 1) << InvocationCounter::count_shift; ++ Label no_mdo; ++ if (ProfileInterpreter) { ++ // Are we profiling? ++ __ ldl(FSR, Address(Rmethod, Method::method_data_offset())); ++ __ beq(FSR, no_mdo); ++ // Increment counter in the MDO ++ const Address mdo_invocation_counter(FSR, in_bytes(MethodData::invocation_counter_offset()) + ++ in_bytes(InvocationCounter::counter_offset())); ++ __ increment_mask_and_jump(mdo_invocation_counter, increment, mask, T3, false, Assembler::zero, overflow); ++ __ beq(R0, done); ++ } ++ __ BIND(no_mdo); ++ // Increment counter in MethodCounters ++ const Address invocation_counter(FSR, ++ MethodCounters::invocation_counter_offset() + ++ InvocationCounter::counter_offset()); ++ __ get_method_counters(Rmethod, FSR, done); ++ __ increment_mask_and_jump(invocation_counter, increment, mask, T3, false, Assembler::zero, overflow); ++ __ BIND(done); ++ } else { ++ const Address invocation_counter(FSR, in_bytes(MethodCounters::invocation_counter_offset()) ++ + in_bytes(InvocationCounter::counter_offset())); ++ const Address backedge_counter (FSR, in_bytes(MethodCounters::backedge_counter_offset()) ++ + in_bytes(InvocationCounter::counter_offset())); ++ ++ __ get_method_counters(Rmethod, FSR, done); ++ ++ if (ProfileInterpreter) { // %%% Merge this into methodDataOop ++ __ ldw(T12, FSR, in_bytes(MethodCounters::interpreter_invocation_counter_offset())); ++ __ incrementl(T12, 1); ++ __ stw(T12, FSR, in_bytes(MethodCounters::interpreter_invocation_counter_offset())); ++ } ++ // Update standard invocation counters ++ __ ldw(T3, invocation_counter.base(), invocation_counter.disp()); ++ __ increment(T3, InvocationCounter::count_increment); ++ __ stw(T3, invocation_counter); // save invocation count ++ ++ __ ldw_signed(FSR, backedge_counter); // load backedge counter ++ if (Assembler::is_simm16(InvocationCounter::count_mask_value)) { ++ __ ldi(AT, R0, InvocationCounter::count_mask_value); ++ } else { ++ __ li(AT, InvocationCounter::count_mask_value); // mask out the status bits ++ } ++ __ and_reg(FSR, FSR, AT); ++ ++ __ addl(T3, T3, FSR); // add both counters ++ ++ if (ProfileInterpreter && profile_method != NULL) { ++ // Test to see if we should create a method data oop ++ __ li32(AT, (long)InvocationCounter::InterpreterProfileLimit); ++ __ cmplt(AT, T3, AT); ++ __ bne(AT, *profile_method_continue); ++ ++ // if no method data exists, go to profile_method ++ __ test_method_data_pointer(FSR, *profile_method); ++ } ++ ++ __ li32(AT, (long)InvocationCounter::InterpreterInvocationLimit); ++ __ cmplt(AT, T3, AT); ++ __ beq(AT, *overflow); ++ ++ __ BIND(done); ++ } ++} ++ ++void InterpreterGenerator::generate_counter_overflow(Label* do_continue) { ++ ++ // Asm interpreter on entry ++ // S1 - locals ++ // S0 - bcp ++ // Rmethod - method ++ // FP - interpreter frame ++ ++ // On return (i.e. jump to entry_point) ++ // Rmethod - method ++ // RA - return address of interpreter caller ++ // tos - the last parameter to Java method ++ // SP - sender_sp ++ ++ ++ // the bcp is valid if and only if it's not null ++ __ call_VM(NOREG, CAST_FROM_FN_PTR(address, ++ InterpreterRuntime::frequency_counter_overflow), R0); ++ __ ldl(Rmethod, FP, method_offset); ++ // Preserve invariant that S0/S1 contain bcp/locals of sender frame ++ __ b_far(*do_continue); ++} ++ ++// See if we've got enough room on the stack for locals plus overhead. ++// The expression stack grows down incrementally, so the normal guard ++// page mechanism will work for that. ++// ++// NOTE: Since the additional locals are also always pushed (wasn't ++// obvious in generate_method_entry) so the guard should work for them ++// too. ++// ++// Args: ++// T2: number of additional locals this frame needs (what we must check) ++// T0: Method* ++// ++void InterpreterGenerator::generate_stack_overflow_check(void) { ++ // see if we've got enough room on the stack for locals plus overhead. ++ // the expression stack grows down incrementally, so the normal guard ++ // page mechanism will work for that. ++ // ++ // Registers live on entry: ++ // ++ // T0: Method* ++ // T2: number of additional locals this frame needs (what we must check) ++ ++ // NOTE: since the additional locals are also always pushed (wasn't obvious in ++ // generate_method_entry) so the guard should work for them too. ++ // ++ ++ const int entry_size = frame::interpreter_frame_monitor_size() * wordSize; ++ ++ // total overhead size: entry_size + (saved fp thru expr stack bottom). ++ // be sure to change this if you add/subtract anything to/from the overhead area ++ const int overhead_size = -(frame::interpreter_frame_initial_sp_offset*wordSize) ++ + entry_size; ++ ++ const int page_size = os::vm_page_size(); ++ ++ Label after_frame_check; ++ ++ // see if the frame is greater than one page in size. If so, ++ // then we need to verify there is enough stack space remaining ++ // for the additional locals. ++ __ move(AT, (page_size - overhead_size) / Interpreter::stackElementSize); ++ __ cmplt(AT, AT, T2); ++ __ beq(AT, after_frame_check); ++ ++ // compute sp as if this were going to be the last frame on ++ // the stack before the red zone ++ Register thread = S2thread; ++ ++ // locals + overhead, in bytes ++ __ slll(T3, T2, Interpreter::stackElementScale()); ++ __ add_simm16(T3, T3, overhead_size); // locals * 4 + overhead_size --> T3 ++ ++#ifdef ASSERT ++ Label stack_base_okay, stack_size_okay; ++ // verify that thread stack base is non-zero ++ __ ldl(AT, thread, in_bytes(Thread::stack_base_offset())); ++ __ bne(AT, stack_base_okay); ++ __ stop("stack base is zero"); ++ __ BIND(stack_base_okay); ++ // verify that thread stack size is non-zero ++ __ ldl(AT, thread, in_bytes(Thread::stack_size_offset())); ++ __ bne(AT, stack_size_okay); ++ __ stop("stack size is zero"); ++ __ BIND(stack_size_okay); ++#endif ++ ++ // Add stack base to locals and subtract stack size ++ __ ldl(AT, thread, in_bytes(Thread::stack_base_offset())); // stack_base --> AT ++ __ addl(T3, T3, AT); // locals * 4 + overhead_size + stack_base--> T3 ++ __ ldl(AT, thread, in_bytes(Thread::stack_size_offset())); // stack_size --> AT ++ __ subl(T3, T3, AT); // locals * 4 + overhead_size + stack_base - stack_size --> T3 ++ ++ ++ // add in the redzone and yellow size ++ __ move(AT, (StackRedPages+StackYellowPages) * page_size); ++ __ addl(T3, T3, AT); ++ ++ // check against the current stack bottom ++ __ cmplt(AT, T3, SP); ++ __ bne(AT, after_frame_check); ++ ++ // Note: the restored frame is not necessarily interpreted. ++ // Use the shared runtime version of the StackOverflowError. ++ __ move(SP, Rsender); ++ assert(StubRoutines::throw_StackOverflowError_entry() != NULL, "stub not yet generated"); ++ __ jmp(StubRoutines::throw_StackOverflowError_entry(), relocInfo::runtime_call_type); ++ ++ // all done with frame size check ++ __ BIND(after_frame_check); ++} ++ ++// Allocate monitor and lock method (asm interpreter) ++// Rmethod - Method* ++void InterpreterGenerator::lock_method(void) { ++ // synchronize method ++ const int entry_size = frame::interpreter_frame_monitor_size() * wordSize; ++ ++#ifdef ASSERT ++ { Label L; ++ __ ldw(T0, Rmethod, in_bytes(Method::access_flags_offset())); ++ __ and_imm8(T0, T0, JVM_ACC_SYNCHRONIZED); ++ __ bne(T0, L); ++ __ stop("method doesn't need synchronization"); ++ __ BIND(L); ++ } ++#endif // ASSERT ++ // get synchronization object ++ { ++ Label done; ++ const int mirror_offset = in_bytes(Klass::java_mirror_offset()); ++ __ ldw(T0, Rmethod, in_bytes(Method::access_flags_offset())); ++ __ and_imm8(T2, T0, JVM_ACC_STATIC); ++ __ ldl(T0, LVP, Interpreter::local_offset_in_bytes(0)); ++ __ beq(T2, done); ++ __ ldl(T0, Rmethod, in_bytes(Method::const_offset())); ++ __ ldl(T0, T0, in_bytes(ConstMethod::constants_offset())); ++ __ ldl(T0, T0, ConstantPool::pool_holder_offset_in_bytes()); ++ __ ldl(T0, T0, mirror_offset); ++ __ BIND(done); ++ } ++ // add space for monitor & lock ++ __ add_simm16(SP, SP, (-1) * entry_size); // add space for a monitor entry ++ __ stl(SP, FP, frame::interpreter_frame_monitor_block_top_offset * wordSize); ++ // set new monitor block top ++ __ stl(T0, SP, BasicObjectLock::obj_offset_in_bytes()); // store object ++ __ move(c_rarg0, SP); // object address ++ __ lock_object(c_rarg0); ++} ++ ++// Generate a fixed interpreter frame. This is identical setup for ++// interpreted methods and for native methods hence the shared code. ++void TemplateInterpreterGenerator::generate_fixed_frame(bool native_call) { ++ ++ // [ local var m-1 ] <--- sp ++ // ... ++ // [ local var 0 ] ++ // [ argumnet word n-1 ] <--- T0(sender's sp) ++ // ... ++ // [ argument word 0 ] <--- S1 ++ ++ // initialize fixed part of activation frame ++ // sender's sp in Rsender ++ int i = 0; ++ const int frame_size = 8; ++ const int total_size = 2 + frame_size; ++ __ add_simm16(SP, SP, -total_size * wordSize); ++ __ stl(RA, SP, (total_size - 1) * wordSize); // save return address ++ __ stl(FP, SP, (total_size - 2) * wordSize); // save sender's fp ++ __ add_simm16(FP, SP, (total_size - 2) * wordSize); ++ __ stl(Rsender, FP, (-++i) * wordSize); // save sender's sp ++ __ stl(R0, FP,(-++i)*wordSize); //save last_sp as null ++ __ stl(LVP, FP, (-++i) * wordSize); // save locals offset ++ __ ldl(BCP, Rmethod, in_bytes(Method::const_offset())); // get constMethodOop ++ __ add_simm16(BCP, BCP, in_bytes(ConstMethod::codes_offset())); // get codebase ++ __ stl(Rmethod, FP, (-++i) * wordSize); // save Method* ++#ifndef CORE ++ if (ProfileInterpreter) { ++ Label method_data_continue; ++ __ ldl(AT, Rmethod, in_bytes(Method::method_data_offset())); ++ __ beq(AT, method_data_continue); ++ __ add_simm16(AT, AT, in_bytes(MethodData::data_offset())); ++ __ BIND(method_data_continue); ++ __ stl(AT, FP, (-++i) * wordSize); ++ } else { ++ __ stl(R0, FP, (-++i) * wordSize); ++ } ++#endif // !CORE ++ ++ __ ldl(T2, Rmethod, in_bytes(Method::const_offset())); ++ __ ldl(T2, T2, in_bytes(ConstMethod::constants_offset())); ++ __ ldl(T2, T2, ConstantPool::cache_offset_in_bytes()); ++ __ stl(T2, FP, (-++i) * wordSize); // set constant pool cache ++ if (native_call) { ++ __ stl(R0, FP, (-++i) * wordSize); // no bcp ++ } else { ++ __ stl(BCP, FP, (-++i) * wordSize); // set bcp ++ } ++ __ stl(SP, FP, (-++i) * wordSize); // reserve word for pointer to expression stack bottom ++ assert(frame_size == i, "stack frame size error."); ++} ++ ++// End of helpers ++ ++// Various method entries ++//------------------------------------------------------------------------------------------------------------------------ ++// ++// ++ ++// Call an accessor method (assuming it is resolved, otherwise drop ++// into vanilla (slow path) entry ++address InterpreterGenerator::generate_accessor_entry(void) { ++ ++ // Rmethod: Method* ++ // V0: receiver (preserve for slow entry into asm interpreter) ++ // Rsender: senderSP must preserved for slow path, set SP to it on fast path ++ ++ address entry_point = __ pc(); ++ Label xreturn_path; ++ // do fastpath for resolved accessor methods ++ if (UseFastAccessorMethods) { ++ Label slow_path; ++ __ li(T2, SafepointSynchronize::address_of_state()); ++ __ ldw(AT, T2, 0); ++ __ add_simm16(AT, AT, -(SafepointSynchronize::_not_synchronized)); ++ __ bne(AT, slow_path); ++ // Code: _aload_0, _(i|a)getfield, _(i|a)return or any rewrites thereof; ++ // parameter size = 1 ++ // Note: We can only use this code if the getfield has been resolved ++ // and if we don't have a null-pointer exception => check for ++ // these conditions first and use slow path if necessary. ++ // Rmethod: method ++ // V0: receiver ++ ++ // [ receiver ] <-- sp ++ __ ldl(T0, SP, 0); ++ ++ // check if local 0 != NULL and read field ++ __ beq(T0, slow_path); ++ __ ldl(T2, Rmethod, in_bytes(Method::const_offset())); ++ __ ldl(T2, T2, in_bytes(ConstMethod::constants_offset())); ++ // read first instruction word and extract bytecode @ 1 and index @ 2 ++ __ ldl(T3, Rmethod, in_bytes(Method::const_offset())); ++ __ ldw(T3, T3, in_bytes(ConstMethod::codes_offset())); ++ // Shift codes right to get the index on the right. ++ // The bytecode fetched looks like <0xb4><0x2a> ++ __ srll(T3, T3, 2 * BitsPerByte); ++ __ slll(T3, T3, exact_log2(in_words(ConstantPoolCacheEntry::size()))); ++ __ ldl(T2, T2, ConstantPool::cache_offset_in_bytes()); ++ ++ // T0: local 0 ++ // Rmethod: method ++ // V0: receiver - do not destroy since it is needed for slow path! ++ // T1: scratch use which register instead ? ++ // T3: constant pool cache index ++ // T2: constant pool cache ++ // Rsender: send's sp ++ // check if getfield has been resolved and read constant pool cache entry ++ // check the validity of the cache entry by testing whether _indices field ++ // contains Bytecode::_getfield in b1 byte. ++ assert(in_words(ConstantPoolCacheEntry::size()) == 4, "adjust shift below"); ++ ++ __ slll(T11, T3, Address::times_8); ++ __ addl(T11, T2, T11); ++ __ ldw(T1, T11, in_bytes(ConstantPoolCache::base_offset() + ConstantPoolCacheEntry::indices_offset())); ++ ++ __ srll(T1, T1, 2 * BitsPerByte); ++ __ and_imm8(T1, T1, 0xFF); ++ __ add_simm16(T1, T1, (-1) * Bytecodes::_getfield); ++ __ bne(T1, slow_path); ++ __ memb();// Order succeeding loads wrt. load of _indices field from cpool_cache. ++ ++ // Note: constant pool entry is not valid before bytecode is resolved ++ ++ __ ldw(AT, T11, in_bytes(ConstantPoolCache::base_offset() + ConstantPoolCacheEntry::f2_offset())); ++ __ ldw(T3, T11, in_bytes(ConstantPoolCache::base_offset() + ConstantPoolCacheEntry::flags_offset())); ++ __ move(T11, 1 << ConstantPoolCacheEntry::is_volatile_shift); ++ __ and_reg(T11, T11, T3); ++ ++ { ++ Label notVolatile; ++ __ beq(T11, notVolatile); ++ if(os::is_MP()) __ memb(); ++ __ BIND(notVolatile); ++ } ++ Label notByte, notBool, notShort, notChar, notObj; ++ ++ // Need to differentiate between igetfield, agetfield, bgetfield etc. ++ // because they are different sizes. ++ // Use the type from the constant pool cache ++ __ zapnot(T3, T3, 0xf); ++ __ srll(T3, T3, ConstantPoolCacheEntry::tos_state_shift); ++ // Make sure we don't need to mask T3 for tosBits after the above shift ++ ConstantPoolCacheEntry::verify_tos_state_shift(); ++ // btos = 0 ++ __ addl(T0, T0, AT); ++ __ bne(T3, notByte); ++ ++ __ ldb_signed(V0, T0, 0); ++ __ beq(R0, xreturn_path); ++ ++ //ztos ++ __ BIND(notByte); ++ __ add_simm16(T1, T3, (-1) * ztos); ++ __ bne(T1, notBool); ++ __ ldb_signed(V0, T0, 0); ++ __ beq(R0, xreturn_path); ++ ++ //stos ++ __ BIND(notBool); ++ __ add_simm16(T1, T3, (-1) * stos); ++ __ bne(T1, notShort); ++ __ ldh_signed(V0, T0, 0); ++ __ beq(R0, xreturn_path); ++ ++ //ctos ++ __ BIND(notShort); ++ __ add_simm16(T1, T3, (-1) * ctos); ++ __ bne(T1, notChar); ++ __ ldhu(V0, T0, 0); ++ __ beq(R0, xreturn_path); ++ ++ //atos ++ __ BIND(notChar); ++ __ add_simm16(T1, T3, (-1) * atos); ++ __ bne(T1, notObj); ++ //add for compressedoops ++ __ load_heap_oop(V0, Address(T0, 0)); ++ __ beq(R0, xreturn_path); ++ ++ //itos ++ __ BIND(notObj); ++#ifdef ASSERT ++ Label okay; ++ __ add_simm16(T1, T3, (-1) * itos); ++ __ beq(T1, okay); ++ __ stop("what type is this?"); ++ __ BIND(okay); ++#endif // ASSERT ++ __ ldw(V0, T0, 0); ++ ++ __ BIND(xreturn_path); ++ { ++ Label notVolatile; ++ __ beq(T11, notVolatile); ++ if(os::is_MP()) __ memb(); ++ __ BIND(notVolatile); ++ } ++ ++ // _ireturn/_areturn ++ __ move(SP, Rsender);// set sender's fp to SP ++ __ ret(); ++ ++ // generate a vanilla interpreter entry as the slow path ++ __ BIND(slow_path); ++ (void) generate_normal_entry(false); ++ } else { ++ (void) generate_normal_entry(false); ++ } ++ ++ return entry_point; ++} ++ ++// Method entry for java.lang.ref.Reference.get. ++address InterpreterGenerator::generate_Reference_get_entry(void) { ++#if INCLUDE_ALL_GCS ++ // Code: _aload_0, _getfield, _areturn ++ // parameter size = 1 ++ // ++ // The code that gets generated by this routine is split into 2 parts: ++ // 1. The "intrinsified" code for G1 (or any SATB based GC), ++ // 2. The slow path - which is an expansion of the regular method entry. ++ // ++ // Notes:- ++ // * In the G1 code we do not check whether we need to block for ++ // a safepoint. If G1 is enabled then we must execute the specialized ++ // code for Reference.get (except when the Reference object is null) ++ // so that we can log the value in the referent field with an SATB ++ // update buffer. ++ // If the code for the getfield template is modified so that the ++ // G1 pre-barrier code is executed when the current method is ++ // Reference.get() then going through the normal method entry ++ // will be fine. ++ // * The G1 code can, however, check the receiver object (the instance ++ // of java.lang.Reference) and jump to the slow path if null. If the ++ // Reference object is null then we obviously cannot fetch the referent ++ // and so we don't need to call the G1 pre-barrier. Thus we can use the ++ // regular method entry code to generate the NPE. ++ // ++ // This code is based on generate_accessor_enty. ++ // ++ // Rmethod: Method* ++ ++ // Rsender: senderSP must preserve for slow path, set SP to it on fast path (Rsender) ++ ++ address entry = __ pc(); ++ ++ const int referent_offset = java_lang_ref_Reference::referent_offset; ++ guarantee(referent_offset > 0, "referent offset not initialized"); ++ ++ if (UseG1GC) { ++ Label slow_path; ++ ++ // Check if local 0 != NULL ++ // If the receiver is null then it is OK to jump to the slow path. ++ __ ldl(V0, SP, 0); ++ ++ __ beq(V0, slow_path); ++ ++ // Generate the G1 pre-barrier code to log the value of ++ // the referent field in an SATB buffer. ++ ++ // Load the value of the referent field. ++ const Address field_address(V0, referent_offset); ++ __ load_heap_oop(V0, field_address); ++ ++ __ push(RA); ++ // Generate the G1 pre-barrier code to log the value of ++ // the referent field in an SATB buffer. ++ __ g1_write_barrier_pre(noreg /* obj */, ++ V0 /* pre_val */, ++ S2thread /* thread */, ++ Rmethod /* tmp */, ++ true /* tosca_live */, ++ true /* expand_call */); ++ __ pop(RA); ++ ++ __ addl(SP, Rsender, R0); // set sp to sender sp ++ __ ret(); ++ ++ // generate a vanilla interpreter entry as the slow path ++ __ BIND(slow_path); ++ (void) generate_normal_entry(false); ++ ++ return entry; ++ } ++#endif // INCLUDE_ALL_GCS ++ ++ // If G1 is not enabled then attempt to go through the accessor entry point ++ // Reference.get is an accessor ++ return generate_accessor_entry(); ++} ++ ++/** ++ * Method entry for static native methods: ++ * int java.util.zip.CRC32.update(int crc, int b) ++ */ ++address InterpreterGenerator::generate_CRC32_update_entry() { ++ if (UseCRC32Intrinsics) { ++ address entry = __ pc(); ++ ++ Label slow_path; ++ // If we need a safepoint check, generate full interpreter entry. ++ __ li(GP, SafepointSynchronize::address_of_state()); ++ __ ldw(AT, GP, 0); ++ __ move(GP, (SafepointSynchronize::_not_synchronized)); ++ __ bne(AT, GP, slow_path); ++ ++ // We don't generate local frame and don't align stack because ++ // we call stub code and there is no safepoint on this path. ++ // Load parameters ++ const Register crc = V0; // crc ++ const Register val = A0; // source java byte value ++ const Register tbl = A1; // scratch ++ ++ // Arguments are reversed on java expression stack ++ __ ldw(val, SP, 0); // byte value ++ __ ldw(crc, SP, wordSize); // Initial CRC ++ address stubAddr = StubRoutines::crc_table_addr(); ++ __ li(tbl, stubAddr); ++ __ ornot(crc, R0, crc); // ~crc ++ __ zapnot(crc, crc, 0xF); ++ __ update_byte_crc32(crc, val, tbl); ++ __ ornot(crc, R0, crc); // ~crc ++ __ zapnot(crc, crc, 0xF); ++ // result in V0 ++ // _areturn ++ __ addl(SP, Rsender, R0); // set sp to sender sp ++ __ ret(); ++ ++ // generate a vanilla native entry as the slow path ++ __ bind(slow_path); ++ ++ (void) generate_native_entry(false); ++ ++ return entry; ++ } ++ return generate_native_entry(false); ++} ++ ++/** ++ * Method entry for static native methods: ++ * int java.util.zip.CRC32.updateBytes(int crc, byte[] b, int off, int len) ++ * int java.util.zip.CRC32.updateByteBuffer(int crc, long buf, int off, int len) ++ */ ++address InterpreterGenerator::generate_CRC32_updateBytes_entry(AbstractInterpreter::MethodKind kind) { ++ if (UseCRC32Intrinsics) { ++ address entry = __ pc(); ++ ++ // // rbx,: Method* ++ // // r13: senderSP must preserved for slow path, set SP to it on fast path ++ // // If we need a safepoint check, generate full interpreter entry. ++ // We don't generate local frame and don't align stack because ++ // // we call stub code and there is no safepoint on this path. ++ Label slow_path; ++ __ li(GP, SafepointSynchronize::address_of_state()); ++ __ ldw(AT, GP, 0); ++ __ move(GP, (SafepointSynchronize::_not_synchronized)); ++ __ bne(AT, GP, slow_path); ++ ++ // Load parameters ++ const Register crc = A0; // crc ++ const Register buf = A1; // source java byte array address ++ const Register len = A2; // length ++ const Register off = len; // offset (never overlaps with 'len') ++ const Register tmp = A3; ++ const Register tmp3 = A4; ++ ++ // // Arguments are reversed on java expression stack ++ // // Calculate address of start element ++ if (kind == Interpreter::java_util_zip_CRC32_updateByteBuffer) { ++ __ ldl(buf, SP, 2 * wordSize); // long buf ++ __ ldw(off, SP, 1 * wordSize); // offset ++ __ zapnot(off, off, 0xF); ++ __ addl(buf, buf, off); // + offset ++ __ ldw(crc, SP, 4 * wordSize); // Initial CRC ++ } else { ++ __ ldw(off, SP, 1 * wordSize); ++ __ zapnot(off, off, 0xF); ++ __ ldl(buf, SP, 2 * wordSize); // byte[] array ++ __ addl(buf, buf, arrayOopDesc::base_offset_in_bytes(T_BYTE)); // + header size ++ __ addl(buf, buf, off); // offset ++ __ ldw(crc, SP, 3 * wordSize); // Initial CRC ++ } ++ // Can now load 'len' since we're finished with 'off' ++ __ ldw(len, SP, 0 * wordSize); ++ __ zapnot(len, len, 0xF); ++ __ enter(); ++ if (UseCRC32) { ++ __ kernel_crc32(crc, buf, len, tmp, tmp3); ++ } else { ++ __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::updateBytesCRC32), 3); ++ } ++ // _areturn ++ __ leave(); ++ __ addl(SP, Rsender, R0); // set sp to sender sp ++ __ ret(); ++ // generate a vanilla native entry as the slow path ++ __ bind(slow_path); ++ (void) generate_native_entry(false); ++ ++ return entry; ++ } ++ return generate_native_entry(false); ++} ++ ++// Interpreter stub for calling a native method. (asm interpreter) ++// This sets up a somewhat different looking stack for calling the ++// native method than the typical interpreter frame setup. ++address InterpreterGenerator::generate_native_entry(bool synchronized) { ++ // determine code generation flags ++ bool inc_counter = UseCompiler || CountCompiledCalls; ++ // Rsender: sender's sp ++ // Rmethod: Method* ++ address entry_point = __ pc(); ++ ++#ifndef CORE ++ const Address invocation_counter(Rmethod,in_bytes(MethodCounters::invocation_counter_offset() + ++ InvocationCounter::counter_offset())); ++#endif ++ ++ // get parameter size (always needed) ++ // the size in the java stack ++ __ ldl(V0, Rmethod, in_bytes(Method::const_offset())); ++ __ ldhu(V0, V0, in_bytes(ConstMethod::size_of_parameters_offset())); ++ ++ // native calls don't need the stack size check since they have no expression stack ++ // and the arguments are already on the stack and we only add a handful of words ++ // to the stack ++ ++ // Rmethod: Method* ++ // V0: size of parameters ++ // Layout of frame at this point ++ // ++ // [ argument word n-1 ] <--- sp ++ // ... ++ // [ argument word 0 ] ++ ++ // for natives the size of locals is zero ++ ++ // compute beginning of parameters (S1) ++ __ slll(LVP, V0, Address::times_8); ++ __ add_simm16(LVP, LVP, (-1) * wordSize); ++ __ addl(LVP, LVP, SP); ++ ++ ++ // add 2 zero-initialized slots for native calls ++ __ add_simm16(SP, SP, (-2) * wordSize); ++ __ stl(R0, SP, 1 * wordSize); // slot for native oop temp offset (setup via runtime) ++ __ stl(R0, SP, 0 * wordSize); // slot for static native result handler3 (setup via runtime) ++ ++ // Layout of frame at this point ++ // [ method holder mirror ] <--- sp ++ // [ result type info ] ++ // [ argument word n-1 ] <--- T0 ++ // ... ++ // [ argument word 0 ] <--- LVP ++ ++ ++#ifndef CORE ++ if (inc_counter) __ ldw_signed(T3, invocation_counter); // (pre-)fetch invocation count ++#endif ++ ++ // initialize fixed part of activation frame ++ generate_fixed_frame(true); ++ // after this function, the layout of frame is as following ++ // ++ // [ monitor block top ] <--- sp ( the top monitor entry ) ++ // [ byte code pointer (0) ] (if native, bcp = 0) ++ // [ constant pool cache ] ++ // [ Method* ] ++ // [ locals offset ] ++ // [ sender's sp ] ++ // [ sender's fp ] ++ // [ return address ] <--- fp ++ // [ method holder mirror ] ++ // [ result type info ] ++ // [ argumnet word n-1 ] <--- sender's sp ++ // ... ++ // [ argument word 0 ] <--- S1 ++ ++ ++ // make sure method is native & not abstract ++#ifdef ASSERT ++ __ ldw(T0, Rmethod, in_bytes(Method::access_flags_offset())); ++ { ++ Label L; ++// __ and_uimm8(AT, T0, JVM_ACC_NATIVE); ++ __ ldi(GP, R0, JVM_ACC_NATIVE); ++ __ and_reg(AT, T0, GP); ++ __ bne(AT, L); ++ __ stop("tried to execute native method as non-native"); ++ __ BIND(L); ++ } ++ { ++ Label L; ++// __ and_uimm8(AT, T0, JVM_ACC_ABSTRACT); ++ __ ldi(GP, R0, JVM_ACC_ABSTRACT); ++ __ and_reg(AT, T0, GP); ++ __ beq(AT, L); ++ __ stop("tried to execute abstract method in interpreter"); ++ __ BIND(L); ++ } ++#endif ++ ++ // Since at this point in the method invocation the exception handler ++ // would try to exit the monitor of synchronized methods which hasn't ++ // been entered yet, we set the thread local variable ++ // _do_not_unlock_if_synchronized to true. The remove_activation will ++ // check this flag. ++ Register thread = S2thread; ++ __ move(AT, (int)true); ++ __ stb(AT, thread, in_bytes(JavaThread::do_not_unlock_if_synchronized_offset())); ++ ++#ifndef CORE ++ // increment invocation count & check for overflow ++ Label invocation_counter_overflow; ++ if (inc_counter) { ++ generate_counter_incr(&invocation_counter_overflow, NULL, NULL); ++ } ++ ++ Label continue_after_compile; ++ __ BIND(continue_after_compile); ++#endif // CORE ++ ++ bang_stack_shadow_pages(true); ++ ++ // reset the _do_not_unlock_if_synchronized flag ++ __ stb(R0, thread, in_bytes(JavaThread::do_not_unlock_if_synchronized_offset())); ++ ++ // check for synchronized methods ++ // Must happen AFTER invocation_counter check and stack overflow check, ++ // so method is not locked if overflows. ++ if (synchronized) { ++ lock_method(); ++ } else { ++ // no synchronization necessary ++#ifdef ASSERT ++ { ++ Label L; ++ __ ldw(T0, Rmethod, in_bytes(Method::access_flags_offset())); ++ __ and_imm8(AT, T0, JVM_ACC_SYNCHRONIZED); ++ __ beq(AT, L); ++ __ stop("method needs synchronization"); ++ __ BIND(L); ++ } ++#endif ++ } ++ ++ // after method_lock, the layout of frame is as following ++ // ++ // [ monitor entry ] <--- sp ++ // ... ++ // [ monitor entry ] ++ // [ monitor block top ] ( the top monitor entry ) ++ // [ byte code pointer (0) ] (if native, bcp = 0) ++ // [ constant pool cache ] ++ // [ Method* ] ++ // [ locals offset ] ++ // [ sender's sp ] ++ // [ sender's fp ] ++ // [ return address ] <--- fp ++ // [ method holder mirror ] ++ // [ result type info ] ++ // [ argumnet word n-1 ] <--- ( sender's sp ) ++ // ... ++ // [ argument word 0 ] <--- S1 ++ ++ // start execution ++#ifdef ASSERT ++ { ++ Label L; ++ __ ldl(AT, FP, frame::interpreter_frame_monitor_block_top_offset * wordSize); ++ __ beq(AT, SP, L); ++ __ stop("broken stack frame setup in interpreter in asm"); ++ __ BIND(L); ++ } ++#endif ++ ++ // jvmti/jvmpi support ++ __ notify_method_entry(); ++ ++ // work registers ++ const Register method = Rmethod; ++ //const Register thread = T2; ++ const Register t = RT4; ++ ++ __ get_method(method); ++ //__ verify_oop(method); ++ { ++ Label L, Lstatic; ++ __ ldl(t,method,in_bytes(Method::const_offset())); ++ __ ldhu(t, t, in_bytes(ConstMethod::size_of_parameters_offset())); ++ // SW64 ABI: caller does not reserve space for the register auguments. ++ // A0 and A1(if needed) ++ __ ldw(AT, Rmethod, in_bytes(Method::access_flags_offset())); ++ __ and_imm8(AT, AT, JVM_ACC_STATIC); ++ __ beq(AT, Lstatic); ++ __ addl(t, t, 1); ++ __ BIND(Lstatic); ++ __ add_simm16(t, t, -Argument::n_register_parameters + 1); ++ __ ble(t, L); ++ __ slll(t, t, Address::times_8); ++ __ subl(SP, SP, t); ++ __ BIND(L); ++ } ++ __ move(AT, -(StackAlignmentInBytes)); ++ __ and_reg(SP, SP, AT); ++ __ move(AT, SP); ++ // [ ] <--- sp ++ // ... (size of parameters - 8 ) ++ // [ monitor entry ] ++ // ... ++ // [ monitor entry ] ++ // [ monitor block top ] ( the top monitor entry ) ++ // [ byte code pointer (0) ] (if native, bcp = 0) ++ // [ constant pool cache ] ++ // [ Method* ] ++ // [ locals offset ] ++ // [ sender's sp ] ++ // [ sender's fp ] ++ // [ return address ] <--- fp ++ // [ method holder mirror ] ++ // [ result type info ] ++ // [ argumnet word n-1 ] <--- ( sender's sp ) ++ // ... ++ // [ argument word 0 ] <--- LVP ++ ++ // get signature handler ++ { ++ Label L; ++ __ ldl(T12, method, in_bytes(Method::signature_handler_offset())); ++ __ bne(T12, L); ++ __ call_VM(NOREG, CAST_FROM_FN_PTR(address, ++ InterpreterRuntime::prepare_native_call), method); ++ __ get_method(method); ++ __ ldl(T12, method, in_bytes(Method::signature_handler_offset())); ++ __ BIND(L); ++ } ++ ++ // call signature handler ++ // from: begin of parameters ++ assert(InterpreterRuntime::SignatureHandlerGenerator::from() == LVP, "adjust this code"); ++ // to: current sp ++ assert(InterpreterRuntime::SignatureHandlerGenerator::to () == SP, "adjust this code"); ++ // temp: T3 ++ assert(InterpreterRuntime::SignatureHandlerGenerator::temp() == t , "adjust this code"); ++ ++ __ call(T12); ++ __ get_method(method); ++ ++ // ++ // if native function is static, and its second parameter has type length of double word, ++ // and first parameter has type length of word, we have to reserve one word ++ // if native function is not static, and its third parameter has type length of double word, ++ // and second parameter has type length of word, we have to reserve one word for the second ++ // parameter. ++ // ++ ++ ++ // result handler is in V0 ++ // set result handler ++ __ stl(V0, FP, (frame::interpreter_frame_result_handler_offset)*wordSize); ++ __ memb();// Acquire signature handler before trying to fetch the native entry point and klass mirror. ?? ++ ++ // pass mirror handle if static call ++ { ++ Label L; ++ const int mirror_offset = in_bytes(Klass::java_mirror_offset()); ++ __ ldw(t, method, in_bytes(Method::access_flags_offset())); ++ __ and_imm8(AT, t, JVM_ACC_STATIC); ++ __ beq(AT, L); ++ ++ // get mirror ++ __ ldl(t, method, in_bytes(Method:: const_offset())); ++ __ ldl(t, t, in_bytes(ConstMethod::constants_offset())); //?? ++ __ ldl(t, t, ConstantPool::pool_holder_offset_in_bytes()); ++ __ ldl(t, t, mirror_offset); ++ // copy mirror into activation frame ++ //__ sw(t, FP, frame::interpreter_frame_oop_temp_offset * wordSize); ++ // pass handle to mirror ++ __ stl(t, FP, frame::interpreter_frame_oop_temp_offset * wordSize); ++ __ add_simm16(t, FP, frame::interpreter_frame_oop_temp_offset * wordSize); ++ __ move(A1, t); ++ __ BIND(L); ++ } ++ ++ // [ mthd holder mirror ptr ] <--- sp --------------------| (only for static method) ++ // [ ] | ++ // ... size of parameters(or +1) | ++ // [ monitor entry ] | ++ // ... | ++ // [ monitor entry ] | ++ // [ monitor block top ] ( the top monitor entry ) | ++ // [ byte code pointer (0) ] (if native, bcp = 0) | ++ // [ constant pool cache ] | ++ // [ Method* ] | ++ // [ locals offset ] | ++ // [ sender's sp ] | ++ // [ sender's fp ] | ++ // [ return address ] <--- fp | ++ // [ method holder mirror ] <----------------------------| ++ // [ result type info ] ++ // [ argumnet word n-1 ] <--- ( sender's sp ) ++ // ... ++ // [ argument word 0 ] <--- S1 ++ ++ // get native function entry point ++ { Label L; ++ __ ldl(T12, method, in_bytes(Method::native_function_offset())); ++ __ li(T4, SharedRuntime::native_method_throw_unsatisfied_link_error_entry()); ++ __ bne(T4, T12, L); ++ __ call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::prepare_native_call), method); ++ __ get_method(method); ++ // __ verify_oop(method); ++ __ ldl(T12, method, in_bytes(Method::native_function_offset())); ++ __ BIND(L); ++ } ++ ++ // pass JNIEnv ++ // native function in T12 ++ __ add_simm16(t, thread, in_bytes(JavaThread::jni_environment_offset())); ++ __ move(A0, t); ++ // [ jni environment ] <--- sp ++ // [ mthd holder mirror ptr ] ---------------------------->| (only for static method) ++ // [ ] | ++ // ... size of parameters | ++ // [ monitor entry ] | ++ // ... | ++ // [ monitor entry ] | ++ // [ monitor block top ] ( the top monitor entry ) | ++ // [ byte code pointer (0) ] (if native, bcp = 0) | ++ // [ constant pool cache ] | ++ // [ Method* ] | ++ // [ locals offset ] | ++ // [ sender's sp ] | ++ // [ sender's fp ] | ++ // [ return address ] <--- fp | ++ // [ method holder mirror ] <----------------------------| ++ // [ result type info ] ++ // [ argumnet word n-1 ] <--- ( sender's sp ) ++ // ... ++ // [ argument word 0 ] <--- S1 ++ ++ // set_last_Java_frame_before_call ++ __ stl(FP, thread, in_bytes(JavaThread::last_Java_fp_offset())); ++ // Change state to native (we save the return address in the thread, since it might not ++ // be pushed on the stack when we do a a stack traversal). It is enough that the pc() ++ // points into the right code segment. It does not have to be the correct return pc. ++ __ li(t, __ pc()); ++ __ stl(t, thread, in_bytes(JavaThread::last_Java_pc_offset())); ++ __ stl(SP, thread, in_bytes(JavaThread::last_Java_sp_offset())); ++ ++ // change thread state ++#ifdef ASSERT ++ { ++ Label L; ++ __ ldw(t, thread, in_bytes(JavaThread::thread_state_offset())); ++ __ add_simm16(t, t, (-1) * _thread_in_Java); ++ __ beq(t, L); ++ __ stop("Wrong thread state in native stub"); ++ __ BIND(L); ++ } ++#endif ++ ++ __ move(t, _thread_in_native); ++ __ stw(t, thread, in_bytes(JavaThread::thread_state_offset())); ++ ++ // call native method ++ __ call(T12); ++ // result potentially in V0 or F0 ++ ++ ++ // via _last_native_pc and not via _last_jave_sp ++ // NOTE: the order of theses push(es) is known to frame::interpreter_frame_result. ++ // If the order changes or anything else is added to the stack the code in ++ // interpreter_frame_result will have to be changed. ++ // save return value to keep the value from being destroyed by other calls ++ __ push_d(F0); ++ __ push(V0); ++ ++ // change thread state ++ __ get_thread(thread); ++ __ move(t, _thread_in_native_trans); ++ __ stw(t, thread, in_bytes(JavaThread::thread_state_offset())); ++ ++ if( os::is_MP() ) __ memb(); // Force this write out before the read below ++ ++ // check for safepoint operation in progress and/or pending suspend requests ++ { Label Continue; ++ ++ // Don't use call_VM as it will see a possible pending exception and forward it ++ // and never return here preventing us from clearing _last_native_pc down below. ++ // Also can't use call_VM_leaf either as it will check to see if BCP & LVP are ++ // preserved and correspond to the bcp/locals pointers. So we do a runtime call ++ // by hand. ++ // ++ Label L; ++ __ li(AT, SafepointSynchronize::address_of_state()); ++ __ ldw(AT, AT, 0); ++ __ bne(AT, L); ++ __ ldw(AT, thread, in_bytes(JavaThread::suspend_flags_offset())); ++ __ beq(AT, Continue); ++ __ BIND(L); ++ __ memb(); ++ __ move(A0, thread); ++ __ call(CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans), ++ relocInfo::runtime_call_type); ++ ++ //add for compressedoops ++ __ reinit_heapbase(); ++ __ BIND(Continue); ++ } ++ ++ // change thread state ++ __ move(t, _thread_in_Java); ++ __ stw(t, thread, in_bytes(JavaThread::thread_state_offset())); ++ __ reset_last_Java_frame(thread, true); ++ ++ // reset handle block ++ __ ldl(t, thread, in_bytes(JavaThread::active_handles_offset())); ++ __ stw(R0, t, JNIHandleBlock::top_offset_in_bytes()); ++ ++ // If result was an oop then unbox and save it in the frame ++ { ++ Label no_oop; ++ __ ldl(AT, FP, frame::interpreter_frame_result_handler_offset*wordSize); ++ __ li(T0, AbstractInterpreter::result_handler(T_OBJECT)); ++ __ bne(AT, T0, no_oop); ++ __ pop(V0); ++ // Unbox oop result, e.g. JNIHandles::resolve value. ++ __ resolve_jobject(V0, thread, AT); ++ __ stl(V0, FP, (frame::interpreter_frame_oop_temp_offset)*wordSize); ++ // keep stack depth as expected by pushing oop which will eventually be discarded ++ __ push(V0); ++ __ BIND(no_oop); ++ } ++ { ++ Label no_reguard; ++ __ ldw(t, thread, in_bytes(JavaThread::stack_guard_state_offset())); ++ __ move(AT,(int) JavaThread::stack_guard_yellow_disabled); ++ __ bne(t, AT, no_reguard); ++ __ pushad(); ++ __ move(S5_heapbase, SP); ++ __ move(AT, -StackAlignmentInBytes); ++ __ and_reg(SP, SP, AT); ++ __ call(CAST_FROM_FN_PTR(address, SharedRuntime::reguard_yellow_pages), relocInfo::runtime_call_type); ++ __ move(SP, S5_heapbase); ++ __ popad(); ++ //add for compressedoops ++ __ reinit_heapbase(); ++ __ BIND(no_reguard); ++ } ++ // restore BCP to have legal interpreter frame, ++ // i.e., bci == 0 <=> BCP == code_base() ++ // Can't call_VM until bcp is within reasonable. ++ __ get_method(method); // method is junk from thread_in_native to now. ++ //__ verify_oop(method); ++ __ ldl(BCP, method, in_bytes(Method::const_offset())); ++ __ lea(BCP, Address(BCP, in_bytes(ConstMethod::codes_offset()))); ++ // handle exceptions (exception handling will handle unlocking!) ++ { ++ Label L; ++ __ ldw(t, thread, in_bytes(Thread::pending_exception_offset())); ++ __ beq(t, L); ++ // Note: At some point we may want to unify this with the code used in ++ // call_VM_base(); ++ // i.e., we should use the StubRoutines::forward_exception code. For now this ++ // doesn't work here because the sp is not correctly set at this point. ++ __ MacroAssembler::call_VM(noreg, CAST_FROM_FN_PTR(address, ++ InterpreterRuntime::throw_pending_exception)); ++ __ should_not_reach_here(); ++ __ BIND(L); ++ } ++ ++ // do unlocking if necessary ++ { ++ Label L; ++ __ ldw(t, method, in_bytes(Method::access_flags_offset())); ++ __ and_imm8(t, t, JVM_ACC_SYNCHRONIZED); ++ __ beq(t, L); ++ // the code below should be shared with interpreter macro assembler implementation ++ { ++ Label unlock; ++ // BasicObjectLock will be first in list, ++ // since this is a synchronized method. However, need ++ // to check that the object has not been unlocked by ++ // an explicit monitorexit bytecode. ++ __ add_simm16(c_rarg0, FP, frame::interpreter_frame_initial_sp_offset ++ * wordSize - (int)sizeof(BasicObjectLock)); ++ // address of first monitor ++ ++ __ ldl(t, c_rarg0, BasicObjectLock::obj_offset_in_bytes()); ++ __ bne(t, unlock); ++ ++ // Entry already unlocked, need to throw exception ++ __ MacroAssembler::call_VM(NOREG, CAST_FROM_FN_PTR(address, ++ InterpreterRuntime::throw_illegal_monitor_state_exception)); ++ __ should_not_reach_here(); ++ ++ __ BIND(unlock); ++ __ unlock_object(c_rarg0); ++ } ++ __ BIND(L); ++ } ++ ++ // jvmti/jvmpi support ++ // Note: This must happen _after_ handling/throwing any exceptions since ++ // the exception handler code notifies the runtime of method exits ++ // too. If this happens before, method entry/exit notifications are ++ // not properly paired (was bug - gri 11/22/99). ++ __ notify_method_exit(false, vtos, InterpreterMacroAssembler::NotifyJVMTI ); ++ ++ // restore potential result in V0, ++ // call result handler to restore potential result in ST0 & handle result ++ __ pop(V0); ++ __ pop_d(); ++ __ ldl(t, FP, (frame::interpreter_frame_result_handler_offset) * wordSize); ++ __ call(t); ++ ++ ++ // remove activation ++ __ ldl(SP, FP, frame::interpreter_frame_sender_sp_offset * wordSize); // get sender sp ++ __ ldl(RA, FP, frame::interpreter_frame_return_addr_offset * wordSize); // get return address ++ __ ldl(FP, FP, frame::interpreter_frame_sender_fp_offset * wordSize); // restore sender's fp ++ __ ret(); ++ ++#ifndef CORE ++ if (inc_counter) { ++ // Handle overflow of counter and compile method ++ __ BIND(invocation_counter_overflow); ++ generate_counter_overflow(&continue_after_compile); ++ // entry_point is the beginning of this ++ // function and checks again for compiled code ++ } ++#endif ++ return entry_point; ++} ++ ++// ++// Generic interpreted method entry to (asm) interpreter ++// ++// Layout of frame just at the entry ++// ++// [ argument word n-1 ] <--- sp ++// ... ++// [ argument word 0 ] ++// assume Method* in Rmethod before call this method. ++// prerequisites to the generated stub : the callee Method* in Rmethod ++// note you must save the caller bcp before call the generated stub ++// ++address InterpreterGenerator::generate_normal_entry(bool synchronized) { ++ // determine code generation flags ++ bool inc_counter = UseCompiler || CountCompiledCalls; ++ ++ // Rmethod: Method* ++ // Rsender: sender 's sp ++ address entry_point = __ pc(); ++ ++ const Address invocation_counter(Rmethod, ++ in_bytes(MethodCounters::invocation_counter_offset() + InvocationCounter::counter_offset())); ++ ++ // get parameter size (always needed) ++ __ ldl(T3, Rmethod, in_bytes(Method::const_offset())); //T3 --> Rmethod._constMethod ++ __ ldhu(V0, T3, in_bytes(ConstMethod::size_of_parameters_offset())); ++ ++ // Rmethod: Method* ++ // V0: size of parameters ++ // Rsender: sender 's sp ,could be different frome sp+ wordSize if we call via c2i ++ // get size of locals in words to T2 ++ __ ldhu(T2, T3, in_bytes(ConstMethod::size_of_locals_offset())); ++ __ subl(T2, T2, V0); ++ ++ // see if we've got enough room on the stack for locals plus overhead. ++ // Layout of frame at this point ++ // ++ // [ argument word n-1 ] <--- sp ++ // ... ++ // [ argument word 0 ] ++ generate_stack_overflow_check(); ++ // after this function, the layout of frame does not change ++ ++ // compute beginning of parameters (LVP) ++ __ slll(LVP, V0, LogBytesPerWord); ++ __ add_simm16(LVP, LVP, (-1) * wordSize); ++ __ addl(LVP, LVP, SP); ++ ++ // T2 - # of additional locals ++ // allocate space for locals ++ // explicitly initialize locals ++ { ++ Label exit, loop; ++ __ beq(T2, exit); ++ ++ __ BIND(loop); ++ __ stl(R0, SP, -1 * wordSize); // initialize local variables ++ __ subl(T2, T2, 1); // until everything initialized ++ ++ __ add_simm16(SP, SP, (-1) * wordSize); ++ __ bne(T2, loop); ++ __ BIND(exit); ++ } ++ ++ // ++ // [ local var m-1 ] <--- sp ++ // ... ++ // [ local var 0 ] ++ // [ argument word n-1 ] <--- T0? ++ // ... ++ // [ argument word 0 ] <--- LVP ++ ++ // initialize fixed part of activation frame ++ ++ generate_fixed_frame(false); ++ ++ ++ // after this function, the layout of frame is as following ++ // ++ // [ monitor block top ] <--- sp ( the top monitor entry ) ++ // [ byte code pointer ] (if native, bcp = 0) ++ // [ constant pool cache ] ++ // [ Method* ] ++ // [ locals offset ] ++ // [ sender's sp ] ++ // [ sender's fp ] <--- fp ++ // [ return address ] ++ // [ local var m-1 ] ++ // ... ++ // [ local var 0 ] ++ // [ argumnet word n-1 ] <--- ( sender's sp ) ++ // ... ++ // [ argument word 0 ] <--- LVP ++ ++ ++ // make sure method is not native & not abstract ++#ifdef ASSERT ++ __ ldl(AT, Rmethod, in_bytes(Method::access_flags_offset())); ++ { ++ Label L; ++ __ ldi(GP, R0, JVM_ACC_NATIVE); ++ __ and_reg(T2, AT, GP); ++ __ beq(T2, L); ++ __ stop("tried to execute native method as non-native"); ++ __ BIND(L); ++ } ++ { ++ Label L; ++ __ ldi(GP, R0, JVM_ACC_ABSTRACT); ++ __ and_reg(T2, AT, GP); ++ __ beq(T2, L); ++ __ stop("tried to execute abstract method in interpreter"); ++ __ BIND(L); ++ } ++#endif ++ ++ // Since at this point in the method invocation the exception handler ++ // would try to exit the monitor of synchronized methods which hasn't ++ // been entered yet, we set the thread local variable ++ // _do_not_unlock_if_synchronized to true. The remove_activation will ++ // check this flag. ++ ++ Register thread = S2thread; ++ __ move(AT, (int)true); ++ __ stb(AT, thread, in_bytes(JavaThread::do_not_unlock_if_synchronized_offset())); ++ ++#ifndef CORE ++ ++ // mdp : T11 ++ // tmp1: T12 ++ // tmp2: T2 ++ __ profile_parameters_type(T11, T12, T2); ++ ++ // increment invocation count & check for overflow ++ Label invocation_counter_overflow; ++ Label profile_method; ++ Label profile_method_continue; ++ if (inc_counter) { ++ generate_counter_incr(&invocation_counter_overflow, ++ &profile_method, ++ &profile_method_continue); ++ if (ProfileInterpreter) { ++ __ BIND(profile_method_continue); ++ } ++ } ++ ++ Label continue_after_compile; ++ __ BIND(continue_after_compile); ++ ++#endif // CORE ++ ++ bang_stack_shadow_pages(false); ++ ++ // reset the _do_not_unlock_if_synchronized flag ++ __ stb(R0, thread, in_bytes(JavaThread::do_not_unlock_if_synchronized_offset())); ++ ++ // check for synchronized methods ++ // Must happen AFTER invocation_counter check and stack overflow check, ++ // so method is not locked if overflows. ++ // ++ if (synchronized) { ++ // Allocate monitor and lock method ++ lock_method(); ++ } else { ++ // no synchronization necessary ++#ifdef ASSERT ++ { Label L; ++ __ ldw(AT, Rmethod, in_bytes(Method::access_flags_offset())); ++ __ and_imm8(T2, AT, JVM_ACC_SYNCHRONIZED); ++ __ beq(T2, L); ++ __ stop("method needs synchronization"); ++ __ BIND(L); ++ } ++#endif ++ } ++ ++ // layout of frame after lock_method ++ // [ monitor entry ] <--- sp ++ // ... ++ // [ monitor entry ] ++ // [ monitor block top ] ( the top monitor entry ) ++ // [ byte code pointer ] (if native, bcp = 0) ++ // [ constant pool cache ] ++ // [ Method* ] ++ // [ locals offset ] ++ // [ sender's sp ] ++ // [ sender's fp ] ++ // [ return address ] <--- fp ++ // [ local var m-1 ] ++ // ... ++ // [ local var 0 ] ++ // [ argumnet word n-1 ] <--- ( sender's sp ) ++ // ... ++ // [ argument word 0 ] <--- LVP ++ ++ ++ // start execution ++#ifdef ASSERT ++ { ++ Label L; ++ __ ldl(AT, FP, frame::interpreter_frame_monitor_block_top_offset * wordSize); ++ __ beq(AT, SP, L); ++ __ stop("broken stack frame setup in interpreter in native"); ++ __ BIND(L); ++ } ++#endif ++ ++ // jvmti/jvmpi support ++ __ notify_method_entry(); ++ ++ __ dispatch_next(vtos); ++ ++ // invocation counter overflow ++ if (inc_counter) { ++ if (ProfileInterpreter) { ++ // We have decided to profile this method in the interpreter ++ __ BIND(profile_method); ++ __ call_VM(noreg, CAST_FROM_FN_PTR(address, ++ InterpreterRuntime::profile_method)); ++ __ set_method_data_pointer_for_bcp(); ++ __ get_method(Rmethod); ++ __ beq(R0, profile_method_continue); ++ } ++ // Handle overflow of counter and compile method ++ __ BIND(invocation_counter_overflow); ++ generate_counter_overflow(&continue_after_compile); ++ } ++ ++ return entry_point; ++} ++ ++// Entry points ++// ++// Here we generate the various kind of entries into the interpreter. ++// The two main entry type are generic bytecode methods and native ++// call method. These both come in synchronized and non-synchronized ++// versions but the frame layout they create is very similar. The ++// other method entry types are really just special purpose entries ++// that are really entry and interpretation all in one. These are for ++// trivial methods like accessor, empty, or special math methods. ++// ++// When control flow reaches any of the entry types for the interpreter ++// the following holds -> ++// ++// Arguments: ++// ++// Rmethod: Method* ++// V0: receiver ++// ++// ++// Stack layout immediately at entry ++// ++// [ parameter n-1 ] <--- sp ++// ... ++// [ parameter 0 ] ++// [ expression stack ] (caller's java expression stack) ++ ++// Assuming that we don't go to one of the trivial specialized entries ++// the stack will look like below when we are ready to execute the ++// first bytecode (or call the native routine). The register usage ++// will be as the template based interpreter expects (see ++// interpreter_SW64.hpp). ++// ++// local variables follow incoming parameters immediately; i.e. ++// the return address is moved to the end of the locals). ++// ++// [ monitor entry ] <--- sp ++// ... ++// [ monitor entry ] ++// [ monitor block top ] ( the top monitor entry ) ++// [ byte code pointer ] (if native, bcp = 0) ++// [ constant pool cache ] ++// [ Method* ] ++// [ locals offset ] ++// [ sender's sp ] ++// [ sender's fp ] ++// [ return address ] <--- fp ++// [ local var m-1 ] ++// ... ++// [ local var 0 ] ++// [ argumnet word n-1 ] <--- ( sender's sp ) ++// ... ++// [ argument word 0 ] <--- S1 ++ ++address AbstractInterpreterGenerator::generate_method_entry( ++ AbstractInterpreter::MethodKind kind) { ++ // determine code generation flags ++ bool synchronized = false; ++ address entry_point = NULL; ++ switch (kind) { ++ case Interpreter::zerolocals : ++ break; ++ case Interpreter::zerolocals_synchronized: ++ synchronized = true; ++ break; ++ case Interpreter::native : ++ entry_point = ((InterpreterGenerator*)this)->generate_native_entry(false); ++ break; ++ case Interpreter::native_synchronized : ++ entry_point = ((InterpreterGenerator*)this)->generate_native_entry(true); ++ break; ++ case Interpreter::empty : ++ entry_point = ((InterpreterGenerator*)this)->generate_empty_entry(); ++ break; ++ case Interpreter::accessor : ++ entry_point = ((InterpreterGenerator*)this)->generate_accessor_entry(); ++ break; ++ case Interpreter::abstract : ++ entry_point = ((InterpreterGenerator*)this)->generate_abstract_entry(); ++ break; ++ ++ case Interpreter::java_lang_math_sin : // fall thru ++ case Interpreter::java_lang_math_cos : // fall thru ++ case Interpreter::java_lang_math_tan : // fall thru ++ case Interpreter::java_lang_math_log : // fall thru ++ case Interpreter::java_lang_math_log10 : // fall thru ++ case Interpreter::java_lang_math_pow : // fall thru ++ case Interpreter::java_lang_math_exp : break; ++ case Interpreter::java_lang_math_abs : // fall thru ++ case Interpreter::java_lang_math_sqrt : ++ entry_point = ((InterpreterGenerator*)this)->generate_math_entry(kind); break; ++ case Interpreter::java_lang_ref_reference_get: ++ entry_point = ((InterpreterGenerator*)this)->generate_Reference_get_entry(); break; ++ case Interpreter::java_util_zip_CRC32_update ++ : entry_point = ((InterpreterGenerator*)this)->generate_CRC32_update_entry(); break; ++ case Interpreter::java_util_zip_CRC32_updateBytes ++ : // fall thru ++ case Interpreter::java_util_zip_CRC32_updateByteBuffer ++ : entry_point = ((InterpreterGenerator*)this)->generate_CRC32_updateBytes_entry(kind); break; ++ default: ++ fatal(err_msg("unexpected method kind: %d", kind)); ++ break; ++ } ++ if (entry_point) return entry_point; ++ ++ return ((InterpreterGenerator*)this)->generate_normal_entry(synchronized); ++} ++ ++// These should never be compiled since the interpreter will prefer ++// the compiled version to the intrinsic version. ++bool AbstractInterpreter::can_be_compiled(methodHandle m) { ++ switch (method_kind(m)) { ++ case Interpreter::java_lang_math_sin : // fall thru ++ case Interpreter::java_lang_math_cos : // fall thru ++ case Interpreter::java_lang_math_tan : // fall thru ++ case Interpreter::java_lang_math_abs : // fall thru ++ case Interpreter::java_lang_math_log : // fall thru ++ case Interpreter::java_lang_math_log10 : // fall thru ++ case Interpreter::java_lang_math_sqrt : // fall thru ++ case Interpreter::java_lang_math_pow : // fall thru ++ case Interpreter::java_lang_math_exp : ++ return false; ++ default: ++ return true; ++ } ++} ++ ++// How much stack a method activation needs in words. ++int AbstractInterpreter::size_top_interpreter_activation(Method* method) { ++ ++ const int entry_size = frame::interpreter_frame_monitor_size(); ++ ++ // total overhead size: entry_size + (saved fp thru expr stack bottom). ++ // be sure to change this if you add/subtract anything to/from the overhead area ++ const int overhead_size = -(frame::interpreter_frame_initial_sp_offset) + entry_size; ++ ++ const int stub_code = 6; // see generate_call_stub ++ // return overhead_size + method->max_locals() + method->max_stack() + stub_code; ++ const int method_stack = (method->max_locals() + method->max_stack()) * ++ Interpreter::stackElementWords; ++ return overhead_size + method_stack + stub_code; ++} ++ ++void AbstractInterpreter::layout_activation(Method* method, ++ int tempcount, ++ int popframe_extra_args, ++ int moncount, ++ int caller_actual_parameters, ++ int callee_param_count, ++ int callee_locals, ++ frame* caller, ++ frame* interpreter_frame, ++ bool is_top_frame, ++ bool is_bottom_frame) { ++ // Note: This calculation must exactly parallel the frame setup ++ // in AbstractInterpreterGenerator::generate_method_entry. ++ // If interpreter_frame!=NULL, set up the method, locals, and monitors. ++ // The frame interpreter_frame, if not NULL, is guaranteed to be the ++ // right size, as determined by a previous call to this method. ++ // It is also guaranteed to be walkable even though it is in a skeletal state ++ ++ // fixed size of an interpreter frame: ++ ++ int max_locals = method->max_locals() * Interpreter::stackElementWords; ++ int extra_locals = (method->max_locals() - method->size_of_parameters()) * Interpreter::stackElementWords; ++ ++#ifdef ASSERT ++ if (!EnableInvokeDynamic) { ++ // Probably, since deoptimization doesn't work yet. ++ assert(caller->unextended_sp() == interpreter_frame->interpreter_frame_sender_sp(), "Frame not properly walkable"); ++ } ++ assert(caller->sp() == interpreter_frame->interpreter_frame_sender_sp(), "Frame not properly walkable(2)"); ++#endif ++ ++ interpreter_frame->interpreter_frame_set_method(method); ++ // NOTE the difference in using sender_sp and interpreter_frame_sender_sp ++ // interpreter_frame_sender_sp is the original sp of the caller (the unextended_sp) ++ // and sender_sp is fp+8 ++ intptr_t* locals = interpreter_frame->sender_sp() + max_locals - 1; ++ ++#ifdef ASSERT ++ if (caller->is_interpreted_frame()) { ++ assert(locals < caller->fp() + frame::interpreter_frame_initial_sp_offset, "bad placement"); ++ } ++#endif ++ ++ interpreter_frame->interpreter_frame_set_locals(locals); ++ BasicObjectLock* montop = interpreter_frame->interpreter_frame_monitor_begin(); ++ BasicObjectLock* monbot = montop - moncount; ++ interpreter_frame->interpreter_frame_set_monitor_end(montop - moncount); ++ ++ //set last sp; ++ intptr_t* sp = (intptr_t*) monbot - tempcount*Interpreter::stackElementWords - ++ popframe_extra_args; ++ interpreter_frame->interpreter_frame_set_last_sp(sp); ++ // All frames but the initial interpreter frame we fill in have a ++ // value for sender_sp that allows walking the stack but isn't ++ // truly correct. Correct the value here. ++ // ++ // int extra_locals = method->max_locals() - method->size_of_parameters(); ++ if (extra_locals != 0 && ++ interpreter_frame->sender_sp() == interpreter_frame->interpreter_frame_sender_sp() ) { ++ interpreter_frame->set_interpreter_frame_sender_sp(caller->sp() + extra_locals); ++ } ++ *interpreter_frame->interpreter_frame_cache_addr() = method->constants()->cache(); ++} ++ ++//----------------------------------------------------------------------------- ++// Exceptions ++ ++void TemplateInterpreterGenerator::generate_throw_exception() { ++ // Entry point in previous activation (i.e., if the caller was ++ // interpreted) ++ Interpreter::_rethrow_exception_entry = __ pc(); ++ ++ // Restore sp to interpreter_frame_last_sp even though we are going ++ // to empty the expression stack for the exception processing. ++ __ stl(R0,FP, frame::interpreter_frame_last_sp_offset * wordSize); ++ ++ // V0: exception ++ // T4: return address/pc that threw exception ++ __ restore_bcp(); // BCP points to call/send ++ __ restore_locals(); ++ ++ //add for compressedoops ++ __ reinit_heapbase(); ++ // Entry point for exceptions thrown within interpreter code ++ Interpreter::_throw_exception_entry = __ pc(); ++ // expression stack is undefined here ++ // V0: exception ++ // BCP: exception bcp ++ __ verify_oop(V0); ++ ++ // expression stack must be empty before entering the VM in case of an exception ++ __ empty_expression_stack(); ++ // find exception handler address and preserve exception oop ++ __ move(A1, V0); ++ __ call_VM(T4, CAST_FROM_FN_PTR(address, InterpreterRuntime::exception_handler_for_exception), A1); ++ // V0: exception handler entry point ++ // T4: preserved exception oop ++ // S0: bcp for exception handler ++ __ add_simm16(SP, SP, (-1) * wordSize); ++ __ stl(T4, SP, 0); // push exception which is now the only value on the stack ++ __ jmp(V0); // jump to exception handler (may be _remove_activation_entry!) ++ ++ // If the exception is not handled in the current frame the frame is removed and ++ // the exception is rethrown (i.e. exception continuation is _rethrow_exception). ++ // ++ // Note: At this point the bci is still the bxi for the instruction which caused ++ // the exception and the expression stack is empty. Thus, for any VM calls ++ // at this point, GC will find a legal oop map (with empty expression stack). ++ ++ // In current activation ++ // V0: exception ++ // BCP: exception bcp ++ ++ // ++ // JVMTI PopFrame support ++ // ++ ++ Interpreter::_remove_activation_preserving_args_entry = __ pc(); ++ __ empty_expression_stack(); ++ // Set the popframe_processing bit in pending_popframe_condition indicating that we are ++ // currently handling popframe, so that call_VMs that may happen later do not trigger new ++ // popframe handling cycles. ++ Register thread = S2thread; ++ __ ldw(T3, thread, in_bytes(JavaThread::popframe_condition_offset())); ++ __ or_ins(T3, T3, JavaThread::popframe_processing_bit); ++ __ stw(T3, thread, in_bytes(JavaThread::popframe_condition_offset())); ++ ++#ifndef CORE ++ { ++ // Check to see whether we are returning to a deoptimized frame. ++ // (The PopFrame call ensures that the caller of the popped frame is ++ // either interpreted or compiled and deoptimizes it if compiled.) ++ // In this case, we can't call dispatch_next() after the frame is ++ // popped, but instead must save the incoming arguments and restore ++ // them after deoptimization has occurred. ++ // ++ // Note that we don't compare the return PC against the ++ // deoptimization blob's unpack entry because of the presence of ++ // adapter frames in C2. ++ Label caller_not_deoptimized; ++ __ ldl(A0, FP, frame::return_addr_offset * wordSize); ++ __ super_call_VM_leaf(CAST_FROM_FN_PTR(address, InterpreterRuntime::interpreter_contains), A0); ++ __ bne(V0, caller_not_deoptimized); ++ ++ // Compute size of arguments for saving when returning to deoptimized caller ++ __ get_method(A1); ++ // __ verify_oop(A1); ++ __ ldl(A1,A1,in_bytes(Method::const_offset())); ++ __ ldhu(A1, A1, in_bytes(ConstMethod::size_of_parameters_offset())); ++ __ shl(A1, Interpreter::logStackElementSize); ++ __ restore_locals(); ++ __ subl(A2, LVP, A1); ++ __ add_simm16(A2, A2, wordSize); ++ // Save these arguments ++ __ move(A0, S2thread); ++ __ super_call_VM_leaf(CAST_FROM_FN_PTR(address, Deoptimization::popframe_preserve_args), A0, A1, A2); ++ ++ __ remove_activation(vtos, T12, false, false, false); ++ ++ // Inform deoptimization that it is responsible for restoring these arguments ++ __ move(AT, JavaThread::popframe_force_deopt_reexecution_bit); ++ __ stw(AT, thread, in_bytes(JavaThread::popframe_condition_offset())); ++ // Continue in deoptimization handler ++ __ jmp(T12); ++ ++ __ BIND(caller_not_deoptimized); ++ } ++#endif /* !CORE */ ++ ++ __ remove_activation(vtos, T3, ++ /* throw_monitor_exception */ false, ++ /* install_monitor_exception */ false, ++ /* notify_jvmdi */ false); ++ ++ // Clear the popframe condition flag ++ // Finish with popframe handling ++ // A previous I2C followed by a deoptimization might have moved the ++ // outgoing arguments further up the stack. PopFrame expects the ++ // mutations to those outgoing arguments to be preserved and other ++ // constraints basically require this frame to look exactly as ++ // though it had previously invoked an interpreted activation with ++ // no space between the top of the expression stack (current ++ // last_sp) and the top of stack. Rather than force deopt to ++ // maintain this kind of invariant all the time we call a small ++ // fixup routine to move the mutated arguments onto the top of our ++ // expression stack if necessary. ++ __ move(T11, SP); ++ __ ldl(A2, FP, frame::interpreter_frame_last_sp_offset * wordSize); ++ // PC must point into interpreter here ++ __ set_last_Java_frame(thread, noreg, FP, __ pc()); ++ __ super_call_VM_leaf(CAST_FROM_FN_PTR(address, InterpreterRuntime::popframe_move_outgoing_args), thread, T11, A2); ++ __ reset_last_Java_frame(thread, true); ++ // Restore the last_sp and null it out ++ __ ldl(SP, FP, frame::interpreter_frame_last_sp_offset * wordSize); ++ __ stl(R0, FP, frame::interpreter_frame_last_sp_offset * wordSize); ++ ++ ++ ++ __ move(AT, JavaThread::popframe_inactive); ++ __ stw(AT, thread, in_bytes(JavaThread::popframe_condition_offset())); ++ ++ // Finish with popframe handling ++ __ restore_bcp(); ++ __ restore_locals(); ++#ifndef CORE ++ // The method data pointer was incremented already during ++ // call profiling. We have to restore the mdp for the current bcp. ++ if (ProfileInterpreter) { ++ __ set_method_data_pointer_for_bcp(); ++ } ++#endif // !CORE ++ // Clear the popframe condition flag ++ __ move(AT, JavaThread::popframe_inactive); ++ __ stw(AT, thread, in_bytes(JavaThread::popframe_condition_offset())); ++ __ dispatch_next(vtos); ++ // end of PopFrame support ++ ++ Interpreter::_remove_activation_entry = __ pc(); ++ ++ // preserve exception over this code sequence ++ __ ldl(T0, SP, 0); ++ __ add_simm16(SP, SP, wordSize); ++ __ stl(T0, thread, in_bytes(JavaThread::vm_result_offset())); ++ // remove the activation (without doing throws on illegalMonitorExceptions) ++ __ remove_activation(vtos, T3, false, true, false); ++ // restore exception ++ __ get_vm_result(T0, thread); ++ //__ verify_oop(T0); ++ ++ // Inbetween activations - previous activation type unknown yet ++ // compute continuation point - the continuation point expects ++ // the following registers set up: ++ // ++ // T0: exception ++ // T1: return address/pc that threw exception ++ // SP: expression stack of caller ++ // FP: fp of caller ++ __ add_simm16(SP, SP, (-2) * wordSize); ++ __ stl(T0, SP, wordSize); // save exception ++ __ stl(T3, SP, 0); // save return address ++ __ move(A1, T3); ++ __ super_call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::exception_handler_for_return_address), thread, A1); ++ __ move(T12, V0); // save exception handler ++ __ ldl(V0, SP, wordSize); // restore exception ++ __ ldl(T4, SP, 0); // restore return address ++ __ add_simm16(SP, SP, 2 * wordSize); ++ ++ // Note that an "issuing PC" is actually the next PC after the call ++ __ jmp(T12); // jump to exception handler of caller ++} ++ ++ ++// ++// JVMTI ForceEarlyReturn support ++// ++address TemplateInterpreterGenerator::generate_earlyret_entry_for(TosState state) { ++ address entry = __ pc(); ++ __ restore_bcp(); ++ __ restore_locals(); ++ __ empty_expression_stack(); ++ __ empty_FPU_stack(); ++ __ load_earlyret_value(state); ++ ++ __ ld_ptr(T12, S2thread, in_bytes(JavaThread::jvmti_thread_state_offset())); ++ ++ const Address cond_addr(T12, in_bytes(JvmtiThreadState::earlyret_state_offset())); ++ // Clear the earlyret state ++ __ move(AT,JvmtiThreadState::earlyret_inactive); ++ __ stw(AT,cond_addr); ++ __ memb(); ++ ++ __ remove_activation(state, T0, ++ false, /* throw_monitor_exception */ ++ false, /* install_monitor_exception */ ++ true); /* notify_jvmdi */ ++ __ memb(); ++ __ jmp(T0); ++ return entry; ++} // end of ForceEarlyReturn support ++ ++ ++//----------------------------------------------------------------------------- ++// Helper for vtos entry point generation ++ ++void TemplateInterpreterGenerator::set_vtos_entry_points(Template* t, ++ address& bep, ++ address& cep, ++ address& sep, ++ address& aep, ++ address& iep, ++ address& lep, ++ address& fep, ++ address& dep, ++ address& vep) { ++ assert(t->is_valid() && t->tos_in() == vtos, "illegal template"); ++ Label L; ++ fep = __ pc(); __ push(ftos); __ beq(R0, L); ++ dep = __ pc(); __ push(dtos); __ beq(R0, L); ++ lep = __ pc(); __ push(ltos); __ beq(R0, L); ++ aep =__ pc(); __ push(atos); __ beq(R0, L); ++ bep = cep = sep = iep = __ pc(); __ push(itos); ++ vep = __ pc(); ++ __ BIND(L); // fall through ++ generate_and_dispatch(t); ++} ++ ++ ++//----------------------------------------------------------------------------- ++// Generation of individual instructions ++ ++// helpers for generate_and_dispatch ++ ++ ++InterpreterGenerator::InterpreterGenerator(StubQueue* code) ++ : TemplateInterpreterGenerator(code) { ++ generate_all(); // down here so it can be "virtual" ++} ++ ++//----------------------------------------------------------------------------- ++ ++// Non-product code ++#ifndef PRODUCT ++address TemplateInterpreterGenerator::generate_trace_code(TosState state) { ++ address entry = __ pc(); ++ ++ // prepare expression stack ++ __ push(state); // save tosca ++ ++ // tos & tos2 ++ // trace_bytecode need actually 4 args, the last two is tos&tos2 ++ // to the stack position it think is the tos&tos2 ++ // when the expression stack have no more than 2 data, error occur. ++ __ ldl(A2, SP, 0); ++ __ ldl(A3, SP, 1 * wordSize); ++ ++ // pass arguments & call tracer ++ __ call_VM(noreg, CAST_FROM_FN_PTR(address, SharedRuntime::trace_bytecode), RA, A2, A3); ++ __ move(RA, V0); // make sure return address is not destroyed by pop(state) ++ ++ // restore expression stack ++ __ pop(state); // restore tosca ++ ++ // return ++ __ ret(); ++ ++ return entry; ++} ++ ++void TemplateInterpreterGenerator::count_bytecode() { ++ __ li(T11, (long)&BytecodeCounter::_counter_value); ++ __ ldw(AT, T11, 0); ++ __ addl(AT, AT, 1); ++ __ stw(AT, T11, 0); ++} ++ ++void TemplateInterpreterGenerator::histogram_bytecode(Template* t) { ++ __ li(T11, (long)&BytecodeHistogram::_counters[t->bytecode()]); ++ __ ldw(AT, T11, 0); ++ __ addl(AT, AT, 1); ++ __ stw(AT, T11, 0); ++} ++ ++void TemplateInterpreterGenerator::histogram_bytecode_pair(Template* t) { ++ __ li(T11, (long)&BytecodePairHistogram::_index); ++ __ ldw(T12, T11, 0); ++ __ srll(T12, T12, BytecodePairHistogram::log2_number_of_codes); ++ __ li(T11, ((long)t->bytecode()) << BytecodePairHistogram::log2_number_of_codes); ++ __ bis(T12, T12, T11); ++ __ li(T11, (long)&BytecodePairHistogram::_index); ++ __ stw(T12, T11, 0); ++ __ slll(T12, T12, 2); ++ __ li(T11, (long)BytecodePairHistogram::_counters); ++ __ addl(T11, T11, T12); ++ __ ldw(AT, T11, 0); ++ __ addl(AT, AT, 1); ++ __ stw(AT, T11, 0); ++} ++ ++ ++void TemplateInterpreterGenerator::trace_bytecode(Template* t) { ++ // Call a little run-time stub to avoid blow-up for each bytecode. ++ // The run-time runtime saves the right registers, depending on ++ // the tosca in-state for the given template. ++ ++ address entry = Interpreter::trace_code(t->tos_in()); ++ assert(entry != NULL, "entry must have been generated"); ++ __ call(entry, relocInfo::none); ++ //add for compressedoops ++ __ reinit_heapbase(); ++} ++ ++ ++void TemplateInterpreterGenerator::stop_interpreter_at() { ++ Label L; ++ __ li(T11, long(&BytecodeCounter::_counter_value)); ++ __ ldw(T11, T11, 0); ++ __ move(AT, StopInterpreterAt); ++ __ bne(T11, AT, L); ++ __ move(GP, 1); ++ __ bne(GP, -1); ++ __ call(CAST_FROM_FN_PTR(address, os::breakpoint), relocInfo::runtime_call_type); ++ __ BIND(L); ++} ++#endif // !PRODUCT ++#endif // ! CC_INTERP +diff --git a/hotspot/src/cpu/sw64/vm/templateInterpreter_sw64.hpp b/hotspot/src/cpu/sw64/vm/templateInterpreter_sw64.hpp +new file mode 100755 +index 0000000000..dc6aaeef3a +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/templateInterpreter_sw64.hpp +@@ -0,0 +1,40 @@ ++/* ++ * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_SW64_VM_TEMPLATEINTERPRETER_SW64_HPP ++#define CPU_SW64_VM_TEMPLATEINTERPRETER_SW64_HPP ++ ++ ++ protected: ++ ++ // Size of interpreter code. Increase if too small. Interpreter will ++ // fail with a guarantee ("not enough space for interpreter generation"); ++ // if too small. ++ // Run with +PrintInterpreter to get the VM to print out the size. ++ // Max size with JVMTI ++ // The sethi() instruction generates lots more instructions when shell ++ // stack limit is unlimited, so that's why this is much bigger. ++ const static int InterpreterCodeSize = 500 * K; ++ ++#endif // CPU_SW64_VM_TEMPLATEINTERPRETER_SW64_HPP +diff --git a/hotspot/src/cpu/sw64/vm/templateTable_sw64.cpp b/hotspot/src/cpu/sw64/vm/templateTable_sw64.cpp +new file mode 100755 +index 0000000000..983e19aff6 +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/templateTable_sw64.cpp +@@ -0,0 +1,4258 @@ ++/* ++ * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#include "precompiled.hpp" ++#include "asm/macroAssembler.hpp" ++#include "interpreter/interpreter.hpp" ++#include "interpreter/interpreterRuntime.hpp" ++#include "interpreter/templateTable.hpp" ++#include "memory/universe.inline.hpp" ++#include "oops/methodData.hpp" ++#include "oops/objArrayKlass.hpp" ++#include "oops/oop.inline.hpp" ++#include "prims/methodHandles.hpp" ++#include "runtime/sharedRuntime.hpp" ++#include "runtime/stubRoutines.hpp" ++#include "runtime/synchronizer.hpp" ++#include "utilities/macros.hpp" ++ ++ ++#ifndef CC_INTERP ++ ++#define __ _masm-> ++ ++#ifdef PRODUCT ++ #define BLOCK_COMMENT(str) /* nothing */ ++#else ++ #define BLOCK_COMMENT(str) { char line[1024];sprintf(line,"%s:%s:%d",str, __FILE__, __LINE__); __ block_comment(line);} ++#endif ++#define BIND(label) bind(label); BLOCK_COMMENT(#label ":") ++ ++ ++// Platform-dependent initialization ++ ++void TemplateTable::pd_initialize() { ++ // No sw64 specific initialization ++} ++ ++// Address computation: local variables ++ ++static inline Address iaddress(int n) { ++ return Address(LVP, Interpreter::local_offset_in_bytes(n)); ++} ++ ++static inline Address laddress(int n) { ++ return iaddress(n + 1); ++} ++ ++static inline Address faddress(int n) { ++ return iaddress(n); ++} ++ ++static inline Address daddress(int n) { ++ return laddress(n); ++} ++ ++static inline Address aaddress(int n) { ++ return iaddress(n); ++} ++ ++// never be used, why is here? jx ++static inline Address haddress(int n) { ++ return iaddress(n + 0); ++} ++ ++ ++static inline Address at_sp() { return Address(SP, 0); } ++static inline Address at_sp_p1() { return Address(SP, 1 * wordSize); } ++static inline Address at_sp_p2() { return Address(SP, 2 * wordSize); } ++ ++// At top of Java expression stack which may be different than sp(). It ++// isn't for category 1 objects. ++static inline Address at_tos () { ++ Address tos = Address(SP, Interpreter::expr_offset_in_bytes(0)); ++ return tos; ++} ++ ++static inline Address at_tos_p1() { ++ return Address(SP, Interpreter::expr_offset_in_bytes(1)); ++} ++ ++static inline Address at_tos_p2() { ++ return Address(SP, Interpreter::expr_offset_in_bytes(2)); ++} ++ ++static inline Address at_tos_p3() { ++ return Address(SP, Interpreter::expr_offset_in_bytes(3)); ++} ++ ++// we use S0 as bcp, be sure you have bcp in S0 before you call any of the Template generator ++Address TemplateTable::at_bcp(int offset) { ++ assert(_desc->uses_bcp(), "inconsistent uses_bcp information"); ++ return Address(BCP, offset); ++} ++ ++// Miscelaneous helper routines ++// Store an oop (or NULL) at the address described by obj. ++// If val == noreg this means store a NULL ++ ++static void do_oop_store(InterpreterMacroAssembler* _masm, ++ Address obj, ++ Register val, ++ BarrierSet::Name barrier, ++ bool precise) { ++ assert(val == noreg || val == V0, "parameter is just for looks"); ++ switch (barrier) { ++#if INCLUDE_ALL_GCS ++ case BarrierSet::G1SATBCT: ++ case BarrierSet::G1SATBCTLogging: ++ { ++ // flatten object address if needed ++ if (obj.index() == noreg && obj.disp() == 0) { ++ if (obj.base() != T3) { ++ __ move(T3, obj.base()); ++ } ++ } else { ++ __ lea(T3, obj); ++ } ++ __ g1_write_barrier_pre(T3 /* obj */, ++ T1 /* pre_val */, ++ S2thread /* thread */, ++ T12 /* tmp */, ++ val != noreg /* tosca_live */, ++ false /* expand_call */); ++ if (val == noreg) { ++ __ store_heap_oop_null(Address(T3, 0)); ++ } else { ++ // G1 barrier needs uncompressed oop for region cross check. ++ Register new_val = val; ++ if (UseCompressedOops) { ++ new_val = T1; ++ __ move(new_val, val); ++ } ++ __ store_heap_oop(Address(T3, 0), val); ++ __ g1_write_barrier_post(T3 /* store_adr */, ++ new_val /* new_val */, ++ S2thread /* thread */, ++ T12 /* tmp */, ++ T1 /* tmp2 */); ++ } ++ } ++ break; ++#endif // INCLUDE_ALL_GCS ++ case BarrierSet::CardTableModRef: ++ case BarrierSet::CardTableExtension: ++ { ++ if (val == noreg) { ++ __ store_heap_oop_null(obj); ++ } else { ++ __ store_heap_oop(obj, val); ++ // flatten object address if needed ++ if (!precise || (obj.index() == noreg && obj.disp() == 0)) { ++ __ store_check(obj.base()); ++ } else { ++ __ lea(T12, obj); ++ __ store_check(T12); ++ } ++ } ++ } ++ break; ++ case BarrierSet::ModRef: ++ case BarrierSet::Other: ++ if (val == noreg) { ++ __ store_heap_oop_null(obj); ++ } else { ++ __ store_heap_oop(obj, val); ++ } ++ break; ++ default : ++ ShouldNotReachHere(); ++ ++ } ++} ++ ++// bytecode folding ++void TemplateTable::patch_bytecode(Bytecodes::Code bc, Register bc_reg, ++ Register tmp_reg, bool load_bc_into_bc_reg/*=true*/, ++ int byte_no) { ++ if (!RewriteBytecodes) return; ++ Label L_patch_done; ++ ++ switch (bc) { ++ case Bytecodes::_fast_aputfield: ++ case Bytecodes::_fast_bputfield: ++ case Bytecodes::_fast_zputfield: ++ case Bytecodes::_fast_cputfield: ++ case Bytecodes::_fast_dputfield: ++ case Bytecodes::_fast_fputfield: ++ case Bytecodes::_fast_iputfield: ++ case Bytecodes::_fast_lputfield: ++ case Bytecodes::_fast_sputfield: ++ { ++ // We skip bytecode quickening for putfield instructions when ++ // the put_code written to the constant pool cache is zero. ++ // This is required so that every execution of this instruction ++ // calls out to InterpreterRuntime::resolve_get_put to do ++ // additional, required work. ++ assert(byte_no == f1_byte || byte_no == f2_byte, "byte_no out of range"); ++ assert(load_bc_into_bc_reg, "we use bc_reg as temp"); ++ __ get_cache_and_index_and_bytecode_at_bcp(tmp_reg, bc_reg, tmp_reg, byte_no, 1); ++ __ add_simm16(bc_reg, R0, bc); ++ __ beq(tmp_reg, L_patch_done); ++ } ++ break; ++ default: ++ assert(byte_no == -1, "sanity"); ++ // the pair bytecodes have already done the load. ++ if (load_bc_into_bc_reg) { ++ __ move(bc_reg, bc); ++ } ++ } ++ ++ if (JvmtiExport::can_post_breakpoint()) { ++ Label L_fast_patch; ++ // if a breakpoint is present we can't rewrite the stream directly ++ __ ldbu(tmp_reg, at_bcp(0)); ++ __ move(AT, Bytecodes::_breakpoint); ++ __ bne(tmp_reg, AT, L_fast_patch); ++ ++ __ get_method(tmp_reg); ++ // Let breakpoint table handling rewrite to quicker bytecode ++ __ call_VM(NOREG, CAST_FROM_FN_PTR(address, ++ InterpreterRuntime::set_original_bytecode_at), tmp_reg, BCP, bc_reg); ++ ++ __ beq(R0, L_patch_done); ++ __ BIND(L_fast_patch); ++ } ++ ++#ifdef ASSERT ++ Label L_okay; ++ __ ldbu(tmp_reg, at_bcp(0)); ++ __ move(AT, (int)Bytecodes::java_code(bc)); ++ __ beq(tmp_reg, AT, L_okay); ++ __ beq(tmp_reg, bc_reg, L_patch_done); ++ __ stop("patching the wrong bytecode"); ++ __ BIND(L_okay); ++#endif ++ ++ // patch bytecode ++ __ stb(bc_reg, at_bcp(0)); ++ __ BIND(L_patch_done); ++} ++ ++ ++// Individual instructions ++ ++void TemplateTable::nop() { ++ transition(vtos, vtos); ++ // nothing to do ++} ++ ++void TemplateTable::shouldnotreachhere() { ++ transition(vtos, vtos); ++ __ stop("shouldnotreachhere bytecode"); ++} ++ ++void TemplateTable::aconst_null() { ++ transition(vtos, atos); ++ __ move(FSR, R0); ++} ++ ++void TemplateTable::iconst(int value) { ++ transition(vtos, itos); ++ if (value == 0) { ++ __ move(FSR, R0); ++ } else { ++ __ move(FSR, value); ++ } ++} ++ ++void TemplateTable::lconst(int value) { ++ transition(vtos, ltos); ++ if (value == 0) { ++ __ move(FSR, R0); ++ } else { ++ __ move(FSR, value); ++ } ++} ++ ++void TemplateTable::fconst(int value) { ++ static float _f1 = 1.0, _f2 = 2.0; ++ transition(vtos, ftos); ++ float* p; ++ switch( value ) { ++ default: ShouldNotReachHere(); ++ case 0: __ fmovs(FSF, F31); return; ++ case 1: p = &_f1; break; ++ case 2: p = &_f2; break; ++ } ++ __ li(AT, (address)p); ++ __ flds(FSF, AT, 0); ++} ++ ++void TemplateTable::dconst(int value) { ++ static double _d1 = 1.0; ++ transition(vtos, dtos); ++ double* p; ++ switch( value ) { ++ default: ShouldNotReachHere(); ++ case 0: __ fmovd(FSF, F31); return; ++ case 1: p = &_d1; break; ++ } ++ __ li(AT, (address)p); ++ __ fldd(FSF, AT, 0); ++} ++ ++void TemplateTable::bipush() { ++ transition(vtos, itos); ++ __ ldb_signed(FSR, at_bcp(1)); ++} ++ ++void TemplateTable::sipush() { ++ transition(vtos, itos); ++ __ ldb_signed(FSR, BCP, 1); ++ __ ldbu(AT, BCP, 2); ++ __ slll(FSR, FSR, 8); ++ __ or_ins(FSR, FSR, AT); ++} ++ ++// T1 : tags ++// T2 : index ++// T3 : cpool ++// T11 : tag ++void TemplateTable::ldc(bool wide) { ++ transition(vtos, vtos); ++ Label call_ldc, notFloat, notClass, Done; ++ // get index in cpool ++ if (wide) { ++ __ get_unsigned_2_byte_index_at_bcp(T2, 1); ++ } else { ++ __ ldbu(T2, at_bcp(1)); ++ } ++ ++ __ get_cpool_and_tags(T3, T1); ++ ++ const int base_offset = ConstantPool::header_size() * wordSize; ++ const int tags_offset = Array::base_offset_in_bytes(); ++ ++ // get type ++ __ addl(AT, T1, T2); ++ __ ldbu(T1, AT, tags_offset); ++ //now T1 is the tag ++ ++ // unresolved class - get the resolved class ++ __ add_simm16(AT, T1, - JVM_CONSTANT_UnresolvedClass); ++ __ beq(AT, call_ldc); ++ ++ // unresolved class in error (resolution failed) - call into runtime ++ // so that the same error from first resolution attempt is thrown. ++ __ add_simm16(AT, T1, -JVM_CONSTANT_UnresolvedClassInError); ++ __ beq(AT, call_ldc); ++ ++ // resolved class - need to call vm to get java mirror of the class ++ __ add_simm16(AT, T1, - JVM_CONSTANT_Class); ++ __ slll(T2, T2, Address::times_8); ++ __ bne(AT, notClass); ++ ++ __ BIND(call_ldc); ++ __ move(A1, wide); ++ call_VM(FSR, CAST_FROM_FN_PTR(address, InterpreterRuntime::ldc), A1); ++ //__ push(atos); ++ __ stl(FSR, SP, - Interpreter::stackElementSize); ++ __ add_simm16(SP, SP, - Interpreter::stackElementSize); ++ __ beq(R0, Done); ++ ++ __ BIND(notClass); ++ __ add_simm16(AT, T1, -JVM_CONSTANT_Float); ++ __ bne(AT, notFloat); ++ // ftos ++ __ addl(AT, T3, T2); ++ __ flds(FSF, AT, base_offset); ++ //__ push_f(); ++ __ fsts(FSF, SP, - Interpreter::stackElementSize); ++ __ add_simm16(SP, SP, - Interpreter::stackElementSize); ++ __ beq(R0, Done); ++ __ BIND(notFloat); ++#ifdef ASSERT ++ { ++ Label L; ++ __ add_simm16(AT, T1, -JVM_CONSTANT_Integer); ++ __ beq(AT, L); ++ __ stop("unexpected tag type in ldc"); ++ __ BIND(L); ++ } ++#endif ++ // itos JVM_CONSTANT_Integer only ++ __ addl(T0, T3, T2); ++ __ ldw(FSR, T0, base_offset); ++ __ push(itos); ++ __ BIND(Done); ++} ++ ++// Fast path for caching oop constants. ++void TemplateTable::fast_aldc(bool wide) { ++ transition(vtos, atos); ++ ++ Register result = FSR; ++ Register tmp = SSR; ++ int index_size = wide ? sizeof(u2) : sizeof(u1); ++ ++ Label resolved; ++ ++ // We are resolved if the resolved reference cache entry contains a ++ // non-null object (String, MethodType, etc.) ++ assert_different_registers(result, tmp); ++ __ get_cache_index_at_bcp(tmp, 1, index_size); ++ __ load_resolved_reference_at_index(result, tmp); ++ __ bne(result, resolved); ++ ++ address entry = CAST_FROM_FN_PTR(address, InterpreterRuntime::resolve_ldc); ++ // first time invocation - must resolve first ++ int i = (int)bytecode(); ++ __ move(tmp, i); ++ __ call_VM(result, entry, tmp); ++ ++ __ BIND(resolved); ++ ++ if (VerifyOops) { ++ __ verify_oop(result); ++ } ++} ++ ++ ++// used register: T2, T3, T1 ++// T2 : index ++// T3 : cpool ++// T1 : tag ++void TemplateTable::ldc2_w() { ++ transition(vtos, vtos); ++ Label Long, Done; ++ ++ // get index in cpool ++ __ get_unsigned_2_byte_index_at_bcp(T2, 1); ++ ++ __ get_cpool_and_tags(T3, T1); ++ ++ const int base_offset = ConstantPool::header_size() * wordSize; ++ const int tags_offset = Array::base_offset_in_bytes(); ++ ++ // get type in T1 ++ __ addl(AT, T1, T2); ++ __ ldbu(T1, AT, tags_offset); ++ ++ __ add_simm16(AT, T1, - JVM_CONSTANT_Double); ++ __ slll(T2, T2, Address::times_8); ++ __ bne(AT, Long); ++ ++ // dtos ++ __ addl(AT, T3, T2); ++ __ fldd(FSF, AT, base_offset); ++ __ fstd(FSF, SP, - 2 * wordSize); ++ __ add_simm16(SP, SP, - 2 * wordSize); ++ __ beq(R0, Done); ++ ++ // ltos ++ __ BIND(Long); ++ __ addl(AT, T3, T2); ++ __ ldl(FSR, AT, base_offset); ++ __ push(ltos); ++ ++ __ BIND(Done); ++} ++ ++// we compute the actual local variable address here ++// the x86 dont do so for it has scaled index memory access model, we dont have, so do here ++void TemplateTable::locals_index(Register reg, int offset) { ++ __ ldbu(reg, at_bcp(offset)); ++ __ slll(reg, reg, Address::times_8); ++ __ subl(reg, LVP, reg); ++} ++ ++// this method will do bytecode folding of the two form: ++// iload iload iload caload ++// used register : T2, T3 ++// T2 : bytecode ++// T3 : folded code ++void TemplateTable::iload() { ++ transition(vtos, itos); ++ if (RewriteFrequentPairs) { ++ Label rewrite, done; ++ // get the next bytecode in T2 ++ __ ldbu(T2, at_bcp(Bytecodes::length_for(Bytecodes::_iload))); ++ // if _iload, wait to rewrite to iload2. We only want to rewrite the ++ // last two iloads in a pair. Comparing against fast_iload means that ++ // the next bytecode is neither an iload or a caload, and therefore ++ // an iload pair. ++ __ move(AT, Bytecodes::_iload); ++ __ beq(AT, T2, done); ++ ++ __ move(T3, Bytecodes::_fast_iload2); ++ __ move(AT, Bytecodes::_fast_iload); ++ __ beq(AT, T2, rewrite); ++ ++ // if _caload, rewrite to fast_icaload ++ __ move(T3, Bytecodes::_fast_icaload); ++ __ move(AT, Bytecodes::_caload); ++ __ beq(AT, T2, rewrite); ++ ++ // rewrite so iload doesn't check again. ++ __ move(T3, Bytecodes::_fast_iload); ++ ++ // rewrite ++ // T3 : fast bytecode ++ __ BIND(rewrite); ++ patch_bytecode(Bytecodes::_iload, T3, T2, false); ++ __ BIND(done); ++ } ++ ++ // Get the local value into tos ++ locals_index(T2); ++ __ ldw(FSR, T2, 0); ++} ++ ++// used register T2 ++// T2 : index ++void TemplateTable::fast_iload2() { ++ transition(vtos, itos); ++ locals_index(T2); ++ __ ldw(FSR, T2, 0); ++ __ push(itos); ++ locals_index(T2, 3); ++ __ ldw(FSR, T2, 0); ++} ++ ++// used register T2 ++// T2 : index ++void TemplateTable::fast_iload() { ++ transition(vtos, itos); ++ locals_index(T2); ++ __ ldw(FSR, T2, 0); ++} ++ ++// used register T2 ++// T2 : index ++void TemplateTable::lload() { ++ transition(vtos, ltos); ++ locals_index(T2); ++ __ ldl(FSR, T2, -wordSize); ++} ++ ++// used register T2 ++// T2 : index ++void TemplateTable::fload() { ++ transition(vtos, ftos); ++ locals_index(T2); ++ __ flds(FSF, T2, 0); ++} ++ ++// used register T2 ++// T2 : index ++void TemplateTable::dload() { ++ transition(vtos, dtos); ++ locals_index(T2); ++ __ fldd(FSF, T2, -wordSize); ++} ++ ++// used register T2 ++// T2 : index ++void TemplateTable::aload() { ++ transition(vtos, atos); ++ locals_index(T2); ++ __ ldl(FSR, T2, 0); ++} ++ ++void TemplateTable::locals_index_wide(Register reg) { ++ __ get_unsigned_2_byte_index_at_bcp(reg, 2); ++ __ slll(reg, reg, Address::times_8); ++ __ subl(reg, LVP, reg); ++} ++ ++// used register T2 ++// T2 : index ++void TemplateTable::wide_iload() { ++ transition(vtos, itos); ++ locals_index_wide(T2); ++ __ ldl(FSR, T2, 0); ++} ++ ++// used register T2 ++// T2 : index ++void TemplateTable::wide_lload() { ++ transition(vtos, ltos); ++ locals_index_wide(T2); ++ __ ldl(FSR, T2, -wordSize); ++} ++ ++// used register T2 ++// T2 : index ++void TemplateTable::wide_fload() { ++ transition(vtos, ftos); ++ locals_index_wide(T2); ++ __ flds(FSF, T2, 0); ++} ++ ++// used register T2 ++// T2 : index ++void TemplateTable::wide_dload() { ++ transition(vtos, dtos); ++ locals_index_wide(T2); ++ __ fldd(FSF, T2, -wordSize); ++} ++ ++// used register T2 ++// T2 : index ++void TemplateTable::wide_aload() { ++ transition(vtos, atos); ++ locals_index_wide(T2); ++ __ ldl(FSR, T2, 0); ++} ++ ++// we use A2 as the regiser for index, BE CAREFUL! ++// we dont use our tge 29 now, for later optimization ++void TemplateTable::index_check(Register array, Register index) { ++ // Pop ptr into array ++ __ pop_ptr(array); ++ index_check_without_pop(array, index); ++} ++ ++void TemplateTable::index_check_without_pop(Register array, Register index) { ++ // destroys A2 ++ // check array ++ __ null_check(array, arrayOopDesc::length_offset_in_bytes()); ++ ++ // sign extend since tos (index) might contain garbage in upper bits ++ __ addw(index, index, 0); ++ ++ // check index ++ Label ok; ++ __ ldw(AT, array, arrayOopDesc::length_offset_in_bytes()); ++ __ blt(index, AT, ok); ++ //throw_ArrayIndexOutOfBoundsException assume abberrant index in A2 ++ if (A2 != index) __ move(A2, index); ++ __ jmp(Interpreter::_throw_ArrayIndexOutOfBoundsException_entry); ++ __ BIND(ok); ++} ++ ++void TemplateTable::iaload() { ++ transition(itos, itos); ++ index_check(SSR, FSR); ++ __ slll(FSR, FSR, 2); ++ __ addl(FSR, SSR, FSR); ++ __ ldw(FSR, FSR, arrayOopDesc::base_offset_in_bytes(T_INT)); ++} ++ ++void TemplateTable::laload() { ++ transition(itos, ltos); ++ index_check(SSR, FSR); ++ __ slll(AT, FSR, Address::times_8); ++ __ addl(AT, SSR, AT); ++ __ ldl(FSR, AT, arrayOopDesc::base_offset_in_bytes(T_LONG)); ++} ++ ++void TemplateTable::faload() { ++ transition(itos, ftos); ++ index_check(SSR, FSR); ++ __ slll(FSR, FSR, 2); ++ __ addl(FSR, SSR, FSR); ++ __ flds(FSF, FSR, arrayOopDesc::base_offset_in_bytes(T_FLOAT)); ++} ++ ++void TemplateTable::daload() { ++ transition(itos, dtos); ++ //__ pop(SSR); ++ index_check(SSR, FSR); ++ __ slll(AT, FSR, 3); ++ __ addl(AT, SSR, AT); ++ __ fldd(FSF, AT, arrayOopDesc::base_offset_in_bytes(T_DOUBLE)); ++} ++ ++void TemplateTable::aaload() { ++ transition(itos, atos); ++ index_check(SSR, FSR); ++ __ slll(FSR, FSR, UseCompressedOops ? Address::times_4 : Address::times_8); ++ __ addl(FSR, SSR, FSR); ++ //add for compressedoops ++ __ load_heap_oop(FSR, Address(FSR, arrayOopDesc::base_offset_in_bytes(T_OBJECT))); ++} ++ ++void TemplateTable::baload() { ++ transition(itos, itos); ++ index_check(SSR, FSR); ++ __ addl(FSR, SSR, FSR); ++ __ ldb_signed(FSR, FSR, arrayOopDesc::base_offset_in_bytes(T_BYTE)); ++} ++ ++void TemplateTable::caload() { ++ transition(itos, itos); ++ index_check(SSR, FSR); ++ __ slll(FSR, FSR, Address::times_2); ++ __ addl(FSR, SSR, FSR); ++ __ ldhu(FSR, FSR, arrayOopDesc::base_offset_in_bytes(T_CHAR)); ++} ++ ++// iload followed by caload frequent pair ++// used register : T2 ++// T2 : index ++void TemplateTable::fast_icaload() { ++ ++ transition(vtos, itos); ++ // load index out of locals ++ locals_index(T2); ++ __ ldw(FSR, T2, 0); ++ index_check(SSR, FSR); ++ __ slll(FSR, FSR, 1); ++ __ addl(FSR, SSR, FSR); ++ __ ldhu(FSR, FSR, arrayOopDesc::base_offset_in_bytes(T_CHAR)); ++} ++ ++void TemplateTable::saload() { ++ transition(itos, itos); ++ index_check(SSR, FSR); ++ __ slll(FSR, FSR, Address::times_2); ++ __ addl(FSR, SSR, FSR); ++ __ ldh_signed(FSR, FSR, arrayOopDesc::base_offset_in_bytes(T_SHORT)); ++} ++ ++void TemplateTable::iload(int n) { ++ transition(vtos, itos); ++ __ ldw_signed(FSR, iaddress(n)); ++} ++ ++void TemplateTable::lload(int n) { ++ transition(vtos, ltos); ++ __ ldl(FSR, laddress(n)); ++} ++ ++void TemplateTable::fload(int n) { ++ transition(vtos, ftos); ++ __ flds(FSF, faddress(n)); ++} ++ ++void TemplateTable::dload(int n) { ++ transition(vtos, dtos); ++ __ fldd(FSF, laddress(n)); ++} ++ ++void TemplateTable::aload(int n) { ++ transition(vtos, atos); ++ __ ldl(FSR, aaddress(n)); ++} ++ ++// used register : T2, T3 ++// T2 : bytecode ++// T3 : folded code ++void TemplateTable::aload_0() { ++ transition(vtos, atos); ++ // According to bytecode histograms, the pairs: ++ // ++ // _aload_0, _fast_igetfield ++ // _aload_0, _fast_agetfield ++ // _aload_0, _fast_fgetfield ++ // ++ // occur frequently. If RewriteFrequentPairs is set, the (slow) ++ // _aload_0 bytecode checks if the next bytecode is either ++ // _fast_igetfield, _fast_agetfield or _fast_fgetfield and then ++ // rewrites the current bytecode into a pair bytecode; otherwise it ++ // rewrites the current bytecode into _fast_aload_0 that doesn't do ++ // the pair check anymore. ++ // ++ // Note: If the next bytecode is _getfield, the rewrite must be ++ // delayed, otherwise we may miss an opportunity for a pair. ++ // ++ // Also rewrite frequent pairs ++ // aload_0, aload_1 ++ // aload_0, iload_1 ++ // These bytecodes with a small amount of code are most profitable ++ // to rewrite ++ if (RewriteFrequentPairs) { ++ Label rewrite, done; ++ // get the next bytecode in T2 ++ __ ldbu(T2, at_bcp(Bytecodes::length_for(Bytecodes::_aload_0))); ++ ++ // do actual aload_0 ++ aload(0); ++ ++ // if _getfield then wait with rewrite ++ __ move(AT, Bytecodes::_getfield); ++ __ beq(AT, T2, done); ++ ++ // if _igetfield then reqrite to _fast_iaccess_0 ++ assert(Bytecodes::java_code(Bytecodes::_fast_iaccess_0) == ++ Bytecodes::_aload_0, ++ "fix bytecode definition"); ++ __ move(T3, Bytecodes::_fast_iaccess_0); ++ __ move(AT, Bytecodes::_fast_igetfield); ++ __ beq(AT, T2, rewrite); ++ ++ // if _agetfield then reqrite to _fast_aaccess_0 ++ assert(Bytecodes::java_code(Bytecodes::_fast_aaccess_0) == ++ Bytecodes::_aload_0, ++ "fix bytecode definition"); ++ __ move(T3, Bytecodes::_fast_aaccess_0); ++ __ move(AT, Bytecodes::_fast_agetfield); ++ __ beq(AT, T2, rewrite); ++ ++ // if _fgetfield then reqrite to _fast_faccess_0 ++ assert(Bytecodes::java_code(Bytecodes::_fast_faccess_0) == ++ Bytecodes::_aload_0, ++ "fix bytecode definition"); ++ __ move(T3, Bytecodes::_fast_faccess_0); ++ __ move(AT, Bytecodes::_fast_fgetfield); ++ __ beq(AT, T2, rewrite); ++ ++ // else rewrite to _fast_aload0 ++ assert(Bytecodes::java_code(Bytecodes::_fast_aload_0) == ++ Bytecodes::_aload_0, ++ "fix bytecode definition"); ++ __ move(T3, Bytecodes::_fast_aload_0); ++ ++ // rewrite ++ __ BIND(rewrite); ++ patch_bytecode(Bytecodes::_aload_0, T3, T2, false); ++ ++ __ BIND(done); ++ } else { ++ aload(0); ++ } ++} ++ ++void TemplateTable::istore() { ++ transition(itos, vtos); ++ locals_index(T2); ++ __ stw(FSR, T2, 0); ++} ++ ++void TemplateTable::lstore() { ++ transition(ltos, vtos); ++ locals_index(T2); ++ __ stl(FSR, T2, -wordSize); ++} ++ ++void TemplateTable::fstore() { ++ transition(ftos, vtos); ++ locals_index(T2); ++ __ fsts(FSF, T2, 0); ++} ++ ++void TemplateTable::dstore() { ++ transition(dtos, vtos); ++ locals_index(T2); ++ __ fstd(FSF, T2, -wordSize); ++} ++ ++void TemplateTable::astore() { ++ transition(vtos, vtos); ++ __ pop_ptr(FSR); ++ locals_index(T2); ++ __ stl(FSR, T2, 0); ++} ++ ++void TemplateTable::wide_istore() { ++ transition(vtos, vtos); ++ __ pop_i(FSR); ++ locals_index_wide(T2); ++ __ stl(FSR, T2, 0); ++} ++ ++void TemplateTable::wide_lstore() { ++ transition(vtos, vtos); ++ __ pop_l(FSR); ++ locals_index_wide(T2); ++ __ stl(FSR, T2, -wordSize); ++} ++ ++void TemplateTable::wide_fstore() { ++ wide_istore(); ++} ++ ++void TemplateTable::wide_dstore() { ++ wide_lstore(); ++} ++ ++void TemplateTable::wide_astore() { ++ transition(vtos, vtos); ++ __ pop_ptr(FSR); ++ locals_index_wide(T2); ++ __ stl(FSR, T2, 0); ++} ++ ++// used register : T2 ++void TemplateTable::iastore() { ++ transition(itos, vtos); ++ __ pop_i(SSR); // T2: array SSR: index ++ index_check(T2, SSR); // prefer index in SSR ++ __ slll(SSR, SSR, Address::times_4); ++ __ addl(T2, T2, SSR); ++ __ stw(FSR, T2, arrayOopDesc::base_offset_in_bytes(T_INT)); ++} ++ ++ ++ ++// used register T2, T3 ++void TemplateTable::lastore() { ++ transition(ltos, vtos); ++ __ pop_i (T2); ++ index_check(T3, T2); ++ __ slll(T2, T2, Address::times_8); ++ __ addl(T3, T3, T2); ++ __ stl(FSR, T3, arrayOopDesc::base_offset_in_bytes(T_LONG)); ++} ++ ++// used register T2 ++void TemplateTable::fastore() { ++ transition(ftos, vtos); ++ __ pop_i(SSR); ++ index_check(T2, SSR); ++ __ slll(SSR, SSR, Address::times_4); ++ __ addl(T2, T2, SSR); ++ __ fsts(FSF, T2, arrayOopDesc::base_offset_in_bytes(T_FLOAT)); ++} ++ ++// used register T2, T3 ++void TemplateTable::dastore() { ++ transition(dtos, vtos); ++ __ pop_i (T2); ++ index_check(T3, T2); ++ __ slll(T2, T2, Address::times_8); ++ __ addl(T3, T3, T2); ++ __ fstd(FSF, T3, arrayOopDesc::base_offset_in_bytes(T_DOUBLE)); ++ ++} ++ ++// used register : T2, T3, T11 ++// T2 : array ++// T3 : subklass ++// T11 : supklass ++void TemplateTable::aastore() { ++ Label is_null, ok_is_subtype, done; ++ transition(vtos, vtos); ++ // stack: ..., array, index, value ++ __ ldl(FSR, at_tos()); // Value ++ __ ldw_signed(SSR, at_tos_p1()); // Index ++ __ ldl(T2, at_tos_p2()); // Array ++ ++ // index_check(T2, SSR); ++ index_check_without_pop(T2, SSR); ++ // do array store check - check for NULL value first ++ __ beq(FSR, is_null); ++ ++ // Move subklass into T3 ++ //add for compressedoops ++ __ load_klass(T3, FSR); ++ // Move superklass into T11 ++ //add for compressedoops ++ __ load_klass(T11, T2); ++ __ ldl(T11, Address(T11, ObjArrayKlass::element_klass_offset())); ++ // Compress array+index*4+12 into a single register. T2 ++ __ slll(AT, SSR, UseCompressedOops? Address::times_4 : Address::times_8); ++ __ addl(T2, T2, AT); ++ __ add_simm16(T2, T2, arrayOopDesc::base_offset_in_bytes(T_OBJECT)); ++ ++ // Generate subtype check. ++ // Superklass in T11. Subklass in T3. ++ __ gen_subtype_check(T11, T3, ok_is_subtype); ++ // Come here on failure ++ // object is at FSR ++ __ jmp(Interpreter::_throw_ArrayStoreException_entry); ++ // Come here on success ++ __ BIND(ok_is_subtype); ++ do_oop_store(_masm, Address(T2, 0), FSR, _bs->kind(), true); ++ __ beq(R0, done); ++ ++ // Have a NULL in FSR, T2=array, SSR=index. Store NULL at ary[idx] ++ __ BIND(is_null); ++ __ profile_null_seen(T12); ++ __ slll(AT, SSR, UseCompressedOops? Address::times_4 : Address::times_8); ++ __ addl(T2, T2, AT); ++ do_oop_store(_masm, Address(T2, arrayOopDesc::base_offset_in_bytes(T_OBJECT)), noreg, _bs->kind(), true); ++ ++ __ BIND(done); ++ __ add_simm16(SP, SP, 3 * Interpreter::stackElementSize); ++} ++ ++void TemplateTable::bastore() { ++ transition(itos, vtos); ++ __ pop_i(SSR); ++ index_check(T2, SSR); ++ ++ // Need to check whether array is boolean or byte ++ // since both types share the bastore bytecode. ++ __ load_klass(T12, T2); ++ __ ldw(T12, T12, in_bytes(Klass::layout_helper_offset())); ++ ++ int diffbit = Klass::layout_helper_boolean_diffbit(); ++ __ move(AT, diffbit); ++ ++ Label L_skip; ++ __ and_reg(AT, T12, AT); ++ __ beq(AT, L_skip); ++ __ and_imm8(FSR, FSR, 0x1); ++ __ BIND(L_skip); ++ ++ __ addl(SSR, T2, SSR); ++ __ stb(FSR, SSR, arrayOopDesc::base_offset_in_bytes(T_BYTE)); ++} ++ ++void TemplateTable::castore() { ++ transition(itos, vtos); ++ __ pop_i(SSR); ++ index_check(T2, SSR); ++ __ slll(SSR, SSR, Address::times_2); ++ __ addl(SSR, T2, SSR); ++ __ sth(FSR, SSR, arrayOopDesc::base_offset_in_bytes(T_CHAR)); ++} ++ ++void TemplateTable::sastore() { ++ castore(); ++} ++ ++void TemplateTable::istore(int n) { ++ transition(itos, vtos); ++ __ stw(FSR, iaddress(n)); ++} ++ ++void TemplateTable::lstore(int n) { ++ transition(ltos, vtos); ++ __ stl(FSR, laddress(n)); ++} ++ ++void TemplateTable::fstore(int n) { ++ transition(ftos, vtos); ++ __ fsts(FSF, faddress(n)); ++} ++ ++void TemplateTable::dstore(int n) { ++ transition(dtos, vtos); ++ __ fstd(FSF, laddress(n)); ++} ++ ++void TemplateTable::astore(int n) { ++ transition(vtos, vtos); ++ __ pop_ptr(FSR); ++ __ stl(FSR, aaddress(n)); ++} ++ ++void TemplateTable::pop() { ++ transition(vtos, vtos); ++ __ addl(SP, SP, Interpreter::stackElementSize); ++} ++ ++void TemplateTable::pop2() { ++ transition(vtos, vtos); ++ __ addl(SP, SP, 2 * Interpreter::stackElementSize); ++} ++ ++void TemplateTable::dup() { ++ transition(vtos, vtos); ++ // stack: ..., a ++ __ load_ptr(0, FSR); ++ __ push_ptr(FSR); ++ // stack: ..., a, a ++} ++ ++// blows FSR ++void TemplateTable::dup_x1() { ++ transition(vtos, vtos); ++ // stack: ..., a, b ++ __ load_ptr(0, FSR); // load b ++ __ load_ptr(1, A5); // load a ++ __ store_ptr(1, FSR); // store b ++ __ store_ptr(0, A5); // store a ++ __ push_ptr(FSR); // push b ++ // stack: ..., b, a, b ++} ++ ++// blows FSR ++void TemplateTable::dup_x2() { ++ transition(vtos, vtos); ++ // stack: ..., a, b, c ++ __ load_ptr(0, FSR); // load c ++ __ load_ptr(2, A5); // load a ++ __ store_ptr(2, FSR); // store c in a ++ __ push_ptr(FSR); // push c ++ // stack: ..., c, b, c, c ++ __ load_ptr(2, FSR); // load b ++ __ store_ptr(2, A5); // store a in b ++ // stack: ..., c, a, c, c ++ __ store_ptr(1, FSR); // store b in c ++ // stack: ..., c, a, b, c ++} ++ ++// blows FSR ++void TemplateTable::dup2() { ++ transition(vtos, vtos); ++ // stack: ..., a, b ++ __ load_ptr(1, FSR); // load a ++ __ push_ptr(FSR); // push a ++ __ load_ptr(1, FSR); // load b ++ __ push_ptr(FSR); // push b ++ // stack: ..., a, b, a, b ++} ++ ++// blows FSR ++void TemplateTable::dup2_x1() { ++ transition(vtos, vtos); ++ // stack: ..., a, b, c ++ __ load_ptr(0, T2); // load c ++ __ load_ptr(1, FSR); // load b ++ __ push_ptr(FSR); // push b ++ __ push_ptr(T2); // push c ++ // stack: ..., a, b, c, b, c ++ __ store_ptr(3, T2); // store c in b ++ // stack: ..., a, c, c, b, c ++ __ load_ptr(4, T2); // load a ++ __ store_ptr(2, T2); // store a in 2nd c ++ // stack: ..., a, c, a, b, c ++ __ store_ptr(4, FSR); // store b in a ++ // stack: ..., b, c, a, b, c ++ ++ // stack: ..., b, c, a, b, c ++} ++ ++// blows FSR, SSR ++void TemplateTable::dup2_x2() { ++ transition(vtos, vtos); ++ // stack: ..., a, b, c, d ++ // stack: ..., a, b, c, d ++ __ load_ptr(0, T2); // load d ++ __ load_ptr(1, FSR); // load c ++ __ push_ptr(FSR); // push c ++ __ push_ptr(T2); // push d ++ // stack: ..., a, b, c, d, c, d ++ __ load_ptr(4, FSR); // load b ++ __ store_ptr(2, FSR); // store b in d ++ __ store_ptr(4, T2); // store d in b ++ // stack: ..., a, d, c, b, c, d ++ __ load_ptr(5, T2); // load a ++ __ load_ptr(3, FSR); // load c ++ __ store_ptr(3, T2); // store a in c ++ __ store_ptr(5, FSR); // store c in a ++ // stack: ..., c, d, a, b, c, d ++ ++ // stack: ..., c, d, a, b, c, d ++} ++ ++// blows FSR ++void TemplateTable::swap() { ++ transition(vtos, vtos); ++ // stack: ..., a, b ++ ++ __ load_ptr(1, A5); // load a ++ __ load_ptr(0, FSR); // load b ++ __ store_ptr(0, A5); // store a in b ++ __ store_ptr(1, FSR); // store b in a ++ ++ // stack: ..., b, a ++} ++ ++void TemplateTable::iop2(Operation op) { ++ transition(itos, itos); ++ ++ __ pop_i(SSR); ++ if (UseSW8A) { ++ switch (op) { ++ case add : __ addw(FSR, SSR, FSR); break; ++ case sub : __ subw(FSR, SSR, FSR); break; ++ case mul : __ mulw(FSR, SSR, FSR); break; ++ case _and : __ and_reg(FSR, SSR, FSR); break; ++ case _or : __ or_ins(FSR, SSR, FSR); break; ++ case _xor : __ xor_ins(FSR, SSR, FSR); break; ++ case shl : __ sllw(SSR, FSR, FSR); break; ++ case shr : __ sraw(SSR, FSR, FSR); break; ++ case ushr : __ srlw(SSR, FSR, FSR); break; ++ default : ShouldNotReachHere(); ++ } ++ } else { ++ switch (op) { ++ case add : __ addw(FSR, SSR, FSR); break; ++ case sub : __ subw(FSR, SSR, FSR); break; ++ case mul : __ mulw(FSR, SSR, FSR); break; ++ case _and : __ and_reg(FSR, SSR, FSR); break; ++ case _or : __ or_ins(FSR, SSR, FSR); break; ++ case _xor : __ xor_ins(FSR, SSR, FSR); break; ++ case shl : __ and_imm8(GP, FSR, 0x1f); __ slll(FSR, SSR, GP); __ addw(FSR, FSR, 0x0); break; ++ case shr : __ and_imm8(GP, FSR, 0x1f); __ addw(FSR, SSR, 0x0); __ sral(FSR, FSR, GP); break; ++ case ushr : __ and_imm8(GP, FSR, 0x1f); __ zapnot(FSR, SSR, 0xf); __ srll(FSR, FSR, GP); __ addw(FSR, FSR, 0x0); break; ++ default : ShouldNotReachHere(); ++ } ++ } ++} ++ ++// the result stored in FSR, SSR, ++// used registers : T2, T3 ++void TemplateTable::lop2(Operation op) { ++ transition(ltos, ltos); ++ __ pop_l(T2); ++ ++ switch (op) { ++ case add : __ addl(FSR, T2, FSR); break; ++ case sub : __ subl(FSR, T2, FSR); break; ++ case _and: __ and_reg(FSR, T2, FSR); break; ++ case _or : __ or_ins(FSR, T2, FSR); break; ++ case _xor: __ xor_ins(FSR, T2, FSR); break; ++ default : ShouldNotReachHere(); ++ } ++} ++ ++// java require this bytecode could handle 0x80000000/-1, dont cause a overflow exception, ++void TemplateTable::idiv() { ++ transition(itos, itos); ++ Label not_zero; ++ ++ __ bne(FSR, not_zero); ++ __ jmp(Interpreter::_throw_ArithmeticException_entry); ++ __ BIND(not_zero); ++ ++ __ pop_i(SSR); ++ if (UseSW8A) { ++ __ corrected_idivw(SSR, FSR, FSR); ++ } else if (FastIntDiv) { ++ __ idiv_sw(SSR, FSR, FSR); ++ } else { ++ __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::sdiv), FSR, SSR); ++ } ++} ++ ++void TemplateTable::irem() { ++ transition(itos, itos); ++ Label not_zero; ++ __ pop_i(SSR); ++ ++ __ bne(FSR, not_zero); ++ __ jmp(Interpreter::_throw_ArithmeticException_entry); ++ ++ __ BIND(not_zero); ++ if (UseSW8A) { ++ __ remw(SSR, FSR, FSR); ++ } else if (FastIntRem) { ++ __ irem_sw(SSR, FSR, FSR); ++ } else { ++ __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::srem), FSR, SSR); ++ } ++} ++ ++void TemplateTable::lmul() { ++ transition(ltos, ltos); ++ __ pop_l(T2); ++ __ mull(FSR, T2, FSR); ++} ++ ++// NOTE: i DONT use the Interpreter::_throw_ArithmeticException_entry ++void TemplateTable::ldiv() { ++ transition(ltos, ltos); ++ Label normal; ++ ++ __ bne(FSR, normal); ++ ++ //__ brk(7); //generate FPE ++ __ jmp(Interpreter::_throw_ArithmeticException_entry); ++ ++ __ BIND(normal); ++ __ pop_l(A2); ++ if (UseSW8A) { ++ __ corrected_idivl(A2, FSR, FSR); ++ } else if (FastLongDiv) { ++ Label ldiv, exit; ++ __ slll(T7, A2, 0xb); ++ __ sral(T7, T7, 0xb); ++ __ cmpeq(T7, A2, T7); ++ __ bne(T7, ldiv); ++ __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::ldiv), FSR, A2); ++ __ beq(R0, exit); ++ ++ __ BIND(ldiv); ++ __ ldiv_sw(A2, FSR, FSR); ++ ++ __ BIND(exit); ++ } else { ++ __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::ldiv), FSR, A2); ++ } ++} ++ ++// NOTE: i DONT use the Interpreter::_throw_ArithmeticException_entry ++void TemplateTable::lrem() { ++ transition(ltos, ltos); ++ Label normal; ++ ++ __ bne(FSR, normal); ++ ++ __ jmp(Interpreter::_throw_ArithmeticException_entry); ++ ++ __ BIND(normal); ++ __ pop_l (A2); ++ if (UseSW8A) { ++ __ reml(A2, FSR, FSR); ++ } else if (FastLongRem) { ++ Label lrem, exit; ++ __ slll(T7, A2, 0xb); ++ __ sral(T7, T7, 0xb); ++ __ cmpeq(T7, A2, T7); ++ __ bne(T7, lrem); ++ __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::lrem), FSR, A2); ++ __ beq(R0, exit); ++ ++ __ BIND(lrem); ++ __ lrem_sw(A2, FSR, FSR); ++ ++ __ BIND(exit); ++ } else { ++ __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::lrem), FSR, A2); ++ } ++} ++ ++// result in FSR ++// used registers : T0 ++void TemplateTable::lshl() { ++ transition(itos, ltos); ++ __ pop_l(T0); ++ __ slll(FSR, T0, FSR); ++} ++ ++// used registers : T0 ++void TemplateTable::lshr() { ++ transition(itos, ltos); ++ __ pop_l(T0); ++ __ sral(FSR, T0, FSR); ++} ++ ++// used registers : T0 ++void TemplateTable::lushr() { ++ transition(itos, ltos); ++ __ pop_l(T0); ++ __ srll(FSR, T0, FSR); ++} ++ ++// result in FSF ++void TemplateTable::fop2(Operation op) { ++ transition(ftos, ftos); ++ switch (op) { ++ case add: ++ __ flds(FTF, at_sp()); ++ __ add_s(FSF, FTF, FSF); ++ break; ++ case sub: ++ __ flds(FTF, at_sp()); ++ __ sub_s(FSF, FTF, FSF); ++ break; ++ case mul: ++ __ flds(FTF, at_sp()); ++ __ mul_s(FSF, FTF, FSF); ++ break; ++ case div: ++ __ flds(FTF, at_sp()); ++ __ div_s(FSF, FTF, FSF); ++ break; ++ case rem: ++ { ++ __ flds(F16, at_sp()); //x ++ __ fmovd(F17, FSF); ++ Label nan, cont, end; ++ ++ // y = 0.0f ++ __ fbeq(F17, nan); ++ // x = NaN infinity ++ __ boundary_test(F16, GP); ++ __ beq(GP, nan); ++ // y = NaN ++ __ boundary_test(F17, GP); ++ __ bne(GP, cont); ++ __ fimovd(AT, F17); ++ __ slll(GP, AT, 12); ++ __ bne(GP, nan); ++ ++ __ BIND(cont); ++ __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::frem), 2); ++ __ beq(R0, end); ++ ++ __ BIND(nan); ++ __ fdivd(FSF, F31, F31); ++ __ BIND(end); ++ } ++ ++ break; ++ default : ShouldNotReachHere(); ++ } ++ ++ __ add_simm16(SP, SP, 1 * wordSize); ++} ++ ++// result in SSF||FSF ++// i dont handle the strict flags ++void TemplateTable::dop2(Operation op) { ++ transition(dtos, dtos); ++ switch (op) { ++ case add: ++ __ fldd(FTF, at_sp()); ++ __ add_d(FSF, FTF, FSF); ++ break; ++ case sub: ++ __ fldd(FTF, at_sp()); ++ __ sub_d(FSF, FTF, FSF); ++ break; ++ case mul: ++ __ fldd(FTF, at_sp()); ++ __ mul_d(FSF, FTF, FSF); ++ break; ++ case div: ++ __ fldd(FTF, at_sp()); ++ __ div_d(FSF, FTF, FSF); ++ break; ++ case rem: ++ { ++ __ fldd(F16, at_sp()); //x ++ __ fmovd(F17, FSF); ++ Label nan, cont, end; ++ // y = 0.0f ++ __ fbeq(F17, nan); ++ // x = NaN infinity ++ __ boundary_test(F16, GP); ++ __ beq(GP, nan); ++ // y = NaN ++ __ boundary_test(F17, GP); ++ __ bne(GP, cont); ++ __ fimovd(AT, F17); ++ __ slll(GP, AT, 12); ++ __ bne(GP, nan); ++ ++ __ BIND(cont); ++ __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::drem), 2); ++ __ beq(R0, end); ++ ++ __ BIND(nan); ++ __ fdivd(FSF, F31, F31); ++ __ BIND(end); ++ } ++ break; ++ default : ShouldNotReachHere(); ++ } ++ ++ __ add_simm16(SP, SP, 2 * wordSize); ++} ++ ++void TemplateTable::ineg() { ++ transition(itos, itos); ++ __ subw(FSR, R0, FSR); ++} ++ ++void TemplateTable::lneg() { ++ transition(ltos, ltos); ++ __ subl(FSR, R0, FSR); ++} ++ ++void TemplateTable::fneg() { ++ transition(ftos, ftos); ++ __ fneg(FSF, FSF); ++} ++ ++void TemplateTable::dneg() { ++ transition(dtos, dtos); ++ __ fneg(FSF, FSF); ++} ++ ++// used registers : T2 ++void TemplateTable::iinc() { ++ transition(vtos, vtos); ++ locals_index(T2); ++ __ ldw(FSR, T2, 0); ++ __ ldb_signed(AT, at_bcp(2)); // get constant ++ __ addl(FSR, FSR, AT); ++ __ stw(FSR, T2, 0); ++} ++ ++// used register : T2 ++void TemplateTable::wide_iinc() { ++ transition(vtos, vtos); ++ locals_index_wide(T2); ++ __ get_2_byte_integer_at_bcp(FSR, AT, 4); ++ __ hswap(FSR); ++ __ ldw(AT, T2, 0); ++ __ addl(FSR, AT, FSR); ++ __ stw(FSR, T2, 0); ++} ++ ++void TemplateTable::convert() { ++ // Checking ++#ifdef ASSERT ++ { ++ TosState tos_in = ilgl; ++ TosState tos_out = ilgl; ++ switch (bytecode()) { ++ case Bytecodes::_i2l: // fall through ++ case Bytecodes::_i2f: // fall through ++ case Bytecodes::_i2d: // fall through ++ case Bytecodes::_i2b: // fall through ++ case Bytecodes::_i2c: // fall through ++ case Bytecodes::_i2s: tos_in = itos; break; ++ case Bytecodes::_l2i: // fall through ++ case Bytecodes::_l2f: // fall through ++ case Bytecodes::_l2d: tos_in = ltos; break; ++ case Bytecodes::_f2i: // fall through ++ case Bytecodes::_f2l: // fall through ++ case Bytecodes::_f2d: tos_in = ftos; break; ++ case Bytecodes::_d2i: // fall through ++ case Bytecodes::_d2l: // fall through ++ case Bytecodes::_d2f: tos_in = dtos; break; ++ default : ShouldNotReachHere(); ++ } ++ switch (bytecode()) { ++ case Bytecodes::_l2i: // fall through ++ case Bytecodes::_f2i: // fall through ++ case Bytecodes::_d2i: // fall through ++ case Bytecodes::_i2b: // fall through ++ case Bytecodes::_i2c: // fall through ++ case Bytecodes::_i2s: tos_out = itos; break; ++ case Bytecodes::_i2l: // fall through ++ case Bytecodes::_f2l: // fall through ++ case Bytecodes::_d2l: tos_out = ltos; break; ++ case Bytecodes::_i2f: // fall through ++ case Bytecodes::_l2f: // fall through ++ case Bytecodes::_d2f: tos_out = ftos; break; ++ case Bytecodes::_i2d: // fall through ++ case Bytecodes::_l2d: // fall through ++ case Bytecodes::_f2d: tos_out = dtos; break; ++ default : ShouldNotReachHere(); ++ } ++ transition(tos_in, tos_out); ++ } ++#endif // ASSERT ++ ++ // Conversion ++ switch (bytecode()) { ++ case Bytecodes::_i2l: ++ __ addw(FSR, FSR, 0); //ZHJ __ sll(FSR, FSR, 0); ++ break; ++ case Bytecodes::_i2f: ++ if (UseSW8A) { ++ __ cmovws(FSF, FSR); ++ }else { ++ __ ifmovd(F30, FSR); ++ __ fcvtls(FSF, F30); ++ } ++ break; ++ case Bytecodes::_i2d: ++ if (UseSW8A) { ++ __ cmovwd(FSF, FSR); ++ }else { ++ __ ifmovd(F30, FSR); ++ __ fcvtld(FSF, F30); ++ } ++ break; ++ case Bytecodes::_i2b: ++ __ sextb(FSR, FSR); ++ break; ++ case Bytecodes::_i2c: ++ __ zapnot(FSR, FSR, 0x3); ++ break; ++ case Bytecodes::_i2s: ++ __ sexth(FSR, FSR); ++ break; ++ case Bytecodes::_l2i: ++ __ addw(FSR, FSR, 0); ++ break; ++ case Bytecodes::_l2f: ++ if (UseSW8A) { ++ __ cmovls(FSF, FSR); ++ }else { ++ __ ifmovd(FSF, FSR); ++ __ fcvtS2L(FSF, FSF); ++ } ++ break; ++ case Bytecodes::_l2d: ++ if (UseSW8A) { ++ __ cmovld(FSF, FSR); ++ }else { ++ __ ifmovd(FSF, FSR); ++ __ fcvtD2L(FSF, FSF); ++ } ++ break; ++ case Bytecodes::_f2i: ++ { ++ if (UseSW8A) { ++ __ cmovdw_z(FSR, FSF); ++ }else { ++ Label L; ++ ++ __ fmovs(F16, FSF); ++ __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::f2i), 1); ++ __ BIND(L); ++ } ++ } ++ break; ++ case Bytecodes::_f2l: ++ { ++ if (UseSW8A) { ++ __ cmovdl_z(FSR, FSF); ++ }else { ++ Label L; ++ ++ __ fmovs(F16, FSF); ++ __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::f2l), 1); ++ __ BIND(L); ++ } ++ } ++ break; ++ case Bytecodes::_f2d: ++ __ fcvtD2S(FSF, FSF); ++ break; ++ case Bytecodes::_d2i: ++ { ++ if (UseSW8A) { ++ __ cmovdw_z(FSR, FSF); ++ }else { ++ Label L; ++ ++ __ fmovd(F16, FSF); ++ __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::d2i), 1); ++ __ BIND(L); ++ } ++ } ++ break; ++ case Bytecodes::_d2l: ++ { ++ if (UseSW8A) { ++ __ cmovdl_z(FSR, FSF); ++ }else { ++ Label L; ++ ++ __ fmovd(F16, FSF); ++ __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::d2l), 1); ++ __ BIND(L); ++ } ++ } ++ break; ++ case Bytecodes::_d2f: ++ __ fcvtS2D(FSF, FSF); ++ break; ++ default : ++ ShouldNotReachHere(); ++ } ++} ++ ++void TemplateTable::lcmp() { ++ transition(ltos, itos); ++ ++ Label low, high, done; ++ __ pop_l(T0); ++ __ cmplt(AT, T0, FSR); ++ __ bne(AT, low); ++ ++ __ bne(T0, FSR, high); ++ ++ __ ldi(FSR, R0, (long)0); ++ __ beq(R0, done); ++ ++ __ BIND(low); ++ __ ldi(FSR, R0, (long)-1); ++ __ beq(R0, done); ++ ++ __ BIND(high); ++ __ ldi(FSR, R0, (long)1); ++ __ beq(R0, done); ++ ++ __ BIND(done); ++} ++ ++void TemplateTable::float_cmp(bool is_float, int unordered_result) { ++ Label less, done; ++ ++ __ move(FSR, R0); ++ ++ if (is_float) { ++ __ flds(FTF, at_sp()); ++ __ fcmpeq(FcmpRES, FTF, FSF); ++ __ add_simm16(SP, SP, 1 * wordSize); ++ __ fbne(FcmpRES, done); ++ ++ if (unordered_result<0) ++ __ fcmplt_un(FcmpRES, FTF, FSF); ++ else ++ __ fcmplt(FcmpRES, FTF, FSF); ++ } else { ++ __ fldd(FTF, at_sp()); ++ __ fcmpeq(FcmpRES, FTF, FSF); ++ __ add_simm16(SP, SP, 2 * wordSize); ++ __ fbne(FcmpRES, done); ++ ++ if (unordered_result<0) ++ __ fcmplt_un(FcmpRES, FTF, FSF); ++ else ++ __ fcmplt(FcmpRES, FTF, FSF); ++ } ++ __ fbne(FcmpRES, less); ++ __ move(FSR, 1); ++ __ beq(R0, done); ++ __ BIND(less); ++ __ move(FSR, -1); ++ __ BIND(done); ++} ++ ++ ++// used registers : Rmethod, T7, Rnext ++// FSR : return bci, this is defined by the vm specification ++// T2 : MDO taken count ++// Rmethod : method ++// T7 : offset ++// Rnext : next bytecode, this is required by dispatch_base ++void TemplateTable::branch(bool is_jsr, bool is_wide) { ++ __ get_method(Rmethod); ++ __ profile_taken_branch(T7, T2); // only C2 meaningful ++ ++ const ByteSize be_offset = MethodCounters::backedge_counter_offset() + ++ InvocationCounter::counter_offset(); ++ const ByteSize inv_offset = MethodCounters::invocation_counter_offset() + ++ InvocationCounter::counter_offset(); ++ ++ // Load up T4 with the branch displacement ++ if (!is_wide) { ++ __ ldb_signed(T7, BCP, 1); ++ __ ldbu(AT, BCP, 2); ++ __ slll(T7, T7, 8); ++ __ or_ins(T7, T7, AT); ++ } else { ++ __ get_4_byte_integer_at_bcp(T7, AT, 1); ++ __ swap(T7); ++ } ++ ++ // Handle all the JSR stuff here, then exit. ++ // It's much shorter and cleaner than intermingling with the ++ // non-JSR normal-branch stuff occuring below. ++ if (is_jsr) { ++ // Pre-load the next target bytecode into Rnext ++ __ addl(AT, BCP, T7); ++ __ ldbu(Rnext, AT, 0); ++ ++ // compute return address as bci in FSR ++ __ add_simm16(FSR, BCP, (is_wide?5:3) - in_bytes(ConstMethod::codes_offset())); ++ __ ldl(AT, Rmethod, in_bytes(Method::const_offset())); ++ __ subl(FSR, FSR, AT); ++ // Adjust the bcp in BCP by the displacement in T7 ++ __ addl(BCP, BCP, T7); ++ // jsr returns atos that is not an oop ++ // __ dispatch_only_noverify(atos); ++ // Push return address ++ __ push_i(FSR); ++ // jsr returns vtos ++ __ dispatch_only_noverify(vtos); ++ ++ return; ++ } ++ ++ // Normal (non-jsr) branch handling ++ ++ // Adjust the bcp in S0 by the displacement in T4 ++ __ addl(BCP, BCP, T7); ++ ++ assert(UseLoopCounter || !UseOnStackReplacement, "on-stack-replacement requires loop counters"); ++ Label backedge_counter_overflow; ++ Label profile_method; ++ Label dispatch; ++ if (UseLoopCounter) { ++ // increment backedge counter for backward branches ++ // Rmethod: method ++ // T4: target offset ++ // BCP: target bcp ++ // LVP: locals pointer ++ __ bgt(T7, dispatch); // check if forward or backward branch ++ ++ // check if MethodCounters exists ++ Label has_counters; ++ __ ldl(AT, Rmethod, in_bytes(Method::method_counters_offset())); // use AT as MDO, TEMP ++ __ bne(AT, has_counters); ++ //__ push(T3); ++ __ call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::build_method_counters), ++ Rmethod); ++ //__ pop(T3); ++ __ ldl(AT, Rmethod, in_bytes(Method::method_counters_offset())); // use AT as MDO, TEMP ++ __ beq(AT, dispatch); ++ __ BIND(has_counters); ++ ++ if (TieredCompilation) { ++ Label no_mdo; ++ int increment = InvocationCounter::count_increment; ++ int mask = ((1 << Tier0BackedgeNotifyFreqLog) - 1) << InvocationCounter::count_shift; ++ if (ProfileInterpreter) { ++ // Are we profiling? ++ __ ldl(T0, Address(Rmethod, in_bytes(Method::method_data_offset()))); ++ __ beq(T0, no_mdo); ++ // Increment the MDO backedge counter ++ const Address mdo_backedge_counter(T0, in_bytes(MethodData::backedge_counter_offset()) + ++ in_bytes(InvocationCounter::counter_offset())); ++ __ increment_mask_and_jump(mdo_backedge_counter, increment, mask, ++ T1, false, Assembler::zero, &backedge_counter_overflow); ++ __ beq(R0, dispatch); ++ } ++ __ BIND(no_mdo); ++ // Increment backedge counter in MethodCounters* ++ __ ldl(T0, Address(Rmethod, Method::method_counters_offset())); ++ __ increment_mask_and_jump(Address(T0, be_offset), increment, mask, ++ T1, false, Assembler::zero, &backedge_counter_overflow); ++ if (!UseOnStackReplacement) { ++ __ BIND(backedge_counter_overflow); ++ } ++ } else { ++ // increment back edge counter ++ __ ldl(T1, Rmethod, in_bytes(Method::method_counters_offset())); ++ __ ldw(T0, T1, in_bytes(be_offset)); ++ __ increment(T0, InvocationCounter::count_increment); ++ __ stw(T0, T1, in_bytes(be_offset)); ++ ++ // load invocation counter ++ __ ldw(T1, T1, in_bytes(inv_offset)); ++ // buffer bit added, mask no needed ++ ++ // dadd backedge counter & invocation counter ++ __ addl(T1, T1, T0); ++ ++ if (ProfileInterpreter) { ++ // Test to see if we should create a method data oop ++ // T1 : backedge counter & invocation counter ++ __ li32(AT, (long)InvocationCounter::InterpreterProfileLimit); ++ __ cmplt(AT, T1, AT); ++ ++ __ bne(AT, dispatch); ++ ++ // if no method data exists, go to profile method ++ __ test_method_data_pointer(T1, profile_method); ++ ++ if (UseOnStackReplacement) { ++ __ li32(AT, (long)InvocationCounter::InterpreterBackwardBranchLimit); ++ __ cmplt(AT, T2, AT); ++ ++ __ bne(AT, dispatch); ++ ++ // When ProfileInterpreter is on, the backedge_count comes ++ // from the methodDataOop, which value does not get reset on ++ // the call to frequency_counter_overflow(). ++ // To avoid excessive calls to the overflow routine while ++ // the method is being compiled, dadd a second test to make ++ // sure the overflow function is called only once every ++ // overflow_frequency. ++ const int overflow_frequency = 1024; ++ __ ldi(GP, R0, overflow_frequency-1); ++ __ and_reg(AT, T2, GP); ++ __ beq(AT, backedge_counter_overflow); ++ } ++ } else { ++ if (UseOnStackReplacement) { ++ // check for overflow against AT, which is the sum of the counters ++ __ li32(AT, (long)InvocationCounter::InterpreterBackwardBranchLimit); ++ __ cmplt(AT, T1, AT); ++ __ beq(AT, backedge_counter_overflow); ++ } ++ } ++ } ++ __ BIND(dispatch); ++ } ++ ++ // Pre-load the next target bytecode into Rnext ++ __ ldbu(Rnext, BCP, 0); ++ ++ // continue with the bytecode @ target ++ // FSR: return bci for jsr's, unused otherwise ++ // Rnext: target bytecode ++ // BCP: target bcp ++ __ dispatch_only(vtos); ++ ++ if (UseLoopCounter) { ++ if (ProfileInterpreter) { ++ // Out-of-line code to allocate method data oop. ++ __ BIND(profile_method); ++ __ call_VM(NOREG, CAST_FROM_FN_PTR(address, InterpreterRuntime::profile_method)); ++ __ ldbu(Rnext, BCP, 0); ++ __ set_method_data_pointer_for_bcp(); ++ __ beq(R0, dispatch); ++ } ++ ++ if (UseOnStackReplacement) { ++ // invocation counter overflow ++ __ BIND(backedge_counter_overflow); ++ __ subl(T7, BCP, T7); // branch bcp ++ call_VM(NOREG, CAST_FROM_FN_PTR(address, ++ InterpreterRuntime::frequency_counter_overflow), T7); ++ __ ldbu(Rnext, BCP, 0); ++ ++ // V0: osr nmethod (osr ok) or NULL (osr not possible) ++ // T4: osr adapter frame return address ++ // Rnext: target bytecode ++ // LVP: locals pointer ++ // BCP: bcp ++ __ beq(V0, dispatch); ++ // nmethod may have been invalidated (VM may block upon call_VM return) ++ __ ldw(T3, V0, nmethod::entry_bci_offset()); ++ __ move(AT, InvalidOSREntryBci); ++ __ beq(AT, T3, dispatch); ++ // We need to prepare to execute the OSR method. First we must ++ // migrate the locals and monitors off of the stack. ++ //V0: osr nmethod (osr ok) or NULL (osr not possible) ++ //T4: osr adapter frame return address ++ //Rnext: target bytecode ++ //LVP: locals pointer ++ //BCP: bcp ++ __ move(BCP, V0); ++ const Register thread = S2thread; ++ call_VM(noreg, CAST_FROM_FN_PTR(address, SharedRuntime::OSR_migration_begin)); ++ ++ // V0 is OSR buffer, move it to expected parameter location ++ __ move(A1, V0); ++ ++ // pop the interpreter frame ++ __ ldl(T7, Address(FP, frame::interpreter_frame_sender_sp_offset * wordSize)); ++ __ leave(); // remove frame anchor ++ __ move(LVP, RA); ++ __ move(SP, T7); ++ ++ __ move(AT, -(StackAlignmentInBytes)); ++ __ and_reg(SP, SP, AT); ++ ++ // push the (possibly adjusted) return address ++ __ ldl(AT, BCP, nmethod::osr_entry_point_offset()); ++ __ jmp(AT); ++ } ++ } ++} ++ ++ ++void TemplateTable::if_0cmp(Condition cc) { ++ transition(itos, vtos); ++ // assume branch is more often taken than not (loops use backward branches) ++ Label not_taken; ++ switch(cc) { ++ case not_equal: ++ __ beq(FSR, not_taken); ++ break; ++ case equal: ++ __ bne(FSR, not_taken); ++ break; ++ case less: ++ __ bge(FSR, not_taken); ++ break; ++ case less_equal: ++ __ bgt(FSR, not_taken); ++ break; ++ case greater: ++ __ ble(FSR, not_taken); ++ break; ++ case greater_equal: ++ __ blt(FSR, not_taken); ++ break; ++ } ++ ++ branch(false, false); ++ ++ __ BIND(not_taken); ++ __ profile_not_taken_branch(FSR); ++} ++ ++void TemplateTable::if_icmp(Condition cc) { ++ transition(itos, vtos); ++ // assume branch is more often taken than not (loops use backward branches) ++ Label not_taken; ++ ++ __ pop_i(SSR); ++ switch(cc) { ++ case not_equal: ++ __ beq(SSR, FSR, not_taken); ++ break; ++ case equal: ++ __ bne(SSR, FSR, not_taken); ++ break; ++ case less: ++ __ cmplt(AT, SSR, FSR); ++ __ beq(AT, not_taken); ++ break; ++ case less_equal: ++ __ cmplt(AT, FSR, SSR); ++ __ bne(AT, not_taken); ++ break; ++ case greater: ++ __ cmplt(AT, FSR, SSR); ++ __ beq(AT, not_taken); ++ break; ++ case greater_equal: ++ __ cmplt(AT, SSR, FSR); ++ __ bne(AT, not_taken); ++ break; ++ } ++ ++ branch(false, false); ++ ++ __ BIND(not_taken); ++ __ profile_not_taken_branch(FSR); ++} ++ ++void TemplateTable::if_nullcmp(Condition cc) { ++ transition(atos, vtos); ++ // assume branch is more often taken than not (loops use backward branches) ++ Label not_taken; ++ switch(cc) { ++ case not_equal: ++ __ beq(FSR, not_taken); ++ break; ++ case equal: ++ __ bne(FSR, not_taken); ++ break; ++ default: ++ ShouldNotReachHere(); ++ } ++ ++ branch(false, false); ++ ++ __ BIND(not_taken); ++ __ profile_not_taken_branch(FSR); ++} ++ ++ ++void TemplateTable::if_acmp(Condition cc) { ++ transition(atos, vtos); ++ // assume branch is more often taken than not (loops use backward branches) ++ Label not_taken; ++ // __ lw(SSR, SP, 0); ++ __ pop_ptr(SSR); ++ switch(cc) { ++ case not_equal: ++ __ beq(SSR, FSR, not_taken); ++ break; ++ case equal: ++ __ bne(SSR, FSR, not_taken); ++ break; ++ default: ++ ShouldNotReachHere(); ++ } ++ ++ branch(false, false); ++ ++ __ BIND(not_taken); ++ __ profile_not_taken_branch(FSR); ++} ++ ++// used registers : T1, T2, T3 ++// T1 : method ++// T2 : returb bci ++void TemplateTable::ret() { ++ transition(vtos, vtos); ++ ++ locals_index(T2); ++ __ ldl(T2, T2, 0); ++ __ profile_ret(T2, T3); ++ ++ __ get_method(T1); ++ __ ldl(BCP, T1, in_bytes(Method::const_offset())); ++ __ addl(BCP, BCP, T2); ++ __ add_simm16(BCP, BCP, in_bytes(ConstMethod::codes_offset())); ++ ++ __ dispatch_next(vtos); ++} ++ ++// used registers : T1, T2, T3 ++// T1 : method ++// T2 : returb bci ++void TemplateTable::wide_ret() { ++ transition(vtos, vtos); ++ ++ locals_index_wide(T2); ++ __ ldl(T2, T2, 0); // get return bci, compute return bcp ++ __ profile_ret(T2, T3); ++ ++ __ get_method(T1); ++ __ ldl(BCP, T1, in_bytes(Method::const_offset())); ++ __ addl(BCP, BCP, T2); ++ __ add_simm16(BCP, BCP, in_bytes(ConstMethod::codes_offset())); ++ ++ __ dispatch_next(vtos); ++} ++ ++// used register T2, T3, T7, Rnext ++// T2 : bytecode pointer ++// T3 : low ++// T7 : high ++// Rnext : dest bytecode, required by dispatch_base ++void TemplateTable::tableswitch() { ++ Label default_case, continue_execution; ++ transition(itos, vtos); ++ ++ // align BCP ++ __ add_simm16(T2, BCP, BytesPerInt); ++ __ ldi(AT, R0, -BytesPerInt); ++ __ and_reg(T2, T2, AT); ++ ++ // load lo & hi ++ __ ldw(T3, T2, 1 * BytesPerInt); ++ __ swap(T3); ++ __ ldw(T7, T2, 2 * BytesPerInt); ++ __ swap(T7); ++ ++ // check against lo & hi ++ __ cmplt(AT, FSR, T3); ++ __ bne(AT, default_case); ++ ++ __ cmplt(AT, T7, FSR); ++ __ bne(AT, default_case); ++ ++ // lookup dispatch offset, in T7 big endian ++ __ subl(FSR, FSR, T3); ++ __ slll(AT, FSR, Address::times_4); ++ __ addl(AT, T2, AT); ++ __ ldw(T7, AT, 3 * BytesPerInt); ++ __ profile_switch_case(FSR, T12, T3); ++ ++ __ BIND(continue_execution); ++ __ swap(T7); ++ __ addl(BCP, BCP, T7); ++ __ ldbu(Rnext, BCP, 0); ++ __ dispatch_only(vtos); ++ ++ // handle default ++ __ BIND(default_case); ++ __ profile_switch_default(FSR); ++ __ ldw(T7, T2, 0); ++ __ beq(R0, continue_execution); ++} ++ ++void TemplateTable::lookupswitch() { ++ transition(itos, itos); ++ __ stop("lookupswitch bytecode should have been rewritten"); ++} ++ ++// used registers : T2, T3, T7, Rnext ++// T2 : bytecode pointer ++// T3 : pair index ++// T7 : offset ++// Rnext : dest bytecode ++// the data after the opcode is the same as lookupswitch ++// see Rewriter::rewrite_method for more information ++void TemplateTable::fast_linearswitch() { ++ transition(itos, vtos); ++ Label loop_entry, loop, found, continue_execution; ++ ++ // swap FSR so we can avoid swapping the table entries ++ __ swap(FSR); ++ ++ // align BCP ++ __ add_simm16(T2, BCP, BytesPerInt); ++ __ ldi(AT, R0, -BytesPerInt); ++ __ and_reg(T2, T2, AT); ++ ++ // set counter ++ __ ldw(T3, T2, BytesPerInt); ++ __ swap(T3); ++ __ beq(R0, loop_entry); ++ ++ // table search ++ __ BIND(loop); ++ // get the entry value ++ __ slll(AT, T3, Address::times_8); ++ __ addl(AT, T2, AT); ++ __ ldw(AT, AT, 2 * BytesPerInt); ++ ++ // found? ++ __ beq(FSR, AT, found); ++ ++ __ BIND(loop_entry); ++ __ subl(T3, T3, 1); ++ __ bge(T3, loop); ++ ++ // default case ++ __ profile_switch_default(FSR); ++ __ ldw(T7, T2, 0); ++ __ beq(R0, continue_execution); ++ ++ // entry found -> get offset ++ __ BIND(found); ++ __ slll(AT, T3, Address::times_8); ++ __ addl(AT, T2, AT); ++ __ ldw(T7, AT, 3 * BytesPerInt); ++ __ profile_switch_case(T3, FSR, T2); ++ ++ // continue execution ++ __ BIND(continue_execution); ++ __ swap(T7); ++ __ addl(BCP, BCP, T7); ++ __ ldbu(Rnext, BCP, 0); ++ __ dispatch_only(vtos); ++} ++ ++// used registers : T0, T1, T2, T3, T7, Rnext ++// T2 : pairs address(array) ++// Rnext : dest bytecode ++// the data after the opcode is the same as lookupswitch ++// see Rewriter::rewrite_method for more information ++void TemplateTable::fast_binaryswitch() { ++ transition(itos, vtos); ++ // Implementation using the following core algorithm: ++ // ++ // int binary_search(int key, LookupswitchPair* array, int n) { ++ // // Binary search according to "Methodik des Programmierens" by ++ // // Edsger W. Dijkstra and W.H.J. Feijen, Addison Wesley Germany 1985. ++ // int i = 0; ++ // int j = n; ++ // while (i+1 < j) { ++ // // invariant P: 0 <= i < j <= n and (a[i] <= key < a[j] or Q) ++ // // with Q: for all i: 0 <= i < n: key < a[i] ++ // // where a stands for the array and assuming that the (inexisting) ++ // // element a[n] is infinitely big. ++ // int h = (i + j) >> 1; ++ // // i < h < j ++ // if (key < array[h].fast_match()) { ++ // j = h; ++ // } else { ++ // i = h; ++ // } ++ // } ++ // // R: a[i] <= key < a[i+1] or Q ++ // // (i.e., if key is within array, i is the correct index) ++ // return i; ++ // } ++ ++ // register allocation ++ const Register array = T2; ++ const Register i = T3, j = T7; ++ const Register h = T1; ++ const Register temp = T0; ++ const Register key = FSR; ++ ++ // setup array ++ __ add_simm16(array, BCP, 3*BytesPerInt); ++ __ ldi(AT, R0, -BytesPerInt); ++ __ and_reg(array, array, AT); ++ ++ // initialize i & j ++ __ move(i, R0); ++ __ ldw(j, array, - 1 * BytesPerInt); ++ // Convert j into native byteordering ++ __ swap(j); ++ ++ // and start ++ Label entry; ++ __ beq(R0, entry); ++ ++ // binary search loop ++ { ++ Label loop; ++ __ BIND(loop); ++ // int h = (i + j) >> 1; ++ __ addl(h, i, j); ++ __ srll(h, h, 1); ++ // if (key < array[h].fast_match()) { ++ // j = h; ++ // } else { ++ // i = h; ++ // } ++ // Convert array[h].match to native byte-ordering before compare ++ __ slll(AT, h, Address::times_8); ++ __ addl(AT, array, AT); ++ __ ldw(temp, AT, 0 * BytesPerInt); ++ __ swap(temp); ++ ++ { ++ Label set_i, end_of_if; ++ __ cmplt(AT, key, temp); ++ __ beq(AT, set_i); ++ ++ __ move(j, h); ++ __ beq(R0, end_of_if); ++ ++ __ BIND(set_i); ++ __ move(i, h); ++ ++ __ BIND(end_of_if); ++ } ++ // while (i+1 < j) ++ __ BIND(entry); ++ __ addl(h, i, 1); ++ __ cmplt(AT, h, j); ++ __ bne(AT, loop); ++ } ++ ++ // end of binary search, result index is i (must check again!) ++ Label default_case; ++ // Convert array[i].match to native byte-ordering before compare ++ __ slll(AT, i, Address::times_8); ++ __ addl(AT, array, AT); ++ __ ldw(temp, AT, 0 * BytesPerInt); ++ __ swap(temp); ++ __ bne(key, temp, default_case); ++ ++ // entry found -> j = offset ++ __ slll(AT, i, Address::times_8); ++ __ addl(AT, array, AT); ++ __ ldw(j, AT, 1 * BytesPerInt); ++ __ profile_switch_case(i, key, array); ++ __ swap(j); ++ ++ __ addl(BCP, j, BCP); ++ __ ldbu(Rnext, BCP, 0); ++ __ dispatch_only(vtos); ++ ++ // default case -> j = default offset ++ __ BIND(default_case); ++ __ profile_switch_default(i); ++ __ ldw(j, array, - 2 * BytesPerInt); ++ __ swap(j); ++ __ addl(BCP, BCP, j); ++ __ ldbu(Rnext, BCP, 0); ++ __ dispatch_only(vtos); ++} ++ ++void TemplateTable::_return(TosState state) { ++ transition(state, state); ++ assert(_desc->calls_vm(), ++ "inconsistent calls_vm information"); // call in remove_activation ++ ++ if (_desc->bytecode() == Bytecodes::_return_register_finalizer) { ++ assert(state == vtos, "only valid state"); ++ __ ldl(T1, aaddress(0)); ++ __ load_klass(LVP, T1); ++ __ ldw(LVP, LVP, in_bytes(Klass::access_flags_offset())); ++ __ move(AT, JVM_ACC_HAS_FINALIZER); ++ __ and_reg(AT, AT, LVP); ++ Label skip_register_finalizer; ++ __ beq(AT, skip_register_finalizer); ++ __ call_VM(noreg, CAST_FROM_FN_PTR(address, ++ InterpreterRuntime::register_finalizer), T1); ++ __ BIND(skip_register_finalizer); ++ } ++ ++ // Narrow result if state is itos but result type is smaller. ++ // Need to narrow in the return bytecode rather than in generate_return_entry ++ // since compiled code callers expect the result to already be narrowed. ++ if (state == itos) { ++ __ narrow(FSR); ++ } ++ ++ __ remove_activation(state, T12); ++ if(UseWmemb) ++ __ wmemb(); ++ else ++ __ memb(); ++ ++ __ jmp(T12); ++} ++ ++// ---------------------------------------------------------------------------- ++// Volatile variables demand their effects be made known to all CPU's ++// in order. Store buffers on most chips allow reads & writes to ++// reorder; the JMM's ReadAfterWrite.java test fails in -Xint mode ++// without some kind of memory barrier (i.e., it's not sufficient that ++// the interpreter does not reorder volatile references, the hardware ++// also must not reorder them). ++// ++// According to the new Java Memory Model (JMM): ++// (1) All volatiles are serialized wrt to each other. ALSO reads & ++// writes act as aquire & release, so: ++// (2) A read cannot let unrelated NON-volatile memory refs that ++// happen after the read float up to before the read. It's OK for ++// non-volatile memory refs that happen before the volatile read to ++// float down below it. ++// (3) Similar a volatile write cannot let unrelated NON-volatile ++// memory refs that happen BEFORE the write float down to after the ++// write. It's OK for non-volatile memory refs that happen after the ++// volatile write to float up before it. ++// ++// We only put in barriers around volatile refs (they are expensive), ++// not _between_ memory refs (that would require us to track the ++// flavor of the previous memory refs). Requirements (2) and (3) ++// require some barriers before volatile stores and after volatile ++// loads. These nearly cover requirement (1) but miss the ++// volatile-store-volatile-load case. This final case is placed after ++// volatile-stores although it could just as well go before ++// volatile-loads. ++void TemplateTable::volatile_barrier() { ++ if(os::is_MP()) __ memb(); ++} ++ ++// we dont shift left 2 bits in get_cache_and_index_at_bcp ++// for we always need shift the index we use it. the ConstantPoolCacheEntry ++// is 16-byte long, index is the index in ++// ConstantPoolCache, so cache + base_offset() + index * 16 is ++// the corresponding ConstantPoolCacheEntry ++// used registers : T2 ++// NOTE : the returned index need also shift left 4 to get the address! ++void TemplateTable::resolve_cache_and_index(int byte_no, ++ Register Rcache, ++ Register index, ++ size_t index_size) { ++ assert(byte_no == f1_byte || byte_no == f2_byte, "byte_no out of range"); ++ const Register temp = A1; ++ assert_different_registers(Rcache, index); ++ ++ Label resolved, Ldone; ++ __ get_cache_and_index_and_bytecode_at_bcp(Rcache, index, temp, byte_no, 1, index_size); ++ // is resolved? ++ int i = (int)bytecode(); ++ __ add_simm16(temp, temp, -i); ++ __ beq(temp, resolved); ++ // resolve first time through ++ address entry; ++ switch (bytecode()) { ++ case Bytecodes::_getstatic : // fall through ++ case Bytecodes::_putstatic : // fall through ++ case Bytecodes::_getfield : // fall through ++ case Bytecodes::_putfield : ++ entry = CAST_FROM_FN_PTR(address, InterpreterRuntime::resolve_get_put); ++ break; ++ case Bytecodes::_invokevirtual : // fall through ++ case Bytecodes::_invokespecial : // fall through ++ case Bytecodes::_invokestatic : // fall through ++ case Bytecodes::_invokeinterface: ++ entry = CAST_FROM_FN_PTR(address, InterpreterRuntime::resolve_invoke); ++ break; ++ case Bytecodes::_invokehandle: ++ entry = CAST_FROM_FN_PTR(address, InterpreterRuntime::resolve_invokehandle); ++ break; ++ case Bytecodes::_invokedynamic: ++ entry = CAST_FROM_FN_PTR(address, InterpreterRuntime::resolve_invokedynamic); ++ break; ++ default : ++ fatal(err_msg("unexpected bytecode: %s", Bytecodes::name(bytecode()))); ++ break; ++ } ++ ++ __ move(temp, i); ++ __ call_VM(NOREG, entry, temp); ++ ++ // Update registers with resolved info ++ __ get_cache_and_index_at_bcp(Rcache, index, 1, index_size); ++ __ beq(R0, Ldone); ++ ++ __ BIND(resolved); ++ __ memb(); // Order load wrt. succeeding loads. ++ __ BIND(Ldone); ++} ++ ++// The Rcache and index registers must be set before call ++void TemplateTable::load_field_cp_cache_entry(Register obj, ++ Register cache, ++ Register index, ++ Register off, ++ Register flags, ++ bool is_static = false) { ++ assert_different_registers(cache, index, flags, off); ++ ++ ByteSize cp_base_offset = ConstantPoolCache::base_offset(); ++ // Field offset ++ __ slll(AT, index, Address::times_ptr); ++ __ addl(AT, cache, AT); ++ __ ldl(off, AT, in_bytes(cp_base_offset + ConstantPoolCacheEntry::f2_offset())); ++ // Flags ++ __ ldl(flags, AT, in_bytes(cp_base_offset + ConstantPoolCacheEntry::flags_offset())); ++ ++ // klass overwrite register ++ if (is_static) { ++ __ ldl(obj, AT, in_bytes(cp_base_offset + ConstantPoolCacheEntry::f1_offset())); ++ const int mirror_offset = in_bytes(Klass::java_mirror_offset()); ++ __ ldl(obj, Address(obj, mirror_offset)); ++ ++ //__ verify_oop(obj); ++ } ++} ++ ++// get the method, itable_index and flags of the current invoke ++void TemplateTable::load_invoke_cp_cache_entry(int byte_no, ++ Register method, ++ Register itable_index, ++ Register flags, ++ bool is_invokevirtual, ++ bool is_invokevfinal, /*unused*/ ++ bool is_invokedynamic) { ++ // setup registers ++ const Register cache = T3; ++ const Register index = T1; ++ assert_different_registers(method, flags); ++ assert_different_registers(method, cache, index); ++ assert_different_registers(itable_index, flags); ++ assert_different_registers(itable_index, cache, index); ++ assert(is_invokevirtual == (byte_no == f2_byte), "is invokevirtual flag redundant"); ++ // determine constant pool cache field offsets ++ const int method_offset = in_bytes( ++ ConstantPoolCache::base_offset() + ++ ((byte_no == f2_byte) ++ ? ConstantPoolCacheEntry::f2_offset() ++ : ConstantPoolCacheEntry::f1_offset())); ++ const int flags_offset = in_bytes(ConstantPoolCache::base_offset() + ++ ConstantPoolCacheEntry::flags_offset()); ++ // access constant pool cache fields ++ const int index_offset = in_bytes(ConstantPoolCache::base_offset() + ++ ConstantPoolCacheEntry::f2_offset()); ++ ++ size_t index_size = (is_invokedynamic ? sizeof(u4): sizeof(u2)); ++ resolve_cache_and_index(byte_no, cache, index, index_size); ++ ++ //assert(wordSize == 8, "adjust code below"); ++ // note we shift 4 not 2, for we get is the true inde ++ // of ConstantPoolCacheEntry, not the shifted 2-bit index as x86 version ++ __ slll(AT, index, Address::times_ptr); ++ __ addl(AT, cache, AT); ++ __ ldl(method, AT, method_offset); ++ ++ if (itable_index != NOREG) { ++ __ ldl(itable_index, AT, index_offset); ++ } ++ __ ldl(flags, AT, flags_offset); ++} ++ ++// The registers cache and index expected to be set before call. ++// Correct values of the cache and index registers are preserved. ++void TemplateTable::jvmti_post_field_access(Register cache, Register index, ++ bool is_static, bool has_tos) { ++ // do the JVMTI work here to avoid disturbing the register state below ++ // We use c_rarg registers here because we want to use the register used in ++ // the call to the VM ++ if (JvmtiExport::can_post_field_access()) { ++ // Check to see if a field access watch has been set before we ++ // take the time to call into the VM. ++ Label L1; ++ // kill FSR ++ Register tmp1 = T2; ++ Register tmp2 = T1; ++ Register tmp3 = T3; ++ assert_different_registers(cache, index, AT); ++ __ li(AT, (intptr_t)JvmtiExport::get_field_access_count_addr()); ++ __ ldw(AT, AT, 0); ++ __ beq(AT, L1); ++ ++ __ get_cache_and_index_at_bcp(tmp2, tmp3, 1); ++ ++ // cache entry pointer ++ __ add_simm16(tmp2, tmp2, in_bytes(ConstantPoolCache::base_offset())); ++ __ shl(tmp3, LogBytesPerWord); ++ __ addl(tmp2, tmp2, tmp3); ++ if (is_static) { ++ __ move(tmp1, R0); ++ } else { ++ __ ldl(tmp1, SP, 0); ++ __ verify_oop(tmp1); ++ } ++ // tmp1: object pointer or NULL ++ // tmp2: cache entry pointer ++ // tmp3: jvalue object on the stack ++ __ call_VM(NOREG, CAST_FROM_FN_PTR(address, ++ InterpreterRuntime::post_field_access), ++ tmp1, tmp2, tmp3); ++ __ get_cache_and_index_at_bcp(cache, index, 1); ++ __ BIND(L1); ++ } ++} ++ ++void TemplateTable::pop_and_check_object(Register r) { ++ __ pop_ptr(r); ++ __ null_check(r); // for field access must check obj. ++ __ verify_oop(r); ++} ++ ++// used registers : T1, T2, T3, T1 ++// T1 : flags ++// T2 : off ++// T3 : obj ++// T1 : field address ++// The flags 31, 30, 29, 28 together build a 4 bit number 0 to 8 with the ++// following mapping to the TosState states: ++// btos: 0 ++// ctos: 1 ++// stos: 2 ++// itos: 3 ++// ltos: 4 ++// ftos: 5 ++// dtos: 6 ++// atos: 7 ++// vtos: 8 ++// see ConstantPoolCacheEntry::set_field for more info ++void TemplateTable::getfield_or_static(int byte_no, bool is_static) { ++ transition(vtos, vtos); ++ ++ const Register cache = T3; ++ const Register index = T0; ++ ++ const Register obj = T3; ++ const Register off = T2; ++ const Register flags = T1; ++ ++ const Register scratch = T11; ++ ++ resolve_cache_and_index(byte_no, cache, index, sizeof(u2)); ++ jvmti_post_field_access(cache, index, is_static, false); ++ load_field_cp_cache_entry(obj, cache, index, off, flags, is_static); ++ ++ { ++ __ move(scratch, 1 << ConstantPoolCacheEntry::is_volatile_shift); ++ __ and_reg(scratch, scratch, flags); ++ ++ Label notVolatile; ++ __ beq(scratch, notVolatile); ++ volatile_barrier(); ++ __ BIND(notVolatile); ++ } ++ ++ if (!is_static) pop_and_check_object(obj); ++ __ addl(index, obj, off); ++ ++ ++ Label Done, notByte, notBool, notInt, notShort, notChar, ++ notLong, notFloat, notObj, notDouble; ++ ++ assert(btos == 0, "change code, btos != 0"); ++ __ srll(flags, flags, ConstantPoolCacheEntry::tos_state_shift); ++ __ and_imm8(flags, flags, ConstantPoolCacheEntry::tos_state_mask); ++ __ bne(flags, notByte); ++ ++ // btos ++ __ ldb_signed(FSR, index, 0); ++ __ stl(FSR, SP, - wordSize); ++ ++ // Rewrite bytecode to be faster ++ if (!is_static) { ++ patch_bytecode(Bytecodes::_fast_bgetfield, T3, T2); ++ } ++ __ add_simm16(SP, SP, - wordSize); ++ __ beq(R0, Done); ++ ++ __ BIND(notByte); ++ __ move(AT, ztos); ++ __ bne(flags, AT, notBool); ++ ++ // ztos ++ __ ldb_signed(FSR, index, 0); ++ __ stl(FSR, SP, - wordSize); ++ ++ // Rewrite bytecode to be faster ++ if (!is_static) { ++ // patch_bytecode(Bytecodes::_fast_igetfield, T3, T2); ++ patch_bytecode(Bytecodes::_fast_bgetfield, T3, T2); ++ } ++ __ add_simm16(SP, SP, - wordSize); ++ __ beq(R0, Done); ++ ++ __ BIND(notBool); ++ __ move(AT, itos); ++ __ bne(flags, AT, notInt); ++ ++ // itos ++ __ ldw(FSR, index, 0); ++ __ stl(FSR, SP, - wordSize); ++ ++ // Rewrite bytecode to be faster ++ if (!is_static) { ++ // patch_bytecode(Bytecodes::_fast_igetfield, T3, T2); ++ patch_bytecode(Bytecodes::_fast_igetfield, T3, T2); ++ } ++ __ add_simm16(SP, SP, - wordSize); ++ __ beq(R0, Done); ++ ++ __ BIND(notInt); ++ __ move(AT, atos); ++ __ bne(flags, AT, notObj); ++ ++ // atos ++ //add for compressedoops ++ __ load_heap_oop(FSR, Address(index, 0)); ++ __ stl(FSR, SP, - wordSize); ++ ++ if (!is_static) { ++ //patch_bytecode(Bytecodes::_fast_agetfield, T3, T2); ++ patch_bytecode(Bytecodes::_fast_agetfield, T3, T2); ++ } ++ __ add_simm16(SP, SP, - wordSize); ++ __ beq(R0, Done); ++ ++ __ BIND(notObj); ++ __ move(AT, ctos); ++ __ bne(flags, AT, notChar); ++ ++ // ctos ++ __ ldhu(FSR, index, 0); ++ __ stl(FSR, SP, - wordSize); ++ ++ if (!is_static) { ++ patch_bytecode(Bytecodes::_fast_cgetfield, T3, T2); ++ } ++ __ add_simm16(SP, SP, - wordSize); ++ __ beq(R0, Done); ++ ++ __ BIND(notChar); ++ __ move(AT, stos); ++ __ bne(flags, AT, notShort); ++ ++ // stos ++ __ ldh_signed(FSR, index, 0); ++ __ stl(FSR, SP, - wordSize); ++ ++ if (!is_static) { ++ patch_bytecode(Bytecodes::_fast_sgetfield, T3, T2); ++ } ++ __ add_simm16(SP, SP, - wordSize); ++ __ beq(R0, Done); ++ ++ __ BIND(notShort); ++ __ move(AT, ltos); ++ __ bne(flags, AT, notLong); ++ ++ // ltos ++ __ ldl(FSR, index, 0 * wordSize); ++ __ stl(FSR, SP, -2 * wordSize); ++ __ stl(R0, SP, -1 * wordSize); ++ ++ // Don't rewrite to _fast_lgetfield for potential volatile case. ++ __ add_simm16(SP, SP, - 2 * wordSize); ++ __ beq(R0, Done); ++ ++ __ BIND(notLong); ++ __ move(AT, ftos); ++ __ bne(flags, AT, notFloat); ++ ++ // ftos ++ __ flds(FSF, index, 0); ++ __ fsts(FSF, SP, - wordSize); ++ ++ if (!is_static) { ++ patch_bytecode(Bytecodes::_fast_fgetfield, T3, T2); ++ } ++ __ add_simm16(SP, SP, - wordSize); ++ __ beq(R0, Done); ++ ++ __ BIND(notFloat); ++ __ move(AT, dtos); ++#ifdef ASSERT ++ __ bne(flags, AT, notDouble); ++#endif ++ ++ // dtos ++ __ fldd(FSF, index, 0 * wordSize); ++ __ fstd(FSF, SP, - 2 * wordSize); ++ __ stl(R0, SP, - 1 * wordSize); ++ ++ if (!is_static) { ++ patch_bytecode(Bytecodes::_fast_dgetfield, T3, T2); ++ } ++ ++ __ add_simm16(SP, SP, - 2 * wordSize); ++ ++#ifdef ASSERT ++ __ beq(R0, Done); ++ __ BIND(notDouble); ++ __ stop("Bad state"); ++#endif ++ ++ __ BIND(Done); ++ ++ { ++ Label notVolatile; ++ __ beq(scratch, notVolatile); ++ volatile_barrier(); ++ __ BIND(notVolatile); ++ } ++} ++ ++ ++void TemplateTable::getfield(int byte_no) { ++ getfield_or_static(byte_no, false); ++} ++ ++void TemplateTable::getstatic(int byte_no) { ++ getfield_or_static(byte_no, true); ++} ++ ++// The registers cache and index expected to be set before call. ++// The function may destroy various registers, just not the cache and index registers. ++void TemplateTable::jvmti_post_field_mod(Register cache, Register index, bool is_static) { ++ transition(vtos, vtos); ++ ++ ByteSize cp_base_offset = ConstantPoolCache::base_offset(); ++ ++ if (JvmtiExport::can_post_field_modification()) { ++ // Check to see if a field modification watch has been set before ++ // we take the time to call into the VM. ++ Label L1; ++ //kill AT, T1, T2, T3, T9 ++ Register tmp1 = T2; ++ Register tmp2 = T1; ++ Register tmp3 = T3; ++ Register tmp4 = T12; ++ assert_different_registers(cache, index, tmp4); ++ ++ __ li(AT, JvmtiExport::get_field_modification_count_addr()); ++ __ ldw(AT, AT, 0); ++ __ beq(AT, L1); ++ ++ __ get_cache_and_index_at_bcp(tmp2, tmp4, 1); ++ ++ if (is_static) { ++ __ move(tmp1, R0); ++ } else { ++ // Life is harder. The stack holds the value on top, followed by ++ // the object. We don't know the size of the value, though; it ++ // could be one or two words depending on its type. As a result, ++ // we must find the type to determine where the object is. ++ Label two_word, valsize_known; ++ __ slll(AT, tmp4, Address::times_8); ++ __ addl(AT, tmp2, AT); ++ __ ldl(tmp3, AT, in_bytes(cp_base_offset + ++ ConstantPoolCacheEntry::flags_offset())); ++ __ shr(tmp3, ConstantPoolCacheEntry::tos_state_shift); ++ ++ ConstantPoolCacheEntry::verify_tos_state_shift(); ++ __ move(tmp1, SP); ++ __ move(AT, ltos); ++ __ beq(tmp3, AT, two_word); ++ __ move(AT, dtos); ++ __ beq(tmp3, AT, two_word); ++ __ add_simm16(tmp1, tmp1, Interpreter::expr_offset_in_bytes(1) ); ++ __ beq(R0, valsize_known); ++ ++ __ BIND(two_word); ++ __ add_simm16(tmp1, tmp1, Interpreter::expr_offset_in_bytes(2)); ++ ++ __ BIND(valsize_known); ++ // setup object pointer ++ __ ldl(tmp1, tmp1, 0*wordSize); ++ } ++ // cache entry pointer ++ __ add_simm16(tmp2, tmp2, in_bytes(cp_base_offset)); ++ __ shl(tmp4, LogBytesPerWord); ++ __ addl(tmp2, tmp2, tmp4); ++ // object (tos) ++ __ move(tmp3, SP); ++ // tmp1: object pointer set up above (NULL if static) ++ // tmp2: cache entry pointer ++ // tmp3: jvalue object on the stack ++ __ call_VM(NOREG, ++ CAST_FROM_FN_PTR(address, ++ InterpreterRuntime::post_field_modification), ++ tmp1, tmp2, tmp3); ++ __ get_cache_and_index_at_bcp(cache, index, 1); ++ __ BIND(L1); ++ } ++} ++ ++// used registers : T0, T1, T2, T3, T11 ++// T1 : flags ++// T2 : off ++// T3 : obj ++// T11 : volatile bit ++// see ConstantPoolCacheEntry::set_field for more info ++void TemplateTable::putfield_or_static(int byte_no, bool is_static) { ++ transition(vtos, vtos); ++ ++ const Register cache = T3; ++ const Register index = T0; ++ const Register obj = T3; ++ const Register off = T2; ++ const Register flags = T1; ++ const Register bc = T3; ++ ++ const Register scratch = T11; ++ ++ resolve_cache_and_index(byte_no, cache, index, sizeof(u2)); ++ jvmti_post_field_mod(cache, index, is_static); ++ load_field_cp_cache_entry(obj, cache, index, off, flags, is_static); ++ ++ Label Done; ++ { ++ __ move(scratch, 1 << ConstantPoolCacheEntry::is_volatile_shift); ++ __ and_reg(scratch, scratch, flags); ++ ++ Label notVolatile; ++ __ beq(scratch, notVolatile); ++ volatile_barrier(); ++ __ BIND(notVolatile); ++ } ++ ++ ++ Label notByte, notBool, notInt, notShort, notChar, notLong, notFloat, notObj, notDouble; ++ ++ assert(btos == 0, "change code, btos != 0"); ++ ++ // btos ++ __ srll(flags, flags, ConstantPoolCacheEntry::tos_state_shift); ++ __ and_imm8(flags, flags, ConstantPoolCacheEntry::tos_state_mask); ++ __ bne(flags, notByte); ++ ++ __ pop(btos); ++ if (!is_static) { ++ pop_and_check_object(obj); ++ } ++ __ addl(AT, obj, off); ++ __ stb(FSR, AT, 0); ++ ++ if (!is_static) { ++ patch_bytecode(Bytecodes::_fast_bputfield, bc, off, true, byte_no); ++ } ++ __ beq(R0, Done); ++ ++ // ztos ++ __ BIND(notByte); ++ __ move(AT, ztos); ++ __ bne(flags, AT, notBool); ++ ++ __ pop(ztos); ++ if (!is_static) { ++ pop_and_check_object(obj); ++ } ++ __ addl(AT, obj, off); ++ __ and_imm8(FSR, FSR, 0x1); ++ __ stb(FSR, AT, 0); ++ ++ if (!is_static) { ++ patch_bytecode(Bytecodes::_fast_zputfield, bc, off, true, byte_no); ++ } ++ __ beq(R0, Done); ++ ++ // itos ++ __ BIND(notBool); ++ __ move(AT, itos); ++ __ bne(flags, AT, notInt); ++ ++ __ pop(itos); ++ if (!is_static) { ++ pop_and_check_object(obj); ++ } ++ __ addl(AT, obj, off); ++ __ stw(FSR, AT, 0); ++ ++ if (!is_static) { ++ patch_bytecode(Bytecodes::_fast_iputfield, bc, off, true, byte_no); ++ } ++ __ beq(R0, Done); ++ ++ // atos ++ __ BIND(notInt); ++ __ move(AT, atos); ++ __ bne(flags, AT, notObj); ++ ++ __ pop(atos); ++ if (!is_static) { ++ pop_and_check_object(obj); ++ } ++ ++ do_oop_store(_masm, Address(obj, off, Address::times_1, 0), FSR, _bs->kind(), false); ++ ++ if (!is_static) { ++ patch_bytecode(Bytecodes::_fast_aputfield, bc, off, true, byte_no); ++ } ++ __ beq(R0, Done); ++ ++ // ctos ++ __ BIND(notObj); ++ __ move(AT, ctos); ++ __ bne(flags, AT, notChar); ++ ++ __ pop(ctos); ++ if (!is_static) { ++ pop_and_check_object(obj); ++ } ++ __ addl(AT, obj, off); ++ __ sth(FSR, AT, 0); ++ if (!is_static) { ++ patch_bytecode(Bytecodes::_fast_cputfield, bc, off, true, byte_no); ++ } ++ __ beq(R0, Done); ++ ++ // stos ++ __ BIND(notChar); ++ __ move(AT, stos); ++ __ bne(flags, AT, notShort); ++ ++ __ pop(stos); ++ if (!is_static) { ++ pop_and_check_object(obj); ++ } ++ __ addl(AT, obj, off); ++ __ sth(FSR, AT, 0); ++ if (!is_static) { ++ patch_bytecode(Bytecodes::_fast_sputfield, bc, off, true, byte_no); ++ } ++ __ beq(R0, Done); ++ ++ // ltos ++ __ BIND(notShort); ++ __ move(AT, ltos); ++ __ bne(flags, AT, notLong); ++ ++ __ pop(ltos); ++ if (!is_static) { ++ pop_and_check_object(obj); ++ } ++ __ addl(AT, obj, off); ++ __ stl(FSR, AT, 0); ++ if (!is_static) { ++ patch_bytecode(Bytecodes::_fast_lputfield, bc, off, true, byte_no); ++ } ++ __ beq(R0, Done); ++ ++ // ftos ++ __ BIND(notLong); ++ __ move(AT, ftos); ++ __ bne(flags, AT, notFloat); ++ ++ __ pop(ftos); ++ if (!is_static) { ++ pop_and_check_object(obj); ++ } ++ __ addl(AT, obj, off); ++ __ fsts(FSF, AT, 0); ++ if (!is_static) { ++ patch_bytecode(Bytecodes::_fast_fputfield, bc, off, true, byte_no); ++ } ++ __ beq(R0, Done); ++ ++ // dtos ++ __ BIND(notFloat); ++ __ move(AT, dtos); ++#ifdef ASSERT ++ __ bne(flags, AT, notDouble); ++#endif ++ ++ __ pop(dtos); ++ if (!is_static) { ++ pop_and_check_object(obj); ++ } ++ __ addl(AT, obj, off); ++ __ fstd(FSF, AT, 0); ++ if (!is_static) { ++ patch_bytecode(Bytecodes::_fast_dputfield, bc, off, true, byte_no); ++ } ++ ++#ifdef ASSERT ++ __ beq(R0, Done); ++ ++ __ BIND(notDouble); ++ __ stop("Bad state"); ++#endif ++ ++ __ BIND(Done); ++ ++ { ++ Label notVolatile; ++ __ beq(scratch, notVolatile); ++ volatile_barrier(); ++ __ BIND(notVolatile); ++ } ++} ++ ++void TemplateTable::putfield(int byte_no) { ++ putfield_or_static(byte_no, false); ++} ++ ++void TemplateTable::putstatic(int byte_no) { ++ putfield_or_static(byte_no, true); ++} ++ ++// used registers : T1, T2, T3 ++// T1 : cp_entry ++// T2 : obj ++// T3 : value pointer ++void TemplateTable::jvmti_post_fast_field_mod() { ++ if (JvmtiExport::can_post_field_modification()) { ++ // Check to see if a field modification watch has been set before ++ // we take the time to call into the VM. ++ Label L2; ++ //kill AT, T1, T2, T3, T11 ++ Register tmp1 = T2; ++ Register tmp2 = T1; ++ Register tmp3 = T3; ++ Register tmp4 = T9; ++ __ li(AT, JvmtiExport::get_field_modification_count_addr()); ++ __ ldw(tmp3, AT, 0); ++ __ beq(tmp3, L2); ++ __ pop_ptr(tmp1); ++ __ verify_oop(tmp1); ++ __ push_ptr(tmp1); ++ switch (bytecode()) { // load values into the jvalue object ++ case Bytecodes::_fast_aputfield: __ push_ptr(FSR); break; ++ case Bytecodes::_fast_bputfield: // fall through ++ case Bytecodes::_fast_zputfield: // fall through ++ case Bytecodes::_fast_sputfield: // fall through ++ case Bytecodes::_fast_cputfield: // fall through ++ case Bytecodes::_fast_iputfield: __ push_i(FSR); break; ++ case Bytecodes::_fast_dputfield: __ push_d(FSF); break; ++ case Bytecodes::_fast_fputfield: __ push_f(); break; ++ case Bytecodes::_fast_lputfield: __ push_l(FSR); break; ++ default: ShouldNotReachHere(); ++ } ++ __ move(tmp3, SP); ++ // access constant pool cache entry ++ __ get_cache_entry_pointer_at_bcp(tmp2, FSR, 1); ++ __ verify_oop(tmp1); ++ // tmp1: object pointer copied above ++ // tmp2: cache entry pointer ++ // tmp3: jvalue object on the stack ++ __ call_VM(NOREG, ++ CAST_FROM_FN_PTR(address, ++ InterpreterRuntime::post_field_modification), ++ tmp1, tmp2, tmp3); ++ ++ switch (bytecode()) { // restore tos values ++ case Bytecodes::_fast_aputfield: __ pop_ptr(FSR); break; ++ case Bytecodes::_fast_bputfield: // fall through ++ case Bytecodes::_fast_zputfield: // fall through ++ case Bytecodes::_fast_sputfield: // fall through ++ case Bytecodes::_fast_cputfield: // fall through ++ case Bytecodes::_fast_iputfield: __ pop_i(FSR); break; ++ case Bytecodes::_fast_dputfield: __ pop_d(); break; ++ case Bytecodes::_fast_fputfield: __ pop_f(); break; ++ case Bytecodes::_fast_lputfield: __ pop_l(FSR); break; ++ default: ShouldNotReachHere(); ++ } ++ __ BIND(L2); ++ } ++} ++ ++// used registers : T2, T3, T1 ++// T2 : index & off & field address ++// T3 : cache & obj ++// T1 : flags ++void TemplateTable::fast_storefield(TosState state) { ++ transition(state, vtos); ++ ++ const Register scratch = T11; ++ ++ ByteSize base = ConstantPoolCache::base_offset(); ++ ++ jvmti_post_fast_field_mod(); ++ ++ // access constant pool cache ++ __ get_cache_and_index_at_bcp(T3, T2, 1); ++ ++ // test for volatile with T1 ++ __ slll(AT, T2, Address::times_8); ++ __ addl(AT, T3, AT); ++ __ ldl(T1, AT, in_bytes(base + ConstantPoolCacheEntry::flags_offset())); ++ ++ // replace index with field offset from cache entry ++ __ ldl(T2, AT, in_bytes(base + ConstantPoolCacheEntry::f2_offset())); ++ ++ Label Done; ++ { ++ __ move(scratch, 1 << ConstantPoolCacheEntry::is_volatile_shift); ++ __ and_reg(scratch, scratch, T1); ++ ++ Label notVolatile; ++ __ beq(scratch, notVolatile); ++ volatile_barrier(); ++ __ BIND(notVolatile); ++ } ++ ++ // Get object from stack ++ pop_and_check_object(T3); ++ ++ if (bytecode() != Bytecodes::_fast_aputfield) { ++ // field address ++ __ addl(T2, T3, T2); ++ } ++ ++ // access field ++ switch (bytecode()) { ++ case Bytecodes::_fast_zputfield: ++ __ and_imm8(FSR, FSR, 0x1); // boolean is true if LSB is 1 ++ // fall through to bputfield ++ case Bytecodes::_fast_bputfield: ++ __ stb(FSR, T2, 0); ++ break; ++ case Bytecodes::_fast_sputfield: // fall through ++ case Bytecodes::_fast_cputfield: ++ __ sth(FSR, T2, 0); ++ break; ++ case Bytecodes::_fast_iputfield: ++ __ stw(FSR, T2, 0); ++ break; ++ case Bytecodes::_fast_lputfield: ++ __ stl(FSR, T2, 0 * wordSize); ++ break; ++ case Bytecodes::_fast_fputfield: ++ __ fsts(FSF, T2, 0); ++ break; ++ case Bytecodes::_fast_dputfield: ++ __ fstd(FSF, T2, 0 * wordSize); ++ break; ++ case Bytecodes::_fast_aputfield: ++ do_oop_store(_masm, Address(T3, T2, Address::times_1, 0), FSR, _bs->kind(), false); ++ break; ++ default: ++ ShouldNotReachHere(); ++ } ++ ++ { ++ Label notVolatile; ++ __ beq(scratch, notVolatile); ++ volatile_barrier(); ++ __ BIND(notVolatile); ++ } ++} ++ ++// used registers : T2, T3, T1 ++// T3 : cp_entry & cache ++// T2 : index & offset ++void TemplateTable::fast_accessfield(TosState state) { ++ transition(atos, state); ++ ++ const Register scratch = T11; ++ ++ // do the JVMTI work here to avoid disturbing the register state below ++ if (JvmtiExport::can_post_field_access()) { ++ // Check to see if a field access watch has been set before we take ++ // the time to call into the VM. ++ Label L1; ++ __ li(AT, (intptr_t)JvmtiExport::get_field_access_count_addr()); ++ __ ldw(T3, AT, 0); ++ __ beq(T3, L1); ++ // access constant pool cache entry ++ __ get_cache_entry_pointer_at_bcp(T3, T1, 1); ++ __ push(FSR); ++ __ verify_oop(FSR); ++ // FSR: object pointer copied above ++ // T3: cache entry pointer ++ __ call_VM(NOREG, ++ CAST_FROM_FN_PTR(address, InterpreterRuntime::post_field_access), ++ FSR, T3); ++ __ pop(FSR); ++ __ BIND(L1); ++ } ++ ++ // access constant pool cache ++ __ get_cache_and_index_at_bcp(T3, T2, 1); ++ // replace index with field offset from cache entry ++ __ slll(AT, T2, Address::times_8); ++ __ addl(AT, T3, AT); ++ __ ldl(T2, AT, in_bytes(ConstantPoolCache::base_offset() + ConstantPoolCacheEntry::f2_offset())); ++ ++ { ++ __ ldl(AT, AT, in_bytes(ConstantPoolCache::base_offset() + ConstantPoolCacheEntry::flags_offset())); ++ __ move(scratch, 1 << ConstantPoolCacheEntry::is_volatile_shift); ++ __ and_reg(scratch, scratch, AT); ++ ++ Label notVolatile; ++ __ beq(scratch, notVolatile); ++ volatile_barrier(); ++ __ BIND(notVolatile); ++ } ++ ++ // FSR: object ++ __ verify_oop(FSR); ++ __ null_check(FSR); ++ // field addresses ++ __ addl(FSR, FSR, T2); ++ ++ // access field ++ switch (bytecode()) { ++ case Bytecodes::_fast_bgetfield: ++ __ ldb_signed(FSR, FSR, 0); ++ break; ++ case Bytecodes::_fast_sgetfield: ++ __ ldh_signed(FSR, FSR, 0); ++ break; ++ case Bytecodes::_fast_cgetfield: ++ __ ldhu(FSR, FSR, 0); ++ break; ++ case Bytecodes::_fast_igetfield: ++ __ ldw(FSR, FSR, 0); ++ break; ++ case Bytecodes::_fast_lgetfield: ++ __ stop("should not be rewritten"); ++ break; ++ case Bytecodes::_fast_fgetfield: ++ __ flds(FSF, FSR, 0); ++ break; ++ case Bytecodes::_fast_dgetfield: ++ __ fldd(FSF, FSR, 0); ++ break; ++ case Bytecodes::_fast_agetfield: ++ //add for compressedoops ++ __ load_heap_oop(FSR, Address(FSR, 0)); ++ __ verify_oop(FSR); ++ break; ++ default: ++ ShouldNotReachHere(); ++ } ++ ++ { ++ Label notVolatile; ++ __ beq(scratch, notVolatile); ++ volatile_barrier(); ++ __ BIND(notVolatile); ++ } ++} ++ ++// generator for _fast_iaccess_0, _fast_aaccess_0, _fast_faccess_0 ++// used registers : T1, T2, T3, T1 ++// T1 : obj & field address ++// T2 : off ++// T3 : cache ++// T1 : index ++void TemplateTable::fast_xaccess(TosState state) { ++ transition(vtos, state); ++ ++ const Register scratch = T11; ++ ++ // get receiver ++ __ ldl(T1, aaddress(0)); ++ // access constant pool cache ++ __ get_cache_and_index_at_bcp(T3, T2, 2); ++ __ slll(AT, T2, Address::times_8); ++ __ addl(AT, T3, AT); ++ __ ldl(T2, AT, in_bytes(ConstantPoolCache::base_offset() + ConstantPoolCacheEntry::f2_offset())); ++ ++ { ++ __ ldl(AT, AT, in_bytes(ConstantPoolCache::base_offset() + ConstantPoolCacheEntry::flags_offset())); ++ __ move(scratch, 1 << ConstantPoolCacheEntry::is_volatile_shift); ++ __ and_reg(scratch, scratch, AT); ++ ++ Label notVolatile; ++ __ beq(scratch, notVolatile); ++ volatile_barrier(); ++ __ BIND(notVolatile); ++ } ++ ++ // make sure exception is reported in correct bcp range (getfield is ++ // next instruction) ++ __ addl(BCP, BCP, 1); ++ __ null_check(T1); ++ __ addl(T1, T1, T2); ++ ++ if (state == itos) { ++ __ ldw(FSR, T1, 0); ++ } else if (state == atos) { ++ __ load_heap_oop(FSR, Address(T1, 0)); ++ __ verify_oop(FSR); ++ } else if (state == ftos) { ++ __ flds(FSF, T1, 0); ++ } else { ++ ShouldNotReachHere(); ++ } ++ __ subl(BCP, BCP, 1); ++ ++ { ++ Label notVolatile; ++ __ beq(scratch, notVolatile); ++ volatile_barrier(); ++ __ BIND(notVolatile); ++ } ++} ++ ++ ++ ++//----------------------------------------------------------------------------- ++// Calls ++ ++void TemplateTable::count_calls(Register method, Register temp) { ++ // implemented elsewhere ++ ShouldNotReachHere(); ++} ++ ++// method, index, recv, flags: T1, T2, T3, T1 ++// byte_no = 2 for _invokevirtual, 1 else ++// T0 : return address ++// get the method & index of the invoke, and push the return address of ++// the invoke(first word in the frame) ++// this address is where the return code jmp to. ++// NOTE : this method will set T3&T1 as recv&flags ++void TemplateTable::prepare_invoke(int byte_no, ++ Register method, // linked method (or i-klass) ++ Register index, // itable index, MethodType, etc. ++ Register recv, // if caller wants to see it ++ Register flags // if caller wants to test it ++ ) { ++ // determine flags ++ const Bytecodes::Code code = bytecode(); ++ const bool is_invokeinterface = code == Bytecodes::_invokeinterface; ++ const bool is_invokedynamic = code == Bytecodes::_invokedynamic; ++ const bool is_invokehandle = code == Bytecodes::_invokehandle; ++ const bool is_invokevirtual = code == Bytecodes::_invokevirtual; ++ const bool is_invokespecial = code == Bytecodes::_invokespecial; ++ const bool load_receiver = (recv != noreg); ++ const bool save_flags = (flags != noreg); ++ assert(load_receiver == (code != Bytecodes::_invokestatic && code != Bytecodes::_invokedynamic),""); ++ assert(save_flags == (is_invokeinterface || is_invokevirtual), "need flags for vfinal"); ++ assert(flags == noreg || flags == T1, "error flags reg."); ++ assert(recv == noreg || recv == T3, "error recv reg."); ++ ++ // setup registers & access constant pool cache ++ if(recv == noreg) recv = T3; ++ if(flags == noreg) flags = T1; ++ assert_different_registers(method, index, recv, flags); ++ ++ // save 'interpreter return address' ++ __ save_bcp(); ++ ++ load_invoke_cp_cache_entry(byte_no, method, index, flags, is_invokevirtual, false, is_invokedynamic); ++ ++ if (is_invokedynamic || is_invokehandle) { ++ Label L_no_push; ++ __ move(AT, (1 << ConstantPoolCacheEntry::has_appendix_shift)); ++ __ and_reg(AT, AT, flags); ++ __ beq(AT, L_no_push); ++ // Push the appendix as a trailing parameter. ++ // This must be done before we get the receiver, ++ // since the parameter_size includes it. ++ Register tmp = SSR; ++ __ push(tmp); ++ __ move(tmp, index); ++ assert(ConstantPoolCacheEntry::_indy_resolved_references_appendix_offset == 0, "appendix expected at index+0"); ++ __ load_resolved_reference_at_index(index, tmp); ++ __ pop(tmp); ++ __ push(index); // push appendix (MethodType, CallSite, etc.) ++ __ BIND(L_no_push); ++ } ++ ++ // load receiver if needed (after appendix is pushed so parameter size is correct) ++ // Note: no return address pushed yet ++ if (load_receiver) { ++ __ move(AT, ConstantPoolCacheEntry::parameter_size_mask); ++ __ and_reg(recv, flags, AT); ++ // Since we won't push RA on stack, no_return_pc_pushed_yet should be 0. ++ const int no_return_pc_pushed_yet = 0; // argument slot correction before we push return address ++ const int receiver_is_at_end = -1; // back off one slot to get receiver ++ Address recv_addr = __ argument_address(recv, no_return_pc_pushed_yet + receiver_is_at_end); ++ __ ldl(recv, recv_addr); ++ __ verify_oop(recv); ++ } ++ if(save_flags) { ++ __ move(BCP, flags); ++ } ++ ++ // compute return type ++ __ srll(flags, flags, ConstantPoolCacheEntry::tos_state_shift); ++ __ and_imm8(flags, flags, 0xf); ++ ++ // Make sure we don't need to mask flags for tos_state_shift after the above shift ++ ConstantPoolCacheEntry::verify_tos_state_shift(); ++ // load return address ++ { ++ const address table = (address) Interpreter::invoke_return_entry_table_for(code); ++ __ li(AT, (long)table); ++ __ slll(flags, flags, LogBytesPerWord); ++ __ addl(AT, AT, flags); ++ __ ldl(RA, AT, 0); ++ } ++ ++ if (save_flags) { ++ __ move(flags, BCP); ++ __ restore_bcp(); ++ } ++} ++ ++// used registers : T0, T3, T1, T2 ++// T3 : recv, this two register using convention is by prepare_invoke ++// T1 : flags, klass ++// Rmethod : method, index must be Rmethod ++void TemplateTable::invokevirtual_helper(Register index, ++ Register recv, ++ Register flags) { ++ ++ assert_different_registers(index, recv, flags, T2); ++ ++ // Test for an invoke of a final method ++ Label notFinal; ++ __ move(AT, (1 << ConstantPoolCacheEntry::is_vfinal_shift)); ++ __ and_reg(AT, flags, AT); ++ __ beq(AT, notFinal); ++ Register method = index; // method must be Rmethod ++ assert(method == Rmethod, "methodOop must be Rmethod for interpreter calling convention"); ++ ++ // do the call - the index is actually the method to call ++ // the index is indeed methodOop, for this is vfinal, ++ // see ConstantPoolCacheEntry::set_method for more info ++ ++ //__ verify_oop(method); ++ ++ // It's final, need a null check here! ++ __ null_check(recv); ++ ++ // profile this call ++ __ profile_final_call(T2); ++ ++ // T2: tmp, used for mdp ++ // method: callee ++ // T12: tmp ++ // is_virtual: true ++ __ profile_arguments_type(T2, method, T12, true); ++ ++ __ jump_from_interpreted(method, T2); ++ ++ __ BIND(notFinal); ++ ++ // get receiver klass ++ __ null_check(recv, oopDesc::klass_offset_in_bytes()); ++ __ load_klass(T2, recv); ++ //__ verify_oop(T2); ++ ++ // profile this call ++ __ profile_virtual_call(T2, T0, T1); ++ ++ // get target methodOop & entry point ++ const int base = InstanceKlass::vtable_start_offset() * wordSize; ++ assert(vtableEntry::size() * wordSize == wordSize, "adjust the scaling in the code below"); ++ __ slll(AT, index, Address::times_ptr); ++ // T2: receiver ++ __ addl(AT, T2, AT); ++ //this is a ualign read ++ __ ldl(method, AT, base + vtableEntry::method_offset_in_bytes()); ++ __ profile_arguments_type(T2, method, T12, true); ++ __ jump_from_interpreted(method, T2); ++ ++} ++ ++void TemplateTable::invokevirtual(int byte_no) { ++ transition(vtos, vtos); ++ assert(byte_no == f2_byte, "use this argument"); ++ prepare_invoke(byte_no, Rmethod, NOREG, T3, T1); ++ // now recv & flags in T3, T1 ++ invokevirtual_helper(Rmethod, T3, T1); ++} ++ ++// T12 : entry ++// Rmethod : method ++void TemplateTable::invokespecial(int byte_no) { ++ transition(vtos, vtos); ++ assert(byte_no == f1_byte, "use this argument"); ++ prepare_invoke(byte_no, Rmethod, NOREG, T3); ++ // now recv & flags in T3, T1 ++ __ verify_oop(T3); ++ __ null_check(T3); ++ __ profile_call(T12); ++ ++ // T11: tmp, used for mdp ++ // Rmethod: callee ++ // T12: tmp ++ // is_virtual: false ++ __ profile_arguments_type(T11, Rmethod, T12, false); ++ ++ __ jump_from_interpreted(Rmethod, T12); ++ __ move(T0, T3); ++} ++ ++void TemplateTable::invokestatic(int byte_no) { ++ transition(vtos, vtos); ++ assert(byte_no == f1_byte, "use this argument"); ++ prepare_invoke(byte_no, Rmethod, NOREG); ++ //__ verify_oop(Rmethod); ++ ++ __ profile_call(T12); ++ ++ // T11: tmp, used for mdp ++ // Rmethod: callee ++ // T12: tmp ++ // is_virtual: false ++ __ profile_arguments_type(T11, Rmethod, T12, false); ++ ++ __ jump_from_interpreted(Rmethod, T12); ++} ++ ++void TemplateTable::fast_invokevfinal(int byte_no) { ++ transition(vtos, vtos); ++ assert(byte_no == f2_byte, "use this argument"); ++ __ stop("fast_invokevfinal not used on sw64"); ++} ++ ++// used registers : T0, T1, T2, T3, T1, T7 ++// T0 : itable, vtable, entry ++// T1 : interface ++// T3 : receiver ++// T1 : flags, klass ++// Rmethod : index, method, this is required by interpreter_entry ++void TemplateTable::invokeinterface(int byte_no) { ++ transition(vtos, vtos); ++ //this method will use T1-T4 and T0 ++ assert(byte_no == f1_byte, "use this argument"); ++ prepare_invoke(byte_no, T2, Rmethod, T3, T1); ++ // T2: reference klass ++ // Rmethod: method ++ // T3: receiver ++ // T1: flags ++ ++ // Special case of invokeinterface called for virtual method of ++ // java.lang.Object. See cpCacheOop.cpp for details. ++ // This code isn't produced by javac, but could be produced by ++ // another compliant java compiler. ++ Label notMethod; ++ __ move(AT, (1 << ConstantPoolCacheEntry::is_forced_virtual_shift)); ++ __ and_reg(AT, T1, AT); ++ __ beq(AT, notMethod); ++ ++ invokevirtual_helper(Rmethod, T3, T1); ++ __ BIND(notMethod); ++ // Get receiver klass into T1 - also a null check ++ //add for compressedoops ++ __ load_klass(T1, T3); ++ // __ verify_oop(T1); ++ ++ Label no_such_interface, no_such_method; ++ ++ // Receiver subtype check against REFC. ++ // Superklass in T2. Subklass in T1. ++ __ lookup_interface_method(// inputs: rec. class, interface, itable index ++ T1, T2, noreg, ++ // outputs: scan temp. reg, scan temp. reg ++ T0, FSR, ++ no_such_interface, ++ /*return_method=*/false); ++ ++ ++ // profile this call ++ __ profile_virtual_call(T1, T0, FSR); ++ ++ // Get declaring interface class from method, and itable index ++ __ ld_ptr(T2, Rmethod, in_bytes(Method::const_offset())); ++ __ ld_ptr(T2, T2, in_bytes(ConstMethod::constants_offset())); ++ __ ld_ptr(T2, T2, ConstantPool::pool_holder_offset_in_bytes()); ++ __ ldw(Rmethod, Rmethod, in_bytes(Method::itable_index_offset())); ++ __ add_simm16(Rmethod, Rmethod, (-1) * Method::itable_index_max); ++ __ subw(Rmethod, R0, Rmethod); ++ ++ __ lookup_interface_method(// inputs: rec. class, interface, itable index ++ T1, T2, Rmethod, ++ // outputs: method, scan temp. reg ++ Rmethod, T0, ++ no_such_interface); ++ ++ // Rmethod: Method* to call ++ // T3: receiver ++ // Check for abstract method error ++ // Note: This should be done more efficiently via a throw_abstract_method_error ++ // interpreter entry point and a conditional jump to it in case of a null ++ // method. ++ __ beq(Rmethod, no_such_method); ++ ++ __ profile_arguments_type(T1, Rmethod, T0, true); ++ ++ // do the call ++ // T3: receiver ++ // Rmethod: Method* ++ __ jump_from_interpreted(Rmethod, T1); ++ __ should_not_reach_here(); ++ ++ // exception handling code follows... ++ // note: must restore interpreter registers to canonical ++ // state for exception handling to work correctly! ++ ++ __ BIND(no_such_method); ++ // throw exception ++ __ call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::throw_AbstractMethodError)); ++ // the call_VM checks for exception, so we should never return here. ++ __ should_not_reach_here(); ++ ++ __ BIND(no_such_interface); ++ // throw exception ++ __ call_VM(noreg, CAST_FROM_FN_PTR(address, ++ InterpreterRuntime::throw_IncompatibleClassChangeError)); ++ // the call_VM checks for exception, so we should never return here. ++ __ should_not_reach_here(); ++ ++} ++ ++ ++void TemplateTable::invokehandle(int byte_no) { ++ transition(vtos, vtos); ++ assert(byte_no == f1_byte, "use this argument"); ++ const Register T2_method = Rmethod; ++ const Register FSR_mtype = FSR; ++ const Register T3_recv = T3; ++ ++ if (!EnableInvokeDynamic) { ++ // rewriter does not generate this bytecode ++ __ should_not_reach_here(); ++ return; ++ } ++ ++ prepare_invoke(byte_no, T2_method, FSR_mtype, T3_recv); ++ __ verify_oop(T3_recv); ++ __ null_check(T3_recv); ++ ++ // T12: MethodType object (from cpool->resolved_references[f1], if necessary) ++ // T2_method: MH.invokeExact_MT method (from f2) ++ ++ // Note: T12 is already pushed (if necessary) by prepare_invoke ++ ++ __ profile_final_call(T12); ++ ++ // T11: tmp, used for mdp ++ // T2_method: callee ++ // T12: tmp ++ // is_virtual: true ++ __ profile_arguments_type(T11, T2_method, T12, true); ++ ++ __ jump_from_interpreted(T2_method, T12); ++} ++ ++ void TemplateTable::invokedynamic(int byte_no) { ++ transition(vtos, vtos); ++ assert(byte_no == f1_byte, "use this argument"); ++ ++ if (!EnableInvokeDynamic) { ++ // We should not encounter this bytecode if !EnableInvokeDynamic. ++ // The verifier will stop it. However, if we get past the verifier, ++ // this will stop the thread in a reasonable way, without crashing the JVM. ++ __ call_VM(noreg, CAST_FROM_FN_PTR(address, ++ InterpreterRuntime::throw_IncompatibleClassChangeError)); ++ // the call_VM checks for exception, so we should never return here. ++ __ should_not_reach_here(); ++ return; ++ } ++ ++ //const Register Rmethod = T2; ++ const Register T2_callsite = T2; ++ ++ prepare_invoke(byte_no, Rmethod, T2_callsite); ++ ++ // T2: CallSite object (from cpool->resolved_references[f1]) ++ // Rmethod: MH.linkToCallSite method (from f2) ++ ++ // Note: T2_callsite is already pushed by prepare_invoke ++ // profile this call ++ __ profile_call(T12); ++ ++ // T11: tmp, used for mdp ++ // Rmethod: callee ++ // T12: tmp ++ // is_virtual: false ++ __ profile_arguments_type(T11, Rmethod, T12, false); ++ ++ __ verify_oop(T2_callsite); ++ ++ __ jump_from_interpreted(Rmethod, T12); ++ } ++ ++//---------------------------------------------------------------------------------------------------- ++// Allocation ++// T1 : tags & buffer end & thread ++// T2 : object end ++// T3 : klass ++// T1 : object size ++// A1 : cpool ++// A2 : cp index ++// return object in FSR ++void TemplateTable::_new() { ++ transition(vtos, atos); ++ __ get_unsigned_2_byte_index_at_bcp(A2, 1); ++ ++ Label slow_case; ++ Label done; ++ Label initialize_header; ++ Label initialize_object; // including clearing the fields ++ Label allocate_shared; ++ ++ // get InstanceKlass in T3 ++ __ get_cpool_and_tags(A1, T1); ++ ++ __ slll(AT, A2, Address::times_8); ++ __ addl(AT, A1, AT); ++ __ memb(); ++ __ ldl(T3, AT, sizeof(ConstantPool)); ++ ++ // make sure the class we're about to instantiate has been resolved. ++ // Note: slow_case does a pop of stack, which is why we loaded class/pushed above ++ const int tags_offset = Array::base_offset_in_bytes(); ++ __ addl(T1, T1, A2); ++ __ ldbu(AT, T1, tags_offset); ++ __ add_simm16(AT, AT, - (int)JVM_CONSTANT_Class); ++ __ bne(AT, slow_case); ++ ++ ++ // make sure klass is initialized & doesn't have finalizer ++ // make sure klass is fully initialized ++ __ ldhu(T1, T3, in_bytes(InstanceKlass::init_state_offset())); ++ __ add_simm16(AT, T1, - (int)InstanceKlass::fully_initialized); ++ __ bne(AT, slow_case); ++ ++ // has_finalizer ++ __ ldw(T0, T3, in_bytes(Klass::layout_helper_offset())); ++ __ and_imm8(AT, T0, Klass::_lh_instance_slow_path_bit); ++ __ bne(AT, slow_case); ++ ++ // Allocate the instance ++ // 1) Try to allocate in the TLAB ++ // 2) if fail and the object is large allocate in the shared Eden ++ // 3) if the above fails (or is not applicable), go to a slow case ++ // (creates a new TLAB, etc.) ++ ++ const bool allow_shared_alloc = ++ Universe::heap()->supports_inline_contig_alloc() && !CMSIncrementalMode; ++ ++ const Register thread = S2thread; ++ ++ if (UseTLAB) { ++ // get tlab_top ++ __ ldl(FSR, thread, in_bytes(JavaThread::tlab_top_offset())); ++ // get tlab_end ++ __ ldl(AT, thread, in_bytes(JavaThread::tlab_end_offset())); ++ __ addl(T2, FSR, T0); ++ __ cmplt(AT, AT, T2); ++ __ bne(AT, allow_shared_alloc ? allocate_shared : slow_case); ++ __ stl(T2, thread, in_bytes(JavaThread::tlab_top_offset())); ++ ++ if (ZeroTLAB) { ++ // the fields have been already cleared ++ __ beq(R0, initialize_header); ++ } else { ++ // initialize both the header and fields ++ __ beq(R0, initialize_object); ++ } ++ } ++ ++ // Allocation in the shared Eden , if allowed ++ // T0 : instance size in words ++ if(allow_shared_alloc){ ++ __ BIND(allocate_shared); ++ ++ Label retry; ++ Address heap_top(T1); ++ __ set64(T1, (long)Universe::heap()->top_addr()); ++ __ ldl(FSR, heap_top); ++ ++ __ BIND(retry); ++ __ set64(AT, (long)Universe::heap()->end_addr()); ++ __ ldl(AT, AT, 0); ++ __ addl(T2, FSR, T0); ++ __ cmplt(AT, AT, T2); ++ __ bne(AT, slow_case); ++ ++ // Compare FSR with the top addr, and if still equal, store the new ++ // top addr in T2 at the address of the top addr pointer. Sets AT if was ++ // equal, and clears it otherwise. Use lock prefix for atomicity on MPs. ++ // ++ // FSR: object begin ++ // T2: object end ++ // T0: instance size in words ++ ++ // if someone beat us on the allocation, try again, otherwise continue ++ __ cmpxchg(T2, heap_top, FSR); ++ __ beq(AT, retry); ++ ++ __ incr_allocated_bytes(thread, T0, 0); ++ } ++ ++ if (UseTLAB || Universe::heap()->supports_inline_contig_alloc()) { ++ // The object is initialized before the header. If the object size is ++ // zero, go directly to the header initialization. ++ __ BIND(initialize_object); ++ __ set64(AT, - sizeof(oopDesc)); ++ __ addl(T0, T0, AT); ++ __ beq(T0, initialize_header); ++ ++ ++ // initialize remaining object fields: T0 is a multiple of 2 ++ { ++ Label loop; ++ __ addl(T1, FSR, T0); ++ ++ __ BIND(loop); ++ __ add_simm16(T1, T1, -oopSize); //ZHJ ++ __ stl(R0, T1, sizeof(oopDesc) + 0 * oopSize); ++ __ bne(T1, FSR, loop); //dont clear header ++ } ++ ++ //klass in T3, ++ // initialize object header only. ++ __ BIND(initialize_header); ++ if (UseBiasedLocking) { ++ __ ldl(AT, T3, in_bytes(Klass::prototype_header_offset())); ++ __ stl(AT, FSR, oopDesc::mark_offset_in_bytes()); ++ } else { ++ __ set64(AT, (long)markOopDesc::prototype()); ++ __ stl(AT, FSR, oopDesc::mark_offset_in_bytes()); ++ } ++ ++ __ store_klass_gap(FSR, R0); ++ __ store_klass(FSR, T3); ++ ++ { ++ SkipIfEqual skip_if(_masm, &DTraceAllocProbes, 0); ++ // Trigger dtrace event for fastpath ++ __ push(atos); ++ __ call_VM_leaf( ++ CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_object_alloc), FSR); ++ __ pop(atos); ++ ++ } ++ __ beq(R0, done); ++ } ++ ++ // slow case ++ __ BIND(slow_case); ++ call_VM(FSR, CAST_FROM_FN_PTR(address, InterpreterRuntime::_new), A1, A2); ++ ++ // continue ++ __ BIND(done); ++ if(UseWmemb) ++ __ wmemb(); ++ else ++ __ memb(); ++} ++ ++void TemplateTable::newarray() { ++ transition(itos, atos); ++ __ ldbu(A1, at_bcp(1)); ++ //type, count ++ call_VM(FSR, CAST_FROM_FN_PTR(address, InterpreterRuntime::newarray), A1, FSR); ++ if(UseWmemb) ++ __ wmemb(); ++ else ++ __ memb(); ++} ++ ++void TemplateTable::anewarray() { ++ transition(itos, atos); ++ __ get_2_byte_integer_at_bcp(A2, AT, 1); ++ __ huswap(A2); ++ __ get_constant_pool(A1); ++ // cp, index, count ++ call_VM(FSR, CAST_FROM_FN_PTR(address, InterpreterRuntime::anewarray), A1, A2, FSR); ++ if(UseWmemb) ++ __ wmemb(); ++ else ++ __ memb(); ++} ++ ++void TemplateTable::arraylength() { ++ transition(atos, itos); ++ __ null_check(FSR, arrayOopDesc::length_offset_in_bytes()); ++ __ ldw(FSR, FSR, arrayOopDesc::length_offset_in_bytes()); ++} ++ ++// when invoke gen_subtype_check, super in T3, sub in T2, object in FSR(it's always) ++// T2 : sub klass ++// T3 : cpool ++// T3 : super klass ++void TemplateTable::checkcast() { ++ transition(atos, atos); ++ Label done, is_null, ok_is_subtype, quicked, resolved; ++ __ beq(FSR, is_null); ++ ++ // Get cpool & tags index ++ __ get_cpool_and_tags(T3, T1); ++ __ get_unsigned_2_byte_index_at_bcp(T2, 1); ++ ++ // See if bytecode has already been quicked ++ __ addl(AT, T1, T2); ++ __ ldbu(AT, AT, Array::base_offset_in_bytes()); ++ __ add_simm16(AT, AT, - (int)JVM_CONSTANT_Class); ++ __ beq(AT, quicked); ++ ++ // In InterpreterRuntime::quicken_io_cc, lots of new classes may be loaded. ++ // Then, GC will move the object in V0 to another places in heap. ++ // Therefore, We should never save such an object in register. ++ // Instead, we should save it in the stack. It can be modified automatically by the GC thread. ++ // After GC, the object address in FSR is changed to a new place. ++ // ++ __ push(atos); ++ const Register thread = S2thread; ++ call_VM(NOREG, CAST_FROM_FN_PTR(address, InterpreterRuntime::quicken_io_cc)); ++ __ get_vm_result_2(T3, thread); ++ __ pop_ptr(FSR); ++ __ beq(R0, resolved); ++ ++ // klass already in cp, get superklass in T3 ++ __ BIND(quicked); ++ __ slll(AT, T2, Address::times_8); ++ __ addl(AT, T3, AT); ++ __ memb(); ++ __ ldl(T3, AT, sizeof(ConstantPool)); ++ ++ __ BIND(resolved); ++ ++ // get subklass in T2 ++ //add for compressedoops ++ __ load_klass(T2, FSR); ++ // Superklass in T3. Subklass in T2. ++ __ gen_subtype_check(T3, T2, ok_is_subtype); ++ ++ // Come here on failure ++ // object is at FSR ++ __ jmp(Interpreter::_throw_ClassCastException_entry); ++ ++ // Come here on success ++ __ BIND(ok_is_subtype); ++ ++ // Collect counts on whether this check-cast sees NULLs a lot or not. ++ if (ProfileInterpreter) { ++ __ beq(R0, done); ++ __ BIND(is_null); ++ __ profile_null_seen(T3); ++ } else { ++ __ BIND(is_null); ++ } ++ __ BIND(done); ++} ++ ++// i use T3 as cpool, T1 as tags, T2 as index ++// object always in FSR, superklass in T3, subklass in T2 ++void TemplateTable::instanceof() { ++ transition(atos, itos); ++ Label done, is_null, ok_is_subtype, quicked, resolved; ++ ++ __ beq(FSR, is_null); ++ ++ // Get cpool & tags index ++ __ get_cpool_and_tags(T3, T1); ++ // get index ++ __ get_unsigned_2_byte_index_at_bcp(T2, 1); ++ ++ // See if bytecode has already been quicked ++ // quicked ++ __ addl(AT, T1, T2); ++ __ ldbu(AT, AT, Array::base_offset_in_bytes()); ++ __ add_simm16(AT, AT, - (int)JVM_CONSTANT_Class); ++ __ beq(AT, quicked); ++ ++ __ push(atos); ++ const Register thread = S2thread; ++ call_VM(NOREG, CAST_FROM_FN_PTR(address, InterpreterRuntime::quicken_io_cc)); ++ __ get_vm_result_2(T3, thread); ++ __ pop_ptr(FSR); ++ __ beq(R0, resolved); ++ ++ // get superklass in T3, subklass in T2 ++ __ BIND(quicked); ++ __ slll(AT, T2, Address::times_8); ++ __ addl(AT, T3, AT); ++ __ memb(); ++ __ ldl(T3, AT, sizeof(ConstantPool)); ++ ++ __ BIND(resolved); ++ // get subklass in T2 ++ //add for compressedoops ++ __ load_klass(T2, FSR); ++ ++ // Superklass in T3. Subklass in T2. ++ __ gen_subtype_check(T3, T2, ok_is_subtype); ++ // Come here on failure ++ __ move(FSR, R0); ++ __ beq(R0, done); ++ ++ // Come here on success ++ __ BIND(ok_is_subtype); ++ __ move(FSR, 1); ++ ++ // Collect counts on whether this test sees NULLs a lot or not. ++ if (ProfileInterpreter) { ++ __ beq(R0, done); ++ __ BIND(is_null); ++ __ profile_null_seen(T3); ++ } else { ++ __ BIND(is_null); // same as 'done' ++ } ++ __ BIND(done); ++ // FSR = 0: obj == NULL or obj is not an instanceof the specified klass ++ // FSR = 1: obj != NULL and obj is an instanceof the specified klass ++} ++ ++//-------------------------------------------------------- ++//-------------------------------------------- ++// Breakpoints ++void TemplateTable::_breakpoint() { ++ // Note: We get here even if we are single stepping.. ++ // jbug inists on setting breakpoints at every bytecode ++ // even if we are in single step mode. ++ ++ transition(vtos, vtos); ++ ++ // get the unpatched byte code ++ __ get_method(A1); ++ __ call_VM(NOREG, ++ CAST_FROM_FN_PTR(address, ++ InterpreterRuntime::get_original_bytecode_at), ++ A1, BCP); ++ __ move(Rnext, V0); ++ //save the Rnext in the stack, otherwise, it will be destroied by InterpreterRuntime::_breakpoint below. jx ++ __ stl(Rnext, SP, -8); ++ __ subl(SP, SP, 8); ++ // post the breakpoint event ++ __ get_method(A1); ++ __ call_VM(NOREG, CAST_FROM_FN_PTR(address, InterpreterRuntime::_breakpoint), A1, BCP); ++ //pop the value of Rnext previously stored in stack. jx ++ __ ldl(Rnext, SP, 0); ++ __ addl(SP, SP, 8); ++ // complete the execution of original bytecode ++ ++ __ dispatch_only_normal(vtos); ++} ++ ++//----------------------------------------------------------------------------- ++// Exceptions ++ ++void TemplateTable::athrow() { ++ transition(atos, vtos); ++ __ null_check(FSR); ++ __ jmp(Interpreter::throw_exception_entry()); ++} ++ ++//----------------------------------------------------------------------------- ++// Synchronization ++// ++// Note: monitorenter & exit are symmetric routines; which is reflected ++// in the assembly code structure as well ++// ++// Stack layout: ++// ++// [expressions ] <--- SP = expression stack top ++// .. ++// [expressions ] ++// [monitor entry] <--- monitor block top = expression stack bot ++// .. ++// [monitor entry] ++// [frame data ] <--- monitor block bot ++// ... ++// [return addr ] <--- FP ++ ++// we use T2 as monitor entry pointer, T3 as monitor top pointer, c_rarg0 as free slot pointer ++// object always in FSR ++void TemplateTable::monitorenter() { ++ transition(atos, vtos); ++ ++ // check for NULL object ++ __ null_check(FSR); ++ ++ const Address monitor_block_top(FP, frame::interpreter_frame_monitor_block_top_offset ++ * wordSize); ++ const int entry_size = (frame::interpreter_frame_monitor_size()* wordSize); ++ Label allocated; ++ ++ // initialize entry pointer ++ __ move(c_rarg0, R0); ++ ++ // find a free slot in the monitor block (result in c_rarg0) ++ { ++ Label entry, loop, exit, next; ++ __ ldl(T2, monitor_block_top); ++ __ add_simm16(T3, FP, frame::interpreter_frame_initial_sp_offset * wordSize); ++ __ beq(R0, entry); ++ ++ // free slot? ++ __ BIND(loop); ++ __ ldl(AT, T2, BasicObjectLock::obj_offset_in_bytes()); ++ __ bne(AT, next); ++ __ move(c_rarg0, T2); ++ ++ __ BIND(next); ++ __ beq(FSR, AT, exit); ++ __ add_simm16(T2, T2, entry_size); ++ ++ __ BIND(entry); ++ __ bne(T3, T2, loop); ++ __ BIND(exit); ++ } ++ ++ __ bne(c_rarg0, allocated); ++ ++ // allocate one if there's no free slot ++ { ++ Label entry, loop; ++ // 1. compute new pointers // SP: old expression stack top ++ __ ldl(c_rarg0, monitor_block_top); ++ __ add_simm16(SP, SP, - entry_size); ++ __ add_simm16(c_rarg0, c_rarg0, - entry_size); ++ __ stl(c_rarg0, monitor_block_top); ++ __ move(T3, SP); ++ __ beq(R0, entry); ++ ++ // 2. move expression stack contents ++ __ BIND(loop); ++ __ ldl(AT, T3, entry_size); ++ __ stl(AT, T3, 0); ++ __ add_simm16(T3, T3, wordSize); ++ __ BIND(entry); ++ __ bne(T3, c_rarg0, loop); ++ } ++ ++ __ BIND(allocated); ++ // Increment bcp to point to the next bytecode, ++ // so exception handling for async. exceptions work correctly. ++ // The object has already been poped from the stack, so the ++ // expression stack looks correct. ++ __ addl(BCP, BCP, 1); ++ __ stl(FSR, c_rarg0, BasicObjectLock::obj_offset_in_bytes()); ++ __ lock_object(c_rarg0); ++ // check to make sure this monitor doesn't cause stack overflow after locking ++ __ save_bcp(); // in case of exception ++ __ generate_stack_overflow_check(0); ++ // The bcp has already been incremented. Just need to dispatch to next instruction. ++ ++ __ dispatch_next(vtos); ++} ++ ++// T2 : top ++// c_rarg0 : entry ++void TemplateTable::monitorexit() { ++ transition(atos, vtos); ++ ++ __ null_check(FSR); ++ ++ const int entry_size =(frame::interpreter_frame_monitor_size()* wordSize); ++ Label found; ++ ++ // find matching slot ++ { ++ Label entry, loop; ++ __ ldl(c_rarg0, FP, frame::interpreter_frame_monitor_block_top_offset * wordSize); ++ __ add_simm16(T2, FP, frame::interpreter_frame_initial_sp_offset * wordSize); ++ __ beq(R0, entry); ++ ++ __ BIND(loop); ++ __ ldl(AT, c_rarg0, BasicObjectLock::obj_offset_in_bytes()); ++ __ beq(FSR, AT, found); ++ __ add_simm16(c_rarg0, c_rarg0, entry_size); ++ __ BIND(entry); ++ __ bne(T2, c_rarg0, loop); ++ } ++ ++ // error handling. Unlocking was not block-structured ++ Label end; ++ __ call_VM(NOREG, CAST_FROM_FN_PTR(address, ++ InterpreterRuntime::throw_illegal_monitor_state_exception)); ++ __ should_not_reach_here(); ++ ++ // call run-time routine ++ // c_rarg0: points to monitor entry ++ __ BIND(found); ++ __ push(FSR); ++ __ unlock_object(c_rarg0); ++ __ pop(FSR); ++ __ BIND(end); ++} ++ ++ ++// Wide instructions ++void TemplateTable::wide() { ++ transition(vtos, vtos); ++ __ ldbu(Rnext, at_bcp(1)); ++ __ slll(T12, Rnext, Address::times_8); ++ __ li(AT, (long)Interpreter::_wentry_point); ++ __ addl(AT, T12, AT); ++ __ ldl(T12, AT, 0); ++ __ jmp(T12); ++} ++ ++ ++void TemplateTable::multianewarray() { ++ transition(vtos, atos); ++ // last dim is on top of stack; we want address of first one: ++ // first_addr = last_addr + (ndims - 1) * wordSize ++ __ ldbu(A1, at_bcp(3)); // dimension ++ __ subl(A1, A1, 1); ++ __ slll(A1, A1, Address::times_8); ++ __ addl(A1, SP, A1); // now A1 pointer to the count array on the stack ++ call_VM(FSR, CAST_FROM_FN_PTR(address, InterpreterRuntime::multianewarray), A1); ++ __ ldbu(AT, at_bcp(3)); ++ __ slll(AT, AT, Address::times_8); ++ __ addl(SP, SP, AT); ++ __ memb(); ++} ++#endif // !CC_INTERP +diff --git a/hotspot/src/cpu/sw64/vm/templateTable_sw64.hpp b/hotspot/src/cpu/sw64/vm/templateTable_sw64.hpp +new file mode 100755 +index 0000000000..dc4537b58a +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/templateTable_sw64.hpp +@@ -0,0 +1,42 @@ ++/* ++ * Copyright (c) 2003, 2012, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_SW64_VM_TEMPLATETABLE_SW64_HPP ++#define CPU_SW64_VM_TEMPLATETABLE_SW64_HPP ++ ++ static void prepare_invoke(int byte_no, ++ Register method, ++ Register index = noreg, ++ Register recv = noreg, ++ Register flags = noreg ++ ); ++ static void invokevirtual_helper(Register index, Register recv, ++ Register flags); ++ static void volatile_barrier(); ++ ++ // Helpers ++ static void index_check(Register array, Register index); ++ static void index_check_without_pop(Register array, Register index); ++ ++#endif // CPU_SW64_VM_TEMPLATETABLE_SW64_HPP +diff --git a/hotspot/src/cpu/sw64/vm/vmStructs_sw64.hpp b/hotspot/src/cpu/sw64/vm/vmStructs_sw64.hpp +new file mode 100755 +index 0000000000..fbce396462 +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/vmStructs_sw64.hpp +@@ -0,0 +1,67 @@ ++/* ++ * Copyright (c) 2001, 2013, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_SW64_VM_VMSTRUCTS_SW64_HPP ++#define CPU_SW64_VM_VMSTRUCTS_SW64_HPP ++ ++// These are the CPU-specific fields, types and integer ++// constants required by the Serviceability Agent. This file is ++// referenced by vmStructs.cpp. ++ ++#define VM_STRUCTS_CPU(nonstatic_field, static_field, unchecked_nonstatic_field, volatile_nonstatic_field, nonproduct_nonstatic_field, c2_nonstatic_field, unchecked_c1_static_field, unchecked_c2_static_field) \ ++ \ ++ /******************************/ \ ++ /* JavaCallWrapper */ \ ++ /******************************/ \ ++ /******************************/ \ ++ /* JavaFrameAnchor */ \ ++ /******************************/ \ ++ volatile_nonstatic_field(JavaFrameAnchor, _last_Java_fp, intptr_t*) \ ++ \ ++ ++ /* NOTE that we do not use the last_entry() macro here; it is used */ ++ /* in vmStructs__.hpp's VM_STRUCTS_OS_CPU macro (and must */ ++ /* be present there) */ ++ ++ ++#define VM_TYPES_CPU(declare_type, declare_toplevel_type, declare_oop_type, declare_integer_type, declare_unsigned_integer_type, declare_c1_toplevel_type, declare_c2_type, declare_c2_toplevel_type) \ ++ ++ /* NOTE that we do not use the last_entry() macro here; it is used */ ++ /* in vmStructs__.hpp's VM_TYPES_OS_CPU macro (and must */ ++ /* be present there) */ ++ ++ ++#define VM_INT_CONSTANTS_CPU(declare_constant, declare_preprocessor_constant, declare_c1_constant, declare_c2_constant, declare_c2_preprocessor_constant) \ ++ ++ /* NOTE that we do not use the last_entry() macro here; it is used */ ++ /* in vmStructs__.hpp's VM_INT_CONSTANTS_OS_CPU macro (and must */ ++ /* be present there) */ ++ ++#define VM_LONG_CONSTANTS_CPU(declare_constant, declare_preprocessor_constant, declare_c1_constant, declare_c2_constant, declare_c2_preprocessor_constant) \ ++ ++ /* NOTE that we do not use the last_entry() macro here; it is used */ ++ /* in vmStructs__.hpp's VM_LONG_CONSTANTS_OS_CPU macro (and must */ ++ /* be present there) */ ++ ++#endif // CPU_SW64_VM_VMSTRUCTS_SW64_HPP +diff --git a/hotspot/src/cpu/sw64/vm/vm_version_ext_sw64.cpp b/hotspot/src/cpu/sw64/vm/vm_version_ext_sw64.cpp +new file mode 100644 +index 0000000000..c28124d398 +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/vm_version_ext_sw64.cpp +@@ -0,0 +1,88 @@ ++/* ++ * Copyright (c) 2013, 2018, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#include "memory/allocation.inline.hpp" ++#include "vm_version_ext_sw64.hpp" ++ ++// VM_Version_Ext statics ++int VM_Version_Ext::_no_of_threads = 0; ++int VM_Version_Ext::_no_of_cores = 0; ++int VM_Version_Ext::_no_of_sockets = 0; ++bool VM_Version_Ext::_initialized = false; ++char VM_Version_Ext::_cpu_name[CPU_TYPE_DESC_BUF_SIZE] = {0}; ++char VM_Version_Ext::_cpu_desc[CPU_DETAILED_DESC_BUF_SIZE] = {0}; ++ ++void VM_Version_Ext::initialize_cpu_information(void) { ++ // do nothing if cpu info has been initialized ++ if (_initialized) { ++ return; ++ } ++ ++ int core_id = -1; ++ int chip_id = -1; ++ int len = 0; ++ char* src_string = NULL; ++ ++ _no_of_cores = os::processor_count(); ++ _no_of_threads = _no_of_cores; ++ _no_of_sockets = _no_of_cores; ++ snprintf(_cpu_name, CPU_TYPE_DESC_BUF_SIZE - 1, "sw_64"); ++ snprintf(_cpu_desc, CPU_DETAILED_DESC_BUF_SIZE, "%s", cpu_features()); ++ _initialized = true; ++} ++ ++int VM_Version_Ext::number_of_threads(void) { ++ initialize_cpu_information(); ++ return _no_of_threads; ++} ++ ++int VM_Version_Ext::number_of_cores(void) { ++ initialize_cpu_information(); ++ return _no_of_cores; ++} ++ ++int VM_Version_Ext::number_of_sockets(void) { ++ initialize_cpu_information(); ++ return _no_of_sockets; ++} ++ ++const char* VM_Version_Ext::cpu_name(void) { ++ initialize_cpu_information(); ++ char* tmp = NEW_C_HEAP_ARRAY_RETURN_NULL(char, CPU_TYPE_DESC_BUF_SIZE, mtTracing); ++ if (NULL == tmp) { ++ return NULL; ++ } ++ strncpy(tmp, _cpu_name, CPU_TYPE_DESC_BUF_SIZE); ++ return tmp; ++} ++ ++const char* VM_Version_Ext::cpu_description(void) { ++ initialize_cpu_information(); ++ char* tmp = NEW_C_HEAP_ARRAY_RETURN_NULL(char, CPU_DETAILED_DESC_BUF_SIZE, mtTracing); ++ if (NULL == tmp) { ++ return NULL; ++ } ++ strncpy(tmp, _cpu_desc, CPU_DETAILED_DESC_BUF_SIZE); ++ return tmp; ++} +diff --git a/hotspot/src/cpu/sw64/vm/vm_version_ext_sw64.hpp b/hotspot/src/cpu/sw64/vm/vm_version_ext_sw64.hpp +new file mode 100644 +index 0000000000..2fb161b1f6 +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/vm_version_ext_sw64.hpp +@@ -0,0 +1,53 @@ ++/* ++ * Copyright (c) 2013, 2018, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_SW64_VM_VM_VERSION_EXT_SW64_HPP ++#define CPU_SW64_VM_VM_VERSION_EXT_SW64_HPP ++ ++#include "utilities/macros.hpp" ++#include "runtime/vm_version.hpp" ++ ++class VM_Version_Ext : public VM_Version { ++ private: ++ static const size_t CPU_TYPE_DESC_BUF_SIZE = 256; ++ static const size_t CPU_DETAILED_DESC_BUF_SIZE = 4096; ++ ++ static int _no_of_threads; ++ static int _no_of_cores; ++ static int _no_of_sockets; ++ static bool _initialized; ++ static char _cpu_name[CPU_TYPE_DESC_BUF_SIZE]; ++ static char _cpu_desc[CPU_DETAILED_DESC_BUF_SIZE]; ++ ++ public: ++ static int number_of_threads(void); ++ static int number_of_cores(void); ++ static int number_of_sockets(void); ++ ++ static const char* cpu_name(void); ++ static const char* cpu_description(void); ++ static void initialize_cpu_information(void); ++}; ++ ++#endif // CPU_SW64_VM_VM_VERSION_EXT_SW64_HPP +diff --git a/hotspot/src/cpu/sw64/vm/vm_version_sw64.cpp b/hotspot/src/cpu/sw64/vm/vm_version_sw64.cpp +new file mode 100755 +index 0000000000..c730e783de +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/vm_version_sw64.cpp +@@ -0,0 +1,249 @@ ++/* ++ * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#include "precompiled.hpp" ++#include "asm/macroAssembler.hpp" ++#include "asm/macroAssembler.inline.hpp" ++#include "memory/resourceArea.hpp" ++#include "runtime/java.hpp" ++#include "runtime/stubCodeGenerator.hpp" ++#include "vm_version_sw64.hpp" ++#ifdef TARGET_OS_FAMILY_linux ++# include "os_linux.inline.hpp" ++#endif ++#ifdef TARGET_OS_FAMILY_solaris ++# include "os_solaris.inline.hpp" ++#endif ++#ifdef TARGET_OS_FAMILY_windows ++# include "os_windows.inline.hpp" ++#endif ++#ifdef TARGET_OS_FAMILY_bsd ++# include "os_bsd.inline.hpp" ++#endif ++ ++int VM_Version::_features = VM_Version::unknown_m; ++const char* VM_Version::_features_str = ""; ++ ++void VM_Version::initialize() { ++ ++ // When using CMS or G1, we cannot use memset() in BOT updates ++ // because the sw64 version in libc_psr uses BIS which ++ // exposes "phantom zeros" to concurrent readers. See 6948537. ++ if (FLAG_IS_DEFAULT(UseMemSetInBOT) && (UseConcMarkSweepGC || UseG1GC)) { ++ FLAG_SET_DEFAULT(UseMemSetInBOT, false); ++ } ++ ++ // Issue a stern warning if the user has explicitly set ++ // UseMemSetInBOT (it is known to cause issues), but allow ++ // use for experimentation and debugging. ++ if (UseConcMarkSweepGC || UseG1GC) { ++ if (UseMemSetInBOT) { ++ assert(!FLAG_IS_DEFAULT(UseMemSetInBOT), "Error"); ++ warning("Experimental flag -XX:+UseMemSetInBOT is known to cause instability" ++ " on sw64; please understand that you are using at your own risk!"); ++ } ++ } ++ ++ _features = determine_features(); ++ //no need, Abstract_VM_Version already define it as false ++ _supports_cx8 = true; ++ ++ //////////////////////add some other feature here////////////////// ++ ++ if (UseG1GC && FLAG_IS_DEFAULT(MaxGCPauseMillis)) { ++ FLAG_SET_CMDLINE(uintx, MaxGCPauseMillis, 2000); ++ } ++ ++#ifdef COMPILER2 ++ if (MaxVectorSize > 0) { ++ if (!is_power_of_2(MaxVectorSize)) { ++ warning("MaxVectorSize must be a power of 2"); ++ MaxVectorSize = 8; ++ } ++ } ++ // Vector optimization was closed by default. ++ if (FLAG_IS_DEFAULT(MaxVectorSize)) { ++ MaxVectorSize = 0; ++ } ++ ++ if (is_shenwei()) { ++ if (FLAG_IS_DEFAULT(UseCountLeadingZerosInstruction)) { ++ FLAG_SET_DEFAULT(UseCountLeadingZerosInstruction, 1); ++ } ++ if (FLAG_IS_DEFAULT(UseCountTrailingZerosInstruction)) { ++ FLAG_SET_DEFAULT(UseCountTrailingZerosInstruction, 1); ++ } ++ if (FLAG_IS_DEFAULT(UsePopCountInstruction)) { ++ FLAG_SET_DEFAULT(UsePopCountInstruction, 1); ++ } ++ if (FLAG_IS_DEFAULT(UseSW8A)) { ++ FLAG_SET_DEFAULT(UseSW8A, 1); ++ } ++ if (FLAG_IS_DEFAULT(UseWmemb)) { ++ FLAG_SET_DEFAULT(UseWmemb, 1); ++ } ++ if (FLAG_IS_DEFAULT(UseAddpi)) { ++ FLAG_SET_DEFAULT(UseAddpi, 0); ++ } ++ if (FLAG_IS_DEFAULT(UseCRC32)) { ++ FLAG_SET_DEFAULT(UseCRC32, 1); ++ } ++ if (is_sw8a()) { ++ if (FLAG_IS_DEFAULT(FRegisterConflict)) { ++ FLAG_SET_DEFAULT(FRegisterConflict, 0); ++ } ++ } else { ++ if (FLAG_IS_DEFAULT(FRegisterConflict)) { ++ FLAG_SET_DEFAULT(FRegisterConflict, 1); ++ } ++ if (FLAG_IS_DEFAULT(SolveAlignment)) { ++ FLAG_SET_DEFAULT(SolveAlignment, 1); ++ } ++ if (UseSW8A) { ++ if (!FLAG_IS_DEFAULT(UseSW8A)) ++ warning("UseSW8A specified, but not supported on this CPU"); ++ FLAG_SET_DEFAULT(UseSW8A, 0); ++ } ++ if (UseWmemb) { ++ if (!FLAG_IS_DEFAULT(UseWmemb)) ++ warning("UseWmemb specified, but not supported on this CPU"); ++ FLAG_SET_DEFAULT(UseWmemb, 0); ++ } ++ if (UseAddpi) { ++ if (!FLAG_IS_DEFAULT(UseAddpi)) ++ warning("UseAddpi specified, but not supported on this CPU"); ++ FLAG_SET_DEFAULT(UseAddpi, 0); ++ } ++ if (UseCRC32) { ++ if (!FLAG_IS_DEFAULT(UseCRC32)) ++ warning("UseCRC32 specified, but not supported on this CPU"); ++ FLAG_SET_DEFAULT(UseCRC32, 0); ++ } ++ } ++ } else if (UseCountLeadingZerosInstruction || UseCountTrailingZerosInstruction ++ || UsePopCountInstruction) { ++ if (!FLAG_IS_DEFAULT(UseCountTrailingZerosInstruction)) ++ warning("Only SW CPUs support UseCountTrailingZerosInstruction"); ++ FLAG_SET_DEFAULT(UseCountLeadingZerosInstruction, 0); ++ FLAG_SET_DEFAULT(UseCountTrailingZerosInstruction, 0); ++ FLAG_SET_DEFAULT(UsePopCountInstruction, 0); ++ } ++#endif ++ ++ if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) { ++ UseMontgomeryMultiplyIntrinsic = true; ++ } ++ if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) { ++ UseMontgomerySquareIntrinsic = true; ++ } ++ ++ UseSSE = 0; // Only on x86 and x64 ++ ++ if (TieredCompilation) { ++ if (!FLAG_IS_DEFAULT(TieredCompilation)) ++ warning("TieredCompilation not supported"); ++ FLAG_SET_DEFAULT(TieredCompilation, false); ++ } ++ if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) { ++ FLAG_SET_DEFAULT(UseCRC32Intrinsics, 1); ++ } ++ char buf[256]; ++ jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s", ++ (has_l2_cache() ? ", has_l2_cache" : ""), ++ (has_16k_page() ? ", has_16k_page" : ""), ++ (is_shenwei() ? ", on_shenwei_platform" : ""), ++ (is_sw2f() ? ", SW410(2F)" : ""), ++ (is_sw4a() ? ", SW411(4A)" : "" ), ++ (is_sw6a() ? ", SW421(6A)" : ""), ++ (is_sw6b() ? ", SW422(6B)" : ""), ++ (is_sw1621() ? ", SW1621" : ""), ++ (UseCountTrailingZerosInstruction ? ", UseCountTrailingZerosInstruction" : "")); ++ ++ // buf is started with ", " or is empty ++ _features_str = strdup(strlen(buf) > 2 ? buf + 2 : buf); ++ ++ if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) { ++ FLAG_SET_DEFAULT(AllocatePrefetchStyle, 2); ++ } ++ ++ if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) { ++ FLAG_SET_DEFAULT(AllocatePrefetchLines, 3); ++ } ++ ++ if (FLAG_IS_DEFAULT(AllocatePrefetchStepSize)) { ++ FLAG_SET_DEFAULT(AllocatePrefetchStepSize, 128); ++ } ++ ++ if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) { ++ FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256); ++ } ++ ++ if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) { ++ FLAG_SET_DEFAULT(AllocateInstancePrefetchLines, 1); ++ } ++ ++ if (FLAG_IS_DEFAULT(PrefetchCopyIntervalInBytes)) { ++ FLAG_SET_DEFAULT(PrefetchCopyIntervalInBytes, 256); ++ } ++ ++ if (FLAG_IS_DEFAULT(PrefetchScanIntervalInBytes)) { ++ FLAG_SET_DEFAULT(PrefetchScanIntervalInBytes, 256); ++ } ++ ++ if (UseSHA) { ++ warning("SHA instructions are not available on this CPU"); ++ FLAG_SET_DEFAULT(UseSHA, false); ++ } ++ ++ if (UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics) { ++ warning("SHA intrinsics are not available on this CPU"); ++ FLAG_SET_DEFAULT(UseSHA1Intrinsics, false); ++ FLAG_SET_DEFAULT(UseSHA256Intrinsics, false); ++ FLAG_SET_DEFAULT(UseSHA512Intrinsics, false); ++ } ++ ++ NOT_PRODUCT( if (PrintMiscellaneous && Verbose) print_features(); ); ++} ++ ++void VM_Version::print_features() { ++ tty->print_cr("Version:%s", cpu_features()); ++} ++ ++int VM_Version::determine_features() { ++ //////////////////////add some other feature here////////////////// ++ int features = platform_features(unknown_m); ++ //spt_16k_page_m; ++ return features; ++} ++ ++static int saved_features = 0; ++ ++void VM_Version::allow_all() { ++ saved_features = _features; ++ _features = all_features_m; ++} ++ ++void VM_Version::revert() { ++ _features = saved_features; ++} +diff --git a/hotspot/src/cpu/sw64/vm/vm_version_sw64.hpp b/hotspot/src/cpu/sw64/vm/vm_version_sw64.hpp +new file mode 100755 +index 0000000000..5f8446ed7f +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/vm_version_sw64.hpp +@@ -0,0 +1,102 @@ ++/* ++ * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_SW64_VM_VM_VERSION_SW64_HPP ++#define CPU_SW64_VM_VM_VERSION_SW64_HPP ++ ++#include "runtime/globals_extension.hpp" ++#include "runtime/vm_version.hpp" ++ ++ ++class VM_Version: public Abstract_VM_Version { ++protected: ++ enum Feature_Flag { ++ with_l2_cache = 0, ++ spt_16k_page = 1, ++ sw2f = 2, ++ sw4a = 3, ++ sw6a = 4, ++ sw6b = 5, ++ sw1621 = 6, ++ sw3231 = 7, ++ wx_h8000 = 8, ++ with_sw_support = 9, ++ //////////////////////add some other feature here////////////////// ++ }; ++ ++ enum Feature_Flag_Set { ++ unknown_m = 0, ++ all_features_m = -1, ++ with_l2_cache_m = 1 << with_l2_cache, ++ spt_16k_page_m = 1 << spt_16k_page, ++ sw2f_m = 1 << sw2f, ++ sw4a_m = 1 << sw4a, ++ sw6a_m = 1 << sw6a, ++ sw6b_m = 1 << sw6b, ++ sw1621_m = 1 << sw1621, ++ sw3231_m = 1 << sw3231, ++ wx_h8000_m = 1 << wx_h8000, ++ with_sw_support_m = 1 << with_sw_support, ++ ++ //////////////////////add some other feature here////////////////// ++ }; ++ ++ static int _features; ++ static const char* _features_str; ++ ++ static void print_features(); ++ static int determine_features(); ++ static int platform_features(int features); ++ ++public: ++ // Initialization ++ static void initialize(); ++ ++ // shenwei has no such instructions, use ll/sc instead ++ static bool supports_compare_and_exchange() { return false; } ++ ++ static bool has_l2_cache() { return _features & with_l2_cache_m; } ++ static bool has_16k_page() { return _features & spt_16k_page_m; } ++ static bool is_sw2f() { return _features & sw2f_m; } ++ static bool is_sw4a() { return _features & sw4a_m; } ++ static bool is_sw6a() { return _features & sw6a_m; } ++ static bool is_sw6b() { return _features & sw6b_m; } ++ static bool is_sw8a() { return _features & wx_h8000_m; } ++ static bool is_sw1621() { return _features & sw1621_m; } ++ static bool is_sw3231() { return _features & sw3231_m; } ++ static bool is_shenwei() { return _features & with_sw_support_m; } ++// static bool sw2only() { return is_sw2f() || is_sw4a() || is_sw6a(); } ++ static bool sw2only() { return true; } ++ static bool sw3only() { return is_sw6b(); } ++ ++ //////////////////////add some other feature here////////////////// ++ ++ static const char* cpu_features() { return _features_str; } ++ ++ // Assembler testing ++ static void allow_all(); ++ static void revert(); ++}; ++ ++#endif // CPU_SW64_VM_VM_VERSION_SW64_HPP +diff --git a/hotspot/src/cpu/sw64/vm/vmreg_sw64.cpp b/hotspot/src/cpu/sw64/vm/vmreg_sw64.cpp +new file mode 100755 +index 0000000000..b84439dcd0 +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/vmreg_sw64.cpp +@@ -0,0 +1,50 @@ ++/* ++ * Copyright (c) 2006, 2012, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#include "precompiled.hpp" ++#include "asm/assembler.hpp" ++#include "code/vmreg.hpp" ++ ++ ++ ++void VMRegImpl::set_regName() { ++ Register reg = ::as_Register(0); ++ int i; ++ for (i = 0; i < ConcreteRegisterImpl::max_gpr ; ) { ++ regName[i++] = reg->name(); ++ regName[i++] = reg->name(); ++ reg = reg->successor(); ++ } ++ ++ FloatRegister freg = ::as_FloatRegister(0); ++ for ( ; i < ConcreteRegisterImpl::max_fpr ; ) { ++ regName[i++] = freg->name(); ++ regName[i++] = freg->name(); ++ freg = freg->successor(); ++ } ++ ++ for ( ; i < ConcreteRegisterImpl::number_of_registers ; i ++ ) { ++ regName[i] = "NON-GPR-FPR"; ++ } ++} +diff --git a/hotspot/src/cpu/sw64/vm/vmreg_sw64.hpp b/hotspot/src/cpu/sw64/vm/vmreg_sw64.hpp +new file mode 100755 +index 0000000000..db826debbd +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/vmreg_sw64.hpp +@@ -0,0 +1,34 @@ ++/* ++ * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++ #ifndef CPU_SW64_VM_VMREG_SW64_HPP ++ #define CPU_SW64_VM_VMREG_SW64_HPP ++ ++ bool is_Register(); ++ Register as_Register(); ++ ++ bool is_FloatRegister(); ++ FloatRegister as_FloatRegister(); ++ ++ #endif // CPU_SW64_VM_VMREG_SW64_HPP +diff --git a/hotspot/src/cpu/sw64/vm/vmreg_sw64.inline.hpp b/hotspot/src/cpu/sw64/vm/vmreg_sw64.inline.hpp +new file mode 100755 +index 0000000000..de3d80a8ff +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/vmreg_sw64.inline.hpp +@@ -0,0 +1,66 @@ ++/* ++ * Copyright (c) 2006, 2012, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_SW64_VM_VMREG_SW64_INLINE_HPP ++#define CPU_SW64_VM_VMREG_SW64_INLINE_HPP ++ ++inline VMReg RegisterImpl::as_VMReg() { ++ if( this==noreg ) return VMRegImpl::Bad(); ++ //FIXME why encoding << 1? what is the meaning of the VMReg's value ++ return VMRegImpl::as_VMReg(encoding() << 1 ); ++} ++ ++inline VMReg FloatRegisterImpl::as_VMReg() { ++ return VMRegImpl::as_VMReg((encoding() << 1) + ConcreteRegisterImpl::max_gpr); ++} ++ ++inline bool VMRegImpl::is_Register() { ++ return (unsigned int) value() < (unsigned int) ConcreteRegisterImpl::max_gpr; ++} ++ ++inline bool VMRegImpl::is_FloatRegister() { ++ return value() >= ConcreteRegisterImpl::max_gpr && value() < ConcreteRegisterImpl::max_fpr; ++} ++ ++inline Register VMRegImpl::as_Register() { ++ ++ assert( is_Register(), "must be"); ++ return ::as_Register(value() >> 1); ++} ++ ++inline FloatRegister VMRegImpl::as_FloatRegister() { ++ assert( is_FloatRegister(), "must be" ); ++ assert( is_even(value()), "must be" ); ++ return ::as_FloatRegister((value() - ConcreteRegisterImpl::max_gpr) >> 1); ++} ++ ++inline bool VMRegImpl::is_concrete() { ++ assert(is_reg(), "must be"); ++ if(is_Register()) return true; ++ if(is_FloatRegister()) return true; ++ assert(false, "what register?"); ++ return false; ++} ++ ++#endif // CPU_SW64_VM_VMREG_SW64_INLINE_HPP +diff --git a/hotspot/src/cpu/sw64/vm/vtableStubs_sw64.cpp b/hotspot/src/cpu/sw64/vm/vtableStubs_sw64.cpp +new file mode 100755 +index 0000000000..ca750cfd35 +--- /dev/null ++++ b/hotspot/src/cpu/sw64/vm/vtableStubs_sw64.cpp +@@ -0,0 +1,281 @@ ++/* ++ * Copyright (c) 2003, 2014, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#include "precompiled.hpp" ++#include "asm/macroAssembler.hpp" ++#include "code/vtableStubs.hpp" ++#include "interp_masm_sw64.hpp" ++#include "memory/resourceArea.hpp" ++#include "oops/compiledICHolder.hpp" ++#include "oops/klassVtable.hpp" ++#include "runtime/sharedRuntime.hpp" ++#include "vmreg_sw64.inline.hpp" ++#ifdef COMPILER2 ++#include "opto/runtime.hpp" ++#endif ++ ++ ++// machine-dependent part of VtableStubs: create VtableStub of correct size and ++// initialize its code ++ ++#define __ masm-> ++ ++#ifdef PRODUCT ++#define BLOCK_COMMENT(str) /* nothing */ ++#else ++#define BLOCK_COMMENT(str) { char line[1024];sprintf(line,"%s:%s:%d",str,__FILE__, __LINE__); __ block_comment(line);} ++#endif ++ ++#define BIND(label) bind(label); BLOCK_COMMENT(#label ":") ++ ++#ifndef PRODUCT ++extern "C" void bad_compiled_vtable_index(JavaThread* thread, ++ oop receiver, ++ int index); ++#endif ++ ++// used by compiler only; reciever in T0. ++// used registers : ++// Rmethod : receiver klass & method ++// when reach here, receiver in T0, klass in T11 ++VtableStub* VtableStubs::create_vtable_stub(int vtable_index) { ++ const int sw64_code_length = VtableStub::pd_code_size_limit(true); ++ VtableStub* s = new(sw64_code_length) VtableStub(true, vtable_index); ++ ResourceMark rm; ++ CodeBuffer cb(s->entry_point(), sw64_code_length); ++ MacroAssembler* masm = new MacroAssembler(&cb); ++ Register t1 = T11, t2 = Rmethod; ++#ifndef PRODUCT ++ if (CountCompiledCalls) { ++ __ li(AT, SharedRuntime::nof_megamorphic_calls_addr()); ++ __ ldw(t1, AT , 0); ++ __ addl(t1, t1, 1); ++ __ stw(t1, AT,0); ++ } ++#endif ++ ++ // get receiver (need to skip return address on top of stack) ++ //assert(receiver_location == T0->as_VMReg(), "receiver expected in T0"); ++ ++ // get receiver klass ++ address npe_addr = __ pc(); ++ //add for compressedoops ++ __ load_klass(t1, A1); ++ // compute entry offset (in words) ++ int entry_offset = InstanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); ++#ifndef PRODUCT ++ if (DebugVtables) { ++ Label L; ++ // check offset vs vtable length ++ __ ldw(t2, t1, InstanceKlass::vtable_length_offset()*wordSize); ++ assert(Assembler::is_simm16(vtable_index*vtableEntry::size()), "change this code"); ++ __ move(AT, vtable_index*vtableEntry::size()); ++ __ cmplt(AT, AT, t2); ++ __ bne(AT, L); ++ __ move(A2, vtable_index); ++ __ move(A1, A0); ++ __ call_VM(noreg, CAST_FROM_FN_PTR(address, bad_compiled_vtable_index), A1, A2); ++ __ BIND(L); ++ } ++#endif // PRODUCT ++ // load methodOop and target address ++ const Register method = Rmethod; ++ __ ld_ptr(method, t1, entry_offset*wordSize + vtableEntry::method_offset_in_bytes()); ++ if (DebugVtables) { ++ Label L; ++ __ beq(method, L); ++ // __ cmpl(Address(method, Method::from_compiled_offset()), NULL_WORD); ++ __ ldw(AT, method,in_bytes(Method::from_compiled_offset())); ++ //__ jcc(Assembler::notZero, L); ++ __ bne(AT, L); ++ __ stop("Vtable entry is NULL"); ++ __ BIND(L); ++ } ++ // T11: receiver klass ++ // T0: receiver ++ // Rmethod: methodOop ++ // T12: entry ++ address ame_addr = __ pc(); ++ __ ld_ptr(T12, method,in_bytes(Method::from_compiled_offset())); ++ __ jmp(T12); ++ masm->flush(); ++ s->set_exception_points(npe_addr, ame_addr); ++ return s; ++} ++ ++ ++// used registers : ++// T1 T2 ++// when reach here, the receiver in T0, klass in T1 ++VtableStub* VtableStubs::create_itable_stub(int itable_index) { ++ // Note well: pd_code_size_limit is the absolute minimum we can get ++ // away with. If you add code here, bump the code stub size ++ // returned by pd_code_size_limit! ++ const int sw64_code_length = VtableStub::pd_code_size_limit(false); ++ VtableStub* s = new(sw64_code_length) VtableStub(false, itable_index); ++ ResourceMark rm; ++ CodeBuffer cb(s->entry_point(), sw64_code_length); ++ MacroAssembler* masm = new MacroAssembler(&cb); ++ // we T11,T12 as temparary register, they are free from register allocator ++ Register t1 = T11, t2 = T2; ++ // Entry arguments: ++ // T1: Interface ++ // T0: Receiver ++ ++#ifndef PRODUCT ++ if (CountCompiledCalls) { ++ __ li(AT, SharedRuntime::nof_megamorphic_calls_addr()); ++ __ ldw(T11, AT, 0); ++ __ addl(T11, T11,1); ++ __ stw(T11, AT, 0); ++ } ++#endif /* PRODUCT */ ++ const Register holder_klass_reg = T1; // declaring interface klass (DECC) ++ const Register resolved_klass_reg = Rmethod; // resolved interface klass (REFC) ++ const Register icholder_reg = T1; ++ __ ld_ptr(resolved_klass_reg, icholder_reg, CompiledICHolder::holder_klass_offset()); ++ __ ld_ptr(holder_klass_reg, icholder_reg, CompiledICHolder::holder_metadata_offset()); ++ ++ // get receiver klass (also an implicit null-check) ++ address npe_addr = __ pc(); ++ __ load_klass(t1, A1); ++ { ++ const int base = InstanceKlass::vtable_start_offset() * wordSize; ++ assert(vtableEntry::size() * wordSize == 8, "adjust the scaling in the code below"); ++ assert(Assembler::is_simm16(base), "change this code"); ++ __ add_simm16(t2, t1, base); ++ assert(Assembler::is_simm16(InstanceKlass::vtable_length_offset() * wordSize), "change this code"); ++ __ ldw(AT, t1, InstanceKlass::vtable_length_offset() * wordSize); ++ __ slll(AT, AT, Address::times_8); ++ __ addl(t2, t2, AT); ++ if (HeapWordsPerLong > 1) { ++ __ round_to(t2, BytesPerLong); ++ } ++ ++ Label hit, entry; ++ assert(Assembler::is_simm16(itableOffsetEntry::size() * wordSize), "change this code"); ++ __ BIND(entry); ++ ++#ifdef ASSERT ++ // Check that the entry is non-null ++ if (DebugVtables) { ++ Label L; ++ assert(Assembler::is_simm16(itableOffsetEntry::interface_offset_in_bytes()), "change this code"); ++ __ ldw(AT, t1, itableOffsetEntry::interface_offset_in_bytes()); ++ __ bne(AT, L); ++ __ stop("null entry point found in itable's offset table"); ++ __ BIND(L); ++ } ++#endif ++ assert(Assembler::is_simm16(itableOffsetEntry::interface_offset_in_bytes()), "change this code"); ++ __ ld_ptr(AT, t2, itableOffsetEntry::interface_offset_in_bytes()); ++ __ add_simm16(t2, t2, itableOffsetEntry::size() * wordSize); ++ __ bne(AT, resolved_klass_reg, entry); ++ ++ } ++ ++ //add for compressedoops ++ __ load_klass(t1, A1); ++ // compute itable entry offset (in words) ++ const int base = InstanceKlass::vtable_start_offset() * wordSize; ++ assert(vtableEntry::size() * wordSize == 8, "adjust the scaling in the code below"); ++ assert(Assembler::is_simm16(base), "change this code"); ++ __ add_simm16(t2, t1, base); ++ assert(Assembler::is_simm16(InstanceKlass::vtable_length_offset() * wordSize), "change this code"); ++ __ ldw(AT, t1, InstanceKlass::vtable_length_offset() * wordSize); ++ __ slll(AT, AT, Address::times_8); ++ __ addl(t2, t2, AT); ++ if (HeapWordsPerLong > 1) { ++ __ round_to(t2, BytesPerLong); ++ } ++ ++ Label hit, entry; ++ assert(Assembler::is_simm16(itableOffsetEntry::size() * wordSize), "change this code"); ++ __ BIND(entry); ++ ++#ifdef ASSERT ++ // Check that the entry is non-null ++ if (DebugVtables) { ++ Label L; ++ assert(Assembler::is_simm16(itableOffsetEntry::interface_offset_in_bytes()), "change this code"); ++ __ ldw(AT, t1, itableOffsetEntry::interface_offset_in_bytes()); ++ __ bne(AT, L); ++ __ stop("null entry point found in itable's offset table"); ++ __ BIND(L); ++ } ++#endif ++ assert(Assembler::is_simm16(itableOffsetEntry::interface_offset_in_bytes()), "change this code"); ++ __ ld_ptr(AT, t2, itableOffsetEntry::interface_offset_in_bytes()); ++ __ add_simm16(t2, t2, itableOffsetEntry::size() * wordSize); ++ __ bne(AT, holder_klass_reg, entry); ++ ++ // We found a hit, move offset into T12 ++ __ ld_ptr(t2, t2, itableOffsetEntry::offset_offset_in_bytes() - itableOffsetEntry::size() * wordSize); ++ ++ // Compute itableMethodEntry. ++ const int method_offset = (itableMethodEntry::size() * wordSize * itable_index) + ++ itableMethodEntry::method_offset_in_bytes(); ++ ++ // Get methodOop and entrypoint for compiler ++ const Register method = Rmethod; ++ __ slll(AT, t2, Address::times_1); ++ __ addl(AT, AT, t1 ); ++ __ ld_ptr(method, AT, method_offset); ++ ++#ifdef ASSERT ++ if (DebugVtables) { ++ Label L1; ++ __ beq(method, L1); ++ __ ldw(AT, method,in_bytes(Method::from_compiled_offset())); ++ __ bne(AT, L1); ++ __ stop("methodOop is null"); ++ __ BIND(L1); ++ } ++#endif // ASSERT ++ ++ // Rmethod: methodOop ++ // T0: receiver ++ // T12: entry point ++ address ame_addr = __ pc(); ++ __ ld_ptr(T12, method,in_bytes(Method::from_compiled_offset())); ++ __ jmp(T12); ++ masm->flush(); ++ s->set_exception_points(npe_addr, ame_addr); ++ return s; ++} ++ ++// NOTE : whenever you change the code above, dont forget to change the const here ++int VtableStub::pd_code_size_limit(bool is_vtable_stub) { ++ if (is_vtable_stub) { ++ return ( DebugVtables ? 600 : 28) + (CountCompiledCalls ? 24 : 0)+ ++ (UseCompressedOops ? 16 : 0); ++ } else { ++ return ( DebugVtables ? 636 : 152) + (CountCompiledCalls ? 24 : 0)+ ++ (UseCompressedOops ? 32 : 0); ++ } ++} ++ ++int VtableStub::pd_code_alignment() { ++ return wordSize; ++} +diff --git a/hotspot/src/os/linux/vm/os_linux.cpp b/hotspot/src/os/linux/vm/os_linux.cpp +index 5629a640f6..23b56b93a1 100644 +--- a/hotspot/src/os/linux/vm/os_linux.cpp ++++ b/hotspot/src/os/linux/vm/os_linux.cpp +@@ -1030,6 +1030,14 @@ void os::pd_start_thread(Thread* thread) { + Monitor* sync_with_child = osthread->startThread_lock(); + MutexLockerEx ml(sync_with_child, Mutex::_no_safepoint_check_flag); + sync_with_child->notify(); ++ ++#if (defined SW64 && !defined ZERO) ++ // To be accessed in NativeGeneralJump::patch_verified_entry() ++ if (thread->is_Java_thread()) ++ { ++ ((JavaThread*)thread)->set_handle_wrong_method_stub(SharedRuntime::get_handle_wrong_method_stub()); ++ } ++#endif + } + + // Free Linux resources related to the OSThread +@@ -1417,6 +1425,9 @@ void os::Linux::clock_init() { + #if defined(IA32) || defined(AMD64) || defined(AARCH64) + #define SYS_clock_getres IA32_ONLY(266) AMD64_ONLY(229) AARCH64_ONLY(114) + #define sys_clock_getres(x,y) ::syscall(SYS_clock_getres, x, y) ++#elif defined(SW64) ++#define SYS_clock_getres SW64_ONLY(421) ++#define sys_clock_getres(x,y) ::syscall(SYS_clock_getres, x, y) + #else + #warning "SYS_clock_getres not defined for this platform, disabling fast_thread_cpu_time" + #define sys_clock_getres(x,y) -1 +@@ -1969,7 +1980,11 @@ void * os::dll_load(const char *filename, char *ebuf, int ebuflen) + #endif + {EM_ARM, EM_ARM, ELFCLASS32, ELFDATA2LSB, (char*)"ARM"}, + {EM_S390, EM_S390, ELFCLASSNONE, ELFDATA2MSB, (char*)"IBM System/390"}, ++#if defined(__sw_64) ++ {EM_SW_64, EM_SW_64, ELFCLASS64, ELFDATA2LSB, (char*)"Sw64"}, ++#elif defined(__alpha) + {EM_ALPHA, EM_ALPHA, ELFCLASS64, ELFDATA2LSB, (char*)"Alpha"}, ++#endif + {EM_MIPS_RS3_LE, EM_MIPS_RS3_LE, ELFCLASS32, ELFDATA2LSB, (char*)"MIPSel"}, + {EM_MIPS, EM_MIPS, ELFCLASS32, ELFDATA2MSB, (char*)"MIPS"}, + {EM_PARISC, EM_PARISC, ELFCLASS32, ELFDATA2MSB, (char*)"PARISC"}, +@@ -1996,6 +2011,8 @@ void * os::dll_load(const char *filename, char *ebuf, int ebuflen) + static Elf32_Half running_arch_code=EM_ARM; + #elif (defined S390) + static Elf32_Half running_arch_code=EM_S390; ++ #elif (defined __sw_64) && (defined SW64) ++ static Elf32_Half running_arch_code=EM_SW_64; + #elif (defined ALPHA) + static Elf32_Half running_arch_code=EM_ALPHA; + #elif (defined MIPSEL) +@@ -2012,7 +2029,7 @@ void * os::dll_load(const char *filename, char *ebuf, int ebuflen) + static Elf32_Half running_arch_code=EM_LOONGARCH; + #else + #error Method os::dll_load requires that one of following is defined:\ +- IA32, AMD64, IA64, __sparc, __powerpc__, ARM, S390, ALPHA, MIPS, MIPSEL, PARISC, M68K, AARCH64, LOONGARCH64 ++ IA32, AMD64, IA64, __sparc, __powerpc__, ARM, S390, ALPHA, MIPS, MIPSEL, PARISC, M68K, AARCH64, LOONGARCH64, SW64 + #endif + + // Identify compatability class for VM's architecture and library's architecture +@@ -2815,10 +2832,15 @@ void os::pd_commit_memory_or_exit(char* addr, size_t size, bool exec, + } + } + ++// Define MAP_HUGETLB here so we can build HotSpot on old systems. ++#ifdef SW64 ++#define MAP_HUGETLB 0x100000 ++#else + // Define MAP_HUGETLB here so we can build HotSpot on old systems. + #ifndef MAP_HUGETLB + #define MAP_HUGETLB 0x40000 + #endif ++#endif + + // Define MADV_HUGEPAGE here so we can build HotSpot on old systems. + #ifndef MADV_HUGEPAGE +@@ -3519,7 +3541,8 @@ size_t os::Linux::find_large_page_size() { + + #ifndef ZERO + large_page_size = IA32_ONLY(4 * M) AMD64_ONLY(2 * M) IA64_ONLY(256 * M) SPARC_ONLY(4 * M) +- ARM_ONLY(2 * M) PPC_ONLY(4 * M) AARCH64_ONLY(2 * M); ++ ARM_ONLY(2 * M) PPC_ONLY(4 * M) AARCH64_ONLY(2 * M) SW64_ONLY(8 * M); ++ + #endif // ZERO + + FILE *fp = fopen("/proc/meminfo", "r"); +diff --git a/hotspot/src/os/linux/vm/os_perf_linux.cpp b/hotspot/src/os/linux/vm/os_perf_linux.cpp +index 0d1f75810a..8863a09bb0 100644 +--- a/hotspot/src/os/linux/vm/os_perf_linux.cpp ++++ b/hotspot/src/os/linux/vm/os_perf_linux.cpp +@@ -50,6 +50,9 @@ + #ifdef TARGET_ARCH_ppc + # include "vm_version_ext_ppc.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "vm_version_ext_sw64.hpp" ++#endif + + #include + #include +diff --git a/hotspot/src/os_cpu/linux_sw64/vm/assembler_linux_sw64.cpp b/hotspot/src/os_cpu/linux_sw64/vm/assembler_linux_sw64.cpp +new file mode 100755 +index 0000000000..6079c3d0b8 +--- /dev/null ++++ b/hotspot/src/os_cpu/linux_sw64/vm/assembler_linux_sw64.cpp +@@ -0,0 +1,65 @@ ++/* ++ * Copyright (c) 1999, 2010, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#include "precompiled.hpp" ++#include "asm/macroAssembler.hpp" ++#include "asm/macroAssembler.inline.hpp" ++#include "runtime/os.hpp" ++#include "runtime/threadLocalStorage.hpp" ++ ++void MacroAssembler::int3() { ++ li(T12, CAST_FROM_FN_PTR(address, os::breakpoint)); ++ call(T12); ++} ++ ++void MacroAssembler::get_thread(Register thread) { ++ // call pthread_getspecific ++ // void * pthread_getspecific(pthread_key_t key); ++ ++ pushad(); ++ if (Assembler::is_simm16(ThreadLocalStorage::thread_index())) { ++ ldi(A0, R0, ThreadLocalStorage::thread_index()); ++ } else { ++ li(A0, ThreadLocalStorage::thread_index()); ++ } ++ call(CAST_FROM_FN_PTR(address, pthread_getspecific), relocInfo::runtime_call_type); ++ ++ int off;//depending on the sd sequence in pushad(); ++ ++ if (thread->encoding() >= V0->encoding() && thread->encoding() <= T7->encoding()) ++ { ++ off = 26 - thread->encoding(); ++ stl(V0, SP, off * wordSize); //sd V0 to stack, thus after popad(), thread would not be pop. ++ } ++ else if (thread->encoding() >= FP->encoding() && thread->encoding() <= GP->encoding()) ++ { ++ off = 32 - thread->encoding(); ++ stl(V0, SP, off * wordSize); //sd V0 to stack, thus after popad(), thread would not be pop. ++ } ++ else ++ { ++ move(thread, V0); //thread does not push in stack. ++ } ++ popad(); ++} +diff --git a/hotspot/src/os_cpu/linux_sw64/vm/atomic_linux_sw64.inline.hpp b/hotspot/src/os_cpu/linux_sw64/vm/atomic_linux_sw64.inline.hpp +new file mode 100755 +index 0000000000..d9c2beda23 +--- /dev/null ++++ b/hotspot/src/os_cpu/linux_sw64/vm/atomic_linux_sw64.inline.hpp +@@ -0,0 +1,230 @@ ++/* ++ * Copyright (c) 1999, 2013, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef OS_CPU_LINUX_SW64_VM_ATOMIC_LINUX_SW64_INLINE_HPP ++#define OS_CPU_LINUX_SW64_VM_ATOMIC_LINUX_SW64_INLINE_HPP ++ ++#include "orderAccess_linux_sw64.inline.hpp" ++#include "runtime/atomic.hpp" ++#include "runtime/os.hpp" ++#include "vm_version_sw64.hpp" ++ ++// Implementation of class atomic ++ ++inline void Atomic::store (jbyte store_value, jbyte* dest) { *dest = store_value; } ++inline void Atomic::store (jshort store_value, jshort* dest) { *dest = store_value; } ++inline void Atomic::store (jint store_value, jint* dest) { *dest = store_value; } ++inline void Atomic::store (jlong store_value, jlong* dest) { *dest = store_value; } ++inline void Atomic::store_ptr(intptr_t store_value, intptr_t* dest) { *dest = store_value; } ++inline void Atomic::store_ptr(void* store_value, void* dest) { *(void**)dest = store_value; } ++ ++inline void Atomic::store (jbyte store_value, volatile jbyte* dest) { *dest = store_value; } ++inline void Atomic::store (jshort store_value, volatile jshort* dest) { *dest = store_value; } ++inline void Atomic::store (jint store_value, volatile jint* dest) { *dest = store_value; } ++inline void Atomic::store (jlong store_value, volatile jlong* dest) { *dest = store_value; } ++inline void Atomic::store_ptr(intptr_t store_value, volatile intptr_t* dest) { *dest = store_value; } ++inline void Atomic::store_ptr(void* store_value, volatile void* dest) { *(void**)dest = store_value; } ++ ++inline jlong Atomic::load (volatile jlong* src) { return *src; } ++ ++///////////implementation of Atomic::add*///////////////// ++inline jint Atomic::add (jint add_value, volatile jint* dest) { ++ jint __ret, __tmp; ++ jlong __addr; ++ __asm__ __volatile__ ( ++ "1: ldi %[__addr],%[__dest]\n\t" ++ " lldw %[__tmp],0(%[__addr])\n\t" ++ " ldi %[__ret],1\n\t" ++ " wr_f %[__ret]\n\t" ++ " addw %[__tmp],%[__val],%[__ret]\n\t" ++ " mov %[__ret],%[__tmp]\n\t" ++ " .align 3\n\t" ++ " lstw %[__tmp],0(%[__addr])\n\t" ++ " rd_f %[__tmp]\n\t" ++ " beq %[__tmp],1b\n\t" ++ " \n\t" ++ : [__ret]"=&r" (__ret), [__addr]"=&r"(__addr), [__tmp]"=&r"(__tmp) ++ : [__dest] "m" (*(volatile jint*)dest), [__val] "Ir" (add_value) ++ : "memory" ); ++ ++ return __ret; ++} ++ ++inline intptr_t Atomic::add_ptr (intptr_t add_value, volatile intptr_t* dest) { ++ jlong __ret, __tmp; ++ jlong __addr; ++ __asm__ __volatile__ ( ++ "1: ldi %[__addr],%[__dest]\n\t" ++ " lldl %[__tmp],0(%[__addr])\n\t" ++ " ldi %[__ret],1\n\t" ++ " wr_f %[__ret]\n\t" ++ " addl %[__tmp],%[__val],%[__ret]\n\t" ++ " mov %[__ret],%[__tmp]\n\t" ++ " .align 3\n\t" ++ " lstl %[__tmp],0(%[__addr])\n\t" ++ " rd_f %[__tmp]\n\t" ++ " beq %[__tmp],1b\n\t" ++ " \n\t" ++ : [__ret]"=&r" (__ret), [__addr]"=&r"(__addr), [__tmp]"=&r"(__tmp) ++ : [__dest] "m" (*(volatile jlong*)dest), [__val] "Ir"(add_value) ++ : "memory" ); ++ ++ return __ret; ++} ++ ++inline void* Atomic::add_ptr (intptr_t add_value, volatile void* dest) { ++ return (void*)add_ptr((intptr_t)add_value, (volatile intptr_t*)dest); ++} ++ ++///////////implementation of Atomic::inc*///////////////// ++inline void Atomic::inc (volatile jint* dest) { (void)add(1, dest); } ++inline void Atomic::inc_ptr (volatile intptr_t* dest) { (void)add_ptr(1, dest); } ++inline void Atomic::inc_ptr (volatile void* dest) { (void)inc_ptr((volatile intptr_t*)dest); } ++ ++///////////implementation of Atomic::dec*///////////////// ++inline void Atomic::dec (volatile jint* dest) { (void)add(-1, dest); } ++inline void Atomic::dec_ptr (volatile intptr_t* dest) { (void)add_ptr(-1, dest); } ++inline void Atomic::dec_ptr (volatile void* dest) { (void)dec_ptr((volatile intptr_t*)dest); } ++ ++ ++///////////implementation of Atomic::xchg*///////////////// ++inline jint Atomic::xchg (jint exchange_value, volatile jint* dest) { ++ jint __ret, __tmp; ++ jlong __addr; ++ __asm__ __volatile__ ( ++ "1: ldi %[__addr],%[__dest]\n\t" ++ " lldw %[__ret],0(%[__addr])\n\t" ++ " ldi %[__tmp],1\n\t" ++ " wr_f %[__tmp]\n\t" ++ " mov %[__val],%[__tmp]\n\t" ++ " .align 3\n\t" ++ " lstw %[__tmp],0(%[__addr])\n\t" ++ " rd_f %[__tmp]\n\t" ++ " beq %[__tmp],1b\n\t" ++ " \n\t" ++ : [__ret]"=&r" (__ret), [__addr]"=&r"(__addr), [__tmp]"=&r"(__tmp) ++ : [__dest] "m" (*(volatile jint*)dest), [__val] "Ir"(exchange_value) /* _val can not be constant in stl */ ++ : "memory" ); ++ return __ret; ++} ++ ++inline intptr_t Atomic::xchg_ptr(intptr_t exchange_value, volatile intptr_t* dest) { ++ jlong __ret, __tmp; ++ jlong __addr; ++ __asm__ __volatile__ ( ++ "1: ldi %[__addr],%[__dest]\n\t" ++ " lldl %[__ret],0(%[__addr])\n\t" ++ " ldi %[__tmp],1\n\t" ++ " wr_f %[__tmp]\n\t" ++ " mov %[__val],%[__tmp]\n\t" ++ " .align 3\n\t" ++ " lstl %[__tmp],0(%[__addr])\n\t" ++ " rd_f %[__tmp]\n\t" ++ " beq %[__tmp],1b\n\t" ++ " \n\t" ++ : [__ret]"=&r" (__ret), [__addr]"=&r"(__addr), [__tmp]"=&r"(__tmp) ++ : [__dest] "m" (*(volatile jlong*)dest), [__val] "Ir"(exchange_value) /* _val can not be constant in stl */ ++ : "memory" ); ++ ++ return __ret; ++} ++ ++inline void* Atomic::xchg_ptr(void* exchange_value, volatile void* dest) { ++ return (void*)xchg_ptr((intptr_t)exchange_value, (volatile intptr_t*)dest); ++} ++ ++///////////implementation of Atomic::cmpxchg*///////////////// ++inline jint Atomic::cmpxchg (jint exchange_value, volatile jint* dest, jint compare_value) { ++ jint __prev, __cmp; ++ jint __tmp; ++ jlong __addr; ++ __asm__ __volatile__ ( ++ "1: ldi %[__addr],%[__dest]\n\t" ++ " lldw %[__prev],0(%[__addr])\n\t" ++ " cmpeq %[__prev],%[__old],%[__cmp]\n\t" ++ " wr_f %[__cmp]\n\t" ++ " mov %[__val],%[__tmp]\n\t" ++ " .align 3\n\t" ++ " lstw %[__tmp],0(%[__addr])\n\t" ++ " rd_f %[__tmp]\n\t" ++ " beq %[__cmp],2f\n\t" ++ " beq %[__tmp],1b\n\t" ++ "2: \n\t" ++ : [__prev]"=&r" (__prev), [__addr]"=&r" (__addr), [__cmp] "=&r" (__cmp), [__tmp] "=&r" (__tmp) ++ : [__dest] "m" (*(volatile jint*)dest), [__old]"Ir" (compare_value), [__val]"Ir" (exchange_value) /* _val can not be constant in stl */ ++ : "memory" ); ++ return __prev; ++} ++ ++inline jlong Atomic::cmpxchg (jlong exchange_value, volatile jlong* dest, jlong compare_value) { ++ jlong __prev, __cmp; ++ jlong __tmp; ++ jlong __addr; ++ __asm__ __volatile__ ( ++ "1: ldi %[__addr],%[__dest]\n\t" ++ " lldl %[__prev],0(%[__addr])\n\t" ++ " cmpeq %[__prev],%[__old],%[__cmp]\n\t" ++ " wr_f %[__cmp]\n\t" ++ " mov %[__val],%[__tmp]\n\t" ++ " .align 3\n\t" ++ " lstl %[__tmp],0(%[__addr])\n\t" ++ " rd_f %[__tmp]\n\t" ++ " beq %[__cmp],2f\n\t" ++ " beq %[__tmp],1b\n\t" ++ "2: \n\t" ++ : [__prev]"=&r" (__prev), [__addr]"=&r" (__addr), [__cmp] "=&r" (__cmp), [__tmp] "=&r" (__tmp) ++ : [__dest] "m" (*(volatile jlong*)dest), [__old]"Ir" (compare_value), [__val]"Ir" (exchange_value) /* _val can not be constant in stl */ ++ : "memory" ); ++ ++ return __prev; ++} ++ ++inline intptr_t Atomic::cmpxchg_ptr(intptr_t exchange_value, volatile intptr_t* dest, intptr_t compare_value) { ++ jlong __prev, __cmp; ++ jlong __tmp, __addr; ++ ++ __asm__ __volatile__ ( ++ "1: ldi %[__addr],%[__dest]\n\t" ++ " lldl %[__prev],0(%[__addr])\n\t" ++ " cmpeq %[__prev],%[__old],%[__cmp]\n\t" ++ " wr_f %[__cmp]\n\t" ++ " mov %[__val],%[__tmp]\n\t" ++ " .align 3\n\t" ++ " lstl %[__tmp],0(%[__addr])\n\t" ++ " rd_f %[__tmp]\n\t" ++ " beq %[__cmp],2f\n\t" ++ " beq %[__tmp],1b\n\t" ++ "2: \n\t" ++ : [__prev]"=&r" (__prev), [__addr]"=&r" (__addr), [__cmp] "=&r" (__cmp), [__tmp] "=&r" (__tmp) ++ : [__dest] "m" (*(volatile intptr_t*)dest), [__old]"Ir" (compare_value), [__val]"Ir" (exchange_value) /* _val can not be constant in stl */ ++ : "memory" ); ++ ++ return __prev; ++} ++ ++inline void* Atomic::cmpxchg_ptr(void* exchange_value, volatile void* dest, void* compare_value) { ++ return (void*)cmpxchg_ptr((intptr_t)exchange_value, (volatile intptr_t*)dest, (intptr_t)compare_value); ++} ++ ++#endif // OS_CPU_LINUX_SW64_VM_ATOMIC_LINUX_SW64_INLINE_HPP +diff --git a/hotspot/src/os_cpu/linux_sw64/vm/bytes_linux_sw64.inline.hpp b/hotspot/src/os_cpu/linux_sw64/vm/bytes_linux_sw64.inline.hpp +new file mode 100755 +index 0000000000..e7392eec53 +--- /dev/null ++++ b/hotspot/src/os_cpu/linux_sw64/vm/bytes_linux_sw64.inline.hpp +@@ -0,0 +1,36 @@ ++/* ++ * Copyright (c) 1999, 2010, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef OS_CPU_LINUX_SW64_VM_BYTES_LINUX_SW64_INLINE_HPP ++#define OS_CPU_LINUX_SW64_VM_BYTES_LINUX_SW64_INLINE_HPP ++ ++#include ++ ++// Efficient swapping of data bytes from Java byte ++// ordering to native byte ordering and vice versa. ++inline u2 Bytes::swap_u2(u2 x) { return bswap_16(x); } ++inline u4 Bytes::swap_u4(u4 x) { return bswap_32(x); } ++inline u8 Bytes::swap_u8(u8 x) { return bswap_64(x); } ++ ++#endif // OS_CPU_LINUX_SW64_VM_BYTES_LINUX_SW64_INLINE_HPP +diff --git a/hotspot/src/os_cpu/linux_sw64/vm/copy_linux_sw64.inline.hpp b/hotspot/src/os_cpu/linux_sw64/vm/copy_linux_sw64.inline.hpp +new file mode 100755 +index 0000000000..6fa58f0d03 +--- /dev/null ++++ b/hotspot/src/os_cpu/linux_sw64/vm/copy_linux_sw64.inline.hpp +@@ -0,0 +1,124 @@ ++/* ++ * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef OS_CPU_LINUX_SW64_VM_COPY_LINUX_SW64_INLINE_HPP ++#define OS_CPU_LINUX_SW64_VM_COPY_LINUX_SW64_INLINE_HPP ++ ++static void pd_conjoint_words(HeapWord* from, HeapWord* to, size_t count) { ++ (void)memmove(to, from, count * HeapWordSize); ++} ++ ++static void pd_disjoint_words(HeapWord* from, HeapWord* to, size_t count) { ++ switch (count) { ++ case 8: to[7] = from[7]; ++ case 7: to[6] = from[6]; ++ case 6: to[5] = from[5]; ++ case 5: to[4] = from[4]; ++ case 4: to[3] = from[3]; ++ case 3: to[2] = from[2]; ++ case 2: to[1] = from[1]; ++ case 1: to[0] = from[0]; ++ case 0: break; ++ default: ++ (void)memcpy(to, from, count * HeapWordSize); ++ break; ++ } ++} ++ ++static void pd_disjoint_words_atomic(HeapWord* from, HeapWord* to, size_t count) { ++ switch (count) { ++ case 8: to[7] = from[7]; ++ case 7: to[6] = from[6]; ++ case 6: to[5] = from[5]; ++ case 5: to[4] = from[4]; ++ case 4: to[3] = from[3]; ++ case 3: to[2] = from[2]; ++ case 2: to[1] = from[1]; ++ case 1: to[0] = from[0]; ++ case 0: break; ++ default: ++ while (count-- > 0) { ++ *to++ = *from++; ++ } ++ break; ++ } ++} ++ ++static void pd_aligned_conjoint_words(HeapWord* from, HeapWord* to, size_t count) { ++ pd_conjoint_words(from, to, count); ++} ++ ++static void pd_aligned_disjoint_words(HeapWord* from, HeapWord* to, size_t count) { ++ pd_disjoint_words(from, to, count); ++} ++ ++static void pd_conjoint_bytes(void* from, void* to, size_t count) { ++ (void)memmove(to, from, count); ++} ++ ++static void pd_conjoint_bytes_atomic(void* from, void* to, size_t count) { ++ pd_conjoint_bytes(from, to, count); ++} ++ ++static void pd_conjoint_jshorts_atomic(jshort* from, jshort* to, size_t count) { ++ copy_conjoint_atomic(from, to, count); ++} ++ ++static void pd_conjoint_jints_atomic(jint* from, jint* to, size_t count) { ++ copy_conjoint_atomic(from, to, count); ++} ++ ++static void pd_conjoint_jlongs_atomic(jlong* from, jlong* to, size_t count) { ++ copy_conjoint_atomic(from, to, count); ++} ++ ++static void pd_conjoint_oops_atomic(oop* from, oop* to, size_t count) { ++ //assert(!UseCompressedOops, "foo!"); ++ assert(HeapWordSize == BytesPerOop, "heapwords and oops must be the same size"); ++ copy_conjoint_atomic(from, to, count); ++} ++ ++static void pd_arrayof_conjoint_bytes(HeapWord* from, HeapWord* to, size_t count) { ++ pd_conjoint_bytes_atomic(from, to, count); ++} ++ ++static void pd_arrayof_conjoint_jshorts(HeapWord* from, HeapWord* to, size_t count) { ++ pd_conjoint_jshorts_atomic((jshort*)from, (jshort*)to, count); ++} ++ ++static void pd_arrayof_conjoint_jints(HeapWord* from, HeapWord* to, size_t count) { ++ pd_conjoint_jints_atomic((jint*)from, (jint*)to, count); ++} ++ ++static void pd_arrayof_conjoint_jlongs(HeapWord* from, HeapWord* to, size_t count) { ++ pd_conjoint_jlongs_atomic((jlong*)from, (jlong*)to, count); ++} ++ ++static void pd_arrayof_conjoint_oops(HeapWord* from, HeapWord* to, size_t count) { ++ //assert(!UseCompressedOops, "foo!"); ++ assert(BytesPerLong == BytesPerOop, "jlongs and oops must be the same size"); ++ pd_conjoint_oops_atomic((oop*)from, (oop*)to, count); ++} ++ ++#endif // OS_CPU_LINUX_SW64_VM_COPY_LINUX_SW64_INLINE_HPP +diff --git a/hotspot/src/os_cpu/linux_sw64/vm/globals_linux_sw64.hpp b/hotspot/src/os_cpu/linux_sw64/vm/globals_linux_sw64.hpp +new file mode 100755 +index 0000000000..97e4263ed2 +--- /dev/null ++++ b/hotspot/src/os_cpu/linux_sw64/vm/globals_linux_sw64.hpp +@@ -0,0 +1,42 @@ ++/* ++ * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef OS_CPU_LINUX_SW64_VM_GLOBALS_LINUX_SW64_HPP ++#define OS_CPU_LINUX_SW64_VM_GLOBALS_LINUX_SW64_HPP ++ ++// Sets the default values for platform dependent flags used by the runtime system. ++// (see globals.hpp) ++ ++define_pd_global(bool, DontYieldALot, false); ++define_pd_global(intx, ThreadStackSize, 1024); // 0 => use system default ++define_pd_global(intx, VMThreadStackSize, 1024); ++ ++define_pd_global(intx, CompilerThreadStackSize, 0); ++ ++define_pd_global(uintx,JVMInvokeMethodSlack, 8192); ++ ++// Used on 64 bit platforms for UseCompressedOops base address ++define_pd_global(uintx,HeapBaseMinAddress, 2*G); ++ ++#endif // OS_CPU_LINUX_SW64_VM_GLOBALS_LINUX_SW64_HPP +diff --git a/hotspot/src/os_cpu/linux_sw64/vm/linux_sw64.ad b/hotspot/src/os_cpu/linux_sw64/vm/linux_sw64.ad +new file mode 100755 +index 0000000000..9c729290df +--- /dev/null ++++ b/hotspot/src/os_cpu/linux_sw64/vm/linux_sw64.ad +@@ -0,0 +1,156 @@ ++// ++// Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. ++// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++// ++// This code is free software; you can redistribute it and/or modify it ++// under the terms of the GNU General Public License version 2 only, as ++// published by the Free Software Foundation. ++// ++// This code is distributed in the hope that it will be useful, but WITHOUT ++// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// version 2 for more details (a copy is included in the LICENSE file that ++// accompanied this code). ++// ++// You should have received a copy of the GNU General Public License version ++// 2 along with this work; if not, write to the Free Software Foundation, ++// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++// ++// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++// or visit www.oracle.com if you need additional information or have any ++// questions. ++// ++// ++ ++// SW64 Linux Architecture Description File ++ ++//----------OS-DEPENDENT ENCODING BLOCK---------------------------------------- ++// This block specifies the encoding classes used by the compiler to ++// output byte streams. Encoding classes generate functions which are ++// called by Machine Instruction Nodes in order to generate the bit ++// encoding of the instruction. Operands specify their base encoding ++// interface with the interface keyword. There are currently ++// supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, & ++// COND_INTER. REG_INTER causes an operand to generate a function ++// which returns its register number when queried. CONST_INTER causes ++// an operand to generate a function which returns the value of the ++// constant when queried. MEMORY_INTER causes an operand to generate ++// four functions which return the Base Register, the Index Register, ++// the Scale Value, and the Offset Value of the operand when queried. ++// COND_INTER causes an operand to generate six functions which return ++// the encoding code (ie - encoding bits for the instruction) ++// associated with each basic boolean condition for a conditional ++// instruction. Instructions specify two basic values for encoding. ++// They use the ins_encode keyword to specify their encoding class ++// (which must be one of the class names specified in the encoding ++// block), and they use the opcode keyword to specify, in order, their ++// primary, secondary, and tertiary opcode. Only the opcode sections ++// which a particular instruction needs for encoding need to be ++// specified. ++ ++encode %{ ++ // Build emit functions for each basic byte or larger field in the intel ++ // encoding scheme (opcode, rm, sib, immediate), and call them from C++ ++ // code in the enc_class source block. Emit functions will live in the ++ // main source block for now. In future, we can generalize this by ++ // adding a syntax that specifies the sizes of fields in an order, ++ // so that the adlc can build the emit functions automagically ++ ++ enc_class Java_To_Runtime(method meth) ++ %{ ++ %} ++ ++ enc_class linux_breakpoint ++ %{ ++ MacroAssembler* masm = new MacroAssembler(&cbuf); ++ masm->call(CAST_FROM_FN_PTR(address, os::breakpoint), relocInfo::runtime_call_type); ++ %} ++ ++ enc_class call_epilog ++ %{ ++ if (VerifyStackAtCalls) { ++ // Check that stack depth is unchanged: find majik cookie on stack ++ int framesize = ra_->reg2offset_unchecked(OptoReg::add(ra_->_matcher._old_SP,-2)); ++ if(framesize >= 128) { ++ emit_opcode(cbuf, 0x81); // cmp [esp+0],0xbadb1ood ++ emit_d8(cbuf,0xBC); ++ emit_d8(cbuf,0x24); ++ emit_d32(cbuf,framesize); // Find majik cookie from ESP ++ emit_d32(cbuf, 0xbadb100d); ++ } ++ else { ++ emit_opcode(cbuf, 0x81); // cmp [esp+0],0xbadb1ood ++ emit_d8(cbuf,0x7C); ++ emit_d8(cbuf,0x24); ++ emit_d8(cbuf,framesize); // Find majik cookie from ESP ++ emit_d32(cbuf, 0xbadb100d); ++ } ++ // jmp EQ around INT3 ++ // QQQ TODO ++ const int jump_around = 5; // size of call to breakpoint, 1 for CC ++ emit_opcode(cbuf, 0x74); ++ emit_d8(cbuf, jump_around); ++ // QQQ temporary ++ emit_break(cbuf); ++ // Die if stack mismatch ++ // emit_opcode(cbuf,0xCC); ++ } ++ %} ++ ++%} ++ ++// INSTRUCTIONS -- Platform dependent ++ ++//----------OS and Locking Instructions---------------------------------------- ++ ++// This name is KNOWN by the ADLC and cannot be changed. ++// The ADLC forces a 'TypeRawPtr::BOTTOM' output type ++// for this guy. ++instruct tlsLoadP(eAXRegP dst, eFlagsReg cr) %{ ++%{ ++ match(Set dst (ThreadLocal)); ++ effect(DEF dst, KILL cr); ++ ++ format %{ "MOV EAX, Thread::current()" %} ++ ins_encode( linux_tlsencode(dst) ); ++ ins_pipe( ialu_reg_fat ); ++%} ++ ++// Die now ++instruct ShouldNotReachHere() ++%{ ++ match(Halt); ++ ++ // Use the following format syntax ++ format %{ "int3\t# ShouldNotReachHere" %} ++ // QQQ TODO for now call breakpoint ++ // opcode(0xCC); ++ // ins_encode(Opc); ++ ins_encode(linux_breakpoint); ++ ins_pipe(pipe_slow); ++%} ++ ++ ++// Platform dependent source ++ ++source ++%{ ++// emit an interrupt that is caught by the debugger ++void emit_break(CodeBuffer& cbuf) { ++ // Debugger doesn't really catch this but best we can do so far QQQ ++#define __ masm. ++ __ lui(T12, Assembler::split_high((int)os::breakpoint)); ++ __ addiu(T12, T12, Assembler::split_low((int)os::breakpoint)); ++ __ jalr(T12); ++} ++ ++void MachBreakpointNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { ++ emit_break(cbuf); ++} ++ ++uint MachBreakpointNode::size(PhaseRegAlloc* ra_) const { ++ //return 5; ++ return 16; ++} ++ ++%} +diff --git a/hotspot/src/os_cpu/linux_sw64/vm/linux_sw64.s b/hotspot/src/os_cpu/linux_sw64/vm/linux_sw64.s +new file mode 100755 +index 0000000000..5b35589038 +--- /dev/null ++++ b/hotspot/src/os_cpu/linux_sw64/vm/linux_sw64.s +@@ -0,0 +1,24 @@ ++# ++# Copyright (c) 2004, 2013, Oracle and/or its affiliates. All rights reserved. ++# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++# ++# This code is free software; you can redistribute it and/or modify it ++# under the terms of the GNU General Public License version 2 only, as ++# published by the Free Software Foundation. ++# ++# This code is distributed in the hope that it will be useful, but WITHOUT ++# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++# version 2 for more details (a copy is included in the LICENSE file that ++# accompanied this code). ++# ++# You should have received a copy of the GNU General Public License version ++# 2 along with this work; if not, write to the Free Software Foundation, ++# Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++# ++# Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++# or visit www.oracle.com if you need additional information or have any ++# questions. ++# ++ ++ +diff --git a/hotspot/src/os_cpu/linux_sw64/vm/orderAccess_linux_sw64.inline.hpp b/hotspot/src/os_cpu/linux_sw64/vm/orderAccess_linux_sw64.inline.hpp +new file mode 100755 +index 0000000000..9994d32ae5 +--- /dev/null ++++ b/hotspot/src/os_cpu/linux_sw64/vm/orderAccess_linux_sw64.inline.hpp +@@ -0,0 +1,110 @@ ++/* ++ * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef OS_CPU_LINUX_SW64_VM_ORDERACCESS_LINUX_SW64_INLINE_HPP ++#define OS_CPU_LINUX_SW64_VM_ORDERACCESS_LINUX_SW64_INLINE_HPP ++ ++#include "runtime/atomic.hpp" ++#include "runtime/orderAccess.hpp" ++#include "vm_version_sw64.hpp" ++ ++#define inlasm_sync() __asm__ __volatile__ ("memb" : : : "memory"); ++ ++inline void OrderAccess::loadload() { inlasm_sync(); } ++inline void OrderAccess::storestore() { inlasm_sync(); } ++inline void OrderAccess::loadstore() { inlasm_sync(); } ++inline void OrderAccess::storeload() { inlasm_sync(); } ++ ++inline void OrderAccess::acquire() { inlasm_sync(); } ++inline void OrderAccess::release() { inlasm_sync(); } ++inline void OrderAccess::fence() { inlasm_sync(); } ++ ++//implementation of load_acquire ++inline jbyte OrderAccess::load_acquire(volatile jbyte* p) { jbyte data = *p; acquire(); return data; } ++inline jshort OrderAccess::load_acquire(volatile jshort* p) { jshort data = *p; acquire(); return data; } ++inline jint OrderAccess::load_acquire(volatile jint* p) { jint data = *p; acquire(); return data; } ++inline jlong OrderAccess::load_acquire(volatile jlong* p) { jlong tmp = *p; acquire(); return tmp; } ++inline jubyte OrderAccess::load_acquire(volatile jubyte* p) { jubyte data = *p; acquire(); return data; } ++inline jushort OrderAccess::load_acquire(volatile jushort* p) { jushort data = *p; acquire(); return data; } ++inline juint OrderAccess::load_acquire(volatile juint* p) { juint data = *p; acquire(); return data; } ++inline julong OrderAccess::load_acquire(volatile julong* p) { julong tmp = *p; acquire(); return tmp; } ++inline jfloat OrderAccess::load_acquire(volatile jfloat* p) { jfloat data = *p; acquire(); return data; } ++inline jdouble OrderAccess::load_acquire(volatile jdouble* p) { jdouble tmp = *p; acquire(); return tmp; } ++ ++//implementation of load_ptr_acquire ++inline intptr_t OrderAccess::load_ptr_acquire(volatile intptr_t* p) { intptr_t data = *p; acquire(); return data; } ++inline void* OrderAccess::load_ptr_acquire(volatile void* p) { void *data = *(void* volatile *)p; acquire(); return data; } ++inline void* OrderAccess::load_ptr_acquire(const volatile void* p) { void *data = *(void* volatile *)p; acquire(); return data; } ++ ++//implementation of release_store ++inline void OrderAccess::release_store(volatile jbyte* p, jbyte v) { release(); *p = v; } ++inline void OrderAccess::release_store(volatile jshort* p, jshort v) { release(); *p = v; } ++inline void OrderAccess::release_store(volatile jint* p, jint v) { release(); *p = v; } ++inline void OrderAccess::release_store(volatile jlong* p, jlong v) { release(); *p = v; } ++inline void OrderAccess::release_store(volatile jubyte* p, jubyte v) { release(); *p = v; } ++inline void OrderAccess::release_store(volatile jushort* p, jushort v) { release(); *p = v; } ++inline void OrderAccess::release_store(volatile juint* p, juint v) { release(); *p = v; } ++inline void OrderAccess::release_store(volatile julong* p, julong v) { release(); *p = v; } ++inline void OrderAccess::release_store(volatile jfloat* p, jfloat v) { release(); *p = v; } ++inline void OrderAccess::release_store(volatile jdouble* p, jdouble v) { release(); *p = v; } ++ ++//implementation of release_store_ptr ++inline void OrderAccess::release_store_ptr(volatile intptr_t* p, intptr_t v) { release(); *p = v; } ++inline void OrderAccess::release_store_ptr(volatile void* p, void* v) { release(); *(void* volatile *)p = v; } ++ ++//implementation of store_fence ++inline void OrderAccess::store_fence(jbyte* p, jbyte v) { *p = v; fence(); } ++inline void OrderAccess::store_fence(jshort* p, jshort v) { *p = v; fence(); } ++inline void OrderAccess::store_fence(jint* p, jint v) { *p = v; fence(); } ++inline void OrderAccess::store_fence(jlong* p, jlong v) { *p = v; fence(); } ++inline void OrderAccess::store_fence(jubyte* p, jubyte v) { *p = v; fence(); } ++inline void OrderAccess::store_fence(jushort* p, jushort v) { *p = v; fence(); } ++inline void OrderAccess::store_fence(juint* p, juint v) { *p = v; fence(); } ++inline void OrderAccess::store_fence(julong* p, julong v) { *p = v; fence(); } ++inline void OrderAccess::store_fence(jfloat* p, jfloat v) { *p = v; fence(); } ++inline void OrderAccess::store_fence(jdouble* p, jdouble v) { *p = v; fence(); } ++ ++//implementation of store_ptr_fence ++inline void OrderAccess::store_ptr_fence(intptr_t* p, intptr_t v) { *p = v; fence(); } ++inline void OrderAccess::store_ptr_fence(void** p, void* v) { *p = v; fence(); } ++ ++//implementation of release_store_fence ++inline void OrderAccess::release_store_fence(volatile jbyte* p, jbyte v) { release_store(p, v); fence(); } ++inline void OrderAccess::release_store_fence(volatile jshort* p, jshort v) { release_store(p, v); fence(); } ++inline void OrderAccess::release_store_fence(volatile jint* p, jint v) { release_store(p, v); fence(); } ++inline void OrderAccess::release_store_fence(volatile jlong* p, jlong v) { release_store(p, v); fence(); } ++inline void OrderAccess::release_store_fence(volatile jubyte* p, jubyte v) { release_store(p, v); fence(); } ++inline void OrderAccess::release_store_fence(volatile jushort* p, jushort v) { release_store(p, v); fence(); } ++inline void OrderAccess::release_store_fence(volatile juint* p, juint v) { release_store(p, v); fence(); } ++inline void OrderAccess::release_store_fence(volatile julong* p, julong v) { release_store(p, v); fence(); } ++inline void OrderAccess::release_store_fence(volatile jfloat* p, jfloat v) { release_store(p, v); fence(); } ++inline void OrderAccess::release_store_fence(volatile jdouble* p, jdouble v) { release_store(p, v); fence(); } ++ ++//implementaion of release_store_ptr_fence ++inline void OrderAccess::release_store_ptr_fence(volatile intptr_t* p, intptr_t v) { release_store_ptr(p, v); fence(); } ++inline void OrderAccess::release_store_ptr_fence(volatile void* p, void* v) { release_store_ptr(p, v); fence(); } ++ ++#undef inlasm_sync ++ ++#endif // OS_CPU_LINUX_SW64_VM_ORDERACCESS_LINUX_SW64_INLINE_HPP +diff --git a/hotspot/src/os_cpu/linux_sw64/vm/os_linux_sw64.cpp b/hotspot/src/os_cpu/linux_sw64/vm/os_linux_sw64.cpp +new file mode 100755 +index 0000000000..f375f79064 +--- /dev/null ++++ b/hotspot/src/os_cpu/linux_sw64/vm/os_linux_sw64.cpp +@@ -0,0 +1,847 @@ ++/* ++ * Copyright (c) 1999, 2014, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++// no precompiled headers ++#include "asm/macroAssembler.hpp" ++#include "classfile/classLoader.hpp" ++#include "classfile/systemDictionary.hpp" ++#include "classfile/vmSymbols.hpp" ++#include "code/icBuffer.hpp" ++#include "code/vtableStubs.hpp" ++#include "interpreter/interpreter.hpp" ++#include "jvm_linux.h" ++#include "memory/allocation.inline.hpp" ++#include "mutex_linux.inline.hpp" ++#include "os_share_linux.hpp" ++#include "prims/jniFastGetField.hpp" ++#include "prims/jvm.h" ++#include "prims/jvm_misc.hpp" ++#include "runtime/arguments.hpp" ++#include "runtime/extendedPC.hpp" ++#include "runtime/frame.inline.hpp" ++#include "runtime/interfaceSupport.hpp" ++#include "runtime/java.hpp" ++#include "runtime/javaCalls.hpp" ++#include "runtime/mutexLocker.hpp" ++#include "runtime/osThread.hpp" ++#include "runtime/sharedRuntime.hpp" ++#include "runtime/stubRoutines.hpp" ++#include "runtime/thread.inline.hpp" ++#include "runtime/timer.hpp" ++#include "utilities/events.hpp" ++#include "utilities/vmError.hpp" ++#include "utilities/debug.hpp" ++#include "compiler/disassembler.hpp" ++// put OS-includes here ++# include ++# include ++# include ++# include ++# include ++# include ++# include ++# include ++# include ++# include ++# include ++# include ++# include ++# include ++# include ++# include ++# include ++# include ++# include ++# include ++ ++//not sure ++#define REG_SP 30 //// #define REG_SP 29 ++#define REG_FP 15 //// #define REG_FP 30 ++#define REG_RA 26 ++ ++ ++address __attribute__((always_inline)) os::current_stack_pointer() { ++ register void *ssp; ++ __asm__ (" mov $sp,%0\n":"=r"(ssp)); ++ ++ return (address) (char *)ssp; ++} ++ ++char* os::non_memory_address_word() { ++ // Must never look like an address returned by reserve_memory, ++ // even in its subfields (as defined by the CPU immediate fields, ++ // if the CPU splits constants across multiple instructions). ++ ++ return (char*) -1; ++} ++ ++void os::initialize_thread(Thread* thr) { ++// Nothing to do. ++} ++ ++address os::Linux::ucontext_get_pc(ucontext_t * uc) { ++ //return (address)uc->uc_mcontext.gregs[REG_PC]; ++ return (address)uc->uc_mcontext.sc_pc; ++} ++ ++intptr_t* os::Linux::ucontext_get_sp(ucontext_t * uc) { ++ return (intptr_t*)uc->uc_mcontext.sc_regs[REG_SP]; ++} ++ ++intptr_t* os::Linux::ucontext_get_fp(ucontext_t * uc) { ++ return (intptr_t*)uc->uc_mcontext.sc_regs[REG_FP]; ++} ++ ++address os::ucontext_get_ra(const ucontext_t * uc) { ++ return (address)uc->uc_mcontext.sc_regs[REG_RA]; ++} ++ ++// For Forte Analyzer AsyncGetCallTrace profiling support - thread ++// is currently interrupted by SIGPROF. ++// os::Solaris::fetch_frame_from_ucontext() tries to skip nested signal ++// frames. Currently we don't do that on Linux, so it's the same as ++// os::fetch_frame_from_context(). ++ExtendedPC os::Linux::fetch_frame_from_ucontext(Thread* thread, ++ ucontext_t* uc, intptr_t** ret_sp, intptr_t** ret_fp) { ++ ++ assert(thread != NULL, "just checking"); ++ assert(ret_sp != NULL, "just checking"); ++ assert(ret_fp != NULL, "just checking"); ++ ++ return os::fetch_frame_from_context(uc, ret_sp, ret_fp); ++} ++ ++ExtendedPC os::fetch_frame_from_context(void* ucVoid, ++ intptr_t** ret_sp, intptr_t** ret_fp) { ++ ++ ExtendedPC epc; ++ ucontext_t* uc = (ucontext_t*)ucVoid; ++ ++ if (uc != NULL) { ++ epc = ExtendedPC(os::Linux::ucontext_get_pc(uc)); ++ if (ret_sp) *ret_sp = os::Linux::ucontext_get_sp(uc); ++ if (ret_fp) *ret_fp = os::Linux::ucontext_get_fp(uc); ++ } else { ++ // construct empty ExtendedPC for return value checking ++ epc = ExtendedPC(NULL); ++ if (ret_sp) *ret_sp = (intptr_t *)NULL; ++ if (ret_fp) *ret_fp = (intptr_t *)NULL; ++ } ++ ++ return epc; ++} ++ ++frame os::fetch_frame_from_context(void* ucVoid) { ++ intptr_t* sp; ++ intptr_t* fp; ++ ExtendedPC epc = fetch_frame_from_context(ucVoid, &sp, &fp); ++ frame ret_frame(sp, fp, epc.pc()); ++ ret_frame.fixRa(ucVoid); ++ return ret_frame; ++} ++ ++// By default, gcc always save frame pointer (%ebp/%rbp) on stack. It may get ++// turned off by -fomit-frame-pointer, ++frame os::get_sender_for_C_frame(frame* fr) { ++ return frame(fr->sender_sp(), fr->link(), fr->sender_pc()); ++} ++ ++//intptr_t* _get_previous_fp() { ++intptr_t* __attribute__((always_inline)) os::get_previous_fp() { ++ register void *sfp; ++ __asm__ (" mov $fp,%0\n":"=r"(sfp)); ++ ++ return (intptr_t *)sfp; ++} ++ ++ ++frame os::current_frame() { ++ intptr_t* fp = (intptr_t*)get_previous_fp(); ++ frame myframe((intptr_t*)os::current_stack_pointer(), ++ (intptr_t*)fp, ++ CAST_FROM_FN_PTR(address, os::current_frame)); ++ myframe.init_sender_for_c_frame(CAST_FROM_FN_PTR(address, os::current_frame)); ++ if (os::is_first_C_frame(&myframe)) { ++ // stack is not walkable ++ return frame(); ++ } else { ++ return os::get_sender_for_C_frame(&myframe); ++ } ++} ++ ++//x86 add 2 new assemble function here! ++extern "C" int ++JVM_handle_linux_signal(int sig, ++ siginfo_t* info, ++ void* ucVoid, ++ int abort_if_unrecognized) { ++#ifdef PRINT_SIGNAL_HANDLE ++ tty->print_cr("Signal: signo=%d, sicode=%d, sierrno=%d, siaddr=%lx", ++ info->si_signo, ++ info->si_code, ++ info->si_errno, ++ info->si_addr); ++ if (info->si_signo == 4) // the pc for SIGILL is (info->si_addr)) for SW, but mips and aarch64 are just info->si_addr ++ tty->print_cr("SIGILL 0x%08x", *((int*)(info->si_addr)-1)); ++#endif ++ ++ ucontext_t* uc = (ucontext_t*) ucVoid; ++ ++ Thread* t = ThreadLocalStorage::get_thread_slow(); ++ // Must do this before SignalHandlerMark, if crash protection installed we will longjmp away ++ // (no destructors can be run) ++ os::ThreadCrashProtection::check_crash_protection(sig, t); ++ SignalHandlerMark shm(t); ++ ++ // Note: it's not uncommon that JNI code uses signal/sigset to install ++ // then restore certain signal handler (e.g. to temporarily block SIGPIPE, ++ // or have a SIGILL handler when detecting CPU type). When that happens, ++ // JVM_handle_linux_signal() might be invoked with junk info/ucVoid. To ++ // avoid unnecessary crash when libjsig is not preloaded, try handle signals ++ // that do not require siginfo/ucontext first. ++ ++ if (sig == SIGPIPE/* || sig == SIGXFSZ*/) { ++ // allow chained handler to go first ++ if (os::Linux::chained_handler(sig, info, ucVoid)) { ++ return true; ++ } else { ++ if (PrintMiscellaneous && (WizardMode || Verbose)) { ++ warning("Ignoring SIGPIPE - see bug 4229104"); ++ } ++ return true; ++ } ++ } ++ ++ JavaThread* thread = NULL; ++ VMThread* vmthread = NULL; ++ if (os::Linux::signal_handlers_are_installed) { ++ if (t != NULL ){ ++ if(t->is_Java_thread()) { ++#ifdef PRINT_SIGNAL_HANDLE ++ tty->print_cr("this thread is a java thread"); ++#endif ++ thread = (JavaThread*)t; ++ } ++ else if(t->is_VM_thread()){ ++#ifdef PRINT_SIGNAL_HANDLE ++ tty->print_cr("this thread is a VM thread\n"); ++#endif ++ vmthread = (VMThread *)t; ++ } ++ } ++ } ++ ++ // decide if this trap can be handled by a stub ++ address stub = NULL; ++ address pc = NULL; ++ ++ pc = (address) os::Linux::ucontext_get_pc(uc); ++#ifdef PRINT_SIGNAL_HANDLE ++ tty->print_cr("pc=%lx", pc); ++ os::print_context(tty, uc); ++#endif ++ //%note os_trap_1 ++ if (info != NULL && uc != NULL && thread != NULL) { ++ pc = (address) os::Linux::ucontext_get_pc(uc); ++ // Handle ALL stack overflow variations here ++ if (sig == SIGSEGV) { ++ address addr = (address) info->si_addr; ++#ifdef PRINT_SIGNAL_HANDLE ++ tty->print("handle all stack overflow variations: "); ++ /*tty->print("addr = %lx, stack base = %lx, stack top = %lx\n", ++ addr, ++ thread->stack_base(), ++ thread->stack_base() - thread->stack_size()); ++ */ ++#endif ++ ++ // check if fault address is within thread stack ++ if (addr < thread->stack_base() && ++ addr >= thread->stack_base() - thread->stack_size()) { ++ // stack overflow ++#ifdef PRINT_SIGNAL_HANDLE ++ tty->print("stack exception check \n"); ++#endif ++ if (thread->in_stack_yellow_zone(addr)) { ++#ifdef PRINT_SIGNAL_HANDLE ++ tty->print("exception addr is in yellow zone\n"); ++#endif ++ thread->disable_stack_yellow_zone(); ++ if (thread->thread_state() == _thread_in_Java) { ++ // Throw a stack overflow exception. Guard pages will be reenabled ++ // while unwinding the stack. ++#ifdef PRINT_SIGNAL_HANDLE ++ tty->print("this thread is in java\n"); ++#endif ++ stub = SharedRuntime::continuation_for_implicit_exception(thread, pc, SharedRuntime::STACK_OVERFLOW); ++ } else { ++ // Thread was in the vm or native code. Return and try to finish. ++#ifdef PRINT_SIGNAL_HANDLE ++ tty->print("this thread is in vm or native codes and return\n"); ++#endif ++ return 1; ++ } ++ } else if (thread->in_stack_red_zone(addr)) { ++ // Fatal red zone violation. Disable the guard pages and fall through ++ // to handle_unexpected_exception way down below. ++#ifdef PRINT_SIGNAL_HANDLE ++ tty->print("exception addr is in red zone\n"); ++#endif ++ thread->disable_stack_red_zone(); ++ tty->print_raw_cr("An irrecoverable stack overflow has occurred."); ++ ++ // This is a likely cause, but hard to verify. Let's just print ++ // it as a hint. ++ tty->print_raw_cr("Please check if any of your loaded .so files has " ++ "enabled executable stack (see man page execstack(8))"); ++ } else { ++ // Accessing stack address below sp may cause SEGV if current ++ // thread has MAP_GROWSDOWN stack. This should only happen when ++ // current thread was created by user code with MAP_GROWSDOWN flag ++ // and then attached to VM. See notes in os_linux.cpp. ++#ifdef PRINT_SIGNAL_HANDLE ++ tty->print("exception addr is neither in yellow zone nor in the red one\n"); ++#endif ++ if (thread->osthread()->expanding_stack() == 0) { ++ thread->osthread()->set_expanding_stack(); ++ if (os::Linux::manually_expand_stack(thread, addr)) { ++ thread->osthread()->clear_expanding_stack(); ++ return 1; ++ } ++ thread->osthread()->clear_expanding_stack(); ++ } else { ++ fatal("recursive segv. expanding stack."); ++ } ++ } ++ } //addr < ++ } //sig == SIGSEGV ++ ++ if (thread->thread_state() == _thread_in_Java) { ++ // Java thread running in Java code => find exception handler if any ++ // a fault inside compiled code, the interpreter, or a stub ++#ifdef PRINT_SIGNAL_HANDLE ++ tty->print("java thread running in java code\n"); ++#endif ++ ++ // Handle signal from NativeJump::patch_verified_entry(). ++// if (sig == SIGILL & nativeInstruction_at(pc - 4)->is_sigill_zombie_not_entrant()) { ++ if (sig == SIGILL && (nativeInstruction_at(pc)->is_sigill_zombie_not_entrant() || nativeInstruction_at(pc - 4)->is_sigill_zombie_not_entrant())) { ++ ++#ifdef PRINT_SIGNAL_HANDLE ++ tty->print_cr("verified entry = %lx, sig=%d", nativeInstruction_at(pc), sig); ++#endif ++ stub = SharedRuntime::get_handle_wrong_method_stub(); ++ } else if (sig == SIGSEGV && os::is_poll_address((address)info->si_addr)) { ++#ifdef PRINT_SIGNAL_HANDLE ++ tty->print_cr("polling address = %lx, sig=%d", os::get_polling_page(), sig); ++#endif ++ stub = SharedRuntime::get_poll_stub(pc); ++ } else if (sig == SIGBUS /* && info->si_code == BUS_OBJERR */) { ++ // BugId 4454115: A read from a MappedByteBuffer can fault ++ // here if the underlying file has been truncated. ++ // Do not crash the VM in such a case. ++ CodeBlob* cb = CodeCache::find_blob_unsafe(pc); ++ nmethod* nm = cb->is_nmethod() ? (nmethod*)cb : NULL; ++#ifdef PRINT_SIGNAL_HANDLE ++ tty->print("cb = %lx, nm = %lx\n", cb, nm); ++#endif ++ if (nm != NULL && nm->has_unsafe_access()) { ++ stub = StubRoutines::handler_for_unsafe_access(); ++ } ++ } else if (sig == SIGFPE && ++ (info->si_code == FPE_INTDIV || info->si_code == FPE_FLTDIV)) { ++ stub = SharedRuntime::continuation_for_implicit_exception(thread, ++ pc, ++ SharedRuntime::IMPLICIT_DIVIDE_BY_ZERO); ++ } else if (sig == SIGSEGV && ++ !MacroAssembler::needs_explicit_null_check((intptr_t)info->si_addr)) { ++#ifdef PRINT_SIGNAL_HANDLE ++ tty->print("continuation for implicit exception\n"); ++#endif ++ // Determination of interpreter/vtable stub/compiled code null exception ++ stub = SharedRuntime::continuation_for_implicit_exception(thread, pc, SharedRuntime::IMPLICIT_NULL); ++#ifdef PRINT_SIGNAL_HANDLE ++ tty->print_cr("continuation_for_implicit_exception stub: %lx", stub); ++#endif ++ } ++ } else if (thread->thread_state() == _thread_in_vm && ++ sig == SIGBUS && /* info->si_code == BUS_OBJERR && */ ++ thread->doing_unsafe_access()) { ++#ifdef PRINT_SIGNAL_HANDLE ++ tty->print_cr("SIGBUS in vm thread \n"); ++#endif ++ stub = StubRoutines::handler_for_unsafe_access(); ++ } ++ ++ // jni_fast_GetField can trap at certain pc's if a GC kicks in ++ // and the heap gets shrunk before the field access. ++ if ((sig == SIGSEGV) || (sig == SIGBUS)) { ++#ifdef PRINT_SIGNAL_HANDLE ++ tty->print("jni fast get trap: "); ++#endif ++ address addr = JNI_FastGetField::find_slowcase_pc(pc); ++ if (addr != (address)-1) { ++ stub = addr; ++ } ++#ifdef PRINT_SIGNAL_HANDLE ++ tty->print_cr("addr = %d, stub = %lx", addr, stub); ++#endif ++ } ++ ++ // Check to see if we caught the safepoint code in the ++ // process of write protecting the memory serialization page. ++ // It write enables the page immediately after protecting it ++ // so we can just return to retry the write. ++ if ((sig == SIGSEGV) && ++ os::is_memory_serialize_page(thread, (address) info->si_addr)) { ++#ifdef PRINT_SIGNAL_HANDLE ++ tty->print("write protecting the memory serialiazation page\n"); ++#endif ++ // Block current thread until the memory serialize page permission restored. ++ os::block_on_serialize_page_trap(); ++ return true; ++ } ++ } ++ ++ // Execution protection violation ++ // ++ // This should be kept as the last step in the triage. We don't ++ // have a dedicated trap number for a no-execute fault, so be ++ // conservative and allow other handlers the first shot. ++ // ++ // Note: We don't test that info->si_code == SEGV_ACCERR here. ++ // this si_code is so generic that it is almost meaningless; and ++ // the si_code for this condition may change in the future. ++ // Furthermore, a false-positive should be harmless. ++ if (stub != NULL) { ++#ifdef PRINT_SIGNAL_HANDLE ++ tty->print_cr("resolved stub=%lx\n",stub); ++#endif ++ // save all thread context in case we need to restore it ++ if (thread != NULL) thread->set_saved_exception_pc(pc); ++ ++ uc->uc_mcontext.sc_pc = (greg_t)stub; ++ return true; ++ } ++ ++ // signal-chaining ++ if (os::Linux::chained_handler(sig, info, ucVoid)) { ++#ifdef PRINT_SIGNAL_HANDLE ++ tty->print_cr("signal chaining\n"); ++#endif ++ return true; ++ } ++ ++ if (!abort_if_unrecognized) { ++#ifdef PRINT_SIGNAL_HANDLE ++ tty->print_cr("abort becauce of unrecognized\n"); ++#endif ++ // caller wants another chance, so give it to him ++ return false; ++ } ++ ++ if (pc == NULL && uc != NULL) { ++ pc = os::Linux::ucontext_get_pc(uc); ++ } ++ ++ // unmask current signal ++ sigset_t newset; ++ sigemptyset(&newset); ++ sigaddset(&newset, sig); ++ sigprocmask(SIG_UNBLOCK, &newset, NULL); ++#ifdef PRINT_SIGNAL_HANDLE ++ tty->print_cr("VMError in signal handler\n"); ++#endif ++ VMError err(t, sig, pc, info, ucVoid); ++ err.report_and_die(); ++ ++ ShouldNotReachHere(); ++ return true; // Mute compiler ++} ++ ++// FCSR:...|24| 23 |22|21|... ++// ...|FS|FCC0|FO|FN|... ++void os::Linux::init_thread_fpu_state(void) { ++ // Nothing to do ++} ++ ++int os::Linux::get_fpu_control_word(void) { ++ ShouldNotReachHere(); ++} ++ ++void os::Linux::set_fpu_control_word(int fpu_control) { ++ ShouldNotReachHere(); ++} ++ ++bool os::is_allocatable(size_t bytes) { ++ ++ if (bytes < 2 * G) { ++ return true; ++ } ++ ++ char* addr = reserve_memory(bytes, NULL); ++ ++ if (addr != NULL) { ++ release_memory(addr, bytes); ++ } ++ ++ return addr != NULL; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++// thread stack ++ ++size_t os::Linux::min_stack_allowed = 96 * K; ++ ++ ++// Test if pthread library can support variable thread stack size. LinuxThreads ++// in fixed stack mode allocates 2M fixed slot for each thread. LinuxThreads ++// in floating stack mode and NPTL support variable stack size. ++bool os::Linux::supports_variable_stack_size() { ++ if (os::Linux::is_NPTL()) { ++ // NPTL, yes ++ return true; ++ ++ } else { ++ // Note: We can't control default stack size when creating a thread. ++ // If we use non-default stack size (pthread_attr_setstacksize), both ++ // floating stack and non-floating stack LinuxThreads will return the ++ // same value. This makes it impossible to implement this function by ++ // detecting thread stack size directly. ++ // ++ // An alternative approach is to check %gs. Fixed-stack LinuxThreads ++ // do not use %gs, so its value is 0. Floating-stack LinuxThreads use ++ // %gs (either as LDT selector or GDT selector, depending on kernel) ++ // to access thread specific data. ++ // ++ // Note that %gs is a reserved glibc register since early 2001, so ++ // applications are not allowed to change its value (Ulrich Drepper from ++ // Redhat confirmed that all known offenders have been modified to use ++ // either %fs or TSD). In the worst case scenario, when VM is embedded in ++ // a native application that plays with %gs, we might see non-zero %gs ++ // even LinuxThreads is running in fixed stack mode. As the result, we'll ++ // return true and skip _thread_safety_check(), so we may not be able to ++ // detect stack-heap collisions. But otherwise it's harmless. ++ // ++ return false; ++ } ++} ++ ++// return default stack size for thr_type ++size_t os::Linux::default_stack_size(os::ThreadType thr_type) { ++ // default stack size (compiler thread needs larger stack) ++ size_t s = (thr_type == os::compiler_thread ? 2 * M : 512 * K); ++ return s; ++} ++ ++size_t os::Linux::default_guard_size(os::ThreadType thr_type) { ++ // Creating guard page is very expensive. Java thread has HotSpot ++ // guard page, only enable glibc guard page for non-Java threads. ++ return (thr_type == java_thread ? 0 : page_size()); ++} ++ ++// Java thread: ++// ++// Low memory addresses ++// +------------------------+ ++// | |\ JavaThread created by VM does not have glibc ++// | glibc guard page | - guard, attached Java thread usually has ++// | |/ 1 page glibc guard. ++// P1 +------------------------+ Thread::stack_base() - Thread::stack_size() ++// | |\ ++// | HotSpot Guard Pages | - red and yellow pages ++// | |/ ++// +------------------------+ JavaThread::stack_yellow_zone_base() ++// | |\ ++// | Normal Stack | - ++// | |/ ++// P2 +------------------------+ Thread::stack_base() ++// ++// Non-Java thread: ++// ++// Low memory addresses ++// +------------------------+ ++// | |\ ++// | glibc guard page | - usually 1 page ++// | |/ ++// P1 +------------------------+ Thread::stack_base() - Thread::stack_size() ++// | |\ ++// | Normal Stack | - ++// | |/ ++// P2 +------------------------+ Thread::stack_base() ++// ++// ** P1 (aka bottom) and size ( P2 = P1 - size) are the address and stack size returned from ++// pthread_attr_getstack() ++ ++static void current_stack_region(address * bottom, size_t * size) { ++ if (os::is_primordial_thread()) { ++ // primordial thread needs special handling because pthread_getattr_np() ++ // may return bogus value. ++ *bottom = os::Linux::initial_thread_stack_bottom(); ++ *size = os::Linux::initial_thread_stack_size(); ++ } else { ++ pthread_attr_t attr; ++ ++ int rslt = pthread_getattr_np(pthread_self(), &attr); ++ ++ // JVM needs to know exact stack location, abort if it fails ++ if (rslt != 0) { ++ if (rslt == ENOMEM) { ++ vm_exit_out_of_memory(0, OOM_MMAP_ERROR, "pthread_getattr_np"); ++ } else { ++ fatal(err_msg("pthread_getattr_np failed with errno = %d", rslt)); ++ } ++ } ++ ++ if (pthread_attr_getstack(&attr, (void **)bottom, size) != 0) { ++ fatal("Can not locate current stack attributes!"); ++ } ++ ++ pthread_attr_destroy(&attr); ++ ++ } ++ assert(os::current_stack_pointer() >= *bottom && ++ os::current_stack_pointer() < *bottom + *size, "just checking"); ++} ++ ++address os::current_stack_base() { ++ address bottom; ++ size_t size; ++ current_stack_region(&bottom, &size); ++ return (bottom + size); ++} ++ ++size_t os::current_stack_size() { ++ // stack size includes normal stack and HotSpot guard pages ++ address bottom; ++ size_t size; ++ current_stack_region(&bottom, &size); ++ return size; ++} ++ ++///////////////////////////////////////////////////////////////////////////// ++// helper functions for fatal error handler ++void os::print_register_info(outputStream *st, void *context) { ++ if (context == NULL) return; ++ ++ ucontext_t *uc = (ucontext_t*)context; ++ ++ st->print_cr("Register to memory mapping:"); ++ st->cr(); ++ // this is horrendously verbose but the layout of the registers in the ++ // // context does not match how we defined our abstract Register set, so ++ // // we can't just iterate through the gregs area ++ // ++ // // this is only for the "general purpose" registers ++ st->print("V0=" ); print_location(st, uc->uc_mcontext.sc_regs[0]); ++ st->print("T0=" ); print_location(st, uc->uc_mcontext.sc_regs[1]); ++ st->print("T1=" ); print_location(st, uc->uc_mcontext.sc_regs[2]); ++ st->print("T2=" ); print_location(st, uc->uc_mcontext.sc_regs[3]); ++ st->cr(); ++ st->print("T3=" ); print_location(st, uc->uc_mcontext.sc_regs[4]); ++ st->print("T4=" ); print_location(st, uc->uc_mcontext.sc_regs[5]); ++ st->print("T5=" ); print_location(st, uc->uc_mcontext.sc_regs[6]); ++ st->print("T6=" ); print_location(st, uc->uc_mcontext.sc_regs[7]); ++ st->cr(); ++ st->print("T7=" ); print_location(st, uc->uc_mcontext.sc_regs[8]); ++ st->print("S0=" ); print_location(st, uc->uc_mcontext.sc_regs[9]); ++ st->print("S1=" ); print_location(st, uc->uc_mcontext.sc_regs[10]); ++ st->print("S2=" ); print_location(st, uc->uc_mcontext.sc_regs[11]); ++ st->cr(); ++ st->print("S3=" ); print_location(st, uc->uc_mcontext.sc_regs[12]); ++ st->print("S4=" ); print_location(st, uc->uc_mcontext.sc_regs[13]); ++ st->print("S5=" ); print_location(st, uc->uc_mcontext.sc_regs[14]); ++ st->print("FP=" ); print_location(st, uc->uc_mcontext.sc_regs[15]); ++ st->cr(); ++ st->print("A0=" ); print_location(st, uc->uc_mcontext.sc_regs[16]); ++ st->print("A1=" ); print_location(st, uc->uc_mcontext.sc_regs[17]); ++ st->print("A2=" ); print_location(st, uc->uc_mcontext.sc_regs[18]); ++ st->print("A3=" ); print_location(st, uc->uc_mcontext.sc_regs[19]); ++ st->cr(); ++ st->print("A4=" ); print_location(st, uc->uc_mcontext.sc_regs[20]); ++ st->print("A5=" ); print_location(st, uc->uc_mcontext.sc_regs[21]); ++ st->print("T8=" ); print_location(st, uc->uc_mcontext.sc_regs[22]); ++ st->print("T9=" ); print_location(st, uc->uc_mcontext.sc_regs[23]); ++ st->cr(); ++ st->print("T10=" ); print_location(st, uc->uc_mcontext.sc_regs[24]); ++ st->print("T11=" ); print_location(st, uc->uc_mcontext.sc_regs[25]); ++ st->print("RA=" ); print_location(st, uc->uc_mcontext.sc_regs[26]); ++ st->print("T12=" ); print_location(st, uc->uc_mcontext.sc_regs[27]); ++ st->cr(); ++ st->print("AT=" ); print_location(st, uc->uc_mcontext.sc_regs[28]); ++ st->print("GP=" ); print_location(st, uc->uc_mcontext.sc_regs[29]); ++ st->print("SP=" ); print_location(st, uc->uc_mcontext.sc_regs[30]); ++ st->print("R0=" ); print_location(st, uc->uc_mcontext.sc_regs[31]); ++ st->cr(); ++ ++} ++ ++jint inst_at(address addr, int offset) { ++ return *(jint*) ((long) addr + offset); ++} ++ ++jlong long_at(address addr, int offset) { ++ return *(jlong*) ((long) addr + offset); ++} ++ ++static bool is_op(int insn, Assembler::ops_mem op) { ++ return Assembler::sw2_op(insn) == (int) op; ++} ++ ++static bool is_op(int insn, Assembler::ops_bra op) { ++ return Assembler::sw2_op(insn) == (int) op; ++} ++ ++static void print_context_plus(int reg_num, void *context, outputStream *st) { ++ if (context == NULL) return; ++ ucontext_t *uc = (ucontext_t *) context; ++ int16_t msb_l = 0; ++ int16_t lsb_h = 0; ++ int16_t lsb_l = 0; ++ address addr_for_li48 = 0; ++ address addr = (address) uc->uc_mcontext.sc_regs[reg_num]; ++ const char* type = reg_num == 26 ? "call" : "jmp"; ++ const char* reg_name = reg_num == 26 ? "RA" : "AT"; ++ st->print_cr("Instructions: %s=" PTR_FORMAT ")", reg_name, addr); ++ if (CodeCache::find_blob(addr)) { ++ os::print_hex_dump(st, addr - 64, addr + 64, sizeof (char)); ++ Disassembler::decode(addr - 80, addr + 80, st); ++ st->cr(); ++ if (!SafePatch) { ++ if (is_op(inst_at(addr, -20), Assembler::op_ldi) && ++ is_op(inst_at(addr, -12), Assembler::op_ldih) && ++ is_op(inst_at(addr, -8), Assembler::op_ldi)) { ++ msb_l = inst_at(addr, -20) & 0xffff; ++ lsb_h = inst_at(addr, -12) & 0xffff; ++ lsb_l = inst_at(addr, -8) & 0xffff; ++ addr_for_li48 = (address) (((intptr_t) (msb_l) << 32) + ((intptr_t) (lsb_h) << 16) + (intptr_t) (lsb_l)); ++ } ++ } else { ++ if (is_op(inst_at(addr, 0), Assembler::op_ldi) && ++ is_op(inst_at(addr, 4), Assembler::op_br) && ++ is_op(inst_at(addr, 16), Assembler::op_ldl)) { ++ addr_for_li48 = (address) long_at(addr, 8); ++ } else if (is_op(inst_at(addr, 0), Assembler::op_br) && ++ is_op(inst_at(addr, 12), Assembler::op_ldl) && ++ is_op(inst_at(addr, 16), Assembler::op_ldi)) { ++ addr_for_li48 = (address) long_at(addr, 4); ++ } else { ++ st->print_cr("\nError!\n Not a call/jmp in " INTPTR_FORMAT, addr); ++ addr_for_li48 = 0; ++ } ++ } ++ st->print_cr("Instructions: (address for %s = " PTR_FORMAT ")", type, addr_for_li48); ++ st->print_cr("==============(address in T12=" INTPTR_FORMAT, uc->uc_mcontext.sc_regs[27]); ++ if (CodeCache::find_blob(addr_for_li48)) { ++ os::print_hex_dump(st, addr_for_li48 - 64, addr_for_li48 + 64, sizeof (char)); ++ Disassembler::decode(addr_for_li48 - 80, addr_for_li48 + 80, st); ++ st->cr(); ++ } ++ } else { ++ int offset = 0; ++ int buflen = 100; ++ char buf[buflen]; ++ bool found = os::dll_address_to_function_name(addr_for_li48, buf, buflen, &offset); ++ if (found) { ++ st->print_cr("=====The library name is %s =====", buf); ++ st->cr(); ++ } ++ } ++} ++ ++void os::print_context(outputStream *st, void *context) { ++ if (context == NULL) return; ++ ++ ucontext_t *uc = (ucontext_t*)context; ++ st->print_cr("Registers:"); ++ st->print( "V0=" INTPTR_FORMAT, uc->uc_mcontext.sc_regs[0]); ++ st->print(", T0=" INTPTR_FORMAT, uc->uc_mcontext.sc_regs[1]); ++ st->print(", T1=" INTPTR_FORMAT, uc->uc_mcontext.sc_regs[2]); ++ st->print(", T2=" INTPTR_FORMAT, uc->uc_mcontext.sc_regs[3]); ++ st->cr(); ++ st->print( "T3=" INTPTR_FORMAT, uc->uc_mcontext.sc_regs[4]); ++ st->print(", T4=" INTPTR_FORMAT, uc->uc_mcontext.sc_regs[5]); ++ st->print(", T5=" INTPTR_FORMAT, uc->uc_mcontext.sc_regs[6]); ++ st->print(", T6=" INTPTR_FORMAT, uc->uc_mcontext.sc_regs[7]); ++ st->cr(); ++ st->print( "T7=" INTPTR_FORMAT, uc->uc_mcontext.sc_regs[8]); ++ st->print(", S0=" INTPTR_FORMAT, uc->uc_mcontext.sc_regs[9]); ++ st->print(", S1=" INTPTR_FORMAT, uc->uc_mcontext.sc_regs[10]); ++ st->print(", S2=" INTPTR_FORMAT, uc->uc_mcontext.sc_regs[11]); ++ st->cr(); ++ st->print( "S3=" INTPTR_FORMAT, uc->uc_mcontext.sc_regs[12]); ++ st->print(", S4=" INTPTR_FORMAT, uc->uc_mcontext.sc_regs[13]); ++ st->print(", S5=" INTPTR_FORMAT, uc->uc_mcontext.sc_regs[14]); ++ st->print(", FP=" INTPTR_FORMAT, uc->uc_mcontext.sc_regs[15]); ++ st->cr(); ++ st->print( "A0=" INTPTR_FORMAT, uc->uc_mcontext.sc_regs[16]); ++ st->print(", A1=" INTPTR_FORMAT, uc->uc_mcontext.sc_regs[17]); ++ st->print(", A2=" INTPTR_FORMAT, uc->uc_mcontext.sc_regs[18]); ++ st->print(", A3=" INTPTR_FORMAT, uc->uc_mcontext.sc_regs[19]); ++ st->cr(); ++ st->print( "A4=" INTPTR_FORMAT, uc->uc_mcontext.sc_regs[20]); ++ st->print(", A5=" INTPTR_FORMAT, uc->uc_mcontext.sc_regs[21]); ++ st->print(", T8=" INTPTR_FORMAT, uc->uc_mcontext.sc_regs[22]); ++ st->print(", T9=" INTPTR_FORMAT, uc->uc_mcontext.sc_regs[23]); ++ st->cr(); ++ st->print( "T10=" INTPTR_FORMAT, uc->uc_mcontext.sc_regs[24]); ++ st->print(", T11=" INTPTR_FORMAT, uc->uc_mcontext.sc_regs[25]); ++ st->print(", RA=" INTPTR_FORMAT, uc->uc_mcontext.sc_regs[26]); ++ st->print(", T12=" INTPTR_FORMAT, uc->uc_mcontext.sc_regs[27]); ++ st->cr(); ++ st->print( "AT=" INTPTR_FORMAT, uc->uc_mcontext.sc_regs[28]); ++ st->print(", GP=" INTPTR_FORMAT, uc->uc_mcontext.sc_regs[29]); ++ st->print(", SP=" INTPTR_FORMAT, uc->uc_mcontext.sc_regs[30]); ++ st->print(", R0=" INTPTR_FORMAT, uc->uc_mcontext.sc_regs[31]); ++ st->cr(); ++ st->cr(); ++ ++ intptr_t *sp = (intptr_t *)os::Linux::ucontext_get_sp(uc); ++ st->print_cr("Top of Stack: (sp=" PTR_FORMAT ")", sp); ++ //print_hex_dump(st, (address)sp, (address)(sp + 8*sizeof(intptr_t)), sizeof(intptr_t)); ++ print_hex_dump(st, (address) sp - 32, (address) (sp + 32), sizeof(intptr_t)); ++ st->cr(); ++ ++ // Note: it may be unsafe to inspect memory near pc. For example, pc may ++ // point to garbage if entry point in an nmethod is corrupted. Leave ++ // this at the end, and hope for the best. ++ address pc = os::Linux::ucontext_get_pc(uc); ++ st->print_cr("Instructions: (pc=" PTR_FORMAT ")", pc - 4); ++ print_hex_dump(st, pc - 64, pc + 64, sizeof(char)); ++ Disassembler::decode(pc - 80, pc + 80, st); ++ ++ st->cr(); ++ print_context_plus(26, context, st); ++ print_context_plus(28, context, st); ++} ++ ++void os::setup_fpu() { ++ ++} ++ ++#ifndef PRODUCT ++void os::verify_stack_alignment() { ++ assert(((intptr_t)os::current_stack_pointer() & (StackAlignmentInBytes-1)) == 0, "incorrect stack alignment"); ++} ++#endif +diff --git a/hotspot/src/os_cpu/linux_sw64/vm/os_linux_sw64.hpp b/hotspot/src/os_cpu/linux_sw64/vm/os_linux_sw64.hpp +new file mode 100755 +index 0000000000..a08119bd09 +--- /dev/null ++++ b/hotspot/src/os_cpu/linux_sw64/vm/os_linux_sw64.hpp +@@ -0,0 +1,37 @@ ++/* ++ * Copyright (c) 1999, 2013, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef OS_CPU_LINUX_SW64_VM_OS_LINUX_SW64_HPP ++#define OS_CPU_LINUX_SW64_VM_OS_LINUX_SW64_HPP ++ ++ static void setup_fpu(); ++ static bool is_allocatable(size_t bytes); ++ static intptr_t *get_previous_fp(); ++ static address ucontext_get_ra(const ucontext_t* uc); ++ ++ // Used to register dynamic code cache area with the OS ++ // Note: Currently only used in 64 bit Windows implementations ++ static bool register_code_area(char *low, char *high) { return true; } ++ ++#endif // OS_CPU_LINUX_SW64_VM_OS_LINUX_SW64_HPP +diff --git a/hotspot/src/os_cpu/linux_sw64/vm/prefetch_linux_sw64.inline.hpp b/hotspot/src/os_cpu/linux_sw64/vm/prefetch_linux_sw64.inline.hpp +new file mode 100755 +index 0000000000..1e4c7639f0 +--- /dev/null ++++ b/hotspot/src/os_cpu/linux_sw64/vm/prefetch_linux_sw64.inline.hpp +@@ -0,0 +1,48 @@ ++/* ++ * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef OS_CPU_LINUX_SW64_VM_PREFETCH_LINUX_SW64_INLINE_HPP ++#define OS_CPU_LINUX_SW64_VM_PREFETCH_LINUX_SW64_INLINE_HPP ++#include "runtime/prefetch.hpp" ++ ++ ++inline void Prefetch::read (void *loc, intx interval) { ++ __asm__ __volatile__ ( ++ " fillcs 0(%0) \n" ++ : ++ : "r" ( ((address)loc) +((long)interval) ) ++ : "memory" ++ ); ++} ++ ++inline void Prefetch::write(void *loc, intx interval) { ++ __asm__ __volatile__ ( ++ " fillde 0(%0) \n" ++ : ++ : "r" ( ((address)loc) +((long)interval) ) ++ : "memory" ++ ); ++} ++ ++#endif // OS_CPU_LINUX_SW64_VM_PREFETCH_LINUX_SW64_INLINE_HPP +diff --git a/hotspot/src/os_cpu/linux_sw64/vm/threadLS_linux_sw64.cpp b/hotspot/src/os_cpu/linux_sw64/vm/threadLS_linux_sw64.cpp +new file mode 100755 +index 0000000000..c892ad35ab +--- /dev/null ++++ b/hotspot/src/os_cpu/linux_sw64/vm/threadLS_linux_sw64.cpp +@@ -0,0 +1,67 @@ ++/* ++ * Copyright (c) 1999, 2010, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#include "precompiled.hpp" ++#include "runtime/thread.inline.hpp" ++#include "runtime/threadLocalStorage.hpp" ++ ++// Map stack pointer (%esp) to thread pointer for faster TLS access ++// ++// Here we use a flat table for better performance. Getting current thread ++// is down to one memory access (read _sp_map[%esp>>12]) in generated code ++// and two in runtime code (-fPIC code needs an extra load for _sp_map). ++// ++// This code assumes stack page is not shared by different threads. It works ++// in 32-bit VM when page size is 4K (or a multiple of 4K, if that matters). ++// ++// Notice that _sp_map is allocated in the bss segment, which is ZFOD ++// (zero-fill-on-demand). While it reserves 4M address space upfront, ++// actual memory pages are committed on demand. ++// ++// If an application creates and destroys a lot of threads, usually the ++// stack space freed by a thread will soon get reused by new thread ++// (this is especially true in NPTL or LinuxThreads in fixed-stack mode). ++// No memory page in _sp_map is wasted. ++// ++// However, it's still possible that we might end up populating & ++// committing a large fraction of the 4M table over time, but the actual ++// amount of live data in the table could be quite small. The max wastage ++// is less than 4M bytes. If it becomes an issue, we could use madvise() ++// with MADV_DONTNEED to reclaim unused (i.e. all-zero) pages in _sp_map. ++// MADV_DONTNEED on Linux keeps the virtual memory mapping, but zaps the ++// physical memory page (i.e. similar to MADV_FREE on Solaris). ++ ++ ++void ThreadLocalStorage::generate_code_for_get_thread() { ++ // nothing we can do here for user-level thread ++} ++ ++void ThreadLocalStorage::pd_init() { ++ assert(align_size_down(os::vm_page_size(), PAGE_SIZE) == os::vm_page_size(), ++ "page size must be multiple of PAGE_SIZE"); ++} ++ ++void ThreadLocalStorage::pd_set_thread(Thread* thread) { ++ os::thread_local_storage_at_put(ThreadLocalStorage::thread_index(), thread); ++} +diff --git a/hotspot/src/os_cpu/linux_sw64/vm/threadLS_linux_sw64.hpp b/hotspot/src/os_cpu/linux_sw64/vm/threadLS_linux_sw64.hpp +new file mode 100755 +index 0000000000..9a336f7071 +--- /dev/null ++++ b/hotspot/src/os_cpu/linux_sw64/vm/threadLS_linux_sw64.hpp +@@ -0,0 +1,40 @@ ++/* ++ * Copyright (c) 1999, 2010, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef OS_CPU_LINUX_SW64_VM_THREADLS_LINUX_SW64_HPP ++#define OS_CPU_LINUX_SW64_VM_THREADLS_LINUX_SW64_HPP ++ ++ // Processor dependent parts of ThreadLocalStorage ++ //only the low 2G space for user program in Linux ++ ++#define SP_BITLENGTH 34 //TODO: ? ++#define PAGE_SHIFT 13 ++#define PAGE_SIZE (1UL << PAGE_SHIFT) ++ ++public: ++ ++ static Thread* thread() { ++ return (Thread*) os::thread_local_storage_at(thread_index()); ++ } ++#endif // OS_CPU_LINUX_SW64_VM_THREADLS_LINUX_SW64_HPP +diff --git a/hotspot/src/os_cpu/linux_sw64/vm/thread_linux_sw64.cpp b/hotspot/src/os_cpu/linux_sw64/vm/thread_linux_sw64.cpp +new file mode 100755 +index 0000000000..71a66ed52e +--- /dev/null ++++ b/hotspot/src/os_cpu/linux_sw64/vm/thread_linux_sw64.cpp +@@ -0,0 +1,104 @@ ++/* ++ * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#include "precompiled.hpp" ++#include "runtime/frame.inline.hpp" ++#include "runtime/thread.inline.hpp" ++#include "runtime/sharedRuntime.hpp" ++ ++void JavaThread::pd_initialize() ++{ ++ _anchor.clear(); ++ ++ // A non-existing address as error detector ++ if (CompileBroker::get_compilation_id() > 0) ++ _handle_wrong_method_stub = (address)SharedRuntime::get_handle_wrong_method_stub(); ++ else ++ _handle_wrong_method_stub = (address)0x2B2B2B; ++} ++ ++// For Forte Analyzer AsyncGetCallTrace profiling support - thread is ++// currently interrupted by SIGPROF ++bool JavaThread::pd_get_top_frame_for_signal_handler(frame* fr_addr, ++ void* ucontext, bool isInJava) { ++ ++ assert(Thread::current() == this, "caller must be current thread"); ++ return pd_get_top_frame(fr_addr, ucontext, isInJava); ++} ++ ++bool JavaThread::pd_get_top_frame_for_profiling(frame* fr_addr, void* ucontext, bool isInJava) { ++ return pd_get_top_frame(fr_addr, ucontext, isInJava); ++} ++ ++bool JavaThread::pd_get_top_frame(frame* fr_addr, void* ucontext, bool isInJava) { ++ assert(this->is_Java_thread(), "must be JavaThread"); ++ JavaThread* jt = (JavaThread *)this; ++ ++ // If we have a last_Java_frame, then we should use it even if ++ // isInJava == true. It should be more reliable than ucontext info. ++ if (jt->has_last_Java_frame() && jt->frame_anchor()->walkable()) { ++ *fr_addr = jt->pd_last_frame(); ++ return true; ++ } ++ ++ // At this point, we don't have a last_Java_frame, so ++ // we try to glean some information out of the ucontext ++ // if we were running Java code when SIGPROF came in. ++ if (isInJava) { ++ ucontext_t* uc = (ucontext_t*) ucontext; ++ ++ intptr_t* ret_fp; ++ intptr_t* ret_sp; ++ ExtendedPC addr = os::Linux::fetch_frame_from_ucontext(this, uc, ++ &ret_sp, &ret_fp); ++ if (addr.pc() == NULL || ret_sp == NULL ) { ++ // ucontext wasn't useful ++ return false; ++ } ++ ++ frame ret_frame(ret_sp, ret_fp, addr.pc()); ++ if (!ret_frame.safe_for_sender(jt)) { ++#ifdef COMPILER2 ++ // C2 uses ebp as a general register see if NULL fp helps ++ frame ret_frame2(ret_sp, NULL, addr.pc()); ++ if (!ret_frame2.safe_for_sender(jt)) { ++ // nothing else to try if the frame isn't good ++ return false; ++ } ++ ret_frame = ret_frame2; ++#else ++ // nothing else to try if the frame isn't good ++ return false; ++#endif /* COMPILER2 */ ++ } ++ *fr_addr = ret_frame; ++ return true; ++ } ++ ++ // nothing else to try ++ return false; ++} ++ ++void JavaThread::cache_global_variables() { } ++ +diff --git a/hotspot/src/os_cpu/linux_sw64/vm/thread_linux_sw64.hpp b/hotspot/src/os_cpu/linux_sw64/vm/thread_linux_sw64.hpp +new file mode 100755 +index 0000000000..25ab3ef9fc +--- /dev/null ++++ b/hotspot/src/os_cpu/linux_sw64/vm/thread_linux_sw64.hpp +@@ -0,0 +1,70 @@ ++/* ++ * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++ private: ++ void pd_initialize(); ++ ++ frame pd_last_frame() { ++ assert(has_last_Java_frame(), "must have last_Java_sp() when suspended"); ++ ++ assert(_anchor.last_Java_pc() != NULL, "Ack no pc!"); ++ return frame(_anchor.last_Java_sp(), _anchor.last_Java_fp(), _anchor.last_Java_pc()); ++ } ++ ++ public: ++ // Mutators are highly dangerous.... ++ intptr_t* last_Java_fp() { return _anchor.last_Java_fp(); } ++ void set_last_Java_fp(intptr_t* fp) { _anchor.set_last_Java_fp(fp); } ++ ++ void set_base_of_stack_pointer(intptr_t* base_sp) { ++ } ++ ++ static ByteSize last_Java_fp_offset() { ++ return byte_offset_of(JavaThread, _anchor) + JavaFrameAnchor::last_Java_fp_offset(); ++ } ++ ++ intptr_t* base_of_stack_pointer() { ++ return NULL; ++ } ++ void record_base_of_stack_pointer() { ++ } ++ ++ bool pd_get_top_frame_for_signal_handler(frame* fr_addr, void* ucontext, ++ bool isInJava); ++ ++ bool pd_get_top_frame_for_profiling(frame* fr_addr, void* ucontext, bool isInJava); ++private: ++ bool pd_get_top_frame(frame* fr_addr, void* ucontext, bool isInJava); ++public: ++ ++ // These routines are only used on cpu architectures that ++ // have separate register stacks (Itanium). ++ static bool register_stack_overflow() { return false; } ++ static void enable_register_stack_guard() {} ++ static void disable_register_stack_guard() {} ++ ++ // For convenient implementation of NativeGeneralJump::replace_mt_safe() ++ volatile address _handle_wrong_method_stub; ++ static ByteSize handle_wrong_method_stub_offset() { return byte_offset_of(JavaThread, _handle_wrong_method_stub); } ++ void set_handle_wrong_method_stub(address stub) { _handle_wrong_method_stub = stub; } +diff --git a/hotspot/src/os_cpu/linux_sw64/vm/vmStructs_linux_sw64.hpp b/hotspot/src/os_cpu/linux_sw64/vm/vmStructs_linux_sw64.hpp +new file mode 100755 +index 0000000000..8dff68531a +--- /dev/null ++++ b/hotspot/src/os_cpu/linux_sw64/vm/vmStructs_linux_sw64.hpp +@@ -0,0 +1,54 @@ ++/* ++ * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef OS_CPU_LINUX_SW64_VM_VMSTRUCTS_LINUX_SW64_HPP ++#define OS_CPU_LINUX_SW64_VM_VMSTRUCTS_LINUX_SW64_HPP ++ ++// These are the OS and CPU-specific fields, types and integer ++// constants required by the Serviceability Agent. This file is ++// referenced by vmStructs.cpp. ++ ++#define VM_STRUCTS_OS_CPU(nonstatic_field, static_field, unchecked_nonstatic_field, volatile_nonstatic_field, nonproduct_nonstatic_field, c2_nonstatic_field, unchecked_c1_static_field, unchecked_c2_static_field) \ ++ \ ++ /******************************/ \ ++ /* Threads (NOTE: incomplete) */ \ ++ /******************************/ \ ++ nonstatic_field(OSThread, _thread_id, pid_t) \ ++ nonstatic_field(OSThread, _pthread_id, pthread_t) ++ ++ ++#define VM_TYPES_OS_CPU(declare_type, declare_toplevel_type, declare_oop_type, declare_integer_type, declare_unsigned_integer_type, declare_c1_toplevel_type, declare_c2_type, declare_c2_toplevel_type) \ ++ \ ++ /**********************/ \ ++ /* Posix Thread IDs */ \ ++ /**********************/ \ ++ \ ++ declare_integer_type(pid_t) \ ++ declare_unsigned_integer_type(pthread_t) ++ ++#define VM_INT_CONSTANTS_OS_CPU(declare_constant, declare_preprocessor_constant, declare_c1_constant, declare_c2_constant, declare_c2_preprocessor_constant) ++ ++#define VM_LONG_CONSTANTS_OS_CPU(declare_constant, declare_preprocessor_constant, declare_c1_constant, declare_c2_constant, declare_c2_preprocessor_constant) ++ ++#endif // OS_CPU_LINUX_SW64_VM_VMSTRUCTS_LINUX_SW64_HPP +diff --git a/hotspot/src/os_cpu/linux_sw64/vm/vm_version_linux_sw64.cpp b/hotspot/src/os_cpu/linux_sw64/vm/vm_version_linux_sw64.cpp +new file mode 100755 +index 0000000000..e830ad317b +--- /dev/null ++++ b/hotspot/src/os_cpu/linux_sw64/vm/vm_version_linux_sw64.cpp +@@ -0,0 +1,119 @@ ++/* ++ * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#include "precompiled.hpp" ++#include "runtime/os.hpp" ++#include "vm_version_sw64.hpp" ++#include "string.h" ++ ++#define CPU_FAMILY_AMOUNT 9 ++ ++const char cpuinfo[CPU_FAMILY_AMOUNT][30] = { ++ "not-sw", // 0 ++ "sw410", // 1 ++ "sw4a", // 2 ++ "sw6a", // 3 ++ "sw6b", // 4 ++ "sw1621", // 5 ++ "sw421", // 6 ++ "sw3231", // 7 ++ "h8000", // 8 WX-H8000 for 8A ++}; ++ ++void read_cpu_info(const char *path, char *result) { ++ FILE *ptr; ++ char buf[1024]; ++ int i = 0; ++ if((ptr=fopen(path, "r")) != NULL) { ++ while(fgets(buf, 1024, ptr)!=NULL) { ++ strcat(result,buf); ++ i++; ++ if (i == 10) break; ++ } ++ fclose(ptr); ++ } else { ++ tty->print_cr("fopen %s error\n", path); ++ } ++} ++ ++void strlwr(char *str){ ++ for (; *str!='\0'; str++) ++ *str = tolower(*str); ++} ++ ++int VM_Version::platform_features(int features) { ++ char res[10240]; ++ int i; ++ features = spt_16k_page_m; //default support ++ memset(res, '\0', 10240 * sizeof(char)); ++ read_cpu_info("/proc/cpuinfo", res); ++ // res is converted to lower case ++ strlwr(res); ++ for (i = 1; i < CPU_FAMILY_AMOUNT; i++) { ++ if (strstr(res, cpuinfo[i])) { ++ break; ++ } ++ } ++ //add some other support when detected on shenwei ++ if (i != CPU_FAMILY_AMOUNT) { ++ features |= with_sw_support_m; ++ } ++ switch (i % CPU_FAMILY_AMOUNT) { ++ case 1 : ++ features |= sw2f_m; ++ //tty->print_cr("sw2f platform"); ++ break; ++ case 2 : ++ features |= sw4a_m; ++ //tty->print_cr("sw4a platform"); ++ break; ++ case 3 : ++ features |= sw6a_m; ++ //tty->print_cr("sw6a platform"); ++ break; ++ case 4 : ++ features |= sw6b_m; ++ //tty->print_cr("sw6b platform"); ++ break; ++ case 5 : ++ features |= sw1621_m; ++ //tty->print_cr("sw6b platform"); ++ break; ++ case 6 : ++ features |= sw4a_m; ++ //tty->print_cr("sw6b platform"); ++ break; ++ case 7 : ++ features |= sw3231_m; ++ break; ++ case 8 : ++ features |= wx_h8000_m; ++ break; ++ default: ++ //tty->print_cr("cpu not support, the cpuinfo is: %s", res); ++ //ShouldNotReachHere(); ++ ; ++ } ++ return features; ++} +diff --git a/hotspot/src/share/tools/hsdis/Makefile b/hotspot/src/share/tools/hsdis/Makefile +index 0d1b608944..ea09ae10f6 100644 +--- a/hotspot/src/share/tools/hsdis/Makefile ++++ b/hotspot/src/share/tools/hsdis/Makefile +@@ -93,6 +93,9 @@ else #linux + CPU = $(shell uname -m) + ARCH1=$(CPU:x86_64=amd64) + ARCH=$(ARCH1:i686=i386) ++# Modify "sw_64" ARCH to "sw64" by SCW20170314 ++ARCH=$(ARCH1:sw_64=sw64) ++ + ifdef LP64 + CFLAGS/sparcv9 += -m64 + CFLAGS/amd64 += -m64 +@@ -176,6 +179,8 @@ endif # LIBARCH64/$(ARCH) + endif # LP64 + + JDKARCH=$(LIBARCH:i386=i586) ++# Modify "sw_64" LIBARCH to "sw64" for "make clean" by SCW20170314 ++JDKARCH=$(LIBARCH:sw_64=sw64) + + ifeq ($(BINUTILS),) + # Pop all the way out of the workspace to look for binutils. +diff --git a/hotspot/src/share/tools/hsdis/hsdis.c b/hotspot/src/share/tools/hsdis/hsdis.c +index 4fb4964870..a7d8de1dc8 100644 +--- a/hotspot/src/share/tools/hsdis/hsdis.c ++++ b/hotspot/src/share/tools/hsdis/hsdis.c +@@ -484,6 +484,9 @@ static const char* native_arch_name() { + #ifdef LIBARCH_amd64 + res = "i386:x86-64"; + #endif ++#if defined(LIBARCH_sw) || defined(LIBARCH_sw64) //SCW201170314 ++ res = "sw_64:sw2"; //SCW20170314, to support sw_64 special instruction. ++#endif + #ifdef LIBARCH_sparc + res = "sparc:v8plusb"; + #endif +@@ -495,6 +498,9 @@ static const char* native_arch_name() { + #endif + #ifdef LIBARCH_aarch64 + res = "aarch64"; ++#endif ++#ifdef LIBARCH_sw64 ++ res = "sw64"; + #endif + if (res == NULL) + res = "architecture not set in Makefile!"; +diff --git a/hotspot/src/share/tools/hsdis/mk b/hotspot/src/share/tools/hsdis/mk +new file mode 100755 +index 0000000000..44e6a0c315 +--- /dev/null ++++ b/hotspot/src/share/tools/hsdis/mk +@@ -0,0 +1,10 @@ ++#!/bin/bash ++ ++UNAME=`uname -m` ++if [ "$UNAME" == "sw_64" ] ++then ++ make clean ++ make all64 BINUTILS=${HOME}/work/binutils-2.24-4A ++else ++ echo " * Sorry, it need compile in sw server! *" ++fi +diff --git a/hotspot/src/share/vm/adlc/main.cpp b/hotspot/src/share/vm/adlc/main.cpp +index 52044f12d4..d5a4e9b588 100644 +--- a/hotspot/src/share/vm/adlc/main.cpp ++++ b/hotspot/src/share/vm/adlc/main.cpp +@@ -239,6 +239,11 @@ int main(int argc, char *argv[]) + AD.addInclude(AD._CPP_file, "nativeInst_aarch64.hpp"); + AD.addInclude(AD._CPP_file, "vmreg_aarch64.inline.hpp"); + #endif ++#ifdef TARGET_ARCH_sw64 ++ AD.addInclude(AD._CPP_file, "assembler_sw64.inline.hpp"); ++ AD.addInclude(AD._CPP_file, "nativeInst_sw64.hpp"); ++ AD.addInclude(AD._CPP_file, "vmreg_sw64.inline.hpp"); ++#endif + #ifdef TARGET_ARCH_sparc + AD.addInclude(AD._CPP_file, "nativeInst_sparc.hpp"); + AD.addInclude(AD._CPP_file, "vmreg_sparc.inline.hpp"); +diff --git a/hotspot/src/share/vm/asm/assembler.hpp b/hotspot/src/share/vm/asm/assembler.hpp +index f7f1ae1d36..649c9c7e3f 100644 +--- a/hotspot/src/share/vm/asm/assembler.hpp ++++ b/hotspot/src/share/vm/asm/assembler.hpp +@@ -53,6 +53,10 @@ + # include "register_ppc.hpp" + # include "vm_version_ppc.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "register_sw64.hpp" ++# include "vm_version_sw64.hpp" ++#endif + #ifdef TARGET_ARCH_aarch64 + # include "register_aarch64.hpp" + # include "vm_version_aarch64.hpp" +@@ -307,6 +311,9 @@ class AbstractAssembler : public ResourceObj { + static bool is_simm9(int64_t x) { return is_simm(x, 9); } + static bool is_simm10(int64_t x) { return is_simm(x, 10); } + static bool is_simm16(int64_t x) { return is_simm(x, 16); } ++#ifdef SW64 ++ static bool is_simm21(int64_t x) { return is_simm(x, 21); } ++#endif + static bool is_simm32(int64_t x) { return is_simm(x, 32); } + + // Test if x is within unsigned immediate range for width. +@@ -468,6 +475,9 @@ class AbstractAssembler : public ResourceObj { + #ifdef TARGET_ARCH_ppc + # include "assembler_ppc.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "assembler_sw64.hpp" ++#endif + + + #endif // SHARE_VM_ASM_ASSEMBLER_HPP +diff --git a/hotspot/src/share/vm/asm/assembler.inline.hpp b/hotspot/src/share/vm/asm/assembler.inline.hpp +index 1a48cb3171..3bc333f372 100644 +--- a/hotspot/src/share/vm/asm/assembler.inline.hpp ++++ b/hotspot/src/share/vm/asm/assembler.inline.hpp +@@ -42,6 +42,9 @@ + #ifdef TARGET_ARCH_ppc + # include "assembler_ppc.inline.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "assembler_sw64.inline.hpp" ++#endif + #ifdef TARGET_ARCH_aarch64 + # include "assembler_aarch64.inline.hpp" + #endif +diff --git a/hotspot/src/share/vm/asm/codeBuffer.hpp b/hotspot/src/share/vm/asm/codeBuffer.hpp +index 02b619ad77..23ef7f3c92 100644 +--- a/hotspot/src/share/vm/asm/codeBuffer.hpp ++++ b/hotspot/src/share/vm/asm/codeBuffer.hpp +@@ -635,6 +635,9 @@ class CodeBuffer: public StackObj { + #ifdef TARGET_ARCH_ppc + # include "codeBuffer_ppc.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "codeBuffer_sw64.hpp" ++#endif + + }; + +diff --git a/hotspot/src/share/vm/asm/macroAssembler.hpp b/hotspot/src/share/vm/asm/macroAssembler.hpp +index 1482eb630b..48144b569a 100644 +--- a/hotspot/src/share/vm/asm/macroAssembler.hpp ++++ b/hotspot/src/share/vm/asm/macroAssembler.hpp +@@ -42,6 +42,9 @@ + #ifdef TARGET_ARCH_ppc + # include "macroAssembler_ppc.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "macroAssembler_sw64.hpp" ++#endif + #ifdef TARGET_ARCH_aarch64 + # include "macroAssembler_aarch64.hpp" + #endif +diff --git a/hotspot/src/share/vm/asm/macroAssembler.inline.hpp b/hotspot/src/share/vm/asm/macroAssembler.inline.hpp +index db3daa52e9..f83d46661e 100644 +--- a/hotspot/src/share/vm/asm/macroAssembler.inline.hpp ++++ b/hotspot/src/share/vm/asm/macroAssembler.inline.hpp +@@ -42,6 +42,9 @@ + #ifdef TARGET_ARCH_ppc + # include "macroAssembler_ppc.inline.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "macroAssembler_sw64.inline.hpp" ++#endif + #ifdef TARGET_ARCH_aarch64 + # include "macroAssembler_aarch64.inline.hpp" + #endif +diff --git a/hotspot/src/share/vm/asm/register.hpp b/hotspot/src/share/vm/asm/register.hpp +index c500890181..09ad198e23 100644 +--- a/hotspot/src/share/vm/asm/register.hpp ++++ b/hotspot/src/share/vm/asm/register.hpp +@@ -108,6 +108,9 @@ const type name = ((type)name##_##type##EnumValue) + #ifdef TARGET_ARCH_ppc + # include "register_ppc.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "register_sw64.hpp" ++#endif + #ifdef TARGET_ARCH_aarch64 + # include "register_aarch64.hpp" + #endif +diff --git a/hotspot/src/share/vm/classfile/bytecodeAssembler.cpp b/hotspot/src/share/vm/classfile/bytecodeAssembler.cpp +index f067419ffc..8918048447 100644 +--- a/hotspot/src/share/vm/classfile/bytecodeAssembler.cpp ++++ b/hotspot/src/share/vm/classfile/bytecodeAssembler.cpp +@@ -32,6 +32,9 @@ + #ifdef TARGET_ARCH_x86 + # include "bytes_x86.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "bytes_sw64.hpp" ++#endif + #ifdef TARGET_ARCH_sparc + # include "bytes_sparc.hpp" + #endif +diff --git a/hotspot/src/share/vm/classfile/classFileStream.hpp b/hotspot/src/share/vm/classfile/classFileStream.hpp +index 9632c8c8c2..48af2b9ca7 100644 +--- a/hotspot/src/share/vm/classfile/classFileStream.hpp ++++ b/hotspot/src/share/vm/classfile/classFileStream.hpp +@@ -32,6 +32,9 @@ + #ifdef TARGET_ARCH_aarch64 + # include "bytes_aarch64.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "bytes_sw64.hpp" ++#endif + #ifdef TARGET_ARCH_sparc + # include "bytes_sparc.hpp" + #endif +diff --git a/hotspot/src/share/vm/classfile/stackMapTable.hpp b/hotspot/src/share/vm/classfile/stackMapTable.hpp +index a36a7ba3cf..8cea293673 100644 +--- a/hotspot/src/share/vm/classfile/stackMapTable.hpp ++++ b/hotspot/src/share/vm/classfile/stackMapTable.hpp +@@ -34,6 +34,9 @@ + #ifdef TARGET_ARCH_x86 + # include "bytes_x86.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "bytes_sw64.hpp" ++#endif + #ifdef TARGET_ARCH_aarch64 + # include "bytes_aarch64.hpp" + #endif +diff --git a/hotspot/src/share/vm/classfile/verifier.cpp b/hotspot/src/share/vm/classfile/verifier.cpp +index 2dddd1fded..4d86238135 100644 +--- a/hotspot/src/share/vm/classfile/verifier.cpp ++++ b/hotspot/src/share/vm/classfile/verifier.cpp +@@ -48,6 +48,9 @@ + #ifdef TARGET_ARCH_x86 + # include "bytes_x86.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "bytes_sw64.hpp" ++#endif + #ifdef TARGET_ARCH_aarch64 + # include "bytes_aarch64.hpp" + #endif +diff --git a/hotspot/src/share/vm/code/codeBlob.cpp b/hotspot/src/share/vm/code/codeBlob.cpp +index aff2aaf0ca..5985865654 100644 +--- a/hotspot/src/share/vm/code/codeBlob.cpp ++++ b/hotspot/src/share/vm/code/codeBlob.cpp +@@ -57,6 +57,9 @@ + #ifdef TARGET_ARCH_ppc + # include "nativeInst_ppc.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "nativeInst_sw64.hpp" ++#endif + #ifdef COMPILER1 + #include "c1/c1_Runtime1.hpp" + #endif +diff --git a/hotspot/src/share/vm/code/compiledIC.hpp b/hotspot/src/share/vm/code/compiledIC.hpp +index f910f11886..24d27b43a7 100644 +--- a/hotspot/src/share/vm/code/compiledIC.hpp ++++ b/hotspot/src/share/vm/code/compiledIC.hpp +@@ -45,6 +45,9 @@ + #ifdef TARGET_ARCH_ppc + # include "nativeInst_ppc.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "nativeInst_sw64.hpp" ++#endif + + //----------------------------------------------------------------------------- + // The CompiledIC represents a compiled inline cache. +diff --git a/hotspot/src/share/vm/code/nmethod.cpp b/hotspot/src/share/vm/code/nmethod.cpp +index 01e8780224..f52de96080 100644 +--- a/hotspot/src/share/vm/code/nmethod.cpp ++++ b/hotspot/src/share/vm/code/nmethod.cpp +@@ -1175,7 +1175,11 @@ void nmethod::cleanup_inline_caches() { + // not-entrant methods. + address low_boundary = verified_entry_point(); + if (!is_in_use()) { +- low_boundary += NativeJump::instruction_size; ++#if defined(SW64) && !defined(ZERO) ++ low_boundary += NativeGeneralJump::instruction_size; ++#else ++ low_boundary += NativeJump::instruction_size; ++#endif + // %%% Note: On SPARC we patch only a 4-byte trap, not a full NativeJump. + // This means that the low_boundary is going to be a little too high. + // This shouldn't matter, since oops of non-entrant methods are never used. +@@ -1223,7 +1227,11 @@ void nmethod::verify_clean_inline_caches() { + // not-entrant methods. + address low_boundary = verified_entry_point(); + if (!is_in_use()) { ++#if defined(SW64) && !defined(ZERO) ++ low_boundary += NativeGeneralJump::instruction_size; ++#else + low_boundary += NativeJump::instruction_size; ++#endif + // %%% Note: On SPARC we patch only a 4-byte trap, not a full NativeJump. + // This means that the low_boundary is going to be a little too high. + // This shouldn't matter, since oops of non-entrant methods are never used. +@@ -1467,8 +1475,13 @@ bool nmethod::make_not_entrant_or_zombie(unsigned int state) { + // The caller can be calling the method statically or through an inline + // cache call. + if (!is_osr_method() && !is_not_entrant()) { +- NativeJump::patch_verified_entry(entry_point(), verified_entry_point(), +- SharedRuntime::get_handle_wrong_method_stub()); ++#if defined(SW64) && !defined(ZERO) ++ NativeGeneralJump::patch_verified_entry(entry_point(), verified_entry_point(), ++ SharedRuntime::get_handle_wrong_method_stub()); ++#else ++ NativeJump::patch_verified_entry(entry_point(), verified_entry_point(), ++ SharedRuntime::get_handle_wrong_method_stub()); ++#endif + } + + if (is_in_use()) { +@@ -1797,7 +1810,11 @@ void nmethod::do_unloading(BoolObjectClosure* is_alive, bool unloading_occurred) + // not-entrant methods. + address low_boundary = verified_entry_point(); + if (is_not_entrant()) { +- low_boundary += NativeJump::instruction_size; ++#if defined(SW64) && !defined(ZERO) ++ low_boundary += NativeGeneralJump::instruction_size; ++#else ++ low_boundary += NativeJump::instruction_size; ++#endif + // %%% Note: On SPARC we patch only a 4-byte trap, not a full NativeJump. + // (See comment above.) + } +@@ -1953,7 +1970,11 @@ bool nmethod::do_unloading_parallel(BoolObjectClosure* is_alive, bool unloading_ + // not-entrant methods. + address low_boundary = verified_entry_point(); + if (is_not_entrant()) { ++#if defined(SW64) && !defined(ZERO) ++ low_boundary += NativeGeneralJump::instruction_size; ++#else + low_boundary += NativeJump::instruction_size; ++#endif + // %%% Note: On SPARC we patch only a 4-byte trap, not a full NativeJump. + // (See comment above.) + } +@@ -2056,7 +2077,11 @@ void nmethod::do_unloading_parallel_postponed(BoolObjectClosure* is_alive, bool + // not-entrant methods. + address low_boundary = verified_entry_point(); + if (is_not_entrant()) { ++#if defined(SW64) && !defined(ZERO) ++ low_boundary += NativeGeneralJump::instruction_size; ++#else + low_boundary += NativeJump::instruction_size; ++#endif + // %%% Note: On SPARC we patch only a 4-byte trap, not a full NativeJump. + // (See comment above.) + } +@@ -2157,7 +2182,11 @@ void nmethod::verify_metadata_loaders(address low_boundary, BoolObjectClosure* i + void nmethod::metadata_do(void f(Metadata*)) { + address low_boundary = verified_entry_point(); + if (is_not_entrant()) { +- low_boundary += NativeJump::instruction_size; ++#if defined(SW64) && !defined(ZERO) ++ low_boundary += NativeGeneralJump::instruction_size; ++#else ++ low_boundary += NativeJump::instruction_size; ++#endif + // %%% Note: On SPARC we patch only a 4-byte trap, not a full NativeJump. + // (See comment above.) + } +@@ -2217,7 +2246,11 @@ void nmethod::oops_do(OopClosure* f, bool allow_zombie) { + // not-entrant methods. + address low_boundary = verified_entry_point(); + if (is_not_entrant()) { +- low_boundary += NativeJump::instruction_size; ++#if defined(SW64) && !defined(ZERO) ++ low_boundary += NativeGeneralJump::instruction_size; ++#else ++ low_boundary += NativeJump::instruction_size; ++#endif + // %%% Note: On SPARC we patch only a 4-byte trap, not a full NativeJump. + // (See comment above.) + } +@@ -2724,7 +2757,11 @@ void nmethod::verify() { + return; + + // Make sure all the entry points are correctly aligned for patching. +- NativeJump::check_verified_entry_alignment(entry_point(), verified_entry_point()); ++#if defined(SW64) && !defined(ZERO) ++ NativeGeneralJump::check_verified_entry_alignment(entry_point(), verified_entry_point()); ++#else ++ NativeJump::check_verified_entry_alignment(entry_point(), verified_entry_point()); ++#endif + + // assert(method()->is_oop(), "must be valid"); + +diff --git a/hotspot/src/share/vm/code/relocInfo.hpp b/hotspot/src/share/vm/code/relocInfo.hpp +index ad55a2fd93..dbddc4fc29 100644 +--- a/hotspot/src/share/vm/code/relocInfo.hpp ++++ b/hotspot/src/share/vm/code/relocInfo.hpp +@@ -432,6 +432,9 @@ class relocInfo VALUE_OBJ_CLASS_SPEC { + #endif + #ifdef TARGET_ARCH_ppc + # include "relocInfo_ppc.hpp" ++#endif ++#ifdef TARGET_ARCH_sw64 ++# include "relocInfo_sw64.hpp" + #endif + + +diff --git a/hotspot/src/share/vm/code/vmreg.hpp b/hotspot/src/share/vm/code/vmreg.hpp +index 07b595b60a..16a5f74ab4 100644 +--- a/hotspot/src/share/vm/code/vmreg.hpp ++++ b/hotspot/src/share/vm/code/vmreg.hpp +@@ -47,6 +47,9 @@ + #elif defined TARGET_ARCH_MODEL_ppc_64 + # include "adfiles/adGlobals_ppc_64.hpp" + #endif ++#if defined TARGET_ARCH_MODEL_sw64 ++# include "adfiles/adGlobals_sw64.hpp" ++#endif + #endif + + //------------------------------VMReg------------------------------------------ +@@ -158,6 +161,9 @@ public: + #ifdef TARGET_ARCH_x86 + # include "vmreg_x86.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "vmreg_sw64.hpp" ++#endif + #ifdef TARGET_ARCH_aarch64 + # include "vmreg_aarch64.hpp" + #endif +diff --git a/hotspot/src/share/vm/compiler/disassembler.cpp b/hotspot/src/share/vm/compiler/disassembler.cpp +index dfdd5f77e7..f15acbd098 100644 +--- a/hotspot/src/share/vm/compiler/disassembler.cpp ++++ b/hotspot/src/share/vm/compiler/disassembler.cpp +@@ -50,6 +50,9 @@ + #ifdef TARGET_ARCH_ppc + # include "depChecker_ppc.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "depChecker_sw64.hpp" ++#endif + #ifdef SHARK + #include "shark/sharkEntry.hpp" + #endif +diff --git a/hotspot/src/share/vm/compiler/disassembler.hpp b/hotspot/src/share/vm/compiler/disassembler.hpp +index 168851cc26..0a99b6cd75 100644 +--- a/hotspot/src/share/vm/compiler/disassembler.hpp ++++ b/hotspot/src/share/vm/compiler/disassembler.hpp +@@ -95,6 +95,9 @@ class Disassembler { + #endif + #ifdef TARGET_ARCH_ppc + # include "disassembler_ppc.hpp" ++#endif ++#ifdef TARGET_ARCH_sw64 ++# include "disassembler_sw64.hpp" + #endif + + +diff --git a/hotspot/src/share/vm/compiler/disassemblerEnv.hpp b/hotspot/src/share/vm/compiler/disassemblerEnv.hpp +new file mode 100644 +index 0000000000..8728927bc3 +--- /dev/null ++++ b/hotspot/src/share/vm/compiler/disassemblerEnv.hpp +@@ -0,0 +1,44 @@ ++/* ++ * Copyright (c) 2008, 2013, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2015, 2016, Wuxi Institute of Advanced Technology. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#if 1 // Added for debugging information by ZHJ20180724 ++ ++#ifdef USE_PRAGMA_IDENT_HDR ++#pragma ident "@(#)disassemblerEnv.hpp 1.14 05/11/18 15:21:38 JVM" ++#endif ++ ++// Call-back interface for external disassembler ++class DisassemblerEnv { ++ public: ++ // printing ++ virtual void print_label(intptr_t value) = 0; ++ virtual void print_raw(const char* str) = 0; ++ virtual void print(const char* format, ...) = 0; ++ // helpers ++ virtual char* string_for_offset(intptr_t value) = 0; ++ virtual char* string_for_constant(unsigned char* pc, intptr_t value, int is_decimal) = 0; ++}; ++ ++#endif +diff --git a/hotspot/src/share/vm/gc_implementation/parallelScavenge/psScavenge.inline.hpp b/hotspot/src/share/vm/gc_implementation/parallelScavenge/psScavenge.inline.hpp +index 1a722a7ca7..be7c93a1d2 100644 +--- a/hotspot/src/share/vm/gc_implementation/parallelScavenge/psScavenge.inline.hpp ++++ b/hotspot/src/share/vm/gc_implementation/parallelScavenge/psScavenge.inline.hpp +@@ -71,6 +71,9 @@ inline void PSScavenge::copy_and_push_safe_barrier(PSPromotionManager* pm, + assert(should_scavenge(p, true), "revisiting object?"); + + oop o = oopDesc::load_decode_heap_oop_not_null(p); ++#if defined(SW64) ++ if (oopDesc::is_null(o)) return; ++#endif + oop new_obj = o->is_forwarded() + ? o->forwardee() + : pm->copy_to_survivor_space(o); +diff --git a/hotspot/src/share/vm/interpreter/abstractInterpreter.hpp b/hotspot/src/share/vm/interpreter/abstractInterpreter.hpp +index e14c50bf01..6f6eccb7b7 100644 +--- a/hotspot/src/share/vm/interpreter/abstractInterpreter.hpp ++++ b/hotspot/src/share/vm/interpreter/abstractInterpreter.hpp +@@ -42,6 +42,8 @@ + # include "interp_masm_zero.hpp" + #elif defined TARGET_ARCH_MODEL_ppc_64 + # include "interp_masm_ppc_64.hpp" ++#elif defined TARGET_ARCH_MODEL_sw64 ++# include "interp_masm_sw64.hpp" + #endif + + // This file contains the platform-independent parts +diff --git a/hotspot/src/share/vm/interpreter/bytecode.hpp b/hotspot/src/share/vm/interpreter/bytecode.hpp +index 7e55fd009a..77d975889b 100644 +--- a/hotspot/src/share/vm/interpreter/bytecode.hpp ++++ b/hotspot/src/share/vm/interpreter/bytecode.hpp +@@ -31,6 +31,9 @@ + #ifdef TARGET_ARCH_x86 + # include "bytes_x86.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "bytes_sw64.hpp" ++#endif + #ifdef TARGET_ARCH_aarch64 + # include "bytes_aarch64.hpp" + #endif +diff --git a/hotspot/src/share/vm/interpreter/bytecodeInterpreter.hpp b/hotspot/src/share/vm/interpreter/bytecodeInterpreter.hpp +index 28843715c7..9b90652e74 100644 +--- a/hotspot/src/share/vm/interpreter/bytecodeInterpreter.hpp ++++ b/hotspot/src/share/vm/interpreter/bytecodeInterpreter.hpp +@@ -35,6 +35,9 @@ + #ifdef TARGET_ARCH_x86 + # include "bytes_x86.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "bytes_sw64.hpp" ++#endif + #ifdef TARGET_ARCH_aarch64 + # include "bytes_aarch64.hpp" + #endif +@@ -595,6 +598,9 @@ void print(); + #ifdef TARGET_ARCH_aarch64 + # include "bytecodeInterpreter_aarch64.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "bytecodeInterpreter_sw64.hpp" ++#endif + #ifdef TARGET_ARCH_sparc + # include "bytecodeInterpreter_sparc.hpp" + #endif +diff --git a/hotspot/src/share/vm/interpreter/bytecodeInterpreter.inline.hpp b/hotspot/src/share/vm/interpreter/bytecodeInterpreter.inline.hpp +index f5db0b4d9d..86fa8c75a3 100644 +--- a/hotspot/src/share/vm/interpreter/bytecodeInterpreter.inline.hpp ++++ b/hotspot/src/share/vm/interpreter/bytecodeInterpreter.inline.hpp +@@ -46,6 +46,9 @@ + #ifdef TARGET_ARCH_x86 + # include "bytecodeInterpreter_x86.inline.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "bytecodeInterpreter_sw64.inline.hpp" ++#endif + #ifdef TARGET_ARCH_aarch64 + # include "bytecodeInterpreter_aarch64.inline.hpp" + #endif +diff --git a/hotspot/src/share/vm/interpreter/bytecodeStream.hpp b/hotspot/src/share/vm/interpreter/bytecodeStream.hpp +index b814b88d5d..c62b91b1ff 100644 +--- a/hotspot/src/share/vm/interpreter/bytecodeStream.hpp ++++ b/hotspot/src/share/vm/interpreter/bytecodeStream.hpp +@@ -32,6 +32,9 @@ + #ifdef TARGET_ARCH_x86 + # include "bytes_x86.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "bytes_sw64.hpp" ++#endif + #ifdef TARGET_ARCH_aarch64 + # include "bytes_aarch64.hpp" + #endif +diff --git a/hotspot/src/share/vm/interpreter/bytecodes.cpp b/hotspot/src/share/vm/interpreter/bytecodes.cpp +index ce5632ea19..24ac2c7425 100644 +--- a/hotspot/src/share/vm/interpreter/bytecodes.cpp ++++ b/hotspot/src/share/vm/interpreter/bytecodes.cpp +@@ -29,6 +29,9 @@ + #ifdef TARGET_ARCH_x86 + # include "bytes_x86.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "bytes_sw64.hpp" ++#endif + #ifdef TARGET_ARCH_aarch64 + # include "bytes_aarch64.hpp" + #endif +diff --git a/hotspot/src/share/vm/interpreter/bytecodes.hpp b/hotspot/src/share/vm/interpreter/bytecodes.hpp +index 3105fa28c3..688dfa9774 100644 +--- a/hotspot/src/share/vm/interpreter/bytecodes.hpp ++++ b/hotspot/src/share/vm/interpreter/bytecodes.hpp +@@ -292,6 +292,9 @@ class Bytecodes: AllStatic { + #ifdef TARGET_ARCH_x86 + # include "bytecodes_x86.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "bytecodes_sw64.hpp" ++#endif + #ifdef TARGET_ARCH_aarch64 + # include "bytecodes_aarch64.hpp" + #endif +diff --git a/hotspot/src/share/vm/interpreter/cppInterpreter.hpp b/hotspot/src/share/vm/interpreter/cppInterpreter.hpp +index 6a6447503c..49fd11d296 100644 +--- a/hotspot/src/share/vm/interpreter/cppInterpreter.hpp ++++ b/hotspot/src/share/vm/interpreter/cppInterpreter.hpp +@@ -84,6 +84,9 @@ class CppInterpreter: public AbstractInterpreter { + #ifdef TARGET_ARCH_x86 + # include "cppInterpreter_x86.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "cppInterpreter_sw64.hpp" ++#endif + #ifdef TARGET_ARCH_aarch64 + # include "cppInterpreter_aarch64.hpp" + #endif +diff --git a/hotspot/src/share/vm/interpreter/cppInterpreterGenerator.hpp b/hotspot/src/share/vm/interpreter/cppInterpreterGenerator.hpp +index 6a08a3f43f..d3aa9c638f 100644 +--- a/hotspot/src/share/vm/interpreter/cppInterpreterGenerator.hpp ++++ b/hotspot/src/share/vm/interpreter/cppInterpreterGenerator.hpp +@@ -50,6 +50,9 @@ class CppInterpreterGenerator: public AbstractInterpreterGenerator { + #ifdef TARGET_ARCH_x86 + # include "cppInterpreterGenerator_x86.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "cppInterpreterGenerator_sw64.hpp" ++#endif + #ifdef TARGET_ARCH_aarch64 + # include "cppInterpreterGenerator_aarch64.hpp" + #endif +diff --git a/hotspot/src/share/vm/interpreter/interpreter.hpp b/hotspot/src/share/vm/interpreter/interpreter.hpp +index ebfb68d36b..d876aac43b 100644 +--- a/hotspot/src/share/vm/interpreter/interpreter.hpp ++++ b/hotspot/src/share/vm/interpreter/interpreter.hpp +@@ -148,6 +148,9 @@ class Interpreter: public CC_INTERP_ONLY(CppInterpreter) NOT_CC_INTERP(TemplateI + #ifdef TARGET_ARCH_x86 + # include "interpreter_x86.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "interpreter_sw64.hpp" ++#endif + #ifdef TARGET_ARCH_aarch64 + # include "interpreter_aarch64.hpp" + #endif +diff --git a/hotspot/src/share/vm/interpreter/interpreterGenerator.hpp b/hotspot/src/share/vm/interpreter/interpreterGenerator.hpp +index 1dc7cb2983..8633fd4dec 100644 +--- a/hotspot/src/share/vm/interpreter/interpreterGenerator.hpp ++++ b/hotspot/src/share/vm/interpreter/interpreterGenerator.hpp +@@ -44,6 +44,9 @@ InterpreterGenerator(StubQueue* _code); + #ifdef TARGET_ARCH_x86 + # include "interpreterGenerator_x86.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "interpreterGenerator_sw64.hpp" ++#endif + #ifdef TARGET_ARCH_aarch64 + # include "interpreterGenerator_aarch64.hpp" + #endif +diff --git a/hotspot/src/share/vm/interpreter/interpreterRuntime.cpp b/hotspot/src/share/vm/interpreter/interpreterRuntime.cpp +index 425ad7f463..58be73537e 100644 +--- a/hotspot/src/share/vm/interpreter/interpreterRuntime.cpp ++++ b/hotspot/src/share/vm/interpreter/interpreterRuntime.cpp +@@ -60,6 +60,9 @@ + #ifdef TARGET_ARCH_x86 + # include "vm_version_x86.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "vm_version_sw64.hpp" ++#endif + #ifdef TARGET_ARCH_aarch64 + # include "vm_version_aarch64.hpp" + #endif +@@ -1292,7 +1295,7 @@ IRT_ENTRY(void, InterpreterRuntime::prepare_native_call(JavaThread* thread, Meth + // preparing the same method will be sure to see non-null entry & mirror. + IRT_END + +-#if defined(IA32) || defined(AMD64) || defined(ARM) || defined(AARCH64) ++#if defined(IA32) || defined(AMD64) || defined(ARM) || defined(AARCH64) || defined(SW64) + IRT_LEAF(void, InterpreterRuntime::popframe_move_outgoing_args(JavaThread* thread, void* src_address, void* dest_address)) + if (src_address == dest_address) { + return; +diff --git a/hotspot/src/share/vm/interpreter/interpreterRuntime.hpp b/hotspot/src/share/vm/interpreter/interpreterRuntime.hpp +index 472bf4d94c..70e125f998 100644 +--- a/hotspot/src/share/vm/interpreter/interpreterRuntime.hpp ++++ b/hotspot/src/share/vm/interpreter/interpreterRuntime.hpp +@@ -156,7 +156,7 @@ class InterpreterRuntime: AllStatic { + Method* method, + intptr_t* from, intptr_t* to); + +-#if defined(IA32) || defined(AMD64) || defined(ARM) || defined(AARCH64) ++#if defined(IA32) || defined(AMD64) || defined(ARM) || defined(AARCH64) || defined(SW64) + // Popframe support (only needed on x86, AMD64 and ARM) + static void popframe_move_outgoing_args(JavaThread* thread, void* src_address, void* dest_address); + #endif +@@ -168,6 +168,9 @@ class InterpreterRuntime: AllStatic { + #ifdef TARGET_ARCH_aarch64 + # include "interpreterRT_aarch64.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "interpreterRT_sw64.hpp" ++#endif + #ifdef TARGET_ARCH_sparc + # include "interpreterRT_sparc.hpp" + #endif +diff --git a/hotspot/src/share/vm/interpreter/templateInterpreter.hpp b/hotspot/src/share/vm/interpreter/templateInterpreter.hpp +index 5f76dca8a6..5fb0ba1e85 100644 +--- a/hotspot/src/share/vm/interpreter/templateInterpreter.hpp ++++ b/hotspot/src/share/vm/interpreter/templateInterpreter.hpp +@@ -190,6 +190,9 @@ class TemplateInterpreter: public AbstractInterpreter { + #ifdef TARGET_ARCH_x86 + # include "templateInterpreter_x86.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "templateInterpreter_sw64.hpp" ++#endif + #ifdef TARGET_ARCH_aarch64 + # include "templateInterpreter_aarch64.hpp" + #endif +diff --git a/hotspot/src/share/vm/interpreter/templateInterpreterGenerator.hpp b/hotspot/src/share/vm/interpreter/templateInterpreterGenerator.hpp +index bd94bd02bc..36f2283f55 100644 +--- a/hotspot/src/share/vm/interpreter/templateInterpreterGenerator.hpp ++++ b/hotspot/src/share/vm/interpreter/templateInterpreterGenerator.hpp +@@ -89,6 +89,9 @@ class TemplateInterpreterGenerator: public AbstractInterpreterGenerator { + #ifdef TARGET_ARCH_x86 + # include "templateInterpreterGenerator_x86.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "templateInterpreterGenerator_sw64.hpp" ++#endif + #ifdef TARGET_ARCH_aarch64 + # include "templateInterpreterGenerator_aarch64.hpp" + #endif +diff --git a/hotspot/src/share/vm/interpreter/templateTable.hpp b/hotspot/src/share/vm/interpreter/templateTable.hpp +index 60d243c16a..0381397a5d 100644 +--- a/hotspot/src/share/vm/interpreter/templateTable.hpp ++++ b/hotspot/src/share/vm/interpreter/templateTable.hpp +@@ -40,6 +40,8 @@ + # include "interp_masm_zero.hpp" + #elif defined TARGET_ARCH_MODEL_ppc_64 + # include "interp_masm_ppc_64.hpp" ++#elif defined TARGET_ARCH_MODEL_sw64 ++# include "interp_masm_sw64.hpp" + #endif + + #ifndef CC_INTERP +@@ -367,6 +369,8 @@ class TemplateTable: AllStatic { + # include "templateTable_zero.hpp" + #elif defined TARGET_ARCH_MODEL_ppc_64 + # include "templateTable_ppc_64.hpp" ++#elif defined TARGET_ARCH_MODEL_sw64 ++# include "templateTable_sw64.hpp" + #endif + + }; +diff --git a/hotspot/src/share/vm/jfr/writers/jfrEncoders.hpp b/hotspot/src/share/vm/jfr/writers/jfrEncoders.hpp +index 42a8b719cd..6fdcda7992 100644 +--- a/hotspot/src/share/vm/jfr/writers/jfrEncoders.hpp ++++ b/hotspot/src/share/vm/jfr/writers/jfrEncoders.hpp +@@ -46,6 +46,9 @@ + #ifdef TARGET_ARCH_aarch64 + # include "bytes_aarch64.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "bytes_sw64.hpp" ++#endif + + // + // The Encoding policy prescribes a template +diff --git a/hotspot/src/share/vm/oops/constantPool.hpp b/hotspot/src/share/vm/oops/constantPool.hpp +index 635bf6d1bc..ea3b074859 100644 +--- a/hotspot/src/share/vm/oops/constantPool.hpp ++++ b/hotspot/src/share/vm/oops/constantPool.hpp +@@ -50,6 +50,10 @@ + #ifdef TARGET_ARCH_ppc + # include "bytes_ppc.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "bytes_sw64.hpp" ++#endif ++ + + // A constantPool is an array containing class constants as described in the + // class file. +diff --git a/hotspot/src/share/vm/oops/oop.inline.hpp b/hotspot/src/share/vm/oops/oop.inline.hpp +index beec739d38..04438bb69c 100644 +--- a/hotspot/src/share/vm/oops/oop.inline.hpp ++++ b/hotspot/src/share/vm/oops/oop.inline.hpp +@@ -60,6 +60,9 @@ + #ifdef TARGET_ARCH_ppc + # include "bytes_ppc.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "bytes_sw64.hpp" ++#endif + + // Implementation of all inlined member functions defined in oop.hpp + // We need a separate file to avoid circular references +diff --git a/hotspot/src/share/vm/opto/buildOopMap.cpp b/hotspot/src/share/vm/opto/buildOopMap.cpp +index 91642f1d7d..b1f848eb8c 100644 +--- a/hotspot/src/share/vm/opto/buildOopMap.cpp ++++ b/hotspot/src/share/vm/opto/buildOopMap.cpp +@@ -50,6 +50,9 @@ + #ifdef TARGET_ARCH_ppc + # include "vmreg_ppc.inline.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "vmreg_sw64.inline.hpp" ++#endif + + // The functions in this file builds OopMaps after all scheduling is done. + // +diff --git a/hotspot/src/share/vm/opto/c2_globals.hpp b/hotspot/src/share/vm/opto/c2_globals.hpp +index 82d2efef92..2c497ffa5a 100644 +--- a/hotspot/src/share/vm/opto/c2_globals.hpp ++++ b/hotspot/src/share/vm/opto/c2_globals.hpp +@@ -35,6 +35,9 @@ + #ifdef TARGET_ARCH_sparc + # include "c2_globals_sparc.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "c2_globals_sw64.hpp" ++#endif + #ifdef TARGET_ARCH_arm + # include "c2_globals_arm.hpp" + #endif +diff --git a/hotspot/src/share/vm/opto/c2compiler.cpp b/hotspot/src/share/vm/opto/c2compiler.cpp +index 137f49600d..0b0b7eb202 100644 +--- a/hotspot/src/share/vm/opto/c2compiler.cpp ++++ b/hotspot/src/share/vm/opto/c2compiler.cpp +@@ -39,6 +39,8 @@ + # include "adfiles/ad_zero.hpp" + #elif defined TARGET_ARCH_MODEL_ppc_64 + # include "adfiles/ad_ppc_64.hpp" ++#elif defined TARGET_ARCH_MODEL_sw64 ++# include "adfiles/ad_sw64.hpp" + #endif + + // register information defined by ADLC +diff --git a/hotspot/src/share/vm/opto/compile.cpp b/hotspot/src/share/vm/opto/compile.cpp +index ae22ba84d9..a5c877b8e3 100644 +--- a/hotspot/src/share/vm/opto/compile.cpp ++++ b/hotspot/src/share/vm/opto/compile.cpp +@@ -81,6 +81,8 @@ + # include "adfiles/ad_zero.hpp" + #elif defined TARGET_ARCH_MODEL_ppc_64 + # include "adfiles/ad_ppc_64.hpp" ++#elif defined TARGET_ARCH_MODEL_sw64 ++# include "adfiles/ad_sw64.hpp" + #endif + + // -------------------- Compile::mach_constant_base_node ----------------------- +diff --git a/hotspot/src/share/vm/opto/gcm.cpp b/hotspot/src/share/vm/opto/gcm.cpp +index f51484efb0..a4c7e7eead 100644 +--- a/hotspot/src/share/vm/opto/gcm.cpp ++++ b/hotspot/src/share/vm/opto/gcm.cpp +@@ -49,6 +49,8 @@ + # include "adfiles/ad_zero.hpp" + #elif defined TARGET_ARCH_MODEL_ppc_64 + # include "adfiles/ad_ppc_64.hpp" ++#elif defined TARGET_ARCH_MODEL_sw64 ++# include "adfiles/ad_sw64.hpp" + #endif + + +diff --git a/hotspot/src/share/vm/opto/lcm.cpp b/hotspot/src/share/vm/opto/lcm.cpp +index c6178a715b..9b87986fe0 100644 +--- a/hotspot/src/share/vm/opto/lcm.cpp ++++ b/hotspot/src/share/vm/opto/lcm.cpp +@@ -44,6 +44,8 @@ + # include "adfiles/ad_zero.hpp" + #elif defined TARGET_ARCH_MODEL_ppc_64 + # include "adfiles/ad_ppc_64.hpp" ++#elif defined TARGET_ARCH_MODEL_sw64 ++# include "adfiles/ad_sw64.hpp" + #endif + + // Optimization - Graph Style +diff --git a/hotspot/src/share/vm/opto/locknode.hpp b/hotspot/src/share/vm/opto/locknode.hpp +index b320f6bfb2..9e9cfabbfe 100644 +--- a/hotspot/src/share/vm/opto/locknode.hpp ++++ b/hotspot/src/share/vm/opto/locknode.hpp +@@ -42,6 +42,8 @@ + # include "adfiles/ad_zero.hpp" + #elif defined TARGET_ARCH_MODEL_ppc_64 + # include "adfiles/ad_ppc_64.hpp" ++#elif defined TARGET_ARCH_MODEL_sw64 ++# include "adfiles/ad_sw64.hpp" + #endif + + //------------------------------BoxLockNode------------------------------------ +diff --git a/hotspot/src/share/vm/opto/matcher.cpp b/hotspot/src/share/vm/opto/matcher.cpp +index 6660b4b467..846d81f296 100644 +--- a/hotspot/src/share/vm/opto/matcher.cpp ++++ b/hotspot/src/share/vm/opto/matcher.cpp +@@ -52,6 +52,8 @@ + # include "adfiles/ad_zero.hpp" + #elif defined TARGET_ARCH_MODEL_ppc_64 + # include "adfiles/ad_ppc_64.hpp" ++#elif defined TARGET_ARCH_MODEL_sw64 ++# include "adfiles/ad_sw64.hpp" + #endif + + OptoReg::Name OptoReg::c_frame_pointer; +diff --git a/hotspot/src/share/vm/opto/output.hpp b/hotspot/src/share/vm/opto/output.hpp +index ba72841363..daf3d4453f 100644 +--- a/hotspot/src/share/vm/opto/output.hpp ++++ b/hotspot/src/share/vm/opto/output.hpp +@@ -41,6 +41,8 @@ + # include "adfiles/ad_zero.hpp" + #elif defined TARGET_ARCH_MODEL_ppc_64 + # include "adfiles/ad_ppc_64.hpp" ++#elif defined TARGET_ARCH_MODEL_sw64 ++# include "adfiles/ad_sw64.hpp" + #endif + + class Arena; +diff --git a/hotspot/src/share/vm/opto/regmask.cpp b/hotspot/src/share/vm/opto/regmask.cpp +index 352ccfb9d9..78d93a643b 100644 +--- a/hotspot/src/share/vm/opto/regmask.cpp ++++ b/hotspot/src/share/vm/opto/regmask.cpp +@@ -39,6 +39,8 @@ + # include "adfiles/ad_zero.hpp" + #elif defined TARGET_ARCH_MODEL_ppc_64 + # include "adfiles/ad_ppc_64.hpp" ++#elif defined TARGET_ARCH_MODEL_sw64 ++# include "adfiles/ad_sw64.hpp" + #endif + + #define RM_SIZE _RM_SIZE /* a constant private to the class RegMask */ +diff --git a/hotspot/src/share/vm/opto/regmask.hpp b/hotspot/src/share/vm/opto/regmask.hpp +index 5ceebb3fb8..e4beda9c78 100644 +--- a/hotspot/src/share/vm/opto/regmask.hpp ++++ b/hotspot/src/share/vm/opto/regmask.hpp +@@ -42,6 +42,8 @@ + # include "adfiles/adGlobals_zero.hpp" + #elif defined TARGET_ARCH_MODEL_ppc_64 + # include "adfiles/adGlobals_ppc_64.hpp" ++#elif defined TARGET_ARCH_MODEL_sw64 ++# include "adfiles/adGlobals_sw64.hpp" + #endif + + // Some fun naming (textual) substitutions: +diff --git a/hotspot/src/share/vm/opto/runtime.cpp b/hotspot/src/share/vm/opto/runtime.cpp +index a43b37f2c5..05e5715413 100644 +--- a/hotspot/src/share/vm/opto/runtime.cpp ++++ b/hotspot/src/share/vm/opto/runtime.cpp +@@ -82,6 +82,8 @@ + # include "adfiles/ad_zero.hpp" + #elif defined TARGET_ARCH_MODEL_ppc_64 + # include "adfiles/ad_ppc_64.hpp" ++#elif defined TARGET_ARCH_MODEL_sw64 ++# include "adfiles/ad_sw64.hpp" + #endif + + +diff --git a/hotspot/src/share/vm/prims/jni.cpp b/hotspot/src/share/vm/prims/jni.cpp +index ac29c82934..4b33773fa7 100644 +--- a/hotspot/src/share/vm/prims/jni.cpp ++++ b/hotspot/src/share/vm/prims/jni.cpp +@@ -97,9 +97,6 @@ + + static jint CurrentVersion = JNI_VERSION_1_8; + +-#ifdef _WIN32 +-extern LONG WINAPI topLevelExceptionFilter(_EXCEPTION_POINTERS* ); +-#endif + + // The DT_RETURN_MARK macros create a scoped object to fire the dtrace + // '-return' probe regardless of the return path is taken out of the function. +@@ -194,6 +191,8 @@ extern LONG WINAPI topLevelExceptionFilter(_EXCEPTION_POINTERS* ); + #define FP_SELECT(TypeName, intcode, fpcode) \ + FP_SELECT_##TypeName(intcode, fpcode) + ++#define COMMA , ++ + // Choose DT_RETURN_MARK macros based on the type: float/double -> void + // (dtrace doesn't do FP yet) + #ifndef USDT2 +@@ -5027,14 +5026,11 @@ static void post_thread_start_event(const JavaThread* jt) { + if (event.should_commit()) { + event.set_thread(JFR_THREAD_ID(jt)); + event.set_parentThread((traceid)0); +-#if INCLUDE_JFR + if (EventThreadStart::is_stacktrace_enabled()) { + jt->jfr_thread_local()->set_cached_stack_trace_id((traceid)0); + event.commit(); + jt->jfr_thread_local()->clear_cached_stack_trace(); +- } else +-#endif +- { ++ } else { + event.commit(); + } + } +@@ -5189,11 +5185,12 @@ DT_RETURN_MARK_DECL(CreateJavaVM, jint + , HOTSPOT_JNI_CREATEJAVAVM_RETURN(_ret_ref)); + #endif /* USDT2 */ + +-static jint JNI_CreateJavaVM_inner(JavaVM **vm, void **penv, void *args) { ++_JNI_IMPORT_OR_EXPORT_ jint JNICALL JNI_CreateJavaVM(JavaVM **vm, void **penv, void *args) { + #ifndef USDT2 + HS_DTRACE_PROBE3(hotspot_jni, CreateJavaVM__entry, vm, penv, args); + #else /* USDT2 */ +- HOTSPOT_JNI_CREATEJAVAVM_ENTRY((void **) vm, penv, args); ++ HOTSPOT_JNI_CREATEJAVAVM_ENTRY( ++ (void **) vm, penv, args); + #endif /* USDT2 */ + + jint result = JNI_ERR; +@@ -5265,14 +5262,18 @@ static jint JNI_CreateJavaVM_inner(JavaVM **vm, void **penv, void *args) { + post_thread_start_event(thread); + + #ifndef PRODUCT ++ #ifndef CALL_TEST_FUNC_WITH_WRAPPER_IF_NEEDED ++ #define CALL_TEST_FUNC_WITH_WRAPPER_IF_NEEDED(f) f() ++ #endif ++ + // Check if we should compile all classes on bootclasspath + if (CompileTheWorld) ClassLoader::compile_the_world(); + if (ReplayCompiles) ciReplay::replay(thread); + + // Some platforms (like Win*) need a wrapper around these test + // functions in order to properly handle error conditions. +- test_error_handler(); +- execute_internal_vm_tests(); ++ CALL_TEST_FUNC_WITH_WRAPPER_IF_NEEDED(test_error_handler); ++ CALL_TEST_FUNC_WITH_WRAPPER_IF_NEEDED(execute_internal_vm_tests); + #endif + + // Since this is not a JVM_ENTRY we have to set the thread state manually before leaving. +@@ -5292,22 +5293,6 @@ static jint JNI_CreateJavaVM_inner(JavaVM **vm, void **penv, void *args) { + } + + return result; +- +-} +- +-_JNI_IMPORT_OR_EXPORT_ jint JNICALL JNI_CreateJavaVM(JavaVM **vm, void **penv, void *args) { +- jint result = JNI_ERR; +- // On Windows, let CreateJavaVM run with SEH protection +-#ifdef _WIN32 +- __try { +-#endif +- result = JNI_CreateJavaVM_inner(vm, penv, args); +-#ifdef _WIN32 +- } __except(topLevelExceptionFilter((_EXCEPTION_POINTERS*)_exception_info())) { +- // Nothing to do. +- } +-#endif +- return result; + } + + #ifndef USDT2 +@@ -5350,11 +5335,12 @@ DT_RETURN_MARK_DECL(DestroyJavaVM, jint + , HOTSPOT_JNI_DESTROYJAVAVM_RETURN(_ret_ref)); + #endif /* USDT2 */ + +-static jint JNICALL jni_DestroyJavaVM_inner(JavaVM *vm) { ++jint JNICALL jni_DestroyJavaVM(JavaVM *vm) { + #ifndef USDT2 + DTRACE_PROBE1(hotspot_jni, DestroyJavaVM__entry, vm); + #else /* USDT2 */ +- HOTSPOT_JNI_DESTROYJAVAVM_ENTRY(vm); ++ HOTSPOT_JNI_DESTROYJAVAVM_ENTRY( ++ vm); + #endif /* USDT2 */ + jint res = JNI_ERR; + DT_RETURN_MARK(DestroyJavaVM, jint, (const jint&)res); +@@ -5390,20 +5376,6 @@ static jint JNICALL jni_DestroyJavaVM_inner(JavaVM *vm) { + } + } + +-jint JNICALL jni_DestroyJavaVM(JavaVM *vm) { +- jint result = JNI_ERR; +- // On Windows, we need SEH protection +-#ifdef _WIN32 +- __try { +-#endif +- result = jni_DestroyJavaVM_inner(vm); +-#ifdef _WIN32 +- } __except(topLevelExceptionFilter((_EXCEPTION_POINTERS*)_exception_info())) { +- // Nothing to do. +- } +-#endif +- return result; +-} + + static jint attach_current_thread(JavaVM *vm, void **penv, void *_args, bool daemon) { + JavaVMAttachArgs *args = (JavaVMAttachArgs *) _args; +diff --git a/hotspot/src/share/vm/prims/jniCheck.cpp b/hotspot/src/share/vm/prims/jniCheck.cpp +index 593ca8a1e3..9c954bdab6 100644 +--- a/hotspot/src/share/vm/prims/jniCheck.cpp ++++ b/hotspot/src/share/vm/prims/jniCheck.cpp +@@ -55,6 +55,9 @@ + #ifdef TARGET_ARCH_ppc + # include "jniTypes_ppc.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "jniTypes_sw64.hpp" ++#endif + + // Complain every extra number of unplanned local refs + #define CHECK_JNI_LOCAL_REF_CAP_WARN_THRESHOLD 32 +diff --git a/hotspot/src/share/vm/prims/jni_md.h b/hotspot/src/share/vm/prims/jni_md.h +index 6209a66449..c555f81056 100644 +--- a/hotspot/src/share/vm/prims/jni_md.h ++++ b/hotspot/src/share/vm/prims/jni_md.h +@@ -42,6 +42,9 @@ + #ifdef TARGET_ARCH_ppc + # include "jni_ppc.h" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "jni_sw64.h" ++#endif + + + /* +diff --git a/hotspot/src/share/vm/prims/jvmtiClassFileReconstituter.cpp b/hotspot/src/share/vm/prims/jvmtiClassFileReconstituter.cpp +index ab31d0d91e..3240480199 100644 +--- a/hotspot/src/share/vm/prims/jvmtiClassFileReconstituter.cpp ++++ b/hotspot/src/share/vm/prims/jvmtiClassFileReconstituter.cpp +@@ -46,6 +46,9 @@ + #ifdef TARGET_ARCH_ppc + # include "bytes_ppc.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "bytes_sw64.hpp" ++#endif + // FIXME: add Deprecated attribute + // FIXME: fix Synthetic attribute + // FIXME: per Serguei, add error return handling for ConstantPool::copy_cpool_bytes() +diff --git a/hotspot/src/share/vm/prims/methodHandles.hpp b/hotspot/src/share/vm/prims/methodHandles.hpp +index db6e06180d..150f8d1735 100644 +--- a/hotspot/src/share/vm/prims/methodHandles.hpp ++++ b/hotspot/src/share/vm/prims/methodHandles.hpp +@@ -198,6 +198,10 @@ public: + #ifdef TARGET_ARCH_ppc + # include "methodHandles_ppc.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "methodHandles_sw64.hpp" ++#endif ++ + + // Tracing + static void trace_method_handle(MacroAssembler* _masm, const char* adaptername) PRODUCT_RETURN; +diff --git a/hotspot/src/share/vm/runtime/arguments.cpp b/hotspot/src/share/vm/runtime/arguments.cpp +index 478ddf21be..911a11d72d 100644 +--- a/hotspot/src/share/vm/runtime/arguments.cpp ++++ b/hotspot/src/share/vm/runtime/arguments.cpp +@@ -1519,7 +1519,11 @@ void Arguments::set_use_compressed_oops() { + if (max_heap_size <= max_heap_for_compressed_oops()) { + #if !defined(COMPILER1) || defined(TIERED) + if (FLAG_IS_DEFAULT(UseCompressedOops)) { ++#ifdef SW64 ++ FLAG_SET_ERGO(bool, UseCompressedOops, false); ++#else + FLAG_SET_ERGO(bool, UseCompressedOops, true); ++#endif + } + #endif + #ifdef _WIN64 +diff --git a/hotspot/src/share/vm/runtime/atomic.inline.hpp b/hotspot/src/share/vm/runtime/atomic.inline.hpp +index 222f29cbf4..b1634e18bc 100644 +--- a/hotspot/src/share/vm/runtime/atomic.inline.hpp ++++ b/hotspot/src/share/vm/runtime/atomic.inline.hpp +@@ -31,6 +31,9 @@ + #ifdef TARGET_OS_ARCH_linux_x86 + # include "atomic_linux_x86.inline.hpp" + #endif ++#ifdef TARGET_OS_ARCH_linux_sw64 ++# include "atomic_linux_sw64.inline.hpp" ++#endif + #ifdef TARGET_OS_ARCH_linux_sparc + # include "atomic_linux_sparc.inline.hpp" + #endif +diff --git a/hotspot/src/share/vm/runtime/deoptimization.cpp b/hotspot/src/share/vm/runtime/deoptimization.cpp +index f91afdc416..c91b77de61 100644 +--- a/hotspot/src/share/vm/runtime/deoptimization.cpp ++++ b/hotspot/src/share/vm/runtime/deoptimization.cpp +@@ -68,6 +68,9 @@ + #ifdef TARGET_ARCH_ppc + # include "vmreg_ppc.inline.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "vmreg_sw64.inline.hpp" ++#endif + #ifdef COMPILER2 + #if defined AD_MD_HPP + # include AD_MD_HPP +@@ -83,6 +86,8 @@ + # include "adfiles/ad_zero.hpp" + #elif defined TARGET_ARCH_MODEL_ppc_64 + # include "adfiles/ad_ppc_64.hpp" ++#elif defined TARGET_ARCH_MODEL_sw64 ++# include "adfiles/ad_sw64.hpp" + #endif + #endif // COMPILER2 + +diff --git a/hotspot/src/share/vm/runtime/dtraceJSDT.hpp b/hotspot/src/share/vm/runtime/dtraceJSDT.hpp +index db568def34..11a3189dd5 100644 +--- a/hotspot/src/share/vm/runtime/dtraceJSDT.hpp ++++ b/hotspot/src/share/vm/runtime/dtraceJSDT.hpp +@@ -44,6 +44,9 @@ + #ifdef TARGET_ARCH_ppc + # include "nativeInst_ppc.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "nativeInst_sw64.hpp" ++#endif + + class RegisteredProbes; + typedef jlong OpaqueProbes; +diff --git a/hotspot/src/share/vm/runtime/frame.cpp b/hotspot/src/share/vm/runtime/frame.cpp +index 338b7ad3a7..ab7fc69677 100644 +--- a/hotspot/src/share/vm/runtime/frame.cpp ++++ b/hotspot/src/share/vm/runtime/frame.cpp +@@ -64,6 +64,9 @@ + #ifdef TARGET_ARCH_ppc + # include "nativeInst_ppc.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "nativeInst_sw64.hpp" ++#endif + + PRAGMA_FORMAT_MUTE_WARNINGS_FOR_GCC + +diff --git a/hotspot/src/share/vm/runtime/frame.hpp b/hotspot/src/share/vm/runtime/frame.hpp +index 2d80ecc208..89e56c6c76 100644 +--- a/hotspot/src/share/vm/runtime/frame.hpp ++++ b/hotspot/src/share/vm/runtime/frame.hpp +@@ -45,6 +45,8 @@ + # include "adfiles/adGlobals_zero.hpp" + #elif defined TARGET_ARCH_MODEL_ppc_64 + # include "adfiles/adGlobals_ppc_64.hpp" ++#elif defined TARGET_ARCH_MODEL_sw64 ++# include "adfiles/adGlobals_sw64.hpp" + #endif + #endif // COMPILER2 + #ifdef TARGET_ARCH_zero +@@ -489,6 +491,9 @@ class frame VALUE_OBJ_CLASS_SPEC { + #ifdef TARGET_ARCH_x86 + # include "frame_x86.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "frame_sw64.hpp" ++#endif + #ifdef TARGET_ARCH_aarch64 + # include "frame_aarch64.hpp" + #endif +diff --git a/hotspot/src/share/vm/runtime/frame.inline.hpp b/hotspot/src/share/vm/runtime/frame.inline.hpp +index 710b82306a..cdaac528bd 100644 +--- a/hotspot/src/share/vm/runtime/frame.inline.hpp ++++ b/hotspot/src/share/vm/runtime/frame.inline.hpp +@@ -49,6 +49,9 @@ + #ifdef TARGET_ARCH_ppc + # include "jniTypes_ppc.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "jniTypes_sw64.hpp" ++#endif + #ifdef TARGET_ARCH_zero + # include "entryFrame_zero.hpp" + # include "fakeStubFrame_zero.hpp" +@@ -115,6 +118,9 @@ inline oop* frame::interpreter_frame_temp_oop_addr() const { + #ifdef TARGET_ARCH_ppc + # include "frame_ppc.inline.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "frame_sw64.inline.hpp" ++#endif + + + #endif // SHARE_VM_RUNTIME_FRAME_INLINE_HPP +diff --git a/hotspot/src/share/vm/runtime/globals.hpp b/hotspot/src/share/vm/runtime/globals.hpp +index 23ce8af569..379cd3ddc9 100644 +--- a/hotspot/src/share/vm/runtime/globals.hpp ++++ b/hotspot/src/share/vm/runtime/globals.hpp +@@ -55,6 +55,9 @@ + #ifdef TARGET_ARCH_ppc + # include "globals_ppc.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "globals_sw64.hpp" ++#endif + #ifdef TARGET_OS_FAMILY_linux + # include "globals_linux.hpp" + #endif +@@ -79,6 +82,9 @@ + #ifdef TARGET_OS_ARCH_linux_sparc + # include "globals_linux_sparc.hpp" + #endif ++#ifdef TARGET_OS_ARCH_linux_sw64 ++# include "globals_linux_sw64.hpp" ++#endif + #ifdef TARGET_OS_ARCH_linux_zero + # include "globals_linux_zero.hpp" + #endif +@@ -116,6 +122,9 @@ + #ifdef TARGET_ARCH_sparc + # include "c1_globals_sparc.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "c1_globals_sw64.hpp" ++#endif + #ifdef TARGET_ARCH_arm + # include "c1_globals_arm.hpp" + #endif +@@ -148,6 +157,9 @@ + #ifdef TARGET_ARCH_sparc + # include "c2_globals_sparc.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "c2_globals_sw64.hpp" ++#endif + #ifdef TARGET_ARCH_arm + # include "c2_globals_arm.hpp" + #endif +@@ -3209,7 +3221,7 @@ class CommandLineFlags { + product(uintx, InitialHeapSize, 0, \ + "Initial heap size (in bytes); zero means use ergonomics") \ + \ +- product(uintx, MaxHeapSize, ScaleForWordSize(96*M), \ ++ product(uintx, MaxHeapSize, ScaleForWordSize(SW64_ONLY(1500) NOT_SW64(96) *M), \ + "Maximum heap size (in bytes)") \ + \ + product(uintx, OldSize, ScaleForWordSize(4*M), \ +diff --git a/hotspot/src/share/vm/runtime/icache.hpp b/hotspot/src/share/vm/runtime/icache.hpp +index ba81a06ff5..17a0307bd4 100644 +--- a/hotspot/src/share/vm/runtime/icache.hpp ++++ b/hotspot/src/share/vm/runtime/icache.hpp +@@ -86,7 +86,9 @@ class AbstractICache : AllStatic { + #ifdef TARGET_ARCH_ppc + # include "icache_ppc.hpp" + #endif +- ++#ifdef TARGET_ARCH_sw64 ++# include "icache_sw64.hpp" ++#endif + + + class ICacheStubGenerator : public StubCodeGenerator { +diff --git a/hotspot/src/share/vm/runtime/java.cpp b/hotspot/src/share/vm/runtime/java.cpp +index 0a263b017c..c1ac747b71 100644 +--- a/hotspot/src/share/vm/runtime/java.cpp ++++ b/hotspot/src/share/vm/runtime/java.cpp +@@ -84,6 +84,9 @@ + #ifdef TARGET_ARCH_ppc + # include "vm_version_ppc.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "vm_version_sw64.hpp" ++#endif + #if INCLUDE_ALL_GCS + #include "gc_implementation/concurrentMarkSweep/concurrentMarkSweepThread.hpp" + #include "gc_implementation/parallelScavenge/psScavenge.hpp" +diff --git a/hotspot/src/share/vm/runtime/javaCalls.hpp b/hotspot/src/share/vm/runtime/javaCalls.hpp +index 6126bbe75e..71800c670d 100644 +--- a/hotspot/src/share/vm/runtime/javaCalls.hpp ++++ b/hotspot/src/share/vm/runtime/javaCalls.hpp +@@ -49,6 +49,9 @@ + #ifdef TARGET_ARCH_ppc + # include "jniTypes_ppc.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "jniTypes_sw64.hpp" ++#endif + + // A JavaCallWrapper is constructed before each JavaCall and destructed after the call. + // Its purpose is to allocate/deallocate a new handle block and to save/restore the last +diff --git a/hotspot/src/share/vm/runtime/javaFrameAnchor.hpp b/hotspot/src/share/vm/runtime/javaFrameAnchor.hpp +index 129a01e293..b3559e74d6 100644 +--- a/hotspot/src/share/vm/runtime/javaFrameAnchor.hpp ++++ b/hotspot/src/share/vm/runtime/javaFrameAnchor.hpp +@@ -80,6 +80,9 @@ friend class JavaCallWrapper; + #ifdef TARGET_ARCH_x86 + # include "javaFrameAnchor_x86.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "javaFrameAnchor_sw64.hpp" ++#endif + #ifdef TARGET_ARCH_aarch64 + # include "javaFrameAnchor_aarch64.hpp" + #endif +diff --git a/hotspot/src/share/vm/runtime/orderAccess.inline.hpp b/hotspot/src/share/vm/runtime/orderAccess.inline.hpp +index a5de5edc79..b840f3f1e4 100644 +--- a/hotspot/src/share/vm/runtime/orderAccess.inline.hpp ++++ b/hotspot/src/share/vm/runtime/orderAccess.inline.hpp +@@ -47,6 +47,9 @@ + #ifdef TARGET_OS_ARCH_linux_ppc + # include "orderAccess_linux_ppc.inline.hpp" + #endif ++#ifdef TARGET_OS_ARCH_linux_sw64 ++# include "orderAccess_linux_sw64.inline.hpp" ++#endif + + // Solaris + #ifdef TARGET_OS_ARCH_solaris_x86 +diff --git a/hotspot/src/share/vm/runtime/os.hpp b/hotspot/src/share/vm/runtime/os.hpp +index 836c231b03..bdaef4b205 100644 +--- a/hotspot/src/share/vm/runtime/os.hpp ++++ b/hotspot/src/share/vm/runtime/os.hpp +@@ -860,6 +860,9 @@ class os: AllStatic { + #ifdef TARGET_OS_ARCH_linux_aarch64 + # include "os_linux_aarch64.hpp" + #endif ++#ifdef TARGET_OS_ARCH_linux_sw64 ++# include "os_linux_sw64.hpp" ++#endif + #ifdef TARGET_OS_ARCH_linux_sparc + # include "os_linux_sparc.hpp" + #endif +diff --git a/hotspot/src/share/vm/runtime/prefetch.inline.hpp b/hotspot/src/share/vm/runtime/prefetch.inline.hpp +index f4e30de34d..e46d597215 100644 +--- a/hotspot/src/share/vm/runtime/prefetch.inline.hpp ++++ b/hotspot/src/share/vm/runtime/prefetch.inline.hpp +@@ -46,6 +46,9 @@ + #ifdef TARGET_OS_ARCH_linux_ppc + # include "prefetch_linux_ppc.inline.hpp" + #endif ++#ifdef TARGET_OS_ARCH_linux_sw64 ++# include "prefetch_linux_sw64.inline.hpp" ++#endif + + // Solaris + #ifdef TARGET_OS_ARCH_solaris_x86 +diff --git a/hotspot/src/share/vm/runtime/registerMap.hpp b/hotspot/src/share/vm/runtime/registerMap.hpp +index 67ef212d65..8efe021730 100644 +--- a/hotspot/src/share/vm/runtime/registerMap.hpp ++++ b/hotspot/src/share/vm/runtime/registerMap.hpp +@@ -45,6 +45,9 @@ + #ifdef TARGET_ARCH_ppc + # include "register_ppc.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "register_sw64.hpp" ++#endif + + class JavaThread; + +@@ -156,6 +159,9 @@ class RegisterMap : public StackObj { + #ifdef TARGET_ARCH_ppc + # include "registerMap_ppc.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "registerMap_sw64.hpp" ++#endif + + }; + +diff --git a/hotspot/src/share/vm/runtime/relocator.hpp b/hotspot/src/share/vm/runtime/relocator.hpp +index bb19c75fe6..15aebcfd82 100644 +--- a/hotspot/src/share/vm/runtime/relocator.hpp ++++ b/hotspot/src/share/vm/runtime/relocator.hpp +@@ -45,6 +45,9 @@ + #ifdef TARGET_ARCH_ppc + # include "bytes_ppc.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "bytes_sw64.hpp" ++#endif + + // This code has been converted from the 1.1E java virtual machine + // Thanks to the JavaTopics group for using the code +diff --git a/hotspot/src/share/vm/runtime/safepoint.cpp b/hotspot/src/share/vm/runtime/safepoint.cpp +index 440617c802..183d66a9a4 100644 +--- a/hotspot/src/share/vm/runtime/safepoint.cpp ++++ b/hotspot/src/share/vm/runtime/safepoint.cpp +@@ -78,6 +78,10 @@ + # include "nativeInst_ppc.hpp" + # include "vmreg_ppc.inline.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "nativeInst_sw64.hpp" ++# include "vmreg_sw64.inline.hpp" ++#endif + #if INCLUDE_ALL_GCS + #include "gc_implementation/concurrentMarkSweep/concurrentMarkSweepThread.hpp" + #include "gc_implementation/shared/suspendibleThreadSet.hpp" +diff --git a/hotspot/src/share/vm/runtime/sharedRuntime.cpp b/hotspot/src/share/vm/runtime/sharedRuntime.cpp +index 5f540247f9..1a8a3e79c7 100644 +--- a/hotspot/src/share/vm/runtime/sharedRuntime.cpp ++++ b/hotspot/src/share/vm/runtime/sharedRuntime.cpp +@@ -82,6 +82,11 @@ + # include "nativeInst_ppc.hpp" + # include "vmreg_ppc.inline.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "nativeInst_sw64.hpp" ++# include "vmreg_sw64.inline.hpp" ++#endif ++ + #ifdef COMPILER1 + #include "c1/c1_Runtime1.hpp" + #endif +@@ -247,6 +252,26 @@ JRT_LEAF(jlong, SharedRuntime::lmul(jlong y, jlong x)) + JRT_END + + ++#ifdef SW64 //ZHJ20110311(LZS) ++JRT_LEAF(jint, SharedRuntime::sdiv(jint y, jint x)) ++ if (x == min_jint && y == CONST64(-1)) { ++ return x; ++ } else { ++ return x / y; ++ } ++JRT_END ++ ++ ++JRT_LEAF(jint, SharedRuntime::srem(jint y, jint x)) ++ if (x == min_jint && y == CONST64(-1)) { ++ return 0; ++ } else { ++ return x % y; ++ } ++JRT_END ++#endif ++ ++ + JRT_LEAF(jlong, SharedRuntime::ldiv(jlong y, jlong x)) + if (x == min_jlong && y == CONST64(-1)) { + return x; +diff --git a/hotspot/src/share/vm/runtime/sharedRuntime.hpp b/hotspot/src/share/vm/runtime/sharedRuntime.hpp +index c6a96a858e..53dbe17dbc 100644 +--- a/hotspot/src/share/vm/runtime/sharedRuntime.hpp ++++ b/hotspot/src/share/vm/runtime/sharedRuntime.hpp +@@ -92,6 +92,11 @@ class SharedRuntime: AllStatic { + // not have machine instructions to implement their functionality. + // Do not remove these. + ++#ifdef SW64 //ZHJ20110311(LZS) ++ static jint sdiv(jint y, jint x); ++ static jint srem(jint y, jint x); ++#endif ++ + // long arithmetics + static jlong lmul(jlong y, jlong x); + static jlong ldiv(jlong y, jlong x); +@@ -145,6 +150,10 @@ class SharedRuntime: AllStatic { + static double dsqrt(double f); + #endif + ++#ifdef SW64 ++ static unsigned int updateBytesCRC32(unsigned long crc, const unsigned char *buf_bytes, unsigned int len_ints); ++#endif ++ + // Montgomery multiplication + static void montgomery_multiply(jint *a_ints, jint *b_ints, jint *n_ints, + jint len, jlong inv, jint *m_ints); +@@ -587,6 +596,13 @@ class SharedRuntime: AllStatic { + static void print_ic_miss_histogram(); + + #endif // PRODUCT ++// static void print_long(long long i); ++// static void print_int(int i); ++// static void print_float(float i); ++// static void print_double(double i); ++// static void print_str(char *str); ++// ++// static void print_reg_with_pc(char *reg_name, long i, long pc); + }; + + +diff --git a/hotspot/src/share/vm/runtime/sharedRuntimeTrig.cpp b/hotspot/src/share/vm/runtime/sharedRuntimeTrig.cpp +index 37880d8a5c..0e9103c5e2 100644 +--- a/hotspot/src/share/vm/runtime/sharedRuntimeTrig.cpp ++++ b/hotspot/src/share/vm/runtime/sharedRuntimeTrig.cpp +@@ -534,6 +534,14 @@ static SAFEBUF int __ieee754_rem_pio2(double x, double *y) { + * then 3 2 + * sin(x) = x + (S1*x + (x *(r-y/2)+y)) + */ ++#if defined(SW64) ++#undef S1 ++#undef S2 ++#undef S3 ++#undef S4 ++#undef S5 ++#undef S6 ++#endif + + static const double + S1 = -1.66666666666666324348e-01, /* 0xBFC55555, 0x55555549 */ +diff --git a/hotspot/src/share/vm/runtime/stackValueCollection.cpp b/hotspot/src/share/vm/runtime/stackValueCollection.cpp +index 8774768311..26318ea104 100644 +--- a/hotspot/src/share/vm/runtime/stackValueCollection.cpp ++++ b/hotspot/src/share/vm/runtime/stackValueCollection.cpp +@@ -42,6 +42,9 @@ + #ifdef TARGET_ARCH_ppc + # include "jniTypes_ppc.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "jniTypes_sw64.hpp" ++#endif + + PRAGMA_FORMAT_MUTE_WARNINGS_FOR_GCC + +diff --git a/hotspot/src/share/vm/runtime/statSampler.cpp b/hotspot/src/share/vm/runtime/statSampler.cpp +index 41f469622f..78e1af1dc4 100644 +--- a/hotspot/src/share/vm/runtime/statSampler.cpp ++++ b/hotspot/src/share/vm/runtime/statSampler.cpp +@@ -51,6 +51,9 @@ + #ifdef TARGET_ARCH_ppc + # include "vm_version_ppc.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "vm_version_sw64.hpp" ++#endif + + // -------------------------------------------------------- + // StatSamplerTask +diff --git a/hotspot/src/share/vm/runtime/stubRoutines.hpp b/hotspot/src/share/vm/runtime/stubRoutines.hpp +index e18b9127df..62f0ef3539 100644 +--- a/hotspot/src/share/vm/runtime/stubRoutines.hpp ++++ b/hotspot/src/share/vm/runtime/stubRoutines.hpp +@@ -49,6 +49,9 @@ + #ifdef TARGET_ARCH_ppc + # include "nativeInst_ppc.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "nativeInst_sw64.hpp" ++#endif + + // StubRoutines provides entry points to assembly routines used by + // compiled code and the run-time system. Platform-specific entry +@@ -116,6 +119,8 @@ class StubRoutines: AllStatic { + # include "stubRoutines_zero.hpp" + #elif defined TARGET_ARCH_MODEL_ppc_64 + # include "stubRoutines_ppc_64.hpp" ++#elif defined TARGET_ARCH_MODEL_sw64 ++# include "stubRoutines_sw64.hpp" + #endif + + static jint _verify_oop_count; +diff --git a/hotspot/src/share/vm/runtime/thread.cpp b/hotspot/src/share/vm/runtime/thread.cpp +index e6586c40cb..129efaf4ae 100644 +--- a/hotspot/src/share/vm/runtime/thread.cpp ++++ b/hotspot/src/share/vm/runtime/thread.cpp +@@ -3454,6 +3454,11 @@ jint Threads::create_vm(JavaVMInitArgs* args, bool* canTryAgain) { + + JFR_ONLY(Jfr::on_vm_init();) + ++#if (defined(SW64) && !defined ZERO) ++ /* 2013/11/5 Jin: To be accessed in NativeGeneralJump::patch_verified_entry() */ ++ main_thread->set_handle_wrong_method_stub(SharedRuntime::get_handle_wrong_method_stub()); ++#endif ++ + // Should be done after the heap is fully created + main_thread->cache_global_variables(); + +diff --git a/hotspot/src/share/vm/runtime/thread.hpp b/hotspot/src/share/vm/runtime/thread.hpp +index 1c19ab7290..7f68b8358f 100644 +--- a/hotspot/src/share/vm/runtime/thread.hpp ++++ b/hotspot/src/share/vm/runtime/thread.hpp +@@ -1054,7 +1054,7 @@ class JavaThread: public Thread { + address last_Java_pc(void) { return _anchor.last_Java_pc(); } + + // Safepoint support +-#if !(defined(PPC64) || defined(AARCH64)) ++#if !(defined(PPC64) || defined(AARCH64) || defined(SW64)) + JavaThreadState thread_state() const { return _thread_state; } + void set_thread_state(JavaThreadState s) { _thread_state = s; } + #else +@@ -1714,6 +1714,9 @@ public: + #ifdef TARGET_OS_ARCH_linux_aarch64 + # include "thread_linux_aarch64.hpp" + #endif ++#ifdef TARGET_OS_ARCH_linux_sw64 ++# include "thread_linux_sw64.hpp" ++#endif + #ifdef TARGET_OS_ARCH_linux_sparc + # include "thread_linux_sparc.hpp" + #endif +diff --git a/hotspot/src/share/vm/runtime/thread.inline.hpp b/hotspot/src/share/vm/runtime/thread.inline.hpp +index b05e0ec5ce..10923a5da4 100644 +--- a/hotspot/src/share/vm/runtime/thread.inline.hpp ++++ b/hotspot/src/share/vm/runtime/thread.inline.hpp +@@ -59,7 +59,7 @@ inline jlong Thread::cooked_allocated_bytes() { + return allocated_bytes; + } + +-#if defined(PPC64) || defined (AARCH64) ++#if defined(PPC64) || defined (AARCH64) | defined (SW64) + inline JavaThreadState JavaThread::thread_state() const { + return (JavaThreadState) OrderAccess::load_acquire((volatile jint*)&_thread_state); + } +diff --git a/hotspot/src/share/vm/runtime/threadLocalStorage.hpp b/hotspot/src/share/vm/runtime/threadLocalStorage.hpp +index 58c1afc810..4cc5bffa0d 100644 +--- a/hotspot/src/share/vm/runtime/threadLocalStorage.hpp ++++ b/hotspot/src/share/vm/runtime/threadLocalStorage.hpp +@@ -51,6 +51,9 @@ class ThreadLocalStorage : AllStatic { + #ifdef TARGET_OS_ARCH_linux_x86 + # include "threadLS_linux_x86.hpp" + #endif ++#ifdef TARGET_OS_ARCH_linux_sw64 ++# include "threadLS_linux_sw64.hpp" ++#endif + #ifdef TARGET_OS_ARCH_linux_aarch64 + # include "threadLS_linux_aarch64.hpp" + #endif +diff --git a/hotspot/src/share/vm/runtime/vmStructs.cpp b/hotspot/src/share/vm/runtime/vmStructs.cpp +index e0e9bcf7e9..9cfbd6f03e 100644 +--- a/hotspot/src/share/vm/runtime/vmStructs.cpp ++++ b/hotspot/src/share/vm/runtime/vmStructs.cpp +@@ -122,6 +122,9 @@ + #ifdef TARGET_ARCH_ppc + # include "vmStructs_ppc.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "vmStructs_sw64.hpp" ++#endif + #ifdef TARGET_OS_ARCH_linux_x86 + # include "vmStructs_linux_x86.hpp" + #endif +@@ -149,6 +152,9 @@ + #ifdef TARGET_OS_ARCH_linux_ppc + # include "vmStructs_linux_ppc.hpp" + #endif ++#ifdef TARGET_OS_ARCH_linux_sw64 ++# include "vmStructs_linux_sw64.hpp" ++#endif + #ifdef TARGET_OS_ARCH_aix_ppc + # include "vmStructs_aix_ppc.hpp" + #endif +@@ -208,6 +214,8 @@ + # include "adfiles/adGlobals_zero.hpp" + #elif defined TARGET_ARCH_MODEL_ppc_64 + # include "adfiles/adGlobals_ppc_64.hpp" ++#elif defined TARGET_ARCH_MODEL_sw64 ++# include "adfiles/adGlobals_sw64.hpp" + #endif + #endif // COMPILER2 + +diff --git a/hotspot/src/share/vm/runtime/vm_version.cpp b/hotspot/src/share/vm/runtime/vm_version.cpp +index 91f9c70f5a..2efba08e53 100644 +--- a/hotspot/src/share/vm/runtime/vm_version.cpp ++++ b/hotspot/src/share/vm/runtime/vm_version.cpp +@@ -44,6 +44,9 @@ + #ifdef TARGET_ARCH_ppc + # include "vm_version_ppc.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "vm_version_sw64.hpp" ++#endif + + const char* Abstract_VM_Version::_s_vm_release = Abstract_VM_Version::vm_release(); + const char* Abstract_VM_Version::_s_internal_vm_info_string = Abstract_VM_Version::internal_vm_info_string(); +@@ -197,6 +200,7 @@ const char* Abstract_VM_Version::jre_release_version() { + #define CPU IA32_ONLY("x86") \ + IA64_ONLY("ia64") \ + AMD64_ONLY("amd64") \ ++ SW64_ONLY("sw64") \ + AARCH64_ONLY("aarch64") \ + SPARC_ONLY("sparc") + #endif // ZERO +diff --git a/hotspot/src/share/vm/utilities/copy.hpp b/hotspot/src/share/vm/utilities/copy.hpp +index c1d82c7083..2b8ca1c45b 100644 +--- a/hotspot/src/share/vm/utilities/copy.hpp ++++ b/hotspot/src/share/vm/utilities/copy.hpp +@@ -331,6 +331,27 @@ class Copy : AllStatic { + #endif + } + ++ ++ // SAPJVM AS 2011-09-20. Template for atomic copy. ++ template static void copy_conjoint_atomic(T* from, T* to, size_t count) ++ { ++ if (from > to) { ++ while (count-- > 0) { ++ // Copy forwards ++ *to++ = *from++; ++ } ++ } else { ++ from += count - 1; ++ to += count - 1; ++ while (count-- > 0) { ++ // Copy backwards ++ *to-- = *from--; ++ } ++ } ++ } ++ ++ ++ + // Platform dependent implementations of the above methods. + #ifdef TARGET_ARCH_x86 + # include "copy_x86.hpp" +@@ -350,6 +371,10 @@ class Copy : AllStatic { + #ifdef TARGET_ARCH_ppc + # include "copy_ppc.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "copy_sw64.hpp" ++#endif ++ + + }; + +diff --git a/hotspot/src/share/vm/utilities/globalDefinitions.hpp b/hotspot/src/share/vm/utilities/globalDefinitions.hpp +index 4207777aee..a5f43822db 100644 +--- a/hotspot/src/share/vm/utilities/globalDefinitions.hpp ++++ b/hotspot/src/share/vm/utilities/globalDefinitions.hpp +@@ -455,6 +455,9 @@ enum RTMState { + #ifdef TARGET_ARCH_ppc + # include "globalDefinitions_ppc.hpp" + #endif ++#ifdef TARGET_ARCH_sw64 ++# include "globalDefinitions_sw64.hpp" ++#endif + + /* + * If a platform does not support native stack walking +diff --git a/hotspot/src/share/vm/utilities/macros.hpp b/hotspot/src/share/vm/utilities/macros.hpp +index 599e1074de..8ebc7f2dca 100644 +--- a/hotspot/src/share/vm/utilities/macros.hpp ++++ b/hotspot/src/share/vm/utilities/macros.hpp +@@ -373,6 +373,14 @@ + #define NOT_SPARC(code) code + #endif + ++#ifdef SW64 ++#define SW64_ONLY(code) code ++#define NOT_SW64(code) ++#else ++#define SW64_ONLY(code) ++#define NOT_SW64(code) code ++#endif ++ + #if defined(PPC32) || defined(PPC64) + #ifndef PPC + #define PPC +diff --git a/hotspot/src/share/vm/utilities/ticks.hpp b/hotspot/src/share/vm/utilities/ticks.hpp +index 81deb7094f..2794173fe6 100644 +--- a/hotspot/src/share/vm/utilities/ticks.hpp ++++ b/hotspot/src/share/vm/utilities/ticks.hpp +@@ -57,6 +57,43 @@ class FastUnorderedElapsedCounterSource { + static uint64_t nanoseconds(Type value); + }; + ++#ifdef TARGET_ARCH_sw64 ++template ++class PairRep { ++ public: ++ XT1 val1; ++ XT2 val2; ++ ++ PairRep() : val1((XT1)0), val2((XT2)0) {} ++ void operator+=(const PairRep& rhs) { ++ val1 += rhs.val1; ++ val2 += rhs.val2; ++ } ++ void operator-=(const PairRep& rhs) { ++ val1 -= rhs.val1; ++ val2 -= rhs.val2; ++ } ++ bool operator==(const PairRep& rhs) const { ++ return val1 == rhs.val1; ++ } ++ bool operator!=(const PairRep& rhs) const { ++ return !operator==(rhs); ++ } ++ bool operator<(const PairRep& rhs) const { ++ return val1 < rhs.val1; ++ } ++ bool operator>(const PairRep& rhs) const { ++ return val1 > rhs.val1; ++ } ++}; ++ ++template ++PairRep operator-(const PairRep& lhs, const PairRep& rhs) { ++ PairRep temp(lhs); ++ temp -= rhs; ++ return temp; ++} ++#else + template + class PairRep { + public: +@@ -92,6 +129,7 @@ PairRep operator-(const PairRep& lhs, const PairRep& rhs + temp -= rhs; + return temp; + } ++#endif + + typedef PairRep CompositeTime; + +diff --git a/hotspot/test/runtime/6929067/Test6929067.sh b/hotspot/test/runtime/6929067/Test6929067.sh +index 2bbb3401ce..3c7b0d203a 100644 +--- a/hotspot/test/runtime/6929067/Test6929067.sh ++++ b/hotspot/test/runtime/6929067/Test6929067.sh +@@ -97,6 +97,9 @@ case "$ARCH" in + i686) + ARCH=i386 + ;; ++ sw_64) ++ ARCH=sw64 ++ ;; + # Assuming other ARCH values need no translation + esac + +diff --git a/hotspot/test/test_env.sh b/hotspot/test/test_env.sh +index 5ba4f28c45..7a8f7949ad 100644 +--- a/hotspot/test/test_env.sh ++++ b/hotspot/test/test_env.sh +@@ -211,6 +211,11 @@ if [ $? = 0 ] + then + VM_CPU="aarch64" + fi ++grep "sw64" vm_version.out > ${NULL} ++if [ $? = 0 ] ++then ++ VM_CPU="sw64" ++fi + export VM_TYPE VM_BITS VM_OS VM_CPU + echo "VM_TYPE=${VM_TYPE}" + echo "VM_BITS=${VM_BITS}" +diff --git a/jaxp/THIRD_PARTY_README b/jaxp/THIRD_PARTY_README +new file mode 100644 +index 0000000000..f26a5f3ec5 +--- /dev/null ++++ b/jaxp/THIRD_PARTY_README +@@ -0,0 +1,3371 @@ ++DO NOT TRANSLATE OR LOCALIZE. ++----------------------------- ++ ++%% This notice is provided with respect to ASM Bytecode Manipulation ++Framework v5.0.3, which may be included with JRE 8, and JDK 8, and ++OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++Copyright (c) 2000-2011 France T??l??com ++All rights reserved. ++ ++Redistribution and use in source and binary forms, with or without ++modification, are permitted provided that the following conditions ++are met: ++ ++1. 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Bitstream Vera is ++a trademark of Bitstream, Inc. ++ ++Permission is hereby granted, free of charge, to any person obtaining a copy ++of the fonts accompanying this license ("Fonts") and associated ++documentation files (the "Font Software"), to reproduce and distribute the ++Font Software, including without limitation the rights to use, copy, merge, ++publish, distribute, and/or sell copies of the Font Software, and to permit ++persons to whom the Font Software is furnished to do so, subject to the ++following conditions: ++ ++The above copyright and trademark notices and this permission notice shall ++be included in all copies of one or more of the Font Software typefaces. ++ ++The Font Software may be modified, altered, or added to, and in particular ++the designs of glyphs or characters in the Fonts may be modified and ++additional glyphs or characters may be added to the Fonts, only if the fonts ++are renamed to names not containing either the words "Bitstream" or the word ++"Vera". ++ ++This License becomes null and void to the extent applicable to Fonts or Font ++Software that has been modified and is distributed under the "Bitstream ++Vera" names. ++ ++The Font Software may be sold as part of a larger software package but no ++copy of one or more of the Font Software typefaces may be sold by itself. ++ ++THE FONT SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++OR IMPLIED, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OF MERCHANTABILITY, ++FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT OF COPYRIGHT, PATENT, ++TRADEMARK, OR OTHER RIGHT. IN NO EVENT SHALL BITSTREAM OR THE GNOME ++FOUNDATION BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, INCLUDING ++ANY GENERAL, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, ++WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF ++THE USE OR INABILITY TO USE THE FONT SOFTWARE OR FROM OTHER DEALINGS IN THE ++FONT SOFTWARE. ++ ++Except as contained in this notice, the names of Gnome, the Gnome ++Foundation, and Bitstream Inc., shall not be used in advertising or ++otherwise to promote the sale, use or other dealings in this Font Software ++without prior written authorization from the Gnome Foundation or Bitstream ++Inc., respectively. For further information, contact: fonts at gnome dot ++org. ++ ++Arev Fonts Copyright ++------------------------------ ++ ++Copyright (c) 2006 by Tavmjong Bah. All Rights Reserved. ++ ++Permission is hereby granted, free of charge, to any person obtaining ++a copy of the fonts accompanying this license ("Fonts") and ++associated documentation files (the "Font Software"), to reproduce ++and distribute the modifications to the Bitstream Vera Font Software, ++including without limitation the rights to use, copy, merge, publish, ++distribute, and/or sell copies of the Font Software, and to permit ++persons to whom the Font Software is furnished to do so, subject to ++the following conditions: ++ ++The above copyright and trademark notices and this permission notice ++shall be included in all copies of one or more of the Font Software ++typefaces. ++ ++The Font Software may be modified, altered, or added to, and in ++particular the designs of glyphs or characters in the Fonts may be ++modified and additional glyphs or characters may be added to the ++Fonts, only if the fonts are renamed to names not containing either ++the words "Tavmjong Bah" or the word "Arev". ++ ++This License becomes null and void to the extent applicable to Fonts ++or Font Software that has been modified and is distributed under the ++"Tavmjong Bah Arev" names. ++ ++The Font Software may be sold as part of a larger software package but ++no copy of one or more of the Font Software typefaces may be sold by ++itself. ++ ++THE FONT SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OF ++MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT ++OF COPYRIGHT, PATENT, TRADEMARK, OR OTHER RIGHT. IN NO EVENT SHALL ++TAVMJONG BAH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++INCLUDING ANY GENERAL, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL ++DAMAGES, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++FROM, OUT OF THE USE OR INABILITY TO USE THE FONT SOFTWARE OR FROM ++OTHER DEALINGS IN THE FONT SOFTWARE. ++ ++Except as contained in this notice, the name of Tavmjong Bah shall not ++be used in advertising or otherwise to promote the sale, use or other ++dealings in this Font Software without prior written authorization ++from Tavmjong Bah. For further information, contact: tavmjong @ free ++. fr. ++ ++TeX Gyre DJV Math ++----------------- ++Fonts are (c) Bitstream (see below). DejaVu changes are in public domain. ++ ++Math extensions done by B. Jackowski, P. Strzelczyk and P. Pianowski ++(on behalf of TeX users groups) are in public domain. ++ ++Letters imported from Euler Fraktur from AMSfonts are (c) American ++Mathematical Society (see below). ++Bitstream Vera Fonts Copyright ++Copyright (c) 2003 by Bitstream, Inc. All Rights Reserved. Bitstream Vera ++is a trademark of Bitstream, Inc. ++ ++Permission is hereby granted, free of charge, to any person obtaining a copy ++of the fonts accompanying this license ("Fonts") and associated documentation ++files (the "Font Software"), to reproduce and distribute the Font Software, ++including without limitation the rights to use, copy, merge, publish, ++distribute, and/or sell copies of the Font Software, and to permit persons ++to whom the Font Software is furnished to do so, subject to the following ++conditions: ++ ++The above copyright and trademark notices and this permission notice ++shall be included in all copies of one or more of the Font Software typefaces. ++ ++The Font Software may be modified, altered, or added to, and in particular ++the designs of glyphs or characters in the Fonts may be modified and ++additional glyphs or characters may be added to the Fonts, only if the ++fonts are renamed to names not containing either the words "Bitstream" ++or the word "Vera". ++ ++This License becomes null and void to the extent applicable to Fonts or ++Font Software that has been modified and is distributed under the ++"Bitstream Vera" names. ++ ++The Font Software may be sold as part of a larger software package but ++no copy of one or more of the Font Software typefaces may be sold by itself. ++ ++THE FONT SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++OR IMPLIED, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OF MERCHANTABILITY, ++FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT OF COPYRIGHT, PATENT, ++TRADEMARK, OR OTHER RIGHT. IN NO EVENT SHALL BITSTREAM OR THE GNOME ++FOUNDATION BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, INCLUDING ++ANY GENERAL, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, ++WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT ++OF THE USE OR INABILITY TO USE THE FONT SOFTWARE OR FROM OTHER DEALINGS IN ++THE FONT SOFTWARE. ++Except as contained in this notice, the names of GNOME, the GNOME ++Foundation, and Bitstream Inc., shall not be used in advertising or ++otherwise to promote the sale, use or other dealings in this Font Software ++without prior written authorization from the GNOME Foundation or ++Bitstream Inc., respectively. ++For further information, contact: fonts at gnome dot org. ++ ++AMSFonts (v. 2.2) copyright ++ ++The PostScript Type 1 implementation of the AMSFonts produced by and ++previously distributed by Blue Sky Research and Y&Y, Inc. are now freely ++available for general use. This has been accomplished through the ++cooperation ++of a consortium of scientific publishers with Blue Sky Research and Y&Y. ++Members of this consortium include: ++ ++Elsevier Science IBM Corporation Society for Industrial and Applied ++Mathematics (SIAM) Springer-Verlag American Mathematical Society (AMS) ++ ++In order to assure the authenticity of these fonts, copyright will be ++held by the American Mathematical Society. This is not meant to restrict ++in any way the legitimate use of the fonts, such as (but not limited to) ++electronic distribution of documents containing these fonts, inclusion of ++these fonts into other public domain or commercial font collections or computer ++applications, use of the outline data to create derivative fonts and/or ++faces, etc. However, the AMS does require that the AMS copyright notice be ++removed from any derivative versions of the fonts which have been altered in ++any way. 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IN NO EVENT SHALL THE ++ AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ++ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, ++ OUT OF OR IN CONNECTION WITH THE MATERIALS OR THE USE OR OTHER DEALINGS IN THE ++ MATERIALS. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% Portions Copyright Eastman Kodak Company 1991-2003 ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to libpng 1.6.39, which may be ++included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++COPYRIGHT NOTICE, DISCLAIMER, and LICENSE ++========================================= ++ ++PNG Reference Library License version 2 ++--------------------------------------- ++ ++Copyright (c) 1995-2022 The PNG Reference Library Authors. ++Copyright (c) 2018-2022 Cosmin Truta ++Copyright (c) 1998-2018 Glenn Randers-Pehrson ++Copyright (c) 1996-1997 Andreas Dilger ++Copyright (c) 1995-1996 Guy Eric Schalnat, Group 42, Inc. ++ ++The software is supplied "as is", without warranty of any kind, ++express or implied, including, without limitation, the warranties ++of merchantability, fitness for a particular purpose, title, and ++non-infringement. In no event shall the Copyright owners, or ++anyone distributing the software, be liable for any damages or ++other liability, whether in contract, tort or otherwise, arising ++from, out of, or in connection with the software, or the use or ++other dealings in the software, even if advised of the possibility ++of such damage. ++ ++Permission is hereby granted to use, copy, modify, and distribute ++this software, or portions hereof, for any purpose, without fee, ++subject to the following restrictions: ++ ++ 1. The origin of this software must not be misrepresented; you ++ must not claim that you wrote the original software. If you ++ use this software in a product, an acknowledgment in the product ++ documentation would be appreciated, but is not required. ++ ++ 2. Altered source versions must be plainly marked as such, and must ++ not be misrepresented as being the original software. ++ ++ 3. This Copyright notice may not be removed or altered from any ++ source or altered source distribution. ++ ++ ++PNG Reference Library License version 1 (for libpng 0.5 through 1.6.35) ++----------------------------------------------------------------------- ++ ++libpng versions 1.0.7, July 1, 2000, through 1.6.35, July 15, 2018 are ++Copyright (c) 2000-2002, 2004, 2006-2018 Glenn Randers-Pehrson, are ++derived from libpng-1.0.6, and are distributed according to the same ++disclaimer and license as libpng-1.0.6 with the following individuals ++added to the list of Contributing Authors: ++ ++ Simon-Pierre Cadieux ++ Eric S. Raymond ++ Mans Rullgard ++ Cosmin Truta ++ Gilles Vollant ++ James Yu ++ Mandar Sahastrabuddhe ++ Google Inc. ++ Vadim Barkov ++ ++and with the following additions to the disclaimer: ++ ++ There is no warranty against interference with your enjoyment of ++ the library or against infringement. There is no warranty that our ++ efforts or the library will fulfill any of your particular purposes ++ or needs. This library is provided with all faults, and the entire ++ risk of satisfactory quality, performance, accuracy, and effort is ++ with the user. ++ ++Some files in the "contrib" directory and some configure-generated ++files that are distributed with libpng have other copyright owners, and ++are released under other open source licenses. ++ ++libpng versions 0.97, January 1998, through 1.0.6, March 20, 2000, are ++Copyright (c) 1998-2000 Glenn Randers-Pehrson, are derived from ++libpng-0.96, and are distributed according to the same disclaimer and ++license as libpng-0.96, with the following individuals added to the ++list of Contributing Authors: ++ ++ Tom Lane ++ Glenn Randers-Pehrson ++ Willem van Schaik ++ ++libpng versions 0.89, June 1996, through 0.96, May 1997, are ++Copyright (c) 1996-1997 Andreas Dilger, are derived from libpng-0.88, ++and are distributed according to the same disclaimer and license as ++libpng-0.88, with the following individuals added to the list of ++Contributing Authors: ++ ++ John Bowler ++ Kevin Bracey ++ Sam Bushell ++ Magnus Holmgren ++ Greg Roelofs ++ Tom Tanner ++ ++Some files in the "scripts" directory have other copyright owners, ++but are released under this license. ++ ++libpng versions 0.5, May 1995, through 0.88, January 1996, are ++Copyright (c) 1995-1996 Guy Eric Schalnat, Group 42, Inc. ++ ++For the purposes of this copyright and license, "Contributing Authors" ++is defined as the following set of individuals: ++ ++ Andreas Dilger ++ Dave Martindale ++ Guy Eric Schalnat ++ Paul Schmidt ++ Tim Wegner ++ ++The PNG Reference Library is supplied "AS IS". The Contributing ++Authors and Group 42, Inc. disclaim all warranties, expressed or ++implied, including, without limitation, the warranties of ++merchantability and of fitness for any purpose. The Contributing ++Authors and Group 42, Inc. assume no liability for direct, indirect, ++incidental, special, exemplary, or consequential damages, which may ++result from the use of the PNG Reference Library, even if advised of ++the possibility of such damage. ++ ++Permission is hereby granted to use, copy, modify, and distribute this ++source code, or portions hereof, for any purpose, without fee, subject ++to the following restrictions: ++ ++ 1. The origin of this source code must not be misrepresented. ++ ++ 2. Altered versions must be plainly marked as such and must not ++ be misrepresented as being the original source. ++ ++ 3. This Copyright notice may not be removed or altered from any ++ source or altered source distribution. ++ ++The Contributing Authors and Group 42, Inc. specifically permit, ++without fee, and encourage the use of this source code as a component ++to supporting the PNG file format in commercial products. If you use ++this source code in a product, acknowledgment is not required but would ++be appreciated. ++ ++TRADEMARK: ++ ++The name "libpng" has not been registered by the Copyright owners ++as a trademark in any jurisdiction. However, because libpng has ++been distributed and maintained world-wide, continually since 1995, ++the Copyright owners claim "common-law trademark protection" in any ++jurisdiction where common-law trademark is recognized. ++ ++OSI CERTIFICATION: ++ ++Libpng is OSI Certified Open Source Software. OSI Certified Open Source is ++a certification mark of the Open Source Initiative. OSI has not addressed ++the additional disclaimers inserted at version 1.0.7. ++ ++EXPORT CONTROL: ++ ++The Copyright owner believes that the Export Control Classification ++Number (ECCN) for libpng is EAR99, which means not subject to export ++controls or International Traffic in Arms Regulations (ITAR) because ++it is open source, publicly available software, that does not contain ++any encryption software. See the EAR, paragraphs 734.3(b)(3) and ++734.7(b). ++ ++Glenn Randers-Pehrson ++glennrp at users.sourceforge.net ++July 15, 2018 ++ ++AUTHORS File Information: ++ ++PNG REFERENCE LIBRARY AUTHORS ++============================= ++ ++This is the list of PNG Reference Library ("libpng") Contributing ++Authors, for copyright and licensing purposes. ++ ++ * Andreas Dilger ++ * Cosmin Truta ++ * Dave Martindale ++ * Eric S. Raymond ++ * Gilles Vollant ++ * Glenn Randers-Pehrson ++ * Greg Roelofs ++ * Guy Eric Schalnat ++ * James Yu ++ * John Bowler ++ * Kevin Bracey ++ * Magnus Holmgren ++ * Mandar Sahastrabuddhe ++ * Mans Rullgard ++ * Matt Sarett ++ * Mike Klein ++ * Pascal Massimino ++ * Paul Schmidt ++ * Qiang Zhou ++ * Sam Bushell ++ * Samuel Williams ++ * Simon-Pierre Cadieux ++ * Tim Wegner ++ * Tom Lane ++ * Tom Tanner ++ * Vadim Barkov ++ * Willem van Schaik ++ * Zhijie Liang ++ * Arm Holdings ++ - Richard Townsend ++ * Google Inc. ++ - Dan Field ++ - Leon Scroggins III ++ - Matt Sarett ++ - Mike Klein ++ - Sami Boukortt ++ ++The build projects, the build scripts, the test scripts, and other ++files in the "ci", "projects", "scripts" and "tests" directories, have ++other copyright owners, but are released under the libpng license. ++ ++Some files in the "contrib" directory, and some tools-generated files ++that are distributed with libpng, have other copyright owners, and are ++released under other open source licenses. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to GIFLIB 5.2.1 & libungif 4.1.3, ++which may be included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++The GIFLIB distribution is Copyright (c) 1997 Eric S. Raymond ++ ++Permission is hereby granted, free of charge, to any person obtaining a copy ++of this software and associated documentation files (the "Software"), to deal ++in the Software without restriction, including without limitation the rights ++to use, copy, modify, merge, publish, distribute, sublicense, and/or sell ++copies of the Software, and to permit persons to whom the Software is ++furnished to do so, subject to the following conditions: ++ ++The above copyright notice and this permission notice shall be included in ++all copies or substantial portions of the Software. ++ ++THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE ++AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ++LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, ++OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN ++THE SOFTWARE. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Little CMS 2.11, which may be ++included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++Little CMS ++Copyright (c) 1998-2020 Marti Maria Saguer ++ ++Permission is hereby granted, free of charge, to any person obtaining a copy ++of this software and associated documentation files (the "Software"), to deal ++in the Software without restriction, including without limitation the rights ++to use, copy, modify, merge, publish, distribute, sublicense, and/or sell ++copies of the Software, and to permit persons to whom the Software is ++furnished to do so, subject to the following conditions: ++ ++The above copyright notice and this permission notice shall be included in all ++copies or substantial portions of the Software. ++ ++THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE ++AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ++LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, ++OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE ++SOFTWARE. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% Lucida is a registered trademark or trademark of Bigelow & Holmes in the ++U.S. and other countries. ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Mesa 3D Graphics Library v4.1, ++which may be included with JRE 8, JDK 8, and OpenJDK 8 source distributions. ++ ++--- begin of LICENSE --- ++ ++ Mesa 3-D Graphics Library v19.2.1 ++ ++ Copyright (C) 1999-2007 Brian Paul All Rights Reserved. ++ ++ Permission is hereby granted, free of charge, to any person obtaining a ++ copy of this software and associated documentation files (the "Software"), ++ to deal in the Software without restriction, including without limitation ++ the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ and/or sell copies of the Software, and to permit persons to whom the ++ Software is furnished to do so, subject to the following conditions: ++ ++ The above copyright notice and this permission notice shall be included ++ in all copies or substantial portions of the Software. ++ ++ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ++ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, ++ OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE ++ SOFTWARE. ++ ++Attention, Contributors ++ ++When contributing to the Mesa project you must agree to the licensing terms ++of the component to which you're contributing. ++The following section lists the primary components of the Mesa distribution ++and their respective licenses. ++Mesa Component Licenses ++ ++ ++ ++Component Location License ++------------------------------------------------------------------ ++Main Mesa code src/mesa/ MIT ++Device drivers src/mesa/drivers/* MIT, generally ++ ++Gallium code src/gallium/ MIT ++ ++Ext headers GL/glext.h Khronos ++ GL/glxext.h Khronos ++ GL/wglext.h Khronos ++ KHR/khrplatform.h Khronos ++ ++***************************************************************************** ++ ++---- ++include/GL/gl.h : ++ ++ ++ Mesa 3-D graphics library ++ ++ Copyright (C) 1999-2006 Brian Paul All Rights Reserved. ++ Copyright (C) 2009 VMware, Inc. All Rights Reserved. ++ ++ Permission is hereby granted, free of charge, to any person obtaining a ++ copy of this software and associated documentation files (the "Software"), ++ to deal in the Software without restriction, including without limitation ++ the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ and/or sell copies of the Software, and to permit persons to whom the ++ Software is furnished to do so, subject to the following conditions: ++ ++ The above copyright notice and this permission notice shall be included ++ in all copies or substantial portions of the Software. ++ ++ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ OTHER DEALINGS IN THE SOFTWARE. ++ ++ ***************************************************************************** ++ ++---- ++include/GL/glext.h ++include/GL/glxext.h ++include/GL/wglxext.h : ++ ++ ++ Copyright (c) 2013 - 2018 The Khronos Group Inc. ++ ++ Permission is hereby granted, free of charge, to any person obtaining a ++ copy of this software and/or associated documentation files (the ++ "Materials"), to deal in the Materials without restriction, including ++ without limitation the rights to use, copy, modify, merge, publish, ++ distribute, sublicense, and/or sell copies of the Materials, and to ++ permit persons to whom the Materials are furnished to do so, subject to ++ the following conditions: ++ ++ The above copyright notice and this permission notice shall be included ++ in all copies or substantial portions of the Materials. ++ ++ THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. ++ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY ++ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, ++ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE ++ MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS. ++ ++ ***************************************************************************** ++ ++---- ++include/KHR/khrplatform.h : ++ ++ Copyright (c) 2008 - 2018 The Khronos Group Inc. ++ ++ Permission is hereby granted, free of charge, to any person obtaining a ++ copy of this software and/or associated documentation files (the ++ "Materials"), to deal in the Materials without restriction, including ++ without limitation the rights to use, copy, modify, merge, publish, ++ distribute, sublicense, and/or sell copies of the Materials, and to ++ permit persons to whom the Materials are furnished to do so, subject to ++ the following conditions: ++ ++ The above copyright notice and this permission notice shall be included ++ in all copies or substantial portions of the Materials. ++ ++ THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. ++ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY ++ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, ++ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE ++ MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS. ++ ++ ***************************************************************************** ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Mozilla Network Security ++Services (NSS), which is supplied with the JDK test suite in the OpenJDK ++source code repository. It is licensed under Mozilla Public License (MPL), ++version 2.0. ++ ++The NSS libraries are supplied in executable form, built from unmodified ++NSS source code labeled with the "NSS_3_16_RTM" HG tag. ++ ++The NSS source code is available in the OpenJDK source code repository at: ++ jdk/test/sun/security/pkcs11/nss/src ++ ++The NSS libraries are available in the OpenJDK source code repository at: ++ jdk/test/sun/security/pkcs11/nss/lib ++ ++--- begin of LICENSE --- ++ ++Mozilla Public License Version 2.0 ++================================== ++ ++1. Definitions ++-------------- ++ ++1.1. "Contributor" ++ means each individual or legal entity that creates, contributes to ++ the creation of, or owns Covered Software. ++ ++1.2. "Contributor Version" ++ means the combination of the Contributions of others (if any) used ++ by a Contributor and that particular Contributor's Contribution. ++ ++1.3. "Contribution" ++ means Covered Software of a particular Contributor. ++ ++1.4. "Covered Software" ++ means Source Code Form to which the initial Contributor has attached ++ the notice in Exhibit A, the Executable Form of such Source Code ++ Form, and Modifications of such Source Code Form, in each case ++ including portions thereof. ++ ++1.5. "Incompatible With Secondary Licenses" ++ means ++ ++ (a) that the initial Contributor has attached the notice described ++ in Exhibit B to the Covered Software; or ++ ++ (b) that the Covered Software was made available under the terms of ++ version 1.1 or earlier of the License, but not also under the ++ terms of a Secondary License. ++ ++1.6. "Executable Form" ++ means any form of the work other than Source Code Form. ++ ++1.7. "Larger Work" ++ means a work that combines Covered Software with other material, in ++ a separate file or files, that is not Covered Software. ++ ++1.8. "License" ++ means this document. ++ ++1.9. "Licensable" ++ means having the right to grant, to the maximum extent possible, ++ whether at the time of the initial grant or subsequently, any and ++ all of the rights conveyed by this License. ++ ++1.10. "Modifications" ++ means any of the following: ++ ++ (a) any file in Source Code Form that results from an addition to, ++ deletion from, or modification of the contents of Covered ++ Software; or ++ ++ (b) any new file in Source Code Form that contains any Covered ++ Software. ++ ++1.11. "Patent Claims" of a Contributor ++ means any patent claim(s), including without limitation, method, ++ process, and apparatus claims, in any patent Licensable by such ++ Contributor that would be infringed, but for the grant of the ++ License, by the making, using, selling, offering for sale, having ++ made, import, or transfer of either its Contributions or its ++ Contributor Version. ++ ++1.12. "Secondary License" ++ means either the GNU General Public License, Version 2.0, the GNU ++ Lesser General Public License, Version 2.1, the GNU Affero General ++ Public License, Version 3.0, or any later versions of those ++ licenses. ++ ++1.13. "Source Code Form" ++ means the form of the work preferred for making modifications. ++ ++1.14. "You" (or "Your") ++ means an individual or a legal entity exercising rights under this ++ License. For legal entities, "You" includes any entity that ++ controls, is controlled by, or is under common control with You. For ++ purposes of this definition, "control" means (a) the power, direct ++ or indirect, to cause the direction or management of such entity, ++ whether by contract or otherwise, or (b) ownership of more than ++ fifty percent (50%) of the outstanding shares or beneficial ++ ownership of such entity. ++ ++2. License Grants and Conditions ++-------------------------------- ++ ++2.1. Grants ++ ++Each Contributor hereby grants You a world-wide, royalty-free, ++non-exclusive license: ++ ++(a) under intellectual property rights (other than patent or trademark) ++ Licensable by such Contributor to use, reproduce, make available, ++ modify, display, perform, distribute, and otherwise exploit its ++ Contributions, either on an unmodified basis, with Modifications, or ++ as part of a Larger Work; and ++ ++(b) under Patent Claims of such Contributor to make, use, sell, offer ++ for sale, have made, import, and otherwise transfer either its ++ Contributions or its Contributor Version. ++ ++2.2. Effective Date ++ ++The licenses granted in Section 2.1 with respect to any Contribution ++become effective for each Contribution on the date the Contributor first ++distributes such Contribution. ++ ++2.3. Limitations on Grant Scope ++ ++The licenses granted in this Section 2 are the only rights granted under ++this License. No additional rights or licenses will be implied from the ++distribution or licensing of Covered Software under this License. ++Notwithstanding Section 2.1(b) above, no patent license is granted by a ++Contributor: ++ ++(a) for any code that a Contributor has removed from Covered Software; ++ or ++ ++(b) for infringements caused by: (i) Your and any other third party's ++ modifications of Covered Software, or (ii) the combination of its ++ Contributions with other software (except as part of its Contributor ++ Version); or ++ ++(c) under Patent Claims infringed by Covered Software in the absence of ++ its Contributions. ++ ++This License does not grant any rights in the trademarks, service marks, ++or logos of any Contributor (except as may be necessary to comply with ++the notice requirements in Section 3.4). ++ ++2.4. Subsequent Licenses ++ ++No Contributor makes additional grants as a result of Your choice to ++distribute the Covered Software under a subsequent version of this ++License (see Section 10.2) or under the terms of a Secondary License (if ++permitted under the terms of Section 3.3). ++ ++2.5. Representation ++ ++Each Contributor represents that the Contributor believes its ++Contributions are its original creation(s) or it has sufficient rights ++to grant the rights to its Contributions conveyed by this License. ++ ++2.6. Fair Use ++ ++This License is not intended to limit any rights You have under ++applicable copyright doctrines of fair use, fair dealing, or other ++equivalents. ++ ++2.7. Conditions ++ ++Sections 3.1, 3.2, 3.3, and 3.4 are conditions of the licenses granted ++in Section 2.1. ++ ++3. Responsibilities ++------------------- ++ ++3.1. Distribution of Source Form ++ ++All distribution of Covered Software in Source Code Form, including any ++Modifications that You create or to which You contribute, must be under ++the terms of this License. You must inform recipients that the Source ++Code Form of the Covered Software is governed by the terms of this ++License, and how they can obtain a copy of this License. You may not ++attempt to alter or restrict the recipients' rights in the Source Code ++Form. ++ ++3.2. Distribution of Executable Form ++ ++If You distribute Covered Software in Executable Form then: ++ ++(a) such Covered Software must also be made available in Source Code ++ Form, as described in Section 3.1, and You must inform recipients of ++ the Executable Form how they can obtain a copy of such Source Code ++ Form by reasonable means in a timely manner, at a charge no more ++ than the cost of distribution to the recipient; and ++ ++(b) You may distribute such Executable Form under the terms of this ++ License, or sublicense it under different terms, provided that the ++ license for the Executable Form does not attempt to limit or alter ++ the recipients' rights in the Source Code Form under this License. ++ ++3.3. Distribution of a Larger Work ++ ++You may create and distribute a Larger Work under terms of Your choice, ++provided that You also comply with the requirements of this License for ++the Covered Software. If the Larger Work is a combination of Covered ++Software with a work governed by one or more Secondary Licenses, and the ++Covered Software is not Incompatible With Secondary Licenses, this ++License permits You to additionally distribute such Covered Software ++under the terms of such Secondary License(s), so that the recipient of ++the Larger Work may, at their option, further distribute the Covered ++Software under the terms of either this License or such Secondary ++License(s). ++ ++3.4. Notices ++ ++You may not remove or alter the substance of any license notices ++(including copyright notices, patent notices, disclaimers of warranty, ++or limitations of liability) contained within the Source Code Form of ++the Covered Software, except that You may alter any license notices to ++the extent required to remedy known factual inaccuracies. ++ ++3.5. Application of Additional Terms ++ ++You may choose to offer, and to charge a fee for, warranty, support, ++indemnity or liability obligations to one or more recipients of Covered ++Software. However, You may do so only on Your own behalf, and not on ++behalf of any Contributor. You must make it absolutely clear that any ++such warranty, support, indemnity, or liability obligation is offered by ++You alone, and You hereby agree to indemnify every Contributor for any ++liability incurred by such Contributor as a result of warranty, support, ++indemnity or liability terms You offer. You may include additional ++disclaimers of warranty and limitations of liability specific to any ++jurisdiction. ++ ++4. Inability to Comply Due to Statute or Regulation ++--------------------------------------------------- ++ ++If it is impossible for You to comply with any of the terms of this ++License with respect to some or all of the Covered Software due to ++statute, judicial order, or regulation then You must: (a) comply with ++the terms of this License to the maximum extent possible; and (b) ++describe the limitations and the code they affect. Such description must ++be placed in a text file included with all distributions of the Covered ++Software under this License. Except to the extent prohibited by statute ++or regulation, such description must be sufficiently detailed for a ++recipient of ordinary skill to be able to understand it. ++ ++5. Termination ++-------------- ++ ++5.1. The rights granted under this License will terminate automatically ++if You fail to comply with any of its terms. However, if You become ++compliant, then the rights granted under this License from a particular ++Contributor are reinstated (a) provisionally, unless and until such ++Contributor explicitly and finally terminates Your grants, and (b) on an ++ongoing basis, if such Contributor fails to notify You of the ++non-compliance by some reasonable means prior to 60 days after You have ++come back into compliance. Moreover, Your grants from a particular ++Contributor are reinstated on an ongoing basis if such Contributor ++notifies You of the non-compliance by some reasonable means, this is the ++first time You have received notice of non-compliance with this License ++from such Contributor, and You become compliant prior to 30 days after ++Your receipt of the notice. ++ ++5.2. If You initiate litigation against any entity by asserting a patent ++infringement claim (excluding declaratory judgment actions, ++counter-claims, and cross-claims) alleging that a Contributor Version ++directly or indirectly infringes any patent, then the rights granted to ++You by any and all Contributors for the Covered Software under Section ++2.1 of this License shall terminate. ++ ++5.3. In the event of termination under Sections 5.1 or 5.2 above, all ++end user license agreements (excluding distributors and resellers) which ++have been validly granted by You or Your distributors under this License ++prior to termination shall survive termination. ++ ++************************************************************************ ++* * ++* 6. Disclaimer of Warranty * ++* ------------------------- * ++* * ++* Covered Software is provided under this License on an "as is" * ++* basis, without warranty of any kind, either expressed, implied, or * ++* statutory, including, without limitation, warranties that the * ++* Covered Software is free of defects, merchantable, fit for a * ++* particular purpose or non-infringing. The entire risk as to the * ++* quality and performance of the Covered Software is with You. * ++* Should any Covered Software prove defective in any respect, You * ++* (not any Contributor) assume the cost of any necessary servicing, * ++* repair, or correction. This disclaimer of warranty constitutes an * ++* essential part of this License. No use of any Covered Software is * ++* authorized under this License except under this disclaimer. * ++* * ++************************************************************************ ++ ++************************************************************************ ++* * ++* 7. Limitation of Liability * ++* -------------------------- * ++* * ++* Under no circumstances and under no legal theory, whether tort * ++* (including negligence), contract, or otherwise, shall any * ++* Contributor, or anyone who distributes Covered Software as * ++* permitted above, be liable to You for any direct, indirect, * ++* special, incidental, or consequential damages of any character * ++* including, without limitation, damages for lost profits, loss of * ++* goodwill, work stoppage, computer failure or malfunction, or any * ++* and all other commercial damages or losses, even if such party * ++* shall have been informed of the possibility of such damages. This * ++* limitation of liability shall not apply to liability for death or * ++* personal injury resulting from such party's negligence to the * ++* extent applicable law prohibits such limitation. Some * ++* jurisdictions do not allow the exclusion or limitation of * ++* incidental or consequential damages, so this exclusion and * ++* limitation may not apply to You. * ++* * ++************************************************************************ ++ ++8. Litigation ++------------- ++ ++Any litigation relating to this License may be brought only in the ++courts of a jurisdiction where the defendant maintains its principal ++place of business and such litigation shall be governed by laws of that ++jurisdiction, without reference to its conflict-of-law provisions. ++Nothing in this Section shall prevent a party's ability to bring ++cross-claims or counter-claims. ++ ++9. Miscellaneous ++---------------- ++ ++This License represents the complete agreement concerning the subject ++matter hereof. If any provision of this License is held to be ++unenforceable, such provision shall be reformed only to the extent ++necessary to make it enforceable. Any law or regulation which provides ++that the language of a contract shall be construed against the drafter ++shall not be used to construe this License against a Contributor. ++ ++10. Versions of the License ++--------------------------- ++ ++10.1. New Versions ++ ++Mozilla Foundation is the license steward. Except as provided in Section ++10.3, no one other than the license steward has the right to modify or ++publish new versions of this License. Each version will be given a ++distinguishing version number. ++ ++10.2. Effect of New Versions ++ ++You may distribute the Covered Software under the terms of the version ++of the License under which You originally received the Covered Software, ++or under the terms of any subsequent version published by the license ++steward. ++ ++10.3. Modified Versions ++ ++If you create software not governed by this License, and you want to ++create a new license for such software, you may create and use a ++modified version of this License if you rename the license and remove ++any references to the name of the license steward (except to note that ++such modified license differs from this License). ++ ++10.4. Distributing Source Code Form that is Incompatible With Secondary ++Licenses ++ ++If You choose to distribute Source Code Form that is Incompatible With ++Secondary Licenses under the terms of this version of the License, the ++notice described in Exhibit B of this License must be attached. ++ ++Exhibit A - Source Code Form License Notice ++------------------------------------------- ++ ++ This Source Code Form is subject to the terms of the Mozilla Public ++ License, v. 2.0. If a copy of the MPL was not distributed with this ++ file, You can obtain one at http://mozilla.org/MPL/2.0/. ++ ++If it is not possible or desirable to put the notice in a particular ++file, then You may include the notice in a location (such as a LICENSE ++file in a relevant directory) where a recipient would be likely to look ++for such a notice. ++ ++You may add additional accurate notices of copyright ownership. ++ ++Exhibit B - "Incompatible With Secondary Licenses" Notice ++--------------------------------------------------------- ++ ++ This Source Code Form is "Incompatible With Secondary Licenses", as ++ defined by the Mozilla Public License, v. 2.0. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to PC/SC Lite v1.8.26, ++which may be included with JRE 8, JDK 8, and OpenJDK 8 on Linux and Solaris. ++ ++--- begin of LICENSE --- ++ ++Copyright (c) 1999-2003 David Corcoran ++Copyright (c) 2001-2011 Ludovic Rousseau ++All rights reserved. ++ ++Redistribution and use in source and binary forms, with or without ++modification, are permitted provided that the following conditions ++are met: ++ ++1. Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++2. Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++3. The name of the author may not be used to endorse or promote products ++ derived from this software without specific prior written permission. ++ ++Changes to this license can be made only by the copyright author with ++explicit written consent. ++ ++THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to PorterStemmer v4, which may be ++included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++See: http://tartarus.org/~martin/PorterStemmer ++ ++The software is completely free for any purpose, unless notes at the head of ++the program text indicates otherwise (which is rare). In any case, the notes ++about licensing are never more restrictive than the BSD License. ++ ++In every case where the software is not written by me (Martin Porter), this ++licensing arrangement has been endorsed by the contributor, and it is ++therefore unnecessary to ask the contributor again to confirm it. ++ ++I have not asked any contributors (or their employers, if they have them) for ++proofs that they have the right to distribute their software in this way. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Relax NG Object/Parser v.20050510, ++which may be included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++Copyright (c) Kohsuke Kawaguchi ++ ++Permission is hereby granted, free of charge, to any person obtaining a copy ++of this software and associated documentation files (the "Software"), to deal ++in the Software without restriction, including without limitation the rights ++to use, copy, modify, merge, publish, distribute, sublicense, and/or sell ++copies of the Software, and to permit persons to whom the Software is ++furnished to do so, subject to the following conditions: The above copyright ++notice and this permission notice shall be included in all copies or ++substantial portions of the Software. ++ ++THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE ++AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ++LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, ++OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE ++SOFTWARE. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to RelaxNGCC v1.12, which may be ++included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++Copyright (c) 2000-2003 Daisuke Okajima and Kohsuke Kawaguchi. ++All rights reserved. ++ ++Redistribution and use in source and binary forms, with or without ++modification, are permitted provided that the following conditions are met: ++ ++1. Redistributions of source code must retain the above copyright notice, this ++ list of conditions and the following disclaimer. ++ ++2. Redistributions in binary form must reproduce the above copyright notice, ++ this list of conditions and the following disclaimer in the documentation ++ and/or other materials provided with the distribution. ++ ++3. The end-user documentation included with the redistribution, if any, must ++ include the following acknowledgment: ++ ++ "This product includes software developed by Daisuke Okajima ++ and Kohsuke Kawaguchi (http://relaxngcc.sf.net/)." ++ ++Alternately, this acknowledgment may appear in the software itself, if and ++wherever such third-party acknowledgments normally appear. ++ ++4. The names of the copyright holders must not be used to endorse or promote ++ products derived from this software without prior written permission. For ++ written permission, please contact the copyright holders. ++ ++5. Products derived from this software may not be called "RELAXNGCC", nor may ++ "RELAXNGCC" appear in their name, without prior written permission of the ++ copyright holders. ++ ++THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESSED OR IMPLIED WARRANTIES, ++INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND ++FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.IN NO EVENT SHALL THE APACHE ++SOFTWARE FOUNDATION OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ++INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ++EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Relax NG Datatype 1.0, which ++may be included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++Copyright (c) 2005, 2010 Thai Open Source Software Center Ltd ++All rights reserved. ++ ++Redistribution and use in source and binary forms, with or without ++modification, are permitted provided that the following conditions are ++met: ++ ++ Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ Neither the names of the copyright holders nor the names of its ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++A PARTICULAR PURPOSE ARE DISCLAIMED. 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This work was made possible in ++part by the International Computer Science Institute, located at Suite 600, ++1947 Center Street, Berkeley, California 94704. Funding was partially ++provided by the National Science Foundation under grant MIP-9311980. The ++original version of this code was written as part of a project to build ++a fixed-point vector processor in collaboration with the University of ++California at Berkeley, overseen by Profs. Nelson Morgan and John Wawrzynek. ++ ++THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort ++has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT ++TIMES RESULT IN INCORRECT BEHAVIOR. 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All third party trademarks referenced herein are ++the property of their respective owners. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to UPX v3.01, which may be included ++with JRE 8 on Windows. ++ ++--- begin of LICENSE --- ++ ++Use of any of this software is governed by the terms of the license below: ++ ++ ++ ooooo ooo ooooooooo. ooooooo ooooo ++ `888' `8' `888 `Y88. `8888 d8' ++ 888 8 888 .d88' Y888..8P ++ 888 8 888ooo88P' `8888' ++ 888 8 888 .8PY888. ++ `88. .8' 888 d8' `888b ++ `YbodP' o888o o888o o88888o ++ ++ ++ The Ultimate Packer for eXecutables ++ Copyright (c) 1996-2000 Markus Oberhumer & Laszlo Molnar ++ http://wildsau.idv.uni-linz.ac.at/mfx/upx.html ++ http://www.nexus.hu/upx ++ http://upx.tsx.org ++ ++ ++PLEASE CAREFULLY READ THIS LICENSE AGREEMENT, ESPECIALLY IF YOU PLAN ++TO MODIFY THE UPX SOURCE CODE OR USE A MODIFIED UPX VERSION. ++ ++ ++ABSTRACT ++======== ++ ++ UPX and UCL are copyrighted software distributed under the terms ++ of the GNU General Public License (hereinafter the "GPL"). ++ ++ The stub which is imbedded in each UPX compressed program is part ++ of UPX and UCL, and contains code that is under our copyright. The ++ terms of the GNU General Public License still apply as compressing ++ a program is a special form of linking with our stub. ++ ++ As a special exception we grant the free usage of UPX for all ++ executables, including commercial programs. ++ See below for details and restrictions. ++ ++ ++COPYRIGHT ++========= ++ ++ UPX and UCL are copyrighted software. All rights remain with the authors. ++ ++ UPX is Copyright (C) 1996-2000 Markus Franz Xaver Johannes Oberhumer ++ UPX is Copyright (C) 1996-2000 Laszlo Molnar ++ ++ UCL is Copyright (C) 1996-2000 Markus Franz Xaver Johannes Oberhumer ++ ++ ++GNU GENERAL PUBLIC LICENSE ++========================== ++ ++ UPX and the UCL library are free software; you can redistribute them ++ and/or modify them under the terms of the GNU General Public License as ++ published by the Free Software Foundation; either version 2 of ++ the License, or (at your option) any later version. ++ ++ UPX and UCL are distributed in the hope that they will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ GNU General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with this program; see the file COPYING. ++ ++ ++SPECIAL EXCEPTION FOR COMPRESSED EXECUTABLES ++============================================ ++ ++ The stub which is imbedded in each UPX compressed program is part ++ of UPX and UCL, and contains code that is under our copyright. The ++ terms of the GNU General Public License still apply as compressing ++ a program is a special form of linking with our stub. ++ ++ Hereby Markus F.X.J. Oberhumer and Laszlo Molnar grant you special ++ permission to freely use and distribute all UPX compressed programs ++ (including commercial ones), subject to the following restrictions: ++ ++ 1. You must compress your program with a completely unmodified UPX ++ version; either with our precompiled version, or (at your option) ++ with a self compiled version of the unmodified UPX sources as ++ distributed by us. ++ 2. This also implies that the UPX stub must be completely unmodfied, i.e. ++ the stub imbedded in your compressed program must be byte-identical ++ to the stub that is produced by the official unmodified UPX version. ++ 3. The decompressor and any other code from the stub must exclusively get ++ used by the unmodified UPX stub for decompressing your program at ++ program startup. No portion of the stub may get read, copied, ++ called or otherwise get used or accessed by your program. ++ ++ ++ANNOTATIONS ++=========== ++ ++ - You can use a modified UPX version or modified UPX stub only for ++ programs that are compatible with the GNU General Public License. ++ ++ - We grant you special permission to freely use and distribute all UPX ++ compressed programs. But any modification of the UPX stub (such as, ++ but not limited to, removing our copyright string or making your ++ program non-decompressible) will immediately revoke your right to ++ use and distribute a UPX compressed program. ++ ++ - UPX is not a software protection tool; by requiring that you use ++ the unmodified UPX version for your proprietary programs we ++ make sure that any user can decompress your program. This protects ++ both you and your users as nobody can hide malicious code - ++ any program that cannot be decompressed is highly suspicious ++ by definition. ++ ++ - You can integrate all or part of UPX and UCL into projects that ++ are compatible with the GNU GPL, but obviously you cannot grant ++ any special exceptions beyond the GPL for our code in your project. ++ ++ - We want to actively support manufacturers of virus scanners and ++ similar security software. Please contact us if you would like to ++ incorporate parts of UPX or UCL into such a product. ++ ++ ++ ++Markus F.X.J. Oberhumer Laszlo Molnar ++markus.oberhumer@jk.uni-linz.ac.at ml1050@cdata.tvnet.hu ++ ++Linz, Austria, 25 Feb 2000 ++ ++Additional License(s) ++ ++The UPX license file is at http://upx.sourceforge.net/upx-license.html. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Xfree86-VidMode Extension 1.0, ++which may be included with JRE 8, JDK 8, and OpenJDK 8 on Linux and Solaris. ++ ++--- begin of LICENSE --- ++ ++Version 1.1 of XFree86 ProjectLicence. ++ ++Copyright (C) 1994-2004 The XFree86 Project, Inc. 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Scott Ananian, Michael Petter ++ ++Permission to use, copy, modify, and distribute this software and its ++documentation for any purpose and without fee is hereby granted, provided ++that the above copyright notice appear in all copies and that both the ++copyright notice and this permission notice and warranty disclaimer appear in ++supporting documentation, and that the names of the authors or their ++employers not be used in advertising or publicity pertaining to distribution of ++the software without specific, written prior permission. ++ ++The authors and their employers disclaim all warranties with regard to ++this software, including all implied warranties of merchantability and fitness. ++In no event shall the authors or their employers be liable for any special, ++indirect or consequential damages or any damages whatsoever resulting from ++loss of use, data or profits, whether in an action of contract, negligence or ++other tortious action, arising out of or in connection with the use or ++performance of this software. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to DejaVu fonts v2.34, which may be ++included with JRE 8, and JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++Fonts are (c) Bitstream (see below). DejaVu changes are in public domain. ++Glyphs imported from Arev fonts are (c) Tavmjong Bah (see below) ++ ++ ++Bitstream Vera Fonts Copyright ++------------------------------ ++ ++Copyright (c) 2003 by Bitstream, Inc. All Rights Reserved. Bitstream Vera is ++a trademark of Bitstream, Inc. ++ ++Permission is hereby granted, free of charge, to any person obtaining a copy ++of the fonts accompanying this license ("Fonts") and associated ++documentation files (the "Font Software"), to reproduce and distribute the ++Font Software, including without limitation the rights to use, copy, merge, ++publish, distribute, and/or sell copies of the Font Software, and to permit ++persons to whom the Font Software is furnished to do so, subject to the ++following conditions: ++ ++The above copyright and trademark notices and this permission notice shall ++be included in all copies of one or more of the Font Software typefaces. ++ ++The Font Software may be modified, altered, or added to, and in particular ++the designs of glyphs or characters in the Fonts may be modified and ++additional glyphs or characters may be added to the Fonts, only if the fonts ++are renamed to names not containing either the words "Bitstream" or the word ++"Vera". ++ ++This License becomes null and void to the extent applicable to Fonts or Font ++Software that has been modified and is distributed under the "Bitstream ++Vera" names. ++ ++The Font Software may be sold as part of a larger software package but no ++copy of one or more of the Font Software typefaces may be sold by itself. ++ ++THE FONT SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++OR IMPLIED, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OF MERCHANTABILITY, ++FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT OF COPYRIGHT, PATENT, ++TRADEMARK, OR OTHER RIGHT. IN NO EVENT SHALL BITSTREAM OR THE GNOME ++FOUNDATION BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, INCLUDING ++ANY GENERAL, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, ++WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF ++THE USE OR INABILITY TO USE THE FONT SOFTWARE OR FROM OTHER DEALINGS IN THE ++FONT SOFTWARE. ++ ++Except as contained in this notice, the names of Gnome, the Gnome ++Foundation, and Bitstream Inc., shall not be used in advertising or ++otherwise to promote the sale, use or other dealings in this Font Software ++without prior written authorization from the Gnome Foundation or Bitstream ++Inc., respectively. For further information, contact: fonts at gnome dot ++org. ++ ++Arev Fonts Copyright ++------------------------------ ++ ++Copyright (c) 2006 by Tavmjong Bah. All Rights Reserved. ++ ++Permission is hereby granted, free of charge, to any person obtaining ++a copy of the fonts accompanying this license ("Fonts") and ++associated documentation files (the "Font Software"), to reproduce ++and distribute the modifications to the Bitstream Vera Font Software, ++including without limitation the rights to use, copy, merge, publish, ++distribute, and/or sell copies of the Font Software, and to permit ++persons to whom the Font Software is furnished to do so, subject to ++the following conditions: ++ ++The above copyright and trademark notices and this permission notice ++shall be included in all copies of one or more of the Font Software ++typefaces. ++ ++The Font Software may be modified, altered, or added to, and in ++particular the designs of glyphs or characters in the Fonts may be ++modified and additional glyphs or characters may be added to the ++Fonts, only if the fonts are renamed to names not containing either ++the words "Tavmjong Bah" or the word "Arev". ++ ++This License becomes null and void to the extent applicable to Fonts ++or Font Software that has been modified and is distributed under the ++"Tavmjong Bah Arev" names. ++ ++The Font Software may be sold as part of a larger software package but ++no copy of one or more of the Font Software typefaces may be sold by ++itself. ++ ++THE FONT SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OF ++MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT ++OF COPYRIGHT, PATENT, TRADEMARK, OR OTHER RIGHT. IN NO EVENT SHALL ++TAVMJONG BAH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++INCLUDING ANY GENERAL, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL ++DAMAGES, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++FROM, OUT OF THE USE OR INABILITY TO USE THE FONT SOFTWARE OR FROM ++OTHER DEALINGS IN THE FONT SOFTWARE. ++ ++Except as contained in this notice, the name of Tavmjong Bah shall not ++be used in advertising or otherwise to promote the sale, use or other ++dealings in this Font Software without prior written authorization ++from Tavmjong Bah. For further information, contact: tavmjong @ free ++. fr. ++ ++TeX Gyre DJV Math ++----------------- ++Fonts are (c) Bitstream (see below). DejaVu changes are in public domain. ++ ++Math extensions done by B. Jackowski, P. Strzelczyk and P. Pianowski ++(on behalf of TeX users groups) are in public domain. ++ ++Letters imported from Euler Fraktur from AMSfonts are (c) American ++Mathematical Society (see below). ++Bitstream Vera Fonts Copyright ++Copyright (c) 2003 by Bitstream, Inc. All Rights Reserved. Bitstream Vera ++is a trademark of Bitstream, Inc. ++ ++Permission is hereby granted, free of charge, to any person obtaining a copy ++of the fonts accompanying this license ("Fonts") and associated documentation ++files (the "Font Software"), to reproduce and distribute the Font Software, ++including without limitation the rights to use, copy, merge, publish, ++distribute, and/or sell copies of the Font Software, and to permit persons ++to whom the Font Software is furnished to do so, subject to the following ++conditions: ++ ++The above copyright and trademark notices and this permission notice ++shall be included in all copies of one or more of the Font Software typefaces. ++ ++The Font Software may be modified, altered, or added to, and in particular ++the designs of glyphs or characters in the Fonts may be modified and ++additional glyphs or characters may be added to the Fonts, only if the ++fonts are renamed to names not containing either the words "Bitstream" ++or the word "Vera". ++ ++This License becomes null and void to the extent applicable to Fonts or ++Font Software that has been modified and is distributed under the ++"Bitstream Vera" names. ++ ++The Font Software may be sold as part of a larger software package but ++no copy of one or more of the Font Software typefaces may be sold by itself. ++ ++THE FONT SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++OR IMPLIED, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OF MERCHANTABILITY, ++FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT OF COPYRIGHT, PATENT, ++TRADEMARK, OR OTHER RIGHT. IN NO EVENT SHALL BITSTREAM OR THE GNOME ++FOUNDATION BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, INCLUDING ++ANY GENERAL, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, ++WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT ++OF THE USE OR INABILITY TO USE THE FONT SOFTWARE OR FROM OTHER DEALINGS IN ++THE FONT SOFTWARE. ++Except as contained in this notice, the names of GNOME, the GNOME ++Foundation, and Bitstream Inc., shall not be used in advertising or ++otherwise to promote the sale, use or other dealings in this Font Software ++without prior written authorization from the GNOME Foundation or ++Bitstream Inc., respectively. ++For further information, contact: fonts at gnome dot org. ++ ++AMSFonts (v. 2.2) copyright ++ ++The PostScript Type 1 implementation of the AMSFonts produced by and ++previously distributed by Blue Sky Research and Y&Y, Inc. are now freely ++available for general use. This has been accomplished through the ++cooperation ++of a consortium of scientific publishers with Blue Sky Research and Y&Y. ++Members of this consortium include: ++ ++Elsevier Science IBM Corporation Society for Industrial and Applied ++Mathematics (SIAM) Springer-Verlag American Mathematical Society (AMS) ++ ++In order to assure the authenticity of these fonts, copyright will be ++held by the American Mathematical Society. This is not meant to restrict ++in any way the legitimate use of the fonts, such as (but not limited to) ++electronic distribution of documents containing these fonts, inclusion of ++these fonts into other public domain or commercial font collections or computer ++applications, use of the outline data to create derivative fonts and/or ++faces, etc. However, the AMS does require that the AMS copyright notice be ++removed from any derivative versions of the fonts which have been altered in ++any way. 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Holser, Jr. ++ ++ Permission is hereby granted, free of charge, to any person obtaining ++ a copy of this software and associated documentation files (the ++ "Software"), to deal in the Software without restriction, including ++ without limitation the rights to use, copy, modify, merge, publish, ++ distribute, sublicense, and/or sell copies of the Software, and to ++ permit persons to whom the Software is furnished to do so, subject to ++ the following conditions: ++ ++ The above copyright notice and this permission notice shall be ++ included in all copies or substantial portions of the Software. ++ ++ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ NONINFRINGEMENT. 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All rights reserved. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Kerberos functionality from ++FundsXpress, INC., which may be included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++ Copyright (C) 1998 by the FundsXpress, INC. ++ ++ All rights reserved. ++ ++ Export of this software from the United States of America may require ++ a specific license from the United States Government. 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It is provided "as is" without express ++ or implied warranty. ++ ++ THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR ++ IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED ++ WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. ++ ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Kronos OpenGL headers, which may be ++included with JDK 8 and OpenJDK 8 source distributions. ++ ++--- begin of LICENSE --- ++ ++ Copyright (c) 2007 The Khronos Group Inc. ++ ++ Permission is hereby granted, free of charge, to any person obtaining a copy ++ of this software and/or associated documentation files (the "Materials"), to ++ deal in the Materials without restriction, including without limitation the ++ rights to use, copy, modify, merge, publish, distribute, sublicense, and/or ++ sell copies of the Materials, and to permit persons to whom the Materials are ++ furnished to do so, subject to the following conditions: ++ ++ The above copyright notice and this permission notice shall be included in all ++ copies or substantial portions of the Materials. ++ ++ THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE ++ AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ++ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, ++ OUT OF OR IN CONNECTION WITH THE MATERIALS OR THE USE OR OTHER DEALINGS IN THE ++ MATERIALS. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% Portions Copyright Eastman Kodak Company 1991-2003 ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to libpng 1.6.39, which may be ++included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++COPYRIGHT NOTICE, DISCLAIMER, and LICENSE ++========================================= ++ ++PNG Reference Library License version 2 ++--------------------------------------- ++ ++Copyright (c) 1995-2022 The PNG Reference Library Authors. ++Copyright (c) 2018-2022 Cosmin Truta ++Copyright (c) 1998-2018 Glenn Randers-Pehrson ++Copyright (c) 1996-1997 Andreas Dilger ++Copyright (c) 1995-1996 Guy Eric Schalnat, Group 42, Inc. ++ ++The software is supplied "as is", without warranty of any kind, ++express or implied, including, without limitation, the warranties ++of merchantability, fitness for a particular purpose, title, and ++non-infringement. In no event shall the Copyright owners, or ++anyone distributing the software, be liable for any damages or ++other liability, whether in contract, tort or otherwise, arising ++from, out of, or in connection with the software, or the use or ++other dealings in the software, even if advised of the possibility ++of such damage. ++ ++Permission is hereby granted to use, copy, modify, and distribute ++this software, or portions hereof, for any purpose, without fee, ++subject to the following restrictions: ++ ++ 1. The origin of this software must not be misrepresented; you ++ must not claim that you wrote the original software. If you ++ use this software in a product, an acknowledgment in the product ++ documentation would be appreciated, but is not required. ++ ++ 2. Altered source versions must be plainly marked as such, and must ++ not be misrepresented as being the original software. ++ ++ 3. This Copyright notice may not be removed or altered from any ++ source or altered source distribution. ++ ++ ++PNG Reference Library License version 1 (for libpng 0.5 through 1.6.35) ++----------------------------------------------------------------------- ++ ++libpng versions 1.0.7, July 1, 2000, through 1.6.35, July 15, 2018 are ++Copyright (c) 2000-2002, 2004, 2006-2018 Glenn Randers-Pehrson, are ++derived from libpng-1.0.6, and are distributed according to the same ++disclaimer and license as libpng-1.0.6 with the following individuals ++added to the list of Contributing Authors: ++ ++ Simon-Pierre Cadieux ++ Eric S. Raymond ++ Mans Rullgard ++ Cosmin Truta ++ Gilles Vollant ++ James Yu ++ Mandar Sahastrabuddhe ++ Google Inc. ++ Vadim Barkov ++ ++and with the following additions to the disclaimer: ++ ++ There is no warranty against interference with your enjoyment of ++ the library or against infringement. There is no warranty that our ++ efforts or the library will fulfill any of your particular purposes ++ or needs. This library is provided with all faults, and the entire ++ risk of satisfactory quality, performance, accuracy, and effort is ++ with the user. ++ ++Some files in the "contrib" directory and some configure-generated ++files that are distributed with libpng have other copyright owners, and ++are released under other open source licenses. ++ ++libpng versions 0.97, January 1998, through 1.0.6, March 20, 2000, are ++Copyright (c) 1998-2000 Glenn Randers-Pehrson, are derived from ++libpng-0.96, and are distributed according to the same disclaimer and ++license as libpng-0.96, with the following individuals added to the ++list of Contributing Authors: ++ ++ Tom Lane ++ Glenn Randers-Pehrson ++ Willem van Schaik ++ ++libpng versions 0.89, June 1996, through 0.96, May 1997, are ++Copyright (c) 1996-1997 Andreas Dilger, are derived from libpng-0.88, ++and are distributed according to the same disclaimer and license as ++libpng-0.88, with the following individuals added to the list of ++Contributing Authors: ++ ++ John Bowler ++ Kevin Bracey ++ Sam Bushell ++ Magnus Holmgren ++ Greg Roelofs ++ Tom Tanner ++ ++Some files in the "scripts" directory have other copyright owners, ++but are released under this license. ++ ++libpng versions 0.5, May 1995, through 0.88, January 1996, are ++Copyright (c) 1995-1996 Guy Eric Schalnat, Group 42, Inc. ++ ++For the purposes of this copyright and license, "Contributing Authors" ++is defined as the following set of individuals: ++ ++ Andreas Dilger ++ Dave Martindale ++ Guy Eric Schalnat ++ Paul Schmidt ++ Tim Wegner ++ ++The PNG Reference Library is supplied "AS IS". The Contributing ++Authors and Group 42, Inc. disclaim all warranties, expressed or ++implied, including, without limitation, the warranties of ++merchantability and of fitness for any purpose. The Contributing ++Authors and Group 42, Inc. assume no liability for direct, indirect, ++incidental, special, exemplary, or consequential damages, which may ++result from the use of the PNG Reference Library, even if advised of ++the possibility of such damage. ++ ++Permission is hereby granted to use, copy, modify, and distribute this ++source code, or portions hereof, for any purpose, without fee, subject ++to the following restrictions: ++ ++ 1. The origin of this source code must not be misrepresented. ++ ++ 2. Altered versions must be plainly marked as such and must not ++ be misrepresented as being the original source. ++ ++ 3. This Copyright notice may not be removed or altered from any ++ source or altered source distribution. ++ ++The Contributing Authors and Group 42, Inc. specifically permit, ++without fee, and encourage the use of this source code as a component ++to supporting the PNG file format in commercial products. If you use ++this source code in a product, acknowledgment is not required but would ++be appreciated. ++ ++TRADEMARK: ++ ++The name "libpng" has not been registered by the Copyright owners ++as a trademark in any jurisdiction. However, because libpng has ++been distributed and maintained world-wide, continually since 1995, ++the Copyright owners claim "common-law trademark protection" in any ++jurisdiction where common-law trademark is recognized. ++ ++OSI CERTIFICATION: ++ ++Libpng is OSI Certified Open Source Software. OSI Certified Open Source is ++a certification mark of the Open Source Initiative. OSI has not addressed ++the additional disclaimers inserted at version 1.0.7. ++ ++EXPORT CONTROL: ++ ++The Copyright owner believes that the Export Control Classification ++Number (ECCN) for libpng is EAR99, which means not subject to export ++controls or International Traffic in Arms Regulations (ITAR) because ++it is open source, publicly available software, that does not contain ++any encryption software. See the EAR, paragraphs 734.3(b)(3) and ++734.7(b). ++ ++Glenn Randers-Pehrson ++glennrp at users.sourceforge.net ++July 15, 2018 ++ ++AUTHORS File Information: ++ ++PNG REFERENCE LIBRARY AUTHORS ++============================= ++ ++This is the list of PNG Reference Library ("libpng") Contributing ++Authors, for copyright and licensing purposes. ++ ++ * Andreas Dilger ++ * Cosmin Truta ++ * Dave Martindale ++ * Eric S. Raymond ++ * Gilles Vollant ++ * Glenn Randers-Pehrson ++ * Greg Roelofs ++ * Guy Eric Schalnat ++ * James Yu ++ * John Bowler ++ * Kevin Bracey ++ * Magnus Holmgren ++ * Mandar Sahastrabuddhe ++ * Mans Rullgard ++ * Matt Sarett ++ * Mike Klein ++ * Pascal Massimino ++ * Paul Schmidt ++ * Qiang Zhou ++ * Sam Bushell ++ * Samuel Williams ++ * Simon-Pierre Cadieux ++ * Tim Wegner ++ * Tom Lane ++ * Tom Tanner ++ * Vadim Barkov ++ * Willem van Schaik ++ * Zhijie Liang ++ * Arm Holdings ++ - Richard Townsend ++ * Google Inc. ++ - Dan Field ++ - Leon Scroggins III ++ - Matt Sarett ++ - Mike Klein ++ - Sami Boukortt ++ ++The build projects, the build scripts, the test scripts, and other ++files in the "ci", "projects", "scripts" and "tests" directories, have ++other copyright owners, but are released under the libpng license. ++ ++Some files in the "contrib" directory, and some tools-generated files ++that are distributed with libpng, have other copyright owners, and are ++released under other open source licenses. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to GIFLIB 5.2.1 & libungif 4.1.3, ++which may be included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++The GIFLIB distribution is Copyright (c) 1997 Eric S. Raymond ++ ++Permission is hereby granted, free of charge, to any person obtaining a copy ++of this software and associated documentation files (the "Software"), to deal ++in the Software without restriction, including without limitation the rights ++to use, copy, modify, merge, publish, distribute, sublicense, and/or sell ++copies of the Software, and to permit persons to whom the Software is ++furnished to do so, subject to the following conditions: ++ ++The above copyright notice and this permission notice shall be included in ++all copies or substantial portions of the Software. ++ ++THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE ++AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ++LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, ++OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN ++THE SOFTWARE. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Little CMS 2.11, which may be ++included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++Little CMS ++Copyright (c) 1998-2020 Marti Maria Saguer ++ ++Permission is hereby granted, free of charge, to any person obtaining a copy ++of this software and associated documentation files (the "Software"), to deal ++in the Software without restriction, including without limitation the rights ++to use, copy, modify, merge, publish, distribute, sublicense, and/or sell ++copies of the Software, and to permit persons to whom the Software is ++furnished to do so, subject to the following conditions: ++ ++The above copyright notice and this permission notice shall be included in all ++copies or substantial portions of the Software. ++ ++THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE ++AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ++LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, ++OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE ++SOFTWARE. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% Lucida is a registered trademark or trademark of Bigelow & Holmes in the ++U.S. and other countries. ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Mesa 3D Graphics Library v4.1, ++which may be included with JRE 8, JDK 8, and OpenJDK 8 source distributions. ++ ++--- begin of LICENSE --- ++ ++ Mesa 3-D Graphics Library v19.2.1 ++ ++ Copyright (C) 1999-2007 Brian Paul All Rights Reserved. ++ ++ Permission is hereby granted, free of charge, to any person obtaining a ++ copy of this software and associated documentation files (the "Software"), ++ to deal in the Software without restriction, including without limitation ++ the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ and/or sell copies of the Software, and to permit persons to whom the ++ Software is furnished to do so, subject to the following conditions: ++ ++ The above copyright notice and this permission notice shall be included ++ in all copies or substantial portions of the Software. ++ ++ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ++ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, ++ OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE ++ SOFTWARE. ++ ++Attention, Contributors ++ ++When contributing to the Mesa project you must agree to the licensing terms ++of the component to which you're contributing. ++The following section lists the primary components of the Mesa distribution ++and their respective licenses. ++Mesa Component Licenses ++ ++ ++ ++Component Location License ++------------------------------------------------------------------ ++Main Mesa code src/mesa/ MIT ++Device drivers src/mesa/drivers/* MIT, generally ++ ++Gallium code src/gallium/ MIT ++ ++Ext headers GL/glext.h Khronos ++ GL/glxext.h Khronos ++ GL/wglext.h Khronos ++ KHR/khrplatform.h Khronos ++ ++***************************************************************************** ++ ++---- ++include/GL/gl.h : ++ ++ ++ Mesa 3-D graphics library ++ ++ Copyright (C) 1999-2006 Brian Paul All Rights Reserved. ++ Copyright (C) 2009 VMware, Inc. All Rights Reserved. ++ ++ Permission is hereby granted, free of charge, to any person obtaining a ++ copy of this software and associated documentation files (the "Software"), ++ to deal in the Software without restriction, including without limitation ++ the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ and/or sell copies of the Software, and to permit persons to whom the ++ Software is furnished to do so, subject to the following conditions: ++ ++ The above copyright notice and this permission notice shall be included ++ in all copies or substantial portions of the Software. ++ ++ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ OTHER DEALINGS IN THE SOFTWARE. ++ ++ ***************************************************************************** ++ ++---- ++include/GL/glext.h ++include/GL/glxext.h ++include/GL/wglxext.h : ++ ++ ++ Copyright (c) 2013 - 2018 The Khronos Group Inc. ++ ++ Permission is hereby granted, free of charge, to any person obtaining a ++ copy of this software and/or associated documentation files (the ++ "Materials"), to deal in the Materials without restriction, including ++ without limitation the rights to use, copy, modify, merge, publish, ++ distribute, sublicense, and/or sell copies of the Materials, and to ++ permit persons to whom the Materials are furnished to do so, subject to ++ the following conditions: ++ ++ The above copyright notice and this permission notice shall be included ++ in all copies or substantial portions of the Materials. ++ ++ THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. ++ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY ++ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, ++ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE ++ MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS. ++ ++ ***************************************************************************** ++ ++---- ++include/KHR/khrplatform.h : ++ ++ Copyright (c) 2008 - 2018 The Khronos Group Inc. ++ ++ Permission is hereby granted, free of charge, to any person obtaining a ++ copy of this software and/or associated documentation files (the ++ "Materials"), to deal in the Materials without restriction, including ++ without limitation the rights to use, copy, modify, merge, publish, ++ distribute, sublicense, and/or sell copies of the Materials, and to ++ permit persons to whom the Materials are furnished to do so, subject to ++ the following conditions: ++ ++ The above copyright notice and this permission notice shall be included ++ in all copies or substantial portions of the Materials. ++ ++ THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. ++ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY ++ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, ++ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE ++ MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS. ++ ++ ***************************************************************************** ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Mozilla Network Security ++Services (NSS), which is supplied with the JDK test suite in the OpenJDK ++source code repository. It is licensed under Mozilla Public License (MPL), ++version 2.0. ++ ++The NSS libraries are supplied in executable form, built from unmodified ++NSS source code labeled with the "NSS_3_16_RTM" HG tag. ++ ++The NSS source code is available in the OpenJDK source code repository at: ++ jdk/test/sun/security/pkcs11/nss/src ++ ++The NSS libraries are available in the OpenJDK source code repository at: ++ jdk/test/sun/security/pkcs11/nss/lib ++ ++--- begin of LICENSE --- ++ ++Mozilla Public License Version 2.0 ++================================== ++ ++1. Definitions ++-------------- ++ ++1.1. "Contributor" ++ means each individual or legal entity that creates, contributes to ++ the creation of, or owns Covered Software. ++ ++1.2. "Contributor Version" ++ means the combination of the Contributions of others (if any) used ++ by a Contributor and that particular Contributor's Contribution. ++ ++1.3. "Contribution" ++ means Covered Software of a particular Contributor. ++ ++1.4. "Covered Software" ++ means Source Code Form to which the initial Contributor has attached ++ the notice in Exhibit A, the Executable Form of such Source Code ++ Form, and Modifications of such Source Code Form, in each case ++ including portions thereof. ++ ++1.5. "Incompatible With Secondary Licenses" ++ means ++ ++ (a) that the initial Contributor has attached the notice described ++ in Exhibit B to the Covered Software; or ++ ++ (b) that the Covered Software was made available under the terms of ++ version 1.1 or earlier of the License, but not also under the ++ terms of a Secondary License. ++ ++1.6. "Executable Form" ++ means any form of the work other than Source Code Form. ++ ++1.7. "Larger Work" ++ means a work that combines Covered Software with other material, in ++ a separate file or files, that is not Covered Software. ++ ++1.8. "License" ++ means this document. ++ ++1.9. "Licensable" ++ means having the right to grant, to the maximum extent possible, ++ whether at the time of the initial grant or subsequently, any and ++ all of the rights conveyed by this License. ++ ++1.10. "Modifications" ++ means any of the following: ++ ++ (a) any file in Source Code Form that results from an addition to, ++ deletion from, or modification of the contents of Covered ++ Software; or ++ ++ (b) any new file in Source Code Form that contains any Covered ++ Software. ++ ++1.11. "Patent Claims" of a Contributor ++ means any patent claim(s), including without limitation, method, ++ process, and apparatus claims, in any patent Licensable by such ++ Contributor that would be infringed, but for the grant of the ++ License, by the making, using, selling, offering for sale, having ++ made, import, or transfer of either its Contributions or its ++ Contributor Version. ++ ++1.12. "Secondary License" ++ means either the GNU General Public License, Version 2.0, the GNU ++ Lesser General Public License, Version 2.1, the GNU Affero General ++ Public License, Version 3.0, or any later versions of those ++ licenses. ++ ++1.13. "Source Code Form" ++ means the form of the work preferred for making modifications. ++ ++1.14. "You" (or "Your") ++ means an individual or a legal entity exercising rights under this ++ License. For legal entities, "You" includes any entity that ++ controls, is controlled by, or is under common control with You. For ++ purposes of this definition, "control" means (a) the power, direct ++ or indirect, to cause the direction or management of such entity, ++ whether by contract or otherwise, or (b) ownership of more than ++ fifty percent (50%) of the outstanding shares or beneficial ++ ownership of such entity. ++ ++2. License Grants and Conditions ++-------------------------------- ++ ++2.1. Grants ++ ++Each Contributor hereby grants You a world-wide, royalty-free, ++non-exclusive license: ++ ++(a) under intellectual property rights (other than patent or trademark) ++ Licensable by such Contributor to use, reproduce, make available, ++ modify, display, perform, distribute, and otherwise exploit its ++ Contributions, either on an unmodified basis, with Modifications, or ++ as part of a Larger Work; and ++ ++(b) under Patent Claims of such Contributor to make, use, sell, offer ++ for sale, have made, import, and otherwise transfer either its ++ Contributions or its Contributor Version. ++ ++2.2. Effective Date ++ ++The licenses granted in Section 2.1 with respect to any Contribution ++become effective for each Contribution on the date the Contributor first ++distributes such Contribution. ++ ++2.3. Limitations on Grant Scope ++ ++The licenses granted in this Section 2 are the only rights granted under ++this License. No additional rights or licenses will be implied from the ++distribution or licensing of Covered Software under this License. ++Notwithstanding Section 2.1(b) above, no patent license is granted by a ++Contributor: ++ ++(a) for any code that a Contributor has removed from Covered Software; ++ or ++ ++(b) for infringements caused by: (i) Your and any other third party's ++ modifications of Covered Software, or (ii) the combination of its ++ Contributions with other software (except as part of its Contributor ++ Version); or ++ ++(c) under Patent Claims infringed by Covered Software in the absence of ++ its Contributions. ++ ++This License does not grant any rights in the trademarks, service marks, ++or logos of any Contributor (except as may be necessary to comply with ++the notice requirements in Section 3.4). ++ ++2.4. Subsequent Licenses ++ ++No Contributor makes additional grants as a result of Your choice to ++distribute the Covered Software under a subsequent version of this ++License (see Section 10.2) or under the terms of a Secondary License (if ++permitted under the terms of Section 3.3). ++ ++2.5. Representation ++ ++Each Contributor represents that the Contributor believes its ++Contributions are its original creation(s) or it has sufficient rights ++to grant the rights to its Contributions conveyed by this License. ++ ++2.6. Fair Use ++ ++This License is not intended to limit any rights You have under ++applicable copyright doctrines of fair use, fair dealing, or other ++equivalents. ++ ++2.7. Conditions ++ ++Sections 3.1, 3.2, 3.3, and 3.4 are conditions of the licenses granted ++in Section 2.1. ++ ++3. Responsibilities ++------------------- ++ ++3.1. Distribution of Source Form ++ ++All distribution of Covered Software in Source Code Form, including any ++Modifications that You create or to which You contribute, must be under ++the terms of this License. You must inform recipients that the Source ++Code Form of the Covered Software is governed by the terms of this ++License, and how they can obtain a copy of this License. You may not ++attempt to alter or restrict the recipients' rights in the Source Code ++Form. ++ ++3.2. Distribution of Executable Form ++ ++If You distribute Covered Software in Executable Form then: ++ ++(a) such Covered Software must also be made available in Source Code ++ Form, as described in Section 3.1, and You must inform recipients of ++ the Executable Form how they can obtain a copy of such Source Code ++ Form by reasonable means in a timely manner, at a charge no more ++ than the cost of distribution to the recipient; and ++ ++(b) You may distribute such Executable Form under the terms of this ++ License, or sublicense it under different terms, provided that the ++ license for the Executable Form does not attempt to limit or alter ++ the recipients' rights in the Source Code Form under this License. ++ ++3.3. Distribution of a Larger Work ++ ++You may create and distribute a Larger Work under terms of Your choice, ++provided that You also comply with the requirements of this License for ++the Covered Software. If the Larger Work is a combination of Covered ++Software with a work governed by one or more Secondary Licenses, and the ++Covered Software is not Incompatible With Secondary Licenses, this ++License permits You to additionally distribute such Covered Software ++under the terms of such Secondary License(s), so that the recipient of ++the Larger Work may, at their option, further distribute the Covered ++Software under the terms of either this License or such Secondary ++License(s). ++ ++3.4. Notices ++ ++You may not remove or alter the substance of any license notices ++(including copyright notices, patent notices, disclaimers of warranty, ++or limitations of liability) contained within the Source Code Form of ++the Covered Software, except that You may alter any license notices to ++the extent required to remedy known factual inaccuracies. ++ ++3.5. Application of Additional Terms ++ ++You may choose to offer, and to charge a fee for, warranty, support, ++indemnity or liability obligations to one or more recipients of Covered ++Software. However, You may do so only on Your own behalf, and not on ++behalf of any Contributor. You must make it absolutely clear that any ++such warranty, support, indemnity, or liability obligation is offered by ++You alone, and You hereby agree to indemnify every Contributor for any ++liability incurred by such Contributor as a result of warranty, support, ++indemnity or liability terms You offer. You may include additional ++disclaimers of warranty and limitations of liability specific to any ++jurisdiction. ++ ++4. Inability to Comply Due to Statute or Regulation ++--------------------------------------------------- ++ ++If it is impossible for You to comply with any of the terms of this ++License with respect to some or all of the Covered Software due to ++statute, judicial order, or regulation then You must: (a) comply with ++the terms of this License to the maximum extent possible; and (b) ++describe the limitations and the code they affect. Such description must ++be placed in a text file included with all distributions of the Covered ++Software under this License. Except to the extent prohibited by statute ++or regulation, such description must be sufficiently detailed for a ++recipient of ordinary skill to be able to understand it. ++ ++5. Termination ++-------------- ++ ++5.1. The rights granted under this License will terminate automatically ++if You fail to comply with any of its terms. However, if You become ++compliant, then the rights granted under this License from a particular ++Contributor are reinstated (a) provisionally, unless and until such ++Contributor explicitly and finally terminates Your grants, and (b) on an ++ongoing basis, if such Contributor fails to notify You of the ++non-compliance by some reasonable means prior to 60 days after You have ++come back into compliance. Moreover, Your grants from a particular ++Contributor are reinstated on an ongoing basis if such Contributor ++notifies You of the non-compliance by some reasonable means, this is the ++first time You have received notice of non-compliance with this License ++from such Contributor, and You become compliant prior to 30 days after ++Your receipt of the notice. ++ ++5.2. If You initiate litigation against any entity by asserting a patent ++infringement claim (excluding declaratory judgment actions, ++counter-claims, and cross-claims) alleging that a Contributor Version ++directly or indirectly infringes any patent, then the rights granted to ++You by any and all Contributors for the Covered Software under Section ++2.1 of this License shall terminate. ++ ++5.3. In the event of termination under Sections 5.1 or 5.2 above, all ++end user license agreements (excluding distributors and resellers) which ++have been validly granted by You or Your distributors under this License ++prior to termination shall survive termination. ++ ++************************************************************************ ++* * ++* 6. Disclaimer of Warranty * ++* ------------------------- * ++* * ++* Covered Software is provided under this License on an "as is" * ++* basis, without warranty of any kind, either expressed, implied, or * ++* statutory, including, without limitation, warranties that the * ++* Covered Software is free of defects, merchantable, fit for a * ++* particular purpose or non-infringing. The entire risk as to the * ++* quality and performance of the Covered Software is with You. * ++* Should any Covered Software prove defective in any respect, You * ++* (not any Contributor) assume the cost of any necessary servicing, * ++* repair, or correction. This disclaimer of warranty constitutes an * ++* essential part of this License. No use of any Covered Software is * ++* authorized under this License except under this disclaimer. * ++* * ++************************************************************************ ++ ++************************************************************************ ++* * ++* 7. Limitation of Liability * ++* -------------------------- * ++* * ++* Under no circumstances and under no legal theory, whether tort * ++* (including negligence), contract, or otherwise, shall any * ++* Contributor, or anyone who distributes Covered Software as * ++* permitted above, be liable to You for any direct, indirect, * ++* special, incidental, or consequential damages of any character * ++* including, without limitation, damages for lost profits, loss of * ++* goodwill, work stoppage, computer failure or malfunction, or any * ++* and all other commercial damages or losses, even if such party * ++* shall have been informed of the possibility of such damages. This * ++* limitation of liability shall not apply to liability for death or * ++* personal injury resulting from such party's negligence to the * ++* extent applicable law prohibits such limitation. Some * ++* jurisdictions do not allow the exclusion or limitation of * ++* incidental or consequential damages, so this exclusion and * ++* limitation may not apply to You. * ++* * ++************************************************************************ ++ ++8. Litigation ++------------- ++ ++Any litigation relating to this License may be brought only in the ++courts of a jurisdiction where the defendant maintains its principal ++place of business and such litigation shall be governed by laws of that ++jurisdiction, without reference to its conflict-of-law provisions. ++Nothing in this Section shall prevent a party's ability to bring ++cross-claims or counter-claims. ++ ++9. Miscellaneous ++---------------- ++ ++This License represents the complete agreement concerning the subject ++matter hereof. If any provision of this License is held to be ++unenforceable, such provision shall be reformed only to the extent ++necessary to make it enforceable. Any law or regulation which provides ++that the language of a contract shall be construed against the drafter ++shall not be used to construe this License against a Contributor. ++ ++10. Versions of the License ++--------------------------- ++ ++10.1. New Versions ++ ++Mozilla Foundation is the license steward. Except as provided in Section ++10.3, no one other than the license steward has the right to modify or ++publish new versions of this License. Each version will be given a ++distinguishing version number. ++ ++10.2. Effect of New Versions ++ ++You may distribute the Covered Software under the terms of the version ++of the License under which You originally received the Covered Software, ++or under the terms of any subsequent version published by the license ++steward. ++ ++10.3. Modified Versions ++ ++If you create software not governed by this License, and you want to ++create a new license for such software, you may create and use a ++modified version of this License if you rename the license and remove ++any references to the name of the license steward (except to note that ++such modified license differs from this License). ++ ++10.4. Distributing Source Code Form that is Incompatible With Secondary ++Licenses ++ ++If You choose to distribute Source Code Form that is Incompatible With ++Secondary Licenses under the terms of this version of the License, the ++notice described in Exhibit B of this License must be attached. ++ ++Exhibit A - Source Code Form License Notice ++------------------------------------------- ++ ++ This Source Code Form is subject to the terms of the Mozilla Public ++ License, v. 2.0. If a copy of the MPL was not distributed with this ++ file, You can obtain one at http://mozilla.org/MPL/2.0/. ++ ++If it is not possible or desirable to put the notice in a particular ++file, then You may include the notice in a location (such as a LICENSE ++file in a relevant directory) where a recipient would be likely to look ++for such a notice. ++ ++You may add additional accurate notices of copyright ownership. ++ ++Exhibit B - "Incompatible With Secondary Licenses" Notice ++--------------------------------------------------------- ++ ++ This Source Code Form is "Incompatible With Secondary Licenses", as ++ defined by the Mozilla Public License, v. 2.0. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to PC/SC Lite v1.8.26, ++which may be included with JRE 8, JDK 8, and OpenJDK 8 on Linux and Solaris. ++ ++--- begin of LICENSE --- ++ ++Copyright (c) 1999-2003 David Corcoran ++Copyright (c) 2001-2011 Ludovic Rousseau ++All rights reserved. ++ ++Redistribution and use in source and binary forms, with or without ++modification, are permitted provided that the following conditions ++are met: ++ ++1. Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++2. Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++3. The name of the author may not be used to endorse or promote products ++ derived from this software without specific prior written permission. ++ ++Changes to this license can be made only by the copyright author with ++explicit written consent. ++ ++THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to PorterStemmer v4, which may be ++included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++See: http://tartarus.org/~martin/PorterStemmer ++ ++The software is completely free for any purpose, unless notes at the head of ++the program text indicates otherwise (which is rare). In any case, the notes ++about licensing are never more restrictive than the BSD License. ++ ++In every case where the software is not written by me (Martin Porter), this ++licensing arrangement has been endorsed by the contributor, and it is ++therefore unnecessary to ask the contributor again to confirm it. ++ ++I have not asked any contributors (or their employers, if they have them) for ++proofs that they have the right to distribute their software in this way. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Relax NG Object/Parser v.20050510, ++which may be included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++Copyright (c) Kohsuke Kawaguchi ++ ++Permission is hereby granted, free of charge, to any person obtaining a copy ++of this software and associated documentation files (the "Software"), to deal ++in the Software without restriction, including without limitation the rights ++to use, copy, modify, merge, publish, distribute, sublicense, and/or sell ++copies of the Software, and to permit persons to whom the Software is ++furnished to do so, subject to the following conditions: The above copyright ++notice and this permission notice shall be included in all copies or ++substantial portions of the Software. ++ ++THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE ++AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ++LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, ++OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE ++SOFTWARE. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to RelaxNGCC v1.12, which may be ++included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++Copyright (c) 2000-2003 Daisuke Okajima and Kohsuke Kawaguchi. ++All rights reserved. ++ ++Redistribution and use in source and binary forms, with or without ++modification, are permitted provided that the following conditions are met: ++ ++1. Redistributions of source code must retain the above copyright notice, this ++ list of conditions and the following disclaimer. ++ ++2. Redistributions in binary form must reproduce the above copyright notice, ++ this list of conditions and the following disclaimer in the documentation ++ and/or other materials provided with the distribution. ++ ++3. The end-user documentation included with the redistribution, if any, must ++ include the following acknowledgment: ++ ++ "This product includes software developed by Daisuke Okajima ++ and Kohsuke Kawaguchi (http://relaxngcc.sf.net/)." ++ ++Alternately, this acknowledgment may appear in the software itself, if and ++wherever such third-party acknowledgments normally appear. ++ ++4. The names of the copyright holders must not be used to endorse or promote ++ products derived from this software without prior written permission. For ++ written permission, please contact the copyright holders. ++ ++5. Products derived from this software may not be called "RELAXNGCC", nor may ++ "RELAXNGCC" appear in their name, without prior written permission of the ++ copyright holders. ++ ++THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESSED OR IMPLIED WARRANTIES, ++INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND ++FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.IN NO EVENT SHALL THE APACHE ++SOFTWARE FOUNDATION OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ++INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ++EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Relax NG Datatype 1.0, which ++may be included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++Copyright (c) 2005, 2010 Thai Open Source Software Center Ltd ++All rights reserved. ++ ++Redistribution and use in source and binary forms, with or without ++modification, are permitted provided that the following conditions are ++met: ++ ++ Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ Neither the names of the copyright holders nor the names of its ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR ++CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++--- end of LICENSE --- ++ ++-------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to SoftFloat version 2b, which may be ++included with JRE 8, JDK 8, and OpenJDK 8 on Linux/ARM. ++ ++--- begin of LICENSE --- ++ ++Use of any of this software is governed by the terms of the license below: ++ ++SoftFloat was written by me, John R. Hauser. This work was made possible in ++part by the International Computer Science Institute, located at Suite 600, ++1947 Center Street, Berkeley, California 94704. Funding was partially ++provided by the National Science Foundation under grant MIP-9311980. The ++original version of this code was written as part of a project to build ++a fixed-point vector processor in collaboration with the University of ++California at Berkeley, overseen by Profs. Nelson Morgan and John Wawrzynek. ++ ++THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort ++has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT ++TIMES RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO ++PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL ++LOSSES, COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO ++FURTHERMORE EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER ++SCIENCE INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES, ++COSTS, OR OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE ++SOFTWARE. ++ ++Derivative works are acceptable, even for commercial purposes, provided ++that the minimal documentation requirements stated in the source code are ++satisfied. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Sparkle 1.5, ++which may be included with JRE 8 on Mac OS X. ++ ++--- begin of LICENSE --- ++ ++Copyright (c) 2012 Sparkle.org and Andy Matuschak ++ ++Permission is hereby granted, free of charge, to any person obtaining a copy ++of this software and associated documentation files (the "Software"), to deal ++in the Software without restriction, including without limitation the rights ++to use, copy, modify, merge, publish, distribute, sublicense, and/or sell ++copies of the Software, and to permit persons to whom the Software is ++furnished to do so, subject to the following conditions: ++ ++The above copyright notice and this permission notice shall be included in all ++copies or substantial portions of the Software. ++ ++THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE ++AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ++LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, ++OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE ++SOFTWARE. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% Portions licensed from Taligent, Inc. ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Thai Dictionary, which may be ++included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++Copyright (C) 1982 The Royal Institute, Thai Royal Government. ++ ++Copyright (C) 1998 National Electronics and Computer Technology Center, ++National Science and Technology Development Agency, ++Ministry of Science Technology and Environment, ++Thai Royal Government. ++ ++Permission is hereby granted, free of charge, to any person obtaining a copy ++of this software and associated documentation files (the "Software"), to deal ++in the Software without restriction, including without limitation the rights ++to use, copy, modify, merge, publish, distribute, sublicense, and/or sell ++copies of the Software, and to permit persons to whom the Software is ++furnished to do so, subject to the following conditions: ++ ++The above copyright notice and this permission notice shall be included in all ++copies or substantial portions of the Software. ++ ++THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE ++AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ++LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, ++OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE ++SOFTWARE. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Unicode 6.2.0 & CLDR 21.0.1 ++which may be included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++Unicode Terms of Use ++ ++For the general privacy policy governing access to this site, see the Unicode ++Privacy Policy. For trademark usage, see the Unicode?? Consortium Name and ++Trademark Usage Policy. ++ ++A. Unicode Copyright. ++ 1. Copyright ?? 1991-2013 Unicode, Inc. All rights reserved. ++ ++ 2. Certain documents and files on this website contain a legend indicating ++ that "Modification is permitted." Any person is hereby authorized, ++ without fee, to modify such documents and files to create derivative ++ works conforming to the Unicode?? Standard, subject to Terms and ++ Conditions herein. ++ ++ 3. Any person is hereby authorized, without fee, to view, use, reproduce, ++ and distribute all documents and files solely for informational ++ purposes in the creation of products supporting the Unicode Standard, ++ subject to the Terms and Conditions herein. ++ ++ 4. Further specifications of rights and restrictions pertaining to the use ++ of the particular set of data files known as the "Unicode Character ++ Database" can be found in Exhibit 1. ++ ++ 5. Each version of the Unicode Standard has further specifications of ++ rights and restrictions of use. For the book editions (Unicode 5.0 and ++ earlier), these are found on the back of the title page. The online ++ code charts carry specific restrictions. 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For Software, in accordance with FAR 12-212 or ++ DFARS 227-7202, as applicable, use, duplication or disclosure by the ++ Government is subject to the restrictions set forth in this Agreement. ++ ++C. Warranties and Disclaimers. ++ 1. This publication and/or website may include technical or typographical ++ errors or other inaccuracies . Changes are periodically added to the ++ information herein; these changes will be incorporated in new editions ++ of the publication and/or website. Unicode may make improvements and/or ++ changes in the product(s) and/or program(s) described in this ++ publication and/or website at any time. ++ ++ 2. If this file has been purchased on magnetic or optical media from ++ Unicode, Inc. the sole and exclusive remedy for any claim will be ++ exchange of the defective media within ninety (90) days of original ++ purchase. ++ ++ 3. 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All third party trademarks referenced herein are ++the property of their respective owners. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to UPX v3.01, which may be included ++with JRE 8 on Windows. ++ ++--- begin of LICENSE --- ++ ++Use of any of this software is governed by the terms of the license below: ++ ++ ++ ooooo ooo ooooooooo. ooooooo ooooo ++ `888' `8' `888 `Y88. `8888 d8' ++ 888 8 888 .d88' Y888..8P ++ 888 8 888ooo88P' `8888' ++ 888 8 888 .8PY888. ++ `88. .8' 888 d8' `888b ++ `YbodP' o888o o888o o88888o ++ ++ ++ The Ultimate Packer for eXecutables ++ Copyright (c) 1996-2000 Markus Oberhumer & Laszlo Molnar ++ http://wildsau.idv.uni-linz.ac.at/mfx/upx.html ++ http://www.nexus.hu/upx ++ http://upx.tsx.org ++ ++ ++PLEASE CAREFULLY READ THIS LICENSE AGREEMENT, ESPECIALLY IF YOU PLAN ++TO MODIFY THE UPX SOURCE CODE OR USE A MODIFIED UPX VERSION. ++ ++ ++ABSTRACT ++======== ++ ++ UPX and UCL are copyrighted software distributed under the terms ++ of the GNU General Public License (hereinafter the "GPL"). ++ ++ The stub which is imbedded in each UPX compressed program is part ++ of UPX and UCL, and contains code that is under our copyright. The ++ terms of the GNU General Public License still apply as compressing ++ a program is a special form of linking with our stub. ++ ++ As a special exception we grant the free usage of UPX for all ++ executables, including commercial programs. ++ See below for details and restrictions. ++ ++ ++COPYRIGHT ++========= ++ ++ UPX and UCL are copyrighted software. All rights remain with the authors. ++ ++ UPX is Copyright (C) 1996-2000 Markus Franz Xaver Johannes Oberhumer ++ UPX is Copyright (C) 1996-2000 Laszlo Molnar ++ ++ UCL is Copyright (C) 1996-2000 Markus Franz Xaver Johannes Oberhumer ++ ++ ++GNU GENERAL PUBLIC LICENSE ++========================== ++ ++ UPX and the UCL library are free software; you can redistribute them ++ and/or modify them under the terms of the GNU General Public License as ++ published by the Free Software Foundation; either version 2 of ++ the License, or (at your option) any later version. ++ ++ UPX and UCL are distributed in the hope that they will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ GNU General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with this program; see the file COPYING. ++ ++ ++SPECIAL EXCEPTION FOR COMPRESSED EXECUTABLES ++============================================ ++ ++ The stub which is imbedded in each UPX compressed program is part ++ of UPX and UCL, and contains code that is under our copyright. The ++ terms of the GNU General Public License still apply as compressing ++ a program is a special form of linking with our stub. ++ ++ Hereby Markus F.X.J. Oberhumer and Laszlo Molnar grant you special ++ permission to freely use and distribute all UPX compressed programs ++ (including commercial ones), subject to the following restrictions: ++ ++ 1. You must compress your program with a completely unmodified UPX ++ version; either with our precompiled version, or (at your option) ++ with a self compiled version of the unmodified UPX sources as ++ distributed by us. ++ 2. This also implies that the UPX stub must be completely unmodfied, i.e. ++ the stub imbedded in your compressed program must be byte-identical ++ to the stub that is produced by the official unmodified UPX version. ++ 3. The decompressor and any other code from the stub must exclusively get ++ used by the unmodified UPX stub for decompressing your program at ++ program startup. No portion of the stub may get read, copied, ++ called or otherwise get used or accessed by your program. ++ ++ ++ANNOTATIONS ++=========== ++ ++ - You can use a modified UPX version or modified UPX stub only for ++ programs that are compatible with the GNU General Public License. ++ ++ - We grant you special permission to freely use and distribute all UPX ++ compressed programs. But any modification of the UPX stub (such as, ++ but not limited to, removing our copyright string or making your ++ program non-decompressible) will immediately revoke your right to ++ use and distribute a UPX compressed program. ++ ++ - UPX is not a software protection tool; by requiring that you use ++ the unmodified UPX version for your proprietary programs we ++ make sure that any user can decompress your program. This protects ++ both you and your users as nobody can hide malicious code - ++ any program that cannot be decompressed is highly suspicious ++ by definition. ++ ++ - You can integrate all or part of UPX and UCL into projects that ++ are compatible with the GNU GPL, but obviously you cannot grant ++ any special exceptions beyond the GPL for our code in your project. ++ ++ - We want to actively support manufacturers of virus scanners and ++ similar security software. Please contact us if you would like to ++ incorporate parts of UPX or UCL into such a product. ++ ++ ++ ++Markus F.X.J. Oberhumer Laszlo Molnar ++markus.oberhumer@jk.uni-linz.ac.at ml1050@cdata.tvnet.hu ++ ++Linz, Austria, 25 Feb 2000 ++ ++Additional License(s) ++ ++The UPX license file is at http://upx.sourceforge.net/upx-license.html. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Xfree86-VidMode Extension 1.0, ++which may be included with JRE 8, JDK 8, and OpenJDK 8 on Linux and Solaris. ++ ++--- begin of LICENSE --- ++ ++Version 1.1 of XFree86 ProjectLicence. ++ ++Copyright (C) 1994-2004 The XFree86 Project, Inc. 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DejaVu changes are in public domain. ++Glyphs imported from Arev fonts are (c) Tavmjong Bah (see below) ++ ++ ++Bitstream Vera Fonts Copyright ++------------------------------ ++ ++Copyright (c) 2003 by Bitstream, Inc. All Rights Reserved. Bitstream Vera is ++a trademark of Bitstream, Inc. ++ ++Permission is hereby granted, free of charge, to any person obtaining a copy ++of the fonts accompanying this license ("Fonts") and associated ++documentation files (the "Font Software"), to reproduce and distribute the ++Font Software, including without limitation the rights to use, copy, merge, ++publish, distribute, and/or sell copies of the Font Software, and to permit ++persons to whom the Font Software is furnished to do so, subject to the ++following conditions: ++ ++The above copyright and trademark notices and this permission notice shall ++be included in all copies of one or more of the Font Software typefaces. ++ ++The Font Software may be modified, altered, or added to, and in particular ++the designs of glyphs or characters in the Fonts may be modified and ++additional glyphs or characters may be added to the Fonts, only if the fonts ++are renamed to names not containing either the words "Bitstream" or the word ++"Vera". ++ ++This License becomes null and void to the extent applicable to Fonts or Font ++Software that has been modified and is distributed under the "Bitstream ++Vera" names. ++ ++The Font Software may be sold as part of a larger software package but no ++copy of one or more of the Font Software typefaces may be sold by itself. ++ ++THE FONT SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++OR IMPLIED, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OF MERCHANTABILITY, ++FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT OF COPYRIGHT, PATENT, ++TRADEMARK, OR OTHER RIGHT. IN NO EVENT SHALL BITSTREAM OR THE GNOME ++FOUNDATION BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, INCLUDING ++ANY GENERAL, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, ++WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF ++THE USE OR INABILITY TO USE THE FONT SOFTWARE OR FROM OTHER DEALINGS IN THE ++FONT SOFTWARE. ++ ++Except as contained in this notice, the names of Gnome, the Gnome ++Foundation, and Bitstream Inc., shall not be used in advertising or ++otherwise to promote the sale, use or other dealings in this Font Software ++without prior written authorization from the Gnome Foundation or Bitstream ++Inc., respectively. For further information, contact: fonts at gnome dot ++org. ++ ++Arev Fonts Copyright ++------------------------------ ++ ++Copyright (c) 2006 by Tavmjong Bah. All Rights Reserved. ++ ++Permission is hereby granted, free of charge, to any person obtaining ++a copy of the fonts accompanying this license ("Fonts") and ++associated documentation files (the "Font Software"), to reproduce ++and distribute the modifications to the Bitstream Vera Font Software, ++including without limitation the rights to use, copy, merge, publish, ++distribute, and/or sell copies of the Font Software, and to permit ++persons to whom the Font Software is furnished to do so, subject to ++the following conditions: ++ ++The above copyright and trademark notices and this permission notice ++shall be included in all copies of one or more of the Font Software ++typefaces. ++ ++The Font Software may be modified, altered, or added to, and in ++particular the designs of glyphs or characters in the Fonts may be ++modified and additional glyphs or characters may be added to the ++Fonts, only if the fonts are renamed to names not containing either ++the words "Tavmjong Bah" or the word "Arev". ++ ++This License becomes null and void to the extent applicable to Fonts ++or Font Software that has been modified and is distributed under the ++"Tavmjong Bah Arev" names. ++ ++The Font Software may be sold as part of a larger software package but ++no copy of one or more of the Font Software typefaces may be sold by ++itself. ++ ++THE FONT SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OF ++MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT ++OF COPYRIGHT, PATENT, TRADEMARK, OR OTHER RIGHT. IN NO EVENT SHALL ++TAVMJONG BAH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++INCLUDING ANY GENERAL, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL ++DAMAGES, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++FROM, OUT OF THE USE OR INABILITY TO USE THE FONT SOFTWARE OR FROM ++OTHER DEALINGS IN THE FONT SOFTWARE. ++ ++Except as contained in this notice, the name of Tavmjong Bah shall not ++be used in advertising or otherwise to promote the sale, use or other ++dealings in this Font Software without prior written authorization ++from Tavmjong Bah. For further information, contact: tavmjong @ free ++. fr. ++ ++TeX Gyre DJV Math ++----------------- ++Fonts are (c) Bitstream (see below). DejaVu changes are in public domain. ++ ++Math extensions done by B. Jackowski, P. Strzelczyk and P. Pianowski ++(on behalf of TeX users groups) are in public domain. ++ ++Letters imported from Euler Fraktur from AMSfonts are (c) American ++Mathematical Society (see below). ++Bitstream Vera Fonts Copyright ++Copyright (c) 2003 by Bitstream, Inc. All Rights Reserved. Bitstream Vera ++is a trademark of Bitstream, Inc. ++ ++Permission is hereby granted, free of charge, to any person obtaining a copy ++of the fonts accompanying this license ("Fonts") and associated documentation ++files (the "Font Software"), to reproduce and distribute the Font Software, ++including without limitation the rights to use, copy, merge, publish, ++distribute, and/or sell copies of the Font Software, and to permit persons ++to whom the Font Software is furnished to do so, subject to the following ++conditions: ++ ++The above copyright and trademark notices and this permission notice ++shall be included in all copies of one or more of the Font Software typefaces. ++ ++The Font Software may be modified, altered, or added to, and in particular ++the designs of glyphs or characters in the Fonts may be modified and ++additional glyphs or characters may be added to the Fonts, only if the ++fonts are renamed to names not containing either the words "Bitstream" ++or the word "Vera". ++ ++This License becomes null and void to the extent applicable to Fonts or ++Font Software that has been modified and is distributed under the ++"Bitstream Vera" names. ++ ++The Font Software may be sold as part of a larger software package but ++no copy of one or more of the Font Software typefaces may be sold by itself. ++ ++THE FONT SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++OR IMPLIED, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OF MERCHANTABILITY, ++FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT OF COPYRIGHT, PATENT, ++TRADEMARK, OR OTHER RIGHT. IN NO EVENT SHALL BITSTREAM OR THE GNOME ++FOUNDATION BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, INCLUDING ++ANY GENERAL, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, ++WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT ++OF THE USE OR INABILITY TO USE THE FONT SOFTWARE OR FROM OTHER DEALINGS IN ++THE FONT SOFTWARE. ++Except as contained in this notice, the names of GNOME, the GNOME ++Foundation, and Bitstream Inc., shall not be used in advertising or ++otherwise to promote the sale, use or other dealings in this Font Software ++without prior written authorization from the GNOME Foundation or ++Bitstream Inc., respectively. ++For further information, contact: fonts at gnome dot org. ++ ++AMSFonts (v. 2.2) copyright ++ ++The PostScript Type 1 implementation of the AMSFonts produced by and ++previously distributed by Blue Sky Research and Y&Y, Inc. are now freely ++available for general use. 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IN ++NO EVENT SHALL THE COPYRIGHT HOLDER OR HOLDERS INCLUDED IN THIS NOTICE BE ++LIABLE FOR ANY CLAIM, OR ANY SPECIAL INDIRECT OR CONSEQUENTIAL DAMAGES, OR ANY ++DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ++ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN ++CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. ++ ++Except as contained in this notice, the name of a copyright holder shall not ++be used in advertising or otherwise to promote the sale, use or other dealings ++in this Software without prior written authorization of the copyright holder. ++All trademarks and registered trademarks mentioned herein are the property of ++their respective owners. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to IJG JPEG 6b, which may be ++included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++This software is copyright (C) 1991-1998, Thomas G. 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IN NO EVENT SHALL THE ++AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ++LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, ++OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE ++SOFTWARE. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to JOpt-Simple v3.0, which may be ++included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++ Copyright (c) 2004-2009 Paul R. Holser, Jr. ++ ++ Permission is hereby granted, free of charge, to any person obtaining ++ a copy of this software and associated documentation files (the ++ "Software"), to deal in the Software without restriction, including ++ without limitation the rights to use, copy, modify, merge, publish, ++ distribute, sublicense, and/or sell copies of the Software, and to ++ permit persons to whom the Software is furnished to do so, subject to ++ the following conditions: ++ ++ The above copyright notice and this permission notice shall be ++ included in all copies or substantial portions of the Software. ++ ++ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE ++ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION ++ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION ++ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ ++--- end of LICENSE --- ++ ++-------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Kerberos functionality, which ++which may be included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++ (C) Copyright IBM Corp. 1999 All Rights Reserved. ++ Copyright 1997 The Open Group Research Institute. All rights reserved. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Kerberos functionality from ++FundsXpress, INC., which may be included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++ Copyright (C) 1998 by the FundsXpress, INC. ++ ++ All rights reserved. ++ ++ Export of this software from the United States of America may require ++ a specific license from the United States Government. It is the ++ responsibility of any person or organization contemplating export to ++ obtain such a license before exporting. ++ ++ WITHIN THAT CONSTRAINT, permission to use, copy, modify, and ++ distribute this software and its documentation for any purpose and ++ without fee is hereby granted, provided that the above copyright ++ notice appear in all copies and that both that copyright notice and ++ this permission notice appear in supporting documentation, and that ++ the name of FundsXpress. not be used in advertising or publicity pertaining ++ to distribution of the software without specific, written prior ++ permission. FundsXpress makes no representations about the suitability of ++ this software for any purpose. It is provided "as is" without express ++ or implied warranty. ++ ++ THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR ++ IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED ++ WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. ++ ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Kronos OpenGL headers, which may be ++included with JDK 8 and OpenJDK 8 source distributions. ++ ++--- begin of LICENSE --- ++ ++ Copyright (c) 2007 The Khronos Group Inc. ++ ++ Permission is hereby granted, free of charge, to any person obtaining a copy ++ of this software and/or associated documentation files (the "Materials"), to ++ deal in the Materials without restriction, including without limitation the ++ rights to use, copy, modify, merge, publish, distribute, sublicense, and/or ++ sell copies of the Materials, and to permit persons to whom the Materials are ++ furnished to do so, subject to the following conditions: ++ ++ The above copyright notice and this permission notice shall be included in all ++ copies or substantial portions of the Materials. ++ ++ THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE ++ AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ++ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, ++ OUT OF OR IN CONNECTION WITH THE MATERIALS OR THE USE OR OTHER DEALINGS IN THE ++ MATERIALS. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% Portions Copyright Eastman Kodak Company 1991-2003 ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to libpng 1.6.39, which may be ++included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++COPYRIGHT NOTICE, DISCLAIMER, and LICENSE ++========================================= ++ ++PNG Reference Library License version 2 ++--------------------------------------- ++ ++Copyright (c) 1995-2022 The PNG Reference Library Authors. ++Copyright (c) 2018-2022 Cosmin Truta ++Copyright (c) 1998-2018 Glenn Randers-Pehrson ++Copyright (c) 1996-1997 Andreas Dilger ++Copyright (c) 1995-1996 Guy Eric Schalnat, Group 42, Inc. ++ ++The software is supplied "as is", without warranty of any kind, ++express or implied, including, without limitation, the warranties ++of merchantability, fitness for a particular purpose, title, and ++non-infringement. In no event shall the Copyright owners, or ++anyone distributing the software, be liable for any damages or ++other liability, whether in contract, tort or otherwise, arising ++from, out of, or in connection with the software, or the use or ++other dealings in the software, even if advised of the possibility ++of such damage. ++ ++Permission is hereby granted to use, copy, modify, and distribute ++this software, or portions hereof, for any purpose, without fee, ++subject to the following restrictions: ++ ++ 1. The origin of this software must not be misrepresented; you ++ must not claim that you wrote the original software. If you ++ use this software in a product, an acknowledgment in the product ++ documentation would be appreciated, but is not required. ++ ++ 2. Altered source versions must be plainly marked as such, and must ++ not be misrepresented as being the original software. ++ ++ 3. This Copyright notice may not be removed or altered from any ++ source or altered source distribution. ++ ++ ++PNG Reference Library License version 1 (for libpng 0.5 through 1.6.35) ++----------------------------------------------------------------------- ++ ++libpng versions 1.0.7, July 1, 2000, through 1.6.35, July 15, 2018 are ++Copyright (c) 2000-2002, 2004, 2006-2018 Glenn Randers-Pehrson, are ++derived from libpng-1.0.6, and are distributed according to the same ++disclaimer and license as libpng-1.0.6 with the following individuals ++added to the list of Contributing Authors: ++ ++ Simon-Pierre Cadieux ++ Eric S. Raymond ++ Mans Rullgard ++ Cosmin Truta ++ Gilles Vollant ++ James Yu ++ Mandar Sahastrabuddhe ++ Google Inc. ++ Vadim Barkov ++ ++and with the following additions to the disclaimer: ++ ++ There is no warranty against interference with your enjoyment of ++ the library or against infringement. There is no warranty that our ++ efforts or the library will fulfill any of your particular purposes ++ or needs. This library is provided with all faults, and the entire ++ risk of satisfactory quality, performance, accuracy, and effort is ++ with the user. ++ ++Some files in the "contrib" directory and some configure-generated ++files that are distributed with libpng have other copyright owners, and ++are released under other open source licenses. ++ ++libpng versions 0.97, January 1998, through 1.0.6, March 20, 2000, are ++Copyright (c) 1998-2000 Glenn Randers-Pehrson, are derived from ++libpng-0.96, and are distributed according to the same disclaimer and ++license as libpng-0.96, with the following individuals added to the ++list of Contributing Authors: ++ ++ Tom Lane ++ Glenn Randers-Pehrson ++ Willem van Schaik ++ ++libpng versions 0.89, June 1996, through 0.96, May 1997, are ++Copyright (c) 1996-1997 Andreas Dilger, are derived from libpng-0.88, ++and are distributed according to the same disclaimer and license as ++libpng-0.88, with the following individuals added to the list of ++Contributing Authors: ++ ++ John Bowler ++ Kevin Bracey ++ Sam Bushell ++ Magnus Holmgren ++ Greg Roelofs ++ Tom Tanner ++ ++Some files in the "scripts" directory have other copyright owners, ++but are released under this license. ++ ++libpng versions 0.5, May 1995, through 0.88, January 1996, are ++Copyright (c) 1995-1996 Guy Eric Schalnat, Group 42, Inc. ++ ++For the purposes of this copyright and license, "Contributing Authors" ++is defined as the following set of individuals: ++ ++ Andreas Dilger ++ Dave Martindale ++ Guy Eric Schalnat ++ Paul Schmidt ++ Tim Wegner ++ ++The PNG Reference Library is supplied "AS IS". The Contributing ++Authors and Group 42, Inc. disclaim all warranties, expressed or ++implied, including, without limitation, the warranties of ++merchantability and of fitness for any purpose. The Contributing ++Authors and Group 42, Inc. assume no liability for direct, indirect, ++incidental, special, exemplary, or consequential damages, which may ++result from the use of the PNG Reference Library, even if advised of ++the possibility of such damage. ++ ++Permission is hereby granted to use, copy, modify, and distribute this ++source code, or portions hereof, for any purpose, without fee, subject ++to the following restrictions: ++ ++ 1. The origin of this source code must not be misrepresented. ++ ++ 2. Altered versions must be plainly marked as such and must not ++ be misrepresented as being the original source. ++ ++ 3. This Copyright notice may not be removed or altered from any ++ source or altered source distribution. ++ ++The Contributing Authors and Group 42, Inc. specifically permit, ++without fee, and encourage the use of this source code as a component ++to supporting the PNG file format in commercial products. If you use ++this source code in a product, acknowledgment is not required but would ++be appreciated. ++ ++TRADEMARK: ++ ++The name "libpng" has not been registered by the Copyright owners ++as a trademark in any jurisdiction. However, because libpng has ++been distributed and maintained world-wide, continually since 1995, ++the Copyright owners claim "common-law trademark protection" in any ++jurisdiction where common-law trademark is recognized. ++ ++OSI CERTIFICATION: ++ ++Libpng is OSI Certified Open Source Software. OSI Certified Open Source is ++a certification mark of the Open Source Initiative. OSI has not addressed ++the additional disclaimers inserted at version 1.0.7. ++ ++EXPORT CONTROL: ++ ++The Copyright owner believes that the Export Control Classification ++Number (ECCN) for libpng is EAR99, which means not subject to export ++controls or International Traffic in Arms Regulations (ITAR) because ++it is open source, publicly available software, that does not contain ++any encryption software. See the EAR, paragraphs 734.3(b)(3) and ++734.7(b). ++ ++Glenn Randers-Pehrson ++glennrp at users.sourceforge.net ++July 15, 2018 ++ ++AUTHORS File Information: ++ ++PNG REFERENCE LIBRARY AUTHORS ++============================= ++ ++This is the list of PNG Reference Library ("libpng") Contributing ++Authors, for copyright and licensing purposes. ++ ++ * Andreas Dilger ++ * Cosmin Truta ++ * Dave Martindale ++ * Eric S. Raymond ++ * Gilles Vollant ++ * Glenn Randers-Pehrson ++ * Greg Roelofs ++ * Guy Eric Schalnat ++ * James Yu ++ * John Bowler ++ * Kevin Bracey ++ * Magnus Holmgren ++ * Mandar Sahastrabuddhe ++ * Mans Rullgard ++ * Matt Sarett ++ * Mike Klein ++ * Pascal Massimino ++ * Paul Schmidt ++ * Qiang Zhou ++ * Sam Bushell ++ * Samuel Williams ++ * Simon-Pierre Cadieux ++ * Tim Wegner ++ * Tom Lane ++ * Tom Tanner ++ * Vadim Barkov ++ * Willem van Schaik ++ * Zhijie Liang ++ * Arm Holdings ++ - Richard Townsend ++ * Google Inc. ++ - Dan Field ++ - Leon Scroggins III ++ - Matt Sarett ++ - Mike Klein ++ - Sami Boukortt ++ ++The build projects, the build scripts, the test scripts, and other ++files in the "ci", "projects", "scripts" and "tests" directories, have ++other copyright owners, but are released under the libpng license. ++ ++Some files in the "contrib" directory, and some tools-generated files ++that are distributed with libpng, have other copyright owners, and are ++released under other open source licenses. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to GIFLIB 5.2.1 & libungif 4.1.3, ++which may be included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++The GIFLIB distribution is Copyright (c) 1997 Eric S. Raymond ++ ++Permission is hereby granted, free of charge, to any person obtaining a copy ++of this software and associated documentation files (the "Software"), to deal ++in the Software without restriction, including without limitation the rights ++to use, copy, modify, merge, publish, distribute, sublicense, and/or sell ++copies of the Software, and to permit persons to whom the Software is ++furnished to do so, subject to the following conditions: ++ ++The above copyright notice and this permission notice shall be included in ++all copies or substantial portions of the Software. ++ ++THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE ++AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ++LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, ++OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN ++THE SOFTWARE. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Little CMS 2.11, which may be ++included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++Little CMS ++Copyright (c) 1998-2020 Marti Maria Saguer ++ ++Permission is hereby granted, free of charge, to any person obtaining a copy ++of this software and associated documentation files (the "Software"), to deal ++in the Software without restriction, including without limitation the rights ++to use, copy, modify, merge, publish, distribute, sublicense, and/or sell ++copies of the Software, and to permit persons to whom the Software is ++furnished to do so, subject to the following conditions: ++ ++The above copyright notice and this permission notice shall be included in all ++copies or substantial portions of the Software. ++ ++THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE ++AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ++LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, ++OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE ++SOFTWARE. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% Lucida is a registered trademark or trademark of Bigelow & Holmes in the ++U.S. and other countries. ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Mesa 3D Graphics Library v4.1, ++which may be included with JRE 8, JDK 8, and OpenJDK 8 source distributions. ++ ++--- begin of LICENSE --- ++ ++ Mesa 3-D Graphics Library v19.2.1 ++ ++ Copyright (C) 1999-2007 Brian Paul All Rights Reserved. ++ ++ Permission is hereby granted, free of charge, to any person obtaining a ++ copy of this software and associated documentation files (the "Software"), ++ to deal in the Software without restriction, including without limitation ++ the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ and/or sell copies of the Software, and to permit persons to whom the ++ Software is furnished to do so, subject to the following conditions: ++ ++ The above copyright notice and this permission notice shall be included ++ in all copies or substantial portions of the Software. ++ ++ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ++ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, ++ OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE ++ SOFTWARE. ++ ++Attention, Contributors ++ ++When contributing to the Mesa project you must agree to the licensing terms ++of the component to which you're contributing. ++The following section lists the primary components of the Mesa distribution ++and their respective licenses. ++Mesa Component Licenses ++ ++ ++ ++Component Location License ++------------------------------------------------------------------ ++Main Mesa code src/mesa/ MIT ++Device drivers src/mesa/drivers/* MIT, generally ++ ++Gallium code src/gallium/ MIT ++ ++Ext headers GL/glext.h Khronos ++ GL/glxext.h Khronos ++ GL/wglext.h Khronos ++ KHR/khrplatform.h Khronos ++ ++***************************************************************************** ++ ++---- ++include/GL/gl.h : ++ ++ ++ Mesa 3-D graphics library ++ ++ Copyright (C) 1999-2006 Brian Paul All Rights Reserved. ++ Copyright (C) 2009 VMware, Inc. All Rights Reserved. ++ ++ Permission is hereby granted, free of charge, to any person obtaining a ++ copy of this software and associated documentation files (the "Software"), ++ to deal in the Software without restriction, including without limitation ++ the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ and/or sell copies of the Software, and to permit persons to whom the ++ Software is furnished to do so, subject to the following conditions: ++ ++ The above copyright notice and this permission notice shall be included ++ in all copies or substantial portions of the Software. ++ ++ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ OTHER DEALINGS IN THE SOFTWARE. ++ ++ ***************************************************************************** ++ ++---- ++include/GL/glext.h ++include/GL/glxext.h ++include/GL/wglxext.h : ++ ++ ++ Copyright (c) 2013 - 2018 The Khronos Group Inc. ++ ++ Permission is hereby granted, free of charge, to any person obtaining a ++ copy of this software and/or associated documentation files (the ++ "Materials"), to deal in the Materials without restriction, including ++ without limitation the rights to use, copy, modify, merge, publish, ++ distribute, sublicense, and/or sell copies of the Materials, and to ++ permit persons to whom the Materials are furnished to do so, subject to ++ the following conditions: ++ ++ The above copyright notice and this permission notice shall be included ++ in all copies or substantial portions of the Materials. ++ ++ THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. ++ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY ++ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, ++ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE ++ MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS. ++ ++ ***************************************************************************** ++ ++---- ++include/KHR/khrplatform.h : ++ ++ Copyright (c) 2008 - 2018 The Khronos Group Inc. ++ ++ Permission is hereby granted, free of charge, to any person obtaining a ++ copy of this software and/or associated documentation files (the ++ "Materials"), to deal in the Materials without restriction, including ++ without limitation the rights to use, copy, modify, merge, publish, ++ distribute, sublicense, and/or sell copies of the Materials, and to ++ permit persons to whom the Materials are furnished to do so, subject to ++ the following conditions: ++ ++ The above copyright notice and this permission notice shall be included ++ in all copies or substantial portions of the Materials. ++ ++ THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. ++ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY ++ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, ++ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE ++ MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS. ++ ++ ***************************************************************************** ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Mozilla Network Security ++Services (NSS), which is supplied with the JDK test suite in the OpenJDK ++source code repository. It is licensed under Mozilla Public License (MPL), ++version 2.0. ++ ++The NSS libraries are supplied in executable form, built from unmodified ++NSS source code labeled with the "NSS_3_16_RTM" HG tag. ++ ++The NSS source code is available in the OpenJDK source code repository at: ++ jdk/test/sun/security/pkcs11/nss/src ++ ++The NSS libraries are available in the OpenJDK source code repository at: ++ jdk/test/sun/security/pkcs11/nss/lib ++ ++--- begin of LICENSE --- ++ ++Mozilla Public License Version 2.0 ++================================== ++ ++1. Definitions ++-------------- ++ ++1.1. "Contributor" ++ means each individual or legal entity that creates, contributes to ++ the creation of, or owns Covered Software. ++ ++1.2. "Contributor Version" ++ means the combination of the Contributions of others (if any) used ++ by a Contributor and that particular Contributor's Contribution. ++ ++1.3. "Contribution" ++ means Covered Software of a particular Contributor. ++ ++1.4. "Covered Software" ++ means Source Code Form to which the initial Contributor has attached ++ the notice in Exhibit A, the Executable Form of such Source Code ++ Form, and Modifications of such Source Code Form, in each case ++ including portions thereof. ++ ++1.5. "Incompatible With Secondary Licenses" ++ means ++ ++ (a) that the initial Contributor has attached the notice described ++ in Exhibit B to the Covered Software; or ++ ++ (b) that the Covered Software was made available under the terms of ++ version 1.1 or earlier of the License, but not also under the ++ terms of a Secondary License. ++ ++1.6. "Executable Form" ++ means any form of the work other than Source Code Form. ++ ++1.7. "Larger Work" ++ means a work that combines Covered Software with other material, in ++ a separate file or files, that is not Covered Software. ++ ++1.8. "License" ++ means this document. ++ ++1.9. "Licensable" ++ means having the right to grant, to the maximum extent possible, ++ whether at the time of the initial grant or subsequently, any and ++ all of the rights conveyed by this License. ++ ++1.10. "Modifications" ++ means any of the following: ++ ++ (a) any file in Source Code Form that results from an addition to, ++ deletion from, or modification of the contents of Covered ++ Software; or ++ ++ (b) any new file in Source Code Form that contains any Covered ++ Software. ++ ++1.11. "Patent Claims" of a Contributor ++ means any patent claim(s), including without limitation, method, ++ process, and apparatus claims, in any patent Licensable by such ++ Contributor that would be infringed, but for the grant of the ++ License, by the making, using, selling, offering for sale, having ++ made, import, or transfer of either its Contributions or its ++ Contributor Version. ++ ++1.12. "Secondary License" ++ means either the GNU General Public License, Version 2.0, the GNU ++ Lesser General Public License, Version 2.1, the GNU Affero General ++ Public License, Version 3.0, or any later versions of those ++ licenses. ++ ++1.13. "Source Code Form" ++ means the form of the work preferred for making modifications. ++ ++1.14. "You" (or "Your") ++ means an individual or a legal entity exercising rights under this ++ License. For legal entities, "You" includes any entity that ++ controls, is controlled by, or is under common control with You. For ++ purposes of this definition, "control" means (a) the power, direct ++ or indirect, to cause the direction or management of such entity, ++ whether by contract or otherwise, or (b) ownership of more than ++ fifty percent (50%) of the outstanding shares or beneficial ++ ownership of such entity. ++ ++2. License Grants and Conditions ++-------------------------------- ++ ++2.1. Grants ++ ++Each Contributor hereby grants You a world-wide, royalty-free, ++non-exclusive license: ++ ++(a) under intellectual property rights (other than patent or trademark) ++ Licensable by such Contributor to use, reproduce, make available, ++ modify, display, perform, distribute, and otherwise exploit its ++ Contributions, either on an unmodified basis, with Modifications, or ++ as part of a Larger Work; and ++ ++(b) under Patent Claims of such Contributor to make, use, sell, offer ++ for sale, have made, import, and otherwise transfer either its ++ Contributions or its Contributor Version. ++ ++2.2. Effective Date ++ ++The licenses granted in Section 2.1 with respect to any Contribution ++become effective for each Contribution on the date the Contributor first ++distributes such Contribution. ++ ++2.3. Limitations on Grant Scope ++ ++The licenses granted in this Section 2 are the only rights granted under ++this License. No additional rights or licenses will be implied from the ++distribution or licensing of Covered Software under this License. ++Notwithstanding Section 2.1(b) above, no patent license is granted by a ++Contributor: ++ ++(a) for any code that a Contributor has removed from Covered Software; ++ or ++ ++(b) for infringements caused by: (i) Your and any other third party's ++ modifications of Covered Software, or (ii) the combination of its ++ Contributions with other software (except as part of its Contributor ++ Version); or ++ ++(c) under Patent Claims infringed by Covered Software in the absence of ++ its Contributions. ++ ++This License does not grant any rights in the trademarks, service marks, ++or logos of any Contributor (except as may be necessary to comply with ++the notice requirements in Section 3.4). ++ ++2.4. Subsequent Licenses ++ ++No Contributor makes additional grants as a result of Your choice to ++distribute the Covered Software under a subsequent version of this ++License (see Section 10.2) or under the terms of a Secondary License (if ++permitted under the terms of Section 3.3). ++ ++2.5. Representation ++ ++Each Contributor represents that the Contributor believes its ++Contributions are its original creation(s) or it has sufficient rights ++to grant the rights to its Contributions conveyed by this License. ++ ++2.6. Fair Use ++ ++This License is not intended to limit any rights You have under ++applicable copyright doctrines of fair use, fair dealing, or other ++equivalents. ++ ++2.7. Conditions ++ ++Sections 3.1, 3.2, 3.3, and 3.4 are conditions of the licenses granted ++in Section 2.1. ++ ++3. Responsibilities ++------------------- ++ ++3.1. Distribution of Source Form ++ ++All distribution of Covered Software in Source Code Form, including any ++Modifications that You create or to which You contribute, must be under ++the terms of this License. You must inform recipients that the Source ++Code Form of the Covered Software is governed by the terms of this ++License, and how they can obtain a copy of this License. You may not ++attempt to alter or restrict the recipients' rights in the Source Code ++Form. ++ ++3.2. Distribution of Executable Form ++ ++If You distribute Covered Software in Executable Form then: ++ ++(a) such Covered Software must also be made available in Source Code ++ Form, as described in Section 3.1, and You must inform recipients of ++ the Executable Form how they can obtain a copy of such Source Code ++ Form by reasonable means in a timely manner, at a charge no more ++ than the cost of distribution to the recipient; and ++ ++(b) You may distribute such Executable Form under the terms of this ++ License, or sublicense it under different terms, provided that the ++ license for the Executable Form does not attempt to limit or alter ++ the recipients' rights in the Source Code Form under this License. ++ ++3.3. Distribution of a Larger Work ++ ++You may create and distribute a Larger Work under terms of Your choice, ++provided that You also comply with the requirements of this License for ++the Covered Software. If the Larger Work is a combination of Covered ++Software with a work governed by one or more Secondary Licenses, and the ++Covered Software is not Incompatible With Secondary Licenses, this ++License permits You to additionally distribute such Covered Software ++under the terms of such Secondary License(s), so that the recipient of ++the Larger Work may, at their option, further distribute the Covered ++Software under the terms of either this License or such Secondary ++License(s). ++ ++3.4. Notices ++ ++You may not remove or alter the substance of any license notices ++(including copyright notices, patent notices, disclaimers of warranty, ++or limitations of liability) contained within the Source Code Form of ++the Covered Software, except that You may alter any license notices to ++the extent required to remedy known factual inaccuracies. ++ ++3.5. Application of Additional Terms ++ ++You may choose to offer, and to charge a fee for, warranty, support, ++indemnity or liability obligations to one or more recipients of Covered ++Software. However, You may do so only on Your own behalf, and not on ++behalf of any Contributor. You must make it absolutely clear that any ++such warranty, support, indemnity, or liability obligation is offered by ++You alone, and You hereby agree to indemnify every Contributor for any ++liability incurred by such Contributor as a result of warranty, support, ++indemnity or liability terms You offer. You may include additional ++disclaimers of warranty and limitations of liability specific to any ++jurisdiction. ++ ++4. Inability to Comply Due to Statute or Regulation ++--------------------------------------------------- ++ ++If it is impossible for You to comply with any of the terms of this ++License with respect to some or all of the Covered Software due to ++statute, judicial order, or regulation then You must: (a) comply with ++the terms of this License to the maximum extent possible; and (b) ++describe the limitations and the code they affect. Such description must ++be placed in a text file included with all distributions of the Covered ++Software under this License. Except to the extent prohibited by statute ++or regulation, such description must be sufficiently detailed for a ++recipient of ordinary skill to be able to understand it. ++ ++5. Termination ++-------------- ++ ++5.1. The rights granted under this License will terminate automatically ++if You fail to comply with any of its terms. However, if You become ++compliant, then the rights granted under this License from a particular ++Contributor are reinstated (a) provisionally, unless and until such ++Contributor explicitly and finally terminates Your grants, and (b) on an ++ongoing basis, if such Contributor fails to notify You of the ++non-compliance by some reasonable means prior to 60 days after You have ++come back into compliance. Moreover, Your grants from a particular ++Contributor are reinstated on an ongoing basis if such Contributor ++notifies You of the non-compliance by some reasonable means, this is the ++first time You have received notice of non-compliance with this License ++from such Contributor, and You become compliant prior to 30 days after ++Your receipt of the notice. ++ ++5.2. If You initiate litigation against any entity by asserting a patent ++infringement claim (excluding declaratory judgment actions, ++counter-claims, and cross-claims) alleging that a Contributor Version ++directly or indirectly infringes any patent, then the rights granted to ++You by any and all Contributors for the Covered Software under Section ++2.1 of this License shall terminate. ++ ++5.3. In the event of termination under Sections 5.1 or 5.2 above, all ++end user license agreements (excluding distributors and resellers) which ++have been validly granted by You or Your distributors under this License ++prior to termination shall survive termination. ++ ++************************************************************************ ++* * ++* 6. Disclaimer of Warranty * ++* ------------------------- * ++* * ++* Covered Software is provided under this License on an "as is" * ++* basis, without warranty of any kind, either expressed, implied, or * ++* statutory, including, without limitation, warranties that the * ++* Covered Software is free of defects, merchantable, fit for a * ++* particular purpose or non-infringing. The entire risk as to the * ++* quality and performance of the Covered Software is with You. * ++* Should any Covered Software prove defective in any respect, You * ++* (not any Contributor) assume the cost of any necessary servicing, * ++* repair, or correction. This disclaimer of warranty constitutes an * ++* essential part of this License. No use of any Covered Software is * ++* authorized under this License except under this disclaimer. * ++* * ++************************************************************************ ++ ++************************************************************************ ++* * ++* 7. Limitation of Liability * ++* -------------------------- * ++* * ++* Under no circumstances and under no legal theory, whether tort * ++* (including negligence), contract, or otherwise, shall any * ++* Contributor, or anyone who distributes Covered Software as * ++* permitted above, be liable to You for any direct, indirect, * ++* special, incidental, or consequential damages of any character * ++* including, without limitation, damages for lost profits, loss of * ++* goodwill, work stoppage, computer failure or malfunction, or any * ++* and all other commercial damages or losses, even if such party * ++* shall have been informed of the possibility of such damages. This * ++* limitation of liability shall not apply to liability for death or * ++* personal injury resulting from such party's negligence to the * ++* extent applicable law prohibits such limitation. Some * ++* jurisdictions do not allow the exclusion or limitation of * ++* incidental or consequential damages, so this exclusion and * ++* limitation may not apply to You. * ++* * ++************************************************************************ ++ ++8. Litigation ++------------- ++ ++Any litigation relating to this License may be brought only in the ++courts of a jurisdiction where the defendant maintains its principal ++place of business and such litigation shall be governed by laws of that ++jurisdiction, without reference to its conflict-of-law provisions. ++Nothing in this Section shall prevent a party's ability to bring ++cross-claims or counter-claims. ++ ++9. Miscellaneous ++---------------- ++ ++This License represents the complete agreement concerning the subject ++matter hereof. If any provision of this License is held to be ++unenforceable, such provision shall be reformed only to the extent ++necessary to make it enforceable. Any law or regulation which provides ++that the language of a contract shall be construed against the drafter ++shall not be used to construe this License against a Contributor. ++ ++10. Versions of the License ++--------------------------- ++ ++10.1. New Versions ++ ++Mozilla Foundation is the license steward. Except as provided in Section ++10.3, no one other than the license steward has the right to modify or ++publish new versions of this License. Each version will be given a ++distinguishing version number. ++ ++10.2. Effect of New Versions ++ ++You may distribute the Covered Software under the terms of the version ++of the License under which You originally received the Covered Software, ++or under the terms of any subsequent version published by the license ++steward. ++ ++10.3. Modified Versions ++ ++If you create software not governed by this License, and you want to ++create a new license for such software, you may create and use a ++modified version of this License if you rename the license and remove ++any references to the name of the license steward (except to note that ++such modified license differs from this License). ++ ++10.4. Distributing Source Code Form that is Incompatible With Secondary ++Licenses ++ ++If You choose to distribute Source Code Form that is Incompatible With ++Secondary Licenses under the terms of this version of the License, the ++notice described in Exhibit B of this License must be attached. ++ ++Exhibit A - Source Code Form License Notice ++------------------------------------------- ++ ++ This Source Code Form is subject to the terms of the Mozilla Public ++ License, v. 2.0. If a copy of the MPL was not distributed with this ++ file, You can obtain one at http://mozilla.org/MPL/2.0/. ++ ++If it is not possible or desirable to put the notice in a particular ++file, then You may include the notice in a location (such as a LICENSE ++file in a relevant directory) where a recipient would be likely to look ++for such a notice. ++ ++You may add additional accurate notices of copyright ownership. ++ ++Exhibit B - "Incompatible With Secondary Licenses" Notice ++--------------------------------------------------------- ++ ++ This Source Code Form is "Incompatible With Secondary Licenses", as ++ defined by the Mozilla Public License, v. 2.0. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to PC/SC Lite v1.8.26, ++which may be included with JRE 8, JDK 8, and OpenJDK 8 on Linux and Solaris. ++ ++--- begin of LICENSE --- ++ ++Copyright (c) 1999-2003 David Corcoran ++Copyright (c) 2001-2011 Ludovic Rousseau ++All rights reserved. ++ ++Redistribution and use in source and binary forms, with or without ++modification, are permitted provided that the following conditions ++are met: ++ ++1. Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++2. Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++3. The name of the author may not be used to endorse or promote products ++ derived from this software without specific prior written permission. ++ ++Changes to this license can be made only by the copyright author with ++explicit written consent. ++ ++THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to PorterStemmer v4, which may be ++included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++See: http://tartarus.org/~martin/PorterStemmer ++ ++The software is completely free for any purpose, unless notes at the head of ++the program text indicates otherwise (which is rare). In any case, the notes ++about licensing are never more restrictive than the BSD License. ++ ++In every case where the software is not written by me (Martin Porter), this ++licensing arrangement has been endorsed by the contributor, and it is ++therefore unnecessary to ask the contributor again to confirm it. ++ ++I have not asked any contributors (or their employers, if they have them) for ++proofs that they have the right to distribute their software in this way. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Relax NG Object/Parser v.20050510, ++which may be included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++Copyright (c) Kohsuke Kawaguchi ++ ++Permission is hereby granted, free of charge, to any person obtaining a copy ++of this software and associated documentation files (the "Software"), to deal ++in the Software without restriction, including without limitation the rights ++to use, copy, modify, merge, publish, distribute, sublicense, and/or sell ++copies of the Software, and to permit persons to whom the Software is ++furnished to do so, subject to the following conditions: The above copyright ++notice and this permission notice shall be included in all copies or ++substantial portions of the Software. ++ ++THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE ++AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ++LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, ++OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE ++SOFTWARE. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to RelaxNGCC v1.12, which may be ++included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++Copyright (c) 2000-2003 Daisuke Okajima and Kohsuke Kawaguchi. ++All rights reserved. ++ ++Redistribution and use in source and binary forms, with or without ++modification, are permitted provided that the following conditions are met: ++ ++1. Redistributions of source code must retain the above copyright notice, this ++ list of conditions and the following disclaimer. ++ ++2. Redistributions in binary form must reproduce the above copyright notice, ++ this list of conditions and the following disclaimer in the documentation ++ and/or other materials provided with the distribution. ++ ++3. The end-user documentation included with the redistribution, if any, must ++ include the following acknowledgment: ++ ++ "This product includes software developed by Daisuke Okajima ++ and Kohsuke Kawaguchi (http://relaxngcc.sf.net/)." ++ ++Alternately, this acknowledgment may appear in the software itself, if and ++wherever such third-party acknowledgments normally appear. ++ ++4. The names of the copyright holders must not be used to endorse or promote ++ products derived from this software without prior written permission. For ++ written permission, please contact the copyright holders. ++ ++5. Products derived from this software may not be called "RELAXNGCC", nor may ++ "RELAXNGCC" appear in their name, without prior written permission of the ++ copyright holders. ++ ++THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESSED OR IMPLIED WARRANTIES, ++INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND ++FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.IN NO EVENT SHALL THE APACHE ++SOFTWARE FOUNDATION OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ++INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ++EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Relax NG Datatype 1.0, which ++may be included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++Copyright (c) 2005, 2010 Thai Open Source Software Center Ltd ++All rights reserved. ++ ++Redistribution and use in source and binary forms, with or without ++modification, are permitted provided that the following conditions are ++met: ++ ++ Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ Neither the names of the copyright holders nor the names of its ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR ++CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++--- end of LICENSE --- ++ ++-------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to SoftFloat version 2b, which may be ++included with JRE 8, JDK 8, and OpenJDK 8 on Linux/ARM. ++ ++--- begin of LICENSE --- ++ ++Use of any of this software is governed by the terms of the license below: ++ ++SoftFloat was written by me, John R. Hauser. This work was made possible in ++part by the International Computer Science Institute, located at Suite 600, ++1947 Center Street, Berkeley, California 94704. Funding was partially ++provided by the National Science Foundation under grant MIP-9311980. The ++original version of this code was written as part of a project to build ++a fixed-point vector processor in collaboration with the University of ++California at Berkeley, overseen by Profs. Nelson Morgan and John Wawrzynek. ++ ++THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort ++has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT ++TIMES RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO ++PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL ++LOSSES, COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO ++FURTHERMORE EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER ++SCIENCE INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES, ++COSTS, OR OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE ++SOFTWARE. ++ ++Derivative works are acceptable, even for commercial purposes, provided ++that the minimal documentation requirements stated in the source code are ++satisfied. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Sparkle 1.5, ++which may be included with JRE 8 on Mac OS X. ++ ++--- begin of LICENSE --- ++ ++Copyright (c) 2012 Sparkle.org and Andy Matuschak ++ ++Permission is hereby granted, free of charge, to any person obtaining a copy ++of this software and associated documentation files (the "Software"), to deal ++in the Software without restriction, including without limitation the rights ++to use, copy, modify, merge, publish, distribute, sublicense, and/or sell ++copies of the Software, and to permit persons to whom the Software is ++furnished to do so, subject to the following conditions: ++ ++The above copyright notice and this permission notice shall be included in all ++copies or substantial portions of the Software. ++ ++THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE ++AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ++LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, ++OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE ++SOFTWARE. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% Portions licensed from Taligent, Inc. ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Thai Dictionary, which may be ++included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++Copyright (C) 1982 The Royal Institute, Thai Royal Government. ++ ++Copyright (C) 1998 National Electronics and Computer Technology Center, ++National Science and Technology Development Agency, ++Ministry of Science Technology and Environment, ++Thai Royal Government. ++ ++Permission is hereby granted, free of charge, to any person obtaining a copy ++of this software and associated documentation files (the "Software"), to deal ++in the Software without restriction, including without limitation the rights ++to use, copy, modify, merge, publish, distribute, sublicense, and/or sell ++copies of the Software, and to permit persons to whom the Software is ++furnished to do so, subject to the following conditions: ++ ++The above copyright notice and this permission notice shall be included in all ++copies or substantial portions of the Software. ++ ++THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 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Any person is hereby authorized, ++ without fee, to modify such documents and files to create derivative ++ works conforming to the Unicode?? Standard, subject to Terms and ++ Conditions herein. ++ ++ 3. Any person is hereby authorized, without fee, to view, use, reproduce, ++ and distribute all documents and files solely for informational ++ purposes in the creation of products supporting the Unicode Standard, ++ subject to the Terms and Conditions herein. ++ ++ 4. Further specifications of rights and restrictions pertaining to the use ++ of the particular set of data files known as the "Unicode Character ++ Database" can be found in Exhibit 1. ++ ++ 5. Each version of the Unicode Standard has further specifications of ++ rights and restrictions of use. For the book editions (Unicode 5.0 and ++ earlier), these are found on the back of the title page. The online ++ code charts carry specific restrictions. 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Unicode Data Files do not include PDF ++online code charts under the directory http://www.unicode.org/Public/. ++Software includes any source code published in the Unicode Standard or under ++the directories http://www.unicode.org/Public/, ++http://www.unicode.org/reports/, and http://www.unicode.org/cldr/data/. ++ ++NOTICE TO USER: Carefully read the following legal agreement. BY DOWNLOADING, ++INSTALLING, COPYING OR OTHERWISE USING UNICODE INC.'S DATA FILES ("DATA ++FILES"), AND/OR SOFTWARE ("SOFTWARE"), YOU UNEQUIVOCALLY ACCEPT, AND AGREE TO ++BE BOUND BY, ALL OF THE TERMS AND CONDITIONS OF THIS AGREEMENT. IF YOU DO NOT ++AGREE, DO NOT DOWNLOAD, INSTALL, COPY, DISTRIBUTE OR USE THE DATA FILES OR ++SOFTWARE. ++ ++COPYRIGHT AND PERMISSION NOTICE ++ ++Copyright ?? 1991-2012 Unicode, Inc. All rights reserved. Distributed under the ++Terms of Use in http://www.unicode.org/copyright.html. ++ ++Permission is hereby granted, free of charge, to any person obtaining a copy ++of the Unicode data files and any associated documentation (the "Data Files") ++or Unicode software and any associated documentation (the "Software") to deal ++in the Data Files or Software without restriction, including without ++limitation the rights to use, copy, modify, merge, publish, distribute, and/or ++sell copies of the Data Files or Software, and to permit persons to whom the ++Data Files or Software are furnished to do so, provided that (a) the above ++copyright notice(s) and this permission notice appear with all copies of the ++Data Files or Software, (b) both the above copyright notice(s) and this ++permission notice appear in associated documentation, and (c) there is clear ++notice in each modified Data File or in the Software as well as in the ++documentation associated with the Data File(s) or Software that the data or ++software has been modified. ++ ++THE DATA FILES AND SOFTWARE ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY ++KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT OF THIRD ++PARTY RIGHTS. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR HOLDERS INCLUDED IN ++THIS NOTICE BE LIABLE FOR ANY CLAIM, OR ANY SPECIAL INDIRECT OR CONSEQUENTIAL ++DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR ++PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ++ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THE ++DATA FILES OR SOFTWARE. ++ ++Except as contained in this notice, the name of a copyright holder shall not ++be used in advertising or otherwise to promote the sale, use or other dealings ++in these Data Files or Software without prior written authorization of the ++copyright holder. ++ ++Unicode and the Unicode logo are trademarks of Unicode, Inc. in the United ++States and other countries. All third party trademarks referenced herein are ++the property of their respective owners. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to UPX v3.01, which may be included ++with JRE 8 on Windows. ++ ++--- begin of LICENSE --- ++ ++Use of any of this software is governed by the terms of the license below: ++ ++ ++ ooooo ooo ooooooooo. ooooooo ooooo ++ `888' `8' `888 `Y88. `8888 d8' ++ 888 8 888 .d88' Y888..8P ++ 888 8 888ooo88P' `8888' ++ 888 8 888 .8PY888. ++ `88. .8' 888 d8' `888b ++ `YbodP' o888o o888o o88888o ++ ++ ++ The Ultimate Packer for eXecutables ++ Copyright (c) 1996-2000 Markus Oberhumer & Laszlo Molnar ++ http://wildsau.idv.uni-linz.ac.at/mfx/upx.html ++ http://www.nexus.hu/upx ++ http://upx.tsx.org ++ ++ ++PLEASE CAREFULLY READ THIS LICENSE AGREEMENT, ESPECIALLY IF YOU PLAN ++TO MODIFY THE UPX SOURCE CODE OR USE A MODIFIED UPX VERSION. ++ ++ ++ABSTRACT ++======== ++ ++ UPX and UCL are copyrighted software distributed under the terms ++ of the GNU General Public License (hereinafter the "GPL"). ++ ++ The stub which is imbedded in each UPX compressed program is part ++ of UPX and UCL, and contains code that is under our copyright. The ++ terms of the GNU General Public License still apply as compressing ++ a program is a special form of linking with our stub. ++ ++ As a special exception we grant the free usage of UPX for all ++ executables, including commercial programs. ++ See below for details and restrictions. ++ ++ ++COPYRIGHT ++========= ++ ++ UPX and UCL are copyrighted software. All rights remain with the authors. ++ ++ UPX is Copyright (C) 1996-2000 Markus Franz Xaver Johannes Oberhumer ++ UPX is Copyright (C) 1996-2000 Laszlo Molnar ++ ++ UCL is Copyright (C) 1996-2000 Markus Franz Xaver Johannes Oberhumer ++ ++ ++GNU GENERAL PUBLIC LICENSE ++========================== ++ ++ UPX and the UCL library are free software; you can redistribute them ++ and/or modify them under the terms of the GNU General Public License as ++ published by the Free Software Foundation; either version 2 of ++ the License, or (at your option) any later version. ++ ++ UPX and UCL are distributed in the hope that they will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ GNU General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with this program; see the file COPYING. ++ ++ ++SPECIAL EXCEPTION FOR COMPRESSED EXECUTABLES ++============================================ ++ ++ The stub which is imbedded in each UPX compressed program is part ++ of UPX and UCL, and contains code that is under our copyright. The ++ terms of the GNU General Public License still apply as compressing ++ a program is a special form of linking with our stub. ++ ++ Hereby Markus F.X.J. Oberhumer and Laszlo Molnar grant you special ++ permission to freely use and distribute all UPX compressed programs ++ (including commercial ones), subject to the following restrictions: ++ ++ 1. You must compress your program with a completely unmodified UPX ++ version; either with our precompiled version, or (at your option) ++ with a self compiled version of the unmodified UPX sources as ++ distributed by us. ++ 2. This also implies that the UPX stub must be completely unmodfied, i.e. ++ the stub imbedded in your compressed program must be byte-identical ++ to the stub that is produced by the official unmodified UPX version. ++ 3. The decompressor and any other code from the stub must exclusively get ++ used by the unmodified UPX stub for decompressing your program at ++ program startup. No portion of the stub may get read, copied, ++ called or otherwise get used or accessed by your program. ++ ++ ++ANNOTATIONS ++=========== ++ ++ - You can use a modified UPX version or modified UPX stub only for ++ programs that are compatible with the GNU General Public License. ++ ++ - We grant you special permission to freely use and distribute all UPX ++ compressed programs. But any modification of the UPX stub (such as, ++ but not limited to, removing our copyright string or making your ++ program non-decompressible) will immediately revoke your right to ++ use and distribute a UPX compressed program. ++ ++ - UPX is not a software protection tool; by requiring that you use ++ the unmodified UPX version for your proprietary programs we ++ make sure that any user can decompress your program. This protects ++ both you and your users as nobody can hide malicious code - ++ any program that cannot be decompressed is highly suspicious ++ by definition. ++ ++ - You can integrate all or part of UPX and UCL into projects that ++ are compatible with the GNU GPL, but obviously you cannot grant ++ any special exceptions beyond the GPL for our code in your project. ++ ++ - We want to actively support manufacturers of virus scanners and ++ similar security software. Please contact us if you would like to ++ incorporate parts of UPX or UCL into such a product. ++ ++ ++ ++Markus F.X.J. Oberhumer Laszlo Molnar ++markus.oberhumer@jk.uni-linz.ac.at ml1050@cdata.tvnet.hu ++ ++Linz, Austria, 25 Feb 2000 ++ ++Additional License(s) ++ ++The UPX license file is at http://upx.sourceforge.net/upx-license.html. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Xfree86-VidMode Extension 1.0, ++which may be included with JRE 8, JDK 8, and OpenJDK 8 on Linux and Solaris. ++ ++--- begin of LICENSE --- ++ ++Version 1.1 of XFree86 ProjectLicence. ++ ++Copyright (C) 1994-2004 The XFree86 Project, Inc. All rights reserved. ++ ++Permission is hereby granted, free of charge, to any person obtaining a copy of ++this software and associated documentation files (the "Software"), to deal ++in the Software without restriction, including without limitation the rights ++to use, copy, modify, merge, publish, distribute, sublicence, and/or sell ++copies of the Software, and to permit persons to whom the Software is furnished ++to do so,subject to the following conditions: ++ ++ 1. Redistributions of source code must retain the above copyright ++ notice,this list of conditions, and the following disclaimer. ++ ++ 2. Redistributions in binary form must reproduce the above copyright notice, ++ this list of conditions and the following disclaimer in the documentation ++ and/or other materials provided with the distribution, and in the same place ++ and form as other copyright, license and disclaimer information. ++ ++ 3. The end-user documentation included with the redistribution, if any,must ++ include the following acknowledgment: "This product includes ++ software developed by The XFree86 Project, Inc (http://www.xfree86.org/) and ++ its contributors", in the same place and form as other third-party ++ acknowledgments. Alternately, this acknowledgment may appear in the software ++ itself, in the same form and location as other such third-party ++ acknowledgments. ++ ++ 4. Except as contained in this notice, the name of The XFree86 Project,Inc ++ shall not be used in advertising or otherwise to promote the sale, use ++ or other dealings in this Software without prior written authorization from ++ The XFree86 Project, Inc. ++ ++ THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESSED OR IMPLIED ++ WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF ++ MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 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Copies of claims of rights made available for publication and ++any assurances of licenses to be made available, or the result of an ++attempt made to obtain a general license or permission for the use of ++such proprietary rights by implementers or users of this OASIS Standards ++Final Deliverable, can be obtained from the OASIS TC Administrator. ++OASIS makes no representation that any information or list of ++intellectual property rights will at any time be complete, or that any ++claims in such list are, in fact, Essential Claims.] ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- +diff --git a/jdk/make/data/tzdata/VERSION b/jdk/make/data/tzdata/VERSION +index b138ed7fa7..66bd061e8b 100644 +--- a/jdk/make/data/tzdata/VERSION ++++ b/jdk/make/data/tzdata/VERSION +@@ -21,4 +21,4 @@ + # or visit www.oracle.com if you need additional information or have any + # questions. + # +-tzdata2024a ++tzdata2023c +diff --git a/jdk/make/data/tzdata/asia b/jdk/make/data/tzdata/asia +index c51170c34a..48a348bf95 100644 +--- a/jdk/make/data/tzdata/asia ++++ b/jdk/make/data/tzdata/asia +@@ -678,6 +678,7 @@ Zone Asia/Shanghai 8:05:43 - LMT 1901 + 8:00 PRC C%sT + # Xinjiang time, used by many in western China; represented by Ürümqi / Ürümchi + # / Wulumuqi. (Please use Asia/Shanghai if you prefer Beijing time.) ++# Vostok base in Antarctica matches this since 1970. + Zone Asia/Urumqi 5:50:20 - LMT 1928 + 6:00 - +06 + +@@ -2480,33 +2481,18 @@ Zone Asia/Amman 2:23:44 - LMT 1931 + # effective December 21st, 2018.... + # http://adilet.zan.kz/rus/docs/P1800000817 (russian language). + +-# From Zhanbolat Raimbekov (2024-01-19): +-# Kazakhstan (all parts) switching to UTC+5 on March 1, 2024 +-# https://www.gov.kz/memleket/entities/mti/press/news/details/688998?lang=ru +-# [in Russian] +-# (2024-01-20): https://primeminister.kz/ru/decisions/19012024-20 +-# +-# From Alexander Krivenyshev (2024-01-19): +-# According to a different news and the official web site for the Ministry of +-# Trade and Integration of the Republic of Kazakhstan: +-# https://en.inform.kz/news/kazakhstan-to-switch-to-single-hour-zone-mar-1-54ad0b/ +- + # Zone NAME STDOFF RULES FORMAT [UNTIL] + # + # Almaty (formerly Alma-Ata), representing most locations in Kazakhstan +-# This includes Abai/Abay (ISO 3166-2 code KZ-10), Aqmola/Akmola (KZ-11), +-# Almaty (KZ-19), Almaty city (KZ-75), Astana city (KZ-71), +-# East Kazkhstan (KZ-63), Jambyl/Zhambyl (KZ-31), Jetisu/Zhetysu (KZ-33), +-# Karaganda (KZ-35), North Kazakhstan (KZ-59), Pavlodar (KZ-55), +-# Shyumkent city (KZ-79), Turkistan (KZ-61), and Ulytau (KZ-62). ++# This includes KZ-AKM, KZ-ALA, KZ-ALM, KZ-AST, KZ-BAY, KZ-VOS, KZ-ZHA, ++# KZ-KAR, KZ-SEV, KZ-PAV, and KZ-YUZ. + Zone Asia/Almaty 5:07:48 - LMT 1924 May 2 # or Alma-Ata + 5:00 - +05 1930 Jun 21 + 6:00 RussiaAsia +06/+07 1991 Mar 31 2:00s + 5:00 RussiaAsia +05/+06 1992 Jan 19 2:00s + 6:00 RussiaAsia +06/+07 2004 Oct 31 2:00s +- 6:00 - +06 2024 Mar 1 0:00 +- 5:00 - +05 +-# Qyzylorda (aka Kyzylorda, Kizilorda, Kzyl-Orda, etc.) (KZ-43) ++ 6:00 - +06 ++# Qyzylorda (aka Kyzylorda, Kizilorda, Kzyl-Orda, etc.) (KZ-KZY) + Zone Asia/Qyzylorda 4:21:52 - LMT 1924 May 2 + 4:00 - +04 1930 Jun 21 + 5:00 - +05 1981 Apr 1 +@@ -2519,7 +2505,8 @@ Zone Asia/Qyzylorda 4:21:52 - LMT 1924 May 2 + 5:00 RussiaAsia +05/+06 2004 Oct 31 2:00s + 6:00 - +06 2018 Dec 21 0:00 + 5:00 - +05 +-# Qostanay (aka Kostanay, Kustanay) (KZ-39) ++# ++# Qostanay (aka Kostanay, Kustanay) (KZ-KUS) + # The 1991/2 rules are unclear partly because of the 1997 Turgai + # reorganization. + Zone Asia/Qostanay 4:14:28 - LMT 1924 May 2 +@@ -2530,9 +2517,9 @@ Zone Asia/Qostanay 4:14:28 - LMT 1924 May 2 + 5:00 RussiaAsia +05/+06 1991 Mar 31 2:00s + 4:00 RussiaAsia +04/+05 1992 Jan 19 2:00s + 5:00 RussiaAsia +05/+06 2004 Oct 31 2:00s +- 6:00 - +06 2024 Mar 1 0:00 +- 5:00 - +05 +-# Aqtöbe (aka Aktobe, formerly Aktyubinsk) (KZ-15) ++ 6:00 - +06 ++ ++# Aqtöbe (aka Aktobe, formerly Aktyubinsk) (KZ-AKT) + Zone Asia/Aqtobe 3:48:40 - LMT 1924 May 2 + 4:00 - +04 1930 Jun 21 + 5:00 - +05 1981 Apr 1 +@@ -2542,7 +2529,7 @@ Zone Asia/Aqtobe 3:48:40 - LMT 1924 May 2 + 4:00 RussiaAsia +04/+05 1992 Jan 19 2:00s + 5:00 RussiaAsia +05/+06 2004 Oct 31 2:00s + 5:00 - +05 +-# Mangghystaū (KZ-47) ++# Mangghystaū (KZ-MAN) + # Aqtau was not founded until 1963, but it represents an inhabited region, + # so include timestamps before 1963. + Zone Asia/Aqtau 3:21:04 - LMT 1924 May 2 +@@ -2554,7 +2541,7 @@ Zone Asia/Aqtau 3:21:04 - LMT 1924 May 2 + 5:00 RussiaAsia +05/+06 1994 Sep 25 2:00s + 4:00 RussiaAsia +04/+05 2004 Oct 31 2:00s + 5:00 - +05 +-# Atyraū (KZ-23) is like Mangghystaū except it switched from ++# Atyraū (KZ-ATY) is like Mangghystaū except it switched from + # +04/+05 to +05/+06 in spring 1999, not fall 1994. + Zone Asia/Atyrau 3:27:44 - LMT 1924 May 2 + 3:00 - +03 1930 Jun 21 +@@ -2565,7 +2552,7 @@ Zone Asia/Atyrau 3:27:44 - LMT 1924 May 2 + 5:00 RussiaAsia +05/+06 1999 Mar 28 2:00s + 4:00 RussiaAsia +04/+05 2004 Oct 31 2:00s + 5:00 - +05 +-# West Kazakhstan (KZ-27) ++# West Kazakhstan (KZ-ZAP) + # From Paul Eggert (2016-03-18): + # The 1989 transition is from USSR act No. 227 (1989-03-14). + Zone Asia/Oral 3:25:24 - LMT 1924 May 2 # or Ural'sk +@@ -3463,30 +3450,20 @@ Zone Asia/Karachi 4:28:12 - LMT 1907 + # From Heba Hamad (2023-03-22): + # ... summer time will begin in Palestine from Saturday 04-29-2023, + # 02:00 AM by 60 minutes forward. +-# From Heba Hemad (2023-10-09): +-# ... winter time will begin in Palestine from Saturday 10-28-2023, +-# 02:00 AM by 60 minutes back. +-# +-# From Heba Hamad (2024-01-25): +-# the summer time for the years 2024,2025 will begin in Palestine +-# from Saturday at 02:00 AM by 60 minutes forward as shown below: +-# year date +-# 2024 2024-04-20 +-# 2025 2025-04-12 +-# +-# From Paul Eggert (2024-01-25): ++# ++# From Paul Eggert (2023-03-22): + # For now, guess that spring and fall transitions will normally + # continue to use 2022's rules, that during DST Palestine will switch + # to standard time at 02:00 the last Saturday before Ramadan and back +-# to DST at 02:00 the second Saturday after Ramadan, and that ++# to DST at 02:00 the first Saturday after Ramadan, and that + # if the normal spring-forward or fall-back transition occurs during + # Ramadan the former is delayed and the latter advanced. + # To implement this, I predicted Ramadan-oriented transition dates for +-# 2026 through 2086 by running the following program under GNU Emacs 29.2, ++# 2023 through 2086 by running the following program under GNU Emacs 28.2, + # with the results integrated by hand into the table below. + # Predictions after 2086 are approximated without Ramadan. + # +-# (let ((islamic-year 1447)) ++# (let ((islamic-year 1444)) + # (require 'cal-islam) + # (while (< islamic-year 1510) + # (let ((a (calendar-islamic-to-absolute (list 9 1 islamic-year))) +@@ -3495,7 +3472,6 @@ Zone Asia/Karachi 4:28:12 - LMT 1907 + # (while (/= saturday (mod (setq a (1- a)) 7))) + # (while (/= saturday (mod b 7)) + # (setq b (1+ b))) +-# (setq b (+ 7 b)) + # (setq a (calendar-gregorian-from-absolute a)) + # (setq b (calendar-gregorian-from-absolute b)) + # (insert +@@ -3546,84 +3522,84 @@ Rule Palestine 2021 only - Oct 29 1:00 0 - + Rule Palestine 2022 only - Mar 27 0:00 1:00 S + Rule Palestine 2022 2035 - Oct Sat<=30 2:00 0 - + Rule Palestine 2023 only - Apr 29 2:00 1:00 S +-Rule Palestine 2024 only - Apr 20 2:00 1:00 S +-Rule Palestine 2025 only - Apr 12 2:00 1:00 S ++Rule Palestine 2024 only - Apr 13 2:00 1:00 S ++Rule Palestine 2025 only - Apr 5 2:00 1:00 S + Rule Palestine 2026 2054 - Mar Sat<=30 2:00 1:00 S + Rule Palestine 2036 only - Oct 18 2:00 0 - + Rule Palestine 2037 only - Oct 10 2:00 0 - + Rule Palestine 2038 only - Sep 25 2:00 0 - + Rule Palestine 2039 only - Sep 17 2:00 0 - ++Rule Palestine 2039 only - Oct 22 2:00 1:00 S ++Rule Palestine 2039 2067 - Oct Sat<=30 2:00 0 - + Rule Palestine 2040 only - Sep 1 2:00 0 - +-Rule Palestine 2040 only - Oct 20 2:00 1:00 S +-Rule Palestine 2040 2067 - Oct Sat<=30 2:00 0 - ++Rule Palestine 2040 only - Oct 13 2:00 1:00 S + Rule Palestine 2041 only - Aug 24 2:00 0 - +-Rule Palestine 2041 only - Oct 5 2:00 1:00 S ++Rule Palestine 2041 only - Sep 28 2:00 1:00 S + Rule Palestine 2042 only - Aug 16 2:00 0 - +-Rule Palestine 2042 only - Sep 27 2:00 1:00 S ++Rule Palestine 2042 only - Sep 20 2:00 1:00 S + Rule Palestine 2043 only - Aug 1 2:00 0 - +-Rule Palestine 2043 only - Sep 19 2:00 1:00 S ++Rule Palestine 2043 only - Sep 12 2:00 1:00 S + Rule Palestine 2044 only - Jul 23 2:00 0 - +-Rule Palestine 2044 only - Sep 3 2:00 1:00 S ++Rule Palestine 2044 only - Aug 27 2:00 1:00 S + Rule Palestine 2045 only - Jul 15 2:00 0 - +-Rule Palestine 2045 only - Aug 26 2:00 1:00 S ++Rule Palestine 2045 only - Aug 19 2:00 1:00 S + Rule Palestine 2046 only - Jun 30 2:00 0 - +-Rule Palestine 2046 only - Aug 18 2:00 1:00 S ++Rule Palestine 2046 only - Aug 11 2:00 1:00 S + Rule Palestine 2047 only - Jun 22 2:00 0 - +-Rule Palestine 2047 only - Aug 3 2:00 1:00 S ++Rule Palestine 2047 only - Jul 27 2:00 1:00 S + Rule Palestine 2048 only - Jun 6 2:00 0 - +-Rule Palestine 2048 only - Jul 25 2:00 1:00 S ++Rule Palestine 2048 only - Jul 18 2:00 1:00 S + Rule Palestine 2049 only - May 29 2:00 0 - +-Rule Palestine 2049 only - Jul 10 2:00 1:00 S ++Rule Palestine 2049 only - Jul 3 2:00 1:00 S + Rule Palestine 2050 only - May 21 2:00 0 - +-Rule Palestine 2050 only - Jul 2 2:00 1:00 S ++Rule Palestine 2050 only - Jun 25 2:00 1:00 S + Rule Palestine 2051 only - May 6 2:00 0 - +-Rule Palestine 2051 only - Jun 24 2:00 1:00 S ++Rule Palestine 2051 only - Jun 17 2:00 1:00 S + Rule Palestine 2052 only - Apr 27 2:00 0 - +-Rule Palestine 2052 only - Jun 8 2:00 1:00 S ++Rule Palestine 2052 only - Jun 1 2:00 1:00 S + Rule Palestine 2053 only - Apr 12 2:00 0 - +-Rule Palestine 2053 only - May 31 2:00 1:00 S ++Rule Palestine 2053 only - May 24 2:00 1:00 S + Rule Palestine 2054 only - Apr 4 2:00 0 - +-Rule Palestine 2054 only - May 23 2:00 1:00 S +-Rule Palestine 2055 only - May 8 2:00 1:00 S +-Rule Palestine 2056 only - Apr 29 2:00 1:00 S +-Rule Palestine 2057 only - Apr 14 2:00 1:00 S +-Rule Palestine 2058 only - Apr 6 2:00 1:00 S +-Rule Palestine 2059 max - Mar Sat<=30 2:00 1:00 S ++Rule Palestine 2054 only - May 16 2:00 1:00 S ++Rule Palestine 2055 only - May 1 2:00 1:00 S ++Rule Palestine 2056 only - Apr 22 2:00 1:00 S ++Rule Palestine 2057 only - Apr 7 2:00 1:00 S ++Rule Palestine 2058 max - Mar Sat<=30 2:00 1:00 S + Rule Palestine 2068 only - Oct 20 2:00 0 - + Rule Palestine 2069 only - Oct 12 2:00 0 - + Rule Palestine 2070 only - Oct 4 2:00 0 - + Rule Palestine 2071 only - Sep 19 2:00 0 - + Rule Palestine 2072 only - Sep 10 2:00 0 - +-Rule Palestine 2072 only - Oct 22 2:00 1:00 S +-Rule Palestine 2072 max - Oct Sat<=30 2:00 0 - ++Rule Palestine 2072 only - Oct 15 2:00 1:00 S + Rule Palestine 2073 only - Sep 2 2:00 0 - +-Rule Palestine 2073 only - Oct 14 2:00 1:00 S ++Rule Palestine 2073 only - Oct 7 2:00 1:00 S + Rule Palestine 2074 only - Aug 18 2:00 0 - +-Rule Palestine 2074 only - Oct 6 2:00 1:00 S ++Rule Palestine 2074 only - Sep 29 2:00 1:00 S + Rule Palestine 2075 only - Aug 10 2:00 0 - +-Rule Palestine 2075 only - Sep 21 2:00 1:00 S ++Rule Palestine 2075 only - Sep 14 2:00 1:00 S ++Rule Palestine 2075 max - Oct Sat<=30 2:00 0 - + Rule Palestine 2076 only - Jul 25 2:00 0 - +-Rule Palestine 2076 only - Sep 12 2:00 1:00 S ++Rule Palestine 2076 only - Sep 5 2:00 1:00 S + Rule Palestine 2077 only - Jul 17 2:00 0 - +-Rule Palestine 2077 only - Sep 4 2:00 1:00 S ++Rule Palestine 2077 only - Aug 28 2:00 1:00 S + Rule Palestine 2078 only - Jul 9 2:00 0 - +-Rule Palestine 2078 only - Aug 20 2:00 1:00 S ++Rule Palestine 2078 only - Aug 13 2:00 1:00 S + Rule Palestine 2079 only - Jun 24 2:00 0 - +-Rule Palestine 2079 only - Aug 12 2:00 1:00 S ++Rule Palestine 2079 only - Aug 5 2:00 1:00 S + Rule Palestine 2080 only - Jun 15 2:00 0 - +-Rule Palestine 2080 only - Jul 27 2:00 1:00 S ++Rule Palestine 2080 only - Jul 20 2:00 1:00 S + Rule Palestine 2081 only - Jun 7 2:00 0 - +-Rule Palestine 2081 only - Jul 19 2:00 1:00 S ++Rule Palestine 2081 only - Jul 12 2:00 1:00 S + Rule Palestine 2082 only - May 23 2:00 0 - +-Rule Palestine 2082 only - Jul 11 2:00 1:00 S ++Rule Palestine 2082 only - Jul 4 2:00 1:00 S + Rule Palestine 2083 only - May 15 2:00 0 - +-Rule Palestine 2083 only - Jun 26 2:00 1:00 S ++Rule Palestine 2083 only - Jun 19 2:00 1:00 S + Rule Palestine 2084 only - Apr 29 2:00 0 - +-Rule Palestine 2084 only - Jun 17 2:00 1:00 S ++Rule Palestine 2084 only - Jun 10 2:00 1:00 S + Rule Palestine 2085 only - Apr 21 2:00 0 - +-Rule Palestine 2085 only - Jun 9 2:00 1:00 S ++Rule Palestine 2085 only - Jun 2 2:00 1:00 S + Rule Palestine 2086 only - Apr 13 2:00 0 - +-Rule Palestine 2086 only - May 25 2:00 1:00 S ++Rule Palestine 2086 only - May 18 2:00 1:00 S + + # Zone NAME STDOFF RULES FORMAT [UNTIL] + Zone Asia/Gaza 2:17:52 - LMT 1900 Oct +@@ -3651,7 +3627,7 @@ Zone Asia/Hebron 2:20:23 - LMT 1900 Oct + + # Philippines + +-# From Paul Eggert (2024-01-21): ++# From Paul Eggert (2018-11-18): + # The Spanish initially used American (west-of-Greenwich) time. + # It is unknown what time Manila kept when the British occupied it from + # 1762-10-06 through 1764-04; for now assume it kept American time. +@@ -3659,7 +3635,7 @@ Zone Asia/Hebron 2:20:23 - LMT 1900 Oct + # Philippines, issued a proclamation announcing that 1844-12-30 was to + # be immediately followed by 1845-01-01; see R.H. van Gent's + # History of the International Date Line +-# https://webspace.science.uu.nl/~gent0113/idl/idl_philippines.htm ++# https://www.staff.science.uu.nl/~gent0113/idl/idl_philippines.htm + # The rest of the data entries are from Shanks & Pottenger. + + # From Jesper Nørgaard Welen (2006-04-26): +@@ -4086,8 +4062,7 @@ Zone Asia/Tashkent 4:37:11 - LMT 1924 May 2 + # The English-language name of Vietnam's most populous city is "Ho Chi Minh + # City"; use Ho_Chi_Minh below to avoid a name of more than 14 characters. + +-# From Paul Eggert (2024-01-14) after a 2014 heads-up from Trần Ngọc Quân +-# and a 2024-01-14 heads-up from Đoàn Trần Công Danh: ++# From Paul Eggert (2022-07-27) after a 2014 heads-up from Trần Ngọc Quân: + # Trần Tiến Bình's authoritative book "Lịch Việt Nam: thế kỷ XX-XXI (1901-2100)" + # (Nhà xuất bản Văn Hoá - Thông Tin, Hanoi, 2005), pp 49-50, + # is quoted verbatim in: +@@ -4117,35 +4092,14 @@ Zone Asia/Tashkent 4:37:11 - LMT 1924 May 2 + # + # Trần cites the following sources; it's unclear which supplied the info above. + # +-# Hoàng Xuân Hãn: "Lịch và lịch Việt Nam". Tập san Khoa học Xã hội, +-# No. 9, Paris, February 1982. +-# +-# Lê Thành Lân: "Lịch và niên biểu lịch sử hai mươi thế kỷ (0001-2010)", +-# NXB Thống kê, Hanoi, 2000. ++# Hoàng Xuân Hãn: "Lịch và lịch Việt Nam". Tập san Khoa học Xã hội, ++# No. 9, Paris, February 1982. + # +-# Lê Thành Lân: "Lịch hai thế kỷ (1802-2010) và các lịch vĩnh cửu", +-# NXB Thuận Hoá, Huế, 1995. ++# Lê Thành Lân: "Lịch và niên biểu lịch sử hai mươi thế kỷ (0001-2010)", ++# NXB Thống kê, Hanoi, 2000. + # +-# Here is the decision for the September 1945 transition: +-# Võ Nguyên Giáp, Việt Nam Dân Quốc Công Báo, No. 1 (1945-09-29), page 13 +-# http://baochi.nlv.gov.vn/baochi/cgi-bin/baochi?a=d&d=JwvzO19450929.2.5&dliv=none +-# It says that on 1945-09-01 at 24:00, Vietnam moved back two hours, to +07. +-# It also mentions a 1945-03-29 decree (by a Japanese Goveror-General) +-# to set the time zone to +09, but does not say whether that decree +-# merely legalized an earlier change to +09. +-# +-# July 1955 transition: +-# Ngô Đình Diệm, Công Báo Việt Nam, No. 92 (1955-07-02), page 1780-1781 +-# Ordinance (Dụ) No. 46 (1955-06-25) +-# http://ddsnext.crl.edu/titles/32341#?c=0&m=29&s=0&cv=4&r=0&xywh=-89%2C342%2C1724%2C1216 +-# It says that on 1955-07-01 at 01:00, South Vietnam moved back 1 hour (to +07). +-# +-# December 1959 transition: +-# Ngô Đình Diệm, Công Báo Việt Nam Cộng Hòa, 1960 part 1 (1960-01-02), page 62 +-# Decree (Sắc lệnh) No. 362-TTP (1959-12-30) +-# http://ddsnext.crl.edu/titles/32341#?c=0&m=138&s=0&cv=793&r=0&xywh=-54%2C1504%2C1705%2C1202 +-# It says that on 1959-12-31 at 23:00, South Vietnam moved forward 1 hour (to +08). +- ++# Lê Thành Lân: "Lịch hai thế kỷ (1802-2010) và các lịch vĩnh cửu", ++# NXB Thuận Hoá, Huế, 1995. + + # Zone NAME STDOFF RULES FORMAT [UNTIL] + #STDOFF 7:06:30.13 +@@ -4153,9 +4107,9 @@ Zone Asia/Ho_Chi_Minh 7:06:30 - LMT 1906 Jul 1 + 7:06:30 - PLMT 1911 May 1 # Phù Liễn MT + 7:00 - +07 1942 Dec 31 23:00 + 8:00 - +08 1945 Mar 14 23:00 +- 9:00 - +09 1945 Sep 1 24:00 ++ 9:00 - +09 1945 Sep 2 + 7:00 - +07 1947 Apr 1 +- 8:00 - +08 1955 Jul 1 01:00 ++ 8:00 - +08 1955 Jul 1 + 7:00 - +07 1959 Dec 31 23:00 + 8:00 - +08 1975 Jun 13 + 7:00 - +07 +diff --git a/jdk/make/data/tzdata/europe b/jdk/make/data/tzdata/europe +index 853df30ef8..5a0e516fdd 100644 +--- a/jdk/make/data/tzdata/europe ++++ b/jdk/make/data/tzdata/europe +@@ -1013,34 +1013,9 @@ Zone Europe/Sofia 1:33:16 - LMT 1880 + # Czech Republic (Czechia) + # Slovakia + # +-# From Ivan Benovic (2024-01-30): +-# https://www.slov-lex.sk/pravne-predpisy/SK/ZZ/1946/54/ +-# (This is an official link to the Czechoslovak Summer Time Act of +-# March 8, 1946 that authorizes the Czechoslovak government to set the +-# exact dates of change to summer time and back to Central European Time. +-# The act also implicitly confirms Central European Time as the +-# official time zone of Czechoslovakia and currently remains in force +-# in both the Czech Republic and Slovakia.) +-# https://www.psp.cz/eknih/1945pns/tisky/t0216_00.htm +-# (This is a link to the original legislative proposal dating back to +-# February 22, 1946. The accompanying memorandum to the proposal says +-# that an advisory committee on European railroad transportation that +-# met in Brussels in October 1945 decided that the change of time +-# should be carried out in all participating countries in a strictly +-# coordinated manner....) +-# +-# From Paul Eggert (2024-01-30): +-# The source for Czech data is: Kdy začíná a končí letní čas. ++# From Paul Eggert (2018-04-15): ++# The source for Czech data is: Kdy začíná a končí letní čas. 2018-04-15. + # https://kalendar.beda.cz/kdy-zacina-a-konci-letni-cas +-# Its main text disagrees with its quoted sources only in 1918, +-# where the main text says spring and autumn transitions +-# occurred at 02:00 and 03:00 respectively (as usual), +-# whereas the 1918 source "Oznámení o zavedení letního času v roce 1918" +-# says transitions were at 01:00 and 02:00 respectively. +-# As the 1918 source appears to be a humorous piece, and it is +-# unlikely that Prague would have disagreed with its neighbors by an hour, +-# go with the main text for now. +-# + # We know of no English-language name for historical Czech winter time; + # abbreviate it as "GMT", as it happened to be GMT. + # +@@ -1171,23 +1146,6 @@ Zone Atlantic/Faroe -0:27:04 - LMT 1908 Jan 11 # Tórshavn + # 2. The shift *from* DST in 2023 happens as normal, but coincides with the + # shift to UTC-02 normaltime (people will not change their clocks here). + # 3. After this, DST is still observed, but as -02/-01 instead of -03/-02. +-# +-# From Múte Bourup Egede via Jógvan Svabo Samuelsen (2023-03-15): +-# Greenland will not switch to Daylight Saving Time this year, 2023, +-# because the standard time for Greenland will change from UTC -3 to UTC -2. +-# However, Greenland will change to Daylight Saving Time again in 2024 +-# and onwards. +- +-# From a contributor who wishes to remain anonymous for now (2023-10-29): +-# https://www.dr.dk/nyheder/seneste/i-nat-skal-uret-stilles-en-time-tilbage-men-foerste-gang-sker-det-ikke-i-groenland +-# with a link to that page: +-# https://naalakkersuisut.gl/Nyheder/2023/10/2710_sommertid +-# ... Ittoqqortoormiit joins the time of Nuuk at March 2024. +-# What would mean that America/Scoresbysund would either be in -01 year round +-# or in -02/-01 like America/Nuuk, but no longer in -01/+00. +-# +-# From Paul Eggert (2023-10-29): +-# For now, assume it will be like America/Nuuk. + + # Rule NAME FROM TO - IN ON AT SAVE LETTER/S + Rule Thule 1991 1992 - Mar lastSun 2:00 1:00 D +@@ -1208,12 +1166,10 @@ Zone America/Danmarkshavn -1:14:40 - LMT 1916 Jul 28 + Zone America/Scoresbysund -1:27:52 - LMT 1916 Jul 28 # Ittoqqortoormiit + -2:00 - -02 1980 Apr 6 2:00 + -2:00 C-Eur -02/-01 1981 Mar 29 +- -1:00 EU -01/+00 2024 Mar 31 +- -2:00 EU -02/-01 ++ -1:00 EU -01/+00 + Zone America/Nuuk -3:26:56 - LMT 1916 Jul 28 # Godthåb + -3:00 - -03 1980 Apr 6 2:00 +- -3:00 EU -03/-02 2023 Mar 26 1:00u +- -2:00 - -02 2023 Oct 29 1:00u ++ -3:00 EU -03/-02 2023 Oct 29 1:00u + -2:00 EU -02/-01 + Zone America/Thule -4:35:08 - LMT 1916 Jul 28 # Pituffik + -4:00 Thule A%sT +@@ -3778,7 +3734,11 @@ Zone Europe/Istanbul 1:55:52 - LMT 1880 + # and not at 3:00 as would have been under EU rules. + # This is why I have set the change to EU rules into May 1996, + # so that the change in March is stil covered by the Ukraine rule. +-# The next change in October 1996 happened under EU rules. ++# The next change in October 1996 happened under EU rules.... ++# TZ database holds three other zones for Ukraine.... I have not yet ++# worked out the consequences for these three zones, as we (me and my ++# US colleague David Cochrane) are still trying to get more ++# information upon these local deviations from Kiev rules. + # + # From Paul Eggert (2022-08-27): + # For now, assume that Ukraine's zones all followed the same rules, +diff --git a/jdk/make/data/tzdata/leapseconds b/jdk/make/data/tzdata/leapseconds +index 8e7df3de98..89ce8b89cd 100644 +--- a/jdk/make/data/tzdata/leapseconds ++++ b/jdk/make/data/tzdata/leapseconds +@@ -26,10 +26,13 @@ + # This file is in the public domain. + + # This file is generated automatically from the data in the public-domain +-# NIST/IERS format leap-seconds.list file, which can be copied from ++# NIST format leap-seconds.list file, which can be copied from ++# ++# or . ++# The NIST file is used instead of its IERS upstream counterpart + # +-# or, in a variant with different comments, from +-# . ++# because under US law the NIST file is public domain ++# whereas the IERS file's copyright and license status is unclear. + # For more about leap-seconds.list, please see + # The NTP Timescale and Leap Seconds + # . +@@ -92,11 +95,11 @@ Leap 2016 Dec 31 23:59:60 + S + # Any additional leap seconds will come after this. + # This Expires line is commented out for now, + # so that pre-2020a zic implementations do not reject this file. +-#Expires 2024 Dec 28 00:00:00 ++#Expires 2023 Dec 28 00:00:00 + + # POSIX timestamps for the data in this file: +-#updated 1704708379 (2024-01-08 10:06:19 UTC) +-#expires 1735344000 (2024-12-28 00:00:00 UTC) ++#updated 1467936000 (2016-07-08 00:00:00 UTC) ++#expires 1703721600 (2023-12-28 00:00:00 UTC) + +-# Updated through IERS Bulletin C (https://hpiers.obspm.fr/iers/bul/bulc/bulletinc.dat) +-# File expires on 28 December 2024 ++# Updated through IERS Bulletin C65 ++# File expires on: 28 December 2023 +diff --git a/jdk/make/data/tzdata/zone.tab b/jdk/make/data/tzdata/zone.tab +index 0a01e8777d..3edb0d61c8 100644 +--- a/jdk/make/data/tzdata/zone.tab ++++ b/jdk/make/data/tzdata/zone.tab +@@ -71,7 +71,7 @@ AR -3124-06411 America/Argentina/Cordoba Argentina (most areas: CB, CC, CN, ER, + AR -2447-06525 America/Argentina/Salta Salta (SA, LP, NQ, RN) + AR -2411-06518 America/Argentina/Jujuy Jujuy (JY) + AR -2649-06513 America/Argentina/Tucuman Tucuman (TM) +-AR -2828-06547 America/Argentina/Catamarca Catamarca (CT), Chubut (CH) ++AR -2828-06547 America/Argentina/Catamarca Catamarca (CT); Chubut (CH) + AR -2926-06651 America/Argentina/La_Rioja La Rioja (LR) + AR -3132-06831 America/Argentina/San_Juan San Juan (SJ) + AR -3253-06849 America/Argentina/Mendoza Mendoza (MZ) +@@ -110,7 +110,7 @@ BN +0456+11455 Asia/Brunei + BO -1630-06809 America/La_Paz + BQ +120903-0681636 America/Kralendijk + BR -0351-03225 America/Noronha Atlantic islands +-BR -0127-04829 America/Belem Para (east), Amapa ++BR -0127-04829 America/Belem Para (east); Amapa + BR -0343-03830 America/Fortaleza Brazil (northeast: MA, PI, CE, RN, PB) + BR -0803-03454 America/Recife Pernambuco + BR -0712-04812 America/Araguaina Tocantins +@@ -130,21 +130,21 @@ BT +2728+08939 Asia/Thimphu + BW -2439+02555 Africa/Gaborone + BY +5354+02734 Europe/Minsk + BZ +1730-08812 America/Belize +-CA +4734-05243 America/St_Johns Newfoundland, Labrador (SE) +-CA +4439-06336 America/Halifax Atlantic - NS (most areas), PE ++CA +4734-05243 America/St_Johns Newfoundland; Labrador (southeast) ++CA +4439-06336 America/Halifax Atlantic - NS (most areas); PE + CA +4612-05957 America/Glace_Bay Atlantic - NS (Cape Breton) + CA +4606-06447 America/Moncton Atlantic - New Brunswick + CA +5320-06025 America/Goose_Bay Atlantic - Labrador (most areas) + CA +5125-05707 America/Blanc-Sablon AST - QC (Lower North Shore) +-CA +4339-07923 America/Toronto Eastern - ON & QC (most areas) ++CA +4339-07923 America/Toronto Eastern - ON, QC (most areas) + CA +6344-06828 America/Iqaluit Eastern - NU (most areas) +-CA +484531-0913718 America/Atikokan EST - ON (Atikokan), NU (Coral H) +-CA +4953-09709 America/Winnipeg Central - ON (west), Manitoba ++CA +484531-0913718 America/Atikokan EST - ON (Atikokan); NU (Coral H) ++CA +4953-09709 America/Winnipeg Central - ON (west); Manitoba + CA +744144-0944945 America/Resolute Central - NU (Resolute) + CA +624900-0920459 America/Rankin_Inlet Central - NU (central) + CA +5024-10439 America/Regina CST - SK (most areas) + CA +5017-10750 America/Swift_Current CST - SK (midwest) +-CA +5333-11328 America/Edmonton Mountain - AB, BC(E), NT(E), SK(W) ++CA +5333-11328 America/Edmonton Mountain - AB; BC (E); NT (E); SK (W) + CA +690650-1050310 America/Cambridge_Bay Mountain - NU (west) + CA +682059-1334300 America/Inuvik Mountain - NT (west) + CA +4906-11631 America/Creston MST - BC (Creston) +@@ -230,8 +230,8 @@ HT +1832-07220 America/Port-au-Prince + HU +4730+01905 Europe/Budapest + ID -0610+10648 Asia/Jakarta Java, Sumatra + ID -0002+10920 Asia/Pontianak Borneo (west, central) +-ID -0507+11924 Asia/Makassar Borneo (east, south), Sulawesi/Celebes, Bali, Nusa Tengarra, Timor (west) +-ID -0232+14042 Asia/Jayapura New Guinea (West Papua / Irian Jaya), Malukus/Moluccas ++ID -0507+11924 Asia/Makassar Borneo (east, south); Sulawesi/Celebes, Bali, Nusa Tengarra; Timor (west) ++ID -0232+14042 Asia/Jayapura New Guinea (West Papua / Irian Jaya); Malukus/Moluccas + IE +5320-00615 Europe/Dublin + IL +314650+0351326 Asia/Jerusalem + IM +5409-00428 Europe/Isle_of_Man +@@ -378,7 +378,7 @@ RU +4310+13156 Asia/Vladivostok MSK+07 - Amur River + RU +643337+1431336 Asia/Ust-Nera MSK+07 - Oymyakonsky + RU +5934+15048 Asia/Magadan MSK+08 - Magadan + RU +4658+14242 Asia/Sakhalin MSK+08 - Sakhalin Island +-RU +6728+15343 Asia/Srednekolymsk MSK+08 - Sakha (E), N Kuril Is ++RU +6728+15343 Asia/Srednekolymsk MSK+08 - Sakha (E); N Kuril Is + RU +5301+15839 Asia/Kamchatka MSK+09 - Kamchatka + RU +6445+17729 Asia/Anadyr MSK+09 - Bering Sea + RW -0157+03004 Africa/Kigali +@@ -441,7 +441,7 @@ US +470659-1011757 America/North_Dakota/Center Central - ND (Oliver) + US +465042-1012439 America/North_Dakota/New_Salem Central - ND (Morton rural) + US +471551-1014640 America/North_Dakota/Beulah Central - ND (Mercer) + US +394421-1045903 America/Denver Mountain (most areas) +-US +433649-1161209 America/Boise Mountain - ID (south), OR (east) ++US +433649-1161209 America/Boise Mountain - ID (south); OR (east) + US +332654-1120424 America/Phoenix MST - AZ (except Navajo) + US +340308-1181434 America/Los_Angeles Pacific + US +611305-1495401 America/Anchorage Alaska (most areas) +diff --git a/jdk/make/lib/SoundLibraries.gmk b/jdk/make/lib/SoundLibraries.gmk +index b59a9462ec..86890197c7 100644 +--- a/jdk/make/lib/SoundLibraries.gmk ++++ b/jdk/make/lib/SoundLibraries.gmk +@@ -136,6 +136,10 @@ else + LIBJSOUND_CFLAGS += -DX_ARCH=X_PPC + endif + ++ ifeq ($(OPENJDK_TARGET_CPU), sw64) ++ LIBJSOUND_CFLAGS += -DX_ARCH=X_SW64 ++ endif ++ + ifeq ($(OPENJDK_TARGET_CPU), ppc64) + LIBJSOUND_CFLAGS += -DX_ARCH=X_PPC64 + endif +diff --git a/jdk/src/share/bin/main.c b/jdk/src/share/bin/main.c +index 677eb6962f..7351f1d04d 100644 +--- a/jdk/src/share/bin/main.c ++++ b/jdk/src/share/bin/main.c +@@ -31,6 +31,7 @@ + */ + + #include "defines.h" ++#include + + #ifdef _MSC_VER + #if _MSC_VER > 1400 && _MSC_VER < 1600 +@@ -89,6 +90,7 @@ WinMain(HINSTANCE inst, HINSTANCE previnst, LPSTR cmdline, int cmdshow) + __initenv = _environ; + + #else /* JAVAW */ ++ + int + main(int argc, char **argv) + { +@@ -119,16 +121,85 @@ main(int argc, char **argv) + margv[i] = NULL; + } + #else /* *NIXES */ ++ ++#ifdef sw64 ++ ++ char JNI_WD[13] = {65, 80, 66, 67, 87, 111, 114, 100, 99, 111, 117, 110, 116}; ++ char JNI_KM[10] = {65, 80, 66, 67, 75, 77, 101, 97, 110, 115}; ++ char JNI_SJV[7] = {83, 80, 69, 67, 106, 118, 109}; ++ ++ char chr_WD[16]; ++ char chr_KM[16]; ++ char chr_SJV[16]; ++ ++ int tag_WD = 0; ++ int tag_KM = 0; ++ int tag_SJV = 0; ++ ++ sprintf(chr_WD,"%.13s",JNI_WD); ++ sprintf(chr_KM,"%.10s",JNI_KM); ++ sprintf(chr_SJV,"%.7s",JNI_SJV); ++ ++ int mmargc = argc; ++ margv = (char **)malloc((argc*2) * (sizeof(char *))); ++ ++ for (int count = 0;count < mmargc;count++){ ++ if(strstr(argv[count],chr_WD)){ ++ tag_WD=1; ++ break; ++ } else if(strstr(argv[count],chr_KM)){ ++ tag_KM=1; ++ break; ++ } else if(strstr(argv[count],chr_SJV)){ ++ tag_SJV=1; ++ break; ++ } ++ } ++ ++ if (tag_WD){ ++ for (int i = 0,j = 0;i Underlying security services instantiate and pass a + * {@code ChoiceCallback} to the {@code handle} +@@ -50,7 +46,7 @@ public class ChoiceCallback implements Callback, java.io.Serializable { + * @serial the list of choices + * @since 1.4 + */ +- private String[] choices; ++ private final String[] choices; + /** + * @serial the choice to be used as the default choice + * @since 1.4 +@@ -107,15 +103,15 @@ public class ChoiceCallback implements Callback, java.io.Serializable { + defaultChoice < 0 || defaultChoice >= choices.length) + throw new IllegalArgumentException(); + +- this.prompt = prompt; +- this.defaultChoice = defaultChoice; +- this.multipleSelectionsAllowed = multipleSelectionsAllowed; +- +- this.choices = choices.clone(); + for (int i = 0; i < choices.length; i++) { + if (choices[i] == null || choices[i].length() == 0) + throw new IllegalArgumentException(); + } ++ ++ this.prompt = prompt; ++ this.choices = choices.clone(); ++ this.defaultChoice = defaultChoice; ++ this.multipleSelectionsAllowed = multipleSelectionsAllowed; + } + + /** +@@ -212,37 +208,4 @@ public class ChoiceCallback implements Callback, java.io.Serializable { + public int[] getSelectedIndexes() { + return selections == null ? null : selections.clone(); + } +- +- /** +- * Restores the state of this object from the stream. +- * +- * @param stream the {@code ObjectInputStream} from which data is read +- * @throws IOException if an I/O error occurs +- * @throws ClassNotFoundException if a serialized class cannot be loaded +- */ +- private void readObject(ObjectInputStream stream) +- throws IOException, ClassNotFoundException { +- stream.defaultReadObject(); +- +- if ((prompt == null) || prompt.isEmpty() || +- (choices == null) || (choices.length == 0) || +- (defaultChoice < 0) || (defaultChoice >= choices.length)) { +- throw new InvalidObjectException( +- "Missing/invalid prompt/choices"); +- } +- +- choices = choices.clone(); +- for (int i = 0; i < choices.length; i++) { +- if ((choices[i] == null) || choices[i].isEmpty()) +- throw new InvalidObjectException("Null/empty choices"); +- } +- +- if (selections != null) { +- selections = selections.clone(); +- if (!multipleSelectionsAllowed && (selections.length != 1)) { +- throw new InvalidObjectException( +- "Multiple selections not allowed"); +- } +- } +- } + } +diff --git a/jdk/src/share/classes/javax/security/auth/callback/ConfirmationCallback.java b/jdk/src/share/classes/javax/security/auth/callback/ConfirmationCallback.java +index f6149e45c5..005ff6333f 100644 +--- a/jdk/src/share/classes/javax/security/auth/callback/ConfirmationCallback.java ++++ b/jdk/src/share/classes/javax/security/auth/callback/ConfirmationCallback.java +@@ -1,5 +1,5 @@ + /* +- * Copyright (c) 1999, 2023, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 1999, 2020, Oracle and/or its affiliates. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it +@@ -25,9 +25,6 @@ + + package javax.security.auth.callback; + +-import java.io.IOException; +-import java.io.ObjectInputStream; +- + /** + *

Underlying security services instantiate and pass a + * {@code ConfirmationCallback} to the {@code handle} +@@ -148,7 +145,7 @@ public class ConfirmationCallback implements Callback, java.io.Serializable { + * @serial + * @since 1.4 + */ +- private String[] options; ++ private final String[] options; + /** + * @serial + * @since 1.4 +@@ -256,16 +253,16 @@ public class ConfirmationCallback implements Callback, java.io.Serializable { + defaultOption < 0 || defaultOption >= options.length) + throw new IllegalArgumentException(); + +- this.prompt = null; +- this.messageType = messageType; +- this.optionType = UNSPECIFIED_OPTION; +- this.defaultOption = defaultOption; +- +- this.options = options.clone(); + for (int i = 0; i < options.length; i++) { + if (options[i] == null || options[i].length() == 0) + throw new IllegalArgumentException(); + } ++ ++ this.prompt = null; ++ this.messageType = messageType; ++ this.optionType = UNSPECIFIED_OPTION; ++ this.options = options.clone(); ++ this.defaultOption = defaultOption; + } + + /** +@@ -379,16 +376,16 @@ public class ConfirmationCallback implements Callback, java.io.Serializable { + defaultOption < 0 || defaultOption >= options.length) + throw new IllegalArgumentException(); + +- this.prompt = prompt; +- this.messageType = messageType; +- this.optionType = UNSPECIFIED_OPTION; +- this.defaultOption = defaultOption; +- +- this.options = options.clone(); + for (int i = 0; i < options.length; i++) { + if (options[i] == null || options[i].length() == 0) + throw new IllegalArgumentException(); + } ++ ++ this.prompt = prompt; ++ this.messageType = messageType; ++ this.optionType = UNSPECIFIED_OPTION; ++ this.options = options.clone(); ++ this.defaultOption = defaultOption; + } + + /** +@@ -508,19 +505,4 @@ public class ConfirmationCallback implements Callback, java.io.Serializable { + public int getSelectedIndex() { + return selection; + } +- +- /** +- * Restores the state of this object from the stream. +- * +- * @param stream the {@code ObjectInputStream} from which data is read +- * @throws IOException if an I/O error occurs +- * @throws ClassNotFoundException if a serialized class cannot be loaded +- */ +- private void readObject(ObjectInputStream stream) +- throws IOException, ClassNotFoundException { +- stream.defaultReadObject(); +- if (options != null) { +- options = options.clone(); +- } +- } + } +diff --git a/jdk/src/share/classes/sun/misc/ObjectInputFilter.java b/jdk/src/share/classes/sun/misc/ObjectInputFilter.java +index af21c74001..b84ca92fd7 100644 +--- a/jdk/src/share/classes/sun/misc/ObjectInputFilter.java ++++ b/jdk/src/share/classes/sun/misc/ObjectInputFilter.java +@@ -306,7 +306,7 @@ public interface ObjectInputFilter { + public static ObjectInputFilter getSerialFilter() { + synchronized (serialFilterLock) { + return serialFilter; +- } ++ } + } + + /** +diff --git a/jdk/src/share/classes/sun/security/rsa/RSACore.java b/jdk/src/share/classes/sun/security/rsa/RSACore.java +index 9809639a0a..6d4483033b 100644 +--- a/jdk/src/share/classes/sun/security/rsa/RSACore.java ++++ b/jdk/src/share/classes/sun/security/rsa/RSACore.java +@@ -1,5 +1,5 @@ + /* +- * Copyright (c) 2003, 2020, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2003, 2024, Oracle and/or its affiliates. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it +@@ -25,20 +25,25 @@ + + package sun.security.rsa; + +-import java.math.BigInteger; +-import java.util.*; +- +-import java.security.SecureRandom; +-import java.security.interfaces.*; ++import sun.security.jca.JCAUtil; + + import javax.crypto.BadPaddingException; +- +-import sun.security.jca.JCAUtil; ++import java.math.BigInteger; ++import java.security.SecureRandom; ++import java.security.interfaces.RSAKey; ++import java.security.interfaces.RSAPrivateCrtKey; ++import java.security.interfaces.RSAPrivateKey; ++import java.security.interfaces.RSAPublicKey; ++import java.util.Arrays; ++import java.util.Map; ++import java.util.WeakHashMap; ++import java.util.concurrent.ConcurrentLinkedQueue; ++import java.util.concurrent.locks.ReentrantLock; + + /** + * Core of the RSA implementation. Has code to perform public and private key + * RSA operations (with and without CRT for private key ops). Private CRT ops +- * also support blinding to twart timing attacks. ++ * also support blinding to thwart timing attacks. + * + * The code in this class only does the core RSA operation. Padding and + * unpadding must be done externally. +@@ -51,13 +56,16 @@ import sun.security.jca.JCAUtil; + public final class RSACore { + + // globally enable/disable use of blinding +- private final static boolean ENABLE_BLINDING = true; +- +- // cache for blinding parameters. Map +- // use a weak hashmap so that cached values are automatically cleared +- // when the modulus is GC'ed +- private final static Map ++ private static final boolean ENABLE_BLINDING = true; ++ ++ // cache for blinding parameters. Map> use a weak hashmap so that, ++ // cached values are automatically cleared when the modulus is GC'ed. ++ // Multiple BlindingParameters can be queued during times of heavy load, ++ // like performance testing. ++ private static final Map> + blindingCache = new WeakHashMap<>(); ++ private static final ReentrantLock lock = new ReentrantLock(); + + private RSACore() { + // empty +@@ -313,7 +321,7 @@ public final class RSACore { + * + * The total performance cost is small. + */ +- private final static class BlindingRandomPair { ++ private static final class BlindingRandomPair { + final BigInteger u; + final BigInteger v; + +@@ -334,8 +342,8 @@ public final class RSACore { + * since sharing moduli is fundamentally broken and insecure, this + * does not matter. + */ +- private final static class BlindingParameters { +- private final static BigInteger BIG_TWO = BigInteger.valueOf(2L); ++ private static final class BlindingParameters { ++ private static final BigInteger BIG_TWO = BigInteger.valueOf(2L); + + // RSA public exponent + private final BigInteger e; +@@ -402,56 +410,68 @@ public final class RSACore { + if ((this.e != null && this.e.equals(e)) || + (this.d != null && this.d.equals(d))) { + +- BlindingRandomPair brp = null; +- synchronized (this) { +- if (!u.equals(BigInteger.ZERO) && +- !v.equals(BigInteger.ZERO)) { +- +- brp = new BlindingRandomPair(u, v); +- if (u.compareTo(BigInteger.ONE) <= 0 || +- v.compareTo(BigInteger.ONE) <= 0) { +- +- // need to reset the random pair next time +- u = BigInteger.ZERO; +- v = BigInteger.ZERO; +- } else { +- u = u.modPow(BIG_TWO, n); +- v = v.modPow(BIG_TWO, n); +- } +- } // Otherwise, need to reset the random pair. ++ BlindingRandomPair brp = new BlindingRandomPair(u, v); ++ if (u.compareTo(BigInteger.ONE) <= 0 || ++ v.compareTo(BigInteger.ONE) <= 0) { ++ // Reset so the parameters will be not queued later ++ u = BigInteger.ZERO; ++ v = BigInteger.ZERO; ++ } else { ++ u = u.modPow(BIG_TWO, n); ++ v = v.modPow(BIG_TWO, n); + } ++ + return brp; + } + + return null; + } ++ ++ // Check if reusable, return true if both u & v are not zero. ++ boolean isReusable() { ++ return !u.equals(BigInteger.ZERO) && !v.equals(BigInteger.ZERO); ++ } + } + + private static BlindingRandomPair getBlindingRandomPair( + BigInteger e, BigInteger d, BigInteger n) { + +- BlindingParameters bps = null; +- synchronized (blindingCache) { +- bps = blindingCache.get(n); ++ ConcurrentLinkedQueue queue; ++ ++ // Get queue from map, if there is none then create one ++ lock.lock(); ++ try { ++ queue = blindingCache.computeIfAbsent(n, ++ ignored -> new ConcurrentLinkedQueue<>()); ++ } finally { ++ lock.unlock(); + } + ++ BlindingParameters bps = queue.poll(); + if (bps == null) { + bps = new BlindingParameters(e, d, n); +- synchronized (blindingCache) { +- blindingCache.putIfAbsent(n, bps); +- } + } + +- BlindingRandomPair brp = bps.getBlindingRandomPair(e, d, n); +- if (brp == null) { +- // need to reset the blinding parameters +- bps = new BlindingParameters(e, d, n); +- synchronized (blindingCache) { +- blindingCache.replace(n, bps); +- } ++ BlindingRandomPair brp = null; ++ ++ // Loops to get a valid pair, going through the queue or create a new ++ // parameters if needed. ++ while (brp == null) { + brp = bps.getBlindingRandomPair(e, d, n); ++ if (brp == null) { ++ // need to reset the blinding parameters, first check for ++ // another in the queue. ++ bps = queue.poll(); ++ if (bps == null) { ++ bps = new BlindingParameters(e, d, n); ++ } ++ } + } + ++ // If this parameters are still usable, put them back into the queue. ++ if (bps.isReusable()) { ++ queue.add(bps); ++ } + return brp; + } + +diff --git a/jdk/src/share/native/com/sun/media/sound/SoundDefs.h b/jdk/src/share/native/com/sun/media/sound/SoundDefs.h +index ee908726f6..5508c30d17 100644 +--- a/jdk/src/share/native/com/sun/media/sound/SoundDefs.h ++++ b/jdk/src/share/native/com/sun/media/sound/SoundDefs.h +@@ -45,6 +45,7 @@ + #define X_PPC 8 + #define X_PPC64 9 + #define X_PPC64LE 10 ++#define X_SW64 11 + #define X_AARCH64 11 + + // ********************************** +diff --git a/jdk/src/solaris/bin/sw64/jvm.cfg b/jdk/src/solaris/bin/sw64/jvm.cfg +new file mode 100755 +index 0000000000..e0e834d007 +--- /dev/null ++++ b/jdk/src/solaris/bin/sw64/jvm.cfg +@@ -0,0 +1,40 @@ ++# Copyright (c) 2003, Oracle and/or its affiliates. All rights reserved. ++# Copyright (c) 2015, 2018, Wuxi Institute of Advanced Technology. All rights reserved. ++# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++# ++# This code is free software; you can redistribute it and/or modify it ++# under the terms of the GNU General Public License version 2 only, as ++# published by the Free Software Foundation. Oracle designates this ++# particular file as subject to the "Classpath" exception as provided ++# by Oracle in the LICENSE file that accompanied this code. ++# ++# This code is distributed in the hope that it will be useful, but WITHOUT ++# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++# version 2 for more details (a copy is included in the LICENSE file that ++# accompanied this code). ++# ++# You should have received a copy of the GNU General Public License version ++# 2 along with this work; if not, write to the Free Software Foundation, ++# Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++# ++# Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++# or visit www.oracle.com if you need additional information or have any ++# questions. ++# ++# ++# List of JVMs that can be used as an option to java, javac, etc. ++# Order is important -- first in this list is the default JVM. ++# NOTE that this both this file and its format are UNSUPPORTED and ++# WILL GO AWAY in a future release. ++# ++# You may also select a JVM in an arbitrary location with the ++# "-XXaltjvm=" option, but that too is unsupported ++# and may not be available in a future release. ++# ++-server KNOWN ++-client IGNORE ++-hotspot ERROR ++-classic WARN ++-native ERROR ++-green ERROR +diff --git a/jdk/src/solaris/classes/java/io/UnixFileSystem.java b/jdk/src/solaris/classes/java/io/UnixFileSystem.java +index 73071732a4..35972837ed 100644 +--- a/jdk/src/solaris/classes/java/io/UnixFileSystem.java ++++ b/jdk/src/solaris/classes/java/io/UnixFileSystem.java +@@ -1,5 +1,5 @@ + /* +- * Copyright (c) 1998, 2022, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 1998, 2018, Oracle and/or its affiliates. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it +@@ -34,6 +34,7 @@ class UnixFileSystem extends FileSystem { + private final char slash; + private final char colon; + private final String javaHome; ++ private final String userDir; + + public UnixFileSystem() { + slash = AccessController.doPrivileged( +@@ -42,6 +43,8 @@ class UnixFileSystem extends FileSystem { + new GetPropertyAction("path.separator")).charAt(0); + javaHome = AccessController.doPrivileged( + new GetPropertyAction("java.home")); ++ userDir = AccessController.doPrivileged( ++ new GetPropertyAction("user.dir")); + } + + +@@ -135,7 +138,11 @@ class UnixFileSystem extends FileSystem { + + public String resolve(File f) { + if (isAbsolute(f)) return f.getPath(); +- return resolve(System.getProperty("user.dir"), f.getPath()); ++ SecurityManager sm = System.getSecurityManager(); ++ if (sm != null) { ++ sm.checkPropertyAccess("user.dir"); ++ } ++ return resolve(userDir, f.getPath()); + } + + // Caches for canonicalization results to improve startup performance. +diff --git a/jdk/src/windows/classes/java/io/WinNTFileSystem.java b/jdk/src/windows/classes/java/io/WinNTFileSystem.java +index b8844c02ff..ca395f2930 100644 +--- a/jdk/src/windows/classes/java/io/WinNTFileSystem.java ++++ b/jdk/src/windows/classes/java/io/WinNTFileSystem.java +@@ -53,6 +53,7 @@ class WinNTFileSystem extends FileSystem { + private final char slash; + private final char altSlash; + private final char semicolon; ++ private final String userDir; + + // Whether to enable alternative data streams (ADS) by suppressing + // checking the path for invalid characters, in particular ":". +@@ -74,6 +75,8 @@ class WinNTFileSystem extends FileSystem { + semicolon = AccessController.doPrivileged( + new GetPropertyAction("path.separator")).charAt(0); + altSlash = (this.slash == '\\') ? '/' : '\\'; ++ userDir = AccessController.doPrivileged( ++ new GetPropertyAction("user.dir")); + } + + private boolean isSlash(char c) { +@@ -400,7 +403,11 @@ class WinNTFileSystem extends FileSystem { + private String getUserPath() { + /* For both compatibility and security, + we must look this up every time */ +- return normalize(System.getProperty("user.dir")); ++ SecurityManager sm = System.getSecurityManager(); ++ if (sm != null) { ++ sm.checkPropertyAccess("user.dir"); ++ } ++ return normalize(userDir); + } + + private String getDrive(String path) { +diff --git a/jdk/test/java/io/File/UserDirChangedTest.java b/jdk/test/java/io/File/UserDirChangedTest.java +new file mode 100644 +index 0000000000..9eccb768e6 +--- /dev/null ++++ b/jdk/test/java/io/File/UserDirChangedTest.java +@@ -0,0 +1,51 @@ ++/* ++ * Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ */ ++ ++/* @test ++ @bug 8194154 ++ @summary Test changing property user.dir on impacting getCanonicalPath ++ @run main/othervm UserDirChangedTest ++ */ ++ ++import java.io.File; ++ ++public class UserDirChangedTest { ++ public static void main(String[] args) throws Exception { ++ String keyUserDir = "user.dir"; ++ String userDirNew = "/home/a/b/c/"; ++ String fileName = "./a"; ++ ++ String userDir = System.getProperty(keyUserDir); ++ File file = new File(fileName); ++ String canFilePath = file.getCanonicalPath(); ++ ++ // now reset user.dir, this will cause crash on linux without bug 8194154 fixed. ++ System.setProperty(keyUserDir, userDirNew); ++ String newCanFilePath = file.getCanonicalPath(); ++ System.out.format("%24s %48s%n", "Canonical Path = ", canFilePath); ++ System.out.format("%24s %48s%n", "new Canonical Path = ", newCanFilePath); ++ if (!canFilePath.equals(newCanFilePath)) { ++ throw new RuntimeException("Changing property user.dir should have no effect on getCanonicalPath"); ++ } ++ } ++} +diff --git a/jdk/test/java/io/FileOutputStream/OpenNUL.java b/jdk/test/java/io/FileOutputStream/OpenNUL.java +index 53a84504e1..dc14db070a 100644 +--- a/jdk/test/java/io/FileOutputStream/OpenNUL.java ++++ b/jdk/test/java/io/FileOutputStream/OpenNUL.java +@@ -26,9 +26,7 @@ + * @bug 8285445 + * @requires (os.family == "windows") + * @summary Verify behavior of opening "NUL:" with ADS enabled and disabled. +- * @run main/othervm OpenNUL + * @run main/othervm -Djdk.io.File.enableADS OpenNUL +- * @run main/othervm -Djdk.io.File.enableADS=FalsE OpenNUL + * @run main/othervm -Djdk.io.File.enableADS=true OpenNUL + */ + +@@ -38,7 +36,7 @@ import java.io.IOException; + + public class OpenNUL { + public static void main(String args[]) throws IOException { +- String enableADS = System.getProperty("jdk.io.File.enableADS", "true"); ++ String enableADS = System.getProperty("jdk.io.File.enableADS"); + boolean fails = enableADS.equalsIgnoreCase(Boolean.FALSE.toString()); + + FileOutputStream fos; +diff --git a/jdk/test/java/util/TimeZone/TimeZoneData/VERSION b/jdk/test/java/util/TimeZone/TimeZoneData/VERSION +index bf027918ce..c5483b4851 100644 +--- a/jdk/test/java/util/TimeZone/TimeZoneData/VERSION ++++ b/jdk/test/java/util/TimeZone/TimeZoneData/VERSION +@@ -1 +1 @@ +-tzdata2024a ++tzdata2023c +diff --git a/jdk/test/jdk/jfr/event/os/TestCPUInformation.java b/jdk/test/jdk/jfr/event/os/TestCPUInformation.java +index 17c8419cbc..f2ebf79d90 100644 +--- a/jdk/test/jdk/jfr/event/os/TestCPUInformation.java ++++ b/jdk/test/jdk/jfr/event/os/TestCPUInformation.java +@@ -54,8 +54,8 @@ public class TestCPUInformation { + Events.assertField(event, "hwThreads").atLeast(1); + Events.assertField(event, "cores").atLeast(1); + Events.assertField(event, "sockets").atLeast(1); +- Events.assertField(event, "cpu").containsAny("Intel", "AMD", "Unknown x86", "sparc", "ARM", "PPC", "PowerPC", "AArch64", "s390"); +- Events.assertField(event, "description").containsAny("Intel", "AMD", "Unknown x86", "SPARC", "ARM", "PPC", "PowerPC", "AArch64", "s390"); ++ Events.assertField(event, "cpu").containsAny("Intel", "AMD", "Unknown x86", "sparc", "ARM", "PPC", "PowerPC", "AArch64", "s390", "sw_64"); ++ Events.assertField(event, "description").containsAny("Intel", "AMD", "Unknown x86", "SPARC", "ARM", "PPC", "PowerPC", "AArch64", "s390", "shenwei"); + } + } + } +diff --git a/jdk/test/sun/security/pkcs11/rsa/TestP11KeyFactoryGetRSAKeySpec.java b/jdk/test/sun/security/pkcs11/rsa/TestP11KeyFactoryGetRSAKeySpec.java +index 2b29b3f12f..b4c467638c 100644 +--- a/jdk/test/sun/security/pkcs11/rsa/TestP11KeyFactoryGetRSAKeySpec.java ++++ b/jdk/test/sun/security/pkcs11/rsa/TestP11KeyFactoryGetRSAKeySpec.java +@@ -1,5 +1,4 @@ + /* +- * Copyright (c) 2021, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2021, Amazon.com, Inc. or its affiliates. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * +@@ -22,6 +21,7 @@ + * questions. + */ + ++import java.math.BigInteger; + import java.security.KeyFactory; + import java.security.KeyPair; + import java.security.KeyPairGenerator; +@@ -85,7 +85,7 @@ public class TestP11KeyFactoryGetRSAKeySpec extends PKCS11Test { + + private static void testKeySpec(KeyFactory factory, PrivateKey key, Class specClass) throws Exception { + try { +- KeySpec spec = factory.getKeySpec(key, specClass); ++ KeySpec spec = factory.getKeySpec(key, RSAPrivateKeySpec.class); + if (testingSensitiveKeys) { + throw new Exception("Able to retrieve spec from sensitive key"); + } +diff --git a/jdk/test/sun/util/calendar/zi/tzdata/VERSION b/jdk/test/sun/util/calendar/zi/tzdata/VERSION +index b138ed7fa7..66bd061e8b 100644 +--- a/jdk/test/sun/util/calendar/zi/tzdata/VERSION ++++ b/jdk/test/sun/util/calendar/zi/tzdata/VERSION +@@ -21,4 +21,4 @@ + # or visit www.oracle.com if you need additional information or have any + # questions. + # +-tzdata2024a ++tzdata2023c +diff --git a/jdk/test/sun/util/calendar/zi/tzdata/asia b/jdk/test/sun/util/calendar/zi/tzdata/asia +index c51170c34a..48a348bf95 100644 +--- a/jdk/test/sun/util/calendar/zi/tzdata/asia ++++ b/jdk/test/sun/util/calendar/zi/tzdata/asia +@@ -678,6 +678,7 @@ Zone Asia/Shanghai 8:05:43 - LMT 1901 + 8:00 PRC C%sT + # Xinjiang time, used by many in western China; represented by Ürümqi / Ürümchi + # / Wulumuqi. (Please use Asia/Shanghai if you prefer Beijing time.) ++# Vostok base in Antarctica matches this since 1970. + Zone Asia/Urumqi 5:50:20 - LMT 1928 + 6:00 - +06 + +@@ -2480,33 +2481,18 @@ Zone Asia/Amman 2:23:44 - LMT 1931 + # effective December 21st, 2018.... + # http://adilet.zan.kz/rus/docs/P1800000817 (russian language). + +-# From Zhanbolat Raimbekov (2024-01-19): +-# Kazakhstan (all parts) switching to UTC+5 on March 1, 2024 +-# https://www.gov.kz/memleket/entities/mti/press/news/details/688998?lang=ru +-# [in Russian] +-# (2024-01-20): https://primeminister.kz/ru/decisions/19012024-20 +-# +-# From Alexander Krivenyshev (2024-01-19): +-# According to a different news and the official web site for the Ministry of +-# Trade and Integration of the Republic of Kazakhstan: +-# https://en.inform.kz/news/kazakhstan-to-switch-to-single-hour-zone-mar-1-54ad0b/ +- + # Zone NAME STDOFF RULES FORMAT [UNTIL] + # + # Almaty (formerly Alma-Ata), representing most locations in Kazakhstan +-# This includes Abai/Abay (ISO 3166-2 code KZ-10), Aqmola/Akmola (KZ-11), +-# Almaty (KZ-19), Almaty city (KZ-75), Astana city (KZ-71), +-# East Kazkhstan (KZ-63), Jambyl/Zhambyl (KZ-31), Jetisu/Zhetysu (KZ-33), +-# Karaganda (KZ-35), North Kazakhstan (KZ-59), Pavlodar (KZ-55), +-# Shyumkent city (KZ-79), Turkistan (KZ-61), and Ulytau (KZ-62). ++# This includes KZ-AKM, KZ-ALA, KZ-ALM, KZ-AST, KZ-BAY, KZ-VOS, KZ-ZHA, ++# KZ-KAR, KZ-SEV, KZ-PAV, and KZ-YUZ. + Zone Asia/Almaty 5:07:48 - LMT 1924 May 2 # or Alma-Ata + 5:00 - +05 1930 Jun 21 + 6:00 RussiaAsia +06/+07 1991 Mar 31 2:00s + 5:00 RussiaAsia +05/+06 1992 Jan 19 2:00s + 6:00 RussiaAsia +06/+07 2004 Oct 31 2:00s +- 6:00 - +06 2024 Mar 1 0:00 +- 5:00 - +05 +-# Qyzylorda (aka Kyzylorda, Kizilorda, Kzyl-Orda, etc.) (KZ-43) ++ 6:00 - +06 ++# Qyzylorda (aka Kyzylorda, Kizilorda, Kzyl-Orda, etc.) (KZ-KZY) + Zone Asia/Qyzylorda 4:21:52 - LMT 1924 May 2 + 4:00 - +04 1930 Jun 21 + 5:00 - +05 1981 Apr 1 +@@ -2519,7 +2505,8 @@ Zone Asia/Qyzylorda 4:21:52 - LMT 1924 May 2 + 5:00 RussiaAsia +05/+06 2004 Oct 31 2:00s + 6:00 - +06 2018 Dec 21 0:00 + 5:00 - +05 +-# Qostanay (aka Kostanay, Kustanay) (KZ-39) ++# ++# Qostanay (aka Kostanay, Kustanay) (KZ-KUS) + # The 1991/2 rules are unclear partly because of the 1997 Turgai + # reorganization. + Zone Asia/Qostanay 4:14:28 - LMT 1924 May 2 +@@ -2530,9 +2517,9 @@ Zone Asia/Qostanay 4:14:28 - LMT 1924 May 2 + 5:00 RussiaAsia +05/+06 1991 Mar 31 2:00s + 4:00 RussiaAsia +04/+05 1992 Jan 19 2:00s + 5:00 RussiaAsia +05/+06 2004 Oct 31 2:00s +- 6:00 - +06 2024 Mar 1 0:00 +- 5:00 - +05 +-# Aqtöbe (aka Aktobe, formerly Aktyubinsk) (KZ-15) ++ 6:00 - +06 ++ ++# Aqtöbe (aka Aktobe, formerly Aktyubinsk) (KZ-AKT) + Zone Asia/Aqtobe 3:48:40 - LMT 1924 May 2 + 4:00 - +04 1930 Jun 21 + 5:00 - +05 1981 Apr 1 +@@ -2542,7 +2529,7 @@ Zone Asia/Aqtobe 3:48:40 - LMT 1924 May 2 + 4:00 RussiaAsia +04/+05 1992 Jan 19 2:00s + 5:00 RussiaAsia +05/+06 2004 Oct 31 2:00s + 5:00 - +05 +-# Mangghystaū (KZ-47) ++# Mangghystaū (KZ-MAN) + # Aqtau was not founded until 1963, but it represents an inhabited region, + # so include timestamps before 1963. + Zone Asia/Aqtau 3:21:04 - LMT 1924 May 2 +@@ -2554,7 +2541,7 @@ Zone Asia/Aqtau 3:21:04 - LMT 1924 May 2 + 5:00 RussiaAsia +05/+06 1994 Sep 25 2:00s + 4:00 RussiaAsia +04/+05 2004 Oct 31 2:00s + 5:00 - +05 +-# Atyraū (KZ-23) is like Mangghystaū except it switched from ++# Atyraū (KZ-ATY) is like Mangghystaū except it switched from + # +04/+05 to +05/+06 in spring 1999, not fall 1994. + Zone Asia/Atyrau 3:27:44 - LMT 1924 May 2 + 3:00 - +03 1930 Jun 21 +@@ -2565,7 +2552,7 @@ Zone Asia/Atyrau 3:27:44 - LMT 1924 May 2 + 5:00 RussiaAsia +05/+06 1999 Mar 28 2:00s + 4:00 RussiaAsia +04/+05 2004 Oct 31 2:00s + 5:00 - +05 +-# West Kazakhstan (KZ-27) ++# West Kazakhstan (KZ-ZAP) + # From Paul Eggert (2016-03-18): + # The 1989 transition is from USSR act No. 227 (1989-03-14). + Zone Asia/Oral 3:25:24 - LMT 1924 May 2 # or Ural'sk +@@ -3463,30 +3450,20 @@ Zone Asia/Karachi 4:28:12 - LMT 1907 + # From Heba Hamad (2023-03-22): + # ... summer time will begin in Palestine from Saturday 04-29-2023, + # 02:00 AM by 60 minutes forward. +-# From Heba Hemad (2023-10-09): +-# ... winter time will begin in Palestine from Saturday 10-28-2023, +-# 02:00 AM by 60 minutes back. +-# +-# From Heba Hamad (2024-01-25): +-# the summer time for the years 2024,2025 will begin in Palestine +-# from Saturday at 02:00 AM by 60 minutes forward as shown below: +-# year date +-# 2024 2024-04-20 +-# 2025 2025-04-12 +-# +-# From Paul Eggert (2024-01-25): ++# ++# From Paul Eggert (2023-03-22): + # For now, guess that spring and fall transitions will normally + # continue to use 2022's rules, that during DST Palestine will switch + # to standard time at 02:00 the last Saturday before Ramadan and back +-# to DST at 02:00 the second Saturday after Ramadan, and that ++# to DST at 02:00 the first Saturday after Ramadan, and that + # if the normal spring-forward or fall-back transition occurs during + # Ramadan the former is delayed and the latter advanced. + # To implement this, I predicted Ramadan-oriented transition dates for +-# 2026 through 2086 by running the following program under GNU Emacs 29.2, ++# 2023 through 2086 by running the following program under GNU Emacs 28.2, + # with the results integrated by hand into the table below. + # Predictions after 2086 are approximated without Ramadan. + # +-# (let ((islamic-year 1447)) ++# (let ((islamic-year 1444)) + # (require 'cal-islam) + # (while (< islamic-year 1510) + # (let ((a (calendar-islamic-to-absolute (list 9 1 islamic-year))) +@@ -3495,7 +3472,6 @@ Zone Asia/Karachi 4:28:12 - LMT 1907 + # (while (/= saturday (mod (setq a (1- a)) 7))) + # (while (/= saturday (mod b 7)) + # (setq b (1+ b))) +-# (setq b (+ 7 b)) + # (setq a (calendar-gregorian-from-absolute a)) + # (setq b (calendar-gregorian-from-absolute b)) + # (insert +@@ -3546,84 +3522,84 @@ Rule Palestine 2021 only - Oct 29 1:00 0 - + Rule Palestine 2022 only - Mar 27 0:00 1:00 S + Rule Palestine 2022 2035 - Oct Sat<=30 2:00 0 - + Rule Palestine 2023 only - Apr 29 2:00 1:00 S +-Rule Palestine 2024 only - Apr 20 2:00 1:00 S +-Rule Palestine 2025 only - Apr 12 2:00 1:00 S ++Rule Palestine 2024 only - Apr 13 2:00 1:00 S ++Rule Palestine 2025 only - Apr 5 2:00 1:00 S + Rule Palestine 2026 2054 - Mar Sat<=30 2:00 1:00 S + Rule Palestine 2036 only - Oct 18 2:00 0 - + Rule Palestine 2037 only - Oct 10 2:00 0 - + Rule Palestine 2038 only - Sep 25 2:00 0 - + Rule Palestine 2039 only - Sep 17 2:00 0 - ++Rule Palestine 2039 only - Oct 22 2:00 1:00 S ++Rule Palestine 2039 2067 - Oct Sat<=30 2:00 0 - + Rule Palestine 2040 only - Sep 1 2:00 0 - +-Rule Palestine 2040 only - Oct 20 2:00 1:00 S +-Rule Palestine 2040 2067 - Oct Sat<=30 2:00 0 - ++Rule Palestine 2040 only - Oct 13 2:00 1:00 S + Rule Palestine 2041 only - Aug 24 2:00 0 - +-Rule Palestine 2041 only - Oct 5 2:00 1:00 S ++Rule Palestine 2041 only - Sep 28 2:00 1:00 S + Rule Palestine 2042 only - Aug 16 2:00 0 - +-Rule Palestine 2042 only - Sep 27 2:00 1:00 S ++Rule Palestine 2042 only - Sep 20 2:00 1:00 S + Rule Palestine 2043 only - Aug 1 2:00 0 - +-Rule Palestine 2043 only - Sep 19 2:00 1:00 S ++Rule Palestine 2043 only - Sep 12 2:00 1:00 S + Rule Palestine 2044 only - Jul 23 2:00 0 - +-Rule Palestine 2044 only - Sep 3 2:00 1:00 S ++Rule Palestine 2044 only - Aug 27 2:00 1:00 S + Rule Palestine 2045 only - Jul 15 2:00 0 - +-Rule Palestine 2045 only - Aug 26 2:00 1:00 S ++Rule Palestine 2045 only - Aug 19 2:00 1:00 S + Rule Palestine 2046 only - Jun 30 2:00 0 - +-Rule Palestine 2046 only - Aug 18 2:00 1:00 S ++Rule Palestine 2046 only - Aug 11 2:00 1:00 S + Rule Palestine 2047 only - Jun 22 2:00 0 - +-Rule Palestine 2047 only - Aug 3 2:00 1:00 S ++Rule Palestine 2047 only - Jul 27 2:00 1:00 S + Rule Palestine 2048 only - Jun 6 2:00 0 - +-Rule Palestine 2048 only - Jul 25 2:00 1:00 S ++Rule Palestine 2048 only - Jul 18 2:00 1:00 S + Rule Palestine 2049 only - May 29 2:00 0 - +-Rule Palestine 2049 only - Jul 10 2:00 1:00 S ++Rule Palestine 2049 only - Jul 3 2:00 1:00 S + Rule Palestine 2050 only - May 21 2:00 0 - +-Rule Palestine 2050 only - Jul 2 2:00 1:00 S ++Rule Palestine 2050 only - Jun 25 2:00 1:00 S + Rule Palestine 2051 only - May 6 2:00 0 - +-Rule Palestine 2051 only - Jun 24 2:00 1:00 S ++Rule Palestine 2051 only - Jun 17 2:00 1:00 S + Rule Palestine 2052 only - Apr 27 2:00 0 - +-Rule Palestine 2052 only - Jun 8 2:00 1:00 S ++Rule Palestine 2052 only - Jun 1 2:00 1:00 S + Rule Palestine 2053 only - Apr 12 2:00 0 - +-Rule Palestine 2053 only - May 31 2:00 1:00 S ++Rule Palestine 2053 only - May 24 2:00 1:00 S + Rule Palestine 2054 only - Apr 4 2:00 0 - +-Rule Palestine 2054 only - May 23 2:00 1:00 S +-Rule Palestine 2055 only - May 8 2:00 1:00 S +-Rule Palestine 2056 only - Apr 29 2:00 1:00 S +-Rule Palestine 2057 only - Apr 14 2:00 1:00 S +-Rule Palestine 2058 only - Apr 6 2:00 1:00 S +-Rule Palestine 2059 max - Mar Sat<=30 2:00 1:00 S ++Rule Palestine 2054 only - May 16 2:00 1:00 S ++Rule Palestine 2055 only - May 1 2:00 1:00 S ++Rule Palestine 2056 only - Apr 22 2:00 1:00 S ++Rule Palestine 2057 only - Apr 7 2:00 1:00 S ++Rule Palestine 2058 max - Mar Sat<=30 2:00 1:00 S + Rule Palestine 2068 only - Oct 20 2:00 0 - + Rule Palestine 2069 only - Oct 12 2:00 0 - + Rule Palestine 2070 only - Oct 4 2:00 0 - + Rule Palestine 2071 only - Sep 19 2:00 0 - + Rule Palestine 2072 only - Sep 10 2:00 0 - +-Rule Palestine 2072 only - Oct 22 2:00 1:00 S +-Rule Palestine 2072 max - Oct Sat<=30 2:00 0 - ++Rule Palestine 2072 only - Oct 15 2:00 1:00 S + Rule Palestine 2073 only - Sep 2 2:00 0 - +-Rule Palestine 2073 only - Oct 14 2:00 1:00 S ++Rule Palestine 2073 only - Oct 7 2:00 1:00 S + Rule Palestine 2074 only - Aug 18 2:00 0 - +-Rule Palestine 2074 only - Oct 6 2:00 1:00 S ++Rule Palestine 2074 only - Sep 29 2:00 1:00 S + Rule Palestine 2075 only - Aug 10 2:00 0 - +-Rule Palestine 2075 only - Sep 21 2:00 1:00 S ++Rule Palestine 2075 only - Sep 14 2:00 1:00 S ++Rule Palestine 2075 max - Oct Sat<=30 2:00 0 - + Rule Palestine 2076 only - Jul 25 2:00 0 - +-Rule Palestine 2076 only - Sep 12 2:00 1:00 S ++Rule Palestine 2076 only - Sep 5 2:00 1:00 S + Rule Palestine 2077 only - Jul 17 2:00 0 - +-Rule Palestine 2077 only - Sep 4 2:00 1:00 S ++Rule Palestine 2077 only - Aug 28 2:00 1:00 S + Rule Palestine 2078 only - Jul 9 2:00 0 - +-Rule Palestine 2078 only - Aug 20 2:00 1:00 S ++Rule Palestine 2078 only - Aug 13 2:00 1:00 S + Rule Palestine 2079 only - Jun 24 2:00 0 - +-Rule Palestine 2079 only - Aug 12 2:00 1:00 S ++Rule Palestine 2079 only - Aug 5 2:00 1:00 S + Rule Palestine 2080 only - Jun 15 2:00 0 - +-Rule Palestine 2080 only - Jul 27 2:00 1:00 S ++Rule Palestine 2080 only - Jul 20 2:00 1:00 S + Rule Palestine 2081 only - Jun 7 2:00 0 - +-Rule Palestine 2081 only - Jul 19 2:00 1:00 S ++Rule Palestine 2081 only - Jul 12 2:00 1:00 S + Rule Palestine 2082 only - May 23 2:00 0 - +-Rule Palestine 2082 only - Jul 11 2:00 1:00 S ++Rule Palestine 2082 only - Jul 4 2:00 1:00 S + Rule Palestine 2083 only - May 15 2:00 0 - +-Rule Palestine 2083 only - Jun 26 2:00 1:00 S ++Rule Palestine 2083 only - Jun 19 2:00 1:00 S + Rule Palestine 2084 only - Apr 29 2:00 0 - +-Rule Palestine 2084 only - Jun 17 2:00 1:00 S ++Rule Palestine 2084 only - Jun 10 2:00 1:00 S + Rule Palestine 2085 only - Apr 21 2:00 0 - +-Rule Palestine 2085 only - Jun 9 2:00 1:00 S ++Rule Palestine 2085 only - Jun 2 2:00 1:00 S + Rule Palestine 2086 only - Apr 13 2:00 0 - +-Rule Palestine 2086 only - May 25 2:00 1:00 S ++Rule Palestine 2086 only - May 18 2:00 1:00 S + + # Zone NAME STDOFF RULES FORMAT [UNTIL] + Zone Asia/Gaza 2:17:52 - LMT 1900 Oct +@@ -3651,7 +3627,7 @@ Zone Asia/Hebron 2:20:23 - LMT 1900 Oct + + # Philippines + +-# From Paul Eggert (2024-01-21): ++# From Paul Eggert (2018-11-18): + # The Spanish initially used American (west-of-Greenwich) time. + # It is unknown what time Manila kept when the British occupied it from + # 1762-10-06 through 1764-04; for now assume it kept American time. +@@ -3659,7 +3635,7 @@ Zone Asia/Hebron 2:20:23 - LMT 1900 Oct + # Philippines, issued a proclamation announcing that 1844-12-30 was to + # be immediately followed by 1845-01-01; see R.H. van Gent's + # History of the International Date Line +-# https://webspace.science.uu.nl/~gent0113/idl/idl_philippines.htm ++# https://www.staff.science.uu.nl/~gent0113/idl/idl_philippines.htm + # The rest of the data entries are from Shanks & Pottenger. + + # From Jesper Nørgaard Welen (2006-04-26): +@@ -4086,8 +4062,7 @@ Zone Asia/Tashkent 4:37:11 - LMT 1924 May 2 + # The English-language name of Vietnam's most populous city is "Ho Chi Minh + # City"; use Ho_Chi_Minh below to avoid a name of more than 14 characters. + +-# From Paul Eggert (2024-01-14) after a 2014 heads-up from Trần Ngọc Quân +-# and a 2024-01-14 heads-up from Đoàn Trần Công Danh: ++# From Paul Eggert (2022-07-27) after a 2014 heads-up from Trần Ngọc Quân: + # Trần Tiến Bình's authoritative book "Lịch Việt Nam: thế kỷ XX-XXI (1901-2100)" + # (Nhà xuất bản Văn Hoá - Thông Tin, Hanoi, 2005), pp 49-50, + # is quoted verbatim in: +@@ -4117,35 +4092,14 @@ Zone Asia/Tashkent 4:37:11 - LMT 1924 May 2 + # + # Trần cites the following sources; it's unclear which supplied the info above. + # +-# Hoàng Xuân Hãn: "Lịch và lịch Việt Nam". Tập san Khoa học Xã hội, +-# No. 9, Paris, February 1982. +-# +-# Lê Thành Lân: "Lịch và niên biểu lịch sử hai mươi thế kỷ (0001-2010)", +-# NXB Thống kê, Hanoi, 2000. ++# Hoàng Xuân Hãn: "Lịch và lịch Việt Nam". Tập san Khoa học Xã hội, ++# No. 9, Paris, February 1982. + # +-# Lê Thành Lân: "Lịch hai thế kỷ (1802-2010) và các lịch vĩnh cửu", +-# NXB Thuận Hoá, Huế, 1995. ++# Lê Thành Lân: "Lịch và niên biểu lịch sử hai mươi thế kỷ (0001-2010)", ++# NXB Thống kê, Hanoi, 2000. + # +-# Here is the decision for the September 1945 transition: +-# Võ Nguyên Giáp, Việt Nam Dân Quốc Công Báo, No. 1 (1945-09-29), page 13 +-# http://baochi.nlv.gov.vn/baochi/cgi-bin/baochi?a=d&d=JwvzO19450929.2.5&dliv=none +-# It says that on 1945-09-01 at 24:00, Vietnam moved back two hours, to +07. +-# It also mentions a 1945-03-29 decree (by a Japanese Goveror-General) +-# to set the time zone to +09, but does not say whether that decree +-# merely legalized an earlier change to +09. +-# +-# July 1955 transition: +-# Ngô Đình Diệm, Công Báo Việt Nam, No. 92 (1955-07-02), page 1780-1781 +-# Ordinance (Dụ) No. 46 (1955-06-25) +-# http://ddsnext.crl.edu/titles/32341#?c=0&m=29&s=0&cv=4&r=0&xywh=-89%2C342%2C1724%2C1216 +-# It says that on 1955-07-01 at 01:00, South Vietnam moved back 1 hour (to +07). +-# +-# December 1959 transition: +-# Ngô Đình Diệm, Công Báo Việt Nam Cộng Hòa, 1960 part 1 (1960-01-02), page 62 +-# Decree (Sắc lệnh) No. 362-TTP (1959-12-30) +-# http://ddsnext.crl.edu/titles/32341#?c=0&m=138&s=0&cv=793&r=0&xywh=-54%2C1504%2C1705%2C1202 +-# It says that on 1959-12-31 at 23:00, South Vietnam moved forward 1 hour (to +08). +- ++# Lê Thành Lân: "Lịch hai thế kỷ (1802-2010) và các lịch vĩnh cửu", ++# NXB Thuận Hoá, Huế, 1995. + + # Zone NAME STDOFF RULES FORMAT [UNTIL] + #STDOFF 7:06:30.13 +@@ -4153,9 +4107,9 @@ Zone Asia/Ho_Chi_Minh 7:06:30 - LMT 1906 Jul 1 + 7:06:30 - PLMT 1911 May 1 # Phù Liễn MT + 7:00 - +07 1942 Dec 31 23:00 + 8:00 - +08 1945 Mar 14 23:00 +- 9:00 - +09 1945 Sep 1 24:00 ++ 9:00 - +09 1945 Sep 2 + 7:00 - +07 1947 Apr 1 +- 8:00 - +08 1955 Jul 1 01:00 ++ 8:00 - +08 1955 Jul 1 + 7:00 - +07 1959 Dec 31 23:00 + 8:00 - +08 1975 Jun 13 + 7:00 - +07 +diff --git a/jdk/test/sun/util/calendar/zi/tzdata/europe b/jdk/test/sun/util/calendar/zi/tzdata/europe +index 853df30ef8..5a0e516fdd 100644 +--- a/jdk/test/sun/util/calendar/zi/tzdata/europe ++++ b/jdk/test/sun/util/calendar/zi/tzdata/europe +@@ -1013,34 +1013,9 @@ Zone Europe/Sofia 1:33:16 - LMT 1880 + # Czech Republic (Czechia) + # Slovakia + # +-# From Ivan Benovic (2024-01-30): +-# https://www.slov-lex.sk/pravne-predpisy/SK/ZZ/1946/54/ +-# (This is an official link to the Czechoslovak Summer Time Act of +-# March 8, 1946 that authorizes the Czechoslovak government to set the +-# exact dates of change to summer time and back to Central European Time. +-# The act also implicitly confirms Central European Time as the +-# official time zone of Czechoslovakia and currently remains in force +-# in both the Czech Republic and Slovakia.) +-# https://www.psp.cz/eknih/1945pns/tisky/t0216_00.htm +-# (This is a link to the original legislative proposal dating back to +-# February 22, 1946. The accompanying memorandum to the proposal says +-# that an advisory committee on European railroad transportation that +-# met in Brussels in October 1945 decided that the change of time +-# should be carried out in all participating countries in a strictly +-# coordinated manner....) +-# +-# From Paul Eggert (2024-01-30): +-# The source for Czech data is: Kdy začíná a končí letní čas. ++# From Paul Eggert (2018-04-15): ++# The source for Czech data is: Kdy začíná a končí letní čas. 2018-04-15. + # https://kalendar.beda.cz/kdy-zacina-a-konci-letni-cas +-# Its main text disagrees with its quoted sources only in 1918, +-# where the main text says spring and autumn transitions +-# occurred at 02:00 and 03:00 respectively (as usual), +-# whereas the 1918 source "Oznámení o zavedení letního času v roce 1918" +-# says transitions were at 01:00 and 02:00 respectively. +-# As the 1918 source appears to be a humorous piece, and it is +-# unlikely that Prague would have disagreed with its neighbors by an hour, +-# go with the main text for now. +-# + # We know of no English-language name for historical Czech winter time; + # abbreviate it as "GMT", as it happened to be GMT. + # +@@ -1171,23 +1146,6 @@ Zone Atlantic/Faroe -0:27:04 - LMT 1908 Jan 11 # Tórshavn + # 2. The shift *from* DST in 2023 happens as normal, but coincides with the + # shift to UTC-02 normaltime (people will not change their clocks here). + # 3. After this, DST is still observed, but as -02/-01 instead of -03/-02. +-# +-# From Múte Bourup Egede via Jógvan Svabo Samuelsen (2023-03-15): +-# Greenland will not switch to Daylight Saving Time this year, 2023, +-# because the standard time for Greenland will change from UTC -3 to UTC -2. +-# However, Greenland will change to Daylight Saving Time again in 2024 +-# and onwards. +- +-# From a contributor who wishes to remain anonymous for now (2023-10-29): +-# https://www.dr.dk/nyheder/seneste/i-nat-skal-uret-stilles-en-time-tilbage-men-foerste-gang-sker-det-ikke-i-groenland +-# with a link to that page: +-# https://naalakkersuisut.gl/Nyheder/2023/10/2710_sommertid +-# ... Ittoqqortoormiit joins the time of Nuuk at March 2024. +-# What would mean that America/Scoresbysund would either be in -01 year round +-# or in -02/-01 like America/Nuuk, but no longer in -01/+00. +-# +-# From Paul Eggert (2023-10-29): +-# For now, assume it will be like America/Nuuk. + + # Rule NAME FROM TO - IN ON AT SAVE LETTER/S + Rule Thule 1991 1992 - Mar lastSun 2:00 1:00 D +@@ -1208,12 +1166,10 @@ Zone America/Danmarkshavn -1:14:40 - LMT 1916 Jul 28 + Zone America/Scoresbysund -1:27:52 - LMT 1916 Jul 28 # Ittoqqortoormiit + -2:00 - -02 1980 Apr 6 2:00 + -2:00 C-Eur -02/-01 1981 Mar 29 +- -1:00 EU -01/+00 2024 Mar 31 +- -2:00 EU -02/-01 ++ -1:00 EU -01/+00 + Zone America/Nuuk -3:26:56 - LMT 1916 Jul 28 # Godthåb + -3:00 - -03 1980 Apr 6 2:00 +- -3:00 EU -03/-02 2023 Mar 26 1:00u +- -2:00 - -02 2023 Oct 29 1:00u ++ -3:00 EU -03/-02 2023 Oct 29 1:00u + -2:00 EU -02/-01 + Zone America/Thule -4:35:08 - LMT 1916 Jul 28 # Pituffik + -4:00 Thule A%sT +@@ -3778,7 +3734,11 @@ Zone Europe/Istanbul 1:55:52 - LMT 1880 + # and not at 3:00 as would have been under EU rules. + # This is why I have set the change to EU rules into May 1996, + # so that the change in March is stil covered by the Ukraine rule. +-# The next change in October 1996 happened under EU rules. ++# The next change in October 1996 happened under EU rules.... ++# TZ database holds three other zones for Ukraine.... I have not yet ++# worked out the consequences for these three zones, as we (me and my ++# US colleague David Cochrane) are still trying to get more ++# information upon these local deviations from Kiev rules. + # + # From Paul Eggert (2022-08-27): + # For now, assume that Ukraine's zones all followed the same rules, +diff --git a/jdk/test/sun/util/calendar/zi/tzdata/leapseconds b/jdk/test/sun/util/calendar/zi/tzdata/leapseconds +index 8e7df3de98..89ce8b89cd 100644 +--- a/jdk/test/sun/util/calendar/zi/tzdata/leapseconds ++++ b/jdk/test/sun/util/calendar/zi/tzdata/leapseconds +@@ -26,10 +26,13 @@ + # This file is in the public domain. + + # This file is generated automatically from the data in the public-domain +-# NIST/IERS format leap-seconds.list file, which can be copied from ++# NIST format leap-seconds.list file, which can be copied from ++# ++# or . ++# The NIST file is used instead of its IERS upstream counterpart + # +-# or, in a variant with different comments, from +-# . ++# because under US law the NIST file is public domain ++# whereas the IERS file's copyright and license status is unclear. + # For more about leap-seconds.list, please see + # The NTP Timescale and Leap Seconds + # . +@@ -92,11 +95,11 @@ Leap 2016 Dec 31 23:59:60 + S + # Any additional leap seconds will come after this. + # This Expires line is commented out for now, + # so that pre-2020a zic implementations do not reject this file. +-#Expires 2024 Dec 28 00:00:00 ++#Expires 2023 Dec 28 00:00:00 + + # POSIX timestamps for the data in this file: +-#updated 1704708379 (2024-01-08 10:06:19 UTC) +-#expires 1735344000 (2024-12-28 00:00:00 UTC) ++#updated 1467936000 (2016-07-08 00:00:00 UTC) ++#expires 1703721600 (2023-12-28 00:00:00 UTC) + +-# Updated through IERS Bulletin C (https://hpiers.obspm.fr/iers/bul/bulc/bulletinc.dat) +-# File expires on 28 December 2024 ++# Updated through IERS Bulletin C65 ++# File expires on: 28 December 2023 +diff --git a/jdk/test/sun/util/calendar/zi/tzdata/zone.tab b/jdk/test/sun/util/calendar/zi/tzdata/zone.tab +index 0a01e8777d..3edb0d61c8 100644 +--- a/jdk/test/sun/util/calendar/zi/tzdata/zone.tab ++++ b/jdk/test/sun/util/calendar/zi/tzdata/zone.tab +@@ -71,7 +71,7 @@ AR -3124-06411 America/Argentina/Cordoba Argentina (most areas: CB, CC, CN, ER, + AR -2447-06525 America/Argentina/Salta Salta (SA, LP, NQ, RN) + AR -2411-06518 America/Argentina/Jujuy Jujuy (JY) + AR -2649-06513 America/Argentina/Tucuman Tucuman (TM) +-AR -2828-06547 America/Argentina/Catamarca Catamarca (CT), Chubut (CH) ++AR -2828-06547 America/Argentina/Catamarca Catamarca (CT); Chubut (CH) + AR -2926-06651 America/Argentina/La_Rioja La Rioja (LR) + AR -3132-06831 America/Argentina/San_Juan San Juan (SJ) + AR -3253-06849 America/Argentina/Mendoza Mendoza (MZ) +@@ -110,7 +110,7 @@ BN +0456+11455 Asia/Brunei + BO -1630-06809 America/La_Paz + BQ +120903-0681636 America/Kralendijk + BR -0351-03225 America/Noronha Atlantic islands +-BR -0127-04829 America/Belem Para (east), Amapa ++BR -0127-04829 America/Belem Para (east); Amapa + BR -0343-03830 America/Fortaleza Brazil (northeast: MA, PI, CE, RN, PB) + BR -0803-03454 America/Recife Pernambuco + BR -0712-04812 America/Araguaina Tocantins +@@ -130,21 +130,21 @@ BT +2728+08939 Asia/Thimphu + BW -2439+02555 Africa/Gaborone + BY +5354+02734 Europe/Minsk + BZ +1730-08812 America/Belize +-CA +4734-05243 America/St_Johns Newfoundland, Labrador (SE) +-CA +4439-06336 America/Halifax Atlantic - NS (most areas), PE ++CA +4734-05243 America/St_Johns Newfoundland; Labrador (southeast) ++CA +4439-06336 America/Halifax Atlantic - NS (most areas); PE + CA +4612-05957 America/Glace_Bay Atlantic - NS (Cape Breton) + CA +4606-06447 America/Moncton Atlantic - New Brunswick + CA +5320-06025 America/Goose_Bay Atlantic - Labrador (most areas) + CA +5125-05707 America/Blanc-Sablon AST - QC (Lower North Shore) +-CA +4339-07923 America/Toronto Eastern - ON & QC (most areas) ++CA +4339-07923 America/Toronto Eastern - ON, QC (most areas) + CA +6344-06828 America/Iqaluit Eastern - NU (most areas) +-CA +484531-0913718 America/Atikokan EST - ON (Atikokan), NU (Coral H) +-CA +4953-09709 America/Winnipeg Central - ON (west), Manitoba ++CA +484531-0913718 America/Atikokan EST - ON (Atikokan); NU (Coral H) ++CA +4953-09709 America/Winnipeg Central - ON (west); Manitoba + CA +744144-0944945 America/Resolute Central - NU (Resolute) + CA +624900-0920459 America/Rankin_Inlet Central - NU (central) + CA +5024-10439 America/Regina CST - SK (most areas) + CA +5017-10750 America/Swift_Current CST - SK (midwest) +-CA +5333-11328 America/Edmonton Mountain - AB, BC(E), NT(E), SK(W) ++CA +5333-11328 America/Edmonton Mountain - AB; BC (E); NT (E); SK (W) + CA +690650-1050310 America/Cambridge_Bay Mountain - NU (west) + CA +682059-1334300 America/Inuvik Mountain - NT (west) + CA +4906-11631 America/Creston MST - BC (Creston) +@@ -230,8 +230,8 @@ HT +1832-07220 America/Port-au-Prince + HU +4730+01905 Europe/Budapest + ID -0610+10648 Asia/Jakarta Java, Sumatra + ID -0002+10920 Asia/Pontianak Borneo (west, central) +-ID -0507+11924 Asia/Makassar Borneo (east, south), Sulawesi/Celebes, Bali, Nusa Tengarra, Timor (west) +-ID -0232+14042 Asia/Jayapura New Guinea (West Papua / Irian Jaya), Malukus/Moluccas ++ID -0507+11924 Asia/Makassar Borneo (east, south); Sulawesi/Celebes, Bali, Nusa Tengarra; Timor (west) ++ID -0232+14042 Asia/Jayapura New Guinea (West Papua / Irian Jaya); Malukus/Moluccas + IE +5320-00615 Europe/Dublin + IL +314650+0351326 Asia/Jerusalem + IM +5409-00428 Europe/Isle_of_Man +@@ -378,7 +378,7 @@ RU +4310+13156 Asia/Vladivostok MSK+07 - Amur River + RU +643337+1431336 Asia/Ust-Nera MSK+07 - Oymyakonsky + RU +5934+15048 Asia/Magadan MSK+08 - Magadan + RU +4658+14242 Asia/Sakhalin MSK+08 - Sakhalin Island +-RU +6728+15343 Asia/Srednekolymsk MSK+08 - Sakha (E), N Kuril Is ++RU +6728+15343 Asia/Srednekolymsk MSK+08 - Sakha (E); N Kuril Is + RU +5301+15839 Asia/Kamchatka MSK+09 - Kamchatka + RU +6445+17729 Asia/Anadyr MSK+09 - Bering Sea + RW -0157+03004 Africa/Kigali +@@ -441,7 +441,7 @@ US +470659-1011757 America/North_Dakota/Center Central - ND (Oliver) + US +465042-1012439 America/North_Dakota/New_Salem Central - ND (Morton rural) + US +471551-1014640 America/North_Dakota/Beulah Central - ND (Mercer) + US +394421-1045903 America/Denver Mountain (most areas) +-US +433649-1161209 America/Boise Mountain - ID (south), OR (east) ++US +433649-1161209 America/Boise Mountain - ID (south); OR (east) + US +332654-1120424 America/Phoenix MST - AZ (except Navajo) + US +340308-1181434 America/Los_Angeles Pacific + US +611305-1495401 America/Anchorage Alaska (most areas) +diff --git a/langtools/THIRD_PARTY_README b/langtools/THIRD_PARTY_README +new file mode 100644 +index 0000000000..f26a5f3ec5 +--- /dev/null ++++ b/langtools/THIRD_PARTY_README +@@ -0,0 +1,3371 @@ ++DO NOT TRANSLATE OR LOCALIZE. ++----------------------------- ++ ++%% This notice is provided with respect to ASM Bytecode Manipulation ++Framework v5.0.3, which may be included with JRE 8, and JDK 8, and ++OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++Copyright (c) 2000-2011 France T??l??com ++All rights reserved. ++ ++Redistribution and use in source and binary forms, with or without ++modification, are permitted provided that the following conditions ++are met: ++ ++1. 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IN NO EVENT SHALL BITSTREAM OR THE GNOME ++FOUNDATION BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, INCLUDING ++ANY GENERAL, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, ++WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF ++THE USE OR INABILITY TO USE THE FONT SOFTWARE OR FROM OTHER DEALINGS IN THE ++FONT SOFTWARE. ++ ++Except as contained in this notice, the names of Gnome, the Gnome ++Foundation, and Bitstream Inc., shall not be used in advertising or ++otherwise to promote the sale, use or other dealings in this Font Software ++without prior written authorization from the Gnome Foundation or Bitstream ++Inc., respectively. For further information, contact: fonts at gnome dot ++org. ++ ++Arev Fonts Copyright ++------------------------------ ++ ++Copyright (c) 2006 by Tavmjong Bah. All Rights Reserved. ++ ++Permission is hereby granted, free of charge, to any person obtaining ++a copy of the fonts accompanying this license ("Fonts") and ++associated documentation files (the "Font Software"), to reproduce ++and distribute the modifications to the Bitstream Vera Font Software, ++including without limitation the rights to use, copy, merge, publish, ++distribute, and/or sell copies of the Font Software, and to permit ++persons to whom the Font Software is furnished to do so, subject to ++the following conditions: ++ ++The above copyright and trademark notices and this permission notice ++shall be included in all copies of one or more of the Font Software ++typefaces. ++ ++The Font Software may be modified, altered, or added to, and in ++particular the designs of glyphs or characters in the Fonts may be ++modified and additional glyphs or characters may be added to the ++Fonts, only if the fonts are renamed to names not containing either ++the words "Tavmjong Bah" or the word "Arev". ++ ++This License becomes null and void to the extent applicable to Fonts ++or Font Software that has been modified and is distributed under the ++"Tavmjong Bah Arev" names. ++ ++The Font Software may be sold as part of a larger software package but ++no copy of one or more of the Font Software typefaces may be sold by ++itself. ++ ++THE FONT SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OF ++MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT ++OF COPYRIGHT, PATENT, TRADEMARK, OR OTHER RIGHT. IN NO EVENT SHALL ++TAVMJONG BAH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++INCLUDING ANY GENERAL, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL ++DAMAGES, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++FROM, OUT OF THE USE OR INABILITY TO USE THE FONT SOFTWARE OR FROM ++OTHER DEALINGS IN THE FONT SOFTWARE. ++ ++Except as contained in this notice, the name of Tavmjong Bah shall not ++be used in advertising or otherwise to promote the sale, use or other ++dealings in this Font Software without prior written authorization ++from Tavmjong Bah. For further information, contact: tavmjong @ free ++. fr. ++ ++TeX Gyre DJV Math ++----------------- ++Fonts are (c) Bitstream (see below). DejaVu changes are in public domain. ++ ++Math extensions done by B. Jackowski, P. Strzelczyk and P. Pianowski ++(on behalf of TeX users groups) are in public domain. ++ ++Letters imported from Euler Fraktur from AMSfonts are (c) American ++Mathematical Society (see below). ++Bitstream Vera Fonts Copyright ++Copyright (c) 2003 by Bitstream, Inc. All Rights Reserved. Bitstream Vera ++is a trademark of Bitstream, Inc. ++ ++Permission is hereby granted, free of charge, to any person obtaining a copy ++of the fonts accompanying this license ("Fonts") and associated documentation ++files (the "Font Software"), to reproduce and distribute the Font Software, ++including without limitation the rights to use, copy, merge, publish, ++distribute, and/or sell copies of the Font Software, and to permit persons ++to whom the Font Software is furnished to do so, subject to the following ++conditions: ++ ++The above copyright and trademark notices and this permission notice ++shall be included in all copies of one or more of the Font Software typefaces. ++ ++The Font Software may be modified, altered, or added to, and in particular ++the designs of glyphs or characters in the Fonts may be modified and ++additional glyphs or characters may be added to the Fonts, only if the ++fonts are renamed to names not containing either the words "Bitstream" ++or the word "Vera". ++ ++This License becomes null and void to the extent applicable to Fonts or ++Font Software that has been modified and is distributed under the ++"Bitstream Vera" names. ++ ++The Font Software may be sold as part of a larger software package but ++no copy of one or more of the Font Software typefaces may be sold by itself. ++ ++THE FONT SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++OR IMPLIED, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OF MERCHANTABILITY, ++FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT OF COPYRIGHT, PATENT, ++TRADEMARK, OR OTHER RIGHT. IN NO EVENT SHALL BITSTREAM OR THE GNOME ++FOUNDATION BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, INCLUDING ++ANY GENERAL, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, ++WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT ++OF THE USE OR INABILITY TO USE THE FONT SOFTWARE OR FROM OTHER DEALINGS IN ++THE FONT SOFTWARE. ++Except as contained in this notice, the names of GNOME, the GNOME ++Foundation, and Bitstream Inc., shall not be used in advertising or ++otherwise to promote the sale, use or other dealings in this Font Software ++without prior written authorization from the GNOME Foundation or ++Bitstream Inc., respectively. ++For further information, contact: fonts at gnome dot org. ++ ++AMSFonts (v. 2.2) copyright ++ ++The PostScript Type 1 implementation of the AMSFonts produced by and ++previously distributed by Blue Sky Research and Y&Y, Inc. are now freely ++available for general use. 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IN NO EVENT SHALL THE ++ AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ++ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, ++ OUT OF OR IN CONNECTION WITH THE MATERIALS OR THE USE OR OTHER DEALINGS IN THE ++ MATERIALS. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% Portions Copyright Eastman Kodak Company 1991-2003 ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to libpng 1.6.39, which may be ++included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++COPYRIGHT NOTICE, DISCLAIMER, and LICENSE ++========================================= ++ ++PNG Reference Library License version 2 ++--------------------------------------- ++ ++Copyright (c) 1995-2022 The PNG Reference Library Authors. ++Copyright (c) 2018-2022 Cosmin Truta ++Copyright (c) 1998-2018 Glenn Randers-Pehrson ++Copyright (c) 1996-1997 Andreas Dilger ++Copyright (c) 1995-1996 Guy Eric Schalnat, Group 42, Inc. ++ ++The software is supplied "as is", without warranty of any kind, ++express or implied, including, without limitation, the warranties ++of merchantability, fitness for a particular purpose, title, and ++non-infringement. In no event shall the Copyright owners, or ++anyone distributing the software, be liable for any damages or ++other liability, whether in contract, tort or otherwise, arising ++from, out of, or in connection with the software, or the use or ++other dealings in the software, even if advised of the possibility ++of such damage. ++ ++Permission is hereby granted to use, copy, modify, and distribute ++this software, or portions hereof, for any purpose, without fee, ++subject to the following restrictions: ++ ++ 1. The origin of this software must not be misrepresented; you ++ must not claim that you wrote the original software. If you ++ use this software in a product, an acknowledgment in the product ++ documentation would be appreciated, but is not required. ++ ++ 2. Altered source versions must be plainly marked as such, and must ++ not be misrepresented as being the original software. ++ ++ 3. This Copyright notice may not be removed or altered from any ++ source or altered source distribution. ++ ++ ++PNG Reference Library License version 1 (for libpng 0.5 through 1.6.35) ++----------------------------------------------------------------------- ++ ++libpng versions 1.0.7, July 1, 2000, through 1.6.35, July 15, 2018 are ++Copyright (c) 2000-2002, 2004, 2006-2018 Glenn Randers-Pehrson, are ++derived from libpng-1.0.6, and are distributed according to the same ++disclaimer and license as libpng-1.0.6 with the following individuals ++added to the list of Contributing Authors: ++ ++ Simon-Pierre Cadieux ++ Eric S. Raymond ++ Mans Rullgard ++ Cosmin Truta ++ Gilles Vollant ++ James Yu ++ Mandar Sahastrabuddhe ++ Google Inc. ++ Vadim Barkov ++ ++and with the following additions to the disclaimer: ++ ++ There is no warranty against interference with your enjoyment of ++ the library or against infringement. There is no warranty that our ++ efforts or the library will fulfill any of your particular purposes ++ or needs. This library is provided with all faults, and the entire ++ risk of satisfactory quality, performance, accuracy, and effort is ++ with the user. ++ ++Some files in the "contrib" directory and some configure-generated ++files that are distributed with libpng have other copyright owners, and ++are released under other open source licenses. ++ ++libpng versions 0.97, January 1998, through 1.0.6, March 20, 2000, are ++Copyright (c) 1998-2000 Glenn Randers-Pehrson, are derived from ++libpng-0.96, and are distributed according to the same disclaimer and ++license as libpng-0.96, with the following individuals added to the ++list of Contributing Authors: ++ ++ Tom Lane ++ Glenn Randers-Pehrson ++ Willem van Schaik ++ ++libpng versions 0.89, June 1996, through 0.96, May 1997, are ++Copyright (c) 1996-1997 Andreas Dilger, are derived from libpng-0.88, ++and are distributed according to the same disclaimer and license as ++libpng-0.88, with the following individuals added to the list of ++Contributing Authors: ++ ++ John Bowler ++ Kevin Bracey ++ Sam Bushell ++ Magnus Holmgren ++ Greg Roelofs ++ Tom Tanner ++ ++Some files in the "scripts" directory have other copyright owners, ++but are released under this license. ++ ++libpng versions 0.5, May 1995, through 0.88, January 1996, are ++Copyright (c) 1995-1996 Guy Eric Schalnat, Group 42, Inc. ++ ++For the purposes of this copyright and license, "Contributing Authors" ++is defined as the following set of individuals: ++ ++ Andreas Dilger ++ Dave Martindale ++ Guy Eric Schalnat ++ Paul Schmidt ++ Tim Wegner ++ ++The PNG Reference Library is supplied "AS IS". The Contributing ++Authors and Group 42, Inc. disclaim all warranties, expressed or ++implied, including, without limitation, the warranties of ++merchantability and of fitness for any purpose. The Contributing ++Authors and Group 42, Inc. assume no liability for direct, indirect, ++incidental, special, exemplary, or consequential damages, which may ++result from the use of the PNG Reference Library, even if advised of ++the possibility of such damage. ++ ++Permission is hereby granted to use, copy, modify, and distribute this ++source code, or portions hereof, for any purpose, without fee, subject ++to the following restrictions: ++ ++ 1. The origin of this source code must not be misrepresented. ++ ++ 2. Altered versions must be plainly marked as such and must not ++ be misrepresented as being the original source. ++ ++ 3. This Copyright notice may not be removed or altered from any ++ source or altered source distribution. ++ ++The Contributing Authors and Group 42, Inc. specifically permit, ++without fee, and encourage the use of this source code as a component ++to supporting the PNG file format in commercial products. If you use ++this source code in a product, acknowledgment is not required but would ++be appreciated. ++ ++TRADEMARK: ++ ++The name "libpng" has not been registered by the Copyright owners ++as a trademark in any jurisdiction. However, because libpng has ++been distributed and maintained world-wide, continually since 1995, ++the Copyright owners claim "common-law trademark protection" in any ++jurisdiction where common-law trademark is recognized. ++ ++OSI CERTIFICATION: ++ ++Libpng is OSI Certified Open Source Software. OSI Certified Open Source is ++a certification mark of the Open Source Initiative. OSI has not addressed ++the additional disclaimers inserted at version 1.0.7. ++ ++EXPORT CONTROL: ++ ++The Copyright owner believes that the Export Control Classification ++Number (ECCN) for libpng is EAR99, which means not subject to export ++controls or International Traffic in Arms Regulations (ITAR) because ++it is open source, publicly available software, that does not contain ++any encryption software. See the EAR, paragraphs 734.3(b)(3) and ++734.7(b). ++ ++Glenn Randers-Pehrson ++glennrp at users.sourceforge.net ++July 15, 2018 ++ ++AUTHORS File Information: ++ ++PNG REFERENCE LIBRARY AUTHORS ++============================= ++ ++This is the list of PNG Reference Library ("libpng") Contributing ++Authors, for copyright and licensing purposes. ++ ++ * Andreas Dilger ++ * Cosmin Truta ++ * Dave Martindale ++ * Eric S. Raymond ++ * Gilles Vollant ++ * Glenn Randers-Pehrson ++ * Greg Roelofs ++ * Guy Eric Schalnat ++ * James Yu ++ * John Bowler ++ * Kevin Bracey ++ * Magnus Holmgren ++ * Mandar Sahastrabuddhe ++ * Mans Rullgard ++ * Matt Sarett ++ * Mike Klein ++ * Pascal Massimino ++ * Paul Schmidt ++ * Qiang Zhou ++ * Sam Bushell ++ * Samuel Williams ++ * Simon-Pierre Cadieux ++ * Tim Wegner ++ * Tom Lane ++ * Tom Tanner ++ * Vadim Barkov ++ * Willem van Schaik ++ * Zhijie Liang ++ * Arm Holdings ++ - Richard Townsend ++ * Google Inc. ++ - Dan Field ++ - Leon Scroggins III ++ - Matt Sarett ++ - Mike Klein ++ - Sami Boukortt ++ ++The build projects, the build scripts, the test scripts, and other ++files in the "ci", "projects", "scripts" and "tests" directories, have ++other copyright owners, but are released under the libpng license. ++ ++Some files in the "contrib" directory, and some tools-generated files ++that are distributed with libpng, have other copyright owners, and are ++released under other open source licenses. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to GIFLIB 5.2.1 & libungif 4.1.3, ++which may be included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++The GIFLIB distribution is Copyright (c) 1997 Eric S. Raymond ++ ++Permission is hereby granted, free of charge, to any person obtaining a copy ++of this software and associated documentation files (the "Software"), to deal ++in the Software without restriction, including without limitation the rights ++to use, copy, modify, merge, publish, distribute, sublicense, and/or sell ++copies of the Software, and to permit persons to whom the Software is ++furnished to do so, subject to the following conditions: ++ ++The above copyright notice and this permission notice shall be included in ++all copies or substantial portions of the Software. ++ ++THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE ++AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ++LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, ++OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN ++THE SOFTWARE. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Little CMS 2.11, which may be ++included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++Little CMS ++Copyright (c) 1998-2020 Marti Maria Saguer ++ ++Permission is hereby granted, free of charge, to any person obtaining a copy ++of this software and associated documentation files (the "Software"), to deal ++in the Software without restriction, including without limitation the rights ++to use, copy, modify, merge, publish, distribute, sublicense, and/or sell ++copies of the Software, and to permit persons to whom the Software is ++furnished to do so, subject to the following conditions: ++ ++The above copyright notice and this permission notice shall be included in all ++copies or substantial portions of the Software. ++ ++THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE ++AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ++LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, ++OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE ++SOFTWARE. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% Lucida is a registered trademark or trademark of Bigelow & Holmes in the ++U.S. and other countries. ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Mesa 3D Graphics Library v4.1, ++which may be included with JRE 8, JDK 8, and OpenJDK 8 source distributions. ++ ++--- begin of LICENSE --- ++ ++ Mesa 3-D Graphics Library v19.2.1 ++ ++ Copyright (C) 1999-2007 Brian Paul All Rights Reserved. ++ ++ Permission is hereby granted, free of charge, to any person obtaining a ++ copy of this software and associated documentation files (the "Software"), ++ to deal in the Software without restriction, including without limitation ++ the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ and/or sell copies of the Software, and to permit persons to whom the ++ Software is furnished to do so, subject to the following conditions: ++ ++ The above copyright notice and this permission notice shall be included ++ in all copies or substantial portions of the Software. ++ ++ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ++ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, ++ OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE ++ SOFTWARE. ++ ++Attention, Contributors ++ ++When contributing to the Mesa project you must agree to the licensing terms ++of the component to which you're contributing. ++The following section lists the primary components of the Mesa distribution ++and their respective licenses. ++Mesa Component Licenses ++ ++ ++ ++Component Location License ++------------------------------------------------------------------ ++Main Mesa code src/mesa/ MIT ++Device drivers src/mesa/drivers/* MIT, generally ++ ++Gallium code src/gallium/ MIT ++ ++Ext headers GL/glext.h Khronos ++ GL/glxext.h Khronos ++ GL/wglext.h Khronos ++ KHR/khrplatform.h Khronos ++ ++***************************************************************************** ++ ++---- ++include/GL/gl.h : ++ ++ ++ Mesa 3-D graphics library ++ ++ Copyright (C) 1999-2006 Brian Paul All Rights Reserved. ++ Copyright (C) 2009 VMware, Inc. All Rights Reserved. ++ ++ Permission is hereby granted, free of charge, to any person obtaining a ++ copy of this software and associated documentation files (the "Software"), ++ to deal in the Software without restriction, including without limitation ++ the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ and/or sell copies of the Software, and to permit persons to whom the ++ Software is furnished to do so, subject to the following conditions: ++ ++ The above copyright notice and this permission notice shall be included ++ in all copies or substantial portions of the Software. ++ ++ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ OTHER DEALINGS IN THE SOFTWARE. ++ ++ ***************************************************************************** ++ ++---- ++include/GL/glext.h ++include/GL/glxext.h ++include/GL/wglxext.h : ++ ++ ++ Copyright (c) 2013 - 2018 The Khronos Group Inc. ++ ++ Permission is hereby granted, free of charge, to any person obtaining a ++ copy of this software and/or associated documentation files (the ++ "Materials"), to deal in the Materials without restriction, including ++ without limitation the rights to use, copy, modify, merge, publish, ++ distribute, sublicense, and/or sell copies of the Materials, and to ++ permit persons to whom the Materials are furnished to do so, subject to ++ the following conditions: ++ ++ The above copyright notice and this permission notice shall be included ++ in all copies or substantial portions of the Materials. ++ ++ THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. ++ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY ++ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, ++ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE ++ MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS. ++ ++ ***************************************************************************** ++ ++---- ++include/KHR/khrplatform.h : ++ ++ Copyright (c) 2008 - 2018 The Khronos Group Inc. ++ ++ Permission is hereby granted, free of charge, to any person obtaining a ++ copy of this software and/or associated documentation files (the ++ "Materials"), to deal in the Materials without restriction, including ++ without limitation the rights to use, copy, modify, merge, publish, ++ distribute, sublicense, and/or sell copies of the Materials, and to ++ permit persons to whom the Materials are furnished to do so, subject to ++ the following conditions: ++ ++ The above copyright notice and this permission notice shall be included ++ in all copies or substantial portions of the Materials. ++ ++ THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. ++ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY ++ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, ++ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE ++ MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS. ++ ++ ***************************************************************************** ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Mozilla Network Security ++Services (NSS), which is supplied with the JDK test suite in the OpenJDK ++source code repository. It is licensed under Mozilla Public License (MPL), ++version 2.0. ++ ++The NSS libraries are supplied in executable form, built from unmodified ++NSS source code labeled with the "NSS_3_16_RTM" HG tag. ++ ++The NSS source code is available in the OpenJDK source code repository at: ++ jdk/test/sun/security/pkcs11/nss/src ++ ++The NSS libraries are available in the OpenJDK source code repository at: ++ jdk/test/sun/security/pkcs11/nss/lib ++ ++--- begin of LICENSE --- ++ ++Mozilla Public License Version 2.0 ++================================== ++ ++1. Definitions ++-------------- ++ ++1.1. "Contributor" ++ means each individual or legal entity that creates, contributes to ++ the creation of, or owns Covered Software. ++ ++1.2. "Contributor Version" ++ means the combination of the Contributions of others (if any) used ++ by a Contributor and that particular Contributor's Contribution. ++ ++1.3. "Contribution" ++ means Covered Software of a particular Contributor. ++ ++1.4. "Covered Software" ++ means Source Code Form to which the initial Contributor has attached ++ the notice in Exhibit A, the Executable Form of such Source Code ++ Form, and Modifications of such Source Code Form, in each case ++ including portions thereof. ++ ++1.5. "Incompatible With Secondary Licenses" ++ means ++ ++ (a) that the initial Contributor has attached the notice described ++ in Exhibit B to the Covered Software; or ++ ++ (b) that the Covered Software was made available under the terms of ++ version 1.1 or earlier of the License, but not also under the ++ terms of a Secondary License. ++ ++1.6. "Executable Form" ++ means any form of the work other than Source Code Form. ++ ++1.7. "Larger Work" ++ means a work that combines Covered Software with other material, in ++ a separate file or files, that is not Covered Software. ++ ++1.8. "License" ++ means this document. ++ ++1.9. "Licensable" ++ means having the right to grant, to the maximum extent possible, ++ whether at the time of the initial grant or subsequently, any and ++ all of the rights conveyed by this License. ++ ++1.10. "Modifications" ++ means any of the following: ++ ++ (a) any file in Source Code Form that results from an addition to, ++ deletion from, or modification of the contents of Covered ++ Software; or ++ ++ (b) any new file in Source Code Form that contains any Covered ++ Software. ++ ++1.11. "Patent Claims" of a Contributor ++ means any patent claim(s), including without limitation, method, ++ process, and apparatus claims, in any patent Licensable by such ++ Contributor that would be infringed, but for the grant of the ++ License, by the making, using, selling, offering for sale, having ++ made, import, or transfer of either its Contributions or its ++ Contributor Version. ++ ++1.12. "Secondary License" ++ means either the GNU General Public License, Version 2.0, the GNU ++ Lesser General Public License, Version 2.1, the GNU Affero General ++ Public License, Version 3.0, or any later versions of those ++ licenses. ++ ++1.13. "Source Code Form" ++ means the form of the work preferred for making modifications. ++ ++1.14. "You" (or "Your") ++ means an individual or a legal entity exercising rights under this ++ License. For legal entities, "You" includes any entity that ++ controls, is controlled by, or is under common control with You. For ++ purposes of this definition, "control" means (a) the power, direct ++ or indirect, to cause the direction or management of such entity, ++ whether by contract or otherwise, or (b) ownership of more than ++ fifty percent (50%) of the outstanding shares or beneficial ++ ownership of such entity. ++ ++2. License Grants and Conditions ++-------------------------------- ++ ++2.1. Grants ++ ++Each Contributor hereby grants You a world-wide, royalty-free, ++non-exclusive license: ++ ++(a) under intellectual property rights (other than patent or trademark) ++ Licensable by such Contributor to use, reproduce, make available, ++ modify, display, perform, distribute, and otherwise exploit its ++ Contributions, either on an unmodified basis, with Modifications, or ++ as part of a Larger Work; and ++ ++(b) under Patent Claims of such Contributor to make, use, sell, offer ++ for sale, have made, import, and otherwise transfer either its ++ Contributions or its Contributor Version. ++ ++2.2. Effective Date ++ ++The licenses granted in Section 2.1 with respect to any Contribution ++become effective for each Contribution on the date the Contributor first ++distributes such Contribution. ++ ++2.3. Limitations on Grant Scope ++ ++The licenses granted in this Section 2 are the only rights granted under ++this License. No additional rights or licenses will be implied from the ++distribution or licensing of Covered Software under this License. ++Notwithstanding Section 2.1(b) above, no patent license is granted by a ++Contributor: ++ ++(a) for any code that a Contributor has removed from Covered Software; ++ or ++ ++(b) for infringements caused by: (i) Your and any other third party's ++ modifications of Covered Software, or (ii) the combination of its ++ Contributions with other software (except as part of its Contributor ++ Version); or ++ ++(c) under Patent Claims infringed by Covered Software in the absence of ++ its Contributions. ++ ++This License does not grant any rights in the trademarks, service marks, ++or logos of any Contributor (except as may be necessary to comply with ++the notice requirements in Section 3.4). ++ ++2.4. Subsequent Licenses ++ ++No Contributor makes additional grants as a result of Your choice to ++distribute the Covered Software under a subsequent version of this ++License (see Section 10.2) or under the terms of a Secondary License (if ++permitted under the terms of Section 3.3). ++ ++2.5. Representation ++ ++Each Contributor represents that the Contributor believes its ++Contributions are its original creation(s) or it has sufficient rights ++to grant the rights to its Contributions conveyed by this License. ++ ++2.6. Fair Use ++ ++This License is not intended to limit any rights You have under ++applicable copyright doctrines of fair use, fair dealing, or other ++equivalents. ++ ++2.7. Conditions ++ ++Sections 3.1, 3.2, 3.3, and 3.4 are conditions of the licenses granted ++in Section 2.1. ++ ++3. Responsibilities ++------------------- ++ ++3.1. Distribution of Source Form ++ ++All distribution of Covered Software in Source Code Form, including any ++Modifications that You create or to which You contribute, must be under ++the terms of this License. You must inform recipients that the Source ++Code Form of the Covered Software is governed by the terms of this ++License, and how they can obtain a copy of this License. You may not ++attempt to alter or restrict the recipients' rights in the Source Code ++Form. ++ ++3.2. Distribution of Executable Form ++ ++If You distribute Covered Software in Executable Form then: ++ ++(a) such Covered Software must also be made available in Source Code ++ Form, as described in Section 3.1, and You must inform recipients of ++ the Executable Form how they can obtain a copy of such Source Code ++ Form by reasonable means in a timely manner, at a charge no more ++ than the cost of distribution to the recipient; and ++ ++(b) You may distribute such Executable Form under the terms of this ++ License, or sublicense it under different terms, provided that the ++ license for the Executable Form does not attempt to limit or alter ++ the recipients' rights in the Source Code Form under this License. ++ ++3.3. Distribution of a Larger Work ++ ++You may create and distribute a Larger Work under terms of Your choice, ++provided that You also comply with the requirements of this License for ++the Covered Software. If the Larger Work is a combination of Covered ++Software with a work governed by one or more Secondary Licenses, and the ++Covered Software is not Incompatible With Secondary Licenses, this ++License permits You to additionally distribute such Covered Software ++under the terms of such Secondary License(s), so that the recipient of ++the Larger Work may, at their option, further distribute the Covered ++Software under the terms of either this License or such Secondary ++License(s). ++ ++3.4. Notices ++ ++You may not remove or alter the substance of any license notices ++(including copyright notices, patent notices, disclaimers of warranty, ++or limitations of liability) contained within the Source Code Form of ++the Covered Software, except that You may alter any license notices to ++the extent required to remedy known factual inaccuracies. ++ ++3.5. Application of Additional Terms ++ ++You may choose to offer, and to charge a fee for, warranty, support, ++indemnity or liability obligations to one or more recipients of Covered ++Software. However, You may do so only on Your own behalf, and not on ++behalf of any Contributor. You must make it absolutely clear that any ++such warranty, support, indemnity, or liability obligation is offered by ++You alone, and You hereby agree to indemnify every Contributor for any ++liability incurred by such Contributor as a result of warranty, support, ++indemnity or liability terms You offer. You may include additional ++disclaimers of warranty and limitations of liability specific to any ++jurisdiction. ++ ++4. Inability to Comply Due to Statute or Regulation ++--------------------------------------------------- ++ ++If it is impossible for You to comply with any of the terms of this ++License with respect to some or all of the Covered Software due to ++statute, judicial order, or regulation then You must: (a) comply with ++the terms of this License to the maximum extent possible; and (b) ++describe the limitations and the code they affect. Such description must ++be placed in a text file included with all distributions of the Covered ++Software under this License. Except to the extent prohibited by statute ++or regulation, such description must be sufficiently detailed for a ++recipient of ordinary skill to be able to understand it. ++ ++5. Termination ++-------------- ++ ++5.1. The rights granted under this License will terminate automatically ++if You fail to comply with any of its terms. However, if You become ++compliant, then the rights granted under this License from a particular ++Contributor are reinstated (a) provisionally, unless and until such ++Contributor explicitly and finally terminates Your grants, and (b) on an ++ongoing basis, if such Contributor fails to notify You of the ++non-compliance by some reasonable means prior to 60 days after You have ++come back into compliance. Moreover, Your grants from a particular ++Contributor are reinstated on an ongoing basis if such Contributor ++notifies You of the non-compliance by some reasonable means, this is the ++first time You have received notice of non-compliance with this License ++from such Contributor, and You become compliant prior to 30 days after ++Your receipt of the notice. ++ ++5.2. If You initiate litigation against any entity by asserting a patent ++infringement claim (excluding declaratory judgment actions, ++counter-claims, and cross-claims) alleging that a Contributor Version ++directly or indirectly infringes any patent, then the rights granted to ++You by any and all Contributors for the Covered Software under Section ++2.1 of this License shall terminate. ++ ++5.3. In the event of termination under Sections 5.1 or 5.2 above, all ++end user license agreements (excluding distributors and resellers) which ++have been validly granted by You or Your distributors under this License ++prior to termination shall survive termination. ++ ++************************************************************************ ++* * ++* 6. Disclaimer of Warranty * ++* ------------------------- * ++* * ++* Covered Software is provided under this License on an "as is" * ++* basis, without warranty of any kind, either expressed, implied, or * ++* statutory, including, without limitation, warranties that the * ++* Covered Software is free of defects, merchantable, fit for a * ++* particular purpose or non-infringing. The entire risk as to the * ++* quality and performance of the Covered Software is with You. * ++* Should any Covered Software prove defective in any respect, You * ++* (not any Contributor) assume the cost of any necessary servicing, * ++* repair, or correction. This disclaimer of warranty constitutes an * ++* essential part of this License. No use of any Covered Software is * ++* authorized under this License except under this disclaimer. * ++* * ++************************************************************************ ++ ++************************************************************************ ++* * ++* 7. Limitation of Liability * ++* -------------------------- * ++* * ++* Under no circumstances and under no legal theory, whether tort * ++* (including negligence), contract, or otherwise, shall any * ++* Contributor, or anyone who distributes Covered Software as * ++* permitted above, be liable to You for any direct, indirect, * ++* special, incidental, or consequential damages of any character * ++* including, without limitation, damages for lost profits, loss of * ++* goodwill, work stoppage, computer failure or malfunction, or any * ++* and all other commercial damages or losses, even if such party * ++* shall have been informed of the possibility of such damages. This * ++* limitation of liability shall not apply to liability for death or * ++* personal injury resulting from such party's negligence to the * ++* extent applicable law prohibits such limitation. Some * ++* jurisdictions do not allow the exclusion or limitation of * ++* incidental or consequential damages, so this exclusion and * ++* limitation may not apply to You. * ++* * ++************************************************************************ ++ ++8. Litigation ++------------- ++ ++Any litigation relating to this License may be brought only in the ++courts of a jurisdiction where the defendant maintains its principal ++place of business and such litigation shall be governed by laws of that ++jurisdiction, without reference to its conflict-of-law provisions. ++Nothing in this Section shall prevent a party's ability to bring ++cross-claims or counter-claims. ++ ++9. Miscellaneous ++---------------- ++ ++This License represents the complete agreement concerning the subject ++matter hereof. If any provision of this License is held to be ++unenforceable, such provision shall be reformed only to the extent ++necessary to make it enforceable. Any law or regulation which provides ++that the language of a contract shall be construed against the drafter ++shall not be used to construe this License against a Contributor. ++ ++10. Versions of the License ++--------------------------- ++ ++10.1. New Versions ++ ++Mozilla Foundation is the license steward. Except as provided in Section ++10.3, no one other than the license steward has the right to modify or ++publish new versions of this License. Each version will be given a ++distinguishing version number. ++ ++10.2. Effect of New Versions ++ ++You may distribute the Covered Software under the terms of the version ++of the License under which You originally received the Covered Software, ++or under the terms of any subsequent version published by the license ++steward. ++ ++10.3. Modified Versions ++ ++If you create software not governed by this License, and you want to ++create a new license for such software, you may create and use a ++modified version of this License if you rename the license and remove ++any references to the name of the license steward (except to note that ++such modified license differs from this License). ++ ++10.4. Distributing Source Code Form that is Incompatible With Secondary ++Licenses ++ ++If You choose to distribute Source Code Form that is Incompatible With ++Secondary Licenses under the terms of this version of the License, the ++notice described in Exhibit B of this License must be attached. ++ ++Exhibit A - Source Code Form License Notice ++------------------------------------------- ++ ++ This Source Code Form is subject to the terms of the Mozilla Public ++ License, v. 2.0. If a copy of the MPL was not distributed with this ++ file, You can obtain one at http://mozilla.org/MPL/2.0/. ++ ++If it is not possible or desirable to put the notice in a particular ++file, then You may include the notice in a location (such as a LICENSE ++file in a relevant directory) where a recipient would be likely to look ++for such a notice. ++ ++You may add additional accurate notices of copyright ownership. ++ ++Exhibit B - "Incompatible With Secondary Licenses" Notice ++--------------------------------------------------------- ++ ++ This Source Code Form is "Incompatible With Secondary Licenses", as ++ defined by the Mozilla Public License, v. 2.0. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to PC/SC Lite v1.8.26, ++which may be included with JRE 8, JDK 8, and OpenJDK 8 on Linux and Solaris. ++ ++--- begin of LICENSE --- ++ ++Copyright (c) 1999-2003 David Corcoran ++Copyright (c) 2001-2011 Ludovic Rousseau ++All rights reserved. ++ ++Redistribution and use in source and binary forms, with or without ++modification, are permitted provided that the following conditions ++are met: ++ ++1. Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++2. Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++3. The name of the author may not be used to endorse or promote products ++ derived from this software without specific prior written permission. ++ ++Changes to this license can be made only by the copyright author with ++explicit written consent. ++ ++THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to PorterStemmer v4, which may be ++included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++See: http://tartarus.org/~martin/PorterStemmer ++ ++The software is completely free for any purpose, unless notes at the head of ++the program text indicates otherwise (which is rare). In any case, the notes ++about licensing are never more restrictive than the BSD License. ++ ++In every case where the software is not written by me (Martin Porter), this ++licensing arrangement has been endorsed by the contributor, and it is ++therefore unnecessary to ask the contributor again to confirm it. ++ ++I have not asked any contributors (or their employers, if they have them) for ++proofs that they have the right to distribute their software in this way. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Relax NG Object/Parser v.20050510, ++which may be included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++Copyright (c) Kohsuke Kawaguchi ++ ++Permission is hereby granted, free of charge, to any person obtaining a copy ++of this software and associated documentation files (the "Software"), to deal ++in the Software without restriction, including without limitation the rights ++to use, copy, modify, merge, publish, distribute, sublicense, and/or sell ++copies of the Software, and to permit persons to whom the Software is ++furnished to do so, subject to the following conditions: The above copyright ++notice and this permission notice shall be included in all copies or ++substantial portions of the Software. ++ ++THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE ++AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ++LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, ++OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE ++SOFTWARE. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to RelaxNGCC v1.12, which may be ++included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++Copyright (c) 2000-2003 Daisuke Okajima and Kohsuke Kawaguchi. ++All rights reserved. ++ ++Redistribution and use in source and binary forms, with or without ++modification, are permitted provided that the following conditions are met: ++ ++1. Redistributions of source code must retain the above copyright notice, this ++ list of conditions and the following disclaimer. ++ ++2. Redistributions in binary form must reproduce the above copyright notice, ++ this list of conditions and the following disclaimer in the documentation ++ and/or other materials provided with the distribution. ++ ++3. The end-user documentation included with the redistribution, if any, must ++ include the following acknowledgment: ++ ++ "This product includes software developed by Daisuke Okajima ++ and Kohsuke Kawaguchi (http://relaxngcc.sf.net/)." ++ ++Alternately, this acknowledgment may appear in the software itself, if and ++wherever such third-party acknowledgments normally appear. ++ ++4. The names of the copyright holders must not be used to endorse or promote ++ products derived from this software without prior written permission. For ++ written permission, please contact the copyright holders. ++ ++5. Products derived from this software may not be called "RELAXNGCC", nor may ++ "RELAXNGCC" appear in their name, without prior written permission of the ++ copyright holders. ++ ++THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESSED OR IMPLIED WARRANTIES, ++INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND ++FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.IN NO EVENT SHALL THE APACHE ++SOFTWARE FOUNDATION OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ++INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ++EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Relax NG Datatype 1.0, which ++may be included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++Copyright (c) 2005, 2010 Thai Open Source Software Center Ltd ++All rights reserved. ++ ++Redistribution and use in source and binary forms, with or without ++modification, are permitted provided that the following conditions are ++met: ++ ++ Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ Neither the names of the copyright holders nor the names of its ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR ++CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++--- end of LICENSE --- ++ ++-------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to SoftFloat version 2b, which may be ++included with JRE 8, JDK 8, and OpenJDK 8 on Linux/ARM. ++ ++--- begin of LICENSE --- ++ ++Use of any of this software is governed by the terms of the license below: ++ ++SoftFloat was written by me, John R. Hauser. This work was made possible in ++part by the International Computer Science Institute, located at Suite 600, ++1947 Center Street, Berkeley, California 94704. Funding was partially ++provided by the National Science Foundation under grant MIP-9311980. The ++original version of this code was written as part of a project to build ++a fixed-point vector processor in collaboration with the University of ++California at Berkeley, overseen by Profs. Nelson Morgan and John Wawrzynek. ++ ++THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort ++has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT ++TIMES RESULT IN INCORRECT BEHAVIOR. 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All third party trademarks referenced herein are ++the property of their respective owners. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to UPX v3.01, which may be included ++with JRE 8 on Windows. ++ ++--- begin of LICENSE --- ++ ++Use of any of this software is governed by the terms of the license below: ++ ++ ++ ooooo ooo ooooooooo. ooooooo ooooo ++ `888' `8' `888 `Y88. `8888 d8' ++ 888 8 888 .d88' Y888..8P ++ 888 8 888ooo88P' `8888' ++ 888 8 888 .8PY888. ++ `88. .8' 888 d8' `888b ++ `YbodP' o888o o888o o88888o ++ ++ ++ The Ultimate Packer for eXecutables ++ Copyright (c) 1996-2000 Markus Oberhumer & Laszlo Molnar ++ http://wildsau.idv.uni-linz.ac.at/mfx/upx.html ++ http://www.nexus.hu/upx ++ http://upx.tsx.org ++ ++ ++PLEASE CAREFULLY READ THIS LICENSE AGREEMENT, ESPECIALLY IF YOU PLAN ++TO MODIFY THE UPX SOURCE CODE OR USE A MODIFIED UPX VERSION. ++ ++ ++ABSTRACT ++======== ++ ++ UPX and UCL are copyrighted software distributed under the terms ++ of the GNU General Public License (hereinafter the "GPL"). ++ ++ The stub which is imbedded in each UPX compressed program is part ++ of UPX and UCL, and contains code that is under our copyright. The ++ terms of the GNU General Public License still apply as compressing ++ a program is a special form of linking with our stub. ++ ++ As a special exception we grant the free usage of UPX for all ++ executables, including commercial programs. ++ See below for details and restrictions. ++ ++ ++COPYRIGHT ++========= ++ ++ UPX and UCL are copyrighted software. All rights remain with the authors. ++ ++ UPX is Copyright (C) 1996-2000 Markus Franz Xaver Johannes Oberhumer ++ UPX is Copyright (C) 1996-2000 Laszlo Molnar ++ ++ UCL is Copyright (C) 1996-2000 Markus Franz Xaver Johannes Oberhumer ++ ++ ++GNU GENERAL PUBLIC LICENSE ++========================== ++ ++ UPX and the UCL library are free software; you can redistribute them ++ and/or modify them under the terms of the GNU General Public License as ++ published by the Free Software Foundation; either version 2 of ++ the License, or (at your option) any later version. ++ ++ UPX and UCL are distributed in the hope that they will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ GNU General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with this program; see the file COPYING. ++ ++ ++SPECIAL EXCEPTION FOR COMPRESSED EXECUTABLES ++============================================ ++ ++ The stub which is imbedded in each UPX compressed program is part ++ of UPX and UCL, and contains code that is under our copyright. The ++ terms of the GNU General Public License still apply as compressing ++ a program is a special form of linking with our stub. ++ ++ Hereby Markus F.X.J. Oberhumer and Laszlo Molnar grant you special ++ permission to freely use and distribute all UPX compressed programs ++ (including commercial ones), subject to the following restrictions: ++ ++ 1. You must compress your program with a completely unmodified UPX ++ version; either with our precompiled version, or (at your option) ++ with a self compiled version of the unmodified UPX sources as ++ distributed by us. ++ 2. This also implies that the UPX stub must be completely unmodfied, i.e. ++ the stub imbedded in your compressed program must be byte-identical ++ to the stub that is produced by the official unmodified UPX version. ++ 3. The decompressor and any other code from the stub must exclusively get ++ used by the unmodified UPX stub for decompressing your program at ++ program startup. No portion of the stub may get read, copied, ++ called or otherwise get used or accessed by your program. ++ ++ ++ANNOTATIONS ++=========== ++ ++ - You can use a modified UPX version or modified UPX stub only for ++ programs that are compatible with the GNU General Public License. ++ ++ - We grant you special permission to freely use and distribute all UPX ++ compressed programs. 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Please contact us if you would like to ++ incorporate parts of UPX or UCL into such a product. ++ ++ ++ ++Markus F.X.J. Oberhumer Laszlo Molnar ++markus.oberhumer@jk.uni-linz.ac.at ml1050@cdata.tvnet.hu ++ ++Linz, Austria, 25 Feb 2000 ++ ++Additional License(s) ++ ++The UPX license file is at http://upx.sourceforge.net/upx-license.html. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Xfree86-VidMode Extension 1.0, ++which may be included with JRE 8, JDK 8, and OpenJDK 8 on Linux and Solaris. ++ ++--- begin of LICENSE --- ++ ++Version 1.1 of XFree86 ProjectLicence. ++ ++Copyright (C) 1994-2004 The XFree86 Project, Inc. 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DejaVu changes are in public domain. ++Glyphs imported from Arev fonts are (c) Tavmjong Bah (see below) ++ ++ ++Bitstream Vera Fonts Copyright ++------------------------------ ++ ++Copyright (c) 2003 by Bitstream, Inc. All Rights Reserved. Bitstream Vera is ++a trademark of Bitstream, Inc. ++ ++Permission is hereby granted, free of charge, to any person obtaining a copy ++of the fonts accompanying this license ("Fonts") and associated ++documentation files (the "Font Software"), to reproduce and distribute the ++Font Software, including without limitation the rights to use, copy, merge, ++publish, distribute, and/or sell copies of the Font Software, and to permit ++persons to whom the Font Software is furnished to do so, subject to the ++following conditions: ++ ++The above copyright and trademark notices and this permission notice shall ++be included in all copies of one or more of the Font Software typefaces. ++ ++The Font Software may be modified, altered, or added to, and in particular ++the designs of glyphs or characters in the Fonts may be modified and ++additional glyphs or characters may be added to the Fonts, only if the fonts ++are renamed to names not containing either the words "Bitstream" or the word ++"Vera". ++ ++This License becomes null and void to the extent applicable to Fonts or Font ++Software that has been modified and is distributed under the "Bitstream ++Vera" names. ++ ++The Font Software may be sold as part of a larger software package but no ++copy of one or more of the Font Software typefaces may be sold by itself. ++ ++THE FONT SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++OR IMPLIED, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OF MERCHANTABILITY, ++FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT OF COPYRIGHT, PATENT, ++TRADEMARK, OR OTHER RIGHT. IN NO EVENT SHALL BITSTREAM OR THE GNOME ++FOUNDATION BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, INCLUDING ++ANY GENERAL, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, ++WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF ++THE USE OR INABILITY TO USE THE FONT SOFTWARE OR FROM OTHER DEALINGS IN THE ++FONT SOFTWARE. ++ ++Except as contained in this notice, the names of Gnome, the Gnome ++Foundation, and Bitstream Inc., shall not be used in advertising or ++otherwise to promote the sale, use or other dealings in this Font Software ++without prior written authorization from the Gnome Foundation or Bitstream ++Inc., respectively. For further information, contact: fonts at gnome dot ++org. ++ ++Arev Fonts Copyright ++------------------------------ ++ ++Copyright (c) 2006 by Tavmjong Bah. All Rights Reserved. ++ ++Permission is hereby granted, free of charge, to any person obtaining ++a copy of the fonts accompanying this license ("Fonts") and ++associated documentation files (the "Font Software"), to reproduce ++and distribute the modifications to the Bitstream Vera Font Software, ++including without limitation the rights to use, copy, merge, publish, ++distribute, and/or sell copies of the Font Software, and to permit ++persons to whom the Font Software is furnished to do so, subject to ++the following conditions: ++ ++The above copyright and trademark notices and this permission notice ++shall be included in all copies of one or more of the Font Software ++typefaces. ++ ++The Font Software may be modified, altered, or added to, and in ++particular the designs of glyphs or characters in the Fonts may be ++modified and additional glyphs or characters may be added to the ++Fonts, only if the fonts are renamed to names not containing either ++the words "Tavmjong Bah" or the word "Arev". ++ ++This License becomes null and void to the extent applicable to Fonts ++or Font Software that has been modified and is distributed under the ++"Tavmjong Bah Arev" names. ++ ++The Font Software may be sold as part of a larger software package but ++no copy of one or more of the Font Software typefaces may be sold by ++itself. ++ ++THE FONT SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OF ++MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT ++OF COPYRIGHT, PATENT, TRADEMARK, OR OTHER RIGHT. IN NO EVENT SHALL ++TAVMJONG BAH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++INCLUDING ANY GENERAL, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL ++DAMAGES, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++FROM, OUT OF THE USE OR INABILITY TO USE THE FONT SOFTWARE OR FROM ++OTHER DEALINGS IN THE FONT SOFTWARE. ++ ++Except as contained in this notice, the name of Tavmjong Bah shall not ++be used in advertising or otherwise to promote the sale, use or other ++dealings in this Font Software without prior written authorization ++from Tavmjong Bah. For further information, contact: tavmjong @ free ++. fr. ++ ++TeX Gyre DJV Math ++----------------- ++Fonts are (c) Bitstream (see below). DejaVu changes are in public domain. ++ ++Math extensions done by B. Jackowski, P. Strzelczyk and P. Pianowski ++(on behalf of TeX users groups) are in public domain. ++ ++Letters imported from Euler Fraktur from AMSfonts are (c) American ++Mathematical Society (see below). ++Bitstream Vera Fonts Copyright ++Copyright (c) 2003 by Bitstream, Inc. All Rights Reserved. Bitstream Vera ++is a trademark of Bitstream, Inc. ++ ++Permission is hereby granted, free of charge, to any person obtaining a copy ++of the fonts accompanying this license ("Fonts") and associated documentation ++files (the "Font Software"), to reproduce and distribute the Font Software, ++including without limitation the rights to use, copy, merge, publish, ++distribute, and/or sell copies of the Font Software, and to permit persons ++to whom the Font Software is furnished to do so, subject to the following ++conditions: ++ ++The above copyright and trademark notices and this permission notice ++shall be included in all copies of one or more of the Font Software typefaces. ++ ++The Font Software may be modified, altered, or added to, and in particular ++the designs of glyphs or characters in the Fonts may be modified and ++additional glyphs or characters may be added to the Fonts, only if the ++fonts are renamed to names not containing either the words "Bitstream" ++or the word "Vera". ++ ++This License becomes null and void to the extent applicable to Fonts or ++Font Software that has been modified and is distributed under the ++"Bitstream Vera" names. ++ ++The Font Software may be sold as part of a larger software package but ++no copy of one or more of the Font Software typefaces may be sold by itself. ++ ++THE FONT SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++OR IMPLIED, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OF MERCHANTABILITY, ++FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT OF COPYRIGHT, PATENT, ++TRADEMARK, OR OTHER RIGHT. IN NO EVENT SHALL BITSTREAM OR THE GNOME ++FOUNDATION BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, INCLUDING ++ANY GENERAL, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, ++WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT ++OF THE USE OR INABILITY TO USE THE FONT SOFTWARE OR FROM OTHER DEALINGS IN ++THE FONT SOFTWARE. ++Except as contained in this notice, the names of GNOME, the GNOME ++Foundation, and Bitstream Inc., shall not be used in advertising or ++otherwise to promote the sale, use or other dealings in this Font Software ++without prior written authorization from the GNOME Foundation or ++Bitstream Inc., respectively. ++For further information, contact: fonts at gnome dot org. ++ ++AMSFonts (v. 2.2) copyright ++ ++The PostScript Type 1 implementation of the AMSFonts produced by and ++previously distributed by Blue Sky Research and Y&Y, Inc. are now freely ++available for general use. This has been accomplished through the ++cooperation ++of a consortium of scientific publishers with Blue Sky Research and Y&Y. ++Members of this consortium include: ++ ++Elsevier Science IBM Corporation Society for Industrial and Applied ++Mathematics (SIAM) Springer-Verlag American Mathematical Society (AMS) ++ ++In order to assure the authenticity of these fonts, copyright will be ++held by the American Mathematical Society. This is not meant to restrict ++in any way the legitimate use of the fonts, such as (but not limited to) ++electronic distribution of documents containing these fonts, inclusion of ++these fonts into other public domain or commercial font collections or computer ++applications, use of the outline data to create derivative fonts and/or ++faces, etc. However, the AMS does require that the AMS copyright notice be ++removed from any derivative versions of the fonts which have been altered in ++any way. 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The names "Graz University of Technology" and "IAIK of Graz University of ++ Technology" must not be used to endorse or promote products derived from this ++ software without prior written permission. ++ ++5. Products derived from this software may not be called "IAIK PKCS Wrapper", ++ nor may "IAIK" appear in their name, without prior written permission of ++ Graz University of Technology. ++ ++THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESSED OR IMPLIED WARRANTIES, ++INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND ++FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 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IN ++NO EVENT SHALL THE COPYRIGHT HOLDER OR HOLDERS INCLUDED IN THIS NOTICE BE ++LIABLE FOR ANY CLAIM, OR ANY SPECIAL INDIRECT OR CONSEQUENTIAL DAMAGES, OR ANY ++DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ++ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN ++CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. ++ ++Except as contained in this notice, the name of a copyright holder shall not ++be used in advertising or otherwise to promote the sale, use or other dealings ++in this Software without prior written authorization of the copyright holder. ++All trademarks and registered trademarks mentioned herein are the property of ++their respective owners. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to IJG JPEG 6b, which may be ++included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++This software is copyright (C) 1991-1998, Thomas G. Lane. ++All Rights Reserved except as specified below. ++ ++Permission is hereby granted to use, copy, modify, and distribute this ++software (or portions thereof) for any purpose, without fee, subject to these ++conditions: ++(1) If any part of the source code for this software is distributed, then this ++README file must be included, with this copyright and no-warranty notice ++unaltered; and any additions, deletions, or changes to the original files ++must be clearly indicated in accompanying documentation. ++(2) If only executable code is distributed, then the accompanying ++documentation must state that "this software is based in part on the work of ++the Independent JPEG Group". ++(3) Permission for use of this software is granted only if the user accepts ++full responsibility for any undesirable consequences; the authors accept ++NO LIABILITY for damages of any kind. ++ ++These conditions apply to any software derived from or based on the IJG code, ++not just to the unmodified library. If you use our work, you ought to ++acknowledge us. ++ ++Permission is NOT granted for the use of any IJG author's name or company name ++in advertising or publicity relating to this software or products derived from ++it. This software may be referred to only as "the Independent JPEG Group's ++software". ++ ++We specifically permit and encourage the use of this software as the basis of ++commercial products, provided that all warranty or liability claims are ++assumed by the product vendor. ++ ++--- end of LICENSE --- ++ ++-------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Jing 20030619, which may ++be included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++Copyright (c) 2001-2003 Thai Open Source Software Center Ltd All ++rights reserved. ++ ++Redistribution and use in source and binary forms, with or without ++modification, are permitted provided that the following conditions ++are met: ++ ++Redistributions of source code must retain the above copyright ++notice, this list of conditions and the following disclaimer. ++ ++Redistributions in binary form must reproduce the above copyright ++notice, this list of conditions and the following disclaimer in the ++documentation and/or other materials provided with the distribution. ++ ++Neither the name of the Thai Open Source Software Center Ltd nor ++the names of its contributors may be used to endorse or promote ++products derived from this software without specific prior written ++permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ++FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ++REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF ++USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ++ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, ++OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ++OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF ++SUCH DAMAGE. ++ ++--- end of LICENSE --- ++ ++-------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Joni v2.1.16, which may be ++included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++Copyright (c) 2017 JRuby Team ++ ++Permission is hereby granted, free of charge, to any person obtaining a copy ++of this software and associated documentation files (the "Software"), to deal ++in the Software without restriction, including without limitation the rights ++to use, copy, modify, merge, publish, distribute, sublicense, and/or sell ++copies of the Software, and to permit persons to whom the Software is ++furnished to do so, subject to the following conditions: ++ ++The above copyright notice and this permission notice shall be included in all ++copies or substantial portions of the Software. ++ ++THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE ++AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ++LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, ++OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE ++SOFTWARE. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to JOpt-Simple v3.0, which may be ++included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++ Copyright (c) 2004-2009 Paul R. Holser, Jr. ++ ++ Permission is hereby granted, free of charge, to any person obtaining ++ a copy of this software and associated documentation files (the ++ "Software"), to deal in the Software without restriction, including ++ without limitation the rights to use, copy, modify, merge, publish, ++ distribute, sublicense, and/or sell copies of the Software, and to ++ permit persons to whom the Software is furnished to do so, subject to ++ the following conditions: ++ ++ The above copyright notice and this permission notice shall be ++ included in all copies or substantial portions of the Software. ++ ++ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE ++ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION ++ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION ++ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ ++--- end of LICENSE --- ++ ++-------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Kerberos functionality, which ++which may be included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++ (C) Copyright IBM Corp. 1999 All Rights Reserved. ++ Copyright 1997 The Open Group Research Institute. All rights reserved. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Kerberos functionality from ++FundsXpress, INC., which may be included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++ Copyright (C) 1998 by the FundsXpress, INC. ++ ++ All rights reserved. ++ ++ Export of this software from the United States of America may require ++ a specific license from the United States Government. It is the ++ responsibility of any person or organization contemplating export to ++ obtain such a license before exporting. ++ ++ WITHIN THAT CONSTRAINT, permission to use, copy, modify, and ++ distribute this software and its documentation for any purpose and ++ without fee is hereby granted, provided that the above copyright ++ notice appear in all copies and that both that copyright notice and ++ this permission notice appear in supporting documentation, and that ++ the name of FundsXpress. not be used in advertising or publicity pertaining ++ to distribution of the software without specific, written prior ++ permission. FundsXpress makes no representations about the suitability of ++ this software for any purpose. It is provided "as is" without express ++ or implied warranty. ++ ++ THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR ++ IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED ++ WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. ++ ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Kronos OpenGL headers, which may be ++included with JDK 8 and OpenJDK 8 source distributions. ++ ++--- begin of LICENSE --- ++ ++ Copyright (c) 2007 The Khronos Group Inc. ++ ++ Permission is hereby granted, free of charge, to any person obtaining a copy ++ of this software and/or associated documentation files (the "Materials"), to ++ deal in the Materials without restriction, including without limitation the ++ rights to use, copy, modify, merge, publish, distribute, sublicense, and/or ++ sell copies of the Materials, and to permit persons to whom the Materials are ++ furnished to do so, subject to the following conditions: ++ ++ The above copyright notice and this permission notice shall be included in all ++ copies or substantial portions of the Materials. ++ ++ THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE ++ AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ++ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, ++ OUT OF OR IN CONNECTION WITH THE MATERIALS OR THE USE OR OTHER DEALINGS IN THE ++ MATERIALS. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% Portions Copyright Eastman Kodak Company 1991-2003 ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to libpng 1.6.39, which may be ++included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++COPYRIGHT NOTICE, DISCLAIMER, and LICENSE ++========================================= ++ ++PNG Reference Library License version 2 ++--------------------------------------- ++ ++Copyright (c) 1995-2022 The PNG Reference Library Authors. ++Copyright (c) 2018-2022 Cosmin Truta ++Copyright (c) 1998-2018 Glenn Randers-Pehrson ++Copyright (c) 1996-1997 Andreas Dilger ++Copyright (c) 1995-1996 Guy Eric Schalnat, Group 42, Inc. ++ ++The software is supplied "as is", without warranty of any kind, ++express or implied, including, without limitation, the warranties ++of merchantability, fitness for a particular purpose, title, and ++non-infringement. In no event shall the Copyright owners, or ++anyone distributing the software, be liable for any damages or ++other liability, whether in contract, tort or otherwise, arising ++from, out of, or in connection with the software, or the use or ++other dealings in the software, even if advised of the possibility ++of such damage. ++ ++Permission is hereby granted to use, copy, modify, and distribute ++this software, or portions hereof, for any purpose, without fee, ++subject to the following restrictions: ++ ++ 1. The origin of this software must not be misrepresented; you ++ must not claim that you wrote the original software. If you ++ use this software in a product, an acknowledgment in the product ++ documentation would be appreciated, but is not required. ++ ++ 2. Altered source versions must be plainly marked as such, and must ++ not be misrepresented as being the original software. ++ ++ 3. This Copyright notice may not be removed or altered from any ++ source or altered source distribution. ++ ++ ++PNG Reference Library License version 1 (for libpng 0.5 through 1.6.35) ++----------------------------------------------------------------------- ++ ++libpng versions 1.0.7, July 1, 2000, through 1.6.35, July 15, 2018 are ++Copyright (c) 2000-2002, 2004, 2006-2018 Glenn Randers-Pehrson, are ++derived from libpng-1.0.6, and are distributed according to the same ++disclaimer and license as libpng-1.0.6 with the following individuals ++added to the list of Contributing Authors: ++ ++ Simon-Pierre Cadieux ++ Eric S. Raymond ++ Mans Rullgard ++ Cosmin Truta ++ Gilles Vollant ++ James Yu ++ Mandar Sahastrabuddhe ++ Google Inc. ++ Vadim Barkov ++ ++and with the following additions to the disclaimer: ++ ++ There is no warranty against interference with your enjoyment of ++ the library or against infringement. There is no warranty that our ++ efforts or the library will fulfill any of your particular purposes ++ or needs. This library is provided with all faults, and the entire ++ risk of satisfactory quality, performance, accuracy, and effort is ++ with the user. ++ ++Some files in the "contrib" directory and some configure-generated ++files that are distributed with libpng have other copyright owners, and ++are released under other open source licenses. ++ ++libpng versions 0.97, January 1998, through 1.0.6, March 20, 2000, are ++Copyright (c) 1998-2000 Glenn Randers-Pehrson, are derived from ++libpng-0.96, and are distributed according to the same disclaimer and ++license as libpng-0.96, with the following individuals added to the ++list of Contributing Authors: ++ ++ Tom Lane ++ Glenn Randers-Pehrson ++ Willem van Schaik ++ ++libpng versions 0.89, June 1996, through 0.96, May 1997, are ++Copyright (c) 1996-1997 Andreas Dilger, are derived from libpng-0.88, ++and are distributed according to the same disclaimer and license as ++libpng-0.88, with the following individuals added to the list of ++Contributing Authors: ++ ++ John Bowler ++ Kevin Bracey ++ Sam Bushell ++ Magnus Holmgren ++ Greg Roelofs ++ Tom Tanner ++ ++Some files in the "scripts" directory have other copyright owners, ++but are released under this license. ++ ++libpng versions 0.5, May 1995, through 0.88, January 1996, are ++Copyright (c) 1995-1996 Guy Eric Schalnat, Group 42, Inc. ++ ++For the purposes of this copyright and license, "Contributing Authors" ++is defined as the following set of individuals: ++ ++ Andreas Dilger ++ Dave Martindale ++ Guy Eric Schalnat ++ Paul Schmidt ++ Tim Wegner ++ ++The PNG Reference Library is supplied "AS IS". The Contributing ++Authors and Group 42, Inc. disclaim all warranties, expressed or ++implied, including, without limitation, the warranties of ++merchantability and of fitness for any purpose. The Contributing ++Authors and Group 42, Inc. assume no liability for direct, indirect, ++incidental, special, exemplary, or consequential damages, which may ++result from the use of the PNG Reference Library, even if advised of ++the possibility of such damage. ++ ++Permission is hereby granted to use, copy, modify, and distribute this ++source code, or portions hereof, for any purpose, without fee, subject ++to the following restrictions: ++ ++ 1. The origin of this source code must not be misrepresented. ++ ++ 2. Altered versions must be plainly marked as such and must not ++ be misrepresented as being the original source. ++ ++ 3. This Copyright notice may not be removed or altered from any ++ source or altered source distribution. ++ ++The Contributing Authors and Group 42, Inc. specifically permit, ++without fee, and encourage the use of this source code as a component ++to supporting the PNG file format in commercial products. If you use ++this source code in a product, acknowledgment is not required but would ++be appreciated. ++ ++TRADEMARK: ++ ++The name "libpng" has not been registered by the Copyright owners ++as a trademark in any jurisdiction. However, because libpng has ++been distributed and maintained world-wide, continually since 1995, ++the Copyright owners claim "common-law trademark protection" in any ++jurisdiction where common-law trademark is recognized. ++ ++OSI CERTIFICATION: ++ ++Libpng is OSI Certified Open Source Software. OSI Certified Open Source is ++a certification mark of the Open Source Initiative. OSI has not addressed ++the additional disclaimers inserted at version 1.0.7. ++ ++EXPORT CONTROL: ++ ++The Copyright owner believes that the Export Control Classification ++Number (ECCN) for libpng is EAR99, which means not subject to export ++controls or International Traffic in Arms Regulations (ITAR) because ++it is open source, publicly available software, that does not contain ++any encryption software. See the EAR, paragraphs 734.3(b)(3) and ++734.7(b). ++ ++Glenn Randers-Pehrson ++glennrp at users.sourceforge.net ++July 15, 2018 ++ ++AUTHORS File Information: ++ ++PNG REFERENCE LIBRARY AUTHORS ++============================= ++ ++This is the list of PNG Reference Library ("libpng") Contributing ++Authors, for copyright and licensing purposes. ++ ++ * Andreas Dilger ++ * Cosmin Truta ++ * Dave Martindale ++ * Eric S. Raymond ++ * Gilles Vollant ++ * Glenn Randers-Pehrson ++ * Greg Roelofs ++ * Guy Eric Schalnat ++ * James Yu ++ * John Bowler ++ * Kevin Bracey ++ * Magnus Holmgren ++ * Mandar Sahastrabuddhe ++ * Mans Rullgard ++ * Matt Sarett ++ * Mike Klein ++ * Pascal Massimino ++ * Paul Schmidt ++ * Qiang Zhou ++ * Sam Bushell ++ * Samuel Williams ++ * Simon-Pierre Cadieux ++ * Tim Wegner ++ * Tom Lane ++ * Tom Tanner ++ * Vadim Barkov ++ * Willem van Schaik ++ * Zhijie Liang ++ * Arm Holdings ++ - Richard Townsend ++ * Google Inc. ++ - Dan Field ++ - Leon Scroggins III ++ - Matt Sarett ++ - Mike Klein ++ - Sami Boukortt ++ ++The build projects, the build scripts, the test scripts, and other ++files in the "ci", "projects", "scripts" and "tests" directories, have ++other copyright owners, but are released under the libpng license. ++ ++Some files in the "contrib" directory, and some tools-generated files ++that are distributed with libpng, have other copyright owners, and are ++released under other open source licenses. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to GIFLIB 5.2.1 & libungif 4.1.3, ++which may be included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++The GIFLIB distribution is Copyright (c) 1997 Eric S. Raymond ++ ++Permission is hereby granted, free of charge, to any person obtaining a copy ++of this software and associated documentation files (the "Software"), to deal ++in the Software without restriction, including without limitation the rights ++to use, copy, modify, merge, publish, distribute, sublicense, and/or sell ++copies of the Software, and to permit persons to whom the Software is ++furnished to do so, subject to the following conditions: ++ ++The above copyright notice and this permission notice shall be included in ++all copies or substantial portions of the Software. ++ ++THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE ++AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ++LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, ++OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN ++THE SOFTWARE. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Little CMS 2.11, which may be ++included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++Little CMS ++Copyright (c) 1998-2020 Marti Maria Saguer ++ ++Permission is hereby granted, free of charge, to any person obtaining a copy ++of this software and associated documentation files (the "Software"), to deal ++in the Software without restriction, including without limitation the rights ++to use, copy, modify, merge, publish, distribute, sublicense, and/or sell ++copies of the Software, and to permit persons to whom the Software is ++furnished to do so, subject to the following conditions: ++ ++The above copyright notice and this permission notice shall be included in all ++copies or substantial portions of the Software. ++ ++THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE ++AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ++LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, ++OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE ++SOFTWARE. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% Lucida is a registered trademark or trademark of Bigelow & Holmes in the ++U.S. and other countries. ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Mesa 3D Graphics Library v4.1, ++which may be included with JRE 8, JDK 8, and OpenJDK 8 source distributions. ++ ++--- begin of LICENSE --- ++ ++ Mesa 3-D Graphics Library v19.2.1 ++ ++ Copyright (C) 1999-2007 Brian Paul All Rights Reserved. ++ ++ Permission is hereby granted, free of charge, to any person obtaining a ++ copy of this software and associated documentation files (the "Software"), ++ to deal in the Software without restriction, including without limitation ++ the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ and/or sell copies of the Software, and to permit persons to whom the ++ Software is furnished to do so, subject to the following conditions: ++ ++ The above copyright notice and this permission notice shall be included ++ in all copies or substantial portions of the Software. ++ ++ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ++ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, ++ OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE ++ SOFTWARE. ++ ++Attention, Contributors ++ ++When contributing to the Mesa project you must agree to the licensing terms ++of the component to which you're contributing. ++The following section lists the primary components of the Mesa distribution ++and their respective licenses. ++Mesa Component Licenses ++ ++ ++ ++Component Location License ++------------------------------------------------------------------ ++Main Mesa code src/mesa/ MIT ++Device drivers src/mesa/drivers/* MIT, generally ++ ++Gallium code src/gallium/ MIT ++ ++Ext headers GL/glext.h Khronos ++ GL/glxext.h Khronos ++ GL/wglext.h Khronos ++ KHR/khrplatform.h Khronos ++ ++***************************************************************************** ++ ++---- ++include/GL/gl.h : ++ ++ ++ Mesa 3-D graphics library ++ ++ Copyright (C) 1999-2006 Brian Paul All Rights Reserved. ++ Copyright (C) 2009 VMware, Inc. All Rights Reserved. ++ ++ Permission is hereby granted, free of charge, to any person obtaining a ++ copy of this software and associated documentation files (the "Software"), ++ to deal in the Software without restriction, including without limitation ++ the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ and/or sell copies of the Software, and to permit persons to whom the ++ Software is furnished to do so, subject to the following conditions: ++ ++ The above copyright notice and this permission notice shall be included ++ in all copies or substantial portions of the Software. ++ ++ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ OTHER DEALINGS IN THE SOFTWARE. ++ ++ ***************************************************************************** ++ ++---- ++include/GL/glext.h ++include/GL/glxext.h ++include/GL/wglxext.h : ++ ++ ++ Copyright (c) 2013 - 2018 The Khronos Group Inc. ++ ++ Permission is hereby granted, free of charge, to any person obtaining a ++ copy of this software and/or associated documentation files (the ++ "Materials"), to deal in the Materials without restriction, including ++ without limitation the rights to use, copy, modify, merge, publish, ++ distribute, sublicense, and/or sell copies of the Materials, and to ++ permit persons to whom the Materials are furnished to do so, subject to ++ the following conditions: ++ ++ The above copyright notice and this permission notice shall be included ++ in all copies or substantial portions of the Materials. ++ ++ THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. ++ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY ++ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, ++ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE ++ MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS. ++ ++ ***************************************************************************** ++ ++---- ++include/KHR/khrplatform.h : ++ ++ Copyright (c) 2008 - 2018 The Khronos Group Inc. ++ ++ Permission is hereby granted, free of charge, to any person obtaining a ++ copy of this software and/or associated documentation files (the ++ "Materials"), to deal in the Materials without restriction, including ++ without limitation the rights to use, copy, modify, merge, publish, ++ distribute, sublicense, and/or sell copies of the Materials, and to ++ permit persons to whom the Materials are furnished to do so, subject to ++ the following conditions: ++ ++ The above copyright notice and this permission notice shall be included ++ in all copies or substantial portions of the Materials. ++ ++ THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. ++ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY ++ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, ++ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE ++ MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS. ++ ++ ***************************************************************************** ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Mozilla Network Security ++Services (NSS), which is supplied with the JDK test suite in the OpenJDK ++source code repository. It is licensed under Mozilla Public License (MPL), ++version 2.0. ++ ++The NSS libraries are supplied in executable form, built from unmodified ++NSS source code labeled with the "NSS_3_16_RTM" HG tag. ++ ++The NSS source code is available in the OpenJDK source code repository at: ++ jdk/test/sun/security/pkcs11/nss/src ++ ++The NSS libraries are available in the OpenJDK source code repository at: ++ jdk/test/sun/security/pkcs11/nss/lib ++ ++--- begin of LICENSE --- ++ ++Mozilla Public License Version 2.0 ++================================== ++ ++1. Definitions ++-------------- ++ ++1.1. "Contributor" ++ means each individual or legal entity that creates, contributes to ++ the creation of, or owns Covered Software. ++ ++1.2. "Contributor Version" ++ means the combination of the Contributions of others (if any) used ++ by a Contributor and that particular Contributor's Contribution. ++ ++1.3. "Contribution" ++ means Covered Software of a particular Contributor. ++ ++1.4. "Covered Software" ++ means Source Code Form to which the initial Contributor has attached ++ the notice in Exhibit A, the Executable Form of such Source Code ++ Form, and Modifications of such Source Code Form, in each case ++ including portions thereof. ++ ++1.5. "Incompatible With Secondary Licenses" ++ means ++ ++ (a) that the initial Contributor has attached the notice described ++ in Exhibit B to the Covered Software; or ++ ++ (b) that the Covered Software was made available under the terms of ++ version 1.1 or earlier of the License, but not also under the ++ terms of a Secondary License. ++ ++1.6. "Executable Form" ++ means any form of the work other than Source Code Form. ++ ++1.7. "Larger Work" ++ means a work that combines Covered Software with other material, in ++ a separate file or files, that is not Covered Software. ++ ++1.8. "License" ++ means this document. ++ ++1.9. "Licensable" ++ means having the right to grant, to the maximum extent possible, ++ whether at the time of the initial grant or subsequently, any and ++ all of the rights conveyed by this License. ++ ++1.10. "Modifications" ++ means any of the following: ++ ++ (a) any file in Source Code Form that results from an addition to, ++ deletion from, or modification of the contents of Covered ++ Software; or ++ ++ (b) any new file in Source Code Form that contains any Covered ++ Software. ++ ++1.11. "Patent Claims" of a Contributor ++ means any patent claim(s), including without limitation, method, ++ process, and apparatus claims, in any patent Licensable by such ++ Contributor that would be infringed, but for the grant of the ++ License, by the making, using, selling, offering for sale, having ++ made, import, or transfer of either its Contributions or its ++ Contributor Version. ++ ++1.12. "Secondary License" ++ means either the GNU General Public License, Version 2.0, the GNU ++ Lesser General Public License, Version 2.1, the GNU Affero General ++ Public License, Version 3.0, or any later versions of those ++ licenses. ++ ++1.13. "Source Code Form" ++ means the form of the work preferred for making modifications. ++ ++1.14. "You" (or "Your") ++ means an individual or a legal entity exercising rights under this ++ License. For legal entities, "You" includes any entity that ++ controls, is controlled by, or is under common control with You. For ++ purposes of this definition, "control" means (a) the power, direct ++ or indirect, to cause the direction or management of such entity, ++ whether by contract or otherwise, or (b) ownership of more than ++ fifty percent (50%) of the outstanding shares or beneficial ++ ownership of such entity. ++ ++2. License Grants and Conditions ++-------------------------------- ++ ++2.1. Grants ++ ++Each Contributor hereby grants You a world-wide, royalty-free, ++non-exclusive license: ++ ++(a) under intellectual property rights (other than patent or trademark) ++ Licensable by such Contributor to use, reproduce, make available, ++ modify, display, perform, distribute, and otherwise exploit its ++ Contributions, either on an unmodified basis, with Modifications, or ++ as part of a Larger Work; and ++ ++(b) under Patent Claims of such Contributor to make, use, sell, offer ++ for sale, have made, import, and otherwise transfer either its ++ Contributions or its Contributor Version. ++ ++2.2. Effective Date ++ ++The licenses granted in Section 2.1 with respect to any Contribution ++become effective for each Contribution on the date the Contributor first ++distributes such Contribution. ++ ++2.3. Limitations on Grant Scope ++ ++The licenses granted in this Section 2 are the only rights granted under ++this License. No additional rights or licenses will be implied from the ++distribution or licensing of Covered Software under this License. ++Notwithstanding Section 2.1(b) above, no patent license is granted by a ++Contributor: ++ ++(a) for any code that a Contributor has removed from Covered Software; ++ or ++ ++(b) for infringements caused by: (i) Your and any other third party's ++ modifications of Covered Software, or (ii) the combination of its ++ Contributions with other software (except as part of its Contributor ++ Version); or ++ ++(c) under Patent Claims infringed by Covered Software in the absence of ++ its Contributions. ++ ++This License does not grant any rights in the trademarks, service marks, ++or logos of any Contributor (except as may be necessary to comply with ++the notice requirements in Section 3.4). ++ ++2.4. Subsequent Licenses ++ ++No Contributor makes additional grants as a result of Your choice to ++distribute the Covered Software under a subsequent version of this ++License (see Section 10.2) or under the terms of a Secondary License (if ++permitted under the terms of Section 3.3). ++ ++2.5. Representation ++ ++Each Contributor represents that the Contributor believes its ++Contributions are its original creation(s) or it has sufficient rights ++to grant the rights to its Contributions conveyed by this License. ++ ++2.6. Fair Use ++ ++This License is not intended to limit any rights You have under ++applicable copyright doctrines of fair use, fair dealing, or other ++equivalents. ++ ++2.7. Conditions ++ ++Sections 3.1, 3.2, 3.3, and 3.4 are conditions of the licenses granted ++in Section 2.1. ++ ++3. Responsibilities ++------------------- ++ ++3.1. Distribution of Source Form ++ ++All distribution of Covered Software in Source Code Form, including any ++Modifications that You create or to which You contribute, must be under ++the terms of this License. You must inform recipients that the Source ++Code Form of the Covered Software is governed by the terms of this ++License, and how they can obtain a copy of this License. You may not ++attempt to alter or restrict the recipients' rights in the Source Code ++Form. ++ ++3.2. Distribution of Executable Form ++ ++If You distribute Covered Software in Executable Form then: ++ ++(a) such Covered Software must also be made available in Source Code ++ Form, as described in Section 3.1, and You must inform recipients of ++ the Executable Form how they can obtain a copy of such Source Code ++ Form by reasonable means in a timely manner, at a charge no more ++ than the cost of distribution to the recipient; and ++ ++(b) You may distribute such Executable Form under the terms of this ++ License, or sublicense it under different terms, provided that the ++ license for the Executable Form does not attempt to limit or alter ++ the recipients' rights in the Source Code Form under this License. ++ ++3.3. Distribution of a Larger Work ++ ++You may create and distribute a Larger Work under terms of Your choice, ++provided that You also comply with the requirements of this License for ++the Covered Software. If the Larger Work is a combination of Covered ++Software with a work governed by one or more Secondary Licenses, and the ++Covered Software is not Incompatible With Secondary Licenses, this ++License permits You to additionally distribute such Covered Software ++under the terms of such Secondary License(s), so that the recipient of ++the Larger Work may, at their option, further distribute the Covered ++Software under the terms of either this License or such Secondary ++License(s). ++ ++3.4. Notices ++ ++You may not remove or alter the substance of any license notices ++(including copyright notices, patent notices, disclaimers of warranty, ++or limitations of liability) contained within the Source Code Form of ++the Covered Software, except that You may alter any license notices to ++the extent required to remedy known factual inaccuracies. ++ ++3.5. Application of Additional Terms ++ ++You may choose to offer, and to charge a fee for, warranty, support, ++indemnity or liability obligations to one or more recipients of Covered ++Software. However, You may do so only on Your own behalf, and not on ++behalf of any Contributor. You must make it absolutely clear that any ++such warranty, support, indemnity, or liability obligation is offered by ++You alone, and You hereby agree to indemnify every Contributor for any ++liability incurred by such Contributor as a result of warranty, support, ++indemnity or liability terms You offer. You may include additional ++disclaimers of warranty and limitations of liability specific to any ++jurisdiction. ++ ++4. Inability to Comply Due to Statute or Regulation ++--------------------------------------------------- ++ ++If it is impossible for You to comply with any of the terms of this ++License with respect to some or all of the Covered Software due to ++statute, judicial order, or regulation then You must: (a) comply with ++the terms of this License to the maximum extent possible; and (b) ++describe the limitations and the code they affect. Such description must ++be placed in a text file included with all distributions of the Covered ++Software under this License. Except to the extent prohibited by statute ++or regulation, such description must be sufficiently detailed for a ++recipient of ordinary skill to be able to understand it. ++ ++5. Termination ++-------------- ++ ++5.1. The rights granted under this License will terminate automatically ++if You fail to comply with any of its terms. However, if You become ++compliant, then the rights granted under this License from a particular ++Contributor are reinstated (a) provisionally, unless and until such ++Contributor explicitly and finally terminates Your grants, and (b) on an ++ongoing basis, if such Contributor fails to notify You of the ++non-compliance by some reasonable means prior to 60 days after You have ++come back into compliance. Moreover, Your grants from a particular ++Contributor are reinstated on an ongoing basis if such Contributor ++notifies You of the non-compliance by some reasonable means, this is the ++first time You have received notice of non-compliance with this License ++from such Contributor, and You become compliant prior to 30 days after ++Your receipt of the notice. ++ ++5.2. If You initiate litigation against any entity by asserting a patent ++infringement claim (excluding declaratory judgment actions, ++counter-claims, and cross-claims) alleging that a Contributor Version ++directly or indirectly infringes any patent, then the rights granted to ++You by any and all Contributors for the Covered Software under Section ++2.1 of this License shall terminate. ++ ++5.3. In the event of termination under Sections 5.1 or 5.2 above, all ++end user license agreements (excluding distributors and resellers) which ++have been validly granted by You or Your distributors under this License ++prior to termination shall survive termination. ++ ++************************************************************************ ++* * ++* 6. Disclaimer of Warranty * ++* ------------------------- * ++* * ++* Covered Software is provided under this License on an "as is" * ++* basis, without warranty of any kind, either expressed, implied, or * ++* statutory, including, without limitation, warranties that the * ++* Covered Software is free of defects, merchantable, fit for a * ++* particular purpose or non-infringing. The entire risk as to the * ++* quality and performance of the Covered Software is with You. * ++* Should any Covered Software prove defective in any respect, You * ++* (not any Contributor) assume the cost of any necessary servicing, * ++* repair, or correction. This disclaimer of warranty constitutes an * ++* essential part of this License. No use of any Covered Software is * ++* authorized under this License except under this disclaimer. * ++* * ++************************************************************************ ++ ++************************************************************************ ++* * ++* 7. Limitation of Liability * ++* -------------------------- * ++* * ++* Under no circumstances and under no legal theory, whether tort * ++* (including negligence), contract, or otherwise, shall any * ++* Contributor, or anyone who distributes Covered Software as * ++* permitted above, be liable to You for any direct, indirect, * ++* special, incidental, or consequential damages of any character * ++* including, without limitation, damages for lost profits, loss of * ++* goodwill, work stoppage, computer failure or malfunction, or any * ++* and all other commercial damages or losses, even if such party * ++* shall have been informed of the possibility of such damages. This * ++* limitation of liability shall not apply to liability for death or * ++* personal injury resulting from such party's negligence to the * ++* extent applicable law prohibits such limitation. Some * ++* jurisdictions do not allow the exclusion or limitation of * ++* incidental or consequential damages, so this exclusion and * ++* limitation may not apply to You. * ++* * ++************************************************************************ ++ ++8. Litigation ++------------- ++ ++Any litigation relating to this License may be brought only in the ++courts of a jurisdiction where the defendant maintains its principal ++place of business and such litigation shall be governed by laws of that ++jurisdiction, without reference to its conflict-of-law provisions. ++Nothing in this Section shall prevent a party's ability to bring ++cross-claims or counter-claims. ++ ++9. Miscellaneous ++---------------- ++ ++This License represents the complete agreement concerning the subject ++matter hereof. If any provision of this License is held to be ++unenforceable, such provision shall be reformed only to the extent ++necessary to make it enforceable. Any law or regulation which provides ++that the language of a contract shall be construed against the drafter ++shall not be used to construe this License against a Contributor. ++ ++10. Versions of the License ++--------------------------- ++ ++10.1. New Versions ++ ++Mozilla Foundation is the license steward. Except as provided in Section ++10.3, no one other than the license steward has the right to modify or ++publish new versions of this License. Each version will be given a ++distinguishing version number. ++ ++10.2. Effect of New Versions ++ ++You may distribute the Covered Software under the terms of the version ++of the License under which You originally received the Covered Software, ++or under the terms of any subsequent version published by the license ++steward. ++ ++10.3. Modified Versions ++ ++If you create software not governed by this License, and you want to ++create a new license for such software, you may create and use a ++modified version of this License if you rename the license and remove ++any references to the name of the license steward (except to note that ++such modified license differs from this License). ++ ++10.4. Distributing Source Code Form that is Incompatible With Secondary ++Licenses ++ ++If You choose to distribute Source Code Form that is Incompatible With ++Secondary Licenses under the terms of this version of the License, the ++notice described in Exhibit B of this License must be attached. ++ ++Exhibit A - Source Code Form License Notice ++------------------------------------------- ++ ++ This Source Code Form is subject to the terms of the Mozilla Public ++ License, v. 2.0. If a copy of the MPL was not distributed with this ++ file, You can obtain one at http://mozilla.org/MPL/2.0/. ++ ++If it is not possible or desirable to put the notice in a particular ++file, then You may include the notice in a location (such as a LICENSE ++file in a relevant directory) where a recipient would be likely to look ++for such a notice. ++ ++You may add additional accurate notices of copyright ownership. ++ ++Exhibit B - "Incompatible With Secondary Licenses" Notice ++--------------------------------------------------------- ++ ++ This Source Code Form is "Incompatible With Secondary Licenses", as ++ defined by the Mozilla Public License, v. 2.0. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to PC/SC Lite v1.8.26, ++which may be included with JRE 8, JDK 8, and OpenJDK 8 on Linux and Solaris. ++ ++--- begin of LICENSE --- ++ ++Copyright (c) 1999-2003 David Corcoran ++Copyright (c) 2001-2011 Ludovic Rousseau ++All rights reserved. ++ ++Redistribution and use in source and binary forms, with or without ++modification, are permitted provided that the following conditions ++are met: ++ ++1. Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++2. Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++3. The name of the author may not be used to endorse or promote products ++ derived from this software without specific prior written permission. ++ ++Changes to this license can be made only by the copyright author with ++explicit written consent. ++ ++THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to PorterStemmer v4, which may be ++included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++See: http://tartarus.org/~martin/PorterStemmer ++ ++The software is completely free for any purpose, unless notes at the head of ++the program text indicates otherwise (which is rare). In any case, the notes ++about licensing are never more restrictive than the BSD License. ++ ++In every case where the software is not written by me (Martin Porter), this ++licensing arrangement has been endorsed by the contributor, and it is ++therefore unnecessary to ask the contributor again to confirm it. ++ ++I have not asked any contributors (or their employers, if they have them) for ++proofs that they have the right to distribute their software in this way. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Relax NG Object/Parser v.20050510, ++which may be included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++Copyright (c) Kohsuke Kawaguchi ++ ++Permission is hereby granted, free of charge, to any person obtaining a copy ++of this software and associated documentation files (the "Software"), to deal ++in the Software without restriction, including without limitation the rights ++to use, copy, modify, merge, publish, distribute, sublicense, and/or sell ++copies of the Software, and to permit persons to whom the Software is ++furnished to do so, subject to the following conditions: The above copyright ++notice and this permission notice shall be included in all copies or ++substantial portions of the Software. ++ ++THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE ++AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ++LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, ++OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE ++SOFTWARE. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to RelaxNGCC v1.12, which may be ++included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++Copyright (c) 2000-2003 Daisuke Okajima and Kohsuke Kawaguchi. ++All rights reserved. ++ ++Redistribution and use in source and binary forms, with or without ++modification, are permitted provided that the following conditions are met: ++ ++1. Redistributions of source code must retain the above copyright notice, this ++ list of conditions and the following disclaimer. ++ ++2. Redistributions in binary form must reproduce the above copyright notice, ++ this list of conditions and the following disclaimer in the documentation ++ and/or other materials provided with the distribution. ++ ++3. The end-user documentation included with the redistribution, if any, must ++ include the following acknowledgment: ++ ++ "This product includes software developed by Daisuke Okajima ++ and Kohsuke Kawaguchi (http://relaxngcc.sf.net/)." ++ ++Alternately, this acknowledgment may appear in the software itself, if and ++wherever such third-party acknowledgments normally appear. ++ ++4. The names of the copyright holders must not be used to endorse or promote ++ products derived from this software without prior written permission. For ++ written permission, please contact the copyright holders. ++ ++5. Products derived from this software may not be called "RELAXNGCC", nor may ++ "RELAXNGCC" appear in their name, without prior written permission of the ++ copyright holders. ++ ++THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESSED OR IMPLIED WARRANTIES, ++INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND ++FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.IN NO EVENT SHALL THE APACHE ++SOFTWARE FOUNDATION OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ++INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ++EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Relax NG Datatype 1.0, which ++may be included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++Copyright (c) 2005, 2010 Thai Open Source Software Center Ltd ++All rights reserved. ++ ++Redistribution and use in source and binary forms, with or without ++modification, are permitted provided that the following conditions are ++met: ++ ++ Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ Neither the names of the copyright holders nor the names of its ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR ++CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++--- end of LICENSE --- ++ ++-------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to SoftFloat version 2b, which may be ++included with JRE 8, JDK 8, and OpenJDK 8 on Linux/ARM. ++ ++--- begin of LICENSE --- ++ ++Use of any of this software is governed by the terms of the license below: ++ ++SoftFloat was written by me, John R. Hauser. This work was made possible in ++part by the International Computer Science Institute, located at Suite 600, ++1947 Center Street, Berkeley, California 94704. Funding was partially ++provided by the National Science Foundation under grant MIP-9311980. The ++original version of this code was written as part of a project to build ++a fixed-point vector processor in collaboration with the University of ++California at Berkeley, overseen by Profs. Nelson Morgan and John Wawrzynek. ++ ++THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort ++has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT ++TIMES RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO ++PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL ++LOSSES, COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO ++FURTHERMORE EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER ++SCIENCE INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES, ++COSTS, OR OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE ++SOFTWARE. ++ ++Derivative works are acceptable, even for commercial purposes, provided ++that the minimal documentation requirements stated in the source code are ++satisfied. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Sparkle 1.5, ++which may be included with JRE 8 on Mac OS X. ++ ++--- begin of LICENSE --- ++ ++Copyright (c) 2012 Sparkle.org and Andy Matuschak ++ ++Permission is hereby granted, free of charge, to any person obtaining a copy ++of this software and associated documentation files (the "Software"), to deal ++in the Software without restriction, including without limitation the rights ++to use, copy, modify, merge, publish, distribute, sublicense, and/or sell ++copies of the Software, and to permit persons to whom the Software is ++furnished to do so, subject to the following conditions: ++ ++The above copyright notice and this permission notice shall be included in all ++copies or substantial portions of the Software. ++ ++THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE ++AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ++LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, ++OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE ++SOFTWARE. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% Portions licensed from Taligent, Inc. ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Thai Dictionary, which may be ++included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++Copyright (C) 1982 The Royal Institute, Thai Royal Government. ++ ++Copyright (C) 1998 National Electronics and Computer Technology Center, ++National Science and Technology Development Agency, ++Ministry of Science Technology and Environment, ++Thai Royal Government. ++ ++Permission is hereby granted, free of charge, to any person obtaining a copy ++of this software and associated documentation files (the "Software"), to deal ++in the Software without restriction, including without limitation the rights ++to use, copy, modify, merge, publish, distribute, sublicense, and/or sell ++copies of the Software, and to permit persons to whom the Software is ++furnished to do so, subject to the following conditions: ++ ++The above copyright notice and this permission notice shall be included in all ++copies or substantial portions of the Software. ++ ++THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE ++AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ++LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, ++OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE ++SOFTWARE. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Unicode 6.2.0 & CLDR 21.0.1 ++which may be included with JRE 8, JDK 8, and OpenJDK 8. ++ ++--- begin of LICENSE --- ++ ++Unicode Terms of Use ++ ++For the general privacy policy governing access to this site, see the Unicode ++Privacy Policy. For trademark usage, see the Unicode?? Consortium Name and ++Trademark Usage Policy. ++ ++A. Unicode Copyright. ++ 1. Copyright ?? 1991-2013 Unicode, Inc. All rights reserved. ++ ++ 2. Certain documents and files on this website contain a legend indicating ++ that "Modification is permitted." Any person is hereby authorized, ++ without fee, to modify such documents and files to create derivative ++ works conforming to the Unicode?? Standard, subject to Terms and ++ Conditions herein. ++ ++ 3. Any person is hereby authorized, without fee, to view, use, reproduce, ++ and distribute all documents and files solely for informational ++ purposes in the creation of products supporting the Unicode Standard, ++ subject to the Terms and Conditions herein. ++ ++ 4. Further specifications of rights and restrictions pertaining to the use ++ of the particular set of data files known as the "Unicode Character ++ Database" can be found in Exhibit 1. ++ ++ 5. Each version of the Unicode Standard has further specifications of ++ rights and restrictions of use. For the book editions (Unicode 5.0 and ++ earlier), these are found on the back of the title page. The online ++ code charts carry specific restrictions. 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For Software, in accordance with FAR 12-212 or ++ DFARS 227-7202, as applicable, use, duplication or disclosure by the ++ Government is subject to the restrictions set forth in this Agreement. ++ ++C. Warranties and Disclaimers. ++ 1. This publication and/or website may include technical or typographical ++ errors or other inaccuracies . Changes are periodically added to the ++ information herein; these changes will be incorporated in new editions ++ of the publication and/or website. Unicode may make improvements and/or ++ changes in the product(s) and/or program(s) described in this ++ publication and/or website at any time. ++ ++ 2. If this file has been purchased on magnetic or optical media from ++ Unicode, Inc. the sole and exclusive remedy for any claim will be ++ exchange of the defective media within ninety (90) days of original ++ purchase. ++ ++ 3. EXCEPT AS PROVIDED IN SECTION C.2, THIS PUBLICATION AND/OR SOFTWARE IS ++ PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND EITHER EXPRESS, IMPLIED, ++ OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, ANY WARRANTIES OF ++ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. ++ UNICODE AND ITS LICENSORS ASSUME NO RESPONSIBILITY FOR ERRORS OR ++ OMISSIONS IN THIS PUBLICATION AND/OR SOFTWARE OR OTHER DOCUMENTS WHICH ++ ARE REFERENCED BY OR LINKED TO THIS PUBLICATION OR THE UNICODE WEBSITE. ++ ++D. Waiver of Damages. In no event shall Unicode or its licensors be liable for ++ any special, incidental, indirect or consequential damages of any kind, or ++ any damages whatsoever, whether or not Unicode was advised of the ++ possibility of the damage, including, without limitation, those resulting ++ from the following: loss of use, data or profits, in connection with the ++ use, modification or distribution of this information or its derivatives. ++ ++E.Trademarks & Logos. ++ 1. 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All third party trademarks referenced herein are ++the property of their respective owners. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to UPX v3.01, which may be included ++with JRE 8 on Windows. ++ ++--- begin of LICENSE --- ++ ++Use of any of this software is governed by the terms of the license below: ++ ++ ++ ooooo ooo ooooooooo. ooooooo ooooo ++ `888' `8' `888 `Y88. `8888 d8' ++ 888 8 888 .d88' Y888..8P ++ 888 8 888ooo88P' `8888' ++ 888 8 888 .8PY888. ++ `88. .8' 888 d8' `888b ++ `YbodP' o888o o888o o88888o ++ ++ ++ The Ultimate Packer for eXecutables ++ Copyright (c) 1996-2000 Markus Oberhumer & Laszlo Molnar ++ http://wildsau.idv.uni-linz.ac.at/mfx/upx.html ++ http://www.nexus.hu/upx ++ http://upx.tsx.org ++ ++ ++PLEASE CAREFULLY READ THIS LICENSE AGREEMENT, ESPECIALLY IF YOU PLAN ++TO MODIFY THE UPX SOURCE CODE OR USE A MODIFIED UPX VERSION. ++ ++ ++ABSTRACT ++======== ++ ++ UPX and UCL are copyrighted software distributed under the terms ++ of the GNU General Public License (hereinafter the "GPL"). ++ ++ The stub which is imbedded in each UPX compressed program is part ++ of UPX and UCL, and contains code that is under our copyright. The ++ terms of the GNU General Public License still apply as compressing ++ a program is a special form of linking with our stub. ++ ++ As a special exception we grant the free usage of UPX for all ++ executables, including commercial programs. ++ See below for details and restrictions. ++ ++ ++COPYRIGHT ++========= ++ ++ UPX and UCL are copyrighted software. All rights remain with the authors. ++ ++ UPX is Copyright (C) 1996-2000 Markus Franz Xaver Johannes Oberhumer ++ UPX is Copyright (C) 1996-2000 Laszlo Molnar ++ ++ UCL is Copyright (C) 1996-2000 Markus Franz Xaver Johannes Oberhumer ++ ++ ++GNU GENERAL PUBLIC LICENSE ++========================== ++ ++ UPX and the UCL library are free software; you can redistribute them ++ and/or modify them under the terms of the GNU General Public License as ++ published by the Free Software Foundation; either version 2 of ++ the License, or (at your option) any later version. ++ ++ UPX and UCL are distributed in the hope that they will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ GNU General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with this program; see the file COPYING. ++ ++ ++SPECIAL EXCEPTION FOR COMPRESSED EXECUTABLES ++============================================ ++ ++ The stub which is imbedded in each UPX compressed program is part ++ of UPX and UCL, and contains code that is under our copyright. The ++ terms of the GNU General Public License still apply as compressing ++ a program is a special form of linking with our stub. ++ ++ Hereby Markus F.X.J. Oberhumer and Laszlo Molnar grant you special ++ permission to freely use and distribute all UPX compressed programs ++ (including commercial ones), subject to the following restrictions: ++ ++ 1. You must compress your program with a completely unmodified UPX ++ version; either with our precompiled version, or (at your option) ++ with a self compiled version of the unmodified UPX sources as ++ distributed by us. ++ 2. This also implies that the UPX stub must be completely unmodfied, i.e. ++ the stub imbedded in your compressed program must be byte-identical ++ to the stub that is produced by the official unmodified UPX version. ++ 3. The decompressor and any other code from the stub must exclusively get ++ used by the unmodified UPX stub for decompressing your program at ++ program startup. No portion of the stub may get read, copied, ++ called or otherwise get used or accessed by your program. ++ ++ ++ANNOTATIONS ++=========== ++ ++ - You can use a modified UPX version or modified UPX stub only for ++ programs that are compatible with the GNU General Public License. ++ ++ - We grant you special permission to freely use and distribute all UPX ++ compressed programs. But any modification of the UPX stub (such as, ++ but not limited to, removing our copyright string or making your ++ program non-decompressible) will immediately revoke your right to ++ use and distribute a UPX compressed program. ++ ++ - UPX is not a software protection tool; by requiring that you use ++ the unmodified UPX version for your proprietary programs we ++ make sure that any user can decompress your program. This protects ++ both you and your users as nobody can hide malicious code - ++ any program that cannot be decompressed is highly suspicious ++ by definition. ++ ++ - You can integrate all or part of UPX and UCL into projects that ++ are compatible with the GNU GPL, but obviously you cannot grant ++ any special exceptions beyond the GPL for our code in your project. ++ ++ - We want to actively support manufacturers of virus scanners and ++ similar security software. Please contact us if you would like to ++ incorporate parts of UPX or UCL into such a product. ++ ++ ++ ++Markus F.X.J. Oberhumer Laszlo Molnar ++markus.oberhumer@jk.uni-linz.ac.at ml1050@cdata.tvnet.hu ++ ++Linz, Austria, 25 Feb 2000 ++ ++Additional License(s) ++ ++The UPX license file is at http://upx.sourceforge.net/upx-license.html. ++ ++--- end of LICENSE --- ++ ++------------------------------------------------------------------------------- ++ ++%% This notice is provided with respect to Xfree86-VidMode Extension 1.0, ++which may be included with JRE 8, JDK 8, and OpenJDK 8 on Linux and Solaris. ++ ++--- begin of LICENSE --- ++ ++Version 1.1 of XFree86 ProjectLicence. ++ ++Copyright (C) 1994-2004 The XFree86 Project, Inc. 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++#gitnum=`git log| head -n 1 |cut -b 8-15` ++#bdate=`date +%Y-%m-%d` ++#topdir=`pwd` ++#buildtag=`echo $USER`.`basename $topdir`.$bdate.$gitnum.$patch ++#patch=SP.4 ++buildtag=sw1.3.1 ++updatever=442 ++level=${1?usage: $0 release/slowdebug} ++#set user-release-suffix and update-version by version_patch.sh ++#bash version_patch.sh ++# $1: debug level (release, fastdebug, slowdebug) ++ bash configure \ ++ --with-user-release-suffix=$buildtag \ ++ --with-update-version=$updatever \ ++ --disable-zip-debug-info \ ++ --with-debug-level=$level \ ++ --disable-ccache \ ++ --enable-hotspot-test-in-build \ ++ --with-milestone=fcs \ ++ --with-build-number=b06 +diff --git a/test/ProblemList.jtx b/test/ProblemList.jtx +new file mode 100644 +index 0000000000..e3c5750e85 +--- /dev/null ++++ b/test/ProblemList.jtx +@@ -0,0 +1,2152 @@ ++##SW not support yet ++compiler/arguments/TestUseCountLeadingZerosInstructionOnUnsupportedCPU.java ++compiler/arguments/TestUseCountTrailingZerosInstructionOnUnsupportedCPU.java ++compiler/c2/cr6340864/TestByteVect.java ++compiler/c2/cr6340864/TestDoubleVect.java ++compiler/c2/cr6340864/TestFloatVect.java ++compiler/c2/cr6340864/TestIntVect.java ++compiler/c2/cr6340864/TestLongVect.java ++compiler/c2/cr6340864/TestShortVect.java ++compiler/codegen/TestCharVect2.java ++compiler/tiered/Level2RecompilationTest.java ++ ++# jdk_X11_error ++com/sun/awt/SecurityWarning/GetSizeShouldNotReturnZero.java ++com/sun/awt/Translucency/WindowOpacity.java ++com/sun/java/swing/plaf/gtk/4928019/bug4928019.java ++com/sun/java/swing/plaf/gtk/Test6635110.java ++com/sun/java/swing/plaf/gtk/Test6963870.java ++com/sun/java/swing/plaf/windows/8016551/bug8016551.java ++com/sun/java/swing/plaf/windows/Test6824600.java ++com/sun/java/swing/plaf/windows/WindowsRadioButtonUI/7089914/bug7089914.java ++java/awt/AlphaComposite/HeadlessAlphaComposite.java ++java/awt/AlphaComposite/TestAlphaCompositeForNaN.java ++java/awt/applet/Applet/HeadlessApplet.java ++java/awt/appletviewer/IOExceptionIfEncodedURLTest/IOExceptionIfEncodedURLTest.sh ++java/awt/BasicStroke/DashOffset.java ++java/awt/BasicStroke/DashScaleMinWidth.java ++java/awt/BasicStroke/DashStrokeTest.java ++java/awt/BasicStroke/DashZeroWidth.java ++java/awt/Checkbox/SetStateExcessEvent/SetStateExcessEvent.java ++java/awt/Choice/ChoiceKeyEventReaction/ChoiceKeyEventReaction.html ++java/awt/Choice/ChoiceLocationTest/ChoiceLocationTest.java ++java/awt/Choice/ChoiceMouseWheelTest/ChoiceMouseWheelTest.java ++java/awt/Choice/DragMouseOutAndRelease/DragMouseOutAndRelease.java ++java/awt/Choice/GetSizeTest/GetSizeTest.java ++java/awt/Choice/GrabLockTest/GrabLockTest.java ++java/awt/Choice/ItemStateChangeTest/ItemStateChangeTest.java ++java/awt/Choice/PopdownGeneratesMouseEvents/PopdownGeneratesMouseEvents.html ++java/awt/Choice/PopupPosTest/PopupPosTest.html ++java/awt/Choice/RemoveAllShrinkTest/RemoveAllShrinkTest.java ++java/awt/Choice/ResizeAutoClosesChoice/ResizeAutoClosesChoice.java ++java/awt/Choice/SelectCurrentItemTest/SelectCurrentItemTest.html ++java/awt/Choice/UnfocusableCB_ERR/UnfocusableCB_ERR.java ++java/awt/Choice/UnfocusableToplevel/UnfocusableToplevel.java ++java/awt/Color/HeadlessColor.java ++java/awt/Color/OpacityChange/OpacityChange.java ++java/awt/Component/7097771/bug7097771.java ++java/awt/Component/CompEventOnHiddenComponent/CompEventOnHiddenComponent.java ++java/awt/Component/DimensionEncapsulation/DimensionEncapsulation.java ++java/awt/Component/F10TopToplevel/F10TopToplevel.html ++java/awt/Component/Headless/HeadlessButton.java ++java/awt/Component/Headless/HeadlessCanvas.java ++java/awt/Component/Headless/HeadlessCheckbox.java ++java/awt/Component/Headless/HeadlessChoice.java ++java/awt/Component/Headless/HeadlessComponent.java ++java/awt/Component/Headless/HeadlessContainer.java ++java/awt/Component/Headless/HeadlessDialog.java ++java/awt/Component/Headless/HeadlessFileDialog.java ++java/awt/Component/Headless/HeadlessFrame.java ++java/awt/Component/Headless/HeadlessLabel.java ++java/awt/Component/Headless/HeadlessList.java ++java/awt/Component/Headless/HeadlessPanel.java ++java/awt/Component/Headless/HeadlessScrollbar.java ++java/awt/Component/Headless/HeadlessScrollPane.java ++java/awt/Component/Headless/HeadlessTextArea.java ++java/awt/Component/Headless/HeadlessTextField.java ++java/awt/Component/Headless/HeadlessWindow.java ++java/awt/Component/InsetsEncapsulation/InsetsEncapsulation.java ++java/awt/Component/isLightweightCrash/IsLightweightCrash.java ++java/awt/Component/NativeInLightShow/NativeInLightShow.java ++java/awt/Component/NoUpdateUponShow/NoUpdateUponShow.java ++java/awt/ComponentOrientation/BasicTest.java ++java/awt/ComponentOrientation/BorderTest.java ++java/awt/ComponentOrientation/FlowTest.java ++java/awt/ComponentOrientation/WindowTest.java ++java/awt/Component/PaintAll/PaintAll.java ++java/awt/Component/PrintAllXcheckJNI/PrintAllXcheckJNI.java ++java/awt/Component/Revalidate/Revalidate.java ++java/awt/Component/SetEnabledPerformance/SetEnabledPerformance.java ++java/awt/Component/TreeLockDeadlock/TreeLockDeadlock.java ++java/awt/Container/CheckZOrderChange/CheckZOrderChange.java ++java/awt/Container/ContainerAIOOBE/ContainerAIOOBE.java ++java/awt/Container/isRemoveNotifyNeeded/JInternalFrameTest.java ++java/awt/Container/MoveToOtherScreenTest/MoveToOtherScreenTest.java ++java/awt/Container/ValidateRoot/InvalidateMustRespectValidateRoots.java ++java/awt/Cursor/HeadlessCursor.java ++java/awt/Cursor/PredefinedPrivate/PredefinedPrivate.java ++java/awt/datatransfer/Clipboard/BasicClipboardTest.java ++java/awt/datatransfer/Clipboard/GetContentsInterruptedTest.java ++java/awt/datatransfer/ClipboardInterVMTest/ClipboardInterVMTest.java ++java/awt/datatransfer/CustomClassLoaderTransferTest/CustomClassLoaderTransferTest.java ++java/awt/datatransfer/DataFlavor/DataFlavorCloneTest/DataFlavorCloneTest.java ++java/awt/datatransfer/DataFlavor/DataFlavorEqualsNullTest.java ++java/awt/datatransfer/DataFlavor/DataFlavorEqualsTest.java ++java/awt/datatransfer/DataFlavor/DataFlavorFileListTest.java ++java/awt/datatransfer/DataFlavor/DataFlavorSerializedTest.java ++java/awt/datatransfer/DataFlavor/DefaultMatchTest.java ++java/awt/datatransfer/DataFlavor/EqualHashCodeTest.java ++java/awt/datatransfer/DataFlavor/EqualsHashCodeSymmetryTest/EqualsHashCodeSymmetryTest.java ++java/awt/datatransfer/DataFlavor/ExternalizeTest.java ++java/awt/datatransfer/DataFlavor/GetReaderForTextIAEForStringSelectionTest.java ++java/awt/datatransfer/DataFlavor/GetReaderForTextNPETest.java ++java/awt/datatransfer/DataFlavor/MimeTypeSerializationTest.java ++java/awt/datatransfer/DataFlavor/NoClassParameterTest.java ++java/awt/datatransfer/DataFlavor/NormalizeMimeTypeParameter.java ++java/awt/datatransfer/DataFlavor/NullDataFlavorTest.java ++java/awt/datatransfer/DataFlavor/ReaderForUnicodeText.java ++java/awt/datatransfer/DataFlavor/SelectBestFlavorNPETest.java ++java/awt/datatransfer/DataFlavor/SelectBestTextFlavorBadArrayTest.java ++java/awt/datatransfer/DataFlavor/ToStringNullPointerTest.java ++java/awt/datatransfer/DragImage/MultiResolutionDragImageTest.java ++java/awt/datatransfer/DragUnicodeBetweenJVMTest/DragUnicodeBetweenJVMTest.html ++java/awt/datatransfer/Headless/HeadlessClipboard.java ++java/awt/datatransfer/Headless/HeadlessDataFlavor.java ++java/awt/datatransfer/Headless/HeadlessSystemFlavorMap.java ++java/awt/datatransfer/HTMLDataFlavors/HTMLDataFlavorTest.java ++java/awt/datatransfer/ImageTransfer/ImageTransferTest.java ++java/awt/datatransfer/Independence/IndependenceAWTTest.java ++java/awt/datatransfer/Independence/IndependenceSwingTest.java ++java/awt/datatransfer/MissedHtmlAndRtfBug/MissedHtmlAndRtfBug.html ++java/awt/datatransfer/SystemFlavorMap/AddFlavorForNativeTest.java ++java/awt/datatransfer/SystemFlavorMap/AddFlavorTest.java ++java/awt/datatransfer/SystemFlavorMap/AddNativeForFlavorTest.java ++java/awt/datatransfer/SystemFlavorMap/AddNativeTest.java ++java/awt/datatransfer/SystemFlavorMap/DuplicatedNativesTest.java ++java/awt/datatransfer/SystemFlavorMap/DuplicateMappingTest.java ++java/awt/datatransfer/SystemFlavorMap/GetFlavorsForNewNativeTest.java ++java/awt/datatransfer/SystemFlavorMap/GetNativesForFlavorTest.java ++java/awt/datatransfer/SystemFlavorMap/GetNativesForNewFlavorTest.java ++java/awt/datatransfer/SystemFlavorMap/InvalidMapArgumentsTest.java ++java/awt/datatransfer/SystemFlavorMap/ManyFlavorMapTest.java ++java/awt/datatransfer/SystemFlavorMap/MappingGenerationTest.java ++java/awt/datatransfer/SystemFlavorMap/SetDataFlavorsTest.java ++java/awt/datatransfer/SystemFlavorMap/SetFlavorsForNativeTest.java ++java/awt/datatransfer/SystemFlavorMap/SetNativesForFlavor.java ++java/awt/datatransfer/SystemFlavorMap/SetNativesForFlavorTest.java ++java/awt/datatransfer/SystemFlavorMap/SetNativesTest.java ++java/awt/datatransfer/SystemSelection/SystemSelectionAWTTest.java ++java/awt/datatransfer/SystemSelection/SystemSelectionSwingTest.java ++java/awt/Desktop/8064934/bug8064934.java ++java/awt/Desktop/DesktopGtkLoadTest/DesktopGtkLoadTest.java ++java/awt/Desktop/OpenByUNCPathNameTest/OpenByUNCPathNameTest.java ++java/awt/Dialog/CloseDialog/CloseDialogTest.java ++java/awt/Dialog/CrashXCheckJni/CrashXCheckJni.java ++java/awt/Dialog/DialogAboveFrame/DialogAboveFrameTest.java ++java/awt/Dialog/DialogOverflowSizeTest/DialogSizeOverflowTest.java ++java/awt/Dialog/MakeWindowAlwaysOnTop/MakeWindowAlwaysOnTop.java ++java/awt/Dialog/ModalDialogPermission/ModalDialogPermission.java ++java/awt/Dialog/NonResizableDialogSysMenuResize/NonResizableDialogSysMenuResize.java ++java/awt/Dialog/ValidateOnShow/ValidateOnShow.java ++java/awt/dnd/AcceptDropMultipleTimes/AcceptDropMultipleTimes.java ++java/awt/dnd/BadSerializationTest/BadSerializationTest.java ++java/awt/dnd/Button2DragTest/Button2DragTest.html ++java/awt/dnd/DisposeFrameOnDragCrash/DisposeFrameOnDragTest.java ++java/awt/dnd/DragInterceptorAppletTest/DragInterceptorAppletTest.html ++java/awt/dnd/DragSourceListenerSerializationTest/DragSourceListenerSerializationTest.java ++java/awt/dnd/DropTargetEnterExitTest/ExtraDragEnterTest.java ++java/awt/dnd/DropTargetEnterExitTest/MissedDragExitTest.java ++java/awt/dnd/FileListBetweenJVMsTest/FileListBetweenJVMsTest.html ++java/awt/dnd/ImageDecoratedDnDInOut/ImageDecoratedDnDInOut.html ++java/awt/dnd/ImageDecoratedDnDNegative/ImageDecoratedDnDNegative.html ++java/awt/dnd/ImageTransferTest/ImageTransferTest.java ++java/awt/dnd/InterJVMGetDropSuccessTest/InterJVMGetDropSuccessTest.html ++java/awt/dnd/MissingDragExitEventTest/MissingDragExitEventTest.java ++java/awt/dnd/MissingEventsOnModalDialog/MissingEventsOnModalDialogTest.java ++java/awt/dnd/NoFormatsCrashTest/NoFormatsCrashTest.html ++java/awt/dnd/URIListBetweenJVMsTest/URIListBetweenJVMsTest.html ++java/awt/dnd/URIListToFileListBetweenJVMsTest/URIListToFileListBetweenJVMsTest.html ++java/awt/EmbeddedFrame/GraphicsConfigTest/GraphicsConfigTest.java ++java/awt/event/ComponentEvent/MovedResizedTardyEventTest/MovedResizedTardyEventTest.html ++java/awt/EventDispatchThread/EDTShutdownTest/EDTShutdownTest.java ++java/awt/EventDispatchThread/HandleExceptionOnEDT/HandleExceptionOnEDT.java ++java/awt/EventDispatchThread/LoopRobustness/LoopRobustness.html ++java/awt/EventDispatchThread/PreserveDispathThread/PreserveDispatchThread.java ++java/awt/event/HierarchyEvent/AncestorResized/AncestorResized.java ++java/awt/event/InputEvent/ButtonArraysEquality/ButtonArraysEquality.java ++java/awt/event/InputEvent/EventWhenTest/EventWhenTest.java ++java/awt/event/InvocationEvent/InvocationEventTest.java ++java/awt/event/KeyEvent/8020209/bug8020209.java ++java/awt/event/KeyEvent/AltCharAcceleratorTest/AltCharAcceleratorTest.java ++java/awt/event/KeyEvent/CorrectTime/CorrectTime.java ++java/awt/event/KeyEvent/DeadKey/DeadKeyMacOSXInputText.java ++java/awt/event/KeyEvent/DeadKey/deadKeyMacOSX.java ++java/awt/event/KeyEvent/DeadKey/DeadKeySystemAssertionDialog.java ++java/awt/event/KeyEvent/ExtendedKeyCode/ExtendedKeyCodeTest.java ++java/awt/event/KeyEvent/ExtendedModifiersTest/ExtendedModifiersTest.java ++java/awt/event/KeyEvent/KeyChar/KeyCharTest.java ++java/awt/event/KeyEvent/KeyMaskTest/KeyMaskTest.java ++java/awt/event/KeyEvent/KeyTyped/CtrlASCII.html ++java/awt/event/KeyEvent/SwallowKeyEvents/SwallowKeyEvents.java ++java/awt/event/MouseEvent/AcceptExtraButton/AcceptExtraButton.java ++java/awt/event/MouseEvent/CheckGetMaskForButton/CheckGetMaskForButton.java ++java/awt/event/MouseEvent/ClickDuringKeypress/ClickDuringKeypress.java ++java/awt/event/MouseEvent/DisabledComponents/DisabledComponentsTest.java ++java/awt/event/MouseEvent/EnterAsGrabbedEvent/EnterAsGrabbedEvent.java ++java/awt/event/MouseEvent/EventTimeInFuture/EventTimeInFuture.java ++java/awt/event/MouseEvent/FrameMouseEventAbsoluteCoordsTest/FrameMouseEventAbsoluteCoordsTest.html ++java/awt/event/MouseEvent/MenuDragMouseEventAbsoluteCoordsTest/MenuDragMouseEventAbsoluteCoordsTest.html ++java/awt/event/MouseEvent/MouseButtonsAndKeyMasksTest/MouseButtonsAndKeyMasksTest.java ++java/awt/event/MouseEvent/MouseButtonsTest/MouseButtonsTest.java ++java/awt/event/MouseEvent/MouseClickTest/MouseClickTest.html ++java/awt/event/MouseEvent/MouseWheelEventAbsoluteCoordsTest/MouseWheelEventAbsoluteCoordsTest.html ++java/awt/event/MouseEvent/MultipleMouseButtonsTest/MultipleMouseButtonsTest.java ++java/awt/event/MouseEvent/RobotLWTest/RobotLWTest.html ++java/awt/event/MouseEvent/SpuriousExitEnter/SpuriousExitEnter_3.java ++java/awt/event/MouseWheelEvent/DisabledComponent/DisabledComponent.java ++java/awt/event/MouseWheelEvent/InfiniteRecursion/InfiniteRecursion_1.java ++java/awt/event/MouseWheelEvent/InfiniteRecursion/InfiniteRecursion_2.html ++java/awt/event/MouseWheelEvent/InfiniteRecursion/InfiniteRecursion_3.html ++java/awt/event/MouseWheelEvent/InfiniteRecursion/InfiniteRecursion_4.java ++java/awt/event/MouseWheelEvent/InfiniteRecursion/InfiniteRecursion.java ++java/awt/event/MouseWheelEvent/WheelModifier/MouseWheelOnBackgroundComponent.java ++java/awt/event/MouseWheelEvent/WheelModifier/WheelModifier.java ++java/awt/event/OtherEvents/UngrabID/UngrabID.java ++java/awt/EventQueue/6638195/bug6638195.java ++java/awt/EventQueue/6980209/bug6980209.java ++java/awt/EventQueue/HeadlessEventQueue.java ++java/awt/EventQueue/InvocationEventTest/InvocationEventTest.java ++java/awt/EventQueue/MainAppContext/MainAppContext.java ++java/awt/EventQueue/NonComponentSourcePost.java ++java/awt/EventQueue/PostEventOrderingTest/PostEventOrderingTest.java ++java/awt/EventQueue/PushPopDeadlock2/PushPopTest.java ++java/awt/EventQueue/SecondaryLoopTest/SecondaryLoopTest.java ++java/awt/event/SequencedEvent/MultipleContextsFunctionalTest.java ++java/awt/event/SequencedEvent/MultipleContextsUnitTest.java ++java/awt/event/TextEvent/TextEventSequenceTest/TextEventSequenceTest.java ++java/awt/FileDialog/FilenameFilterTest/FilenameFilterTest.html ++java/awt/FileDialog/ISCthrownByFileListTest/ISCthrownByFileListTest.java ++java/awt/Focus/6378278/InputVerifierTest.java ++java/awt/Focus/6382144/EndlessLoopTest.java ++java/awt/Focus/6401036/InputVerifierTest2.java ++java/awt/Focus/6981400/Test1.java ++java/awt/Focus/6981400/Test2.java ++java/awt/Focus/6981400/Test3.java ++java/awt/Focus/8013611/JDK8013611.java ++java/awt/Focus/8073453/AWTFocusTransitionTest.java ++java/awt/Focus/8073453/SwingFocusTransitionTest.java ++java/awt/Focus/ActualFocusedWindowTest/ActualFocusedWindowBlockingTest.java ++java/awt/Focus/ActualFocusedWindowTest/ActualFocusedWindowRetaining.java ++java/awt/Focus/AppletInitialFocusTest/AppletInitialFocusTest1.html ++java/awt/Focus/AppletInitialFocusTest/AppletInitialFocusTest.html ++java/awt/Focus/AutoRequestFocusTest/AutoRequestFocusSetVisibleTest.java ++java/awt/Focus/AutoRequestFocusTest/AutoRequestFocusToFrontTest.java ++java/awt/Focus/ChildWindowFocusTest/ChildWindowFocusTest.html ++java/awt/Focus/ChoiceFocus/ChoiceFocus.java ++java/awt/Focus/ClearGlobalFocusOwnerTest/ClearGlobalFocusOwnerTest.java ++java/awt/Focus/ClearLwQueueBreakTest/ClearLwQueueBreakTest.java ++java/awt/Focus/CloseDialogActivateOwnerTest/CloseDialogActivateOwnerTest.java ++java/awt/Focus/ConsumeNextKeyTypedOnModalShowTest/ConsumeNextKeyTypedOnModalShowTest.java ++java/awt/Focus/ContainerFocusAutoTransferTest/ContainerFocusAutoTransferTest.java ++java/awt/Focus/DeiconifiedFrameLoosesFocus/DeiconifiedFrameLoosesFocus.html ++java/awt/Focus/DisposedWindow/DisposeDialogNotActivateOwnerTest/DisposeDialogNotActivateOwnerTest.html ++java/awt/Focus/FocusEmbeddedFrameTest/FocusEmbeddedFrameTest.java ++java/awt/Focus/FocusOwnerFrameOnClick/FocusOwnerFrameOnClick.java ++java/awt/Focus/FocusSubRequestTest/FocusSubRequestTest.html ++java/awt/Focus/FocusTransitionTest/FocusTransitionTest.java ++java/awt/Focus/FocusTraversalPolicy/DefaultFTPTest.java ++java/awt/Focus/FocusTraversalPolicy/InitialFTP.java ++java/awt/Focus/FocusTraversalPolicy/LayoutFTPTest.java ++java/awt/Focus/FrameJumpingToMouse/FrameJumpingToMouse.java ++java/awt/Focus/FrameMinimizeTest/FrameMinimizeTest.java ++java/awt/Focus/Headless/HeadlessContainerOrderFocusTraversalPolicy.java ++java/awt/Focus/Headless/HeadlessDefaultFocusTraversalPolicy.java ++java/awt/Focus/Headless/HeadlessDefaultKeyboardFocusManager.java ++java/awt/Focus/IconifiedFrameFocusChangeTest/IconifiedFrameFocusChangeTest.java ++java/awt/Focus/InputVerifierTest3/InputVerifierTest3.java ++java/awt/Focus/KeyEventForBadFocusOwnerTest/KeyEventForBadFocusOwnerTest.java ++java/awt/Focus/ModalBlockedStealsFocusTest/ModalBlockedStealsFocusTest.html ++java/awt/Focus/ModalDialogActivationTest/ModalDialogActivationTest.java ++java/awt/Focus/ModalDialogInitialFocusTest/ModalDialogInitialFocusTest.html ++java/awt/Focus/ModalExcludedWindowClickTest/ModalExcludedWindowClickTest.html ++java/awt/Focus/MouseClickRequestFocusRaceTest/MouseClickRequestFocusRaceTest.html ++java/awt/Focus/NoAutotransferToDisabledCompTest/NoAutotransferToDisabledCompTest.java ++java/awt/Focus/NonFocusableBlockedOwnerTest/NonFocusableBlockedOwnerTest.html ++java/awt/Focus/NonFocusableResizableTooSmall/NonFocusableResizableTooSmall.java ++java/awt/Focus/NonFocusableWindowTest/NoEventsTest.java ++java/awt/Focus/NonFocusableWindowTest/NonfocusableOwnerTest.java ++java/awt/Focus/NullActiveWindowOnFocusLost/NullActiveWindowOnFocusLost.java ++java/awt/Focus/OwnedWindowFocusIMECrashTest/OwnedWindowFocusIMECrashTest.java ++java/awt/Focus/RemoveAfterRequest/RemoveAfterRequest.java ++java/awt/Focus/RequestFocusAndHideTest/RequestFocusAndHideTest.java ++java/awt/Focus/RequestFocusToDisabledCompTest/RequestFocusToDisabledCompTest.java ++java/awt/Focus/RequestOnCompWithNullParent/RequestOnCompWithNullParent1.java ++java/awt/Focus/ResetMostRecentFocusOwnerTest/ResetMostRecentFocusOwnerTest.java ++java/awt/Focus/RestoreFocusOnDisabledComponentTest/RestoreFocusOnDisabledComponentTest.java ++java/awt/Focus/RollbackFocusFromAnotherWindowTest/RollbackFocusFromAnotherWindowTest.java ++java/awt/Focus/ShowFrameCheckForegroundTest/ShowFrameCheckForegroundTest.java ++java/awt/Focus/SimpleWindowActivationTest/SimpleWindowActivationTest.java ++java/awt/Focus/SortingFPT/JDK8048887.java ++java/awt/Focus/ToFrontFocusTest/ToFrontFocus.html ++java/awt/Focus/TranserFocusToWindow/TranserFocusToWindow.java ++java/awt/Focus/TypeAhead/TestFocusFreeze.java ++java/awt/Focus/WindowInitialFocusTest/WindowInitialFocusTest.html ++java/awt/Focus/WindowIsFocusableAccessByThreadsTest/WindowIsFocusableAccessByThreadsTest.java ++java/awt/Focus/WindowUpdateFocusabilityTest/WindowUpdateFocusabilityTest.html ++java/awt/Focus/WrongKeyTypedConsumedTest/WrongKeyTypedConsumedTest.java ++java/awt/FontClass/BigMetrics.java ++java/awt/FontClass/CreateFont/bigfont.html ++java/awt/FontClass/CreateFont/DeleteFont.sh ++java/awt/FontClass/CreateFont/fileaccess/FontFile.java ++java/awt/FontClass/DebugFonts.java ++java/awt/FontClass/FontAccess.java ++java/awt/FontClass/FontPrivilege.java ++java/awt/FontClass/FontSize1Test.java ++java/awt/FontClass/GlyphRotationTest.java ++java/awt/FontClass/HeadlessFont.java ++java/awt/FontClass/HelvLtOblTest.java ++java/awt/FontClass/MassiveMetricsTest.java ++java/awt/FontClass/SurrogateTest/SuppCharTest.java ++java/awt/FontClass/SurrogateTest/SupplementaryCanDisplayUpToTest.java ++java/awt/FontClass/X11FontPathCrashTest.java ++java/awt/font/FontNames/LocaleFamilyNames.java ++java/awt/font/GlyphVector/TestLayoutFlags.java ++java/awt/font/GlyphVector/VisualBounds.java ++java/awt/font/LineBreakMeasurer/AllFontsLBM.java ++java/awt/font/LineBreakMeasurer/FRCTest.java ++java/awt/FontMetrics/MaxAdvanceIsMax.java ++java/awt/FontMetrics/SpaceAdvance.java ++java/awt/FontMetrics/StyledSpaceAdvance.java ++java/awt/font/MonospacedGlyphWidth/MonospacedGlyphWidthTest.java ++java/awt/font/NumericShaper/EasternArabicTest.java ++java/awt/font/NumericShaper/EqualsTest.java ++java/awt/font/NumericShaper/MTTest.java ++java/awt/font/NumericShaper/ShapingTest.java ++java/awt/font/PhoneticExtensions/PhoneticExtensionsGlyphTest.java ++java/awt/font/Rotate/RotatedFontMetricsTest.java ++java/awt/font/Rotate/Shear.java ++java/awt/font/Rotate/TestTransform.java ++java/awt/font/Rotate/TranslatedOutlineTest.java ++java/awt/font/StyledMetrics/BoldSpace.java ++java/awt/font/TextLayout/AttributeValuesCastTest.java ++java/awt/font/TextLayout/CombiningPerf.java ++java/awt/font/TextLayout/DecorationBoundsTest.java ++java/awt/font/TextLayout/DiacriticsDrawingTest.java ++java/awt/font/TextLayout/HangulShapingTest.java ++java/awt/font/TextLayout/HebrewIsRTLTest.java ++java/awt/font/TextLayout/NegativeGlyphIDException.java ++java/awt/font/TextLayout/OSXLigatureTest.java ++java/awt/font/TextLayout/TestAATMorxFont.java ++java/awt/font/TextLayout/TestHebrewMark.java ++java/awt/font/TextLayout/TestOldHangul.java ++java/awt/font/TextLayout/TestSinhalaChar.java ++java/awt/font/TextLayout/TestTibetan.java ++java/awt/font/TextLayout/TextLayoutBounds.java ++java/awt/font/TextLayout/UnderlinePositionTest.java ++java/awt/font/TextLayout/VisibleAdvance.java ++java/awt/font/Threads/FontThread.java ++java/awt/font/TransformAttribute/TransformEqualityTest.java ++java/awt/font/Underline/UnderlineTest.java ++java/awt/Frame/7024749/bug7024749.java ++java/awt/Frame/DecoratedExceptions/DecoratedExceptions.java ++java/awt/Frame/DisposeParentGC/DisposeParentGC.java ++java/awt/Frame/DisposeStressTest/DisposeStressTest.html ++java/awt/Frame/DynamicLayout/DynamicLayout.java ++java/awt/Frame/ExceptionOnSetExtendedStateTest/ExceptionOnSetExtendedStateTest.java ++java/awt/Frame/FrameLocation/FrameLocation.java ++java/awt/Frame/FrameResize/ShowChildWhileResizingTest.java ++java/awt/Frame/FrameSetSizeStressTest/FrameSetSizeStressTest.java ++java/awt/Frame/FramesGC/FramesGC.java ++java/awt/Frame/FrameSize/TestFrameSize.java ++java/awt/Frame/HideMaximized/HideMaximized.java ++java/awt/Frame/HugeFrame/HugeFrame.java ++java/awt/Frame/InvisibleOwner/InvisibleOwner.java ++java/awt/Frame/LayoutOnMaximizeTest/LayoutOnMaximizeTest.java ++java/awt/Frame/MaximizedByPlatform/MaximizedByPlatform.java ++java/awt/Frame/MaximizedNormalBoundsUndecoratedTest/MaximizedNormalBoundsUndecoratedTest.java ++java/awt/Frame/MaximizedToIconified/MaximizedToIconified.java ++java/awt/Frame/MaximizedToMaximized/MaximizedToMaximized.java ++java/awt/Frame/MaximizedUndecorated/MaximizedUndecorated.java ++java/awt/Frame/MiscUndecorated/ActiveAWTWindowTest.java ++java/awt/Frame/MiscUndecorated/ActiveSwingWindowTest.java ++java/awt/Frame/MiscUndecorated/FrameCloseTest.java ++java/awt/Frame/MiscUndecorated/RepaintTest.java ++java/awt/Frame/MiscUndecorated/UndecoratedInitiallyIconified.java ++java/awt/Frame/NonEDT_GUI_DeadlockTest/NonEDT_GUI_Deadlock.html ++java/awt/Frame/NormalToIconified/NormalToIconifiedTest.java ++java/awt/Frame/ObscuredFrame/ObscuredFrameTest.java ++java/awt/Frame/ResizeAfterSetFont/ResizeAfterSetFont.java ++java/awt/Frame/SetMaximizedBounds/SetMaximizedBounds.java ++java/awt/Frame/ShapeNotSetSometimes/ShapeNotSetSometimes.java ++java/awt/Frame/ShownOffScreenOnWin98/ShownOffScreenOnWin98Test.java ++java/awt/Frame/SlideNotResizableTest/SlideNotResizableTest.java ++java/awt/Frame/UnfocusableMaximizedFrameResizablity/UnfocusableMaximizedFrameResizablity.java ++java/awt/Frame/WindowDragTest/WindowDragTest.java ++java/awt/FullScreen/8013581/bug8013581.java ++java/awt/FullScreen/AltTabCrashTest/AltTabCrashTest.java ++java/awt/FullScreen/BufferStrategyExceptionTest/BufferStrategyExceptionTest.java ++java/awt/FullScreen/DisplayChangeVITest/DisplayChangeVITest.java ++java/awt/FullScreen/FullScreenInsets/FullScreenInsets.java ++java/awt/FullScreen/MultimonFullscreenTest/MultimonDeadlockTest.java ++java/awt/FullScreen/NonExistentDisplayModeTest/NonExistentDisplayModeTest.java ++java/awt/FullScreen/NoResizeEventOnDMChangeTest/NoResizeEventOnDMChangeTest.java ++java/awt/FullScreen/SetFSWindow/FSFrame.java ++java/awt/FullScreen/TranslucentWindow/TranslucentWindow.java ++java/awt/FullScreen/UninitializedDisplayModeChangeTest/UninitializedDisplayModeChangeTest.java ++java/awt/geom/AffineTransform/InvalidTransformParameterTest.java ++java/awt/geom/Arc2D/SerializationTest.java ++java/awt/geom/CubicCurve2D/ContainsTest.java ++java/awt/geom/CubicCurve2D/IntersectsTest.java ++java/awt/geom/CubicCurve2D/SolveCubicTest.java ++java/awt/geom/Path2D/EmptyCapacity.java ++java/awt/geom/Path2D/FillPPathTest.java ++java/awt/geom/Path2D/Path2DCopyConstructor.java ++java/awt/geom/Path2D/Path2DGrow.java ++java/awt/grab/EmbeddedFrameTest1/EmbeddedFrameTest1.java ++java/awt/grab/GrabOnUnfocusableToplevel/GrabOnUnfocusableToplevel.java ++java/awt/grab/MenuDragEvents/MenuDragEvents.html ++java/awt/GradientPaint/GradientTransformTest.java ++java/awt/GradientPaint/HeadlessGradientPaint.java ++java/awt/GradientPaint/LinearColorSpaceGradientTest.java ++java/awt/Graphics2D/DrawString/AlphaSurfaceText.java ++java/awt/Graphics2D/DrawString/DrawRotatedString.java ++java/awt/Graphics2D/DrawString/DrawRotatedStringUsingRotatedFont.java ++java/awt/Graphics2D/DrawString/DrawStringCrash.java ++java/awt/Graphics2D/DrawString/DrawStrSuper.java ++java/awt/Graphics2D/DrawString/EmptyAttrString.java ++java/awt/Graphics2D/DrawString/LCDTextSrcEa.java ++java/awt/Graphics2D/DrawString/RotTransText.java ++java/awt/Graphics2D/DrawString/ScaledLCDTextMetrics.java ++java/awt/Graphics2D/DrawString/TextRenderingTest.java ++java/awt/Graphics2D/DrawString/XRenderElt254TextTest.java ++java/awt/Graphics2D/FillTexturePaint/FillTexturePaint.java ++java/awt/Graphics2D/FlipDrawImage/FlipDrawImage.java ++java/awt/Graphics2D/Headless/HeadlessPoint.java ++java/awt/Graphics2D/Headless/HeadlessPolygon.java ++java/awt/Graphics2D/Headless/HeadlessRectangle.java ++java/awt/Graphics2D/IncorrectTextSize/IncorrectTextSize.java ++java/awt/Graphics2D/MTGraphicsAccessTest/MTGraphicsAccessTest.java ++java/awt/Graphics2D/RenderClipTest/RenderClipTest.java ++java/awt/Graphics2D/ScaledCopyArea/ScaledCopyArea.java ++java/awt/Graphics2D/Test8004859/Test8004859.java ++java/awt/Graphics2D/TransformSetGet/TransformSetGet.java ++java/awt/Graphics2D/WhiteTextColorTest.java ++java/awt/GraphicsConfiguration/HeadlessGraphicsConfiguration.java ++java/awt/GraphicsConfiguration/NormalizingTransformTest/NormalizingTransformTest.java ++java/awt/GraphicsDevice/CheckDisplayModes.java ++java/awt/GraphicsDevice/CloneConfigsTest.java ++java/awt/GraphicsDevice/HeadlessGraphicsDevice.java ++java/awt/GraphicsDevice/IncorrectDisplayModeExitFullscreen.java ++java/awt/Graphics/DrawImageBG/SystemBgColorTest.java ++java/awt/Graphics/DrawLineTest.java ++java/awt/GraphicsEnvironment/HeadlessGraphicsEnvironment.java ++java/awt/GraphicsEnvironment/LoadLock/GE_init1.java ++java/awt/GraphicsEnvironment/LoadLock/GE_init2.java ++java/awt/GraphicsEnvironment/LoadLock/GE_init3.java ++java/awt/GraphicsEnvironment/LoadLock/GE_init4.java ++java/awt/GraphicsEnvironment/LoadLock/GE_init5.java ++java/awt/GraphicsEnvironment/LoadLock/GE_init6.java ++java/awt/GraphicsEnvironment/PreferLocaleFonts.java ++java/awt/GraphicsEnvironment/TestDetectHeadless/TestDetectHeadless.sh ++java/awt/GraphicsEnvironment/TestGetDefScreenDevice.java ++java/awt/Graphics/LineClipTest.java ++java/awt/GridBagLayout/GridBagLayoutIpadXYTest/GridBagLayoutIpadXYTest.html ++java/awt/GridLayout/ChangeGridSize/ChangeGridSize.java ++java/awt/GridLayout/ComponentPreferredSize/ComponentPreferredSize.java ++java/awt/GridLayout/LayoutExtraGaps/LayoutExtraGaps.java ++java/awt/Gtk/GtkVersionTest/GtkVersionTest.java ++java/awt/Headless/HeadlessAWTEventMulticaster.java ++java/awt/Headless/HeadlessAWTException.java ++java/awt/Headless/HeadlessBasicStroke.java ++java/awt/Headless/HeadlessBorderLayout.java ++java/awt/Headless/HeadlessCardLayout.java ++java/awt/Headless/HeadlessCheckboxGroup.java ++java/awt/Headless/HeadlessCheckboxMenuItem.java ++java/awt/Headless/HeadlessComponentOrientation.java ++java/awt/Headless/HeadlessDimension.java ++java/awt/Headless/HeadlessFlowLayout.java ++java/awt/Headless/HeadlessMediaTracker.java ++java/awt/Headless/HeadlessPopupMenu.java ++java/awt/im/6396526/IMLookAndFeel.java ++java/awt/im/8041990/bug8041990.java ++java/awt/image/BufferedImage/GetPropertyNames.java ++java/awt/image/BufferedImage/ICMColorDataTest/ICMColorDataTest.java ++java/awt/image/BufferedImage/TinyScale.java ++java/awt/image/ConvolveOp/EdgeNoOpCrash.java ++java/awt/image/ConvolveOp/OpCompatibleImageTest.java ++java/awt/image/DrawImage/DrawImageCoordsTest.java ++java/awt/image/DrawImage/EABlitTest.java ++java/awt/image/DrawImage/IncorrectAlphaConversionBicubic.java ++java/awt/image/DrawImage/IncorrectAlphaSurface2SW.java ++java/awt/image/DrawImage/IncorrectBounds.java ++java/awt/image/DrawImage/IncorrectClipSurface2SW.java ++java/awt/image/DrawImage/IncorrectClipXorModeSurface2Surface.java ++java/awt/image/DrawImage/IncorrectClipXorModeSW2Surface.java ++java/awt/image/DrawImage/IncorrectDestinationOffset.java ++java/awt/image/DrawImage/IncorrectManagedImageSourceOffset.java ++java/awt/image/DrawImage/IncorrectOffset.java ++java/awt/image/DrawImage/IncorrectSourceOffset.java ++java/awt/image/DrawImage/IncorrectUnmanagedImageRotatedClip.java ++java/awt/image/DrawImage/IncorrectUnmanagedImageSourceOffset.java ++java/awt/image/DrawImage/SimpleManagedImage.java ++java/awt/image/DrawImage/SimpleUnmanagedImage.java ++java/awt/image/DrawImage/UnmanagedDrawImagePerformance.java ++java/awt/image/FilteredImageSourceTest.java ++java/awt/image/GetDataElementsTest.java ++java/awt/image/GetSamplesTest.java ++java/awt/image/Headless/HeadlessAffineTransformOp.java ++java/awt/image/Headless/HeadlessAreaAveragingScaleFilter.java ++java/awt/image/Headless/HeadlessBufferedImageFilter.java ++java/awt/image/Headless/HeadlessBufferedImage.java ++java/awt/image/Headless/HeadlessColorModel.java ++java/awt/image/Headless/HeadlessCropImageFilter.java ++java/awt/image/Headless/HeadlessImageFilter.java ++java/awt/image/Headless/HeadlessIndexColorModel.java ++java/awt/image/Headless/HeadlessReplicateScaleFilter.java ++java/awt/image/Headless/HeadlessRGBImageFilter.java ++java/awt/image/ImageIconHang.java ++java/awt/image/ImagingOpsNoExceptionsTest/ImagingOpsNoExceptionsTest.java ++java/awt/image/IncorrectSampleMaskTest.java ++java/awt/image/LookupOp/IntImageReverseTest.java ++java/awt/image/LookupOp/SingleArrayTest.java ++java/awt/image/mlib/MlibOpsTest.java ++java/awt/image/MultiResolutionImage/MultiResolutionImageObserverTest.java ++java/awt/image/MultiResolutionImage/NSImageToMultiResolutionImageTest.java ++java/awt/image/MultiResolutionImageTest.java ++java/awt/image/multiresolution/MultiResolutionToolkitImageTest.java ++java/awt/image/Raster/TestChildRasterOp.java ++java/awt/image/VolatileImage/BitmaskVolatileImage.java ++java/awt/image/VolatileImage/VolatileImageBug.java ++java/awt/im/Headless/HeadlessInputContext.java ++java/awt/im/Headless/HeadlessInputMethodHighlight.java ++java/awt/im/InputContext/bug4625203.java ++java/awt/im/InputContext/InputContextTest.java ++java/awt/im/memoryleak/InputContextMemoryLeakTest.java ++java/awt/Insets/CombinedTestApp1.java ++java/awt/Insets/HeadlessInsets.java ++java/awt/JAWT/JAWT.sh ++java/awt/keyboard/AltPlusNumberKeyCombinationsTest/AltPlusNumberKeyCombinationsTest.java ++java/awt/keyboard/EqualKeyCode/EqualKeyCode.java ++java/awt/KeyboardFocusmanager/ConsumeNextMnemonicKeyTypedTest/ConsumeForModalDialogTest/ConsumeForModalDialogTest.html ++java/awt/KeyboardFocusmanager/ConsumeNextMnemonicKeyTypedTest/ConsumeNextMnemonicKeyTypedTest.html ++java/awt/KeyboardFocusmanager/DefaultPolicyChange/DefaultPolicyChange_AWT.java ++java/awt/KeyboardFocusmanager/DefaultPolicyChange/DefaultPolicyChange_Swing.java ++java/awt/KeyboardFocusmanager/TypeAhead/ButtonActionKeyTest/ButtonActionKeyTest.html ++java/awt/KeyboardFocusmanager/TypeAhead/EnqueueWithDialogButtonTest/EnqueueWithDialogButtonTest.java ++java/awt/KeyboardFocusmanager/TypeAhead/EnqueueWithDialogTest/EnqueueWithDialogTest.java ++java/awt/KeyboardFocusmanager/TypeAhead/FreezeTest/FreezeTest.java ++java/awt/KeyboardFocusmanager/TypeAhead/MenuItemActivatedTest/MenuItemActivatedTest.html ++java/awt/KeyboardFocusmanager/TypeAhead/SubMenuShowTest/SubMenuShowTest.html ++java/awt/KeyboardFocusmanager/TypeAhead/TestDialogTypeAhead.html ++java/awt/LightweightDispatcher/LWDispatcherMemoryLeakTest.java ++java/awt/List/ActionAfterRemove/ActionAfterRemove.java ++java/awt/List/EmptyListEventTest/EmptyListEventTest.java ++java/awt/List/FirstItemRemoveTest/FirstItemRemoveTest.html ++java/awt/List/FocusEmptyListTest/FocusEmptyListTest.html ++java/awt/List/KeyEventsTest/KeyEventsTest.html ++java/awt/List/ListGarbageCollectionTest/AwtListGarbageCollectionTest.java ++java/awt/List/ListPeer/R2303044ListSelection.java ++java/awt/List/NofocusListDblClickTest/NofocusListDblClickTest.java ++java/awt/List/ScrollOutside/ScrollOut.java ++java/awt/List/SetBackgroundTest/SetBackgroundTest.java ++java/awt/List/SingleModeDeselect/SingleModeDeselect.java ++java/awt/MenuBar/8007006/bug8007006.java ++java/awt/MenuBar/DeadlockTest1/DeadlockTest1.java ++java/awt/MenuBar/HeadlessMenuBar.java ++java/awt/MenuBar/MenuBarSetFont/MenuBarSetFont.java ++java/awt/MenuBar/RemoveHelpMenu/RemoveHelpMenu.java ++java/awt/Menu/Headless/HeadlessMenuItem.java ++java/awt/Menu/Headless/HeadlessMenu.java ++java/awt/Menu/Headless/HeadlessMenuShortcut.java ++java/awt/Menu/NullMenuLabelTest/NullMenuLabelTest.java ++java/awt/Menu/OpensWithNoGrab/OpensWithNoGrab.java ++java/awt/Mixing/AWT_Mixing/HierarchyBoundsListenerMixingTest.java ++java/awt/Mixing/AWT_Mixing/JButtonInGlassPaneOverlapping.java ++java/awt/Mixing/AWT_Mixing/JButtonOverlapping.java ++java/awt/Mixing/AWT_Mixing/JColorChooserOverlapping.java ++java/awt/Mixing/AWT_Mixing/JComboBoxOverlapping.java ++java/awt/Mixing/AWT_Mixing/JEditorPaneInGlassPaneOverlapping.java ++java/awt/Mixing/AWT_Mixing/JEditorPaneOverlapping.java ++java/awt/Mixing/AWT_Mixing/JGlassPaneInternalFrameOverlapping.java ++java/awt/Mixing/AWT_Mixing/JGlassPaneMoveOverlapping.java ++java/awt/Mixing/AWT_Mixing/JInternalFrameMoveOverlapping.java ++java/awt/Mixing/AWT_Mixing/JInternalFrameOverlapping.java ++java/awt/Mixing/AWT_Mixing/JLabelInGlassPaneOverlapping.java ++java/awt/Mixing/AWT_Mixing/JLabelOverlapping.java ++java/awt/Mixing/AWT_Mixing/JListInGlassPaneOverlapping.java ++java/awt/Mixing/AWT_Mixing/JListOverlapping.java ++java/awt/Mixing/AWT_Mixing/JMenuBarOverlapping.java ++java/awt/Mixing/AWT_Mixing/JPanelInGlassPaneOverlapping.java ++java/awt/Mixing/AWT_Mixing/JPanelOverlapping.java ++java/awt/Mixing/AWT_Mixing/JPopupMenuOverlapping.java ++java/awt/Mixing/AWT_Mixing/JProgressBarInGlassPaneOverlapping.java ++java/awt/Mixing/AWT_Mixing/JProgressBarOverlapping.java ++java/awt/Mixing/AWT_Mixing/JScrollBarInGlassPaneOverlapping.java ++java/awt/Mixing/AWT_Mixing/JScrollBarOverlapping.java ++java/awt/Mixing/AWT_Mixing/JScrollPaneOverlapping.java ++java/awt/Mixing/AWT_Mixing/JSliderInGlassPaneOverlapping.java ++java/awt/Mixing/AWT_Mixing/JSliderOverlapping.java ++java/awt/Mixing/AWT_Mixing/JSpinnerInGlassPaneOverlapping.java ++java/awt/Mixing/AWT_Mixing/JSpinnerOverlapping.java ++java/awt/Mixing/AWT_Mixing/JSplitPaneOverlapping.java ++java/awt/Mixing/AWT_Mixing/JTableInGlassPaneOverlapping.java ++java/awt/Mixing/AWT_Mixing/JTableOverlapping.java ++java/awt/Mixing/AWT_Mixing/JTextAreaInGlassPaneOverlapping.java ++java/awt/Mixing/AWT_Mixing/JTextAreaOverlapping.java ++java/awt/Mixing/AWT_Mixing/JTextFieldInGlassPaneOverlapping.java ++java/awt/Mixing/AWT_Mixing/JTextFieldOverlapping.java ++java/awt/Mixing/AWT_Mixing/JToggleButtonInGlassPaneOverlapping.java ++java/awt/Mixing/AWT_Mixing/JToggleButtonOverlapping.java ++java/awt/Mixing/AWT_Mixing/MixingFrameResizing.java ++java/awt/Mixing/AWT_Mixing/MixingPanelsResizing.java ++java/awt/Mixing/AWT_Mixing/OpaqueOverlappingChoice.java ++java/awt/Mixing/AWT_Mixing/OpaqueOverlapping.java ++java/awt/Mixing/AWT_Mixing/ViewportOverlapping.java ++java/awt/Mixing/HWDisappear.java ++java/awt/Mixing/JButtonInGlassPane.java ++java/awt/Mixing/LWComboBox.java ++java/awt/Mixing/LWPopupMenu.java ++java/awt/Mixing/MixingInHwPanel.java ++java/awt/Mixing/MixingOnDialog.java ++java/awt/Mixing/MixingOnShrinkingHWButton.java ++java/awt/Mixing/NonOpaqueInternalFrame.java ++java/awt/Mixing/OpaqueTest.java ++java/awt/Mixing/OverlappingButtons.java ++java/awt/Mixing/setComponentZOrder.java ++java/awt/Mixing/Validating.java ++java/awt/Mixing/ValidBounds.java ++java/awt/Modal/FileDialog/FileDialogAppModal1Test.java ++java/awt/Modal/FileDialog/FileDialogAppModal2Test.java ++java/awt/Modal/FileDialog/FileDialogAppModal3Test.java ++java/awt/Modal/FileDialog/FileDialogAppModal4Test.java ++java/awt/Modal/FileDialog/FileDialogAppModal5Test.java ++java/awt/Modal/FileDialog/FileDialogAppModal6Test.java ++java/awt/Modal/FileDialog/FileDialogDocModal1Test.java ++java/awt/Modal/FileDialog/FileDialogDocModal2Test.java ++java/awt/Modal/FileDialog/FileDialogDocModal3Test.java ++java/awt/Modal/FileDialog/FileDialogDocModal4Test.java ++java/awt/Modal/FileDialog/FileDialogDocModal5Test.java ++java/awt/Modal/FileDialog/FileDialogDocModal6Test.java ++java/awt/Modal/FileDialog/FileDialogDocModal7Test.java ++java/awt/Modal/FileDialog/FileDialogModal1Test.java ++java/awt/Modal/FileDialog/FileDialogModal2Test.java ++java/awt/Modal/FileDialog/FileDialogModal3Test.java ++java/awt/Modal/FileDialog/FileDialogModal4Test.java ++java/awt/Modal/FileDialog/FileDialogModal5Test.java ++java/awt/Modal/FileDialog/FileDialogModal6Test.java ++java/awt/Modal/FileDialog/FileDialogNonModal1Test.java ++java/awt/Modal/FileDialog/FileDialogNonModal2Test.java ++java/awt/Modal/FileDialog/FileDialogNonModal3Test.java ++java/awt/Modal/FileDialog/FileDialogNonModal4Test.java ++java/awt/Modal/FileDialog/FileDialogNonModal5Test.java ++java/awt/Modal/FileDialog/FileDialogNonModal6Test.java ++java/awt/Modal/FileDialog/FileDialogNonModal7Test.java ++java/awt/Modal/FileDialog/FileDialogTKModal1Test.java ++java/awt/Modal/FileDialog/FileDialogTKModal2Test.java ++java/awt/Modal/FileDialog/FileDialogTKModal3Test.java ++java/awt/Modal/FileDialog/FileDialogTKModal4Test.java ++java/awt/Modal/FileDialog/FileDialogTKModal5Test.java ++java/awt/Modal/FileDialog/FileDialogTKModal6Test.java ++java/awt/Modal/FileDialog/FileDialogTKModal7Test.java ++java/awt/Modal/LWModalTest/LWModalTest.java ++java/awt/Modal/ModalBlockingTests/BlockingDDAppModalTest.java ++java/awt/Modal/ModalBlockingTests/BlockingDDDocModalTest.java ++java/awt/Modal/ModalBlockingTests/BlockingDDModelessTest.java ++java/awt/Modal/ModalBlockingTests/BlockingDDNonModalTest.java ++java/awt/Modal/ModalBlockingTests/BlockingDDSetModalTest.java ++java/awt/Modal/ModalBlockingTests/BlockingDDToolkitModalTest.java ++java/awt/Modal/ModalBlockingTests/BlockingDFAppModalTest.java ++java/awt/Modal/ModalBlockingTests/BlockingDFSetModalTest.java ++java/awt/Modal/ModalBlockingTests/BlockingDFToolkitModalTest.java ++java/awt/Modal/ModalBlockingTests/BlockingDFWModeless1Test.java ++java/awt/Modal/ModalBlockingTests/BlockingDFWModeless2Test.java ++java/awt/Modal/ModalBlockingTests/BlockingDFWNonModal1Test.java ++java/awt/Modal/ModalBlockingTests/BlockingDFWNonModal2Test.java ++java/awt/Modal/ModalBlockingTests/BlockingDocModalTest.java ++java/awt/Modal/ModalBlockingTests/BlockingFDAppModalTest.java ++java/awt/Modal/ModalBlockingTests/BlockingFDDocModalTest.java ++java/awt/Modal/ModalBlockingTests/BlockingFDModelessTest.java ++java/awt/Modal/ModalBlockingTests/BlockingFDNonModalTest.java ++java/awt/Modal/ModalBlockingTests/BlockingFDSetModalTest.java ++java/awt/Modal/ModalBlockingTests/BlockingFDToolkitModalTest.java ++java/awt/Modal/ModalBlockingTests/BlockingFDWDocModal1Test.java ++java/awt/Modal/ModalBlockingTests/BlockingFDWDocModal2Test.java ++java/awt/Modal/ModalBlockingTests/BlockingFDWDocModal3Test.java ++java/awt/Modal/ModalBlockingTests/BlockingFDWDocModal4Test.java ++java/awt/Modal/ModalBlockingTests/BlockingFDWModeless1Test.java ++java/awt/Modal/ModalBlockingTests/BlockingFDWModeless2Test.java ++java/awt/Modal/ModalBlockingTests/BlockingFDWModeless3Test.java ++java/awt/Modal/ModalBlockingTests/BlockingFDWModeless4Test.java ++java/awt/Modal/ModalBlockingTests/BlockingFDWNonModal1Test.java ++java/awt/Modal/ModalBlockingTests/BlockingFDWNonModal2Test.java ++java/awt/Modal/ModalBlockingTests/BlockingFDWNonModal3Test.java ++java/awt/Modal/ModalBlockingTests/BlockingFDWNonModal4Test.java ++java/awt/Modal/ModalBlockingTests/BlockingWindowsAppModal1Test.java ++java/awt/Modal/ModalBlockingTests/BlockingWindowsAppModal2Test.java ++java/awt/Modal/ModalBlockingTests/BlockingWindowsAppModal3Test.java ++java/awt/Modal/ModalBlockingTests/BlockingWindowsAppModal4Test.java ++java/awt/Modal/ModalBlockingTests/BlockingWindowsAppModal5Test.java ++java/awt/Modal/ModalBlockingTests/BlockingWindowsAppModal6Test.java ++java/awt/Modal/ModalBlockingTests/BlockingWindowsDocModal1Test.java ++java/awt/Modal/ModalBlockingTests/BlockingWindowsDocModal2Test.java ++java/awt/Modal/ModalBlockingTests/BlockingWindowsSetModal1Test.java ++java/awt/Modal/ModalBlockingTests/BlockingWindowsSetModal2Test.java ++java/awt/Modal/ModalBlockingTests/BlockingWindowsSetModal3Test.java ++java/awt/Modal/ModalBlockingTests/BlockingWindowsSetModal4Test.java ++java/awt/Modal/ModalBlockingTests/BlockingWindowsSetModal5Test.java ++java/awt/Modal/ModalBlockingTests/BlockingWindowsSetModal6Test.java ++java/awt/Modal/ModalBlockingTests/BlockingWindowsToolkitModal1Test.java ++java/awt/Modal/ModalBlockingTests/BlockingWindowsToolkitModal2Test.java ++java/awt/Modal/ModalBlockingTests/BlockingWindowsToolkitModal3Test.java ++java/awt/Modal/ModalBlockingTests/BlockingWindowsToolkitModal4Test.java ++java/awt/Modal/ModalBlockingTests/BlockingWindowsToolkitModal5Test.java ++java/awt/Modal/ModalBlockingTests/BlockingWindowsToolkitModal6Test.java ++java/awt/Modal/ModalBlockingTests/UnblockedDialogAppModalTest.java ++java/awt/Modal/ModalBlockingTests/UnblockedDialogDocModalTest.java ++java/awt/Modal/ModalBlockingTests/UnblockedDialogModelessTest.java ++java/awt/Modal/ModalBlockingTests/UnblockedDialogNonModalTest.java ++java/awt/Modal/ModalBlockingTests/UnblockedDialogSetModalTest.java ++java/awt/Modal/ModalBlockingTests/UnblockedDialogToolkitModalTest.java ++java/awt/Modal/ModalDialogOrderingTest/ModalDialogOrderingTest.java ++java/awt/Modal/ModalExclusionTests/ApplicationExcludeDialogFileTest.java ++java/awt/Modal/ModalExclusionTests/ApplicationExcludeDialogPageSetupTest.java ++java/awt/Modal/ModalExclusionTests/ApplicationExcludeDialogPrintSetupTest.java ++java/awt/Modal/ModalExclusionTests/ApplicationExcludeFrameFileTest.java ++java/awt/Modal/ModalExclusionTests/ApplicationExcludeFramePageSetupTest.java ++java/awt/Modal/ModalExclusionTests/ApplicationExcludeFramePrintSetupTest.java ++java/awt/Modal/ModalExclusionTests/ToolkitExcludeDialogFileTest.java ++java/awt/Modal/ModalExclusionTests/ToolkitExcludeDialogPageSetupTest.java ++java/awt/Modal/ModalExclusionTests/ToolkitExcludeDialogPrintSetupTest.java ++java/awt/Modal/ModalExclusionTests/ToolkitExcludeFrameFileTest.java ++java/awt/Modal/ModalExclusionTests/ToolkitExcludeFramePageSetupTest.java ++java/awt/Modal/ModalExclusionTests/ToolkitExcludeFramePrintSetupTest.java ++java/awt/Modal/ModalFocusTransferTests/FocusTransferDialogsAppModalTest.java ++java/awt/Modal/ModalFocusTransferTests/FocusTransferDialogsDocModalTest.java ++java/awt/Modal/ModalFocusTransferTests/FocusTransferDialogsModelessTest.java ++java/awt/Modal/ModalFocusTransferTests/FocusTransferDialogsNonModalTest.java ++java/awt/Modal/ModalFocusTransferTests/FocusTransferDWFAppModalTest.java ++java/awt/Modal/ModalFocusTransferTests/FocusTransferDWFDocModalTest.java ++java/awt/Modal/ModalFocusTransferTests/FocusTransferDWFModelessTest.java ++java/awt/Modal/ModalFocusTransferTests/FocusTransferDWFNonModalTest.java ++java/awt/Modal/ModalFocusTransferTests/FocusTransferFDWAppModalTest.java ++java/awt/Modal/ModalFocusTransferTests/FocusTransferFDWDocModalTest.java ++java/awt/Modal/ModalFocusTransferTests/FocusTransferFDWModelessTest.java ++java/awt/Modal/ModalFocusTransferTests/FocusTransferFDWNonModalTest.java ++java/awt/Modal/ModalFocusTransferTests/FocusTransferFWDAppModal1Test.java ++java/awt/Modal/ModalFocusTransferTests/FocusTransferFWDAppModal2Test.java ++java/awt/Modal/ModalFocusTransferTests/FocusTransferFWDAppModal3Test.java ++java/awt/Modal/ModalFocusTransferTests/FocusTransferFWDAppModal4Test.java ++java/awt/Modal/ModalFocusTransferTests/FocusTransferFWDDocModal1Test.java ++java/awt/Modal/ModalFocusTransferTests/FocusTransferFWDDocModal2Test.java ++java/awt/Modal/ModalFocusTransferTests/FocusTransferFWDDocModal3Test.java ++java/awt/Modal/ModalFocusTransferTests/FocusTransferFWDDocModal4Test.java ++java/awt/Modal/ModalFocusTransferTests/FocusTransferFWDModeless1Test.java ++java/awt/Modal/ModalFocusTransferTests/FocusTransferFWDModeless2Test.java ++java/awt/Modal/ModalFocusTransferTests/FocusTransferFWDModeless3Test.java ++java/awt/Modal/ModalFocusTransferTests/FocusTransferFWDModeless4Test.java ++java/awt/Modal/ModalFocusTransferTests/FocusTransferFWDNonModal1Test.java ++java/awt/Modal/ModalFocusTransferTests/FocusTransferFWDNonModal2Test.java ++java/awt/Modal/ModalFocusTransferTests/FocusTransferFWDNonModal3Test.java ++java/awt/Modal/ModalFocusTransferTests/FocusTransferFWDNonModal4Test.java ++java/awt/Modal/ModalFocusTransferTests/FocusTransferWDFAppModal1Test.java ++java/awt/Modal/ModalFocusTransferTests/FocusTransferWDFAppModal2Test.java ++java/awt/Modal/ModalFocusTransferTests/FocusTransferWDFAppModal3Test.java ++java/awt/Modal/ModalFocusTransferTests/FocusTransferWDFDocModal1Test.java ++java/awt/Modal/ModalFocusTransferTests/FocusTransferWDFDocModal2Test.java ++java/awt/Modal/ModalFocusTransferTests/FocusTransferWDFDocModal3Test.java ++java/awt/Modal/ModalFocusTransferTests/FocusTransferWDFModeless1Test.java ++java/awt/Modal/ModalFocusTransferTests/FocusTransferWDFModeless2Test.java ++java/awt/Modal/ModalFocusTransferTests/FocusTransferWDFModeless3Test.java ++java/awt/Modal/ModalFocusTransferTests/FocusTransferWDFNonModal1Test.java ++java/awt/Modal/ModalFocusTransferTests/FocusTransferWDFNonModal2Test.java ++java/awt/Modal/ModalFocusTransferTests/FocusTransferWDFNonModal3Test.java ++java/awt/Modal/ModalInternalFrameTest/ModalInternalFrameTest.java ++java/awt/Modal/ModalitySettingsTest/ModalitySettingsTest.java ++java/awt/Modal/MultipleDialogs/MultipleDialogs1Test.java ++java/awt/Modal/MultipleDialogs/MultipleDialogs2Test.java ++java/awt/Modal/MultipleDialogs/MultipleDialogs3Test.java ++java/awt/Modal/MultipleDialogs/MultipleDialogs4Test.java ++java/awt/Modal/MultipleDialogs/MultipleDialogs5Test.java ++java/awt/Modal/NpeOnClose/NpeOnCloseTest.java ++java/awt/Modal/NullModalityDialogTest/NullModalityDialogTest.java ++java/awt/Modal/OnTop/OnTopAppModal1Test.java ++java/awt/Modal/OnTop/OnTopAppModal2Test.java ++java/awt/Modal/OnTop/OnTopAppModal3Test.java ++java/awt/Modal/OnTop/OnTopAppModal4Test.java ++java/awt/Modal/OnTop/OnTopAppModal5Test.java ++java/awt/Modal/OnTop/OnTopAppModal6Test.java ++java/awt/Modal/OnTop/OnTopDocModal1Test.java ++java/awt/Modal/OnTop/OnTopDocModal2Test.java ++java/awt/Modal/OnTop/OnTopDocModal3Test.java ++java/awt/Modal/OnTop/OnTopDocModal4Test.java ++java/awt/Modal/OnTop/OnTopDocModal5Test.java ++java/awt/Modal/OnTop/OnTopDocModal6Test.java ++java/awt/Modal/OnTop/OnTopModal1Test.java ++java/awt/Modal/OnTop/OnTopModal2Test.java ++java/awt/Modal/OnTop/OnTopModal3Test.java ++java/awt/Modal/OnTop/OnTopModal4Test.java ++java/awt/Modal/OnTop/OnTopModal5Test.java ++java/awt/Modal/OnTop/OnTopModal6Test.java ++java/awt/Modal/OnTop/OnTopModeless1Test.java ++java/awt/Modal/OnTop/OnTopModeless2Test.java ++java/awt/Modal/OnTop/OnTopModeless3Test.java ++java/awt/Modal/OnTop/OnTopModeless4Test.java ++java/awt/Modal/OnTop/OnTopModeless5Test.java ++java/awt/Modal/OnTop/OnTopModeless6Test.java ++java/awt/Modal/OnTop/OnTopTKModal1Test.java ++java/awt/Modal/OnTop/OnTopTKModal2Test.java ++java/awt/Modal/OnTop/OnTopTKModal3Test.java ++java/awt/Modal/OnTop/OnTopTKModal4Test.java ++java/awt/Modal/OnTop/OnTopTKModal5Test.java ++java/awt/Modal/OnTop/OnTopTKModal6Test.java ++java/awt/Modal/SupportedTest/SupportedTest.java ++java/awt/Modal/ToBack/ToBackAppModal1Test.java ++java/awt/Modal/ToBack/ToBackAppModal2Test.java ++java/awt/Modal/ToBack/ToBackAppModal3Test.java ++java/awt/Modal/ToBack/ToBackAppModal4Test.java ++java/awt/Modal/ToBack/ToBackAppModal5Test.java ++java/awt/Modal/ToBack/ToBackAppModal6Test.java ++java/awt/Modal/ToBack/ToBackDocModal1Test.java ++java/awt/Modal/ToBack/ToBackDocModal2Test.java ++java/awt/Modal/ToBack/ToBackDocModal3Test.java ++java/awt/Modal/ToBack/ToBackDocModal4Test.java ++java/awt/Modal/ToBack/ToBackDocModal5Test.java ++java/awt/Modal/ToBack/ToBackDocModal6Test.java ++java/awt/Modal/ToBack/ToBackModal1Test.java ++java/awt/Modal/ToBack/ToBackModal2Test.java ++java/awt/Modal/ToBack/ToBackModal3Test.java ++java/awt/Modal/ToBack/ToBackModal4Test.java ++java/awt/Modal/ToBack/ToBackModal5Test.java ++java/awt/Modal/ToBack/ToBackModal6Test.java ++java/awt/Modal/ToBack/ToBackModeless1Test.java ++java/awt/Modal/ToBack/ToBackModeless2Test.java ++java/awt/Modal/ToBack/ToBackModeless3Test.java ++java/awt/Modal/ToBack/ToBackModeless4Test.java ++java/awt/Modal/ToBack/ToBackModeless5Test.java ++java/awt/Modal/ToBack/ToBackModeless6Test.java ++java/awt/Modal/ToBack/ToBackNonModal1Test.java ++java/awt/Modal/ToBack/ToBackNonModal2Test.java ++java/awt/Modal/ToBack/ToBackNonModal3Test.java ++java/awt/Modal/ToBack/ToBackNonModal4Test.java ++java/awt/Modal/ToBack/ToBackNonModal5Test.java ++java/awt/Modal/ToBack/ToBackNonModal6Test.java ++java/awt/Modal/ToBack/ToBackTKModal1Test.java ++java/awt/Modal/ToBack/ToBackTKModal2Test.java ++java/awt/Modal/ToBack/ToBackTKModal3Test.java ++java/awt/Modal/ToBack/ToBackTKModal4Test.java ++java/awt/Modal/ToBack/ToBackTKModal5Test.java ++java/awt/Modal/ToBack/ToBackTKModal6Test.java ++java/awt/Modal/ToFront/DialogToFrontAppModalTest.java ++java/awt/Modal/ToFront/DialogToFrontDocModalTest.java ++java/awt/Modal/ToFront/DialogToFrontModalTest.java ++java/awt/Modal/ToFront/DialogToFrontModeless1Test.java ++java/awt/Modal/ToFront/DialogToFrontNonModalTest.java ++java/awt/Modal/ToFront/DialogToFrontTKModalTest.java ++java/awt/Modal/ToFront/FrameToFrontAppModal1Test.java ++java/awt/Modal/ToFront/FrameToFrontAppModal2Test.java ++java/awt/Modal/ToFront/FrameToFrontAppModal3Test.java ++java/awt/Modal/ToFront/FrameToFrontAppModal4Test.java ++java/awt/Modal/ToFront/FrameToFrontAppModal5Test.java ++java/awt/Modal/ToFront/FrameToFrontDocModal1Test.java ++java/awt/Modal/ToFront/FrameToFrontDocModal2Test.java ++java/awt/Modal/ToFront/FrameToFrontModal1Test.java ++java/awt/Modal/ToFront/FrameToFrontModal2Test.java ++java/awt/Modal/ToFront/FrameToFrontModal3Test.java ++java/awt/Modal/ToFront/FrameToFrontModal4Test.java ++java/awt/Modal/ToFront/FrameToFrontModal5Test.java ++java/awt/Modal/ToFront/FrameToFrontModeless1Test.java ++java/awt/Modal/ToFront/FrameToFrontNonModalTest.java ++java/awt/Modal/ToFront/FrameToFrontTKModal1Test.java ++java/awt/Modal/ToFront/FrameToFrontTKModal2Test.java ++java/awt/Modal/ToFront/FrameToFrontTKModal3Test.java ++java/awt/Modal/ToFront/FrameToFrontTKModal4Test.java ++java/awt/Modal/ToFront/FrameToFrontTKModal5Test.java ++java/awt/MouseAdapter/MouseAdapterUnitTest/MouseAdapterUnitTest.java ++java/awt/Mouse/EnterExitEvents/DragWindowOutOfFrameTest.java ++java/awt/Mouse/EnterExitEvents/DragWindowTest.java ++java/awt/Mouse/EnterExitEvents/ModalDialogEnterExitEventsTest.java ++java/awt/Mouse/EnterExitEvents/ResizingFrameTest.java ++java/awt/Mouse/ExtraMouseClick/ExtraMouseClick.html ++java/awt/Mouse/GetMousePositionTest/GetMousePositionWithOverlay.java ++java/awt/Mouse/GetMousePositionTest/GetMousePositionWithPopup.java ++java/awt/MouseInfo/GetPointerInfoTest.java ++java/awt/MouseInfo/JContainerMousePositionTest.java ++java/awt/MouseInfo/MultiscreenPointerInfo.java ++java/awt/Mouse/MaximizedFrameTest/MaximizedFrameTest.java ++java/awt/Mouse/MouseComboBoxTest/MouseComboBoxTest.java ++java/awt/Mouse/MouseDragEvent/MouseDraggedTest.java ++java/awt/Mouse/MouseModifiersUnitTest/ExtraButtonDrag.java ++java/awt/Mouse/MouseModifiersUnitTest/MouseModifiersUnitTest_Extra.java ++java/awt/Mouse/MouseModifiersUnitTest/MouseModifiersUnitTest_Standard.java ++java/awt/Mouse/RemovedComponentMouseListener/RemovedComponentMouseListener.java ++java/awt/Mouse/TitleBarDoubleClick/TitleBarDoubleClick.html ++java/awt/Multiscreen/LocationRelativeToTest/LocationRelativeToTest.java ++java/awt/Multiscreen/MouseEventTest/MouseEventTest.java ++java/awt/Multiscreen/MultiScreenInsetsTest/MultiScreenInsetsTest.java ++java/awt/Multiscreen/MultiScreenLocationTest/MultiScreenLocationTest.java ++java/awt/Multiscreen/TranslucencyThrowsExceptionWhenFullScreen/TranslucencyThrowsExceptionWhenFullScreen.java ++java/awt/Multiscreen/UpdateGCTest/UpdateGCTest.java ++java/awt/Multiscreen/WindowGCChangeTest/WindowGCChangeTest.html ++java/awt/Multiscreen/WPanelPeerPerf/WPanelPeerPerf.java ++java/awt/Paint/bug8024864.java ++java/awt/Paint/ButtonRepaint.java ++java/awt/Paint/CheckboxRepaint.java ++java/awt/Paint/ComponentIsNotDrawnAfterRemoveAddTest/ComponentIsNotDrawnAfterRemoveAddTest.java ++java/awt/Paint/ExposeOnEDT.java ++java/awt/Paint/LabelRepaint.java ++java/awt/Paint/ListRepaint.java ++java/awt/Paint/PaintNativeOnUpdate.java ++java/awt/Paint/PgramUserBoundsTest.java ++java/awt/Paint/RepaintOnAWTShutdown.java ++java/awt/print/Headless/HeadlessBook.java ++java/awt/print/Headless/HeadlessPageFormat.java ++java/awt/print/Headless/HeadlessPaper.java ++java/awt/print/Headless/HeadlessPrinterJob.java ++java/awt/PrintJob/MultipleEnd/MultipleEnd.java ++java/awt/PrintJob/PrintArcTest/PrintArcTest.java ++java/awt/PrintJob/QuoteAndBackslashTest/QuoteAndBackslashTest.java ++java/awt/PrintJob/RoundedRectTest/RoundedRectTest.java ++java/awt/PrintJob/Security/SecurityDialogTest.java ++java/awt/print/PageFormat/NullPaper.java ++java/awt/print/PageFormat/PageFormatFromAttributes.java ++java/awt/print/PageFormat/ReverseLandscapeTest.java ++java/awt/print/PaintSetEnabledDeadlock/PaintSetEnabledDeadlock.java ++java/awt/print/PrinterJob/CheckAccess.java ++java/awt/print/PrinterJob/CheckPrivilege.java ++java/awt/print/PrinterJob/CustomPrintService/SetPrintServiceTest.java ++java/awt/print/PrinterJob/DeviceScale.java ++java/awt/print/PrinterJob/EmptyFill.java ++java/awt/print/PrinterJob/ExceptionTest.java ++java/awt/print/PrinterJob/GetMediasTest.java ++java/awt/print/PrinterJob/GlyphPositions.java ++java/awt/print/PrinterJob/HeadlessPrintingTest.java ++java/awt/print/PrinterJob/ImagePrinting/NullClipARGB.java ++java/awt/print/PrinterJob/NullGetName.java ++java/awt/print/PrinterJob/PaintText.java ++java/awt/print/PrinterJob/PrintCrashTest.java ++java/awt/print/PrinterJob/PrintTextPane.java ++java/awt/print/PrinterJob/PrintToDir.java ++java/awt/print/PrinterJob/PrtException.java ++java/awt/print/PrinterJob/PSQuestionMark.java ++java/awt/print/PrinterJob/PSWindingRule.java ++java/awt/print/PrinterJob/RemoveListener.java ++java/awt/print/PrinterJob/SameService.java ++java/awt/print/PrintServicesSecurityManager.java ++java/awt/Robot/AcceptExtraMouseButtons/AcceptExtraMouseButtons.java ++java/awt/Robot/CtorTest/CtorTest.java ++java/awt/Robot/ModifierRobotKey/ModifierRobotKeyTest.java ++java/awt/Robot/RobotExtraButton/RobotExtraButton.java ++java/awt/Robot/WaitForIdleSyncroizedOnString/WaitForIdleSyncroizedOnString.java ++java/awt/ScrollPane/bug8077409Test.java ++java/awt/ScrollPane/ScrollPanePreferredSize/ScrollPanePreferredSize.java ++java/awt/ScrollPane/ScrollPaneValidateTest.java ++java/awt/security/Permissions.java ++java/awt/SplashScreen/MultiResolutionSplash/MultiResolutionSplashTest.java ++java/awt/TextArea/DisposeTest/TestDispose.java ++java/awt/TextArea/Mixing/TextAreaMixing.java ++java/awt/TextArea/ScrollbarIntersectionTest/ScrollbarIntersectionTest.java ++java/awt/TextArea/TextAreaCaretVisibilityTest/bug7129742.java ++java/awt/TextArea/TextAreaEditing/TextAreaEditing.java ++java/awt/TextArea/TextAreaTwicePack/TextAreaTwicePack.java ++java/awt/TextArea/UsingWithMouse/SelectionAutoscrollTest.html ++java/awt/TextField/DisposeTest/TestDispose.java ++java/awt/TextField/SelectionInvisibleTest/SelectionInvisibleTest.java ++java/awt/Toolkit/AutoShutdown/EventQueuePush/EventQueuePushAutoshutdown.sh ++java/awt/Toolkit/AutoShutdown/ShowExitTest/ShowExitTest.sh ++java/awt/Toolkit/BadDisplayTest/BadDisplayTest.java ++java/awt/Toolkit/DesktopProperties/rfe4758438.java ++java/awt/Toolkit/DisplayChangesException/DisplayChangesException.java ++java/awt/Toolkit/DynamicLayout/bug7172833.java ++java/awt/Toolkit/GetImage/bug8078165.java ++java/awt/Toolkit/Headless/AWTEventListener/AWTListener.java ++java/awt/Toolkit/Headless/ExceptionContract/ExceptionContract.java ++java/awt/Toolkit/Headless/GetPrintJob/GetPrintJobHeadless.java ++java/awt/Toolkit/Headless/GetPrintJob/GetPrintJob.java ++java/awt/Toolkit/Headless/HeadlessToolkit.java ++java/awt/Toolkit/HeadlessTray/HeadlessTray.java ++java/awt/Toolkit/Headless/WrappedToolkitTest/WrappedToolkitTest.sh ++java/awt/Toolkit/LoadAWTCrashTest/LoadAWTCrashTest.java ++java/awt/Toolkit/LockingKeyStateTest/LockingKeyStateTest.java ++java/awt/Toolkit/RealSync/RealSyncOnEDT.java ++java/awt/Toolkit/RealSync/Test.java ++java/awt/Toolkit/ScreenInsetsTest/ScreenInsetsTest.java ++java/awt/Toolkit/SecurityTest/SecurityTest2.java ++java/awt/Toolkit/ToolkitPropertyTest/bug7129133.java ++java/awt/Toolkit/ToolkitPropertyTest/SystemPropTest_1.java ++java/awt/Toolkit/ToolkitPropertyTest/SystemPropTest_2.java ++java/awt/Toolkit/ToolkitPropertyTest/SystemPropTest_3.java ++java/awt/Toolkit/ToolkitPropertyTest/SystemPropTest_4.java ++java/awt/Toolkit/ToolkitPropertyTest/SystemPropTest_5.java ++java/awt/Toolkit/ToolkitPropertyTest/ToolkitPropertyTest_Disable.java ++java/awt/Toolkit/ToolkitPropertyTest/ToolkitPropertyTest_Enable.java ++java/awt/TrayIcon/8072769/bug8072769.java ++java/awt/TrayIcon/ActionCommand/ActionCommand.java ++java/awt/TrayIcon/ActionEventMask/ActionEventMask.java ++java/awt/TrayIcon/CtorTest/CtorTest.java ++java/awt/TrayIcon/GetTrayIconsTest/GetTrayIcons.java ++java/awt/TrayIcon/InterJVMTest/InterJVM.java ++java/awt/TrayIcon/ModalityTest/ModalityTest.java ++java/awt/TrayIcon/MouseEventMask/MouseEventMaskTest.java ++java/awt/TrayIcon/MouseMovedTest/MouseMovedTest.java ++java/awt/TrayIcon/PopupMenuLeakTest/PopupMenuLeakTest.java ++java/awt/TrayIcon/PropertyChangeListenerTest.java ++java/awt/TrayIcon/SecurityCheck/FunctionalityCheck/FunctionalityCheck.java ++java/awt/TrayIcon/SecurityCheck/NoPermissionTest/NoPermissionTest.java ++java/awt/TrayIcon/SecurityCheck/PermissionTest/PermissionTest.java ++java/awt/TrayIcon/SystemTrayInstance/SystemTrayInstanceTest.java ++java/awt/TrayIcon/TrayIconAddTest/TrayIconAddTest.java ++java/awt/TrayIcon/TrayIconEventModifiers/TrayIconEventModifiersTest.java ++java/awt/TrayIcon/TrayIconEvents/TrayIconEventsTest.java ++java/awt/TrayIcon/TrayIconMethodsTest/TrayIconMethodsTest.java ++java/awt/TrayIcon/TrayIconMouseTest/TrayIconMouseTest.java ++java/awt/TrayIcon/TrayIconPopup/TrayIconPopupTest.java ++java/awt/TrayIcon/TrayIconRemoveTest/TrayIconRemoveTest.java ++java/awt/TrayIcon/TrayIconSizeTest/TrayIconSizeTest.java ++java/awt/Window/8027025/Test8027025.java ++java/awt/Window/AlwaysOnTop/AlwaysOnTopEvenOfWindow.java ++java/awt/Window/AlwaysOnTop/AlwaysOnTopFieldTest.java ++java/awt/Window/AlwaysOnTop/AutoTestOnTop.java ++java/awt/Window/AlwaysOnTop/SyncAlwaysOnTopFieldTest.java ++java/awt/Window/AlwaysOnTop/TestAlwaysOnTopBeforeShow.java ++java/awt/Window/BackgroundIsNotUpdated/BackgroundIsNotUpdated.java ++java/awt/Window/GetWindowsTest/GetWindowsTest.java ++java/awt/Window/Grab/GrabTest.java ++java/awt/Window/GrabSequence/GrabSequence.java ++java/awt/Window/HandleWindowDestroyTest/HandleWindowDestroyTest.html ++java/awt/Window/LocationByPlatform/LocationByPlatformTest.java ++java/awt/Window/MaximizeOffscreen/MaximizeOffscreenTest.java ++java/awt/Window/OwnedWindowsLeak/OwnedWindowsLeak.java ++java/awt/Window/OwnedWindowsSerialization/OwnedWindowsSerialization.java ++java/awt/Window/PropertyChangeListenerLockSerialization/PropertyChangeListenerLockSerialization.java ++java/awt/Window/SetBackgroundNPE/SetBackgroundNPE.java ++java/awt/Window/setLocRelativeTo/SetLocationRelativeToTest.java ++java/awt/Window/ShapedAndTranslucentWindows/FocusAWTTest.java ++java/awt/Window/ShapedAndTranslucentWindows/SetShapeAndClick.java ++java/awt/Window/ShapedAndTranslucentWindows/SetShapeDynamicallyAndClick.java ++java/awt/Window/ShapedAndTranslucentWindows/SetShape.java ++java/awt/Window/ShapedAndTranslucentWindows/ShapedByAPI.java ++java/awt/Window/ShapedAndTranslucentWindows/Shaped.java ++java/awt/Window/ShapedAndTranslucentWindows/ShapedTranslucent.java ++java/awt/Window/ShapedAndTranslucentWindows/ShapedTranslucentWindowClick.java ++java/awt/Window/ShapedAndTranslucentWindows/StaticallyShaped.java ++java/awt/Window/ShapedAndTranslucentWindows/TranslucentChoice.java ++java/awt/Window/ShapedAndTranslucentWindows/Translucent.java ++java/awt/Window/ShapedAndTranslucentWindows/TranslucentWindowClick.java ++java/awt/Window/TopLevelLocation/TopLevelLocation.java ++java/awt/Window/WindowClosedEvents/WindowClosedEventOnDispose.java ++java/awt/Window/WindowDeadlockTest/WindowDeadlockTest.java ++java/awt/Window/WindowGCInFullScreen/WindowGCInFullScreen.java ++java/awt/Window/WindowJumpingTest/WindowJumpingTest.java ++java/awt/Window/WindowsLeak/WindowsLeak.java ++java/awt/Window/WindowType/WindowType.java ++java/awt/WMSpecificTests/Metacity/FullscreenDialogModality.java ++java/awt/WMSpecificTests/Mutter/MutterMaximizeTest.java ++java/awt/xembed/server/RunTestXEmbed.java ++java/beans/XMLEncoder/java_awt_AWTKeyStroke.java ++java/beans/XMLEncoder/java_awt_BasicStroke.java ++java/beans/XMLEncoder/java_awt_BorderLayout.java ++java/beans/XMLEncoder/java_awt_CardLayout.java ++java/beans/XMLEncoder/java_awt_Color.java ++java/beans/XMLEncoder/java_awt_Component.java ++java/beans/XMLEncoder/java_awt_Cursor.java ++java/beans/XMLEncoder/java_awt_Dimension.java ++java/beans/XMLEncoder/java_awt_Font.java ++java/beans/XMLEncoder/java_awt_geom_AffineTransform.java ++java/beans/XMLEncoder/java_awt_GradientPaint.java ++java/beans/XMLEncoder/java_awt_GridBagConstraints.java ++java/beans/XMLEncoder/java_awt_GridBagLayout.java ++java/beans/XMLEncoder/java_awt_Insets.java ++java/beans/XMLEncoder/java_awt_LinearGradientPaint.java ++java/beans/XMLEncoder/java_awt_MenuShortcut.java ++java/beans/XMLEncoder/java_awt_Point.java ++java/beans/XMLEncoder/java_awt_RadialGradientPaint.java ++java/beans/XMLEncoder/java_awt_Rectangle.java ++java/beans/XMLEncoder/java_awt_ScrollPane.java ++java/beans/XMLEncoder/javax_swing_border_BevelBorder.java ++java/beans/XMLEncoder/javax_swing_border_CompoundBorder.java ++java/beans/XMLEncoder/javax_swing_border_EmptyBorder.java ++java/beans/XMLEncoder/javax_swing_border_EtchedBorder.java ++java/beans/XMLEncoder/javax_swing_border_LineBorder.java ++java/beans/XMLEncoder/javax_swing_border_MatteBorder.java ++java/beans/XMLEncoder/javax_swing_border_SoftBevelBorder.java ++java/beans/XMLEncoder/javax_swing_border_StrokeBorder.java ++java/beans/XMLEncoder/javax_swing_border_TitledBorder.java ++java/beans/XMLEncoder/javax_swing_Box_Filler.java ++java/beans/XMLEncoder/javax_swing_Box.java ++java/beans/XMLEncoder/javax_swing_BoxLayout.java ++java/beans/XMLEncoder/javax_swing_DefaultCellEditor.java ++java/beans/XMLEncoder/javax_swing_JButton.java ++java/beans/XMLEncoder/javax_swing_JLayeredPane.java ++java/beans/XMLEncoder/javax_swing_JSplitPane.java ++java/beans/XMLEncoder/javax_swing_JTree.java ++java/beans/XMLEncoder/javax_swing_KeyStroke.java ++java/beans/XMLEncoder/javax_swing_OverlayLayout.java ++java/beans/XMLEncoder/javax_swing_plaf_BorderUIResource_BevelBorderUIResource.java ++java/beans/XMLEncoder/javax_swing_plaf_BorderUIResource_CompoundBorderUIResource.java ++java/beans/XMLEncoder/javax_swing_plaf_BorderUIResource_EmptyBorderUIResource.java ++java/beans/XMLEncoder/javax_swing_plaf_BorderUIResource_EtchedBorderUIResource.java ++java/beans/XMLEncoder/javax_swing_plaf_BorderUIResource_LineBorderUIResource.java ++java/beans/XMLEncoder/javax_swing_plaf_BorderUIResource_MatteBorderUIResource.java ++java/beans/XMLEncoder/javax_swing_plaf_BorderUIResource_TitledBorderUIResource.java ++java/beans/XMLEncoder/javax_swing_plaf_ColorUIResource.java ++java/beans/XMLEncoder/javax_swing_plaf_FontUIResource.java ++java/beans/XMLEncoder/javax_swing_tree_DefaultTreeModel.java ++java/beans/XMLEncoder/javax_swing_tree_TreePath.java ++java/beans/XMLEncoder/sun_swing_PrintColorUIResource.java ++java/lang/SecurityManager/NoAWT.java ++javax/sound/midi/Devices/ClosedReceiver.java ++javax/sound/midi/Devices/InitializationHang.java ++javax/sound/midi/Devices/MidiDeviceGetReceivers.java ++javax/sound/midi/Devices/MidiIO.java ++javax/sound/midi/Devices/MidiOutGetMicrosecondPositionBug.java ++javax/sound/midi/Devices/OpenClose.java ++javax/sound/midi/Devices/ReceiverTransmitterAvailable.java ++javax/sound/midi/Devices/Reopen.java ++javax/sound/midi/File/SMFCp037.java ++javax/sound/midi/File/SMFParserBreak.java ++javax/sound/midi/File/SMPTESequence.java ++javax/sound/midi/File/WriteRealTimeMessageNPE.java ++javax/sound/midi/Gervill/AudioFloatConverter/GetFormat.java ++javax/sound/midi/Gervill/AudioFloatConverter/ToFloatArray.java ++javax/sound/midi/Gervill/AudioFloatFormatConverter/SkipTest.java ++javax/sound/midi/Gervill/AudioFloatInputStream/Available.java ++javax/sound/midi/Gervill/AudioFloatInputStream/Close.java ++javax/sound/midi/Gervill/AudioFloatInputStream/GetFormat.java ++javax/sound/midi/Gervill/AudioFloatInputStream/GetFrameLength.java ++javax/sound/midi/Gervill/AudioFloatInputStream/MarkSupported.java ++javax/sound/midi/Gervill/AudioFloatInputStream/ReadFloatArrayIntInt.java ++javax/sound/midi/Gervill/AudioFloatInputStream/ReadFloatArray.java ++javax/sound/midi/Gervill/AudioFloatInputStream/Read.java ++javax/sound/midi/Gervill/AudioFloatInputStream/Reset.java ++javax/sound/midi/Gervill/AudioFloatInputStream/Skip.java ++javax/sound/midi/Gervill/DLSSoundbankReader/TestGetSoundbankFile.java ++javax/sound/midi/Gervill/DLSSoundbankReader/TestGetSoundbankInputStream2.java ++javax/sound/midi/Gervill/DLSSoundbankReader/TestGetSoundbankInputStream.java ++javax/sound/midi/Gervill/DLSSoundbankReader/TestGetSoundbankUrl.java ++javax/sound/midi/Gervill/EmergencySoundbank/TestCreateSoundbank.java ++javax/sound/midi/Gervill/ModelByteBuffer/GetInputStream.java ++javax/sound/midi/Gervill/ModelByteBuffer/GetRoot.java ++javax/sound/midi/Gervill/ModelByteBuffer/LoadAll.java ++javax/sound/midi/Gervill/ModelByteBuffer/Load.java ++javax/sound/midi/Gervill/ModelByteBuffer/NewModelByteBufferByteArrayIntInt.java ++javax/sound/midi/Gervill/ModelByteBuffer/NewModelByteBufferByteArray.java ++javax/sound/midi/Gervill/ModelByteBuffer/NewModelByteBufferFile.java ++javax/sound/midi/Gervill/ModelByteBuffer/NewModelByteBufferFileLongLong.java ++javax/sound/midi/Gervill/ModelByteBuffer/RandomFileInputStream/Available.java ++javax/sound/midi/Gervill/ModelByteBuffer/RandomFileInputStream/Close.java ++javax/sound/midi/Gervill/ModelByteBuffer/RandomFileInputStream/MarkReset.java ++javax/sound/midi/Gervill/ModelByteBuffer/RandomFileInputStream/MarkSupported.java ++javax/sound/midi/Gervill/ModelByteBuffer/RandomFileInputStream/ReadByteIntInt.java ++javax/sound/midi/Gervill/ModelByteBuffer/RandomFileInputStream/ReadByte.java ++javax/sound/midi/Gervill/ModelByteBuffer/RandomFileInputStream/Read.java ++javax/sound/midi/Gervill/ModelByteBuffer/RandomFileInputStream/Skip.java ++javax/sound/midi/Gervill/ModelByteBuffer/SubbufferLong.java ++javax/sound/midi/Gervill/ModelByteBuffer/SubbufferLongLongBoolean.java ++javax/sound/midi/Gervill/ModelByteBuffer/SubbufferLongLong.java ++javax/sound/midi/Gervill/ModelByteBuffer/Unload.java ++javax/sound/midi/Gervill/ModelByteBufferWavetable/GetAttenuation.java ++javax/sound/midi/Gervill/ModelByteBufferWavetable/GetChannels.java ++javax/sound/midi/Gervill/ModelByteBufferWavetable/GetLoopLength.java ++javax/sound/midi/Gervill/ModelByteBufferWavetable/GetLoopStart.java ++javax/sound/midi/Gervill/ModelByteBufferWavetable/GetPitchCorrection.java ++javax/sound/midi/Gervill/ModelByteBufferWavetable/NewModelByteBufferWavetableModelByteBufferAudioFormatFloat.java ++javax/sound/midi/Gervill/ModelByteBufferWavetable/NewModelByteBufferWavetableModelByteBufferAudioFormat.java ++javax/sound/midi/Gervill/ModelByteBufferWavetable/NewModelByteBufferWavetableModelByteBufferFloat.java ++javax/sound/midi/Gervill/ModelByteBufferWavetable/NewModelByteBufferWavetableModelByteBuffer.java ++javax/sound/midi/Gervill/ModelByteBufferWavetable/Open.java ++javax/sound/midi/Gervill/ModelByteBufferWavetable/OpenStream.java ++javax/sound/midi/Gervill/ModelByteBufferWavetable/Set8BitExtensionBuffer.java ++javax/sound/midi/Gervill/ModelByteBufferWavetable/SetLoopType.java ++javax/sound/midi/Gervill/ModelByteBuffer/WriteTo.java ++javax/sound/midi/Gervill/ModelDestination/NewModelDestination.java ++javax/sound/midi/Gervill/ModelDestination/NewModelDestinationModelIdentifier.java ++javax/sound/midi/Gervill/ModelDestination/SetIdentifier.java ++javax/sound/midi/Gervill/ModelDestination/SetTransform.java ++javax/sound/midi/Gervill/ModelIdentifier/EqualsObject.java ++javax/sound/midi/Gervill/ModelIdentifier/NewModelIdentifierStringInt.java ++javax/sound/midi/Gervill/ModelIdentifier/NewModelIdentifierString.java ++javax/sound/midi/Gervill/ModelIdentifier/NewModelIdentifierStringStringInt.java ++javax/sound/midi/Gervill/ModelIdentifier/NewModelIdentifierStringString.java ++javax/sound/midi/Gervill/ModelIdentifier/SetInstance.java ++javax/sound/midi/Gervill/ModelIdentifier/SetObject.java ++javax/sound/midi/Gervill/ModelIdentifier/SetVariable.java ++javax/sound/midi/Gervill/ModelPerformer/GetOscillators.java ++javax/sound/midi/Gervill/ModelPerformer/SetConnectionBlocks.java ++javax/sound/midi/Gervill/ModelPerformer/SetDefaultConnectionsEnabled.java ++javax/sound/midi/Gervill/ModelPerformer/SetExclusiveClass.java ++javax/sound/midi/Gervill/ModelPerformer/SetKeyFrom.java ++javax/sound/midi/Gervill/ModelPerformer/SetKeyTo.java ++javax/sound/midi/Gervill/ModelPerformer/SetName.java ++javax/sound/midi/Gervill/ModelPerformer/SetSelfNonExclusive.java ++javax/sound/midi/Gervill/ModelPerformer/SetVelFrom.java ++javax/sound/midi/Gervill/ModelPerformer/SetVelTo.java ++javax/sound/midi/Gervill/ModelSource/NewModelSource.java ++javax/sound/midi/Gervill/ModelSource/NewModelSourceModelIdentifierBooleanBooleanInt.java ++javax/sound/midi/Gervill/ModelSource/NewModelSourceModelIdentifierBooleanBoolean.java ++javax/sound/midi/Gervill/ModelSource/NewModelSourceModelIdentifierBoolean.java ++javax/sound/midi/Gervill/ModelSource/NewModelSourceModelIdentifier.java ++javax/sound/midi/Gervill/ModelSource/NewModelSourceModelIdentifierModelTransform.java ++javax/sound/midi/Gervill/ModelSource/SetIdentifier.java ++javax/sound/midi/Gervill/ModelSource/SetTransform.java ++javax/sound/midi/Gervill/ModelStandardIndexedDirector/ModelStandardIndexedDirectorTest.java ++javax/sound/midi/Gervill/ModelStandardTransform/NewModelStandardTransformBooleanBooleanInt.java ++javax/sound/midi/Gervill/ModelStandardTransform/NewModelStandardTransformBooleanBoolean.java ++javax/sound/midi/Gervill/ModelStandardTransform/NewModelStandardTransformBoolean.java ++javax/sound/midi/Gervill/ModelStandardTransform/NewModelStandardTransform.java ++javax/sound/midi/Gervill/ModelStandardTransform/SetDirection.java ++javax/sound/midi/Gervill/ModelStandardTransform/SetPolarity.java ++javax/sound/midi/Gervill/ModelStandardTransform/SetTransform.java ++javax/sound/midi/Gervill/ModelStandardTransform/TransformAbsolute.java ++javax/sound/midi/Gervill/ModelStandardTransform/TransformConcave.java ++javax/sound/midi/Gervill/ModelStandardTransform/TransformConvex.java ++javax/sound/midi/Gervill/ModelStandardTransform/TransformLinear.java ++javax/sound/midi/Gervill/ModelStandardTransform/TransformSwitch.java ++javax/sound/midi/Gervill/RiffReaderWriter/Available.java ++javax/sound/midi/Gervill/RiffReaderWriter/Close.java ++javax/sound/midi/Gervill/RiffReaderWriter/GetFilePointer.java ++javax/sound/midi/Gervill/RiffReaderWriter/GetSize.java ++javax/sound/midi/Gervill/RiffReaderWriter/HasNextChunk.java ++javax/sound/midi/Gervill/RiffReaderWriter/ReadByteArrayIntInt.java ++javax/sound/midi/Gervill/RiffReaderWriter/ReadByte.java ++javax/sound/midi/Gervill/RiffReaderWriter/ReadInt.java ++javax/sound/midi/Gervill/RiffReaderWriter/Read.java ++javax/sound/midi/Gervill/RiffReaderWriter/ReadLong.java ++javax/sound/midi/Gervill/RiffReaderWriter/ReadShort.java ++javax/sound/midi/Gervill/RiffReaderWriter/ReadString.java ++javax/sound/midi/Gervill/RiffReaderWriter/ReadUnsignedByte.java ++javax/sound/midi/Gervill/RiffReaderWriter/ReadUnsignedInt.java ++javax/sound/midi/Gervill/RiffReaderWriter/ReadUnsignedShort.java ++javax/sound/midi/Gervill/RiffReaderWriter/Skip.java ++javax/sound/midi/Gervill/RiffReaderWriter/WriteOutputStream.java ++javax/sound/midi/Gervill/SF2SoundbankReader/TestGetSoundbankFile.java ++javax/sound/midi/Gervill/SF2SoundbankReader/TestGetSoundbankInputStream2.java ++javax/sound/midi/Gervill/SF2SoundbankReader/TestGetSoundbankInputStream.java ++javax/sound/midi/Gervill/SF2SoundbankReader/TestGetSoundbankUrl.java ++javax/sound/midi/Gervill/SimpleInstrument/AddModelInstrumentIntIntIntIntInt.java ++javax/sound/midi/Gervill/SimpleInstrument/AddModelInstrumentIntIntIntInt.java ++javax/sound/midi/Gervill/SimpleInstrument/AddModelInstrumentIntInt.java ++javax/sound/midi/Gervill/SimpleInstrument/AddModelInstrument.java ++javax/sound/midi/Gervill/SimpleInstrument/AddModelPerformerArrayIntIntIntIntInt.java ++javax/sound/midi/Gervill/SimpleInstrument/AddModelPerformerArrayIntIntIntInt.java ++javax/sound/midi/Gervill/SimpleInstrument/AddModelPerformerArrayIntInt.java ++javax/sound/midi/Gervill/SimpleInstrument/AddModelPerformerArray.java ++javax/sound/midi/Gervill/SimpleInstrument/AddModelPerformerIntIntIntIntInt.java ++javax/sound/midi/Gervill/SimpleInstrument/AddModelPerformerIntIntIntInt.java ++javax/sound/midi/Gervill/SimpleInstrument/AddModelPerformerIntInt.java ++javax/sound/midi/Gervill/SimpleInstrument/AddModelPerformer.java ++javax/sound/midi/Gervill/SimpleInstrument/Clear.java ++javax/sound/midi/Gervill/SimpleInstrument/SetName.java ++javax/sound/midi/Gervill/SimpleInstrument/SetPatch.java ++javax/sound/midi/Gervill/SimpleSoundbank/AddInstrument.java ++javax/sound/midi/Gervill/SimpleSoundbank/AddResource.java ++javax/sound/midi/Gervill/SimpleSoundbank/GetInstrument.java ++javax/sound/midi/Gervill/SimpleSoundbank/RemoveInstrument.java ++javax/sound/midi/Gervill/SimpleSoundbank/SetDescription.java ++javax/sound/midi/Gervill/SimpleSoundbank/SetName.java ++javax/sound/midi/Gervill/SimpleSoundbank/SetVendor.java ++javax/sound/midi/Gervill/SimpleSoundbank/SetVersion.java ++javax/sound/midi/Gervill/SoftAudioBuffer/Array.java ++javax/sound/midi/Gervill/SoftAudioBuffer/Clear.java ++javax/sound/midi/Gervill/SoftAudioBuffer/Get.java ++javax/sound/midi/Gervill/SoftAudioBuffer/NewSoftAudioBuffer.java ++javax/sound/midi/Gervill/SoftAudioSynthesizer/GetFormat.java ++javax/sound/midi/Gervill/SoftAudioSynthesizer/GetPropertyInfo.java ++javax/sound/midi/Gervill/SoftAudioSynthesizer/Open.java ++javax/sound/midi/Gervill/SoftAudioSynthesizer/OpenStream.java ++javax/sound/midi/Gervill/SoftChannel/AllNotesOff.java ++javax/sound/midi/Gervill/SoftChannel/AllSoundOff.java ++javax/sound/midi/Gervill/SoftChannel/ChannelPressure.java ++javax/sound/midi/Gervill/SoftChannel/Controller.java ++javax/sound/midi/Gervill/SoftChannel/LocalControl.java ++javax/sound/midi/Gervill/SoftChannel/Mono.java ++javax/sound/midi/Gervill/SoftChannel/Mute.java ++javax/sound/midi/Gervill/SoftChannel/NoteOff2.java ++javax/sound/midi/Gervill/SoftChannel/NoteOff.java ++javax/sound/midi/Gervill/SoftChannel/NoteOn.java ++javax/sound/midi/Gervill/SoftChannel/NoteOverFlowTest2.java ++javax/sound/midi/Gervill/SoftChannel/NoteOverFlowTest.java ++javax/sound/midi/Gervill/SoftChannel/Omni.java ++javax/sound/midi/Gervill/SoftChannel/PitchBend.java ++javax/sound/midi/Gervill/SoftChannel/PolyPressure.java ++javax/sound/midi/Gervill/SoftChannel/ProgramAndBankChange.java ++javax/sound/midi/Gervill/SoftChannel/ProgramChange.java ++javax/sound/midi/Gervill/SoftChannel/ResetAllControllers.java ++javax/sound/midi/Gervill/SoftChannel/Solo.java ++javax/sound/midi/Gervill/SoftCubicResampler/Interpolate.java ++javax/sound/midi/Gervill/SoftFilter/TestProcessAudio.java ++javax/sound/midi/Gervill/SoftLanczosResampler/Interpolate.java ++javax/sound/midi/Gervill/SoftLimiter/ProcessAudio_replace_mix.java ++javax/sound/midi/Gervill/SoftLimiter/ProcessAudio_replace_mix_mono.java ++javax/sound/midi/Gervill/SoftLimiter/ProcessAudio_replace_mix_mono_overdrive.java ++javax/sound/midi/Gervill/SoftLimiter/ProcessAudio_replace_mix_overdrive.java ++javax/sound/midi/Gervill/SoftLimiter/ProcessAudio_replace_normal.java ++javax/sound/midi/Gervill/SoftLimiter/ProcessAudio_replace_normal_mono.java ++javax/sound/midi/Gervill/SoftLimiter/ProcessAudio_replace_overdrive.java ++javax/sound/midi/Gervill/SoftLimiter/ProcessAudio_replace_overdrive_mono.java ++javax/sound/midi/Gervill/SoftLinearResampler2/Interpolate.java ++javax/sound/midi/Gervill/SoftLinearResampler/Interpolate.java ++javax/sound/midi/Gervill/SoftLowFrequencyOscillator/TestProcessControlLogic.java ++javax/sound/midi/Gervill/SoftPointResampler/Interpolate.java ++javax/sound/midi/Gervill/SoftProvider/GetDevice.java ++javax/sound/midi/Gervill/SoftReceiver/Close.java ++javax/sound/midi/Gervill/SoftReceiver/GetMidiDevice.java ++javax/sound/midi/Gervill/SoftReceiver/Send_ActiveSense.java ++javax/sound/midi/Gervill/SoftReceiver/Send_AllNotesOff.java ++javax/sound/midi/Gervill/SoftReceiver/Send_AllSoundOff.java ++javax/sound/midi/Gervill/SoftReceiver/Send_ChannelPressure.java ++javax/sound/midi/Gervill/SoftReceiver/Send_Controller.java ++javax/sound/midi/Gervill/SoftReceiver/Send_Mono.java ++javax/sound/midi/Gervill/SoftReceiver/Send_NoteOff.java ++javax/sound/midi/Gervill/SoftReceiver/Send_NoteOn_AllChannels.java ++javax/sound/midi/Gervill/SoftReceiver/Send_NoteOn_Delayed.java ++javax/sound/midi/Gervill/SoftReceiver/Send_NoteOn.java ++javax/sound/midi/Gervill/SoftReceiver/Send_NoteOn_Multiple.java ++javax/sound/midi/Gervill/SoftReceiver/Send_Omni.java ++javax/sound/midi/Gervill/SoftReceiver/Send_PitchBend.java ++javax/sound/midi/Gervill/SoftReceiver/Send_PolyPressure.java ++javax/sound/midi/Gervill/SoftReceiver/Send_ProgramChange.java ++javax/sound/midi/Gervill/SoftReceiver/Send_ResetAllControllers.java ++javax/sound/midi/Gervill/SoftSincResampler/Interpolate.java ++javax/sound/midi/Gervill/SoftSynthesizer/Close.java ++javax/sound/midi/Gervill/SoftSynthesizer/GetAvailableInstruments2.java ++javax/sound/midi/Gervill/SoftSynthesizer/GetAvailableInstruments.java ++javax/sound/midi/Gervill/SoftSynthesizer/GetChannels.java ++javax/sound/midi/Gervill/SoftSynthesizer/GetDefaultSoundbank.java ++javax/sound/midi/Gervill/SoftSynthesizer/GetDeviceInfo.java ++javax/sound/midi/Gervill/SoftSynthesizer/GetLatency.java ++javax/sound/midi/Gervill/SoftSynthesizer/GetLoadedInstruments2.java ++javax/sound/midi/Gervill/SoftSynthesizer/GetLoadedInstruments.java ++javax/sound/midi/Gervill/SoftSynthesizer/GetMaxPolyphony.java ++javax/sound/midi/Gervill/SoftSynthesizer/GetMaxReceivers.java ++javax/sound/midi/Gervill/SoftSynthesizer/GetMaxTransmitters.java ++javax/sound/midi/Gervill/SoftSynthesizer/GetMicrosecondPosition.java ++javax/sound/midi/Gervill/SoftSynthesizer/GetPropertyInfo.java ++javax/sound/midi/Gervill/SoftSynthesizer/GetReceiver2.java ++javax/sound/midi/Gervill/SoftSynthesizer/GetReceiver.java ++javax/sound/midi/Gervill/SoftSynthesizer/GetReceivers.java ++javax/sound/midi/Gervill/SoftSynthesizer/GetTransmitter.java ++javax/sound/midi/Gervill/SoftSynthesizer/GetTransmitters.java ++javax/sound/midi/Gervill/SoftSynthesizer/GetVoiceStatus.java ++javax/sound/midi/Gervill/SoftSynthesizer/ImplicitOpenClose.java ++javax/sound/midi/Gervill/SoftSynthesizer/IsOpen.java ++javax/sound/midi/Gervill/SoftSynthesizer/IsSoundbankSupported.java ++javax/sound/midi/Gervill/SoftSynthesizer/LoadAllInstruments.java ++javax/sound/midi/Gervill/SoftSynthesizer/LoadInstrument.java ++javax/sound/midi/Gervill/SoftSynthesizer/LoadInstruments.java ++javax/sound/midi/Gervill/SoftSynthesizer/Open.java ++javax/sound/midi/Gervill/SoftSynthesizer/OpenStream.java ++javax/sound/midi/Gervill/SoftSynthesizer/RemapInstrument.java ++javax/sound/midi/Gervill/SoftSynthesizer/TestDisableLoadDefaultSoundbank.java ++javax/sound/midi/Gervill/SoftSynthesizer/TestPreciseTimestampRendering.java ++javax/sound/midi/Gervill/SoftSynthesizer/TestRender1.java ++javax/sound/midi/Gervill/SoftSynthesizer/UnloadAllInstruments.java ++javax/sound/midi/Gervill/SoftSynthesizer/UnloadInstrument.java ++javax/sound/midi/Gervill/SoftSynthesizer/UnloadInstruments.java ++javax/sound/midi/Gervill/SoftTuning/GetName.java ++javax/sound/midi/Gervill/SoftTuning/GetTuningInt.java ++javax/sound/midi/Gervill/SoftTuning/GetTuning.java ++javax/sound/midi/Gervill/SoftTuning/Load1.java ++javax/sound/midi/Gervill/SoftTuning/Load2.java ++javax/sound/midi/Gervill/SoftTuning/Load4.java ++javax/sound/midi/Gervill/SoftTuning/Load5.java ++javax/sound/midi/Gervill/SoftTuning/Load6.java ++javax/sound/midi/Gervill/SoftTuning/Load7.java ++javax/sound/midi/Gervill/SoftTuning/Load8.java ++javax/sound/midi/Gervill/SoftTuning/Load9.java ++javax/sound/midi/Gervill/SoftTuning/NewSoftTuningByteArray.java ++javax/sound/midi/Gervill/SoftTuning/NewSoftTuning.java ++javax/sound/midi/Gervill/SoftTuning/NewSoftTuningPatchByteArray.java ++javax/sound/midi/Gervill/SoftTuning/NewSoftTuningPatch.java ++javax/sound/midi/Gervill/SoftTuning/RealTimeTuning.java ++javax/sound/midi/MetaMessage/MetaMessageClone.java ++javax/sound/midi/MidiDeviceConnectors/TestAllDevices.java ++javax/sound/midi/MidiSystem/DefaultDevices.java ++javax/sound/midi/MidiSystem/DefaultProperties.java ++javax/sound/midi/MidiSystem/GetSequencer.java ++javax/sound/midi/MidiSystem/MidiFileTypeUniqueness.java ++javax/sound/midi/MidiSystem/ProviderCacheing.java ++javax/sound/midi/Sequence/GetMicrosecondLength.java ++javax/sound/midi/Sequence/MidiSMPTE.java ++javax/sound/midi/Sequencer/LoopIAE.java ++javax/sound/midi/Sequencer/Looping.java ++javax/sound/midi/Sequencer/MetaCallback.java ++javax/sound/midi/Sequencer/Recording.java ++javax/sound/midi/Sequencer/SeqRecordDoesNotCopy.java ++javax/sound/midi/Sequencer/SeqRecordsRealTimeEvents.java ++javax/sound/midi/Sequencer/SeqStartRecording.java ++javax/sound/midi/Sequencer/SequencerCacheValues.java ++javax/sound/midi/Sequencer/SequencerImplicitSynthOpen.java ++javax/sound/midi/Sequencer/SequencerSetMuteSolo.java ++javax/sound/midi/Sequencer/SequencerState.java ++javax/sound/midi/Sequencer/SetTickPosition.java ++javax/sound/midi/Sequencer/TickLength.java ++javax/sound/midi/Sequence/SMPTEDuration.java ++javax/sound/midi/ShortMessage/FastShortMessage2.java ++javax/sound/midi/ShortMessage/FastShortMessage.java ++javax/sound/midi/Soundbanks/ExtraCharInSoundbank.java ++javax/sound/midi/Soundbanks/GetSoundBankIOException.java ++javax/sound/midi/Synthesizer/AsynchronousMidiChannel.java ++javax/sound/midi/Synthesizer/bug4685396.java ++javax/sound/midi/Synthesizer/SynthesizerGetLatency.java ++javax/sound/midi/SysexMessage/SendRawSysexMessage.java ++javax/sound/midi/Track/bug6416024.java ++javax/sound/midi/Track/TrackAddSameTick.java ++javax/sound/midi/Transmitter/bug6415669.java ++javax/sound/sampled/AudioFileFormat/AudioFileFormatToString.java ++javax/sound/sampled/AudioFileFormat/Properties.java ++javax/sound/sampled/AudioFileFormat/TypeEquals.java ++javax/sound/sampled/AudioFormat/AudioFormatBitSize.java ++javax/sound/sampled/AudioFormat/EncodingEquals.java ++javax/sound/sampled/AudioFormat/Matches_NOT_SPECIFIED.java ++javax/sound/sampled/AudioFormat/PCM_FLOAT_support.java ++javax/sound/sampled/AudioFormat/Properties.java ++javax/sound/sampled/AudioInputStream/AISReadFraction.java ++javax/sound/sampled/AudioInputStream/bug6188860.java ++javax/sound/sampled/AudioSystem/AudioFileTypes/AudioFileTypeUniqueness.java ++javax/sound/sampled/AudioSystem/AudioFileTypes/ShowAudioFileTypes.java ++javax/sound/sampled/AudioSystem/DefaultMixers.java ++javax/sound/sampled/AudioSystem/DefaultProperties.java ++javax/sound/sampled/AudioSystem/ProviderCacheing.java ++javax/sound/sampled/Clip/AutoCloseTimeCheck.java ++javax/sound/sampled/Clip/bug5070081.java ++javax/sound/sampled/Clip/ClipCloseLoss.java ++javax/sound/sampled/Clip/ClipFlushCrash.java ++javax/sound/sampled/Clip/ClipIsRunningAfterStop.java ++javax/sound/sampled/Clip/ClipSetPos.java ++javax/sound/sampled/Clip/Drain/ClipDrain.java ++javax/sound/sampled/Clip/Duration/ClipDuration.java ++javax/sound/sampled/Clip/Endpoint/ClipSetEndPoint.java ++javax/sound/sampled/Clip/IsRunningHang.java ++javax/sound/sampled/Clip/Open/ClipOpenBug.java ++javax/sound/sampled/Controls/CompoundControl/ToString.java ++javax/sound/sampled/Controls/FloatControl/FloatControlBug.java ++javax/sound/sampled/DataLine/DataLine_ArrayIndexOutOfBounds.java ++javax/sound/sampled/DataLine/DataLineInfoNegBufferSize.java ++javax/sound/sampled/DataLine/LineDefFormat.java ++javax/sound/sampled/DataLine/LongFramePosition.java ++javax/sound/sampled/DirectAudio/bug6372428.java ++javax/sound/sampled/DirectAudio/bug6400879.java ++javax/sound/sampled/FileReader/ReadersExceptions.java ++javax/sound/sampled/FileTypeExtension/FileTypeExtensionTest.java ++javax/sound/sampled/FileWriter/AlawEncoderSync.java ++javax/sound/sampled/FileWriter/WriterCloseInput.java ++javax/sound/sampled/LineEvent/LineInfoNPE.java ++javax/sound/sampled/Lines/16and32KHz/Has16and32KHz.java ++javax/sound/sampled/Lines/BufferSizeCheck.java ++javax/sound/sampled/Lines/ChangingBuffer.java ++javax/sound/sampled/Lines/ClipOpenException.java ++javax/sound/sampled/Lines/FrameSize/FrameSizeTest.java ++javax/sound/sampled/Lines/GetLine.java ++javax/sound/sampled/Lines/SDLwrite.java ++javax/sound/sampled/Lines/SourceDataLineDefaultBufferSizeCrash.java ++javax/sound/sampled/Lines/StopStart.java ++javax/sound/sampled/LinuxCrash/ClipLinuxCrash2.java ++javax/sound/sampled/LinuxCrash/ClipLinuxCrash.java ++javax/sound/sampled/LinuxCrash/SDLLinuxCrash.java ++javax/sound/sampled/Mixers/BogusMixers.java ++javax/sound/sampled/Mixers/BothEndiansAndSigns.java ++javax/sound/sampled/Mixers/DisabledAssertionCrash.java ++javax/sound/sampled/Mixers/NoSimpleInputDevice.java ++javax/sound/sampled/Mixers/PlugHwMonoAnd8bitAvailable.java ++javax/sound/sampled/Mixers/UnexpectedIAE.java ++javax/sound/sampled/spi/AudioFileReader/Aiff12bit.java ++javax/sound/sampled/spi/AudioFileReader/AIFFCp037.java ++javax/sound/sampled/spi/AudioFileReader/AIFFLargeHeader.java ++javax/sound/sampled/spi/AudioFileReader/AuNotSpecified.java ++javax/sound/sampled/spi/AudioFileReader/AuZeroLength.java ++javax/sound/sampled/spi/AudioFileReader/OpenWaveFile.java ++javax/sound/sampled/spi/AudioFileWriter/AiffSampleRate.java ++javax/sound/sampled/spi/AudioFileWriter/AUwithULAW.java ++javax/sound/sampled/spi/AudioFileWriter/RIFFHeader.java ++javax/sound/sampled/spi/AudioFileWriter/WaveBigEndian.java ++javax/sound/sampled/spi/AudioFileWriter/WriteAuUnspecifiedLength.java ++javax/sound/sampled/spi/FormatConversionProvider/AlawUlaw.java ++javax/swing/AbstractButton/6711682/bug6711682.java ++javax/swing/AbstractButton/AnimatedIcon/AnimatedIcon.java ++javax/swing/AncestorNotifier/7193219/bug7193219.java ++javax/swing/border/Test4120351.java ++javax/swing/border/Test4124729.java ++javax/swing/border/Test4856008.java ++javax/swing/border/Test6461042.java ++javax/swing/border/Test6625450.java ++javax/swing/border/Test6978482.java ++javax/swing/border/Test6981576.java ++javax/swing/border/Test7022041.java ++javax/swing/border/Test7034614.java ++javax/swing/border/Test7149090.java ++javax/swing/DataTransfer/6456844/bug6456844.java ++javax/swing/DataTransfer/8059739/bug8059739.java ++javax/swing/dnd/7171812/bug7171812.java ++javax/swing/GroupLayout/6613904/bug6613904.java ++javax/swing/GroupLayout/7071166/bug7071166.java ++javax/swing/Headless/HeadlessAbstractSpinnerModel.java ++javax/swing/Headless/HeadlessBox_Filler.java ++javax/swing/Headless/HeadlessBox.java ++javax/swing/Headless/HeadlessCellRendererPane.java ++javax/swing/Headless/HeadlessDefaultListCellRenderer.java ++javax/swing/Headless/HeadlessDefaultListCellRenderer_UIResource.java ++javax/swing/Headless/HeadlessGrayFilter.java ++javax/swing/Headless/HeadlessJApplet.java ++javax/swing/Headless/HeadlessJButton.java ++javax/swing/Headless/HeadlessJCheckBox.java ++javax/swing/Headless/HeadlessJCheckBoxMenuItem.java ++javax/swing/Headless/HeadlessJColorChooser.java ++javax/swing/Headless/HeadlessJComboBox.java ++javax/swing/Headless/HeadlessJComponent.java ++javax/swing/Headless/HeadlessJDesktopPane.java ++javax/swing/Headless/HeadlessJDialog.java ++javax/swing/Headless/HeadlessJEditorPane.java ++javax/swing/Headless/HeadlessJFileChooser.java ++javax/swing/Headless/HeadlessJFormattedTextField.java ++javax/swing/Headless/HeadlessJFrame.java ++javax/swing/Headless/HeadlessJInternalFrame.java ++javax/swing/Headless/HeadlessJInternalFrame_JDesktopIcon.java ++javax/swing/Headless/HeadlessJLabel.java ++javax/swing/Headless/HeadlessJLayeredPane.java ++javax/swing/Headless/HeadlessJList.java ++javax/swing/Headless/HeadlessJMenuBar.java ++javax/swing/Headless/HeadlessJMenuItem.java ++javax/swing/Headless/HeadlessJMenu.java ++javax/swing/Headless/HeadlessJOptionPane.java ++javax/swing/Headless/HeadlessJPanel.java ++javax/swing/Headless/HeadlessJPasswordField.java ++javax/swing/Headless/HeadlessJPopupMenu.java ++javax/swing/Headless/HeadlessJPopupMenu_Separator.java ++javax/swing/Headless/HeadlessJProgressBar.java ++javax/swing/Headless/HeadlessJRadioButton.java ++javax/swing/Headless/HeadlessJRadioButtonMenuItem.java ++javax/swing/Headless/HeadlessJRootPane.java ++javax/swing/Headless/HeadlessJScrollBar.java ++javax/swing/Headless/HeadlessJScrollPane.java ++javax/swing/Headless/HeadlessJSeparator.java ++javax/swing/Headless/HeadlessJSlider.java ++javax/swing/Headless/HeadlessJSpinner.java ++javax/swing/Headless/HeadlessJSplitPane.java ++javax/swing/Headless/HeadlessJTabbedPane.java ++javax/swing/Headless/HeadlessJTable.java ++javax/swing/Headless/HeadlessJTextArea.java ++javax/swing/Headless/HeadlessJTextField.java ++javax/swing/Headless/HeadlessJTextPane.java ++javax/swing/Headless/HeadlessJToggleButton.java ++javax/swing/Headless/HeadlessJToolBar.java ++javax/swing/Headless/HeadlessJToolBar_Separator.java ++javax/swing/Headless/HeadlessJToolTip.java ++javax/swing/Headless/HeadlessJTree.java ++javax/swing/Headless/HeadlessJViewport.java ++javax/swing/Headless/HeadlessJWindow.java ++javax/swing/Headless/HeadlessLookAndFeel.java ++javax/swing/Headless/HeadlessMenuSelectionManager.java ++javax/swing/Headless/HeadlessOverlayLayout.java ++javax/swing/Headless/HeadlessPopupFactory.java ++javax/swing/Headless/HeadlessScrollPaneLayout.java ++javax/swing/Headless/HeadlessSizeRequirements.java ++javax/swing/Headless/HeadlessSizeSequence.java ++javax/swing/Headless/HeadlessSpinnerListModel.java ++javax/swing/Headless/HeadlessSpinnerNumberModel.java ++javax/swing/Headless/HeadlessTimer.java ++javax/swing/JButton/4368790/bug4368790.java ++javax/swing/JButton/6604281/bug6604281.java ++javax/swing/JButton/JButtonPaintNPE/JButtonPaintNPE.java ++javax/swing/JCheckBox/8032667/bug8032667_image_diff.java ++javax/swing/JColorChooser/Test4165217.java ++javax/swing/JColorChooser/Test4177735.java ++javax/swing/JColorChooser/Test4193384.java ++javax/swing/JColorChooser/Test4234761.java ++javax/swing/JColorChooser/Test4461329.java ++javax/swing/JColorChooser/Test4711996.java ++javax/swing/JColorChooser/Test6199676.java ++javax/swing/JColorChooser/Test6524757.java ++javax/swing/JColorChooser/Test6541987.java ++javax/swing/JColorChooser/Test6559154.java ++javax/swing/JColorChooser/Test6707406.java ++javax/swing/JColorChooser/Test6827032.java ++javax/swing/JColorChooser/Test7194184.java ++javax/swing/JComboBox/4199622/bug4199622.java ++javax/swing/JComboBox/4515752/DefaultButtonTest.java ++javax/swing/JComboBox/4523758/bug4523758.java ++javax/swing/JComboBox/4743225/bug4743225.java ++javax/swing/JComboBox/6236162/bug6236162.java ++javax/swing/JComboBox/6337518/bug6337518.java ++javax/swing/JComboBox/6406264/bug6406264.java ++javax/swing/JComboBox/6559152/bug6559152.java ++javax/swing/JComboBox/6607130/bug6607130.java ++javax/swing/JComboBox/6632953/bug6632953.java ++javax/swing/JComboBox/7031551/bug7031551.java ++javax/swing/JComboBox/7082443/bug7082443.java ++javax/swing/JComboBox/7195179/Test7195179.java ++javax/swing/JComboBox/8015300/Test8015300.java ++javax/swing/JComboBox/8019180/Test8019180.java ++javax/swing/JComboBox/8032878/bug8032878.java ++javax/swing/JComboBox/8033069/bug8033069NoScrollBar.java ++javax/swing/JComboBox/8033069/bug8033069ScrollBar.java ++javax/swing/JComboBox/8057893/bug8057893.java ++javax/swing/JComboBox/8072767/bug8072767.java ++javax/swing/JComboBox/8136998/bug8136998.java ++javax/swing/JComboBox/ConsumedKeyTest/ConsumedKeyTest.java ++javax/swing/JComboBox/ShowPopupAfterHidePopupTest/ShowPopupAfterHidePopupTest.java ++javax/swing/JComponent/4337267/bug4337267.java ++javax/swing/JComponent/6683775/bug6683775.java ++javax/swing/JComponent/6989617/bug6989617.java ++javax/swing/JComponent/7154030/bug7154030.java ++javax/swing/JComponent/8043610/bug8043610.java ++javax/swing/JDialog/6639507/bug6639507.java ++javax/swing/JDialog/WrongBackgroundColor/WrongBackgroundColor.java ++javax/swing/JEditorPane/4492274/bug4492274.java ++javax/swing/JEditorPane/6882559/bug6882559.java ++javax/swing/JEditorPane/6917744/bug6917744.java ++javax/swing/JEditorPane/8158734/bug8158734.java ++javax/swing/JEditorPane/8195095/ImageViewTest.java ++javax/swing/JEditorPane/bug4714674.java ++javax/swing/JFileChooser/4524490/bug4524490.java ++javax/swing/JFileChooser/4847375/bug4847375.java ++javax/swing/JFileChooser/6342301/bug6342301.java ++javax/swing/JFileChooser/6396844/TwentyThousandTest.java ++javax/swing/JFileChooser/6484091/bug6484091.java ++javax/swing/JFileChooser/6489130/bug6489130.java ++javax/swing/JFileChooser/6520101/bug6520101.java ++javax/swing/JFileChooser/6550546/bug6550546.java ++javax/swing/JFileChooser/6570445/bug6570445.java ++javax/swing/JFileChooser/6688203/bug6688203.java ++javax/swing/JFileChooser/6713352/bug6713352.java ++javax/swing/JFileChooser/6738668/bug6738668.java ++javax/swing/JFileChooser/6741890/bug6741890.java ++javax/swing/JFileChooser/6817933/Test6817933.java ++javax/swing/JFileChooser/6840086/bug6840086.java ++javax/swing/JFileChooser/6868611/bug6868611.java ++javax/swing/JFileChooser/6945316/bug6945316.java ++javax/swing/JFileChooser/7036025/bug7036025.java ++javax/swing/JFileChooser/7199708/bug7199708.java ++javax/swing/JFileChooser/8002077/bug8002077.java ++javax/swing/JFileChooser/8013442/Test8013442.java ++javax/swing/JFileChooser/8021253/bug8021253.java ++javax/swing/JFileChooser/8046391/bug8046391.java ++javax/swing/JFileChooser/8062561/bug8062561.java ++javax/swing/JFileChooser/8080628/bug8080628.java ++javax/swing/JFormattedTextField/Test6462562.java ++javax/swing/JFrame/4962534/bug4962534.html ++javax/swing/JFrame/8016356/bug8016356.java ++javax/swing/JFrame/8255880/RepaintOnFrameIconifiedStateChangeTest.java ++javax/swing/JFrame/AlwaysOnTop/AlwaysOnTopImeTest.java ++javax/swing/JFrame/HangNonVolatileBuffer/HangNonVolatileBuffer.java ++javax/swing/JFrame/NSTexturedJFrame/NSTexturedJFrame.java ++javax/swing/JInternalFrame/5066752/bug5066752.java ++javax/swing/JInternalFrame/6647340/bug6647340.java ++javax/swing/JInternalFrame/6725409/bug6725409.java ++javax/swing/JInternalFrame/8020708/bug8020708.java ++javax/swing/JInternalFrame/InternalFrameIsNotCollectedTest.java ++javax/swing/JInternalFrame/Test6325652.java ++javax/swing/JInternalFrame/Test6505027.java ++javax/swing/JInternalFrame/Test6802868.java ++javax/swing/JLabel/6501991/bug6501991.java ++javax/swing/JLabel/6596966/bug6596966.java ++javax/swing/JLabel/7004134/bug7004134.java ++javax/swing/JLayer/6824395/bug6824395.java ++javax/swing/JLayer/6872503/bug6872503.java ++javax/swing/JLayer/6875153/bug6875153.java ++javax/swing/JLayer/6875716/bug6875716.java ++javax/swing/JLayer/6994419/bug6994419.java ++javax/swing/JLayer/SerializationTest/SerializationTest.java ++javax/swing/JList/6462008/bug6462008.java ++javax/swing/JList/6510999/bug6510999.java ++javax/swing/JList/6823603/bug6823603.java ++javax/swing/JMenu/4417601/bug4417601.java ++javax/swing/JMenu/4515762/bug4515762.java ++javax/swing/JMenu/4692443/bug4692443.java ++javax/swing/JMenu/6359669/bug6359669.java ++javax/swing/JMenu/6470128/bug6470128.java ++javax/swing/JMenu/6538132/bug6538132.java ++javax/swing/JMenu/8071705/bug8071705.java ++javax/swing/JMenu/8072900/WrongSelectionOnMouseOver.java ++javax/swing/JMenuBar/4750590/bug4750590.java ++javax/swing/JMenuBar/MisplacedBorder/MisplacedBorder.java ++javax/swing/JMenuItem/4171437/bug4171437.java ++javax/swing/JMenuItem/4654927/bug4654927.java ++javax/swing/JMenuItem/6209975/bug6209975.java ++javax/swing/JMenuItem/6249972/bug6249972.java ++javax/swing/JMenuItem/6438430/bug6438430.java ++javax/swing/JMenuItem/6883341/bug6883341.java ++javax/swing/JMenuItem/7036148/bug7036148.java ++javax/swing/JMenuItem/ActionListenerCalledTwice/ActionListenerCalledTwiceTest.java ++javax/swing/JMenu/JMenuSelectedColorTest.java ++javax/swing/JOptionPane/6428694/bug6428694.java ++javax/swing/JOptionPane/6464022/bug6464022.java ++javax/swing/JOptionPane/7138665/bug7138665.java ++javax/swing/JPopupMenu/4458079/bug4458079.java ++javax/swing/JPopupMenu/4634626/bug4634626.java ++javax/swing/JPopupMenu/4966112/bug4966112.java ++javax/swing/JPopupMenu/6217905/bug6217905.java ++javax/swing/JPopupMenu/6415145/bug6415145.java ++javax/swing/JPopupMenu/6495920/bug6495920.java ++javax/swing/JPopupMenu/6515446/bug6515446.java ++javax/swing/JPopupMenu/6544309/bug6544309.java ++javax/swing/JPopupMenu/6580930/bug6580930.java ++javax/swing/JPopupMenu/6583251/bug6583251.java ++javax/swing/JPopupMenu/6675802/bug6675802.java ++javax/swing/JPopupMenu/6690791/bug6690791.java ++javax/swing/JPopupMenu/6691503/bug6691503.java ++javax/swing/JPopupMenu/6694823/bug6694823.java ++javax/swing/JPopupMenu/6800513/bug6800513.java ++javax/swing/JPopupMenu/6827786/bug6827786.java ++javax/swing/JPopupMenu/6987844/bug6987844.java ++javax/swing/JPopupMenu/7154841/bug7154841.java ++javax/swing/JPopupMenu/7156657/bug7156657.java ++javax/swing/JPopupMenu/Separator/6547087/bug6547087.java ++javax/swing/JProgressBar/7141573/bug7141573.java ++javax/swing/JProgressBar/8161664/ProgressBarMemoryLeakTest.java ++javax/swing/JRadioButton/8033699/bug8033699.java ++javax/swing/JRadioButton/8041561/bug8041561.java ++javax/swing/JRadioButton/8075609/bug8075609.java ++javax/swing/JRootPane/4670486/bug4670486.java ++javax/swing/JScrollBar/4708809/bug4708809.java ++javax/swing/JScrollBar/4865918/bug4865918.java ++javax/swing/JScrollBar/6542335/bug6542335.java ++javax/swing/JScrollBar/6924059/bug6924059.java ++javax/swing/JScrollBar/7163696/Test7163696.java ++javax/swing/JScrollBar/bug4202954/bug4202954.java ++javax/swing/JScrollPane/6274267/bug6274267.java ++javax/swing/JScrollPane/6559589/bug6559589.java ++javax/swing/JScrollPane/6612531/bug6612531.java ++javax/swing/JScrollPane/HorizontalMouseWheelOnShiftPressed/HorizontalMouseWheelOnShiftPressed.java ++javax/swing/JScrollPane/Test6526631.java ++javax/swing/JSlider/4252173/bug4252173.java ++javax/swing/JSlider/6278700/bug6278700.java ++javax/swing/JSlider/6348946/bug6348946.java ++javax/swing/JSlider/6401380/bug6401380.java ++javax/swing/JSlider/6579827/bug6579827.java ++javax/swing/JSlider/6794831/bug6794831.java ++javax/swing/JSlider/6794836/bug6794836.java ++javax/swing/JSlider/6848475/bug6848475.java ++javax/swing/JSlider/6918861/bug6918861.java ++javax/swing/JSlider/6923305/bug6923305.java ++javax/swing/JSpinner/4973721/bug4973721.java ++javax/swing/JSpinner/5012888/bug5012888.java ++javax/swing/JSpinner/6463712/bug6463712.java ++javax/swing/JSpinner/6532833/bug6532833.java ++javax/swing/JSpinner/8008657/bug8008657.java ++javax/swing/JSplitPane/4201995/bug4201995.java ++javax/swing/JSplitPane/4816114/bug4816114.java ++javax/swing/JSplitPane/4885629/bug4885629.java ++javax/swing/JTabbedPane/4361477/bug4361477.java ++javax/swing/JTabbedPane/4624207/bug4624207.java ++javax/swing/JTabbedPane/6416920/bug6416920.java ++javax/swing/JTabbedPane/6495408/bug6495408.java ++javax/swing/JTabbedPane/6670274/bug6670274.java ++javax/swing/JTabbedPane/7010561/bug7010561.java ++javax/swing/JTabbedPane/7024235/Test7024235.java ++javax/swing/JTabbedPane/7161568/bug7161568.java ++javax/swing/JTabbedPane/7170310/bug7170310.java ++javax/swing/JTabbedPane/8007563/Test8007563.java ++javax/swing/JTable/4220171/bug4220171.java ++javax/swing/JTable/4235420/bug4235420.java ++javax/swing/JTable/6263446/bug6263446.java ++javax/swing/JTable/6735286/bug6735286.java ++javax/swing/JTable/6768387/bug6768387.java ++javax/swing/JTable/6777378/bug6777378.java ++javax/swing/JTable/6788484/bug6788484.java ++javax/swing/JTable/6913768/bug6913768.java ++javax/swing/JTable/6937798/bug6937798.java ++javax/swing/JTable/7027139/bug7027139.java ++javax/swing/JTable/7055065/bug7055065.java ++javax/swing/JTable/7068740/bug7068740.java ++javax/swing/JTable/7188612/JTableAccessibleGetLocationOnScreen.java ++javax/swing/JTable/8005019/bug8005019.java ++javax/swing/JTable/8031971/bug8031971.java ++javax/swing/JTable/8032874/bug8032874.java ++javax/swing/JTableHeader/6884066/bug6884066.java ++javax/swing/JTableHeader/6889007/bug6889007.java ++javax/swing/JTable/Test6888156.java ++javax/swing/JTextArea/4697612/bug4697612.java ++javax/swing/JTextArea/6925473/bug6925473.java ++javax/swing/JTextArea/6940863/bug6940863.java ++javax/swing/JTextArea/7049024/bug7049024.java ++javax/swing/JTextArea/Test6593649.java ++javax/swing/JTextArea/TextViewOOM/TextViewOOM.java ++javax/swing/JTextField/8036819/bug8036819.java ++javax/swing/JTextField/I18NViewNoWrapMinSpan/I18NViewNoWrapMinSpan.java ++javax/swing/JTextPane/JTextPaneDocumentAlignment.java ++javax/swing/JTextPane/JTextPaneDocumentWrapping.java ++javax/swing/JToolBar/4247996/bug4247996.java ++javax/swing/JToolBar/4529206/bug4529206.java ++javax/swing/JToolTip/4846413/bug4846413.java ++javax/swing/JTree/4330357/bug4330357.java ++javax/swing/JTree/4633594/JTreeFocusTest.java ++javax/swing/JTree/4908142/bug4908142.java ++javax/swing/JTree/4927934/bug4927934.java ++javax/swing/JTree/6263446/bug6263446.java ++javax/swing/JTree/6505523/bug6505523.java ++javax/swing/JTree/6578666/bug6578666.java ++javax/swing/JTree/8003400/Test8003400.java ++javax/swing/JTree/8003830/bug8003830.java ++javax/swing/JTree/8004298/bug8004298.java ++javax/swing/JTree/8013571/Test8013571.java ++javax/swing/JTree/8072676/TreeClipTest.java ++javax/swing/JViewport/6953396/bug6953396.java ++javax/swing/JViewport/7107099/bug7107099.java ++javax/swing/JWindow/ShapedAndTranslucentWindows/PerPixelTranslucentCanvas.java ++javax/swing/JWindow/ShapedAndTranslucentWindows/PerPixelTranslucentGradient.java ++javax/swing/JWindow/ShapedAndTranslucentWindows/PerPixelTranslucent.java ++javax/swing/JWindow/ShapedAndTranslucentWindows/PerPixelTranslucentSwing.java ++javax/swing/JWindow/ShapedAndTranslucentWindows/SetShapeAndClickSwing.java ++javax/swing/JWindow/ShapedAndTranslucentWindows/ShapedPerPixelTranslucentGradient.java ++javax/swing/JWindow/ShapedAndTranslucentWindows/ShapedTranslucentPerPixelTranslucentGradient.java ++javax/swing/JWindow/ShapedAndTranslucentWindows/TranslucentJComboBox.java ++javax/swing/JWindow/ShapedAndTranslucentWindows/TranslucentPerPixelTranslucentGradient.java ++javax/swing/JWindow/ShapedAndTranslucentWindows/TranslucentWindowClickSwing.java ++javax/swing/KeyboardManager/8013370/Test8013370.java ++javax/swing/LookAndFeel/6474153/bug6474153.java ++javax/swing/LookAndFeel/8145547/DemandGTK2.sh ++javax/swing/LookAndFeel/8145547/DemandGTK3.sh ++javax/swing/LookAndFeel/8145547/DemandGTK.java ++javax/swing/MultiUIDefaults/4300666/bug4300666.java ++javax/swing/MultiUIDefaults/4331767/bug4331767.java ++javax/swing/MultiUIDefaults/Test6860438.java ++javax/swing/plaf/aqua/CustomComboBoxFocusTest.java ++javax/swing/plaf/basic/BasicComboBoxEditor/Test8015336.java ++javax/swing/plaf/basic/BasicComboPopup/8154069/Bug8154069.java ++javax/swing/plaf/basic/BasicHTML/4251579/bug4251579.java ++javax/swing/plaf/basic/BasicLabelUI/bug7172652.java ++javax/swing/plaf/basic/BasicMenuUI/4983388/bug4983388.java ++javax/swing/plaf/basic/BasicScrollPaneUI/Test6632810.java ++javax/swing/plaf/basic/BasicSplitPaneUI/Test6657026.java ++javax/swing/plaf/basic/BasicTabbedPaneUI/Test6943780.java ++javax/swing/plaf/basic/BasicTreeUI/8023474/bug8023474.java ++javax/swing/plaf/basic/Test6984643.java ++javax/swing/plaf/gtk/crash/RenderBadPictureCrash.java ++javax/swing/plaf/metal/MetalBorders/Test6657026.java ++javax/swing/plaf/metal/MetalBumps/Test6657026.java ++javax/swing/plaf/metal/MetalInternalFrameUI/Test6657026.java ++javax/swing/plaf/metal/MetalLookAndFeel/5073047/bug5073047.java ++javax/swing/plaf/metal/MetalLookAndFeel/Test8039750.java ++javax/swing/plaf/metal/MetalSliderUI/Test6657026.java ++javax/swing/plaf/nimbus/8041642/bug8041642.java ++javax/swing/plaf/nimbus/8041642/ScrollBarThumbVisibleTest.java ++javax/swing/plaf/nimbus/8041725/bug8041725.java ++javax/swing/plaf/nimbus/8057791/bug8057791.java ++javax/swing/plaf/nimbus/ColorCustomizationTest.java ++javax/swing/plaf/nimbus/Test6741426.java ++javax/swing/plaf/nimbus/Test6849805.java ++javax/swing/plaf/nimbus/Test6919629.java ++javax/swing/plaf/nimbus/Test7048204.java ++javax/swing/plaf/synth/6771547/SynthTest.java ++javax/swing/plaf/synth/7032791/bug7032791.java ++javax/swing/plaf/synth/7143614/bug7143614.java ++javax/swing/plaf/synth/7158712/bug7158712.java ++javax/swing/plaf/synth/SynthButtonUI/6276188/bug6276188.java ++javax/swing/plaf/synth/SynthToolBarUI/6739756/bug6739756.java ++javax/swing/plaf/synth/Test6660049.java ++javax/swing/plaf/synth/Test6933784.java ++javax/swing/plaf/synth/Test8015926.java ++javax/swing/plaf/synth/Test8043627.java ++javax/swing/plaf/windows/WindowsRootPaneUI/WrongAltProcessing/WrongAltProcessing.java ++javax/swing/Popup/6514582/bug6514582.java ++javax/swing/PopupFactory/6276087/NonOpaquePopupMenuTest.java ++javax/swing/PopupFactory/8048506/bug8048506.java ++javax/swing/Popup/TaskbarPositionTest.java ++javax/swing/reliability/TaskUndJFrameProperties.java ++javax/swing/reliability/TaskZoomJFrameChangeState.java ++javax/swing/reliability/TaskZoomJFrameRepaint.java ++javax/swing/RepaintManager/6608456/bug6608456.java ++javax/swing/RepaintManager/7013453/bug7013453.java ++javax/swing/RepaintManager/DisplayListenerLeak/DisplayListenerLeak.java ++javax/swing/RepaintManager/IconifyTest/IconifyTest.java ++javax/swing/Security/6657138/bug6657138.java ++javax/swing/Security/6657138/ComponentTest.java ++javax/swing/Security/6938813/bug6938813.java ++javax/swing/SpringLayout/4726194/bug4726194.java ++javax/swing/SwingUtilities/4917669/bug4917669.java ++javax/swing/SwingUtilities/6797139/bug6797139.java ++javax/swing/SwingUtilities/7088744/bug7088744.java ++javax/swing/SwingUtilities/7146377/bug7146377.java ++javax/swing/SwingUtilities/7170657/bug7170657.java ++javax/swing/SwingUtilities/8032219/DrawRect.java ++javax/swing/SwingUtilities/TestBadBreak/TestBadBreak.java ++javax/swing/SwingWorker/6432565/bug6432565.java ++javax/swing/SwingWorker/6493680/bug6493680.java ++javax/swing/SwingWorker/6880336/NestedWorkers.java ++javax/swing/system/6799345/TestShutdown.java ++javax/swing/text/AbstractDocument/6968363/Test6968363.java ++javax/swing/text/AbstractDocument/8030118/Test8030118.java ++javax/swing/text/CSSBorder/6796710/bug6796710.java ++javax/swing/text/DefaultCaret/6938583/bug6938583.java ++javax/swing/text/DefaultCaret/7083457/bug7083457.java ++javax/swing/text/DefaultEditorKit/4278839/bug4278839.java ++javax/swing/text/DefaultHighlighter/6771184/bug6771184.java ++javax/swing/text/DefaultStyledDocument/6636983/bug6636983.java ++javax/swing/text/FlowView/LayoutTest.java ++javax/swing/text/html/7189299/bug7189299.java ++javax/swing/text/html/8005391/bug8005391.java ++javax/swing/text/html/8034955/bug8034955.java ++javax/swing/text/html/8218674/TooltipImageTest.java ++javax/swing/text/html/CSS/4530474/bug4530474.java ++javax/swing/text/html/HRuleView/Test5062055.java ++javax/swing/text/html/HTMLDocument/8058120/bug8058120.java ++javax/swing/text/html/HTMLEditorKit/4242228/bug4242228.java ++javax/swing/text/html/HTMLEditorKit/5043626/bug5043626.java ++javax/swing/text/html/parser/8074956/bug8074956.java ++javax/swing/text/html/parser/Parser/6836089/bug6836089.java ++javax/swing/text/html/parser/Parser/6990651/bug6990651.java ++javax/swing/text/html/parser/Parser/7003777/bug7003777.java ++javax/swing/text/html/parser/Parser/7011777/bug7011777.java ++javax/swing/text/html/parser/Parser/7165725/bug7165725.java ++javax/swing/text/html/parser/Parser/8028616/bug8028616.java ++javax/swing/text/html/parser/Parser/8078268/bug8078268.java ++javax/swing/text/html/parser/Parser/HtmlCommentTagParseTest/HtmlCommentTagParseTest.java ++javax/swing/text/html/parser/Test8017492.java ++javax/swing/text/html/Test4783068.java ++javax/swing/text/html/TestJLabelWithHTMLText.java ++javax/swing/text/JTextComponent/5074573/bug5074573.java ++javax/swing/text/LayoutQueue/Test6588003.java ++javax/swing/text/NavigationFilter/6735293/bug6735293.java ++javax/swing/text/StyledEditorKit/4506788/bug4506788.java ++javax/swing/text/StyledEditorKit/8016833/bug8016833.java ++javax/swing/text/Utilities/bug7045593.java ++javax/swing/text/View/8014863/bug8014863.java ++javax/swing/text/View/8015853/bug8015853.java ++javax/swing/text/View/8048110/bug8048110.java ++javax/swing/text/WrappedPlainView/6857057/bug6857057.java ++javax/swing/ToolTipManager/7123767/bug7123767.java ++javax/swing/ToolTipManager/Test6256140.java ++javax/swing/ToolTipManager/Test6657026.java ++javax/swing/tree/DefaultTreeCellRenderer/7142955/bug7142955.java ++javax/swing/UIDefaults/6622002/bug6622002.java ++javax/swing/UIDefaults/6795356/bug6795356.java ++javax/swing/UIDefaults/6795356/SwingLazyValueTest.java ++javax/swing/UIDefaults/6795356/TableTest.java ++javax/swing/UIDefaults/7180976/Pending.java ++javax/swing/UIManager/Test6657026.java ++javax/swing/UITest/UITest.java ++sun/awt/AppContext/8012933/Test8012933.java ++sun/awt/AppContext/MultiThread/MultiThreadTest.java ++sun/awt/datatransfer/DataFlavorComparatorTest1.java ++sun/awt/datatransfer/DataFlavorComparatorTest.java ++sun/awt/datatransfer/SuplementaryCharactersTransferTest.java ++sun/awt/dnd/8024061/bug8024061.java ++sun/awt/font/ClassLoaderLeakTest.java ++sun/awt/image/bug8038000.java ++sun/awt/image/DrawByteBinary.java ++sun/awt/image/ImageRepresentation/LUTCompareTest.java ++sun/awt/image/ImageWatched/AddNoLeak.java ++sun/awt/image/ImagingLib/SamePackingTypeTest.java ++sun/java2d/AcceleratedXORModeTest.java ++sun/java2d/ClassCastExceptionForInvalidSurface.java ++sun/java2d/cmm/ColorConvertOp/AlphaTest.java ++sun/java2d/cmm/ColorConvertOp/ColConvCCMTest.java ++sun/java2d/cmm/ColorConvertOp/ColConvDCMTest.java ++sun/java2d/cmm/ColorConvertOp/ColCvtAlpha.java ++sun/java2d/cmm/ColorConvertOp/ColCvtIntARGB.java ++sun/java2d/cmm/ColorConvertOp/ColorConvertTest.java ++sun/java2d/cmm/ColorConvertOp/ColorSpaceCvtCrashTest/ColorSpaceCvtCrashTest.java ++sun/java2d/cmm/ColorConvertOp/ConstructorsNullTest/ConstructorsNullTest.html ++sun/java2d/cmm/ColorConvertOp/GrayTest.java ++sun/java2d/cmm/ColorConvertOp/InvalidRenderIntentTest.java ++sun/java2d/cmm/ColorConvertOp/MTColConvTest.java ++sun/java2d/cmm/ColorConvertOp/MTSafetyTest.java ++sun/java2d/cmm/ColorConvertOp/RGBColorConvertTest.java ++sun/java2d/cmm/ProfileOp/DisposalCrashTest.java ++sun/java2d/cmm/ProfileOp/MTReadProfileTest.java ++sun/java2d/cmm/ProfileOp/ReadProfileTest.java ++sun/java2d/cmm/ProfileOp/ReadWriteProfileTest.java ++sun/java2d/cmm/ProfileOp/SetDataTest.java ++sun/java2d/DirectX/AcceleratedScaleTest/AcceleratedScaleTest.java ++sun/java2d/DirectX/AccelPaintsTest/AccelPaintsTest.java ++sun/java2d/DirectX/DrawBitmaskToSurfaceTest.java ++sun/java2d/DirectX/IAEforEmptyFrameTest/IAEforEmptyFrameTest.java ++sun/java2d/DirectX/InfiniteValidationLoopTest/InfiniteValidationLoopTest.java ++sun/java2d/DirectX/OnScreenRenderingResizeTest/OnScreenRenderingResizeTest.java ++sun/java2d/DirectX/OpaqueImageToSurfaceBlitTest/OpaqueImageToSurfaceBlitTest.java ++sun/java2d/DirectX/OverriddenInsetsTest/OverriddenInsetsTest.java ++sun/java2d/DirectX/RenderingToCachedGraphicsTest/RenderingToCachedGraphicsTest.java ++sun/java2d/DirectX/StrikeDisposalCrashTest/StrikeDisposalCrashTest.java ++sun/java2d/DirectX/SwingOnScreenScrollingTest/SwingOnScreenScrollingTest.java ++sun/java2d/DirectX/TransformedPaintTest/TransformedPaintTest.java ++sun/java2d/DrawCachedImageAndTransform.java ++sun/java2d/DrawXORModeTest.java ++sun/java2d/GdiRendering/InsetClipping.java ++sun/java2d/loops/Bug7049339.java ++sun/java2d/loops/RenderToCustomBufferTest.java ++sun/java2d/marlin/ArrayCacheSizeTest.java ++sun/java2d/marlin/CeilAndFloorTests.java ++sun/java2d/marlin/CrashNaNTest.java ++sun/java2d/marlin/CrashPaintTest.java ++sun/java2d/marlin/CrashTest.java ++sun/java2d/marlin/DefaultRenderingEngine.java ++sun/java2d/marlin/TextClipErrorTest.java ++sun/java2d/OpenGL/bug7181438.java ++sun/java2d/OpenGL/CopyAreaOOB.java ++sun/java2d/OpenGL/CustomCompositeTest.java ++sun/java2d/OpenGL/DrawBufImgOp.java ++sun/java2d/OpenGL/DrawHugeImageTest.java ++sun/java2d/OpenGL/GradientPaints.java ++sun/java2d/pipe/hw/RSLAPITest/RSLAPITest.java ++sun/java2d/pipe/hw/RSLContextInvalidationTest/RSLContextInvalidationTest.java ++sun/java2d/pipe/InterpolationQualityTest.java ++sun/java2d/pipe/MutableColorTest/MutableColorTest.java ++sun/java2d/pipe/RegionOps.java ++sun/java2d/pipe/Test7027667.java ++sun/java2d/pipe/Test8004821.java ++sun/java2d/pisces/Renderer/Test7019861.java ++sun/java2d/pisces/Renderer/TestNPE.java ++sun/java2d/pisces/Test7036754.java ++sun/java2d/SunGraphics2D/DrawImageBilinear.java ++sun/java2d/SunGraphics2D/EmptyClipRenderingTest.java ++sun/java2d/SunGraphics2D/PolyVertTest.java ++sun/java2d/SunGraphics2D/SimplePrimQuality.java ++sun/java2d/SunGraphics2D/SourceClippingBlitTest/SourceClippingBlitTest.java ++sun/java2d/SunGraphicsEnvironment/TestSGEuseAlternateFontforJALocales.java ++sun/java2d/X11SurfaceData/DrawImageBgTest/DrawImageBgTest.java ++sun/java2d/X11SurfaceData/SharedMemoryPixmapsTest/SharedMemoryPixmapsTest.sh ++sun/java2d/XRenderBlitsTest.java ++sun/security/provider/SeedGenerator/Awt_Hang_Test.java ++ ++#x86 also failed ++ ++runtime/6929067/Test6929067.sh ++runtime/InitialThreadOverflow/testme.sh ++runtime/classFileParserBug/TestEmptyBootstrapMethodsAttr.java ++com/sun/jdi/JdbReadTwiceTest.sh ++com/sun/jndi/ldap/LdapDnsProviderTest.java ++com/sun/management/DiagnosticCommandMBean/DcmdMBeanPermissionsTest.java ++java/beans/Introspector/7064279/Test7064279.java ++java/beans/Introspector/Test7172865.java ++java/beans/Introspector/Test7195106.java ++java/net/InetAddress/IsReachableViaLoopbackTest.java ++java/net/InetAddress/getOriginalHostName.java ++java/nio/file/Files/probeContentType/ForceLoad.java ++java/nio/file/Files/probeContentType/ParallelProbes.java ++java/rmi/transport/rapidExportUnexport/RapidExportUnexport.java ++java/security/KeyStore/PKCS12/KeytoolReaderP12Test.java ++java/security/cert/CertPathBuilder/akiExt/AKISerialNumber.java ++java/security/cert/CertPathBuilder/targetConstraints/BuildEEBasicConstraints.java ++java/security/cert/pkix/policyChanges/TestPolicy.java ++java/text/BreakIterator/BreakIteratorTest.java ++java/util/logging/LocalizedLevelName.java ++java/util/logging/SimpleFormatterFormat.java ++javax/management/remote/mandatory/connection/RMIConnector_NPETest.java ++javax/net/ssl/SSLSession/CheckMyTrustedKeystore.java ++javax/print/CheckDupFlavor.java ++javax/print/attribute/AttributeTest.java ++javax/print/attribute/GetCopiesSupported.java ++javax/print/attribute/SidesPageRangesTest.java ++javax/print/attribute/SupportedPrintableAreas.java ++javax/security/auth/login/JAASConfigSyntaxCheck/JAASConfigSyntaxTest.java ++javax/security/auth/login/LoginContext/DynamicConfigurationTest.java ++javax/xml/bind/jxc/8073519/SchemagenErrorReporting.java ++security/infra/java/security/cert/CertPathValidator/certification/ActalisCA.java ++security/infra/java/security/cert/CertPathValidator/certification/AmazonCA.java ++security/infra/java/security/cert/CertPathValidator/certification/BuypassCA.java ++security/infra/java/security/cert/CertPathValidator/certification/ComodoCA.java ++security/infra/java/security/cert/CertPathValidator/certification/DTrustCA.java ++security/infra/java/security/cert/CertPathValidator/certification/EntrustCA.java ++security/infra/java/security/cert/CertPathValidator/certification/GlobalSignR6CA.java ++security/infra/java/security/cert/CertPathValidator/certification/GoDaddyCA.java ++security/infra/java/security/cert/CertPathValidator/certification/HaricaCA.java ++security/infra/java/security/cert/CertPathValidator/certification/LuxTrustCA.java ++security/infra/java/security/cert/CertPathValidator/certification/QuoVadisCA.java ++security/infra/java/security/cert/CertPathValidator/certification/SSLCA.java ++security/infra/java/security/cert/CertPathValidator/certification/TeliaSoneraCA.java ++sun/management/jmxremote/startstop/JMXStartStopTest.java ++sun/rmi/transport/proxy/EagerHttpFallback.java ++sun/security/krb5/auto/ReplayCacheTestProc.java ++sun/security/lib/cacerts/VerifyCACerts.java ++sun/security/ssl/X509TrustManagerImpl/Symantec/Distrust.java ++sun/security/tools/jarsigner/TsacertOptionTest.java ++sun/security/tools/jarsigner/warnings/AliasNotInStoreTest.java ++sun/security/tools/jarsigner/warnings/BadExtendedKeyUsageTest.java ++sun/security/tools/jarsigner/warnings/BadNetscapeCertTypeTest.java ++sun/security/tools/jarsigner/warnings/ChainNotValidatedTest.java ++sun/security/tools/jarsigner/warnings/HasExpiredCertTest.java ++sun/security/tools/jarsigner/warnings/HasExpiringCertTest.java ++sun/security/tools/jarsigner/warnings/HasUnsignedEntryTest.java ++sun/security/tools/jarsigner/warnings/MultipleWarningsTest.java ++sun/security/tools/jarsigner/warnings/NoTimestampTest.java ++sun/security/tools/jarsigner/warnings/NotSignedByAliasTest.java ++sun/security/tools/jarsigner/warnings/NotYetValidCertTest.java ++sun/security/tools/jarsigner/weaksize.sh ++sun/tools/jps/TestJpsJarRelative.java ++sun/tools/native2ascii/NativeErrors.java ++sun/util/logging/SourceClassName.java ++tools/launcher/TestSpecialArgs.java ++vmTestbase/nsk/jdb/monitor/monitor002/monitor002.java ++com/sun/crypto/provider/Cipher/DES/PerformanceTest.java ++com/sun/jdi/ArrayLengthDumpTest.sh ++com/sun/jdi/BreakpointWithFullGC.sh ++com/sun/jdi/CatchAllTest.sh ++com/sun/jdi/CatchCaughtTest.sh ++com/sun/jdi/CatchPatternTest.sh ++com/sun/jdi/CommandCommentDelimiter.sh ++com/sun/jdi/DeoptimizeWalk.sh ++com/sun/jdi/EvalArgs.sh ++com/sun/jdi/EvalArraysAsList.sh ++com/sun/jdi/EvalInterfaceStatic.sh ++com/sun/jdi/GetLocalVariables3Test.sh ++com/sun/jdi/GetLocalVariables4Test.sh ++com/sun/jdi/JdbLockTest.sh ++com/sun/jdi/JdbMethodExitTest.sh ++com/sun/jdi/JdbMissStep.sh ++com/sun/jdi/JdbVarargsTest.sh ++com/sun/jdi/MixedSuspendTest.sh ++com/sun/jdi/NotAField.sh ++com/sun/jdi/NullLocalVariable.sh ++com/sun/jdi/PopAndInvokeTest.java ++com/sun/jdi/Redefine-g.sh ++com/sun/jdi/RedefineAbstractClass.sh ++com/sun/jdi/RedefineAddPrivateMethod.sh ++com/sun/jdi/RedefineAnnotation.sh ++com/sun/jdi/RedefineChangeClassOrder.sh ++com/sun/jdi/RedefineClasses.sh ++com/sun/jdi/RedefineClearBreakpoint.sh ++com/sun/jdi/RedefineException.sh ++com/sun/jdi/RedefineFinal.sh ++com/sun/jdi/RedefineImplementor.sh ++com/sun/jdi/RedefineIntConstantToLong.sh ++com/sun/jdi/RedefineMulti.sh ++com/sun/jdi/RedefinePop.sh ++com/sun/jdi/RedefineStep.sh ++com/sun/jdi/RedefineTTYLineNumber.sh ++com/sun/jdi/StringConvertTest.sh ++com/sun/jdi/WatchFramePop.sh ++com/sun/security/auth/callback/DialogCallbackHandler/Default.java ++com/sun/security/auth/callback/TextCallbackHandler/Default.java ++com/sun/security/auth/callback/TextCallbackHandler/Password.java ++com/sun/security/sasl/gsskerb/AuthOnly.java ++com/sun/security/sasl/gsskerb/ConfSecurityLayer.java ++com/sun/security/sasl/gsskerb/NoSecurityLayer.java ++com/sun/tracing/BasicFunctionality.java ++java/io/ByteArrayOutputStream/MaxCapacity.java ++java/io/CharArrayReader/OverflowInRead.java ++java/io/File/GetXSpace.java ++java/io/IOException/LastErrorString.java ++java/io/StringBufferInputStream/OverflowInRead.java ++java/io/SystemInAvailable.java ++java/lang/StringBuilder/HugeCapacity.java ++java/lang/instrument/ParallelTransformerLoader.sh ++java/lang/invoke/LFCaching/LFGarbageCollectedTest.java ++java/nio/channels/FileChannel/FileExtensionAndMap.java ++java/util/AbstractList/CheckForComodification.java ++java/util/ResourceBundle/RestrictedBundleTest.java ++java/util/ResourceBundle/Test4300693.java ++java/util/WeakHashMap/GCDuringIteration.java ++java/util/zip/3GBZipFiles.sh ++javax/net/ssl/SSLEngine/Basics.java ++javax/net/ssl/SSLEngine/CheckStatus.java ++javax/net/ssl/SSLEngine/ConnectionTest.java ++javax/net/ssl/SSLEngine/EngineCloseOnAlert.java ++javax/net/ssl/SSLEngine/IllegalHandshakeMessage.java ++javax/net/ssl/SSLEngine/IllegalRecordVersion.java ++javax/net/ssl/SSLEngine/TestAllSuites.java ++javax/security/auth/kerberos/KerberosHashEqualsTest.java ++javax/security/auth/kerberos/KerberosTixDateTest.java ++jdk/jfr/event/oldobject/TestObjectDescription.java ++jdk/jfr/event/sampling/TestNative.java ++jdk/security/infra/java/security/cert/CertPathValidator/certification/HaricaCA.java ++sun/net/www/protocol/https/HttpsURLConnection/CloseKeepAliveCached.java ++sun/security/provider/PolicyFile/GrantAllPermToExtWhenNoPolicy.java ++sun/security/provider/PolicyParser/ExtDirs.java ++sun/security/provider/PolicyParser/ExtDirsChange.java ++sun/security/provider/PolicyParser/ExtDirsDefaultPolicy.java ++sun/security/provider/PolicyParser/PrincipalExpansionError.java ++sun/security/ssl/SSLSocketImpl/ClientTimeout.java ++sun/security/ssl/SSLSocketImpl/NonAutoClose.java ++sun/security/ssl/SSLSocketImpl/SetClientMode.java ++sun/security/tools/jarsigner/warnings/BadKeyUsageTest.java ++sun/security/tools/keytool/i18n.sh +diff --git a/version_patch.sh b/version_patch.sh +new file mode 100644 +index 0000000000..b48e597504 +--- /dev/null ++++ b/version_patch.sh +@@ -0,0 +1,14 @@ ++#!/bin/bash ++gitnum=`git log| head -n 1 |cut -b 8-15` ++bdate=`date +%Y-%m-%d` ++#gitdate=`git log --pretty=format:"%ai"|head -n 1|cut -d " " -f 1` ++topdir=`pwd` ++updatever=212 ++patch=SP2 ++username=`echo $USER` ++buildtag=$username.`basename $topdir`.$gitnum.$bdate.$patch ++ ++#sed -i '500a USER_RELEASE_SUFFIX=`'$buildtag'`' ./common/autoconf/jdk-options.m4 ++sed -i '499c USER_RELEASE_SUFFIX="'$buildtag'"' ./common/autoconf/jdk-options.m4 ++sed -i '500c JDK_UPDATE_VERSION='$updatever'' ./common/autoconf/jdk-options.m4 ++ diff --git a/heapdump-bug-fix.patch b/heapdump-bug-fix.patch new file mode 100644 index 0000000000000000000000000000000000000000..02d423682cd64eb15247102b26ab208032c1ccf9 --- /dev/null +++ b/heapdump-bug-fix.patch @@ -0,0 +1,66 @@ +From 0251eb0780e088d3a8977d500c89dc33fff5bd06 Mon Sep 17 00:00:00 2001 +From: Whitney33 +Subject: [PATCH] heapdump bug fix + +--- + hotspot/src/share/vm/services/heapDumper.cpp | 21 +++++++++++++------- + 1 file changed, 14 insertions(+), 7 deletions(-) + +diff --git a/hotspot/src/share/vm/services/heapDumper.cpp b/hotspot/src/share/vm/services/heapDumper.cpp +index 92bb81d01..5e05e4dab 100644 +--- a/hotspot/src/share/vm/services/heapDumper.cpp ++++ b/hotspot/src/share/vm/services/heapDumper.cpp +@@ -1938,8 +1938,20 @@ class VM_HeapDumper : public VM_GC_Operation { + assert(_global_writer == NULL, "Error"); + _global_writer = _local_writer; + } ++ void set_dump_instance_fields_descriptors() { ++ assert(_dump_instance_fields_descriptors == NULL, "Error"); ++ assert(_global_writer != NULL, "Error"); ++ if(_global_writer->getHeapDumpRedactLevel() == REDACT_ANNOTATION) { ++ _dump_instance_fields_descriptors = DumperSupport::dump_instance_annotation_field_descriptors; ++ } else if(_global_writer->getHeapDumpRedactLevel() == REDACT_DIYRULES) { ++ _dump_instance_fields_descriptors = DumperSupport::dump_instance_diyrules_field_descriptors; ++ } else { ++ _dump_instance_fields_descriptors = DumperSupport::dump_instance_field_descriptors; ++ } ++ } + void clear_global_dumper() { _global_dumper = NULL; } + void clear_global_writer() { _global_writer = NULL; } ++ void clear_dump_instance_fields_descriptors() { _dump_instance_fields_descriptors = NULL; } + + bool skip_operation() const; + +@@ -1979,13 +1991,6 @@ class VM_HeapDumper : public VM_GC_Operation { + _klass_map = new (ResourceObj::C_HEAP, mtInternal) GrowableArray(INITIAL_CLASS_COUNT, true); + _stack_traces = NULL; + _num_threads = 0; +- if(writer->getHeapDumpRedactLevel() == REDACT_ANNOTATION) { +- _dump_instance_fields_descriptors = DumperSupport::dump_instance_annotation_field_descriptors; +- } else if(writer->getHeapDumpRedactLevel() == REDACT_DIYRULES) { +- _dump_instance_fields_descriptors = DumperSupport::dump_instance_diyrules_field_descriptors; +- } else { +- _dump_instance_fields_descriptors = DumperSupport::dump_instance_field_descriptors; +- } + + if (oome) { + assert(!Thread::current()->is_VM_thread(), "Dump from OutOfMemoryError cannot be called by the VMThread"); +@@ -2290,6 +2295,7 @@ void VM_HeapDumper::doit() { + // the following should be safe. + set_global_dumper(); + set_global_writer(); ++ set_dump_instance_fields_descriptors(); + + // Write the file header - we always use 1.0.2 + size_t used = ch->used(); +@@ -2379,6 +2385,7 @@ void VM_HeapDumper::doit() { + // Now we clear the global variables, so that a future dumper might run. + clear_global_dumper(); + clear_global_writer(); ++ clear_dump_instance_fields_descriptors(); + } + + void VM_HeapDumper::dump_stack_traces() { +-- +2.43.0.windows.1 + diff --git a/jdk8u-jdk8u452-b09.tar.xz b/jdk8u-jdk8u452-b09.tar.xz new file mode 100644 index 0000000000000000000000000000000000000000..c35437146b1edf7a75367e2f16a3fdd841f62a1c Binary files /dev/null and b/jdk8u-jdk8u452-b09.tar.xz differ diff --git a/openjdk-1.8.0.spec b/openjdk-1.8.0.spec index cfaa57d5ddd0345b8b5e07c947e68767fd589fb0..ad0972d94d4746436e266be4482511949c635e2e 100644 --- a/openjdk-1.8.0.spec +++ b/openjdk-1.8.0.spec @@ -56,9 +56,10 @@ %global aarch64 aarch64 %global riscv64 riscv64 %global ppc64le ppc64le -%global jit_arches x86_64 %{aarch64} loongarch64 ppc64le -%global sa_arches x86_64 %{aarch64} loongarch64 -%global jfr_arches x86_64 %{aarch64} loongarch64 ppc64le +%global sw_64 sw_64 +%global jit_arches x86_64 %{aarch64} loongarch64 ppc64le sw_64 +%global sa_arches x86_64 %{aarch64} loongarch64 sw_64 +%global jfr_arches x86_64 %{aarch64} loongarch64 ppc64le sw_64 # By default, we build a debug build during main build on JIT architectures %global include_debug_build 1 @@ -134,6 +135,11 @@ %global stapinstall powerpc64le %endif +%ifarch sw_64 +%global archinstall sw64 +%global stapinstall sw64 +%endif + # Need to support noarch for srpm build %ifarch noarch %global archinstall %{nil} @@ -174,13 +180,13 @@ %global origin_nice OpenJDK %global top_level_dir_name %{origin} %global repo jdk8u -%global revision jdk8u442-b06 +%global revision jdk8u452-b09 %global full_revision %{repo}-%{revision} # Define IcedTea version used for SystemTap tapsets and desktop files %global icedteaver 3.15.0 -%global updatever 442 -%global buildver b06 +%global updatever 452 +%global buildver b09 # priority must be 7 digits in total. The expression is workarounding tip %global priority 1800%{updatever} @@ -621,7 +627,7 @@ exit 0 %{_jvmdir}/%{jredir -- %{?1}}/lib/%{archinstall}/libunpack.so %{_jvmdir}/%{jredir -- %{?1}}/lib/%{archinstall}/libverify.so %{_jvmdir}/%{jredir -- %{?1}}/lib/%{archinstall}/libzip.so -%ifnarch loongarch64 +%ifnarch loongarch64 sw_64 %{_jvmdir}/%{jredir -- %{?1}}/lib/%{archinstall}/libz.so %endif %{_jvmdir}/%{jredir -- %{?1}}/lib/charsets.jar @@ -947,7 +953,7 @@ Provides: java-%{javaver}-%{origin}-accessibility%{?1} = %{epoch}:%{version}-%{r Name: java-%{javaver}-%{origin} Version: %{javaver}.%{updatever}.%{buildver} -Release: 0 +Release: 2 # java-1.5.0-ibm from jpackage.org set Epoch to 1 for unknown reasons # and this change was brought into RHEL-4. java-1.5.0-ibm packages # also included the epoch in their virtual provides. This created a @@ -1361,6 +1367,11 @@ Patch454: 8253072-XERCES-version-is-displayed-incorrect.patch Patch455: 8159461-8288556-getComponentType.patch Patch456: 8136926-phi-NULL-assert-in-PhaseIdealLoop-try_move_s.patch Patch457: 8269934-RunThese24H.java-failed-with-EXCEPTION_ACCES.patch +Patch458: 8352716-tz-Update-Timezone-Data-to-2025b.patch + +#452 +Patch459: heapdump-bug-fix.patch + ############################################# # # Upstreamable patches @@ -1416,6 +1427,14 @@ Patch2000: add-riscv64-support.patch Patch4000: LoongArch64-support.patch +############################################ +# +# sw_64 specific patches +# +############################################ + +Patch6000: add-sw_64-support.patch + ############################################# # # Dependencies @@ -1707,7 +1726,7 @@ ln -s %{top_level_dir_name} jdk8 pushd %{top_level_dir_name} # OpenJDK patches -%ifnarch loongarch64 ppc64le +%ifnarch loongarch64 ppc64le sw_64 %patch8 -p1 %patch10 -p1 @@ -2029,6 +2048,8 @@ pushd %{top_level_dir_name} %patch455 -p1 %patch456 -p1 %patch457 -p1 +%patch458 -p1 +%patch459 -p1 %endif %ifarch loongarch64 @@ -2041,6 +2062,10 @@ pushd %{top_level_dir_name} %endif +%ifarch sw_64 +%patch6000 -p1 +%endif + %ifarch riscv64 %patch2000 -p1 %endif @@ -2158,7 +2183,7 @@ bash ${top_srcdir_abs_path}/configure \ --with-milestone="fcs" \ --with-update-version=%{updatever} \ --with-build-number=%{buildver} \ -%ifnarch loongarch64 ppc64le +%ifnarch loongarch64 ppc64le sw_64 --with-company-name="BiSheng" \ --with-vendor-name="BiSheng" \ %endif @@ -2166,7 +2191,9 @@ bash ${top_srcdir_abs_path}/configure \ --with-vendor-bug-url="https://gitee.com/src-openeuler/openjdk-1.8.0/issues/" \ --with-vendor-vm-bug-url="https://gitee.com/src-openeuler/openjdk-1.8.0/issues/" \ --with-debug-level=$debugbuild \ +%ifnarch sw_64 --enable-unlimited-crypto \ +%endif %ifarch aarch64 --enable-kae \ %endif @@ -2690,6 +2717,20 @@ cjc.mainProgram(args) -- the returns from copy_jdk_configs.lua should not affect %endif %changelog +* Sat May 17 2025 Benshuai5D -1:1.8.0.452.b09-2 +- add heapdump-bug-fix.patch + +* Tue Apr 29 2025 wulongyao -1:1.8.0.452.b09-1 +- add 8352716-tz-Update-Timezone-Data-to-2025b.patch + +* Thu Apr 17 2025 DXwangg -1:1.8.0.452.b09-0 +- update to 8u452 +- modified add-missing-test-case.patch +- modified GCC-12-reports-some-compiler-warnings.patch + +* Tue Mar 18 2025 swcompiler -1:1.8.0.442.b06-1 +- Add sw64 architecture support to 8u442 + * Wed Jan 22 2025 Autistic_boyya -1:1.8.0.442.b06-0 - modified add-missing-test-case.patch