From d062382ce09bfe8e7cc67329120c93cc153e5c32 Mon Sep 17 00:00:00 2001 From: vicwang-oc Date: Fri, 5 Sep 2025 16:53:56 +0800 Subject: [PATCH] add zhaoxin processors support. --- openjdk-1.8.0.spec | 7 +- zhaoxin_processors_support.patch | 331 +++++++++++++++++++++++++++++++ 2 files changed, 337 insertions(+), 1 deletion(-) create mode 100644 zhaoxin_processors_support.patch diff --git a/openjdk-1.8.0.spec b/openjdk-1.8.0.spec index a09665b..c8c2c92 100644 --- a/openjdk-1.8.0.spec +++ b/openjdk-1.8.0.spec @@ -953,7 +953,7 @@ Provides: java-%{javaver}-%{origin}-accessibility%{?1} = %{epoch}:%{version}-%{r Name: java-%{javaver}-%{origin} Version: %{javaver}.%{updatever}.%{buildver} -Release: 3 +Release: 4 # java-1.5.0-ibm from jpackage.org set Epoch to 1 for unknown reasons # and this change was brought into RHEL-4. java-1.5.0-ibm packages # also included the epoch in their virtual provides. This created a @@ -1383,6 +1383,7 @@ Patch470: Backport-8296924-C2-assert-is_valid_AArch64_address-dest.targ.patch #462 Patch471: Fix-tests-for-OS-with-64k-page-size.patch Patch472: Add-testcase-for-jdk.Deoptimization-and-bug-fixes-fo.patch +Patch473: zhaoxin_processors_support.patch ############################################# # @@ -2070,6 +2071,7 @@ pushd %{top_level_dir_name} %patch470 -p1 %patch471 -p1 %patch472 -p1 +%patch473 -p1 %endif %ifarch loongarch64 @@ -3054,6 +3056,9 @@ cjc.mainProgram(args) -- the returns from copy_jdk_configs.lua should not affect %endif %changelog +* Fri Sep 5 2025 vicwang-oc -1:1.8.0.462.b08-4 +- add zhaoxin_processors_support.patch + * Wed Jul 30 2025 neu-mobi -1:1.8.0.462.b08-3 - add Add-testcase-for-jdk.Deoptimization-and-bug-fixes-fo.patch diff --git a/zhaoxin_processors_support.patch b/zhaoxin_processors_support.patch new file mode 100644 index 0000000..0633621 --- /dev/null +++ b/zhaoxin_processors_support.patch @@ -0,0 +1,331 @@ +diff -Naur a/hotspot/src/cpu/x86/vm/assembler_x86.cpp b/hotspot/src/cpu/x86/vm/assembler_x86.cpp +--- a/hotspot/src/cpu/x86/vm/assembler_x86.cpp 2025-09-05 16:18:56.912284839 +0800 ++++ b/hotspot/src/cpu/x86/vm/assembler_x86.cpp 2025-09-05 16:19:11.066485486 +0800 +@@ -2231,6 +2231,89 @@ + return; + } + ++ if (UseAddressNop && VM_Version::is_zx()) { ++ // ++ // Using multi-bytes nops "0x0F 0x1F [address]" for ZX ++ // 1: 0x90 ++ // 2: 0x66 0x90 ++ // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding) ++ // 4: 0x0F 0x1F 0x40 0x00 ++ // 5: 0x0F 0x1F 0x44 0x00 0x00 ++ // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00 ++ // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 ++ // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 ++ // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 ++ // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 ++ // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 ++ ++ // The rest coding is ZX specific - don't use consecutive address nops ++ ++ // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 ++ // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 ++ // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 ++ // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 ++ ++ while (i >= 15) { ++ // For ZX don't generate consecutive addess nops (mix with regular nops) ++ i -= 15; ++ emit_int8(0x66); // size prefix ++ emit_int8(0x66); // size prefix ++ emit_int8(0x66); // size prefix ++ addr_nop_8(); ++ emit_int8(0x66); // size prefix ++ emit_int8(0x66); // size prefix ++ emit_int8(0x66); // size prefix ++ emit_int8((unsigned char)0x90); ++ // nop ++ } ++ switch (i) { ++ case 14: ++ emit_int8(0x66); // size prefix ++ case 13: ++ emit_int8(0x66); // size prefix ++ case 12: ++ addr_nop_8(); ++ emit_int8(0x66); // size prefix ++ emit_int8(0x66); // size prefix ++ emit_int8(0x66); // size prefix ++ emit_int8((unsigned char)0x90); ++ // nop ++ break; ++ case 11: ++ emit_int8(0x66); // size prefix ++ case 10: ++ emit_int8(0x66); // size prefix ++ case 9: ++ emit_int8(0x66); // size prefix ++ case 8: ++ addr_nop_8(); ++ break; ++ case 7: ++ addr_nop_7(); ++ break; ++ case 6: ++ emit_int8(0x66); // size prefix ++ case 5: ++ addr_nop_5(); ++ break; ++ case 4: ++ addr_nop_4(); ++ break; ++ case 3: ++ // Don't use "0x0F 0x1F 0x00" - need patching safe padding ++ emit_int8(0x66); // size prefix ++ case 2: ++ emit_int8(0x66); // size prefix ++ case 1: ++ emit_int8((unsigned char)0x90); ++ // nop ++ break; ++ default: ++ assert(i == 0, " "); ++ } ++ return; ++ } ++ + // Using nops with size prefixes "0x66 0x90". + // From AMD Optimization Guide: + // 1: 0x90 +diff -Naur a/hotspot/src/cpu/x86/vm/vm_version_ext_x86.cpp b/hotspot/src/cpu/x86/vm/vm_version_ext_x86.cpp +--- a/hotspot/src/cpu/x86/vm/vm_version_ext_x86.cpp 2025-09-05 16:18:56.914284867 +0800 ++++ b/hotspot/src/cpu/x86/vm/vm_version_ext_x86.cpp 2025-09-05 16:19:11.076485627 +0800 +@@ -398,6 +398,7 @@ + + const char* VM_Version_Ext::cpu_family_description(void) { + int cpu_family_id = extended_cpu_family(); ++ int cpu_model_id = extended_cpu_model(); + if (is_amd()) { + return _family_id_amd[cpu_family_id]; + } +@@ -407,6 +408,22 @@ + } + return _family_id_intel[cpu_family_id]; + } ++ if (is_zx()) { ++ if (cpu_family_id == 7) { ++ switch (cpu_model_id) { ++ case 0x1B: ++ return "wudaokou"; ++ case 0x3B: ++ return "lujiazui"; ++ case 0x5B: ++ return "yongfeng"; ++ case 0x6B: ++ return "shijidadao"; ++ } ++ } else if (cpu_family_id == 6) { ++ return "zhangjiang"; ++ } ++ } + return "Unknown x86"; + } + +@@ -423,6 +440,9 @@ + } else if (is_amd()) { + cpu_type = "AMD"; + x64 = cpu_is_em64t() ? " AMD64" : ""; ++ } else if (is_zx()) { ++ cpu_type = "Zhaoxin"; ++ x64 = cpu_is_em64t() ? "x86_64" : ""; + } else { + cpu_type = "Unknown x86"; + x64 = cpu_is_em64t() ? " x86_64" : ""; +diff -Naur a/hotspot/src/cpu/x86/vm/vm_version_x86.cpp b/hotspot/src/cpu/x86/vm/vm_version_x86.cpp +--- a/hotspot/src/cpu/x86/vm/vm_version_x86.cpp 2025-09-05 16:18:56.923284995 +0800 ++++ b/hotspot/src/cpu/x86/vm/vm_version_x86.cpp 2025-09-05 16:19:11.076485627 +0800 +@@ -470,6 +470,19 @@ + if (UseSSE < 1) + _cpuFeatures &= ~CPU_SSE; + ++ //ZX cpus specific settings ++ if (is_zx() && FLAG_IS_DEFAULT(UseAVX)) { ++ if (cpu_family() == 7) { ++ if (extended_cpu_model() == 0x5B || extended_cpu_model() == 0x6B) { ++ UseAVX = 1; ++ } else if (extended_cpu_model() == 0x1B || extended_cpu_model() == 0x3B) { ++ UseAVX = 0; ++ } ++ } else if (cpu_family() == 6) { ++ UseAVX = 0; ++ } ++ } ++ + if (UseAVX < 2) + _cpuFeatures &= ~CPU_AVX2; + +@@ -823,6 +836,65 @@ + // UseXmmRegToRegMoveAll == true --> movaps(xmm, xmm), movapd(xmm, xmm). + // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm), movsd(xmm, xmm). + ++ if (is_zx()) { // ZX cpus specific settings ++ if (FLAG_IS_DEFAULT(UseStoreImmI16)) { ++ UseStoreImmI16 = false; // don't use it on ZX cpus ++ } ++ if ((cpu_family() == 6) || (cpu_family() == 7)) { ++ if (FLAG_IS_DEFAULT(UseAddressNop)) { ++ // Use it on all ZX cpus ++ UseAddressNop = true; ++ } ++ } ++ if (FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper)) { ++ UseXmmLoadAndClearUpper = true; // use movsd on all ZX cpus ++ } ++ if (FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll)) { ++ if (supports_sse3()) { ++ UseXmmRegToRegMoveAll = true; // use movaps, movapd on new ZX cpus ++ } else { ++ UseXmmRegToRegMoveAll = false; ++ } ++ } ++ if (((cpu_family() == 6) || (cpu_family() == 7)) && supports_sse3()) { // new ZX cpus ++#ifdef COMPILER2 ++ if (FLAG_IS_DEFAULT(MaxLoopPad)) { ++ // For new ZX cpus do the next optimization: ++ // don't align the beginning of a loop if there are enough instructions ++ // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp) ++ // in current fetch line (OptoLoopAlignment) or the padding ++ // is big (> MaxLoopPad). ++ // Set MaxLoopPad to 11 for new ZX cpus to reduce number of ++ // generated NOP instructions. 11 is the largest size of one ++ // address NOP instruction '0F 1F' (see Assembler::nop(i)). ++ MaxLoopPad = 11; ++ } ++#endif // COMPILER2 ++ if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) { ++ UseXMMForArrayCopy = true; // use SSE2 movq on new ZX cpus ++ } ++ if (supports_sse4_2()) { // new ZX cpus ++ if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) { ++ UseUnalignedLoadStores = true; // use movdqu on newest ZX cpus ++ } ++ } ++ if (supports_sse4_2()) { ++ if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) { ++ FLAG_SET_DEFAULT(UseSSE42Intrinsics, true); ++ } ++ } else { ++ if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) { ++ warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled."); ++ } ++ FLAG_SET_DEFAULT(UseSSE42Intrinsics, false); ++ } ++ } ++ ++ if (FLAG_IS_DEFAULT(AllocatePrefetchInstr) && supports_3dnow_prefetch()) { ++ FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3); ++ } ++ } ++ + if( is_amd() ) { // AMD cpus specific settings + if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) { + // Use it on new AMD cpus starting from Opteron. +@@ -1083,6 +1155,15 @@ + } + #endif + } ++ ++ if (is_zx() && ((cpu_family() == 6) || (cpu_family() == 7)) && supports_sse4_2()) { ++#ifdef COMPILER2 ++ if (FLAG_IS_DEFAULT(UseFPUForSpilling)) { ++ FLAG_SET_DEFAULT(UseFPUForSpilling, true); ++ } ++#endif ++ } ++ + assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value"); + + #ifdef _LP64 +diff -Naur a/hotspot/src/cpu/x86/vm/vm_version_x86.hpp b/hotspot/src/cpu/x86/vm/vm_version_x86.hpp +--- a/hotspot/src/cpu/x86/vm/vm_version_x86.hpp 2025-09-05 16:18:56.918284924 +0800 ++++ b/hotspot/src/cpu/x86/vm/vm_version_x86.hpp 2025-09-05 16:19:11.076485627 +0800 +@@ -269,6 +269,9 @@ + enum { + // AMD + CPU_FAMILY_AMD_11H = 0x11, ++ // ZX ++ CPU_FAMILY_ZX_CORE_F6 = 6, ++ CPU_FAMILY_ZX_CORE_F7 = 7, + // Intel + CPU_FAMILY_INTEL_CORE = 6, + CPU_MODEL_NEHALEM = 0x1e, +@@ -480,6 +483,20 @@ + } + } + ++ // ZX features. ++ if (is_zx()) { ++ if(_cpuid_info.sef_cpuid7_ebx.bits.adx != 0) ++ result |= CPU_ADX; ++ if(_cpuid_info.sef_cpuid7_ebx.bits.bmi2 != 0) ++ result |= CPU_BMI2; ++ if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0) ++ result |= CPU_LZCNT; ++ // for ZX, ecx.bits.misalignsse bit (bit 8) indicates support for prefetchw ++ if (_cpuid_info.ext_cpuid1_ecx.bits.misalignsse != 0) { ++ result |= CPU_3DNOW_PREFETCH; ++ } ++ } ++ + return result; + } + +@@ -559,6 +576,7 @@ + static bool is_P6() { return cpu_family() >= 6; } + static bool is_amd() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA' + static bool is_intel() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x756e6547; } // 'uneG' ++ static bool is_zx() { assert_is_initialized(); return (_cpuid_info.std_vendor_name_0 == 0x746e6543) || (_cpuid_info.std_vendor_name_0 == 0x68532020); } // 'tneC'||'hS ' + + static bool supports_processor_topology() { + return (_cpuid_info.std_max_function >= 0xB) && +@@ -580,6 +598,15 @@ + } + } else if (is_amd()) { + result = (_cpuid_info.ext_cpuid8_ecx.bits.cores_per_cpu + 1); ++ } else if (is_zx()) { ++ bool supports_topology = supports_processor_topology(); ++ if (supports_topology) { ++ result = _cpuid_info.tpl_cpuidB1_ebx.bits.logical_cpus / ++ _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus; ++ } ++ if (!supports_topology || result == 0) { ++ result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1); ++ } + } + return result; + } +@@ -588,6 +615,8 @@ + uint result = 1; + if (is_intel() && supports_processor_topology()) { + result = _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus; ++ } else if (is_zx() && supports_processor_topology()) { ++ result = _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus; + } else if (_cpuid_info.std_cpuid1_edx.bits.ht != 0) { + result = _cpuid_info.std_cpuid1_ebx.bits.threads_per_cpu / + cores_per_cpu(); +@@ -601,6 +630,8 @@ + result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1); + } else if (is_amd()) { + result = _cpuid_info.ext_cpuid5_ecx.bits.L1_line_size; ++ } else if (is_zx()) { ++ result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1); + } + if (result < 32) // not defined ? + result = 32; // 32 bytes by default on x86 and other x64 +@@ -711,6 +742,12 @@ + count = 256; // Opteron + else + count = 128; // Athlon ++ } else if (is_zx()) { // ZX ++ if (supports_sse2()) { ++ return 256; ++ } else { ++ return 128; ++ } + } else { // Intel + if (supports_sse2()) + if (cpu_family() == 6) { -- Gitee