diff --git a/8207160-ClassReader-adjustMethodParams-can-potentially-return-null-if-the-args-list-is-empty.patch b/8207160-ClassReader-adjustMethodParams-can-potentially-return-null-if-the-args-list-is-empty.patch deleted file mode 100755 index f95d845b3d32c5d6530c1dac53d937134042e8c9..0000000000000000000000000000000000000000 --- a/8207160-ClassReader-adjustMethodParams-can-potentially-return-null-if-the-args-list-is-empty.patch +++ /dev/null @@ -1,168 +0,0 @@ -diff --git a/src/jdk.compiler/share/classes/com/sun/tools/javac/jvm/ClassReader.java b/src/jdk.compiler/share/classes/com/sun/tools/javac/jvm/ClassReader.java -index 5a1d3b900..ab327bf9a 100644 ---- a/src/jdk.compiler/share/classes/com/sun/tools/javac/jvm/ClassReader.java -+++ b/src/jdk.compiler/share/classes/com/sun/tools/javac/jvm/ClassReader.java -@@ -2471,6 +2471,9 @@ public class ClassReader { - } - - private List adjustMethodParams(long flags, List args) { -+ if (args.isEmpty()) { -+ return args; -+ } - boolean isVarargs = (flags & VARARGS) != 0; - if (isVarargs) { - Type varargsElem = args.last(); -diff --git a/test/langtools/tools/javac/AvoidNPEAtClassReader/AvoidNPEAtClassReaderTest.java b/test/langtools/tools/javac/AvoidNPEAtClassReader/AvoidNPEAtClassReaderTest.java -new file mode 100644 -index 000000000..3b47d6944 ---- /dev/null -+++ b/test/langtools/tools/javac/AvoidNPEAtClassReader/AvoidNPEAtClassReaderTest.java -@@ -0,0 +1,43 @@ -+/* -+ * Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved. -+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+ * -+ * This code is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 only, as -+ * published by the Free Software Foundation. -+ * -+ * This code is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * version 2 for more details (a copy is included in the LICENSE file that -+ * accompanied this code). -+ * -+ * You should have received a copy of the GNU General Public License version -+ * 2 along with this work; if not, write to the Free Software Foundation, -+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+ * or visit www.oracle.com if you need additional information or have any -+ * questions. -+ */ -+ -+/** -+ * @test -+ * @bug 8207160 -+ * @summary ClassReader::adjustMethodParams can potentially return null if the args list is empty -+ * @compile pkg/Outer.jasm pkg/Outer$Inner.jasm AvoidNPEAtClassReaderTest.java -+ */ -+ -+ -+/** this test is checking that javac doesn't fail with NPE when reading inner classes with constructors -+ * that doesn't have as a parameter a reference to the outer class. Such constructors were generated by -+ * versions of javac previous to JDK7. -+ */ -+ -+import pkg.*; -+ -+public class AvoidNPEAtClassReaderTest { -+ public void bar(Outer outer) { -+ Object stuff = outer.foo(); -+ } -+} -diff --git a/test/langtools/tools/javac/AvoidNPEAtClassReader/pkg/Outer$Inner.jasm b/test/langtools/tools/javac/AvoidNPEAtClassReader/pkg/Outer$Inner.jasm -new file mode 100644 -index 000000000..23fe2eb4b ---- /dev/null -+++ b/test/langtools/tools/javac/AvoidNPEAtClassReader/pkg/Outer$Inner.jasm -@@ -0,0 +1,42 @@ -+/* -+ * Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved. -+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+ * -+ * This code is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 only, as -+ * published by the Free Software Foundation. -+ * -+ * This code is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * version 2 for more details (a copy is included in the LICENSE file that -+ * accompanied this code). -+ * -+ * You should have received a copy of the GNU General Public License version -+ * 2 along with this work; if not, write to the Free Software Foundation, -+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+ * or visit www.oracle.com if you need additional information or have any -+ * questions. -+ */ -+ -+package pkg; -+ -+super public final class Outer$Inner -+ version 55:0 -+{ -+ -+final synthetic Field this$0:"Lpkg/Outer;"; -+ -+public Method "":"()V" -+ stack 1 locals 1 -+{ -+ aload_0; -+ invokespecial Method java/lang/Object."":"()V"; -+ return; -+} -+ -+public final InnerClass Inner=class Outer$Inner of class Outer; -+ -+} // end Class Outer$Inner -diff --git a/test/langtools/tools/javac/AvoidNPEAtClassReader/pkg/Outer.jasm b/test/langtools/tools/javac/AvoidNPEAtClassReader/pkg/Outer.jasm -new file mode 100644 -index 000000000..13baaf761 ---- /dev/null -+++ b/test/langtools/tools/javac/AvoidNPEAtClassReader/pkg/Outer.jasm -@@ -0,0 +1,48 @@ -+/* -+ * Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved. -+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+ * -+ * This code is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 only, as -+ * published by the Free Software Foundation. -+ * -+ * This code is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * version 2 for more details (a copy is included in the LICENSE file that -+ * accompanied this code). -+ * -+ * You should have received a copy of the GNU General Public License version -+ * 2 along with this work; if not, write to the Free Software Foundation, -+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+ * or visit www.oracle.com if you need additional information or have any -+ * questions. -+ */ -+ -+package pkg; -+ -+super public class Outer -+ version 55:0 -+{ -+ -+ -+public Method "":"()V" -+ stack 1 locals 1 -+{ -+ aload_0; -+ invokespecial Method java/lang/Object."":"()V"; -+ return; -+} -+ -+public Method foo:"()Lpkg/Outer$Inner;" -+ stack 1 locals 1 -+{ -+ aconst_null; -+ areturn; -+} -+ -+public final InnerClass Inner=class Outer$Inner of class Outer; -+ -+} // end Class Outer --- -2.19.1 - diff --git a/8214527-AArch64-ZGC-for-Aarch64.patch b/8214527-AArch64-ZGC-for-Aarch64.patch index 3696fcea2793404dc1bf0531677fc588cf8e4c51..c4c8a8670e8035217a707940816b27363669895a 100644 --- a/8214527-AArch64-ZGC-for-Aarch64.patch +++ b/8214527-AArch64-ZGC-for-Aarch64.patch @@ -1,5 +1,5 @@ diff --git a/make/autoconf/hotspot.m4 b/make/autoconf/hotspot.m4 -index d598b98..61739b9 100644 +index d598b9897..61739b900 100644 --- a/make/autoconf/hotspot.m4 +++ b/make/autoconf/hotspot.m4 @@ -367,7 +367,8 @@ AC_DEFUN_ONCE([HOTSPOT_SETUP_JVM_FEATURES], @@ -13,7 +13,7 @@ index d598b98..61739b9 100644 else DISABLED_JVM_FEATURES="$DISABLED_JVM_FEATURES zgc" diff --git a/src/hotspot/cpu/aarch64/aarch64.ad b/src/hotspot/cpu/aarch64/aarch64.ad -index 890e457..0625053 100644 +index ce103dc1c..53cd702b9 100644 --- a/src/hotspot/cpu/aarch64/aarch64.ad +++ b/src/hotspot/cpu/aarch64/aarch64.ad @@ -957,6 +957,146 @@ reg_class v3_reg( @@ -175,7 +175,7 @@ index 890e457..0625053 100644 //----------SOURCE BLOCK------------------------------------------------------- // This is a block of C++ code which provides values, functions, and -@@ -4738,6 +4883,258 @@ operand vRegD_V3() +@@ -4761,6 +4906,258 @@ operand vRegD_V3() interface(REG_INTER); %} @@ -434,8 +434,8 @@ index 890e457..0625053 100644 // Flags register, used as output of signed compare instructions // note that on AArch64 we also use this register as the output for -@@ -17078,6 +17475,95 @@ instruct vsrl2L_imm(vecX dst, vecX src, immI shift) %{ - ins_pipe(vshift128_imm); +@@ -17700,6 +18097,95 @@ instruct vpopcount2I(vecD dst, vecD src) %{ + ins_pipe(pipe_class_default); %} +source %{ @@ -531,10 +531,10 @@ index 890e457..0625053 100644 // These must follow all instruction definitions as they use the names // defined in the instructions definitions. diff --git a/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp b/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp -index fe301df..6ab944b 100644 +index 4ba97e035..96042ace5 100644 --- a/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp -@@ -1013,7 +1013,11 @@ void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_Patch +@@ -1033,7 +1033,11 @@ void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_Patch if (UseCompressedOops && !wide) { __ decode_heap_oop(dest->as_register()); } @@ -547,7 +547,7 @@ index fe301df..6ab944b 100644 } else if (type == T_ADDRESS && addr->disp() == oopDesc::klass_offset_in_bytes()) { if (UseCompressedClassPointers) { __ decode_klass_not_null(dest->as_register()); -@@ -2825,7 +2829,11 @@ void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest, LIR_PatchCode patch_code, C +@@ -2903,7 +2907,11 @@ void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest, LIR_PatchCode patch_code, C return; } #endif @@ -562,7 +562,7 @@ index fe301df..6ab944b 100644 diff --git a/src/hotspot/cpu/aarch64/gc/z/zBarrierSetAssembler_aarch64.cpp b/src/hotspot/cpu/aarch64/gc/z/zBarrierSetAssembler_aarch64.cpp new file mode 100644 -index 0000000..90b2b4c +index 000000000..90b2b4ca7 --- /dev/null +++ b/src/hotspot/cpu/aarch64/gc/z/zBarrierSetAssembler_aarch64.cpp @@ -0,0 +1,408 @@ @@ -976,7 +976,7 @@ index 0000000..90b2b4c +} diff --git a/src/hotspot/cpu/aarch64/gc/z/zBarrierSetAssembler_aarch64.hpp b/src/hotspot/cpu/aarch64/gc/z/zBarrierSetAssembler_aarch64.hpp new file mode 100644 -index 0000000..7e8be01 +index 000000000..7e8be01cc --- /dev/null +++ b/src/hotspot/cpu/aarch64/gc/z/zBarrierSetAssembler_aarch64.hpp @@ -0,0 +1,92 @@ @@ -1073,10 +1073,10 @@ index 0000000..7e8be01 + +#endif // CPU_AARCH64_GC_Z_ZBARRIERSETASSEMBLER_AARCH64_HPP diff --git a/src/hotspot/cpu/aarch64/stubGenerator_aarch64.cpp b/src/hotspot/cpu/aarch64/stubGenerator_aarch64.cpp -index 89a4330..ac7eb84 100644 +index 864171278..2eee84cd9 100644 --- a/src/hotspot/cpu/aarch64/stubGenerator_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/stubGenerator_aarch64.cpp -@@ -45,6 +45,9 @@ +@@ -47,6 +47,9 @@ #ifdef COMPILER2 #include "opto/runtime.hpp" #endif @@ -1086,7 +1086,7 @@ index 89a4330..ac7eb84 100644 // Declaration and definition of StubGenerator (no .hpp file). // For a more detailed description of the stub routine structure -@@ -549,6 +552,16 @@ class StubGenerator: public StubCodeGenerator { +@@ -551,6 +554,16 @@ class StubGenerator: public StubCodeGenerator { // make sure object is 'reasonable' __ cbz(r0, exit); // if obj is NULL it is OK @@ -1104,7 +1104,7 @@ index 89a4330..ac7eb84 100644 __ mov(c_rarg3, (intptr_t) Universe::verify_oop_mask()); __ andr(c_rarg2, r0, c_rarg3); diff --git a/src/hotspot/cpu/x86/gc/z/zBarrierSetAssembler_x86.cpp b/src/hotspot/cpu/x86/gc/z/zBarrierSetAssembler_x86.cpp -index d2290a6..381211e 100644 +index d2290a670..381211ecc 100644 --- a/src/hotspot/cpu/x86/gc/z/zBarrierSetAssembler_x86.cpp +++ b/src/hotspot/cpu/x86/gc/z/zBarrierSetAssembler_x86.cpp @@ -273,13 +273,13 @@ void ZBarrierSetAssembler::generate_c1_load_barrier_stub(LIR_Assembler* ce, @@ -1127,7 +1127,7 @@ index d2290a6..381211e 100644 assert_different_registers(ref, ref_addr, noreg); diff --git a/src/hotspot/os_cpu/linux_aarch64/gc/z/zAddress_linux_aarch64.inline.hpp b/src/hotspot/os_cpu/linux_aarch64/gc/z/zAddress_linux_aarch64.inline.hpp new file mode 100644 -index 0000000..936480c +index 000000000..936480cb5 --- /dev/null +++ b/src/hotspot/os_cpu/linux_aarch64/gc/z/zAddress_linux_aarch64.inline.hpp @@ -0,0 +1,31 @@ @@ -1164,7 +1164,7 @@ index 0000000..936480c +#endif // OS_CPU_LINUX_AARCH64_ZADDRESS_LINUX_AARCH64_INLINE_HPP diff --git a/src/hotspot/os_cpu/linux_aarch64/gc/z/zBackingFile_linux_aarch64.cpp b/src/hotspot/os_cpu/linux_aarch64/gc/z/zBackingFile_linux_aarch64.cpp new file mode 100644 -index 0000000..47894b5 +index 000000000..47894b5c8 --- /dev/null +++ b/src/hotspot/os_cpu/linux_aarch64/gc/z/zBackingFile_linux_aarch64.cpp @@ -0,0 +1,426 @@ @@ -1596,7 +1596,7 @@ index 0000000..47894b5 +} diff --git a/src/hotspot/os_cpu/linux_aarch64/gc/z/zBackingFile_linux_aarch64.hpp b/src/hotspot/os_cpu/linux_aarch64/gc/z/zBackingFile_linux_aarch64.hpp new file mode 100644 -index 0000000..032dbc1 +index 000000000..032dbc133 --- /dev/null +++ b/src/hotspot/os_cpu/linux_aarch64/gc/z/zBackingFile_linux_aarch64.hpp @@ -0,0 +1,63 @@ @@ -1665,7 +1665,7 @@ index 0000000..032dbc1 +#endif // OS_CPU_LINUX_AARCH64_ZBACKINGFILE_LINUX_AARCH64_HPP diff --git a/src/hotspot/os_cpu/linux_aarch64/gc/z/zBackingPath_linux_aarch64.cpp b/src/hotspot/os_cpu/linux_aarch64/gc/z/zBackingPath_linux_aarch64.cpp new file mode 100644 -index 0000000..1adffa3 +index 000000000..1adffa32b --- /dev/null +++ b/src/hotspot/os_cpu/linux_aarch64/gc/z/zBackingPath_linux_aarch64.cpp @@ -0,0 +1,149 @@ @@ -1820,7 +1820,7 @@ index 0000000..1adffa3 +} diff --git a/src/hotspot/os_cpu/linux_aarch64/gc/z/zBackingPath_linux_aarch64.hpp b/src/hotspot/os_cpu/linux_aarch64/gc/z/zBackingPath_linux_aarch64.hpp new file mode 100644 -index 0000000..a03aaf9 +index 000000000..a03aaf960 --- /dev/null +++ b/src/hotspot/os_cpu/linux_aarch64/gc/z/zBackingPath_linux_aarch64.hpp @@ -0,0 +1,52 @@ @@ -1878,7 +1878,7 @@ index 0000000..a03aaf9 +#endif // OS_CPU_LINUX_AARCH64_ZBACKINGPATH_LINUX_AARCH64_HPP diff --git a/src/hotspot/os_cpu/linux_aarch64/gc/z/zGlobals_linux_aarch64.cpp b/src/hotspot/os_cpu/linux_aarch64/gc/z/zGlobals_linux_aarch64.cpp new file mode 100644 -index 0000000..5d24809 +index 000000000..5d2480993 --- /dev/null +++ b/src/hotspot/os_cpu/linux_aarch64/gc/z/zGlobals_linux_aarch64.cpp @@ -0,0 +1,33 @@ @@ -1917,7 +1917,7 @@ index 0000000..5d24809 +} diff --git a/src/hotspot/os_cpu/linux_aarch64/gc/z/zGlobals_linux_aarch64.hpp b/src/hotspot/os_cpu/linux_aarch64/gc/z/zGlobals_linux_aarch64.hpp new file mode 100644 -index 0000000..93c1806 +index 000000000..93c18067b --- /dev/null +++ b/src/hotspot/os_cpu/linux_aarch64/gc/z/zGlobals_linux_aarch64.hpp @@ -0,0 +1,88 @@ @@ -2011,7 +2011,7 @@ index 0000000..93c1806 +#endif // OS_CPU_LINUX_AARCH64_ZGLOBALS_LINUX_AARCH64_HPP diff --git a/src/hotspot/os_cpu/linux_aarch64/gc/z/zLargePages_linux_aarch64.cpp b/src/hotspot/os_cpu/linux_aarch64/gc/z/zLargePages_linux_aarch64.cpp new file mode 100644 -index 0000000..c79195c +index 000000000..c79195cd1 --- /dev/null +++ b/src/hotspot/os_cpu/linux_aarch64/gc/z/zLargePages_linux_aarch64.cpp @@ -0,0 +1,38 @@ @@ -2055,7 +2055,7 @@ index 0000000..c79195c +} diff --git a/src/hotspot/os_cpu/linux_aarch64/gc/z/zNUMA_linux_aarch64.cpp b/src/hotspot/os_cpu/linux_aarch64/gc/z/zNUMA_linux_aarch64.cpp new file mode 100644 -index 0000000..10706fa +index 000000000..10706fac2 --- /dev/null +++ b/src/hotspot/os_cpu/linux_aarch64/gc/z/zNUMA_linux_aarch64.cpp @@ -0,0 +1,83 @@ @@ -2144,7 +2144,7 @@ index 0000000..10706fa +} diff --git a/src/hotspot/os_cpu/linux_aarch64/gc/z/zPhysicalMemoryBacking_linux_aarch64.cpp b/src/hotspot/os_cpu/linux_aarch64/gc/z/zPhysicalMemoryBacking_linux_aarch64.cpp new file mode 100644 -index 0000000..55c2a16 +index 000000000..55c2a16e0 --- /dev/null +++ b/src/hotspot/os_cpu/linux_aarch64/gc/z/zPhysicalMemoryBacking_linux_aarch64.cpp @@ -0,0 +1,270 @@ @@ -2420,7 +2420,7 @@ index 0000000..55c2a16 +} diff --git a/src/hotspot/os_cpu/linux_aarch64/gc/z/zPhysicalMemoryBacking_linux_aarch64.hpp b/src/hotspot/os_cpu/linux_aarch64/gc/z/zPhysicalMemoryBacking_linux_aarch64.hpp new file mode 100644 -index 0000000..c55b7b1 +index 000000000..c55b7b17c --- /dev/null +++ b/src/hotspot/os_cpu/linux_aarch64/gc/z/zPhysicalMemoryBacking_linux_aarch64.hpp @@ -0,0 +1,65 @@ @@ -2491,7 +2491,7 @@ index 0000000..c55b7b1 +#endif // OS_CPU_LINUX_AARCH64_ZPHYSICALMEMORYBACKING_LINUX_AARCH64_HPP diff --git a/src/hotspot/os_cpu/linux_aarch64/gc/z/zVirtualMemory_linux_aarch64.cpp b/src/hotspot/os_cpu/linux_aarch64/gc/z/zVirtualMemory_linux_aarch64.cpp new file mode 100644 -index 0000000..68df401 +index 000000000..68df40191 --- /dev/null +++ b/src/hotspot/os_cpu/linux_aarch64/gc/z/zVirtualMemory_linux_aarch64.cpp @@ -0,0 +1,41 @@ @@ -2537,7 +2537,7 @@ index 0000000..68df401 + return true; +} diff --git a/src/hotspot/share/gc/z/c1/zBarrierSetC1.cpp b/src/hotspot/share/gc/z/c1/zBarrierSetC1.cpp -index 9f8ce74..0abd398 100644 +index 9f8ce7424..0abd3980f 100644 --- a/src/hotspot/share/gc/z/c1/zBarrierSetC1.cpp +++ b/src/hotspot/share/gc/z/c1/zBarrierSetC1.cpp @@ -38,21 +38,15 @@ ZLoadBarrierStubC1::ZLoadBarrierStubC1(LIRAccess& access, LIR_Opr ref, address r @@ -2569,3 +2569,6 @@ index 9f8ce74..0abd398 100644 } DecoratorSet ZLoadBarrierStubC1::decorators() const { +-- +2.19.0 + diff --git a/8217856-ZGC-Break-out-C2-matching-rules-into-separat.patch b/8217856-ZGC-Break-out-C2-matching-rules-into-separat.patch index df9f0a658f564e82ea66beacffbcb3b7381df5cb..b88b4bfecef68c704a43f77a4050494101550597 100644 --- a/8217856-ZGC-Break-out-C2-matching-rules-into-separat.patch +++ b/8217856-ZGC-Break-out-C2-matching-rules-into-separat.patch @@ -1,8 +1,8 @@ diff --git a/make/hotspot/gensrc/GensrcAdlc.gmk b/make/hotspot/gensrc/GensrcAdlc.gmk -index 6878962..bb9721c 100644 +index 687896251..a39640526 100644 --- a/make/hotspot/gensrc/GensrcAdlc.gmk +++ b/make/hotspot/gensrc/GensrcAdlc.gmk -@@ -146,6 +146,12 @@ ifeq ($(call check-jvm-feature, compiler2), true) +@@ -140,6 +140,12 @@ ifeq ($(call check-jvm-feature, compiler2), true) $d/os_cpu/$(HOTSPOT_TARGET_OS)_$(HOTSPOT_TARGET_CPU_ARCH)/$(HOTSPOT_TARGET_OS)_$(HOTSPOT_TARGET_CPU_ARCH).ad \ ))) @@ -16,7 +16,7 @@ index 6878962..bb9721c 100644 AD_SRC_FILES += $(call uniq, $(wildcard $(foreach d, $(AD_SRC_ROOTS), \ $d/cpu/$(HOTSPOT_TARGET_CPU_ARCH)/gc/shenandoah/shenandoah_$(HOTSPOT_TARGET_CPU).ad \ diff --git a/src/hotspot/cpu/aarch64/aarch64.ad b/src/hotspot/cpu/aarch64/aarch64.ad -index 05b36e2..18e774f 100644 +index 29f81face..ab578476a 100644 --- a/src/hotspot/cpu/aarch64/aarch64.ad +++ b/src/hotspot/cpu/aarch64/aarch64.ad @@ -1128,13 +1128,6 @@ definitions %{ @@ -33,8 +33,8 @@ index 05b36e2..18e774f 100644 //----------SOURCE BLOCK------------------------------------------------------- // This is a block of C++ code which provides values, functions, and // definitions necessary in the rest of the architecture description -@@ -17488,243 +17481,6 @@ instruct vsrl2L_imm(vecX dst, vecX src, immI shift) %{ - ins_pipe(vshift128_imm); +@@ -18110,243 +18103,6 @@ instruct vpopcount2I(vecD dst, vecD src) %{ + ins_pipe(pipe_class_default); %} -source %{ @@ -279,7 +279,7 @@ index 05b36e2..18e774f 100644 // These must follow all instruction definitions as they use the names diff --git a/src/hotspot/cpu/aarch64/gc/z/z_aarch64.ad b/src/hotspot/cpu/aarch64/gc/z/z_aarch64.ad new file mode 100644 -index 0000000..50cc6f9 +index 000000000..50cc6f924 --- /dev/null +++ b/src/hotspot/cpu/aarch64/gc/z/z_aarch64.ad @@ -0,0 +1,268 @@ @@ -553,7 +553,7 @@ index 0000000..50cc6f9 + diff --git a/src/hotspot/cpu/x86/gc/z/z_x86_64.ad b/src/hotspot/cpu/x86/gc/z/z_x86_64.ad new file mode 100644 -index 0000000..38c2e92 +index 000000000..38c2e926b --- /dev/null +++ b/src/hotspot/cpu/x86/gc/z/z_x86_64.ad @@ -0,0 +1,168 @@ @@ -726,7 +726,7 @@ index 0000000..38c2e92 +%} + diff --git a/src/hotspot/cpu/x86/x86_64.ad b/src/hotspot/cpu/x86/x86_64.ad -index d127732..fce1b85 100644 +index 95a8538f3..ede4d8864 100644 --- a/src/hotspot/cpu/x86/x86_64.ad +++ b/src/hotspot/cpu/x86/x86_64.ad @@ -538,19 +538,6 @@ reg_class int_rdi_reg(RDI); @@ -749,7 +749,7 @@ index d127732..fce1b85 100644 //----------SOURCE BLOCK------------------------------------------------------- // This is a block of C++ code which provides values, functions, and // definitions necessary in the rest of the architecture description -@@ -1801,19 +1788,6 @@ const RegMask Matcher::method_handle_invoke_SP_save_mask() { +@@ -1882,19 +1869,6 @@ const RegMask Matcher::method_handle_invoke_SP_save_mask() { return NO_REG_mask(); } @@ -769,7 +769,7 @@ index d127732..fce1b85 100644 %} //----------ENCODING BLOCK----------------------------------------------------- -@@ -12555,131 +12529,6 @@ instruct RethrowException() +@@ -12845,131 +12819,6 @@ instruct RethrowException() ins_pipe(pipe_jmp); %} @@ -901,3 +901,6 @@ index d127732..fce1b85 100644 // ============================================================================ // This name is KNOWN by the ADLC and cannot be changed. // The ADLC forces a 'TypeRawPtr::BOTTOM' output type +-- +2.19.0 + diff --git a/8217918-C2-XX-AggressiveUnboxing-is-broken.patch b/8217918-C2-XX-AggressiveUnboxing-is-broken.patch deleted file mode 100755 index 03a94c27513b8b7fbb17ed319c482db16c2ca9d1..0000000000000000000000000000000000000000 --- a/8217918-C2-XX-AggressiveUnboxing-is-broken.patch +++ /dev/null @@ -1,263 +0,0 @@ -From 8da2787209da1906e3a92fff95dc46abe793b433 Mon Sep 17 00:00:00 2001 -Date: Thu, 18 Mar 2021 12:36:13 +0000 -Subject: [PATCH 3/4] 8217918: C2 -XX:+AggressiveUnboxing is broken - ---- - src/hotspot/share/opto/cfgnode.hpp | 4 +- - src/hotspot/share/opto/phaseX.cpp | 96 ++++++++++++++++++++++++------ - src/hotspot/share/opto/phaseX.hpp | 10 ++++ - src/hotspot/share/opto/type.cpp | 16 +++++ - src/hotspot/share/opto/type.hpp | 4 ++ - 5 files changed, 111 insertions(+), 19 deletions(-) - -diff --git a/src/hotspot/share/opto/cfgnode.hpp b/src/hotspot/share/opto/cfgnode.hpp -index 0d8c9b33b..04029ca91 100644 ---- a/src/hotspot/share/opto/cfgnode.hpp -+++ b/src/hotspot/share/opto/cfgnode.hpp -@@ -118,11 +118,13 @@ class JProjNode : public ProjNode { - // can turn PhiNodes into copys in-place by NULL'ing out their RegionNode - // input in slot 0. - class PhiNode : public TypeNode { -+ friend class PhaseRenumberLive; -+ - const TypePtr* const _adr_type; // non-null only for Type::MEMORY nodes. - // The following fields are only used for data PhiNodes to indicate - // that the PhiNode represents the value of a known instance field. - int _inst_mem_id; // Instance memory id (node index of the memory Phi) -- const int _inst_id; // Instance id of the memory slice. -+ int _inst_id; // Instance id of the memory slice. - const int _inst_index; // Alias index of the instance memory slice. - // Array elements references have the same alias_idx but different offset. - const int _inst_offset; // Offset of the instance memory slice. -diff --git a/src/hotspot/share/opto/phaseX.cpp b/src/hotspot/share/opto/phaseX.cpp -index 9d5d4deed..f4a38cd28 100644 ---- a/src/hotspot/share/opto/phaseX.cpp -+++ b/src/hotspot/share/opto/phaseX.cpp -@@ -463,55 +463,115 @@ PhaseRemoveUseless::PhaseRemoveUseless(PhaseGVN *gvn, Unique_Node_List *worklist - PhaseRenumberLive::PhaseRenumberLive(PhaseGVN* gvn, - Unique_Node_List* worklist, Unique_Node_List* new_worklist, - PhaseNumber phase_num) : -- PhaseRemoveUseless(gvn, worklist, Remove_Useless_And_Renumber_Live) { -- -+ PhaseRemoveUseless(gvn, worklist, Remove_Useless_And_Renumber_Live), -+ _new_type_array(C->comp_arena()), -+ _old2new_map(C->unique(), C->unique(), -1), -+ _delayed(Thread::current()->resource_area()), -+ _is_pass_finished(false), -+ _live_node_count(C->live_nodes()) -+{ - assert(RenumberLiveNodes, "RenumberLiveNodes must be set to true for node renumbering to take place"); - assert(C->live_nodes() == _useful.size(), "the number of live nodes must match the number of useful nodes"); - assert(gvn->nodes_size() == 0, "GVN must not contain any nodes at this point"); -+ assert(_delayed.size() == 0, "should be empty"); - -- uint old_unique_count = C->unique(); -- uint live_node_count = C->live_nodes(); - uint worklist_size = worklist->size(); - -- // Storage for the updated type information. -- Type_Array new_type_array(C->comp_arena()); -- - // Iterate over the set of live nodes. -- uint current_idx = 0; // The current new node ID. Incremented after every assignment. -- for (uint i = 0; i < _useful.size(); i++) { -- Node* n = _useful.at(i); -- // Sanity check that fails if we ever decide to execute this phase after EA -- assert(!n->is_Phi() || n->as_Phi()->inst_mem_id() == -1, "should not be linked to data Phi"); -- const Type* type = gvn->type_or_null(n); -- new_type_array.map(current_idx, type); -+ for (uint current_idx = 0; current_idx < _useful.size(); current_idx++) { -+ Node* n = _useful.at(current_idx); - - bool in_worklist = false; - if (worklist->member(n)) { - in_worklist = true; - } - -+ const Type* type = gvn->type_or_null(n); -+ _new_type_array.map(current_idx, type); -+ -+ assert(_old2new_map.at(n->_idx) == -1, "already seen"); -+ _old2new_map.at_put(n->_idx, current_idx); -+ - n->set_idx(current_idx); // Update node ID. - - if (in_worklist) { - new_worklist->push(n); - } - -- current_idx++; -+ if (update_embedded_ids(n) < 0) { -+ _delayed.push(n); // has embedded IDs; handle later -+ } - } - - assert(worklist_size == new_worklist->size(), "the new worklist must have the same size as the original worklist"); -- assert(live_node_count == current_idx, "all live nodes must be processed"); -+ assert(_live_node_count == _useful.size(), "all live nodes must be processed"); -+ -+ _is_pass_finished = true; // pass finished; safe to process delayed updates -+ -+ while (_delayed.size() > 0) { -+ Node* n = _delayed.pop(); -+ int no_of_updates = update_embedded_ids(n); -+ assert(no_of_updates > 0, "should be updated"); -+ } - - // Replace the compiler's type information with the updated type information. -- gvn->replace_types(new_type_array); -+ gvn->replace_types(_new_type_array); - - // Update the unique node count of the compilation to the number of currently live nodes. -- C->set_unique(live_node_count); -+ C->set_unique(_live_node_count); - - // Set the dead node count to 0 and reset dead node list. - C->reset_dead_node_list(); - } - -+int PhaseRenumberLive::new_index(int old_idx) { -+ assert(_is_pass_finished, "not finished"); -+ if (_old2new_map.at(old_idx) == -1) { // absent -+ // Allocate a placeholder to preserve uniqueness -+ _old2new_map.at_put(old_idx, _live_node_count); -+ _live_node_count++; -+ } -+ return _old2new_map.at(old_idx); -+} -+ -+int PhaseRenumberLive::update_embedded_ids(Node* n) { -+ int no_of_updates = 0; -+ if (n->is_Phi()) { -+ PhiNode* phi = n->as_Phi(); -+ if (phi->_inst_id != -1) { -+ if (!_is_pass_finished) { -+ return -1; // delay -+ } -+ int new_idx = new_index(phi->_inst_id); -+ assert(new_idx != -1, ""); -+ phi->_inst_id = new_idx; -+ no_of_updates++; -+ } -+ if (phi->_inst_mem_id != -1) { -+ if (!_is_pass_finished) { -+ return -1; // delay -+ } -+ int new_idx = new_index(phi->_inst_mem_id); -+ assert(new_idx != -1, ""); -+ phi->_inst_mem_id = new_idx; -+ no_of_updates++; -+ } -+ } -+ -+ const Type* type = _new_type_array.fast_lookup(n->_idx); -+ if (type != NULL && type->isa_oopptr() && type->is_oopptr()->is_known_instance()) { -+ if (!_is_pass_finished) { -+ return -1; // delay -+ } -+ int old_idx = type->is_oopptr()->instance_id(); -+ int new_idx = new_index(old_idx); -+ const Type* new_type = type->is_oopptr()->with_instance_id(new_idx); -+ _new_type_array.map(n->_idx, new_type); -+ no_of_updates++; -+ } -+ -+ return no_of_updates; -+} - - //============================================================================= - //------------------------------PhaseTransform--------------------------------- -diff --git a/src/hotspot/share/opto/phaseX.hpp b/src/hotspot/share/opto/phaseX.hpp -index 3b33a8cb2..ef5eb488e 100644 ---- a/src/hotspot/share/opto/phaseX.hpp -+++ b/src/hotspot/share/opto/phaseX.hpp -@@ -157,6 +157,16 @@ public: - // Phase that first performs a PhaseRemoveUseless, then it renumbers compiler - // structures accordingly. - class PhaseRenumberLive : public PhaseRemoveUseless { -+protected: -+ Type_Array _new_type_array; // Storage for the updated type information. -+ GrowableArray _old2new_map; -+ Node_List _delayed; -+ bool _is_pass_finished; -+ uint _live_node_count; -+ -+ int update_embedded_ids(Node* n); -+ int new_index(int old_idx); -+ - public: - PhaseRenumberLive(PhaseGVN* gvn, - Unique_Node_List* worklist, Unique_Node_List* new_worklist, -diff --git a/src/hotspot/share/opto/type.cpp b/src/hotspot/share/opto/type.cpp -index 0078b8773..964f9d247 100644 ---- a/src/hotspot/share/opto/type.cpp -+++ b/src/hotspot/share/opto/type.cpp -@@ -3456,6 +3456,12 @@ const TypePtr* TypeOopPtr::with_inline_depth(int depth) const { - return make(_ptr, _offset, _instance_id, _speculative, depth); - } - -+//------------------------------with_instance_id-------------------------------- -+const TypePtr* TypeOopPtr::with_instance_id(int instance_id) const { -+ assert(_instance_id != -1, "should be known"); -+ return make(_ptr, _offset, instance_id, _speculative, _inline_depth); -+} -+ - //------------------------------meet_instance_id-------------------------------- - int TypeOopPtr::meet_instance_id( int instance_id ) const { - // Either is 'TOP' instance? Return the other instance! -@@ -4059,6 +4065,11 @@ const TypePtr *TypeInstPtr::with_inline_depth(int depth) const { - return make(_ptr, klass(), klass_is_exact(), const_oop(), _offset, _instance_id, _speculative, depth); - } - -+const TypePtr *TypeInstPtr::with_instance_id(int instance_id) const { -+ assert(is_known_instance(), "should be known"); -+ return make(_ptr, klass(), klass_is_exact(), const_oop(), _offset, instance_id, _speculative, _inline_depth); -+} -+ - //============================================================================= - // Convenience common pre-built types. - const TypeAryPtr *TypeAryPtr::RANGE; -@@ -4529,6 +4540,11 @@ const TypePtr *TypeAryPtr::with_inline_depth(int depth) const { - return make(_ptr, _const_oop, _ary->remove_speculative()->is_ary(), _klass, _klass_is_exact, _offset, _instance_id, _speculative, depth); - } - -+const TypePtr *TypeAryPtr::with_instance_id(int instance_id) const { -+ assert(is_known_instance(), "should be known"); -+ return make(_ptr, _const_oop, _ary->remove_speculative()->is_ary(), _klass, _klass_is_exact, _offset, instance_id, _speculative, _inline_depth); -+} -+ - //============================================================================= - - //------------------------------hash------------------------------------------- -diff --git a/src/hotspot/share/opto/type.hpp b/src/hotspot/share/opto/type.hpp -index ca92fe3ab..e9ed7ce40 100644 ---- a/src/hotspot/share/opto/type.hpp -+++ b/src/hotspot/share/opto/type.hpp -@@ -1048,6 +1048,8 @@ public: - virtual bool would_improve_type(ciKlass* exact_kls, int inline_depth) const; - virtual const TypePtr* with_inline_depth(int depth) const; - -+ virtual const TypePtr* with_instance_id(int instance_id) const; -+ - virtual const Type *xdual() const; // Compute dual right now. - // the core of the computation of the meet for TypeOopPtr and for its subclasses - virtual const Type *xmeet_helper(const Type *t) const; -@@ -1124,6 +1126,7 @@ class TypeInstPtr : public TypeOopPtr { - // Speculative type helper methods. - virtual const Type* remove_speculative() const; - virtual const TypePtr* with_inline_depth(int depth) const; -+ virtual const TypePtr* with_instance_id(int instance_id) const; - - // the core of the computation of the meet of 2 types - virtual const Type *xmeet_helper(const Type *t) const; -@@ -1211,6 +1214,7 @@ public: - // Speculative type helper methods. - virtual const Type* remove_speculative() const; - virtual const TypePtr* with_inline_depth(int depth) const; -+ virtual const TypePtr* with_instance_id(int instance_id) const; - - // the core of the computation of the meet of 2 types - virtual const Type *xmeet_helper(const Type *t) const; --- -2.19.0 - diff --git a/8223667-ASAN-build-broken.patch b/8223667-ASAN-build-broken.patch deleted file mode 100644 index c9fd099bba08debd735ee5afc44d2c94a83b3009..0000000000000000000000000000000000000000 --- a/8223667-ASAN-build-broken.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 2d8c2049c7caad19e6cacccea1bc8962ac481f5a Mon Sep 17 00:00:00 2001 -Date: Wed, 17 Jun 2020 10:10:35 +0000 -Subject: [PATCH] 8223667: ASAN build broken - -Summary: : -LLT: N/A -Bug url: https://bugs.openjdk.java.net/browse/JDK-8223667 ---- - make/autoconf/spec.gmk.in | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/make/autoconf/spec.gmk.in b/make/autoconf/spec.gmk.in -index 9473481bc..38fa47d9f 100644 ---- a/make/autoconf/spec.gmk.in -+++ b/make/autoconf/spec.gmk.in -@@ -382,7 +382,7 @@ GCOV_ENABLED=@GCOV_ENABLED@ - export ASAN_ENABLED:=@ASAN_ENABLED@ - export DEVKIT_LIB_DIR:=@DEVKIT_LIB_DIR@ - ifeq ($(ASAN_ENABLED), yes) -- export ASAN_OPTIONS="handle_segv=0 detect_leaks=0" -+ export ASAN_OPTIONS=handle_segv=0 detect_leaks=0 - ifneq ($(DEVKIT_LIB_DIR),) - export LD_LIBRARY_PATH:=$(LD_LIBRARY_PATH):$(DEVKIT_LIB_DIR) - endif --- -1.8.3.1 diff --git a/8264640.patch b/8264640.patch deleted file mode 100755 index 18413b89827ea820feb13a4784632f603ae77fd3..0000000000000000000000000000000000000000 --- a/8264640.patch +++ /dev/null @@ -1,20 +0,0 @@ -diff --git a/src/hotspot/share/gc/cms/parOopClosures.inline.hpp b/src/hotspot/share/gc/cms/parOopClosures.inline.hpp -index 1e206292d..609a14868 100644 ---- a/src/hotspot/share/gc/cms/parOopClosures.inline.hpp -+++ b/src/hotspot/share/gc/cms/parOopClosures.inline.hpp -@@ -44,6 +44,7 @@ template inline void ParScanWeakRefClosure::do_oop_work(T* p) { - // we need to ensure that it is copied (see comment in - // ParScanClosure::do_oop_work). - Klass* objK = obj->klass(); -+ OrderAccess::loadload(); - markOop m = obj->mark_raw(); - oop new_obj; - if (m->is_marked()) { // Contains forwarding pointer. -@@ -108,6 +109,7 @@ inline void ParScanClosure::do_oop_work(T* p, - // overwritten with an overflow next pointer after the object is - // forwarded. - Klass* objK = obj->klass(); -+ OrderAccess::loadload(); - markOop m = obj->mark_raw(); - oop new_obj; - if (m->is_marked()) { // Contains forwarding pointer. diff --git a/add-LazyBox-feature.patch b/add-LazyBox-feature.patch old mode 100755 new mode 100644 index 25d293e4e98ae668ecb2b1c60f1c11b4b5adba04..d07d1c6c3a052d2fa1eadfd04c566adab2ddd682 --- a/add-LazyBox-feature.patch +++ b/add-LazyBox-feature.patch @@ -1,30 +1,3 @@ -From 616dd14fb435476b0f9fb6696084fd71dd6ecc05 Mon Sep 17 00:00:00 2001 -Date: Tue, 16 Mar 2021 07:00:07 +0000 -Subject: [PATCH 2/4] add LazyBox feature - ---- - src/hotspot/share/opto/c2_globals.hpp | 6 + - src/hotspot/share/opto/callGenerator.cpp | 33 ++- - src/hotspot/share/opto/callnode.cpp | 18 ++ - src/hotspot/share/opto/callnode.hpp | 15 ++ - src/hotspot/share/opto/compile.cpp | 5 + - src/hotspot/share/opto/doCall.cpp | 50 +++++ - src/hotspot/share/opto/graphKit.cpp | 189 +++++++++++++++- - src/hotspot/share/opto/graphKit.hpp | 9 + - src/hotspot/share/opto/parse.hpp | 3 + - src/hotspot/share/opto/parse1.cpp | 2 +- - src/hotspot/share/opto/parse2.cpp | 25 ++- - src/hotspot/share/opto/parse3.cpp | 8 + - src/hotspot/share/opto/phase.hpp | 1 + - src/hotspot/share/opto/phaseX.cpp | 211 ++++++++++++++++++ - src/hotspot/share/opto/phaseX.hpp | 20 ++ - src/hotspot/share/opto/phasetype.hpp | 2 + - src/hotspot/share/runtime/arguments.cpp | 13 ++ - .../jvm/hotspot/opto/CompilerPhaseType.java | 1 + - .../jtreg/compiler/lazybox/TestLazyBox.java | 82 +++++++ - 19 files changed, 679 insertions(+), 14 deletions(-) - create mode 100644 test/hotspot/jtreg/compiler/lazybox/TestLazyBox.java - diff --git a/src/hotspot/share/opto/c2_globals.hpp b/src/hotspot/share/opto/c2_globals.hpp index 8111a63d4..84c2817e3 100644 --- a/src/hotspot/share/opto/c2_globals.hpp @@ -43,7 +16,7 @@ index 8111a63d4..84c2817e3 100644 " register allocation.") \ \ diff --git a/src/hotspot/share/opto/callGenerator.cpp b/src/hotspot/share/opto/callGenerator.cpp -index ffe50ed86..a5846537d 100644 +index 59a02fbb1..11df8b6f5 100644 --- a/src/hotspot/share/opto/callGenerator.cpp +++ b/src/hotspot/share/opto/callGenerator.cpp @@ -150,12 +150,15 @@ JVMState* DirectCallGenerator::generate(JVMState* jvms) { @@ -137,7 +110,7 @@ index c4064dca0..f17eda879 100644 // Add a LockNode, which points to both the original BoxLockNode (the // stack space for the monitor) and the Object being locked. diff --git a/src/hotspot/share/opto/callnode.hpp b/src/hotspot/share/opto/callnode.hpp -index cc65d9ef9..c7ea73946 100644 +index cde33ad8b..0e07bdd62 100644 --- a/src/hotspot/share/opto/callnode.hpp +++ b/src/hotspot/share/opto/callnode.hpp @@ -331,6 +331,7 @@ public: @@ -194,10 +167,10 @@ index cc65d9ef9..c7ea73946 100644 bool _is_scalar_replaceable; bool _is_non_escaping; diff --git a/src/hotspot/share/opto/compile.cpp b/src/hotspot/share/opto/compile.cpp -index f350f9d68..838147f53 100644 +index 9c8474f18..2f188ea53 100644 --- a/src/hotspot/share/opto/compile.cpp +++ b/src/hotspot/share/opto/compile.cpp -@@ -2235,6 +2235,11 @@ void Compile::Optimize() { +@@ -2237,6 +2237,11 @@ void Compile::Optimize() { print_method(PHASE_AFTER_PARSING); @@ -210,10 +183,10 @@ index f350f9d68..838147f53 100644 // Iterative Global Value Numbering, including ideal transforms // Initialize IterGVN with types and values from parse-time GVN diff --git a/src/hotspot/share/opto/doCall.cpp b/src/hotspot/share/opto/doCall.cpp -index c9d06a833..343e9d00d 100644 +index dfcc8c402..6db88965b 100644 --- a/src/hotspot/share/opto/doCall.cpp +++ b/src/hotspot/share/opto/doCall.cpp -@@ -416,6 +416,49 @@ static bool check_call_consistency(JVMState* jvms, CallGenerator* cg) { +@@ -418,6 +418,49 @@ static bool check_call_consistency(JVMState* jvms, CallGenerator* cg) { } #endif // ASSERT @@ -263,7 +236,7 @@ index c9d06a833..343e9d00d 100644 //------------------------------do_call---------------------------------------- // Handle your basic call. Inline if we can & want to, else just setup call. void Parse::do_call() { -@@ -552,6 +595,13 @@ void Parse::do_call() { +@@ -554,6 +597,13 @@ void Parse::do_call() { // It decides whether inlining is desirable or not. CallGenerator* cg = C->call_generator(callee, vtable_index, call_does_dispatch, jvms, try_inline, prof_factor(), speculative_receiver_type); @@ -278,7 +251,7 @@ index c9d06a833..343e9d00d 100644 orig_callee = callee = NULL; diff --git a/src/hotspot/share/opto/graphKit.cpp b/src/hotspot/share/opto/graphKit.cpp -index 219d272ff..356bd5ccc 100644 +index 6d4949de2..22222efbc 100644 --- a/src/hotspot/share/opto/graphKit.cpp +++ b/src/hotspot/share/opto/graphKit.cpp @@ -31,6 +31,7 @@ @@ -306,7 +279,7 @@ index 219d272ff..356bd5ccc 100644 assert(is_hidden_merge(dstphi), "must be a special merge node"); assert(is_hidden_merge(srcphi), "must be a special merge node"); @@ -840,6 +850,19 @@ static bool should_reexecute_implied_by_bytecode(JVMState *jvms, bool is_anewarr - return false; + } } +// Delay boxnode to uncommon trap @@ -335,7 +308,7 @@ index 219d272ff..356bd5ccc 100644 // Walk the inline list to fill in the correct set of JVMState's // Also fill in the associated edges for each JVMState. -@@ -910,6 +934,9 @@ void GraphKit::add_safepoint_edges(SafePointNode* call, bool must_throw) { +@@ -916,6 +940,9 @@ void GraphKit::add_safepoint_edges(SafePointNode* call, bool must_throw) { // Fill pointer walks backwards from "young:" to "root:" in the diagram above: uint debug_ptr = call->req(); @@ -345,7 +318,7 @@ index 219d272ff..356bd5ccc 100644 // Loop over the map input edges associated with jvms, add them // to the call node, & reset all offsets to match call node array. for (JVMState* in_jvms = youngest_jvms; in_jvms != NULL; ) { -@@ -938,7 +965,7 @@ void GraphKit::add_safepoint_edges(SafePointNode* call, bool must_throw) { +@@ -944,7 +971,7 @@ void GraphKit::add_safepoint_edges(SafePointNode* call, bool must_throw) { out_jvms->set_locoff(p); if (!can_prune_locals) { for (j = 0; j < l; j++) @@ -354,7 +327,7 @@ index 219d272ff..356bd5ccc 100644 } else { p += l; // already set to top above by add_req_batch } -@@ -949,7 +976,7 @@ void GraphKit::add_safepoint_edges(SafePointNode* call, bool must_throw) { +@@ -955,7 +982,7 @@ void GraphKit::add_safepoint_edges(SafePointNode* call, bool must_throw) { out_jvms->set_stkoff(p); if (!can_prune_locals) { for (j = 0; j < l; j++) @@ -363,7 +336,7 @@ index 219d272ff..356bd5ccc 100644 } else if (can_prune_locals && stack_slots_not_pruned != 0) { // Divide stack into {S0,...,S1}, where S0 is set to top. uint s1 = stack_slots_not_pruned; -@@ -958,7 +985,8 @@ void GraphKit::add_safepoint_edges(SafePointNode* call, bool must_throw) { +@@ -964,7 +991,8 @@ void GraphKit::add_safepoint_edges(SafePointNode* call, bool must_throw) { uint s0 = l - s1; p += s0; // skip the tops preinstalled by add_req_batch for (j = s0; j < l; j++) @@ -373,7 +346,7 @@ index 219d272ff..356bd5ccc 100644 } else { p += l; // already set to top above by add_req_batch } -@@ -992,6 +1020,35 @@ void GraphKit::add_safepoint_edges(SafePointNode* call, bool must_throw) { +@@ -998,6 +1026,35 @@ void GraphKit::add_safepoint_edges(SafePointNode* call, bool must_throw) { in_jvms = in_jvms->caller(); } @@ -409,7 +382,7 @@ index 219d272ff..356bd5ccc 100644 assert(debug_ptr == non_debug_edges, "debug info must fit exactly"); // Test the correctness of JVMState::debug_xxx accessors: -@@ -4017,6 +4074,130 @@ void GraphKit::inflate_string_slow(Node* src, Node* dst, Node* start, Node* coun +@@ -4031,6 +4088,130 @@ void GraphKit::inflate_string_slow(Node* src, Node* dst, Node* start, Node* coun set_memory(st, TypeAryPtr::BYTES); } @@ -589,10 +562,10 @@ index aa13e8863..b16671ace 100644 void do_call(); diff --git a/src/hotspot/share/opto/parse1.cpp b/src/hotspot/share/opto/parse1.cpp -index f94f028c6..48f111d76 100644 +index e12d1e5d3..561fe0690 100644 --- a/src/hotspot/share/opto/parse1.cpp +++ b/src/hotspot/share/opto/parse1.cpp -@@ -918,7 +918,7 @@ void Parse::do_exceptions() { +@@ -919,7 +919,7 @@ void Parse::do_exceptions() { SafePointNode* ex_map; while ((ex_map = pop_exception_state()) != NULL) { @@ -602,10 +575,10 @@ index f94f028c6..48f111d76 100644 // Doing it this early allows the exceptions to common up // even between adjacent method calls. diff --git a/src/hotspot/share/opto/parse2.cpp b/src/hotspot/share/opto/parse2.cpp -index 2b21881bc..78e83afa5 100644 +index 85bba6a50..027e32cec 100644 --- a/src/hotspot/share/opto/parse2.cpp +++ b/src/hotspot/share/opto/parse2.cpp -@@ -2660,9 +2660,17 @@ void Parse::do_one_bytecode() { +@@ -2672,9 +2672,17 @@ void Parse::do_one_bytecode() { case Bytecodes::_return: return_current(NULL); break; @@ -625,7 +598,7 @@ index 2b21881bc..78e83afa5 100644 case Bytecodes::_freturn: return_current(pop()); break; -@@ -2749,6 +2757,19 @@ void Parse::do_one_bytecode() { +@@ -2761,6 +2769,19 @@ void Parse::do_one_bytecode() { maybe_add_safepoint(iter().get_dest()); a = pop(); b = pop(); @@ -677,10 +650,10 @@ index 4b0c53ffc..38683f8a7 100644 }; diff --git a/src/hotspot/share/opto/phaseX.cpp b/src/hotspot/share/opto/phaseX.cpp -index f4a38cd28..c2060e445 100644 +index 0a285315d..b3e2fb9b9 100644 --- a/src/hotspot/share/opto/phaseX.cpp +++ b/src/hotspot/share/opto/phaseX.cpp -@@ -407,6 +407,217 @@ void NodeHash::operator=(const NodeHash& nh) { +@@ -412,6 +412,217 @@ void NodeHash::operator=(const NodeHash& nh) { #endif @@ -899,7 +872,7 @@ index f4a38cd28..c2060e445 100644 //============================================================================= //------------------------------PhaseRemoveUseless----------------------------- diff --git a/src/hotspot/share/opto/phaseX.hpp b/src/hotspot/share/opto/phaseX.hpp -index ef5eb488e..915884b33 100644 +index 0591e9807..5a55b75e2 100644 --- a/src/hotspot/share/opto/phaseX.hpp +++ b/src/hotspot/share/opto/phaseX.hpp @@ -173,6 +173,26 @@ public: diff --git a/add-SVE-backend-feature.patch b/add-SVE-backend-feature.patch old mode 100755 new mode 100644 index 1d51d8fcb132bcb878bce13b95a1b284b2410ac2..efd0689252765510589845cca0faa70beff722aa --- a/add-SVE-backend-feature.patch +++ b/add-SVE-backend-feature.patch @@ -1,10 +1,10 @@ diff --git a/make/hotspot/gensrc/GensrcAdlc.gmk b/make/hotspot/gensrc/GensrcAdlc.gmk -index bb9721c8e..3774dd730 100644 +index a39640526..2479853fa 100644 --- a/make/hotspot/gensrc/GensrcAdlc.gmk +++ b/make/hotspot/gensrc/GensrcAdlc.gmk -@@ -140,6 +140,12 @@ ifeq ($(call check-jvm-feature, compiler2), true) - $d/os_cpu/$(HOTSPOT_TARGET_OS)_$(HOTSPOT_TARGET_CPU_ARCH)/$(HOTSPOT_TARGET_OS)_$(HOTSPOT_TARGET_CPU_ARCH).ad \ - ))) +@@ -146,6 +146,12 @@ ifeq ($(call check-jvm-feature, compiler2), true) + ))) + endif + ifeq ($(HOTSPOT_TARGET_CPU_ARCH), aarch64) + AD_SRC_FILES += $(call uniq, $(wildcard $(foreach d, $(AD_SRC_ROOTS), \ @@ -12,11 +12,11 @@ index bb9721c8e..3774dd730 100644 + ))) + endif + - ifeq ($(call check-jvm-feature, zgc), true) + ifeq ($(call check-jvm-feature, shenandoahgc), true) AD_SRC_FILES += $(call uniq, $(wildcard $(foreach d, $(AD_SRC_ROOTS), \ - $d/cpu/$(HOTSPOT_TARGET_CPU_ARCH)/gc/z/z_$(HOTSPOT_TARGET_CPU).ad \ + $d/cpu/$(HOTSPOT_TARGET_CPU_ARCH)/gc/shenandoah/shenandoah_$(HOTSPOT_TARGET_CPU).ad \ diff --git a/src/hotspot/cpu/aarch64/aarch64.ad b/src/hotspot/cpu/aarch64/aarch64.ad -index 617b2b8fb..eab0101b0 100644 +index b64919a62..fa434df7d 100644 --- a/src/hotspot/cpu/aarch64/aarch64.ad +++ b/src/hotspot/cpu/aarch64/aarch64.ad @@ -69,7 +69,7 @@ register %{ @@ -524,15 +524,7 @@ index 617b2b8fb..eab0101b0 100644 // ---------------------------- // Special Registers -@@ -333,7 +488,6 @@ reg_def R31_H ( NS, NS, Op_RegI, 31, r31_sp->as_VMReg()->next()); - - reg_def RFLAGS(SOC, SOC, 0, 32, VMRegImpl::Bad()); - -- - // Specify priority of register selection within phases of register - // allocation. Highest priority is first. A useful heuristic is to - // give registers a low priority when they are required by machine -@@ -381,50 +535,64 @@ alloc_class chunk0( +@@ -381,50 +536,64 @@ alloc_class chunk0( R29, R29_H, // fp R30, R30_H, // lr R31, R31_H, // sp @@ -611,8 +603,9 @@ index 617b2b8fb..eab0101b0 100644 + V13, V13_H, V13_J, V13_K, V13_L, V13_M, V13_N, V13_O, + V14, V14_H, V14_J, V14_K, V14_L, V14_M, V14_N, V14_O, + V15, V15_H, V15_J, V15_K, V15_L, V15_M, V15_N, V15_O, -+); -+ + ); + +-alloc_class chunk2(RFLAGS); +alloc_class chunk2 ( + P0, + P1, @@ -623,14 +616,13 @@ index 617b2b8fb..eab0101b0 100644 + P6, + P7, + // Only use P0~P7 here for performance - ); - --alloc_class chunk2(RFLAGS); ++); ++ +alloc_class chunk3(RFLAGS); //----------Architecture Description Register Classes-------------------------- // Several register classes are automatically defined based upon information in -@@ -865,6 +1033,42 @@ reg_class double_reg( +@@ -865,6 +1034,42 @@ reg_class double_reg( V31, V31_H ); @@ -673,7 +665,7 @@ index 617b2b8fb..eab0101b0 100644 // Class for all 64bit vector registers reg_class vectord_reg( V0, V0_H, -@@ -1097,6 +1301,31 @@ reg_class v31_reg( +@@ -1097,6 +1302,31 @@ reg_class v31_reg( V31, V31_H ); @@ -705,7 +697,7 @@ index 617b2b8fb..eab0101b0 100644 // Singleton class for condition codes reg_class int_flags(RFLAGS); -@@ -1758,6 +1987,10 @@ void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { +@@ -1761,6 +1991,10 @@ void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { // branch if we need to invalidate the method later __ nop(); @@ -716,7 +708,7 @@ index 617b2b8fb..eab0101b0 100644 int bangsize = C->bang_size_in_bytes(); if (C->need_stack_bang(bangsize) && UseStackBanging) __ generate_stack_overflow_check(bangsize); -@@ -1859,7 +2092,7 @@ int MachEpilogNode::safepoint_offset() const { +@@ -1862,7 +2096,7 @@ int MachEpilogNode::safepoint_offset() const { // Figure out which register class each belongs in: rc_int, rc_float or // rc_stack. @@ -725,22 +717,22 @@ index 617b2b8fb..eab0101b0 100644 static enum RC rc_class(OptoReg::Name reg) { -@@ -1867,19 +2100,25 @@ static enum RC rc_class(OptoReg::Name reg) { +@@ -1870,20 +2104,25 @@ static enum RC rc_class(OptoReg::Name reg) { return rc_bad; } - // we have 30 int registers * 2 halves - // (rscratch1 and rscratch2 are omitted) +- int slots_of_int_registers = RegisterImpl::max_slots_per_register * (RegisterImpl::number_of_registers - 2); + // we have 32 int registers * 2 halves + int slots_of_int_registers = RegisterImpl::max_slots_per_register * RegisterImpl::number_of_registers; -- if (reg < 60) { -+ if (reg < slots_of_int_registers) { + if (reg < slots_of_int_registers) { return rc_int; } -- // we have 32 float register * 2 halves -- if (reg < 60 + 128) { +- // we have 32 float register * 4 halves +- if (reg < slots_of_int_registers + FloatRegisterImpl::max_slots_per_register * FloatRegisterImpl::number_of_registers) { + // we have 32 float register * 8 halves + int slots_of_float_registers = FloatRegisterImpl::max_slots_per_register * FloatRegisterImpl::number_of_registers; + if (reg < slots_of_int_registers + slots_of_float_registers) { @@ -757,7 +749,7 @@ index 617b2b8fb..eab0101b0 100644 assert(OptoReg::is_stack(reg), "blow up if spilling flags"); return rc_stack; -@@ -1918,8 +2157,28 @@ uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, boo +@@ -1922,8 +2161,28 @@ uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, boo if (bottom_type()->isa_vect() != NULL) { uint ireg = ideal_reg(); @@ -788,7 +780,7 @@ index 617b2b8fb..eab0101b0 100644 MacroAssembler _masm(cbuf); assert((src_lo_rc != rc_int && dst_lo_rc != rc_int), "sanity"); if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) { -@@ -1937,12 +2196,12 @@ uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, boo +@@ -1941,12 +2200,12 @@ uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, boo as_FloatRegister(Matcher::_regEncode[src_lo])); } else if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) { __ spill(as_FloatRegister(Matcher::_regEncode[src_lo]), @@ -801,11 +793,11 @@ index 617b2b8fb..eab0101b0 100644 - ireg == Op_VecD ? __ D : __ Q, - ra_->reg2offset(src_lo)); + ireg == Op_VecD ? __ D : __ Q, -+ ra_->reg2offset(src_lo)); ++ ra_->reg2offset(src_lo)); } else { ShouldNotReachHere(); } -@@ -2027,9 +2286,24 @@ uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, boo +@@ -2031,9 +2290,24 @@ uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, boo st->print("%s", Matcher::regName[dst_lo]); } if (bottom_type()->isa_vect() != NULL) { @@ -832,7 +824,7 @@ index 617b2b8fb..eab0101b0 100644 } } -@@ -2188,19 +2462,32 @@ const bool Matcher::match_rule_supported(int opcode) { +@@ -2192,19 +2466,32 @@ const bool Matcher::match_rule_supported(int opcode) { return true; // Per default match rules are supported. } @@ -875,7 +867,7 @@ index 617b2b8fb..eab0101b0 100644 } const int Matcher::float_pressure(int default_pressure_threshold) { -@@ -2236,7 +2523,8 @@ const bool Matcher::convL2FSupported(void) { +@@ -2240,7 +2527,8 @@ const bool Matcher::convL2FSupported(void) { // Vector width in bytes. const int Matcher::vector_width_in_bytes(BasicType bt) { @@ -885,7 +877,7 @@ index 617b2b8fb..eab0101b0 100644 // Minimum 2 values in vector if (size < 2*type2aelembytes(bt)) size = 0; // But never < 4 -@@ -2249,14 +2537,32 @@ const int Matcher::max_vector_size(const BasicType bt) { +@@ -2253,14 +2541,32 @@ const int Matcher::max_vector_size(const BasicType bt) { return vector_width_in_bytes(bt)/type2aelembytes(bt); } const int Matcher::min_vector_size(const BasicType bt) { @@ -895,7 +887,7 @@ index 617b2b8fb..eab0101b0 100644 + // Currently vector length less than SVE vector register size is not supported. + return max_size; + } else { -+ // For the moment limit the vector size to 8 bytes with NEON. ++ // For the moment limit the vector size to 8 bytes with NEON. int size = 8 / type2aelembytes(bt); if (size < 2) size = 2; return size; @@ -919,7 +911,7 @@ index 617b2b8fb..eab0101b0 100644 switch(len) { case 8: return Op_VecD; case 16: return Op_VecX; -@@ -2266,6 +2572,9 @@ const uint Matcher::vector_ideal_reg(int len) { +@@ -2270,6 +2576,9 @@ const uint Matcher::vector_ideal_reg(int len) { } const uint Matcher::vector_shift_count_ideal_reg(int size) { @@ -930,18 +922,18 @@ index 617b2b8fb..eab0101b0 100644 case 8: return Op_VecD; case 16: return Op_VecX; @@ -3419,6 +3728,11 @@ encode %{ - if (call == NULL) { - ciEnv::current()->record_failure("CodeCache is full"); - return; + if (call == NULL) { + ciEnv::current()->record_failure("CodeCache is full"); + return; + } else if (UseSVE > 0 && Compile::current()->max_vector_size() >= 16) { + // Only non uncommon_trap calls need to reinitialize ptrue. + if (uncommon_trap_request() == 0) { + __ reinitialize_ptrue(); + } - } - %} - -@@ -3429,6 +3743,8 @@ encode %{ + } + // Emit stub for static call + address stub = CompiledStaticCall::emit_to_interp_stub(cbuf); +@@ -3436,6 +3750,8 @@ encode %{ if (call == NULL) { ciEnv::current()->record_failure("CodeCache is full"); return; @@ -950,7 +942,7 @@ index 617b2b8fb..eab0101b0 100644 } %} -@@ -3465,6 +3781,9 @@ encode %{ +@@ -3472,6 +3788,9 @@ encode %{ __ bind(retaddr); __ add(sp, sp, 2 * wordSize); } @@ -960,7 +952,7 @@ index 617b2b8fb..eab0101b0 100644 %} enc_class aarch64_enc_rethrow() %{ -@@ -3474,6 +3793,11 @@ encode %{ +@@ -3481,6 +3800,11 @@ encode %{ enc_class aarch64_enc_ret() %{ MacroAssembler _masm(&cbuf); @@ -972,7 +964,7 @@ index 617b2b8fb..eab0101b0 100644 __ ret(lr); %} -@@ -4203,6 +4527,41 @@ operand immLoffset16() +@@ -4222,6 +4546,41 @@ operand immLoffset16() interface(CONST_INTER); %} @@ -1014,7 +1006,7 @@ index 617b2b8fb..eab0101b0 100644 // 32 bit integer valid for add sub immediate operand immIAddSub() %{ -@@ -4832,6 +5191,18 @@ operand vRegD() +@@ -4851,6 +5210,18 @@ operand vRegD() interface(REG_INTER); %} @@ -1033,7 +1025,7 @@ index 617b2b8fb..eab0101b0 100644 operand vecD() %{ constraint(ALLOC_IN_RC(vectord_reg)); -@@ -5140,6 +5511,15 @@ operand vRegD_V31() +@@ -5159,6 +5530,15 @@ operand vRegD_V31() interface(REG_INTER); %} @@ -1049,7 +1041,7 @@ index 617b2b8fb..eab0101b0 100644 // Flags register, used as output of signed compare instructions // note that on AArch64 we also use this register as the output for -@@ -15477,7 +15857,7 @@ instruct loadV8(vecD dst, vmem8 mem) +@@ -15745,7 +16125,7 @@ instruct loadV8(vecD dst, vmem8 mem) // Load Vector (128 bits) instruct loadV16(vecX dst, vmem16 mem) %{ @@ -1058,7 +1050,7 @@ index 617b2b8fb..eab0101b0 100644 match(Set dst (LoadVector mem)); ins_cost(4 * INSN_COST); format %{ "ldrq $dst,$mem\t# vector (128 bits)" %} -@@ -15533,7 +15913,7 @@ instruct replicate8B(vecD dst, iRegIorL2I src) +@@ -15801,7 +16181,7 @@ instruct replicate8B(vecD dst, iRegIorL2I src) instruct replicate16B(vecX dst, iRegIorL2I src) %{ @@ -1067,7 +1059,7 @@ index 617b2b8fb..eab0101b0 100644 match(Set dst (ReplicateB src)); ins_cost(INSN_COST); format %{ "dup $dst, $src\t# vector (16B)" %} -@@ -15558,7 +15938,7 @@ instruct replicate8B_imm(vecD dst, immI con) +@@ -15826,7 +16206,7 @@ instruct replicate8B_imm(vecD dst, immI con) instruct replicate16B_imm(vecX dst, immI con) %{ @@ -1076,7 +1068,7 @@ index 617b2b8fb..eab0101b0 100644 match(Set dst (ReplicateB con)); ins_cost(INSN_COST); format %{ "movi $dst, $con\t# vector(16B)" %} -@@ -15583,7 +15963,7 @@ instruct replicate4S(vecD dst, iRegIorL2I src) +@@ -15851,7 +16231,7 @@ instruct replicate4S(vecD dst, iRegIorL2I src) instruct replicate8S(vecX dst, iRegIorL2I src) %{ @@ -1085,7 +1077,7 @@ index 617b2b8fb..eab0101b0 100644 match(Set dst (ReplicateS src)); ins_cost(INSN_COST); format %{ "dup $dst, $src\t# vector (8S)" %} -@@ -15608,7 +15988,7 @@ instruct replicate4S_imm(vecD dst, immI con) +@@ -15876,7 +16256,7 @@ instruct replicate4S_imm(vecD dst, immI con) instruct replicate8S_imm(vecX dst, immI con) %{ @@ -1094,7 +1086,7 @@ index 617b2b8fb..eab0101b0 100644 match(Set dst (ReplicateS con)); ins_cost(INSN_COST); format %{ "movi $dst, $con\t# vector(8H)" %} -@@ -15632,7 +16012,7 @@ instruct replicate2I(vecD dst, iRegIorL2I src) +@@ -15900,7 +16280,7 @@ instruct replicate2I(vecD dst, iRegIorL2I src) instruct replicate4I(vecX dst, iRegIorL2I src) %{ @@ -1103,7 +1095,7 @@ index 617b2b8fb..eab0101b0 100644 match(Set dst (ReplicateI src)); ins_cost(INSN_COST); format %{ "dup $dst, $src\t# vector (4I)" %} -@@ -15656,7 +16036,7 @@ instruct replicate2I_imm(vecD dst, immI con) +@@ -15924,7 +16304,7 @@ instruct replicate2I_imm(vecD dst, immI con) instruct replicate4I_imm(vecX dst, immI con) %{ @@ -1112,7 +1104,7 @@ index 617b2b8fb..eab0101b0 100644 match(Set dst (ReplicateI con)); ins_cost(INSN_COST); format %{ "movi $dst, $con\t# vector(4I)" %} -@@ -15668,7 +16048,7 @@ instruct replicate4I_imm(vecX dst, immI con) +@@ -15936,7 +16316,7 @@ instruct replicate4I_imm(vecX dst, immI con) instruct replicate2L(vecX dst, iRegL src) %{ @@ -1121,7 +1113,7 @@ index 617b2b8fb..eab0101b0 100644 match(Set dst (ReplicateL src)); ins_cost(INSN_COST); format %{ "dup $dst, $src\t# vector (2L)" %} -@@ -15680,7 +16060,7 @@ instruct replicate2L(vecX dst, iRegL src) +@@ -15948,7 +16328,7 @@ instruct replicate2L(vecX dst, iRegL src) instruct replicate2L_zero(vecX dst, immI0 zero) %{ @@ -1130,7 +1122,7 @@ index 617b2b8fb..eab0101b0 100644 match(Set dst (ReplicateI zero)); ins_cost(INSN_COST); format %{ "movi $dst, $zero\t# vector(4I)" %} -@@ -15707,7 +16087,7 @@ instruct replicate2F(vecD dst, vRegF src) +@@ -15975,7 +16355,7 @@ instruct replicate2F(vecD dst, vRegF src) instruct replicate4F(vecX dst, vRegF src) %{ @@ -1139,7 +1131,7 @@ index 617b2b8fb..eab0101b0 100644 match(Set dst (ReplicateF src)); ins_cost(INSN_COST); format %{ "dup $dst, $src\t# vector (4F)" %} -@@ -15720,7 +16100,7 @@ instruct replicate4F(vecX dst, vRegF src) +@@ -15988,7 +16368,7 @@ instruct replicate4F(vecX dst, vRegF src) instruct replicate2D(vecX dst, vRegD src) %{ @@ -1148,50 +1140,6 @@ index 617b2b8fb..eab0101b0 100644 match(Set dst (ReplicateD src)); ins_cost(INSN_COST); format %{ "dup $dst, $src\t# vector (2D)" %} -@@ -17496,6 +17876,43 @@ instruct vsrl2L_imm(vecX dst, vecX src, immI shift) %{ - ins_pipe(vshift128_imm); - %} - -+instruct vpopcount4I(vecX dst, vecX src) %{ -+ predicate(UsePopCountInstruction && n->as_Vector()->length() == 4); -+ match(Set dst (PopCountVI src)); -+ format %{ -+ "cnt $dst, $src\t# vector (16B)\n\t" -+ "uaddlp $dst, $dst\t# vector (16B)\n\t" -+ "uaddlp $dst, $dst\t# vector (8H)" -+ %} -+ ins_encode %{ -+ __ cnt(as_FloatRegister($dst$$reg), __ T16B, -+ as_FloatRegister($src$$reg)); -+ __ uaddlp(as_FloatRegister($dst$$reg), __ T16B, -+ as_FloatRegister($dst$$reg)); -+ __ uaddlp(as_FloatRegister($dst$$reg), __ T8H, -+ as_FloatRegister($dst$$reg)); -+ %} -+ ins_pipe(pipe_class_default); -+%} -+ -+instruct vpopcount2I(vecD dst, vecD src) %{ -+ predicate(UsePopCountInstruction && n->as_Vector()->length() == 2); -+ match(Set dst (PopCountVI src)); -+ format %{ -+ "cnt $dst, $src\t# vector (8B)\n\t" -+ "uaddlp $dst, $dst\t# vector (8B)\n\t" -+ "uaddlp $dst, $dst\t# vector (4H)" -+ %} -+ ins_encode %{ -+ __ cnt(as_FloatRegister($dst$$reg), __ T8B, -+ as_FloatRegister($src$$reg)); -+ __ uaddlp(as_FloatRegister($dst$$reg), __ T8B, -+ as_FloatRegister($dst$$reg)); -+ __ uaddlp(as_FloatRegister($dst$$reg), __ T4H, -+ as_FloatRegister($dst$$reg)); -+ %} -+ ins_pipe(pipe_class_default); -+%} - - //----------PEEPHOLE RULES----------------------------------------------------- - // These must follow all instruction definitions as they use the names diff --git a/src/hotspot/cpu/aarch64/aarch64_sve.ad b/src/hotspot/cpu/aarch64/aarch64_sve.ad new file mode 100644 index 000000000..8d80cb37a @@ -3298,105 +3246,105 @@ index 000000000..0323f2f8c +BINARY_OP_UNPREDICATED(vsubF, SubVF, S, 4, sve_fsub) +BINARY_OP_UNPREDICATED(vsubD, SubVD, D, 2, sve_fsub) diff --git a/src/hotspot/cpu/aarch64/assembler_aarch64.cpp b/src/hotspot/cpu/aarch64/assembler_aarch64.cpp -index 586743eb9..441ea4066 100644 +index 2a17d8e0f..943d2a615 100644 --- a/src/hotspot/cpu/aarch64/assembler_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/assembler_aarch64.cpp -@@ -98,531 +98,617 @@ void entry(CodeBuffer *cb) { +@@ -96,662 +96,662 @@ void entry(CodeBuffer *cb) { __ bind(back); // ArithOp -- __ add(r19, r22, r7, Assembler::LSL, 28); // add x19, x22, x7, LSL #28 -- __ sub(r16, r11, r10, Assembler::LSR, 13); // sub x16, x11, x10, LSR #13 -- __ adds(r27, r13, r28, Assembler::ASR, 2); // adds x27, x13, x28, ASR #2 -- __ subs(r20, r28, r26, Assembler::ASR, 41); // subs x20, x28, x26, ASR #41 -- __ addw(r8, r19, r19, Assembler::ASR, 19); // add w8, w19, w19, ASR #19 -- __ subw(r4, r9, r10, Assembler::LSL, 14); // sub w4, w9, w10, LSL #14 -- __ addsw(r8, r11, r30, Assembler::LSL, 13); // adds w8, w11, w30, LSL #13 -- __ subsw(r0, r25, r19, Assembler::LSL, 9); // subs w0, w25, w19, LSL #9 -- __ andr(r20, r0, r21, Assembler::LSL, 19); // and x20, x0, x21, LSL #19 -- __ orr(r21, r14, r20, Assembler::LSL, 17); // orr x21, x14, x20, LSL #17 -- __ eor(r25, r28, r1, Assembler::LSL, 51); // eor x25, x28, x1, LSL #51 -- __ ands(r10, r27, r11, Assembler::ASR, 15); // ands x10, x27, x11, ASR #15 -- __ andw(r25, r5, r12, Assembler::ASR, 23); // and w25, w5, w12, ASR #23 -- __ orrw(r18, r14, r10, Assembler::LSR, 4); // orr w18, w14, w10, LSR #4 -- __ eorw(r4, r21, r5, Assembler::ASR, 22); // eor w4, w21, w5, ASR #22 -- __ andsw(r21, r0, r5, Assembler::ASR, 29); // ands w21, w0, w5, ASR #29 -- __ bic(r26, r30, r6, Assembler::ASR, 37); // bic x26, x30, x6, ASR #37 -- __ orn(r3, r1, r13, Assembler::LSR, 29); // orn x3, x1, x13, LSR #29 -- __ eon(r0, r28, r9, Assembler::LSL, 47); // eon x0, x28, x9, LSL #47 -- __ bics(r29, r5, r28, Assembler::LSL, 46); // bics x29, x5, x28, LSL #46 -- __ bicw(r9, r18, r7, Assembler::LSR, 20); // bic w9, w18, w7, LSR #20 -- __ ornw(r26, r13, r25, Assembler::ASR, 24); // orn w26, w13, w25, ASR #24 -- __ eonw(r25, r4, r19, Assembler::LSL, 6); // eon w25, w4, w19, LSL #6 -- __ bicsw(r5, r26, r4, Assembler::LSR, 24); // bics w5, w26, w4, LSR #24 -+ __ add(r26, r23, r13, Assembler::LSL, 32); // add x26, x23, x13, LSL #32 -+ __ sub(r12, r24, r9, Assembler::LSR, 37); // sub x12, x24, x9, LSR #37 -+ __ adds(r28, r15, r8, Assembler::ASR, 39); // adds x28, x15, x8, ASR #39 -+ __ subs(r7, r28, r30, Assembler::ASR, 57); // subs x7, x28, x30, ASR #57 -+ __ addw(r9, r22, r27, Assembler::ASR, 15); // add w9, w22, w27, ASR #15 -+ __ subw(r3, r13, r18, Assembler::ASR, 30); // sub w3, w13, w18, ASR #30 -+ __ addsw(r14, r26, r8, Assembler::ASR, 17); // adds w14, w26, w8, ASR #17 -+ __ subsw(r0, r22, r12, Assembler::ASR, 21); // subs w0, w22, w12, ASR #21 -+ __ andr(r0, r15, r26, Assembler::LSL, 20); // and x0, x15, x26, LSL #20 -+ __ orr(r26, r5, r17, Assembler::LSL, 61); // orr x26, x5, x17, LSL #61 -+ __ eor(r24, r13, r2, Assembler::LSL, 32); // eor x24, x13, x2, LSL #32 -+ __ ands(r28, r3, r17, Assembler::ASR, 35); // ands x28, x3, x17, ASR #35 -+ __ andw(r25, r16, r29, Assembler::LSR, 18); // and w25, w16, w29, LSR #18 -+ __ orrw(r13, r18, r11, Assembler::LSR, 9); // orr w13, w18, w11, LSR #9 -+ __ eorw(r5, r5, r18, Assembler::LSR, 15); // eor w5, w5, w18, LSR #15 -+ __ andsw(r2, r23, r27, Assembler::ASR, 26); // ands w2, w23, w27, ASR #26 -+ __ bic(r27, r28, r16, Assembler::LSR, 45); // bic x27, x28, x16, LSR #45 -+ __ orn(r8, r25, r26, Assembler::ASR, 37); // orn x8, x25, x26, ASR #37 -+ __ eon(r29, r17, r13, Assembler::LSR, 63); // eon x29, x17, x13, LSR #63 -+ __ bics(r28, r24, r2, Assembler::LSR, 31); // bics x28, x24, x2, LSR #31 -+ __ bicw(r19, r26, r7, Assembler::ASR, 3); // bic w19, w26, w7, ASR #3 -+ __ ornw(r6, r24, r10, Assembler::ASR, 3); // orn w6, w24, w10, ASR #3 -+ __ eonw(r4, r21, r1, Assembler::LSR, 29); // eon w4, w21, w1, LSR #29 -+ __ bicsw(r16, r21, r0, Assembler::LSR, 19); // bics w16, w21, w0, LSR #19 +- __ add(r15, r12, r16, Assembler::LSR, 30); // add x15, x12, x16, LSR #30 +- __ sub(r1, r15, r3, Assembler::LSR, 32); // sub x1, x15, x3, LSR #32 +- __ adds(r13, r25, r5, Assembler::LSL, 13); // adds x13, x25, x5, LSL #13 +- __ subs(r22, r28, r6, Assembler::ASR, 17); // subs x22, x28, x6, ASR #17 +- __ addw(r0, r9, r22, Assembler::ASR, 6); // add w0, w9, w22, ASR #6 +- __ subw(r19, r3, r25, Assembler::LSL, 21); // sub w19, w3, w25, LSL #21 +- __ addsw(r4, r19, r11, Assembler::LSL, 20); // adds w4, w19, w11, LSL #20 +- __ subsw(r24, r7, r19, Assembler::ASR, 0); // subs w24, w7, w19, ASR #0 +- __ andr(r30, r7, r11, Assembler::LSL, 48); // and x30, x7, x11, LSL #48 +- __ orr(r24, r8, r15, Assembler::LSL, 12); // orr x24, x8, x15, LSL #12 +- __ eor(r17, r9, r23, Assembler::LSL, 1); // eor x17, x9, x23, LSL #1 +- __ ands(r14, r11, r4, Assembler::LSR, 55); // ands x14, x11, x4, LSR #55 +- __ andw(r19, r7, r12, Assembler::LSR, 17); // and w19, w7, w12, LSR #17 +- __ orrw(r19, r27, r11, Assembler::ASR, 28); // orr w19, w27, w11, ASR #28 +- __ eorw(r30, r3, r22, Assembler::LSR, 31); // eor w30, w3, w22, LSR #31 +- __ andsw(r19, r26, r28, Assembler::ASR, 0); // ands w19, w26, w28, ASR #0 +- __ bic(r29, r6, r26, Assembler::LSL, 51); // bic x29, x6, x26, LSL #51 +- __ orn(r26, r27, r17, Assembler::LSL, 35); // orn x26, x27, x17, LSL #35 +- __ eon(r21, r4, r14, Assembler::LSL, 5); // eon x21, x4, x14, LSL #5 +- __ bics(r2, r15, r0, Assembler::ASR, 5); // bics x2, x15, x0, ASR #5 +- __ bicw(r2, r7, r2, Assembler::LSL, 29); // bic w2, w7, w2, LSL #29 +- __ ornw(r24, r12, r21, Assembler::LSR, 5); // orn w24, w12, w21, LSR #5 +- __ eonw(r30, r15, r19, Assembler::LSL, 2); // eon w30, w15, w19, LSL #2 +- __ bicsw(r30, r23, r17, Assembler::ASR, 28); // bics w30, w23, w17, ASR #28 ++ __ add(r23, r1, r13, Assembler::LSR, 45); // add x23, x1, x13, LSR #45 ++ __ sub(r8, r30, r12, Assembler::ASR, 56); // sub x8, x30, x12, ASR #56 ++ __ adds(r27, r23, r14, Assembler::LSL, 54); // adds x27, x23, x14, LSL #54 ++ __ subs(r21, r15, r20, Assembler::LSR, 38); // subs x21, x15, x20, LSR #38 ++ __ addw(r25, r17, r4, Assembler::LSL, 3); // add w25, w17, w4, LSL #3 ++ __ subw(r29, r1, r9, Assembler::ASR, 20); // sub w29, w1, w9, ASR #20 ++ __ addsw(r10, r26, r9, Assembler::ASR, 9); // adds w10, w26, w9, ASR #9 ++ __ subsw(r21, r30, r7, Assembler::ASR, 3); // subs w21, w30, w7, ASR #3 ++ __ andr(r9, r8, r11, Assembler::LSR, 4); // and x9, x8, x11, LSR #4 ++ __ orr(r3, r18, r1, Assembler::ASR, 1); // orr x3, x18, x1, ASR #1 ++ __ eor(r10, r20, r2, Assembler::LSL, 27); // eor x10, x20, x2, LSL #27 ++ __ ands(r12, r9, r11, Assembler::ASR, 31); // ands x12, x9, x11, ASR #31 ++ __ andw(r20, r9, r30, Assembler::ASR, 26); // and w20, w9, w30, ASR #26 ++ __ orrw(r21, r10, r26, Assembler::ASR, 17); // orr w21, w10, w26, ASR #17 ++ __ eorw(r0, r8, r7, Assembler::ASR, 7); // eor w0, w8, w7, ASR #7 ++ __ andsw(r19, r11, r8, Assembler::LSL, 18); // ands w19, w11, w8, LSL #18 ++ __ bic(r23, r4, r3, Assembler::LSL, 53); // bic x23, x4, x3, LSL #53 ++ __ orn(r9, r6, r19, Assembler::LSL, 24); // orn x9, x6, x19, LSL #24 ++ __ eon(r12, r6, r26, Assembler::LSR, 54); // eon x12, x6, x26, LSR #54 ++ __ bics(r22, r19, r12, Assembler::LSL, 14); // bics x22, x19, x12, LSL #14 ++ __ bicw(r29, r13, r22, Assembler::LSL, 11); // bic w29, w13, w22, LSL #11 ++ __ ornw(r17, r30, r20, Assembler::ASR, 5); // orn w17, w30, w20, ASR #5 ++ __ eonw(r1, r29, r11, Assembler::LSL, 8); // eon w1, w29, w11, LSL #8 ++ __ bicsw(r4, r20, r6, Assembler::LSR, 29); // bics w4, w20, w6, LSR #29 // AddSubImmOp -- __ addw(r7, r19, 340u); // add w7, w19, #340 -- __ addsw(r8, r0, 401u); // adds w8, w0, #401 -- __ subw(r29, r20, 163u); // sub w29, w20, #163 -- __ subsw(r8, r23, 759u); // subs w8, w23, #759 -- __ add(r1, r12, 523u); // add x1, x12, #523 -- __ adds(r2, r11, 426u); // adds x2, x11, #426 -- __ sub(r14, r29, 716u); // sub x14, x29, #716 -- __ subs(r11, r5, 582u); // subs x11, x5, #582 -+ __ addw(r17, r12, 379u); // add w17, w12, #379 -+ __ addsw(r30, r1, 22u); // adds w30, w1, #22 -+ __ subw(r29, r5, 126u); // sub w29, w5, #126 -+ __ subsw(r6, r24, 960u); // subs w6, w24, #960 -+ __ add(r0, r13, 104u); // add x0, x13, #104 -+ __ adds(r8, r6, 663u); // adds x8, x6, #663 -+ __ sub(r10, r5, 516u); // sub x10, x5, #516 -+ __ subs(r1, r3, 1012u); // subs x1, x3, #1012 +- __ addw(r4, r20, 660u); // add w4, w20, #660 +- __ addsw(r2, r10, 710u); // adds w2, w10, #710 +- __ subw(r19, r26, 244u); // sub w19, w26, #244 +- __ subsw(r28, r13, 73u); // subs w28, w13, #73 +- __ add(r2, r30, 862u); // add x2, x30, #862 +- __ adds(r27, r16, 574u); // adds x27, x16, #574 +- __ sub(r22, r9, 589u); // sub x22, x9, #589 +- __ subs(r4, r1, 698u); // subs x4, x1, #698 ++ __ addw(r30, r6, 504u); // add w30, w6, #504 ++ __ addsw(r19, r8, 943u); // adds w19, w8, #943 ++ __ subw(r29, r10, 365u); // sub w29, w10, #365 ++ __ subsw(r4, r8, 284u); // subs w4, w8, #284 ++ __ add(r3, r14, 958u); // add x3, x14, #958 ++ __ adds(r22, r20, 167u); // adds x22, x20, #167 ++ __ sub(r27, r15, 725u); // sub x27, x15, #725 ++ __ subs(r24, r28, 947u); // subs x24, x28, #947 // LogicalImmOp -- __ andw(r23, r22, 32768ul); // and w23, w22, #0x8000 -- __ orrw(r4, r10, 4042322160ul); // orr w4, w10, #0xf0f0f0f0 -- __ eorw(r0, r24, 4042322160ul); // eor w0, w24, #0xf0f0f0f0 -- __ andsw(r19, r29, 2139127680ul); // ands w19, w29, #0x7f807f80 -- __ andr(r5, r10, 4503599627354112ul); // and x5, x10, #0xfffffffffc000 -- __ orr(r12, r30, 18445618178097414144ul); // orr x12, x30, #0xfffc0000fffc0000 -- __ eor(r30, r5, 262128ul); // eor x30, x5, #0x3fff0 -- __ ands(r26, r23, 4194300ul); // ands x26, x23, #0x3ffffc -+ __ andw(r6, r11, 4294049777ull); // and w6, w11, #0xfff1fff1 -+ __ orrw(r28, r5, 4294966791ull); // orr w28, w5, #0xfffffe07 -+ __ eorw(r1, r20, 134217216ull); // eor w1, w20, #0x7fffe00 -+ __ andsw(r7, r18, 1048576ull); // ands w7, w18, #0x100000 -+ __ andr(r14, r12, 9223372036854775808ull); // and x14, x12, #0x8000000000000000 -+ __ orr(r9, r11, 562675075514368ull); // orr x9, x11, #0x1ffc000000000 -+ __ eor(r17, r0, 18014398509481728ull); // eor x17, x0, #0x3fffffffffff00 -+ __ ands(r1, r8, 18446744073705357315ull); // ands x1, x8, #0xffffffffffc00003 +- __ andw(r28, r19, 4294709247ul); // and w28, w19, #0xfffc0fff +- __ orrw(r27, r5, 536870910ul); // orr w27, w5, #0x1ffffffe +- __ eorw(r30, r20, 4294840319ul); // eor w30, w20, #0xfffe0fff +- __ andsw(r22, r26, 4294959615ul); // ands w22, w26, #0xffffe1ff +- __ andr(r5, r7, 4194300ul); // and x5, x7, #0x3ffffc +- __ orr(r13, r7, 18014398509481728ul); // orr x13, x7, #0x3fffffffffff00 +- __ eor(r7, r9, 18442240474082197503ul); // eor x7, x9, #0xfff0000000003fff +- __ ands(r3, r0, 18374686479671656447ul); // ands x3, x0, #0xff00000000007fff ++ __ andw(r25, r25, 2139127680ul); // and w25, w25, #0x7f807f80 ++ __ orrw(r13, r26, 2097120ul); // orr w13, w26, #0x1fffe0 ++ __ eorw(r21, r13, 3758096384ul); // eor w21, w13, #0xe0000000 ++ __ andsw(r2, r3, 1073733632ul); // ands w2, w3, #0x3fffe000 ++ __ andr(r8, r10, 1125895612137471ul); // and x8, x10, #0x3ffff0003ffff ++ __ orr(r27, r16, 18444492273897963519ul); // orr x27, x16, #0xfff80000001fffff ++ __ eor(r27, r3, 4611685469745315712ul); // eor x27, x3, #0x3fffff803fffff80 ++ __ ands(r4, r23, 18446744056529698815ul); // ands x4, x23, #0xfffffffc00003fff // AbsOp -- __ b(__ pc()); // b . -- __ b(back); // b back -- __ b(forth); // b forth -- __ bl(__ pc()); // bl . -- __ bl(back); // bl back -- __ bl(forth); // bl forth +- __ b(__ pc()); // b . +- __ b(back); // b back +- __ b(forth); // b forth +- __ bl(__ pc()); // bl . +- __ bl(back); // bl back +- __ bl(forth); // bl forth + __ b(__ pc()); // b . + __ b(back); // b back + __ b(forth); // b forth @@ -3405,142 +3353,142 @@ index 586743eb9..441ea4066 100644 + __ bl(forth); // bl forth // RegAndAbsOp -- __ cbzw(r12, __ pc()); // cbz w12, . -- __ cbzw(r12, back); // cbz w12, back -- __ cbzw(r12, forth); // cbz w12, forth -- __ cbnzw(r20, __ pc()); // cbnz w20, . -- __ cbnzw(r20, back); // cbnz w20, back -- __ cbnzw(r20, forth); // cbnz w20, forth -- __ cbz(r12, __ pc()); // cbz x12, . -- __ cbz(r12, back); // cbz x12, back -- __ cbz(r12, forth); // cbz x12, forth -- __ cbnz(r24, __ pc()); // cbnz x24, . -- __ cbnz(r24, back); // cbnz x24, back -- __ cbnz(r24, forth); // cbnz x24, forth -- __ adr(r6, __ pc()); // adr x6, . -- __ adr(r6, back); // adr x6, back -- __ adr(r6, forth); // adr x6, forth -- __ _adrp(r21, __ pc()); // adrp x21, . -+ __ cbzw(r10, __ pc()); // cbz w10, . -+ __ cbzw(r10, back); // cbz w10, back -+ __ cbzw(r10, forth); // cbz w10, forth -+ __ cbnzw(r8, __ pc()); // cbnz w8, . -+ __ cbnzw(r8, back); // cbnz w8, back -+ __ cbnzw(r8, forth); // cbnz w8, forth -+ __ cbz(r11, __ pc()); // cbz x11, . -+ __ cbz(r11, back); // cbz x11, back -+ __ cbz(r11, forth); // cbz x11, forth -+ __ cbnz(r29, __ pc()); // cbnz x29, . -+ __ cbnz(r29, back); // cbnz x29, back -+ __ cbnz(r29, forth); // cbnz x29, forth -+ __ adr(r19, __ pc()); // adr x19, . -+ __ adr(r19, back); // adr x19, back -+ __ adr(r19, forth); // adr x19, forth -+ __ _adrp(r19, __ pc()); // adrp x19, . +- __ cbzw(r16, __ pc()); // cbz w16, . +- __ cbzw(r16, back); // cbz w16, back +- __ cbzw(r16, forth); // cbz w16, forth +- __ cbnzw(r19, __ pc()); // cbnz w19, . +- __ cbnzw(r19, back); // cbnz w19, back +- __ cbnzw(r19, forth); // cbnz w19, forth +- __ cbz(r5, __ pc()); // cbz x5, . +- __ cbz(r5, back); // cbz x5, back +- __ cbz(r5, forth); // cbz x5, forth +- __ cbnz(r4, __ pc()); // cbnz x4, . +- __ cbnz(r4, back); // cbnz x4, back +- __ cbnz(r4, forth); // cbnz x4, forth +- __ adr(r27, __ pc()); // adr x27, . +- __ adr(r27, back); // adr x27, back +- __ adr(r27, forth); // adr x27, forth +- __ _adrp(r16, __ pc()); // adrp x16, . ++ __ cbzw(r3, __ pc()); // cbz w3, . ++ __ cbzw(r3, back); // cbz w3, back ++ __ cbzw(r3, forth); // cbz w3, forth ++ __ cbnzw(r2, __ pc()); // cbnz w2, . ++ __ cbnzw(r2, back); // cbnz w2, back ++ __ cbnzw(r2, forth); // cbnz w2, forth ++ __ cbz(r25, __ pc()); // cbz x25, . ++ __ cbz(r25, back); // cbz x25, back ++ __ cbz(r25, forth); // cbz x25, forth ++ __ cbnz(r18, __ pc()); // cbnz x18, . ++ __ cbnz(r18, back); // cbnz x18, back ++ __ cbnz(r18, forth); // cbnz x18, forth ++ __ adr(r8, __ pc()); // adr x8, . ++ __ adr(r8, back); // adr x8, back ++ __ adr(r8, forth); // adr x8, forth ++ __ _adrp(r15, __ pc()); // adrp x15, . // RegImmAbsOp -- __ tbz(r1, 1, __ pc()); // tbz x1, #1, . -- __ tbz(r1, 1, back); // tbz x1, #1, back -- __ tbz(r1, 1, forth); // tbz x1, #1, forth -- __ tbnz(r8, 9, __ pc()); // tbnz x8, #9, . -- __ tbnz(r8, 9, back); // tbnz x8, #9, back -- __ tbnz(r8, 9, forth); // tbnz x8, #9, forth -+ __ tbz(r22, 6, __ pc()); // tbz x22, #6, . -+ __ tbz(r22, 6, back); // tbz x22, #6, back -+ __ tbz(r22, 6, forth); // tbz x22, #6, forth -+ __ tbnz(r12, 11, __ pc()); // tbnz x12, #11, . -+ __ tbnz(r12, 11, back); // tbnz x12, #11, back -+ __ tbnz(r12, 11, forth); // tbnz x12, #11, forth +- __ tbz(r28, 8, __ pc()); // tbz x28, #8, . +- __ tbz(r28, 8, back); // tbz x28, #8, back +- __ tbz(r28, 8, forth); // tbz x28, #8, forth +- __ tbnz(r1, 1, __ pc()); // tbnz x1, #1, . +- __ tbnz(r1, 1, back); // tbnz x1, #1, back +- __ tbnz(r1, 1, forth); // tbnz x1, #1, forth ++ __ tbz(r18, 14, __ pc()); // tbz x18, #14, . ++ __ tbz(r18, 14, back); // tbz x18, #14, back ++ __ tbz(r18, 14, forth); // tbz x18, #14, forth ++ __ tbnz(r25, 15, __ pc()); // tbnz x25, #15, . ++ __ tbnz(r25, 15, back); // tbnz x25, #15, back ++ __ tbnz(r25, 15, forth); // tbnz x25, #15, forth // MoveWideImmOp -- __ movnw(r12, 23175, 0); // movn w12, #23175, lsl 0 -- __ movzw(r11, 20476, 16); // movz w11, #20476, lsl 16 -- __ movkw(r21, 3716, 0); // movk w21, #3716, lsl 0 -- __ movn(r29, 28661, 48); // movn x29, #28661, lsl 48 -- __ movz(r3, 6927, 0); // movz x3, #6927, lsl 0 -- __ movk(r22, 9828, 16); // movk x22, #9828, lsl 16 -+ __ movnw(r0, 6301, 0); // movn w0, #6301, lsl 0 -+ __ movzw(r7, 20886, 0); // movz w7, #20886, lsl 0 -+ __ movkw(r27, 18617, 0); // movk w27, #18617, lsl 0 -+ __ movn(r12, 22998, 16); // movn x12, #22998, lsl 16 -+ __ movz(r20, 1532, 16); // movz x20, #1532, lsl 16 -+ __ movk(r8, 5167, 32); // movk x8, #5167, lsl 32 +- __ movnw(r20, 8639, 16); // movn w20, #8639, lsl 16 +- __ movzw(r7, 25835, 0); // movz w7, #25835, lsl 0 +- __ movkw(r17, 7261, 0); // movk w17, #7261, lsl 0 +- __ movn(r14, 2097, 32); // movn x14, #2097, lsl 32 +- __ movz(r9, 16082, 0); // movz x9, #16082, lsl 0 +- __ movk(r19, 13962, 16); // movk x19, #13962, lsl 16 ++ __ movnw(r18, 4126, 16); // movn w18, #4126, lsl 16 ++ __ movzw(r30, 13712, 0); // movz w30, #13712, lsl 0 ++ __ movkw(r21, 13161, 16); // movk w21, #13161, lsl 16 ++ __ movn(r18, 28524, 48); // movn x18, #28524, lsl 48 ++ __ movz(r13, 30710, 48); // movz x13, #30710, lsl 48 ++ __ movk(r3, 31565, 48); // movk x3, #31565, lsl 48 // BitfieldOp -- __ sbfm(r12, r8, 6, 22); // sbfm x12, x8, #6, #22 -- __ bfmw(r19, r25, 25, 19); // bfm w19, w25, #25, #19 -- __ ubfmw(r9, r12, 29, 15); // ubfm w9, w12, #29, #15 -- __ sbfm(r28, r25, 16, 16); // sbfm x28, x25, #16, #16 -- __ bfm(r12, r5, 4, 25); // bfm x12, x5, #4, #25 -- __ ubfm(r0, r10, 6, 8); // ubfm x0, x10, #6, #8 -+ __ sbfm(r15, r17, 24, 28); // sbfm x15, x17, #24, #28 -+ __ bfmw(r15, r9, 14, 25); // bfm w15, w9, #14, #25 -+ __ ubfmw(r27, r25, 6, 31); // ubfm w27, w25, #6, #31 -+ __ sbfm(r19, r2, 23, 31); // sbfm x19, x2, #23, #31 -+ __ bfm(r12, r21, 10, 6); // bfm x12, x21, #10, #6 -+ __ ubfm(r22, r0, 26, 16); // ubfm x22, x0, #26, #16 +- __ sbfm(r9, r22, 6, 22); // sbfm x9, x22, #6, #22 +- __ bfmw(r19, r0, 11, 0); // bfm w19, w0, #11, #0 +- __ ubfmw(r10, r19, 11, 19); // ubfm w10, w19, #11, #19 +- __ sbfm(r4, r15, 5, 17); // sbfm x4, x15, #5, #17 +- __ bfm(r3, r5, 19, 28); // bfm x3, x5, #19, #28 +- __ ubfm(r12, r28, 17, 2); // ubfm x12, x28, #17, #2 ++ __ sbfm(r10, r1, 0, 3); // sbfm x10, x1, #0, #3 ++ __ bfmw(r12, r22, 5, 24); // bfm w12, w22, #5, #24 ++ __ ubfmw(r17, r3, 11, 8); // ubfm w17, w3, #11, #8 ++ __ sbfm(r0, r3, 11, 14); // sbfm x0, x3, #11, #14 ++ __ bfm(r28, r6, 7, 15); // bfm x28, x6, #7, #15 ++ __ ubfm(r9, r10, 1, 25); // ubfm x9, x10, #1, #25 // ExtractOp -- __ extrw(r4, r13, r26, 24); // extr w4, w13, w26, #24 -- __ extr(r23, r30, r24, 31); // extr x23, x30, x24, #31 -+ __ extrw(r3, r3, r20, 27); // extr w3, w3, w20, #27 -+ __ extr(r8, r30, r3, 54); // extr x8, x30, x3, #54 +- __ extrw(r15, r0, r22, 3); // extr w15, w0, w22, #3 +- __ extr(r6, r14, r14, 55); // extr x6, x14, x14, #55 ++ __ extrw(r21, r27, r25, 23); // extr w21, w27, w25, #23 ++ __ extr(r14, r17, r22, 17); // extr x14, x17, x22, #17 // CondBranchOp -- __ br(Assembler::EQ, __ pc()); // b.EQ . -- __ br(Assembler::EQ, back); // b.EQ back -- __ br(Assembler::EQ, forth); // b.EQ forth -- __ br(Assembler::NE, __ pc()); // b.NE . -- __ br(Assembler::NE, back); // b.NE back -- __ br(Assembler::NE, forth); // b.NE forth -- __ br(Assembler::HS, __ pc()); // b.HS . -- __ br(Assembler::HS, back); // b.HS back -- __ br(Assembler::HS, forth); // b.HS forth -- __ br(Assembler::CS, __ pc()); // b.CS . -- __ br(Assembler::CS, back); // b.CS back -- __ br(Assembler::CS, forth); // b.CS forth -- __ br(Assembler::LO, __ pc()); // b.LO . -- __ br(Assembler::LO, back); // b.LO back -- __ br(Assembler::LO, forth); // b.LO forth -- __ br(Assembler::CC, __ pc()); // b.CC . -- __ br(Assembler::CC, back); // b.CC back -- __ br(Assembler::CC, forth); // b.CC forth -- __ br(Assembler::MI, __ pc()); // b.MI . -- __ br(Assembler::MI, back); // b.MI back -- __ br(Assembler::MI, forth); // b.MI forth -- __ br(Assembler::PL, __ pc()); // b.PL . -- __ br(Assembler::PL, back); // b.PL back -- __ br(Assembler::PL, forth); // b.PL forth -- __ br(Assembler::VS, __ pc()); // b.VS . -- __ br(Assembler::VS, back); // b.VS back -- __ br(Assembler::VS, forth); // b.VS forth -- __ br(Assembler::VC, __ pc()); // b.VC . -- __ br(Assembler::VC, back); // b.VC back -- __ br(Assembler::VC, forth); // b.VC forth -- __ br(Assembler::HI, __ pc()); // b.HI . -- __ br(Assembler::HI, back); // b.HI back -- __ br(Assembler::HI, forth); // b.HI forth -- __ br(Assembler::LS, __ pc()); // b.LS . -- __ br(Assembler::LS, back); // b.LS back -- __ br(Assembler::LS, forth); // b.LS forth -- __ br(Assembler::GE, __ pc()); // b.GE . -- __ br(Assembler::GE, back); // b.GE back -- __ br(Assembler::GE, forth); // b.GE forth -- __ br(Assembler::LT, __ pc()); // b.LT . -- __ br(Assembler::LT, back); // b.LT back -- __ br(Assembler::LT, forth); // b.LT forth -- __ br(Assembler::GT, __ pc()); // b.GT . -- __ br(Assembler::GT, back); // b.GT back -- __ br(Assembler::GT, forth); // b.GT forth -- __ br(Assembler::LE, __ pc()); // b.LE . -- __ br(Assembler::LE, back); // b.LE back -- __ br(Assembler::LE, forth); // b.LE forth -- __ br(Assembler::AL, __ pc()); // b.AL . -- __ br(Assembler::AL, back); // b.AL back -- __ br(Assembler::AL, forth); // b.AL forth -- __ br(Assembler::NV, __ pc()); // b.NV . -- __ br(Assembler::NV, back); // b.NV back -- __ br(Assembler::NV, forth); // b.NV forth +- __ br(Assembler::EQ, __ pc()); // b.EQ . +- __ br(Assembler::EQ, back); // b.EQ back +- __ br(Assembler::EQ, forth); // b.EQ forth +- __ br(Assembler::NE, __ pc()); // b.NE . +- __ br(Assembler::NE, back); // b.NE back +- __ br(Assembler::NE, forth); // b.NE forth +- __ br(Assembler::HS, __ pc()); // b.HS . +- __ br(Assembler::HS, back); // b.HS back +- __ br(Assembler::HS, forth); // b.HS forth +- __ br(Assembler::CS, __ pc()); // b.CS . +- __ br(Assembler::CS, back); // b.CS back +- __ br(Assembler::CS, forth); // b.CS forth +- __ br(Assembler::LO, __ pc()); // b.LO . +- __ br(Assembler::LO, back); // b.LO back +- __ br(Assembler::LO, forth); // b.LO forth +- __ br(Assembler::CC, __ pc()); // b.CC . +- __ br(Assembler::CC, back); // b.CC back +- __ br(Assembler::CC, forth); // b.CC forth +- __ br(Assembler::MI, __ pc()); // b.MI . +- __ br(Assembler::MI, back); // b.MI back +- __ br(Assembler::MI, forth); // b.MI forth +- __ br(Assembler::PL, __ pc()); // b.PL . +- __ br(Assembler::PL, back); // b.PL back +- __ br(Assembler::PL, forth); // b.PL forth +- __ br(Assembler::VS, __ pc()); // b.VS . +- __ br(Assembler::VS, back); // b.VS back +- __ br(Assembler::VS, forth); // b.VS forth +- __ br(Assembler::VC, __ pc()); // b.VC . +- __ br(Assembler::VC, back); // b.VC back +- __ br(Assembler::VC, forth); // b.VC forth +- __ br(Assembler::HI, __ pc()); // b.HI . +- __ br(Assembler::HI, back); // b.HI back +- __ br(Assembler::HI, forth); // b.HI forth +- __ br(Assembler::LS, __ pc()); // b.LS . +- __ br(Assembler::LS, back); // b.LS back +- __ br(Assembler::LS, forth); // b.LS forth +- __ br(Assembler::GE, __ pc()); // b.GE . +- __ br(Assembler::GE, back); // b.GE back +- __ br(Assembler::GE, forth); // b.GE forth +- __ br(Assembler::LT, __ pc()); // b.LT . +- __ br(Assembler::LT, back); // b.LT back +- __ br(Assembler::LT, forth); // b.LT forth +- __ br(Assembler::GT, __ pc()); // b.GT . +- __ br(Assembler::GT, back); // b.GT back +- __ br(Assembler::GT, forth); // b.GT forth +- __ br(Assembler::LE, __ pc()); // b.LE . +- __ br(Assembler::LE, back); // b.LE back +- __ br(Assembler::LE, forth); // b.LE forth +- __ br(Assembler::AL, __ pc()); // b.AL . +- __ br(Assembler::AL, back); // b.AL back +- __ br(Assembler::AL, forth); // b.AL forth +- __ br(Assembler::NV, __ pc()); // b.NV . +- __ br(Assembler::NV, back); // b.NV back +- __ br(Assembler::NV, forth); // b.NV forth + __ br(Assembler::EQ, __ pc()); // b.EQ . + __ br(Assembler::EQ, back); // b.EQ back + __ br(Assembler::EQ, forth); // b.EQ forth @@ -3597,678 +3545,725 @@ index 586743eb9..441ea4066 100644 + __ br(Assembler::NV, forth); // b.NV forth // ImmOp -- __ svc(12729); // svc #12729 -- __ hvc(6788); // hvc #6788 -- __ smc(1535); // smc #1535 -- __ brk(16766); // brk #16766 -- __ hlt(9753); // hlt #9753 -+ __ svc(12999); // svc #12999 -+ __ hvc(2665); // hvc #2665 -+ __ smc(9002); // smc #9002 -+ __ brk(14843); // brk #14843 -+ __ hlt(25964); // hlt #25964 +- __ svc(22064); // svc #22064 +- __ hvc(533); // hvc #533 +- __ smc(9942); // smc #9942 +- __ brk(4714); // brk #4714 +- __ hlt(4302); // hlt #4302 ++ __ svc(31973); // svc #31973 ++ __ hvc(1113); // hvc #1113 ++ __ smc(24334); // smc #24334 ++ __ brk(7815); // brk #7815 ++ __ hlt(28529); // hlt #28529 // Op -- __ nop(); // nop -- __ eret(); // eret -- __ drps(); // drps -- __ isb(); // isb +- __ nop(); // nop +- __ eret(); // eret +- __ drps(); // drps +- __ isb(); // isb + __ nop(); // nop + __ eret(); // eret + __ drps(); // drps + __ isb(); // isb // SystemOp -- __ dsb(Assembler::SY); // dsb SY -- __ dmb(Assembler::ISHST); // dmb ISHST -+ __ dsb(Assembler::ST); // dsb ST -+ __ dmb(Assembler::OSHST); // dmb OSHST +- __ dsb(Assembler::OSH); // dsb OSH +- __ dmb(Assembler::NSHLD); // dmb NSHLD ++ __ dsb(Assembler::NSHLD); // dsb NSHLD ++ __ dmb(Assembler::NSH); // dmb NSH // OneRegOp -- __ br(r2); // br x2 -- __ blr(r5); // blr x5 -+ __ br(r16); // br x16 -+ __ blr(r20); // blr x20 +- __ br(r20); // br x20 +- __ blr(r2); // blr x2 ++ __ br(r28); // br x28 ++ __ blr(r17); // blr x17 // LoadStoreExclusiveOp -- __ stxr(r20, r21, r2); // stxr w20, x21, [x2] -- __ stlxr(r5, r29, r7); // stlxr w5, x29, [x7] -- __ ldxr(r5, r16); // ldxr x5, [x16] -- __ ldaxr(r27, r29); // ldaxr x27, [x29] -- __ stlr(r0, r29); // stlr x0, [x29] -- __ ldar(r21, r28); // ldar x21, [x28] -+ __ stxr(r10, r27, r8); // stxr w10, x27, [x8] -+ __ stlxr(r0, r1, r21); // stlxr w0, x1, [x21] -+ __ ldxr(r17, r29); // ldxr x17, [x29] -+ __ ldaxr(r29, r28); // ldaxr x29, [x28] -+ __ stlr(r1, r23); // stlr x1, [x23] -+ __ ldar(r21, r20); // ldar x21, [x20] +- __ stxr(r18, r23, r0); // stxr w18, x23, [x0] +- __ stlxr(r30, r5, r22); // stlxr w30, x5, [x22] +- __ ldxr(r5, r8); // ldxr x5, [x8] +- __ ldaxr(r20, r16); // ldaxr x20, [x16] +- __ stlr(r6, r11); // stlr x6, [x11] +- __ ldar(r6, r27); // ldar x6, [x27] ++ __ stxr(r18, r7, r26); // stxr w18, x7, [x26] ++ __ stlxr(r25, r12, r6); // stlxr w25, x12, [x6] ++ __ ldxr(r0, r16); // ldxr x0, [x16] ++ __ ldaxr(r6, r3); // ldaxr x6, [x3] ++ __ stlr(r14, r1); // stlr x14, [x1] ++ __ ldar(r29, r24); // ldar x29, [x24] // LoadStoreExclusiveOp -- __ stxrw(r21, r24, r7); // stxr w21, w24, [x7] -- __ stlxrw(r21, r26, r28); // stlxr w21, w26, [x28] -- __ ldxrw(r21, r6); // ldxr w21, [x6] -- __ ldaxrw(r15, r30); // ldaxr w15, [x30] -- __ stlrw(r19, r3); // stlr w19, [x3] -- __ ldarw(r22, r2); // ldar w22, [x2] -+ __ stxrw(r22, r27, r19); // stxr w22, w27, [x19] -+ __ stlxrw(r11, r16, r6); // stlxr w11, w16, [x6] -+ __ ldxrw(r18, r0); // ldxr w18, [x0] -+ __ ldaxrw(r4, r10); // ldaxr w4, [x10] -+ __ stlrw(r24, r22); // stlr w24, [x22] -+ __ ldarw(r10, r19); // ldar w10, [x19] +- __ stxrw(r10, r17, r5); // stxr w10, w17, [x5] +- __ stlxrw(r22, r9, r12); // stlxr w22, w9, [x12] +- __ ldxrw(r27, r8); // ldxr w27, [x8] +- __ ldaxrw(r23, r2); // ldaxr w23, [x2] +- __ stlrw(r26, r29); // stlr w26, [x29] +- __ ldarw(r13, r10); // ldar w13, [x10] ++ __ stxrw(r28, r15, r23); // stxr w28, w15, [x23] ++ __ stlxrw(r9, r7, r3); // stlxr w9, w7, [x3] ++ __ ldxrw(r1, r20); // ldxr w1, [x20] ++ __ ldaxrw(r20, r15); // ldaxr w20, [x15] ++ __ stlrw(r21, r9); // stlr w21, [x9] ++ __ ldarw(r5, r17); // ldar w5, [x17] // LoadStoreExclusiveOp -- __ stxrh(r18, r15, r0); // stxrh w18, w15, [x0] -- __ stlxrh(r11, r5, r28); // stlxrh w11, w5, [x28] -- __ ldxrh(r29, r6); // ldxrh w29, [x6] -- __ ldaxrh(r18, r7); // ldaxrh w18, [x7] -- __ stlrh(r25, r28); // stlrh w25, [x28] -- __ ldarh(r2, r19); // ldarh w2, [x19] -+ __ stxrh(r1, r5, r30); // stxrh w1, w5, [x30] -+ __ stlxrh(r8, r12, r17); // stlxrh w8, w12, [x17] -+ __ ldxrh(r9, r14); // ldxrh w9, [x14] -+ __ ldaxrh(r7, r1); // ldaxrh w7, [x1] -+ __ stlrh(r5, r16); // stlrh w5, [x16] -+ __ ldarh(r2, r12); // ldarh w2, [x12] +- __ stxrh(r25, r28, r27); // stxrh w25, w28, [x27] +- __ stlxrh(r29, r22, r12); // stlxrh w29, w22, [x12] +- __ ldxrh(r22, r28); // ldxrh w22, [x28] +- __ ldaxrh(r3, r30); // ldaxrh w3, [x30] +- __ stlrh(r24, r15); // stlrh w24, [x15] +- __ ldarh(r27, r26); // ldarh w27, [x26] ++ __ stxrh(r13, r20, r30); // stxrh w13, w20, [x30] ++ __ stlxrh(r10, r12, r18); // stlxrh w10, w12, [x18] ++ __ ldxrh(r4, r19); // ldxrh w4, [x19] ++ __ ldaxrh(r22, r10); // ldaxrh w22, [x10] ++ __ stlrh(r30, r15); // stlrh w30, [x15] ++ __ ldarh(r4, r24); // ldarh w4, [x24] // LoadStoreExclusiveOp -- __ stxrb(r10, r30, r1); // stxrb w10, w30, [x1] -- __ stlxrb(r20, r21, r22); // stlxrb w20, w21, [x22] -- __ ldxrb(r25, r2); // ldxrb w25, [x2] -- __ ldaxrb(r24, r5); // ldaxrb w24, [x5] -- __ stlrb(r16, r3); // stlrb w16, [x3] -- __ ldarb(r22, r29); // ldarb w22, [x29] -+ __ stxrb(r10, r12, r3); // stxrb w10, w12, [x3] -+ __ stlxrb(r28, r14, r26); // stlxrb w28, w14, [x26] -+ __ ldxrb(r30, r10); // ldxrb w30, [x10] -+ __ ldaxrb(r14, r21); // ldaxrb w14, [x21] -+ __ stlrb(r13, r9); // stlrb w13, [x9] -+ __ ldarb(r22, r27); // ldarb w22, [x27] +- __ stxrb(r11, r10, r19); // stxrb w11, w10, [x19] +- __ stlxrb(r23, r27, r22); // stlxrb w23, w27, [x22] +- __ ldxrb(r24, r16); // ldxrb w24, [x16] +- __ ldaxrb(r24, r1); // ldaxrb w24, [x1] +- __ stlrb(r5, r29); // stlrb w5, [x29] +- __ ldarb(r24, r16); // ldarb w24, [x16] ++ __ stxrb(r10, r20, r12); // stxrb w10, w20, [x12] ++ __ stlxrb(r20, r29, r11); // stlxrb w20, w29, [x11] ++ __ ldxrb(r21, r5); // ldxrb w21, [x5] ++ __ ldaxrb(r4, r9); // ldaxrb w4, [x9] ++ __ stlrb(r30, r28); // stlrb w30, [x28] ++ __ ldarb(r19, r24); // ldarb w19, [x24] // LoadStoreExclusiveOp -- __ ldxp(r8, r2, r19); // ldxp x8, x2, [x19] -- __ ldaxp(r7, r19, r14); // ldaxp x7, x19, [x14] -- __ stxp(r8, r27, r28, r5); // stxp w8, x27, x28, [x5] -- __ stlxp(r5, r8, r14, r6); // stlxp w5, x8, x14, [x6] -+ __ ldxp(r28, r19, r11); // ldxp x28, x19, [x11] -+ __ ldaxp(r30, r19, r2); // ldaxp x30, x19, [x2] -+ __ stxp(r2, r23, r1, r0); // stxp w2, x23, x1, [x0] -+ __ stlxp(r12, r16, r13, r15); // stlxp w12, x16, x13, [x15] +- __ ldxp(r25, r24, r17); // ldxp x25, x24, [x17] +- __ ldaxp(r22, r12, r19); // ldaxp x22, x12, [x19] +- __ stxp(r0, r26, r21, r25); // stxp w0, x26, x21, [x25] +- __ stlxp(r1, r6, r11, r5); // stlxp w1, x6, x11, [x5] ++ __ ldxp(r11, r16, r18); // ldxp x11, x16, [x18] ++ __ ldaxp(r8, r7, r15); // ldaxp x8, x7, [x15] ++ __ stxp(r28, r20, r16, r10); // stxp w28, x20, x16, [x10] ++ __ stlxp(r7, r9, r21, r3); // stlxp w7, x9, x21, [x3] // LoadStoreExclusiveOp -- __ ldxpw(r25, r4, r22); // ldxp w25, w4, [x22] -- __ ldaxpw(r13, r14, r15); // ldaxp w13, w14, [x15] -- __ stxpw(r20, r26, r8, r10); // stxp w20, w26, w8, [x10] -- __ stlxpw(r23, r18, r18, r18); // stlxp w23, w18, w18, [x18] -+ __ ldxpw(r18, r21, r13); // ldxp w18, w21, [x13] -+ __ ldaxpw(r11, r30, r8); // ldaxp w11, w30, [x8] -+ __ stxpw(r24, r13, r11, r1); // stxp w24, w13, w11, [x1] -+ __ stlxpw(r26, r21, r27, r13); // stlxp w26, w21, w27, [x13] +- __ ldxpw(r13, r14, r4); // ldxp w13, w14, [x4] +- __ ldaxpw(r17, r2, r6); // ldaxp w17, w2, [x6] +- __ stxpw(r15, r3, r9, r18); // stxp w15, w3, w9, [x18] +- __ stlxpw(r18, r17, r4, r9); // stlxp w18, w17, w4, [x9] ++ __ ldxpw(r25, r6, r19); // ldxp w25, w6, [x19] ++ __ ldaxpw(r30, r9, r2); // ldaxp w30, w9, [x2] ++ __ stxpw(r16, r0, r20, r12); // stxp w16, w0, w20, [x12] ++ __ stlxpw(r5, r2, r7, r28); // stlxp w5, w2, w7, [x28] -// base_plus_unscaled_offset +// base_plus_unscaled_offset // LoadStoreOp -- __ str(r30, Address(r11, 99)); // str x30, [x11, 99] -- __ strw(r23, Address(r25, -77)); // str w23, [x25, -77] -- __ strb(r2, Address(r14, 3)); // strb w2, [x14, 3] -- __ strh(r9, Address(r10, 5)); // strh w9, [x10, 5] -- __ ldr(r20, Address(r15, 57)); // ldr x20, [x15, 57] -- __ ldrw(r12, Address(r16, -78)); // ldr w12, [x16, -78] -- __ ldrb(r22, Address(r26, -3)); // ldrb w22, [x26, -3] -- __ ldrh(r30, Address(r19, -47)); // ldrh w30, [x19, -47] -- __ ldrsb(r9, Address(r10, -12)); // ldrsb x9, [x10, -12] -- __ ldrsh(r28, Address(r17, 14)); // ldrsh x28, [x17, 14] -- __ ldrshw(r3, Address(r5, 10)); // ldrsh w3, [x5, 10] -- __ ldrsw(r17, Address(r17, -91)); // ldrsw x17, [x17, -91] -- __ ldrd(v2, Address(r20, -17)); // ldr d2, [x20, -17] -- __ ldrs(v22, Address(r7, -10)); // ldr s22, [x7, -10] -- __ strd(v30, Address(r18, -223)); // str d30, [x18, -223] -- __ strs(v13, Address(r22, 21)); // str s13, [x22, 21] +- __ str(r23, Address(r21, -49)); // str x23, [x21, -49] +- __ strw(r21, Address(r2, 63)); // str w21, [x2, 63] +- __ strb(r27, Address(r28, 11)); // strb w27, [x28, 11] +- __ strh(r29, Address(r15, -13)); // strh w29, [x15, -13] +- __ ldr(r14, Address(r30, -45)); // ldr x14, [x30, -45] +- __ ldrw(r29, Address(r28, 53)); // ldr w29, [x28, 53] +- __ ldrb(r20, Address(r26, 7)); // ldrb w20, [x26, 7] +- __ ldrh(r25, Address(r2, -50)); // ldrh w25, [x2, -50] +- __ ldrsb(r3, Address(r10, -15)); // ldrsb x3, [x10, -15] +- __ ldrsh(r14, Address(r15, 19)); // ldrsh x14, [x15, 19] +- __ ldrshw(r29, Address(r11, -5)); // ldrsh w29, [x11, -5] +- __ ldrsw(r15, Address(r5, -71)); // ldrsw x15, [x5, -71] +- __ ldrd(v19, Address(r12, 3)); // ldr d19, [x12, 3] +- __ ldrs(v12, Address(r27, 42)); // ldr s12, [x27, 42] +- __ strd(v22, Address(r28, 125)); // str d22, [x28, 125] +- __ strs(v24, Address(r15, -20)); // str s24, [x15, -20] - -// pre -+ __ str(r11, Address(r20, -103)); // str x11, [x20, -103] -+ __ strw(r28, Address(r16, 62)); // str w28, [x16, 62] -+ __ strb(r27, Address(r9, -9)); // strb w27, [x9, -9] -+ __ strh(r2, Address(r25, -50)); // strh w2, [x25, -50] -+ __ ldr(r4, Address(r2, -241)); // ldr x4, [x2, -241] -+ __ ldrw(r30, Address(r20, -31)); // ldr w30, [x20, -31] -+ __ ldrb(r18, Address(r23, -23)); // ldrb w18, [x23, -23] -+ __ ldrh(r29, Address(r26, -1)); // ldrh w29, [x26, -1] -+ __ ldrsb(r1, Address(r9, 6)); // ldrsb x1, [x9, 6] -+ __ ldrsh(r11, Address(r12, 19)); // ldrsh x11, [x12, 19] -+ __ ldrshw(r11, Address(r1, -50)); // ldrsh w11, [x1, -50] -+ __ ldrsw(r19, Address(r24, 41)); // ldrsw x19, [x24, 41] -+ __ ldrd(v24, Address(r24, 95)); // ldr d24, [x24, 95] -+ __ ldrs(v15, Address(r5, -43)); // ldr s15, [x5, -43] -+ __ strd(v21, Address(r27, 1)); // str d21, [x27, 1] -+ __ strs(v23, Address(r13, -107)); // str s23, [x13, -107] ++ __ str(r16, Address(r19, -75)); // str x16, [x19, -75] ++ __ strw(r1, Address(r28, 30)); // str w1, [x28, 30] ++ __ strb(r28, Address(r13, -26)); // strb w28, [x13, -26] ++ __ strh(r8, Address(r6, -51)); // strh w8, [x6, -51] ++ __ ldr(r0, Address(r28, -227)); // ldr x0, [x28, -227] ++ __ ldrw(r28, Address(r10, -26)); // ldr w28, [x10, -26] ++ __ ldrb(r4, Address(r11, 12)); // ldrb w4, [x11, 12] ++ __ ldrh(r1, Address(r17, 5)); // ldrh w1, [x17, 5] ++ __ ldrsb(r11, Address(r9, 12)); // ldrsb x11, [x9, 12] ++ __ ldrsh(r8, Address(r8, -17)); // ldrsh x8, [x8, -17] ++ __ ldrshw(r20, Address(r13, -35)); // ldrsh w20, [x13, -35] ++ __ ldrsw(r23, Address(r9, 49)); // ldrsw x23, [x9, 49] ++ __ ldrd(v9, Address(r4, 29)); // ldr d9, [x4, 29] ++ __ ldrs(v11, Address(r19, 40)); // ldr s11, [x19, 40] ++ __ strd(v25, Address(r20, -43)); // str d25, [x20, -43] ++ __ strs(v25, Address(r1, -80)); // str s25, [x1, -80] + +// pre // LoadStoreOp -- __ str(r9, Address(__ pre(r18, -112))); // str x9, [x18, -112]! -- __ strw(r29, Address(__ pre(r23, 11))); // str w29, [x23, 11]! -- __ strb(r18, Address(__ pre(r12, -1))); // strb w18, [x12, -1]! -- __ strh(r16, Address(__ pre(r20, -23))); // strh w16, [x20, -23]! -- __ ldr(r3, Address(__ pre(r29, 9))); // ldr x3, [x29, 9]! -- __ ldrw(r25, Address(__ pre(r3, 19))); // ldr w25, [x3, 19]! -- __ ldrb(r1, Address(__ pre(r29, -1))); // ldrb w1, [x29, -1]! -- __ ldrh(r8, Address(__ pre(r29, -57))); // ldrh w8, [x29, -57]! -- __ ldrsb(r5, Address(__ pre(r14, -13))); // ldrsb x5, [x14, -13]! -- __ ldrsh(r10, Address(__ pre(r27, 1))); // ldrsh x10, [x27, 1]! -- __ ldrshw(r11, Address(__ pre(r10, 25))); // ldrsh w11, [x10, 25]! -- __ ldrsw(r4, Address(__ pre(r22, -92))); // ldrsw x4, [x22, -92]! -- __ ldrd(v11, Address(__ pre(r23, 8))); // ldr d11, [x23, 8]! -- __ ldrs(v25, Address(__ pre(r19, 54))); // ldr s25, [x19, 54]! -- __ strd(v1, Address(__ pre(r7, -174))); // str d1, [x7, -174]! -- __ strs(v8, Address(__ pre(r25, 54))); // str s8, [x25, 54]! +- __ str(r8, Address(__ pre(r28, -24))); // str x8, [x28, -24]! +- __ strw(r6, Address(__ pre(r15, 37))); // str w6, [x15, 37]! +- __ strb(r7, Address(__ pre(r1, 7))); // strb w7, [x1, 7]! +- __ strh(r0, Address(__ pre(r17, 30))); // strh w0, [x17, 30]! +- __ ldr(r25, Address(__ pre(r29, 84))); // ldr x25, [x29, 84]! +- __ ldrw(r26, Address(__ pre(r20, -52))); // ldr w26, [x20, -52]! +- __ ldrb(r26, Address(__ pre(r29, -25))); // ldrb w26, [x29, -25]! +- __ ldrh(r4, Address(__ pre(r25, 26))); // ldrh w4, [x25, 26]! +- __ ldrsb(r28, Address(__ pre(r8, -21))); // ldrsb x28, [x8, -21]! +- __ ldrsh(r17, Address(__ pre(r14, -6))); // ldrsh x17, [x14, -6]! +- __ ldrshw(r28, Address(__ pre(r23, 10))); // ldrsh w28, [x23, 10]! +- __ ldrsw(r30, Address(__ pre(r27, -64))); // ldrsw x30, [x27, -64]! +- __ ldrd(v20, Address(__ pre(r30, -242))); // ldr d20, [x30, -242]! +- __ ldrs(v17, Address(__ pre(r27, 20))); // ldr s17, [x27, 20]! +- __ strd(v7, Address(__ pre(r3, 17))); // str d7, [x3, 17]! +- __ strs(v13, Address(__ pre(r11, -16))); // str s13, [x11, -16]! - -// post -+ __ str(r11, Address(__ pre(r0, 8))); // str x11, [x0, 8]! -+ __ strw(r3, Address(__ pre(r0, 29))); // str w3, [x0, 29]! -+ __ strb(r11, Address(__ pre(r14, 9))); // strb w11, [x14, 9]! -+ __ strh(r29, Address(__ pre(r24, -3))); // strh w29, [x24, -3]! -+ __ ldr(r13, Address(__ pre(r17, -144))); // ldr x13, [x17, -144]! -+ __ ldrw(r12, Address(__ pre(r22, -6))); // ldr w12, [x22, -6]! -+ __ ldrb(r13, Address(__ pre(r12, -10))); // ldrb w13, [x12, -10]! -+ __ ldrh(r0, Address(__ pre(r21, -21))); // ldrh w0, [x21, -21]! -+ __ ldrsb(r23, Address(__ pre(r7, 4))); // ldrsb x23, [x7, 4]! -+ __ ldrsh(r3, Address(__ pre(r7, -53))); // ldrsh x3, [x7, -53]! -+ __ ldrshw(r28, Address(__ pre(r5, -7))); // ldrsh w28, [x5, -7]! -+ __ ldrsw(r24, Address(__ pre(r9, -18))); // ldrsw x24, [x9, -18]! -+ __ ldrd(v14, Address(__ pre(r11, 12))); // ldr d14, [x11, 12]! -+ __ ldrs(v19, Address(__ pre(r12, -67))); // ldr s19, [x12, -67]! -+ __ strd(v20, Address(__ pre(r0, -253))); // str d20, [x0, -253]! -+ __ strs(v8, Address(__ pre(r0, 64))); // str s8, [x0, 64]! ++ __ str(r20, Address(__ pre(r0, 25))); // str x20, [x0, 25]! ++ __ strw(r12, Address(__ pre(r12, -49))); // str w12, [x12, -49]! ++ __ strb(r28, Address(__ pre(r19, -10))); // strb w28, [x19, -10]! ++ __ strh(r13, Address(__ pre(r28, -63))); // strh w13, [x28, -63]! ++ __ ldr(r11, Address(__ pre(r23, -46))); // ldr x11, [x23, -46]! ++ __ ldrw(r27, Address(__ pre(r24, 17))); // ldr w27, [x24, 17]! ++ __ ldrb(r14, Address(__ pre(r26, -12))); // ldrb w14, [x26, -12]! ++ __ ldrh(r24, Address(__ pre(r22, -45))); // ldrh w24, [x22, -45]! ++ __ ldrsb(r25, Address(__ pre(r9, -11))); // ldrsb x25, [x9, -11]! ++ __ ldrsh(r5, Address(__ pre(r6, 29))); // ldrsh x5, [x6, 29]! ++ __ ldrshw(r7, Address(__ pre(r23, -1))); // ldrsh w7, [x23, -1]! ++ __ ldrsw(r26, Address(__ pre(r13, -61))); // ldrsw x26, [x13, -61]! ++ __ ldrd(v24, Address(__ pre(r24, -245))); // ldr d24, [x24, -245]! ++ __ ldrs(v20, Address(__ pre(r25, -55))); // ldr s20, [x25, -55]! ++ __ strd(v9, Address(__ pre(r2, -203))); // str d9, [x2, -203]! ++ __ strs(v14, Address(__ pre(r1, -59))); // str s14, [x1, -59]! + +// post // LoadStoreOp -- __ str(r5, Address(__ post(r11, 37))); // str x5, [x11], 37 -- __ strw(r24, Address(__ post(r15, 19))); // str w24, [x15], 19 -- __ strb(r15, Address(__ post(r26, -1))); // strb w15, [x26], -1 -- __ strh(r18, Address(__ post(r18, -6))); // strh w18, [x18], -6 -- __ ldr(r7, Address(__ post(r2, -230))); // ldr x7, [x2], -230 -- __ ldrw(r27, Address(__ post(r11, -27))); // ldr w27, [x11], -27 -- __ ldrb(r18, Address(__ post(r3, -25))); // ldrb w18, [x3], -25 -- __ ldrh(r10, Address(__ post(r24, -32))); // ldrh w10, [x24], -32 -- __ ldrsb(r22, Address(__ post(r10, 4))); // ldrsb x22, [x10], 4 -- __ ldrsh(r17, Address(__ post(r12, 25))); // ldrsh x17, [x12], 25 -- __ ldrshw(r8, Address(__ post(r7, -62))); // ldrsh w8, [x7], -62 -- __ ldrsw(r23, Address(__ post(r22, -51))); // ldrsw x23, [x22], -51 -- __ ldrd(v24, Address(__ post(r25, 48))); // ldr d24, [x25], 48 -- __ ldrs(v21, Address(__ post(r12, -10))); // ldr s21, [x12], -10 -- __ strd(v18, Address(__ post(r13, -222))); // str d18, [x13], -222 -- __ strs(v16, Address(__ post(r1, -41))); // str s16, [x1], -41 +- __ str(r6, Address(__ post(r9, -61))); // str x6, [x9], -61 +- __ strw(r16, Address(__ post(r5, -29))); // str w16, [x5], -29 +- __ strb(r29, Address(__ post(r29, 15))); // strb w29, [x29], 15 +- __ strh(r4, Address(__ post(r20, 18))); // strh w4, [x20], 18 +- __ ldr(r19, Address(__ post(r18, 46))); // ldr x19, [x18], 46 +- __ ldrw(r22, Address(__ post(r2, 23))); // ldr w22, [x2], 23 +- __ ldrb(r7, Address(__ post(r3, -30))); // ldrb w7, [x3], -30 +- __ ldrh(r11, Address(__ post(r12, -29))); // ldrh w11, [x12], -29 +- __ ldrsb(r8, Address(__ post(r6, -29))); // ldrsb x8, [x6], -29 +- __ ldrsh(r24, Address(__ post(r23, 4))); // ldrsh x24, [x23], 4 +- __ ldrshw(r17, Address(__ post(r16, 0))); // ldrsh w17, [x16], 0 +- __ ldrsw(r0, Address(__ post(r20, -8))); // ldrsw x0, [x20], -8 +- __ ldrd(v20, Address(__ post(r2, -126))); // ldr d20, [x2], -126 +- __ ldrs(v19, Address(__ post(r30, -104))); // ldr s19, [x30], -104 +- __ strd(v4, Address(__ post(r17, 118))); // str d4, [x17], 118 +- __ strs(v21, Address(__ post(r19, -112))); // str s21, [x19], -112 - -// base_plus_reg -+ __ str(r4, Address(__ post(r28, -94))); // str x4, [x28], -94 -+ __ strw(r12, Address(__ post(r7, -54))); // str w12, [x7], -54 -+ __ strb(r27, Address(__ post(r10, -24))); // strb w27, [x10], -24 -+ __ strh(r6, Address(__ post(r8, 27))); // strh w6, [x8], 27 -+ __ ldr(r14, Address(__ post(r10, -202))); // ldr x14, [x10], -202 -+ __ ldrw(r16, Address(__ post(r5, -41))); // ldr w16, [x5], -41 -+ __ ldrb(r2, Address(__ post(r14, 9))); // ldrb w2, [x14], 9 -+ __ ldrh(r28, Address(__ post(r13, -20))); // ldrh w28, [x13], -20 -+ __ ldrsb(r9, Address(__ post(r13, -31))); // ldrsb x9, [x13], -31 -+ __ ldrsh(r3, Address(__ post(r24, -36))); // ldrsh x3, [x24], -36 -+ __ ldrshw(r20, Address(__ post(r3, 6))); // ldrsh w20, [x3], 6 -+ __ ldrsw(r7, Address(__ post(r19, -1))); // ldrsw x7, [x19], -1 -+ __ ldrd(v30, Address(__ post(r8, -130))); // ldr d30, [x8], -130 -+ __ ldrs(v25, Address(__ post(r15, 21))); // ldr s25, [x15], 21 -+ __ strd(v14, Address(__ post(r23, 90))); // str d14, [x23], 90 -+ __ strs(v8, Address(__ post(r0, -33))); // str s8, [x0], -33 ++ __ str(r19, Address(__ post(r1, 109))); // str x19, [x1], 109 ++ __ strw(r4, Address(__ post(r5, -54))); // str w4, [x5], -54 ++ __ strb(r29, Address(__ post(r3, 9))); // strb w29, [x3], 9 ++ __ strh(r0, Address(__ post(r1, -50))); // strh w0, [x1], -50 ++ __ ldr(r2, Address(__ post(r6, -48))); // ldr x2, [x6], -48 ++ __ ldrw(r15, Address(__ post(r6, -115))); // ldr w15, [x6], -115 ++ __ ldrb(r4, Address(__ post(r2, -27))); // ldrb w4, [x2], -27 ++ __ ldrh(r17, Address(__ post(r26, -21))); // ldrh w17, [x26], -21 ++ __ ldrsb(r21, Address(__ post(r24, -13))); // ldrsb x21, [x24], -13 ++ __ ldrsh(r22, Address(__ post(r6, -48))); // ldrsh x22, [x6], -48 ++ __ ldrshw(r11, Address(__ post(r6, -48))); // ldrsh w11, [x6], -48 ++ __ ldrsw(r14, Address(__ post(r30, -5))); // ldrsw x14, [x30], -5 ++ __ ldrd(v2, Address(__ post(r15, -105))); // ldr d2, [x15], -105 ++ __ ldrs(v25, Address(__ post(r19, -91))); // ldr s25, [x19], -91 ++ __ strd(v13, Address(__ post(r23, -191))); // str d13, [x23], -191 ++ __ strs(v22, Address(__ post(r21, 0))); // str s22, [x21], 0 + +// base_plus_reg // LoadStoreOp -- __ str(r2, Address(r22, r15, Address::sxtw(0))); // str x2, [x22, w15, sxtw #0] -- __ strw(r2, Address(r16, r29, Address::lsl(0))); // str w2, [x16, x29, lsl #0] -- __ strb(r20, Address(r18, r14, Address::uxtw(0))); // strb w20, [x18, w14, uxtw #0] -- __ strh(r6, Address(r19, r20, Address::sxtx(1))); // strh w6, [x19, x20, sxtx #1] -- __ ldr(r14, Address(r29, r14, Address::sxtw(0))); // ldr x14, [x29, w14, sxtw #0] -- __ ldrw(r16, Address(r20, r12, Address::sxtw(2))); // ldr w16, [x20, w12, sxtw #2] -- __ ldrb(r9, Address(r12, r0, Address::sxtw(0))); // ldrb w9, [x12, w0, sxtw #0] -- __ ldrh(r12, Address(r17, r3, Address::lsl(1))); // ldrh w12, [x17, x3, lsl #1] -- __ ldrsb(r2, Address(r17, r3, Address::sxtx(0))); // ldrsb x2, [x17, x3, sxtx #0] -- __ ldrsh(r7, Address(r1, r17, Address::uxtw(1))); // ldrsh x7, [x1, w17, uxtw #1] -- __ ldrshw(r25, Address(r15, r18, Address::sxtw(1))); // ldrsh w25, [x15, w18, sxtw #1] -- __ ldrsw(r23, Address(r21, r12, Address::lsl(0))); // ldrsw x23, [x21, x12, lsl #0] -- __ ldrd(v5, Address(r13, r8, Address::lsl(3))); // ldr d5, [x13, x8, lsl #3] -- __ ldrs(v3, Address(r10, r22, Address::lsl(2))); // ldr s3, [x10, x22, lsl #2] -- __ strd(v14, Address(r2, r27, Address::sxtw(0))); // str d14, [x2, w27, sxtw #0] -- __ strs(v20, Address(r6, r25, Address::lsl(0))); // str s20, [x6, x25, lsl #0] +- __ str(r26, Address(r2, r19, Address::lsl(3))); // str x26, [x2, x19, lsl #3] +- __ strw(r9, Address(r0, r15, Address::sxtw(2))); // str w9, [x0, w15, sxtw #2] +- __ strb(r26, Address(r12, r1, Address::lsl(0))); // strb w26, [x12, x1, lsl #0] +- __ strh(r21, Address(r11, r10, Address::lsl(1))); // strh w21, [x11, x10, lsl #1] +- __ ldr(r16, Address(r23, r16, Address::sxtx(0))); // ldr x16, [x23, x16, sxtx #0] +- __ ldrw(r10, Address(r11, r17, Address::sxtw(2))); // ldr w10, [x11, w17, sxtw #2] +- __ ldrb(r13, Address(r23, r11, Address::lsl(0))); // ldrb w13, [x23, x11, lsl #0] +- __ ldrh(r27, Address(r4, r21, Address::lsl(0))); // ldrh w27, [x4, x21, lsl #0] +- __ ldrsb(r26, Address(r8, r15, Address::sxtw(0))); // ldrsb x26, [x8, w15, sxtw #0] +- __ ldrsh(r21, Address(r10, r2, Address::sxtw(0))); // ldrsh x21, [x10, w2, sxtw #0] +- __ ldrshw(r8, Address(r30, r14, Address::lsl(0))); // ldrsh w8, [x30, x14, lsl #0] +- __ ldrsw(r29, Address(r14, r20, Address::sxtx(2))); // ldrsw x29, [x14, x20, sxtx #2] +- __ ldrd(v30, Address(r27, r22, Address::sxtx(0))); // ldr d30, [x27, x22, sxtx #0] +- __ ldrs(v13, Address(r9, r22, Address::lsl(0))); // ldr s13, [x9, x22, lsl #0] +- __ strd(v8, Address(r25, r17, Address::sxtw(3))); // str d8, [x25, w17, sxtw #3] +- __ strs(v1, Address(r24, r5, Address::uxtw(2))); // str s1, [x24, w5, uxtw #2] - -// base_plus_scaled_offset -+ __ str(r10, Address(r18, r21, Address::sxtw(3))); // str x10, [x18, w21, sxtw #3] -+ __ strw(r4, Address(r13, r22, Address::sxtw(2))); // str w4, [x13, w22, sxtw #2] -+ __ strb(r13, Address(r0, r19, Address::uxtw(0))); // strb w13, [x0, w19, uxtw #0] -+ __ strh(r12, Address(r27, r6, Address::sxtw(0))); // strh w12, [x27, w6, sxtw #0] -+ __ ldr(r0, Address(r8, r16, Address::lsl(0))); // ldr x0, [x8, x16, lsl #0] -+ __ ldrw(r0, Address(r4, r26, Address::sxtx(0))); // ldr w0, [x4, x26, sxtx #0] -+ __ ldrb(r14, Address(r25, r5, Address::sxtw(0))); // ldrb w14, [x25, w5, sxtw #0] -+ __ ldrh(r9, Address(r4, r18, Address::uxtw(0))); // ldrh w9, [x4, w18, uxtw #0] -+ __ ldrsb(r27, Address(r4, r7, Address::lsl(0))); // ldrsb x27, [x4, x7, lsl #0] -+ __ ldrsh(r15, Address(r17, r30, Address::sxtw(0))); // ldrsh x15, [x17, w30, sxtw #0] -+ __ ldrshw(r16, Address(r0, r22, Address::sxtw(0))); // ldrsh w16, [x0, w22, sxtw #0] -+ __ ldrsw(r22, Address(r10, r30, Address::sxtx(2))); // ldrsw x22, [x10, x30, sxtx #2] -+ __ ldrd(v29, Address(r21, r10, Address::sxtx(3))); // ldr d29, [x21, x10, sxtx #3] -+ __ ldrs(v3, Address(r11, r19, Address::uxtw(0))); // ldr s3, [x11, w19, uxtw #0] -+ __ strd(v13, Address(r28, r29, Address::uxtw(3))); // str d13, [x28, w29, uxtw #3] -+ __ strs(v23, Address(r29, r5, Address::sxtx(2))); // str s23, [x29, x5, sxtx #2] ++ __ str(r22, Address(r12, r18, Address::sxtw(0))); // str x22, [x12, w18, sxtw #0] ++ __ strw(r30, Address(r27, r12, Address::uxtw(0))); // str w30, [x27, w12, uxtw #0] ++ __ strb(r7, Address(r4, r22, Address::lsl(0))); // strb w7, [x4, x22, lsl #0] ++ __ strh(r19, Address(r23, r29, Address::sxtx(1))); // strh w19, [x23, x29, sxtx #1] ++ __ ldr(r17, Address(r4, r27, Address::sxtx(3))); // ldr x17, [x4, x27, sxtx #3] ++ __ ldrw(r1, Address(r13, r17, Address::sxtw(0))); // ldr w1, [x13, w17, sxtw #0] ++ __ ldrb(r16, Address(r27, r29, Address::sxtx(0))); // ldrb w16, [x27, x29, sxtx #0] ++ __ ldrh(r25, Address(r9, r4, Address::uxtw(1))); // ldrh w25, [x9, w4, uxtw #1] ++ __ ldrsb(r4, Address(r12, r22, Address::lsl(0))); // ldrsb x4, [x12, x22, lsl #0] ++ __ ldrsh(r25, Address(r1, r5, Address::uxtw(1))); // ldrsh x25, [x1, w5, uxtw #1] ++ __ ldrshw(r9, Address(r16, r28, Address::lsl(0))); // ldrsh w9, [x16, x28, lsl #0] ++ __ ldrsw(r8, Address(r7, r14, Address::sxtx(0))); // ldrsw x8, [x7, x14, sxtx #0] ++ __ ldrd(v4, Address(r28, r16, Address::uxtw(3))); // ldr d4, [x28, w16, uxtw #3] ++ __ ldrs(v16, Address(r2, r27, Address::sxtw(2))); // ldr s16, [x2, w27, sxtw #2] ++ __ strd(v23, Address(r0, r25, Address::lsl(0))); // str d23, [x0, x25, lsl #0] ++ __ strs(v6, Address(r16, r7, Address::lsl(2))); // str s6, [x16, x7, lsl #2] + +// base_plus_scaled_offset // LoadStoreOp -- __ str(r30, Address(r7, 16256)); // str x30, [x7, 16256] -- __ strw(r15, Address(r8, 7588)); // str w15, [x8, 7588] -- __ strb(r11, Address(r0, 1866)); // strb w11, [x0, 1866] -- __ strh(r3, Address(r17, 3734)); // strh w3, [x17, 3734] -- __ ldr(r2, Address(r7, 14224)); // ldr x2, [x7, 14224] -- __ ldrw(r5, Address(r9, 7396)); // ldr w5, [x9, 7396] -- __ ldrb(r28, Address(r9, 1721)); // ldrb w28, [x9, 1721] -- __ ldrh(r2, Address(r20, 3656)); // ldrh w2, [x20, 3656] -- __ ldrsb(r22, Address(r14, 1887)); // ldrsb x22, [x14, 1887] -- __ ldrsh(r8, Address(r0, 4080)); // ldrsh x8, [x0, 4080] -- __ ldrshw(r0, Address(r30, 3916)); // ldrsh w0, [x30, 3916] -- __ ldrsw(r24, Address(r19, 6828)); // ldrsw x24, [x19, 6828] -- __ ldrd(v24, Address(r12, 13032)); // ldr d24, [x12, 13032] -- __ ldrs(v8, Address(r8, 7452)); // ldr s8, [x8, 7452] -- __ strd(v10, Address(r15, 15992)); // str d10, [x15, 15992] -- __ strs(v26, Address(r19, 6688)); // str s26, [x19, 6688] +- __ str(r10, Address(r21, 14496)); // str x10, [x21, 14496] +- __ strw(r18, Address(r29, 7228)); // str w18, [x29, 7228] +- __ strb(r23, Address(r3, 2018)); // strb w23, [x3, 2018] +- __ strh(r28, Address(r11, 3428)); // strh w28, [x11, 3428] +- __ ldr(r24, Address(r26, 14376)); // ldr x24, [x26, 14376] +- __ ldrw(r21, Address(r2, 6972)); // ldr w21, [x2, 6972] +- __ ldrb(r4, Address(r5, 1848)); // ldrb w4, [x5, 1848] +- __ ldrh(r14, Address(r14, 3112)); // ldrh w14, [x14, 3112] +- __ ldrsb(r4, Address(r27, 1959)); // ldrsb x4, [x27, 1959] +- __ ldrsh(r4, Address(r27, 3226)); // ldrsh x4, [x27, 3226] +- __ ldrshw(r10, Address(r28, 3286)); // ldrsh w10, [x28, 3286] +- __ ldrsw(r10, Address(r17, 7912)); // ldrsw x10, [x17, 7912] +- __ ldrd(v13, Address(r28, 13400)); // ldr d13, [x28, 13400] +- __ ldrs(v24, Address(r3, 7596)); // ldr s24, [x3, 7596] +- __ strd(v2, Address(r12, 15360)); // str d2, [x12, 15360] +- __ strs(v17, Address(r1, 6492)); // str s17, [x1, 6492] - -// pcrel -+ __ str(r5, Address(r8, 12600)); // str x5, [x8, 12600] -+ __ strw(r29, Address(r24, 7880)); // str w29, [x24, 7880] -+ __ strb(r19, Address(r17, 1566)); // strb w19, [x17, 1566] -+ __ strh(r13, Address(r19, 3984)); // strh w13, [x19, 3984] -+ __ ldr(r19, Address(r23, 13632)); // ldr x19, [x23, 13632] -+ __ ldrw(r23, Address(r29, 6264)); // ldr w23, [x29, 6264] -+ __ ldrb(r22, Address(r11, 2012)); // ldrb w22, [x11, 2012] -+ __ ldrh(r3, Address(r10, 3784)); // ldrh w3, [x10, 3784] -+ __ ldrsb(r8, Address(r16, 1951)); // ldrsb x8, [x16, 1951] -+ __ ldrsh(r23, Address(r20, 3346)); // ldrsh x23, [x20, 3346] -+ __ ldrshw(r2, Address(r1, 3994)); // ldrsh w2, [x1, 3994] -+ __ ldrsw(r4, Address(r17, 7204)); // ldrsw x4, [x17, 7204] -+ __ ldrd(v20, Address(r27, 14400)); // ldr d20, [x27, 14400] -+ __ ldrs(v25, Address(r14, 8096)); // ldr s25, [x14, 8096] -+ __ strd(v26, Address(r10, 15024)); // str d26, [x10, 15024] -+ __ strs(v9, Address(r3, 6936)); // str s9, [x3, 6936] ++ __ str(r2, Address(r12, 15288)); // str x2, [x12, 15288] ++ __ strw(r8, Address(r5, 6928)); // str w8, [x5, 6928] ++ __ strb(r1, Address(r17, 2016)); // strb w1, [x17, 2016] ++ __ strh(r8, Address(r25, 3258)); // strh w8, [x25, 3258] ++ __ ldr(r28, Address(r3, 14656)); // ldr x28, [x3, 14656] ++ __ ldrw(r21, Address(r11, 7004)); // ldr w21, [x11, 7004] ++ __ ldrb(r15, Address(r5, 1906)); // ldrb w15, [x5, 1906] ++ __ ldrh(r0, Address(r19, 3668)); // ldrh w0, [x19, 3668] ++ __ ldrsb(r29, Address(r9, 1909)); // ldrsb x29, [x9, 1909] ++ __ ldrsh(r23, Address(r28, 3640)); // ldrsh x23, [x28, 3640] ++ __ ldrshw(r27, Address(r10, 3672)); // ldrsh w27, [x10, 3672] ++ __ ldrsw(r21, Address(r27, 7736)); // ldrsw x21, [x27, 7736] ++ __ ldrd(v26, Address(r27, 14584)); // ldr d26, [x27, 14584] ++ __ ldrs(v2, Address(r4, 7464)); // ldr s2, [x4, 7464] ++ __ strd(v1, Address(r21, 16224)); // str d1, [x21, 16224] ++ __ strs(v4, Address(r22, 7552)); // str s4, [x22, 7552] + +// pcrel // LoadStoreOp -- __ ldr(r10, forth); // ldr x10, forth -- __ ldrw(r3, __ pc()); // ldr w3, . -+ __ ldr(r27, forth); // ldr x27, forth -+ __ ldrw(r11, __ pc()); // ldr w11, . +- __ ldr(r16, __ pc()); // ldr x16, . +- __ ldrw(r13, __ pc()); // ldr w13, . ++ __ ldr(r1, __ pc()); // ldr x1, . ++ __ ldrw(r27, __ pc()); // ldr w27, . // LoadStoreOp -- __ prfm(Address(r23, 9)); // prfm PLDL1KEEP, [x23, 9] -+ __ prfm(Address(r3, -187)); // prfm PLDL1KEEP, [x3, -187] +- __ prfm(Address(r18, -127)); // prfm PLDL1KEEP, [x18, -127] ++ __ prfm(Address(r4, 45)); // prfm PLDL1KEEP, [x4, 45] // LoadStoreOp -- __ prfm(back); // prfm PLDL1KEEP, back +- __ prfm(back); // prfm PLDL1KEEP, back + __ prfm(__ pc()); // prfm PLDL1KEEP, . // LoadStoreOp -- __ prfm(Address(r3, r8, Address::uxtw(0))); // prfm PLDL1KEEP, [x3, w8, uxtw #0] -+ __ prfm(Address(r29, r14, Address::lsl(0))); // prfm PLDL1KEEP, [x29, x14, lsl #0] +- __ prfm(Address(r20, r2, Address::lsl(3))); // prfm PLDL1KEEP, [x20, x2, lsl #3] ++ __ prfm(Address(r30, r0, Address::sxtw(0))); // prfm PLDL1KEEP, [x30, w0, sxtw #0] // LoadStoreOp -- __ prfm(Address(r11, 15080)); // prfm PLDL1KEEP, [x11, 15080] -+ __ prfm(Address(r4, 13312)); // prfm PLDL1KEEP, [x4, 13312] +- __ prfm(Address(r9, 13808)); // prfm PLDL1KEEP, [x9, 13808] ++ __ prfm(Address(r24, 16208)); // prfm PLDL1KEEP, [x24, 16208] // AddSubCarryOp -- __ adcw(r13, r9, r28); // adc w13, w9, w28 -- __ adcsw(r27, r19, r28); // adcs w27, w19, w28 -- __ sbcw(r19, r18, r6); // sbc w19, w18, w6 -- __ sbcsw(r14, r20, r3); // sbcs w14, w20, w3 -- __ adc(r16, r14, r8); // adc x16, x14, x8 -- __ adcs(r0, r29, r8); // adcs x0, x29, x8 -- __ sbc(r8, r24, r20); // sbc x8, x24, x20 -- __ sbcs(r12, r28, r0); // sbcs x12, x28, x0 -+ __ adcw(r21, r1, r7); // adc w21, w1, w7 -+ __ adcsw(r8, r5, r7); // adcs w8, w5, w7 -+ __ sbcw(r7, r27, r14); // sbc w7, w27, w14 -+ __ sbcsw(r27, r4, r17); // sbcs w27, w4, w17 -+ __ adc(r0, r28, r0); // adc x0, x28, x0 -+ __ adcs(r12, r24, r30); // adcs x12, x24, x30 -+ __ sbc(r0, r25, r15); // sbc x0, x25, x15 -+ __ sbcs(r1, r24, r3); // sbcs x1, x24, x3 +- __ adcw(r8, r23, r2); // adc w8, w23, w2 +- __ adcsw(r24, r3, r19); // adcs w24, w3, w19 +- __ sbcw(r22, r24, r29); // sbc w22, w24, w29 +- __ sbcsw(r12, r27, r3); // sbcs w12, w27, w3 +- __ adc(r11, r23, r1); // adc x11, x23, x1 +- __ adcs(r29, r5, r23); // adcs x29, x5, x23 +- __ sbc(r9, r25, r12); // sbc x9, x25, x12 +- __ sbcs(r12, r0, r22); // sbcs x12, x0, x22 ++ __ adcw(r0, r29, r24); // adc w0, w29, w24 ++ __ adcsw(r22, r28, r18); // adcs w22, w28, w18 ++ __ sbcw(r23, r16, r30); // sbc w23, w16, w30 ++ __ sbcsw(r7, r29, r14); // sbcs w7, w29, w14 ++ __ adc(r22, r12, r14); // adc x22, x12, x14 ++ __ adcs(r29, r24, r23); // adcs x29, x24, x23 ++ __ sbc(r17, r28, r22); // sbc x17, x28, x22 ++ __ sbcs(r24, r20, r19); // sbcs x24, x20, x19 // AddSubExtendedOp -- __ addw(r23, r6, r16, ext::uxtb, 4); // add w23, w6, w16, uxtb #4 -- __ addsw(r25, r25, r23, ext::sxth, 2); // adds w25, w25, w23, sxth #2 -- __ sub(r26, r22, r4, ext::uxtx, 1); // sub x26, x22, x4, uxtx #1 -- __ subsw(r17, r29, r19, ext::sxtx, 3); // subs w17, w29, w19, sxtx #3 -- __ add(r11, r30, r21, ext::uxtb, 3); // add x11, x30, x21, uxtb #3 -- __ adds(r16, r19, r0, ext::sxtb, 2); // adds x16, x19, x0, sxtb #2 -- __ sub(r11, r9, r25, ext::sxtx, 1); // sub x11, x9, x25, sxtx #1 -- __ subs(r17, r20, r12, ext::sxtb, 4); // subs x17, x20, x12, sxtb #4 -+ __ addw(r18, r24, r20, ext::uxtb, 2); // add w18, w24, w20, uxtb #2 -+ __ addsw(r13, r28, r10, ext::uxth, 1); // adds w13, w28, w10, uxth #1 -+ __ sub(r15, r16, r2, ext::sxth, 2); // sub x15, x16, x2, sxth #2 -+ __ subsw(r29, r13, r13, ext::uxth, 2); // subs w29, w13, w13, uxth #2 -+ __ add(r12, r20, r12, ext::sxtw, 3); // add x12, x20, x12, sxtw #3 -+ __ adds(r30, r27, r11, ext::sxtb, 1); // adds x30, x27, x11, sxtb #1 -+ __ sub(r14, r7, r1, ext::sxtw, 2); // sub x14, x7, x1, sxtw #2 -+ __ subs(r29, r3, r27, ext::sxth, 1); // subs x29, x3, x27, sxth #1 +- __ addw(r26, r12, r3, ext::uxtw, 1); // add w26, w12, w3, uxtw #1 +- __ addsw(r20, r16, r18, ext::sxtb, 2); // adds w20, w16, w18, sxtb #2 +- __ sub(r30, r30, r7, ext::uxtw, 2); // sub x30, x30, x7, uxtw #2 +- __ subsw(r11, r21, r2, ext::uxth, 3); // subs w11, w21, w2, uxth #3 +- __ add(r2, r26, r1, ext::uxtw, 2); // add x2, x26, x1, uxtw #2 +- __ adds(r18, r29, r20, ext::sxth, 1); // adds x18, x29, x20, sxth #1 +- __ sub(r14, r16, r4, ext::uxtw, 4); // sub x14, x16, x4, uxtw #4 +- __ subs(r0, r17, r23, ext::sxtb, 3); // subs x0, x17, x23, sxtb #3 ++ __ addw(r27, r22, r6, ext::sxtw, 2); // add w27, w22, w6, sxtw #2 ++ __ addsw(r13, r11, r24, ext::uxtw, 4); // adds w13, w11, w24, uxtw #4 ++ __ sub(r16, r8, r4, ext::uxth, 3); // sub x16, x8, x4, uxth #3 ++ __ subsw(r21, r18, r20, ext::sxtx, 2); // subs w21, w18, w20, sxtx #2 ++ __ add(r14, r17, r29, ext::uxtb, 2); // add x14, x17, x29, uxtb #2 ++ __ adds(r17, r17, r14, ext::sxth, 4); // adds x17, x17, x14, sxth #4 ++ __ sub(r22, r3, r26, ext::sxtw, 1); // sub x22, x3, x26, sxtw #1 ++ __ subs(r13, r13, r21, ext::uxth, 4); // subs x13, x13, x21, uxth #4 // ConditionalCompareOp -- __ ccmnw(r13, r11, 3u, Assembler::LE); // ccmn w13, w11, #3, LE -- __ ccmpw(r13, r12, 2u, Assembler::HI); // ccmp w13, w12, #2, HI -- __ ccmn(r3, r2, 12u, Assembler::NE); // ccmn x3, x2, #12, NE -- __ ccmp(r7, r21, 3u, Assembler::VS); // ccmp x7, x21, #3, VS -+ __ ccmnw(r0, r13, 14u, Assembler::MI); // ccmn w0, w13, #14, MI -+ __ ccmpw(r22, r18, 6u, Assembler::CC); // ccmp w22, w18, #6, CC -+ __ ccmn(r18, r30, 14u, Assembler::VS); // ccmn x18, x30, #14, VS -+ __ ccmp(r10, r19, 12u, Assembler::HI); // ccmp x10, x19, #12, HI +- __ ccmnw(r20, r22, 3u, Assembler::PL); // ccmn w20, w22, #3, PL +- __ ccmpw(r25, r2, 1u, Assembler::EQ); // ccmp w25, w2, #1, EQ +- __ ccmn(r18, r24, 7u, Assembler::GT); // ccmn x18, x24, #7, GT +- __ ccmp(r8, r13, 6u, Assembler::PL); // ccmp x8, x13, #6, PL ++ __ ccmnw(r17, r26, 15u, Assembler::VC); // ccmn w17, w26, #15, VC ++ __ ccmpw(r25, r6, 5u, Assembler::LO); // ccmp w25, w6, #5, LO ++ __ ccmn(r1, r30, 1u, Assembler::LS); // ccmn x1, x30, #1, LS ++ __ ccmp(r17, r7, 2u, Assembler::GE); // ccmp x17, x7, #2, GE // ConditionalCompareImmedOp -- __ ccmnw(r2, 14, 4, Assembler::CC); // ccmn w2, #14, #4, CC -- __ ccmpw(r17, 17, 6, Assembler::PL); // ccmp w17, #17, #6, PL -- __ ccmn(r10, 12, 0, Assembler::CS); // ccmn x10, #12, #0, CS -- __ ccmp(r21, 18, 14, Assembler::GE); // ccmp x21, #18, #14, GE -+ __ ccmnw(r6, 18, 2, Assembler::LE); // ccmn w6, #18, #2, LE -+ __ ccmpw(r9, 13, 4, Assembler::HI); // ccmp w9, #13, #4, HI -+ __ ccmn(r21, 11, 11, Assembler::LO); // ccmn x21, #11, #11, LO -+ __ ccmp(r4, 13, 2, Assembler::VC); // ccmp x4, #13, #2, VC +- __ ccmnw(r9, 2, 4, Assembler::VS); // ccmn w9, #2, #4, VS +- __ ccmpw(r2, 27, 7, Assembler::EQ); // ccmp w2, #27, #7, EQ +- __ ccmn(r16, 1, 2, Assembler::CC); // ccmn x16, #1, #2, CC +- __ ccmp(r17, 31, 3, Assembler::LT); // ccmp x17, #31, #3, LT ++ __ ccmnw(r17, 25, 6, Assembler::EQ); // ccmn w17, #25, #6, EQ ++ __ ccmpw(r2, 5, 5, Assembler::EQ); // ccmp w2, #5, #5, EQ ++ __ ccmn(r19, 17, 10, Assembler::MI); // ccmn x19, #17, #10, MI ++ __ ccmp(r14, 8, 3, Assembler::GT); // ccmp x14, #8, #3, GT // ConditionalSelectOp -- __ cselw(r21, r13, r12, Assembler::GT); // csel w21, w13, w12, GT -- __ csincw(r10, r27, r15, Assembler::LS); // csinc w10, w27, w15, LS -- __ csinvw(r0, r13, r9, Assembler::HI); // csinv w0, w13, w9, HI -- __ csnegw(r18, r4, r26, Assembler::VS); // csneg w18, w4, w26, VS -- __ csel(r12, r29, r7, Assembler::LS); // csel x12, x29, x7, LS -- __ csinc(r6, r7, r20, Assembler::VC); // csinc x6, x7, x20, VC -- __ csinv(r22, r21, r3, Assembler::LE); // csinv x22, x21, x3, LE -- __ csneg(r19, r12, r27, Assembler::LS); // csneg x19, x12, x27, LS -+ __ cselw(r12, r2, r22, Assembler::HI); // csel w12, w2, w22, HI -+ __ csincw(r24, r16, r17, Assembler::HS); // csinc w24, w16, w17, HS -+ __ csinvw(r6, r7, r16, Assembler::LT); // csinv w6, w7, w16, LT -+ __ csnegw(r11, r27, r22, Assembler::LS); // csneg w11, w27, w22, LS -+ __ csel(r10, r3, r29, Assembler::LT); // csel x10, x3, x29, LT -+ __ csinc(r12, r26, r27, Assembler::CC); // csinc x12, x26, x27, CC -+ __ csinv(r15, r10, r21, Assembler::GT); // csinv x15, x10, x21, GT -+ __ csneg(r30, r23, r9, Assembler::GT); // csneg x30, x23, x9, GT +- __ cselw(r23, r27, r23, Assembler::LS); // csel w23, w27, w23, LS +- __ csincw(r10, r0, r6, Assembler::VS); // csinc w10, w0, w6, VS +- __ csinvw(r11, r0, r9, Assembler::CC); // csinv w11, w0, w9, CC +- __ csnegw(r17, r27, r18, Assembler::LO); // csneg w17, w27, w18, LO +- __ csel(r12, r16, r11, Assembler::VC); // csel x12, x16, x11, VC +- __ csinc(r6, r28, r6, Assembler::HI); // csinc x6, x28, x6, HI +- __ csinv(r13, r27, r26, Assembler::VC); // csinv x13, x27, x26, VC +- __ csneg(r29, r22, r18, Assembler::PL); // csneg x29, x22, x18, PL ++ __ cselw(r9, r8, r14, Assembler::LS); // csel w9, w8, w14, LS ++ __ csincw(r27, r11, r5, Assembler::LE); // csinc w27, w11, w5, LE ++ __ csinvw(r11, r23, r22, Assembler::LO); // csinv w11, w23, w22, LO ++ __ csnegw(r19, r28, r27, Assembler::CS); // csneg w19, w28, w27, CS ++ __ csel(r16, r9, r1, Assembler::PL); // csel x16, x9, x1, PL ++ __ csinc(r28, r14, r12, Assembler::EQ); // csinc x28, x14, x12, EQ ++ __ csinv(r22, r4, r14, Assembler::PL); // csinv x22, x4, x14, PL ++ __ csneg(r26, r11, r27, Assembler::HS); // csneg x26, x11, x27, HS // TwoRegOp -- __ rbitw(r0, r16); // rbit w0, w16 -- __ rev16w(r17, r23); // rev16 w17, w23 -- __ revw(r17, r14); // rev w17, w14 -- __ clzw(r24, r30); // clz w24, w30 -- __ clsw(r24, r22); // cls w24, w22 -- __ rbit(r3, r17); // rbit x3, x17 -- __ rev16(r12, r13); // rev16 x12, x13 -- __ rev32(r9, r22); // rev32 x9, x22 -- __ rev(r0, r0); // rev x0, x0 -- __ clz(r5, r16); // clz x5, x16 -- __ cls(r25, r22); // cls x25, x22 -+ __ rbitw(r30, r10); // rbit w30, w10 -+ __ rev16w(r29, r15); // rev16 w29, w15 -+ __ revw(r29, r30); // rev w29, w30 -+ __ clzw(r25, r21); // clz w25, w21 -+ __ clsw(r4, r0); // cls w4, w0 -+ __ rbit(r18, r21); // rbit x18, x21 -+ __ rev16(r29, r16); // rev16 x29, x16 -+ __ rev32(r21, r20); // rev32 x21, x20 -+ __ rev(r6, r19); // rev x6, x19 -+ __ clz(r30, r3); // clz x30, x3 -+ __ cls(r21, r19); // cls x21, x19 +- __ rbitw(r12, r19); // rbit w12, w19 +- __ rev16w(r23, r18); // rev16 w23, w18 +- __ revw(r9, r28); // rev w9, w28 +- __ clzw(r2, r19); // clz w2, w19 +- __ clsw(r25, r29); // cls w25, w29 +- __ rbit(r4, r23); // rbit x4, x23 +- __ rev16(r29, r18); // rev16 x29, x18 +- __ rev32(r7, r8); // rev32 x7, x8 +- __ rev(r13, r17); // rev x13, x17 +- __ clz(r17, r0); // clz x17, x0 +- __ cls(r18, r26); // cls x18, x26 ++ __ rbitw(r24, r11); // rbit w24, w11 ++ __ rev16w(r10, r14); // rev16 w10, w14 ++ __ revw(r9, r5); // rev w9, w5 ++ __ clzw(r18, r20); // clz w18, w20 ++ __ clsw(r25, r8); // cls w25, w8 ++ __ rbit(r22, r24); // rbit x22, x24 ++ __ rev16(r28, r27); // rev16 x28, x27 ++ __ rev32(r8, r29); // rev32 x8, x29 ++ __ rev(r17, r10); // rev x17, x10 ++ __ clz(r23, r11); // clz x23, x11 ++ __ cls(r26, r14); // cls x26, x14 // ThreeRegOp -- __ udivw(r29, r4, r0); // udiv w29, w4, w0 -- __ sdivw(r0, r29, r29); // sdiv w0, w29, w29 -- __ lslvw(r5, r17, r21); // lslv w5, w17, w21 -- __ lsrvw(r9, r9, r18); // lsrv w9, w9, w18 -- __ asrvw(r1, r27, r8); // asrv w1, w27, w8 -- __ rorvw(r18, r20, r13); // rorv w18, w20, w13 -- __ udiv(r8, r25, r12); // udiv x8, x25, x12 -- __ sdiv(r7, r5, r28); // sdiv x7, x5, x28 -- __ lslv(r5, r17, r27); // lslv x5, x17, x27 -- __ lsrv(r23, r26, r20); // lsrv x23, x26, x20 -- __ asrv(r28, r8, r28); // asrv x28, x8, x28 -- __ rorv(r3, r29, r4); // rorv x3, x29, x4 -+ __ udivw(r11, r24, r0); // udiv w11, w24, w0 -+ __ sdivw(r27, r25, r14); // sdiv w27, w25, w14 -+ __ lslvw(r3, r14, r18); // lslv w3, w14, w18 -+ __ lsrvw(r7, r15, r24); // lsrv w7, w15, w24 -+ __ asrvw(r28, r17, r25); // asrv w28, w17, w25 -+ __ rorvw(r2, r26, r28); // rorv w2, w26, w28 -+ __ udiv(r5, r25, r26); // udiv x5, x25, x26 -+ __ sdiv(r27, r16, r18); // sdiv x27, x16, x18 -+ __ lslv(r6, r21, r12); // lslv x6, x21, x12 -+ __ lsrv(r0, r4, r12); // lsrv x0, x4, x12 -+ __ asrv(r27, r17, r28); // asrv x27, x17, x28 -+ __ rorv(r28, r2, r18); // rorv x28, x2, x18 +- __ udivw(r11, r12, r16); // udiv w11, w12, w16 +- __ sdivw(r4, r9, r7); // sdiv w4, w9, w7 +- __ lslvw(r12, r7, r16); // lslv w12, w7, w16 +- __ lsrvw(r19, r16, r23); // lsrv w19, w16, w23 +- __ asrvw(r7, r4, r6); // asrv w7, w4, w6 +- __ rorvw(r21, r20, r23); // rorv w21, w20, w23 +- __ udiv(r16, r12, r28); // udiv x16, x12, x28 +- __ sdiv(r4, r12, r13); // sdiv x4, x12, x13 +- __ lslv(r9, r13, r7); // lslv x9, x13, x7 +- __ lsrv(r28, r27, r15); // lsrv x28, x27, x15 +- __ asrv(r20, r30, r14); // asrv x20, x30, x14 +- __ rorv(r14, r18, r30); // rorv x14, x18, x30 +- __ umulh(r3, r11, r7); // umulh x3, x11, x7 +- __ smulh(r23, r20, r24); // smulh x23, x20, x24 ++ __ udivw(r21, r4, r28); // udiv w21, w4, w28 ++ __ sdivw(r30, r10, r22); // sdiv w30, w10, w22 ++ __ lslvw(r29, r2, r26); // lslv w29, w2, w26 ++ __ lsrvw(r28, r22, r10); // lsrv w28, w22, w10 ++ __ asrvw(r11, r24, r12); // asrv w11, w24, w12 ++ __ rorvw(r21, r30, r16); // rorv w21, w30, w16 ++ __ udiv(r1, r0, r13); // udiv x1, x0, x13 ++ __ sdiv(r2, r17, r6); // sdiv x2, x17, x6 ++ __ lslv(r10, r24, r21); // lslv x10, x24, x21 ++ __ lsrv(r5, r9, r6); // lsrv x5, x9, x6 ++ __ asrv(r0, r27, r4); // asrv x0, x27, x4 ++ __ rorv(r28, r4, r2); // rorv x28, x4, x2 ++ __ umulh(r1, r30, r7); // umulh x1, x30, x7 ++ __ smulh(r30, r5, r10); // smulh x30, x5, x10 // FourRegMulOp -- __ maddw(r17, r14, r26, r21); // madd w17, w14, w26, w21 -- __ msubw(r1, r30, r11, r11); // msub w1, w30, w11, w11 -- __ madd(r1, r17, r6, r28); // madd x1, x17, x6, x28 -- __ msub(r30, r6, r30, r8); // msub x30, x6, x30, x8 -- __ smaddl(r21, r6, r14, r8); // smaddl x21, w6, w14, x8 -- __ smsubl(r10, r10, r24, r19); // smsubl x10, w10, w24, x19 -- __ umaddl(r20, r18, r14, r24); // umaddl x20, w18, w14, x24 -- __ umsubl(r18, r2, r5, r5); // umsubl x18, w2, w5, x5 -+ __ maddw(r10, r15, r14, r14); // madd w10, w15, w14, w14 -+ __ msubw(r3, r25, r15, r19); // msub w3, w25, w15, w19 -+ __ madd(r14, r5, r16, r4); // madd x14, x5, x16, x4 -+ __ msub(r26, r25, r4, r2); // msub x26, x25, x4, x2 -+ __ smaddl(r2, r12, r29, r17); // smaddl x2, w12, w29, x17 -+ __ smsubl(r8, r7, r3, r4); // smsubl x8, w7, w3, x4 -+ __ umaddl(r25, r4, r26, r25); // umaddl x25, w4, w26, x25 -+ __ umsubl(r4, r17, r0, r26); // umsubl x4, w17, w0, x26 +- __ maddw(r2, r5, r21, r9); // madd w2, w5, w21, w9 +- __ msubw(r24, r24, r4, r8); // msub w24, w24, w4, w8 +- __ madd(r11, r12, r15, r19); // madd x11, x12, x15, x19 +- __ msub(r29, r25, r12, r25); // msub x29, x25, x12, x25 +- __ smaddl(r17, r11, r12, r22); // smaddl x17, w11, w12, x22 +- __ smsubl(r28, r3, r20, r18); // smsubl x28, w3, w20, x18 +- __ umaddl(r7, r4, r28, r26); // umaddl x7, w4, w28, x26 +- __ umsubl(r22, r10, r17, r5); // umsubl x22, w10, w17, x5 ++ __ maddw(r7, r15, r13, r17); // madd w7, w15, w13, w17 ++ __ msubw(r25, r1, r12, r28); // msub w25, w1, w12, w28 ++ __ madd(r2, r11, r30, r9); // madd x2, x11, x30, x9 ++ __ msub(r5, r23, r3, r22); // msub x5, x23, x3, x22 ++ __ smaddl(r25, r10, r9, r4); // smaddl x25, w10, w9, x4 ++ __ smsubl(r5, r8, r7, r18); // smsubl x5, w8, w7, x18 ++ __ umaddl(r24, r5, r26, r25); // umaddl x24, w5, w26, x25 ++ __ umsubl(r14, r1, r26, r28); // umsubl x14, w1, w26, x28 // ThreeRegFloatOp -- __ fmuls(v8, v18, v13); // fmul s8, s18, s13 -- __ fdivs(v2, v14, v28); // fdiv s2, s14, s28 -- __ fadds(v15, v12, v28); // fadd s15, s12, s28 -- __ fsubs(v0, v12, v1); // fsub s0, s12, s1 -- __ fmuls(v15, v29, v4); // fmul s15, s29, s4 -- __ fmuld(v12, v1, v23); // fmul d12, d1, d23 -- __ fdivd(v27, v8, v18); // fdiv d27, d8, d18 -- __ faddd(v23, v20, v11); // fadd d23, d20, d11 -- __ fsubd(v8, v12, v18); // fsub d8, d12, d18 -- __ fmuld(v26, v24, v23); // fmul d26, d24, d23 -+ __ fmuls(v17, v23, v15); // fmul s17, s23, s15 -+ __ fdivs(v21, v28, v17); // fdiv s21, s28, s17 -+ __ fadds(v27, v10, v3); // fadd s27, s10, s3 -+ __ fsubs(v0, v7, v25); // fsub s0, s7, s25 -+ __ fmuls(v9, v6, v15); // fmul s9, s6, s15 -+ __ fmuld(v29, v15, v10); // fmul d29, d15, d10 -+ __ fdivd(v2, v17, v7); // fdiv d2, d17, d7 -+ __ faddd(v11, v11, v23); // fadd d11, d11, d23 -+ __ fsubd(v7, v29, v23); // fsub d7, d29, d23 -+ __ fmuld(v14, v27, v11); // fmul d14, d27, d11 +- __ fmuls(v17, v3, v17); // fmul s17, s3, s17 +- __ fdivs(v11, v17, v6); // fdiv s11, s17, s6 +- __ fadds(v29, v7, v9); // fadd s29, s7, s9 +- __ fsubs(v7, v12, v19); // fsub s7, s12, s19 +- __ fmuls(v0, v23, v3); // fmul s0, s23, s3 +- __ fmuld(v26, v3, v21); // fmul d26, d3, d21 +- __ fdivd(v0, v19, v5); // fdiv d0, d19, d5 +- __ faddd(v0, v26, v9); // fadd d0, d26, d9 +- __ fsubd(v25, v21, v21); // fsub d25, d21, d21 +- __ fmuld(v16, v13, v19); // fmul d16, d13, d19 ++ __ fmuls(v24, v22, v8); // fmul s24, s22, s8 ++ __ fdivs(v16, v3, v6); // fdiv s16, s3, s6 ++ __ fadds(v16, v21, v25); // fadd s16, s21, s25 ++ __ fsubs(v0, v26, v27); // fsub s0, s26, s27 ++ __ fmuls(v24, v3, v17); // fmul s24, s3, s17 ++ __ fmuld(v9, v8, v6); // fmul d9, d8, d6 ++ __ fdivd(v22, v19, v30); // fdiv d22, d19, d30 ++ __ faddd(v14, v17, v3); // fadd d14, d17, d3 ++ __ fsubd(v24, v27, v20); // fsub d24, d27, d20 ++ __ fmuld(v12, v1, v22); // fmul d12, d1, d22 // FourRegFloatOp -- __ fmadds(v21, v23, v13, v25); // fmadd s21, s23, s13, s25 -- __ fmsubs(v22, v10, v1, v14); // fmsub s22, s10, s1, s14 -- __ fnmadds(v14, v20, v2, v30); // fnmadd s14, s20, s2, s30 -- __ fnmadds(v7, v29, v22, v22); // fnmadd s7, s29, s22, s22 -- __ fmaddd(v13, v5, v15, v5); // fmadd d13, d5, d15, d5 -- __ fmsubd(v14, v12, v5, v10); // fmsub d14, d12, d5, d10 -- __ fnmaddd(v10, v19, v0, v1); // fnmadd d10, d19, d0, d1 -- __ fnmaddd(v20, v2, v2, v0); // fnmadd d20, d2, d2, d0 -+ __ fmadds(v11, v4, v24, v12); // fmadd s11, s4, s24, s12 -+ __ fmsubs(v15, v14, v20, v11); // fmsub s15, s14, s20, s11 -+ __ fnmadds(v28, v13, v11, v12); // fnmadd s28, s13, s11, s12 -+ __ fnmadds(v23, v30, v26, v14); // fnmadd s23, s30, s26, s14 -+ __ fmaddd(v9, v13, v10, v7); // fmadd d9, d13, d10, d7 -+ __ fmsubd(v5, v29, v15, v3); // fmsub d5, d29, d15, d3 -+ __ fnmaddd(v11, v12, v15, v30); // fnmadd d11, d12, d15, d30 -+ __ fnmaddd(v30, v17, v19, v20); // fnmadd d30, d17, d19, d20 +- __ fmadds(v29, v18, v0, v16); // fmadd s29, s18, s0, s16 +- __ fmsubs(v23, v13, v29, v5); // fmsub s23, s13, s29, s5 +- __ fnmadds(v9, v7, v10, v14); // fnmadd s9, s7, s10, s14 +- __ fnmadds(v25, v28, v15, v23); // fnmadd s25, s28, s15, s23 +- __ fmaddd(v6, v13, v21, v17); // fmadd d6, d13, d21, d17 +- __ fmsubd(v3, v21, v2, v7); // fmsub d3, d21, d2, d7 +- __ fnmaddd(v10, v25, v5, v17); // fnmadd d10, d25, d5, d17 +- __ fnmaddd(v14, v14, v20, v18); // fnmadd d14, d14, d20, d18 ++ __ fmadds(v16, v8, v11, v29); // fmadd s16, s8, s11, s29 ++ __ fmsubs(v22, v19, v18, v1); // fmsub s22, s19, s18, s1 ++ __ fnmadds(v15, v24, v24, v9); // fnmadd s15, s24, s24, s9 ++ __ fnmadds(v27, v19, v13, v23); // fnmadd s27, s19, s13, s23 ++ __ fmaddd(v3, v0, v16, v12); // fmadd d3, d0, d16, d12 ++ __ fmsubd(v19, v3, v18, v10); // fmsub d19, d3, d18, d10 ++ __ fnmaddd(v1, v2, v11, v20); // fnmadd d1, d2, d11, d20 ++ __ fnmaddd(v12, v9, v25, v14); // fnmadd d12, d9, d25, d14 // TwoRegFloatOp -- __ fmovs(v25, v9); // fmov s25, s9 -- __ fabss(v20, v4); // fabs s20, s4 -- __ fnegs(v3, v27); // fneg s3, s27 -- __ fsqrts(v1, v2); // fsqrt s1, s2 -- __ fcvts(v30, v0); // fcvt d30, s0 -- __ fmovd(v12, v4); // fmov d12, d4 -- __ fabsd(v1, v27); // fabs d1, d27 -- __ fnegd(v8, v22); // fneg d8, d22 -- __ fsqrtd(v11, v11); // fsqrt d11, d11 -- __ fcvtd(v22, v28); // fcvt s22, d28 -+ __ fmovs(v27, v7); // fmov s27, s7 -+ __ fabss(v9, v21); // fabs s9, s21 -+ __ fnegs(v2, v9); // fneg s2, s9 -+ __ fsqrts(v27, v7); // fsqrt s27, s7 -+ __ fcvts(v29, v30); // fcvt d29, s30 -+ __ fmovd(v17, v1); // fmov d17, d1 -+ __ fabsd(v2, v6); // fabs d2, d6 -+ __ fnegd(v10, v3); // fneg d10, d3 -+ __ fsqrtd(v24, v11); // fsqrt d24, d11 -+ __ fcvtd(v7, v1); // fcvt s7, d1 +- __ fmovs(v15, v2); // fmov s15, s2 +- __ fabss(v18, v7); // fabs s18, s7 +- __ fnegs(v3, v6); // fneg s3, s6 +- __ fsqrts(v12, v1); // fsqrt s12, s1 +- __ fcvts(v9, v0); // fcvt d9, s0 +- __ fmovd(v4, v5); // fmov d4, d5 +- __ fabsd(v3, v15); // fabs d3, d15 +- __ fnegd(v17, v25); // fneg d17, d25 +- __ fsqrtd(v12, v24); // fsqrt d12, d24 +- __ fcvtd(v21, v5); // fcvt s21, d5 ++ __ fmovs(v0, v23); // fmov s0, s23 ++ __ fabss(v23, v6); // fabs s23, s6 ++ __ fnegs(v4, v4); // fneg s4, s4 ++ __ fsqrts(v5, v28); // fsqrt s5, s28 ++ __ fcvts(v21, v15); // fcvt d21, s15 ++ __ fmovd(v11, v5); // fmov d11, d5 ++ __ fabsd(v18, v4); // fabs d18, d4 ++ __ fnegd(v11, v12); // fneg d11, d12 ++ __ fsqrtd(v15, v8); // fsqrt d15, d8 ++ __ fcvtd(v8, v2); // fcvt s8, d2 // FloatConvertOp -- __ fcvtzsw(r28, v22); // fcvtzs w28, s22 -- __ fcvtzs(r20, v27); // fcvtzs x20, s27 -- __ fcvtzdw(r14, v0); // fcvtzs w14, d0 -- __ fcvtzd(r26, v11); // fcvtzs x26, d11 -- __ scvtfws(v28, r22); // scvtf s28, w22 -- __ scvtfs(v16, r10); // scvtf s16, x10 -- __ scvtfwd(v8, r21); // scvtf d8, w21 -- __ scvtfd(v21, r28); // scvtf d21, x28 -- __ fmovs(r24, v24); // fmov w24, s24 -- __ fmovd(r8, v19); // fmov x8, d19 -- __ fmovs(v8, r12); // fmov s8, w12 -- __ fmovd(v6, r7); // fmov d6, x7 -+ __ fcvtzsw(r11, v0); // fcvtzs w11, s0 -+ __ fcvtzs(r3, v18); // fcvtzs x3, s18 -+ __ fcvtzdw(r28, v6); // fcvtzs w28, d6 -+ __ fcvtzd(r22, v6); // fcvtzs x22, d6 -+ __ scvtfws(v0, r27); // scvtf s0, w27 -+ __ scvtfs(v26, r2); // scvtf s26, x2 -+ __ scvtfwd(v5, r7); // scvtf d5, w7 -+ __ scvtfd(v28, r11); // scvtf d28, x11 -+ __ fmovs(r25, v13); // fmov w25, s13 -+ __ fmovd(r11, v23); // fmov x11, d23 -+ __ fmovs(v19, r8); // fmov s19, w8 -+ __ fmovd(v18, r21); // fmov d18, x21 +- __ fcvtzsw(r4, v21); // fcvtzs w4, s21 +- __ fcvtzs(r27, v3); // fcvtzs x27, s3 +- __ fcvtzdw(r29, v8); // fcvtzs w29, d8 +- __ fcvtzd(r9, v21); // fcvtzs x9, d21 +- __ scvtfws(v20, r29); // scvtf s20, w29 +- __ scvtfs(v7, r8); // scvtf s7, x8 +- __ scvtfwd(v12, r21); // scvtf d12, w21 +- __ scvtfd(v16, r21); // scvtf d16, x21 +- __ fmovs(r18, v5); // fmov w18, s5 +- __ fmovd(r25, v8); // fmov x25, d8 +- __ fmovs(v18, r26); // fmov s18, w26 +- __ fmovd(v0, r11); // fmov d0, x11 ++ __ fcvtzsw(r19, v18); // fcvtzs w19, s18 ++ __ fcvtzs(r17, v0); // fcvtzs x17, s0 ++ __ fcvtzdw(r0, v13); // fcvtzs w0, d13 ++ __ fcvtzd(r22, v9); // fcvtzs x22, d9 ++ __ scvtfws(v6, r29); // scvtf s6, w29 ++ __ scvtfs(v12, r14); // scvtf s12, x14 ++ __ scvtfwd(v16, r22); // scvtf d16, w22 ++ __ scvtfd(v14, r5); // scvtf d14, x5 ++ __ fmovs(r7, v0); // fmov w7, s0 ++ __ fmovd(r28, v6); // fmov x28, d6 ++ __ fmovs(v2, r26); // fmov s2, w26 ++ __ fmovd(v4, r0); // fmov d4, x0 // TwoRegFloatOp -- __ fcmps(v30, v16); // fcmp s30, s16 -- __ fcmpd(v25, v11); // fcmp d25, d11 -- __ fcmps(v11, 0.0); // fcmp s11, #0.0 -- __ fcmpd(v11, 0.0); // fcmp d11, #0.0 -+ __ fcmps(v25, v20); // fcmp s25, s20 -+ __ fcmpd(v19, v18); // fcmp d19, d18 -+ __ fcmps(v2, 0.0); // fcmp s2, #0.0 -+ __ fcmpd(v29, 0.0); // fcmp d29, #0.0 +- __ fcmps(v16, v6); // fcmp s16, s6 +- __ fcmpd(v16, v29); // fcmp d16, d29 +- __ fcmps(v30, 0.0); // fcmp s30, #0.0 +- __ fcmpd(v9, 0.0); // fcmp d9, #0.0 ++ __ fcmps(v1, v11); // fcmp s1, s11 ++ __ fcmpd(v6, v21); // fcmp d6, d21 ++ __ fcmps(v16, 0.0); // fcmp s16, #0.0 ++ __ fcmpd(v22, 0.0); // fcmp d22, #0.0 // LoadStorePairOp -- __ stpw(r29, r12, Address(r17, 128)); // stp w29, w12, [x17, #128] -- __ ldpw(r22, r18, Address(r14, -96)); // ldp w22, w18, [x14, #-96] -- __ ldpsw(r11, r16, Address(r1, 64)); // ldpsw x11, x16, [x1, #64] -- __ stp(r0, r11, Address(r26, 112)); // stp x0, x11, [x26, #112] -- __ ldp(r7, r1, Address(r26, 16)); // ldp x7, x1, [x26, #16] -+ __ stpw(r8, r21, Address(r19, 16)); // stp w8, w21, [x19, #16] -+ __ ldpw(r6, r15, Address(r20, 0)); // ldp w6, w15, [x20, #0] -+ __ ldpsw(r27, r14, Address(r3, -208)); // ldpsw x27, x14, [x3, #-208] -+ __ stp(r10, r12, Address(r11, -80)); // stp x10, x12, [x11, #-80] -+ __ ldp(r7, r14, Address(r7, -32)); // ldp x7, x14, [x7, #-32] +- __ stpw(r27, r4, Address(r12, -16)); // stp w27, w4, [x12, #-16] +- __ ldpw(r3, r9, Address(r10, 80)); // ldp w3, w9, [x10, #80] +- __ ldpsw(r16, r3, Address(r3, 64)); // ldpsw x16, x3, [x3, #64] +- __ stp(r10, r28, Address(r19, -192)); // stp x10, x28, [x19, #-192] +- __ ldp(r19, r18, Address(r7, -192)); // ldp x19, x18, [x7, #-192] ++ __ stpw(r5, r0, Address(r2, 96)); // stp w5, w0, [x2, #96] ++ __ ldpw(r14, r29, Address(r19, -64)); // ldp w14, w29, [x19, #-64] ++ __ ldpsw(r15, r3, Address(r3, -160)); // ldpsw x15, x3, [x3, #-160] ++ __ stp(r7, r13, Address(r27, -224)); // stp x7, x13, [x27, #-224] ++ __ ldp(r17, r14, Address(r1, 128)); // ldp x17, x14, [x1, #128] // LoadStorePairOp -- __ stpw(r10, r7, Address(__ pre(r24, 0))); // stp w10, w7, [x24, #0]! -- __ ldpw(r7, r28, Address(__ pre(r24, -256))); // ldp w7, w28, [x24, #-256]! -- __ ldpsw(r25, r28, Address(__ pre(r21, -240))); // ldpsw x25, x28, [x21, #-240]! -- __ stp(r20, r18, Address(__ pre(r14, -16))); // stp x20, x18, [x14, #-16]! -- __ ldp(r8, r10, Address(__ pre(r13, 80))); // ldp x8, x10, [x13, #80]! -+ __ stpw(r0, r22, Address(__ pre(r12, 112))); // stp w0, w22, [x12, #112]! -+ __ ldpw(r14, r7, Address(__ pre(r8, 48))); // ldp w14, w7, [x8, #48]! -+ __ ldpsw(r16, r2, Address(__ pre(r9, 0))); // ldpsw x16, x2, [x9, #0]! -+ __ stp(r20, r29, Address(__ pre(r1, -64))); // stp x20, x29, [x1, #-64]! -+ __ ldp(r21, r12, Address(__ pre(r5, 80))); // ldp x21, x12, [x5, #80]! +- __ stpw(r10, r16, Address(__ pre(r30, 16))); // stp w10, w16, [x30, #16]! +- __ ldpw(r2, r4, Address(__ pre(r18, -240))); // ldp w2, w4, [x18, #-240]! +- __ ldpsw(r24, r19, Address(__ pre(r13, 48))); // ldpsw x24, x19, [x13, #48]! +- __ stp(r17, r0, Address(__ pre(r24, 0))); // stp x17, x0, [x24, #0]! +- __ ldp(r14, r26, Address(__ pre(r3, -192))); // ldp x14, x26, [x3, #-192]! ++ __ stpw(r21, r22, Address(__ pre(r4, 128))); // stp w21, w22, [x4, #128]! ++ __ ldpw(r17, r13, Address(__ pre(r2, -96))); // ldp w17, w13, [x2, #-96]! ++ __ ldpsw(r21, r25, Address(__ pre(r23, -144))); // ldpsw x21, x25, [x23, #-144]! ++ __ stp(r4, r16, Address(__ pre(r15, -16))); // stp x4, x16, [x15, #-16]! ++ __ ldp(r29, r21, Address(__ pre(r25, -160))); // ldp x29, x21, [x25, #-160]! // LoadStorePairOp -- __ stpw(r26, r24, Address(__ post(r2, -128))); // stp w26, w24, [x2], #-128 -- __ ldpw(r2, r25, Address(__ post(r21, -192))); // ldp w2, w25, [x21], #-192 -- __ ldpsw(r17, r2, Address(__ post(r21, -144))); // ldpsw x17, x2, [x21], #-144 -- __ stp(r12, r10, Address(__ post(r11, 96))); // stp x12, x10, [x11], #96 -- __ ldp(r24, r6, Address(__ post(r17, -32))); // ldp x24, x6, [x17], #-32 -+ __ stpw(r24, r24, Address(__ post(r27, -112))); // stp w24, w24, [x27], #-112 -+ __ ldpw(r28, r22, Address(__ post(r18, 16))); // ldp w28, w22, [x18], #16 -+ __ ldpsw(r17, r6, Address(__ post(r13, -96))); // ldpsw x17, x6, [x13], #-96 -+ __ stp(r28, r26, Address(__ post(r5, -160))); // stp x28, x26, [x5], #-160 -+ __ ldp(r6, r21, Address(__ post(r26, -240))); // ldp x6, x21, [x26], #-240 +- __ stpw(r22, r1, Address(__ post(r0, 80))); // stp w22, w1, [x0], #80 +- __ ldpw(r18, r10, Address(__ post(r0, -16))); // ldp w18, w10, [x0], #-16 +- __ ldpsw(r24, r24, Address(__ post(r22, -16))); // ldpsw x24, x24, [x22], #-16 +- __ stp(r12, r12, Address(__ post(r4, 80))); // stp x12, x12, [x4], #80 +- __ ldp(r4, r9, Address(__ post(r19, -240))); // ldp x4, x9, [x19], #-240 ++ __ stpw(r24, r17, Address(__ post(r26, 80))); // stp w24, w17, [x26], #80 ++ __ ldpw(r3, r30, Address(__ post(r30, -240))); // ldp w3, w30, [x30], #-240 ++ __ ldpsw(r3, r19, Address(__ post(r30, -32))); // ldpsw x3, x19, [x30], #-32 ++ __ stp(r25, r1, Address(__ post(r27, -144))); // stp x25, x1, [x27], #-144 ++ __ ldp(r26, r20, Address(__ post(r28, -64))); // ldp x26, x20, [x28], #-64 // LoadStorePairOp -- __ stnpw(r3, r30, Address(r14, -224)); // stnp w3, w30, [x14, #-224] -- __ ldnpw(r15, r20, Address(r26, -144)); // ldnp w15, w20, [x26, #-144] -- __ stnp(r22, r25, Address(r12, -128)); // stnp x22, x25, [x12, #-128] -- __ ldnp(r27, r22, Address(r17, -176)); // ldnp x27, x22, [x17, #-176] -+ __ stnpw(r13, r20, Address(r30, 32)); // stnp w13, w20, [x30, #32] -+ __ ldnpw(r17, r11, Address(r5, 96)); // ldnp w17, w11, [x5, #96] -+ __ stnp(r13, r20, Address(r26, -96)); // stnp x13, x20, [x26, #-96] -+ __ ldnp(r29, r12, Address(r23, -80)); // ldnp x29, x12, [x23, #-80] -+ -+// SpecialCases -+ __ sve_cpy(z0, __ S, p0, v1); // mov z0.s, p0/m, s1 -+ __ sve_inc(r0, __ S); // incw x0 -+ __ sve_dec(r1, __ H); // dech x1 -+ __ sve_lsl(z0, __ B, z1, 7); // lsl z0.b, z1.b, #7 -+ __ sve_lsl(z21, __ H, z1, 15); // lsl z21.h, z1.h, #15 -+ __ sve_lsl(z0, __ S, z1, 31); // lsl z0.s, z1.s, #31 -+ __ sve_lsl(z0, __ D, z1, 63); // lsl z0.d, z1.d, #63 -+ __ sve_lsr(z0, __ B, z1, 7); // lsr z0.b, z1.b, #7 -+ __ sve_asr(z0, __ H, z11, 15); // asr z0.h, z11.h, #15 -+ __ sve_lsr(z30, __ S, z1, 31); // lsr z30.s, z1.s, #31 -+ __ sve_asr(z0, __ D, z1, 63); // asr z0.d, z1.d, #63 -+ __ sve_addvl(sp, r0, 31); // addvl sp, x0, #31 -+ __ sve_addpl(r1, sp, -32); // addpl x1, sp, -32 -+ __ sve_cntp(r8, __ B, p0, p1); // cntp x8, p0, p1.b -+ __ sve_dup(z0, __ B, 127); // dup z0.b, 127 -+ __ sve_dup(z1, __ H, -128); // dup z1.h, -128 -+ __ sve_dup(z2, __ S, 32512); // dup z2.s, 32512 -+ __ sve_dup(z7, __ D, -32768); // dup z7.d, -32768 -+ __ sve_ld1b(z0, __ B, p0, Address(sp)); // ld1b {z0.b}, p0/z, [sp] -+ __ sve_ld1h(z10, __ H, p1, Address(sp, -8)); // ld1h {z10.h}, p1/z, [sp, #-8, MUL VL] -+ __ sve_ld1w(z20, __ S, p2, Address(r0, 7)); // ld1w {z20.s}, p2/z, [x0, #7, MUL VL] -+ __ sve_ld1b(z30, __ B, p3, Address(sp, r8)); // ld1b {z30.b}, p3/z, [sp, x8] -+ __ sve_ld1w(z0, __ S, p4, Address(sp, r28)); // ld1w {z0.s}, p4/z, [sp, x28, LSL #2] -+ __ sve_ld1d(z11, __ D, p5, Address(r0, r1)); // ld1d {z11.d}, p5/z, [x0, x1, LSL #3] -+ __ sve_st1b(z22, __ B, p6, Address(sp)); // st1b {z22.b}, p6, [sp] -+ __ sve_st1b(z31, __ B, p7, Address(sp, -8)); // st1b {z31.b}, p7, [sp, #-8, MUL VL] -+ __ sve_st1w(z0, __ S, p1, Address(r0, 7)); // st1w {z0.s}, p1, [x0, #7, MUL VL] -+ __ sve_st1b(z0, __ B, p2, Address(sp, r1)); // st1b {z0.b}, p2, [sp, x1] -+ __ sve_st1h(z0, __ H, p3, Address(sp, r8)); // st1h {z0.h}, p3, [sp, x8, LSL #1] -+ __ sve_st1d(z0, __ D, p4, Address(r0, r18)); // st1d {z0.d}, p4, [x0, x18, LSL #3] -+ __ sve_ldr(z0, Address(sp)); // ldr z0, [sp] -+ __ sve_ldr(z31, Address(sp, -256)); // ldr z31, [sp, #-256, MUL VL] -+ __ sve_str(z8, Address(r8, 255)); // str z8, [x8, #255, MUL VL] +- __ stnpw(r18, r26, Address(r6, -224)); // stnp w18, w26, [x6, #-224] +- __ ldnpw(r21, r20, Address(r1, 112)); // ldnp w21, w20, [x1, #112] +- __ stnp(r25, r29, Address(r20, -224)); // stnp x25, x29, [x20, #-224] +- __ ldnp(r1, r5, Address(r23, 112)); // ldnp x1, x5, [x23, #112] ++ __ stnpw(r29, r25, Address(r9, -48)); // stnp w29, w25, [x9, #-48] ++ __ ldnpw(r25, r14, Address(r19, -128)); // ldnp w25, w14, [x19, #-128] ++ __ stnp(r25, r22, Address(r3, 32)); // stnp x25, x22, [x3, #32] ++ __ ldnp(r9, r18, Address(r29, -208)); // ldnp x9, x18, [x29, #-208] + + // LdStSIMDOp +- __ ld1(v4, __ T8B, Address(r20)); // ld1 {v4.8B}, [x20] +- __ ld1(v24, v25, __ T16B, Address(__ post(r10, 32))); // ld1 {v24.16B, v25.16B}, [x10], 32 +- __ ld1(v24, v25, v26, __ T1D, Address(__ post(r6, r15))); // ld1 {v24.1D, v25.1D, v26.1D}, [x6], x15 +- __ ld1(v3, v4, v5, v6, __ T8H, Address(__ post(r4, 64))); // ld1 {v3.8H, v4.8H, v5.8H, v6.8H}, [x4], 64 +- __ ld1r(v2, __ T8B, Address(r6)); // ld1r {v2.8B}, [x6] +- __ ld1r(v13, __ T4S, Address(__ post(r14, 4))); // ld1r {v13.4S}, [x14], 4 +- __ ld1r(v15, __ T1D, Address(__ post(r21, r24))); // ld1r {v15.1D}, [x21], x24 +- __ ld2(v9, v10, __ T2D, Address(r21)); // ld2 {v9.2D, v10.2D}, [x21] +- __ ld2(v29, v30, __ T4H, Address(__ post(r21, 16))); // ld2 {v29.4H, v30.4H}, [x21], 16 +- __ ld2r(v8, v9, __ T16B, Address(r14)); // ld2r {v8.16B, v9.16B}, [x14] +- __ ld2r(v7, v8, __ T2S, Address(__ post(r20, 8))); // ld2r {v7.2S, v8.2S}, [x20], 8 +- __ ld2r(v28, v29, __ T2D, Address(__ post(r3, r3))); // ld2r {v28.2D, v29.2D}, [x3], x3 +- __ ld3(v27, v28, v29, __ T4S, Address(__ post(r11, r29))); // ld3 {v27.4S, v28.4S, v29.4S}, [x11], x29 +- __ ld3(v16, v17, v18, __ T2S, Address(r10)); // ld3 {v16.2S, v17.2S, v18.2S}, [x10] +- __ ld3r(v21, v22, v23, __ T8H, Address(r12)); // ld3r {v21.8H, v22.8H, v23.8H}, [x12] +- __ ld3r(v4, v5, v6, __ T4S, Address(__ post(r29, 12))); // ld3r {v4.4S, v5.4S, v6.4S}, [x29], 12 +- __ ld3r(v24, v25, v26, __ T1D, Address(__ post(r9, r19))); // ld3r {v24.1D, v25.1D, v26.1D}, [x9], x19 +- __ ld4(v10, v11, v12, v13, __ T8H, Address(__ post(r3, 64))); // ld4 {v10.8H, v11.8H, v12.8H, v13.8H}, [x3], 64 +- __ ld4(v27, v28, v29, v30, __ T8B, Address(__ post(r28, r9))); // ld4 {v27.8B, v28.8B, v29.8B, v30.8B}, [x28], x9 +- __ ld4r(v21, v22, v23, v24, __ T8B, Address(r30)); // ld4r {v21.8B, v22.8B, v23.8B, v24.8B}, [x30] +- __ ld4r(v23, v24, v25, v26, __ T4H, Address(__ post(r14, 8))); // ld4r {v23.4H, v24.4H, v25.4H, v26.4H}, [x14], 8 +- __ ld4r(v4, v5, v6, v7, __ T2S, Address(__ post(r13, r20))); // ld4r {v4.2S, v5.2S, v6.2S, v7.2S}, [x13], x20 ++ __ ld1(v21, __ T8B, Address(r19)); // ld1 {v21.8B}, [x19] ++ __ ld1(v27, v28, __ T16B, Address(__ post(r20, 32))); // ld1 {v27.16B, v28.16B}, [x20], 32 ++ __ ld1(v5, v6, v7, __ T1D, Address(__ post(r22, r6))); // ld1 {v5.1D, v6.1D, v7.1D}, [x22], x6 ++ __ ld1(v22, v23, v24, v25, __ T8H, Address(__ post(r12, 64))); // ld1 {v22.8H, v23.8H, v24.8H, v25.8H}, [x12], 64 ++ __ ld1r(v17, __ T8B, Address(r9)); // ld1r {v17.8B}, [x9] ++ __ ld1r(v5, __ T4S, Address(__ post(r21, 4))); // ld1r {v5.4S}, [x21], 4 ++ __ ld1r(v10, __ T1D, Address(__ post(r28, r18))); // ld1r {v10.1D}, [x28], x18 ++ __ ld2(v26, v27, __ T2D, Address(r15)); // ld2 {v26.2D, v27.2D}, [x15] ++ __ ld2(v16, v17, __ T4H, Address(__ post(r26, 16))); // ld2 {v16.4H, v17.4H}, [x26], 16 ++ __ ld2r(v14, v15, __ T16B, Address(r2)); // ld2r {v14.16B, v15.16B}, [x2] ++ __ ld2r(v18, v19, __ T2S, Address(__ post(r28, 8))); // ld2r {v18.2S, v19.2S}, [x28], 8 ++ __ ld2r(v19, v20, __ T2D, Address(__ post(r0, r22))); // ld2r {v19.2D, v20.2D}, [x0], x22 ++ __ ld3(v16, v17, v18, __ T4S, Address(__ post(r2, r18))); // ld3 {v16.4S, v17.4S, v18.4S}, [x2], x18 ++ __ ld3(v24, v25, v26, __ T2S, Address(r0)); // ld3 {v24.2S, v25.2S, v26.2S}, [x0] ++ __ ld3r(v4, v5, v6, __ T8H, Address(r16)); // ld3r {v4.8H, v5.8H, v6.8H}, [x16] ++ __ ld3r(v5, v6, v7, __ T4S, Address(__ post(r1, 12))); // ld3r {v5.4S, v6.4S, v7.4S}, [x1], 12 ++ __ ld3r(v7, v8, v9, __ T1D, Address(__ post(r10, r16))); // ld3r {v7.1D, v8.1D, v9.1D}, [x10], x16 ++ __ ld4(v22, v23, v24, v25, __ T8H, Address(__ post(r20, 64))); // ld4 {v22.8H, v23.8H, v24.8H, v25.8H}, [x20], 64 ++ __ ld4(v15, v16, v17, v18, __ T8B, Address(__ post(r4, r25))); // ld4 {v15.8B, v16.8B, v17.8B, v18.8B}, [x4], x25 ++ __ ld4r(v0, v1, v2, v3, __ T8B, Address(r5)); // ld4r {v0.8B, v1.8B, v2.8B, v3.8B}, [x5] ++ __ ld4r(v0, v1, v2, v3, __ T4H, Address(__ post(r1, 8))); // ld4r {v0.4H, v1.4H, v2.4H, v3.4H}, [x1], 8 ++ __ ld4r(v30, v31, v0, v1, __ T2S, Address(__ post(r28, r14))); // ld4r {v30.2S, v31.2S, v0.2S, v1.2S}, [x28], x14 + + // SpecialCases +- __ ccmn(zr, zr, 3u, Assembler::LE); // ccmn xzr, xzr, #3, LE +- __ ccmnw(zr, zr, 5u, Assembler::EQ); // ccmn wzr, wzr, #5, EQ +- __ ccmp(zr, 1, 4u, Assembler::NE); // ccmp xzr, 1, #4, NE +- __ ccmpw(zr, 2, 2, Assembler::GT); // ccmp wzr, 2, #2, GT +- __ extr(zr, zr, zr, 0); // extr xzr, xzr, xzr, 0 +- __ stlxp(r0, zr, zr, sp); // stlxp w0, xzr, xzr, [sp] +- __ stlxpw(r2, zr, zr, r3); // stlxp w2, wzr, wzr, [x3] +- __ stxp(r4, zr, zr, r5); // stxp w4, xzr, xzr, [x5] +- __ stxpw(r6, zr, zr, sp); // stxp w6, wzr, wzr, [sp] +- __ dup(v0, __ T16B, zr); // dup v0.16b, wzr +- __ mov(v1, __ T1D, 0, zr); // mov v1.d[0], xzr +- __ mov(v1, __ T2S, 1, zr); // mov v1.s[1], wzr +- __ mov(v1, __ T4H, 2, zr); // mov v1.h[2], wzr +- __ mov(v1, __ T8B, 3, zr); // mov v1.b[3], wzr +- __ ld1(v31, v0, __ T2D, Address(__ post(r1, r0))); // ld1 {v31.2d, v0.2d}, [x1], x0 ++ __ ccmn(zr, zr, 3u, Assembler::LE); // ccmn xzr, xzr, #3, LE ++ __ ccmnw(zr, zr, 5u, Assembler::EQ); // ccmn wzr, wzr, #5, EQ ++ __ ccmp(zr, 1, 4u, Assembler::NE); // ccmp xzr, 1, #4, NE ++ __ ccmpw(zr, 2, 2, Assembler::GT); // ccmp wzr, 2, #2, GT ++ __ extr(zr, zr, zr, 0); // extr xzr, xzr, xzr, 0 ++ __ stlxp(r0, zr, zr, sp); // stlxp w0, xzr, xzr, [sp] ++ __ stlxpw(r2, zr, zr, r3); // stlxp w2, wzr, wzr, [x3] ++ __ stxp(r4, zr, zr, r5); // stxp w4, xzr, xzr, [x5] ++ __ stxpw(r6, zr, zr, sp); // stxp w6, wzr, wzr, [sp] ++ __ dup(v0, __ T16B, zr); // dup v0.16b, wzr ++ __ mov(v1, __ T1D, 0, zr); // mov v1.d[0], xzr ++ __ mov(v1, __ T2S, 1, zr); // mov v1.s[1], wzr ++ __ mov(v1, __ T4H, 2, zr); // mov v1.h[2], wzr ++ __ mov(v1, __ T8B, 3, zr); // mov v1.b[3], wzr ++ __ ld1(v31, v0, __ T2D, Address(__ post(r1, r0))); // ld1 {v31.2d, v0.2d}, [x1], x0 // FloatImmediateOp -- __ fmovd(v0, 2.0); // fmov d0, #2.0 -- __ fmovd(v0, 2.125); // fmov d0, #2.125 -- __ fmovd(v0, 4.0); // fmov d0, #4.0 -- __ fmovd(v0, 4.25); // fmov d0, #4.25 -- __ fmovd(v0, 8.0); // fmov d0, #8.0 -- __ fmovd(v0, 8.5); // fmov d0, #8.5 -- __ fmovd(v0, 16.0); // fmov d0, #16.0 -- __ fmovd(v0, 17.0); // fmov d0, #17.0 -- __ fmovd(v0, 0.125); // fmov d0, #0.125 -- __ fmovd(v0, 0.1328125); // fmov d0, #0.1328125 -- __ fmovd(v0, 0.25); // fmov d0, #0.25 -- __ fmovd(v0, 0.265625); // fmov d0, #0.265625 -- __ fmovd(v0, 0.5); // fmov d0, #0.5 -- __ fmovd(v0, 0.53125); // fmov d0, #0.53125 -- __ fmovd(v0, 1.0); // fmov d0, #1.0 -- __ fmovd(v0, 1.0625); // fmov d0, #1.0625 -- __ fmovd(v0, -2.0); // fmov d0, #-2.0 -- __ fmovd(v0, -2.125); // fmov d0, #-2.125 -- __ fmovd(v0, -4.0); // fmov d0, #-4.0 -- __ fmovd(v0, -4.25); // fmov d0, #-4.25 -- __ fmovd(v0, -8.0); // fmov d0, #-8.0 -- __ fmovd(v0, -8.5); // fmov d0, #-8.5 -- __ fmovd(v0, -16.0); // fmov d0, #-16.0 -- __ fmovd(v0, -17.0); // fmov d0, #-17.0 -- __ fmovd(v0, -0.125); // fmov d0, #-0.125 -- __ fmovd(v0, -0.1328125); // fmov d0, #-0.1328125 -- __ fmovd(v0, -0.25); // fmov d0, #-0.25 -- __ fmovd(v0, -0.265625); // fmov d0, #-0.265625 -- __ fmovd(v0, -0.5); // fmov d0, #-0.5 -- __ fmovd(v0, -0.53125); // fmov d0, #-0.53125 -- __ fmovd(v0, -1.0); // fmov d0, #-1.0 -- __ fmovd(v0, -1.0625); // fmov d0, #-1.0625 +- __ fmovd(v0, 2.0); // fmov d0, #2.0 +- __ fmovd(v0, 2.125); // fmov d0, #2.125 +- __ fmovd(v0, 4.0); // fmov d0, #4.0 +- __ fmovd(v0, 4.25); // fmov d0, #4.25 +- __ fmovd(v0, 8.0); // fmov d0, #8.0 +- __ fmovd(v0, 8.5); // fmov d0, #8.5 +- __ fmovd(v0, 16.0); // fmov d0, #16.0 +- __ fmovd(v0, 17.0); // fmov d0, #17.0 +- __ fmovd(v0, 0.125); // fmov d0, #0.125 +- __ fmovd(v0, 0.1328125); // fmov d0, #0.1328125 +- __ fmovd(v0, 0.25); // fmov d0, #0.25 +- __ fmovd(v0, 0.265625); // fmov d0, #0.265625 +- __ fmovd(v0, 0.5); // fmov d0, #0.5 +- __ fmovd(v0, 0.53125); // fmov d0, #0.53125 +- __ fmovd(v0, 1.0); // fmov d0, #1.0 +- __ fmovd(v0, 1.0625); // fmov d0, #1.0625 +- __ fmovd(v0, -2.0); // fmov d0, #-2.0 +- __ fmovd(v0, -2.125); // fmov d0, #-2.125 +- __ fmovd(v0, -4.0); // fmov d0, #-4.0 +- __ fmovd(v0, -4.25); // fmov d0, #-4.25 +- __ fmovd(v0, -8.0); // fmov d0, #-8.0 +- __ fmovd(v0, -8.5); // fmov d0, #-8.5 +- __ fmovd(v0, -16.0); // fmov d0, #-16.0 +- __ fmovd(v0, -17.0); // fmov d0, #-17.0 +- __ fmovd(v0, -0.125); // fmov d0, #-0.125 +- __ fmovd(v0, -0.1328125); // fmov d0, #-0.1328125 +- __ fmovd(v0, -0.25); // fmov d0, #-0.25 +- __ fmovd(v0, -0.265625); // fmov d0, #-0.265625 +- __ fmovd(v0, -0.5); // fmov d0, #-0.5 +- __ fmovd(v0, -0.53125); // fmov d0, #-0.53125 +- __ fmovd(v0, -1.0); // fmov d0, #-1.0 +- __ fmovd(v0, -1.0625); // fmov d0, #-1.0625 + __ fmovd(v0, 2.0); // fmov d0, #2.0 + __ fmovd(v0, 2.125); // fmov d0, #2.125 + __ fmovd(v0, 4.0); // fmov d0, #4.0 @@ -4301,1237 +4296,1487 @@ index 586743eb9..441ea4066 100644 + __ fmovd(v0, -0.53125); // fmov d0, #-0.53125 + __ fmovd(v0, -1.0); // fmov d0, #-1.0 + __ fmovd(v0, -1.0625); // fmov d0, #-1.0625 -+ -+// SVEVectorOp -+ __ sve_add(z14, __ S, z16, z27); // add z14.s, z16.s, z27.s -+ __ sve_sub(z0, __ S, z6, z26); // sub z0.s, z6.s, z26.s -+ __ sve_fadd(z27, __ S, z12, z6); // fadd z27.s, z12.s, z6.s -+ __ sve_fmul(z30, __ S, z4, z19); // fmul z30.s, z4.s, z19.s -+ __ sve_fsub(z11, __ D, z16, z2); // fsub z11.d, z16.d, z2.d -+ __ sve_abs(z15, __ D, p0, z12); // abs z15.d, p0/m, z12.d -+ __ sve_add(z9, __ B, p5, z23); // add z9.b, p5/m, z9.b, z23.b -+ __ sve_asr(z30, __ S, p0, z26); // asr z30.s, p0/m, z30.s, z26.s -+ __ sve_cnt(z4, __ H, p2, z18); // cnt z4.h, p2/m, z18.h -+ __ sve_lsl(z25, __ S, p1, z11); // lsl z25.s, p1/m, z25.s, z11.s -+ __ sve_lsr(z10, __ B, p6, z8); // lsr z10.b, p6/m, z10.b, z8.b -+ __ sve_mul(z4, __ B, p5, z17); // mul z4.b, p5/m, z4.b, z17.b -+ __ sve_neg(z30, __ S, p3, z9); // neg z30.s, p3/m, z9.s -+ __ sve_not(z0, __ D, p3, z20); // not z0.d, p3/m, z20.d -+ __ sve_smax(z23, __ H, p7, z3); // smax z23.h, p7/m, z23.h, z3.h -+ __ sve_smin(z0, __ H, p2, z11); // smin z0.h, p2/m, z0.h, z11.h -+ __ sve_sub(z11, __ D, p6, z5); // sub z11.d, p6/m, z11.d, z5.d -+ __ sve_fabs(z16, __ S, p2, z17); // fabs z16.s, p2/m, z17.s -+ __ sve_fadd(z15, __ S, p0, z26); // fadd z15.s, p0/m, z15.s, z26.s -+ __ sve_fdiv(z10, __ S, p7, z19); // fdiv z10.s, p7/m, z10.s, z19.s -+ __ sve_fmax(z24, __ D, p0, z17); // fmax z24.d, p0/m, z24.d, z17.d -+ __ sve_fmin(z26, __ D, p4, z15); // fmin z26.d, p4/m, z26.d, z15.d -+ __ sve_fmul(z24, __ D, p2, z17); // fmul z24.d, p2/m, z24.d, z17.d -+ __ sve_fneg(z30, __ S, p5, z29); // fneg z30.s, p5/m, z29.s -+ __ sve_frintm(z18, __ S, p5, z10); // frintm z18.s, p5/m, z10.s -+ __ sve_frintn(z30, __ D, p2, z30); // frintn z30.d, p2/m, z30.d -+ __ sve_frintp(z6, __ S, p6, z30); // frintp z6.s, p6/m, z30.s -+ __ sve_fsqrt(z20, __ D, p6, z2); // fsqrt z20.d, p6/m, z2.d -+ __ sve_fsub(z9, __ S, p5, z29); // fsub z9.s, p5/m, z9.s, z29.s -+ __ sve_fmla(z18, __ D, p2, z3, z22); // fmla z18.d, p2/m, z3.d, z22.d -+ __ sve_fmls(z15, __ D, p2, z13, z12); // fmls z15.d, p2/m, z13.d, z12.d -+ __ sve_fnmla(z12, __ S, p0, z30, z30); // fnmla z12.s, p0/m, z30.s, z30.s -+ __ sve_fnmls(z7, __ D, p3, z21, z0); // fnmls z7.d, p3/m, z21.d, z0.d -+ __ sve_mla(z19, __ H, p2, z26, z20); // mla z19.h, p2/m, z26.h, z20.h -+ __ sve_mls(z16, __ D, p7, z1, z21); // mls z16.d, p7/m, z1.d, z21.d -+ __ sve_and(z21, z4, z18); // and z21.d, z4.d, z18.d -+ __ sve_eor(z12, z18, z7); // eor z12.d, z18.d, z7.d -+ __ sve_orr(z25, z15, z13); // orr z25.d, z15.d, z13.d -+ -+// SVEReductionOp -+ __ sve_andv(v11, __ D, p4, z7); // andv d11, p4, z7.d -+ __ sve_orv(v11, __ D, p1, z9); // orv d11, p1, z9.d -+ __ sve_eorv(v28, __ D, p7, z0); // eorv d28, p7, z0.d -+ __ sve_smaxv(v16, __ H, p0, z7); // smaxv h16, p0, z7.h -+ __ sve_sminv(v12, __ B, p3, z29); // sminv b12, p3, z29.b -+ __ sve_fminv(v21, __ S, p6, z11); // fminv s21, p6, z11.s -+ __ sve_fmaxv(v6, __ D, p2, z4); // fmaxv d6, p2, z4.d -+ __ sve_fadda(v7, __ D, p0, z7); // fadda d7, p0, d7, z7.d -+ __ sve_uaddv(v12, __ B, p7, z29); // uaddv d12, p7, z29.b + + // LSEOp +- __ swp(Assembler::xword, r21, r5, r24); // swp x21, x5, [x24] +- __ ldadd(Assembler::xword, r13, r13, r15); // ldadd x13, x13, [x15] +- __ ldbic(Assembler::xword, r22, r19, r26); // ldclr x22, x19, [x26] +- __ ldeor(Assembler::xword, r25, r10, r26); // ldeor x25, x10, [x26] +- __ ldorr(Assembler::xword, r5, r27, r15); // ldset x5, x27, [x15] +- __ ldsmin(Assembler::xword, r19, r5, r11); // ldsmin x19, x5, [x11] +- __ ldsmax(Assembler::xword, r26, r0, r4); // ldsmax x26, x0, [x4] +- __ ldumin(Assembler::xword, r22, r23, r30); // ldumin x22, x23, [x30] +- __ ldumax(Assembler::xword, r18, r28, r8); // ldumax x18, x28, [x8] ++ __ swp(Assembler::xword, r26, r9, r17); // swp x26, x9, [x17] ++ __ ldadd(Assembler::xword, r28, r23, r2); // ldadd x28, x23, [x2] ++ __ ldbic(Assembler::xword, r22, r2, r3); // ldclr x22, x2, [x3] ++ __ ldeor(Assembler::xword, r11, r25, r30); // ldeor x11, x25, [x30] ++ __ ldorr(Assembler::xword, r22, r28, r4); // ldset x22, x28, [x4] ++ __ ldsmin(Assembler::xword, r6, r11, r24); // ldsmin x6, x11, [x24] ++ __ ldsmax(Assembler::xword, r12, zr, sp); // ldsmax x12, xzr, [sp] ++ __ ldumin(Assembler::xword, r23, r30, r9); // ldumin x23, x30, [x9] ++ __ ldumax(Assembler::xword, r6, r1, r20); // ldumax x6, x1, [x20] + + // LSEOp +- __ swpa(Assembler::xword, r13, r29, r27); // swpa x13, x29, [x27] +- __ ldadda(Assembler::xword, r11, r5, r13); // ldadda x11, x5, [x13] +- __ ldbica(Assembler::xword, r1, r24, r21); // ldclra x1, x24, [x21] +- __ ldeora(Assembler::xword, r27, r17, r24); // ldeora x27, x17, [x24] +- __ ldorra(Assembler::xword, r18, r30, r5); // ldseta x18, x30, [x5] +- __ ldsmina(Assembler::xword, r7, r22, r25); // ldsmina x7, x22, [x25] +- __ ldsmaxa(Assembler::xword, r4, r26, r19); // ldsmaxa x4, x26, [x19] +- __ ldumina(Assembler::xword, r6, r30, r3); // ldumina x6, x30, [x3] +- __ ldumaxa(Assembler::xword, r24, r23, r5); // ldumaxa x24, x23, [x5] ++ __ swpa(Assembler::xword, r17, r2, r22); // swpa x17, x2, [x22] ++ __ ldadda(Assembler::xword, r14, r27, r10); // ldadda x14, x27, [x10] ++ __ ldbica(Assembler::xword, r6, r30, r19); // ldclra x6, x30, [x19] ++ __ ldeora(Assembler::xword, r0, r25, r11); // ldeora x0, x25, [x11] ++ __ ldorra(Assembler::xword, r23, r0, r30); // ldseta x23, x0, [x30] ++ __ ldsmina(Assembler::xword, r21, r3, r10); // ldsmina x21, x3, [x10] ++ __ ldsmaxa(Assembler::xword, r15, r22, r0); // ldsmaxa x15, x22, [x0] ++ __ ldumina(Assembler::xword, r17, r0, r20); // ldumina x17, x0, [x20] ++ __ ldumaxa(Assembler::xword, r16, r13, r1); // ldumaxa x16, x13, [x1] + + // LSEOp +- __ swpal(Assembler::xword, r24, r18, r28); // swpal x24, x18, [x28] +- __ ldaddal(Assembler::xword, r19, zr, r7); // ldaddal x19, xzr, [x7] +- __ ldbical(Assembler::xword, r13, r6, r28); // ldclral x13, x6, [x28] +- __ ldeoral(Assembler::xword, r8, r15, r21); // ldeoral x8, x15, [x21] +- __ ldorral(Assembler::xword, r2, r13, r1); // ldsetal x2, x13, [x1] +- __ ldsminal(Assembler::xword, r17, r29, r25); // ldsminal x17, x29, [x25] +- __ ldsmaxal(Assembler::xword, r25, r18, r14); // ldsmaxal x25, x18, [x14] +- __ lduminal(Assembler::xword, zr, r6, r27); // lduminal xzr, x6, [x27] +- __ ldumaxal(Assembler::xword, r16, r5, r15); // ldumaxal x16, x5, [x15] ++ __ swpal(Assembler::xword, r27, r15, r23); // swpal x27, x15, [x23] ++ __ ldaddal(Assembler::xword, r19, r30, r1); // ldaddal x19, x30, [x1] ++ __ ldbical(Assembler::xword, r15, r28, r23); // ldclral x15, x28, [x23] ++ __ ldeoral(Assembler::xword, r7, r15, r19); // ldeoral x7, x15, [x19] ++ __ ldorral(Assembler::xword, r11, r12, r10); // ldsetal x11, x12, [x10] ++ __ ldsminal(Assembler::xword, r6, r7, r12); // ldsminal x6, x7, [x12] ++ __ ldsmaxal(Assembler::xword, r28, r5, r13); // ldsmaxal x28, x5, [x13] ++ __ lduminal(Assembler::xword, r9, r20, r17); // lduminal x9, x20, [x17] ++ __ ldumaxal(Assembler::xword, r21, r25, r11); // ldumaxal x21, x25, [x11] + + // LSEOp +- __ swpl(Assembler::xword, r11, r18, r3); // swpl x11, x18, [x3] +- __ ldaddl(Assembler::xword, r26, r20, r2); // ldaddl x26, x20, [x2] +- __ ldbicl(Assembler::xword, r11, r4, r11); // ldclrl x11, x4, [x11] +- __ ldeorl(Assembler::xword, r30, r19, r23); // ldeorl x30, x19, [x23] +- __ ldorrl(Assembler::xword, r3, r15, r14); // ldsetl x3, x15, [x14] +- __ ldsminl(Assembler::xword, r30, r22, r20); // ldsminl x30, x22, [x20] +- __ ldsmaxl(Assembler::xword, r7, r5, r24); // ldsmaxl x7, x5, [x24] +- __ lduminl(Assembler::xword, r23, r16, r15); // lduminl x23, x16, [x15] +- __ ldumaxl(Assembler::xword, r11, r19, r0); // ldumaxl x11, x19, [x0] ++ __ swpl(Assembler::xword, r19, r24, r24); // swpl x19, x24, [x24] ++ __ ldaddl(Assembler::xword, r8, r26, r30); // ldaddl x8, x26, [x30] ++ __ ldbicl(Assembler::xword, r17, r18, r8); // ldclrl x17, x18, [x8] ++ __ ldeorl(Assembler::xword, r2, r3, r3); // ldeorl x2, x3, [x3] ++ __ ldorrl(Assembler::xword, r26, r7, r16); // ldsetl x26, x7, [x16] ++ __ ldsminl(Assembler::xword, r27, r6, r5); // ldsminl x27, x6, [x5] ++ __ ldsmaxl(Assembler::xword, r22, r0, r20); // ldsmaxl x22, x0, [x20] ++ __ lduminl(Assembler::xword, r11, r26, r2); // lduminl x11, x26, [x2] ++ __ ldumaxl(Assembler::xword, r30, r29, r4); // ldumaxl x30, x29, [x4] + + // LSEOp +- __ swp(Assembler::word, r28, r28, r1); // swp w28, w28, [x1] +- __ ldadd(Assembler::word, r11, r21, r12); // ldadd w11, w21, [x12] +- __ ldbic(Assembler::word, r29, r0, r18); // ldclr w29, w0, [x18] +- __ ldeor(Assembler::word, r5, r0, r25); // ldeor w5, w0, [x25] +- __ ldorr(Assembler::word, r14, r0, r26); // ldset w14, w0, [x26] +- __ ldsmin(Assembler::word, r28, r18, r29); // ldsmin w28, w18, [x29] +- __ ldsmax(Assembler::word, r15, r1, r29); // ldsmax w15, w1, [x29] +- __ ldumin(Assembler::word, r8, r26, r28); // ldumin w8, w26, [x28] +- __ ldumax(Assembler::word, r17, r14, r4); // ldumax w17, w14, [x4] ++ __ swp(Assembler::word, r4, r5, r7); // swp w4, w5, [x7] ++ __ ldadd(Assembler::word, r10, r26, r2); // ldadd w10, w26, [x2] ++ __ ldbic(Assembler::word, r27, r16, r27); // ldclr w27, w16, [x27] ++ __ ldeor(Assembler::word, zr, r23, r10); // ldeor wzr, w23, [x10] ++ __ ldorr(Assembler::word, r4, r2, r13); // ldset w4, w2, [x13] ++ __ ldsmin(Assembler::word, r3, r15, r3); // ldsmin w3, w15, [x3] ++ __ ldsmax(Assembler::word, r3, r10, r6); // ldsmax w3, w10, [x6] ++ __ ldumin(Assembler::word, r8, r11, r10); // ldumin w8, w11, [x10] ++ __ ldumax(Assembler::word, r29, r30, r13); // ldumax w29, w30, [x13] + + // LSEOp +- __ swpa(Assembler::word, r24, r25, r1); // swpa w24, w25, [x1] +- __ ldadda(Assembler::word, r10, r17, r17); // ldadda w10, w17, [x17] +- __ ldbica(Assembler::word, r29, r20, r21); // ldclra w29, w20, [x21] +- __ ldeora(Assembler::word, r29, r9, r12); // ldeora w29, w9, [x12] +- __ ldorra(Assembler::word, r11, r6, r5); // ldseta w11, w6, [x5] +- __ ldsmina(Assembler::word, r21, r7, r21); // ldsmina w21, w7, [x21] +- __ ldsmaxa(Assembler::word, r10, r23, r12); // ldsmaxa w10, w23, [x12] +- __ ldumina(Assembler::word, r21, r5, r10); // ldumina w21, w5, [x10] +- __ ldumaxa(Assembler::word, r30, r20, r18); // ldumaxa w30, w20, [x18] ++ __ swpa(Assembler::word, r11, r17, r20); // swpa w11, w17, [x20] ++ __ ldadda(Assembler::word, r26, r16, r6); // ldadda w26, w16, [x6] ++ __ ldbica(Assembler::word, r21, r10, r1); // ldclra w21, w10, [x1] ++ __ ldeora(Assembler::word, r29, r12, r23); // ldeora w29, w12, [x23] ++ __ ldorra(Assembler::word, r29, r8, r8); // ldseta w29, w8, [x8] ++ __ ldsmina(Assembler::word, r11, r10, r14); // ldsmina w11, w10, [x14] ++ __ ldsmaxa(Assembler::word, r4, r13, r22); // ldsmaxa w4, w13, [x22] ++ __ ldumina(Assembler::word, r7, r13, r7); // ldumina w7, w13, [x7] ++ __ ldumaxa(Assembler::word, r14, r0, sp); // ldumaxa w14, w0, [sp] + + // LSEOp +- __ swpal(Assembler::word, r13, r23, r5); // swpal w13, w23, [x5] +- __ ldaddal(Assembler::word, r15, r24, r5); // ldaddal w15, w24, [x5] +- __ ldbical(Assembler::word, r9, r10, r25); // ldclral w9, w10, [x25] +- __ ldeoral(Assembler::word, r20, r17, r17); // ldeoral w20, w17, [x17] +- __ ldorral(Assembler::word, r12, r18, r30); // ldsetal w12, w18, [x30] +- __ ldsminal(Assembler::word, r3, r3, r25); // ldsminal w3, w3, [x25] +- __ ldsmaxal(Assembler::word, r26, r25, r10); // ldsmaxal w26, w25, [x10] +- __ lduminal(Assembler::word, r2, r11, sp); // lduminal w2, w11, [sp] +- __ ldumaxal(Assembler::word, r7, r2, r5); // ldumaxal w7, w2, [x5] ++ __ swpal(Assembler::word, r17, r2, r28); // swpal w17, w2, [x28] ++ __ ldaddal(Assembler::word, r19, r11, r10); // ldaddal w19, w11, [x10] ++ __ ldbical(Assembler::word, r12, r19, r20); // ldclral w12, w19, [x20] ++ __ ldeoral(Assembler::word, r0, r8, r8); // ldeoral w0, w8, [x8] ++ __ ldorral(Assembler::word, r17, r3, r24); // ldsetal w17, w3, [x24] ++ __ ldsminal(Assembler::word, r25, r5, r7); // ldsminal w25, w5, [x7] ++ __ ldsmaxal(Assembler::word, r16, r30, r9); // ldsmaxal w16, w30, [x9] ++ __ lduminal(Assembler::word, r10, zr, r14); // lduminal w10, wzr, [x14] ++ __ ldumaxal(Assembler::word, r17, r19, r11); // ldumaxal w17, w19, [x11] + + // LSEOp +- __ swpl(Assembler::word, r0, r7, r20); // swpl w0, w7, [x20] +- __ ldaddl(Assembler::word, r5, zr, r2); // ldaddl w5, wzr, [x2] +- __ ldbicl(Assembler::word, r27, r25, r27); // ldclrl w27, w25, [x27] +- __ ldeorl(Assembler::word, r30, r24, r26); // ldeorl w30, w24, [x26] +- __ ldorrl(Assembler::word, r15, r2, r22); // ldsetl w15, w2, [x22] +- __ ldsminl(Assembler::word, r0, r3, sp); // ldsminl w0, w3, [sp] +- __ ldsmaxl(Assembler::word, r15, r20, r10); // ldsmaxl w15, w20, [x10] +- __ lduminl(Assembler::word, r22, r21, r14); // lduminl w22, w21, [x14] +- __ ldumaxl(Assembler::word, r6, r30, r2); // ldumaxl w6, w30, [x2] ++ __ swpl(Assembler::word, r20, r1, r13); // swpl w20, w1, [x13] ++ __ ldaddl(Assembler::word, r26, r11, r20); // ldaddl w26, w11, [x20] ++ __ ldbicl(Assembler::word, r18, r24, r30); // ldclrl w18, w24, [x30] ++ __ ldeorl(Assembler::word, r12, r25, r20); // ldeorl w12, w25, [x20] ++ __ ldorrl(Assembler::word, r14, r29, r5); // ldsetl w14, w29, [x5] ++ __ ldsminl(Assembler::word, r2, r26, r27); // ldsminl w2, w26, [x27] ++ __ ldsmaxl(Assembler::word, r25, r27, r11); // ldsmaxl w25, w27, [x11] ++ __ lduminl(Assembler::word, r4, r29, r7); // lduminl w4, w29, [x7] ++ __ ldumaxl(Assembler::word, r16, r29, r10); // ldumaxl w16, w29, [x10] __ bind(forth); -@@ -633,542 +719,642 @@ aarch64ops.o: file format elf64-littleaarch64 +@@ -762,567 +762,567 @@ aarch64ops.o: file format elf64-littleaarch64 Disassembly of section .text: 0000000000000000 : -- 0: 8b0772d3 add x19, x22, x7, lsl #28 -- 4: cb4a3570 sub x16, x11, x10, lsr #13 -- 8: ab9c09bb adds x27, x13, x28, asr #2 -- c: eb9aa794 subs x20, x28, x26, asr #41 -- 10: 0b934e68 add w8, w19, w19, asr #19 -- 14: 4b0a3924 sub w4, w9, w10, lsl #14 -- 18: 2b1e3568 adds w8, w11, w30, lsl #13 -- 1c: 6b132720 subs w0, w25, w19, lsl #9 -- 20: 8a154c14 and x20, x0, x21, lsl #19 -- 24: aa1445d5 orr x21, x14, x20, lsl #17 -- 28: ca01cf99 eor x25, x28, x1, lsl #51 -- 2c: ea8b3f6a ands x10, x27, x11, asr #15 -- 30: 0a8c5cb9 and w25, w5, w12, asr #23 -- 34: 2a4a11d2 orr w18, w14, w10, lsr #4 -- 38: 4a855aa4 eor w4, w21, w5, asr #22 -- 3c: 6a857415 ands w21, w0, w5, asr #29 -- 40: 8aa697da bic x26, x30, x6, asr #37 -- 44: aa6d7423 orn x3, x1, x13, lsr #29 -- 48: ca29bf80 eon x0, x28, x9, lsl #47 -- 4c: ea3cb8bd bics x29, x5, x28, lsl #46 -- 50: 0a675249 bic w9, w18, w7, lsr #20 -- 54: 2ab961ba orn w26, w13, w25, asr #24 -- 58: 4a331899 eon w25, w4, w19, lsl #6 -- 5c: 6a646345 bics w5, w26, w4, lsr #24 -- 60: 11055267 add w7, w19, #0x154 -- 64: 31064408 adds w8, w0, #0x191 -- 68: 51028e9d sub w29, w20, #0xa3 -- 6c: 710bdee8 subs w8, w23, #0x2f7 -- 70: 91082d81 add x1, x12, #0x20b -- 74: b106a962 adds x2, x11, #0x1aa -- 78: d10b33ae sub x14, x29, #0x2cc -- 7c: f10918ab subs x11, x5, #0x246 -- 80: 121102d7 and w23, w22, #0x8000 -- 84: 3204cd44 orr w4, w10, #0xf0f0f0f0 -- 88: 5204cf00 eor w0, w24, #0xf0f0f0f0 -- 8c: 72099fb3 ands w19, w29, #0x7f807f80 -- 90: 92729545 and x5, x10, #0xfffffffffc000 -- 94: b20e37cc orr x12, x30, #0xfffc0000fffc0000 -- 98: d27c34be eor x30, x5, #0x3fff0 -- 9c: f27e4efa ands x26, x23, #0x3ffffc -- a0: 14000000 b a0 -- a4: 17ffffd7 b 0 -- a8: 1400017f b 6a4 -- ac: 94000000 bl ac -- b0: 97ffffd4 bl 0 -- b4: 9400017c bl 6a4 -- b8: 3400000c cbz w12, b8 -- bc: 34fffa2c cbz w12, 0 -- c0: 34002f2c cbz w12, 6a4 -- c4: 35000014 cbnz w20, c4 -- c8: 35fff9d4 cbnz w20, 0 -- cc: 35002ed4 cbnz w20, 6a4 -- d0: b400000c cbz x12, d0 -- d4: b4fff96c cbz x12, 0 -- d8: b4002e6c cbz x12, 6a4 -- dc: b5000018 cbnz x24, dc -- e0: b5fff918 cbnz x24, 0 -- e4: b5002e18 cbnz x24, 6a4 -- e8: 10000006 adr x6, e8 -- ec: 10fff8a6 adr x6, 0 -- f0: 10002da6 adr x6, 6a4 -- f4: 90000015 adrp x21, 0 -- f8: 36080001 tbz w1, #1, f8 -- fc: 360ff821 tbz w1, #1, 0 -- 100: 36082d21 tbz w1, #1, 6a4 -- 104: 37480008 tbnz w8, #9, 104 -- 108: 374ff7c8 tbnz w8, #9, 0 -- 10c: 37482cc8 tbnz w8, #9, 6a4 -- 110: 128b50ec movn w12, #0x5a87 -- 114: 52a9ff8b movz w11, #0x4ffc, lsl #16 -- 118: 7281d095 movk w21, #0xe84 -- 11c: 92edfebd movn x29, #0x6ff5, lsl #48 -- 120: d28361e3 movz x3, #0x1b0f -- 124: f2a4cc96 movk x22, #0x2664, lsl #16 -- 128: 9346590c sbfx x12, x8, #6, #17 -- 12c: 33194f33 bfi w19, w25, #7, #20 -- 130: 531d3d89 ubfiz w9, w12, #3, #16 -- 134: 9350433c sbfx x28, x25, #16, #1 -- 138: b34464ac bfxil x12, x5, #4, #22 -- 13c: d3462140 ubfx x0, x10, #6, #3 -- 140: 139a61a4 extr w4, w13, w26, #24 -- 144: 93d87fd7 extr x23, x30, x24, #31 -- 148: 54000000 b.eq 148 -- 14c: 54fff5a0 b.eq 0 -- 150: 54002aa0 b.eq 6a4 -- 154: 54000001 b.ne 154 -- 158: 54fff541 b.ne 0 -- 15c: 54002a41 b.ne 6a4 -- 160: 54000002 b.cs 160 -- 164: 54fff4e2 b.cs 0 -- 168: 540029e2 b.cs 6a4 -- 16c: 54000002 b.cs 16c -- 170: 54fff482 b.cs 0 -- 174: 54002982 b.cs 6a4 -- 178: 54000003 b.cc 178 -- 17c: 54fff423 b.cc 0 -- 180: 54002923 b.cc 6a4 -- 184: 54000003 b.cc 184 -- 188: 54fff3c3 b.cc 0 -- 18c: 540028c3 b.cc 6a4 -- 190: 54000004 b.mi 190 -- 194: 54fff364 b.mi 0 -- 198: 54002864 b.mi 6a4 -- 19c: 54000005 b.pl 19c -- 1a0: 54fff305 b.pl 0 -- 1a4: 54002805 b.pl 6a4 -- 1a8: 54000006 b.vs 1a8 -- 1ac: 54fff2a6 b.vs 0 -- 1b0: 540027a6 b.vs 6a4 -- 1b4: 54000007 b.vc 1b4 -- 1b8: 54fff247 b.vc 0 -- 1bc: 54002747 b.vc 6a4 -- 1c0: 54000008 b.hi 1c0 -- 1c4: 54fff1e8 b.hi 0 -- 1c8: 540026e8 b.hi 6a4 -- 1cc: 54000009 b.ls 1cc -- 1d0: 54fff189 b.ls 0 -- 1d4: 54002689 b.ls 6a4 -- 1d8: 5400000a b.ge 1d8 -- 1dc: 54fff12a b.ge 0 -- 1e0: 5400262a b.ge 6a4 -- 1e4: 5400000b b.lt 1e4 -- 1e8: 54fff0cb b.lt 0 -- 1ec: 540025cb b.lt 6a4 -- 1f0: 5400000c b.gt 1f0 -- 1f4: 54fff06c b.gt 0 -- 1f8: 5400256c b.gt 6a4 -- 1fc: 5400000d b.le 1fc -- 200: 54fff00d b.le 0 -- 204: 5400250d b.le 6a4 -- 208: 5400000e b.al 208 -- 20c: 54ffefae b.al 0 -- 210: 540024ae b.al 6a4 -- 214: 5400000f b.nv 214 -- 218: 54ffef4f b.nv 0 -- 21c: 5400244f b.nv 6a4 -- 220: d4063721 svc #0x31b9 -- 224: d4035082 hvc #0x1a84 -- 228: d400bfe3 smc #0x5ff -- 22c: d4282fc0 brk #0x417e -- 230: d444c320 hlt #0x2619 -- 234: d503201f nop -- 238: d69f03e0 eret -- 23c: d6bf03e0 drps -- 240: d5033fdf isb -- 244: d5033f9f dsb sy -- 248: d5033abf dmb ishst -- 24c: d61f0040 br x2 -- 250: d63f00a0 blr x5 -- 254: c8147c55 stxr w20, x21, [x2] -- 258: c805fcfd stlxr w5, x29, [x7] -- 25c: c85f7e05 ldxr x5, [x16] -- 260: c85fffbb ldaxr x27, [x29] -- 264: c89fffa0 stlr x0, [x29] -- 268: c8dfff95 ldar x21, [x28] -- 26c: 88157cf8 stxr w21, w24, [x7] -- 270: 8815ff9a stlxr w21, w26, [x28] -- 274: 885f7cd5 ldxr w21, [x6] -- 278: 885fffcf ldaxr w15, [x30] -- 27c: 889ffc73 stlr w19, [x3] -- 280: 88dffc56 ldar w22, [x2] -- 284: 48127c0f stxrh w18, w15, [x0] -- 288: 480bff85 stlxrh w11, w5, [x28] -- 28c: 485f7cdd ldxrh w29, [x6] -- 290: 485ffcf2 ldaxrh w18, [x7] -- 294: 489fff99 stlrh w25, [x28] -- 298: 48dffe62 ldarh w2, [x19] -- 29c: 080a7c3e stxrb w10, w30, [x1] -- 2a0: 0814fed5 stlxrb w20, w21, [x22] -- 2a4: 085f7c59 ldxrb w25, [x2] -- 2a8: 085ffcb8 ldaxrb w24, [x5] -- 2ac: 089ffc70 stlrb w16, [x3] -- 2b0: 08dfffb6 ldarb w22, [x29] -- 2b4: c87f0a68 ldxp x8, x2, [x19] -- 2b8: c87fcdc7 ldaxp x7, x19, [x14] -- 2bc: c82870bb stxp w8, x27, x28, [x5] -- 2c0: c825b8c8 stlxp w5, x8, x14, [x6] -- 2c4: 887f12d9 ldxp w25, w4, [x22] -- 2c8: 887fb9ed ldaxp w13, w14, [x15] -- 2cc: 8834215a stxp w20, w26, w8, [x10] -- 2d0: 8837ca52 stlxp w23, w18, w18, [x18] -- 2d4: f806317e str x30, [x11,#99] -- 2d8: b81b3337 str w23, [x25,#-77] -- 2dc: 39000dc2 strb w2, [x14,#3] -- 2e0: 78005149 strh w9, [x10,#5] -- 2e4: f84391f4 ldr x20, [x15,#57] -- 2e8: b85b220c ldr w12, [x16,#-78] -- 2ec: 385fd356 ldrb w22, [x26,#-3] -- 2f0: 785d127e ldrh w30, [x19,#-47] -- 2f4: 389f4149 ldrsb x9, [x10,#-12] -- 2f8: 79801e3c ldrsh x28, [x17,#14] -- 2fc: 79c014a3 ldrsh w3, [x5,#10] -- 300: b89a5231 ldrsw x17, [x17,#-91] -- 304: fc5ef282 ldr d2, [x20,#-17] -- 308: bc5f60f6 ldr s22, [x7,#-10] -- 30c: fc12125e str d30, [x18,#-223] -- 310: bc0152cd str s13, [x22,#21] -- 314: f8190e49 str x9, [x18,#-112]! -- 318: b800befd str w29, [x23,#11]! -- 31c: 381ffd92 strb w18, [x12,#-1]! -- 320: 781e9e90 strh w16, [x20,#-23]! -- 324: f8409fa3 ldr x3, [x29,#9]! -- 328: b8413c79 ldr w25, [x3,#19]! -- 32c: 385fffa1 ldrb w1, [x29,#-1]! -- 330: 785c7fa8 ldrh w8, [x29,#-57]! -- 334: 389f3dc5 ldrsb x5, [x14,#-13]! -- 338: 78801f6a ldrsh x10, [x27,#1]! -- 33c: 78c19d4b ldrsh w11, [x10,#25]! -- 340: b89a4ec4 ldrsw x4, [x22,#-92]! -- 344: fc408eeb ldr d11, [x23,#8]! -- 348: bc436e79 ldr s25, [x19,#54]! -- 34c: fc152ce1 str d1, [x7,#-174]! -- 350: bc036f28 str s8, [x25,#54]! -- 354: f8025565 str x5, [x11],#37 -- 358: b80135f8 str w24, [x15],#19 -- 35c: 381ff74f strb w15, [x26],#-1 -- 360: 781fa652 strh w18, [x18],#-6 -- 364: f851a447 ldr x7, [x2],#-230 -- 368: b85e557b ldr w27, [x11],#-27 -- 36c: 385e7472 ldrb w18, [x3],#-25 -- 370: 785e070a ldrh w10, [x24],#-32 -- 374: 38804556 ldrsb x22, [x10],#4 -- 378: 78819591 ldrsh x17, [x12],#25 -- 37c: 78dc24e8 ldrsh w8, [x7],#-62 -- 380: b89cd6d7 ldrsw x23, [x22],#-51 -- 384: fc430738 ldr d24, [x25],#48 -- 388: bc5f6595 ldr s21, [x12],#-10 -- 38c: fc1225b2 str d18, [x13],#-222 -- 390: bc1d7430 str s16, [x1],#-41 -- 394: f82fcac2 str x2, [x22,w15,sxtw] -- 398: b83d6a02 str w2, [x16,x29] -- 39c: 382e5a54 strb w20, [x18,w14,uxtw #0] -- 3a0: 7834fa66 strh w6, [x19,x20,sxtx #1] -- 3a4: f86ecbae ldr x14, [x29,w14,sxtw] -- 3a8: b86cda90 ldr w16, [x20,w12,sxtw #2] -- 3ac: 3860d989 ldrb w9, [x12,w0,sxtw #0] -- 3b0: 78637a2c ldrh w12, [x17,x3,lsl #1] -- 3b4: 38a3fa22 ldrsb x2, [x17,x3,sxtx #0] -- 3b8: 78b15827 ldrsh x7, [x1,w17,uxtw #1] -- 3bc: 78f2d9f9 ldrsh w25, [x15,w18,sxtw #1] -- 3c0: b8ac6ab7 ldrsw x23, [x21,x12] -- 3c4: fc6879a5 ldr d5, [x13,x8,lsl #3] -- 3c8: bc767943 ldr s3, [x10,x22,lsl #2] -- 3cc: fc3bc84e str d14, [x2,w27,sxtw] -- 3d0: bc3968d4 str s20, [x6,x25] -- 3d4: f91fc0fe str x30, [x7,#16256] -- 3d8: b91da50f str w15, [x8,#7588] -- 3dc: 391d280b strb w11, [x0,#1866] -- 3e0: 791d2e23 strh w3, [x17,#3734] -- 3e4: f95bc8e2 ldr x2, [x7,#14224] -- 3e8: b95ce525 ldr w5, [x9,#7396] -- 3ec: 395ae53c ldrb w28, [x9,#1721] -- 3f0: 795c9282 ldrh w2, [x20,#3656] -- 3f4: 399d7dd6 ldrsb x22, [x14,#1887] -- 3f8: 799fe008 ldrsh x8, [x0,#4080] -- 3fc: 79de9bc0 ldrsh w0, [x30,#3916] -- 400: b99aae78 ldrsw x24, [x19,#6828] -- 404: fd597598 ldr d24, [x12,#13032] -- 408: bd5d1d08 ldr s8, [x8,#7452] -- 40c: fd1f3dea str d10, [x15,#15992] -- 410: bd1a227a str s26, [x19,#6688] -- 414: 5800148a ldr x10, 6a4 -- 418: 18000003 ldr w3, 418 -- 41c: f88092e0 prfm pldl1keep, [x23,#9] -- 420: d8ffdf00 prfm pldl1keep, 0 -- 424: f8a84860 prfm pldl1keep, [x3,w8,uxtw] -- 428: f99d7560 prfm pldl1keep, [x11,#15080] -- 42c: 1a1c012d adc w13, w9, w28 -- 430: 3a1c027b adcs w27, w19, w28 -- 434: 5a060253 sbc w19, w18, w6 -- 438: 7a03028e sbcs w14, w20, w3 -- 43c: 9a0801d0 adc x16, x14, x8 -- 440: ba0803a0 adcs x0, x29, x8 -- 444: da140308 sbc x8, x24, x20 -- 448: fa00038c sbcs x12, x28, x0 -- 44c: 0b3010d7 add w23, w6, w16, uxtb #4 -- 450: 2b37ab39 adds w25, w25, w23, sxth #2 -- 454: cb2466da sub x26, x22, x4, uxtx #1 -- 458: 6b33efb1 subs w17, w29, w19, sxtx #3 -- 45c: 8b350fcb add x11, x30, w21, uxtb #3 -- 460: ab208a70 adds x16, x19, w0, sxtb #2 -- 464: cb39e52b sub x11, x9, x25, sxtx #1 -- 468: eb2c9291 subs x17, x20, w12, sxtb #4 -- 46c: 3a4bd1a3 ccmn w13, w11, #0x3, le -- 470: 7a4c81a2 ccmp w13, w12, #0x2, hi -- 474: ba42106c ccmn x3, x2, #0xc, ne -- 478: fa5560e3 ccmp x7, x21, #0x3, vs -- 47c: 3a4e3844 ccmn w2, #0xe, #0x4, cc -- 480: 7a515a26 ccmp w17, #0x11, #0x6, pl -- 484: ba4c2940 ccmn x10, #0xc, #0x0, cs -- 488: fa52aaae ccmp x21, #0x12, #0xe, ge -- 48c: 1a8cc1b5 csel w21, w13, w12, gt -- 490: 1a8f976a csinc w10, w27, w15, ls -- 494: 5a8981a0 csinv w0, w13, w9, hi -- 498: 5a9a6492 csneg w18, w4, w26, vs -- 49c: 9a8793ac csel x12, x29, x7, ls -- 4a0: 9a9474e6 csinc x6, x7, x20, vc -- 4a4: da83d2b6 csinv x22, x21, x3, le -- 4a8: da9b9593 csneg x19, x12, x27, ls -- 4ac: 5ac00200 rbit w0, w16 -- 4b0: 5ac006f1 rev16 w17, w23 -- 4b4: 5ac009d1 rev w17, w14 -- 4b8: 5ac013d8 clz w24, w30 -- 4bc: 5ac016d8 cls w24, w22 -- 4c0: dac00223 rbit x3, x17 -- 4c4: dac005ac rev16 x12, x13 -- 4c8: dac00ac9 rev32 x9, x22 -- 4cc: dac00c00 rev x0, x0 -- 4d0: dac01205 clz x5, x16 -- 4d4: dac016d9 cls x25, x22 -- 4d8: 1ac0089d udiv w29, w4, w0 -- 4dc: 1add0fa0 sdiv w0, w29, w29 -- 4e0: 1ad52225 lsl w5, w17, w21 -- 4e4: 1ad22529 lsr w9, w9, w18 -- 4e8: 1ac82b61 asr w1, w27, w8 -- 4ec: 1acd2e92 ror w18, w20, w13 -- 4f0: 9acc0b28 udiv x8, x25, x12 -- 4f4: 9adc0ca7 sdiv x7, x5, x28 -- 4f8: 9adb2225 lsl x5, x17, x27 -- 4fc: 9ad42757 lsr x23, x26, x20 -- 500: 9adc291c asr x28, x8, x28 -- 504: 9ac42fa3 ror x3, x29, x4 -- 508: 1b1a55d1 madd w17, w14, w26, w21 -- 50c: 1b0bafc1 msub w1, w30, w11, w11 -- 510: 9b067221 madd x1, x17, x6, x28 -- 514: 9b1ea0de msub x30, x6, x30, x8 -- 518: 9b2e20d5 smaddl x21, w6, w14, x8 -- 51c: 9b38cd4a smsubl x10, w10, w24, x19 -- 520: 9bae6254 umaddl x20, w18, w14, x24 -- 524: 9ba59452 umsubl x18, w2, w5, x5 -- 528: 1e2d0a48 fmul s8, s18, s13 -- 52c: 1e3c19c2 fdiv s2, s14, s28 -- 530: 1e3c298f fadd s15, s12, s28 -- 534: 1e213980 fsub s0, s12, s1 -- 538: 1e240baf fmul s15, s29, s4 -- 53c: 1e77082c fmul d12, d1, d23 -- 540: 1e72191b fdiv d27, d8, d18 -- 544: 1e6b2a97 fadd d23, d20, d11 -- 548: 1e723988 fsub d8, d12, d18 -- 54c: 1e770b1a fmul d26, d24, d23 -- 550: 1f0d66f5 fmadd s21, s23, s13, s25 -- 554: 1f01b956 fmsub s22, s10, s1, s14 -- 558: 1f227a8e fnmadd s14, s20, s2, s30 -- 55c: 1f365ba7 fnmadd s7, s29, s22, s22 -- 560: 1f4f14ad fmadd d13, d5, d15, d5 -- 564: 1f45a98e fmsub d14, d12, d5, d10 -- 568: 1f60066a fnmadd d10, d19, d0, d1 -- 56c: 1f620054 fnmadd d20, d2, d2, d0 -- 570: 1e204139 fmov s25, s9 -- 574: 1e20c094 fabs s20, s4 -- 578: 1e214363 fneg s3, s27 -- 57c: 1e21c041 fsqrt s1, s2 -- 580: 1e22c01e fcvt d30, s0 -- 584: 1e60408c fmov d12, d4 -- 588: 1e60c361 fabs d1, d27 -- 58c: 1e6142c8 fneg d8, d22 -- 590: 1e61c16b fsqrt d11, d11 -- 594: 1e624396 fcvt s22, d28 -- 598: 1e3802dc fcvtzs w28, s22 -- 59c: 9e380374 fcvtzs x20, s27 -- 5a0: 1e78000e fcvtzs w14, d0 -- 5a4: 9e78017a fcvtzs x26, d11 -- 5a8: 1e2202dc scvtf s28, w22 -- 5ac: 9e220150 scvtf s16, x10 -- 5b0: 1e6202a8 scvtf d8, w21 -- 5b4: 9e620395 scvtf d21, x28 -- 5b8: 1e260318 fmov w24, s24 -- 5bc: 9e660268 fmov x8, d19 -- 5c0: 1e270188 fmov s8, w12 -- 5c4: 9e6700e6 fmov d6, x7 -- 5c8: 1e3023c0 fcmp s30, s16 -- 5cc: 1e6b2320 fcmp d25, d11 -- 5d0: 1e202168 fcmp s11, #0.0 -- 5d4: 1e602168 fcmp d11, #0.0 -- 5d8: 2910323d stp w29, w12, [x17,#128] -- 5dc: 297449d6 ldp w22, w18, [x14,#-96] -- 5e0: 6948402b ldpsw x11, x16, [x1,#64] -- 5e4: a9072f40 stp x0, x11, [x26,#112] -- 5e8: a9410747 ldp x7, x1, [x26,#16] -- 5ec: 29801f0a stp w10, w7, [x24,#0]! -- 5f0: 29e07307 ldp w7, w28, [x24,#-256]! -- 5f4: 69e272b9 ldpsw x25, x28, [x21,#-240]! -- 5f8: a9bf49d4 stp x20, x18, [x14,#-16]! -- 5fc: a9c529a8 ldp x8, x10, [x13,#80]! -- 600: 28b0605a stp w26, w24, [x2],#-128 -- 604: 28e866a2 ldp w2, w25, [x21],#-192 -- 608: 68ee0ab1 ldpsw x17, x2, [x21],#-144 -- 60c: a886296c stp x12, x10, [x11],#96 -- 610: a8fe1a38 ldp x24, x6, [x17],#-32 -- 614: 282479c3 stnp w3, w30, [x14,#-224] -- 618: 286e534f ldnp w15, w20, [x26,#-144] -- 61c: a8386596 stnp x22, x25, [x12,#-128] -- 620: a8755a3b ldnp x27, x22, [x17,#-176] -- 624: 1e601000 fmov d0, #2.000000000000000000e+00 -- 628: 1e603000 fmov d0, #2.125000000000000000e+00 -- 62c: 1e621000 fmov d0, #4.000000000000000000e+00 -- 630: 1e623000 fmov d0, #4.250000000000000000e+00 -- 634: 1e641000 fmov d0, #8.000000000000000000e+00 -- 638: 1e643000 fmov d0, #8.500000000000000000e+00 -- 63c: 1e661000 fmov d0, #1.600000000000000000e+01 -- 640: 1e663000 fmov d0, #1.700000000000000000e+01 -- 644: 1e681000 fmov d0, #1.250000000000000000e-01 -- 648: 1e683000 fmov d0, #1.328125000000000000e-01 -- 64c: 1e6a1000 fmov d0, #2.500000000000000000e-01 -- 650: 1e6a3000 fmov d0, #2.656250000000000000e-01 -- 654: 1e6c1000 fmov d0, #5.000000000000000000e-01 -- 658: 1e6c3000 fmov d0, #5.312500000000000000e-01 -- 65c: 1e6e1000 fmov d0, #1.000000000000000000e+00 -- 660: 1e6e3000 fmov d0, #1.062500000000000000e+00 -- 664: 1e701000 fmov d0, #-2.000000000000000000e+00 -- 668: 1e703000 fmov d0, #-2.125000000000000000e+00 -- 66c: 1e721000 fmov d0, #-4.000000000000000000e+00 -- 670: 1e723000 fmov d0, #-4.250000000000000000e+00 -- 674: 1e741000 fmov d0, #-8.000000000000000000e+00 -- 678: 1e743000 fmov d0, #-8.500000000000000000e+00 -- 67c: 1e761000 fmov d0, #-1.600000000000000000e+01 -- 680: 1e763000 fmov d0, #-1.700000000000000000e+01 -- 684: 1e781000 fmov d0, #-1.250000000000000000e-01 -- 688: 1e783000 fmov d0, #-1.328125000000000000e-01 -- 68c: 1e7a1000 fmov d0, #-2.500000000000000000e-01 -- 690: 1e7a3000 fmov d0, #-2.656250000000000000e-01 -- 694: 1e7c1000 fmov d0, #-5.000000000000000000e-01 -- 698: 1e7c3000 fmov d0, #-5.312500000000000000e-01 -- 69c: 1e7e1000 fmov d0, #-1.000000000000000000e+00 -- 6a0: 1e7e3000 fmov d0, #-1.062500000000000000e+00 -+ 0: 8b0d82fa add x26, x23, x13, lsl #32 -+ 4: cb49970c sub x12, x24, x9, lsr #37 -+ 8: ab889dfc adds x28, x15, x8, asr #39 -+ c: eb9ee787 subs x7, x28, x30, asr #57 -+ 10: 0b9b3ec9 add w9, w22, w27, asr #15 -+ 14: 4b9279a3 sub w3, w13, w18, asr #30 -+ 18: 2b88474e adds w14, w26, w8, asr #17 -+ 1c: 6b8c56c0 subs w0, w22, w12, asr #21 -+ 20: 8a1a51e0 and x0, x15, x26, lsl #20 -+ 24: aa11f4ba orr x26, x5, x17, lsl #61 -+ 28: ca0281b8 eor x24, x13, x2, lsl #32 -+ 2c: ea918c7c ands x28, x3, x17, asr #35 -+ 30: 0a5d4a19 and w25, w16, w29, lsr #18 -+ 34: 2a4b264d orr w13, w18, w11, lsr #9 -+ 38: 4a523ca5 eor w5, w5, w18, lsr #15 -+ 3c: 6a9b6ae2 ands w2, w23, w27, asr #26 -+ 40: 8a70b79b bic x27, x28, x16, lsr #45 -+ 44: aaba9728 orn x8, x25, x26, asr #37 -+ 48: ca6dfe3d eon x29, x17, x13, lsr #63 -+ 4c: ea627f1c bics x28, x24, x2, lsr #31 -+ 50: 0aa70f53 bic w19, w26, w7, asr #3 -+ 54: 2aaa0f06 orn w6, w24, w10, asr #3 -+ 58: 4a6176a4 eon w4, w21, w1, lsr #29 -+ 5c: 6a604eb0 bics w16, w21, w0, lsr #19 -+ 60: 1105ed91 add w17, w12, #0x17b -+ 64: 3100583e adds w30, w1, #0x16 -+ 68: 5101f8bd sub w29, w5, #0x7e -+ 6c: 710f0306 subs w6, w24, #0x3c0 -+ 70: 9101a1a0 add x0, x13, #0x68 -+ 74: b10a5cc8 adds x8, x6, #0x297 -+ 78: d10810aa sub x10, x5, #0x204 -+ 7c: f10fd061 subs x1, x3, #0x3f4 -+ 80: 120cb166 and w6, w11, #0xfff1fff1 -+ 84: 321764bc orr w28, w5, #0xfffffe07 -+ 88: 52174681 eor w1, w20, #0x7fffe00 -+ 8c: 720c0247 ands w7, w18, #0x100000 -+ 90: 9241018e and x14, x12, #0x8000000000000000 -+ 94: b25a2969 orr x9, x11, #0x1ffc000000000 -+ 98: d278b411 eor x17, x0, #0x3fffffffffff00 -+ 9c: f26aad01 ands x1, x8, #0xffffffffffc00003 +- 0: 8b50798f add x15, x12, x16, lsr #30 +- 4: cb4381e1 sub x1, x15, x3, lsr #32 +- 8: ab05372d adds x13, x25, x5, lsl #13 +- c: eb864796 subs x22, x28, x6, asr #17 +- 10: 0b961920 add w0, w9, w22, asr #6 +- 14: 4b195473 sub w19, w3, w25, lsl #21 +- 18: 2b0b5264 adds w4, w19, w11, lsl #20 +- 1c: 6b9300f8 subs w24, w7, w19, asr #0 +- 20: 8a0bc0fe and x30, x7, x11, lsl #48 +- 24: aa0f3118 orr x24, x8, x15, lsl #12 +- 28: ca170531 eor x17, x9, x23, lsl #1 +- 2c: ea44dd6e ands x14, x11, x4, lsr #55 +- 30: 0a4c44f3 and w19, w7, w12, lsr #17 +- 34: 2a8b7373 orr w19, w27, w11, asr #28 +- 38: 4a567c7e eor w30, w3, w22, lsr #31 +- 3c: 6a9c0353 ands w19, w26, w28, asr #0 +- 40: 8a3accdd bic x29, x6, x26, lsl #51 +- 44: aa318f7a orn x26, x27, x17, lsl #35 +- 48: ca2e1495 eon x21, x4, x14, lsl #5 +- 4c: eaa015e2 bics x2, x15, x0, asr #5 +- 50: 0a2274e2 bic w2, w7, w2, lsl #29 +- 54: 2a751598 orn w24, w12, w21, lsr #5 +- 58: 4a3309fe eon w30, w15, w19, lsl #2 +- 5c: 6ab172fe bics w30, w23, w17, asr #28 +- 60: 110a5284 add w4, w20, #0x294 +- 64: 310b1942 adds w2, w10, #0x2c6 +- 68: 5103d353 sub w19, w26, #0xf4 +- 6c: 710125bc subs w28, w13, #0x49 +- 70: 910d7bc2 add x2, x30, #0x35e +- 74: b108fa1b adds x27, x16, #0x23e +- 78: d1093536 sub x22, x9, #0x24d +- 7c: f10ae824 subs x4, x1, #0x2ba +- 80: 120e667c and w28, w19, #0xfffc0fff +- 84: 321f6cbb orr w27, w5, #0x1ffffffe +- 88: 520f6a9e eor w30, w20, #0xfffe0fff +- 8c: 72136f56 ands w22, w26, #0xffffe1ff +- 90: 927e4ce5 and x5, x7, #0x3ffffc +- 94: b278b4ed orr x13, x7, #0x3fffffffffff00 +- 98: d24c6527 eor x7, x9, #0xfff0000000003fff +- 9c: f2485803 ands x3, x0, #0xff00000000007fff +- a0: 14000000 b a0 +- a4: 17ffffd7 b 0 +- a8: 140001ee b 860 +- ac: 94000000 bl ac +- b0: 97ffffd4 bl 0 +- b4: 940001eb bl 860 +- b8: 34000010 cbz w16, b8 +- bc: 34fffa30 cbz w16, 0 +- c0: 34003d10 cbz w16, 860 +- c4: 35000013 cbnz w19, c4 +- c8: 35fff9d3 cbnz w19, 0 +- cc: 35003cb3 cbnz w19, 860 +- d0: b4000005 cbz x5, d0 +- d4: b4fff965 cbz x5, 0 +- d8: b4003c45 cbz x5, 860 +- dc: b5000004 cbnz x4, dc +- e0: b5fff904 cbnz x4, 0 +- e4: b5003be4 cbnz x4, 860 +- e8: 1000001b adr x27, e8 +- ec: 10fff8bb adr x27, 0 +- f0: 10003b9b adr x27, 860 +- f4: 90000010 adrp x16, 0 +- f8: 3640001c tbz w28, #8, f8 +- fc: 3647f83c tbz w28, #8, 0 +- 100: 36403b1c tbz w28, #8, 860 +- 104: 37080001 tbnz w1, #1, 104 +- 108: 370ff7c1 tbnz w1, #1, 0 +- 10c: 37083aa1 tbnz w1, #1, 860 +- 110: 12a437f4 mov w20, #0xde40ffff // #-566165505 +- 114: 528c9d67 mov w7, #0x64eb // #25835 +- 118: 72838bb1 movk w17, #0x1c5d +- 11c: 92c1062e mov x14, #0xfffff7ceffffffff // #-9006546419713 +- 120: d287da49 mov x9, #0x3ed2 // #16082 +- 124: f2a6d153 movk x19, #0x368a, lsl #16 +- 128: 93465ac9 sbfx x9, x22, #6, #17 +- 12c: 330b0013 bfi w19, w0, #21, #1 +- 130: 530b4e6a ubfx w10, w19, #11, #9 +- 134: 934545e4 sbfx x4, x15, #5, #13 +- 138: b35370a3 bfxil x3, x5, #19, #10 +- 13c: d3510b8c ubfiz x12, x28, #47, #3 +- 140: 13960c0f extr w15, w0, w22, #3 +- 144: 93ceddc6 ror x6, x14, #55 +- 148: 54000000 b.eq 148 // b.none +- 14c: 54fff5a0 b.eq 0 // b.none +- 150: 54003880 b.eq 860 // b.none +- 154: 54000001 b.ne 154 // b.any +- 158: 54fff541 b.ne 0 // b.any +- 15c: 54003821 b.ne 860 // b.any +- 160: 54000002 b.cs 160 // b.hs, b.nlast +- 164: 54fff4e2 b.cs 0 // b.hs, b.nlast +- 168: 540037c2 b.cs 860 // b.hs, b.nlast +- 16c: 54000002 b.cs 16c // b.hs, b.nlast +- 170: 54fff482 b.cs 0 // b.hs, b.nlast +- 174: 54003762 b.cs 860 // b.hs, b.nlast +- 178: 54000003 b.cc 178 // b.lo, b.ul, b.last +- 17c: 54fff423 b.cc 0 // b.lo, b.ul, b.last +- 180: 54003703 b.cc 860 // b.lo, b.ul, b.last +- 184: 54000003 b.cc 184 // b.lo, b.ul, b.last +- 188: 54fff3c3 b.cc 0 // b.lo, b.ul, b.last +- 18c: 540036a3 b.cc 860 // b.lo, b.ul, b.last +- 190: 54000004 b.mi 190 // b.first +- 194: 54fff364 b.mi 0 // b.first +- 198: 54003644 b.mi 860 // b.first +- 19c: 54000005 b.pl 19c // b.nfrst +- 1a0: 54fff305 b.pl 0 // b.nfrst +- 1a4: 540035e5 b.pl 860 // b.nfrst +- 1a8: 54000006 b.vs 1a8 +- 1ac: 54fff2a6 b.vs 0 +- 1b0: 54003586 b.vs 860 +- 1b4: 54000007 b.vc 1b4 +- 1b8: 54fff247 b.vc 0 +- 1bc: 54003527 b.vc 860 +- 1c0: 54000008 b.hi 1c0 // b.pmore +- 1c4: 54fff1e8 b.hi 0 // b.pmore +- 1c8: 540034c8 b.hi 860 // b.pmore +- 1cc: 54000009 b.ls 1cc // b.plast +- 1d0: 54fff189 b.ls 0 // b.plast +- 1d4: 54003469 b.ls 860 // b.plast +- 1d8: 5400000a b.ge 1d8 // b.tcont +- 1dc: 54fff12a b.ge 0 // b.tcont +- 1e0: 5400340a b.ge 860 // b.tcont +- 1e4: 5400000b b.lt 1e4 // b.tstop +- 1e8: 54fff0cb b.lt 0 // b.tstop +- 1ec: 540033ab b.lt 860 // b.tstop +- 1f0: 5400000c b.gt 1f0 +- 1f4: 54fff06c b.gt 0 +- 1f8: 5400334c b.gt 860 +- 1fc: 5400000d b.le 1fc +- 200: 54fff00d b.le 0 +- 204: 540032ed b.le 860 +- 208: 5400000e b.al 208 +- 20c: 54ffefae b.al 0 +- 210: 5400328e b.al 860 +- 214: 5400000f b.nv 214 +- 218: 54ffef4f b.nv 0 +- 21c: 5400322f b.nv 860 +- 220: d40ac601 svc #0x5630 +- 224: d40042a2 hvc #0x215 +- 228: d404dac3 smc #0x26d6 +- 22c: d4224d40 brk #0x126a +- 230: d44219c0 hlt #0x10ce +- 234: d503201f nop +- 238: d69f03e0 eret +- 23c: d6bf03e0 drps +- 240: d5033fdf isb +- 244: d503339f dsb osh +- 248: d50335bf dmb nshld +- 24c: d61f0280 br x20 +- 250: d63f0040 blr x2 +- 254: c8127c17 stxr w18, x23, [x0] +- 258: c81efec5 stlxr w30, x5, [x22] +- 25c: c85f7d05 ldxr x5, [x8] +- 260: c85ffe14 ldaxr x20, [x16] +- 264: c89ffd66 stlr x6, [x11] +- 268: c8dfff66 ldar x6, [x27] +- 26c: 880a7cb1 stxr w10, w17, [x5] +- 270: 8816fd89 stlxr w22, w9, [x12] +- 274: 885f7d1b ldxr w27, [x8] +- 278: 885ffc57 ldaxr w23, [x2] +- 27c: 889fffba stlr w26, [x29] +- 280: 88dffd4d ldar w13, [x10] +- 284: 48197f7c stxrh w25, w28, [x27] +- 288: 481dfd96 stlxrh w29, w22, [x12] +- 28c: 485f7f96 ldxrh w22, [x28] +- 290: 485fffc3 ldaxrh w3, [x30] +- 294: 489ffdf8 stlrh w24, [x15] +- 298: 48dfff5b ldarh w27, [x26] +- 29c: 080b7e6a stxrb w11, w10, [x19] +- 2a0: 0817fedb stlxrb w23, w27, [x22] +- 2a4: 085f7e18 ldxrb w24, [x16] +- 2a8: 085ffc38 ldaxrb w24, [x1] +- 2ac: 089fffa5 stlrb w5, [x29] +- 2b0: 08dffe18 ldarb w24, [x16] +- 2b4: c87f6239 ldxp x25, x24, [x17] +- 2b8: c87fb276 ldaxp x22, x12, [x19] +- 2bc: c820573a stxp w0, x26, x21, [x25] +- 2c0: c821aca6 stlxp w1, x6, x11, [x5] +- 2c4: 887f388d ldxp w13, w14, [x4] +- 2c8: 887f88d1 ldaxp w17, w2, [x6] +- 2cc: 882f2643 stxp w15, w3, w9, [x18] +- 2d0: 88329131 stlxp w18, w17, w4, [x9] +- 2d4: f81cf2b7 stur x23, [x21, #-49] +- 2d8: b803f055 stur w21, [x2, #63] +- 2dc: 39002f9b strb w27, [x28, #11] +- 2e0: 781f31fd sturh w29, [x15, #-13] +- 2e4: f85d33ce ldur x14, [x30, #-45] +- 2e8: b843539d ldur w29, [x28, #53] +- 2ec: 39401f54 ldrb w20, [x26, #7] +- 2f0: 785ce059 ldurh w25, [x2, #-50] +- 2f4: 389f1143 ldursb x3, [x10, #-15] +- 2f8: 788131ee ldursh x14, [x15, #19] +- 2fc: 78dfb17d ldursh w29, [x11, #-5] +- 300: b89b90af ldursw x15, [x5, #-71] +- 304: fc403193 ldur d19, [x12, #3] +- 308: bc42a36c ldur s12, [x27, #42] +- 30c: fc07d396 stur d22, [x28, #125] +- 310: bc1ec1f8 stur s24, [x15, #-20] +- 314: f81e8f88 str x8, [x28, #-24]! +- 318: b8025de6 str w6, [x15, #37]! +- 31c: 38007c27 strb w7, [x1, #7]! +- 320: 7801ee20 strh w0, [x17, #30]! +- 324: f8454fb9 ldr x25, [x29, #84]! +- 328: b85cce9a ldr w26, [x20, #-52]! +- 32c: 385e7fba ldrb w26, [x29, #-25]! +- 330: 7841af24 ldrh w4, [x25, #26]! +- 334: 389ebd1c ldrsb x28, [x8, #-21]! +- 338: 789fadd1 ldrsh x17, [x14, #-6]! +- 33c: 78c0aefc ldrsh w28, [x23, #10]! +- 340: b89c0f7e ldrsw x30, [x27, #-64]! +- 344: fc50efd4 ldr d20, [x30, #-242]! +- 348: bc414f71 ldr s17, [x27, #20]! +- 34c: fc011c67 str d7, [x3, #17]! +- 350: bc1f0d6d str s13, [x11, #-16]! +- 354: f81c3526 str x6, [x9], #-61 +- 358: b81e34b0 str w16, [x5], #-29 +- 35c: 3800f7bd strb w29, [x29], #15 +- 360: 78012684 strh w4, [x20], #18 +- 364: f842e653 ldr x19, [x18], #46 +- 368: b8417456 ldr w22, [x2], #23 +- 36c: 385e2467 ldrb w7, [x3], #-30 +- 370: 785e358b ldrh w11, [x12], #-29 +- 374: 389e34c8 ldrsb x8, [x6], #-29 +- 378: 788046f8 ldrsh x24, [x23], #4 +- 37c: 78c00611 ldrsh w17, [x16], #0 +- 380: b89f8680 ldrsw x0, [x20], #-8 +- 384: fc582454 ldr d20, [x2], #-126 +- 388: bc5987d3 ldr s19, [x30], #-104 +- 38c: fc076624 str d4, [x17], #118 +- 390: bc190675 str s21, [x19], #-112 +- 394: f833785a str x26, [x2, x19, lsl #3] +- 398: b82fd809 str w9, [x0, w15, sxtw #2] +- 39c: 3821799a strb w26, [x12, x1, lsl #0] +- 3a0: 782a7975 strh w21, [x11, x10, lsl #1] +- 3a4: f870eaf0 ldr x16, [x23, x16, sxtx] +- 3a8: b871d96a ldr w10, [x11, w17, sxtw #2] +- 3ac: 386b7aed ldrb w13, [x23, x11, lsl #0] +- 3b0: 7875689b ldrh w27, [x4, x21] +- 3b4: 38afd91a ldrsb x26, [x8, w15, sxtw #0] +- 3b8: 78a2c955 ldrsh x21, [x10, w2, sxtw] +- 3bc: 78ee6bc8 ldrsh w8, [x30, x14] +- 3c0: b8b4f9dd ldrsw x29, [x14, x20, sxtx #2] +- 3c4: fc76eb7e ldr d30, [x27, x22, sxtx] +- 3c8: bc76692d ldr s13, [x9, x22] +- 3cc: fc31db28 str d8, [x25, w17, sxtw #3] +- 3d0: bc255b01 str s1, [x24, w5, uxtw #2] +- 3d4: f91c52aa str x10, [x21, #14496] +- 3d8: b91c3fb2 str w18, [x29, #7228] +- 3dc: 391f8877 strb w23, [x3, #2018] +- 3e0: 791ac97c strh w28, [x11, #3428] +- 3e4: f95c1758 ldr x24, [x26, #14376] +- 3e8: b95b3c55 ldr w21, [x2, #6972] +- 3ec: 395ce0a4 ldrb w4, [x5, #1848] +- 3f0: 795851ce ldrh w14, [x14, #3112] +- 3f4: 399e9f64 ldrsb x4, [x27, #1959] +- 3f8: 79993764 ldrsh x4, [x27, #3226] +- 3fc: 79d9af8a ldrsh w10, [x28, #3286] +- 400: b99eea2a ldrsw x10, [x17, #7912] +- 404: fd5a2f8d ldr d13, [x28, #13400] +- 408: bd5dac78 ldr s24, [x3, #7596] +- 40c: fd1e0182 str d2, [x12, #15360] +- 410: bd195c31 str s17, [x1, #6492] +- 414: 58000010 ldr x16, 414 +- 418: 1800000d ldr w13, 418 +- 41c: f8981240 prfum pldl1keep, [x18, #-127] +- 420: d8ffdf00 prfm pldl1keep, 0 +- 424: f8a27a80 prfm pldl1keep, [x20, x2, lsl #3] +- 428: f99af920 prfm pldl1keep, [x9, #13808] +- 42c: 1a0202e8 adc w8, w23, w2 +- 430: 3a130078 adcs w24, w3, w19 +- 434: 5a1d0316 sbc w22, w24, w29 +- 438: 7a03036c sbcs w12, w27, w3 +- 43c: 9a0102eb adc x11, x23, x1 +- 440: ba1700bd adcs x29, x5, x23 +- 444: da0c0329 sbc x9, x25, x12 +- 448: fa16000c sbcs x12, x0, x22 +- 44c: 0b23459a add w26, w12, w3, uxtw #1 +- 450: 2b328a14 adds w20, w16, w18, sxtb #2 +- 454: cb274bde sub x30, x30, w7, uxtw #2 +- 458: 6b222eab subs w11, w21, w2, uxth #3 +- 45c: 8b214b42 add x2, x26, w1, uxtw #2 +- 460: ab34a7b2 adds x18, x29, w20, sxth #1 +- 464: cb24520e sub x14, x16, w4, uxtw #4 +- 468: eb378e20 subs x0, x17, w23, sxtb #3 +- 46c: 3a565283 ccmn w20, w22, #0x3, pl // pl = nfrst +- 470: 7a420321 ccmp w25, w2, #0x1, eq // eq = none +- 474: ba58c247 ccmn x18, x24, #0x7, gt +- 478: fa4d5106 ccmp x8, x13, #0x6, pl // pl = nfrst +- 47c: 3a426924 ccmn w9, #0x2, #0x4, vs +- 480: 7a5b0847 ccmp w2, #0x1b, #0x7, eq // eq = none +- 484: ba413a02 ccmn x16, #0x1, #0x2, cc // cc = lo, ul, last +- 488: fa5fba23 ccmp x17, #0x1f, #0x3, lt // lt = tstop +- 48c: 1a979377 csel w23, w27, w23, ls // ls = plast +- 490: 1a86640a csinc w10, w0, w6, vs +- 494: 5a89300b csinv w11, w0, w9, cc // cc = lo, ul, last +- 498: 5a923771 csneg w17, w27, w18, cc // cc = lo, ul, last +- 49c: 9a8b720c csel x12, x16, x11, vc +- 4a0: 9a868786 csinc x6, x28, x6, hi // hi = pmore +- 4a4: da9a736d csinv x13, x27, x26, vc +- 4a8: da9256dd csneg x29, x22, x18, pl // pl = nfrst +- 4ac: 5ac0026c rbit w12, w19 +- 4b0: 5ac00657 rev16 w23, w18 +- 4b4: 5ac00b89 rev w9, w28 +- 4b8: 5ac01262 clz w2, w19 +- 4bc: 5ac017b9 cls w25, w29 +- 4c0: dac002e4 rbit x4, x23 +- 4c4: dac0065d rev16 x29, x18 +- 4c8: dac00907 rev32 x7, x8 +- 4cc: dac00e2d rev x13, x17 +- 4d0: dac01011 clz x17, x0 +- 4d4: dac01752 cls x18, x26 +- 4d8: 1ad0098b udiv w11, w12, w16 +- 4dc: 1ac70d24 sdiv w4, w9, w7 +- 4e0: 1ad020ec lsl w12, w7, w16 +- 4e4: 1ad72613 lsr w19, w16, w23 +- 4e8: 1ac62887 asr w7, w4, w6 +- 4ec: 1ad72e95 ror w21, w20, w23 +- 4f0: 9adc0990 udiv x16, x12, x28 +- 4f4: 9acd0d84 sdiv x4, x12, x13 +- 4f8: 9ac721a9 lsl x9, x13, x7 +- 4fc: 9acf277c lsr x28, x27, x15 +- 500: 9ace2bd4 asr x20, x30, x14 +- 504: 9ade2e4e ror x14, x18, x30 +- 508: 9bc77d63 umulh x3, x11, x7 +- 50c: 9b587e97 smulh x23, x20, x24 +- 510: 1b1524a2 madd w2, w5, w21, w9 +- 514: 1b04a318 msub w24, w24, w4, w8 +- 518: 9b0f4d8b madd x11, x12, x15, x19 +- 51c: 9b0ce73d msub x29, x25, x12, x25 +- 520: 9b2c5971 smaddl x17, w11, w12, x22 +- 524: 9b34c87c smsubl x28, w3, w20, x18 +- 528: 9bbc6887 umaddl x7, w4, w28, x26 +- 52c: 9bb19556 umsubl x22, w10, w17, x5 +- 530: 1e310871 fmul s17, s3, s17 +- 534: 1e261a2b fdiv s11, s17, s6 +- 538: 1e2928fd fadd s29, s7, s9 +- 53c: 1e333987 fsub s7, s12, s19 +- 540: 1e230ae0 fmul s0, s23, s3 +- 544: 1e75087a fmul d26, d3, d21 +- 548: 1e651a60 fdiv d0, d19, d5 +- 54c: 1e692b40 fadd d0, d26, d9 +- 550: 1e753ab9 fsub d25, d21, d21 +- 554: 1e7309b0 fmul d16, d13, d19 +- 558: 1f00425d fmadd s29, s18, s0, s16 +- 55c: 1f1d95b7 fmsub s23, s13, s29, s5 +- 560: 1f2a38e9 fnmadd s9, s7, s10, s14 +- 564: 1f2f5f99 fnmadd s25, s28, s15, s23 +- 568: 1f5545a6 fmadd d6, d13, d21, d17 +- 56c: 1f429ea3 fmsub d3, d21, d2, d7 +- 570: 1f65472a fnmadd d10, d25, d5, d17 +- 574: 1f7449ce fnmadd d14, d14, d20, d18 +- 578: 1e20404f fmov s15, s2 +- 57c: 1e20c0f2 fabs s18, s7 +- 580: 1e2140c3 fneg s3, s6 +- 584: 1e21c02c fsqrt s12, s1 +- 588: 1e22c009 fcvt d9, s0 +- 58c: 1e6040a4 fmov d4, d5 +- 590: 1e60c1e3 fabs d3, d15 +- 594: 1e614331 fneg d17, d25 +- 598: 1e61c30c fsqrt d12, d24 +- 59c: 1e6240b5 fcvt s21, d5 +- 5a0: 1e3802a4 fcvtzs w4, s21 +- 5a4: 9e38007b fcvtzs x27, s3 +- 5a8: 1e78011d fcvtzs w29, d8 +- 5ac: 9e7802a9 fcvtzs x9, d21 +- 5b0: 1e2203b4 scvtf s20, w29 +- 5b4: 9e220107 scvtf s7, x8 +- 5b8: 1e6202ac scvtf d12, w21 +- 5bc: 9e6202b0 scvtf d16, x21 +- 5c0: 1e2600b2 fmov w18, s5 +- 5c4: 9e660119 fmov x25, d8 +- 5c8: 1e270352 fmov s18, w26 +- 5cc: 9e670160 fmov d0, x11 +- 5d0: 1e262200 fcmp s16, s6 +- 5d4: 1e7d2200 fcmp d16, d29 +- 5d8: 1e2023c8 fcmp s30, #0.0 +- 5dc: 1e602128 fcmp d9, #0.0 +- 5e0: 293e119b stp w27, w4, [x12, #-16] +- 5e4: 294a2543 ldp w3, w9, [x10, #80] +- 5e8: 69480c70 ldpsw x16, x3, [x3, #64] +- 5ec: a934726a stp x10, x28, [x19, #-192] +- 5f0: a97448f3 ldp x19, x18, [x7, #-192] +- 5f4: 298243ca stp w10, w16, [x30, #16]! +- 5f8: 29e21242 ldp w2, w4, [x18, #-240]! +- 5fc: 69c64db8 ldpsw x24, x19, [x13, #48]! +- 600: a9800311 stp x17, x0, [x24, #0]! +- 604: a9f4686e ldp x14, x26, [x3, #-192]! +- 608: 288a0416 stp w22, w1, [x0], #80 +- 60c: 28fe2812 ldp w18, w10, [x0], #-16 +- 610: 68fe62d8 .inst 0x68fe62d8 ; undefined +- 614: a885308c stp x12, x12, [x4], #80 +- 618: a8f12664 ldp x4, x9, [x19], #-240 +- 61c: 282468d2 stnp w18, w26, [x6, #-224] +- 620: 284e5035 ldnp w21, w20, [x1, #112] +- 624: a8327699 stnp x25, x29, [x20, #-224] +- 628: a84716e1 ldnp x1, x5, [x23, #112] +- 62c: 0c407284 ld1 {v4.8b}, [x20] +- 630: 4cdfa158 ld1 {v24.16b, v25.16b}, [x10], #32 +- 634: 0ccf6cd8 ld1 {v24.1d-v26.1d}, [x6], x15 +- 638: 4cdf2483 ld1 {v3.8h-v6.8h}, [x4], #64 +- 63c: 0d40c0c2 ld1r {v2.8b}, [x6] +- 640: 4ddfc9cd ld1r {v13.4s}, [x14], #4 +- 644: 0dd8ceaf ld1r {v15.1d}, [x21], x24 +- 648: 4c408ea9 ld2 {v9.2d, v10.2d}, [x21] +- 64c: 0cdf86bd ld2 {v29.4h, v30.4h}, [x21], #16 +- 650: 4d60c1c8 ld2r {v8.16b, v9.16b}, [x14] +- 654: 0dffca87 ld2r {v7.2s, v8.2s}, [x20], #8 +- 658: 4de3cc7c ld2r {v28.2d, v29.2d}, [x3], x3 +- 65c: 4cdd497b ld3 {v27.4s-v29.4s}, [x11], x29 +- 660: 0c404950 ld3 {v16.2s-v18.2s}, [x10] +- 664: 4d40e595 ld3r {v21.8h-v23.8h}, [x12] +- 668: 4ddfeba4 ld3r {v4.4s-v6.4s}, [x29], #12 +- 66c: 0dd3ed38 ld3r {v24.1d-v26.1d}, [x9], x19 +- 670: 4cdf046a ld4 {v10.8h-v13.8h}, [x3], #64 +- 674: 0cc9039b ld4 {v27.8b-v30.8b}, [x28], x9 +- 678: 0d60e3d5 ld4r {v21.8b-v24.8b}, [x30] +- 67c: 0dffe5d7 ld4r {v23.4h-v26.4h}, [x14], #8 +- 680: 0df4e9a4 ld4r {v4.2s-v7.2s}, [x13], x20 +- 684: ba5fd3e3 ccmn xzr, xzr, #0x3, le +- 688: 3a5f03e5 ccmn wzr, wzr, #0x5, eq // eq = none +- 68c: fa411be4 ccmp xzr, #0x1, #0x4, ne // ne = any +- 690: 7a42cbe2 ccmp wzr, #0x2, #0x2, gt +- 694: 93df03ff ror xzr, xzr, #0 +- 698: c820ffff stlxp w0, xzr, xzr, [sp] +- 69c: 8822fc7f stlxp w2, wzr, wzr, [x3] +- 6a0: c8247cbf stxp w4, xzr, xzr, [x5] +- 6a4: 88267fff stxp w6, wzr, wzr, [sp] +- 6a8: 4e010fe0 dup v0.16b, wzr +- 6ac: 4e081fe1 mov v1.d[0], xzr +- 6b0: 4e0c1fe1 mov v1.s[1], wzr +- 6b4: 4e0a1fe1 mov v1.h[2], wzr +- 6b8: 4e071fe1 mov v1.b[3], wzr +- 6bc: 4cc0ac3f ld1 {v31.2d, v0.2d}, [x1], x0 +- 6c0: 1e601000 fmov d0, #2.000000000000000000e+00 +- 6c4: 1e603000 fmov d0, #2.125000000000000000e+00 +- 6c8: 1e621000 fmov d0, #4.000000000000000000e+00 +- 6cc: 1e623000 fmov d0, #4.250000000000000000e+00 +- 6d0: 1e641000 fmov d0, #8.000000000000000000e+00 +- 6d4: 1e643000 fmov d0, #8.500000000000000000e+00 +- 6d8: 1e661000 fmov d0, #1.600000000000000000e+01 +- 6dc: 1e663000 fmov d0, #1.700000000000000000e+01 +- 6e0: 1e681000 fmov d0, #1.250000000000000000e-01 +- 6e4: 1e683000 fmov d0, #1.328125000000000000e-01 +- 6e8: 1e6a1000 fmov d0, #2.500000000000000000e-01 +- 6ec: 1e6a3000 fmov d0, #2.656250000000000000e-01 +- 6f0: 1e6c1000 fmov d0, #5.000000000000000000e-01 +- 6f4: 1e6c3000 fmov d0, #5.312500000000000000e-01 +- 6f8: 1e6e1000 fmov d0, #1.000000000000000000e+00 +- 6fc: 1e6e3000 fmov d0, #1.062500000000000000e+00 +- 700: 1e701000 fmov d0, #-2.000000000000000000e+00 +- 704: 1e703000 fmov d0, #-2.125000000000000000e+00 +- 708: 1e721000 fmov d0, #-4.000000000000000000e+00 +- 70c: 1e723000 fmov d0, #-4.250000000000000000e+00 +- 710: 1e741000 fmov d0, #-8.000000000000000000e+00 +- 714: 1e743000 fmov d0, #-8.500000000000000000e+00 +- 718: 1e761000 fmov d0, #-1.600000000000000000e+01 +- 71c: 1e763000 fmov d0, #-1.700000000000000000e+01 +- 720: 1e781000 fmov d0, #-1.250000000000000000e-01 +- 724: 1e783000 fmov d0, #-1.328125000000000000e-01 +- 728: 1e7a1000 fmov d0, #-2.500000000000000000e-01 +- 72c: 1e7a3000 fmov d0, #-2.656250000000000000e-01 +- 730: 1e7c1000 fmov d0, #-5.000000000000000000e-01 +- 734: 1e7c3000 fmov d0, #-5.312500000000000000e-01 +- 738: 1e7e1000 fmov d0, #-1.000000000000000000e+00 +- 73c: 1e7e3000 fmov d0, #-1.062500000000000000e+00 +- 740: f8358305 swp x21, x5, [x24] +- 744: f82d01ed ldadd x13, x13, [x15] +- 748: f8361353 ldclr x22, x19, [x26] +- 74c: f839234a ldeor x25, x10, [x26] +- 750: f82531fb ldset x5, x27, [x15] +- 754: f8335165 ldsmin x19, x5, [x11] +- 758: f83a4080 ldsmax x26, x0, [x4] +- 75c: f83673d7 ldumin x22, x23, [x30] +- 760: f832611c ldumax x18, x28, [x8] +- 764: f8ad837d swpa x13, x29, [x27] +- 768: f8ab01a5 ldadda x11, x5, [x13] +- 76c: f8a112b8 ldclra x1, x24, [x21] +- 770: f8bb2311 ldeora x27, x17, [x24] +- 774: f8b230be ldseta x18, x30, [x5] +- 778: f8a75336 ldsmina x7, x22, [x25] +- 77c: f8a4427a ldsmaxa x4, x26, [x19] +- 780: f8a6707e ldumina x6, x30, [x3] +- 784: f8b860b7 ldumaxa x24, x23, [x5] +- 788: f8f88392 swpal x24, x18, [x28] +- 78c: f8f300ff ldaddal x19, xzr, [x7] +- 790: f8ed1386 ldclral x13, x6, [x28] +- 794: f8e822af ldeoral x8, x15, [x21] +- 798: f8e2302d ldsetal x2, x13, [x1] +- 79c: f8f1533d ldsminal x17, x29, [x25] +- 7a0: f8f941d2 ldsmaxal x25, x18, [x14] +- 7a4: f8ff7366 lduminal xzr, x6, [x27] +- 7a8: f8f061e5 ldumaxal x16, x5, [x15] +- 7ac: f86b8072 swpl x11, x18, [x3] +- 7b0: f87a0054 ldaddl x26, x20, [x2] +- 7b4: f86b1164 ldclrl x11, x4, [x11] +- 7b8: f87e22f3 ldeorl x30, x19, [x23] +- 7bc: f86331cf ldsetl x3, x15, [x14] +- 7c0: f87e5296 ldsminl x30, x22, [x20] +- 7c4: f8674305 ldsmaxl x7, x5, [x24] +- 7c8: f87771f0 lduminl x23, x16, [x15] +- 7cc: f86b6013 ldumaxl x11, x19, [x0] +- 7d0: b83c803c swp w28, w28, [x1] +- 7d4: b82b0195 ldadd w11, w21, [x12] +- 7d8: b83d1240 ldclr w29, w0, [x18] +- 7dc: b8252320 ldeor w5, w0, [x25] +- 7e0: b82e3340 ldset w14, w0, [x26] +- 7e4: b83c53b2 ldsmin w28, w18, [x29] +- 7e8: b82f43a1 ldsmax w15, w1, [x29] +- 7ec: b828739a ldumin w8, w26, [x28] +- 7f0: b831608e ldumax w17, w14, [x4] +- 7f4: b8b88039 swpa w24, w25, [x1] +- 7f8: b8aa0231 ldadda w10, w17, [x17] +- 7fc: b8bd12b4 ldclra w29, w20, [x21] +- 800: b8bd2189 ldeora w29, w9, [x12] +- 804: b8ab30a6 ldseta w11, w6, [x5] +- 808: b8b552a7 ldsmina w21, w7, [x21] +- 80c: b8aa4197 ldsmaxa w10, w23, [x12] +- 810: b8b57145 ldumina w21, w5, [x10] +- 814: b8be6254 ldumaxa w30, w20, [x18] +- 818: b8ed80b7 swpal w13, w23, [x5] +- 81c: b8ef00b8 ldaddal w15, w24, [x5] +- 820: b8e9132a ldclral w9, w10, [x25] +- 824: b8f42231 ldeoral w20, w17, [x17] +- 828: b8ec33d2 ldsetal w12, w18, [x30] +- 82c: b8e35323 ldsminal w3, w3, [x25] +- 830: b8fa4159 ldsmaxal w26, w25, [x10] +- 834: b8e273eb lduminal w2, w11, [sp] +- 838: b8e760a2 ldumaxal w7, w2, [x5] +- 83c: b8608287 swpl w0, w7, [x20] +- 840: b865005f staddl w5, [x2] +- 844: b87b1379 ldclrl w27, w25, [x27] +- 848: b87e2358 ldeorl w30, w24, [x26] +- 84c: b86f32c2 ldsetl w15, w2, [x22] +- 850: b86053e3 ldsminl w0, w3, [sp] +- 854: b86f4154 ldsmaxl w15, w20, [x10] +- 858: b87671d5 lduminl w22, w21, [x14] +- 85c: b866605e ldumaxl w6, w30, [x2] ++ 0: 8b4db437 add x23, x1, x13, lsr #45 ++ 4: cb8ce3c8 sub x8, x30, x12, asr #56 ++ 8: ab0edafb adds x27, x23, x14, lsl #54 ++ c: eb5499f5 subs x21, x15, x20, lsr #38 ++ 10: 0b040e39 add w25, w17, w4, lsl #3 ++ 14: 4b89503d sub w29, w1, w9, asr #20 ++ 18: 2b89274a adds w10, w26, w9, asr #9 ++ 1c: 6b870fd5 subs w21, w30, w7, asr #3 ++ 20: 8a4b1109 and x9, x8, x11, lsr #4 ++ 24: aa810643 orr x3, x18, x1, asr #1 ++ 28: ca026e8a eor x10, x20, x2, lsl #27 ++ 2c: ea8b7d2c ands x12, x9, x11, asr #31 ++ 30: 0a9e6934 and w20, w9, w30, asr #26 ++ 34: 2a9a4555 orr w21, w10, w26, asr #17 ++ 38: 4a871d00 eor w0, w8, w7, asr #7 ++ 3c: 6a084973 ands w19, w11, w8, lsl #18 ++ 40: 8a23d497 bic x23, x4, x3, lsl #53 ++ 44: aa3360c9 orn x9, x6, x19, lsl #24 ++ 48: ca7ad8cc eon x12, x6, x26, lsr #54 ++ 4c: ea2c3a76 bics x22, x19, x12, lsl #14 ++ 50: 0a362dbd bic w29, w13, w22, lsl #11 ++ 54: 2ab417d1 orn w17, w30, w20, asr #5 ++ 58: 4a2b23a1 eon w1, w29, w11, lsl #8 ++ 5c: 6a667684 bics w4, w20, w6, lsr #29 ++ 60: 1107e0de add w30, w6, #0x1f8 ++ 64: 310ebd13 adds w19, w8, #0x3af ++ 68: 5105b55d sub w29, w10, #0x16d ++ 6c: 71047104 subs w4, w8, #0x11c ++ 70: 910ef9c3 add x3, x14, #0x3be ++ 74: b1029e96 adds x22, x20, #0xa7 ++ 78: d10b55fb sub x27, x15, #0x2d5 ++ 7c: f10ecf98 subs x24, x28, #0x3b3 ++ 80: 12099f39 and w25, w25, #0x7f807f80 ++ 84: 321b3f4d orr w13, w26, #0x1fffe0 ++ 88: 520309b5 eor w21, w13, #0xe0000000 ++ 8c: 72134062 ands w2, w3, #0x3fffe000 ++ 90: 92004548 and x8, x10, #0x3ffff0003ffff ++ 94: b24d861b orr x27, x16, #0xfff80000001fffff ++ 98: d219587b eor x27, x3, #0x3fffff803fffff80 ++ 9c: f25eaee4 ands x4, x23, #0xfffffffc00003fff + a0: 14000000 b a0 + a4: 17ffffd7 b 0 -+ a8: 140001cf b 7e4 ++ a8: 140001ee b 860 + ac: 94000000 bl ac + b0: 97ffffd4 bl 0 -+ b4: 940001cc bl 7e4 -+ b8: 3400000a cbz w10, b8 -+ bc: 34fffa2a cbz w10, 0 -+ c0: 3400392a cbz w10, 7e4 -+ c4: 35000008 cbnz w8, c4 -+ c8: 35fff9c8 cbnz w8, 0 -+ cc: 350038c8 cbnz w8, 7e4 -+ d0: b400000b cbz x11, d0 -+ d4: b4fff96b cbz x11, 0 -+ d8: b400386b cbz x11, 7e4 -+ dc: b500001d cbnz x29, dc -+ e0: b5fff91d cbnz x29, 0 -+ e4: b500381d cbnz x29, 7e4 -+ e8: 10000013 adr x19, e8 -+ ec: 10fff8b3 adr x19, 0 -+ f0: 100037b3 adr x19, 7e4 -+ f4: 90000013 adrp x19, 0 -+ f8: 36300016 tbz w22, #6, f8 -+ fc: 3637f836 tbz w22, #6, 0 -+ 100: 36303736 tbz w22, #6, 7e4 -+ 104: 3758000c tbnz w12, #11, 104 -+ 108: 375ff7cc tbnz w12, #11, 0 -+ 10c: 375836cc tbnz w12, #11, 7e4 -+ 110: 128313a0 mov w0, #0xffffe762 // #-6302 -+ 114: 528a32c7 mov w7, #0x5196 // #20886 -+ 118: 7289173b movk w27, #0x48b9 -+ 11c: 92ab3acc mov x12, #0xffffffffa629ffff // #-1507196929 -+ 120: d2a0bf94 mov x20, #0x5fc0000 // #100401152 -+ 124: f2c285e8 movk x8, #0x142f, lsl #32 -+ 128: 9358722f sbfx x15, x17, #24, #5 -+ 12c: 330e652f bfxil w15, w9, #14, #12 -+ 130: 53067f3b lsr w27, w25, #6 -+ 134: 93577c53 sbfx x19, x2, #23, #9 -+ 138: b34a1aac bfi x12, x21, #54, #7 -+ 13c: d35a4016 ubfiz x22, x0, #38, #17 -+ 140: 13946c63 extr w3, w3, w20, #27 -+ 144: 93c3dbc8 extr x8, x30, x3, #54 ++ b4: 940001eb bl 860 ++ b8: 34000003 cbz w3, b8 ++ bc: 34fffa23 cbz w3, 0 ++ c0: 34003d03 cbz w3, 860 ++ c4: 35000002 cbnz w2, c4 ++ c8: 35fff9c2 cbnz w2, 0 ++ cc: 35003ca2 cbnz w2, 860 ++ d0: b4000019 cbz x25, d0 ++ d4: b4fff979 cbz x25, 0 ++ d8: b4003c59 cbz x25, 860 ++ dc: b5000012 cbnz x18, dc ++ e0: b5fff912 cbnz x18, 0 ++ e4: b5003bf2 cbnz x18, 860 ++ e8: 10000008 adr x8, e8 ++ ec: 10fff8a8 adr x8, 0 ++ f0: 10003b88 adr x8, 860 ++ f4: 9000000f adrp x15, 0 ++ f8: 36700012 tbz w18, #14, f8 ++ fc: 3677f832 tbz w18, #14, 0 ++ 100: 36703b12 tbz w18, #14, 860 ++ 104: 37780019 tbnz w25, #15, 104 ++ 108: 377ff7d9 tbnz w25, #15, 0 ++ 10c: 37783ab9 tbnz w25, #15, 860 ++ 110: 12a203d2 mov w18, #0xefe1ffff // #-270401537 ++ 114: 5286b21e mov w30, #0x3590 // #13712 ++ 118: 72a66d35 movk w21, #0x3369, lsl #16 ++ 11c: 92eded92 mov x18, #0x9093ffffffffffff // #-8028792235694751745 ++ 120: d2eefecd mov x13, #0x77f6000000000000 // #8644096534784245760 ++ 124: f2ef69a3 movk x3, #0x7b4d, lsl #48 ++ 128: 93400c2a sbfx x10, x1, #0, #4 ++ 12c: 330562cc bfxil w12, w22, #5, #20 ++ 130: 530b2071 ubfiz w17, w3, #21, #9 ++ 134: 934b3860 sbfx x0, x3, #11, #4 ++ 138: b3473cdc bfxil x28, x6, #7, #9 ++ 13c: d3416549 ubfx x9, x10, #1, #25 ++ 140: 13995f75 extr w21, w27, w25, #23 ++ 144: 93d6462e extr x14, x17, x22, #17 + 148: 54000000 b.eq 148 // b.none + 14c: 54fff5a0 b.eq 0 // b.none -+ 150: 540034a0 b.eq 7e4 // b.none ++ 150: 54003880 b.eq 860 // b.none + 154: 54000001 b.ne 154 // b.any + 158: 54fff541 b.ne 0 // b.any -+ 15c: 54003441 b.ne 7e4 // b.any ++ 15c: 54003821 b.ne 860 // b.any + 160: 54000002 b.cs 160 // b.hs, b.nlast + 164: 54fff4e2 b.cs 0 // b.hs, b.nlast -+ 168: 540033e2 b.cs 7e4 // b.hs, b.nlast ++ 168: 540037c2 b.cs 860 // b.hs, b.nlast + 16c: 54000002 b.cs 16c // b.hs, b.nlast + 170: 54fff482 b.cs 0 // b.hs, b.nlast -+ 174: 54003382 b.cs 7e4 // b.hs, b.nlast ++ 174: 54003762 b.cs 860 // b.hs, b.nlast + 178: 54000003 b.cc 178 // b.lo, b.ul, b.last + 17c: 54fff423 b.cc 0 // b.lo, b.ul, b.last -+ 180: 54003323 b.cc 7e4 // b.lo, b.ul, b.last ++ 180: 54003703 b.cc 860 // b.lo, b.ul, b.last + 184: 54000003 b.cc 184 // b.lo, b.ul, b.last + 188: 54fff3c3 b.cc 0 // b.lo, b.ul, b.last -+ 18c: 540032c3 b.cc 7e4 // b.lo, b.ul, b.last ++ 18c: 540036a3 b.cc 860 // b.lo, b.ul, b.last + 190: 54000004 b.mi 190 // b.first + 194: 54fff364 b.mi 0 // b.first -+ 198: 54003264 b.mi 7e4 // b.first ++ 198: 54003644 b.mi 860 // b.first + 19c: 54000005 b.pl 19c // b.nfrst + 1a0: 54fff305 b.pl 0 // b.nfrst -+ 1a4: 54003205 b.pl 7e4 // b.nfrst ++ 1a4: 540035e5 b.pl 860 // b.nfrst + 1a8: 54000006 b.vs 1a8 + 1ac: 54fff2a6 b.vs 0 -+ 1b0: 540031a6 b.vs 7e4 ++ 1b0: 54003586 b.vs 860 + 1b4: 54000007 b.vc 1b4 + 1b8: 54fff247 b.vc 0 -+ 1bc: 54003147 b.vc 7e4 ++ 1bc: 54003527 b.vc 860 + 1c0: 54000008 b.hi 1c0 // b.pmore + 1c4: 54fff1e8 b.hi 0 // b.pmore -+ 1c8: 540030e8 b.hi 7e4 // b.pmore ++ 1c8: 540034c8 b.hi 860 // b.pmore + 1cc: 54000009 b.ls 1cc // b.plast + 1d0: 54fff189 b.ls 0 // b.plast -+ 1d4: 54003089 b.ls 7e4 // b.plast ++ 1d4: 54003469 b.ls 860 // b.plast + 1d8: 5400000a b.ge 1d8 // b.tcont + 1dc: 54fff12a b.ge 0 // b.tcont -+ 1e0: 5400302a b.ge 7e4 // b.tcont ++ 1e0: 5400340a b.ge 860 // b.tcont + 1e4: 5400000b b.lt 1e4 // b.tstop + 1e8: 54fff0cb b.lt 0 // b.tstop -+ 1ec: 54002fcb b.lt 7e4 // b.tstop ++ 1ec: 540033ab b.lt 860 // b.tstop + 1f0: 5400000c b.gt 1f0 + 1f4: 54fff06c b.gt 0 -+ 1f8: 54002f6c b.gt 7e4 ++ 1f8: 5400334c b.gt 860 + 1fc: 5400000d b.le 1fc + 200: 54fff00d b.le 0 -+ 204: 54002f0d b.le 7e4 ++ 204: 540032ed b.le 860 + 208: 5400000e b.al 208 + 20c: 54ffefae b.al 0 -+ 210: 54002eae b.al 7e4 ++ 210: 5400328e b.al 860 + 214: 5400000f b.nv 214 + 218: 54ffef4f b.nv 0 -+ 21c: 54002e4f b.nv 7e4 -+ 220: d40658e1 svc #0x32c7 -+ 224: d4014d22 hvc #0xa69 -+ 228: d4046543 smc #0x232a -+ 22c: d4273f60 brk #0x39fb -+ 230: d44cad80 hlt #0x656c ++ 21c: 5400322f b.nv 860 ++ 220: d40f9ca1 svc #0x7ce5 ++ 224: d4008b22 hvc #0x459 ++ 228: d40be1c3 smc #0x5f0e ++ 22c: d423d0e0 brk #0x1e87 ++ 230: d44dee20 hlt #0x6f71 + 234: d503201f nop + 238: d69f03e0 eret + 23c: d6bf03e0 drps + 240: d5033fdf isb -+ 244: d5033e9f dsb st -+ 248: d50332bf dmb oshst -+ 24c: d61f0200 br x16 -+ 250: d63f0280 blr x20 -+ 254: c80a7d1b stxr w10, x27, [x8] -+ 258: c800fea1 stlxr w0, x1, [x21] -+ 25c: c85f7fb1 ldxr x17, [x29] -+ 260: c85fff9d ldaxr x29, [x28] -+ 264: c89ffee1 stlr x1, [x23] -+ 268: c8dffe95 ldar x21, [x20] -+ 26c: 88167e7b stxr w22, w27, [x19] -+ 270: 880bfcd0 stlxr w11, w16, [x6] -+ 274: 885f7c12 ldxr w18, [x0] -+ 278: 885ffd44 ldaxr w4, [x10] -+ 27c: 889ffed8 stlr w24, [x22] -+ 280: 88dffe6a ldar w10, [x19] -+ 284: 48017fc5 stxrh w1, w5, [x30] -+ 288: 4808fe2c stlxrh w8, w12, [x17] -+ 28c: 485f7dc9 ldxrh w9, [x14] -+ 290: 485ffc27 ldaxrh w7, [x1] -+ 294: 489ffe05 stlrh w5, [x16] -+ 298: 48dffd82 ldarh w2, [x12] -+ 29c: 080a7c6c stxrb w10, w12, [x3] -+ 2a0: 081cff4e stlxrb w28, w14, [x26] -+ 2a4: 085f7d5e ldxrb w30, [x10] -+ 2a8: 085ffeae ldaxrb w14, [x21] -+ 2ac: 089ffd2d stlrb w13, [x9] -+ 2b0: 08dfff76 ldarb w22, [x27] -+ 2b4: c87f4d7c ldxp x28, x19, [x11] -+ 2b8: c87fcc5e ldaxp x30, x19, [x2] -+ 2bc: c8220417 stxp w2, x23, x1, [x0] -+ 2c0: c82cb5f0 stlxp w12, x16, x13, [x15] -+ 2c4: 887f55b2 ldxp w18, w21, [x13] -+ 2c8: 887ff90b ldaxp w11, w30, [x8] -+ 2cc: 88382c2d stxp w24, w13, w11, [x1] -+ 2d0: 883aedb5 stlxp w26, w21, w27, [x13] -+ 2d4: f819928b stur x11, [x20, #-103] -+ 2d8: b803e21c stur w28, [x16, #62] -+ 2dc: 381f713b sturb w27, [x9, #-9] -+ 2e0: 781ce322 sturh w2, [x25, #-50] -+ 2e4: f850f044 ldur x4, [x2, #-241] -+ 2e8: b85e129e ldur w30, [x20, #-31] -+ 2ec: 385e92f2 ldurb w18, [x23, #-23] -+ 2f0: 785ff35d ldurh w29, [x26, #-1] -+ 2f4: 39801921 ldrsb x1, [x9, #6] -+ 2f8: 7881318b ldursh x11, [x12, #19] -+ 2fc: 78dce02b ldursh w11, [x1, #-50] -+ 300: b8829313 ldursw x19, [x24, #41] -+ 304: fc45f318 ldur d24, [x24, #95] -+ 308: bc5d50af ldur s15, [x5, #-43] -+ 30c: fc001375 stur d21, [x27, #1] -+ 310: bc1951b7 stur s23, [x13, #-107] -+ 314: f8008c0b str x11, [x0, #8]! -+ 318: b801dc03 str w3, [x0, #29]! -+ 31c: 38009dcb strb w11, [x14, #9]! -+ 320: 781fdf1d strh w29, [x24, #-3]! -+ 324: f8570e2d ldr x13, [x17, #-144]! -+ 328: b85faecc ldr w12, [x22, #-6]! -+ 32c: 385f6d8d ldrb w13, [x12, #-10]! -+ 330: 785ebea0 ldrh w0, [x21, #-21]! -+ 334: 38804cf7 ldrsb x23, [x7, #4]! -+ 338: 789cbce3 ldrsh x3, [x7, #-53]! -+ 33c: 78df9cbc ldrsh w28, [x5, #-7]! -+ 340: b89eed38 ldrsw x24, [x9, #-18]! -+ 344: fc40cd6e ldr d14, [x11, #12]! -+ 348: bc5bdd93 ldr s19, [x12, #-67]! -+ 34c: fc103c14 str d20, [x0, #-253]! -+ 350: bc040c08 str s8, [x0, #64]! -+ 354: f81a2784 str x4, [x28], #-94 -+ 358: b81ca4ec str w12, [x7], #-54 -+ 35c: 381e855b strb w27, [x10], #-24 -+ 360: 7801b506 strh w6, [x8], #27 -+ 364: f853654e ldr x14, [x10], #-202 -+ 368: b85d74b0 ldr w16, [x5], #-41 -+ 36c: 384095c2 ldrb w2, [x14], #9 -+ 370: 785ec5bc ldrh w28, [x13], #-20 -+ 374: 389e15a9 ldrsb x9, [x13], #-31 -+ 378: 789dc703 ldrsh x3, [x24], #-36 -+ 37c: 78c06474 ldrsh w20, [x3], #6 -+ 380: b89ff667 ldrsw x7, [x19], #-1 -+ 384: fc57e51e ldr d30, [x8], #-130 -+ 388: bc4155f9 ldr s25, [x15], #21 -+ 38c: fc05a6ee str d14, [x23], #90 -+ 390: bc1df408 str s8, [x0], #-33 -+ 394: f835da4a str x10, [x18, w21, sxtw #3] -+ 398: b836d9a4 str w4, [x13, w22, sxtw #2] -+ 39c: 3833580d strb w13, [x0, w19, uxtw #0] -+ 3a0: 7826cb6c strh w12, [x27, w6, sxtw] -+ 3a4: f8706900 ldr x0, [x8, x16] -+ 3a8: b87ae880 ldr w0, [x4, x26, sxtx] -+ 3ac: 3865db2e ldrb w14, [x25, w5, sxtw #0] -+ 3b0: 78724889 ldrh w9, [x4, w18, uxtw] -+ 3b4: 38a7789b ldrsb x27, [x4, x7, lsl #0] -+ 3b8: 78beca2f ldrsh x15, [x17, w30, sxtw] -+ 3bc: 78f6c810 ldrsh w16, [x0, w22, sxtw] -+ 3c0: b8bef956 ldrsw x22, [x10, x30, sxtx #2] -+ 3c4: fc6afabd ldr d29, [x21, x10, sxtx #3] -+ 3c8: bc734963 ldr s3, [x11, w19, uxtw] -+ 3cc: fc3d5b8d str d13, [x28, w29, uxtw #3] -+ 3d0: bc25fbb7 str s23, [x29, x5, sxtx #2] -+ 3d4: f9189d05 str x5, [x8, #12600] -+ 3d8: b91ecb1d str w29, [x24, #7880] -+ 3dc: 39187a33 strb w19, [x17, #1566] -+ 3e0: 791f226d strh w13, [x19, #3984] -+ 3e4: f95aa2f3 ldr x19, [x23, #13632] -+ 3e8: b9587bb7 ldr w23, [x29, #6264] -+ 3ec: 395f7176 ldrb w22, [x11, #2012] -+ 3f0: 795d9143 ldrh w3, [x10, #3784] -+ 3f4: 399e7e08 ldrsb x8, [x16, #1951] -+ 3f8: 799a2697 ldrsh x23, [x20, #3346] -+ 3fc: 79df3422 ldrsh w2, [x1, #3994] -+ 400: b99c2624 ldrsw x4, [x17, #7204] -+ 404: fd5c2374 ldr d20, [x27, #14400] -+ 408: bd5fa1d9 ldr s25, [x14, #8096] -+ 40c: fd1d595a str d26, [x10, #15024] -+ 410: bd1b1869 str s9, [x3, #6936] -+ 414: 58001e9b ldr x27, 7e4 -+ 418: 1800000b ldr w11, 418 -+ 41c: f8945060 prfum pldl1keep, [x3, #-187] ++ 244: d503359f dsb nshld ++ 248: d50337bf dmb nsh ++ 24c: d61f0380 br x28 ++ 250: d63f0220 blr x17 ++ 254: c8127f47 stxr w18, x7, [x26] ++ 258: c819fccc stlxr w25, x12, [x6] ++ 25c: c85f7e00 ldxr x0, [x16] ++ 260: c85ffc66 ldaxr x6, [x3] ++ 264: c89ffc2e stlr x14, [x1] ++ 268: c8dfff1d ldar x29, [x24] ++ 26c: 881c7eef stxr w28, w15, [x23] ++ 270: 8809fc67 stlxr w9, w7, [x3] ++ 274: 885f7e81 ldxr w1, [x20] ++ 278: 885ffdf4 ldaxr w20, [x15] ++ 27c: 889ffd35 stlr w21, [x9] ++ 280: 88dffe25 ldar w5, [x17] ++ 284: 480d7fd4 stxrh w13, w20, [x30] ++ 288: 480afe4c stlxrh w10, w12, [x18] ++ 28c: 485f7e64 ldxrh w4, [x19] ++ 290: 485ffd56 ldaxrh w22, [x10] ++ 294: 489ffdfe stlrh w30, [x15] ++ 298: 48dfff04 ldarh w4, [x24] ++ 29c: 080a7d94 stxrb w10, w20, [x12] ++ 2a0: 0814fd7d stlxrb w20, w29, [x11] ++ 2a4: 085f7cb5 ldxrb w21, [x5] ++ 2a8: 085ffd24 ldaxrb w4, [x9] ++ 2ac: 089fff9e stlrb w30, [x28] ++ 2b0: 08dfff13 ldarb w19, [x24] ++ 2b4: c87f424b ldxp x11, x16, [x18] ++ 2b8: c87f9de8 ldaxp x8, x7, [x15] ++ 2bc: c83c4154 stxp w28, x20, x16, [x10] ++ 2c0: c827d469 stlxp w7, x9, x21, [x3] ++ 2c4: 887f1a79 ldxp w25, w6, [x19] ++ 2c8: 887fa45e ldaxp w30, w9, [x2] ++ 2cc: 88305180 stxp w16, w0, w20, [x12] ++ 2d0: 88259f82 stlxp w5, w2, w7, [x28] ++ 2d4: f81b5270 stur x16, [x19, #-75] ++ 2d8: b801e381 stur w1, [x28, #30] ++ 2dc: 381e61bc sturb w28, [x13, #-26] ++ 2e0: 781cd0c8 sturh w8, [x6, #-51] ++ 2e4: f851d380 ldur x0, [x28, #-227] ++ 2e8: b85e615c ldur w28, [x10, #-26] ++ 2ec: 39403164 ldrb w4, [x11, #12] ++ 2f0: 78405221 ldurh w1, [x17, #5] ++ 2f4: 3980312b ldrsb x11, [x9, #12] ++ 2f8: 789ef108 ldursh x8, [x8, #-17] ++ 2fc: 78ddd1b4 ldursh w20, [x13, #-35] ++ 300: b8831137 ldursw x23, [x9, #49] ++ 304: fc41d089 ldur d9, [x4, #29] ++ 308: bd402a6b ldr s11, [x19, #40] ++ 30c: fc1d5299 stur d25, [x20, #-43] ++ 310: bc1b0039 stur s25, [x1, #-80] ++ 314: f8019c14 str x20, [x0, #25]! ++ 318: b81cfd8c str w12, [x12, #-49]! ++ 31c: 381f6e7c strb w28, [x19, #-10]! ++ 320: 781c1f8d strh w13, [x28, #-63]! ++ 324: f85d2eeb ldr x11, [x23, #-46]! ++ 328: b8411f1b ldr w27, [x24, #17]! ++ 32c: 385f4f4e ldrb w14, [x26, #-12]! ++ 330: 785d3ed8 ldrh w24, [x22, #-45]! ++ 334: 389f5d39 ldrsb x25, [x9, #-11]! ++ 338: 7881dcc5 ldrsh x5, [x6, #29]! ++ 33c: 78dffee7 ldrsh w7, [x23, #-1]! ++ 340: b89c3dba ldrsw x26, [x13, #-61]! ++ 344: fc50bf18 ldr d24, [x24, #-245]! ++ 348: bc5c9f34 ldr s20, [x25, #-55]! ++ 34c: fc135c49 str d9, [x2, #-203]! ++ 350: bc1c5c2e str s14, [x1, #-59]! ++ 354: f806d433 str x19, [x1], #109 ++ 358: b81ca4a4 str w4, [x5], #-54 ++ 35c: 3800947d strb w29, [x3], #9 ++ 360: 781ce420 strh w0, [x1], #-50 ++ 364: f85d04c2 ldr x2, [x6], #-48 ++ 368: b858d4cf ldr w15, [x6], #-115 ++ 36c: 385e5444 ldrb w4, [x2], #-27 ++ 370: 785eb751 ldrh w17, [x26], #-21 ++ 374: 389f3715 ldrsb x21, [x24], #-13 ++ 378: 789d04d6 ldrsh x22, [x6], #-48 ++ 37c: 78dd04cb ldrsh w11, [x6], #-48 ++ 380: b89fb7ce ldrsw x14, [x30], #-5 ++ 384: fc5975e2 ldr d2, [x15], #-105 ++ 388: bc5a5679 ldr s25, [x19], #-91 ++ 38c: fc1416ed str d13, [x23], #-191 ++ 390: bc0006b6 str s22, [x21], #0 ++ 394: f832c996 str x22, [x12, w18, sxtw] ++ 398: b82c4b7e str w30, [x27, w12, uxtw] ++ 39c: 38367887 strb w7, [x4, x22, lsl #0] ++ 3a0: 783dfaf3 strh w19, [x23, x29, sxtx #1] ++ 3a4: f87bf891 ldr x17, [x4, x27, sxtx #3] ++ 3a8: b871c9a1 ldr w1, [x13, w17, sxtw] ++ 3ac: 387dfb70 ldrb w16, [x27, x29, sxtx #0] ++ 3b0: 78645939 ldrh w25, [x9, w4, uxtw #1] ++ 3b4: 38b67984 ldrsb x4, [x12, x22, lsl #0] ++ 3b8: 78a55839 ldrsh x25, [x1, w5, uxtw #1] ++ 3bc: 78fc6a09 ldrsh w9, [x16, x28] ++ 3c0: b8aee8e8 ldrsw x8, [x7, x14, sxtx] ++ 3c4: fc705b84 ldr d4, [x28, w16, uxtw #3] ++ 3c8: bc7bd850 ldr s16, [x2, w27, sxtw #2] ++ 3cc: fc396817 str d23, [x0, x25] ++ 3d0: bc277a06 str s6, [x16, x7, lsl #2] ++ 3d4: f91ddd82 str x2, [x12, #15288] ++ 3d8: b91b10a8 str w8, [x5, #6928] ++ 3dc: 391f8221 strb w1, [x17, #2016] ++ 3e0: 79197728 strh w8, [x25, #3258] ++ 3e4: f95ca07c ldr x28, [x3, #14656] ++ 3e8: b95b5d75 ldr w21, [x11, #7004] ++ 3ec: 395dc8af ldrb w15, [x5, #1906] ++ 3f0: 795caa60 ldrh w0, [x19, #3668] ++ 3f4: 399dd53d ldrsb x29, [x9, #1909] ++ 3f8: 799c7397 ldrsh x23, [x28, #3640] ++ 3fc: 79dcb15b ldrsh w27, [x10, #3672] ++ 400: b99e3b75 ldrsw x21, [x27, #7736] ++ 404: fd5c7f7a ldr d26, [x27, #14584] ++ 408: bd5d2882 ldr s2, [x4, #7464] ++ 40c: fd1fb2a1 str d1, [x21, #16224] ++ 410: bd1d82c4 str s4, [x22, #7552] ++ 414: 58000001 ldr x1, 414 ++ 418: 1800001b ldr w27, 418 ++ 41c: f882d080 prfum pldl1keep, [x4, #45] + 420: d8000000 prfm pldl1keep, 420 -+ 424: f8ae6ba0 prfm pldl1keep, [x29, x14] -+ 428: f99a0080 prfm pldl1keep, [x4, #13312] -+ 42c: 1a070035 adc w21, w1, w7 -+ 430: 3a0700a8 adcs w8, w5, w7 -+ 434: 5a0e0367 sbc w7, w27, w14 -+ 438: 7a11009b sbcs w27, w4, w17 -+ 43c: 9a000380 adc x0, x28, x0 -+ 440: ba1e030c adcs x12, x24, x30 -+ 444: da0f0320 sbc x0, x25, x15 -+ 448: fa030301 sbcs x1, x24, x3 -+ 44c: 0b340b12 add w18, w24, w20, uxtb #2 -+ 450: 2b2a278d adds w13, w28, w10, uxth #1 -+ 454: cb22aa0f sub x15, x16, w2, sxth #2 -+ 458: 6b2d29bd subs w29, w13, w13, uxth #2 -+ 45c: 8b2cce8c add x12, x20, w12, sxtw #3 -+ 460: ab2b877e adds x30, x27, w11, sxtb #1 -+ 464: cb21c8ee sub x14, x7, w1, sxtw #2 -+ 468: eb3ba47d subs x29, x3, w27, sxth #1 -+ 46c: 3a4d400e ccmn w0, w13, #0xe, mi // mi = first -+ 470: 7a5232c6 ccmp w22, w18, #0x6, cc // cc = lo, ul, last -+ 474: ba5e624e ccmn x18, x30, #0xe, vs -+ 478: fa53814c ccmp x10, x19, #0xc, hi // hi = pmore -+ 47c: 3a52d8c2 ccmn w6, #0x12, #0x2, le -+ 480: 7a4d8924 ccmp w9, #0xd, #0x4, hi // hi = pmore -+ 484: ba4b3aab ccmn x21, #0xb, #0xb, cc // cc = lo, ul, last -+ 488: fa4d7882 ccmp x4, #0xd, #0x2, vc -+ 48c: 1a96804c csel w12, w2, w22, hi // hi = pmore -+ 490: 1a912618 csinc w24, w16, w17, cs // cs = hs, nlast -+ 494: 5a90b0e6 csinv w6, w7, w16, lt // lt = tstop -+ 498: 5a96976b csneg w11, w27, w22, ls // ls = plast -+ 49c: 9a9db06a csel x10, x3, x29, lt // lt = tstop -+ 4a0: 9a9b374c csinc x12, x26, x27, cc // cc = lo, ul, last -+ 4a4: da95c14f csinv x15, x10, x21, gt -+ 4a8: da89c6fe csneg x30, x23, x9, gt -+ 4ac: 5ac0015e rbit w30, w10 -+ 4b0: 5ac005fd rev16 w29, w15 -+ 4b4: 5ac00bdd rev w29, w30 -+ 4b8: 5ac012b9 clz w25, w21 -+ 4bc: 5ac01404 cls w4, w0 -+ 4c0: dac002b2 rbit x18, x21 -+ 4c4: dac0061d rev16 x29, x16 -+ 4c8: dac00a95 rev32 x21, x20 -+ 4cc: dac00e66 rev x6, x19 -+ 4d0: dac0107e clz x30, x3 -+ 4d4: dac01675 cls x21, x19 -+ 4d8: 1ac00b0b udiv w11, w24, w0 -+ 4dc: 1ace0f3b sdiv w27, w25, w14 -+ 4e0: 1ad221c3 lsl w3, w14, w18 -+ 4e4: 1ad825e7 lsr w7, w15, w24 -+ 4e8: 1ad92a3c asr w28, w17, w25 -+ 4ec: 1adc2f42 ror w2, w26, w28 -+ 4f0: 9ada0b25 udiv x5, x25, x26 -+ 4f4: 9ad20e1b sdiv x27, x16, x18 -+ 4f8: 9acc22a6 lsl x6, x21, x12 -+ 4fc: 9acc2480 lsr x0, x4, x12 -+ 500: 9adc2a3b asr x27, x17, x28 -+ 504: 9ad22c5c ror x28, x2, x18 -+ 508: 1b0e39ea madd w10, w15, w14, w14 -+ 50c: 1b0fcf23 msub w3, w25, w15, w19 -+ 510: 9b1010ae madd x14, x5, x16, x4 -+ 514: 9b048b3a msub x26, x25, x4, x2 -+ 518: 9b3d4582 smaddl x2, w12, w29, x17 -+ 51c: 9b2390e8 smsubl x8, w7, w3, x4 -+ 520: 9bba6499 umaddl x25, w4, w26, x25 -+ 524: 9ba0ea24 umsubl x4, w17, w0, x26 -+ 528: 1e2f0af1 fmul s17, s23, s15 -+ 52c: 1e311b95 fdiv s21, s28, s17 -+ 530: 1e23295b fadd s27, s10, s3 -+ 534: 1e3938e0 fsub s0, s7, s25 -+ 538: 1e2f08c9 fmul s9, s6, s15 -+ 53c: 1e6a09fd fmul d29, d15, d10 -+ 540: 1e671a22 fdiv d2, d17, d7 -+ 544: 1e77296b fadd d11, d11, d23 -+ 548: 1e773ba7 fsub d7, d29, d23 -+ 54c: 1e6b0b6e fmul d14, d27, d11 -+ 550: 1f18308b fmadd s11, s4, s24, s12 -+ 554: 1f14adcf fmsub s15, s14, s20, s11 -+ 558: 1f2b31bc nmadd s28, s13, s11, s12 -+ 55c: 1f3a3bd7 fnmadd s23, s30, s26, s14 -+ 560: 1f4a1da9 fmadd d9, d13, d10, d7 -+ 564: 1f4f8fa5 fmsub d5, d29, d15, d3 -+ 568: 1f6f798b fnmadd d11, d12, d15, d30 -+ 56c: 1f73523e fnmadd d30, d17, d19, d20 -+ 570: 1e2040fb fmov s27, s7 -+ 574: 1e20c2a9 fabs s9, s21 -+ 578: 1e214122 fneg s2, s9 -+ 57c: 1e21c0fb fsqrt s27, s7 -+ 580: 1e22c3dd fcvt d29, s30 -+ 584: 1e604031 fmov d17, d1 -+ 588: 1e60c0c2 fabs d2, d6 -+ 58c: 1e61406a fneg d10, d3 -+ 590: 1e61c178 fsqrt d24, d11 -+ 594: 1e624027 fcvt s7, d1 -+ 598: 1e38000b fcvtzs w11, s0 -+ 59c: 9e380243 fcvtzs x3, s18 -+ 5a0: 1e7800dc fcvtzs w28, d6 -+ 5a4: 9e7800d6 fcvtzs x22, d6 -+ 5a8: 1e220360 scvtf s0, w27 -+ 5ac: 9e22005a scvtf s26, x2 -+ 5b0: 1e6200e5 scvtf d5, w7 -+ 5b4: 9e62017c scvtf d28, x11 -+ 5b8: 1e2601b9 fmov w25, s13 -+ 5bc: 9e6602eb fmov x11, d23 -+ 5c0: 1e270113 fmov s19, w8 -+ 5c4: 9e6702b2 fmov d18, x21 -+ 5c8: 1e342320 fcmp s25, s20 -+ 5cc: 1e722260 fcmp d19, d18 -+ 5d0: 1e202048 fcmp s2, #0.0 -+ 5d4: 1e6023a8 fcmp d29, #0.0 -+ 5d8: 29025668 stp w8, w21, [x19, #16] -+ 5dc: 29403e86 ldp w6, w15, [x20] -+ 5e0: 6966387b ldpsw x27, x14, [x3, #-208] -+ 5e4: a93b316a stp x10, x12, [x11, #-80] -+ 5e8: a97e38e7 ldp x7, x14, [x7, #-32] -+ 5ec: 298e5980 stp w0, w22, [x12, #112]! -+ 5f0: 29c61d0e ldp w14, w7, [x8, #48]! -+ 5f4: 69c00930 ldpsw x16, x2, [x9, #0]! -+ 5f8: a9bc7434 stp x20, x29, [x1, #-64]! -+ 5fc: a9c530b5 ldp x21, x12, [x5, #80]! -+ 600: 28b26378 stp w24, w24, [x27], #-112 -+ 604: 28c25a5c ldp w28, w22, [x18], #16 -+ 608: 68f419b1 ldpsw x17, x6, [x13], #-96 -+ 60c: a8b668bc stp x28, x26, [x5], #-160 -+ 610: a8f15746 ldp x6, x21, [x26], #-240 -+ 614: 280453cd stnp w13, w20, [x30, #32] -+ 618: 284c2cb1 ldnp w17, w11, [x5, #96] -+ 61c: a83a534d stnp x13, x20, [x26, #-96] -+ 620: a87b32fd ldnp x29, x12, [x23, #-80] -+ 624: 05a08020 mov z0.s, p0/m, s1 -+ 628: 04b0e3e0 incw x0 -+ 62c: 0470e7e1 dech x1 -+ 630: 042f9c20 lsl z0.b, z1.b, #7 -+ 634: 043f9c35 lsl z21.h, z1.h, #15 -+ 638: 047f9c20 lsl z0.s, z1.s, #31 -+ 63c: 04ff9c20 lsl z0.d, z1.d, #63 -+ 640: 04299420 lsr z0.b, z1.b, #7 -+ 644: 04319160 asr z0.h, z11.h, #15 -+ 648: 0461943e lsr z30.s, z1.s, #31 -+ 64c: 04a19020 asr z0.d, z1.d, #63 -+ 650: 042053ff addvl sp, x0, #31 -+ 654: 047f5401 addpl x1, sp, #-32 -+ 658: 25208028 cntp x8, p0, p1.b -+ 65c: 2538cfe0 mov z0.b, #127 -+ 660: 2578d001 mov z1.h, #-128 -+ 664: 25b8efe2 mov z2.s, #32512 -+ 668: 25f8f007 mov z7.d, #-32768 -+ 66c: a400a3e0 ld1b {z0.b}, p0/z, [sp] -+ 670: a4a8a7ea ld1h {z10.h}, p1/z, [sp, #-8, mul vl] -+ 674: a547a814 ld1w {z20.s}, p2/z, [x0, #7, mul vl] -+ 678: a4084ffe ld1b {z30.b}, p3/z, [sp, x8] -+ 67c: a55c53e0 ld1w {z0.s}, p4/z, [sp, x28, lsl #2] -+ 680: a5e1540b ld1d {z11.d}, p5/z, [x0, x1, lsl #3] -+ 684: e400fbf6 st1b {z22.b}, p6, [sp] -+ 688: e408ffff st1b {z31.b}, p7, [sp, #-8, mul vl] -+ 68c: e547e400 st1w {z0.s}, p1, [x0, #7, mul vl] -+ 690: e4014be0 st1b {z0.b}, p2, [sp, x1] -+ 694: e4a84fe0 st1h {z0.h}, p3, [sp, x8, lsl #1] -+ 698: e5f25000 st1d {z0.d}, p4, [x0, x18, lsl #3] -+ 69c: 858043e0 ldr z0, [sp] -+ 6a0: 85a043ff ldr z31, [sp, #-256, mul vl] -+ 6a4: e59f5d08 str z8, [x8, #255, mul vl] -+ 6a8: 1e601000 fmov d0, #2.000000000000000000e+00 -+ 6ac: 1e603000 fmov d0, #2.125000000000000000e+00 -+ 6b0: 1e621000 fmov d0, #4.000000000000000000e+00 -+ 6b4: 1e623000 fmov d0, #4.250000000000000000e+00 -+ 6b8: 1e641000 fmov d0, #8.000000000000000000e+00 -+ 6bc: 1e643000 fmov d0, #8.500000000000000000e+00 -+ 6c0: 1e661000 fmov d0, #1.600000000000000000e+01 -+ 6c4: 1e663000 fmov d0, #1.700000000000000000e+01 -+ 6c8: 1e681000 fmov d0, #1.250000000000000000e-01 -+ 6cc: 1e683000 fmov d0, #1.328125000000000000e-01 -+ 6d0: 1e6a1000 fmov d0, #2.500000000000000000e-01 -+ 6d4: 1e6a3000 fmov d0, #2.656250000000000000e-01 -+ 6d8: 1e6c1000 fmov d0, #5.000000000000000000e-01 -+ 6dc: 1e6c3000 fmov d0, #5.312500000000000000e-01 -+ 6e0: 1e6e1000 fmov d0, #1.000000000000000000e+00 -+ 6e4: 1e6e3000 fmov d0, #1.062500000000000000e+00 -+ 6e8: 1e701000 fmov d0, #-2.000000000000000000e+00 -+ 6ec: 1e703000 fmov d0, #-2.125000000000000000e+00 -+ 6f0: 1e721000 fmov d0, #-4.000000000000000000e+00 -+ 6f4: 1e723000 fmov d0, #-4.250000000000000000e+00 -+ 6f8: 1e741000 fmov d0, #-8.000000000000000000e+00 -+ 6fc: 1e743000 fmov d0, #-8.500000000000000000e+00 -+ 700: 1e761000 fmov d0, #-1.600000000000000000e+01 -+ 704: 1e763000 fmov d0, #-1.700000000000000000e+01 -+ 708: 1e781000 fmov d0, #-1.250000000000000000e-01 -+ 70c: 1e783000 fmov d0, #-1.328125000000000000e-01 -+ 710: 1e7a1000 fmov d0, #-2.500000000000000000e-01 -+ 714: 1e7a3000 fmov d0, #-2.656250000000000000e-01 -+ 718: 1e7c1000 fmov d0, #-5.000000000000000000e-01 -+ 71c: 1e7c3000 fmov d0, #-5.312500000000000000e-01 -+ 720: 1e7e1000 fmov d0, #-1.000000000000000000e+00 -+ 724: 1e7e3000 fmov d0, #-1.062500000000000000e+00 -+ 728: 04bb020e add z14.s, z16.s, z27.s -+ 72c: 04ba04c0 sub z0.s, z6.s, z26.s -+ 730: 6586019b fadd z27.s, z12.s, z6.s -+ 734: 6593089e fmul z30.s, z4.s, z19.s -+ 738: 65c2060b fsub z11.d, z16.d, z2.d -+ 73c: 04d6a18f abs z15.d, p0/m, z12.d -+ 740: 040016e9 add z9.b, p5/m, z9.b, z23.b -+ 744: 0490835e asr z30.s, p0/m, z30.s, z26.s -+ 748: 045aaa44 cnt z4.h, p2/m, z18.h -+ 74c: 04938579 lsl z25.s, p1/m, z25.s, z11.s -+ 750: 0411990a lsr z10.b, p6/m, z10.b, z8.b -+ 754: 04101624 mul z4.b, p5/m, z4.b, z17.b -+ 758: 0497ad3e neg z30.s, p3/m, z9.s -+ 75c: 04deae80 not z0.d, p3/m, z20.d -+ 760: 04481c77 smax z23.h, p7/m, z23.h, z3.h -+ 764: 044a0960 smin z0.h, p2/m, z0.h, z11.h -+ 768: 04c118ab sub z11.d, p6/m, z11.d, z5.d -+ 76c: 049caa30 fabs z16.s, p2/m, z17.s -+ 770: 6580834f fadd z15.s, p0/m, z15.s, z26.s -+ 774: 658d9e6a fdiv z10.s, p7/m, z10.s, z19.s -+ 778: 65c68238 fmax z24.d, p0/m, z24.d, z17.d -+ 77c: 65c791fa fmin z26.d, p4/m, z26.d, z15.d -+ 780: 65c28a38 fmul z24.d, p2/m, z24.d, z17.d -+ 784: 049db7be fneg z30.s, p5/m, z29.s -+ 788: 6582b552 frintm z18.s, p5/m, z10.s -+ 78c: 65c0abde frintn z30.d, p2/m, z30.d -+ 790: 6581bbc6 frintp z6.s, p6/m, z30.s -+ 794: 65cdb854 fsqrt z20.d, p6/m, z2.d -+ 798: 658197a9 fsub z9.s, p5/m, z9.s, z29.s -+ 79c: 65f60872 fmla z18.d, p2/m, z3.d, z22.d -+ 7a0: 65ec29af fmls z15.d, p2/m, z13.d, z12.d -+ 7a4: 65be43cc fnmla z12.s, p0/m, z30.s, z30.s -+ 7a8: 65e06ea7 fnmls z7.d, p3/m, z21.d, z0.d -+ 7ac: 04544b53 mla z19.h, p2/m, z26.h, z20.h -+ 7b0: 04d57c30 mls z16.d, p7/m, z1.d, z21.d -+ 7b4: 04323095 and z21.d, z4.d, z18.d -+ 7b8: 04a7324c eor z12.d, z18.d, z7.d -+ 7bc: 046d31f9 orr z25.d, z15.d, z13.d -+ 7c0: 04da30eb andv d11, p4, z7.d -+ 7c4: 04d8252b orv d11, p1, z9.d -+ 7c8: 04d93c1c eorv d28, p7, z0.d -+ 7cc: 044820f0 smaxv h16, p0, z7.h -+ 7d0: 040a2fac sminv b12, p3, z29.b -+ 7d4: 65873975 fminv s21, p6, z11.s -+ 7d8: 65c62886 fmaxv d6, p2, z4.d -+ 7dc: 65d820e7 fadda d7, p0, d7, z7.d -+ 7e0: 04013fac uaddv d12, p7, z29.b ++ 424: f8a0cbc0 prfm pldl1keep, [x30, w0, sxtw] ++ 428: f99fab00 prfm pldl1keep, [x24, #16208] ++ 42c: 1a1803a0 adc w0, w29, w24 ++ 430: 3a120396 adcs w22, w28, w18 ++ 434: 5a1e0217 sbc w23, w16, w30 ++ 438: 7a0e03a7 sbcs w7, w29, w14 ++ 43c: 9a0e0196 adc x22, x12, x14 ++ 440: ba17031d adcs x29, x24, x23 ++ 444: da160391 sbc x17, x28, x22 ++ 448: fa130298 sbcs x24, x20, x19 ++ 44c: 0b26cadb add w27, w22, w6, sxtw #2 ++ 450: 2b38516d adds w13, w11, w24, uxtw #4 ++ 454: cb242d10 sub x16, x8, w4, uxth #3 ++ 458: 6b34ea55 subs w21, w18, w20, sxtx #2 ++ 45c: 8b3d0a2e add x14, x17, w29, uxtb #2 ++ 460: ab2eb231 adds x17, x17, w14, sxth #4 ++ 464: cb3ac476 sub x22, x3, w26, sxtw #1 ++ 468: eb3531ad subs x13, x13, w21, uxth #4 ++ 46c: 3a5a722f ccmn w17, w26, #0xf, vc ++ 470: 7a463325 ccmp w25, w6, #0x5, cc // cc = lo, ul, last ++ 474: ba5e9021 ccmn x1, x30, #0x1, ls // ls = plast ++ 478: fa47a222 ccmp x17, x7, #0x2, ge // ge = tcont ++ 47c: 3a590a26 ccmn w17, #0x19, #0x6, eq // eq = none ++ 480: 7a450845 ccmp w2, #0x5, #0x5, eq // eq = none ++ 484: ba514a6a ccmn x19, #0x11, #0xa, mi // mi = first ++ 488: fa48c9c3 ccmp x14, #0x8, #0x3, gt ++ 48c: 1a8e9109 csel w9, w8, w14, ls // ls = plast ++ 490: 1a85d57b csinc w27, w11, w5, le ++ 494: 5a9632eb csinv w11, w23, w22, cc // cc = lo, ul, last ++ 498: 5a9b2793 csneg w19, w28, w27, cs // cs = hs, nlast ++ 49c: 9a815130 csel x16, x9, x1, pl // pl = nfrst ++ 4a0: 9a8c05dc csinc x28, x14, x12, eq // eq = none ++ 4a4: da8e5096 csinv x22, x4, x14, pl // pl = nfrst ++ 4a8: da9b257a csneg x26, x11, x27, cs // cs = hs, nlast ++ 4ac: 5ac00178 rbit w24, w11 ++ 4b0: 5ac005ca rev16 w10, w14 ++ 4b4: 5ac008a9 rev w9, w5 ++ 4b8: 5ac01292 clz w18, w20 ++ 4bc: 5ac01519 cls w25, w8 ++ 4c0: dac00316 rbit x22, x24 ++ 4c4: dac0077c rev16 x28, x27 ++ 4c8: dac00ba8 rev32 x8, x29 ++ 4cc: dac00d51 rev x17, x10 ++ 4d0: dac01177 clz x23, x11 ++ 4d4: dac015da cls x26, x14 ++ 4d8: 1adc0895 udiv w21, w4, w28 ++ 4dc: 1ad60d5e sdiv w30, w10, w22 ++ 4e0: 1ada205d lsl w29, w2, w26 ++ 4e4: 1aca26dc lsr w28, w22, w10 ++ 4e8: 1acc2b0b asr w11, w24, w12 ++ 4ec: 1ad02fd5 ror w21, w30, w16 ++ 4f0: 9acd0801 udiv x1, x0, x13 ++ 4f4: 9ac60e22 sdiv x2, x17, x6 ++ 4f8: 9ad5230a lsl x10, x24, x21 ++ 4fc: 9ac62525 lsr x5, x9, x6 ++ 500: 9ac42b60 asr x0, x27, x4 ++ 504: 9ac22c9c ror x28, x4, x2 ++ 508: 9bc77fc1 umulh x1, x30, x7 ++ 50c: 9b4a7cbe smulh x30, x5, x10 ++ 510: 1b0d45e7 madd w7, w15, w13, w17 ++ 514: 1b0cf039 msub w25, w1, w12, w28 ++ 518: 9b1e2562 madd x2, x11, x30, x9 ++ 51c: 9b03dae5 msub x5, x23, x3, x22 ++ 520: 9b291159 smaddl x25, w10, w9, x4 ++ 524: 9b27c905 smsubl x5, w8, w7, x18 ++ 528: 9bba64b8 umaddl x24, w5, w26, x25 ++ 52c: 9bbaf02e umsubl x14, w1, w26, x28 ++ 530: 1e280ad8 fmul s24, s22, s8 ++ 534: 1e261870 fdiv s16, s3, s6 ++ 538: 1e392ab0 fadd s16, s21, s25 ++ 53c: 1e3b3b40 fsub s0, s26, s27 ++ 540: 1e310878 fmul s24, s3, s17 ++ 544: 1e660909 fmul d9, d8, d6 ++ 548: 1e7e1a76 fdiv d22, d19, d30 ++ 54c: 1e632a2e fadd d14, d17, d3 ++ 550: 1e743b78 fsub d24, d27, d20 ++ 554: 1e76082c fmul d12, d1, d22 ++ 558: 1f0b7510 fmadd s16, s8, s11, s29 ++ 55c: 1f128676 fmsub s22, s19, s18, s1 ++ 560: 1f38270f fnmadd s15, s24, s24, s9 ++ 564: 1f2d5e7b fnmadd s27, s19, s13, s23 ++ 568: 1f503003 fmadd d3, d0, d16, d12 ++ 56c: 1f52a873 fmsub d19, d3, d18, d10 ++ 570: 1f6b5041 fnmadd d1, d2, d11, d20 ++ 574: 1f79392c fnmadd d12, d9, d25, d14 ++ 578: 1e2042e0 fmov s0, s23 ++ 57c: 1e20c0d7 fabs s23, s6 ++ 580: 1e214084 fneg s4, s4 ++ 584: 1e21c385 fsqrt s5, s28 ++ 588: 1e22c1f5 fcvt d21, s15 ++ 58c: 1e6040ab fmov d11, d5 ++ 590: 1e60c092 fabs d18, d4 ++ 594: 1e61418b fneg d11, d12 ++ 598: 1e61c10f fsqrt d15, d8 ++ 59c: 1e624048 fcvt s8, d2 ++ 5a0: 1e380253 fcvtzs w19, s18 ++ 5a4: 9e380011 fcvtzs x17, s0 ++ 5a8: 1e7801a0 fcvtzs w0, d13 ++ 5ac: 9e780136 fcvtzs x22, d9 ++ 5b0: 1e2203a6 scvtf s6, w29 ++ 5b4: 9e2201cc scvtf s12, x14 ++ 5b8: 1e6202d0 scvtf d16, w22 ++ 5bc: 9e6200ae scvtf d14, x5 ++ 5c0: 1e260007 fmov w7, s0 ++ 5c4: 9e6600dc fmov x28, d6 ++ 5c8: 1e270342 fmov s2, w26 ++ 5cc: 9e670004 fmov d4, x0 ++ 5d0: 1e2b2020 fcmp s1, s11 ++ 5d4: 1e7520c0 fcmp d6, d21 ++ 5d8: 1e202208 fcmp s16, #0.0 ++ 5dc: 1e6022c8 fcmp d22, #0.0 ++ 5e0: 290c0045 stp w5, w0, [x2, #96] ++ 5e4: 2978766e ldp w14, w29, [x19, #-64] ++ 5e8: 696c0c6f ldpsw x15, x3, [x3, #-160] ++ 5ec: a9323767 stp x7, x13, [x27, #-224] ++ 5f0: a9483831 ldp x17, x14, [x1, #128] ++ 5f4: 29905895 stp w21, w22, [x4, #128]! ++ 5f8: 29f43451 ldp w17, w13, [x2, #-96]! ++ 5fc: 69ee66f5 ldpsw x21, x25, [x23, #-144]! ++ 600: a9bf41e4 stp x4, x16, [x15, #-16]! ++ 604: a9f6573d ldp x29, x21, [x25, #-160]! ++ 608: 288a4758 stp w24, w17, [x26], #80 ++ 60c: 28e27bc3 ldp w3, w30, [x30], #-240 ++ 610: 68fc4fc3 ldpsw x3, x19, [x30], #-32 ++ 614: a8b70779 stp x25, x1, [x27], #-144 ++ 618: a8fc539a ldp x26, x20, [x28], #-64 ++ 61c: 283a653d stnp w29, w25, [x9, #-48] ++ 620: 28703a79 ldnp w25, w14, [x19, #-128] ++ 624: a8025879 stnp x25, x22, [x3, #32] ++ 628: a8734ba9 ldnp x9, x18, [x29, #-208] ++ 62c: 0c407275 ld1 {v21.8b}, [x19] ++ 630: 4cdfa29b ld1 {v27.16b, v28.16b}, [x20], #32 ++ 634: 0cc66ec5 ld1 {v5.1d-v7.1d}, [x22], x6 ++ 638: 4cdf2596 ld1 {v22.8h-v25.8h}, [x12], #64 ++ 63c: 0d40c131 ld1r {v17.8b}, [x9] ++ 640: 4ddfcaa5 ld1r {v5.4s}, [x21], #4 ++ 644: 0dd2cf8a ld1r {v10.1d}, [x28], x18 ++ 648: 4c408dfa ld2 {v26.2d, v27.2d}, [x15] ++ 64c: 0cdf8750 ld2 {v16.4h, v17.4h}, [x26], #16 ++ 650: 4d60c04e ld2r {v14.16b, v15.16b}, [x2] ++ 654: 0dffcb92 ld2r {v18.2s, v19.2s}, [x28], #8 ++ 658: 4df6cc13 ld2r {v19.2d, v20.2d}, [x0], x22 ++ 65c: 4cd24850 ld3 {v16.4s-v18.4s}, [x2], x18 ++ 660: 0c404818 ld3 {v24.2s-v26.2s}, [x0] ++ 664: 4d40e604 ld3r {v4.8h-v6.8h}, [x16] ++ 668: 4ddfe825 ld3r {v5.4s-v7.4s}, [x1], #12 ++ 66c: 0dd0ed47 ld3r {v7.1d-v9.1d}, [x10], x16 ++ 670: 4cdf0696 ld4 {v22.8h-v25.8h}, [x20], #64 ++ 674: 0cd9008f ld4 {v15.8b-v18.8b}, [x4], x25 ++ 678: 0d60e0a0 ld4r {v0.8b-v3.8b}, [x5] ++ 67c: 0dffe420 ld4r {v0.4h-v3.4h}, [x1], #8 ++ 680: 0deeeb9e ld4r {v30.2s, v31.2s, v0.2s, v1.2s}, [x28], x14 ++ 684: ba5fd3e3 ccmn xzr, xzr, #0x3, le ++ 688: 3a5f03e5 ccmn wzr, wzr, #0x5, eq // eq = none ++ 68c: fa411be4 ccmp xzr, #0x1, #0x4, ne // ne = any ++ 690: 7a42cbe2 ccmp wzr, #0x2, #0x2, gt ++ 694: 93df03ff ror xzr, xzr, #0 ++ 698: c820ffff stlxp w0, xzr, xzr, [sp] ++ 69c: 8822fc7f stlxp w2, wzr, wzr, [x3] ++ 6a0: c8247cbf stxp w4, xzr, xzr, [x5] ++ 6a4: 88267fff stxp w6, wzr, wzr, [sp] ++ 6a8: 4e010fe0 dup v0.16b, wzr ++ 6ac: 4e081fe1 mov v1.d[0], xzr ++ 6b0: 4e0c1fe1 mov v1.s[1], wzr ++ 6b4: 4e0a1fe1 mov v1.h[2], wzr ++ 6b8: 4e071fe1 mov v1.b[3], wzr ++ 6bc: 4cc0ac3f ld1 {v31.2d, v0.2d}, [x1], x0 ++ 6c0: 1e601000 fmov d0, #2.000000000000000000e+00 ++ 6c4: 1e603000 fmov d0, #2.125000000000000000e+00 ++ 6c8: 1e621000 fmov d0, #4.000000000000000000e+00 ++ 6cc: 1e623000 fmov d0, #4.250000000000000000e+00 ++ 6d0: 1e641000 fmov d0, #8.000000000000000000e+00 ++ 6d4: 1e643000 fmov d0, #8.500000000000000000e+00 ++ 6d8: 1e661000 fmov d0, #1.600000000000000000e+01 ++ 6dc: 1e663000 fmov d0, #1.700000000000000000e+01 ++ 6e0: 1e681000 fmov d0, #1.250000000000000000e-01 ++ 6e4: 1e683000 fmov d0, #1.328125000000000000e-01 ++ 6e8: 1e6a1000 fmov d0, #2.500000000000000000e-01 ++ 6ec: 1e6a3000 fmov d0, #2.656250000000000000e-01 ++ 6f0: 1e6c1000 fmov d0, #5.000000000000000000e-01 ++ 6f4: 1e6c3000 fmov d0, #5.312500000000000000e-01 ++ 6f8: 1e6e1000 fmov d0, #1.000000000000000000e+00 ++ 6fc: 1e6e3000 fmov d0, #1.062500000000000000e+00 ++ 700: 1e701000 fmov d0, #-2.000000000000000000e+00 ++ 704: 1e703000 fmov d0, #-2.125000000000000000e+00 ++ 708: 1e721000 fmov d0, #-4.000000000000000000e+00 ++ 70c: 1e723000 fmov d0, #-4.250000000000000000e+00 ++ 710: 1e741000 fmov d0, #-8.000000000000000000e+00 ++ 714: 1e743000 fmov d0, #-8.500000000000000000e+00 ++ 718: 1e761000 fmov d0, #-1.600000000000000000e+01 ++ 71c: 1e763000 fmov d0, #-1.700000000000000000e+01 ++ 720: 1e781000 fmov d0, #-1.250000000000000000e-01 ++ 724: 1e783000 fmov d0, #-1.328125000000000000e-01 ++ 728: 1e7a1000 fmov d0, #-2.500000000000000000e-01 ++ 72c: 1e7a3000 fmov d0, #-2.656250000000000000e-01 ++ 730: 1e7c1000 fmov d0, #-5.000000000000000000e-01 ++ 734: 1e7c3000 fmov d0, #-5.312500000000000000e-01 ++ 738: 1e7e1000 fmov d0, #-1.000000000000000000e+00 ++ 73c: 1e7e3000 fmov d0, #-1.062500000000000000e+00 ++ 740: f83a8229 swp x26, x9, [x17] ++ 744: f83c0057 ldadd x28, x23, [x2] ++ 748: f8361062 ldclr x22, x2, [x3] ++ 74c: f82b23d9 ldeor x11, x25, [x30] ++ 750: f836309c ldset x22, x28, [x4] ++ 754: f826530b ldsmin x6, x11, [x24] ++ 758: f82c43ff stsmax x12, [sp] ++ 75c: f837713e ldumin x23, x30, [x9] ++ 760: f8266281 ldumax x6, x1, [x20] ++ 764: f8b182c2 swpa x17, x2, [x22] ++ 768: f8ae015b ldadda x14, x27, [x10] ++ 76c: f8a6127e ldclra x6, x30, [x19] ++ 770: f8a02179 ldeora x0, x25, [x11] ++ 774: f8b733c0 ldseta x23, x0, [x30] ++ 778: f8b55143 ldsmina x21, x3, [x10] ++ 77c: f8af4016 ldsmaxa x15, x22, [x0] ++ 780: f8b17280 ldumina x17, x0, [x20] ++ 784: f8b0602d ldumaxa x16, x13, [x1] ++ 788: f8fb82ef swpal x27, x15, [x23] ++ 78c: f8f3003e ldaddal x19, x30, [x1] ++ 790: f8ef12fc ldclral x15, x28, [x23] ++ 794: f8e7226f ldeoral x7, x15, [x19] ++ 798: f8eb314c ldsetal x11, x12, [x10] ++ 79c: f8e65187 ldsminal x6, x7, [x12] ++ 7a0: f8fc41a5 ldsmaxal x28, x5, [x13] ++ 7a4: f8e97234 lduminal x9, x20, [x17] ++ 7a8: f8f56179 ldumaxal x21, x25, [x11] ++ 7ac: f8738318 swpl x19, x24, [x24] ++ 7b0: f86803da ldaddl x8, x26, [x30] ++ 7b4: f8711112 ldclrl x17, x18, [x8] ++ 7b8: f8622063 ldeorl x2, x3, [x3] ++ 7bc: f87a3207 ldsetl x26, x7, [x16] ++ 7c0: f87b50a6 ldsminl x27, x6, [x5] ++ 7c4: f8764280 ldsmaxl x22, x0, [x20] ++ 7c8: f86b705a lduminl x11, x26, [x2] ++ 7cc: f87e609d ldumaxl x30, x29, [x4] ++ 7d0: b82480e5 swp w4, w5, [x7] ++ 7d4: b82a005a ldadd w10, w26, [x2] ++ 7d8: b83b1370 ldclr w27, w16, [x27] ++ 7dc: b83f2157 ldeor wzr, w23, [x10] ++ 7e0: b82431a2 ldset w4, w2, [x13] ++ 7e4: b823506f ldsmin w3, w15, [x3] ++ 7e8: b82340ca ldsmax w3, w10, [x6] ++ 7ec: b828714b ldumin w8, w11, [x10] ++ 7f0: b83d61be ldumax w29, w30, [x13] ++ 7f4: b8ab8291 swpa w11, w17, [x20] ++ 7f8: b8ba00d0 ldadda w26, w16, [x6] ++ 7fc: b8b5102a ldclra w21, w10, [x1] ++ 800: b8bd22ec ldeora w29, w12, [x23] ++ 804: b8bd3108 ldseta w29, w8, [x8] ++ 808: b8ab51ca ldsmina w11, w10, [x14] ++ 80c: b8a442cd ldsmaxa w4, w13, [x22] ++ 810: b8a770ed ldumina w7, w13, [x7] ++ 814: b8ae63e0 ldumaxa w14, w0, [sp] ++ 818: b8f18382 swpal w17, w2, [x28] ++ 81c: b8f3014b ldaddal w19, w11, [x10] ++ 820: b8ec1293 ldclral w12, w19, [x20] ++ 824: b8e02108 ldeoral w0, w8, [x8] ++ 828: b8f13303 ldsetal w17, w3, [x24] ++ 82c: b8f950e5 ldsminal w25, w5, [x7] ++ 830: b8f0413e ldsmaxal w16, w30, [x9] ++ 834: b8ea71df lduminal w10, wzr, [x14] ++ 838: b8f16173 ldumaxal w17, w19, [x11] ++ 83c: b87481a1 swpl w20, w1, [x13] ++ 840: b87a028b ldaddl w26, w11, [x20] ++ 844: b87213d8 ldclrl w18, w24, [x30] ++ 848: b86c2299 ldeorl w12, w25, [x20] ++ 84c: b86e30bd ldsetl w14, w29, [x5] ++ 850: b862537a ldsminl w2, w26, [x27] ++ 854: b879417b ldsmaxl w25, w27, [x11] ++ 858: b86470fd lduminl w4, w29, [x7] ++ 85c: b870615d ldumaxl w16, w29, [x10] */ static const unsigned int insns[] = { -- 0x8b0772d3, 0xcb4a3570, 0xab9c09bb, 0xeb9aa794, -- 0x0b934e68, 0x4b0a3924, 0x2b1e3568, 0x6b132720, -- 0x8a154c14, 0xaa1445d5, 0xca01cf99, 0xea8b3f6a, -- 0x0a8c5cb9, 0x2a4a11d2, 0x4a855aa4, 0x6a857415, -- 0x8aa697da, 0xaa6d7423, 0xca29bf80, 0xea3cb8bd, -- 0x0a675249, 0x2ab961ba, 0x4a331899, 0x6a646345, -- 0x11055267, 0x31064408, 0x51028e9d, 0x710bdee8, -- 0x91082d81, 0xb106a962, 0xd10b33ae, 0xf10918ab, -- 0x121102d7, 0x3204cd44, 0x5204cf00, 0x72099fb3, -- 0x92729545, 0xb20e37cc, 0xd27c34be, 0xf27e4efa, -- 0x14000000, 0x17ffffd7, 0x1400017f, 0x94000000, -- 0x97ffffd4, 0x9400017c, 0x3400000c, 0x34fffa2c, -- 0x34002f2c, 0x35000014, 0x35fff9d4, 0x35002ed4, -- 0xb400000c, 0xb4fff96c, 0xb4002e6c, 0xb5000018, -- 0xb5fff918, 0xb5002e18, 0x10000006, 0x10fff8a6, -- 0x10002da6, 0x90000015, 0x36080001, 0x360ff821, -- 0x36082d21, 0x37480008, 0x374ff7c8, 0x37482cc8, -- 0x128b50ec, 0x52a9ff8b, 0x7281d095, 0x92edfebd, -- 0xd28361e3, 0xf2a4cc96, 0x9346590c, 0x33194f33, -- 0x531d3d89, 0x9350433c, 0xb34464ac, 0xd3462140, -- 0x139a61a4, 0x93d87fd7, 0x54000000, 0x54fff5a0, -- 0x54002aa0, 0x54000001, 0x54fff541, 0x54002a41, -- 0x54000002, 0x54fff4e2, 0x540029e2, 0x54000002, -- 0x54fff482, 0x54002982, 0x54000003, 0x54fff423, -- 0x54002923, 0x54000003, 0x54fff3c3, 0x540028c3, -- 0x54000004, 0x54fff364, 0x54002864, 0x54000005, -- 0x54fff305, 0x54002805, 0x54000006, 0x54fff2a6, -- 0x540027a6, 0x54000007, 0x54fff247, 0x54002747, -- 0x54000008, 0x54fff1e8, 0x540026e8, 0x54000009, -- 0x54fff189, 0x54002689, 0x5400000a, 0x54fff12a, -- 0x5400262a, 0x5400000b, 0x54fff0cb, 0x540025cb, -- 0x5400000c, 0x54fff06c, 0x5400256c, 0x5400000d, -- 0x54fff00d, 0x5400250d, 0x5400000e, 0x54ffefae, -- 0x540024ae, 0x5400000f, 0x54ffef4f, 0x5400244f, -- 0xd4063721, 0xd4035082, 0xd400bfe3, 0xd4282fc0, -- 0xd444c320, 0xd503201f, 0xd69f03e0, 0xd6bf03e0, -- 0xd5033fdf, 0xd5033f9f, 0xd5033abf, 0xd61f0040, -- 0xd63f00a0, 0xc8147c55, 0xc805fcfd, 0xc85f7e05, -- 0xc85fffbb, 0xc89fffa0, 0xc8dfff95, 0x88157cf8, -- 0x8815ff9a, 0x885f7cd5, 0x885fffcf, 0x889ffc73, -- 0x88dffc56, 0x48127c0f, 0x480bff85, 0x485f7cdd, -- 0x485ffcf2, 0x489fff99, 0x48dffe62, 0x080a7c3e, -- 0x0814fed5, 0x085f7c59, 0x085ffcb8, 0x089ffc70, -- 0x08dfffb6, 0xc87f0a68, 0xc87fcdc7, 0xc82870bb, -- 0xc825b8c8, 0x887f12d9, 0x887fb9ed, 0x8834215a, -- 0x8837ca52, 0xf806317e, 0xb81b3337, 0x39000dc2, -- 0x78005149, 0xf84391f4, 0xb85b220c, 0x385fd356, -- 0x785d127e, 0x389f4149, 0x79801e3c, 0x79c014a3, -- 0xb89a5231, 0xfc5ef282, 0xbc5f60f6, 0xfc12125e, -- 0xbc0152cd, 0xf8190e49, 0xb800befd, 0x381ffd92, -- 0x781e9e90, 0xf8409fa3, 0xb8413c79, 0x385fffa1, -- 0x785c7fa8, 0x389f3dc5, 0x78801f6a, 0x78c19d4b, -- 0xb89a4ec4, 0xfc408eeb, 0xbc436e79, 0xfc152ce1, -- 0xbc036f28, 0xf8025565, 0xb80135f8, 0x381ff74f, -- 0x781fa652, 0xf851a447, 0xb85e557b, 0x385e7472, -- 0x785e070a, 0x38804556, 0x78819591, 0x78dc24e8, -- 0xb89cd6d7, 0xfc430738, 0xbc5f6595, 0xfc1225b2, -- 0xbc1d7430, 0xf82fcac2, 0xb83d6a02, 0x382e5a54, -- 0x7834fa66, 0xf86ecbae, 0xb86cda90, 0x3860d989, -- 0x78637a2c, 0x38a3fa22, 0x78b15827, 0x78f2d9f9, -- 0xb8ac6ab7, 0xfc6879a5, 0xbc767943, 0xfc3bc84e, -- 0xbc3968d4, 0xf91fc0fe, 0xb91da50f, 0x391d280b, -- 0x791d2e23, 0xf95bc8e2, 0xb95ce525, 0x395ae53c, -- 0x795c9282, 0x399d7dd6, 0x799fe008, 0x79de9bc0, -- 0xb99aae78, 0xfd597598, 0xbd5d1d08, 0xfd1f3dea, -- 0xbd1a227a, 0x5800148a, 0x18000003, 0xf88092e0, -- 0xd8ffdf00, 0xf8a84860, 0xf99d7560, 0x1a1c012d, -- 0x3a1c027b, 0x5a060253, 0x7a03028e, 0x9a0801d0, -- 0xba0803a0, 0xda140308, 0xfa00038c, 0x0b3010d7, -- 0x2b37ab39, 0xcb2466da, 0x6b33efb1, 0x8b350fcb, -- 0xab208a70, 0xcb39e52b, 0xeb2c9291, 0x3a4bd1a3, -- 0x7a4c81a2, 0xba42106c, 0xfa5560e3, 0x3a4e3844, -- 0x7a515a26, 0xba4c2940, 0xfa52aaae, 0x1a8cc1b5, -- 0x1a8f976a, 0x5a8981a0, 0x5a9a6492, 0x9a8793ac, -- 0x9a9474e6, 0xda83d2b6, 0xda9b9593, 0x5ac00200, -- 0x5ac006f1, 0x5ac009d1, 0x5ac013d8, 0x5ac016d8, -- 0xdac00223, 0xdac005ac, 0xdac00ac9, 0xdac00c00, -- 0xdac01205, 0xdac016d9, 0x1ac0089d, 0x1add0fa0, -- 0x1ad52225, 0x1ad22529, 0x1ac82b61, 0x1acd2e92, -- 0x9acc0b28, 0x9adc0ca7, 0x9adb2225, 0x9ad42757, -- 0x9adc291c, 0x9ac42fa3, 0x1b1a55d1, 0x1b0bafc1, -- 0x9b067221, 0x9b1ea0de, 0x9b2e20d5, 0x9b38cd4a, -- 0x9bae6254, 0x9ba59452, 0x1e2d0a48, 0x1e3c19c2, -- 0x1e3c298f, 0x1e213980, 0x1e240baf, 0x1e77082c, -- 0x1e72191b, 0x1e6b2a97, 0x1e723988, 0x1e770b1a, -- 0x1f0d66f5, 0x1f01b956, 0x1f227a8e, 0x1f365ba7, -- 0x1f4f14ad, 0x1f45a98e, 0x1f60066a, 0x1f620054, -- 0x1e204139, 0x1e20c094, 0x1e214363, 0x1e21c041, -- 0x1e22c01e, 0x1e60408c, 0x1e60c361, 0x1e6142c8, -- 0x1e61c16b, 0x1e624396, 0x1e3802dc, 0x9e380374, -- 0x1e78000e, 0x9e78017a, 0x1e2202dc, 0x9e220150, -- 0x1e6202a8, 0x9e620395, 0x1e260318, 0x9e660268, -- 0x1e270188, 0x9e6700e6, 0x1e3023c0, 0x1e6b2320, -- 0x1e202168, 0x1e602168, 0x2910323d, 0x297449d6, -- 0x6948402b, 0xa9072f40, 0xa9410747, 0x29801f0a, -- 0x29e07307, 0x69e272b9, 0xa9bf49d4, 0xa9c529a8, -- 0x28b0605a, 0x28e866a2, 0x68ee0ab1, 0xa886296c, -- 0xa8fe1a38, 0x282479c3, 0x286e534f, 0xa8386596, -- 0xa8755a3b, 0x1e601000, 0x1e603000, 0x1e621000, -- 0x1e623000, 0x1e641000, 0x1e643000, 0x1e661000, -- 0x1e663000, 0x1e681000, 0x1e683000, 0x1e6a1000, -- 0x1e6a3000, 0x1e6c1000, 0x1e6c3000, 0x1e6e1000, -- 0x1e6e3000, 0x1e701000, 0x1e703000, 0x1e721000, -- 0x1e723000, 0x1e741000, 0x1e743000, 0x1e761000, -- 0x1e763000, 0x1e781000, 0x1e783000, 0x1e7a1000, -- 0x1e7a3000, 0x1e7c1000, 0x1e7c3000, 0x1e7e1000, -- 0x1e7e3000, -+ 0x8b0d82fa, 0xcb49970c, 0xab889dfc, 0xeb9ee787, -+ 0x0b9b3ec9, 0x4b9279a3, 0x2b88474e, 0x6b8c56c0, -+ 0x8a1a51e0, 0xaa11f4ba, 0xca0281b8, 0xea918c7c, -+ 0x0a5d4a19, 0x2a4b264d, 0x4a523ca5, 0x6a9b6ae2, -+ 0x8a70b79b, 0xaaba9728, 0xca6dfe3d, 0xea627f1c, -+ 0x0aa70f53, 0x2aaa0f06, 0x4a6176a4, 0x6a604eb0, -+ 0x1105ed91, 0x3100583e, 0x5101f8bd, 0x710f0306, -+ 0x9101a1a0, 0xb10a5cc8, 0xd10810aa, 0xf10fd061, -+ 0x120cb166, 0x321764bc, 0x52174681, 0x720c0247, -+ 0x9241018e, 0xb25a2969, 0xd278b411, 0xf26aad01, -+ 0x14000000, 0x17ffffd7, 0x140001cf, 0x94000000, -+ 0x97ffffd4, 0x940001cc, 0x3400000a, 0x34fffa2a, -+ 0x3400392a, 0x35000008, 0x35fff9c8, 0x350038c8, -+ 0xb400000b, 0xb4fff96b, 0xb400386b, 0xb500001d, -+ 0xb5fff91d, 0xb500381d, 0x10000013, 0x10fff8b3, -+ 0x100037b3, 0x90000013, 0x36300016, 0x3637f836, -+ 0x36303736, 0x3758000c, 0x375ff7cc, 0x375836cc, -+ 0x128313a0, 0x528a32c7, 0x7289173b, 0x92ab3acc, -+ 0xd2a0bf94, 0xf2c285e8, 0x9358722f, 0x330e652f, -+ 0x53067f3b, 0x93577c53, 0xb34a1aac, 0xd35a4016, -+ 0x13946c63, 0x93c3dbc8, 0x54000000, 0x54fff5a0, -+ 0x540034a0, 0x54000001, 0x54fff541, 0x54003441, -+ 0x54000002, 0x54fff4e2, 0x540033e2, 0x54000002, -+ 0x54fff482, 0x54003382, 0x54000003, 0x54fff423, -+ 0x54003323, 0x54000003, 0x54fff3c3, 0x540032c3, -+ 0x54000004, 0x54fff364, 0x54003264, 0x54000005, -+ 0x54fff305, 0x54003205, 0x54000006, 0x54fff2a6, -+ 0x540031a6, 0x54000007, 0x54fff247, 0x54003147, -+ 0x54000008, 0x54fff1e8, 0x540030e8, 0x54000009, -+ 0x54fff189, 0x54003089, 0x5400000a, 0x54fff12a, -+ 0x5400302a, 0x5400000b, 0x54fff0cb, 0x54002fcb, -+ 0x5400000c, 0x54fff06c, 0x54002f6c, 0x5400000d, -+ 0x54fff00d, 0x54002f0d, 0x5400000e, 0x54ffefae, -+ 0x54002eae, 0x5400000f, 0x54ffef4f, 0x54002e4f, -+ 0xd40658e1, 0xd4014d22, 0xd4046543, 0xd4273f60, -+ 0xd44cad80, 0xd503201f, 0xd69f03e0, 0xd6bf03e0, -+ 0xd5033fdf, 0xd5033e9f, 0xd50332bf, 0xd61f0200, -+ 0xd63f0280, 0xc80a7d1b, 0xc800fea1, 0xc85f7fb1, -+ 0xc85fff9d, 0xc89ffee1, 0xc8dffe95, 0x88167e7b, -+ 0x880bfcd0, 0x885f7c12, 0x885ffd44, 0x889ffed8, -+ 0x88dffe6a, 0x48017fc5, 0x4808fe2c, 0x485f7dc9, -+ 0x485ffc27, 0x489ffe05, 0x48dffd82, 0x080a7c6c, -+ 0x081cff4e, 0x085f7d5e, 0x085ffeae, 0x089ffd2d, -+ 0x08dfff76, 0xc87f4d7c, 0xc87fcc5e, 0xc8220417, -+ 0xc82cb5f0, 0x887f55b2, 0x887ff90b, 0x88382c2d, -+ 0x883aedb5, 0xf819928b, 0xb803e21c, 0x381f713b, -+ 0x781ce322, 0xf850f044, 0xb85e129e, 0x385e92f2, -+ 0x785ff35d, 0x39801921, 0x7881318b, 0x78dce02b, -+ 0xb8829313, 0xfc45f318, 0xbc5d50af, 0xfc001375, -+ 0xbc1951b7, 0xf8008c0b, 0xb801dc03, 0x38009dcb, -+ 0x781fdf1d, 0xf8570e2d, 0xb85faecc, 0x385f6d8d, -+ 0x785ebea0, 0x38804cf7, 0x789cbce3, 0x78df9cbc, -+ 0xb89eed38, 0xfc40cd6e, 0xbc5bdd93, 0xfc103c14, -+ 0xbc040c08, 0xf81a2784, 0xb81ca4ec, 0x381e855b, -+ 0x7801b506, 0xf853654e, 0xb85d74b0, 0x384095c2, -+ 0x785ec5bc, 0x389e15a9, 0x789dc703, 0x78c06474, -+ 0xb89ff667, 0xfc57e51e, 0xbc4155f9, 0xfc05a6ee, -+ 0xbc1df408, 0xf835da4a, 0xb836d9a4, 0x3833580d, -+ 0x7826cb6c, 0xf8706900, 0xb87ae880, 0x3865db2e, -+ 0x78724889, 0x38a7789b, 0x78beca2f, 0x78f6c810, -+ 0xb8bef956, 0xfc6afabd, 0xbc734963, 0xfc3d5b8d, -+ 0xbc25fbb7, 0xf9189d05, 0xb91ecb1d, 0x39187a33, -+ 0x791f226d, 0xf95aa2f3, 0xb9587bb7, 0x395f7176, -+ 0x795d9143, 0x399e7e08, 0x799a2697, 0x79df3422, -+ 0xb99c2624, 0xfd5c2374, 0xbd5fa1d9, 0xfd1d595a, -+ 0xbd1b1869, 0x58001e9b, 0x1800000b, 0xf8945060, -+ 0xd8000000, 0xf8ae6ba0, 0xf99a0080, 0x1a070035, -+ 0x3a0700a8, 0x5a0e0367, 0x7a11009b, 0x9a000380, -+ 0xba1e030c, 0xda0f0320, 0xfa030301, 0x0b340b12, -+ 0x2b2a278d, 0xcb22aa0f, 0x6b2d29bd, 0x8b2cce8c, -+ 0xab2b877e, 0xcb21c8ee, 0xeb3ba47d, 0x3a4d400e, -+ 0x7a5232c6, 0xba5e624e, 0xfa53814c, 0x3a52d8c2, -+ 0x7a4d8924, 0xba4b3aab, 0xfa4d7882, 0x1a96804c, -+ 0x1a912618, 0x5a90b0e6, 0x5a96976b, 0x9a9db06a, -+ 0x9a9b374c, 0xda95c14f, 0xda89c6fe, 0x5ac0015e, -+ 0x5ac005fd, 0x5ac00bdd, 0x5ac012b9, 0x5ac01404, -+ 0xdac002b2, 0xdac0061d, 0xdac00a95, 0xdac00e66, -+ 0xdac0107e, 0xdac01675, 0x1ac00b0b, 0x1ace0f3b, -+ 0x1ad221c3, 0x1ad825e7, 0x1ad92a3c, 0x1adc2f42, -+ 0x9ada0b25, 0x9ad20e1b, 0x9acc22a6, 0x9acc2480, -+ 0x9adc2a3b, 0x9ad22c5c, 0x1b0e39ea, 0x1b0fcf23, -+ 0x9b1010ae, 0x9b048b3a, 0x9b3d4582, 0x9b2390e8, -+ 0x9bba6499, 0x9ba0ea24, 0x1e2f0af1, 0x1e311b95, -+ 0x1e23295b, 0x1e3938e0, 0x1e2f08c9, 0x1e6a09fd, -+ 0x1e671a22, 0x1e77296b, 0x1e773ba7, 0x1e6b0b6e, -+ 0x1f18308b, 0x1f14adcf, 0x1f2b31bc, 0x1f3a3bd7, -+ 0x1f4a1da9, 0x1f4f8fa5, 0x1f6f798b, 0x1f73523e, -+ 0x1e2040fb, 0x1e20c2a9, 0x1e214122, 0x1e21c0fb, -+ 0x1e22c3dd, 0x1e604031, 0x1e60c0c2, 0x1e61406a, -+ 0x1e61c178, 0x1e624027, 0x1e38000b, 0x9e380243, -+ 0x1e7800dc, 0x9e7800d6, 0x1e220360, 0x9e22005a, -+ 0x1e6200e5, 0x9e62017c, 0x1e2601b9, 0x9e6602eb, -+ 0x1e270113, 0x9e6702b2, 0x1e342320, 0x1e722260, -+ 0x1e202048, 0x1e6023a8, 0x29025668, 0x29403e86, -+ 0x6966387b, 0xa93b316a, 0xa97e38e7, 0x298e5980, -+ 0x29c61d0e, 0x69c00930, 0xa9bc7434, 0xa9c530b5, -+ 0x28b26378, 0x28c25a5c, 0x68f419b1, 0xa8b668bc, -+ 0xa8f15746, 0x280453cd, 0x284c2cb1, 0xa83a534d, -+ 0xa87b32fd, 0x05a08020, 0x04b0e3e0, 0x0470e7e1, -+ 0x042f9c20, 0x043f9c35, 0x047f9c20, 0x04ff9c20, -+ 0x04299420, 0x04319160, 0x0461943e, 0x04a19020, -+ 0x042053ff, 0x047f5401, 0x25208028, 0x2538cfe0, -+ 0x2578d001, 0x25b8efe2, 0x25f8f007, 0xa400a3e0, -+ 0xa4a8a7ea, 0xa547a814, 0xa4084ffe, 0xa55c53e0, -+ 0xa5e1540b, 0xe400fbf6, 0xe408ffff, 0xe547e400, -+ 0xe4014be0, 0xe4a84fe0, 0xe5f25000, 0x858043e0, -+ 0x85a043ff, 0xe59f5d08, 0x1e601000, 0x1e603000, -+ 0x1e621000, 0x1e623000, 0x1e641000, 0x1e643000, -+ 0x1e661000, 0x1e663000, 0x1e681000, 0x1e683000, -+ 0x1e6a1000, 0x1e6a3000, 0x1e6c1000, 0x1e6c3000, -+ 0x1e6e1000, 0x1e6e3000, 0x1e701000, 0x1e703000, -+ 0x1e721000, 0x1e723000, 0x1e741000, 0x1e743000, -+ 0x1e761000, 0x1e763000, 0x1e781000, 0x1e783000, -+ 0x1e7a1000, 0x1e7a3000, 0x1e7c1000, 0x1e7c3000, -+ 0x1e7e1000, 0x1e7e3000, 0x04bb020e, 0x04ba04c0, -+ 0x6586019b, 0x6593089e, 0x65c2060b, 0x04d6a18f, -+ 0x040016e9, 0x0490835e, 0x045aaa44, 0x04938579, -+ 0x0411990a, 0x04101624, 0x0497ad3e, 0x04deae80, -+ 0x04481c77, 0x044a0960, 0x04c118ab, 0x049caa30, -+ 0x6580834f, 0x658d9e6a, 0x65c68238, 0x65c791fa, -+ 0x65c28a38, 0x049db7be, 0x6582b552, 0x65c0abde, -+ 0x6581bbc6, 0x65cdb854, 0x658197a9, 0x65f60872, -+ 0x65ec29af, 0x65be43cc, 0x65e06ea7, 0x04544b53, -+ 0x04d57c30, 0x04323095, 0x04a7324c, 0x046d31f9, -+ 0x04da30eb, 0x04d8252b, 0x04d93c1c, 0x044820f0, -+ 0x040a2fac, 0x65873975, 0x65c62886, 0x65d820e7, -+ 0x04013fac, +- 0x8b50798f, 0xcb4381e1, 0xab05372d, 0xeb864796, +- 0x0b961920, 0x4b195473, 0x2b0b5264, 0x6b9300f8, +- 0x8a0bc0fe, 0xaa0f3118, 0xca170531, 0xea44dd6e, +- 0x0a4c44f3, 0x2a8b7373, 0x4a567c7e, 0x6a9c0353, +- 0x8a3accdd, 0xaa318f7a, 0xca2e1495, 0xeaa015e2, +- 0x0a2274e2, 0x2a751598, 0x4a3309fe, 0x6ab172fe, +- 0x110a5284, 0x310b1942, 0x5103d353, 0x710125bc, +- 0x910d7bc2, 0xb108fa1b, 0xd1093536, 0xf10ae824, +- 0x120e667c, 0x321f6cbb, 0x520f6a9e, 0x72136f56, +- 0x927e4ce5, 0xb278b4ed, 0xd24c6527, 0xf2485803, ++ 0x8b4db437, 0xcb8ce3c8, 0xab0edafb, 0xeb5499f5, ++ 0x0b040e39, 0x4b89503d, 0x2b89274a, 0x6b870fd5, ++ 0x8a4b1109, 0xaa810643, 0xca026e8a, 0xea8b7d2c, ++ 0x0a9e6934, 0x2a9a4555, 0x4a871d00, 0x6a084973, ++ 0x8a23d497, 0xaa3360c9, 0xca7ad8cc, 0xea2c3a76, ++ 0x0a362dbd, 0x2ab417d1, 0x4a2b23a1, 0x6a667684, ++ 0x1107e0de, 0x310ebd13, 0x5105b55d, 0x71047104, ++ 0x910ef9c3, 0xb1029e96, 0xd10b55fb, 0xf10ecf98, ++ 0x12099f39, 0x321b3f4d, 0x520309b5, 0x72134062, ++ 0x92004548, 0xb24d861b, 0xd219587b, 0xf25eaee4, + 0x14000000, 0x17ffffd7, 0x140001ee, 0x94000000, +- 0x97ffffd4, 0x940001eb, 0x34000010, 0x34fffa30, +- 0x34003d10, 0x35000013, 0x35fff9d3, 0x35003cb3, +- 0xb4000005, 0xb4fff965, 0xb4003c45, 0xb5000004, +- 0xb5fff904, 0xb5003be4, 0x1000001b, 0x10fff8bb, +- 0x10003b9b, 0x90000010, 0x3640001c, 0x3647f83c, +- 0x36403b1c, 0x37080001, 0x370ff7c1, 0x37083aa1, +- 0x12a437f4, 0x528c9d67, 0x72838bb1, 0x92c1062e, +- 0xd287da49, 0xf2a6d153, 0x93465ac9, 0x330b0013, +- 0x530b4e6a, 0x934545e4, 0xb35370a3, 0xd3510b8c, +- 0x13960c0f, 0x93ceddc6, 0x54000000, 0x54fff5a0, ++ 0x97ffffd4, 0x940001eb, 0x34000003, 0x34fffa23, ++ 0x34003d03, 0x35000002, 0x35fff9c2, 0x35003ca2, ++ 0xb4000019, 0xb4fff979, 0xb4003c59, 0xb5000012, ++ 0xb5fff912, 0xb5003bf2, 0x10000008, 0x10fff8a8, ++ 0x10003b88, 0x9000000f, 0x36700012, 0x3677f832, ++ 0x36703b12, 0x37780019, 0x377ff7d9, 0x37783ab9, ++ 0x12a203d2, 0x5286b21e, 0x72a66d35, 0x92eded92, ++ 0xd2eefecd, 0xf2ef69a3, 0x93400c2a, 0x330562cc, ++ 0x530b2071, 0x934b3860, 0xb3473cdc, 0xd3416549, ++ 0x13995f75, 0x93d6462e, 0x54000000, 0x54fff5a0, + 0x54003880, 0x54000001, 0x54fff541, 0x54003821, + 0x54000002, 0x54fff4e2, 0x540037c2, 0x54000002, + 0x54fff482, 0x54003762, 0x54000003, 0x54fff423, +@@ -1336,77 +1336,77 @@ Disassembly of section .text: + 0x5400000c, 0x54fff06c, 0x5400334c, 0x5400000d, + 0x54fff00d, 0x540032ed, 0x5400000e, 0x54ffefae, + 0x5400328e, 0x5400000f, 0x54ffef4f, 0x5400322f, +- 0xd40ac601, 0xd40042a2, 0xd404dac3, 0xd4224d40, +- 0xd44219c0, 0xd503201f, 0xd69f03e0, 0xd6bf03e0, +- 0xd5033fdf, 0xd503339f, 0xd50335bf, 0xd61f0280, +- 0xd63f0040, 0xc8127c17, 0xc81efec5, 0xc85f7d05, +- 0xc85ffe14, 0xc89ffd66, 0xc8dfff66, 0x880a7cb1, +- 0x8816fd89, 0x885f7d1b, 0x885ffc57, 0x889fffba, +- 0x88dffd4d, 0x48197f7c, 0x481dfd96, 0x485f7f96, +- 0x485fffc3, 0x489ffdf8, 0x48dfff5b, 0x080b7e6a, +- 0x0817fedb, 0x085f7e18, 0x085ffc38, 0x089fffa5, +- 0x08dffe18, 0xc87f6239, 0xc87fb276, 0xc820573a, +- 0xc821aca6, 0x887f388d, 0x887f88d1, 0x882f2643, +- 0x88329131, 0xf81cf2b7, 0xb803f055, 0x39002f9b, +- 0x781f31fd, 0xf85d33ce, 0xb843539d, 0x39401f54, +- 0x785ce059, 0x389f1143, 0x788131ee, 0x78dfb17d, +- 0xb89b90af, 0xfc403193, 0xbc42a36c, 0xfc07d396, +- 0xbc1ec1f8, 0xf81e8f88, 0xb8025de6, 0x38007c27, +- 0x7801ee20, 0xf8454fb9, 0xb85cce9a, 0x385e7fba, +- 0x7841af24, 0x389ebd1c, 0x789fadd1, 0x78c0aefc, +- 0xb89c0f7e, 0xfc50efd4, 0xbc414f71, 0xfc011c67, +- 0xbc1f0d6d, 0xf81c3526, 0xb81e34b0, 0x3800f7bd, +- 0x78012684, 0xf842e653, 0xb8417456, 0x385e2467, +- 0x785e358b, 0x389e34c8, 0x788046f8, 0x78c00611, +- 0xb89f8680, 0xfc582454, 0xbc5987d3, 0xfc076624, +- 0xbc190675, 0xf833785a, 0xb82fd809, 0x3821799a, +- 0x782a7975, 0xf870eaf0, 0xb871d96a, 0x386b7aed, +- 0x7875689b, 0x38afd91a, 0x78a2c955, 0x78ee6bc8, +- 0xb8b4f9dd, 0xfc76eb7e, 0xbc76692d, 0xfc31db28, +- 0xbc255b01, 0xf91c52aa, 0xb91c3fb2, 0x391f8877, +- 0x791ac97c, 0xf95c1758, 0xb95b3c55, 0x395ce0a4, +- 0x795851ce, 0x399e9f64, 0x79993764, 0x79d9af8a, +- 0xb99eea2a, 0xfd5a2f8d, 0xbd5dac78, 0xfd1e0182, +- 0xbd195c31, 0x58000010, 0x1800000d, 0xf8981240, +- 0xd8ffdf00, 0xf8a27a80, 0xf99af920, 0x1a0202e8, +- 0x3a130078, 0x5a1d0316, 0x7a03036c, 0x9a0102eb, +- 0xba1700bd, 0xda0c0329, 0xfa16000c, 0x0b23459a, +- 0x2b328a14, 0xcb274bde, 0x6b222eab, 0x8b214b42, +- 0xab34a7b2, 0xcb24520e, 0xeb378e20, 0x3a565283, +- 0x7a420321, 0xba58c247, 0xfa4d5106, 0x3a426924, +- 0x7a5b0847, 0xba413a02, 0xfa5fba23, 0x1a979377, +- 0x1a86640a, 0x5a89300b, 0x5a923771, 0x9a8b720c, +- 0x9a868786, 0xda9a736d, 0xda9256dd, 0x5ac0026c, +- 0x5ac00657, 0x5ac00b89, 0x5ac01262, 0x5ac017b9, +- 0xdac002e4, 0xdac0065d, 0xdac00907, 0xdac00e2d, +- 0xdac01011, 0xdac01752, 0x1ad0098b, 0x1ac70d24, +- 0x1ad020ec, 0x1ad72613, 0x1ac62887, 0x1ad72e95, +- 0x9adc0990, 0x9acd0d84, 0x9ac721a9, 0x9acf277c, +- 0x9ace2bd4, 0x9ade2e4e, 0x9bc77d63, 0x9b587e97, +- 0x1b1524a2, 0x1b04a318, 0x9b0f4d8b, 0x9b0ce73d, +- 0x9b2c5971, 0x9b34c87c, 0x9bbc6887, 0x9bb19556, +- 0x1e310871, 0x1e261a2b, 0x1e2928fd, 0x1e333987, +- 0x1e230ae0, 0x1e75087a, 0x1e651a60, 0x1e692b40, +- 0x1e753ab9, 0x1e7309b0, 0x1f00425d, 0x1f1d95b7, +- 0x1f2a38e9, 0x1f2f5f99, 0x1f5545a6, 0x1f429ea3, +- 0x1f65472a, 0x1f7449ce, 0x1e20404f, 0x1e20c0f2, +- 0x1e2140c3, 0x1e21c02c, 0x1e22c009, 0x1e6040a4, +- 0x1e60c1e3, 0x1e614331, 0x1e61c30c, 0x1e6240b5, +- 0x1e3802a4, 0x9e38007b, 0x1e78011d, 0x9e7802a9, +- 0x1e2203b4, 0x9e220107, 0x1e6202ac, 0x9e6202b0, +- 0x1e2600b2, 0x9e660119, 0x1e270352, 0x9e670160, +- 0x1e262200, 0x1e7d2200, 0x1e2023c8, 0x1e602128, +- 0x293e119b, 0x294a2543, 0x69480c70, 0xa934726a, +- 0xa97448f3, 0x298243ca, 0x29e21242, 0x69c64db8, +- 0xa9800311, 0xa9f4686e, 0x288a0416, 0x28fe2812, +- 0x68fe62d8, 0xa885308c, 0xa8f12664, 0x282468d2, +- 0x284e5035, 0xa8327699, 0xa84716e1, 0x0c407284, +- 0x4cdfa158, 0x0ccf6cd8, 0x4cdf2483, 0x0d40c0c2, +- 0x4ddfc9cd, 0x0dd8ceaf, 0x4c408ea9, 0x0cdf86bd, +- 0x4d60c1c8, 0x0dffca87, 0x4de3cc7c, 0x4cdd497b, +- 0x0c404950, 0x4d40e595, 0x4ddfeba4, 0x0dd3ed38, +- 0x4cdf046a, 0x0cc9039b, 0x0d60e3d5, 0x0dffe5d7, +- 0x0df4e9a4, 0xba5fd3e3, 0x3a5f03e5, 0xfa411be4, ++ 0xd40f9ca1, 0xd4008b22, 0xd40be1c3, 0xd423d0e0, ++ 0xd44dee20, 0xd503201f, 0xd69f03e0, 0xd6bf03e0, ++ 0xd5033fdf, 0xd503359f, 0xd50337bf, 0xd61f0380, ++ 0xd63f0220, 0xc8127f47, 0xc819fccc, 0xc85f7e00, ++ 0xc85ffc66, 0xc89ffc2e, 0xc8dfff1d, 0x881c7eef, ++ 0x8809fc67, 0x885f7e81, 0x885ffdf4, 0x889ffd35, ++ 0x88dffe25, 0x480d7fd4, 0x480afe4c, 0x485f7e64, ++ 0x485ffd56, 0x489ffdfe, 0x48dfff04, 0x080a7d94, ++ 0x0814fd7d, 0x085f7cb5, 0x085ffd24, 0x089fff9e, ++ 0x08dfff13, 0xc87f424b, 0xc87f9de8, 0xc83c4154, ++ 0xc827d469, 0x887f1a79, 0x887fa45e, 0x88305180, ++ 0x88259f82, 0xf81b5270, 0xb801e381, 0x381e61bc, ++ 0x781cd0c8, 0xf851d380, 0xb85e615c, 0x39403164, ++ 0x78405221, 0x3980312b, 0x789ef108, 0x78ddd1b4, ++ 0xb8831137, 0xfc41d089, 0xbd402a6b, 0xfc1d5299, ++ 0xbc1b0039, 0xf8019c14, 0xb81cfd8c, 0x381f6e7c, ++ 0x781c1f8d, 0xf85d2eeb, 0xb8411f1b, 0x385f4f4e, ++ 0x785d3ed8, 0x389f5d39, 0x7881dcc5, 0x78dffee7, ++ 0xb89c3dba, 0xfc50bf18, 0xbc5c9f34, 0xfc135c49, ++ 0xbc1c5c2e, 0xf806d433, 0xb81ca4a4, 0x3800947d, ++ 0x781ce420, 0xf85d04c2, 0xb858d4cf, 0x385e5444, ++ 0x785eb751, 0x389f3715, 0x789d04d6, 0x78dd04cb, ++ 0xb89fb7ce, 0xfc5975e2, 0xbc5a5679, 0xfc1416ed, ++ 0xbc0006b6, 0xf832c996, 0xb82c4b7e, 0x38367887, ++ 0x783dfaf3, 0xf87bf891, 0xb871c9a1, 0x387dfb70, ++ 0x78645939, 0x38b67984, 0x78a55839, 0x78fc6a09, ++ 0xb8aee8e8, 0xfc705b84, 0xbc7bd850, 0xfc396817, ++ 0xbc277a06, 0xf91ddd82, 0xb91b10a8, 0x391f8221, ++ 0x79197728, 0xf95ca07c, 0xb95b5d75, 0x395dc8af, ++ 0x795caa60, 0x399dd53d, 0x799c7397, 0x79dcb15b, ++ 0xb99e3b75, 0xfd5c7f7a, 0xbd5d2882, 0xfd1fb2a1, ++ 0xbd1d82c4, 0x58000001, 0x1800001b, 0xf882d080, ++ 0xd8000000, 0xf8a0cbc0, 0xf99fab00, 0x1a1803a0, ++ 0x3a120396, 0x5a1e0217, 0x7a0e03a7, 0x9a0e0196, ++ 0xba17031d, 0xda160391, 0xfa130298, 0x0b26cadb, ++ 0x2b38516d, 0xcb242d10, 0x6b34ea55, 0x8b3d0a2e, ++ 0xab2eb231, 0xcb3ac476, 0xeb3531ad, 0x3a5a722f, ++ 0x7a463325, 0xba5e9021, 0xfa47a222, 0x3a590a26, ++ 0x7a450845, 0xba514a6a, 0xfa48c9c3, 0x1a8e9109, ++ 0x1a85d57b, 0x5a9632eb, 0x5a9b2793, 0x9a815130, ++ 0x9a8c05dc, 0xda8e5096, 0xda9b257a, 0x5ac00178, ++ 0x5ac005ca, 0x5ac008a9, 0x5ac01292, 0x5ac01519, ++ 0xdac00316, 0xdac0077c, 0xdac00ba8, 0xdac00d51, ++ 0xdac01177, 0xdac015da, 0x1adc0895, 0x1ad60d5e, ++ 0x1ada205d, 0x1aca26dc, 0x1acc2b0b, 0x1ad02fd5, ++ 0x9acd0801, 0x9ac60e22, 0x9ad5230a, 0x9ac62525, ++ 0x9ac42b60, 0x9ac22c9c, 0x9bc77fc1, 0x9b4a7cbe, ++ 0x1b0d45e7, 0x1b0cf039, 0x9b1e2562, 0x9b03dae5, ++ 0x9b291159, 0x9b27c905, 0x9bba64b8, 0x9bbaf02e, ++ 0x1e280ad8, 0x1e261870, 0x1e392ab0, 0x1e3b3b40, ++ 0x1e310878, 0x1e660909, 0x1e7e1a76, 0x1e632a2e, ++ 0x1e743b78, 0x1e76082c, 0x1f0b7510, 0x1f128676, ++ 0x1f38270f, 0x1f2d5e7b, 0x1f503003, 0x1f52a873, ++ 0x1f6b5041, 0x1f79392c, 0x1e2042e0, 0x1e20c0d7, ++ 0x1e214084, 0x1e21c385, 0x1e22c1f5, 0x1e6040ab, ++ 0x1e60c092, 0x1e61418b, 0x1e61c10f, 0x1e624048, ++ 0x1e380253, 0x9e380011, 0x1e7801a0, 0x9e780136, ++ 0x1e2203a6, 0x9e2201cc, 0x1e6202d0, 0x9e6200ae, ++ 0x1e260007, 0x9e6600dc, 0x1e270342, 0x9e670004, ++ 0x1e2b2020, 0x1e7520c0, 0x1e202208, 0x1e6022c8, ++ 0x290c0045, 0x2978766e, 0x696c0c6f, 0xa9323767, ++ 0xa9483831, 0x29905895, 0x29f43451, 0x69ee66f5, ++ 0xa9bf41e4, 0xa9f6573d, 0x288a4758, 0x28e27bc3, ++ 0x68fc4fc3, 0xa8b70779, 0xa8fc539a, 0x283a653d, ++ 0x28703a79, 0xa8025879, 0xa8734ba9, 0x0c407275, ++ 0x4cdfa29b, 0x0cc66ec5, 0x4cdf2596, 0x0d40c131, ++ 0x4ddfcaa5, 0x0dd2cf8a, 0x4c408dfa, 0x0cdf8750, ++ 0x4d60c04e, 0x0dffcb92, 0x4df6cc13, 0x4cd24850, ++ 0x0c404818, 0x4d40e604, 0x4ddfe825, 0x0dd0ed47, ++ 0x4cdf0696, 0x0cd9008f, 0x0d60e0a0, 0x0dffe420, ++ 0x0deeeb9e, 0xba5fd3e3, 0x3a5f03e5, 0xfa411be4, + 0x7a42cbe2, 0x93df03ff, 0xc820ffff, 0x8822fc7f, + 0xc8247cbf, 0x88267fff, 0x4e010fe0, 0x4e081fe1, + 0x4e0c1fe1, 0x4e0a1fe1, 0x4e071fe1, 0x4cc0ac3f, +@@ -1418,24 +1418,24 @@ Disassembly of section .text: + 0x1e741000, 0x1e743000, 0x1e761000, 0x1e763000, + 0x1e781000, 0x1e783000, 0x1e7a1000, 0x1e7a3000, + 0x1e7c1000, 0x1e7c3000, 0x1e7e1000, 0x1e7e3000, +- 0xf8358305, 0xf82d01ed, 0xf8361353, 0xf839234a, +- 0xf82531fb, 0xf8335165, 0xf83a4080, 0xf83673d7, +- 0xf832611c, 0xf8ad837d, 0xf8ab01a5, 0xf8a112b8, +- 0xf8bb2311, 0xf8b230be, 0xf8a75336, 0xf8a4427a, +- 0xf8a6707e, 0xf8b860b7, 0xf8f88392, 0xf8f300ff, +- 0xf8ed1386, 0xf8e822af, 0xf8e2302d, 0xf8f1533d, +- 0xf8f941d2, 0xf8ff7366, 0xf8f061e5, 0xf86b8072, +- 0xf87a0054, 0xf86b1164, 0xf87e22f3, 0xf86331cf, +- 0xf87e5296, 0xf8674305, 0xf87771f0, 0xf86b6013, +- 0xb83c803c, 0xb82b0195, 0xb83d1240, 0xb8252320, +- 0xb82e3340, 0xb83c53b2, 0xb82f43a1, 0xb828739a, +- 0xb831608e, 0xb8b88039, 0xb8aa0231, 0xb8bd12b4, +- 0xb8bd2189, 0xb8ab30a6, 0xb8b552a7, 0xb8aa4197, +- 0xb8b57145, 0xb8be6254, 0xb8ed80b7, 0xb8ef00b8, +- 0xb8e9132a, 0xb8f42231, 0xb8ec33d2, 0xb8e35323, +- 0xb8fa4159, 0xb8e273eb, 0xb8e760a2, 0xb8608287, +- 0xb865005f, 0xb87b1379, 0xb87e2358, 0xb86f32c2, +- 0xb86053e3, 0xb86f4154, 0xb87671d5, 0xb866605e, ++ 0xf83a8229, 0xf83c0057, 0xf8361062, 0xf82b23d9, ++ 0xf836309c, 0xf826530b, 0xf82c43ff, 0xf837713e, ++ 0xf8266281, 0xf8b182c2, 0xf8ae015b, 0xf8a6127e, ++ 0xf8a02179, 0xf8b733c0, 0xf8b55143, 0xf8af4016, ++ 0xf8b17280, 0xf8b0602d, 0xf8fb82ef, 0xf8f3003e, ++ 0xf8ef12fc, 0xf8e7226f, 0xf8eb314c, 0xf8e65187, ++ 0xf8fc41a5, 0xf8e97234, 0xf8f56179, 0xf8738318, ++ 0xf86803da, 0xf8711112, 0xf8622063, 0xf87a3207, ++ 0xf87b50a6, 0xf8764280, 0xf86b705a, 0xf87e609d, ++ 0xb82480e5, 0xb82a005a, 0xb83b1370, 0xb83f2157, ++ 0xb82431a2, 0xb823506f, 0xb82340ca, 0xb828714b, ++ 0xb83d61be, 0xb8ab8291, 0xb8ba00d0, 0xb8b5102a, ++ 0xb8bd22ec, 0xb8bd3108, 0xb8ab51ca, 0xb8a442cd, ++ 0xb8a770ed, 0xb8ae63e0, 0xb8f18382, 0xb8f3014b, ++ 0xb8ec1293, 0xb8e02108, 0xb8f13303, 0xb8f950e5, ++ 0xb8f0413e, 0xb8ea71df, 0xb8f16173, 0xb87481a1, ++ 0xb87a028b, 0xb87213d8, 0xb86c2299, 0xb86e30bd, ++ 0xb862537a, 0xb879417b, 0xb86470fd, 0xb870615d, + }; // END Generated code -- do not edit - diff --git a/src/hotspot/cpu/aarch64/assembler_aarch64.hpp b/src/hotspot/cpu/aarch64/assembler_aarch64.hpp -index 80ddb9b31..f554b5e15 100644 +index 0824ca393..dc2d5e2c9 100644 --- a/src/hotspot/cpu/aarch64/assembler_aarch64.hpp +++ b/src/hotspot/cpu/aarch64/assembler_aarch64.hpp @@ -139,6 +139,9 @@ REGISTER_DECLARATION(Register, rdispatch, r21); @@ -5578,18 +5823,7 @@ index 80ddb9b31..f554b5e15 100644 }; // Convience classes -@@ -596,7 +619,9 @@ class InternalAddress: public Address { - InternalAddress(address target) : Address(target, relocInfo::internal_word_type) {} - }; - --const int FPUStateSizeInWords = 32 * 2; -+const int FPUStateSizeInWords = FloatRegisterImpl::number_of_registers * -+ FloatRegisterImpl::save_slots_per_register; -+ - typedef enum { - PLDL1KEEP = 0b00000, PLDL1STRM, PLDL2KEEP, PLDL2STRM, PLDL3KEEP, PLDL3STRM, - PSTL1KEEP = 0b10000, PSTL1STRM, PSTL2KEEP, PSTL2STRM, PSTL3KEEP, PSTL3STRM, -@@ -667,6 +692,12 @@ public: +@@ -669,6 +692,12 @@ public: void rf(FloatRegister reg, int lsb) { current->rf(reg, lsb); } @@ -5602,43 +5836,7 @@ index 80ddb9b31..f554b5e15 100644 void fixed(unsigned value, unsigned mask) { current->fixed(value, mask); } -@@ -2228,21 +2259,27 @@ public: - - #undef INSN - --#define INSN(NAME, opc, opc2) \ -+#define INSN(NAME, opc, opc2, accepted) \ - void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \ -+ guarantee(T != T1Q && T != T1D, "incorrect arrangement"); \ -+ if (accepted < 3) guarantee(T != T2D, "incorrect arrangement"); \ -+ if (accepted < 2) guarantee(T != T2S, "incorrect arrangement"); \ -+ if (accepted < 1) guarantee(T == T8B || T == T16B, "incorrect arrangement"); \ - starti; \ - f(0, 31), f((int)T & 1, 30), f(opc, 29), f(0b01110, 28, 24); \ - f((int)T >> 1, 23, 22), f(opc2, 21, 10); \ - rf(Vn, 5), rf(Vd, 0); \ - } - -- INSN(absr, 0, 0b100000101110); -- INSN(negr, 1, 0b100000101110); -- INSN(notr, 1, 0b100000010110); -- INSN(addv, 0, 0b110001101110); -- INSN(cls, 0, 0b100000010010); -- INSN(clz, 1, 0b100000010010); -- INSN(cnt, 0, 0b100000010110); -+ INSN(absr, 0, 0b100000101110, 3); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D -+ INSN(negr, 1, 0b100000101110, 3); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D -+ INSN(notr, 1, 0b100000010110, 0); // accepted arrangements: T8B, T16B -+ INSN(addv, 0, 0b110001101110, 1); // accepted arrangements: T8B, T16B, T4H, T8H, T4S -+ INSN(cls, 0, 0b100000010010, 2); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S -+ INSN(clz, 1, 0b100000010010, 2); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S -+ INSN(cnt, 0, 0b100000010110, 0); // accepted arrangements: T8B, T16B -+ INSN(uaddlp, 1, 0b100000001010, 2); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S -+ INSN(uaddlv, 1, 0b110000001110, 1); // accepted arrangements: T8B, T16B, T4H, T8H, T4S - - #undef INSN - -@@ -2376,13 +2413,18 @@ public: +@@ -2431,13 +2460,18 @@ public: f(sidx<<(int)T, 14, 11), f(1, 10), rf(Vn, 5), rf(Vd, 0); } @@ -5662,7 +5860,7 @@ index 80ddb9b31..f554b5e15 100644 #define INSN(NAME, opc, opc2, isSHR) \ void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, int shift){ \ starti; \ -@@ -2582,13 +2624,299 @@ public: +@@ -2670,13 +2704,299 @@ public: #undef INSN void ext(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm, int index) @@ -5923,7 +6121,7 @@ index 80ddb9b31..f554b5e15 100644 + INSN(sve_dec, 1); +#undef INSN + -+ // SVE predicate count ++// SVE predicate count + void sve_cntp(Register Xd, SIMD_RegVariant T, PRegister Pg, PRegister Pn) { + starti; + assert(T != Q, "invalid size"); @@ -6001,20 +6199,18 @@ index 071845e5b..f26ea2a8b 100644 "Use DC ZVA for block zeroing") \ product(intx, BlockZeroingLowLimit, 256, \ diff --git a/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp b/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp -index 241197075..431c5f005 100644 +index aecab30c1..b6b070e62 100644 --- a/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp -@@ -50,6 +50,9 @@ - #include "runtime/jniHandles.inline.hpp" - #include "runtime/sharedRuntime.hpp" - #include "runtime/thread.hpp" -+#ifdef COMPILER2 +@@ -53,6 +53,7 @@ + #include "opto/compile.hpp" + #include "opto/intrinsicnode.hpp" + #include "opto/node.hpp" +#include "opto/matcher.hpp" -+#endif + #endif #ifdef PRODUCT - #define BLOCK_COMMENT(str) /* nothing */ -@@ -2098,8 +2098,17 @@ int MacroAssembler::pop(unsigned int bitset, Register stack) { +@@ -2110,8 +2110,17 @@ int MacroAssembler::pop(unsigned int bitset, Register stack) { } // Push lots of registers in the bit set supplied. Don't push sp. @@ -6033,7 +6229,7 @@ index 241197075..431c5f005 100644 // Scan bitset to accumulate register pairs unsigned char regs[32]; int count = 0; -@@ -2114,8 +2123,18 @@ int MacroAssembler::push_fp(unsigned int bitset, Register stack) { +@@ -2126,8 +2135,18 @@ int MacroAssembler::push_fp(unsigned int bitset, Register stack) { return 0; } @@ -6052,7 +6248,7 @@ index 241197075..431c5f005 100644 if (count & 1) { strq(as_FloatRegister(regs[0]), Address(stack)); i += 1; -@@ -2128,7 +2147,16 @@ int MacroAssembler::push_fp(unsigned int bitset, Register stack) { +@@ -2140,7 +2159,16 @@ int MacroAssembler::push_fp(unsigned int bitset, Register stack) { return count; } @@ -6069,7 +6265,7 @@ index 241197075..431c5f005 100644 // Scan bitset to accumulate register pairs unsigned char regs[32]; int count = 0; -@@ -2143,6 +2171,16 @@ int MacroAssembler::pop_fp(unsigned int bitset, Register stack) { +@@ -2155,6 +2183,16 @@ int MacroAssembler::pop_fp(unsigned int bitset, Register stack) { return 0; } @@ -6086,7 +6282,7 @@ index 241197075..431c5f005 100644 if (count & 1) { ldrq(as_FloatRegister(regs[0]), Address(stack)); i += 1; -@@ -2616,23 +2654,39 @@ void MacroAssembler::pop_call_clobbered_registers() { +@@ -2630,23 +2668,39 @@ void MacroAssembler::pop_call_clobbered_registers() { pop(RegSet::range(r0, r18) - RegSet::of(rscratch1, rscratch2), sp); } @@ -6139,7 +6335,7 @@ index 241197075..431c5f005 100644 pop(0x3fffffff, sp); // integer registers except lr & sp } -@@ -2681,6 +2735,21 @@ Address MacroAssembler::spill_address(int size, int offset, Register tmp) +@@ -2695,6 +2749,21 @@ Address MacroAssembler::spill_address(int size, int offset, Register tmp) return Address(base, offset); } @@ -6161,7 +6357,7 @@ index 241197075..431c5f005 100644 // Checks whether offset is aligned. // Returns true if it is, else false. bool MacroAssembler::merge_alignment_check(Register base, -@@ -5843,3 +5912,24 @@ void MacroAssembler::get_thread(Register dst) { +@@ -5879,3 +5948,24 @@ void MacroAssembler::get_thread(Register dst) { pop(saved_regs, sp); } @@ -6187,7 +6383,7 @@ index 241197075..431c5f005 100644 + bind(verify_ok); +} diff --git a/src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp b/src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp -index 014a4d3c6..9fb98c010 100644 +index 85fdc0c88..dccd24911 100644 --- a/src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp +++ b/src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp @@ -862,8 +862,10 @@ public: @@ -6215,7 +6411,7 @@ index 014a4d3c6..9fb98c010 100644 // Debugging -@@ -1307,6 +1314,7 @@ private: +@@ -1319,6 +1326,7 @@ private: // Returns an address on the stack which is reachable with a ldr/str of size // Uses rscratch2 if the address is not directly reachable Address spill_address(int size, int offset, Register tmp=rscratch2); @@ -6223,7 +6419,7 @@ index 014a4d3c6..9fb98c010 100644 bool merge_alignment_check(Register base, size_t size, long cur_offset, long prev_offset) const; -@@ -1330,6 +1338,9 @@ public: +@@ -1342,6 +1350,9 @@ public: void spill(FloatRegister Vx, SIMD_RegVariant T, int offset) { str(Vx, T, spill_address(1 << (int)T, offset)); } @@ -6233,7 +6429,7 @@ index 014a4d3c6..9fb98c010 100644 void unspill(Register Rx, bool is64, int offset) { if (is64) { ldr(Rx, spill_address(8, offset)); -@@ -1340,6 +1351,9 @@ public: +@@ -1352,6 +1363,9 @@ public: void unspill(FloatRegister Vx, SIMD_RegVariant T, int offset) { ldr(Vx, T, spill_address(1 << (int)T, offset)); } @@ -6243,7 +6439,7 @@ index 014a4d3c6..9fb98c010 100644 void spill_copy128(int src_offset, int dst_offset, Register tmp1=rscratch1, Register tmp2=rscratch2) { if (src_offset < 512 && (src_offset & 7) == 0 && -@@ -1353,6 +1367,15 @@ public: +@@ -1365,6 +1379,15 @@ public: spill(tmp1, true, dst_offset+8); } } @@ -6260,7 +6456,7 @@ index 014a4d3c6..9fb98c010 100644 #ifdef ASSERT diff --git a/src/hotspot/cpu/aarch64/register_aarch64.cpp b/src/hotspot/cpu/aarch64/register_aarch64.cpp -index 30924e8a5..3db8e8337 100644 +index 36cbe3fee..3db8e8337 100644 --- a/src/hotspot/cpu/aarch64/register_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/register_aarch64.cpp @@ -1,6 +1,6 @@ @@ -6272,25 +6468,17 @@ index 30924e8a5..3db8e8337 100644 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it -@@ -26,10 +26,15 @@ - #include "precompiled.hpp" - #include "register_aarch64.hpp" +@@ -33,6 +33,9 @@ const int ConcreteRegisterImpl::max_fpr + = ConcreteRegisterImpl::max_gpr + + FloatRegisterImpl::number_of_registers * FloatRegisterImpl::max_slots_per_register; --const int ConcreteRegisterImpl::max_gpr = RegisterImpl::number_of_registers << 1; -+const int ConcreteRegisterImpl::max_gpr = RegisterImpl::number_of_registers * -+ RegisterImpl::max_slots_per_register; - - const int ConcreteRegisterImpl::max_fpr -- = ConcreteRegisterImpl::max_gpr + (FloatRegisterImpl::number_of_registers << 1); -+ = ConcreteRegisterImpl::max_gpr + -+ FloatRegisterImpl::number_of_registers * FloatRegisterImpl::max_slots_per_register; -+ +const int ConcreteRegisterImpl::max_pr + = ConcreteRegisterImpl::max_fpr + PRegisterImpl::number_of_registers; - ++ const char* RegisterImpl::name() const { const char* names[number_of_registers] = { -@@ -52,3 +57,10 @@ const char* FloatRegisterImpl::name() const { + "c_rarg0", "c_rarg1", "c_rarg2", "c_rarg3", "c_rarg4", "c_rarg5", "c_rarg6", "c_rarg7", +@@ -54,3 +57,10 @@ const char* FloatRegisterImpl::name() const { }; return is_valid() ? names[encoding()] : "noreg"; } @@ -6302,7 +6490,7 @@ index 30924e8a5..3db8e8337 100644 + return is_valid() ? names[encoding()] : "noreg"; +} diff --git a/src/hotspot/cpu/aarch64/register_aarch64.hpp b/src/hotspot/cpu/aarch64/register_aarch64.hpp -index 5f7662c89..c211b39ee 100644 +index 75db19977..f6ab3b640 100644 --- a/src/hotspot/cpu/aarch64/register_aarch64.hpp +++ b/src/hotspot/cpu/aarch64/register_aarch64.hpp @@ -1,5 +1,5 @@ @@ -6312,30 +6500,20 @@ index 5f7662c89..c211b39ee 100644 * Copyright (c) 2014, Red Hat Inc. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * -@@ -44,7 +44,8 @@ class RegisterImpl: public AbstractRegisterImpl { - enum { - number_of_registers = 32, - number_of_byte_registers = 32, -- number_of_registers_for_jvmci = 34 // Including SP and ZR. -+ number_of_registers_for_jvmci = 34, // Including SP and ZR. -+ max_slots_per_register = 2 - }; - - // derived registers, offsets, and addresses -@@ -127,7 +128,11 @@ inline FloatRegister as_FloatRegister(int encoding) { - class FloatRegisterImpl: public AbstractRegisterImpl { +@@ -129,9 +129,10 @@ class FloatRegisterImpl: public AbstractRegisterImpl { public: enum { -- number_of_registers = 32 -+ number_of_registers = 32, + number_of_registers = 32, +- max_slots_per_register = 4, + max_slots_per_register = 8, -+ save_slots_per_register = 2, + save_slots_per_register = 2, +- extra_save_slots_per_register = max_slots_per_register - save_slots_per_register + slots_per_neon_register = 4, + extra_save_slots_per_neon_register = slots_per_neon_register - save_slots_per_register }; // construction -@@ -183,6 +188,80 @@ CONSTANT_REGISTER_DECLARATION(FloatRegister, v29 , (29)); +@@ -187,6 +188,79 @@ CONSTANT_REGISTER_DECLARATION(FloatRegister, v29 , (29)); CONSTANT_REGISTER_DECLARATION(FloatRegister, v30 , (30)); CONSTANT_REGISTER_DECLARATION(FloatRegister, v31 , (31)); @@ -6373,7 +6551,6 @@ index 5f7662c89..c211b39ee 100644 +CONSTANT_REGISTER_DECLARATION(FloatRegister, z30 , (30)); +CONSTANT_REGISTER_DECLARATION(FloatRegister, z31 , (31)); + -+ +class PRegisterImpl; +typedef PRegisterImpl* PRegister; +inline PRegister as_PRegister(int encoding) { @@ -6416,15 +6593,11 @@ index 5f7662c89..c211b39ee 100644 // Need to know the total number of registers of all sorts for SharedInfo. // Define a class that exports it. class ConcreteRegisterImpl : public AbstractRegisterImpl { -@@ -193,14 +272,16 @@ class ConcreteRegisterImpl : public AbstractRegisterImpl { - // There is no requirement that any ordering here matches any ordering c2 gives - // it's optoregs. - -- number_of_registers = (2 * RegisterImpl::number_of_registers + -- 4 * FloatRegisterImpl::number_of_registers + -+ number_of_registers = (RegisterImpl::max_slots_per_register * RegisterImpl::number_of_registers + -+ FloatRegisterImpl::max_slots_per_register * FloatRegisterImpl::number_of_registers + -+ PRegisterImpl::max_slots_per_register * PRegisterImpl::number_of_registers + +@@ -199,12 +273,14 @@ class ConcreteRegisterImpl : public AbstractRegisterImpl { + + number_of_registers = (RegisterImpl::max_slots_per_register * RegisterImpl::number_of_registers + + FloatRegisterImpl::max_slots_per_register * FloatRegisterImpl::number_of_registers + ++ PRegisterImpl::max_slots_per_register * PRegisterImpl::number_of_registers + 1) // flags }; @@ -6495,28 +6668,10 @@ index c18109087..e337f582a 100644 + +REGISTER_DEFINITION(PRegister, ptrue); diff --git a/src/hotspot/cpu/aarch64/sharedRuntime_aarch64.cpp b/src/hotspot/cpu/aarch64/sharedRuntime_aarch64.cpp -index da2bc6b05..05cc32e7e 100644 +index 3d3cc3a1e..6242cce08 100644 --- a/src/hotspot/cpu/aarch64/sharedRuntime_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/sharedRuntime_aarch64.cpp -@@ -98,42 +98,60 @@ class RegisterSaver { - // Capture info about frame layout - enum layout { - fpu_state_off = 0, -- fpu_state_end = fpu_state_off+FPUStateSizeInWords-1, -+ fpu_state_end = fpu_state_off + FPUStateSizeInWords - 1, - // The frame sender code expects that rfp will be in - // the "natural" place and will override any oopMap - // setting for it. We must therefore force the layout - // so that it agrees with the frame sender code. -- r0_off = fpu_state_off+FPUStateSizeInWords, -- rfp_off = r0_off + 30 * 2, -- return_off = rfp_off + 2, // slot for return address -- reg_save_size = return_off + 2}; -+ r0_off = fpu_state_off + FPUStateSizeInWords, -+ rfp_off = r0_off + (RegisterImpl::number_of_registers - 2) * RegisterImpl::max_slots_per_register, -+ return_off = rfp_off + RegisterImpl::max_slots_per_register, // slot for return address -+ reg_save_size = return_off + RegisterImpl::max_slots_per_register}; - +@@ -111,11 +111,28 @@ class RegisterSaver { }; OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words, bool save_vectors) { @@ -6535,7 +6690,8 @@ index da2bc6b05..05cc32e7e 100644 + int vect_words = 0; + int extra_save_slots_per_register = 0; // Save upper half of vector registers -- int vect_words = 32 * 8 / wordSize; +- int vect_words = FloatRegisterImpl::number_of_registers * FloatRegisterImpl::extra_save_slots_per_register / +- VMRegImpl::slots_per_word; + if (use_sve) { + extra_save_slots_per_register = sve_vector_size_in_slots - FloatRegisterImpl::save_slots_per_register; + } else { @@ -6546,21 +6702,7 @@ index da2bc6b05..05cc32e7e 100644 additional_frame_words += vect_words; } #else - assert(!save_vectors, "vectors are generated only by C2 and JVMCI"); - #endif - -- int frame_size_in_bytes = align_up(additional_frame_words*wordSize + -- reg_save_size*BytesPerInt, 16); -+ int frame_size_in_bytes = align_up(additional_frame_words * wordSize + -+ reg_save_size * BytesPerInt, 16); - // OopMap frame size is in compiler stack slots (jint's) not bytes or words - int frame_size_in_slots = frame_size_in_bytes / BytesPerInt; - // The caller will allocate additional_frame_words -- int additional_frame_slots = additional_frame_words*wordSize / BytesPerInt; -+ int additional_frame_slots = additional_frame_words * wordSize / BytesPerInt; - // CodeBlob frame size is in words. - int frame_size_in_words = frame_size_in_bytes / wordSize; - *total_frame_words = frame_size_in_words; +@@ -134,7 +151,7 @@ OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_ // Save Integer and Float registers. __ enter(); @@ -6569,26 +6711,12 @@ index da2bc6b05..05cc32e7e 100644 // Set an oopmap for the call site. This oopmap will map all // oop-registers and debug-info registers as callee-saved. This -@@ -146,10 +164,10 @@ OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_ - for (int i = 0; i < RegisterImpl::number_of_registers; i++) { - Register r = as_Register(i); - if (r < rheapbase && r != rscratch1 && r != rscratch2) { -- int sp_offset = 2 * (i + 32); // SP offsets are in 4-byte words, -- // register slots are 8 bytes -- // wide, 32 floating-point -- // registers -+ // SP offsets are in 4-byte words. -+ // Register slots are 8 bytes wide, 32 floating-point registers. -+ int sp_offset = RegisterImpl::max_slots_per_register * i + -+ FloatRegisterImpl::save_slots_per_register * FloatRegisterImpl::number_of_registers; - oop_map->set_callee_saved(VMRegImpl::stack2reg(sp_offset + additional_frame_slots), - r->as_VMReg()); - } -@@ -157,7 +175,13 @@ OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_ +@@ -158,8 +175,13 @@ OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_ for (int i = 0; i < FloatRegisterImpl::number_of_registers; i++) { FloatRegister r = as_FloatRegister(i); -- int sp_offset = save_vectors ? (4 * i) : (2 * i); +- int sp_offset = save_vectors ? (FloatRegisterImpl::max_slots_per_register * i) : +- (FloatRegisterImpl::save_slots_per_register * i); + int sp_offset = 0; + if (save_vectors) { + sp_offset = use_sve ? (sve_vector_size_in_slots * i) : @@ -6599,7 +6727,7 @@ index da2bc6b05..05cc32e7e 100644 oop_map->set_callee_saved(VMRegImpl::stack2reg(sp_offset), r->as_VMReg()); } -@@ -166,10 +190,15 @@ OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_ +@@ -168,10 +190,15 @@ OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_ } void RegisterSaver::restore_live_registers(MacroAssembler* masm, bool restore_vectors) { @@ -6616,7 +6744,7 @@ index da2bc6b05..05cc32e7e 100644 __ leave(); } -@@ -1855,6 +1884,11 @@ nmethod* SharedRuntime::generate_native_wrapper(MacroAssembler* masm, +@@ -1829,6 +1856,11 @@ nmethod* SharedRuntime::generate_native_wrapper(MacroAssembler* masm, __ strw(rscratch1, Address(rthread, JavaThread::thread_state_offset())); } @@ -6628,7 +6756,7 @@ index da2bc6b05..05cc32e7e 100644 // check for safepoint operation in progress and/or pending suspend requests Label safepoint_in_progress, safepoint_in_progress_done; { -@@ -2785,6 +2819,12 @@ SafepointBlob* SharedRuntime::generate_handler_blob(address call_ptr, int poll_t +@@ -2759,6 +2791,12 @@ SafepointBlob* SharedRuntime::generate_handler_blob(address call_ptr, int poll_t __ maybe_isb(); __ membar(Assembler::LoadLoad | Assembler::LoadStore); @@ -6642,10 +6770,10 @@ index da2bc6b05..05cc32e7e 100644 __ cbz(rscratch1, noException); diff --git a/src/hotspot/cpu/aarch64/stubGenerator_aarch64.cpp b/src/hotspot/cpu/aarch64/stubGenerator_aarch64.cpp -index 0310463ac..979ff51f8 100644 +index 26a54c87e..85f64c007 100644 --- a/src/hotspot/cpu/aarch64/stubGenerator_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/stubGenerator_aarch64.cpp -@@ -486,6 +486,11 @@ class StubGenerator: public StubCodeGenerator { +@@ -488,6 +488,11 @@ class StubGenerator: public StubCodeGenerator { __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::exception_handler_for_return_address), rthread, c_rarg1); @@ -6657,7 +6785,7 @@ index 0310463ac..979ff51f8 100644 // we should not really care that lr is no longer the callee // address. we saved the value the handler needs in r19 so we can // just copy it to r3. however, the C2 handler will push its own -@@ -4804,6 +4809,12 @@ class StubGenerator: public StubCodeGenerator { +@@ -5092,6 +5097,12 @@ class StubGenerator: public StubCodeGenerator { __ reset_last_Java_frame(true); __ maybe_isb(); @@ -6671,7 +6799,7 @@ index 0310463ac..979ff51f8 100644 // check for pending exceptions diff --git a/src/hotspot/cpu/aarch64/templateInterpreterGenerator_aarch64.cpp b/src/hotspot/cpu/aarch64/templateInterpreterGenerator_aarch64.cpp -index 6e4eb1a7a..1bb12d24f 100644 +index 03d7a6e2d..42f301531 100644 --- a/src/hotspot/cpu/aarch64/templateInterpreterGenerator_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/templateInterpreterGenerator_aarch64.cpp @@ -1377,6 +1377,11 @@ address TemplateInterpreterGenerator::generate_native_entry(bool synchronized) { @@ -6687,16 +6815,15 @@ index 6e4eb1a7a..1bb12d24f 100644 __ mov(rscratch1, _thread_in_native_trans); __ lea(rscratch2, Address(rthread, JavaThread::thread_state_offset())); diff --git a/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp b/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp -index 04ae1167d..8f2c95e8b 100644 +index e906454f1..7ae881b74 100644 --- a/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp -@@ -29,13 +29,15 @@ - #include "memory/resourceArea.hpp" +@@ -30,12 +30,14 @@ #include "runtime/java.hpp" #include "runtime/stubCodeGenerator.hpp" + #include "runtime/vm_version.hpp" +#include "utilities/formatBuffer.hpp" #include "utilities/macros.hpp" - #include "vm_version_aarch64.hpp" #include OS_HEADER_INLINE(os) @@ -6735,7 +6862,7 @@ index 04ae1167d..8f2c95e8b 100644 VM_Version::PsrInfo VM_Version::_psr_info = { 0, }; static BufferBlob* stub_blob; -@@ -160,6 +177,7 @@ void VM_Version::get_processor_features() { +@@ -164,6 +181,7 @@ void VM_Version::get_processor_features() { } unsigned long auxv = getauxval(AT_HWCAP); @@ -6743,7 +6870,7 @@ index 04ae1167d..8f2c95e8b 100644 char buf[512]; -@@ -250,6 +268,8 @@ void VM_Version::get_processor_features() { +@@ -269,6 +287,8 @@ void VM_Version::get_processor_features() { if (auxv & HWCAP_SHA1) strcat(buf, ", sha1"); if (auxv & HWCAP_SHA2) strcat(buf, ", sha256"); if (auxv & HWCAP_ATOMICS) strcat(buf, ", lse"); @@ -6752,7 +6879,7 @@ index 04ae1167d..8f2c95e8b 100644 _features_string = os::strdup(buf); -@@ -379,6 +399,18 @@ void VM_Version::get_processor_features() { +@@ -402,6 +422,18 @@ void VM_Version::get_processor_features() { FLAG_SET_DEFAULT(UseBlockZeroing, false); } @@ -6771,7 +6898,7 @@ index 04ae1167d..8f2c95e8b 100644 // This machine allows unaligned memory accesses if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) { FLAG_SET_DEFAULT(UseUnalignedAccesses, true); -@@ -411,6 +443,50 @@ void VM_Version::get_processor_features() { +@@ -435,6 +467,50 @@ void VM_Version::get_processor_features() { UseMontgomerySquareIntrinsic = true; } @@ -6819,11 +6946,11 @@ index 04ae1167d..8f2c95e8b 100644 + } + } + - #ifdef COMPILER2 if (FLAG_IS_DEFAULT(OptoScheduling)) { OptoScheduling = true; + } diff --git a/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp b/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp -index 0a17f3e73..23c3c1338 100644 +index dcb6342e1..ae2715102 100644 --- a/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp +++ b/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp @@ -40,6 +40,7 @@ protected: @@ -6842,55 +6969,8 @@ index 0a17f3e73..23c3c1338 100644 static ByteSize dczid_el0_offset() { return byte_offset_of(PsrInfo, dczid_el0); } static ByteSize ctr_el0_offset() { return byte_offset_of(PsrInfo, ctr_el0); } static bool is_zva_enabled() { -diff --git a/src/hotspot/cpu/aarch64/vmreg_aarch64.cpp b/src/hotspot/cpu/aarch64/vmreg_aarch64.cpp -index 9fd20be0f..35d0adf5b 100644 ---- a/src/hotspot/cpu/aarch64/vmreg_aarch64.cpp -+++ b/src/hotspot/cpu/aarch64/vmreg_aarch64.cpp -@@ -33,15 +33,17 @@ void VMRegImpl::set_regName() { - Register reg = ::as_Register(0); - int i; - for (i = 0; i < ConcreteRegisterImpl::max_gpr ; ) { -- regName[i++] = reg->name(); -- regName[i++] = reg->name(); -+ for (int j = 0 ; j < RegisterImpl::max_slots_per_register ; j++) { -+ regName[i++] = reg->name(); -+ } - reg = reg->successor(); - } - - FloatRegister freg = ::as_FloatRegister(0); - for ( ; i < ConcreteRegisterImpl::max_fpr ; ) { -- regName[i++] = freg->name(); -- regName[i++] = freg->name(); -+ for (int j = 0 ; j < FloatRegisterImpl::max_slots_per_register ; j++) { -+ regName[i++] = freg->name(); -+ } - freg = freg->successor(); - } - -diff --git a/src/hotspot/cpu/aarch64/vmreg_aarch64.hpp b/src/hotspot/cpu/aarch64/vmreg_aarch64.hpp -index 0b1d000bb..c249c26a8 100644 ---- a/src/hotspot/cpu/aarch64/vmreg_aarch64.hpp -+++ b/src/hotspot/cpu/aarch64/vmreg_aarch64.hpp -@@ -38,13 +38,14 @@ inline Register as_Register() { - - assert( is_Register(), "must be"); - // Yuk -- return ::as_Register(value() >> 1); -+ return ::as_Register(value() / RegisterImpl::max_slots_per_register); - } - - inline FloatRegister as_FloatRegister() { - assert( is_FloatRegister() && is_even(value()), "must be" ); - // Yuk -- return ::as_FloatRegister((value() - ConcreteRegisterImpl::max_gpr) >> 1); -+ return ::as_FloatRegister((value() - ConcreteRegisterImpl::max_gpr) / -+ FloatRegisterImpl::max_slots_per_register); - } - - inline bool is_concrete() { diff --git a/src/hotspot/cpu/aarch64/vmreg_aarch64.inline.hpp b/src/hotspot/cpu/aarch64/vmreg_aarch64.inline.hpp -index 145f9797f..dde7a7a91 100644 +index c5d4383b4..dde7a7a91 100644 --- a/src/hotspot/cpu/aarch64/vmreg_aarch64.inline.hpp +++ b/src/hotspot/cpu/aarch64/vmreg_aarch64.inline.hpp @@ -1,6 +1,6 @@ @@ -6902,27 +6982,17 @@ index 145f9797f..dde7a7a91 100644 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it -@@ -28,11 +28,16 @@ - - inline VMReg RegisterImpl::as_VMReg() { - if( this==noreg ) return VMRegImpl::Bad(); -- return VMRegImpl::as_VMReg(encoding() << 1 ); -+ return VMRegImpl::as_VMReg(encoding() * RegisterImpl::max_slots_per_register); +@@ -36,4 +36,8 @@ inline VMReg FloatRegisterImpl::as_VMReg() { + ConcreteRegisterImpl::max_gpr); } - inline VMReg FloatRegisterImpl::as_VMReg() { -- return VMRegImpl::as_VMReg((encoding() << 1) + ConcreteRegisterImpl::max_gpr); -+ return VMRegImpl::as_VMReg((encoding() * FloatRegisterImpl::max_slots_per_register) + -+ ConcreteRegisterImpl::max_gpr); -+} -+ +inline VMReg PRegisterImpl::as_VMReg() { + return VMRegImpl::as_VMReg(encoding() + ConcreteRegisterImpl::max_fpr); - } - ++} ++ #endif // CPU_AARCH64_VM_VMREG_AARCH64_INLINE_HPP diff --git a/src/hotspot/cpu/arm/arm.ad b/src/hotspot/cpu/arm/arm.ad -index 18e81bdc5..87e5f331b 100644 +index 4a32af54e..03248b2e0 100644 --- a/src/hotspot/cpu/arm/arm.ad +++ b/src/hotspot/cpu/arm/arm.ad @@ -1093,7 +1093,7 @@ const bool Matcher::match_rule_supported(int opcode) { @@ -6950,7 +7020,7 @@ index 18e81bdc5..87e5f331b 100644 const uint Matcher::vector_ideal_reg(int size) { assert(MaxVectorSize >= size, ""); diff --git a/src/hotspot/cpu/ppc/ppc.ad b/src/hotspot/cpu/ppc/ppc.ad -index 07bda6d71..4cbe2cf5c 100644 +index 36cbada53..571a6aeb0 100644 --- a/src/hotspot/cpu/ppc/ppc.ad +++ b/src/hotspot/cpu/ppc/ppc.ad @@ -2242,7 +2242,7 @@ const bool Matcher::match_rule_supported(int opcode) { @@ -7019,17 +7089,17 @@ index a09c795c9..3b1b1046e 100644 // TODO // identify extra cases that we might want to provide match rules for diff --git a/src/hotspot/cpu/x86/x86.ad b/src/hotspot/cpu/x86/x86.ad -index 8fb9a3e34..dc5f1ecf9 100644 +index abdd7483d..93aee6d6c 100644 --- a/src/hotspot/cpu/x86/x86.ad +++ b/src/hotspot/cpu/x86/x86.ad @@ -1,5 +1,5 @@ // --// Copyright (c) 2011, 2018, Oracle and/or its affiliates. All rights reserved. +-// Copyright (c) 2011, 2019, Oracle and/or its affiliates. All rights reserved. +// Copyright (c) 2011, 2020, Oracle and/or its affiliates. All rights reserved. // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. // // This code is free software; you can redistribute it and/or modify it -@@ -1341,7 +1341,7 @@ const bool Matcher::match_rule_supported(int opcode) { +@@ -1354,7 +1354,7 @@ const bool Matcher::match_rule_supported(int opcode) { return ret_value; // Per default match rules are supported. } @@ -7038,7 +7108,7 @@ index 8fb9a3e34..dc5f1ecf9 100644 // identify extra cases that we might want to provide match rules for // e.g. Op_ vector nodes and other intrinsics while guarding with vlen bool ret_value = match_rule_supported(opcode); -@@ -1468,6 +1468,14 @@ const int Matcher::min_vector_size(const BasicType bt) { +@@ -1485,6 +1485,14 @@ const int Matcher::min_vector_size(const BasicType bt) { return MIN2(size,max_size); } @@ -7054,10 +7124,10 @@ index 8fb9a3e34..dc5f1ecf9 100644 const uint Matcher::vector_ideal_reg(int size) { assert(MaxVectorSize >= size, ""); diff --git a/src/hotspot/cpu/x86/x86_64.ad b/src/hotspot/cpu/x86/x86_64.ad -index c2d1aca0c..0db8e6a14 100644 +index 8904bba97..e09cdd061 100644 --- a/src/hotspot/cpu/x86/x86_64.ad +++ b/src/hotspot/cpu/x86/x86_64.ad -@@ -2887,7 +2887,7 @@ frame +@@ -2968,7 +2968,7 @@ frame RAX_H_num // Op_RegL }; // Excluded flags and vector registers. @@ -7097,10 +7167,10 @@ index ba61aa4c0..9e41b2dc6 100644 switch(last_char) { case 'I': return "TypeInt::INT"; diff --git a/src/hotspot/share/adlc/formssel.cpp b/src/hotspot/share/adlc/formssel.cpp -index 5ba1fdc57..45826d3b2 100644 +index c7b855a7e..a37866824 100644 --- a/src/hotspot/share/adlc/formssel.cpp +++ b/src/hotspot/share/adlc/formssel.cpp -@@ -3946,6 +3946,8 @@ bool MatchRule::is_base_register(FormDict &globals) const { +@@ -3963,6 +3963,8 @@ bool MatchRule::is_base_register(FormDict &globals) const { strcmp(opType,"RegL")==0 || strcmp(opType,"RegF")==0 || strcmp(opType,"RegD")==0 || @@ -7279,7 +7349,7 @@ index 914dc43f6..710af9de8 100644 } else { // Else fatproj // mask must be equal to fatproj bits, by definition diff --git a/src/hotspot/share/opto/chaitin.hpp b/src/hotspot/share/opto/chaitin.hpp -index 776e3cf63..674791c64 100644 +index e5be5b966..5408a24ef 100644 --- a/src/hotspot/share/opto/chaitin.hpp +++ b/src/hotspot/share/opto/chaitin.hpp @@ -1,5 +1,5 @@ @@ -7349,7 +7419,7 @@ index 776e3cf63..674791c64 100644 _was_spilled2:1, // True if twice prior spilling on def _is_bound:1, // live range starts life with no diff --git a/src/hotspot/share/opto/matcher.cpp b/src/hotspot/share/opto/matcher.cpp -index 05fdab21e..14e5425b8 100644 +index 4cc7580a8..4fb732161 100644 --- a/src/hotspot/share/opto/matcher.cpp +++ b/src/hotspot/share/opto/matcher.cpp @@ -84,6 +84,7 @@ Matcher::Matcher() @@ -7502,7 +7572,7 @@ index 05fdab21e..14e5425b8 100644 if (Matcher::vector_size_supported(T_BYTE,4)) { TypeVect::VECTS = TypeVect::make(T_BYTE, 4); MachNode *spillVectS = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTS)); -@@ -1573,7 +1609,6 @@ Node* Matcher::Label_Root(const Node* n, State* svec, Node* control, Node*& mem) +@@ -1575,7 +1611,6 @@ Node* Matcher::Label_Root(const Node* n, State* svec, Node* control, Node*& mem) } } @@ -7855,10 +7925,10 @@ index c64d08795..b733b87ad 100644 // Fast overlap test. Non-zero if any registers in common. int overlap( const RegMask &rm ) const { diff --git a/src/hotspot/share/opto/superword.cpp b/src/hotspot/share/opto/superword.cpp -index e7714ba3e..a6a62ea4a 100644 +index 92f70b77d..ed67928f5 100644 --- a/src/hotspot/share/opto/superword.cpp +++ b/src/hotspot/share/opto/superword.cpp -@@ -93,8 +93,11 @@ SuperWord::SuperWord(PhaseIdealLoop* phase) : +@@ -96,8 +96,11 @@ static const bool _do_vector_loop_experimental = false; // Experimental vectoriz //------------------------------transform_loop--------------------------- void SuperWord::transform_loop(IdealLoopTree* lpt, bool do_optimization) { assert(UseSuperWord, "should be"); @@ -7873,7 +7943,7 @@ index e7714ba3e..a6a62ea4a 100644 assert(lpt->_head->is_CountedLoop(), "must be"); CountedLoopNode *cl = lpt->_head->as_CountedLoop(); diff --git a/src/hotspot/share/opto/type.cpp b/src/hotspot/share/opto/type.cpp -index 8898a3f00..37ec81995 100644 +index 223b7a1c6..1b46cb452 100644 --- a/src/hotspot/share/opto/type.cpp +++ b/src/hotspot/share/opto/type.cpp @@ -79,6 +79,7 @@ const Type::TypeInfo Type::_type_info[Type::lastype] = { @@ -7884,7 +7954,7 @@ index 8898a3f00..37ec81995 100644 { Bad, T_ILLEGAL, "vectors:", false, Op_VecS, relocInfo::none }, // VectorS { Bad, T_ILLEGAL, "vectord:", false, Op_VecD, relocInfo::none }, // VectorD { Bad, T_ILLEGAL, "vectorx:", false, Op_VecX, relocInfo::none }, // VectorX -@@ -649,6 +650,10 @@ void Type::Initialize_shared(Compile* current) { +@@ -655,6 +656,10 @@ void Type::Initialize_shared(Compile* current) { // get_zero_type() should not happen for T_CONFLICT _zero_type[T_CONFLICT]= NULL; @@ -7895,7 +7965,7 @@ index 8898a3f00..37ec81995 100644 // Vector predefined types, it needs initialized _const_basic_type[]. if (Matcher::vector_size_supported(T_BYTE,4)) { TypeVect::VECTS = TypeVect::make(T_BYTE,4); -@@ -665,6 +670,8 @@ void Type::Initialize_shared(Compile* current) { +@@ -671,6 +676,8 @@ void Type::Initialize_shared(Compile* current) { if (Matcher::vector_size_supported(T_FLOAT,16)) { TypeVect::VECTZ = TypeVect::make(T_FLOAT,16); } @@ -7904,7 +7974,7 @@ index 8898a3f00..37ec81995 100644 mreg2type[Op_VecS] = TypeVect::VECTS; mreg2type[Op_VecD] = TypeVect::VECTD; mreg2type[Op_VecX] = TypeVect::VECTX; -@@ -984,6 +991,7 @@ const Type::TYPES Type::dual_type[Type::lastype] = { +@@ -990,6 +997,7 @@ const Type::TYPES Type::dual_type[Type::lastype] = { Bad, // Tuple - handled in v-call Bad, // Array - handled in v-call @@ -7912,7 +7982,7 @@ index 8898a3f00..37ec81995 100644 Bad, // VectorS - handled in v-call Bad, // VectorD - handled in v-call Bad, // VectorX - handled in v-call -@@ -1880,7 +1888,6 @@ const TypeTuple *TypeTuple::LONG_PAIR; +@@ -1890,7 +1898,6 @@ const TypeTuple *TypeTuple::LONG_PAIR; const TypeTuple *TypeTuple::INT_CC_PAIR; const TypeTuple *TypeTuple::LONG_CC_PAIR; @@ -7920,7 +7990,7 @@ index 8898a3f00..37ec81995 100644 //------------------------------make------------------------------------------- // Make a TypeTuple from the range of a method signature const TypeTuple *TypeTuple::make_range(ciSignature* sig) { -@@ -2252,6 +2259,7 @@ bool TypeAry::ary_must_be_exact() const { +@@ -2262,6 +2269,7 @@ bool TypeAry::ary_must_be_exact() const { //==============================TypeVect======================================= // Convenience common pre-built types. @@ -7928,7 +7998,7 @@ index 8898a3f00..37ec81995 100644 const TypeVect *TypeVect::VECTS = NULL; // 32-bit vectors const TypeVect *TypeVect::VECTD = NULL; // 64-bit vectors const TypeVect *TypeVect::VECTX = NULL; // 128-bit vectors -@@ -2262,10 +2270,11 @@ const TypeVect *TypeVect::VECTZ = NULL; // 512-bit vectors +@@ -2272,10 +2280,11 @@ const TypeVect *TypeVect::VECTZ = NULL; // 512-bit vectors const TypeVect* TypeVect::make(const Type *elem, uint length) { BasicType elem_bt = elem->array_element_basic_type(); assert(is_java_primitive(elem_bt), "only primitive types in vector"); @@ -7941,7 +8011,7 @@ index 8898a3f00..37ec81995 100644 case Op_VecS: return (TypeVect*)(new TypeVectS(elem, length))->hashcons(); case Op_RegL: -@@ -2297,7 +2306,7 @@ const Type *TypeVect::xmeet( const Type *t ) const { +@@ -2307,7 +2316,7 @@ const Type *TypeVect::xmeet( const Type *t ) const { default: // All else is a mistake typerr(t); @@ -7950,7 +8020,7 @@ index 8898a3f00..37ec81995 100644 case VectorS: case VectorD: case VectorX: -@@ -2352,6 +2361,8 @@ bool TypeVect::empty(void) const { +@@ -2362,6 +2371,8 @@ bool TypeVect::empty(void) const { #ifndef PRODUCT void TypeVect::dump2(Dict &d, uint depth, outputStream *st) const { switch (base()) { @@ -7960,7 +8030,7 @@ index 8898a3f00..37ec81995 100644 st->print("vectors["); break; case VectorD: diff --git a/src/hotspot/share/opto/type.hpp b/src/hotspot/share/opto/type.hpp -index 6c8194670..ca92fe3ab 100644 +index a7eec281e..6787b947d 100644 --- a/src/hotspot/share/opto/type.hpp +++ b/src/hotspot/share/opto/type.hpp @@ -1,5 +1,5 @@ @@ -7986,7 +8056,7 @@ index 6c8194670..ca92fe3ab 100644 VectorS, // 32bit Vector types VectorD, // 64bit Vector types VectorX, // 128bit Vector types -@@ -754,6 +756,7 @@ public: +@@ -758,6 +760,7 @@ public: virtual const Type *xmeet( const Type *t) const; virtual const Type *xdual() const; // Compute dual right now. @@ -7994,7 +8064,7 @@ index 6c8194670..ca92fe3ab 100644 static const TypeVect *VECTS; static const TypeVect *VECTD; static const TypeVect *VECTX; -@@ -765,6 +768,11 @@ public: +@@ -769,6 +772,11 @@ public: #endif }; @@ -8006,7 +8076,7 @@ index 6c8194670..ca92fe3ab 100644 class TypeVectS : public TypeVect { friend class TypeVect; TypeVectS(const Type* elem, uint length) : TypeVect(VectorS, elem, length) {} -@@ -1611,12 +1619,12 @@ inline const TypeAry *Type::is_ary() const { +@@ -1619,12 +1627,12 @@ inline const TypeAry *Type::is_ary() const { } inline const TypeVect *Type::is_vect() const { @@ -8022,7 +8092,7 @@ index 6c8194670..ca92fe3ab 100644 inline const TypePtr *Type::is_ptr() const { diff --git a/src/hotspot/share/opto/vectornode.cpp b/src/hotspot/share/opto/vectornode.cpp -index fae147fa8..3a0a42513 100644 +index 1f2cf2c64..6867177c1 100644 --- a/src/hotspot/share/opto/vectornode.cpp +++ b/src/hotspot/share/opto/vectornode.cpp @@ -1,5 +1,5 @@ @@ -8032,7 +8102,7 @@ index fae147fa8..3a0a42513 100644 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it -@@ -221,7 +221,7 @@ bool VectorNode::implemented(int opc, uint vlen, BasicType bt) { +@@ -236,7 +236,7 @@ bool VectorNode::implemented(int opc, uint vlen, BasicType bt) { (vlen > 1) && is_power_of_2(vlen) && Matcher::vector_size_supported(bt, vlen)) { int vopc = VectorNode::opcode(opc, bt); @@ -8041,7 +8111,7 @@ index fae147fa8..3a0a42513 100644 } return false; } -@@ -608,7 +608,7 @@ bool ReductionNode::implemented(int opc, uint vlen, BasicType bt) { +@@ -653,7 +653,7 @@ bool ReductionNode::implemented(int opc, uint vlen, BasicType bt) { (vlen > 1) && is_power_of_2(vlen) && Matcher::vector_size_supported(bt, vlen)) { int vopc = ReductionNode::opcode(opc, bt); @@ -8259,5 +8329,5 @@ index 000000000..0cb3ab0b5 + +#endif -- -2.19.1 +2.19.0 diff --git a/delete_expired_certificates.patch b/delete_expired_certificates.patch old mode 100755 new mode 100644 index 4c2a8e4281e99418ba968308af4b20792cab422d..0ea4f54fac9b7fd88a47208b61b93f8fcbc732fe --- a/delete_expired_certificates.patch +++ b/delete_expired_certificates.patch @@ -79,54 +79,22 @@ index 0c195ff51..000000000 -xFIY6iHOsfHmhIHluqmGKPJDWl0Snawe2ajlCmqnf6CHKc/yiU3U7MXi5nrQNiOK -SnQ2+Q== ------END CERTIFICATE----- -diff --git a/make/data/cacerts/soneraclass2ca b/make/data/cacerts/soneraclass2ca -deleted file mode 100644 -index 43faa5e21..000000000 ---- a/make/data/cacerts/soneraclass2ca -+++ /dev/null -@@ -1,26 +0,0 @@ --Owner: CN=Sonera Class2 CA, O=Sonera, C=FI --Issuer: CN=Sonera Class2 CA, O=Sonera, C=FI --Serial number: 1d --Valid from: Fri Apr 06 07:29:40 GMT 2001 until: Tue Apr 06 07:29:40 GMT 2021 --Signature algorithm name: SHA1withRSA --Subject Public Key Algorithm: 2048-bit RSA key --Version: 3 -------BEGIN CERTIFICATE----- --MIIDIDCCAgigAwIBAgIBHTANBgkqhkiG9w0BAQUFADA5MQswCQYDVQQGEwJGSTEP --MA0GA1UEChMGU29uZXJhMRkwFwYDVQQDExBTb25lcmEgQ2xhc3MyIENBMB4XDTAx --MDQwNjA3Mjk0MFoXDTIxMDQwNjA3Mjk0MFowOTELMAkGA1UEBhMCRkkxDzANBgNV --BAoTBlNvbmVyYTEZMBcGA1UEAxMQU29uZXJhIENsYXNzMiBDQTCCASIwDQYJKoZI --hvcNAQEBBQADggEPADCCAQoCggEBAJAXSjWdyvANlsdE+hY3/Ei9vX+ALTU74W+o --Z6m/AxxNjG8yR9VBaKQTBME1DJqEQ/xcHf+Js+gXGM2RX/uJ4+q/Tl18GybTdXnt --5oTjV+WtKcT0OijnpXuENmmz/V52vaMtmdOQTiMofRhj8VQ7Jp12W5dCsv+u8E7s --3TmVToMGf+dJQMjFAbJUWmYdPfz56TwKnoG4cPABi+QjVHzIrviQHgCWctRUz2Ej --vOr7nQKV0ba5cTppCD8PtOFCx4j1P5iop7oc4HFx71hXgVB6XGt0Rg6DA5jDjqhu --8nYybieDwnPz3BjotJPqdURrBGAgcVeHnfO+oJAjPYok4doh28MCAwEAAaMzMDEw --DwYDVR0TAQH/BAUwAwEB/zARBgNVHQ4ECgQISqCqWITTXjwwCwYDVR0PBAQDAgEG --MA0GCSqGSIb3DQEBBQUAA4IBAQBazof5FnIVV0sd2ZvnoiYw7JNn39Yt0jSv9zil --zqsWuasvfDXLrNAPtEwr/IDva4yRXzZ299uzGxnq9LIR/WFxRL8oszodv7ND6J+/ --3DEIcbCdjdY0RzKQxmUk96BKfARzjzlvF4xytb1LyHr4e4PDKE6cCepnP7JnBBvD --FNr450kkkdAdavphOe9r5yF1BgfYErQhIHBCcYHaPJo2vqZbDWpsmh+Re/n570K6 --Tk6ezAyNlNzZRZxe7EJQY670XcSxEtzKO6gunRRaBXW37Ndj4ro1tgQIkejanZz2 --ZrUYrAqmVCY0M9IbwdR/GjqOC6oybtv8TyWf2TLHllpwrN9M -------END CERTIFICATE----- diff --git a/test/jdk/sun/security/lib/cacerts/VerifyCACerts.java b/test/jdk/sun/security/lib/cacerts/VerifyCACerts.java -index ec9cca01f..793376ea1 100644 +index b0e28f192..986f4a332 100644 --- a/test/jdk/sun/security/lib/cacerts/VerifyCACerts.java +++ b/test/jdk/sun/security/lib/cacerts/VerifyCACerts.java @@ -53,12 +53,12 @@ public class VerifyCACerts { + File.separator + "security" + File.separator + "cacerts"; // The numbers of certs now. -- private static final int COUNT = 89; +- private static final int COUNT = 88; + private static final int COUNT = 86; // SHA-256 of cacerts, can be generated with // shasum -a 256 cacerts | sed -e 's/../&:/g' | tr '[:lower:]' '[:upper:]' | cut -c1-95 private static final String CHECKSUM -- = "9F:6B:41:1D:05:AF:E3:C5:4F:E8:39:89:50:79:60:B1:F6:A4:02:40:0C:28:8D:73:78:08:E5:61:7C:17:EA:59"; -+ = "A5:00:71:02:B4:8B:AC:BE:64:34:0A:F2:DF:9D:F7:75:9D:05:84:7E:F6:EA:48:F0:64:36:29:8C:E7:A2:2D:63"; +- = "9B:C3:0B:24:D4:26:E4:A9:4F:2C:96:25:06:9B:08:E5:13:5B:0B:33:74:5F:78:DB:BD:91:CD:31:D4:37:07:28"; ++ = "E3:B0:C4:42:98:FC:1C:14:9A:FB:F4:C8:99:6F:B9:24:27:AE:41:E4:64:9B:93:4C:A4:95:99:1B:78:52:B8:55"; // map of cert alias to SHA-256 fingerprint @SuppressWarnings("serial") @@ -141,12 +109,6 @@ index ec9cca01f..793376ea1 100644 put("quovadisrootca1g3 [jdk]", "8A:86:6F:D1:B2:76:B5:7E:57:8E:92:1C:65:82:8A:2B:ED:58:E9:F2:F2:88:05:41:34:B7:F1:F4:BF:C9:CC:74"); put("quovadisrootca2 [jdk]", -@@ -170,8 +166,6 @@ public class VerifyCACerts { - "3B:22:2E:56:67:11:E9:92:30:0D:C0:B1:5A:B9:47:3D:AF:DE:F8:C8:4D:0C:EF:7D:33:17:B4:C1:82:1D:14:36"); - put("swisssignsilverg2ca [jdk]", - "BE:6C:4D:A2:BB:B9:BA:59:B6:F3:93:97:68:37:42:46:C3:C0:05:99:3F:A9:8F:02:0D:1D:ED:BE:D4:8A:81:D5"); -- put("soneraclass2ca [jdk]", -- "79:08:B4:03:14:C1:38:10:0B:51:8D:07:35:80:7F:FB:FC:F8:51:8A:00:95:33:71:05:BA:38:6B:15:3D:D9:27"); - put("securetrustca [jdk]", - "F1:C1:B5:0A:E5:A2:0D:D8:03:0E:C9:F6:BC:24:82:3D:D3:67:B5:25:57:59:B4:E7:1B:61:FC:E9:F7:37:5D:73"); - put("xrampglobalca [jdk]", +-- +2.19.0 + diff --git a/jdk-updates-jdk11u-jdk-11.0.11-ga.tar.xz b/jdk-updates-jdk11u-jdk-11.0.12-ga.tar.xz similarity index 83% rename from jdk-updates-jdk11u-jdk-11.0.11-ga.tar.xz rename to jdk-updates-jdk11u-jdk-11.0.12-ga.tar.xz index ba2e83dd2a85b18ac8c27d430ee9486112f4950b..c9ba2753756a01fa82b22b7c9a9202502d0b3a07 100644 Binary files a/jdk-updates-jdk11u-jdk-11.0.11-ga.tar.xz and b/jdk-updates-jdk11u-jdk-11.0.12-ga.tar.xz differ diff --git a/openjdk-11.spec b/openjdk-11.spec index d69020ecc6c9a3e50bce0df0d7c6a0ee8a2aeaa1..7fc6b4c38645b70ddf4c10999345d96553f84788 100644 --- a/openjdk-11.spec +++ b/openjdk-11.spec @@ -114,7 +114,7 @@ # New Version-String scheme-style defines %global majorver 11 -%global securityver 11 +%global securityver 12 # buildjdkver is usually same as %%{majorver}, # but in time of bootstrap of next jdk, it is majorver-1, # and this it is better to change it here, on single place @@ -135,7 +135,7 @@ %global project jdk-updates %global repo jdk11u -%global revision jdk-11.0.11-ga +%global revision jdk-11.0.12-ga %global full_revision %{project}-%{repo}-%{revision} # priority must be 7 digits in total # setting to 1, so debug ones can have 0 @@ -740,7 +740,7 @@ Provides: java-src%{?1} = %{epoch}:%{version}-%{release} Name: java-%{javaver}-%{origin} Version: %{newjavaver}.%{buildver} -Release: 7 +Release: 0 # java-1.5.0-ibm from jpackage.org set Epoch to 1 for unknown reasons # and this change was brought into RHEL-4. java-1.5.0-ibm packages # also included the epoch in their virtual provides. This created a @@ -826,7 +826,6 @@ Patch36: ZGC-in-c1-load-barrier-d0-and-d1-registers-miss-restoring.patch Patch37: fix-compile-error-without-disable-precompiled-headers.patch Patch38: fast-serializer-jdk11.patch Patch39: fix-jck-failure-on-FastSerializer.patch -Patch40: 8223667-ASAN-build-broken.patch Patch42: 8229496-SIGFPE-division-by-zero-in-C2-OSR-compiled-method.patch Patch45: leaf-optimize-in-ParallelScanvageGC.patch Patch46: ZGC-correct-free-heap-size-excluding-waste-in-rule_allocation_rate.patch @@ -834,7 +833,6 @@ Patch47: 8204947-Port-ShenandoahTaskTerminator-to-mainline-and-make-it-default.p Patch48: 8205921-Optimizing-best_of_2-work-stealing-queue-selection.patch # 11.0.9 -Patch54: 8207160-ClassReader-adjustMethodParams-can-potentially-return-null-if-the-args-list-is-empty.patch Patch55: 8215047-Task-terminators-do-not-complete-termination-in-consistent-state.patch Patch57: add-zgc-parameter-adaptation-feature.patch Patch58: add-integerCache-feature.patch @@ -843,7 +841,6 @@ Patch59: add-SVE-backend-feature.patch #11.0.10 Patch61: downgrade-the-symver-of-log2f-posix-spawn.patch Patch62: 8254078-DataOutputStream-is-very-slow-post-disabling.patch -Patch63: 8217918-C2-XX-AggressiveUnboxing-is-broken.patch Patch64: Fix-the-memcpy-symbol-issue-during-JDK11-x64-build.patch Patch65: add-LazyBox-feature.patch Patch66: add-G1-Full-GC-optimization.patch @@ -852,7 +849,6 @@ Patch68: src-openeuler-openjdk-11-resolve-code-inconsistencies.patch Patch69: G1-iterate-region-by-bitmap-rather-than-obj-size-in.patch #11.0.11 -Patch70: 8264640.patch Patch71: numa_mem_leak.patch Patch72: select_nearest_numa_node.patch Patch73: support_jmap_parallel_inspection_for_cms_gc.patch @@ -1110,27 +1106,23 @@ pushd %{top_level_dir_name} %patch37 -p1 %patch38 -p1 %patch39 -p1 -%patch40 -p1 %patch42 -p1 %patch45 -p1 %patch46 -p1 %patch47 -p1 %patch48 -p1 -%patch54 -p1 %patch55 -p1 %patch57 -p1 %patch58 -p1 %patch59 -p1 %patch61 -p1 %patch62 -p1 -%patch63 -p1 %patch64 -p1 %patch65 -p1 %patch66 -p1 %patch67 -p1 %patch68 -p1 %patch69 -p1 -%patch70 -p1 %patch71 -p1 %patch72 -p1 %patch73 -p1 @@ -1637,6 +1629,14 @@ require "copy_jdk_configs.lua" %changelog +* Tue Aug 3 2021 linhaibing21 - 1:11.0.12.7-0 +- Update to 11.0.12+7 (GA) +- delete 8207160-ClassReader-adjustMethodParams-can-potentially-return-null-if-the-args-list-is-empty.patch +- delete 8217918-C2-XX-AggressiveUnboxing-is-broken.patch +- delete 8223667-ASAN-build-broken.patch +- delete 8264640.patch +- other adaptations to 11.0.12 + * Thu Jul 8 2021 noah - 1:11.0.11.9-7 - delete debug log to reduce build time diff --git a/src-openeuler-openjdk-11-resolve-code-inconsistencies.patch b/src-openeuler-openjdk-11-resolve-code-inconsistencies.patch old mode 100755 new mode 100644 index ba133b9b7b119a436d2034fda306155ed3f91049..51df00cc4159edb9f0b5b8c55fb02fafba548d27 --- a/src-openeuler-openjdk-11-resolve-code-inconsistencies.patch +++ b/src-openeuler-openjdk-11-resolve-code-inconsistencies.patch @@ -1,9 +1,3 @@ -commit c2748cd0d7b5a92b275aff0cd1d1fa0b113ba64f -Author: aijiaming -Date: Mon Apr 12 10:53:53 2021 +0800 - - fix patch - diff --git a/make/launcher/Launcher-java.base.gmk b/make/launcher/Launcher-java.base.gmk index f6d4aa28f..d511c0be5 100644 --- a/make/launcher/Launcher-java.base.gmk @@ -53,7 +47,7 @@ index a93fd2a90..2e0bc7a5b 100644 CFLAGS_release := -DPRODUCT, \ CFLAGS_linux := -fPIC, \ diff --git a/make/lib/Awt2dLibraries.gmk b/make/lib/Awt2dLibraries.gmk -index 7b0441507..b334b76e4 100644 +index e8c27e902..9ebb93dcb 100644 --- a/make/lib/Awt2dLibraries.gmk +++ b/make/lib/Awt2dLibraries.gmk @@ -35,6 +35,11 @@ LIBAWT_DEFAULT_HEADER_DIRS := \ @@ -84,7 +78,7 @@ index 7b0441507..b334b76e4 100644 EXCLUDES := $(LIBAWT_EXCLUDES), \ EXCLUDE_FILES := $(LIBAWT_EXFILES), \ OPTIMIZATION := LOW, \ -@@ -431,6 +438,7 @@ endif +@@ -430,6 +437,7 @@ endif $(eval $(call SetupJdkLibrary, BUILD_LIBJAVAJPEG, \ NAME := javajpeg, \ INCLUDE_FILES := $(BUILD_LIBJAVAJPEG_INCLUDE_FILES), \ @@ -92,7 +86,7 @@ index 7b0441507..b334b76e4 100644 OPTIMIZATION := HIGHEST, \ CFLAGS := $(CFLAGS_JDKLIB), \ HEADERS_FROM_SRC := $(LIBJPEG_HEADERS_FROM_SRC), \ -@@ -921,6 +929,7 @@ ifeq ($(ENABLE_HEADLESS_ONLY), false) +@@ -919,6 +927,7 @@ ifeq ($(ENABLE_HEADLESS_ONLY), false) NAME := splashscreen, \ EXTRA_SRC := $(LIBSPLASHSCREEN_EXTRA_SRC), \ EXCLUDE_SRC_PATTERNS := $(LIBSPLASHSCREEN_EXCLUDE_SRC_PATTERNS), \ @@ -162,7 +156,7 @@ index 226e20892..f180a28c3 100644 CFLAGS := $(CFLAGS_JDKLIB) $(LIBJLI_CFLAGS), \ DISABLED_WARNINGS_gcc := unused-function implicit-fallthrough, \ diff --git a/make/lib/Lib-java.base.gmk b/make/lib/Lib-java.base.gmk -index 880249b8a..48876b84c 100644 +index a529768f3..0c888b65c 100644 --- a/make/lib/Lib-java.base.gmk +++ b/make/lib/Lib-java.base.gmk @@ -36,12 +36,18 @@ $(call FillFindCache, $(wildcard $(TOPDIR)/src/java.base/*/native)) @@ -185,7 +179,7 @@ index 880249b8a..48876b84c 100644 DISABLED_WARNINGS_gcc := format-nonliteral, \ DISABLED_WARNINGS_clang := parentheses-equality constant-logical-operand, \ diff --git a/make/lib/Lib-java.desktop.gmk b/make/lib/Lib-java.desktop.gmk -index 2bb02cdd7..917ab02fc 100644 +index 274df2b8e..932e0b3e8 100644 --- a/make/lib/Lib-java.desktop.gmk +++ b/make/lib/Lib-java.desktop.gmk @@ -36,6 +36,11 @@ $(call FillFindCache, $(wildcard $(TOPDIR)/src/java.desktop/*/native)) @@ -275,7 +269,7 @@ index dfecc1d3c..4137a371d 100644 -DMP_API_COMPATIBLE -DNSS_ECC_MORE_THAN_SUITE_B, \ CXXFLAGS := $(BUILD_LIBSUNEC_CXXFLAGS_JDKLIB), \ diff --git a/make/lib/Lib-jdk.hotspot.agent.gmk b/make/lib/Lib-jdk.hotspot.agent.gmk -index 1cbae7065..1ac259517 100644 +index 2d0c36a47..ad3075f00 100644 --- a/make/lib/Lib-jdk.hotspot.agent.gmk +++ b/make/lib/Lib-jdk.hotspot.agent.gmk @@ -27,6 +27,11 @@ include LibCommon.gmk @@ -404,7 +398,7 @@ index d79bd1bac..eafe26906 100644 RESTARTABLE(::stat64(fn, &st), ret); if (ret == -1) { diff --git a/src/hotspot/share/c1/c1_GraphBuilder.cpp b/src/hotspot/share/c1/c1_GraphBuilder.cpp -index bc2561fb0..6780fe3ed 100644 +index 211c2acda..86cc0108b 100644 --- a/src/hotspot/share/c1/c1_GraphBuilder.cpp +++ b/src/hotspot/share/c1/c1_GraphBuilder.cpp @@ -1,5 +1,5 @@ @@ -414,7 +408,7 @@ index bc2561fb0..6780fe3ed 100644 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it -@@ -3784,6 +3784,23 @@ bool GraphBuilder::try_inline_full(ciMethod* callee, bool holder_known, bool ign +@@ -3783,6 +3783,23 @@ bool GraphBuilder::try_inline_full(ciMethod* callee, bool holder_known, bool ign INLINE_BAILOUT("mdo allocation failed"); } @@ -438,7 +432,7 @@ index bc2561fb0..6780fe3ed 100644 // now perform tests that are based on flag settings bool inlinee_by_directive = compilation()->directive()->should_inline(callee); if (callee->force_inline() || inlinee_by_directive) { -@@ -3826,21 +3843,11 @@ bool GraphBuilder::try_inline_full(ciMethod* callee, bool holder_known, bool ign +@@ -3825,21 +3842,11 @@ bool GraphBuilder::try_inline_full(ciMethod* callee, bool holder_known, bool ign BlockBegin* orig_block = block(); @@ -524,10 +518,10 @@ index c60609617..f0b8638c1 100644 case NotInCSet: return "NotInCSet"; case Young: return "Young"; diff --git a/src/hotspot/share/gc/parallel/parallelScavengeHeap.cpp b/src/hotspot/share/gc/parallel/parallelScavengeHeap.cpp -index 66e1b32a6..7a403c3b2 100644 +index c70d8e89a..c8a3abaf3 100644 --- a/src/hotspot/share/gc/parallel/parallelScavengeHeap.cpp +++ b/src/hotspot/share/gc/parallel/parallelScavengeHeap.cpp -@@ -541,7 +541,7 @@ public: +@@ -542,7 +542,7 @@ public: // Claim the block and get the block index. size_t claim_and_get_block() { size_t block_index; @@ -563,10 +557,10 @@ index 246e82be6..110757684 100644 // Reset the terminator, so that it may be reused again. // The caller is responsible for ensuring that this is done diff --git a/src/hotspot/share/gc/shenandoah/shenandoahConcurrentMark.cpp b/src/hotspot/share/gc/shenandoah/shenandoahConcurrentMark.cpp -index 5266c911e..849be8e99 100644 +index 0f3c429ed..82fde2c94 100644 --- a/src/hotspot/share/gc/shenandoah/shenandoahConcurrentMark.cpp +++ b/src/hotspot/share/gc/shenandoah/shenandoahConcurrentMark.cpp -@@ -875,7 +875,6 @@ void ShenandoahConcurrentMark::mark_loop_prework(uint w, ShenandoahTaskTerminato +@@ -889,7 +889,6 @@ void ShenandoahConcurrentMark::mark_loop_prework(uint w, ShenandoahTaskTerminato template void ShenandoahConcurrentMark::mark_loop_work(T* cl, ShenandoahLiveData* live_data, uint worker_id, ShenandoahTaskTerminator *terminator) { @@ -574,7 +568,7 @@ index 5266c911e..849be8e99 100644 uintx stride = ShenandoahMarkLoopStride; ShenandoahHeap* heap = ShenandoahHeap::heap(); -@@ -929,7 +928,7 @@ void ShenandoahConcurrentMark::mark_loop_work(T* cl, ShenandoahLiveData* live_da +@@ -943,7 +942,7 @@ void ShenandoahConcurrentMark::mark_loop_work(T* cl, ShenandoahLiveData* live_da uint work = 0; for (uint i = 0; i < stride; i++) { if (q->pop(t) || @@ -584,7 +578,7 @@ index 5266c911e..849be8e99 100644 work++; } else { diff --git a/src/hotspot/share/memory/heapInspection.cpp b/src/hotspot/share/memory/heapInspection.cpp -index dbc0eb274..e612a1ff8 100644 +index dd76165a7..d492751a6 100644 --- a/src/hotspot/share/memory/heapInspection.cpp +++ b/src/hotspot/share/memory/heapInspection.cpp @@ -746,7 +746,7 @@ class RecordInstanceClosure : public ObjectClosure { @@ -597,7 +591,7 @@ index dbc0eb274..e612a1ff8 100644 uintx missed_count = 0; bool merge_success = true; diff --git a/src/hotspot/share/opto/graphKit.cpp b/src/hotspot/share/opto/graphKit.cpp -index 356bd5ccc..3e742c0ef 100644 +index 22222efbc..5849e8f86 100644 --- a/src/hotspot/share/opto/graphKit.cpp +++ b/src/hotspot/share/opto/graphKit.cpp @@ -44,8 +44,8 @@ @@ -611,10 +605,10 @@ index 356bd5ccc..3e742c0ef 100644 #include "gc/shenandoah/c2/shenandoahBarrierSetC2.hpp" #endif diff --git a/src/hotspot/share/opto/loopnode.cpp b/src/hotspot/share/opto/loopnode.cpp -index c65f2f6be..621110183 100644 +index b32cd9580..1f9ebd3bd 100644 --- a/src/hotspot/share/opto/loopnode.cpp +++ b/src/hotspot/share/opto/loopnode.cpp -@@ -2730,7 +2730,7 @@ bool PhaseIdealLoop::process_expensive_nodes() { +@@ -2794,7 +2794,7 @@ bool PhaseIdealLoop::only_has_infinite_loops() { //----------------------------build_and_optimize------------------------------- // Create a PhaseLoop. Build the ideal Loop tree. Map each Ideal Node to // its corresponding LoopNode. If 'optimize' is true, do some loop cleanups. @@ -623,7 +617,7 @@ index c65f2f6be..621110183 100644 bool do_split_ifs = (mode == LoopOptsDefault || mode == LoopOptsLastRound); bool skip_loop_opts = (mode == LoopOptsNone); #if INCLUDE_SHENANDOAHGC -@@ -2801,8 +2801,7 @@ void PhaseIdealLoop::build_and_optimize(LoopOptsMode mode, bool z_barrier_insert +@@ -2872,8 +2872,7 @@ void PhaseIdealLoop::build_and_optimize(LoopOptsMode mode, bool z_barrier_insert } // Nothing to do, so get out @@ -633,7 +627,7 @@ index c65f2f6be..621110183 100644 bool do_expensive_nodes = C->should_optimize_expensive_nodes(_igvn); if (stop_early && !do_expensive_nodes) { _igvn.optimize(); // Cleanup NeverBranches -@@ -2958,16 +2957,6 @@ void PhaseIdealLoop::build_and_optimize(LoopOptsMode mode, bool z_barrier_insert +@@ -3029,16 +3028,6 @@ void PhaseIdealLoop::build_and_optimize(LoopOptsMode mode, bool z_barrier_insert } #endif @@ -651,10 +645,10 @@ index c65f2f6be..621110183 100644 // Reassociate invariants and prep for split_thru_phi for (LoopTreeIterator iter(_ltree_root); !iter.done(); iter.next()) { diff --git a/src/hotspot/share/opto/loopnode.hpp b/src/hotspot/share/opto/loopnode.hpp -index 8bc62a89e..56b8492d3 100644 +index 74aab91f9..6cf2d2a6d 100644 --- a/src/hotspot/share/opto/loopnode.hpp +++ b/src/hotspot/share/opto/loopnode.hpp -@@ -936,7 +936,7 @@ public: +@@ -943,7 +943,7 @@ public: } // build the loop tree and perform any requested optimizations @@ -663,7 +657,7 @@ index 8bc62a89e..56b8492d3 100644 // Dominators for the sea of nodes void Dominators(); -@@ -946,13 +946,13 @@ public: +@@ -953,13 +953,13 @@ public: Node *dom_lca_internal( Node *n1, Node *n2 ) const; // Compute the Ideal Node to Loop mapping @@ -680,10 +674,10 @@ index 8bc62a89e..56b8492d3 100644 // Verify that verify_me made the same decisions as a fresh run. diff --git a/src/hotspot/share/prims/unsafe.cpp b/src/hotspot/share/prims/unsafe.cpp -index f3c845772..18ea89b85 100644 +index 784dc782f..9158f6d36 100644 --- a/src/hotspot/share/prims/unsafe.cpp +++ b/src/hotspot/share/prims/unsafe.cpp -@@ -1111,9 +1111,11 @@ static JNINativeMethod jdk_internal_misc_Unsafe_methods[] = { +@@ -1100,9 +1100,11 @@ static JNINativeMethod jdk_internal_misc_Unsafe_methods[] = { {CC "fullFence", CC "()V", FN_PTR(Unsafe_FullFence)}, {CC "isBigEndian0", CC "()Z", FN_PTR(Unsafe_isBigEndian0)}, @@ -806,7 +800,7 @@ index 39a9918d4..1115c48d8 100644 } } diff --git a/src/java.base/share/classes/sun/security/ssl/SSLContextImpl.java b/src/java.base/share/classes/sun/security/ssl/SSLContextImpl.java -index 6068de9e7..a104a25df 100644 +index de7da5c33..e8852f6bd 100644 --- a/src/java.base/share/classes/sun/security/ssl/SSLContextImpl.java +++ b/src/java.base/share/classes/sun/security/ssl/SSLContextImpl.java @@ -207,6 +207,10 @@ public abstract class SSLContextImpl extends SSLContextSpi { @@ -995,15 +989,15 @@ index 000000000..66d5581f5 +} + diff --git a/test/jdk/sun/security/lib/cacerts/VerifyCACerts.java b/test/jdk/sun/security/lib/cacerts/VerifyCACerts.java -index 540f353e6..727b9b948 100644 +index 66ba75a10..b0e28f192 100644 --- a/test/jdk/sun/security/lib/cacerts/VerifyCACerts.java +++ b/test/jdk/sun/security/lib/cacerts/VerifyCACerts.java @@ -53,7 +53,7 @@ public class VerifyCACerts { + File.separator + "security" + File.separator + "cacerts"; // The numbers of certs now. -- private static final int COUNT = 97; -+ private static final int COUNT = 89; +- private static final int COUNT = 91; ++ private static final int COUNT = 88; // SHA-256 of cacerts, can be generated with // shasum -a 256 cacerts | sed -e 's/../&:/g' | tr '[:lower:]' '[:upper:]' | cut -c1-95 @@ -1020,23 +1014,6 @@ index 540f353e6..727b9b948 100644 put("baltimorecybertrustca [jdk]", "16:AF:57:A9:F6:76:B0:AB:12:60:95:AA:5E:BA:DE:F2:2A:B3:11:19:D6:44:AC:95:CD:4B:93:DB:F3:F2:6A:EB"); put("digicertglobalrootca [jdk]", -@@ -132,16 +126,6 @@ public class VerifyCACerts { - "A4:31:0D:50:AF:18:A6:44:71:90:37:2A:86:AF:AF:8B:95:1F:FB:43:1D:83:7F:1E:56:88:B4:59:71:ED:15:57"); - put("thawteprimaryrootcag3 [jdk]", - "4B:03:F4:58:07:AD:70:F2:1B:FC:2C:AE:71:C9:FD:E4:60:4C:06:4C:F5:FF:B6:86:BA:E5:DB:AA:D7:FD:D3:4C"); -- put("thawtepremiumserverca [jdk]", -- "3F:9F:27:D5:83:20:4B:9E:09:C8:A3:D2:06:6C:4B:57:D3:A2:47:9C:36:93:65:08:80:50:56:98:10:5D:BC:E9"); -- put("verisigntsaca [jdk]", -- "CB:6B:05:D9:E8:E5:7C:D8:82:B1:0B:4D:B7:0D:E4:BB:1D:E4:2B:A4:8A:7B:D0:31:8B:63:5B:F6:E7:78:1A:9D"); -- put("verisignclass2g2ca [jdk]", -- "3A:43:E2:20:FE:7F:3E:A9:65:3D:1E:21:74:2E:AC:2B:75:C2:0F:D8:98:03:05:BC:50:2C:AF:8C:2D:9B:41:A1"); -- put("verisignclass3ca [jdk]", -- "A4:B6:B3:99:6F:C2:F3:06:B3:FD:86:81:BD:63:41:3D:8C:50:09:CC:4F:A3:29:C2:CC:F0:E2:FA:1B:14:03:05"); -- put("verisignclass3g2ca [jdk]", -- "83:CE:3C:12:29:68:8A:59:3D:48:5F:81:97:3C:0F:91:95:43:1E:DA:37:CC:5E:36:43:0E:79:C7:A8:88:63:8B"); - put("verisignuniversalrootca [jdk]", - "23:99:56:11:27:A5:71:25:DE:8C:EF:EA:61:0D:DF:2F:A0:78:B5:C8:06:7F:4E:82:82:90:BF:B8:60:E8:4B:3C"); - put("verisignclass3g3ca [jdk]", diff --git a/test/jdk/sun/security/ssl/SSLContextImpl/CustomizedDTLSDefaultProtocols.java b/test/jdk/sun/security/ssl/SSLContextImpl/CustomizedDTLSDefaultProtocols.java index 0dc0ffac2..e4e9434f9 100644 --- a/test/jdk/sun/security/ssl/SSLContextImpl/CustomizedDTLSDefaultProtocols.java @@ -1303,3 +1280,6 @@ index ccfff01b6..029771541 100644 } if (failed) { +-- +2.19.0 +