diff --git a/8214535-support-Jmap-parallel.patch b/8214535-support-Jmap-parallel.patch deleted file mode 100755 index b613bd91d09535bd36fea450f70c957414e23032..0000000000000000000000000000000000000000 --- a/8214535-support-Jmap-parallel.patch +++ /dev/null @@ -1,858 +0,0 @@ -From 65e9f0b4c719146b0958cb3c01fd31e11e49ec37 Mon Sep 17 00:00:00 2001 -Date: Tue, 16 Mar 2021 07:09:57 +0000 -Subject: [PATCH 4/4] backport JDK-8214535 to support Jmap parallel - ---- - src/hotspot/share/gc/g1/g1CollectedHeap.cpp | 25 ++++ - src/hotspot/share/gc/g1/g1CollectedHeap.hpp | 4 + - .../gc/parallel/parallelScavengeHeap.cpp | 64 +++++++++++ - .../gc/parallel/parallelScavengeHeap.hpp | 22 +++- - src/hotspot/share/gc/parallel/psOldGen.cpp | 32 ++++++ - src/hotspot/share/gc/parallel/psOldGen.hpp | 11 ++ - src/hotspot/share/gc/shared/collectedHeap.hpp | 11 ++ - .../share/gc/shared/vmGCOperations.cpp | 2 +- - .../share/gc/shared/vmGCOperations.hpp | 5 +- - src/hotspot/share/gc/shared/workgroup.hpp | 21 ++++ - src/hotspot/share/memory/heapInspection.cpp | 108 ++++++++++++++++-- - src/hotspot/share/memory/heapInspection.hpp | 44 ++++++- - src/hotspot/share/runtime/arguments.hpp | 12 +- - src/hotspot/share/services/attachListener.cpp | 15 ++- - .../share/classes/sun/tools/jmap/JMap.java | 41 +++++-- - test/jdk/sun/tools/jmap/BasicJMapTest.java | 55 +++++++++ - 16 files changed, 442 insertions(+), 30 deletions(-) - -diff --git a/src/hotspot/share/gc/g1/g1CollectedHeap.cpp b/src/hotspot/share/gc/g1/g1CollectedHeap.cpp -index 7e9c6254c..fd2da14a3 100644 ---- a/src/hotspot/share/gc/g1/g1CollectedHeap.cpp -+++ b/src/hotspot/share/gc/g1/g1CollectedHeap.cpp -@@ -77,6 +77,7 @@ - #include "gc/shared/weakProcessor.hpp" - #include "logging/log.hpp" - #include "memory/allocation.hpp" -+#include "memory/heapInspection.hpp" - #include "memory/iterator.hpp" - #include "memory/metaspaceShared.hpp" - #include "memory/resourceArea.hpp" -@@ -2208,6 +2209,30 @@ void G1CollectedHeap::object_iterate(ObjectClosure* cl) { - heap_region_iterate(&blk); - } - -+class G1ParallelObjectIterator : public ParallelObjectIterator { -+private: -+ G1CollectedHeap* _heap; -+ HeapRegionClaimer _claimer; -+ -+public: -+ G1ParallelObjectIterator(uint thread_num) : -+ _heap(G1CollectedHeap::heap()), -+ _claimer(thread_num == 0 ? G1CollectedHeap::heap()->workers()->active_workers() : thread_num) {} -+ -+ virtual void object_iterate(ObjectClosure* cl, uint worker_id) { -+ _heap->object_iterate_parallel(cl, worker_id, &_claimer); -+ } -+}; -+ -+ParallelObjectIterator* G1CollectedHeap::parallel_object_iterator(uint thread_num) { -+ return new G1ParallelObjectIterator(thread_num); -+} -+ -+void G1CollectedHeap::object_iterate_parallel(ObjectClosure* cl, uint worker_id, HeapRegionClaimer* claimer) { -+ IterateObjectClosureRegionClosure blk(cl); -+ heap_region_par_iterate_from_worker_offset(&blk, claimer, worker_id); -+} -+ - void G1CollectedHeap::keep_alive(oop obj) { - G1BarrierSet::enqueue(obj); - } -diff --git a/src/hotspot/share/gc/g1/g1CollectedHeap.hpp b/src/hotspot/share/gc/g1/g1CollectedHeap.hpp -index bb46cae83..82f59d69b 100644 ---- a/src/hotspot/share/gc/g1/g1CollectedHeap.hpp -+++ b/src/hotspot/share/gc/g1/g1CollectedHeap.hpp -@@ -1125,9 +1125,13 @@ public: - - // Iteration functions. - -+ void object_iterate_parallel(ObjectClosure* cl, uint worker_id, HeapRegionClaimer* claimer); -+ - // Iterate over all objects, calling "cl.do_object" on each. - virtual void object_iterate(ObjectClosure* cl); - -+ virtual ParallelObjectIterator* parallel_object_iterator(uint thread_num); -+ - virtual void safe_object_iterate(ObjectClosure* cl) { - object_iterate(cl); - } -diff --git a/src/hotspot/share/gc/parallel/parallelScavengeHeap.cpp b/src/hotspot/share/gc/parallel/parallelScavengeHeap.cpp -index 29f967fb3..66e1b32a6 100644 ---- a/src/hotspot/share/gc/parallel/parallelScavengeHeap.cpp -+++ b/src/hotspot/share/gc/parallel/parallelScavengeHeap.cpp -@@ -523,6 +523,70 @@ void ParallelScavengeHeap::object_iterate(ObjectClosure* cl) { - old_gen()->object_iterate(cl); - } - -+// The HeapBlockClaimer is used during parallel iteration over the heap, -+// allowing workers to claim heap areas ("blocks"), gaining exclusive rights to these. -+// The eden and survivor spaces are treated as single blocks as it is hard to divide -+// these spaces. -+// The old space is divided into fixed-size blocks. -+class HeapBlockClaimer : public StackObj { -+ size_t _claimed_index; -+ -+public: -+ static const size_t InvalidIndex = SIZE_MAX; -+ static const size_t EdenIndex = 0; -+ static const size_t SurvivorIndex = 1; -+ static const size_t NumNonOldGenClaims = 2; -+ -+ HeapBlockClaimer() : _claimed_index(EdenIndex) { } -+ // Claim the block and get the block index. -+ size_t claim_and_get_block() { -+ size_t block_index; -+ block_index = Atomic::add(1u, &_claimed_index) - 1; // TODO: original impl is: Atomic::fetch_and_add(&_claimed_index, 1u); -+ -+ PSOldGen* old_gen = ParallelScavengeHeap::heap()->old_gen(); -+ size_t num_claims = old_gen->num_iterable_blocks() + NumNonOldGenClaims; -+ -+ return block_index < num_claims ? block_index : InvalidIndex; -+ } -+}; -+ -+void ParallelScavengeHeap::object_iterate_parallel(ObjectClosure* cl, -+ HeapBlockClaimer* claimer) { -+ size_t block_index = claimer->claim_and_get_block(); -+ // Iterate until all blocks are claimed -+ if (block_index == HeapBlockClaimer::EdenIndex) { -+ young_gen()->eden_space()->object_iterate(cl); -+ block_index = claimer->claim_and_get_block(); -+ } -+ if (block_index == HeapBlockClaimer::SurvivorIndex) { -+ young_gen()->from_space()->object_iterate(cl); -+ young_gen()->to_space()->object_iterate(cl); -+ block_index = claimer->claim_and_get_block(); -+ } -+ while (block_index != HeapBlockClaimer::InvalidIndex) { -+ old_gen()->object_iterate_block(cl, block_index - HeapBlockClaimer::NumNonOldGenClaims); -+ block_index = claimer->claim_and_get_block(); -+ } -+} -+ -+class PSScavengeParallelObjectIterator : public ParallelObjectIterator { -+private: -+ ParallelScavengeHeap* _heap; -+ HeapBlockClaimer _claimer; -+ -+public: -+ PSScavengeParallelObjectIterator() : -+ _heap(ParallelScavengeHeap::heap()), -+ _claimer() {} -+ -+ virtual void object_iterate(ObjectClosure* cl, uint worker_id) { -+ _heap->object_iterate_parallel(cl, &_claimer); -+ } -+}; -+ -+ParallelObjectIterator* ParallelScavengeHeap::parallel_object_iterator(uint thread_num) { -+ return new PSScavengeParallelObjectIterator(); -+} - - HeapWord* ParallelScavengeHeap::block_start(const void* addr) const { - if (young_gen()->is_in_reserved(addr)) { -diff --git a/src/hotspot/share/gc/parallel/parallelScavengeHeap.hpp b/src/hotspot/share/gc/parallel/parallelScavengeHeap.hpp -index 5d18efb92..0a9b7bd3f 100644 ---- a/src/hotspot/share/gc/parallel/parallelScavengeHeap.hpp -+++ b/src/hotspot/share/gc/parallel/parallelScavengeHeap.hpp -@@ -44,6 +44,7 @@ - class AdjoiningGenerations; - class GCHeapSummary; - class GCTaskManager; -+class HeapBlockClaimer; - class MemoryManager; - class MemoryPool; - class PSAdaptiveSizePolicy; -@@ -79,6 +80,8 @@ class ParallelScavengeHeap : public CollectedHeap { - MemoryPool* _survivor_pool; - MemoryPool* _old_pool; - -+ WorkGang _workers; -+ - virtual void initialize_serviceability(); - - void trace_heap(GCWhen::Type when, const GCTracer* tracer); -@@ -93,7 +96,20 @@ class ParallelScavengeHeap : public CollectedHeap { - - public: - ParallelScavengeHeap(GenerationSizer* policy) : -- CollectedHeap(), _collector_policy(policy), _death_march_count(0) { } -+ CollectedHeap(), -+ _collector_policy(policy), -+ _death_march_count(0), -+ _young_manager(NULL), -+ _old_manager(NULL), -+ _eden_pool(NULL), -+ _survivor_pool(NULL), -+ _old_pool(NULL), -+ _workers("GC Thread", -+ ParallelGCThreads, -+ true /* are_GC_task_threads */, -+ false /* are_ConcurrentGC_threads */) { -+ _workers.initialize_workers(); -+ } - - // For use by VM operations - enum CollectionType { -@@ -217,6 +233,8 @@ class ParallelScavengeHeap : public CollectedHeap { - - void object_iterate(ObjectClosure* cl); - void safe_object_iterate(ObjectClosure* cl) { object_iterate(cl); } -+ void object_iterate_parallel(ObjectClosure* cl, HeapBlockClaimer* claimer); -+ virtual ParallelObjectIterator* parallel_object_iterator(uint thread_num); - - HeapWord* block_start(const void* addr) const; - size_t block_size(const HeapWord* addr) const; -@@ -232,6 +250,8 @@ class ParallelScavengeHeap : public CollectedHeap { - virtual void gc_threads_do(ThreadClosure* tc) const; - virtual void print_tracing_info() const; - -+ virtual WorkGang* get_safepoint_workers() { return &_workers; } -+ - void verify(VerifyOption option /* ignored */); - - // Resize the young generation. The reserved space for the -diff --git a/src/hotspot/share/gc/parallel/psOldGen.cpp b/src/hotspot/share/gc/parallel/psOldGen.cpp -index 35844b14b..dbb5148fd 100644 ---- a/src/hotspot/share/gc/parallel/psOldGen.cpp -+++ b/src/hotspot/share/gc/parallel/psOldGen.cpp -@@ -213,6 +213,38 @@ HeapWord* PSOldGen::allocate(size_t word_size) { - return res; - } - -+size_t PSOldGen::num_iterable_blocks() const { -+ return (object_space()->used_in_bytes() + IterateBlockSize - 1) / IterateBlockSize; -+} -+ -+void PSOldGen::object_iterate_block(ObjectClosure* cl, size_t block_index) { -+ size_t block_word_size = IterateBlockSize / HeapWordSize; -+ assert((block_word_size % (ObjectStartArray::block_size)) == 0, -+ "Block size not a multiple of start_array block"); -+ -+ MutableSpace *space = object_space(); -+ -+ HeapWord* begin = space->bottom() + block_index * block_word_size; -+ HeapWord* end = MIN2(space->top(), begin + block_word_size); -+ -+ if (!start_array()->object_starts_in_range(begin, end)) { -+ return; -+ } -+ -+ // Get object starting at or reaching into this block. -+ HeapWord* start = start_array()->object_start(begin); -+ if (start < begin) { -+ start += oop(start)->size(); -+ } -+ assert(start >= begin, -+ "Object address" PTR_FORMAT " must be larger or equal to block address at " PTR_FORMAT, -+ p2i(start), p2i(begin)); -+ // Iterate all objects until the end. -+ for (HeapWord* p = start; p < end; p += oop(p)->size()) { -+ cl->do_object(oop(p)); -+ } -+} -+ - HeapWord* PSOldGen::expand_and_allocate(size_t word_size) { - expand(word_size*HeapWordSize); - if (GCExpandToAllocateDelayMillis > 0) { -diff --git a/src/hotspot/share/gc/parallel/psOldGen.hpp b/src/hotspot/share/gc/parallel/psOldGen.hpp -index fa27f5a04..fa6e4849b 100644 ---- a/src/hotspot/share/gc/parallel/psOldGen.hpp -+++ b/src/hotspot/share/gc/parallel/psOldGen.hpp -@@ -59,6 +59,9 @@ class PSOldGen : public CHeapObj { - const size_t _min_gen_size; - const size_t _max_gen_size; - -+ // Block size for parallel iteration -+ static const size_t IterateBlockSize = 1024 * 1024; -+ - // Used when initializing the _name field. - static inline const char* select_name(); - -@@ -195,6 +198,14 @@ class PSOldGen : public CHeapObj { - void oop_iterate(OopIterateClosure* cl) { object_space()->oop_iterate(cl); } - void object_iterate(ObjectClosure* cl) { object_space()->object_iterate(cl); } - -+ // Number of blocks to be iterated over in the used part of old gen. -+ size_t num_iterable_blocks() const; -+ // Iterate the objects starting in block block_index within [bottom, top) of the -+ // old gen. The object just reaching into this block is not iterated over. -+ // A block is an evenly sized non-overlapping part of the old gen of -+ // IterateBlockSize bytes. -+ void object_iterate_block(ObjectClosure* cl, size_t block_index); -+ - // Debugging - do not use for time critical operations - virtual void print() const; - virtual void print_on(outputStream* st) const; -diff --git a/src/hotspot/share/gc/shared/collectedHeap.hpp b/src/hotspot/share/gc/shared/collectedHeap.hpp -index 47acf22cb..bcd4da29a 100644 ---- a/src/hotspot/share/gc/shared/collectedHeap.hpp -+++ b/src/hotspot/share/gc/shared/collectedHeap.hpp -@@ -28,6 +28,7 @@ - #include "gc/shared/gcCause.hpp" - #include "gc/shared/gcWhen.hpp" - #include "memory/allocation.hpp" -+#include "memory/heapInspection.hpp" - #include "runtime/handles.hpp" - #include "runtime/perfData.hpp" - #include "runtime/safepoint.hpp" -@@ -42,6 +43,7 @@ - // class defines the functions that a heap must implement, and contains - // infrastructure common to all heaps. - -+class AbstractGangTask; - class AdaptiveSizePolicy; - class BarrierSet; - class CollectorPolicy; -@@ -83,6 +85,11 @@ class GCHeapLog : public EventLogBase { - } - }; - -+class ParallelObjectIterator : public CHeapObj { -+public: -+ virtual void object_iterate(ObjectClosure* cl, uint worker_id) = 0; -+}; -+ - // - // CollectedHeap - // GenCollectedHeap -@@ -434,6 +441,10 @@ class CollectedHeap : public CHeapObj { - // Iterate over all objects, calling "cl.do_object" on each. - virtual void object_iterate(ObjectClosure* cl) = 0; - -+ virtual ParallelObjectIterator* parallel_object_iterator(uint thread_num) { -+ return NULL; -+ } -+ - // Similar to object_iterate() except iterates only - // over live objects. - virtual void safe_object_iterate(ObjectClosure* cl) = 0; -diff --git a/src/hotspot/share/gc/shared/vmGCOperations.cpp b/src/hotspot/share/gc/shared/vmGCOperations.cpp -index b02305a6e..728290a7b 100644 ---- a/src/hotspot/share/gc/shared/vmGCOperations.cpp -+++ b/src/hotspot/share/gc/shared/vmGCOperations.cpp -@@ -154,7 +154,7 @@ void VM_GC_HeapInspection::doit() { - } - HeapInspection inspect(_csv_format, _print_help, _print_class_stats, - _columns); -- inspect.heap_inspection(_out); -+ inspect.heap_inspection(_out, _parallel_thread_num); - } - - -diff --git a/src/hotspot/share/gc/shared/vmGCOperations.hpp b/src/hotspot/share/gc/shared/vmGCOperations.hpp -index 65876e559..ef73b45de 100644 ---- a/src/hotspot/share/gc/shared/vmGCOperations.hpp -+++ b/src/hotspot/share/gc/shared/vmGCOperations.hpp -@@ -125,18 +125,21 @@ class VM_GC_HeapInspection: public VM_GC_Operation { - private: - outputStream* _out; - bool _full_gc; -+ uint _parallel_thread_num; - bool _csv_format; // "comma separated values" format for spreadsheet. - bool _print_help; - bool _print_class_stats; - const char* _columns; - public: -- VM_GC_HeapInspection(outputStream* out, bool request_full_gc) : -+ VM_GC_HeapInspection(outputStream* out, bool request_full_gc, -+ uint parallel_thread_num = 1) : - VM_GC_Operation(0 /* total collections, dummy, ignored */, - GCCause::_heap_inspection /* GC Cause */, - 0 /* total full collections, dummy, ignored */, - request_full_gc) { - _out = out; - _full_gc = request_full_gc; -+ _parallel_thread_num = parallel_thread_num; - _csv_format = false; - _print_help = false; - _print_class_stats = false; -diff --git a/src/hotspot/share/gc/shared/workgroup.hpp b/src/hotspot/share/gc/shared/workgroup.hpp -index 8b46d3bc4..109649df0 100644 ---- a/src/hotspot/share/gc/shared/workgroup.hpp -+++ b/src/hotspot/share/gc/shared/workgroup.hpp -@@ -228,6 +228,27 @@ protected: - virtual AbstractGangWorker* allocate_worker(uint which); - }; - -+// Temporarily try to set the number of active workers. -+// It's not guaranteed that it succeeds, and users need to -+// query the number of active workers. -+class WithUpdatedActiveWorkers : public StackObj { -+private: -+ AbstractWorkGang* const _gang; -+ const uint _old_active_workers; -+ -+public: -+ WithUpdatedActiveWorkers(AbstractWorkGang* gang, uint requested_num_workers) : -+ _gang(gang), -+ _old_active_workers(gang->active_workers()) { -+ uint capped_num_workers = MIN2(requested_num_workers, gang->total_workers()); -+ gang->update_active_workers(capped_num_workers); -+ } -+ -+ ~WithUpdatedActiveWorkers() { -+ _gang->update_active_workers(_old_active_workers); -+ } -+}; -+ - // Several instances of this class run in parallel as workers for a gang. - class AbstractGangWorker: public WorkerThread { - public: -diff --git a/src/hotspot/share/memory/heapInspection.cpp b/src/hotspot/share/memory/heapInspection.cpp -index 9c2cdc117..dbc0eb274 100644 ---- a/src/hotspot/share/memory/heapInspection.cpp -+++ b/src/hotspot/share/memory/heapInspection.cpp -@@ -31,6 +31,7 @@ - #include "memory/resourceArea.hpp" - #include "oops/oop.inline.hpp" - #include "oops/reflectionAccessorImplKlassHelper.hpp" -+#include "runtime/atomic.hpp" - #include "runtime/os.hpp" - #include "utilities/globalDefinitions.hpp" - #include "utilities/macros.hpp" -@@ -236,6 +237,41 @@ size_t KlassInfoTable::size_of_instances_in_words() const { - return _size_of_instances_in_words; - } - -+// Return false if the entry could not be recorded on account -+// of running out of space required to create a new entry. -+bool KlassInfoTable::merge_entry(const KlassInfoEntry* cie) { -+ Klass* k = cie->klass(); -+ KlassInfoEntry* elt = lookup(k); -+ // elt may be NULL if it's a new klass for which we -+ // could not allocate space for a new entry in the hashtable. -+ if (elt != NULL) { -+ elt->set_count(elt->count() + cie->count()); -+ elt->set_words(elt->words() + cie->words()); -+ _size_of_instances_in_words += cie->words(); -+ return true; -+ } -+ return false; -+} -+ -+class KlassInfoTableMergeClosure : public KlassInfoClosure { -+ private: -+ KlassInfoTable* _dest; -+ bool _success; -+ public: -+ KlassInfoTableMergeClosure(KlassInfoTable* table) : _dest(table), _success(true) {} -+ void do_cinfo(KlassInfoEntry* cie) { -+ _success &= _dest->merge_entry(cie); -+ } -+ bool success() { return _success; } -+}; -+ -+// merge from table -+bool KlassInfoTable::merge(KlassInfoTable* table) { -+ KlassInfoTableMergeClosure closure(this); -+ table->iterate(&closure); -+ return closure.success(); -+} -+ - int KlassInfoHisto::sort_helper(KlassInfoEntry** e1, KlassInfoEntry** e2) { - return (*e1)->compare(*e1,*e2); - } -@@ -687,7 +723,7 @@ class HistoClosure : public KlassInfoClosure { - class RecordInstanceClosure : public ObjectClosure { - private: - KlassInfoTable* _cit; -- size_t _missed_count; -+ uintx _missed_count; - BoolObjectClosure* _filter; - public: - RecordInstanceClosure(KlassInfoTable* cit, BoolObjectClosure* filter) : -@@ -701,7 +737,7 @@ class RecordInstanceClosure : public ObjectClosure { - } - } - -- size_t missed_count() { return _missed_count; } -+ uintx missed_count() { return _missed_count; } - - private: - bool should_visit(oop obj) { -@@ -709,15 +745,73 @@ class RecordInstanceClosure : public ObjectClosure { - } - }; - --size_t HeapInspection::populate_table(KlassInfoTable* cit, BoolObjectClosure *filter) { -- ResourceMark rm; -+// Heap inspection for every worker. -+// When native OOM hanppens for KlassInfoTable, set _success to false. -+void ParHeapInspectTask::work(uint worker_id) { -+ uintx missed_count = 0; -+ bool merge_success = true; -+ if (!Atomic::load(&_success)) { -+ // other worker has failed on parallel iteration. -+ return; -+ } - -+ KlassInfoTable cit(false); -+ if (cit.allocation_failed()) { -+ // fail to allocate memory, stop parallel mode -+ Atomic::store(false, &_success); -+ return; -+ } -+ RecordInstanceClosure ric(&cit, _filter); -+ _poi->object_iterate(&ric, worker_id); -+ missed_count = ric.missed_count(); -+ { -+ MutexLocker x(&_mutex); -+ merge_success = _shared_cit->merge(&cit); -+ } -+ if (merge_success) { -+ Atomic::add(missed_count, &_missed_count); -+ } else { -+ Atomic::store(false, &_success); -+ } -+} -+ -+size_t HeapInspection::populate_table(KlassInfoTable* cit, BoolObjectClosure *filter, uint parallel_thread_num) { -+ // Try parallel first. -+ if (parallel_thread_num > 1) { -+ ResourceMark rm; -+ -+ WorkGang* gang = Universe::heap()->get_safepoint_workers(); -+ if (gang != NULL) { -+ // The GC provided a WorkGang to be used during a safepoint. -+ -+ // Can't run with more threads than provided by the WorkGang. -+ WithUpdatedActiveWorkers update_and_restore(gang, parallel_thread_num); -+ -+ ParallelObjectIterator* poi = Universe::heap()->parallel_object_iterator(gang->active_workers()); -+ if (poi != NULL) { -+ // The GC supports parallel object iteration. -+ -+ ParHeapInspectTask task(poi, cit, filter); -+ // Run task with the active workers. -+ -+ gang->run_task(&task); -+ -+ delete poi; -+ if (task.success()) { -+ return task.missed_count(); -+ } -+ } -+ } -+ } -+ -+ ResourceMark rm; -+ // If no parallel iteration available, run serially. - RecordInstanceClosure ric(cit, filter); - Universe::heap()->safe_object_iterate(&ric); - return ric.missed_count(); - } - --void HeapInspection::heap_inspection(outputStream* st) { -+void HeapInspection::heap_inspection(outputStream* st, uint parallel_thread_num) { - ResourceMark rm; - - if (_print_help) { -@@ -741,9 +835,9 @@ void HeapInspection::heap_inspection(outputStream* st) { - KlassInfoTable cit(_print_class_stats); - if (!cit.allocation_failed()) { - // populate table with object allocation info -- size_t missed_count = populate_table(&cit); -+ uintx missed_count = populate_table(&cit, NULL, parallel_thread_num); - if (missed_count != 0) { -- st->print_cr("WARNING: Ran out of C-heap; undercounted " SIZE_FORMAT -+ st->print_cr("WARNING: Ran out of C-heap; undercounted " UINTX_FORMAT - " total instances in data below", - missed_count); - } -diff --git a/src/hotspot/share/memory/heapInspection.hpp b/src/hotspot/share/memory/heapInspection.hpp -index d8935dc68..026293bf7 100644 ---- a/src/hotspot/share/memory/heapInspection.hpp -+++ b/src/hotspot/share/memory/heapInspection.hpp -@@ -25,12 +25,15 @@ - #ifndef SHARE_VM_MEMORY_HEAPINSPECTION_HPP - #define SHARE_VM_MEMORY_HEAPINSPECTION_HPP - -+#include "gc/shared/workgroup.hpp" - #include "memory/allocation.hpp" - #include "oops/objArrayOop.hpp" - #include "oops/oop.hpp" - #include "oops/annotations.hpp" - #include "utilities/macros.hpp" - -+class ParallelObjectIterator; -+ - #if INCLUDE_SERVICES - - -@@ -261,6 +264,8 @@ class KlassInfoTable: public StackObj { - void iterate(KlassInfoClosure* cic); - bool allocation_failed() { return _buckets == NULL; } - size_t size_of_instances_in_words() const; -+ bool merge(KlassInfoTable* table); -+ bool merge_entry(const KlassInfoEntry* cie); - - friend class KlassInfoHisto; - friend class KlassHierarchy; -@@ -364,11 +369,46 @@ class HeapInspection : public StackObj { - bool print_class_stats, const char *columns) : - _csv_format(csv_format), _print_help(print_help), - _print_class_stats(print_class_stats), _columns(columns) {} -- void heap_inspection(outputStream* st) NOT_SERVICES_RETURN; -- size_t populate_table(KlassInfoTable* cit, BoolObjectClosure* filter = NULL) NOT_SERVICES_RETURN_(0); -+ void heap_inspection(outputStream* st, uint parallel_thread_num = 1) NOT_SERVICES_RETURN; -+ size_t populate_table(KlassInfoTable* cit, BoolObjectClosure* filter = NULL, uint parallel_thread_num = 1) NOT_SERVICES_RETURN_(0); - static void find_instances_at_safepoint(Klass* k, GrowableArray* result) NOT_SERVICES_RETURN; - private: - void iterate_over_heap(KlassInfoTable* cit, BoolObjectClosure* filter = NULL); - }; - -+// Parallel heap inspection task. Parallel inspection can fail due to -+// a native OOM when allocating memory for TL-KlassInfoTable. -+// _success will be set false on an OOM, and serial inspection tried. -+class ParHeapInspectTask : public AbstractGangTask { -+private: -+ ParallelObjectIterator *_poi; -+ KlassInfoTable *_shared_cit; -+ BoolObjectClosure *_filter; -+ uintx _missed_count; -+ bool _success; -+ Mutex _mutex; -+ -+public: -+ ParHeapInspectTask(ParallelObjectIterator *poi, -+ KlassInfoTable *shared_cit, -+ BoolObjectClosure *filter) : -+ AbstractGangTask("Iterating heap"), -+ _poi(poi), -+ _shared_cit(shared_cit), -+ _filter(filter), -+ _missed_count(0), -+ _success(true), -+ _mutex(Mutex::leaf, "Parallel heap iteration data merge lock") {} -+ -+ uintx missed_count() const { -+ return _missed_count; -+ } -+ -+ bool success() { -+ return _success; -+ } -+ -+ virtual void work(uint worker_id); -+}; -+ - #endif // SHARE_VM_MEMORY_HEAPINSPECTION_HPP -diff --git a/src/hotspot/share/runtime/arguments.hpp b/src/hotspot/share/runtime/arguments.hpp -index bd439aab0..9827a4c66 100644 ---- a/src/hotspot/share/runtime/arguments.hpp -+++ b/src/hotspot/share/runtime/arguments.hpp -@@ -450,12 +450,6 @@ class Arguments : AllStatic { - static ArgsRange check_memory_size(julong size, julong min_size, julong max_size); - static ArgsRange parse_memory_size(const char* s, julong* long_arg, - julong min_size, julong max_size = max_uintx); -- // Parse a string for a unsigned integer. Returns true if value -- // is an unsigned integer greater than or equal to the minimum -- // parameter passed and returns the value in uintx_arg. Returns -- // false otherwise, with uintx_arg undefined. -- static bool parse_uintx(const char* value, uintx* uintx_arg, -- uintx min_size); - - // methods to build strings from individual args - static void build_jvm_args(const char* arg); -@@ -493,6 +487,12 @@ class Arguments : AllStatic { - public: - // Parses the arguments, first phase - static jint parse(const JavaVMInitArgs* args); -+ // Parse a string for a unsigned integer. Returns true if value -+ // is an unsigned integer greater than or equal to the minimum -+ // parameter passed and returns the value in uintx_arg. Returns -+ // false otherwise, with uintx_arg undefined. -+ static bool parse_uintx(const char* value, uintx* uintx_arg, -+ uintx min_size); - // Apply ergonomics - static jint apply_ergo(); - // Adjusts the arguments after the OS have adjusted the arguments -diff --git a/src/hotspot/share/services/attachListener.cpp b/src/hotspot/share/services/attachListener.cpp -index fc77970a0..b0f3b2e87 100644 ---- a/src/hotspot/share/services/attachListener.cpp -+++ b/src/hotspot/share/services/attachListener.cpp -@@ -258,9 +258,11 @@ jint dump_heap(AttachOperation* op, outputStream* out) { - // - // Input arguments :- - // arg0: "-live" or "-all" -+// arg1: parallel thread number - static jint heap_inspection(AttachOperation* op, outputStream* out) { - bool live_objects_only = true; // default is true to retain the behavior before this change is made - const char* arg0 = op->arg(0); -+ uint parallel_thread_num = MAX2(1, (uint)os::initial_active_processor_count() * 3 / 8); - if (arg0 != NULL && (strlen(arg0) > 0)) { - if (strcmp(arg0, "-all") != 0 && strcmp(arg0, "-live") != 0) { - out->print_cr("Invalid argument to inspectheap operation: %s", arg0); -@@ -268,7 +270,18 @@ static jint heap_inspection(AttachOperation* op, outputStream* out) { - } - live_objects_only = strcmp(arg0, "-live") == 0; - } -- VM_GC_HeapInspection heapop(out, live_objects_only /* request full gc */); -+ -+ const char* num_str = op->arg(1); -+ if (num_str != NULL && num_str[0] != '\0') { -+ uintx num; -+ if (!Arguments::parse_uintx(num_str, &num, 0)) { -+ out->print_cr("Invalid parallel thread number: [%s]", num_str); -+ return JNI_ERR; -+ } -+ parallel_thread_num = num == 0 ? parallel_thread_num : (uint)num; -+ } -+ -+ VM_GC_HeapInspection heapop(out, live_objects_only /* request full gc */, parallel_thread_num); - VMThread::execute(&heapop); - return JNI_OK; - } -diff --git a/src/jdk.jcmd/share/classes/sun/tools/jmap/JMap.java b/src/jdk.jcmd/share/classes/sun/tools/jmap/JMap.java -index f2db61ab7..9af74f362 100644 ---- a/src/jdk.jcmd/share/classes/sun/tools/jmap/JMap.java -+++ b/src/jdk.jcmd/share/classes/sun/tools/jmap/JMap.java -@@ -149,18 +149,28 @@ public class JMap { - throws AttachNotSupportedException, IOException, - UnsupportedEncodingException { - String liveopt = "-all"; -- if (options.equals("") || options.equals("all")) { -- // pass -- } -- else if (options.equals("live")) { -- liveopt = "-live"; -- } -- else { -- usage(1); -+ String parallel = null; -+ String subopts[] = options.split(","); -+ -+ for (int i = 0; i < subopts.length; i++) { -+ String subopt = subopts[i]; -+ if (subopt.equals("") || subopt.equals("all")) { -+ // pass -+ } else if (subopt.equals("live")) { -+ liveopt = "-live"; -+ } else if (subopt.startsWith("parallel=")) { -+ parallel = subopt.substring("parallel=".length()); -+ if (parallel == null) { -+ System.err.println("Fail: no number provided in option: '" + subopt + "'"); -+ System.exit(1); -+ } -+ } else { -+ usage(1); -+ } - } - - // inspectHeap is not the same as jcmd GC.class_histogram -- executeCommandForPid(pid, "inspectheap", liveopt); -+ executeCommandForPid(pid, "inspectheap", liveopt, parallel); - } - - private static void dump(String pid, String options) -@@ -246,9 +256,8 @@ public class JMap { - System.err.println(" to connect to running process and print class loader statistics"); - System.err.println(" jmap -finalizerinfo "); - System.err.println(" to connect to running process and print information on objects awaiting finalization"); -- System.err.println(" jmap -histo[:live] "); -+ System.err.println(" jmap -histo: "); - System.err.println(" to connect to running process and print histogram of java object heap"); -- System.err.println(" if the \"live\" suboption is specified, only count live objects"); - System.err.println(" jmap -dump: "); - System.err.println(" to connect to running process and dump java heap"); - System.err.println(" jmap -? -h --help"); -@@ -261,6 +270,16 @@ public class JMap { - System.err.println(" file= dump heap to "); - System.err.println(""); - System.err.println(" Example: jmap -dump:live,format=b,file=heap.bin "); -+ System.err.println(""); -+ System.err.println(" histo-options:"); -+ System.err.println(" live count only live objects"); -+ System.err.println(" all count all objects in the heap (default if one of \"live\" or \"all\" is not specified)"); -+ System.err.println(" parallel= parallel threads number for heap iteration:"); -+ System.err.println(" parallel=0 default behavior, use predefined number of threads"); -+ System.err.println(" parallel=1 disable parallel heap iteration"); -+ System.err.println(" parallel= use N threads for parallel heap iteration"); -+ System.err.println(""); -+ System.err.println(" Example: jmap -histo:live,parallel=2 "); - System.exit(exit); - } - } -diff --git a/test/jdk/sun/tools/jmap/BasicJMapTest.java b/test/jdk/sun/tools/jmap/BasicJMapTest.java -index c0432dede..960705e24 100644 ---- a/test/jdk/sun/tools/jmap/BasicJMapTest.java -+++ b/test/jdk/sun/tools/jmap/BasicJMapTest.java -@@ -45,6 +45,35 @@ import jdk.testlibrary.ProcessTools; - * @build jdk.test.lib.hprof.util.* - * @run main/timeout=240 BasicJMapTest - */ -+ -+/* -+ * @test id=Parallel -+ * @summary Unit test for jmap utility (Parallel GC) -+ * @key intermittent -+ * @library /lib/testlibrary -+ * @library /test/lib -+ * @build jdk.testlibrary.* -+ * @build jdk.test.lib.hprof.* -+ * @build jdk.test.lib.hprof.model.* -+ * @build jdk.test.lib.hprof.parser.* -+ * @build jdk.test.lib.hprof.util.* -+ * @run main/othervm/timeout=240 -XX:+UseParallelGC BasicJMapTest -+ */ -+ -+/* -+ * @test id=G1 -+ * @summary Unit test for jmap utility (G1 GC) -+ * @key intermittent -+ * @library /lib/testlibrary -+ * @library /test/lib -+ * @build jdk.testlibrary.* -+ * @build jdk.test.lib.hprof.* -+ * @build jdk.test.lib.hprof.model.* -+ * @build jdk.test.lib.hprof.parser.* -+ * @build jdk.test.lib.hprof.util.* -+ * @run main/othervm/timeout=240 -XX:+UseG1GC BasicJMapTest -+ */ -+ - public class BasicJMapTest { - - private static ProcessBuilder processBuilder = new ProcessBuilder(); -@@ -68,6 +97,32 @@ public class BasicJMapTest { - output.shouldHaveExitValue(0); - } - -+ private static void testHistoParallelZero() throws Exception { -+ OutputAnalyzer output = jmap("-histo:parallel=0"); -+ output.shouldHaveExitValue(0); -+ } -+ -+ private static void testHistoParallel() throws Exception { -+ OutputAnalyzer output = jmap("-histo:parallel=2"); -+ output.shouldHaveExitValue(0); -+ } -+ -+ private static void testHistoNonParallel() throws Exception { -+ OutputAnalyzer output = jmap("-histo:parallel=1"); -+ output.shouldHaveExitValue(0); -+ } -+ -+ private static void testHistoMultipleParameters() throws Exception { -+ OutputAnalyzer output = jmap("-histo:parallel=2,live"); -+ output.shouldHaveExitValue(0); -+ output = jmap("-histo:live,parallel=2"); -+ output.shouldHaveExitValue(0); -+ output = jmap("-histo:parallel=2,all"); -+ output.shouldHaveExitValue(0); -+ output = jmap("-histo:all,parallel=2"); -+ output.shouldHaveExitValue(0); -+ } -+ - private static void testFinalizerInfo() throws Exception { - OutputAnalyzer output = jmap("-finalizerinfo"); - output.shouldHaveExitValue(0); --- -2.19.0 - diff --git a/8224675-Late-GC-barrier-insertion-for-ZGC.patch b/8224675-Late-GC-barrier-insertion-for-ZGC.patch index 20337cf0f77fc71fd4452fe601c4365adb0730bc..b804b1ce102def66d795208d3818ccd15d312bbf 100644 --- a/8224675-Late-GC-barrier-insertion-for-ZGC.patch +++ b/8224675-Late-GC-barrier-insertion-for-ZGC.patch @@ -2818,39 +2818,10 @@ index 50c0c2d..05ec9fa 100644 case Op_LoadS: case Op_LoadKlass: diff --git a/src/hotspot/share/opto/loopnode.cpp b/src/hotspot/share/opto/loopnode.cpp -index 641c829..6aff3d5 100644 +index 5454d1350..d7eb3996b 100644 --- a/src/hotspot/share/opto/loopnode.cpp +++ b/src/hotspot/share/opto/loopnode.cpp -@@ -990,7 +990,7 @@ void LoopNode::verify_strip_mined(int expect_skeleton) const { - wq.push(u); - bool found_sfpt = false; - for (uint next = 0; next < wq.size() && !found_sfpt; next++) { -- Node *n = wq.at(next); -+ Node* n = wq.at(next); - for (DUIterator_Fast imax, i = n->fast_outs(imax); i < imax && !found_sfpt; i++) { - Node* u = n->fast_out(i); - if (u == sfpt) { -@@ -1004,6 +1004,19 @@ void LoopNode::verify_strip_mined(int expect_skeleton) const { - assert(found_sfpt, "no node in loop that's not input to safepoint"); - } - } -+ -+ if (UseZGC && !inner_out->in(0)->is_CountedLoopEnd()) { -+ // In some very special cases there can be a load that has no other uses than the -+ // counted loop safepoint. Then its loadbarrier will be placed between the inner -+ // loop exit and the safepoint. This is very rare -+ -+ Node* ifnode = inner_out->in(1)->in(0); -+ // Region->IfTrue->If == Region->Iffalse->If -+ if (ifnode == inner_out->in(2)->in(0)) { -+ inner_out = ifnode->in(0); -+ } -+ } -+ - CountedLoopEndNode* cle = inner_out->in(0)->as_CountedLoopEnd(); - assert(cle == inner->loopexit_or_null(), "mismatch"); - bool has_skeleton = outer_le->in(1)->bottom_type()->singleton() && outer_le->in(1)->bottom_type()->is_int()->get_con() == 0; -@@ -2729,7 +2742,7 @@ bool PhaseIdealLoop::process_expensive_nodes() { +@@ -2762,7 +2762,7 @@ bool PhaseIdealLoop::only_has_infinite_loops() { //----------------------------build_and_optimize------------------------------- // Create a PhaseLoop. Build the ideal Loop tree. Map each Ideal Node to // its corresponding LoopNode. If 'optimize' is true, do some loop cleanups. @@ -2859,7 +2830,7 @@ index 641c829..6aff3d5 100644 bool do_split_ifs = (mode == LoopOptsDefault || mode == LoopOptsLastRound); bool skip_loop_opts = (mode == LoopOptsNone); #if INCLUDE_SHENANDOAHGC -@@ -2800,7 +2813,8 @@ void PhaseIdealLoop::build_and_optimize(LoopOptsMode mode) { +@@ -2840,7 +2840,8 @@ void PhaseIdealLoop::build_and_optimize(LoopOptsMode mode) { } // Nothing to do, so get out @@ -2869,7 +2840,7 @@ index 641c829..6aff3d5 100644 bool do_expensive_nodes = C->should_optimize_expensive_nodes(_igvn); if (stop_early && !do_expensive_nodes) { _igvn.optimize(); // Cleanup NeverBranches -@@ -2892,9 +2906,7 @@ void PhaseIdealLoop::build_and_optimize(LoopOptsMode mode) { +@@ -2932,9 +2933,7 @@ void PhaseIdealLoop::build_and_optimize(LoopOptsMode mode) { build_loop_late( visited, worklist, nstack ); if (_verify_only) { @@ -2880,19 +2851,19 @@ index 641c829..6aff3d5 100644 assert(C->unique() == unique, "verification mode made Nodes? ? ?"); assert(_igvn._worklist.size() == orig_worklist_size, "shouldn't push anything"); return; -@@ -2938,10 +2950,7 @@ void PhaseIdealLoop::build_and_optimize(LoopOptsMode mode) { +@@ -2977,10 +2976,7 @@ void PhaseIdealLoop::build_and_optimize(LoopOptsMode mode) { + #endif if (skip_loop_opts) { - // restore major progress flag +- // restore major progress flag - for (int i = 0; i < old_progress; i++) { - C->set_major_progress(); - } -- + C->restore_major_progress(old_progress); + // Cleanup any modified bits _igvn.optimize(); - -@@ -2961,6 +2970,16 @@ void PhaseIdealLoop::build_and_optimize(LoopOptsMode mode) { +@@ -3001,6 +2997,16 @@ void PhaseIdealLoop::build_and_optimize(LoopOptsMode mode) { } #endif @@ -2909,7 +2880,7 @@ index 641c829..6aff3d5 100644 if (ReassociateInvariants) { // Reassociate invariants and prep for split_thru_phi for (LoopTreeIterator iter(_ltree_root); !iter.done(); iter.next()) { -@@ -3127,8 +3146,7 @@ void PhaseIdealLoop::verify() const { +@@ -3167,8 +3173,7 @@ void PhaseIdealLoop::verify() const { _ltree_root->verify_tree(loop_verify._ltree_root, NULL); // Reset major-progress. It was cleared by creating a verify version of // PhaseIdealLoop. @@ -2919,7 +2890,7 @@ index 641c829..6aff3d5 100644 } //------------------------------verify_compare--------------------------------- -@@ -4256,7 +4274,6 @@ void PhaseIdealLoop::build_loop_late_post( Node *n ) { +@@ -4296,7 +4301,6 @@ void PhaseIdealLoop::build_loop_late_post( Node *n ) { case Op_LoadS: case Op_LoadP: case Op_LoadBarrierSlowReg: diff --git a/8231441-1-AArch64-Initial-SVE-backend-support.patch b/8231441-1-AArch64-Initial-SVE-backend-support.patch new file mode 100755 index 0000000000000000000000000000000000000000..183a8c91e2659a6adef92648234ba4b1a9402dfd --- /dev/null +++ b/8231441-1-AArch64-Initial-SVE-backend-support.patch @@ -0,0 +1,523 @@ +diff --git a/src/hotspot/cpu/aarch64/assembler_aarch64.hpp b/src/hotspot/cpu/aarch64/assembler_aarch64.hpp +index 0824ca393..228b82660 100644 +--- a/src/hotspot/cpu/aarch64/assembler_aarch64.hpp ++++ b/src/hotspot/cpu/aarch64/assembler_aarch64.hpp +@@ -2670,15 +2670,28 @@ public: + #undef INSN + + void ext(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm, int index) +- { +- starti; +- assert(T == T8B || T == T16B, "invalid arrangement"); +- assert((T == T8B && index <= 0b0111) || (T == T16B && index <= 0b1111), "Invalid index value"); +- f(0, 31), f((int)T & 1, 30), f(0b101110000, 29, 21); +- rf(Vm, 16), f(0, 15), f(index, 14, 11); +- f(0, 10), rf(Vn, 5), rf(Vd, 0); ++{ ++ starti; ++ assert(T == T8B || T == T16B, "invalid arrangement"); ++ assert((T == T8B && index <= 0b0111) || (T == T16B && index <= 0b1111), "Invalid index value"); ++ f(0, 31), f((int)T & 1, 30), f(0b101110000, 29, 21); ++ rf(Vm, 16), f(0, 15), f(index, 14, 11); ++ f(0, 10), rf(Vn, 5), rf(Vd, 0); ++} ++ ++// SVE inc/dec register by element count ++#define INSN(NAME, op) \ ++ void NAME(Register Xdn, SIMD_RegVariant T, unsigned imm4 = 1, int pattern = 0b11111) { \ ++ starti; \ ++ assert(T != Q, "invalid size"); \ ++ f(0b00000100,31, 24), f(T, 23, 22), f(0b11, 21, 20); \ ++ f(imm4 - 1, 19, 16), f(0b11100, 15, 11), f(op, 10), f(pattern, 9, 5), rf(Xdn, 0); \ + } + ++ INSN(sve_inc, 0); ++ INSN(sve_dec, 1); ++#undef INSN ++ + Assembler(CodeBuffer* code) : AbstractAssembler(code) { + } + +diff --git a/src/hotspot/cpu/aarch64/globals_aarch64.hpp b/src/hotspot/cpu/aarch64/globals_aarch64.hpp +index 071845e5b..f26ea2a8b 100644 +--- a/src/hotspot/cpu/aarch64/globals_aarch64.hpp ++++ b/src/hotspot/cpu/aarch64/globals_aarch64.hpp +@@ -112,6 +112,9 @@ define_pd_global(intx, InlineSmallCode, 1000); + "Avoid generating unaligned memory accesses") \ + product(bool, UseLSE, false, \ + "Use LSE instructions") \ ++ product(uint, UseSVE, 0, \ ++ "Highest supported SVE instruction set version") \ ++ range(0, 2) \ + product(bool, UseBlockZeroing, true, \ + "Use DC ZVA for block zeroing") \ + product(intx, BlockZeroingLowLimit, 256, \ +diff --git a/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp b/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp +index aecab30c1..5d10c08a6 100644 +--- a/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp ++++ b/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp +@@ -5879,3 +5879,14 @@ void MacroAssembler::get_thread(Register dst) { + + pop(saved_regs, sp); + } ++ ++void MacroAssembler::verify_sve_vector_length() { ++ Label verify_ok; ++ assert(UseSVE > 0, "should only be used for SVE"); ++ movw(rscratch1, zr); ++ sve_inc(rscratch1, B); ++ subsw(zr, rscratch1, VM_Version::get_initial_sve_vector_length()); ++ br(EQ, verify_ok); ++ stop("Error: SVE vector length has changed since jvm startup"); ++ bind(verify_ok); ++} +diff --git a/src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp b/src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp +index 85fdc0c88..1e7a7401f 100644 +--- a/src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp ++++ b/src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp +@@ -938,6 +938,7 @@ public: + + Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0); + ++ void verify_sve_vector_length(); + + // Debugging + +diff --git a/src/hotspot/cpu/aarch64/sharedRuntime_aarch64.cpp b/src/hotspot/cpu/aarch64/sharedRuntime_aarch64.cpp +index 3d3cc3a1e..dbad48582 100644 +--- a/src/hotspot/cpu/aarch64/sharedRuntime_aarch64.cpp ++++ b/src/hotspot/cpu/aarch64/sharedRuntime_aarch64.cpp +@@ -1829,6 +1829,11 @@ nmethod* SharedRuntime::generate_native_wrapper(MacroAssembler* masm, + __ strw(rscratch1, Address(rthread, JavaThread::thread_state_offset())); + } + ++ if (UseSVE > 0) { ++ // Make sure that jni code does not change SVE vector length. ++ __ verify_sve_vector_length(); ++ } ++ + // check for safepoint operation in progress and/or pending suspend requests + Label safepoint_in_progress, safepoint_in_progress_done; + { +diff --git a/src/hotspot/cpu/aarch64/templateInterpreterGenerator_aarch64.cpp b/src/hotspot/cpu/aarch64/templateInterpreterGenerator_aarch64.cpp +index 03d7a6e2d..42f301531 100644 +--- a/src/hotspot/cpu/aarch64/templateInterpreterGenerator_aarch64.cpp ++++ b/src/hotspot/cpu/aarch64/templateInterpreterGenerator_aarch64.cpp +@@ -1377,6 +1377,11 @@ address TemplateInterpreterGenerator::generate_native_entry(bool synchronized) { + __ push(dtos); + __ push(ltos); + ++ if (UseSVE > 0) { ++ // Make sure that jni code does not change SVE vector length. ++ __ verify_sve_vector_length(); ++ } ++ + // change thread state + __ mov(rscratch1, _thread_in_native_trans); + __ lea(rscratch2, Address(rthread, JavaThread::thread_state_offset())); +diff --git a/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp b/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp +index 0136f24f4..f9696fd08 100644 +--- a/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp ++++ b/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp +@@ -40,6 +40,7 @@ int VM_Version::_model2; + int VM_Version::_variant; + int VM_Version::_revision; + int VM_Version::_stepping; ++int VM_Version::_initial_sve_vector_length; + + int VM_Version::_zva_length; + int VM_Version::_dcache_line_size; +@@ -177,6 +178,8 @@ void VM_Version::initialize() { + if (_features & CPU_SHA1) strcat(buf, ", sha1"); + if (_features & CPU_SHA2) strcat(buf, ", sha256"); + if (_features & CPU_LSE) strcat(buf, ", lse"); ++ if (_features & CPU_SVE) strcat(buf, ", sve"); ++ if (_features & CPU_SVE2) strcat(buf, ", sve2"); + + _features_string = os::strdup(buf); + +@@ -312,6 +315,18 @@ void VM_Version::initialize() { + FLAG_SET_DEFAULT(UseBlockZeroing, false); + } + ++ if (_features & CPU_SVE) { ++ if (FLAG_IS_DEFAULT(UseSVE)) { ++ FLAG_SET_DEFAULT(UseSVE, (_features & CPU_SVE2) ? 2 : 1); ++ } ++ if (UseSVE > 0) { ++ _initial_sve_vector_length = get_current_sve_vector_length(); ++ } ++ } else if (UseSVE > 0) { ++ warning("UseSVE specified, but not supported on current CPU. Disabling SVE."); ++ FLAG_SET_DEFAULT(UseSVE, 0); ++ } ++ + // This machine allows unaligned memory accesses + if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) { + FLAG_SET_DEFAULT(UseUnalignedAccesses, true); +@@ -345,6 +360,50 @@ void VM_Version::initialize() { + UseMontgomerySquareIntrinsic = true; + } + ++ if (UseSVE > 0) { ++ if (FLAG_IS_DEFAULT(MaxVectorSize)) { ++ MaxVectorSize = _initial_sve_vector_length; ++ } else if (MaxVectorSize < 16) { ++ warning("SVE does not support vector length less than 16 bytes. Disabling SVE."); ++ UseSVE = 0; ++ } else if ((MaxVectorSize % 16) == 0 && is_power_of_2(MaxVectorSize)) { ++ int new_vl = set_and_get_current_sve_vector_length(MaxVectorSize); ++ _initial_sve_vector_length = new_vl; ++ // If MaxVectorSize is larger than system largest supported SVE vector length, above prctl() ++ // call will set task vector length to the system largest supported value. So, we also update ++ // MaxVectorSize to that largest supported value. ++ if (new_vl < 0) { ++ vm_exit_during_initialization( ++ err_msg("Current system does not support SVE vector length for MaxVectorSize: %d", ++ (int)MaxVectorSize)); ++ } else if (new_vl != MaxVectorSize) { ++ warning("Current system only supports max SVE vector length %d. Set MaxVectorSize to %d", ++ new_vl, new_vl); ++ } ++ MaxVectorSize = new_vl; ++ } else { ++ vm_exit_during_initialization(err_msg("Unsupported MaxVectorSize: %d", (int)MaxVectorSize)); ++ } ++ } ++ ++ if (UseSVE == 0) { // NEON ++ int min_vector_size = 8; ++ int max_vector_size = 16; ++ if (!FLAG_IS_DEFAULT(MaxVectorSize)) { ++ if (!is_power_of_2(MaxVectorSize)) { ++ vm_exit_during_initialization(err_msg("Unsupported MaxVectorSize: %d", (int)MaxVectorSize)); ++ } else if (MaxVectorSize < min_vector_size) { ++ warning("MaxVectorSize must be at least %i on this platform", min_vector_size); ++ FLAG_SET_DEFAULT(MaxVectorSize, min_vector_size); ++ } else if (MaxVectorSize > max_vector_size) { ++ warning("MaxVectorSize must be at most %i on this platform", max_vector_size); ++ FLAG_SET_DEFAULT(MaxVectorSize, max_vector_size); ++ } ++ } else { ++ FLAG_SET_DEFAULT(MaxVectorSize, 16); ++ } ++ } ++ + if (FLAG_IS_DEFAULT(OptoScheduling)) { + OptoScheduling = true; + } +diff --git a/src/hotspot/os_cpu/linux_aarch64/vm_version_linux_aarch64.cpp b/src/hotspot/os_cpu/linux_aarch64/vm_version_linux_aarch64.cpp +index 5d943ff38..2763c1c6a 100644 +--- a/src/hotspot/os_cpu/linux_aarch64/vm_version_linux_aarch64.cpp ++++ b/src/hotspot/os_cpu/linux_aarch64/vm_version_linux_aarch64.cpp +@@ -55,9 +55,35 @@ + #define HWCAP_ATOMICS (1<<8) + #endif + ++#ifndef HWCAP_SVE ++#define HWCAP_SVE (1 << 22) ++#endif ++ ++#ifndef HWCAP2_SVE2 ++#define HWCAP2_SVE2 (1 << 1) ++#endif ++ ++#ifndef PR_SVE_GET_VL ++// For old toolchains which do not have SVE related macros defined. ++#define PR_SVE_SET_VL 50 ++#define PR_SVE_GET_VL 51 ++#endif ++ ++int VM_Version::get_current_sve_vector_length() { ++ assert(_features & CPU_SVE, "should not call this"); ++ return prctl(PR_SVE_GET_VL); ++} ++ ++int VM_Version::set_and_get_current_sve_vector_length(int length) { ++ assert(_features & CPU_SVE, "should not call this"); ++ int new_length = prctl(PR_SVE_SET_VL, length); ++ return new_length; ++} ++ + void VM_Version::get_os_cpu_info() { + + uint64_t auxv = getauxval(AT_HWCAP); ++ unsigned long auxv2 = getauxval(AT_HWCAP2); + + STATIC_ASSERT(CPU_FP == HWCAP_FP); + STATIC_ASSERT(CPU_ASIMD == HWCAP_ASIMD); +@@ -68,6 +94,8 @@ void VM_Version::get_os_cpu_info() { + STATIC_ASSERT(CPU_SHA2 == HWCAP_SHA2); + STATIC_ASSERT(CPU_CRC32 == HWCAP_CRC32); + STATIC_ASSERT(CPU_LSE == HWCAP_ATOMICS); ++ STATIC_ASSERT(CPU_SVE == HWCAP_SVE); ++ + _features = auxv & ( + HWCAP_FP | + HWCAP_ASIMD | +@@ -77,7 +105,10 @@ void VM_Version::get_os_cpu_info() { + HWCAP_SHA1 | + HWCAP_SHA2 | + HWCAP_CRC32 | +- HWCAP_ATOMICS); ++ HWCAP_ATOMICS | ++ HWCAP_SVE); ++ ++ if (auxv2 & HWCAP2_SVE2) _features |= CPU_SVE2; + + uint64_t ctr_el0; + uint64_t dczid_el0; +diff --git a/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp b/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp +index 643e3d564..82e615241 100644 +--- a/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp ++++ b/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp +@@ -40,6 +40,7 @@ protected: + static int _variant; + static int _revision; + static int _stepping; ++ static int _initial_sve_vector_length; + + static int _zva_length; + static int _dcache_line_size; +@@ -48,6 +49,13 @@ protected: + // Read additional info using OS-specific interfaces + static void get_os_cpu_info(); + ++ ++ // Sets the SVE length and returns a new actual value or negative on error. ++ // If the len is larger than the system largest supported SVE vector length, ++ // the function sets the largest supported value. ++ static int set_and_get_current_sve_vector_length(int len); ++ static int get_current_sve_vector_length(); ++ + public: + // Initialization + static void initialize(); +@@ -91,6 +99,8 @@ public: + CPU_SHA2 = (1<<6), + CPU_CRC32 = (1<<7), + CPU_LSE = (1<<8), ++ CPU_SVE = (1<<22), ++ CPU_SVE2 = (1<<28), + // flags above must follow Linux HWCAP + CPU_STXR_PREFETCH= (1 << 29), + CPU_A53MAC = (1 << 30), +@@ -102,6 +112,7 @@ public: + static int cpu_model2() { return _model2; } + static int cpu_variant() { return _variant; } + static int cpu_revision() { return _revision; } ++ static int get_initial_sve_vector_length() { return _initial_sve_vector_length; }; + + static bool is_zva_enabled() { return 0 <= _zva_length; } + static int zva_length() { +diff --git a/test/hotspot/jtreg/compiler/c2/aarch64/TestSVEWithJNI.java b/test/hotspot/jtreg/compiler/c2/aarch64/TestSVEWithJNI.java +new file mode 100644 +index 000000000..dc15ca800 +--- /dev/null ++++ b/test/hotspot/jtreg/compiler/c2/aarch64/TestSVEWithJNI.java +@@ -0,0 +1,128 @@ ++/* ++* Copyright (c) 2020, Oracle and/or its affiliates. All rights reserved. ++* Copyright (c) 2020, Arm Limited. All rights reserved. ++* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++* ++* This code is free software; you can redistribute it and/or modify it ++* under the terms of the GNU General Public License version 2 only, as ++* published by the Free Software Foundation. ++* ++* This code is distributed in the hope that it will be useful, but WITHOUT ++* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++* version 2 for more details (a copy is included in the LICENSE file that ++* accompanied this code). ++* ++* You should have received a copy of the GNU General Public License version ++* 2 along with this work; if not, write to the Free Software Foundation, ++* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++* ++* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++* or visit www.oracle.com if you need additional information or have any ++* questions. ++* ++*/ ++ ++/** ++ * @test ++ * ++ * @requires os.arch == "aarch64" & vm.compiler2.enabled ++ * @summary Verify VM SVE checking behavior ++ * @library /test/lib ++ * @run main/othervm/native compiler.c2.aarch64.TestSVEWithJNI ++ * ++ */ ++ ++package compiler.c2.aarch64; ++ ++import java.util.ArrayList; ++import java.util.Collections; ++import java.util.List; ++import jdk.test.lib.process.ProcessTools; ++import jdk.test.lib.process.OutputAnalyzer; ++ ++public class TestSVEWithJNI { ++ static { ++ System.loadLibrary("TestSVEWithJNI"); ++ } ++ ++ static final int EXIT_CODE = 99; ++ // Returns a nonnegative on success, or a negative value on error. ++ public static native int setVectorLength(int arg); ++ // Returns a nonnegative value on success, or a negative value on error. ++ public static native int getVectorLength(); ++ ++ public static final String MSG = "Current Vector Size: "; ++ public static void testNormal() { ++ int vlen = getVectorLength(); ++ System.out.println(MSG + vlen); ++ // Should be fine if no vector length changed. ++ if (setVectorLength(vlen) < 0) { ++ throw new Error("Error in setting vector length."); ++ } ++ } ++ ++ public static void testAbort() { ++ int vlen = getVectorLength(); ++ if (vlen <= 16) { ++ throw new Error("Error: unsupported vector length."); ++ } ++ if (setVectorLength(16) < 0) { ++ throw new Error("Error: setting vector length failed."); ++ } ++ } ++ ++ public static ProcessBuilder createProcessBuilder(String [] args, String mode) { ++ List vmopts = new ArrayList<>(); ++ String testjdkPath = System.getProperty("test.jdk"); ++ Collections.addAll(vmopts, "-Dtest.jdk=" + testjdkPath); ++ Collections.addAll(vmopts, args); ++ Collections.addAll(vmopts, TestSVEWithJNI.class.getName(), mode); ++ return ProcessTools.createJavaProcessBuilder(vmopts.toArray(new String[vmopts.size()])); ++ } ++ ++ public static void main(String [] args) throws Exception { ++ if (args.length == 0) { ++ int vlen = getVectorLength(); ++ if (vlen < 0) { ++ return; ++ } ++ String [][] testOpts = { ++ {"-Xint", "-XX:UseSVE=1"}, ++ {"-Xcomp", "-XX:UseSVE=1"}, ++ }; ++ ProcessBuilder pb; ++ OutputAnalyzer output; ++ for (String [] opts : testOpts) { ++ pb = createProcessBuilder(opts, "normal"); ++ output = new OutputAnalyzer(pb.start()); ++ output.shouldHaveExitValue(EXIT_CODE); ++ ++ pb = createProcessBuilder(opts, "abort"); ++ output = new OutputAnalyzer(pb.start()); ++ output.shouldNotHaveExitValue(EXIT_CODE); ++ output.shouldMatch("(error|Error|ERROR)"); ++ } ++ ++ // Verify MaxVectorSize ++ ++ // Any SVE architecture should support 128-bit vector size. ++ pb = createProcessBuilder(new String []{"-XX:UseSVE=1", "-XX:MaxVectorSize=16"}, "normal"); ++ output = new OutputAnalyzer(pb.start()); ++ output.shouldHaveExitValue(EXIT_CODE); ++ output.shouldContain(MSG + 16); ++ ++ // An unsupported large vector size value. ++ pb = createProcessBuilder(new String []{"-XX:UseSVE=1", "-XX:MaxVectorSize=512"}, "normal"); ++ output = new OutputAnalyzer(pb.start()); ++ output.shouldHaveExitValue(EXIT_CODE); ++ output.shouldContain("warning"); ++ } else if (args[0].equals("normal")) { ++ testNormal(); ++ System.exit(EXIT_CODE); ++ } else if (args[0].equals("abort")) { ++ testAbort(); ++ System.exit(EXIT_CODE); ++ } ++ } ++} +diff --git a/test/hotspot/jtreg/compiler/c2/aarch64/libTestSVEWithJNI.c b/test/hotspot/jtreg/compiler/c2/aarch64/libTestSVEWithJNI.c +new file mode 100644 +index 000000000..0cb3ab0b5 +--- /dev/null ++++ b/test/hotspot/jtreg/compiler/c2/aarch64/libTestSVEWithJNI.c +@@ -0,0 +1,68 @@ ++/* ++* Copyright (c) 2020, Oracle and/or its affiliates. All rights reserved. ++* Copyright (c) 2020, Arm Limited. All rights reserved. ++* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++* ++* This code is free software; you can redistribute it and/or modify it ++* under the terms of the GNU General Public License version 2 only, as ++* published by the Free Software Foundation. ++* ++* This code is distributed in the hope that it will be useful, but WITHOUT ++* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++* version 2 for more details (a copy is included in the LICENSE file that ++* accompanied this code). ++* ++* You should have received a copy of the GNU General Public License version ++* 2 along with this work; if not, write to the Free Software Foundation, ++* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++* ++* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++* or visit www.oracle.com if you need additional information or have any ++* questions. ++* ++*/ ++ ++#ifdef __aarch64__ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifndef PR_SVE_GET_VL ++// For old toolchains which do not have SVE related macros defined. ++#define PR_SVE_SET_VL 50 ++#define PR_SVE_GET_VL 51 ++#endif ++ ++int get_current_thread_vl() { ++ return prctl(PR_SVE_GET_VL); ++} ++ ++int set_current_thread_vl(unsigned long arg) { ++ return prctl(PR_SVE_SET_VL, arg); ++} ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++JNIEXPORT jint JNICALL Java_compiler_c2_aarch64_TestSVEWithJNI_setVectorLength ++(JNIEnv * env, jclass clz, jint length) { ++ return set_current_thread_vl(length); ++} ++ ++JNIEXPORT jint JNICALL Java_compiler_c2_aarch64_TestSVEWithJNI_getVectorLength ++(JNIEnv *env, jclass clz) { ++ return get_current_thread_vl(); ++} ++ ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif +-- +2.19.0 + diff --git a/8231441-2-AArch64-Initial-SVE-backend-support.patch b/8231441-2-AArch64-Initial-SVE-backend-support.patch new file mode 100755 index 0000000000000000000000000000000000000000..4dfb8d605b67e77d636814485318181542b16b14 --- /dev/null +++ b/8231441-2-AArch64-Initial-SVE-backend-support.patch @@ -0,0 +1,2201 @@ +diff --git a/src/hotspot/cpu/aarch64/aarch64.ad b/src/hotspot/cpu/aarch64/aarch64.ad +index b64919a62..64985e498 100644 +--- a/src/hotspot/cpu/aarch64/aarch64.ad ++++ b/src/hotspot/cpu/aarch64/aarch64.ad +@@ -69,7 +69,7 @@ register %{ + // + // r0-r7,r10-r26 volatile (caller save) + // r27-r32 system (no save, no allocate) +-// r8-r9 invisible to the allocator (so we can use them as scratch regs) ++// r8-r9 non-allocatable (so we can use them as scratch regs) + // + // as regards Java usage. we don't use any callee save registers + // because this makes it difficult to de-optimise a frame (see comment +@@ -94,6 +94,10 @@ reg_def R6 ( SOC, SOC, Op_RegI, 6, r6->as_VMReg() ); + reg_def R6_H ( SOC, SOC, Op_RegI, 6, r6->as_VMReg()->next() ); + reg_def R7 ( SOC, SOC, Op_RegI, 7, r7->as_VMReg() ); + reg_def R7_H ( SOC, SOC, Op_RegI, 7, r7->as_VMReg()->next() ); ++reg_def R8 ( NS, SOC, Op_RegI, 8, r8->as_VMReg() ); // rscratch1, non-allocatable ++reg_def R8_H ( NS, SOC, Op_RegI, 8, r8->as_VMReg()->next() ); ++reg_def R9 ( NS, SOC, Op_RegI, 9, r9->as_VMReg() ); // rscratch2, non-allocatable ++reg_def R9_H ( NS, SOC, Op_RegI, 9, r9->as_VMReg()->next() ); + reg_def R10 ( SOC, SOC, Op_RegI, 10, r10->as_VMReg() ); + reg_def R10_H ( SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next()); + reg_def R11 ( SOC, SOC, Op_RegI, 11, r11->as_VMReg() ); +@@ -140,7 +144,7 @@ reg_def R31 ( NS, NS, Op_RegI, 31, r31_sp->as_VMReg() ); // sp + reg_def R31_H ( NS, NS, Op_RegI, 31, r31_sp->as_VMReg()->next()); + + // ---------------------------- +-// Float/Double Registers ++// Float/Double/Vector Registers + // ---------------------------- + + // Double Registers +@@ -161,165 +165,317 @@ reg_def R31_H ( NS, NS, Op_RegI, 31, r31_sp->as_VMReg()->next()); + // the platform ABI treats v8-v15 as callee save). float registers + // v16-v31 are SOC as per the platform spec + +- reg_def V0 ( SOC, SOC, Op_RegF, 0, v0->as_VMReg() ); +- reg_def V0_H ( SOC, SOC, Op_RegF, 0, v0->as_VMReg()->next() ); +- reg_def V0_J ( SOC, SOC, Op_RegF, 0, v0->as_VMReg()->next(2) ); +- reg_def V0_K ( SOC, SOC, Op_RegF, 0, v0->as_VMReg()->next(3) ); +- +- reg_def V1 ( SOC, SOC, Op_RegF, 1, v1->as_VMReg() ); +- reg_def V1_H ( SOC, SOC, Op_RegF, 1, v1->as_VMReg()->next() ); +- reg_def V1_J ( SOC, SOC, Op_RegF, 1, v1->as_VMReg()->next(2) ); +- reg_def V1_K ( SOC, SOC, Op_RegF, 1, v1->as_VMReg()->next(3) ); +- +- reg_def V2 ( SOC, SOC, Op_RegF, 2, v2->as_VMReg() ); +- reg_def V2_H ( SOC, SOC, Op_RegF, 2, v2->as_VMReg()->next() ); +- reg_def V2_J ( SOC, SOC, Op_RegF, 2, v2->as_VMReg()->next(2) ); +- reg_def V2_K ( SOC, SOC, Op_RegF, 2, v2->as_VMReg()->next(3) ); +- +- reg_def V3 ( SOC, SOC, Op_RegF, 3, v3->as_VMReg() ); +- reg_def V3_H ( SOC, SOC, Op_RegF, 3, v3->as_VMReg()->next() ); +- reg_def V3_J ( SOC, SOC, Op_RegF, 3, v3->as_VMReg()->next(2) ); +- reg_def V3_K ( SOC, SOC, Op_RegF, 3, v3->as_VMReg()->next(3) ); +- +- reg_def V4 ( SOC, SOC, Op_RegF, 4, v4->as_VMReg() ); +- reg_def V4_H ( SOC, SOC, Op_RegF, 4, v4->as_VMReg()->next() ); +- reg_def V4_J ( SOC, SOC, Op_RegF, 4, v4->as_VMReg()->next(2) ); +- reg_def V4_K ( SOC, SOC, Op_RegF, 4, v4->as_VMReg()->next(3) ); +- +- reg_def V5 ( SOC, SOC, Op_RegF, 5, v5->as_VMReg() ); +- reg_def V5_H ( SOC, SOC, Op_RegF, 5, v5->as_VMReg()->next() ); +- reg_def V5_J ( SOC, SOC, Op_RegF, 5, v5->as_VMReg()->next(2) ); +- reg_def V5_K ( SOC, SOC, Op_RegF, 5, v5->as_VMReg()->next(3) ); +- +- reg_def V6 ( SOC, SOC, Op_RegF, 6, v6->as_VMReg() ); +- reg_def V6_H ( SOC, SOC, Op_RegF, 6, v6->as_VMReg()->next() ); +- reg_def V6_J ( SOC, SOC, Op_RegF, 6, v6->as_VMReg()->next(2) ); +- reg_def V6_K ( SOC, SOC, Op_RegF, 6, v6->as_VMReg()->next(3) ); +- +- reg_def V7 ( SOC, SOC, Op_RegF, 7, v7->as_VMReg() ); +- reg_def V7_H ( SOC, SOC, Op_RegF, 7, v7->as_VMReg()->next() ); +- reg_def V7_J ( SOC, SOC, Op_RegF, 7, v7->as_VMReg()->next(2) ); +- reg_def V7_K ( SOC, SOC, Op_RegF, 7, v7->as_VMReg()->next(3) ); +- +- reg_def V8 ( SOC, SOE, Op_RegF, 8, v8->as_VMReg() ); +- reg_def V8_H ( SOC, SOE, Op_RegF, 8, v8->as_VMReg()->next() ); +- reg_def V8_J ( SOC, SOC, Op_RegF, 8, v8->as_VMReg()->next(2) ); +- reg_def V8_K ( SOC, SOC, Op_RegF, 8, v8->as_VMReg()->next(3) ); +- +- reg_def V9 ( SOC, SOE, Op_RegF, 9, v9->as_VMReg() ); +- reg_def V9_H ( SOC, SOE, Op_RegF, 9, v9->as_VMReg()->next() ); +- reg_def V9_J ( SOC, SOC, Op_RegF, 9, v9->as_VMReg()->next(2) ); +- reg_def V9_K ( SOC, SOC, Op_RegF, 9, v9->as_VMReg()->next(3) ); +- +- reg_def V10 ( SOC, SOE, Op_RegF, 10, v10->as_VMReg() ); +- reg_def V10_H( SOC, SOE, Op_RegF, 10, v10->as_VMReg()->next() ); +- reg_def V10_J( SOC, SOC, Op_RegF, 10, v10->as_VMReg()->next(2)); +- reg_def V10_K( SOC, SOC, Op_RegF, 10, v10->as_VMReg()->next(3)); +- +- reg_def V11 ( SOC, SOE, Op_RegF, 11, v11->as_VMReg() ); +- reg_def V11_H( SOC, SOE, Op_RegF, 11, v11->as_VMReg()->next() ); +- reg_def V11_J( SOC, SOC, Op_RegF, 11, v11->as_VMReg()->next(2)); +- reg_def V11_K( SOC, SOC, Op_RegF, 11, v11->as_VMReg()->next(3)); +- +- reg_def V12 ( SOC, SOE, Op_RegF, 12, v12->as_VMReg() ); +- reg_def V12_H( SOC, SOE, Op_RegF, 12, v12->as_VMReg()->next() ); +- reg_def V12_J( SOC, SOC, Op_RegF, 12, v12->as_VMReg()->next(2)); +- reg_def V12_K( SOC, SOC, Op_RegF, 12, v12->as_VMReg()->next(3)); +- +- reg_def V13 ( SOC, SOE, Op_RegF, 13, v13->as_VMReg() ); +- reg_def V13_H( SOC, SOE, Op_RegF, 13, v13->as_VMReg()->next() ); +- reg_def V13_J( SOC, SOC, Op_RegF, 13, v13->as_VMReg()->next(2)); +- reg_def V13_K( SOC, SOC, Op_RegF, 13, v13->as_VMReg()->next(3)); +- +- reg_def V14 ( SOC, SOE, Op_RegF, 14, v14->as_VMReg() ); +- reg_def V14_H( SOC, SOE, Op_RegF, 14, v14->as_VMReg()->next() ); +- reg_def V14_J( SOC, SOC, Op_RegF, 14, v14->as_VMReg()->next(2)); +- reg_def V14_K( SOC, SOC, Op_RegF, 14, v14->as_VMReg()->next(3)); +- +- reg_def V15 ( SOC, SOE, Op_RegF, 15, v15->as_VMReg() ); +- reg_def V15_H( SOC, SOE, Op_RegF, 15, v15->as_VMReg()->next() ); +- reg_def V15_J( SOC, SOC, Op_RegF, 15, v15->as_VMReg()->next(2)); +- reg_def V15_K( SOC, SOC, Op_RegF, 15, v15->as_VMReg()->next(3)); +- +- reg_def V16 ( SOC, SOC, Op_RegF, 16, v16->as_VMReg() ); +- reg_def V16_H( SOC, SOC, Op_RegF, 16, v16->as_VMReg()->next() ); +- reg_def V16_J( SOC, SOC, Op_RegF, 16, v16->as_VMReg()->next(2)); +- reg_def V16_K( SOC, SOC, Op_RegF, 16, v16->as_VMReg()->next(3)); +- +- reg_def V17 ( SOC, SOC, Op_RegF, 17, v17->as_VMReg() ); +- reg_def V17_H( SOC, SOC, Op_RegF, 17, v17->as_VMReg()->next() ); +- reg_def V17_J( SOC, SOC, Op_RegF, 17, v17->as_VMReg()->next(2)); +- reg_def V17_K( SOC, SOC, Op_RegF, 17, v17->as_VMReg()->next(3)); +- +- reg_def V18 ( SOC, SOC, Op_RegF, 18, v18->as_VMReg() ); +- reg_def V18_H( SOC, SOC, Op_RegF, 18, v18->as_VMReg()->next() ); +- reg_def V18_J( SOC, SOC, Op_RegF, 18, v18->as_VMReg()->next(2)); +- reg_def V18_K( SOC, SOC, Op_RegF, 18, v18->as_VMReg()->next(3)); +- +- reg_def V19 ( SOC, SOC, Op_RegF, 19, v19->as_VMReg() ); +- reg_def V19_H( SOC, SOC, Op_RegF, 19, v19->as_VMReg()->next() ); +- reg_def V19_J( SOC, SOC, Op_RegF, 19, v19->as_VMReg()->next(2)); +- reg_def V19_K( SOC, SOC, Op_RegF, 19, v19->as_VMReg()->next(3)); +- +- reg_def V20 ( SOC, SOC, Op_RegF, 20, v20->as_VMReg() ); +- reg_def V20_H( SOC, SOC, Op_RegF, 20, v20->as_VMReg()->next() ); +- reg_def V20_J( SOC, SOC, Op_RegF, 20, v20->as_VMReg()->next(2)); +- reg_def V20_K( SOC, SOC, Op_RegF, 20, v20->as_VMReg()->next(3)); +- +- reg_def V21 ( SOC, SOC, Op_RegF, 21, v21->as_VMReg() ); +- reg_def V21_H( SOC, SOC, Op_RegF, 21, v21->as_VMReg()->next() ); +- reg_def V21_J( SOC, SOC, Op_RegF, 21, v21->as_VMReg()->next(2)); +- reg_def V21_K( SOC, SOC, Op_RegF, 21, v21->as_VMReg()->next(3)); +- +- reg_def V22 ( SOC, SOC, Op_RegF, 22, v22->as_VMReg() ); +- reg_def V22_H( SOC, SOC, Op_RegF, 22, v22->as_VMReg()->next() ); +- reg_def V22_J( SOC, SOC, Op_RegF, 22, v22->as_VMReg()->next(2)); +- reg_def V22_K( SOC, SOC, Op_RegF, 22, v22->as_VMReg()->next(3)); +- +- reg_def V23 ( SOC, SOC, Op_RegF, 23, v23->as_VMReg() ); +- reg_def V23_H( SOC, SOC, Op_RegF, 23, v23->as_VMReg()->next() ); +- reg_def V23_J( SOC, SOC, Op_RegF, 23, v23->as_VMReg()->next(2)); +- reg_def V23_K( SOC, SOC, Op_RegF, 23, v23->as_VMReg()->next(3)); +- +- reg_def V24 ( SOC, SOC, Op_RegF, 24, v24->as_VMReg() ); +- reg_def V24_H( SOC, SOC, Op_RegF, 24, v24->as_VMReg()->next() ); +- reg_def V24_J( SOC, SOC, Op_RegF, 24, v24->as_VMReg()->next(2)); +- reg_def V24_K( SOC, SOC, Op_RegF, 24, v24->as_VMReg()->next(3)); +- +- reg_def V25 ( SOC, SOC, Op_RegF, 25, v25->as_VMReg() ); +- reg_def V25_H( SOC, SOC, Op_RegF, 25, v25->as_VMReg()->next() ); +- reg_def V25_J( SOC, SOC, Op_RegF, 25, v25->as_VMReg()->next(2)); +- reg_def V25_K( SOC, SOC, Op_RegF, 25, v25->as_VMReg()->next(3)); +- +- reg_def V26 ( SOC, SOC, Op_RegF, 26, v26->as_VMReg() ); +- reg_def V26_H( SOC, SOC, Op_RegF, 26, v26->as_VMReg()->next() ); +- reg_def V26_J( SOC, SOC, Op_RegF, 26, v26->as_VMReg()->next(2)); +- reg_def V26_K( SOC, SOC, Op_RegF, 26, v26->as_VMReg()->next(3)); +- +- reg_def V27 ( SOC, SOC, Op_RegF, 27, v27->as_VMReg() ); +- reg_def V27_H( SOC, SOC, Op_RegF, 27, v27->as_VMReg()->next() ); +- reg_def V27_J( SOC, SOC, Op_RegF, 27, v27->as_VMReg()->next(2)); +- reg_def V27_K( SOC, SOC, Op_RegF, 27, v27->as_VMReg()->next(3)); +- +- reg_def V28 ( SOC, SOC, Op_RegF, 28, v28->as_VMReg() ); +- reg_def V28_H( SOC, SOC, Op_RegF, 28, v28->as_VMReg()->next() ); +- reg_def V28_J( SOC, SOC, Op_RegF, 28, v28->as_VMReg()->next(2)); +- reg_def V28_K( SOC, SOC, Op_RegF, 28, v28->as_VMReg()->next(3)); +- +- reg_def V29 ( SOC, SOC, Op_RegF, 29, v29->as_VMReg() ); +- reg_def V29_H( SOC, SOC, Op_RegF, 29, v29->as_VMReg()->next() ); +- reg_def V29_J( SOC, SOC, Op_RegF, 29, v29->as_VMReg()->next(2)); +- reg_def V29_K( SOC, SOC, Op_RegF, 29, v29->as_VMReg()->next(3)); +- +- reg_def V30 ( SOC, SOC, Op_RegF, 30, v30->as_VMReg() ); +- reg_def V30_H( SOC, SOC, Op_RegF, 30, v30->as_VMReg()->next() ); +- reg_def V30_J( SOC, SOC, Op_RegF, 30, v30->as_VMReg()->next(2)); +- reg_def V30_K( SOC, SOC, Op_RegF, 30, v30->as_VMReg()->next(3)); +- +- reg_def V31 ( SOC, SOC, Op_RegF, 31, v31->as_VMReg() ); +- reg_def V31_H( SOC, SOC, Op_RegF, 31, v31->as_VMReg()->next() ); +- reg_def V31_J( SOC, SOC, Op_RegF, 31, v31->as_VMReg()->next(2)); +- reg_def V31_K( SOC, SOC, Op_RegF, 31, v31->as_VMReg()->next(3)); ++// For SVE vector registers, we simply extend vector register size to 8 ++// 'logical' slots. This is nominally 256 bits but it actually covers ++// all possible 'physical' SVE vector register lengths from 128 ~ 2048 ++// bits. The 'physical' SVE vector register length is detected during ++// startup, so the register allocator is able to identify the correct ++// number of bytes needed for an SVE spill/unspill. ++// Note that a vector register with 4 slots denotes a 128-bit NEON ++// register allowing it to be distinguished from the corresponding SVE ++// vector register when the SVE vector length is 128 bits. ++ ++reg_def V0 ( SOC, SOC, Op_RegF, 0, v0->as_VMReg() ); ++reg_def V0_H ( SOC, SOC, Op_RegF, 0, v0->as_VMReg()->next() ); ++reg_def V0_J ( SOC, SOC, Op_RegF, 0, v0->as_VMReg()->next(2) ); ++reg_def V0_K ( SOC, SOC, Op_RegF, 0, v0->as_VMReg()->next(3) ); ++reg_def V0_L ( SOC, SOC, Op_RegF, 0, v0->as_VMReg()->next(4) ); ++reg_def V0_M ( SOC, SOC, Op_RegF, 0, v0->as_VMReg()->next(5) ); ++reg_def V0_N ( SOC, SOC, Op_RegF, 0, v0->as_VMReg()->next(6) ); ++reg_def V0_O ( SOC, SOC, Op_RegF, 0, v0->as_VMReg()->next(7) ); ++ ++reg_def V1 ( SOC, SOC, Op_RegF, 1, v1->as_VMReg() ); ++reg_def V1_H ( SOC, SOC, Op_RegF, 1, v1->as_VMReg()->next() ); ++reg_def V1_J ( SOC, SOC, Op_RegF, 1, v1->as_VMReg()->next(2) ); ++reg_def V1_K ( SOC, SOC, Op_RegF, 1, v1->as_VMReg()->next(3) ); ++reg_def V1_L ( SOC, SOC, Op_RegF, 1, v1->as_VMReg()->next(4) ); ++reg_def V1_M ( SOC, SOC, Op_RegF, 1, v1->as_VMReg()->next(5) ); ++reg_def V1_N ( SOC, SOC, Op_RegF, 1, v1->as_VMReg()->next(6) ); ++reg_def V1_O ( SOC, SOC, Op_RegF, 1, v1->as_VMReg()->next(7) ); ++ ++reg_def V2 ( SOC, SOC, Op_RegF, 2, v2->as_VMReg() ); ++reg_def V2_H ( SOC, SOC, Op_RegF, 2, v2->as_VMReg()->next() ); ++reg_def V2_J ( SOC, SOC, Op_RegF, 2, v2->as_VMReg()->next(2) ); ++reg_def V2_K ( SOC, SOC, Op_RegF, 2, v2->as_VMReg()->next(3) ); ++reg_def V2_L ( SOC, SOC, Op_RegF, 2, v2->as_VMReg()->next(4) ); ++reg_def V2_M ( SOC, SOC, Op_RegF, 2, v2->as_VMReg()->next(5) ); ++reg_def V2_N ( SOC, SOC, Op_RegF, 2, v2->as_VMReg()->next(6) ); ++reg_def V2_O ( SOC, SOC, Op_RegF, 2, v2->as_VMReg()->next(7) ); ++ ++reg_def V3 ( SOC, SOC, Op_RegF, 3, v3->as_VMReg() ); ++reg_def V3_H ( SOC, SOC, Op_RegF, 3, v3->as_VMReg()->next() ); ++reg_def V3_J ( SOC, SOC, Op_RegF, 3, v3->as_VMReg()->next(2) ); ++reg_def V3_K ( SOC, SOC, Op_RegF, 3, v3->as_VMReg()->next(3) ); ++reg_def V3_L ( SOC, SOC, Op_RegF, 3, v3->as_VMReg()->next(4) ); ++reg_def V3_M ( SOC, SOC, Op_RegF, 3, v3->as_VMReg()->next(5) ); ++reg_def V3_N ( SOC, SOC, Op_RegF, 3, v3->as_VMReg()->next(6) ); ++reg_def V3_O ( SOC, SOC, Op_RegF, 3, v3->as_VMReg()->next(7) ); ++ ++reg_def V4 ( SOC, SOC, Op_RegF, 4, v4->as_VMReg() ); ++reg_def V4_H ( SOC, SOC, Op_RegF, 4, v4->as_VMReg()->next() ); ++reg_def V4_J ( SOC, SOC, Op_RegF, 4, v4->as_VMReg()->next(2) ); ++reg_def V4_K ( SOC, SOC, Op_RegF, 4, v4->as_VMReg()->next(3) ); ++reg_def V4_L ( SOC, SOC, Op_RegF, 4, v4->as_VMReg()->next(4) ); ++reg_def V4_M ( SOC, SOC, Op_RegF, 4, v4->as_VMReg()->next(5) ); ++reg_def V4_N ( SOC, SOC, Op_RegF, 4, v4->as_VMReg()->next(6) ); ++reg_def V4_O ( SOC, SOC, Op_RegF, 4, v4->as_VMReg()->next(7) ); ++ ++reg_def V5 ( SOC, SOC, Op_RegF, 5, v5->as_VMReg() ); ++reg_def V5_H ( SOC, SOC, Op_RegF, 5, v5->as_VMReg()->next() ); ++reg_def V5_J ( SOC, SOC, Op_RegF, 5, v5->as_VMReg()->next(2) ); ++reg_def V5_K ( SOC, SOC, Op_RegF, 5, v5->as_VMReg()->next(3) ); ++reg_def V5_L ( SOC, SOC, Op_RegF, 5, v5->as_VMReg()->next(4) ); ++reg_def V5_M ( SOC, SOC, Op_RegF, 5, v5->as_VMReg()->next(5) ); ++reg_def V5_N ( SOC, SOC, Op_RegF, 5, v5->as_VMReg()->next(6) ); ++reg_def V5_O ( SOC, SOC, Op_RegF, 5, v5->as_VMReg()->next(7) ); ++ ++reg_def V6 ( SOC, SOC, Op_RegF, 6, v6->as_VMReg() ); ++reg_def V6_H ( SOC, SOC, Op_RegF, 6, v6->as_VMReg()->next() ); ++reg_def V6_J ( SOC, SOC, Op_RegF, 6, v6->as_VMReg()->next(2) ); ++reg_def V6_K ( SOC, SOC, Op_RegF, 6, v6->as_VMReg()->next(3) ); ++reg_def V6_L ( SOC, SOC, Op_RegF, 6, v6->as_VMReg()->next(4) ); ++reg_def V6_M ( SOC, SOC, Op_RegF, 6, v6->as_VMReg()->next(5) ); ++reg_def V6_N ( SOC, SOC, Op_RegF, 6, v6->as_VMReg()->next(6) ); ++reg_def V6_O ( SOC, SOC, Op_RegF, 6, v6->as_VMReg()->next(7) ); ++ ++reg_def V7 ( SOC, SOC, Op_RegF, 7, v7->as_VMReg() ); ++reg_def V7_H ( SOC, SOC, Op_RegF, 7, v7->as_VMReg()->next() ); ++reg_def V7_J ( SOC, SOC, Op_RegF, 7, v7->as_VMReg()->next(2) ); ++reg_def V7_K ( SOC, SOC, Op_RegF, 7, v7->as_VMReg()->next(3) ); ++reg_def V7_L ( SOC, SOC, Op_RegF, 7, v7->as_VMReg()->next(4) ); ++reg_def V7_M ( SOC, SOC, Op_RegF, 7, v7->as_VMReg()->next(5) ); ++reg_def V7_N ( SOC, SOC, Op_RegF, 7, v7->as_VMReg()->next(6) ); ++reg_def V7_O ( SOC, SOC, Op_RegF, 7, v7->as_VMReg()->next(7) ); ++ ++reg_def V8 ( SOC, SOE, Op_RegF, 8, v8->as_VMReg() ); ++reg_def V8_H ( SOC, SOE, Op_RegF, 8, v8->as_VMReg()->next() ); ++reg_def V8_J ( SOC, SOC, Op_RegF, 8, v8->as_VMReg()->next(2) ); ++reg_def V8_K ( SOC, SOC, Op_RegF, 8, v8->as_VMReg()->next(3) ); ++reg_def V8_L ( SOC, SOC, Op_RegF, 8, v8->as_VMReg()->next(4) ); ++reg_def V8_M ( SOC, SOC, Op_RegF, 8, v8->as_VMReg()->next(5) ); ++reg_def V8_N ( SOC, SOC, Op_RegF, 8, v8->as_VMReg()->next(6) ); ++reg_def V8_O ( SOC, SOC, Op_RegF, 8, v8->as_VMReg()->next(7) ); ++ ++reg_def V9 ( SOC, SOE, Op_RegF, 9, v9->as_VMReg() ); ++reg_def V9_H ( SOC, SOE, Op_RegF, 9, v9->as_VMReg()->next() ); ++reg_def V9_J ( SOC, SOC, Op_RegF, 9, v9->as_VMReg()->next(2) ); ++reg_def V9_K ( SOC, SOC, Op_RegF, 9, v9->as_VMReg()->next(3) ); ++reg_def V9_L ( SOC, SOC, Op_RegF, 9, v9->as_VMReg()->next(4) ); ++reg_def V9_M ( SOC, SOC, Op_RegF, 9, v9->as_VMReg()->next(5) ); ++reg_def V9_N ( SOC, SOC, Op_RegF, 9, v9->as_VMReg()->next(6) ); ++reg_def V9_O ( SOC, SOC, Op_RegF, 9, v9->as_VMReg()->next(7) ); ++ ++reg_def V10 ( SOC, SOE, Op_RegF, 10, v10->as_VMReg() ); ++reg_def V10_H ( SOC, SOE, Op_RegF, 10, v10->as_VMReg()->next() ); ++reg_def V10_J ( SOC, SOC, Op_RegF, 10, v10->as_VMReg()->next(2) ); ++reg_def V10_K ( SOC, SOC, Op_RegF, 10, v10->as_VMReg()->next(3) ); ++reg_def V10_L ( SOC, SOC, Op_RegF, 10, v10->as_VMReg()->next(4) ); ++reg_def V10_M ( SOC, SOC, Op_RegF, 10, v10->as_VMReg()->next(5) ); ++reg_def V10_N ( SOC, SOC, Op_RegF, 10, v10->as_VMReg()->next(6) ); ++reg_def V10_O ( SOC, SOC, Op_RegF, 10, v10->as_VMReg()->next(7) ); ++ ++reg_def V11 ( SOC, SOE, Op_RegF, 11, v11->as_VMReg() ); ++reg_def V11_H ( SOC, SOE, Op_RegF, 11, v11->as_VMReg()->next() ); ++reg_def V11_J ( SOC, SOC, Op_RegF, 11, v11->as_VMReg()->next(2) ); ++reg_def V11_K ( SOC, SOC, Op_RegF, 11, v11->as_VMReg()->next(3) ); ++reg_def V11_L ( SOC, SOC, Op_RegF, 11, v11->as_VMReg()->next(4) ); ++reg_def V11_M ( SOC, SOC, Op_RegF, 11, v11->as_VMReg()->next(5) ); ++reg_def V11_N ( SOC, SOC, Op_RegF, 11, v11->as_VMReg()->next(6) ); ++reg_def V11_O ( SOC, SOC, Op_RegF, 11, v11->as_VMReg()->next(7) ); ++ ++reg_def V12 ( SOC, SOE, Op_RegF, 12, v12->as_VMReg() ); ++reg_def V12_H ( SOC, SOE, Op_RegF, 12, v12->as_VMReg()->next() ); ++reg_def V12_J ( SOC, SOC, Op_RegF, 12, v12->as_VMReg()->next(2) ); ++reg_def V12_K ( SOC, SOC, Op_RegF, 12, v12->as_VMReg()->next(3) ); ++reg_def V12_L ( SOC, SOC, Op_RegF, 12, v12->as_VMReg()->next(4) ); ++reg_def V12_M ( SOC, SOC, Op_RegF, 12, v12->as_VMReg()->next(5) ); ++reg_def V12_N ( SOC, SOC, Op_RegF, 12, v12->as_VMReg()->next(6) ); ++reg_def V12_O ( SOC, SOC, Op_RegF, 12, v12->as_VMReg()->next(7) ); ++ ++reg_def V13 ( SOC, SOE, Op_RegF, 13, v13->as_VMReg() ); ++reg_def V13_H ( SOC, SOE, Op_RegF, 13, v13->as_VMReg()->next() ); ++reg_def V13_J ( SOC, SOC, Op_RegF, 13, v13->as_VMReg()->next(2) ); ++reg_def V13_K ( SOC, SOC, Op_RegF, 13, v13->as_VMReg()->next(3) ); ++reg_def V13_L ( SOC, SOC, Op_RegF, 13, v13->as_VMReg()->next(4) ); ++reg_def V13_M ( SOC, SOC, Op_RegF, 13, v13->as_VMReg()->next(5) ); ++reg_def V13_N ( SOC, SOC, Op_RegF, 13, v13->as_VMReg()->next(6) ); ++reg_def V13_O ( SOC, SOC, Op_RegF, 13, v13->as_VMReg()->next(7) ); ++ ++reg_def V14 ( SOC, SOE, Op_RegF, 14, v14->as_VMReg() ); ++reg_def V14_H ( SOC, SOE, Op_RegF, 14, v14->as_VMReg()->next() ); ++reg_def V14_J ( SOC, SOC, Op_RegF, 14, v14->as_VMReg()->next(2) ); ++reg_def V14_K ( SOC, SOC, Op_RegF, 14, v14->as_VMReg()->next(3) ); ++reg_def V14_L ( SOC, SOC, Op_RegF, 14, v14->as_VMReg()->next(4) ); ++reg_def V14_M ( SOC, SOC, Op_RegF, 14, v14->as_VMReg()->next(5) ); ++reg_def V14_N ( SOC, SOC, Op_RegF, 14, v14->as_VMReg()->next(6) ); ++reg_def V14_O ( SOC, SOC, Op_RegF, 14, v14->as_VMReg()->next(7) ); ++ ++reg_def V15 ( SOC, SOE, Op_RegF, 15, v15->as_VMReg() ); ++reg_def V15_H ( SOC, SOE, Op_RegF, 15, v15->as_VMReg()->next() ); ++reg_def V15_J ( SOC, SOC, Op_RegF, 15, v15->as_VMReg()->next(2) ); ++reg_def V15_K ( SOC, SOC, Op_RegF, 15, v15->as_VMReg()->next(3) ); ++reg_def V15_L ( SOC, SOC, Op_RegF, 15, v15->as_VMReg()->next(4) ); ++reg_def V15_M ( SOC, SOC, Op_RegF, 15, v15->as_VMReg()->next(5) ); ++reg_def V15_N ( SOC, SOC, Op_RegF, 15, v15->as_VMReg()->next(6) ); ++reg_def V15_O ( SOC, SOC, Op_RegF, 15, v15->as_VMReg()->next(7) ); ++ ++reg_def V16 ( SOC, SOC, Op_RegF, 16, v16->as_VMReg() ); ++reg_def V16_H ( SOC, SOC, Op_RegF, 16, v16->as_VMReg()->next() ); ++reg_def V16_J ( SOC, SOC, Op_RegF, 16, v16->as_VMReg()->next(2) ); ++reg_def V16_K ( SOC, SOC, Op_RegF, 16, v16->as_VMReg()->next(3) ); ++reg_def V16_L ( SOC, SOC, Op_RegF, 16, v16->as_VMReg()->next(4) ); ++reg_def V16_M ( SOC, SOC, Op_RegF, 16, v16->as_VMReg()->next(5) ); ++reg_def V16_N ( SOC, SOC, Op_RegF, 16, v16->as_VMReg()->next(6) ); ++reg_def V16_O ( SOC, SOC, Op_RegF, 16, v16->as_VMReg()->next(7) ); ++ ++reg_def V17 ( SOC, SOC, Op_RegF, 17, v17->as_VMReg() ); ++reg_def V17_H ( SOC, SOC, Op_RegF, 17, v17->as_VMReg()->next() ); ++reg_def V17_J ( SOC, SOC, Op_RegF, 17, v17->as_VMReg()->next(2) ); ++reg_def V17_K ( SOC, SOC, Op_RegF, 17, v17->as_VMReg()->next(3) ); ++reg_def V17_L ( SOC, SOC, Op_RegF, 17, v17->as_VMReg()->next(4) ); ++reg_def V17_M ( SOC, SOC, Op_RegF, 17, v17->as_VMReg()->next(5) ); ++reg_def V17_N ( SOC, SOC, Op_RegF, 17, v17->as_VMReg()->next(6) ); ++reg_def V17_O ( SOC, SOC, Op_RegF, 17, v17->as_VMReg()->next(7) ); ++ ++reg_def V18 ( SOC, SOC, Op_RegF, 18, v18->as_VMReg() ); ++reg_def V18_H ( SOC, SOC, Op_RegF, 18, v18->as_VMReg()->next() ); ++reg_def V18_J ( SOC, SOC, Op_RegF, 18, v18->as_VMReg()->next(2) ); ++reg_def V18_K ( SOC, SOC, Op_RegF, 18, v18->as_VMReg()->next(3) ); ++reg_def V18_L ( SOC, SOC, Op_RegF, 18, v18->as_VMReg()->next(4) ); ++reg_def V18_M ( SOC, SOC, Op_RegF, 18, v18->as_VMReg()->next(5) ); ++reg_def V18_N ( SOC, SOC, Op_RegF, 18, v18->as_VMReg()->next(6) ); ++reg_def V18_O ( SOC, SOC, Op_RegF, 18, v18->as_VMReg()->next(7) ); ++ ++reg_def V19 ( SOC, SOC, Op_RegF, 19, v19->as_VMReg() ); ++reg_def V19_H ( SOC, SOC, Op_RegF, 19, v19->as_VMReg()->next() ); ++reg_def V19_J ( SOC, SOC, Op_RegF, 19, v19->as_VMReg()->next(2) ); ++reg_def V19_K ( SOC, SOC, Op_RegF, 19, v19->as_VMReg()->next(3) ); ++reg_def V19_L ( SOC, SOC, Op_RegF, 19, v19->as_VMReg()->next(4) ); ++reg_def V19_M ( SOC, SOC, Op_RegF, 19, v19->as_VMReg()->next(5) ); ++reg_def V19_N ( SOC, SOC, Op_RegF, 19, v19->as_VMReg()->next(6) ); ++reg_def V19_O ( SOC, SOC, Op_RegF, 19, v19->as_VMReg()->next(7) ); ++ ++reg_def V20 ( SOC, SOC, Op_RegF, 20, v20->as_VMReg() ); ++reg_def V20_H ( SOC, SOC, Op_RegF, 20, v20->as_VMReg()->next() ); ++reg_def V20_J ( SOC, SOC, Op_RegF, 20, v20->as_VMReg()->next(2) ); ++reg_def V20_K ( SOC, SOC, Op_RegF, 20, v20->as_VMReg()->next(3) ); ++reg_def V20_L ( SOC, SOC, Op_RegF, 20, v20->as_VMReg()->next(4) ); ++reg_def V20_M ( SOC, SOC, Op_RegF, 20, v20->as_VMReg()->next(5) ); ++reg_def V20_N ( SOC, SOC, Op_RegF, 20, v20->as_VMReg()->next(6) ); ++reg_def V20_O ( SOC, SOC, Op_RegF, 20, v20->as_VMReg()->next(7) ); ++ ++reg_def V21 ( SOC, SOC, Op_RegF, 21, v21->as_VMReg() ); ++reg_def V21_H ( SOC, SOC, Op_RegF, 21, v21->as_VMReg()->next() ); ++reg_def V21_J ( SOC, SOC, Op_RegF, 21, v21->as_VMReg()->next(2) ); ++reg_def V21_K ( SOC, SOC, Op_RegF, 21, v21->as_VMReg()->next(3) ); ++reg_def V21_L ( SOC, SOC, Op_RegF, 21, v21->as_VMReg()->next(4) ); ++reg_def V21_M ( SOC, SOC, Op_RegF, 21, v21->as_VMReg()->next(5) ); ++reg_def V21_N ( SOC, SOC, Op_RegF, 21, v21->as_VMReg()->next(6) ); ++reg_def V21_O ( SOC, SOC, Op_RegF, 21, v21->as_VMReg()->next(7) ); ++ ++reg_def V22 ( SOC, SOC, Op_RegF, 22, v22->as_VMReg() ); ++reg_def V22_H ( SOC, SOC, Op_RegF, 22, v22->as_VMReg()->next() ); ++reg_def V22_J ( SOC, SOC, Op_RegF, 22, v22->as_VMReg()->next(2) ); ++reg_def V22_K ( SOC, SOC, Op_RegF, 22, v22->as_VMReg()->next(3) ); ++reg_def V22_L ( SOC, SOC, Op_RegF, 22, v22->as_VMReg()->next(4) ); ++reg_def V22_M ( SOC, SOC, Op_RegF, 22, v22->as_VMReg()->next(5) ); ++reg_def V22_N ( SOC, SOC, Op_RegF, 22, v22->as_VMReg()->next(6) ); ++reg_def V22_O ( SOC, SOC, Op_RegF, 22, v22->as_VMReg()->next(7) ); ++ ++reg_def V23 ( SOC, SOC, Op_RegF, 23, v23->as_VMReg() ); ++reg_def V23_H ( SOC, SOC, Op_RegF, 23, v23->as_VMReg()->next() ); ++reg_def V23_J ( SOC, SOC, Op_RegF, 23, v23->as_VMReg()->next(2) ); ++reg_def V23_K ( SOC, SOC, Op_RegF, 23, v23->as_VMReg()->next(3) ); ++reg_def V23_L ( SOC, SOC, Op_RegF, 23, v23->as_VMReg()->next(4) ); ++reg_def V23_M ( SOC, SOC, Op_RegF, 23, v23->as_VMReg()->next(5) ); ++reg_def V23_N ( SOC, SOC, Op_RegF, 23, v23->as_VMReg()->next(6) ); ++reg_def V23_O ( SOC, SOC, Op_RegF, 23, v23->as_VMReg()->next(7) ); ++ ++reg_def V24 ( SOC, SOC, Op_RegF, 24, v24->as_VMReg() ); ++reg_def V24_H ( SOC, SOC, Op_RegF, 24, v24->as_VMReg()->next() ); ++reg_def V24_J ( SOC, SOC, Op_RegF, 24, v24->as_VMReg()->next(2) ); ++reg_def V24_K ( SOC, SOC, Op_RegF, 24, v24->as_VMReg()->next(3) ); ++reg_def V24_L ( SOC, SOC, Op_RegF, 24, v24->as_VMReg()->next(4) ); ++reg_def V24_M ( SOC, SOC, Op_RegF, 24, v24->as_VMReg()->next(5) ); ++reg_def V24_N ( SOC, SOC, Op_RegF, 24, v24->as_VMReg()->next(6) ); ++reg_def V24_O ( SOC, SOC, Op_RegF, 24, v24->as_VMReg()->next(7) ); ++ ++reg_def V25 ( SOC, SOC, Op_RegF, 25, v25->as_VMReg() ); ++reg_def V25_H ( SOC, SOC, Op_RegF, 25, v25->as_VMReg()->next() ); ++reg_def V25_J ( SOC, SOC, Op_RegF, 25, v25->as_VMReg()->next(2) ); ++reg_def V25_K ( SOC, SOC, Op_RegF, 25, v25->as_VMReg()->next(3) ); ++reg_def V25_L ( SOC, SOC, Op_RegF, 25, v25->as_VMReg()->next(4) ); ++reg_def V25_M ( SOC, SOC, Op_RegF, 25, v25->as_VMReg()->next(5) ); ++reg_def V25_N ( SOC, SOC, Op_RegF, 25, v25->as_VMReg()->next(6) ); ++reg_def V25_O ( SOC, SOC, Op_RegF, 25, v25->as_VMReg()->next(7) ); ++ ++reg_def V26 ( SOC, SOC, Op_RegF, 26, v26->as_VMReg() ); ++reg_def V26_H ( SOC, SOC, Op_RegF, 26, v26->as_VMReg()->next() ); ++reg_def V26_J ( SOC, SOC, Op_RegF, 26, v26->as_VMReg()->next(2) ); ++reg_def V26_K ( SOC, SOC, Op_RegF, 26, v26->as_VMReg()->next(3) ); ++reg_def V26_L ( SOC, SOC, Op_RegF, 26, v26->as_VMReg()->next(4) ); ++reg_def V26_M ( SOC, SOC, Op_RegF, 26, v26->as_VMReg()->next(5) ); ++reg_def V26_N ( SOC, SOC, Op_RegF, 26, v26->as_VMReg()->next(6) ); ++reg_def V26_O ( SOC, SOC, Op_RegF, 26, v26->as_VMReg()->next(7) ); ++ ++reg_def V27 ( SOC, SOC, Op_RegF, 27, v27->as_VMReg() ); ++reg_def V27_H ( SOC, SOC, Op_RegF, 27, v27->as_VMReg()->next() ); ++reg_def V27_J ( SOC, SOC, Op_RegF, 27, v27->as_VMReg()->next(2) ); ++reg_def V27_K ( SOC, SOC, Op_RegF, 27, v27->as_VMReg()->next(3) ); ++reg_def V27_L ( SOC, SOC, Op_RegF, 27, v27->as_VMReg()->next(4) ); ++reg_def V27_M ( SOC, SOC, Op_RegF, 27, v27->as_VMReg()->next(5) ); ++reg_def V27_N ( SOC, SOC, Op_RegF, 27, v27->as_VMReg()->next(6) ); ++reg_def V27_O ( SOC, SOC, Op_RegF, 27, v27->as_VMReg()->next(7) ); ++ ++reg_def V28 ( SOC, SOC, Op_RegF, 28, v28->as_VMReg() ); ++reg_def V28_H ( SOC, SOC, Op_RegF, 28, v28->as_VMReg()->next() ); ++reg_def V28_J ( SOC, SOC, Op_RegF, 28, v28->as_VMReg()->next(2) ); ++reg_def V28_K ( SOC, SOC, Op_RegF, 28, v28->as_VMReg()->next(3) ); ++reg_def V28_L ( SOC, SOC, Op_RegF, 28, v28->as_VMReg()->next(4) ); ++reg_def V28_M ( SOC, SOC, Op_RegF, 28, v28->as_VMReg()->next(5) ); ++reg_def V28_N ( SOC, SOC, Op_RegF, 28, v28->as_VMReg()->next(6) ); ++reg_def V28_O ( SOC, SOC, Op_RegF, 28, v28->as_VMReg()->next(7) ); ++ ++reg_def V29 ( SOC, SOC, Op_RegF, 29, v29->as_VMReg() ); ++reg_def V29_H ( SOC, SOC, Op_RegF, 29, v29->as_VMReg()->next() ); ++reg_def V29_J ( SOC, SOC, Op_RegF, 29, v29->as_VMReg()->next(2) ); ++reg_def V29_K ( SOC, SOC, Op_RegF, 29, v29->as_VMReg()->next(3) ); ++reg_def V29_L ( SOC, SOC, Op_RegF, 29, v29->as_VMReg()->next(4) ); ++reg_def V29_M ( SOC, SOC, Op_RegF, 29, v29->as_VMReg()->next(5) ); ++reg_def V29_N ( SOC, SOC, Op_RegF, 29, v29->as_VMReg()->next(6) ); ++reg_def V29_O ( SOC, SOC, Op_RegF, 29, v29->as_VMReg()->next(7) ); ++ ++reg_def V30 ( SOC, SOC, Op_RegF, 30, v30->as_VMReg() ); ++reg_def V30_H ( SOC, SOC, Op_RegF, 30, v30->as_VMReg()->next() ); ++reg_def V30_J ( SOC, SOC, Op_RegF, 30, v30->as_VMReg()->next(2) ); ++reg_def V30_K ( SOC, SOC, Op_RegF, 30, v30->as_VMReg()->next(3) ); ++reg_def V30_L ( SOC, SOC, Op_RegF, 30, v30->as_VMReg()->next(4) ); ++reg_def V30_M ( SOC, SOC, Op_RegF, 30, v30->as_VMReg()->next(5) ); ++reg_def V30_N ( SOC, SOC, Op_RegF, 30, v30->as_VMReg()->next(6) ); ++reg_def V30_O ( SOC, SOC, Op_RegF, 30, v30->as_VMReg()->next(7) ); ++ ++reg_def V31 ( SOC, SOC, Op_RegF, 31, v31->as_VMReg() ); ++reg_def V31_H ( SOC, SOC, Op_RegF, 31, v31->as_VMReg()->next() ); ++reg_def V31_J ( SOC, SOC, Op_RegF, 31, v31->as_VMReg()->next(2) ); ++reg_def V31_K ( SOC, SOC, Op_RegF, 31, v31->as_VMReg()->next(3) ); ++reg_def V31_L ( SOC, SOC, Op_RegF, 31, v31->as_VMReg()->next(4) ); ++reg_def V31_M ( SOC, SOC, Op_RegF, 31, v31->as_VMReg()->next(5) ); ++reg_def V31_N ( SOC, SOC, Op_RegF, 31, v31->as_VMReg()->next(6) ); ++reg_def V31_O ( SOC, SOC, Op_RegF, 31, v31->as_VMReg()->next(7) ); ++ ++ ++// ---------------------------- ++// SVE Predicate Registers ++// ---------------------------- ++reg_def P0 (SOC, SOC, Op_RegVMask, 0, p0->as_VMReg()); ++reg_def P1 (SOC, SOC, Op_RegVMask, 1, p1->as_VMReg()); ++reg_def P2 (SOC, SOC, Op_RegVMask, 2, p2->as_VMReg()); ++reg_def P3 (SOC, SOC, Op_RegVMask, 3, p3->as_VMReg()); ++reg_def P4 (SOC, SOC, Op_RegVMask, 4, p4->as_VMReg()); ++reg_def P5 (SOC, SOC, Op_RegVMask, 5, p5->as_VMReg()); ++reg_def P6 (SOC, SOC, Op_RegVMask, 6, p6->as_VMReg()); ++reg_def P7 (SOC, SOC, Op_RegVMask, 7, p7->as_VMReg()); ++ + + // ---------------------------- + // Special Registers +@@ -381,50 +536,64 @@ alloc_class chunk0( + R29, R29_H, // fp + R30, R30_H, // lr + R31, R31_H, // sp ++ R8, R8_H, // rscratch1 ++ R9, R9_H, // rscratch2 + ); + + alloc_class chunk1( + + // no save +- V16, V16_H, V16_J, V16_K, +- V17, V17_H, V17_J, V17_K, +- V18, V18_H, V18_J, V18_K, +- V19, V19_H, V19_J, V19_K, +- V20, V20_H, V20_J, V20_K, +- V21, V21_H, V21_J, V21_K, +- V22, V22_H, V22_J, V22_K, +- V23, V23_H, V23_J, V23_K, +- V24, V24_H, V24_J, V24_K, +- V25, V25_H, V25_J, V25_K, +- V26, V26_H, V26_J, V26_K, +- V27, V27_H, V27_J, V27_K, +- V28, V28_H, V28_J, V28_K, +- V29, V29_H, V29_J, V29_K, +- V30, V30_H, V30_J, V30_K, +- V31, V31_H, V31_J, V31_K, ++ V16, V16_H, V16_J, V16_K, V16_L, V16_M, V16_N, V16_O, ++ V17, V17_H, V17_J, V17_K, V17_L, V17_M, V17_N, V17_O, ++ V18, V18_H, V18_J, V18_K, V18_L, V18_M, V18_N, V18_O, ++ V19, V19_H, V19_J, V19_K, V19_L, V19_M, V19_N, V19_O, ++ V20, V20_H, V20_J, V20_K, V20_L, V20_M, V20_N, V20_O, ++ V21, V21_H, V21_J, V21_K, V21_L, V21_M, V21_N, V21_O, ++ V22, V22_H, V22_J, V22_K, V22_L, V22_M, V22_N, V22_O, ++ V23, V23_H, V23_J, V23_K, V23_L, V23_M, V23_N, V23_O, ++ V24, V24_H, V24_J, V24_K, V24_L, V24_M, V24_N, V24_O, ++ V25, V25_H, V25_J, V25_K, V25_L, V25_M, V25_N, V25_O, ++ V26, V26_H, V26_J, V26_K, V26_L, V26_M, V26_N, V26_O, ++ V27, V27_H, V27_J, V27_K, V27_L, V27_M, V27_N, V27_O, ++ V28, V28_H, V28_J, V28_K, V28_L, V28_M, V28_N, V28_O, ++ V29, V29_H, V29_J, V29_K, V29_L, V29_M, V29_N, V29_O, ++ V30, V30_H, V30_J, V30_K, V30_L, V30_M, V30_N, V30_O, ++ V31, V31_H, V31_J, V31_K, V31_L, V31_M, V31_N, V31_O, + + // arg registers +- V0, V0_H, V0_J, V0_K, +- V1, V1_H, V1_J, V1_K, +- V2, V2_H, V2_J, V2_K, +- V3, V3_H, V3_J, V3_K, +- V4, V4_H, V4_J, V4_K, +- V5, V5_H, V5_J, V5_K, +- V6, V6_H, V6_J, V6_K, +- V7, V7_H, V7_J, V7_K, ++ V0, V0_H, V0_J, V0_K, V0_L, V0_M, V0_N, V0_O, ++ V1, V1_H, V1_J, V1_K, V1_L, V1_M, V1_N, V1_O, ++ V2, V2_H, V2_J, V2_K, V2_L, V2_M, V2_N, V2_O, ++ V3, V3_H, V3_J, V3_K, V3_L, V3_M, V3_N, V3_O, ++ V4, V4_H, V4_J, V4_K, V4_L, V4_M, V4_N, V4_O, ++ V5, V5_H, V5_J, V5_K, V5_L, V5_M, V5_N, V5_O, ++ V6, V6_H, V6_J, V6_K, V6_L, V6_M, V6_N, V6_O, ++ V7, V7_H, V7_J, V7_K, V7_L, V7_M, V7_N, V7_O, + + // non-volatiles +- V8, V8_H, V8_J, V8_K, +- V9, V9_H, V9_J, V9_K, +- V10, V10_H, V10_J, V10_K, +- V11, V11_H, V11_J, V11_K, +- V12, V12_H, V12_J, V12_K, +- V13, V13_H, V13_J, V13_K, +- V14, V14_H, V14_J, V14_K, +- V15, V15_H, V15_J, V15_K, ++ V8, V8_H, V8_J, V8_K, V8_L, V8_M, V8_N, V8_O, ++ V9, V9_H, V9_J, V9_K, V9_L, V9_M, V9_N, V9_O, ++ V10, V10_H, V10_J, V10_K, V10_L, V10_M, V10_N, V10_O, ++ V11, V11_H, V11_J, V11_K, V11_L, V11_M, V11_N, V11_O, ++ V12, V12_H, V12_J, V12_K, V12_L, V12_M, V12_N, V12_O, ++ V13, V13_H, V13_J, V13_K, V13_L, V13_M, V13_N, V13_O, ++ V14, V14_H, V14_J, V14_K, V14_L, V14_M, V14_N, V14_O, ++ V15, V15_H, V15_J, V15_K, V15_L, V15_M, V15_N, V15_O, ++); ++ ++alloc_class chunk2 ( ++ P0, ++ P1, ++ P2, ++ P3, ++ P4, ++ P5, ++ P6, ++ P7, ++ // Only use P0~P7 here for performance + ); + +-alloc_class chunk2(RFLAGS); ++alloc_class chunk3(RFLAGS); + + //----------Architecture Description Register Classes-------------------------- + // Several register classes are automatically defined based upon information in +@@ -865,6 +1034,42 @@ reg_class double_reg( + V31, V31_H + ); + ++// Class for all SVE vector registers. ++reg_class vectora_reg ( ++ V0, V0_H, V0_J, V0_K, V0_L, V0_M, V0_N, V0_O, ++ V1, V1_H, V1_J, V1_K, V1_L, V1_M, V1_N, V1_O, ++ V2, V2_H, V2_J, V2_K, V2_L, V2_M, V2_N, V2_O, ++ V3, V3_H, V3_J, V3_K, V3_L, V3_M, V3_N, V3_O, ++ V4, V4_H, V4_J, V4_K, V4_L, V4_M, V4_N, V4_O, ++ V5, V5_H, V5_J, V5_K, V5_L, V5_M, V5_N, V5_O, ++ V6, V6_H, V6_J, V6_K, V6_L, V6_M, V6_N, V6_O, ++ V7, V7_H, V7_J, V7_K, V7_L, V7_M, V7_N, V7_O, ++ V8, V8_H, V8_J, V8_K, V8_L, V8_M, V8_N, V8_O, ++ V9, V9_H, V9_J, V9_K, V9_L, V9_M, V9_N, V9_O, ++ V10, V10_H, V10_J, V10_K, V10_L, V10_M, V10_N, V10_O, ++ V11, V11_H, V11_J, V11_K, V11_L, V11_M, V11_N, V11_O, ++ V12, V12_H, V12_J, V12_K, V12_L, V12_M, V12_N, V12_O, ++ V13, V13_H, V13_J, V13_K, V13_L, V13_M, V13_N, V13_O, ++ V14, V14_H, V14_J, V14_K, V14_L, V14_M, V14_N, V14_O, ++ V15, V15_H, V15_J, V15_K, V15_L, V15_M, V15_N, V15_O, ++ V16, V16_H, V16_J, V16_K, V16_L, V16_M, V16_N, V16_O, ++ V17, V17_H, V17_J, V17_K, V17_L, V17_M, V17_N, V17_O, ++ V18, V18_H, V18_J, V18_K, V18_L, V18_M, V18_N, V18_O, ++ V19, V19_H, V19_J, V19_K, V19_L, V19_M, V19_N, V19_O, ++ V20, V20_H, V20_J, V20_K, V20_L, V20_M, V20_N, V20_O, ++ V21, V21_H, V21_J, V21_K, V21_L, V21_M, V21_N, V21_O, ++ V22, V22_H, V22_J, V22_K, V22_L, V22_M, V22_N, V22_O, ++ V23, V23_H, V23_J, V23_K, V23_L, V23_M, V23_N, V23_O, ++ V24, V24_H, V24_J, V24_K, V24_L, V24_M, V24_N, V24_O, ++ V25, V25_H, V25_J, V25_K, V25_L, V25_M, V25_N, V25_O, ++ V26, V26_H, V26_J, V26_K, V26_L, V26_M, V26_N, V26_O, ++ V27, V27_H, V27_J, V27_K, V27_L, V27_M, V27_N, V27_O, ++ V28, V28_H, V28_J, V28_K, V28_L, V28_M, V28_N, V28_O, ++ V29, V29_H, V29_J, V29_K, V29_L, V29_M, V29_N, V29_O, ++ V30, V30_H, V30_J, V30_K, V30_L, V30_M, V30_N, V30_O, ++ V31, V31_H, V31_J, V31_K, V31_L, V31_M, V31_N, V31_O, ++); ++ + // Class for all 64bit vector registers + reg_class vectord_reg( + V0, V0_H, +@@ -1097,6 +1302,31 @@ reg_class v31_reg( + V31, V31_H + ); + ++// Class for all SVE predicate registers. ++reg_class pr_reg ( ++ P0, ++ P1, ++ P2, ++ P3, ++ P4, ++ P5, ++ P6, ++ // P7, non-allocatable, preserved with all elements preset to TRUE. ++); ++ ++// Class for SVE governing predicate registers, which are used ++// to determine the active elements of a predicated instruction. ++reg_class gov_pr ( ++ P0, ++ P1, ++ P2, ++ P3, ++ P4, ++ P5, ++ P6, ++ // P7, non-allocatable, preserved with all elements preset to TRUE. ++); ++ + // Singleton class for condition codes + reg_class int_flags(RFLAGS); + +@@ -1862,7 +2092,7 @@ int MachEpilogNode::safepoint_offset() const { + + // Figure out which register class each belongs in: rc_int, rc_float or + // rc_stack. +-enum RC { rc_bad, rc_int, rc_float, rc_stack }; ++enum RC { rc_bad, rc_int, rc_float, rc_predicate, rc_stack }; + + static enum RC rc_class(OptoReg::Name reg) { + +@@ -1870,20 +2100,25 @@ static enum RC rc_class(OptoReg::Name reg) { + return rc_bad; + } + +- // we have 30 int registers * 2 halves +- // (rscratch1 and rscratch2 are omitted) +- int slots_of_int_registers = RegisterImpl::max_slots_per_register * (RegisterImpl::number_of_registers - 2); ++ // we have 32 int registers * 2 halves ++ int slots_of_int_registers = RegisterImpl::max_slots_per_register * RegisterImpl::number_of_registers; + + if (reg < slots_of_int_registers) { + return rc_int; + } + +- // we have 32 float register * 4 halves +- if (reg < slots_of_int_registers + FloatRegisterImpl::max_slots_per_register * FloatRegisterImpl::number_of_registers) { ++ // we have 32 float register * 8 halves ++ int slots_of_float_registers = FloatRegisterImpl::max_slots_per_register * FloatRegisterImpl::number_of_registers; ++ if (reg < slots_of_int_registers + slots_of_float_registers) { + return rc_float; + } + +- // Between float regs & stack is the flags regs. ++ int slots_of_predicate_registers = PRegisterImpl::max_slots_per_register * PRegisterImpl::number_of_registers; ++ if (reg < slots_of_int_registers + slots_of_float_registers + slots_of_predicate_registers) { ++ return rc_predicate; ++ } ++ ++ // Between predicate regs & stack is the flags. + assert(OptoReg::is_stack(reg), "blow up if spilling flags"); + + return rc_stack; +@@ -1941,12 +2176,12 @@ uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, boo + as_FloatRegister(Matcher::_regEncode[src_lo])); + } else if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) { + __ spill(as_FloatRegister(Matcher::_regEncode[src_lo]), +- ireg == Op_VecD ? __ D : __ Q, +- ra_->reg2offset(dst_lo)); ++ ireg == Op_VecD ? __ D : __ Q, ++ ra_->reg2offset(dst_lo)); + } else if (src_lo_rc == rc_stack && dst_lo_rc == rc_float) { + __ unspill(as_FloatRegister(Matcher::_regEncode[dst_lo]), +- ireg == Op_VecD ? __ D : __ Q, +- ra_->reg2offset(src_lo)); ++ ireg == Op_VecD ? __ D : __ Q, ++ ra_->reg2offset(src_lo)); + } else { + ShouldNotReachHere(); + } +@@ -2031,9 +2266,24 @@ uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, boo + st->print("%s", Matcher::regName[dst_lo]); + } + if (bottom_type()->isa_vect() != NULL) { +- st->print("\t# vector spill size = %d", ideal_reg()==Op_VecD ? 64:128); ++ int vsize = 0; ++ switch (ideal_reg()) { ++ case Op_VecD: ++ vsize = 64; ++ break; ++ case Op_VecX: ++ vsize = 128; ++ break; ++ case Op_VecA: ++ vsize = Matcher::scalable_vector_reg_size(T_BYTE) * 8; ++ break; ++ default: ++ assert(false, "bad register type for spill"); ++ ShouldNotReachHere(); ++ } ++ st->print("\t# vector spill size = %d", vsize); + } else { +- st->print("\t# spill size = %d", is64 ? 64:32); ++ st->print("\t# spill size = %d", is64 ? 64 : 32); + } + } + +@@ -2204,7 +2454,7 @@ const bool Matcher::match_rule_supported_vector(int opcode, int vlen) { + } + + const bool Matcher::has_predicated_vectors(void) { +- return false; ++ return UseSVE > 0; + } + + const int Matcher::float_pressure(int default_pressure_threshold) { +@@ -2240,7 +2490,8 @@ const bool Matcher::convL2FSupported(void) { + + // Vector width in bytes. + const int Matcher::vector_width_in_bytes(BasicType bt) { +- int size = MIN2(16,(int)MaxVectorSize); ++ // The MaxVectorSize should have been set by detecting SVE max vector register size. ++ int size = MIN2((UseSVE > 0) ? 256 : 16, (int)MaxVectorSize); + // Minimum 2 values in vector + if (size < 2*type2aelembytes(bt)) size = 0; + // But never < 4 +@@ -2253,14 +2504,32 @@ const int Matcher::max_vector_size(const BasicType bt) { + return vector_width_in_bytes(bt)/type2aelembytes(bt); + } + const int Matcher::min_vector_size(const BasicType bt) { +-// For the moment limit the vector size to 8 bytes ++ int max_size = max_vector_size(bt); ++ if ((UseSVE > 0) && (MaxVectorSize >= 16)) { ++ // Currently vector length less than SVE vector register size is not supported. ++ return max_size; ++ } else { ++ // For the moment limit the vector size to 8 bytes with NEON. + int size = 8 / type2aelembytes(bt); + if (size < 2) size = 2; + return size; ++ } ++} ++ ++const bool Matcher::supports_scalable_vector() { ++ return UseSVE > 0; ++} ++ ++// Actual max scalable vector register length. ++const int Matcher::scalable_vector_reg_size(const BasicType bt) { ++ return Matcher::max_vector_size(bt); + } + + // Vector ideal reg. + const uint Matcher::vector_ideal_reg(int len) { ++ if (UseSVE > 0 && 16 <= len && len <= 256) { ++ return Op_VecA; ++ } + switch(len) { + case 8: return Op_VecD; + case 16: return Op_VecX; +@@ -2270,6 +2539,9 @@ const uint Matcher::vector_ideal_reg(int len) { + } + + const uint Matcher::vector_shift_count_ideal_reg(int size) { ++ if (UseSVE > 0 && 16 <= size && size <= 256) { ++ return Op_VecA; ++ } + switch(size) { + case 8: return Op_VecD; + case 16: return Op_VecX; +@@ -4851,6 +5123,18 @@ operand vRegD() + interface(REG_INTER); + %} + ++// Generic vector class. This will be used for ++// all vector operands, including NEON and SVE, ++// but currently only used for SVE VecA. ++operand vReg() ++%{ ++ constraint(ALLOC_IN_RC(vectora_reg)); ++ match(VecA); ++ op_cost(0); ++ format %{ %} ++ interface(REG_INTER); ++%} ++ + operand vecD() + %{ + constraint(ALLOC_IN_RC(vectord_reg)); +@@ -5159,6 +5443,15 @@ operand vRegD_V31() + interface(REG_INTER); + %} + ++operand pRegGov() ++%{ ++ constraint(ALLOC_IN_RC(gov_pr)); ++ match(RegVMask); ++ op_cost(0); ++ format %{ %} ++ interface(REG_INTER); ++%} ++ + // Flags register, used as output of signed compare instructions + + // note that on AArch64 we also use this register as the output for +diff --git a/src/hotspot/cpu/aarch64/assembler_aarch64.hpp b/src/hotspot/cpu/aarch64/assembler_aarch64.hpp +index 228b82660..6f4e75ff4 100644 +--- a/src/hotspot/cpu/aarch64/assembler_aarch64.hpp ++++ b/src/hotspot/cpu/aarch64/assembler_aarch64.hpp +@@ -273,6 +273,14 @@ public: + f(r->encoding_nocheck(), lsb + 4, lsb); + } + ++ void prf(PRegister r, int lsb) { ++ f(r->encoding_nocheck(), lsb + 3, lsb); ++ } ++ ++ void pgrf(PRegister r, int lsb) { ++ f(r->encoding_nocheck(), lsb + 2, lsb); ++ } ++ + unsigned get(int msb = 31, int lsb = 0) { + int nbits = msb - lsb + 1; + unsigned mask = checked_cast(right_n_bits(nbits)) << lsb; +@@ -669,6 +677,12 @@ public: + void rf(FloatRegister reg, int lsb) { + current->rf(reg, lsb); + } ++ void prf(PRegister reg, int lsb) { ++ current->prf(reg, lsb); ++ } ++ void pgrf(PRegister reg, int lsb) { ++ current->pgrf(reg, lsb); ++ } + void fixed(unsigned value, unsigned mask) { + current->fixed(value, mask); + } +diff --git a/src/hotspot/cpu/aarch64/register_aarch64.cpp b/src/hotspot/cpu/aarch64/register_aarch64.cpp +index 36cbe3fee..3db8e8337 100644 +--- a/src/hotspot/cpu/aarch64/register_aarch64.cpp ++++ b/src/hotspot/cpu/aarch64/register_aarch64.cpp +@@ -1,6 +1,6 @@ + /* +- * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved. +- * Copyright (c) 2014, Red Hat Inc. All rights reserved. ++ * Copyright (c) 2000, 2020, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it +@@ -33,6 +33,9 @@ const int ConcreteRegisterImpl::max_fpr + = ConcreteRegisterImpl::max_gpr + + FloatRegisterImpl::number_of_registers * FloatRegisterImpl::max_slots_per_register; + ++const int ConcreteRegisterImpl::max_pr ++ = ConcreteRegisterImpl::max_fpr + PRegisterImpl::number_of_registers; ++ + const char* RegisterImpl::name() const { + const char* names[number_of_registers] = { + "c_rarg0", "c_rarg1", "c_rarg2", "c_rarg3", "c_rarg4", "c_rarg5", "c_rarg6", "c_rarg7", +@@ -54,3 +57,10 @@ const char* FloatRegisterImpl::name() const { + }; + return is_valid() ? names[encoding()] : "noreg"; + } ++ ++const char* PRegisterImpl::name() const { ++ const char* names[number_of_registers] = { ++ "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7" ++ }; ++ return is_valid() ? names[encoding()] : "noreg"; ++} +diff --git a/src/hotspot/cpu/aarch64/register_aarch64.hpp b/src/hotspot/cpu/aarch64/register_aarch64.hpp +index 20f549188..e7a9cee92 100644 +--- a/src/hotspot/cpu/aarch64/register_aarch64.hpp ++++ b/src/hotspot/cpu/aarch64/register_aarch64.hpp +@@ -140,9 +140,10 @@ class FloatRegisterImpl: public AbstractRegisterImpl { + public: + enum { + number_of_registers = 32, +- max_slots_per_register = 4, ++ max_slots_per_register = 8, + save_slots_per_register = 2, +- extra_save_slots_per_register = max_slots_per_register - save_slots_per_register ++ slots_per_neon_register = 4, ++ extra_save_slots_per_neon_register = slots_per_neon_register - save_slots_per_register + }; + + // construction +@@ -198,6 +199,79 @@ CONSTANT_REGISTER_DECLARATION(FloatRegister, v29 , (29)); + CONSTANT_REGISTER_DECLARATION(FloatRegister, v30 , (30)); + CONSTANT_REGISTER_DECLARATION(FloatRegister, v31 , (31)); + ++// SVE vector registers, shared with the SIMD&FP v0-v31. Vn maps to Zn[127:0]. ++CONSTANT_REGISTER_DECLARATION(FloatRegister, z0 , ( 0)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, z1 , ( 1)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, z2 , ( 2)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, z3 , ( 3)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, z4 , ( 4)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, z5 , ( 5)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, z6 , ( 6)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, z7 , ( 7)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, z8 , ( 8)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, z9 , ( 9)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, z10 , (10)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, z11 , (11)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, z12 , (12)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, z13 , (13)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, z14 , (14)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, z15 , (15)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, z16 , (16)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, z17 , (17)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, z18 , (18)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, z19 , (19)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, z20 , (20)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, z21 , (21)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, z22 , (22)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, z23 , (23)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, z24 , (24)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, z25 , (25)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, z26 , (26)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, z27 , (27)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, z28 , (28)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, z29 , (29)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, z30 , (30)); ++CONSTANT_REGISTER_DECLARATION(FloatRegister, z31 , (31)); ++ ++class PRegisterImpl; ++typedef PRegisterImpl* PRegister; ++inline PRegister as_PRegister(int encoding) { ++ return (PRegister)(intptr_t)encoding; ++} ++ ++// The implementation of predicate registers for the architecture ++class PRegisterImpl: public AbstractRegisterImpl { ++ public: ++ enum { ++ number_of_registers = 8, ++ max_slots_per_register = 1 ++ }; ++ ++ // construction ++ inline friend PRegister as_PRegister(int encoding); ++ ++ VMReg as_VMReg(); ++ ++ // derived registers, offsets, and addresses ++ PRegister successor() const { return as_PRegister(encoding() + 1); } ++ ++ // accessors ++ int encoding() const { assert(is_valid(), "invalid register"); return (intptr_t)this; } ++ int encoding_nocheck() const { return (intptr_t)this; } ++ bool is_valid() const { return 0 <= (intptr_t)this && (intptr_t)this < number_of_registers; } ++ const char* name() const; ++}; ++ ++// The predicate registers of SVE. ++CONSTANT_REGISTER_DECLARATION(PRegister, p0, ( 0)); ++CONSTANT_REGISTER_DECLARATION(PRegister, p1, ( 1)); ++CONSTANT_REGISTER_DECLARATION(PRegister, p2, ( 2)); ++CONSTANT_REGISTER_DECLARATION(PRegister, p3, ( 3)); ++CONSTANT_REGISTER_DECLARATION(PRegister, p4, ( 4)); ++CONSTANT_REGISTER_DECLARATION(PRegister, p5, ( 5)); ++CONSTANT_REGISTER_DECLARATION(PRegister, p6, ( 6)); ++CONSTANT_REGISTER_DECLARATION(PRegister, p7, ( 7)); ++ + // Need to know the total number of registers of all sorts for SharedInfo. + // Define a class that exports it. + class ConcreteRegisterImpl : public AbstractRegisterImpl { +@@ -210,12 +284,14 @@ class ConcreteRegisterImpl : public AbstractRegisterImpl { + + number_of_registers = (RegisterImpl::max_slots_per_register * RegisterImpl::number_of_registers + + FloatRegisterImpl::max_slots_per_register * FloatRegisterImpl::number_of_registers + ++ PRegisterImpl::max_slots_per_register * PRegisterImpl::number_of_registers + + 1) // flags + }; + + // added to make it compile + static const int max_gpr; + static const int max_fpr; ++ static const int max_pr; + }; + + class RegSetIterator; +diff --git a/src/hotspot/cpu/aarch64/register_definitions_aarch64.cpp b/src/hotspot/cpu/aarch64/register_definitions_aarch64.cpp +index c18109087..15131ed32 100644 +--- a/src/hotspot/cpu/aarch64/register_definitions_aarch64.cpp ++++ b/src/hotspot/cpu/aarch64/register_definitions_aarch64.cpp +@@ -1,5 +1,5 @@ + /* +- * Copyright (c) 2002, 2018, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2002, 2020, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2014, Red Hat Inc. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * +@@ -154,3 +154,45 @@ REGISTER_DEFINITION(Register, rthread); + REGISTER_DEFINITION(Register, rheapbase); + + REGISTER_DEFINITION(Register, r31_sp); ++ ++REGISTER_DEFINITION(FloatRegister, z0); ++REGISTER_DEFINITION(FloatRegister, z1); ++REGISTER_DEFINITION(FloatRegister, z2); ++REGISTER_DEFINITION(FloatRegister, z3); ++REGISTER_DEFINITION(FloatRegister, z4); ++REGISTER_DEFINITION(FloatRegister, z5); ++REGISTER_DEFINITION(FloatRegister, z6); ++REGISTER_DEFINITION(FloatRegister, z7); ++REGISTER_DEFINITION(FloatRegister, z8); ++REGISTER_DEFINITION(FloatRegister, z9); ++REGISTER_DEFINITION(FloatRegister, z10); ++REGISTER_DEFINITION(FloatRegister, z11); ++REGISTER_DEFINITION(FloatRegister, z12); ++REGISTER_DEFINITION(FloatRegister, z13); ++REGISTER_DEFINITION(FloatRegister, z14); ++REGISTER_DEFINITION(FloatRegister, z15); ++REGISTER_DEFINITION(FloatRegister, z16); ++REGISTER_DEFINITION(FloatRegister, z17); ++REGISTER_DEFINITION(FloatRegister, z18); ++REGISTER_DEFINITION(FloatRegister, z19); ++REGISTER_DEFINITION(FloatRegister, z20); ++REGISTER_DEFINITION(FloatRegister, z21); ++REGISTER_DEFINITION(FloatRegister, z22); ++REGISTER_DEFINITION(FloatRegister, z23); ++REGISTER_DEFINITION(FloatRegister, z24); ++REGISTER_DEFINITION(FloatRegister, z25); ++REGISTER_DEFINITION(FloatRegister, z26); ++REGISTER_DEFINITION(FloatRegister, z27); ++REGISTER_DEFINITION(FloatRegister, z28); ++REGISTER_DEFINITION(FloatRegister, z29); ++REGISTER_DEFINITION(FloatRegister, z30); ++REGISTER_DEFINITION(FloatRegister, z31); ++ ++REGISTER_DEFINITION(PRegister, p0); ++REGISTER_DEFINITION(PRegister, p1); ++REGISTER_DEFINITION(PRegister, p2); ++REGISTER_DEFINITION(PRegister, p3); ++REGISTER_DEFINITION(PRegister, p4); ++REGISTER_DEFINITION(PRegister, p5); ++REGISTER_DEFINITION(PRegister, p6); ++REGISTER_DEFINITION(PRegister, p7); +diff --git a/src/hotspot/cpu/aarch64/sharedRuntime_aarch64.cpp b/src/hotspot/cpu/aarch64/sharedRuntime_aarch64.cpp +index dbad48582..3bf7284a7 100644 +--- a/src/hotspot/cpu/aarch64/sharedRuntime_aarch64.cpp ++++ b/src/hotspot/cpu/aarch64/sharedRuntime_aarch64.cpp +@@ -111,11 +111,28 @@ class RegisterSaver { + }; + + OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words, bool save_vectors) { ++ bool use_sve = false; ++ int sve_vector_size_in_bytes = 0; ++ int sve_vector_size_in_slots = 0; ++ ++#ifdef COMPILER2 ++ use_sve = Matcher::supports_scalable_vector(); ++ sve_vector_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE); ++ sve_vector_size_in_slots = Matcher::scalable_vector_reg_size(T_FLOAT); ++#endif ++ + #if COMPILER2_OR_JVMCI + if (save_vectors) { ++ int vect_words = 0; ++ int extra_save_slots_per_register = 0; + // Save upper half of vector registers +- int vect_words = FloatRegisterImpl::number_of_registers * FloatRegisterImpl::extra_save_slots_per_register / +- VMRegImpl::slots_per_word; ++ if (use_sve) { ++ extra_save_slots_per_register = sve_vector_size_in_slots - FloatRegisterImpl::save_slots_per_register; ++ } else { ++ extra_save_slots_per_register = FloatRegisterImpl::extra_save_slots_per_neon_register; ++ } ++ vect_words = FloatRegisterImpl::number_of_registers * extra_save_slots_per_register / ++ VMRegImpl::slots_per_word; + additional_frame_words += vect_words; + } + #else +@@ -158,8 +175,13 @@ OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_ + + for (int i = 0; i < FloatRegisterImpl::number_of_registers; i++) { + FloatRegister r = as_FloatRegister(i); +- int sp_offset = save_vectors ? (FloatRegisterImpl::max_slots_per_register * i) : +- (FloatRegisterImpl::save_slots_per_register * i); ++ int sp_offset = 0; ++ if (save_vectors) { ++ sp_offset = use_sve ? (sve_vector_size_in_slots * i) : ++ (FloatRegisterImpl::slots_per_neon_register * i); ++ } else { ++ sp_offset = FloatRegisterImpl::save_slots_per_register * i; ++ } + oop_map->set_callee_saved(VMRegImpl::stack2reg(sp_offset), + r->as_VMReg()); + } +diff --git a/src/hotspot/cpu/aarch64/vmreg_aarch64.inline.hpp b/src/hotspot/cpu/aarch64/vmreg_aarch64.inline.hpp +index c5d4383b4..dde7a7a91 100644 +--- a/src/hotspot/cpu/aarch64/vmreg_aarch64.inline.hpp ++++ b/src/hotspot/cpu/aarch64/vmreg_aarch64.inline.hpp +@@ -1,6 +1,6 @@ + /* +- * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved. +- * Copyright (c) 2014, Red Hat Inc. All rights reserved. ++ * Copyright (c) 2006, 2020, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it +@@ -36,4 +36,8 @@ inline VMReg FloatRegisterImpl::as_VMReg() { + ConcreteRegisterImpl::max_gpr); + } + ++inline VMReg PRegisterImpl::as_VMReg() { ++ return VMRegImpl::as_VMReg(encoding() + ConcreteRegisterImpl::max_fpr); ++} ++ + #endif // CPU_AARCH64_VM_VMREG_AARCH64_INLINE_HPP +diff --git a/src/hotspot/cpu/arm/arm.ad b/src/hotspot/cpu/arm/arm.ad +index 4a32af54e..0ef4d7f3e 100644 +--- a/src/hotspot/cpu/arm/arm.ad ++++ b/src/hotspot/cpu/arm/arm.ad +@@ -1121,6 +1121,14 @@ const int Matcher::vector_width_in_bytes(BasicType bt) { + return MaxVectorSize; + } + ++const bool Matcher::supports_scalable_vector() { ++ return false; ++} ++ ++const int Matcher::scalable_vector_reg_size(const BasicType bt) { ++ return -1; ++} ++ + // Vector ideal reg corresponding to specified size in bytes + const uint Matcher::vector_ideal_reg(int size) { + assert(MaxVectorSize >= size, ""); +diff --git a/src/hotspot/cpu/ppc/ppc.ad b/src/hotspot/cpu/ppc/ppc.ad +index 36cbada53..7ee16a975 100644 +--- a/src/hotspot/cpu/ppc/ppc.ad ++++ b/src/hotspot/cpu/ppc/ppc.ad +@@ -2310,6 +2310,14 @@ const int Matcher::min_vector_size(const BasicType bt) { + return max_vector_size(bt); // Same as max. + } + ++const bool Matcher::supports_scalable_vector() { ++ return false; ++} ++ ++const int Matcher::scalable_vector_reg_size(const BasicType bt) { ++ return -1; ++} ++ + // PPC implementation uses VSX load/store instructions (if + // SuperwordUseVSX) which support 4 byte but not arbitrary alignment + const bool Matcher::misaligned_vectors_ok() { +diff --git a/src/hotspot/cpu/s390/s390.ad b/src/hotspot/cpu/s390/s390.ad +index 96c231b0a..ea09aaafc 100644 +--- a/src/hotspot/cpu/s390/s390.ad ++++ b/src/hotspot/cpu/s390/s390.ad +@@ -1573,6 +1573,14 @@ const int Matcher::min_vector_size(const BasicType bt) { + return max_vector_size(bt); // Same as max. + } + ++const bool Matcher::supports_scalable_vector() { ++ return false; ++} ++ ++const int Matcher::scalable_vector_reg_size(const BasicType bt) { ++ return -1; ++} ++ + const uint Matcher::vector_shift_count_ideal_reg(int size) { + fatal("vector shift is not supported"); + return Node::NotAMachineReg; +diff --git a/src/hotspot/cpu/x86/x86.ad b/src/hotspot/cpu/x86/x86.ad +index abdd7483d..76dd6addd 100644 +--- a/src/hotspot/cpu/x86/x86.ad ++++ b/src/hotspot/cpu/x86/x86.ad +@@ -1,5 +1,5 @@ + // +-// Copyright (c) 2011, 2019, Oracle and/or its affiliates. All rights reserved. ++// Copyright (c) 2011, 2020, Oracle and/or its affiliates. All rights reserved. + // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + // + // This code is free software; you can redistribute it and/or modify it +@@ -1485,6 +1485,14 @@ const int Matcher::min_vector_size(const BasicType bt) { + return MIN2(size,max_size); + } + ++const bool Matcher::supports_scalable_vector() { ++ return false; ++} ++ ++const int Matcher::scalable_vector_reg_size(const BasicType bt) { ++ return -1; ++} ++ + // Vector ideal reg corresponding to specified size in bytes + const uint Matcher::vector_ideal_reg(int size) { + assert(MaxVectorSize >= size, ""); +diff --git a/src/hotspot/cpu/x86/x86_64.ad b/src/hotspot/cpu/x86/x86_64.ad +index 8904bba97..e09cdd061 100644 +--- a/src/hotspot/cpu/x86/x86_64.ad ++++ b/src/hotspot/cpu/x86/x86_64.ad +@@ -2968,7 +2968,7 @@ frame + RAX_H_num // Op_RegL + }; + // Excluded flags and vector registers. +- assert(ARRAY_SIZE(hi) == _last_machine_leaf - 6, "missing type"); ++ assert(ARRAY_SIZE(hi) == _last_machine_leaf - 8, "missing type"); + return OptoRegPair(hi[ideal_reg], lo[ideal_reg]); + %} + %} +diff --git a/src/hotspot/share/adlc/archDesc.cpp b/src/hotspot/share/adlc/archDesc.cpp +index ba61aa4c0..9e41b2dc6 100644 +--- a/src/hotspot/share/adlc/archDesc.cpp ++++ b/src/hotspot/share/adlc/archDesc.cpp +@@ -1,5 +1,5 @@ + // +-// Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved. ++// Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved. + // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + // + // This code is free software; you can redistribute it and/or modify it +@@ -929,6 +929,7 @@ const char *ArchDesc::getIdealType(const char *idealOp) { + // Match Vector types. + if (strncmp(idealOp, "Vec",3)==0) { + switch(last_char) { ++ case 'A': return "TypeVect::VECTA"; + case 'S': return "TypeVect::VECTS"; + case 'D': return "TypeVect::VECTD"; + case 'X': return "TypeVect::VECTX"; +@@ -939,6 +940,10 @@ const char *ArchDesc::getIdealType(const char *idealOp) { + } + } + ++ if (strncmp(idealOp, "RegVMask", 8) == 0) { ++ return "Type::BOTTOM"; ++ } ++ + // !!!!! + switch(last_char) { + case 'I': return "TypeInt::INT"; +diff --git a/src/hotspot/share/adlc/formssel.cpp b/src/hotspot/share/adlc/formssel.cpp +index c7b855a7e..a37866824 100644 +--- a/src/hotspot/share/adlc/formssel.cpp ++++ b/src/hotspot/share/adlc/formssel.cpp +@@ -3963,6 +3963,8 @@ bool MatchRule::is_base_register(FormDict &globals) const { + strcmp(opType,"RegL")==0 || + strcmp(opType,"RegF")==0 || + strcmp(opType,"RegD")==0 || ++ strcmp(opType,"RegVMask")==0 || ++ strcmp(opType,"VecA")==0 || + strcmp(opType,"VecS")==0 || + strcmp(opType,"VecD")==0 || + strcmp(opType,"VecX")==0 || +diff --git a/src/hotspot/share/opto/chaitin.cpp b/src/hotspot/share/opto/chaitin.cpp +index 914dc43f6..710af9de8 100644 +--- a/src/hotspot/share/opto/chaitin.cpp ++++ b/src/hotspot/share/opto/chaitin.cpp +@@ -77,6 +77,7 @@ void LRG::dump() const { + if( _is_oop ) tty->print("Oop "); + if( _is_float ) tty->print("Float "); + if( _is_vector ) tty->print("Vector "); ++ if( _is_scalable ) tty->print("Scalable "); + if( _was_spilled1 ) tty->print("Spilled "); + if( _was_spilled2 ) tty->print("Spilled2 "); + if( _direct_conflict ) tty->print("Direct_conflict "); +@@ -646,7 +647,15 @@ void PhaseChaitin::Register_Allocate() { + // Live ranges record the highest register in their mask. + // We want the low register for the AD file writer's convenience. + OptoReg::Name hi = lrg.reg(); // Get hi register +- OptoReg::Name lo = OptoReg::add(hi, (1-lrg.num_regs())); // Find lo ++ int num_regs = lrg.num_regs(); ++ if (lrg.is_scalable() && OptoReg::is_stack(hi)) { ++ // For scalable vector registers, when they are allocated in physical ++ // registers, num_regs is RegMask::SlotsPerVecA for reg mask of scalable ++ // vector. If they are allocated on stack, we need to get the actual ++ // num_regs, which reflects the physical length of scalable registers. ++ num_regs = lrg.scalable_reg_slots(); ++ } ++ OptoReg::Name lo = OptoReg::add(hi, (1-num_regs)); // Find lo + // We have to use pair [lo,lo+1] even for wide vectors because + // the rest of code generation works only with pairs. It is safe + // since for registers encoding only 'lo' is used. +@@ -801,8 +810,19 @@ void PhaseChaitin::gather_lrg_masks( bool after_aggressive ) { + // Check for vector live range (only if vector register is used). + // On SPARC vector uses RegD which could be misaligned so it is not + // processes as vector in RA. +- if (RegMask::is_vector(ireg)) ++ if (RegMask::is_vector(ireg)) { + lrg._is_vector = 1; ++ if (ireg == Op_VecA) { ++ assert(Matcher::supports_scalable_vector(), "scalable vector should be supported"); ++ lrg._is_scalable = 1; ++ // For scalable vector, when it is allocated in physical register, ++ // num_regs is RegMask::SlotsPerVecA for reg mask, ++ // which may not be the actual physical register size. ++ // If it is allocated in stack, we need to get the actual ++ // physical length of scalable vector register. ++ lrg.set_scalable_reg_slots(Matcher::scalable_vector_reg_size(T_FLOAT)); ++ } ++ } + assert(n_type->isa_vect() == NULL || lrg._is_vector || ireg == Op_RegD || ireg == Op_RegL, + "vector must be in vector registers"); + +@@ -912,6 +932,13 @@ void PhaseChaitin::gather_lrg_masks( bool after_aggressive ) { + lrg.set_reg_pressure(1); + #endif + break; ++ case Op_VecA: ++ assert(Matcher::supports_scalable_vector(), "does not support scalable vector"); ++ assert(RegMask::num_registers(Op_VecA) == RegMask::SlotsPerVecA, "sanity"); ++ assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecA), "vector should be aligned"); ++ lrg.set_num_regs(RegMask::SlotsPerVecA); ++ lrg.set_reg_pressure(1); ++ break; + case Op_VecS: + assert(Matcher::vector_size_supported(T_BYTE,4), "sanity"); + assert(RegMask::num_registers(Op_VecS) == RegMask::SlotsPerVecS, "sanity"); +@@ -1358,6 +1385,46 @@ static bool is_legal_reg(LRG &lrg, OptoReg::Name reg, int chunk) { + return false; + } + ++static OptoReg::Name find_first_set(LRG &lrg, RegMask mask, int chunk) { ++ int num_regs = lrg.num_regs(); ++ OptoReg::Name assigned = mask.find_first_set(lrg, num_regs); ++ ++ if (lrg.is_scalable()) { ++ // a physical register is found ++ if (chunk == 0 && OptoReg::is_reg(assigned)) { ++ return assigned; ++ } ++ ++ // find available stack slots for scalable register ++ if (lrg._is_vector) { ++ num_regs = lrg.scalable_reg_slots(); ++ // if actual scalable vector register is exactly SlotsPerVecA * 32 bits ++ if (num_regs == RegMask::SlotsPerVecA) { ++ return assigned; ++ } ++ ++ // mask has been cleared out by clear_to_sets(SlotsPerVecA) before choose_color, but it ++ // does not work for scalable size. We have to find adjacent scalable_reg_slots() bits ++ // instead of SlotsPerVecA bits. ++ assigned = mask.find_first_set(lrg, num_regs); // find highest valid reg ++ while (OptoReg::is_valid(assigned) && RegMask::can_represent(assigned)) { ++ // Verify the found reg has scalable_reg_slots() bits set. ++ if (mask.is_valid_reg(assigned, num_regs)) { ++ return assigned; ++ } else { ++ // Remove more for each iteration ++ mask.Remove(assigned - num_regs + 1); // Unmask the lowest reg ++ mask.clear_to_sets(RegMask::SlotsPerVecA); // Align by SlotsPerVecA bits ++ assigned = mask.find_first_set(lrg, num_regs); ++ } ++ } ++ return OptoReg::Bad; // will cause chunk change, and retry next chunk ++ } ++ } ++ ++ return assigned; ++} ++ + // Choose a color using the biasing heuristic + OptoReg::Name PhaseChaitin::bias_color( LRG &lrg, int chunk ) { + +@@ -1391,7 +1458,7 @@ OptoReg::Name PhaseChaitin::bias_color( LRG &lrg, int chunk ) { + RegMask tempmask = lrg.mask(); + tempmask.AND(lrgs(copy_lrg).mask()); + tempmask.clear_to_sets(lrg.num_regs()); +- OptoReg::Name reg = tempmask.find_first_set(lrg.num_regs()); ++ OptoReg::Name reg = find_first_set(lrg, tempmask, chunk); + if (OptoReg::is_valid(reg)) + return reg; + } +@@ -1400,7 +1467,7 @@ OptoReg::Name PhaseChaitin::bias_color( LRG &lrg, int chunk ) { + // If no bias info exists, just go with the register selection ordering + if (lrg._is_vector || lrg.num_regs() == 2) { + // Find an aligned set +- return OptoReg::add(lrg.mask().find_first_set(lrg.num_regs()),chunk); ++ return OptoReg::add(find_first_set(lrg, lrg.mask(), chunk), chunk); + } + + // CNC - Fun hack. Alternate 1st and 2nd selection. Enables post-allocate +@@ -1455,7 +1522,6 @@ uint PhaseChaitin::Select( ) { + LRG *lrg = &lrgs(lidx); + _simplified = lrg->_next; + +- + #ifndef PRODUCT + if (trace_spilling()) { + ttyLocker ttyl; +@@ -1539,7 +1605,6 @@ uint PhaseChaitin::Select( ) { + // Bump register mask up to next stack chunk + chunk += RegMask::CHUNK_SIZE; + lrg->Set_All(); +- + goto retry_next_chunk; + } + +@@ -1564,12 +1629,21 @@ uint PhaseChaitin::Select( ) { + int n_regs = lrg->num_regs(); + assert(!lrg->_is_vector || !lrg->_fat_proj, "sanity"); + if (n_regs == 1 || !lrg->_fat_proj) { +- assert(!lrg->_is_vector || n_regs <= RegMask::SlotsPerVecZ, "sanity"); ++ if (Matcher::supports_scalable_vector()) { ++ assert(!lrg->_is_vector || n_regs <= RegMask::SlotsPerVecA, "sanity"); ++ } else { ++ assert(!lrg->_is_vector || n_regs <= RegMask::SlotsPerVecZ, "sanity"); ++ } + lrg->Clear(); // Clear the mask + lrg->Insert(reg); // Set regmask to match selected reg + // For vectors and pairs, also insert the low bit of the pair +- for (int i = 1; i < n_regs; i++) ++ // We always choose the high bit, then mask the low bits by register size ++ if (lrg->is_scalable() && OptoReg::is_stack(lrg->reg())) { // stack ++ n_regs = lrg->scalable_reg_slots(); ++ } ++ for (int i = 1; i < n_regs; i++) { + lrg->Insert(OptoReg::add(reg,-i)); ++ } + lrg->set_mask_size(n_regs); + } else { // Else fatproj + // mask must be equal to fatproj bits, by definition +diff --git a/src/hotspot/share/opto/chaitin.hpp b/src/hotspot/share/opto/chaitin.hpp +index e5be5b966..5408a24ef 100644 +--- a/src/hotspot/share/opto/chaitin.hpp ++++ b/src/hotspot/share/opto/chaitin.hpp +@@ -1,5 +1,5 @@ + /* +- * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it +@@ -115,7 +115,9 @@ public: + _msize_valid=1; + if (_is_vector) { + assert(!_fat_proj, "sanity"); +- _mask.verify_sets(_num_regs); ++ if (!(_is_scalable && OptoReg::is_stack(_reg))) { ++ _mask.verify_sets(_num_regs); ++ } + } else if (_num_regs == 2 && !_fat_proj) { + _mask.verify_pairs(); + } +@@ -139,14 +141,37 @@ public: + void clear_to_pairs() { _mask.clear_to_pairs(); debug_only(_msize_valid=0;) } + void clear_to_sets() { _mask.clear_to_sets(_num_regs); debug_only(_msize_valid=0;) } + +- // Number of registers this live range uses when it colors + private: ++ // Number of registers this live range uses when it colors + uint16_t _num_regs; // 2 for Longs and Doubles, 1 for all else + // except _num_regs is kill count for fat_proj ++ ++ // For scalable register, num_regs may not be the actual physical register size. ++ // We need to get the actual physical length of scalable register when scalable ++ // register is spilled. The size of one slot is 32-bit. ++ uint _scalable_reg_slots; // Actual scalable register length of slots. ++ // Meaningful only when _is_scalable is true. + public: + int num_regs() const { return _num_regs; } + void set_num_regs( int reg ) { assert( _num_regs == reg || !_num_regs, "" ); _num_regs = reg; } + ++ uint scalable_reg_slots() { return _scalable_reg_slots; } ++ void set_scalable_reg_slots(uint slots) { ++ assert(_is_scalable, "scalable register"); ++ assert(slots > 0, "slots of scalable register is not valid"); ++ _scalable_reg_slots = slots; ++ } ++ ++ bool is_scalable() { ++#ifdef ASSERT ++ if (_is_scalable) { ++ // Should only be a vector for now, but it could also be a RegVMask in future. ++ assert(_is_vector && (_num_regs == RegMask::SlotsPerVecA), "unexpected scalable reg"); ++ } ++#endif ++ return _is_scalable; ++ } ++ + private: + // Number of physical registers this live range uses when it colors + // Architecture and register-set dependent +@@ -172,6 +197,8 @@ public: + uint _is_oop:1, // Live-range holds an oop + _is_float:1, // True if in float registers + _is_vector:1, // True if in vector registers ++ _is_scalable:1, // True if register size is scalable ++ // e.g. Arm SVE vector/predicate registers. + _was_spilled1:1, // True if prior spilling on def + _was_spilled2:1, // True if twice prior spilling on def + _is_bound:1, // live range starts life with no +diff --git a/src/hotspot/share/opto/matcher.cpp b/src/hotspot/share/opto/matcher.cpp +index 4cc7580a8..4fb732161 100644 +--- a/src/hotspot/share/opto/matcher.cpp ++++ b/src/hotspot/share/opto/matcher.cpp +@@ -84,6 +84,7 @@ Matcher::Matcher() + idealreg2spillmask [Op_RegF] = NULL; + idealreg2spillmask [Op_RegD] = NULL; + idealreg2spillmask [Op_RegP] = NULL; ++ idealreg2spillmask [Op_VecA] = NULL; + idealreg2spillmask [Op_VecS] = NULL; + idealreg2spillmask [Op_VecD] = NULL; + idealreg2spillmask [Op_VecX] = NULL; +@@ -97,6 +98,7 @@ Matcher::Matcher() + idealreg2debugmask [Op_RegF] = NULL; + idealreg2debugmask [Op_RegD] = NULL; + idealreg2debugmask [Op_RegP] = NULL; ++ idealreg2debugmask [Op_VecA] = NULL; + idealreg2debugmask [Op_VecS] = NULL; + idealreg2debugmask [Op_VecD] = NULL; + idealreg2debugmask [Op_VecX] = NULL; +@@ -110,6 +112,7 @@ Matcher::Matcher() + idealreg2mhdebugmask[Op_RegF] = NULL; + idealreg2mhdebugmask[Op_RegD] = NULL; + idealreg2mhdebugmask[Op_RegP] = NULL; ++ idealreg2mhdebugmask[Op_VecA] = NULL; + idealreg2mhdebugmask[Op_VecS] = NULL; + idealreg2mhdebugmask[Op_VecD] = NULL; + idealreg2mhdebugmask[Op_VecX] = NULL; +@@ -417,6 +420,8 @@ static RegMask *init_input_masks( uint size, RegMask &ret_adr, RegMask &fp ) { + return rms; + } + ++#define NOF_STACK_MASKS (3*6+6) ++ + //---------------------------init_first_stack_mask----------------------------- + // Create the initial stack mask used by values spilling to the stack. + // Disallow any debug info in outgoing argument areas by setting the +@@ -424,7 +429,12 @@ static RegMask *init_input_masks( uint size, RegMask &ret_adr, RegMask &fp ) { + void Matcher::init_first_stack_mask() { + + // Allocate storage for spill masks as masks for the appropriate load type. +- RegMask *rms = (RegMask*)C->comp_arena()->Amalloc_D(sizeof(RegMask) * (3*6+5)); ++ RegMask *rms = (RegMask*)C->comp_arena()->Amalloc_D(sizeof(RegMask) * NOF_STACK_MASKS); ++ ++ // Initialize empty placeholder masks into the newly allocated arena ++ for (int i = 0; i < NOF_STACK_MASKS; i++) { ++ new (rms + i) RegMask(); ++ } + + idealreg2spillmask [Op_RegN] = &rms[0]; + idealreg2spillmask [Op_RegI] = &rms[1]; +@@ -447,11 +457,12 @@ void Matcher::init_first_stack_mask() { + idealreg2mhdebugmask[Op_RegD] = &rms[16]; + idealreg2mhdebugmask[Op_RegP] = &rms[17]; + +- idealreg2spillmask [Op_VecS] = &rms[18]; +- idealreg2spillmask [Op_VecD] = &rms[19]; +- idealreg2spillmask [Op_VecX] = &rms[20]; +- idealreg2spillmask [Op_VecY] = &rms[21]; +- idealreg2spillmask [Op_VecZ] = &rms[22]; ++ idealreg2spillmask [Op_VecA] = &rms[18]; ++ idealreg2spillmask [Op_VecS] = &rms[19]; ++ idealreg2spillmask [Op_VecD] = &rms[20]; ++ idealreg2spillmask [Op_VecX] = &rms[21]; ++ idealreg2spillmask [Op_VecY] = &rms[22]; ++ idealreg2spillmask [Op_VecZ] = &rms[23]; + + OptoReg::Name i; + +@@ -478,6 +489,7 @@ void Matcher::init_first_stack_mask() { + // Keep spill masks aligned. + aligned_stack_mask.clear_to_pairs(); + assert(aligned_stack_mask.is_AllStack(), "should be infinite stack"); ++ RegMask scalable_stack_mask = aligned_stack_mask; + + *idealreg2spillmask[Op_RegP] = *idealreg2regmask[Op_RegP]; + #ifdef _LP64 +@@ -548,28 +560,48 @@ void Matcher::init_first_stack_mask() { + *idealreg2spillmask[Op_VecZ] = *idealreg2regmask[Op_VecZ]; + idealreg2spillmask[Op_VecZ]->OR(aligned_stack_mask); + } +- if (UseFPUForSpilling) { +- // This mask logic assumes that the spill operations are +- // symmetric and that the registers involved are the same size. +- // On sparc for instance we may have to use 64 bit moves will +- // kill 2 registers when used with F0-F31. +- idealreg2spillmask[Op_RegI]->OR(*idealreg2regmask[Op_RegF]); +- idealreg2spillmask[Op_RegF]->OR(*idealreg2regmask[Op_RegI]); ++ ++ if (Matcher::supports_scalable_vector()) { ++ int k = 1; ++ OptoReg::Name in = OptoReg::add(_in_arg_limit, -1); ++ // Exclude last input arg stack slots to avoid spilling vector register there, ++ // otherwise vector spills could stomp over stack slots in caller frame. ++ for (; (in >= init_in) && (k < scalable_vector_reg_size(T_FLOAT)); k++) { ++ scalable_stack_mask.Remove(in); ++ in = OptoReg::add(in, -1); ++ } ++ ++ // For VecA ++ scalable_stack_mask.clear_to_sets(RegMask::SlotsPerVecA); ++ assert(scalable_stack_mask.is_AllStack(), "should be infinite stack"); ++ *idealreg2spillmask[Op_VecA] = *idealreg2regmask[Op_VecA]; ++ idealreg2spillmask[Op_VecA]->OR(scalable_stack_mask); ++ } else { ++ *idealreg2spillmask[Op_VecA] = RegMask::Empty; ++ } ++ ++ if (UseFPUForSpilling) { ++ // This mask logic assumes that the spill operations are ++ // symmetric and that the registers involved are the same size. ++ // On sparc for instance we may have to use 64 bit moves will ++ // kill 2 registers when used with F0-F31. ++ idealreg2spillmask[Op_RegI]->OR(*idealreg2regmask[Op_RegF]); ++ idealreg2spillmask[Op_RegF]->OR(*idealreg2regmask[Op_RegI]); + #ifdef _LP64 +- idealreg2spillmask[Op_RegN]->OR(*idealreg2regmask[Op_RegF]); +- idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]); +- idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]); +- idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegD]); ++ idealreg2spillmask[Op_RegN]->OR(*idealreg2regmask[Op_RegF]); ++ idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]); ++ idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]); ++ idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegD]); + #else +- idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegF]); ++ idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegF]); + #ifdef ARM +- // ARM has support for moving 64bit values between a pair of +- // integer registers and a double register +- idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]); +- idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]); ++ // ARM has support for moving 64bit values between a pair of ++ // integer registers and a double register ++ idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]); ++ idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]); + #endif + #endif +- } ++ } + + // Make up debug masks. Any spill slot plus callee-save registers. + // Caller-save registers are assumed to be trashable by the various +@@ -872,6 +904,10 @@ void Matcher::init_spill_mask( Node *ret ) { + idealreg2regmask[Op_RegP] = &spillP->out_RegMask(); + + // Vector regmasks. ++ if (Matcher::supports_scalable_vector()) { ++ MachNode *spillVectA = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTA)); ++ idealreg2regmask[Op_VecA] = &spillVectA->out_RegMask(); ++ } + if (Matcher::vector_size_supported(T_BYTE,4)) { + TypeVect::VECTS = TypeVect::make(T_BYTE, 4); + MachNode *spillVectS = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTS)); +@@ -1575,7 +1611,6 @@ Node* Matcher::Label_Root(const Node* n, State* svec, Node* control, Node*& mem) + } + } + +- + // Call DFA to match this node, and return + svec->DFA( n->Opcode(), n ); + +diff --git a/src/hotspot/share/opto/matcher.hpp b/src/hotspot/share/opto/matcher.hpp +index 244e3d1f8..ed890f88e 100644 +--- a/src/hotspot/share/opto/matcher.hpp ++++ b/src/hotspot/share/opto/matcher.hpp +@@ -333,6 +333,10 @@ public: + Matcher::min_vector_size(bt) <= size); + } + ++ static const bool supports_scalable_vector(); ++ // Actual max scalable vector register length. ++ static const int scalable_vector_reg_size(const BasicType bt); ++ + // Vector ideal reg + static const uint vector_ideal_reg(int len); + static const uint vector_shift_count_ideal_reg(int len); +diff --git a/src/hotspot/share/opto/opcodes.cpp b/src/hotspot/share/opto/opcodes.cpp +index e31e8d847..1a826d8ba 100644 +--- a/src/hotspot/share/opto/opcodes.cpp ++++ b/src/hotspot/share/opto/opcodes.cpp +@@ -1,5 +1,5 @@ + /* +- * Copyright (c) 1998, 2012, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 1998, 2020, Oracle and/or its affiliates. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it +@@ -38,12 +38,14 @@ const char *NodeClassNames[] = { + "RegF", + "RegD", + "RegL", +- "RegFlags", ++ "VecA", + "VecS", + "VecD", + "VecX", + "VecY", + "VecZ", ++ "RegVMask", ++ "RegFlags", + "_last_machine_leaf", + #include "classes.hpp" + "_last_class_name", +diff --git a/src/hotspot/share/opto/opcodes.hpp b/src/hotspot/share/opto/opcodes.hpp +index ae3d61ce0..ec96ba055 100644 +--- a/src/hotspot/share/opto/opcodes.hpp ++++ b/src/hotspot/share/opto/opcodes.hpp +@@ -1,5 +1,5 @@ + /* +- * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it +@@ -37,11 +37,13 @@ enum Opcodes { + macro(RegF) // Machine float register + macro(RegD) // Machine double register + macro(RegL) // Machine long register ++ macro(VecA) // Machine vectora register + macro(VecS) // Machine vectors register + macro(VecD) // Machine vectord register + macro(VecX) // Machine vectorx register + macro(VecY) // Machine vectory register + macro(VecZ) // Machine vectorz register ++ macro(RegVMask) // Vector mask/predicate register + macro(RegFlags) // Machine flags register + _last_machine_leaf, // Split between regular opcodes and machine + #include "classes.hpp" +diff --git a/src/hotspot/share/opto/postaloc.cpp b/src/hotspot/share/opto/postaloc.cpp +index d572ac9fe..3514b37bc 100644 +--- a/src/hotspot/share/opto/postaloc.cpp ++++ b/src/hotspot/share/opto/postaloc.cpp +@@ -1,5 +1,5 @@ + /* +- * Copyright (c) 1998, 2016, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 1998, 2020, Oracle and/or its affiliates. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it +@@ -266,9 +266,9 @@ int PhaseChaitin::elide_copy( Node *n, int k, Block *current_block, Node_List &v + Node *val = skip_copies(n->in(k)); + if (val == x) return blk_adjust; // No progress? + +- int n_regs = RegMask::num_registers(val->ideal_reg()); + uint val_idx = _lrg_map.live_range_id(val); + OptoReg::Name val_reg = lrgs(val_idx).reg(); ++ int n_regs = RegMask::num_registers(val->ideal_reg(), lrgs(val_idx)); + + // See if it happens to already be in the correct register! + // (either Phi's direct register, or the common case of the name +@@ -305,8 +305,26 @@ int PhaseChaitin::elide_copy( Node *n, int k, Block *current_block, Node_List &v + } + + Node *vv = value[reg]; ++ // For scalable register, number of registers may be inconsistent between ++ // "val_reg" and "reg". For example, when "val" resides in register ++ // but "reg" is located in stack. ++ if (lrgs(val_idx).is_scalable()) { ++ assert(val->ideal_reg() == Op_VecA, "scalable vector register"); ++ if (OptoReg::is_stack(reg)) { ++ n_regs = lrgs(val_idx).scalable_reg_slots(); ++ } else { ++ n_regs = RegMask::SlotsPerVecA; ++ } ++ } + if (n_regs > 1) { // Doubles and vectors check for aligned-adjacent set +- uint last = (n_regs-1); // Looking for the last part of a set ++ uint last; ++ if (lrgs(val_idx).is_scalable()) { ++ assert(val->ideal_reg() == Op_VecA, "scalable vector register"); ++ // For scalable vector register, regmask is always SlotsPerVecA bits aligned ++ last = RegMask::SlotsPerVecA - 1; ++ } else { ++ last = (n_regs-1); // Looking for the last part of a set ++ } + if ((reg&last) != last) continue; // Wrong part of a set + if (!register_contains_value(vv, reg, n_regs, value)) continue; // Different value + } +@@ -591,7 +609,7 @@ void PhaseChaitin::post_allocate_copy_removal() { + uint k; + Node *phi = block->get_node(j); + uint pidx = _lrg_map.live_range_id(phi); +- OptoReg::Name preg = lrgs(_lrg_map.live_range_id(phi)).reg(); ++ OptoReg::Name preg = lrgs(pidx).reg(); + + // Remove copies remaining on edges. Check for junk phi. + Node *u = NULL; +@@ -619,7 +637,7 @@ void PhaseChaitin::post_allocate_copy_removal() { + if( pidx ) { + value.map(preg,phi); + regnd.map(preg,phi); +- int n_regs = RegMask::num_registers(phi->ideal_reg()); ++ int n_regs = RegMask::num_registers(phi->ideal_reg(), lrgs(pidx)); + for (int l = 1; l < n_regs; l++) { + OptoReg::Name preg_lo = OptoReg::add(preg,-l); + value.map(preg_lo,phi); +@@ -663,7 +681,7 @@ void PhaseChaitin::post_allocate_copy_removal() { + regnd.map(ureg, def); + // Record other half of doubles + uint def_ideal_reg = def->ideal_reg(); +- int n_regs = RegMask::num_registers(def_ideal_reg); ++ int n_regs = RegMask::num_registers(def_ideal_reg, lrgs(_lrg_map.live_range_id(def))); + for (int l = 1; l < n_regs; l++) { + OptoReg::Name ureg_lo = OptoReg::add(ureg,-l); + if (!value[ureg_lo] && +@@ -707,7 +725,7 @@ void PhaseChaitin::post_allocate_copy_removal() { + } + + uint n_ideal_reg = n->ideal_reg(); +- int n_regs = RegMask::num_registers(n_ideal_reg); ++ int n_regs = RegMask::num_registers(n_ideal_reg, lrgs(lidx)); + if (n_regs == 1) { + // If Node 'n' does not change the value mapped by the register, + // then 'n' is a useless copy. Do not update the register->node +diff --git a/src/hotspot/share/opto/regmask.cpp b/src/hotspot/share/opto/regmask.cpp +index 2e04c42eb..dd9b5476b 100644 +--- a/src/hotspot/share/opto/regmask.cpp ++++ b/src/hotspot/share/opto/regmask.cpp +@@ -1,5 +1,5 @@ + /* +- * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it +@@ -24,6 +24,7 @@ + + #include "precompiled.hpp" + #include "opto/ad.hpp" ++#include "opto/chaitin.hpp" + #include "opto/compile.hpp" + #include "opto/matcher.hpp" + #include "opto/node.hpp" +@@ -116,30 +117,47 @@ const RegMask RegMask::Empty( + + //============================================================================= + bool RegMask::is_vector(uint ireg) { +- return (ireg == Op_VecS || ireg == Op_VecD || ++ return (ireg == Op_VecA || ireg == Op_VecS || ireg == Op_VecD || + ireg == Op_VecX || ireg == Op_VecY || ireg == Op_VecZ ); + } + + int RegMask::num_registers(uint ireg) { + switch(ireg) { + case Op_VecZ: +- return 16; ++ return SlotsPerVecZ; + case Op_VecY: +- return 8; ++ return SlotsPerVecY; + case Op_VecX: +- return 4; ++ return SlotsPerVecX; + case Op_VecD: ++ return SlotsPerVecD; + case Op_RegD: + case Op_RegL: + #ifdef _LP64 + case Op_RegP: + #endif + return 2; ++ case Op_VecA: ++ assert(Matcher::supports_scalable_vector(), "does not support scalable vector"); ++ return SlotsPerVecA; + } + // Op_VecS and the rest ideal registers. + return 1; + } + ++int RegMask::num_registers(uint ireg, LRG &lrg) { ++ int n_regs = num_registers(ireg); ++ ++ // assigned is OptoReg which is selected by register allocator ++ OptoReg::Name assigned = lrg.reg(); ++ assert(OptoReg::is_valid(assigned), "should be valid opto register"); ++ ++ if (lrg.is_scalable() && OptoReg::is_stack(assigned)) { ++ n_regs = lrg.scalable_reg_slots(); ++ } ++ return n_regs; ++} ++ + //------------------------------find_first_pair-------------------------------- + // Find the lowest-numbered register pair in the mask. Return the + // HIGHEST register number in the pair, or BAD if no pairs. +@@ -238,14 +256,30 @@ int RegMask::is_bound_pair() const { + return true; + } + ++// Check that whether given reg number with size is valid ++// for current regmask, where reg is the highest number. ++bool RegMask::is_valid_reg(OptoReg::Name reg, const int size) const { ++ for (int i = 0; i < size; i++) { ++ if (!Member(reg - i)) { ++ return false; ++ } ++ } ++ return true; ++} ++ + // only indicies of power 2 are accessed, so index 3 is only filled in for storage. + static int low_bits[5] = { 0x55555555, 0x11111111, 0x01010101, 0x00000000, 0x00010001 }; + //------------------------------find_first_set--------------------------------- + // Find the lowest-numbered register set in the mask. Return the + // HIGHEST register number in the set, or BAD if no sets. + // Works also for size 1. +-OptoReg::Name RegMask::find_first_set(const int size) const { +- verify_sets(size); ++OptoReg::Name RegMask::find_first_set(LRG &lrg, const int size) const { ++ if (lrg.is_scalable()) { ++ // For scalable vector register, regmask is SlotsPerVecA bits aligned. ++ assert(is_aligned_sets(SlotsPerVecA), "mask is not aligned, adjacent sets"); ++ } else { ++ assert(is_aligned_sets(size), "mask is not aligned, adjacent sets"); ++ } + for (int i = 0; i < RM_SIZE; i++) { + if (_A[i]) { // Found some bits + int bit = _A[i] & -_A[i]; // Extract low bit +@@ -325,12 +359,16 @@ bool RegMask::is_aligned_sets(const int size) const { + while (bits) { // Check bits for pairing + int bit = bits & -bits; // Extract low bit + // Low bit is not odd means its mis-aligned. +- if ((bit & low_bits_mask) == 0) return false; ++ if ((bit & low_bits_mask) == 0) { ++ return false; ++ } + // Do extra work since (bit << size) may overflow. + int hi_bit = bit << (size-1); // high bit + int set = hi_bit + ((hi_bit-1) & ~(bit-1)); + // Check for aligned adjacent bits in this set +- if ((bits & set) != set) return false; ++ if ((bits & set) != set) { ++ return false; ++ } + bits -= set; // Remove this set + } + } +diff --git a/src/hotspot/share/opto/regmask.hpp b/src/hotspot/share/opto/regmask.hpp +index c64d08795..b733b87ad 100644 +--- a/src/hotspot/share/opto/regmask.hpp ++++ b/src/hotspot/share/opto/regmask.hpp +@@ -1,5 +1,5 @@ + /* +- * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it +@@ -28,6 +28,8 @@ + #include "code/vmreg.hpp" + #include "opto/optoreg.hpp" + ++class LRG; ++ + // Some fun naming (textual) substitutions: + // + // RegMask::get_low_elem() ==> RegMask::find_first_elem() +@@ -95,11 +97,13 @@ public: + // requirement is internal to the allocator, and independent of any + // particular platform. + enum { SlotsPerLong = 2, ++ SlotsPerVecA = 8, + SlotsPerVecS = 1, + SlotsPerVecD = 2, + SlotsPerVecX = 4, + SlotsPerVecY = 8, +- SlotsPerVecZ = 16 }; ++ SlotsPerVecZ = 16, ++ }; + + // A constructor only used by the ADLC output. All mask fields are filled + // in directly. Calls to this look something like RM(1,2,3,4); +@@ -204,10 +208,14 @@ public: + return false; + } + ++ // Check that whether given reg number with size is valid ++ // for current regmask, where reg is the highest number. ++ bool is_valid_reg(OptoReg::Name reg, const int size) const; ++ + // Find the lowest-numbered register set in the mask. Return the + // HIGHEST register number in the set, or BAD if no sets. + // Assert that the mask contains only bit sets. +- OptoReg::Name find_first_set(const int size) const; ++ OptoReg::Name find_first_set(LRG &lrg, const int size) const; + + // Clear out partial bits; leave only aligned adjacent bit sets of size. + void clear_to_sets(const int size); +@@ -226,6 +234,7 @@ public: + + static bool is_vector(uint ireg); + static int num_registers(uint ireg); ++ static int num_registers(uint ireg, LRG &lrg); + + // Fast overlap test. Non-zero if any registers in common. + int overlap( const RegMask &rm ) const { +diff --git a/src/hotspot/share/opto/type.cpp b/src/hotspot/share/opto/type.cpp +index 223b7a1c6..1b46cb452 100644 +--- a/src/hotspot/share/opto/type.cpp ++++ b/src/hotspot/share/opto/type.cpp +@@ -79,6 +79,7 @@ const Type::TypeInfo Type::_type_info[Type::lastype] = { + { Bad, T_ILLEGAL, "vectory:", false, 0, relocInfo::none }, // VectorY + { Bad, T_ILLEGAL, "vectorz:", false, 0, relocInfo::none }, // VectorZ + #else // all other ++ { Bad, T_ILLEGAL, "vectora:", false, Op_VecA, relocInfo::none }, // VectorA. + { Bad, T_ILLEGAL, "vectors:", false, Op_VecS, relocInfo::none }, // VectorS + { Bad, T_ILLEGAL, "vectord:", false, Op_VecD, relocInfo::none }, // VectorD + { Bad, T_ILLEGAL, "vectorx:", false, Op_VecX, relocInfo::none }, // VectorX +@@ -655,6 +656,10 @@ void Type::Initialize_shared(Compile* current) { + // get_zero_type() should not happen for T_CONFLICT + _zero_type[T_CONFLICT]= NULL; + ++ if (Matcher::supports_scalable_vector()) { ++ TypeVect::VECTA = TypeVect::make(T_BYTE, Matcher::scalable_vector_reg_size(T_BYTE)); ++ } ++ + // Vector predefined types, it needs initialized _const_basic_type[]. + if (Matcher::vector_size_supported(T_BYTE,4)) { + TypeVect::VECTS = TypeVect::make(T_BYTE,4); +@@ -671,6 +676,8 @@ void Type::Initialize_shared(Compile* current) { + if (Matcher::vector_size_supported(T_FLOAT,16)) { + TypeVect::VECTZ = TypeVect::make(T_FLOAT,16); + } ++ ++ mreg2type[Op_VecA] = TypeVect::VECTA; + mreg2type[Op_VecS] = TypeVect::VECTS; + mreg2type[Op_VecD] = TypeVect::VECTD; + mreg2type[Op_VecX] = TypeVect::VECTX; +@@ -990,6 +997,7 @@ const Type::TYPES Type::dual_type[Type::lastype] = { + + Bad, // Tuple - handled in v-call + Bad, // Array - handled in v-call ++ Bad, // VectorA - handled in v-call + Bad, // VectorS - handled in v-call + Bad, // VectorD - handled in v-call + Bad, // VectorX - handled in v-call +@@ -1890,7 +1898,6 @@ const TypeTuple *TypeTuple::LONG_PAIR; + const TypeTuple *TypeTuple::INT_CC_PAIR; + const TypeTuple *TypeTuple::LONG_CC_PAIR; + +- + //------------------------------make------------------------------------------- + // Make a TypeTuple from the range of a method signature + const TypeTuple *TypeTuple::make_range(ciSignature* sig) { +@@ -2262,6 +2269,7 @@ bool TypeAry::ary_must_be_exact() const { + + //==============================TypeVect======================================= + // Convenience common pre-built types. ++const TypeVect *TypeVect::VECTA = NULL; // vector length agnostic + const TypeVect *TypeVect::VECTS = NULL; // 32-bit vectors + const TypeVect *TypeVect::VECTD = NULL; // 64-bit vectors + const TypeVect *TypeVect::VECTX = NULL; // 128-bit vectors +@@ -2272,10 +2280,11 @@ const TypeVect *TypeVect::VECTZ = NULL; // 512-bit vectors + const TypeVect* TypeVect::make(const Type *elem, uint length) { + BasicType elem_bt = elem->array_element_basic_type(); + assert(is_java_primitive(elem_bt), "only primitive types in vector"); +- assert(length > 1 && is_power_of_2(length), "vector length is power of 2"); + assert(Matcher::vector_size_supported(elem_bt, length), "length in range"); + int size = length * type2aelembytes(elem_bt); + switch (Matcher::vector_ideal_reg(size)) { ++ case Op_VecA: ++ return (TypeVect*)(new TypeVectA(elem, length))->hashcons(); + case Op_VecS: + return (TypeVect*)(new TypeVectS(elem, length))->hashcons(); + case Op_RegL: +@@ -2307,7 +2316,7 @@ const Type *TypeVect::xmeet( const Type *t ) const { + + default: // All else is a mistake + typerr(t); +- ++ case VectorA: + case VectorS: + case VectorD: + case VectorX: +@@ -2362,6 +2371,8 @@ bool TypeVect::empty(void) const { + #ifndef PRODUCT + void TypeVect::dump2(Dict &d, uint depth, outputStream *st) const { + switch (base()) { ++ case VectorA: ++ st->print("vectora["); break; + case VectorS: + st->print("vectors["); break; + case VectorD: +diff --git a/src/hotspot/share/opto/type.hpp b/src/hotspot/share/opto/type.hpp +index a7eec281e..6787b947d 100644 +--- a/src/hotspot/share/opto/type.hpp ++++ b/src/hotspot/share/opto/type.hpp +@@ -1,5 +1,5 @@ + /* +- * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it +@@ -53,6 +53,7 @@ class TypeNarrowKlass; + class TypeAry; + class TypeTuple; + class TypeVect; ++class TypeVectA; + class TypeVectS; + class TypeVectD; + class TypeVectX; +@@ -87,6 +88,7 @@ public: + + Tuple, // Method signature or object layout + Array, // Array types ++ VectorA, // (Scalable) Vector types for vector length agnostic + VectorS, // 32bit Vector types + VectorD, // 64bit Vector types + VectorX, // 128bit Vector types +@@ -758,6 +760,7 @@ public: + virtual const Type *xmeet( const Type *t) const; + virtual const Type *xdual() const; // Compute dual right now. + ++ static const TypeVect *VECTA; + static const TypeVect *VECTS; + static const TypeVect *VECTD; + static const TypeVect *VECTX; +@@ -769,6 +772,11 @@ public: + #endif + }; + ++class TypeVectA : public TypeVect { ++ friend class TypeVect; ++ TypeVectA(const Type* elem, uint length) : TypeVect(VectorA, elem, length) {} ++}; ++ + class TypeVectS : public TypeVect { + friend class TypeVect; + TypeVectS(const Type* elem, uint length) : TypeVect(VectorS, elem, length) {} +@@ -1619,12 +1627,12 @@ inline const TypeAry *Type::is_ary() const { + } + + inline const TypeVect *Type::is_vect() const { +- assert( _base >= VectorS && _base <= VectorZ, "Not a Vector" ); ++ assert( _base >= VectorA && _base <= VectorZ, "Not a Vector" ); + return (TypeVect*)this; + } + + inline const TypeVect *Type::isa_vect() const { +- return (_base >= VectorS && _base <= VectorZ) ? (TypeVect*)this : NULL; ++ return (_base >= VectorA && _base <= VectorZ) ? (TypeVect*)this : NULL; + } + + inline const TypePtr *Type::is_ptr() const { +-- +2.19.1 + diff --git a/add-SVE-backend-feature.patch b/8231441-3-AArch64-Initial-SVE-backend-support.patch old mode 100644 new mode 100755 similarity index 34% rename from add-SVE-backend-feature.patch rename to 8231441-3-AArch64-Initial-SVE-backend-support.patch index 04283774f163e36ac1a12a4e26d43477328c5828..b6bbacb1e4cdbd447bbaeb86811a1774dfb5556c --- a/add-SVE-backend-feature.patch +++ b/8231441-3-AArch64-Initial-SVE-backend-support.patch @@ -16,688 +16,10 @@ index a39640526..2479853fa 100644 AD_SRC_FILES += $(call uniq, $(wildcard $(foreach d, $(AD_SRC_ROOTS), \ $d/cpu/$(HOTSPOT_TARGET_CPU_ARCH)/gc/shenandoah/shenandoah_$(HOTSPOT_TARGET_CPU).ad \ diff --git a/src/hotspot/cpu/aarch64/aarch64.ad b/src/hotspot/cpu/aarch64/aarch64.ad -index b64919a62..fa434df7d 100644 +index 64985e498..fa434df7d 100644 --- a/src/hotspot/cpu/aarch64/aarch64.ad +++ b/src/hotspot/cpu/aarch64/aarch64.ad -@@ -69,7 +69,7 @@ register %{ - // - // r0-r7,r10-r26 volatile (caller save) - // r27-r32 system (no save, no allocate) --// r8-r9 invisible to the allocator (so we can use them as scratch regs) -+// r8-r9 non-allocatable (so we can use them as scratch regs) - // - // as regards Java usage. we don't use any callee save registers - // because this makes it difficult to de-optimise a frame (see comment -@@ -94,6 +94,10 @@ reg_def R6 ( SOC, SOC, Op_RegI, 6, r6->as_VMReg() ); - reg_def R6_H ( SOC, SOC, Op_RegI, 6, r6->as_VMReg()->next() ); - reg_def R7 ( SOC, SOC, Op_RegI, 7, r7->as_VMReg() ); - reg_def R7_H ( SOC, SOC, Op_RegI, 7, r7->as_VMReg()->next() ); -+reg_def R8 ( NS, SOC, Op_RegI, 8, r8->as_VMReg() ); // rscratch1, non-allocatable -+reg_def R8_H ( NS, SOC, Op_RegI, 8, r8->as_VMReg()->next() ); -+reg_def R9 ( NS, SOC, Op_RegI, 9, r9->as_VMReg() ); // rscratch2, non-allocatable -+reg_def R9_H ( NS, SOC, Op_RegI, 9, r9->as_VMReg()->next() ); - reg_def R10 ( SOC, SOC, Op_RegI, 10, r10->as_VMReg() ); - reg_def R10_H ( SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next()); - reg_def R11 ( SOC, SOC, Op_RegI, 11, r11->as_VMReg() ); -@@ -140,7 +144,7 @@ reg_def R31 ( NS, NS, Op_RegI, 31, r31_sp->as_VMReg() ); // sp - reg_def R31_H ( NS, NS, Op_RegI, 31, r31_sp->as_VMReg()->next()); - - // ---------------------------- --// Float/Double Registers -+// Float/Double/Vector Registers - // ---------------------------- - - // Double Registers -@@ -161,165 +165,316 @@ reg_def R31_H ( NS, NS, Op_RegI, 31, r31_sp->as_VMReg()->next()); - // the platform ABI treats v8-v15 as callee save). float registers - // v16-v31 are SOC as per the platform spec - -- reg_def V0 ( SOC, SOC, Op_RegF, 0, v0->as_VMReg() ); -- reg_def V0_H ( SOC, SOC, Op_RegF, 0, v0->as_VMReg()->next() ); -- reg_def V0_J ( SOC, SOC, Op_RegF, 0, v0->as_VMReg()->next(2) ); -- reg_def V0_K ( SOC, SOC, Op_RegF, 0, v0->as_VMReg()->next(3) ); -- -- reg_def V1 ( SOC, SOC, Op_RegF, 1, v1->as_VMReg() ); -- reg_def V1_H ( SOC, SOC, Op_RegF, 1, v1->as_VMReg()->next() ); -- reg_def V1_J ( SOC, SOC, Op_RegF, 1, v1->as_VMReg()->next(2) ); -- reg_def V1_K ( SOC, SOC, Op_RegF, 1, v1->as_VMReg()->next(3) ); -- -- reg_def V2 ( SOC, SOC, Op_RegF, 2, v2->as_VMReg() ); -- reg_def V2_H ( SOC, SOC, Op_RegF, 2, v2->as_VMReg()->next() ); -- reg_def V2_J ( SOC, SOC, Op_RegF, 2, v2->as_VMReg()->next(2) ); -- reg_def V2_K ( SOC, SOC, Op_RegF, 2, v2->as_VMReg()->next(3) ); -- -- reg_def V3 ( SOC, SOC, Op_RegF, 3, v3->as_VMReg() ); -- reg_def V3_H ( SOC, SOC, Op_RegF, 3, v3->as_VMReg()->next() ); -- reg_def V3_J ( SOC, SOC, Op_RegF, 3, v3->as_VMReg()->next(2) ); -- reg_def V3_K ( SOC, SOC, Op_RegF, 3, v3->as_VMReg()->next(3) ); -- -- reg_def V4 ( SOC, SOC, Op_RegF, 4, v4->as_VMReg() ); -- reg_def V4_H ( SOC, SOC, Op_RegF, 4, v4->as_VMReg()->next() ); -- reg_def V4_J ( SOC, SOC, Op_RegF, 4, v4->as_VMReg()->next(2) ); -- reg_def V4_K ( SOC, SOC, Op_RegF, 4, v4->as_VMReg()->next(3) ); -- -- reg_def V5 ( SOC, SOC, Op_RegF, 5, v5->as_VMReg() ); -- reg_def V5_H ( SOC, SOC, Op_RegF, 5, v5->as_VMReg()->next() ); -- reg_def V5_J ( SOC, SOC, Op_RegF, 5, v5->as_VMReg()->next(2) ); -- reg_def V5_K ( SOC, SOC, Op_RegF, 5, v5->as_VMReg()->next(3) ); -- -- reg_def V6 ( SOC, SOC, Op_RegF, 6, v6->as_VMReg() ); -- reg_def V6_H ( SOC, SOC, Op_RegF, 6, v6->as_VMReg()->next() ); -- reg_def V6_J ( SOC, SOC, Op_RegF, 6, v6->as_VMReg()->next(2) ); -- reg_def V6_K ( SOC, SOC, Op_RegF, 6, v6->as_VMReg()->next(3) ); -- -- reg_def V7 ( SOC, SOC, Op_RegF, 7, v7->as_VMReg() ); -- reg_def V7_H ( SOC, SOC, Op_RegF, 7, v7->as_VMReg()->next() ); -- reg_def V7_J ( SOC, SOC, Op_RegF, 7, v7->as_VMReg()->next(2) ); -- reg_def V7_K ( SOC, SOC, Op_RegF, 7, v7->as_VMReg()->next(3) ); -- -- reg_def V8 ( SOC, SOE, Op_RegF, 8, v8->as_VMReg() ); -- reg_def V8_H ( SOC, SOE, Op_RegF, 8, v8->as_VMReg()->next() ); -- reg_def V8_J ( SOC, SOC, Op_RegF, 8, v8->as_VMReg()->next(2) ); -- reg_def V8_K ( SOC, SOC, Op_RegF, 8, v8->as_VMReg()->next(3) ); -- -- reg_def V9 ( SOC, SOE, Op_RegF, 9, v9->as_VMReg() ); -- reg_def V9_H ( SOC, SOE, Op_RegF, 9, v9->as_VMReg()->next() ); -- reg_def V9_J ( SOC, SOC, Op_RegF, 9, v9->as_VMReg()->next(2) ); -- reg_def V9_K ( SOC, SOC, Op_RegF, 9, v9->as_VMReg()->next(3) ); -- -- reg_def V10 ( SOC, SOE, Op_RegF, 10, v10->as_VMReg() ); -- reg_def V10_H( SOC, SOE, Op_RegF, 10, v10->as_VMReg()->next() ); -- reg_def V10_J( SOC, SOC, Op_RegF, 10, v10->as_VMReg()->next(2)); -- reg_def V10_K( SOC, SOC, Op_RegF, 10, v10->as_VMReg()->next(3)); -- -- reg_def V11 ( SOC, SOE, Op_RegF, 11, v11->as_VMReg() ); -- reg_def V11_H( SOC, SOE, Op_RegF, 11, v11->as_VMReg()->next() ); -- reg_def V11_J( SOC, SOC, Op_RegF, 11, v11->as_VMReg()->next(2)); -- reg_def V11_K( SOC, SOC, Op_RegF, 11, v11->as_VMReg()->next(3)); -- -- reg_def V12 ( SOC, SOE, Op_RegF, 12, v12->as_VMReg() ); -- reg_def V12_H( SOC, SOE, Op_RegF, 12, v12->as_VMReg()->next() ); -- reg_def V12_J( SOC, SOC, Op_RegF, 12, v12->as_VMReg()->next(2)); -- reg_def V12_K( SOC, SOC, Op_RegF, 12, v12->as_VMReg()->next(3)); -- -- reg_def V13 ( SOC, SOE, Op_RegF, 13, v13->as_VMReg() ); -- reg_def V13_H( SOC, SOE, Op_RegF, 13, v13->as_VMReg()->next() ); -- reg_def V13_J( SOC, SOC, Op_RegF, 13, v13->as_VMReg()->next(2)); -- reg_def V13_K( SOC, SOC, Op_RegF, 13, v13->as_VMReg()->next(3)); -- -- reg_def V14 ( SOC, SOE, Op_RegF, 14, v14->as_VMReg() ); -- reg_def V14_H( SOC, SOE, Op_RegF, 14, v14->as_VMReg()->next() ); -- reg_def V14_J( SOC, SOC, Op_RegF, 14, v14->as_VMReg()->next(2)); -- reg_def V14_K( SOC, SOC, Op_RegF, 14, v14->as_VMReg()->next(3)); -- -- reg_def V15 ( SOC, SOE, Op_RegF, 15, v15->as_VMReg() ); -- reg_def V15_H( SOC, SOE, Op_RegF, 15, v15->as_VMReg()->next() ); -- reg_def V15_J( SOC, SOC, Op_RegF, 15, v15->as_VMReg()->next(2)); -- reg_def V15_K( SOC, SOC, Op_RegF, 15, v15->as_VMReg()->next(3)); -- -- reg_def V16 ( SOC, SOC, Op_RegF, 16, v16->as_VMReg() ); -- reg_def V16_H( SOC, SOC, Op_RegF, 16, v16->as_VMReg()->next() ); -- reg_def V16_J( SOC, SOC, Op_RegF, 16, v16->as_VMReg()->next(2)); -- reg_def V16_K( SOC, SOC, Op_RegF, 16, v16->as_VMReg()->next(3)); -- -- reg_def V17 ( SOC, SOC, Op_RegF, 17, v17->as_VMReg() ); -- reg_def V17_H( SOC, SOC, Op_RegF, 17, v17->as_VMReg()->next() ); -- reg_def V17_J( SOC, SOC, Op_RegF, 17, v17->as_VMReg()->next(2)); -- reg_def V17_K( SOC, SOC, Op_RegF, 17, v17->as_VMReg()->next(3)); -- -- reg_def V18 ( SOC, SOC, Op_RegF, 18, v18->as_VMReg() ); -- reg_def V18_H( SOC, SOC, Op_RegF, 18, v18->as_VMReg()->next() ); -- reg_def V18_J( SOC, SOC, Op_RegF, 18, v18->as_VMReg()->next(2)); -- reg_def V18_K( SOC, SOC, Op_RegF, 18, v18->as_VMReg()->next(3)); -- -- reg_def V19 ( SOC, SOC, Op_RegF, 19, v19->as_VMReg() ); -- reg_def V19_H( SOC, SOC, Op_RegF, 19, v19->as_VMReg()->next() ); -- reg_def V19_J( SOC, SOC, Op_RegF, 19, v19->as_VMReg()->next(2)); -- reg_def V19_K( SOC, SOC, Op_RegF, 19, v19->as_VMReg()->next(3)); -- -- reg_def V20 ( SOC, SOC, Op_RegF, 20, v20->as_VMReg() ); -- reg_def V20_H( SOC, SOC, Op_RegF, 20, v20->as_VMReg()->next() ); -- reg_def V20_J( SOC, SOC, Op_RegF, 20, v20->as_VMReg()->next(2)); -- reg_def V20_K( SOC, SOC, Op_RegF, 20, v20->as_VMReg()->next(3)); -- -- reg_def V21 ( SOC, SOC, Op_RegF, 21, v21->as_VMReg() ); -- reg_def V21_H( SOC, SOC, Op_RegF, 21, v21->as_VMReg()->next() ); -- reg_def V21_J( SOC, SOC, Op_RegF, 21, v21->as_VMReg()->next(2)); -- reg_def V21_K( SOC, SOC, Op_RegF, 21, v21->as_VMReg()->next(3)); -- -- reg_def V22 ( SOC, SOC, Op_RegF, 22, v22->as_VMReg() ); -- reg_def V22_H( SOC, SOC, Op_RegF, 22, v22->as_VMReg()->next() ); -- reg_def V22_J( SOC, SOC, Op_RegF, 22, v22->as_VMReg()->next(2)); -- reg_def V22_K( SOC, SOC, Op_RegF, 22, v22->as_VMReg()->next(3)); -- -- reg_def V23 ( SOC, SOC, Op_RegF, 23, v23->as_VMReg() ); -- reg_def V23_H( SOC, SOC, Op_RegF, 23, v23->as_VMReg()->next() ); -- reg_def V23_J( SOC, SOC, Op_RegF, 23, v23->as_VMReg()->next(2)); -- reg_def V23_K( SOC, SOC, Op_RegF, 23, v23->as_VMReg()->next(3)); -- -- reg_def V24 ( SOC, SOC, Op_RegF, 24, v24->as_VMReg() ); -- reg_def V24_H( SOC, SOC, Op_RegF, 24, v24->as_VMReg()->next() ); -- reg_def V24_J( SOC, SOC, Op_RegF, 24, v24->as_VMReg()->next(2)); -- reg_def V24_K( SOC, SOC, Op_RegF, 24, v24->as_VMReg()->next(3)); -- -- reg_def V25 ( SOC, SOC, Op_RegF, 25, v25->as_VMReg() ); -- reg_def V25_H( SOC, SOC, Op_RegF, 25, v25->as_VMReg()->next() ); -- reg_def V25_J( SOC, SOC, Op_RegF, 25, v25->as_VMReg()->next(2)); -- reg_def V25_K( SOC, SOC, Op_RegF, 25, v25->as_VMReg()->next(3)); -- -- reg_def V26 ( SOC, SOC, Op_RegF, 26, v26->as_VMReg() ); -- reg_def V26_H( SOC, SOC, Op_RegF, 26, v26->as_VMReg()->next() ); -- reg_def V26_J( SOC, SOC, Op_RegF, 26, v26->as_VMReg()->next(2)); -- reg_def V26_K( SOC, SOC, Op_RegF, 26, v26->as_VMReg()->next(3)); -- -- reg_def V27 ( SOC, SOC, Op_RegF, 27, v27->as_VMReg() ); -- reg_def V27_H( SOC, SOC, Op_RegF, 27, v27->as_VMReg()->next() ); -- reg_def V27_J( SOC, SOC, Op_RegF, 27, v27->as_VMReg()->next(2)); -- reg_def V27_K( SOC, SOC, Op_RegF, 27, v27->as_VMReg()->next(3)); -- -- reg_def V28 ( SOC, SOC, Op_RegF, 28, v28->as_VMReg() ); -- reg_def V28_H( SOC, SOC, Op_RegF, 28, v28->as_VMReg()->next() ); -- reg_def V28_J( SOC, SOC, Op_RegF, 28, v28->as_VMReg()->next(2)); -- reg_def V28_K( SOC, SOC, Op_RegF, 28, v28->as_VMReg()->next(3)); -- -- reg_def V29 ( SOC, SOC, Op_RegF, 29, v29->as_VMReg() ); -- reg_def V29_H( SOC, SOC, Op_RegF, 29, v29->as_VMReg()->next() ); -- reg_def V29_J( SOC, SOC, Op_RegF, 29, v29->as_VMReg()->next(2)); -- reg_def V29_K( SOC, SOC, Op_RegF, 29, v29->as_VMReg()->next(3)); -- -- reg_def V30 ( SOC, SOC, Op_RegF, 30, v30->as_VMReg() ); -- reg_def V30_H( SOC, SOC, Op_RegF, 30, v30->as_VMReg()->next() ); -- reg_def V30_J( SOC, SOC, Op_RegF, 30, v30->as_VMReg()->next(2)); -- reg_def V30_K( SOC, SOC, Op_RegF, 30, v30->as_VMReg()->next(3)); -- -- reg_def V31 ( SOC, SOC, Op_RegF, 31, v31->as_VMReg() ); -- reg_def V31_H( SOC, SOC, Op_RegF, 31, v31->as_VMReg()->next() ); -- reg_def V31_J( SOC, SOC, Op_RegF, 31, v31->as_VMReg()->next(2)); -- reg_def V31_K( SOC, SOC, Op_RegF, 31, v31->as_VMReg()->next(3)); -+// For SVE vector registers, we simply extend vector register size to 8 -+// 'logical' slots. This is nominally 256 bits but it actually covers -+// all possible 'physical' SVE vector register lengths from 128 ~ 2048 -+// bits. The 'physical' SVE vector register length is detected during -+// startup, so the register allocator is able to identify the correct -+// number of bytes needed for an SVE spill/unspill. -+// Note that a vector register with 4 slots denotes a 128-bit NEON -+// register allowing it to be distinguished from the corresponding SVE -+// vector register when the SVE vector length is 128 bits. -+ -+ reg_def V0 ( SOC, SOC, Op_RegF, 0, v0->as_VMReg() ); -+ reg_def V0_H ( SOC, SOC, Op_RegF, 0, v0->as_VMReg()->next() ); -+ reg_def V0_J ( SOC, SOC, Op_RegF, 0, v0->as_VMReg()->next(2) ); -+ reg_def V0_K ( SOC, SOC, Op_RegF, 0, v0->as_VMReg()->next(3) ); -+ reg_def V0_L ( SOC, SOC, Op_RegF, 0, v0->as_VMReg()->next(4) ); -+ reg_def V0_M ( SOC, SOC, Op_RegF, 0, v0->as_VMReg()->next(5) ); -+ reg_def V0_N ( SOC, SOC, Op_RegF, 0, v0->as_VMReg()->next(6) ); -+ reg_def V0_O ( SOC, SOC, Op_RegF, 0, v0->as_VMReg()->next(7) ); -+ -+ reg_def V1 ( SOC, SOC, Op_RegF, 1, v1->as_VMReg() ); -+ reg_def V1_H ( SOC, SOC, Op_RegF, 1, v1->as_VMReg()->next() ); -+ reg_def V1_J ( SOC, SOC, Op_RegF, 1, v1->as_VMReg()->next(2) ); -+ reg_def V1_K ( SOC, SOC, Op_RegF, 1, v1->as_VMReg()->next(3) ); -+ reg_def V1_L ( SOC, SOC, Op_RegF, 1, v1->as_VMReg()->next(4) ); -+ reg_def V1_M ( SOC, SOC, Op_RegF, 1, v1->as_VMReg()->next(5) ); -+ reg_def V1_N ( SOC, SOC, Op_RegF, 1, v1->as_VMReg()->next(6) ); -+ reg_def V1_O ( SOC, SOC, Op_RegF, 1, v1->as_VMReg()->next(7) ); -+ -+ reg_def V2 ( SOC, SOC, Op_RegF, 2, v2->as_VMReg() ); -+ reg_def V2_H ( SOC, SOC, Op_RegF, 2, v2->as_VMReg()->next() ); -+ reg_def V2_J ( SOC, SOC, Op_RegF, 2, v2->as_VMReg()->next(2) ); -+ reg_def V2_K ( SOC, SOC, Op_RegF, 2, v2->as_VMReg()->next(3) ); -+ reg_def V2_L ( SOC, SOC, Op_RegF, 2, v2->as_VMReg()->next(4) ); -+ reg_def V2_M ( SOC, SOC, Op_RegF, 2, v2->as_VMReg()->next(5) ); -+ reg_def V2_N ( SOC, SOC, Op_RegF, 2, v2->as_VMReg()->next(6) ); -+ reg_def V2_O ( SOC, SOC, Op_RegF, 2, v2->as_VMReg()->next(7) ); -+ -+ reg_def V3 ( SOC, SOC, Op_RegF, 3, v3->as_VMReg() ); -+ reg_def V3_H ( SOC, SOC, Op_RegF, 3, v3->as_VMReg()->next() ); -+ reg_def V3_J ( SOC, SOC, Op_RegF, 3, v3->as_VMReg()->next(2) ); -+ reg_def V3_K ( SOC, SOC, Op_RegF, 3, v3->as_VMReg()->next(3) ); -+ reg_def V3_L ( SOC, SOC, Op_RegF, 3, v3->as_VMReg()->next(4) ); -+ reg_def V3_M ( SOC, SOC, Op_RegF, 3, v3->as_VMReg()->next(5) ); -+ reg_def V3_N ( SOC, SOC, Op_RegF, 3, v3->as_VMReg()->next(6) ); -+ reg_def V3_O ( SOC, SOC, Op_RegF, 3, v3->as_VMReg()->next(7) ); -+ -+ reg_def V4 ( SOC, SOC, Op_RegF, 4, v4->as_VMReg() ); -+ reg_def V4_H ( SOC, SOC, Op_RegF, 4, v4->as_VMReg()->next() ); -+ reg_def V4_J ( SOC, SOC, Op_RegF, 4, v4->as_VMReg()->next(2) ); -+ reg_def V4_K ( SOC, SOC, Op_RegF, 4, v4->as_VMReg()->next(3) ); -+ reg_def V4_L ( SOC, SOC, Op_RegF, 4, v4->as_VMReg()->next(4) ); -+ reg_def V4_M ( SOC, SOC, Op_RegF, 4, v4->as_VMReg()->next(5) ); -+ reg_def V4_N ( SOC, SOC, Op_RegF, 4, v4->as_VMReg()->next(6) ); -+ reg_def V4_O ( SOC, SOC, Op_RegF, 4, v4->as_VMReg()->next(7) ); -+ -+ reg_def V5 ( SOC, SOC, Op_RegF, 5, v5->as_VMReg() ); -+ reg_def V5_H ( SOC, SOC, Op_RegF, 5, v5->as_VMReg()->next() ); -+ reg_def V5_J ( SOC, SOC, Op_RegF, 5, v5->as_VMReg()->next(2) ); -+ reg_def V5_K ( SOC, SOC, Op_RegF, 5, v5->as_VMReg()->next(3) ); -+ reg_def V5_L ( SOC, SOC, Op_RegF, 5, v5->as_VMReg()->next(4) ); -+ reg_def V5_M ( SOC, SOC, Op_RegF, 5, v5->as_VMReg()->next(5) ); -+ reg_def V5_N ( SOC, SOC, Op_RegF, 5, v5->as_VMReg()->next(6) ); -+ reg_def V5_O ( SOC, SOC, Op_RegF, 5, v5->as_VMReg()->next(7) ); -+ -+ reg_def V6 ( SOC, SOC, Op_RegF, 6, v6->as_VMReg() ); -+ reg_def V6_H ( SOC, SOC, Op_RegF, 6, v6->as_VMReg()->next() ); -+ reg_def V6_J ( SOC, SOC, Op_RegF, 6, v6->as_VMReg()->next(2) ); -+ reg_def V6_K ( SOC, SOC, Op_RegF, 6, v6->as_VMReg()->next(3) ); -+ reg_def V6_L ( SOC, SOC, Op_RegF, 6, v6->as_VMReg()->next(4) ); -+ reg_def V6_M ( SOC, SOC, Op_RegF, 6, v6->as_VMReg()->next(5) ); -+ reg_def V6_N ( SOC, SOC, Op_RegF, 6, v6->as_VMReg()->next(6) ); -+ reg_def V6_O ( SOC, SOC, Op_RegF, 6, v6->as_VMReg()->next(7) ); -+ -+ reg_def V7 ( SOC, SOC, Op_RegF, 7, v7->as_VMReg() ); -+ reg_def V7_H ( SOC, SOC, Op_RegF, 7, v7->as_VMReg()->next() ); -+ reg_def V7_J ( SOC, SOC, Op_RegF, 7, v7->as_VMReg()->next(2) ); -+ reg_def V7_K ( SOC, SOC, Op_RegF, 7, v7->as_VMReg()->next(3) ); -+ reg_def V7_L ( SOC, SOC, Op_RegF, 7, v7->as_VMReg()->next(4) ); -+ reg_def V7_M ( SOC, SOC, Op_RegF, 7, v7->as_VMReg()->next(5) ); -+ reg_def V7_N ( SOC, SOC, Op_RegF, 7, v7->as_VMReg()->next(6) ); -+ reg_def V7_O ( SOC, SOC, Op_RegF, 7, v7->as_VMReg()->next(7) ); -+ -+ reg_def V8 ( SOC, SOE, Op_RegF, 8, v8->as_VMReg() ); -+ reg_def V8_H ( SOC, SOE, Op_RegF, 8, v8->as_VMReg()->next() ); -+ reg_def V8_J ( SOC, SOC, Op_RegF, 8, v8->as_VMReg()->next(2) ); -+ reg_def V8_K ( SOC, SOC, Op_RegF, 8, v8->as_VMReg()->next(3) ); -+ reg_def V8_L ( SOC, SOC, Op_RegF, 8, v8->as_VMReg()->next(4) ); -+ reg_def V8_M ( SOC, SOC, Op_RegF, 8, v8->as_VMReg()->next(5) ); -+ reg_def V8_N ( SOC, SOC, Op_RegF, 8, v8->as_VMReg()->next(6) ); -+ reg_def V8_O ( SOC, SOC, Op_RegF, 8, v8->as_VMReg()->next(7) ); -+ -+ reg_def V9 ( SOC, SOE, Op_RegF, 9, v9->as_VMReg() ); -+ reg_def V9_H ( SOC, SOE, Op_RegF, 9, v9->as_VMReg()->next() ); -+ reg_def V9_J ( SOC, SOC, Op_RegF, 9, v9->as_VMReg()->next(2) ); -+ reg_def V9_K ( SOC, SOC, Op_RegF, 9, v9->as_VMReg()->next(3) ); -+ reg_def V9_L ( SOC, SOC, Op_RegF, 9, v9->as_VMReg()->next(4) ); -+ reg_def V9_M ( SOC, SOC, Op_RegF, 9, v9->as_VMReg()->next(5) ); -+ reg_def V9_N ( SOC, SOC, Op_RegF, 9, v9->as_VMReg()->next(6) ); -+ reg_def V9_O ( SOC, SOC, Op_RegF, 9, v9->as_VMReg()->next(7) ); -+ -+ reg_def V10 ( SOC, SOE, Op_RegF, 10, v10->as_VMReg() ); -+ reg_def V10_H ( SOC, SOE, Op_RegF, 10, v10->as_VMReg()->next() ); -+ reg_def V10_J ( SOC, SOC, Op_RegF, 10, v10->as_VMReg()->next(2) ); -+ reg_def V10_K ( SOC, SOC, Op_RegF, 10, v10->as_VMReg()->next(3) ); -+ reg_def V10_L ( SOC, SOC, Op_RegF, 10, v10->as_VMReg()->next(4) ); -+ reg_def V10_M ( SOC, SOC, Op_RegF, 10, v10->as_VMReg()->next(5) ); -+ reg_def V10_N ( SOC, SOC, Op_RegF, 10, v10->as_VMReg()->next(6) ); -+ reg_def V10_O ( SOC, SOC, Op_RegF, 10, v10->as_VMReg()->next(7) ); -+ -+ reg_def V11 ( SOC, SOE, Op_RegF, 11, v11->as_VMReg() ); -+ reg_def V11_H ( SOC, SOE, Op_RegF, 11, v11->as_VMReg()->next() ); -+ reg_def V11_J ( SOC, SOC, Op_RegF, 11, v11->as_VMReg()->next(2) ); -+ reg_def V11_K ( SOC, SOC, Op_RegF, 11, v11->as_VMReg()->next(3) ); -+ reg_def V11_L ( SOC, SOC, Op_RegF, 11, v11->as_VMReg()->next(4) ); -+ reg_def V11_M ( SOC, SOC, Op_RegF, 11, v11->as_VMReg()->next(5) ); -+ reg_def V11_N ( SOC, SOC, Op_RegF, 11, v11->as_VMReg()->next(6) ); -+ reg_def V11_O ( SOC, SOC, Op_RegF, 11, v11->as_VMReg()->next(7) ); -+ -+ reg_def V12 ( SOC, SOE, Op_RegF, 12, v12->as_VMReg() ); -+ reg_def V12_H ( SOC, SOE, Op_RegF, 12, v12->as_VMReg()->next() ); -+ reg_def V12_J ( SOC, SOC, Op_RegF, 12, v12->as_VMReg()->next(2) ); -+ reg_def V12_K ( SOC, SOC, Op_RegF, 12, v12->as_VMReg()->next(3) ); -+ reg_def V12_L ( SOC, SOC, Op_RegF, 12, v12->as_VMReg()->next(4) ); -+ reg_def V12_M ( SOC, SOC, Op_RegF, 12, v12->as_VMReg()->next(5) ); -+ reg_def V12_N ( SOC, SOC, Op_RegF, 12, v12->as_VMReg()->next(6) ); -+ reg_def V12_O ( SOC, SOC, Op_RegF, 12, v12->as_VMReg()->next(7) ); -+ -+ reg_def V13 ( SOC, SOE, Op_RegF, 13, v13->as_VMReg() ); -+ reg_def V13_H ( SOC, SOE, Op_RegF, 13, v13->as_VMReg()->next() ); -+ reg_def V13_J ( SOC, SOC, Op_RegF, 13, v13->as_VMReg()->next(2) ); -+ reg_def V13_K ( SOC, SOC, Op_RegF, 13, v13->as_VMReg()->next(3) ); -+ reg_def V13_L ( SOC, SOC, Op_RegF, 13, v13->as_VMReg()->next(4) ); -+ reg_def V13_M ( SOC, SOC, Op_RegF, 13, v13->as_VMReg()->next(5) ); -+ reg_def V13_N ( SOC, SOC, Op_RegF, 13, v13->as_VMReg()->next(6) ); -+ reg_def V13_O ( SOC, SOC, Op_RegF, 13, v13->as_VMReg()->next(7) ); -+ -+ reg_def V14 ( SOC, SOE, Op_RegF, 14, v14->as_VMReg() ); -+ reg_def V14_H ( SOC, SOE, Op_RegF, 14, v14->as_VMReg()->next() ); -+ reg_def V14_J ( SOC, SOC, Op_RegF, 14, v14->as_VMReg()->next(2) ); -+ reg_def V14_K ( SOC, SOC, Op_RegF, 14, v14->as_VMReg()->next(3) ); -+ reg_def V14_L ( SOC, SOC, Op_RegF, 14, v14->as_VMReg()->next(4) ); -+ reg_def V14_M ( SOC, SOC, Op_RegF, 14, v14->as_VMReg()->next(5) ); -+ reg_def V14_N ( SOC, SOC, Op_RegF, 14, v14->as_VMReg()->next(6) ); -+ reg_def V14_O ( SOC, SOC, Op_RegF, 14, v14->as_VMReg()->next(7) ); -+ -+ reg_def V15 ( SOC, SOE, Op_RegF, 15, v15->as_VMReg() ); -+ reg_def V15_H ( SOC, SOE, Op_RegF, 15, v15->as_VMReg()->next() ); -+ reg_def V15_J ( SOC, SOC, Op_RegF, 15, v15->as_VMReg()->next(2) ); -+ reg_def V15_K ( SOC, SOC, Op_RegF, 15, v15->as_VMReg()->next(3) ); -+ reg_def V15_L ( SOC, SOC, Op_RegF, 15, v15->as_VMReg()->next(4) ); -+ reg_def V15_M ( SOC, SOC, Op_RegF, 15, v15->as_VMReg()->next(5) ); -+ reg_def V15_N ( SOC, SOC, Op_RegF, 15, v15->as_VMReg()->next(6) ); -+ reg_def V15_O ( SOC, SOC, Op_RegF, 15, v15->as_VMReg()->next(7) ); -+ -+ reg_def V16 ( SOC, SOC, Op_RegF, 16, v16->as_VMReg() ); -+ reg_def V16_H ( SOC, SOC, Op_RegF, 16, v16->as_VMReg()->next() ); -+ reg_def V16_J ( SOC, SOC, Op_RegF, 16, v16->as_VMReg()->next(2) ); -+ reg_def V16_K ( SOC, SOC, Op_RegF, 16, v16->as_VMReg()->next(3) ); -+ reg_def V16_L ( SOC, SOC, Op_RegF, 16, v16->as_VMReg()->next(4) ); -+ reg_def V16_M ( SOC, SOC, Op_RegF, 16, v16->as_VMReg()->next(5) ); -+ reg_def V16_N ( SOC, SOC, Op_RegF, 16, v16->as_VMReg()->next(6) ); -+ reg_def V16_O ( SOC, SOC, Op_RegF, 16, v16->as_VMReg()->next(7) ); -+ -+ reg_def V17 ( SOC, SOC, Op_RegF, 17, v17->as_VMReg() ); -+ reg_def V17_H ( SOC, SOC, Op_RegF, 17, v17->as_VMReg()->next() ); -+ reg_def V17_J ( SOC, SOC, Op_RegF, 17, v17->as_VMReg()->next(2) ); -+ reg_def V17_K ( SOC, SOC, Op_RegF, 17, v17->as_VMReg()->next(3) ); -+ reg_def V17_L ( SOC, SOC, Op_RegF, 17, v17->as_VMReg()->next(4) ); -+ reg_def V17_M ( SOC, SOC, Op_RegF, 17, v17->as_VMReg()->next(5) ); -+ reg_def V17_N ( SOC, SOC, Op_RegF, 17, v17->as_VMReg()->next(6) ); -+ reg_def V17_O ( SOC, SOC, Op_RegF, 17, v17->as_VMReg()->next(7) ); -+ -+ reg_def V18 ( SOC, SOC, Op_RegF, 18, v18->as_VMReg() ); -+ reg_def V18_H ( SOC, SOC, Op_RegF, 18, v18->as_VMReg()->next() ); -+ reg_def V18_J ( SOC, SOC, Op_RegF, 18, v18->as_VMReg()->next(2) ); -+ reg_def V18_K ( SOC, SOC, Op_RegF, 18, v18->as_VMReg()->next(3) ); -+ reg_def V18_L ( SOC, SOC, Op_RegF, 18, v18->as_VMReg()->next(4) ); -+ reg_def V18_M ( SOC, SOC, Op_RegF, 18, v18->as_VMReg()->next(5) ); -+ reg_def V18_N ( SOC, SOC, Op_RegF, 18, v18->as_VMReg()->next(6) ); -+ reg_def V18_O ( SOC, SOC, Op_RegF, 18, v18->as_VMReg()->next(7) ); -+ -+ reg_def V19 ( SOC, SOC, Op_RegF, 19, v19->as_VMReg() ); -+ reg_def V19_H ( SOC, SOC, Op_RegF, 19, v19->as_VMReg()->next() ); -+ reg_def V19_J ( SOC, SOC, Op_RegF, 19, v19->as_VMReg()->next(2) ); -+ reg_def V19_K ( SOC, SOC, Op_RegF, 19, v19->as_VMReg()->next(3) ); -+ reg_def V19_L ( SOC, SOC, Op_RegF, 19, v19->as_VMReg()->next(4) ); -+ reg_def V19_M ( SOC, SOC, Op_RegF, 19, v19->as_VMReg()->next(5) ); -+ reg_def V19_N ( SOC, SOC, Op_RegF, 19, v19->as_VMReg()->next(6) ); -+ reg_def V19_O ( SOC, SOC, Op_RegF, 19, v19->as_VMReg()->next(7) ); -+ -+ reg_def V20 ( SOC, SOC, Op_RegF, 20, v20->as_VMReg() ); -+ reg_def V20_H ( SOC, SOC, Op_RegF, 20, v20->as_VMReg()->next() ); -+ reg_def V20_J ( SOC, SOC, Op_RegF, 20, v20->as_VMReg()->next(2) ); -+ reg_def V20_K ( SOC, SOC, Op_RegF, 20, v20->as_VMReg()->next(3) ); -+ reg_def V20_L ( SOC, SOC, Op_RegF, 20, v20->as_VMReg()->next(4) ); -+ reg_def V20_M ( SOC, SOC, Op_RegF, 20, v20->as_VMReg()->next(5) ); -+ reg_def V20_N ( SOC, SOC, Op_RegF, 20, v20->as_VMReg()->next(6) ); -+ reg_def V20_O ( SOC, SOC, Op_RegF, 20, v20->as_VMReg()->next(7) ); -+ -+ reg_def V21 ( SOC, SOC, Op_RegF, 21, v21->as_VMReg() ); -+ reg_def V21_H ( SOC, SOC, Op_RegF, 21, v21->as_VMReg()->next() ); -+ reg_def V21_J ( SOC, SOC, Op_RegF, 21, v21->as_VMReg()->next(2) ); -+ reg_def V21_K ( SOC, SOC, Op_RegF, 21, v21->as_VMReg()->next(3) ); -+ reg_def V21_L ( SOC, SOC, Op_RegF, 21, v21->as_VMReg()->next(4) ); -+ reg_def V21_M ( SOC, SOC, Op_RegF, 21, v21->as_VMReg()->next(5) ); -+ reg_def V21_N ( SOC, SOC, Op_RegF, 21, v21->as_VMReg()->next(6) ); -+ reg_def V21_O ( SOC, SOC, Op_RegF, 21, v21->as_VMReg()->next(7) ); -+ -+ reg_def V22 ( SOC, SOC, Op_RegF, 22, v22->as_VMReg() ); -+ reg_def V22_H ( SOC, SOC, Op_RegF, 22, v22->as_VMReg()->next() ); -+ reg_def V22_J ( SOC, SOC, Op_RegF, 22, v22->as_VMReg()->next(2) ); -+ reg_def V22_K ( SOC, SOC, Op_RegF, 22, v22->as_VMReg()->next(3) ); -+ reg_def V22_L ( SOC, SOC, Op_RegF, 22, v22->as_VMReg()->next(4) ); -+ reg_def V22_M ( SOC, SOC, Op_RegF, 22, v22->as_VMReg()->next(5) ); -+ reg_def V22_N ( SOC, SOC, Op_RegF, 22, v22->as_VMReg()->next(6) ); -+ reg_def V22_O ( SOC, SOC, Op_RegF, 22, v22->as_VMReg()->next(7) ); -+ -+ reg_def V23 ( SOC, SOC, Op_RegF, 23, v23->as_VMReg() ); -+ reg_def V23_H ( SOC, SOC, Op_RegF, 23, v23->as_VMReg()->next() ); -+ reg_def V23_J ( SOC, SOC, Op_RegF, 23, v23->as_VMReg()->next(2) ); -+ reg_def V23_K ( SOC, SOC, Op_RegF, 23, v23->as_VMReg()->next(3) ); -+ reg_def V23_L ( SOC, SOC, Op_RegF, 23, v23->as_VMReg()->next(4) ); -+ reg_def V23_M ( SOC, SOC, Op_RegF, 23, v23->as_VMReg()->next(5) ); -+ reg_def V23_N ( SOC, SOC, Op_RegF, 23, v23->as_VMReg()->next(6) ); -+ reg_def V23_O ( SOC, SOC, Op_RegF, 23, v23->as_VMReg()->next(7) ); -+ -+ reg_def V24 ( SOC, SOC, Op_RegF, 24, v24->as_VMReg() ); -+ reg_def V24_H ( SOC, SOC, Op_RegF, 24, v24->as_VMReg()->next() ); -+ reg_def V24_J ( SOC, SOC, Op_RegF, 24, v24->as_VMReg()->next(2) ); -+ reg_def V24_K ( SOC, SOC, Op_RegF, 24, v24->as_VMReg()->next(3) ); -+ reg_def V24_L ( SOC, SOC, Op_RegF, 24, v24->as_VMReg()->next(4) ); -+ reg_def V24_M ( SOC, SOC, Op_RegF, 24, v24->as_VMReg()->next(5) ); -+ reg_def V24_N ( SOC, SOC, Op_RegF, 24, v24->as_VMReg()->next(6) ); -+ reg_def V24_O ( SOC, SOC, Op_RegF, 24, v24->as_VMReg()->next(7) ); -+ -+ reg_def V25 ( SOC, SOC, Op_RegF, 25, v25->as_VMReg() ); -+ reg_def V25_H ( SOC, SOC, Op_RegF, 25, v25->as_VMReg()->next() ); -+ reg_def V25_J ( SOC, SOC, Op_RegF, 25, v25->as_VMReg()->next(2) ); -+ reg_def V25_K ( SOC, SOC, Op_RegF, 25, v25->as_VMReg()->next(3) ); -+ reg_def V25_L ( SOC, SOC, Op_RegF, 25, v25->as_VMReg()->next(4) ); -+ reg_def V25_M ( SOC, SOC, Op_RegF, 25, v25->as_VMReg()->next(5) ); -+ reg_def V25_N ( SOC, SOC, Op_RegF, 25, v25->as_VMReg()->next(6) ); -+ reg_def V25_O ( SOC, SOC, Op_RegF, 25, v25->as_VMReg()->next(7) ); -+ -+ reg_def V26 ( SOC, SOC, Op_RegF, 26, v26->as_VMReg() ); -+ reg_def V26_H ( SOC, SOC, Op_RegF, 26, v26->as_VMReg()->next() ); -+ reg_def V26_J ( SOC, SOC, Op_RegF, 26, v26->as_VMReg()->next(2) ); -+ reg_def V26_K ( SOC, SOC, Op_RegF, 26, v26->as_VMReg()->next(3) ); -+ reg_def V26_L ( SOC, SOC, Op_RegF, 26, v26->as_VMReg()->next(4) ); -+ reg_def V26_M ( SOC, SOC, Op_RegF, 26, v26->as_VMReg()->next(5) ); -+ reg_def V26_N ( SOC, SOC, Op_RegF, 26, v26->as_VMReg()->next(6) ); -+ reg_def V26_O ( SOC, SOC, Op_RegF, 26, v26->as_VMReg()->next(7) ); -+ -+ reg_def V27 ( SOC, SOC, Op_RegF, 27, v27->as_VMReg() ); -+ reg_def V27_H ( SOC, SOC, Op_RegF, 27, v27->as_VMReg()->next() ); -+ reg_def V27_J ( SOC, SOC, Op_RegF, 27, v27->as_VMReg()->next(2) ); -+ reg_def V27_K ( SOC, SOC, Op_RegF, 27, v27->as_VMReg()->next(3) ); -+ reg_def V27_L ( SOC, SOC, Op_RegF, 27, v27->as_VMReg()->next(4) ); -+ reg_def V27_M ( SOC, SOC, Op_RegF, 27, v27->as_VMReg()->next(5) ); -+ reg_def V27_N ( SOC, SOC, Op_RegF, 27, v27->as_VMReg()->next(6) ); -+ reg_def V27_O ( SOC, SOC, Op_RegF, 27, v27->as_VMReg()->next(7) ); -+ -+ reg_def V28 ( SOC, SOC, Op_RegF, 28, v28->as_VMReg() ); -+ reg_def V28_H ( SOC, SOC, Op_RegF, 28, v28->as_VMReg()->next() ); -+ reg_def V28_J ( SOC, SOC, Op_RegF, 28, v28->as_VMReg()->next(2) ); -+ reg_def V28_K ( SOC, SOC, Op_RegF, 28, v28->as_VMReg()->next(3) ); -+ reg_def V28_L ( SOC, SOC, Op_RegF, 28, v28->as_VMReg()->next(4) ); -+ reg_def V28_M ( SOC, SOC, Op_RegF, 28, v28->as_VMReg()->next(5) ); -+ reg_def V28_N ( SOC, SOC, Op_RegF, 28, v28->as_VMReg()->next(6) ); -+ reg_def V28_O ( SOC, SOC, Op_RegF, 28, v28->as_VMReg()->next(7) ); -+ -+ reg_def V29 ( SOC, SOC, Op_RegF, 29, v29->as_VMReg() ); -+ reg_def V29_H ( SOC, SOC, Op_RegF, 29, v29->as_VMReg()->next() ); -+ reg_def V29_J ( SOC, SOC, Op_RegF, 29, v29->as_VMReg()->next(2) ); -+ reg_def V29_K ( SOC, SOC, Op_RegF, 29, v29->as_VMReg()->next(3) ); -+ reg_def V29_L ( SOC, SOC, Op_RegF, 29, v29->as_VMReg()->next(4) ); -+ reg_def V29_M ( SOC, SOC, Op_RegF, 29, v29->as_VMReg()->next(5) ); -+ reg_def V29_N ( SOC, SOC, Op_RegF, 29, v29->as_VMReg()->next(6) ); -+ reg_def V29_O ( SOC, SOC, Op_RegF, 29, v29->as_VMReg()->next(7) ); -+ -+ reg_def V30 ( SOC, SOC, Op_RegF, 30, v30->as_VMReg() ); -+ reg_def V30_H ( SOC, SOC, Op_RegF, 30, v30->as_VMReg()->next() ); -+ reg_def V30_J ( SOC, SOC, Op_RegF, 30, v30->as_VMReg()->next(2) ); -+ reg_def V30_K ( SOC, SOC, Op_RegF, 30, v30->as_VMReg()->next(3) ); -+ reg_def V30_L ( SOC, SOC, Op_RegF, 30, v30->as_VMReg()->next(4) ); -+ reg_def V30_M ( SOC, SOC, Op_RegF, 30, v30->as_VMReg()->next(5) ); -+ reg_def V30_N ( SOC, SOC, Op_RegF, 30, v30->as_VMReg()->next(6) ); -+ reg_def V30_O ( SOC, SOC, Op_RegF, 30, v30->as_VMReg()->next(7) ); -+ -+ reg_def V31 ( SOC, SOC, Op_RegF, 31, v31->as_VMReg() ); -+ reg_def V31_H ( SOC, SOC, Op_RegF, 31, v31->as_VMReg()->next() ); -+ reg_def V31_J ( SOC, SOC, Op_RegF, 31, v31->as_VMReg()->next(2) ); -+ reg_def V31_K ( SOC, SOC, Op_RegF, 31, v31->as_VMReg()->next(3) ); -+ reg_def V31_L ( SOC, SOC, Op_RegF, 31, v31->as_VMReg()->next(4) ); -+ reg_def V31_M ( SOC, SOC, Op_RegF, 31, v31->as_VMReg()->next(5) ); -+ reg_def V31_N ( SOC, SOC, Op_RegF, 31, v31->as_VMReg()->next(6) ); -+ reg_def V31_O ( SOC, SOC, Op_RegF, 31, v31->as_VMReg()->next(7) ); -+ -+ -+// ---------------------------- -+// SVE Predicate Registers -+// ---------------------------- -+ reg_def P0 (SOC, SOC, Op_RegVMask, 0, p0->as_VMReg()); -+ reg_def P1 (SOC, SOC, Op_RegVMask, 1, p1->as_VMReg()); -+ reg_def P2 (SOC, SOC, Op_RegVMask, 2, p2->as_VMReg()); -+ reg_def P3 (SOC, SOC, Op_RegVMask, 3, p3->as_VMReg()); -+ reg_def P4 (SOC, SOC, Op_RegVMask, 4, p4->as_VMReg()); -+ reg_def P5 (SOC, SOC, Op_RegVMask, 5, p5->as_VMReg()); -+ reg_def P6 (SOC, SOC, Op_RegVMask, 6, p6->as_VMReg()); -+ reg_def P7 (SOC, SOC, Op_RegVMask, 7, p7->as_VMReg()); - - // ---------------------------- - // Special Registers -@@ -381,50 +536,64 @@ alloc_class chunk0( - R29, R29_H, // fp - R30, R30_H, // lr - R31, R31_H, // sp -+ R8, R8_H, // rscratch1 -+ R9, R9_H, // rscratch2 - ); - - alloc_class chunk1( - - // no save -- V16, V16_H, V16_J, V16_K, -- V17, V17_H, V17_J, V17_K, -- V18, V18_H, V18_J, V18_K, -- V19, V19_H, V19_J, V19_K, -- V20, V20_H, V20_J, V20_K, -- V21, V21_H, V21_J, V21_K, -- V22, V22_H, V22_J, V22_K, -- V23, V23_H, V23_J, V23_K, -- V24, V24_H, V24_J, V24_K, -- V25, V25_H, V25_J, V25_K, -- V26, V26_H, V26_J, V26_K, -- V27, V27_H, V27_J, V27_K, -- V28, V28_H, V28_J, V28_K, -- V29, V29_H, V29_J, V29_K, -- V30, V30_H, V30_J, V30_K, -- V31, V31_H, V31_J, V31_K, -+ V16, V16_H, V16_J, V16_K, V16_L, V16_M, V16_N, V16_O, -+ V17, V17_H, V17_J, V17_K, V17_L, V17_M, V17_N, V17_O, -+ V18, V18_H, V18_J, V18_K, V18_L, V18_M, V18_N, V18_O, -+ V19, V19_H, V19_J, V19_K, V19_L, V19_M, V19_N, V19_O, -+ V20, V20_H, V20_J, V20_K, V20_L, V20_M, V20_N, V20_O, -+ V21, V21_H, V21_J, V21_K, V21_L, V21_M, V21_N, V21_O, -+ V22, V22_H, V22_J, V22_K, V22_L, V22_M, V22_N, V22_O, -+ V23, V23_H, V23_J, V23_K, V23_L, V23_M, V23_N, V23_O, -+ V24, V24_H, V24_J, V24_K, V24_L, V24_M, V24_N, V24_O, -+ V25, V25_H, V25_J, V25_K, V25_L, V25_M, V25_N, V25_O, -+ V26, V26_H, V26_J, V26_K, V26_L, V26_M, V26_N, V26_O, -+ V27, V27_H, V27_J, V27_K, V27_L, V27_M, V27_N, V27_O, -+ V28, V28_H, V28_J, V28_K, V28_L, V28_M, V28_N, V28_O, -+ V29, V29_H, V29_J, V29_K, V29_L, V29_M, V29_N, V29_O, -+ V30, V30_H, V30_J, V30_K, V30_L, V30_M, V30_N, V30_O, -+ V31, V31_H, V31_J, V31_K, V31_L, V31_M, V31_N, V31_O, - - // arg registers -- V0, V0_H, V0_J, V0_K, -- V1, V1_H, V1_J, V1_K, -- V2, V2_H, V2_J, V2_K, -- V3, V3_H, V3_J, V3_K, -- V4, V4_H, V4_J, V4_K, -- V5, V5_H, V5_J, V5_K, -- V6, V6_H, V6_J, V6_K, -- V7, V7_H, V7_J, V7_K, -+ V0, V0_H, V0_J, V0_K, V0_L, V0_M, V0_N, V0_O, -+ V1, V1_H, V1_J, V1_K, V1_L, V1_M, V1_N, V1_O, -+ V2, V2_H, V2_J, V2_K, V2_L, V2_M, V2_N, V2_O, -+ V3, V3_H, V3_J, V3_K, V3_L, V3_M, V3_N, V3_O, -+ V4, V4_H, V4_J, V4_K, V4_L, V4_M, V4_N, V4_O, -+ V5, V5_H, V5_J, V5_K, V5_L, V5_M, V5_N, V5_O, -+ V6, V6_H, V6_J, V6_K, V6_L, V6_M, V6_N, V6_O, -+ V7, V7_H, V7_J, V7_K, V7_L, V7_M, V7_N, V7_O, - - // non-volatiles -- V8, V8_H, V8_J, V8_K, -- V9, V9_H, V9_J, V9_K, -- V10, V10_H, V10_J, V10_K, -- V11, V11_H, V11_J, V11_K, -- V12, V12_H, V12_J, V12_K, -- V13, V13_H, V13_J, V13_K, -- V14, V14_H, V14_J, V14_K, -- V15, V15_H, V15_J, V15_K, -+ V8, V8_H, V8_J, V8_K, V8_L, V8_M, V8_N, V8_O, -+ V9, V9_H, V9_J, V9_K, V9_L, V9_M, V9_N, V9_O, -+ V10, V10_H, V10_J, V10_K, V10_L, V10_M, V10_N, V10_O, -+ V11, V11_H, V11_J, V11_K, V11_L, V11_M, V11_N, V11_O, -+ V12, V12_H, V12_J, V12_K, V12_L, V12_M, V12_N, V12_O, -+ V13, V13_H, V13_J, V13_K, V13_L, V13_M, V13_N, V13_O, -+ V14, V14_H, V14_J, V14_K, V14_L, V14_M, V14_N, V14_O, -+ V15, V15_H, V15_J, V15_K, V15_L, V15_M, V15_N, V15_O, - ); - --alloc_class chunk2(RFLAGS); -+alloc_class chunk2 ( -+ P0, -+ P1, -+ P2, -+ P3, -+ P4, -+ P5, -+ P6, -+ P7, -+ // Only use P0~P7 here for performance -+); -+ -+alloc_class chunk3(RFLAGS); - - //----------Architecture Description Register Classes-------------------------- - // Several register classes are automatically defined based upon information in -@@ -865,6 +1034,42 @@ reg_class double_reg( - V31, V31_H - ); - -+// Class for all SVE vector registers. -+reg_class vectora_reg ( -+ V0, V0_H, V0_J, V0_K, V0_L, V0_M, V0_N, V0_O, -+ V1, V1_H, V1_J, V1_K, V1_L, V1_M, V1_N, V1_O, -+ V2, V2_H, V2_J, V2_K, V2_L, V2_M, V2_N, V2_O, -+ V3, V3_H, V3_J, V3_K, V3_L, V3_M, V3_N, V3_O, -+ V4, V4_H, V4_J, V4_K, V4_L, V4_M, V4_N, V4_O, -+ V5, V5_H, V5_J, V5_K, V5_L, V5_M, V5_N, V5_O, -+ V6, V6_H, V6_J, V6_K, V6_L, V6_M, V6_N, V6_O, -+ V7, V7_H, V7_J, V7_K, V7_L, V7_M, V7_N, V7_O, -+ V8, V8_H, V8_J, V8_K, V8_L, V8_M, V8_N, V8_O, -+ V9, V9_H, V9_J, V9_K, V9_L, V9_M, V9_N, V9_O, -+ V10, V10_H, V10_J, V10_K, V10_L, V10_M, V10_N, V10_O, -+ V11, V11_H, V11_J, V11_K, V11_L, V11_M, V11_N, V11_O, -+ V12, V12_H, V12_J, V12_K, V12_L, V12_M, V12_N, V12_O, -+ V13, V13_H, V13_J, V13_K, V13_L, V13_M, V13_N, V13_O, -+ V14, V14_H, V14_J, V14_K, V14_L, V14_M, V14_N, V14_O, -+ V15, V15_H, V15_J, V15_K, V15_L, V15_M, V15_N, V15_O, -+ V16, V16_H, V16_J, V16_K, V16_L, V16_M, V16_N, V16_O, -+ V17, V17_H, V17_J, V17_K, V17_L, V17_M, V17_N, V17_O, -+ V18, V18_H, V18_J, V18_K, V18_L, V18_M, V18_N, V18_O, -+ V19, V19_H, V19_J, V19_K, V19_L, V19_M, V19_N, V19_O, -+ V20, V20_H, V20_J, V20_K, V20_L, V20_M, V20_N, V20_O, -+ V21, V21_H, V21_J, V21_K, V21_L, V21_M, V21_N, V21_O, -+ V22, V22_H, V22_J, V22_K, V22_L, V22_M, V22_N, V22_O, -+ V23, V23_H, V23_J, V23_K, V23_L, V23_M, V23_N, V23_O, -+ V24, V24_H, V24_J, V24_K, V24_L, V24_M, V24_N, V24_O, -+ V25, V25_H, V25_J, V25_K, V25_L, V25_M, V25_N, V25_O, -+ V26, V26_H, V26_J, V26_K, V26_L, V26_M, V26_N, V26_O, -+ V27, V27_H, V27_J, V27_K, V27_L, V27_M, V27_N, V27_O, -+ V28, V28_H, V28_J, V28_K, V28_L, V28_M, V28_N, V28_O, -+ V29, V29_H, V29_J, V29_K, V29_L, V29_M, V29_N, V29_O, -+ V30, V30_H, V30_J, V30_K, V30_L, V30_M, V30_N, V30_O, -+ V31, V31_H, V31_J, V31_K, V31_L, V31_M, V31_N, V31_O, -+); -+ - // Class for all 64bit vector registers - reg_class vectord_reg( - V0, V0_H, -@@ -1097,6 +1302,31 @@ reg_class v31_reg( - V31, V31_H - ); - -+// Class for all SVE predicate registers. -+reg_class pr_reg ( -+ P0, -+ P1, -+ P2, -+ P3, -+ P4, -+ P5, -+ P6, -+ // P7, non-allocatable, preserved with all elements preset to TRUE. -+); -+ -+// Class for SVE governing predicate registers, which are used -+// to determine the active elements of a predicated instruction. -+reg_class gov_pr ( -+ P0, -+ P1, -+ P2, -+ P3, -+ P4, -+ P5, -+ P6, -+ // P7, non-allocatable, preserved with all elements preset to TRUE. -+); -+ - // Singleton class for condition codes - reg_class int_flags(RFLAGS); - -@@ -1761,6 +1991,10 @@ void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { +@@ -1991,6 +1991,10 @@ void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { // branch if we need to invalidate the method later __ nop(); @@ -708,48 +30,7 @@ index b64919a62..fa434df7d 100644 int bangsize = C->bang_size_in_bytes(); if (C->need_stack_bang(bangsize) && UseStackBanging) __ generate_stack_overflow_check(bangsize); -@@ -1862,7 +2096,7 @@ int MachEpilogNode::safepoint_offset() const { - - // Figure out which register class each belongs in: rc_int, rc_float or - // rc_stack. --enum RC { rc_bad, rc_int, rc_float, rc_stack }; -+enum RC { rc_bad, rc_int, rc_float, rc_predicate, rc_stack }; - - static enum RC rc_class(OptoReg::Name reg) { - -@@ -1870,20 +2104,25 @@ static enum RC rc_class(OptoReg::Name reg) { - return rc_bad; - } - -- // we have 30 int registers * 2 halves -- // (rscratch1 and rscratch2 are omitted) -- int slots_of_int_registers = RegisterImpl::max_slots_per_register * (RegisterImpl::number_of_registers - 2); -+ // we have 32 int registers * 2 halves -+ int slots_of_int_registers = RegisterImpl::max_slots_per_register * RegisterImpl::number_of_registers; - - if (reg < slots_of_int_registers) { - return rc_int; - } - -- // we have 32 float register * 4 halves -- if (reg < slots_of_int_registers + FloatRegisterImpl::max_slots_per_register * FloatRegisterImpl::number_of_registers) { -+ // we have 32 float register * 8 halves -+ int slots_of_float_registers = FloatRegisterImpl::max_slots_per_register * FloatRegisterImpl::number_of_registers; -+ if (reg < slots_of_int_registers + slots_of_float_registers) { - return rc_float; - } - -- // Between float regs & stack is the flags regs. -+ int slots_of_predicate_registers = PRegisterImpl::max_slots_per_register * PRegisterImpl::number_of_registers; -+ if (reg < slots_of_int_registers + slots_of_float_registers + slots_of_predicate_registers) { -+ return rc_predicate; -+ } -+ -+ // Between predicate regs & stack is the flags. - assert(OptoReg::is_stack(reg), "blow up if spilling flags"); - - return rc_stack; -@@ -1922,8 +2161,28 @@ uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, boo +@@ -2157,8 +2161,28 @@ uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, boo if (bottom_type()->isa_vect() != NULL) { uint ireg = ideal_reg(); @@ -780,51 +61,7 @@ index b64919a62..fa434df7d 100644 MacroAssembler _masm(cbuf); assert((src_lo_rc != rc_int && dst_lo_rc != rc_int), "sanity"); if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) { -@@ -1941,12 +2200,12 @@ uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, boo - as_FloatRegister(Matcher::_regEncode[src_lo])); - } else if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) { - __ spill(as_FloatRegister(Matcher::_regEncode[src_lo]), -- ireg == Op_VecD ? __ D : __ Q, -- ra_->reg2offset(dst_lo)); -+ ireg == Op_VecD ? __ D : __ Q, -+ ra_->reg2offset(dst_lo)); - } else if (src_lo_rc == rc_stack && dst_lo_rc == rc_float) { - __ unspill(as_FloatRegister(Matcher::_regEncode[dst_lo]), -- ireg == Op_VecD ? __ D : __ Q, -- ra_->reg2offset(src_lo)); -+ ireg == Op_VecD ? __ D : __ Q, -+ ra_->reg2offset(src_lo)); - } else { - ShouldNotReachHere(); - } -@@ -2031,9 +2290,24 @@ uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, boo - st->print("%s", Matcher::regName[dst_lo]); - } - if (bottom_type()->isa_vect() != NULL) { -- st->print("\t# vector spill size = %d", ideal_reg()==Op_VecD ? 64:128); -+ int vsize = 0; -+ switch (ideal_reg()) { -+ case Op_VecD: -+ vsize = 64; -+ break; -+ case Op_VecX: -+ vsize = 128; -+ break; -+ case Op_VecA: -+ vsize = Matcher::scalable_vector_reg_size(T_BYTE) * 8; -+ break; -+ default: -+ assert(false, "bad register type for spill"); -+ ShouldNotReachHere(); -+ } -+ st->print("\t# vector spill size = %d", vsize); - } else { -- st->print("\t# spill size = %d", is64 ? 64:32); -+ st->print("\t# spill size = %d", is64 ? 64 : 32); - } - } - -@@ -2192,19 +2466,32 @@ const bool Matcher::match_rule_supported(int opcode) { +@@ -2442,15 +2466,28 @@ const bool Matcher::match_rule_supported(int opcode) { return true; // Per default match rules are supported. } @@ -862,66 +99,7 @@ index b64919a62..fa434df7d 100644 } const bool Matcher::has_predicated_vectors(void) { -- return false; -+ return UseSVE > 0; - } - - const int Matcher::float_pressure(int default_pressure_threshold) { -@@ -2240,7 +2527,8 @@ const bool Matcher::convL2FSupported(void) { - - // Vector width in bytes. - const int Matcher::vector_width_in_bytes(BasicType bt) { -- int size = MIN2(16,(int)MaxVectorSize); -+ // The MaxVectorSize should have been set by detecting SVE max vector register size. -+ int size = MIN2((UseSVE > 0) ? 256 : 16, (int)MaxVectorSize); - // Minimum 2 values in vector - if (size < 2*type2aelembytes(bt)) size = 0; - // But never < 4 -@@ -2253,14 +2541,32 @@ const int Matcher::max_vector_size(const BasicType bt) { - return vector_width_in_bytes(bt)/type2aelembytes(bt); - } - const int Matcher::min_vector_size(const BasicType bt) { --// For the moment limit the vector size to 8 bytes -+ int max_size = max_vector_size(bt); -+ if ((UseSVE > 0) && (MaxVectorSize >= 16)) { -+ // Currently vector length less than SVE vector register size is not supported. -+ return max_size; -+ } else { -+ // For the moment limit the vector size to 8 bytes with NEON. - int size = 8 / type2aelembytes(bt); - if (size < 2) size = 2; - return size; -+ } -+} -+ -+const bool Matcher::supports_scalable_vector() { -+ return UseSVE > 0; -+} -+ -+// Actual max scalable vector register length. -+const int Matcher::scalable_vector_reg_size(const BasicType bt) { -+ return Matcher::max_vector_size(bt); - } - - // Vector ideal reg. - const uint Matcher::vector_ideal_reg(int len) { -+ if (UseSVE > 0 && 16 <= len && len <= 256) { -+ return Op_VecA; -+ } - switch(len) { - case 8: return Op_VecD; - case 16: return Op_VecX; -@@ -2270,6 +2576,9 @@ const uint Matcher::vector_ideal_reg(int len) { - } - - const uint Matcher::vector_shift_count_ideal_reg(int size) { -+ if (UseSVE > 0 && 16 <= size && size <= 256) { -+ return Op_VecA; -+ } - switch(size) { - case 8: return Op_VecD; - case 16: return Op_VecX; -@@ -3419,6 +3728,11 @@ encode %{ +@@ -3691,6 +3728,11 @@ encode %{ if (call == NULL) { ciEnv::current()->record_failure("CodeCache is full"); return; @@ -933,7 +111,7 @@ index b64919a62..fa434df7d 100644 } // Emit stub for static call address stub = CompiledStaticCall::emit_to_interp_stub(cbuf); -@@ -3436,6 +3750,8 @@ encode %{ +@@ -3708,6 +3750,8 @@ encode %{ if (call == NULL) { ciEnv::current()->record_failure("CodeCache is full"); return; @@ -942,7 +120,7 @@ index b64919a62..fa434df7d 100644 } %} -@@ -3472,6 +3788,9 @@ encode %{ +@@ -3744,6 +3788,9 @@ encode %{ __ bind(retaddr); __ add(sp, sp, 2 * wordSize); } @@ -952,7 +130,7 @@ index b64919a62..fa434df7d 100644 %} enc_class aarch64_enc_rethrow() %{ -@@ -3481,6 +3800,11 @@ encode %{ +@@ -3753,6 +3800,11 @@ encode %{ enc_class aarch64_enc_ret() %{ MacroAssembler _masm(&cbuf); @@ -964,7 +142,7 @@ index b64919a62..fa434df7d 100644 __ ret(lr); %} -@@ -4222,6 +4546,41 @@ operand immLoffset16() +@@ -4494,6 +4546,41 @@ operand immLoffset16() interface(CONST_INTER); %} @@ -1006,42 +184,7 @@ index b64919a62..fa434df7d 100644 // 32 bit integer valid for add sub immediate operand immIAddSub() %{ -@@ -4851,6 +5210,18 @@ operand vRegD() - interface(REG_INTER); - %} - -+// Generic vector class. This will be used for -+// all vector operands, including NEON and SVE, -+// but currently only used for SVE VecA. -+operand vReg() -+%{ -+ constraint(ALLOC_IN_RC(vectora_reg)); -+ match(VecA); -+ op_cost(0); -+ format %{ %} -+ interface(REG_INTER); -+%} -+ - operand vecD() - %{ - constraint(ALLOC_IN_RC(vectord_reg)); -@@ -5159,6 +5530,15 @@ operand vRegD_V31() - interface(REG_INTER); - %} - -+operand pRegGov() -+%{ -+ constraint(ALLOC_IN_RC(gov_pr)); -+ match(RegVMask); -+ op_cost(0); -+ format %{ %} -+ interface(REG_INTER); -+%} -+ - // Flags register, used as output of signed compare instructions - - // note that on AArch64 we also use this register as the output for -@@ -15745,7 +16125,7 @@ instruct loadV8(vecD dst, vmem8 mem) +@@ -16038,7 +16125,7 @@ instruct loadV8(vecD dst, vmem8 mem) // Load Vector (128 bits) instruct loadV16(vecX dst, vmem16 mem) %{ @@ -1050,7 +193,7 @@ index b64919a62..fa434df7d 100644 match(Set dst (LoadVector mem)); ins_cost(4 * INSN_COST); format %{ "ldrq $dst,$mem\t# vector (128 bits)" %} -@@ -15801,7 +16181,7 @@ instruct replicate8B(vecD dst, iRegIorL2I src) +@@ -16094,7 +16181,7 @@ instruct replicate8B(vecD dst, iRegIorL2I src) instruct replicate16B(vecX dst, iRegIorL2I src) %{ @@ -1059,7 +202,7 @@ index b64919a62..fa434df7d 100644 match(Set dst (ReplicateB src)); ins_cost(INSN_COST); format %{ "dup $dst, $src\t# vector (16B)" %} -@@ -15826,7 +16206,7 @@ instruct replicate8B_imm(vecD dst, immI con) +@@ -16119,7 +16206,7 @@ instruct replicate8B_imm(vecD dst, immI con) instruct replicate16B_imm(vecX dst, immI con) %{ @@ -1068,7 +211,7 @@ index b64919a62..fa434df7d 100644 match(Set dst (ReplicateB con)); ins_cost(INSN_COST); format %{ "movi $dst, $con\t# vector(16B)" %} -@@ -15851,7 +16231,7 @@ instruct replicate4S(vecD dst, iRegIorL2I src) +@@ -16144,7 +16231,7 @@ instruct replicate4S(vecD dst, iRegIorL2I src) instruct replicate8S(vecX dst, iRegIorL2I src) %{ @@ -1077,7 +220,7 @@ index b64919a62..fa434df7d 100644 match(Set dst (ReplicateS src)); ins_cost(INSN_COST); format %{ "dup $dst, $src\t# vector (8S)" %} -@@ -15876,7 +16256,7 @@ instruct replicate4S_imm(vecD dst, immI con) +@@ -16169,7 +16256,7 @@ instruct replicate4S_imm(vecD dst, immI con) instruct replicate8S_imm(vecX dst, immI con) %{ @@ -1086,7 +229,7 @@ index b64919a62..fa434df7d 100644 match(Set dst (ReplicateS con)); ins_cost(INSN_COST); format %{ "movi $dst, $con\t# vector(8H)" %} -@@ -15900,7 +16280,7 @@ instruct replicate2I(vecD dst, iRegIorL2I src) +@@ -16193,7 +16280,7 @@ instruct replicate2I(vecD dst, iRegIorL2I src) instruct replicate4I(vecX dst, iRegIorL2I src) %{ @@ -1095,7 +238,7 @@ index b64919a62..fa434df7d 100644 match(Set dst (ReplicateI src)); ins_cost(INSN_COST); format %{ "dup $dst, $src\t# vector (4I)" %} -@@ -15924,7 +16304,7 @@ instruct replicate2I_imm(vecD dst, immI con) +@@ -16217,7 +16304,7 @@ instruct replicate2I_imm(vecD dst, immI con) instruct replicate4I_imm(vecX dst, immI con) %{ @@ -1104,7 +247,7 @@ index b64919a62..fa434df7d 100644 match(Set dst (ReplicateI con)); ins_cost(INSN_COST); format %{ "movi $dst, $con\t# vector(4I)" %} -@@ -15936,7 +16316,7 @@ instruct replicate4I_imm(vecX dst, immI con) +@@ -16229,7 +16316,7 @@ instruct replicate4I_imm(vecX dst, immI con) instruct replicate2L(vecX dst, iRegL src) %{ @@ -1113,7 +256,7 @@ index b64919a62..fa434df7d 100644 match(Set dst (ReplicateL src)); ins_cost(INSN_COST); format %{ "dup $dst, $src\t# vector (2L)" %} -@@ -15948,7 +16328,7 @@ instruct replicate2L(vecX dst, iRegL src) +@@ -16241,7 +16328,7 @@ instruct replicate2L(vecX dst, iRegL src) instruct replicate2L_zero(vecX dst, immI0 zero) %{ @@ -1122,7 +265,7 @@ index b64919a62..fa434df7d 100644 match(Set dst (ReplicateI zero)); ins_cost(INSN_COST); format %{ "movi $dst, $zero\t# vector(4I)" %} -@@ -15975,7 +16355,7 @@ instruct replicate2F(vecD dst, vRegF src) +@@ -16268,7 +16355,7 @@ instruct replicate2F(vecD dst, vRegF src) instruct replicate4F(vecX dst, vRegF src) %{ @@ -1131,7 +274,7 @@ index b64919a62..fa434df7d 100644 match(Set dst (ReplicateF src)); ins_cost(INSN_COST); format %{ "dup $dst, $src\t# vector (4F)" %} -@@ -15988,7 +16368,7 @@ instruct replicate4F(vecX dst, vRegF src) +@@ -16281,7 +16368,7 @@ instruct replicate4F(vecX dst, vRegF src) instruct replicate2D(vecX dst, vRegD src) %{ @@ -3246,105 +2389,105 @@ index 000000000..0323f2f8c +BINARY_OP_UNPREDICATED(vsubF, SubVF, S, 4, sve_fsub) +BINARY_OP_UNPREDICATED(vsubD, SubVD, D, 2, sve_fsub) diff --git a/src/hotspot/cpu/aarch64/assembler_aarch64.cpp b/src/hotspot/cpu/aarch64/assembler_aarch64.cpp -index 2a17d8e0f..943d2a615 100644 +index 8047ed8fd..32e53336b 100644 --- a/src/hotspot/cpu/aarch64/assembler_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/assembler_aarch64.cpp -@@ -96,662 +96,662 @@ void entry(CodeBuffer *cb) { +@@ -96,662 +96,746 @@ void entry(CodeBuffer *cb) { __ bind(back); // ArithOp -- __ add(r15, r12, r16, Assembler::LSR, 30); // add x15, x12, x16, LSR #30 -- __ sub(r1, r15, r3, Assembler::LSR, 32); // sub x1, x15, x3, LSR #32 -- __ adds(r13, r25, r5, Assembler::LSL, 13); // adds x13, x25, x5, LSL #13 -- __ subs(r22, r28, r6, Assembler::ASR, 17); // subs x22, x28, x6, ASR #17 -- __ addw(r0, r9, r22, Assembler::ASR, 6); // add w0, w9, w22, ASR #6 -- __ subw(r19, r3, r25, Assembler::LSL, 21); // sub w19, w3, w25, LSL #21 -- __ addsw(r4, r19, r11, Assembler::LSL, 20); // adds w4, w19, w11, LSL #20 -- __ subsw(r24, r7, r19, Assembler::ASR, 0); // subs w24, w7, w19, ASR #0 -- __ andr(r30, r7, r11, Assembler::LSL, 48); // and x30, x7, x11, LSL #48 -- __ orr(r24, r8, r15, Assembler::LSL, 12); // orr x24, x8, x15, LSL #12 -- __ eor(r17, r9, r23, Assembler::LSL, 1); // eor x17, x9, x23, LSL #1 -- __ ands(r14, r11, r4, Assembler::LSR, 55); // ands x14, x11, x4, LSR #55 -- __ andw(r19, r7, r12, Assembler::LSR, 17); // and w19, w7, w12, LSR #17 -- __ orrw(r19, r27, r11, Assembler::ASR, 28); // orr w19, w27, w11, ASR #28 -- __ eorw(r30, r3, r22, Assembler::LSR, 31); // eor w30, w3, w22, LSR #31 -- __ andsw(r19, r26, r28, Assembler::ASR, 0); // ands w19, w26, w28, ASR #0 -- __ bic(r29, r6, r26, Assembler::LSL, 51); // bic x29, x6, x26, LSL #51 -- __ orn(r26, r27, r17, Assembler::LSL, 35); // orn x26, x27, x17, LSL #35 -- __ eon(r21, r4, r14, Assembler::LSL, 5); // eon x21, x4, x14, LSL #5 -- __ bics(r2, r15, r0, Assembler::ASR, 5); // bics x2, x15, x0, ASR #5 -- __ bicw(r2, r7, r2, Assembler::LSL, 29); // bic w2, w7, w2, LSL #29 -- __ ornw(r24, r12, r21, Assembler::LSR, 5); // orn w24, w12, w21, LSR #5 -- __ eonw(r30, r15, r19, Assembler::LSL, 2); // eon w30, w15, w19, LSL #2 -- __ bicsw(r30, r23, r17, Assembler::ASR, 28); // bics w30, w23, w17, ASR #28 -+ __ add(r23, r1, r13, Assembler::LSR, 45); // add x23, x1, x13, LSR #45 -+ __ sub(r8, r30, r12, Assembler::ASR, 56); // sub x8, x30, x12, ASR #56 -+ __ adds(r27, r23, r14, Assembler::LSL, 54); // adds x27, x23, x14, LSL #54 -+ __ subs(r21, r15, r20, Assembler::LSR, 38); // subs x21, x15, x20, LSR #38 -+ __ addw(r25, r17, r4, Assembler::LSL, 3); // add w25, w17, w4, LSL #3 -+ __ subw(r29, r1, r9, Assembler::ASR, 20); // sub w29, w1, w9, ASR #20 -+ __ addsw(r10, r26, r9, Assembler::ASR, 9); // adds w10, w26, w9, ASR #9 -+ __ subsw(r21, r30, r7, Assembler::ASR, 3); // subs w21, w30, w7, ASR #3 -+ __ andr(r9, r8, r11, Assembler::LSR, 4); // and x9, x8, x11, LSR #4 -+ __ orr(r3, r18, r1, Assembler::ASR, 1); // orr x3, x18, x1, ASR #1 -+ __ eor(r10, r20, r2, Assembler::LSL, 27); // eor x10, x20, x2, LSL #27 -+ __ ands(r12, r9, r11, Assembler::ASR, 31); // ands x12, x9, x11, ASR #31 -+ __ andw(r20, r9, r30, Assembler::ASR, 26); // and w20, w9, w30, ASR #26 -+ __ orrw(r21, r10, r26, Assembler::ASR, 17); // orr w21, w10, w26, ASR #17 -+ __ eorw(r0, r8, r7, Assembler::ASR, 7); // eor w0, w8, w7, ASR #7 -+ __ andsw(r19, r11, r8, Assembler::LSL, 18); // ands w19, w11, w8, LSL #18 -+ __ bic(r23, r4, r3, Assembler::LSL, 53); // bic x23, x4, x3, LSL #53 -+ __ orn(r9, r6, r19, Assembler::LSL, 24); // orn x9, x6, x19, LSL #24 -+ __ eon(r12, r6, r26, Assembler::LSR, 54); // eon x12, x6, x26, LSR #54 -+ __ bics(r22, r19, r12, Assembler::LSL, 14); // bics x22, x19, x12, LSL #14 -+ __ bicw(r29, r13, r22, Assembler::LSL, 11); // bic w29, w13, w22, LSL #11 -+ __ ornw(r17, r30, r20, Assembler::ASR, 5); // orn w17, w30, w20, ASR #5 -+ __ eonw(r1, r29, r11, Assembler::LSL, 8); // eon w1, w29, w11, LSL #8 -+ __ bicsw(r4, r20, r6, Assembler::LSR, 29); // bics w4, w20, w6, LSR #29 +- __ add(r15, r0, r24, Assembler::LSL, 59); // add x15, x0, x24, LSL #59 +- __ sub(r17, r22, r22, Assembler::ASR, 13); // sub x17, x22, x22, ASR #13 +- __ adds(r10, r26, r28, Assembler::LSL, 57); // adds x10, x26, x28, LSL #57 +- __ subs(r25, r16, r24, Assembler::LSL, 18); // subs x25, x16, x24, LSL #18 +- __ addw(r8, r5, r28, Assembler::LSL, 7); // add w8, w5, w28, LSL #7 +- __ subw(r8, r28, r1, Assembler::ASR, 28); // sub w8, w28, w1, ASR #28 +- __ addsw(r12, r2, r1, Assembler::LSL, 0); // adds w12, w2, w1, LSL #0 +- __ subsw(r23, r5, r17, Assembler::LSR, 25); // subs w23, w5, w17, LSR #25 +- __ andr(r21, r12, r13, Assembler::LSL, 21); // and x21, x12, x13, LSL #21 +- __ orr(r21, r15, r23, Assembler::ASR, 36); // orr x21, x15, x23, ASR #36 +- __ eor(r22, r24, r27, Assembler::ASR, 48); // eor x22, x24, x27, ASR #48 +- __ ands(r22, r15, r2, Assembler::ASR, 52); // ands x22, x15, x2, ASR #52 +- __ andw(r1, r17, r24, Assembler::ASR, 3); // and w1, w17, w24, ASR #3 +- __ orrw(r5, r2, r6, Assembler::ASR, 11); // orr w5, w2, w6, ASR #11 +- __ eorw(r23, r1, r5, Assembler::LSR, 12); // eor w23, w1, w5, LSR #12 +- __ andsw(r0, r12, r14, Assembler::ASR, 20); // ands w0, w12, w14, ASR #20 +- __ bic(r1, r6, r2, Assembler::LSR, 7); // bic x1, x6, x2, LSR #7 +- __ orn(r30, r8, r4, Assembler::LSL, 47); // orn x30, x8, x4, LSL #47 +- __ eon(r17, r22, r20, Assembler::ASR, 53); // eon x17, x22, x20, ASR #53 +- __ bics(r29, r15, r5, Assembler::ASR, 36); // bics x29, x15, x5, ASR #36 +- __ bicw(r30, r23, r29, Assembler::LSR, 27); // bic w30, w23, w29, LSR #27 +- __ ornw(r12, r29, r2, Assembler::LSL, 20); // orn w12, w29, w2, LSL #20 +- __ eonw(r7, r12, r6, Assembler::ASR, 4); // eon w7, w12, w6, ASR #4 +- __ bicsw(r16, r13, r7, Assembler::ASR, 21); // bics w16, w13, w7, ASR #21 ++ __ add(r27, r27, r14, Assembler::ASR, 25); // add x27, x27, x14, ASR #25 ++ __ sub(r4, r11, r17, Assembler::LSR, 10); // sub x4, x11, x17, LSR #10 ++ __ adds(r7, r17, r25, Assembler::ASR, 33); // adds x7, x17, x25, ASR #33 ++ __ subs(r13, r22, r20, Assembler::ASR, 5); // subs x13, x22, x20, ASR #5 ++ __ addw(r10, r28, r3, Assembler::ASR, 16); // add w10, w28, w3, ASR #16 ++ __ subw(r21, r2, r6, Assembler::LSR, 15); // sub w21, w2, w6, LSR #15 ++ __ addsw(r6, r0, r27, Assembler::ASR, 9); // adds w6, w0, w27, ASR #9 ++ __ subsw(r5, r27, r8, Assembler::ASR, 10); // subs w5, w27, w8, ASR #10 ++ __ andr(r12, r4, r7, Assembler::ASR, 39); // and x12, x4, x7, ASR #39 ++ __ orr(r21, r27, r22, Assembler::LSL, 50); // orr x21, x27, x22, LSL #50 ++ __ eor(r3, r21, r0, Assembler::ASR, 46); // eor x3, x21, x0, ASR #46 ++ __ ands(r21, r10, r5, Assembler::ASR, 22); // ands x21, x10, x5, ASR #22 ++ __ andw(r13, r21, r29, Assembler::LSL, 22); // and w13, w21, w29, LSL #22 ++ __ orrw(r17, r10, r16, Assembler::LSR, 18); // orr w17, w10, w16, LSR #18 ++ __ eorw(r16, r7, r23, Assembler::ASR, 27); // eor w16, w7, w23, ASR #27 ++ __ andsw(r10, r6, r12, Assembler::ASR, 12); // ands w10, w6, w12, ASR #12 ++ __ bic(r19, r25, r7, Assembler::LSL, 22); // bic x19, x25, x7, LSL #22 ++ __ orn(r25, r2, r7, Assembler::LSL, 53); // orn x25, x2, x7, LSL #53 ++ __ eon(r9, r23, r23, Assembler::ASR, 3); // eon x9, x23, x23, ASR #3 ++ __ bics(r5, r6, r13, Assembler::ASR, 50); // bics x5, x6, x13, ASR #50 ++ __ bicw(r15, r21, r10, Assembler::LSL, 9); // bic w15, w21, w10, LSL #9 ++ __ ornw(r17, r21, r30, Assembler::ASR, 1); // orn w17, w21, w30, ASR #1 ++ __ eonw(r7, r28, r29, Assembler::LSL, 19); // eon w7, w28, w29, LSL #19 ++ __ bicsw(r25, r22, r22, Assembler::ASR, 12); // bics w25, w22, w22, ASR #12 // AddSubImmOp -- __ addw(r4, r20, 660u); // add w4, w20, #660 -- __ addsw(r2, r10, 710u); // adds w2, w10, #710 -- __ subw(r19, r26, 244u); // sub w19, w26, #244 -- __ subsw(r28, r13, 73u); // subs w28, w13, #73 -- __ add(r2, r30, 862u); // add x2, x30, #862 -- __ adds(r27, r16, 574u); // adds x27, x16, #574 -- __ sub(r22, r9, 589u); // sub x22, x9, #589 -- __ subs(r4, r1, 698u); // subs x4, x1, #698 -+ __ addw(r30, r6, 504u); // add w30, w6, #504 -+ __ addsw(r19, r8, 943u); // adds w19, w8, #943 -+ __ subw(r29, r10, 365u); // sub w29, w10, #365 -+ __ subsw(r4, r8, 284u); // subs w4, w8, #284 -+ __ add(r3, r14, 958u); // add x3, x14, #958 -+ __ adds(r22, r20, 167u); // adds x22, x20, #167 -+ __ sub(r27, r15, 725u); // sub x27, x15, #725 -+ __ subs(r24, r28, 947u); // subs x24, x28, #947 +- __ addw(r5, r17, 726u); // add w5, w17, #726 +- __ addsw(r10, r16, 347u); // adds w10, w16, #347 +- __ subw(r26, r5, 978u); // sub w26, w5, #978 +- __ subsw(r21, r24, 689u); // subs w21, w24, #689 +- __ add(r10, r16, 987u); // add x10, x16, #987 +- __ adds(r15, r15, 665u); // adds x15, x15, #665 +- __ sub(r24, r20, 39u); // sub x24, x20, #39 +- __ subs(r10, r13, 76u); // subs x10, x13, #76 ++ __ addw(r6, r26, 788u); // add w6, w26, #788 ++ __ addsw(r3, r17, 490u); // adds w3, w17, #490 ++ __ subw(r5, r21, 507u); // sub w5, w21, #507 ++ __ subsw(r22, r27, 883u); // subs w22, w27, #883 ++ __ add(r12, r8, 244u); // add x12, x8, #244 ++ __ adds(r29, r8, 928u); // adds x29, x8, #928 ++ __ sub(r26, r3, 642u); // sub x26, x3, #642 ++ __ subs(r29, r15, 628u); // subs x29, x15, #628 // LogicalImmOp -- __ andw(r28, r19, 4294709247ull); // and w28, w19, #0xfffc0fff -- __ orrw(r27, r5, 536870910ull); // orr w27, w5, #0x1ffffffe -- __ eorw(r30, r20, 4294840319ull); // eor w30, w20, #0xfffe0fff -- __ andsw(r22, r26, 4294959615ull); // ands w22, w26, #0xffffe1ff -- __ andr(r5, r7, 4194300ull); // and x5, x7, #0x3ffffc -- __ orr(r13, r7, 18014398509481728ull); // orr x13, x7, #0x3fffffffffff00 -- __ eor(r7, r9, 18442240474082197503ull); // eor x7, x9, #0xfff0000000003fff -- __ ands(r3, r0, 18374686479671656447ull); // ands x3, x0, #0xff00000000007fff -+ __ andw(r25, r25, 2139127680ull); // and w25, w25, #0x7f807f80 -+ __ orrw(r13, r26, 2097120ull); // orr w13, w26, #0x1fffe0 -+ __ eorw(r21, r13, 3758096384ull); // eor w21, w13, #0xe0000000 -+ __ andsw(r2, r3, 1073733632ull); // ands w2, w3, #0x3fffe000 -+ __ andr(r8, r10, 1125895612137471ull); // and x8, x10, #0x3ffff0003ffff -+ __ orr(r27, r16, 18444492273897963519ull); // orr x27, x16, #0xfff80000001fffff -+ __ eor(r27, r3, 4611685469745315712ull); // eor x27, x3, #0x3fffff803fffff80 -+ __ ands(r4, r23, 18446744056529698815ull); // ands x4, x23, #0xfffffffc00003fff +- __ andw(r7, r19, 8388600ull); // and w7, w19, #0x7ffff8 +- __ orrw(r5, r17, 4026535935ull); // orr w5, w17, #0xf0000fff +- __ eorw(r16, r28, 4186112ull); // eor w16, w28, #0x3fe000 +- __ andsw(r14, r24, 7168ull); // ands w14, w24, #0x1c00 +- __ andr(r14, r27, 18446744073709543551ull); // and x14, x27, #0xffffffffffffe07f +- __ orr(r12, r11, 576456354256912384ull); // orr x12, x11, #0x7fffc0000000000 +- __ eor(r2, r0, 18437736874454811647ull); // eor x2, x0, #0xffe00000000003ff +- __ ands(r13, r20, 18446744073642573823ull); // ands x13, x20, #0xfffffffffc01ffff ++ __ andw(r21, r30, 4287102855ull); // and w21, w30, #0xff87ff87 ++ __ orrw(r21, r12, 2139127680ull); // orr w21, w12, #0x7f807f80 ++ __ eorw(r11, r17, 3233857728ull); // eor w11, w17, #0xc0c0c0c0 ++ __ andsw(r26, r30, 1056980736ull); // ands w26, w30, #0x3f003f00 ++ __ andr(r25, r23, 18445618178097414144ull); // and x25, x23, #0xfffc0000fffc0000 ++ __ orr(r30, r14, 16429131440647569407ull); // orr x30, x14, #0xe3ffffffffffffff ++ __ eor(r26, r4, 18446744073172942847ull); // eor x26, x4, #0xffffffffe003ffff ++ __ ands(r26, r0, 18446181398634037247ull); // ands x26, x0, #0xfffe003fffffffff // AbsOp -- __ b(__ pc()); // b . -- __ b(back); // b back -- __ b(forth); // b forth -- __ bl(__ pc()); // bl . -- __ bl(back); // bl back -- __ bl(forth); // bl forth +- __ b(__ pc()); // b . +- __ b(back); // b back +- __ b(forth); // b forth +- __ bl(__ pc()); // bl . +- __ bl(back); // bl back +- __ bl(forth); // bl forth + __ b(__ pc()); // b . + __ b(back); // b back + __ b(forth); // b forth @@ -3353,142 +2496,142 @@ index 2a17d8e0f..943d2a615 100644 + __ bl(forth); // bl forth // RegAndAbsOp -- __ cbzw(r16, __ pc()); // cbz w16, . -- __ cbzw(r16, back); // cbz w16, back -- __ cbzw(r16, forth); // cbz w16, forth -- __ cbnzw(r19, __ pc()); // cbnz w19, . -- __ cbnzw(r19, back); // cbnz w19, back -- __ cbnzw(r19, forth); // cbnz w19, forth -- __ cbz(r5, __ pc()); // cbz x5, . -- __ cbz(r5, back); // cbz x5, back -- __ cbz(r5, forth); // cbz x5, forth -- __ cbnz(r4, __ pc()); // cbnz x4, . -- __ cbnz(r4, back); // cbnz x4, back -- __ cbnz(r4, forth); // cbnz x4, forth -- __ adr(r27, __ pc()); // adr x27, . -- __ adr(r27, back); // adr x27, back -- __ adr(r27, forth); // adr x27, forth -- __ _adrp(r16, __ pc()); // adrp x16, . -+ __ cbzw(r3, __ pc()); // cbz w3, . -+ __ cbzw(r3, back); // cbz w3, back -+ __ cbzw(r3, forth); // cbz w3, forth -+ __ cbnzw(r2, __ pc()); // cbnz w2, . -+ __ cbnzw(r2, back); // cbnz w2, back -+ __ cbnzw(r2, forth); // cbnz w2, forth +- __ cbzw(r15, __ pc()); // cbz w15, . +- __ cbzw(r15, back); // cbz w15, back +- __ cbzw(r15, forth); // cbz w15, forth +- __ cbnzw(r28, __ pc()); // cbnz w28, . +- __ cbnzw(r28, back); // cbnz w28, back +- __ cbnzw(r28, forth); // cbnz w28, forth +- __ cbz(r27, __ pc()); // cbz x27, . +- __ cbz(r27, back); // cbz x27, back +- __ cbz(r27, forth); // cbz x27, forth +- __ cbnz(r0, __ pc()); // cbnz x0, . +- __ cbnz(r0, back); // cbnz x0, back +- __ cbnz(r0, forth); // cbnz x0, forth +- __ adr(r13, __ pc()); // adr x13, . +- __ adr(r13, back); // adr x13, back +- __ adr(r13, forth); // adr x13, forth +- __ _adrp(r3, __ pc()); // adrp x3, . ++ __ cbzw(r28, __ pc()); // cbz w28, . ++ __ cbzw(r28, back); // cbz w28, back ++ __ cbzw(r28, forth); // cbz w28, forth ++ __ cbnzw(r17, __ pc()); // cbnz w17, . ++ __ cbnzw(r17, back); // cbnz w17, back ++ __ cbnzw(r17, forth); // cbnz w17, forth + __ cbz(r25, __ pc()); // cbz x25, . + __ cbz(r25, back); // cbz x25, back + __ cbz(r25, forth); // cbz x25, forth -+ __ cbnz(r18, __ pc()); // cbnz x18, . -+ __ cbnz(r18, back); // cbnz x18, back -+ __ cbnz(r18, forth); // cbnz x18, forth -+ __ adr(r8, __ pc()); // adr x8, . -+ __ adr(r8, back); // adr x8, back -+ __ adr(r8, forth); // adr x8, forth -+ __ _adrp(r15, __ pc()); // adrp x15, . ++ __ cbnz(r2, __ pc()); // cbnz x2, . ++ __ cbnz(r2, back); // cbnz x2, back ++ __ cbnz(r2, forth); // cbnz x2, forth ++ __ adr(r29, __ pc()); // adr x29, . ++ __ adr(r29, back); // adr x29, back ++ __ adr(r29, forth); // adr x29, forth ++ __ _adrp(r29, __ pc()); // adrp x29, . // RegImmAbsOp -- __ tbz(r28, 8, __ pc()); // tbz x28, #8, . -- __ tbz(r28, 8, back); // tbz x28, #8, back -- __ tbz(r28, 8, forth); // tbz x28, #8, forth -- __ tbnz(r1, 1, __ pc()); // tbnz x1, #1, . -- __ tbnz(r1, 1, back); // tbnz x1, #1, back -- __ tbnz(r1, 1, forth); // tbnz x1, #1, forth -+ __ tbz(r18, 14, __ pc()); // tbz x18, #14, . -+ __ tbz(r18, 14, back); // tbz x18, #14, back -+ __ tbz(r18, 14, forth); // tbz x18, #14, forth -+ __ tbnz(r25, 15, __ pc()); // tbnz x25, #15, . -+ __ tbnz(r25, 15, back); // tbnz x25, #15, back -+ __ tbnz(r25, 15, forth); // tbnz x25, #15, forth +- __ tbz(r21, 7, __ pc()); // tbz x21, #7, . +- __ tbz(r21, 7, back); // tbz x21, #7, back +- __ tbz(r21, 7, forth); // tbz x21, #7, forth +- __ tbnz(r15, 9, __ pc()); // tbnz x15, #9, . +- __ tbnz(r15, 9, back); // tbnz x15, #9, back +- __ tbnz(r15, 9, forth); // tbnz x15, #9, forth ++ __ tbz(r6, 6, __ pc()); // tbz x6, #6, . ++ __ tbz(r6, 6, back); // tbz x6, #6, back ++ __ tbz(r6, 6, forth); // tbz x6, #6, forth ++ __ tbnz(r21, 2, __ pc()); // tbnz x21, #2, . ++ __ tbnz(r21, 2, back); // tbnz x21, #2, back ++ __ tbnz(r21, 2, forth); // tbnz x21, #2, forth // MoveWideImmOp -- __ movnw(r20, 8639, 16); // movn w20, #8639, lsl 16 -- __ movzw(r7, 25835, 0); // movz w7, #25835, lsl 0 -- __ movkw(r17, 7261, 0); // movk w17, #7261, lsl 0 -- __ movn(r14, 2097, 32); // movn x14, #2097, lsl 32 -- __ movz(r9, 16082, 0); // movz x9, #16082, lsl 0 -- __ movk(r19, 13962, 16); // movk x19, #13962, lsl 16 -+ __ movnw(r18, 4126, 16); // movn w18, #4126, lsl 16 -+ __ movzw(r30, 13712, 0); // movz w30, #13712, lsl 0 -+ __ movkw(r21, 13161, 16); // movk w21, #13161, lsl 16 -+ __ movn(r18, 28524, 48); // movn x18, #28524, lsl 48 -+ __ movz(r13, 30710, 48); // movz x13, #30710, lsl 48 -+ __ movk(r3, 31565, 48); // movk x3, #31565, lsl 48 +- __ movnw(r14, 2655, 16); // movn w14, #2655, lsl 16 +- __ movzw(r17, 7642, 0); // movz w17, #7642, lsl 0 +- __ movkw(r27, 11381, 0); // movk w27, #11381, lsl 0 +- __ movn(r1, 19524, 32); // movn x1, #19524, lsl 32 +- __ movz(r20, 21126, 16); // movz x20, #21126, lsl 16 +- __ movk(r20, 32462, 16); // movk x20, #32462, lsl 16 ++ __ movnw(r8, 2735, 0); // movn w8, #2735, lsl 0 ++ __ movzw(r11, 11185, 16); // movz w11, #11185, lsl 16 ++ __ movkw(r26, 26028, 16); // movk w26, #26028, lsl 16 ++ __ movn(r13, 13140, 0); // movn x13, #13140, lsl 0 ++ __ movz(r6, 5829, 48); // movz x6, #5829, lsl 48 ++ __ movk(r16, 10786, 32); // movk x16, #10786, lsl 32 // BitfieldOp -- __ sbfm(r9, r22, 6, 22); // sbfm x9, x22, #6, #22 -- __ bfmw(r19, r0, 11, 0); // bfm w19, w0, #11, #0 -- __ ubfmw(r10, r19, 11, 19); // ubfm w10, w19, #11, #19 -- __ sbfm(r4, r15, 5, 17); // sbfm x4, x15, #5, #17 -- __ bfm(r3, r5, 19, 28); // bfm x3, x5, #19, #28 -- __ ubfm(r12, r28, 17, 2); // ubfm x12, x28, #17, #2 -+ __ sbfm(r10, r1, 0, 3); // sbfm x10, x1, #0, #3 -+ __ bfmw(r12, r22, 5, 24); // bfm w12, w22, #5, #24 -+ __ ubfmw(r17, r3, 11, 8); // ubfm w17, w3, #11, #8 -+ __ sbfm(r0, r3, 11, 14); // sbfm x0, x3, #11, #14 -+ __ bfm(r28, r6, 7, 15); // bfm x28, x6, #7, #15 -+ __ ubfm(r9, r10, 1, 25); // ubfm x9, x10, #1, #25 +- __ sbfm(r13, r2, 28, 20); // sbfm x13, x2, #28, #20 +- __ bfmw(r16, r20, 19, 15); // bfm w16, w20, #19, #15 +- __ ubfmw(r11, r11, 9, 6); // ubfm w11, w11, #9, #6 +- __ sbfm(r2, r4, 25, 21); // sbfm x2, x4, #25, #21 +- __ bfm(r13, r16, 2, 19); // bfm x13, x16, #2, #19 +- __ ubfm(r8, r25, 8, 5); // ubfm x8, x25, #8, #5 ++ __ sbfm(r30, r30, 17, 26); // sbfm x30, x30, #17, #26 ++ __ bfmw(r4, r9, 15, 12); // bfm w4, w9, #15, #12 ++ __ ubfmw(r15, r20, 1, 5); // ubfm w15, w20, #1, #5 ++ __ sbfm(r27, r8, 19, 14); // sbfm x27, x8, #19, #14 ++ __ bfm(r30, r0, 21, 29); // bfm x30, x0, #21, #29 ++ __ ubfm(r27, r26, 22, 11); // ubfm x27, x26, #22, #11 // ExtractOp -- __ extrw(r15, r0, r22, 3); // extr w15, w0, w22, #3 -- __ extr(r6, r14, r14, 55); // extr x6, x14, x14, #55 -+ __ extrw(r21, r27, r25, 23); // extr w21, w27, w25, #23 -+ __ extr(r14, r17, r22, 17); // extr x14, x17, x22, #17 +- __ extrw(r29, r27, r10, 14); // extr w29, w27, w10, #14 +- __ extr(r6, r20, r6, 24); // extr x6, x20, x6, #24 ++ __ extrw(r12, r12, r6, 27); // extr w12, w12, w6, #27 ++ __ extr(r19, r13, r22, 45); // extr x19, x13, x22, #45 // CondBranchOp -- __ br(Assembler::EQ, __ pc()); // b.EQ . -- __ br(Assembler::EQ, back); // b.EQ back -- __ br(Assembler::EQ, forth); // b.EQ forth -- __ br(Assembler::NE, __ pc()); // b.NE . -- __ br(Assembler::NE, back); // b.NE back -- __ br(Assembler::NE, forth); // b.NE forth -- __ br(Assembler::HS, __ pc()); // b.HS . -- __ br(Assembler::HS, back); // b.HS back -- __ br(Assembler::HS, forth); // b.HS forth -- __ br(Assembler::CS, __ pc()); // b.CS . -- __ br(Assembler::CS, back); // b.CS back -- __ br(Assembler::CS, forth); // b.CS forth -- __ br(Assembler::LO, __ pc()); // b.LO . -- __ br(Assembler::LO, back); // b.LO back -- __ br(Assembler::LO, forth); // b.LO forth -- __ br(Assembler::CC, __ pc()); // b.CC . -- __ br(Assembler::CC, back); // b.CC back -- __ br(Assembler::CC, forth); // b.CC forth -- __ br(Assembler::MI, __ pc()); // b.MI . -- __ br(Assembler::MI, back); // b.MI back -- __ br(Assembler::MI, forth); // b.MI forth -- __ br(Assembler::PL, __ pc()); // b.PL . -- __ br(Assembler::PL, back); // b.PL back -- __ br(Assembler::PL, forth); // b.PL forth -- __ br(Assembler::VS, __ pc()); // b.VS . -- __ br(Assembler::VS, back); // b.VS back -- __ br(Assembler::VS, forth); // b.VS forth -- __ br(Assembler::VC, __ pc()); // b.VC . -- __ br(Assembler::VC, back); // b.VC back -- __ br(Assembler::VC, forth); // b.VC forth -- __ br(Assembler::HI, __ pc()); // b.HI . -- __ br(Assembler::HI, back); // b.HI back -- __ br(Assembler::HI, forth); // b.HI forth -- __ br(Assembler::LS, __ pc()); // b.LS . -- __ br(Assembler::LS, back); // b.LS back -- __ br(Assembler::LS, forth); // b.LS forth -- __ br(Assembler::GE, __ pc()); // b.GE . -- __ br(Assembler::GE, back); // b.GE back -- __ br(Assembler::GE, forth); // b.GE forth -- __ br(Assembler::LT, __ pc()); // b.LT . -- __ br(Assembler::LT, back); // b.LT back -- __ br(Assembler::LT, forth); // b.LT forth -- __ br(Assembler::GT, __ pc()); // b.GT . -- __ br(Assembler::GT, back); // b.GT back -- __ br(Assembler::GT, forth); // b.GT forth -- __ br(Assembler::LE, __ pc()); // b.LE . -- __ br(Assembler::LE, back); // b.LE back -- __ br(Assembler::LE, forth); // b.LE forth -- __ br(Assembler::AL, __ pc()); // b.AL . -- __ br(Assembler::AL, back); // b.AL back -- __ br(Assembler::AL, forth); // b.AL forth -- __ br(Assembler::NV, __ pc()); // b.NV . -- __ br(Assembler::NV, back); // b.NV back -- __ br(Assembler::NV, forth); // b.NV forth +- __ br(Assembler::EQ, __ pc()); // b.EQ . +- __ br(Assembler::EQ, back); // b.EQ back +- __ br(Assembler::EQ, forth); // b.EQ forth +- __ br(Assembler::NE, __ pc()); // b.NE . +- __ br(Assembler::NE, back); // b.NE back +- __ br(Assembler::NE, forth); // b.NE forth +- __ br(Assembler::HS, __ pc()); // b.HS . +- __ br(Assembler::HS, back); // b.HS back +- __ br(Assembler::HS, forth); // b.HS forth +- __ br(Assembler::CS, __ pc()); // b.CS . +- __ br(Assembler::CS, back); // b.CS back +- __ br(Assembler::CS, forth); // b.CS forth +- __ br(Assembler::LO, __ pc()); // b.LO . +- __ br(Assembler::LO, back); // b.LO back +- __ br(Assembler::LO, forth); // b.LO forth +- __ br(Assembler::CC, __ pc()); // b.CC . +- __ br(Assembler::CC, back); // b.CC back +- __ br(Assembler::CC, forth); // b.CC forth +- __ br(Assembler::MI, __ pc()); // b.MI . +- __ br(Assembler::MI, back); // b.MI back +- __ br(Assembler::MI, forth); // b.MI forth +- __ br(Assembler::PL, __ pc()); // b.PL . +- __ br(Assembler::PL, back); // b.PL back +- __ br(Assembler::PL, forth); // b.PL forth +- __ br(Assembler::VS, __ pc()); // b.VS . +- __ br(Assembler::VS, back); // b.VS back +- __ br(Assembler::VS, forth); // b.VS forth +- __ br(Assembler::VC, __ pc()); // b.VC . +- __ br(Assembler::VC, back); // b.VC back +- __ br(Assembler::VC, forth); // b.VC forth +- __ br(Assembler::HI, __ pc()); // b.HI . +- __ br(Assembler::HI, back); // b.HI back +- __ br(Assembler::HI, forth); // b.HI forth +- __ br(Assembler::LS, __ pc()); // b.LS . +- __ br(Assembler::LS, back); // b.LS back +- __ br(Assembler::LS, forth); // b.LS forth +- __ br(Assembler::GE, __ pc()); // b.GE . +- __ br(Assembler::GE, back); // b.GE back +- __ br(Assembler::GE, forth); // b.GE forth +- __ br(Assembler::LT, __ pc()); // b.LT . +- __ br(Assembler::LT, back); // b.LT back +- __ br(Assembler::LT, forth); // b.LT forth +- __ br(Assembler::GT, __ pc()); // b.GT . +- __ br(Assembler::GT, back); // b.GT back +- __ br(Assembler::GT, forth); // b.GT forth +- __ br(Assembler::LE, __ pc()); // b.LE . +- __ br(Assembler::LE, back); // b.LE back +- __ br(Assembler::LE, forth); // b.LE forth +- __ br(Assembler::AL, __ pc()); // b.AL . +- __ br(Assembler::AL, back); // b.AL back +- __ br(Assembler::AL, forth); // b.AL forth +- __ br(Assembler::NV, __ pc()); // b.NV . +- __ br(Assembler::NV, back); // b.NV back +- __ br(Assembler::NV, forth); // b.NV forth + __ br(Assembler::EQ, __ pc()); // b.EQ . + __ br(Assembler::EQ, back); // b.EQ back + __ br(Assembler::EQ, forth); // b.EQ forth @@ -3545,676 +2688,676 @@ index 2a17d8e0f..943d2a615 100644 + __ br(Assembler::NV, forth); // b.NV forth // ImmOp -- __ svc(22064); // svc #22064 -- __ hvc(533); // hvc #533 -- __ smc(9942); // smc #9942 -- __ brk(4714); // brk #4714 -- __ hlt(4302); // hlt #4302 -+ __ svc(31973); // svc #31973 -+ __ hvc(1113); // hvc #1113 -+ __ smc(24334); // smc #24334 -+ __ brk(7815); // brk #7815 -+ __ hlt(28529); // hlt #28529 +- __ svc(26948); // svc #26948 +- __ hvc(29998); // hvc #29998 +- __ smc(10437); // smc #10437 +- __ brk(30290); // brk #30290 +- __ hlt(20851); // hlt #20851 ++ __ svc(16084); // svc #16084 ++ __ hvc(5802); // hvc #5802 ++ __ smc(14039); // smc #14039 ++ __ brk(11389); // brk #11389 ++ __ hlt(27339); // hlt #27339 // Op -- __ nop(); // nop -- __ eret(); // eret -- __ drps(); // drps -- __ isb(); // isb +- __ nop(); // nop +- __ eret(); // eret +- __ drps(); // drps +- __ isb(); // isb + __ nop(); // nop + __ eret(); // eret + __ drps(); // drps + __ isb(); // isb // SystemOp -- __ dsb(Assembler::OSH); // dsb OSH -- __ dmb(Assembler::NSHLD); // dmb NSHLD -+ __ dsb(Assembler::NSHLD); // dsb NSHLD -+ __ dmb(Assembler::NSH); // dmb NSH +- __ dsb(Assembler::LD); // dsb LD +- __ dmb(Assembler::ISH); // dmb ISH ++ __ dsb(Assembler::OSH); // dsb OSH ++ __ dmb(Assembler::NSHST); // dmb NSHST // OneRegOp -- __ br(r20); // br x20 -- __ blr(r2); // blr x2 -+ __ br(r28); // br x28 -+ __ blr(r17); // blr x17 +- __ br(r9); // br x9 +- __ blr(r9); // blr x9 ++ __ br(r11); // br x11 ++ __ blr(r25); // blr x25 // LoadStoreExclusiveOp -- __ stxr(r18, r23, r0); // stxr w18, x23, [x0] -- __ stlxr(r30, r5, r22); // stlxr w30, x5, [x22] -- __ ldxr(r5, r8); // ldxr x5, [x8] -- __ ldaxr(r20, r16); // ldaxr x20, [x16] -- __ stlr(r6, r11); // stlr x6, [x11] -- __ ldar(r6, r27); // ldar x6, [x27] -+ __ stxr(r18, r7, r26); // stxr w18, x7, [x26] -+ __ stlxr(r25, r12, r6); // stlxr w25, x12, [x6] -+ __ ldxr(r0, r16); // ldxr x0, [x16] -+ __ ldaxr(r6, r3); // ldaxr x6, [x3] -+ __ stlr(r14, r1); // stlr x14, [x1] -+ __ ldar(r29, r24); // ldar x29, [x24] +- __ stxr(r2, r29, r11); // stxr w2, x29, [x11] +- __ stlxr(r22, r5, r28); // stlxr w22, x5, [x28] +- __ ldxr(r14, r20); // ldxr x14, [x20] +- __ ldaxr(r29, r19); // ldaxr x29, [x19] +- __ stlr(r6, r21); // stlr x6, [x21] +- __ ldar(r19, r3); // ldar x19, [x3] ++ __ stxr(r14, r15, r13); // stxr w14, x15, [x13] ++ __ stlxr(r30, r25, r1); // stlxr w30, x25, [x1] ++ __ ldxr(r13, r3); // ldxr x13, [x3] ++ __ ldaxr(r8, r21); // ldaxr x8, [x21] ++ __ stlr(r13, r28); // stlr x13, [x28] ++ __ ldar(r8, r30); // ldar x8, [x30] // LoadStoreExclusiveOp -- __ stxrw(r10, r17, r5); // stxr w10, w17, [x5] -- __ stlxrw(r22, r9, r12); // stlxr w22, w9, [x12] -- __ ldxrw(r27, r8); // ldxr w27, [x8] -- __ ldaxrw(r23, r2); // ldaxr w23, [x2] -- __ stlrw(r26, r29); // stlr w26, [x29] -- __ ldarw(r13, r10); // ldar w13, [x10] -+ __ stxrw(r28, r15, r23); // stxr w28, w15, [x23] -+ __ stlxrw(r9, r7, r3); // stlxr w9, w7, [x3] -+ __ ldxrw(r1, r20); // ldxr w1, [x20] -+ __ ldaxrw(r20, r15); // ldaxr w20, [x15] -+ __ stlrw(r21, r9); // stlr w21, [x9] -+ __ ldarw(r5, r17); // ldar w5, [x17] +- __ stxrw(r12, r3, r27); // stxr w12, w3, [x27] +- __ stlxrw(r17, r26, r15); // stlxr w17, w26, [x15] +- __ ldxrw(r13, r14); // ldxr w13, [x14] +- __ ldaxrw(r12, r26); // ldaxr w12, [x26] +- __ stlrw(r8, r17); // stlr w8, [x17] +- __ ldarw(r21, r30); // ldar w21, [x30] ++ __ stxrw(r13, r17, r28); // stxr w13, w17, [x28] ++ __ stlxrw(r21, r17, r19); // stlxr w21, w17, [x19] ++ __ ldxrw(r3, r8); // ldxr w3, [x8] ++ __ ldaxrw(r29, r21); // ldaxr w29, [x21] ++ __ stlrw(r9, r24); // stlr w9, [x24] ++ __ ldarw(r2, r6); // ldar w2, [x6] // LoadStoreExclusiveOp -- __ stxrh(r25, r28, r27); // stxrh w25, w28, [x27] -- __ stlxrh(r29, r22, r12); // stlxrh w29, w22, [x12] -- __ ldxrh(r22, r28); // ldxrh w22, [x28] -- __ ldaxrh(r3, r30); // ldaxrh w3, [x30] -- __ stlrh(r24, r15); // stlrh w24, [x15] -- __ ldarh(r27, r26); // ldarh w27, [x26] -+ __ stxrh(r13, r20, r30); // stxrh w13, w20, [x30] -+ __ stlxrh(r10, r12, r18); // stlxrh w10, w12, [x18] -+ __ ldxrh(r4, r19); // ldxrh w4, [x19] -+ __ ldaxrh(r22, r10); // ldaxrh w22, [x10] -+ __ stlrh(r30, r15); // stlrh w30, [x15] -+ __ ldarh(r4, r24); // ldarh w4, [x24] +- __ stxrh(r0, r15, r11); // stxrh w0, w15, [x11] +- __ stlxrh(r17, r20, r1); // stlxrh w17, w20, [x1] +- __ ldxrh(r29, r8); // ldxrh w29, [x8] +- __ ldaxrh(r17, r12); // ldaxrh w17, [x12] +- __ stlrh(r11, r4); // stlrh w11, [x4] +- __ ldarh(r16, r4); // ldarh w16, [x4] ++ __ stxrh(r12, r20, r16); // stxrh w12, w20, [x16] ++ __ stlxrh(r2, r28, r5); // stlxrh w2, w28, [x5] ++ __ ldxrh(r1, r3); // ldxrh w1, [x3] ++ __ ldaxrh(r24, r13); // ldaxrh w24, [x13] ++ __ stlrh(r15, r25); // stlrh w15, [x25] ++ __ ldarh(r10, r20); // ldarh w10, [x20] // LoadStoreExclusiveOp -- __ stxrb(r11, r10, r19); // stxrb w11, w10, [x19] -- __ stlxrb(r23, r27, r22); // stlxrb w23, w27, [x22] -- __ ldxrb(r24, r16); // ldxrb w24, [x16] -- __ ldaxrb(r24, r1); // ldaxrb w24, [x1] -- __ stlrb(r5, r29); // stlrb w5, [x29] -- __ ldarb(r24, r16); // ldarb w24, [x16] -+ __ stxrb(r10, r20, r12); // stxrb w10, w20, [x12] -+ __ stlxrb(r20, r29, r11); // stlxrb w20, w29, [x11] -+ __ ldxrb(r21, r5); // ldxrb w21, [x5] -+ __ ldaxrb(r4, r9); // ldaxrb w4, [x9] -+ __ stlrb(r30, r28); // stlrb w30, [x28] -+ __ ldarb(r19, r24); // ldarb w19, [x24] +- __ stxrb(r14, r5, r4); // stxrb w14, w5, [x4] +- __ stlxrb(r27, r17, r16); // stlxrb w27, w17, [x16] +- __ ldxrb(r6, r27); // ldxrb w6, [x27] +- __ ldaxrb(r27, r24); // ldaxrb w27, [x24] +- __ stlrb(r10, r20); // stlrb w10, [x20] +- __ ldarb(r9, r26); // ldarb w9, [x26] ++ __ stxrb(r5, r16, r13); // stxrb w5, w16, [x13] ++ __ stlxrb(r10, r15, r17); // stlxrb w10, w15, [x17] ++ __ ldxrb(r17, r19); // ldxrb w17, [x19] ++ __ ldaxrb(r30, r9); // ldaxrb w30, [x9] ++ __ stlrb(r20, r24); // stlrb w20, [x24] ++ __ ldarb(r10, r4); // ldarb w10, [x4] // LoadStoreExclusiveOp -- __ ldxp(r25, r24, r17); // ldxp x25, x24, [x17] -- __ ldaxp(r22, r12, r19); // ldaxp x22, x12, [x19] -- __ stxp(r0, r26, r21, r25); // stxp w0, x26, x21, [x25] -- __ stlxp(r1, r6, r11, r5); // stlxp w1, x6, x11, [x5] -+ __ ldxp(r11, r16, r18); // ldxp x11, x16, [x18] -+ __ ldaxp(r8, r7, r15); // ldaxp x8, x7, [x15] -+ __ stxp(r28, r20, r16, r10); // stxp w28, x20, x16, [x10] -+ __ stlxp(r7, r9, r21, r3); // stlxp w7, x9, x21, [x3] +- __ ldxp(r5, r30, r28); // ldxp x5, x30, [x28] +- __ ldaxp(r10, r9, r19); // ldaxp x10, x9, [x19] +- __ stxp(r11, r16, r21, r12); // stxp w11, x16, x21, [x12] +- __ stlxp(r10, r20, r23, r4); // stlxp w10, x20, x23, [x4] ++ __ ldxp(r25, r8, r9); // ldxp x25, x8, [x9] ++ __ ldaxp(r7, r10, r16); // ldaxp x7, x10, [x16] ++ __ stxp(r25, r16, r11, r9); // stxp w25, x16, x11, [x9] ++ __ stlxp(r7, r5, r9, r15); // stlxp w7, x5, x9, [x15] // LoadStoreExclusiveOp -- __ ldxpw(r13, r14, r4); // ldxp w13, w14, [x4] -- __ ldaxpw(r17, r2, r6); // ldaxp w17, w2, [x6] -- __ stxpw(r15, r3, r9, r18); // stxp w15, w3, w9, [x18] -- __ stlxpw(r18, r17, r4, r9); // stlxp w18, w17, w4, [x9] -+ __ ldxpw(r25, r6, r19); // ldxp w25, w6, [x19] -+ __ ldaxpw(r30, r9, r2); // ldaxp w30, w9, [x2] -+ __ stxpw(r16, r0, r20, r12); // stxp w16, w0, w20, [x12] -+ __ stlxpw(r5, r2, r7, r28); // stlxp w5, w2, w7, [x28] +- __ ldxpw(r22, r1, r0); // ldxp w22, w1, [x0] +- __ ldaxpw(r3, r1, r8); // ldaxp w3, w1, [x8] +- __ stxpw(r0, r9, r23, r30); // stxp w0, w9, w23, [x30] +- __ stlxpw(r23, r0, r17, r11); // stlxp w23, w0, w17, [x11] ++ __ ldxpw(r12, r4, r3); // ldxp w12, w4, [x3] ++ __ ldaxpw(r17, r2, r5); // ldaxp w17, w2, [x5] ++ __ stxpw(r4, r8, r24, r6); // stxp w4, w8, w24, [x6] ++ __ stlxpw(r4, r12, r25, r16); // stlxp w4, w12, w25, [x16] -// base_plus_unscaled_offset +// base_plus_unscaled_offset // LoadStoreOp -- __ str(r23, Address(r21, -49)); // str x23, [x21, -49] -- __ strw(r21, Address(r2, 63)); // str w21, [x2, 63] -- __ strb(r27, Address(r28, 11)); // strb w27, [x28, 11] -- __ strh(r29, Address(r15, -13)); // strh w29, [x15, -13] -- __ ldr(r14, Address(r30, -45)); // ldr x14, [x30, -45] -- __ ldrw(r29, Address(r28, 53)); // ldr w29, [x28, 53] -- __ ldrb(r20, Address(r26, 7)); // ldrb w20, [x26, 7] -- __ ldrh(r25, Address(r2, -50)); // ldrh w25, [x2, -50] -- __ ldrsb(r3, Address(r10, -15)); // ldrsb x3, [x10, -15] -- __ ldrsh(r14, Address(r15, 19)); // ldrsh x14, [x15, 19] -- __ ldrshw(r29, Address(r11, -5)); // ldrsh w29, [x11, -5] -- __ ldrsw(r15, Address(r5, -71)); // ldrsw x15, [x5, -71] -- __ ldrd(v19, Address(r12, 3)); // ldr d19, [x12, 3] -- __ ldrs(v12, Address(r27, 42)); // ldr s12, [x27, 42] -- __ strd(v22, Address(r28, 125)); // str d22, [x28, 125] -- __ strs(v24, Address(r15, -20)); // str s24, [x15, -20] +- __ str(r6, Address(r10, -31)); // str x6, [x10, -31] +- __ strw(r7, Address(r0, -5)); // str w7, [x0, -5] +- __ strb(r5, Address(r16, -13)); // strb w5, [x16, -13] +- __ strh(r30, Address(r19, 31)); // strh w30, [x19, 31] +- __ ldr(r16, Address(r9, 119)); // ldr x16, [x9, 119] +- __ ldrw(r8, Address(r16, 59)); // ldr w8, [x16, 59] +- __ ldrb(r10, Address(r12, -7)); // ldrb w10, [x12, -7] +- __ ldrh(r14, Address(r9, -38)); // ldrh w14, [x9, -38] +- __ ldrsb(r24, Address(r30, -8)); // ldrsb x24, [x30, -8] +- __ ldrsh(r7, Address(r4, 23)); // ldrsh x7, [x4, 23] +- __ ldrshw(r17, Address(r14, -39)); // ldrsh w17, [x14, -39] +- __ ldrsw(r11, Address(r27, -31)); // ldrsw x11, [x27, -31] +- __ ldrd(v12, Address(r7, 65)); // ldr d12, [x7, 65] +- __ ldrs(v0, Address(r16, -2)); // ldr s0, [x16, -2] +- __ strd(v13, Address(r23, -161)); // str d13, [x23, -161] +- __ strs(v21, Address(r3, -62)); // str s21, [x3, -62] - -// pre -+ __ str(r16, Address(r19, -75)); // str x16, [x19, -75] -+ __ strw(r1, Address(r28, 30)); // str w1, [x28, 30] -+ __ strb(r28, Address(r13, -26)); // strb w28, [x13, -26] -+ __ strh(r8, Address(r6, -51)); // strh w8, [x6, -51] -+ __ ldr(r0, Address(r28, -227)); // ldr x0, [x28, -227] -+ __ ldrw(r28, Address(r10, -26)); // ldr w28, [x10, -26] -+ __ ldrb(r4, Address(r11, 12)); // ldrb w4, [x11, 12] -+ __ ldrh(r1, Address(r17, 5)); // ldrh w1, [x17, 5] -+ __ ldrsb(r11, Address(r9, 12)); // ldrsb x11, [x9, 12] -+ __ ldrsh(r8, Address(r8, -17)); // ldrsh x8, [x8, -17] -+ __ ldrshw(r20, Address(r13, -35)); // ldrsh w20, [x13, -35] -+ __ ldrsw(r23, Address(r9, 49)); // ldrsw x23, [x9, 49] -+ __ ldrd(v9, Address(r4, 29)); // ldr d9, [x4, 29] -+ __ ldrs(v11, Address(r19, 40)); // ldr s11, [x19, 40] -+ __ strd(v25, Address(r20, -43)); // str d25, [x20, -43] -+ __ strs(v25, Address(r1, -80)); // str s25, [x1, -80] ++ __ str(r14, Address(r30, 11)); // str x14, [x30, 11] ++ __ strw(r6, Address(r29, -97)); // str w6, [x29, -97] ++ __ strb(r2, Address(r11, -7)); // strb w2, [x11, -7] ++ __ strh(r20, Address(r8, -22)); // strh w20, [x8, -22] ++ __ ldr(r20, Address(r29, -29)); // ldr x20, [x29, -29] ++ __ ldrw(r9, Address(r0, -26)); // ldr w9, [x0, -26] ++ __ ldrb(r14, Address(r2, 8)); // ldrb w14, [x2, 8] ++ __ ldrh(r13, Address(r1, -24)); // ldrh w13, [x1, -24] ++ __ ldrsb(r13, Address(r17, -7)); // ldrsb x13, [x17, -7] ++ __ ldrsh(r17, Address(r7, -11)); // ldrsh x17, [x7, -11] ++ __ ldrshw(r3, Address(r8, -60)); // ldrsh w3, [x8, -60] ++ __ ldrsw(r14, Address(r12, 12)); // ldrsw x14, [x12, 12] ++ __ ldrd(v5, Address(r21, -235)); // ldr d5, [x21, -235] ++ __ ldrs(v9, Address(r0, -54)); // ldr s9, [x0, -54] ++ __ strd(v15, Address(r8, 95)); // str d15, [x8, 95] ++ __ strs(v22, Address(r0, -16)); // str s22, [x0, -16] + +// pre // LoadStoreOp -- __ str(r8, Address(__ pre(r28, -24))); // str x8, [x28, -24]! -- __ strw(r6, Address(__ pre(r15, 37))); // str w6, [x15, 37]! -- __ strb(r7, Address(__ pre(r1, 7))); // strb w7, [x1, 7]! -- __ strh(r0, Address(__ pre(r17, 30))); // strh w0, [x17, 30]! -- __ ldr(r25, Address(__ pre(r29, 84))); // ldr x25, [x29, 84]! -- __ ldrw(r26, Address(__ pre(r20, -52))); // ldr w26, [x20, -52]! -- __ ldrb(r26, Address(__ pre(r29, -25))); // ldrb w26, [x29, -25]! -- __ ldrh(r4, Address(__ pre(r25, 26))); // ldrh w4, [x25, 26]! -- __ ldrsb(r28, Address(__ pre(r8, -21))); // ldrsb x28, [x8, -21]! -- __ ldrsh(r17, Address(__ pre(r14, -6))); // ldrsh x17, [x14, -6]! -- __ ldrshw(r28, Address(__ pre(r23, 10))); // ldrsh w28, [x23, 10]! -- __ ldrsw(r30, Address(__ pre(r27, -64))); // ldrsw x30, [x27, -64]! -- __ ldrd(v20, Address(__ pre(r30, -242))); // ldr d20, [x30, -242]! -- __ ldrs(v17, Address(__ pre(r27, 20))); // ldr s17, [x27, 20]! -- __ strd(v7, Address(__ pre(r3, 17))); // str d7, [x3, 17]! -- __ strs(v13, Address(__ pre(r11, -16))); // str s13, [x11, -16]! +- __ str(r2, Address(__ pre(r5, 100))); // str x2, [x5, 100]! +- __ strw(r9, Address(__ pre(r1, -92))); // str w9, [x1, -92]! +- __ strb(r27, Address(__ pre(r30, -5))); // strb w27, [x30, -5]! +- __ strh(r27, Address(__ pre(r15, 12))); // strh w27, [x15, 12]! +- __ ldr(r4, Address(__ pre(r17, -212))); // ldr x4, [x17, -212]! +- __ ldrw(r21, Address(__ pre(r23, 30))); // ldr w21, [x23, 30]! +- __ ldrb(r13, Address(__ pre(r17, -7))); // ldrb w13, [x17, -7]! +- __ ldrh(r25, Address(__ pre(r0, -50))); // ldrh w25, [x0, -50]! +- __ ldrsb(r1, Address(__ pre(r21, -21))); // ldrsb x1, [x21, -21]! +- __ ldrsh(r28, Address(__ pre(r21, -54))); // ldrsh x28, [x21, -54]! +- __ ldrshw(r11, Address(__ pre(r4, 2))); // ldrsh w11, [x4, 2]! +- __ ldrsw(r17, Address(__ pre(r9, 61))); // ldrsw x17, [x9, 61]! +- __ ldrd(v29, Address(__ pre(r19, 39))); // ldr d29, [x19, 39]! +- __ ldrs(v22, Address(__ pre(r22, -85))); // ldr s22, [x22, -85]! +- __ strd(v9, Address(__ pre(r25, -225))); // str d9, [x25, -225]! +- __ strs(v9, Address(__ pre(r2, -15))); // str s9, [x2, -15]! - -// post -+ __ str(r20, Address(__ pre(r0, 25))); // str x20, [x0, 25]! -+ __ strw(r12, Address(__ pre(r12, -49))); // str w12, [x12, -49]! -+ __ strb(r28, Address(__ pre(r19, -10))); // strb w28, [x19, -10]! -+ __ strh(r13, Address(__ pre(r28, -63))); // strh w13, [x28, -63]! -+ __ ldr(r11, Address(__ pre(r23, -46))); // ldr x11, [x23, -46]! -+ __ ldrw(r27, Address(__ pre(r24, 17))); // ldr w27, [x24, 17]! -+ __ ldrb(r14, Address(__ pre(r26, -12))); // ldrb w14, [x26, -12]! -+ __ ldrh(r24, Address(__ pre(r22, -45))); // ldrh w24, [x22, -45]! -+ __ ldrsb(r25, Address(__ pre(r9, -11))); // ldrsb x25, [x9, -11]! -+ __ ldrsh(r5, Address(__ pre(r6, 29))); // ldrsh x5, [x6, 29]! -+ __ ldrshw(r7, Address(__ pre(r23, -1))); // ldrsh w7, [x23, -1]! -+ __ ldrsw(r26, Address(__ pre(r13, -61))); // ldrsw x26, [x13, -61]! -+ __ ldrd(v24, Address(__ pre(r24, -245))); // ldr d24, [x24, -245]! -+ __ ldrs(v20, Address(__ pre(r25, -55))); // ldr s20, [x25, -55]! -+ __ strd(v9, Address(__ pre(r2, -203))); // str d9, [x2, -203]! -+ __ strs(v14, Address(__ pre(r1, -59))); // str s14, [x1, -59]! ++ __ str(r23, Address(__ pre(r4, -239))); // str x23, [x4, -239]! ++ __ strw(r17, Address(__ pre(r0, -122))); // str w17, [x0, -122]! ++ __ strb(r26, Address(__ pre(r9, -5))); // strb w26, [x9, -5]! ++ __ strh(r21, Address(__ pre(r14, -8))); // strh w21, [x14, -8]! ++ __ ldr(r8, Address(__ pre(r7, 23))); // ldr x8, [x7, 23]! ++ __ ldrw(r12, Address(__ pre(r8, 22))); // ldr w12, [x8, 22]! ++ __ ldrb(r27, Address(__ pre(r28, 6))); // ldrb w27, [x28, 6]! ++ __ ldrh(r6, Address(__ pre(r19, -58))); // ldrh w6, [x19, -58]! ++ __ ldrsb(r7, Address(__ pre(r5, -20))); // ldrsb x7, [x5, -20]! ++ __ ldrsh(r22, Address(__ pre(r17, -32))); // ldrsh x22, [x17, -32]! ++ __ ldrshw(r17, Address(__ pre(r13, -2))); // ldrsh w17, [x13, -2]! ++ __ ldrsw(r29, Address(__ pre(r4, 22))); // ldrsw x29, [x4, 22]! ++ __ ldrd(v8, Address(__ pre(r28, -78))); // ldr d8, [x28, -78]! ++ __ ldrs(v23, Address(__ pre(r11, -5))); // ldr s23, [x11, -5]! ++ __ strd(v9, Address(__ pre(r20, -23))); // str d9, [x20, -23]! ++ __ strs(v5, Address(__ pre(r3, -103))); // str s5, [x3, -103]! + +// post // LoadStoreOp -- __ str(r6, Address(__ post(r9, -61))); // str x6, [x9], -61 -- __ strw(r16, Address(__ post(r5, -29))); // str w16, [x5], -29 -- __ strb(r29, Address(__ post(r29, 15))); // strb w29, [x29], 15 -- __ strh(r4, Address(__ post(r20, 18))); // strh w4, [x20], 18 -- __ ldr(r19, Address(__ post(r18, 46))); // ldr x19, [x18], 46 -- __ ldrw(r22, Address(__ post(r2, 23))); // ldr w22, [x2], 23 -- __ ldrb(r7, Address(__ post(r3, -30))); // ldrb w7, [x3], -30 -- __ ldrh(r11, Address(__ post(r12, -29))); // ldrh w11, [x12], -29 -- __ ldrsb(r8, Address(__ post(r6, -29))); // ldrsb x8, [x6], -29 -- __ ldrsh(r24, Address(__ post(r23, 4))); // ldrsh x24, [x23], 4 -- __ ldrshw(r17, Address(__ post(r16, 0))); // ldrsh w17, [x16], 0 -- __ ldrsw(r0, Address(__ post(r20, -8))); // ldrsw x0, [x20], -8 -- __ ldrd(v20, Address(__ post(r2, -126))); // ldr d20, [x2], -126 -- __ ldrs(v19, Address(__ post(r30, -104))); // ldr s19, [x30], -104 -- __ strd(v4, Address(__ post(r17, 118))); // str d4, [x17], 118 -- __ strs(v21, Address(__ post(r19, -112))); // str s21, [x19], -112 +- __ str(r13, Address(__ post(r23, -66))); // str x13, [x23], -66 +- __ strw(r17, Address(__ post(r16, 10))); // str w17, [x16], 10 +- __ strb(r1, Address(__ post(r14, -32))); // strb w1, [x14], -32 +- __ strh(r17, Address(__ post(r0, 6))); // strh w17, [x0], 6 +- __ ldr(r27, Address(__ post(r25, -172))); // ldr x27, [x25], -172 +- __ ldrw(r13, Address(__ post(r25, -38))); // ldr w13, [x25], -38 +- __ ldrb(r11, Address(__ post(r25, -29))); // ldrb w11, [x25], -29 +- __ ldrh(r30, Address(__ post(r5, 20))); // ldrh w30, [x5], 20 +- __ ldrsb(r9, Address(__ post(r7, -7))); // ldrsb x9, [x7], -7 +- __ ldrsh(r0, Address(__ post(r3, -62))); // ldrsh x0, [x3], -62 +- __ ldrshw(r7, Address(__ post(r14, 31))); // ldrsh w7, [x14], 31 +- __ ldrsw(r17, Address(__ post(r27, 39))); // ldrsw x17, [x27], 39 +- __ ldrd(v17, Address(__ post(r4, -235))); // ldr d17, [x4], -235 +- __ ldrs(v26, Address(__ post(r21, 34))); // ldr s26, [x21], 34 +- __ strd(v5, Address(__ post(r17, -57))); // str d5, [x17], -57 +- __ strs(v13, Address(__ post(r13, -109))); // str s13, [x13], -109 - -// base_plus_reg -+ __ str(r19, Address(__ post(r1, 109))); // str x19, [x1], 109 -+ __ strw(r4, Address(__ post(r5, -54))); // str w4, [x5], -54 -+ __ strb(r29, Address(__ post(r3, 9))); // strb w29, [x3], 9 -+ __ strh(r0, Address(__ post(r1, -50))); // strh w0, [x1], -50 -+ __ ldr(r2, Address(__ post(r6, -48))); // ldr x2, [x6], -48 -+ __ ldrw(r15, Address(__ post(r6, -115))); // ldr w15, [x6], -115 -+ __ ldrb(r4, Address(__ post(r2, -27))); // ldrb w4, [x2], -27 -+ __ ldrh(r17, Address(__ post(r26, -21))); // ldrh w17, [x26], -21 -+ __ ldrsb(r21, Address(__ post(r24, -13))); // ldrsb x21, [x24], -13 -+ __ ldrsh(r22, Address(__ post(r6, -48))); // ldrsh x22, [x6], -48 -+ __ ldrshw(r11, Address(__ post(r6, -48))); // ldrsh w11, [x6], -48 -+ __ ldrsw(r14, Address(__ post(r30, -5))); // ldrsw x14, [x30], -5 -+ __ ldrd(v2, Address(__ post(r15, -105))); // ldr d2, [x15], -105 -+ __ ldrs(v25, Address(__ post(r19, -91))); // ldr s25, [x19], -91 -+ __ strd(v13, Address(__ post(r23, -191))); // str d13, [x23], -191 -+ __ strs(v22, Address(__ post(r21, 0))); // str s22, [x21], 0 ++ __ str(r13, Address(__ post(r2, 32))); // str x13, [x2], 32 ++ __ strw(r30, Address(__ post(r19, 57))); // str w30, [x19], 57 ++ __ strb(r29, Address(__ post(r1, 3))); // strb w29, [x1], 3 ++ __ strh(r10, Address(__ post(r26, -17))); // strh w10, [x26], -17 ++ __ ldr(r15, Address(__ post(r1, -12))); // ldr x15, [x1], -12 ++ __ ldrw(r1, Address(__ post(r5, -6))); // ldr w1, [x5], -6 ++ __ ldrb(r24, Address(__ post(r15, -14))); // ldrb w24, [x15], -14 ++ __ ldrh(r29, Address(__ post(r17, -5))); // ldrh w29, [x17], -5 ++ __ ldrsb(r4, Address(__ post(r15, -17))); // ldrsb x4, [x15], -17 ++ __ ldrsh(r6, Address(__ post(r2, -54))); // ldrsh x6, [x2], -54 ++ __ ldrshw(r27, Address(__ post(r27, 18))); // ldrsh w27, [x27], 18 ++ __ ldrsw(r9, Address(__ post(r25, -77))); // ldrsw x9, [x25], -77 ++ __ ldrd(v21, Address(__ post(r29, -176))); // ldr d21, [x29], -176 ++ __ ldrs(v30, Address(__ post(r9, -50))); // ldr s30, [x9], -50 ++ __ strd(v2, Address(__ post(r12, -46))); // str d2, [x12], -46 ++ __ strs(v7, Address(__ post(r21, -59))); // str s7, [x21], -59 + +// base_plus_reg // LoadStoreOp -- __ str(r26, Address(r2, r19, Address::lsl(3))); // str x26, [x2, x19, lsl #3] -- __ strw(r9, Address(r0, r15, Address::sxtw(2))); // str w9, [x0, w15, sxtw #2] -- __ strb(r26, Address(r12, r1, Address::lsl(0))); // strb w26, [x12, x1, lsl #0] -- __ strh(r21, Address(r11, r10, Address::lsl(1))); // strh w21, [x11, x10, lsl #1] -- __ ldr(r16, Address(r23, r16, Address::sxtx(0))); // ldr x16, [x23, x16, sxtx #0] -- __ ldrw(r10, Address(r11, r17, Address::sxtw(2))); // ldr w10, [x11, w17, sxtw #2] -- __ ldrb(r13, Address(r23, r11, Address::lsl(0))); // ldrb w13, [x23, x11, lsl #0] -- __ ldrh(r27, Address(r4, r21, Address::lsl(0))); // ldrh w27, [x4, x21, lsl #0] -- __ ldrsb(r26, Address(r8, r15, Address::sxtw(0))); // ldrsb x26, [x8, w15, sxtw #0] -- __ ldrsh(r21, Address(r10, r2, Address::sxtw(0))); // ldrsh x21, [x10, w2, sxtw #0] -- __ ldrshw(r8, Address(r30, r14, Address::lsl(0))); // ldrsh w8, [x30, x14, lsl #0] -- __ ldrsw(r29, Address(r14, r20, Address::sxtx(2))); // ldrsw x29, [x14, x20, sxtx #2] -- __ ldrd(v30, Address(r27, r22, Address::sxtx(0))); // ldr d30, [x27, x22, sxtx #0] -- __ ldrs(v13, Address(r9, r22, Address::lsl(0))); // ldr s13, [x9, x22, lsl #0] -- __ strd(v8, Address(r25, r17, Address::sxtw(3))); // str d8, [x25, w17, sxtw #3] -- __ strs(v1, Address(r24, r5, Address::uxtw(2))); // str s1, [x24, w5, uxtw #2] +- __ str(r6, Address(r16, r4, Address::sxtw(3))); // str x6, [x16, w4, sxtw #3] +- __ strw(r9, Address(r24, r20, Address::sxtw(2))); // str w9, [x24, w20, sxtw #2] +- __ strb(r3, Address(r29, r3, Address::lsl(0))); // strb w3, [x29, x3, lsl #0] +- __ strh(r10, Address(r17, r30, Address::lsl(0))); // strh w10, [x17, x30, lsl #0] +- __ ldr(r27, Address(r11, r7, Address::uxtw(0))); // ldr x27, [x11, w7, uxtw #0] +- __ ldrw(r14, Address(r15, r25, Address::uxtw(0))); // ldr w14, [x15, w25, uxtw #0] +- __ ldrb(r24, Address(r14, r19, Address::lsl(0))); // ldrb w24, [x14, x19, lsl #0] +- __ ldrh(r16, Address(r0, r6, Address::sxtw(0))); // ldrh w16, [x0, w6, sxtw #0] +- __ ldrsb(r10, Address(r12, r12, Address::sxtw(0))); // ldrsb x10, [x12, w12, sxtw #0] +- __ ldrsh(r26, Address(r12, r16, Address::uxtw(0))); // ldrsh x26, [x12, w16, uxtw #0] +- __ ldrshw(r26, Address(r0, r14, Address::lsl(1))); // ldrsh w26, [x0, x14, lsl #1] +- __ ldrsw(r17, Address(r11, r27, Address::sxtx(2))); // ldrsw x17, [x11, x27, sxtx #2] +- __ ldrd(v3, Address(r0, r19, Address::sxtw(3))); // ldr d3, [x0, w19, sxtw #3] +- __ ldrs(v26, Address(r15, r9, Address::lsl(2))); // ldr s26, [x15, x9, lsl #2] +- __ strd(v11, Address(r13, r16, Address::sxtx(0))); // str d11, [x13, x16, sxtx #0] +- __ strs(v26, Address(r19, r21, Address::uxtw(2))); // str s26, [x19, w21, uxtw #2] - -// base_plus_scaled_offset -+ __ str(r22, Address(r12, r18, Address::sxtw(0))); // str x22, [x12, w18, sxtw #0] -+ __ strw(r30, Address(r27, r12, Address::uxtw(0))); // str w30, [x27, w12, uxtw #0] -+ __ strb(r7, Address(r4, r22, Address::lsl(0))); // strb w7, [x4, x22, lsl #0] -+ __ strh(r19, Address(r23, r29, Address::sxtx(1))); // strh w19, [x23, x29, sxtx #1] -+ __ ldr(r17, Address(r4, r27, Address::sxtx(3))); // ldr x17, [x4, x27, sxtx #3] -+ __ ldrw(r1, Address(r13, r17, Address::sxtw(0))); // ldr w1, [x13, w17, sxtw #0] -+ __ ldrb(r16, Address(r27, r29, Address::sxtx(0))); // ldrb w16, [x27, x29, sxtx #0] -+ __ ldrh(r25, Address(r9, r4, Address::uxtw(1))); // ldrh w25, [x9, w4, uxtw #1] -+ __ ldrsb(r4, Address(r12, r22, Address::lsl(0))); // ldrsb x4, [x12, x22, lsl #0] -+ __ ldrsh(r25, Address(r1, r5, Address::uxtw(1))); // ldrsh x25, [x1, w5, uxtw #1] -+ __ ldrshw(r9, Address(r16, r28, Address::lsl(0))); // ldrsh w9, [x16, x28, lsl #0] -+ __ ldrsw(r8, Address(r7, r14, Address::sxtx(0))); // ldrsw x8, [x7, x14, sxtx #0] -+ __ ldrd(v4, Address(r28, r16, Address::uxtw(3))); // ldr d4, [x28, w16, uxtw #3] -+ __ ldrs(v16, Address(r2, r27, Address::sxtw(2))); // ldr s16, [x2, w27, sxtw #2] -+ __ strd(v23, Address(r0, r25, Address::lsl(0))); // str d23, [x0, x25, lsl #0] -+ __ strs(v6, Address(r16, r7, Address::lsl(2))); // str s6, [x16, x7, lsl #2] ++ __ str(r12, Address(r12, r23, Address::uxtw(3))); // str x12, [x12, w23, uxtw #3] ++ __ strw(r14, Address(r30, r22, Address::uxtw(0))); // str w14, [x30, w22, uxtw #0] ++ __ strb(r12, Address(r3, r26, Address::uxtw(0))); // strb w12, [x3, w26, uxtw #0] ++ __ strh(r11, Address(r14, r30, Address::uxtw(0))); // strh w11, [x14, w30, uxtw #0] ++ __ ldr(r24, Address(r8, r24, Address::lsl(3))); // ldr x24, [x8, x24, lsl #3] ++ __ ldrw(r12, Address(r13, r20, Address::lsl(0))); // ldr w12, [x13, x20, lsl #0] ++ __ ldrb(r22, Address(r4, r5, Address::uxtw(0))); // ldrb w22, [x4, w5, uxtw #0] ++ __ ldrh(r28, Address(r5, r6, Address::uxtw(1))); // ldrh w28, [x5, w6, uxtw #1] ++ __ ldrsb(r2, Address(r11, r25, Address::lsl(0))); // ldrsb x2, [x11, x25, lsl #0] ++ __ ldrsh(r23, Address(r22, r25, Address::sxtx(0))); // ldrsh x23, [x22, x25, sxtx #0] ++ __ ldrshw(r3, Address(r20, r22, Address::sxtw(1))); // ldrsh w3, [x20, w22, sxtw #1] ++ __ ldrsw(r9, Address(r29, r14, Address::sxtx(2))); // ldrsw x9, [x29, x14, sxtx #2] ++ __ ldrd(v16, Address(r23, r29, Address::sxtx(3))); // ldr d16, [x23, x29, sxtx #3] ++ __ ldrs(v7, Address(r28, r20, Address::lsl(2))); // ldr s7, [x28, x20, lsl #2] ++ __ strd(v20, Address(r20, r24, Address::lsl(3))); // str d20, [x20, x24, lsl #3] ++ __ strs(v25, Address(r21, r23, Address::lsl(2))); // str s25, [x21, x23, lsl #2] + +// base_plus_scaled_offset // LoadStoreOp -- __ str(r10, Address(r21, 14496)); // str x10, [x21, 14496] -- __ strw(r18, Address(r29, 7228)); // str w18, [x29, 7228] -- __ strb(r23, Address(r3, 2018)); // strb w23, [x3, 2018] -- __ strh(r28, Address(r11, 3428)); // strh w28, [x11, 3428] -- __ ldr(r24, Address(r26, 14376)); // ldr x24, [x26, 14376] -- __ ldrw(r21, Address(r2, 6972)); // ldr w21, [x2, 6972] -- __ ldrb(r4, Address(r5, 1848)); // ldrb w4, [x5, 1848] -- __ ldrh(r14, Address(r14, 3112)); // ldrh w14, [x14, 3112] -- __ ldrsb(r4, Address(r27, 1959)); // ldrsb x4, [x27, 1959] -- __ ldrsh(r4, Address(r27, 3226)); // ldrsh x4, [x27, 3226] -- __ ldrshw(r10, Address(r28, 3286)); // ldrsh w10, [x28, 3286] -- __ ldrsw(r10, Address(r17, 7912)); // ldrsw x10, [x17, 7912] -- __ ldrd(v13, Address(r28, 13400)); // ldr d13, [x28, 13400] -- __ ldrs(v24, Address(r3, 7596)); // ldr s24, [x3, 7596] -- __ strd(v2, Address(r12, 15360)); // str d2, [x12, 15360] -- __ strs(v17, Address(r1, 6492)); // str s17, [x1, 6492] +- __ str(r8, Address(r21, 12552)); // str x8, [x21, 12552] +- __ strw(r10, Address(r27, 6380)); // str w10, [x27, 6380] +- __ strb(r27, Address(r14, 1733)); // strb w27, [x14, 1733] +- __ strh(r16, Address(r7, 3424)); // strh w16, [x7, 3424] +- __ ldr(r27, Address(r9, 12520)); // ldr x27, [x9, 12520] +- __ ldrw(r24, Address(r10, 6680)); // ldr w24, [x10, 6680] +- __ ldrb(r24, Address(r24, 1743)); // ldrb w24, [x24, 1743] +- __ ldrh(r20, Address(r5, 3072)); // ldrh w20, [x5, 3072] +- __ ldrsb(r17, Address(r4, 1570)); // ldrsb x17, [x4, 1570] +- __ ldrsh(r14, Address(r13, 3392)); // ldrsh x14, [x13, 3392] +- __ ldrshw(r10, Address(r25, 3722)); // ldrsh w10, [x25, 3722] +- __ ldrsw(r2, Address(r26, 6160)); // ldrsw x2, [x26, 6160] +- __ ldrd(v26, Address(r14, 14912)); // ldr d26, [x14, 14912] +- __ ldrs(v28, Address(r4, 7804)); // ldr s28, [x4, 7804] +- __ strd(v14, Address(r19, 13984)); // str d14, [x19, 13984] +- __ strs(v23, Address(r28, 6364)); // str s23, [x28, 6364] - -// pcrel -+ __ str(r2, Address(r12, 15288)); // str x2, [x12, 15288] -+ __ strw(r8, Address(r5, 6928)); // str w8, [x5, 6928] -+ __ strb(r1, Address(r17, 2016)); // strb w1, [x17, 2016] -+ __ strh(r8, Address(r25, 3258)); // strh w8, [x25, 3258] -+ __ ldr(r28, Address(r3, 14656)); // ldr x28, [x3, 14656] -+ __ ldrw(r21, Address(r11, 7004)); // ldr w21, [x11, 7004] -+ __ ldrb(r15, Address(r5, 1906)); // ldrb w15, [x5, 1906] -+ __ ldrh(r0, Address(r19, 3668)); // ldrh w0, [x19, 3668] -+ __ ldrsb(r29, Address(r9, 1909)); // ldrsb x29, [x9, 1909] -+ __ ldrsh(r23, Address(r28, 3640)); // ldrsh x23, [x28, 3640] -+ __ ldrshw(r27, Address(r10, 3672)); // ldrsh w27, [x10, 3672] -+ __ ldrsw(r21, Address(r27, 7736)); // ldrsw x21, [x27, 7736] -+ __ ldrd(v26, Address(r27, 14584)); // ldr d26, [x27, 14584] -+ __ ldrs(v2, Address(r4, 7464)); // ldr s2, [x4, 7464] -+ __ strd(v1, Address(r21, 16224)); // str d1, [x21, 16224] -+ __ strs(v4, Address(r22, 7552)); // str s4, [x22, 7552] ++ __ str(r17, Address(r2, 12312)); // str x17, [x2, 12312] ++ __ strw(r30, Address(r7, 6968)); // str w30, [x7, 6968] ++ __ strb(r3, Address(r7, 1833)); // strb w3, [x7, 1833] ++ __ strh(r7, Address(r1, 3366)); // strh w7, [x1, 3366] ++ __ ldr(r7, Address(r27, 14664)); // ldr x7, [x27, 14664] ++ __ ldrw(r8, Address(r17, 6156)); // ldr w8, [x17, 6156] ++ __ ldrb(r0, Address(r17, 1594)); // ldrb w0, [x17, 1594] ++ __ ldrh(r0, Address(r20, 3562)); // ldrh w0, [x20, 3562] ++ __ ldrsb(r19, Address(r17, 1681)); // ldrsb x19, [x17, 1681] ++ __ ldrsh(r19, Address(r6, 3776)); // ldrsh x19, [x6, 3776] ++ __ ldrshw(r4, Address(r10, 3708)); // ldrsh w4, [x10, 3708] ++ __ ldrsw(r29, Address(r4, 6948)); // ldrsw x29, [x4, 6948] ++ __ ldrd(v29, Address(r1, 13352)); // ldr d29, [x1, 13352] ++ __ ldrs(v15, Address(r28, 6544)); // ldr s15, [x28, 6544] ++ __ strd(v7, Address(r26, 14112)); // str d7, [x26, 14112] ++ __ strs(v0, Address(r30, 6820)); // str s0, [x30, 6820] + +// pcrel // LoadStoreOp -- __ ldr(r16, __ pc()); // ldr x16, . -- __ ldrw(r13, __ pc()); // ldr w13, . -+ __ ldr(r1, __ pc()); // ldr x1, . -+ __ ldrw(r27, __ pc()); // ldr w27, . +- __ ldr(r8, forth); // ldr x8, forth +- __ ldrw(r17, back); // ldr w17, back ++ __ ldr(r25, __ pc()); // ldr x25, . ++ __ ldrw(r9, __ pc()); // ldr w9, . // LoadStoreOp -- __ prfm(Address(r18, -127)); // prfm PLDL1KEEP, [x18, -127] -+ __ prfm(Address(r4, 45)); // prfm PLDL1KEEP, [x4, 45] +- __ prfm(Address(r4, -175)); // prfm PLDL1KEEP, [x4, -175] ++ __ prfm(Address(r22, 105)); // prfm PLDL1KEEP, [x22, 105] // LoadStoreOp -- __ prfm(back); // prfm PLDL1KEEP, back -+ __ prfm(__ pc()); // prfm PLDL1KEEP, . +- __ prfm(__ pc()); // prfm PLDL1KEEP, . ++ __ prfm(back); // prfm PLDL1KEEP, back // LoadStoreOp -- __ prfm(Address(r20, r2, Address::lsl(3))); // prfm PLDL1KEEP, [x20, x2, lsl #3] -+ __ prfm(Address(r30, r0, Address::sxtw(0))); // prfm PLDL1KEEP, [x30, w0, sxtw #0] +- __ prfm(Address(r8, r4, Address::sxtw(0))); // prfm PLDL1KEEP, [x8, w4, sxtw #0] ++ __ prfm(Address(r28, r30, Address::lsl(3))); // prfm PLDL1KEEP, [x28, x30, lsl #3] // LoadStoreOp -- __ prfm(Address(r9, 13808)); // prfm PLDL1KEEP, [x9, 13808] -+ __ prfm(Address(r24, 16208)); // prfm PLDL1KEEP, [x24, 16208] +- __ prfm(Address(r12, 13248)); // prfm PLDL1KEEP, [x12, 13248] ++ __ prfm(Address(r19, 14592)); // prfm PLDL1KEEP, [x19, 14592] // AddSubCarryOp -- __ adcw(r8, r23, r2); // adc w8, w23, w2 -- __ adcsw(r24, r3, r19); // adcs w24, w3, w19 -- __ sbcw(r22, r24, r29); // sbc w22, w24, w29 -- __ sbcsw(r12, r27, r3); // sbcs w12, w27, w3 -- __ adc(r11, r23, r1); // adc x11, x23, x1 -- __ adcs(r29, r5, r23); // adcs x29, x5, x23 -- __ sbc(r9, r25, r12); // sbc x9, x25, x12 -- __ sbcs(r12, r0, r22); // sbcs x12, x0, x22 -+ __ adcw(r0, r29, r24); // adc w0, w29, w24 -+ __ adcsw(r22, r28, r18); // adcs w22, w28, w18 -+ __ sbcw(r23, r16, r30); // sbc w23, w16, w30 -+ __ sbcsw(r7, r29, r14); // sbcs w7, w29, w14 -+ __ adc(r22, r12, r14); // adc x22, x12, x14 -+ __ adcs(r29, r24, r23); // adcs x29, x24, x23 -+ __ sbc(r17, r28, r22); // sbc x17, x28, x22 -+ __ sbcs(r24, r20, r19); // sbcs x24, x20, x19 +- __ adcw(r20, r27, r21); // adc w20, w27, w21 +- __ adcsw(r7, r17, r6); // adcs w7, w17, w6 +- __ sbcw(r5, r6, r25); // sbc w5, w6, w25 +- __ sbcsw(r30, r11, r14); // sbcs w30, w11, w14 +- __ adc(r3, r17, r11); // adc x3, x17, x11 +- __ adcs(r25, r10, r17); // adcs x25, x10, x17 +- __ sbc(r7, r16, r23); // sbc x7, x16, x23 +- __ sbcs(r4, r10, r5); // sbcs x4, x10, x5 ++ __ adcw(r17, r8, r24); // adc w17, w8, w24 ++ __ adcsw(r14, r17, r9); // adcs w14, w17, w9 ++ __ sbcw(r22, r1, r25); // sbc w22, w1, w25 ++ __ sbcsw(r15, r9, r19); // sbcs w15, w9, w19 ++ __ adc(r15, r20, r11); // adc x15, x20, x11 ++ __ adcs(r4, r11, r30); // adcs x4, x11, x30 ++ __ sbc(r20, r8, r6); // sbc x20, x8, x6 ++ __ sbcs(r10, r21, r15); // sbcs x10, x21, x15 // AddSubExtendedOp -- __ addw(r26, r12, r3, ext::uxtw, 1); // add w26, w12, w3, uxtw #1 -- __ addsw(r20, r16, r18, ext::sxtb, 2); // adds w20, w16, w18, sxtb #2 -- __ sub(r30, r30, r7, ext::uxtw, 2); // sub x30, x30, x7, uxtw #2 -- __ subsw(r11, r21, r2, ext::uxth, 3); // subs w11, w21, w2, uxth #3 -- __ add(r2, r26, r1, ext::uxtw, 2); // add x2, x26, x1, uxtw #2 -- __ adds(r18, r29, r20, ext::sxth, 1); // adds x18, x29, x20, sxth #1 -- __ sub(r14, r16, r4, ext::uxtw, 4); // sub x14, x16, x4, uxtw #4 -- __ subs(r0, r17, r23, ext::sxtb, 3); // subs x0, x17, x23, sxtb #3 -+ __ addw(r27, r22, r6, ext::sxtw, 2); // add w27, w22, w6, sxtw #2 -+ __ addsw(r13, r11, r24, ext::uxtw, 4); // adds w13, w11, w24, uxtw #4 -+ __ sub(r16, r8, r4, ext::uxth, 3); // sub x16, x8, x4, uxth #3 -+ __ subsw(r21, r18, r20, ext::sxtx, 2); // subs w21, w18, w20, sxtx #2 -+ __ add(r14, r17, r29, ext::uxtb, 2); // add x14, x17, x29, uxtb #2 -+ __ adds(r17, r17, r14, ext::sxth, 4); // adds x17, x17, x14, sxth #4 -+ __ sub(r22, r3, r26, ext::sxtw, 1); // sub x22, x3, x26, sxtw #1 -+ __ subs(r13, r13, r21, ext::uxth, 4); // subs x13, x13, x21, uxth #4 +- __ addw(r9, r30, r9, ext::uxtx, 4); // add w9, w30, w9, uxtx #4 +- __ addsw(r0, r5, r16, ext::sxth, 2); // adds w0, w5, w16, sxth #2 +- __ sub(r15, r29, r27, ext::sxtb, 2); // sub x15, x29, x27, sxtb #2 +- __ subsw(r11, r9, r1, ext::sxtx, 4); // subs w11, w9, w1, sxtx #4 +- __ add(r2, r24, r6, ext::uxtw, 3); // add x2, x24, x6, uxtw #3 +- __ adds(r19, r6, r26, ext::uxtx, 4); // adds x19, x6, x26, uxtx #4 +- __ sub(r8, r26, r25, ext::sxtx, 3); // sub x8, x26, x25, sxtx #3 +- __ subs(r26, r20, r9, ext::uxth, 4); // subs x26, x20, x9, uxth #4 ++ __ addw(r1, r11, r9, ext::sxtb, 3); // add w1, w11, w9, sxtb #3 ++ __ addsw(r4, r17, r28, ext::sxtx, 3); // adds w4, w17, w28, sxtx #3 ++ __ sub(r21, r29, r28, ext::sxth, 1); // sub x21, x29, x28, sxth #1 ++ __ subsw(r11, r28, r23, ext::sxtw, 4); // subs w11, w28, w23, sxtw #4 ++ __ add(r12, r26, r5, ext::sxtx, 4); // add x12, x26, x5, sxtx #4 ++ __ adds(r17, r6, r30, ext::uxtx, 2); // adds x17, x6, x30, uxtx #2 ++ __ sub(r7, r20, r1, ext::uxtb, 2); // sub x7, x20, x1, uxtb #2 ++ __ subs(r30, r9, r30, ext::sxtx, 3); // subs x30, x9, x30, sxtx #3 // ConditionalCompareOp -- __ ccmnw(r20, r22, 3u, Assembler::PL); // ccmn w20, w22, #3, PL -- __ ccmpw(r25, r2, 1u, Assembler::EQ); // ccmp w25, w2, #1, EQ -- __ ccmn(r18, r24, 7u, Assembler::GT); // ccmn x18, x24, #7, GT -- __ ccmp(r8, r13, 6u, Assembler::PL); // ccmp x8, x13, #6, PL -+ __ ccmnw(r17, r26, 15u, Assembler::VC); // ccmn w17, w26, #15, VC -+ __ ccmpw(r25, r6, 5u, Assembler::LO); // ccmp w25, w6, #5, LO -+ __ ccmn(r1, r30, 1u, Assembler::LS); // ccmn x1, x30, #1, LS -+ __ ccmp(r17, r7, 2u, Assembler::GE); // ccmp x17, x7, #2, GE +- __ ccmnw(r13, r26, 7u, Assembler::MI); // ccmn w13, w26, #7, MI +- __ ccmpw(r8, r20, 15u, Assembler::LO); // ccmp w8, w20, #15, LO +- __ ccmn(r22, r3, 8u, Assembler::EQ); // ccmn x22, x3, #8, EQ +- __ ccmp(r2, r24, 10u, Assembler::GE); // ccmp x2, x24, #10, GE ++ __ ccmnw(r4, r11, 7u, Assembler::EQ); // ccmn w4, w11, #7, EQ ++ __ ccmpw(r15, r5, 11u, Assembler::VC); // ccmp w15, w5, #11, VC ++ __ ccmn(r23, r17, 6u, Assembler::CS); // ccmn x23, x17, #6, CS ++ __ ccmp(r11, r11, 10u, Assembler::GT); // ccmp x11, x11, #10, GT // ConditionalCompareImmedOp -- __ ccmnw(r9, 2, 4, Assembler::VS); // ccmn w9, #2, #4, VS -- __ ccmpw(r2, 27, 7, Assembler::EQ); // ccmp w2, #27, #7, EQ -- __ ccmn(r16, 1, 2, Assembler::CC); // ccmn x16, #1, #2, CC -- __ ccmp(r17, 31, 3, Assembler::LT); // ccmp x17, #31, #3, LT -+ __ ccmnw(r17, 25, 6, Assembler::EQ); // ccmn w17, #25, #6, EQ -+ __ ccmpw(r2, 5, 5, Assembler::EQ); // ccmp w2, #5, #5, EQ -+ __ ccmn(r19, 17, 10, Assembler::MI); // ccmn x19, #17, #10, MI -+ __ ccmp(r14, 8, 3, Assembler::GT); // ccmp x14, #8, #3, GT +- __ ccmnw(r8, 16, 13, Assembler::MI); // ccmn w8, #16, #13, MI +- __ ccmpw(r16, 12, 1, Assembler::EQ); // ccmp w16, #12, #1, EQ +- __ ccmn(r15, 31, 3, Assembler::VC); // ccmn x15, #31, #3, VC +- __ ccmp(r23, 12, 15, Assembler::EQ); // ccmp x23, #12, #15, EQ ++ __ ccmnw(r14, 5, 12, Assembler::NE); // ccmn w14, #5, #12, NE ++ __ ccmpw(r23, 28, 15, Assembler::NE); // ccmp w23, #28, #15, NE ++ __ ccmn(r17, 30, 7, Assembler::LO); // ccmn x17, #30, #7, LO ++ __ ccmp(r30, 12, 0, Assembler::HI); // ccmp x30, #12, #0, HI // ConditionalSelectOp -- __ cselw(r23, r27, r23, Assembler::LS); // csel w23, w27, w23, LS -- __ csincw(r10, r0, r6, Assembler::VS); // csinc w10, w0, w6, VS -- __ csinvw(r11, r0, r9, Assembler::CC); // csinv w11, w0, w9, CC -- __ csnegw(r17, r27, r18, Assembler::LO); // csneg w17, w27, w18, LO -- __ csel(r12, r16, r11, Assembler::VC); // csel x12, x16, x11, VC -- __ csinc(r6, r28, r6, Assembler::HI); // csinc x6, x28, x6, HI -- __ csinv(r13, r27, r26, Assembler::VC); // csinv x13, x27, x26, VC -- __ csneg(r29, r22, r18, Assembler::PL); // csneg x29, x22, x18, PL -+ __ cselw(r9, r8, r14, Assembler::LS); // csel w9, w8, w14, LS -+ __ csincw(r27, r11, r5, Assembler::LE); // csinc w27, w11, w5, LE -+ __ csinvw(r11, r23, r22, Assembler::LO); // csinv w11, w23, w22, LO -+ __ csnegw(r19, r28, r27, Assembler::CS); // csneg w19, w28, w27, CS -+ __ csel(r16, r9, r1, Assembler::PL); // csel x16, x9, x1, PL -+ __ csinc(r28, r14, r12, Assembler::EQ); // csinc x28, x14, x12, EQ -+ __ csinv(r22, r4, r14, Assembler::PL); // csinv x22, x4, x14, PL -+ __ csneg(r26, r11, r27, Assembler::HS); // csneg x26, x11, x27, HS +- __ cselw(r14, r7, r26, Assembler::LO); // csel w14, w7, w26, LO +- __ csincw(r3, r27, r30, Assembler::LE); // csinc w3, w27, w30, LE +- __ csinvw(r11, r21, r23, Assembler::EQ); // csinv w11, w21, w23, EQ +- __ csnegw(r26, r30, r21, Assembler::GT); // csneg w26, w30, w21, GT +- __ csel(r28, r26, r13, Assembler::HI); // csel x28, x26, x13, HI +- __ csinc(r17, r3, r16, Assembler::LS); // csinc x17, x3, x16, LS +- __ csinv(r11, r5, r3, Assembler::HI); // csinv x11, x5, x3, HI +- __ csneg(r1, r3, r19, Assembler::GT); // csneg x1, x3, x19, GT ++ __ cselw(r26, r27, r1, Assembler::PL); // csel w26, w27, w1, PL ++ __ csincw(r14, r11, r21, Assembler::LE); // csinc w14, w11, w21, LE ++ __ csinvw(r30, r6, r15, Assembler::VS); // csinv w30, w6, w15, VS ++ __ csnegw(r17, r2, r25, Assembler::PL); // csneg w17, w2, w25, PL ++ __ csel(r16, r5, r7, Assembler::HI); // csel x16, x5, x7, HI ++ __ csinc(r10, r20, r28, Assembler::GT); // csinc x10, x20, x28, GT ++ __ csinv(r6, r7, r1, Assembler::HI); // csinv x6, x7, x1, HI ++ __ csneg(r22, r26, r17, Assembler::CS); // csneg x22, x26, x17, CS // TwoRegOp -- __ rbitw(r12, r19); // rbit w12, w19 -- __ rev16w(r23, r18); // rev16 w23, w18 -- __ revw(r9, r28); // rev w9, w28 -- __ clzw(r2, r19); // clz w2, w19 -- __ clsw(r25, r29); // cls w25, w29 -- __ rbit(r4, r23); // rbit x4, x23 -- __ rev16(r29, r18); // rev16 x29, x18 -- __ rev32(r7, r8); // rev32 x7, x8 -- __ rev(r13, r17); // rev x13, x17 -- __ clz(r17, r0); // clz x17, x0 -- __ cls(r18, r26); // cls x18, x26 -+ __ rbitw(r24, r11); // rbit w24, w11 -+ __ rev16w(r10, r14); // rev16 w10, w14 -+ __ revw(r9, r5); // rev w9, w5 -+ __ clzw(r18, r20); // clz w18, w20 -+ __ clsw(r25, r8); // cls w25, w8 -+ __ rbit(r22, r24); // rbit x22, x24 -+ __ rev16(r28, r27); // rev16 x28, x27 -+ __ rev32(r8, r29); // rev32 x8, x29 -+ __ rev(r17, r10); // rev x17, x10 -+ __ clz(r23, r11); // clz x23, x11 -+ __ cls(r26, r14); // cls x26, x14 +- __ rbitw(r0, r9); // rbit w0, w9 +- __ rev16w(r26, r14); // rev16 w26, w14 +- __ revw(r13, r17); // rev w13, w17 +- __ clzw(r11, r20); // clz w11, w20 +- __ clsw(r28, r17); // cls w28, w17 +- __ rbit(r13, r4); // rbit x13, x4 +- __ rev16(r1, r30); // rev16 x1, x30 +- __ rev32(r13, r14); // rev32 x13, x14 +- __ rev(r5, r8); // rev x5, x8 +- __ clz(r2, r25); // clz x2, x25 +- __ cls(r20, r8); // cls x20, x8 ++ __ rbitw(r11, r6); // rbit w11, w6 ++ __ rev16w(r0, r27); // rev16 w0, w27 ++ __ revw(r1, r29); // rev w1, w29 ++ __ clzw(r20, r21); // clz w20, w21 ++ __ clsw(r12, r12); // cls w12, w12 ++ __ rbit(r24, r19); // rbit x24, x19 ++ __ rev16(r23, r15); // rev16 x23, x15 ++ __ rev32(r17, r1); // rev32 x17, x1 ++ __ rev(r27, r3); // rev x27, x3 ++ __ clz(r30, r5); // clz x30, x5 ++ __ cls(r15, r0); // cls x15, x0 // ThreeRegOp -- __ udivw(r11, r12, r16); // udiv w11, w12, w16 -- __ sdivw(r4, r9, r7); // sdiv w4, w9, w7 -- __ lslvw(r12, r7, r16); // lslv w12, w7, w16 -- __ lsrvw(r19, r16, r23); // lsrv w19, w16, w23 -- __ asrvw(r7, r4, r6); // asrv w7, w4, w6 -- __ rorvw(r21, r20, r23); // rorv w21, w20, w23 -- __ udiv(r16, r12, r28); // udiv x16, x12, x28 -- __ sdiv(r4, r12, r13); // sdiv x4, x12, x13 -- __ lslv(r9, r13, r7); // lslv x9, x13, x7 -- __ lsrv(r28, r27, r15); // lsrv x28, x27, x15 -- __ asrv(r20, r30, r14); // asrv x20, x30, x14 -- __ rorv(r14, r18, r30); // rorv x14, x18, x30 -- __ umulh(r3, r11, r7); // umulh x3, x11, x7 -- __ smulh(r23, r20, r24); // smulh x23, x20, x24 -+ __ udivw(r21, r4, r28); // udiv w21, w4, w28 -+ __ sdivw(r30, r10, r22); // sdiv w30, w10, w22 -+ __ lslvw(r29, r2, r26); // lslv w29, w2, w26 -+ __ lsrvw(r28, r22, r10); // lsrv w28, w22, w10 -+ __ asrvw(r11, r24, r12); // asrv w11, w24, w12 -+ __ rorvw(r21, r30, r16); // rorv w21, w30, w16 -+ __ udiv(r1, r0, r13); // udiv x1, x0, x13 -+ __ sdiv(r2, r17, r6); // sdiv x2, x17, x6 -+ __ lslv(r10, r24, r21); // lslv x10, x24, x21 -+ __ lsrv(r5, r9, r6); // lsrv x5, x9, x6 -+ __ asrv(r0, r27, r4); // asrv x0, x27, x4 -+ __ rorv(r28, r4, r2); // rorv x28, x4, x2 -+ __ umulh(r1, r30, r7); // umulh x1, x30, x7 -+ __ smulh(r30, r5, r10); // smulh x30, x5, x10 +- __ udivw(r21, r25, r27); // udiv w21, w25, w27 +- __ sdivw(r13, r10, r16); // sdiv w13, w10, w16 +- __ lslvw(r28, r1, r17); // lslv w28, w1, w17 +- __ lsrvw(r25, r23, r10); // lsrv w25, w23, w10 +- __ asrvw(r7, r3, r7); // asrv w7, w3, w7 +- __ rorvw(r14, r30, r14); // rorv w14, w30, w14 +- __ udiv(r12, r22, r15); // udiv x12, x22, x15 +- __ sdiv(r2, r25, r13); // sdiv x2, x25, x13 +- __ lslv(r7, r23, r21); // lslv x7, x23, x21 +- __ lsrv(r11, r12, r0); // lsrv x11, x12, x0 +- __ asrv(r30, r9, r28); // asrv x30, x9, x28 +- __ rorv(r13, r5, r22); // rorv x13, x5, x22 +- __ umulh(r5, r21, r4); // umulh x5, x21, x4 +- __ smulh(r17, r2, r7); // smulh x17, x2, x7 ++ __ udivw(r14, r0, r20); // udiv w14, w0, w20 ++ __ sdivw(r27, r12, r21); // sdiv w27, w12, w21 ++ __ lslvw(r12, r10, r26); // lslv w12, w10, w26 ++ __ lsrvw(r14, r19, r6); // lsrv w14, w19, w6 ++ __ asrvw(r27, r19, r30); // asrv w27, w19, w30 ++ __ rorvw(r6, r14, r16); // rorv w6, w14, w16 ++ __ udiv(r17, r13, r2); // udiv x17, x13, x2 ++ __ sdiv(r0, r29, r2); // sdiv x0, x29, x2 ++ __ lslv(r12, r16, r2); // lslv x12, x16, x2 ++ __ lsrv(r9, r23, r29); // lsrv x9, x23, x29 ++ __ asrv(r6, r17, r29); // asrv x6, x17, x29 ++ __ rorv(r14, r30, r26); // rorv x14, x30, x26 ++ __ umulh(r17, r24, r26); // umulh x17, x24, x26 ++ __ smulh(r20, r26, r14); // smulh x20, x26, x14 // FourRegMulOp -- __ maddw(r2, r5, r21, r9); // madd w2, w5, w21, w9 -- __ msubw(r24, r24, r4, r8); // msub w24, w24, w4, w8 -- __ madd(r11, r12, r15, r19); // madd x11, x12, x15, x19 -- __ msub(r29, r25, r12, r25); // msub x29, x25, x12, x25 -- __ smaddl(r17, r11, r12, r22); // smaddl x17, w11, w12, x22 -- __ smsubl(r28, r3, r20, r18); // smsubl x28, w3, w20, x18 -- __ umaddl(r7, r4, r28, r26); // umaddl x7, w4, w28, x26 -- __ umsubl(r22, r10, r17, r5); // umsubl x22, w10, w17, x5 -+ __ maddw(r7, r15, r13, r17); // madd w7, w15, w13, w17 -+ __ msubw(r25, r1, r12, r28); // msub w25, w1, w12, w28 -+ __ madd(r2, r11, r30, r9); // madd x2, x11, x30, x9 -+ __ msub(r5, r23, r3, r22); // msub x5, x23, x3, x22 -+ __ smaddl(r25, r10, r9, r4); // smaddl x25, w10, w9, x4 -+ __ smsubl(r5, r8, r7, r18); // smsubl x5, w8, w7, x18 -+ __ umaddl(r24, r5, r26, r25); // umaddl x24, w5, w26, x25 -+ __ umsubl(r14, r1, r26, r28); // umsubl x14, w1, w26, x28 +- __ maddw(r12, r12, r17, r12); // madd w12, w12, w17, w12 +- __ msubw(r30, r15, r1, r27); // msub w30, w15, w1, w27 +- __ madd(r2, r19, r17, r29); // madd x2, x19, x17, x29 +- __ msub(r4, r23, r3, r30); // msub x4, x23, x3, x30 +- __ smaddl(r15, r23, r17, r15); // smaddl x15, w23, w17, x15 +- __ smsubl(r27, r12, r1, r13); // smsubl x27, w12, w1, x13 +- __ umaddl(r6, r13, r12, r17); // umaddl x6, w13, w12, x17 +- __ umsubl(r25, r1, r6, r10); // umsubl x25, w1, w6, x10 ++ __ maddw(r27, r8, r2, r7); // madd w27, w8, w2, w7 ++ __ msubw(r28, r13, r25, r12); // msub w28, w13, w25, w12 ++ __ madd(r4, r9, r10, r27); // madd x4, x9, x10, x27 ++ __ msub(r22, r10, r8, r30); // msub x22, x10, x8, x30 ++ __ smaddl(r20, r20, r25, r5); // smaddl x20, w20, w25, x5 ++ __ smsubl(r22, r22, r11, r27); // smsubl x22, w22, w11, x27 ++ __ umaddl(r4, r6, r12, r19); // umaddl x4, w6, w12, x19 ++ __ umsubl(r17, r15, r8, r0); // umsubl x17, w15, w8, x0 // ThreeRegFloatOp -- __ fmuls(v17, v3, v17); // fmul s17, s3, s17 -- __ fdivs(v11, v17, v6); // fdiv s11, s17, s6 -- __ fadds(v29, v7, v9); // fadd s29, s7, s9 -- __ fsubs(v7, v12, v19); // fsub s7, s12, s19 -- __ fmuls(v0, v23, v3); // fmul s0, s23, s3 -- __ fmuld(v26, v3, v21); // fmul d26, d3, d21 -- __ fdivd(v0, v19, v5); // fdiv d0, d19, d5 -- __ faddd(v0, v26, v9); // fadd d0, d26, d9 -- __ fsubd(v25, v21, v21); // fsub d25, d21, d21 -- __ fmuld(v16, v13, v19); // fmul d16, d13, d19 -+ __ fmuls(v24, v22, v8); // fmul s24, s22, s8 -+ __ fdivs(v16, v3, v6); // fdiv s16, s3, s6 -+ __ fadds(v16, v21, v25); // fadd s16, s21, s25 -+ __ fsubs(v0, v26, v27); // fsub s0, s26, s27 -+ __ fmuls(v24, v3, v17); // fmul s24, s3, s17 -+ __ fmuld(v9, v8, v6); // fmul d9, d8, d6 -+ __ fdivd(v22, v19, v30); // fdiv d22, d19, d30 -+ __ faddd(v14, v17, v3); // fadd d14, d17, d3 -+ __ fsubd(v24, v27, v20); // fsub d24, d27, d20 -+ __ fmuld(v12, v1, v22); // fmul d12, d1, d22 +- __ fmuls(v17, v3, v4); // fmul s17, s3, s4 +- __ fdivs(v16, v5, v21); // fdiv s16, s5, s21 +- __ fadds(v3, v27, v17); // fadd s3, s27, s17 +- __ fsubs(v25, v10, v15); // fsub s25, s10, s15 +- __ fmuls(v10, v17, v0); // fmul s10, s17, s0 +- __ fmuld(v28, v26, v3); // fmul d28, d26, d3 +- __ fdivd(v4, v0, v27); // fdiv d4, d0, d27 +- __ faddd(v28, v14, v2); // fadd d28, d14, d2 +- __ fsubd(v12, v26, v23); // fsub d12, d26, d23 +- __ fmuld(v15, v30, v1); // fmul d15, d30, d1 ++ __ fmuls(v22, v5, v10); // fmul s22, s5, s10 ++ __ fdivs(v4, v8, v16); // fdiv s4, s8, s16 ++ __ fadds(v25, v8, v6); // fadd s25, s8, s6 ++ __ fsubs(v6, v27, v25); // fsub s6, s27, s25 ++ __ fmuls(v10, v23, v9); // fmul s10, s23, s9 ++ __ fmuld(v22, v17, v12); // fmul d22, d17, d12 ++ __ fdivd(v11, v0, v20); // fdiv d11, d0, d20 ++ __ faddd(v0, v12, v15); // fadd d0, d12, d15 ++ __ fsubd(v15, v22, v4); // fsub d15, d22, d4 ++ __ fmuld(v29, v1, v25); // fmul d29, d1, d25 // FourRegFloatOp -- __ fmadds(v29, v18, v0, v16); // fmadd s29, s18, s0, s16 -- __ fmsubs(v23, v13, v29, v5); // fmsub s23, s13, s29, s5 -- __ fnmadds(v9, v7, v10, v14); // fnmadd s9, s7, s10, s14 -- __ fnmadds(v25, v28, v15, v23); // fnmadd s25, s28, s15, s23 -- __ fmaddd(v6, v13, v21, v17); // fmadd d6, d13, d21, d17 -- __ fmsubd(v3, v21, v2, v7); // fmsub d3, d21, d2, d7 -- __ fnmaddd(v10, v25, v5, v17); // fnmadd d10, d25, d5, d17 -- __ fnmaddd(v14, v14, v20, v18); // fnmadd d14, d14, d20, d18 -+ __ fmadds(v16, v8, v11, v29); // fmadd s16, s8, s11, s29 -+ __ fmsubs(v22, v19, v18, v1); // fmsub s22, s19, s18, s1 -+ __ fnmadds(v15, v24, v24, v9); // fnmadd s15, s24, s24, s9 -+ __ fnmadds(v27, v19, v13, v23); // fnmadd s27, s19, s13, s23 -+ __ fmaddd(v3, v0, v16, v12); // fmadd d3, d0, d16, d12 -+ __ fmsubd(v19, v3, v18, v10); // fmsub d19, d3, d18, d10 -+ __ fnmaddd(v1, v2, v11, v20); // fnmadd d1, d2, d11, d20 -+ __ fnmaddd(v12, v9, v25, v14); // fnmadd d12, d9, d25, d14 +- __ fmadds(v4, v5, v5, v13); // fmadd s4, s5, s5, s13 +- __ fmsubs(v21, v13, v28, v1); // fmsub s21, s13, s28, s1 +- __ fnmadds(v17, v3, v29, v7); // fnmadd s17, s3, s29, s7 +- __ fnmadds(v23, v25, v29, v26); // fnmadd s23, s25, s29, s26 +- __ fmaddd(v14, v7, v30, v26); // fmadd d14, d7, d30, d26 +- __ fmsubd(v22, v7, v10, v9); // fmsub d22, d7, d10, d9 +- __ fnmaddd(v7, v7, v14, v9); // fnmadd d7, d7, d14, d9 +- __ fnmaddd(v14, v24, v15, v24); // fnmadd d14, d24, d15, d24 ++ __ fmadds(v9, v27, v19, v5); // fmadd s9, s27, s19, s5 ++ __ fmsubs(v26, v3, v6, v26); // fmsub s26, s3, s6, s26 ++ __ fnmadds(v4, v12, v8, v20); // fnmadd s4, s12, s8, s20 ++ __ fnmadds(v25, v9, v21, v17); // fnmadd s25, s9, s21, s17 ++ __ fmaddd(v7, v3, v30, v22); // fmadd d7, d3, d30, d22 ++ __ fmsubd(v1, v27, v10, v10); // fmsub d1, d27, d10, d10 ++ __ fnmaddd(v17, v8, v22, v1); // fnmadd d17, d8, d22, d1 ++ __ fnmaddd(v14, v28, v2, v27); // fnmadd d14, d28, d2, d27 // TwoRegFloatOp -- __ fmovs(v15, v2); // fmov s15, s2 -- __ fabss(v18, v7); // fabs s18, s7 -- __ fnegs(v3, v6); // fneg s3, s6 -- __ fsqrts(v12, v1); // fsqrt s12, s1 -- __ fcvts(v9, v0); // fcvt d9, s0 -- __ fmovd(v4, v5); // fmov d4, d5 -- __ fabsd(v3, v15); // fabs d3, d15 -- __ fnegd(v17, v25); // fneg d17, d25 -- __ fsqrtd(v12, v24); // fsqrt d12, d24 -- __ fcvtd(v21, v5); // fcvt s21, d5 -+ __ fmovs(v0, v23); // fmov s0, s23 -+ __ fabss(v23, v6); // fabs s23, s6 -+ __ fnegs(v4, v4); // fneg s4, s4 -+ __ fsqrts(v5, v28); // fsqrt s5, s28 -+ __ fcvts(v21, v15); // fcvt d21, s15 -+ __ fmovd(v11, v5); // fmov d11, d5 -+ __ fabsd(v18, v4); // fabs d18, d4 -+ __ fnegd(v11, v12); // fneg d11, d12 -+ __ fsqrtd(v15, v8); // fsqrt d15, d8 -+ __ fcvtd(v8, v2); // fcvt s8, d2 +- __ fmovs(v22, v2); // fmov s22, s2 +- __ fabss(v0, v3); // fabs s0, s3 +- __ fnegs(v9, v17); // fneg s9, s17 +- __ fsqrts(v24, v11); // fsqrt s24, s11 +- __ fcvts(v15, v25); // fcvt d15, s25 +- __ fmovd(v4, v3); // fmov d4, d3 +- __ fabsd(v26, v22); // fabs d26, d22 +- __ fnegd(v30, v19); // fneg d30, d19 +- __ fsqrtd(v12, v14); // fsqrt d12, d14 +- __ fcvtd(v17, v7); // fcvt s17, d7 ++ __ fmovs(v27, v30); // fmov s27, s30 ++ __ fabss(v5, v1); // fabs s5, s1 ++ __ fnegs(v23, v19); // fneg s23, s19 ++ __ fsqrts(v28, v17); // fsqrt s28, s17 ++ __ fcvts(v25, v6); // fcvt d25, s6 ++ __ fmovd(v20, v14); // fmov d20, d14 ++ __ fabsd(v17, v10); // fabs d17, d10 ++ __ fnegd(v10, v17); // fneg d10, d17 ++ __ fsqrtd(v21, v17); // fsqrt d21, d17 ++ __ fcvtd(v21, v15); // fcvt s21, d15 // FloatConvertOp -- __ fcvtzsw(r4, v21); // fcvtzs w4, s21 -- __ fcvtzs(r27, v3); // fcvtzs x27, s3 -- __ fcvtzdw(r29, v8); // fcvtzs w29, d8 -- __ fcvtzd(r9, v21); // fcvtzs x9, d21 -- __ scvtfws(v20, r29); // scvtf s20, w29 -- __ scvtfs(v7, r8); // scvtf s7, x8 -- __ scvtfwd(v12, r21); // scvtf d12, w21 -- __ scvtfd(v16, r21); // scvtf d16, x21 -- __ fmovs(r18, v5); // fmov w18, s5 -- __ fmovd(r25, v8); // fmov x25, d8 -- __ fmovs(v18, r26); // fmov s18, w26 -- __ fmovd(v0, r11); // fmov d0, x11 -+ __ fcvtzsw(r19, v18); // fcvtzs w19, s18 -+ __ fcvtzs(r17, v0); // fcvtzs x17, s0 -+ __ fcvtzdw(r0, v13); // fcvtzs w0, d13 -+ __ fcvtzd(r22, v9); // fcvtzs x22, d9 -+ __ scvtfws(v6, r29); // scvtf s6, w29 -+ __ scvtfs(v12, r14); // scvtf s12, x14 -+ __ scvtfwd(v16, r22); // scvtf d16, w22 -+ __ scvtfd(v14, r5); // scvtf d14, x5 -+ __ fmovs(r7, v0); // fmov w7, s0 -+ __ fmovd(r28, v6); // fmov x28, d6 -+ __ fmovs(v2, r26); // fmov s2, w26 -+ __ fmovd(v4, r0); // fmov d4, x0 +- __ fcvtzsw(r24, v14); // fcvtzs w24, s14 +- __ fcvtzs(r13, v26); // fcvtzs x13, s26 +- __ fcvtzdw(r2, v1); // fcvtzs w2, d1 +- __ fcvtzd(r5, v11); // fcvtzs x5, d11 +- __ scvtfws(v14, r19); // scvtf s14, w19 +- __ scvtfs(v1, r22); // scvtf s1, x22 +- __ scvtfwd(v27, r17); // scvtf d27, w17 +- __ scvtfd(v22, r9); // scvtf d22, x9 +- __ fmovs(r14, v3); // fmov w14, s3 +- __ fmovd(r12, v17); // fmov x12, d17 +- __ fmovs(v8, r27); // fmov s8, w27 +- __ fmovd(v29, r28); // fmov d29, x28 ++ __ fcvtzsw(r7, v11); // fcvtzs w7, s11 ++ __ fcvtzs(r2, v29); // fcvtzs x2, s29 ++ __ fcvtzdw(r3, v25); // fcvtzs w3, d25 ++ __ fcvtzd(r28, v8); // fcvtzs x28, d8 ++ __ scvtfws(v11, r3); // scvtf s11, w3 ++ __ scvtfs(v2, r21); // scvtf s2, x21 ++ __ scvtfwd(v29, r25); // scvtf d29, w25 ++ __ scvtfd(v19, r3); // scvtf d19, x3 ++ __ fmovs(r20, v29); // fmov w20, s29 ++ __ fmovd(r23, v17); // fmov x23, d17 ++ __ fmovs(v0, r28); // fmov s0, w28 ++ __ fmovd(v9, r20); // fmov d9, x20 // TwoRegFloatOp -- __ fcmps(v16, v6); // fcmp s16, s6 -- __ fcmpd(v16, v29); // fcmp d16, d29 -- __ fcmps(v30, 0.0); // fcmp s30, #0.0 -- __ fcmpd(v9, 0.0); // fcmp d9, #0.0 -+ __ fcmps(v1, v11); // fcmp s1, s11 -+ __ fcmpd(v6, v21); // fcmp d6, d21 -+ __ fcmps(v16, 0.0); // fcmp s16, #0.0 -+ __ fcmpd(v22, 0.0); // fcmp d22, #0.0 +- __ fcmps(v0, v30); // fcmp s0, s30 +- __ fcmpd(v12, v9); // fcmp d12, d9 +- __ fcmps(v10, 0.0); // fcmp s10, #0.0 +- __ fcmpd(v25, 0.0); // fcmp d25, #0.0 ++ __ fcmps(v7, v12); // fcmp s7, s12 ++ __ fcmpd(v13, v14); // fcmp d13, d14 ++ __ fcmps(v12, 0.0); // fcmp s12, #0.0 ++ __ fcmpd(v1, 0.0); // fcmp d1, #0.0 // LoadStorePairOp -- __ stpw(r27, r4, Address(r12, -16)); // stp w27, w4, [x12, #-16] -- __ ldpw(r3, r9, Address(r10, 80)); // ldp w3, w9, [x10, #80] -- __ ldpsw(r16, r3, Address(r3, 64)); // ldpsw x16, x3, [x3, #64] -- __ stp(r10, r28, Address(r19, -192)); // stp x10, x28, [x19, #-192] -- __ ldp(r19, r18, Address(r7, -192)); // ldp x19, x18, [x7, #-192] -+ __ stpw(r5, r0, Address(r2, 96)); // stp w5, w0, [x2, #96] -+ __ ldpw(r14, r29, Address(r19, -64)); // ldp w14, w29, [x19, #-64] -+ __ ldpsw(r15, r3, Address(r3, -160)); // ldpsw x15, x3, [x3, #-160] -+ __ stp(r7, r13, Address(r27, -224)); // stp x7, x13, [x27, #-224] -+ __ ldp(r17, r14, Address(r1, 128)); // ldp x17, x14, [x1, #128] +- __ stpw(r8, r30, Address(r27, -144)); // stp w8, w30, [x27, #-144] +- __ ldpw(r21, r19, Address(r24, 80)); // ldp w21, w19, [x24, #80] +- __ ldpsw(r16, r27, Address(r2, -240)); // ldpsw x16, x27, [x2, #-240] +- __ stp(r21, r5, Address(r6, -128)); // stp x21, x5, [x6, #-128] +- __ ldp(r29, r25, Address(r28, -32)); // ldp x29, x25, [x28, #-32] ++ __ stpw(r12, r2, Address(r22, -64)); // stp w12, w2, [x22, #-64] ++ __ ldpw(r27, r9, Address(r24, -208)); // ldp w27, w9, [x24, #-208] ++ __ ldpsw(r15, r4, Address(r24, -176)); // ldpsw x15, x4, [x24, #-176] ++ __ stp(r5, r21, Address(r0, 16)); // stp x5, x21, [x0, #16] ++ __ ldp(r6, r23, Address(r9, -208)); // ldp x6, x23, [x9, #-208] // LoadStorePairOp -- __ stpw(r10, r16, Address(__ pre(r30, 16))); // stp w10, w16, [x30, #16]! -- __ ldpw(r2, r4, Address(__ pre(r18, -240))); // ldp w2, w4, [x18, #-240]! -- __ ldpsw(r24, r19, Address(__ pre(r13, 48))); // ldpsw x24, x19, [x13, #48]! -- __ stp(r17, r0, Address(__ pre(r24, 0))); // stp x17, x0, [x24, #0]! -- __ ldp(r14, r26, Address(__ pre(r3, -192))); // ldp x14, x26, [x3, #-192]! -+ __ stpw(r21, r22, Address(__ pre(r4, 128))); // stp w21, w22, [x4, #128]! -+ __ ldpw(r17, r13, Address(__ pre(r2, -96))); // ldp w17, w13, [x2, #-96]! -+ __ ldpsw(r21, r25, Address(__ pre(r23, -144))); // ldpsw x21, x25, [x23, #-144]! -+ __ stp(r4, r16, Address(__ pre(r15, -16))); // stp x4, x16, [x15, #-16]! -+ __ ldp(r29, r21, Address(__ pre(r25, -160))); // ldp x29, x21, [x25, #-160]! +- __ stpw(r8, r13, Address(__ pre(r0, 128))); // stp w8, w13, [x0, #128]! +- __ ldpw(r25, r20, Address(__ pre(r1, -160))); // ldp w25, w20, [x1, #-160]! +- __ ldpsw(r14, r24, Address(__ pre(r22, -32))); // ldpsw x14, x24, [x22, #-32]! +- __ stp(r17, r1, Address(__ pre(r6, 80))); // stp x17, x1, [x6, #80]! +- __ ldp(r21, r17, Address(__ pre(r25, -64))); // ldp x21, x17, [x25, #-64]! ++ __ stpw(r0, r3, Address(__ pre(r29, 16))); // stp w0, w3, [x29, #16]! ++ __ ldpw(r29, r16, Address(__ pre(r1, -144))); // ldp w29, w16, [x1, #-144]! ++ __ ldpsw(r27, r19, Address(__ pre(r21, 16))); // ldpsw x27, x19, [x21, #16]! ++ __ stp(r6, r17, Address(__ pre(r13, -176))); // stp x6, x17, [x13, #-176]! ++ __ ldp(r0, r24, Address(__ pre(r1, 16))); // ldp x0, x24, [x1, #16]! // LoadStorePairOp -- __ stpw(r22, r1, Address(__ post(r0, 80))); // stp w22, w1, [x0], #80 -- __ ldpw(r18, r10, Address(__ post(r0, -16))); // ldp w18, w10, [x0], #-16 -- __ ldpsw(r24, r24, Address(__ post(r22, -16))); // ldpsw x24, x24, [x22], #-16 -- __ stp(r12, r12, Address(__ post(r4, 80))); // stp x12, x12, [x4], #80 -- __ ldp(r4, r9, Address(__ post(r19, -240))); // ldp x4, x9, [x19], #-240 -+ __ stpw(r24, r17, Address(__ post(r26, 80))); // stp w24, w17, [x26], #80 -+ __ ldpw(r3, r30, Address(__ post(r30, -240))); // ldp w3, w30, [x30], #-240 -+ __ ldpsw(r3, r19, Address(__ post(r30, -32))); // ldpsw x3, x19, [x30], #-32 -+ __ stp(r25, r1, Address(__ post(r27, -144))); // stp x25, x1, [x27], #-144 -+ __ ldp(r26, r20, Address(__ post(r28, -64))); // ldp x26, x20, [x28], #-64 +- __ stpw(r17, r21, Address(__ post(r20, -128))); // stp w17, w21, [x20], #-128 +- __ ldpw(r28, r28, Address(__ post(r2, 64))); // ldp w28, w28, [x2], #64 +- __ ldpsw(r19, r30, Address(__ post(r10, -256))); // ldpsw x19, x30, [x10], #-256 +- __ stp(r17, r15, Address(__ post(r17, -16))); // stp x17, x15, [x17], #-16 +- __ ldp(r17, r0, Address(__ post(r25, -32))); // ldp x17, x0, [x25], #-32 ++ __ stpw(r0, r20, Address(__ post(r22, 0))); // stp w0, w20, [x22], #0 ++ __ ldpw(r17, r12, Address(__ post(r14, -48))); // ldp w17, w12, [x14], #-48 ++ __ ldpsw(r10, r26, Address(__ post(r1, 112))); // ldpsw x10, x26, [x1], #112 ++ __ stp(r20, r24, Address(__ post(r13, -96))); // stp x20, x24, [x13], #-96 ++ __ ldp(r1, r12, Address(__ post(r7, 48))); // ldp x1, x12, [x7], #48 // LoadStorePairOp -- __ stnpw(r18, r26, Address(r6, -224)); // stnp w18, w26, [x6, #-224] -- __ ldnpw(r21, r20, Address(r1, 112)); // ldnp w21, w20, [x1, #112] -- __ stnp(r25, r29, Address(r20, -224)); // stnp x25, x29, [x20, #-224] -- __ ldnp(r1, r5, Address(r23, 112)); // ldnp x1, x5, [x23, #112] -+ __ stnpw(r29, r25, Address(r9, -48)); // stnp w29, w25, [x9, #-48] -+ __ ldnpw(r25, r14, Address(r19, -128)); // ldnp w25, w14, [x19, #-128] -+ __ stnp(r25, r22, Address(r3, 32)); // stnp x25, x22, [x3, #32] -+ __ ldnp(r9, r18, Address(r29, -208)); // ldnp x9, x18, [x29, #-208] +- __ stnpw(r14, r5, Address(r24, -32)); // stnp w14, w5, [x24, #-32] +- __ ldnpw(r23, r19, Address(r1, 112)); // ldnp w23, w19, [x1, #112] +- __ stnp(r11, r6, Address(r14, 64)); // stnp x11, x6, [x14, #64] +- __ ldnp(r2, r11, Address(r27, -224)); // ldnp x2, x11, [x27, #-224] ++ __ stnpw(r5, r10, Address(r23, -80)); // stnp w5, w10, [x23, #-80] ++ __ ldnpw(r8, r10, Address(r24, -48)); // ldnp w8, w10, [x24, #-48] ++ __ stnp(r11, r15, Address(r11, 64)); // stnp x11, x15, [x11, #64] ++ __ ldnp(r9, r28, Address(r5, 64)); // ldnp x9, x28, [x5, #64] // LdStSIMDOp -- __ ld1(v4, __ T8B, Address(r20)); // ld1 {v4.8B}, [x20] -- __ ld1(v24, v25, __ T16B, Address(__ post(r10, 32))); // ld1 {v24.16B, v25.16B}, [x10], 32 -- __ ld1(v24, v25, v26, __ T1D, Address(__ post(r6, r15))); // ld1 {v24.1D, v25.1D, v26.1D}, [x6], x15 -- __ ld1(v3, v4, v5, v6, __ T8H, Address(__ post(r4, 64))); // ld1 {v3.8H, v4.8H, v5.8H, v6.8H}, [x4], 64 -- __ ld1r(v2, __ T8B, Address(r6)); // ld1r {v2.8B}, [x6] -- __ ld1r(v13, __ T4S, Address(__ post(r14, 4))); // ld1r {v13.4S}, [x14], 4 -- __ ld1r(v15, __ T1D, Address(__ post(r21, r24))); // ld1r {v15.1D}, [x21], x24 -- __ ld2(v9, v10, __ T2D, Address(r21)); // ld2 {v9.2D, v10.2D}, [x21] -- __ ld2(v29, v30, __ T4H, Address(__ post(r21, 16))); // ld2 {v29.4H, v30.4H}, [x21], 16 -- __ ld2r(v8, v9, __ T16B, Address(r14)); // ld2r {v8.16B, v9.16B}, [x14] -- __ ld2r(v7, v8, __ T2S, Address(__ post(r20, 8))); // ld2r {v7.2S, v8.2S}, [x20], 8 -- __ ld2r(v28, v29, __ T2D, Address(__ post(r3, r3))); // ld2r {v28.2D, v29.2D}, [x3], x3 -- __ ld3(v27, v28, v29, __ T4S, Address(__ post(r11, r29))); // ld3 {v27.4S, v28.4S, v29.4S}, [x11], x29 -- __ ld3(v16, v17, v18, __ T2S, Address(r10)); // ld3 {v16.2S, v17.2S, v18.2S}, [x10] -- __ ld3r(v21, v22, v23, __ T8H, Address(r12)); // ld3r {v21.8H, v22.8H, v23.8H}, [x12] -- __ ld3r(v4, v5, v6, __ T4S, Address(__ post(r29, 12))); // ld3r {v4.4S, v5.4S, v6.4S}, [x29], 12 -- __ ld3r(v24, v25, v26, __ T1D, Address(__ post(r9, r19))); // ld3r {v24.1D, v25.1D, v26.1D}, [x9], x19 -- __ ld4(v10, v11, v12, v13, __ T8H, Address(__ post(r3, 64))); // ld4 {v10.8H, v11.8H, v12.8H, v13.8H}, [x3], 64 -- __ ld4(v27, v28, v29, v30, __ T8B, Address(__ post(r28, r9))); // ld4 {v27.8B, v28.8B, v29.8B, v30.8B}, [x28], x9 -- __ ld4r(v21, v22, v23, v24, __ T8B, Address(r30)); // ld4r {v21.8B, v22.8B, v23.8B, v24.8B}, [x30] -- __ ld4r(v23, v24, v25, v26, __ T4H, Address(__ post(r14, 8))); // ld4r {v23.4H, v24.4H, v25.4H, v26.4H}, [x14], 8 -- __ ld4r(v4, v5, v6, v7, __ T2S, Address(__ post(r13, r20))); // ld4r {v4.2S, v5.2S, v6.2S, v7.2S}, [x13], x20 -+ __ ld1(v21, __ T8B, Address(r19)); // ld1 {v21.8B}, [x19] -+ __ ld1(v27, v28, __ T16B, Address(__ post(r20, 32))); // ld1 {v27.16B, v28.16B}, [x20], 32 -+ __ ld1(v5, v6, v7, __ T1D, Address(__ post(r22, r6))); // ld1 {v5.1D, v6.1D, v7.1D}, [x22], x6 -+ __ ld1(v22, v23, v24, v25, __ T8H, Address(__ post(r12, 64))); // ld1 {v22.8H, v23.8H, v24.8H, v25.8H}, [x12], 64 -+ __ ld1r(v17, __ T8B, Address(r9)); // ld1r {v17.8B}, [x9] -+ __ ld1r(v5, __ T4S, Address(__ post(r21, 4))); // ld1r {v5.4S}, [x21], 4 -+ __ ld1r(v10, __ T1D, Address(__ post(r28, r18))); // ld1r {v10.1D}, [x28], x18 -+ __ ld2(v26, v27, __ T2D, Address(r15)); // ld2 {v26.2D, v27.2D}, [x15] -+ __ ld2(v16, v17, __ T4H, Address(__ post(r26, 16))); // ld2 {v16.4H, v17.4H}, [x26], 16 -+ __ ld2r(v14, v15, __ T16B, Address(r2)); // ld2r {v14.16B, v15.16B}, [x2] -+ __ ld2r(v18, v19, __ T2S, Address(__ post(r28, 8))); // ld2r {v18.2S, v19.2S}, [x28], 8 -+ __ ld2r(v19, v20, __ T2D, Address(__ post(r0, r22))); // ld2r {v19.2D, v20.2D}, [x0], x22 -+ __ ld3(v16, v17, v18, __ T4S, Address(__ post(r2, r18))); // ld3 {v16.4S, v17.4S, v18.4S}, [x2], x18 -+ __ ld3(v24, v25, v26, __ T2S, Address(r0)); // ld3 {v24.2S, v25.2S, v26.2S}, [x0] -+ __ ld3r(v4, v5, v6, __ T8H, Address(r16)); // ld3r {v4.8H, v5.8H, v6.8H}, [x16] -+ __ ld3r(v5, v6, v7, __ T4S, Address(__ post(r1, 12))); // ld3r {v5.4S, v6.4S, v7.4S}, [x1], 12 -+ __ ld3r(v7, v8, v9, __ T1D, Address(__ post(r10, r16))); // ld3r {v7.1D, v8.1D, v9.1D}, [x10], x16 -+ __ ld4(v22, v23, v24, v25, __ T8H, Address(__ post(r20, 64))); // ld4 {v22.8H, v23.8H, v24.8H, v25.8H}, [x20], 64 -+ __ ld4(v15, v16, v17, v18, __ T8B, Address(__ post(r4, r25))); // ld4 {v15.8B, v16.8B, v17.8B, v18.8B}, [x4], x25 -+ __ ld4r(v0, v1, v2, v3, __ T8B, Address(r5)); // ld4r {v0.8B, v1.8B, v2.8B, v3.8B}, [x5] -+ __ ld4r(v0, v1, v2, v3, __ T4H, Address(__ post(r1, 8))); // ld4r {v0.4H, v1.4H, v2.4H, v3.4H}, [x1], 8 -+ __ ld4r(v30, v31, v0, v1, __ T2S, Address(__ post(r28, r14))); // ld4r {v30.2S, v31.2S, v0.2S, v1.2S}, [x28], x14 +- __ ld1(v16, __ T8B, Address(r17)); // ld1 {v16.8B}, [x17] +- __ ld1(v29, v30, __ T16B, Address(__ post(r9, 32))); // ld1 {v29.16B, v30.16B}, [x9], 32 +- __ ld1(v30, v31, v0, __ T1D, Address(__ post(r24, r21))); // ld1 {v30.1D, v31.1D, v0.1D}, [x24], x21 +- __ ld1(v0, v1, v2, v3, __ T8H, Address(__ post(r2, 64))); // ld1 {v0.8H, v1.8H, v2.8H, v3.8H}, [x2], 64 +- __ ld1r(v20, __ T8B, Address(r9)); // ld1r {v20.8B}, [x9] +- __ ld1r(v17, __ T4S, Address(__ post(r0, 4))); // ld1r {v17.4S}, [x0], 4 +- __ ld1r(v21, __ T1D, Address(__ post(r22, r26))); // ld1r {v21.1D}, [x22], x26 +- __ ld2(v19, v20, __ T2D, Address(r25)); // ld2 {v19.2D, v20.2D}, [x25] +- __ ld2(v10, v11, __ T4H, Address(__ post(r5, 16))); // ld2 {v10.4H, v11.4H}, [x5], 16 +- __ ld2r(v10, v11, __ T16B, Address(r24)); // ld2r {v10.16B, v11.16B}, [x24] +- __ ld2r(v13, v14, __ T2S, Address(__ post(r29, 8))); // ld2r {v13.2S, v14.2S}, [x29], 8 +- __ ld2r(v22, v23, __ T2D, Address(__ post(r28, r2))); // ld2r {v22.2D, v23.2D}, [x28], x2 +- __ ld3(v30, v31, v0, __ T4S, Address(__ post(r4, r11))); // ld3 {v30.4S, v31.4S, v0.4S}, [x4], x11 +- __ ld3(v29, v30, v31, __ T2S, Address(r0)); // ld3 {v29.2S, v30.2S, v31.2S}, [x0] +- __ ld3r(v23, v24, v25, __ T8H, Address(r27)); // ld3r {v23.8H, v24.8H, v25.8H}, [x27] +- __ ld3r(v3, v4, v5, __ T4S, Address(__ post(r10, 12))); // ld3r {v3.4S, v4.4S, v5.4S}, [x10], 12 +- __ ld3r(v19, v20, v21, __ T1D, Address(__ post(r14, r22))); // ld3r {v19.1D, v20.1D, v21.1D}, [x14], x22 +- __ ld4(v14, v15, v16, v17, __ T8H, Address(__ post(r0, 64))); // ld4 {v14.8H, v15.8H, v16.8H, v17.8H}, [x0], 64 +- __ ld4(v30, v31, v0, v1, __ T8B, Address(__ post(r22, r25))); // ld4 {v30.8B, v31.8B, v0.8B, v1.8B}, [x22], x25 +- __ ld4r(v25, v26, v27, v28, __ T8B, Address(r0)); // ld4r {v25.8B, v26.8B, v27.8B, v28.8B}, [x0] +- __ ld4r(v10, v11, v12, v13, __ T4H, Address(__ post(r8, 8))); // ld4r {v10.4H, v11.4H, v12.4H, v13.4H}, [x8], 8 +- __ ld4r(v1, v2, v3, v4, __ T2S, Address(__ post(r6, r28))); // ld4r {v1.2S, v2.2S, v3.2S, v4.2S}, [x6], x28 ++ __ ld1(v11, __ T8B, Address(r20)); // ld1 {v11.8B}, [x20] ++ __ ld1(v19, v20, __ T16B, Address(__ post(r8, 32))); // ld1 {v19.16B, v20.16B}, [x8], 32 ++ __ ld1(v3, v4, v5, __ T1D, Address(__ post(r2, r3))); // ld1 {v3.1D, v4.1D, v5.1D}, [x2], x3 ++ __ ld1(v21, v22, v23, v24, __ T8H, Address(__ post(r3, 64))); // ld1 {v21.8H, v22.8H, v23.8H, v24.8H}, [x3], 64 ++ __ ld1r(v14, __ T8B, Address(r5)); // ld1r {v14.8B}, [x5] ++ __ ld1r(v13, __ T4S, Address(__ post(r27, 4))); // ld1r {v13.4S}, [x27], 4 ++ __ ld1r(v17, __ T1D, Address(__ post(r19, r0))); // ld1r {v17.1D}, [x19], x0 ++ __ ld2(v27, v28, __ T2D, Address(r5)); // ld2 {v27.2D, v28.2D}, [x5] ++ __ ld2(v26, v27, __ T4H, Address(__ post(r4, 16))); // ld2 {v26.4H, v27.4H}, [x4], 16 ++ __ ld2r(v8, v9, __ T16B, Address(r23)); // ld2r {v8.16B, v9.16B}, [x23] ++ __ ld2r(v14, v15, __ T2S, Address(__ post(r10, 8))); // ld2r {v14.2S, v15.2S}, [x10], 8 ++ __ ld2r(v10, v11, __ T2D, Address(__ post(r21, r19))); // ld2r {v10.2D, v11.2D}, [x21], x19 ++ __ ld3(v17, v18, v19, __ T4S, Address(__ post(r14, r30))); // ld3 {v17.4S, v18.4S, v19.4S}, [x14], x30 ++ __ ld3(v20, v21, v22, __ T2S, Address(r20)); // ld3 {v20.2S, v21.2S, v22.2S}, [x20] ++ __ ld3r(v24, v25, v26, __ T8H, Address(r21)); // ld3r {v24.8H, v25.8H, v26.8H}, [x21] ++ __ ld3r(v26, v27, v28, __ T4S, Address(__ post(r1, 12))); // ld3r {v26.4S, v27.4S, v28.4S}, [x1], 12 ++ __ ld3r(v12, v13, v14, __ T1D, Address(__ post(r2, r0))); // ld3r {v12.1D, v13.1D, v14.1D}, [x2], x0 ++ __ ld4(v21, v22, v23, v24, __ T8H, Address(__ post(r6, 64))); // ld4 {v21.8H, v22.8H, v23.8H, v24.8H}, [x6], 64 ++ __ ld4(v17, v18, v19, v20, __ T8B, Address(__ post(r28, r22))); // ld4 {v17.8B, v18.8B, v19.8B, v20.8B}, [x28], x22 ++ __ ld4r(v19, v20, v21, v22, __ T8B, Address(r25)); // ld4r {v19.8B, v20.8B, v21.8B, v22.8B}, [x25] ++ __ ld4r(v6, v7, v8, v9, __ T4H, Address(__ post(r23, 8))); // ld4r {v6.4H, v7.4H, v8.4H, v9.4H}, [x23], 8 ++ __ ld4r(v8, v9, v10, v11, __ T2S, Address(__ post(r9, r26))); // ld4r {v8.2S, v9.2S, v10.2S, v11.2S}, [x9], x26 // SpecialCases -- __ ccmn(zr, zr, 3u, Assembler::LE); // ccmn xzr, xzr, #3, LE -- __ ccmnw(zr, zr, 5u, Assembler::EQ); // ccmn wzr, wzr, #5, EQ -- __ ccmp(zr, 1, 4u, Assembler::NE); // ccmp xzr, 1, #4, NE -- __ ccmpw(zr, 2, 2, Assembler::GT); // ccmp wzr, 2, #2, GT -- __ extr(zr, zr, zr, 0); // extr xzr, xzr, xzr, 0 -- __ stlxp(r0, zr, zr, sp); // stlxp w0, xzr, xzr, [sp] -- __ stlxpw(r2, zr, zr, r3); // stlxp w2, wzr, wzr, [x3] -- __ stxp(r4, zr, zr, r5); // stxp w4, xzr, xzr, [x5] -- __ stxpw(r6, zr, zr, sp); // stxp w6, wzr, wzr, [sp] -- __ dup(v0, __ T16B, zr); // dup v0.16b, wzr -- __ mov(v1, __ T1D, 0, zr); // mov v1.d[0], xzr -- __ mov(v1, __ T2S, 1, zr); // mov v1.s[1], wzr -- __ mov(v1, __ T4H, 2, zr); // mov v1.h[2], wzr -- __ mov(v1, __ T8B, 3, zr); // mov v1.b[3], wzr -- __ ld1(v31, v0, __ T2D, Address(__ post(r1, r0))); // ld1 {v31.2d, v0.2d}, [x1], x0 +- __ ccmn(zr, zr, 3u, Assembler::LE); // ccmn xzr, xzr, #3, LE +- __ ccmnw(zr, zr, 5u, Assembler::EQ); // ccmn wzr, wzr, #5, EQ +- __ ccmp(zr, 1, 4u, Assembler::NE); // ccmp xzr, 1, #4, NE +- __ ccmpw(zr, 2, 2, Assembler::GT); // ccmp wzr, 2, #2, GT +- __ extr(zr, zr, zr, 0); // extr xzr, xzr, xzr, 0 +- __ stlxp(r0, zr, zr, sp); // stlxp w0, xzr, xzr, [sp] +- __ stlxpw(r2, zr, zr, r3); // stlxp w2, wzr, wzr, [x3] +- __ stxp(r4, zr, zr, r5); // stxp w4, xzr, xzr, [x5] +- __ stxpw(r6, zr, zr, sp); // stxp w6, wzr, wzr, [sp] +- __ dup(v0, __ T16B, zr); // dup v0.16b, wzr +- __ mov(v1, __ T1D, 0, zr); // mov v1.d[0], xzr +- __ mov(v1, __ T2S, 1, zr); // mov v1.s[1], wzr +- __ mov(v1, __ T4H, 2, zr); // mov v1.h[2], wzr +- __ mov(v1, __ T8B, 3, zr); // mov v1.b[3], wzr +- __ ld1(v31, v0, __ T2D, Address(__ post(r1, r0))); // ld1 {v31.2d, v0.2d}, [x1], x0 + __ ccmn(zr, zr, 3u, Assembler::LE); // ccmn xzr, xzr, #3, LE + __ ccmnw(zr, zr, 5u, Assembler::EQ); // ccmn wzr, wzr, #5, EQ + __ ccmp(zr, 1, 4u, Assembler::NE); // ccmp xzr, 1, #4, NE @@ -4230,40 +3373,73 @@ index 2a17d8e0f..943d2a615 100644 + __ mov(v1, __ T4H, 2, zr); // mov v1.h[2], wzr + __ mov(v1, __ T8B, 3, zr); // mov v1.b[3], wzr + __ ld1(v31, v0, __ T2D, Address(__ post(r1, r0))); // ld1 {v31.2d, v0.2d}, [x1], x0 ++ __ sve_cpy(z0, __ S, p0, v1); // mov z0.s, p0/m, s1 ++ __ sve_inc(r0, __ S); // incw x0 ++ __ sve_dec(r1, __ H); // dech x1 ++ __ sve_lsl(z0, __ B, z1, 7); // lsl z0.b, z1.b, #7 ++ __ sve_lsl(z21, __ H, z1, 15); // lsl z21.h, z1.h, #15 ++ __ sve_lsl(z0, __ S, z1, 31); // lsl z0.s, z1.s, #31 ++ __ sve_lsl(z0, __ D, z1, 63); // lsl z0.d, z1.d, #63 ++ __ sve_lsr(z0, __ B, z1, 7); // lsr z0.b, z1.b, #7 ++ __ sve_asr(z0, __ H, z11, 15); // asr z0.h, z11.h, #15 ++ __ sve_lsr(z30, __ S, z1, 31); // lsr z30.s, z1.s, #31 ++ __ sve_asr(z0, __ D, z1, 63); // asr z0.d, z1.d, #63 ++ __ sve_addvl(sp, r0, 31); // addvl sp, x0, #31 ++ __ sve_addpl(r1, sp, -32); // addpl x1, sp, -32 ++ __ sve_cntp(r8, __ B, p0, p1); // cntp x8, p0, p1.b ++ __ sve_dup(z0, __ B, 127); // dup z0.b, 127 ++ __ sve_dup(z1, __ H, -128); // dup z1.h, -128 ++ __ sve_dup(z2, __ S, 32512); // dup z2.s, 32512 ++ __ sve_dup(z7, __ D, -32768); // dup z7.d, -32768 ++ __ sve_ld1b(z0, __ B, p0, Address(sp)); // ld1b {z0.b}, p0/z, [sp] ++ __ sve_ld1h(z10, __ H, p1, Address(sp, -8)); // ld1h {z10.h}, p1/z, [sp, #-8, MUL VL] ++ __ sve_ld1w(z20, __ S, p2, Address(r0, 7)); // ld1w {z20.s}, p2/z, [x0, #7, MUL VL] ++ __ sve_ld1b(z30, __ B, p3, Address(sp, r8)); // ld1b {z30.b}, p3/z, [sp, x8] ++ __ sve_ld1w(z0, __ S, p4, Address(sp, r28)); // ld1w {z0.s}, p4/z, [sp, x28, LSL #2] ++ __ sve_ld1d(z11, __ D, p5, Address(r0, r1)); // ld1d {z11.d}, p5/z, [x0, x1, LSL #3] ++ __ sve_st1b(z22, __ B, p6, Address(sp)); // st1b {z22.b}, p6, [sp] ++ __ sve_st1b(z31, __ B, p7, Address(sp, -8)); // st1b {z31.b}, p7, [sp, #-8, MUL VL] ++ __ sve_st1w(z0, __ S, p1, Address(r0, 7)); // st1w {z0.s}, p1, [x0, #7, MUL VL] ++ __ sve_st1b(z0, __ B, p2, Address(sp, r1)); // st1b {z0.b}, p2, [sp, x1] ++ __ sve_st1h(z0, __ H, p3, Address(sp, r8)); // st1h {z0.h}, p3, [sp, x8, LSL #1] ++ __ sve_st1d(z0, __ D, p4, Address(r0, r8)); // st1d {z0.d}, p4, [x0, x8, LSL #3] ++ __ sve_ldr(z0, Address(sp)); // ldr z0, [sp] ++ __ sve_ldr(z31, Address(sp, -256)); // ldr z31, [sp, #-256, MUL VL] ++ __ sve_str(z8, Address(r8, 255)); // str z8, [x8, #255, MUL VL] // FloatImmediateOp -- __ fmovd(v0, 2.0); // fmov d0, #2.0 -- __ fmovd(v0, 2.125); // fmov d0, #2.125 -- __ fmovd(v0, 4.0); // fmov d0, #4.0 -- __ fmovd(v0, 4.25); // fmov d0, #4.25 -- __ fmovd(v0, 8.0); // fmov d0, #8.0 -- __ fmovd(v0, 8.5); // fmov d0, #8.5 -- __ fmovd(v0, 16.0); // fmov d0, #16.0 -- __ fmovd(v0, 17.0); // fmov d0, #17.0 -- __ fmovd(v0, 0.125); // fmov d0, #0.125 -- __ fmovd(v0, 0.1328125); // fmov d0, #0.1328125 -- __ fmovd(v0, 0.25); // fmov d0, #0.25 -- __ fmovd(v0, 0.265625); // fmov d0, #0.265625 -- __ fmovd(v0, 0.5); // fmov d0, #0.5 -- __ fmovd(v0, 0.53125); // fmov d0, #0.53125 -- __ fmovd(v0, 1.0); // fmov d0, #1.0 -- __ fmovd(v0, 1.0625); // fmov d0, #1.0625 -- __ fmovd(v0, -2.0); // fmov d0, #-2.0 -- __ fmovd(v0, -2.125); // fmov d0, #-2.125 -- __ fmovd(v0, -4.0); // fmov d0, #-4.0 -- __ fmovd(v0, -4.25); // fmov d0, #-4.25 -- __ fmovd(v0, -8.0); // fmov d0, #-8.0 -- __ fmovd(v0, -8.5); // fmov d0, #-8.5 -- __ fmovd(v0, -16.0); // fmov d0, #-16.0 -- __ fmovd(v0, -17.0); // fmov d0, #-17.0 -- __ fmovd(v0, -0.125); // fmov d0, #-0.125 -- __ fmovd(v0, -0.1328125); // fmov d0, #-0.1328125 -- __ fmovd(v0, -0.25); // fmov d0, #-0.25 -- __ fmovd(v0, -0.265625); // fmov d0, #-0.265625 -- __ fmovd(v0, -0.5); // fmov d0, #-0.5 -- __ fmovd(v0, -0.53125); // fmov d0, #-0.53125 -- __ fmovd(v0, -1.0); // fmov d0, #-1.0 -- __ fmovd(v0, -1.0625); // fmov d0, #-1.0625 +- __ fmovd(v0, 2.0); // fmov d0, #2.0 +- __ fmovd(v0, 2.125); // fmov d0, #2.125 +- __ fmovd(v0, 4.0); // fmov d0, #4.0 +- __ fmovd(v0, 4.25); // fmov d0, #4.25 +- __ fmovd(v0, 8.0); // fmov d0, #8.0 +- __ fmovd(v0, 8.5); // fmov d0, #8.5 +- __ fmovd(v0, 16.0); // fmov d0, #16.0 +- __ fmovd(v0, 17.0); // fmov d0, #17.0 +- __ fmovd(v0, 0.125); // fmov d0, #0.125 +- __ fmovd(v0, 0.1328125); // fmov d0, #0.1328125 +- __ fmovd(v0, 0.25); // fmov d0, #0.25 +- __ fmovd(v0, 0.265625); // fmov d0, #0.265625 +- __ fmovd(v0, 0.5); // fmov d0, #0.5 +- __ fmovd(v0, 0.53125); // fmov d0, #0.53125 +- __ fmovd(v0, 1.0); // fmov d0, #1.0 +- __ fmovd(v0, 1.0625); // fmov d0, #1.0625 +- __ fmovd(v0, -2.0); // fmov d0, #-2.0 +- __ fmovd(v0, -2.125); // fmov d0, #-2.125 +- __ fmovd(v0, -4.0); // fmov d0, #-4.0 +- __ fmovd(v0, -4.25); // fmov d0, #-4.25 +- __ fmovd(v0, -8.0); // fmov d0, #-8.0 +- __ fmovd(v0, -8.5); // fmov d0, #-8.5 +- __ fmovd(v0, -16.0); // fmov d0, #-16.0 +- __ fmovd(v0, -17.0); // fmov d0, #-17.0 +- __ fmovd(v0, -0.125); // fmov d0, #-0.125 +- __ fmovd(v0, -0.1328125); // fmov d0, #-0.1328125 +- __ fmovd(v0, -0.25); // fmov d0, #-0.25 +- __ fmovd(v0, -0.265625); // fmov d0, #-0.265625 +- __ fmovd(v0, -0.5); // fmov d0, #-0.5 +- __ fmovd(v0, -0.53125); // fmov d0, #-0.53125 +- __ fmovd(v0, -1.0); // fmov d0, #-1.0 +- __ fmovd(v0, -1.0625); // fmov d0, #-1.0625 + __ fmovd(v0, 2.0); // fmov d0, #2.0 + __ fmovd(v0, 2.125); // fmov d0, #2.125 + __ fmovd(v0, 4.0); // fmov d0, #4.0 @@ -4298,1124 +3474,1175 @@ index 2a17d8e0f..943d2a615 100644 + __ fmovd(v0, -1.0625); // fmov d0, #-1.0625 // LSEOp -- __ swp(Assembler::xword, r21, r5, r24); // swp x21, x5, [x24] -- __ ldadd(Assembler::xword, r13, r13, r15); // ldadd x13, x13, [x15] -- __ ldbic(Assembler::xword, r22, r19, r26); // ldclr x22, x19, [x26] -- __ ldeor(Assembler::xword, r25, r10, r26); // ldeor x25, x10, [x26] -- __ ldorr(Assembler::xword, r5, r27, r15); // ldset x5, x27, [x15] -- __ ldsmin(Assembler::xword, r19, r5, r11); // ldsmin x19, x5, [x11] -- __ ldsmax(Assembler::xword, r26, r0, r4); // ldsmax x26, x0, [x4] -- __ ldumin(Assembler::xword, r22, r23, r30); // ldumin x22, x23, [x30] -- __ ldumax(Assembler::xword, r18, r28, r8); // ldumax x18, x28, [x8] -+ __ swp(Assembler::xword, r26, r9, r17); // swp x26, x9, [x17] -+ __ ldadd(Assembler::xword, r28, r23, r2); // ldadd x28, x23, [x2] -+ __ ldbic(Assembler::xword, r22, r2, r3); // ldclr x22, x2, [x3] -+ __ ldeor(Assembler::xword, r11, r25, r30); // ldeor x11, x25, [x30] -+ __ ldorr(Assembler::xword, r22, r28, r4); // ldset x22, x28, [x4] -+ __ ldsmin(Assembler::xword, r6, r11, r24); // ldsmin x6, x11, [x24] -+ __ ldsmax(Assembler::xword, r12, zr, sp); // ldsmax x12, xzr, [sp] -+ __ ldumin(Assembler::xword, r23, r30, r9); // ldumin x23, x30, [x9] -+ __ ldumax(Assembler::xword, r6, r1, r20); // ldumax x6, x1, [x20] +- __ swp(Assembler::xword, r16, r20, r15); // swp x16, x20, [x15] +- __ ldadd(Assembler::xword, r2, r7, r28); // ldadd x2, x7, [x28] +- __ ldbic(Assembler::xword, r20, r10, r25); // ldclr x20, x10, [x25] +- __ ldeor(Assembler::xword, r22, r11, r2); // ldeor x22, x11, [x2] +- __ ldorr(Assembler::xword, r1, r10, r19); // ldset x1, x10, [x19] +- __ ldsmin(Assembler::xword, r14, r21, r3); // ldsmin x14, x21, [x3] +- __ ldsmax(Assembler::xword, r28, r27, r13); // ldsmax x28, x27, [x13] +- __ ldumin(Assembler::xword, r17, r30, r21); // ldumin x17, x30, [x21] +- __ ldumax(Assembler::xword, r27, r16, r29); // ldumax x27, x16, [x29] ++ __ swp(Assembler::xword, r11, r15, r21); // swp x11, x15, [x21] ++ __ ldadd(Assembler::xword, r23, r8, r5); // ldadd x23, x8, [x5] ++ __ ldbic(Assembler::xword, r7, r6, r8); // ldclr x7, x6, [x8] ++ __ ldeor(Assembler::xword, r14, r14, r23); // ldeor x14, x14, [x23] ++ __ ldorr(Assembler::xword, r10, r25, r0); // ldset x10, x25, [x0] ++ __ ldsmin(Assembler::xword, r5, r9, r21); // ldsmin x5, x9, [x21] ++ __ ldsmax(Assembler::xword, r4, r27, r17); // ldsmax x4, x27, [x17] ++ __ ldumin(Assembler::xword, r10, r6, r13); // ldumin x10, x6, [x13] ++ __ ldumax(Assembler::xword, r3, r3, r16); // ldumax x3, x3, [x16] // LSEOp -- __ swpa(Assembler::xword, r13, r29, r27); // swpa x13, x29, [x27] -- __ ldadda(Assembler::xword, r11, r5, r13); // ldadda x11, x5, [x13] -- __ ldbica(Assembler::xword, r1, r24, r21); // ldclra x1, x24, [x21] -- __ ldeora(Assembler::xword, r27, r17, r24); // ldeora x27, x17, [x24] -- __ ldorra(Assembler::xword, r18, r30, r5); // ldseta x18, x30, [x5] -- __ ldsmina(Assembler::xword, r7, r22, r25); // ldsmina x7, x22, [x25] -- __ ldsmaxa(Assembler::xword, r4, r26, r19); // ldsmaxa x4, x26, [x19] -- __ ldumina(Assembler::xword, r6, r30, r3); // ldumina x6, x30, [x3] -- __ ldumaxa(Assembler::xword, r24, r23, r5); // ldumaxa x24, x23, [x5] -+ __ swpa(Assembler::xword, r17, r2, r22); // swpa x17, x2, [x22] -+ __ ldadda(Assembler::xword, r14, r27, r10); // ldadda x14, x27, [x10] -+ __ ldbica(Assembler::xword, r6, r30, r19); // ldclra x6, x30, [x19] -+ __ ldeora(Assembler::xword, r0, r25, r11); // ldeora x0, x25, [x11] -+ __ ldorra(Assembler::xword, r23, r0, r30); // ldseta x23, x0, [x30] -+ __ ldsmina(Assembler::xword, r21, r3, r10); // ldsmina x21, x3, [x10] -+ __ ldsmaxa(Assembler::xword, r15, r22, r0); // ldsmaxa x15, x22, [x0] -+ __ ldumina(Assembler::xword, r17, r0, r20); // ldumina x17, x0, [x20] -+ __ ldumaxa(Assembler::xword, r16, r13, r1); // ldumaxa x16, x13, [x1] +- __ swpa(Assembler::xword, r30, r9, r0); // swpa x30, x9, [x0] +- __ ldadda(Assembler::xword, r28, r27, r28); // ldadda x28, x27, [x28] +- __ ldbica(Assembler::xword, r21, r25, r10); // ldclra x21, x25, [x10] +- __ ldeora(Assembler::xword, zr, r20, r15); // ldeora xzr, x20, [x15] +- __ ldorra(Assembler::xword, r1, r25, r14); // ldseta x1, x25, [x14] +- __ ldsmina(Assembler::xword, r21, r26, r29); // ldsmina x21, x26, [x29] +- __ ldsmaxa(Assembler::xword, r8, r29, r25); // ldsmaxa x8, x29, [x25] +- __ ldumina(Assembler::xword, r13, r2, r25); // ldumina x13, x2, [x25] +- __ ldumaxa(Assembler::xword, r15, r23, r0); // ldumaxa x15, x23, [x0] ++ __ swpa(Assembler::xword, r9, r28, r2); // swpa x9, x28, [x2] ++ __ ldadda(Assembler::xword, r23, r2, r1); // ldadda x23, x2, [x1] ++ __ ldbica(Assembler::xword, r4, r26, r7); // ldclra x4, x26, [x7] ++ __ ldeora(Assembler::xword, r0, r3, r10); // ldeora x0, x3, [x10] ++ __ ldorra(Assembler::xword, r24, r25, r3); // ldseta x24, x25, [x3] ++ __ ldsmina(Assembler::xword, r11, r8, r1); // ldsmina x11, x8, [x1] ++ __ ldsmaxa(Assembler::xword, r16, r13, r29); // ldsmaxa x16, x13, [x29] ++ __ ldumina(Assembler::xword, r6, r0, r5); // ldumina x6, x0, [x5] ++ __ ldumaxa(Assembler::xword, r16, r17, r13); // ldumaxa x16, x17, [x13] // LSEOp -- __ swpal(Assembler::xword, r24, r18, r28); // swpal x24, x18, [x28] -- __ ldaddal(Assembler::xword, r19, zr, r7); // ldaddal x19, xzr, [x7] -- __ ldbical(Assembler::xword, r13, r6, r28); // ldclral x13, x6, [x28] -- __ ldeoral(Assembler::xword, r8, r15, r21); // ldeoral x8, x15, [x21] -- __ ldorral(Assembler::xword, r2, r13, r1); // ldsetal x2, x13, [x1] -- __ ldsminal(Assembler::xword, r17, r29, r25); // ldsminal x17, x29, [x25] -- __ ldsmaxal(Assembler::xword, r25, r18, r14); // ldsmaxal x25, x18, [x14] -- __ lduminal(Assembler::xword, zr, r6, r27); // lduminal xzr, x6, [x27] -- __ ldumaxal(Assembler::xword, r16, r5, r15); // ldumaxal x16, x5, [x15] -+ __ swpal(Assembler::xword, r27, r15, r23); // swpal x27, x15, [x23] -+ __ ldaddal(Assembler::xword, r19, r30, r1); // ldaddal x19, x30, [x1] -+ __ ldbical(Assembler::xword, r15, r28, r23); // ldclral x15, x28, [x23] -+ __ ldeoral(Assembler::xword, r7, r15, r19); // ldeoral x7, x15, [x19] -+ __ ldorral(Assembler::xword, r11, r12, r10); // ldsetal x11, x12, [x10] -+ __ ldsminal(Assembler::xword, r6, r7, r12); // ldsminal x6, x7, [x12] -+ __ ldsmaxal(Assembler::xword, r28, r5, r13); // ldsmaxal x28, x5, [x13] -+ __ lduminal(Assembler::xword, r9, r20, r17); // lduminal x9, x20, [x17] -+ __ ldumaxal(Assembler::xword, r21, r25, r11); // ldumaxal x21, x25, [x11] +- __ swpal(Assembler::xword, r3, r1, r2); // swpal x3, x1, [x2] +- __ ldaddal(Assembler::xword, r28, r3, r20); // ldaddal x28, x3, [x20] +- __ ldbical(Assembler::xword, r14, zr, r14); // ldclral x14, xzr, [x14] +- __ ldeoral(Assembler::xword, r7, r28, r2); // ldeoral x7, x28, [x2] +- __ ldorral(Assembler::xword, r0, r11, r5); // ldsetal x0, x11, [x5] +- __ ldsminal(Assembler::xword, r11, r14, r20); // ldsminal x11, x14, [x20] +- __ ldsmaxal(Assembler::xword, zr, r4, r2); // ldsmaxal xzr, x4, [x2] +- __ lduminal(Assembler::xword, r26, r0, r22); // lduminal x26, x0, [x22] +- __ ldumaxal(Assembler::xword, r17, r1, r13); // ldumaxal x17, x1, [x13] ++ __ swpal(Assembler::xword, r11, r27, r14); // swpal x11, x27, [x14] ++ __ ldaddal(Assembler::xword, r2, r13, r21); // ldaddal x2, x13, [x21] ++ __ ldbical(Assembler::xword, r22, zr, r12); // ldclral x22, xzr, [x12] ++ __ ldeoral(Assembler::xword, r7, r30, r15); // ldeoral x7, x30, [x15] ++ __ ldorral(Assembler::xword, r7, r16, r15); // ldsetal x7, x16, [x15] ++ __ ldsminal(Assembler::xword, r16, r26, r13); // ldsminal x16, x26, [x13] ++ __ ldsmaxal(Assembler::xword, r23, r25, r27); // ldsmaxal x23, x25, [x27] ++ __ lduminal(Assembler::xword, r4, r14, sp); // lduminal x4, x14, [sp] ++ __ ldumaxal(Assembler::xword, r24, r1, r17); // ldumaxal x24, x1, [x17] // LSEOp -- __ swpl(Assembler::xword, r11, r18, r3); // swpl x11, x18, [x3] -- __ ldaddl(Assembler::xword, r26, r20, r2); // ldaddl x26, x20, [x2] -- __ ldbicl(Assembler::xword, r11, r4, r11); // ldclrl x11, x4, [x11] -- __ ldeorl(Assembler::xword, r30, r19, r23); // ldeorl x30, x19, [x23] -- __ ldorrl(Assembler::xword, r3, r15, r14); // ldsetl x3, x15, [x14] -- __ ldsminl(Assembler::xword, r30, r22, r20); // ldsminl x30, x22, [x20] -- __ ldsmaxl(Assembler::xword, r7, r5, r24); // ldsmaxl x7, x5, [x24] -- __ lduminl(Assembler::xword, r23, r16, r15); // lduminl x23, x16, [x15] -- __ ldumaxl(Assembler::xword, r11, r19, r0); // ldumaxl x11, x19, [x0] -+ __ swpl(Assembler::xword, r19, r24, r24); // swpl x19, x24, [x24] -+ __ ldaddl(Assembler::xword, r8, r26, r30); // ldaddl x8, x26, [x30] -+ __ ldbicl(Assembler::xword, r17, r18, r8); // ldclrl x17, x18, [x8] -+ __ ldeorl(Assembler::xword, r2, r3, r3); // ldeorl x2, x3, [x3] -+ __ ldorrl(Assembler::xword, r26, r7, r16); // ldsetl x26, x7, [x16] -+ __ ldsminl(Assembler::xword, r27, r6, r5); // ldsminl x27, x6, [x5] -+ __ ldsmaxl(Assembler::xword, r22, r0, r20); // ldsmaxl x22, x0, [x20] -+ __ lduminl(Assembler::xword, r11, r26, r2); // lduminl x11, x26, [x2] -+ __ ldumaxl(Assembler::xword, r30, r29, r4); // ldumaxl x30, x29, [x4] +- __ swpl(Assembler::xword, r23, r26, r20); // swpl x23, x26, [x20] +- __ ldaddl(Assembler::xword, r14, r11, r12); // ldaddl x14, x11, [x12] +- __ ldbicl(Assembler::xword, r12, zr, r15); // ldclrl x12, xzr, [x15] +- __ ldeorl(Assembler::xword, r27, r14, r8); // ldeorl x27, x14, [x8] +- __ ldorrl(Assembler::xword, r10, r30, r25); // ldsetl x10, x30, [x25] +- __ ldsminl(Assembler::xword, r22, r7, r16); // ldsminl x22, x7, [x16] +- __ ldsmaxl(Assembler::xword, r1, r16, r8); // ldsmaxl x1, x16, [x8] +- __ lduminl(Assembler::xword, r1, r1, r26); // lduminl x1, x1, [x26] +- __ ldumaxl(Assembler::xword, r0, r23, r15); // ldumaxl x0, x23, [x15] ++ __ swpl(Assembler::xword, r2, r8, r24); // swpl x2, x8, [x24] ++ __ ldaddl(Assembler::xword, r20, r27, r19); // ldaddl x20, x27, [x19] ++ __ ldbicl(Assembler::xword, r19, r17, r6); // ldclrl x19, x17, [x6] ++ __ ldeorl(Assembler::xword, r14, r28, r26); // ldeorl x14, x28, [x26] ++ __ ldorrl(Assembler::xword, r2, r16, r19); // ldsetl x2, x16, [x19] ++ __ ldsminl(Assembler::xword, r14, r16, r4); // ldsminl x14, x16, [x4] ++ __ ldsmaxl(Assembler::xword, r25, r8, r9); // ldsmaxl x25, x8, [x9] ++ __ lduminl(Assembler::xword, r10, r5, r29); // lduminl x10, x5, [x29] ++ __ ldumaxl(Assembler::xword, r6, r2, r14); // ldumaxl x6, x2, [x14] // LSEOp -- __ swp(Assembler::word, r28, r28, r1); // swp w28, w28, [x1] -- __ ldadd(Assembler::word, r11, r21, r12); // ldadd w11, w21, [x12] -- __ ldbic(Assembler::word, r29, r0, r18); // ldclr w29, w0, [x18] -- __ ldeor(Assembler::word, r5, r0, r25); // ldeor w5, w0, [x25] -- __ ldorr(Assembler::word, r14, r0, r26); // ldset w14, w0, [x26] -- __ ldsmin(Assembler::word, r28, r18, r29); // ldsmin w28, w18, [x29] -- __ ldsmax(Assembler::word, r15, r1, r29); // ldsmax w15, w1, [x29] -- __ ldumin(Assembler::word, r8, r26, r28); // ldumin w8, w26, [x28] -- __ ldumax(Assembler::word, r17, r14, r4); // ldumax w17, w14, [x4] -+ __ swp(Assembler::word, r4, r5, r7); // swp w4, w5, [x7] -+ __ ldadd(Assembler::word, r10, r26, r2); // ldadd w10, w26, [x2] -+ __ ldbic(Assembler::word, r27, r16, r27); // ldclr w27, w16, [x27] -+ __ ldeor(Assembler::word, zr, r23, r10); // ldeor wzr, w23, [x10] -+ __ ldorr(Assembler::word, r4, r2, r13); // ldset w4, w2, [x13] -+ __ ldsmin(Assembler::word, r3, r15, r3); // ldsmin w3, w15, [x3] -+ __ ldsmax(Assembler::word, r3, r10, r6); // ldsmax w3, w10, [x6] -+ __ ldumin(Assembler::word, r8, r11, r10); // ldumin w8, w11, [x10] -+ __ ldumax(Assembler::word, r29, r30, r13); // ldumax w29, w30, [x13] +- __ swp(Assembler::word, r11, r16, r8); // swp w11, w16, [x8] +- __ ldadd(Assembler::word, r1, r7, r14); // ldadd w1, w7, [x14] +- __ ldbic(Assembler::word, r16, zr, r9); // ldclr w16, wzr, [x9] +- __ ldeor(Assembler::word, r22, r6, r13); // ldeor w22, w6, [x13] +- __ ldorr(Assembler::word, r11, r13, r4); // ldset w11, w13, [x4] +- __ ldsmin(Assembler::word, r16, r22, r0); // ldsmin w16, w22, [x0] +- __ ldsmax(Assembler::word, r28, zr, r10); // ldsmax w28, wzr, [x10] +- __ ldumin(Assembler::word, r16, r5, r8); // ldumin w16, w5, [x8] +- __ ldumax(Assembler::word, r26, r20, r15); // ldumax w26, w20, [x15] ++ __ swp(Assembler::word, r17, r11, r4); // swp w17, w11, [x4] ++ __ ldadd(Assembler::word, r7, r16, r15); // ldadd w7, w16, [x15] ++ __ ldbic(Assembler::word, r11, r25, r9); // ldclr w11, w25, [x9] ++ __ ldeor(Assembler::word, r3, r14, r0); // ldeor w3, w14, [x0] ++ __ ldorr(Assembler::word, r0, r30, r0); // ldset w0, w30, [x0] ++ __ ldsmin(Assembler::word, r6, r10, r28); // ldsmin w6, w10, [x28] ++ __ ldsmax(Assembler::word, r7, r14, r6); // ldsmax w7, w14, [x6] ++ __ ldumin(Assembler::word, r6, r30, r0); // ldumin w6, w30, [x0] ++ __ ldumax(Assembler::word, r22, r30, r29); // ldumax w22, w30, [x29] // LSEOp -- __ swpa(Assembler::word, r24, r25, r1); // swpa w24, w25, [x1] -- __ ldadda(Assembler::word, r10, r17, r17); // ldadda w10, w17, [x17] -- __ ldbica(Assembler::word, r29, r20, r21); // ldclra w29, w20, [x21] -- __ ldeora(Assembler::word, r29, r9, r12); // ldeora w29, w9, [x12] -- __ ldorra(Assembler::word, r11, r6, r5); // ldseta w11, w6, [x5] -- __ ldsmina(Assembler::word, r21, r7, r21); // ldsmina w21, w7, [x21] -- __ ldsmaxa(Assembler::word, r10, r23, r12); // ldsmaxa w10, w23, [x12] -- __ ldumina(Assembler::word, r21, r5, r10); // ldumina w21, w5, [x10] -- __ ldumaxa(Assembler::word, r30, r20, r18); // ldumaxa w30, w20, [x18] -+ __ swpa(Assembler::word, r11, r17, r20); // swpa w11, w17, [x20] -+ __ ldadda(Assembler::word, r26, r16, r6); // ldadda w26, w16, [x6] -+ __ ldbica(Assembler::word, r21, r10, r1); // ldclra w21, w10, [x1] -+ __ ldeora(Assembler::word, r29, r12, r23); // ldeora w29, w12, [x23] -+ __ ldorra(Assembler::word, r29, r8, r8); // ldseta w29, w8, [x8] -+ __ ldsmina(Assembler::word, r11, r10, r14); // ldsmina w11, w10, [x14] -+ __ ldsmaxa(Assembler::word, r4, r13, r22); // ldsmaxa w4, w13, [x22] -+ __ ldumina(Assembler::word, r7, r13, r7); // ldumina w7, w13, [x7] -+ __ ldumaxa(Assembler::word, r14, r0, sp); // ldumaxa w14, w0, [sp] +- __ swpa(Assembler::word, r27, r6, r16); // swpa w27, w6, [x16] +- __ ldadda(Assembler::word, zr, zr, r2); // ldadda wzr, wzr, [x2] +- __ ldbica(Assembler::word, r24, r28, r8); // ldclra w24, w28, [x8] +- __ ldeora(Assembler::word, r15, r9, r23); // ldeora w15, w9, [x23] +- __ ldorra(Assembler::word, r26, r2, r7); // ldseta w26, w2, [x7] +- __ ldsmina(Assembler::word, r3, r17, r15); // ldsmina w3, w17, [x15] +- __ ldsmaxa(Assembler::word, r19, r5, r21); // ldsmaxa w19, w5, [x21] +- __ ldumina(Assembler::word, r7, r26, r12); // ldumina w7, w26, [x12] +- __ ldumaxa(Assembler::word, r12, r7, r29); // ldumaxa w12, w7, [x29] ++ __ swpa(Assembler::word, r16, r14, r19); // swpa w16, w14, [x19] ++ __ ldadda(Assembler::word, r21, r3, r25); // ldadda w21, w3, [x25] ++ __ ldbica(Assembler::word, r2, r16, r19); // ldclra w2, w16, [x19] ++ __ ldeora(Assembler::word, r26, r20, r23); // ldeora w26, w20, [x23] ++ __ ldorra(Assembler::word, r17, r6, sp); // ldseta w17, w6, [sp] ++ __ ldsmina(Assembler::word, r5, r23, r30); // ldsmina w5, w23, [x30] ++ __ ldsmaxa(Assembler::word, r11, r12, r14); // ldsmaxa w11, w12, [x14] ++ __ ldumina(Assembler::word, r2, r20, r13); // ldumina w2, w20, [x13] ++ __ ldumaxa(Assembler::word, r15, r17, r20); // ldumaxa w15, w17, [x20] // LSEOp -- __ swpal(Assembler::word, r13, r23, r5); // swpal w13, w23, [x5] -- __ ldaddal(Assembler::word, r15, r24, r5); // ldaddal w15, w24, [x5] -- __ ldbical(Assembler::word, r9, r10, r25); // ldclral w9, w10, [x25] -- __ ldeoral(Assembler::word, r20, r17, r17); // ldeoral w20, w17, [x17] -- __ ldorral(Assembler::word, r12, r18, r30); // ldsetal w12, w18, [x30] -- __ ldsminal(Assembler::word, r3, r3, r25); // ldsminal w3, w3, [x25] -- __ ldsmaxal(Assembler::word, r26, r25, r10); // ldsmaxal w26, w25, [x10] -- __ lduminal(Assembler::word, r2, r11, sp); // lduminal w2, w11, [sp] -- __ ldumaxal(Assembler::word, r7, r2, r5); // ldumaxal w7, w2, [x5] -+ __ swpal(Assembler::word, r17, r2, r28); // swpal w17, w2, [x28] -+ __ ldaddal(Assembler::word, r19, r11, r10); // ldaddal w19, w11, [x10] -+ __ ldbical(Assembler::word, r12, r19, r20); // ldclral w12, w19, [x20] -+ __ ldeoral(Assembler::word, r0, r8, r8); // ldeoral w0, w8, [x8] -+ __ ldorral(Assembler::word, r17, r3, r24); // ldsetal w17, w3, [x24] -+ __ ldsminal(Assembler::word, r25, r5, r7); // ldsminal w25, w5, [x7] -+ __ ldsmaxal(Assembler::word, r16, r30, r9); // ldsmaxal w16, w30, [x9] -+ __ lduminal(Assembler::word, r10, zr, r14); // lduminal w10, wzr, [x14] -+ __ ldumaxal(Assembler::word, r17, r19, r11); // ldumaxal w17, w19, [x11] +- __ swpal(Assembler::word, r9, r8, r20); // swpal w9, w8, [x20] +- __ ldaddal(Assembler::word, r8, zr, r30); // ldaddal w8, wzr, [x30] +- __ ldbical(Assembler::word, r0, r6, r12); // ldclral w0, w6, [x12] +- __ ldeoral(Assembler::word, r17, r23, r2); // ldeoral w17, w23, [x2] +- __ ldorral(Assembler::word, r0, r30, r1); // ldsetal w0, w30, [x1] +- __ ldsminal(Assembler::word, r22, r3, r15); // ldsminal w22, w3, [x15] +- __ ldsmaxal(Assembler::word, r25, r21, r13); // ldsmaxal w25, w21, [x13] +- __ lduminal(Assembler::word, r13, r24, r27); // lduminal w13, w24, [x27] +- __ ldumaxal(Assembler::word, r20, r3, r11); // ldumaxal w20, w3, [x11] ++ __ swpal(Assembler::word, r6, r28, r23); // swpal w6, w28, [x23] ++ __ ldaddal(Assembler::word, r27, r16, r13); // ldaddal w27, w16, [x13] ++ __ ldbical(Assembler::word, r2, r23, r24); // ldclral w2, w23, [x24] ++ __ ldeoral(Assembler::word, r0, r28, r10); // ldeoral w0, w28, [x10] ++ __ ldorral(Assembler::word, r3, r15, r5); // ldsetal w3, w15, [x5] ++ __ ldsminal(Assembler::word, r3, r11, r29); // ldsminal w3, w11, [x29] ++ __ ldsmaxal(Assembler::word, r22, r27, r6); // ldsmaxal w22, w27, [x6] ++ __ lduminal(Assembler::word, r17, r20, r16); // lduminal w17, w20, [x16] ++ __ ldumaxal(Assembler::word, r23, r15, r7); // ldumaxal w23, w15, [x7] // LSEOp -- __ swpl(Assembler::word, r0, r7, r20); // swpl w0, w7, [x20] -- __ ldaddl(Assembler::word, r5, zr, r2); // ldaddl w5, wzr, [x2] -- __ ldbicl(Assembler::word, r27, r25, r27); // ldclrl w27, w25, [x27] -- __ ldeorl(Assembler::word, r30, r24, r26); // ldeorl w30, w24, [x26] -- __ ldorrl(Assembler::word, r15, r2, r22); // ldsetl w15, w2, [x22] -- __ ldsminl(Assembler::word, r0, r3, sp); // ldsminl w0, w3, [sp] -- __ ldsmaxl(Assembler::word, r15, r20, r10); // ldsmaxl w15, w20, [x10] -- __ lduminl(Assembler::word, r22, r21, r14); // lduminl w22, w21, [x14] -- __ ldumaxl(Assembler::word, r6, r30, r2); // ldumaxl w6, w30, [x2] -+ __ swpl(Assembler::word, r20, r1, r13); // swpl w20, w1, [x13] -+ __ ldaddl(Assembler::word, r26, r11, r20); // ldaddl w26, w11, [x20] -+ __ ldbicl(Assembler::word, r18, r24, r30); // ldclrl w18, w24, [x30] -+ __ ldeorl(Assembler::word, r12, r25, r20); // ldeorl w12, w25, [x20] -+ __ ldorrl(Assembler::word, r14, r29, r5); // ldsetl w14, w29, [x5] -+ __ ldsminl(Assembler::word, r2, r26, r27); // ldsminl w2, w26, [x27] -+ __ ldsmaxl(Assembler::word, r25, r27, r11); // ldsmaxl w25, w27, [x11] -+ __ lduminl(Assembler::word, r4, r29, r7); // lduminl w4, w29, [x7] -+ __ ldumaxl(Assembler::word, r16, r29, r10); // ldumaxl w16, w29, [x10] +- __ swpl(Assembler::word, r3, r13, r21); // swpl w3, w13, [x21] +- __ ldaddl(Assembler::word, r26, r15, r26); // ldaddl w26, w15, [x26] +- __ ldbicl(Assembler::word, r9, r19, r2); // ldclrl w9, w19, [x2] +- __ ldeorl(Assembler::word, r24, r29, r7); // ldeorl w24, w29, [x7] +- __ ldorrl(Assembler::word, r29, r25, r15); // ldsetl w29, w25, [x15] +- __ ldsminl(Assembler::word, r11, r30, r7); // ldsminl w11, w30, [x7] +- __ ldsmaxl(Assembler::word, r11, r2, r6); // ldsmaxl w11, w2, [x6] +- __ lduminl(Assembler::word, r16, r11, r14); // lduminl w16, w11, [x14] +- __ ldumaxl(Assembler::word, r5, r8, r11); // ldumaxl w5, w8, [x11] ++ __ swpl(Assembler::word, r8, r16, r14); // swpl w8, w16, [x14] ++ __ ldaddl(Assembler::word, r23, r16, r23); // ldaddl w23, w16, [x23] ++ __ ldbicl(Assembler::word, r28, r12, r7); // ldclrl w28, w12, [x7] ++ __ ldeorl(Assembler::word, r28, r7, r19); // ldeorl w28, w7, [x19] ++ __ ldorrl(Assembler::word, r7, r12, r11); // ldsetl w7, w12, [x11] ++ __ ldsminl(Assembler::word, r10, zr, r20); // ldsminl w10, wzr, [x20] ++ __ ldsmaxl(Assembler::word, r9, r8, sp); // ldsmaxl w9, w8, [sp] ++ __ lduminl(Assembler::word, r10, r8, r2); // lduminl w10, w8, [x2] ++ __ ldumaxl(Assembler::word, r17, zr, sp); // ldumaxl w17, wzr, [sp] ++ ++// SVEVectorOp ++ __ sve_add(z2, __ H, z7, z22); // add z2.h, z7.h, z22.h ++ __ sve_sub(z30, __ S, z22, z30); // sub z30.s, z22.s, z30.s ++ __ sve_fadd(z10, __ D, z22, z25); // fadd z10.d, z22.d, z25.d ++ __ sve_fmul(z23, __ D, z16, z12); // fmul z23.d, z16.d, z12.d ++ __ sve_fsub(z3, __ D, z17, z25); // fsub z3.d, z17.d, z25.d ++ __ sve_abs(z25, __ S, p0, z4); // abs z25.s, p0/m, z4.s ++ __ sve_add(z23, __ H, p6, z26); // add z23.h, p6/m, z23.h, z26.h ++ __ sve_asr(z6, __ D, p0, z17); // asr z6.d, p0/m, z6.d, z17.d ++ __ sve_cnt(z23, __ D, p3, z3); // cnt z23.d, p3/m, z3.d ++ __ sve_lsl(z11, __ S, p7, z9); // lsl z11.s, p7/m, z11.s, z9.s ++ __ sve_lsr(z27, __ S, p7, z3); // lsr z27.s, p7/m, z27.s, z3.s ++ __ sve_mul(z9, __ S, p4, z2); // mul z9.s, p4/m, z9.s, z2.s ++ __ sve_neg(z16, __ B, p2, z15); // neg z16.b, p2/m, z15.b ++ __ sve_not(z9, __ D, p2, z9); // not z9.d, p2/m, z9.d ++ __ sve_smax(z10, __ S, p5, z23); // smax z10.s, p5/m, z10.s, z23.s ++ __ sve_smin(z13, __ B, p5, z25); // smin z13.b, p5/m, z13.b, z25.b ++ __ sve_sub(z19, __ S, p5, z0); // sub z19.s, p5/m, z19.s, z0.s ++ __ sve_fabs(z17, __ D, p0, z22); // fabs z17.d, p0/m, z22.d ++ __ sve_fadd(z9, __ S, p2, z16); // fadd z9.s, p2/m, z9.s, z16.s ++ __ sve_fdiv(z17, __ S, p5, z0); // fdiv z17.s, p5/m, z17.s, z0.s ++ __ sve_fmax(z29, __ S, p5, z3); // fmax z29.s, p5/m, z29.s, z3.s ++ __ sve_fmin(z1, __ S, p3, z17); // fmin z1.s, p3/m, z1.s, z17.s ++ __ sve_fmul(z14, __ D, p2, z0); // fmul z14.d, p2/m, z14.d, z0.d ++ __ sve_fneg(z19, __ D, p4, z22); // fneg z19.d, p4/m, z22.d ++ __ sve_frintm(z17, __ D, p1, z15); // frintm z17.d, p1/m, z15.d ++ __ sve_frintn(z8, __ D, p4, z4); // frintn z8.d, p4/m, z4.d ++ __ sve_frintp(z5, __ D, p4, z29); // frintp z5.d, p4/m, z29.d ++ __ sve_fsqrt(z11, __ D, p0, z19); // fsqrt z11.d, p0/m, z19.d ++ __ sve_fsub(z10, __ D, p4, z28); // fsub z10.d, p4/m, z10.d, z28.d ++ __ sve_fmla(z13, __ D, p3, z15, z11); // fmla z13.d, p3/m, z15.d, z11.d ++ __ sve_fmls(z6, __ S, p7, z20, z15); // fmls z6.s, p7/m, z20.s, z15.s ++ __ sve_fnmla(z30, __ S, p2, z13, z7); // fnmla z30.s, p2/m, z13.s, z7.s ++ __ sve_fnmls(z22, __ D, p6, z14, z19); // fnmls z22.d, p6/m, z14.d, z19.d ++ __ sve_mla(z30, __ H, p3, z25, z0); // mla z30.h, p3/m, z25.h, z0.h ++ __ sve_mls(z10, __ D, p2, z24, z1); // mls z10.d, p2/m, z24.d, z1.d ++ __ sve_and(z6, z17, z22); // and z6.d, z17.d, z22.d ++ __ sve_eor(z10, z9, z17); // eor z10.d, z9.d, z17.d ++ __ sve_orr(z2, z12, z21); // orr z2.d, z12.d, z21.d ++ ++// SVEReductionOp ++ __ sve_andv(v15, __ S, p6, z14); // andv s15, p6, z14.s ++ __ sve_orv(v9, __ D, p3, z7); // orv d9, p3, z7.d ++ __ sve_eorv(v30, __ H, p5, z9); // eorv h30, p5, z9.h ++ __ sve_smaxv(v7, __ S, p4, z26); // smaxv s7, p4, z26.s ++ __ sve_sminv(v20, __ S, p3, z29); // sminv s20, p3, z29.s ++ __ sve_fminv(v28, __ S, p3, z16); // fminv s28, p3, z16.s ++ __ sve_fmaxv(v6, __ D, p3, z9); // fmaxv d6, p3, z9.d ++ __ sve_fadda(v10, __ S, p5, z3); // fadda s10, p5, s10, z3.s ++ __ sve_uaddv(v21, __ B, p6, z8); // uaddv d21, p6, z8.b __ bind(forth); -@@ -762,567 +762,567 @@ aarch64ops.o: file format elf64-littleaarch64 +@@ -762,680 +846,780 @@ aarch64ops.o: file format elf64-littleaarch64 Disassembly of section .text: 0000000000000000 : -- 0: 8b50798f add x15, x12, x16, lsr #30 -- 4: cb4381e1 sub x1, x15, x3, lsr #32 -- 8: ab05372d adds x13, x25, x5, lsl #13 -- c: eb864796 subs x22, x28, x6, asr #17 -- 10: 0b961920 add w0, w9, w22, asr #6 -- 14: 4b195473 sub w19, w3, w25, lsl #21 -- 18: 2b0b5264 adds w4, w19, w11, lsl #20 -- 1c: 6b9300f8 subs w24, w7, w19, asr #0 -- 20: 8a0bc0fe and x30, x7, x11, lsl #48 -- 24: aa0f3118 orr x24, x8, x15, lsl #12 -- 28: ca170531 eor x17, x9, x23, lsl #1 -- 2c: ea44dd6e ands x14, x11, x4, lsr #55 -- 30: 0a4c44f3 and w19, w7, w12, lsr #17 -- 34: 2a8b7373 orr w19, w27, w11, asr #28 -- 38: 4a567c7e eor w30, w3, w22, lsr #31 -- 3c: 6a9c0353 ands w19, w26, w28, asr #0 -- 40: 8a3accdd bic x29, x6, x26, lsl #51 -- 44: aa318f7a orn x26, x27, x17, lsl #35 -- 48: ca2e1495 eon x21, x4, x14, lsl #5 -- 4c: eaa015e2 bics x2, x15, x0, asr #5 -- 50: 0a2274e2 bic w2, w7, w2, lsl #29 -- 54: 2a751598 orn w24, w12, w21, lsr #5 -- 58: 4a3309fe eon w30, w15, w19, lsl #2 -- 5c: 6ab172fe bics w30, w23, w17, asr #28 -- 60: 110a5284 add w4, w20, #0x294 -- 64: 310b1942 adds w2, w10, #0x2c6 -- 68: 5103d353 sub w19, w26, #0xf4 -- 6c: 710125bc subs w28, w13, #0x49 -- 70: 910d7bc2 add x2, x30, #0x35e -- 74: b108fa1b adds x27, x16, #0x23e -- 78: d1093536 sub x22, x9, #0x24d -- 7c: f10ae824 subs x4, x1, #0x2ba -- 80: 120e667c and w28, w19, #0xfffc0fff -- 84: 321f6cbb orr w27, w5, #0x1ffffffe -- 88: 520f6a9e eor w30, w20, #0xfffe0fff -- 8c: 72136f56 ands w22, w26, #0xffffe1ff -- 90: 927e4ce5 and x5, x7, #0x3ffffc -- 94: b278b4ed orr x13, x7, #0x3fffffffffff00 -- 98: d24c6527 eor x7, x9, #0xfff0000000003fff -- 9c: f2485803 ands x3, x0, #0xff00000000007fff -- a0: 14000000 b a0 -- a4: 17ffffd7 b 0 -- a8: 140001ee b 860 -- ac: 94000000 bl ac -- b0: 97ffffd4 bl 0 -- b4: 940001eb bl 860 -- b8: 34000010 cbz w16, b8 -- bc: 34fffa30 cbz w16, 0 -- c0: 34003d10 cbz w16, 860 -- c4: 35000013 cbnz w19, c4 -- c8: 35fff9d3 cbnz w19, 0 -- cc: 35003cb3 cbnz w19, 860 -- d0: b4000005 cbz x5, d0 -- d4: b4fff965 cbz x5, 0 -- d8: b4003c45 cbz x5, 860 -- dc: b5000004 cbnz x4, dc -- e0: b5fff904 cbnz x4, 0 -- e4: b5003be4 cbnz x4, 860 -- e8: 1000001b adr x27, e8 -- ec: 10fff8bb adr x27, 0 -- f0: 10003b9b adr x27, 860 -- f4: 90000010 adrp x16, 0 -- f8: 3640001c tbz w28, #8, f8 -- fc: 3647f83c tbz w28, #8, 0 -- 100: 36403b1c tbz w28, #8, 860 -- 104: 37080001 tbnz w1, #1, 104 -- 108: 370ff7c1 tbnz w1, #1, 0 -- 10c: 37083aa1 tbnz w1, #1, 860 -- 110: 12a437f4 mov w20, #0xde40ffff // #-566165505 -- 114: 528c9d67 mov w7, #0x64eb // #25835 -- 118: 72838bb1 movk w17, #0x1c5d -- 11c: 92c1062e mov x14, #0xfffff7ceffffffff // #-9006546419713 -- 120: d287da49 mov x9, #0x3ed2 // #16082 -- 124: f2a6d153 movk x19, #0x368a, lsl #16 -- 128: 93465ac9 sbfx x9, x22, #6, #17 -- 12c: 330b0013 bfi w19, w0, #21, #1 -- 130: 530b4e6a ubfx w10, w19, #11, #9 -- 134: 934545e4 sbfx x4, x15, #5, #13 -- 138: b35370a3 bfxil x3, x5, #19, #10 -- 13c: d3510b8c ubfiz x12, x28, #47, #3 -- 140: 13960c0f extr w15, w0, w22, #3 -- 144: 93ceddc6 ror x6, x14, #55 -- 148: 54000000 b.eq 148 // b.none -- 14c: 54fff5a0 b.eq 0 // b.none -- 150: 54003880 b.eq 860 // b.none -- 154: 54000001 b.ne 154 // b.any -- 158: 54fff541 b.ne 0 // b.any -- 15c: 54003821 b.ne 860 // b.any -- 160: 54000002 b.cs 160 // b.hs, b.nlast -- 164: 54fff4e2 b.cs 0 // b.hs, b.nlast -- 168: 540037c2 b.cs 860 // b.hs, b.nlast -- 16c: 54000002 b.cs 16c // b.hs, b.nlast -- 170: 54fff482 b.cs 0 // b.hs, b.nlast -- 174: 54003762 b.cs 860 // b.hs, b.nlast -- 178: 54000003 b.cc 178 // b.lo, b.ul, b.last -- 17c: 54fff423 b.cc 0 // b.lo, b.ul, b.last -- 180: 54003703 b.cc 860 // b.lo, b.ul, b.last -- 184: 54000003 b.cc 184 // b.lo, b.ul, b.last -- 188: 54fff3c3 b.cc 0 // b.lo, b.ul, b.last -- 18c: 540036a3 b.cc 860 // b.lo, b.ul, b.last -- 190: 54000004 b.mi 190 // b.first -- 194: 54fff364 b.mi 0 // b.first -- 198: 54003644 b.mi 860 // b.first -- 19c: 54000005 b.pl 19c // b.nfrst -- 1a0: 54fff305 b.pl 0 // b.nfrst -- 1a4: 540035e5 b.pl 860 // b.nfrst -- 1a8: 54000006 b.vs 1a8 -- 1ac: 54fff2a6 b.vs 0 -- 1b0: 54003586 b.vs 860 -- 1b4: 54000007 b.vc 1b4 -- 1b8: 54fff247 b.vc 0 -- 1bc: 54003527 b.vc 860 -- 1c0: 54000008 b.hi 1c0 // b.pmore -- 1c4: 54fff1e8 b.hi 0 // b.pmore -- 1c8: 540034c8 b.hi 860 // b.pmore -- 1cc: 54000009 b.ls 1cc // b.plast -- 1d0: 54fff189 b.ls 0 // b.plast -- 1d4: 54003469 b.ls 860 // b.plast -- 1d8: 5400000a b.ge 1d8 // b.tcont -- 1dc: 54fff12a b.ge 0 // b.tcont -- 1e0: 5400340a b.ge 860 // b.tcont -- 1e4: 5400000b b.lt 1e4 // b.tstop -- 1e8: 54fff0cb b.lt 0 // b.tstop -- 1ec: 540033ab b.lt 860 // b.tstop -- 1f0: 5400000c b.gt 1f0 -- 1f4: 54fff06c b.gt 0 -- 1f8: 5400334c b.gt 860 -- 1fc: 5400000d b.le 1fc -- 200: 54fff00d b.le 0 -- 204: 540032ed b.le 860 -- 208: 5400000e b.al 208 -- 20c: 54ffefae b.al 0 -- 210: 5400328e b.al 860 -- 214: 5400000f b.nv 214 -- 218: 54ffef4f b.nv 0 -- 21c: 5400322f b.nv 860 -- 220: d40ac601 svc #0x5630 -- 224: d40042a2 hvc #0x215 -- 228: d404dac3 smc #0x26d6 -- 22c: d4224d40 brk #0x126a -- 230: d44219c0 hlt #0x10ce -- 234: d503201f nop -- 238: d69f03e0 eret -- 23c: d6bf03e0 drps -- 240: d5033fdf isb -- 244: d503339f dsb osh -- 248: d50335bf dmb nshld -- 24c: d61f0280 br x20 -- 250: d63f0040 blr x2 -- 254: c8127c17 stxr w18, x23, [x0] -- 258: c81efec5 stlxr w30, x5, [x22] -- 25c: c85f7d05 ldxr x5, [x8] -- 260: c85ffe14 ldaxr x20, [x16] -- 264: c89ffd66 stlr x6, [x11] -- 268: c8dfff66 ldar x6, [x27] -- 26c: 880a7cb1 stxr w10, w17, [x5] -- 270: 8816fd89 stlxr w22, w9, [x12] -- 274: 885f7d1b ldxr w27, [x8] -- 278: 885ffc57 ldaxr w23, [x2] -- 27c: 889fffba stlr w26, [x29] -- 280: 88dffd4d ldar w13, [x10] -- 284: 48197f7c stxrh w25, w28, [x27] -- 288: 481dfd96 stlxrh w29, w22, [x12] -- 28c: 485f7f96 ldxrh w22, [x28] -- 290: 485fffc3 ldaxrh w3, [x30] -- 294: 489ffdf8 stlrh w24, [x15] -- 298: 48dfff5b ldarh w27, [x26] -- 29c: 080b7e6a stxrb w11, w10, [x19] -- 2a0: 0817fedb stlxrb w23, w27, [x22] -- 2a4: 085f7e18 ldxrb w24, [x16] -- 2a8: 085ffc38 ldaxrb w24, [x1] -- 2ac: 089fffa5 stlrb w5, [x29] -- 2b0: 08dffe18 ldarb w24, [x16] -- 2b4: c87f6239 ldxp x25, x24, [x17] -- 2b8: c87fb276 ldaxp x22, x12, [x19] -- 2bc: c820573a stxp w0, x26, x21, [x25] -- 2c0: c821aca6 stlxp w1, x6, x11, [x5] -- 2c4: 887f388d ldxp w13, w14, [x4] -- 2c8: 887f88d1 ldaxp w17, w2, [x6] -- 2cc: 882f2643 stxp w15, w3, w9, [x18] -- 2d0: 88329131 stlxp w18, w17, w4, [x9] -- 2d4: f81cf2b7 stur x23, [x21, #-49] -- 2d8: b803f055 stur w21, [x2, #63] -- 2dc: 39002f9b strb w27, [x28, #11] -- 2e0: 781f31fd sturh w29, [x15, #-13] -- 2e4: f85d33ce ldur x14, [x30, #-45] -- 2e8: b843539d ldur w29, [x28, #53] -- 2ec: 39401f54 ldrb w20, [x26, #7] -- 2f0: 785ce059 ldurh w25, [x2, #-50] -- 2f4: 389f1143 ldursb x3, [x10, #-15] -- 2f8: 788131ee ldursh x14, [x15, #19] -- 2fc: 78dfb17d ldursh w29, [x11, #-5] -- 300: b89b90af ldursw x15, [x5, #-71] -- 304: fc403193 ldur d19, [x12, #3] -- 308: bc42a36c ldur s12, [x27, #42] -- 30c: fc07d396 stur d22, [x28, #125] -- 310: bc1ec1f8 stur s24, [x15, #-20] -- 314: f81e8f88 str x8, [x28, #-24]! -- 318: b8025de6 str w6, [x15, #37]! -- 31c: 38007c27 strb w7, [x1, #7]! -- 320: 7801ee20 strh w0, [x17, #30]! -- 324: f8454fb9 ldr x25, [x29, #84]! -- 328: b85cce9a ldr w26, [x20, #-52]! -- 32c: 385e7fba ldrb w26, [x29, #-25]! -- 330: 7841af24 ldrh w4, [x25, #26]! -- 334: 389ebd1c ldrsb x28, [x8, #-21]! -- 338: 789fadd1 ldrsh x17, [x14, #-6]! -- 33c: 78c0aefc ldrsh w28, [x23, #10]! -- 340: b89c0f7e ldrsw x30, [x27, #-64]! -- 344: fc50efd4 ldr d20, [x30, #-242]! -- 348: bc414f71 ldr s17, [x27, #20]! -- 34c: fc011c67 str d7, [x3, #17]! -- 350: bc1f0d6d str s13, [x11, #-16]! -- 354: f81c3526 str x6, [x9], #-61 -- 358: b81e34b0 str w16, [x5], #-29 -- 35c: 3800f7bd strb w29, [x29], #15 -- 360: 78012684 strh w4, [x20], #18 -- 364: f842e653 ldr x19, [x18], #46 -- 368: b8417456 ldr w22, [x2], #23 -- 36c: 385e2467 ldrb w7, [x3], #-30 -- 370: 785e358b ldrh w11, [x12], #-29 -- 374: 389e34c8 ldrsb x8, [x6], #-29 -- 378: 788046f8 ldrsh x24, [x23], #4 -- 37c: 78c00611 ldrsh w17, [x16], #0 -- 380: b89f8680 ldrsw x0, [x20], #-8 -- 384: fc582454 ldr d20, [x2], #-126 -- 388: bc5987d3 ldr s19, [x30], #-104 -- 38c: fc076624 str d4, [x17], #118 -- 390: bc190675 str s21, [x19], #-112 -- 394: f833785a str x26, [x2, x19, lsl #3] -- 398: b82fd809 str w9, [x0, w15, sxtw #2] -- 39c: 3821799a strb w26, [x12, x1, lsl #0] -- 3a0: 782a7975 strh w21, [x11, x10, lsl #1] -- 3a4: f870eaf0 ldr x16, [x23, x16, sxtx] -- 3a8: b871d96a ldr w10, [x11, w17, sxtw #2] -- 3ac: 386b7aed ldrb w13, [x23, x11, lsl #0] -- 3b0: 7875689b ldrh w27, [x4, x21] -- 3b4: 38afd91a ldrsb x26, [x8, w15, sxtw #0] -- 3b8: 78a2c955 ldrsh x21, [x10, w2, sxtw] -- 3bc: 78ee6bc8 ldrsh w8, [x30, x14] -- 3c0: b8b4f9dd ldrsw x29, [x14, x20, sxtx #2] -- 3c4: fc76eb7e ldr d30, [x27, x22, sxtx] -- 3c8: bc76692d ldr s13, [x9, x22] -- 3cc: fc31db28 str d8, [x25, w17, sxtw #3] -- 3d0: bc255b01 str s1, [x24, w5, uxtw #2] -- 3d4: f91c52aa str x10, [x21, #14496] -- 3d8: b91c3fb2 str w18, [x29, #7228] -- 3dc: 391f8877 strb w23, [x3, #2018] -- 3e0: 791ac97c strh w28, [x11, #3428] -- 3e4: f95c1758 ldr x24, [x26, #14376] -- 3e8: b95b3c55 ldr w21, [x2, #6972] -- 3ec: 395ce0a4 ldrb w4, [x5, #1848] -- 3f0: 795851ce ldrh w14, [x14, #3112] -- 3f4: 399e9f64 ldrsb x4, [x27, #1959] -- 3f8: 79993764 ldrsh x4, [x27, #3226] -- 3fc: 79d9af8a ldrsh w10, [x28, #3286] -- 400: b99eea2a ldrsw x10, [x17, #7912] -- 404: fd5a2f8d ldr d13, [x28, #13400] -- 408: bd5dac78 ldr s24, [x3, #7596] -- 40c: fd1e0182 str d2, [x12, #15360] -- 410: bd195c31 str s17, [x1, #6492] -- 414: 58000010 ldr x16, 414 -- 418: 1800000d ldr w13, 418 -- 41c: f8981240 prfum pldl1keep, [x18, #-127] -- 420: d8ffdf00 prfm pldl1keep, 0 -- 424: f8a27a80 prfm pldl1keep, [x20, x2, lsl #3] -- 428: f99af920 prfm pldl1keep, [x9, #13808] -- 42c: 1a0202e8 adc w8, w23, w2 -- 430: 3a130078 adcs w24, w3, w19 -- 434: 5a1d0316 sbc w22, w24, w29 -- 438: 7a03036c sbcs w12, w27, w3 -- 43c: 9a0102eb adc x11, x23, x1 -- 440: ba1700bd adcs x29, x5, x23 -- 444: da0c0329 sbc x9, x25, x12 -- 448: fa16000c sbcs x12, x0, x22 -- 44c: 0b23459a add w26, w12, w3, uxtw #1 -- 450: 2b328a14 adds w20, w16, w18, sxtb #2 -- 454: cb274bde sub x30, x30, w7, uxtw #2 -- 458: 6b222eab subs w11, w21, w2, uxth #3 -- 45c: 8b214b42 add x2, x26, w1, uxtw #2 -- 460: ab34a7b2 adds x18, x29, w20, sxth #1 -- 464: cb24520e sub x14, x16, w4, uxtw #4 -- 468: eb378e20 subs x0, x17, w23, sxtb #3 -- 46c: 3a565283 ccmn w20, w22, #0x3, pl // pl = nfrst -- 470: 7a420321 ccmp w25, w2, #0x1, eq // eq = none -- 474: ba58c247 ccmn x18, x24, #0x7, gt -- 478: fa4d5106 ccmp x8, x13, #0x6, pl // pl = nfrst -- 47c: 3a426924 ccmn w9, #0x2, #0x4, vs -- 480: 7a5b0847 ccmp w2, #0x1b, #0x7, eq // eq = none -- 484: ba413a02 ccmn x16, #0x1, #0x2, cc // cc = lo, ul, last -- 488: fa5fba23 ccmp x17, #0x1f, #0x3, lt // lt = tstop -- 48c: 1a979377 csel w23, w27, w23, ls // ls = plast -- 490: 1a86640a csinc w10, w0, w6, vs -- 494: 5a89300b csinv w11, w0, w9, cc // cc = lo, ul, last -- 498: 5a923771 csneg w17, w27, w18, cc // cc = lo, ul, last -- 49c: 9a8b720c csel x12, x16, x11, vc -- 4a0: 9a868786 csinc x6, x28, x6, hi // hi = pmore -- 4a4: da9a736d csinv x13, x27, x26, vc -- 4a8: da9256dd csneg x29, x22, x18, pl // pl = nfrst -- 4ac: 5ac0026c rbit w12, w19 -- 4b0: 5ac00657 rev16 w23, w18 -- 4b4: 5ac00b89 rev w9, w28 -- 4b8: 5ac01262 clz w2, w19 -- 4bc: 5ac017b9 cls w25, w29 -- 4c0: dac002e4 rbit x4, x23 -- 4c4: dac0065d rev16 x29, x18 -- 4c8: dac00907 rev32 x7, x8 -- 4cc: dac00e2d rev x13, x17 -- 4d0: dac01011 clz x17, x0 -- 4d4: dac01752 cls x18, x26 -- 4d8: 1ad0098b udiv w11, w12, w16 -- 4dc: 1ac70d24 sdiv w4, w9, w7 -- 4e0: 1ad020ec lsl w12, w7, w16 -- 4e4: 1ad72613 lsr w19, w16, w23 -- 4e8: 1ac62887 asr w7, w4, w6 -- 4ec: 1ad72e95 ror w21, w20, w23 -- 4f0: 9adc0990 udiv x16, x12, x28 -- 4f4: 9acd0d84 sdiv x4, x12, x13 -- 4f8: 9ac721a9 lsl x9, x13, x7 -- 4fc: 9acf277c lsr x28, x27, x15 -- 500: 9ace2bd4 asr x20, x30, x14 -- 504: 9ade2e4e ror x14, x18, x30 -- 508: 9bc77d63 umulh x3, x11, x7 -- 50c: 9b587e97 smulh x23, x20, x24 -- 510: 1b1524a2 madd w2, w5, w21, w9 -- 514: 1b04a318 msub w24, w24, w4, w8 -- 518: 9b0f4d8b madd x11, x12, x15, x19 -- 51c: 9b0ce73d msub x29, x25, x12, x25 -- 520: 9b2c5971 smaddl x17, w11, w12, x22 -- 524: 9b34c87c smsubl x28, w3, w20, x18 -- 528: 9bbc6887 umaddl x7, w4, w28, x26 -- 52c: 9bb19556 umsubl x22, w10, w17, x5 -- 530: 1e310871 fmul s17, s3, s17 -- 534: 1e261a2b fdiv s11, s17, s6 -- 538: 1e2928fd fadd s29, s7, s9 -- 53c: 1e333987 fsub s7, s12, s19 -- 540: 1e230ae0 fmul s0, s23, s3 -- 544: 1e75087a fmul d26, d3, d21 -- 548: 1e651a60 fdiv d0, d19, d5 -- 54c: 1e692b40 fadd d0, d26, d9 -- 550: 1e753ab9 fsub d25, d21, d21 -- 554: 1e7309b0 fmul d16, d13, d19 -- 558: 1f00425d fmadd s29, s18, s0, s16 -- 55c: 1f1d95b7 fmsub s23, s13, s29, s5 -- 560: 1f2a38e9 fnmadd s9, s7, s10, s14 -- 564: 1f2f5f99 fnmadd s25, s28, s15, s23 -- 568: 1f5545a6 fmadd d6, d13, d21, d17 -- 56c: 1f429ea3 fmsub d3, d21, d2, d7 -- 570: 1f65472a fnmadd d10, d25, d5, d17 -- 574: 1f7449ce fnmadd d14, d14, d20, d18 -- 578: 1e20404f fmov s15, s2 -- 57c: 1e20c0f2 fabs s18, s7 -- 580: 1e2140c3 fneg s3, s6 -- 584: 1e21c02c fsqrt s12, s1 -- 588: 1e22c009 fcvt d9, s0 -- 58c: 1e6040a4 fmov d4, d5 -- 590: 1e60c1e3 fabs d3, d15 -- 594: 1e614331 fneg d17, d25 -- 598: 1e61c30c fsqrt d12, d24 -- 59c: 1e6240b5 fcvt s21, d5 -- 5a0: 1e3802a4 fcvtzs w4, s21 -- 5a4: 9e38007b fcvtzs x27, s3 -- 5a8: 1e78011d fcvtzs w29, d8 -- 5ac: 9e7802a9 fcvtzs x9, d21 -- 5b0: 1e2203b4 scvtf s20, w29 -- 5b4: 9e220107 scvtf s7, x8 -- 5b8: 1e6202ac scvtf d12, w21 -- 5bc: 9e6202b0 scvtf d16, x21 -- 5c0: 1e2600b2 fmov w18, s5 -- 5c4: 9e660119 fmov x25, d8 -- 5c8: 1e270352 fmov s18, w26 -- 5cc: 9e670160 fmov d0, x11 -- 5d0: 1e262200 fcmp s16, s6 -- 5d4: 1e7d2200 fcmp d16, d29 -- 5d8: 1e2023c8 fcmp s30, #0.0 -- 5dc: 1e602128 fcmp d9, #0.0 -- 5e0: 293e119b stp w27, w4, [x12, #-16] -- 5e4: 294a2543 ldp w3, w9, [x10, #80] -- 5e8: 69480c70 ldpsw x16, x3, [x3, #64] -- 5ec: a934726a stp x10, x28, [x19, #-192] -- 5f0: a97448f3 ldp x19, x18, [x7, #-192] -- 5f4: 298243ca stp w10, w16, [x30, #16]! -- 5f8: 29e21242 ldp w2, w4, [x18, #-240]! -- 5fc: 69c64db8 ldpsw x24, x19, [x13, #48]! -- 600: a9800311 stp x17, x0, [x24, #0]! -- 604: a9f4686e ldp x14, x26, [x3, #-192]! -- 608: 288a0416 stp w22, w1, [x0], #80 -- 60c: 28fe2812 ldp w18, w10, [x0], #-16 -- 610: 68fe62d8 .inst 0x68fe62d8 ; undefined -- 614: a885308c stp x12, x12, [x4], #80 -- 618: a8f12664 ldp x4, x9, [x19], #-240 -- 61c: 282468d2 stnp w18, w26, [x6, #-224] -- 620: 284e5035 ldnp w21, w20, [x1, #112] -- 624: a8327699 stnp x25, x29, [x20, #-224] -- 628: a84716e1 ldnp x1, x5, [x23, #112] -- 62c: 0c407284 ld1 {v4.8b}, [x20] -- 630: 4cdfa158 ld1 {v24.16b, v25.16b}, [x10], #32 -- 634: 0ccf6cd8 ld1 {v24.1d-v26.1d}, [x6], x15 -- 638: 4cdf2483 ld1 {v3.8h-v6.8h}, [x4], #64 -- 63c: 0d40c0c2 ld1r {v2.8b}, [x6] -- 640: 4ddfc9cd ld1r {v13.4s}, [x14], #4 -- 644: 0dd8ceaf ld1r {v15.1d}, [x21], x24 -- 648: 4c408ea9 ld2 {v9.2d, v10.2d}, [x21] -- 64c: 0cdf86bd ld2 {v29.4h, v30.4h}, [x21], #16 -- 650: 4d60c1c8 ld2r {v8.16b, v9.16b}, [x14] -- 654: 0dffca87 ld2r {v7.2s, v8.2s}, [x20], #8 -- 658: 4de3cc7c ld2r {v28.2d, v29.2d}, [x3], x3 -- 65c: 4cdd497b ld3 {v27.4s-v29.4s}, [x11], x29 -- 660: 0c404950 ld3 {v16.2s-v18.2s}, [x10] -- 664: 4d40e595 ld3r {v21.8h-v23.8h}, [x12] -- 668: 4ddfeba4 ld3r {v4.4s-v6.4s}, [x29], #12 -- 66c: 0dd3ed38 ld3r {v24.1d-v26.1d}, [x9], x19 -- 670: 4cdf046a ld4 {v10.8h-v13.8h}, [x3], #64 -- 674: 0cc9039b ld4 {v27.8b-v30.8b}, [x28], x9 -- 678: 0d60e3d5 ld4r {v21.8b-v24.8b}, [x30] -- 67c: 0dffe5d7 ld4r {v23.4h-v26.4h}, [x14], #8 -- 680: 0df4e9a4 ld4r {v4.2s-v7.2s}, [x13], x20 -- 684: ba5fd3e3 ccmn xzr, xzr, #0x3, le -- 688: 3a5f03e5 ccmn wzr, wzr, #0x5, eq // eq = none -- 68c: fa411be4 ccmp xzr, #0x1, #0x4, ne // ne = any -- 690: 7a42cbe2 ccmp wzr, #0x2, #0x2, gt -- 694: 93df03ff ror xzr, xzr, #0 -- 698: c820ffff stlxp w0, xzr, xzr, [sp] -- 69c: 8822fc7f stlxp w2, wzr, wzr, [x3] -- 6a0: c8247cbf stxp w4, xzr, xzr, [x5] -- 6a4: 88267fff stxp w6, wzr, wzr, [sp] -- 6a8: 4e010fe0 dup v0.16b, wzr -- 6ac: 4e081fe1 mov v1.d[0], xzr -- 6b0: 4e0c1fe1 mov v1.s[1], wzr -- 6b4: 4e0a1fe1 mov v1.h[2], wzr -- 6b8: 4e071fe1 mov v1.b[3], wzr -- 6bc: 4cc0ac3f ld1 {v31.2d, v0.2d}, [x1], x0 -- 6c0: 1e601000 fmov d0, #2.000000000000000000e+00 -- 6c4: 1e603000 fmov d0, #2.125000000000000000e+00 -- 6c8: 1e621000 fmov d0, #4.000000000000000000e+00 -- 6cc: 1e623000 fmov d0, #4.250000000000000000e+00 -- 6d0: 1e641000 fmov d0, #8.000000000000000000e+00 -- 6d4: 1e643000 fmov d0, #8.500000000000000000e+00 -- 6d8: 1e661000 fmov d0, #1.600000000000000000e+01 -- 6dc: 1e663000 fmov d0, #1.700000000000000000e+01 -- 6e0: 1e681000 fmov d0, #1.250000000000000000e-01 -- 6e4: 1e683000 fmov d0, #1.328125000000000000e-01 -- 6e8: 1e6a1000 fmov d0, #2.500000000000000000e-01 -- 6ec: 1e6a3000 fmov d0, #2.656250000000000000e-01 -- 6f0: 1e6c1000 fmov d0, #5.000000000000000000e-01 -- 6f4: 1e6c3000 fmov d0, #5.312500000000000000e-01 -- 6f8: 1e6e1000 fmov d0, #1.000000000000000000e+00 -- 6fc: 1e6e3000 fmov d0, #1.062500000000000000e+00 -- 700: 1e701000 fmov d0, #-2.000000000000000000e+00 -- 704: 1e703000 fmov d0, #-2.125000000000000000e+00 -- 708: 1e721000 fmov d0, #-4.000000000000000000e+00 -- 70c: 1e723000 fmov d0, #-4.250000000000000000e+00 -- 710: 1e741000 fmov d0, #-8.000000000000000000e+00 -- 714: 1e743000 fmov d0, #-8.500000000000000000e+00 -- 718: 1e761000 fmov d0, #-1.600000000000000000e+01 -- 71c: 1e763000 fmov d0, #-1.700000000000000000e+01 -- 720: 1e781000 fmov d0, #-1.250000000000000000e-01 -- 724: 1e783000 fmov d0, #-1.328125000000000000e-01 -- 728: 1e7a1000 fmov d0, #-2.500000000000000000e-01 -- 72c: 1e7a3000 fmov d0, #-2.656250000000000000e-01 -- 730: 1e7c1000 fmov d0, #-5.000000000000000000e-01 -- 734: 1e7c3000 fmov d0, #-5.312500000000000000e-01 -- 738: 1e7e1000 fmov d0, #-1.000000000000000000e+00 -- 73c: 1e7e3000 fmov d0, #-1.062500000000000000e+00 -- 740: f8358305 swp x21, x5, [x24] -- 744: f82d01ed ldadd x13, x13, [x15] -- 748: f8361353 ldclr x22, x19, [x26] -- 74c: f839234a ldeor x25, x10, [x26] -- 750: f82531fb ldset x5, x27, [x15] -- 754: f8335165 ldsmin x19, x5, [x11] -- 758: f83a4080 ldsmax x26, x0, [x4] -- 75c: f83673d7 ldumin x22, x23, [x30] -- 760: f832611c ldumax x18, x28, [x8] -- 764: f8ad837d swpa x13, x29, [x27] -- 768: f8ab01a5 ldadda x11, x5, [x13] -- 76c: f8a112b8 ldclra x1, x24, [x21] -- 770: f8bb2311 ldeora x27, x17, [x24] -- 774: f8b230be ldseta x18, x30, [x5] -- 778: f8a75336 ldsmina x7, x22, [x25] -- 77c: f8a4427a ldsmaxa x4, x26, [x19] -- 780: f8a6707e ldumina x6, x30, [x3] -- 784: f8b860b7 ldumaxa x24, x23, [x5] -- 788: f8f88392 swpal x24, x18, [x28] -- 78c: f8f300ff ldaddal x19, xzr, [x7] -- 790: f8ed1386 ldclral x13, x6, [x28] -- 794: f8e822af ldeoral x8, x15, [x21] -- 798: f8e2302d ldsetal x2, x13, [x1] -- 79c: f8f1533d ldsminal x17, x29, [x25] -- 7a0: f8f941d2 ldsmaxal x25, x18, [x14] -- 7a4: f8ff7366 lduminal xzr, x6, [x27] -- 7a8: f8f061e5 ldumaxal x16, x5, [x15] -- 7ac: f86b8072 swpl x11, x18, [x3] -- 7b0: f87a0054 ldaddl x26, x20, [x2] -- 7b4: f86b1164 ldclrl x11, x4, [x11] -- 7b8: f87e22f3 ldeorl x30, x19, [x23] -- 7bc: f86331cf ldsetl x3, x15, [x14] -- 7c0: f87e5296 ldsminl x30, x22, [x20] -- 7c4: f8674305 ldsmaxl x7, x5, [x24] -- 7c8: f87771f0 lduminl x23, x16, [x15] -- 7cc: f86b6013 ldumaxl x11, x19, [x0] -- 7d0: b83c803c swp w28, w28, [x1] -- 7d4: b82b0195 ldadd w11, w21, [x12] -- 7d8: b83d1240 ldclr w29, w0, [x18] -- 7dc: b8252320 ldeor w5, w0, [x25] -- 7e0: b82e3340 ldset w14, w0, [x26] -- 7e4: b83c53b2 ldsmin w28, w18, [x29] -- 7e8: b82f43a1 ldsmax w15, w1, [x29] -- 7ec: b828739a ldumin w8, w26, [x28] -- 7f0: b831608e ldumax w17, w14, [x4] -- 7f4: b8b88039 swpa w24, w25, [x1] -- 7f8: b8aa0231 ldadda w10, w17, [x17] -- 7fc: b8bd12b4 ldclra w29, w20, [x21] -- 800: b8bd2189 ldeora w29, w9, [x12] -- 804: b8ab30a6 ldseta w11, w6, [x5] -- 808: b8b552a7 ldsmina w21, w7, [x21] -- 80c: b8aa4197 ldsmaxa w10, w23, [x12] -- 810: b8b57145 ldumina w21, w5, [x10] -- 814: b8be6254 ldumaxa w30, w20, [x18] -- 818: b8ed80b7 swpal w13, w23, [x5] -- 81c: b8ef00b8 ldaddal w15, w24, [x5] -- 820: b8e9132a ldclral w9, w10, [x25] -- 824: b8f42231 ldeoral w20, w17, [x17] -- 828: b8ec33d2 ldsetal w12, w18, [x30] -- 82c: b8e35323 ldsminal w3, w3, [x25] -- 830: b8fa4159 ldsmaxal w26, w25, [x10] -- 834: b8e273eb lduminal w2, w11, [sp] -- 838: b8e760a2 ldumaxal w7, w2, [x5] -- 83c: b8608287 swpl w0, w7, [x20] -- 840: b865005f staddl w5, [x2] -- 844: b87b1379 ldclrl w27, w25, [x27] -- 848: b87e2358 ldeorl w30, w24, [x26] -- 84c: b86f32c2 ldsetl w15, w2, [x22] -- 850: b86053e3 ldsminl w0, w3, [sp] -- 854: b86f4154 ldsmaxl w15, w20, [x10] -- 858: b87671d5 lduminl w22, w21, [x14] -- 85c: b866605e ldumaxl w6, w30, [x2] -+ 0: 8b4db437 add x23, x1, x13, lsr #45 -+ 4: cb8ce3c8 sub x8, x30, x12, asr #56 -+ 8: ab0edafb adds x27, x23, x14, lsl #54 -+ c: eb5499f5 subs x21, x15, x20, lsr #38 -+ 10: 0b040e39 add w25, w17, w4, lsl #3 -+ 14: 4b89503d sub w29, w1, w9, asr #20 -+ 18: 2b89274a adds w10, w26, w9, asr #9 -+ 1c: 6b870fd5 subs w21, w30, w7, asr #3 -+ 20: 8a4b1109 and x9, x8, x11, lsr #4 -+ 24: aa810643 orr x3, x18, x1, asr #1 -+ 28: ca026e8a eor x10, x20, x2, lsl #27 -+ 2c: ea8b7d2c ands x12, x9, x11, asr #31 -+ 30: 0a9e6934 and w20, w9, w30, asr #26 -+ 34: 2a9a4555 orr w21, w10, w26, asr #17 -+ 38: 4a871d00 eor w0, w8, w7, asr #7 -+ 3c: 6a084973 ands w19, w11, w8, lsl #18 -+ 40: 8a23d497 bic x23, x4, x3, lsl #53 -+ 44: aa3360c9 orn x9, x6, x19, lsl #24 -+ 48: ca7ad8cc eon x12, x6, x26, lsr #54 -+ 4c: ea2c3a76 bics x22, x19, x12, lsl #14 -+ 50: 0a362dbd bic w29, w13, w22, lsl #11 -+ 54: 2ab417d1 orn w17, w30, w20, asr #5 -+ 58: 4a2b23a1 eon w1, w29, w11, lsl #8 -+ 5c: 6a667684 bics w4, w20, w6, lsr #29 -+ 60: 1107e0de add w30, w6, #0x1f8 -+ 64: 310ebd13 adds w19, w8, #0x3af -+ 68: 5105b55d sub w29, w10, #0x16d -+ 6c: 71047104 subs w4, w8, #0x11c -+ 70: 910ef9c3 add x3, x14, #0x3be -+ 74: b1029e96 adds x22, x20, #0xa7 -+ 78: d10b55fb sub x27, x15, #0x2d5 -+ 7c: f10ecf98 subs x24, x28, #0x3b3 -+ 80: 12099f39 and w25, w25, #0x7f807f80 -+ 84: 321b3f4d orr w13, w26, #0x1fffe0 -+ 88: 520309b5 eor w21, w13, #0xe0000000 -+ 8c: 72134062 ands w2, w3, #0x3fffe000 -+ 90: 92004548 and x8, x10, #0x3ffff0003ffff -+ 94: b24d861b orr x27, x16, #0xfff80000001fffff -+ 98: d219587b eor x27, x3, #0x3fffff803fffff80 -+ 9c: f25eaee4 ands x4, x23, #0xfffffffc00003fff +- 0: 8b18ec0f add x15, x0, x24, lsl #59 +- 4: cb9636d1 sub x17, x22, x22, asr #13 +- 8: ab1ce74a adds x10, x26, x28, lsl #57 +- c: eb184a19 subs x25, x16, x24, lsl #18 +- 10: 0b1c1ca8 add w8, w5, w28, lsl #7 +- 14: 4b817388 sub w8, w28, w1, asr #28 +- 18: 2b01004c adds w12, w2, w1 +- 1c: 6b5164b7 subs w23, w5, w17, lsr #25 +- 20: 8a0d5595 and x21, x12, x13, lsl #21 +- 24: aa9791f5 orr x21, x15, x23, asr #36 +- 28: ca9bc316 eor x22, x24, x27, asr #48 +- 2c: ea82d1f6 ands x22, x15, x2, asr #52 +- 30: 0a980e21 and w1, w17, w24, asr #3 +- 34: 2a862c45 orr w5, w2, w6, asr #11 +- 38: 4a453037 eor w23, w1, w5, lsr #12 +- 3c: 6a8e5180 ands w0, w12, w14, asr #20 +- 40: 8a621cc1 bic x1, x6, x2, lsr #7 +- 44: aa24bd1e orn x30, x8, x4, lsl #47 +- 48: cab4d6d1 eon x17, x22, x20, asr #53 +- 4c: eaa591fd bics x29, x15, x5, asr #36 +- 50: 0a7d6efe bic w30, w23, w29, lsr #27 +- 54: 2a2253ac orn w12, w29, w2, lsl #20 +- 58: 4aa61187 eon w7, w12, w6, asr #4 +- 5c: 6aa755b0 bics w16, w13, w7, asr #21 +- 60: 110b5a25 add w5, w17, #0x2d6 +- 64: 31056e0a adds w10, w16, #0x15b +- 68: 510f48ba sub w26, w5, #0x3d2 +- 6c: 710ac715 subs w21, w24, #0x2b1 +- 70: 910f6e0a add x10, x16, #0x3db +- 74: b10a65ef adds x15, x15, #0x299 +- 78: d1009e98 sub x24, x20, #0x27 +- 7c: f10131aa subs x10, x13, #0x4c +- 80: 121d4e67 and w7, w19, #0x7ffff8 +- 84: 32043e25 orr w5, w17, #0xf0000fff +- 88: 52132390 eor w16, w28, #0x3fe000 +- 8c: 72160b0e ands w14, w24, #0x1c00 +- 90: 9273e76e and x14, x27, #0xffffffffffffe07f +- 94: b256416c orr x12, x11, #0x7fffc0000000000 +- 98: d24b5002 eor x2, x0, #0xffe00000000003ff +- 9c: f266da8d ands x13, x20, #0xfffffffffc01ffff +- a0: 14000000 b a0 +- a4: 17ffffd7 b 0 +- a8: 140001ee b 860 +- ac: 94000000 bl ac +- b0: 97ffffd4 bl 0 +- b4: 940001eb bl 860 +- b8: 3400000f cbz w15, b8 +- bc: 34fffa2f cbz w15, 0 +- c0: 34003d0f cbz w15, 860 +- c4: 3500001c cbnz w28, c4 +- c8: 35fff9dc cbnz w28, 0 +- cc: 35003cbc cbnz w28, 860 +- d0: b400001b cbz x27, d0 +- d4: b4fff97b cbz x27, 0 +- d8: b4003c5b cbz x27, 860 +- dc: b5000000 cbnz x0, dc +- e0: b5fff900 cbnz x0, 0 +- e4: b5003be0 cbnz x0, 860 +- e8: 1000000d adr x13, e8 +- ec: 10fff8ad adr x13, 0 +- f0: 10003b8d adr x13, 860 +- f4: 90000003 adrp x3, 0 +- f8: 36380015 tbz w21, #7, f8 +- fc: 363ff835 tbz w21, #7, 0 +- 100: 36383b15 tbz w21, #7, 860 +- 104: 3748000f tbnz w15, #9, 104 +- 108: 374ff7cf tbnz w15, #9, 0 +- 10c: 37483aaf tbnz w15, #9, 860 +- 110: 12a14bee mov w14, #0xf5a0ffff // #-173998081 +- 114: 5283bb51 mov w17, #0x1dda // #7642 +- 118: 72858ebb movk w27, #0x2c75 +- 11c: 92c98881 mov x1, #0xffffb3bbffffffff // #-83854941487105 +- 120: d2aa50d4 mov x20, #0x52860000 // #1384513536 +- 124: f2afd9d4 movk x20, #0x7ece, lsl #16 +- 128: 935c504d sbfiz x13, x2, #36, #21 +- 12c: 33133e90 bfi w16, w20, #13, #16 +- 130: 5309196b ubfiz w11, w11, #23, #7 +- 134: 93595482 sbfiz x2, x4, #39, #22 +- 138: b3424e0d bfxil x13, x16, #2, #18 +- 13c: d3481728 ubfiz x8, x25, #56, #6 +- 140: 138a3b7d extr w29, w27, w10, #14 +- 144: 93c66286 extr x6, x20, x6, #24 +- 148: 54000000 b.eq 148 // b.none +- 14c: 54fff5a0 b.eq 0 // b.none +- 150: 54003880 b.eq 860 // b.none +- 154: 54000001 b.ne 154 // b.any +- 158: 54fff541 b.ne 0 // b.any +- 15c: 54003821 b.ne 860 // b.any +- 160: 54000002 b.cs 160 // b.hs, b.nlast +- 164: 54fff4e2 b.cs 0 // b.hs, b.nlast +- 168: 540037c2 b.cs 860 // b.hs, b.nlast +- 16c: 54000002 b.cs 16c // b.hs, b.nlast +- 170: 54fff482 b.cs 0 // b.hs, b.nlast +- 174: 54003762 b.cs 860 // b.hs, b.nlast +- 178: 54000003 b.cc 178 // b.lo, b.ul, b.last +- 17c: 54fff423 b.cc 0 // b.lo, b.ul, b.last +- 180: 54003703 b.cc 860 // b.lo, b.ul, b.last +- 184: 54000003 b.cc 184 // b.lo, b.ul, b.last +- 188: 54fff3c3 b.cc 0 // b.lo, b.ul, b.last +- 18c: 540036a3 b.cc 860 // b.lo, b.ul, b.last +- 190: 54000004 b.mi 190 // b.first +- 194: 54fff364 b.mi 0 // b.first +- 198: 54003644 b.mi 860 // b.first +- 19c: 54000005 b.pl 19c // b.nfrst +- 1a0: 54fff305 b.pl 0 // b.nfrst +- 1a4: 540035e5 b.pl 860 // b.nfrst +- 1a8: 54000006 b.vs 1a8 +- 1ac: 54fff2a6 b.vs 0 +- 1b0: 54003586 b.vs 860 +- 1b4: 54000007 b.vc 1b4 +- 1b8: 54fff247 b.vc 0 +- 1bc: 54003527 b.vc 860 +- 1c0: 54000008 b.hi 1c0 // b.pmore +- 1c4: 54fff1e8 b.hi 0 // b.pmore +- 1c8: 540034c8 b.hi 860 // b.pmore +- 1cc: 54000009 b.ls 1cc // b.plast +- 1d0: 54fff189 b.ls 0 // b.plast +- 1d4: 54003469 b.ls 860 // b.plast +- 1d8: 5400000a b.ge 1d8 // b.tcont +- 1dc: 54fff12a b.ge 0 // b.tcont +- 1e0: 5400340a b.ge 860 // b.tcont +- 1e4: 5400000b b.lt 1e4 // b.tstop +- 1e8: 54fff0cb b.lt 0 // b.tstop +- 1ec: 540033ab b.lt 860 // b.tstop +- 1f0: 5400000c b.gt 1f0 +- 1f4: 54fff06c b.gt 0 +- 1f8: 5400334c b.gt 860 +- 1fc: 5400000d b.le 1fc +- 200: 54fff00d b.le 0 +- 204: 540032ed b.le 860 +- 208: 5400000e b.al 208 +- 20c: 54ffefae b.al 0 +- 210: 5400328e b.al 860 +- 214: 5400000f b.nv 214 +- 218: 54ffef4f b.nv 0 +- 21c: 5400322f b.nv 860 +- 220: d40d2881 svc #0x6944 +- 224: d40ea5c2 hvc #0x752e +- 228: d40518a3 smc #0x28c5 +- 22c: d42eca40 brk #0x7652 +- 230: d44a2e60 hlt #0x5173 +- 234: d503201f nop +- 238: d69f03e0 eret +- 23c: d6bf03e0 drps +- 240: d5033fdf isb +- 244: d5033d9f dsb ld +- 248: d5033bbf dmb ish +- 24c: d61f0120 br x9 +- 250: d63f0120 blr x9 +- 254: c8027d7d stxr w2, x29, [x11] +- 258: c816ff85 stlxr w22, x5, [x28] +- 25c: c85f7e8e ldxr x14, [x20] +- 260: c85ffe7d ldaxr x29, [x19] +- 264: c89ffea6 stlr x6, [x21] +- 268: c8dffc73 ldar x19, [x3] +- 26c: 880c7f63 stxr w12, w3, [x27] +- 270: 8811fdfa stlxr w17, w26, [x15] +- 274: 885f7dcd ldxr w13, [x14] +- 278: 885fff4c ldaxr w12, [x26] +- 27c: 889ffe28 stlr w8, [x17] +- 280: 88dfffd5 ldar w21, [x30] +- 284: 48007d6f stxrh w0, w15, [x11] +- 288: 4811fc34 stlxrh w17, w20, [x1] +- 28c: 485f7d1d ldxrh w29, [x8] +- 290: 485ffd91 ldaxrh w17, [x12] +- 294: 489ffc8b stlrh w11, [x4] +- 298: 48dffc90 ldarh w16, [x4] +- 29c: 080e7c85 stxrb w14, w5, [x4] +- 2a0: 081bfe11 stlxrb w27, w17, [x16] +- 2a4: 085f7f66 ldxrb w6, [x27] +- 2a8: 085fff1b ldaxrb w27, [x24] +- 2ac: 089ffe8a stlrb w10, [x20] +- 2b0: 08dfff49 ldarb w9, [x26] +- 2b4: c87f7b85 ldxp x5, x30, [x28] +- 2b8: c87fa66a ldaxp x10, x9, [x19] +- 2bc: c82b5590 stxp w11, x16, x21, [x12] +- 2c0: c82adc94 stlxp w10, x20, x23, [x4] +- 2c4: 887f0416 ldxp w22, w1, [x0] +- 2c8: 887f8503 ldaxp w3, w1, [x8] +- 2cc: 88205fc9 stxp w0, w9, w23, [x30] +- 2d0: 8837c560 stlxp w23, w0, w17, [x11] +- 2d4: f81e1146 stur x6, [x10, #-31] +- 2d8: b81fb007 stur w7, [x0, #-5] +- 2dc: 381f3205 sturb w5, [x16, #-13] +- 2e0: 7801f27e sturh w30, [x19, #31] +- 2e4: f8477130 ldur x16, [x9, #119] +- 2e8: b843b208 ldur w8, [x16, #59] +- 2ec: 385f918a ldurb w10, [x12, #-7] +- 2f0: 785da12e ldurh w14, [x9, #-38] +- 2f4: 389f83d8 ldursb x24, [x30, #-8] +- 2f8: 78817087 ldursh x7, [x4, #23] +- 2fc: 78dd91d1 ldursh w17, [x14, #-39] +- 300: b89e136b ldursw x11, [x27, #-31] +- 304: fc4410ec ldur d12, [x7, #65] +- 308: bc5fe200 ldur s0, [x16, #-2] +- 30c: fc15f2ed stur d13, [x23, #-161] +- 310: bc1c2075 stur s21, [x3, #-62] +- 314: f8064ca2 str x2, [x5, #100]! +- 318: b81a4c29 str w9, [x1, #-92]! +- 31c: 381fbfdb strb w27, [x30, #-5]! +- 320: 7800cdfb strh w27, [x15, #12]! +- 324: f852ce24 ldr x4, [x17, #-212]! +- 328: b841eef5 ldr w21, [x23, #30]! +- 32c: 385f9e2d ldrb w13, [x17, #-7]! +- 330: 785cec19 ldrh w25, [x0, #-50]! +- 334: 389ebea1 ldrsb x1, [x21, #-21]! +- 338: 789caebc ldrsh x28, [x21, #-54]! +- 33c: 78c02c8b ldrsh w11, [x4, #2]! +- 340: b883dd31 ldrsw x17, [x9, #61]! +- 344: fc427e7d ldr d29, [x19, #39]! +- 348: bc5abed6 ldr s22, [x22, #-85]! +- 34c: fc11ff29 str d9, [x25, #-225]! +- 350: bc1f1c49 str s9, [x2, #-15]! +- 354: f81be6ed str x13, [x23], #-66 +- 358: b800a611 str w17, [x16], #10 +- 35c: 381e05c1 strb w1, [x14], #-32 +- 360: 78006411 strh w17, [x0], #6 +- 364: f855473b ldr x27, [x25], #-172 +- 368: b85da72d ldr w13, [x25], #-38 +- 36c: 385e372b ldrb w11, [x25], #-29 +- 370: 784144be ldrh w30, [x5], #20 +- 374: 389f94e9 ldrsb x9, [x7], #-7 +- 378: 789c2460 ldrsh x0, [x3], #-62 +- 37c: 78c1f5c7 ldrsh w7, [x14], #31 +- 380: b8827771 ldrsw x17, [x27], #39 +- 384: fc515491 ldr d17, [x4], #-235 +- 388: bc4226ba ldr s26, [x21], #34 +- 38c: fc1c7625 str d5, [x17], #-57 +- 390: bc1935ad str s13, [x13], #-109 +- 394: f824da06 str x6, [x16, w4, sxtw #3] +- 398: b834db09 str w9, [x24, w20, sxtw #2] +- 39c: 38237ba3 strb w3, [x29, x3, lsl #0] +- 3a0: 783e6a2a strh w10, [x17, x30] +- 3a4: f867497b ldr x27, [x11, w7, uxtw] +- 3a8: b87949ee ldr w14, [x15, w25, uxtw] +- 3ac: 387379d8 ldrb w24, [x14, x19, lsl #0] +- 3b0: 7866c810 ldrh w16, [x0, w6, sxtw] +- 3b4: 38acd98a ldrsb x10, [x12, w12, sxtw #0] +- 3b8: 78b0499a ldrsh x26, [x12, w16, uxtw] +- 3bc: 78ee781a ldrsh w26, [x0, x14, lsl #1] +- 3c0: b8bbf971 ldrsw x17, [x11, x27, sxtx #2] +- 3c4: fc73d803 ldr d3, [x0, w19, sxtw #3] +- 3c8: bc6979fa ldr s26, [x15, x9, lsl #2] +- 3cc: fc30e9ab str d11, [x13, x16, sxtx] +- 3d0: bc355a7a str s26, [x19, w21, uxtw #2] +- 3d4: f91886a8 str x8, [x21, #12552] +- 3d8: b918ef6a str w10, [x27, #6380] +- 3dc: 391b15db strb w27, [x14, #1733] +- 3e0: 791ac0f0 strh w16, [x7, #3424] +- 3e4: f958753b ldr x27, [x9, #12520] +- 3e8: b95a1958 ldr w24, [x10, #6680] +- 3ec: 395b3f18 ldrb w24, [x24, #1743] +- 3f0: 795800b4 ldrh w20, [x5, #3072] +- 3f4: 39988891 ldrsb x17, [x4, #1570] +- 3f8: 799a81ae ldrsh x14, [x13, #3392] +- 3fc: 79dd172a ldrsh w10, [x25, #3722] +- 400: b9981342 ldrsw x2, [x26, #6160] +- 404: fd5d21da ldr d26, [x14, #14912] +- 408: bd5e7c9c ldr s28, [x4, #7804] +- 40c: fd1b526e str d14, [x19, #13984] +- 410: bd18df97 str s23, [x28, #6364] +- 414: 58002268 ldr x8, 860 +- 418: 18ffdf51 ldr w17, 0 +- 41c: f8951080 prfum pldl1keep, [x4, #-175] +- 420: d8000000 prfm pldl1keep, 420 +- 424: f8a4c900 prfm pldl1keep, [x8, w4, sxtw] +- 428: f999e180 prfm pldl1keep, [x12, #13248] +- 42c: 1a150374 adc w20, w27, w21 +- 430: 3a060227 adcs w7, w17, w6 +- 434: 5a1900c5 sbc w5, w6, w25 +- 438: 7a0e017e sbcs w30, w11, w14 +- 43c: 9a0b0223 adc x3, x17, x11 +- 440: ba110159 adcs x25, x10, x17 +- 444: da170207 sbc x7, x16, x23 +- 448: fa050144 sbcs x4, x10, x5 +- 44c: 0b2973c9 add w9, w30, w9, uxtx #4 +- 450: 2b30a8a0 adds w0, w5, w16, sxth #2 +- 454: cb3b8baf sub x15, x29, w27, sxtb #2 +- 458: 6b21f12b subs w11, w9, w1, sxtx #4 +- 45c: 8b264f02 add x2, x24, w6, uxtw #3 +- 460: ab3a70d3 adds x19, x6, x26, uxtx #4 +- 464: cb39ef48 sub x8, x26, x25, sxtx #3 +- 468: eb29329a subs x26, x20, w9, uxth #4 +- 46c: 3a5a41a7 ccmn w13, w26, #0x7, mi // mi = first +- 470: 7a54310f ccmp w8, w20, #0xf, cc // cc = lo, ul, last +- 474: ba4302c8 ccmn x22, x3, #0x8, eq // eq = none +- 478: fa58a04a ccmp x2, x24, #0xa, ge // ge = tcont +- 47c: 3a50490d ccmn w8, #0x10, #0xd, mi // mi = first +- 480: 7a4c0a01 ccmp w16, #0xc, #0x1, eq // eq = none +- 484: ba5f79e3 ccmn x15, #0x1f, #0x3, vc +- 488: fa4c0aef ccmp x23, #0xc, #0xf, eq // eq = none +- 48c: 1a9a30ee csel w14, w7, w26, cc // cc = lo, ul, last +- 490: 1a9ed763 csinc w3, w27, w30, le +- 494: 5a9702ab csinv w11, w21, w23, eq // eq = none +- 498: 5a95c7da csneg w26, w30, w21, gt +- 49c: 9a8d835c csel x28, x26, x13, hi // hi = pmore +- 4a0: 9a909471 csinc x17, x3, x16, ls // ls = plast +- 4a4: da8380ab csinv x11, x5, x3, hi // hi = pmore +- 4a8: da93c461 csneg x1, x3, x19, gt +- 4ac: 5ac00120 rbit w0, w9 +- 4b0: 5ac005da rev16 w26, w14 +- 4b4: 5ac00a2d rev w13, w17 +- 4b8: 5ac0128b clz w11, w20 +- 4bc: 5ac0163c cls w28, w17 +- 4c0: dac0008d rbit x13, x4 +- 4c4: dac007c1 rev16 x1, x30 +- 4c8: dac009cd rev32 x13, x14 +- 4cc: dac00d05 rev x5, x8 +- 4d0: dac01322 clz x2, x25 +- 4d4: dac01514 cls x20, x8 +- 4d8: 1adb0b35 udiv w21, w25, w27 +- 4dc: 1ad00d4d sdiv w13, w10, w16 +- 4e0: 1ad1203c lsl w28, w1, w17 +- 4e4: 1aca26f9 lsr w25, w23, w10 +- 4e8: 1ac72867 asr w7, w3, w7 +- 4ec: 1ace2fce ror w14, w30, w14 +- 4f0: 9acf0acc udiv x12, x22, x15 +- 4f4: 9acd0f22 sdiv x2, x25, x13 +- 4f8: 9ad522e7 lsl x7, x23, x21 +- 4fc: 9ac0258b lsr x11, x12, x0 +- 500: 9adc293e asr x30, x9, x28 +- 504: 9ad62cad ror x13, x5, x22 +- 508: 9bc47ea5 umulh x5, x21, x4 +- 50c: 9b477c51 smulh x17, x2, x7 +- 510: 1b11318c madd w12, w12, w17, w12 +- 514: 1b01edfe msub w30, w15, w1, w27 +- 518: 9b117662 madd x2, x19, x17, x29 +- 51c: 9b03fae4 msub x4, x23, x3, x30 +- 520: 9b313eef smaddl x15, w23, w17, x15 +- 524: 9b21b59b smsubl x27, w12, w1, x13 +- 528: 9bac45a6 umaddl x6, w13, w12, x17 +- 52c: 9ba6a839 umsubl x25, w1, w6, x10 +- 530: 1e240871 fmul s17, s3, s4 +- 534: 1e3518b0 fdiv s16, s5, s21 +- 538: 1e312b63 fadd s3, s27, s17 +- 53c: 1e2f3959 fsub s25, s10, s15 +- 540: 1e200a2a fmul s10, s17, s0 +- 544: 1e630b5c fmul d28, d26, d3 +- 548: 1e7b1804 fdiv d4, d0, d27 +- 54c: 1e6229dc fadd d28, d14, d2 +- 550: 1e773b4c fsub d12, d26, d23 +- 554: 1e610bcf fmul d15, d30, d1 +- 558: 1f0534a4 fmadd s4, s5, s5, s13 +- 55c: 1f1c85b5 fmsub s21, s13, s28, s1 +- 560: 1f3d1c71 fnmadd s17, s3, s29, s7 +- 564: 1f3d6b37 fnmadd s23, s25, s29, s26 +- 568: 1f5e68ee fmadd d14, d7, d30, d26 +- 56c: 1f4aa4f6 fmsub d22, d7, d10, d9 +- 570: 1f6e24e7 fnmadd d7, d7, d14, d9 +- 574: 1f6f630e fnmadd d14, d24, d15, d24 +- 578: 1e204056 fmov s22, s2 +- 57c: 1e20c060 fabs s0, s3 +- 580: 1e214229 fneg s9, s17 +- 584: 1e21c178 fsqrt s24, s11 +- 588: 1e22c32f fcvt d15, s25 +- 58c: 1e604064 fmov d4, d3 +- 590: 1e60c2da fabs d26, d22 +- 594: 1e61427e fneg d30, d19 +- 598: 1e61c1cc fsqrt d12, d14 +- 59c: 1e6240f1 fcvt s17, d7 +- 5a0: 1e3801d8 fcvtzs w24, s14 +- 5a4: 9e38034d fcvtzs x13, s26 +- 5a8: 1e780022 fcvtzs w2, d1 +- 5ac: 9e780165 fcvtzs x5, d11 +- 5b0: 1e22026e scvtf s14, w19 +- 5b4: 9e2202c1 scvtf s1, x22 +- 5b8: 1e62023b scvtf d27, w17 +- 5bc: 9e620136 scvtf d22, x9 +- 5c0: 1e26006e fmov w14, s3 +- 5c4: 9e66022c fmov x12, d17 +- 5c8: 1e270368 fmov s8, w27 +- 5cc: 9e67039d fmov d29, x28 +- 5d0: 1e3e2000 fcmp s0, s30 +- 5d4: 1e692180 fcmp d12, d9 +- 5d8: 1e202148 fcmp s10, #0.0 +- 5dc: 1e602328 fcmp d25, #0.0 +- 5e0: 292e7b68 stp w8, w30, [x27, #-144] +- 5e4: 294a4f15 ldp w21, w19, [x24, #80] +- 5e8: 69626c50 ldpsw x16, x27, [x2, #-240] +- 5ec: a93814d5 stp x21, x5, [x6, #-128] +- 5f0: a97e679d ldp x29, x25, [x28, #-32] +- 5f4: 29903408 stp w8, w13, [x0, #128]! +- 5f8: 29ec5039 ldp w25, w20, [x1, #-160]! +- 5fc: 69fc62ce ldpsw x14, x24, [x22, #-32]! +- 600: a98504d1 stp x17, x1, [x6, #80]! +- 604: a9fc4735 ldp x21, x17, [x25, #-64]! +- 608: 28b05691 stp w17, w21, [x20], #-128 +- 60c: 28c8705c ldp w28, w28, [x2], #64 +- 610: 68e07953 ldpsw x19, x30, [x10], #-256 +- 614: a8bf3e31 stp x17, x15, [x17], #-16 +- 618: a8fe0331 ldp x17, x0, [x25], #-32 +- 61c: 283c170e stnp w14, w5, [x24, #-32] +- 620: 284e4c37 ldnp w23, w19, [x1, #112] +- 624: a80419cb stnp x11, x6, [x14, #64] +- 628: a8722f62 ldnp x2, x11, [x27, #-224] +- 62c: 0c407230 ld1 {v16.8b}, [x17] +- 630: 4cdfa13d ld1 {v29.16b, v30.16b}, [x9], #32 +- 634: 0cd56f1e ld1 {v30.1d, v31.1d, v0.1d}, [x24], x21 +- 638: 4cdf2440 ld1 {v0.8h-v3.8h}, [x2], #64 +- 63c: 0d40c134 ld1r {v20.8b}, [x9] +- 640: 4ddfc811 ld1r {v17.4s}, [x0], #4 +- 644: 0ddaced5 ld1r {v21.1d}, [x22], x26 +- 648: 4c408f33 ld2 {v19.2d, v20.2d}, [x25] +- 64c: 0cdf84aa ld2 {v10.4h, v11.4h}, [x5], #16 +- 650: 4d60c30a ld2r {v10.16b, v11.16b}, [x24] +- 654: 0dffcbad ld2r {v13.2s, v14.2s}, [x29], #8 +- 658: 4de2cf96 ld2r {v22.2d, v23.2d}, [x28], x2 +- 65c: 4ccb489e ld3 {v30.4s, v31.4s, v0.4s}, [x4], x11 +- 660: 0c40481d ld3 {v29.2s-v31.2s}, [x0] +- 664: 4d40e777 ld3r {v23.8h-v25.8h}, [x27] +- 668: 4ddfe943 ld3r {v3.4s-v5.4s}, [x10], #12 +- 66c: 0dd6edd3 ld3r {v19.1d-v21.1d}, [x14], x22 +- 670: 4cdf040e ld4 {v14.8h-v17.8h}, [x0], #64 +- 674: 0cd902de ld4 {v30.8b, v31.8b, v0.8b, v1.8b}, [x22], x25 +- 678: 0d60e019 ld4r {v25.8b-v28.8b}, [x0] +- 67c: 0dffe50a ld4r {v10.4h-v13.4h}, [x8], #8 +- 680: 0dfce8c1 ld4r {v1.2s-v4.2s}, [x6], x28 +- 684: ba5fd3e3 ccmn xzr, xzr, #0x3, le +- 688: 3a5f03e5 ccmn wzr, wzr, #0x5, eq // eq = none +- 68c: fa411be4 ccmp xzr, #0x1, #0x4, ne // ne = any +- 690: 7a42cbe2 ccmp wzr, #0x2, #0x2, gt +- 694: 93df03ff ror xzr, xzr, #0 +- 698: c820ffff stlxp w0, xzr, xzr, [sp] +- 69c: 8822fc7f stlxp w2, wzr, wzr, [x3] +- 6a0: c8247cbf stxp w4, xzr, xzr, [x5] +- 6a4: 88267fff stxp w6, wzr, wzr, [sp] +- 6a8: 4e010fe0 dup v0.16b, wzr +- 6ac: 4e081fe1 mov v1.d[0], xzr +- 6b0: 4e0c1fe1 mov v1.s[1], wzr +- 6b4: 4e0a1fe1 mov v1.h[2], wzr +- 6b8: 4e071fe1 mov v1.b[3], wzr +- 6bc: 4cc0ac3f ld1 {v31.2d, v0.2d}, [x1], x0 +- 6c0: 1e601000 fmov d0, #2.000000000000000000e+00 +- 6c4: 1e603000 fmov d0, #2.125000000000000000e+00 +- 6c8: 1e621000 fmov d0, #4.000000000000000000e+00 +- 6cc: 1e623000 fmov d0, #4.250000000000000000e+00 +- 6d0: 1e641000 fmov d0, #8.000000000000000000e+00 +- 6d4: 1e643000 fmov d0, #8.500000000000000000e+00 +- 6d8: 1e661000 fmov d0, #1.600000000000000000e+01 +- 6dc: 1e663000 fmov d0, #1.700000000000000000e+01 +- 6e0: 1e681000 fmov d0, #1.250000000000000000e-01 +- 6e4: 1e683000 fmov d0, #1.328125000000000000e-01 +- 6e8: 1e6a1000 fmov d0, #2.500000000000000000e-01 +- 6ec: 1e6a3000 fmov d0, #2.656250000000000000e-01 +- 6f0: 1e6c1000 fmov d0, #5.000000000000000000e-01 +- 6f4: 1e6c3000 fmov d0, #5.312500000000000000e-01 +- 6f8: 1e6e1000 fmov d0, #1.000000000000000000e+00 +- 6fc: 1e6e3000 fmov d0, #1.062500000000000000e+00 +- 700: 1e701000 fmov d0, #-2.000000000000000000e+00 +- 704: 1e703000 fmov d0, #-2.125000000000000000e+00 +- 708: 1e721000 fmov d0, #-4.000000000000000000e+00 +- 70c: 1e723000 fmov d0, #-4.250000000000000000e+00 +- 710: 1e741000 fmov d0, #-8.000000000000000000e+00 +- 714: 1e743000 fmov d0, #-8.500000000000000000e+00 +- 718: 1e761000 fmov d0, #-1.600000000000000000e+01 +- 71c: 1e763000 fmov d0, #-1.700000000000000000e+01 +- 720: 1e781000 fmov d0, #-1.250000000000000000e-01 +- 724: 1e783000 fmov d0, #-1.328125000000000000e-01 +- 728: 1e7a1000 fmov d0, #-2.500000000000000000e-01 +- 72c: 1e7a3000 fmov d0, #-2.656250000000000000e-01 +- 730: 1e7c1000 fmov d0, #-5.000000000000000000e-01 +- 734: 1e7c3000 fmov d0, #-5.312500000000000000e-01 +- 738: 1e7e1000 fmov d0, #-1.000000000000000000e+00 +- 73c: 1e7e3000 fmov d0, #-1.062500000000000000e+00 +- 740: f83081f4 swp x16, x20, [x15] +- 744: f8220387 ldadd x2, x7, [x28] +- 748: f834132a ldclr x20, x10, [x25] +- 74c: f836204b ldeor x22, x11, [x2] +- 750: f821326a ldset x1, x10, [x19] +- 754: f82e5075 ldsmin x14, x21, [x3] +- 758: f83c41bb ldsmax x28, x27, [x13] +- 75c: f83172be ldumin x17, x30, [x21] +- 760: f83b63b0 ldumax x27, x16, [x29] +- 764: f8be8009 swpa x30, x9, [x0] +- 768: f8bc039b ldadda x28, x27, [x28] +- 76c: f8b51159 ldclra x21, x25, [x10] +- 770: f8bf21f4 ldeora xzr, x20, [x15] +- 774: f8a131d9 ldseta x1, x25, [x14] +- 778: f8b553ba ldsmina x21, x26, [x29] +- 77c: f8a8433d ldsmaxa x8, x29, [x25] +- 780: f8ad7322 ldumina x13, x2, [x25] +- 784: f8af6017 ldumaxa x15, x23, [x0] +- 788: f8e38041 swpal x3, x1, [x2] +- 78c: f8fc0283 ldaddal x28, x3, [x20] +- 790: f8ee11df ldclral x14, xzr, [x14] +- 794: f8e7205c ldeoral x7, x28, [x2] +- 798: f8e030ab ldsetal x0, x11, [x5] +- 79c: f8eb528e ldsminal x11, x14, [x20] +- 7a0: f8ff4044 ldsmaxal xzr, x4, [x2] +- 7a4: f8fa72c0 lduminal x26, x0, [x22] +- 7a8: f8f161a1 ldumaxal x17, x1, [x13] +- 7ac: f877829a swpl x23, x26, [x20] +- 7b0: f86e018b ldaddl x14, x11, [x12] +- 7b4: f86c11ff stclrl x12, [x15] +- 7b8: f87b210e ldeorl x27, x14, [x8] +- 7bc: f86a333e ldsetl x10, x30, [x25] +- 7c0: f8765207 ldsminl x22, x7, [x16] +- 7c4: f8614110 ldsmaxl x1, x16, [x8] +- 7c8: f8617341 lduminl x1, x1, [x26] +- 7cc: f86061f7 ldumaxl x0, x23, [x15] +- 7d0: b82b8110 swp w11, w16, [x8] +- 7d4: b82101c7 ldadd w1, w7, [x14] +- 7d8: b830113f stclr w16, [x9] +- 7dc: b83621a6 ldeor w22, w6, [x13] +- 7e0: b82b308d ldset w11, w13, [x4] +- 7e4: b8305016 ldsmin w16, w22, [x0] +- 7e8: b83c415f stsmax w28, [x10] +- 7ec: b8307105 ldumin w16, w5, [x8] +- 7f0: b83a61f4 ldumax w26, w20, [x15] +- 7f4: b8bb8206 swpa w27, w6, [x16] +- 7f8: b8bf005f ldadda wzr, wzr, [x2] +- 7fc: b8b8111c ldclra w24, w28, [x8] +- 800: b8af22e9 ldeora w15, w9, [x23] +- 804: b8ba30e2 ldseta w26, w2, [x7] +- 808: b8a351f1 ldsmina w3, w17, [x15] +- 80c: b8b342a5 ldsmaxa w19, w5, [x21] +- 810: b8a7719a ldumina w7, w26, [x12] +- 814: b8ac63a7 ldumaxa w12, w7, [x29] +- 818: b8e98288 swpal w9, w8, [x20] +- 81c: b8e803df ldaddal w8, wzr, [x30] +- 820: b8e01186 ldclral w0, w6, [x12] +- 824: b8f12057 ldeoral w17, w23, [x2] +- 828: b8e0303e ldsetal w0, w30, [x1] +- 82c: b8f651e3 ldsminal w22, w3, [x15] +- 830: b8f941b5 ldsmaxal w25, w21, [x13] +- 834: b8ed7378 lduminal w13, w24, [x27] +- 838: b8f46163 ldumaxal w20, w3, [x11] +- 83c: b86382ad swpl w3, w13, [x21] +- 840: b87a034f ldaddl w26, w15, [x26] +- 844: b8691053 ldclrl w9, w19, [x2] +- 848: b87820fd ldeorl w24, w29, [x7] +- 84c: b87d31f9 ldsetl w29, w25, [x15] +- 850: b86b50fe ldsminl w11, w30, [x7] +- 854: b86b40c2 ldsmaxl w11, w2, [x6] +- 858: b87071cb lduminl w16, w11, [x14] +- 85c: b8656168 ldumaxl w5, w8, [x11] ++ 0: 8b8e677b add x27, x27, x14, asr #25 ++ 4: cb512964 sub x4, x11, x17, lsr #10 ++ 8: ab998627 adds x7, x17, x25, asr #33 ++ c: eb9416cd subs x13, x22, x20, asr #5 ++ 10: 0b83438a add w10, w28, w3, asr #16 ++ 14: 4b463c55 sub w21, w2, w6, lsr #15 ++ 18: 2b9b2406 adds w6, w0, w27, asr #9 ++ 1c: 6b882b65 subs w5, w27, w8, asr #10 ++ 20: 8a879c8c and x12, x4, x7, asr #39 ++ 24: aa16cb75 orr x21, x27, x22, lsl #50 ++ 28: ca80baa3 eor x3, x21, x0, asr #46 ++ 2c: ea855955 ands x21, x10, x5, asr #22 ++ 30: 0a1d5aad and w13, w21, w29, lsl #22 ++ 34: 2a504951 orr w17, w10, w16, lsr #18 ++ 38: 4a976cf0 eor w16, w7, w23, asr #27 ++ 3c: 6a8c30ca ands w10, w6, w12, asr #12 ++ 40: 8a275b33 bic x19, x25, x7, lsl #22 ++ 44: aa27d459 orn x25, x2, x7, lsl #53 ++ 48: cab70ee9 eon x9, x23, x23, asr #3 ++ 4c: eaadc8c5 bics x5, x6, x13, asr #50 ++ 50: 0a2a26af bic w15, w21, w10, lsl #9 ++ 54: 2abe06b1 orn w17, w21, w30, asr #1 ++ 58: 4a3d4f87 eon w7, w28, w29, lsl #19 ++ 5c: 6ab632d9 bics w25, w22, w22, asr #12 ++ 60: 110c5346 add w6, w26, #0x314 ++ 64: 3107aa23 adds w3, w17, #0x1ea ++ 68: 5107eea5 sub w5, w21, #0x1fb ++ 6c: 710dcf76 subs w22, w27, #0x373 ++ 70: 9103d10c add x12, x8, #0xf4 ++ 74: b10e811d adds x29, x8, #0x3a0 ++ 78: d10a087a sub x26, x3, #0x282 ++ 7c: f109d1fd subs x29, x15, #0x274 ++ 80: 1209afd5 and w21, w30, #0xff87ff87 ++ 84: 32099d95 orr w21, w12, #0x7f807f80 ++ 88: 5202c62b eor w11, w17, #0xc0c0c0c0 ++ 8c: 720897da ands w26, w30, #0x3f003f00 ++ 90: 920e36f9 and x25, x23, #0xfffc0000fffc0000 ++ 94: b243f1de orr x30, x14, #0xe3ffffffffffffff ++ 98: d263d09a eor x26, x4, #0xffffffffe003ffff ++ 9c: f24fd01a ands x26, x0, #0xfffe003fffffffff + a0: 14000000 b a0 + a4: 17ffffd7 b 0 -+ a8: 140001ee b 860 ++ a8: 1400023e b 9a0 + ac: 94000000 bl ac + b0: 97ffffd4 bl 0 -+ b4: 940001eb bl 860 -+ b8: 34000003 cbz w3, b8 -+ bc: 34fffa23 cbz w3, 0 -+ c0: 34003d03 cbz w3, 860 -+ c4: 35000002 cbnz w2, c4 -+ c8: 35fff9c2 cbnz w2, 0 -+ cc: 35003ca2 cbnz w2, 860 ++ b4: 9400023b bl 9a0 ++ b8: 3400001c cbz w28, b8 ++ bc: 34fffa3c cbz w28, 0 ++ c0: 3400471c cbz w28, 9a0 ++ c4: 35000011 cbnz w17, c4 ++ c8: 35fff9d1 cbnz w17, 0 ++ cc: 350046b1 cbnz w17, 9a0 + d0: b4000019 cbz x25, d0 + d4: b4fff979 cbz x25, 0 -+ d8: b4003c59 cbz x25, 860 -+ dc: b5000012 cbnz x18, dc -+ e0: b5fff912 cbnz x18, 0 -+ e4: b5003bf2 cbnz x18, 860 -+ e8: 10000008 adr x8, e8 -+ ec: 10fff8a8 adr x8, 0 -+ f0: 10003b88 adr x8, 860 -+ f4: 9000000f adrp x15, 0 -+ f8: 36700012 tbz w18, #14, f8 -+ fc: 3677f832 tbz w18, #14, 0 -+ 100: 36703b12 tbz w18, #14, 860 -+ 104: 37780019 tbnz w25, #15, 104 -+ 108: 377ff7d9 tbnz w25, #15, 0 -+ 10c: 37783ab9 tbnz w25, #15, 860 -+ 110: 12a203d2 mov w18, #0xefe1ffff // #-270401537 -+ 114: 5286b21e mov w30, #0x3590 // #13712 -+ 118: 72a66d35 movk w21, #0x3369, lsl #16 -+ 11c: 92eded92 mov x18, #0x9093ffffffffffff // #-8028792235694751745 -+ 120: d2eefecd mov x13, #0x77f6000000000000 // #8644096534784245760 -+ 124: f2ef69a3 movk x3, #0x7b4d, lsl #48 -+ 128: 93400c2a sbfx x10, x1, #0, #4 -+ 12c: 330562cc bfxil w12, w22, #5, #20 -+ 130: 530b2071 ubfiz w17, w3, #21, #9 -+ 134: 934b3860 sbfx x0, x3, #11, #4 -+ 138: b3473cdc bfxil x28, x6, #7, #9 -+ 13c: d3416549 ubfx x9, x10, #1, #25 -+ 140: 13995f75 extr w21, w27, w25, #23 -+ 144: 93d6462e extr x14, x17, x22, #17 ++ d8: b4004659 cbz x25, 9a0 ++ dc: b5000002 cbnz x2, dc ++ e0: b5fff902 cbnz x2, 0 ++ e4: b50045e2 cbnz x2, 9a0 ++ e8: 1000001d adr x29, e8 ++ ec: 10fff8bd adr x29, 0 ++ f0: 1000459d adr x29, 9a0 ++ f4: 9000001d adrp x29, 0 ++ f8: 36300006 tbz w6, #6, f8 ++ fc: 3637f826 tbz w6, #6, 0 ++ 100: 36304506 tbz w6, #6, 9a0 ++ 104: 37100015 tbnz w21, #2, 104 ++ 108: 3717f7d5 tbnz w21, #2, 0 ++ 10c: 371044b5 tbnz w21, #2, 9a0 ++ 110: 128155e8 mov w8, #0xfffff550 // #-2736 ++ 114: 52a5762b mov w11, #0x2bb10000 // #733020160 ++ 118: 72acb59a movk w26, #0x65ac, lsl #16 ++ 11c: 92866a8d mov x13, #0xffffffffffffccab // #-13141 ++ 120: d2e2d8a6 mov x6, #0x16c5000000000000 // #1640717639246413824 ++ 124: f2c54450 movk x16, #0x2a22, lsl #32 ++ 128: 93516bde sbfx x30, x30, #17, #10 ++ 12c: 330f3124 bfi w4, w9, #17, #13 ++ 130: 5301168f ubfx w15, w20, #1, #5 ++ 134: 9353391b sbfiz x27, x8, #45, #15 ++ 138: b355741e bfxil x30, x0, #21, #9 ++ 13c: d3562f5b ubfiz x27, x26, #42, #12 ++ 140: 13866d8c extr w12, w12, w6, #27 ++ 144: 93d6b5b3 extr x19, x13, x22, #45 + 148: 54000000 b.eq 148 // b.none + 14c: 54fff5a0 b.eq 0 // b.none -+ 150: 54003880 b.eq 860 // b.none ++ 150: 54004280 b.eq 9a0 // b.none + 154: 54000001 b.ne 154 // b.any + 158: 54fff541 b.ne 0 // b.any -+ 15c: 54003821 b.ne 860 // b.any ++ 15c: 54004221 b.ne 9a0 // b.any + 160: 54000002 b.cs 160 // b.hs, b.nlast + 164: 54fff4e2 b.cs 0 // b.hs, b.nlast -+ 168: 540037c2 b.cs 860 // b.hs, b.nlast ++ 168: 540041c2 b.cs 9a0 // b.hs, b.nlast + 16c: 54000002 b.cs 16c // b.hs, b.nlast + 170: 54fff482 b.cs 0 // b.hs, b.nlast -+ 174: 54003762 b.cs 860 // b.hs, b.nlast ++ 174: 54004162 b.cs 9a0 // b.hs, b.nlast + 178: 54000003 b.cc 178 // b.lo, b.ul, b.last + 17c: 54fff423 b.cc 0 // b.lo, b.ul, b.last -+ 180: 54003703 b.cc 860 // b.lo, b.ul, b.last ++ 180: 54004103 b.cc 9a0 // b.lo, b.ul, b.last + 184: 54000003 b.cc 184 // b.lo, b.ul, b.last + 188: 54fff3c3 b.cc 0 // b.lo, b.ul, b.last -+ 18c: 540036a3 b.cc 860 // b.lo, b.ul, b.last ++ 18c: 540040a3 b.cc 9a0 // b.lo, b.ul, b.last + 190: 54000004 b.mi 190 // b.first + 194: 54fff364 b.mi 0 // b.first -+ 198: 54003644 b.mi 860 // b.first ++ 198: 54004044 b.mi 9a0 // b.first + 19c: 54000005 b.pl 19c // b.nfrst + 1a0: 54fff305 b.pl 0 // b.nfrst -+ 1a4: 540035e5 b.pl 860 // b.nfrst ++ 1a4: 54003fe5 b.pl 9a0 // b.nfrst + 1a8: 54000006 b.vs 1a8 + 1ac: 54fff2a6 b.vs 0 -+ 1b0: 54003586 b.vs 860 ++ 1b0: 54003f86 b.vs 9a0 + 1b4: 54000007 b.vc 1b4 + 1b8: 54fff247 b.vc 0 -+ 1bc: 54003527 b.vc 860 ++ 1bc: 54003f27 b.vc 9a0 + 1c0: 54000008 b.hi 1c0 // b.pmore + 1c4: 54fff1e8 b.hi 0 // b.pmore -+ 1c8: 540034c8 b.hi 860 // b.pmore ++ 1c8: 54003ec8 b.hi 9a0 // b.pmore + 1cc: 54000009 b.ls 1cc // b.plast + 1d0: 54fff189 b.ls 0 // b.plast -+ 1d4: 54003469 b.ls 860 // b.plast ++ 1d4: 54003e69 b.ls 9a0 // b.plast + 1d8: 5400000a b.ge 1d8 // b.tcont + 1dc: 54fff12a b.ge 0 // b.tcont -+ 1e0: 5400340a b.ge 860 // b.tcont ++ 1e0: 54003e0a b.ge 9a0 // b.tcont + 1e4: 5400000b b.lt 1e4 // b.tstop + 1e8: 54fff0cb b.lt 0 // b.tstop -+ 1ec: 540033ab b.lt 860 // b.tstop ++ 1ec: 54003dab b.lt 9a0 // b.tstop + 1f0: 5400000c b.gt 1f0 + 1f4: 54fff06c b.gt 0 -+ 1f8: 5400334c b.gt 860 ++ 1f8: 54003d4c b.gt 9a0 + 1fc: 5400000d b.le 1fc + 200: 54fff00d b.le 0 -+ 204: 540032ed b.le 860 ++ 204: 54003ced b.le 9a0 + 208: 5400000e b.al 208 + 20c: 54ffefae b.al 0 -+ 210: 5400328e b.al 860 ++ 210: 54003c8e b.al 9a0 + 214: 5400000f b.nv 214 + 218: 54ffef4f b.nv 0 -+ 21c: 5400322f b.nv 860 -+ 220: d40f9ca1 svc #0x7ce5 -+ 224: d4008b22 hvc #0x459 -+ 228: d40be1c3 smc #0x5f0e -+ 22c: d423d0e0 brk #0x1e87 -+ 230: d44dee20 hlt #0x6f71 ++ 21c: 54003c2f b.nv 9a0 ++ 220: d407da81 svc #0x3ed4 ++ 224: d402d542 hvc #0x16aa ++ 228: d406dae3 smc #0x36d7 ++ 22c: d4258fa0 brk #0x2c7d ++ 230: d44d5960 hlt #0x6acb + 234: d503201f nop + 238: d69f03e0 eret + 23c: d6bf03e0 drps + 240: d5033fdf isb -+ 244: d503359f dsb nshld -+ 248: d50337bf dmb nsh -+ 24c: d61f0380 br x28 -+ 250: d63f0220 blr x17 -+ 254: c8127f47 stxr w18, x7, [x26] -+ 258: c819fccc stlxr w25, x12, [x6] -+ 25c: c85f7e00 ldxr x0, [x16] -+ 260: c85ffc66 ldaxr x6, [x3] -+ 264: c89ffc2e stlr x14, [x1] -+ 268: c8dfff1d ldar x29, [x24] -+ 26c: 881c7eef stxr w28, w15, [x23] -+ 270: 8809fc67 stlxr w9, w7, [x3] -+ 274: 885f7e81 ldxr w1, [x20] -+ 278: 885ffdf4 ldaxr w20, [x15] -+ 27c: 889ffd35 stlr w21, [x9] -+ 280: 88dffe25 ldar w5, [x17] -+ 284: 480d7fd4 stxrh w13, w20, [x30] -+ 288: 480afe4c stlxrh w10, w12, [x18] -+ 28c: 485f7e64 ldxrh w4, [x19] -+ 290: 485ffd56 ldaxrh w22, [x10] -+ 294: 489ffdfe stlrh w30, [x15] -+ 298: 48dfff04 ldarh w4, [x24] -+ 29c: 080a7d94 stxrb w10, w20, [x12] -+ 2a0: 0814fd7d stlxrb w20, w29, [x11] -+ 2a4: 085f7cb5 ldxrb w21, [x5] -+ 2a8: 085ffd24 ldaxrb w4, [x9] -+ 2ac: 089fff9e stlrb w30, [x28] -+ 2b0: 08dfff13 ldarb w19, [x24] -+ 2b4: c87f424b ldxp x11, x16, [x18] -+ 2b8: c87f9de8 ldaxp x8, x7, [x15] -+ 2bc: c83c4154 stxp w28, x20, x16, [x10] -+ 2c0: c827d469 stlxp w7, x9, x21, [x3] -+ 2c4: 887f1a79 ldxp w25, w6, [x19] -+ 2c8: 887fa45e ldaxp w30, w9, [x2] -+ 2cc: 88305180 stxp w16, w0, w20, [x12] -+ 2d0: 88259f82 stlxp w5, w2, w7, [x28] -+ 2d4: f81b5270 stur x16, [x19, #-75] -+ 2d8: b801e381 stur w1, [x28, #30] -+ 2dc: 381e61bc sturb w28, [x13, #-26] -+ 2e0: 781cd0c8 sturh w8, [x6, #-51] -+ 2e4: f851d380 ldur x0, [x28, #-227] -+ 2e8: b85e615c ldur w28, [x10, #-26] -+ 2ec: 39403164 ldrb w4, [x11, #12] -+ 2f0: 78405221 ldurh w1, [x17, #5] -+ 2f4: 3980312b ldrsb x11, [x9, #12] -+ 2f8: 789ef108 ldursh x8, [x8, #-17] -+ 2fc: 78ddd1b4 ldursh w20, [x13, #-35] -+ 300: b8831137 ldursw x23, [x9, #49] -+ 304: fc41d089 ldur d9, [x4, #29] -+ 308: bd402a6b ldr s11, [x19, #40] -+ 30c: fc1d5299 stur d25, [x20, #-43] -+ 310: bc1b0039 stur s25, [x1, #-80] -+ 314: f8019c14 str x20, [x0, #25]! -+ 318: b81cfd8c str w12, [x12, #-49]! -+ 31c: 381f6e7c strb w28, [x19, #-10]! -+ 320: 781c1f8d strh w13, [x28, #-63]! -+ 324: f85d2eeb ldr x11, [x23, #-46]! -+ 328: b8411f1b ldr w27, [x24, #17]! -+ 32c: 385f4f4e ldrb w14, [x26, #-12]! -+ 330: 785d3ed8 ldrh w24, [x22, #-45]! -+ 334: 389f5d39 ldrsb x25, [x9, #-11]! -+ 338: 7881dcc5 ldrsh x5, [x6, #29]! -+ 33c: 78dffee7 ldrsh w7, [x23, #-1]! -+ 340: b89c3dba ldrsw x26, [x13, #-61]! -+ 344: fc50bf18 ldr d24, [x24, #-245]! -+ 348: bc5c9f34 ldr s20, [x25, #-55]! -+ 34c: fc135c49 str d9, [x2, #-203]! -+ 350: bc1c5c2e str s14, [x1, #-59]! -+ 354: f806d433 str x19, [x1], #109 -+ 358: b81ca4a4 str w4, [x5], #-54 -+ 35c: 3800947d strb w29, [x3], #9 -+ 360: 781ce420 strh w0, [x1], #-50 -+ 364: f85d04c2 ldr x2, [x6], #-48 -+ 368: b858d4cf ldr w15, [x6], #-115 -+ 36c: 385e5444 ldrb w4, [x2], #-27 -+ 370: 785eb751 ldrh w17, [x26], #-21 -+ 374: 389f3715 ldrsb x21, [x24], #-13 -+ 378: 789d04d6 ldrsh x22, [x6], #-48 -+ 37c: 78dd04cb ldrsh w11, [x6], #-48 -+ 380: b89fb7ce ldrsw x14, [x30], #-5 -+ 384: fc5975e2 ldr d2, [x15], #-105 -+ 388: bc5a5679 ldr s25, [x19], #-91 -+ 38c: fc1416ed str d13, [x23], #-191 -+ 390: bc0006b6 str s22, [x21], #0 -+ 394: f832c996 str x22, [x12, w18, sxtw] -+ 398: b82c4b7e str w30, [x27, w12, uxtw] -+ 39c: 38367887 strb w7, [x4, x22, lsl #0] -+ 3a0: 783dfaf3 strh w19, [x23, x29, sxtx #1] -+ 3a4: f87bf891 ldr x17, [x4, x27, sxtx #3] -+ 3a8: b871c9a1 ldr w1, [x13, w17, sxtw] -+ 3ac: 387dfb70 ldrb w16, [x27, x29, sxtx #0] -+ 3b0: 78645939 ldrh w25, [x9, w4, uxtw #1] -+ 3b4: 38b67984 ldrsb x4, [x12, x22, lsl #0] -+ 3b8: 78a55839 ldrsh x25, [x1, w5, uxtw #1] -+ 3bc: 78fc6a09 ldrsh w9, [x16, x28] -+ 3c0: b8aee8e8 ldrsw x8, [x7, x14, sxtx] -+ 3c4: fc705b84 ldr d4, [x28, w16, uxtw #3] -+ 3c8: bc7bd850 ldr s16, [x2, w27, sxtw #2] -+ 3cc: fc396817 str d23, [x0, x25] -+ 3d0: bc277a06 str s6, [x16, x7, lsl #2] -+ 3d4: f91ddd82 str x2, [x12, #15288] -+ 3d8: b91b10a8 str w8, [x5, #6928] -+ 3dc: 391f8221 strb w1, [x17, #2016] -+ 3e0: 79197728 strh w8, [x25, #3258] -+ 3e4: f95ca07c ldr x28, [x3, #14656] -+ 3e8: b95b5d75 ldr w21, [x11, #7004] -+ 3ec: 395dc8af ldrb w15, [x5, #1906] -+ 3f0: 795caa60 ldrh w0, [x19, #3668] -+ 3f4: 399dd53d ldrsb x29, [x9, #1909] -+ 3f8: 799c7397 ldrsh x23, [x28, #3640] -+ 3fc: 79dcb15b ldrsh w27, [x10, #3672] -+ 400: b99e3b75 ldrsw x21, [x27, #7736] -+ 404: fd5c7f7a ldr d26, [x27, #14584] -+ 408: bd5d2882 ldr s2, [x4, #7464] -+ 40c: fd1fb2a1 str d1, [x21, #16224] -+ 410: bd1d82c4 str s4, [x22, #7552] -+ 414: 58000001 ldr x1, 414 -+ 418: 1800001b ldr w27, 418 -+ 41c: f882d080 prfum pldl1keep, [x4, #45] -+ 420: d8000000 prfm pldl1keep, 420 -+ 424: f8a0cbc0 prfm pldl1keep, [x30, w0, sxtw] -+ 428: f99fab00 prfm pldl1keep, [x24, #16208] -+ 42c: 1a1803a0 adc w0, w29, w24 -+ 430: 3a120396 adcs w22, w28, w18 -+ 434: 5a1e0217 sbc w23, w16, w30 -+ 438: 7a0e03a7 sbcs w7, w29, w14 -+ 43c: 9a0e0196 adc x22, x12, x14 -+ 440: ba17031d adcs x29, x24, x23 -+ 444: da160391 sbc x17, x28, x22 -+ 448: fa130298 sbcs x24, x20, x19 -+ 44c: 0b26cadb add w27, w22, w6, sxtw #2 -+ 450: 2b38516d adds w13, w11, w24, uxtw #4 -+ 454: cb242d10 sub x16, x8, w4, uxth #3 -+ 458: 6b34ea55 subs w21, w18, w20, sxtx #2 -+ 45c: 8b3d0a2e add x14, x17, w29, uxtb #2 -+ 460: ab2eb231 adds x17, x17, w14, sxth #4 -+ 464: cb3ac476 sub x22, x3, w26, sxtw #1 -+ 468: eb3531ad subs x13, x13, w21, uxth #4 -+ 46c: 3a5a722f ccmn w17, w26, #0xf, vc -+ 470: 7a463325 ccmp w25, w6, #0x5, cc // cc = lo, ul, last -+ 474: ba5e9021 ccmn x1, x30, #0x1, ls // ls = plast -+ 478: fa47a222 ccmp x17, x7, #0x2, ge // ge = tcont -+ 47c: 3a590a26 ccmn w17, #0x19, #0x6, eq // eq = none -+ 480: 7a450845 ccmp w2, #0x5, #0x5, eq // eq = none -+ 484: ba514a6a ccmn x19, #0x11, #0xa, mi // mi = first -+ 488: fa48c9c3 ccmp x14, #0x8, #0x3, gt -+ 48c: 1a8e9109 csel w9, w8, w14, ls // ls = plast -+ 490: 1a85d57b csinc w27, w11, w5, le -+ 494: 5a9632eb csinv w11, w23, w22, cc // cc = lo, ul, last -+ 498: 5a9b2793 csneg w19, w28, w27, cs // cs = hs, nlast -+ 49c: 9a815130 csel x16, x9, x1, pl // pl = nfrst -+ 4a0: 9a8c05dc csinc x28, x14, x12, eq // eq = none -+ 4a4: da8e5096 csinv x22, x4, x14, pl // pl = nfrst -+ 4a8: da9b257a csneg x26, x11, x27, cs // cs = hs, nlast -+ 4ac: 5ac00178 rbit w24, w11 -+ 4b0: 5ac005ca rev16 w10, w14 -+ 4b4: 5ac008a9 rev w9, w5 -+ 4b8: 5ac01292 clz w18, w20 -+ 4bc: 5ac01519 cls w25, w8 -+ 4c0: dac00316 rbit x22, x24 -+ 4c4: dac0077c rev16 x28, x27 -+ 4c8: dac00ba8 rev32 x8, x29 -+ 4cc: dac00d51 rev x17, x10 -+ 4d0: dac01177 clz x23, x11 -+ 4d4: dac015da cls x26, x14 -+ 4d8: 1adc0895 udiv w21, w4, w28 -+ 4dc: 1ad60d5e sdiv w30, w10, w22 -+ 4e0: 1ada205d lsl w29, w2, w26 -+ 4e4: 1aca26dc lsr w28, w22, w10 -+ 4e8: 1acc2b0b asr w11, w24, w12 -+ 4ec: 1ad02fd5 ror w21, w30, w16 -+ 4f0: 9acd0801 udiv x1, x0, x13 -+ 4f4: 9ac60e22 sdiv x2, x17, x6 -+ 4f8: 9ad5230a lsl x10, x24, x21 -+ 4fc: 9ac62525 lsr x5, x9, x6 -+ 500: 9ac42b60 asr x0, x27, x4 -+ 504: 9ac22c9c ror x28, x4, x2 -+ 508: 9bc77fc1 umulh x1, x30, x7 -+ 50c: 9b4a7cbe smulh x30, x5, x10 -+ 510: 1b0d45e7 madd w7, w15, w13, w17 -+ 514: 1b0cf039 msub w25, w1, w12, w28 -+ 518: 9b1e2562 madd x2, x11, x30, x9 -+ 51c: 9b03dae5 msub x5, x23, x3, x22 -+ 520: 9b291159 smaddl x25, w10, w9, x4 -+ 524: 9b27c905 smsubl x5, w8, w7, x18 -+ 528: 9bba64b8 umaddl x24, w5, w26, x25 -+ 52c: 9bbaf02e umsubl x14, w1, w26, x28 -+ 530: 1e280ad8 fmul s24, s22, s8 -+ 534: 1e261870 fdiv s16, s3, s6 -+ 538: 1e392ab0 fadd s16, s21, s25 -+ 53c: 1e3b3b40 fsub s0, s26, s27 -+ 540: 1e310878 fmul s24, s3, s17 -+ 544: 1e660909 fmul d9, d8, d6 -+ 548: 1e7e1a76 fdiv d22, d19, d30 -+ 54c: 1e632a2e fadd d14, d17, d3 -+ 550: 1e743b78 fsub d24, d27, d20 -+ 554: 1e76082c fmul d12, d1, d22 -+ 558: 1f0b7510 fmadd s16, s8, s11, s29 -+ 55c: 1f128676 fmsub s22, s19, s18, s1 -+ 560: 1f38270f fnmadd s15, s24, s24, s9 -+ 564: 1f2d5e7b fnmadd s27, s19, s13, s23 -+ 568: 1f503003 fmadd d3, d0, d16, d12 -+ 56c: 1f52a873 fmsub d19, d3, d18, d10 -+ 570: 1f6b5041 fnmadd d1, d2, d11, d20 -+ 574: 1f79392c fnmadd d12, d9, d25, d14 -+ 578: 1e2042e0 fmov s0, s23 -+ 57c: 1e20c0d7 fabs s23, s6 -+ 580: 1e214084 fneg s4, s4 -+ 584: 1e21c385 fsqrt s5, s28 -+ 588: 1e22c1f5 fcvt d21, s15 -+ 58c: 1e6040ab fmov d11, d5 -+ 590: 1e60c092 fabs d18, d4 -+ 594: 1e61418b fneg d11, d12 -+ 598: 1e61c10f fsqrt d15, d8 -+ 59c: 1e624048 fcvt s8, d2 -+ 5a0: 1e380253 fcvtzs w19, s18 -+ 5a4: 9e380011 fcvtzs x17, s0 -+ 5a8: 1e7801a0 fcvtzs w0, d13 -+ 5ac: 9e780136 fcvtzs x22, d9 -+ 5b0: 1e2203a6 scvtf s6, w29 -+ 5b4: 9e2201cc scvtf s12, x14 -+ 5b8: 1e6202d0 scvtf d16, w22 -+ 5bc: 9e6200ae scvtf d14, x5 -+ 5c0: 1e260007 fmov w7, s0 -+ 5c4: 9e6600dc fmov x28, d6 -+ 5c8: 1e270342 fmov s2, w26 -+ 5cc: 9e670004 fmov d4, x0 -+ 5d0: 1e2b2020 fcmp s1, s11 -+ 5d4: 1e7520c0 fcmp d6, d21 -+ 5d8: 1e202208 fcmp s16, #0.0 -+ 5dc: 1e6022c8 fcmp d22, #0.0 -+ 5e0: 290c0045 stp w5, w0, [x2, #96] -+ 5e4: 2978766e ldp w14, w29, [x19, #-64] -+ 5e8: 696c0c6f ldpsw x15, x3, [x3, #-160] -+ 5ec: a9323767 stp x7, x13, [x27, #-224] -+ 5f0: a9483831 ldp x17, x14, [x1, #128] -+ 5f4: 29905895 stp w21, w22, [x4, #128]! -+ 5f8: 29f43451 ldp w17, w13, [x2, #-96]! -+ 5fc: 69ee66f5 ldpsw x21, x25, [x23, #-144]! -+ 600: a9bf41e4 stp x4, x16, [x15, #-16]! -+ 604: a9f6573d ldp x29, x21, [x25, #-160]! -+ 608: 288a4758 stp w24, w17, [x26], #80 -+ 60c: 28e27bc3 ldp w3, w30, [x30], #-240 -+ 610: 68fc4fc3 ldpsw x3, x19, [x30], #-32 -+ 614: a8b70779 stp x25, x1, [x27], #-144 -+ 618: a8fc539a ldp x26, x20, [x28], #-64 -+ 61c: 283a653d stnp w29, w25, [x9, #-48] -+ 620: 28703a79 ldnp w25, w14, [x19, #-128] -+ 624: a8025879 stnp x25, x22, [x3, #32] -+ 628: a8734ba9 ldnp x9, x18, [x29, #-208] -+ 62c: 0c407275 ld1 {v21.8b}, [x19] -+ 630: 4cdfa29b ld1 {v27.16b, v28.16b}, [x20], #32 -+ 634: 0cc66ec5 ld1 {v5.1d-v7.1d}, [x22], x6 -+ 638: 4cdf2596 ld1 {v22.8h-v25.8h}, [x12], #64 -+ 63c: 0d40c131 ld1r {v17.8b}, [x9] -+ 640: 4ddfcaa5 ld1r {v5.4s}, [x21], #4 -+ 644: 0dd2cf8a ld1r {v10.1d}, [x28], x18 -+ 648: 4c408dfa ld2 {v26.2d, v27.2d}, [x15] -+ 64c: 0cdf8750 ld2 {v16.4h, v17.4h}, [x26], #16 -+ 650: 4d60c04e ld2r {v14.16b, v15.16b}, [x2] -+ 654: 0dffcb92 ld2r {v18.2s, v19.2s}, [x28], #8 -+ 658: 4df6cc13 ld2r {v19.2d, v20.2d}, [x0], x22 -+ 65c: 4cd24850 ld3 {v16.4s-v18.4s}, [x2], x18 -+ 660: 0c404818 ld3 {v24.2s-v26.2s}, [x0] -+ 664: 4d40e604 ld3r {v4.8h-v6.8h}, [x16] -+ 668: 4ddfe825 ld3r {v5.4s-v7.4s}, [x1], #12 -+ 66c: 0dd0ed47 ld3r {v7.1d-v9.1d}, [x10], x16 -+ 670: 4cdf0696 ld4 {v22.8h-v25.8h}, [x20], #64 -+ 674: 0cd9008f ld4 {v15.8b-v18.8b}, [x4], x25 -+ 678: 0d60e0a0 ld4r {v0.8b-v3.8b}, [x5] -+ 67c: 0dffe420 ld4r {v0.4h-v3.4h}, [x1], #8 -+ 680: 0deeeb9e ld4r {v30.2s, v31.2s, v0.2s, v1.2s}, [x28], x14 ++ 244: d503339f dsb osh ++ 248: d50336bf dmb nshst ++ 24c: d61f0160 br x11 ++ 250: d63f0320 blr x25 ++ 254: c80e7daf stxr w14, x15, [x13] ++ 258: c81efc39 stlxr w30, x25, [x1] ++ 25c: c85f7c6d ldxr x13, [x3] ++ 260: c85ffea8 ldaxr x8, [x21] ++ 264: c89fff8d stlr x13, [x28] ++ 268: c8dfffc8 ldar x8, [x30] ++ 26c: 880d7f91 stxr w13, w17, [x28] ++ 270: 8815fe71 stlxr w21, w17, [x19] ++ 274: 885f7d03 ldxr w3, [x8] ++ 278: 885ffebd ldaxr w29, [x21] ++ 27c: 889fff09 stlr w9, [x24] ++ 280: 88dffcc2 ldar w2, [x6] ++ 284: 480c7e14 stxrh w12, w20, [x16] ++ 288: 4802fcbc stlxrh w2, w28, [x5] ++ 28c: 485f7c61 ldxrh w1, [x3] ++ 290: 485ffdb8 ldaxrh w24, [x13] ++ 294: 489fff2f stlrh w15, [x25] ++ 298: 48dffe8a ldarh w10, [x20] ++ 29c: 08057db0 stxrb w5, w16, [x13] ++ 2a0: 080afe2f stlxrb w10, w15, [x17] ++ 2a4: 085f7e71 ldxrb w17, [x19] ++ 2a8: 085ffd3e ldaxrb w30, [x9] ++ 2ac: 089fff14 stlrb w20, [x24] ++ 2b0: 08dffc8a ldarb w10, [x4] ++ 2b4: c87f2139 ldxp x25, x8, [x9] ++ 2b8: c87faa07 ldaxp x7, x10, [x16] ++ 2bc: c8392d30 stxp w25, x16, x11, [x9] ++ 2c0: c827a5e5 stlxp w7, x5, x9, [x15] ++ 2c4: 887f106c ldxp w12, w4, [x3] ++ 2c8: 887f88b1 ldaxp w17, w2, [x5] ++ 2cc: 882460c8 stxp w4, w8, w24, [x6] ++ 2d0: 8824e60c stlxp w4, w12, w25, [x16] ++ 2d4: f800b3ce stur x14, [x30, #11] ++ 2d8: b819f3a6 stur w6, [x29, #-97] ++ 2dc: 381f9162 sturb w2, [x11, #-7] ++ 2e0: 781ea114 sturh w20, [x8, #-22] ++ 2e4: f85e33b4 ldur x20, [x29, #-29] ++ 2e8: b85e6009 ldur w9, [x0, #-26] ++ 2ec: 3940204e ldrb w14, [x2, #8] ++ 2f0: 785e802d ldurh w13, [x1, #-24] ++ 2f4: 389f922d ldursb x13, [x17, #-7] ++ 2f8: 789f50f1 ldursh x17, [x7, #-11] ++ 2fc: 78dc4103 ldursh w3, [x8, #-60] ++ 300: b9800d8e ldrsw x14, [x12, #12] ++ 304: fc5152a5 ldur d5, [x21, #-235] ++ 308: bc5ca009 ldur s9, [x0, #-54] ++ 30c: fc05f10f stur d15, [x8, #95] ++ 310: bc1f0016 stur s22, [x0, #-16] ++ 314: f8111c97 str x23, [x4, #-239]! ++ 318: b8186c11 str w17, [x0, #-122]! ++ 31c: 381fbd3a strb w26, [x9, #-5]! ++ 320: 781f8dd5 strh w21, [x14, #-8]! ++ 324: f8417ce8 ldr x8, [x7, #23]! ++ 328: b8416d0c ldr w12, [x8, #22]! ++ 32c: 38406f9b ldrb w27, [x28, #6]! ++ 330: 785c6e66 ldrh w6, [x19, #-58]! ++ 334: 389ecca7 ldrsb x7, [x5, #-20]! ++ 338: 789e0e36 ldrsh x22, [x17, #-32]! ++ 33c: 78dfedb1 ldrsh w17, [x13, #-2]! ++ 340: b8816c9d ldrsw x29, [x4, #22]! ++ 344: fc5b2f88 ldr d8, [x28, #-78]! ++ 348: bc5fbd77 ldr s23, [x11, #-5]! ++ 34c: fc1e9e89 str d9, [x20, #-23]! ++ 350: bc199c65 str s5, [x3, #-103]! ++ 354: f802044d str x13, [x2], #32 ++ 358: b803967e str w30, [x19], #57 ++ 35c: 3800343d strb w29, [x1], #3 ++ 360: 781ef74a strh w10, [x26], #-17 ++ 364: f85f442f ldr x15, [x1], #-12 ++ 368: b85fa4a1 ldr w1, [x5], #-6 ++ 36c: 385f25f8 ldrb w24, [x15], #-14 ++ 370: 785fb63d ldrh w29, [x17], #-5 ++ 374: 389ef5e4 ldrsb x4, [x15], #-17 ++ 378: 789ca446 ldrsh x6, [x2], #-54 ++ 37c: 78c1277b ldrsh w27, [x27], #18 ++ 380: b89b3729 ldrsw x9, [x25], #-77 ++ 384: fc5507b5 ldr d21, [x29], #-176 ++ 388: bc5ce53e ldr s30, [x9], #-50 ++ 38c: fc1d2582 str d2, [x12], #-46 ++ 390: bc1c56a7 str s7, [x21], #-59 ++ 394: f837598c str x12, [x12, w23, uxtw #3] ++ 398: b8364bce str w14, [x30, w22, uxtw] ++ 39c: 383a586c strb w12, [x3, w26, uxtw #0] ++ 3a0: 783e49cb strh w11, [x14, w30, uxtw] ++ 3a4: f8787918 ldr x24, [x8, x24, lsl #3] ++ 3a8: b87469ac ldr w12, [x13, x20] ++ 3ac: 38655896 ldrb w22, [x4, w5, uxtw #0] ++ 3b0: 786658bc ldrh w28, [x5, w6, uxtw #1] ++ 3b4: 38b97962 ldrsb x2, [x11, x25, lsl #0] ++ 3b8: 78b9ead7 ldrsh x23, [x22, x25, sxtx] ++ 3bc: 78f6da83 ldrsh w3, [x20, w22, sxtw #1] ++ 3c0: b8aefba9 ldrsw x9, [x29, x14, sxtx #2] ++ 3c4: fc7dfaf0 ldr d16, [x23, x29, sxtx #3] ++ 3c8: bc747b87 ldr s7, [x28, x20, lsl #2] ++ 3cc: fc387a94 str d20, [x20, x24, lsl #3] ++ 3d0: bc377ab9 str s25, [x21, x23, lsl #2] ++ 3d4: f9180c51 str x17, [x2, #12312] ++ 3d8: b91b38fe str w30, [x7, #6968] ++ 3dc: 391ca4e3 strb w3, [x7, #1833] ++ 3e0: 791a4c27 strh w7, [x1, #3366] ++ 3e4: f95ca767 ldr x7, [x27, #14664] ++ 3e8: b9580e28 ldr w8, [x17, #6156] ++ 3ec: 3958ea20 ldrb w0, [x17, #1594] ++ 3f0: 795bd680 ldrh w0, [x20, #3562] ++ 3f4: 399a4633 ldrsb x19, [x17, #1681] ++ 3f8: 799d80d3 ldrsh x19, [x6, #3776] ++ 3fc: 79dcf944 ldrsh w4, [x10, #3708] ++ 400: b99b249d ldrsw x29, [x4, #6948] ++ 404: fd5a143d ldr d29, [x1, #13352] ++ 408: bd59938f ldr s15, [x28, #6544] ++ 40c: fd1b9347 str d7, [x26, #14112] ++ 410: bd1aa7c0 str s0, [x30, #6820] ++ 414: 58000019 ldr x25, 414 ++ 418: 18000009 ldr w9, 418 ++ 41c: f88692c0 prfum pldl1keep, [x22, #105] ++ 420: d8ffdf00 prfm pldl1keep, 0 ++ 424: f8be7b80 prfm pldl1keep, [x28, x30, lsl #3] ++ 428: f99c8260 prfm pldl1keep, [x19, #14592] ++ 42c: 1a180111 adc w17, w8, w24 ++ 430: 3a09022e adcs w14, w17, w9 ++ 434: 5a190036 sbc w22, w1, w25 ++ 438: 7a13012f sbcs w15, w9, w19 ++ 43c: 9a0b028f adc x15, x20, x11 ++ 440: ba1e0164 adcs x4, x11, x30 ++ 444: da060114 sbc x20, x8, x6 ++ 448: fa0f02aa sbcs x10, x21, x15 ++ 44c: 0b298d61 add w1, w11, w9, sxtb #3 ++ 450: 2b3cee24 adds w4, w17, w28, sxtx #3 ++ 454: cb3ca7b5 sub x21, x29, w28, sxth #1 ++ 458: 6b37d38b subs w11, w28, w23, sxtw #4 ++ 45c: 8b25f34c add x12, x26, x5, sxtx #4 ++ 460: ab3e68d1 adds x17, x6, x30, uxtx #2 ++ 464: cb210a87 sub x7, x20, w1, uxtb #2 ++ 468: eb3eed3e subs x30, x9, x30, sxtx #3 ++ 46c: 3a4b0087 ccmn w4, w11, #0x7, eq // eq = none ++ 470: 7a4571eb ccmp w15, w5, #0xb, vc ++ 474: ba5122e6 ccmn x23, x17, #0x6, cs // cs = hs, nlast ++ 478: fa4bc16a ccmp x11, x11, #0xa, gt ++ 47c: 3a4519cc ccmn w14, #0x5, #0xc, ne // ne = any ++ 480: 7a5c1aef ccmp w23, #0x1c, #0xf, ne // ne = any ++ 484: ba5e3a27 ccmn x17, #0x1e, #0x7, cc // cc = lo, ul, last ++ 488: fa4c8bc0 ccmp x30, #0xc, #0x0, hi // hi = pmore ++ 48c: 1a81537a csel w26, w27, w1, pl // pl = nfrst ++ 490: 1a95d56e csinc w14, w11, w21, le ++ 494: 5a8f60de csinv w30, w6, w15, vs ++ 498: 5a995451 csneg w17, w2, w25, pl // pl = nfrst ++ 49c: 9a8780b0 csel x16, x5, x7, hi // hi = pmore ++ 4a0: 9a9cc68a csinc x10, x20, x28, gt ++ 4a4: da8180e6 csinv x6, x7, x1, hi // hi = pmore ++ 4a8: da912756 csneg x22, x26, x17, cs // cs = hs, nlast ++ 4ac: 5ac000cb rbit w11, w6 ++ 4b0: 5ac00760 rev16 w0, w27 ++ 4b4: 5ac00ba1 rev w1, w29 ++ 4b8: 5ac012b4 clz w20, w21 ++ 4bc: 5ac0158c cls w12, w12 ++ 4c0: dac00278 rbit x24, x19 ++ 4c4: dac005f7 rev16 x23, x15 ++ 4c8: dac00831 rev32 x17, x1 ++ 4cc: dac00c7b rev x27, x3 ++ 4d0: dac010be clz x30, x5 ++ 4d4: dac0140f cls x15, x0 ++ 4d8: 1ad4080e udiv w14, w0, w20 ++ 4dc: 1ad50d9b sdiv w27, w12, w21 ++ 4e0: 1ada214c lsl w12, w10, w26 ++ 4e4: 1ac6266e lsr w14, w19, w6 ++ 4e8: 1ade2a7b asr w27, w19, w30 ++ 4ec: 1ad02dc6 ror w6, w14, w16 ++ 4f0: 9ac209b1 udiv x17, x13, x2 ++ 4f4: 9ac20fa0 sdiv x0, x29, x2 ++ 4f8: 9ac2220c lsl x12, x16, x2 ++ 4fc: 9add26e9 lsr x9, x23, x29 ++ 500: 9add2a26 asr x6, x17, x29 ++ 504: 9ada2fce ror x14, x30, x26 ++ 508: 9bda7f11 umulh x17, x24, x26 ++ 50c: 9b4e7f54 smulh x20, x26, x14 ++ 510: 1b021d1b madd w27, w8, w2, w7 ++ 514: 1b19b1bc msub w28, w13, w25, w12 ++ 518: 9b0a6d24 madd x4, x9, x10, x27 ++ 51c: 9b08f956 msub x22, x10, x8, x30 ++ 520: 9b391694 smaddl x20, w20, w25, x5 ++ 524: 9b2beed6 smsubl x22, w22, w11, x27 ++ 528: 9bac4cc4 umaddl x4, w6, w12, x19 ++ 52c: 9ba881f1 umsubl x17, w15, w8, x0 ++ 530: 1e2a08b6 fmul s22, s5, s10 ++ 534: 1e301904 fdiv s4, s8, s16 ++ 538: 1e262919 fadd s25, s8, s6 ++ 53c: 1e393b66 fsub s6, s27, s25 ++ 540: 1e290aea fmul s10, s23, s9 ++ 544: 1e6c0a36 fmul d22, d17, d12 ++ 548: 1e74180b fdiv d11, d0, d20 ++ 54c: 1e6f2980 fadd d0, d12, d15 ++ 550: 1e643acf fsub d15, d22, d4 ++ 554: 1e79083d fmul d29, d1, d25 ++ 558: 1f131769 fmadd s9, s27, s19, s5 ++ 55c: 1f06e87a fmsub s26, s3, s6, s26 ++ 560: 1f285184 fnmadd s4, s12, s8, s20 ++ 564: 1f354539 fnmadd s25, s9, s21, s17 ++ 568: 1f5e5867 fmadd d7, d3, d30, d22 ++ 56c: 1f4aab61 fmsub d1, d27, d10, d10 ++ 570: 1f760511 fnmadd d17, d8, d22, d1 ++ 574: 1f626f8e fnmadd d14, d28, d2, d27 ++ 578: 1e2043db fmov s27, s30 ++ 57c: 1e20c025 fabs s5, s1 ++ 580: 1e214277 fneg s23, s19 ++ 584: 1e21c23c fsqrt s28, s17 ++ 588: 1e22c0d9 fcvt d25, s6 ++ 58c: 1e6041d4 fmov d20, d14 ++ 590: 1e60c151 fabs d17, d10 ++ 594: 1e61422a fneg d10, d17 ++ 598: 1e61c235 fsqrt d21, d17 ++ 59c: 1e6241f5 fcvt s21, d15 ++ 5a0: 1e380167 fcvtzs w7, s11 ++ 5a4: 9e3803a2 fcvtzs x2, s29 ++ 5a8: 1e780323 fcvtzs w3, d25 ++ 5ac: 9e78011c fcvtzs x28, d8 ++ 5b0: 1e22006b scvtf s11, w3 ++ 5b4: 9e2202a2 scvtf s2, x21 ++ 5b8: 1e62033d scvtf d29, w25 ++ 5bc: 9e620073 scvtf d19, x3 ++ 5c0: 1e2603b4 fmov w20, s29 ++ 5c4: 9e660237 fmov x23, d17 ++ 5c8: 1e270380 fmov s0, w28 ++ 5cc: 9e670289 fmov d9, x20 ++ 5d0: 1e2c20e0 fcmp s7, s12 ++ 5d4: 1e6e21a0 fcmp d13, d14 ++ 5d8: 1e202188 fcmp s12, #0.0 ++ 5dc: 1e602028 fcmp d1, #0.0 ++ 5e0: 29380acc stp w12, w2, [x22, #-64] ++ 5e4: 2966271b ldp w27, w9, [x24, #-208] ++ 5e8: 696a130f ldpsw x15, x4, [x24, #-176] ++ 5ec: a9015405 stp x5, x21, [x0, #16] ++ 5f0: a9735d26 ldp x6, x23, [x9, #-208] ++ 5f4: 29820fa0 stp w0, w3, [x29, #16]! ++ 5f8: 29ee403d ldp w29, w16, [x1, #-144]! ++ 5fc: 69c24ebb ldpsw x27, x19, [x21, #16]! ++ 600: a9b545a6 stp x6, x17, [x13, #-176]! ++ 604: a9c16020 ldp x0, x24, [x1, #16]! ++ 608: 288052c0 stp w0, w20, [x22], #0 ++ 60c: 28fa31d1 ldp w17, w12, [x14], #-48 ++ 610: 68ce682a ldpsw x10, x26, [x1], #112 ++ 614: a8ba61b4 stp x20, x24, [x13], #-96 ++ 618: a8c330e1 ldp x1, x12, [x7], #48 ++ 61c: 28362ae5 stnp w5, w10, [x23, #-80] ++ 620: 287a2b08 ldnp w8, w10, [x24, #-48] ++ 624: a8043d6b stnp x11, x15, [x11, #64] ++ 628: a84470a9 ldnp x9, x28, [x5, #64] ++ 62c: 0c40728b ld1 {v11.8b}, [x20] ++ 630: 4cdfa113 ld1 {v19.16b, v20.16b}, [x8], #32 ++ 634: 0cc36c43 ld1 {v3.1d-v5.1d}, [x2], x3 ++ 638: 4cdf2475 ld1 {v21.8h-v24.8h}, [x3], #64 ++ 63c: 0d40c0ae ld1r {v14.8b}, [x5] ++ 640: 4ddfcb6d ld1r {v13.4s}, [x27], #4 ++ 644: 0dc0ce71 ld1r {v17.1d}, [x19], x0 ++ 648: 4c408cbb ld2 {v27.2d, v28.2d}, [x5] ++ 64c: 0cdf849a ld2 {v26.4h, v27.4h}, [x4], #16 ++ 650: 4d60c2e8 ld2r {v8.16b, v9.16b}, [x23] ++ 654: 0dffc94e ld2r {v14.2s, v15.2s}, [x10], #8 ++ 658: 4df3ceaa ld2r {v10.2d, v11.2d}, [x21], x19 ++ 65c: 4cde49d1 ld3 {v17.4s-v19.4s}, [x14], x30 ++ 660: 0c404a94 ld3 {v20.2s-v22.2s}, [x20] ++ 664: 4d40e6b8 ld3r {v24.8h-v26.8h}, [x21] ++ 668: 4ddfe83a ld3r {v26.4s-v28.4s}, [x1], #12 ++ 66c: 0dc0ec4c ld3r {v12.1d-v14.1d}, [x2], x0 ++ 670: 4cdf04d5 ld4 {v21.8h-v24.8h}, [x6], #64 ++ 674: 0cd60391 ld4 {v17.8b-v20.8b}, [x28], x22 ++ 678: 0d60e333 ld4r {v19.8b-v22.8b}, [x25] ++ 67c: 0dffe6e6 ld4r {v6.4h-v9.4h}, [x23], #8 ++ 680: 0dfae928 ld4r {v8.2s-v11.2s}, [x9], x26 + 684: ba5fd3e3 ccmn xzr, xzr, #0x3, le + 688: 3a5f03e5 ccmn wzr, wzr, #0x5, eq // eq = none + 68c: fa411be4 ccmp xzr, #0x1, #0x4, ne // ne = any @@ -5431,352 +4658,756 @@ index 2a17d8e0f..943d2a615 100644 + 6b4: 4e0a1fe1 mov v1.h[2], wzr + 6b8: 4e071fe1 mov v1.b[3], wzr + 6bc: 4cc0ac3f ld1 {v31.2d, v0.2d}, [x1], x0 -+ 6c0: 1e601000 fmov d0, #2.000000000000000000e+00 -+ 6c4: 1e603000 fmov d0, #2.125000000000000000e+00 -+ 6c8: 1e621000 fmov d0, #4.000000000000000000e+00 -+ 6cc: 1e623000 fmov d0, #4.250000000000000000e+00 -+ 6d0: 1e641000 fmov d0, #8.000000000000000000e+00 -+ 6d4: 1e643000 fmov d0, #8.500000000000000000e+00 -+ 6d8: 1e661000 fmov d0, #1.600000000000000000e+01 -+ 6dc: 1e663000 fmov d0, #1.700000000000000000e+01 -+ 6e0: 1e681000 fmov d0, #1.250000000000000000e-01 -+ 6e4: 1e683000 fmov d0, #1.328125000000000000e-01 -+ 6e8: 1e6a1000 fmov d0, #2.500000000000000000e-01 -+ 6ec: 1e6a3000 fmov d0, #2.656250000000000000e-01 -+ 6f0: 1e6c1000 fmov d0, #5.000000000000000000e-01 -+ 6f4: 1e6c3000 fmov d0, #5.312500000000000000e-01 -+ 6f8: 1e6e1000 fmov d0, #1.000000000000000000e+00 -+ 6fc: 1e6e3000 fmov d0, #1.062500000000000000e+00 -+ 700: 1e701000 fmov d0, #-2.000000000000000000e+00 -+ 704: 1e703000 fmov d0, #-2.125000000000000000e+00 -+ 708: 1e721000 fmov d0, #-4.000000000000000000e+00 -+ 70c: 1e723000 fmov d0, #-4.250000000000000000e+00 -+ 710: 1e741000 fmov d0, #-8.000000000000000000e+00 -+ 714: 1e743000 fmov d0, #-8.500000000000000000e+00 -+ 718: 1e761000 fmov d0, #-1.600000000000000000e+01 -+ 71c: 1e763000 fmov d0, #-1.700000000000000000e+01 -+ 720: 1e781000 fmov d0, #-1.250000000000000000e-01 -+ 724: 1e783000 fmov d0, #-1.328125000000000000e-01 -+ 728: 1e7a1000 fmov d0, #-2.500000000000000000e-01 -+ 72c: 1e7a3000 fmov d0, #-2.656250000000000000e-01 -+ 730: 1e7c1000 fmov d0, #-5.000000000000000000e-01 -+ 734: 1e7c3000 fmov d0, #-5.312500000000000000e-01 -+ 738: 1e7e1000 fmov d0, #-1.000000000000000000e+00 -+ 73c: 1e7e3000 fmov d0, #-1.062500000000000000e+00 -+ 740: f83a8229 swp x26, x9, [x17] -+ 744: f83c0057 ldadd x28, x23, [x2] -+ 748: f8361062 ldclr x22, x2, [x3] -+ 74c: f82b23d9 ldeor x11, x25, [x30] -+ 750: f836309c ldset x22, x28, [x4] -+ 754: f826530b ldsmin x6, x11, [x24] -+ 758: f82c43ff stsmax x12, [sp] -+ 75c: f837713e ldumin x23, x30, [x9] -+ 760: f8266281 ldumax x6, x1, [x20] -+ 764: f8b182c2 swpa x17, x2, [x22] -+ 768: f8ae015b ldadda x14, x27, [x10] -+ 76c: f8a6127e ldclra x6, x30, [x19] -+ 770: f8a02179 ldeora x0, x25, [x11] -+ 774: f8b733c0 ldseta x23, x0, [x30] -+ 778: f8b55143 ldsmina x21, x3, [x10] -+ 77c: f8af4016 ldsmaxa x15, x22, [x0] -+ 780: f8b17280 ldumina x17, x0, [x20] -+ 784: f8b0602d ldumaxa x16, x13, [x1] -+ 788: f8fb82ef swpal x27, x15, [x23] -+ 78c: f8f3003e ldaddal x19, x30, [x1] -+ 790: f8ef12fc ldclral x15, x28, [x23] -+ 794: f8e7226f ldeoral x7, x15, [x19] -+ 798: f8eb314c ldsetal x11, x12, [x10] -+ 79c: f8e65187 ldsminal x6, x7, [x12] -+ 7a0: f8fc41a5 ldsmaxal x28, x5, [x13] -+ 7a4: f8e97234 lduminal x9, x20, [x17] -+ 7a8: f8f56179 ldumaxal x21, x25, [x11] -+ 7ac: f8738318 swpl x19, x24, [x24] -+ 7b0: f86803da ldaddl x8, x26, [x30] -+ 7b4: f8711112 ldclrl x17, x18, [x8] -+ 7b8: f8622063 ldeorl x2, x3, [x3] -+ 7bc: f87a3207 ldsetl x26, x7, [x16] -+ 7c0: f87b50a6 ldsminl x27, x6, [x5] -+ 7c4: f8764280 ldsmaxl x22, x0, [x20] -+ 7c8: f86b705a lduminl x11, x26, [x2] -+ 7cc: f87e609d ldumaxl x30, x29, [x4] -+ 7d0: b82480e5 swp w4, w5, [x7] -+ 7d4: b82a005a ldadd w10, w26, [x2] -+ 7d8: b83b1370 ldclr w27, w16, [x27] -+ 7dc: b83f2157 ldeor wzr, w23, [x10] -+ 7e0: b82431a2 ldset w4, w2, [x13] -+ 7e4: b823506f ldsmin w3, w15, [x3] -+ 7e8: b82340ca ldsmax w3, w10, [x6] -+ 7ec: b828714b ldumin w8, w11, [x10] -+ 7f0: b83d61be ldumax w29, w30, [x13] -+ 7f4: b8ab8291 swpa w11, w17, [x20] -+ 7f8: b8ba00d0 ldadda w26, w16, [x6] -+ 7fc: b8b5102a ldclra w21, w10, [x1] -+ 800: b8bd22ec ldeora w29, w12, [x23] -+ 804: b8bd3108 ldseta w29, w8, [x8] -+ 808: b8ab51ca ldsmina w11, w10, [x14] -+ 80c: b8a442cd ldsmaxa w4, w13, [x22] -+ 810: b8a770ed ldumina w7, w13, [x7] -+ 814: b8ae63e0 ldumaxa w14, w0, [sp] -+ 818: b8f18382 swpal w17, w2, [x28] -+ 81c: b8f3014b ldaddal w19, w11, [x10] -+ 820: b8ec1293 ldclral w12, w19, [x20] -+ 824: b8e02108 ldeoral w0, w8, [x8] -+ 828: b8f13303 ldsetal w17, w3, [x24] -+ 82c: b8f950e5 ldsminal w25, w5, [x7] -+ 830: b8f0413e ldsmaxal w16, w30, [x9] -+ 834: b8ea71df lduminal w10, wzr, [x14] -+ 838: b8f16173 ldumaxal w17, w19, [x11] -+ 83c: b87481a1 swpl w20, w1, [x13] -+ 840: b87a028b ldaddl w26, w11, [x20] -+ 844: b87213d8 ldclrl w18, w24, [x30] -+ 848: b86c2299 ldeorl w12, w25, [x20] -+ 84c: b86e30bd ldsetl w14, w29, [x5] -+ 850: b862537a ldsminl w2, w26, [x27] -+ 854: b879417b ldsmaxl w25, w27, [x11] -+ 858: b86470fd lduminl w4, w29, [x7] -+ 85c: b870615d ldumaxl w16, w29, [x10] ++ 6c0: 05a08020 mov z0.s, p0/m, s1 ++ 6c4: 04b0e3e0 incw x0 ++ 6c8: 0470e7e1 dech x1 ++ 6cc: 042f9c20 lsl z0.b, z1.b, #7 ++ 6d0: 043f9c35 lsl z21.h, z1.h, #15 ++ 6d4: 047f9c20 lsl z0.s, z1.s, #31 ++ 6d8: 04ff9c20 lsl z0.d, z1.d, #63 ++ 6dc: 04299420 lsr z0.b, z1.b, #7 ++ 6e0: 04319160 asr z0.h, z11.h, #15 ++ 6e4: 0461943e lsr z30.s, z1.s, #31 ++ 6e8: 04a19020 asr z0.d, z1.d, #63 ++ 6ec: 042053ff addvl sp, x0, #31 ++ 6f0: 047f5401 addpl x1, sp, #-32 ++ 6f4: 25208028 cntp x8, p0, p1.b ++ 6f8: 2538cfe0 mov z0.b, #127 ++ 6fc: 2578d001 mov z1.h, #-128 ++ 700: 25b8efe2 mov z2.s, #32512 ++ 704: 25f8f007 mov z7.d, #-32768 ++ 708: a400a3e0 ld1b {z0.b}, p0/z, [sp] ++ 70c: a4a8a7ea ld1h {z10.h}, p1/z, [sp, #-8, mul vl] ++ 710: a547a814 ld1w {z20.s}, p2/z, [x0, #7, mul vl] ++ 714: a4084ffe ld1b {z30.b}, p3/z, [sp, x8] ++ 718: a55c53e0 ld1w {z0.s}, p4/z, [sp, x28, lsl #2] ++ 71c: a5e1540b ld1d {z11.d}, p5/z, [x0, x1, lsl #3] ++ 720: e400fbf6 st1b {z22.b}, p6, [sp] ++ 724: e408ffff st1b {z31.b}, p7, [sp, #-8, mul vl] ++ 728: e547e400 st1w {z0.s}, p1, [x0, #7, mul vl] ++ 72c: e4014be0 st1b {z0.b}, p2, [sp, x1] ++ 730: e4a84fe0 st1h {z0.h}, p3, [sp, x8, lsl #1] ++ 734: e5e85000 st1d {z0.d}, p4, [x0, x8, lsl #3] ++ 738: 858043e0 ldr z0, [sp] ++ 73c: 85a043ff ldr z31, [sp, #-256, mul vl] ++ 740: e59f5d08 str z8, [x8, #255, mul vl] ++ 744: 1e601000 fmov d0, #2.000000000000000000e+00 ++ 748: 1e603000 fmov d0, #2.125000000000000000e+00 ++ 74c: 1e621000 fmov d0, #4.000000000000000000e+00 ++ 750: 1e623000 fmov d0, #4.250000000000000000e+00 ++ 754: 1e641000 fmov d0, #8.000000000000000000e+00 ++ 758: 1e643000 fmov d0, #8.500000000000000000e+00 ++ 75c: 1e661000 fmov d0, #1.600000000000000000e+01 ++ 760: 1e663000 fmov d0, #1.700000000000000000e+01 ++ 764: 1e681000 fmov d0, #1.250000000000000000e-01 ++ 768: 1e683000 fmov d0, #1.328125000000000000e-01 ++ 76c: 1e6a1000 fmov d0, #2.500000000000000000e-01 ++ 770: 1e6a3000 fmov d0, #2.656250000000000000e-01 ++ 774: 1e6c1000 fmov d0, #5.000000000000000000e-01 ++ 778: 1e6c3000 fmov d0, #5.312500000000000000e-01 ++ 77c: 1e6e1000 fmov d0, #1.000000000000000000e+00 ++ 780: 1e6e3000 fmov d0, #1.062500000000000000e+00 ++ 784: 1e701000 fmov d0, #-2.000000000000000000e+00 ++ 788: 1e703000 fmov d0, #-2.125000000000000000e+00 ++ 78c: 1e721000 fmov d0, #-4.000000000000000000e+00 ++ 790: 1e723000 fmov d0, #-4.250000000000000000e+00 ++ 794: 1e741000 fmov d0, #-8.000000000000000000e+00 ++ 798: 1e743000 fmov d0, #-8.500000000000000000e+00 ++ 79c: 1e761000 fmov d0, #-1.600000000000000000e+01 ++ 7a0: 1e763000 fmov d0, #-1.700000000000000000e+01 ++ 7a4: 1e781000 fmov d0, #-1.250000000000000000e-01 ++ 7a8: 1e783000 fmov d0, #-1.328125000000000000e-01 ++ 7ac: 1e7a1000 fmov d0, #-2.500000000000000000e-01 ++ 7b0: 1e7a3000 fmov d0, #-2.656250000000000000e-01 ++ 7b4: 1e7c1000 fmov d0, #-5.000000000000000000e-01 ++ 7b8: 1e7c3000 fmov d0, #-5.312500000000000000e-01 ++ 7bc: 1e7e1000 fmov d0, #-1.000000000000000000e+00 ++ 7c0: 1e7e3000 fmov d0, #-1.062500000000000000e+00 ++ 7c4: f82b82af swp x11, x15, [x21] ++ 7c8: f83700a8 ldadd x23, x8, [x5] ++ 7cc: f8271106 ldclr x7, x6, [x8] ++ 7d0: f82e22ee ldeor x14, x14, [x23] ++ 7d4: f82a3019 ldset x10, x25, [x0] ++ 7d8: f82552a9 ldsmin x5, x9, [x21] ++ 7dc: f824423b ldsmax x4, x27, [x17] ++ 7e0: f82a71a6 ldumin x10, x6, [x13] ++ 7e4: f8236203 ldumax x3, x3, [x16] ++ 7e8: f8a9805c swpa x9, x28, [x2] ++ 7ec: f8b70022 ldadda x23, x2, [x1] ++ 7f0: f8a410fa ldclra x4, x26, [x7] ++ 7f4: f8a02143 ldeora x0, x3, [x10] ++ 7f8: f8b83079 ldseta x24, x25, [x3] ++ 7fc: f8ab5028 ldsmina x11, x8, [x1] ++ 800: f8b043ad ldsmaxa x16, x13, [x29] ++ 804: f8a670a0 ldumina x6, x0, [x5] ++ 808: f8b061b1 ldumaxa x16, x17, [x13] ++ 80c: f8eb81db swpal x11, x27, [x14] ++ 810: f8e202ad ldaddal x2, x13, [x21] ++ 814: f8f6119f ldclral x22, xzr, [x12] ++ 818: f8e721fe ldeoral x7, x30, [x15] ++ 81c: f8e731f0 ldsetal x7, x16, [x15] ++ 820: f8f051ba ldsminal x16, x26, [x13] ++ 824: f8f74379 ldsmaxal x23, x25, [x27] ++ 828: f8e473ee lduminal x4, x14, [sp] ++ 82c: f8f86221 ldumaxal x24, x1, [x17] ++ 830: f8628308 swpl x2, x8, [x24] ++ 834: f874027b ldaddl x20, x27, [x19] ++ 838: f87310d1 ldclrl x19, x17, [x6] ++ 83c: f86e235c ldeorl x14, x28, [x26] ++ 840: f8623270 ldsetl x2, x16, [x19] ++ 844: f86e5090 ldsminl x14, x16, [x4] ++ 848: f8794128 ldsmaxl x25, x8, [x9] ++ 84c: f86a73a5 lduminl x10, x5, [x29] ++ 850: f86661c2 ldumaxl x6, x2, [x14] ++ 854: b831808b swp w17, w11, [x4] ++ 858: b82701f0 ldadd w7, w16, [x15] ++ 85c: b82b1139 ldclr w11, w25, [x9] ++ 860: b823200e ldeor w3, w14, [x0] ++ 864: b820301e ldset w0, w30, [x0] ++ 868: b826538a ldsmin w6, w10, [x28] ++ 86c: b82740ce ldsmax w7, w14, [x6] ++ 870: b826701e ldumin w6, w30, [x0] ++ 874: b83663be ldumax w22, w30, [x29] ++ 878: b8b0826e swpa w16, w14, [x19] ++ 87c: b8b50323 ldadda w21, w3, [x25] ++ 880: b8a21270 ldclra w2, w16, [x19] ++ 884: b8ba22f4 ldeora w26, w20, [x23] ++ 888: b8b133e6 ldseta w17, w6, [sp] ++ 88c: b8a553d7 ldsmina w5, w23, [x30] ++ 890: b8ab41cc ldsmaxa w11, w12, [x14] ++ 894: b8a271b4 ldumina w2, w20, [x13] ++ 898: b8af6291 ldumaxa w15, w17, [x20] ++ 89c: b8e682fc swpal w6, w28, [x23] ++ 8a0: b8fb01b0 ldaddal w27, w16, [x13] ++ 8a4: b8e21317 ldclral w2, w23, [x24] ++ 8a8: b8e0215c ldeoral w0, w28, [x10] ++ 8ac: b8e330af ldsetal w3, w15, [x5] ++ 8b0: b8e353ab ldsminal w3, w11, [x29] ++ 8b4: b8f640db ldsmaxal w22, w27, [x6] ++ 8b8: b8f17214 lduminal w17, w20, [x16] ++ 8bc: b8f760ef ldumaxal w23, w15, [x7] ++ 8c0: b86881d0 swpl w8, w16, [x14] ++ 8c4: b87702f0 ldaddl w23, w16, [x23] ++ 8c8: b87c10ec ldclrl w28, w12, [x7] ++ 8cc: b87c2267 ldeorl w28, w7, [x19] ++ 8d0: b867316c ldsetl w7, w12, [x11] ++ 8d4: b86a529f stsminl w10, [x20] ++ 8d8: b86943e8 ldsmaxl w9, w8, [sp] ++ 8dc: b86a7048 lduminl w10, w8, [x2] ++ 8e0: b87163ff stumaxl w17, [sp] ++ 8e4: 047600e2 add z2.h, z7.h, z22.h ++ 8e8: 04be06de sub z30.s, z22.s, z30.s ++ 8ec: 65d902ca fadd z10.d, z22.d, z25.d ++ 8f0: 65cc0a17 fmul z23.d, z16.d, z12.d ++ 8f4: 65d90623 fsub z3.d, z17.d, z25.d ++ 8f8: 0496a099 abs z25.s, p0/m, z4.s ++ 8fc: 04401b57 add z23.h, p6/m, z23.h, z26.h ++ 900: 04d08226 asr z6.d, p0/m, z6.d, z17.d ++ 904: 04daac77 cnt z23.d, p3/m, z3.d ++ 908: 04939d2b lsl z11.s, p7/m, z11.s, z9.s ++ 90c: 04919c7b lsr z27.s, p7/m, z27.s, z3.s ++ 910: 04901049 mul z9.s, p4/m, z9.s, z2.s ++ 914: 0417a9f0 neg z16.b, p2/m, z15.b ++ 918: 04dea929 not z9.d, p2/m, z9.d ++ 91c: 048816ea smax z10.s, p5/m, z10.s, z23.s ++ 920: 040a172d smin z13.b, p5/m, z13.b, z25.b ++ 924: 04811413 sub z19.s, p5/m, z19.s, z0.s ++ 928: 04dca2d1 fabs z17.d, p0/m, z22.d ++ 92c: 65808a09 fadd z9.s, p2/m, z9.s, z16.s ++ 930: 658d9411 fdiv z17.s, p5/m, z17.s, z0.s ++ 934: 6586947d fmax z29.s, p5/m, z29.s, z3.s ++ 938: 65878e21 fmin z1.s, p3/m, z1.s, z17.s ++ 93c: 65c2880e fmul z14.d, p2/m, z14.d, z0.d ++ 940: 04ddb2d3 fneg z19.d, p4/m, z22.d ++ 944: 65c2a5f1 frintm z17.d, p1/m, z15.d ++ 948: 65c0b088 frintn z8.d, p4/m, z4.d ++ 94c: 65c1b3a5 frintp z5.d, p4/m, z29.d ++ 950: 65cda26b fsqrt z11.d, p0/m, z19.d ++ 954: 65c1938a fsub z10.d, p4/m, z10.d, z28.d ++ 958: 65eb0ded fmla z13.d, p3/m, z15.d, z11.d ++ 95c: 65af3e86 fmls z6.s, p7/m, z20.s, z15.s ++ 960: 65a749be fnmla z30.s, p2/m, z13.s, z7.s ++ 964: 65f379d6 fnmls z22.d, p6/m, z14.d, z19.d ++ 968: 04404f3e mla z30.h, p3/m, z25.h, z0.h ++ 96c: 04c16b0a mls z10.d, p2/m, z24.d, z1.d ++ 970: 04363226 and z6.d, z17.d, z22.d ++ 974: 04b1312a eor z10.d, z9.d, z17.d ++ 978: 04753182 orr z2.d, z12.d, z21.d ++ 97c: 049a39cf andv s15, p6, z14.s ++ 980: 04d82ce9 orv d9, p3, z7.d ++ 984: 0459353e eorv h30, p5, z9.h ++ 988: 04883347 smaxv s7, p4, z26.s ++ 98c: 048a2fb4 sminv s20, p3, z29.s ++ 990: 65872e1c fminv s28, p3, z16.s ++ 994: 65c62d26 fmaxv d6, p3, z9.d ++ 998: 6598346a fadda s10, p5, s10, z3.s ++ 99c: 04013915 uaddv d21, p6, z8.b */ static const unsigned int insns[] = { -- 0x8b50798f, 0xcb4381e1, 0xab05372d, 0xeb864796, -- 0x0b961920, 0x4b195473, 0x2b0b5264, 0x6b9300f8, -- 0x8a0bc0fe, 0xaa0f3118, 0xca170531, 0xea44dd6e, -- 0x0a4c44f3, 0x2a8b7373, 0x4a567c7e, 0x6a9c0353, -- 0x8a3accdd, 0xaa318f7a, 0xca2e1495, 0xeaa015e2, -- 0x0a2274e2, 0x2a751598, 0x4a3309fe, 0x6ab172fe, -- 0x110a5284, 0x310b1942, 0x5103d353, 0x710125bc, -- 0x910d7bc2, 0xb108fa1b, 0xd1093536, 0xf10ae824, -- 0x120e667c, 0x321f6cbb, 0x520f6a9e, 0x72136f56, -- 0x927e4ce5, 0xb278b4ed, 0xd24c6527, 0xf2485803, -+ 0x8b4db437, 0xcb8ce3c8, 0xab0edafb, 0xeb5499f5, -+ 0x0b040e39, 0x4b89503d, 0x2b89274a, 0x6b870fd5, -+ 0x8a4b1109, 0xaa810643, 0xca026e8a, 0xea8b7d2c, -+ 0x0a9e6934, 0x2a9a4555, 0x4a871d00, 0x6a084973, -+ 0x8a23d497, 0xaa3360c9, 0xca7ad8cc, 0xea2c3a76, -+ 0x0a362dbd, 0x2ab417d1, 0x4a2b23a1, 0x6a667684, -+ 0x1107e0de, 0x310ebd13, 0x5105b55d, 0x71047104, -+ 0x910ef9c3, 0xb1029e96, 0xd10b55fb, 0xf10ecf98, -+ 0x12099f39, 0x321b3f4d, 0x520309b5, 0x72134062, -+ 0x92004548, 0xb24d861b, 0xd219587b, 0xf25eaee4, - 0x14000000, 0x17ffffd7, 0x140001ee, 0x94000000, -- 0x97ffffd4, 0x940001eb, 0x34000010, 0x34fffa30, -- 0x34003d10, 0x35000013, 0x35fff9d3, 0x35003cb3, -- 0xb4000005, 0xb4fff965, 0xb4003c45, 0xb5000004, -- 0xb5fff904, 0xb5003be4, 0x1000001b, 0x10fff8bb, -- 0x10003b9b, 0x90000010, 0x3640001c, 0x3647f83c, -- 0x36403b1c, 0x37080001, 0x370ff7c1, 0x37083aa1, -- 0x12a437f4, 0x528c9d67, 0x72838bb1, 0x92c1062e, -- 0xd287da49, 0xf2a6d153, 0x93465ac9, 0x330b0013, -- 0x530b4e6a, 0x934545e4, 0xb35370a3, 0xd3510b8c, -- 0x13960c0f, 0x93ceddc6, 0x54000000, 0x54fff5a0, -+ 0x97ffffd4, 0x940001eb, 0x34000003, 0x34fffa23, -+ 0x34003d03, 0x35000002, 0x35fff9c2, 0x35003ca2, -+ 0xb4000019, 0xb4fff979, 0xb4003c59, 0xb5000012, -+ 0xb5fff912, 0xb5003bf2, 0x10000008, 0x10fff8a8, -+ 0x10003b88, 0x9000000f, 0x36700012, 0x3677f832, -+ 0x36703b12, 0x37780019, 0x377ff7d9, 0x37783ab9, -+ 0x12a203d2, 0x5286b21e, 0x72a66d35, 0x92eded92, -+ 0xd2eefecd, 0xf2ef69a3, 0x93400c2a, 0x330562cc, -+ 0x530b2071, 0x934b3860, 0xb3473cdc, 0xd3416549, -+ 0x13995f75, 0x93d6462e, 0x54000000, 0x54fff5a0, - 0x54003880, 0x54000001, 0x54fff541, 0x54003821, - 0x54000002, 0x54fff4e2, 0x540037c2, 0x54000002, - 0x54fff482, 0x54003762, 0x54000003, 0x54fff423, -@@ -1336,77 +1336,77 @@ Disassembly of section .text: - 0x5400000c, 0x54fff06c, 0x5400334c, 0x5400000d, - 0x54fff00d, 0x540032ed, 0x5400000e, 0x54ffefae, - 0x5400328e, 0x5400000f, 0x54ffef4f, 0x5400322f, -- 0xd40ac601, 0xd40042a2, 0xd404dac3, 0xd4224d40, -- 0xd44219c0, 0xd503201f, 0xd69f03e0, 0xd6bf03e0, -- 0xd5033fdf, 0xd503339f, 0xd50335bf, 0xd61f0280, -- 0xd63f0040, 0xc8127c17, 0xc81efec5, 0xc85f7d05, -- 0xc85ffe14, 0xc89ffd66, 0xc8dfff66, 0x880a7cb1, -- 0x8816fd89, 0x885f7d1b, 0x885ffc57, 0x889fffba, -- 0x88dffd4d, 0x48197f7c, 0x481dfd96, 0x485f7f96, -- 0x485fffc3, 0x489ffdf8, 0x48dfff5b, 0x080b7e6a, -- 0x0817fedb, 0x085f7e18, 0x085ffc38, 0x089fffa5, -- 0x08dffe18, 0xc87f6239, 0xc87fb276, 0xc820573a, -- 0xc821aca6, 0x887f388d, 0x887f88d1, 0x882f2643, -- 0x88329131, 0xf81cf2b7, 0xb803f055, 0x39002f9b, -- 0x781f31fd, 0xf85d33ce, 0xb843539d, 0x39401f54, -- 0x785ce059, 0x389f1143, 0x788131ee, 0x78dfb17d, -- 0xb89b90af, 0xfc403193, 0xbc42a36c, 0xfc07d396, -- 0xbc1ec1f8, 0xf81e8f88, 0xb8025de6, 0x38007c27, -- 0x7801ee20, 0xf8454fb9, 0xb85cce9a, 0x385e7fba, -- 0x7841af24, 0x389ebd1c, 0x789fadd1, 0x78c0aefc, -- 0xb89c0f7e, 0xfc50efd4, 0xbc414f71, 0xfc011c67, -- 0xbc1f0d6d, 0xf81c3526, 0xb81e34b0, 0x3800f7bd, -- 0x78012684, 0xf842e653, 0xb8417456, 0x385e2467, -- 0x785e358b, 0x389e34c8, 0x788046f8, 0x78c00611, -- 0xb89f8680, 0xfc582454, 0xbc5987d3, 0xfc076624, -- 0xbc190675, 0xf833785a, 0xb82fd809, 0x3821799a, -- 0x782a7975, 0xf870eaf0, 0xb871d96a, 0x386b7aed, -- 0x7875689b, 0x38afd91a, 0x78a2c955, 0x78ee6bc8, -- 0xb8b4f9dd, 0xfc76eb7e, 0xbc76692d, 0xfc31db28, -- 0xbc255b01, 0xf91c52aa, 0xb91c3fb2, 0x391f8877, -- 0x791ac97c, 0xf95c1758, 0xb95b3c55, 0x395ce0a4, -- 0x795851ce, 0x399e9f64, 0x79993764, 0x79d9af8a, -- 0xb99eea2a, 0xfd5a2f8d, 0xbd5dac78, 0xfd1e0182, -- 0xbd195c31, 0x58000010, 0x1800000d, 0xf8981240, -- 0xd8ffdf00, 0xf8a27a80, 0xf99af920, 0x1a0202e8, -- 0x3a130078, 0x5a1d0316, 0x7a03036c, 0x9a0102eb, -- 0xba1700bd, 0xda0c0329, 0xfa16000c, 0x0b23459a, -- 0x2b328a14, 0xcb274bde, 0x6b222eab, 0x8b214b42, -- 0xab34a7b2, 0xcb24520e, 0xeb378e20, 0x3a565283, -- 0x7a420321, 0xba58c247, 0xfa4d5106, 0x3a426924, -- 0x7a5b0847, 0xba413a02, 0xfa5fba23, 0x1a979377, -- 0x1a86640a, 0x5a89300b, 0x5a923771, 0x9a8b720c, -- 0x9a868786, 0xda9a736d, 0xda9256dd, 0x5ac0026c, -- 0x5ac00657, 0x5ac00b89, 0x5ac01262, 0x5ac017b9, -- 0xdac002e4, 0xdac0065d, 0xdac00907, 0xdac00e2d, -- 0xdac01011, 0xdac01752, 0x1ad0098b, 0x1ac70d24, -- 0x1ad020ec, 0x1ad72613, 0x1ac62887, 0x1ad72e95, -- 0x9adc0990, 0x9acd0d84, 0x9ac721a9, 0x9acf277c, -- 0x9ace2bd4, 0x9ade2e4e, 0x9bc77d63, 0x9b587e97, -- 0x1b1524a2, 0x1b04a318, 0x9b0f4d8b, 0x9b0ce73d, -- 0x9b2c5971, 0x9b34c87c, 0x9bbc6887, 0x9bb19556, -- 0x1e310871, 0x1e261a2b, 0x1e2928fd, 0x1e333987, -- 0x1e230ae0, 0x1e75087a, 0x1e651a60, 0x1e692b40, -- 0x1e753ab9, 0x1e7309b0, 0x1f00425d, 0x1f1d95b7, -- 0x1f2a38e9, 0x1f2f5f99, 0x1f5545a6, 0x1f429ea3, -- 0x1f65472a, 0x1f7449ce, 0x1e20404f, 0x1e20c0f2, -- 0x1e2140c3, 0x1e21c02c, 0x1e22c009, 0x1e6040a4, -- 0x1e60c1e3, 0x1e614331, 0x1e61c30c, 0x1e6240b5, -- 0x1e3802a4, 0x9e38007b, 0x1e78011d, 0x9e7802a9, -- 0x1e2203b4, 0x9e220107, 0x1e6202ac, 0x9e6202b0, -- 0x1e2600b2, 0x9e660119, 0x1e270352, 0x9e670160, -- 0x1e262200, 0x1e7d2200, 0x1e2023c8, 0x1e602128, -- 0x293e119b, 0x294a2543, 0x69480c70, 0xa934726a, -- 0xa97448f3, 0x298243ca, 0x29e21242, 0x69c64db8, -- 0xa9800311, 0xa9f4686e, 0x288a0416, 0x28fe2812, -- 0x68fe62d8, 0xa885308c, 0xa8f12664, 0x282468d2, -- 0x284e5035, 0xa8327699, 0xa84716e1, 0x0c407284, -- 0x4cdfa158, 0x0ccf6cd8, 0x4cdf2483, 0x0d40c0c2, -- 0x4ddfc9cd, 0x0dd8ceaf, 0x4c408ea9, 0x0cdf86bd, -- 0x4d60c1c8, 0x0dffca87, 0x4de3cc7c, 0x4cdd497b, -- 0x0c404950, 0x4d40e595, 0x4ddfeba4, 0x0dd3ed38, -- 0x4cdf046a, 0x0cc9039b, 0x0d60e3d5, 0x0dffe5d7, -- 0x0df4e9a4, 0xba5fd3e3, 0x3a5f03e5, 0xfa411be4, -+ 0xd40f9ca1, 0xd4008b22, 0xd40be1c3, 0xd423d0e0, -+ 0xd44dee20, 0xd503201f, 0xd69f03e0, 0xd6bf03e0, -+ 0xd5033fdf, 0xd503359f, 0xd50337bf, 0xd61f0380, -+ 0xd63f0220, 0xc8127f47, 0xc819fccc, 0xc85f7e00, -+ 0xc85ffc66, 0xc89ffc2e, 0xc8dfff1d, 0x881c7eef, -+ 0x8809fc67, 0x885f7e81, 0x885ffdf4, 0x889ffd35, -+ 0x88dffe25, 0x480d7fd4, 0x480afe4c, 0x485f7e64, -+ 0x485ffd56, 0x489ffdfe, 0x48dfff04, 0x080a7d94, -+ 0x0814fd7d, 0x085f7cb5, 0x085ffd24, 0x089fff9e, -+ 0x08dfff13, 0xc87f424b, 0xc87f9de8, 0xc83c4154, -+ 0xc827d469, 0x887f1a79, 0x887fa45e, 0x88305180, -+ 0x88259f82, 0xf81b5270, 0xb801e381, 0x381e61bc, -+ 0x781cd0c8, 0xf851d380, 0xb85e615c, 0x39403164, -+ 0x78405221, 0x3980312b, 0x789ef108, 0x78ddd1b4, -+ 0xb8831137, 0xfc41d089, 0xbd402a6b, 0xfc1d5299, -+ 0xbc1b0039, 0xf8019c14, 0xb81cfd8c, 0x381f6e7c, -+ 0x781c1f8d, 0xf85d2eeb, 0xb8411f1b, 0x385f4f4e, -+ 0x785d3ed8, 0x389f5d39, 0x7881dcc5, 0x78dffee7, -+ 0xb89c3dba, 0xfc50bf18, 0xbc5c9f34, 0xfc135c49, -+ 0xbc1c5c2e, 0xf806d433, 0xb81ca4a4, 0x3800947d, -+ 0x781ce420, 0xf85d04c2, 0xb858d4cf, 0x385e5444, -+ 0x785eb751, 0x389f3715, 0x789d04d6, 0x78dd04cb, -+ 0xb89fb7ce, 0xfc5975e2, 0xbc5a5679, 0xfc1416ed, -+ 0xbc0006b6, 0xf832c996, 0xb82c4b7e, 0x38367887, -+ 0x783dfaf3, 0xf87bf891, 0xb871c9a1, 0x387dfb70, -+ 0x78645939, 0x38b67984, 0x78a55839, 0x78fc6a09, -+ 0xb8aee8e8, 0xfc705b84, 0xbc7bd850, 0xfc396817, -+ 0xbc277a06, 0xf91ddd82, 0xb91b10a8, 0x391f8221, -+ 0x79197728, 0xf95ca07c, 0xb95b5d75, 0x395dc8af, -+ 0x795caa60, 0x399dd53d, 0x799c7397, 0x79dcb15b, -+ 0xb99e3b75, 0xfd5c7f7a, 0xbd5d2882, 0xfd1fb2a1, -+ 0xbd1d82c4, 0x58000001, 0x1800001b, 0xf882d080, -+ 0xd8000000, 0xf8a0cbc0, 0xf99fab00, 0x1a1803a0, -+ 0x3a120396, 0x5a1e0217, 0x7a0e03a7, 0x9a0e0196, -+ 0xba17031d, 0xda160391, 0xfa130298, 0x0b26cadb, -+ 0x2b38516d, 0xcb242d10, 0x6b34ea55, 0x8b3d0a2e, -+ 0xab2eb231, 0xcb3ac476, 0xeb3531ad, 0x3a5a722f, -+ 0x7a463325, 0xba5e9021, 0xfa47a222, 0x3a590a26, -+ 0x7a450845, 0xba514a6a, 0xfa48c9c3, 0x1a8e9109, -+ 0x1a85d57b, 0x5a9632eb, 0x5a9b2793, 0x9a815130, -+ 0x9a8c05dc, 0xda8e5096, 0xda9b257a, 0x5ac00178, -+ 0x5ac005ca, 0x5ac008a9, 0x5ac01292, 0x5ac01519, -+ 0xdac00316, 0xdac0077c, 0xdac00ba8, 0xdac00d51, -+ 0xdac01177, 0xdac015da, 0x1adc0895, 0x1ad60d5e, -+ 0x1ada205d, 0x1aca26dc, 0x1acc2b0b, 0x1ad02fd5, -+ 0x9acd0801, 0x9ac60e22, 0x9ad5230a, 0x9ac62525, -+ 0x9ac42b60, 0x9ac22c9c, 0x9bc77fc1, 0x9b4a7cbe, -+ 0x1b0d45e7, 0x1b0cf039, 0x9b1e2562, 0x9b03dae5, -+ 0x9b291159, 0x9b27c905, 0x9bba64b8, 0x9bbaf02e, -+ 0x1e280ad8, 0x1e261870, 0x1e392ab0, 0x1e3b3b40, -+ 0x1e310878, 0x1e660909, 0x1e7e1a76, 0x1e632a2e, -+ 0x1e743b78, 0x1e76082c, 0x1f0b7510, 0x1f128676, -+ 0x1f38270f, 0x1f2d5e7b, 0x1f503003, 0x1f52a873, -+ 0x1f6b5041, 0x1f79392c, 0x1e2042e0, 0x1e20c0d7, -+ 0x1e214084, 0x1e21c385, 0x1e22c1f5, 0x1e6040ab, -+ 0x1e60c092, 0x1e61418b, 0x1e61c10f, 0x1e624048, -+ 0x1e380253, 0x9e380011, 0x1e7801a0, 0x9e780136, -+ 0x1e2203a6, 0x9e2201cc, 0x1e6202d0, 0x9e6200ae, -+ 0x1e260007, 0x9e6600dc, 0x1e270342, 0x9e670004, -+ 0x1e2b2020, 0x1e7520c0, 0x1e202208, 0x1e6022c8, -+ 0x290c0045, 0x2978766e, 0x696c0c6f, 0xa9323767, -+ 0xa9483831, 0x29905895, 0x29f43451, 0x69ee66f5, -+ 0xa9bf41e4, 0xa9f6573d, 0x288a4758, 0x28e27bc3, -+ 0x68fc4fc3, 0xa8b70779, 0xa8fc539a, 0x283a653d, -+ 0x28703a79, 0xa8025879, 0xa8734ba9, 0x0c407275, -+ 0x4cdfa29b, 0x0cc66ec5, 0x4cdf2596, 0x0d40c131, -+ 0x4ddfcaa5, 0x0dd2cf8a, 0x4c408dfa, 0x0cdf8750, -+ 0x4d60c04e, 0x0dffcb92, 0x4df6cc13, 0x4cd24850, -+ 0x0c404818, 0x4d40e604, 0x4ddfe825, 0x0dd0ed47, -+ 0x4cdf0696, 0x0cd9008f, 0x0d60e0a0, 0x0dffe420, -+ 0x0deeeb9e, 0xba5fd3e3, 0x3a5f03e5, 0xfa411be4, +- 0x8b18ec0f, 0xcb9636d1, 0xab1ce74a, 0xeb184a19, +- 0x0b1c1ca8, 0x4b817388, 0x2b01004c, 0x6b5164b7, +- 0x8a0d5595, 0xaa9791f5, 0xca9bc316, 0xea82d1f6, +- 0x0a980e21, 0x2a862c45, 0x4a453037, 0x6a8e5180, +- 0x8a621cc1, 0xaa24bd1e, 0xcab4d6d1, 0xeaa591fd, +- 0x0a7d6efe, 0x2a2253ac, 0x4aa61187, 0x6aa755b0, +- 0x110b5a25, 0x31056e0a, 0x510f48ba, 0x710ac715, +- 0x910f6e0a, 0xb10a65ef, 0xd1009e98, 0xf10131aa, +- 0x121d4e67, 0x32043e25, 0x52132390, 0x72160b0e, +- 0x9273e76e, 0xb256416c, 0xd24b5002, 0xf266da8d, +- 0x14000000, 0x17ffffd7, 0x140001ee, 0x94000000, +- 0x97ffffd4, 0x940001eb, 0x3400000f, 0x34fffa2f, +- 0x34003d0f, 0x3500001c, 0x35fff9dc, 0x35003cbc, +- 0xb400001b, 0xb4fff97b, 0xb4003c5b, 0xb5000000, +- 0xb5fff900, 0xb5003be0, 0x1000000d, 0x10fff8ad, +- 0x10003b8d, 0x90000003, 0x36380015, 0x363ff835, +- 0x36383b15, 0x3748000f, 0x374ff7cf, 0x37483aaf, +- 0x12a14bee, 0x5283bb51, 0x72858ebb, 0x92c98881, +- 0xd2aa50d4, 0xf2afd9d4, 0x935c504d, 0x33133e90, +- 0x5309196b, 0x93595482, 0xb3424e0d, 0xd3481728, +- 0x138a3b7d, 0x93c66286, 0x54000000, 0x54fff5a0, +- 0x54003880, 0x54000001, 0x54fff541, 0x54003821, +- 0x54000002, 0x54fff4e2, 0x540037c2, 0x54000002, +- 0x54fff482, 0x54003762, 0x54000003, 0x54fff423, +- 0x54003703, 0x54000003, 0x54fff3c3, 0x540036a3, +- 0x54000004, 0x54fff364, 0x54003644, 0x54000005, +- 0x54fff305, 0x540035e5, 0x54000006, 0x54fff2a6, +- 0x54003586, 0x54000007, 0x54fff247, 0x54003527, +- 0x54000008, 0x54fff1e8, 0x540034c8, 0x54000009, +- 0x54fff189, 0x54003469, 0x5400000a, 0x54fff12a, +- 0x5400340a, 0x5400000b, 0x54fff0cb, 0x540033ab, +- 0x5400000c, 0x54fff06c, 0x5400334c, 0x5400000d, +- 0x54fff00d, 0x540032ed, 0x5400000e, 0x54ffefae, +- 0x5400328e, 0x5400000f, 0x54ffef4f, 0x5400322f, +- 0xd40d2881, 0xd40ea5c2, 0xd40518a3, 0xd42eca40, +- 0xd44a2e60, 0xd503201f, 0xd69f03e0, 0xd6bf03e0, +- 0xd5033fdf, 0xd5033d9f, 0xd5033bbf, 0xd61f0120, +- 0xd63f0120, 0xc8027d7d, 0xc816ff85, 0xc85f7e8e, +- 0xc85ffe7d, 0xc89ffea6, 0xc8dffc73, 0x880c7f63, +- 0x8811fdfa, 0x885f7dcd, 0x885fff4c, 0x889ffe28, +- 0x88dfffd5, 0x48007d6f, 0x4811fc34, 0x485f7d1d, +- 0x485ffd91, 0x489ffc8b, 0x48dffc90, 0x080e7c85, +- 0x081bfe11, 0x085f7f66, 0x085fff1b, 0x089ffe8a, +- 0x08dfff49, 0xc87f7b85, 0xc87fa66a, 0xc82b5590, +- 0xc82adc94, 0x887f0416, 0x887f8503, 0x88205fc9, +- 0x8837c560, 0xf81e1146, 0xb81fb007, 0x381f3205, +- 0x7801f27e, 0xf8477130, 0xb843b208, 0x385f918a, +- 0x785da12e, 0x389f83d8, 0x78817087, 0x78dd91d1, +- 0xb89e136b, 0xfc4410ec, 0xbc5fe200, 0xfc15f2ed, +- 0xbc1c2075, 0xf8064ca2, 0xb81a4c29, 0x381fbfdb, +- 0x7800cdfb, 0xf852ce24, 0xb841eef5, 0x385f9e2d, +- 0x785cec19, 0x389ebea1, 0x789caebc, 0x78c02c8b, +- 0xb883dd31, 0xfc427e7d, 0xbc5abed6, 0xfc11ff29, +- 0xbc1f1c49, 0xf81be6ed, 0xb800a611, 0x381e05c1, +- 0x78006411, 0xf855473b, 0xb85da72d, 0x385e372b, +- 0x784144be, 0x389f94e9, 0x789c2460, 0x78c1f5c7, +- 0xb8827771, 0xfc515491, 0xbc4226ba, 0xfc1c7625, +- 0xbc1935ad, 0xf824da06, 0xb834db09, 0x38237ba3, +- 0x783e6a2a, 0xf867497b, 0xb87949ee, 0x387379d8, +- 0x7866c810, 0x38acd98a, 0x78b0499a, 0x78ee781a, +- 0xb8bbf971, 0xfc73d803, 0xbc6979fa, 0xfc30e9ab, +- 0xbc355a7a, 0xf91886a8, 0xb918ef6a, 0x391b15db, +- 0x791ac0f0, 0xf958753b, 0xb95a1958, 0x395b3f18, +- 0x795800b4, 0x39988891, 0x799a81ae, 0x79dd172a, +- 0xb9981342, 0xfd5d21da, 0xbd5e7c9c, 0xfd1b526e, +- 0xbd18df97, 0x58002268, 0x18ffdf51, 0xf8951080, +- 0xd8000000, 0xf8a4c900, 0xf999e180, 0x1a150374, +- 0x3a060227, 0x5a1900c5, 0x7a0e017e, 0x9a0b0223, +- 0xba110159, 0xda170207, 0xfa050144, 0x0b2973c9, +- 0x2b30a8a0, 0xcb3b8baf, 0x6b21f12b, 0x8b264f02, +- 0xab3a70d3, 0xcb39ef48, 0xeb29329a, 0x3a5a41a7, +- 0x7a54310f, 0xba4302c8, 0xfa58a04a, 0x3a50490d, +- 0x7a4c0a01, 0xba5f79e3, 0xfa4c0aef, 0x1a9a30ee, +- 0x1a9ed763, 0x5a9702ab, 0x5a95c7da, 0x9a8d835c, +- 0x9a909471, 0xda8380ab, 0xda93c461, 0x5ac00120, +- 0x5ac005da, 0x5ac00a2d, 0x5ac0128b, 0x5ac0163c, +- 0xdac0008d, 0xdac007c1, 0xdac009cd, 0xdac00d05, +- 0xdac01322, 0xdac01514, 0x1adb0b35, 0x1ad00d4d, +- 0x1ad1203c, 0x1aca26f9, 0x1ac72867, 0x1ace2fce, +- 0x9acf0acc, 0x9acd0f22, 0x9ad522e7, 0x9ac0258b, +- 0x9adc293e, 0x9ad62cad, 0x9bc47ea5, 0x9b477c51, +- 0x1b11318c, 0x1b01edfe, 0x9b117662, 0x9b03fae4, +- 0x9b313eef, 0x9b21b59b, 0x9bac45a6, 0x9ba6a839, +- 0x1e240871, 0x1e3518b0, 0x1e312b63, 0x1e2f3959, +- 0x1e200a2a, 0x1e630b5c, 0x1e7b1804, 0x1e6229dc, +- 0x1e773b4c, 0x1e610bcf, 0x1f0534a4, 0x1f1c85b5, +- 0x1f3d1c71, 0x1f3d6b37, 0x1f5e68ee, 0x1f4aa4f6, +- 0x1f6e24e7, 0x1f6f630e, 0x1e204056, 0x1e20c060, +- 0x1e214229, 0x1e21c178, 0x1e22c32f, 0x1e604064, +- 0x1e60c2da, 0x1e61427e, 0x1e61c1cc, 0x1e6240f1, +- 0x1e3801d8, 0x9e38034d, 0x1e780022, 0x9e780165, +- 0x1e22026e, 0x9e2202c1, 0x1e62023b, 0x9e620136, +- 0x1e26006e, 0x9e66022c, 0x1e270368, 0x9e67039d, +- 0x1e3e2000, 0x1e692180, 0x1e202148, 0x1e602328, +- 0x292e7b68, 0x294a4f15, 0x69626c50, 0xa93814d5, +- 0xa97e679d, 0x29903408, 0x29ec5039, 0x69fc62ce, +- 0xa98504d1, 0xa9fc4735, 0x28b05691, 0x28c8705c, +- 0x68e07953, 0xa8bf3e31, 0xa8fe0331, 0x283c170e, +- 0x284e4c37, 0xa80419cb, 0xa8722f62, 0x0c407230, +- 0x4cdfa13d, 0x0cd56f1e, 0x4cdf2440, 0x0d40c134, +- 0x4ddfc811, 0x0ddaced5, 0x4c408f33, 0x0cdf84aa, +- 0x4d60c30a, 0x0dffcbad, 0x4de2cf96, 0x4ccb489e, +- 0x0c40481d, 0x4d40e777, 0x4ddfe943, 0x0dd6edd3, +- 0x4cdf040e, 0x0cd902de, 0x0d60e019, 0x0dffe50a, +- 0x0dfce8c1, 0xba5fd3e3, 0x3a5f03e5, 0xfa411be4, ++ 0x8b8e677b, 0xcb512964, 0xab998627, 0xeb9416cd, ++ 0x0b83438a, 0x4b463c55, 0x2b9b2406, 0x6b882b65, ++ 0x8a879c8c, 0xaa16cb75, 0xca80baa3, 0xea855955, ++ 0x0a1d5aad, 0x2a504951, 0x4a976cf0, 0x6a8c30ca, ++ 0x8a275b33, 0xaa27d459, 0xcab70ee9, 0xeaadc8c5, ++ 0x0a2a26af, 0x2abe06b1, 0x4a3d4f87, 0x6ab632d9, ++ 0x110c5346, 0x3107aa23, 0x5107eea5, 0x710dcf76, ++ 0x9103d10c, 0xb10e811d, 0xd10a087a, 0xf109d1fd, ++ 0x1209afd5, 0x32099d95, 0x5202c62b, 0x720897da, ++ 0x920e36f9, 0xb243f1de, 0xd263d09a, 0xf24fd01a, ++ 0x14000000, 0x17ffffd7, 0x1400023e, 0x94000000, ++ 0x97ffffd4, 0x9400023b, 0x3400001c, 0x34fffa3c, ++ 0x3400471c, 0x35000011, 0x35fff9d1, 0x350046b1, ++ 0xb4000019, 0xb4fff979, 0xb4004659, 0xb5000002, ++ 0xb5fff902, 0xb50045e2, 0x1000001d, 0x10fff8bd, ++ 0x1000459d, 0x9000001d, 0x36300006, 0x3637f826, ++ 0x36304506, 0x37100015, 0x3717f7d5, 0x371044b5, ++ 0x128155e8, 0x52a5762b, 0x72acb59a, 0x92866a8d, ++ 0xd2e2d8a6, 0xf2c54450, 0x93516bde, 0x330f3124, ++ 0x5301168f, 0x9353391b, 0xb355741e, 0xd3562f5b, ++ 0x13866d8c, 0x93d6b5b3, 0x54000000, 0x54fff5a0, ++ 0x54004280, 0x54000001, 0x54fff541, 0x54004221, ++ 0x54000002, 0x54fff4e2, 0x540041c2, 0x54000002, ++ 0x54fff482, 0x54004162, 0x54000003, 0x54fff423, ++ 0x54004103, 0x54000003, 0x54fff3c3, 0x540040a3, ++ 0x54000004, 0x54fff364, 0x54004044, 0x54000005, ++ 0x54fff305, 0x54003fe5, 0x54000006, 0x54fff2a6, ++ 0x54003f86, 0x54000007, 0x54fff247, 0x54003f27, ++ 0x54000008, 0x54fff1e8, 0x54003ec8, 0x54000009, ++ 0x54fff189, 0x54003e69, 0x5400000a, 0x54fff12a, ++ 0x54003e0a, 0x5400000b, 0x54fff0cb, 0x54003dab, ++ 0x5400000c, 0x54fff06c, 0x54003d4c, 0x5400000d, ++ 0x54fff00d, 0x54003ced, 0x5400000e, 0x54ffefae, ++ 0x54003c8e, 0x5400000f, 0x54ffef4f, 0x54003c2f, ++ 0xd407da81, 0xd402d542, 0xd406dae3, 0xd4258fa0, ++ 0xd44d5960, 0xd503201f, 0xd69f03e0, 0xd6bf03e0, ++ 0xd5033fdf, 0xd503339f, 0xd50336bf, 0xd61f0160, ++ 0xd63f0320, 0xc80e7daf, 0xc81efc39, 0xc85f7c6d, ++ 0xc85ffea8, 0xc89fff8d, 0xc8dfffc8, 0x880d7f91, ++ 0x8815fe71, 0x885f7d03, 0x885ffebd, 0x889fff09, ++ 0x88dffcc2, 0x480c7e14, 0x4802fcbc, 0x485f7c61, ++ 0x485ffdb8, 0x489fff2f, 0x48dffe8a, 0x08057db0, ++ 0x080afe2f, 0x085f7e71, 0x085ffd3e, 0x089fff14, ++ 0x08dffc8a, 0xc87f2139, 0xc87faa07, 0xc8392d30, ++ 0xc827a5e5, 0x887f106c, 0x887f88b1, 0x882460c8, ++ 0x8824e60c, 0xf800b3ce, 0xb819f3a6, 0x381f9162, ++ 0x781ea114, 0xf85e33b4, 0xb85e6009, 0x3940204e, ++ 0x785e802d, 0x389f922d, 0x789f50f1, 0x78dc4103, ++ 0xb9800d8e, 0xfc5152a5, 0xbc5ca009, 0xfc05f10f, ++ 0xbc1f0016, 0xf8111c97, 0xb8186c11, 0x381fbd3a, ++ 0x781f8dd5, 0xf8417ce8, 0xb8416d0c, 0x38406f9b, ++ 0x785c6e66, 0x389ecca7, 0x789e0e36, 0x78dfedb1, ++ 0xb8816c9d, 0xfc5b2f88, 0xbc5fbd77, 0xfc1e9e89, ++ 0xbc199c65, 0xf802044d, 0xb803967e, 0x3800343d, ++ 0x781ef74a, 0xf85f442f, 0xb85fa4a1, 0x385f25f8, ++ 0x785fb63d, 0x389ef5e4, 0x789ca446, 0x78c1277b, ++ 0xb89b3729, 0xfc5507b5, 0xbc5ce53e, 0xfc1d2582, ++ 0xbc1c56a7, 0xf837598c, 0xb8364bce, 0x383a586c, ++ 0x783e49cb, 0xf8787918, 0xb87469ac, 0x38655896, ++ 0x786658bc, 0x38b97962, 0x78b9ead7, 0x78f6da83, ++ 0xb8aefba9, 0xfc7dfaf0, 0xbc747b87, 0xfc387a94, ++ 0xbc377ab9, 0xf9180c51, 0xb91b38fe, 0x391ca4e3, ++ 0x791a4c27, 0xf95ca767, 0xb9580e28, 0x3958ea20, ++ 0x795bd680, 0x399a4633, 0x799d80d3, 0x79dcf944, ++ 0xb99b249d, 0xfd5a143d, 0xbd59938f, 0xfd1b9347, ++ 0xbd1aa7c0, 0x58000019, 0x18000009, 0xf88692c0, ++ 0xd8ffdf00, 0xf8be7b80, 0xf99c8260, 0x1a180111, ++ 0x3a09022e, 0x5a190036, 0x7a13012f, 0x9a0b028f, ++ 0xba1e0164, 0xda060114, 0xfa0f02aa, 0x0b298d61, ++ 0x2b3cee24, 0xcb3ca7b5, 0x6b37d38b, 0x8b25f34c, ++ 0xab3e68d1, 0xcb210a87, 0xeb3eed3e, 0x3a4b0087, ++ 0x7a4571eb, 0xba5122e6, 0xfa4bc16a, 0x3a4519cc, ++ 0x7a5c1aef, 0xba5e3a27, 0xfa4c8bc0, 0x1a81537a, ++ 0x1a95d56e, 0x5a8f60de, 0x5a995451, 0x9a8780b0, ++ 0x9a9cc68a, 0xda8180e6, 0xda912756, 0x5ac000cb, ++ 0x5ac00760, 0x5ac00ba1, 0x5ac012b4, 0x5ac0158c, ++ 0xdac00278, 0xdac005f7, 0xdac00831, 0xdac00c7b, ++ 0xdac010be, 0xdac0140f, 0x1ad4080e, 0x1ad50d9b, ++ 0x1ada214c, 0x1ac6266e, 0x1ade2a7b, 0x1ad02dc6, ++ 0x9ac209b1, 0x9ac20fa0, 0x9ac2220c, 0x9add26e9, ++ 0x9add2a26, 0x9ada2fce, 0x9bda7f11, 0x9b4e7f54, ++ 0x1b021d1b, 0x1b19b1bc, 0x9b0a6d24, 0x9b08f956, ++ 0x9b391694, 0x9b2beed6, 0x9bac4cc4, 0x9ba881f1, ++ 0x1e2a08b6, 0x1e301904, 0x1e262919, 0x1e393b66, ++ 0x1e290aea, 0x1e6c0a36, 0x1e74180b, 0x1e6f2980, ++ 0x1e643acf, 0x1e79083d, 0x1f131769, 0x1f06e87a, ++ 0x1f285184, 0x1f354539, 0x1f5e5867, 0x1f4aab61, ++ 0x1f760511, 0x1f626f8e, 0x1e2043db, 0x1e20c025, ++ 0x1e214277, 0x1e21c23c, 0x1e22c0d9, 0x1e6041d4, ++ 0x1e60c151, 0x1e61422a, 0x1e61c235, 0x1e6241f5, ++ 0x1e380167, 0x9e3803a2, 0x1e780323, 0x9e78011c, ++ 0x1e22006b, 0x9e2202a2, 0x1e62033d, 0x9e620073, ++ 0x1e2603b4, 0x9e660237, 0x1e270380, 0x9e670289, ++ 0x1e2c20e0, 0x1e6e21a0, 0x1e202188, 0x1e602028, ++ 0x29380acc, 0x2966271b, 0x696a130f, 0xa9015405, ++ 0xa9735d26, 0x29820fa0, 0x29ee403d, 0x69c24ebb, ++ 0xa9b545a6, 0xa9c16020, 0x288052c0, 0x28fa31d1, ++ 0x68ce682a, 0xa8ba61b4, 0xa8c330e1, 0x28362ae5, ++ 0x287a2b08, 0xa8043d6b, 0xa84470a9, 0x0c40728b, ++ 0x4cdfa113, 0x0cc36c43, 0x4cdf2475, 0x0d40c0ae, ++ 0x4ddfcb6d, 0x0dc0ce71, 0x4c408cbb, 0x0cdf849a, ++ 0x4d60c2e8, 0x0dffc94e, 0x4df3ceaa, 0x4cde49d1, ++ 0x0c404a94, 0x4d40e6b8, 0x4ddfe83a, 0x0dc0ec4c, ++ 0x4cdf04d5, 0x0cd60391, 0x0d60e333, 0x0dffe6e6, ++ 0x0dfae928, 0xba5fd3e3, 0x3a5f03e5, 0xfa411be4, 0x7a42cbe2, 0x93df03ff, 0xc820ffff, 0x8822fc7f, 0xc8247cbf, 0x88267fff, 0x4e010fe0, 0x4e081fe1, 0x4e0c1fe1, 0x4e0a1fe1, 0x4e071fe1, 0x4cc0ac3f, -@@ -1418,24 +1418,24 @@ Disassembly of section .text: - 0x1e741000, 0x1e743000, 0x1e761000, 0x1e763000, - 0x1e781000, 0x1e783000, 0x1e7a1000, 0x1e7a3000, - 0x1e7c1000, 0x1e7c3000, 0x1e7e1000, 0x1e7e3000, -- 0xf8358305, 0xf82d01ed, 0xf8361353, 0xf839234a, -- 0xf82531fb, 0xf8335165, 0xf83a4080, 0xf83673d7, -- 0xf832611c, 0xf8ad837d, 0xf8ab01a5, 0xf8a112b8, -- 0xf8bb2311, 0xf8b230be, 0xf8a75336, 0xf8a4427a, -- 0xf8a6707e, 0xf8b860b7, 0xf8f88392, 0xf8f300ff, -- 0xf8ed1386, 0xf8e822af, 0xf8e2302d, 0xf8f1533d, -- 0xf8f941d2, 0xf8ff7366, 0xf8f061e5, 0xf86b8072, -- 0xf87a0054, 0xf86b1164, 0xf87e22f3, 0xf86331cf, -- 0xf87e5296, 0xf8674305, 0xf87771f0, 0xf86b6013, -- 0xb83c803c, 0xb82b0195, 0xb83d1240, 0xb8252320, -- 0xb82e3340, 0xb83c53b2, 0xb82f43a1, 0xb828739a, -- 0xb831608e, 0xb8b88039, 0xb8aa0231, 0xb8bd12b4, -- 0xb8bd2189, 0xb8ab30a6, 0xb8b552a7, 0xb8aa4197, -- 0xb8b57145, 0xb8be6254, 0xb8ed80b7, 0xb8ef00b8, -- 0xb8e9132a, 0xb8f42231, 0xb8ec33d2, 0xb8e35323, -- 0xb8fa4159, 0xb8e273eb, 0xb8e760a2, 0xb8608287, -- 0xb865005f, 0xb87b1379, 0xb87e2358, 0xb86f32c2, -- 0xb86053e3, 0xb86f4154, 0xb87671d5, 0xb866605e, -+ 0xf83a8229, 0xf83c0057, 0xf8361062, 0xf82b23d9, -+ 0xf836309c, 0xf826530b, 0xf82c43ff, 0xf837713e, -+ 0xf8266281, 0xf8b182c2, 0xf8ae015b, 0xf8a6127e, -+ 0xf8a02179, 0xf8b733c0, 0xf8b55143, 0xf8af4016, -+ 0xf8b17280, 0xf8b0602d, 0xf8fb82ef, 0xf8f3003e, -+ 0xf8ef12fc, 0xf8e7226f, 0xf8eb314c, 0xf8e65187, -+ 0xf8fc41a5, 0xf8e97234, 0xf8f56179, 0xf8738318, -+ 0xf86803da, 0xf8711112, 0xf8622063, 0xf87a3207, -+ 0xf87b50a6, 0xf8764280, 0xf86b705a, 0xf87e609d, -+ 0xb82480e5, 0xb82a005a, 0xb83b1370, 0xb83f2157, -+ 0xb82431a2, 0xb823506f, 0xb82340ca, 0xb828714b, -+ 0xb83d61be, 0xb8ab8291, 0xb8ba00d0, 0xb8b5102a, -+ 0xb8bd22ec, 0xb8bd3108, 0xb8ab51ca, 0xb8a442cd, -+ 0xb8a770ed, 0xb8ae63e0, 0xb8f18382, 0xb8f3014b, -+ 0xb8ec1293, 0xb8e02108, 0xb8f13303, 0xb8f950e5, -+ 0xb8f0413e, 0xb8ea71df, 0xb8f16173, 0xb87481a1, -+ 0xb87a028b, 0xb87213d8, 0xb86c2299, 0xb86e30bd, -+ 0xb862537a, 0xb879417b, 0xb86470fd, 0xb870615d, +- 0x1e601000, 0x1e603000, 0x1e621000, 0x1e623000, +- 0x1e641000, 0x1e643000, 0x1e661000, 0x1e663000, +- 0x1e681000, 0x1e683000, 0x1e6a1000, 0x1e6a3000, +- 0x1e6c1000, 0x1e6c3000, 0x1e6e1000, 0x1e6e3000, +- 0x1e701000, 0x1e703000, 0x1e721000, 0x1e723000, +- 0x1e741000, 0x1e743000, 0x1e761000, 0x1e763000, +- 0x1e781000, 0x1e783000, 0x1e7a1000, 0x1e7a3000, +- 0x1e7c1000, 0x1e7c3000, 0x1e7e1000, 0x1e7e3000, +- 0xf83081f4, 0xf8220387, 0xf834132a, 0xf836204b, +- 0xf821326a, 0xf82e5075, 0xf83c41bb, 0xf83172be, +- 0xf83b63b0, 0xf8be8009, 0xf8bc039b, 0xf8b51159, +- 0xf8bf21f4, 0xf8a131d9, 0xf8b553ba, 0xf8a8433d, +- 0xf8ad7322, 0xf8af6017, 0xf8e38041, 0xf8fc0283, +- 0xf8ee11df, 0xf8e7205c, 0xf8e030ab, 0xf8eb528e, +- 0xf8ff4044, 0xf8fa72c0, 0xf8f161a1, 0xf877829a, +- 0xf86e018b, 0xf86c11ff, 0xf87b210e, 0xf86a333e, +- 0xf8765207, 0xf8614110, 0xf8617341, 0xf86061f7, +- 0xb82b8110, 0xb82101c7, 0xb830113f, 0xb83621a6, +- 0xb82b308d, 0xb8305016, 0xb83c415f, 0xb8307105, +- 0xb83a61f4, 0xb8bb8206, 0xb8bf005f, 0xb8b8111c, +- 0xb8af22e9, 0xb8ba30e2, 0xb8a351f1, 0xb8b342a5, +- 0xb8a7719a, 0xb8ac63a7, 0xb8e98288, 0xb8e803df, +- 0xb8e01186, 0xb8f12057, 0xb8e0303e, 0xb8f651e3, +- 0xb8f941b5, 0xb8ed7378, 0xb8f46163, 0xb86382ad, +- 0xb87a034f, 0xb8691053, 0xb87820fd, 0xb87d31f9, +- 0xb86b50fe, 0xb86b40c2, 0xb87071cb, 0xb8656168, ++ 0x05a08020, 0x04b0e3e0, 0x0470e7e1, 0x042f9c20, ++ 0x043f9c35, 0x047f9c20, 0x04ff9c20, 0x04299420, ++ 0x04319160, 0x0461943e, 0x04a19020, 0x042053ff, ++ 0x047f5401, 0x25208028, 0x2538cfe0, 0x2578d001, ++ 0x25b8efe2, 0x25f8f007, 0xa400a3e0, 0xa4a8a7ea, ++ 0xa547a814, 0xa4084ffe, 0xa55c53e0, 0xa5e1540b, ++ 0xe400fbf6, 0xe408ffff, 0xe547e400, 0xe4014be0, ++ 0xe4a84fe0, 0xe5e85000, 0x858043e0, 0x85a043ff, ++ 0xe59f5d08, 0x1e601000, 0x1e603000, 0x1e621000, ++ 0x1e623000, 0x1e641000, 0x1e643000, 0x1e661000, ++ 0x1e663000, 0x1e681000, 0x1e683000, 0x1e6a1000, ++ 0x1e6a3000, 0x1e6c1000, 0x1e6c3000, 0x1e6e1000, ++ 0x1e6e3000, 0x1e701000, 0x1e703000, 0x1e721000, ++ 0x1e723000, 0x1e741000, 0x1e743000, 0x1e761000, ++ 0x1e763000, 0x1e781000, 0x1e783000, 0x1e7a1000, ++ 0x1e7a3000, 0x1e7c1000, 0x1e7c3000, 0x1e7e1000, ++ 0x1e7e3000, 0xf82b82af, 0xf83700a8, 0xf8271106, ++ 0xf82e22ee, 0xf82a3019, 0xf82552a9, 0xf824423b, ++ 0xf82a71a6, 0xf8236203, 0xf8a9805c, 0xf8b70022, ++ 0xf8a410fa, 0xf8a02143, 0xf8b83079, 0xf8ab5028, ++ 0xf8b043ad, 0xf8a670a0, 0xf8b061b1, 0xf8eb81db, ++ 0xf8e202ad, 0xf8f6119f, 0xf8e721fe, 0xf8e731f0, ++ 0xf8f051ba, 0xf8f74379, 0xf8e473ee, 0xf8f86221, ++ 0xf8628308, 0xf874027b, 0xf87310d1, 0xf86e235c, ++ 0xf8623270, 0xf86e5090, 0xf8794128, 0xf86a73a5, ++ 0xf86661c2, 0xb831808b, 0xb82701f0, 0xb82b1139, ++ 0xb823200e, 0xb820301e, 0xb826538a, 0xb82740ce, ++ 0xb826701e, 0xb83663be, 0xb8b0826e, 0xb8b50323, ++ 0xb8a21270, 0xb8ba22f4, 0xb8b133e6, 0xb8a553d7, ++ 0xb8ab41cc, 0xb8a271b4, 0xb8af6291, 0xb8e682fc, ++ 0xb8fb01b0, 0xb8e21317, 0xb8e0215c, 0xb8e330af, ++ 0xb8e353ab, 0xb8f640db, 0xb8f17214, 0xb8f760ef, ++ 0xb86881d0, 0xb87702f0, 0xb87c10ec, 0xb87c2267, ++ 0xb867316c, 0xb86a529f, 0xb86943e8, 0xb86a7048, ++ 0xb87163ff, 0x047600e2, 0x04be06de, 0x65d902ca, ++ 0x65cc0a17, 0x65d90623, 0x0496a099, 0x04401b57, ++ 0x04d08226, 0x04daac77, 0x04939d2b, 0x04919c7b, ++ 0x04901049, 0x0417a9f0, 0x04dea929, 0x048816ea, ++ 0x040a172d, 0x04811413, 0x04dca2d1, 0x65808a09, ++ 0x658d9411, 0x6586947d, 0x65878e21, 0x65c2880e, ++ 0x04ddb2d3, 0x65c2a5f1, 0x65c0b088, 0x65c1b3a5, ++ 0x65cda26b, 0x65c1938a, 0x65eb0ded, 0x65af3e86, ++ 0x65a749be, 0x65f379d6, 0x04404f3e, 0x04c16b0a, ++ 0x04363226, 0x04b1312a, 0x04753182, 0x049a39cf, ++ 0x04d82ce9, 0x0459353e, 0x04883347, 0x048a2fb4, ++ 0x65872e1c, 0x65c62d26, 0x6598346a, 0x04013915, }; // END Generated code -- do not edit +diff --git a/src/hotspot/cpu/aarch64/aarch64-asmtest.py b/src/hotspot/cpu/aarch64/aarch64-asmtest.py +index 31c6965b7..2211bd25a 100644 +--- a/src/hotspot/cpu/aarch64/aarch64-asmtest.py ++++ b/src/hotspot/cpu/aarch64/aarch64-asmtest.py +@@ -73,6 +73,48 @@ class GeneralRegisterOrSp(Register): + return self.astr() + else: + return self.astr("r") ++class SVEVectorRegister(FloatRegister): ++ def __str__(self): ++ return self.astr("z") ++ ++class SVEPRegister(Register): ++ def __str__(self): ++ return self.astr("p") ++ ++ def generate(self): ++ self.number = random.randint(0, 15) ++ return self ++ ++class SVEGoverningPRegister(Register): ++ def __str__(self): ++ return self.astr("p") ++ def generate(self): ++ self.number = random.randint(0, 7) ++ return self ++ ++class RegVariant(object): ++ def __init__(self, low, high): ++ self.number = random.randint(low, high) ++ ++ def astr(self): ++ nameMap = { ++ 0: ".b", ++ 1: ".h", ++ 2: ".s", ++ 3: ".d", ++ 4: ".q" ++ } ++ return nameMap.get(self.number) ++ ++ def cstr(self): ++ nameMap = { ++ 0: "__ B", ++ 1: "__ H", ++ 2: "__ S", ++ 3: "__ D", ++ 4: "__ Q" ++ } ++ return nameMap.get(self.number) + + class FloatZero(Operand): + +@@ -88,7 +130,10 @@ class OperandFactory: + 'w' : GeneralRegister, + 's' : FloatRegister, + 'd' : FloatRegister, +- 'z' : FloatZero} ++ 'z' : FloatZero, ++ 'p' : SVEPRegister, ++ 'P' : SVEGoverningPRegister, ++ 'Z' : SVEVectorRegister} + + @classmethod + def create(cls, mode): +@@ -834,6 +879,100 @@ class FloatInstruction(Instruction): + % tuple([Instruction.astr(self)] + + [(self.reg[i].astr(self.modes[i])) for i in range(self.numRegs)])) + ++class SVEVectorOp(Instruction): ++ def __init__(self, args): ++ name = args[0] ++ regTypes = args[1] ++ regs = [] ++ for c in regTypes: ++ regs.append(OperandFactory.create(c).generate()) ++ self.reg = regs ++ self.numRegs = len(regs) ++ if regTypes[0] != "p" and regTypes[1] == 'P': ++ self._isPredicated = True ++ self._merge = "/m" ++ else: ++ self._isPredicated = False ++ self._merge ="" ++ ++ self._bitwiseop = False ++ if name[0] == 'f': ++ self._width = RegVariant(2, 3) ++ elif not self._isPredicated and (name in ["and", "eor", "orr", "bic"]): ++ self._width = RegVariant(3, 3) ++ self._bitwiseop = True ++ else: ++ self._width = RegVariant(0, 3) ++ if len(args) > 2: ++ self._dnm = args[2] ++ else: ++ self._dnm = None ++ Instruction.__init__(self, name) ++ ++ def cstr(self): ++ formatStr = "%s%s" + ''.join([", %s" for i in range(0, self.numRegs)] + [");"]) ++ if self._bitwiseop: ++ width = [] ++ formatStr = "%s%s" + ''.join([", %s" for i in range(1, self.numRegs)] + [");"]) ++ else: ++ width = [self._width.cstr()] ++ return (formatStr ++ % tuple(["__ sve_" + self._name + "("] + ++ [str(self.reg[0])] + ++ width + ++ [str(self.reg[i]) for i in range(1, self.numRegs)])) ++ def astr(self): ++ formatStr = "%s%s" + ''.join([", %s" for i in range(1, self.numRegs)]) ++ if self._dnm == 'dn': ++ formatStr += ", %s" ++ dnReg = [str(self.reg[0]) + self._width.astr()] ++ else: ++ dnReg = [] ++ ++ if self._isPredicated: ++ restRegs = [str(self.reg[1]) + self._merge] + dnReg + [str(self.reg[i]) + self._width.astr() for i in range(2, self.numRegs)] ++ else: ++ restRegs = dnReg + [str(self.reg[i]) + self._width.astr() for i in range(1, self.numRegs)] ++ return (formatStr ++ % tuple([Instruction.astr(self)] + ++ [str(self.reg[0]) + self._width.astr()] + ++ restRegs)) ++ def generate(self): ++ return self ++ ++class SVEReductionOp(Instruction): ++ def __init__(self, args): ++ name = args[0] ++ lowRegType = args[1] ++ self.reg = [] ++ Instruction.__init__(self, name) ++ self.reg.append(OperandFactory.create('s').generate()) ++ self.reg.append(OperandFactory.create('P').generate()) ++ self.reg.append(OperandFactory.create('Z').generate()) ++ self._width = RegVariant(lowRegType, 3) ++ def cstr(self): ++ return "__ sve_%s(%s, %s, %s, %s);" % (self.name(), ++ str(self.reg[0]), ++ self._width.cstr(), ++ str(self.reg[1]), ++ str(self.reg[2])) ++ def astr(self): ++ if self.name() == "uaddv": ++ dstRegName = "d" + str(self.reg[0].number) ++ else: ++ dstRegName = self._width.astr()[1] + str(self.reg[0].number) ++ formatStr = "%s %s, %s, %s" ++ if self.name() == "fadda": ++ formatStr += ", %s" ++ moreReg = [dstRegName] ++ else: ++ moreReg = [] ++ return formatStr % tuple([self.name()] + ++ [dstRegName] + ++ [str(self.reg[1])] + ++ moreReg + ++ [str(self.reg[2]) + self._width.astr()]) ++ + class LdStSIMDOp(Instruction): + def __init__(self, args): + self._name, self.regnum, self.arrangement, self.addresskind = args +@@ -1120,7 +1259,42 @@ generate(SpecialCases, [["ccmn", "__ ccmn(zr, zr, 3u, Assembler::LE);", + ["mov", "__ mov(v1, __ T2S, 1, zr);", "mov\tv1.s[1], wzr"], + ["mov", "__ mov(v1, __ T4H, 2, zr);", "mov\tv1.h[2], wzr"], + ["mov", "__ mov(v1, __ T8B, 3, zr);", "mov\tv1.b[3], wzr"], +- ["ld1", "__ ld1(v31, v0, __ T2D, Address(__ post(r1, r0)));", "ld1\t{v31.2d, v0.2d}, [x1], x0"]]) ++ ["ld1", "__ ld1(v31, v0, __ T2D, Address(__ post(r1, r0)));", "ld1\t{v31.2d, v0.2d}, [x1], x0"], ++ # SVE instructions ++ ["cpy", "__ sve_cpy(z0, __ S, p0, v1);", "mov\tz0.s, p0/m, s1"], ++ ["inc", "__ sve_inc(r0, __ S);", "incw\tx0"], ++ ["dec", "__ sve_dec(r1, __ H);", "dech\tx1"], ++ ["lsl", "__ sve_lsl(z0, __ B, z1, 7);", "lsl\tz0.b, z1.b, #7"], ++ ["lsl", "__ sve_lsl(z21, __ H, z1, 15);", "lsl\tz21.h, z1.h, #15"], ++ ["lsl", "__ sve_lsl(z0, __ S, z1, 31);", "lsl\tz0.s, z1.s, #31"], ++ ["lsl", "__ sve_lsl(z0, __ D, z1, 63);", "lsl\tz0.d, z1.d, #63"], ++ ["lsr", "__ sve_lsr(z0, __ B, z1, 7);", "lsr\tz0.b, z1.b, #7"], ++ ["asr", "__ sve_asr(z0, __ H, z11, 15);", "asr\tz0.h, z11.h, #15"], ++ ["lsr", "__ sve_lsr(z30, __ S, z1, 31);", "lsr\tz30.s, z1.s, #31"], ++ ["asr", "__ sve_asr(z0, __ D, z1, 63);", "asr\tz0.d, z1.d, #63"], ++ ["addvl", "__ sve_addvl(sp, r0, 31);", "addvl\tsp, x0, #31"], ++ ["addpl", "__ sve_addpl(r1, sp, -32);", "addpl\tx1, sp, -32"], ++ ["cntp", "__ sve_cntp(r8, __ B, p0, p1);", "cntp\tx8, p0, p1.b"], ++ ["dup", "__ sve_dup(z0, __ B, 127);", "dup\tz0.b, 127"], ++ ["dup", "__ sve_dup(z1, __ H, -128);", "dup\tz1.h, -128"], ++ ["dup", "__ sve_dup(z2, __ S, 32512);", "dup\tz2.s, 32512"], ++ ["dup", "__ sve_dup(z7, __ D, -32768);", "dup\tz7.d, -32768"], ++ ["ld1b", "__ sve_ld1b(z0, __ B, p0, Address(sp));", "ld1b\t{z0.b}, p0/z, [sp]"], ++ ["ld1h", "__ sve_ld1h(z10, __ H, p1, Address(sp, -8));", "ld1h\t{z10.h}, p1/z, [sp, #-8, MUL VL]"], ++ ["ld1w", "__ sve_ld1w(z20, __ S, p2, Address(r0, 7));", "ld1w\t{z20.s}, p2/z, [x0, #7, MUL VL]"], ++ ["ld1b", "__ sve_ld1b(z30, __ B, p3, Address(sp, r8));", "ld1b\t{z30.b}, p3/z, [sp, x8]"], ++ ["ld1w", "__ sve_ld1w(z0, __ S, p4, Address(sp, r28));", "ld1w\t{z0.s}, p4/z, [sp, x28, LSL #2]"], ++ ["ld1d", "__ sve_ld1d(z11, __ D, p5, Address(r0, r1));", "ld1d\t{z11.d}, p5/z, [x0, x1, LSL #3]"], ++ ["st1b", "__ sve_st1b(z22, __ B, p6, Address(sp));", "st1b\t{z22.b}, p6, [sp]"], ++ ["st1b", "__ sve_st1b(z31, __ B, p7, Address(sp, -8));", "st1b\t{z31.b}, p7, [sp, #-8, MUL VL]"], ++ ["st1w", "__ sve_st1w(z0, __ S, p1, Address(r0, 7));", "st1w\t{z0.s}, p1, [x0, #7, MUL VL]"], ++ ["st1b", "__ sve_st1b(z0, __ B, p2, Address(sp, r1));", "st1b\t{z0.b}, p2, [sp, x1]"], ++ ["st1h", "__ sve_st1h(z0, __ H, p3, Address(sp, r8));", "st1h\t{z0.h}, p3, [sp, x8, LSL #1]"], ++ ["st1d", "__ sve_st1d(z0, __ D, p4, Address(r0, r8));", "st1d\t{z0.d}, p4, [x0, x8, LSL #3]"], ++ ["ldr", "__ sve_ldr(z0, Address(sp));", "ldr\tz0, [sp]"], ++ ["ldr", "__ sve_ldr(z31, Address(sp, -256));", "ldr\tz31, [sp, #-256, MUL VL]"], ++ ["str", "__ sve_str(z8, Address(r8, 255));", "str\tz8, [x8, #255, MUL VL]"], ++]) + + print "\n// FloatImmediateOp" + for float in ("2.0", "2.125", "4.0", "4.25", "8.0", "8.5", "16.0", "17.0", "0.125", +@@ -1145,6 +1319,50 @@ for size in ("x", "w"): + ["ldumin", "ldumin", size, suffix], + ["ldumax", "ldumax", size, suffix]]); + ++ ++generate(SVEVectorOp, [["add", "ZZZ"], ++ ["sub", "ZZZ"], ++ ["fadd", "ZZZ"], ++ ["fmul", "ZZZ"], ++ ["fsub", "ZZZ"], ++ ["abs", "ZPZ"], ++ ["add", "ZPZ", "dn"], ++ ["asr", "ZPZ", "dn"], ++ ["cnt", "ZPZ"], ++ ["lsl", "ZPZ", "dn"], ++ ["lsr", "ZPZ", "dn"], ++ ["mul", "ZPZ", "dn"], ++ ["neg", "ZPZ"], ++ ["not", "ZPZ"], ++ ["smax", "ZPZ", "dn"], ++ ["smin", "ZPZ", "dn"], ++ ["sub", "ZPZ", "dn"], ++ ["fabs", "ZPZ"], ++ ["fadd", "ZPZ", "dn"], ++ ["fdiv", "ZPZ", "dn"], ++ ["fmax", "ZPZ", "dn"], ++ ["fmin", "ZPZ", "dn"], ++ ["fmul", "ZPZ", "dn"], ++ ["fneg", "ZPZ"], ++ ["frintm", "ZPZ"], ++ ["frintn", "ZPZ"], ++ ["frintp", "ZPZ"], ++ ["fsqrt", "ZPZ"], ++ ["fsub", "ZPZ", "dn"], ++ ["fmla", "ZPZZ"], ++ ["fmls", "ZPZZ"], ++ ["fnmla", "ZPZZ"], ++ ["fnmls", "ZPZZ"], ++ ["mla", "ZPZZ"], ++ ["mls", "ZPZZ"], ++ ["and", "ZZZ"], ++ ["eor", "ZZZ"], ++ ["orr", "ZZZ"], ++ ]) ++ ++generate(SVEReductionOp, [["andv", 0], ["orv", 0], ["eorv", 0], ["smaxv", 0], ["sminv", 0], ++ ["fminv", 2], ["fmaxv", 2], ["fadda", 2], ["uaddv", 0]]) ++ + print "\n __ bind(forth);" + outfile.write("forth:\n") + +@@ -1153,8 +1372,8 @@ outfile.close() + import subprocess + import sys + +-# compile for 8.1 because of lse atomics +-subprocess.check_call([AARCH64_AS, "-march=armv8.1-a", "aarch64ops.s", "-o", "aarch64ops.o"]) ++# compile for sve with 8.1 and sha2 because of lse atomics and sha512 crypto extension. ++subprocess.check_call([AARCH64_AS, "-march=armv8.1-a+sha2+sve", "aarch64ops.s", "-o", "aarch64ops.o"]) + + print + print "/*", diff --git a/src/hotspot/cpu/aarch64/assembler_aarch64.hpp b/src/hotspot/cpu/aarch64/assembler_aarch64.hpp -index 0824ca393..dc2d5e2c9 100644 +index 6f4e75ff4..dc2d5e2c9 100644 --- a/src/hotspot/cpu/aarch64/assembler_aarch64.hpp +++ b/src/hotspot/cpu/aarch64/assembler_aarch64.hpp @@ -139,6 +139,9 @@ REGISTER_DECLARATION(Register, rdispatch, r21); @@ -5789,22 +5420,7 @@ index 0824ca393..dc2d5e2c9 100644 #define assert_cond(ARG1) assert(ARG1, #ARG1) namespace asm_util { -@@ -273,6 +276,14 @@ public: - f(r->encoding_nocheck(), lsb + 4, lsb); - } - -+ void prf(PRegister r, int lsb) { -+ f(r->encoding_nocheck(), lsb + 3, lsb); -+ } -+ -+ void pgrf(PRegister r, int lsb) { -+ f(r->encoding_nocheck(), lsb + 2, lsb); -+ } -+ - unsigned get(int msb = 31, int lsb = 0) { - int nbits = msb - lsb + 1; - unsigned mask = checked_cast(right_n_bits(nbits)) << lsb; -@@ -554,6 +565,18 @@ class Address { +@@ -562,6 +565,18 @@ class Address { void lea(MacroAssembler *, Register) const; static bool offset_ok_for_immed(int64_t offset, uint shift = 0); @@ -5823,20 +5439,7 @@ index 0824ca393..dc2d5e2c9 100644 }; // Convience classes -@@ -669,6 +692,12 @@ public: - void rf(FloatRegister reg, int lsb) { - current->rf(reg, lsb); - } -+ void prf(PRegister reg, int lsb) { -+ current->prf(reg, lsb); -+ } -+ void pgrf(PRegister reg, int lsb) { -+ current->pgrf(reg, lsb); -+ } - void fixed(unsigned value, unsigned mask) { - current->fixed(value, mask); - } -@@ -2431,13 +2460,18 @@ public: +@@ -2445,13 +2460,18 @@ public: f(sidx<<(int)T, 14, 11), f(1, 10), rf(Vn, 5), rf(Vd, 0); } @@ -5860,20 +5463,10 @@ index 0824ca393..dc2d5e2c9 100644 #define INSN(NAME, opc, opc2, isSHR) \ void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, int shift){ \ starti; \ -@@ -2670,13 +2704,299 @@ public: - #undef INSN +@@ -2693,6 +2713,240 @@ void ext(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister V + f(0, 10), rf(Vn, 5), rf(Vd, 0); + } - void ext(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm, int index) -- { -+{ -+ starti; -+ assert(T == T8B || T == T16B, "invalid arrangement"); -+ assert((T == T8B && index <= 0b0111) || (T == T16B && index <= 0b1111), "Invalid index value"); -+ f(0, 31), f((int)T & 1, 30), f(0b101110000, 29, 21); -+ rf(Vm, 16), f(0, 15), f(index, 14, 11); -+ f(0, 10), rf(Vn, 5), rf(Vd, 0); -+} -+ +// SVE arithmetics - unpredicated +#define INSN(NAME, opcode) \ + void NAME(FloatRegister Zd, SIMD_RegVariant T, FloatRegister Zn, FloatRegister Zm) { \ @@ -6108,19 +5701,13 @@ index 0824ca393..dc2d5e2c9 100644 + INSN(sve_addpl, 0b11); +#undef INSN + -+// SVE inc/dec register by element count -+#define INSN(NAME, op) \ -+ void NAME(Register Xdn, SIMD_RegVariant T, unsigned imm4 = 1, int pattern = 0b11111) { \ -+ starti; \ -+ assert(T != Q, "invalid size"); \ -+ f(0b00000100,31, 24), f(T, 23, 22), f(0b11, 21, 20); \ -+ f(imm4 - 1, 19, 16), f(0b11100, 15, 11), f(op, 10), f(pattern, 9, 5), rf(Xdn, 0); \ -+ } -+ -+ INSN(sve_inc, 0); -+ INSN(sve_dec, 1); -+#undef INSN -+ + // SVE inc/dec register by element count + #define INSN(NAME, op) \ + void NAME(Register Xdn, SIMD_RegVariant T, unsigned imm4 = 1, int pattern = 0b11111) { \ +@@ -2706,6 +2960,45 @@ void ext(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister V + INSN(sve_dec, 1); + #undef INSN + +// SVE predicate count + void sve_cntp(Register Xd, SIMD_RegVariant T, PRegister Pg, PRegister Pn) { + starti; @@ -6155,17 +5742,14 @@ index 0824ca393..dc2d5e2c9 100644 + } + + void sve_ptrue(PRegister pd, SIMD_RegVariant esize, int pattern = 0b11111) { - starti; -- assert(T == T8B || T == T16B, "invalid arrangement"); -- assert((T == T8B && index <= 0b0111) || (T == T16B && index <= 0b1111), "Invalid index value"); -- f(0, 31), f((int)T & 1, 30), f(0b101110000, 29, 21); -- rf(Vm, 16), f(0, 15), f(index, 14, 11); -- f(0, 10), rf(Vn, 5), rf(Vd, 0); ++ starti; + f(0b00100101, 31, 24), f(esize, 23, 22), f(0b011000111000, 21, 10); + f(pattern, 9, 5), f(0b0, 4), prf(pd, 0); ++ } ++ + Assembler(CodeBuffer* code) : AbstractAssembler(code) { } - Assembler(CodeBuffer* code) : AbstractAssembler(code) { diff --git a/src/hotspot/cpu/aarch64/gc/z/zBarrierSetAssembler_aarch64.cpp b/src/hotspot/cpu/aarch64/gc/z/zBarrierSetAssembler_aarch64.cpp index 6ac54f257..a258528ea 100644 --- a/src/hotspot/cpu/aarch64/gc/z/zBarrierSetAssembler_aarch64.cpp @@ -6184,32 +5768,10 @@ index 6ac54f257..a258528ea 100644 // Stub exit __ b(*stub->continuation()); } -diff --git a/src/hotspot/cpu/aarch64/globals_aarch64.hpp b/src/hotspot/cpu/aarch64/globals_aarch64.hpp -index 071845e5b..f26ea2a8b 100644 ---- a/src/hotspot/cpu/aarch64/globals_aarch64.hpp -+++ b/src/hotspot/cpu/aarch64/globals_aarch64.hpp -@@ -112,6 +112,9 @@ define_pd_global(intx, InlineSmallCode, 1000); - "Avoid generating unaligned memory accesses") \ - product(bool, UseLSE, false, \ - "Use LSE instructions") \ -+ product(uint, UseSVE, 0, \ -+ "Highest supported SVE instruction set version") \ -+ range(0, 2) \ - product(bool, UseBlockZeroing, true, \ - "Use DC ZVA for block zeroing") \ - product(intx, BlockZeroingLowLimit, 256, \ diff --git a/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp b/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp -index aecab30c1..b6b070e62 100644 +index 265cd0888..590fd8662 100644 --- a/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp -@@ -53,6 +53,7 @@ - #include "opto/compile.hpp" - #include "opto/intrinsicnode.hpp" - #include "opto/node.hpp" -+#include "opto/matcher.hpp" - #endif - - #ifdef PRODUCT @@ -2110,8 +2110,17 @@ int MacroAssembler::pop(unsigned int bitset, Register stack) { } @@ -6282,14 +5844,14 @@ index aecab30c1..b6b070e62 100644 if (count & 1) { ldrq(as_FloatRegister(regs[0]), Address(stack)); i += 1; -@@ -2630,23 +2668,39 @@ void MacroAssembler::pop_call_clobbered_registers() { - pop(RegSet::range(r0, r18) - RegSet::of(rscratch1, rscratch2), sp); +@@ -2638,23 +2676,39 @@ void MacroAssembler::pop_call_clobbered_registers() { + pop(call_clobbered_registers() - RegSet::of(rscratch1, rscratch2), sp); } -void MacroAssembler::push_CPU_state(bool save_vectors) { - int step = (save_vectors ? 8 : 4) * wordSize; +void MacroAssembler::push_CPU_state(bool save_vectors, bool use_sve, -+ int sve_vector_size_in_bytes) { ++ int sve_vector_size_in_bytes) { push(0x3fffffff, sp); // integer registers except lr & sp - mov(rscratch1, -step); - sub(sp, sp, step); @@ -6335,7 +5897,7 @@ index aecab30c1..b6b070e62 100644 pop(0x3fffffff, sp); // integer registers except lr & sp } -@@ -2695,6 +2749,21 @@ Address MacroAssembler::spill_address(int size, int offset, Register tmp) +@@ -2703,6 +2757,21 @@ Address MacroAssembler::spill_address(int size, int offset, Register tmp) return Address(base, offset); } @@ -6357,22 +5919,11 @@ index aecab30c1..b6b070e62 100644 // Checks whether offset is aligned. // Returns true if it is, else false. bool MacroAssembler::merge_alignment_check(Register base, -@@ -5879,3 +5948,24 @@ void MacroAssembler::get_thread(Register dst) { - - pop(saved_regs, sp); +@@ -5901,3 +5970,13 @@ void MacroAssembler::verify_sve_vector_length() { + stop("Error: SVE vector length has changed since jvm startup"); + bind(verify_ok); } + -+void MacroAssembler::verify_sve_vector_length() { -+ Label verify_ok; -+ assert(UseSVE > 0, "should only be used for SVE"); -+ movw(rscratch1, zr); -+ sve_inc(rscratch1, B); -+ subsw(zr, rscratch1, VM_Version::get_initial_sve_vector_length()); -+ br(EQ, verify_ok); -+ stop("Error: SVE vector length has changed since jvm startup"); -+ bind(verify_ok); -+} -+ +void MacroAssembler::verify_ptrue() { + Label verify_ok; + assert(UseSVE > 0, "should only be used for SVE"); @@ -6383,43 +5934,42 @@ index aecab30c1..b6b070e62 100644 + bind(verify_ok); +} diff --git a/src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp b/src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp -index 85fdc0c88..dccd24911 100644 +index 7fd9e3c97..bc3175b2b 100644 --- a/src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp +++ b/src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp @@ -862,8 +862,10 @@ public: - + DEBUG_ONLY(void verify_heapbase(const char* msg);) - + - void push_CPU_state(bool save_vectors = false); - void pop_CPU_state(bool restore_vectors = false) ; + void push_CPU_state(bool save_vectors = false, bool use_sve = false, + int sve_vector_size_in_bytes = 0); + void pop_CPU_state(bool restore_vectors = false, bool use_sve = false, + int sve_vector_size_in_bytes = 0); - + // Round up to a power of two void round_to(Register reg, int modulus); -@@ -938,6 +940,11 @@ public: - +@@ -939,6 +941,10 @@ public: Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0); - -+ void verify_sve_vector_length(); + + void verify_sve_vector_length(); + void reinitialize_ptrue() { + sve_ptrue(ptrue, B); + } + void verify_ptrue(); - + // Debugging - -@@ -1319,6 +1326,7 @@ private: + +@@ -1320,6 +1326,7 @@ private: // Returns an address on the stack which is reachable with a ldr/str of size // Uses rscratch2 if the address is not directly reachable Address spill_address(int size, int offset, Register tmp=rscratch2); + Address sve_spill_address(int sve_reg_size_in_bytes, int offset, Register tmp=rscratch2); - + bool merge_alignment_check(Register base, size_t size, int64_t cur_offset, int64_t prev_offset) const; - -@@ -1342,6 +1350,9 @@ public: + +@@ -1343,6 +1350,9 @@ public: void spill(FloatRegister Vx, SIMD_RegVariant T, int offset) { str(Vx, T, spill_address(1 << (int)T, offset)); } @@ -6429,7 +5979,7 @@ index 85fdc0c88..dccd24911 100644 void unspill(Register Rx, bool is64, int offset) { if (is64) { ldr(Rx, spill_address(8, offset)); -@@ -1352,6 +1363,9 @@ public: +@@ -1353,6 +1363,9 @@ public: void unspill(FloatRegister Vx, SIMD_RegVariant T, int offset) { ldr(Vx, T, spill_address(1 << (int)T, offset)); } @@ -6439,7 +5989,7 @@ index 85fdc0c88..dccd24911 100644 void spill_copy128(int src_offset, int dst_offset, Register tmp1=rscratch1, Register tmp2=rscratch2) { if (src_offset < 512 && (src_offset & 7) == 0 && -@@ -1365,6 +1379,15 @@ public: +@@ -1366,6 +1379,15 @@ public: spill(tmp1, true, dst_offset+8); } } @@ -6455,244 +6005,21 @@ index 85fdc0c88..dccd24911 100644 }; #ifdef ASSERT -diff --git a/src/hotspot/cpu/aarch64/register_aarch64.cpp b/src/hotspot/cpu/aarch64/register_aarch64.cpp -index 36cbe3fee..3db8e8337 100644 ---- a/src/hotspot/cpu/aarch64/register_aarch64.cpp -+++ b/src/hotspot/cpu/aarch64/register_aarch64.cpp -@@ -1,6 +1,6 @@ - /* -- * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved. -- * Copyright (c) 2014, Red Hat Inc. All rights reserved. -+ * Copyright (c) 2000, 2020, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved. - * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. - * - * This code is free software; you can redistribute it and/or modify it -@@ -33,6 +33,9 @@ const int ConcreteRegisterImpl::max_fpr - = ConcreteRegisterImpl::max_gpr + - FloatRegisterImpl::number_of_registers * FloatRegisterImpl::max_slots_per_register; - -+const int ConcreteRegisterImpl::max_pr -+ = ConcreteRegisterImpl::max_fpr + PRegisterImpl::number_of_registers; -+ - const char* RegisterImpl::name() const { - const char* names[number_of_registers] = { - "c_rarg0", "c_rarg1", "c_rarg2", "c_rarg3", "c_rarg4", "c_rarg5", "c_rarg6", "c_rarg7", -@@ -54,3 +57,10 @@ const char* FloatRegisterImpl::name() const { - }; - return is_valid() ? names[encoding()] : "noreg"; - } -+ -+const char* PRegisterImpl::name() const { -+ const char* names[number_of_registers] = { -+ "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7" -+ }; -+ return is_valid() ? names[encoding()] : "noreg"; -+} -diff --git a/src/hotspot/cpu/aarch64/register_aarch64.hpp b/src/hotspot/cpu/aarch64/register_aarch64.hpp -@@ -129,9 +129,10 @@ class FloatRegisterImpl: public AbstractRegisterImpl { - public: - enum { - number_of_registers = 32, -- max_slots_per_register = 4, -+ max_slots_per_register = 8, - save_slots_per_register = 2, -- extra_save_slots_per_register = max_slots_per_register - save_slots_per_register -+ slots_per_neon_register = 4, -+ extra_save_slots_per_neon_register = slots_per_neon_register - save_slots_per_register - }; - - // construction -@@ -187,6 +188,79 @@ CONSTANT_REGISTER_DECLARATION(FloatRegister, v29 , (29)); - CONSTANT_REGISTER_DECLARATION(FloatRegister, v30 , (30)); - CONSTANT_REGISTER_DECLARATION(FloatRegister, v31 , (31)); - -+// SVE vector registers, shared with the SIMD&FP v0-v31. Vn maps to Zn[127:0]. -+CONSTANT_REGISTER_DECLARATION(FloatRegister, z0 , ( 0)); -+CONSTANT_REGISTER_DECLARATION(FloatRegister, z1 , ( 1)); -+CONSTANT_REGISTER_DECLARATION(FloatRegister, z2 , ( 2)); -+CONSTANT_REGISTER_DECLARATION(FloatRegister, z3 , ( 3)); -+CONSTANT_REGISTER_DECLARATION(FloatRegister, z4 , ( 4)); -+CONSTANT_REGISTER_DECLARATION(FloatRegister, z5 , ( 5)); -+CONSTANT_REGISTER_DECLARATION(FloatRegister, z6 , ( 6)); -+CONSTANT_REGISTER_DECLARATION(FloatRegister, z7 , ( 7)); -+CONSTANT_REGISTER_DECLARATION(FloatRegister, z8 , ( 8)); -+CONSTANT_REGISTER_DECLARATION(FloatRegister, z9 , ( 9)); -+CONSTANT_REGISTER_DECLARATION(FloatRegister, z10 , (10)); -+CONSTANT_REGISTER_DECLARATION(FloatRegister, z11 , (11)); -+CONSTANT_REGISTER_DECLARATION(FloatRegister, z12 , (12)); -+CONSTANT_REGISTER_DECLARATION(FloatRegister, z13 , (13)); -+CONSTANT_REGISTER_DECLARATION(FloatRegister, z14 , (14)); -+CONSTANT_REGISTER_DECLARATION(FloatRegister, z15 , (15)); -+CONSTANT_REGISTER_DECLARATION(FloatRegister, z16 , (16)); -+CONSTANT_REGISTER_DECLARATION(FloatRegister, z17 , (17)); -+CONSTANT_REGISTER_DECLARATION(FloatRegister, z18 , (18)); -+CONSTANT_REGISTER_DECLARATION(FloatRegister, z19 , (19)); -+CONSTANT_REGISTER_DECLARATION(FloatRegister, z20 , (20)); -+CONSTANT_REGISTER_DECLARATION(FloatRegister, z21 , (21)); -+CONSTANT_REGISTER_DECLARATION(FloatRegister, z22 , (22)); -+CONSTANT_REGISTER_DECLARATION(FloatRegister, z23 , (23)); -+CONSTANT_REGISTER_DECLARATION(FloatRegister, z24 , (24)); -+CONSTANT_REGISTER_DECLARATION(FloatRegister, z25 , (25)); -+CONSTANT_REGISTER_DECLARATION(FloatRegister, z26 , (26)); -+CONSTANT_REGISTER_DECLARATION(FloatRegister, z27 , (27)); -+CONSTANT_REGISTER_DECLARATION(FloatRegister, z28 , (28)); -+CONSTANT_REGISTER_DECLARATION(FloatRegister, z29 , (29)); -+CONSTANT_REGISTER_DECLARATION(FloatRegister, z30 , (30)); -+CONSTANT_REGISTER_DECLARATION(FloatRegister, z31 , (31)); -+ -+class PRegisterImpl; -+typedef PRegisterImpl* PRegister; -+inline PRegister as_PRegister(int encoding) { -+ return (PRegister)(intptr_t)encoding; -+} -+ -+// The implementation of predicate registers for the architecture -+class PRegisterImpl: public AbstractRegisterImpl { -+ public: -+ enum { -+ number_of_registers = 8, -+ max_slots_per_register = 1 -+ }; -+ -+ // construction -+ inline friend PRegister as_PRegister(int encoding); -+ -+ VMReg as_VMReg(); -+ -+ // derived registers, offsets, and addresses -+ PRegister successor() const { return as_PRegister(encoding() + 1); } -+ -+ // accessors -+ int encoding() const { assert(is_valid(), "invalid register"); return (intptr_t)this; } -+ int encoding_nocheck() const { return (intptr_t)this; } -+ bool is_valid() const { return 0 <= (intptr_t)this && (intptr_t)this < number_of_registers; } -+ const char* name() const; -+}; -+ -+// The predicate registers of SVE. -+CONSTANT_REGISTER_DECLARATION(PRegister, p0, ( 0)); -+CONSTANT_REGISTER_DECLARATION(PRegister, p1, ( 1)); -+CONSTANT_REGISTER_DECLARATION(PRegister, p2, ( 2)); -+CONSTANT_REGISTER_DECLARATION(PRegister, p3, ( 3)); -+CONSTANT_REGISTER_DECLARATION(PRegister, p4, ( 4)); -+CONSTANT_REGISTER_DECLARATION(PRegister, p5, ( 5)); -+CONSTANT_REGISTER_DECLARATION(PRegister, p6, ( 6)); -+CONSTANT_REGISTER_DECLARATION(PRegister, p7, ( 7)); -+ - // Need to know the total number of registers of all sorts for SharedInfo. - // Define a class that exports it. - class ConcreteRegisterImpl : public AbstractRegisterImpl { -@@ -199,12 +273,14 @@ class ConcreteRegisterImpl : public AbstractRegisterImpl { - - number_of_registers = (RegisterImpl::max_slots_per_register * RegisterImpl::number_of_registers + - FloatRegisterImpl::max_slots_per_register * FloatRegisterImpl::number_of_registers + -+ PRegisterImpl::max_slots_per_register * PRegisterImpl::number_of_registers + - 1) // flags - }; - - // added to make it compile - static const int max_gpr; - static const int max_fpr; -+ static const int max_pr; - }; - - // A set of registers diff --git a/src/hotspot/cpu/aarch64/register_definitions_aarch64.cpp b/src/hotspot/cpu/aarch64/register_definitions_aarch64.cpp -index c18109087..e337f582a 100644 +index 15131ed32..e337f582a 100644 --- a/src/hotspot/cpu/aarch64/register_definitions_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/register_definitions_aarch64.cpp -@@ -1,5 +1,5 @@ - /* -- * Copyright (c) 2002, 2018, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2002, 2020, Oracle and/or its affiliates. All rights reserved. - * Copyright (c) 2014, Red Hat Inc. All rights reserved. - * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. - * -@@ -154,3 +154,47 @@ REGISTER_DEFINITION(Register, rthread); - REGISTER_DEFINITION(Register, rheapbase); - - REGISTER_DEFINITION(Register, r31_sp); -+ -+REGISTER_DEFINITION(FloatRegister, z0); -+REGISTER_DEFINITION(FloatRegister, z1); -+REGISTER_DEFINITION(FloatRegister, z2); -+REGISTER_DEFINITION(FloatRegister, z3); -+REGISTER_DEFINITION(FloatRegister, z4); -+REGISTER_DEFINITION(FloatRegister, z5); -+REGISTER_DEFINITION(FloatRegister, z6); -+REGISTER_DEFINITION(FloatRegister, z7); -+REGISTER_DEFINITION(FloatRegister, z8); -+REGISTER_DEFINITION(FloatRegister, z9); -+REGISTER_DEFINITION(FloatRegister, z10); -+REGISTER_DEFINITION(FloatRegister, z11); -+REGISTER_DEFINITION(FloatRegister, z12); -+REGISTER_DEFINITION(FloatRegister, z13); -+REGISTER_DEFINITION(FloatRegister, z14); -+REGISTER_DEFINITION(FloatRegister, z15); -+REGISTER_DEFINITION(FloatRegister, z16); -+REGISTER_DEFINITION(FloatRegister, z17); -+REGISTER_DEFINITION(FloatRegister, z18); -+REGISTER_DEFINITION(FloatRegister, z19); -+REGISTER_DEFINITION(FloatRegister, z20); -+REGISTER_DEFINITION(FloatRegister, z21); -+REGISTER_DEFINITION(FloatRegister, z22); -+REGISTER_DEFINITION(FloatRegister, z23); -+REGISTER_DEFINITION(FloatRegister, z24); -+REGISTER_DEFINITION(FloatRegister, z25); -+REGISTER_DEFINITION(FloatRegister, z26); -+REGISTER_DEFINITION(FloatRegister, z27); -+REGISTER_DEFINITION(FloatRegister, z28); -+REGISTER_DEFINITION(FloatRegister, z29); -+REGISTER_DEFINITION(FloatRegister, z30); -+REGISTER_DEFINITION(FloatRegister, z31); -+ -+REGISTER_DEFINITION(PRegister, p0); -+REGISTER_DEFINITION(PRegister, p1); -+REGISTER_DEFINITION(PRegister, p2); -+REGISTER_DEFINITION(PRegister, p3); -+REGISTER_DEFINITION(PRegister, p4); -+REGISTER_DEFINITION(PRegister, p5); -+REGISTER_DEFINITION(PRegister, p6); -+REGISTER_DEFINITION(PRegister, p7); +@@ -196,3 +196,5 @@ REGISTER_DEFINITION(PRegister, p4); + REGISTER_DEFINITION(PRegister, p5); + REGISTER_DEFINITION(PRegister, p6); + REGISTER_DEFINITION(PRegister, p7); + +REGISTER_DEFINITION(PRegister, ptrue); diff --git a/src/hotspot/cpu/aarch64/sharedRuntime_aarch64.cpp b/src/hotspot/cpu/aarch64/sharedRuntime_aarch64.cpp -index 3d3cc3a1e..6242cce08 100644 +index 3bf7284a7..6242cce08 100644 --- a/src/hotspot/cpu/aarch64/sharedRuntime_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/sharedRuntime_aarch64.cpp -@@ -111,11 +111,28 @@ class RegisterSaver { - }; - - OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words, bool save_vectors) { -+ bool use_sve = false; -+ int sve_vector_size_in_bytes = 0; -+ int sve_vector_size_in_slots = 0; -+ -+#ifdef COMPILER2 -+ use_sve = Matcher::supports_scalable_vector(); -+ sve_vector_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE); -+ sve_vector_size_in_slots = Matcher::scalable_vector_reg_size(T_FLOAT); -+#endif -+ - #if COMPILER2_OR_JVMCI - if (save_vectors) { -+ int vect_words = 0; -+ int extra_save_slots_per_register = 0; - // Save upper half of vector registers -- int vect_words = FloatRegisterImpl::number_of_registers * FloatRegisterImpl::extra_save_slots_per_register / -- VMRegImpl::slots_per_word; -+ if (use_sve) { -+ extra_save_slots_per_register = sve_vector_size_in_slots - FloatRegisterImpl::save_slots_per_register; -+ } else { -+ extra_save_slots_per_register = FloatRegisterImpl::extra_save_slots_per_neon_register; -+ } -+ vect_words = FloatRegisterImpl::number_of_registers * extra_save_slots_per_register / -+ VMRegImpl::slots_per_word; - additional_frame_words += vect_words; - } - #else -@@ -134,7 +151,7 @@ OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_ +@@ -151,7 +151,7 @@ OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_ // Save Integer and Float registers. __ enter(); @@ -6701,23 +6028,7 @@ index 3d3cc3a1e..6242cce08 100644 // Set an oopmap for the call site. This oopmap will map all // oop-registers and debug-info registers as callee-saved. This -@@ -158,8 +175,13 @@ OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_ - - for (int i = 0; i < FloatRegisterImpl::number_of_registers; i++) { - FloatRegister r = as_FloatRegister(i); -- int sp_offset = save_vectors ? (FloatRegisterImpl::max_slots_per_register * i) : -- (FloatRegisterImpl::save_slots_per_register * i); -+ int sp_offset = 0; -+ if (save_vectors) { -+ sp_offset = use_sve ? (sve_vector_size_in_slots * i) : -+ (FloatRegisterImpl::slots_per_neon_register * i); -+ } else { -+ sp_offset = FloatRegisterImpl::save_slots_per_register * i; -+ } - oop_map->set_callee_saved(VMRegImpl::stack2reg(sp_offset), - r->as_VMReg()); - } -@@ -168,10 +190,15 @@ OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_ +@@ -190,10 +190,15 @@ OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_ } void RegisterSaver::restore_live_registers(MacroAssembler* masm, bool restore_vectors) { @@ -6734,19 +6045,7 @@ index 3d3cc3a1e..6242cce08 100644 __ leave(); } -@@ -1829,6 +1856,11 @@ nmethod* SharedRuntime::generate_native_wrapper(MacroAssembler* masm, - __ strw(rscratch1, Address(rthread, JavaThread::thread_state_offset())); - } - -+ if (UseSVE > 0) { -+ // Make sure that jni code does not change SVE vector length. -+ __ verify_sve_vector_length(); -+ } -+ - // check for safepoint operation in progress and/or pending suspend requests - Label safepoint_in_progress, safepoint_in_progress_done; - { -@@ -2759,6 +2791,12 @@ SafepointBlob* SharedRuntime::generate_handler_blob(address call_ptr, int poll_t +@@ -2786,6 +2791,12 @@ SafepointBlob* SharedRuntime::generate_handler_blob(address call_ptr, int poll_t __ maybe_isb(); __ membar(Assembler::LoadLoad | Assembler::LoadStore); @@ -6788,201 +6087,8 @@ index 26a54c87e..85f64c007 100644 __ leave(); // check for pending exceptions -diff --git a/src/hotspot/cpu/aarch64/templateInterpreterGenerator_aarch64.cpp b/src/hotspot/cpu/aarch64/templateInterpreterGenerator_aarch64.cpp -index 03d7a6e2d..42f301531 100644 ---- a/src/hotspot/cpu/aarch64/templateInterpreterGenerator_aarch64.cpp -+++ b/src/hotspot/cpu/aarch64/templateInterpreterGenerator_aarch64.cpp -@@ -1377,6 +1377,11 @@ address TemplateInterpreterGenerator::generate_native_entry(bool synchronized) { - __ push(dtos); - __ push(ltos); - -+ if (UseSVE > 0) { -+ // Make sure that jni code does not change SVE vector length. -+ __ verify_sve_vector_length(); -+ } -+ - // change thread state - __ mov(rscratch1, _thread_in_native_trans); - __ lea(rscratch2, Address(rthread, JavaThread::thread_state_offset())); -diff --git a/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp b/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp -index e906454f1..7ae881b74 100644 ---- a/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp -+++ b/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp -@@ -30,12 +30,14 @@ - #include "runtime/java.hpp" - #include "runtime/stubCodeGenerator.hpp" - #include "runtime/vm_version.hpp" -+#include "utilities/formatBuffer.hpp" - #include "utilities/macros.hpp" - - #include OS_HEADER_INLINE(os) - --#include - #include -+#include -+#include - - #ifndef HWCAP_AES - #define HWCAP_AES (1<<3) -@@ -61,12 +63,27 @@ - #define HWCAP_ATOMICS (1<<8) - #endif - -+#ifndef HWCAP_SVE -+#define HWCAP_SVE (1 << 22) -+#endif -+ -+#ifndef HWCAP2_SVE2 -+#define HWCAP2_SVE2 (1 << 1) -+#endif -+ -+#ifndef PR_SVE_GET_VL -+// For old toolchains which do not have SVE related macros defined. -+#define PR_SVE_SET_VL 50 -+#define PR_SVE_GET_VL 51 -+#endif -+ - int VM_Version::_cpu; - int VM_Version::_model; - int VM_Version::_model2; - int VM_Version::_variant; - int VM_Version::_revision; - int VM_Version::_stepping; -+int VM_Version::_initial_sve_vector_length; - VM_Version::PsrInfo VM_Version::_psr_info = { 0, }; - - static BufferBlob* stub_blob; -@@ -164,6 +181,7 @@ void VM_Version::get_processor_features() { - } - - uint64_t auxv = getauxval(AT_HWCAP); -+ uint64_t auxv2 = getauxval(AT_HWCAP2); - - char buf[512]; - -@@ -269,6 +287,8 @@ void VM_Version::get_processor_features() { - if (auxv & HWCAP_SHA1) strcat(buf, ", sha1"); - if (auxv & HWCAP_SHA2) strcat(buf, ", sha256"); - if (auxv & HWCAP_ATOMICS) strcat(buf, ", lse"); -+ if (auxv & HWCAP_SVE) strcat(buf, ", sve"); -+ if (auxv2 & HWCAP2_SVE2) strcat(buf, ", sve2"); - - _features_string = os::strdup(buf); - -@@ -402,6 +422,18 @@ void VM_Version::get_processor_features() { - FLAG_SET_DEFAULT(UseBlockZeroing, false); - } - -+ if (auxv & HWCAP_SVE) { -+ if (FLAG_IS_DEFAULT(UseSVE)) { -+ FLAG_SET_DEFAULT(UseSVE, (auxv2 & HWCAP2_SVE2) ? 2 : 1); -+ } -+ if (UseSVE > 0) { -+ _initial_sve_vector_length = prctl(PR_SVE_GET_VL); -+ } -+ } else if (UseSVE > 0) { -+ warning("UseSVE specified, but not supported on current CPU. Disabling SVE."); -+ FLAG_SET_DEFAULT(UseSVE, 0); -+ } -+ - // This machine allows unaligned memory accesses - if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) { - FLAG_SET_DEFAULT(UseUnalignedAccesses, true); -@@ -435,6 +467,50 @@ void VM_Version::get_processor_features() { - UseMontgomerySquareIntrinsic = true; - } - -+ if (UseSVE > 0) { -+ if (FLAG_IS_DEFAULT(MaxVectorSize)) { -+ MaxVectorSize = _initial_sve_vector_length; -+ } else if (MaxVectorSize < 16) { -+ warning("SVE does not support vector length less than 16 bytes. Disabling SVE."); -+ UseSVE = 0; -+ } else if ((MaxVectorSize % 16) == 0 && is_power_of_2(MaxVectorSize)) { -+ int new_vl = prctl(PR_SVE_SET_VL, MaxVectorSize); -+ _initial_sve_vector_length = new_vl; -+ // If MaxVectorSize is larger than system largest supported SVE vector length, above prctl() -+ // call will set task vector length to the system largest supported value. So, we also update -+ // MaxVectorSize to that largest supported value. -+ if (new_vl < 0) { -+ vm_exit_during_initialization( -+ err_msg("Current system does not support SVE vector length for MaxVectorSize: %d", -+ (int)MaxVectorSize)); -+ } else if (new_vl != MaxVectorSize) { -+ warning("Current system only supports max SVE vector length %d. Set MaxVectorSize to %d", -+ new_vl, new_vl); -+ } -+ MaxVectorSize = new_vl; -+ } else { -+ vm_exit_during_initialization(err_msg("Unsupported MaxVectorSize: %d", (int)MaxVectorSize)); -+ } -+ } -+ -+ if (UseSVE == 0) { // NEON -+ int min_vector_size = 8; -+ int max_vector_size = 16; -+ if (!FLAG_IS_DEFAULT(MaxVectorSize)) { -+ if (!is_power_of_2(MaxVectorSize)) { -+ vm_exit_during_initialization(err_msg("Unsupported MaxVectorSize: %d", (int)MaxVectorSize)); -+ } else if (MaxVectorSize < min_vector_size) { -+ warning("MaxVectorSize must be at least %i on this platform", min_vector_size); -+ FLAG_SET_DEFAULT(MaxVectorSize, min_vector_size); -+ } else if (MaxVectorSize > max_vector_size) { -+ warning("MaxVectorSize must be at most %i on this platform", max_vector_size); -+ FLAG_SET_DEFAULT(MaxVectorSize, max_vector_size); -+ } -+ } else { -+ FLAG_SET_DEFAULT(MaxVectorSize, 16); -+ } -+ } -+ - if (FLAG_IS_DEFAULT(OptoScheduling)) { - OptoScheduling = true; - } -diff --git a/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp b/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp -index dcb6342e1..ae2715102 100644 ---- a/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp -+++ b/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp -@@ -40,6 +40,7 @@ protected: - static int _variant; - static int _revision; - static int _stepping; -+ static int _initial_sve_vector_length; - - struct PsrInfo { - uint32_t dczid_el0; -@@ -101,6 +102,7 @@ public: - static int cpu_model2() { return _model2; } - static int cpu_variant() { return _variant; } - static int cpu_revision() { return _revision; } -+ static int get_initial_sve_vector_length() { return _initial_sve_vector_length; }; - static ByteSize dczid_el0_offset() { return byte_offset_of(PsrInfo, dczid_el0); } - static ByteSize ctr_el0_offset() { return byte_offset_of(PsrInfo, ctr_el0); } - static bool is_zva_enabled() { -diff --git a/src/hotspot/cpu/aarch64/vmreg_aarch64.inline.hpp b/src/hotspot/cpu/aarch64/vmreg_aarch64.inline.hpp -index c5d4383b4..dde7a7a91 100644 ---- a/src/hotspot/cpu/aarch64/vmreg_aarch64.inline.hpp -+++ b/src/hotspot/cpu/aarch64/vmreg_aarch64.inline.hpp -@@ -1,6 +1,6 @@ - /* -- * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved. -- * Copyright (c) 2014, Red Hat Inc. All rights reserved. -+ * Copyright (c) 2006, 2020, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved. - * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. - * - * This code is free software; you can redistribute it and/or modify it -@@ -36,4 +36,8 @@ inline VMReg FloatRegisterImpl::as_VMReg() { - ConcreteRegisterImpl::max_gpr); - } - -+inline VMReg PRegisterImpl::as_VMReg() { -+ return VMRegImpl::as_VMReg(encoding() + ConcreteRegisterImpl::max_fpr); -+} -+ - #endif // CPU_AARCH64_VM_VMREG_AARCH64_INLINE_HPP diff --git a/src/hotspot/cpu/arm/arm.ad b/src/hotspot/cpu/arm/arm.ad -index 4a32af54e..03248b2e0 100644 +index 0ef4d7f3e..03248b2e0 100644 --- a/src/hotspot/cpu/arm/arm.ad +++ b/src/hotspot/cpu/arm/arm.ad @@ -1093,7 +1093,7 @@ const bool Matcher::match_rule_supported(int opcode) { @@ -6994,23 +6100,8 @@ index 4a32af54e..03248b2e0 100644 // TODO // identify extra cases that we might want to provide match rules for -@@ -1121,6 +1121,14 @@ const int Matcher::vector_width_in_bytes(BasicType bt) { - return MaxVectorSize; - } - -+const bool Matcher::supports_scalable_vector() { -+ return false; -+} -+ -+const int Matcher::scalable_vector_reg_size(const BasicType bt) { -+ return -1; -+} -+ - // Vector ideal reg corresponding to specified size in bytes - const uint Matcher::vector_ideal_reg(int size) { - assert(MaxVectorSize >= size, ""); diff --git a/src/hotspot/cpu/ppc/ppc.ad b/src/hotspot/cpu/ppc/ppc.ad -index 36cbada53..571a6aeb0 100644 +index 7ee16a975..571a6aeb0 100644 --- a/src/hotspot/cpu/ppc/ppc.ad +++ b/src/hotspot/cpu/ppc/ppc.ad @@ -2242,7 +2242,7 @@ const bool Matcher::match_rule_supported(int opcode) { @@ -7022,23 +6113,8 @@ index 36cbada53..571a6aeb0 100644 // TODO // identify extra cases that we might want to provide match rules for -@@ -2310,6 +2310,14 @@ const int Matcher::min_vector_size(const BasicType bt) { - return max_vector_size(bt); // Same as max. - } - -+const bool Matcher::supports_scalable_vector() { -+ return false; -+} -+ -+const int Matcher::scalable_vector_reg_size(const BasicType bt) { -+ return -1; -+} -+ - // PPC implementation uses VSX load/store instructions (if - // SuperwordUseVSX) which support 4 byte but not arbitrary alignment - const bool Matcher::misaligned_vectors_ok() { diff --git a/src/hotspot/cpu/s390/s390.ad b/src/hotspot/cpu/s390/s390.ad -index 96c231b0a..782c1c7c4 100644 +index ea09aaafc..782c1c7c4 100644 --- a/src/hotspot/cpu/s390/s390.ad +++ b/src/hotspot/cpu/s390/s390.ad @@ -1522,7 +1522,7 @@ const bool Matcher::match_rule_supported(int opcode) { @@ -7050,21 +6126,6 @@ index 96c231b0a..782c1c7c4 100644 // TODO // Identify extra cases that we might want to provide match rules for // e.g. Op_ vector nodes and other intrinsics while guarding with vlen. -@@ -1573,6 +1573,14 @@ const int Matcher::min_vector_size(const BasicType bt) { - return max_vector_size(bt); // Same as max. - } - -+const bool Matcher::supports_scalable_vector() { -+ return false; -+} -+ -+const int Matcher::scalable_vector_reg_size(const BasicType bt) { -+ return -1; -+} -+ - const uint Matcher::vector_shift_count_ideal_reg(int size) { - fatal("vector shift is not supported"); - return Node::NotAMachineReg; diff --git a/src/hotspot/cpu/sparc/sparc.ad b/src/hotspot/cpu/sparc/sparc.ad index a09c795c9..3b1b1046e 100644 --- a/src/hotspot/cpu/sparc/sparc.ad @@ -7079,16 +6140,9 @@ index a09c795c9..3b1b1046e 100644 // TODO // identify extra cases that we might want to provide match rules for diff --git a/src/hotspot/cpu/x86/x86.ad b/src/hotspot/cpu/x86/x86.ad -index abdd7483d..93aee6d6c 100644 +index 76dd6addd..93aee6d6c 100644 --- a/src/hotspot/cpu/x86/x86.ad +++ b/src/hotspot/cpu/x86/x86.ad -@@ -1,5 +1,5 @@ - // --// Copyright (c) 2011, 2019, Oracle and/or its affiliates. All rights reserved. -+// Copyright (c) 2011, 2020, Oracle and/or its affiliates. All rights reserved. - // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. - // - // This code is free software; you can redistribute it and/or modify it @@ -1354,7 +1354,7 @@ const bool Matcher::match_rule_supported(int opcode) { return ret_value; // Per default match rules are supported. } @@ -7098,480 +6152,8 @@ index abdd7483d..93aee6d6c 100644 // identify extra cases that we might want to provide match rules for // e.g. Op_ vector nodes and other intrinsics while guarding with vlen bool ret_value = match_rule_supported(opcode); -@@ -1485,6 +1485,14 @@ const int Matcher::min_vector_size(const BasicType bt) { - return MIN2(size,max_size); - } - -+const bool Matcher::supports_scalable_vector() { -+ return false; -+} -+ -+const int Matcher::scalable_vector_reg_size(const BasicType bt) { -+ return -1; -+} -+ - // Vector ideal reg corresponding to specified size in bytes - const uint Matcher::vector_ideal_reg(int size) { - assert(MaxVectorSize >= size, ""); -diff --git a/src/hotspot/cpu/x86/x86_64.ad b/src/hotspot/cpu/x86/x86_64.ad -index 8904bba97..e09cdd061 100644 ---- a/src/hotspot/cpu/x86/x86_64.ad -+++ b/src/hotspot/cpu/x86/x86_64.ad -@@ -2968,7 +2968,7 @@ frame - RAX_H_num // Op_RegL - }; - // Excluded flags and vector registers. -- assert(ARRAY_SIZE(hi) == _last_machine_leaf - 6, "missing type"); -+ assert(ARRAY_SIZE(hi) == _last_machine_leaf - 8, "missing type"); - return OptoRegPair(hi[ideal_reg], lo[ideal_reg]); - %} - %} -diff --git a/src/hotspot/share/adlc/archDesc.cpp b/src/hotspot/share/adlc/archDesc.cpp -index ba61aa4c0..9e41b2dc6 100644 ---- a/src/hotspot/share/adlc/archDesc.cpp -+++ b/src/hotspot/share/adlc/archDesc.cpp -@@ -1,5 +1,5 @@ - // --// Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved. -+// Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved. - // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. - // - // This code is free software; you can redistribute it and/or modify it -@@ -929,6 +929,7 @@ const char *ArchDesc::getIdealType(const char *idealOp) { - // Match Vector types. - if (strncmp(idealOp, "Vec",3)==0) { - switch(last_char) { -+ case 'A': return "TypeVect::VECTA"; - case 'S': return "TypeVect::VECTS"; - case 'D': return "TypeVect::VECTD"; - case 'X': return "TypeVect::VECTX"; -@@ -939,6 +940,10 @@ const char *ArchDesc::getIdealType(const char *idealOp) { - } - } - -+ if (strncmp(idealOp, "RegVMask", 8) == 0) { -+ return "Type::BOTTOM"; -+ } -+ - // !!!!! - switch(last_char) { - case 'I': return "TypeInt::INT"; -diff --git a/src/hotspot/share/adlc/formssel.cpp b/src/hotspot/share/adlc/formssel.cpp -index c7b855a7e..a37866824 100644 ---- a/src/hotspot/share/adlc/formssel.cpp -+++ b/src/hotspot/share/adlc/formssel.cpp -@@ -3963,6 +3963,8 @@ bool MatchRule::is_base_register(FormDict &globals) const { - strcmp(opType,"RegL")==0 || - strcmp(opType,"RegF")==0 || - strcmp(opType,"RegD")==0 || -+ strcmp(opType,"RegVMask")==0 || -+ strcmp(opType,"VecA")==0 || - strcmp(opType,"VecS")==0 || - strcmp(opType,"VecD")==0 || - strcmp(opType,"VecX")==0 || -diff --git a/src/hotspot/share/opto/chaitin.cpp b/src/hotspot/share/opto/chaitin.cpp -index 914dc43f6..710af9de8 100644 ---- a/src/hotspot/share/opto/chaitin.cpp -+++ b/src/hotspot/share/opto/chaitin.cpp -@@ -77,6 +77,7 @@ void LRG::dump() const { - if( _is_oop ) tty->print("Oop "); - if( _is_float ) tty->print("Float "); - if( _is_vector ) tty->print("Vector "); -+ if( _is_scalable ) tty->print("Scalable "); - if( _was_spilled1 ) tty->print("Spilled "); - if( _was_spilled2 ) tty->print("Spilled2 "); - if( _direct_conflict ) tty->print("Direct_conflict "); -@@ -646,7 +647,15 @@ void PhaseChaitin::Register_Allocate() { - // Live ranges record the highest register in their mask. - // We want the low register for the AD file writer's convenience. - OptoReg::Name hi = lrg.reg(); // Get hi register -- OptoReg::Name lo = OptoReg::add(hi, (1-lrg.num_regs())); // Find lo -+ int num_regs = lrg.num_regs(); -+ if (lrg.is_scalable() && OptoReg::is_stack(hi)) { -+ // For scalable vector registers, when they are allocated in physical -+ // registers, num_regs is RegMask::SlotsPerVecA for reg mask of scalable -+ // vector. If they are allocated on stack, we need to get the actual -+ // num_regs, which reflects the physical length of scalable registers. -+ num_regs = lrg.scalable_reg_slots(); -+ } -+ OptoReg::Name lo = OptoReg::add(hi, (1-num_regs)); // Find lo - // We have to use pair [lo,lo+1] even for wide vectors because - // the rest of code generation works only with pairs. It is safe - // since for registers encoding only 'lo' is used. -@@ -801,8 +810,19 @@ void PhaseChaitin::gather_lrg_masks( bool after_aggressive ) { - // Check for vector live range (only if vector register is used). - // On SPARC vector uses RegD which could be misaligned so it is not - // processes as vector in RA. -- if (RegMask::is_vector(ireg)) -+ if (RegMask::is_vector(ireg)) { - lrg._is_vector = 1; -+ if (ireg == Op_VecA) { -+ assert(Matcher::supports_scalable_vector(), "scalable vector should be supported"); -+ lrg._is_scalable = 1; -+ // For scalable vector, when it is allocated in physical register, -+ // num_regs is RegMask::SlotsPerVecA for reg mask, -+ // which may not be the actual physical register size. -+ // If it is allocated in stack, we need to get the actual -+ // physical length of scalable vector register. -+ lrg.set_scalable_reg_slots(Matcher::scalable_vector_reg_size(T_FLOAT)); -+ } -+ } - assert(n_type->isa_vect() == NULL || lrg._is_vector || ireg == Op_RegD || ireg == Op_RegL, - "vector must be in vector registers"); - -@@ -912,6 +932,13 @@ void PhaseChaitin::gather_lrg_masks( bool after_aggressive ) { - lrg.set_reg_pressure(1); - #endif - break; -+ case Op_VecA: -+ assert(Matcher::supports_scalable_vector(), "does not support scalable vector"); -+ assert(RegMask::num_registers(Op_VecA) == RegMask::SlotsPerVecA, "sanity"); -+ assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecA), "vector should be aligned"); -+ lrg.set_num_regs(RegMask::SlotsPerVecA); -+ lrg.set_reg_pressure(1); -+ break; - case Op_VecS: - assert(Matcher::vector_size_supported(T_BYTE,4), "sanity"); - assert(RegMask::num_registers(Op_VecS) == RegMask::SlotsPerVecS, "sanity"); -@@ -1358,6 +1385,46 @@ static bool is_legal_reg(LRG &lrg, OptoReg::Name reg, int chunk) { - return false; - } - -+static OptoReg::Name find_first_set(LRG &lrg, RegMask mask, int chunk) { -+ int num_regs = lrg.num_regs(); -+ OptoReg::Name assigned = mask.find_first_set(lrg, num_regs); -+ -+ if (lrg.is_scalable()) { -+ // a physical register is found -+ if (chunk == 0 && OptoReg::is_reg(assigned)) { -+ return assigned; -+ } -+ -+ // find available stack slots for scalable register -+ if (lrg._is_vector) { -+ num_regs = lrg.scalable_reg_slots(); -+ // if actual scalable vector register is exactly SlotsPerVecA * 32 bits -+ if (num_regs == RegMask::SlotsPerVecA) { -+ return assigned; -+ } -+ -+ // mask has been cleared out by clear_to_sets(SlotsPerVecA) before choose_color, but it -+ // does not work for scalable size. We have to find adjacent scalable_reg_slots() bits -+ // instead of SlotsPerVecA bits. -+ assigned = mask.find_first_set(lrg, num_regs); // find highest valid reg -+ while (OptoReg::is_valid(assigned) && RegMask::can_represent(assigned)) { -+ // Verify the found reg has scalable_reg_slots() bits set. -+ if (mask.is_valid_reg(assigned, num_regs)) { -+ return assigned; -+ } else { -+ // Remove more for each iteration -+ mask.Remove(assigned - num_regs + 1); // Unmask the lowest reg -+ mask.clear_to_sets(RegMask::SlotsPerVecA); // Align by SlotsPerVecA bits -+ assigned = mask.find_first_set(lrg, num_regs); -+ } -+ } -+ return OptoReg::Bad; // will cause chunk change, and retry next chunk -+ } -+ } -+ -+ return assigned; -+} -+ - // Choose a color using the biasing heuristic - OptoReg::Name PhaseChaitin::bias_color( LRG &lrg, int chunk ) { - -@@ -1391,7 +1458,7 @@ OptoReg::Name PhaseChaitin::bias_color( LRG &lrg, int chunk ) { - RegMask tempmask = lrg.mask(); - tempmask.AND(lrgs(copy_lrg).mask()); - tempmask.clear_to_sets(lrg.num_regs()); -- OptoReg::Name reg = tempmask.find_first_set(lrg.num_regs()); -+ OptoReg::Name reg = find_first_set(lrg, tempmask, chunk); - if (OptoReg::is_valid(reg)) - return reg; - } -@@ -1400,7 +1467,7 @@ OptoReg::Name PhaseChaitin::bias_color( LRG &lrg, int chunk ) { - // If no bias info exists, just go with the register selection ordering - if (lrg._is_vector || lrg.num_regs() == 2) { - // Find an aligned set -- return OptoReg::add(lrg.mask().find_first_set(lrg.num_regs()),chunk); -+ return OptoReg::add(find_first_set(lrg, lrg.mask(), chunk), chunk); - } - - // CNC - Fun hack. Alternate 1st and 2nd selection. Enables post-allocate -@@ -1455,7 +1522,6 @@ uint PhaseChaitin::Select( ) { - LRG *lrg = &lrgs(lidx); - _simplified = lrg->_next; - -- - #ifndef PRODUCT - if (trace_spilling()) { - ttyLocker ttyl; -@@ -1539,7 +1605,6 @@ uint PhaseChaitin::Select( ) { - // Bump register mask up to next stack chunk - chunk += RegMask::CHUNK_SIZE; - lrg->Set_All(); -- - goto retry_next_chunk; - } - -@@ -1564,12 +1629,21 @@ uint PhaseChaitin::Select( ) { - int n_regs = lrg->num_regs(); - assert(!lrg->_is_vector || !lrg->_fat_proj, "sanity"); - if (n_regs == 1 || !lrg->_fat_proj) { -- assert(!lrg->_is_vector || n_regs <= RegMask::SlotsPerVecZ, "sanity"); -+ if (Matcher::supports_scalable_vector()) { -+ assert(!lrg->_is_vector || n_regs <= RegMask::SlotsPerVecA, "sanity"); -+ } else { -+ assert(!lrg->_is_vector || n_regs <= RegMask::SlotsPerVecZ, "sanity"); -+ } - lrg->Clear(); // Clear the mask - lrg->Insert(reg); // Set regmask to match selected reg - // For vectors and pairs, also insert the low bit of the pair -- for (int i = 1; i < n_regs; i++) -+ // We always choose the high bit, then mask the low bits by register size -+ if (lrg->is_scalable() && OptoReg::is_stack(lrg->reg())) { // stack -+ n_regs = lrg->scalable_reg_slots(); -+ } -+ for (int i = 1; i < n_regs; i++) { - lrg->Insert(OptoReg::add(reg,-i)); -+ } - lrg->set_mask_size(n_regs); - } else { // Else fatproj - // mask must be equal to fatproj bits, by definition -diff --git a/src/hotspot/share/opto/chaitin.hpp b/src/hotspot/share/opto/chaitin.hpp -index e5be5b966..5408a24ef 100644 ---- a/src/hotspot/share/opto/chaitin.hpp -+++ b/src/hotspot/share/opto/chaitin.hpp -@@ -1,5 +1,5 @@ - /* -- * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved. - * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. - * - * This code is free software; you can redistribute it and/or modify it -@@ -115,7 +115,9 @@ public: - _msize_valid=1; - if (_is_vector) { - assert(!_fat_proj, "sanity"); -- _mask.verify_sets(_num_regs); -+ if (!(_is_scalable && OptoReg::is_stack(_reg))) { -+ _mask.verify_sets(_num_regs); -+ } - } else if (_num_regs == 2 && !_fat_proj) { - _mask.verify_pairs(); - } -@@ -139,14 +141,37 @@ public: - void clear_to_pairs() { _mask.clear_to_pairs(); debug_only(_msize_valid=0;) } - void clear_to_sets() { _mask.clear_to_sets(_num_regs); debug_only(_msize_valid=0;) } - -- // Number of registers this live range uses when it colors - private: -+ // Number of registers this live range uses when it colors - uint16_t _num_regs; // 2 for Longs and Doubles, 1 for all else - // except _num_regs is kill count for fat_proj -+ -+ // For scalable register, num_regs may not be the actual physical register size. -+ // We need to get the actual physical length of scalable register when scalable -+ // register is spilled. The size of one slot is 32-bit. -+ uint _scalable_reg_slots; // Actual scalable register length of slots. -+ // Meaningful only when _is_scalable is true. - public: - int num_regs() const { return _num_regs; } - void set_num_regs( int reg ) { assert( _num_regs == reg || !_num_regs, "" ); _num_regs = reg; } - -+ uint scalable_reg_slots() { return _scalable_reg_slots; } -+ void set_scalable_reg_slots(uint slots) { -+ assert(_is_scalable, "scalable register"); -+ assert(slots > 0, "slots of scalable register is not valid"); -+ _scalable_reg_slots = slots; -+ } -+ -+ bool is_scalable() { -+#ifdef ASSERT -+ if (_is_scalable) { -+ // Should only be a vector for now, but it could also be a RegVMask in future. -+ assert(_is_vector && (_num_regs == RegMask::SlotsPerVecA), "unexpected scalable reg"); -+ } -+#endif -+ return _is_scalable; -+ } -+ - private: - // Number of physical registers this live range uses when it colors - // Architecture and register-set dependent -@@ -172,6 +197,8 @@ public: - uint _is_oop:1, // Live-range holds an oop - _is_float:1, // True if in float registers - _is_vector:1, // True if in vector registers -+ _is_scalable:1, // True if register size is scalable -+ // e.g. Arm SVE vector/predicate registers. - _was_spilled1:1, // True if prior spilling on def - _was_spilled2:1, // True if twice prior spilling on def - _is_bound:1, // live range starts life with no -diff --git a/src/hotspot/share/opto/matcher.cpp b/src/hotspot/share/opto/matcher.cpp -index 4cc7580a8..4fb732161 100644 ---- a/src/hotspot/share/opto/matcher.cpp -+++ b/src/hotspot/share/opto/matcher.cpp -@@ -84,6 +84,7 @@ Matcher::Matcher() - idealreg2spillmask [Op_RegF] = NULL; - idealreg2spillmask [Op_RegD] = NULL; - idealreg2spillmask [Op_RegP] = NULL; -+ idealreg2spillmask [Op_VecA] = NULL; - idealreg2spillmask [Op_VecS] = NULL; - idealreg2spillmask [Op_VecD] = NULL; - idealreg2spillmask [Op_VecX] = NULL; -@@ -97,6 +98,7 @@ Matcher::Matcher() - idealreg2debugmask [Op_RegF] = NULL; - idealreg2debugmask [Op_RegD] = NULL; - idealreg2debugmask [Op_RegP] = NULL; -+ idealreg2debugmask [Op_VecA] = NULL; - idealreg2debugmask [Op_VecS] = NULL; - idealreg2debugmask [Op_VecD] = NULL; - idealreg2debugmask [Op_VecX] = NULL; -@@ -110,6 +112,7 @@ Matcher::Matcher() - idealreg2mhdebugmask[Op_RegF] = NULL; - idealreg2mhdebugmask[Op_RegD] = NULL; - idealreg2mhdebugmask[Op_RegP] = NULL; -+ idealreg2mhdebugmask[Op_VecA] = NULL; - idealreg2mhdebugmask[Op_VecS] = NULL; - idealreg2mhdebugmask[Op_VecD] = NULL; - idealreg2mhdebugmask[Op_VecX] = NULL; -@@ -417,6 +420,8 @@ static RegMask *init_input_masks( uint size, RegMask &ret_adr, RegMask &fp ) { - return rms; - } - -+#define NOF_STACK_MASKS (3*6+6) -+ - //---------------------------init_first_stack_mask----------------------------- - // Create the initial stack mask used by values spilling to the stack. - // Disallow any debug info in outgoing argument areas by setting the -@@ -424,7 +429,12 @@ static RegMask *init_input_masks( uint size, RegMask &ret_adr, RegMask &fp ) { - void Matcher::init_first_stack_mask() { - - // Allocate storage for spill masks as masks for the appropriate load type. -- RegMask *rms = (RegMask*)C->comp_arena()->Amalloc_D(sizeof(RegMask) * (3*6+5)); -+ RegMask *rms = (RegMask*)C->comp_arena()->Amalloc_D(sizeof(RegMask) * NOF_STACK_MASKS); -+ -+ // Initialize empty placeholder masks into the newly allocated arena -+ for (int i = 0; i < NOF_STACK_MASKS; i++) { -+ new (rms + i) RegMask(); -+ } - - idealreg2spillmask [Op_RegN] = &rms[0]; - idealreg2spillmask [Op_RegI] = &rms[1]; -@@ -447,11 +457,12 @@ void Matcher::init_first_stack_mask() { - idealreg2mhdebugmask[Op_RegD] = &rms[16]; - idealreg2mhdebugmask[Op_RegP] = &rms[17]; - -- idealreg2spillmask [Op_VecS] = &rms[18]; -- idealreg2spillmask [Op_VecD] = &rms[19]; -- idealreg2spillmask [Op_VecX] = &rms[20]; -- idealreg2spillmask [Op_VecY] = &rms[21]; -- idealreg2spillmask [Op_VecZ] = &rms[22]; -+ idealreg2spillmask [Op_VecA] = &rms[18]; -+ idealreg2spillmask [Op_VecS] = &rms[19]; -+ idealreg2spillmask [Op_VecD] = &rms[20]; -+ idealreg2spillmask [Op_VecX] = &rms[21]; -+ idealreg2spillmask [Op_VecY] = &rms[22]; -+ idealreg2spillmask [Op_VecZ] = &rms[23]; - - OptoReg::Name i; - -@@ -478,6 +489,7 @@ void Matcher::init_first_stack_mask() { - // Keep spill masks aligned. - aligned_stack_mask.clear_to_pairs(); - assert(aligned_stack_mask.is_AllStack(), "should be infinite stack"); -+ RegMask scalable_stack_mask = aligned_stack_mask; - - *idealreg2spillmask[Op_RegP] = *idealreg2regmask[Op_RegP]; - #ifdef _LP64 -@@ -548,28 +560,48 @@ void Matcher::init_first_stack_mask() { - *idealreg2spillmask[Op_VecZ] = *idealreg2regmask[Op_VecZ]; - idealreg2spillmask[Op_VecZ]->OR(aligned_stack_mask); - } -- if (UseFPUForSpilling) { -- // This mask logic assumes that the spill operations are -- // symmetric and that the registers involved are the same size. -- // On sparc for instance we may have to use 64 bit moves will -- // kill 2 registers when used with F0-F31. -- idealreg2spillmask[Op_RegI]->OR(*idealreg2regmask[Op_RegF]); -- idealreg2spillmask[Op_RegF]->OR(*idealreg2regmask[Op_RegI]); -+ -+ if (Matcher::supports_scalable_vector()) { -+ int k = 1; -+ OptoReg::Name in = OptoReg::add(_in_arg_limit, -1); -+ // Exclude last input arg stack slots to avoid spilling vector register there, -+ // otherwise vector spills could stomp over stack slots in caller frame. -+ for (; (in >= init_in) && (k < scalable_vector_reg_size(T_FLOAT)); k++) { -+ scalable_stack_mask.Remove(in); -+ in = OptoReg::add(in, -1); -+ } -+ -+ // For VecA -+ scalable_stack_mask.clear_to_sets(RegMask::SlotsPerVecA); -+ assert(scalable_stack_mask.is_AllStack(), "should be infinite stack"); -+ *idealreg2spillmask[Op_VecA] = *idealreg2regmask[Op_VecA]; -+ idealreg2spillmask[Op_VecA]->OR(scalable_stack_mask); -+ } else { -+ *idealreg2spillmask[Op_VecA] = RegMask::Empty; -+ } -+ -+ if (UseFPUForSpilling) { -+ // This mask logic assumes that the spill operations are -+ // symmetric and that the registers involved are the same size. -+ // On sparc for instance we may have to use 64 bit moves will -+ // kill 2 registers when used with F0-F31. -+ idealreg2spillmask[Op_RegI]->OR(*idealreg2regmask[Op_RegF]); -+ idealreg2spillmask[Op_RegF]->OR(*idealreg2regmask[Op_RegI]); - #ifdef _LP64 -- idealreg2spillmask[Op_RegN]->OR(*idealreg2regmask[Op_RegF]); -- idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]); -- idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]); -- idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegD]); -+ idealreg2spillmask[Op_RegN]->OR(*idealreg2regmask[Op_RegF]); -+ idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]); -+ idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]); -+ idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegD]); - #else -- idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegF]); -+ idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegF]); - #ifdef ARM -- // ARM has support for moving 64bit values between a pair of -- // integer registers and a double register -- idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]); -- idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]); -+ // ARM has support for moving 64bit values between a pair of -+ // integer registers and a double register -+ idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]); -+ idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]); - #endif - #endif -- } -+ } - - // Make up debug masks. Any spill slot plus callee-save registers. - // Caller-save registers are assumed to be trashable by the various -@@ -872,6 +904,10 @@ void Matcher::init_spill_mask( Node *ret ) { - idealreg2regmask[Op_RegP] = &spillP->out_RegMask(); - - // Vector regmasks. -+ if (Matcher::supports_scalable_vector()) { -+ MachNode *spillVectA = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTA)); -+ idealreg2regmask[Op_VecA] = &spillVectA->out_RegMask(); -+ } - if (Matcher::vector_size_supported(T_BYTE,4)) { - TypeVect::VECTS = TypeVect::make(T_BYTE, 4); - MachNode *spillVectS = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTS)); -@@ -1575,7 +1611,6 @@ Node* Matcher::Label_Root(const Node* n, State* svec, Node* control, Node*& mem) - } - } - -- - // Call DFA to match this node, and return - svec->DFA( n->Opcode(), n ); - diff --git a/src/hotspot/share/opto/matcher.hpp b/src/hotspot/share/opto/matcher.hpp -index 244e3d1f8..9a8307102 100644 +index ed890f88e..9a8307102 100644 --- a/src/hotspot/share/opto/matcher.hpp +++ b/src/hotspot/share/opto/matcher.hpp @@ -310,7 +310,7 @@ public: @@ -7583,337 +6165,6 @@ index 244e3d1f8..9a8307102 100644 // Some microarchitectures have mask registers used on vectors static const bool has_predicated_vectors(void); -@@ -333,6 +333,10 @@ public: - Matcher::min_vector_size(bt) <= size); - } - -+ static const bool supports_scalable_vector(); -+ // Actual max scalable vector register length. -+ static const int scalable_vector_reg_size(const BasicType bt); -+ - // Vector ideal reg - static const uint vector_ideal_reg(int len); - static const uint vector_shift_count_ideal_reg(int len); -diff --git a/src/hotspot/share/opto/opcodes.cpp b/src/hotspot/share/opto/opcodes.cpp -index e31e8d847..1a826d8ba 100644 ---- a/src/hotspot/share/opto/opcodes.cpp -+++ b/src/hotspot/share/opto/opcodes.cpp -@@ -1,5 +1,5 @@ - /* -- * Copyright (c) 1998, 2012, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 1998, 2020, Oracle and/or its affiliates. All rights reserved. - * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. - * - * This code is free software; you can redistribute it and/or modify it -@@ -38,12 +38,14 @@ const char *NodeClassNames[] = { - "RegF", - "RegD", - "RegL", -- "RegFlags", -+ "VecA", - "VecS", - "VecD", - "VecX", - "VecY", - "VecZ", -+ "RegVMask", -+ "RegFlags", - "_last_machine_leaf", - #include "classes.hpp" - "_last_class_name", -diff --git a/src/hotspot/share/opto/opcodes.hpp b/src/hotspot/share/opto/opcodes.hpp -index ae3d61ce0..ec96ba055 100644 ---- a/src/hotspot/share/opto/opcodes.hpp -+++ b/src/hotspot/share/opto/opcodes.hpp -@@ -1,5 +1,5 @@ - /* -- * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved. - * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. - * - * This code is free software; you can redistribute it and/or modify it -@@ -37,11 +37,13 @@ enum Opcodes { - macro(RegF) // Machine float register - macro(RegD) // Machine double register - macro(RegL) // Machine long register -+ macro(VecA) // Machine vectora register - macro(VecS) // Machine vectors register - macro(VecD) // Machine vectord register - macro(VecX) // Machine vectorx register - macro(VecY) // Machine vectory register - macro(VecZ) // Machine vectorz register -+ macro(RegVMask) // Vector mask/predicate register - macro(RegFlags) // Machine flags register - _last_machine_leaf, // Split between regular opcodes and machine - #include "classes.hpp" -diff --git a/src/hotspot/share/opto/postaloc.cpp b/src/hotspot/share/opto/postaloc.cpp -index d572ac9fe..3514b37bc 100644 ---- a/src/hotspot/share/opto/postaloc.cpp -+++ b/src/hotspot/share/opto/postaloc.cpp -@@ -1,5 +1,5 @@ - /* -- * Copyright (c) 1998, 2016, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 1998, 2020, Oracle and/or its affiliates. All rights reserved. - * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. - * - * This code is free software; you can redistribute it and/or modify it -@@ -266,9 +266,9 @@ int PhaseChaitin::elide_copy( Node *n, int k, Block *current_block, Node_List &v - Node *val = skip_copies(n->in(k)); - if (val == x) return blk_adjust; // No progress? - -- int n_regs = RegMask::num_registers(val->ideal_reg()); - uint val_idx = _lrg_map.live_range_id(val); - OptoReg::Name val_reg = lrgs(val_idx).reg(); -+ int n_regs = RegMask::num_registers(val->ideal_reg(), lrgs(val_idx)); - - // See if it happens to already be in the correct register! - // (either Phi's direct register, or the common case of the name -@@ -305,8 +305,26 @@ int PhaseChaitin::elide_copy( Node *n, int k, Block *current_block, Node_List &v - } - - Node *vv = value[reg]; -+ // For scalable register, number of registers may be inconsistent between -+ // "val_reg" and "reg". For example, when "val" resides in register -+ // but "reg" is located in stack. -+ if (lrgs(val_idx).is_scalable()) { -+ assert(val->ideal_reg() == Op_VecA, "scalable vector register"); -+ if (OptoReg::is_stack(reg)) { -+ n_regs = lrgs(val_idx).scalable_reg_slots(); -+ } else { -+ n_regs = RegMask::SlotsPerVecA; -+ } -+ } - if (n_regs > 1) { // Doubles and vectors check for aligned-adjacent set -- uint last = (n_regs-1); // Looking for the last part of a set -+ uint last; -+ if (lrgs(val_idx).is_scalable()) { -+ assert(val->ideal_reg() == Op_VecA, "scalable vector register"); -+ // For scalable vector register, regmask is always SlotsPerVecA bits aligned -+ last = RegMask::SlotsPerVecA - 1; -+ } else { -+ last = (n_regs-1); // Looking for the last part of a set -+ } - if ((reg&last) != last) continue; // Wrong part of a set - if (!register_contains_value(vv, reg, n_regs, value)) continue; // Different value - } -@@ -591,7 +609,7 @@ void PhaseChaitin::post_allocate_copy_removal() { - uint k; - Node *phi = block->get_node(j); - uint pidx = _lrg_map.live_range_id(phi); -- OptoReg::Name preg = lrgs(_lrg_map.live_range_id(phi)).reg(); -+ OptoReg::Name preg = lrgs(pidx).reg(); - - // Remove copies remaining on edges. Check for junk phi. - Node *u = NULL; -@@ -619,7 +637,7 @@ void PhaseChaitin::post_allocate_copy_removal() { - if( pidx ) { - value.map(preg,phi); - regnd.map(preg,phi); -- int n_regs = RegMask::num_registers(phi->ideal_reg()); -+ int n_regs = RegMask::num_registers(phi->ideal_reg(), lrgs(pidx)); - for (int l = 1; l < n_regs; l++) { - OptoReg::Name preg_lo = OptoReg::add(preg,-l); - value.map(preg_lo,phi); -@@ -663,7 +681,7 @@ void PhaseChaitin::post_allocate_copy_removal() { - regnd.map(ureg, def); - // Record other half of doubles - uint def_ideal_reg = def->ideal_reg(); -- int n_regs = RegMask::num_registers(def_ideal_reg); -+ int n_regs = RegMask::num_registers(def_ideal_reg, lrgs(_lrg_map.live_range_id(def))); - for (int l = 1; l < n_regs; l++) { - OptoReg::Name ureg_lo = OptoReg::add(ureg,-l); - if (!value[ureg_lo] && -@@ -707,7 +725,7 @@ void PhaseChaitin::post_allocate_copy_removal() { - } - - uint n_ideal_reg = n->ideal_reg(); -- int n_regs = RegMask::num_registers(n_ideal_reg); -+ int n_regs = RegMask::num_registers(n_ideal_reg, lrgs(lidx)); - if (n_regs == 1) { - // If Node 'n' does not change the value mapped by the register, - // then 'n' is a useless copy. Do not update the register->node -diff --git a/src/hotspot/share/opto/regmask.cpp b/src/hotspot/share/opto/regmask.cpp -index 2e04c42eb..dd9b5476b 100644 ---- a/src/hotspot/share/opto/regmask.cpp -+++ b/src/hotspot/share/opto/regmask.cpp -@@ -1,5 +1,5 @@ - /* -- * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved. - * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. - * - * This code is free software; you can redistribute it and/or modify it -@@ -24,6 +24,7 @@ - - #include "precompiled.hpp" - #include "opto/ad.hpp" -+#include "opto/chaitin.hpp" - #include "opto/compile.hpp" - #include "opto/matcher.hpp" - #include "opto/node.hpp" -@@ -116,30 +117,47 @@ const RegMask RegMask::Empty( - - //============================================================================= - bool RegMask::is_vector(uint ireg) { -- return (ireg == Op_VecS || ireg == Op_VecD || -+ return (ireg == Op_VecA || ireg == Op_VecS || ireg == Op_VecD || - ireg == Op_VecX || ireg == Op_VecY || ireg == Op_VecZ ); - } - - int RegMask::num_registers(uint ireg) { - switch(ireg) { - case Op_VecZ: -- return 16; -+ return SlotsPerVecZ; - case Op_VecY: -- return 8; -+ return SlotsPerVecY; - case Op_VecX: -- return 4; -+ return SlotsPerVecX; - case Op_VecD: -+ return SlotsPerVecD; - case Op_RegD: - case Op_RegL: - #ifdef _LP64 - case Op_RegP: - #endif - return 2; -+ case Op_VecA: -+ assert(Matcher::supports_scalable_vector(), "does not support scalable vector"); -+ return SlotsPerVecA; - } - // Op_VecS and the rest ideal registers. - return 1; - } - -+int RegMask::num_registers(uint ireg, LRG &lrg) { -+ int n_regs = num_registers(ireg); -+ -+ // assigned is OptoReg which is selected by register allocator -+ OptoReg::Name assigned = lrg.reg(); -+ assert(OptoReg::is_valid(assigned), "should be valid opto register"); -+ -+ if (lrg.is_scalable() && OptoReg::is_stack(assigned)) { -+ n_regs = lrg.scalable_reg_slots(); -+ } -+ return n_regs; -+} -+ - //------------------------------find_first_pair-------------------------------- - // Find the lowest-numbered register pair in the mask. Return the - // HIGHEST register number in the pair, or BAD if no pairs. -@@ -238,14 +256,30 @@ int RegMask::is_bound_pair() const { - return true; - } - -+// Check that whether given reg number with size is valid -+// for current regmask, where reg is the highest number. -+bool RegMask::is_valid_reg(OptoReg::Name reg, const int size) const { -+ for (int i = 0; i < size; i++) { -+ if (!Member(reg - i)) { -+ return false; -+ } -+ } -+ return true; -+} -+ - // only indicies of power 2 are accessed, so index 3 is only filled in for storage. - static int low_bits[5] = { 0x55555555, 0x11111111, 0x01010101, 0x00000000, 0x00010001 }; - //------------------------------find_first_set--------------------------------- - // Find the lowest-numbered register set in the mask. Return the - // HIGHEST register number in the set, or BAD if no sets. - // Works also for size 1. --OptoReg::Name RegMask::find_first_set(const int size) const { -- verify_sets(size); -+OptoReg::Name RegMask::find_first_set(LRG &lrg, const int size) const { -+ if (lrg.is_scalable()) { -+ // For scalable vector register, regmask is SlotsPerVecA bits aligned. -+ assert(is_aligned_sets(SlotsPerVecA), "mask is not aligned, adjacent sets"); -+ } else { -+ assert(is_aligned_sets(size), "mask is not aligned, adjacent sets"); -+ } - for (int i = 0; i < RM_SIZE; i++) { - if (_A[i]) { // Found some bits - int bit = _A[i] & -_A[i]; // Extract low bit -@@ -325,12 +359,16 @@ bool RegMask::is_aligned_sets(const int size) const { - while (bits) { // Check bits for pairing - int bit = bits & -bits; // Extract low bit - // Low bit is not odd means its mis-aligned. -- if ((bit & low_bits_mask) == 0) return false; -+ if ((bit & low_bits_mask) == 0) { -+ return false; -+ } - // Do extra work since (bit << size) may overflow. - int hi_bit = bit << (size-1); // high bit - int set = hi_bit + ((hi_bit-1) & ~(bit-1)); - // Check for aligned adjacent bits in this set -- if ((bits & set) != set) return false; -+ if ((bits & set) != set) { -+ return false; -+ } - bits -= set; // Remove this set - } - } -diff --git a/src/hotspot/share/opto/regmask.hpp b/src/hotspot/share/opto/regmask.hpp -index c64d08795..b733b87ad 100644 ---- a/src/hotspot/share/opto/regmask.hpp -+++ b/src/hotspot/share/opto/regmask.hpp -@@ -1,5 +1,5 @@ - /* -- * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved. - * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. - * - * This code is free software; you can redistribute it and/or modify it -@@ -28,6 +28,8 @@ - #include "code/vmreg.hpp" - #include "opto/optoreg.hpp" - -+class LRG; -+ - // Some fun naming (textual) substitutions: - // - // RegMask::get_low_elem() ==> RegMask::find_first_elem() -@@ -95,11 +97,13 @@ public: - // requirement is internal to the allocator, and independent of any - // particular platform. - enum { SlotsPerLong = 2, -+ SlotsPerVecA = 8, - SlotsPerVecS = 1, - SlotsPerVecD = 2, - SlotsPerVecX = 4, - SlotsPerVecY = 8, -- SlotsPerVecZ = 16 }; -+ SlotsPerVecZ = 16, -+ }; - - // A constructor only used by the ADLC output. All mask fields are filled - // in directly. Calls to this look something like RM(1,2,3,4); -@@ -204,10 +208,14 @@ public: - return false; - } - -+ // Check that whether given reg number with size is valid -+ // for current regmask, where reg is the highest number. -+ bool is_valid_reg(OptoReg::Name reg, const int size) const; -+ - // Find the lowest-numbered register set in the mask. Return the - // HIGHEST register number in the set, or BAD if no sets. - // Assert that the mask contains only bit sets. -- OptoReg::Name find_first_set(const int size) const; -+ OptoReg::Name find_first_set(LRG &lrg, const int size) const; - - // Clear out partial bits; leave only aligned adjacent bit sets of size. - void clear_to_sets(const int size); -@@ -226,6 +234,7 @@ public: - - static bool is_vector(uint ireg); - static int num_registers(uint ireg); -+ static int num_registers(uint ireg, LRG &lrg); - - // Fast overlap test. Non-zero if any registers in common. - int overlap( const RegMask &rm ) const { diff --git a/src/hotspot/share/opto/superword.cpp b/src/hotspot/share/opto/superword.cpp index 92f70b77d..ed67928f5 100644 --- a/src/hotspot/share/opto/superword.cpp @@ -7932,155 +6183,6 @@ index 92f70b77d..ed67928f5 100644 assert(lpt->_head->is_CountedLoop(), "must be"); CountedLoopNode *cl = lpt->_head->as_CountedLoop(); -diff --git a/src/hotspot/share/opto/type.cpp b/src/hotspot/share/opto/type.cpp -index 223b7a1c6..1b46cb452 100644 ---- a/src/hotspot/share/opto/type.cpp -+++ b/src/hotspot/share/opto/type.cpp -@@ -79,6 +79,7 @@ const Type::TypeInfo Type::_type_info[Type::lastype] = { - { Bad, T_ILLEGAL, "vectory:", false, 0, relocInfo::none }, // VectorY - { Bad, T_ILLEGAL, "vectorz:", false, 0, relocInfo::none }, // VectorZ - #else // all other -+ { Bad, T_ILLEGAL, "vectora:", false, Op_VecA, relocInfo::none }, // VectorA. - { Bad, T_ILLEGAL, "vectors:", false, Op_VecS, relocInfo::none }, // VectorS - { Bad, T_ILLEGAL, "vectord:", false, Op_VecD, relocInfo::none }, // VectorD - { Bad, T_ILLEGAL, "vectorx:", false, Op_VecX, relocInfo::none }, // VectorX -@@ -655,6 +656,10 @@ void Type::Initialize_shared(Compile* current) { - // get_zero_type() should not happen for T_CONFLICT - _zero_type[T_CONFLICT]= NULL; - -+ if (Matcher::supports_scalable_vector()) { -+ TypeVect::VECTA = TypeVect::make(T_BYTE, Matcher::scalable_vector_reg_size(T_BYTE)); -+ } -+ - // Vector predefined types, it needs initialized _const_basic_type[]. - if (Matcher::vector_size_supported(T_BYTE,4)) { - TypeVect::VECTS = TypeVect::make(T_BYTE,4); -@@ -671,6 +676,8 @@ void Type::Initialize_shared(Compile* current) { - if (Matcher::vector_size_supported(T_FLOAT,16)) { - TypeVect::VECTZ = TypeVect::make(T_FLOAT,16); - } -+ -+ mreg2type[Op_VecA] = TypeVect::VECTA; - mreg2type[Op_VecS] = TypeVect::VECTS; - mreg2type[Op_VecD] = TypeVect::VECTD; - mreg2type[Op_VecX] = TypeVect::VECTX; -@@ -990,6 +997,7 @@ const Type::TYPES Type::dual_type[Type::lastype] = { - - Bad, // Tuple - handled in v-call - Bad, // Array - handled in v-call -+ Bad, // VectorA - handled in v-call - Bad, // VectorS - handled in v-call - Bad, // VectorD - handled in v-call - Bad, // VectorX - handled in v-call -@@ -1890,7 +1898,6 @@ const TypeTuple *TypeTuple::LONG_PAIR; - const TypeTuple *TypeTuple::INT_CC_PAIR; - const TypeTuple *TypeTuple::LONG_CC_PAIR; - -- - //------------------------------make------------------------------------------- - // Make a TypeTuple from the range of a method signature - const TypeTuple *TypeTuple::make_range(ciSignature* sig) { -@@ -2262,6 +2269,7 @@ bool TypeAry::ary_must_be_exact() const { - - //==============================TypeVect======================================= - // Convenience common pre-built types. -+const TypeVect *TypeVect::VECTA = NULL; // vector length agnostic - const TypeVect *TypeVect::VECTS = NULL; // 32-bit vectors - const TypeVect *TypeVect::VECTD = NULL; // 64-bit vectors - const TypeVect *TypeVect::VECTX = NULL; // 128-bit vectors -@@ -2272,10 +2280,11 @@ const TypeVect *TypeVect::VECTZ = NULL; // 512-bit vectors - const TypeVect* TypeVect::make(const Type *elem, uint length) { - BasicType elem_bt = elem->array_element_basic_type(); - assert(is_java_primitive(elem_bt), "only primitive types in vector"); -- assert(length > 1 && is_power_of_2(length), "vector length is power of 2"); - assert(Matcher::vector_size_supported(elem_bt, length), "length in range"); - int size = length * type2aelembytes(elem_bt); - switch (Matcher::vector_ideal_reg(size)) { -+ case Op_VecA: -+ return (TypeVect*)(new TypeVectA(elem, length))->hashcons(); - case Op_VecS: - return (TypeVect*)(new TypeVectS(elem, length))->hashcons(); - case Op_RegL: -@@ -2307,7 +2316,7 @@ const Type *TypeVect::xmeet( const Type *t ) const { - - default: // All else is a mistake - typerr(t); -- -+ case VectorA: - case VectorS: - case VectorD: - case VectorX: -@@ -2362,6 +2371,8 @@ bool TypeVect::empty(void) const { - #ifndef PRODUCT - void TypeVect::dump2(Dict &d, uint depth, outputStream *st) const { - switch (base()) { -+ case VectorA: -+ st->print("vectora["); break; - case VectorS: - st->print("vectors["); break; - case VectorD: -diff --git a/src/hotspot/share/opto/type.hpp b/src/hotspot/share/opto/type.hpp -index a7eec281e..6787b947d 100644 ---- a/src/hotspot/share/opto/type.hpp -+++ b/src/hotspot/share/opto/type.hpp -@@ -1,5 +1,5 @@ - /* -- * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved. - * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. - * - * This code is free software; you can redistribute it and/or modify it -@@ -53,6 +53,7 @@ class TypeNarrowKlass; - class TypeAry; - class TypeTuple; - class TypeVect; -+class TypeVectA; - class TypeVectS; - class TypeVectD; - class TypeVectX; -@@ -87,6 +88,7 @@ public: - - Tuple, // Method signature or object layout - Array, // Array types -+ VectorA, // (Scalable) Vector types for vector length agnostic - VectorS, // 32bit Vector types - VectorD, // 64bit Vector types - VectorX, // 128bit Vector types -@@ -758,6 +760,7 @@ public: - virtual const Type *xmeet( const Type *t) const; - virtual const Type *xdual() const; // Compute dual right now. - -+ static const TypeVect *VECTA; - static const TypeVect *VECTS; - static const TypeVect *VECTD; - static const TypeVect *VECTX; -@@ -769,6 +772,11 @@ public: - #endif - }; - -+class TypeVectA : public TypeVect { -+ friend class TypeVect; -+ TypeVectA(const Type* elem, uint length) : TypeVect(VectorA, elem, length) {} -+}; -+ - class TypeVectS : public TypeVect { - friend class TypeVect; - TypeVectS(const Type* elem, uint length) : TypeVect(VectorS, elem, length) {} -@@ -1619,12 +1627,12 @@ inline const TypeAry *Type::is_ary() const { - } - - inline const TypeVect *Type::is_vect() const { -- assert( _base >= VectorS && _base <= VectorZ, "Not a Vector" ); -+ assert( _base >= VectorA && _base <= VectorZ, "Not a Vector" ); - return (TypeVect*)this; - } - - inline const TypeVect *Type::isa_vect() const { -- return (_base >= VectorS && _base <= VectorZ) ? (TypeVect*)this : NULL; -+ return (_base >= VectorA && _base <= VectorZ) ? (TypeVect*)this : NULL; - } - - inline const TypePtr *Type::is_ptr() const { diff --git a/src/hotspot/share/opto/vectornode.cpp b/src/hotspot/share/opto/vectornode.cpp index 1f2cf2c64..6867177c1 100644 --- a/src/hotspot/share/opto/vectornode.cpp @@ -8110,214 +6212,6 @@ index 1f2cf2c64..6867177c1 100644 } return false; } -diff --git a/test/hotspot/jtreg/compiler/c2/aarch64/TestSVEWithJNI.java b/test/hotspot/jtreg/compiler/c2/aarch64/TestSVEWithJNI.java -new file mode 100644 -index 000000000..dc15ca800 ---- /dev/null -+++ b/test/hotspot/jtreg/compiler/c2/aarch64/TestSVEWithJNI.java -@@ -0,0 +1,128 @@ -+/* -+* Copyright (c) 2020, Oracle and/or its affiliates. All rights reserved. -+* Copyright (c) 2020, Arm Limited. All rights reserved. -+* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+* -+* This code is free software; you can redistribute it and/or modify it -+* under the terms of the GNU General Public License version 2 only, as -+* published by the Free Software Foundation. -+* -+* This code is distributed in the hope that it will be useful, but WITHOUT -+* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+* version 2 for more details (a copy is included in the LICENSE file that -+* accompanied this code). -+* -+* You should have received a copy of the GNU General Public License version -+* 2 along with this work; if not, write to the Free Software Foundation, -+* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+* -+* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+* or visit www.oracle.com if you need additional information or have any -+* questions. -+* -+*/ -+ -+/** -+ * @test -+ * -+ * @requires os.arch == "aarch64" & vm.compiler2.enabled -+ * @summary Verify VM SVE checking behavior -+ * @library /test/lib -+ * @run main/othervm/native compiler.c2.aarch64.TestSVEWithJNI -+ * -+ */ -+ -+package compiler.c2.aarch64; -+ -+import java.util.ArrayList; -+import java.util.Collections; -+import java.util.List; -+import jdk.test.lib.process.ProcessTools; -+import jdk.test.lib.process.OutputAnalyzer; -+ -+public class TestSVEWithJNI { -+ static { -+ System.loadLibrary("TestSVEWithJNI"); -+ } -+ -+ static final int EXIT_CODE = 99; -+ // Returns a nonnegative on success, or a negative value on error. -+ public static native int setVectorLength(int arg); -+ // Returns a nonnegative value on success, or a negative value on error. -+ public static native int getVectorLength(); -+ -+ public static final String MSG = "Current Vector Size: "; -+ public static void testNormal() { -+ int vlen = getVectorLength(); -+ System.out.println(MSG + vlen); -+ // Should be fine if no vector length changed. -+ if (setVectorLength(vlen) < 0) { -+ throw new Error("Error in setting vector length."); -+ } -+ } -+ -+ public static void testAbort() { -+ int vlen = getVectorLength(); -+ if (vlen <= 16) { -+ throw new Error("Error: unsupported vector length."); -+ } -+ if (setVectorLength(16) < 0) { -+ throw new Error("Error: setting vector length failed."); -+ } -+ } -+ -+ public static ProcessBuilder createProcessBuilder(String [] args, String mode) { -+ List vmopts = new ArrayList<>(); -+ String testjdkPath = System.getProperty("test.jdk"); -+ Collections.addAll(vmopts, "-Dtest.jdk=" + testjdkPath); -+ Collections.addAll(vmopts, args); -+ Collections.addAll(vmopts, TestSVEWithJNI.class.getName(), mode); -+ return ProcessTools.createJavaProcessBuilder(vmopts.toArray(new String[vmopts.size()])); -+ } -+ -+ public static void main(String [] args) throws Exception { -+ if (args.length == 0) { -+ int vlen = getVectorLength(); -+ if (vlen < 0) { -+ return; -+ } -+ String [][] testOpts = { -+ {"-Xint", "-XX:UseSVE=1"}, -+ {"-Xcomp", "-XX:UseSVE=1"}, -+ }; -+ ProcessBuilder pb; -+ OutputAnalyzer output; -+ for (String [] opts : testOpts) { -+ pb = createProcessBuilder(opts, "normal"); -+ output = new OutputAnalyzer(pb.start()); -+ output.shouldHaveExitValue(EXIT_CODE); -+ -+ pb = createProcessBuilder(opts, "abort"); -+ output = new OutputAnalyzer(pb.start()); -+ output.shouldNotHaveExitValue(EXIT_CODE); -+ output.shouldMatch("(error|Error|ERROR)"); -+ } -+ -+ // Verify MaxVectorSize -+ -+ // Any SVE architecture should support 128-bit vector size. -+ pb = createProcessBuilder(new String []{"-XX:UseSVE=1", "-XX:MaxVectorSize=16"}, "normal"); -+ output = new OutputAnalyzer(pb.start()); -+ output.shouldHaveExitValue(EXIT_CODE); -+ output.shouldContain(MSG + 16); -+ -+ // An unsupported large vector size value. -+ pb = createProcessBuilder(new String []{"-XX:UseSVE=1", "-XX:MaxVectorSize=512"}, "normal"); -+ output = new OutputAnalyzer(pb.start()); -+ output.shouldHaveExitValue(EXIT_CODE); -+ output.shouldContain("warning"); -+ } else if (args[0].equals("normal")) { -+ testNormal(); -+ System.exit(EXIT_CODE); -+ } else if (args[0].equals("abort")) { -+ testAbort(); -+ System.exit(EXIT_CODE); -+ } -+ } -+} -diff --git a/test/hotspot/jtreg/compiler/c2/aarch64/libTestSVEWithJNI.c b/test/hotspot/jtreg/compiler/c2/aarch64/libTestSVEWithJNI.c -new file mode 100644 -index 000000000..0cb3ab0b5 ---- /dev/null -+++ b/test/hotspot/jtreg/compiler/c2/aarch64/libTestSVEWithJNI.c -@@ -0,0 +1,68 @@ -+/* -+* Copyright (c) 2020, Oracle and/or its affiliates. All rights reserved. -+* Copyright (c) 2020, Arm Limited. All rights reserved. -+* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+* -+* This code is free software; you can redistribute it and/or modify it -+* under the terms of the GNU General Public License version 2 only, as -+* published by the Free Software Foundation. -+* -+* This code is distributed in the hope that it will be useful, but WITHOUT -+* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+* version 2 for more details (a copy is included in the LICENSE file that -+* accompanied this code). -+* -+* You should have received a copy of the GNU General Public License version -+* 2 along with this work; if not, write to the Free Software Foundation, -+* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+* -+* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+* or visit www.oracle.com if you need additional information or have any -+* questions. -+* -+*/ -+ -+#ifdef __aarch64__ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#ifndef PR_SVE_GET_VL -+// For old toolchains which do not have SVE related macros defined. -+#define PR_SVE_SET_VL 50 -+#define PR_SVE_GET_VL 51 -+#endif -+ -+int get_current_thread_vl() { -+ return prctl(PR_SVE_GET_VL); -+} -+ -+int set_current_thread_vl(unsigned long arg) { -+ return prctl(PR_SVE_SET_VL, arg); -+} -+ -+#ifdef __cplusplus -+extern "C" { -+#endif -+ -+JNIEXPORT jint JNICALL Java_compiler_c2_aarch64_TestSVEWithJNI_setVectorLength -+(JNIEnv * env, jclass clz, jint length) { -+ return set_current_thread_vl(length); -+} -+ -+JNIEXPORT jint JNICALL Java_compiler_c2_aarch64_TestSVEWithJNI_getVectorLength -+(JNIEnv *env, jclass clz) { -+ return get_current_thread_vl(); -+} -+ -+ -+#ifdef __cplusplus -+} -+#endif -+ -+#endif -- -2.19.0 +2.19.1 diff --git a/8252103-support-Jmap-parallel-heap-inspection.patch b/8252103-support-Jmap-parallel-heap-inspection.patch new file mode 100755 index 0000000000000000000000000000000000000000..5f5267c61892604d52cc71ebccb7fe4c4aea4d22 --- /dev/null +++ b/8252103-support-Jmap-parallel-heap-inspection.patch @@ -0,0 +1,266 @@ +diff --git a/src/hotspot/share/gc/parallel/parallelScavengeHeap.cpp b/src/hotspot/share/gc/parallel/parallelScavengeHeap.cpp +index 820b4bef9..db5c41cd3 100644 +--- a/src/hotspot/share/gc/parallel/parallelScavengeHeap.cpp ++++ b/src/hotspot/share/gc/parallel/parallelScavengeHeap.cpp +@@ -525,6 +525,72 @@ void ParallelScavengeHeap::object_iterate(ObjectClosure* cl) { + } + + ++// The HeapBlockClaimer is used during parallel iteration over the heap, ++// allowing workers to claim heap areas ("blocks"), gaining exclusive rights to these. ++// The eden and survivor spaces are treated as single blocks as it is hard to divide ++// these spaces. ++// The old space is divided into fixed-size blocks. ++class HeapBlockClaimer : public StackObj { ++ size_t _claimed_index; ++ ++public: ++ static const size_t InvalidIndex = SIZE_MAX; ++ static const size_t EdenIndex = 0; ++ static const size_t SurvivorIndex = 1; ++ static const size_t NumNonOldGenClaims = 2; ++ ++ HeapBlockClaimer() : _claimed_index(EdenIndex) { } ++ // Claim the block and get the block index. ++ size_t claim_and_get_block() { ++ size_t block_index; ++ block_index = Atomic::add(1u, &_claimed_index) - 1; ++ ++ PSOldGen* old_gen = ParallelScavengeHeap::heap()->old_gen(); ++ size_t num_claims = old_gen->num_iterable_blocks() + NumNonOldGenClaims; ++ ++ return block_index < num_claims ? block_index : InvalidIndex; ++ } ++}; ++ ++void ParallelScavengeHeap::object_iterate_parallel(ObjectClosure* cl, ++ HeapBlockClaimer* claimer) { ++ size_t block_index = claimer->claim_and_get_block(); ++ // Iterate until all blocks are claimed ++ if (block_index == HeapBlockClaimer::EdenIndex) { ++ young_gen()->eden_space()->object_iterate(cl); ++ block_index = claimer->claim_and_get_block(); ++ } ++ if (block_index == HeapBlockClaimer::SurvivorIndex) { ++ young_gen()->from_space()->object_iterate(cl); ++ young_gen()->to_space()->object_iterate(cl); ++ block_index = claimer->claim_and_get_block(); ++ } ++ while (block_index != HeapBlockClaimer::InvalidIndex) { ++ old_gen()->object_iterate_block(cl, block_index - HeapBlockClaimer::NumNonOldGenClaims); ++ block_index = claimer->claim_and_get_block(); ++ } ++} ++ ++class PSScavengeParallelObjectIterator : public ParallelObjectIterator { ++private: ++ ParallelScavengeHeap* _heap; ++ HeapBlockClaimer _claimer; ++ ++public: ++ PSScavengeParallelObjectIterator() : ++ _heap(ParallelScavengeHeap::heap()), ++ _claimer() {} ++ ++ virtual void object_iterate(ObjectClosure* cl, uint worker_id) { ++ _heap->object_iterate_parallel(cl, &_claimer); ++ } ++}; ++ ++ParallelObjectIterator* ParallelScavengeHeap::parallel_object_iterator(uint thread_num) { ++ return new PSScavengeParallelObjectIterator(); ++} ++ ++ + HeapWord* ParallelScavengeHeap::block_start(const void* addr) const { + if (young_gen()->is_in_reserved(addr)) { + assert(young_gen()->is_in(addr), +diff --git a/src/hotspot/share/gc/parallel/parallelScavengeHeap.hpp b/src/hotspot/share/gc/parallel/parallelScavengeHeap.hpp +index 82aeba67a..b7c481949 100644 +--- a/src/hotspot/share/gc/parallel/parallelScavengeHeap.hpp ++++ b/src/hotspot/share/gc/parallel/parallelScavengeHeap.hpp +@@ -44,6 +44,7 @@ + class AdjoiningGenerations; + class GCHeapSummary; + class GCTaskManager; ++class HeapBlockClaimer; + class MemoryManager; + class MemoryPool; + class PSAdaptiveSizePolicy; +@@ -80,6 +81,8 @@ class ParallelScavengeHeap : public CollectedHeap { + MemoryPool* _survivor_pool; + MemoryPool* _old_pool; + ++ WorkGang _workers; ++ + virtual void initialize_serviceability(); + + void trace_heap(GCWhen::Type when, const GCTracer* tracer); +@@ -94,7 +97,20 @@ class ParallelScavengeHeap : public CollectedHeap { + + public: + ParallelScavengeHeap(GenerationSizer* policy) : +- CollectedHeap(), _collector_policy(policy), _death_march_count(0) { } ++ CollectedHeap(), ++ _collector_policy(policy), ++ _death_march_count(0), ++ _young_manager(NULL), ++ _old_manager(NULL), ++ _eden_pool(NULL), ++ _survivor_pool(NULL), ++ _old_pool(NULL), ++ _workers("GC Thread", ++ ParallelGCThreads, ++ true /* are_GC_task_threads */, ++ false /* are_ConcurrentGC_threads */) { ++ _workers.initialize_workers(); ++ } + + // For use by VM operations + enum CollectionType { +@@ -218,6 +234,8 @@ class ParallelScavengeHeap : public CollectedHeap { + + void object_iterate(ObjectClosure* cl); + void safe_object_iterate(ObjectClosure* cl) { object_iterate(cl); } ++ void object_iterate_parallel(ObjectClosure* cl, HeapBlockClaimer* claimer); ++ virtual ParallelObjectIterator* parallel_object_iterator(uint thread_num); + + HeapWord* block_start(const void* addr) const; + size_t block_size(const HeapWord* addr) const; +@@ -232,6 +250,7 @@ class ParallelScavengeHeap : public CollectedHeap { + virtual void print_gc_threads_on(outputStream* st) const; + virtual void gc_threads_do(ThreadClosure* tc) const; + virtual void print_tracing_info() const; ++ virtual WorkGang* get_safepoint_workers() { return &_workers; } + + void verify(VerifyOption option /* ignored */); + +diff --git a/src/hotspot/share/gc/parallel/psOldGen.cpp b/src/hotspot/share/gc/parallel/psOldGen.cpp +index 486bb7c87..830b1b758 100644 +--- a/src/hotspot/share/gc/parallel/psOldGen.cpp ++++ b/src/hotspot/share/gc/parallel/psOldGen.cpp +@@ -213,6 +213,38 @@ HeapWord* PSOldGen::allocate(size_t word_size) { + return res; + } + ++size_t PSOldGen::num_iterable_blocks() const { ++ return (object_space()->used_in_bytes() + IterateBlockSize - 1) / IterateBlockSize; ++} ++ ++void PSOldGen::object_iterate_block(ObjectClosure* cl, size_t block_index) { ++ size_t block_word_size = IterateBlockSize / HeapWordSize; ++ assert((block_word_size % (ObjectStartArray::block_size)) == 0, ++ "Block size not a multiple of start_array block"); ++ ++ MutableSpace *space = object_space(); ++ ++ HeapWord* begin = space->bottom() + block_index * block_word_size; ++ HeapWord* end = MIN2(space->top(), begin + block_word_size); ++ ++ if (!start_array()->object_starts_in_range(begin, end)) { ++ return; ++ } ++ ++ // Get object starting at or reaching into this block. ++ HeapWord* start = start_array()->object_start(begin); ++ if (start < begin) { ++ start += oop(start)->size(); ++ } ++ assert(start >= begin, ++ "Object address" PTR_FORMAT " must be larger or equal to block address at " PTR_FORMAT, ++ p2i(start), p2i(begin)); ++ // Iterate all objects until the end. ++ for (HeapWord* p = start; p < end; p += oop(p)->size()) { ++ cl->do_object(oop(p)); ++ } ++} ++ + HeapWord* PSOldGen::expand_and_allocate(size_t word_size) { + expand(word_size*HeapWordSize); + if (GCExpandToAllocateDelayMillis > 0) { +diff --git a/src/hotspot/share/gc/parallel/psOldGen.hpp b/src/hotspot/share/gc/parallel/psOldGen.hpp +index fa27f5a04..fa6e4849b 100644 +--- a/src/hotspot/share/gc/parallel/psOldGen.hpp ++++ b/src/hotspot/share/gc/parallel/psOldGen.hpp +@@ -59,6 +59,9 @@ class PSOldGen : public CHeapObj { + const size_t _min_gen_size; + const size_t _max_gen_size; + ++ // Block size for parallel iteration ++ static const size_t IterateBlockSize = 1024 * 1024; ++ + // Used when initializing the _name field. + static inline const char* select_name(); + +@@ -195,6 +198,14 @@ class PSOldGen : public CHeapObj { + void oop_iterate(OopIterateClosure* cl) { object_space()->oop_iterate(cl); } + void object_iterate(ObjectClosure* cl) { object_space()->object_iterate(cl); } + ++ // Number of blocks to be iterated over in the used part of old gen. ++ size_t num_iterable_blocks() const; ++ // Iterate the objects starting in block block_index within [bottom, top) of the ++ // old gen. The object just reaching into this block is not iterated over. ++ // A block is an evenly sized non-overlapping part of the old gen of ++ // IterateBlockSize bytes. ++ void object_iterate_block(ObjectClosure* cl, size_t block_index); ++ + // Debugging - do not use for time critical operations + virtual void print() const; + virtual void print_on(outputStream* st) const; +diff --git a/test/jdk/sun/tools/jmap/BasicJMapTest.java b/test/jdk/sun/tools/jmap/BasicJMapTest.java +index ad890f880..8658e6e5a 100644 +--- a/test/jdk/sun/tools/jmap/BasicJMapTest.java ++++ b/test/jdk/sun/tools/jmap/BasicJMapTest.java +@@ -46,6 +46,34 @@ import jdk.testlibrary.ProcessTools; + * @run main/timeout=240 BasicJMapTest + */ + ++/* ++ * @test id=Parallel ++ * @summary Unit test for jmap utility (Parallel GC) ++ * @key intermittent ++ * @library /lib/testlibrary ++ * @library /test/lib ++ * @build jdk.testlibrary.* ++ * @build jdk.test.lib.hprof.* ++ * @build jdk.test.lib.hprof.model.* ++ * @build jdk.test.lib.hprof.parser.* ++ * @build jdk.test.lib.hprof.util.* ++ * @run main/othervm/timeout=240 -XX:+UseParallelGC BasicJMapTest ++ */ ++ ++/* ++ * @test id=G1 ++ * @summary Unit test for jmap utility (G1 GC) ++ * @key intermittent ++ * @library /lib/testlibrary ++ * @library /test/lib ++ * @build jdk.testlibrary.* ++ * @build jdk.test.lib.hprof.* ++ * @build jdk.test.lib.hprof.model.* ++ * @build jdk.test.lib.hprof.parser.* ++ * @build jdk.test.lib.hprof.util.* ++ * @run main/othervm/timeout=240 -XX:+UseG1GC BasicJMapTest ++ */ ++ + /* + * @test id=CMS + * @summary Unit test for jmap utility (CMS GC) +@@ -98,6 +126,17 @@ public class BasicJMapTest { + output.shouldHaveExitValue(0); + } + ++ private static void testHistoMultipleParameters() throws Exception { ++ OutputAnalyzer output = jmap("-histo:parallel=2,live"); ++ output.shouldHaveExitValue(0); ++ output = jmap("-histo:live,parallel=2"); ++ output.shouldHaveExitValue(0); ++ output = jmap("-histo:parallel=2,all"); ++ output.shouldHaveExitValue(0); ++ output = jmap("-histo:all,parallel=2"); ++ output.shouldHaveExitValue(0); ++ } ++ + private static void testFinalizerInfo() throws Exception { + OutputAnalyzer output = jmap("-finalizerinfo"); + output.shouldHaveExitValue(0); diff --git a/Delete-expired-certificate-globalsignr2ca.patch b/Delete-expired-certificate-globalsignr2ca.patch deleted file mode 100755 index eefa275bc1dfb1b7a0bc96fcb727373238b89865..0000000000000000000000000000000000000000 --- a/Delete-expired-certificate-globalsignr2ca.patch +++ /dev/null @@ -1,189 +0,0 @@ -From 417887ac236f58b1ecba79826229295794a3e0be Mon Sep 17 00:00:00 2001 -From: zhangyipeng -Date: Wed, 15 Dec 2021 18:33:09 +0800 -Subject: [PATCH 2/2] Delete expired certificate - -DTS/AR: DTS2021112910463 -Summary: < JDK> : Delete expired certificate -LLT: NA -Patch Type: huawei -Bug url: NA ---- - make/data/cacerts/globalsignr2ca | 29 ------------- - make/data/cacerts/luxtrustglobalrootca | 28 ------------- - make/data/cacerts/quovadisrootca | 41 ------------------- - .../security/lib/cacerts/VerifyCACerts.java | 14 +------ - 4 files changed, 2 insertions(+), 110 deletions(-) - delete mode 100644 make/data/cacerts/globalsignr2ca - delete mode 100644 make/data/cacerts/luxtrustglobalrootca - delete mode 100644 make/data/cacerts/quovadisrootca - -diff --git a/make/data/cacerts/globalsignr2ca b/make/data/cacerts/globalsignr2ca -deleted file mode 100644 -index 746d1fab9..000000000 ---- a/make/data/cacerts/globalsignr2ca -+++ /dev/null -@@ -1,29 +0,0 @@ --Owner: CN=GlobalSign, O=GlobalSign, OU=GlobalSign Root CA - R2 --Issuer: CN=GlobalSign, O=GlobalSign, OU=GlobalSign Root CA - R2 --Serial number: 400000000010f8626e60d --Valid from: Fri Dec 15 08:00:00 GMT 2006 until: Wed Dec 15 08:00:00 GMT 2021 --Signature algorithm name: SHA1withRSA --Subject Public Key Algorithm: 2048-bit RSA key --Version: 3 -------BEGIN CERTIFICATE----- --MIIDujCCAqKgAwIBAgILBAAAAAABD4Ym5g0wDQYJKoZIhvcNAQEFBQAwTDEgMB4G --A1UECxMXR2xvYmFsU2lnbiBSb290IENBIC0gUjIxEzARBgNVBAoTCkdsb2JhbFNp --Z24xEzARBgNVBAMTCkdsb2JhbFNpZ24wHhcNMDYxMjE1MDgwMDAwWhcNMjExMjE1 --MDgwMDAwWjBMMSAwHgYDVQQLExdHbG9iYWxTaWduIFJvb3QgQ0EgLSBSMjETMBEG --A1UEChMKR2xvYmFsU2lnbjETMBEGA1UEAxMKR2xvYmFsU2lnbjCCASIwDQYJKoZI --hvcNAQEBBQADggEPADCCAQoCggEBAKbPJA6+Lm8omUVCxKs+IVSbC9N/hHD6ErPL --v4dfxn+G07IwXNb9rfF73OX4YJYJkhD10FPe+3t+c4isUoh7SqbKSaZeqKeMWhG8 --eoLrvozps6yWJQeXSpkqBy+0Hne/ig+1AnwblrjFuTosvNYSuetZfeLQBoZfXklq --tTleiDTsvHgMCJiEbKjNS7SgfQx5TfC4LcshytVsW33hoCmEofnTlEnLJGKRILzd --C9XZzPnqJworc5HGnRusyMvo4KD0L5CLTfuwNhv2GXqF4G3yYROIXJ/gkwpRl4pa --zq+r1feqCapgvdzZX99yqWATXgAByUr6P6TqBwMhAo6CygPCm48CAwEAAaOBnDCB --mTAOBgNVHQ8BAf8EBAMCAQYwDwYDVR0TAQH/BAUwAwEB/zAdBgNVHQ4EFgQUm+IH --V2ccHsBqBt5ZtJot39wZhi4wNgYDVR0fBC8wLTAroCmgJ4YlaHR0cDovL2NybC5n --bG9iYWxzaWduLm5ldC9yb290LXIyLmNybDAfBgNVHSMEGDAWgBSb4gdXZxwewGoG --3lm0mi3f3BmGLjANBgkqhkiG9w0BAQUFAAOCAQEAmYFThxxol4aR7OBKuEQLq4Gs --J0/WwbgcQ3izDJr86iw8bmEbTUsp9Z8FHSbBuOmDAGJFtqkIk7mpM0sYmsL4h4hO --291xNBrBVNpGP+DTKqttVCL1OmLNIG+6KYnX3ZHu01yiPqFbQfXf5WRDLenVOavS --ot+3i9DAgBkcRcAtjOj4LaR0VknFBbVPFd5uRHg5h6h+u/N5GJG79G+dwfCMNYxd --AfvDbbnvRG15RjF+Cv6pgsH/76tuIMRQyV+dTZsXjAzlAcmgQWpzU/qlULRuJQ/7 --TBj0/VLZjmmx6BEP3ojY+x1J96relc8geMJgEtslQIxq/H5COEBkEveegeGTLg== -------END CERTIFICATE----- -diff --git a/make/data/cacerts/luxtrustglobalrootca b/make/data/cacerts/luxtrustglobalrootca -deleted file mode 100644 -index 7fb3d818f..000000000 ---- a/make/data/cacerts/luxtrustglobalrootca -+++ /dev/null -@@ -1,28 +0,0 @@ --Owner: CN=LuxTrust Global Root, O=LuxTrust s.a., C=LU --Issuer: CN=LuxTrust Global Root, O=LuxTrust s.a., C=LU --Serial number: bb8 --Valid from: Thu Mar 17 09:51:37 GMT 2011 until: Wed Mar 17 09:51:37 GMT 2021 --Signature algorithm name: SHA256withRSA --Subject Public Key Algorithm: 2048-bit RSA key --Version: 3 -------BEGIN CERTIFICATE----- --MIIDZDCCAkygAwIBAgICC7gwDQYJKoZIhvcNAQELBQAwRDELMAkGA1UEBhMCTFUx --FjAUBgNVBAoTDUx1eFRydXN0IHMuYS4xHTAbBgNVBAMTFEx1eFRydXN0IEdsb2Jh --bCBSb290MB4XDTExMDMxNzA5NTEzN1oXDTIxMDMxNzA5NTEzN1owRDELMAkGA1UE --BhMCTFUxFjAUBgNVBAoTDUx1eFRydXN0IHMuYS4xHTAbBgNVBAMTFEx1eFRydXN0 --IEdsb2JhbCBSb290MIIBIjANBgkqhkiG9w0BAQEFAAOCAQ8AMIIBCgKCAQEAsn+n --QPAiygz267Hxyw6VV0B1r6A/Ps7sqjJX5hmxZ0OYWmt8s7j6eJyqpoSyYBuAQc5j --zR8XCJmk9e8+EsdMsFeaXHhAePxFjdqRZ9w6Ubltc+a3OY52OrQfBfVpVfmTz3iI --Sr6qm9d7R1tGBEyCFqY19vx039a0r9jitScRdFmiwmYsaArhmIiIPIoFdRTjuK7z --CISbasE/MRivJ6VLm6T9eTHemD0OYcqHmMH4ijCc+j4z1aXEAwfh95Z0GAAnOCfR --K6qq4UFFi2/xJcLcopeVx0IUM115hCNq52XAV6DYXaljAeew5Ivo+MVjuOVsdJA9 --x3f8K7p56aTGEnin/wIDAQABo2AwXjAMBgNVHRMEBTADAQH/MA4GA1UdDwEB/wQE --AwIBBjAfBgNVHSMEGDAWgBQXFYWJCS8kh28/HRvk8pZ5g0gTzjAdBgNVHQ4EFgQU --FxWFiQkvJIdvPx0b5PKWeYNIE84wDQYJKoZIhvcNAQELBQADggEBAFrwHNDUUM9B --fua4nX3DcNBeNv9ujnov3kgR1TQuPLdFwlQlp+HBHjeDtpSutkVIA+qVvuucarQ3 --XB8u02uCgUNbCj8RVWOs+nwIAjegPDkEM/6XMshS5dklTbDG7mgfcKpzzlcD3H0K --DTPy0lrfCmw7zBFRlxqkIaKFNQLXgCLShLL4wKpov9XrqsMLq6F8K/f1O4fhVFfs --BSTveUJO84ton+Ruy4KZycwq3FPCH3CDqyEPVrRI/98HIrOM+R2mBN8tAza53W/+ --MYhm/2xtRDSvCHc+JtJy9LtHVpM8mGPhM7uZI5K1g3noHZ9nrWLWidb2/CfeMifL --hNp3hSGhEiE= -------END CERTIFICATE----- -diff --git a/make/data/cacerts/quovadisrootca b/make/data/cacerts/quovadisrootca -deleted file mode 100644 -index 0c195ff51..000000000 ---- a/make/data/cacerts/quovadisrootca -+++ /dev/null -@@ -1,41 +0,0 @@ --Owner: CN=QuoVadis Root Certification Authority, OU=Root Certification Authority, O=QuoVadis Limited, C=BM --Issuer: CN=QuoVadis Root Certification Authority, OU=Root Certification Authority, O=QuoVadis Limited, C=BM --Serial number: 3ab6508b --Valid from: Mon Mar 19 18:33:33 GMT 2001 until: Wed Mar 17 18:33:33 GMT 2021 --Signature algorithm name: SHA1withRSA --Subject Public Key Algorithm: 2048-bit RSA key --Version: 3 -------BEGIN CERTIFICATE----- --MIIF0DCCBLigAwIBAgIEOrZQizANBgkqhkiG9w0BAQUFADB/MQswCQYDVQQGEwJC --TTEZMBcGA1UEChMQUXVvVmFkaXMgTGltaXRlZDElMCMGA1UECxMcUm9vdCBDZXJ0 --aWZpY2F0aW9uIEF1dGhvcml0eTEuMCwGA1UEAxMlUXVvVmFkaXMgUm9vdCBDZXJ0 --aWZpY2F0aW9uIEF1dGhvcml0eTAeFw0wMTAzMTkxODMzMzNaFw0yMTAzMTcxODMz --MzNaMH8xCzAJBgNVBAYTAkJNMRkwFwYDVQQKExBRdW9WYWRpcyBMaW1pdGVkMSUw --IwYDVQQLExxSb290IENlcnRpZmljYXRpb24gQXV0aG9yaXR5MS4wLAYDVQQDEyVR --dW9WYWRpcyBSb290IENlcnRpZmljYXRpb24gQXV0aG9yaXR5MIIBIjANBgkqhkiG --9w0BAQEFAAOCAQ8AMIIBCgKCAQEAv2G1lVO6V/z68mcLOhrfEYBklbTRvM16z/Yp --li4kVEAkOPcahdxYTMukJ0KX0J+DisPkBgNbAKVRHnAEdOLB1Dqr1607BxgFjv2D --rOpm2RgbaIr1VxqYuvXtdj182d6UajtLF8HVj71lODqV0D1VNk7feVcxKh7YWWVJ --WCCYfqtffp/p1k3sg3Spx2zY7ilKhSoGFPlU5tPaZQeLYzcS19Dsw3sgQUSj7cug --F+FxZc4dZjH3dgEZyH0DWLaVSR2mEiboxgx24ONmy+pdpibu5cxfvWenAScOospU --xbF6lR1xHkopigPcakXBpBlebzbNw6Kwt/5cOOJSvPhEQ+aQuwIDAQABo4ICUjCC --Ak4wPQYIKwYBBQUHAQEEMTAvMC0GCCsGAQUFBzABhiFodHRwczovL29jc3AucXVv --dmFkaXNvZmZzaG9yZS5jb20wDwYDVR0TAQH/BAUwAwEB/zCCARoGA1UdIASCAREw --ggENMIIBCQYJKwYBBAG+WAABMIH7MIHUBggrBgEFBQcCAjCBxxqBxFJlbGlhbmNl --IG9uIHRoZSBRdW9WYWRpcyBSb290IENlcnRpZmljYXRlIGJ5IGFueSBwYXJ0eSBh --c3N1bWVzIGFjY2VwdGFuY2Ugb2YgdGhlIHRoZW4gYXBwbGljYWJsZSBzdGFuZGFy --ZCB0ZXJtcyBhbmQgY29uZGl0aW9ucyBvZiB1c2UsIGNlcnRpZmljYXRpb24gcHJh --Y3RpY2VzLCBhbmQgdGhlIFF1b1ZhZGlzIENlcnRpZmljYXRlIFBvbGljeS4wIgYI --KwYBBQUHAgEWFmh0dHA6Ly93d3cucXVvdmFkaXMuYm0wHQYDVR0OBBYEFItLbe3T --KbkGGew5Oanwl4Rqy+/fMIGuBgNVHSMEgaYwgaOAFItLbe3TKbkGGew5Oanwl4Rq --y+/foYGEpIGBMH8xCzAJBgNVBAYTAkJNMRkwFwYDVQQKExBRdW9WYWRpcyBMaW1p --dGVkMSUwIwYDVQQLExxSb290IENlcnRpZmljYXRpb24gQXV0aG9yaXR5MS4wLAYD --VQQDEyVRdW9WYWRpcyBSb290IENlcnRpZmljYXRpb24gQXV0aG9yaXR5ggQ6tlCL --MA4GA1UdDwEB/wQEAwIBBjANBgkqhkiG9w0BAQUFAAOCAQEAitQUtf70mpKnGdSk --fnIYj9lofFIk3WdvOXrEql494liwTXCYhGHoG+NpGA7O+0dQoE7/8CQfvbLO9Sf8 --7C9TqnN7Az10buYWnuulLsS/VidQK2K6vkscPFVcQR0kvoIgR13VRH56FmjffU1R --cHhXHTMe/QKZnAzNCgVPx7uOpHX6Sm2xgI4JVrmcGmD+XcHXetwReNDWXcG31a0y --mQM6isxUJTkxgXsTIlG6Rmyhu576BGxJJnSP0nPrzDCi5upZIof4l/UO/erMkqQW --xFIY6iHOsfHmhIHluqmGKPJDWl0Snawe2ajlCmqnf6CHKc/yiU3U7MXi5nrQNiOK --SnQ2+Q== -------END CERTIFICATE----- -diff --git a/test/jdk/sun/security/lib/cacerts/VerifyCACerts.java b/test/jdk/sun/security/lib/cacerts/VerifyCACerts.java -index 8b8739d33..1b258059f 100644 ---- a/test/jdk/sun/security/lib/cacerts/VerifyCACerts.java -+++ b/test/jdk/sun/security/lib/cacerts/VerifyCACerts.java -@@ -53,12 +53,12 @@ public class VerifyCACerts { - + File.separator + "security" + File.separator + "cacerts"; - - // The numbers of certs now. -- private static final int COUNT = 87; -+ private static final int COUNT = 84; - - // SHA-256 of cacerts, can be generated with - // shasum -a 256 cacerts | sed -e 's/../&:/g' | tr '[:lower:]' '[:upper:]' | cut -c1-95 - private static final String CHECKSUM -- = "EA:29:DE:36:FD:06:0A:A1:D9:46:0B:DF:E0:B8:E7:16:40:1B:52:3B:5F:0F:58:EE:E0:2A:A9:2A:D7:8D:34:68"; -+ = "D3:05:21:64:FA:D7:CD:29:E8:CB:57:E7:47:ED:79:9B:47:D8:0E:75:2D:CA:83:BB:86:AF:D9:43:FD:3E:17:85"; - - // map of cert alias to SHA-256 fingerprint - @SuppressWarnings("serial") -@@ -144,10 +144,6 @@ public class VerifyCACerts { - "5D:56:49:9B:E4:D2:E0:8B:CF:CA:D0:8A:3E:38:72:3D:50:50:3B:DE:70:69:48:E4:2F:55:60:30:19:E5:28:AE"); - put("letsencryptisrgx1 [jdk]", - "96:BC:EC:06:26:49:76:F3:74:60:77:9A:CF:28:C5:A7:CF:E8:A3:C0:AA:E1:1A:8F:FC:EE:05:C0:BD:DF:08:C6"); -- put("luxtrustglobalrootca [jdk]", -- "A1:B2:DB:EB:64:E7:06:C6:16:9E:3C:41:18:B2:3B:AA:09:01:8A:84:27:66:6D:8B:F0:E2:88:91:EC:05:19:50"); -- put("quovadisrootca [jdk]", -- "A4:5E:DE:3B:BB:F0:9C:8A:E1:5C:72:EF:C0:72:68:D6:93:A2:1C:99:6F:D5:1E:67:CA:07:94:60:FD:6D:88:73"); - put("quovadisrootca1g3 [jdk]", - "8A:86:6F:D1:B2:76:B5:7E:57:8E:92:1C:65:82:8A:2B:ED:58:E9:F2:F2:88:05:41:34:B7:F1:F4:BF:C9:CC:74"); - put("quovadisrootca2 [jdk]", -@@ -210,8 +206,6 @@ public class VerifyCACerts { - "17:9F:BC:14:8A:3D:D0:0F:D2:4E:A1:34:58:CC:43:BF:A7:F5:9C:81:82:D7:83:A5:13:F6:EB:EC:10:0C:89:24"); - put("globalsigneccrootcar4 [jdk]", - "BE:C9:49:11:C2:95:56:76:DB:6C:0A:55:09:86:D7:6E:3B:A0:05:66:7C:44:2C:97:62:B4:FB:B7:73:DE:22:8C"); -- put("globalsignr2ca [jdk]", -- "CA:42:DD:41:74:5F:D0:B8:1E:B9:02:36:2C:F9:D8:BF:71:9D:A1:BD:1B:1E:FC:94:6F:5B:4C:99:F4:2C:1B:9E"); - put("teliasonerarootcav1 [jdk]", - "DD:69:36:FE:21:F8:F0:77:C1:23:A1:A5:21:C1:22:24:F7:22:55:B7:3E:03:A7:26:06:93:E8:A2:4B:0F:A3:89"); - put("globalsignrootcar6 [jdk]", -@@ -252,10 +246,6 @@ public class VerifyCACerts { - add("addtrustexternalca [jdk]"); - // Valid until: Sat May 30 10:44:50 GMT 2020 - add("addtrustqualifiedca [jdk]"); -- // Valid until: Wed Mar 17 02:51:37 PDT 2021 -- add("luxtrustglobalrootca [jdk]"); -- // Valid until: Wed Mar 17 11:33:33 PDT 2021 -- add("quovadisrootca [jdk]"); - // Valid until: Wed Dec 15 08:00:00 UTC 2021 - add("globalsignr2ca [jdk]"); - } --- -2.22.0 - diff --git a/ZGC-Redesign-C2-load-barrier-to-expand-on-th.patch b/ZGC-Redesign-C2-load-barrier-to-expand-on-th.patch index 91d0b766ad26be9a6d7c279b3f2b61dbd01a3683..e9b97a6a9fe1bec388189721390c03394d961581 100644 --- a/ZGC-Redesign-C2-load-barrier-to-expand-on-th.patch +++ b/ZGC-Redesign-C2-load-barrier-to-expand-on-th.patch @@ -998,44 +998,28 @@ index 279ff79..f9b2b3b 100644 void MacroAssembler::verify_heapbase(const char* msg) { #if 0 diff --git a/src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp b/src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp -index af8056b..44497ea 100644 +index edcfd9ceb..60b728e94 100644 --- a/src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp +++ b/src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp -@@ -440,12 +440,18 @@ private: +@@ -462,12 +462,18 @@ private: int push(unsigned int bitset, Register stack); int pop(unsigned int bitset, Register stack); - + + int push_fp(unsigned int bitset, Register stack); + int pop_fp(unsigned int bitset, Register stack); + void mov(Register dst, Address a); - + public: void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); } void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); } - + + void push_fp(RegSet regs, Register stack) { if (regs.bits()) push_fp(regs.bits(), stack); } + void pop_fp(RegSet regs, Register stack) { if (regs.bits()) pop_fp(regs.bits(), stack); } + + static RegSet call_clobbered_registers(); + // Push and pop everything that might be clobbered by a native - // runtime call except rscratch1 and rscratch2. (They are always - // scratch, so we don't have to protect them.) Only save the lower -diff --git a/src/hotspot/cpu/aarch64/register_aarch64.hpp b/src/hotspot/cpu/aarch64/register_aarch64.hpp -index 8cda52a..5f7662c 100644 ---- a/src/hotspot/cpu/aarch64/register_aarch64.hpp -+++ b/src/hotspot/cpu/aarch64/register_aarch64.hpp -@@ -230,6 +230,11 @@ public: - return *this; - } - -+ RegSet &operator-=(const RegSet aSet) { -+ *this = *this - aSet; -+ return *this; -+ } -+ - static RegSet of(Register r1) { - return RegSet(r1); - } diff --git a/src/hotspot/cpu/aarch64/templateInterpreterGenerator_aarch64.cpp b/src/hotspot/cpu/aarch64/templateInterpreterGenerator_aarch64.cpp index c162024..6e4eb1a 100644 --- a/src/hotspot/cpu/aarch64/templateInterpreterGenerator_aarch64.cpp @@ -4695,29 +4679,10 @@ index 05ec9fa..16b80bf 100644 case Op_LoadS: case Op_LoadKlass: diff --git a/src/hotspot/share/opto/loopnode.cpp b/src/hotspot/share/opto/loopnode.cpp -index 6aff3d5..38f0449 100644 +index d7eb3996b..366d0f378 100644 --- a/src/hotspot/share/opto/loopnode.cpp +++ b/src/hotspot/share/opto/loopnode.cpp -@@ -1005,18 +1005,6 @@ void LoopNode::verify_strip_mined(int expect_skeleton) const { - } - } - -- if (UseZGC && !inner_out->in(0)->is_CountedLoopEnd()) { -- // In some very special cases there can be a load that has no other uses than the -- // counted loop safepoint. Then its loadbarrier will be placed between the inner -- // loop exit and the safepoint. This is very rare -- -- Node* ifnode = inner_out->in(1)->in(0); -- // Region->IfTrue->If == Region->Iffalse->If -- if (ifnode == inner_out->in(2)->in(0)) { -- inner_out = ifnode->in(0); -- } -- } -- - CountedLoopEndNode* cle = inner_out->in(0)->as_CountedLoopEnd(); - assert(cle == inner->loopexit_or_null(), "mismatch"); - bool has_skeleton = outer_le->in(1)->bottom_type()->singleton() && outer_le->in(1)->bottom_type()->is_int()->get_con() == 0; -@@ -4273,7 +4261,6 @@ void PhaseIdealLoop::build_loop_late_post( Node *n ) { +@@ -4300,7 +4300,6 @@ void PhaseIdealLoop::build_loop_late_post( Node *n ) { case Op_LoadL: case Op_LoadS: case Op_LoadP: diff --git a/add-integerCache-feature.patch b/add-integerCache-feature.patch index 0665764676cbfd8605656c3966fbb6c4f4985989..e41a310ff089794b8af5c1cdb3a11365e920f00d 100755 --- a/add-integerCache-feature.patch +++ b/add-integerCache-feature.patch @@ -2,7 +2,7 @@ diff --git a/src/hotspot/share/prims/unsafe.cpp b/src/hotspot/share/prims/unsafe index d8f1679b4..18ea89b85 100644 --- a/src/hotspot/share/prims/unsafe.cpp +++ b/src/hotspot/share/prims/unsafe.cpp -@@ -1018,7 +1018,11 @@ UNSAFE_ENTRY(jint, Unsafe_GetLoadAverage0(JNIEnv *env, jobject unsafe, jdoubleAr +@@ -1018,6 +1018,11 @@ UNSAFE_ENTRY(jint, Unsafe_GetLoadAverage0(JNIEnv *env, jobject unsafe, jdoubleAr return ret; } UNSAFE_END @@ -10,20 +10,20 @@ index d8f1679b4..18ea89b85 100644 + return UseHashMapIntegerCache; +} +UNSAFE_END - ++ UNSAFE_ENTRY(jboolean, Unsafe_GetUseFastSerializer(JNIEnv *env, jobject unsafe)) { return UseFastSerializer; } @@ -1108,6 +1113,7 @@ static JNINativeMethod jdk_internal_misc_Unsafe_methods[] = { - {CC "fullFence", CC "()V", FN_PTR(Unsafe_FullFence)}, - {CC "isBigEndian0", CC "()Z", FN_PTR(Unsafe_isBigEndian0)}, + {CC "unalignedAccess0", CC "()Z", FN_PTR(Unsafe_unalignedAccess0)}, + + {CC "getUseHashMapIntegerCache", CC "()Z", FN_PTR(Unsafe_GetUseHashMapIntegerCache)}, {CC "getUseFastSerializer", CC "()Z", FN_PTR(Unsafe_GetUseFastSerializer)}, - {CC "unalignedAccess0", CC "()Z", FN_PTR(Unsafe_unalignedAccess0)} + }; diff --git a/src/hotspot/share/runtime/globals.hpp b/src/hotspot/share/runtime/globals.hpp -index 47458b6c1..b8c0bec40 100644 +index 10c06c2d6..71ab94d34 100644 --- a/src/hotspot/share/runtime/globals.hpp +++ b/src/hotspot/share/runtime/globals.hpp @@ -2677,6 +2677,11 @@ define_pd_global(uint64_t,MaxRAM, 1ULL*G); @@ -409,5 +409,5 @@ index d78caabdc..4d71e671e 100644 private native long allocateMemory0(long bytes); private native long reallocateMemory0(long address, long bytes); -- -2.19.1 +2.19.0 diff --git a/delete_expired_certificates.patch b/delete_expired_certificates.patch index 16422d7185c14405f339aa7fd6132fd8c9f1fdb6..acf3dcde59d770e782436e2f53d7c86a1172dec9 100644 --- a/delete_expired_certificates.patch +++ b/delete_expired_certificates.patch @@ -74,6 +74,87 @@ index 0c62d44c7..000000000 -iQBCYz95OdBEsIJuQRno3eDBiFrRHnGTHyQwdOUeqN48Jzd/g66ed8/wMLH/S5no -xqE= ------END CERTIFICATE----- +diff --git a/make/data/cacerts/luxtrustglobalrootca b/make/data/cacerts/luxtrustglobalrootca +deleted file mode 100644 +index 7fb3d818f..000000000 +--- a/make/data/cacerts/luxtrustglobalrootca ++++ /dev/null +@@ -1,28 +0,0 @@ +-Owner: CN=LuxTrust Global Root, O=LuxTrust s.a., C=LU +-Issuer: CN=LuxTrust Global Root, O=LuxTrust s.a., C=LU +-Serial number: bb8 +-Valid from: Thu Mar 17 09:51:37 GMT 2011 until: Wed Mar 17 09:51:37 GMT 2021 +-Signature algorithm name: SHA256withRSA +-Subject Public Key Algorithm: 2048-bit RSA key +-Version: 3 +------BEGIN CERTIFICATE----- +-MIIDZDCCAkygAwIBAgICC7gwDQYJKoZIhvcNAQELBQAwRDELMAkGA1UEBhMCTFUx +-FjAUBgNVBAoTDUx1eFRydXN0IHMuYS4xHTAbBgNVBAMTFEx1eFRydXN0IEdsb2Jh +-bCBSb290MB4XDTExMDMxNzA5NTEzN1oXDTIxMDMxNzA5NTEzN1owRDELMAkGA1UE +-BhMCTFUxFjAUBgNVBAoTDUx1eFRydXN0IHMuYS4xHTAbBgNVBAMTFEx1eFRydXN0 +-IEdsb2JhbCBSb290MIIBIjANBgkqhkiG9w0BAQEFAAOCAQ8AMIIBCgKCAQEAsn+n +-QPAiygz267Hxyw6VV0B1r6A/Ps7sqjJX5hmxZ0OYWmt8s7j6eJyqpoSyYBuAQc5j +-zR8XCJmk9e8+EsdMsFeaXHhAePxFjdqRZ9w6Ubltc+a3OY52OrQfBfVpVfmTz3iI +-Sr6qm9d7R1tGBEyCFqY19vx039a0r9jitScRdFmiwmYsaArhmIiIPIoFdRTjuK7z +-CISbasE/MRivJ6VLm6T9eTHemD0OYcqHmMH4ijCc+j4z1aXEAwfh95Z0GAAnOCfR +-K6qq4UFFi2/xJcLcopeVx0IUM115hCNq52XAV6DYXaljAeew5Ivo+MVjuOVsdJA9 +-x3f8K7p56aTGEnin/wIDAQABo2AwXjAMBgNVHRMEBTADAQH/MA4GA1UdDwEB/wQE +-AwIBBjAfBgNVHSMEGDAWgBQXFYWJCS8kh28/HRvk8pZ5g0gTzjAdBgNVHQ4EFgQU +-FxWFiQkvJIdvPx0b5PKWeYNIE84wDQYJKoZIhvcNAQELBQADggEBAFrwHNDUUM9B +-fua4nX3DcNBeNv9ujnov3kgR1TQuPLdFwlQlp+HBHjeDtpSutkVIA+qVvuucarQ3 +-XB8u02uCgUNbCj8RVWOs+nwIAjegPDkEM/6XMshS5dklTbDG7mgfcKpzzlcD3H0K +-DTPy0lrfCmw7zBFRlxqkIaKFNQLXgCLShLL4wKpov9XrqsMLq6F8K/f1O4fhVFfs +-BSTveUJO84ton+Ruy4KZycwq3FPCH3CDqyEPVrRI/98HIrOM+R2mBN8tAza53W/+ +-MYhm/2xtRDSvCHc+JtJy9LtHVpM8mGPhM7uZI5K1g3noHZ9nrWLWidb2/CfeMifL +-hNp3hSGhEiE= +------END CERTIFICATE----- +diff --git a/make/data/cacerts/quovadisrootca b/make/data/cacerts/quovadisrootca +deleted file mode 100644 +index 0c195ff51..000000000 +--- a/make/data/cacerts/quovadisrootca ++++ /dev/null +@@ -1,41 +0,0 @@ +-Owner: CN=QuoVadis Root Certification Authority, OU=Root Certification Authority, O=QuoVadis Limited, C=BM +-Issuer: CN=QuoVadis Root Certification Authority, OU=Root Certification Authority, O=QuoVadis Limited, C=BM +-Serial number: 3ab6508b +-Valid from: Mon Mar 19 18:33:33 GMT 2001 until: Wed Mar 17 18:33:33 GMT 2021 +-Signature algorithm name: SHA1withRSA +-Subject Public Key Algorithm: 2048-bit RSA key +-Version: 3 +------BEGIN CERTIFICATE----- +-MIIF0DCCBLigAwIBAgIEOrZQizANBgkqhkiG9w0BAQUFADB/MQswCQYDVQQGEwJC +-TTEZMBcGA1UEChMQUXVvVmFkaXMgTGltaXRlZDElMCMGA1UECxMcUm9vdCBDZXJ0 +-aWZpY2F0aW9uIEF1dGhvcml0eTEuMCwGA1UEAxMlUXVvVmFkaXMgUm9vdCBDZXJ0 +-aWZpY2F0aW9uIEF1dGhvcml0eTAeFw0wMTAzMTkxODMzMzNaFw0yMTAzMTcxODMz +-MzNaMH8xCzAJBgNVBAYTAkJNMRkwFwYDVQQKExBRdW9WYWRpcyBMaW1pdGVkMSUw +-IwYDVQQLExxSb290IENlcnRpZmljYXRpb24gQXV0aG9yaXR5MS4wLAYDVQQDEyVR +-dW9WYWRpcyBSb290IENlcnRpZmljYXRpb24gQXV0aG9yaXR5MIIBIjANBgkqhkiG +-9w0BAQEFAAOCAQ8AMIIBCgKCAQEAv2G1lVO6V/z68mcLOhrfEYBklbTRvM16z/Yp +-li4kVEAkOPcahdxYTMukJ0KX0J+DisPkBgNbAKVRHnAEdOLB1Dqr1607BxgFjv2D +-rOpm2RgbaIr1VxqYuvXtdj182d6UajtLF8HVj71lODqV0D1VNk7feVcxKh7YWWVJ +-WCCYfqtffp/p1k3sg3Spx2zY7ilKhSoGFPlU5tPaZQeLYzcS19Dsw3sgQUSj7cug +-F+FxZc4dZjH3dgEZyH0DWLaVSR2mEiboxgx24ONmy+pdpibu5cxfvWenAScOospU +-xbF6lR1xHkopigPcakXBpBlebzbNw6Kwt/5cOOJSvPhEQ+aQuwIDAQABo4ICUjCC +-Ak4wPQYIKwYBBQUHAQEEMTAvMC0GCCsGAQUFBzABhiFodHRwczovL29jc3AucXVv +-dmFkaXNvZmZzaG9yZS5jb20wDwYDVR0TAQH/BAUwAwEB/zCCARoGA1UdIASCAREw +-ggENMIIBCQYJKwYBBAG+WAABMIH7MIHUBggrBgEFBQcCAjCBxxqBxFJlbGlhbmNl +-IG9uIHRoZSBRdW9WYWRpcyBSb290IENlcnRpZmljYXRlIGJ5IGFueSBwYXJ0eSBh +-c3N1bWVzIGFjY2VwdGFuY2Ugb2YgdGhlIHRoZW4gYXBwbGljYWJsZSBzdGFuZGFy +-ZCB0ZXJtcyBhbmQgY29uZGl0aW9ucyBvZiB1c2UsIGNlcnRpZmljYXRpb24gcHJh +-Y3RpY2VzLCBhbmQgdGhlIFF1b1ZhZGlzIENlcnRpZmljYXRlIFBvbGljeS4wIgYI +-KwYBBQUHAgEWFmh0dHA6Ly93d3cucXVvdmFkaXMuYm0wHQYDVR0OBBYEFItLbe3T +-KbkGGew5Oanwl4Rqy+/fMIGuBgNVHSMEgaYwgaOAFItLbe3TKbkGGew5Oanwl4Rq +-y+/foYGEpIGBMH8xCzAJBgNVBAYTAkJNMRkwFwYDVQQKExBRdW9WYWRpcyBMaW1p +-dGVkMSUwIwYDVQQLExxSb290IENlcnRpZmljYXRpb24gQXV0aG9yaXR5MS4wLAYD +-VQQDEyVRdW9WYWRpcyBSb290IENlcnRpZmljYXRpb24gQXV0aG9yaXR5ggQ6tlCL +-MA4GA1UdDwEB/wQEAwIBBjANBgkqhkiG9w0BAQUFAAOCAQEAitQUtf70mpKnGdSk +-fnIYj9lofFIk3WdvOXrEql494liwTXCYhGHoG+NpGA7O+0dQoE7/8CQfvbLO9Sf8 +-7C9TqnN7Az10buYWnuulLsS/VidQK2K6vkscPFVcQR0kvoIgR13VRH56FmjffU1R +-cHhXHTMe/QKZnAzNCgVPx7uOpHX6Sm2xgI4JVrmcGmD+XcHXetwReNDWXcG31a0y +-mQM6isxUJTkxgXsTIlG6Rmyhu576BGxJJnSP0nPrzDCi5upZIof4l/UO/erMkqQW +-xFIY6iHOsfHmhIHluqmGKPJDWl0Snawe2ajlCmqnf6CHKc/yiU3U7MXi5nrQNiOK +-SnQ2+Q== +------END CERTIFICATE----- diff --git a/make/data/cacerts/utnuserfirstobjectca b/make/data/cacerts/utnuserfirstobjectca deleted file mode 100644 index 80a0b5c23..000000000 @@ -114,21 +195,21 @@ index 80a0b5c23..000000000 -Uh+U3xeUc8OzwcFxBSAAeL0TUh2oPs0AH8g= ------END CERTIFICATE----- diff --git a/test/jdk/sun/security/lib/cacerts/VerifyCACerts.java b/test/jdk/sun/security/lib/cacerts/VerifyCACerts.java -index a0e4cf294..8b8739d33 100644 +index 91d78e8fe..68f85e215 100644 --- a/test/jdk/sun/security/lib/cacerts/VerifyCACerts.java +++ b/test/jdk/sun/security/lib/cacerts/VerifyCACerts.java @@ -53,12 +53,12 @@ public class VerifyCACerts { + File.separator + "security" + File.separator + "cacerts"; // The numbers of certs now. -- private static final int COUNT = 90; -+ private static final int COUNT = 87; +- private static final int COUNT = 89; ++ private static final int COUNT = 84; // SHA-256 of cacerts, can be generated with // shasum -a 256 cacerts | sed -e 's/../&:/g' | tr '[:lower:]' '[:upper:]' | cut -c1-95 private static final String CHECKSUM -- = "A2:36:27:B7:F6:99:7A:C7:7E:2D:55:47:66:57:08:3F:F8:8C:F2:28:77:29:30:40:A2:D3:6D:1A:B6:C7:32:6F"; -+ = "EA:29:DE:36:FD:06:0A:A1:D9:46:0B:DF:E0:B8:E7:16:40:1B:52:3B:5F:0F:58:EE:E0:2A:A9:2A:D7:8D:34:68"; +- = "CC:AD:BB:49:70:97:3F:42:AD:73:91:A0:A2:C4:B8:AA:D1:95:59:F3:B3:22:09:2A:1F:2C:AB:04:47:08:EF:AA"; ++ = "D3:05:21:64:FA:D7:CD:29:E8:CB:57:E7:47:ED:79:9B:47:D8:0E:75:2D:CA:83:BB:86:AF:D9:43:FD:3E:17:85"; // map of cert alias to SHA-256 fingerprint @SuppressWarnings("serial") @@ -145,12 +226,35 @@ index a0e4cf294..8b8739d33 100644 put("baltimorecybertrustca [jdk]", "16:AF:57:A9:F6:76:B0:AB:12:60:95:AA:5E:BA:DE:F2:2A:B3:11:19:D6:44:AC:95:CD:4B:93:DB:F3:F2:6A:EB"); put("digicertglobalrootca [jdk]", -@@ -262,6 +256,8 @@ public class VerifyCACerts { +@@ -150,10 +144,6 @@ public class VerifyCACerts { + "5D:56:49:9B:E4:D2:E0:8B:CF:CA:D0:8A:3E:38:72:3D:50:50:3B:DE:70:69:48:E4:2F:55:60:30:19:E5:28:AE"); + put("letsencryptisrgx1 [jdk]", + "96:BC:EC:06:26:49:76:F3:74:60:77:9A:CF:28:C5:A7:CF:E8:A3:C0:AA:E1:1A:8F:FC:EE:05:C0:BD:DF:08:C6"); +- put("luxtrustglobalrootca [jdk]", +- "A1:B2:DB:EB:64:E7:06:C6:16:9E:3C:41:18:B2:3B:AA:09:01:8A:84:27:66:6D:8B:F0:E2:88:91:EC:05:19:50"); +- put("quovadisrootca [jdk]", +- "A4:5E:DE:3B:BB:F0:9C:8A:E1:5C:72:EF:C0:72:68:D6:93:A2:1C:99:6F:D5:1E:67:CA:07:94:60:FD:6D:88:73"); + put("quovadisrootca1g3 [jdk]", + "8A:86:6F:D1:B2:76:B5:7E:57:8E:92:1C:65:82:8A:2B:ED:58:E9:F2:F2:88:05:41:34:B7:F1:F4:BF:C9:CC:74"); + put("quovadisrootca2 [jdk]", +@@ -250,16 +240,14 @@ public class VerifyCACerts { + @SuppressWarnings("serial") + private static final HashSet EXPIRY_EXC_ENTRIES = new HashSet<>() { + { +- // Valid until: Tue Jul 09 14:40:36 EDT 2019 +- add("utnuserfirstobjectca [jdk]"); +- // Valid until: Sat May 30 10:38:31 GMT 2020 +- add("addtrustexternalca [jdk]"); +- // Valid until: Sat May 30 10:44:50 GMT 2020 +- add("addtrustqualifiedca [jdk]"); + // Valid until: Wed Mar 17 02:51:37 PDT 2021 add("luxtrustglobalrootca [jdk]"); // Valid until: Wed Mar 17 11:33:33 PDT 2021 add("quovadisrootca [jdk]"); + // Valid until: Wed Dec 15 08:00:00 UTC 2021 + add("globalsignr2ca [jdk]"); ++ // Valid until: Thu Sep 30 14:01:15 UTC 2021 ++ add("identrustdstx3 [jdk]"); } }; diff --git a/dfx-enhancement-of-FastSerializer.patch b/dfx-enhancement-of-FastSerializer.patch new file mode 100755 index 0000000000000000000000000000000000000000..9b26d881aa759d19748045f1013a0ca47bd2703e --- /dev/null +++ b/dfx-enhancement-of-FastSerializer.patch @@ -0,0 +1,190 @@ +diff --git a/src/java.base/share/classes/java/io/ObjectInputStream.java b/src/java.base/share/classes/java/io/ObjectInputStream.java +index 78008081f..a77a5d5b6 100644 +--- a/src/java.base/share/classes/java/io/ObjectInputStream.java ++++ b/src/java.base/share/classes/java/io/ObjectInputStream.java +@@ -306,6 +306,23 @@ public class ObjectInputStream + filterLogger = (filterLog.isLoggable(Logger.Level.DEBUG) + || filterLog.isLoggable(Logger.Level.TRACE)) ? filterLog : null; + } ++ ++ /* ++ * Logger for FastSerializer. ++ * Setup the FastSerializer logger if it is set to DEBUG. ++ * (Assuming it will not change). ++ */ ++ static final System.Logger fastSerLogger; ++ ++ static { ++ if (printFastSerializer) { ++ Logger fastSerLog = System.getLogger("fastSerializer"); ++ fastSerLogger = (fastSerLog.isLoggable(Logger.Level.DEBUG)) ++ ? fastSerLog : null; ++ } else { ++ fastSerLogger = null; ++ } ++ } + } + + /** filter stream for handling block data conversion */ +@@ -366,6 +383,14 @@ public class ObjectInputStream + new sun.security.action.GetBooleanAction( + "fastSerializerEscapeMode")).booleanValue(); + ++ /** ++ * value of "printFastSerializer" property, ++ * as true or false for printing FastSerializer logs. ++ */ ++ private static final boolean printFastSerializer = java.security.AccessController.doPrivileged( ++ new sun.security.action.GetBooleanAction( ++ "printFastSerializer")).booleanValue(); ++ + /** + * Creates an ObjectInputStream that reads from the specified InputStream. + * A serialization stream header is read from the stream and verified. +@@ -988,7 +1013,7 @@ public class ObjectInputStream + if (s0 != STREAM_MAGIC_FAST || s1 != STREAM_VERSION) { + if (s0 != STREAM_MAGIC) { + throw new StreamCorruptedException( +- String.format("invalid stream header: %04X%04X", s0, s1)); ++ String.format("invalid stream header: %04X%04X, and FastSerializer is activated", s0, s1)); + } + + if (!fastSerializerEscapeMode) { +@@ -999,10 +1024,18 @@ public class ObjectInputStream + + // Escape to default serialization + useFastSerializer = false; ++ if (Logging.fastSerLogger != null) { ++ Logging.fastSerLogger.log(Logger.Level.DEBUG, "[Deserialize]: Escape and disable FastSerializer"); ++ } + } + } else if (s0 != STREAM_MAGIC || s1 != STREAM_VERSION) { ++ if (s0 == STREAM_MAGIC_FAST && s1 == STREAM_VERSION) { ++ throw new StreamCorruptedException( ++ String.format("invalid stream header: %04X%04X, and it is a FastSerializer stream", s0, s1)); ++ } else { + throw new StreamCorruptedException( + String.format("invalid stream header: %04X%04X", s0, s1)); ++ } + } + } + +@@ -2129,6 +2162,12 @@ public class ObjectInputStream + handles.finish(descHandle); + passHandle = descHandle; + ++ if (Logging.fastSerLogger != null) { ++ Logging.fastSerLogger.log(Logger.Level.DEBUG, ++ "[Deserialize] useFastSerializer:{0}, Class name:{1}, SerialVersionUID:{2}, flags:{3}", ++ useFastSerializer, desc.getName(), desc.getSerialVersionUID(), desc.getFlags(this)); ++ } ++ + return desc; + } + +diff --git a/src/java.base/share/classes/java/io/ObjectOutputStream.java b/src/java.base/share/classes/java/io/ObjectOutputStream.java +index 044924593..8935e61dc 100644 +--- a/src/java.base/share/classes/java/io/ObjectOutputStream.java ++++ b/src/java.base/share/classes/java/io/ObjectOutputStream.java +@@ -175,6 +175,25 @@ public class ObjectOutputStream + new ReferenceQueue<>(); + } + ++ private static class Logging { ++ /* ++ * Logger for FastSerializer. ++ * Setup the FastSerializer logger if it is set to DEBUG. ++ * (Assuming it will not change). ++ */ ++ static final System.Logger fastSerLogger; ++ ++ static { ++ if (printFastSerializer) { ++ System.Logger fastSerLog = System.getLogger("fastSerializer"); ++ fastSerLogger = (fastSerLog.isLoggable(System.Logger.Level.DEBUG)) ++ ? fastSerLog : null; ++ } else { ++ fastSerLogger = null; ++ } ++ } ++ } ++ + /** filter stream for handling block data conversion */ + private final BlockDataOutputStream bout; + /** obj -> wire handle map */ +@@ -223,6 +242,14 @@ public class ObjectOutputStream + */ + private static final boolean useFastSerializer = UNSAFE.getUseFastSerializer(); + ++ /** ++ * value of "printFastSerializer" property, ++ * as true or false for printing FastSerializer logs. ++ */ ++ private static final boolean printFastSerializer = java.security.AccessController.doPrivileged( ++ new sun.security.action.GetBooleanAction( ++ "printFastSerializer")).booleanValue(); ++ + /** + * Creates an ObjectOutputStream that writes to the specified OutputStream. + * This constructor writes the serialization stream header to the +@@ -1301,6 +1328,12 @@ public class ObjectOutputStream + bout.writeByte(TC_CLASSDESC); + handles.assign(unshared ? null : desc); + ++ if (Logging.fastSerLogger != null) { ++ Logging.fastSerLogger.log(System.Logger.Level.DEBUG, ++ "[Serialize] useFastSerializer:{0}, Class name:{1}, SerialVersionUID:{2}, flags:{3}, protocol:{4}", ++ useFastSerializer, desc.getName(), desc.getSerialVersionUID(), desc.getFlags(this), protocol); ++ } ++ + if (protocol == PROTOCOL_VERSION_1) { + // do not invoke class descriptor write hook with old protocol + if (useFastSerializer) { +diff --git a/src/java.base/share/classes/java/io/ObjectStreamClass.java b/src/java.base/share/classes/java/io/ObjectStreamClass.java +index ac3a92bef..a5d7d2d75 100644 +--- a/src/java.base/share/classes/java/io/ObjectStreamClass.java ++++ b/src/java.base/share/classes/java/io/ObjectStreamClass.java +@@ -270,6 +270,40 @@ public class ObjectStreamClass implements Serializable { + return suid.longValue(); + } + ++ /** ++ * Return the flags for this class described by this descriptor. The flags ++ * means a set of bit masks for ObjectStreamClass, which indicate the status ++ * of SC_WRITE_METHOD, SC_SERIALIZABLE, SC_EXTERNALIZABLE, SC_BLOCK_DATA and ++ * SC_ENUM. ++ * ++ * @param serialStream ObjectOutputStream or ObjectInputStream ++ * ++ * @return the flags for this class described by this descriptor ++ */ ++ public byte getFlags(Object serialStream) { ++ byte flags = 0; ++ if (externalizable) { ++ flags |= ObjectStreamConstants.SC_EXTERNALIZABLE; ++ if (serialStream instanceof ObjectOutputStream) { ++ int protocol = ((ObjectOutputStream)serialStream).getProtocolVersion(); ++ if (protocol != ObjectStreamConstants.PROTOCOL_VERSION_1) { ++ flags |= ObjectStreamConstants.SC_BLOCK_DATA; ++ } ++ } else if (serialStream instanceof ObjectInputStream) { ++ flags |= ObjectStreamConstants.SC_BLOCK_DATA; ++ } ++ } else if (serializable) { ++ flags |= ObjectStreamConstants.SC_SERIALIZABLE; ++ } ++ if (hasWriteObjectData) { ++ flags |= ObjectStreamConstants.SC_WRITE_METHOD; ++ } ++ if (isEnum) { ++ flags |= ObjectStreamConstants.SC_ENUM; ++ } ++ return flags; ++ } ++ + /** + * Return the class in the local VM that this version is mapped to. Null + * is returned if there is no corresponding local class. +-- +2.19.0 + diff --git a/fast-serializer-jdk11.patch b/fast-serializer-jdk11.patch index 1456f032cf89caee10e51d479511a0e7f5d64e56..dcd65fe228ecef3c4bfaad815bfc0236f34e4503 100644 --- a/fast-serializer-jdk11.patch +++ b/fast-serializer-jdk11.patch @@ -1,41 +1,35 @@ -commit cbbef85e20818d23651e553ad9915ec8225a3456 -Date: Thu May 28 11:04:16 2020 +0800 - - Add FastSerializer - - Summary:: Add FastSerializer - LLT: jtreg - Bug url: NA - diff --git a/src/hotspot/share/prims/unsafe.cpp b/src/hotspot/share/prims/unsafe.cpp -index 2f14e01ce..2f7f96aee 100644 +index 2f14e01ce..d8f1679b4 100644 --- a/src/hotspot/share/prims/unsafe.cpp +++ b/src/hotspot/share/prims/unsafe.cpp -@@ -1019,6 +1019,11 @@ UNSAFE_ENTRY(jint, Unsafe_GetLoadAverage0(JNIEnv *env, jobject unsafe, jdoubleAr +@@ -1018,6 +1018,10 @@ UNSAFE_ENTRY(jint, Unsafe_GetLoadAverage0(JNIEnv *env, jobject unsafe, jdoubleAr + return ret; } UNSAFE_END - +UNSAFE_ENTRY(jboolean, Unsafe_GetUseFastSerializer(JNIEnv *env, jobject unsafe)) { + return UseFastSerializer; +} +UNSAFE_END -+ + /// JVM_RegisterUnsafeMethods - #define ADR "J" -@@ -1102,6 +1107,7 @@ static JNINativeMethod jdk_internal_misc_Unsafe_methods[] = { +@@ -1102,7 +1106,10 @@ static JNINativeMethod jdk_internal_misc_Unsafe_methods[] = { {CC "fullFence", CC "()V", FN_PTR(Unsafe_FullFence)}, {CC "isBigEndian0", CC "()Z", FN_PTR(Unsafe_isBigEndian0)}, +- {CC "unalignedAccess0", CC "()Z", FN_PTR(Unsafe_unalignedAccess0)} ++ {CC "unalignedAccess0", CC "()Z", FN_PTR(Unsafe_unalignedAccess0)}, ++ + {CC "getUseFastSerializer", CC "()Z", FN_PTR(Unsafe_GetUseFastSerializer)}, - {CC "unalignedAccess0", CC "()Z", FN_PTR(Unsafe_unalignedAccess0)} ++ }; + #undef CC diff --git a/src/hotspot/share/runtime/globals.hpp b/src/hotspot/share/runtime/globals.hpp -index 1e2408b4b..7fc3c1fb7 100644 +index 4b8dbe899..ec5a4e50c 100644 --- a/src/hotspot/share/runtime/globals.hpp +++ b/src/hotspot/share/runtime/globals.hpp -@@ -2670,6 +2670,10 @@ define_pd_global(uint64_t,MaxRAM, 1ULL*G); +@@ -2684,6 +2684,10 @@ define_pd_global(uint64_t,MaxRAM, 1ULL*G); JFR_ONLY(product(ccstr, StartFlightRecording, NULL, \ "Start flight recording with options")) \ \ @@ -47,34 +41,10 @@ index 1e2408b4b..7fc3c1fb7 100644 "Use platform unstable time where supported for timestamps only") diff --git a/src/java.base/share/classes/java/io/ObjectInputStream.java b/src/java.base/share/classes/java/io/ObjectInputStream.java -index 3386b1a08..d71d44a98 100644 +index 939b7647e..f59a51316 100644 --- a/src/java.base/share/classes/java/io/ObjectInputStream.java +++ b/src/java.base/share/classes/java/io/ObjectInputStream.java -@@ -295,6 +295,23 @@ public class ObjectInputStream - filterLogger = (filterLog.isLoggable(Logger.Level.DEBUG) - || filterLog.isLoggable(Logger.Level.TRACE)) ? filterLog : null; - } -+ -+ /* -+ * Logger for FastSerializer. -+ * Setup the FastSerializer logger if it is set to DEBUG. -+ * (Assuming it will not change). -+ */ -+ static final System.Logger fastSerLogger; -+ -+ static { -+ if (printFastSerializer) { -+ Logger fastSerLog = System.getLogger("fastSerializer"); -+ fastSerLogger = (fastSerLog.isLoggable(Logger.Level.DEBUG)) -+ ? fastSerLog : null; -+ } else { -+ fastSerLogger = null; -+ } -+ } - } - - /** filter stream for handling block data conversion */ -@@ -320,6 +337,9 @@ public class ObjectInputStream +@@ -331,6 +331,9 @@ public class ObjectInputStream /** if true, invoke resolveObject() */ private boolean enableResolve; @@ -84,7 +54,7 @@ index 3386b1a08..d71d44a98 100644 /** * Context during upcalls to class-defined readObject methods; holds * object currently being deserialized and descriptor for current class. -@@ -333,6 +353,33 @@ public class ObjectInputStream +@@ -344,6 +347,25 @@ public class ObjectInputStream */ private ObjectInputFilter serialFilter; @@ -106,19 +76,11 @@ index 3386b1a08..d71d44a98 100644 + private static final boolean fastSerializerEscapeMode = java.security.AccessController.doPrivileged( + new sun.security.action.GetBooleanAction( + "fastSerializerEscapeMode")).booleanValue(); -+ -+ /** -+ * value of "printFastSerializer" property, -+ * as true or false for printing FastSerializer logs. -+ */ -+ private static final boolean printFastSerializer = java.security.AccessController.doPrivileged( -+ new sun.security.action.GetBooleanAction( -+ "printFastSerializer")).booleanValue(); + /** * Creates an ObjectInputStream that reads from the specified InputStream. * A serialization stream header is read from the stream and verified. -@@ -410,6 +457,9 @@ public class ObjectInputStream +@@ -421,6 +443,9 @@ public class ObjectInputStream * transitively so that a complete equivalent graph of objects is * reconstructed by readObject. * @@ -128,7 +90,7 @@ index 3386b1a08..d71d44a98 100644 *

The root object is completely restored when all of its fields and the * objects it references are completely restored. At this point the object * validation callbacks are executed in order based on their registered -@@ -698,11 +748,20 @@ public class ObjectInputStream +@@ -709,11 +734,20 @@ public class ObjectInputStream vlist.register(obj, prio); } @@ -149,7 +111,7 @@ index 3386b1a08..d71d44a98 100644 *

The corresponding method in ObjectOutputStream is * annotateClass. This method will be invoked only once for * each unique class in the stream. This method can be implemented by -@@ -741,18 +800,33 @@ public class ObjectInputStream +@@ -752,16 +786,26 @@ public class ObjectInputStream throws IOException, ClassNotFoundException { String name = desc.getName(); @@ -165,9 +127,7 @@ index 3386b1a08..d71d44a98 100644 return cl; - } else { + } -+ } -+ -+ try { ++ } try { + cl = Class.forName(name, false, latestUserDefinedLoader()); + } catch (ClassNotFoundException ex) { + cl = primClasses.get(name); @@ -175,20 +135,15 @@ index 3386b1a08..d71d44a98 100644 throw ex; } } -+ + if (useFastSerializer) { + nameToClass.put(name, cl); + } + + return cl; -+ } -+ /** - * Returns a proxy class that implements the interfaces named in a proxy - * class descriptor; subclasses may implement this method to read custom -@@ -924,9 +998,33 @@ public class ObjectInputStream +@@ -935,9 +979,25 @@ public class ObjectInputStream { short s0 = bin.readShort(); short s1 = bin.readShort(); @@ -199,7 +154,7 @@ index 3386b1a08..d71d44a98 100644 + if (s0 != STREAM_MAGIC_FAST || s1 != STREAM_VERSION) { + if (s0 != STREAM_MAGIC) { + throw new StreamCorruptedException( -+ String.format("invalid stream header: %04X%04X, and FastSerializer is activated", s0, s1)); ++ String.format("invalid stream header: %04X%04X", s0, s1)); + } + + if (!fastSerializerEscapeMode) { @@ -210,22 +165,14 @@ index 3386b1a08..d71d44a98 100644 + + // Escape to default serialization + useFastSerializer = false; -+ if (Logging.fastSerLogger != null) { -+ Logging.fastSerLogger.log(Logger.Level.DEBUG, "[Deserialize]: Escape and disable FastSerializer"); -+ } + } + } else if (s0 != STREAM_MAGIC || s1 != STREAM_VERSION) { -+ if (s0 == STREAM_MAGIC_FAST && s1 == STREAM_VERSION) { -+ throw new StreamCorruptedException( -+ String.format("invalid stream header: %04X%04X, and it is a FastSerializer stream", s0, s1)); -+ } else { + throw new StreamCorruptedException( + String.format("invalid stream header: %04X%04X", s0, s1)); -+ } } } -@@ -940,6 +1038,11 @@ public class ObjectInputStream +@@ -951,6 +1011,11 @@ public class ObjectInputStream * this method reads class descriptors according to the format defined in * the Object Serialization specification. * @@ -237,7 +184,7 @@ index 3386b1a08..d71d44a98 100644 * @return the class descriptor read * @throws IOException If an I/O error has occurred. * @throws ClassNotFoundException If the Class of a serialized object used -@@ -950,6 +1053,29 @@ public class ObjectInputStream +@@ -961,6 +1026,29 @@ public class ObjectInputStream protected ObjectStreamClass readClassDescriptor() throws IOException, ClassNotFoundException { @@ -267,20 +214,7 @@ index 3386b1a08..d71d44a98 100644 ObjectStreamClass desc = new ObjectStreamClass(); desc.readNonProxy(this); return desc; -@@ -1946,10 +2072,12 @@ public class ObjectInputStream - } - - ObjectStreamClass desc = new ObjectStreamClass(); -+ - int descHandle = handles.assign(unshared ? unsharedMarker : desc); - passHandle = NULL_HANDLE; - - ObjectStreamClass readDesc; -+ - try { - readDesc = readClassDescriptor(); - } catch (ClassNotFoundException ex) { -@@ -1976,17 +2104,40 @@ public class ObjectInputStream +@@ -2008,36 +2096,52 @@ public class ObjectInputStream skipCustomData(); @@ -288,11 +222,19 @@ index 3386b1a08..d71d44a98 100644 - totalObjectRefs++; - depth++; - desc.initNonProxy(readDesc, cl, resolveEx, readClassDesc(false)); -- } finally { -- depth--; + totalObjectRefs++; + depth++; -+ + +- if (cl != null) { +- // Check that serial filtering has been done on the local class descriptor's superclass, +- // in case it does not appear in the stream. +- +- // Find the next super descriptor that has a local class descriptor. +- // Descriptors for which there is no local class are ignored. +- ObjectStreamClass superLocal = null; +- for (ObjectStreamClass sDesc = desc.getSuperDesc(); sDesc != null; sDesc = sDesc.getSuperDesc()) { +- if ((superLocal = sDesc.getLocalDesc()) != null) { +- break; + if (useFastSerializer) { + desc.initNonProxyFast(readDesc, resolveEx); + ObjectStreamClass superDesc = desc.getSuperDesc(); @@ -310,33 +252,57 @@ index 3386b1a08..d71d44a98 100644 + } else { + try { + desc.initNonProxy(readDesc, cl, resolveEx, readClassDesc(false)); ++ ++ if (cl != null) { ++ // Check that serial filtering has been done on the local class descriptor's superclass, ++ // in case it does not appear in the stream. ++ // Find the next super descriptor that has a local class descriptor. ++ // Descriptors for which there is no local class are ignored. ++ ObjectStreamClass superLocal = null; ++ for (ObjectStreamClass sDesc = desc.getSuperDesc(); sDesc != null; sDesc = sDesc.getSuperDesc()) { ++ if ((superLocal = sDesc.getLocalDesc()) != null) { ++ break; ++ } + } +- } + +- // Scan local descriptor superclasses for a match with the local descriptor of the super found above. +- // For each super descriptor before the match, invoke the serial filter on the class. +- // The filter is invoked for each class that has not already been filtered +- // but would be filtered if the instance had been serialized by this Java runtime. +- for (ObjectStreamClass lDesc = desc.getLocalDesc().getSuperDesc(); +- lDesc != null && lDesc != superLocal; +- lDesc = lDesc.getSuperDesc()) { +- filterCheck(lDesc.forClass(), -1); ++ // Scan local descriptor superclasses for a match with the local descriptor of the super found above. ++ // For each super descriptor before the match, invoke the serial filter on the class. ++ // The filter is invoked for each class that has not already been filtered ++ // but would be filtered if the instance had been serialized by this Java runtime. ++ for (ObjectStreamClass lDesc = desc.getLocalDesc().getSuperDesc(); ++ lDesc != null && lDesc != superLocal; ++ lDesc = lDesc.getSuperDesc()) { ++ filterCheck(lDesc.forClass(), -1); ++ } + } + } finally { + depth--; -+ } + } +- } finally { +- depth--; } handles.finish(descHandle); - passHandle = descHandle; - -+ if (Logging.fastSerLogger != null) { -+ Logging.fastSerLogger.log(Logger.Level.DEBUG, -+ "[Deserialize] useFastSerializer:{0}, Class name:{1}, SerialVersionUID:{2}, flags:{3}", -+ useFastSerializer, desc.getName(), desc.getSerialVersionUID(), desc.getFlags(this)); -+ } -+ - return desc; - } - -@@ -2873,7 +3024,6 @@ public class ObjectInputStream +@@ -2936,8 +3040,6 @@ public class ObjectInputStream } } - private static final Unsafe UNSAFE = Unsafe.getUnsafe(); - +- /** * Performs a "freeze" action, required to adhere to final field semantics. + * diff --git a/src/java.base/share/classes/java/io/ObjectOutputStream.java b/src/java.base/share/classes/java/io/ObjectOutputStream.java -index 135e5645a..8935e61dc 100644 +index 135e5645a..044924593 100644 --- a/src/java.base/share/classes/java/io/ObjectOutputStream.java +++ b/src/java.base/share/classes/java/io/ObjectOutputStream.java @@ -36,6 +36,7 @@ import java.util.StringJoiner; @@ -347,33 +313,7 @@ index 135e5645a..8935e61dc 100644 import sun.reflect.misc.ReflectUtil; /** -@@ -174,6 +175,25 @@ public class ObjectOutputStream - new ReferenceQueue<>(); - } - -+ private static class Logging { -+ /* -+ * Logger for FastSerializer. -+ * Setup the FastSerializer logger if it is set to DEBUG. -+ * (Assuming it will not change). -+ */ -+ static final System.Logger fastSerLogger; -+ -+ static { -+ if (printFastSerializer) { -+ System.Logger fastSerLog = System.getLogger("fastSerializer"); -+ fastSerLogger = (fastSerLog.isLoggable(System.Logger.Level.DEBUG)) -+ ? fastSerLog : null; -+ } else { -+ fastSerLogger = null; -+ } -+ } -+ } -+ - /** filter stream for handling block data conversion */ - private final BlockDataOutputStream bout; - /** obj -> wire handle map */ -@@ -192,7 +212,6 @@ public class ObjectOutputStream +@@ -192,7 +193,6 @@ public class ObjectOutputStream private final boolean enableOverride; /** if true, invoke replaceObject() */ private boolean enableReplace; @@ -381,7 +321,7 @@ index 135e5645a..8935e61dc 100644 // values below valid only during upcalls to writeObject()/writeExternal() /** * Context during upcalls to class-defined writeObject methods; holds -@@ -215,6 +234,22 @@ public class ObjectOutputStream +@@ -215,6 +215,14 @@ public class ObjectOutputStream new sun.security.action.GetBooleanAction( "sun.io.serialization.extendedDebugInfo")).booleanValue(); @@ -392,19 +332,11 @@ index 135e5645a..8935e61dc 100644 + * on when it is true. + */ + private static final boolean useFastSerializer = UNSAFE.getUseFastSerializer(); -+ -+ /** -+ * value of "printFastSerializer" property, -+ * as true or false for printing FastSerializer logs. -+ */ -+ private static final boolean printFastSerializer = java.security.AccessController.doPrivileged( -+ new sun.security.action.GetBooleanAction( -+ "printFastSerializer")).booleanValue(); + /** * Creates an ObjectOutputStream that writes to the specified OutputStream. * This constructor writes the serialization stream header to the -@@ -328,6 +363,9 @@ public class ObjectOutputStream +@@ -328,6 +336,9 @@ public class ObjectOutputStream * object are written transitively so that a complete equivalent graph of * objects can be reconstructed by an ObjectInputStream. * @@ -414,7 +346,7 @@ index 135e5645a..8935e61dc 100644 *

Exceptions are thrown for problems with the OutputStream and for * classes that should not be serialized. All exceptions are fatal to the * OutputStream, which is left in an indeterminate state, and it is up to -@@ -636,7 +674,11 @@ public class ObjectOutputStream +@@ -636,7 +647,11 @@ public class ObjectOutputStream * stream */ protected void writeStreamHeader() throws IOException { @@ -427,7 +359,7 @@ index 135e5645a..8935e61dc 100644 bout.writeShort(STREAM_VERSION); } -@@ -651,6 +693,9 @@ public class ObjectOutputStream +@@ -651,6 +666,9 @@ public class ObjectOutputStream * By default, this method writes class descriptors according to the format * defined in the Object Serialization specification. * @@ -437,7 +369,7 @@ index 135e5645a..8935e61dc 100644 *

Note that this method will only be called if the ObjectOutputStream * is not using the old serialization stream format (set by calling * ObjectOutputStream's useProtocolVersion method). If this -@@ -668,7 +713,14 @@ public class ObjectOutputStream +@@ -668,7 +686,14 @@ public class ObjectOutputStream protected void writeClassDescriptor(ObjectStreamClass desc) throws IOException { @@ -453,16 +385,8 @@ index 135e5645a..8935e61dc 100644 } /** -@@ -1276,9 +1328,21 @@ public class ObjectOutputStream - bout.writeByte(TC_CLASSDESC); - handles.assign(unshared ? null : desc); +@@ -1278,7 +1303,13 @@ public class ObjectOutputStream -+ if (Logging.fastSerLogger != null) { -+ Logging.fastSerLogger.log(System.Logger.Level.DEBUG, -+ "[Serialize] useFastSerializer:{0}, Class name:{1}, SerialVersionUID:{2}, flags:{3}, protocol:{4}", -+ useFastSerializer, desc.getName(), desc.getSerialVersionUID(), desc.getFlags(this), protocol); -+ } -+ if (protocol == PROTOCOL_VERSION_1) { // do not invoke class descriptor write hook with old protocol - desc.writeNonProxy(this); @@ -476,7 +400,7 @@ index 135e5645a..8935e61dc 100644 } else { writeClassDescriptor(desc); } -@@ -1291,8 +1355,9 @@ public class ObjectOutputStream +@@ -1291,8 +1322,9 @@ public class ObjectOutputStream annotateClass(cl); bout.setBlockDataMode(false); bout.writeByte(TC_ENDBLOCKDATA); @@ -489,51 +413,10 @@ index 135e5645a..8935e61dc 100644 /** diff --git a/src/java.base/share/classes/java/io/ObjectStreamClass.java b/src/java.base/share/classes/java/io/ObjectStreamClass.java -index 17739cdc7..a5d7d2d75 100644 +index 17739cdc7..ac3a92bef 100644 --- a/src/java.base/share/classes/java/io/ObjectStreamClass.java +++ b/src/java.base/share/classes/java/io/ObjectStreamClass.java -@@ -270,6 +270,40 @@ public class ObjectStreamClass implements Serializable { - return suid.longValue(); - } - -+ /** -+ * Return the flags for this class described by this descriptor. The flags -+ * means a set of bit masks for ObjectStreamClass, which indicate the status -+ * of SC_WRITE_METHOD, SC_SERIALIZABLE, SC_EXTERNALIZABLE, SC_BLOCK_DATA and -+ * SC_ENUM. -+ * -+ * @param serialStream ObjectOutputStream or ObjectInputStream -+ * -+ * @return the flags for this class described by this descriptor -+ */ -+ public byte getFlags(Object serialStream) { -+ byte flags = 0; -+ if (externalizable) { -+ flags |= ObjectStreamConstants.SC_EXTERNALIZABLE; -+ if (serialStream instanceof ObjectOutputStream) { -+ int protocol = ((ObjectOutputStream)serialStream).getProtocolVersion(); -+ if (protocol != ObjectStreamConstants.PROTOCOL_VERSION_1) { -+ flags |= ObjectStreamConstants.SC_BLOCK_DATA; -+ } -+ } else if (serialStream instanceof ObjectInputStream) { -+ flags |= ObjectStreamConstants.SC_BLOCK_DATA; -+ } -+ } else if (serializable) { -+ flags |= ObjectStreamConstants.SC_SERIALIZABLE; -+ } -+ if (hasWriteObjectData) { -+ flags |= ObjectStreamConstants.SC_WRITE_METHOD; -+ } -+ if (isEnum) { -+ flags |= ObjectStreamConstants.SC_ENUM; -+ } -+ return flags; -+ } -+ - /** - * Return the class in the local VM that this version is mapped to. Null - * is returned if there is no corresponding local class. -@@ -560,6 +594,15 @@ public class ObjectStreamClass implements Serializable { +@@ -560,6 +560,15 @@ public class ObjectStreamClass implements Serializable { ObjectStreamClass() { } @@ -549,7 +432,7 @@ index 17739cdc7..a5d7d2d75 100644 /** * Creates a PermissionDomain that grants no permission. */ -@@ -746,6 +789,44 @@ public class ObjectStreamClass implements Serializable { +@@ -746,6 +755,44 @@ public class ObjectStreamClass implements Serializable { initialized = true; } @@ -623,3 +506,6 @@ index 031b5aae5..d78caabdc 100644 private native long allocateMemory0(long bytes); private native long reallocateMemory0(long address, long bytes); private native void freeMemory0(long address); +-- +2.19.0 + diff --git a/fix-error-in-build-core-variants.patch b/fix-error-in-build-core-variants.patch new file mode 100755 index 0000000000000000000000000000000000000000..560ba27ce6e4228367c07a90389211379a8c3c17 --- /dev/null +++ b/fix-error-in-build-core-variants.patch @@ -0,0 +1,14 @@ +diff --git a/src/hotspot/cpu/aarch64/globals_aarch64.hpp b/src/hotspot/cpu/aarch64/globals_aarch64.hpp +index f26ea2a8b..d8b198a0b 100644 +--- a/src/hotspot/cpu/aarch64/globals_aarch64.hpp ++++ b/src/hotspot/cpu/aarch64/globals_aarch64.hpp +@@ -80,9 +80,7 @@ define_pd_global(intx, InitArrayShortSize, BytesPerLong); + + define_pd_global(bool, ThreadLocalHandshakes, true); + +-#if defined(COMPILER1) || defined(COMPILER2) + define_pd_global(intx, InlineSmallCode, 1000); +-#endif + + #define ARCH_FLAGS(develop, \ + product, \ diff --git a/fix-jck-failure-on-FastSerializer.patch b/fix-jck-failure-on-FastSerializer.patch index bb850482ae603596c1930c000565854ffdb67625..b2e1710ee9d43ddb08aa87fd9b51208e4e597abc 100644 --- a/fix-jck-failure-on-FastSerializer.patch +++ b/fix-jck-failure-on-FastSerializer.patch @@ -1,34 +1,20 @@ -From cd63946e80ceb3f9de8a1ee02b38548c06cf532a Mon Sep 17 00:00:00 2001 -Date: Thu, 23 Jul 2020 16:40:31 +0800 -Subject: [PATCH] fix jck failure on FastSerializer - -Summary: : -LLT: jck -Bug url: NA ---- - src/java.base/share/classes/java/io/ObjectInputStream.java | 7 ++++++- - src/java.base/share/classes/java/io/ObjectOutputStream.java | 5 +++++ - src/java.base/share/classes/java/io/ObjectStreamClass.java | 2 +- - src/java.base/share/classes/java/io/ObjectStreamConstants.java | 5 ----- - 4 files changed, 12 insertions(+), 7 deletions(-) - diff --git a/src/java.base/share/classes/java/io/ObjectInputStream.java b/src/java.base/share/classes/java/io/ObjectInputStream.java -index d71d44a..a48e50c 100644 +index a77a5d5b6..f2791a4cb 100644 --- a/src/java.base/share/classes/java/io/ObjectInputStream.java +++ b/src/java.base/share/classes/java/io/ObjectInputStream.java -@@ -381,6 +381,11 @@ public class ObjectInputStream +@@ -391,6 +391,11 @@ public class ObjectInputStream + new sun.security.action.GetBooleanAction( "printFastSerializer")).booleanValue(); - /** ++ /** + * Magic number that is written to the stream header when using fastserilizer. + */ + private static final short STREAM_MAGIC_FAST = (short)0xdeca; + -+ /** + /** * Creates an ObjectInputStream that reads from the specified InputStream. * A serialization stream header is read from the stream and verified. - * This constructor will block until the corresponding ObjectOutputStream -@@ -752,7 +757,7 @@ public class ObjectInputStream +@@ -763,7 +768,7 @@ public class ObjectInputStream * Cache the class meta during serialization. * Only used in FastSerilizer. */ @@ -38,23 +24,23 @@ index d71d44a..a48e50c 100644 /** * Load the local class equivalent of the specified stream class diff --git a/src/java.base/share/classes/java/io/ObjectOutputStream.java b/src/java.base/share/classes/java/io/ObjectOutputStream.java -index 8935e61..0e54763 100644 +index 8935e61dc..0e5476395 100644 --- a/src/java.base/share/classes/java/io/ObjectOutputStream.java +++ b/src/java.base/share/classes/java/io/ObjectOutputStream.java -@@ -251,6 +251,11 @@ public class ObjectOutputStream +@@ -250,6 +250,11 @@ public class ObjectOutputStream + new sun.security.action.GetBooleanAction( "printFastSerializer")).booleanValue(); - /** ++ /** + * Magic number that is written to the stream header when using fastserilizer. + */ + private static final short STREAM_MAGIC_FAST = (short)0xdeca; + -+ /** + /** * Creates an ObjectOutputStream that writes to the specified OutputStream. * This constructor writes the serialization stream header to the - * underlying stream; callers may wish to flush the stream immediately to diff --git a/src/java.base/share/classes/java/io/ObjectStreamClass.java b/src/java.base/share/classes/java/io/ObjectStreamClass.java -index a5d7d2d..e37a784 100644 +index a5d7d2d75..e37a7841e 100644 --- a/src/java.base/share/classes/java/io/ObjectStreamClass.java +++ b/src/java.base/share/classes/java/io/ObjectStreamClass.java @@ -280,7 +280,7 @@ public class ObjectStreamClass implements Serializable { @@ -67,22 +53,21 @@ index a5d7d2d..e37a784 100644 if (externalizable) { flags |= ObjectStreamConstants.SC_EXTERNALIZABLE; diff --git a/src/java.base/share/classes/java/io/ObjectStreamConstants.java b/src/java.base/share/classes/java/io/ObjectStreamConstants.java -index 9615778..43a480c 100644 +index 96157782a..43a480ce4 100644 --- a/src/java.base/share/classes/java/io/ObjectStreamConstants.java +++ b/src/java.base/share/classes/java/io/ObjectStreamConstants.java -@@ -39,11 +39,6 @@ public interface ObjectStreamConstants { +@@ -38,11 +38,6 @@ public interface ObjectStreamConstants { + */ static final short STREAM_MAGIC = (short)0xaced; - /** +- /** - * Magic number that is written to the stream header when using fastserilizer. - */ - static final short STREAM_MAGIC_FAST = (short)0xdeca; - -- /** + /** * Version number that is written to the stream header. */ - static final short STREAM_VERSION = 5; -- -1.8.3.1 - +2.19.0 diff --git a/fix_macroAssembler_missing_matcher_header_file_causing_build_failure.patch b/fix_macroAssembler_missing_matcher_header_file_causing_build_failure.patch new file mode 100755 index 0000000000000000000000000000000000000000..26e842b8ddd76bddf165dcc709dcba7c7bdc91cd --- /dev/null +++ b/fix_macroAssembler_missing_matcher_header_file_causing_build_failure.patch @@ -0,0 +1,15 @@ +diff --git a/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp b/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp +index b6b070e62..60dc92953 100644 +--- a/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp ++++ b/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp +@@ -50,6 +50,7 @@ + #include "c1/c1_LIRAssembler.hpp" + #endif + #ifdef COMPILER2 ++#include "opto/matcher.hpp" + #include "oops/oop.hpp" + #include "opto/compile.hpp" + #include "opto/intrinsicnode.hpp" +-- +2.19.0 + diff --git a/jdk-updates-jdk11u-jdk-11.0.13-ga.tar.xz b/jdk-updates-jdk11u-jdk-11.0.14-ga.tar.xz similarity index 84% rename from jdk-updates-jdk11u-jdk-11.0.13-ga.tar.xz rename to jdk-updates-jdk11u-jdk-11.0.14-ga.tar.xz index e8ba78a3554395139e53bfa3b7ab156db9d720ab..6296a450788e93a7d91cd37b6058f59b35379cf6 100644 Binary files a/jdk-updates-jdk11u-jdk-11.0.13-ga.tar.xz and b/jdk-updates-jdk11u-jdk-11.0.14-ga.tar.xz differ diff --git a/openjdk-11.spec b/openjdk-11.spec index 110a5de4cf3156b8210b499e3af6707ab76abbc5..f4e93b2f974a1d6e4fd5609d847bbc049b140d76 100644 --- a/openjdk-11.spec +++ b/openjdk-11.spec @@ -1,4 +1,4 @@ -# RPM conditionals so as to be able to dynamically produce +# RPM conditionals so as to be able to dynamically producef # slowdebug/release builds. See: # http://rpm.org/user_doc/conditional_builds.html @@ -114,7 +114,7 @@ # New Version-String scheme-style defines %global majorver 11 -%global securityver 13 +%global securityver 14 # buildjdkver is usually same as %%{majorver}, # but in time of bootstrap of next jdk, it is majorver-1, # and this it is better to change it here, on single place @@ -135,7 +135,7 @@ %global project jdk-updates %global repo jdk11u -%global revision jdk-11.0.13-ga +%global revision jdk-11.0.14-ga %global full_revision %{project}-%{repo}-%{revision} # priority must be 7 digits in total # setting to 1, so debug ones can have 0 @@ -506,7 +506,7 @@ exit 0 %dir %{etcjavadir -- %{?1}}/conf/security/policy/limited %dir %{etcjavadir -- %{?1}}/conf/security/policy/unlimited %config(noreplace) %{etcjavadir -- %{?1}}/lib/security/default.policy -%config(noreplace) %{etcjavadir -- %{?1}}/lib/security/blacklisted.certs +%config(noreplace) %{etcjavadir -- %{?1}}/lib/security/blocked.certs %config(noreplace) %{etcjavadir -- %{?1}}/lib/security/public_suffix_list.dat %config(noreplace) %{etcjavadir -- %{?1}}/conf/security/policy/limited/exempt_local.policy %config(noreplace) %{etcjavadir -- %{?1}}/conf/security/policy/limited/default_local.policy @@ -740,7 +740,7 @@ Provides: java-src%{?1} = %{epoch}:%{version}-%{release} Name: java-%{javaver}-%{origin} Version: %{newjavaver}.%{buildver} -Release: 7 +Release: 1 # java-1.5.0-ibm from jpackage.org set Epoch to 1 for unknown reasons # and this change was brought into RHEL-4. java-1.5.0-ibm packages # also included the epoch in their virtual provides. This created a @@ -825,7 +825,8 @@ Patch35: NUMA-Aware-Implementation-humongous-region.patch Patch36: ZGC-in-c1-load-barrier-d0-and-d1-registers-miss-restoring.patch Patch37: fix-compile-error-without-disable-precompiled-headers.patch Patch38: fast-serializer-jdk11.patch -Patch39: fix-jck-failure-on-FastSerializer.patch +Patch39: dfx-enhancement-of-FastSerializer.patch +Patch40: fix-jck-failure-on-FastSerializer.patch Patch42: 8229496-SIGFPE-division-by-zero-in-C2-OSR-compiled-method.patch Patch45: leaf-optimize-in-ParallelScanvageGC.patch Patch46: ZGC-correct-free-heap-size-excluding-waste-in-rule_allocation_rate.patch @@ -834,16 +835,17 @@ Patch48: 8205921-Optimizing-best_of_2-work-stealing-queue-selection.patch # 11.0.9 Patch55: 8215047-Task-terminators-do-not-complete-termination-in-consistent-state.patch -Patch57: add-zgc-parameter-adaptation-feature.patch -Patch58: add-integerCache-feature.patch -Patch59: add-SVE-backend-feature.patch +Patch56: add-zgc-parameter-adaptation-feature.patch +Patch57: add-integerCache-feature.patch +Patch58: 8231441-1-AArch64-Initial-SVE-backend-support.patch +Patch59: 8231441-2-AArch64-Initial-SVE-backend-support.patch +Patch60: 8231441-3-AArch64-Initial-SVE-backend-support.patch # 11.0.10 Patch61: downgrade-the-symver-of-log2f-posix-spawn.patch Patch62: 8254078-DataOutputStream-is-very-slow-post-disabling.patch Patch65: add-LazyBox-feature.patch Patch66: add-G1-Full-GC-optimization.patch -Patch67: 8214535-support-Jmap-parallel.patch Patch68: src-openeuler-openjdk-11-resolve-code-inconsistencies.patch Patch69: G1-iterate-region-by-bitmap-rather-than-obj-size-in.patch @@ -866,7 +868,10 @@ Patch82: PS-introduce-UsePSRelaxedForwardee-to-enable-using-r.patch Patch83: 8273111-Default-timezone-should-return-zone-ID-if-locatiome-is-valid-but-not-canonicalization-on-linux.patch Patch84: fix-memcpy-compile-warning-when-building-on-linux-x86.patch Patch85: 8239017-cmp-baseline-fails-because-of-differences-in-TimeZoneNames_kea.patch -Patch86: Delete-expired-certificate-globalsignr2ca.patch +# 11.0.14 +Patch86: 8252103-support-Jmap-parallel-heap-inspection.patch +Patch87: fix_macroAssembler_missing_matcher_header_file_causing_build_failure.patch +Patch88: fix-error-in-build-core-variants.patch BuildRequires: autoconf BuildRequires: alsa-lib-devel @@ -1120,20 +1125,22 @@ pushd %{top_level_dir_name} %patch37 -p1 %patch38 -p1 %patch39 -p1 +%patch40 -p1 %patch42 -p1 %patch45 -p1 %patch46 -p1 %patch47 -p1 %patch48 -p1 %patch55 -p1 +%patch56 -p1 %patch57 -p1 %patch58 -p1 %patch59 -p1 +%patch60 -p1 %patch61 -p1 %patch62 -p1 %patch65 -p1 %patch66 -p1 -%patch67 -p1 %patch68 -p1 %patch69 -p1 %patch71 -p1 @@ -1151,6 +1158,8 @@ pushd %{top_level_dir_name} %patch84 -p1 %patch85 -p1 %patch86 -p1 +%patch87 -p1 +%patch88 -p1 popd # openjdk # %patch1000 @@ -1660,6 +1669,12 @@ cjc.mainProgram(arg) %changelog +* Wed Feb 9 2022 kuenking111 - 1:11.0.14.9-1 +- add fix-error-in-build-core-variants.patch + +* Tue Feb 8 2022 kuenking111 - 1:11.0.14.9-0 +- Update to 11.0.14+9 (GA) + * Wed Jan 05 2021 noah - 1:11.0.13.7-7 - adapted to newst cjc to fix issue with rpm 4.17 @@ -1752,10 +1767,10 @@ cjc.mainProgram(arg) * Sun Feb 7 2021 jdkboy - 1:11.0.10.9-2 - remove redundant file info -* Thu Feb 5 2021 eapen - 1:11.0.10.9-1 +* Fri Feb 5 2021 eapen - 1:11.0.10.9-1 - add 8240353.patch -* Thu Feb 5 2021 eapen - 1:11.0.10.9-0 +* Fri Feb 5 2021 eapen - 1:11.0.10.9-0 - update to 11.0.10+9(GA) - use system harfbuzz now this is supported @@ -1820,7 +1835,7 @@ cjc.mainProgram(arg) * Mon Sep 7 2020 noah - 1:11.0.8.10-5 - Delete some file header information -* Tue Aug 31 2020 jdkboy - 1:11.0.8.10-4 +* Mon Aug 31 2020 jdkboy - 1:11.0.8.10-4 - Add 8210473-JEP-345-NUMA-Aware-Memory-Allocation-for-G1.patch - Add 8210461-AArch64-Math.cos-intrinsic-gives-incorrect-results.patch - Add NUMA-Aware-Implementation-humongous-region.patch @@ -1844,13 +1859,13 @@ cjc.mainProgram(arg) * Sat Jul 18 2020 jvmboy - 1:11.0.8.10-0 - Update to 11.0.8+10 (GA) -* Thu Jun 9 2020 jdkboy - 1:11.0.7.10-5 +* The Jun 9 2020 jdkboy - 1:11.0.7.10-5 - Version support fulljavaver.buildver - Judge with_systemtap - 8228407: JVM crashes with shared archive file mismatch - Remove javadoc-slowdebug -* Thu May 25 2020 noah - 1:11.0.7.10-4 +* Mon May 25 2020 noah - 1:11.0.7.10-4 - Support nss, systemtap and desktop * Thu May 21 2020 jdkboy - 1:11.0.7.10-3 diff --git a/src-openeuler-openjdk-11-resolve-code-inconsistencies.patch b/src-openeuler-openjdk-11-resolve-code-inconsistencies.patch index cbf0442c882c0a0ec790d68fa291fcb7f3bc6757..65015d65cd7c67967dc2c696d816c801f2063037 100644 --- a/src-openeuler-openjdk-11-resolve-code-inconsistencies.patch +++ b/src-openeuler-openjdk-11-resolve-code-inconsistencies.patch @@ -484,19 +484,6 @@ index c60609617..f0b8638c1 100644 case Humongous: return "Humongous"; case NotInCSet: return "NotInCSet"; case Young: return "Young"; -diff --git a/src/hotspot/share/gc/parallel/parallelScavengeHeap.cpp b/src/hotspot/share/gc/parallel/parallelScavengeHeap.cpp -index c70d8e89a..c8a3abaf3 100644 ---- a/src/hotspot/share/gc/parallel/parallelScavengeHeap.cpp -+++ b/src/hotspot/share/gc/parallel/parallelScavengeHeap.cpp -@@ -542,7 +542,7 @@ public: - // Claim the block and get the block index. - size_t claim_and_get_block() { - size_t block_index; -- block_index = Atomic::add(1u, &_claimed_index) - 1; // TODO: original impl is: Atomic::fetch_and_add(&_claimed_index, 1u); -+ block_index = Atomic::add(1u, &_claimed_index) - 1; - - PSOldGen* old_gen = ParallelScavengeHeap::heap()->old_gen(); - size_t num_claims = old_gen->num_iterable_blocks() + NumNonOldGenClaims; diff --git a/src/hotspot/share/gc/shared/c2/barrierSetC2.hpp b/src/hotspot/share/gc/shared/c2/barrierSetC2.hpp index 8b4be7d11..1b9dd5ada 100644 --- a/src/hotspot/share/gc/shared/c2/barrierSetC2.hpp @@ -544,19 +531,6 @@ index 0f3c429ed..82fde2c94 100644 do_task(q, cl, live_data, &t); work++; } else { -diff --git a/src/hotspot/share/memory/heapInspection.cpp b/src/hotspot/share/memory/heapInspection.cpp -index dd76165a7..d492751a6 100644 ---- a/src/hotspot/share/memory/heapInspection.cpp -+++ b/src/hotspot/share/memory/heapInspection.cpp -@@ -746,7 +746,7 @@ class RecordInstanceClosure : public ObjectClosure { - }; - - // Heap inspection for every worker. --// When native OOM hanppens for KlassInfoTable, set _success to false. -+// When native OOM happens for KlassInfoTable, set _success to false. - void ParHeapInspectTask::work(uint worker_id) { - uintx missed_count = 0; - bool merge_success = true; diff --git a/src/hotspot/share/opto/graphKit.cpp b/src/hotspot/share/opto/graphKit.cpp index 22222efbc..5849e8f86 100644 --- a/src/hotspot/share/opto/graphKit.cpp @@ -640,23 +614,6 @@ index 74aab91f9..6cf2d2a6d 100644 } // Verify that verify_me made the same decisions as a fresh run. -diff --git a/src/hotspot/share/prims/unsafe.cpp b/src/hotspot/share/prims/unsafe.cpp -index 784dc782f..9158f6d36 100644 ---- a/src/hotspot/share/prims/unsafe.cpp -+++ b/src/hotspot/share/prims/unsafe.cpp -@@ -1100,9 +1100,11 @@ static JNINativeMethod jdk_internal_misc_Unsafe_methods[] = { - {CC "fullFence", CC "()V", FN_PTR(Unsafe_FullFence)}, - - {CC "isBigEndian0", CC "()Z", FN_PTR(Unsafe_isBigEndian0)}, -+ {CC "unalignedAccess0", CC "()Z", FN_PTR(Unsafe_unalignedAccess0)}, -+ - {CC "getUseHashMapIntegerCache", CC "()Z", FN_PTR(Unsafe_GetUseHashMapIntegerCache)}, - {CC "getUseFastSerializer", CC "()Z", FN_PTR(Unsafe_GetUseFastSerializer)}, -- {CC "unalignedAccess0", CC "()Z", FN_PTR(Unsafe_unalignedAccess0)} -+ - }; - - #undef CC diff --git a/src/hotspot/share/runtime/memcpy.cpp b/src/hotspot/share/runtime/memcpy.cpp new file mode 100644 index 000000000..ed8330679 diff --git a/support_jmap_parallel_inspection_for_cms_gc.patch b/support_jmap_parallel_inspection_for_cms_gc.patch index a87ab109e17e263dc39258f8a98254561d0f3a76..aeea56b7edafaabf799f6d7b2429219c62af3ab2 100755 --- a/support_jmap_parallel_inspection_for_cms_gc.patch +++ b/support_jmap_parallel_inspection_for_cms_gc.patch @@ -172,13 +172,14 @@ index 4f272394b..9e93fefac 100644 bool refs_discovery_is_mt() const { // Note: CMS does MT-discovery during the parallel-remark diff --git a/test/jdk/sun/tools/jmap/BasicJMapTest.java b/test/jdk/sun/tools/jmap/BasicJMapTest.java -index 960705e24..f87774f93 100644 +index 327feb25d..ad890f880 100644 --- a/test/jdk/sun/tools/jmap/BasicJMapTest.java +++ b/test/jdk/sun/tools/jmap/BasicJMapTest.java -@@ -74,6 +74,20 @@ import jdk.testlibrary.ProcessTools; - * @run main/othervm/timeout=240 -XX:+UseG1GC BasicJMapTest +@@ -45,6 +45,21 @@ import jdk.testlibrary.ProcessTools; + * @build jdk.test.lib.hprof.util.* + * @run main/timeout=240 BasicJMapTest */ - ++ +/* + * @test id=CMS + * @summary Unit test for jmap utility (CMS GC)