diff --git a/8231441-3-AArch64-Initial-SVE-backend-support.patch b/8231441-3-AArch64-Initial-SVE-backend-support.patch index 3691f9dfefabf92ff666d4b6d844072bd2500fab..3418659180d38bd8521a98d070e1f2a0136ad5c6 100755 --- a/8231441-3-AArch64-Initial-SVE-backend-support.patch +++ b/8231441-3-AArch64-Initial-SVE-backend-support.patch @@ -1,8 +1,8 @@ diff --git a/make/hotspot/gensrc/GensrcAdlc.gmk b/make/hotspot/gensrc/GensrcAdlc.gmk -index a39640526..2479853fa 100644 +index 2af2f9a..f23b972 100644 --- a/make/hotspot/gensrc/GensrcAdlc.gmk +++ b/make/hotspot/gensrc/GensrcAdlc.gmk -@@ -146,6 +146,12 @@ ifeq ($(call check-jvm-feature, compiler2), true) +@@ -156,6 +156,12 @@ ifeq ($(call check-jvm-feature, compiler2), true) ))) endif @@ -15,436 +15,709 @@ index a39640526..2479853fa 100644 ifeq ($(call check-jvm-feature, shenandoahgc), true) AD_SRC_FILES += $(call uniq, $(wildcard $(foreach d, $(AD_SRC_ROOTS), \ $d/cpu/$(HOTSPOT_TARGET_CPU_ARCH)/gc/shenandoah/shenandoah_$(HOTSPOT_TARGET_CPU).ad \ -diff --git a/src/hotspot/cpu/aarch64/aarch64.ad b/src/hotspot/cpu/aarch64/aarch64.ad -index 64985e498..fa434df7d 100644 ---- a/src/hotspot/cpu/aarch64/aarch64.ad -+++ b/src/hotspot/cpu/aarch64/aarch64.ad -@@ -1991,6 +1991,10 @@ void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { - // branch if we need to invalidate the method later - __ nop(); - -+ if (UseSVE > 0 && C->max_vector_size() >= 16) { -+ __ reinitialize_ptrue(); -+ } -+ - int bangsize = C->bang_size_in_bytes(); - if (C->need_stack_bang(bangsize) && UseStackBanging) - __ generate_stack_overflow_check(bangsize); -@@ -2157,8 +2161,28 @@ uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, boo - - if (bottom_type()->isa_vect() != NULL) { - uint ireg = ideal_reg(); -- assert(ireg == Op_VecD || ireg == Op_VecX, "must be 64 bit or 128 bit vector"); -- if (cbuf) { -+ if (ireg == Op_VecA && cbuf) { -+ MacroAssembler _masm(cbuf); -+ int sve_vector_reg_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE); -+ if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) { -+ // stack->stack -+ __ spill_copy_sve_vector_stack_to_stack(src_offset, dst_offset, -+ sve_vector_reg_size_in_bytes); -+ } else if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) { -+ __ spill_sve_vector(as_FloatRegister(Matcher::_regEncode[src_lo]), ra_->reg2offset(dst_lo), -+ sve_vector_reg_size_in_bytes); -+ } else if (src_lo_rc == rc_stack && dst_lo_rc == rc_float) { -+ __ unspill_sve_vector(as_FloatRegister(Matcher::_regEncode[dst_lo]), ra_->reg2offset(src_lo), -+ sve_vector_reg_size_in_bytes); -+ } else if (src_lo_rc == rc_float && dst_lo_rc == rc_float) { -+ __ sve_orr(as_FloatRegister(Matcher::_regEncode[dst_lo]), -+ as_FloatRegister(Matcher::_regEncode[src_lo]), -+ as_FloatRegister(Matcher::_regEncode[src_lo])); -+ } else { -+ ShouldNotReachHere(); -+ } -+ } else if (cbuf) { -+ assert(ireg == Op_VecD || ireg == Op_VecX, "must be 64 bit or 128 bit vector"); - MacroAssembler _masm(cbuf); - assert((src_lo_rc != rc_int && dst_lo_rc != rc_int), "sanity"); - if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) { -@@ -2442,15 +2466,28 @@ const bool Matcher::match_rule_supported(int opcode) { - return true; // Per default match rules are supported. - } - --const bool Matcher::match_rule_supported_vector(int opcode, int vlen) { -- -- // TODO -- // identify extra cases that we might want to provide match rules for -- // e.g. Op_ vector nodes and other intrinsics while guarding with vlen -- bool ret_value = match_rule_supported(opcode); -- // Add rules here. -- -- return ret_value; // Per default match rules are supported. -+ // Identify extra cases that we might want to provide match rules for vector nodes and -+ // other intrinsics guarded with vector length (vlen) and element type (bt). -+ const bool Matcher::match_rule_supported_vector(int opcode, int vlen, BasicType bt) { -+ if (!match_rule_supported(opcode) || !vector_size_supported(bt, vlen)) { -+ return false; -+ } -+ int bit_size = vlen * type2aelembytes(bt) * 8; -+ if (UseSVE == 0 && bit_size > 128) { -+ return false; -+ } -+ if (UseSVE > 0) { -+ return op_sve_supported(opcode); -+ } else { // NEON -+ // Special cases -+ switch (opcode) { -+ case Op_MulVL: -+ return false; -+ default: -+ break; -+ } -+ } -+ return true; // Per default match rules are supported. - } - - const bool Matcher::has_predicated_vectors(void) { -@@ -3691,6 +3728,11 @@ encode %{ - if (call == NULL) { - ciEnv::current()->record_failure("CodeCache is full"); - return; -+ } else if (UseSVE > 0 && Compile::current()->max_vector_size() >= 16) { -+ // Only non uncommon_trap calls need to reinitialize ptrue. -+ if (uncommon_trap_request() == 0) { -+ __ reinitialize_ptrue(); -+ } - } - // Emit stub for static call - address stub = CompiledStaticCall::emit_to_interp_stub(cbuf); -@@ -3708,6 +3750,8 @@ encode %{ - if (call == NULL) { - ciEnv::current()->record_failure("CodeCache is full"); - return; -+ } else if (UseSVE > 0 && Compile::current()->max_vector_size() >= 16) { -+ __ reinitialize_ptrue(); - } - %} - -@@ -3744,6 +3788,9 @@ encode %{ - __ bind(retaddr); - __ add(sp, sp, 2 * wordSize); - } -+ if (UseSVE > 0 && Compile::current()->max_vector_size() >= 16) { -+ __ reinitialize_ptrue(); -+ } - %} - - enc_class aarch64_enc_rethrow() %{ -@@ -3753,6 +3800,11 @@ encode %{ - - enc_class aarch64_enc_ret() %{ - MacroAssembler _masm(&cbuf); -+#ifdef ASSERT -+ if (UseSVE > 0 && Compile::current()->max_vector_size() >= 16) { -+ __ verify_ptrue(); -+ } -+#endif - __ ret(lr); - %} - -@@ -4494,6 +4546,41 @@ operand immLoffset16() - interface(CONST_INTER); - %} - -+// 8 bit signed value. -+operand immI8() -+%{ -+ predicate(n->get_int() <= 127 && n->get_int() >= -128); -+ match(ConI); +diff --git a/src/hotspot/cpu/aarch64/aarch64-asmtest.py b/src/hotspot/cpu/aarch64/aarch64-asmtest.py +index 31c6965..e621402 100644 +--- a/src/hotspot/cpu/aarch64/aarch64-asmtest.py ++++ b/src/hotspot/cpu/aarch64/aarch64-asmtest.py +@@ -73,6 +73,48 @@ class GeneralRegisterOrSp(Register): + return self.astr() + else: + return self.astr("r") ++class SVEVectorRegister(FloatRegister): ++ def __str__(self): ++ return self.astr("z") + -+ op_cost(0); -+ format %{ %} -+ interface(CONST_INTER); -+%} ++class SVEPRegister(Register): ++ def __str__(self): ++ return self.astr("p") + -+// 8 bit signed value (simm8), or #simm8 LSL 8. -+operand immI8_shift8() -+%{ -+ predicate((n->get_int() <= 127 && n->get_int() >= -128) || -+ (n->get_int() <= 32512 && n->get_int() >= -32768 && (n->get_int() & 0xff) == 0)); -+ match(ConI); ++ def generate(self): ++ self.number = random.randint(0, 15) ++ return self + -+ op_cost(0); -+ format %{ %} -+ interface(CONST_INTER); -+%} ++class SVEGoverningPRegister(Register): ++ def __str__(self): ++ return self.astr("p") ++ def generate(self): ++ self.number = random.randint(0, 7) ++ return self + -+// 8 bit signed value (simm8), or #simm8 LSL 8. -+operand immL8_shift8() -+%{ -+ predicate((n->get_long() <= 127 && n->get_long() >= -128) || -+ (n->get_long() <= 32512 && n->get_long() >= -32768 && (n->get_long() & 0xff) == 0)); -+ match(ConL); ++class RegVariant(object): ++ def __init__(self, low, high): ++ self.number = random.randint(low, high) + -+ op_cost(0); -+ format %{ %} -+ interface(CONST_INTER); -+%} ++ def astr(self): ++ nameMap = { ++ 0: ".b", ++ 1: ".h", ++ 2: ".s", ++ 3: ".d", ++ 4: ".q" ++ } ++ return nameMap.get(self.number) + - // 32 bit integer valid for add sub immediate - operand immIAddSub() - %{ -@@ -16038,7 +16125,7 @@ instruct loadV8(vecD dst, vmem8 mem) - // Load Vector (128 bits) - instruct loadV16(vecX dst, vmem16 mem) - %{ -- predicate(n->as_LoadVector()->memory_size() == 16); -+ predicate(UseSVE == 0 && n->as_LoadVector()->memory_size() == 16); - match(Set dst (LoadVector mem)); - ins_cost(4 * INSN_COST); - format %{ "ldrq $dst,$mem\t# vector (128 bits)" %} -@@ -16094,7 +16181,7 @@ instruct replicate8B(vecD dst, iRegIorL2I src) - - instruct replicate16B(vecX dst, iRegIorL2I src) - %{ -- predicate(n->as_Vector()->length() == 16); -+ predicate(UseSVE == 0 && n->as_Vector()->length() == 16); - match(Set dst (ReplicateB src)); - ins_cost(INSN_COST); - format %{ "dup $dst, $src\t# vector (16B)" %} -@@ -16119,7 +16206,7 @@ instruct replicate8B_imm(vecD dst, immI con) - - instruct replicate16B_imm(vecX dst, immI con) - %{ -- predicate(n->as_Vector()->length() == 16); -+ predicate(UseSVE == 0 && n->as_Vector()->length() == 16); - match(Set dst (ReplicateB con)); - ins_cost(INSN_COST); - format %{ "movi $dst, $con\t# vector(16B)" %} -@@ -16144,7 +16231,7 @@ instruct replicate4S(vecD dst, iRegIorL2I src) ++ def cstr(self): ++ nameMap = { ++ 0: "__ B", ++ 1: "__ H", ++ 2: "__ S", ++ 3: "__ D", ++ 4: "__ Q" ++ } ++ return nameMap.get(self.number) - instruct replicate8S(vecX dst, iRegIorL2I src) - %{ -- predicate(n->as_Vector()->length() == 8); -+ predicate(UseSVE == 0 && n->as_Vector()->length() == 8); - match(Set dst (ReplicateS src)); - ins_cost(INSN_COST); - format %{ "dup $dst, $src\t# vector (8S)" %} -@@ -16169,7 +16256,7 @@ instruct replicate4S_imm(vecD dst, immI con) + class FloatZero(Operand): - instruct replicate8S_imm(vecX dst, immI con) - %{ -- predicate(n->as_Vector()->length() == 8); -+ predicate(UseSVE == 0 && n->as_Vector()->length() == 8); - match(Set dst (ReplicateS con)); - ins_cost(INSN_COST); - format %{ "movi $dst, $con\t# vector(8H)" %} -@@ -16193,7 +16280,7 @@ instruct replicate2I(vecD dst, iRegIorL2I src) +@@ -88,7 +130,10 @@ class OperandFactory: + 'w' : GeneralRegister, + 's' : FloatRegister, + 'd' : FloatRegister, +- 'z' : FloatZero} ++ 'z' : FloatZero, ++ 'p' : SVEPRegister, ++ 'P' : SVEGoverningPRegister, ++ 'Z' : SVEVectorRegister} - instruct replicate4I(vecX dst, iRegIorL2I src) - %{ -- predicate(n->as_Vector()->length() == 4); -+ predicate(UseSVE == 0 && n->as_Vector()->length() == 4); - match(Set dst (ReplicateI src)); - ins_cost(INSN_COST); - format %{ "dup $dst, $src\t# vector (4I)" %} -@@ -16217,7 +16304,7 @@ instruct replicate2I_imm(vecD dst, immI con) + @classmethod + def create(cls, mode): +@@ -834,6 +879,100 @@ class FloatInstruction(Instruction): + % tuple([Instruction.astr(self)] + + [(self.reg[i].astr(self.modes[i])) for i in range(self.numRegs)])) - instruct replicate4I_imm(vecX dst, immI con) - %{ -- predicate(n->as_Vector()->length() == 4); -+ predicate(UseSVE == 0 && n->as_Vector()->length() == 4); - match(Set dst (ReplicateI con)); - ins_cost(INSN_COST); - format %{ "movi $dst, $con\t# vector(4I)" %} -@@ -16229,7 +16316,7 @@ instruct replicate4I_imm(vecX dst, immI con) - - instruct replicate2L(vecX dst, iRegL src) - %{ -- predicate(n->as_Vector()->length() == 2); -+ predicate(UseSVE == 0 && n->as_Vector()->length() == 2); - match(Set dst (ReplicateL src)); - ins_cost(INSN_COST); - format %{ "dup $dst, $src\t# vector (2L)" %} -@@ -16241,7 +16328,7 @@ instruct replicate2L(vecX dst, iRegL src) - - instruct replicate2L_zero(vecX dst, immI0 zero) - %{ -- predicate(n->as_Vector()->length() == 2); -+ predicate(UseSVE == 0 && n->as_Vector()->length() == 2); - match(Set dst (ReplicateI zero)); - ins_cost(INSN_COST); - format %{ "movi $dst, $zero\t# vector(4I)" %} -@@ -16268,7 +16355,7 @@ instruct replicate2F(vecD dst, vRegF src) - - instruct replicate4F(vecX dst, vRegF src) - %{ -- predicate(n->as_Vector()->length() == 4); -+ predicate(UseSVE == 0 && n->as_Vector()->length() == 4); - match(Set dst (ReplicateF src)); - ins_cost(INSN_COST); - format %{ "dup $dst, $src\t# vector (4F)" %} -@@ -16281,7 +16368,7 @@ instruct replicate4F(vecX dst, vRegF src) - - instruct replicate2D(vecX dst, vRegD src) - %{ -- predicate(n->as_Vector()->length() == 2); -+ predicate(UseSVE == 0 && n->as_Vector()->length() == 2); - match(Set dst (ReplicateD src)); - ins_cost(INSN_COST); - format %{ "dup $dst, $src\t# vector (2D)" %} -diff --git a/src/hotspot/cpu/aarch64/aarch64_sve.ad b/src/hotspot/cpu/aarch64/aarch64_sve.ad -new file mode 100644 -index 000000000..8d80cb37a ---- /dev/null -+++ b/src/hotspot/cpu/aarch64/aarch64_sve.ad -@@ -0,0 +1,1366 @@ -+// -+// Copyright (c) 2020, Oracle and/or its affiliates. All rights reserved. -+// Copyright (c) 2020, Arm Limited. All rights reserved. -+// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+// -+// This code is free software; you can redistribute it and/or modify it -+// under the terms of the GNU General Public License version 2 only, as -+// published by the Free Software Foundation. -+// -+// This code is distributed in the hope that it will be useful, but WITHOUT -+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+// version 2 for more details (a copy is included in the LICENSE file that -+// accompanied this code). -+// -+// You should have received a copy of the GNU General Public License version -+// 2 along with this work; if not, write to the Free Software Foundation, -+// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+// -+// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+// or visit www.oracle.com if you need additional information or have any -+// questions. -+// -+// ++class SVEVectorOp(Instruction): ++ def __init__(self, args): ++ name = args[0] ++ regTypes = args[1] ++ regs = [] ++ for c in regTypes: ++ regs.append(OperandFactory.create(c).generate()) ++ self.reg = regs ++ self.numRegs = len(regs) ++ if regTypes[0] != "p" and regTypes[1] == 'P': ++ self._isPredicated = True ++ self._merge = "/m" ++ else: ++ self._isPredicated = False ++ self._merge ="" + -+// This file is automatically generated by running "m4 aarch64_sve_ad.m4". Do not edit ---- ++ self._bitwiseop = False ++ if name[0] == 'f': ++ self._width = RegVariant(2, 3) ++ elif not self._isPredicated and (name in ["and", "eor", "orr", "bic"]): ++ self._width = RegVariant(3, 3) ++ self._bitwiseop = True ++ else: ++ self._width = RegVariant(0, 3) ++ if len(args) > 2: ++ self._dnm = args[2] ++ else: ++ self._dnm = None ++ Instruction.__init__(self, name) + -+// AArch64 SVE Architecture Description File ++ def cstr(self): ++ formatStr = "%s%s" + ''.join([", %s" for i in range(0, self.numRegs)] + [");"]) ++ if self._bitwiseop: ++ width = [] ++ formatStr = "%s%s" + ''.join([", %s" for i in range(1, self.numRegs)] + [");"]) ++ else: ++ width = [self._width.cstr()] ++ return (formatStr ++ % tuple(["__ sve_" + self._name + "("] + ++ [str(self.reg[0])] + ++ width + ++ [str(self.reg[i]) for i in range(1, self.numRegs)])) ++ def astr(self): ++ formatStr = "%s%s" + ''.join([", %s" for i in range(1, self.numRegs)]) ++ if self._dnm == 'dn': ++ formatStr += ", %s" ++ dnReg = [str(self.reg[0]) + self._width.astr()] ++ else: ++ dnReg = [] + ++ if self._isPredicated: ++ restRegs = [str(self.reg[1]) + self._merge] + dnReg + [str(self.reg[i]) + self._width.astr() for i in range(2, self.numRegs)] ++ else: ++ restRegs = dnReg + [str(self.reg[i]) + self._width.astr() for i in range(1, self.numRegs)] ++ return (formatStr ++ % tuple([Instruction.astr(self)] + ++ [str(self.reg[0]) + self._width.astr()] + ++ restRegs)) ++ def generate(self): ++ return self + -+// 4 bit signed offset -- for predicated load/store ++class SVEReductionOp(Instruction): ++ def __init__(self, args): ++ name = args[0] ++ lowRegType = args[1] ++ self.reg = [] ++ Instruction.__init__(self, name) ++ self.reg.append(OperandFactory.create('s').generate()) ++ self.reg.append(OperandFactory.create('P').generate()) ++ self.reg.append(OperandFactory.create('Z').generate()) ++ self._width = RegVariant(lowRegType, 3) ++ def cstr(self): ++ return "__ sve_%s(%s, %s, %s, %s);" % (self.name(), ++ str(self.reg[0]), ++ self._width.cstr(), ++ str(self.reg[1]), ++ str(self.reg[2])) ++ def astr(self): ++ if self.name() == "uaddv": ++ dstRegName = "d" + str(self.reg[0].number) ++ else: ++ dstRegName = self._width.astr()[1] + str(self.reg[0].number) ++ formatStr = "%s %s, %s, %s" ++ if self.name() == "fadda": ++ formatStr += ", %s" ++ moreReg = [dstRegName] ++ else: ++ moreReg = [] ++ return formatStr % tuple([self.name()] + ++ [dstRegName] + ++ [str(self.reg[1])] + ++ moreReg + ++ [str(self.reg[2]) + self._width.astr()]) + -+operand vmemA_immIOffset4() -+%{ -+ predicate(Address::offset_ok_for_sve_immed(n->get_int(), 4, -+ Matcher::scalable_vector_reg_size(T_BYTE))); -+ match(ConI); + class LdStSIMDOp(Instruction): + def __init__(self, args): + self._name, self.regnum, self.arrangement, self.addresskind = args +@@ -1120,7 +1259,42 @@ generate(SpecialCases, [["ccmn", "__ ccmn(zr, zr, 3u, Assembler::LE);", + ["mov", "__ mov(v1, __ T2S, 1, zr);", "mov\tv1.s[1], wzr"], + ["mov", "__ mov(v1, __ T4H, 2, zr);", "mov\tv1.h[2], wzr"], + ["mov", "__ mov(v1, __ T8B, 3, zr);", "mov\tv1.b[3], wzr"], +- ["ld1", "__ ld1(v31, v0, __ T2D, Address(__ post(r1, r0)));", "ld1\t{v31.2d, v0.2d}, [x1], x0"]]) ++ ["ld1", "__ ld1(v31, v0, __ T2D, Address(__ post(r1, r0)));", "ld1\t{v31.2d, v0.2d}, [x1], x0"], ++ # SVE instructions ++ ["cpy", "__ sve_cpy(z0, __ S, p0, v1);", "mov\tz0.s, p0/m, s1"], ++ ["inc", "__ sve_inc(r0, __ S);", "incw\tx0"], ++ ["dec", "__ sve_dec(r1, __ H);", "dech\tx1"], ++ ["lsl", "__ sve_lsl(z0, __ B, z1, 7);", "lsl\tz0.b, z1.b, #7"], ++ ["lsl", "__ sve_lsl(z21, __ H, z1, 15);", "lsl\tz21.h, z1.h, #15"], ++ ["lsl", "__ sve_lsl(z0, __ S, z1, 31);", "lsl\tz0.s, z1.s, #31"], ++ ["lsl", "__ sve_lsl(z0, __ D, z1, 63);", "lsl\tz0.d, z1.d, #63"], ++ ["lsr", "__ sve_lsr(z0, __ B, z1, 7);", "lsr\tz0.b, z1.b, #7"], ++ ["asr", "__ sve_asr(z0, __ H, z11, 15);", "asr\tz0.h, z11.h, #15"], ++ ["lsr", "__ sve_lsr(z30, __ S, z1, 31);", "lsr\tz30.s, z1.s, #31"], ++ ["asr", "__ sve_asr(z0, __ D, z1, 63);", "asr\tz0.d, z1.d, #63"], ++ ["addvl", "__ sve_addvl(sp, r0, 31);", "addvl\tsp, x0, #31"], ++ ["addpl", "__ sve_addpl(r1, sp, -32);", "addpl\tx1, sp, -32"], ++ ["cntp", "__ sve_cntp(r8, __ B, p0, p1);", "cntp\tx8, p0, p1.b"], ++ ["dup", "__ sve_dup(z0, __ B, 127);", "dup\tz0.b, 127"], ++ ["dup", "__ sve_dup(z1, __ H, -128);", "dup\tz1.h, -128"], ++ ["dup", "__ sve_dup(z2, __ S, 32512);", "dup\tz2.s, 32512"], ++ ["dup", "__ sve_dup(z7, __ D, -32768);", "dup\tz7.d, -32768"], ++ ["ld1b", "__ sve_ld1b(z0, __ B, p0, Address(sp));", "ld1b\t{z0.b}, p0/z, [sp]"], ++ ["ld1h", "__ sve_ld1h(z10, __ H, p1, Address(sp, -8));", "ld1h\t{z10.h}, p1/z, [sp, #-8, MUL VL]"], ++ ["ld1w", "__ sve_ld1w(z20, __ S, p2, Address(r0, 7));", "ld1w\t{z20.s}, p2/z, [x0, #7, MUL VL]"], ++ ["ld1b", "__ sve_ld1b(z30, __ B, p3, Address(sp, r8));", "ld1b\t{z30.b}, p3/z, [sp, x8]"], ++ ["ld1w", "__ sve_ld1w(z0, __ S, p4, Address(sp, r28));", "ld1w\t{z0.s}, p4/z, [sp, x28, LSL #2]"], ++ ["ld1d", "__ sve_ld1d(z11, __ D, p5, Address(r0, r1));", "ld1d\t{z11.d}, p5/z, [x0, x1, LSL #3]"], ++ ["st1b", "__ sve_st1b(z22, __ B, p6, Address(sp));", "st1b\t{z22.b}, p6, [sp]"], ++ ["st1b", "__ sve_st1b(z31, __ B, p7, Address(sp, -8));", "st1b\t{z31.b}, p7, [sp, #-8, MUL VL]"], ++ ["st1w", "__ sve_st1w(z0, __ S, p1, Address(r0, 7));", "st1w\t{z0.s}, p1, [x0, #7, MUL VL]"], ++ ["st1b", "__ sve_st1b(z0, __ B, p2, Address(sp, r1));", "st1b\t{z0.b}, p2, [sp, x1]"], ++ ["st1h", "__ sve_st1h(z0, __ H, p3, Address(sp, r8));", "st1h\t{z0.h}, p3, [sp, x8, LSL #1]"], ++ ["st1d", "__ sve_st1d(z0, __ D, p4, Address(r0, r8));", "st1d\t{z0.d}, p4, [x0, x8, LSL #3]"], ++ ["ldr", "__ sve_ldr(z0, Address(sp));", "ldr\tz0, [sp]"], ++ ["ldr", "__ sve_ldr(z31, Address(sp, -256));", "ldr\tz31, [sp, #-256, MUL VL]"], ++ ["str", "__ sve_str(z8, Address(r8, 255));", "str\tz8, [x8, #255, MUL VL]"], ++]) + + print "\n// FloatImmediateOp" + for float in ("2.0", "2.125", "4.0", "4.25", "8.0", "8.5", "16.0", "17.0", "0.125", +@@ -1145,6 +1319,50 @@ for size in ("x", "w"): + ["ldumin", "ldumin", size, suffix], + ["ldumax", "ldumax", size, suffix]]); + + -+ op_cost(0); -+ format %{ %} -+ interface(CONST_INTER); -+%} ++generate(SVEVectorOp, [["add", "ZZZ"], ++ ["sub", "ZZZ"], ++ ["fadd", "ZZZ"], ++ ["fmul", "ZZZ"], ++ ["fsub", "ZZZ"], ++ ["abs", "ZPZ"], ++ ["add", "ZPZ", "dn"], ++ ["asr", "ZPZ", "dn"], ++ ["cnt", "ZPZ"], ++ ["lsl", "ZPZ", "dn"], ++ ["lsr", "ZPZ", "dn"], ++ ["mul", "ZPZ", "dn"], ++ ["neg", "ZPZ"], ++ ["not", "ZPZ"], ++ ["smax", "ZPZ", "dn"], ++ ["smin", "ZPZ", "dn"], ++ ["sub", "ZPZ", "dn"], ++ ["fabs", "ZPZ"], ++ ["fadd", "ZPZ", "dn"], ++ ["fdiv", "ZPZ", "dn"], ++ ["fmax", "ZPZ", "dn"], ++ ["fmin", "ZPZ", "dn"], ++ ["fmul", "ZPZ", "dn"], ++ ["fneg", "ZPZ"], ++ ["frintm", "ZPZ"], ++ ["frintn", "ZPZ"], ++ ["frintp", "ZPZ"], ++ ["fsqrt", "ZPZ"], ++ ["fsub", "ZPZ", "dn"], ++ ["fmla", "ZPZZ"], ++ ["fmls", "ZPZZ"], ++ ["fnmla", "ZPZZ"], ++ ["fnmls", "ZPZZ"], ++ ["mla", "ZPZZ"], ++ ["mls", "ZPZZ"], ++ ["and", "ZZZ"], ++ ["eor", "ZZZ"], ++ ["orr", "ZZZ"], ++ ]) + -+operand vmemA_immLOffset4() ++generate(SVEReductionOp, [["andv", 0], ["orv", 0], ["eorv", 0], ["smaxv", 0], ["sminv", 0], ++ ["fminv", 2], ["fmaxv", 2], ["fadda", 2], ["uaddv", 0]]) ++ + print "\n __ bind(forth);" + outfile.write("forth:\n") + +@@ -1153,8 +1371,8 @@ outfile.close() + import subprocess + import sys + +-# compile for 8.1 because of lse atomics +-subprocess.check_call([AARCH64_AS, "-march=armv8.1-a", "aarch64ops.s", "-o", "aarch64ops.o"]) ++# compile for sve with 8.1 and sha2 because of lse atomics and sha512 crypto extension. ++subprocess.check_call([AARCH64_AS, "-march=armv8.1-a+sha2+sve", "aarch64ops.s", "-o", "aarch64ops.o"]) + + print + print "/*", +diff --git a/src/hotspot/cpu/aarch64/aarch64.ad b/src/hotspot/cpu/aarch64/aarch64.ad +index f126488..8a92ff2 100644 +--- a/src/hotspot/cpu/aarch64/aarch64.ad ++++ b/src/hotspot/cpu/aarch64/aarch64.ad +@@ -2006,6 +2006,10 @@ void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { + // branch if we need to invalidate the method later + __ nop(); + ++ if (UseSVE > 0 && C->max_vector_size() >= 16) { ++ __ reinitialize_ptrue(); ++ } ++ + int bangsize = C->bang_size_in_bytes(); + if (C->need_stack_bang(bangsize) && UseStackBanging) + __ generate_stack_overflow_check(bangsize); +@@ -2172,8 +2176,28 @@ uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, boo + + if (bottom_type()->isa_vect() != NULL) { + uint ireg = ideal_reg(); +- assert(ireg == Op_VecD || ireg == Op_VecX, "must be 64 bit or 128 bit vector"); +- if (cbuf) { ++ if (ireg == Op_VecA && cbuf) { ++ MacroAssembler _masm(cbuf); ++ int sve_vector_reg_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE); ++ if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) { ++ // stack->stack ++ __ spill_copy_sve_vector_stack_to_stack(src_offset, dst_offset, ++ sve_vector_reg_size_in_bytes); ++ } else if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) { ++ __ spill_sve_vector(as_FloatRegister(Matcher::_regEncode[src_lo]), ra_->reg2offset(dst_lo), ++ sve_vector_reg_size_in_bytes); ++ } else if (src_lo_rc == rc_stack && dst_lo_rc == rc_float) { ++ __ unspill_sve_vector(as_FloatRegister(Matcher::_regEncode[dst_lo]), ra_->reg2offset(src_lo), ++ sve_vector_reg_size_in_bytes); ++ } else if (src_lo_rc == rc_float && dst_lo_rc == rc_float) { ++ __ sve_orr(as_FloatRegister(Matcher::_regEncode[dst_lo]), ++ as_FloatRegister(Matcher::_regEncode[src_lo]), ++ as_FloatRegister(Matcher::_regEncode[src_lo])); ++ } else { ++ ShouldNotReachHere(); ++ } ++ } else if (cbuf) { ++ assert(ireg == Op_VecD || ireg == Op_VecX, "must be 64 bit or 128 bit vector"); + MacroAssembler _masm(cbuf); + assert((src_lo_rc != rc_int && dst_lo_rc != rc_int), "sanity"); + if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) { +@@ -2452,15 +2476,28 @@ const bool Matcher::match_rule_supported(int opcode) { + return true; // Per default match rules are supported. + } + +-const bool Matcher::match_rule_supported_vector(int opcode, int vlen) { +- +- // TODO +- // identify extra cases that we might want to provide match rules for +- // e.g. Op_ vector nodes and other intrinsics while guarding with vlen +- bool ret_value = match_rule_supported(opcode); +- // Add rules here. +- +- return ret_value; // Per default match rules are supported. ++ // Identify extra cases that we might want to provide match rules for vector nodes and ++ // other intrinsics guarded with vector length (vlen) and element type (bt). ++ const bool Matcher::match_rule_supported_vector(int opcode, int vlen, BasicType bt) { ++ if (!match_rule_supported(opcode) || !vector_size_supported(bt, vlen)) { ++ return false; ++ } ++ int bit_size = vlen * type2aelembytes(bt) * 8; ++ if (UseSVE == 0 && bit_size > 128) { ++ return false; ++ } ++ if (UseSVE > 0) { ++ return op_sve_supported(opcode); ++ } else { // NEON ++ // Special cases ++ switch (opcode) { ++ case Op_MulVL: ++ return false; ++ default: ++ break; ++ } ++ } ++ return true; // Per default match rules are supported. + } + + const bool Matcher::has_predicated_vectors(void) { +@@ -3812,6 +3849,12 @@ encode %{ + return; + } + } ++ if (UseSVE > 0 && Compile::current()->max_vector_size() >= 16) { ++ // Only non uncommon_trap calls need to reinitialize ptrue. ++ if (uncommon_trap_request() == 0) { ++ __ reinitialize_ptrue(); ++ } ++ } + %} + + enc_class aarch64_enc_java_dynamic_call(method meth) %{ +@@ -3821,6 +3864,8 @@ encode %{ + if (call == NULL) { + ciEnv::current()->record_failure("CodeCache is full"); + return; ++ } else if (UseSVE > 0 && Compile::current()->max_vector_size() >= 16) { ++ __ reinitialize_ptrue(); + } + %} + +@@ -3857,6 +3902,9 @@ encode %{ + __ bind(retaddr); + __ add(sp, sp, 2 * wordSize); + } ++ if (UseSVE > 0 && Compile::current()->max_vector_size() >= 16) { ++ __ reinitialize_ptrue(); ++ } + %} + + enc_class aarch64_enc_rethrow() %{ +@@ -3866,6 +3914,11 @@ encode %{ + + enc_class aarch64_enc_ret() %{ + MacroAssembler _masm(&cbuf); ++#ifdef ASSERT ++ if (UseSVE > 0 && Compile::current()->max_vector_size() >= 16) { ++ __ verify_ptrue(); ++ } ++#endif + __ ret(lr); + %} + +@@ -4607,6 +4660,41 @@ operand immLoffset16() + interface(CONST_INTER); + %} + ++// 8 bit signed value. ++operand immI8() +%{ -+ predicate(Address::offset_ok_for_sve_immed(n->get_long(), 4, -+ Matcher::scalable_vector_reg_size(T_BYTE))); -+ match(ConL); ++ predicate(n->get_int() <= 127 && n->get_int() >= -128); ++ match(ConI); + + op_cost(0); + format %{ %} + interface(CONST_INTER); +%} + -+ -+operand vmemA_indOffI4(iRegP reg, vmemA_immIOffset4 off) ++// 8 bit signed value (simm8), or #simm8 LSL 8. ++operand immI8_shift8() +%{ -+ constraint(ALLOC_IN_RC(ptr_reg)); -+ match(AddP reg off); -+ op_cost(0); -+ format %{ "[$reg, $off, MUL VL]" %} -+ interface(MEMORY_INTER) %{ -+ base($reg); -+ index(0xffffffff); -+ scale(0x0); -+ disp($off); -+ %} -+%} ++ predicate((n->get_int() <= 127 && n->get_int() >= -128) || ++ (n->get_int() <= 32512 && n->get_int() >= -32768 && (n->get_int() & 0xff) == 0)); ++ match(ConI); + -+operand vmemA_indOffL4(iRegP reg, vmemA_immLOffset4 off) -+%{ -+ constraint(ALLOC_IN_RC(ptr_reg)); -+ match(AddP reg off); + op_cost(0); -+ format %{ "[$reg, $off, MUL VL]" %} -+ interface(MEMORY_INTER) %{ -+ base($reg); -+ index(0xffffffff); -+ scale(0x0); -+ disp($off); -+ %} ++ format %{ %} ++ interface(CONST_INTER); +%} + -+opclass vmemA(indirect, vmemA_indOffI4, vmemA_indOffL4); ++// 8 bit signed value (simm8), or #simm8 LSL 8. ++operand immL8_shift8() ++%{ ++ predicate((n->get_long() <= 127 && n->get_long() >= -128) || ++ (n->get_long() <= 32512 && n->get_long() >= -32768 && (n->get_long() & 0xff) == 0)); ++ match(ConL); + -+source_hpp %{ -+ bool op_sve_supported(int opcode); ++ op_cost(0); ++ format %{ %} ++ interface(CONST_INTER); +%} + -+source %{ -+ -+ static inline BasicType vector_element_basic_type(const MachNode* n) { -+ const TypeVect* vt = n->bottom_type()->is_vect(); -+ return vt->element_basic_type(); -+ } -+ -+ static inline BasicType vector_element_basic_type(const MachNode* use, const MachOper* opnd) { -+ int def_idx = use->operand_index(opnd); -+ Node* def = use->in(def_idx); -+ const TypeVect* vt = def->bottom_type()->is_vect(); -+ return vt->element_basic_type(); -+ } -+ -+ typedef void (MacroAssembler::* sve_mem_insn_predicate)(FloatRegister Rt, Assembler::SIMD_RegVariant T, -+ PRegister Pg, const Address &adr); -+ -+ // Predicated load/store, with optional ptrue to all elements of given predicate register. -+ static void loadStoreA_predicate(MacroAssembler masm, bool is_store, -+ FloatRegister reg, PRegister pg, BasicType bt, -+ int opcode, Register base, int index, int size, int disp) { -+ sve_mem_insn_predicate insn = NULL; -+ Assembler::SIMD_RegVariant type = Assembler::B; -+ int esize = type2aelembytes(bt); -+ if (index == -1) { -+ assert(size == 0, "unsupported address mode: scale size = %d", size); -+ switch(esize) { -+ case 1: -+ insn = is_store ? &MacroAssembler::sve_st1b : &MacroAssembler::sve_ld1b; -+ type = Assembler::B; -+ break; -+ case 2: -+ insn = is_store ? &MacroAssembler::sve_st1h : &MacroAssembler::sve_ld1h; -+ type = Assembler::H; -+ break; -+ case 4: -+ insn = is_store ? &MacroAssembler::sve_st1w : &MacroAssembler::sve_ld1w; -+ type = Assembler::S; -+ break; -+ case 8: -+ insn = is_store ? &MacroAssembler::sve_st1d : &MacroAssembler::sve_ld1d; -+ type = Assembler::D; -+ break; -+ default: -+ assert(false, "unsupported"); -+ ShouldNotReachHere(); -+ } -+ (masm.*insn)(reg, type, pg, Address(base, disp / Matcher::scalable_vector_reg_size(T_BYTE))); -+ } else { -+ assert(false, "unimplemented"); -+ ShouldNotReachHere(); -+ } -+ } -+ -+ bool op_sve_supported(int opcode) { -+ switch (opcode) { -+ // No multiply reduction instructions -+ case Op_MulReductionVD: -+ case Op_MulReductionVF: -+ case Op_MulReductionVI: -+ case Op_MulReductionVL: -+ // Others -+ case Op_Extract: -+ case Op_ExtractB: -+ case Op_ExtractC: -+ case Op_ExtractD: -+ case Op_ExtractF: + // 32 bit integer valid for add sub immediate + operand immIAddSub() + %{ +@@ -16433,7 +16521,7 @@ instruct loadV8(vecD dst, vmem8 mem) + // Load Vector (128 bits) + instruct loadV16(vecX dst, vmem16 mem) + %{ +- predicate(n->as_LoadVector()->memory_size() == 16); ++ predicate(UseSVE == 0 && n->as_LoadVector()->memory_size() == 16); + match(Set dst (LoadVector mem)); + ins_cost(4 * INSN_COST); + format %{ "ldrq $dst,$mem\t# vector (128 bits)" %} +@@ -16489,7 +16577,7 @@ instruct replicate8B(vecD dst, iRegIorL2I src) + + instruct replicate16B(vecX dst, iRegIorL2I src) + %{ +- predicate(n->as_Vector()->length() == 16); ++ predicate(UseSVE == 0 && n->as_Vector()->length() == 16); + match(Set dst (ReplicateB src)); + ins_cost(INSN_COST); + format %{ "dup $dst, $src\t# vector (16B)" %} +@@ -16514,7 +16602,7 @@ instruct replicate8B_imm(vecD dst, immI con) + + instruct replicate16B_imm(vecX dst, immI con) + %{ +- predicate(n->as_Vector()->length() == 16); ++ predicate(UseSVE == 0 && n->as_Vector()->length() == 16); + match(Set dst (ReplicateB con)); + ins_cost(INSN_COST); + format %{ "movi $dst, $con\t# vector(16B)" %} +@@ -16539,7 +16627,7 @@ instruct replicate4S(vecD dst, iRegIorL2I src) + + instruct replicate8S(vecX dst, iRegIorL2I src) + %{ +- predicate(n->as_Vector()->length() == 8); ++ predicate(UseSVE == 0 && n->as_Vector()->length() == 8); + match(Set dst (ReplicateS src)); + ins_cost(INSN_COST); + format %{ "dup $dst, $src\t# vector (8S)" %} +@@ -16564,7 +16652,7 @@ instruct replicate4S_imm(vecD dst, immI con) + + instruct replicate8S_imm(vecX dst, immI con) + %{ +- predicate(n->as_Vector()->length() == 8); ++ predicate(UseSVE == 0 && n->as_Vector()->length() == 8); + match(Set dst (ReplicateS con)); + ins_cost(INSN_COST); + format %{ "movi $dst, $con\t# vector(8H)" %} +@@ -16588,7 +16676,7 @@ instruct replicate2I(vecD dst, iRegIorL2I src) + + instruct replicate4I(vecX dst, iRegIorL2I src) + %{ +- predicate(n->as_Vector()->length() == 4); ++ predicate(UseSVE == 0 && n->as_Vector()->length() == 4); + match(Set dst (ReplicateI src)); + ins_cost(INSN_COST); + format %{ "dup $dst, $src\t# vector (4I)" %} +@@ -16612,7 +16700,7 @@ instruct replicate2I_imm(vecD dst, immI con) + + instruct replicate4I_imm(vecX dst, immI con) + %{ +- predicate(n->as_Vector()->length() == 4); ++ predicate(UseSVE == 0 && n->as_Vector()->length() == 4); + match(Set dst (ReplicateI con)); + ins_cost(INSN_COST); + format %{ "movi $dst, $con\t# vector(4I)" %} +@@ -16624,7 +16712,7 @@ instruct replicate4I_imm(vecX dst, immI con) + + instruct replicate2L(vecX dst, iRegL src) + %{ +- predicate(n->as_Vector()->length() == 2); ++ predicate(UseSVE == 0 && n->as_Vector()->length() == 2); + match(Set dst (ReplicateL src)); + ins_cost(INSN_COST); + format %{ "dup $dst, $src\t# vector (2L)" %} +@@ -16636,7 +16724,7 @@ instruct replicate2L(vecX dst, iRegL src) + + instruct replicate2L_zero(vecX dst, immI0 zero) + %{ +- predicate(n->as_Vector()->length() == 2); ++ predicate(UseSVE == 0 && n->as_Vector()->length() == 2); + match(Set dst (ReplicateI zero)); + ins_cost(INSN_COST); + format %{ "movi $dst, $zero\t# vector(4I)" %} +@@ -16663,7 +16751,7 @@ instruct replicate2F(vecD dst, vRegF src) + + instruct replicate4F(vecX dst, vRegF src) + %{ +- predicate(n->as_Vector()->length() == 4); ++ predicate(UseSVE == 0 && n->as_Vector()->length() == 4); + match(Set dst (ReplicateF src)); + ins_cost(INSN_COST); + format %{ "dup $dst, $src\t# vector (4F)" %} +@@ -16676,7 +16764,7 @@ instruct replicate4F(vecX dst, vRegF src) + + instruct replicate2D(vecX dst, vRegD src) + %{ +- predicate(n->as_Vector()->length() == 2); ++ predicate(UseSVE == 0 && n->as_Vector()->length() == 2); + match(Set dst (ReplicateD src)); + ins_cost(INSN_COST); + format %{ "dup $dst, $src\t# vector (2D)" %} +diff --git a/src/hotspot/cpu/aarch64/aarch64_sve.ad b/src/hotspot/cpu/aarch64/aarch64_sve.ad +new file mode 100644 +index 0000000..8d80cb3 +--- /dev/null ++++ b/src/hotspot/cpu/aarch64/aarch64_sve.ad +@@ -0,0 +1,1366 @@ ++// ++// Copyright (c) 2020, Oracle and/or its affiliates. All rights reserved. ++// Copyright (c) 2020, Arm Limited. All rights reserved. ++// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++// ++// This code is free software; you can redistribute it and/or modify it ++// under the terms of the GNU General Public License version 2 only, as ++// published by the Free Software Foundation. ++// ++// This code is distributed in the hope that it will be useful, but WITHOUT ++// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// version 2 for more details (a copy is included in the LICENSE file that ++// accompanied this code). ++// ++// You should have received a copy of the GNU General Public License version ++// 2 along with this work; if not, write to the Free Software Foundation, ++// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++// ++// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++// or visit www.oracle.com if you need additional information or have any ++// questions. ++// ++// ++ ++// This file is automatically generated by running "m4 aarch64_sve_ad.m4". Do not edit ---- ++ ++// AArch64 SVE Architecture Description File ++ ++ ++// 4 bit signed offset -- for predicated load/store ++ ++operand vmemA_immIOffset4() ++%{ ++ predicate(Address::offset_ok_for_sve_immed(n->get_int(), 4, ++ Matcher::scalable_vector_reg_size(T_BYTE))); ++ match(ConI); ++ ++ op_cost(0); ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++operand vmemA_immLOffset4() ++%{ ++ predicate(Address::offset_ok_for_sve_immed(n->get_long(), 4, ++ Matcher::scalable_vector_reg_size(T_BYTE))); ++ match(ConL); ++ ++ op_cost(0); ++ format %{ %} ++ interface(CONST_INTER); ++%} ++ ++ ++operand vmemA_indOffI4(iRegP reg, vmemA_immIOffset4 off) ++%{ ++ constraint(ALLOC_IN_RC(ptr_reg)); ++ match(AddP reg off); ++ op_cost(0); ++ format %{ "[$reg, $off, MUL VL]" %} ++ interface(MEMORY_INTER) %{ ++ base($reg); ++ index(0xffffffff); ++ scale(0x0); ++ disp($off); ++ %} ++%} ++ ++operand vmemA_indOffL4(iRegP reg, vmemA_immLOffset4 off) ++%{ ++ constraint(ALLOC_IN_RC(ptr_reg)); ++ match(AddP reg off); ++ op_cost(0); ++ format %{ "[$reg, $off, MUL VL]" %} ++ interface(MEMORY_INTER) %{ ++ base($reg); ++ index(0xffffffff); ++ scale(0x0); ++ disp($off); ++ %} ++%} ++ ++opclass vmemA(indirect, vmemA_indOffI4, vmemA_indOffL4); ++ ++source_hpp %{ ++ bool op_sve_supported(int opcode); ++%} ++ ++source %{ ++ ++ static inline BasicType vector_element_basic_type(const MachNode* n) { ++ const TypeVect* vt = n->bottom_type()->is_vect(); ++ return vt->element_basic_type(); ++ } ++ ++ static inline BasicType vector_element_basic_type(const MachNode* use, const MachOper* opnd) { ++ int def_idx = use->operand_index(opnd); ++ Node* def = use->in(def_idx); ++ const TypeVect* vt = def->bottom_type()->is_vect(); ++ return vt->element_basic_type(); ++ } ++ ++ typedef void (MacroAssembler::* sve_mem_insn_predicate)(FloatRegister Rt, Assembler::SIMD_RegVariant T, ++ PRegister Pg, const Address &adr); ++ ++ // Predicated load/store, with optional ptrue to all elements of given predicate register. ++ static void loadStoreA_predicate(MacroAssembler masm, bool is_store, ++ FloatRegister reg, PRegister pg, BasicType bt, ++ int opcode, Register base, int index, int size, int disp) { ++ sve_mem_insn_predicate insn = NULL; ++ Assembler::SIMD_RegVariant type = Assembler::B; ++ int esize = type2aelembytes(bt); ++ if (index == -1) { ++ assert(size == 0, "unsupported address mode: scale size = %d", size); ++ switch(esize) { ++ case 1: ++ insn = is_store ? &MacroAssembler::sve_st1b : &MacroAssembler::sve_ld1b; ++ type = Assembler::B; ++ break; ++ case 2: ++ insn = is_store ? &MacroAssembler::sve_st1h : &MacroAssembler::sve_ld1h; ++ type = Assembler::H; ++ break; ++ case 4: ++ insn = is_store ? &MacroAssembler::sve_st1w : &MacroAssembler::sve_ld1w; ++ type = Assembler::S; ++ break; ++ case 8: ++ insn = is_store ? &MacroAssembler::sve_st1d : &MacroAssembler::sve_ld1d; ++ type = Assembler::D; ++ break; ++ default: ++ assert(false, "unsupported"); ++ ShouldNotReachHere(); ++ } ++ (masm.*insn)(reg, type, pg, Address(base, disp / Matcher::scalable_vector_reg_size(T_BYTE))); ++ } else { ++ assert(false, "unimplemented"); ++ ShouldNotReachHere(); ++ } ++ } ++ ++ bool op_sve_supported(int opcode) { ++ switch (opcode) { ++ // No multiply reduction instructions ++ case Op_MulReductionVD: ++ case Op_MulReductionVF: ++ case Op_MulReductionVI: ++ case Op_MulReductionVL: ++ // Others ++ case Op_Extract: ++ case Op_ExtractB: ++ case Op_ExtractC: ++ case Op_ExtractD: ++ case Op_ExtractF: + case Op_ExtractI: + case Op_ExtractL: + case Op_ExtractS: @@ -1657,7 +1930,7 @@ index 000000000..8d80cb37a +%} diff --git a/src/hotspot/cpu/aarch64/aarch64_sve_ad.m4 b/src/hotspot/cpu/aarch64/aarch64_sve_ad.m4 new file mode 100644 -index 000000000..0323f2f8c +index 0000000..0323f2f --- /dev/null +++ b/src/hotspot/cpu/aarch64/aarch64_sve_ad.m4 @@ -0,0 +1,727 @@ @@ -2389,7 +2662,7 @@ index 000000000..0323f2f8c +BINARY_OP_UNPREDICATED(vsubF, SubVF, S, 4, sve_fsub) +BINARY_OP_UNPREDICATED(vsubD, SubVD, D, 2, sve_fsub) diff --git a/src/hotspot/cpu/aarch64/assembler_aarch64.cpp b/src/hotspot/cpu/aarch64/assembler_aarch64.cpp -index 8047ed8fd..32e53336b 100644 +index 8047ed8..32e5333 100644 --- a/src/hotspot/cpu/aarch64/assembler_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/assembler_aarch64.cpp @@ -96,662 +96,746 @@ void entry(CodeBuffer *cb) { @@ -4888,529 +5161,257 @@ index 8047ed8fd..32e53336b 100644 - 0x8811fdfa, 0x885f7dcd, 0x885fff4c, 0x889ffe28, - 0x88dfffd5, 0x48007d6f, 0x4811fc34, 0x485f7d1d, - 0x485ffd91, 0x489ffc8b, 0x48dffc90, 0x080e7c85, -- 0x081bfe11, 0x085f7f66, 0x085fff1b, 0x089ffe8a, -- 0x08dfff49, 0xc87f7b85, 0xc87fa66a, 0xc82b5590, -- 0xc82adc94, 0x887f0416, 0x887f8503, 0x88205fc9, -- 0x8837c560, 0xf81e1146, 0xb81fb007, 0x381f3205, -- 0x7801f27e, 0xf8477130, 0xb843b208, 0x385f918a, -- 0x785da12e, 0x389f83d8, 0x78817087, 0x78dd91d1, -- 0xb89e136b, 0xfc4410ec, 0xbc5fe200, 0xfc15f2ed, -- 0xbc1c2075, 0xf8064ca2, 0xb81a4c29, 0x381fbfdb, -- 0x7800cdfb, 0xf852ce24, 0xb841eef5, 0x385f9e2d, -- 0x785cec19, 0x389ebea1, 0x789caebc, 0x78c02c8b, -- 0xb883dd31, 0xfc427e7d, 0xbc5abed6, 0xfc11ff29, -- 0xbc1f1c49, 0xf81be6ed, 0xb800a611, 0x381e05c1, -- 0x78006411, 0xf855473b, 0xb85da72d, 0x385e372b, -- 0x784144be, 0x389f94e9, 0x789c2460, 0x78c1f5c7, -- 0xb8827771, 0xfc515491, 0xbc4226ba, 0xfc1c7625, -- 0xbc1935ad, 0xf824da06, 0xb834db09, 0x38237ba3, -- 0x783e6a2a, 0xf867497b, 0xb87949ee, 0x387379d8, -- 0x7866c810, 0x38acd98a, 0x78b0499a, 0x78ee781a, -- 0xb8bbf971, 0xfc73d803, 0xbc6979fa, 0xfc30e9ab, -- 0xbc355a7a, 0xf91886a8, 0xb918ef6a, 0x391b15db, -- 0x791ac0f0, 0xf958753b, 0xb95a1958, 0x395b3f18, -- 0x795800b4, 0x39988891, 0x799a81ae, 0x79dd172a, -- 0xb9981342, 0xfd5d21da, 0xbd5e7c9c, 0xfd1b526e, -- 0xbd18df97, 0x58002268, 0x18ffdf51, 0xf8951080, -- 0xd8000000, 0xf8a4c900, 0xf999e180, 0x1a150374, -- 0x3a060227, 0x5a1900c5, 0x7a0e017e, 0x9a0b0223, -- 0xba110159, 0xda170207, 0xfa050144, 0x0b2973c9, -- 0x2b30a8a0, 0xcb3b8baf, 0x6b21f12b, 0x8b264f02, -- 0xab3a70d3, 0xcb39ef48, 0xeb29329a, 0x3a5a41a7, -- 0x7a54310f, 0xba4302c8, 0xfa58a04a, 0x3a50490d, -- 0x7a4c0a01, 0xba5f79e3, 0xfa4c0aef, 0x1a9a30ee, -- 0x1a9ed763, 0x5a9702ab, 0x5a95c7da, 0x9a8d835c, -- 0x9a909471, 0xda8380ab, 0xda93c461, 0x5ac00120, -- 0x5ac005da, 0x5ac00a2d, 0x5ac0128b, 0x5ac0163c, -- 0xdac0008d, 0xdac007c1, 0xdac009cd, 0xdac00d05, -- 0xdac01322, 0xdac01514, 0x1adb0b35, 0x1ad00d4d, -- 0x1ad1203c, 0x1aca26f9, 0x1ac72867, 0x1ace2fce, -- 0x9acf0acc, 0x9acd0f22, 0x9ad522e7, 0x9ac0258b, -- 0x9adc293e, 0x9ad62cad, 0x9bc47ea5, 0x9b477c51, -- 0x1b11318c, 0x1b01edfe, 0x9b117662, 0x9b03fae4, -- 0x9b313eef, 0x9b21b59b, 0x9bac45a6, 0x9ba6a839, -- 0x1e240871, 0x1e3518b0, 0x1e312b63, 0x1e2f3959, -- 0x1e200a2a, 0x1e630b5c, 0x1e7b1804, 0x1e6229dc, -- 0x1e773b4c, 0x1e610bcf, 0x1f0534a4, 0x1f1c85b5, -- 0x1f3d1c71, 0x1f3d6b37, 0x1f5e68ee, 0x1f4aa4f6, -- 0x1f6e24e7, 0x1f6f630e, 0x1e204056, 0x1e20c060, -- 0x1e214229, 0x1e21c178, 0x1e22c32f, 0x1e604064, -- 0x1e60c2da, 0x1e61427e, 0x1e61c1cc, 0x1e6240f1, -- 0x1e3801d8, 0x9e38034d, 0x1e780022, 0x9e780165, -- 0x1e22026e, 0x9e2202c1, 0x1e62023b, 0x9e620136, -- 0x1e26006e, 0x9e66022c, 0x1e270368, 0x9e67039d, -- 0x1e3e2000, 0x1e692180, 0x1e202148, 0x1e602328, -- 0x292e7b68, 0x294a4f15, 0x69626c50, 0xa93814d5, -- 0xa97e679d, 0x29903408, 0x29ec5039, 0x69fc62ce, -- 0xa98504d1, 0xa9fc4735, 0x28b05691, 0x28c8705c, -- 0x68e07953, 0xa8bf3e31, 0xa8fe0331, 0x283c170e, -- 0x284e4c37, 0xa80419cb, 0xa8722f62, 0x0c407230, -- 0x4cdfa13d, 0x0cd56f1e, 0x4cdf2440, 0x0d40c134, -- 0x4ddfc811, 0x0ddaced5, 0x4c408f33, 0x0cdf84aa, -- 0x4d60c30a, 0x0dffcbad, 0x4de2cf96, 0x4ccb489e, -- 0x0c40481d, 0x4d40e777, 0x4ddfe943, 0x0dd6edd3, -- 0x4cdf040e, 0x0cd902de, 0x0d60e019, 0x0dffe50a, -- 0x0dfce8c1, 0xba5fd3e3, 0x3a5f03e5, 0xfa411be4, -+ 0x8b8e677b, 0xcb512964, 0xab998627, 0xeb9416cd, -+ 0x0b83438a, 0x4b463c55, 0x2b9b2406, 0x6b882b65, -+ 0x8a879c8c, 0xaa16cb75, 0xca80baa3, 0xea855955, -+ 0x0a1d5aad, 0x2a504951, 0x4a976cf0, 0x6a8c30ca, -+ 0x8a275b33, 0xaa27d459, 0xcab70ee9, 0xeaadc8c5, -+ 0x0a2a26af, 0x2abe06b1, 0x4a3d4f87, 0x6ab632d9, -+ 0x110c5346, 0x3107aa23, 0x5107eea5, 0x710dcf76, -+ 0x9103d10c, 0xb10e811d, 0xd10a087a, 0xf109d1fd, -+ 0x1209afd5, 0x32099d95, 0x5202c62b, 0x720897da, -+ 0x920e36f9, 0xb243f1de, 0xd263d09a, 0xf24fd01a, -+ 0x14000000, 0x17ffffd7, 0x1400023e, 0x94000000, -+ 0x97ffffd4, 0x9400023b, 0x3400001c, 0x34fffa3c, -+ 0x3400471c, 0x35000011, 0x35fff9d1, 0x350046b1, -+ 0xb4000019, 0xb4fff979, 0xb4004659, 0xb5000002, -+ 0xb5fff902, 0xb50045e2, 0x1000001d, 0x10fff8bd, -+ 0x1000459d, 0x9000001d, 0x36300006, 0x3637f826, -+ 0x36304506, 0x37100015, 0x3717f7d5, 0x371044b5, -+ 0x128155e8, 0x52a5762b, 0x72acb59a, 0x92866a8d, -+ 0xd2e2d8a6, 0xf2c54450, 0x93516bde, 0x330f3124, -+ 0x5301168f, 0x9353391b, 0xb355741e, 0xd3562f5b, -+ 0x13866d8c, 0x93d6b5b3, 0x54000000, 0x54fff5a0, -+ 0x54004280, 0x54000001, 0x54fff541, 0x54004221, -+ 0x54000002, 0x54fff4e2, 0x540041c2, 0x54000002, -+ 0x54fff482, 0x54004162, 0x54000003, 0x54fff423, -+ 0x54004103, 0x54000003, 0x54fff3c3, 0x540040a3, -+ 0x54000004, 0x54fff364, 0x54004044, 0x54000005, -+ 0x54fff305, 0x54003fe5, 0x54000006, 0x54fff2a6, -+ 0x54003f86, 0x54000007, 0x54fff247, 0x54003f27, -+ 0x54000008, 0x54fff1e8, 0x54003ec8, 0x54000009, -+ 0x54fff189, 0x54003e69, 0x5400000a, 0x54fff12a, -+ 0x54003e0a, 0x5400000b, 0x54fff0cb, 0x54003dab, -+ 0x5400000c, 0x54fff06c, 0x54003d4c, 0x5400000d, -+ 0x54fff00d, 0x54003ced, 0x5400000e, 0x54ffefae, -+ 0x54003c8e, 0x5400000f, 0x54ffef4f, 0x54003c2f, -+ 0xd407da81, 0xd402d542, 0xd406dae3, 0xd4258fa0, -+ 0xd44d5960, 0xd503201f, 0xd69f03e0, 0xd6bf03e0, -+ 0xd5033fdf, 0xd503339f, 0xd50336bf, 0xd61f0160, -+ 0xd63f0320, 0xc80e7daf, 0xc81efc39, 0xc85f7c6d, -+ 0xc85ffea8, 0xc89fff8d, 0xc8dfffc8, 0x880d7f91, -+ 0x8815fe71, 0x885f7d03, 0x885ffebd, 0x889fff09, -+ 0x88dffcc2, 0x480c7e14, 0x4802fcbc, 0x485f7c61, -+ 0x485ffdb8, 0x489fff2f, 0x48dffe8a, 0x08057db0, -+ 0x080afe2f, 0x085f7e71, 0x085ffd3e, 0x089fff14, -+ 0x08dffc8a, 0xc87f2139, 0xc87faa07, 0xc8392d30, -+ 0xc827a5e5, 0x887f106c, 0x887f88b1, 0x882460c8, -+ 0x8824e60c, 0xf800b3ce, 0xb819f3a6, 0x381f9162, -+ 0x781ea114, 0xf85e33b4, 0xb85e6009, 0x3940204e, -+ 0x785e802d, 0x389f922d, 0x789f50f1, 0x78dc4103, -+ 0xb9800d8e, 0xfc5152a5, 0xbc5ca009, 0xfc05f10f, -+ 0xbc1f0016, 0xf8111c97, 0xb8186c11, 0x381fbd3a, -+ 0x781f8dd5, 0xf8417ce8, 0xb8416d0c, 0x38406f9b, -+ 0x785c6e66, 0x389ecca7, 0x789e0e36, 0x78dfedb1, -+ 0xb8816c9d, 0xfc5b2f88, 0xbc5fbd77, 0xfc1e9e89, -+ 0xbc199c65, 0xf802044d, 0xb803967e, 0x3800343d, -+ 0x781ef74a, 0xf85f442f, 0xb85fa4a1, 0x385f25f8, -+ 0x785fb63d, 0x389ef5e4, 0x789ca446, 0x78c1277b, -+ 0xb89b3729, 0xfc5507b5, 0xbc5ce53e, 0xfc1d2582, -+ 0xbc1c56a7, 0xf837598c, 0xb8364bce, 0x383a586c, -+ 0x783e49cb, 0xf8787918, 0xb87469ac, 0x38655896, -+ 0x786658bc, 0x38b97962, 0x78b9ead7, 0x78f6da83, -+ 0xb8aefba9, 0xfc7dfaf0, 0xbc747b87, 0xfc387a94, -+ 0xbc377ab9, 0xf9180c51, 0xb91b38fe, 0x391ca4e3, -+ 0x791a4c27, 0xf95ca767, 0xb9580e28, 0x3958ea20, -+ 0x795bd680, 0x399a4633, 0x799d80d3, 0x79dcf944, -+ 0xb99b249d, 0xfd5a143d, 0xbd59938f, 0xfd1b9347, -+ 0xbd1aa7c0, 0x58000019, 0x18000009, 0xf88692c0, -+ 0xd8ffdf00, 0xf8be7b80, 0xf99c8260, 0x1a180111, -+ 0x3a09022e, 0x5a190036, 0x7a13012f, 0x9a0b028f, -+ 0xba1e0164, 0xda060114, 0xfa0f02aa, 0x0b298d61, -+ 0x2b3cee24, 0xcb3ca7b5, 0x6b37d38b, 0x8b25f34c, -+ 0xab3e68d1, 0xcb210a87, 0xeb3eed3e, 0x3a4b0087, -+ 0x7a4571eb, 0xba5122e6, 0xfa4bc16a, 0x3a4519cc, -+ 0x7a5c1aef, 0xba5e3a27, 0xfa4c8bc0, 0x1a81537a, -+ 0x1a95d56e, 0x5a8f60de, 0x5a995451, 0x9a8780b0, -+ 0x9a9cc68a, 0xda8180e6, 0xda912756, 0x5ac000cb, -+ 0x5ac00760, 0x5ac00ba1, 0x5ac012b4, 0x5ac0158c, -+ 0xdac00278, 0xdac005f7, 0xdac00831, 0xdac00c7b, -+ 0xdac010be, 0xdac0140f, 0x1ad4080e, 0x1ad50d9b, -+ 0x1ada214c, 0x1ac6266e, 0x1ade2a7b, 0x1ad02dc6, -+ 0x9ac209b1, 0x9ac20fa0, 0x9ac2220c, 0x9add26e9, -+ 0x9add2a26, 0x9ada2fce, 0x9bda7f11, 0x9b4e7f54, -+ 0x1b021d1b, 0x1b19b1bc, 0x9b0a6d24, 0x9b08f956, -+ 0x9b391694, 0x9b2beed6, 0x9bac4cc4, 0x9ba881f1, -+ 0x1e2a08b6, 0x1e301904, 0x1e262919, 0x1e393b66, -+ 0x1e290aea, 0x1e6c0a36, 0x1e74180b, 0x1e6f2980, -+ 0x1e643acf, 0x1e79083d, 0x1f131769, 0x1f06e87a, -+ 0x1f285184, 0x1f354539, 0x1f5e5867, 0x1f4aab61, -+ 0x1f760511, 0x1f626f8e, 0x1e2043db, 0x1e20c025, -+ 0x1e214277, 0x1e21c23c, 0x1e22c0d9, 0x1e6041d4, -+ 0x1e60c151, 0x1e61422a, 0x1e61c235, 0x1e6241f5, -+ 0x1e380167, 0x9e3803a2, 0x1e780323, 0x9e78011c, -+ 0x1e22006b, 0x9e2202a2, 0x1e62033d, 0x9e620073, -+ 0x1e2603b4, 0x9e660237, 0x1e270380, 0x9e670289, -+ 0x1e2c20e0, 0x1e6e21a0, 0x1e202188, 0x1e602028, -+ 0x29380acc, 0x2966271b, 0x696a130f, 0xa9015405, -+ 0xa9735d26, 0x29820fa0, 0x29ee403d, 0x69c24ebb, -+ 0xa9b545a6, 0xa9c16020, 0x288052c0, 0x28fa31d1, -+ 0x68ce682a, 0xa8ba61b4, 0xa8c330e1, 0x28362ae5, -+ 0x287a2b08, 0xa8043d6b, 0xa84470a9, 0x0c40728b, -+ 0x4cdfa113, 0x0cc36c43, 0x4cdf2475, 0x0d40c0ae, -+ 0x4ddfcb6d, 0x0dc0ce71, 0x4c408cbb, 0x0cdf849a, -+ 0x4d60c2e8, 0x0dffc94e, 0x4df3ceaa, 0x4cde49d1, -+ 0x0c404a94, 0x4d40e6b8, 0x4ddfe83a, 0x0dc0ec4c, -+ 0x4cdf04d5, 0x0cd60391, 0x0d60e333, 0x0dffe6e6, -+ 0x0dfae928, 0xba5fd3e3, 0x3a5f03e5, 0xfa411be4, - 0x7a42cbe2, 0x93df03ff, 0xc820ffff, 0x8822fc7f, - 0xc8247cbf, 0x88267fff, 0x4e010fe0, 0x4e081fe1, - 0x4e0c1fe1, 0x4e0a1fe1, 0x4e071fe1, 0x4cc0ac3f, -- 0x1e601000, 0x1e603000, 0x1e621000, 0x1e623000, -- 0x1e641000, 0x1e643000, 0x1e661000, 0x1e663000, -- 0x1e681000, 0x1e683000, 0x1e6a1000, 0x1e6a3000, -- 0x1e6c1000, 0x1e6c3000, 0x1e6e1000, 0x1e6e3000, -- 0x1e701000, 0x1e703000, 0x1e721000, 0x1e723000, -- 0x1e741000, 0x1e743000, 0x1e761000, 0x1e763000, -- 0x1e781000, 0x1e783000, 0x1e7a1000, 0x1e7a3000, -- 0x1e7c1000, 0x1e7c3000, 0x1e7e1000, 0x1e7e3000, -- 0xf83081f4, 0xf8220387, 0xf834132a, 0xf836204b, -- 0xf821326a, 0xf82e5075, 0xf83c41bb, 0xf83172be, -- 0xf83b63b0, 0xf8be8009, 0xf8bc039b, 0xf8b51159, -- 0xf8bf21f4, 0xf8a131d9, 0xf8b553ba, 0xf8a8433d, -- 0xf8ad7322, 0xf8af6017, 0xf8e38041, 0xf8fc0283, -- 0xf8ee11df, 0xf8e7205c, 0xf8e030ab, 0xf8eb528e, -- 0xf8ff4044, 0xf8fa72c0, 0xf8f161a1, 0xf877829a, -- 0xf86e018b, 0xf86c11ff, 0xf87b210e, 0xf86a333e, -- 0xf8765207, 0xf8614110, 0xf8617341, 0xf86061f7, -- 0xb82b8110, 0xb82101c7, 0xb830113f, 0xb83621a6, -- 0xb82b308d, 0xb8305016, 0xb83c415f, 0xb8307105, -- 0xb83a61f4, 0xb8bb8206, 0xb8bf005f, 0xb8b8111c, -- 0xb8af22e9, 0xb8ba30e2, 0xb8a351f1, 0xb8b342a5, -- 0xb8a7719a, 0xb8ac63a7, 0xb8e98288, 0xb8e803df, -- 0xb8e01186, 0xb8f12057, 0xb8e0303e, 0xb8f651e3, -- 0xb8f941b5, 0xb8ed7378, 0xb8f46163, 0xb86382ad, -- 0xb87a034f, 0xb8691053, 0xb87820fd, 0xb87d31f9, -- 0xb86b50fe, 0xb86b40c2, 0xb87071cb, 0xb8656168, -+ 0x05a08020, 0x04b0e3e0, 0x0470e7e1, 0x042f9c20, -+ 0x043f9c35, 0x047f9c20, 0x04ff9c20, 0x04299420, -+ 0x04319160, 0x0461943e, 0x04a19020, 0x042053ff, -+ 0x047f5401, 0x25208028, 0x2538cfe0, 0x2578d001, -+ 0x25b8efe2, 0x25f8f007, 0xa400a3e0, 0xa4a8a7ea, -+ 0xa547a814, 0xa4084ffe, 0xa55c53e0, 0xa5e1540b, -+ 0xe400fbf6, 0xe408ffff, 0xe547e400, 0xe4014be0, -+ 0xe4a84fe0, 0xe5e85000, 0x858043e0, 0x85a043ff, -+ 0xe59f5d08, 0x1e601000, 0x1e603000, 0x1e621000, -+ 0x1e623000, 0x1e641000, 0x1e643000, 0x1e661000, -+ 0x1e663000, 0x1e681000, 0x1e683000, 0x1e6a1000, -+ 0x1e6a3000, 0x1e6c1000, 0x1e6c3000, 0x1e6e1000, -+ 0x1e6e3000, 0x1e701000, 0x1e703000, 0x1e721000, -+ 0x1e723000, 0x1e741000, 0x1e743000, 0x1e761000, -+ 0x1e763000, 0x1e781000, 0x1e783000, 0x1e7a1000, -+ 0x1e7a3000, 0x1e7c1000, 0x1e7c3000, 0x1e7e1000, -+ 0x1e7e3000, 0xf82b82af, 0xf83700a8, 0xf8271106, -+ 0xf82e22ee, 0xf82a3019, 0xf82552a9, 0xf824423b, -+ 0xf82a71a6, 0xf8236203, 0xf8a9805c, 0xf8b70022, -+ 0xf8a410fa, 0xf8a02143, 0xf8b83079, 0xf8ab5028, -+ 0xf8b043ad, 0xf8a670a0, 0xf8b061b1, 0xf8eb81db, -+ 0xf8e202ad, 0xf8f6119f, 0xf8e721fe, 0xf8e731f0, -+ 0xf8f051ba, 0xf8f74379, 0xf8e473ee, 0xf8f86221, -+ 0xf8628308, 0xf874027b, 0xf87310d1, 0xf86e235c, -+ 0xf8623270, 0xf86e5090, 0xf8794128, 0xf86a73a5, -+ 0xf86661c2, 0xb831808b, 0xb82701f0, 0xb82b1139, -+ 0xb823200e, 0xb820301e, 0xb826538a, 0xb82740ce, -+ 0xb826701e, 0xb83663be, 0xb8b0826e, 0xb8b50323, -+ 0xb8a21270, 0xb8ba22f4, 0xb8b133e6, 0xb8a553d7, -+ 0xb8ab41cc, 0xb8a271b4, 0xb8af6291, 0xb8e682fc, -+ 0xb8fb01b0, 0xb8e21317, 0xb8e0215c, 0xb8e330af, -+ 0xb8e353ab, 0xb8f640db, 0xb8f17214, 0xb8f760ef, -+ 0xb86881d0, 0xb87702f0, 0xb87c10ec, 0xb87c2267, -+ 0xb867316c, 0xb86a529f, 0xb86943e8, 0xb86a7048, -+ 0xb87163ff, 0x047600e2, 0x04be06de, 0x65d902ca, -+ 0x65cc0a17, 0x65d90623, 0x0496a099, 0x04401b57, -+ 0x04d08226, 0x04daac77, 0x04939d2b, 0x04919c7b, -+ 0x04901049, 0x0417a9f0, 0x04dea929, 0x048816ea, -+ 0x040a172d, 0x04811413, 0x04dca2d1, 0x65808a09, -+ 0x658d9411, 0x6586947d, 0x65878e21, 0x65c2880e, -+ 0x04ddb2d3, 0x65c2a5f1, 0x65c0b088, 0x65c1b3a5, -+ 0x65cda26b, 0x65c1938a, 0x65eb0ded, 0x65af3e86, -+ 0x65a749be, 0x65f379d6, 0x04404f3e, 0x04c16b0a, -+ 0x04363226, 0x04b1312a, 0x04753182, 0x049a39cf, -+ 0x04d82ce9, 0x0459353e, 0x04883347, 0x048a2fb4, -+ 0x65872e1c, 0x65c62d26, 0x6598346a, 0x04013915, - - }; - // END Generated code -- do not edit -diff --git a/src/hotspot/cpu/aarch64/aarch64-asmtest.py b/src/hotspot/cpu/aarch64/aarch64-asmtest.py -index 31c6965b7..2211bd25a 100644 ---- a/src/hotspot/cpu/aarch64/aarch64-asmtest.py -+++ b/src/hotspot/cpu/aarch64/aarch64-asmtest.py -@@ -73,6 +73,48 @@ class GeneralRegisterOrSp(Register): - return self.astr() - else: - return self.astr("r") -+class SVEVectorRegister(FloatRegister): -+ def __str__(self): -+ return self.astr("z") -+ -+class SVEPRegister(Register): -+ def __str__(self): -+ return self.astr("p") -+ -+ def generate(self): -+ self.number = random.randint(0, 15) -+ return self -+ -+class SVEGoverningPRegister(Register): -+ def __str__(self): -+ return self.astr("p") -+ def generate(self): -+ self.number = random.randint(0, 7) -+ return self -+ -+class RegVariant(object): -+ def __init__(self, low, high): -+ self.number = random.randint(low, high) -+ -+ def astr(self): -+ nameMap = { -+ 0: ".b", -+ 1: ".h", -+ 2: ".s", -+ 3: ".d", -+ 4: ".q" -+ } -+ return nameMap.get(self.number) -+ -+ def cstr(self): -+ nameMap = { -+ 0: "__ B", -+ 1: "__ H", -+ 2: "__ S", -+ 3: "__ D", -+ 4: "__ Q" -+ } -+ return nameMap.get(self.number) - - class FloatZero(Operand): - -@@ -88,7 +130,10 @@ class OperandFactory: - 'w' : GeneralRegister, - 's' : FloatRegister, - 'd' : FloatRegister, -- 'z' : FloatZero} -+ 'z' : FloatZero, -+ 'p' : SVEPRegister, -+ 'P' : SVEGoverningPRegister, -+ 'Z' : SVEVectorRegister} - - @classmethod - def create(cls, mode): -@@ -834,6 +879,100 @@ class FloatInstruction(Instruction): - % tuple([Instruction.astr(self)] + - [(self.reg[i].astr(self.modes[i])) for i in range(self.numRegs)])) - -+class SVEVectorOp(Instruction): -+ def __init__(self, args): -+ name = args[0] -+ regTypes = args[1] -+ regs = [] -+ for c in regTypes: -+ regs.append(OperandFactory.create(c).generate()) -+ self.reg = regs -+ self.numRegs = len(regs) -+ if regTypes[0] != "p" and regTypes[1] == 'P': -+ self._isPredicated = True -+ self._merge = "/m" -+ else: -+ self._isPredicated = False -+ self._merge ="" -+ -+ self._bitwiseop = False -+ if name[0] == 'f': -+ self._width = RegVariant(2, 3) -+ elif not self._isPredicated and (name in ["and", "eor", "orr", "bic"]): -+ self._width = RegVariant(3, 3) -+ self._bitwiseop = True -+ else: -+ self._width = RegVariant(0, 3) -+ if len(args) > 2: -+ self._dnm = args[2] -+ else: -+ self._dnm = None -+ Instruction.__init__(self, name) -+ -+ def cstr(self): -+ formatStr = "%s%s" + ''.join([", %s" for i in range(0, self.numRegs)] + [");"]) -+ if self._bitwiseop: -+ width = [] -+ formatStr = "%s%s" + ''.join([", %s" for i in range(1, self.numRegs)] + [");"]) -+ else: -+ width = [self._width.cstr()] -+ return (formatStr -+ % tuple(["__ sve_" + self._name + "("] + -+ [str(self.reg[0])] + -+ width + -+ [str(self.reg[i]) for i in range(1, self.numRegs)])) -+ def astr(self): -+ formatStr = "%s%s" + ''.join([", %s" for i in range(1, self.numRegs)]) -+ if self._dnm == 'dn': -+ formatStr += ", %s" -+ dnReg = [str(self.reg[0]) + self._width.astr()] -+ else: -+ dnReg = [] -+ -+ if self._isPredicated: -+ restRegs = [str(self.reg[1]) + self._merge] + dnReg + [str(self.reg[i]) + self._width.astr() for i in range(2, self.numRegs)] -+ else: -+ restRegs = dnReg + [str(self.reg[i]) + self._width.astr() for i in range(1, self.numRegs)] -+ return (formatStr -+ % tuple([Instruction.astr(self)] + -+ [str(self.reg[0]) + self._width.astr()] + -+ restRegs)) -+ def generate(self): -+ return self -+ -+class SVEReductionOp(Instruction): -+ def __init__(self, args): -+ name = args[0] -+ lowRegType = args[1] -+ self.reg = [] -+ Instruction.__init__(self, name) -+ self.reg.append(OperandFactory.create('s').generate()) -+ self.reg.append(OperandFactory.create('P').generate()) -+ self.reg.append(OperandFactory.create('Z').generate()) -+ self._width = RegVariant(lowRegType, 3) -+ def cstr(self): -+ return "__ sve_%s(%s, %s, %s, %s);" % (self.name(), -+ str(self.reg[0]), -+ self._width.cstr(), -+ str(self.reg[1]), -+ str(self.reg[2])) -+ def astr(self): -+ if self.name() == "uaddv": -+ dstRegName = "d" + str(self.reg[0].number) -+ else: -+ dstRegName = self._width.astr()[1] + str(self.reg[0].number) -+ formatStr = "%s %s, %s, %s" -+ if self.name() == "fadda": -+ formatStr += ", %s" -+ moreReg = [dstRegName] -+ else: -+ moreReg = [] -+ return formatStr % tuple([self.name()] + -+ [dstRegName] + -+ [str(self.reg[1])] + -+ moreReg + -+ [str(self.reg[2]) + self._width.astr()]) -+ - class LdStSIMDOp(Instruction): - def __init__(self, args): - self._name, self.regnum, self.arrangement, self.addresskind = args -@@ -1120,7 +1259,42 @@ generate(SpecialCases, [["ccmn", "__ ccmn(zr, zr, 3u, Assembler::LE);", - ["mov", "__ mov(v1, __ T2S, 1, zr);", "mov\tv1.s[1], wzr"], - ["mov", "__ mov(v1, __ T4H, 2, zr);", "mov\tv1.h[2], wzr"], - ["mov", "__ mov(v1, __ T8B, 3, zr);", "mov\tv1.b[3], wzr"], -- ["ld1", "__ ld1(v31, v0, __ T2D, Address(__ post(r1, r0)));", "ld1\t{v31.2d, v0.2d}, [x1], x0"]]) -+ ["ld1", "__ ld1(v31, v0, __ T2D, Address(__ post(r1, r0)));", "ld1\t{v31.2d, v0.2d}, [x1], x0"], -+ # SVE instructions -+ ["cpy", "__ sve_cpy(z0, __ S, p0, v1);", "mov\tz0.s, p0/m, s1"], -+ ["inc", "__ sve_inc(r0, __ S);", "incw\tx0"], -+ ["dec", "__ sve_dec(r1, __ H);", "dech\tx1"], -+ ["lsl", "__ sve_lsl(z0, __ B, z1, 7);", "lsl\tz0.b, z1.b, #7"], -+ ["lsl", "__ sve_lsl(z21, __ H, z1, 15);", "lsl\tz21.h, z1.h, #15"], -+ ["lsl", "__ sve_lsl(z0, __ S, z1, 31);", "lsl\tz0.s, z1.s, #31"], -+ ["lsl", "__ sve_lsl(z0, __ D, z1, 63);", "lsl\tz0.d, z1.d, #63"], -+ ["lsr", "__ sve_lsr(z0, __ B, z1, 7);", "lsr\tz0.b, z1.b, #7"], -+ ["asr", "__ sve_asr(z0, __ H, z11, 15);", "asr\tz0.h, z11.h, #15"], -+ ["lsr", "__ sve_lsr(z30, __ S, z1, 31);", "lsr\tz30.s, z1.s, #31"], -+ ["asr", "__ sve_asr(z0, __ D, z1, 63);", "asr\tz0.d, z1.d, #63"], -+ ["addvl", "__ sve_addvl(sp, r0, 31);", "addvl\tsp, x0, #31"], -+ ["addpl", "__ sve_addpl(r1, sp, -32);", "addpl\tx1, sp, -32"], -+ ["cntp", "__ sve_cntp(r8, __ B, p0, p1);", "cntp\tx8, p0, p1.b"], -+ ["dup", "__ sve_dup(z0, __ B, 127);", "dup\tz0.b, 127"], -+ ["dup", "__ sve_dup(z1, __ H, -128);", "dup\tz1.h, -128"], -+ ["dup", "__ sve_dup(z2, __ S, 32512);", "dup\tz2.s, 32512"], -+ ["dup", "__ sve_dup(z7, __ D, -32768);", "dup\tz7.d, -32768"], -+ ["ld1b", "__ sve_ld1b(z0, __ B, p0, Address(sp));", "ld1b\t{z0.b}, p0/z, [sp]"], -+ ["ld1h", "__ sve_ld1h(z10, __ H, p1, Address(sp, -8));", "ld1h\t{z10.h}, p1/z, [sp, #-8, MUL VL]"], -+ ["ld1w", "__ sve_ld1w(z20, __ S, p2, Address(r0, 7));", "ld1w\t{z20.s}, p2/z, [x0, #7, MUL VL]"], -+ ["ld1b", "__ sve_ld1b(z30, __ B, p3, Address(sp, r8));", "ld1b\t{z30.b}, p3/z, [sp, x8]"], -+ ["ld1w", "__ sve_ld1w(z0, __ S, p4, Address(sp, r28));", "ld1w\t{z0.s}, p4/z, [sp, x28, LSL #2]"], -+ ["ld1d", "__ sve_ld1d(z11, __ D, p5, Address(r0, r1));", "ld1d\t{z11.d}, p5/z, [x0, x1, LSL #3]"], -+ ["st1b", "__ sve_st1b(z22, __ B, p6, Address(sp));", "st1b\t{z22.b}, p6, [sp]"], -+ ["st1b", "__ sve_st1b(z31, __ B, p7, Address(sp, -8));", "st1b\t{z31.b}, p7, [sp, #-8, MUL VL]"], -+ ["st1w", "__ sve_st1w(z0, __ S, p1, Address(r0, 7));", "st1w\t{z0.s}, p1, [x0, #7, MUL VL]"], -+ ["st1b", "__ sve_st1b(z0, __ B, p2, Address(sp, r1));", "st1b\t{z0.b}, p2, [sp, x1]"], -+ ["st1h", "__ sve_st1h(z0, __ H, p3, Address(sp, r8));", "st1h\t{z0.h}, p3, [sp, x8, LSL #1]"], -+ ["st1d", "__ sve_st1d(z0, __ D, p4, Address(r0, r8));", "st1d\t{z0.d}, p4, [x0, x8, LSL #3]"], -+ ["ldr", "__ sve_ldr(z0, Address(sp));", "ldr\tz0, [sp]"], -+ ["ldr", "__ sve_ldr(z31, Address(sp, -256));", "ldr\tz31, [sp, #-256, MUL VL]"], -+ ["str", "__ sve_str(z8, Address(r8, 255));", "str\tz8, [x8, #255, MUL VL]"], -+]) - - print "\n// FloatImmediateOp" - for float in ("2.0", "2.125", "4.0", "4.25", "8.0", "8.5", "16.0", "17.0", "0.125", -@@ -1145,6 +1319,50 @@ for size in ("x", "w"): - ["ldumin", "ldumin", size, suffix], - ["ldumax", "ldumax", size, suffix]]); - -+ -+generate(SVEVectorOp, [["add", "ZZZ"], -+ ["sub", "ZZZ"], -+ ["fadd", "ZZZ"], -+ ["fmul", "ZZZ"], -+ ["fsub", "ZZZ"], -+ ["abs", "ZPZ"], -+ ["add", "ZPZ", "dn"], -+ ["asr", "ZPZ", "dn"], -+ ["cnt", "ZPZ"], -+ ["lsl", "ZPZ", "dn"], -+ ["lsr", "ZPZ", "dn"], -+ ["mul", "ZPZ", "dn"], -+ ["neg", "ZPZ"], -+ ["not", "ZPZ"], -+ ["smax", "ZPZ", "dn"], -+ ["smin", "ZPZ", "dn"], -+ ["sub", "ZPZ", "dn"], -+ ["fabs", "ZPZ"], -+ ["fadd", "ZPZ", "dn"], -+ ["fdiv", "ZPZ", "dn"], -+ ["fmax", "ZPZ", "dn"], -+ ["fmin", "ZPZ", "dn"], -+ ["fmul", "ZPZ", "dn"], -+ ["fneg", "ZPZ"], -+ ["frintm", "ZPZ"], -+ ["frintn", "ZPZ"], -+ ["frintp", "ZPZ"], -+ ["fsqrt", "ZPZ"], -+ ["fsub", "ZPZ", "dn"], -+ ["fmla", "ZPZZ"], -+ ["fmls", "ZPZZ"], -+ ["fnmla", "ZPZZ"], -+ ["fnmls", "ZPZZ"], -+ ["mla", "ZPZZ"], -+ ["mls", "ZPZZ"], -+ ["and", "ZZZ"], -+ ["eor", "ZZZ"], -+ ["orr", "ZZZ"], -+ ]) -+ -+generate(SVEReductionOp, [["andv", 0], ["orv", 0], ["eorv", 0], ["smaxv", 0], ["sminv", 0], -+ ["fminv", 2], ["fmaxv", 2], ["fadda", 2], ["uaddv", 0]]) -+ - print "\n __ bind(forth);" - outfile.write("forth:\n") - -@@ -1153,8 +1372,8 @@ outfile.close() - import subprocess - import sys - --# compile for 8.1 because of lse atomics --subprocess.check_call([AARCH64_AS, "-march=armv8.1-a", "aarch64ops.s", "-o", "aarch64ops.o"]) -+# compile for sve with 8.1 and sha2 because of lse atomics and sha512 crypto extension. -+subprocess.check_call([AARCH64_AS, "-march=armv8.1-a+sha2+sve", "aarch64ops.s", "-o", "aarch64ops.o"]) +- 0x081bfe11, 0x085f7f66, 0x085fff1b, 0x089ffe8a, +- 0x08dfff49, 0xc87f7b85, 0xc87fa66a, 0xc82b5590, +- 0xc82adc94, 0x887f0416, 0x887f8503, 0x88205fc9, +- 0x8837c560, 0xf81e1146, 0xb81fb007, 0x381f3205, +- 0x7801f27e, 0xf8477130, 0xb843b208, 0x385f918a, +- 0x785da12e, 0x389f83d8, 0x78817087, 0x78dd91d1, +- 0xb89e136b, 0xfc4410ec, 0xbc5fe200, 0xfc15f2ed, +- 0xbc1c2075, 0xf8064ca2, 0xb81a4c29, 0x381fbfdb, +- 0x7800cdfb, 0xf852ce24, 0xb841eef5, 0x385f9e2d, +- 0x785cec19, 0x389ebea1, 0x789caebc, 0x78c02c8b, +- 0xb883dd31, 0xfc427e7d, 0xbc5abed6, 0xfc11ff29, +- 0xbc1f1c49, 0xf81be6ed, 0xb800a611, 0x381e05c1, +- 0x78006411, 0xf855473b, 0xb85da72d, 0x385e372b, +- 0x784144be, 0x389f94e9, 0x789c2460, 0x78c1f5c7, +- 0xb8827771, 0xfc515491, 0xbc4226ba, 0xfc1c7625, +- 0xbc1935ad, 0xf824da06, 0xb834db09, 0x38237ba3, +- 0x783e6a2a, 0xf867497b, 0xb87949ee, 0x387379d8, +- 0x7866c810, 0x38acd98a, 0x78b0499a, 0x78ee781a, +- 0xb8bbf971, 0xfc73d803, 0xbc6979fa, 0xfc30e9ab, +- 0xbc355a7a, 0xf91886a8, 0xb918ef6a, 0x391b15db, +- 0x791ac0f0, 0xf958753b, 0xb95a1958, 0x395b3f18, +- 0x795800b4, 0x39988891, 0x799a81ae, 0x79dd172a, +- 0xb9981342, 0xfd5d21da, 0xbd5e7c9c, 0xfd1b526e, +- 0xbd18df97, 0x58002268, 0x18ffdf51, 0xf8951080, +- 0xd8000000, 0xf8a4c900, 0xf999e180, 0x1a150374, +- 0x3a060227, 0x5a1900c5, 0x7a0e017e, 0x9a0b0223, +- 0xba110159, 0xda170207, 0xfa050144, 0x0b2973c9, +- 0x2b30a8a0, 0xcb3b8baf, 0x6b21f12b, 0x8b264f02, +- 0xab3a70d3, 0xcb39ef48, 0xeb29329a, 0x3a5a41a7, +- 0x7a54310f, 0xba4302c8, 0xfa58a04a, 0x3a50490d, +- 0x7a4c0a01, 0xba5f79e3, 0xfa4c0aef, 0x1a9a30ee, +- 0x1a9ed763, 0x5a9702ab, 0x5a95c7da, 0x9a8d835c, +- 0x9a909471, 0xda8380ab, 0xda93c461, 0x5ac00120, +- 0x5ac005da, 0x5ac00a2d, 0x5ac0128b, 0x5ac0163c, +- 0xdac0008d, 0xdac007c1, 0xdac009cd, 0xdac00d05, +- 0xdac01322, 0xdac01514, 0x1adb0b35, 0x1ad00d4d, +- 0x1ad1203c, 0x1aca26f9, 0x1ac72867, 0x1ace2fce, +- 0x9acf0acc, 0x9acd0f22, 0x9ad522e7, 0x9ac0258b, +- 0x9adc293e, 0x9ad62cad, 0x9bc47ea5, 0x9b477c51, +- 0x1b11318c, 0x1b01edfe, 0x9b117662, 0x9b03fae4, +- 0x9b313eef, 0x9b21b59b, 0x9bac45a6, 0x9ba6a839, +- 0x1e240871, 0x1e3518b0, 0x1e312b63, 0x1e2f3959, +- 0x1e200a2a, 0x1e630b5c, 0x1e7b1804, 0x1e6229dc, +- 0x1e773b4c, 0x1e610bcf, 0x1f0534a4, 0x1f1c85b5, +- 0x1f3d1c71, 0x1f3d6b37, 0x1f5e68ee, 0x1f4aa4f6, +- 0x1f6e24e7, 0x1f6f630e, 0x1e204056, 0x1e20c060, +- 0x1e214229, 0x1e21c178, 0x1e22c32f, 0x1e604064, +- 0x1e60c2da, 0x1e61427e, 0x1e61c1cc, 0x1e6240f1, +- 0x1e3801d8, 0x9e38034d, 0x1e780022, 0x9e780165, +- 0x1e22026e, 0x9e2202c1, 0x1e62023b, 0x9e620136, +- 0x1e26006e, 0x9e66022c, 0x1e270368, 0x9e67039d, +- 0x1e3e2000, 0x1e692180, 0x1e202148, 0x1e602328, +- 0x292e7b68, 0x294a4f15, 0x69626c50, 0xa93814d5, +- 0xa97e679d, 0x29903408, 0x29ec5039, 0x69fc62ce, +- 0xa98504d1, 0xa9fc4735, 0x28b05691, 0x28c8705c, +- 0x68e07953, 0xa8bf3e31, 0xa8fe0331, 0x283c170e, +- 0x284e4c37, 0xa80419cb, 0xa8722f62, 0x0c407230, +- 0x4cdfa13d, 0x0cd56f1e, 0x4cdf2440, 0x0d40c134, +- 0x4ddfc811, 0x0ddaced5, 0x4c408f33, 0x0cdf84aa, +- 0x4d60c30a, 0x0dffcbad, 0x4de2cf96, 0x4ccb489e, +- 0x0c40481d, 0x4d40e777, 0x4ddfe943, 0x0dd6edd3, +- 0x4cdf040e, 0x0cd902de, 0x0d60e019, 0x0dffe50a, +- 0x0dfce8c1, 0xba5fd3e3, 0x3a5f03e5, 0xfa411be4, ++ 0x8b8e677b, 0xcb512964, 0xab998627, 0xeb9416cd, ++ 0x0b83438a, 0x4b463c55, 0x2b9b2406, 0x6b882b65, ++ 0x8a879c8c, 0xaa16cb75, 0xca80baa3, 0xea855955, ++ 0x0a1d5aad, 0x2a504951, 0x4a976cf0, 0x6a8c30ca, ++ 0x8a275b33, 0xaa27d459, 0xcab70ee9, 0xeaadc8c5, ++ 0x0a2a26af, 0x2abe06b1, 0x4a3d4f87, 0x6ab632d9, ++ 0x110c5346, 0x3107aa23, 0x5107eea5, 0x710dcf76, ++ 0x9103d10c, 0xb10e811d, 0xd10a087a, 0xf109d1fd, ++ 0x1209afd5, 0x32099d95, 0x5202c62b, 0x720897da, ++ 0x920e36f9, 0xb243f1de, 0xd263d09a, 0xf24fd01a, ++ 0x14000000, 0x17ffffd7, 0x1400023e, 0x94000000, ++ 0x97ffffd4, 0x9400023b, 0x3400001c, 0x34fffa3c, ++ 0x3400471c, 0x35000011, 0x35fff9d1, 0x350046b1, ++ 0xb4000019, 0xb4fff979, 0xb4004659, 0xb5000002, ++ 0xb5fff902, 0xb50045e2, 0x1000001d, 0x10fff8bd, ++ 0x1000459d, 0x9000001d, 0x36300006, 0x3637f826, ++ 0x36304506, 0x37100015, 0x3717f7d5, 0x371044b5, ++ 0x128155e8, 0x52a5762b, 0x72acb59a, 0x92866a8d, ++ 0xd2e2d8a6, 0xf2c54450, 0x93516bde, 0x330f3124, ++ 0x5301168f, 0x9353391b, 0xb355741e, 0xd3562f5b, ++ 0x13866d8c, 0x93d6b5b3, 0x54000000, 0x54fff5a0, ++ 0x54004280, 0x54000001, 0x54fff541, 0x54004221, ++ 0x54000002, 0x54fff4e2, 0x540041c2, 0x54000002, ++ 0x54fff482, 0x54004162, 0x54000003, 0x54fff423, ++ 0x54004103, 0x54000003, 0x54fff3c3, 0x540040a3, ++ 0x54000004, 0x54fff364, 0x54004044, 0x54000005, ++ 0x54fff305, 0x54003fe5, 0x54000006, 0x54fff2a6, ++ 0x54003f86, 0x54000007, 0x54fff247, 0x54003f27, ++ 0x54000008, 0x54fff1e8, 0x54003ec8, 0x54000009, ++ 0x54fff189, 0x54003e69, 0x5400000a, 0x54fff12a, ++ 0x54003e0a, 0x5400000b, 0x54fff0cb, 0x54003dab, ++ 0x5400000c, 0x54fff06c, 0x54003d4c, 0x5400000d, ++ 0x54fff00d, 0x54003ced, 0x5400000e, 0x54ffefae, ++ 0x54003c8e, 0x5400000f, 0x54ffef4f, 0x54003c2f, ++ 0xd407da81, 0xd402d542, 0xd406dae3, 0xd4258fa0, ++ 0xd44d5960, 0xd503201f, 0xd69f03e0, 0xd6bf03e0, ++ 0xd5033fdf, 0xd503339f, 0xd50336bf, 0xd61f0160, ++ 0xd63f0320, 0xc80e7daf, 0xc81efc39, 0xc85f7c6d, ++ 0xc85ffea8, 0xc89fff8d, 0xc8dfffc8, 0x880d7f91, ++ 0x8815fe71, 0x885f7d03, 0x885ffebd, 0x889fff09, ++ 0x88dffcc2, 0x480c7e14, 0x4802fcbc, 0x485f7c61, ++ 0x485ffdb8, 0x489fff2f, 0x48dffe8a, 0x08057db0, ++ 0x080afe2f, 0x085f7e71, 0x085ffd3e, 0x089fff14, ++ 0x08dffc8a, 0xc87f2139, 0xc87faa07, 0xc8392d30, ++ 0xc827a5e5, 0x887f106c, 0x887f88b1, 0x882460c8, ++ 0x8824e60c, 0xf800b3ce, 0xb819f3a6, 0x381f9162, ++ 0x781ea114, 0xf85e33b4, 0xb85e6009, 0x3940204e, ++ 0x785e802d, 0x389f922d, 0x789f50f1, 0x78dc4103, ++ 0xb9800d8e, 0xfc5152a5, 0xbc5ca009, 0xfc05f10f, ++ 0xbc1f0016, 0xf8111c97, 0xb8186c11, 0x381fbd3a, ++ 0x781f8dd5, 0xf8417ce8, 0xb8416d0c, 0x38406f9b, ++ 0x785c6e66, 0x389ecca7, 0x789e0e36, 0x78dfedb1, ++ 0xb8816c9d, 0xfc5b2f88, 0xbc5fbd77, 0xfc1e9e89, ++ 0xbc199c65, 0xf802044d, 0xb803967e, 0x3800343d, ++ 0x781ef74a, 0xf85f442f, 0xb85fa4a1, 0x385f25f8, ++ 0x785fb63d, 0x389ef5e4, 0x789ca446, 0x78c1277b, ++ 0xb89b3729, 0xfc5507b5, 0xbc5ce53e, 0xfc1d2582, ++ 0xbc1c56a7, 0xf837598c, 0xb8364bce, 0x383a586c, ++ 0x783e49cb, 0xf8787918, 0xb87469ac, 0x38655896, ++ 0x786658bc, 0x38b97962, 0x78b9ead7, 0x78f6da83, ++ 0xb8aefba9, 0xfc7dfaf0, 0xbc747b87, 0xfc387a94, ++ 0xbc377ab9, 0xf9180c51, 0xb91b38fe, 0x391ca4e3, ++ 0x791a4c27, 0xf95ca767, 0xb9580e28, 0x3958ea20, ++ 0x795bd680, 0x399a4633, 0x799d80d3, 0x79dcf944, ++ 0xb99b249d, 0xfd5a143d, 0xbd59938f, 0xfd1b9347, ++ 0xbd1aa7c0, 0x58000019, 0x18000009, 0xf88692c0, ++ 0xd8ffdf00, 0xf8be7b80, 0xf99c8260, 0x1a180111, ++ 0x3a09022e, 0x5a190036, 0x7a13012f, 0x9a0b028f, ++ 0xba1e0164, 0xda060114, 0xfa0f02aa, 0x0b298d61, ++ 0x2b3cee24, 0xcb3ca7b5, 0x6b37d38b, 0x8b25f34c, ++ 0xab3e68d1, 0xcb210a87, 0xeb3eed3e, 0x3a4b0087, ++ 0x7a4571eb, 0xba5122e6, 0xfa4bc16a, 0x3a4519cc, ++ 0x7a5c1aef, 0xba5e3a27, 0xfa4c8bc0, 0x1a81537a, ++ 0x1a95d56e, 0x5a8f60de, 0x5a995451, 0x9a8780b0, ++ 0x9a9cc68a, 0xda8180e6, 0xda912756, 0x5ac000cb, ++ 0x5ac00760, 0x5ac00ba1, 0x5ac012b4, 0x5ac0158c, ++ 0xdac00278, 0xdac005f7, 0xdac00831, 0xdac00c7b, ++ 0xdac010be, 0xdac0140f, 0x1ad4080e, 0x1ad50d9b, ++ 0x1ada214c, 0x1ac6266e, 0x1ade2a7b, 0x1ad02dc6, ++ 0x9ac209b1, 0x9ac20fa0, 0x9ac2220c, 0x9add26e9, ++ 0x9add2a26, 0x9ada2fce, 0x9bda7f11, 0x9b4e7f54, ++ 0x1b021d1b, 0x1b19b1bc, 0x9b0a6d24, 0x9b08f956, ++ 0x9b391694, 0x9b2beed6, 0x9bac4cc4, 0x9ba881f1, ++ 0x1e2a08b6, 0x1e301904, 0x1e262919, 0x1e393b66, ++ 0x1e290aea, 0x1e6c0a36, 0x1e74180b, 0x1e6f2980, ++ 0x1e643acf, 0x1e79083d, 0x1f131769, 0x1f06e87a, ++ 0x1f285184, 0x1f354539, 0x1f5e5867, 0x1f4aab61, ++ 0x1f760511, 0x1f626f8e, 0x1e2043db, 0x1e20c025, ++ 0x1e214277, 0x1e21c23c, 0x1e22c0d9, 0x1e6041d4, ++ 0x1e60c151, 0x1e61422a, 0x1e61c235, 0x1e6241f5, ++ 0x1e380167, 0x9e3803a2, 0x1e780323, 0x9e78011c, ++ 0x1e22006b, 0x9e2202a2, 0x1e62033d, 0x9e620073, ++ 0x1e2603b4, 0x9e660237, 0x1e270380, 0x9e670289, ++ 0x1e2c20e0, 0x1e6e21a0, 0x1e202188, 0x1e602028, ++ 0x29380acc, 0x2966271b, 0x696a130f, 0xa9015405, ++ 0xa9735d26, 0x29820fa0, 0x29ee403d, 0x69c24ebb, ++ 0xa9b545a6, 0xa9c16020, 0x288052c0, 0x28fa31d1, ++ 0x68ce682a, 0xa8ba61b4, 0xa8c330e1, 0x28362ae5, ++ 0x287a2b08, 0xa8043d6b, 0xa84470a9, 0x0c40728b, ++ 0x4cdfa113, 0x0cc36c43, 0x4cdf2475, 0x0d40c0ae, ++ 0x4ddfcb6d, 0x0dc0ce71, 0x4c408cbb, 0x0cdf849a, ++ 0x4d60c2e8, 0x0dffc94e, 0x4df3ceaa, 0x4cde49d1, ++ 0x0c404a94, 0x4d40e6b8, 0x4ddfe83a, 0x0dc0ec4c, ++ 0x4cdf04d5, 0x0cd60391, 0x0d60e333, 0x0dffe6e6, ++ 0x0dfae928, 0xba5fd3e3, 0x3a5f03e5, 0xfa411be4, + 0x7a42cbe2, 0x93df03ff, 0xc820ffff, 0x8822fc7f, + 0xc8247cbf, 0x88267fff, 0x4e010fe0, 0x4e081fe1, + 0x4e0c1fe1, 0x4e0a1fe1, 0x4e071fe1, 0x4cc0ac3f, +- 0x1e601000, 0x1e603000, 0x1e621000, 0x1e623000, +- 0x1e641000, 0x1e643000, 0x1e661000, 0x1e663000, +- 0x1e681000, 0x1e683000, 0x1e6a1000, 0x1e6a3000, +- 0x1e6c1000, 0x1e6c3000, 0x1e6e1000, 0x1e6e3000, +- 0x1e701000, 0x1e703000, 0x1e721000, 0x1e723000, +- 0x1e741000, 0x1e743000, 0x1e761000, 0x1e763000, +- 0x1e781000, 0x1e783000, 0x1e7a1000, 0x1e7a3000, +- 0x1e7c1000, 0x1e7c3000, 0x1e7e1000, 0x1e7e3000, +- 0xf83081f4, 0xf8220387, 0xf834132a, 0xf836204b, +- 0xf821326a, 0xf82e5075, 0xf83c41bb, 0xf83172be, +- 0xf83b63b0, 0xf8be8009, 0xf8bc039b, 0xf8b51159, +- 0xf8bf21f4, 0xf8a131d9, 0xf8b553ba, 0xf8a8433d, +- 0xf8ad7322, 0xf8af6017, 0xf8e38041, 0xf8fc0283, +- 0xf8ee11df, 0xf8e7205c, 0xf8e030ab, 0xf8eb528e, +- 0xf8ff4044, 0xf8fa72c0, 0xf8f161a1, 0xf877829a, +- 0xf86e018b, 0xf86c11ff, 0xf87b210e, 0xf86a333e, +- 0xf8765207, 0xf8614110, 0xf8617341, 0xf86061f7, +- 0xb82b8110, 0xb82101c7, 0xb830113f, 0xb83621a6, +- 0xb82b308d, 0xb8305016, 0xb83c415f, 0xb8307105, +- 0xb83a61f4, 0xb8bb8206, 0xb8bf005f, 0xb8b8111c, +- 0xb8af22e9, 0xb8ba30e2, 0xb8a351f1, 0xb8b342a5, +- 0xb8a7719a, 0xb8ac63a7, 0xb8e98288, 0xb8e803df, +- 0xb8e01186, 0xb8f12057, 0xb8e0303e, 0xb8f651e3, +- 0xb8f941b5, 0xb8ed7378, 0xb8f46163, 0xb86382ad, +- 0xb87a034f, 0xb8691053, 0xb87820fd, 0xb87d31f9, +- 0xb86b50fe, 0xb86b40c2, 0xb87071cb, 0xb8656168, ++ 0x05a08020, 0x04b0e3e0, 0x0470e7e1, 0x042f9c20, ++ 0x043f9c35, 0x047f9c20, 0x04ff9c20, 0x04299420, ++ 0x04319160, 0x0461943e, 0x04a19020, 0x042053ff, ++ 0x047f5401, 0x25208028, 0x2538cfe0, 0x2578d001, ++ 0x25b8efe2, 0x25f8f007, 0xa400a3e0, 0xa4a8a7ea, ++ 0xa547a814, 0xa4084ffe, 0xa55c53e0, 0xa5e1540b, ++ 0xe400fbf6, 0xe408ffff, 0xe547e400, 0xe4014be0, ++ 0xe4a84fe0, 0xe5e85000, 0x858043e0, 0x85a043ff, ++ 0xe59f5d08, 0x1e601000, 0x1e603000, 0x1e621000, ++ 0x1e623000, 0x1e641000, 0x1e643000, 0x1e661000, ++ 0x1e663000, 0x1e681000, 0x1e683000, 0x1e6a1000, ++ 0x1e6a3000, 0x1e6c1000, 0x1e6c3000, 0x1e6e1000, ++ 0x1e6e3000, 0x1e701000, 0x1e703000, 0x1e721000, ++ 0x1e723000, 0x1e741000, 0x1e743000, 0x1e761000, ++ 0x1e763000, 0x1e781000, 0x1e783000, 0x1e7a1000, ++ 0x1e7a3000, 0x1e7c1000, 0x1e7c3000, 0x1e7e1000, ++ 0x1e7e3000, 0xf82b82af, 0xf83700a8, 0xf8271106, ++ 0xf82e22ee, 0xf82a3019, 0xf82552a9, 0xf824423b, ++ 0xf82a71a6, 0xf8236203, 0xf8a9805c, 0xf8b70022, ++ 0xf8a410fa, 0xf8a02143, 0xf8b83079, 0xf8ab5028, ++ 0xf8b043ad, 0xf8a670a0, 0xf8b061b1, 0xf8eb81db, ++ 0xf8e202ad, 0xf8f6119f, 0xf8e721fe, 0xf8e731f0, ++ 0xf8f051ba, 0xf8f74379, 0xf8e473ee, 0xf8f86221, ++ 0xf8628308, 0xf874027b, 0xf87310d1, 0xf86e235c, ++ 0xf8623270, 0xf86e5090, 0xf8794128, 0xf86a73a5, ++ 0xf86661c2, 0xb831808b, 0xb82701f0, 0xb82b1139, ++ 0xb823200e, 0xb820301e, 0xb826538a, 0xb82740ce, ++ 0xb826701e, 0xb83663be, 0xb8b0826e, 0xb8b50323, ++ 0xb8a21270, 0xb8ba22f4, 0xb8b133e6, 0xb8a553d7, ++ 0xb8ab41cc, 0xb8a271b4, 0xb8af6291, 0xb8e682fc, ++ 0xb8fb01b0, 0xb8e21317, 0xb8e0215c, 0xb8e330af, ++ 0xb8e353ab, 0xb8f640db, 0xb8f17214, 0xb8f760ef, ++ 0xb86881d0, 0xb87702f0, 0xb87c10ec, 0xb87c2267, ++ 0xb867316c, 0xb86a529f, 0xb86943e8, 0xb86a7048, ++ 0xb87163ff, 0x047600e2, 0x04be06de, 0x65d902ca, ++ 0x65cc0a17, 0x65d90623, 0x0496a099, 0x04401b57, ++ 0x04d08226, 0x04daac77, 0x04939d2b, 0x04919c7b, ++ 0x04901049, 0x0417a9f0, 0x04dea929, 0x048816ea, ++ 0x040a172d, 0x04811413, 0x04dca2d1, 0x65808a09, ++ 0x658d9411, 0x6586947d, 0x65878e21, 0x65c2880e, ++ 0x04ddb2d3, 0x65c2a5f1, 0x65c0b088, 0x65c1b3a5, ++ 0x65cda26b, 0x65c1938a, 0x65eb0ded, 0x65af3e86, ++ 0x65a749be, 0x65f379d6, 0x04404f3e, 0x04c16b0a, ++ 0x04363226, 0x04b1312a, 0x04753182, 0x049a39cf, ++ 0x04d82ce9, 0x0459353e, 0x04883347, 0x048a2fb4, ++ 0x65872e1c, 0x65c62d26, 0x6598346a, 0x04013915, - print - print "/*", + }; + // END Generated code -- do not edit diff --git a/src/hotspot/cpu/aarch64/assembler_aarch64.hpp b/src/hotspot/cpu/aarch64/assembler_aarch64.hpp -index 6f4e75ff4..dc2d5e2c9 100644 +index 8f0d7f5..13daa4e 100644 --- a/src/hotspot/cpu/aarch64/assembler_aarch64.hpp +++ b/src/hotspot/cpu/aarch64/assembler_aarch64.hpp -@@ -139,6 +139,9 @@ REGISTER_DECLARATION(Register, rdispatch, r21); +@@ -152,6 +152,9 @@ REGISTER_DECLARATION(Register, rdispatch, r21); // Java stack pointer REGISTER_DECLARATION(Register, esp, r20); @@ -5420,7 +5421,7 @@ index 6f4e75ff4..dc2d5e2c9 100644 #define assert_cond(ARG1) assert(ARG1, #ARG1) namespace asm_util { -@@ -562,6 +565,18 @@ class Address { +@@ -581,6 +584,18 @@ class Address { void lea(MacroAssembler *, Register) const; static bool offset_ok_for_immed(int64_t offset, uint shift = 0); @@ -5439,7 +5440,7 @@ index 6f4e75ff4..dc2d5e2c9 100644 }; // Convience classes -@@ -2445,13 +2460,18 @@ public: +@@ -2473,13 +2488,18 @@ public: f(sidx<<(int)T, 14, 11), f(1, 10), rf(Vn, 5), rf(Vd, 0); } @@ -5463,7 +5464,7 @@ index 6f4e75ff4..dc2d5e2c9 100644 #define INSN(NAME, opc, opc2, isSHR) \ void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, int shift){ \ starti; \ -@@ -2693,6 +2713,240 @@ void ext(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister V +@@ -2721,6 +2741,240 @@ void ext(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister V f(0, 10), rf(Vn, 5), rf(Vd, 0); } @@ -5704,7 +5705,7 @@ index 6f4e75ff4..dc2d5e2c9 100644 // SVE inc/dec register by element count #define INSN(NAME, op) \ void NAME(Register Xdn, SIMD_RegVariant T, unsigned imm4 = 1, int pattern = 0b11111) { \ -@@ -2706,6 +2960,45 @@ void ext(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister V +@@ -2734,6 +2988,45 @@ void ext(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister V INSN(sve_dec, 1); #undef INSN @@ -5751,7 +5752,7 @@ index 6f4e75ff4..dc2d5e2c9 100644 } diff --git a/src/hotspot/cpu/aarch64/gc/z/zBarrierSetAssembler_aarch64.cpp b/src/hotspot/cpu/aarch64/gc/z/zBarrierSetAssembler_aarch64.cpp -index 6ac54f257..a258528ea 100644 +index 6ac54f2..a258528 100644 --- a/src/hotspot/cpu/aarch64/gc/z/zBarrierSetAssembler_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/gc/z/zBarrierSetAssembler_aarch64.cpp @@ -456,8 +456,12 @@ void ZBarrierSetAssembler::generate_c2_load_barrier_stub(MacroAssembler* masm, Z @@ -5769,10 +5770,10 @@ index 6ac54f257..a258528ea 100644 __ b(*stub->continuation()); } diff --git a/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp b/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp -index 265cd0888..590fd8662 100644 +index c70d424..7cfa70a 100644 --- a/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp -@@ -2110,8 +2110,17 @@ int MacroAssembler::pop(unsigned int bitset, Register stack) { +@@ -2131,8 +2131,17 @@ int MacroAssembler::pop(unsigned int bitset, Register stack) { } // Push lots of registers in the bit set supplied. Don't push sp. @@ -5791,7 +5792,7 @@ index 265cd0888..590fd8662 100644 // Scan bitset to accumulate register pairs unsigned char regs[32]; int count = 0; -@@ -2126,8 +2135,18 @@ int MacroAssembler::push_fp(unsigned int bitset, Register stack) { +@@ -2147,8 +2156,18 @@ int MacroAssembler::push_fp(unsigned int bitset, Register stack) { return 0; } @@ -5810,7 +5811,7 @@ index 265cd0888..590fd8662 100644 if (count & 1) { strq(as_FloatRegister(regs[0]), Address(stack)); i += 1; -@@ -2140,7 +2159,16 @@ int MacroAssembler::push_fp(unsigned int bitset, Register stack) { +@@ -2161,7 +2180,16 @@ int MacroAssembler::push_fp(unsigned int bitset, Register stack) { return count; } @@ -5827,7 +5828,7 @@ index 265cd0888..590fd8662 100644 // Scan bitset to accumulate register pairs unsigned char regs[32]; int count = 0; -@@ -2155,6 +2183,16 @@ int MacroAssembler::pop_fp(unsigned int bitset, Register stack) { +@@ -2176,6 +2204,16 @@ int MacroAssembler::pop_fp(unsigned int bitset, Register stack) { return 0; } @@ -5844,7 +5845,7 @@ index 265cd0888..590fd8662 100644 if (count & 1) { ldrq(as_FloatRegister(regs[0]), Address(stack)); i += 1; -@@ -2638,23 +2676,39 @@ void MacroAssembler::pop_call_clobbered_registers() { +@@ -2659,23 +2697,39 @@ void MacroAssembler::pop_call_clobbered_registers() { pop(call_clobbered_registers() - RegSet::of(rscratch1, rscratch2), sp); } @@ -5894,10 +5895,10 @@ index 265cd0888..590fd8662 100644 + ld1(as_FloatRegister(i), as_FloatRegister(i+1), as_FloatRegister(i+2), + as_FloatRegister(i+3), restore_vectors ? T2D : T1D, Address(post(sp, step))); + } - + // integer registers except lr & sp pop(RegSet::range(r0, r17), sp); -@@ -2703,6 +2757,21 @@ Address MacroAssembler::spill_address(int size, int offset, Register tmp) +@@ -2732,6 +2786,21 @@ Address MacroAssembler::spill_address(int size, int offset, Register tmp) return Address(base, offset); } @@ -5919,7 +5920,7 @@ index 265cd0888..590fd8662 100644 // Checks whether offset is aligned. // Returns true if it is, else false. bool MacroAssembler::merge_alignment_check(Register base, -@@ -5901,3 +5970,13 @@ void MacroAssembler::verify_sve_vector_length() { +@@ -5930,3 +5999,13 @@ void MacroAssembler::verify_sve_vector_length() { stop("Error: SVE vector length has changed since jvm startup"); bind(verify_ok); } @@ -5934,42 +5935,42 @@ index 265cd0888..590fd8662 100644 + bind(verify_ok); +} diff --git a/src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp b/src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp -index 7fd9e3c97..bc3175b2b 100644 +index ec9b3cc..07e3169 100644 --- a/src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp +++ b/src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp @@ -862,8 +862,10 @@ public: - + DEBUG_ONLY(void verify_heapbase(const char* msg);) - + - void push_CPU_state(bool save_vectors = false); - void pop_CPU_state(bool restore_vectors = false) ; + void push_CPU_state(bool save_vectors = false, bool use_sve = false, + int sve_vector_size_in_bytes = 0); + void pop_CPU_state(bool restore_vectors = false, bool use_sve = false, + int sve_vector_size_in_bytes = 0); - + // Round up to a power of two void round_to(Register reg, int modulus); @@ -939,6 +941,10 @@ public: Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0); - + void verify_sve_vector_length(); + void reinitialize_ptrue() { + sve_ptrue(ptrue, B); + } + void verify_ptrue(); - + // Debugging - -@@ -1320,6 +1326,7 @@ private: + +@@ -1338,6 +1344,7 @@ private: // Returns an address on the stack which is reachable with a ldr/str of size // Uses rscratch2 if the address is not directly reachable Address spill_address(int size, int offset, Register tmp=rscratch2); + Address sve_spill_address(int sve_reg_size_in_bytes, int offset, Register tmp=rscratch2); - + bool merge_alignment_check(Register base, size_t size, int64_t cur_offset, int64_t prev_offset) const; - -@@ -1343,6 +1350,9 @@ public: + +@@ -1361,6 +1368,9 @@ public: void spill(FloatRegister Vx, SIMD_RegVariant T, int offset) { str(Vx, T, spill_address(1 << (int)T, offset)); } @@ -5979,7 +5980,7 @@ index 7fd9e3c97..bc3175b2b 100644 void unspill(Register Rx, bool is64, int offset) { if (is64) { ldr(Rx, spill_address(8, offset)); -@@ -1353,6 +1363,9 @@ public: +@@ -1371,6 +1381,9 @@ public: void unspill(FloatRegister Vx, SIMD_RegVariant T, int offset) { ldr(Vx, T, spill_address(1 << (int)T, offset)); } @@ -5989,7 +5990,7 @@ index 7fd9e3c97..bc3175b2b 100644 void spill_copy128(int src_offset, int dst_offset, Register tmp1=rscratch1, Register tmp2=rscratch2) { if (src_offset < 512 && (src_offset & 7) == 0 && -@@ -1366,6 +1379,15 @@ public: +@@ -1384,6 +1397,15 @@ public: spill(tmp1, true, dst_offset+8); } } @@ -6006,7 +6007,7 @@ index 7fd9e3c97..bc3175b2b 100644 #ifdef ASSERT diff --git a/src/hotspot/cpu/aarch64/register_definitions_aarch64.cpp b/src/hotspot/cpu/aarch64/register_definitions_aarch64.cpp -index 15131ed32..e337f582a 100644 +index 1602a78..e476456 100644 --- a/src/hotspot/cpu/aarch64/register_definitions_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/register_definitions_aarch64.cpp @@ -196,3 +196,5 @@ REGISTER_DEFINITION(PRegister, p4); @@ -6016,10 +6017,10 @@ index 15131ed32..e337f582a 100644 + +REGISTER_DEFINITION(PRegister, ptrue); diff --git a/src/hotspot/cpu/aarch64/sharedRuntime_aarch64.cpp b/src/hotspot/cpu/aarch64/sharedRuntime_aarch64.cpp -index 3bf7284a7..6242cce08 100644 +index 4b35aa6..491e29d 100644 --- a/src/hotspot/cpu/aarch64/sharedRuntime_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/sharedRuntime_aarch64.cpp -@@ -151,7 +151,7 @@ OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_ +@@ -152,7 +152,7 @@ OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_ // Save Integer and Float registers. __ enter(); @@ -6028,7 +6029,7 @@ index 3bf7284a7..6242cce08 100644 // Set an oopmap for the call site. This oopmap will map all // oop-registers and debug-info registers as callee-saved. This -@@ -190,10 +190,15 @@ OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_ +@@ -191,10 +191,15 @@ OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_ } void RegisterSaver::restore_live_registers(MacroAssembler* masm, bool restore_vectors) { @@ -6045,7 +6046,7 @@ index 3bf7284a7..6242cce08 100644 __ leave(); } -@@ -2786,6 +2791,12 @@ SafepointBlob* SharedRuntime::generate_handler_blob(address call_ptr, int poll_t +@@ -2810,6 +2815,12 @@ SafepointBlob* SharedRuntime::generate_handler_blob(address call_ptr, int poll_t __ maybe_isb(); __ membar(Assembler::LoadLoad | Assembler::LoadStore); @@ -6059,7 +6060,7 @@ index 3bf7284a7..6242cce08 100644 __ cbz(rscratch1, noException); diff --git a/src/hotspot/cpu/aarch64/stubGenerator_aarch64.cpp b/src/hotspot/cpu/aarch64/stubGenerator_aarch64.cpp -index 26a54c87e..85f64c007 100644 +index d307871..cd3f6f4 100644 --- a/src/hotspot/cpu/aarch64/stubGenerator_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/stubGenerator_aarch64.cpp @@ -488,6 +488,11 @@ class StubGenerator: public StubCodeGenerator { @@ -6074,7 +6075,7 @@ index 26a54c87e..85f64c007 100644 // we should not really care that lr is no longer the callee // address. we saved the value the handler needs in r19 so we can // just copy it to r3. however, the C2 handler will push its own -@@ -5092,6 +5097,12 @@ class StubGenerator: public StubCodeGenerator { +@@ -5421,6 +5426,12 @@ class StubGenerator: public StubCodeGenerator { __ reset_last_Java_frame(true); __ maybe_isb(); @@ -6088,7 +6089,7 @@ index 26a54c87e..85f64c007 100644 // check for pending exceptions diff --git a/src/hotspot/cpu/arm/arm.ad b/src/hotspot/cpu/arm/arm.ad -index 0ef4d7f3e..03248b2e0 100644 +index f142afa..98e6780 100644 --- a/src/hotspot/cpu/arm/arm.ad +++ b/src/hotspot/cpu/arm/arm.ad @@ -1093,7 +1093,7 @@ const bool Matcher::match_rule_supported(int opcode) { @@ -6101,7 +6102,7 @@ index 0ef4d7f3e..03248b2e0 100644 // TODO // identify extra cases that we might want to provide match rules for diff --git a/src/hotspot/cpu/ppc/ppc.ad b/src/hotspot/cpu/ppc/ppc.ad -index 7ee16a975..571a6aeb0 100644 +index b3bf64c..cc1e1a1 100644 --- a/src/hotspot/cpu/ppc/ppc.ad +++ b/src/hotspot/cpu/ppc/ppc.ad @@ -2242,7 +2242,7 @@ const bool Matcher::match_rule_supported(int opcode) { @@ -6114,7 +6115,7 @@ index 7ee16a975..571a6aeb0 100644 // TODO // identify extra cases that we might want to provide match rules for diff --git a/src/hotspot/cpu/s390/s390.ad b/src/hotspot/cpu/s390/s390.ad -index ea09aaafc..782c1c7c4 100644 +index ea09aaa..782c1c7 100644 --- a/src/hotspot/cpu/s390/s390.ad +++ b/src/hotspot/cpu/s390/s390.ad @@ -1522,7 +1522,7 @@ const bool Matcher::match_rule_supported(int opcode) { @@ -6127,7 +6128,7 @@ index ea09aaafc..782c1c7c4 100644 // Identify extra cases that we might want to provide match rules for // e.g. Op_ vector nodes and other intrinsics while guarding with vlen. diff --git a/src/hotspot/cpu/sparc/sparc.ad b/src/hotspot/cpu/sparc/sparc.ad -index a09c795c9..3b1b1046e 100644 +index a09c795..3b1b104 100644 --- a/src/hotspot/cpu/sparc/sparc.ad +++ b/src/hotspot/cpu/sparc/sparc.ad @@ -1710,7 +1710,7 @@ const bool Matcher::match_rule_supported(int opcode) { @@ -6140,10 +6141,10 @@ index a09c795c9..3b1b1046e 100644 // TODO // identify extra cases that we might want to provide match rules for diff --git a/src/hotspot/cpu/x86/x86.ad b/src/hotspot/cpu/x86/x86.ad -index 76dd6addd..93aee6d6c 100644 +index 4e1336f..b75d0ff 100644 --- a/src/hotspot/cpu/x86/x86.ad +++ b/src/hotspot/cpu/x86/x86.ad -@@ -1354,7 +1354,7 @@ const bool Matcher::match_rule_supported(int opcode) { +@@ -1379,7 +1379,7 @@ const bool Matcher::match_rule_supported(int opcode) { return ret_value; // Per default match rules are supported. } @@ -6153,7 +6154,7 @@ index 76dd6addd..93aee6d6c 100644 // e.g. Op_ vector nodes and other intrinsics while guarding with vlen bool ret_value = match_rule_supported(opcode); diff --git a/src/hotspot/share/opto/matcher.hpp b/src/hotspot/share/opto/matcher.hpp -index ed890f88e..9a8307102 100644 +index ed890f8..9a83071 100644 --- a/src/hotspot/share/opto/matcher.hpp +++ b/src/hotspot/share/opto/matcher.hpp @@ -310,7 +310,7 @@ public: @@ -6166,7 +6167,7 @@ index ed890f88e..9a8307102 100644 // Some microarchitectures have mask registers used on vectors static const bool has_predicated_vectors(void); diff --git a/src/hotspot/share/opto/superword.cpp b/src/hotspot/share/opto/superword.cpp -index 92f70b77d..ed67928f5 100644 +index fed52e4..ee58323 100644 --- a/src/hotspot/share/opto/superword.cpp +++ b/src/hotspot/share/opto/superword.cpp @@ -96,8 +96,11 @@ static const bool _do_vector_loop_experimental = false; // Experimental vectoriz @@ -6184,7 +6185,7 @@ index 92f70b77d..ed67928f5 100644 assert(lpt->_head->is_CountedLoop(), "must be"); CountedLoopNode *cl = lpt->_head->as_CountedLoop(); diff --git a/src/hotspot/share/opto/vectornode.cpp b/src/hotspot/share/opto/vectornode.cpp -index 1f2cf2c64..6867177c1 100644 +index 1f2cf2c..6867177 100644 --- a/src/hotspot/share/opto/vectornode.cpp +++ b/src/hotspot/share/opto/vectornode.cpp @@ -1,5 +1,5 @@ @@ -6212,6 +6213,3 @@ index 1f2cf2c64..6867177c1 100644 } return false; } --- -2.19.1 - diff --git a/8268427-Improve-AlgorithmConstraints-checkAlgorithm-.patch b/8268427-Improve-AlgorithmConstraints-checkAlgorithm-.patch deleted file mode 100755 index 776c4e75397edbd72d5c3dd0c3148f5a6f7d1a73..0000000000000000000000000000000000000000 --- a/8268427-Improve-AlgorithmConstraints-checkAlgorithm-.patch +++ /dev/null @@ -1,242 +0,0 @@ -From e3d9485d01941cfbbe01dc8dcea7b913c2e8469d Mon Sep 17 00:00:00 2001 -From: chenshanyao -Date: Tue, 14 Sep 2021 11:43:18 +0800 -Subject: [PATCH 8/8] 8268427: Improve AlgorithmConstraints:checkAlgorithm - performance - -Summary: : performance -LLT: jdk_security -Patch Type: backport -Bug url: https://bugs.openjdk.java.net/browse/JDK-8268427 ---- - .../util/AbstractAlgorithmConstraints.java | 39 +++++------ - .../util/DisabledAlgorithmConstraints.java | 28 ++++---- - .../util/LegacyAlgorithmConstraints.java | 2 +- - .../security/AlgorithmConstraintsPermits.java | 66 +++++++++++++++++++ - 4 files changed, 95 insertions(+), 40 deletions(-) - create mode 100644 test/micro/org/openjdk/bench/java/security/AlgorithmConstraintsPermits.java - -diff --git a/src/java.base/share/classes/sun/security/util/AbstractAlgorithmConstraints.java b/src/java.base/share/classes/sun/security/util/AbstractAlgorithmConstraints.java -index 8d8c5d6fe..3f5678950 100644 ---- a/src/java.base/share/classes/sun/security/util/AbstractAlgorithmConstraints.java -+++ b/src/java.base/share/classes/sun/security/util/AbstractAlgorithmConstraints.java -@@ -32,6 +32,7 @@ import java.security.Security; - import java.util.ArrayList; - import java.util.Arrays; - import java.util.Collections; -+import java.util.TreeSet; - import java.util.List; - import java.util.Set; - -@@ -48,7 +49,7 @@ public abstract class AbstractAlgorithmConstraints - } - - // Get algorithm constraints from the specified security property. -- static List getAlgorithms(String propertyName) { -+ static Set getAlgorithms(String propertyName) { - String property = AccessController.doPrivileged( - new PrivilegedAction() { - @Override -@@ -72,38 +73,30 @@ public abstract class AbstractAlgorithmConstraints - - // map the disabled algorithms - if (algorithmsInProperty == null) { -- return Collections.emptyList(); -+ return Collections.emptySet(); - } -- return new ArrayList<>(Arrays.asList(algorithmsInProperty)); -+ Set algorithmsInPropertySet = new TreeSet<>(String.CASE_INSENSITIVE_ORDER); -+ algorithmsInPropertySet.addAll(Arrays.asList(algorithmsInProperty)); -+ return algorithmsInPropertySet; - } - -- static boolean checkAlgorithm(List algorithms, String algorithm, -+ static boolean checkAlgorithm(Set algorithms, String algorithm, - AlgorithmDecomposer decomposer) { - if (algorithm == null || algorithm.isEmpty()) { - throw new IllegalArgumentException("No algorithm name specified"); - } - -- Set elements = null; -- for (String item : algorithms) { -- if (item == null || item.isEmpty()) { -- continue; -- } -- -- // check the full name -- if (item.equalsIgnoreCase(algorithm)) { -- return false; -- } -+ if (algorithms.contains(algorithm)) { -+ return false; -+ } - -- // decompose the algorithm into sub-elements -- if (elements == null) { -- elements = decomposer.decompose(algorithm); -- } -+ // decompose the algorithm into sub-elements -+ Set elements = decomposer.decompose(algorithm); - -- // check the items of the algorithm -- for (String element : elements) { -- if (item.equalsIgnoreCase(element)) { -- return false; -- } -+ // check the element of the elements -+ for (String element : elements) { -+ if (algorithms.contains(element)) { -+ return false; - } - } - -diff --git a/src/java.base/share/classes/sun/security/util/DisabledAlgorithmConstraints.java b/src/java.base/share/classes/sun/security/util/DisabledAlgorithmConstraints.java -index 3ee431e62..efc6d339f 100644 ---- a/src/java.base/share/classes/sun/security/util/DisabledAlgorithmConstraints.java -+++ b/src/java.base/share/classes/sun/security/util/DisabledAlgorithmConstraints.java -@@ -85,6 +85,9 @@ public class DisabledAlgorithmConstraints extends AbstractAlgorithmConstraints { - private static final String PROPERTY_DISABLED_EC_CURVES = - "jdk.disabled.namedCurves"; - -+ private static final Pattern INCLUDE_PATTERN = Pattern.compile("include " + -+ PROPERTY_DISABLED_EC_CURVES, Pattern.CASE_INSENSITIVE); -+ - private static class CertPathHolder { - static final DisabledAlgorithmConstraints CONSTRAINTS = - new DisabledAlgorithmConstraints(PROPERTY_CERTPATH_DISABLED_ALGS); -@@ -95,7 +98,7 @@ public class DisabledAlgorithmConstraints extends AbstractAlgorithmConstraints { - new DisabledAlgorithmConstraints(PROPERTY_JAR_DISABLED_ALGS); - } - -- private final List disabledAlgorithms; -+ private final Set disabledAlgorithms; - private final Constraints algorithmConstraints; - - public static DisabledAlgorithmConstraints certPathConstraints() { -@@ -130,21 +133,14 @@ public class DisabledAlgorithmConstraints extends AbstractAlgorithmConstraints { - disabledAlgorithms = getAlgorithms(propertyName); - - // Check for alias -- int ecindex = -1, i = 0; - for (String s : disabledAlgorithms) { -- if (s.regionMatches(true, 0,"include ", 0, 8)) { -- if (s.regionMatches(true, 8, PROPERTY_DISABLED_EC_CURVES, 0, -- PROPERTY_DISABLED_EC_CURVES.length())) { -- ecindex = i; -- break; -- } -+ Matcher matcher = INCLUDE_PATTERN.matcher(s); -+ if (matcher.matches()) { -+ disabledAlgorithms.remove(matcher.group()); -+ disabledAlgorithms.addAll( -+ getAlgorithms(PROPERTY_DISABLED_EC_CURVES)); -+ break; - } -- i++; -- } -- if (ecindex > -1) { -- disabledAlgorithms.remove(ecindex); -- disabledAlgorithms.addAll(ecindex, -- getAlgorithms(PROPERTY_DISABLED_EC_CURVES)); - } - algorithmConstraints = new Constraints(propertyName, disabledAlgorithms); - } -@@ -323,8 +319,8 @@ public class DisabledAlgorithmConstraints extends AbstractAlgorithmConstraints { - "denyAfter\\s+(\\d{4})-(\\d{2})-(\\d{2})"); - } - -- public Constraints(String propertyName, List constraintArray) { -- for (String constraintEntry : constraintArray) { -+ public Constraints(String propertyName, Set constraintSet) { -+ for (String constraintEntry : constraintSet) { - if (constraintEntry == null || constraintEntry.isEmpty()) { - continue; - } -diff --git a/src/java.base/share/classes/sun/security/util/LegacyAlgorithmConstraints.java b/src/java.base/share/classes/sun/security/util/LegacyAlgorithmConstraints.java -index e4e5cedc1..550173080 100644 ---- a/src/java.base/share/classes/sun/security/util/LegacyAlgorithmConstraints.java -+++ b/src/java.base/share/classes/sun/security/util/LegacyAlgorithmConstraints.java -@@ -40,7 +40,7 @@ public class LegacyAlgorithmConstraints extends AbstractAlgorithmConstraints { - public static final String PROPERTY_TLS_LEGACY_ALGS = - "jdk.tls.legacyAlgorithms"; - -- private final List legacyAlgorithms; -+ private final Set legacyAlgorithms; - - public LegacyAlgorithmConstraints(String propertyName, - AlgorithmDecomposer decomposer) { -diff --git a/test/micro/org/openjdk/bench/java/security/AlgorithmConstraintsPermits.java b/test/micro/org/openjdk/bench/java/security/AlgorithmConstraintsPermits.java -new file mode 100644 -index 000000000..3cb9567b9 ---- /dev/null -+++ b/test/micro/org/openjdk/bench/java/security/AlgorithmConstraintsPermits.java -@@ -0,0 +1,66 @@ -+/* -+ * Copyright (c) 2021, Huawei Technologies Co., Ltd. All rights reserved. -+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+ * -+ * This code is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 only, as -+ * published by the Free Software Foundation. -+ * -+ * This code is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * version 2 for more details (a copy is included in the LICENSE file that -+ * accompanied this code). -+ * -+ * You should have received a copy of the GNU General Public License version -+ * 2 along with this work; if not, write to the Free Software Foundation, -+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+ * or visit www.oracle.com if you need additional information or have any -+ * questions. -+ */ -+package org.openjdk.bench.java.security; -+ -+import org.openjdk.jmh.annotations.Benchmark; -+import org.openjdk.jmh.annotations.BenchmarkMode; -+import org.openjdk.jmh.annotations.Fork; -+import org.openjdk.jmh.annotations.Mode; -+import org.openjdk.jmh.annotations.OutputTimeUnit; -+import org.openjdk.jmh.annotations.Param; -+import org.openjdk.jmh.annotations.Scope; -+import org.openjdk.jmh.annotations.Setup; -+import org.openjdk.jmh.annotations.State; -+import sun.security.util.DisabledAlgorithmConstraints; -+ -+import java.security.AlgorithmConstraints; -+import java.security.CryptoPrimitive; -+import java.util.concurrent.TimeUnit; -+import java.util.EnumSet; -+import java.util.Set; -+ -+import static sun.security.util.DisabledAlgorithmConstraints.PROPERTY_TLS_DISABLED_ALGS; -+ -+@BenchmarkMode(Mode.AverageTime) -+@OutputTimeUnit(TimeUnit.NANOSECONDS) -+@Fork(jvmArgsAppend = {"--add-exports", "java.base/sun.security.util=ALL-UNNAMED"}) -+@State(Scope.Thread) -+public class AlgorithmConstraintsPermits { -+ -+ AlgorithmConstraints tlsDisabledAlgConstraints; -+ Set primitives = EnumSet.of(CryptoPrimitive.KEY_AGREEMENT); -+ -+ @Param({"SSLv3", "DES", "NULL", "TLS1.3"}) -+ String algorithm; -+ -+ @Setup -+ public void setup() { -+ tlsDisabledAlgConstraints = new DisabledAlgorithmConstraints(PROPERTY_TLS_DISABLED_ALGS); -+ } -+ -+ @Benchmark -+ public boolean permits() { -+ return tlsDisabledAlgConstraints.permits(primitives, algorithm, null); -+ } -+} -+ --- -2.22.0 - diff --git a/G1-iterate-region-by-bitmap-rather-than-obj-size-in.patch b/G1-iterate-region-by-bitmap-rather-than-obj-size-in.patch index de07fd8e73579473af4c7060520a47bf3cb405e9..d97aa7f01b7c2cb9795c20cd4ad88b0e0bc557e3 100755 --- a/G1-iterate-region-by-bitmap-rather-than-obj-size-in.patch +++ b/G1-iterate-region-by-bitmap-rather-than-obj-size-in.patch @@ -367,4 +367,4 @@ index 000000000..85b49171c --- /dev/null +++ b/version.txt @@ -0,0 +1 @@ -+11.0.19.0.13 ++11.0.20.0.13 diff --git a/delete_expired_certificates.patch b/delete_expired_certificates.patch index 340c9a19032ab3ed94cb301f4c449734d2aff333..94b5636c0652e6a4b47cea939186158da5783e9e 100644 --- a/delete_expired_certificates.patch +++ b/delete_expired_certificates.patch @@ -120,14 +120,14 @@ index 122a01901..c131bd493 100644 + File.separator + "security" + File.separator + "cacerts"; // The numbers of certs now. -- private static final int COUNT = 90; -+ private static final int COUNT = 87; +- private static final int COUNT = 97; ++ private static final int COUNT = 94; // SHA-256 of cacerts, can be generated with // shasum -a 256 cacerts | sed -e 's/../&:/g' | tr '[:lower:]' '[:upper:]' | cut -c1-95 private static final String CHECKSUM -- = "21:8C:35:29:4C:E2:49:D2:83:30:DF:8B:5E:39:F8:8C:D6:C5:2B:59:05:32:74:E5:79:A5:91:9F:3C:57:B9:E3"; -+ = "D5:5B:7A:BD:8F:4A:DA:19:75:90:28:61:E7:40:6D:A2:54:F5:64:C0:F0:30:29:16:FB:46:9B:57:D5:F7:04:D7"; +- = "72:C7:B8:9E:54:94:D2:D9:C0:E5:9F:F7:C3:8C:3B:18:D7:42:23:82:51:F2:AD:A1:14:26:E0:4A:F2:5F:AE:80"; ++ = "38:20:3E:9C:85:F4:5C:F2:4A:F4:1C:FF:DA:AD:DF:A6:1E:B0:E9:8F:D4:C3:B5:AA:F5:54:E2:94:3E:AF:2F:7C"; // map of cert alias to SHA-256 fingerprint @SuppressWarnings("serial") diff --git a/fix_X509TrustManagerImpl_symantec_distrust.patch b/fix_X509TrustManagerImpl_symantec_distrust.patch deleted file mode 100644 index 570e0666d66509e55e529bd7fe86ea0ef06311c3..0000000000000000000000000000000000000000 --- a/fix_X509TrustManagerImpl_symantec_distrust.patch +++ /dev/null @@ -1,72 +0,0 @@ -diff --git a/make/data/cacerts/geotrustglobalca b/make/data/cacerts/geotrustglobalca -new file mode 100644 -index 000000000..7f8bf9a66 ---- /dev/null -+++ b/make/data/cacerts/geotrustglobalca -@@ -0,0 +1,27 @@ -+Owner: CN=GeoTrust Global CA, O=GeoTrust Inc., C=US -+Issuer: CN=GeoTrust Global CA, O=GeoTrust Inc., C=US -+Serial number: 23456 -+Valid from: Tue May 21 04:00:00 GMT 2002 until: Sat May 21 04:00:00 GMT 2022 -+Signature algorithm name: SHA1withRSA -+Subject Public Key Algorithm: 2048-bit RSA key -+Version: 3 -+-----BEGIN CERTIFICATE----- -+MIIDVDCCAjygAwIBAgIDAjRWMA0GCSqGSIb3DQEBBQUAMEIxCzAJBgNVBAYTAlVT -+MRYwFAYDVQQKEw1HZW9UcnVzdCBJbmMuMRswGQYDVQQDExJHZW9UcnVzdCBHbG9i -+YWwgQ0EwHhcNMDIwNTIxMDQwMDAwWhcNMjIwNTIxMDQwMDAwWjBCMQswCQYDVQQG -+EwJVUzEWMBQGA1UEChMNR2VvVHJ1c3QgSW5jLjEbMBkGA1UEAxMSR2VvVHJ1c3Qg -+R2xvYmFsIENBMIIBIjANBgkqhkiG9w0BAQEFAAOCAQ8AMIIBCgKCAQEA2swYYzD9 -+9BcjGlZ+W988bDjkcbd4kdS8odhM+KhDtgPpTSEHCIjaWC9mOSm9BXiLnTjoBbdq -+fnGk5sRgprDvgOSJKA+eJdbtg/OtppHHmMlCGDUUna2YRpIuT8rxh0PBFpVXLVDv -+iS2Aelet8u5fa9IAjbkU+BQVNdnARqN7csiRv8lVK83Qlz6cJmTM386DGXHKTubU -+1XupGc1V3sjs0l44U+VcT4wt/lAjNvxm5suOpDkZALeVAjmRCw7+OC7RHQWa9k0+ -+bw8HHa8sHo9gOeL6NlMTOdReJivbPagUvTLrGAMoUgRx5aszPeE4uwc2hGKceeoW -+MPRfwCvocWvk+QIDAQABo1MwUTAPBgNVHRMBAf8EBTADAQH/MB0GA1UdDgQWBBTA -+ephojYn7qwVkDBF9qn1luMrMTjAfBgNVHSMEGDAWgBTAephojYn7qwVkDBF9qn1l -+uMrMTjANBgkqhkiG9w0BAQUFAAOCAQEANeMpauUvXVSOKVCUn5kaFOSPeCpilKIn -+Z57QzxpeR+nBsqTP3UEaBU6bS+5Kb1VSsyShNwrrZHYqLizz/Tt1kL/6cdjHPTfS -+tQWVYrmm3ok9Nns4d0iXrKYgjy6myQzCsplFAMfOEVEiIuCl6rYVSAlk6l5PdPcF -+PseKUgzbFbS9bZvlxrFUaKnjaZC2mqUPuLk/IH2uSrW4nOQdtqvmlKXBx4Ot2/Un -+hw4EbNX/3aBd7YdStysVAq45pmp06drE57xNNB6pXE0zX5IJL4hmXXeXxx12E6nV -+5fEWCRE11azbJHFwLJhWC9kXtNHjUStedejV0NxPNO3CBWaAocvmMw== -+-----END CERTIFICATE----- -diff --git a/test/jdk/sun/security/lib/cacerts/VerifyCACerts.java b/test/jdk/sun/security/lib/cacerts/VerifyCACerts.java -index c131bd493..478cc7235 100644 ---- a/test/jdk/sun/security/lib/cacerts/VerifyCACerts.java -+++ b/test/jdk/sun/security/lib/cacerts/VerifyCACerts.java -@@ -53,12 +53,12 @@ public class VerifyCACerts { - + File.separator + "security" + File.separator + "cacerts"; - - // The numbers of certs now. -- private static final int COUNT = 86; -+ private static final int COUNT = 87; - - // SHA-256 of cacerts, can be generated with - // shasum -a 256 cacerts | sed -e 's/../&:/g' | tr '[:lower:]' '[:upper:]' | cut -c1-95 - private static final String CHECKSUM -- = "89:78:5A:96:F4:B2:68:4C:91:C0:32:2C:ED:2D:6B:3B:26:B8:37:C3:07:DD:9E:50:87:53:53:7A:24:98:97:E0"; -+ = "63:C4:11:7D:BF:C5:05:2B:BF:C2:B4:5A:2C:B6:26:C4:57:76:FB:D4:48:3B:E7:4C:62:B0:A1:7B:4F:07:B1:0C"; - - // map of cert alias to SHA-256 fingerprint - @SuppressWarnings("serial") -@@ -116,7 +116,9 @@ public class VerifyCACerts { - "7E:37:CB:8B:4C:47:09:0C:AB:36:55:1B:A6:F4:5D:B8:40:68:0F:BA:16:6A:95:2D:B1:00:71:7F:43:05:3F:C2"); - put("digicerthighassuranceevrootca [jdk]", - "74:31:E5:F4:C3:C1:CE:46:90:77:4F:0B:61:E0:54:40:88:3B:A9:A0:1E:D0:0B:A6:AB:D7:80:6E:D3:B1:18:CF"); -- put("geotrustprimaryca [jdk]", -+ put("geotrustglobalca [jdk]", -+ "FF:85:6A:2D:25:1D:CD:88:D3:66:56:F4:50:12:67:98:CF:AB:AA:DE:40:79:9C:72:2D:E4:D2:B5:DB:36:A7:3A"); -+ put("geotrustprimaryca [jdk]", - "37:D5:10:06:C5:12:EA:AB:62:64:21:F1:EC:8C:92:01:3F:C5:F8:2A:E9:8E:E5:33:EB:46:19:B8:DE:B4:D0:6C"); - put("geotrustprimarycag2 [jdk]", - "5E:DB:7A:C4:3B:82:A0:6A:87:61:E8:D7:BE:49:79:EB:F2:61:1F:7D:D7:9B:F9:1C:1C:6B:56:6A:21:9E:D7:66"); -@@ -250,6 +252,8 @@ public class VerifyCACerts { - add("addtrustexternalca [jdk]"); - // Valid until: Sat May 30 10:44:50 GMT 2020 - add("addtrustqualifiedca [jdk]"); -+ // Valid until: Sat May 21 04:00:00 GMT 2022 -+ add("geotrustglobalca [jdk]"); - } - }; - diff --git a/jdk-updates-jdk11u-jdk-11.0.19-ga.tar.gz b/jdk-updates-jdk11u-jdk-11.0.20-ga.tar.xz similarity index 57% rename from jdk-updates-jdk11u-jdk-11.0.19-ga.tar.gz rename to jdk-updates-jdk11u-jdk-11.0.20-ga.tar.xz index 360f3a82edd09a7f20ac98f878f2b1bdd6566009..4b97083fbe022c78ce8c568be1183451cb77a233 100644 Binary files a/jdk-updates-jdk11u-jdk-11.0.19-ga.tar.gz and b/jdk-updates-jdk11u-jdk-11.0.20-ga.tar.xz differ diff --git a/openjdk-11.spec b/openjdk-11.spec index d9e896d93f73b32179c0ac8c575d8843f794c1e3..50bc7bbc12ba89148a09d488949c5dedc57c0b54 100644 --- a/openjdk-11.spec +++ b/openjdk-11.spec @@ -114,7 +114,7 @@ # New Version-String scheme-style defines %global majorver 11 -%global securityver 19 +%global securityver 20 # buildjdkver is usually same as %%{majorver}, # but in time of bootstrap of next jdk, it is majorver-1, # and this it is better to change it here, on single place @@ -130,12 +130,12 @@ %global origin_nice OpenJDK %global top_level_dir_name %{origin} %global minorver 0 -%global buildver 7 +%global buildver 8 %global patchver 0 %global project jdk-updates %global repo jdk11u -%global revision jdk-11.0.19-ga +%global revision jdk-11.0.20-ga %global full_revision %{project}-%{repo}-%{revision} # priority must be 7 digits in total # setting to 1, so debug ones can have 0 @@ -740,7 +740,7 @@ Provides: java-src%{?1} = %{epoch}:%{version}-%{release} Name: java-%{javaver}-%{origin} Version: %{newjavaver}.%{buildver} -Release: 0 +Release: 1 # java-1.5.0-ibm from jpackage.org set Epoch to 1 for unknown reasons # and this change was brought into RHEL-4. java-1.5.0-ibm packages # also included the epoch in their virtual provides. This created a @@ -773,7 +773,7 @@ License: ASL 1.1 and ASL 2.0 and BSD and BSD with advertising and GPL+ and GPLv URL: http://openjdk.java.net/ -Source0: %{full_revision}.tar.gz +Source0: %{full_revision}.tar.xz # Use 'icedtea_sync.sh' to update the following # They are based on code contained in the IcedTea project (3.x). @@ -845,7 +845,7 @@ Patch61: downgrade-the-symver-of-log2f-posix-spawn.patch Patch62: 8254078-DataOutputStream-is-very-slow-post-disabling.patch Patch65: add-LazyBox-feature.patch Patch66: add-G1-Full-GC-optimization.patch -Patch68: src-openeuler-openjdk-11-resolve-code-inconsistencies.patch +Patch68: src-openeuler-openjdk-11-resolve-code-inconsistencies.patch Patch69: G1-iterate-region-by-bitmap-rather-than-obj-size-in.patch # 11.0.11 @@ -875,7 +875,7 @@ Patch89: downgrade-the-symver-of-memcpy-GLIBC_2.14-on-x86.patch # 11.0.16 Patch90: fix_Internal_and_external_code_inconsistency.patch -# 11.0.18 +# 11.0.18 Patch91: 8222289-Overhaul-logic-for-reading-writing-constant-pool-entries.patch BuildRequires: elfutils-extra @@ -1328,7 +1328,7 @@ export JAVA_HOME=$(pwd)/%{buildoutputdir -- $suffix}/images/%{jdkimage} # Check debug symbols are present and can identify code find "$JAVA_HOME" -iname '*.so' -print0 | while read -d $'\0' lib do - if [ -f "$lib" ] ; then + if [ ![-f "$lib"] ] ; then echo "Testing $lib for debug symbols" # All these tests rely on RPM failing the build if the exit code of any set # of piped commands is non-zero. @@ -1371,7 +1371,7 @@ done # Make sure gdb can do a backtrace based on line numbers on libjvm.so # javaCalls.cpp:58 should map to: -# http://hg.openjdk.java.net/jdk8u/jdk8u/hotspot/file/ff3b27e6bcc2/src/share/vm/runtime/javaCalls.cpp#l58 +# http://hg.openjdk.java.net/jdk8u/jdk8u/hotspot/file/ff3b27e6bcc2/src/share/vm/runtime/javaCalls.cpp#l58 # Using line number 1 might cause build problems. See: gdb -q "$JAVA_HOME/bin/java" < - 1:11.0.19.7-0 +* Wed Aug 2023 noah - 1:11.0.20.8-1 +- fix CPUBench kmeans random fails + +* Wed Jul 2023 DXwangg - 1:11.0.20.8-0 +- update to 11.0.20+8(GA) +- modified delete_expired_certificates.patch + + +* Thu Apr 2023 DXwangg - 1:11.0.19.7-0 - update to 11.0.19+7(GA) - deleted 8225648-TESTBUG-java-lang-annotation-loaderLeak-Main.patch - modified Add-KAE-implementation.patch - modified G1-iterate-region-by-bitmap-rather-than-obj-size-in.patch - modified delete_expired_certificates.patch - modified 8205921-Optimizing-best_of_2-work-stealing-queue-selection.patch + +* Thu Jan 5 2023 Henry_Yang - 1:11.0.18.10-1 - add 8222289-Overhaul-logic-for-reading-writing-constant-pool-entries.patch -- modified 8224675-Late-GC-barrier-insertion-for-ZGC.patch + +* Thu Jan 5 2023 DXwangg - 1:11.0.18.10-0 +- update to 11.0.18+10(GA) - modified 8231441-2-AArch64-Initial-SVE-backend-support.patch -- deleted 8290705_fix_StringConcat_validate_mem_flow_asserts_with_unexpected_userStoreI.patch +- delete 8290705_fix_StringConcat_validate_mem_flow_asserts_with_unexpected_userStoreI.patch * Wed Oct 19 2022 DXwangg - 1:11.0.17.8-0 - update to 11.0.17+8(GA) @@ -1862,7 +1874,7 @@ cjc.mainProgram(arg) - add 8248336-AArch64-C2-offset-overflow-in-BoxLockNode-em.patch * Mon Oct 26 2020 noah - 1:11.0.9.11-1 -- add 8229495-SIGILL-in-C2-generated-OSR-compilation.patch +- add 8229495-SIGILL-in-C2-generated-OSR-compilation.patch * Thu Oct 22 2020 noah - 1:11.0.9.11-0 - Update to 11.0.9+11 (GA)